1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 */ 34 35 /* 36 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 37 * series chips and several workalikes including the following: 38 * 39 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 40 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 41 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 42 * ASIX Electronics AX88140A (www.asix.com.tw) 43 * ASIX Electronics AX88141 (www.asix.com.tw) 44 * ADMtek AL981 (www.admtek.com.tw) 45 * ADMtek AN985 (www.admtek.com.tw) 46 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 47 * Accton EN1217 (www.accton.com) 48 * Xircom X3201 (www.xircom.com) 49 * Abocom FE2500 50 * Conexant LANfinity (www.conexant.com) 51 * 52 * Datasheets for the 21143 are available at developer.intel.com. 53 * Datasheets for the clone parts can be found at their respective sites. 54 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 55 * The PNIC II is essentially a Macronix 98715A chip; the only difference 56 * worth noting is that its multicast hash table is only 128 bits wide 57 * instead of 512. 58 * 59 * Written by Bill Paul <wpaul@ee.columbia.edu> 60 * Electrical Engineering Department 61 * Columbia University, New York City 62 */ 63 64 /* 65 * The Intel 21143 is the successor to the DEC 21140. It is basically 66 * the same as the 21140 but with a few new features. The 21143 supports 67 * three kinds of media attachments: 68 * 69 * o MII port, for 10Mbps and 100Mbps support and NWAY 70 * autonegotiation provided by an external PHY. 71 * o SYM port, for symbol mode 100Mbps support. 72 * o 10baseT port. 73 * o AUI/BNC port. 74 * 75 * The 100Mbps SYM port and 10baseT port can be used together in 76 * combination with the internal NWAY support to create a 10/100 77 * autosensing configuration. 78 * 79 * Note that not all tulip workalikes are handled in this driver: we only 80 * deal with those which are relatively well behaved. The Winbond is 81 * handled separately due to its different register offsets and the 82 * special handling needed for its various bugs. The PNIC is handled 83 * here, but I'm not thrilled about it. 84 * 85 * All of the workalike chips use some form of MII transceiver support 86 * with the exception of the Macronix chips, which also have a SYM port. 87 * The ASIX AX88140A is also documented to have a SYM port, but all 88 * the cards I've seen use an MII transceiver, probably because the 89 * AX88140A doesn't support internal NWAY. 90 */ 91 92 #include <sys/param.h> 93 #include <sys/systm.h> 94 #include <sys/sockio.h> 95 #include <sys/mbuf.h> 96 #include <sys/malloc.h> 97 #include <sys/kernel.h> 98 #include <sys/socket.h> 99 #include <sys/sysctl.h> 100 101 #include <net/if.h> 102 #include <net/if_arp.h> 103 #include <net/ethernet.h> 104 #include <net/if_dl.h> 105 #include <net/if_media.h> 106 #include <net/if_types.h> 107 #include <net/if_vlan_var.h> 108 109 #include <net/bpf.h> 110 111 #include <vm/vm.h> /* for vtophys */ 112 #include <vm/pmap.h> /* for vtophys */ 113 #include <machine/bus_pio.h> 114 #include <machine/bus_memio.h> 115 #include <machine/bus.h> 116 #include <machine/resource.h> 117 #include <sys/bus.h> 118 #include <sys/rman.h> 119 120 #include <dev/mii/mii.h> 121 #include <dev/mii/miivar.h> 122 123 #include <pci/pcireg.h> 124 #include <pci/pcivar.h> 125 126 #define DC_USEIOSPACE 127 #ifdef __alpha__ 128 #define SRM_MEDIA 129 #endif 130 131 #include <pci/if_dcreg.h> 132 133 MODULE_DEPEND(dc, miibus, 1, 1, 1); 134 135 /* "controller miibus0" required. See GENERIC if you get errors here. */ 136 #include "miibus_if.h" 137 138 #ifndef lint 139 static const char rcsid[] = 140 "$FreeBSD$"; 141 #endif 142 143 /* 144 * Various supported device vendors/types and their names. 145 */ 146 static struct dc_type dc_devs[] = { 147 { DC_VENDORID_DEC, DC_DEVICEID_21143, 148 "Intel 21143 10/100BaseTX" }, 149 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 150 "Davicom DM9100 10/100BaseTX" }, 151 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 152 "Davicom DM9102 10/100BaseTX" }, 153 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 154 "Davicom DM9102A 10/100BaseTX" }, 155 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 156 "ADMtek AL981 10/100BaseTX" }, 157 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 158 "ADMtek AN985 10/100BaseTX" }, 159 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 160 "ASIX AX88140A 10/100BaseTX" }, 161 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 162 "ASIX AX88141 10/100BaseTX" }, 163 { DC_VENDORID_MX, DC_DEVICEID_98713, 164 "Macronix 98713 10/100BaseTX" }, 165 { DC_VENDORID_MX, DC_DEVICEID_98713, 166 "Macronix 98713A 10/100BaseTX" }, 167 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 168 "Compex RL100-TX 10/100BaseTX" }, 169 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 170 "Compex RL100-TX 10/100BaseTX" }, 171 { DC_VENDORID_MX, DC_DEVICEID_987x5, 172 "Macronix 98715/98715A 10/100BaseTX" }, 173 { DC_VENDORID_MX, DC_DEVICEID_987x5, 174 "Macronix 98715AEC-C 10/100BaseTX" }, 175 { DC_VENDORID_MX, DC_DEVICEID_987x5, 176 "Macronix 98725 10/100BaseTX" }, 177 { DC_VENDORID_MX, DC_DEVICEID_98727, 178 "Macronix 98727/98732 10/100BaseTX" }, 179 { DC_VENDORID_LO, DC_DEVICEID_82C115, 180 "LC82C115 PNIC II 10/100BaseTX" }, 181 { DC_VENDORID_LO, DC_DEVICEID_82C168, 182 "82c168 PNIC 10/100BaseTX" }, 183 { DC_VENDORID_LO, DC_DEVICEID_82C168, 184 "82c169 PNIC 10/100BaseTX" }, 185 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217, 186 "Accton EN1217 10/100BaseTX" }, 187 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242, 188 "Accton EN2242 MiniPCI 10/100BaseTX" }, 189 { DC_VENDORID_XIRCOM, DC_DEVICEID_X3201, 190 "Xircom X3201 10/100BaseTX" }, 191 { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500, 192 "Abocom FE2500 10/100BaseTX" }, 193 { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112, 194 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 195 { 0, 0, NULL } 196 }; 197 198 static int dc_probe (device_t); 199 static int dc_attach (device_t); 200 static int dc_detach (device_t); 201 static int dc_suspend (device_t); 202 static int dc_resume (device_t); 203 static void dc_acpi (device_t); 204 static struct dc_type *dc_devtype (device_t); 205 static int dc_newbuf (struct dc_softc *, int, struct mbuf *); 206 static int dc_encap (struct dc_softc *, struct mbuf *, u_int32_t *); 207 static int dc_coal (struct dc_softc *, struct mbuf **); 208 static void dc_pnic_rx_bug_war (struct dc_softc *, int); 209 static int dc_rx_resync (struct dc_softc *); 210 static void dc_rxeof (struct dc_softc *); 211 static void dc_txeof (struct dc_softc *); 212 static void dc_tick (void *); 213 static void dc_tx_underrun (struct dc_softc *); 214 static void dc_intr (void *); 215 static void dc_start (struct ifnet *); 216 static int dc_ioctl (struct ifnet *, u_long, caddr_t); 217 static void dc_init (void *); 218 static void dc_stop (struct dc_softc *); 219 static void dc_watchdog (struct ifnet *); 220 static void dc_shutdown (device_t); 221 static int dc_ifmedia_upd (struct ifnet *); 222 static void dc_ifmedia_sts (struct ifnet *, struct ifmediareq *); 223 224 static void dc_delay (struct dc_softc *); 225 static void dc_eeprom_idle (struct dc_softc *); 226 static void dc_eeprom_putbyte (struct dc_softc *, int); 227 static void dc_eeprom_getword (struct dc_softc *, int, u_int16_t *); 228 static void dc_eeprom_getword_pnic 229 (struct dc_softc *, int, u_int16_t *); 230 static void dc_eeprom_getword_xircom 231 (struct dc_softc *, int, u_int16_t *); 232 static void dc_read_eeprom (struct dc_softc *, caddr_t, int, int, int); 233 234 static void dc_mii_writebit (struct dc_softc *, int); 235 static int dc_mii_readbit (struct dc_softc *); 236 static void dc_mii_sync (struct dc_softc *); 237 static void dc_mii_send (struct dc_softc *, u_int32_t, int); 238 static int dc_mii_readreg (struct dc_softc *, struct dc_mii_frame *); 239 static int dc_mii_writereg (struct dc_softc *, struct dc_mii_frame *); 240 static int dc_miibus_readreg (device_t, int, int); 241 static int dc_miibus_writereg (device_t, int, int, int); 242 static void dc_miibus_statchg (device_t); 243 static void dc_miibus_mediainit (device_t); 244 245 static void dc_setcfg (struct dc_softc *, int); 246 static u_int32_t dc_crc_le (struct dc_softc *, caddr_t); 247 static u_int32_t dc_crc_be (caddr_t); 248 static void dc_setfilt_21143 (struct dc_softc *); 249 static void dc_setfilt_asix (struct dc_softc *); 250 static void dc_setfilt_admtek (struct dc_softc *); 251 static void dc_setfilt_xircom (struct dc_softc *); 252 253 static void dc_setfilt (struct dc_softc *); 254 255 static void dc_reset (struct dc_softc *); 256 static int dc_list_rx_init (struct dc_softc *); 257 static int dc_list_tx_init (struct dc_softc *); 258 259 static void dc_parse_21143_srom (struct dc_softc *); 260 static void dc_decode_leaf_sia (struct dc_softc *, struct dc_eblock_sia *); 261 static void dc_decode_leaf_mii (struct dc_softc *, struct dc_eblock_mii *); 262 static void dc_decode_leaf_sym (struct dc_softc *, struct dc_eblock_sym *); 263 static void dc_apply_fixup (struct dc_softc *, int); 264 265 #ifdef DC_USEIOSPACE 266 #define DC_RES SYS_RES_IOPORT 267 #define DC_RID DC_PCI_CFBIO 268 #else 269 #define DC_RES SYS_RES_MEMORY 270 #define DC_RID DC_PCI_CFBMA 271 #endif 272 273 static device_method_t dc_methods[] = { 274 /* Device interface */ 275 DEVMETHOD(device_probe, dc_probe), 276 DEVMETHOD(device_attach, dc_attach), 277 DEVMETHOD(device_detach, dc_detach), 278 DEVMETHOD(device_suspend, dc_suspend), 279 DEVMETHOD(device_resume, dc_resume), 280 DEVMETHOD(device_shutdown, dc_shutdown), 281 282 /* bus interface */ 283 DEVMETHOD(bus_print_child, bus_generic_print_child), 284 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 285 286 /* MII interface */ 287 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 288 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 289 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 290 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 291 292 { 0, 0 } 293 }; 294 295 static driver_t dc_driver = { 296 "dc", 297 dc_methods, 298 sizeof(struct dc_softc) 299 }; 300 301 static devclass_t dc_devclass; 302 #ifdef __i386__ 303 static int dc_quick=1; 304 SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW, 305 &dc_quick,0,"do not mdevget in dc driver"); 306 #endif 307 308 DRIVER_MODULE(if_dc, cardbus, dc_driver, dc_devclass, 0, 0); 309 DRIVER_MODULE(if_dc, pci, dc_driver, dc_devclass, 0, 0); 310 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 311 312 #define DC_SETBIT(sc, reg, x) \ 313 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 314 315 #define DC_CLRBIT(sc, reg, x) \ 316 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 317 318 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 319 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 320 321 #define IS_MPSAFE 0 322 323 static void 324 dc_delay(sc) 325 struct dc_softc *sc; 326 { 327 int idx; 328 329 for (idx = (300 / 33) + 1; idx > 0; idx--) 330 CSR_READ_4(sc, DC_BUSCTL); 331 } 332 333 static void 334 dc_eeprom_idle(sc) 335 struct dc_softc *sc; 336 { 337 register int i; 338 339 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 340 dc_delay(sc); 341 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 342 dc_delay(sc); 343 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 344 dc_delay(sc); 345 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 346 dc_delay(sc); 347 348 for (i = 0; i < 25; i++) { 349 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 350 dc_delay(sc); 351 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 352 dc_delay(sc); 353 } 354 355 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 356 dc_delay(sc); 357 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 358 dc_delay(sc); 359 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 360 361 return; 362 } 363 364 /* 365 * Send a read command and address to the EEPROM, check for ACK. 366 */ 367 static void 368 dc_eeprom_putbyte(sc, addr) 369 struct dc_softc *sc; 370 int addr; 371 { 372 register int d, i; 373 374 /* 375 * The AN985 has a 93C66 EEPROM on it instead of 376 * a 93C46. It uses a different bit sequence for 377 * specifying the "read" opcode. 378 */ 379 if (DC_IS_CENTAUR(sc) || DC_IS_CONEXANT(sc)) 380 d = addr | (DC_EECMD_READ << 2); 381 else 382 d = addr | DC_EECMD_READ; 383 384 /* 385 * Feed in each bit and strobe the clock. 386 */ 387 for (i = 0x400; i; i >>= 1) { 388 if (d & i) { 389 SIO_SET(DC_SIO_EE_DATAIN); 390 } else { 391 SIO_CLR(DC_SIO_EE_DATAIN); 392 } 393 dc_delay(sc); 394 SIO_SET(DC_SIO_EE_CLK); 395 dc_delay(sc); 396 SIO_CLR(DC_SIO_EE_CLK); 397 dc_delay(sc); 398 } 399 400 return; 401 } 402 403 /* 404 * Read a word of data stored in the EEPROM at address 'addr.' 405 * The PNIC 82c168/82c169 has its own non-standard way to read 406 * the EEPROM. 407 */ 408 static void 409 dc_eeprom_getword_pnic(sc, addr, dest) 410 struct dc_softc *sc; 411 int addr; 412 u_int16_t *dest; 413 { 414 register int i; 415 u_int32_t r; 416 417 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ|addr); 418 419 for (i = 0; i < DC_TIMEOUT; i++) { 420 DELAY(1); 421 r = CSR_READ_4(sc, DC_SIO); 422 if (!(r & DC_PN_SIOCTL_BUSY)) { 423 *dest = (u_int16_t)(r & 0xFFFF); 424 return; 425 } 426 } 427 428 return; 429 } 430 431 /* 432 * Read a word of data stored in the EEPROM at address 'addr.' 433 * The Xircom X3201 has its own non-standard way to read 434 * the EEPROM, too. 435 */ 436 static void 437 dc_eeprom_getword_xircom(sc, addr, dest) 438 struct dc_softc *sc; 439 int addr; 440 u_int16_t *dest; 441 { 442 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 443 444 addr *= 2; 445 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 446 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff; 447 addr += 1; 448 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 449 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff) << 8; 450 451 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 452 return; 453 } 454 455 /* 456 * Read a word of data stored in the EEPROM at address 'addr.' 457 */ 458 static void 459 dc_eeprom_getword(sc, addr, dest) 460 struct dc_softc *sc; 461 int addr; 462 u_int16_t *dest; 463 { 464 register int i; 465 u_int16_t word = 0; 466 467 /* Force EEPROM to idle state. */ 468 dc_eeprom_idle(sc); 469 470 /* Enter EEPROM access mode. */ 471 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 472 dc_delay(sc); 473 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 474 dc_delay(sc); 475 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 476 dc_delay(sc); 477 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 478 dc_delay(sc); 479 480 /* 481 * Send address of word we want to read. 482 */ 483 dc_eeprom_putbyte(sc, addr); 484 485 /* 486 * Start reading bits from EEPROM. 487 */ 488 for (i = 0x8000; i; i >>= 1) { 489 SIO_SET(DC_SIO_EE_CLK); 490 dc_delay(sc); 491 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 492 word |= i; 493 dc_delay(sc); 494 SIO_CLR(DC_SIO_EE_CLK); 495 dc_delay(sc); 496 } 497 498 /* Turn off EEPROM access mode. */ 499 dc_eeprom_idle(sc); 500 501 *dest = word; 502 503 return; 504 } 505 506 /* 507 * Read a sequence of words from the EEPROM. 508 */ 509 static void 510 dc_read_eeprom(sc, dest, off, cnt, swap) 511 struct dc_softc *sc; 512 caddr_t dest; 513 int off; 514 int cnt; 515 int swap; 516 { 517 int i; 518 u_int16_t word = 0, *ptr; 519 520 for (i = 0; i < cnt; i++) { 521 if (DC_IS_PNIC(sc)) 522 dc_eeprom_getword_pnic(sc, off + i, &word); 523 else if (DC_IS_XIRCOM(sc)) 524 dc_eeprom_getword_xircom(sc, off + i, &word); 525 else 526 dc_eeprom_getword(sc, off + i, &word); 527 ptr = (u_int16_t *)(dest + (i * 2)); 528 if (swap) 529 *ptr = ntohs(word); 530 else 531 *ptr = word; 532 } 533 534 return; 535 } 536 537 /* 538 * The following two routines are taken from the Macronix 98713 539 * Application Notes pp.19-21. 540 */ 541 /* 542 * Write a bit to the MII bus. 543 */ 544 static void 545 dc_mii_writebit(sc, bit) 546 struct dc_softc *sc; 547 int bit; 548 { 549 if (bit) 550 CSR_WRITE_4(sc, DC_SIO, 551 DC_SIO_ROMCTL_WRITE|DC_SIO_MII_DATAOUT); 552 else 553 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 554 555 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 556 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 557 558 return; 559 } 560 561 /* 562 * Read a bit from the MII bus. 563 */ 564 static int 565 dc_mii_readbit(sc) 566 struct dc_softc *sc; 567 { 568 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ|DC_SIO_MII_DIR); 569 CSR_READ_4(sc, DC_SIO); 570 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 571 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 572 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 573 return(1); 574 575 return(0); 576 } 577 578 /* 579 * Sync the PHYs by setting data bit and strobing the clock 32 times. 580 */ 581 static void 582 dc_mii_sync(sc) 583 struct dc_softc *sc; 584 { 585 register int i; 586 587 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 588 589 for (i = 0; i < 32; i++) 590 dc_mii_writebit(sc, 1); 591 592 return; 593 } 594 595 /* 596 * Clock a series of bits through the MII. 597 */ 598 static void 599 dc_mii_send(sc, bits, cnt) 600 struct dc_softc *sc; 601 u_int32_t bits; 602 int cnt; 603 { 604 int i; 605 606 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 607 dc_mii_writebit(sc, bits & i); 608 } 609 610 /* 611 * Read an PHY register through the MII. 612 */ 613 static int 614 dc_mii_readreg(sc, frame) 615 struct dc_softc *sc; 616 struct dc_mii_frame *frame; 617 618 { 619 int i, ack; 620 621 DC_LOCK(sc); 622 623 /* 624 * Set up frame for RX. 625 */ 626 frame->mii_stdelim = DC_MII_STARTDELIM; 627 frame->mii_opcode = DC_MII_READOP; 628 frame->mii_turnaround = 0; 629 frame->mii_data = 0; 630 631 /* 632 * Sync the PHYs. 633 */ 634 dc_mii_sync(sc); 635 636 /* 637 * Send command/address info. 638 */ 639 dc_mii_send(sc, frame->mii_stdelim, 2); 640 dc_mii_send(sc, frame->mii_opcode, 2); 641 dc_mii_send(sc, frame->mii_phyaddr, 5); 642 dc_mii_send(sc, frame->mii_regaddr, 5); 643 644 #ifdef notdef 645 /* Idle bit */ 646 dc_mii_writebit(sc, 1); 647 dc_mii_writebit(sc, 0); 648 #endif 649 650 /* Check for ack */ 651 ack = dc_mii_readbit(sc); 652 653 /* 654 * Now try reading data bits. If the ack failed, we still 655 * need to clock through 16 cycles to keep the PHY(s) in sync. 656 */ 657 if (ack) { 658 for(i = 0; i < 16; i++) { 659 dc_mii_readbit(sc); 660 } 661 goto fail; 662 } 663 664 for (i = 0x8000; i; i >>= 1) { 665 if (!ack) { 666 if (dc_mii_readbit(sc)) 667 frame->mii_data |= i; 668 } 669 } 670 671 fail: 672 673 dc_mii_writebit(sc, 0); 674 dc_mii_writebit(sc, 0); 675 676 DC_UNLOCK(sc); 677 678 if (ack) 679 return(1); 680 return(0); 681 } 682 683 /* 684 * Write to a PHY register through the MII. 685 */ 686 static int 687 dc_mii_writereg(sc, frame) 688 struct dc_softc *sc; 689 struct dc_mii_frame *frame; 690 691 { 692 DC_LOCK(sc); 693 /* 694 * Set up frame for TX. 695 */ 696 697 frame->mii_stdelim = DC_MII_STARTDELIM; 698 frame->mii_opcode = DC_MII_WRITEOP; 699 frame->mii_turnaround = DC_MII_TURNAROUND; 700 701 /* 702 * Sync the PHYs. 703 */ 704 dc_mii_sync(sc); 705 706 dc_mii_send(sc, frame->mii_stdelim, 2); 707 dc_mii_send(sc, frame->mii_opcode, 2); 708 dc_mii_send(sc, frame->mii_phyaddr, 5); 709 dc_mii_send(sc, frame->mii_regaddr, 5); 710 dc_mii_send(sc, frame->mii_turnaround, 2); 711 dc_mii_send(sc, frame->mii_data, 16); 712 713 /* Idle bit. */ 714 dc_mii_writebit(sc, 0); 715 dc_mii_writebit(sc, 0); 716 717 DC_UNLOCK(sc); 718 719 return(0); 720 } 721 722 static int 723 dc_miibus_readreg(dev, phy, reg) 724 device_t dev; 725 int phy, reg; 726 { 727 struct dc_mii_frame frame; 728 struct dc_softc *sc; 729 int i, rval, phy_reg = 0; 730 731 sc = device_get_softc(dev); 732 bzero((char *)&frame, sizeof(frame)); 733 734 /* 735 * Note: both the AL981 and AN985 have internal PHYs, 736 * however the AL981 provides direct access to the PHY 737 * registers while the AN985 uses a serial MII interface. 738 * The AN985's MII interface is also buggy in that you 739 * can read from any MII address (0 to 31), but only address 1 740 * behaves normally. To deal with both cases, we pretend 741 * that the PHY is at MII address 1. 742 */ 743 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 744 return(0); 745 746 /* 747 * Note: the ukphy probes of the RS7112 report a PHY at 748 * MII address 0 (possibly HomePNA?) and 1 (ethernet) 749 * so we only respond to correct one. 750 */ 751 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 752 return(0); 753 754 if (sc->dc_pmode != DC_PMODE_MII) { 755 if (phy == (MII_NPHY - 1)) { 756 switch(reg) { 757 case MII_BMSR: 758 /* 759 * Fake something to make the probe 760 * code think there's a PHY here. 761 */ 762 return(BMSR_MEDIAMASK); 763 break; 764 case MII_PHYIDR1: 765 if (DC_IS_PNIC(sc)) 766 return(DC_VENDORID_LO); 767 return(DC_VENDORID_DEC); 768 break; 769 case MII_PHYIDR2: 770 if (DC_IS_PNIC(sc)) 771 return(DC_DEVICEID_82C168); 772 return(DC_DEVICEID_21143); 773 break; 774 default: 775 return(0); 776 break; 777 } 778 } else 779 return(0); 780 } 781 782 if (DC_IS_PNIC(sc)) { 783 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 784 (phy << 23) | (reg << 18)); 785 for (i = 0; i < DC_TIMEOUT; i++) { 786 DELAY(1); 787 rval = CSR_READ_4(sc, DC_PN_MII); 788 if (!(rval & DC_PN_MII_BUSY)) { 789 rval &= 0xFFFF; 790 return(rval == 0xFFFF ? 0 : rval); 791 } 792 } 793 return(0); 794 } 795 796 if (DC_IS_COMET(sc)) { 797 switch(reg) { 798 case MII_BMCR: 799 phy_reg = DC_AL_BMCR; 800 break; 801 case MII_BMSR: 802 phy_reg = DC_AL_BMSR; 803 break; 804 case MII_PHYIDR1: 805 phy_reg = DC_AL_VENID; 806 break; 807 case MII_PHYIDR2: 808 phy_reg = DC_AL_DEVID; 809 break; 810 case MII_ANAR: 811 phy_reg = DC_AL_ANAR; 812 break; 813 case MII_ANLPAR: 814 phy_reg = DC_AL_LPAR; 815 break; 816 case MII_ANER: 817 phy_reg = DC_AL_ANER; 818 break; 819 default: 820 printf("dc%d: phy_read: bad phy register %x\n", 821 sc->dc_unit, reg); 822 return(0); 823 break; 824 } 825 826 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 827 828 if (rval == 0xFFFF) 829 return(0); 830 return(rval); 831 } 832 833 frame.mii_phyaddr = phy; 834 frame.mii_regaddr = reg; 835 if (sc->dc_type == DC_TYPE_98713) { 836 phy_reg = CSR_READ_4(sc, DC_NETCFG); 837 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 838 } 839 dc_mii_readreg(sc, &frame); 840 if (sc->dc_type == DC_TYPE_98713) 841 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 842 843 return(frame.mii_data); 844 } 845 846 static int 847 dc_miibus_writereg(dev, phy, reg, data) 848 device_t dev; 849 int phy, reg, data; 850 { 851 struct dc_softc *sc; 852 struct dc_mii_frame frame; 853 int i, phy_reg = 0; 854 855 sc = device_get_softc(dev); 856 bzero((char *)&frame, sizeof(frame)); 857 858 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 859 return(0); 860 861 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 862 return(0); 863 864 if (DC_IS_PNIC(sc)) { 865 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 866 (phy << 23) | (reg << 10) | data); 867 for (i = 0; i < DC_TIMEOUT; i++) { 868 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 869 break; 870 } 871 return(0); 872 } 873 874 if (DC_IS_COMET(sc)) { 875 switch(reg) { 876 case MII_BMCR: 877 phy_reg = DC_AL_BMCR; 878 break; 879 case MII_BMSR: 880 phy_reg = DC_AL_BMSR; 881 break; 882 case MII_PHYIDR1: 883 phy_reg = DC_AL_VENID; 884 break; 885 case MII_PHYIDR2: 886 phy_reg = DC_AL_DEVID; 887 break; 888 case MII_ANAR: 889 phy_reg = DC_AL_ANAR; 890 break; 891 case MII_ANLPAR: 892 phy_reg = DC_AL_LPAR; 893 break; 894 case MII_ANER: 895 phy_reg = DC_AL_ANER; 896 break; 897 default: 898 printf("dc%d: phy_write: bad phy register %x\n", 899 sc->dc_unit, reg); 900 return(0); 901 break; 902 } 903 904 CSR_WRITE_4(sc, phy_reg, data); 905 return(0); 906 } 907 908 frame.mii_phyaddr = phy; 909 frame.mii_regaddr = reg; 910 frame.mii_data = data; 911 912 if (sc->dc_type == DC_TYPE_98713) { 913 phy_reg = CSR_READ_4(sc, DC_NETCFG); 914 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 915 } 916 dc_mii_writereg(sc, &frame); 917 if (sc->dc_type == DC_TYPE_98713) 918 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 919 920 return(0); 921 } 922 923 static void 924 dc_miibus_statchg(dev) 925 device_t dev; 926 { 927 struct dc_softc *sc; 928 struct mii_data *mii; 929 struct ifmedia *ifm; 930 931 sc = device_get_softc(dev); 932 if (DC_IS_ADMTEK(sc)) 933 return; 934 935 mii = device_get_softc(sc->dc_miibus); 936 ifm = &mii->mii_media; 937 if (DC_IS_DAVICOM(sc) && 938 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 939 dc_setcfg(sc, ifm->ifm_media); 940 sc->dc_if_media = ifm->ifm_media; 941 } else { 942 dc_setcfg(sc, mii->mii_media_active); 943 sc->dc_if_media = mii->mii_media_active; 944 } 945 946 return; 947 } 948 949 /* 950 * Special support for DM9102A cards with HomePNA PHYs. Note: 951 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 952 * to be impossible to talk to the management interface of the DM9801 953 * PHY (its MDIO pin is not connected to anything). Consequently, 954 * the driver has to just 'know' about the additional mode and deal 955 * with it itself. *sigh* 956 */ 957 static void 958 dc_miibus_mediainit(dev) 959 device_t dev; 960 { 961 struct dc_softc *sc; 962 struct mii_data *mii; 963 struct ifmedia *ifm; 964 int rev; 965 966 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 967 968 sc = device_get_softc(dev); 969 mii = device_get_softc(sc->dc_miibus); 970 ifm = &mii->mii_media; 971 972 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 973 ifmedia_add(ifm, IFM_ETHER|IFM_HPNA_1, 0, NULL); 974 975 return; 976 } 977 978 #define DC_POLY 0xEDB88320 979 #define DC_BITS_512 9 980 #define DC_BITS_128 7 981 #define DC_BITS_64 6 982 983 static u_int32_t 984 dc_crc_le(sc, addr) 985 struct dc_softc *sc; 986 caddr_t addr; 987 { 988 u_int32_t idx, bit, data, crc; 989 990 /* Compute CRC for the address value. */ 991 crc = 0xFFFFFFFF; /* initial value */ 992 993 for (idx = 0; idx < 6; idx++) { 994 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 995 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 996 } 997 998 /* 999 * The hash table on the PNIC II and the MX98715AEC-C/D/E 1000 * chips is only 128 bits wide. 1001 */ 1002 if (sc->dc_flags & DC_128BIT_HASH) 1003 return (crc & ((1 << DC_BITS_128) - 1)); 1004 1005 /* The hash table on the MX98715BEC is only 64 bits wide. */ 1006 if (sc->dc_flags & DC_64BIT_HASH) 1007 return (crc & ((1 << DC_BITS_64) - 1)); 1008 1009 /* Xircom's hash filtering table is different (read: weird) */ 1010 /* Xircom uses the LEAST significant bits */ 1011 if (DC_IS_XIRCOM(sc)) { 1012 if ((crc & 0x180) == 0x180) 1013 return (crc & 0x0F) + (crc & 0x70)*3 + (14 << 4); 1014 else 1015 return (crc & 0x1F) + ((crc>>1) & 0xF0)*3 + (12 << 4); 1016 } 1017 1018 return (crc & ((1 << DC_BITS_512) - 1)); 1019 } 1020 1021 /* 1022 * Calculate CRC of a multicast group address, return the lower 6 bits. 1023 */ 1024 static u_int32_t 1025 dc_crc_be(addr) 1026 caddr_t addr; 1027 { 1028 u_int32_t crc, carry; 1029 int i, j; 1030 u_int8_t c; 1031 1032 /* Compute CRC for the address value. */ 1033 crc = 0xFFFFFFFF; /* initial value */ 1034 1035 for (i = 0; i < 6; i++) { 1036 c = *(addr + i); 1037 for (j = 0; j < 8; j++) { 1038 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 1039 crc <<= 1; 1040 c >>= 1; 1041 if (carry) 1042 crc = (crc ^ 0x04c11db6) | carry; 1043 } 1044 } 1045 1046 /* return the filter bit position */ 1047 return((crc >> 26) & 0x0000003F); 1048 } 1049 1050 /* 1051 * 21143-style RX filter setup routine. Filter programming is done by 1052 * downloading a special setup frame into the TX engine. 21143, Macronix, 1053 * PNIC, PNIC II and Davicom chips are programmed this way. 1054 * 1055 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1056 * address (our node address) and a 512-bit hash filter for multicast 1057 * frames. We also sneak the broadcast address into the hash filter since 1058 * we need that too. 1059 */ 1060 void 1061 dc_setfilt_21143(sc) 1062 struct dc_softc *sc; 1063 { 1064 struct dc_desc *sframe; 1065 u_int32_t h, *sp; 1066 struct ifmultiaddr *ifma; 1067 struct ifnet *ifp; 1068 int i; 1069 1070 ifp = &sc->arpcom.ac_if; 1071 1072 i = sc->dc_cdata.dc_tx_prod; 1073 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1074 sc->dc_cdata.dc_tx_cnt++; 1075 sframe = &sc->dc_ldata->dc_tx_list[i]; 1076 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1077 bzero((char *)sp, DC_SFRAME_LEN); 1078 1079 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1080 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1081 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1082 1083 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1084 1085 /* If we want promiscuous mode, set the allframes bit. */ 1086 if (ifp->if_flags & IFF_PROMISC) 1087 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1088 else 1089 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1090 1091 if (ifp->if_flags & IFF_ALLMULTI) 1092 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1093 else 1094 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1095 1096 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1097 if (ifma->ifma_addr->sa_family != AF_LINK) 1098 continue; 1099 h = dc_crc_le(sc, 1100 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1101 sp[h >> 4] |= 1 << (h & 0xF); 1102 } 1103 1104 if (ifp->if_flags & IFF_BROADCAST) { 1105 h = dc_crc_le(sc, (caddr_t)ðerbroadcastaddr); 1106 sp[h >> 4] |= 1 << (h & 0xF); 1107 } 1108 1109 /* Set our MAC address */ 1110 sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1111 sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1112 sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1113 1114 sframe->dc_status = DC_TXSTAT_OWN; 1115 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1116 1117 /* 1118 * The PNIC takes an exceedingly long time to process its 1119 * setup frame; wait 10ms after posting the setup frame 1120 * before proceeding, just so it has time to swallow its 1121 * medicine. 1122 */ 1123 DELAY(10000); 1124 1125 ifp->if_timer = 5; 1126 1127 return; 1128 } 1129 1130 void 1131 dc_setfilt_admtek(sc) 1132 struct dc_softc *sc; 1133 { 1134 struct ifnet *ifp; 1135 int h = 0; 1136 u_int32_t hashes[2] = { 0, 0 }; 1137 struct ifmultiaddr *ifma; 1138 1139 ifp = &sc->arpcom.ac_if; 1140 1141 /* Init our MAC address */ 1142 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1143 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1144 1145 /* If we want promiscuous mode, set the allframes bit. */ 1146 if (ifp->if_flags & IFF_PROMISC) 1147 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1148 else 1149 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1150 1151 if (ifp->if_flags & IFF_ALLMULTI) 1152 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1153 else 1154 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1155 1156 /* first, zot all the existing hash bits */ 1157 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1158 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1159 1160 /* 1161 * If we're already in promisc or allmulti mode, we 1162 * don't have to bother programming the multicast filter. 1163 */ 1164 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1165 return; 1166 1167 /* now program new ones */ 1168 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1169 if (ifma->ifma_addr->sa_family != AF_LINK) 1170 continue; 1171 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1172 if (h < 32) 1173 hashes[0] |= (1 << h); 1174 else 1175 hashes[1] |= (1 << (h - 32)); 1176 } 1177 1178 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1179 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1180 1181 return; 1182 } 1183 1184 void 1185 dc_setfilt_asix(sc) 1186 struct dc_softc *sc; 1187 { 1188 struct ifnet *ifp; 1189 int h = 0; 1190 u_int32_t hashes[2] = { 0, 0 }; 1191 struct ifmultiaddr *ifma; 1192 1193 ifp = &sc->arpcom.ac_if; 1194 1195 /* Init our MAC address */ 1196 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1197 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1198 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1199 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1200 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1201 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1202 1203 /* If we want promiscuous mode, set the allframes bit. */ 1204 if (ifp->if_flags & IFF_PROMISC) 1205 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1206 else 1207 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1208 1209 if (ifp->if_flags & IFF_ALLMULTI) 1210 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1211 else 1212 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1213 1214 /* 1215 * The ASIX chip has a special bit to enable reception 1216 * of broadcast frames. 1217 */ 1218 if (ifp->if_flags & IFF_BROADCAST) 1219 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1220 else 1221 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1222 1223 /* first, zot all the existing hash bits */ 1224 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1225 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1226 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1227 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1228 1229 /* 1230 * If we're already in promisc or allmulti mode, we 1231 * don't have to bother programming the multicast filter. 1232 */ 1233 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1234 return; 1235 1236 /* now program new ones */ 1237 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1238 if (ifma->ifma_addr->sa_family != AF_LINK) 1239 continue; 1240 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1241 if (h < 32) 1242 hashes[0] |= (1 << h); 1243 else 1244 hashes[1] |= (1 << (h - 32)); 1245 } 1246 1247 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1248 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1249 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1250 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1251 1252 return; 1253 } 1254 1255 void 1256 dc_setfilt_xircom(sc) 1257 struct dc_softc *sc; 1258 { 1259 struct dc_desc *sframe; 1260 u_int32_t h, *sp; 1261 struct ifmultiaddr *ifma; 1262 struct ifnet *ifp; 1263 int i; 1264 1265 ifp = &sc->arpcom.ac_if; 1266 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1267 1268 i = sc->dc_cdata.dc_tx_prod; 1269 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1270 sc->dc_cdata.dc_tx_cnt++; 1271 sframe = &sc->dc_ldata->dc_tx_list[i]; 1272 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1273 bzero((char *)sp, DC_SFRAME_LEN); 1274 1275 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1276 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1277 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1278 1279 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1280 1281 /* If we want promiscuous mode, set the allframes bit. */ 1282 if (ifp->if_flags & IFF_PROMISC) 1283 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1284 else 1285 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1286 1287 if (ifp->if_flags & IFF_ALLMULTI) 1288 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1289 else 1290 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1291 1292 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1293 if (ifma->ifma_addr->sa_family != AF_LINK) 1294 continue; 1295 h = dc_crc_le(sc, 1296 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1297 sp[h >> 4] |= 1 << (h & 0xF); 1298 } 1299 1300 if (ifp->if_flags & IFF_BROADCAST) { 1301 h = dc_crc_le(sc, (caddr_t)ðerbroadcastaddr); 1302 sp[h >> 4] |= 1 << (h & 0xF); 1303 } 1304 1305 /* Set our MAC address */ 1306 sp[0] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1307 sp[1] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1308 sp[2] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1309 1310 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1311 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1312 ifp->if_flags |= IFF_RUNNING; 1313 sframe->dc_status = DC_TXSTAT_OWN; 1314 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1315 1316 /* 1317 * wait some time... 1318 */ 1319 DELAY(1000); 1320 1321 ifp->if_timer = 5; 1322 1323 return; 1324 } 1325 1326 static void 1327 dc_setfilt(sc) 1328 struct dc_softc *sc; 1329 { 1330 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1331 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1332 dc_setfilt_21143(sc); 1333 1334 if (DC_IS_ASIX(sc)) 1335 dc_setfilt_asix(sc); 1336 1337 if (DC_IS_ADMTEK(sc)) 1338 dc_setfilt_admtek(sc); 1339 1340 if (DC_IS_XIRCOM(sc)) 1341 dc_setfilt_xircom(sc); 1342 1343 return; 1344 } 1345 1346 /* 1347 * In order to fiddle with the 1348 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 1349 * first have to put the transmit and/or receive logic in the idle state. 1350 */ 1351 static void 1352 dc_setcfg(sc, media) 1353 struct dc_softc *sc; 1354 int media; 1355 { 1356 int i, restart = 0; 1357 u_int32_t isr; 1358 1359 if (IFM_SUBTYPE(media) == IFM_NONE) 1360 return; 1361 1362 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)) { 1363 restart = 1; 1364 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1365 1366 for (i = 0; i < DC_TIMEOUT; i++) { 1367 isr = CSR_READ_4(sc, DC_ISR); 1368 if (isr & DC_ISR_TX_IDLE && 1369 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1370 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT)) 1371 break; 1372 DELAY(10); 1373 } 1374 1375 if (i == DC_TIMEOUT) 1376 printf("dc%d: failed to force tx and " 1377 "rx to idle state\n", sc->dc_unit); 1378 } 1379 1380 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1381 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1382 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1383 if (sc->dc_pmode == DC_PMODE_MII) { 1384 int watchdogreg; 1385 1386 if (DC_IS_INTEL(sc)) { 1387 /* there's a write enable bit here that reads as 1 */ 1388 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1389 watchdogreg &= ~DC_WDOG_CTLWREN; 1390 watchdogreg |= DC_WDOG_JABBERDIS; 1391 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1392 } else { 1393 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1394 } 1395 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1396 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1397 if (sc->dc_type == DC_TYPE_98713) 1398 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1399 DC_NETCFG_SCRAMBLER)); 1400 if (!DC_IS_DAVICOM(sc)) 1401 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1402 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1403 if (DC_IS_INTEL(sc)) 1404 dc_apply_fixup(sc, IFM_AUTO); 1405 } else { 1406 if (DC_IS_PNIC(sc)) { 1407 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1408 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1409 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1410 } 1411 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1412 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1413 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1414 if (DC_IS_INTEL(sc)) 1415 dc_apply_fixup(sc, 1416 (media & IFM_GMASK) == IFM_FDX ? 1417 IFM_100_TX|IFM_FDX : IFM_100_TX); 1418 } 1419 } 1420 1421 if (IFM_SUBTYPE(media) == IFM_10_T) { 1422 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1423 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1424 if (sc->dc_pmode == DC_PMODE_MII) { 1425 int watchdogreg; 1426 1427 /* there's a write enable bit here that reads as 1 */ 1428 if (DC_IS_INTEL(sc)) { 1429 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1430 watchdogreg &= ~DC_WDOG_CTLWREN; 1431 watchdogreg |= DC_WDOG_JABBERDIS; 1432 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1433 } else { 1434 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1435 } 1436 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1437 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1438 if (sc->dc_type == DC_TYPE_98713) 1439 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1440 if (!DC_IS_DAVICOM(sc)) 1441 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1442 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1443 if (DC_IS_INTEL(sc)) 1444 dc_apply_fixup(sc, IFM_AUTO); 1445 } else { 1446 if (DC_IS_PNIC(sc)) { 1447 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1448 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1449 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1450 } 1451 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1452 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1453 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1454 if (DC_IS_INTEL(sc)) { 1455 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1456 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1457 if ((media & IFM_GMASK) == IFM_FDX) 1458 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1459 else 1460 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1461 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1462 DC_CLRBIT(sc, DC_10BTCTRL, 1463 DC_TCTL_AUTONEGENBL); 1464 dc_apply_fixup(sc, 1465 (media & IFM_GMASK) == IFM_FDX ? 1466 IFM_10_T|IFM_FDX : IFM_10_T); 1467 DELAY(20000); 1468 } 1469 } 1470 } 1471 1472 /* 1473 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1474 * PHY and we want HomePNA mode, set the portsel bit to turn 1475 * on the external MII port. 1476 */ 1477 if (DC_IS_DAVICOM(sc)) { 1478 if (IFM_SUBTYPE(media) == IFM_HPNA_1) { 1479 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1480 sc->dc_link = 1; 1481 } else { 1482 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1483 } 1484 } 1485 1486 if (DC_IS_ADMTEK(sc)) 1487 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); 1488 1489 if ((media & IFM_GMASK) == IFM_FDX) { 1490 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1491 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1492 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1493 } else { 1494 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1495 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1496 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1497 } 1498 1499 if (restart) 1500 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON|DC_NETCFG_RX_ON); 1501 1502 return; 1503 } 1504 1505 static void 1506 dc_reset(sc) 1507 struct dc_softc *sc; 1508 { 1509 register int i; 1510 1511 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1512 1513 for (i = 0; i < DC_TIMEOUT; i++) { 1514 DELAY(10); 1515 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1516 break; 1517 } 1518 1519 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) || 1520 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) { 1521 DELAY(10000); 1522 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1523 i = 0; 1524 } 1525 1526 if (i == DC_TIMEOUT) 1527 printf("dc%d: reset never completed!\n", sc->dc_unit); 1528 1529 /* Wait a little while for the chip to get its brains in order. */ 1530 DELAY(1000); 1531 1532 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1533 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1534 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1535 1536 /* 1537 * Bring the SIA out of reset. In some cases, it looks 1538 * like failing to unreset the SIA soon enough gets it 1539 * into a state where it will never come out of reset 1540 * until we reset the whole chip again. 1541 */ 1542 if (DC_IS_INTEL(sc)) { 1543 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1544 CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1545 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1546 } 1547 1548 return; 1549 } 1550 1551 static struct dc_type * 1552 dc_devtype(dev) 1553 device_t dev; 1554 { 1555 struct dc_type *t; 1556 u_int32_t rev; 1557 1558 t = dc_devs; 1559 1560 while(t->dc_name != NULL) { 1561 if ((pci_get_vendor(dev) == t->dc_vid) && 1562 (pci_get_device(dev) == t->dc_did)) { 1563 /* Check the PCI revision */ 1564 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1565 if (t->dc_did == DC_DEVICEID_98713 && 1566 rev >= DC_REVISION_98713A) 1567 t++; 1568 if (t->dc_did == DC_DEVICEID_98713_CP && 1569 rev >= DC_REVISION_98713A) 1570 t++; 1571 if (t->dc_did == DC_DEVICEID_987x5 && 1572 rev >= DC_REVISION_98715AEC_C) 1573 t++; 1574 if (t->dc_did == DC_DEVICEID_987x5 && 1575 rev >= DC_REVISION_98725) 1576 t++; 1577 if (t->dc_did == DC_DEVICEID_AX88140A && 1578 rev >= DC_REVISION_88141) 1579 t++; 1580 if (t->dc_did == DC_DEVICEID_82C168 && 1581 rev >= DC_REVISION_82C169) 1582 t++; 1583 if (t->dc_did == DC_DEVICEID_DM9102 && 1584 rev >= DC_REVISION_DM9102A) 1585 t++; 1586 return(t); 1587 } 1588 t++; 1589 } 1590 1591 return(NULL); 1592 } 1593 1594 /* 1595 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1596 * IDs against our list and return a device name if we find a match. 1597 * We do a little bit of extra work to identify the exact type of 1598 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1599 * but different revision IDs. The same is true for 98715/98715A 1600 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1601 * cases, the exact chip revision affects driver behavior. 1602 */ 1603 static int 1604 dc_probe(dev) 1605 device_t dev; 1606 { 1607 struct dc_type *t; 1608 1609 t = dc_devtype(dev); 1610 1611 if (t != NULL) { 1612 device_set_desc(dev, t->dc_name); 1613 return(0); 1614 } 1615 1616 return(ENXIO); 1617 } 1618 1619 static void 1620 dc_acpi(dev) 1621 device_t dev; 1622 { 1623 int unit; 1624 1625 unit = device_get_unit(dev); 1626 1627 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1628 u_int32_t iobase, membase, irq; 1629 1630 /* Save important PCI config data. */ 1631 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4); 1632 membase = pci_read_config(dev, DC_PCI_CFBMA, 4); 1633 irq = pci_read_config(dev, DC_PCI_CFIT, 4); 1634 1635 /* Reset the power state. */ 1636 printf("dc%d: chip is in D%d power mode " 1637 "-- setting to D0\n", unit, 1638 pci_get_powerstate(dev)); 1639 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1640 1641 /* Restore PCI config data. */ 1642 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4); 1643 pci_write_config(dev, DC_PCI_CFBMA, membase, 4); 1644 pci_write_config(dev, DC_PCI_CFIT, irq, 4); 1645 } 1646 1647 return; 1648 } 1649 1650 static void 1651 dc_apply_fixup(sc, media) 1652 struct dc_softc *sc; 1653 int media; 1654 { 1655 struct dc_mediainfo *m; 1656 u_int8_t *p; 1657 int i; 1658 u_int32_t reg; 1659 1660 m = sc->dc_mi; 1661 1662 while (m != NULL) { 1663 if (m->dc_media == media) 1664 break; 1665 m = m->dc_next; 1666 } 1667 1668 if (m == NULL) 1669 return; 1670 1671 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1672 reg = (p[0] | (p[1] << 8)) << 16; 1673 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1674 } 1675 1676 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1677 reg = (p[0] | (p[1] << 8)) << 16; 1678 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1679 } 1680 1681 return; 1682 } 1683 1684 static void 1685 dc_decode_leaf_sia(sc, l) 1686 struct dc_softc *sc; 1687 struct dc_eblock_sia *l; 1688 { 1689 struct dc_mediainfo *m; 1690 1691 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1692 bzero(m, sizeof(struct dc_mediainfo)); 1693 if (l->dc_sia_code == DC_SIA_CODE_10BT) 1694 m->dc_media = IFM_10_T; 1695 1696 if (l->dc_sia_code == DC_SIA_CODE_10BT_FDX) 1697 m->dc_media = IFM_10_T|IFM_FDX; 1698 1699 if (l->dc_sia_code == DC_SIA_CODE_10B2) 1700 m->dc_media = IFM_10_2; 1701 1702 if (l->dc_sia_code == DC_SIA_CODE_10B5) 1703 m->dc_media = IFM_10_5; 1704 1705 m->dc_gp_len = 2; 1706 m->dc_gp_ptr = (u_int8_t *)&l->dc_sia_gpio_ctl; 1707 1708 m->dc_next = sc->dc_mi; 1709 sc->dc_mi = m; 1710 1711 sc->dc_pmode = DC_PMODE_SIA; 1712 1713 return; 1714 } 1715 1716 static void 1717 dc_decode_leaf_sym(sc, l) 1718 struct dc_softc *sc; 1719 struct dc_eblock_sym *l; 1720 { 1721 struct dc_mediainfo *m; 1722 1723 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1724 bzero(m, sizeof(struct dc_mediainfo)); 1725 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1726 m->dc_media = IFM_100_TX; 1727 1728 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1729 m->dc_media = IFM_100_TX|IFM_FDX; 1730 1731 m->dc_gp_len = 2; 1732 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1733 1734 m->dc_next = sc->dc_mi; 1735 sc->dc_mi = m; 1736 1737 sc->dc_pmode = DC_PMODE_SYM; 1738 1739 return; 1740 } 1741 1742 static void 1743 dc_decode_leaf_mii(sc, l) 1744 struct dc_softc *sc; 1745 struct dc_eblock_mii *l; 1746 { 1747 u_int8_t *p; 1748 struct dc_mediainfo *m; 1749 1750 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1751 bzero(m, sizeof(struct dc_mediainfo)); 1752 /* We abuse IFM_AUTO to represent MII. */ 1753 m->dc_media = IFM_AUTO; 1754 m->dc_gp_len = l->dc_gpr_len; 1755 1756 p = (u_int8_t *)l; 1757 p += sizeof(struct dc_eblock_mii); 1758 m->dc_gp_ptr = p; 1759 p += 2 * l->dc_gpr_len; 1760 m->dc_reset_len = *p; 1761 p++; 1762 m->dc_reset_ptr = p; 1763 1764 m->dc_next = sc->dc_mi; 1765 sc->dc_mi = m; 1766 1767 return; 1768 } 1769 1770 static void 1771 dc_parse_21143_srom(sc) 1772 struct dc_softc *sc; 1773 { 1774 struct dc_leaf_hdr *lhdr; 1775 struct dc_eblock_hdr *hdr; 1776 int i, loff; 1777 char *ptr; 1778 1779 loff = sc->dc_srom[27]; 1780 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1781 1782 ptr = (char *)lhdr; 1783 ptr += sizeof(struct dc_leaf_hdr) - 1; 1784 for (i = 0; i < lhdr->dc_mcnt; i++) { 1785 hdr = (struct dc_eblock_hdr *)ptr; 1786 switch(hdr->dc_type) { 1787 case DC_EBLOCK_MII: 1788 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1789 break; 1790 case DC_EBLOCK_SIA: 1791 dc_decode_leaf_sia(sc, (struct dc_eblock_sia *)hdr); 1792 break; 1793 case DC_EBLOCK_SYM: 1794 dc_decode_leaf_sym(sc, (struct dc_eblock_sym *)hdr); 1795 break; 1796 default: 1797 /* Don't care. Yet. */ 1798 break; 1799 } 1800 ptr += (hdr->dc_len & 0x7F); 1801 ptr++; 1802 } 1803 1804 return; 1805 } 1806 1807 /* 1808 * Attach the interface. Allocate softc structures, do ifmedia 1809 * setup and ethernet/BPF attach. 1810 */ 1811 static int 1812 dc_attach(dev) 1813 device_t dev; 1814 { 1815 int tmp = 0; 1816 u_char eaddr[ETHER_ADDR_LEN]; 1817 u_int32_t command; 1818 struct dc_softc *sc; 1819 struct ifnet *ifp; 1820 u_int32_t revision; 1821 int unit, error = 0, rid, mac_offset; 1822 1823 sc = device_get_softc(dev); 1824 unit = device_get_unit(dev); 1825 bzero(sc, sizeof(struct dc_softc)); 1826 1827 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1828 MTX_DEF | MTX_RECURSE); 1829 1830 /* 1831 * Handle power management nonsense. 1832 */ 1833 dc_acpi(dev); 1834 1835 /* 1836 * Map control/status registers. 1837 */ 1838 pci_enable_busmaster(dev); 1839 pci_enable_io(dev, SYS_RES_IOPORT); 1840 pci_enable_io(dev, SYS_RES_MEMORY); 1841 command = pci_read_config(dev, PCIR_COMMAND, 4); 1842 1843 #ifdef DC_USEIOSPACE 1844 if (!(command & PCIM_CMD_PORTEN)) { 1845 printf("dc%d: failed to enable I/O ports!\n", unit); 1846 error = ENXIO; 1847 goto fail_nolock; 1848 } 1849 #else 1850 if (!(command & PCIM_CMD_MEMEN)) { 1851 printf("dc%d: failed to enable memory mapping!\n", unit); 1852 error = ENXIO; 1853 goto fail_nolock; 1854 } 1855 #endif 1856 1857 rid = DC_RID; 1858 sc->dc_res = bus_alloc_resource(dev, DC_RES, &rid, 1859 0, ~0, 1, RF_ACTIVE); 1860 1861 if (sc->dc_res == NULL) { 1862 printf("dc%d: couldn't map ports/memory\n", unit); 1863 error = ENXIO; 1864 goto fail_nolock; 1865 } 1866 1867 sc->dc_btag = rman_get_bustag(sc->dc_res); 1868 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1869 1870 /* Allocate interrupt */ 1871 rid = 0; 1872 sc->dc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1873 RF_SHAREABLE | RF_ACTIVE); 1874 1875 if (sc->dc_irq == NULL) { 1876 printf("dc%d: couldn't map interrupt\n", unit); 1877 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1878 error = ENXIO; 1879 goto fail_nolock; 1880 } 1881 1882 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | 1883 (IS_MPSAFE ? INTR_MPSAFE : 0), 1884 dc_intr, sc, &sc->dc_intrhand); 1885 1886 if (error) { 1887 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 1888 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1889 printf("dc%d: couldn't set up irq\n", unit); 1890 goto fail_nolock; 1891 } 1892 DC_LOCK(sc); 1893 1894 /* Need this info to decide on a chip type. */ 1895 sc->dc_info = dc_devtype(dev); 1896 revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF; 1897 1898 switch(sc->dc_info->dc_did) { 1899 case DC_DEVICEID_21143: 1900 sc->dc_type = DC_TYPE_21143; 1901 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1902 sc->dc_flags |= DC_REDUCED_MII_POLL; 1903 /* Save EEPROM contents so we can parse them later. */ 1904 dc_read_eeprom(sc, (caddr_t)&sc->dc_srom, 0, 512, 0); 1905 break; 1906 case DC_DEVICEID_DM9100: 1907 case DC_DEVICEID_DM9102: 1908 sc->dc_type = DC_TYPE_DM9102; 1909 sc->dc_flags |= DC_TX_COALESCE|DC_TX_INTR_ALWAYS; 1910 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_TX_STORENFWD; 1911 sc->dc_pmode = DC_PMODE_MII; 1912 /* Increase the latency timer value. */ 1913 command = pci_read_config(dev, DC_PCI_CFLT, 4); 1914 command &= 0xFFFF00FF; 1915 command |= 0x00008000; 1916 pci_write_config(dev, DC_PCI_CFLT, command, 4); 1917 break; 1918 case DC_DEVICEID_AL981: 1919 sc->dc_type = DC_TYPE_AL981; 1920 sc->dc_flags |= DC_TX_USE_TX_INTR; 1921 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1922 sc->dc_pmode = DC_PMODE_MII; 1923 break; 1924 case DC_DEVICEID_AN985: 1925 case DC_DEVICEID_FE2500: 1926 case DC_DEVICEID_EN2242: 1927 sc->dc_type = DC_TYPE_AN985; 1928 sc->dc_flags |= DC_TX_USE_TX_INTR; 1929 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1930 sc->dc_pmode = DC_PMODE_MII; 1931 break; 1932 case DC_DEVICEID_98713: 1933 case DC_DEVICEID_98713_CP: 1934 if (revision < DC_REVISION_98713A) { 1935 sc->dc_type = DC_TYPE_98713; 1936 } 1937 if (revision >= DC_REVISION_98713A) { 1938 sc->dc_type = DC_TYPE_98713A; 1939 sc->dc_flags |= DC_21143_NWAY; 1940 } 1941 sc->dc_flags |= DC_REDUCED_MII_POLL; 1942 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1943 break; 1944 case DC_DEVICEID_987x5: 1945 case DC_DEVICEID_EN1217: 1946 /* 1947 * Macronix MX98715AEC-C/D/E parts have only a 1948 * 128-bit hash table. We need to deal with these 1949 * in the same manner as the PNIC II so that we 1950 * get the right number of bits out of the 1951 * CRC routine. 1952 */ 1953 if (revision >= DC_REVISION_98715AEC_C && 1954 revision < DC_REVISION_98725) 1955 sc->dc_flags |= DC_128BIT_HASH; 1956 sc->dc_type = DC_TYPE_987x5; 1957 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1958 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1959 break; 1960 case DC_DEVICEID_98727: 1961 sc->dc_type = DC_TYPE_987x5; 1962 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1963 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1964 break; 1965 case DC_DEVICEID_82C115: 1966 sc->dc_type = DC_TYPE_PNICII; 1967 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR|DC_128BIT_HASH; 1968 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1969 break; 1970 case DC_DEVICEID_82C168: 1971 sc->dc_type = DC_TYPE_PNIC; 1972 sc->dc_flags |= DC_TX_STORENFWD|DC_TX_INTR_ALWAYS; 1973 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 1974 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 1975 if (revision < DC_REVISION_82C169) 1976 sc->dc_pmode = DC_PMODE_SYM; 1977 break; 1978 case DC_DEVICEID_AX88140A: 1979 sc->dc_type = DC_TYPE_ASIX; 1980 sc->dc_flags |= DC_TX_USE_TX_INTR|DC_TX_INTR_FIRSTFRAG; 1981 sc->dc_flags |= DC_REDUCED_MII_POLL; 1982 sc->dc_pmode = DC_PMODE_MII; 1983 break; 1984 case DC_DEVICEID_X3201: 1985 sc->dc_type = DC_TYPE_XIRCOM; 1986 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 1987 DC_TX_ALIGN; 1988 /* 1989 * We don't actually need to coalesce, but we're doing 1990 * it to obtain a double word aligned buffer. 1991 * The DC_TX_COALESCE flag is required. 1992 */ 1993 break; 1994 case DC_DEVICEID_RS7112: 1995 sc->dc_type = DC_TYPE_CONEXANT; 1996 sc->dc_flags |= DC_TX_INTR_ALWAYS; 1997 sc->dc_flags |= DC_REDUCED_MII_POLL; 1998 sc->dc_pmode = DC_PMODE_MII; 1999 dc_read_eeprom(sc, (caddr_t)&sc->dc_srom, 0, 256, 0); 2000 break; 2001 default: 2002 printf("dc%d: unknown device: %x\n", sc->dc_unit, 2003 sc->dc_info->dc_did); 2004 break; 2005 } 2006 2007 /* Save the cache line size. */ 2008 if (DC_IS_DAVICOM(sc)) 2009 sc->dc_cachesize = 0; 2010 else 2011 sc->dc_cachesize = pci_read_config(dev, 2012 DC_PCI_CFLT, 4) & 0xFF; 2013 2014 /* Reset the adapter. */ 2015 dc_reset(sc); 2016 2017 /* Take 21143 out of snooze mode */ 2018 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 2019 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2020 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 2021 pci_write_config(dev, DC_PCI_CFDD, command, 4); 2022 } 2023 2024 /* 2025 * Try to learn something about the supported media. 2026 * We know that ASIX and ADMtek and Davicom devices 2027 * will *always* be using MII media, so that's a no-brainer. 2028 * The tricky ones are the Macronix/PNIC II and the 2029 * Intel 21143. 2030 */ 2031 if (DC_IS_INTEL(sc)) 2032 dc_parse_21143_srom(sc); 2033 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2034 if (sc->dc_type == DC_TYPE_98713) 2035 sc->dc_pmode = DC_PMODE_MII; 2036 else 2037 sc->dc_pmode = DC_PMODE_SYM; 2038 } else if (!sc->dc_pmode) 2039 sc->dc_pmode = DC_PMODE_MII; 2040 2041 /* 2042 * Get station address from the EEPROM. 2043 */ 2044 switch(sc->dc_type) { 2045 case DC_TYPE_98713: 2046 case DC_TYPE_98713A: 2047 case DC_TYPE_987x5: 2048 case DC_TYPE_PNICII: 2049 dc_read_eeprom(sc, (caddr_t)&mac_offset, 2050 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2051 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2052 break; 2053 case DC_TYPE_PNIC: 2054 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2055 break; 2056 case DC_TYPE_DM9102: 2057 case DC_TYPE_21143: 2058 case DC_TYPE_ASIX: 2059 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2060 break; 2061 case DC_TYPE_AL981: 2062 case DC_TYPE_AN985: 2063 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_AL_EE_NODEADDR, 3, 0); 2064 break; 2065 case DC_TYPE_CONEXANT: 2066 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 6); 2067 break; 2068 case DC_TYPE_XIRCOM: 2069 dc_read_eeprom(sc, (caddr_t)&eaddr, 3, 3, 0); 2070 break; 2071 default: 2072 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2073 break; 2074 } 2075 2076 /* 2077 * A 21143 or clone chip was detected. Inform the world. 2078 */ 2079 printf("dc%d: Ethernet address: %6D\n", unit, eaddr, ":"); 2080 2081 sc->dc_unit = unit; 2082 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 2083 2084 sc->dc_ldata = contigmalloc(sizeof(struct dc_list_data), M_DEVBUF, 2085 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 2086 2087 if (sc->dc_ldata == NULL) { 2088 printf("dc%d: no memory for list buffers!\n", unit); 2089 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2090 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2091 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2092 error = ENXIO; 2093 goto fail; 2094 } 2095 2096 bzero(sc->dc_ldata, sizeof(struct dc_list_data)); 2097 2098 ifp = &sc->arpcom.ac_if; 2099 ifp->if_softc = sc; 2100 ifp->if_unit = unit; 2101 ifp->if_name = "dc"; 2102 /* XXX: bleah, MTU gets overwritten in ether_ifattach() */ 2103 ifp->if_mtu = ETHERMTU; 2104 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2105 ifp->if_ioctl = dc_ioctl; 2106 ifp->if_output = ether_output; 2107 ifp->if_start = dc_start; 2108 ifp->if_watchdog = dc_watchdog; 2109 ifp->if_init = dc_init; 2110 ifp->if_baudrate = 10000000; 2111 ifp->if_snd.ifq_maxlen = DC_TX_LIST_CNT - 1; 2112 2113 /* 2114 * Do MII setup. If this is a 21143, check for a PHY on the 2115 * MII bus after applying any necessary fixups to twiddle the 2116 * GPIO bits. If we don't end up finding a PHY, restore the 2117 * old selection (SIA only or SIA/SYM) and attach the dcphy 2118 * driver instead. 2119 */ 2120 if (DC_IS_INTEL(sc)) { 2121 dc_apply_fixup(sc, IFM_AUTO); 2122 tmp = sc->dc_pmode; 2123 sc->dc_pmode = DC_PMODE_MII; 2124 } 2125 2126 error = mii_phy_probe(dev, &sc->dc_miibus, 2127 dc_ifmedia_upd, dc_ifmedia_sts); 2128 2129 if (error && DC_IS_INTEL(sc)) { 2130 sc->dc_pmode = tmp; 2131 if (sc->dc_pmode != DC_PMODE_SIA) 2132 sc->dc_pmode = DC_PMODE_SYM; 2133 sc->dc_flags |= DC_21143_NWAY; 2134 mii_phy_probe(dev, &sc->dc_miibus, 2135 dc_ifmedia_upd, dc_ifmedia_sts); 2136 /* 2137 * For non-MII cards, we need to have the 21143 2138 * drive the LEDs. Except there are some systems 2139 * like the NEC VersaPro NoteBook PC which have no 2140 * LEDs, and twiddling these bits has adverse effects 2141 * on them. (I.e. you suddenly can't get a link.) 2142 */ 2143 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033) 2144 sc->dc_flags |= DC_TULIP_LEDS; 2145 error = 0; 2146 } 2147 2148 if (error) { 2149 printf("dc%d: MII without any PHY!\n", sc->dc_unit); 2150 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2151 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2152 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2153 error = ENXIO; 2154 goto fail; 2155 } 2156 2157 if (DC_IS_XIRCOM(sc)) { 2158 /* 2159 * setup General Purpose Port mode and data so the tulip 2160 * can talk to the MII. 2161 */ 2162 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2163 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2164 DELAY(10); 2165 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2166 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2167 DELAY(10); 2168 } 2169 2170 /* 2171 * Call MI attach routine. 2172 */ 2173 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 2174 2175 /* 2176 * Tell the upper layer(s) we support long frames. 2177 */ 2178 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2179 2180 callout_init(&sc->dc_stat_ch, IS_MPSAFE); 2181 2182 #ifdef SRM_MEDIA 2183 sc->dc_srm_media = 0; 2184 2185 /* Remember the SRM console media setting */ 2186 if (DC_IS_INTEL(sc)) { 2187 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2188 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 2189 switch ((command >> 8) & 0xff) { 2190 case 3: 2191 sc->dc_srm_media = IFM_10_T; 2192 break; 2193 case 4: 2194 sc->dc_srm_media = IFM_10_T | IFM_FDX; 2195 break; 2196 case 5: 2197 sc->dc_srm_media = IFM_100_TX; 2198 break; 2199 case 6: 2200 sc->dc_srm_media = IFM_100_TX | IFM_FDX; 2201 break; 2202 } 2203 if (sc->dc_srm_media) 2204 sc->dc_srm_media |= IFM_ACTIVE | IFM_ETHER; 2205 } 2206 #endif 2207 2208 DC_UNLOCK(sc); 2209 return(0); 2210 2211 fail: 2212 DC_UNLOCK(sc); 2213 fail_nolock: 2214 mtx_destroy(&sc->dc_mtx); 2215 return(error); 2216 } 2217 2218 static int 2219 dc_detach(dev) 2220 device_t dev; 2221 { 2222 struct dc_softc *sc; 2223 struct ifnet *ifp; 2224 struct dc_mediainfo *m; 2225 2226 sc = device_get_softc(dev); 2227 2228 DC_LOCK(sc); 2229 2230 ifp = &sc->arpcom.ac_if; 2231 2232 dc_stop(sc); 2233 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 2234 2235 bus_generic_detach(dev); 2236 device_delete_child(dev, sc->dc_miibus); 2237 2238 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2239 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2240 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2241 2242 contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF); 2243 if (sc->dc_pnic_rx_buf != NULL) 2244 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2245 2246 while(sc->dc_mi != NULL) { 2247 m = sc->dc_mi->dc_next; 2248 free(sc->dc_mi, M_DEVBUF); 2249 sc->dc_mi = m; 2250 } 2251 2252 DC_UNLOCK(sc); 2253 mtx_destroy(&sc->dc_mtx); 2254 2255 return(0); 2256 } 2257 2258 /* 2259 * Initialize the transmit descriptors. 2260 */ 2261 static int 2262 dc_list_tx_init(sc) 2263 struct dc_softc *sc; 2264 { 2265 struct dc_chain_data *cd; 2266 struct dc_list_data *ld; 2267 int i, nexti; 2268 2269 cd = &sc->dc_cdata; 2270 ld = sc->dc_ldata; 2271 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2272 nexti = (i == (DC_TX_LIST_CNT - 1)) ? 0 : i+1; 2273 ld->dc_tx_list[i].dc_next = vtophys(&ld->dc_tx_list[nexti]); 2274 cd->dc_tx_chain[i] = NULL; 2275 ld->dc_tx_list[i].dc_data = 0; 2276 ld->dc_tx_list[i].dc_ctl = 0; 2277 } 2278 2279 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2280 2281 return(0); 2282 } 2283 2284 2285 /* 2286 * Initialize the RX descriptors and allocate mbufs for them. Note that 2287 * we arrange the descriptors in a closed ring, so that the last descriptor 2288 * points back to the first. 2289 */ 2290 static int 2291 dc_list_rx_init(sc) 2292 struct dc_softc *sc; 2293 { 2294 struct dc_chain_data *cd; 2295 struct dc_list_data *ld; 2296 int i, nexti; 2297 2298 cd = &sc->dc_cdata; 2299 ld = sc->dc_ldata; 2300 2301 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2302 if (dc_newbuf(sc, i, NULL) == ENOBUFS) 2303 return(ENOBUFS); 2304 nexti = (i == (DC_RX_LIST_CNT - 1)) ? 0 : i+1; 2305 ld->dc_rx_list[i].dc_next = vtophys(&ld->dc_rx_list[nexti]); 2306 } 2307 2308 cd->dc_rx_prod = 0; 2309 2310 return(0); 2311 } 2312 2313 /* 2314 * Initialize an RX descriptor and attach an MBUF cluster. 2315 */ 2316 static int 2317 dc_newbuf(sc, i, m) 2318 struct dc_softc *sc; 2319 int i; 2320 struct mbuf *m; 2321 { 2322 struct mbuf *m_new = NULL; 2323 struct dc_desc *c; 2324 2325 c = &sc->dc_ldata->dc_rx_list[i]; 2326 2327 if (m == NULL) { 2328 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 2329 if (m_new == NULL) 2330 return(ENOBUFS); 2331 2332 MCLGET(m_new, M_DONTWAIT); 2333 if (!(m_new->m_flags & M_EXT)) { 2334 m_freem(m_new); 2335 return(ENOBUFS); 2336 } 2337 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2338 } else { 2339 m_new = m; 2340 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2341 m_new->m_data = m_new->m_ext.ext_buf; 2342 } 2343 2344 m_adj(m_new, sizeof(u_int64_t)); 2345 2346 /* 2347 * If this is a PNIC chip, zero the buffer. This is part 2348 * of the workaround for the receive bug in the 82c168 and 2349 * 82c169 chips. 2350 */ 2351 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2352 bzero((char *)mtod(m_new, char *), m_new->m_len); 2353 2354 sc->dc_cdata.dc_rx_chain[i] = m_new; 2355 c->dc_data = vtophys(mtod(m_new, caddr_t)); 2356 c->dc_ctl = DC_RXCTL_RLINK | DC_RXLEN; 2357 c->dc_status = DC_RXSTAT_OWN; 2358 2359 return(0); 2360 } 2361 2362 /* 2363 * Grrrrr. 2364 * The PNIC chip has a terrible bug in it that manifests itself during 2365 * periods of heavy activity. The exact mode of failure if difficult to 2366 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2367 * will happen on slow machines. The bug is that sometimes instead of 2368 * uploading one complete frame during reception, it uploads what looks 2369 * like the entire contents of its FIFO memory. The frame we want is at 2370 * the end of the whole mess, but we never know exactly how much data has 2371 * been uploaded, so salvaging the frame is hard. 2372 * 2373 * There is only one way to do it reliably, and it's disgusting. 2374 * Here's what we know: 2375 * 2376 * - We know there will always be somewhere between one and three extra 2377 * descriptors uploaded. 2378 * 2379 * - We know the desired received frame will always be at the end of the 2380 * total data upload. 2381 * 2382 * - We know the size of the desired received frame because it will be 2383 * provided in the length field of the status word in the last descriptor. 2384 * 2385 * Here's what we do: 2386 * 2387 * - When we allocate buffers for the receive ring, we bzero() them. 2388 * This means that we know that the buffer contents should be all 2389 * zeros, except for data uploaded by the chip. 2390 * 2391 * - We also force the PNIC chip to upload frames that include the 2392 * ethernet CRC at the end. 2393 * 2394 * - We gather all of the bogus frame data into a single buffer. 2395 * 2396 * - We then position a pointer at the end of this buffer and scan 2397 * backwards until we encounter the first non-zero byte of data. 2398 * This is the end of the received frame. We know we will encounter 2399 * some data at the end of the frame because the CRC will always be 2400 * there, so even if the sender transmits a packet of all zeros, 2401 * we won't be fooled. 2402 * 2403 * - We know the size of the actual received frame, so we subtract 2404 * that value from the current pointer location. This brings us 2405 * to the start of the actual received packet. 2406 * 2407 * - We copy this into an mbuf and pass it on, along with the actual 2408 * frame length. 2409 * 2410 * The performance hit is tremendous, but it beats dropping frames all 2411 * the time. 2412 */ 2413 2414 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG) 2415 static void 2416 dc_pnic_rx_bug_war(sc, idx) 2417 struct dc_softc *sc; 2418 int idx; 2419 { 2420 struct dc_desc *cur_rx; 2421 struct dc_desc *c = NULL; 2422 struct mbuf *m = NULL; 2423 unsigned char *ptr; 2424 int i, total_len; 2425 u_int32_t rxstat = 0; 2426 2427 i = sc->dc_pnic_rx_bug_save; 2428 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2429 ptr = sc->dc_pnic_rx_buf; 2430 bzero(ptr, sizeof(DC_RXLEN * 5)); 2431 2432 /* Copy all the bytes from the bogus buffers. */ 2433 while (1) { 2434 c = &sc->dc_ldata->dc_rx_list[i]; 2435 rxstat = c->dc_status; 2436 m = sc->dc_cdata.dc_rx_chain[i]; 2437 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2438 ptr += DC_RXLEN; 2439 /* If this is the last buffer, break out. */ 2440 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2441 break; 2442 dc_newbuf(sc, i, m); 2443 DC_INC(i, DC_RX_LIST_CNT); 2444 } 2445 2446 /* Find the length of the actual receive frame. */ 2447 total_len = DC_RXBYTES(rxstat); 2448 2449 /* Scan backwards until we hit a non-zero byte. */ 2450 while(*ptr == 0x00) 2451 ptr--; 2452 2453 /* Round off. */ 2454 if ((uintptr_t)(ptr) & 0x3) 2455 ptr -= 1; 2456 2457 /* Now find the start of the frame. */ 2458 ptr -= total_len; 2459 if (ptr < sc->dc_pnic_rx_buf) 2460 ptr = sc->dc_pnic_rx_buf; 2461 2462 /* 2463 * Now copy the salvaged frame to the last mbuf and fake up 2464 * the status word to make it look like a successful 2465 * frame reception. 2466 */ 2467 dc_newbuf(sc, i, m); 2468 bcopy(ptr, mtod(m, char *), total_len); 2469 cur_rx->dc_status = rxstat | DC_RXSTAT_FIRSTFRAG; 2470 2471 return; 2472 } 2473 2474 /* 2475 * This routine searches the RX ring for dirty descriptors in the 2476 * event that the rxeof routine falls out of sync with the chip's 2477 * current descriptor pointer. This may happen sometimes as a result 2478 * of a "no RX buffer available" condition that happens when the chip 2479 * consumes all of the RX buffers before the driver has a chance to 2480 * process the RX ring. This routine may need to be called more than 2481 * once to bring the driver back in sync with the chip, however we 2482 * should still be getting RX DONE interrupts to drive the search 2483 * for new packets in the RX ring, so we should catch up eventually. 2484 */ 2485 static int 2486 dc_rx_resync(sc) 2487 struct dc_softc *sc; 2488 { 2489 int i, pos; 2490 struct dc_desc *cur_rx; 2491 2492 pos = sc->dc_cdata.dc_rx_prod; 2493 2494 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2495 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2496 if (!(cur_rx->dc_status & DC_RXSTAT_OWN)) 2497 break; 2498 DC_INC(pos, DC_RX_LIST_CNT); 2499 } 2500 2501 /* If the ring really is empty, then just return. */ 2502 if (i == DC_RX_LIST_CNT) 2503 return(0); 2504 2505 /* We've fallen behing the chip: catch it. */ 2506 sc->dc_cdata.dc_rx_prod = pos; 2507 2508 return(EAGAIN); 2509 } 2510 2511 /* 2512 * A frame has been uploaded: pass the resulting mbuf chain up to 2513 * the higher level protocols. 2514 */ 2515 static void 2516 dc_rxeof(sc) 2517 struct dc_softc *sc; 2518 { 2519 struct ether_header *eh; 2520 struct mbuf *m; 2521 struct ifnet *ifp; 2522 struct dc_desc *cur_rx; 2523 int i, total_len = 0; 2524 u_int32_t rxstat; 2525 2526 ifp = &sc->arpcom.ac_if; 2527 i = sc->dc_cdata.dc_rx_prod; 2528 2529 while(!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) { 2530 2531 #ifdef DEVICE_POLLING 2532 if (ifp->if_flags & IFF_POLLING) { 2533 if (sc->rxcycles <= 0) 2534 break; 2535 sc->rxcycles--; 2536 } 2537 #endif /* DEVICE_POLLING */ 2538 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2539 rxstat = cur_rx->dc_status; 2540 m = sc->dc_cdata.dc_rx_chain[i]; 2541 total_len = DC_RXBYTES(rxstat); 2542 2543 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2544 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2545 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2546 sc->dc_pnic_rx_bug_save = i; 2547 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2548 DC_INC(i, DC_RX_LIST_CNT); 2549 continue; 2550 } 2551 dc_pnic_rx_bug_war(sc, i); 2552 rxstat = cur_rx->dc_status; 2553 total_len = DC_RXBYTES(rxstat); 2554 } 2555 } 2556 2557 sc->dc_cdata.dc_rx_chain[i] = NULL; 2558 2559 /* 2560 * If an error occurs, update stats, clear the 2561 * status word and leave the mbuf cluster in place: 2562 * it should simply get re-used next time this descriptor 2563 * comes up in the ring. However, don't report long 2564 * frames as errors since they could be vlans 2565 */ 2566 if ((rxstat & DC_RXSTAT_RXERR)){ 2567 if (!(rxstat & DC_RXSTAT_GIANT) || 2568 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2569 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2570 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2571 ifp->if_ierrors++; 2572 if (rxstat & DC_RXSTAT_COLLSEEN) 2573 ifp->if_collisions++; 2574 dc_newbuf(sc, i, m); 2575 if (rxstat & DC_RXSTAT_CRCERR) { 2576 DC_INC(i, DC_RX_LIST_CNT); 2577 continue; 2578 } else { 2579 dc_init(sc); 2580 return; 2581 } 2582 } 2583 } 2584 2585 /* No errors; receive the packet. */ 2586 total_len -= ETHER_CRC_LEN; 2587 #ifdef __i386__ 2588 /* 2589 * On the x86 we do not have alignment problems, so try to 2590 * allocate a new buffer for the receive ring, and pass up 2591 * the one where the packet is already, saving the expensive 2592 * copy done in m_devget(). 2593 * If we are on an architecture with alignment problems, or 2594 * if the allocation fails, then use m_devget and leave the 2595 * existing buffer in the receive ring. 2596 */ 2597 if (dc_quick && dc_newbuf(sc, i, NULL) == 0) { 2598 m->m_pkthdr.rcvif = ifp; 2599 m->m_pkthdr.len = m->m_len = total_len; 2600 DC_INC(i, DC_RX_LIST_CNT); 2601 } else 2602 #endif 2603 { 2604 struct mbuf *m0; 2605 2606 m0 = m_devget(mtod(m, char *), total_len, 2607 ETHER_ALIGN, ifp, NULL); 2608 dc_newbuf(sc, i, m); 2609 DC_INC(i, DC_RX_LIST_CNT); 2610 if (m0 == NULL) { 2611 ifp->if_ierrors++; 2612 continue; 2613 } 2614 m = m0; 2615 } 2616 2617 ifp->if_ipackets++; 2618 eh = mtod(m, struct ether_header *); 2619 2620 /* Remove header from mbuf and pass it on. */ 2621 m_adj(m, sizeof(struct ether_header)); 2622 ether_input(ifp, eh, m); 2623 } 2624 2625 sc->dc_cdata.dc_rx_prod = i; 2626 } 2627 2628 /* 2629 * A frame was downloaded to the chip. It's safe for us to clean up 2630 * the list buffers. 2631 */ 2632 2633 static void 2634 dc_txeof(sc) 2635 struct dc_softc *sc; 2636 { 2637 struct dc_desc *cur_tx = NULL; 2638 struct ifnet *ifp; 2639 int idx; 2640 2641 ifp = &sc->arpcom.ac_if; 2642 2643 /* 2644 * Go through our tx list and free mbufs for those 2645 * frames that have been transmitted. 2646 */ 2647 idx = sc->dc_cdata.dc_tx_cons; 2648 while(idx != sc->dc_cdata.dc_tx_prod) { 2649 u_int32_t txstat; 2650 2651 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2652 txstat = cur_tx->dc_status; 2653 2654 if (txstat & DC_TXSTAT_OWN) 2655 break; 2656 2657 if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) || 2658 cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2659 if (cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2660 /* 2661 * Yes, the PNIC is so brain damaged 2662 * that it will sometimes generate a TX 2663 * underrun error while DMAing the RX 2664 * filter setup frame. If we detect this, 2665 * we have to send the setup frame again, 2666 * or else the filter won't be programmed 2667 * correctly. 2668 */ 2669 if (DC_IS_PNIC(sc)) { 2670 if (txstat & DC_TXSTAT_ERRSUM) 2671 dc_setfilt(sc); 2672 } 2673 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2674 } 2675 sc->dc_cdata.dc_tx_cnt--; 2676 DC_INC(idx, DC_TX_LIST_CNT); 2677 continue; 2678 } 2679 2680 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) { 2681 /* 2682 * XXX: Why does my Xircom taunt me so? 2683 * For some reason it likes setting the CARRLOST flag 2684 * even when the carrier is there. wtf?!? 2685 * Who knows, but Conexant chips have the 2686 * same problem. Maybe they took lessons 2687 * from Xircom. 2688 */ 2689 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2690 sc->dc_pmode == DC_PMODE_MII && 2691 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2692 DC_TXSTAT_NOCARRIER))) 2693 txstat &= ~DC_TXSTAT_ERRSUM; 2694 } else { 2695 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2696 sc->dc_pmode == DC_PMODE_MII && 2697 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2698 DC_TXSTAT_NOCARRIER|DC_TXSTAT_CARRLOST))) 2699 txstat &= ~DC_TXSTAT_ERRSUM; 2700 } 2701 2702 if (txstat & DC_TXSTAT_ERRSUM) { 2703 ifp->if_oerrors++; 2704 if (txstat & DC_TXSTAT_EXCESSCOLL) 2705 ifp->if_collisions++; 2706 if (txstat & DC_TXSTAT_LATECOLL) 2707 ifp->if_collisions++; 2708 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2709 dc_init(sc); 2710 return; 2711 } 2712 } 2713 2714 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2715 2716 ifp->if_opackets++; 2717 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2718 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2719 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2720 } 2721 2722 sc->dc_cdata.dc_tx_cnt--; 2723 DC_INC(idx, DC_TX_LIST_CNT); 2724 } 2725 2726 if (idx != sc->dc_cdata.dc_tx_cons) { 2727 /* some buffers have been freed */ 2728 sc->dc_cdata.dc_tx_cons = idx; 2729 ifp->if_flags &= ~IFF_OACTIVE; 2730 } 2731 ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5; 2732 2733 return; 2734 } 2735 2736 static void 2737 dc_tick(xsc) 2738 void *xsc; 2739 { 2740 struct dc_softc *sc; 2741 struct mii_data *mii; 2742 struct ifnet *ifp; 2743 u_int32_t r; 2744 2745 sc = xsc; 2746 DC_LOCK(sc); 2747 ifp = &sc->arpcom.ac_if; 2748 mii = device_get_softc(sc->dc_miibus); 2749 2750 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2751 if (sc->dc_flags & DC_21143_NWAY) { 2752 r = CSR_READ_4(sc, DC_10BTSTAT); 2753 if (IFM_SUBTYPE(mii->mii_media_active) == 2754 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2755 sc->dc_link = 0; 2756 mii_mediachg(mii); 2757 } 2758 if (IFM_SUBTYPE(mii->mii_media_active) == 2759 IFM_10_T && (r & DC_TSTAT_LS10)) { 2760 sc->dc_link = 0; 2761 mii_mediachg(mii); 2762 } 2763 if (sc->dc_link == 0) 2764 mii_tick(mii); 2765 } else { 2766 r = CSR_READ_4(sc, DC_ISR); 2767 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2768 sc->dc_cdata.dc_tx_cnt == 0) 2769 mii_tick(mii); 2770 if (!(mii->mii_media_status & IFM_ACTIVE)) 2771 sc->dc_link = 0; 2772 } 2773 } else 2774 mii_tick(mii); 2775 2776 /* 2777 * When the init routine completes, we expect to be able to send 2778 * packets right away, and in fact the network code will send a 2779 * gratuitous ARP the moment the init routine marks the interface 2780 * as running. However, even though the MAC may have been initialized, 2781 * there may be a delay of a few seconds before the PHY completes 2782 * autonegotiation and the link is brought up. Any transmissions 2783 * made during that delay will be lost. Dealing with this is tricky: 2784 * we can't just pause in the init routine while waiting for the 2785 * PHY to come ready since that would bring the whole system to 2786 * a screeching halt for several seconds. 2787 * 2788 * What we do here is prevent the TX start routine from sending 2789 * any packets until a link has been established. After the 2790 * interface has been initialized, the tick routine will poll 2791 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2792 * that time, packets will stay in the send queue, and once the 2793 * link comes up, they will be flushed out to the wire. 2794 */ 2795 if (!sc->dc_link && mii->mii_media_status & IFM_ACTIVE && 2796 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2797 sc->dc_link++; 2798 if (ifp->if_snd.ifq_head != NULL) 2799 dc_start(ifp); 2800 } 2801 2802 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 2803 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 2804 else 2805 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 2806 2807 DC_UNLOCK(sc); 2808 2809 return; 2810 } 2811 2812 /* 2813 * A transmit underrun has occurred. Back off the transmit threshold, 2814 * or switch to store and forward mode if we have to. 2815 */ 2816 static void 2817 dc_tx_underrun(sc) 2818 struct dc_softc *sc; 2819 { 2820 u_int32_t isr; 2821 int i; 2822 2823 if (DC_IS_DAVICOM(sc)) 2824 dc_init(sc); 2825 2826 if (DC_IS_INTEL(sc)) { 2827 /* 2828 * The real 21143 requires that the transmitter be idle 2829 * in order to change the transmit threshold or store 2830 * and forward state. 2831 */ 2832 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2833 2834 for (i = 0; i < DC_TIMEOUT; i++) { 2835 isr = CSR_READ_4(sc, DC_ISR); 2836 if (isr & DC_ISR_TX_IDLE) 2837 break; 2838 DELAY(10); 2839 } 2840 if (i == DC_TIMEOUT) { 2841 printf("dc%d: failed to force tx to idle state\n", 2842 sc->dc_unit); 2843 dc_init(sc); 2844 } 2845 } 2846 2847 printf("dc%d: TX underrun -- ", sc->dc_unit); 2848 sc->dc_txthresh += DC_TXTHRESH_INC; 2849 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 2850 printf("using store and forward mode\n"); 2851 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2852 } else { 2853 printf("increasing TX threshold\n"); 2854 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 2855 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2856 } 2857 2858 if (DC_IS_INTEL(sc)) 2859 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2860 2861 return; 2862 } 2863 2864 #ifdef DEVICE_POLLING 2865 static poll_handler_t dc_poll; 2866 2867 static void 2868 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2869 { 2870 struct dc_softc *sc = ifp->if_softc; 2871 2872 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 2873 /* Re-enable interrupts. */ 2874 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2875 return; 2876 } 2877 sc->rxcycles = count; 2878 dc_rxeof(sc); 2879 dc_txeof(sc); 2880 if (ifp->if_snd.ifq_head != NULL && !(ifp->if_flags & IFF_OACTIVE)) 2881 dc_start(ifp); 2882 2883 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2884 u_int32_t status; 2885 2886 status = CSR_READ_4(sc, DC_ISR); 2887 status &= (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF| 2888 DC_ISR_TX_NOBUF|DC_ISR_TX_IDLE|DC_ISR_TX_UNDERRUN| 2889 DC_ISR_BUS_ERR); 2890 if (!status) 2891 return; 2892 /* ack what we have */ 2893 CSR_WRITE_4(sc, DC_ISR, status); 2894 2895 if (status & (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF)) { 2896 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 2897 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 2898 2899 if (dc_rx_resync(sc)) 2900 dc_rxeof(sc); 2901 } 2902 /* restart transmit unit if necessary */ 2903 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 2904 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2905 2906 if (status & DC_ISR_TX_UNDERRUN) 2907 dc_tx_underrun(sc); 2908 2909 if (status & DC_ISR_BUS_ERR) { 2910 printf("dc_poll: dc%d bus error\n", sc->dc_unit); 2911 dc_reset(sc); 2912 dc_init(sc); 2913 } 2914 } 2915 } 2916 #endif /* DEVICE_POLLING */ 2917 2918 static void 2919 dc_intr(arg) 2920 void *arg; 2921 { 2922 struct dc_softc *sc; 2923 struct ifnet *ifp; 2924 u_int32_t status; 2925 2926 sc = arg; 2927 2928 if (sc->suspended) { 2929 return; 2930 } 2931 2932 if ((CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) 2933 return; 2934 2935 DC_LOCK(sc); 2936 ifp = &sc->arpcom.ac_if; 2937 #ifdef DEVICE_POLLING 2938 if (ifp->if_flags & IFF_POLLING) 2939 goto done; 2940 if (ether_poll_register(dc_poll, ifp)) { /* ok, disable interrupts */ 2941 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2942 goto done; 2943 } 2944 #endif /* DEVICE_POLLING */ 2945 2946 /* Suppress unwanted interrupts */ 2947 if (!(ifp->if_flags & IFF_UP)) { 2948 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 2949 dc_stop(sc); 2950 DC_UNLOCK(sc); 2951 return; 2952 } 2953 2954 /* Disable interrupts. */ 2955 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2956 2957 while(((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) 2958 && status != 0xFFFFFFFF) { 2959 2960 CSR_WRITE_4(sc, DC_ISR, status); 2961 2962 if (status & DC_ISR_RX_OK) { 2963 int curpkts; 2964 curpkts = ifp->if_ipackets; 2965 dc_rxeof(sc); 2966 if (curpkts == ifp->if_ipackets) { 2967 while(dc_rx_resync(sc)) 2968 dc_rxeof(sc); 2969 } 2970 } 2971 2972 if (status & (DC_ISR_TX_OK|DC_ISR_TX_NOBUF)) 2973 dc_txeof(sc); 2974 2975 if (status & DC_ISR_TX_IDLE) { 2976 dc_txeof(sc); 2977 if (sc->dc_cdata.dc_tx_cnt) { 2978 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2979 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2980 } 2981 } 2982 2983 if (status & DC_ISR_TX_UNDERRUN) 2984 dc_tx_underrun(sc); 2985 2986 if ((status & DC_ISR_RX_WATDOGTIMEO) 2987 || (status & DC_ISR_RX_NOBUF)) { 2988 int curpkts; 2989 curpkts = ifp->if_ipackets; 2990 dc_rxeof(sc); 2991 if (curpkts == ifp->if_ipackets) { 2992 while(dc_rx_resync(sc)) 2993 dc_rxeof(sc); 2994 } 2995 } 2996 2997 if (status & DC_ISR_BUS_ERR) { 2998 dc_reset(sc); 2999 dc_init(sc); 3000 } 3001 } 3002 3003 /* Re-enable interrupts. */ 3004 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3005 3006 if (ifp->if_snd.ifq_head != NULL) 3007 dc_start(ifp); 3008 3009 #ifdef DEVICE_POLLING 3010 done: 3011 #endif /* DEVICE_POLLING */ 3012 3013 DC_UNLOCK(sc); 3014 3015 return; 3016 } 3017 3018 /* 3019 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 3020 * pointers to the fragment pointers. 3021 */ 3022 static int 3023 dc_encap(sc, m_head, txidx) 3024 struct dc_softc *sc; 3025 struct mbuf *m_head; 3026 u_int32_t *txidx; 3027 { 3028 struct dc_desc *f = NULL; 3029 struct mbuf *m; 3030 int frag, cur, cnt = 0; 3031 3032 /* 3033 * Start packing the mbufs in this chain into 3034 * the fragment pointers. Stop when we run out 3035 * of fragments or hit the end of the mbuf chain. 3036 */ 3037 m = m_head; 3038 cur = frag = *txidx; 3039 3040 for (m = m_head; m != NULL; m = m->m_next) { 3041 if (m->m_len != 0) { 3042 if (sc->dc_flags & DC_TX_ADMTEK_WAR) { 3043 if (*txidx != sc->dc_cdata.dc_tx_prod && 3044 frag == (DC_TX_LIST_CNT - 1)) 3045 return(ENOBUFS); 3046 } 3047 if ((DC_TX_LIST_CNT - 3048 (sc->dc_cdata.dc_tx_cnt + cnt)) < 5) 3049 return(ENOBUFS); 3050 3051 f = &sc->dc_ldata->dc_tx_list[frag]; 3052 f->dc_ctl = DC_TXCTL_TLINK | m->m_len; 3053 if (cnt == 0) { 3054 f->dc_status = 0; 3055 f->dc_ctl |= DC_TXCTL_FIRSTFRAG; 3056 } else 3057 f->dc_status = DC_TXSTAT_OWN; 3058 f->dc_data = vtophys(mtod(m, vm_offset_t)); 3059 cur = frag; 3060 DC_INC(frag, DC_TX_LIST_CNT); 3061 cnt++; 3062 } 3063 } 3064 3065 if (m != NULL) 3066 return(ENOBUFS); 3067 3068 sc->dc_cdata.dc_tx_cnt += cnt; 3069 sc->dc_cdata.dc_tx_chain[cur] = m_head; 3070 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_LASTFRAG; 3071 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 3072 sc->dc_ldata->dc_tx_list[*txidx].dc_ctl |= DC_TXCTL_FINT; 3073 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 3074 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 3075 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 3076 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 3077 sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN; 3078 *txidx = frag; 3079 3080 return(0); 3081 } 3082 3083 /* 3084 * Coalesce an mbuf chain into a single mbuf cluster buffer. 3085 * Needed for some really badly behaved chips that just can't 3086 * do scatter/gather correctly. 3087 */ 3088 static int 3089 dc_coal(sc, m_head) 3090 struct dc_softc *sc; 3091 struct mbuf **m_head; 3092 { 3093 struct mbuf *m_new, *m; 3094 3095 m = *m_head; 3096 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 3097 if (m_new == NULL) 3098 return(ENOBUFS); 3099 if (m->m_pkthdr.len > MHLEN) { 3100 MCLGET(m_new, M_DONTWAIT); 3101 if (!(m_new->m_flags & M_EXT)) { 3102 m_freem(m_new); 3103 return(ENOBUFS); 3104 } 3105 } 3106 m_copydata(m, 0, m->m_pkthdr.len, mtod(m_new, caddr_t)); 3107 m_new->m_pkthdr.len = m_new->m_len = m->m_pkthdr.len; 3108 m_freem(m); 3109 *m_head = m_new; 3110 3111 return(0); 3112 } 3113 3114 /* 3115 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3116 * to the mbuf data regions directly in the transmit lists. We also save a 3117 * copy of the pointers since the transmit list fragment pointers are 3118 * physical addresses. 3119 */ 3120 3121 static void 3122 dc_start(ifp) 3123 struct ifnet *ifp; 3124 { 3125 struct dc_softc *sc; 3126 struct mbuf *m_head = NULL; 3127 int idx; 3128 3129 sc = ifp->if_softc; 3130 3131 DC_LOCK(sc); 3132 3133 if (!sc->dc_link && ifp->if_snd.ifq_len < 10) { 3134 DC_UNLOCK(sc); 3135 return; 3136 } 3137 3138 if (ifp->if_flags & IFF_OACTIVE) { 3139 DC_UNLOCK(sc); 3140 return; 3141 } 3142 3143 idx = sc->dc_cdata.dc_tx_prod; 3144 3145 while(sc->dc_cdata.dc_tx_chain[idx] == NULL) { 3146 IF_DEQUEUE(&ifp->if_snd, m_head); 3147 if (m_head == NULL) 3148 break; 3149 3150 if (sc->dc_flags & DC_TX_COALESCE && 3151 (m_head->m_next != NULL || 3152 sc->dc_flags & DC_TX_ALIGN)) { 3153 if (dc_coal(sc, &m_head)) { 3154 IF_PREPEND(&ifp->if_snd, m_head); 3155 ifp->if_flags |= IFF_OACTIVE; 3156 break; 3157 } 3158 } 3159 3160 if (dc_encap(sc, m_head, &idx)) { 3161 IF_PREPEND(&ifp->if_snd, m_head); 3162 ifp->if_flags |= IFF_OACTIVE; 3163 break; 3164 } 3165 3166 /* 3167 * If there's a BPF listener, bounce a copy of this frame 3168 * to him. 3169 */ 3170 if (ifp->if_bpf) 3171 bpf_mtap(ifp, m_head); 3172 3173 if (sc->dc_flags & DC_TX_ONE) { 3174 ifp->if_flags |= IFF_OACTIVE; 3175 break; 3176 } 3177 } 3178 3179 /* Transmit */ 3180 sc->dc_cdata.dc_tx_prod = idx; 3181 if (!(sc->dc_flags & DC_TX_POLL)) 3182 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3183 3184 /* 3185 * Set a timeout in case the chip goes out to lunch. 3186 */ 3187 ifp->if_timer = 5; 3188 3189 DC_UNLOCK(sc); 3190 3191 return; 3192 } 3193 3194 static void 3195 dc_init(xsc) 3196 void *xsc; 3197 { 3198 struct dc_softc *sc = xsc; 3199 struct ifnet *ifp = &sc->arpcom.ac_if; 3200 struct mii_data *mii; 3201 3202 DC_LOCK(sc); 3203 3204 mii = device_get_softc(sc->dc_miibus); 3205 3206 /* 3207 * Cancel pending I/O and free all RX/TX buffers. 3208 */ 3209 dc_stop(sc); 3210 dc_reset(sc); 3211 3212 /* 3213 * Set cache alignment and burst length. 3214 */ 3215 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 3216 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3217 else 3218 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE); 3219 /* 3220 * Evenly share the bus between receive and transmit process. 3221 */ 3222 if (DC_IS_INTEL(sc)) 3223 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3224 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3225 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3226 } else { 3227 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3228 } 3229 if (sc->dc_flags & DC_TX_POLL) 3230 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3231 switch(sc->dc_cachesize) { 3232 case 32: 3233 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3234 break; 3235 case 16: 3236 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3237 break; 3238 case 8: 3239 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3240 break; 3241 case 0: 3242 default: 3243 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3244 break; 3245 } 3246 3247 if (sc->dc_flags & DC_TX_STORENFWD) 3248 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3249 else { 3250 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3251 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3252 } else { 3253 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3254 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3255 } 3256 } 3257 3258 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3259 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3260 3261 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3262 /* 3263 * The app notes for the 98713 and 98715A say that 3264 * in order to have the chips operate properly, a magic 3265 * number must be written to CSR16. Macronix does not 3266 * document the meaning of these bits so there's no way 3267 * to know exactly what they do. The 98713 has a magic 3268 * number all its own; the rest all use a different one. 3269 */ 3270 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3271 if (sc->dc_type == DC_TYPE_98713) 3272 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3273 else 3274 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3275 } 3276 3277 if (DC_IS_XIRCOM(sc)) { 3278 /* 3279 * setup General Purpose Port mode and data so the tulip 3280 * can talk to the MII. 3281 */ 3282 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3283 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3284 DELAY(10); 3285 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3286 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3287 DELAY(10); 3288 } 3289 3290 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3291 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3292 3293 /* Init circular RX list. */ 3294 if (dc_list_rx_init(sc) == ENOBUFS) { 3295 printf("dc%d: initialization failed: no " 3296 "memory for rx buffers\n", sc->dc_unit); 3297 dc_stop(sc); 3298 DC_UNLOCK(sc); 3299 return; 3300 } 3301 3302 /* 3303 * Init tx descriptors. 3304 */ 3305 dc_list_tx_init(sc); 3306 3307 /* 3308 * Load the address of the RX list. 3309 */ 3310 CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0])); 3311 CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0])); 3312 3313 /* 3314 * Enable interrupts. 3315 */ 3316 #ifdef DEVICE_POLLING 3317 /* 3318 * ... but only if we are not polling, and make sure they are off in 3319 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3320 * after a reset. 3321 */ 3322 if (ifp->if_flags & IFF_POLLING) 3323 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3324 else 3325 #endif 3326 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3327 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3328 3329 /* Enable transmitter. */ 3330 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3331 3332 /* 3333 * If this is an Intel 21143 and we're not using the 3334 * MII port, program the LED control pins so we get 3335 * link and activity indications. 3336 */ 3337 if (sc->dc_flags & DC_TULIP_LEDS) { 3338 CSR_WRITE_4(sc, DC_WATCHDOG, 3339 DC_WDOG_CTLWREN|DC_WDOG_LINK|DC_WDOG_ACTIVITY); 3340 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3341 } 3342 3343 /* 3344 * Load the RX/multicast filter. We do this sort of late 3345 * because the filter programming scheme on the 21143 and 3346 * some clones requires DMAing a setup frame via the TX 3347 * engine, and we need the transmitter enabled for that. 3348 */ 3349 dc_setfilt(sc); 3350 3351 /* Enable receiver. */ 3352 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3353 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3354 3355 mii_mediachg(mii); 3356 dc_setcfg(sc, sc->dc_if_media); 3357 3358 ifp->if_flags |= IFF_RUNNING; 3359 ifp->if_flags &= ~IFF_OACTIVE; 3360 3361 /* Don't start the ticker if this is a homePNA link. */ 3362 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) 3363 sc->dc_link = 1; 3364 else { 3365 if (sc->dc_flags & DC_21143_NWAY) 3366 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3367 else 3368 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3369 } 3370 3371 #ifdef SRM_MEDIA 3372 if(sc->dc_srm_media) { 3373 struct ifreq ifr; 3374 3375 ifr.ifr_media = sc->dc_srm_media; 3376 ifmedia_ioctl(ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA); 3377 sc->dc_srm_media = 0; 3378 } 3379 #endif 3380 DC_UNLOCK(sc); 3381 return; 3382 } 3383 3384 /* 3385 * Set media options. 3386 */ 3387 static int 3388 dc_ifmedia_upd(ifp) 3389 struct ifnet *ifp; 3390 { 3391 struct dc_softc *sc; 3392 struct mii_data *mii; 3393 struct ifmedia *ifm; 3394 3395 sc = ifp->if_softc; 3396 mii = device_get_softc(sc->dc_miibus); 3397 mii_mediachg(mii); 3398 ifm = &mii->mii_media; 3399 3400 if (DC_IS_DAVICOM(sc) && 3401 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) 3402 dc_setcfg(sc, ifm->ifm_media); 3403 else 3404 sc->dc_link = 0; 3405 3406 return(0); 3407 } 3408 3409 /* 3410 * Report current media status. 3411 */ 3412 static void 3413 dc_ifmedia_sts(ifp, ifmr) 3414 struct ifnet *ifp; 3415 struct ifmediareq *ifmr; 3416 { 3417 struct dc_softc *sc; 3418 struct mii_data *mii; 3419 struct ifmedia *ifm; 3420 3421 sc = ifp->if_softc; 3422 mii = device_get_softc(sc->dc_miibus); 3423 mii_pollstat(mii); 3424 ifm = &mii->mii_media; 3425 if (DC_IS_DAVICOM(sc)) { 3426 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 3427 ifmr->ifm_active = ifm->ifm_media; 3428 ifmr->ifm_status = 0; 3429 return; 3430 } 3431 } 3432 ifmr->ifm_active = mii->mii_media_active; 3433 ifmr->ifm_status = mii->mii_media_status; 3434 3435 return; 3436 } 3437 3438 static int 3439 dc_ioctl(ifp, command, data) 3440 struct ifnet *ifp; 3441 u_long command; 3442 caddr_t data; 3443 { 3444 struct dc_softc *sc = ifp->if_softc; 3445 struct ifreq *ifr = (struct ifreq *) data; 3446 struct mii_data *mii; 3447 int error = 0; 3448 3449 DC_LOCK(sc); 3450 3451 switch(command) { 3452 case SIOCSIFADDR: 3453 case SIOCGIFADDR: 3454 case SIOCSIFMTU: 3455 error = ether_ioctl(ifp, command, data); 3456 break; 3457 case SIOCSIFFLAGS: 3458 if (ifp->if_flags & IFF_UP) { 3459 if (ifp->if_flags & IFF_RUNNING && 3460 ifp->if_flags & IFF_PROMISC && 3461 !(sc->dc_if_flags & IFF_PROMISC)) { 3462 dc_setfilt(sc); 3463 } else if (ifp->if_flags & IFF_RUNNING && 3464 !(ifp->if_flags & IFF_PROMISC) && 3465 sc->dc_if_flags & IFF_PROMISC) { 3466 dc_setfilt(sc); 3467 } else if (!(ifp->if_flags & IFF_RUNNING)) { 3468 sc->dc_txthresh = 0; 3469 dc_init(sc); 3470 } 3471 } else { 3472 if (ifp->if_flags & IFF_RUNNING) 3473 dc_stop(sc); 3474 } 3475 sc->dc_if_flags = ifp->if_flags; 3476 error = 0; 3477 break; 3478 case SIOCADDMULTI: 3479 case SIOCDELMULTI: 3480 dc_setfilt(sc); 3481 error = 0; 3482 break; 3483 case SIOCGIFMEDIA: 3484 case SIOCSIFMEDIA: 3485 mii = device_get_softc(sc->dc_miibus); 3486 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3487 #ifdef SRM_MEDIA 3488 if (sc->dc_srm_media) 3489 sc->dc_srm_media = 0; 3490 #endif 3491 break; 3492 default: 3493 error = EINVAL; 3494 break; 3495 } 3496 3497 DC_UNLOCK(sc); 3498 3499 return(error); 3500 } 3501 3502 static void 3503 dc_watchdog(ifp) 3504 struct ifnet *ifp; 3505 { 3506 struct dc_softc *sc; 3507 3508 sc = ifp->if_softc; 3509 3510 DC_LOCK(sc); 3511 3512 ifp->if_oerrors++; 3513 printf("dc%d: watchdog timeout\n", sc->dc_unit); 3514 3515 dc_stop(sc); 3516 dc_reset(sc); 3517 dc_init(sc); 3518 3519 if (ifp->if_snd.ifq_head != NULL) 3520 dc_start(ifp); 3521 3522 DC_UNLOCK(sc); 3523 3524 return; 3525 } 3526 3527 /* 3528 * Stop the adapter and free any mbufs allocated to the 3529 * RX and TX lists. 3530 */ 3531 static void 3532 dc_stop(sc) 3533 struct dc_softc *sc; 3534 { 3535 register int i; 3536 struct ifnet *ifp; 3537 3538 DC_LOCK(sc); 3539 3540 ifp = &sc->arpcom.ac_if; 3541 ifp->if_timer = 0; 3542 3543 callout_stop(&sc->dc_stat_ch); 3544 3545 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3546 #ifdef DEVICE_POLLING 3547 ether_poll_deregister(ifp); 3548 #endif 3549 3550 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON|DC_NETCFG_TX_ON)); 3551 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3552 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3553 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3554 sc->dc_link = 0; 3555 3556 /* 3557 * Free data in the RX lists. 3558 */ 3559 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3560 if (sc->dc_cdata.dc_rx_chain[i] != NULL) { 3561 m_freem(sc->dc_cdata.dc_rx_chain[i]); 3562 sc->dc_cdata.dc_rx_chain[i] = NULL; 3563 } 3564 } 3565 bzero((char *)&sc->dc_ldata->dc_rx_list, 3566 sizeof(sc->dc_ldata->dc_rx_list)); 3567 3568 /* 3569 * Free the TX list buffers. 3570 */ 3571 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3572 if (sc->dc_cdata.dc_tx_chain[i] != NULL) { 3573 if (sc->dc_ldata->dc_tx_list[i].dc_ctl & 3574 DC_TXCTL_SETUP) { 3575 sc->dc_cdata.dc_tx_chain[i] = NULL; 3576 continue; 3577 } 3578 m_freem(sc->dc_cdata.dc_tx_chain[i]); 3579 sc->dc_cdata.dc_tx_chain[i] = NULL; 3580 } 3581 } 3582 3583 bzero((char *)&sc->dc_ldata->dc_tx_list, 3584 sizeof(sc->dc_ldata->dc_tx_list)); 3585 3586 DC_UNLOCK(sc); 3587 3588 return; 3589 } 3590 3591 /* 3592 * Device suspend routine. Stop the interface and save some PCI 3593 * settings in case the BIOS doesn't restore them properly on 3594 * resume. 3595 */ 3596 static int 3597 dc_suspend(dev) 3598 device_t dev; 3599 { 3600 register int i; 3601 int s; 3602 struct dc_softc *sc; 3603 3604 s = splimp(); 3605 3606 sc = device_get_softc(dev); 3607 3608 dc_stop(sc); 3609 3610 for (i = 0; i < 5; i++) 3611 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 3612 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 3613 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 3614 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 3615 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 3616 3617 sc->suspended = 1; 3618 3619 splx(s); 3620 return (0); 3621 } 3622 3623 /* 3624 * Device resume routine. Restore some PCI settings in case the BIOS 3625 * doesn't, re-enable busmastering, and restart the interface if 3626 * appropriate. 3627 */ 3628 static int 3629 dc_resume(dev) 3630 device_t dev; 3631 { 3632 register int i; 3633 int s; 3634 struct dc_softc *sc; 3635 struct ifnet *ifp; 3636 3637 s = splimp(); 3638 3639 sc = device_get_softc(dev); 3640 ifp = &sc->arpcom.ac_if; 3641 3642 dc_acpi(dev); 3643 3644 /* better way to do this? */ 3645 for (i = 0; i < 5; i++) 3646 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 3647 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 3648 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 3649 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 3650 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 3651 3652 /* reenable busmastering */ 3653 pci_enable_busmaster(dev); 3654 pci_enable_io(dev, DC_RES); 3655 3656 /* reinitialize interface if necessary */ 3657 if (ifp->if_flags & IFF_UP) 3658 dc_init(sc); 3659 3660 sc->suspended = 0; 3661 3662 splx(s); 3663 return (0); 3664 } 3665 3666 /* 3667 * Stop all chip I/O so that the kernel's probe routines don't 3668 * get confused by errant DMAs when rebooting. 3669 */ 3670 static void 3671 dc_shutdown(dev) 3672 device_t dev; 3673 { 3674 struct dc_softc *sc; 3675 3676 sc = device_get_softc(dev); 3677 3678 dc_stop(sc); 3679 3680 return; 3681 } 3682