1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 38 * series chips and several workalikes including the following: 39 * 40 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 41 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 42 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 43 * ASIX Electronics AX88140A (www.asix.com.tw) 44 * ASIX Electronics AX88141 (www.asix.com.tw) 45 * ADMtek AL981 (www.admtek.com.tw) 46 * ADMtek AN985 (www.admtek.com.tw) 47 * Netgear FA511 (www.netgear.com) Appears to be rebadged ADMTek AN985 48 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 49 * Accton EN1217 (www.accton.com) 50 * Xircom X3201 (www.xircom.com) 51 * Abocom FE2500 52 * Conexant LANfinity (www.conexant.com) 53 * 3Com OfficeConnect 10/100B 3CSOHO100B (www.3com.com) 54 * 55 * Datasheets for the 21143 are available at developer.intel.com. 56 * Datasheets for the clone parts can be found at their respective sites. 57 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 58 * The PNIC II is essentially a Macronix 98715A chip; the only difference 59 * worth noting is that its multicast hash table is only 128 bits wide 60 * instead of 512. 61 * 62 * Written by Bill Paul <wpaul@ee.columbia.edu> 63 * Electrical Engineering Department 64 * Columbia University, New York City 65 */ 66 /* 67 * The Intel 21143 is the successor to the DEC 21140. It is basically 68 * the same as the 21140 but with a few new features. The 21143 supports 69 * three kinds of media attachments: 70 * 71 * o MII port, for 10Mbps and 100Mbps support and NWAY 72 * autonegotiation provided by an external PHY. 73 * o SYM port, for symbol mode 100Mbps support. 74 * o 10baseT port. 75 * o AUI/BNC port. 76 * 77 * The 100Mbps SYM port and 10baseT port can be used together in 78 * combination with the internal NWAY support to create a 10/100 79 * autosensing configuration. 80 * 81 * Note that not all tulip workalikes are handled in this driver: we only 82 * deal with those which are relatively well behaved. The Winbond is 83 * handled separately due to its different register offsets and the 84 * special handling needed for its various bugs. The PNIC is handled 85 * here, but I'm not thrilled about it. 86 * 87 * All of the workalike chips use some form of MII transceiver support 88 * with the exception of the Macronix chips, which also have a SYM port. 89 * The ASIX AX88140A is also documented to have a SYM port, but all 90 * the cards I've seen use an MII transceiver, probably because the 91 * AX88140A doesn't support internal NWAY. 92 */ 93 94 #include <sys/param.h> 95 #include <sys/endian.h> 96 #include <sys/systm.h> 97 #include <sys/sockio.h> 98 #include <sys/mbuf.h> 99 #include <sys/malloc.h> 100 #include <sys/kernel.h> 101 #include <sys/module.h> 102 #include <sys/socket.h> 103 #include <sys/sysctl.h> 104 105 #include <net/if.h> 106 #include <net/if_arp.h> 107 #include <net/ethernet.h> 108 #include <net/if_dl.h> 109 #include <net/if_media.h> 110 #include <net/if_types.h> 111 #include <net/if_vlan_var.h> 112 113 #include <net/bpf.h> 114 115 #include <machine/bus_pio.h> 116 #include <machine/bus_memio.h> 117 #include <machine/bus.h> 118 #include <machine/resource.h> 119 #include <sys/bus.h> 120 #include <sys/rman.h> 121 122 #include <dev/mii/mii.h> 123 #include <dev/mii/miivar.h> 124 125 #include <dev/pci/pcireg.h> 126 #include <dev/pci/pcivar.h> 127 128 #define DC_USEIOSPACE 129 #ifdef __alpha__ 130 #define SRM_MEDIA 131 #endif 132 133 #include <pci/if_dcreg.h> 134 135 #ifdef __sparc64__ 136 #include <dev/ofw/openfirm.h> 137 #include <machine/ofw_machdep.h> 138 #endif 139 140 MODULE_DEPEND(dc, pci, 1, 1, 1); 141 MODULE_DEPEND(dc, ether, 1, 1, 1); 142 MODULE_DEPEND(dc, miibus, 1, 1, 1); 143 144 /* "controller miibus0" required. See GENERIC if you get errors here. */ 145 #include "miibus_if.h" 146 147 /* 148 * Various supported device vendors/types and their names. 149 */ 150 static struct dc_type dc_devs[] = { 151 { DC_VENDORID_DEC, DC_DEVICEID_21143, 152 "Intel 21143 10/100BaseTX" }, 153 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009, 154 "Davicom DM9009 10/100BaseTX" }, 155 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 156 "Davicom DM9100 10/100BaseTX" }, 157 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 158 "Davicom DM9102 10/100BaseTX" }, 159 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 160 "Davicom DM9102A 10/100BaseTX" }, 161 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 162 "ADMtek AL981 10/100BaseTX" }, 163 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 164 "ADMtek AN985 10/100BaseTX" }, 165 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511, 166 "ADMtek ADM9511 10/100BaseTX" }, 167 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513, 168 "ADMtek ADM9513 10/100BaseTX" }, 169 { DC_VENDORID_ADMTEK, DC_DEVICEID_FA511, 170 "Netgear FA511 10/100BaseTX" }, 171 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 172 "ASIX AX88140A 10/100BaseTX" }, 173 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 174 "ASIX AX88141 10/100BaseTX" }, 175 { DC_VENDORID_MX, DC_DEVICEID_98713, 176 "Macronix 98713 10/100BaseTX" }, 177 { DC_VENDORID_MX, DC_DEVICEID_98713, 178 "Macronix 98713A 10/100BaseTX" }, 179 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 180 "Compex RL100-TX 10/100BaseTX" }, 181 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 182 "Compex RL100-TX 10/100BaseTX" }, 183 { DC_VENDORID_MX, DC_DEVICEID_987x5, 184 "Macronix 98715/98715A 10/100BaseTX" }, 185 { DC_VENDORID_MX, DC_DEVICEID_987x5, 186 "Macronix 98715AEC-C 10/100BaseTX" }, 187 { DC_VENDORID_MX, DC_DEVICEID_987x5, 188 "Macronix 98725 10/100BaseTX" }, 189 { DC_VENDORID_MX, DC_DEVICEID_98727, 190 "Macronix 98727/98732 10/100BaseTX" }, 191 { DC_VENDORID_LO, DC_DEVICEID_82C115, 192 "LC82C115 PNIC II 10/100BaseTX" }, 193 { DC_VENDORID_LO, DC_DEVICEID_82C168, 194 "82c168 PNIC 10/100BaseTX" }, 195 { DC_VENDORID_LO, DC_DEVICEID_82C168, 196 "82c169 PNIC 10/100BaseTX" }, 197 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217, 198 "Accton EN1217 10/100BaseTX" }, 199 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242, 200 "Accton EN2242 MiniPCI 10/100BaseTX" }, 201 { DC_VENDORID_XIRCOM, DC_DEVICEID_X3201, 202 "Xircom X3201 10/100BaseTX" }, 203 { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500, 204 "Abocom FE2500 10/100BaseTX" }, 205 { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX, 206 "Abocom FE2500MX 10/100BaseTX" }, 207 { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112, 208 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 209 { DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX, 210 "Hawking CB102 CardBus 10/100" }, 211 { DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T, 212 "PlaneX FNW-3602-T CardBus 10/100" }, 213 { DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB, 214 "3Com OfficeConnect 10/100B" }, 215 { DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120, 216 "Microsoft MN-120 CardBus 10/100" }, 217 { DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130, 218 "Microsoft MN-130 10/100" }, 219 { DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130_FAKE, 220 "Microsoft MN-130 10/100" }, 221 { 0, 0, NULL } 222 }; 223 224 static int dc_probe (device_t); 225 static int dc_attach (device_t); 226 static int dc_detach (device_t); 227 static int dc_suspend (device_t); 228 static int dc_resume (device_t); 229 #ifndef BURN_BRIDGES 230 static void dc_acpi (device_t); 231 #endif 232 static struct dc_type *dc_devtype (device_t); 233 static int dc_newbuf (struct dc_softc *, int, int); 234 static int dc_encap (struct dc_softc *, struct mbuf **); 235 static void dc_pnic_rx_bug_war (struct dc_softc *, int); 236 static int dc_rx_resync (struct dc_softc *); 237 static void dc_rxeof (struct dc_softc *); 238 static void dc_txeof (struct dc_softc *); 239 static void dc_tick (void *); 240 static void dc_tx_underrun (struct dc_softc *); 241 static void dc_intr (void *); 242 static void dc_start (struct ifnet *); 243 static int dc_ioctl (struct ifnet *, u_long, caddr_t); 244 static void dc_init (void *); 245 static void dc_stop (struct dc_softc *); 246 static void dc_watchdog (struct ifnet *); 247 static void dc_shutdown (device_t); 248 static int dc_ifmedia_upd (struct ifnet *); 249 static void dc_ifmedia_sts (struct ifnet *, struct ifmediareq *); 250 251 static void dc_delay (struct dc_softc *); 252 static void dc_eeprom_idle (struct dc_softc *); 253 static void dc_eeprom_putbyte (struct dc_softc *, int); 254 static void dc_eeprom_getword (struct dc_softc *, int, u_int16_t *); 255 static void dc_eeprom_getword_pnic 256 (struct dc_softc *, int, u_int16_t *); 257 static void dc_eeprom_getword_xircom 258 (struct dc_softc *, int, u_int16_t *); 259 static void dc_eeprom_width (struct dc_softc *); 260 static void dc_read_eeprom (struct dc_softc *, caddr_t, int, int, int); 261 262 static void dc_mii_writebit (struct dc_softc *, int); 263 static int dc_mii_readbit (struct dc_softc *); 264 static void dc_mii_sync (struct dc_softc *); 265 static void dc_mii_send (struct dc_softc *, u_int32_t, int); 266 static int dc_mii_readreg (struct dc_softc *, struct dc_mii_frame *); 267 static int dc_mii_writereg (struct dc_softc *, struct dc_mii_frame *); 268 static int dc_miibus_readreg (device_t, int, int); 269 static int dc_miibus_writereg (device_t, int, int, int); 270 static void dc_miibus_statchg (device_t); 271 static void dc_miibus_mediainit (device_t); 272 273 static void dc_setcfg (struct dc_softc *, int); 274 static uint32_t dc_mchash_le (struct dc_softc *, const uint8_t *); 275 static uint32_t dc_mchash_be (const uint8_t *); 276 static void dc_setfilt_21143 (struct dc_softc *); 277 static void dc_setfilt_asix (struct dc_softc *); 278 static void dc_setfilt_admtek (struct dc_softc *); 279 static void dc_setfilt_xircom (struct dc_softc *); 280 281 static void dc_setfilt (struct dc_softc *); 282 283 static void dc_reset (struct dc_softc *); 284 static int dc_list_rx_init (struct dc_softc *); 285 static int dc_list_tx_init (struct dc_softc *); 286 287 static void dc_read_srom (struct dc_softc *, int); 288 static void dc_parse_21143_srom (struct dc_softc *); 289 static void dc_decode_leaf_sia (struct dc_softc *, struct dc_eblock_sia *); 290 static void dc_decode_leaf_mii (struct dc_softc *, struct dc_eblock_mii *); 291 static void dc_decode_leaf_sym (struct dc_softc *, struct dc_eblock_sym *); 292 static void dc_apply_fixup (struct dc_softc *, int); 293 294 static void dc_dma_map_txbuf (void *, bus_dma_segment_t *, int, bus_size_t, 295 int); 296 static void dc_dma_map_rxbuf (void *, bus_dma_segment_t *, int, bus_size_t, 297 int); 298 299 #ifdef DC_USEIOSPACE 300 #define DC_RES SYS_RES_IOPORT 301 #define DC_RID DC_PCI_CFBIO 302 #else 303 #define DC_RES SYS_RES_MEMORY 304 #define DC_RID DC_PCI_CFBMA 305 #endif 306 307 static device_method_t dc_methods[] = { 308 /* Device interface */ 309 DEVMETHOD(device_probe, dc_probe), 310 DEVMETHOD(device_attach, dc_attach), 311 DEVMETHOD(device_detach, dc_detach), 312 DEVMETHOD(device_suspend, dc_suspend), 313 DEVMETHOD(device_resume, dc_resume), 314 DEVMETHOD(device_shutdown, dc_shutdown), 315 316 /* bus interface */ 317 DEVMETHOD(bus_print_child, bus_generic_print_child), 318 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 319 320 /* MII interface */ 321 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 322 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 323 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 324 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 325 326 { 0, 0 } 327 }; 328 329 static driver_t dc_driver = { 330 "dc", 331 dc_methods, 332 sizeof(struct dc_softc) 333 }; 334 335 static devclass_t dc_devclass; 336 #ifdef __i386__ 337 static int dc_quick = 1; 338 SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW, &dc_quick, 0, 339 "do not m_devget() in dc driver"); 340 #endif 341 342 DRIVER_MODULE(dc, cardbus, dc_driver, dc_devclass, 0, 0); 343 DRIVER_MODULE(dc, pci, dc_driver, dc_devclass, 0, 0); 344 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 345 346 #define DC_SETBIT(sc, reg, x) \ 347 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 348 349 #define DC_CLRBIT(sc, reg, x) \ 350 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 351 352 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 353 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 354 355 #define IS_MPSAFE 0 356 357 static void 358 dc_delay(struct dc_softc *sc) 359 { 360 int idx; 361 362 for (idx = (300 / 33) + 1; idx > 0; idx--) 363 CSR_READ_4(sc, DC_BUSCTL); 364 } 365 366 static void 367 dc_eeprom_width(struct dc_softc *sc) 368 { 369 int i; 370 371 /* Force EEPROM to idle state. */ 372 dc_eeprom_idle(sc); 373 374 /* Enter EEPROM access mode. */ 375 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 376 dc_delay(sc); 377 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 378 dc_delay(sc); 379 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 380 dc_delay(sc); 381 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 382 dc_delay(sc); 383 384 for (i = 3; i--;) { 385 if (6 & (1 << i)) 386 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 387 else 388 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 389 dc_delay(sc); 390 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 391 dc_delay(sc); 392 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 393 dc_delay(sc); 394 } 395 396 for (i = 1; i <= 12; i++) { 397 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 398 dc_delay(sc); 399 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { 400 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 401 dc_delay(sc); 402 break; 403 } 404 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 405 dc_delay(sc); 406 } 407 408 /* Turn off EEPROM access mode. */ 409 dc_eeprom_idle(sc); 410 411 if (i < 4 || i > 12) 412 sc->dc_romwidth = 6; 413 else 414 sc->dc_romwidth = i; 415 416 /* Enter EEPROM access mode. */ 417 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 418 dc_delay(sc); 419 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 420 dc_delay(sc); 421 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 422 dc_delay(sc); 423 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 424 dc_delay(sc); 425 426 /* Turn off EEPROM access mode. */ 427 dc_eeprom_idle(sc); 428 } 429 430 static void 431 dc_eeprom_idle(struct dc_softc *sc) 432 { 433 int i; 434 435 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 436 dc_delay(sc); 437 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 438 dc_delay(sc); 439 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 440 dc_delay(sc); 441 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 442 dc_delay(sc); 443 444 for (i = 0; i < 25; i++) { 445 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 446 dc_delay(sc); 447 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 448 dc_delay(sc); 449 } 450 451 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 452 dc_delay(sc); 453 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 454 dc_delay(sc); 455 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 456 } 457 458 /* 459 * Send a read command and address to the EEPROM, check for ACK. 460 */ 461 static void 462 dc_eeprom_putbyte(struct dc_softc *sc, int addr) 463 { 464 int d, i; 465 466 d = DC_EECMD_READ >> 6; 467 for (i = 3; i--; ) { 468 if (d & (1 << i)) 469 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 470 else 471 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 472 dc_delay(sc); 473 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 474 dc_delay(sc); 475 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 476 dc_delay(sc); 477 } 478 479 /* 480 * Feed in each bit and strobe the clock. 481 */ 482 for (i = sc->dc_romwidth; i--;) { 483 if (addr & (1 << i)) { 484 SIO_SET(DC_SIO_EE_DATAIN); 485 } else { 486 SIO_CLR(DC_SIO_EE_DATAIN); 487 } 488 dc_delay(sc); 489 SIO_SET(DC_SIO_EE_CLK); 490 dc_delay(sc); 491 SIO_CLR(DC_SIO_EE_CLK); 492 dc_delay(sc); 493 } 494 } 495 496 /* 497 * Read a word of data stored in the EEPROM at address 'addr.' 498 * The PNIC 82c168/82c169 has its own non-standard way to read 499 * the EEPROM. 500 */ 501 static void 502 dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, u_int16_t *dest) 503 { 504 int i; 505 u_int32_t r; 506 507 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr); 508 509 for (i = 0; i < DC_TIMEOUT; i++) { 510 DELAY(1); 511 r = CSR_READ_4(sc, DC_SIO); 512 if (!(r & DC_PN_SIOCTL_BUSY)) { 513 *dest = (u_int16_t)(r & 0xFFFF); 514 return; 515 } 516 } 517 } 518 519 /* 520 * Read a word of data stored in the EEPROM at address 'addr.' 521 * The Xircom X3201 has its own non-standard way to read 522 * the EEPROM, too. 523 */ 524 static void 525 dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, u_int16_t *dest) 526 { 527 528 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 529 530 addr *= 2; 531 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 532 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff; 533 addr += 1; 534 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 535 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8; 536 537 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 538 } 539 540 /* 541 * Read a word of data stored in the EEPROM at address 'addr.' 542 */ 543 static void 544 dc_eeprom_getword(struct dc_softc *sc, int addr, u_int16_t *dest) 545 { 546 int i; 547 u_int16_t word = 0; 548 549 /* Force EEPROM to idle state. */ 550 dc_eeprom_idle(sc); 551 552 /* Enter EEPROM access mode. */ 553 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 554 dc_delay(sc); 555 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 556 dc_delay(sc); 557 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 558 dc_delay(sc); 559 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 560 dc_delay(sc); 561 562 /* 563 * Send address of word we want to read. 564 */ 565 dc_eeprom_putbyte(sc, addr); 566 567 /* 568 * Start reading bits from EEPROM. 569 */ 570 for (i = 0x8000; i; i >>= 1) { 571 SIO_SET(DC_SIO_EE_CLK); 572 dc_delay(sc); 573 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 574 word |= i; 575 dc_delay(sc); 576 SIO_CLR(DC_SIO_EE_CLK); 577 dc_delay(sc); 578 } 579 580 /* Turn off EEPROM access mode. */ 581 dc_eeprom_idle(sc); 582 583 *dest = word; 584 } 585 586 /* 587 * Read a sequence of words from the EEPROM. 588 */ 589 static void 590 dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int swap) 591 { 592 int i; 593 u_int16_t word = 0, *ptr; 594 595 for (i = 0; i < cnt; i++) { 596 if (DC_IS_PNIC(sc)) 597 dc_eeprom_getword_pnic(sc, off + i, &word); 598 else if (DC_IS_XIRCOM(sc)) 599 dc_eeprom_getword_xircom(sc, off + i, &word); 600 else 601 dc_eeprom_getword(sc, off + i, &word); 602 ptr = (u_int16_t *)(dest + (i * 2)); 603 if (swap) 604 *ptr = ntohs(word); 605 else 606 *ptr = word; 607 } 608 } 609 610 /* 611 * The following two routines are taken from the Macronix 98713 612 * Application Notes pp.19-21. 613 */ 614 /* 615 * Write a bit to the MII bus. 616 */ 617 static void 618 dc_mii_writebit(struct dc_softc *sc, int bit) 619 { 620 621 if (bit) 622 CSR_WRITE_4(sc, DC_SIO, 623 DC_SIO_ROMCTL_WRITE | DC_SIO_MII_DATAOUT); 624 else 625 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 626 627 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 628 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 629 } 630 631 /* 632 * Read a bit from the MII bus. 633 */ 634 static int 635 dc_mii_readbit(struct dc_softc *sc) 636 { 637 638 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ | DC_SIO_MII_DIR); 639 CSR_READ_4(sc, DC_SIO); 640 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 641 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 642 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 643 return (1); 644 645 return (0); 646 } 647 648 /* 649 * Sync the PHYs by setting data bit and strobing the clock 32 times. 650 */ 651 static void 652 dc_mii_sync(struct dc_softc *sc) 653 { 654 int i; 655 656 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 657 658 for (i = 0; i < 32; i++) 659 dc_mii_writebit(sc, 1); 660 } 661 662 /* 663 * Clock a series of bits through the MII. 664 */ 665 static void 666 dc_mii_send(struct dc_softc *sc, u_int32_t bits, int cnt) 667 { 668 int i; 669 670 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 671 dc_mii_writebit(sc, bits & i); 672 } 673 674 /* 675 * Read an PHY register through the MII. 676 */ 677 static int 678 dc_mii_readreg(struct dc_softc *sc, struct dc_mii_frame *frame) 679 { 680 int i, ack; 681 682 DC_LOCK(sc); 683 684 /* 685 * Set up frame for RX. 686 */ 687 frame->mii_stdelim = DC_MII_STARTDELIM; 688 frame->mii_opcode = DC_MII_READOP; 689 frame->mii_turnaround = 0; 690 frame->mii_data = 0; 691 692 /* 693 * Sync the PHYs. 694 */ 695 dc_mii_sync(sc); 696 697 /* 698 * Send command/address info. 699 */ 700 dc_mii_send(sc, frame->mii_stdelim, 2); 701 dc_mii_send(sc, frame->mii_opcode, 2); 702 dc_mii_send(sc, frame->mii_phyaddr, 5); 703 dc_mii_send(sc, frame->mii_regaddr, 5); 704 705 #ifdef notdef 706 /* Idle bit */ 707 dc_mii_writebit(sc, 1); 708 dc_mii_writebit(sc, 0); 709 #endif 710 711 /* Check for ack. */ 712 ack = dc_mii_readbit(sc); 713 714 /* 715 * Now try reading data bits. If the ack failed, we still 716 * need to clock through 16 cycles to keep the PHY(s) in sync. 717 */ 718 if (ack) { 719 for (i = 0; i < 16; i++) 720 dc_mii_readbit(sc); 721 goto fail; 722 } 723 724 for (i = 0x8000; i; i >>= 1) { 725 if (!ack) { 726 if (dc_mii_readbit(sc)) 727 frame->mii_data |= i; 728 } 729 } 730 731 fail: 732 733 dc_mii_writebit(sc, 0); 734 dc_mii_writebit(sc, 0); 735 736 DC_UNLOCK(sc); 737 738 if (ack) 739 return (1); 740 return (0); 741 } 742 743 /* 744 * Write to a PHY register through the MII. 745 */ 746 static int 747 dc_mii_writereg(struct dc_softc *sc, struct dc_mii_frame *frame) 748 { 749 750 DC_LOCK(sc); 751 /* 752 * Set up frame for TX. 753 */ 754 755 frame->mii_stdelim = DC_MII_STARTDELIM; 756 frame->mii_opcode = DC_MII_WRITEOP; 757 frame->mii_turnaround = DC_MII_TURNAROUND; 758 759 /* 760 * Sync the PHYs. 761 */ 762 dc_mii_sync(sc); 763 764 dc_mii_send(sc, frame->mii_stdelim, 2); 765 dc_mii_send(sc, frame->mii_opcode, 2); 766 dc_mii_send(sc, frame->mii_phyaddr, 5); 767 dc_mii_send(sc, frame->mii_regaddr, 5); 768 dc_mii_send(sc, frame->mii_turnaround, 2); 769 dc_mii_send(sc, frame->mii_data, 16); 770 771 /* Idle bit. */ 772 dc_mii_writebit(sc, 0); 773 dc_mii_writebit(sc, 0); 774 775 DC_UNLOCK(sc); 776 777 return (0); 778 } 779 780 static int 781 dc_miibus_readreg(device_t dev, int phy, int reg) 782 { 783 struct dc_mii_frame frame; 784 struct dc_softc *sc; 785 int i, rval, phy_reg = 0; 786 787 sc = device_get_softc(dev); 788 bzero(&frame, sizeof(frame)); 789 790 /* 791 * Note: both the AL981 and AN985 have internal PHYs, 792 * however the AL981 provides direct access to the PHY 793 * registers while the AN985 uses a serial MII interface. 794 * The AN985's MII interface is also buggy in that you 795 * can read from any MII address (0 to 31), but only address 1 796 * behaves normally. To deal with both cases, we pretend 797 * that the PHY is at MII address 1. 798 */ 799 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 800 return (0); 801 802 /* 803 * Note: the ukphy probes of the RS7112 report a PHY at 804 * MII address 0 (possibly HomePNA?) and 1 (ethernet) 805 * so we only respond to correct one. 806 */ 807 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 808 return (0); 809 810 if (sc->dc_pmode != DC_PMODE_MII) { 811 if (phy == (MII_NPHY - 1)) { 812 switch (reg) { 813 case MII_BMSR: 814 /* 815 * Fake something to make the probe 816 * code think there's a PHY here. 817 */ 818 return (BMSR_MEDIAMASK); 819 break; 820 case MII_PHYIDR1: 821 if (DC_IS_PNIC(sc)) 822 return (DC_VENDORID_LO); 823 return (DC_VENDORID_DEC); 824 break; 825 case MII_PHYIDR2: 826 if (DC_IS_PNIC(sc)) 827 return (DC_DEVICEID_82C168); 828 return (DC_DEVICEID_21143); 829 break; 830 default: 831 return (0); 832 break; 833 } 834 } else 835 return (0); 836 } 837 838 if (DC_IS_PNIC(sc)) { 839 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 840 (phy << 23) | (reg << 18)); 841 for (i = 0; i < DC_TIMEOUT; i++) { 842 DELAY(1); 843 rval = CSR_READ_4(sc, DC_PN_MII); 844 if (!(rval & DC_PN_MII_BUSY)) { 845 rval &= 0xFFFF; 846 return (rval == 0xFFFF ? 0 : rval); 847 } 848 } 849 return (0); 850 } 851 852 if (DC_IS_COMET(sc)) { 853 switch (reg) { 854 case MII_BMCR: 855 phy_reg = DC_AL_BMCR; 856 break; 857 case MII_BMSR: 858 phy_reg = DC_AL_BMSR; 859 break; 860 case MII_PHYIDR1: 861 phy_reg = DC_AL_VENID; 862 break; 863 case MII_PHYIDR2: 864 phy_reg = DC_AL_DEVID; 865 break; 866 case MII_ANAR: 867 phy_reg = DC_AL_ANAR; 868 break; 869 case MII_ANLPAR: 870 phy_reg = DC_AL_LPAR; 871 break; 872 case MII_ANER: 873 phy_reg = DC_AL_ANER; 874 break; 875 default: 876 printf("dc%d: phy_read: bad phy register %x\n", 877 sc->dc_unit, reg); 878 return (0); 879 break; 880 } 881 882 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 883 884 if (rval == 0xFFFF) 885 return (0); 886 return (rval); 887 } 888 889 frame.mii_phyaddr = phy; 890 frame.mii_regaddr = reg; 891 if (sc->dc_type == DC_TYPE_98713) { 892 phy_reg = CSR_READ_4(sc, DC_NETCFG); 893 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 894 } 895 dc_mii_readreg(sc, &frame); 896 if (sc->dc_type == DC_TYPE_98713) 897 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 898 899 return (frame.mii_data); 900 } 901 902 static int 903 dc_miibus_writereg(device_t dev, int phy, int reg, int data) 904 { 905 struct dc_softc *sc; 906 struct dc_mii_frame frame; 907 int i, phy_reg = 0; 908 909 sc = device_get_softc(dev); 910 bzero(&frame, sizeof(frame)); 911 912 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 913 return (0); 914 915 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 916 return (0); 917 918 if (DC_IS_PNIC(sc)) { 919 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 920 (phy << 23) | (reg << 10) | data); 921 for (i = 0; i < DC_TIMEOUT; i++) { 922 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 923 break; 924 } 925 return (0); 926 } 927 928 if (DC_IS_COMET(sc)) { 929 switch (reg) { 930 case MII_BMCR: 931 phy_reg = DC_AL_BMCR; 932 break; 933 case MII_BMSR: 934 phy_reg = DC_AL_BMSR; 935 break; 936 case MII_PHYIDR1: 937 phy_reg = DC_AL_VENID; 938 break; 939 case MII_PHYIDR2: 940 phy_reg = DC_AL_DEVID; 941 break; 942 case MII_ANAR: 943 phy_reg = DC_AL_ANAR; 944 break; 945 case MII_ANLPAR: 946 phy_reg = DC_AL_LPAR; 947 break; 948 case MII_ANER: 949 phy_reg = DC_AL_ANER; 950 break; 951 default: 952 printf("dc%d: phy_write: bad phy register %x\n", 953 sc->dc_unit, reg); 954 return (0); 955 break; 956 } 957 958 CSR_WRITE_4(sc, phy_reg, data); 959 return (0); 960 } 961 962 frame.mii_phyaddr = phy; 963 frame.mii_regaddr = reg; 964 frame.mii_data = data; 965 966 if (sc->dc_type == DC_TYPE_98713) { 967 phy_reg = CSR_READ_4(sc, DC_NETCFG); 968 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 969 } 970 dc_mii_writereg(sc, &frame); 971 if (sc->dc_type == DC_TYPE_98713) 972 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 973 974 return (0); 975 } 976 977 static void 978 dc_miibus_statchg(device_t dev) 979 { 980 struct dc_softc *sc; 981 struct mii_data *mii; 982 struct ifmedia *ifm; 983 984 sc = device_get_softc(dev); 985 if (DC_IS_ADMTEK(sc)) 986 return; 987 988 mii = device_get_softc(sc->dc_miibus); 989 ifm = &mii->mii_media; 990 if (DC_IS_DAVICOM(sc) && 991 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 992 dc_setcfg(sc, ifm->ifm_media); 993 sc->dc_if_media = ifm->ifm_media; 994 } else { 995 dc_setcfg(sc, mii->mii_media_active); 996 sc->dc_if_media = mii->mii_media_active; 997 } 998 } 999 1000 /* 1001 * Special support for DM9102A cards with HomePNA PHYs. Note: 1002 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 1003 * to be impossible to talk to the management interface of the DM9801 1004 * PHY (its MDIO pin is not connected to anything). Consequently, 1005 * the driver has to just 'know' about the additional mode and deal 1006 * with it itself. *sigh* 1007 */ 1008 static void 1009 dc_miibus_mediainit(device_t dev) 1010 { 1011 struct dc_softc *sc; 1012 struct mii_data *mii; 1013 struct ifmedia *ifm; 1014 int rev; 1015 1016 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1017 1018 sc = device_get_softc(dev); 1019 mii = device_get_softc(sc->dc_miibus); 1020 ifm = &mii->mii_media; 1021 1022 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 1023 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL); 1024 } 1025 1026 #define DC_BITS_512 9 1027 #define DC_BITS_128 7 1028 #define DC_BITS_64 6 1029 1030 static uint32_t 1031 dc_mchash_le(struct dc_softc *sc, const uint8_t *addr) 1032 { 1033 uint32_t crc; 1034 1035 /* Compute CRC for the address value. */ 1036 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 1037 1038 /* 1039 * The hash table on the PNIC II and the MX98715AEC-C/D/E 1040 * chips is only 128 bits wide. 1041 */ 1042 if (sc->dc_flags & DC_128BIT_HASH) 1043 return (crc & ((1 << DC_BITS_128) - 1)); 1044 1045 /* The hash table on the MX98715BEC is only 64 bits wide. */ 1046 if (sc->dc_flags & DC_64BIT_HASH) 1047 return (crc & ((1 << DC_BITS_64) - 1)); 1048 1049 /* Xircom's hash filtering table is different (read: weird) */ 1050 /* Xircom uses the LEAST significant bits */ 1051 if (DC_IS_XIRCOM(sc)) { 1052 if ((crc & 0x180) == 0x180) 1053 return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4)); 1054 else 1055 return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 + 1056 (12 << 4)); 1057 } 1058 1059 return (crc & ((1 << DC_BITS_512) - 1)); 1060 } 1061 1062 /* 1063 * Calculate CRC of a multicast group address, return the lower 6 bits. 1064 */ 1065 static uint32_t 1066 dc_mchash_be(const uint8_t *addr) 1067 { 1068 uint32_t crc; 1069 1070 /* Compute CRC for the address value. */ 1071 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 1072 1073 /* Return the filter bit position. */ 1074 return ((crc >> 26) & 0x0000003F); 1075 } 1076 1077 /* 1078 * 21143-style RX filter setup routine. Filter programming is done by 1079 * downloading a special setup frame into the TX engine. 21143, Macronix, 1080 * PNIC, PNIC II and Davicom chips are programmed this way. 1081 * 1082 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1083 * address (our node address) and a 512-bit hash filter for multicast 1084 * frames. We also sneak the broadcast address into the hash filter since 1085 * we need that too. 1086 */ 1087 static void 1088 dc_setfilt_21143(struct dc_softc *sc) 1089 { 1090 struct dc_desc *sframe; 1091 u_int32_t h, *sp; 1092 struct ifmultiaddr *ifma; 1093 struct ifnet *ifp; 1094 int i; 1095 1096 ifp = &sc->arpcom.ac_if; 1097 1098 i = sc->dc_cdata.dc_tx_prod; 1099 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1100 sc->dc_cdata.dc_tx_cnt++; 1101 sframe = &sc->dc_ldata->dc_tx_list[i]; 1102 sp = sc->dc_cdata.dc_sbuf; 1103 bzero(sp, DC_SFRAME_LEN); 1104 1105 sframe->dc_data = htole32(sc->dc_saddr); 1106 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1107 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1108 1109 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1110 1111 /* If we want promiscuous mode, set the allframes bit. */ 1112 if (ifp->if_flags & IFF_PROMISC) 1113 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1114 else 1115 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1116 1117 if (ifp->if_flags & IFF_ALLMULTI) 1118 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1119 else 1120 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1121 1122 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1123 if (ifma->ifma_addr->sa_family != AF_LINK) 1124 continue; 1125 h = dc_mchash_le(sc, 1126 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1127 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1128 } 1129 1130 if (ifp->if_flags & IFF_BROADCAST) { 1131 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1132 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1133 } 1134 1135 /* Set our MAC address */ 1136 sp[39] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1137 sp[40] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1138 sp[41] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1139 1140 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1141 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1142 1143 /* 1144 * The PNIC takes an exceedingly long time to process its 1145 * setup frame; wait 10ms after posting the setup frame 1146 * before proceeding, just so it has time to swallow its 1147 * medicine. 1148 */ 1149 DELAY(10000); 1150 1151 ifp->if_timer = 5; 1152 } 1153 1154 static void 1155 dc_setfilt_admtek(struct dc_softc *sc) 1156 { 1157 struct ifnet *ifp; 1158 struct ifmultiaddr *ifma; 1159 int h = 0; 1160 u_int32_t hashes[2] = { 0, 0 }; 1161 1162 ifp = &sc->arpcom.ac_if; 1163 1164 /* Init our MAC address. */ 1165 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1166 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1167 1168 /* If we want promiscuous mode, set the allframes bit. */ 1169 if (ifp->if_flags & IFF_PROMISC) 1170 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1171 else 1172 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1173 1174 if (ifp->if_flags & IFF_ALLMULTI) 1175 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1176 else 1177 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1178 1179 /* First, zot all the existing hash bits. */ 1180 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1181 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1182 1183 /* 1184 * If we're already in promisc or allmulti mode, we 1185 * don't have to bother programming the multicast filter. 1186 */ 1187 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1188 return; 1189 1190 /* Now program new ones. */ 1191 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1192 if (ifma->ifma_addr->sa_family != AF_LINK) 1193 continue; 1194 if (DC_IS_CENTAUR(sc)) 1195 h = dc_mchash_le(sc, 1196 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1197 else 1198 h = dc_mchash_be( 1199 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1200 if (h < 32) 1201 hashes[0] |= (1 << h); 1202 else 1203 hashes[1] |= (1 << (h - 32)); 1204 } 1205 1206 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1207 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1208 } 1209 1210 static void 1211 dc_setfilt_asix(struct dc_softc *sc) 1212 { 1213 struct ifnet *ifp; 1214 struct ifmultiaddr *ifma; 1215 int h = 0; 1216 u_int32_t hashes[2] = { 0, 0 }; 1217 1218 ifp = &sc->arpcom.ac_if; 1219 1220 /* Init our MAC address */ 1221 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1222 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1223 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1224 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1225 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1226 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1227 1228 /* If we want promiscuous mode, set the allframes bit. */ 1229 if (ifp->if_flags & IFF_PROMISC) 1230 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1231 else 1232 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1233 1234 if (ifp->if_flags & IFF_ALLMULTI) 1235 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1236 else 1237 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1238 1239 /* 1240 * The ASIX chip has a special bit to enable reception 1241 * of broadcast frames. 1242 */ 1243 if (ifp->if_flags & IFF_BROADCAST) 1244 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1245 else 1246 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1247 1248 /* first, zot all the existing hash bits */ 1249 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1250 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1251 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1252 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1253 1254 /* 1255 * If we're already in promisc or allmulti mode, we 1256 * don't have to bother programming the multicast filter. 1257 */ 1258 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1259 return; 1260 1261 /* now program new ones */ 1262 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1263 if (ifma->ifma_addr->sa_family != AF_LINK) 1264 continue; 1265 h = dc_mchash_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1266 if (h < 32) 1267 hashes[0] |= (1 << h); 1268 else 1269 hashes[1] |= (1 << (h - 32)); 1270 } 1271 1272 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1273 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1274 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1275 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1276 } 1277 1278 static void 1279 dc_setfilt_xircom(struct dc_softc *sc) 1280 { 1281 struct ifnet *ifp; 1282 struct ifmultiaddr *ifma; 1283 struct dc_desc *sframe; 1284 u_int32_t h, *sp; 1285 int i; 1286 1287 ifp = &sc->arpcom.ac_if; 1288 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1289 1290 i = sc->dc_cdata.dc_tx_prod; 1291 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1292 sc->dc_cdata.dc_tx_cnt++; 1293 sframe = &sc->dc_ldata->dc_tx_list[i]; 1294 sp = sc->dc_cdata.dc_sbuf; 1295 bzero(sp, DC_SFRAME_LEN); 1296 1297 sframe->dc_data = htole32(sc->dc_saddr); 1298 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1299 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1300 1301 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1302 1303 /* If we want promiscuous mode, set the allframes bit. */ 1304 if (ifp->if_flags & IFF_PROMISC) 1305 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1306 else 1307 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1308 1309 if (ifp->if_flags & IFF_ALLMULTI) 1310 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1311 else 1312 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1313 1314 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1315 if (ifma->ifma_addr->sa_family != AF_LINK) 1316 continue; 1317 h = dc_mchash_le(sc, 1318 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1319 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1320 } 1321 1322 if (ifp->if_flags & IFF_BROADCAST) { 1323 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1324 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1325 } 1326 1327 /* Set our MAC address */ 1328 sp[0] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1329 sp[1] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1330 sp[2] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1331 1332 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1333 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1334 ifp->if_flags |= IFF_RUNNING; 1335 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1336 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1337 1338 /* 1339 * Wait some time... 1340 */ 1341 DELAY(1000); 1342 1343 ifp->if_timer = 5; 1344 } 1345 1346 static void 1347 dc_setfilt(struct dc_softc *sc) 1348 { 1349 1350 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1351 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1352 dc_setfilt_21143(sc); 1353 1354 if (DC_IS_ASIX(sc)) 1355 dc_setfilt_asix(sc); 1356 1357 if (DC_IS_ADMTEK(sc)) 1358 dc_setfilt_admtek(sc); 1359 1360 if (DC_IS_XIRCOM(sc)) 1361 dc_setfilt_xircom(sc); 1362 } 1363 1364 /* 1365 * In order to fiddle with the 'full-duplex' and '100Mbps' bits in 1366 * the netconfig register, we first have to put the transmit and/or 1367 * receive logic in the idle state. 1368 */ 1369 static void 1370 dc_setcfg(struct dc_softc *sc, int media) 1371 { 1372 int i, restart = 0, watchdogreg; 1373 u_int32_t isr; 1374 1375 if (IFM_SUBTYPE(media) == IFM_NONE) 1376 return; 1377 1378 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) { 1379 restart = 1; 1380 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1381 1382 for (i = 0; i < DC_TIMEOUT; i++) { 1383 isr = CSR_READ_4(sc, DC_ISR); 1384 if (isr & DC_ISR_TX_IDLE && 1385 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1386 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT)) 1387 break; 1388 DELAY(10); 1389 } 1390 1391 if (i == DC_TIMEOUT) 1392 printf("dc%d: failed to force tx and " 1393 "rx to idle state\n", sc->dc_unit); 1394 } 1395 1396 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1397 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1398 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1399 if (sc->dc_pmode == DC_PMODE_MII) { 1400 if (DC_IS_INTEL(sc)) { 1401 /* There's a write enable bit here that reads as 1. */ 1402 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1403 watchdogreg &= ~DC_WDOG_CTLWREN; 1404 watchdogreg |= DC_WDOG_JABBERDIS; 1405 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1406 } else { 1407 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1408 } 1409 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1410 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1411 if (sc->dc_type == DC_TYPE_98713) 1412 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1413 DC_NETCFG_SCRAMBLER)); 1414 if (!DC_IS_DAVICOM(sc)) 1415 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1416 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1417 if (DC_IS_INTEL(sc)) 1418 dc_apply_fixup(sc, IFM_AUTO); 1419 } else { 1420 if (DC_IS_PNIC(sc)) { 1421 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1422 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1423 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1424 } 1425 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1426 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1427 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1428 if (DC_IS_INTEL(sc)) 1429 dc_apply_fixup(sc, 1430 (media & IFM_GMASK) == IFM_FDX ? 1431 IFM_100_TX | IFM_FDX : IFM_100_TX); 1432 } 1433 } 1434 1435 if (IFM_SUBTYPE(media) == IFM_10_T) { 1436 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1437 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1438 if (sc->dc_pmode == DC_PMODE_MII) { 1439 /* There's a write enable bit here that reads as 1. */ 1440 if (DC_IS_INTEL(sc)) { 1441 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1442 watchdogreg &= ~DC_WDOG_CTLWREN; 1443 watchdogreg |= DC_WDOG_JABBERDIS; 1444 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1445 } else { 1446 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1447 } 1448 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1449 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1450 if (sc->dc_type == DC_TYPE_98713) 1451 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1452 if (!DC_IS_DAVICOM(sc)) 1453 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1454 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1455 if (DC_IS_INTEL(sc)) 1456 dc_apply_fixup(sc, IFM_AUTO); 1457 } else { 1458 if (DC_IS_PNIC(sc)) { 1459 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1460 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1461 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1462 } 1463 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1464 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1465 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1466 if (DC_IS_INTEL(sc)) { 1467 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1468 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1469 if ((media & IFM_GMASK) == IFM_FDX) 1470 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1471 else 1472 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1473 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1474 DC_CLRBIT(sc, DC_10BTCTRL, 1475 DC_TCTL_AUTONEGENBL); 1476 dc_apply_fixup(sc, 1477 (media & IFM_GMASK) == IFM_FDX ? 1478 IFM_10_T | IFM_FDX : IFM_10_T); 1479 DELAY(20000); 1480 } 1481 } 1482 } 1483 1484 /* 1485 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1486 * PHY and we want HomePNA mode, set the portsel bit to turn 1487 * on the external MII port. 1488 */ 1489 if (DC_IS_DAVICOM(sc)) { 1490 if (IFM_SUBTYPE(media) == IFM_HPNA_1) { 1491 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1492 sc->dc_link = 1; 1493 } else { 1494 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1495 } 1496 } 1497 1498 if ((media & IFM_GMASK) == IFM_FDX) { 1499 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1500 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1501 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1502 } else { 1503 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1504 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1505 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1506 } 1507 1508 if (restart) 1509 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON | DC_NETCFG_RX_ON); 1510 } 1511 1512 static void 1513 dc_reset(struct dc_softc *sc) 1514 { 1515 int i; 1516 1517 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1518 1519 for (i = 0; i < DC_TIMEOUT; i++) { 1520 DELAY(10); 1521 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1522 break; 1523 } 1524 1525 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) || 1526 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) { 1527 DELAY(10000); 1528 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1529 i = 0; 1530 } 1531 1532 if (i == DC_TIMEOUT) 1533 printf("dc%d: reset never completed!\n", sc->dc_unit); 1534 1535 /* Wait a little while for the chip to get its brains in order. */ 1536 DELAY(1000); 1537 1538 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1539 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1540 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1541 1542 /* 1543 * Bring the SIA out of reset. In some cases, it looks 1544 * like failing to unreset the SIA soon enough gets it 1545 * into a state where it will never come out of reset 1546 * until we reset the whole chip again. 1547 */ 1548 if (DC_IS_INTEL(sc)) { 1549 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1550 CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1551 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1552 } 1553 } 1554 1555 static struct dc_type * 1556 dc_devtype(device_t dev) 1557 { 1558 struct dc_type *t; 1559 u_int32_t rev; 1560 1561 t = dc_devs; 1562 1563 while (t->dc_name != NULL) { 1564 if ((pci_get_vendor(dev) == t->dc_vid) && 1565 (pci_get_device(dev) == t->dc_did)) { 1566 /* Check the PCI revision */ 1567 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1568 if (t->dc_did == DC_DEVICEID_98713 && 1569 rev >= DC_REVISION_98713A) 1570 t++; 1571 if (t->dc_did == DC_DEVICEID_98713_CP && 1572 rev >= DC_REVISION_98713A) 1573 t++; 1574 if (t->dc_did == DC_DEVICEID_987x5 && 1575 rev >= DC_REVISION_98715AEC_C) 1576 t++; 1577 if (t->dc_did == DC_DEVICEID_987x5 && 1578 rev >= DC_REVISION_98725) 1579 t++; 1580 if (t->dc_did == DC_DEVICEID_AX88140A && 1581 rev >= DC_REVISION_88141) 1582 t++; 1583 if (t->dc_did == DC_DEVICEID_82C168 && 1584 rev >= DC_REVISION_82C169) 1585 t++; 1586 if (t->dc_did == DC_DEVICEID_DM9102 && 1587 rev >= DC_REVISION_DM9102A) 1588 t++; 1589 /* 1590 * The Microsoft MN-130 has a device ID of 0x0002, 1591 * which happens to be the same as the PNIC 82c168. 1592 * To keep dc_attach() from getting confused, we 1593 * pretend its ID is something different. 1594 * XXX: ideally, dc_attach() should be checking 1595 * vendorid+deviceid together to avoid such 1596 * collisions. 1597 */ 1598 if (t->dc_vid == DC_VENDORID_MICROSOFT && 1599 t->dc_did == DC_DEVICEID_MSMN130) 1600 t++; 1601 return (t); 1602 } 1603 t++; 1604 } 1605 1606 return (NULL); 1607 } 1608 1609 /* 1610 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1611 * IDs against our list and return a device name if we find a match. 1612 * We do a little bit of extra work to identify the exact type of 1613 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1614 * but different revision IDs. The same is true for 98715/98715A 1615 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1616 * cases, the exact chip revision affects driver behavior. 1617 */ 1618 static int 1619 dc_probe(device_t dev) 1620 { 1621 struct dc_type *t; 1622 1623 t = dc_devtype(dev); 1624 1625 if (t != NULL) { 1626 device_set_desc(dev, t->dc_name); 1627 return (0); 1628 } 1629 1630 return (ENXIO); 1631 } 1632 1633 #ifndef BURN_BRIDGES 1634 static void 1635 dc_acpi(device_t dev) 1636 { 1637 int unit; 1638 u_int32_t iobase, membase, irq; 1639 1640 unit = device_get_unit(dev); 1641 1642 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1643 /* Save important PCI config data. */ 1644 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4); 1645 membase = pci_read_config(dev, DC_PCI_CFBMA, 4); 1646 irq = pci_read_config(dev, DC_PCI_CFIT, 4); 1647 1648 /* Reset the power state. */ 1649 printf("dc%d: chip is in D%d power mode " 1650 "-- setting to D0\n", unit, 1651 pci_get_powerstate(dev)); 1652 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1653 1654 /* Restore PCI config data. */ 1655 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4); 1656 pci_write_config(dev, DC_PCI_CFBMA, membase, 4); 1657 pci_write_config(dev, DC_PCI_CFIT, irq, 4); 1658 } 1659 } 1660 #endif 1661 1662 static void 1663 dc_apply_fixup(struct dc_softc *sc, int media) 1664 { 1665 struct dc_mediainfo *m; 1666 u_int8_t *p; 1667 int i; 1668 u_int32_t reg; 1669 1670 m = sc->dc_mi; 1671 1672 while (m != NULL) { 1673 if (m->dc_media == media) 1674 break; 1675 m = m->dc_next; 1676 } 1677 1678 if (m == NULL) 1679 return; 1680 1681 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1682 reg = (p[0] | (p[1] << 8)) << 16; 1683 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1684 } 1685 1686 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1687 reg = (p[0] | (p[1] << 8)) << 16; 1688 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1689 } 1690 } 1691 1692 static void 1693 dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l) 1694 { 1695 struct dc_mediainfo *m; 1696 1697 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1698 switch (l->dc_sia_code & ~DC_SIA_CODE_EXT) { 1699 case DC_SIA_CODE_10BT: 1700 m->dc_media = IFM_10_T; 1701 break; 1702 case DC_SIA_CODE_10BT_FDX: 1703 m->dc_media = IFM_10_T | IFM_FDX; 1704 break; 1705 case DC_SIA_CODE_10B2: 1706 m->dc_media = IFM_10_2; 1707 break; 1708 case DC_SIA_CODE_10B5: 1709 m->dc_media = IFM_10_5; 1710 break; 1711 default: 1712 break; 1713 } 1714 1715 /* 1716 * We need to ignore CSR13, CSR14, CSR15 for SIA mode. 1717 * Things apparently already work for cards that do 1718 * supply Media Specific Data. 1719 */ 1720 if (l->dc_sia_code & DC_SIA_CODE_EXT) { 1721 m->dc_gp_len = 2; 1722 m->dc_gp_ptr = 1723 (u_int8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl; 1724 } else { 1725 m->dc_gp_len = 2; 1726 m->dc_gp_ptr = 1727 (u_int8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl; 1728 } 1729 1730 m->dc_next = sc->dc_mi; 1731 sc->dc_mi = m; 1732 1733 sc->dc_pmode = DC_PMODE_SIA; 1734 } 1735 1736 static void 1737 dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l) 1738 { 1739 struct dc_mediainfo *m; 1740 1741 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1742 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1743 m->dc_media = IFM_100_TX; 1744 1745 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1746 m->dc_media = IFM_100_TX | IFM_FDX; 1747 1748 m->dc_gp_len = 2; 1749 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1750 1751 m->dc_next = sc->dc_mi; 1752 sc->dc_mi = m; 1753 1754 sc->dc_pmode = DC_PMODE_SYM; 1755 } 1756 1757 static void 1758 dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l) 1759 { 1760 struct dc_mediainfo *m; 1761 u_int8_t *p; 1762 1763 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1764 /* We abuse IFM_AUTO to represent MII. */ 1765 m->dc_media = IFM_AUTO; 1766 m->dc_gp_len = l->dc_gpr_len; 1767 1768 p = (u_int8_t *)l; 1769 p += sizeof(struct dc_eblock_mii); 1770 m->dc_gp_ptr = p; 1771 p += 2 * l->dc_gpr_len; 1772 m->dc_reset_len = *p; 1773 p++; 1774 m->dc_reset_ptr = p; 1775 1776 m->dc_next = sc->dc_mi; 1777 sc->dc_mi = m; 1778 } 1779 1780 static void 1781 dc_read_srom(struct dc_softc *sc, int bits) 1782 { 1783 int size; 1784 1785 size = 2 << bits; 1786 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT); 1787 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); 1788 } 1789 1790 static void 1791 dc_parse_21143_srom(struct dc_softc *sc) 1792 { 1793 struct dc_leaf_hdr *lhdr; 1794 struct dc_eblock_hdr *hdr; 1795 int have_mii, i, loff; 1796 char *ptr; 1797 1798 have_mii = 0; 1799 loff = sc->dc_srom[27]; 1800 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1801 1802 ptr = (char *)lhdr; 1803 ptr += sizeof(struct dc_leaf_hdr) - 1; 1804 /* 1805 * Look if we got a MII media block. 1806 */ 1807 for (i = 0; i < lhdr->dc_mcnt; i++) { 1808 hdr = (struct dc_eblock_hdr *)ptr; 1809 if (hdr->dc_type == DC_EBLOCK_MII) 1810 have_mii++; 1811 1812 ptr += (hdr->dc_len & 0x7F); 1813 ptr++; 1814 } 1815 1816 /* 1817 * Do the same thing again. Only use SIA and SYM media 1818 * blocks if no MII media block is available. 1819 */ 1820 ptr = (char *)lhdr; 1821 ptr += sizeof(struct dc_leaf_hdr) - 1; 1822 for (i = 0; i < lhdr->dc_mcnt; i++) { 1823 hdr = (struct dc_eblock_hdr *)ptr; 1824 switch (hdr->dc_type) { 1825 case DC_EBLOCK_MII: 1826 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1827 break; 1828 case DC_EBLOCK_SIA: 1829 if (! have_mii) 1830 dc_decode_leaf_sia(sc, 1831 (struct dc_eblock_sia *)hdr); 1832 break; 1833 case DC_EBLOCK_SYM: 1834 if (! have_mii) 1835 dc_decode_leaf_sym(sc, 1836 (struct dc_eblock_sym *)hdr); 1837 break; 1838 default: 1839 /* Don't care. Yet. */ 1840 break; 1841 } 1842 ptr += (hdr->dc_len & 0x7F); 1843 ptr++; 1844 } 1845 } 1846 1847 static void 1848 dc_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1849 { 1850 u_int32_t *paddr; 1851 1852 KASSERT(nseg == 1, ("wrong number of segments, should be 1")); 1853 paddr = arg; 1854 *paddr = segs->ds_addr; 1855 } 1856 1857 /* 1858 * Attach the interface. Allocate softc structures, do ifmedia 1859 * setup and ethernet/BPF attach. 1860 */ 1861 static int 1862 dc_attach(device_t dev) 1863 { 1864 int tmp = 0; 1865 u_char eaddr[ETHER_ADDR_LEN]; 1866 u_int32_t command; 1867 struct dc_softc *sc; 1868 struct ifnet *ifp; 1869 u_int32_t revision; 1870 int unit, error = 0, rid, mac_offset; 1871 int i; 1872 u_int8_t *mac; 1873 1874 sc = device_get_softc(dev); 1875 unit = device_get_unit(dev); 1876 1877 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1878 MTX_DEF | MTX_RECURSE); 1879 #ifndef BURN_BRIDGES 1880 /* 1881 * Handle power management nonsense. 1882 */ 1883 dc_acpi(dev); 1884 #endif 1885 /* 1886 * Map control/status registers. 1887 */ 1888 pci_enable_busmaster(dev); 1889 1890 rid = DC_RID; 1891 sc->dc_res = bus_alloc_resource_any(dev, DC_RES, &rid, RF_ACTIVE); 1892 1893 if (sc->dc_res == NULL) { 1894 printf("dc%d: couldn't map ports/memory\n", unit); 1895 error = ENXIO; 1896 goto fail; 1897 } 1898 1899 sc->dc_btag = rman_get_bustag(sc->dc_res); 1900 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1901 1902 /* Allocate interrupt. */ 1903 rid = 0; 1904 sc->dc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1905 RF_SHAREABLE | RF_ACTIVE); 1906 1907 if (sc->dc_irq == NULL) { 1908 printf("dc%d: couldn't map interrupt\n", unit); 1909 error = ENXIO; 1910 goto fail; 1911 } 1912 1913 /* Need this info to decide on a chip type. */ 1914 sc->dc_info = dc_devtype(dev); 1915 revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF; 1916 1917 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */ 1918 if (sc->dc_info->dc_did != DC_DEVICEID_82C168 && 1919 sc->dc_info->dc_did != DC_DEVICEID_X3201) 1920 dc_eeprom_width(sc); 1921 1922 switch (sc->dc_info->dc_did) { 1923 case DC_DEVICEID_21143: 1924 sc->dc_type = DC_TYPE_21143; 1925 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1926 sc->dc_flags |= DC_REDUCED_MII_POLL; 1927 /* Save EEPROM contents so we can parse them later. */ 1928 dc_read_srom(sc, sc->dc_romwidth); 1929 break; 1930 case DC_DEVICEID_DM9009: 1931 case DC_DEVICEID_DM9100: 1932 case DC_DEVICEID_DM9102: 1933 sc->dc_type = DC_TYPE_DM9102; 1934 sc->dc_flags |= DC_TX_COALESCE | DC_TX_INTR_ALWAYS; 1935 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_TX_STORENFWD; 1936 sc->dc_flags |= DC_TX_ALIGN; 1937 sc->dc_pmode = DC_PMODE_MII; 1938 /* Increase the latency timer value. */ 1939 command = pci_read_config(dev, DC_PCI_CFLT, 4); 1940 command &= 0xFFFF00FF; 1941 command |= 0x00008000; 1942 pci_write_config(dev, DC_PCI_CFLT, command, 4); 1943 break; 1944 case DC_DEVICEID_AL981: 1945 sc->dc_type = DC_TYPE_AL981; 1946 sc->dc_flags |= DC_TX_USE_TX_INTR; 1947 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1948 sc->dc_pmode = DC_PMODE_MII; 1949 dc_read_srom(sc, sc->dc_romwidth); 1950 break; 1951 case DC_DEVICEID_AN985: 1952 case DC_DEVICEID_ADM9511: 1953 case DC_DEVICEID_ADM9513: 1954 case DC_DEVICEID_FA511: 1955 case DC_DEVICEID_FE2500: 1956 case DC_DEVICEID_EN2242: 1957 case DC_DEVICEID_HAWKING_PN672TX: 1958 case DC_DEVICEID_3CSOHOB: 1959 case DC_DEVICEID_MSMN120: 1960 case DC_DEVICEID_MSMN130_FAKE: /* XXX avoid collision with PNIC*/ 1961 sc->dc_type = DC_TYPE_AN985; 1962 sc->dc_flags |= DC_64BIT_HASH; 1963 sc->dc_flags |= DC_TX_USE_TX_INTR; 1964 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1965 sc->dc_pmode = DC_PMODE_MII; 1966 /* Don't read SROM for - auto-loaded on reset */ 1967 break; 1968 case DC_DEVICEID_98713: 1969 case DC_DEVICEID_98713_CP: 1970 if (revision < DC_REVISION_98713A) { 1971 sc->dc_type = DC_TYPE_98713; 1972 } 1973 if (revision >= DC_REVISION_98713A) { 1974 sc->dc_type = DC_TYPE_98713A; 1975 sc->dc_flags |= DC_21143_NWAY; 1976 } 1977 sc->dc_flags |= DC_REDUCED_MII_POLL; 1978 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1979 break; 1980 case DC_DEVICEID_987x5: 1981 case DC_DEVICEID_EN1217: 1982 /* 1983 * Macronix MX98715AEC-C/D/E parts have only a 1984 * 128-bit hash table. We need to deal with these 1985 * in the same manner as the PNIC II so that we 1986 * get the right number of bits out of the 1987 * CRC routine. 1988 */ 1989 if (revision >= DC_REVISION_98715AEC_C && 1990 revision < DC_REVISION_98725) 1991 sc->dc_flags |= DC_128BIT_HASH; 1992 sc->dc_type = DC_TYPE_987x5; 1993 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1994 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1995 break; 1996 case DC_DEVICEID_98727: 1997 sc->dc_type = DC_TYPE_987x5; 1998 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1999 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 2000 break; 2001 case DC_DEVICEID_82C115: 2002 sc->dc_type = DC_TYPE_PNICII; 2003 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR | DC_128BIT_HASH; 2004 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 2005 break; 2006 case DC_DEVICEID_82C168: 2007 sc->dc_type = DC_TYPE_PNIC; 2008 sc->dc_flags |= DC_TX_STORENFWD | DC_TX_INTR_ALWAYS; 2009 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 2010 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 2011 if (revision < DC_REVISION_82C169) 2012 sc->dc_pmode = DC_PMODE_SYM; 2013 break; 2014 case DC_DEVICEID_AX88140A: 2015 sc->dc_type = DC_TYPE_ASIX; 2016 sc->dc_flags |= DC_TX_USE_TX_INTR | DC_TX_INTR_FIRSTFRAG; 2017 sc->dc_flags |= DC_REDUCED_MII_POLL; 2018 sc->dc_pmode = DC_PMODE_MII; 2019 break; 2020 case DC_DEVICEID_X3201: 2021 sc->dc_type = DC_TYPE_XIRCOM; 2022 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 2023 DC_TX_ALIGN; 2024 /* 2025 * We don't actually need to coalesce, but we're doing 2026 * it to obtain a double word aligned buffer. 2027 * The DC_TX_COALESCE flag is required. 2028 */ 2029 sc->dc_pmode = DC_PMODE_MII; 2030 break; 2031 case DC_DEVICEID_RS7112: 2032 sc->dc_type = DC_TYPE_CONEXANT; 2033 sc->dc_flags |= DC_TX_INTR_ALWAYS; 2034 sc->dc_flags |= DC_REDUCED_MII_POLL; 2035 sc->dc_pmode = DC_PMODE_MII; 2036 dc_read_srom(sc, sc->dc_romwidth); 2037 break; 2038 default: 2039 printf("dc%d: unknown device: %x\n", sc->dc_unit, 2040 sc->dc_info->dc_did); 2041 break; 2042 } 2043 2044 /* Save the cache line size. */ 2045 if (DC_IS_DAVICOM(sc)) 2046 sc->dc_cachesize = 0; 2047 else 2048 sc->dc_cachesize = pci_read_config(dev, 2049 DC_PCI_CFLT, 4) & 0xFF; 2050 2051 /* Reset the adapter. */ 2052 dc_reset(sc); 2053 2054 /* Take 21143 out of snooze mode */ 2055 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 2056 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2057 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 2058 pci_write_config(dev, DC_PCI_CFDD, command, 4); 2059 } 2060 2061 /* 2062 * Try to learn something about the supported media. 2063 * We know that ASIX and ADMtek and Davicom devices 2064 * will *always* be using MII media, so that's a no-brainer. 2065 * The tricky ones are the Macronix/PNIC II and the 2066 * Intel 21143. 2067 */ 2068 if (DC_IS_INTEL(sc)) 2069 dc_parse_21143_srom(sc); 2070 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2071 if (sc->dc_type == DC_TYPE_98713) 2072 sc->dc_pmode = DC_PMODE_MII; 2073 else 2074 sc->dc_pmode = DC_PMODE_SYM; 2075 } else if (!sc->dc_pmode) 2076 sc->dc_pmode = DC_PMODE_MII; 2077 2078 /* 2079 * Get station address from the EEPROM. 2080 */ 2081 switch(sc->dc_type) { 2082 case DC_TYPE_98713: 2083 case DC_TYPE_98713A: 2084 case DC_TYPE_987x5: 2085 case DC_TYPE_PNICII: 2086 dc_read_eeprom(sc, (caddr_t)&mac_offset, 2087 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2088 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2089 break; 2090 case DC_TYPE_PNIC: 2091 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2092 break; 2093 case DC_TYPE_DM9102: 2094 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2095 #ifdef __sparc64__ 2096 /* 2097 * If this is an onboard dc(4) the station address read from 2098 * the EEPROM is all zero and we have to get it from the fcode. 2099 */ 2100 for (i = 0; i < ETHER_ADDR_LEN; i++) 2101 if (eaddr[i] != 0x00) 2102 break; 2103 if (i >= ETHER_ADDR_LEN && OF_getetheraddr2(dev, eaddr) == -1) 2104 OF_getetheraddr(dev, eaddr); 2105 #endif 2106 break; 2107 case DC_TYPE_21143: 2108 case DC_TYPE_ASIX: 2109 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2110 break; 2111 case DC_TYPE_AL981: 2112 case DC_TYPE_AN985: 2113 *(u_int32_t *)(&eaddr[0]) = CSR_READ_4(sc, DC_AL_PAR0); 2114 *(u_int16_t *)(&eaddr[4]) = CSR_READ_4(sc, DC_AL_PAR1); 2115 break; 2116 case DC_TYPE_CONEXANT: 2117 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 2118 ETHER_ADDR_LEN); 2119 break; 2120 case DC_TYPE_XIRCOM: 2121 /* The MAC comes from the CIS. */ 2122 mac = pci_get_ether(dev); 2123 if (!mac) { 2124 device_printf(dev, "No station address in CIS!\n"); 2125 error = ENXIO; 2126 goto fail; 2127 } 2128 bcopy(mac, eaddr, ETHER_ADDR_LEN); 2129 break; 2130 default: 2131 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2132 break; 2133 } 2134 2135 sc->dc_unit = unit; 2136 bcopy(eaddr, &sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 2137 2138 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */ 2139 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 2140 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct dc_list_data), 1, 2141 sizeof(struct dc_list_data), 0, NULL, NULL, &sc->dc_ltag); 2142 if (error) { 2143 printf("dc%d: failed to allocate busdma tag\n", unit); 2144 error = ENXIO; 2145 goto fail; 2146 } 2147 error = bus_dmamem_alloc(sc->dc_ltag, (void **)&sc->dc_ldata, 2148 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->dc_lmap); 2149 if (error) { 2150 printf("dc%d: failed to allocate DMA safe memory\n", unit); 2151 error = ENXIO; 2152 goto fail; 2153 } 2154 error = bus_dmamap_load(sc->dc_ltag, sc->dc_lmap, sc->dc_ldata, 2155 sizeof(struct dc_list_data), dc_dma_map_addr, &sc->dc_laddr, 2156 BUS_DMA_NOWAIT); 2157 if (error) { 2158 printf("dc%d: cannot get address of the descriptors\n", unit); 2159 error = ENXIO; 2160 goto fail; 2161 } 2162 2163 /* 2164 * Allocate a busdma tag and DMA safe memory for the multicast 2165 * setup frame. 2166 */ 2167 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 2168 BUS_SPACE_MAXADDR, NULL, NULL, DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1, 2169 DC_SFRAME_LEN + DC_MIN_FRAMELEN, 0, NULL, NULL, &sc->dc_stag); 2170 if (error) { 2171 printf("dc%d: failed to allocate busdma tag\n", unit); 2172 error = ENXIO; 2173 goto fail; 2174 } 2175 error = bus_dmamem_alloc(sc->dc_stag, (void **)&sc->dc_cdata.dc_sbuf, 2176 BUS_DMA_NOWAIT, &sc->dc_smap); 2177 if (error) { 2178 printf("dc%d: failed to allocate DMA safe memory\n", unit); 2179 error = ENXIO; 2180 goto fail; 2181 } 2182 error = bus_dmamap_load(sc->dc_stag, sc->dc_smap, sc->dc_cdata.dc_sbuf, 2183 DC_SFRAME_LEN, dc_dma_map_addr, &sc->dc_saddr, BUS_DMA_NOWAIT); 2184 if (error) { 2185 printf("dc%d: cannot get address of the descriptors\n", unit); 2186 error = ENXIO; 2187 goto fail; 2188 } 2189 2190 /* Allocate a busdma tag for mbufs. */ 2191 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 2192 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * DC_TX_LIST_CNT, 2193 DC_TX_LIST_CNT, MCLBYTES, 0, NULL, NULL, &sc->dc_mtag); 2194 if (error) { 2195 printf("dc%d: failed to allocate busdma tag\n", unit); 2196 error = ENXIO; 2197 goto fail; 2198 } 2199 2200 /* Create the TX/RX busdma maps. */ 2201 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2202 error = bus_dmamap_create(sc->dc_mtag, 0, 2203 &sc->dc_cdata.dc_tx_map[i]); 2204 if (error) { 2205 printf("dc%d: failed to init TX ring\n", unit); 2206 error = ENXIO; 2207 goto fail; 2208 } 2209 } 2210 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2211 error = bus_dmamap_create(sc->dc_mtag, 0, 2212 &sc->dc_cdata.dc_rx_map[i]); 2213 if (error) { 2214 printf("dc%d: failed to init RX ring\n", unit); 2215 error = ENXIO; 2216 goto fail; 2217 } 2218 } 2219 error = bus_dmamap_create(sc->dc_mtag, 0, &sc->dc_sparemap); 2220 if (error) { 2221 printf("dc%d: failed to init RX ring\n", unit); 2222 error = ENXIO; 2223 goto fail; 2224 } 2225 2226 ifp = &sc->arpcom.ac_if; 2227 ifp->if_softc = sc; 2228 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2229 /* XXX: bleah, MTU gets overwritten in ether_ifattach() */ 2230 ifp->if_mtu = ETHERMTU; 2231 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2232 ifp->if_ioctl = dc_ioctl; 2233 ifp->if_start = dc_start; 2234 ifp->if_watchdog = dc_watchdog; 2235 ifp->if_init = dc_init; 2236 ifp->if_baudrate = 10000000; 2237 ifp->if_snd.ifq_maxlen = DC_TX_LIST_CNT - 1; 2238 2239 /* 2240 * Do MII setup. If this is a 21143, check for a PHY on the 2241 * MII bus after applying any necessary fixups to twiddle the 2242 * GPIO bits. If we don't end up finding a PHY, restore the 2243 * old selection (SIA only or SIA/SYM) and attach the dcphy 2244 * driver instead. 2245 */ 2246 if (DC_IS_INTEL(sc)) { 2247 dc_apply_fixup(sc, IFM_AUTO); 2248 tmp = sc->dc_pmode; 2249 sc->dc_pmode = DC_PMODE_MII; 2250 } 2251 2252 error = mii_phy_probe(dev, &sc->dc_miibus, 2253 dc_ifmedia_upd, dc_ifmedia_sts); 2254 2255 if (error && DC_IS_INTEL(sc)) { 2256 sc->dc_pmode = tmp; 2257 if (sc->dc_pmode != DC_PMODE_SIA) 2258 sc->dc_pmode = DC_PMODE_SYM; 2259 sc->dc_flags |= DC_21143_NWAY; 2260 mii_phy_probe(dev, &sc->dc_miibus, 2261 dc_ifmedia_upd, dc_ifmedia_sts); 2262 /* 2263 * For non-MII cards, we need to have the 21143 2264 * drive the LEDs. Except there are some systems 2265 * like the NEC VersaPro NoteBook PC which have no 2266 * LEDs, and twiddling these bits has adverse effects 2267 * on them. (I.e. you suddenly can't get a link.) 2268 */ 2269 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033) 2270 sc->dc_flags |= DC_TULIP_LEDS; 2271 error = 0; 2272 } 2273 2274 if (error) { 2275 printf("dc%d: MII without any PHY!\n", sc->dc_unit); 2276 goto fail; 2277 } 2278 2279 if (DC_IS_XIRCOM(sc)) { 2280 /* 2281 * setup General Purpose Port mode and data so the tulip 2282 * can talk to the MII. 2283 */ 2284 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2285 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2286 DELAY(10); 2287 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2288 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2289 DELAY(10); 2290 } 2291 2292 if (DC_IS_ADMTEK(sc)) { 2293 /* 2294 * Set automatic TX underrun recovery for the ADMtek chips 2295 */ 2296 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); 2297 } 2298 2299 /* 2300 * Tell the upper layer(s) we support long frames. 2301 */ 2302 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2303 ifp->if_capabilities |= IFCAP_VLAN_MTU; 2304 #ifdef DEVICE_POLLING 2305 ifp->if_capabilities |= IFCAP_POLLING; 2306 #endif 2307 ifp->if_capenable = ifp->if_capabilities; 2308 2309 callout_init(&sc->dc_stat_ch, IS_MPSAFE ? CALLOUT_MPSAFE : 0); 2310 2311 #ifdef SRM_MEDIA 2312 sc->dc_srm_media = 0; 2313 2314 /* Remember the SRM console media setting */ 2315 if (DC_IS_INTEL(sc)) { 2316 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2317 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 2318 switch ((command >> 8) & 0xff) { 2319 case 3: 2320 sc->dc_srm_media = IFM_10_T; 2321 break; 2322 case 4: 2323 sc->dc_srm_media = IFM_10_T | IFM_FDX; 2324 break; 2325 case 5: 2326 sc->dc_srm_media = IFM_100_TX; 2327 break; 2328 case 6: 2329 sc->dc_srm_media = IFM_100_TX | IFM_FDX; 2330 break; 2331 } 2332 if (sc->dc_srm_media) 2333 sc->dc_srm_media |= IFM_ACTIVE | IFM_ETHER; 2334 } 2335 #endif 2336 2337 /* 2338 * Call MI attach routine. 2339 */ 2340 ether_ifattach(ifp, eaddr); 2341 2342 /* Hook interrupt last to avoid having to lock softc */ 2343 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | 2344 (IS_MPSAFE ? INTR_MPSAFE : 0), 2345 dc_intr, sc, &sc->dc_intrhand); 2346 2347 if (error) { 2348 printf("dc%d: couldn't set up irq\n", unit); 2349 ether_ifdetach(ifp); 2350 goto fail; 2351 } 2352 2353 fail: 2354 if (error) 2355 dc_detach(dev); 2356 return (error); 2357 } 2358 2359 /* 2360 * Shutdown hardware and free up resources. This can be called any 2361 * time after the mutex has been initialized. It is called in both 2362 * the error case in attach and the normal detach case so it needs 2363 * to be careful about only freeing resources that have actually been 2364 * allocated. 2365 */ 2366 static int 2367 dc_detach(device_t dev) 2368 { 2369 struct dc_softc *sc; 2370 struct ifnet *ifp; 2371 struct dc_mediainfo *m; 2372 int i; 2373 2374 sc = device_get_softc(dev); 2375 KASSERT(mtx_initialized(&sc->dc_mtx), ("dc mutex not initialized")); 2376 DC_LOCK(sc); 2377 2378 ifp = &sc->arpcom.ac_if; 2379 2380 /* These should only be active if attach succeeded */ 2381 if (device_is_attached(dev)) { 2382 dc_stop(sc); 2383 ether_ifdetach(ifp); 2384 } 2385 if (sc->dc_miibus) 2386 device_delete_child(dev, sc->dc_miibus); 2387 bus_generic_detach(dev); 2388 2389 if (sc->dc_intrhand) 2390 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2391 if (sc->dc_irq) 2392 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2393 if (sc->dc_res) 2394 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2395 2396 if (sc->dc_cdata.dc_sbuf != NULL) 2397 bus_dmamem_free(sc->dc_stag, sc->dc_cdata.dc_sbuf, sc->dc_smap); 2398 if (sc->dc_ldata != NULL) 2399 bus_dmamem_free(sc->dc_ltag, sc->dc_ldata, sc->dc_lmap); 2400 for (i = 0; i < DC_TX_LIST_CNT; i++) 2401 bus_dmamap_destroy(sc->dc_mtag, sc->dc_cdata.dc_tx_map[i]); 2402 for (i = 0; i < DC_RX_LIST_CNT; i++) 2403 bus_dmamap_destroy(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i]); 2404 bus_dmamap_destroy(sc->dc_mtag, sc->dc_sparemap); 2405 if (sc->dc_stag) 2406 bus_dma_tag_destroy(sc->dc_stag); 2407 if (sc->dc_mtag) 2408 bus_dma_tag_destroy(sc->dc_mtag); 2409 if (sc->dc_ltag) 2410 bus_dma_tag_destroy(sc->dc_ltag); 2411 2412 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2413 2414 while (sc->dc_mi != NULL) { 2415 m = sc->dc_mi->dc_next; 2416 free(sc->dc_mi, M_DEVBUF); 2417 sc->dc_mi = m; 2418 } 2419 free(sc->dc_srom, M_DEVBUF); 2420 2421 DC_UNLOCK(sc); 2422 mtx_destroy(&sc->dc_mtx); 2423 2424 return (0); 2425 } 2426 2427 /* 2428 * Initialize the transmit descriptors. 2429 */ 2430 static int 2431 dc_list_tx_init(struct dc_softc *sc) 2432 { 2433 struct dc_chain_data *cd; 2434 struct dc_list_data *ld; 2435 int i, nexti; 2436 2437 cd = &sc->dc_cdata; 2438 ld = sc->dc_ldata; 2439 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2440 if (i == DC_TX_LIST_CNT - 1) 2441 nexti = 0; 2442 else 2443 nexti = i + 1; 2444 ld->dc_tx_list[i].dc_next = htole32(DC_TXDESC(sc, nexti)); 2445 cd->dc_tx_chain[i] = NULL; 2446 ld->dc_tx_list[i].dc_data = 0; 2447 ld->dc_tx_list[i].dc_ctl = 0; 2448 } 2449 2450 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2451 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2452 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2453 return (0); 2454 } 2455 2456 2457 /* 2458 * Initialize the RX descriptors and allocate mbufs for them. Note that 2459 * we arrange the descriptors in a closed ring, so that the last descriptor 2460 * points back to the first. 2461 */ 2462 static int 2463 dc_list_rx_init(struct dc_softc *sc) 2464 { 2465 struct dc_chain_data *cd; 2466 struct dc_list_data *ld; 2467 int i, nexti; 2468 2469 cd = &sc->dc_cdata; 2470 ld = sc->dc_ldata; 2471 2472 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2473 if (dc_newbuf(sc, i, 1) != 0) 2474 return (ENOBUFS); 2475 if (i == DC_RX_LIST_CNT - 1) 2476 nexti = 0; 2477 else 2478 nexti = i + 1; 2479 ld->dc_rx_list[i].dc_next = htole32(DC_RXDESC(sc, nexti)); 2480 } 2481 2482 cd->dc_rx_prod = 0; 2483 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2484 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2485 return (0); 2486 } 2487 2488 static void 2489 dc_dma_map_rxbuf(arg, segs, nseg, mapsize, error) 2490 void *arg; 2491 bus_dma_segment_t *segs; 2492 int nseg; 2493 bus_size_t mapsize; 2494 int error; 2495 { 2496 struct dc_softc *sc; 2497 struct dc_desc *c; 2498 2499 sc = arg; 2500 c = &sc->dc_ldata->dc_rx_list[sc->dc_cdata.dc_rx_cur]; 2501 if (error) { 2502 sc->dc_cdata.dc_rx_err = error; 2503 return; 2504 } 2505 2506 KASSERT(nseg == 1, ("wrong number of segments, should be 1")); 2507 sc->dc_cdata.dc_rx_err = 0; 2508 c->dc_data = htole32(segs->ds_addr); 2509 } 2510 2511 /* 2512 * Initialize an RX descriptor and attach an MBUF cluster. 2513 */ 2514 static int 2515 dc_newbuf(struct dc_softc *sc, int i, int alloc) 2516 { 2517 struct mbuf *m_new; 2518 bus_dmamap_t tmp; 2519 int error; 2520 2521 if (alloc) { 2522 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2523 if (m_new == NULL) 2524 return (ENOBUFS); 2525 } else { 2526 m_new = sc->dc_cdata.dc_rx_chain[i]; 2527 m_new->m_data = m_new->m_ext.ext_buf; 2528 } 2529 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2530 m_adj(m_new, sizeof(u_int64_t)); 2531 2532 /* 2533 * If this is a PNIC chip, zero the buffer. This is part 2534 * of the workaround for the receive bug in the 82c168 and 2535 * 82c169 chips. 2536 */ 2537 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2538 bzero(mtod(m_new, char *), m_new->m_len); 2539 2540 /* No need to remap the mbuf if we're reusing it. */ 2541 if (alloc) { 2542 sc->dc_cdata.dc_rx_cur = i; 2543 error = bus_dmamap_load_mbuf(sc->dc_mtag, sc->dc_sparemap, 2544 m_new, dc_dma_map_rxbuf, sc, 0); 2545 if (error) { 2546 m_freem(m_new); 2547 return (error); 2548 } 2549 if (sc->dc_cdata.dc_rx_err != 0) { 2550 m_freem(m_new); 2551 return (sc->dc_cdata.dc_rx_err); 2552 } 2553 bus_dmamap_unload(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i]); 2554 tmp = sc->dc_cdata.dc_rx_map[i]; 2555 sc->dc_cdata.dc_rx_map[i] = sc->dc_sparemap; 2556 sc->dc_sparemap = tmp; 2557 sc->dc_cdata.dc_rx_chain[i] = m_new; 2558 } 2559 2560 sc->dc_ldata->dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN); 2561 sc->dc_ldata->dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN); 2562 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i], 2563 BUS_DMASYNC_PREREAD); 2564 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2565 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2566 return (0); 2567 } 2568 2569 /* 2570 * Grrrrr. 2571 * The PNIC chip has a terrible bug in it that manifests itself during 2572 * periods of heavy activity. The exact mode of failure if difficult to 2573 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2574 * will happen on slow machines. The bug is that sometimes instead of 2575 * uploading one complete frame during reception, it uploads what looks 2576 * like the entire contents of its FIFO memory. The frame we want is at 2577 * the end of the whole mess, but we never know exactly how much data has 2578 * been uploaded, so salvaging the frame is hard. 2579 * 2580 * There is only one way to do it reliably, and it's disgusting. 2581 * Here's what we know: 2582 * 2583 * - We know there will always be somewhere between one and three extra 2584 * descriptors uploaded. 2585 * 2586 * - We know the desired received frame will always be at the end of the 2587 * total data upload. 2588 * 2589 * - We know the size of the desired received frame because it will be 2590 * provided in the length field of the status word in the last descriptor. 2591 * 2592 * Here's what we do: 2593 * 2594 * - When we allocate buffers for the receive ring, we bzero() them. 2595 * This means that we know that the buffer contents should be all 2596 * zeros, except for data uploaded by the chip. 2597 * 2598 * - We also force the PNIC chip to upload frames that include the 2599 * ethernet CRC at the end. 2600 * 2601 * - We gather all of the bogus frame data into a single buffer. 2602 * 2603 * - We then position a pointer at the end of this buffer and scan 2604 * backwards until we encounter the first non-zero byte of data. 2605 * This is the end of the received frame. We know we will encounter 2606 * some data at the end of the frame because the CRC will always be 2607 * there, so even if the sender transmits a packet of all zeros, 2608 * we won't be fooled. 2609 * 2610 * - We know the size of the actual received frame, so we subtract 2611 * that value from the current pointer location. This brings us 2612 * to the start of the actual received packet. 2613 * 2614 * - We copy this into an mbuf and pass it on, along with the actual 2615 * frame length. 2616 * 2617 * The performance hit is tremendous, but it beats dropping frames all 2618 * the time. 2619 */ 2620 2621 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG | DC_RXSTAT_LASTFRAG) 2622 static void 2623 dc_pnic_rx_bug_war(struct dc_softc *sc, int idx) 2624 { 2625 struct dc_desc *cur_rx; 2626 struct dc_desc *c = NULL; 2627 struct mbuf *m = NULL; 2628 unsigned char *ptr; 2629 int i, total_len; 2630 u_int32_t rxstat = 0; 2631 2632 i = sc->dc_pnic_rx_bug_save; 2633 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2634 ptr = sc->dc_pnic_rx_buf; 2635 bzero(ptr, DC_RXLEN * 5); 2636 2637 /* Copy all the bytes from the bogus buffers. */ 2638 while (1) { 2639 c = &sc->dc_ldata->dc_rx_list[i]; 2640 rxstat = le32toh(c->dc_status); 2641 m = sc->dc_cdata.dc_rx_chain[i]; 2642 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2643 ptr += DC_RXLEN; 2644 /* If this is the last buffer, break out. */ 2645 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2646 break; 2647 dc_newbuf(sc, i, 0); 2648 DC_INC(i, DC_RX_LIST_CNT); 2649 } 2650 2651 /* Find the length of the actual receive frame. */ 2652 total_len = DC_RXBYTES(rxstat); 2653 2654 /* Scan backwards until we hit a non-zero byte. */ 2655 while (*ptr == 0x00) 2656 ptr--; 2657 2658 /* Round off. */ 2659 if ((uintptr_t)(ptr) & 0x3) 2660 ptr -= 1; 2661 2662 /* Now find the start of the frame. */ 2663 ptr -= total_len; 2664 if (ptr < sc->dc_pnic_rx_buf) 2665 ptr = sc->dc_pnic_rx_buf; 2666 2667 /* 2668 * Now copy the salvaged frame to the last mbuf and fake up 2669 * the status word to make it look like a successful 2670 * frame reception. 2671 */ 2672 dc_newbuf(sc, i, 0); 2673 bcopy(ptr, mtod(m, char *), total_len); 2674 cur_rx->dc_status = htole32(rxstat | DC_RXSTAT_FIRSTFRAG); 2675 } 2676 2677 /* 2678 * This routine searches the RX ring for dirty descriptors in the 2679 * event that the rxeof routine falls out of sync with the chip's 2680 * current descriptor pointer. This may happen sometimes as a result 2681 * of a "no RX buffer available" condition that happens when the chip 2682 * consumes all of the RX buffers before the driver has a chance to 2683 * process the RX ring. This routine may need to be called more than 2684 * once to bring the driver back in sync with the chip, however we 2685 * should still be getting RX DONE interrupts to drive the search 2686 * for new packets in the RX ring, so we should catch up eventually. 2687 */ 2688 static int 2689 dc_rx_resync(struct dc_softc *sc) 2690 { 2691 struct dc_desc *cur_rx; 2692 int i, pos; 2693 2694 pos = sc->dc_cdata.dc_rx_prod; 2695 2696 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2697 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2698 if (!(le32toh(cur_rx->dc_status) & DC_RXSTAT_OWN)) 2699 break; 2700 DC_INC(pos, DC_RX_LIST_CNT); 2701 } 2702 2703 /* If the ring really is empty, then just return. */ 2704 if (i == DC_RX_LIST_CNT) 2705 return (0); 2706 2707 /* We've fallen behing the chip: catch it. */ 2708 sc->dc_cdata.dc_rx_prod = pos; 2709 2710 return (EAGAIN); 2711 } 2712 2713 /* 2714 * A frame has been uploaded: pass the resulting mbuf chain up to 2715 * the higher level protocols. 2716 */ 2717 static void 2718 dc_rxeof(struct dc_softc *sc) 2719 { 2720 struct mbuf *m; 2721 struct ifnet *ifp; 2722 struct dc_desc *cur_rx; 2723 int i, total_len = 0; 2724 u_int32_t rxstat; 2725 2726 DC_LOCK_ASSERT(sc); 2727 2728 ifp = &sc->arpcom.ac_if; 2729 i = sc->dc_cdata.dc_rx_prod; 2730 2731 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD); 2732 while (!(le32toh(sc->dc_ldata->dc_rx_list[i].dc_status) & 2733 DC_RXSTAT_OWN)) { 2734 #ifdef DEVICE_POLLING 2735 if (ifp->if_flags & IFF_POLLING) { 2736 if (sc->rxcycles <= 0) 2737 break; 2738 sc->rxcycles--; 2739 } 2740 #endif 2741 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2742 rxstat = le32toh(cur_rx->dc_status); 2743 m = sc->dc_cdata.dc_rx_chain[i]; 2744 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i], 2745 BUS_DMASYNC_POSTREAD); 2746 total_len = DC_RXBYTES(rxstat); 2747 2748 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2749 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2750 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2751 sc->dc_pnic_rx_bug_save = i; 2752 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2753 DC_INC(i, DC_RX_LIST_CNT); 2754 continue; 2755 } 2756 dc_pnic_rx_bug_war(sc, i); 2757 rxstat = le32toh(cur_rx->dc_status); 2758 total_len = DC_RXBYTES(rxstat); 2759 } 2760 } 2761 2762 /* 2763 * If an error occurs, update stats, clear the 2764 * status word and leave the mbuf cluster in place: 2765 * it should simply get re-used next time this descriptor 2766 * comes up in the ring. However, don't report long 2767 * frames as errors since they could be vlans. 2768 */ 2769 if ((rxstat & DC_RXSTAT_RXERR)) { 2770 if (!(rxstat & DC_RXSTAT_GIANT) || 2771 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2772 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2773 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2774 ifp->if_ierrors++; 2775 if (rxstat & DC_RXSTAT_COLLSEEN) 2776 ifp->if_collisions++; 2777 dc_newbuf(sc, i, 0); 2778 if (rxstat & DC_RXSTAT_CRCERR) { 2779 DC_INC(i, DC_RX_LIST_CNT); 2780 continue; 2781 } else { 2782 dc_init(sc); 2783 return; 2784 } 2785 } 2786 } 2787 2788 /* No errors; receive the packet. */ 2789 total_len -= ETHER_CRC_LEN; 2790 #ifdef __i386__ 2791 /* 2792 * On the x86 we do not have alignment problems, so try to 2793 * allocate a new buffer for the receive ring, and pass up 2794 * the one where the packet is already, saving the expensive 2795 * copy done in m_devget(). 2796 * If we are on an architecture with alignment problems, or 2797 * if the allocation fails, then use m_devget and leave the 2798 * existing buffer in the receive ring. 2799 */ 2800 if (dc_quick && dc_newbuf(sc, i, 1) == 0) { 2801 m->m_pkthdr.rcvif = ifp; 2802 m->m_pkthdr.len = m->m_len = total_len; 2803 DC_INC(i, DC_RX_LIST_CNT); 2804 } else 2805 #endif 2806 { 2807 struct mbuf *m0; 2808 2809 m0 = m_devget(mtod(m, char *), total_len, 2810 ETHER_ALIGN, ifp, NULL); 2811 dc_newbuf(sc, i, 0); 2812 DC_INC(i, DC_RX_LIST_CNT); 2813 if (m0 == NULL) { 2814 ifp->if_ierrors++; 2815 continue; 2816 } 2817 m = m0; 2818 } 2819 2820 ifp->if_ipackets++; 2821 DC_UNLOCK(sc); 2822 (*ifp->if_input)(ifp, m); 2823 DC_LOCK(sc); 2824 } 2825 2826 sc->dc_cdata.dc_rx_prod = i; 2827 } 2828 2829 /* 2830 * A frame was downloaded to the chip. It's safe for us to clean up 2831 * the list buffers. 2832 */ 2833 2834 static void 2835 dc_txeof(struct dc_softc *sc) 2836 { 2837 struct dc_desc *cur_tx = NULL; 2838 struct ifnet *ifp; 2839 int idx; 2840 u_int32_t ctl, txstat; 2841 2842 ifp = &sc->arpcom.ac_if; 2843 2844 /* 2845 * Go through our tx list and free mbufs for those 2846 * frames that have been transmitted. 2847 */ 2848 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD); 2849 idx = sc->dc_cdata.dc_tx_cons; 2850 while (idx != sc->dc_cdata.dc_tx_prod) { 2851 2852 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2853 txstat = le32toh(cur_tx->dc_status); 2854 ctl = le32toh(cur_tx->dc_ctl); 2855 2856 if (txstat & DC_TXSTAT_OWN) 2857 break; 2858 2859 if (!(ctl & DC_TXCTL_LASTFRAG) || ctl & DC_TXCTL_SETUP) { 2860 if (ctl & DC_TXCTL_SETUP) { 2861 /* 2862 * Yes, the PNIC is so brain damaged 2863 * that it will sometimes generate a TX 2864 * underrun error while DMAing the RX 2865 * filter setup frame. If we detect this, 2866 * we have to send the setup frame again, 2867 * or else the filter won't be programmed 2868 * correctly. 2869 */ 2870 if (DC_IS_PNIC(sc)) { 2871 if (txstat & DC_TXSTAT_ERRSUM) 2872 dc_setfilt(sc); 2873 } 2874 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2875 } 2876 sc->dc_cdata.dc_tx_cnt--; 2877 DC_INC(idx, DC_TX_LIST_CNT); 2878 continue; 2879 } 2880 2881 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) { 2882 /* 2883 * XXX: Why does my Xircom taunt me so? 2884 * For some reason it likes setting the CARRLOST flag 2885 * even when the carrier is there. wtf?!? 2886 * Who knows, but Conexant chips have the 2887 * same problem. Maybe they took lessons 2888 * from Xircom. 2889 */ 2890 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2891 sc->dc_pmode == DC_PMODE_MII && 2892 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 2893 DC_TXSTAT_NOCARRIER))) 2894 txstat &= ~DC_TXSTAT_ERRSUM; 2895 } else { 2896 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2897 sc->dc_pmode == DC_PMODE_MII && 2898 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 2899 DC_TXSTAT_NOCARRIER | DC_TXSTAT_CARRLOST))) 2900 txstat &= ~DC_TXSTAT_ERRSUM; 2901 } 2902 2903 if (txstat & DC_TXSTAT_ERRSUM) { 2904 ifp->if_oerrors++; 2905 if (txstat & DC_TXSTAT_EXCESSCOLL) 2906 ifp->if_collisions++; 2907 if (txstat & DC_TXSTAT_LATECOLL) 2908 ifp->if_collisions++; 2909 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2910 dc_init(sc); 2911 return; 2912 } 2913 } 2914 2915 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2916 2917 ifp->if_opackets++; 2918 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2919 bus_dmamap_sync(sc->dc_mtag, 2920 sc->dc_cdata.dc_tx_map[idx], 2921 BUS_DMASYNC_POSTWRITE); 2922 bus_dmamap_unload(sc->dc_mtag, 2923 sc->dc_cdata.dc_tx_map[idx]); 2924 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2925 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2926 } 2927 2928 sc->dc_cdata.dc_tx_cnt--; 2929 DC_INC(idx, DC_TX_LIST_CNT); 2930 } 2931 2932 if (idx != sc->dc_cdata.dc_tx_cons) { 2933 /* Some buffers have been freed. */ 2934 sc->dc_cdata.dc_tx_cons = idx; 2935 ifp->if_flags &= ~IFF_OACTIVE; 2936 } 2937 ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5; 2938 } 2939 2940 static void 2941 dc_tick(void *xsc) 2942 { 2943 struct dc_softc *sc; 2944 struct mii_data *mii; 2945 struct ifnet *ifp; 2946 u_int32_t r; 2947 2948 sc = xsc; 2949 DC_LOCK(sc); 2950 ifp = &sc->arpcom.ac_if; 2951 mii = device_get_softc(sc->dc_miibus); 2952 2953 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2954 if (sc->dc_flags & DC_21143_NWAY) { 2955 r = CSR_READ_4(sc, DC_10BTSTAT); 2956 if (IFM_SUBTYPE(mii->mii_media_active) == 2957 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2958 sc->dc_link = 0; 2959 mii_mediachg(mii); 2960 } 2961 if (IFM_SUBTYPE(mii->mii_media_active) == 2962 IFM_10_T && (r & DC_TSTAT_LS10)) { 2963 sc->dc_link = 0; 2964 mii_mediachg(mii); 2965 } 2966 if (sc->dc_link == 0) 2967 mii_tick(mii); 2968 } else { 2969 r = CSR_READ_4(sc, DC_ISR); 2970 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2971 sc->dc_cdata.dc_tx_cnt == 0) { 2972 mii_tick(mii); 2973 if (!(mii->mii_media_status & IFM_ACTIVE)) 2974 sc->dc_link = 0; 2975 } 2976 } 2977 } else 2978 mii_tick(mii); 2979 2980 /* 2981 * When the init routine completes, we expect to be able to send 2982 * packets right away, and in fact the network code will send a 2983 * gratuitous ARP the moment the init routine marks the interface 2984 * as running. However, even though the MAC may have been initialized, 2985 * there may be a delay of a few seconds before the PHY completes 2986 * autonegotiation and the link is brought up. Any transmissions 2987 * made during that delay will be lost. Dealing with this is tricky: 2988 * we can't just pause in the init routine while waiting for the 2989 * PHY to come ready since that would bring the whole system to 2990 * a screeching halt for several seconds. 2991 * 2992 * What we do here is prevent the TX start routine from sending 2993 * any packets until a link has been established. After the 2994 * interface has been initialized, the tick routine will poll 2995 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2996 * that time, packets will stay in the send queue, and once the 2997 * link comes up, they will be flushed out to the wire. 2998 */ 2999 if (!sc->dc_link && mii->mii_media_status & IFM_ACTIVE && 3000 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 3001 sc->dc_link++; 3002 if (ifp->if_snd.ifq_head != NULL) 3003 dc_start(ifp); 3004 } 3005 3006 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 3007 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3008 else 3009 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3010 3011 DC_UNLOCK(sc); 3012 } 3013 3014 /* 3015 * A transmit underrun has occurred. Back off the transmit threshold, 3016 * or switch to store and forward mode if we have to. 3017 */ 3018 static void 3019 dc_tx_underrun(struct dc_softc *sc) 3020 { 3021 u_int32_t isr; 3022 int i; 3023 3024 if (DC_IS_DAVICOM(sc)) 3025 dc_init(sc); 3026 3027 if (DC_IS_INTEL(sc)) { 3028 /* 3029 * The real 21143 requires that the transmitter be idle 3030 * in order to change the transmit threshold or store 3031 * and forward state. 3032 */ 3033 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3034 3035 for (i = 0; i < DC_TIMEOUT; i++) { 3036 isr = CSR_READ_4(sc, DC_ISR); 3037 if (isr & DC_ISR_TX_IDLE) 3038 break; 3039 DELAY(10); 3040 } 3041 if (i == DC_TIMEOUT) { 3042 printf("dc%d: failed to force tx to idle state\n", 3043 sc->dc_unit); 3044 dc_init(sc); 3045 } 3046 } 3047 3048 printf("dc%d: TX underrun -- ", sc->dc_unit); 3049 sc->dc_txthresh += DC_TXTHRESH_INC; 3050 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3051 printf("using store and forward mode\n"); 3052 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3053 } else { 3054 printf("increasing TX threshold\n"); 3055 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3056 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3057 } 3058 3059 if (DC_IS_INTEL(sc)) 3060 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3061 } 3062 3063 #ifdef DEVICE_POLLING 3064 static poll_handler_t dc_poll; 3065 3066 static void 3067 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 3068 { 3069 struct dc_softc *sc = ifp->if_softc; 3070 3071 if (!(ifp->if_capenable & IFCAP_POLLING)) { 3072 ether_poll_deregister(ifp); 3073 cmd = POLL_DEREGISTER; 3074 } 3075 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 3076 /* Re-enable interrupts. */ 3077 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3078 return; 3079 } 3080 DC_LOCK(sc); 3081 sc->rxcycles = count; 3082 dc_rxeof(sc); 3083 dc_txeof(sc); 3084 if (ifp->if_snd.ifq_head != NULL && !(ifp->if_flags & IFF_OACTIVE)) 3085 dc_start(ifp); 3086 3087 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 3088 u_int32_t status; 3089 3090 status = CSR_READ_4(sc, DC_ISR); 3091 status &= (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF | 3092 DC_ISR_TX_NOBUF | DC_ISR_TX_IDLE | DC_ISR_TX_UNDERRUN | 3093 DC_ISR_BUS_ERR); 3094 if (!status) { 3095 DC_UNLOCK(sc); 3096 return; 3097 } 3098 /* ack what we have */ 3099 CSR_WRITE_4(sc, DC_ISR, status); 3100 3101 if (status & (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF)) { 3102 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 3103 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 3104 3105 if (dc_rx_resync(sc)) 3106 dc_rxeof(sc); 3107 } 3108 /* restart transmit unit if necessary */ 3109 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 3110 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3111 3112 if (status & DC_ISR_TX_UNDERRUN) 3113 dc_tx_underrun(sc); 3114 3115 if (status & DC_ISR_BUS_ERR) { 3116 printf("dc_poll: dc%d bus error\n", sc->dc_unit); 3117 dc_reset(sc); 3118 dc_init(sc); 3119 } 3120 } 3121 DC_UNLOCK(sc); 3122 } 3123 #endif /* DEVICE_POLLING */ 3124 3125 static void 3126 dc_intr(void *arg) 3127 { 3128 struct dc_softc *sc; 3129 struct ifnet *ifp; 3130 u_int32_t status; 3131 3132 sc = arg; 3133 3134 if (sc->suspended) 3135 return; 3136 3137 if ((CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) 3138 return; 3139 3140 DC_LOCK(sc); 3141 ifp = &sc->arpcom.ac_if; 3142 #ifdef DEVICE_POLLING 3143 if (ifp->if_flags & IFF_POLLING) 3144 goto done; 3145 if ((ifp->if_capenable & IFCAP_POLLING) && 3146 ether_poll_register(dc_poll, ifp)) { /* ok, disable interrupts */ 3147 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3148 goto done; 3149 } 3150 #endif 3151 3152 /* Suppress unwanted interrupts */ 3153 if (!(ifp->if_flags & IFF_UP)) { 3154 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 3155 dc_stop(sc); 3156 DC_UNLOCK(sc); 3157 return; 3158 } 3159 3160 /* Disable interrupts. */ 3161 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3162 3163 while (((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) 3164 && status != 0xFFFFFFFF) { 3165 3166 CSR_WRITE_4(sc, DC_ISR, status); 3167 3168 if (status & DC_ISR_RX_OK) { 3169 int curpkts; 3170 curpkts = ifp->if_ipackets; 3171 dc_rxeof(sc); 3172 if (curpkts == ifp->if_ipackets) { 3173 while (dc_rx_resync(sc)) 3174 dc_rxeof(sc); 3175 } 3176 } 3177 3178 if (status & (DC_ISR_TX_OK | DC_ISR_TX_NOBUF)) 3179 dc_txeof(sc); 3180 3181 if (status & DC_ISR_TX_IDLE) { 3182 dc_txeof(sc); 3183 if (sc->dc_cdata.dc_tx_cnt) { 3184 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3185 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3186 } 3187 } 3188 3189 if (status & DC_ISR_TX_UNDERRUN) 3190 dc_tx_underrun(sc); 3191 3192 if ((status & DC_ISR_RX_WATDOGTIMEO) 3193 || (status & DC_ISR_RX_NOBUF)) { 3194 int curpkts; 3195 curpkts = ifp->if_ipackets; 3196 dc_rxeof(sc); 3197 if (curpkts == ifp->if_ipackets) { 3198 while (dc_rx_resync(sc)) 3199 dc_rxeof(sc); 3200 } 3201 } 3202 3203 if (status & DC_ISR_BUS_ERR) { 3204 dc_reset(sc); 3205 dc_init(sc); 3206 } 3207 } 3208 3209 /* Re-enable interrupts. */ 3210 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3211 3212 if (ifp->if_snd.ifq_head != NULL) 3213 dc_start(ifp); 3214 3215 #ifdef DEVICE_POLLING 3216 done: 3217 #endif 3218 3219 DC_UNLOCK(sc); 3220 } 3221 3222 static void 3223 dc_dma_map_txbuf(arg, segs, nseg, mapsize, error) 3224 void *arg; 3225 bus_dma_segment_t *segs; 3226 int nseg; 3227 bus_size_t mapsize; 3228 int error; 3229 { 3230 struct dc_softc *sc; 3231 struct dc_desc *f; 3232 int cur, first, frag, i; 3233 3234 sc = arg; 3235 if (error) { 3236 sc->dc_cdata.dc_tx_err = error; 3237 return; 3238 } 3239 3240 first = cur = frag = sc->dc_cdata.dc_tx_prod; 3241 for (i = 0; i < nseg; i++) { 3242 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) && 3243 (frag == (DC_TX_LIST_CNT - 1)) && 3244 (first != sc->dc_cdata.dc_tx_first)) { 3245 bus_dmamap_unload(sc->dc_mtag, 3246 sc->dc_cdata.dc_tx_map[first]); 3247 sc->dc_cdata.dc_tx_err = ENOBUFS; 3248 return; 3249 } 3250 3251 f = &sc->dc_ldata->dc_tx_list[frag]; 3252 f->dc_ctl = htole32(DC_TXCTL_TLINK | segs[i].ds_len); 3253 if (i == 0) { 3254 f->dc_status = 0; 3255 f->dc_ctl |= htole32(DC_TXCTL_FIRSTFRAG); 3256 } else 3257 f->dc_status = htole32(DC_TXSTAT_OWN); 3258 f->dc_data = htole32(segs[i].ds_addr); 3259 cur = frag; 3260 DC_INC(frag, DC_TX_LIST_CNT); 3261 } 3262 3263 sc->dc_cdata.dc_tx_err = 0; 3264 sc->dc_cdata.dc_tx_prod = frag; 3265 sc->dc_cdata.dc_tx_cnt += nseg; 3266 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_LASTFRAG); 3267 sc->dc_cdata.dc_tx_chain[cur] = sc->dc_cdata.dc_tx_mapping; 3268 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 3269 sc->dc_ldata->dc_tx_list[first].dc_ctl |= 3270 htole32(DC_TXCTL_FINT); 3271 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 3272 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3273 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 3274 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3275 sc->dc_ldata->dc_tx_list[first].dc_status = htole32(DC_TXSTAT_OWN); 3276 } 3277 3278 /* 3279 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 3280 * pointers to the fragment pointers. 3281 */ 3282 static int 3283 dc_encap(struct dc_softc *sc, struct mbuf **m_head) 3284 { 3285 struct mbuf *m; 3286 int error, idx, chainlen = 0; 3287 3288 /* 3289 * If there's no way we can send any packets, return now. 3290 */ 3291 if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt < 6) 3292 return (ENOBUFS); 3293 3294 /* 3295 * Count the number of frags in this chain to see if 3296 * we need to m_defrag. Since the descriptor list is shared 3297 * by all packets, we'll m_defrag long chains so that they 3298 * do not use up the entire list, even if they would fit. 3299 */ 3300 for (m = *m_head; m != NULL; m = m->m_next) 3301 chainlen++; 3302 3303 if ((chainlen > DC_TX_LIST_CNT / 4) || 3304 ((DC_TX_LIST_CNT - (chainlen + sc->dc_cdata.dc_tx_cnt)) < 6)) { 3305 m = m_defrag(*m_head, M_DONTWAIT); 3306 if (m == NULL) 3307 return (ENOBUFS); 3308 *m_head = m; 3309 } 3310 3311 /* 3312 * Start packing the mbufs in this chain into 3313 * the fragment pointers. Stop when we run out 3314 * of fragments or hit the end of the mbuf chain. 3315 */ 3316 idx = sc->dc_cdata.dc_tx_prod; 3317 sc->dc_cdata.dc_tx_mapping = *m_head; 3318 error = bus_dmamap_load_mbuf(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx], 3319 *m_head, dc_dma_map_txbuf, sc, 0); 3320 if (error) 3321 return (error); 3322 if (sc->dc_cdata.dc_tx_err != 0) 3323 return (sc->dc_cdata.dc_tx_err); 3324 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx], 3325 BUS_DMASYNC_PREWRITE); 3326 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 3327 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3328 return (0); 3329 } 3330 3331 /* 3332 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3333 * to the mbuf data regions directly in the transmit lists. We also save a 3334 * copy of the pointers since the transmit list fragment pointers are 3335 * physical addresses. 3336 */ 3337 3338 static void 3339 dc_start(struct ifnet *ifp) 3340 { 3341 struct dc_softc *sc; 3342 struct mbuf *m_head = NULL, *m; 3343 int idx; 3344 3345 sc = ifp->if_softc; 3346 3347 DC_LOCK(sc); 3348 3349 if (!sc->dc_link && ifp->if_snd.ifq_len < 10) { 3350 DC_UNLOCK(sc); 3351 return; 3352 } 3353 3354 if (ifp->if_flags & IFF_OACTIVE) { 3355 DC_UNLOCK(sc); 3356 return; 3357 } 3358 3359 idx = sc->dc_cdata.dc_tx_first = sc->dc_cdata.dc_tx_prod; 3360 3361 while (sc->dc_cdata.dc_tx_chain[idx] == NULL) { 3362 IF_DEQUEUE(&ifp->if_snd, m_head); 3363 if (m_head == NULL) 3364 break; 3365 3366 if (sc->dc_flags & DC_TX_COALESCE && 3367 (m_head->m_next != NULL || 3368 sc->dc_flags & DC_TX_ALIGN)) { 3369 m = m_defrag(m_head, M_DONTWAIT); 3370 if (m == NULL) { 3371 IF_PREPEND(&ifp->if_snd, m_head); 3372 ifp->if_flags |= IFF_OACTIVE; 3373 break; 3374 } else { 3375 m_head = m; 3376 } 3377 } 3378 3379 if (dc_encap(sc, &m_head)) { 3380 IF_PREPEND(&ifp->if_snd, m_head); 3381 ifp->if_flags |= IFF_OACTIVE; 3382 break; 3383 } 3384 idx = sc->dc_cdata.dc_tx_prod; 3385 3386 /* 3387 * If there's a BPF listener, bounce a copy of this frame 3388 * to him. 3389 */ 3390 BPF_MTAP(ifp, m_head); 3391 3392 if (sc->dc_flags & DC_TX_ONE) { 3393 ifp->if_flags |= IFF_OACTIVE; 3394 break; 3395 } 3396 } 3397 3398 /* Transmit */ 3399 if (!(sc->dc_flags & DC_TX_POLL)) 3400 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3401 3402 /* 3403 * Set a timeout in case the chip goes out to lunch. 3404 */ 3405 ifp->if_timer = 5; 3406 3407 DC_UNLOCK(sc); 3408 } 3409 3410 static void 3411 dc_init(void *xsc) 3412 { 3413 struct dc_softc *sc = xsc; 3414 struct ifnet *ifp = &sc->arpcom.ac_if; 3415 struct mii_data *mii; 3416 3417 DC_LOCK(sc); 3418 3419 mii = device_get_softc(sc->dc_miibus); 3420 3421 /* 3422 * Cancel pending I/O and free all RX/TX buffers. 3423 */ 3424 dc_stop(sc); 3425 dc_reset(sc); 3426 3427 /* 3428 * Set cache alignment and burst length. 3429 */ 3430 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 3431 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3432 else 3433 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME | DC_BUSCTL_MRLE); 3434 /* 3435 * Evenly share the bus between receive and transmit process. 3436 */ 3437 if (DC_IS_INTEL(sc)) 3438 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3439 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3440 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3441 } else { 3442 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3443 } 3444 if (sc->dc_flags & DC_TX_POLL) 3445 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3446 switch(sc->dc_cachesize) { 3447 case 32: 3448 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3449 break; 3450 case 16: 3451 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3452 break; 3453 case 8: 3454 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3455 break; 3456 case 0: 3457 default: 3458 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3459 break; 3460 } 3461 3462 if (sc->dc_flags & DC_TX_STORENFWD) 3463 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3464 else { 3465 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3466 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3467 } else { 3468 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3469 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3470 } 3471 } 3472 3473 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3474 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3475 3476 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3477 /* 3478 * The app notes for the 98713 and 98715A say that 3479 * in order to have the chips operate properly, a magic 3480 * number must be written to CSR16. Macronix does not 3481 * document the meaning of these bits so there's no way 3482 * to know exactly what they do. The 98713 has a magic 3483 * number all its own; the rest all use a different one. 3484 */ 3485 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3486 if (sc->dc_type == DC_TYPE_98713) 3487 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3488 else 3489 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3490 } 3491 3492 if (DC_IS_XIRCOM(sc)) { 3493 /* 3494 * setup General Purpose Port mode and data so the tulip 3495 * can talk to the MII. 3496 */ 3497 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3498 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3499 DELAY(10); 3500 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3501 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3502 DELAY(10); 3503 } 3504 3505 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3506 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3507 3508 /* Init circular RX list. */ 3509 if (dc_list_rx_init(sc) == ENOBUFS) { 3510 printf("dc%d: initialization failed: no " 3511 "memory for rx buffers\n", sc->dc_unit); 3512 dc_stop(sc); 3513 DC_UNLOCK(sc); 3514 return; 3515 } 3516 3517 /* 3518 * Init TX descriptors. 3519 */ 3520 dc_list_tx_init(sc); 3521 3522 /* 3523 * Load the address of the RX list. 3524 */ 3525 CSR_WRITE_4(sc, DC_RXADDR, DC_RXDESC(sc, 0)); 3526 CSR_WRITE_4(sc, DC_TXADDR, DC_TXDESC(sc, 0)); 3527 3528 /* 3529 * Enable interrupts. 3530 */ 3531 #ifdef DEVICE_POLLING 3532 /* 3533 * ... but only if we are not polling, and make sure they are off in 3534 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3535 * after a reset. 3536 */ 3537 if (ifp->if_flags & IFF_POLLING) 3538 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3539 else 3540 #endif 3541 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3542 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3543 3544 /* Enable transmitter. */ 3545 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3546 3547 /* 3548 * If this is an Intel 21143 and we're not using the 3549 * MII port, program the LED control pins so we get 3550 * link and activity indications. 3551 */ 3552 if (sc->dc_flags & DC_TULIP_LEDS) { 3553 CSR_WRITE_4(sc, DC_WATCHDOG, 3554 DC_WDOG_CTLWREN | DC_WDOG_LINK | DC_WDOG_ACTIVITY); 3555 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3556 } 3557 3558 /* 3559 * Load the RX/multicast filter. We do this sort of late 3560 * because the filter programming scheme on the 21143 and 3561 * some clones requires DMAing a setup frame via the TX 3562 * engine, and we need the transmitter enabled for that. 3563 */ 3564 dc_setfilt(sc); 3565 3566 /* Enable receiver. */ 3567 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3568 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3569 3570 mii_mediachg(mii); 3571 dc_setcfg(sc, sc->dc_if_media); 3572 3573 ifp->if_flags |= IFF_RUNNING; 3574 ifp->if_flags &= ~IFF_OACTIVE; 3575 3576 /* Don't start the ticker if this is a homePNA link. */ 3577 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) 3578 sc->dc_link = 1; 3579 else { 3580 if (sc->dc_flags & DC_21143_NWAY) 3581 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3582 else 3583 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3584 } 3585 3586 #ifdef SRM_MEDIA 3587 if(sc->dc_srm_media) { 3588 struct ifreq ifr; 3589 3590 ifr.ifr_media = sc->dc_srm_media; 3591 ifmedia_ioctl(ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA); 3592 sc->dc_srm_media = 0; 3593 } 3594 #endif 3595 DC_UNLOCK(sc); 3596 } 3597 3598 /* 3599 * Set media options. 3600 */ 3601 static int 3602 dc_ifmedia_upd(struct ifnet *ifp) 3603 { 3604 struct dc_softc *sc; 3605 struct mii_data *mii; 3606 struct ifmedia *ifm; 3607 3608 sc = ifp->if_softc; 3609 mii = device_get_softc(sc->dc_miibus); 3610 mii_mediachg(mii); 3611 ifm = &mii->mii_media; 3612 3613 if (DC_IS_DAVICOM(sc) && 3614 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) 3615 dc_setcfg(sc, ifm->ifm_media); 3616 else 3617 sc->dc_link = 0; 3618 3619 return (0); 3620 } 3621 3622 /* 3623 * Report current media status. 3624 */ 3625 static void 3626 dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3627 { 3628 struct dc_softc *sc; 3629 struct mii_data *mii; 3630 struct ifmedia *ifm; 3631 3632 sc = ifp->if_softc; 3633 mii = device_get_softc(sc->dc_miibus); 3634 mii_pollstat(mii); 3635 ifm = &mii->mii_media; 3636 if (DC_IS_DAVICOM(sc)) { 3637 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 3638 ifmr->ifm_active = ifm->ifm_media; 3639 ifmr->ifm_status = 0; 3640 return; 3641 } 3642 } 3643 ifmr->ifm_active = mii->mii_media_active; 3644 ifmr->ifm_status = mii->mii_media_status; 3645 } 3646 3647 static int 3648 dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3649 { 3650 struct dc_softc *sc = ifp->if_softc; 3651 struct ifreq *ifr = (struct ifreq *)data; 3652 struct mii_data *mii; 3653 int error = 0; 3654 3655 DC_LOCK(sc); 3656 3657 switch (command) { 3658 case SIOCSIFFLAGS: 3659 if (ifp->if_flags & IFF_UP) { 3660 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) & 3661 (IFF_PROMISC | IFF_ALLMULTI); 3662 3663 if (ifp->if_flags & IFF_RUNNING) { 3664 if (need_setfilt) 3665 dc_setfilt(sc); 3666 } else { 3667 sc->dc_txthresh = 0; 3668 dc_init(sc); 3669 } 3670 } else { 3671 if (ifp->if_flags & IFF_RUNNING) 3672 dc_stop(sc); 3673 } 3674 sc->dc_if_flags = ifp->if_flags; 3675 error = 0; 3676 break; 3677 case SIOCADDMULTI: 3678 case SIOCDELMULTI: 3679 dc_setfilt(sc); 3680 error = 0; 3681 break; 3682 case SIOCGIFMEDIA: 3683 case SIOCSIFMEDIA: 3684 mii = device_get_softc(sc->dc_miibus); 3685 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3686 #ifdef SRM_MEDIA 3687 if (sc->dc_srm_media) 3688 sc->dc_srm_media = 0; 3689 #endif 3690 break; 3691 case SIOCSIFCAP: 3692 ifp->if_capenable &= ~IFCAP_POLLING; 3693 ifp->if_capenable |= ifr->ifr_reqcap & IFCAP_POLLING; 3694 break; 3695 default: 3696 error = ether_ioctl(ifp, command, data); 3697 break; 3698 } 3699 3700 DC_UNLOCK(sc); 3701 3702 return (error); 3703 } 3704 3705 static void 3706 dc_watchdog(struct ifnet *ifp) 3707 { 3708 struct dc_softc *sc; 3709 3710 sc = ifp->if_softc; 3711 3712 DC_LOCK(sc); 3713 3714 ifp->if_oerrors++; 3715 printf("dc%d: watchdog timeout\n", sc->dc_unit); 3716 3717 dc_stop(sc); 3718 dc_reset(sc); 3719 dc_init(sc); 3720 3721 if (ifp->if_snd.ifq_head != NULL) 3722 dc_start(ifp); 3723 3724 DC_UNLOCK(sc); 3725 } 3726 3727 /* 3728 * Stop the adapter and free any mbufs allocated to the 3729 * RX and TX lists. 3730 */ 3731 static void 3732 dc_stop(struct dc_softc *sc) 3733 { 3734 struct ifnet *ifp; 3735 struct dc_list_data *ld; 3736 struct dc_chain_data *cd; 3737 int i; 3738 u_int32_t ctl; 3739 3740 DC_LOCK(sc); 3741 3742 ifp = &sc->arpcom.ac_if; 3743 ifp->if_timer = 0; 3744 ld = sc->dc_ldata; 3745 cd = &sc->dc_cdata; 3746 3747 callout_stop(&sc->dc_stat_ch); 3748 3749 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3750 #ifdef DEVICE_POLLING 3751 ether_poll_deregister(ifp); 3752 #endif 3753 3754 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)); 3755 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3756 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3757 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3758 sc->dc_link = 0; 3759 3760 /* 3761 * Free data in the RX lists. 3762 */ 3763 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3764 if (cd->dc_rx_chain[i] != NULL) { 3765 m_freem(cd->dc_rx_chain[i]); 3766 cd->dc_rx_chain[i] = NULL; 3767 } 3768 } 3769 bzero(&ld->dc_rx_list, sizeof(ld->dc_rx_list)); 3770 3771 /* 3772 * Free the TX list buffers. 3773 */ 3774 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3775 if (cd->dc_tx_chain[i] != NULL) { 3776 ctl = le32toh(ld->dc_tx_list[i].dc_ctl); 3777 if ((ctl & DC_TXCTL_SETUP) || 3778 !(ctl & DC_TXCTL_LASTFRAG)) { 3779 cd->dc_tx_chain[i] = NULL; 3780 continue; 3781 } 3782 bus_dmamap_unload(sc->dc_mtag, cd->dc_tx_map[i]); 3783 m_freem(cd->dc_tx_chain[i]); 3784 cd->dc_tx_chain[i] = NULL; 3785 } 3786 } 3787 bzero(&ld->dc_tx_list, sizeof(ld->dc_tx_list)); 3788 3789 DC_UNLOCK(sc); 3790 } 3791 3792 /* 3793 * Device suspend routine. Stop the interface and save some PCI 3794 * settings in case the BIOS doesn't restore them properly on 3795 * resume. 3796 */ 3797 static int 3798 dc_suspend(device_t dev) 3799 { 3800 struct dc_softc *sc; 3801 int i, s; 3802 3803 s = splimp(); 3804 3805 sc = device_get_softc(dev); 3806 3807 dc_stop(sc); 3808 3809 for (i = 0; i < 5; i++) 3810 sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4); 3811 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 3812 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 3813 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 3814 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 3815 3816 sc->suspended = 1; 3817 3818 splx(s); 3819 return (0); 3820 } 3821 3822 /* 3823 * Device resume routine. Restore some PCI settings in case the BIOS 3824 * doesn't, re-enable busmastering, and restart the interface if 3825 * appropriate. 3826 */ 3827 static int 3828 dc_resume(device_t dev) 3829 { 3830 struct dc_softc *sc; 3831 struct ifnet *ifp; 3832 int i, s; 3833 3834 s = splimp(); 3835 3836 sc = device_get_softc(dev); 3837 ifp = &sc->arpcom.ac_if; 3838 #ifndef BURN_BRIDGES 3839 dc_acpi(dev); 3840 #endif 3841 /* better way to do this? */ 3842 for (i = 0; i < 5; i++) 3843 pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4); 3844 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 3845 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 3846 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 3847 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 3848 3849 /* reenable busmastering */ 3850 pci_enable_busmaster(dev); 3851 pci_enable_io(dev, DC_RES); 3852 3853 /* reinitialize interface if necessary */ 3854 if (ifp->if_flags & IFF_UP) 3855 dc_init(sc); 3856 3857 sc->suspended = 0; 3858 3859 splx(s); 3860 return (0); 3861 } 3862 3863 /* 3864 * Stop all chip I/O so that the kernel's probe routines don't 3865 * get confused by errant DMAs when rebooting. 3866 */ 3867 static void 3868 dc_shutdown(device_t dev) 3869 { 3870 struct dc_softc *sc; 3871 3872 sc = device_get_softc(dev); 3873 3874 dc_stop(sc); 3875 } 3876