1 /*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 38 * series chips and several workalikes including the following: 39 * 40 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 41 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 42 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 43 * ASIX Electronics AX88140A (www.asix.com.tw) 44 * ASIX Electronics AX88141 (www.asix.com.tw) 45 * ADMtek AL981 (www.admtek.com.tw) 46 * ADMtek AN985 (www.admtek.com.tw) 47 * Netgear FA511 (www.netgear.com) Appears to be rebadged ADMTek AN985 48 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 49 * Accton EN1217 (www.accton.com) 50 * Xircom X3201 (www.xircom.com) 51 * Abocom FE2500 52 * Conexant LANfinity (www.conexant.com) 53 * 3Com OfficeConnect 10/100B 3CSOHO100B (www.3com.com) 54 * 55 * Datasheets for the 21143 are available at developer.intel.com. 56 * Datasheets for the clone parts can be found at their respective sites. 57 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 58 * The PNIC II is essentially a Macronix 98715A chip; the only difference 59 * worth noting is that its multicast hash table is only 128 bits wide 60 * instead of 512. 61 * 62 * Written by Bill Paul <wpaul@ee.columbia.edu> 63 * Electrical Engineering Department 64 * Columbia University, New York City 65 */ 66 /* 67 * The Intel 21143 is the successor to the DEC 21140. It is basically 68 * the same as the 21140 but with a few new features. The 21143 supports 69 * three kinds of media attachments: 70 * 71 * o MII port, for 10Mbps and 100Mbps support and NWAY 72 * autonegotiation provided by an external PHY. 73 * o SYM port, for symbol mode 100Mbps support. 74 * o 10baseT port. 75 * o AUI/BNC port. 76 * 77 * The 100Mbps SYM port and 10baseT port can be used together in 78 * combination with the internal NWAY support to create a 10/100 79 * autosensing configuration. 80 * 81 * Note that not all tulip workalikes are handled in this driver: we only 82 * deal with those which are relatively well behaved. The Winbond is 83 * handled separately due to its different register offsets and the 84 * special handling needed for its various bugs. The PNIC is handled 85 * here, but I'm not thrilled about it. 86 * 87 * All of the workalike chips use some form of MII transceiver support 88 * with the exception of the Macronix chips, which also have a SYM port. 89 * The ASIX AX88140A is also documented to have a SYM port, but all 90 * the cards I've seen use an MII transceiver, probably because the 91 * AX88140A doesn't support internal NWAY. 92 */ 93 94 #ifdef HAVE_KERNEL_OPTION_HEADERS 95 #include "opt_device_polling.h" 96 #endif 97 98 #include <sys/param.h> 99 #include <sys/endian.h> 100 #include <sys/systm.h> 101 #include <sys/sockio.h> 102 #include <sys/mbuf.h> 103 #include <sys/malloc.h> 104 #include <sys/kernel.h> 105 #include <sys/module.h> 106 #include <sys/socket.h> 107 108 #include <net/if.h> 109 #include <net/if_arp.h> 110 #include <net/ethernet.h> 111 #include <net/if_dl.h> 112 #include <net/if_media.h> 113 #include <net/if_types.h> 114 #include <net/if_vlan_var.h> 115 116 #include <net/bpf.h> 117 118 #include <machine/bus.h> 119 #include <machine/resource.h> 120 #include <sys/bus.h> 121 #include <sys/rman.h> 122 123 #include <dev/mii/mii.h> 124 #include <dev/mii/miivar.h> 125 126 #include <dev/pci/pcireg.h> 127 #include <dev/pci/pcivar.h> 128 129 #define DC_USEIOSPACE 130 131 #include <dev/dc/if_dcreg.h> 132 133 #ifdef __sparc64__ 134 #include <dev/ofw/openfirm.h> 135 #include <machine/ofw_machdep.h> 136 #endif 137 138 MODULE_DEPEND(dc, pci, 1, 1, 1); 139 MODULE_DEPEND(dc, ether, 1, 1, 1); 140 MODULE_DEPEND(dc, miibus, 1, 1, 1); 141 142 /* 143 * "device miibus" is required in kernel config. See GENERIC if you get 144 * errors here. 145 */ 146 #include "miibus_if.h" 147 148 /* 149 * Various supported device vendors/types and their names. 150 */ 151 static const struct dc_type dc_devs[] = { 152 { DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143), 0, 153 "Intel 21143 10/100BaseTX" }, 154 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009), 0, 155 "Davicom DM9009 10/100BaseTX" }, 156 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100), 0, 157 "Davicom DM9100 10/100BaseTX" }, 158 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), DC_REVISION_DM9102A, 159 "Davicom DM9102A 10/100BaseTX" }, 160 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), 0, 161 "Davicom DM9102 10/100BaseTX" }, 162 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981), 0, 163 "ADMtek AL981 10/100BaseTX" }, 164 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985), 0, 165 "ADMtek AN985 10/100BaseTX" }, 166 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511), 0, 167 "ADMtek ADM9511 10/100BaseTX" }, 168 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513), 0, 169 "ADMtek ADM9513 10/100BaseTX" }, 170 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_FA511), 0, 171 "Netgear FA511 10/100BaseTX" }, 172 { DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), DC_REVISION_88141, 173 "ASIX AX88141 10/100BaseTX" }, 174 { DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), 0, 175 "ASIX AX88140A 10/100BaseTX" }, 176 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), DC_REVISION_98713A, 177 "Macronix 98713A 10/100BaseTX" }, 178 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), 0, 179 "Macronix 98713 10/100BaseTX" }, 180 { DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), DC_REVISION_98713A, 181 "Compex RL100-TX 10/100BaseTX" }, 182 { DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), 0, 183 "Compex RL100-TX 10/100BaseTX" }, 184 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98725, 185 "Macronix 98725 10/100BaseTX" }, 186 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98715AEC_C, 187 "Macronix 98715AEC-C 10/100BaseTX" }, 188 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), 0, 189 "Macronix 98715/98715A 10/100BaseTX" }, 190 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727), 0, 191 "Macronix 98727/98732 10/100BaseTX" }, 192 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115), 0, 193 "LC82C115 PNIC II 10/100BaseTX" }, 194 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), DC_REVISION_82C169, 195 "82c169 PNIC 10/100BaseTX" }, 196 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), 0, 197 "82c168 PNIC 10/100BaseTX" }, 198 { DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217), 0, 199 "Accton EN1217 10/100BaseTX" }, 200 { DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242), 0, 201 "Accton EN2242 MiniPCI 10/100BaseTX" }, 202 { DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201), 0, 203 "Xircom X3201 10/100BaseTX" }, 204 { DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD), 0, 205 "Neteasy DRP-32TXD Cardbus 10/100" }, 206 { DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500), 0, 207 "Abocom FE2500 10/100BaseTX" }, 208 { DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX), 0, 209 "Abocom FE2500MX 10/100BaseTX" }, 210 { DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112), 0, 211 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 212 { DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX), 0, 213 "Hawking CB102 CardBus 10/100" }, 214 { DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T), 0, 215 "PlaneX FNW-3602-T CardBus 10/100" }, 216 { DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB), 0, 217 "3Com OfficeConnect 10/100B" }, 218 { DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120), 0, 219 "Microsoft MN-120 CardBus 10/100" }, 220 { DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130), 0, 221 "Microsoft MN-130 10/100" }, 222 { DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08), 0, 223 "Linksys PCMPC200 CardBus 10/100" }, 224 { DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09), 0, 225 "Linksys PCMPC200 CardBus 10/100" }, 226 { 0, 0, NULL } 227 }; 228 229 static int dc_probe(device_t); 230 static int dc_attach(device_t); 231 static int dc_detach(device_t); 232 static int dc_suspend(device_t); 233 static int dc_resume(device_t); 234 static const struct dc_type *dc_devtype(device_t); 235 static int dc_newbuf(struct dc_softc *, int, int); 236 static int dc_encap(struct dc_softc *, struct mbuf **); 237 static void dc_pnic_rx_bug_war(struct dc_softc *, int); 238 static int dc_rx_resync(struct dc_softc *); 239 static void dc_rxeof(struct dc_softc *); 240 static void dc_txeof(struct dc_softc *); 241 static void dc_tick(void *); 242 static void dc_tx_underrun(struct dc_softc *); 243 static void dc_intr(void *); 244 static void dc_start(struct ifnet *); 245 static void dc_start_locked(struct ifnet *); 246 static int dc_ioctl(struct ifnet *, u_long, caddr_t); 247 static void dc_init(void *); 248 static void dc_init_locked(struct dc_softc *); 249 static void dc_stop(struct dc_softc *); 250 static void dc_watchdog(void *); 251 static int dc_shutdown(device_t); 252 static int dc_ifmedia_upd(struct ifnet *); 253 static void dc_ifmedia_sts(struct ifnet *, struct ifmediareq *); 254 255 static void dc_delay(struct dc_softc *); 256 static void dc_eeprom_idle(struct dc_softc *); 257 static void dc_eeprom_putbyte(struct dc_softc *, int); 258 static void dc_eeprom_getword(struct dc_softc *, int, u_int16_t *); 259 static void dc_eeprom_getword_pnic(struct dc_softc *, int, u_int16_t *); 260 static void dc_eeprom_getword_xircom(struct dc_softc *, int, u_int16_t *); 261 static void dc_eeprom_width(struct dc_softc *); 262 static void dc_read_eeprom(struct dc_softc *, caddr_t, int, int, int); 263 264 static void dc_mii_writebit(struct dc_softc *, int); 265 static int dc_mii_readbit(struct dc_softc *); 266 static void dc_mii_sync(struct dc_softc *); 267 static void dc_mii_send(struct dc_softc *, u_int32_t, int); 268 static int dc_mii_readreg(struct dc_softc *, struct dc_mii_frame *); 269 static int dc_mii_writereg(struct dc_softc *, struct dc_mii_frame *); 270 static int dc_miibus_readreg(device_t, int, int); 271 static int dc_miibus_writereg(device_t, int, int, int); 272 static void dc_miibus_statchg(device_t); 273 static void dc_miibus_mediainit(device_t); 274 275 static void dc_setcfg(struct dc_softc *, int); 276 static uint32_t dc_mchash_le(struct dc_softc *, const uint8_t *); 277 static uint32_t dc_mchash_be(const uint8_t *); 278 static void dc_setfilt_21143(struct dc_softc *); 279 static void dc_setfilt_asix(struct dc_softc *); 280 static void dc_setfilt_admtek(struct dc_softc *); 281 static void dc_setfilt_xircom(struct dc_softc *); 282 283 static void dc_setfilt(struct dc_softc *); 284 285 static void dc_reset(struct dc_softc *); 286 static int dc_list_rx_init(struct dc_softc *); 287 static int dc_list_tx_init(struct dc_softc *); 288 289 static void dc_read_srom(struct dc_softc *, int); 290 static void dc_parse_21143_srom(struct dc_softc *); 291 static void dc_decode_leaf_sia(struct dc_softc *, struct dc_eblock_sia *); 292 static void dc_decode_leaf_mii(struct dc_softc *, struct dc_eblock_mii *); 293 static void dc_decode_leaf_sym(struct dc_softc *, struct dc_eblock_sym *); 294 static void dc_apply_fixup(struct dc_softc *, int); 295 296 #ifdef DC_USEIOSPACE 297 #define DC_RES SYS_RES_IOPORT 298 #define DC_RID DC_PCI_CFBIO 299 #else 300 #define DC_RES SYS_RES_MEMORY 301 #define DC_RID DC_PCI_CFBMA 302 #endif 303 304 static device_method_t dc_methods[] = { 305 /* Device interface */ 306 DEVMETHOD(device_probe, dc_probe), 307 DEVMETHOD(device_attach, dc_attach), 308 DEVMETHOD(device_detach, dc_detach), 309 DEVMETHOD(device_suspend, dc_suspend), 310 DEVMETHOD(device_resume, dc_resume), 311 DEVMETHOD(device_shutdown, dc_shutdown), 312 313 /* bus interface */ 314 DEVMETHOD(bus_print_child, bus_generic_print_child), 315 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 316 317 /* MII interface */ 318 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 319 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 320 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 321 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 322 323 { 0, 0 } 324 }; 325 326 static driver_t dc_driver = { 327 "dc", 328 dc_methods, 329 sizeof(struct dc_softc) 330 }; 331 332 static devclass_t dc_devclass; 333 334 DRIVER_MODULE(dc, cardbus, dc_driver, dc_devclass, 0, 0); 335 DRIVER_MODULE(dc, pci, dc_driver, dc_devclass, 0, 0); 336 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 337 338 #define DC_SETBIT(sc, reg, x) \ 339 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 340 341 #define DC_CLRBIT(sc, reg, x) \ 342 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 343 344 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 345 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 346 347 static void 348 dc_delay(struct dc_softc *sc) 349 { 350 int idx; 351 352 for (idx = (300 / 33) + 1; idx > 0; idx--) 353 CSR_READ_4(sc, DC_BUSCTL); 354 } 355 356 static void 357 dc_eeprom_width(struct dc_softc *sc) 358 { 359 int i; 360 361 /* Force EEPROM to idle state. */ 362 dc_eeprom_idle(sc); 363 364 /* Enter EEPROM access mode. */ 365 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 366 dc_delay(sc); 367 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 368 dc_delay(sc); 369 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 370 dc_delay(sc); 371 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 372 dc_delay(sc); 373 374 for (i = 3; i--;) { 375 if (6 & (1 << i)) 376 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 377 else 378 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 379 dc_delay(sc); 380 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 381 dc_delay(sc); 382 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 383 dc_delay(sc); 384 } 385 386 for (i = 1; i <= 12; i++) { 387 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 388 dc_delay(sc); 389 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { 390 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 391 dc_delay(sc); 392 break; 393 } 394 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 395 dc_delay(sc); 396 } 397 398 /* Turn off EEPROM access mode. */ 399 dc_eeprom_idle(sc); 400 401 if (i < 4 || i > 12) 402 sc->dc_romwidth = 6; 403 else 404 sc->dc_romwidth = i; 405 406 /* Enter EEPROM access mode. */ 407 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 408 dc_delay(sc); 409 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 410 dc_delay(sc); 411 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 412 dc_delay(sc); 413 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 414 dc_delay(sc); 415 416 /* Turn off EEPROM access mode. */ 417 dc_eeprom_idle(sc); 418 } 419 420 static void 421 dc_eeprom_idle(struct dc_softc *sc) 422 { 423 int i; 424 425 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 426 dc_delay(sc); 427 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 428 dc_delay(sc); 429 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 430 dc_delay(sc); 431 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 432 dc_delay(sc); 433 434 for (i = 0; i < 25; i++) { 435 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 436 dc_delay(sc); 437 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 438 dc_delay(sc); 439 } 440 441 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 442 dc_delay(sc); 443 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 444 dc_delay(sc); 445 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 446 } 447 448 /* 449 * Send a read command and address to the EEPROM, check for ACK. 450 */ 451 static void 452 dc_eeprom_putbyte(struct dc_softc *sc, int addr) 453 { 454 int d, i; 455 456 d = DC_EECMD_READ >> 6; 457 for (i = 3; i--; ) { 458 if (d & (1 << i)) 459 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 460 else 461 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 462 dc_delay(sc); 463 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 464 dc_delay(sc); 465 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 466 dc_delay(sc); 467 } 468 469 /* 470 * Feed in each bit and strobe the clock. 471 */ 472 for (i = sc->dc_romwidth; i--;) { 473 if (addr & (1 << i)) { 474 SIO_SET(DC_SIO_EE_DATAIN); 475 } else { 476 SIO_CLR(DC_SIO_EE_DATAIN); 477 } 478 dc_delay(sc); 479 SIO_SET(DC_SIO_EE_CLK); 480 dc_delay(sc); 481 SIO_CLR(DC_SIO_EE_CLK); 482 dc_delay(sc); 483 } 484 } 485 486 /* 487 * Read a word of data stored in the EEPROM at address 'addr.' 488 * The PNIC 82c168/82c169 has its own non-standard way to read 489 * the EEPROM. 490 */ 491 static void 492 dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, u_int16_t *dest) 493 { 494 int i; 495 u_int32_t r; 496 497 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr); 498 499 for (i = 0; i < DC_TIMEOUT; i++) { 500 DELAY(1); 501 r = CSR_READ_4(sc, DC_SIO); 502 if (!(r & DC_PN_SIOCTL_BUSY)) { 503 *dest = (u_int16_t)(r & 0xFFFF); 504 return; 505 } 506 } 507 } 508 509 /* 510 * Read a word of data stored in the EEPROM at address 'addr.' 511 * The Xircom X3201 has its own non-standard way to read 512 * the EEPROM, too. 513 */ 514 static void 515 dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, u_int16_t *dest) 516 { 517 518 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 519 520 addr *= 2; 521 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 522 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff; 523 addr += 1; 524 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 525 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8; 526 527 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 528 } 529 530 /* 531 * Read a word of data stored in the EEPROM at address 'addr.' 532 */ 533 static void 534 dc_eeprom_getword(struct dc_softc *sc, int addr, u_int16_t *dest) 535 { 536 int i; 537 u_int16_t word = 0; 538 539 /* Force EEPROM to idle state. */ 540 dc_eeprom_idle(sc); 541 542 /* Enter EEPROM access mode. */ 543 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 544 dc_delay(sc); 545 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 546 dc_delay(sc); 547 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 548 dc_delay(sc); 549 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 550 dc_delay(sc); 551 552 /* 553 * Send address of word we want to read. 554 */ 555 dc_eeprom_putbyte(sc, addr); 556 557 /* 558 * Start reading bits from EEPROM. 559 */ 560 for (i = 0x8000; i; i >>= 1) { 561 SIO_SET(DC_SIO_EE_CLK); 562 dc_delay(sc); 563 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 564 word |= i; 565 dc_delay(sc); 566 SIO_CLR(DC_SIO_EE_CLK); 567 dc_delay(sc); 568 } 569 570 /* Turn off EEPROM access mode. */ 571 dc_eeprom_idle(sc); 572 573 *dest = word; 574 } 575 576 /* 577 * Read a sequence of words from the EEPROM. 578 */ 579 static void 580 dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int be) 581 { 582 int i; 583 u_int16_t word = 0, *ptr; 584 585 for (i = 0; i < cnt; i++) { 586 if (DC_IS_PNIC(sc)) 587 dc_eeprom_getword_pnic(sc, off + i, &word); 588 else if (DC_IS_XIRCOM(sc)) 589 dc_eeprom_getword_xircom(sc, off + i, &word); 590 else 591 dc_eeprom_getword(sc, off + i, &word); 592 ptr = (u_int16_t *)(dest + (i * 2)); 593 if (be) 594 *ptr = be16toh(word); 595 else 596 *ptr = le16toh(word); 597 } 598 } 599 600 /* 601 * The following two routines are taken from the Macronix 98713 602 * Application Notes pp.19-21. 603 */ 604 /* 605 * Write a bit to the MII bus. 606 */ 607 static void 608 dc_mii_writebit(struct dc_softc *sc, int bit) 609 { 610 611 if (bit) 612 CSR_WRITE_4(sc, DC_SIO, 613 DC_SIO_ROMCTL_WRITE | DC_SIO_MII_DATAOUT); 614 else 615 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 616 617 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 618 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 619 } 620 621 /* 622 * Read a bit from the MII bus. 623 */ 624 static int 625 dc_mii_readbit(struct dc_softc *sc) 626 { 627 628 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ | DC_SIO_MII_DIR); 629 CSR_READ_4(sc, DC_SIO); 630 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 631 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 632 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 633 return (1); 634 635 return (0); 636 } 637 638 /* 639 * Sync the PHYs by setting data bit and strobing the clock 32 times. 640 */ 641 static void 642 dc_mii_sync(struct dc_softc *sc) 643 { 644 int i; 645 646 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 647 648 for (i = 0; i < 32; i++) 649 dc_mii_writebit(sc, 1); 650 } 651 652 /* 653 * Clock a series of bits through the MII. 654 */ 655 static void 656 dc_mii_send(struct dc_softc *sc, u_int32_t bits, int cnt) 657 { 658 int i; 659 660 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 661 dc_mii_writebit(sc, bits & i); 662 } 663 664 /* 665 * Read an PHY register through the MII. 666 */ 667 static int 668 dc_mii_readreg(struct dc_softc *sc, struct dc_mii_frame *frame) 669 { 670 int i, ack; 671 672 /* 673 * Set up frame for RX. 674 */ 675 frame->mii_stdelim = DC_MII_STARTDELIM; 676 frame->mii_opcode = DC_MII_READOP; 677 frame->mii_turnaround = 0; 678 frame->mii_data = 0; 679 680 /* 681 * Sync the PHYs. 682 */ 683 dc_mii_sync(sc); 684 685 /* 686 * Send command/address info. 687 */ 688 dc_mii_send(sc, frame->mii_stdelim, 2); 689 dc_mii_send(sc, frame->mii_opcode, 2); 690 dc_mii_send(sc, frame->mii_phyaddr, 5); 691 dc_mii_send(sc, frame->mii_regaddr, 5); 692 693 #ifdef notdef 694 /* Idle bit */ 695 dc_mii_writebit(sc, 1); 696 dc_mii_writebit(sc, 0); 697 #endif 698 699 /* Check for ack. */ 700 ack = dc_mii_readbit(sc); 701 702 /* 703 * Now try reading data bits. If the ack failed, we still 704 * need to clock through 16 cycles to keep the PHY(s) in sync. 705 */ 706 if (ack) { 707 for (i = 0; i < 16; i++) 708 dc_mii_readbit(sc); 709 goto fail; 710 } 711 712 for (i = 0x8000; i; i >>= 1) { 713 if (!ack) { 714 if (dc_mii_readbit(sc)) 715 frame->mii_data |= i; 716 } 717 } 718 719 fail: 720 721 dc_mii_writebit(sc, 0); 722 dc_mii_writebit(sc, 0); 723 724 if (ack) 725 return (1); 726 return (0); 727 } 728 729 /* 730 * Write to a PHY register through the MII. 731 */ 732 static int 733 dc_mii_writereg(struct dc_softc *sc, struct dc_mii_frame *frame) 734 { 735 736 /* 737 * Set up frame for TX. 738 */ 739 740 frame->mii_stdelim = DC_MII_STARTDELIM; 741 frame->mii_opcode = DC_MII_WRITEOP; 742 frame->mii_turnaround = DC_MII_TURNAROUND; 743 744 /* 745 * Sync the PHYs. 746 */ 747 dc_mii_sync(sc); 748 749 dc_mii_send(sc, frame->mii_stdelim, 2); 750 dc_mii_send(sc, frame->mii_opcode, 2); 751 dc_mii_send(sc, frame->mii_phyaddr, 5); 752 dc_mii_send(sc, frame->mii_regaddr, 5); 753 dc_mii_send(sc, frame->mii_turnaround, 2); 754 dc_mii_send(sc, frame->mii_data, 16); 755 756 /* Idle bit. */ 757 dc_mii_writebit(sc, 0); 758 dc_mii_writebit(sc, 0); 759 760 return (0); 761 } 762 763 static int 764 dc_miibus_readreg(device_t dev, int phy, int reg) 765 { 766 struct dc_mii_frame frame; 767 struct dc_softc *sc; 768 int i, rval, phy_reg = 0; 769 770 sc = device_get_softc(dev); 771 bzero(&frame, sizeof(frame)); 772 773 /* 774 * Note: both the AL981 and AN985 have internal PHYs, 775 * however the AL981 provides direct access to the PHY 776 * registers while the AN985 uses a serial MII interface. 777 * The AN985's MII interface is also buggy in that you 778 * can read from any MII address (0 to 31), but only address 1 779 * behaves normally. To deal with both cases, we pretend 780 * that the PHY is at MII address 1. 781 */ 782 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 783 return (0); 784 785 /* 786 * Note: the ukphy probes of the RS7112 report a PHY at 787 * MII address 0 (possibly HomePNA?) and 1 (ethernet) 788 * so we only respond to correct one. 789 */ 790 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 791 return (0); 792 793 if (sc->dc_pmode != DC_PMODE_MII) { 794 if (phy == (MII_NPHY - 1)) { 795 switch (reg) { 796 case MII_BMSR: 797 /* 798 * Fake something to make the probe 799 * code think there's a PHY here. 800 */ 801 return (BMSR_MEDIAMASK); 802 break; 803 case MII_PHYIDR1: 804 if (DC_IS_PNIC(sc)) 805 return (DC_VENDORID_LO); 806 return (DC_VENDORID_DEC); 807 break; 808 case MII_PHYIDR2: 809 if (DC_IS_PNIC(sc)) 810 return (DC_DEVICEID_82C168); 811 return (DC_DEVICEID_21143); 812 break; 813 default: 814 return (0); 815 break; 816 } 817 } else 818 return (0); 819 } 820 821 if (DC_IS_PNIC(sc)) { 822 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 823 (phy << 23) | (reg << 18)); 824 for (i = 0; i < DC_TIMEOUT; i++) { 825 DELAY(1); 826 rval = CSR_READ_4(sc, DC_PN_MII); 827 if (!(rval & DC_PN_MII_BUSY)) { 828 rval &= 0xFFFF; 829 return (rval == 0xFFFF ? 0 : rval); 830 } 831 } 832 return (0); 833 } 834 835 if (DC_IS_COMET(sc)) { 836 switch (reg) { 837 case MII_BMCR: 838 phy_reg = DC_AL_BMCR; 839 break; 840 case MII_BMSR: 841 phy_reg = DC_AL_BMSR; 842 break; 843 case MII_PHYIDR1: 844 phy_reg = DC_AL_VENID; 845 break; 846 case MII_PHYIDR2: 847 phy_reg = DC_AL_DEVID; 848 break; 849 case MII_ANAR: 850 phy_reg = DC_AL_ANAR; 851 break; 852 case MII_ANLPAR: 853 phy_reg = DC_AL_LPAR; 854 break; 855 case MII_ANER: 856 phy_reg = DC_AL_ANER; 857 break; 858 default: 859 device_printf(dev, "phy_read: bad phy register %x\n", 860 reg); 861 return (0); 862 break; 863 } 864 865 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 866 867 if (rval == 0xFFFF) 868 return (0); 869 return (rval); 870 } 871 872 frame.mii_phyaddr = phy; 873 frame.mii_regaddr = reg; 874 if (sc->dc_type == DC_TYPE_98713) { 875 phy_reg = CSR_READ_4(sc, DC_NETCFG); 876 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 877 } 878 dc_mii_readreg(sc, &frame); 879 if (sc->dc_type == DC_TYPE_98713) 880 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 881 882 return (frame.mii_data); 883 } 884 885 static int 886 dc_miibus_writereg(device_t dev, int phy, int reg, int data) 887 { 888 struct dc_softc *sc; 889 struct dc_mii_frame frame; 890 int i, phy_reg = 0; 891 892 sc = device_get_softc(dev); 893 bzero(&frame, sizeof(frame)); 894 895 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 896 return (0); 897 898 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 899 return (0); 900 901 if (DC_IS_PNIC(sc)) { 902 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 903 (phy << 23) | (reg << 10) | data); 904 for (i = 0; i < DC_TIMEOUT; i++) { 905 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 906 break; 907 } 908 return (0); 909 } 910 911 if (DC_IS_COMET(sc)) { 912 switch (reg) { 913 case MII_BMCR: 914 phy_reg = DC_AL_BMCR; 915 break; 916 case MII_BMSR: 917 phy_reg = DC_AL_BMSR; 918 break; 919 case MII_PHYIDR1: 920 phy_reg = DC_AL_VENID; 921 break; 922 case MII_PHYIDR2: 923 phy_reg = DC_AL_DEVID; 924 break; 925 case MII_ANAR: 926 phy_reg = DC_AL_ANAR; 927 break; 928 case MII_ANLPAR: 929 phy_reg = DC_AL_LPAR; 930 break; 931 case MII_ANER: 932 phy_reg = DC_AL_ANER; 933 break; 934 default: 935 device_printf(dev, "phy_write: bad phy register %x\n", 936 reg); 937 return (0); 938 break; 939 } 940 941 CSR_WRITE_4(sc, phy_reg, data); 942 return (0); 943 } 944 945 frame.mii_phyaddr = phy; 946 frame.mii_regaddr = reg; 947 frame.mii_data = data; 948 949 if (sc->dc_type == DC_TYPE_98713) { 950 phy_reg = CSR_READ_4(sc, DC_NETCFG); 951 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 952 } 953 dc_mii_writereg(sc, &frame); 954 if (sc->dc_type == DC_TYPE_98713) 955 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 956 957 return (0); 958 } 959 960 static void 961 dc_miibus_statchg(device_t dev) 962 { 963 struct dc_softc *sc; 964 struct mii_data *mii; 965 struct ifmedia *ifm; 966 967 sc = device_get_softc(dev); 968 if (DC_IS_ADMTEK(sc)) 969 return; 970 971 mii = device_get_softc(sc->dc_miibus); 972 ifm = &mii->mii_media; 973 if (DC_IS_DAVICOM(sc) && 974 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 975 dc_setcfg(sc, ifm->ifm_media); 976 sc->dc_if_media = ifm->ifm_media; 977 } else { 978 dc_setcfg(sc, mii->mii_media_active); 979 sc->dc_if_media = mii->mii_media_active; 980 } 981 } 982 983 /* 984 * Special support for DM9102A cards with HomePNA PHYs. Note: 985 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 986 * to be impossible to talk to the management interface of the DM9801 987 * PHY (its MDIO pin is not connected to anything). Consequently, 988 * the driver has to just 'know' about the additional mode and deal 989 * with it itself. *sigh* 990 */ 991 static void 992 dc_miibus_mediainit(device_t dev) 993 { 994 struct dc_softc *sc; 995 struct mii_data *mii; 996 struct ifmedia *ifm; 997 int rev; 998 999 rev = pci_get_revid(dev); 1000 1001 sc = device_get_softc(dev); 1002 mii = device_get_softc(sc->dc_miibus); 1003 ifm = &mii->mii_media; 1004 1005 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 1006 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL); 1007 } 1008 1009 #define DC_BITS_512 9 1010 #define DC_BITS_128 7 1011 #define DC_BITS_64 6 1012 1013 static uint32_t 1014 dc_mchash_le(struct dc_softc *sc, const uint8_t *addr) 1015 { 1016 uint32_t crc; 1017 1018 /* Compute CRC for the address value. */ 1019 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 1020 1021 /* 1022 * The hash table on the PNIC II and the MX98715AEC-C/D/E 1023 * chips is only 128 bits wide. 1024 */ 1025 if (sc->dc_flags & DC_128BIT_HASH) 1026 return (crc & ((1 << DC_BITS_128) - 1)); 1027 1028 /* The hash table on the MX98715BEC is only 64 bits wide. */ 1029 if (sc->dc_flags & DC_64BIT_HASH) 1030 return (crc & ((1 << DC_BITS_64) - 1)); 1031 1032 /* Xircom's hash filtering table is different (read: weird) */ 1033 /* Xircom uses the LEAST significant bits */ 1034 if (DC_IS_XIRCOM(sc)) { 1035 if ((crc & 0x180) == 0x180) 1036 return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4)); 1037 else 1038 return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 + 1039 (12 << 4)); 1040 } 1041 1042 return (crc & ((1 << DC_BITS_512) - 1)); 1043 } 1044 1045 /* 1046 * Calculate CRC of a multicast group address, return the lower 6 bits. 1047 */ 1048 static uint32_t 1049 dc_mchash_be(const uint8_t *addr) 1050 { 1051 uint32_t crc; 1052 1053 /* Compute CRC for the address value. */ 1054 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 1055 1056 /* Return the filter bit position. */ 1057 return ((crc >> 26) & 0x0000003F); 1058 } 1059 1060 /* 1061 * 21143-style RX filter setup routine. Filter programming is done by 1062 * downloading a special setup frame into the TX engine. 21143, Macronix, 1063 * PNIC, PNIC II and Davicom chips are programmed this way. 1064 * 1065 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1066 * address (our node address) and a 512-bit hash filter for multicast 1067 * frames. We also sneak the broadcast address into the hash filter since 1068 * we need that too. 1069 */ 1070 static void 1071 dc_setfilt_21143(struct dc_softc *sc) 1072 { 1073 uint16_t eaddr[(ETHER_ADDR_LEN+1)/2]; 1074 struct dc_desc *sframe; 1075 u_int32_t h, *sp; 1076 struct ifmultiaddr *ifma; 1077 struct ifnet *ifp; 1078 int i; 1079 1080 ifp = sc->dc_ifp; 1081 1082 i = sc->dc_cdata.dc_tx_prod; 1083 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1084 sc->dc_cdata.dc_tx_cnt++; 1085 sframe = &sc->dc_ldata->dc_tx_list[i]; 1086 sp = sc->dc_cdata.dc_sbuf; 1087 bzero(sp, DC_SFRAME_LEN); 1088 1089 sframe->dc_data = htole32(sc->dc_saddr); 1090 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1091 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1092 1093 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1094 1095 /* If we want promiscuous mode, set the allframes bit. */ 1096 if (ifp->if_flags & IFF_PROMISC) 1097 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1098 else 1099 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1100 1101 if (ifp->if_flags & IFF_ALLMULTI) 1102 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1103 else 1104 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1105 1106 IF_ADDR_LOCK(ifp); 1107 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1108 if (ifma->ifma_addr->sa_family != AF_LINK) 1109 continue; 1110 h = dc_mchash_le(sc, 1111 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1112 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1113 } 1114 IF_ADDR_UNLOCK(ifp); 1115 1116 if (ifp->if_flags & IFF_BROADCAST) { 1117 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1118 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1119 } 1120 1121 /* Set our MAC address. */ 1122 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1123 sp[39] = DC_SP_MAC(eaddr[0]); 1124 sp[40] = DC_SP_MAC(eaddr[1]); 1125 sp[41] = DC_SP_MAC(eaddr[2]); 1126 1127 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1128 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1129 1130 /* 1131 * The PNIC takes an exceedingly long time to process its 1132 * setup frame; wait 10ms after posting the setup frame 1133 * before proceeding, just so it has time to swallow its 1134 * medicine. 1135 */ 1136 DELAY(10000); 1137 1138 sc->dc_wdog_timer = 5; 1139 } 1140 1141 static void 1142 dc_setfilt_admtek(struct dc_softc *sc) 1143 { 1144 uint8_t eaddr[ETHER_ADDR_LEN]; 1145 struct ifnet *ifp; 1146 struct ifmultiaddr *ifma; 1147 int h = 0; 1148 u_int32_t hashes[2] = { 0, 0 }; 1149 1150 ifp = sc->dc_ifp; 1151 1152 /* Init our MAC address. */ 1153 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1154 CSR_WRITE_4(sc, DC_AL_PAR0, eaddr[3] << 24 | eaddr[2] << 16 | 1155 eaddr[1] << 8 | eaddr[0]); 1156 CSR_WRITE_4(sc, DC_AL_PAR1, eaddr[5] << 8 | eaddr[4]); 1157 1158 /* If we want promiscuous mode, set the allframes bit. */ 1159 if (ifp->if_flags & IFF_PROMISC) 1160 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1161 else 1162 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1163 1164 if (ifp->if_flags & IFF_ALLMULTI) 1165 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1166 else 1167 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1168 1169 /* First, zot all the existing hash bits. */ 1170 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1171 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1172 1173 /* 1174 * If we're already in promisc or allmulti mode, we 1175 * don't have to bother programming the multicast filter. 1176 */ 1177 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1178 return; 1179 1180 /* Now program new ones. */ 1181 IF_ADDR_LOCK(ifp); 1182 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1183 if (ifma->ifma_addr->sa_family != AF_LINK) 1184 continue; 1185 if (DC_IS_CENTAUR(sc)) 1186 h = dc_mchash_le(sc, 1187 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1188 else 1189 h = dc_mchash_be( 1190 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1191 if (h < 32) 1192 hashes[0] |= (1 << h); 1193 else 1194 hashes[1] |= (1 << (h - 32)); 1195 } 1196 IF_ADDR_UNLOCK(ifp); 1197 1198 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1199 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1200 } 1201 1202 static void 1203 dc_setfilt_asix(struct dc_softc *sc) 1204 { 1205 uint32_t eaddr[(ETHER_ADDR_LEN+3)/4]; 1206 struct ifnet *ifp; 1207 struct ifmultiaddr *ifma; 1208 int h = 0; 1209 u_int32_t hashes[2] = { 0, 0 }; 1210 1211 ifp = sc->dc_ifp; 1212 1213 /* Init our MAC address. */ 1214 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1215 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1216 CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[0]); 1217 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1218 CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[1]); 1219 1220 /* If we want promiscuous mode, set the allframes bit. */ 1221 if (ifp->if_flags & IFF_PROMISC) 1222 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1223 else 1224 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1225 1226 if (ifp->if_flags & IFF_ALLMULTI) 1227 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1228 else 1229 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1230 1231 /* 1232 * The ASIX chip has a special bit to enable reception 1233 * of broadcast frames. 1234 */ 1235 if (ifp->if_flags & IFF_BROADCAST) 1236 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1237 else 1238 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1239 1240 /* first, zot all the existing hash bits */ 1241 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1242 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1243 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1244 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1245 1246 /* 1247 * If we're already in promisc or allmulti mode, we 1248 * don't have to bother programming the multicast filter. 1249 */ 1250 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1251 return; 1252 1253 /* now program new ones */ 1254 IF_ADDR_LOCK(ifp); 1255 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1256 if (ifma->ifma_addr->sa_family != AF_LINK) 1257 continue; 1258 h = dc_mchash_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1259 if (h < 32) 1260 hashes[0] |= (1 << h); 1261 else 1262 hashes[1] |= (1 << (h - 32)); 1263 } 1264 IF_ADDR_UNLOCK(ifp); 1265 1266 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1267 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1268 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1269 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1270 } 1271 1272 static void 1273 dc_setfilt_xircom(struct dc_softc *sc) 1274 { 1275 uint16_t eaddr[(ETHER_ADDR_LEN+1)/2]; 1276 struct ifnet *ifp; 1277 struct ifmultiaddr *ifma; 1278 struct dc_desc *sframe; 1279 u_int32_t h, *sp; 1280 int i; 1281 1282 ifp = sc->dc_ifp; 1283 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1284 1285 i = sc->dc_cdata.dc_tx_prod; 1286 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1287 sc->dc_cdata.dc_tx_cnt++; 1288 sframe = &sc->dc_ldata->dc_tx_list[i]; 1289 sp = sc->dc_cdata.dc_sbuf; 1290 bzero(sp, DC_SFRAME_LEN); 1291 1292 sframe->dc_data = htole32(sc->dc_saddr); 1293 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1294 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1295 1296 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1297 1298 /* If we want promiscuous mode, set the allframes bit. */ 1299 if (ifp->if_flags & IFF_PROMISC) 1300 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1301 else 1302 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1303 1304 if (ifp->if_flags & IFF_ALLMULTI) 1305 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1306 else 1307 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1308 1309 IF_ADDR_LOCK(ifp); 1310 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1311 if (ifma->ifma_addr->sa_family != AF_LINK) 1312 continue; 1313 h = dc_mchash_le(sc, 1314 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1315 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1316 } 1317 IF_ADDR_UNLOCK(ifp); 1318 1319 if (ifp->if_flags & IFF_BROADCAST) { 1320 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1321 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1322 } 1323 1324 /* Set our MAC address. */ 1325 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1326 sp[0] = DC_SP_MAC(eaddr[0]); 1327 sp[1] = DC_SP_MAC(eaddr[1]); 1328 sp[2] = DC_SP_MAC(eaddr[2]); 1329 1330 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1331 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1332 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1333 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1334 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1335 1336 /* 1337 * Wait some time... 1338 */ 1339 DELAY(1000); 1340 1341 sc->dc_wdog_timer = 5; 1342 } 1343 1344 static void 1345 dc_setfilt(struct dc_softc *sc) 1346 { 1347 1348 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1349 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1350 dc_setfilt_21143(sc); 1351 1352 if (DC_IS_ASIX(sc)) 1353 dc_setfilt_asix(sc); 1354 1355 if (DC_IS_ADMTEK(sc)) 1356 dc_setfilt_admtek(sc); 1357 1358 if (DC_IS_XIRCOM(sc)) 1359 dc_setfilt_xircom(sc); 1360 } 1361 1362 /* 1363 * In order to fiddle with the 'full-duplex' and '100Mbps' bits in 1364 * the netconfig register, we first have to put the transmit and/or 1365 * receive logic in the idle state. 1366 */ 1367 static void 1368 dc_setcfg(struct dc_softc *sc, int media) 1369 { 1370 int i, restart = 0, watchdogreg; 1371 u_int32_t isr; 1372 1373 if (IFM_SUBTYPE(media) == IFM_NONE) 1374 return; 1375 1376 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) { 1377 restart = 1; 1378 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1379 1380 for (i = 0; i < DC_TIMEOUT; i++) { 1381 isr = CSR_READ_4(sc, DC_ISR); 1382 if (isr & DC_ISR_TX_IDLE && 1383 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1384 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT)) 1385 break; 1386 DELAY(10); 1387 } 1388 1389 if (i == DC_TIMEOUT) { 1390 if (!(isr & DC_ISR_TX_IDLE) && !DC_IS_ASIX(sc)) 1391 device_printf(sc->dc_dev, 1392 "%s: failed to force tx to idle state\n", 1393 __func__); 1394 if (!((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1395 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT) && 1396 !DC_HAS_BROKEN_RXSTATE(sc)) 1397 device_printf(sc->dc_dev, 1398 "%s: failed to force rx to idle state\n", 1399 __func__); 1400 } 1401 } 1402 1403 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1404 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1405 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1406 if (sc->dc_pmode == DC_PMODE_MII) { 1407 if (DC_IS_INTEL(sc)) { 1408 /* There's a write enable bit here that reads as 1. */ 1409 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1410 watchdogreg &= ~DC_WDOG_CTLWREN; 1411 watchdogreg |= DC_WDOG_JABBERDIS; 1412 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1413 } else { 1414 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1415 } 1416 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1417 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1418 if (sc->dc_type == DC_TYPE_98713) 1419 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1420 DC_NETCFG_SCRAMBLER)); 1421 if (!DC_IS_DAVICOM(sc)) 1422 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1423 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1424 if (DC_IS_INTEL(sc)) 1425 dc_apply_fixup(sc, IFM_AUTO); 1426 } else { 1427 if (DC_IS_PNIC(sc)) { 1428 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1429 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1430 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1431 } 1432 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1433 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1434 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1435 if (DC_IS_INTEL(sc)) 1436 dc_apply_fixup(sc, 1437 (media & IFM_GMASK) == IFM_FDX ? 1438 IFM_100_TX | IFM_FDX : IFM_100_TX); 1439 } 1440 } 1441 1442 if (IFM_SUBTYPE(media) == IFM_10_T) { 1443 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1444 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1445 if (sc->dc_pmode == DC_PMODE_MII) { 1446 /* There's a write enable bit here that reads as 1. */ 1447 if (DC_IS_INTEL(sc)) { 1448 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1449 watchdogreg &= ~DC_WDOG_CTLWREN; 1450 watchdogreg |= DC_WDOG_JABBERDIS; 1451 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1452 } else { 1453 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1454 } 1455 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1456 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1457 if (sc->dc_type == DC_TYPE_98713) 1458 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1459 if (!DC_IS_DAVICOM(sc)) 1460 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1461 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1462 if (DC_IS_INTEL(sc)) 1463 dc_apply_fixup(sc, IFM_AUTO); 1464 } else { 1465 if (DC_IS_PNIC(sc)) { 1466 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1467 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1468 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1469 } 1470 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1471 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1472 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1473 if (DC_IS_INTEL(sc)) { 1474 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1475 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1476 if ((media & IFM_GMASK) == IFM_FDX) 1477 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1478 else 1479 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1480 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1481 DC_CLRBIT(sc, DC_10BTCTRL, 1482 DC_TCTL_AUTONEGENBL); 1483 dc_apply_fixup(sc, 1484 (media & IFM_GMASK) == IFM_FDX ? 1485 IFM_10_T | IFM_FDX : IFM_10_T); 1486 DELAY(20000); 1487 } 1488 } 1489 } 1490 1491 /* 1492 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1493 * PHY and we want HomePNA mode, set the portsel bit to turn 1494 * on the external MII port. 1495 */ 1496 if (DC_IS_DAVICOM(sc)) { 1497 if (IFM_SUBTYPE(media) == IFM_HPNA_1) { 1498 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1499 sc->dc_link = 1; 1500 } else { 1501 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1502 } 1503 } 1504 1505 if ((media & IFM_GMASK) == IFM_FDX) { 1506 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1507 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1508 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1509 } else { 1510 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1511 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1512 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1513 } 1514 1515 if (restart) 1516 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON | DC_NETCFG_RX_ON); 1517 } 1518 1519 static void 1520 dc_reset(struct dc_softc *sc) 1521 { 1522 int i; 1523 1524 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1525 1526 for (i = 0; i < DC_TIMEOUT; i++) { 1527 DELAY(10); 1528 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1529 break; 1530 } 1531 1532 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) || 1533 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) { 1534 DELAY(10000); 1535 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1536 i = 0; 1537 } 1538 1539 if (i == DC_TIMEOUT) 1540 device_printf(sc->dc_dev, "reset never completed!\n"); 1541 1542 /* Wait a little while for the chip to get its brains in order. */ 1543 DELAY(1000); 1544 1545 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1546 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1547 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1548 1549 /* 1550 * Bring the SIA out of reset. In some cases, it looks 1551 * like failing to unreset the SIA soon enough gets it 1552 * into a state where it will never come out of reset 1553 * until we reset the whole chip again. 1554 */ 1555 if (DC_IS_INTEL(sc)) { 1556 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1557 CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1558 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1559 } 1560 } 1561 1562 static const struct dc_type * 1563 dc_devtype(device_t dev) 1564 { 1565 const struct dc_type *t; 1566 u_int32_t devid; 1567 u_int8_t rev; 1568 1569 t = dc_devs; 1570 devid = pci_get_devid(dev); 1571 rev = pci_get_revid(dev); 1572 1573 while (t->dc_name != NULL) { 1574 if (devid == t->dc_devid && rev >= t->dc_minrev) 1575 return (t); 1576 t++; 1577 } 1578 1579 return (NULL); 1580 } 1581 1582 /* 1583 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1584 * IDs against our list and return a device name if we find a match. 1585 * We do a little bit of extra work to identify the exact type of 1586 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1587 * but different revision IDs. The same is true for 98715/98715A 1588 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1589 * cases, the exact chip revision affects driver behavior. 1590 */ 1591 static int 1592 dc_probe(device_t dev) 1593 { 1594 const struct dc_type *t; 1595 1596 t = dc_devtype(dev); 1597 1598 if (t != NULL) { 1599 device_set_desc(dev, t->dc_name); 1600 return (BUS_PROBE_DEFAULT); 1601 } 1602 1603 return (ENXIO); 1604 } 1605 1606 static void 1607 dc_apply_fixup(struct dc_softc *sc, int media) 1608 { 1609 struct dc_mediainfo *m; 1610 u_int8_t *p; 1611 int i; 1612 u_int32_t reg; 1613 1614 m = sc->dc_mi; 1615 1616 while (m != NULL) { 1617 if (m->dc_media == media) 1618 break; 1619 m = m->dc_next; 1620 } 1621 1622 if (m == NULL) 1623 return; 1624 1625 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1626 reg = (p[0] | (p[1] << 8)) << 16; 1627 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1628 } 1629 1630 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1631 reg = (p[0] | (p[1] << 8)) << 16; 1632 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1633 } 1634 } 1635 1636 static void 1637 dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l) 1638 { 1639 struct dc_mediainfo *m; 1640 1641 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1642 switch (l->dc_sia_code & ~DC_SIA_CODE_EXT) { 1643 case DC_SIA_CODE_10BT: 1644 m->dc_media = IFM_10_T; 1645 break; 1646 case DC_SIA_CODE_10BT_FDX: 1647 m->dc_media = IFM_10_T | IFM_FDX; 1648 break; 1649 case DC_SIA_CODE_10B2: 1650 m->dc_media = IFM_10_2; 1651 break; 1652 case DC_SIA_CODE_10B5: 1653 m->dc_media = IFM_10_5; 1654 break; 1655 default: 1656 break; 1657 } 1658 1659 /* 1660 * We need to ignore CSR13, CSR14, CSR15 for SIA mode. 1661 * Things apparently already work for cards that do 1662 * supply Media Specific Data. 1663 */ 1664 if (l->dc_sia_code & DC_SIA_CODE_EXT) { 1665 m->dc_gp_len = 2; 1666 m->dc_gp_ptr = 1667 (u_int8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl; 1668 } else { 1669 m->dc_gp_len = 2; 1670 m->dc_gp_ptr = 1671 (u_int8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl; 1672 } 1673 1674 m->dc_next = sc->dc_mi; 1675 sc->dc_mi = m; 1676 1677 sc->dc_pmode = DC_PMODE_SIA; 1678 } 1679 1680 static void 1681 dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l) 1682 { 1683 struct dc_mediainfo *m; 1684 1685 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1686 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1687 m->dc_media = IFM_100_TX; 1688 1689 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1690 m->dc_media = IFM_100_TX | IFM_FDX; 1691 1692 m->dc_gp_len = 2; 1693 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1694 1695 m->dc_next = sc->dc_mi; 1696 sc->dc_mi = m; 1697 1698 sc->dc_pmode = DC_PMODE_SYM; 1699 } 1700 1701 static void 1702 dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l) 1703 { 1704 struct dc_mediainfo *m; 1705 u_int8_t *p; 1706 1707 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1708 /* We abuse IFM_AUTO to represent MII. */ 1709 m->dc_media = IFM_AUTO; 1710 m->dc_gp_len = l->dc_gpr_len; 1711 1712 p = (u_int8_t *)l; 1713 p += sizeof(struct dc_eblock_mii); 1714 m->dc_gp_ptr = p; 1715 p += 2 * l->dc_gpr_len; 1716 m->dc_reset_len = *p; 1717 p++; 1718 m->dc_reset_ptr = p; 1719 1720 m->dc_next = sc->dc_mi; 1721 sc->dc_mi = m; 1722 } 1723 1724 static void 1725 dc_read_srom(struct dc_softc *sc, int bits) 1726 { 1727 int size; 1728 1729 size = 2 << bits; 1730 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT); 1731 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); 1732 } 1733 1734 static void 1735 dc_parse_21143_srom(struct dc_softc *sc) 1736 { 1737 struct dc_leaf_hdr *lhdr; 1738 struct dc_eblock_hdr *hdr; 1739 int have_mii, i, loff; 1740 char *ptr; 1741 1742 have_mii = 0; 1743 loff = sc->dc_srom[27]; 1744 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1745 1746 ptr = (char *)lhdr; 1747 ptr += sizeof(struct dc_leaf_hdr) - 1; 1748 /* 1749 * Look if we got a MII media block. 1750 */ 1751 for (i = 0; i < lhdr->dc_mcnt; i++) { 1752 hdr = (struct dc_eblock_hdr *)ptr; 1753 if (hdr->dc_type == DC_EBLOCK_MII) 1754 have_mii++; 1755 1756 ptr += (hdr->dc_len & 0x7F); 1757 ptr++; 1758 } 1759 1760 /* 1761 * Do the same thing again. Only use SIA and SYM media 1762 * blocks if no MII media block is available. 1763 */ 1764 ptr = (char *)lhdr; 1765 ptr += sizeof(struct dc_leaf_hdr) - 1; 1766 for (i = 0; i < lhdr->dc_mcnt; i++) { 1767 hdr = (struct dc_eblock_hdr *)ptr; 1768 switch (hdr->dc_type) { 1769 case DC_EBLOCK_MII: 1770 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1771 break; 1772 case DC_EBLOCK_SIA: 1773 if (! have_mii) 1774 dc_decode_leaf_sia(sc, 1775 (struct dc_eblock_sia *)hdr); 1776 break; 1777 case DC_EBLOCK_SYM: 1778 if (! have_mii) 1779 dc_decode_leaf_sym(sc, 1780 (struct dc_eblock_sym *)hdr); 1781 break; 1782 default: 1783 /* Don't care. Yet. */ 1784 break; 1785 } 1786 ptr += (hdr->dc_len & 0x7F); 1787 ptr++; 1788 } 1789 } 1790 1791 static void 1792 dc_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1793 { 1794 u_int32_t *paddr; 1795 1796 KASSERT(nseg == 1, 1797 ("%s: wrong number of segments (%d)", __func__, nseg)); 1798 paddr = arg; 1799 *paddr = segs->ds_addr; 1800 } 1801 1802 /* 1803 * Attach the interface. Allocate softc structures, do ifmedia 1804 * setup and ethernet/BPF attach. 1805 */ 1806 static int 1807 dc_attach(device_t dev) 1808 { 1809 int tmp = 0; 1810 uint32_t eaddr[(ETHER_ADDR_LEN+3)/4]; 1811 u_int32_t command; 1812 struct dc_softc *sc; 1813 struct ifnet *ifp; 1814 u_int32_t reg, revision; 1815 int error = 0, rid, mac_offset; 1816 int i; 1817 u_int8_t *mac; 1818 1819 sc = device_get_softc(dev); 1820 sc->dc_dev = dev; 1821 1822 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1823 MTX_DEF); 1824 1825 /* 1826 * Map control/status registers. 1827 */ 1828 pci_enable_busmaster(dev); 1829 1830 rid = DC_RID; 1831 sc->dc_res = bus_alloc_resource_any(dev, DC_RES, &rid, RF_ACTIVE); 1832 1833 if (sc->dc_res == NULL) { 1834 device_printf(dev, "couldn't map ports/memory\n"); 1835 error = ENXIO; 1836 goto fail; 1837 } 1838 1839 sc->dc_btag = rman_get_bustag(sc->dc_res); 1840 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1841 1842 /* Allocate interrupt. */ 1843 rid = 0; 1844 sc->dc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1845 RF_SHAREABLE | RF_ACTIVE); 1846 1847 if (sc->dc_irq == NULL) { 1848 device_printf(dev, "couldn't map interrupt\n"); 1849 error = ENXIO; 1850 goto fail; 1851 } 1852 1853 /* Need this info to decide on a chip type. */ 1854 sc->dc_info = dc_devtype(dev); 1855 revision = pci_get_revid(dev); 1856 1857 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */ 1858 if (sc->dc_info->dc_devid != 1859 DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168) && 1860 sc->dc_info->dc_devid != 1861 DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201)) 1862 dc_eeprom_width(sc); 1863 1864 switch (sc->dc_info->dc_devid) { 1865 case DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143): 1866 sc->dc_type = DC_TYPE_21143; 1867 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1868 sc->dc_flags |= DC_REDUCED_MII_POLL; 1869 /* Save EEPROM contents so we can parse them later. */ 1870 dc_read_srom(sc, sc->dc_romwidth); 1871 break; 1872 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009): 1873 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100): 1874 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102): 1875 sc->dc_type = DC_TYPE_DM9102; 1876 sc->dc_flags |= DC_TX_COALESCE | DC_TX_INTR_ALWAYS; 1877 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_TX_STORENFWD; 1878 sc->dc_flags |= DC_TX_ALIGN; 1879 sc->dc_pmode = DC_PMODE_MII; 1880 1881 /* Increase the latency timer value. */ 1882 pci_write_config(dev, PCIR_LATTIMER, 0x80, 1); 1883 break; 1884 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981): 1885 sc->dc_type = DC_TYPE_AL981; 1886 sc->dc_flags |= DC_TX_USE_TX_INTR; 1887 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1888 sc->dc_pmode = DC_PMODE_MII; 1889 dc_read_srom(sc, sc->dc_romwidth); 1890 break; 1891 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985): 1892 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511): 1893 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513): 1894 case DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD): 1895 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_FA511): 1896 case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500): 1897 case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX): 1898 case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242): 1899 case DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX): 1900 case DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T): 1901 case DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB): 1902 case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120): 1903 case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130): 1904 case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08): 1905 case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09): 1906 sc->dc_type = DC_TYPE_AN985; 1907 sc->dc_flags |= DC_64BIT_HASH; 1908 sc->dc_flags |= DC_TX_USE_TX_INTR; 1909 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1910 sc->dc_pmode = DC_PMODE_MII; 1911 /* Don't read SROM for - auto-loaded on reset */ 1912 break; 1913 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713): 1914 case DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP): 1915 if (revision < DC_REVISION_98713A) { 1916 sc->dc_type = DC_TYPE_98713; 1917 } 1918 if (revision >= DC_REVISION_98713A) { 1919 sc->dc_type = DC_TYPE_98713A; 1920 sc->dc_flags |= DC_21143_NWAY; 1921 } 1922 sc->dc_flags |= DC_REDUCED_MII_POLL; 1923 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1924 break; 1925 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5): 1926 case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217): 1927 /* 1928 * Macronix MX98715AEC-C/D/E parts have only a 1929 * 128-bit hash table. We need to deal with these 1930 * in the same manner as the PNIC II so that we 1931 * get the right number of bits out of the 1932 * CRC routine. 1933 */ 1934 if (revision >= DC_REVISION_98715AEC_C && 1935 revision < DC_REVISION_98725) 1936 sc->dc_flags |= DC_128BIT_HASH; 1937 sc->dc_type = DC_TYPE_987x5; 1938 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1939 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1940 break; 1941 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727): 1942 sc->dc_type = DC_TYPE_987x5; 1943 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1944 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1945 break; 1946 case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115): 1947 sc->dc_type = DC_TYPE_PNICII; 1948 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR | DC_128BIT_HASH; 1949 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1950 break; 1951 case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168): 1952 sc->dc_type = DC_TYPE_PNIC; 1953 sc->dc_flags |= DC_TX_STORENFWD | DC_TX_INTR_ALWAYS; 1954 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 1955 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 1956 if (revision < DC_REVISION_82C169) 1957 sc->dc_pmode = DC_PMODE_SYM; 1958 break; 1959 case DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A): 1960 sc->dc_type = DC_TYPE_ASIX; 1961 sc->dc_flags |= DC_TX_USE_TX_INTR | DC_TX_INTR_FIRSTFRAG; 1962 sc->dc_flags |= DC_REDUCED_MII_POLL; 1963 sc->dc_pmode = DC_PMODE_MII; 1964 break; 1965 case DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201): 1966 sc->dc_type = DC_TYPE_XIRCOM; 1967 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 1968 DC_TX_ALIGN; 1969 /* 1970 * We don't actually need to coalesce, but we're doing 1971 * it to obtain a double word aligned buffer. 1972 * The DC_TX_COALESCE flag is required. 1973 */ 1974 sc->dc_pmode = DC_PMODE_MII; 1975 break; 1976 case DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112): 1977 sc->dc_type = DC_TYPE_CONEXANT; 1978 sc->dc_flags |= DC_TX_INTR_ALWAYS; 1979 sc->dc_flags |= DC_REDUCED_MII_POLL; 1980 sc->dc_pmode = DC_PMODE_MII; 1981 dc_read_srom(sc, sc->dc_romwidth); 1982 break; 1983 default: 1984 device_printf(dev, "unknown device: %x\n", 1985 sc->dc_info->dc_devid); 1986 break; 1987 } 1988 1989 /* Save the cache line size. */ 1990 if (DC_IS_DAVICOM(sc)) 1991 sc->dc_cachesize = 0; 1992 else 1993 sc->dc_cachesize = pci_get_cachelnsz(dev); 1994 1995 /* Reset the adapter. */ 1996 dc_reset(sc); 1997 1998 /* Take 21143 out of snooze mode */ 1999 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 2000 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2001 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 2002 pci_write_config(dev, DC_PCI_CFDD, command, 4); 2003 } 2004 2005 /* 2006 * Try to learn something about the supported media. 2007 * We know that ASIX and ADMtek and Davicom devices 2008 * will *always* be using MII media, so that's a no-brainer. 2009 * The tricky ones are the Macronix/PNIC II and the 2010 * Intel 21143. 2011 */ 2012 if (DC_IS_INTEL(sc)) 2013 dc_parse_21143_srom(sc); 2014 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2015 if (sc->dc_type == DC_TYPE_98713) 2016 sc->dc_pmode = DC_PMODE_MII; 2017 else 2018 sc->dc_pmode = DC_PMODE_SYM; 2019 } else if (!sc->dc_pmode) 2020 sc->dc_pmode = DC_PMODE_MII; 2021 2022 /* 2023 * Get station address from the EEPROM. 2024 */ 2025 switch(sc->dc_type) { 2026 case DC_TYPE_98713: 2027 case DC_TYPE_98713A: 2028 case DC_TYPE_987x5: 2029 case DC_TYPE_PNICII: 2030 dc_read_eeprom(sc, (caddr_t)&mac_offset, 2031 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2032 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2033 break; 2034 case DC_TYPE_PNIC: 2035 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2036 break; 2037 case DC_TYPE_DM9102: 2038 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2039 #ifdef __sparc64__ 2040 /* 2041 * If this is an onboard dc(4) the station address read from 2042 * the EEPROM is all zero and we have to get it from the FCode. 2043 */ 2044 if (eaddr[0] == 0 && (eaddr[1] & ~0xffff) == 0) 2045 OF_getetheraddr(dev, (caddr_t)&eaddr); 2046 #endif 2047 break; 2048 case DC_TYPE_21143: 2049 case DC_TYPE_ASIX: 2050 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2051 break; 2052 case DC_TYPE_AL981: 2053 case DC_TYPE_AN985: 2054 reg = CSR_READ_4(sc, DC_AL_PAR0); 2055 mac = (uint8_t *)&eaddr[0]; 2056 mac[0] = (reg >> 0) & 0xff; 2057 mac[1] = (reg >> 8) & 0xff; 2058 mac[2] = (reg >> 16) & 0xff; 2059 mac[3] = (reg >> 24) & 0xff; 2060 reg = CSR_READ_4(sc, DC_AL_PAR1); 2061 mac[4] = (reg >> 0) & 0xff; 2062 mac[5] = (reg >> 8) & 0xff; 2063 break; 2064 case DC_TYPE_CONEXANT: 2065 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 2066 ETHER_ADDR_LEN); 2067 break; 2068 case DC_TYPE_XIRCOM: 2069 /* The MAC comes from the CIS. */ 2070 mac = pci_get_ether(dev); 2071 if (!mac) { 2072 device_printf(dev, "No station address in CIS!\n"); 2073 error = ENXIO; 2074 goto fail; 2075 } 2076 bcopy(mac, eaddr, ETHER_ADDR_LEN); 2077 break; 2078 default: 2079 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2080 break; 2081 } 2082 2083 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */ 2084 error = bus_dma_tag_create(bus_get_dma_tag(dev), PAGE_SIZE, 0, 2085 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 2086 sizeof(struct dc_list_data), 1, sizeof(struct dc_list_data), 2087 0, NULL, NULL, &sc->dc_ltag); 2088 if (error) { 2089 device_printf(dev, "failed to allocate busdma tag\n"); 2090 error = ENXIO; 2091 goto fail; 2092 } 2093 error = bus_dmamem_alloc(sc->dc_ltag, (void **)&sc->dc_ldata, 2094 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->dc_lmap); 2095 if (error) { 2096 device_printf(dev, "failed to allocate DMA safe memory\n"); 2097 error = ENXIO; 2098 goto fail; 2099 } 2100 error = bus_dmamap_load(sc->dc_ltag, sc->dc_lmap, sc->dc_ldata, 2101 sizeof(struct dc_list_data), dc_dma_map_addr, &sc->dc_laddr, 2102 BUS_DMA_NOWAIT); 2103 if (error) { 2104 device_printf(dev, "cannot get address of the descriptors\n"); 2105 error = ENXIO; 2106 goto fail; 2107 } 2108 2109 /* 2110 * Allocate a busdma tag and DMA safe memory for the multicast 2111 * setup frame. 2112 */ 2113 error = bus_dma_tag_create(bus_get_dma_tag(dev), PAGE_SIZE, 0, 2114 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 2115 DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1, DC_SFRAME_LEN + DC_MIN_FRAMELEN, 2116 0, NULL, NULL, &sc->dc_stag); 2117 if (error) { 2118 device_printf(dev, "failed to allocate busdma tag\n"); 2119 error = ENXIO; 2120 goto fail; 2121 } 2122 error = bus_dmamem_alloc(sc->dc_stag, (void **)&sc->dc_cdata.dc_sbuf, 2123 BUS_DMA_NOWAIT, &sc->dc_smap); 2124 if (error) { 2125 device_printf(dev, "failed to allocate DMA safe memory\n"); 2126 error = ENXIO; 2127 goto fail; 2128 } 2129 error = bus_dmamap_load(sc->dc_stag, sc->dc_smap, sc->dc_cdata.dc_sbuf, 2130 DC_SFRAME_LEN, dc_dma_map_addr, &sc->dc_saddr, BUS_DMA_NOWAIT); 2131 if (error) { 2132 device_printf(dev, "cannot get address of the descriptors\n"); 2133 error = ENXIO; 2134 goto fail; 2135 } 2136 2137 /* Allocate a busdma tag for mbufs. */ 2138 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 2139 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 2140 MCLBYTES * DC_MAXFRAGS, DC_MAXFRAGS, MCLBYTES, 2141 0, NULL, NULL, &sc->dc_mtag); 2142 if (error) { 2143 device_printf(dev, "failed to allocate busdma tag\n"); 2144 error = ENXIO; 2145 goto fail; 2146 } 2147 2148 /* Create the TX/RX busdma maps. */ 2149 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2150 error = bus_dmamap_create(sc->dc_mtag, 0, 2151 &sc->dc_cdata.dc_tx_map[i]); 2152 if (error) { 2153 device_printf(dev, "failed to init TX ring\n"); 2154 error = ENXIO; 2155 goto fail; 2156 } 2157 } 2158 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2159 error = bus_dmamap_create(sc->dc_mtag, 0, 2160 &sc->dc_cdata.dc_rx_map[i]); 2161 if (error) { 2162 device_printf(dev, "failed to init RX ring\n"); 2163 error = ENXIO; 2164 goto fail; 2165 } 2166 } 2167 error = bus_dmamap_create(sc->dc_mtag, 0, &sc->dc_sparemap); 2168 if (error) { 2169 device_printf(dev, "failed to init RX ring\n"); 2170 error = ENXIO; 2171 goto fail; 2172 } 2173 2174 ifp = sc->dc_ifp = if_alloc(IFT_ETHER); 2175 if (ifp == NULL) { 2176 device_printf(dev, "can not if_alloc()\n"); 2177 error = ENOSPC; 2178 goto fail; 2179 } 2180 ifp->if_softc = sc; 2181 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2182 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2183 ifp->if_ioctl = dc_ioctl; 2184 ifp->if_start = dc_start; 2185 ifp->if_init = dc_init; 2186 IFQ_SET_MAXLEN(&ifp->if_snd, DC_TX_LIST_CNT - 1); 2187 ifp->if_snd.ifq_drv_maxlen = DC_TX_LIST_CNT - 1; 2188 IFQ_SET_READY(&ifp->if_snd); 2189 2190 /* 2191 * Do MII setup. If this is a 21143, check for a PHY on the 2192 * MII bus after applying any necessary fixups to twiddle the 2193 * GPIO bits. If we don't end up finding a PHY, restore the 2194 * old selection (SIA only or SIA/SYM) and attach the dcphy 2195 * driver instead. 2196 */ 2197 if (DC_IS_INTEL(sc)) { 2198 dc_apply_fixup(sc, IFM_AUTO); 2199 tmp = sc->dc_pmode; 2200 sc->dc_pmode = DC_PMODE_MII; 2201 } 2202 2203 /* 2204 * Setup General Purpose port mode and data so the tulip can talk 2205 * to the MII. This needs to be done before mii_phy_probe so that 2206 * we can actually see them. 2207 */ 2208 if (DC_IS_XIRCOM(sc)) { 2209 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2210 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2211 DELAY(10); 2212 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2213 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2214 DELAY(10); 2215 } 2216 2217 error = mii_phy_probe(dev, &sc->dc_miibus, 2218 dc_ifmedia_upd, dc_ifmedia_sts); 2219 2220 if (error && DC_IS_INTEL(sc)) { 2221 sc->dc_pmode = tmp; 2222 if (sc->dc_pmode != DC_PMODE_SIA) 2223 sc->dc_pmode = DC_PMODE_SYM; 2224 sc->dc_flags |= DC_21143_NWAY; 2225 mii_phy_probe(dev, &sc->dc_miibus, 2226 dc_ifmedia_upd, dc_ifmedia_sts); 2227 /* 2228 * For non-MII cards, we need to have the 21143 2229 * drive the LEDs. Except there are some systems 2230 * like the NEC VersaPro NoteBook PC which have no 2231 * LEDs, and twiddling these bits has adverse effects 2232 * on them. (I.e. you suddenly can't get a link.) 2233 */ 2234 if (!(pci_get_subvendor(dev) == 0x1033 && 2235 pci_get_subdevice(dev) == 0x8028)) 2236 sc->dc_flags |= DC_TULIP_LEDS; 2237 error = 0; 2238 } 2239 2240 if (error) { 2241 device_printf(dev, "MII without any PHY!\n"); 2242 goto fail; 2243 } 2244 2245 if (DC_IS_ADMTEK(sc)) { 2246 /* 2247 * Set automatic TX underrun recovery for the ADMtek chips 2248 */ 2249 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); 2250 } 2251 2252 /* 2253 * Tell the upper layer(s) we support long frames. 2254 */ 2255 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2256 ifp->if_capabilities |= IFCAP_VLAN_MTU; 2257 ifp->if_capenable = ifp->if_capabilities; 2258 #ifdef DEVICE_POLLING 2259 ifp->if_capabilities |= IFCAP_POLLING; 2260 #endif 2261 2262 callout_init_mtx(&sc->dc_stat_ch, &sc->dc_mtx, 0); 2263 callout_init_mtx(&sc->dc_wdog_ch, &sc->dc_mtx, 0); 2264 2265 /* 2266 * Call MI attach routine. 2267 */ 2268 ether_ifattach(ifp, (caddr_t)eaddr); 2269 2270 /* Hook interrupt last to avoid having to lock softc */ 2271 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | INTR_MPSAFE, 2272 NULL, dc_intr, sc, &sc->dc_intrhand); 2273 2274 if (error) { 2275 device_printf(dev, "couldn't set up irq\n"); 2276 ether_ifdetach(ifp); 2277 goto fail; 2278 } 2279 2280 fail: 2281 if (error) 2282 dc_detach(dev); 2283 return (error); 2284 } 2285 2286 /* 2287 * Shutdown hardware and free up resources. This can be called any 2288 * time after the mutex has been initialized. It is called in both 2289 * the error case in attach and the normal detach case so it needs 2290 * to be careful about only freeing resources that have actually been 2291 * allocated. 2292 */ 2293 static int 2294 dc_detach(device_t dev) 2295 { 2296 struct dc_softc *sc; 2297 struct ifnet *ifp; 2298 struct dc_mediainfo *m; 2299 int i; 2300 2301 sc = device_get_softc(dev); 2302 KASSERT(mtx_initialized(&sc->dc_mtx), ("dc mutex not initialized")); 2303 2304 ifp = sc->dc_ifp; 2305 2306 #ifdef DEVICE_POLLING 2307 if (ifp->if_capenable & IFCAP_POLLING) 2308 ether_poll_deregister(ifp); 2309 #endif 2310 2311 /* These should only be active if attach succeeded */ 2312 if (device_is_attached(dev)) { 2313 DC_LOCK(sc); 2314 dc_stop(sc); 2315 DC_UNLOCK(sc); 2316 callout_drain(&sc->dc_stat_ch); 2317 callout_drain(&sc->dc_wdog_ch); 2318 ether_ifdetach(ifp); 2319 } 2320 if (sc->dc_miibus) 2321 device_delete_child(dev, sc->dc_miibus); 2322 bus_generic_detach(dev); 2323 2324 if (sc->dc_intrhand) 2325 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2326 if (sc->dc_irq) 2327 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2328 if (sc->dc_res) 2329 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2330 2331 if (ifp) 2332 if_free(ifp); 2333 2334 if (sc->dc_cdata.dc_sbuf != NULL) 2335 bus_dmamem_free(sc->dc_stag, sc->dc_cdata.dc_sbuf, sc->dc_smap); 2336 if (sc->dc_ldata != NULL) 2337 bus_dmamem_free(sc->dc_ltag, sc->dc_ldata, sc->dc_lmap); 2338 if (sc->dc_mtag) { 2339 for (i = 0; i < DC_TX_LIST_CNT; i++) 2340 if (sc->dc_cdata.dc_tx_map[i] != NULL) 2341 bus_dmamap_destroy(sc->dc_mtag, 2342 sc->dc_cdata.dc_tx_map[i]); 2343 for (i = 0; i < DC_RX_LIST_CNT; i++) 2344 if (sc->dc_cdata.dc_rx_map[i] != NULL) 2345 bus_dmamap_destroy(sc->dc_mtag, 2346 sc->dc_cdata.dc_rx_map[i]); 2347 bus_dmamap_destroy(sc->dc_mtag, sc->dc_sparemap); 2348 } 2349 if (sc->dc_stag) 2350 bus_dma_tag_destroy(sc->dc_stag); 2351 if (sc->dc_mtag) 2352 bus_dma_tag_destroy(sc->dc_mtag); 2353 if (sc->dc_ltag) 2354 bus_dma_tag_destroy(sc->dc_ltag); 2355 2356 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2357 2358 while (sc->dc_mi != NULL) { 2359 m = sc->dc_mi->dc_next; 2360 free(sc->dc_mi, M_DEVBUF); 2361 sc->dc_mi = m; 2362 } 2363 free(sc->dc_srom, M_DEVBUF); 2364 2365 mtx_destroy(&sc->dc_mtx); 2366 2367 return (0); 2368 } 2369 2370 /* 2371 * Initialize the transmit descriptors. 2372 */ 2373 static int 2374 dc_list_tx_init(struct dc_softc *sc) 2375 { 2376 struct dc_chain_data *cd; 2377 struct dc_list_data *ld; 2378 int i, nexti; 2379 2380 cd = &sc->dc_cdata; 2381 ld = sc->dc_ldata; 2382 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2383 if (i == DC_TX_LIST_CNT - 1) 2384 nexti = 0; 2385 else 2386 nexti = i + 1; 2387 ld->dc_tx_list[i].dc_next = htole32(DC_TXDESC(sc, nexti)); 2388 cd->dc_tx_chain[i] = NULL; 2389 ld->dc_tx_list[i].dc_data = 0; 2390 ld->dc_tx_list[i].dc_ctl = 0; 2391 } 2392 2393 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2394 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2395 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2396 return (0); 2397 } 2398 2399 2400 /* 2401 * Initialize the RX descriptors and allocate mbufs for them. Note that 2402 * we arrange the descriptors in a closed ring, so that the last descriptor 2403 * points back to the first. 2404 */ 2405 static int 2406 dc_list_rx_init(struct dc_softc *sc) 2407 { 2408 struct dc_chain_data *cd; 2409 struct dc_list_data *ld; 2410 int i, nexti; 2411 2412 cd = &sc->dc_cdata; 2413 ld = sc->dc_ldata; 2414 2415 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2416 if (dc_newbuf(sc, i, 1) != 0) 2417 return (ENOBUFS); 2418 if (i == DC_RX_LIST_CNT - 1) 2419 nexti = 0; 2420 else 2421 nexti = i + 1; 2422 ld->dc_rx_list[i].dc_next = htole32(DC_RXDESC(sc, nexti)); 2423 } 2424 2425 cd->dc_rx_prod = 0; 2426 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2427 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2428 return (0); 2429 } 2430 2431 /* 2432 * Initialize an RX descriptor and attach an MBUF cluster. 2433 */ 2434 static int 2435 dc_newbuf(struct dc_softc *sc, int i, int alloc) 2436 { 2437 struct mbuf *m_new; 2438 bus_dmamap_t tmp; 2439 bus_dma_segment_t segs[1]; 2440 int error, nseg; 2441 2442 if (alloc) { 2443 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2444 if (m_new == NULL) 2445 return (ENOBUFS); 2446 } else { 2447 m_new = sc->dc_cdata.dc_rx_chain[i]; 2448 m_new->m_data = m_new->m_ext.ext_buf; 2449 } 2450 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2451 m_adj(m_new, sizeof(u_int64_t)); 2452 2453 /* 2454 * If this is a PNIC chip, zero the buffer. This is part 2455 * of the workaround for the receive bug in the 82c168 and 2456 * 82c169 chips. 2457 */ 2458 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2459 bzero(mtod(m_new, char *), m_new->m_len); 2460 2461 /* No need to remap the mbuf if we're reusing it. */ 2462 if (alloc) { 2463 error = bus_dmamap_load_mbuf_sg(sc->dc_mtag, sc->dc_sparemap, 2464 m_new, segs, &nseg, 0); 2465 if (error) { 2466 m_freem(m_new); 2467 return (error); 2468 } 2469 KASSERT(nseg == 1, 2470 ("%s: wrong number of segments (%d)", __func__, nseg)); 2471 sc->dc_ldata->dc_rx_list[i].dc_data = htole32(segs->ds_addr); 2472 bus_dmamap_unload(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i]); 2473 tmp = sc->dc_cdata.dc_rx_map[i]; 2474 sc->dc_cdata.dc_rx_map[i] = sc->dc_sparemap; 2475 sc->dc_sparemap = tmp; 2476 sc->dc_cdata.dc_rx_chain[i] = m_new; 2477 } 2478 2479 sc->dc_ldata->dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN); 2480 sc->dc_ldata->dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN); 2481 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i], 2482 BUS_DMASYNC_PREREAD); 2483 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2484 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2485 return (0); 2486 } 2487 2488 /* 2489 * Grrrrr. 2490 * The PNIC chip has a terrible bug in it that manifests itself during 2491 * periods of heavy activity. The exact mode of failure if difficult to 2492 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2493 * will happen on slow machines. The bug is that sometimes instead of 2494 * uploading one complete frame during reception, it uploads what looks 2495 * like the entire contents of its FIFO memory. The frame we want is at 2496 * the end of the whole mess, but we never know exactly how much data has 2497 * been uploaded, so salvaging the frame is hard. 2498 * 2499 * There is only one way to do it reliably, and it's disgusting. 2500 * Here's what we know: 2501 * 2502 * - We know there will always be somewhere between one and three extra 2503 * descriptors uploaded. 2504 * 2505 * - We know the desired received frame will always be at the end of the 2506 * total data upload. 2507 * 2508 * - We know the size of the desired received frame because it will be 2509 * provided in the length field of the status word in the last descriptor. 2510 * 2511 * Here's what we do: 2512 * 2513 * - When we allocate buffers for the receive ring, we bzero() them. 2514 * This means that we know that the buffer contents should be all 2515 * zeros, except for data uploaded by the chip. 2516 * 2517 * - We also force the PNIC chip to upload frames that include the 2518 * ethernet CRC at the end. 2519 * 2520 * - We gather all of the bogus frame data into a single buffer. 2521 * 2522 * - We then position a pointer at the end of this buffer and scan 2523 * backwards until we encounter the first non-zero byte of data. 2524 * This is the end of the received frame. We know we will encounter 2525 * some data at the end of the frame because the CRC will always be 2526 * there, so even if the sender transmits a packet of all zeros, 2527 * we won't be fooled. 2528 * 2529 * - We know the size of the actual received frame, so we subtract 2530 * that value from the current pointer location. This brings us 2531 * to the start of the actual received packet. 2532 * 2533 * - We copy this into an mbuf and pass it on, along with the actual 2534 * frame length. 2535 * 2536 * The performance hit is tremendous, but it beats dropping frames all 2537 * the time. 2538 */ 2539 2540 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG | DC_RXSTAT_LASTFRAG) 2541 static void 2542 dc_pnic_rx_bug_war(struct dc_softc *sc, int idx) 2543 { 2544 struct dc_desc *cur_rx; 2545 struct dc_desc *c = NULL; 2546 struct mbuf *m = NULL; 2547 unsigned char *ptr; 2548 int i, total_len; 2549 u_int32_t rxstat = 0; 2550 2551 i = sc->dc_pnic_rx_bug_save; 2552 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2553 ptr = sc->dc_pnic_rx_buf; 2554 bzero(ptr, DC_RXLEN * 5); 2555 2556 /* Copy all the bytes from the bogus buffers. */ 2557 while (1) { 2558 c = &sc->dc_ldata->dc_rx_list[i]; 2559 rxstat = le32toh(c->dc_status); 2560 m = sc->dc_cdata.dc_rx_chain[i]; 2561 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2562 ptr += DC_RXLEN; 2563 /* If this is the last buffer, break out. */ 2564 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2565 break; 2566 dc_newbuf(sc, i, 0); 2567 DC_INC(i, DC_RX_LIST_CNT); 2568 } 2569 2570 /* Find the length of the actual receive frame. */ 2571 total_len = DC_RXBYTES(rxstat); 2572 2573 /* Scan backwards until we hit a non-zero byte. */ 2574 while (*ptr == 0x00) 2575 ptr--; 2576 2577 /* Round off. */ 2578 if ((uintptr_t)(ptr) & 0x3) 2579 ptr -= 1; 2580 2581 /* Now find the start of the frame. */ 2582 ptr -= total_len; 2583 if (ptr < sc->dc_pnic_rx_buf) 2584 ptr = sc->dc_pnic_rx_buf; 2585 2586 /* 2587 * Now copy the salvaged frame to the last mbuf and fake up 2588 * the status word to make it look like a successful 2589 * frame reception. 2590 */ 2591 dc_newbuf(sc, i, 0); 2592 bcopy(ptr, mtod(m, char *), total_len); 2593 cur_rx->dc_status = htole32(rxstat | DC_RXSTAT_FIRSTFRAG); 2594 } 2595 2596 /* 2597 * This routine searches the RX ring for dirty descriptors in the 2598 * event that the rxeof routine falls out of sync with the chip's 2599 * current descriptor pointer. This may happen sometimes as a result 2600 * of a "no RX buffer available" condition that happens when the chip 2601 * consumes all of the RX buffers before the driver has a chance to 2602 * process the RX ring. This routine may need to be called more than 2603 * once to bring the driver back in sync with the chip, however we 2604 * should still be getting RX DONE interrupts to drive the search 2605 * for new packets in the RX ring, so we should catch up eventually. 2606 */ 2607 static int 2608 dc_rx_resync(struct dc_softc *sc) 2609 { 2610 struct dc_desc *cur_rx; 2611 int i, pos; 2612 2613 pos = sc->dc_cdata.dc_rx_prod; 2614 2615 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2616 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2617 if (!(le32toh(cur_rx->dc_status) & DC_RXSTAT_OWN)) 2618 break; 2619 DC_INC(pos, DC_RX_LIST_CNT); 2620 } 2621 2622 /* If the ring really is empty, then just return. */ 2623 if (i == DC_RX_LIST_CNT) 2624 return (0); 2625 2626 /* We've fallen behing the chip: catch it. */ 2627 sc->dc_cdata.dc_rx_prod = pos; 2628 2629 return (EAGAIN); 2630 } 2631 2632 /* 2633 * A frame has been uploaded: pass the resulting mbuf chain up to 2634 * the higher level protocols. 2635 */ 2636 static void 2637 dc_rxeof(struct dc_softc *sc) 2638 { 2639 struct mbuf *m, *m0; 2640 struct ifnet *ifp; 2641 struct dc_desc *cur_rx; 2642 int i, total_len = 0; 2643 u_int32_t rxstat; 2644 2645 DC_LOCK_ASSERT(sc); 2646 2647 ifp = sc->dc_ifp; 2648 i = sc->dc_cdata.dc_rx_prod; 2649 2650 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD); 2651 while (!(le32toh(sc->dc_ldata->dc_rx_list[i].dc_status) & 2652 DC_RXSTAT_OWN)) { 2653 #ifdef DEVICE_POLLING 2654 if (ifp->if_capenable & IFCAP_POLLING) { 2655 if (sc->rxcycles <= 0) 2656 break; 2657 sc->rxcycles--; 2658 } 2659 #endif 2660 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2661 rxstat = le32toh(cur_rx->dc_status); 2662 m = sc->dc_cdata.dc_rx_chain[i]; 2663 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i], 2664 BUS_DMASYNC_POSTREAD); 2665 total_len = DC_RXBYTES(rxstat); 2666 2667 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2668 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2669 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2670 sc->dc_pnic_rx_bug_save = i; 2671 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2672 DC_INC(i, DC_RX_LIST_CNT); 2673 continue; 2674 } 2675 dc_pnic_rx_bug_war(sc, i); 2676 rxstat = le32toh(cur_rx->dc_status); 2677 total_len = DC_RXBYTES(rxstat); 2678 } 2679 } 2680 2681 /* 2682 * If an error occurs, update stats, clear the 2683 * status word and leave the mbuf cluster in place: 2684 * it should simply get re-used next time this descriptor 2685 * comes up in the ring. However, don't report long 2686 * frames as errors since they could be vlans. 2687 */ 2688 if ((rxstat & DC_RXSTAT_RXERR)) { 2689 if (!(rxstat & DC_RXSTAT_GIANT) || 2690 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2691 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2692 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2693 ifp->if_ierrors++; 2694 if (rxstat & DC_RXSTAT_COLLSEEN) 2695 ifp->if_collisions++; 2696 dc_newbuf(sc, i, 0); 2697 if (rxstat & DC_RXSTAT_CRCERR) { 2698 DC_INC(i, DC_RX_LIST_CNT); 2699 continue; 2700 } else { 2701 dc_init_locked(sc); 2702 return; 2703 } 2704 } 2705 } 2706 2707 /* No errors; receive the packet. */ 2708 total_len -= ETHER_CRC_LEN; 2709 #ifdef __NO_STRICT_ALIGNMENT 2710 /* 2711 * On architectures without alignment problems we try to 2712 * allocate a new buffer for the receive ring, and pass up 2713 * the one where the packet is already, saving the expensive 2714 * copy done in m_devget(). 2715 * If we are on an architecture with alignment problems, or 2716 * if the allocation fails, then use m_devget and leave the 2717 * existing buffer in the receive ring. 2718 */ 2719 if (dc_newbuf(sc, i, 1) == 0) { 2720 m->m_pkthdr.rcvif = ifp; 2721 m->m_pkthdr.len = m->m_len = total_len; 2722 DC_INC(i, DC_RX_LIST_CNT); 2723 } else 2724 #endif 2725 { 2726 m0 = m_devget(mtod(m, char *), total_len, 2727 ETHER_ALIGN, ifp, NULL); 2728 dc_newbuf(sc, i, 0); 2729 DC_INC(i, DC_RX_LIST_CNT); 2730 if (m0 == NULL) { 2731 ifp->if_ierrors++; 2732 continue; 2733 } 2734 m = m0; 2735 } 2736 2737 ifp->if_ipackets++; 2738 DC_UNLOCK(sc); 2739 (*ifp->if_input)(ifp, m); 2740 DC_LOCK(sc); 2741 } 2742 2743 sc->dc_cdata.dc_rx_prod = i; 2744 } 2745 2746 /* 2747 * A frame was downloaded to the chip. It's safe for us to clean up 2748 * the list buffers. 2749 */ 2750 static void 2751 dc_txeof(struct dc_softc *sc) 2752 { 2753 struct dc_desc *cur_tx = NULL; 2754 struct ifnet *ifp; 2755 int idx; 2756 u_int32_t ctl, txstat; 2757 2758 ifp = sc->dc_ifp; 2759 2760 /* 2761 * Go through our tx list and free mbufs for those 2762 * frames that have been transmitted. 2763 */ 2764 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD); 2765 idx = sc->dc_cdata.dc_tx_cons; 2766 while (idx != sc->dc_cdata.dc_tx_prod) { 2767 2768 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2769 txstat = le32toh(cur_tx->dc_status); 2770 ctl = le32toh(cur_tx->dc_ctl); 2771 2772 if (txstat & DC_TXSTAT_OWN) 2773 break; 2774 2775 if (!(ctl & DC_TXCTL_LASTFRAG) || ctl & DC_TXCTL_SETUP) { 2776 if (ctl & DC_TXCTL_SETUP) { 2777 /* 2778 * Yes, the PNIC is so brain damaged 2779 * that it will sometimes generate a TX 2780 * underrun error while DMAing the RX 2781 * filter setup frame. If we detect this, 2782 * we have to send the setup frame again, 2783 * or else the filter won't be programmed 2784 * correctly. 2785 */ 2786 if (DC_IS_PNIC(sc)) { 2787 if (txstat & DC_TXSTAT_ERRSUM) 2788 dc_setfilt(sc); 2789 } 2790 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2791 } 2792 sc->dc_cdata.dc_tx_cnt--; 2793 DC_INC(idx, DC_TX_LIST_CNT); 2794 continue; 2795 } 2796 2797 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) { 2798 /* 2799 * XXX: Why does my Xircom taunt me so? 2800 * For some reason it likes setting the CARRLOST flag 2801 * even when the carrier is there. wtf?!? 2802 * Who knows, but Conexant chips have the 2803 * same problem. Maybe they took lessons 2804 * from Xircom. 2805 */ 2806 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2807 sc->dc_pmode == DC_PMODE_MII && 2808 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 2809 DC_TXSTAT_NOCARRIER))) 2810 txstat &= ~DC_TXSTAT_ERRSUM; 2811 } else { 2812 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2813 sc->dc_pmode == DC_PMODE_MII && 2814 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 2815 DC_TXSTAT_NOCARRIER | DC_TXSTAT_CARRLOST))) 2816 txstat &= ~DC_TXSTAT_ERRSUM; 2817 } 2818 2819 if (txstat & DC_TXSTAT_ERRSUM) { 2820 ifp->if_oerrors++; 2821 if (txstat & DC_TXSTAT_EXCESSCOLL) 2822 ifp->if_collisions++; 2823 if (txstat & DC_TXSTAT_LATECOLL) 2824 ifp->if_collisions++; 2825 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2826 dc_init_locked(sc); 2827 return; 2828 } 2829 } 2830 2831 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2832 2833 ifp->if_opackets++; 2834 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2835 bus_dmamap_sync(sc->dc_mtag, 2836 sc->dc_cdata.dc_tx_map[idx], 2837 BUS_DMASYNC_POSTWRITE); 2838 bus_dmamap_unload(sc->dc_mtag, 2839 sc->dc_cdata.dc_tx_map[idx]); 2840 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2841 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2842 } 2843 2844 sc->dc_cdata.dc_tx_cnt--; 2845 DC_INC(idx, DC_TX_LIST_CNT); 2846 } 2847 sc->dc_cdata.dc_tx_cons = idx; 2848 2849 if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt > DC_TX_LIST_RSVD) 2850 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2851 2852 if (sc->dc_cdata.dc_tx_cnt == 0) 2853 sc->dc_wdog_timer = 0; 2854 } 2855 2856 static void 2857 dc_tick(void *xsc) 2858 { 2859 struct dc_softc *sc; 2860 struct mii_data *mii; 2861 struct ifnet *ifp; 2862 u_int32_t r; 2863 2864 sc = xsc; 2865 DC_LOCK_ASSERT(sc); 2866 ifp = sc->dc_ifp; 2867 mii = device_get_softc(sc->dc_miibus); 2868 2869 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2870 if (sc->dc_flags & DC_21143_NWAY) { 2871 r = CSR_READ_4(sc, DC_10BTSTAT); 2872 if (IFM_SUBTYPE(mii->mii_media_active) == 2873 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2874 sc->dc_link = 0; 2875 mii_mediachg(mii); 2876 } 2877 if (IFM_SUBTYPE(mii->mii_media_active) == 2878 IFM_10_T && (r & DC_TSTAT_LS10)) { 2879 sc->dc_link = 0; 2880 mii_mediachg(mii); 2881 } 2882 if (sc->dc_link == 0) 2883 mii_tick(mii); 2884 } else { 2885 /* 2886 * For NICs which never report DC_RXSTATE_WAIT, we 2887 * have to bite the bullet... 2888 */ 2889 if ((DC_HAS_BROKEN_RXSTATE(sc) || (CSR_READ_4(sc, 2890 DC_ISR) & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT) && 2891 sc->dc_cdata.dc_tx_cnt == 0) { 2892 mii_tick(mii); 2893 if (!(mii->mii_media_status & IFM_ACTIVE)) 2894 sc->dc_link = 0; 2895 } 2896 } 2897 } else 2898 mii_tick(mii); 2899 2900 /* 2901 * When the init routine completes, we expect to be able to send 2902 * packets right away, and in fact the network code will send a 2903 * gratuitous ARP the moment the init routine marks the interface 2904 * as running. However, even though the MAC may have been initialized, 2905 * there may be a delay of a few seconds before the PHY completes 2906 * autonegotiation and the link is brought up. Any transmissions 2907 * made during that delay will be lost. Dealing with this is tricky: 2908 * we can't just pause in the init routine while waiting for the 2909 * PHY to come ready since that would bring the whole system to 2910 * a screeching halt for several seconds. 2911 * 2912 * What we do here is prevent the TX start routine from sending 2913 * any packets until a link has been established. After the 2914 * interface has been initialized, the tick routine will poll 2915 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2916 * that time, packets will stay in the send queue, and once the 2917 * link comes up, they will be flushed out to the wire. 2918 */ 2919 if (!sc->dc_link && mii->mii_media_status & IFM_ACTIVE && 2920 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2921 sc->dc_link++; 2922 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2923 dc_start_locked(ifp); 2924 } 2925 2926 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 2927 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 2928 else 2929 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 2930 } 2931 2932 /* 2933 * A transmit underrun has occurred. Back off the transmit threshold, 2934 * or switch to store and forward mode if we have to. 2935 */ 2936 static void 2937 dc_tx_underrun(struct dc_softc *sc) 2938 { 2939 u_int32_t isr; 2940 int i; 2941 2942 if (DC_IS_DAVICOM(sc)) 2943 dc_init_locked(sc); 2944 2945 if (DC_IS_INTEL(sc)) { 2946 /* 2947 * The real 21143 requires that the transmitter be idle 2948 * in order to change the transmit threshold or store 2949 * and forward state. 2950 */ 2951 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2952 2953 for (i = 0; i < DC_TIMEOUT; i++) { 2954 isr = CSR_READ_4(sc, DC_ISR); 2955 if (isr & DC_ISR_TX_IDLE) 2956 break; 2957 DELAY(10); 2958 } 2959 if (i == DC_TIMEOUT) { 2960 device_printf(sc->dc_dev, 2961 "%s: failed to force tx to idle state\n", 2962 __func__); 2963 dc_init_locked(sc); 2964 } 2965 } 2966 2967 device_printf(sc->dc_dev, "TX underrun -- "); 2968 sc->dc_txthresh += DC_TXTHRESH_INC; 2969 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 2970 printf("using store and forward mode\n"); 2971 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2972 } else { 2973 printf("increasing TX threshold\n"); 2974 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 2975 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2976 } 2977 2978 if (DC_IS_INTEL(sc)) 2979 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2980 } 2981 2982 #ifdef DEVICE_POLLING 2983 static poll_handler_t dc_poll; 2984 2985 static void 2986 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2987 { 2988 struct dc_softc *sc = ifp->if_softc; 2989 2990 DC_LOCK(sc); 2991 2992 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 2993 DC_UNLOCK(sc); 2994 return; 2995 } 2996 2997 sc->rxcycles = count; 2998 dc_rxeof(sc); 2999 dc_txeof(sc); 3000 if (!IFQ_IS_EMPTY(&ifp->if_snd) && 3001 !(ifp->if_drv_flags & IFF_DRV_OACTIVE)) 3002 dc_start_locked(ifp); 3003 3004 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 3005 u_int32_t status; 3006 3007 status = CSR_READ_4(sc, DC_ISR); 3008 status &= (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF | 3009 DC_ISR_TX_NOBUF | DC_ISR_TX_IDLE | DC_ISR_TX_UNDERRUN | 3010 DC_ISR_BUS_ERR); 3011 if (!status) { 3012 DC_UNLOCK(sc); 3013 return; 3014 } 3015 /* ack what we have */ 3016 CSR_WRITE_4(sc, DC_ISR, status); 3017 3018 if (status & (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF)) { 3019 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 3020 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 3021 3022 if (dc_rx_resync(sc)) 3023 dc_rxeof(sc); 3024 } 3025 /* restart transmit unit if necessary */ 3026 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 3027 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3028 3029 if (status & DC_ISR_TX_UNDERRUN) 3030 dc_tx_underrun(sc); 3031 3032 if (status & DC_ISR_BUS_ERR) { 3033 if_printf(ifp, "%s: bus error\n", __func__); 3034 dc_reset(sc); 3035 dc_init_locked(sc); 3036 } 3037 } 3038 DC_UNLOCK(sc); 3039 } 3040 #endif /* DEVICE_POLLING */ 3041 3042 static void 3043 dc_intr(void *arg) 3044 { 3045 struct dc_softc *sc; 3046 struct ifnet *ifp; 3047 u_int32_t status; 3048 3049 sc = arg; 3050 3051 if (sc->suspended) 3052 return; 3053 3054 if ((CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) 3055 return; 3056 3057 DC_LOCK(sc); 3058 ifp = sc->dc_ifp; 3059 #ifdef DEVICE_POLLING 3060 if (ifp->if_capenable & IFCAP_POLLING) { 3061 DC_UNLOCK(sc); 3062 return; 3063 } 3064 #endif 3065 3066 /* Suppress unwanted interrupts */ 3067 if (!(ifp->if_flags & IFF_UP)) { 3068 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 3069 dc_stop(sc); 3070 DC_UNLOCK(sc); 3071 return; 3072 } 3073 3074 /* Disable interrupts. */ 3075 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3076 3077 while (((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) && 3078 status != 0xFFFFFFFF && 3079 (ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3080 3081 CSR_WRITE_4(sc, DC_ISR, status); 3082 3083 if (status & DC_ISR_RX_OK) { 3084 int curpkts; 3085 curpkts = ifp->if_ipackets; 3086 dc_rxeof(sc); 3087 if (curpkts == ifp->if_ipackets) { 3088 while (dc_rx_resync(sc)) 3089 dc_rxeof(sc); 3090 } 3091 } 3092 3093 if (status & (DC_ISR_TX_OK | DC_ISR_TX_NOBUF)) 3094 dc_txeof(sc); 3095 3096 if (status & DC_ISR_TX_IDLE) { 3097 dc_txeof(sc); 3098 if (sc->dc_cdata.dc_tx_cnt) { 3099 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3100 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3101 } 3102 } 3103 3104 if (status & DC_ISR_TX_UNDERRUN) 3105 dc_tx_underrun(sc); 3106 3107 if ((status & DC_ISR_RX_WATDOGTIMEO) 3108 || (status & DC_ISR_RX_NOBUF)) { 3109 int curpkts; 3110 curpkts = ifp->if_ipackets; 3111 dc_rxeof(sc); 3112 if (curpkts == ifp->if_ipackets) { 3113 while (dc_rx_resync(sc)) 3114 dc_rxeof(sc); 3115 } 3116 } 3117 3118 if (status & DC_ISR_BUS_ERR) { 3119 dc_reset(sc); 3120 dc_init_locked(sc); 3121 } 3122 } 3123 3124 /* Re-enable interrupts. */ 3125 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3126 3127 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3128 dc_start_locked(ifp); 3129 3130 DC_UNLOCK(sc); 3131 } 3132 3133 /* 3134 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 3135 * pointers to the fragment pointers. 3136 */ 3137 static int 3138 dc_encap(struct dc_softc *sc, struct mbuf **m_head) 3139 { 3140 bus_dma_segment_t segs[DC_MAXFRAGS]; 3141 struct dc_desc *f; 3142 struct mbuf *m; 3143 int cur, defragged, error, first, frag, i, idx, nseg; 3144 3145 /* 3146 * If there's no way we can send any packets, return now. 3147 */ 3148 if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt <= DC_TX_LIST_RSVD) 3149 return (ENOBUFS); 3150 3151 m = NULL; 3152 defragged = 0; 3153 if (sc->dc_flags & DC_TX_COALESCE && 3154 ((*m_head)->m_next != NULL || sc->dc_flags & DC_TX_ALIGN)) { 3155 m = m_defrag(*m_head, M_DONTWAIT); 3156 defragged = 1; 3157 } else { 3158 /* 3159 * Count the number of frags in this chain to see if we 3160 * need to m_collapse. Since the descriptor list is shared 3161 * by all packets, we'll m_collapse long chains so that they 3162 * do not use up the entire list, even if they would fit. 3163 */ 3164 i = 0; 3165 for (m = *m_head; m != NULL; m = m->m_next) 3166 i++; 3167 if (i > DC_TX_LIST_CNT / 4 || 3168 DC_TX_LIST_CNT - i + sc->dc_cdata.dc_tx_cnt <= 3169 DC_TX_LIST_RSVD) { 3170 m = m_collapse(*m_head, M_DONTWAIT, DC_MAXFRAGS); 3171 defragged = 1; 3172 } 3173 } 3174 if (defragged != 0) { 3175 if (m == NULL) { 3176 m_freem(*m_head); 3177 *m_head = NULL; 3178 return (ENOBUFS); 3179 } 3180 *m_head = m; 3181 } 3182 3183 idx = sc->dc_cdata.dc_tx_prod; 3184 error = bus_dmamap_load_mbuf_sg(sc->dc_mtag, 3185 sc->dc_cdata.dc_tx_map[idx], *m_head, segs, &nseg, 0); 3186 if (error == EFBIG) { 3187 if (defragged != 0 || (m = m_collapse(*m_head, M_DONTWAIT, 3188 DC_MAXFRAGS)) == NULL) { 3189 m_freem(*m_head); 3190 *m_head = NULL; 3191 return (defragged != 0 ? error : ENOBUFS); 3192 } 3193 *m_head = m; 3194 error = bus_dmamap_load_mbuf_sg(sc->dc_mtag, 3195 sc->dc_cdata.dc_tx_map[idx], *m_head, segs, &nseg, 0); 3196 if (error != 0) { 3197 m_freem(*m_head); 3198 *m_head = NULL; 3199 return (error); 3200 } 3201 } else if (error != 0) 3202 return (error); 3203 KASSERT(nseg <= DC_MAXFRAGS, 3204 ("%s: wrong number of segments (%d)", __func__, nseg)); 3205 if (nseg == 0) { 3206 m_freem(*m_head); 3207 *m_head = NULL; 3208 return (EIO); 3209 } 3210 3211 first = cur = frag = sc->dc_cdata.dc_tx_prod; 3212 for (i = 0; i < nseg; i++) { 3213 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) && 3214 (frag == (DC_TX_LIST_CNT - 1)) && 3215 (first != sc->dc_cdata.dc_tx_first)) { 3216 bus_dmamap_unload(sc->dc_mtag, 3217 sc->dc_cdata.dc_tx_map[first]); 3218 m_freem(*m_head); 3219 *m_head = NULL; 3220 return (ENOBUFS); 3221 } 3222 3223 f = &sc->dc_ldata->dc_tx_list[frag]; 3224 f->dc_ctl = htole32(DC_TXCTL_TLINK | segs[i].ds_len); 3225 if (i == 0) { 3226 f->dc_status = 0; 3227 f->dc_ctl |= htole32(DC_TXCTL_FIRSTFRAG); 3228 } else 3229 f->dc_status = htole32(DC_TXSTAT_OWN); 3230 f->dc_data = htole32(segs[i].ds_addr); 3231 cur = frag; 3232 DC_INC(frag, DC_TX_LIST_CNT); 3233 } 3234 3235 sc->dc_cdata.dc_tx_prod = frag; 3236 sc->dc_cdata.dc_tx_cnt += nseg; 3237 sc->dc_cdata.dc_tx_chain[cur] = *m_head; 3238 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_LASTFRAG); 3239 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 3240 sc->dc_ldata->dc_tx_list[first].dc_ctl |= 3241 htole32(DC_TXCTL_FINT); 3242 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 3243 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3244 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 3245 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3246 sc->dc_ldata->dc_tx_list[first].dc_status = htole32(DC_TXSTAT_OWN); 3247 3248 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx], 3249 BUS_DMASYNC_PREWRITE); 3250 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 3251 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3252 return (0); 3253 } 3254 3255 static void 3256 dc_start(struct ifnet *ifp) 3257 { 3258 struct dc_softc *sc; 3259 3260 sc = ifp->if_softc; 3261 DC_LOCK(sc); 3262 dc_start_locked(ifp); 3263 DC_UNLOCK(sc); 3264 } 3265 3266 /* 3267 * Main transmit routine 3268 * To avoid having to do mbuf copies, we put pointers to the mbuf data 3269 * regions directly in the transmit lists. We also save a copy of the 3270 * pointers since the transmit list fragment pointers are physical 3271 * addresses. 3272 */ 3273 static void 3274 dc_start_locked(struct ifnet *ifp) 3275 { 3276 struct dc_softc *sc; 3277 struct mbuf *m_head = NULL; 3278 unsigned int queued = 0; 3279 int idx; 3280 3281 sc = ifp->if_softc; 3282 3283 DC_LOCK_ASSERT(sc); 3284 3285 if (!sc->dc_link && ifp->if_snd.ifq_len < 10) 3286 return; 3287 3288 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 3289 return; 3290 3291 idx = sc->dc_cdata.dc_tx_first = sc->dc_cdata.dc_tx_prod; 3292 3293 while (sc->dc_cdata.dc_tx_chain[idx] == NULL) { 3294 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 3295 if (m_head == NULL) 3296 break; 3297 3298 if (dc_encap(sc, &m_head)) { 3299 if (m_head == NULL) 3300 break; 3301 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3302 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3303 break; 3304 } 3305 idx = sc->dc_cdata.dc_tx_prod; 3306 3307 queued++; 3308 /* 3309 * If there's a BPF listener, bounce a copy of this frame 3310 * to him. 3311 */ 3312 BPF_MTAP(ifp, m_head); 3313 3314 if (sc->dc_flags & DC_TX_ONE) { 3315 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3316 break; 3317 } 3318 } 3319 3320 if (queued > 0) { 3321 /* Transmit */ 3322 if (!(sc->dc_flags & DC_TX_POLL)) 3323 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3324 3325 /* 3326 * Set a timeout in case the chip goes out to lunch. 3327 */ 3328 sc->dc_wdog_timer = 5; 3329 } 3330 } 3331 3332 static void 3333 dc_init(void *xsc) 3334 { 3335 struct dc_softc *sc = xsc; 3336 3337 DC_LOCK(sc); 3338 dc_init_locked(sc); 3339 DC_UNLOCK(sc); 3340 } 3341 3342 static void 3343 dc_init_locked(struct dc_softc *sc) 3344 { 3345 struct ifnet *ifp = sc->dc_ifp; 3346 struct mii_data *mii; 3347 3348 DC_LOCK_ASSERT(sc); 3349 3350 mii = device_get_softc(sc->dc_miibus); 3351 3352 /* 3353 * Cancel pending I/O and free all RX/TX buffers. 3354 */ 3355 dc_stop(sc); 3356 dc_reset(sc); 3357 3358 /* 3359 * Set cache alignment and burst length. 3360 */ 3361 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 3362 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3363 else 3364 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME | DC_BUSCTL_MRLE); 3365 /* 3366 * Evenly share the bus between receive and transmit process. 3367 */ 3368 if (DC_IS_INTEL(sc)) 3369 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3370 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3371 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3372 } else { 3373 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3374 } 3375 if (sc->dc_flags & DC_TX_POLL) 3376 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3377 switch(sc->dc_cachesize) { 3378 case 32: 3379 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3380 break; 3381 case 16: 3382 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3383 break; 3384 case 8: 3385 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3386 break; 3387 case 0: 3388 default: 3389 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3390 break; 3391 } 3392 3393 if (sc->dc_flags & DC_TX_STORENFWD) 3394 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3395 else { 3396 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3397 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3398 } else { 3399 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3400 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3401 } 3402 } 3403 3404 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3405 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3406 3407 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3408 /* 3409 * The app notes for the 98713 and 98715A say that 3410 * in order to have the chips operate properly, a magic 3411 * number must be written to CSR16. Macronix does not 3412 * document the meaning of these bits so there's no way 3413 * to know exactly what they do. The 98713 has a magic 3414 * number all its own; the rest all use a different one. 3415 */ 3416 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3417 if (sc->dc_type == DC_TYPE_98713) 3418 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3419 else 3420 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3421 } 3422 3423 if (DC_IS_XIRCOM(sc)) { 3424 /* 3425 * setup General Purpose Port mode and data so the tulip 3426 * can talk to the MII. 3427 */ 3428 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3429 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3430 DELAY(10); 3431 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3432 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3433 DELAY(10); 3434 } 3435 3436 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3437 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3438 3439 /* Init circular RX list. */ 3440 if (dc_list_rx_init(sc) == ENOBUFS) { 3441 device_printf(sc->dc_dev, 3442 "initialization failed: no memory for rx buffers\n"); 3443 dc_stop(sc); 3444 return; 3445 } 3446 3447 /* 3448 * Init TX descriptors. 3449 */ 3450 dc_list_tx_init(sc); 3451 3452 /* 3453 * Load the address of the RX list. 3454 */ 3455 CSR_WRITE_4(sc, DC_RXADDR, DC_RXDESC(sc, 0)); 3456 CSR_WRITE_4(sc, DC_TXADDR, DC_TXDESC(sc, 0)); 3457 3458 /* 3459 * Enable interrupts. 3460 */ 3461 #ifdef DEVICE_POLLING 3462 /* 3463 * ... but only if we are not polling, and make sure they are off in 3464 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3465 * after a reset. 3466 */ 3467 if (ifp->if_capenable & IFCAP_POLLING) 3468 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3469 else 3470 #endif 3471 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3472 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3473 3474 /* Enable transmitter. */ 3475 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3476 3477 /* 3478 * If this is an Intel 21143 and we're not using the 3479 * MII port, program the LED control pins so we get 3480 * link and activity indications. 3481 */ 3482 if (sc->dc_flags & DC_TULIP_LEDS) { 3483 CSR_WRITE_4(sc, DC_WATCHDOG, 3484 DC_WDOG_CTLWREN | DC_WDOG_LINK | DC_WDOG_ACTIVITY); 3485 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3486 } 3487 3488 /* 3489 * Load the RX/multicast filter. We do this sort of late 3490 * because the filter programming scheme on the 21143 and 3491 * some clones requires DMAing a setup frame via the TX 3492 * engine, and we need the transmitter enabled for that. 3493 */ 3494 dc_setfilt(sc); 3495 3496 /* Enable receiver. */ 3497 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3498 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3499 3500 mii_mediachg(mii); 3501 dc_setcfg(sc, sc->dc_if_media); 3502 3503 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3504 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3505 3506 /* Don't start the ticker if this is a homePNA link. */ 3507 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) 3508 sc->dc_link = 1; 3509 else { 3510 if (sc->dc_flags & DC_21143_NWAY) 3511 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3512 else 3513 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3514 } 3515 3516 sc->dc_wdog_timer = 0; 3517 callout_reset(&sc->dc_wdog_ch, hz, dc_watchdog, sc); 3518 } 3519 3520 /* 3521 * Set media options. 3522 */ 3523 static int 3524 dc_ifmedia_upd(struct ifnet *ifp) 3525 { 3526 struct dc_softc *sc; 3527 struct mii_data *mii; 3528 struct ifmedia *ifm; 3529 3530 sc = ifp->if_softc; 3531 mii = device_get_softc(sc->dc_miibus); 3532 DC_LOCK(sc); 3533 mii_mediachg(mii); 3534 ifm = &mii->mii_media; 3535 3536 if (DC_IS_DAVICOM(sc) && 3537 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) 3538 dc_setcfg(sc, ifm->ifm_media); 3539 else 3540 sc->dc_link = 0; 3541 DC_UNLOCK(sc); 3542 3543 return (0); 3544 } 3545 3546 /* 3547 * Report current media status. 3548 */ 3549 static void 3550 dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3551 { 3552 struct dc_softc *sc; 3553 struct mii_data *mii; 3554 struct ifmedia *ifm; 3555 3556 sc = ifp->if_softc; 3557 mii = device_get_softc(sc->dc_miibus); 3558 DC_LOCK(sc); 3559 mii_pollstat(mii); 3560 ifm = &mii->mii_media; 3561 if (DC_IS_DAVICOM(sc)) { 3562 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 3563 ifmr->ifm_active = ifm->ifm_media; 3564 ifmr->ifm_status = 0; 3565 DC_UNLOCK(sc); 3566 return; 3567 } 3568 } 3569 ifmr->ifm_active = mii->mii_media_active; 3570 ifmr->ifm_status = mii->mii_media_status; 3571 DC_UNLOCK(sc); 3572 } 3573 3574 static int 3575 dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3576 { 3577 struct dc_softc *sc = ifp->if_softc; 3578 struct ifreq *ifr = (struct ifreq *)data; 3579 struct mii_data *mii; 3580 int error = 0; 3581 3582 switch (command) { 3583 case SIOCSIFFLAGS: 3584 DC_LOCK(sc); 3585 if (ifp->if_flags & IFF_UP) { 3586 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) & 3587 (IFF_PROMISC | IFF_ALLMULTI); 3588 3589 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3590 if (need_setfilt) 3591 dc_setfilt(sc); 3592 } else { 3593 sc->dc_txthresh = 0; 3594 dc_init_locked(sc); 3595 } 3596 } else { 3597 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3598 dc_stop(sc); 3599 } 3600 sc->dc_if_flags = ifp->if_flags; 3601 DC_UNLOCK(sc); 3602 error = 0; 3603 break; 3604 case SIOCADDMULTI: 3605 case SIOCDELMULTI: 3606 DC_LOCK(sc); 3607 dc_setfilt(sc); 3608 DC_UNLOCK(sc); 3609 error = 0; 3610 break; 3611 case SIOCGIFMEDIA: 3612 case SIOCSIFMEDIA: 3613 mii = device_get_softc(sc->dc_miibus); 3614 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3615 break; 3616 case SIOCSIFCAP: 3617 #ifdef DEVICE_POLLING 3618 if (ifr->ifr_reqcap & IFCAP_POLLING && 3619 !(ifp->if_capenable & IFCAP_POLLING)) { 3620 error = ether_poll_register(dc_poll, ifp); 3621 if (error) 3622 return(error); 3623 DC_LOCK(sc); 3624 /* Disable interrupts */ 3625 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3626 ifp->if_capenable |= IFCAP_POLLING; 3627 DC_UNLOCK(sc); 3628 return (error); 3629 } 3630 if (!(ifr->ifr_reqcap & IFCAP_POLLING) && 3631 ifp->if_capenable & IFCAP_POLLING) { 3632 error = ether_poll_deregister(ifp); 3633 /* Enable interrupts. */ 3634 DC_LOCK(sc); 3635 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3636 ifp->if_capenable &= ~IFCAP_POLLING; 3637 DC_UNLOCK(sc); 3638 return (error); 3639 } 3640 #endif /* DEVICE_POLLING */ 3641 break; 3642 default: 3643 error = ether_ioctl(ifp, command, data); 3644 break; 3645 } 3646 3647 return (error); 3648 } 3649 3650 static void 3651 dc_watchdog(void *xsc) 3652 { 3653 struct dc_softc *sc = xsc; 3654 struct ifnet *ifp; 3655 3656 DC_LOCK_ASSERT(sc); 3657 3658 if (sc->dc_wdog_timer == 0 || --sc->dc_wdog_timer != 0) { 3659 callout_reset(&sc->dc_wdog_ch, hz, dc_watchdog, sc); 3660 return; 3661 } 3662 3663 ifp = sc->dc_ifp; 3664 ifp->if_oerrors++; 3665 device_printf(sc->dc_dev, "watchdog timeout\n"); 3666 3667 dc_stop(sc); 3668 dc_reset(sc); 3669 dc_init_locked(sc); 3670 3671 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3672 dc_start_locked(ifp); 3673 } 3674 3675 /* 3676 * Stop the adapter and free any mbufs allocated to the 3677 * RX and TX lists. 3678 */ 3679 static void 3680 dc_stop(struct dc_softc *sc) 3681 { 3682 struct ifnet *ifp; 3683 struct dc_list_data *ld; 3684 struct dc_chain_data *cd; 3685 int i; 3686 u_int32_t ctl; 3687 3688 DC_LOCK_ASSERT(sc); 3689 3690 ifp = sc->dc_ifp; 3691 ld = sc->dc_ldata; 3692 cd = &sc->dc_cdata; 3693 3694 callout_stop(&sc->dc_stat_ch); 3695 callout_stop(&sc->dc_wdog_ch); 3696 sc->dc_wdog_timer = 0; 3697 3698 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3699 3700 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)); 3701 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3702 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3703 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3704 sc->dc_link = 0; 3705 3706 /* 3707 * Free data in the RX lists. 3708 */ 3709 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3710 if (cd->dc_rx_chain[i] != NULL) { 3711 m_freem(cd->dc_rx_chain[i]); 3712 cd->dc_rx_chain[i] = NULL; 3713 } 3714 } 3715 bzero(&ld->dc_rx_list, sizeof(ld->dc_rx_list)); 3716 3717 /* 3718 * Free the TX list buffers. 3719 */ 3720 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3721 if (cd->dc_tx_chain[i] != NULL) { 3722 ctl = le32toh(ld->dc_tx_list[i].dc_ctl); 3723 if ((ctl & DC_TXCTL_SETUP) || 3724 !(ctl & DC_TXCTL_LASTFRAG)) { 3725 cd->dc_tx_chain[i] = NULL; 3726 continue; 3727 } 3728 bus_dmamap_unload(sc->dc_mtag, cd->dc_tx_map[i]); 3729 m_freem(cd->dc_tx_chain[i]); 3730 cd->dc_tx_chain[i] = NULL; 3731 } 3732 } 3733 bzero(&ld->dc_tx_list, sizeof(ld->dc_tx_list)); 3734 } 3735 3736 /* 3737 * Device suspend routine. Stop the interface and save some PCI 3738 * settings in case the BIOS doesn't restore them properly on 3739 * resume. 3740 */ 3741 static int 3742 dc_suspend(device_t dev) 3743 { 3744 struct dc_softc *sc; 3745 3746 sc = device_get_softc(dev); 3747 DC_LOCK(sc); 3748 dc_stop(sc); 3749 sc->suspended = 1; 3750 DC_UNLOCK(sc); 3751 3752 return (0); 3753 } 3754 3755 /* 3756 * Device resume routine. Restore some PCI settings in case the BIOS 3757 * doesn't, re-enable busmastering, and restart the interface if 3758 * appropriate. 3759 */ 3760 static int 3761 dc_resume(device_t dev) 3762 { 3763 struct dc_softc *sc; 3764 struct ifnet *ifp; 3765 3766 sc = device_get_softc(dev); 3767 ifp = sc->dc_ifp; 3768 3769 /* reinitialize interface if necessary */ 3770 DC_LOCK(sc); 3771 if (ifp->if_flags & IFF_UP) 3772 dc_init_locked(sc); 3773 3774 sc->suspended = 0; 3775 DC_UNLOCK(sc); 3776 3777 return (0); 3778 } 3779 3780 /* 3781 * Stop all chip I/O so that the kernel's probe routines don't 3782 * get confused by errant DMAs when rebooting. 3783 */ 3784 static int 3785 dc_shutdown(device_t dev) 3786 { 3787 struct dc_softc *sc; 3788 3789 sc = device_get_softc(dev); 3790 3791 DC_LOCK(sc); 3792 dc_stop(sc); 3793 DC_UNLOCK(sc); 3794 3795 return (0); 3796 } 3797