1 /*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 38 * series chips and several workalikes including the following: 39 * 40 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 41 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 42 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 43 * ASIX Electronics AX88140A (www.asix.com.tw) 44 * ASIX Electronics AX88141 (www.asix.com.tw) 45 * ADMtek AL981 (www.admtek.com.tw) 46 * ADMtek AN985 (www.admtek.com.tw) 47 * Netgear FA511 (www.netgear.com) Appears to be rebadged ADMTek AN985 48 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 49 * Accton EN1217 (www.accton.com) 50 * Xircom X3201 (www.xircom.com) 51 * Abocom FE2500 52 * Conexant LANfinity (www.conexant.com) 53 * 3Com OfficeConnect 10/100B 3CSOHO100B (www.3com.com) 54 * 55 * Datasheets for the 21143 are available at developer.intel.com. 56 * Datasheets for the clone parts can be found at their respective sites. 57 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 58 * The PNIC II is essentially a Macronix 98715A chip; the only difference 59 * worth noting is that its multicast hash table is only 128 bits wide 60 * instead of 512. 61 * 62 * Written by Bill Paul <wpaul@ee.columbia.edu> 63 * Electrical Engineering Department 64 * Columbia University, New York City 65 */ 66 /* 67 * The Intel 21143 is the successor to the DEC 21140. It is basically 68 * the same as the 21140 but with a few new features. The 21143 supports 69 * three kinds of media attachments: 70 * 71 * o MII port, for 10Mbps and 100Mbps support and NWAY 72 * autonegotiation provided by an external PHY. 73 * o SYM port, for symbol mode 100Mbps support. 74 * o 10baseT port. 75 * o AUI/BNC port. 76 * 77 * The 100Mbps SYM port and 10baseT port can be used together in 78 * combination with the internal NWAY support to create a 10/100 79 * autosensing configuration. 80 * 81 * Note that not all tulip workalikes are handled in this driver: we only 82 * deal with those which are relatively well behaved. The Winbond is 83 * handled separately due to its different register offsets and the 84 * special handling needed for its various bugs. The PNIC is handled 85 * here, but I'm not thrilled about it. 86 * 87 * All of the workalike chips use some form of MII transceiver support 88 * with the exception of the Macronix chips, which also have a SYM port. 89 * The ASIX AX88140A is also documented to have a SYM port, but all 90 * the cards I've seen use an MII transceiver, probably because the 91 * AX88140A doesn't support internal NWAY. 92 */ 93 94 #ifdef HAVE_KERNEL_OPTION_HEADERS 95 #include "opt_device_polling.h" 96 #endif 97 98 #include <sys/param.h> 99 #include <sys/endian.h> 100 #include <sys/systm.h> 101 #include <sys/sockio.h> 102 #include <sys/mbuf.h> 103 #include <sys/malloc.h> 104 #include <sys/kernel.h> 105 #include <sys/module.h> 106 #include <sys/socket.h> 107 108 #include <net/if.h> 109 #include <net/if_arp.h> 110 #include <net/ethernet.h> 111 #include <net/if_dl.h> 112 #include <net/if_media.h> 113 #include <net/if_types.h> 114 #include <net/if_vlan_var.h> 115 116 #include <net/bpf.h> 117 118 #include <machine/bus.h> 119 #include <machine/resource.h> 120 #include <sys/bus.h> 121 #include <sys/rman.h> 122 123 #include <dev/mii/mii.h> 124 #include <dev/mii/miivar.h> 125 126 #include <dev/pci/pcireg.h> 127 #include <dev/pci/pcivar.h> 128 129 #define DC_USEIOSPACE 130 131 #include <dev/dc/if_dcreg.h> 132 133 #ifdef __sparc64__ 134 #include <dev/ofw/openfirm.h> 135 #include <machine/ofw_machdep.h> 136 #endif 137 138 MODULE_DEPEND(dc, pci, 1, 1, 1); 139 MODULE_DEPEND(dc, ether, 1, 1, 1); 140 MODULE_DEPEND(dc, miibus, 1, 1, 1); 141 142 /* 143 * "device miibus" is required in kernel config. See GENERIC if you get 144 * errors here. 145 */ 146 #include "miibus_if.h" 147 148 /* 149 * Various supported device vendors/types and their names. 150 */ 151 static const struct dc_type dc_devs[] = { 152 { DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143), 0, 153 "Intel 21143 10/100BaseTX" }, 154 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009), 0, 155 "Davicom DM9009 10/100BaseTX" }, 156 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100), 0, 157 "Davicom DM9100 10/100BaseTX" }, 158 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), DC_REVISION_DM9102A, 159 "Davicom DM9102A 10/100BaseTX" }, 160 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), 0, 161 "Davicom DM9102 10/100BaseTX" }, 162 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981), 0, 163 "ADMtek AL981 10/100BaseTX" }, 164 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985), 0, 165 "ADMtek AN985 10/100BaseTX" }, 166 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511), 0, 167 "ADMtek ADM9511 10/100BaseTX" }, 168 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513), 0, 169 "ADMtek ADM9513 10/100BaseTX" }, 170 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_FA511), 0, 171 "Netgear FA511 10/100BaseTX" }, 172 { DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), DC_REVISION_88141, 173 "ASIX AX88141 10/100BaseTX" }, 174 { DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), 0, 175 "ASIX AX88140A 10/100BaseTX" }, 176 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), DC_REVISION_98713A, 177 "Macronix 98713A 10/100BaseTX" }, 178 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), 0, 179 "Macronix 98713 10/100BaseTX" }, 180 { DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), DC_REVISION_98713A, 181 "Compex RL100-TX 10/100BaseTX" }, 182 { DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), 0, 183 "Compex RL100-TX 10/100BaseTX" }, 184 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98725, 185 "Macronix 98725 10/100BaseTX" }, 186 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98715AEC_C, 187 "Macronix 98715AEC-C 10/100BaseTX" }, 188 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), 0, 189 "Macronix 98715/98715A 10/100BaseTX" }, 190 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727), 0, 191 "Macronix 98727/98732 10/100BaseTX" }, 192 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115), 0, 193 "LC82C115 PNIC II 10/100BaseTX" }, 194 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), DC_REVISION_82C169, 195 "82c169 PNIC 10/100BaseTX" }, 196 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), 0, 197 "82c168 PNIC 10/100BaseTX" }, 198 { DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217), 0, 199 "Accton EN1217 10/100BaseTX" }, 200 { DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242), 0, 201 "Accton EN2242 MiniPCI 10/100BaseTX" }, 202 { DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201), 0, 203 "Xircom X3201 10/100BaseTX" }, 204 { DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD), 0, 205 "Neteasy DRP-32TXD Cardbus 10/100" }, 206 { DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500), 0, 207 "Abocom FE2500 10/100BaseTX" }, 208 { DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX), 0, 209 "Abocom FE2500MX 10/100BaseTX" }, 210 { DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112), 0, 211 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 212 { DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX), 0, 213 "Hawking CB102 CardBus 10/100" }, 214 { DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T), 0, 215 "PlaneX FNW-3602-T CardBus 10/100" }, 216 { DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB), 0, 217 "3Com OfficeConnect 10/100B" }, 218 { DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120), 0, 219 "Microsoft MN-120 CardBus 10/100" }, 220 { DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130), 0, 221 "Microsoft MN-130 10/100" }, 222 { DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08), 0, 223 "Linksys PCMPC200 CardBus 10/100" }, 224 { DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09), 0, 225 "Linksys PCMPC200 CardBus 10/100" }, 226 { 0, 0, NULL } 227 }; 228 229 static int dc_probe(device_t); 230 static int dc_attach(device_t); 231 static int dc_detach(device_t); 232 static int dc_suspend(device_t); 233 static int dc_resume(device_t); 234 static const struct dc_type *dc_devtype(device_t); 235 static int dc_newbuf(struct dc_softc *, int, int); 236 static int dc_encap(struct dc_softc *, struct mbuf **); 237 static void dc_pnic_rx_bug_war(struct dc_softc *, int); 238 static int dc_rx_resync(struct dc_softc *); 239 static void dc_rxeof(struct dc_softc *); 240 static void dc_txeof(struct dc_softc *); 241 static void dc_tick(void *); 242 static void dc_tx_underrun(struct dc_softc *); 243 static void dc_intr(void *); 244 static void dc_start(struct ifnet *); 245 static void dc_start_locked(struct ifnet *); 246 static int dc_ioctl(struct ifnet *, u_long, caddr_t); 247 static void dc_init(void *); 248 static void dc_init_locked(struct dc_softc *); 249 static void dc_stop(struct dc_softc *); 250 static void dc_watchdog(void *); 251 static int dc_shutdown(device_t); 252 static int dc_ifmedia_upd(struct ifnet *); 253 static void dc_ifmedia_sts(struct ifnet *, struct ifmediareq *); 254 255 static void dc_delay(struct dc_softc *); 256 static void dc_eeprom_idle(struct dc_softc *); 257 static void dc_eeprom_putbyte(struct dc_softc *, int); 258 static void dc_eeprom_getword(struct dc_softc *, int, u_int16_t *); 259 static void dc_eeprom_getword_pnic(struct dc_softc *, int, u_int16_t *); 260 static void dc_eeprom_getword_xircom(struct dc_softc *, int, u_int16_t *); 261 static void dc_eeprom_width(struct dc_softc *); 262 static void dc_read_eeprom(struct dc_softc *, caddr_t, int, int, int); 263 264 static void dc_mii_writebit(struct dc_softc *, int); 265 static int dc_mii_readbit(struct dc_softc *); 266 static void dc_mii_sync(struct dc_softc *); 267 static void dc_mii_send(struct dc_softc *, u_int32_t, int); 268 static int dc_mii_readreg(struct dc_softc *, struct dc_mii_frame *); 269 static int dc_mii_writereg(struct dc_softc *, struct dc_mii_frame *); 270 static int dc_miibus_readreg(device_t, int, int); 271 static int dc_miibus_writereg(device_t, int, int, int); 272 static void dc_miibus_statchg(device_t); 273 static void dc_miibus_mediainit(device_t); 274 275 static void dc_setcfg(struct dc_softc *, int); 276 static uint32_t dc_mchash_le(struct dc_softc *, const uint8_t *); 277 static uint32_t dc_mchash_be(const uint8_t *); 278 static void dc_setfilt_21143(struct dc_softc *); 279 static void dc_setfilt_asix(struct dc_softc *); 280 static void dc_setfilt_admtek(struct dc_softc *); 281 static void dc_setfilt_xircom(struct dc_softc *); 282 283 static void dc_setfilt(struct dc_softc *); 284 285 static void dc_reset(struct dc_softc *); 286 static int dc_list_rx_init(struct dc_softc *); 287 static int dc_list_tx_init(struct dc_softc *); 288 289 static void dc_read_srom(struct dc_softc *, int); 290 static void dc_parse_21143_srom(struct dc_softc *); 291 static void dc_decode_leaf_sia(struct dc_softc *, struct dc_eblock_sia *); 292 static void dc_decode_leaf_mii(struct dc_softc *, struct dc_eblock_mii *); 293 static void dc_decode_leaf_sym(struct dc_softc *, struct dc_eblock_sym *); 294 static void dc_apply_fixup(struct dc_softc *, int); 295 296 #ifdef DC_USEIOSPACE 297 #define DC_RES SYS_RES_IOPORT 298 #define DC_RID DC_PCI_CFBIO 299 #else 300 #define DC_RES SYS_RES_MEMORY 301 #define DC_RID DC_PCI_CFBMA 302 #endif 303 304 static device_method_t dc_methods[] = { 305 /* Device interface */ 306 DEVMETHOD(device_probe, dc_probe), 307 DEVMETHOD(device_attach, dc_attach), 308 DEVMETHOD(device_detach, dc_detach), 309 DEVMETHOD(device_suspend, dc_suspend), 310 DEVMETHOD(device_resume, dc_resume), 311 DEVMETHOD(device_shutdown, dc_shutdown), 312 313 /* bus interface */ 314 DEVMETHOD(bus_print_child, bus_generic_print_child), 315 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 316 317 /* MII interface */ 318 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 319 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 320 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 321 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 322 323 { 0, 0 } 324 }; 325 326 static driver_t dc_driver = { 327 "dc", 328 dc_methods, 329 sizeof(struct dc_softc) 330 }; 331 332 static devclass_t dc_devclass; 333 334 DRIVER_MODULE(dc, cardbus, dc_driver, dc_devclass, 0, 0); 335 DRIVER_MODULE(dc, pci, dc_driver, dc_devclass, 0, 0); 336 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 337 338 #define DC_SETBIT(sc, reg, x) \ 339 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 340 341 #define DC_CLRBIT(sc, reg, x) \ 342 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 343 344 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 345 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 346 347 static void 348 dc_delay(struct dc_softc *sc) 349 { 350 int idx; 351 352 for (idx = (300 / 33) + 1; idx > 0; idx--) 353 CSR_READ_4(sc, DC_BUSCTL); 354 } 355 356 static void 357 dc_eeprom_width(struct dc_softc *sc) 358 { 359 int i; 360 361 /* Force EEPROM to idle state. */ 362 dc_eeprom_idle(sc); 363 364 /* Enter EEPROM access mode. */ 365 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 366 dc_delay(sc); 367 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 368 dc_delay(sc); 369 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 370 dc_delay(sc); 371 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 372 dc_delay(sc); 373 374 for (i = 3; i--;) { 375 if (6 & (1 << i)) 376 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 377 else 378 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 379 dc_delay(sc); 380 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 381 dc_delay(sc); 382 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 383 dc_delay(sc); 384 } 385 386 for (i = 1; i <= 12; i++) { 387 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 388 dc_delay(sc); 389 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { 390 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 391 dc_delay(sc); 392 break; 393 } 394 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 395 dc_delay(sc); 396 } 397 398 /* Turn off EEPROM access mode. */ 399 dc_eeprom_idle(sc); 400 401 if (i < 4 || i > 12) 402 sc->dc_romwidth = 6; 403 else 404 sc->dc_romwidth = i; 405 406 /* Enter EEPROM access mode. */ 407 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 408 dc_delay(sc); 409 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 410 dc_delay(sc); 411 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 412 dc_delay(sc); 413 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 414 dc_delay(sc); 415 416 /* Turn off EEPROM access mode. */ 417 dc_eeprom_idle(sc); 418 } 419 420 static void 421 dc_eeprom_idle(struct dc_softc *sc) 422 { 423 int i; 424 425 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 426 dc_delay(sc); 427 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 428 dc_delay(sc); 429 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 430 dc_delay(sc); 431 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 432 dc_delay(sc); 433 434 for (i = 0; i < 25; i++) { 435 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 436 dc_delay(sc); 437 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 438 dc_delay(sc); 439 } 440 441 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 442 dc_delay(sc); 443 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 444 dc_delay(sc); 445 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 446 } 447 448 /* 449 * Send a read command and address to the EEPROM, check for ACK. 450 */ 451 static void 452 dc_eeprom_putbyte(struct dc_softc *sc, int addr) 453 { 454 int d, i; 455 456 d = DC_EECMD_READ >> 6; 457 for (i = 3; i--; ) { 458 if (d & (1 << i)) 459 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 460 else 461 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 462 dc_delay(sc); 463 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 464 dc_delay(sc); 465 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 466 dc_delay(sc); 467 } 468 469 /* 470 * Feed in each bit and strobe the clock. 471 */ 472 for (i = sc->dc_romwidth; i--;) { 473 if (addr & (1 << i)) { 474 SIO_SET(DC_SIO_EE_DATAIN); 475 } else { 476 SIO_CLR(DC_SIO_EE_DATAIN); 477 } 478 dc_delay(sc); 479 SIO_SET(DC_SIO_EE_CLK); 480 dc_delay(sc); 481 SIO_CLR(DC_SIO_EE_CLK); 482 dc_delay(sc); 483 } 484 } 485 486 /* 487 * Read a word of data stored in the EEPROM at address 'addr.' 488 * The PNIC 82c168/82c169 has its own non-standard way to read 489 * the EEPROM. 490 */ 491 static void 492 dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, u_int16_t *dest) 493 { 494 int i; 495 u_int32_t r; 496 497 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr); 498 499 for (i = 0; i < DC_TIMEOUT; i++) { 500 DELAY(1); 501 r = CSR_READ_4(sc, DC_SIO); 502 if (!(r & DC_PN_SIOCTL_BUSY)) { 503 *dest = (u_int16_t)(r & 0xFFFF); 504 return; 505 } 506 } 507 } 508 509 /* 510 * Read a word of data stored in the EEPROM at address 'addr.' 511 * The Xircom X3201 has its own non-standard way to read 512 * the EEPROM, too. 513 */ 514 static void 515 dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, u_int16_t *dest) 516 { 517 518 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 519 520 addr *= 2; 521 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 522 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff; 523 addr += 1; 524 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 525 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8; 526 527 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 528 } 529 530 /* 531 * Read a word of data stored in the EEPROM at address 'addr.' 532 */ 533 static void 534 dc_eeprom_getword(struct dc_softc *sc, int addr, u_int16_t *dest) 535 { 536 int i; 537 u_int16_t word = 0; 538 539 /* Force EEPROM to idle state. */ 540 dc_eeprom_idle(sc); 541 542 /* Enter EEPROM access mode. */ 543 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 544 dc_delay(sc); 545 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 546 dc_delay(sc); 547 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 548 dc_delay(sc); 549 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 550 dc_delay(sc); 551 552 /* 553 * Send address of word we want to read. 554 */ 555 dc_eeprom_putbyte(sc, addr); 556 557 /* 558 * Start reading bits from EEPROM. 559 */ 560 for (i = 0x8000; i; i >>= 1) { 561 SIO_SET(DC_SIO_EE_CLK); 562 dc_delay(sc); 563 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 564 word |= i; 565 dc_delay(sc); 566 SIO_CLR(DC_SIO_EE_CLK); 567 dc_delay(sc); 568 } 569 570 /* Turn off EEPROM access mode. */ 571 dc_eeprom_idle(sc); 572 573 *dest = word; 574 } 575 576 /* 577 * Read a sequence of words from the EEPROM. 578 */ 579 static void 580 dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int be) 581 { 582 int i; 583 u_int16_t word = 0, *ptr; 584 585 for (i = 0; i < cnt; i++) { 586 if (DC_IS_PNIC(sc)) 587 dc_eeprom_getword_pnic(sc, off + i, &word); 588 else if (DC_IS_XIRCOM(sc)) 589 dc_eeprom_getword_xircom(sc, off + i, &word); 590 else 591 dc_eeprom_getword(sc, off + i, &word); 592 ptr = (u_int16_t *)(dest + (i * 2)); 593 if (be) 594 *ptr = be16toh(word); 595 else 596 *ptr = le16toh(word); 597 } 598 } 599 600 /* 601 * The following two routines are taken from the Macronix 98713 602 * Application Notes pp.19-21. 603 */ 604 /* 605 * Write a bit to the MII bus. 606 */ 607 static void 608 dc_mii_writebit(struct dc_softc *sc, int bit) 609 { 610 611 if (bit) 612 CSR_WRITE_4(sc, DC_SIO, 613 DC_SIO_ROMCTL_WRITE | DC_SIO_MII_DATAOUT); 614 else 615 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 616 617 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 618 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 619 } 620 621 /* 622 * Read a bit from the MII bus. 623 */ 624 static int 625 dc_mii_readbit(struct dc_softc *sc) 626 { 627 628 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ | DC_SIO_MII_DIR); 629 CSR_READ_4(sc, DC_SIO); 630 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 631 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 632 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 633 return (1); 634 635 return (0); 636 } 637 638 /* 639 * Sync the PHYs by setting data bit and strobing the clock 32 times. 640 */ 641 static void 642 dc_mii_sync(struct dc_softc *sc) 643 { 644 int i; 645 646 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 647 648 for (i = 0; i < 32; i++) 649 dc_mii_writebit(sc, 1); 650 } 651 652 /* 653 * Clock a series of bits through the MII. 654 */ 655 static void 656 dc_mii_send(struct dc_softc *sc, u_int32_t bits, int cnt) 657 { 658 int i; 659 660 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 661 dc_mii_writebit(sc, bits & i); 662 } 663 664 /* 665 * Read an PHY register through the MII. 666 */ 667 static int 668 dc_mii_readreg(struct dc_softc *sc, struct dc_mii_frame *frame) 669 { 670 int i, ack; 671 672 /* 673 * Set up frame for RX. 674 */ 675 frame->mii_stdelim = DC_MII_STARTDELIM; 676 frame->mii_opcode = DC_MII_READOP; 677 frame->mii_turnaround = 0; 678 frame->mii_data = 0; 679 680 /* 681 * Sync the PHYs. 682 */ 683 dc_mii_sync(sc); 684 685 /* 686 * Send command/address info. 687 */ 688 dc_mii_send(sc, frame->mii_stdelim, 2); 689 dc_mii_send(sc, frame->mii_opcode, 2); 690 dc_mii_send(sc, frame->mii_phyaddr, 5); 691 dc_mii_send(sc, frame->mii_regaddr, 5); 692 693 #ifdef notdef 694 /* Idle bit */ 695 dc_mii_writebit(sc, 1); 696 dc_mii_writebit(sc, 0); 697 #endif 698 699 /* Check for ack. */ 700 ack = dc_mii_readbit(sc); 701 702 /* 703 * Now try reading data bits. If the ack failed, we still 704 * need to clock through 16 cycles to keep the PHY(s) in sync. 705 */ 706 if (ack) { 707 for (i = 0; i < 16; i++) 708 dc_mii_readbit(sc); 709 goto fail; 710 } 711 712 for (i = 0x8000; i; i >>= 1) { 713 if (!ack) { 714 if (dc_mii_readbit(sc)) 715 frame->mii_data |= i; 716 } 717 } 718 719 fail: 720 721 dc_mii_writebit(sc, 0); 722 dc_mii_writebit(sc, 0); 723 724 if (ack) 725 return (1); 726 return (0); 727 } 728 729 /* 730 * Write to a PHY register through the MII. 731 */ 732 static int 733 dc_mii_writereg(struct dc_softc *sc, struct dc_mii_frame *frame) 734 { 735 736 /* 737 * Set up frame for TX. 738 */ 739 740 frame->mii_stdelim = DC_MII_STARTDELIM; 741 frame->mii_opcode = DC_MII_WRITEOP; 742 frame->mii_turnaround = DC_MII_TURNAROUND; 743 744 /* 745 * Sync the PHYs. 746 */ 747 dc_mii_sync(sc); 748 749 dc_mii_send(sc, frame->mii_stdelim, 2); 750 dc_mii_send(sc, frame->mii_opcode, 2); 751 dc_mii_send(sc, frame->mii_phyaddr, 5); 752 dc_mii_send(sc, frame->mii_regaddr, 5); 753 dc_mii_send(sc, frame->mii_turnaround, 2); 754 dc_mii_send(sc, frame->mii_data, 16); 755 756 /* Idle bit. */ 757 dc_mii_writebit(sc, 0); 758 dc_mii_writebit(sc, 0); 759 760 return (0); 761 } 762 763 static int 764 dc_miibus_readreg(device_t dev, int phy, int reg) 765 { 766 struct dc_mii_frame frame; 767 struct dc_softc *sc; 768 int i, rval, phy_reg = 0; 769 770 sc = device_get_softc(dev); 771 bzero(&frame, sizeof(frame)); 772 773 /* 774 * Note: both the AL981 and AN985 have internal PHYs, 775 * however the AL981 provides direct access to the PHY 776 * registers while the AN985 uses a serial MII interface. 777 * The AN985's MII interface is also buggy in that you 778 * can read from any MII address (0 to 31), but only address 1 779 * behaves normally. To deal with both cases, we pretend 780 * that the PHY is at MII address 1. 781 */ 782 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 783 return (0); 784 785 /* 786 * Note: the ukphy probes of the RS7112 report a PHY at 787 * MII address 0 (possibly HomePNA?) and 1 (ethernet) 788 * so we only respond to correct one. 789 */ 790 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 791 return (0); 792 793 if (sc->dc_pmode != DC_PMODE_MII) { 794 if (phy == (MII_NPHY - 1)) { 795 switch (reg) { 796 case MII_BMSR: 797 /* 798 * Fake something to make the probe 799 * code think there's a PHY here. 800 */ 801 return (BMSR_MEDIAMASK); 802 break; 803 case MII_PHYIDR1: 804 if (DC_IS_PNIC(sc)) 805 return (DC_VENDORID_LO); 806 return (DC_VENDORID_DEC); 807 break; 808 case MII_PHYIDR2: 809 if (DC_IS_PNIC(sc)) 810 return (DC_DEVICEID_82C168); 811 return (DC_DEVICEID_21143); 812 break; 813 default: 814 return (0); 815 break; 816 } 817 } else 818 return (0); 819 } 820 821 if (DC_IS_PNIC(sc)) { 822 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 823 (phy << 23) | (reg << 18)); 824 for (i = 0; i < DC_TIMEOUT; i++) { 825 DELAY(1); 826 rval = CSR_READ_4(sc, DC_PN_MII); 827 if (!(rval & DC_PN_MII_BUSY)) { 828 rval &= 0xFFFF; 829 return (rval == 0xFFFF ? 0 : rval); 830 } 831 } 832 return (0); 833 } 834 835 if (DC_IS_COMET(sc)) { 836 switch (reg) { 837 case MII_BMCR: 838 phy_reg = DC_AL_BMCR; 839 break; 840 case MII_BMSR: 841 phy_reg = DC_AL_BMSR; 842 break; 843 case MII_PHYIDR1: 844 phy_reg = DC_AL_VENID; 845 break; 846 case MII_PHYIDR2: 847 phy_reg = DC_AL_DEVID; 848 break; 849 case MII_ANAR: 850 phy_reg = DC_AL_ANAR; 851 break; 852 case MII_ANLPAR: 853 phy_reg = DC_AL_LPAR; 854 break; 855 case MII_ANER: 856 phy_reg = DC_AL_ANER; 857 break; 858 default: 859 device_printf(dev, "phy_read: bad phy register %x\n", 860 reg); 861 return (0); 862 break; 863 } 864 865 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 866 867 if (rval == 0xFFFF) 868 return (0); 869 return (rval); 870 } 871 872 frame.mii_phyaddr = phy; 873 frame.mii_regaddr = reg; 874 if (sc->dc_type == DC_TYPE_98713) { 875 phy_reg = CSR_READ_4(sc, DC_NETCFG); 876 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 877 } 878 dc_mii_readreg(sc, &frame); 879 if (sc->dc_type == DC_TYPE_98713) 880 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 881 882 return (frame.mii_data); 883 } 884 885 static int 886 dc_miibus_writereg(device_t dev, int phy, int reg, int data) 887 { 888 struct dc_softc *sc; 889 struct dc_mii_frame frame; 890 int i, phy_reg = 0; 891 892 sc = device_get_softc(dev); 893 bzero(&frame, sizeof(frame)); 894 895 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 896 return (0); 897 898 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 899 return (0); 900 901 if (DC_IS_PNIC(sc)) { 902 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 903 (phy << 23) | (reg << 10) | data); 904 for (i = 0; i < DC_TIMEOUT; i++) { 905 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 906 break; 907 } 908 return (0); 909 } 910 911 if (DC_IS_COMET(sc)) { 912 switch (reg) { 913 case MII_BMCR: 914 phy_reg = DC_AL_BMCR; 915 break; 916 case MII_BMSR: 917 phy_reg = DC_AL_BMSR; 918 break; 919 case MII_PHYIDR1: 920 phy_reg = DC_AL_VENID; 921 break; 922 case MII_PHYIDR2: 923 phy_reg = DC_AL_DEVID; 924 break; 925 case MII_ANAR: 926 phy_reg = DC_AL_ANAR; 927 break; 928 case MII_ANLPAR: 929 phy_reg = DC_AL_LPAR; 930 break; 931 case MII_ANER: 932 phy_reg = DC_AL_ANER; 933 break; 934 default: 935 device_printf(dev, "phy_write: bad phy register %x\n", 936 reg); 937 return (0); 938 break; 939 } 940 941 CSR_WRITE_4(sc, phy_reg, data); 942 return (0); 943 } 944 945 frame.mii_phyaddr = phy; 946 frame.mii_regaddr = reg; 947 frame.mii_data = data; 948 949 if (sc->dc_type == DC_TYPE_98713) { 950 phy_reg = CSR_READ_4(sc, DC_NETCFG); 951 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 952 } 953 dc_mii_writereg(sc, &frame); 954 if (sc->dc_type == DC_TYPE_98713) 955 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 956 957 return (0); 958 } 959 960 static void 961 dc_miibus_statchg(device_t dev) 962 { 963 struct dc_softc *sc; 964 struct mii_data *mii; 965 struct ifmedia *ifm; 966 967 sc = device_get_softc(dev); 968 if (DC_IS_ADMTEK(sc)) 969 return; 970 971 mii = device_get_softc(sc->dc_miibus); 972 ifm = &mii->mii_media; 973 if (DC_IS_DAVICOM(sc) && 974 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 975 dc_setcfg(sc, ifm->ifm_media); 976 sc->dc_if_media = ifm->ifm_media; 977 } else { 978 dc_setcfg(sc, mii->mii_media_active); 979 sc->dc_if_media = mii->mii_media_active; 980 } 981 } 982 983 /* 984 * Special support for DM9102A cards with HomePNA PHYs. Note: 985 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 986 * to be impossible to talk to the management interface of the DM9801 987 * PHY (its MDIO pin is not connected to anything). Consequently, 988 * the driver has to just 'know' about the additional mode and deal 989 * with it itself. *sigh* 990 */ 991 static void 992 dc_miibus_mediainit(device_t dev) 993 { 994 struct dc_softc *sc; 995 struct mii_data *mii; 996 struct ifmedia *ifm; 997 int rev; 998 999 rev = pci_get_revid(dev); 1000 1001 sc = device_get_softc(dev); 1002 mii = device_get_softc(sc->dc_miibus); 1003 ifm = &mii->mii_media; 1004 1005 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 1006 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL); 1007 } 1008 1009 #define DC_BITS_512 9 1010 #define DC_BITS_128 7 1011 #define DC_BITS_64 6 1012 1013 static uint32_t 1014 dc_mchash_le(struct dc_softc *sc, const uint8_t *addr) 1015 { 1016 uint32_t crc; 1017 1018 /* Compute CRC for the address value. */ 1019 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 1020 1021 /* 1022 * The hash table on the PNIC II and the MX98715AEC-C/D/E 1023 * chips is only 128 bits wide. 1024 */ 1025 if (sc->dc_flags & DC_128BIT_HASH) 1026 return (crc & ((1 << DC_BITS_128) - 1)); 1027 1028 /* The hash table on the MX98715BEC is only 64 bits wide. */ 1029 if (sc->dc_flags & DC_64BIT_HASH) 1030 return (crc & ((1 << DC_BITS_64) - 1)); 1031 1032 /* Xircom's hash filtering table is different (read: weird) */ 1033 /* Xircom uses the LEAST significant bits */ 1034 if (DC_IS_XIRCOM(sc)) { 1035 if ((crc & 0x180) == 0x180) 1036 return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4)); 1037 else 1038 return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 + 1039 (12 << 4)); 1040 } 1041 1042 return (crc & ((1 << DC_BITS_512) - 1)); 1043 } 1044 1045 /* 1046 * Calculate CRC of a multicast group address, return the lower 6 bits. 1047 */ 1048 static uint32_t 1049 dc_mchash_be(const uint8_t *addr) 1050 { 1051 uint32_t crc; 1052 1053 /* Compute CRC for the address value. */ 1054 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 1055 1056 /* Return the filter bit position. */ 1057 return ((crc >> 26) & 0x0000003F); 1058 } 1059 1060 /* 1061 * 21143-style RX filter setup routine. Filter programming is done by 1062 * downloading a special setup frame into the TX engine. 21143, Macronix, 1063 * PNIC, PNIC II and Davicom chips are programmed this way. 1064 * 1065 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1066 * address (our node address) and a 512-bit hash filter for multicast 1067 * frames. We also sneak the broadcast address into the hash filter since 1068 * we need that too. 1069 */ 1070 static void 1071 dc_setfilt_21143(struct dc_softc *sc) 1072 { 1073 uint16_t eaddr[(ETHER_ADDR_LEN+1)/2]; 1074 struct dc_desc *sframe; 1075 u_int32_t h, *sp; 1076 struct ifmultiaddr *ifma; 1077 struct ifnet *ifp; 1078 int i; 1079 1080 ifp = sc->dc_ifp; 1081 1082 i = sc->dc_cdata.dc_tx_prod; 1083 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1084 sc->dc_cdata.dc_tx_cnt++; 1085 sframe = &sc->dc_ldata->dc_tx_list[i]; 1086 sp = sc->dc_cdata.dc_sbuf; 1087 bzero(sp, DC_SFRAME_LEN); 1088 1089 sframe->dc_data = htole32(sc->dc_saddr); 1090 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1091 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1092 1093 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1094 1095 /* If we want promiscuous mode, set the allframes bit. */ 1096 if (ifp->if_flags & IFF_PROMISC) 1097 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1098 else 1099 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1100 1101 if (ifp->if_flags & IFF_ALLMULTI) 1102 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1103 else 1104 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1105 1106 IF_ADDR_LOCK(ifp); 1107 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1108 if (ifma->ifma_addr->sa_family != AF_LINK) 1109 continue; 1110 h = dc_mchash_le(sc, 1111 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1112 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1113 } 1114 IF_ADDR_UNLOCK(ifp); 1115 1116 if (ifp->if_flags & IFF_BROADCAST) { 1117 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1118 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1119 } 1120 1121 /* Set our MAC address. */ 1122 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1123 sp[39] = DC_SP_MAC(eaddr[0]); 1124 sp[40] = DC_SP_MAC(eaddr[1]); 1125 sp[41] = DC_SP_MAC(eaddr[2]); 1126 1127 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1128 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1129 1130 /* 1131 * The PNIC takes an exceedingly long time to process its 1132 * setup frame; wait 10ms after posting the setup frame 1133 * before proceeding, just so it has time to swallow its 1134 * medicine. 1135 */ 1136 DELAY(10000); 1137 1138 sc->dc_wdog_timer = 5; 1139 } 1140 1141 static void 1142 dc_setfilt_admtek(struct dc_softc *sc) 1143 { 1144 uint32_t eaddr[(ETHER_ADDR_LEN+3)/4]; 1145 struct ifnet *ifp; 1146 struct ifmultiaddr *ifma; 1147 int h = 0; 1148 u_int32_t hashes[2] = { 0, 0 }; 1149 1150 ifp = sc->dc_ifp; 1151 1152 /* Init our MAC address. */ 1153 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1154 CSR_WRITE_4(sc, DC_AL_PAR0, eaddr[0]); 1155 CSR_WRITE_4(sc, DC_AL_PAR1, eaddr[1]); 1156 1157 /* If we want promiscuous mode, set the allframes bit. */ 1158 if (ifp->if_flags & IFF_PROMISC) 1159 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1160 else 1161 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1162 1163 if (ifp->if_flags & IFF_ALLMULTI) 1164 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1165 else 1166 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1167 1168 /* First, zot all the existing hash bits. */ 1169 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1170 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1171 1172 /* 1173 * If we're already in promisc or allmulti mode, we 1174 * don't have to bother programming the multicast filter. 1175 */ 1176 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1177 return; 1178 1179 /* Now program new ones. */ 1180 IF_ADDR_LOCK(ifp); 1181 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1182 if (ifma->ifma_addr->sa_family != AF_LINK) 1183 continue; 1184 if (DC_IS_CENTAUR(sc)) 1185 h = dc_mchash_le(sc, 1186 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1187 else 1188 h = dc_mchash_be( 1189 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1190 if (h < 32) 1191 hashes[0] |= (1 << h); 1192 else 1193 hashes[1] |= (1 << (h - 32)); 1194 } 1195 IF_ADDR_UNLOCK(ifp); 1196 1197 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1198 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1199 } 1200 1201 static void 1202 dc_setfilt_asix(struct dc_softc *sc) 1203 { 1204 uint32_t eaddr[(ETHER_ADDR_LEN+3)/4]; 1205 struct ifnet *ifp; 1206 struct ifmultiaddr *ifma; 1207 int h = 0; 1208 u_int32_t hashes[2] = { 0, 0 }; 1209 1210 ifp = sc->dc_ifp; 1211 1212 /* Init our MAC address. */ 1213 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1214 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1215 CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[0]); 1216 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1217 CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[1]); 1218 1219 /* If we want promiscuous mode, set the allframes bit. */ 1220 if (ifp->if_flags & IFF_PROMISC) 1221 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1222 else 1223 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1224 1225 if (ifp->if_flags & IFF_ALLMULTI) 1226 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1227 else 1228 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1229 1230 /* 1231 * The ASIX chip has a special bit to enable reception 1232 * of broadcast frames. 1233 */ 1234 if (ifp->if_flags & IFF_BROADCAST) 1235 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1236 else 1237 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1238 1239 /* first, zot all the existing hash bits */ 1240 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1241 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1242 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1243 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1244 1245 /* 1246 * If we're already in promisc or allmulti mode, we 1247 * don't have to bother programming the multicast filter. 1248 */ 1249 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1250 return; 1251 1252 /* now program new ones */ 1253 IF_ADDR_LOCK(ifp); 1254 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1255 if (ifma->ifma_addr->sa_family != AF_LINK) 1256 continue; 1257 h = dc_mchash_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1258 if (h < 32) 1259 hashes[0] |= (1 << h); 1260 else 1261 hashes[1] |= (1 << (h - 32)); 1262 } 1263 IF_ADDR_UNLOCK(ifp); 1264 1265 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1266 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1267 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1268 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1269 } 1270 1271 static void 1272 dc_setfilt_xircom(struct dc_softc *sc) 1273 { 1274 uint16_t eaddr[(ETHER_ADDR_LEN+1)/2]; 1275 struct ifnet *ifp; 1276 struct ifmultiaddr *ifma; 1277 struct dc_desc *sframe; 1278 u_int32_t h, *sp; 1279 int i; 1280 1281 ifp = sc->dc_ifp; 1282 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1283 1284 i = sc->dc_cdata.dc_tx_prod; 1285 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1286 sc->dc_cdata.dc_tx_cnt++; 1287 sframe = &sc->dc_ldata->dc_tx_list[i]; 1288 sp = sc->dc_cdata.dc_sbuf; 1289 bzero(sp, DC_SFRAME_LEN); 1290 1291 sframe->dc_data = htole32(sc->dc_saddr); 1292 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1293 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1294 1295 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1296 1297 /* If we want promiscuous mode, set the allframes bit. */ 1298 if (ifp->if_flags & IFF_PROMISC) 1299 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1300 else 1301 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1302 1303 if (ifp->if_flags & IFF_ALLMULTI) 1304 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1305 else 1306 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1307 1308 IF_ADDR_LOCK(ifp); 1309 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1310 if (ifma->ifma_addr->sa_family != AF_LINK) 1311 continue; 1312 h = dc_mchash_le(sc, 1313 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1314 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1315 } 1316 IF_ADDR_UNLOCK(ifp); 1317 1318 if (ifp->if_flags & IFF_BROADCAST) { 1319 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1320 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1321 } 1322 1323 /* Set our MAC address. */ 1324 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1325 sp[0] = DC_SP_MAC(eaddr[0]); 1326 sp[1] = DC_SP_MAC(eaddr[1]); 1327 sp[2] = DC_SP_MAC(eaddr[2]); 1328 1329 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1330 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1331 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1332 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1333 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1334 1335 /* 1336 * Wait some time... 1337 */ 1338 DELAY(1000); 1339 1340 sc->dc_wdog_timer = 5; 1341 } 1342 1343 static void 1344 dc_setfilt(struct dc_softc *sc) 1345 { 1346 1347 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1348 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1349 dc_setfilt_21143(sc); 1350 1351 if (DC_IS_ASIX(sc)) 1352 dc_setfilt_asix(sc); 1353 1354 if (DC_IS_ADMTEK(sc)) 1355 dc_setfilt_admtek(sc); 1356 1357 if (DC_IS_XIRCOM(sc)) 1358 dc_setfilt_xircom(sc); 1359 } 1360 1361 /* 1362 * In order to fiddle with the 'full-duplex' and '100Mbps' bits in 1363 * the netconfig register, we first have to put the transmit and/or 1364 * receive logic in the idle state. 1365 */ 1366 static void 1367 dc_setcfg(struct dc_softc *sc, int media) 1368 { 1369 int i, restart = 0, watchdogreg; 1370 u_int32_t isr; 1371 1372 if (IFM_SUBTYPE(media) == IFM_NONE) 1373 return; 1374 1375 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) { 1376 restart = 1; 1377 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1378 1379 for (i = 0; i < DC_TIMEOUT; i++) { 1380 isr = CSR_READ_4(sc, DC_ISR); 1381 if (isr & DC_ISR_TX_IDLE && 1382 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1383 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT)) 1384 break; 1385 DELAY(10); 1386 } 1387 1388 if (i == DC_TIMEOUT) { 1389 if (!(isr & DC_ISR_TX_IDLE) && !DC_IS_ASIX(sc)) 1390 device_printf(sc->dc_dev, 1391 "%s: failed to force tx to idle state\n", 1392 __func__); 1393 if (!((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1394 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT) && 1395 !(DC_IS_CENTAUR(sc) || DC_IS_CONEXANT(sc) || 1396 (DC_IS_DAVICOM(sc) && pci_get_revid(sc->dc_dev) >= 1397 DC_REVISION_DM9102A))) 1398 device_printf(sc->dc_dev, 1399 "%s: failed to force rx to idle state\n", 1400 __func__); 1401 } 1402 } 1403 1404 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1405 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1406 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1407 if (sc->dc_pmode == DC_PMODE_MII) { 1408 if (DC_IS_INTEL(sc)) { 1409 /* There's a write enable bit here that reads as 1. */ 1410 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1411 watchdogreg &= ~DC_WDOG_CTLWREN; 1412 watchdogreg |= DC_WDOG_JABBERDIS; 1413 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1414 } else { 1415 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1416 } 1417 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1418 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1419 if (sc->dc_type == DC_TYPE_98713) 1420 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1421 DC_NETCFG_SCRAMBLER)); 1422 if (!DC_IS_DAVICOM(sc)) 1423 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1424 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1425 if (DC_IS_INTEL(sc)) 1426 dc_apply_fixup(sc, IFM_AUTO); 1427 } else { 1428 if (DC_IS_PNIC(sc)) { 1429 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1430 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1431 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1432 } 1433 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1434 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1435 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1436 if (DC_IS_INTEL(sc)) 1437 dc_apply_fixup(sc, 1438 (media & IFM_GMASK) == IFM_FDX ? 1439 IFM_100_TX | IFM_FDX : IFM_100_TX); 1440 } 1441 } 1442 1443 if (IFM_SUBTYPE(media) == IFM_10_T) { 1444 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1445 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1446 if (sc->dc_pmode == DC_PMODE_MII) { 1447 /* There's a write enable bit here that reads as 1. */ 1448 if (DC_IS_INTEL(sc)) { 1449 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1450 watchdogreg &= ~DC_WDOG_CTLWREN; 1451 watchdogreg |= DC_WDOG_JABBERDIS; 1452 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1453 } else { 1454 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1455 } 1456 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1457 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1458 if (sc->dc_type == DC_TYPE_98713) 1459 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1460 if (!DC_IS_DAVICOM(sc)) 1461 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1462 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1463 if (DC_IS_INTEL(sc)) 1464 dc_apply_fixup(sc, IFM_AUTO); 1465 } else { 1466 if (DC_IS_PNIC(sc)) { 1467 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1468 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1469 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1470 } 1471 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1472 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1473 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1474 if (DC_IS_INTEL(sc)) { 1475 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1476 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1477 if ((media & IFM_GMASK) == IFM_FDX) 1478 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1479 else 1480 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1481 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1482 DC_CLRBIT(sc, DC_10BTCTRL, 1483 DC_TCTL_AUTONEGENBL); 1484 dc_apply_fixup(sc, 1485 (media & IFM_GMASK) == IFM_FDX ? 1486 IFM_10_T | IFM_FDX : IFM_10_T); 1487 DELAY(20000); 1488 } 1489 } 1490 } 1491 1492 /* 1493 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1494 * PHY and we want HomePNA mode, set the portsel bit to turn 1495 * on the external MII port. 1496 */ 1497 if (DC_IS_DAVICOM(sc)) { 1498 if (IFM_SUBTYPE(media) == IFM_HPNA_1) { 1499 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1500 sc->dc_link = 1; 1501 } else { 1502 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1503 } 1504 } 1505 1506 if ((media & IFM_GMASK) == IFM_FDX) { 1507 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1508 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1509 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1510 } else { 1511 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1512 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1513 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1514 } 1515 1516 if (restart) 1517 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON | DC_NETCFG_RX_ON); 1518 } 1519 1520 static void 1521 dc_reset(struct dc_softc *sc) 1522 { 1523 int i; 1524 1525 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1526 1527 for (i = 0; i < DC_TIMEOUT; i++) { 1528 DELAY(10); 1529 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1530 break; 1531 } 1532 1533 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) || 1534 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) { 1535 DELAY(10000); 1536 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1537 i = 0; 1538 } 1539 1540 if (i == DC_TIMEOUT) 1541 device_printf(sc->dc_dev, "reset never completed!\n"); 1542 1543 /* Wait a little while for the chip to get its brains in order. */ 1544 DELAY(1000); 1545 1546 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1547 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1548 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1549 1550 /* 1551 * Bring the SIA out of reset. In some cases, it looks 1552 * like failing to unreset the SIA soon enough gets it 1553 * into a state where it will never come out of reset 1554 * until we reset the whole chip again. 1555 */ 1556 if (DC_IS_INTEL(sc)) { 1557 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1558 CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1559 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1560 } 1561 } 1562 1563 static const struct dc_type * 1564 dc_devtype(device_t dev) 1565 { 1566 const struct dc_type *t; 1567 u_int32_t devid; 1568 u_int8_t rev; 1569 1570 t = dc_devs; 1571 devid = pci_get_devid(dev); 1572 rev = pci_get_revid(dev); 1573 1574 while (t->dc_name != NULL) { 1575 if (devid == t->dc_devid && rev >= t->dc_minrev) 1576 return (t); 1577 t++; 1578 } 1579 1580 return (NULL); 1581 } 1582 1583 /* 1584 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1585 * IDs against our list and return a device name if we find a match. 1586 * We do a little bit of extra work to identify the exact type of 1587 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1588 * but different revision IDs. The same is true for 98715/98715A 1589 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1590 * cases, the exact chip revision affects driver behavior. 1591 */ 1592 static int 1593 dc_probe(device_t dev) 1594 { 1595 const struct dc_type *t; 1596 1597 t = dc_devtype(dev); 1598 1599 if (t != NULL) { 1600 device_set_desc(dev, t->dc_name); 1601 return (BUS_PROBE_DEFAULT); 1602 } 1603 1604 return (ENXIO); 1605 } 1606 1607 static void 1608 dc_apply_fixup(struct dc_softc *sc, int media) 1609 { 1610 struct dc_mediainfo *m; 1611 u_int8_t *p; 1612 int i; 1613 u_int32_t reg; 1614 1615 m = sc->dc_mi; 1616 1617 while (m != NULL) { 1618 if (m->dc_media == media) 1619 break; 1620 m = m->dc_next; 1621 } 1622 1623 if (m == NULL) 1624 return; 1625 1626 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1627 reg = (p[0] | (p[1] << 8)) << 16; 1628 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1629 } 1630 1631 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1632 reg = (p[0] | (p[1] << 8)) << 16; 1633 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1634 } 1635 } 1636 1637 static void 1638 dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l) 1639 { 1640 struct dc_mediainfo *m; 1641 1642 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1643 switch (l->dc_sia_code & ~DC_SIA_CODE_EXT) { 1644 case DC_SIA_CODE_10BT: 1645 m->dc_media = IFM_10_T; 1646 break; 1647 case DC_SIA_CODE_10BT_FDX: 1648 m->dc_media = IFM_10_T | IFM_FDX; 1649 break; 1650 case DC_SIA_CODE_10B2: 1651 m->dc_media = IFM_10_2; 1652 break; 1653 case DC_SIA_CODE_10B5: 1654 m->dc_media = IFM_10_5; 1655 break; 1656 default: 1657 break; 1658 } 1659 1660 /* 1661 * We need to ignore CSR13, CSR14, CSR15 for SIA mode. 1662 * Things apparently already work for cards that do 1663 * supply Media Specific Data. 1664 */ 1665 if (l->dc_sia_code & DC_SIA_CODE_EXT) { 1666 m->dc_gp_len = 2; 1667 m->dc_gp_ptr = 1668 (u_int8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl; 1669 } else { 1670 m->dc_gp_len = 2; 1671 m->dc_gp_ptr = 1672 (u_int8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl; 1673 } 1674 1675 m->dc_next = sc->dc_mi; 1676 sc->dc_mi = m; 1677 1678 sc->dc_pmode = DC_PMODE_SIA; 1679 } 1680 1681 static void 1682 dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l) 1683 { 1684 struct dc_mediainfo *m; 1685 1686 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1687 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1688 m->dc_media = IFM_100_TX; 1689 1690 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1691 m->dc_media = IFM_100_TX | IFM_FDX; 1692 1693 m->dc_gp_len = 2; 1694 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1695 1696 m->dc_next = sc->dc_mi; 1697 sc->dc_mi = m; 1698 1699 sc->dc_pmode = DC_PMODE_SYM; 1700 } 1701 1702 static void 1703 dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l) 1704 { 1705 struct dc_mediainfo *m; 1706 u_int8_t *p; 1707 1708 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1709 /* We abuse IFM_AUTO to represent MII. */ 1710 m->dc_media = IFM_AUTO; 1711 m->dc_gp_len = l->dc_gpr_len; 1712 1713 p = (u_int8_t *)l; 1714 p += sizeof(struct dc_eblock_mii); 1715 m->dc_gp_ptr = p; 1716 p += 2 * l->dc_gpr_len; 1717 m->dc_reset_len = *p; 1718 p++; 1719 m->dc_reset_ptr = p; 1720 1721 m->dc_next = sc->dc_mi; 1722 sc->dc_mi = m; 1723 } 1724 1725 static void 1726 dc_read_srom(struct dc_softc *sc, int bits) 1727 { 1728 int size; 1729 1730 size = 2 << bits; 1731 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT); 1732 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); 1733 } 1734 1735 static void 1736 dc_parse_21143_srom(struct dc_softc *sc) 1737 { 1738 struct dc_leaf_hdr *lhdr; 1739 struct dc_eblock_hdr *hdr; 1740 int have_mii, i, loff; 1741 char *ptr; 1742 1743 have_mii = 0; 1744 loff = sc->dc_srom[27]; 1745 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1746 1747 ptr = (char *)lhdr; 1748 ptr += sizeof(struct dc_leaf_hdr) - 1; 1749 /* 1750 * Look if we got a MII media block. 1751 */ 1752 for (i = 0; i < lhdr->dc_mcnt; i++) { 1753 hdr = (struct dc_eblock_hdr *)ptr; 1754 if (hdr->dc_type == DC_EBLOCK_MII) 1755 have_mii++; 1756 1757 ptr += (hdr->dc_len & 0x7F); 1758 ptr++; 1759 } 1760 1761 /* 1762 * Do the same thing again. Only use SIA and SYM media 1763 * blocks if no MII media block is available. 1764 */ 1765 ptr = (char *)lhdr; 1766 ptr += sizeof(struct dc_leaf_hdr) - 1; 1767 for (i = 0; i < lhdr->dc_mcnt; i++) { 1768 hdr = (struct dc_eblock_hdr *)ptr; 1769 switch (hdr->dc_type) { 1770 case DC_EBLOCK_MII: 1771 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1772 break; 1773 case DC_EBLOCK_SIA: 1774 if (! have_mii) 1775 dc_decode_leaf_sia(sc, 1776 (struct dc_eblock_sia *)hdr); 1777 break; 1778 case DC_EBLOCK_SYM: 1779 if (! have_mii) 1780 dc_decode_leaf_sym(sc, 1781 (struct dc_eblock_sym *)hdr); 1782 break; 1783 default: 1784 /* Don't care. Yet. */ 1785 break; 1786 } 1787 ptr += (hdr->dc_len & 0x7F); 1788 ptr++; 1789 } 1790 } 1791 1792 static void 1793 dc_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1794 { 1795 u_int32_t *paddr; 1796 1797 KASSERT(nseg == 1, 1798 ("%s: wrong number of segments (%d)", __func__, nseg)); 1799 paddr = arg; 1800 *paddr = segs->ds_addr; 1801 } 1802 1803 /* 1804 * Attach the interface. Allocate softc structures, do ifmedia 1805 * setup and ethernet/BPF attach. 1806 */ 1807 static int 1808 dc_attach(device_t dev) 1809 { 1810 int tmp = 0; 1811 uint32_t eaddr[(ETHER_ADDR_LEN+3)/4]; 1812 u_int32_t command; 1813 struct dc_softc *sc; 1814 struct ifnet *ifp; 1815 u_int32_t revision; 1816 int error = 0, rid, mac_offset; 1817 int i; 1818 u_int8_t *mac; 1819 1820 sc = device_get_softc(dev); 1821 sc->dc_dev = dev; 1822 1823 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1824 MTX_DEF); 1825 1826 /* 1827 * Map control/status registers. 1828 */ 1829 pci_enable_busmaster(dev); 1830 1831 rid = DC_RID; 1832 sc->dc_res = bus_alloc_resource_any(dev, DC_RES, &rid, RF_ACTIVE); 1833 1834 if (sc->dc_res == NULL) { 1835 device_printf(dev, "couldn't map ports/memory\n"); 1836 error = ENXIO; 1837 goto fail; 1838 } 1839 1840 sc->dc_btag = rman_get_bustag(sc->dc_res); 1841 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1842 1843 /* Allocate interrupt. */ 1844 rid = 0; 1845 sc->dc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1846 RF_SHAREABLE | RF_ACTIVE); 1847 1848 if (sc->dc_irq == NULL) { 1849 device_printf(dev, "couldn't map interrupt\n"); 1850 error = ENXIO; 1851 goto fail; 1852 } 1853 1854 /* Need this info to decide on a chip type. */ 1855 sc->dc_info = dc_devtype(dev); 1856 revision = pci_get_revid(dev); 1857 1858 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */ 1859 if (sc->dc_info->dc_devid != 1860 DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168) && 1861 sc->dc_info->dc_devid != 1862 DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201)) 1863 dc_eeprom_width(sc); 1864 1865 switch (sc->dc_info->dc_devid) { 1866 case DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143): 1867 sc->dc_type = DC_TYPE_21143; 1868 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1869 sc->dc_flags |= DC_REDUCED_MII_POLL; 1870 /* Save EEPROM contents so we can parse them later. */ 1871 dc_read_srom(sc, sc->dc_romwidth); 1872 break; 1873 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009): 1874 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100): 1875 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102): 1876 sc->dc_type = DC_TYPE_DM9102; 1877 sc->dc_flags |= DC_TX_COALESCE | DC_TX_INTR_ALWAYS; 1878 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_TX_STORENFWD; 1879 sc->dc_flags |= DC_TX_ALIGN; 1880 sc->dc_pmode = DC_PMODE_MII; 1881 1882 /* Increase the latency timer value. */ 1883 pci_write_config(dev, PCIR_LATTIMER, 0x80, 1); 1884 break; 1885 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981): 1886 sc->dc_type = DC_TYPE_AL981; 1887 sc->dc_flags |= DC_TX_USE_TX_INTR; 1888 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1889 sc->dc_pmode = DC_PMODE_MII; 1890 dc_read_srom(sc, sc->dc_romwidth); 1891 break; 1892 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985): 1893 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511): 1894 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513): 1895 case DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD): 1896 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_FA511): 1897 case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500): 1898 case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX): 1899 case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242): 1900 case DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX): 1901 case DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T): 1902 case DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB): 1903 case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120): 1904 case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130): 1905 case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08): 1906 case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09): 1907 sc->dc_type = DC_TYPE_AN985; 1908 sc->dc_flags |= DC_64BIT_HASH; 1909 sc->dc_flags |= DC_TX_USE_TX_INTR; 1910 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1911 sc->dc_pmode = DC_PMODE_MII; 1912 /* Don't read SROM for - auto-loaded on reset */ 1913 break; 1914 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713): 1915 case DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP): 1916 if (revision < DC_REVISION_98713A) { 1917 sc->dc_type = DC_TYPE_98713; 1918 } 1919 if (revision >= DC_REVISION_98713A) { 1920 sc->dc_type = DC_TYPE_98713A; 1921 sc->dc_flags |= DC_21143_NWAY; 1922 } 1923 sc->dc_flags |= DC_REDUCED_MII_POLL; 1924 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1925 break; 1926 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5): 1927 case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217): 1928 /* 1929 * Macronix MX98715AEC-C/D/E parts have only a 1930 * 128-bit hash table. We need to deal with these 1931 * in the same manner as the PNIC II so that we 1932 * get the right number of bits out of the 1933 * CRC routine. 1934 */ 1935 if (revision >= DC_REVISION_98715AEC_C && 1936 revision < DC_REVISION_98725) 1937 sc->dc_flags |= DC_128BIT_HASH; 1938 sc->dc_type = DC_TYPE_987x5; 1939 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1940 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1941 break; 1942 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727): 1943 sc->dc_type = DC_TYPE_987x5; 1944 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1945 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1946 break; 1947 case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115): 1948 sc->dc_type = DC_TYPE_PNICII; 1949 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR | DC_128BIT_HASH; 1950 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1951 break; 1952 case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168): 1953 sc->dc_type = DC_TYPE_PNIC; 1954 sc->dc_flags |= DC_TX_STORENFWD | DC_TX_INTR_ALWAYS; 1955 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 1956 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 1957 if (revision < DC_REVISION_82C169) 1958 sc->dc_pmode = DC_PMODE_SYM; 1959 break; 1960 case DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A): 1961 sc->dc_type = DC_TYPE_ASIX; 1962 sc->dc_flags |= DC_TX_USE_TX_INTR | DC_TX_INTR_FIRSTFRAG; 1963 sc->dc_flags |= DC_REDUCED_MII_POLL; 1964 sc->dc_pmode = DC_PMODE_MII; 1965 break; 1966 case DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201): 1967 sc->dc_type = DC_TYPE_XIRCOM; 1968 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 1969 DC_TX_ALIGN; 1970 /* 1971 * We don't actually need to coalesce, but we're doing 1972 * it to obtain a double word aligned buffer. 1973 * The DC_TX_COALESCE flag is required. 1974 */ 1975 sc->dc_pmode = DC_PMODE_MII; 1976 break; 1977 case DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112): 1978 sc->dc_type = DC_TYPE_CONEXANT; 1979 sc->dc_flags |= DC_TX_INTR_ALWAYS; 1980 sc->dc_flags |= DC_REDUCED_MII_POLL; 1981 sc->dc_pmode = DC_PMODE_MII; 1982 dc_read_srom(sc, sc->dc_romwidth); 1983 break; 1984 default: 1985 device_printf(dev, "unknown device: %x\n", 1986 sc->dc_info->dc_devid); 1987 break; 1988 } 1989 1990 /* Save the cache line size. */ 1991 if (DC_IS_DAVICOM(sc)) 1992 sc->dc_cachesize = 0; 1993 else 1994 sc->dc_cachesize = pci_get_cachelnsz(dev); 1995 1996 /* Reset the adapter. */ 1997 dc_reset(sc); 1998 1999 /* Take 21143 out of snooze mode */ 2000 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 2001 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2002 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 2003 pci_write_config(dev, DC_PCI_CFDD, command, 4); 2004 } 2005 2006 /* 2007 * Try to learn something about the supported media. 2008 * We know that ASIX and ADMtek and Davicom devices 2009 * will *always* be using MII media, so that's a no-brainer. 2010 * The tricky ones are the Macronix/PNIC II and the 2011 * Intel 21143. 2012 */ 2013 if (DC_IS_INTEL(sc)) 2014 dc_parse_21143_srom(sc); 2015 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2016 if (sc->dc_type == DC_TYPE_98713) 2017 sc->dc_pmode = DC_PMODE_MII; 2018 else 2019 sc->dc_pmode = DC_PMODE_SYM; 2020 } else if (!sc->dc_pmode) 2021 sc->dc_pmode = DC_PMODE_MII; 2022 2023 /* 2024 * Get station address from the EEPROM. 2025 */ 2026 switch(sc->dc_type) { 2027 case DC_TYPE_98713: 2028 case DC_TYPE_98713A: 2029 case DC_TYPE_987x5: 2030 case DC_TYPE_PNICII: 2031 dc_read_eeprom(sc, (caddr_t)&mac_offset, 2032 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2033 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2034 break; 2035 case DC_TYPE_PNIC: 2036 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2037 break; 2038 case DC_TYPE_DM9102: 2039 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2040 #ifdef __sparc64__ 2041 /* 2042 * If this is an onboard dc(4) the station address read from 2043 * the EEPROM is all zero and we have to get it from the FCode. 2044 */ 2045 if (eaddr[0] == 0 && (eaddr[1] & ~0xffff) == 0) 2046 OF_getetheraddr(dev, (caddr_t)&eaddr); 2047 #endif 2048 break; 2049 case DC_TYPE_21143: 2050 case DC_TYPE_ASIX: 2051 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2052 break; 2053 case DC_TYPE_AL981: 2054 case DC_TYPE_AN985: 2055 eaddr[0] = CSR_READ_4(sc, DC_AL_PAR0); 2056 eaddr[1] = CSR_READ_4(sc, DC_AL_PAR1); 2057 break; 2058 case DC_TYPE_CONEXANT: 2059 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 2060 ETHER_ADDR_LEN); 2061 break; 2062 case DC_TYPE_XIRCOM: 2063 /* The MAC comes from the CIS. */ 2064 mac = pci_get_ether(dev); 2065 if (!mac) { 2066 device_printf(dev, "No station address in CIS!\n"); 2067 error = ENXIO; 2068 goto fail; 2069 } 2070 bcopy(mac, eaddr, ETHER_ADDR_LEN); 2071 break; 2072 default: 2073 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2074 break; 2075 } 2076 2077 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */ 2078 error = bus_dma_tag_create(bus_get_dma_tag(dev), PAGE_SIZE, 0, 2079 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 2080 sizeof(struct dc_list_data), 1, sizeof(struct dc_list_data), 2081 0, NULL, NULL, &sc->dc_ltag); 2082 if (error) { 2083 device_printf(dev, "failed to allocate busdma tag\n"); 2084 error = ENXIO; 2085 goto fail; 2086 } 2087 error = bus_dmamem_alloc(sc->dc_ltag, (void **)&sc->dc_ldata, 2088 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->dc_lmap); 2089 if (error) { 2090 device_printf(dev, "failed to allocate DMA safe memory\n"); 2091 error = ENXIO; 2092 goto fail; 2093 } 2094 error = bus_dmamap_load(sc->dc_ltag, sc->dc_lmap, sc->dc_ldata, 2095 sizeof(struct dc_list_data), dc_dma_map_addr, &sc->dc_laddr, 2096 BUS_DMA_NOWAIT); 2097 if (error) { 2098 device_printf(dev, "cannot get address of the descriptors\n"); 2099 error = ENXIO; 2100 goto fail; 2101 } 2102 2103 /* 2104 * Allocate a busdma tag and DMA safe memory for the multicast 2105 * setup frame. 2106 */ 2107 error = bus_dma_tag_create(bus_get_dma_tag(dev), PAGE_SIZE, 0, 2108 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 2109 DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1, DC_SFRAME_LEN + DC_MIN_FRAMELEN, 2110 0, NULL, NULL, &sc->dc_stag); 2111 if (error) { 2112 device_printf(dev, "failed to allocate busdma tag\n"); 2113 error = ENXIO; 2114 goto fail; 2115 } 2116 error = bus_dmamem_alloc(sc->dc_stag, (void **)&sc->dc_cdata.dc_sbuf, 2117 BUS_DMA_NOWAIT, &sc->dc_smap); 2118 if (error) { 2119 device_printf(dev, "failed to allocate DMA safe memory\n"); 2120 error = ENXIO; 2121 goto fail; 2122 } 2123 error = bus_dmamap_load(sc->dc_stag, sc->dc_smap, sc->dc_cdata.dc_sbuf, 2124 DC_SFRAME_LEN, dc_dma_map_addr, &sc->dc_saddr, BUS_DMA_NOWAIT); 2125 if (error) { 2126 device_printf(dev, "cannot get address of the descriptors\n"); 2127 error = ENXIO; 2128 goto fail; 2129 } 2130 2131 /* Allocate a busdma tag for mbufs. */ 2132 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 2133 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 2134 MCLBYTES * DC_MAXFRAGS, DC_MAXFRAGS, MCLBYTES, 2135 0, NULL, NULL, &sc->dc_mtag); 2136 if (error) { 2137 device_printf(dev, "failed to allocate busdma tag\n"); 2138 error = ENXIO; 2139 goto fail; 2140 } 2141 2142 /* Create the TX/RX busdma maps. */ 2143 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2144 error = bus_dmamap_create(sc->dc_mtag, 0, 2145 &sc->dc_cdata.dc_tx_map[i]); 2146 if (error) { 2147 device_printf(dev, "failed to init TX ring\n"); 2148 error = ENXIO; 2149 goto fail; 2150 } 2151 } 2152 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2153 error = bus_dmamap_create(sc->dc_mtag, 0, 2154 &sc->dc_cdata.dc_rx_map[i]); 2155 if (error) { 2156 device_printf(dev, "failed to init RX ring\n"); 2157 error = ENXIO; 2158 goto fail; 2159 } 2160 } 2161 error = bus_dmamap_create(sc->dc_mtag, 0, &sc->dc_sparemap); 2162 if (error) { 2163 device_printf(dev, "failed to init RX ring\n"); 2164 error = ENXIO; 2165 goto fail; 2166 } 2167 2168 ifp = sc->dc_ifp = if_alloc(IFT_ETHER); 2169 if (ifp == NULL) { 2170 device_printf(dev, "can not if_alloc()\n"); 2171 error = ENOSPC; 2172 goto fail; 2173 } 2174 ifp->if_softc = sc; 2175 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2176 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2177 ifp->if_ioctl = dc_ioctl; 2178 ifp->if_start = dc_start; 2179 ifp->if_init = dc_init; 2180 IFQ_SET_MAXLEN(&ifp->if_snd, DC_TX_LIST_CNT - 1); 2181 ifp->if_snd.ifq_drv_maxlen = DC_TX_LIST_CNT - 1; 2182 IFQ_SET_READY(&ifp->if_snd); 2183 2184 /* 2185 * Do MII setup. If this is a 21143, check for a PHY on the 2186 * MII bus after applying any necessary fixups to twiddle the 2187 * GPIO bits. If we don't end up finding a PHY, restore the 2188 * old selection (SIA only or SIA/SYM) and attach the dcphy 2189 * driver instead. 2190 */ 2191 if (DC_IS_INTEL(sc)) { 2192 dc_apply_fixup(sc, IFM_AUTO); 2193 tmp = sc->dc_pmode; 2194 sc->dc_pmode = DC_PMODE_MII; 2195 } 2196 2197 /* 2198 * Setup General Purpose port mode and data so the tulip can talk 2199 * to the MII. This needs to be done before mii_phy_probe so that 2200 * we can actually see them. 2201 */ 2202 if (DC_IS_XIRCOM(sc)) { 2203 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2204 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2205 DELAY(10); 2206 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2207 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2208 DELAY(10); 2209 } 2210 2211 error = mii_phy_probe(dev, &sc->dc_miibus, 2212 dc_ifmedia_upd, dc_ifmedia_sts); 2213 2214 if (error && DC_IS_INTEL(sc)) { 2215 sc->dc_pmode = tmp; 2216 if (sc->dc_pmode != DC_PMODE_SIA) 2217 sc->dc_pmode = DC_PMODE_SYM; 2218 sc->dc_flags |= DC_21143_NWAY; 2219 mii_phy_probe(dev, &sc->dc_miibus, 2220 dc_ifmedia_upd, dc_ifmedia_sts); 2221 /* 2222 * For non-MII cards, we need to have the 21143 2223 * drive the LEDs. Except there are some systems 2224 * like the NEC VersaPro NoteBook PC which have no 2225 * LEDs, and twiddling these bits has adverse effects 2226 * on them. (I.e. you suddenly can't get a link.) 2227 */ 2228 if (!(pci_get_subvendor(dev) == 0x1033 && 2229 pci_get_subdevice(dev) == 0x8028)) 2230 sc->dc_flags |= DC_TULIP_LEDS; 2231 error = 0; 2232 } 2233 2234 if (error) { 2235 device_printf(dev, "MII without any PHY!\n"); 2236 goto fail; 2237 } 2238 2239 if (DC_IS_ADMTEK(sc)) { 2240 /* 2241 * Set automatic TX underrun recovery for the ADMtek chips 2242 */ 2243 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); 2244 } 2245 2246 /* 2247 * Tell the upper layer(s) we support long frames. 2248 */ 2249 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2250 ifp->if_capabilities |= IFCAP_VLAN_MTU; 2251 ifp->if_capenable = ifp->if_capabilities; 2252 #ifdef DEVICE_POLLING 2253 ifp->if_capabilities |= IFCAP_POLLING; 2254 #endif 2255 2256 callout_init_mtx(&sc->dc_stat_ch, &sc->dc_mtx, 0); 2257 callout_init_mtx(&sc->dc_wdog_ch, &sc->dc_mtx, 0); 2258 2259 /* 2260 * Call MI attach routine. 2261 */ 2262 ether_ifattach(ifp, (caddr_t)eaddr); 2263 2264 /* Hook interrupt last to avoid having to lock softc */ 2265 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | INTR_MPSAFE, 2266 NULL, dc_intr, sc, &sc->dc_intrhand); 2267 2268 if (error) { 2269 device_printf(dev, "couldn't set up irq\n"); 2270 ether_ifdetach(ifp); 2271 goto fail; 2272 } 2273 2274 fail: 2275 if (error) 2276 dc_detach(dev); 2277 return (error); 2278 } 2279 2280 /* 2281 * Shutdown hardware and free up resources. This can be called any 2282 * time after the mutex has been initialized. It is called in both 2283 * the error case in attach and the normal detach case so it needs 2284 * to be careful about only freeing resources that have actually been 2285 * allocated. 2286 */ 2287 static int 2288 dc_detach(device_t dev) 2289 { 2290 struct dc_softc *sc; 2291 struct ifnet *ifp; 2292 struct dc_mediainfo *m; 2293 int i; 2294 2295 sc = device_get_softc(dev); 2296 KASSERT(mtx_initialized(&sc->dc_mtx), ("dc mutex not initialized")); 2297 2298 ifp = sc->dc_ifp; 2299 2300 #ifdef DEVICE_POLLING 2301 if (ifp->if_capenable & IFCAP_POLLING) 2302 ether_poll_deregister(ifp); 2303 #endif 2304 2305 /* These should only be active if attach succeeded */ 2306 if (device_is_attached(dev)) { 2307 DC_LOCK(sc); 2308 dc_stop(sc); 2309 DC_UNLOCK(sc); 2310 callout_drain(&sc->dc_stat_ch); 2311 callout_drain(&sc->dc_wdog_ch); 2312 ether_ifdetach(ifp); 2313 } 2314 if (sc->dc_miibus) 2315 device_delete_child(dev, sc->dc_miibus); 2316 bus_generic_detach(dev); 2317 2318 if (sc->dc_intrhand) 2319 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2320 if (sc->dc_irq) 2321 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2322 if (sc->dc_res) 2323 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2324 2325 if (ifp) 2326 if_free(ifp); 2327 2328 if (sc->dc_cdata.dc_sbuf != NULL) 2329 bus_dmamem_free(sc->dc_stag, sc->dc_cdata.dc_sbuf, sc->dc_smap); 2330 if (sc->dc_ldata != NULL) 2331 bus_dmamem_free(sc->dc_ltag, sc->dc_ldata, sc->dc_lmap); 2332 if (sc->dc_mtag) { 2333 for (i = 0; i < DC_TX_LIST_CNT; i++) 2334 if (sc->dc_cdata.dc_tx_map[i] != NULL) 2335 bus_dmamap_destroy(sc->dc_mtag, 2336 sc->dc_cdata.dc_tx_map[i]); 2337 for (i = 0; i < DC_RX_LIST_CNT; i++) 2338 if (sc->dc_cdata.dc_rx_map[i] != NULL) 2339 bus_dmamap_destroy(sc->dc_mtag, 2340 sc->dc_cdata.dc_rx_map[i]); 2341 bus_dmamap_destroy(sc->dc_mtag, sc->dc_sparemap); 2342 } 2343 if (sc->dc_stag) 2344 bus_dma_tag_destroy(sc->dc_stag); 2345 if (sc->dc_mtag) 2346 bus_dma_tag_destroy(sc->dc_mtag); 2347 if (sc->dc_ltag) 2348 bus_dma_tag_destroy(sc->dc_ltag); 2349 2350 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2351 2352 while (sc->dc_mi != NULL) { 2353 m = sc->dc_mi->dc_next; 2354 free(sc->dc_mi, M_DEVBUF); 2355 sc->dc_mi = m; 2356 } 2357 free(sc->dc_srom, M_DEVBUF); 2358 2359 mtx_destroy(&sc->dc_mtx); 2360 2361 return (0); 2362 } 2363 2364 /* 2365 * Initialize the transmit descriptors. 2366 */ 2367 static int 2368 dc_list_tx_init(struct dc_softc *sc) 2369 { 2370 struct dc_chain_data *cd; 2371 struct dc_list_data *ld; 2372 int i, nexti; 2373 2374 cd = &sc->dc_cdata; 2375 ld = sc->dc_ldata; 2376 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2377 if (i == DC_TX_LIST_CNT - 1) 2378 nexti = 0; 2379 else 2380 nexti = i + 1; 2381 ld->dc_tx_list[i].dc_next = htole32(DC_TXDESC(sc, nexti)); 2382 cd->dc_tx_chain[i] = NULL; 2383 ld->dc_tx_list[i].dc_data = 0; 2384 ld->dc_tx_list[i].dc_ctl = 0; 2385 } 2386 2387 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2388 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2389 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2390 return (0); 2391 } 2392 2393 2394 /* 2395 * Initialize the RX descriptors and allocate mbufs for them. Note that 2396 * we arrange the descriptors in a closed ring, so that the last descriptor 2397 * points back to the first. 2398 */ 2399 static int 2400 dc_list_rx_init(struct dc_softc *sc) 2401 { 2402 struct dc_chain_data *cd; 2403 struct dc_list_data *ld; 2404 int i, nexti; 2405 2406 cd = &sc->dc_cdata; 2407 ld = sc->dc_ldata; 2408 2409 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2410 if (dc_newbuf(sc, i, 1) != 0) 2411 return (ENOBUFS); 2412 if (i == DC_RX_LIST_CNT - 1) 2413 nexti = 0; 2414 else 2415 nexti = i + 1; 2416 ld->dc_rx_list[i].dc_next = htole32(DC_RXDESC(sc, nexti)); 2417 } 2418 2419 cd->dc_rx_prod = 0; 2420 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2421 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2422 return (0); 2423 } 2424 2425 /* 2426 * Initialize an RX descriptor and attach an MBUF cluster. 2427 */ 2428 static int 2429 dc_newbuf(struct dc_softc *sc, int i, int alloc) 2430 { 2431 struct mbuf *m_new; 2432 bus_dmamap_t tmp; 2433 bus_dma_segment_t segs[1]; 2434 int error, nseg; 2435 2436 if (alloc) { 2437 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2438 if (m_new == NULL) 2439 return (ENOBUFS); 2440 } else { 2441 m_new = sc->dc_cdata.dc_rx_chain[i]; 2442 m_new->m_data = m_new->m_ext.ext_buf; 2443 } 2444 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2445 m_adj(m_new, sizeof(u_int64_t)); 2446 2447 /* 2448 * If this is a PNIC chip, zero the buffer. This is part 2449 * of the workaround for the receive bug in the 82c168 and 2450 * 82c169 chips. 2451 */ 2452 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2453 bzero(mtod(m_new, char *), m_new->m_len); 2454 2455 /* No need to remap the mbuf if we're reusing it. */ 2456 if (alloc) { 2457 error = bus_dmamap_load_mbuf_sg(sc->dc_mtag, sc->dc_sparemap, 2458 m_new, segs, &nseg, 0); 2459 if (error) { 2460 m_freem(m_new); 2461 return (error); 2462 } 2463 KASSERT(nseg == 1, 2464 ("%s: wrong number of segments (%d)", __func__, nseg)); 2465 sc->dc_ldata->dc_rx_list[i].dc_data = htole32(segs->ds_addr); 2466 bus_dmamap_unload(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i]); 2467 tmp = sc->dc_cdata.dc_rx_map[i]; 2468 sc->dc_cdata.dc_rx_map[i] = sc->dc_sparemap; 2469 sc->dc_sparemap = tmp; 2470 sc->dc_cdata.dc_rx_chain[i] = m_new; 2471 } 2472 2473 sc->dc_ldata->dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN); 2474 sc->dc_ldata->dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN); 2475 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i], 2476 BUS_DMASYNC_PREREAD); 2477 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2478 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2479 return (0); 2480 } 2481 2482 /* 2483 * Grrrrr. 2484 * The PNIC chip has a terrible bug in it that manifests itself during 2485 * periods of heavy activity. The exact mode of failure if difficult to 2486 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2487 * will happen on slow machines. The bug is that sometimes instead of 2488 * uploading one complete frame during reception, it uploads what looks 2489 * like the entire contents of its FIFO memory. The frame we want is at 2490 * the end of the whole mess, but we never know exactly how much data has 2491 * been uploaded, so salvaging the frame is hard. 2492 * 2493 * There is only one way to do it reliably, and it's disgusting. 2494 * Here's what we know: 2495 * 2496 * - We know there will always be somewhere between one and three extra 2497 * descriptors uploaded. 2498 * 2499 * - We know the desired received frame will always be at the end of the 2500 * total data upload. 2501 * 2502 * - We know the size of the desired received frame because it will be 2503 * provided in the length field of the status word in the last descriptor. 2504 * 2505 * Here's what we do: 2506 * 2507 * - When we allocate buffers for the receive ring, we bzero() them. 2508 * This means that we know that the buffer contents should be all 2509 * zeros, except for data uploaded by the chip. 2510 * 2511 * - We also force the PNIC chip to upload frames that include the 2512 * ethernet CRC at the end. 2513 * 2514 * - We gather all of the bogus frame data into a single buffer. 2515 * 2516 * - We then position a pointer at the end of this buffer and scan 2517 * backwards until we encounter the first non-zero byte of data. 2518 * This is the end of the received frame. We know we will encounter 2519 * some data at the end of the frame because the CRC will always be 2520 * there, so even if the sender transmits a packet of all zeros, 2521 * we won't be fooled. 2522 * 2523 * - We know the size of the actual received frame, so we subtract 2524 * that value from the current pointer location. This brings us 2525 * to the start of the actual received packet. 2526 * 2527 * - We copy this into an mbuf and pass it on, along with the actual 2528 * frame length. 2529 * 2530 * The performance hit is tremendous, but it beats dropping frames all 2531 * the time. 2532 */ 2533 2534 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG | DC_RXSTAT_LASTFRAG) 2535 static void 2536 dc_pnic_rx_bug_war(struct dc_softc *sc, int idx) 2537 { 2538 struct dc_desc *cur_rx; 2539 struct dc_desc *c = NULL; 2540 struct mbuf *m = NULL; 2541 unsigned char *ptr; 2542 int i, total_len; 2543 u_int32_t rxstat = 0; 2544 2545 i = sc->dc_pnic_rx_bug_save; 2546 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2547 ptr = sc->dc_pnic_rx_buf; 2548 bzero(ptr, DC_RXLEN * 5); 2549 2550 /* Copy all the bytes from the bogus buffers. */ 2551 while (1) { 2552 c = &sc->dc_ldata->dc_rx_list[i]; 2553 rxstat = le32toh(c->dc_status); 2554 m = sc->dc_cdata.dc_rx_chain[i]; 2555 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2556 ptr += DC_RXLEN; 2557 /* If this is the last buffer, break out. */ 2558 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2559 break; 2560 dc_newbuf(sc, i, 0); 2561 DC_INC(i, DC_RX_LIST_CNT); 2562 } 2563 2564 /* Find the length of the actual receive frame. */ 2565 total_len = DC_RXBYTES(rxstat); 2566 2567 /* Scan backwards until we hit a non-zero byte. */ 2568 while (*ptr == 0x00) 2569 ptr--; 2570 2571 /* Round off. */ 2572 if ((uintptr_t)(ptr) & 0x3) 2573 ptr -= 1; 2574 2575 /* Now find the start of the frame. */ 2576 ptr -= total_len; 2577 if (ptr < sc->dc_pnic_rx_buf) 2578 ptr = sc->dc_pnic_rx_buf; 2579 2580 /* 2581 * Now copy the salvaged frame to the last mbuf and fake up 2582 * the status word to make it look like a successful 2583 * frame reception. 2584 */ 2585 dc_newbuf(sc, i, 0); 2586 bcopy(ptr, mtod(m, char *), total_len); 2587 cur_rx->dc_status = htole32(rxstat | DC_RXSTAT_FIRSTFRAG); 2588 } 2589 2590 /* 2591 * This routine searches the RX ring for dirty descriptors in the 2592 * event that the rxeof routine falls out of sync with the chip's 2593 * current descriptor pointer. This may happen sometimes as a result 2594 * of a "no RX buffer available" condition that happens when the chip 2595 * consumes all of the RX buffers before the driver has a chance to 2596 * process the RX ring. This routine may need to be called more than 2597 * once to bring the driver back in sync with the chip, however we 2598 * should still be getting RX DONE interrupts to drive the search 2599 * for new packets in the RX ring, so we should catch up eventually. 2600 */ 2601 static int 2602 dc_rx_resync(struct dc_softc *sc) 2603 { 2604 struct dc_desc *cur_rx; 2605 int i, pos; 2606 2607 pos = sc->dc_cdata.dc_rx_prod; 2608 2609 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2610 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2611 if (!(le32toh(cur_rx->dc_status) & DC_RXSTAT_OWN)) 2612 break; 2613 DC_INC(pos, DC_RX_LIST_CNT); 2614 } 2615 2616 /* If the ring really is empty, then just return. */ 2617 if (i == DC_RX_LIST_CNT) 2618 return (0); 2619 2620 /* We've fallen behing the chip: catch it. */ 2621 sc->dc_cdata.dc_rx_prod = pos; 2622 2623 return (EAGAIN); 2624 } 2625 2626 /* 2627 * A frame has been uploaded: pass the resulting mbuf chain up to 2628 * the higher level protocols. 2629 */ 2630 static void 2631 dc_rxeof(struct dc_softc *sc) 2632 { 2633 struct mbuf *m, *m0; 2634 struct ifnet *ifp; 2635 struct dc_desc *cur_rx; 2636 int i, total_len = 0; 2637 u_int32_t rxstat; 2638 2639 DC_LOCK_ASSERT(sc); 2640 2641 ifp = sc->dc_ifp; 2642 i = sc->dc_cdata.dc_rx_prod; 2643 2644 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD); 2645 while (!(le32toh(sc->dc_ldata->dc_rx_list[i].dc_status) & 2646 DC_RXSTAT_OWN)) { 2647 #ifdef DEVICE_POLLING 2648 if (ifp->if_capenable & IFCAP_POLLING) { 2649 if (sc->rxcycles <= 0) 2650 break; 2651 sc->rxcycles--; 2652 } 2653 #endif 2654 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2655 rxstat = le32toh(cur_rx->dc_status); 2656 m = sc->dc_cdata.dc_rx_chain[i]; 2657 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i], 2658 BUS_DMASYNC_POSTREAD); 2659 total_len = DC_RXBYTES(rxstat); 2660 2661 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2662 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2663 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2664 sc->dc_pnic_rx_bug_save = i; 2665 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2666 DC_INC(i, DC_RX_LIST_CNT); 2667 continue; 2668 } 2669 dc_pnic_rx_bug_war(sc, i); 2670 rxstat = le32toh(cur_rx->dc_status); 2671 total_len = DC_RXBYTES(rxstat); 2672 } 2673 } 2674 2675 /* 2676 * If an error occurs, update stats, clear the 2677 * status word and leave the mbuf cluster in place: 2678 * it should simply get re-used next time this descriptor 2679 * comes up in the ring. However, don't report long 2680 * frames as errors since they could be vlans. 2681 */ 2682 if ((rxstat & DC_RXSTAT_RXERR)) { 2683 if (!(rxstat & DC_RXSTAT_GIANT) || 2684 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2685 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2686 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2687 ifp->if_ierrors++; 2688 if (rxstat & DC_RXSTAT_COLLSEEN) 2689 ifp->if_collisions++; 2690 dc_newbuf(sc, i, 0); 2691 if (rxstat & DC_RXSTAT_CRCERR) { 2692 DC_INC(i, DC_RX_LIST_CNT); 2693 continue; 2694 } else { 2695 dc_init_locked(sc); 2696 return; 2697 } 2698 } 2699 } 2700 2701 /* No errors; receive the packet. */ 2702 total_len -= ETHER_CRC_LEN; 2703 #ifdef __NO_STRICT_ALIGNMENT 2704 /* 2705 * On architectures without alignment problems we try to 2706 * allocate a new buffer for the receive ring, and pass up 2707 * the one where the packet is already, saving the expensive 2708 * copy done in m_devget(). 2709 * If we are on an architecture with alignment problems, or 2710 * if the allocation fails, then use m_devget and leave the 2711 * existing buffer in the receive ring. 2712 */ 2713 if (dc_newbuf(sc, i, 1) == 0) { 2714 m->m_pkthdr.rcvif = ifp; 2715 m->m_pkthdr.len = m->m_len = total_len; 2716 DC_INC(i, DC_RX_LIST_CNT); 2717 } else 2718 #endif 2719 { 2720 m0 = m_devget(mtod(m, char *), total_len, 2721 ETHER_ALIGN, ifp, NULL); 2722 dc_newbuf(sc, i, 0); 2723 DC_INC(i, DC_RX_LIST_CNT); 2724 if (m0 == NULL) { 2725 ifp->if_ierrors++; 2726 continue; 2727 } 2728 m = m0; 2729 } 2730 2731 ifp->if_ipackets++; 2732 DC_UNLOCK(sc); 2733 (*ifp->if_input)(ifp, m); 2734 DC_LOCK(sc); 2735 } 2736 2737 sc->dc_cdata.dc_rx_prod = i; 2738 } 2739 2740 /* 2741 * A frame was downloaded to the chip. It's safe for us to clean up 2742 * the list buffers. 2743 */ 2744 static void 2745 dc_txeof(struct dc_softc *sc) 2746 { 2747 struct dc_desc *cur_tx = NULL; 2748 struct ifnet *ifp; 2749 int idx; 2750 u_int32_t ctl, txstat; 2751 2752 ifp = sc->dc_ifp; 2753 2754 /* 2755 * Go through our tx list and free mbufs for those 2756 * frames that have been transmitted. 2757 */ 2758 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD); 2759 idx = sc->dc_cdata.dc_tx_cons; 2760 while (idx != sc->dc_cdata.dc_tx_prod) { 2761 2762 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2763 txstat = le32toh(cur_tx->dc_status); 2764 ctl = le32toh(cur_tx->dc_ctl); 2765 2766 if (txstat & DC_TXSTAT_OWN) 2767 break; 2768 2769 if (!(ctl & DC_TXCTL_LASTFRAG) || ctl & DC_TXCTL_SETUP) { 2770 if (ctl & DC_TXCTL_SETUP) { 2771 /* 2772 * Yes, the PNIC is so brain damaged 2773 * that it will sometimes generate a TX 2774 * underrun error while DMAing the RX 2775 * filter setup frame. If we detect this, 2776 * we have to send the setup frame again, 2777 * or else the filter won't be programmed 2778 * correctly. 2779 */ 2780 if (DC_IS_PNIC(sc)) { 2781 if (txstat & DC_TXSTAT_ERRSUM) 2782 dc_setfilt(sc); 2783 } 2784 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2785 } 2786 sc->dc_cdata.dc_tx_cnt--; 2787 DC_INC(idx, DC_TX_LIST_CNT); 2788 continue; 2789 } 2790 2791 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) { 2792 /* 2793 * XXX: Why does my Xircom taunt me so? 2794 * For some reason it likes setting the CARRLOST flag 2795 * even when the carrier is there. wtf?!? 2796 * Who knows, but Conexant chips have the 2797 * same problem. Maybe they took lessons 2798 * from Xircom. 2799 */ 2800 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2801 sc->dc_pmode == DC_PMODE_MII && 2802 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 2803 DC_TXSTAT_NOCARRIER))) 2804 txstat &= ~DC_TXSTAT_ERRSUM; 2805 } else { 2806 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2807 sc->dc_pmode == DC_PMODE_MII && 2808 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 2809 DC_TXSTAT_NOCARRIER | DC_TXSTAT_CARRLOST))) 2810 txstat &= ~DC_TXSTAT_ERRSUM; 2811 } 2812 2813 if (txstat & DC_TXSTAT_ERRSUM) { 2814 ifp->if_oerrors++; 2815 if (txstat & DC_TXSTAT_EXCESSCOLL) 2816 ifp->if_collisions++; 2817 if (txstat & DC_TXSTAT_LATECOLL) 2818 ifp->if_collisions++; 2819 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2820 dc_init_locked(sc); 2821 return; 2822 } 2823 } 2824 2825 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2826 2827 ifp->if_opackets++; 2828 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2829 bus_dmamap_sync(sc->dc_mtag, 2830 sc->dc_cdata.dc_tx_map[idx], 2831 BUS_DMASYNC_POSTWRITE); 2832 bus_dmamap_unload(sc->dc_mtag, 2833 sc->dc_cdata.dc_tx_map[idx]); 2834 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2835 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2836 } 2837 2838 sc->dc_cdata.dc_tx_cnt--; 2839 DC_INC(idx, DC_TX_LIST_CNT); 2840 } 2841 sc->dc_cdata.dc_tx_cons = idx; 2842 2843 if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt > DC_TX_LIST_RSVD) 2844 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2845 2846 if (sc->dc_cdata.dc_tx_cnt == 0) 2847 sc->dc_wdog_timer = 0; 2848 } 2849 2850 static void 2851 dc_tick(void *xsc) 2852 { 2853 struct dc_softc *sc; 2854 struct mii_data *mii; 2855 struct ifnet *ifp; 2856 u_int32_t r; 2857 2858 sc = xsc; 2859 DC_LOCK_ASSERT(sc); 2860 ifp = sc->dc_ifp; 2861 mii = device_get_softc(sc->dc_miibus); 2862 2863 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2864 if (sc->dc_flags & DC_21143_NWAY) { 2865 r = CSR_READ_4(sc, DC_10BTSTAT); 2866 if (IFM_SUBTYPE(mii->mii_media_active) == 2867 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2868 sc->dc_link = 0; 2869 mii_mediachg(mii); 2870 } 2871 if (IFM_SUBTYPE(mii->mii_media_active) == 2872 IFM_10_T && (r & DC_TSTAT_LS10)) { 2873 sc->dc_link = 0; 2874 mii_mediachg(mii); 2875 } 2876 if (sc->dc_link == 0) 2877 mii_tick(mii); 2878 } else { 2879 r = CSR_READ_4(sc, DC_ISR); 2880 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2881 sc->dc_cdata.dc_tx_cnt == 0) { 2882 mii_tick(mii); 2883 if (!(mii->mii_media_status & IFM_ACTIVE)) 2884 sc->dc_link = 0; 2885 } 2886 } 2887 } else 2888 mii_tick(mii); 2889 2890 /* 2891 * When the init routine completes, we expect to be able to send 2892 * packets right away, and in fact the network code will send a 2893 * gratuitous ARP the moment the init routine marks the interface 2894 * as running. However, even though the MAC may have been initialized, 2895 * there may be a delay of a few seconds before the PHY completes 2896 * autonegotiation and the link is brought up. Any transmissions 2897 * made during that delay will be lost. Dealing with this is tricky: 2898 * we can't just pause in the init routine while waiting for the 2899 * PHY to come ready since that would bring the whole system to 2900 * a screeching halt for several seconds. 2901 * 2902 * What we do here is prevent the TX start routine from sending 2903 * any packets until a link has been established. After the 2904 * interface has been initialized, the tick routine will poll 2905 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2906 * that time, packets will stay in the send queue, and once the 2907 * link comes up, they will be flushed out to the wire. 2908 */ 2909 if (!sc->dc_link && mii->mii_media_status & IFM_ACTIVE && 2910 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2911 sc->dc_link++; 2912 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2913 dc_start_locked(ifp); 2914 } 2915 2916 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 2917 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 2918 else 2919 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 2920 } 2921 2922 /* 2923 * A transmit underrun has occurred. Back off the transmit threshold, 2924 * or switch to store and forward mode if we have to. 2925 */ 2926 static void 2927 dc_tx_underrun(struct dc_softc *sc) 2928 { 2929 u_int32_t isr; 2930 int i; 2931 2932 if (DC_IS_DAVICOM(sc)) 2933 dc_init_locked(sc); 2934 2935 if (DC_IS_INTEL(sc)) { 2936 /* 2937 * The real 21143 requires that the transmitter be idle 2938 * in order to change the transmit threshold or store 2939 * and forward state. 2940 */ 2941 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2942 2943 for (i = 0; i < DC_TIMEOUT; i++) { 2944 isr = CSR_READ_4(sc, DC_ISR); 2945 if (isr & DC_ISR_TX_IDLE) 2946 break; 2947 DELAY(10); 2948 } 2949 if (i == DC_TIMEOUT) { 2950 device_printf(sc->dc_dev, 2951 "%s: failed to force tx to idle state\n", 2952 __func__); 2953 dc_init_locked(sc); 2954 } 2955 } 2956 2957 device_printf(sc->dc_dev, "TX underrun -- "); 2958 sc->dc_txthresh += DC_TXTHRESH_INC; 2959 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 2960 printf("using store and forward mode\n"); 2961 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2962 } else { 2963 printf("increasing TX threshold\n"); 2964 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 2965 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2966 } 2967 2968 if (DC_IS_INTEL(sc)) 2969 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2970 } 2971 2972 #ifdef DEVICE_POLLING 2973 static poll_handler_t dc_poll; 2974 2975 static void 2976 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2977 { 2978 struct dc_softc *sc = ifp->if_softc; 2979 2980 DC_LOCK(sc); 2981 2982 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 2983 DC_UNLOCK(sc); 2984 return; 2985 } 2986 2987 sc->rxcycles = count; 2988 dc_rxeof(sc); 2989 dc_txeof(sc); 2990 if (!IFQ_IS_EMPTY(&ifp->if_snd) && 2991 !(ifp->if_drv_flags & IFF_DRV_OACTIVE)) 2992 dc_start_locked(ifp); 2993 2994 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2995 u_int32_t status; 2996 2997 status = CSR_READ_4(sc, DC_ISR); 2998 status &= (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF | 2999 DC_ISR_TX_NOBUF | DC_ISR_TX_IDLE | DC_ISR_TX_UNDERRUN | 3000 DC_ISR_BUS_ERR); 3001 if (!status) { 3002 DC_UNLOCK(sc); 3003 return; 3004 } 3005 /* ack what we have */ 3006 CSR_WRITE_4(sc, DC_ISR, status); 3007 3008 if (status & (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF)) { 3009 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 3010 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 3011 3012 if (dc_rx_resync(sc)) 3013 dc_rxeof(sc); 3014 } 3015 /* restart transmit unit if necessary */ 3016 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 3017 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3018 3019 if (status & DC_ISR_TX_UNDERRUN) 3020 dc_tx_underrun(sc); 3021 3022 if (status & DC_ISR_BUS_ERR) { 3023 if_printf(ifp, "%s: bus error\n", __func__); 3024 dc_reset(sc); 3025 dc_init_locked(sc); 3026 } 3027 } 3028 DC_UNLOCK(sc); 3029 } 3030 #endif /* DEVICE_POLLING */ 3031 3032 static void 3033 dc_intr(void *arg) 3034 { 3035 struct dc_softc *sc; 3036 struct ifnet *ifp; 3037 u_int32_t status; 3038 3039 sc = arg; 3040 3041 if (sc->suspended) 3042 return; 3043 3044 if ((CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) 3045 return; 3046 3047 DC_LOCK(sc); 3048 ifp = sc->dc_ifp; 3049 #ifdef DEVICE_POLLING 3050 if (ifp->if_capenable & IFCAP_POLLING) { 3051 DC_UNLOCK(sc); 3052 return; 3053 } 3054 #endif 3055 3056 /* Suppress unwanted interrupts */ 3057 if (!(ifp->if_flags & IFF_UP)) { 3058 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 3059 dc_stop(sc); 3060 DC_UNLOCK(sc); 3061 return; 3062 } 3063 3064 /* Disable interrupts. */ 3065 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3066 3067 while (((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) && 3068 status != 0xFFFFFFFF && 3069 (ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3070 3071 CSR_WRITE_4(sc, DC_ISR, status); 3072 3073 if (status & DC_ISR_RX_OK) { 3074 int curpkts; 3075 curpkts = ifp->if_ipackets; 3076 dc_rxeof(sc); 3077 if (curpkts == ifp->if_ipackets) { 3078 while (dc_rx_resync(sc)) 3079 dc_rxeof(sc); 3080 } 3081 } 3082 3083 if (status & (DC_ISR_TX_OK | DC_ISR_TX_NOBUF)) 3084 dc_txeof(sc); 3085 3086 if (status & DC_ISR_TX_IDLE) { 3087 dc_txeof(sc); 3088 if (sc->dc_cdata.dc_tx_cnt) { 3089 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3090 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3091 } 3092 } 3093 3094 if (status & DC_ISR_TX_UNDERRUN) 3095 dc_tx_underrun(sc); 3096 3097 if ((status & DC_ISR_RX_WATDOGTIMEO) 3098 || (status & DC_ISR_RX_NOBUF)) { 3099 int curpkts; 3100 curpkts = ifp->if_ipackets; 3101 dc_rxeof(sc); 3102 if (curpkts == ifp->if_ipackets) { 3103 while (dc_rx_resync(sc)) 3104 dc_rxeof(sc); 3105 } 3106 } 3107 3108 if (status & DC_ISR_BUS_ERR) { 3109 dc_reset(sc); 3110 dc_init_locked(sc); 3111 } 3112 } 3113 3114 /* Re-enable interrupts. */ 3115 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3116 3117 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3118 dc_start_locked(ifp); 3119 3120 DC_UNLOCK(sc); 3121 } 3122 3123 /* 3124 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 3125 * pointers to the fragment pointers. 3126 */ 3127 static int 3128 dc_encap(struct dc_softc *sc, struct mbuf **m_head) 3129 { 3130 bus_dma_segment_t segs[DC_MAXFRAGS]; 3131 struct dc_desc *f; 3132 struct mbuf *m; 3133 int chainlen, cur, error, first, frag, i, idx, nseg; 3134 3135 /* 3136 * If there's no way we can send any packets, return now. 3137 */ 3138 if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt <= DC_TX_LIST_RSVD) 3139 return (ENOBUFS); 3140 3141 /* 3142 * Count the number of frags in this chain to see if 3143 * we need to m_defrag. Since the descriptor list is shared 3144 * by all packets, we'll m_defrag long chains so that they 3145 * do not use up the entire list, even if they would fit. 3146 */ 3147 chainlen = 0; 3148 for (m = *m_head; m != NULL; m = m->m_next) 3149 chainlen++; 3150 3151 m = NULL; 3152 if ((sc->dc_flags & DC_TX_COALESCE && ((*m_head)->m_next != NULL || 3153 sc->dc_flags & DC_TX_ALIGN)) || (chainlen > DC_TX_LIST_CNT / 4) || 3154 (DC_TX_LIST_CNT - (chainlen + sc->dc_cdata.dc_tx_cnt) <= 3155 DC_TX_LIST_RSVD)) { 3156 m = m_defrag(*m_head, M_DONTWAIT); 3157 if (m == NULL) { 3158 m_freem(*m_head); 3159 *m_head = NULL; 3160 return (ENOBUFS); 3161 } 3162 *m_head = m; 3163 } 3164 idx = sc->dc_cdata.dc_tx_prod; 3165 error = bus_dmamap_load_mbuf_sg(sc->dc_mtag, 3166 sc->dc_cdata.dc_tx_map[idx], *m_head, segs, &nseg, 0); 3167 if (error == EFBIG) { 3168 m = m_defrag(*m_head, M_DONTWAIT); 3169 if (m == NULL) { 3170 m_freem(*m_head); 3171 *m_head = NULL; 3172 return (ENOBUFS); 3173 } 3174 *m_head = m; 3175 error = bus_dmamap_load_mbuf_sg(sc->dc_mtag, 3176 sc->dc_cdata.dc_tx_map[idx], *m_head, segs, &nseg, 0); 3177 if (error != 0) { 3178 m_freem(*m_head); 3179 *m_head = NULL; 3180 return (error); 3181 } 3182 } else if (error != 0) 3183 return (error); 3184 KASSERT(nseg <= DC_MAXFRAGS, 3185 ("%s: wrong number of segments (%d)", __func__, nseg)); 3186 if (nseg == 0) { 3187 m_freem(*m_head); 3188 *m_head = NULL; 3189 return (EIO); 3190 } 3191 3192 first = cur = frag = sc->dc_cdata.dc_tx_prod; 3193 for (i = 0; i < nseg; i++) { 3194 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) && 3195 (frag == (DC_TX_LIST_CNT - 1)) && 3196 (first != sc->dc_cdata.dc_tx_first)) { 3197 bus_dmamap_unload(sc->dc_mtag, 3198 sc->dc_cdata.dc_tx_map[first]); 3199 m_freem(*m_head); 3200 *m_head = NULL; 3201 return (ENOBUFS); 3202 } 3203 3204 f = &sc->dc_ldata->dc_tx_list[frag]; 3205 f->dc_ctl = htole32(DC_TXCTL_TLINK | segs[i].ds_len); 3206 if (i == 0) { 3207 f->dc_status = 0; 3208 f->dc_ctl |= htole32(DC_TXCTL_FIRSTFRAG); 3209 } else 3210 f->dc_status = htole32(DC_TXSTAT_OWN); 3211 f->dc_data = htole32(segs[i].ds_addr); 3212 cur = frag; 3213 DC_INC(frag, DC_TX_LIST_CNT); 3214 } 3215 3216 sc->dc_cdata.dc_tx_prod = frag; 3217 sc->dc_cdata.dc_tx_cnt += nseg; 3218 sc->dc_cdata.dc_tx_chain[cur] = *m_head; 3219 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_LASTFRAG); 3220 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 3221 sc->dc_ldata->dc_tx_list[first].dc_ctl |= 3222 htole32(DC_TXCTL_FINT); 3223 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 3224 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3225 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 3226 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3227 sc->dc_ldata->dc_tx_list[first].dc_status = htole32(DC_TXSTAT_OWN); 3228 3229 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx], 3230 BUS_DMASYNC_PREWRITE); 3231 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 3232 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3233 return (0); 3234 } 3235 3236 static void 3237 dc_start(struct ifnet *ifp) 3238 { 3239 struct dc_softc *sc; 3240 3241 sc = ifp->if_softc; 3242 DC_LOCK(sc); 3243 dc_start_locked(ifp); 3244 DC_UNLOCK(sc); 3245 } 3246 3247 /* 3248 * Main transmit routine 3249 * To avoid having to do mbuf copies, we put pointers to the mbuf data 3250 * regions directly in the transmit lists. We also save a copy of the 3251 * pointers since the transmit list fragment pointers are physical 3252 * addresses. 3253 */ 3254 static void 3255 dc_start_locked(struct ifnet *ifp) 3256 { 3257 struct dc_softc *sc; 3258 struct mbuf *m_head = NULL; 3259 unsigned int queued = 0; 3260 int idx; 3261 3262 sc = ifp->if_softc; 3263 3264 DC_LOCK_ASSERT(sc); 3265 3266 if (!sc->dc_link && ifp->if_snd.ifq_len < 10) 3267 return; 3268 3269 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 3270 return; 3271 3272 idx = sc->dc_cdata.dc_tx_first = sc->dc_cdata.dc_tx_prod; 3273 3274 while (sc->dc_cdata.dc_tx_chain[idx] == NULL) { 3275 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 3276 if (m_head == NULL) 3277 break; 3278 3279 if (dc_encap(sc, &m_head)) { 3280 if (m_head == NULL) 3281 break; 3282 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3283 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3284 break; 3285 } 3286 idx = sc->dc_cdata.dc_tx_prod; 3287 3288 queued++; 3289 /* 3290 * If there's a BPF listener, bounce a copy of this frame 3291 * to him. 3292 */ 3293 BPF_MTAP(ifp, m_head); 3294 3295 if (sc->dc_flags & DC_TX_ONE) { 3296 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3297 break; 3298 } 3299 } 3300 3301 if (queued > 0) { 3302 /* Transmit */ 3303 if (!(sc->dc_flags & DC_TX_POLL)) 3304 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3305 3306 /* 3307 * Set a timeout in case the chip goes out to lunch. 3308 */ 3309 sc->dc_wdog_timer = 5; 3310 } 3311 } 3312 3313 static void 3314 dc_init(void *xsc) 3315 { 3316 struct dc_softc *sc = xsc; 3317 3318 DC_LOCK(sc); 3319 dc_init_locked(sc); 3320 DC_UNLOCK(sc); 3321 } 3322 3323 static void 3324 dc_init_locked(struct dc_softc *sc) 3325 { 3326 struct ifnet *ifp = sc->dc_ifp; 3327 struct mii_data *mii; 3328 3329 DC_LOCK_ASSERT(sc); 3330 3331 mii = device_get_softc(sc->dc_miibus); 3332 3333 /* 3334 * Cancel pending I/O and free all RX/TX buffers. 3335 */ 3336 dc_stop(sc); 3337 dc_reset(sc); 3338 3339 /* 3340 * Set cache alignment and burst length. 3341 */ 3342 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 3343 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3344 else 3345 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME | DC_BUSCTL_MRLE); 3346 /* 3347 * Evenly share the bus between receive and transmit process. 3348 */ 3349 if (DC_IS_INTEL(sc)) 3350 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3351 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3352 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3353 } else { 3354 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3355 } 3356 if (sc->dc_flags & DC_TX_POLL) 3357 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3358 switch(sc->dc_cachesize) { 3359 case 32: 3360 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3361 break; 3362 case 16: 3363 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3364 break; 3365 case 8: 3366 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3367 break; 3368 case 0: 3369 default: 3370 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3371 break; 3372 } 3373 3374 if (sc->dc_flags & DC_TX_STORENFWD) 3375 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3376 else { 3377 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3378 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3379 } else { 3380 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3381 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3382 } 3383 } 3384 3385 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3386 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3387 3388 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3389 /* 3390 * The app notes for the 98713 and 98715A say that 3391 * in order to have the chips operate properly, a magic 3392 * number must be written to CSR16. Macronix does not 3393 * document the meaning of these bits so there's no way 3394 * to know exactly what they do. The 98713 has a magic 3395 * number all its own; the rest all use a different one. 3396 */ 3397 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3398 if (sc->dc_type == DC_TYPE_98713) 3399 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3400 else 3401 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3402 } 3403 3404 if (DC_IS_XIRCOM(sc)) { 3405 /* 3406 * setup General Purpose Port mode and data so the tulip 3407 * can talk to the MII. 3408 */ 3409 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3410 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3411 DELAY(10); 3412 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3413 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3414 DELAY(10); 3415 } 3416 3417 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3418 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3419 3420 /* Init circular RX list. */ 3421 if (dc_list_rx_init(sc) == ENOBUFS) { 3422 device_printf(sc->dc_dev, 3423 "initialization failed: no memory for rx buffers\n"); 3424 dc_stop(sc); 3425 return; 3426 } 3427 3428 /* 3429 * Init TX descriptors. 3430 */ 3431 dc_list_tx_init(sc); 3432 3433 /* 3434 * Load the address of the RX list. 3435 */ 3436 CSR_WRITE_4(sc, DC_RXADDR, DC_RXDESC(sc, 0)); 3437 CSR_WRITE_4(sc, DC_TXADDR, DC_TXDESC(sc, 0)); 3438 3439 /* 3440 * Enable interrupts. 3441 */ 3442 #ifdef DEVICE_POLLING 3443 /* 3444 * ... but only if we are not polling, and make sure they are off in 3445 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3446 * after a reset. 3447 */ 3448 if (ifp->if_capenable & IFCAP_POLLING) 3449 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3450 else 3451 #endif 3452 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3453 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3454 3455 /* Enable transmitter. */ 3456 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3457 3458 /* 3459 * If this is an Intel 21143 and we're not using the 3460 * MII port, program the LED control pins so we get 3461 * link and activity indications. 3462 */ 3463 if (sc->dc_flags & DC_TULIP_LEDS) { 3464 CSR_WRITE_4(sc, DC_WATCHDOG, 3465 DC_WDOG_CTLWREN | DC_WDOG_LINK | DC_WDOG_ACTIVITY); 3466 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3467 } 3468 3469 /* 3470 * Load the RX/multicast filter. We do this sort of late 3471 * because the filter programming scheme on the 21143 and 3472 * some clones requires DMAing a setup frame via the TX 3473 * engine, and we need the transmitter enabled for that. 3474 */ 3475 dc_setfilt(sc); 3476 3477 /* Enable receiver. */ 3478 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3479 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3480 3481 mii_mediachg(mii); 3482 dc_setcfg(sc, sc->dc_if_media); 3483 3484 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3485 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3486 3487 /* Don't start the ticker if this is a homePNA link. */ 3488 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) 3489 sc->dc_link = 1; 3490 else { 3491 if (sc->dc_flags & DC_21143_NWAY) 3492 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3493 else 3494 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3495 } 3496 3497 sc->dc_wdog_timer = 0; 3498 callout_reset(&sc->dc_wdog_ch, hz, dc_watchdog, sc); 3499 } 3500 3501 /* 3502 * Set media options. 3503 */ 3504 static int 3505 dc_ifmedia_upd(struct ifnet *ifp) 3506 { 3507 struct dc_softc *sc; 3508 struct mii_data *mii; 3509 struct ifmedia *ifm; 3510 3511 sc = ifp->if_softc; 3512 mii = device_get_softc(sc->dc_miibus); 3513 DC_LOCK(sc); 3514 mii_mediachg(mii); 3515 ifm = &mii->mii_media; 3516 3517 if (DC_IS_DAVICOM(sc) && 3518 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) 3519 dc_setcfg(sc, ifm->ifm_media); 3520 else 3521 sc->dc_link = 0; 3522 DC_UNLOCK(sc); 3523 3524 return (0); 3525 } 3526 3527 /* 3528 * Report current media status. 3529 */ 3530 static void 3531 dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3532 { 3533 struct dc_softc *sc; 3534 struct mii_data *mii; 3535 struct ifmedia *ifm; 3536 3537 sc = ifp->if_softc; 3538 mii = device_get_softc(sc->dc_miibus); 3539 DC_LOCK(sc); 3540 mii_pollstat(mii); 3541 ifm = &mii->mii_media; 3542 if (DC_IS_DAVICOM(sc)) { 3543 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 3544 ifmr->ifm_active = ifm->ifm_media; 3545 ifmr->ifm_status = 0; 3546 DC_UNLOCK(sc); 3547 return; 3548 } 3549 } 3550 ifmr->ifm_active = mii->mii_media_active; 3551 ifmr->ifm_status = mii->mii_media_status; 3552 DC_UNLOCK(sc); 3553 } 3554 3555 static int 3556 dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3557 { 3558 struct dc_softc *sc = ifp->if_softc; 3559 struct ifreq *ifr = (struct ifreq *)data; 3560 struct mii_data *mii; 3561 int error = 0; 3562 3563 switch (command) { 3564 case SIOCSIFFLAGS: 3565 DC_LOCK(sc); 3566 if (ifp->if_flags & IFF_UP) { 3567 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) & 3568 (IFF_PROMISC | IFF_ALLMULTI); 3569 3570 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3571 if (need_setfilt) 3572 dc_setfilt(sc); 3573 } else { 3574 sc->dc_txthresh = 0; 3575 dc_init_locked(sc); 3576 } 3577 } else { 3578 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3579 dc_stop(sc); 3580 } 3581 sc->dc_if_flags = ifp->if_flags; 3582 DC_UNLOCK(sc); 3583 error = 0; 3584 break; 3585 case SIOCADDMULTI: 3586 case SIOCDELMULTI: 3587 DC_LOCK(sc); 3588 dc_setfilt(sc); 3589 DC_UNLOCK(sc); 3590 error = 0; 3591 break; 3592 case SIOCGIFMEDIA: 3593 case SIOCSIFMEDIA: 3594 mii = device_get_softc(sc->dc_miibus); 3595 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3596 break; 3597 case SIOCSIFCAP: 3598 #ifdef DEVICE_POLLING 3599 if (ifr->ifr_reqcap & IFCAP_POLLING && 3600 !(ifp->if_capenable & IFCAP_POLLING)) { 3601 error = ether_poll_register(dc_poll, ifp); 3602 if (error) 3603 return(error); 3604 DC_LOCK(sc); 3605 /* Disable interrupts */ 3606 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3607 ifp->if_capenable |= IFCAP_POLLING; 3608 DC_UNLOCK(sc); 3609 return (error); 3610 } 3611 if (!(ifr->ifr_reqcap & IFCAP_POLLING) && 3612 ifp->if_capenable & IFCAP_POLLING) { 3613 error = ether_poll_deregister(ifp); 3614 /* Enable interrupts. */ 3615 DC_LOCK(sc); 3616 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3617 ifp->if_capenable &= ~IFCAP_POLLING; 3618 DC_UNLOCK(sc); 3619 return (error); 3620 } 3621 #endif /* DEVICE_POLLING */ 3622 break; 3623 default: 3624 error = ether_ioctl(ifp, command, data); 3625 break; 3626 } 3627 3628 return (error); 3629 } 3630 3631 static void 3632 dc_watchdog(void *xsc) 3633 { 3634 struct dc_softc *sc = xsc; 3635 struct ifnet *ifp; 3636 3637 DC_LOCK_ASSERT(sc); 3638 3639 if (sc->dc_wdog_timer == 0 || --sc->dc_wdog_timer != 0) { 3640 callout_reset(&sc->dc_wdog_ch, hz, dc_watchdog, sc); 3641 return; 3642 } 3643 3644 ifp = sc->dc_ifp; 3645 ifp->if_oerrors++; 3646 device_printf(sc->dc_dev, "watchdog timeout\n"); 3647 3648 dc_stop(sc); 3649 dc_reset(sc); 3650 dc_init_locked(sc); 3651 3652 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3653 dc_start_locked(ifp); 3654 } 3655 3656 /* 3657 * Stop the adapter and free any mbufs allocated to the 3658 * RX and TX lists. 3659 */ 3660 static void 3661 dc_stop(struct dc_softc *sc) 3662 { 3663 struct ifnet *ifp; 3664 struct dc_list_data *ld; 3665 struct dc_chain_data *cd; 3666 int i; 3667 u_int32_t ctl; 3668 3669 DC_LOCK_ASSERT(sc); 3670 3671 ifp = sc->dc_ifp; 3672 ld = sc->dc_ldata; 3673 cd = &sc->dc_cdata; 3674 3675 callout_stop(&sc->dc_stat_ch); 3676 callout_stop(&sc->dc_wdog_ch); 3677 sc->dc_wdog_timer = 0; 3678 3679 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3680 3681 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)); 3682 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3683 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3684 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3685 sc->dc_link = 0; 3686 3687 /* 3688 * Free data in the RX lists. 3689 */ 3690 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3691 if (cd->dc_rx_chain[i] != NULL) { 3692 m_freem(cd->dc_rx_chain[i]); 3693 cd->dc_rx_chain[i] = NULL; 3694 } 3695 } 3696 bzero(&ld->dc_rx_list, sizeof(ld->dc_rx_list)); 3697 3698 /* 3699 * Free the TX list buffers. 3700 */ 3701 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3702 if (cd->dc_tx_chain[i] != NULL) { 3703 ctl = le32toh(ld->dc_tx_list[i].dc_ctl); 3704 if ((ctl & DC_TXCTL_SETUP) || 3705 !(ctl & DC_TXCTL_LASTFRAG)) { 3706 cd->dc_tx_chain[i] = NULL; 3707 continue; 3708 } 3709 bus_dmamap_unload(sc->dc_mtag, cd->dc_tx_map[i]); 3710 m_freem(cd->dc_tx_chain[i]); 3711 cd->dc_tx_chain[i] = NULL; 3712 } 3713 } 3714 bzero(&ld->dc_tx_list, sizeof(ld->dc_tx_list)); 3715 } 3716 3717 /* 3718 * Device suspend routine. Stop the interface and save some PCI 3719 * settings in case the BIOS doesn't restore them properly on 3720 * resume. 3721 */ 3722 static int 3723 dc_suspend(device_t dev) 3724 { 3725 struct dc_softc *sc; 3726 3727 sc = device_get_softc(dev); 3728 DC_LOCK(sc); 3729 dc_stop(sc); 3730 sc->suspended = 1; 3731 DC_UNLOCK(sc); 3732 3733 return (0); 3734 } 3735 3736 /* 3737 * Device resume routine. Restore some PCI settings in case the BIOS 3738 * doesn't, re-enable busmastering, and restart the interface if 3739 * appropriate. 3740 */ 3741 static int 3742 dc_resume(device_t dev) 3743 { 3744 struct dc_softc *sc; 3745 struct ifnet *ifp; 3746 3747 sc = device_get_softc(dev); 3748 ifp = sc->dc_ifp; 3749 3750 /* reinitialize interface if necessary */ 3751 DC_LOCK(sc); 3752 if (ifp->if_flags & IFF_UP) 3753 dc_init_locked(sc); 3754 3755 sc->suspended = 0; 3756 DC_UNLOCK(sc); 3757 3758 return (0); 3759 } 3760 3761 /* 3762 * Stop all chip I/O so that the kernel's probe routines don't 3763 * get confused by errant DMAs when rebooting. 3764 */ 3765 static int 3766 dc_shutdown(device_t dev) 3767 { 3768 struct dc_softc *sc; 3769 3770 sc = device_get_softc(dev); 3771 3772 DC_LOCK(sc); 3773 dc_stop(sc); 3774 DC_UNLOCK(sc); 3775 3776 return (0); 3777 } 3778