1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 38 * series chips and several workalikes including the following: 39 * 40 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 41 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 42 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 43 * ASIX Electronics AX88140A (www.asix.com.tw) 44 * ASIX Electronics AX88141 (www.asix.com.tw) 45 * ADMtek AL981 (www.admtek.com.tw) 46 * ADMtek AN985 (www.admtek.com.tw) 47 * Netgear FA511 (www.netgear.com) Appears to be rebadged ADMTek AN985 48 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 49 * Accton EN1217 (www.accton.com) 50 * Xircom X3201 (www.xircom.com) 51 * Abocom FE2500 52 * Conexant LANfinity (www.conexant.com) 53 * 3Com OfficeConnect 10/100B 3CSOHO100B (www.3com.com) 54 * 55 * Datasheets for the 21143 are available at developer.intel.com. 56 * Datasheets for the clone parts can be found at their respective sites. 57 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 58 * The PNIC II is essentially a Macronix 98715A chip; the only difference 59 * worth noting is that its multicast hash table is only 128 bits wide 60 * instead of 512. 61 * 62 * Written by Bill Paul <wpaul@ee.columbia.edu> 63 * Electrical Engineering Department 64 * Columbia University, New York City 65 */ 66 /* 67 * The Intel 21143 is the successor to the DEC 21140. It is basically 68 * the same as the 21140 but with a few new features. The 21143 supports 69 * three kinds of media attachments: 70 * 71 * o MII port, for 10Mbps and 100Mbps support and NWAY 72 * autonegotiation provided by an external PHY. 73 * o SYM port, for symbol mode 100Mbps support. 74 * o 10baseT port. 75 * o AUI/BNC port. 76 * 77 * The 100Mbps SYM port and 10baseT port can be used together in 78 * combination with the internal NWAY support to create a 10/100 79 * autosensing configuration. 80 * 81 * Note that not all tulip workalikes are handled in this driver: we only 82 * deal with those which are relatively well behaved. The Winbond is 83 * handled separately due to its different register offsets and the 84 * special handling needed for its various bugs. The PNIC is handled 85 * here, but I'm not thrilled about it. 86 * 87 * All of the workalike chips use some form of MII transceiver support 88 * with the exception of the Macronix chips, which also have a SYM port. 89 * The ASIX AX88140A is also documented to have a SYM port, but all 90 * the cards I've seen use an MII transceiver, probably because the 91 * AX88140A doesn't support internal NWAY. 92 */ 93 94 #include <sys/param.h> 95 #include <sys/endian.h> 96 #include <sys/systm.h> 97 #include <sys/sockio.h> 98 #include <sys/mbuf.h> 99 #include <sys/malloc.h> 100 #include <sys/kernel.h> 101 #include <sys/socket.h> 102 #include <sys/sysctl.h> 103 104 #include <net/if.h> 105 #include <net/if_arp.h> 106 #include <net/ethernet.h> 107 #include <net/if_dl.h> 108 #include <net/if_media.h> 109 #include <net/if_types.h> 110 #include <net/if_vlan_var.h> 111 112 #include <net/bpf.h> 113 114 #include <machine/bus_pio.h> 115 #include <machine/bus_memio.h> 116 #include <machine/bus.h> 117 #include <machine/resource.h> 118 #include <sys/bus.h> 119 #include <sys/rman.h> 120 121 #include <dev/mii/mii.h> 122 #include <dev/mii/miivar.h> 123 124 #include <dev/pci/pcireg.h> 125 #include <dev/pci/pcivar.h> 126 127 #define DC_USEIOSPACE 128 #ifdef __alpha__ 129 #define SRM_MEDIA 130 #endif 131 132 #include <pci/if_dcreg.h> 133 134 MODULE_DEPEND(dc, pci, 1, 1, 1); 135 MODULE_DEPEND(dc, ether, 1, 1, 1); 136 MODULE_DEPEND(dc, miibus, 1, 1, 1); 137 138 /* "controller miibus0" required. See GENERIC if you get errors here. */ 139 #include "miibus_if.h" 140 141 /* 142 * Various supported device vendors/types and their names. 143 */ 144 static struct dc_type dc_devs[] = { 145 { DC_VENDORID_DEC, DC_DEVICEID_21143, 146 "Intel 21143 10/100BaseTX" }, 147 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009, 148 "Davicom DM9009 10/100BaseTX" }, 149 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 150 "Davicom DM9100 10/100BaseTX" }, 151 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 152 "Davicom DM9102 10/100BaseTX" }, 153 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 154 "Davicom DM9102A 10/100BaseTX" }, 155 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 156 "ADMtek AL981 10/100BaseTX" }, 157 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 158 "ADMtek AN985 10/100BaseTX" }, 159 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511, 160 "ADMtek ADM9511 10/100BaseTX" }, 161 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513, 162 "ADMtek ADM9513 10/100BaseTX" }, 163 { DC_VENDORID_ADMTEK, DC_DEVICEID_FA511, 164 "Netgear FA511 10/100BaseTX" }, 165 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 166 "ASIX AX88140A 10/100BaseTX" }, 167 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 168 "ASIX AX88141 10/100BaseTX" }, 169 { DC_VENDORID_MX, DC_DEVICEID_98713, 170 "Macronix 98713 10/100BaseTX" }, 171 { DC_VENDORID_MX, DC_DEVICEID_98713, 172 "Macronix 98713A 10/100BaseTX" }, 173 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 174 "Compex RL100-TX 10/100BaseTX" }, 175 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 176 "Compex RL100-TX 10/100BaseTX" }, 177 { DC_VENDORID_MX, DC_DEVICEID_987x5, 178 "Macronix 98715/98715A 10/100BaseTX" }, 179 { DC_VENDORID_MX, DC_DEVICEID_987x5, 180 "Macronix 98715AEC-C 10/100BaseTX" }, 181 { DC_VENDORID_MX, DC_DEVICEID_987x5, 182 "Macronix 98725 10/100BaseTX" }, 183 { DC_VENDORID_MX, DC_DEVICEID_98727, 184 "Macronix 98727/98732 10/100BaseTX" }, 185 { DC_VENDORID_LO, DC_DEVICEID_82C115, 186 "LC82C115 PNIC II 10/100BaseTX" }, 187 { DC_VENDORID_LO, DC_DEVICEID_82C168, 188 "82c168 PNIC 10/100BaseTX" }, 189 { DC_VENDORID_LO, DC_DEVICEID_82C168, 190 "82c169 PNIC 10/100BaseTX" }, 191 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217, 192 "Accton EN1217 10/100BaseTX" }, 193 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242, 194 "Accton EN2242 MiniPCI 10/100BaseTX" }, 195 { DC_VENDORID_XIRCOM, DC_DEVICEID_X3201, 196 "Xircom X3201 10/100BaseTX" }, 197 { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500, 198 "Abocom FE2500 10/100BaseTX" }, 199 { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX, 200 "Abocom FE2500MX 10/100BaseTX" }, 201 { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112, 202 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 203 { DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX, 204 "Hawking CB102 CardBus 10/100" }, 205 { DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T, 206 "PlaneX FNW-3602-T CardBus 10/100" }, 207 { DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB, 208 "3Com OfficeConnect 10/100B" }, 209 { DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120, 210 "Microsoft MN-120 CardBus 10/100" }, 211 { DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130, 212 "Microsoft MN-130 10/100" }, 213 { DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130_FAKE, 214 "Microsoft MN-130 10/100" }, 215 { 0, 0, NULL } 216 }; 217 218 static int dc_probe (device_t); 219 static int dc_attach (device_t); 220 static int dc_detach (device_t); 221 static int dc_suspend (device_t); 222 static int dc_resume (device_t); 223 #ifndef BURN_BRIDGES 224 static void dc_acpi (device_t); 225 #endif 226 static struct dc_type *dc_devtype (device_t); 227 static int dc_newbuf (struct dc_softc *, int, int); 228 static int dc_encap (struct dc_softc *, struct mbuf **); 229 static void dc_pnic_rx_bug_war (struct dc_softc *, int); 230 static int dc_rx_resync (struct dc_softc *); 231 static void dc_rxeof (struct dc_softc *); 232 static void dc_txeof (struct dc_softc *); 233 static void dc_tick (void *); 234 static void dc_tx_underrun (struct dc_softc *); 235 static void dc_intr (void *); 236 static void dc_start (struct ifnet *); 237 static int dc_ioctl (struct ifnet *, u_long, caddr_t); 238 static void dc_init (void *); 239 static void dc_stop (struct dc_softc *); 240 static void dc_watchdog (struct ifnet *); 241 static void dc_shutdown (device_t); 242 static int dc_ifmedia_upd (struct ifnet *); 243 static void dc_ifmedia_sts (struct ifnet *, struct ifmediareq *); 244 245 static void dc_delay (struct dc_softc *); 246 static void dc_eeprom_idle (struct dc_softc *); 247 static void dc_eeprom_putbyte (struct dc_softc *, int); 248 static void dc_eeprom_getword (struct dc_softc *, int, u_int16_t *); 249 static void dc_eeprom_getword_pnic 250 (struct dc_softc *, int, u_int16_t *); 251 static void dc_eeprom_getword_xircom 252 (struct dc_softc *, int, u_int16_t *); 253 static void dc_eeprom_width (struct dc_softc *); 254 static void dc_read_eeprom (struct dc_softc *, caddr_t, int, int, int); 255 256 static void dc_mii_writebit (struct dc_softc *, int); 257 static int dc_mii_readbit (struct dc_softc *); 258 static void dc_mii_sync (struct dc_softc *); 259 static void dc_mii_send (struct dc_softc *, u_int32_t, int); 260 static int dc_mii_readreg (struct dc_softc *, struct dc_mii_frame *); 261 static int dc_mii_writereg (struct dc_softc *, struct dc_mii_frame *); 262 static int dc_miibus_readreg (device_t, int, int); 263 static int dc_miibus_writereg (device_t, int, int, int); 264 static void dc_miibus_statchg (device_t); 265 static void dc_miibus_mediainit (device_t); 266 267 static void dc_setcfg (struct dc_softc *, int); 268 static uint32_t dc_mchash_le (struct dc_softc *, const uint8_t *); 269 static uint32_t dc_mchash_be (const uint8_t *); 270 static void dc_setfilt_21143 (struct dc_softc *); 271 static void dc_setfilt_asix (struct dc_softc *); 272 static void dc_setfilt_admtek (struct dc_softc *); 273 static void dc_setfilt_xircom (struct dc_softc *); 274 275 static void dc_setfilt (struct dc_softc *); 276 277 static void dc_reset (struct dc_softc *); 278 static int dc_list_rx_init (struct dc_softc *); 279 static int dc_list_tx_init (struct dc_softc *); 280 281 static void dc_read_srom (struct dc_softc *, int); 282 static void dc_parse_21143_srom (struct dc_softc *); 283 static void dc_decode_leaf_sia (struct dc_softc *, struct dc_eblock_sia *); 284 static void dc_decode_leaf_mii (struct dc_softc *, struct dc_eblock_mii *); 285 static void dc_decode_leaf_sym (struct dc_softc *, struct dc_eblock_sym *); 286 static void dc_apply_fixup (struct dc_softc *, int); 287 288 static void dc_dma_map_txbuf (void *, bus_dma_segment_t *, int, bus_size_t, 289 int); 290 static void dc_dma_map_rxbuf (void *, bus_dma_segment_t *, int, bus_size_t, 291 int); 292 293 #ifdef DC_USEIOSPACE 294 #define DC_RES SYS_RES_IOPORT 295 #define DC_RID DC_PCI_CFBIO 296 #else 297 #define DC_RES SYS_RES_MEMORY 298 #define DC_RID DC_PCI_CFBMA 299 #endif 300 301 static device_method_t dc_methods[] = { 302 /* Device interface */ 303 DEVMETHOD(device_probe, dc_probe), 304 DEVMETHOD(device_attach, dc_attach), 305 DEVMETHOD(device_detach, dc_detach), 306 DEVMETHOD(device_suspend, dc_suspend), 307 DEVMETHOD(device_resume, dc_resume), 308 DEVMETHOD(device_shutdown, dc_shutdown), 309 310 /* bus interface */ 311 DEVMETHOD(bus_print_child, bus_generic_print_child), 312 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 313 314 /* MII interface */ 315 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 316 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 317 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 318 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 319 320 { 0, 0 } 321 }; 322 323 static driver_t dc_driver = { 324 "dc", 325 dc_methods, 326 sizeof(struct dc_softc) 327 }; 328 329 static devclass_t dc_devclass; 330 #ifdef __i386__ 331 static int dc_quick = 1; 332 SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW, &dc_quick, 0, 333 "do not m_devget() in dc driver"); 334 #endif 335 336 DRIVER_MODULE(dc, cardbus, dc_driver, dc_devclass, 0, 0); 337 DRIVER_MODULE(dc, pci, dc_driver, dc_devclass, 0, 0); 338 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 339 340 #define DC_SETBIT(sc, reg, x) \ 341 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 342 343 #define DC_CLRBIT(sc, reg, x) \ 344 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 345 346 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 347 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 348 349 #define IS_MPSAFE 0 350 351 static void 352 dc_delay(struct dc_softc *sc) 353 { 354 int idx; 355 356 for (idx = (300 / 33) + 1; idx > 0; idx--) 357 CSR_READ_4(sc, DC_BUSCTL); 358 } 359 360 static void 361 dc_eeprom_width(struct dc_softc *sc) 362 { 363 int i; 364 365 /* Force EEPROM to idle state. */ 366 dc_eeprom_idle(sc); 367 368 /* Enter EEPROM access mode. */ 369 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 370 dc_delay(sc); 371 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 372 dc_delay(sc); 373 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 374 dc_delay(sc); 375 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 376 dc_delay(sc); 377 378 for (i = 3; i--;) { 379 if (6 & (1 << i)) 380 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 381 else 382 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 383 dc_delay(sc); 384 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 385 dc_delay(sc); 386 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 387 dc_delay(sc); 388 } 389 390 for (i = 1; i <= 12; i++) { 391 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 392 dc_delay(sc); 393 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { 394 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 395 dc_delay(sc); 396 break; 397 } 398 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 399 dc_delay(sc); 400 } 401 402 /* Turn off EEPROM access mode. */ 403 dc_eeprom_idle(sc); 404 405 if (i < 4 || i > 12) 406 sc->dc_romwidth = 6; 407 else 408 sc->dc_romwidth = i; 409 410 /* Enter EEPROM access mode. */ 411 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 412 dc_delay(sc); 413 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 414 dc_delay(sc); 415 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 416 dc_delay(sc); 417 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 418 dc_delay(sc); 419 420 /* Turn off EEPROM access mode. */ 421 dc_eeprom_idle(sc); 422 } 423 424 static void 425 dc_eeprom_idle(struct dc_softc *sc) 426 { 427 int i; 428 429 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 430 dc_delay(sc); 431 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 432 dc_delay(sc); 433 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 434 dc_delay(sc); 435 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 436 dc_delay(sc); 437 438 for (i = 0; i < 25; i++) { 439 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 440 dc_delay(sc); 441 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 442 dc_delay(sc); 443 } 444 445 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 446 dc_delay(sc); 447 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 448 dc_delay(sc); 449 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 450 } 451 452 /* 453 * Send a read command and address to the EEPROM, check for ACK. 454 */ 455 static void 456 dc_eeprom_putbyte(struct dc_softc *sc, int addr) 457 { 458 int d, i; 459 460 d = DC_EECMD_READ >> 6; 461 for (i = 3; i--; ) { 462 if (d & (1 << i)) 463 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 464 else 465 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 466 dc_delay(sc); 467 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 468 dc_delay(sc); 469 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 470 dc_delay(sc); 471 } 472 473 /* 474 * Feed in each bit and strobe the clock. 475 */ 476 for (i = sc->dc_romwidth; i--;) { 477 if (addr & (1 << i)) { 478 SIO_SET(DC_SIO_EE_DATAIN); 479 } else { 480 SIO_CLR(DC_SIO_EE_DATAIN); 481 } 482 dc_delay(sc); 483 SIO_SET(DC_SIO_EE_CLK); 484 dc_delay(sc); 485 SIO_CLR(DC_SIO_EE_CLK); 486 dc_delay(sc); 487 } 488 } 489 490 /* 491 * Read a word of data stored in the EEPROM at address 'addr.' 492 * The PNIC 82c168/82c169 has its own non-standard way to read 493 * the EEPROM. 494 */ 495 static void 496 dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, u_int16_t *dest) 497 { 498 int i; 499 u_int32_t r; 500 501 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr); 502 503 for (i = 0; i < DC_TIMEOUT; i++) { 504 DELAY(1); 505 r = CSR_READ_4(sc, DC_SIO); 506 if (!(r & DC_PN_SIOCTL_BUSY)) { 507 *dest = (u_int16_t)(r & 0xFFFF); 508 return; 509 } 510 } 511 } 512 513 /* 514 * Read a word of data stored in the EEPROM at address 'addr.' 515 * The Xircom X3201 has its own non-standard way to read 516 * the EEPROM, too. 517 */ 518 static void 519 dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, u_int16_t *dest) 520 { 521 522 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 523 524 addr *= 2; 525 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 526 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff; 527 addr += 1; 528 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 529 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8; 530 531 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 532 } 533 534 /* 535 * Read a word of data stored in the EEPROM at address 'addr.' 536 */ 537 static void 538 dc_eeprom_getword(struct dc_softc *sc, int addr, u_int16_t *dest) 539 { 540 int i; 541 u_int16_t word = 0; 542 543 /* Force EEPROM to idle state. */ 544 dc_eeprom_idle(sc); 545 546 /* Enter EEPROM access mode. */ 547 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 548 dc_delay(sc); 549 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 550 dc_delay(sc); 551 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 552 dc_delay(sc); 553 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 554 dc_delay(sc); 555 556 /* 557 * Send address of word we want to read. 558 */ 559 dc_eeprom_putbyte(sc, addr); 560 561 /* 562 * Start reading bits from EEPROM. 563 */ 564 for (i = 0x8000; i; i >>= 1) { 565 SIO_SET(DC_SIO_EE_CLK); 566 dc_delay(sc); 567 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 568 word |= i; 569 dc_delay(sc); 570 SIO_CLR(DC_SIO_EE_CLK); 571 dc_delay(sc); 572 } 573 574 /* Turn off EEPROM access mode. */ 575 dc_eeprom_idle(sc); 576 577 *dest = word; 578 } 579 580 /* 581 * Read a sequence of words from the EEPROM. 582 */ 583 static void 584 dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int swap) 585 { 586 int i; 587 u_int16_t word = 0, *ptr; 588 589 for (i = 0; i < cnt; i++) { 590 if (DC_IS_PNIC(sc)) 591 dc_eeprom_getword_pnic(sc, off + i, &word); 592 else if (DC_IS_XIRCOM(sc)) 593 dc_eeprom_getword_xircom(sc, off + i, &word); 594 else 595 dc_eeprom_getword(sc, off + i, &word); 596 ptr = (u_int16_t *)(dest + (i * 2)); 597 if (swap) 598 *ptr = ntohs(word); 599 else 600 *ptr = word; 601 } 602 } 603 604 /* 605 * The following two routines are taken from the Macronix 98713 606 * Application Notes pp.19-21. 607 */ 608 /* 609 * Write a bit to the MII bus. 610 */ 611 static void 612 dc_mii_writebit(struct dc_softc *sc, int bit) 613 { 614 615 if (bit) 616 CSR_WRITE_4(sc, DC_SIO, 617 DC_SIO_ROMCTL_WRITE | DC_SIO_MII_DATAOUT); 618 else 619 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 620 621 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 622 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 623 } 624 625 /* 626 * Read a bit from the MII bus. 627 */ 628 static int 629 dc_mii_readbit(struct dc_softc *sc) 630 { 631 632 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ | DC_SIO_MII_DIR); 633 CSR_READ_4(sc, DC_SIO); 634 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 635 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 636 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 637 return (1); 638 639 return (0); 640 } 641 642 /* 643 * Sync the PHYs by setting data bit and strobing the clock 32 times. 644 */ 645 static void 646 dc_mii_sync(struct dc_softc *sc) 647 { 648 int i; 649 650 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 651 652 for (i = 0; i < 32; i++) 653 dc_mii_writebit(sc, 1); 654 } 655 656 /* 657 * Clock a series of bits through the MII. 658 */ 659 static void 660 dc_mii_send(struct dc_softc *sc, u_int32_t bits, int cnt) 661 { 662 int i; 663 664 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 665 dc_mii_writebit(sc, bits & i); 666 } 667 668 /* 669 * Read an PHY register through the MII. 670 */ 671 static int 672 dc_mii_readreg(struct dc_softc *sc, struct dc_mii_frame *frame) 673 { 674 int i, ack; 675 676 DC_LOCK(sc); 677 678 /* 679 * Set up frame for RX. 680 */ 681 frame->mii_stdelim = DC_MII_STARTDELIM; 682 frame->mii_opcode = DC_MII_READOP; 683 frame->mii_turnaround = 0; 684 frame->mii_data = 0; 685 686 /* 687 * Sync the PHYs. 688 */ 689 dc_mii_sync(sc); 690 691 /* 692 * Send command/address info. 693 */ 694 dc_mii_send(sc, frame->mii_stdelim, 2); 695 dc_mii_send(sc, frame->mii_opcode, 2); 696 dc_mii_send(sc, frame->mii_phyaddr, 5); 697 dc_mii_send(sc, frame->mii_regaddr, 5); 698 699 #ifdef notdef 700 /* Idle bit */ 701 dc_mii_writebit(sc, 1); 702 dc_mii_writebit(sc, 0); 703 #endif 704 705 /* Check for ack. */ 706 ack = dc_mii_readbit(sc); 707 708 /* 709 * Now try reading data bits. If the ack failed, we still 710 * need to clock through 16 cycles to keep the PHY(s) in sync. 711 */ 712 if (ack) { 713 for (i = 0; i < 16; i++) 714 dc_mii_readbit(sc); 715 goto fail; 716 } 717 718 for (i = 0x8000; i; i >>= 1) { 719 if (!ack) { 720 if (dc_mii_readbit(sc)) 721 frame->mii_data |= i; 722 } 723 } 724 725 fail: 726 727 dc_mii_writebit(sc, 0); 728 dc_mii_writebit(sc, 0); 729 730 DC_UNLOCK(sc); 731 732 if (ack) 733 return (1); 734 return (0); 735 } 736 737 /* 738 * Write to a PHY register through the MII. 739 */ 740 static int 741 dc_mii_writereg(struct dc_softc *sc, struct dc_mii_frame *frame) 742 { 743 744 DC_LOCK(sc); 745 /* 746 * Set up frame for TX. 747 */ 748 749 frame->mii_stdelim = DC_MII_STARTDELIM; 750 frame->mii_opcode = DC_MII_WRITEOP; 751 frame->mii_turnaround = DC_MII_TURNAROUND; 752 753 /* 754 * Sync the PHYs. 755 */ 756 dc_mii_sync(sc); 757 758 dc_mii_send(sc, frame->mii_stdelim, 2); 759 dc_mii_send(sc, frame->mii_opcode, 2); 760 dc_mii_send(sc, frame->mii_phyaddr, 5); 761 dc_mii_send(sc, frame->mii_regaddr, 5); 762 dc_mii_send(sc, frame->mii_turnaround, 2); 763 dc_mii_send(sc, frame->mii_data, 16); 764 765 /* Idle bit. */ 766 dc_mii_writebit(sc, 0); 767 dc_mii_writebit(sc, 0); 768 769 DC_UNLOCK(sc); 770 771 return (0); 772 } 773 774 static int 775 dc_miibus_readreg(device_t dev, int phy, int reg) 776 { 777 struct dc_mii_frame frame; 778 struct dc_softc *sc; 779 int i, rval, phy_reg = 0; 780 781 sc = device_get_softc(dev); 782 bzero(&frame, sizeof(frame)); 783 784 /* 785 * Note: both the AL981 and AN985 have internal PHYs, 786 * however the AL981 provides direct access to the PHY 787 * registers while the AN985 uses a serial MII interface. 788 * The AN985's MII interface is also buggy in that you 789 * can read from any MII address (0 to 31), but only address 1 790 * behaves normally. To deal with both cases, we pretend 791 * that the PHY is at MII address 1. 792 */ 793 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 794 return (0); 795 796 /* 797 * Note: the ukphy probes of the RS7112 report a PHY at 798 * MII address 0 (possibly HomePNA?) and 1 (ethernet) 799 * so we only respond to correct one. 800 */ 801 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 802 return (0); 803 804 if (sc->dc_pmode != DC_PMODE_MII) { 805 if (phy == (MII_NPHY - 1)) { 806 switch (reg) { 807 case MII_BMSR: 808 /* 809 * Fake something to make the probe 810 * code think there's a PHY here. 811 */ 812 return (BMSR_MEDIAMASK); 813 break; 814 case MII_PHYIDR1: 815 if (DC_IS_PNIC(sc)) 816 return (DC_VENDORID_LO); 817 return (DC_VENDORID_DEC); 818 break; 819 case MII_PHYIDR2: 820 if (DC_IS_PNIC(sc)) 821 return (DC_DEVICEID_82C168); 822 return (DC_DEVICEID_21143); 823 break; 824 default: 825 return (0); 826 break; 827 } 828 } else 829 return (0); 830 } 831 832 if (DC_IS_PNIC(sc)) { 833 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 834 (phy << 23) | (reg << 18)); 835 for (i = 0; i < DC_TIMEOUT; i++) { 836 DELAY(1); 837 rval = CSR_READ_4(sc, DC_PN_MII); 838 if (!(rval & DC_PN_MII_BUSY)) { 839 rval &= 0xFFFF; 840 return (rval == 0xFFFF ? 0 : rval); 841 } 842 } 843 return (0); 844 } 845 846 if (DC_IS_COMET(sc)) { 847 switch (reg) { 848 case MII_BMCR: 849 phy_reg = DC_AL_BMCR; 850 break; 851 case MII_BMSR: 852 phy_reg = DC_AL_BMSR; 853 break; 854 case MII_PHYIDR1: 855 phy_reg = DC_AL_VENID; 856 break; 857 case MII_PHYIDR2: 858 phy_reg = DC_AL_DEVID; 859 break; 860 case MII_ANAR: 861 phy_reg = DC_AL_ANAR; 862 break; 863 case MII_ANLPAR: 864 phy_reg = DC_AL_LPAR; 865 break; 866 case MII_ANER: 867 phy_reg = DC_AL_ANER; 868 break; 869 default: 870 printf("dc%d: phy_read: bad phy register %x\n", 871 sc->dc_unit, reg); 872 return (0); 873 break; 874 } 875 876 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 877 878 if (rval == 0xFFFF) 879 return (0); 880 return (rval); 881 } 882 883 frame.mii_phyaddr = phy; 884 frame.mii_regaddr = reg; 885 if (sc->dc_type == DC_TYPE_98713) { 886 phy_reg = CSR_READ_4(sc, DC_NETCFG); 887 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 888 } 889 dc_mii_readreg(sc, &frame); 890 if (sc->dc_type == DC_TYPE_98713) 891 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 892 893 return (frame.mii_data); 894 } 895 896 static int 897 dc_miibus_writereg(device_t dev, int phy, int reg, int data) 898 { 899 struct dc_softc *sc; 900 struct dc_mii_frame frame; 901 int i, phy_reg = 0; 902 903 sc = device_get_softc(dev); 904 bzero(&frame, sizeof(frame)); 905 906 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 907 return (0); 908 909 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 910 return (0); 911 912 if (DC_IS_PNIC(sc)) { 913 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 914 (phy << 23) | (reg << 10) | data); 915 for (i = 0; i < DC_TIMEOUT; i++) { 916 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 917 break; 918 } 919 return (0); 920 } 921 922 if (DC_IS_COMET(sc)) { 923 switch (reg) { 924 case MII_BMCR: 925 phy_reg = DC_AL_BMCR; 926 break; 927 case MII_BMSR: 928 phy_reg = DC_AL_BMSR; 929 break; 930 case MII_PHYIDR1: 931 phy_reg = DC_AL_VENID; 932 break; 933 case MII_PHYIDR2: 934 phy_reg = DC_AL_DEVID; 935 break; 936 case MII_ANAR: 937 phy_reg = DC_AL_ANAR; 938 break; 939 case MII_ANLPAR: 940 phy_reg = DC_AL_LPAR; 941 break; 942 case MII_ANER: 943 phy_reg = DC_AL_ANER; 944 break; 945 default: 946 printf("dc%d: phy_write: bad phy register %x\n", 947 sc->dc_unit, reg); 948 return (0); 949 break; 950 } 951 952 CSR_WRITE_4(sc, phy_reg, data); 953 return (0); 954 } 955 956 frame.mii_phyaddr = phy; 957 frame.mii_regaddr = reg; 958 frame.mii_data = data; 959 960 if (sc->dc_type == DC_TYPE_98713) { 961 phy_reg = CSR_READ_4(sc, DC_NETCFG); 962 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 963 } 964 dc_mii_writereg(sc, &frame); 965 if (sc->dc_type == DC_TYPE_98713) 966 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 967 968 return (0); 969 } 970 971 static void 972 dc_miibus_statchg(device_t dev) 973 { 974 struct dc_softc *sc; 975 struct mii_data *mii; 976 struct ifmedia *ifm; 977 978 sc = device_get_softc(dev); 979 if (DC_IS_ADMTEK(sc)) 980 return; 981 982 mii = device_get_softc(sc->dc_miibus); 983 ifm = &mii->mii_media; 984 if (DC_IS_DAVICOM(sc) && 985 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 986 dc_setcfg(sc, ifm->ifm_media); 987 sc->dc_if_media = ifm->ifm_media; 988 } else { 989 dc_setcfg(sc, mii->mii_media_active); 990 sc->dc_if_media = mii->mii_media_active; 991 } 992 } 993 994 /* 995 * Special support for DM9102A cards with HomePNA PHYs. Note: 996 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 997 * to be impossible to talk to the management interface of the DM9801 998 * PHY (its MDIO pin is not connected to anything). Consequently, 999 * the driver has to just 'know' about the additional mode and deal 1000 * with it itself. *sigh* 1001 */ 1002 static void 1003 dc_miibus_mediainit(device_t dev) 1004 { 1005 struct dc_softc *sc; 1006 struct mii_data *mii; 1007 struct ifmedia *ifm; 1008 int rev; 1009 1010 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1011 1012 sc = device_get_softc(dev); 1013 mii = device_get_softc(sc->dc_miibus); 1014 ifm = &mii->mii_media; 1015 1016 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 1017 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL); 1018 } 1019 1020 #define DC_POLY 0xEDB88320 1021 #define DC_BITS_512 9 1022 #define DC_BITS_128 7 1023 #define DC_BITS_64 6 1024 1025 static uint32_t 1026 dc_mchash_le(struct dc_softc *sc, const uint8_t *addr) 1027 { 1028 uint32_t crc; 1029 int idx, bit; 1030 uint8_t data; 1031 1032 /* Compute CRC for the address value. */ 1033 crc = 0xFFFFFFFF; /* initial value */ 1034 1035 for (idx = 0; idx < 6; idx++) { 1036 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 1037 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 1038 } 1039 1040 /* 1041 * The hash table on the PNIC II and the MX98715AEC-C/D/E 1042 * chips is only 128 bits wide. 1043 */ 1044 if (sc->dc_flags & DC_128BIT_HASH) 1045 return (crc & ((1 << DC_BITS_128) - 1)); 1046 1047 /* The hash table on the MX98715BEC is only 64 bits wide. */ 1048 if (sc->dc_flags & DC_64BIT_HASH) 1049 return (crc & ((1 << DC_BITS_64) - 1)); 1050 1051 /* Xircom's hash filtering table is different (read: weird) */ 1052 /* Xircom uses the LEAST significant bits */ 1053 if (DC_IS_XIRCOM(sc)) { 1054 if ((crc & 0x180) == 0x180) 1055 return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4)); 1056 else 1057 return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 + 1058 (12 << 4)); 1059 } 1060 1061 return (crc & ((1 << DC_BITS_512) - 1)); 1062 } 1063 1064 /* 1065 * Calculate CRC of a multicast group address, return the lower 6 bits. 1066 */ 1067 static uint32_t 1068 dc_mchash_be(const uint8_t *addr) 1069 { 1070 uint32_t crc, carry; 1071 int idx, bit; 1072 uint8_t data; 1073 1074 /* Compute CRC for the address value. */ 1075 crc = 0xFFFFFFFF; /* initial value */ 1076 1077 for (idx = 0; idx < 6; idx++) { 1078 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) { 1079 carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01); 1080 data >>= 1; 1081 crc <<= 1; 1082 if (carry) 1083 crc = (crc ^ 0x04c11db6) | carry; 1084 } 1085 } 1086 1087 /* Return the filter bit position. */ 1088 return ((crc >> 26) & 0x0000003F); 1089 } 1090 1091 /* 1092 * 21143-style RX filter setup routine. Filter programming is done by 1093 * downloading a special setup frame into the TX engine. 21143, Macronix, 1094 * PNIC, PNIC II and Davicom chips are programmed this way. 1095 * 1096 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1097 * address (our node address) and a 512-bit hash filter for multicast 1098 * frames. We also sneak the broadcast address into the hash filter since 1099 * we need that too. 1100 */ 1101 static void 1102 dc_setfilt_21143(struct dc_softc *sc) 1103 { 1104 struct dc_desc *sframe; 1105 u_int32_t h, *sp; 1106 struct ifmultiaddr *ifma; 1107 struct ifnet *ifp; 1108 int i; 1109 1110 ifp = &sc->arpcom.ac_if; 1111 1112 i = sc->dc_cdata.dc_tx_prod; 1113 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1114 sc->dc_cdata.dc_tx_cnt++; 1115 sframe = &sc->dc_ldata->dc_tx_list[i]; 1116 sp = sc->dc_cdata.dc_sbuf; 1117 bzero(sp, DC_SFRAME_LEN); 1118 1119 sframe->dc_data = htole32(sc->dc_saddr); 1120 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1121 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1122 1123 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1124 1125 /* If we want promiscuous mode, set the allframes bit. */ 1126 if (ifp->if_flags & IFF_PROMISC) 1127 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1128 else 1129 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1130 1131 if (ifp->if_flags & IFF_ALLMULTI) 1132 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1133 else 1134 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1135 1136 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1137 if (ifma->ifma_addr->sa_family != AF_LINK) 1138 continue; 1139 h = dc_mchash_le(sc, 1140 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1141 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1142 } 1143 1144 if (ifp->if_flags & IFF_BROADCAST) { 1145 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1146 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1147 } 1148 1149 /* Set our MAC address */ 1150 sp[39] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1151 sp[40] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1152 sp[41] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1153 1154 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1155 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1156 1157 /* 1158 * The PNIC takes an exceedingly long time to process its 1159 * setup frame; wait 10ms after posting the setup frame 1160 * before proceeding, just so it has time to swallow its 1161 * medicine. 1162 */ 1163 DELAY(10000); 1164 1165 ifp->if_timer = 5; 1166 } 1167 1168 static void 1169 dc_setfilt_admtek(struct dc_softc *sc) 1170 { 1171 struct ifnet *ifp; 1172 struct ifmultiaddr *ifma; 1173 int h = 0; 1174 u_int32_t hashes[2] = { 0, 0 }; 1175 1176 ifp = &sc->arpcom.ac_if; 1177 1178 /* Init our MAC address. */ 1179 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1180 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1181 1182 /* If we want promiscuous mode, set the allframes bit. */ 1183 if (ifp->if_flags & IFF_PROMISC) 1184 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1185 else 1186 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1187 1188 if (ifp->if_flags & IFF_ALLMULTI) 1189 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1190 else 1191 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1192 1193 /* First, zot all the existing hash bits. */ 1194 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1195 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1196 1197 /* 1198 * If we're already in promisc or allmulti mode, we 1199 * don't have to bother programming the multicast filter. 1200 */ 1201 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1202 return; 1203 1204 /* Now program new ones. */ 1205 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1206 if (ifma->ifma_addr->sa_family != AF_LINK) 1207 continue; 1208 if (DC_IS_CENTAUR(sc)) 1209 h = dc_mchash_le(sc, 1210 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1211 else 1212 h = dc_mchash_be( 1213 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1214 if (h < 32) 1215 hashes[0] |= (1 << h); 1216 else 1217 hashes[1] |= (1 << (h - 32)); 1218 } 1219 1220 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1221 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1222 } 1223 1224 static void 1225 dc_setfilt_asix(struct dc_softc *sc) 1226 { 1227 struct ifnet *ifp; 1228 struct ifmultiaddr *ifma; 1229 int h = 0; 1230 u_int32_t hashes[2] = { 0, 0 }; 1231 1232 ifp = &sc->arpcom.ac_if; 1233 1234 /* Init our MAC address */ 1235 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1236 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1237 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1238 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1239 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1240 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1241 1242 /* If we want promiscuous mode, set the allframes bit. */ 1243 if (ifp->if_flags & IFF_PROMISC) 1244 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1245 else 1246 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1247 1248 if (ifp->if_flags & IFF_ALLMULTI) 1249 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1250 else 1251 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1252 1253 /* 1254 * The ASIX chip has a special bit to enable reception 1255 * of broadcast frames. 1256 */ 1257 if (ifp->if_flags & IFF_BROADCAST) 1258 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1259 else 1260 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1261 1262 /* first, zot all the existing hash bits */ 1263 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1264 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1265 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1266 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1267 1268 /* 1269 * If we're already in promisc or allmulti mode, we 1270 * don't have to bother programming the multicast filter. 1271 */ 1272 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1273 return; 1274 1275 /* now program new ones */ 1276 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1277 if (ifma->ifma_addr->sa_family != AF_LINK) 1278 continue; 1279 h = dc_mchash_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1280 if (h < 32) 1281 hashes[0] |= (1 << h); 1282 else 1283 hashes[1] |= (1 << (h - 32)); 1284 } 1285 1286 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1287 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1288 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1289 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1290 } 1291 1292 static void 1293 dc_setfilt_xircom(struct dc_softc *sc) 1294 { 1295 struct ifnet *ifp; 1296 struct ifmultiaddr *ifma; 1297 struct dc_desc *sframe; 1298 u_int32_t h, *sp; 1299 int i; 1300 1301 ifp = &sc->arpcom.ac_if; 1302 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1303 1304 i = sc->dc_cdata.dc_tx_prod; 1305 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1306 sc->dc_cdata.dc_tx_cnt++; 1307 sframe = &sc->dc_ldata->dc_tx_list[i]; 1308 sp = sc->dc_cdata.dc_sbuf; 1309 bzero(sp, DC_SFRAME_LEN); 1310 1311 sframe->dc_data = htole32(sc->dc_saddr); 1312 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1313 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1314 1315 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1316 1317 /* If we want promiscuous mode, set the allframes bit. */ 1318 if (ifp->if_flags & IFF_PROMISC) 1319 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1320 else 1321 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1322 1323 if (ifp->if_flags & IFF_ALLMULTI) 1324 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1325 else 1326 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1327 1328 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1329 if (ifma->ifma_addr->sa_family != AF_LINK) 1330 continue; 1331 h = dc_mchash_le(sc, 1332 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1333 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1334 } 1335 1336 if (ifp->if_flags & IFF_BROADCAST) { 1337 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1338 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1339 } 1340 1341 /* Set our MAC address */ 1342 sp[0] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1343 sp[1] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1344 sp[2] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1345 1346 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1347 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1348 ifp->if_flags |= IFF_RUNNING; 1349 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1350 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1351 1352 /* 1353 * Wait some time... 1354 */ 1355 DELAY(1000); 1356 1357 ifp->if_timer = 5; 1358 } 1359 1360 static void 1361 dc_setfilt(struct dc_softc *sc) 1362 { 1363 1364 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1365 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1366 dc_setfilt_21143(sc); 1367 1368 if (DC_IS_ASIX(sc)) 1369 dc_setfilt_asix(sc); 1370 1371 if (DC_IS_ADMTEK(sc)) 1372 dc_setfilt_admtek(sc); 1373 1374 if (DC_IS_XIRCOM(sc)) 1375 dc_setfilt_xircom(sc); 1376 } 1377 1378 /* 1379 * In order to fiddle with the 'full-duplex' and '100Mbps' bits in 1380 * the netconfig register, we first have to put the transmit and/or 1381 * receive logic in the idle state. 1382 */ 1383 static void 1384 dc_setcfg(struct dc_softc *sc, int media) 1385 { 1386 int i, restart = 0, watchdogreg; 1387 u_int32_t isr; 1388 1389 if (IFM_SUBTYPE(media) == IFM_NONE) 1390 return; 1391 1392 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) { 1393 restart = 1; 1394 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1395 1396 for (i = 0; i < DC_TIMEOUT; i++) { 1397 isr = CSR_READ_4(sc, DC_ISR); 1398 if (isr & DC_ISR_TX_IDLE && 1399 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1400 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT)) 1401 break; 1402 DELAY(10); 1403 } 1404 1405 if (i == DC_TIMEOUT) 1406 printf("dc%d: failed to force tx and " 1407 "rx to idle state\n", sc->dc_unit); 1408 } 1409 1410 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1411 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1412 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1413 if (sc->dc_pmode == DC_PMODE_MII) { 1414 if (DC_IS_INTEL(sc)) { 1415 /* There's a write enable bit here that reads as 1. */ 1416 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1417 watchdogreg &= ~DC_WDOG_CTLWREN; 1418 watchdogreg |= DC_WDOG_JABBERDIS; 1419 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1420 } else { 1421 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1422 } 1423 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1424 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1425 if (sc->dc_type == DC_TYPE_98713) 1426 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1427 DC_NETCFG_SCRAMBLER)); 1428 if (!DC_IS_DAVICOM(sc)) 1429 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1430 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1431 if (DC_IS_INTEL(sc)) 1432 dc_apply_fixup(sc, IFM_AUTO); 1433 } else { 1434 if (DC_IS_PNIC(sc)) { 1435 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1436 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1437 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1438 } 1439 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1440 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1441 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1442 if (DC_IS_INTEL(sc)) 1443 dc_apply_fixup(sc, 1444 (media & IFM_GMASK) == IFM_FDX ? 1445 IFM_100_TX | IFM_FDX : IFM_100_TX); 1446 } 1447 } 1448 1449 if (IFM_SUBTYPE(media) == IFM_10_T) { 1450 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1451 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1452 if (sc->dc_pmode == DC_PMODE_MII) { 1453 /* There's a write enable bit here that reads as 1. */ 1454 if (DC_IS_INTEL(sc)) { 1455 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1456 watchdogreg &= ~DC_WDOG_CTLWREN; 1457 watchdogreg |= DC_WDOG_JABBERDIS; 1458 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1459 } else { 1460 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1461 } 1462 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1463 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1464 if (sc->dc_type == DC_TYPE_98713) 1465 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1466 if (!DC_IS_DAVICOM(sc)) 1467 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1468 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1469 if (DC_IS_INTEL(sc)) 1470 dc_apply_fixup(sc, IFM_AUTO); 1471 } else { 1472 if (DC_IS_PNIC(sc)) { 1473 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1474 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1475 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1476 } 1477 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1478 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1479 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1480 if (DC_IS_INTEL(sc)) { 1481 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1482 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1483 if ((media & IFM_GMASK) == IFM_FDX) 1484 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1485 else 1486 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1487 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1488 DC_CLRBIT(sc, DC_10BTCTRL, 1489 DC_TCTL_AUTONEGENBL); 1490 dc_apply_fixup(sc, 1491 (media & IFM_GMASK) == IFM_FDX ? 1492 IFM_10_T | IFM_FDX : IFM_10_T); 1493 DELAY(20000); 1494 } 1495 } 1496 } 1497 1498 /* 1499 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1500 * PHY and we want HomePNA mode, set the portsel bit to turn 1501 * on the external MII port. 1502 */ 1503 if (DC_IS_DAVICOM(sc)) { 1504 if (IFM_SUBTYPE(media) == IFM_HPNA_1) { 1505 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1506 sc->dc_link = 1; 1507 } else { 1508 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1509 } 1510 } 1511 1512 if ((media & IFM_GMASK) == IFM_FDX) { 1513 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1514 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1515 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1516 } else { 1517 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1518 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1519 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1520 } 1521 1522 if (restart) 1523 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON | DC_NETCFG_RX_ON); 1524 } 1525 1526 static void 1527 dc_reset(struct dc_softc *sc) 1528 { 1529 int i; 1530 1531 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1532 1533 for (i = 0; i < DC_TIMEOUT; i++) { 1534 DELAY(10); 1535 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1536 break; 1537 } 1538 1539 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) || 1540 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) { 1541 DELAY(10000); 1542 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1543 i = 0; 1544 } 1545 1546 if (i == DC_TIMEOUT) 1547 printf("dc%d: reset never completed!\n", sc->dc_unit); 1548 1549 /* Wait a little while for the chip to get its brains in order. */ 1550 DELAY(1000); 1551 1552 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1553 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1554 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1555 1556 /* 1557 * Bring the SIA out of reset. In some cases, it looks 1558 * like failing to unreset the SIA soon enough gets it 1559 * into a state where it will never come out of reset 1560 * until we reset the whole chip again. 1561 */ 1562 if (DC_IS_INTEL(sc)) { 1563 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1564 CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1565 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1566 } 1567 } 1568 1569 static struct dc_type * 1570 dc_devtype(device_t dev) 1571 { 1572 struct dc_type *t; 1573 u_int32_t rev; 1574 1575 t = dc_devs; 1576 1577 while (t->dc_name != NULL) { 1578 if ((pci_get_vendor(dev) == t->dc_vid) && 1579 (pci_get_device(dev) == t->dc_did)) { 1580 /* Check the PCI revision */ 1581 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1582 if (t->dc_did == DC_DEVICEID_98713 && 1583 rev >= DC_REVISION_98713A) 1584 t++; 1585 if (t->dc_did == DC_DEVICEID_98713_CP && 1586 rev >= DC_REVISION_98713A) 1587 t++; 1588 if (t->dc_did == DC_DEVICEID_987x5 && 1589 rev >= DC_REVISION_98715AEC_C) 1590 t++; 1591 if (t->dc_did == DC_DEVICEID_987x5 && 1592 rev >= DC_REVISION_98725) 1593 t++; 1594 if (t->dc_did == DC_DEVICEID_AX88140A && 1595 rev >= DC_REVISION_88141) 1596 t++; 1597 if (t->dc_did == DC_DEVICEID_82C168 && 1598 rev >= DC_REVISION_82C169) 1599 t++; 1600 if (t->dc_did == DC_DEVICEID_DM9102 && 1601 rev >= DC_REVISION_DM9102A) 1602 t++; 1603 /* 1604 * The Microsoft MN-130 has a device ID of 0x0002, 1605 * which happens to be the same as the PNIC 82c168. 1606 * To keep dc_attach() from getting confused, we 1607 * pretend its ID is something different. 1608 * XXX: ideally, dc_attach() should be checking 1609 * vendorid+deviceid together to avoid such 1610 * collisions. 1611 */ 1612 if (t->dc_vid == DC_VENDORID_MICROSOFT && 1613 t->dc_did == DC_DEVICEID_MSMN130) 1614 t++; 1615 return (t); 1616 } 1617 t++; 1618 } 1619 1620 return (NULL); 1621 } 1622 1623 /* 1624 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1625 * IDs against our list and return a device name if we find a match. 1626 * We do a little bit of extra work to identify the exact type of 1627 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1628 * but different revision IDs. The same is true for 98715/98715A 1629 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1630 * cases, the exact chip revision affects driver behavior. 1631 */ 1632 static int 1633 dc_probe(device_t dev) 1634 { 1635 struct dc_type *t; 1636 1637 t = dc_devtype(dev); 1638 1639 if (t != NULL) { 1640 device_set_desc(dev, t->dc_name); 1641 return (0); 1642 } 1643 1644 return (ENXIO); 1645 } 1646 1647 #ifndef BURN_BRIDGES 1648 static void 1649 dc_acpi(device_t dev) 1650 { 1651 int unit; 1652 u_int32_t iobase, membase, irq; 1653 1654 unit = device_get_unit(dev); 1655 1656 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1657 /* Save important PCI config data. */ 1658 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4); 1659 membase = pci_read_config(dev, DC_PCI_CFBMA, 4); 1660 irq = pci_read_config(dev, DC_PCI_CFIT, 4); 1661 1662 /* Reset the power state. */ 1663 printf("dc%d: chip is in D%d power mode " 1664 "-- setting to D0\n", unit, 1665 pci_get_powerstate(dev)); 1666 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1667 1668 /* Restore PCI config data. */ 1669 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4); 1670 pci_write_config(dev, DC_PCI_CFBMA, membase, 4); 1671 pci_write_config(dev, DC_PCI_CFIT, irq, 4); 1672 } 1673 } 1674 #endif 1675 1676 static void 1677 dc_apply_fixup(struct dc_softc *sc, int media) 1678 { 1679 struct dc_mediainfo *m; 1680 u_int8_t *p; 1681 int i; 1682 u_int32_t reg; 1683 1684 m = sc->dc_mi; 1685 1686 while (m != NULL) { 1687 if (m->dc_media == media) 1688 break; 1689 m = m->dc_next; 1690 } 1691 1692 if (m == NULL) 1693 return; 1694 1695 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1696 reg = (p[0] | (p[1] << 8)) << 16; 1697 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1698 } 1699 1700 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1701 reg = (p[0] | (p[1] << 8)) << 16; 1702 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1703 } 1704 } 1705 1706 static void 1707 dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l) 1708 { 1709 struct dc_mediainfo *m; 1710 1711 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1712 switch (l->dc_sia_code & ~DC_SIA_CODE_EXT) { 1713 case DC_SIA_CODE_10BT: 1714 m->dc_media = IFM_10_T; 1715 break; 1716 case DC_SIA_CODE_10BT_FDX: 1717 m->dc_media = IFM_10_T | IFM_FDX; 1718 break; 1719 case DC_SIA_CODE_10B2: 1720 m->dc_media = IFM_10_2; 1721 break; 1722 case DC_SIA_CODE_10B5: 1723 m->dc_media = IFM_10_5; 1724 break; 1725 default: 1726 break; 1727 } 1728 1729 /* 1730 * We need to ignore CSR13, CSR14, CSR15 for SIA mode. 1731 * Things apparently already work for cards that do 1732 * supply Media Specific Data. 1733 */ 1734 if (l->dc_sia_code & DC_SIA_CODE_EXT) { 1735 m->dc_gp_len = 2; 1736 m->dc_gp_ptr = 1737 (u_int8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl; 1738 } else { 1739 m->dc_gp_len = 2; 1740 m->dc_gp_ptr = 1741 (u_int8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl; 1742 } 1743 1744 m->dc_next = sc->dc_mi; 1745 sc->dc_mi = m; 1746 1747 sc->dc_pmode = DC_PMODE_SIA; 1748 } 1749 1750 static void 1751 dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l) 1752 { 1753 struct dc_mediainfo *m; 1754 1755 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1756 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1757 m->dc_media = IFM_100_TX; 1758 1759 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1760 m->dc_media = IFM_100_TX | IFM_FDX; 1761 1762 m->dc_gp_len = 2; 1763 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1764 1765 m->dc_next = sc->dc_mi; 1766 sc->dc_mi = m; 1767 1768 sc->dc_pmode = DC_PMODE_SYM; 1769 } 1770 1771 static void 1772 dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l) 1773 { 1774 struct dc_mediainfo *m; 1775 u_int8_t *p; 1776 1777 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1778 /* We abuse IFM_AUTO to represent MII. */ 1779 m->dc_media = IFM_AUTO; 1780 m->dc_gp_len = l->dc_gpr_len; 1781 1782 p = (u_int8_t *)l; 1783 p += sizeof(struct dc_eblock_mii); 1784 m->dc_gp_ptr = p; 1785 p += 2 * l->dc_gpr_len; 1786 m->dc_reset_len = *p; 1787 p++; 1788 m->dc_reset_ptr = p; 1789 1790 m->dc_next = sc->dc_mi; 1791 sc->dc_mi = m; 1792 } 1793 1794 static void 1795 dc_read_srom(struct dc_softc *sc, int bits) 1796 { 1797 int size; 1798 1799 size = 2 << bits; 1800 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT); 1801 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); 1802 } 1803 1804 static void 1805 dc_parse_21143_srom(struct dc_softc *sc) 1806 { 1807 struct dc_leaf_hdr *lhdr; 1808 struct dc_eblock_hdr *hdr; 1809 int have_mii, i, loff; 1810 char *ptr; 1811 1812 have_mii = 0; 1813 loff = sc->dc_srom[27]; 1814 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1815 1816 ptr = (char *)lhdr; 1817 ptr += sizeof(struct dc_leaf_hdr) - 1; 1818 /* 1819 * Look if we got a MII media block. 1820 */ 1821 for (i = 0; i < lhdr->dc_mcnt; i++) { 1822 hdr = (struct dc_eblock_hdr *)ptr; 1823 if (hdr->dc_type == DC_EBLOCK_MII) 1824 have_mii++; 1825 1826 ptr += (hdr->dc_len & 0x7F); 1827 ptr++; 1828 } 1829 1830 /* 1831 * Do the same thing again. Only use SIA and SYM media 1832 * blocks if no MII media block is available. 1833 */ 1834 ptr = (char *)lhdr; 1835 ptr += sizeof(struct dc_leaf_hdr) - 1; 1836 for (i = 0; i < lhdr->dc_mcnt; i++) { 1837 hdr = (struct dc_eblock_hdr *)ptr; 1838 switch (hdr->dc_type) { 1839 case DC_EBLOCK_MII: 1840 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1841 break; 1842 case DC_EBLOCK_SIA: 1843 if (! have_mii) 1844 dc_decode_leaf_sia(sc, 1845 (struct dc_eblock_sia *)hdr); 1846 break; 1847 case DC_EBLOCK_SYM: 1848 if (! have_mii) 1849 dc_decode_leaf_sym(sc, 1850 (struct dc_eblock_sym *)hdr); 1851 break; 1852 default: 1853 /* Don't care. Yet. */ 1854 break; 1855 } 1856 ptr += (hdr->dc_len & 0x7F); 1857 ptr++; 1858 } 1859 } 1860 1861 static void 1862 dc_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1863 { 1864 u_int32_t *paddr; 1865 1866 KASSERT(nseg == 1, ("wrong number of segments, should be 1")); 1867 paddr = arg; 1868 *paddr = segs->ds_addr; 1869 } 1870 1871 /* 1872 * Attach the interface. Allocate softc structures, do ifmedia 1873 * setup and ethernet/BPF attach. 1874 */ 1875 static int 1876 dc_attach(device_t dev) 1877 { 1878 int tmp = 0; 1879 u_char eaddr[ETHER_ADDR_LEN]; 1880 u_int32_t command; 1881 struct dc_softc *sc; 1882 struct ifnet *ifp; 1883 u_int32_t revision; 1884 int unit, error = 0, rid, mac_offset; 1885 int i; 1886 u_int8_t *mac; 1887 1888 sc = device_get_softc(dev); 1889 unit = device_get_unit(dev); 1890 1891 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1892 MTX_DEF | MTX_RECURSE); 1893 #ifndef BURN_BRIDGES 1894 /* 1895 * Handle power management nonsense. 1896 */ 1897 dc_acpi(dev); 1898 #endif 1899 /* 1900 * Map control/status registers. 1901 */ 1902 pci_enable_busmaster(dev); 1903 1904 rid = DC_RID; 1905 sc->dc_res = bus_alloc_resource(dev, DC_RES, &rid, 1906 0, ~0, 1, RF_ACTIVE); 1907 1908 if (sc->dc_res == NULL) { 1909 printf("dc%d: couldn't map ports/memory\n", unit); 1910 error = ENXIO; 1911 goto fail; 1912 } 1913 1914 sc->dc_btag = rman_get_bustag(sc->dc_res); 1915 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1916 1917 /* Allocate interrupt. */ 1918 rid = 0; 1919 sc->dc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1920 RF_SHAREABLE | RF_ACTIVE); 1921 1922 if (sc->dc_irq == NULL) { 1923 printf("dc%d: couldn't map interrupt\n", unit); 1924 error = ENXIO; 1925 goto fail; 1926 } 1927 1928 /* Need this info to decide on a chip type. */ 1929 sc->dc_info = dc_devtype(dev); 1930 revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF; 1931 1932 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */ 1933 if (sc->dc_info->dc_did != DC_DEVICEID_82C168 && 1934 sc->dc_info->dc_did != DC_DEVICEID_X3201) 1935 dc_eeprom_width(sc); 1936 1937 switch (sc->dc_info->dc_did) { 1938 case DC_DEVICEID_21143: 1939 sc->dc_type = DC_TYPE_21143; 1940 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1941 sc->dc_flags |= DC_REDUCED_MII_POLL; 1942 /* Save EEPROM contents so we can parse them later. */ 1943 dc_read_srom(sc, sc->dc_romwidth); 1944 break; 1945 case DC_DEVICEID_DM9009: 1946 case DC_DEVICEID_DM9100: 1947 case DC_DEVICEID_DM9102: 1948 sc->dc_type = DC_TYPE_DM9102; 1949 sc->dc_flags |= DC_TX_COALESCE | DC_TX_INTR_ALWAYS; 1950 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_TX_STORENFWD; 1951 sc->dc_flags |= DC_TX_ALIGN; 1952 sc->dc_pmode = DC_PMODE_MII; 1953 /* Increase the latency timer value. */ 1954 command = pci_read_config(dev, DC_PCI_CFLT, 4); 1955 command &= 0xFFFF00FF; 1956 command |= 0x00008000; 1957 pci_write_config(dev, DC_PCI_CFLT, command, 4); 1958 break; 1959 case DC_DEVICEID_AL981: 1960 sc->dc_type = DC_TYPE_AL981; 1961 sc->dc_flags |= DC_TX_USE_TX_INTR; 1962 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1963 sc->dc_pmode = DC_PMODE_MII; 1964 dc_read_srom(sc, sc->dc_romwidth); 1965 break; 1966 case DC_DEVICEID_AN985: 1967 case DC_DEVICEID_ADM9511: 1968 case DC_DEVICEID_ADM9513: 1969 case DC_DEVICEID_FA511: 1970 case DC_DEVICEID_FE2500: 1971 case DC_DEVICEID_EN2242: 1972 case DC_DEVICEID_HAWKING_PN672TX: 1973 case DC_DEVICEID_3CSOHOB: 1974 case DC_DEVICEID_MSMN120: 1975 case DC_DEVICEID_MSMN130_FAKE: /* XXX avoid collision with PNIC*/ 1976 sc->dc_type = DC_TYPE_AN985; 1977 sc->dc_flags |= DC_64BIT_HASH; 1978 sc->dc_flags |= DC_TX_USE_TX_INTR; 1979 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1980 sc->dc_pmode = DC_PMODE_MII; 1981 /* Don't read SROM for - auto-loaded on reset */ 1982 break; 1983 case DC_DEVICEID_98713: 1984 case DC_DEVICEID_98713_CP: 1985 if (revision < DC_REVISION_98713A) { 1986 sc->dc_type = DC_TYPE_98713; 1987 } 1988 if (revision >= DC_REVISION_98713A) { 1989 sc->dc_type = DC_TYPE_98713A; 1990 sc->dc_flags |= DC_21143_NWAY; 1991 } 1992 sc->dc_flags |= DC_REDUCED_MII_POLL; 1993 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1994 break; 1995 case DC_DEVICEID_987x5: 1996 case DC_DEVICEID_EN1217: 1997 /* 1998 * Macronix MX98715AEC-C/D/E parts have only a 1999 * 128-bit hash table. We need to deal with these 2000 * in the same manner as the PNIC II so that we 2001 * get the right number of bits out of the 2002 * CRC routine. 2003 */ 2004 if (revision >= DC_REVISION_98715AEC_C && 2005 revision < DC_REVISION_98725) 2006 sc->dc_flags |= DC_128BIT_HASH; 2007 sc->dc_type = DC_TYPE_987x5; 2008 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 2009 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 2010 break; 2011 case DC_DEVICEID_98727: 2012 sc->dc_type = DC_TYPE_987x5; 2013 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 2014 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 2015 break; 2016 case DC_DEVICEID_82C115: 2017 sc->dc_type = DC_TYPE_PNICII; 2018 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR | DC_128BIT_HASH; 2019 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 2020 break; 2021 case DC_DEVICEID_82C168: 2022 sc->dc_type = DC_TYPE_PNIC; 2023 sc->dc_flags |= DC_TX_STORENFWD | DC_TX_INTR_ALWAYS; 2024 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 2025 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 2026 if (revision < DC_REVISION_82C169) 2027 sc->dc_pmode = DC_PMODE_SYM; 2028 break; 2029 case DC_DEVICEID_AX88140A: 2030 sc->dc_type = DC_TYPE_ASIX; 2031 sc->dc_flags |= DC_TX_USE_TX_INTR | DC_TX_INTR_FIRSTFRAG; 2032 sc->dc_flags |= DC_REDUCED_MII_POLL; 2033 sc->dc_pmode = DC_PMODE_MII; 2034 break; 2035 case DC_DEVICEID_X3201: 2036 sc->dc_type = DC_TYPE_XIRCOM; 2037 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 2038 DC_TX_ALIGN; 2039 /* 2040 * We don't actually need to coalesce, but we're doing 2041 * it to obtain a double word aligned buffer. 2042 * The DC_TX_COALESCE flag is required. 2043 */ 2044 sc->dc_pmode = DC_PMODE_MII; 2045 break; 2046 case DC_DEVICEID_RS7112: 2047 sc->dc_type = DC_TYPE_CONEXANT; 2048 sc->dc_flags |= DC_TX_INTR_ALWAYS; 2049 sc->dc_flags |= DC_REDUCED_MII_POLL; 2050 sc->dc_pmode = DC_PMODE_MII; 2051 dc_read_srom(sc, sc->dc_romwidth); 2052 break; 2053 default: 2054 printf("dc%d: unknown device: %x\n", sc->dc_unit, 2055 sc->dc_info->dc_did); 2056 break; 2057 } 2058 2059 /* Save the cache line size. */ 2060 if (DC_IS_DAVICOM(sc)) 2061 sc->dc_cachesize = 0; 2062 else 2063 sc->dc_cachesize = pci_read_config(dev, 2064 DC_PCI_CFLT, 4) & 0xFF; 2065 2066 /* Reset the adapter. */ 2067 dc_reset(sc); 2068 2069 /* Take 21143 out of snooze mode */ 2070 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 2071 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2072 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 2073 pci_write_config(dev, DC_PCI_CFDD, command, 4); 2074 } 2075 2076 /* 2077 * Try to learn something about the supported media. 2078 * We know that ASIX and ADMtek and Davicom devices 2079 * will *always* be using MII media, so that's a no-brainer. 2080 * The tricky ones are the Macronix/PNIC II and the 2081 * Intel 21143. 2082 */ 2083 if (DC_IS_INTEL(sc)) 2084 dc_parse_21143_srom(sc); 2085 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2086 if (sc->dc_type == DC_TYPE_98713) 2087 sc->dc_pmode = DC_PMODE_MII; 2088 else 2089 sc->dc_pmode = DC_PMODE_SYM; 2090 } else if (!sc->dc_pmode) 2091 sc->dc_pmode = DC_PMODE_MII; 2092 2093 /* 2094 * Get station address from the EEPROM. 2095 */ 2096 switch(sc->dc_type) { 2097 case DC_TYPE_98713: 2098 case DC_TYPE_98713A: 2099 case DC_TYPE_987x5: 2100 case DC_TYPE_PNICII: 2101 dc_read_eeprom(sc, (caddr_t)&mac_offset, 2102 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2103 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2104 break; 2105 case DC_TYPE_PNIC: 2106 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2107 break; 2108 case DC_TYPE_DM9102: 2109 case DC_TYPE_21143: 2110 case DC_TYPE_ASIX: 2111 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2112 break; 2113 case DC_TYPE_AL981: 2114 case DC_TYPE_AN985: 2115 *(u_int32_t *)(&eaddr[0]) = CSR_READ_4(sc, DC_AL_PAR0); 2116 *(u_int16_t *)(&eaddr[4]) = CSR_READ_4(sc, DC_AL_PAR1); 2117 break; 2118 case DC_TYPE_CONEXANT: 2119 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 2120 ETHER_ADDR_LEN); 2121 break; 2122 case DC_TYPE_XIRCOM: 2123 /* The MAC comes from the CIS. */ 2124 mac = pci_get_ether(dev); 2125 if (!mac) { 2126 device_printf(dev, "No station address in CIS!\n"); 2127 error = ENXIO; 2128 goto fail; 2129 } 2130 bcopy(mac, eaddr, ETHER_ADDR_LEN); 2131 break; 2132 default: 2133 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2134 break; 2135 } 2136 2137 /* 2138 * A 21143 or clone chip was detected. Inform the world. 2139 */ 2140 printf("dc%d: Ethernet address: %6D\n", unit, eaddr, ":"); 2141 2142 sc->dc_unit = unit; 2143 bcopy(eaddr, &sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 2144 2145 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */ 2146 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 2147 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct dc_list_data), 1, 2148 sizeof(struct dc_list_data), 0, NULL, NULL, &sc->dc_ltag); 2149 if (error) { 2150 printf("dc%d: failed to allocate busdma tag\n", unit); 2151 error = ENXIO; 2152 goto fail; 2153 } 2154 error = bus_dmamem_alloc(sc->dc_ltag, (void **)&sc->dc_ldata, 2155 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->dc_lmap); 2156 if (error) { 2157 printf("dc%d: failed to allocate DMA safe memory\n", unit); 2158 error = ENXIO; 2159 goto fail; 2160 } 2161 error = bus_dmamap_load(sc->dc_ltag, sc->dc_lmap, sc->dc_ldata, 2162 sizeof(struct dc_list_data), dc_dma_map_addr, &sc->dc_laddr, 2163 BUS_DMA_NOWAIT); 2164 if (error) { 2165 printf("dc%d: cannot get address of the descriptors\n", unit); 2166 error = ENXIO; 2167 goto fail; 2168 } 2169 2170 /* 2171 * Allocate a busdma tag and DMA safe memory for the multicast 2172 * setup frame. 2173 */ 2174 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 2175 BUS_SPACE_MAXADDR, NULL, NULL, DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1, 2176 DC_SFRAME_LEN + DC_MIN_FRAMELEN, 0, NULL, NULL, &sc->dc_stag); 2177 if (error) { 2178 printf("dc%d: failed to allocate busdma tag\n", unit); 2179 error = ENXIO; 2180 goto fail; 2181 } 2182 error = bus_dmamem_alloc(sc->dc_stag, (void **)&sc->dc_cdata.dc_sbuf, 2183 BUS_DMA_NOWAIT, &sc->dc_smap); 2184 if (error) { 2185 printf("dc%d: failed to allocate DMA safe memory\n", unit); 2186 error = ENXIO; 2187 goto fail; 2188 } 2189 error = bus_dmamap_load(sc->dc_stag, sc->dc_smap, sc->dc_cdata.dc_sbuf, 2190 DC_SFRAME_LEN, dc_dma_map_addr, &sc->dc_saddr, BUS_DMA_NOWAIT); 2191 if (error) { 2192 printf("dc%d: cannot get address of the descriptors\n", unit); 2193 error = ENXIO; 2194 goto fail; 2195 } 2196 2197 /* Allocate a busdma tag for mbufs. */ 2198 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 2199 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * DC_TX_LIST_CNT, 2200 DC_TX_LIST_CNT, MCLBYTES, 0, NULL, NULL, &sc->dc_mtag); 2201 if (error) { 2202 printf("dc%d: failed to allocate busdma tag\n", unit); 2203 error = ENXIO; 2204 goto fail; 2205 } 2206 2207 /* Create the TX/RX busdma maps. */ 2208 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2209 error = bus_dmamap_create(sc->dc_mtag, 0, 2210 &sc->dc_cdata.dc_tx_map[i]); 2211 if (error) { 2212 printf("dc%d: failed to init TX ring\n", unit); 2213 error = ENXIO; 2214 goto fail; 2215 } 2216 } 2217 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2218 error = bus_dmamap_create(sc->dc_mtag, 0, 2219 &sc->dc_cdata.dc_rx_map[i]); 2220 if (error) { 2221 printf("dc%d: failed to init RX ring\n", unit); 2222 error = ENXIO; 2223 goto fail; 2224 } 2225 } 2226 error = bus_dmamap_create(sc->dc_mtag, 0, &sc->dc_sparemap); 2227 if (error) { 2228 printf("dc%d: failed to init RX ring\n", unit); 2229 error = ENXIO; 2230 goto fail; 2231 } 2232 2233 ifp = &sc->arpcom.ac_if; 2234 ifp->if_softc = sc; 2235 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2236 /* XXX: bleah, MTU gets overwritten in ether_ifattach() */ 2237 ifp->if_mtu = ETHERMTU; 2238 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2239 ifp->if_ioctl = dc_ioctl; 2240 ifp->if_start = dc_start; 2241 ifp->if_watchdog = dc_watchdog; 2242 ifp->if_init = dc_init; 2243 ifp->if_baudrate = 10000000; 2244 ifp->if_snd.ifq_maxlen = DC_TX_LIST_CNT - 1; 2245 2246 /* 2247 * Do MII setup. If this is a 21143, check for a PHY on the 2248 * MII bus after applying any necessary fixups to twiddle the 2249 * GPIO bits. If we don't end up finding a PHY, restore the 2250 * old selection (SIA only or SIA/SYM) and attach the dcphy 2251 * driver instead. 2252 */ 2253 if (DC_IS_INTEL(sc)) { 2254 dc_apply_fixup(sc, IFM_AUTO); 2255 tmp = sc->dc_pmode; 2256 sc->dc_pmode = DC_PMODE_MII; 2257 } 2258 2259 error = mii_phy_probe(dev, &sc->dc_miibus, 2260 dc_ifmedia_upd, dc_ifmedia_sts); 2261 2262 if (error && DC_IS_INTEL(sc)) { 2263 sc->dc_pmode = tmp; 2264 if (sc->dc_pmode != DC_PMODE_SIA) 2265 sc->dc_pmode = DC_PMODE_SYM; 2266 sc->dc_flags |= DC_21143_NWAY; 2267 mii_phy_probe(dev, &sc->dc_miibus, 2268 dc_ifmedia_upd, dc_ifmedia_sts); 2269 /* 2270 * For non-MII cards, we need to have the 21143 2271 * drive the LEDs. Except there are some systems 2272 * like the NEC VersaPro NoteBook PC which have no 2273 * LEDs, and twiddling these bits has adverse effects 2274 * on them. (I.e. you suddenly can't get a link.) 2275 */ 2276 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033) 2277 sc->dc_flags |= DC_TULIP_LEDS; 2278 error = 0; 2279 } 2280 2281 if (error) { 2282 printf("dc%d: MII without any PHY!\n", sc->dc_unit); 2283 goto fail; 2284 } 2285 2286 if (DC_IS_XIRCOM(sc)) { 2287 /* 2288 * setup General Purpose Port mode and data so the tulip 2289 * can talk to the MII. 2290 */ 2291 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2292 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2293 DELAY(10); 2294 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2295 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2296 DELAY(10); 2297 } 2298 2299 if (DC_IS_ADMTEK(sc)) { 2300 /* 2301 * Set automatic TX underrun recovery for the ADMtek chips 2302 */ 2303 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); 2304 } 2305 2306 /* 2307 * Tell the upper layer(s) we support long frames. 2308 */ 2309 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2310 ifp->if_capabilities |= IFCAP_VLAN_MTU; 2311 2312 callout_init(&sc->dc_stat_ch, IS_MPSAFE ? CALLOUT_MPSAFE : 0); 2313 2314 #ifdef SRM_MEDIA 2315 sc->dc_srm_media = 0; 2316 2317 /* Remember the SRM console media setting */ 2318 if (DC_IS_INTEL(sc)) { 2319 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2320 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 2321 switch ((command >> 8) & 0xff) { 2322 case 3: 2323 sc->dc_srm_media = IFM_10_T; 2324 break; 2325 case 4: 2326 sc->dc_srm_media = IFM_10_T | IFM_FDX; 2327 break; 2328 case 5: 2329 sc->dc_srm_media = IFM_100_TX; 2330 break; 2331 case 6: 2332 sc->dc_srm_media = IFM_100_TX | IFM_FDX; 2333 break; 2334 } 2335 if (sc->dc_srm_media) 2336 sc->dc_srm_media |= IFM_ACTIVE | IFM_ETHER; 2337 } 2338 #endif 2339 2340 /* 2341 * Call MI attach routine. 2342 */ 2343 ether_ifattach(ifp, eaddr); 2344 2345 /* Hook interrupt last to avoid having to lock softc */ 2346 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | 2347 (IS_MPSAFE ? INTR_MPSAFE : 0), 2348 dc_intr, sc, &sc->dc_intrhand); 2349 2350 if (error) { 2351 printf("dc%d: couldn't set up irq\n", unit); 2352 ether_ifdetach(ifp); 2353 goto fail; 2354 } 2355 2356 fail: 2357 if (error) 2358 dc_detach(dev); 2359 return (error); 2360 } 2361 2362 /* 2363 * Shutdown hardware and free up resources. This can be called any 2364 * time after the mutex has been initialized. It is called in both 2365 * the error case in attach and the normal detach case so it needs 2366 * to be careful about only freeing resources that have actually been 2367 * allocated. 2368 */ 2369 static int 2370 dc_detach(device_t dev) 2371 { 2372 struct dc_softc *sc; 2373 struct ifnet *ifp; 2374 struct dc_mediainfo *m; 2375 int i; 2376 2377 sc = device_get_softc(dev); 2378 KASSERT(mtx_initialized(&sc->dc_mtx), ("dc mutex not initialized")); 2379 DC_LOCK(sc); 2380 2381 ifp = &sc->arpcom.ac_if; 2382 2383 /* These should only be active if attach succeeded */ 2384 if (device_is_attached(dev)) { 2385 dc_stop(sc); 2386 ether_ifdetach(ifp); 2387 } 2388 if (sc->dc_miibus) 2389 device_delete_child(dev, sc->dc_miibus); 2390 bus_generic_detach(dev); 2391 2392 if (sc->dc_intrhand) 2393 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2394 if (sc->dc_irq) 2395 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2396 if (sc->dc_res) 2397 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2398 2399 if (sc->dc_cdata.dc_sbuf != NULL) 2400 bus_dmamem_free(sc->dc_stag, sc->dc_cdata.dc_sbuf, sc->dc_smap); 2401 if (sc->dc_ldata != NULL) 2402 bus_dmamem_free(sc->dc_ltag, sc->dc_ldata, sc->dc_lmap); 2403 for (i = 0; i < DC_TX_LIST_CNT; i++) 2404 bus_dmamap_destroy(sc->dc_mtag, sc->dc_cdata.dc_tx_map[i]); 2405 for (i = 0; i < DC_RX_LIST_CNT; i++) 2406 bus_dmamap_destroy(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i]); 2407 bus_dmamap_destroy(sc->dc_mtag, sc->dc_sparemap); 2408 if (sc->dc_stag) 2409 bus_dma_tag_destroy(sc->dc_stag); 2410 if (sc->dc_mtag) 2411 bus_dma_tag_destroy(sc->dc_mtag); 2412 if (sc->dc_ltag) 2413 bus_dma_tag_destroy(sc->dc_ltag); 2414 2415 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2416 2417 while (sc->dc_mi != NULL) { 2418 m = sc->dc_mi->dc_next; 2419 free(sc->dc_mi, M_DEVBUF); 2420 sc->dc_mi = m; 2421 } 2422 free(sc->dc_srom, M_DEVBUF); 2423 2424 DC_UNLOCK(sc); 2425 mtx_destroy(&sc->dc_mtx); 2426 2427 return (0); 2428 } 2429 2430 /* 2431 * Initialize the transmit descriptors. 2432 */ 2433 static int 2434 dc_list_tx_init(struct dc_softc *sc) 2435 { 2436 struct dc_chain_data *cd; 2437 struct dc_list_data *ld; 2438 int i, nexti; 2439 2440 cd = &sc->dc_cdata; 2441 ld = sc->dc_ldata; 2442 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2443 if (i == DC_TX_LIST_CNT - 1) 2444 nexti = 0; 2445 else 2446 nexti = i + 1; 2447 ld->dc_tx_list[i].dc_next = htole32(DC_TXDESC(sc, nexti)); 2448 cd->dc_tx_chain[i] = NULL; 2449 ld->dc_tx_list[i].dc_data = 0; 2450 ld->dc_tx_list[i].dc_ctl = 0; 2451 } 2452 2453 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2454 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2455 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2456 return (0); 2457 } 2458 2459 2460 /* 2461 * Initialize the RX descriptors and allocate mbufs for them. Note that 2462 * we arrange the descriptors in a closed ring, so that the last descriptor 2463 * points back to the first. 2464 */ 2465 static int 2466 dc_list_rx_init(struct dc_softc *sc) 2467 { 2468 struct dc_chain_data *cd; 2469 struct dc_list_data *ld; 2470 int i, nexti; 2471 2472 cd = &sc->dc_cdata; 2473 ld = sc->dc_ldata; 2474 2475 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2476 if (dc_newbuf(sc, i, 1) != 0) 2477 return (ENOBUFS); 2478 if (i == DC_RX_LIST_CNT - 1) 2479 nexti = 0; 2480 else 2481 nexti = i + 1; 2482 ld->dc_rx_list[i].dc_next = htole32(DC_RXDESC(sc, nexti)); 2483 } 2484 2485 cd->dc_rx_prod = 0; 2486 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2487 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2488 return (0); 2489 } 2490 2491 static void 2492 dc_dma_map_rxbuf(arg, segs, nseg, mapsize, error) 2493 void *arg; 2494 bus_dma_segment_t *segs; 2495 int nseg; 2496 bus_size_t mapsize; 2497 int error; 2498 { 2499 struct dc_softc *sc; 2500 struct dc_desc *c; 2501 2502 sc = arg; 2503 c = &sc->dc_ldata->dc_rx_list[sc->dc_cdata.dc_rx_cur]; 2504 if (error) { 2505 sc->dc_cdata.dc_rx_err = error; 2506 return; 2507 } 2508 2509 KASSERT(nseg == 1, ("wrong number of segments, should be 1")); 2510 sc->dc_cdata.dc_rx_err = 0; 2511 c->dc_data = htole32(segs->ds_addr); 2512 } 2513 2514 /* 2515 * Initialize an RX descriptor and attach an MBUF cluster. 2516 */ 2517 static int 2518 dc_newbuf(struct dc_softc *sc, int i, int alloc) 2519 { 2520 struct mbuf *m_new; 2521 bus_dmamap_t tmp; 2522 int error; 2523 2524 if (alloc) { 2525 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2526 if (m_new == NULL) 2527 return (ENOBUFS); 2528 } else { 2529 m_new = sc->dc_cdata.dc_rx_chain[i]; 2530 m_new->m_data = m_new->m_ext.ext_buf; 2531 } 2532 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2533 m_adj(m_new, sizeof(u_int64_t)); 2534 2535 /* 2536 * If this is a PNIC chip, zero the buffer. This is part 2537 * of the workaround for the receive bug in the 82c168 and 2538 * 82c169 chips. 2539 */ 2540 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2541 bzero(mtod(m_new, char *), m_new->m_len); 2542 2543 /* No need to remap the mbuf if we're reusing it. */ 2544 if (alloc) { 2545 sc->dc_cdata.dc_rx_cur = i; 2546 error = bus_dmamap_load_mbuf(sc->dc_mtag, sc->dc_sparemap, 2547 m_new, dc_dma_map_rxbuf, sc, 0); 2548 if (error) { 2549 m_freem(m_new); 2550 return (error); 2551 } 2552 if (sc->dc_cdata.dc_rx_err != 0) { 2553 m_freem(m_new); 2554 return (sc->dc_cdata.dc_rx_err); 2555 } 2556 bus_dmamap_unload(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i]); 2557 tmp = sc->dc_cdata.dc_rx_map[i]; 2558 sc->dc_cdata.dc_rx_map[i] = sc->dc_sparemap; 2559 sc->dc_sparemap = tmp; 2560 sc->dc_cdata.dc_rx_chain[i] = m_new; 2561 } 2562 2563 sc->dc_ldata->dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN); 2564 sc->dc_ldata->dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN); 2565 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i], 2566 BUS_DMASYNC_PREREAD); 2567 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2568 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2569 return (0); 2570 } 2571 2572 /* 2573 * Grrrrr. 2574 * The PNIC chip has a terrible bug in it that manifests itself during 2575 * periods of heavy activity. The exact mode of failure if difficult to 2576 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2577 * will happen on slow machines. The bug is that sometimes instead of 2578 * uploading one complete frame during reception, it uploads what looks 2579 * like the entire contents of its FIFO memory. The frame we want is at 2580 * the end of the whole mess, but we never know exactly how much data has 2581 * been uploaded, so salvaging the frame is hard. 2582 * 2583 * There is only one way to do it reliably, and it's disgusting. 2584 * Here's what we know: 2585 * 2586 * - We know there will always be somewhere between one and three extra 2587 * descriptors uploaded. 2588 * 2589 * - We know the desired received frame will always be at the end of the 2590 * total data upload. 2591 * 2592 * - We know the size of the desired received frame because it will be 2593 * provided in the length field of the status word in the last descriptor. 2594 * 2595 * Here's what we do: 2596 * 2597 * - When we allocate buffers for the receive ring, we bzero() them. 2598 * This means that we know that the buffer contents should be all 2599 * zeros, except for data uploaded by the chip. 2600 * 2601 * - We also force the PNIC chip to upload frames that include the 2602 * ethernet CRC at the end. 2603 * 2604 * - We gather all of the bogus frame data into a single buffer. 2605 * 2606 * - We then position a pointer at the end of this buffer and scan 2607 * backwards until we encounter the first non-zero byte of data. 2608 * This is the end of the received frame. We know we will encounter 2609 * some data at the end of the frame because the CRC will always be 2610 * there, so even if the sender transmits a packet of all zeros, 2611 * we won't be fooled. 2612 * 2613 * - We know the size of the actual received frame, so we subtract 2614 * that value from the current pointer location. This brings us 2615 * to the start of the actual received packet. 2616 * 2617 * - We copy this into an mbuf and pass it on, along with the actual 2618 * frame length. 2619 * 2620 * The performance hit is tremendous, but it beats dropping frames all 2621 * the time. 2622 */ 2623 2624 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG | DC_RXSTAT_LASTFRAG) 2625 static void 2626 dc_pnic_rx_bug_war(struct dc_softc *sc, int idx) 2627 { 2628 struct dc_desc *cur_rx; 2629 struct dc_desc *c = NULL; 2630 struct mbuf *m = NULL; 2631 unsigned char *ptr; 2632 int i, total_len; 2633 u_int32_t rxstat = 0; 2634 2635 i = sc->dc_pnic_rx_bug_save; 2636 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2637 ptr = sc->dc_pnic_rx_buf; 2638 bzero(ptr, DC_RXLEN * 5); 2639 2640 /* Copy all the bytes from the bogus buffers. */ 2641 while (1) { 2642 c = &sc->dc_ldata->dc_rx_list[i]; 2643 rxstat = le32toh(c->dc_status); 2644 m = sc->dc_cdata.dc_rx_chain[i]; 2645 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2646 ptr += DC_RXLEN; 2647 /* If this is the last buffer, break out. */ 2648 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2649 break; 2650 dc_newbuf(sc, i, 0); 2651 DC_INC(i, DC_RX_LIST_CNT); 2652 } 2653 2654 /* Find the length of the actual receive frame. */ 2655 total_len = DC_RXBYTES(rxstat); 2656 2657 /* Scan backwards until we hit a non-zero byte. */ 2658 while (*ptr == 0x00) 2659 ptr--; 2660 2661 /* Round off. */ 2662 if ((uintptr_t)(ptr) & 0x3) 2663 ptr -= 1; 2664 2665 /* Now find the start of the frame. */ 2666 ptr -= total_len; 2667 if (ptr < sc->dc_pnic_rx_buf) 2668 ptr = sc->dc_pnic_rx_buf; 2669 2670 /* 2671 * Now copy the salvaged frame to the last mbuf and fake up 2672 * the status word to make it look like a successful 2673 * frame reception. 2674 */ 2675 dc_newbuf(sc, i, 0); 2676 bcopy(ptr, mtod(m, char *), total_len); 2677 cur_rx->dc_status = htole32(rxstat | DC_RXSTAT_FIRSTFRAG); 2678 } 2679 2680 /* 2681 * This routine searches the RX ring for dirty descriptors in the 2682 * event that the rxeof routine falls out of sync with the chip's 2683 * current descriptor pointer. This may happen sometimes as a result 2684 * of a "no RX buffer available" condition that happens when the chip 2685 * consumes all of the RX buffers before the driver has a chance to 2686 * process the RX ring. This routine may need to be called more than 2687 * once to bring the driver back in sync with the chip, however we 2688 * should still be getting RX DONE interrupts to drive the search 2689 * for new packets in the RX ring, so we should catch up eventually. 2690 */ 2691 static int 2692 dc_rx_resync(struct dc_softc *sc) 2693 { 2694 struct dc_desc *cur_rx; 2695 int i, pos; 2696 2697 pos = sc->dc_cdata.dc_rx_prod; 2698 2699 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2700 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2701 if (!(le32toh(cur_rx->dc_status) & DC_RXSTAT_OWN)) 2702 break; 2703 DC_INC(pos, DC_RX_LIST_CNT); 2704 } 2705 2706 /* If the ring really is empty, then just return. */ 2707 if (i == DC_RX_LIST_CNT) 2708 return (0); 2709 2710 /* We've fallen behing the chip: catch it. */ 2711 sc->dc_cdata.dc_rx_prod = pos; 2712 2713 return (EAGAIN); 2714 } 2715 2716 /* 2717 * A frame has been uploaded: pass the resulting mbuf chain up to 2718 * the higher level protocols. 2719 */ 2720 static void 2721 dc_rxeof(struct dc_softc *sc) 2722 { 2723 struct mbuf *m; 2724 struct ifnet *ifp; 2725 struct dc_desc *cur_rx; 2726 int i, total_len = 0; 2727 u_int32_t rxstat; 2728 2729 DC_LOCK_ASSERT(sc); 2730 2731 ifp = &sc->arpcom.ac_if; 2732 i = sc->dc_cdata.dc_rx_prod; 2733 2734 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD); 2735 while (!(le32toh(sc->dc_ldata->dc_rx_list[i].dc_status) & 2736 DC_RXSTAT_OWN)) { 2737 #ifdef DEVICE_POLLING 2738 if (ifp->if_flags & IFF_POLLING) { 2739 if (sc->rxcycles <= 0) 2740 break; 2741 sc->rxcycles--; 2742 } 2743 #endif 2744 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2745 rxstat = le32toh(cur_rx->dc_status); 2746 m = sc->dc_cdata.dc_rx_chain[i]; 2747 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i], 2748 BUS_DMASYNC_POSTREAD); 2749 total_len = DC_RXBYTES(rxstat); 2750 2751 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2752 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2753 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2754 sc->dc_pnic_rx_bug_save = i; 2755 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2756 DC_INC(i, DC_RX_LIST_CNT); 2757 continue; 2758 } 2759 dc_pnic_rx_bug_war(sc, i); 2760 rxstat = le32toh(cur_rx->dc_status); 2761 total_len = DC_RXBYTES(rxstat); 2762 } 2763 } 2764 2765 /* 2766 * If an error occurs, update stats, clear the 2767 * status word and leave the mbuf cluster in place: 2768 * it should simply get re-used next time this descriptor 2769 * comes up in the ring. However, don't report long 2770 * frames as errors since they could be vlans. 2771 */ 2772 if ((rxstat & DC_RXSTAT_RXERR)) { 2773 if (!(rxstat & DC_RXSTAT_GIANT) || 2774 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2775 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2776 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2777 ifp->if_ierrors++; 2778 if (rxstat & DC_RXSTAT_COLLSEEN) 2779 ifp->if_collisions++; 2780 dc_newbuf(sc, i, 0); 2781 if (rxstat & DC_RXSTAT_CRCERR) { 2782 DC_INC(i, DC_RX_LIST_CNT); 2783 continue; 2784 } else { 2785 dc_init(sc); 2786 return; 2787 } 2788 } 2789 } 2790 2791 /* No errors; receive the packet. */ 2792 total_len -= ETHER_CRC_LEN; 2793 #ifdef __i386__ 2794 /* 2795 * On the x86 we do not have alignment problems, so try to 2796 * allocate a new buffer for the receive ring, and pass up 2797 * the one where the packet is already, saving the expensive 2798 * copy done in m_devget(). 2799 * If we are on an architecture with alignment problems, or 2800 * if the allocation fails, then use m_devget and leave the 2801 * existing buffer in the receive ring. 2802 */ 2803 if (dc_quick && dc_newbuf(sc, i, 1) == 0) { 2804 m->m_pkthdr.rcvif = ifp; 2805 m->m_pkthdr.len = m->m_len = total_len; 2806 DC_INC(i, DC_RX_LIST_CNT); 2807 } else 2808 #endif 2809 { 2810 struct mbuf *m0; 2811 2812 m0 = m_devget(mtod(m, char *), total_len, 2813 ETHER_ALIGN, ifp, NULL); 2814 dc_newbuf(sc, i, 0); 2815 DC_INC(i, DC_RX_LIST_CNT); 2816 if (m0 == NULL) { 2817 ifp->if_ierrors++; 2818 continue; 2819 } 2820 m = m0; 2821 } 2822 2823 ifp->if_ipackets++; 2824 DC_UNLOCK(sc); 2825 (*ifp->if_input)(ifp, m); 2826 DC_LOCK(sc); 2827 } 2828 2829 sc->dc_cdata.dc_rx_prod = i; 2830 } 2831 2832 /* 2833 * A frame was downloaded to the chip. It's safe for us to clean up 2834 * the list buffers. 2835 */ 2836 2837 static void 2838 dc_txeof(struct dc_softc *sc) 2839 { 2840 struct dc_desc *cur_tx = NULL; 2841 struct ifnet *ifp; 2842 int idx; 2843 u_int32_t ctl, txstat; 2844 2845 ifp = &sc->arpcom.ac_if; 2846 2847 /* 2848 * Go through our tx list and free mbufs for those 2849 * frames that have been transmitted. 2850 */ 2851 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD); 2852 idx = sc->dc_cdata.dc_tx_cons; 2853 while (idx != sc->dc_cdata.dc_tx_prod) { 2854 2855 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2856 txstat = le32toh(cur_tx->dc_status); 2857 ctl = le32toh(cur_tx->dc_ctl); 2858 2859 if (txstat & DC_TXSTAT_OWN) 2860 break; 2861 2862 if (!(ctl & DC_TXCTL_FIRSTFRAG) || ctl & DC_TXCTL_SETUP) { 2863 if (ctl & DC_TXCTL_SETUP) { 2864 /* 2865 * Yes, the PNIC is so brain damaged 2866 * that it will sometimes generate a TX 2867 * underrun error while DMAing the RX 2868 * filter setup frame. If we detect this, 2869 * we have to send the setup frame again, 2870 * or else the filter won't be programmed 2871 * correctly. 2872 */ 2873 if (DC_IS_PNIC(sc)) { 2874 if (txstat & DC_TXSTAT_ERRSUM) 2875 dc_setfilt(sc); 2876 } 2877 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2878 } 2879 sc->dc_cdata.dc_tx_cnt--; 2880 DC_INC(idx, DC_TX_LIST_CNT); 2881 continue; 2882 } 2883 2884 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) { 2885 /* 2886 * XXX: Why does my Xircom taunt me so? 2887 * For some reason it likes setting the CARRLOST flag 2888 * even when the carrier is there. wtf?!? 2889 * Who knows, but Conexant chips have the 2890 * same problem. Maybe they took lessons 2891 * from Xircom. 2892 */ 2893 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2894 sc->dc_pmode == DC_PMODE_MII && 2895 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 2896 DC_TXSTAT_NOCARRIER))) 2897 txstat &= ~DC_TXSTAT_ERRSUM; 2898 } else { 2899 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2900 sc->dc_pmode == DC_PMODE_MII && 2901 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 2902 DC_TXSTAT_NOCARRIER | DC_TXSTAT_CARRLOST))) 2903 txstat &= ~DC_TXSTAT_ERRSUM; 2904 } 2905 2906 if (txstat & DC_TXSTAT_ERRSUM) { 2907 ifp->if_oerrors++; 2908 if (txstat & DC_TXSTAT_EXCESSCOLL) 2909 ifp->if_collisions++; 2910 if (txstat & DC_TXSTAT_LATECOLL) 2911 ifp->if_collisions++; 2912 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2913 dc_init(sc); 2914 return; 2915 } 2916 } 2917 2918 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2919 2920 ifp->if_opackets++; 2921 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2922 bus_dmamap_sync(sc->dc_mtag, 2923 sc->dc_cdata.dc_tx_map[idx], 2924 BUS_DMASYNC_POSTWRITE); 2925 bus_dmamap_unload(sc->dc_mtag, 2926 sc->dc_cdata.dc_tx_map[idx]); 2927 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2928 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2929 } 2930 2931 sc->dc_cdata.dc_tx_cnt--; 2932 DC_INC(idx, DC_TX_LIST_CNT); 2933 } 2934 2935 if (idx != sc->dc_cdata.dc_tx_cons) { 2936 /* Some buffers have been freed. */ 2937 sc->dc_cdata.dc_tx_cons = idx; 2938 ifp->if_flags &= ~IFF_OACTIVE; 2939 } 2940 ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5; 2941 } 2942 2943 static void 2944 dc_tick(void *xsc) 2945 { 2946 struct dc_softc *sc; 2947 struct mii_data *mii; 2948 struct ifnet *ifp; 2949 u_int32_t r; 2950 2951 sc = xsc; 2952 DC_LOCK(sc); 2953 ifp = &sc->arpcom.ac_if; 2954 mii = device_get_softc(sc->dc_miibus); 2955 2956 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2957 if (sc->dc_flags & DC_21143_NWAY) { 2958 r = CSR_READ_4(sc, DC_10BTSTAT); 2959 if (IFM_SUBTYPE(mii->mii_media_active) == 2960 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2961 sc->dc_link = 0; 2962 mii_mediachg(mii); 2963 } 2964 if (IFM_SUBTYPE(mii->mii_media_active) == 2965 IFM_10_T && (r & DC_TSTAT_LS10)) { 2966 sc->dc_link = 0; 2967 mii_mediachg(mii); 2968 } 2969 if (sc->dc_link == 0) 2970 mii_tick(mii); 2971 } else { 2972 r = CSR_READ_4(sc, DC_ISR); 2973 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2974 sc->dc_cdata.dc_tx_cnt == 0) { 2975 mii_tick(mii); 2976 if (!(mii->mii_media_status & IFM_ACTIVE)) 2977 sc->dc_link = 0; 2978 } 2979 } 2980 } else 2981 mii_tick(mii); 2982 2983 /* 2984 * When the init routine completes, we expect to be able to send 2985 * packets right away, and in fact the network code will send a 2986 * gratuitous ARP the moment the init routine marks the interface 2987 * as running. However, even though the MAC may have been initialized, 2988 * there may be a delay of a few seconds before the PHY completes 2989 * autonegotiation and the link is brought up. Any transmissions 2990 * made during that delay will be lost. Dealing with this is tricky: 2991 * we can't just pause in the init routine while waiting for the 2992 * PHY to come ready since that would bring the whole system to 2993 * a screeching halt for several seconds. 2994 * 2995 * What we do here is prevent the TX start routine from sending 2996 * any packets until a link has been established. After the 2997 * interface has been initialized, the tick routine will poll 2998 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2999 * that time, packets will stay in the send queue, and once the 3000 * link comes up, they will be flushed out to the wire. 3001 */ 3002 if (!sc->dc_link && mii->mii_media_status & IFM_ACTIVE && 3003 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 3004 sc->dc_link++; 3005 if (ifp->if_snd.ifq_head != NULL) 3006 dc_start(ifp); 3007 } 3008 3009 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 3010 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3011 else 3012 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3013 3014 DC_UNLOCK(sc); 3015 } 3016 3017 /* 3018 * A transmit underrun has occurred. Back off the transmit threshold, 3019 * or switch to store and forward mode if we have to. 3020 */ 3021 static void 3022 dc_tx_underrun(struct dc_softc *sc) 3023 { 3024 u_int32_t isr; 3025 int i; 3026 3027 if (DC_IS_DAVICOM(sc)) 3028 dc_init(sc); 3029 3030 if (DC_IS_INTEL(sc)) { 3031 /* 3032 * The real 21143 requires that the transmitter be idle 3033 * in order to change the transmit threshold or store 3034 * and forward state. 3035 */ 3036 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3037 3038 for (i = 0; i < DC_TIMEOUT; i++) { 3039 isr = CSR_READ_4(sc, DC_ISR); 3040 if (isr & DC_ISR_TX_IDLE) 3041 break; 3042 DELAY(10); 3043 } 3044 if (i == DC_TIMEOUT) { 3045 printf("dc%d: failed to force tx to idle state\n", 3046 sc->dc_unit); 3047 dc_init(sc); 3048 } 3049 } 3050 3051 printf("dc%d: TX underrun -- ", sc->dc_unit); 3052 sc->dc_txthresh += DC_TXTHRESH_INC; 3053 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3054 printf("using store and forward mode\n"); 3055 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3056 } else { 3057 printf("increasing TX threshold\n"); 3058 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3059 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3060 } 3061 3062 if (DC_IS_INTEL(sc)) 3063 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3064 } 3065 3066 #ifdef DEVICE_POLLING 3067 static poll_handler_t dc_poll; 3068 3069 static void 3070 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 3071 { 3072 struct dc_softc *sc = ifp->if_softc; 3073 3074 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 3075 /* Re-enable interrupts. */ 3076 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3077 return; 3078 } 3079 DC_LOCK(sc); 3080 sc->rxcycles = count; 3081 dc_rxeof(sc); 3082 dc_txeof(sc); 3083 if (ifp->if_snd.ifq_head != NULL && !(ifp->if_flags & IFF_OACTIVE)) 3084 dc_start(ifp); 3085 3086 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 3087 u_int32_t status; 3088 3089 status = CSR_READ_4(sc, DC_ISR); 3090 status &= (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF | 3091 DC_ISR_TX_NOBUF | DC_ISR_TX_IDLE | DC_ISR_TX_UNDERRUN | 3092 DC_ISR_BUS_ERR); 3093 if (!status) { 3094 DC_UNLOCK(sc); 3095 return; 3096 } 3097 /* ack what we have */ 3098 CSR_WRITE_4(sc, DC_ISR, status); 3099 3100 if (status & (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF)) { 3101 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 3102 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 3103 3104 if (dc_rx_resync(sc)) 3105 dc_rxeof(sc); 3106 } 3107 /* restart transmit unit if necessary */ 3108 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 3109 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3110 3111 if (status & DC_ISR_TX_UNDERRUN) 3112 dc_tx_underrun(sc); 3113 3114 if (status & DC_ISR_BUS_ERR) { 3115 printf("dc_poll: dc%d bus error\n", sc->dc_unit); 3116 dc_reset(sc); 3117 dc_init(sc); 3118 } 3119 } 3120 DC_UNLOCK(sc); 3121 } 3122 #endif /* DEVICE_POLLING */ 3123 3124 static void 3125 dc_intr(void *arg) 3126 { 3127 struct dc_softc *sc; 3128 struct ifnet *ifp; 3129 u_int32_t status; 3130 3131 sc = arg; 3132 3133 if (sc->suspended) 3134 return; 3135 3136 if ((CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) 3137 return; 3138 3139 DC_LOCK(sc); 3140 ifp = &sc->arpcom.ac_if; 3141 #ifdef DEVICE_POLLING 3142 if (ifp->if_flags & IFF_POLLING) 3143 goto done; 3144 if (ether_poll_register(dc_poll, ifp)) { /* ok, disable interrupts */ 3145 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3146 goto done; 3147 } 3148 #endif 3149 3150 /* Suppress unwanted interrupts */ 3151 if (!(ifp->if_flags & IFF_UP)) { 3152 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 3153 dc_stop(sc); 3154 DC_UNLOCK(sc); 3155 return; 3156 } 3157 3158 /* Disable interrupts. */ 3159 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3160 3161 while (((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) 3162 && status != 0xFFFFFFFF) { 3163 3164 CSR_WRITE_4(sc, DC_ISR, status); 3165 3166 if (status & DC_ISR_RX_OK) { 3167 int curpkts; 3168 curpkts = ifp->if_ipackets; 3169 dc_rxeof(sc); 3170 if (curpkts == ifp->if_ipackets) { 3171 while (dc_rx_resync(sc)) 3172 dc_rxeof(sc); 3173 } 3174 } 3175 3176 if (status & (DC_ISR_TX_OK | DC_ISR_TX_NOBUF)) 3177 dc_txeof(sc); 3178 3179 if (status & DC_ISR_TX_IDLE) { 3180 dc_txeof(sc); 3181 if (sc->dc_cdata.dc_tx_cnt) { 3182 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3183 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3184 } 3185 } 3186 3187 if (status & DC_ISR_TX_UNDERRUN) 3188 dc_tx_underrun(sc); 3189 3190 if ((status & DC_ISR_RX_WATDOGTIMEO) 3191 || (status & DC_ISR_RX_NOBUF)) { 3192 int curpkts; 3193 curpkts = ifp->if_ipackets; 3194 dc_rxeof(sc); 3195 if (curpkts == ifp->if_ipackets) { 3196 while (dc_rx_resync(sc)) 3197 dc_rxeof(sc); 3198 } 3199 } 3200 3201 if (status & DC_ISR_BUS_ERR) { 3202 dc_reset(sc); 3203 dc_init(sc); 3204 } 3205 } 3206 3207 /* Re-enable interrupts. */ 3208 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3209 3210 if (ifp->if_snd.ifq_head != NULL) 3211 dc_start(ifp); 3212 3213 #ifdef DEVICE_POLLING 3214 done: 3215 #endif 3216 3217 DC_UNLOCK(sc); 3218 } 3219 3220 static void 3221 dc_dma_map_txbuf(arg, segs, nseg, mapsize, error) 3222 void *arg; 3223 bus_dma_segment_t *segs; 3224 int nseg; 3225 bus_size_t mapsize; 3226 int error; 3227 { 3228 struct dc_softc *sc; 3229 struct dc_desc *f; 3230 int cur, first, frag, i; 3231 3232 sc = arg; 3233 if (error) { 3234 sc->dc_cdata.dc_tx_err = error; 3235 return; 3236 } 3237 3238 first = cur = frag = sc->dc_cdata.dc_tx_prod; 3239 for (i = 0; i < nseg; i++) { 3240 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) && 3241 (frag == (DC_TX_LIST_CNT - 1)) && 3242 (first != sc->dc_cdata.dc_tx_first)) { 3243 bus_dmamap_unload(sc->dc_mtag, 3244 sc->dc_cdata.dc_tx_map[first]); 3245 sc->dc_cdata.dc_tx_err = ENOBUFS; 3246 return; 3247 } 3248 3249 f = &sc->dc_ldata->dc_tx_list[frag]; 3250 f->dc_ctl = htole32(DC_TXCTL_TLINK | segs[i].ds_len); 3251 if (i == 0) { 3252 f->dc_status = 0; 3253 f->dc_ctl |= htole32(DC_TXCTL_FIRSTFRAG); 3254 } else 3255 f->dc_status = htole32(DC_TXSTAT_OWN); 3256 f->dc_data = htole32(segs[i].ds_addr); 3257 cur = frag; 3258 DC_INC(frag, DC_TX_LIST_CNT); 3259 } 3260 3261 sc->dc_cdata.dc_tx_err = 0; 3262 sc->dc_cdata.dc_tx_prod = frag; 3263 sc->dc_cdata.dc_tx_cnt += nseg; 3264 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_LASTFRAG); 3265 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 3266 sc->dc_ldata->dc_tx_list[first].dc_ctl |= 3267 htole32(DC_TXCTL_FINT); 3268 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 3269 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3270 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 3271 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3272 sc->dc_ldata->dc_tx_list[first].dc_status = htole32(DC_TXSTAT_OWN); 3273 } 3274 3275 /* 3276 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 3277 * pointers to the fragment pointers. 3278 */ 3279 static int 3280 dc_encap(struct dc_softc *sc, struct mbuf **m_head) 3281 { 3282 struct mbuf *m; 3283 int error, idx, chainlen = 0; 3284 3285 /* 3286 * If there's no way we can send any packets, return now. 3287 */ 3288 if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt < 6) 3289 return (ENOBUFS); 3290 3291 /* 3292 * Count the number of frags in this chain to see if 3293 * we need to m_defrag. Since the descriptor list is shared 3294 * by all packets, we'll m_defrag long chains so that they 3295 * do not use up the entire list, even if they would fit. 3296 */ 3297 for (m = *m_head; m != NULL; m = m->m_next) 3298 chainlen++; 3299 3300 if ((chainlen > DC_TX_LIST_CNT / 4) || 3301 ((DC_TX_LIST_CNT - (chainlen + sc->dc_cdata.dc_tx_cnt)) < 6)) { 3302 m = m_defrag(*m_head, M_DONTWAIT); 3303 if (m == NULL) 3304 return (ENOBUFS); 3305 *m_head = m; 3306 } 3307 3308 /* 3309 * Start packing the mbufs in this chain into 3310 * the fragment pointers. Stop when we run out 3311 * of fragments or hit the end of the mbuf chain. 3312 */ 3313 idx = sc->dc_cdata.dc_tx_prod; 3314 error = bus_dmamap_load_mbuf(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx], 3315 *m_head, dc_dma_map_txbuf, sc, 0); 3316 if (error) 3317 return (error); 3318 if (sc->dc_cdata.dc_tx_err != 0) 3319 return (sc->dc_cdata.dc_tx_err); 3320 sc->dc_cdata.dc_tx_chain[idx] = *m_head; 3321 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx], 3322 BUS_DMASYNC_PREWRITE); 3323 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 3324 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3325 return (0); 3326 } 3327 3328 /* 3329 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3330 * to the mbuf data regions directly in the transmit lists. We also save a 3331 * copy of the pointers since the transmit list fragment pointers are 3332 * physical addresses. 3333 */ 3334 3335 static void 3336 dc_start(struct ifnet *ifp) 3337 { 3338 struct dc_softc *sc; 3339 struct mbuf *m_head = NULL, *m; 3340 int idx; 3341 3342 sc = ifp->if_softc; 3343 3344 DC_LOCK(sc); 3345 3346 if (!sc->dc_link && ifp->if_snd.ifq_len < 10) { 3347 DC_UNLOCK(sc); 3348 return; 3349 } 3350 3351 if (ifp->if_flags & IFF_OACTIVE) { 3352 DC_UNLOCK(sc); 3353 return; 3354 } 3355 3356 idx = sc->dc_cdata.dc_tx_first = sc->dc_cdata.dc_tx_prod; 3357 3358 while (sc->dc_cdata.dc_tx_chain[idx] == NULL) { 3359 IF_DEQUEUE(&ifp->if_snd, m_head); 3360 if (m_head == NULL) 3361 break; 3362 3363 if (sc->dc_flags & DC_TX_COALESCE && 3364 (m_head->m_next != NULL || 3365 sc->dc_flags & DC_TX_ALIGN)) { 3366 m = m_defrag(m_head, M_DONTWAIT); 3367 if (m == NULL) { 3368 IF_PREPEND(&ifp->if_snd, m_head); 3369 ifp->if_flags |= IFF_OACTIVE; 3370 break; 3371 } else { 3372 m_head = m; 3373 } 3374 } 3375 3376 if (dc_encap(sc, &m_head)) { 3377 IF_PREPEND(&ifp->if_snd, m_head); 3378 ifp->if_flags |= IFF_OACTIVE; 3379 break; 3380 } 3381 idx = sc->dc_cdata.dc_tx_prod; 3382 3383 /* 3384 * If there's a BPF listener, bounce a copy of this frame 3385 * to him. 3386 */ 3387 BPF_MTAP(ifp, m_head); 3388 3389 if (sc->dc_flags & DC_TX_ONE) { 3390 ifp->if_flags |= IFF_OACTIVE; 3391 break; 3392 } 3393 } 3394 3395 /* Transmit */ 3396 if (!(sc->dc_flags & DC_TX_POLL)) 3397 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3398 3399 /* 3400 * Set a timeout in case the chip goes out to lunch. 3401 */ 3402 ifp->if_timer = 5; 3403 3404 DC_UNLOCK(sc); 3405 } 3406 3407 static void 3408 dc_init(void *xsc) 3409 { 3410 struct dc_softc *sc = xsc; 3411 struct ifnet *ifp = &sc->arpcom.ac_if; 3412 struct mii_data *mii; 3413 3414 DC_LOCK(sc); 3415 3416 mii = device_get_softc(sc->dc_miibus); 3417 3418 /* 3419 * Cancel pending I/O and free all RX/TX buffers. 3420 */ 3421 dc_stop(sc); 3422 dc_reset(sc); 3423 3424 /* 3425 * Set cache alignment and burst length. 3426 */ 3427 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 3428 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3429 else 3430 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME | DC_BUSCTL_MRLE); 3431 /* 3432 * Evenly share the bus between receive and transmit process. 3433 */ 3434 if (DC_IS_INTEL(sc)) 3435 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3436 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3437 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3438 } else { 3439 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3440 } 3441 if (sc->dc_flags & DC_TX_POLL) 3442 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3443 switch(sc->dc_cachesize) { 3444 case 32: 3445 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3446 break; 3447 case 16: 3448 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3449 break; 3450 case 8: 3451 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3452 break; 3453 case 0: 3454 default: 3455 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3456 break; 3457 } 3458 3459 if (sc->dc_flags & DC_TX_STORENFWD) 3460 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3461 else { 3462 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3463 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3464 } else { 3465 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3466 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3467 } 3468 } 3469 3470 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3471 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3472 3473 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3474 /* 3475 * The app notes for the 98713 and 98715A say that 3476 * in order to have the chips operate properly, a magic 3477 * number must be written to CSR16. Macronix does not 3478 * document the meaning of these bits so there's no way 3479 * to know exactly what they do. The 98713 has a magic 3480 * number all its own; the rest all use a different one. 3481 */ 3482 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3483 if (sc->dc_type == DC_TYPE_98713) 3484 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3485 else 3486 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3487 } 3488 3489 if (DC_IS_XIRCOM(sc)) { 3490 /* 3491 * setup General Purpose Port mode and data so the tulip 3492 * can talk to the MII. 3493 */ 3494 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3495 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3496 DELAY(10); 3497 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3498 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3499 DELAY(10); 3500 } 3501 3502 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3503 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3504 3505 /* Init circular RX list. */ 3506 if (dc_list_rx_init(sc) == ENOBUFS) { 3507 printf("dc%d: initialization failed: no " 3508 "memory for rx buffers\n", sc->dc_unit); 3509 dc_stop(sc); 3510 DC_UNLOCK(sc); 3511 return; 3512 } 3513 3514 /* 3515 * Init TX descriptors. 3516 */ 3517 dc_list_tx_init(sc); 3518 3519 /* 3520 * Load the address of the RX list. 3521 */ 3522 CSR_WRITE_4(sc, DC_RXADDR, DC_RXDESC(sc, 0)); 3523 CSR_WRITE_4(sc, DC_TXADDR, DC_TXDESC(sc, 0)); 3524 3525 /* 3526 * Enable interrupts. 3527 */ 3528 #ifdef DEVICE_POLLING 3529 /* 3530 * ... but only if we are not polling, and make sure they are off in 3531 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3532 * after a reset. 3533 */ 3534 if (ifp->if_flags & IFF_POLLING) 3535 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3536 else 3537 #endif 3538 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3539 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3540 3541 /* Enable transmitter. */ 3542 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3543 3544 /* 3545 * If this is an Intel 21143 and we're not using the 3546 * MII port, program the LED control pins so we get 3547 * link and activity indications. 3548 */ 3549 if (sc->dc_flags & DC_TULIP_LEDS) { 3550 CSR_WRITE_4(sc, DC_WATCHDOG, 3551 DC_WDOG_CTLWREN | DC_WDOG_LINK | DC_WDOG_ACTIVITY); 3552 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3553 } 3554 3555 /* 3556 * Load the RX/multicast filter. We do this sort of late 3557 * because the filter programming scheme on the 21143 and 3558 * some clones requires DMAing a setup frame via the TX 3559 * engine, and we need the transmitter enabled for that. 3560 */ 3561 dc_setfilt(sc); 3562 3563 /* Enable receiver. */ 3564 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3565 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3566 3567 mii_mediachg(mii); 3568 dc_setcfg(sc, sc->dc_if_media); 3569 3570 ifp->if_flags |= IFF_RUNNING; 3571 ifp->if_flags &= ~IFF_OACTIVE; 3572 3573 /* Don't start the ticker if this is a homePNA link. */ 3574 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) 3575 sc->dc_link = 1; 3576 else { 3577 if (sc->dc_flags & DC_21143_NWAY) 3578 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3579 else 3580 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3581 } 3582 3583 #ifdef SRM_MEDIA 3584 if(sc->dc_srm_media) { 3585 struct ifreq ifr; 3586 3587 ifr.ifr_media = sc->dc_srm_media; 3588 ifmedia_ioctl(ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA); 3589 sc->dc_srm_media = 0; 3590 } 3591 #endif 3592 DC_UNLOCK(sc); 3593 } 3594 3595 /* 3596 * Set media options. 3597 */ 3598 static int 3599 dc_ifmedia_upd(struct ifnet *ifp) 3600 { 3601 struct dc_softc *sc; 3602 struct mii_data *mii; 3603 struct ifmedia *ifm; 3604 3605 sc = ifp->if_softc; 3606 mii = device_get_softc(sc->dc_miibus); 3607 mii_mediachg(mii); 3608 ifm = &mii->mii_media; 3609 3610 if (DC_IS_DAVICOM(sc) && 3611 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) 3612 dc_setcfg(sc, ifm->ifm_media); 3613 else 3614 sc->dc_link = 0; 3615 3616 return (0); 3617 } 3618 3619 /* 3620 * Report current media status. 3621 */ 3622 static void 3623 dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3624 { 3625 struct dc_softc *sc; 3626 struct mii_data *mii; 3627 struct ifmedia *ifm; 3628 3629 sc = ifp->if_softc; 3630 mii = device_get_softc(sc->dc_miibus); 3631 mii_pollstat(mii); 3632 ifm = &mii->mii_media; 3633 if (DC_IS_DAVICOM(sc)) { 3634 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 3635 ifmr->ifm_active = ifm->ifm_media; 3636 ifmr->ifm_status = 0; 3637 return; 3638 } 3639 } 3640 ifmr->ifm_active = mii->mii_media_active; 3641 ifmr->ifm_status = mii->mii_media_status; 3642 } 3643 3644 static int 3645 dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3646 { 3647 struct dc_softc *sc = ifp->if_softc; 3648 struct ifreq *ifr = (struct ifreq *)data; 3649 struct mii_data *mii; 3650 int error = 0; 3651 3652 DC_LOCK(sc); 3653 3654 switch (command) { 3655 case SIOCSIFFLAGS: 3656 if (ifp->if_flags & IFF_UP) { 3657 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) & 3658 (IFF_PROMISC | IFF_ALLMULTI); 3659 3660 if (ifp->if_flags & IFF_RUNNING) { 3661 if (need_setfilt) 3662 dc_setfilt(sc); 3663 } else { 3664 sc->dc_txthresh = 0; 3665 dc_init(sc); 3666 } 3667 } else { 3668 if (ifp->if_flags & IFF_RUNNING) 3669 dc_stop(sc); 3670 } 3671 sc->dc_if_flags = ifp->if_flags; 3672 error = 0; 3673 break; 3674 case SIOCADDMULTI: 3675 case SIOCDELMULTI: 3676 dc_setfilt(sc); 3677 error = 0; 3678 break; 3679 case SIOCGIFMEDIA: 3680 case SIOCSIFMEDIA: 3681 mii = device_get_softc(sc->dc_miibus); 3682 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3683 #ifdef SRM_MEDIA 3684 if (sc->dc_srm_media) 3685 sc->dc_srm_media = 0; 3686 #endif 3687 break; 3688 default: 3689 error = ether_ioctl(ifp, command, data); 3690 break; 3691 } 3692 3693 DC_UNLOCK(sc); 3694 3695 return (error); 3696 } 3697 3698 static void 3699 dc_watchdog(struct ifnet *ifp) 3700 { 3701 struct dc_softc *sc; 3702 3703 sc = ifp->if_softc; 3704 3705 DC_LOCK(sc); 3706 3707 ifp->if_oerrors++; 3708 printf("dc%d: watchdog timeout\n", sc->dc_unit); 3709 3710 dc_stop(sc); 3711 dc_reset(sc); 3712 dc_init(sc); 3713 3714 if (ifp->if_snd.ifq_head != NULL) 3715 dc_start(ifp); 3716 3717 DC_UNLOCK(sc); 3718 } 3719 3720 /* 3721 * Stop the adapter and free any mbufs allocated to the 3722 * RX and TX lists. 3723 */ 3724 static void 3725 dc_stop(struct dc_softc *sc) 3726 { 3727 struct ifnet *ifp; 3728 struct dc_list_data *ld; 3729 struct dc_chain_data *cd; 3730 int i; 3731 u_int32_t ctl; 3732 3733 DC_LOCK(sc); 3734 3735 ifp = &sc->arpcom.ac_if; 3736 ifp->if_timer = 0; 3737 ld = sc->dc_ldata; 3738 cd = &sc->dc_cdata; 3739 3740 callout_stop(&sc->dc_stat_ch); 3741 3742 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3743 #ifdef DEVICE_POLLING 3744 ether_poll_deregister(ifp); 3745 #endif 3746 3747 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)); 3748 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3749 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3750 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3751 sc->dc_link = 0; 3752 3753 /* 3754 * Free data in the RX lists. 3755 */ 3756 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3757 if (cd->dc_rx_chain[i] != NULL) { 3758 m_freem(cd->dc_rx_chain[i]); 3759 cd->dc_rx_chain[i] = NULL; 3760 } 3761 } 3762 bzero(&ld->dc_rx_list, sizeof(ld->dc_rx_list)); 3763 3764 /* 3765 * Free the TX list buffers. 3766 */ 3767 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3768 if (cd->dc_tx_chain[i] != NULL) { 3769 ctl = le32toh(ld->dc_tx_list[i].dc_ctl); 3770 if ((ctl & DC_TXCTL_SETUP) || 3771 !(ctl & DC_TXCTL_FIRSTFRAG)) { 3772 cd->dc_tx_chain[i] = NULL; 3773 continue; 3774 } 3775 bus_dmamap_unload(sc->dc_mtag, cd->dc_tx_map[i]); 3776 m_freem(cd->dc_tx_chain[i]); 3777 cd->dc_tx_chain[i] = NULL; 3778 } 3779 } 3780 bzero(&ld->dc_tx_list, sizeof(ld->dc_tx_list)); 3781 3782 DC_UNLOCK(sc); 3783 } 3784 3785 /* 3786 * Device suspend routine. Stop the interface and save some PCI 3787 * settings in case the BIOS doesn't restore them properly on 3788 * resume. 3789 */ 3790 static int 3791 dc_suspend(device_t dev) 3792 { 3793 struct dc_softc *sc; 3794 int i, s; 3795 3796 s = splimp(); 3797 3798 sc = device_get_softc(dev); 3799 3800 dc_stop(sc); 3801 3802 for (i = 0; i < 5; i++) 3803 sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4); 3804 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 3805 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 3806 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 3807 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 3808 3809 sc->suspended = 1; 3810 3811 splx(s); 3812 return (0); 3813 } 3814 3815 /* 3816 * Device resume routine. Restore some PCI settings in case the BIOS 3817 * doesn't, re-enable busmastering, and restart the interface if 3818 * appropriate. 3819 */ 3820 static int 3821 dc_resume(device_t dev) 3822 { 3823 struct dc_softc *sc; 3824 struct ifnet *ifp; 3825 int i, s; 3826 3827 s = splimp(); 3828 3829 sc = device_get_softc(dev); 3830 ifp = &sc->arpcom.ac_if; 3831 #ifndef BURN_BRIDGES 3832 dc_acpi(dev); 3833 #endif 3834 /* better way to do this? */ 3835 for (i = 0; i < 5; i++) 3836 pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4); 3837 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 3838 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 3839 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 3840 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 3841 3842 /* reenable busmastering */ 3843 pci_enable_busmaster(dev); 3844 pci_enable_io(dev, DC_RES); 3845 3846 /* reinitialize interface if necessary */ 3847 if (ifp->if_flags & IFF_UP) 3848 dc_init(sc); 3849 3850 sc->suspended = 0; 3851 3852 splx(s); 3853 return (0); 3854 } 3855 3856 /* 3857 * Stop all chip I/O so that the kernel's probe routines don't 3858 * get confused by errant DMAs when rebooting. 3859 */ 3860 static void 3861 dc_shutdown(device_t dev) 3862 { 3863 struct dc_softc *sc; 3864 3865 sc = device_get_softc(dev); 3866 3867 dc_stop(sc); 3868 } 3869