1 /*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 38 * series chips and several workalikes including the following: 39 * 40 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 41 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 42 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 43 * ASIX Electronics AX88140A (www.asix.com.tw) 44 * ASIX Electronics AX88141 (www.asix.com.tw) 45 * ADMtek AL981 (www.admtek.com.tw) 46 * ADMtek AN983 (www.admtek.com.tw) 47 * ADMtek CardBus AN985 (www.admtek.com.tw) 48 * Netgear FA511 (www.netgear.com) Appears to be rebadged ADMTek CardBus AN985 49 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 50 * Accton EN1217 (www.accton.com) 51 * Xircom X3201 (www.xircom.com) 52 * Abocom FE2500 53 * Conexant LANfinity (www.conexant.com) 54 * 3Com OfficeConnect 10/100B 3CSOHO100B (www.3com.com) 55 * 56 * Datasheets for the 21143 are available at developer.intel.com. 57 * Datasheets for the clone parts can be found at their respective sites. 58 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 59 * The PNIC II is essentially a Macronix 98715A chip; the only difference 60 * worth noting is that its multicast hash table is only 128 bits wide 61 * instead of 512. 62 * 63 * Written by Bill Paul <wpaul@ee.columbia.edu> 64 * Electrical Engineering Department 65 * Columbia University, New York City 66 */ 67 /* 68 * The Intel 21143 is the successor to the DEC 21140. It is basically 69 * the same as the 21140 but with a few new features. The 21143 supports 70 * three kinds of media attachments: 71 * 72 * o MII port, for 10Mbps and 100Mbps support and NWAY 73 * autonegotiation provided by an external PHY. 74 * o SYM port, for symbol mode 100Mbps support. 75 * o 10baseT port. 76 * o AUI/BNC port. 77 * 78 * The 100Mbps SYM port and 10baseT port can be used together in 79 * combination with the internal NWAY support to create a 10/100 80 * autosensing configuration. 81 * 82 * Note that not all tulip workalikes are handled in this driver: we only 83 * deal with those which are relatively well behaved. The Winbond is 84 * handled separately due to its different register offsets and the 85 * special handling needed for its various bugs. The PNIC is handled 86 * here, but I'm not thrilled about it. 87 * 88 * All of the workalike chips use some form of MII transceiver support 89 * with the exception of the Macronix chips, which also have a SYM port. 90 * The ASIX AX88140A is also documented to have a SYM port, but all 91 * the cards I've seen use an MII transceiver, probably because the 92 * AX88140A doesn't support internal NWAY. 93 */ 94 95 #ifdef HAVE_KERNEL_OPTION_HEADERS 96 #include "opt_device_polling.h" 97 #endif 98 99 #include <sys/param.h> 100 #include <sys/endian.h> 101 #include <sys/systm.h> 102 #include <sys/sockio.h> 103 #include <sys/mbuf.h> 104 #include <sys/malloc.h> 105 #include <sys/kernel.h> 106 #include <sys/module.h> 107 #include <sys/socket.h> 108 109 #include <net/if.h> 110 #include <net/if_arp.h> 111 #include <net/ethernet.h> 112 #include <net/if_dl.h> 113 #include <net/if_media.h> 114 #include <net/if_types.h> 115 #include <net/if_vlan_var.h> 116 117 #include <net/bpf.h> 118 119 #include <machine/bus.h> 120 #include <machine/resource.h> 121 #include <sys/bus.h> 122 #include <sys/rman.h> 123 124 #include <dev/mii/mii.h> 125 #include <dev/mii/mii_bitbang.h> 126 #include <dev/mii/miivar.h> 127 128 #include <dev/pci/pcireg.h> 129 #include <dev/pci/pcivar.h> 130 131 #define DC_USEIOSPACE 132 133 #include <dev/dc/if_dcreg.h> 134 135 #ifdef __sparc64__ 136 #include <dev/ofw/openfirm.h> 137 #include <machine/ofw_machdep.h> 138 #endif 139 140 MODULE_DEPEND(dc, pci, 1, 1, 1); 141 MODULE_DEPEND(dc, ether, 1, 1, 1); 142 MODULE_DEPEND(dc, miibus, 1, 1, 1); 143 144 /* 145 * "device miibus" is required in kernel config. See GENERIC if you get 146 * errors here. 147 */ 148 #include "miibus_if.h" 149 150 /* 151 * Various supported device vendors/types and their names. 152 */ 153 static const struct dc_type const dc_devs[] = { 154 { DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143), 0, 155 "Intel 21143 10/100BaseTX" }, 156 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009), 0, 157 "Davicom DM9009 10/100BaseTX" }, 158 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100), 0, 159 "Davicom DM9100 10/100BaseTX" }, 160 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), DC_REVISION_DM9102A, 161 "Davicom DM9102A 10/100BaseTX" }, 162 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), 0, 163 "Davicom DM9102 10/100BaseTX" }, 164 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981), 0, 165 "ADMtek AL981 10/100BaseTX" }, 166 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN983), 0, 167 "ADMtek AN983 10/100BaseTX" }, 168 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985), 0, 169 "ADMtek AN985 CardBus 10/100BaseTX or clone" }, 170 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511), 0, 171 "ADMtek ADM9511 10/100BaseTX" }, 172 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513), 0, 173 "ADMtek ADM9513 10/100BaseTX" }, 174 { DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), DC_REVISION_88141, 175 "ASIX AX88141 10/100BaseTX" }, 176 { DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), 0, 177 "ASIX AX88140A 10/100BaseTX" }, 178 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), DC_REVISION_98713A, 179 "Macronix 98713A 10/100BaseTX" }, 180 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), 0, 181 "Macronix 98713 10/100BaseTX" }, 182 { DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), DC_REVISION_98713A, 183 "Compex RL100-TX 10/100BaseTX" }, 184 { DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), 0, 185 "Compex RL100-TX 10/100BaseTX" }, 186 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98725, 187 "Macronix 98725 10/100BaseTX" }, 188 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98715AEC_C, 189 "Macronix 98715AEC-C 10/100BaseTX" }, 190 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), 0, 191 "Macronix 98715/98715A 10/100BaseTX" }, 192 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727), 0, 193 "Macronix 98727/98732 10/100BaseTX" }, 194 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115), 0, 195 "LC82C115 PNIC II 10/100BaseTX" }, 196 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), DC_REVISION_82C169, 197 "82c169 PNIC 10/100BaseTX" }, 198 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), 0, 199 "82c168 PNIC 10/100BaseTX" }, 200 { DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217), 0, 201 "Accton EN1217 10/100BaseTX" }, 202 { DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242), 0, 203 "Accton EN2242 MiniPCI 10/100BaseTX" }, 204 { DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201), 0, 205 "Xircom X3201 10/100BaseTX" }, 206 { DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD), 0, 207 "Neteasy DRP-32TXD Cardbus 10/100" }, 208 { DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500), 0, 209 "Abocom FE2500 10/100BaseTX" }, 210 { DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX), 0, 211 "Abocom FE2500MX 10/100BaseTX" }, 212 { DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112), 0, 213 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 214 { DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX), 0, 215 "Hawking CB102 CardBus 10/100" }, 216 { DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T), 0, 217 "PlaneX FNW-3602-T CardBus 10/100" }, 218 { DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB), 0, 219 "3Com OfficeConnect 10/100B" }, 220 { DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120), 0, 221 "Microsoft MN-120 CardBus 10/100" }, 222 { DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130), 0, 223 "Microsoft MN-130 10/100" }, 224 { DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08), 0, 225 "Linksys PCMPC200 CardBus 10/100" }, 226 { DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09), 0, 227 "Linksys PCMPC200 CardBus 10/100" }, 228 { DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5261), 0, 229 "ULi M5261 FastEthernet" }, 230 { DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5263), 0, 231 "ULi M5263 FastEthernet" }, 232 { 0, 0, NULL } 233 }; 234 235 static int dc_probe(device_t); 236 static int dc_attach(device_t); 237 static int dc_detach(device_t); 238 static int dc_suspend(device_t); 239 static int dc_resume(device_t); 240 static const struct dc_type *dc_devtype(device_t); 241 static void dc_discard_rxbuf(struct dc_softc *, int); 242 static int dc_newbuf(struct dc_softc *, int); 243 static int dc_encap(struct dc_softc *, struct mbuf **); 244 static void dc_pnic_rx_bug_war(struct dc_softc *, int); 245 static int dc_rx_resync(struct dc_softc *); 246 static int dc_rxeof(struct dc_softc *); 247 static void dc_txeof(struct dc_softc *); 248 static void dc_tick(void *); 249 static void dc_tx_underrun(struct dc_softc *); 250 static void dc_intr(void *); 251 static void dc_start(struct ifnet *); 252 static void dc_start_locked(struct ifnet *); 253 static int dc_ioctl(struct ifnet *, u_long, caddr_t); 254 static void dc_init(void *); 255 static void dc_init_locked(struct dc_softc *); 256 static void dc_stop(struct dc_softc *); 257 static void dc_watchdog(void *); 258 static int dc_shutdown(device_t); 259 static int dc_ifmedia_upd(struct ifnet *); 260 static int dc_ifmedia_upd_locked(struct dc_softc *); 261 static void dc_ifmedia_sts(struct ifnet *, struct ifmediareq *); 262 263 static int dc_dma_alloc(struct dc_softc *); 264 static void dc_dma_free(struct dc_softc *); 265 static void dc_dma_map_addr(void *, bus_dma_segment_t *, int, int); 266 267 static void dc_delay(struct dc_softc *); 268 static void dc_eeprom_idle(struct dc_softc *); 269 static void dc_eeprom_putbyte(struct dc_softc *, int); 270 static void dc_eeprom_getword(struct dc_softc *, int, uint16_t *); 271 static void dc_eeprom_getword_pnic(struct dc_softc *, int, uint16_t *); 272 static void dc_eeprom_getword_xircom(struct dc_softc *, int, uint16_t *); 273 static void dc_eeprom_width(struct dc_softc *); 274 static void dc_read_eeprom(struct dc_softc *, caddr_t, int, int, int); 275 276 static int dc_miibus_readreg(device_t, int, int); 277 static int dc_miibus_writereg(device_t, int, int, int); 278 static void dc_miibus_statchg(device_t); 279 static void dc_miibus_mediainit(device_t); 280 281 static void dc_setcfg(struct dc_softc *, int); 282 static void dc_netcfg_wait(struct dc_softc *); 283 static uint32_t dc_mchash_le(struct dc_softc *, const uint8_t *); 284 static uint32_t dc_mchash_be(const uint8_t *); 285 static void dc_setfilt_21143(struct dc_softc *); 286 static void dc_setfilt_asix(struct dc_softc *); 287 static void dc_setfilt_admtek(struct dc_softc *); 288 static void dc_setfilt_uli(struct dc_softc *); 289 static void dc_setfilt_xircom(struct dc_softc *); 290 291 static void dc_setfilt(struct dc_softc *); 292 293 static void dc_reset(struct dc_softc *); 294 static int dc_list_rx_init(struct dc_softc *); 295 static int dc_list_tx_init(struct dc_softc *); 296 297 static int dc_read_srom(struct dc_softc *, int); 298 static int dc_parse_21143_srom(struct dc_softc *); 299 static int dc_decode_leaf_sia(struct dc_softc *, struct dc_eblock_sia *); 300 static int dc_decode_leaf_mii(struct dc_softc *, struct dc_eblock_mii *); 301 static int dc_decode_leaf_sym(struct dc_softc *, struct dc_eblock_sym *); 302 static void dc_apply_fixup(struct dc_softc *, int); 303 static int dc_check_multiport(struct dc_softc *); 304 305 /* 306 * MII bit-bang glue 307 */ 308 static uint32_t dc_mii_bitbang_read(device_t); 309 static void dc_mii_bitbang_write(device_t, uint32_t); 310 311 static const struct mii_bitbang_ops dc_mii_bitbang_ops = { 312 dc_mii_bitbang_read, 313 dc_mii_bitbang_write, 314 { 315 DC_SIO_MII_DATAOUT, /* MII_BIT_MDO */ 316 DC_SIO_MII_DATAIN, /* MII_BIT_MDI */ 317 DC_SIO_MII_CLK, /* MII_BIT_MDC */ 318 0, /* MII_BIT_DIR_HOST_PHY */ 319 DC_SIO_MII_DIR, /* MII_BIT_DIR_PHY_HOST */ 320 } 321 }; 322 323 #ifdef DC_USEIOSPACE 324 #define DC_RES SYS_RES_IOPORT 325 #define DC_RID DC_PCI_CFBIO 326 #else 327 #define DC_RES SYS_RES_MEMORY 328 #define DC_RID DC_PCI_CFBMA 329 #endif 330 331 static device_method_t dc_methods[] = { 332 /* Device interface */ 333 DEVMETHOD(device_probe, dc_probe), 334 DEVMETHOD(device_attach, dc_attach), 335 DEVMETHOD(device_detach, dc_detach), 336 DEVMETHOD(device_suspend, dc_suspend), 337 DEVMETHOD(device_resume, dc_resume), 338 DEVMETHOD(device_shutdown, dc_shutdown), 339 340 /* bus interface */ 341 DEVMETHOD(bus_print_child, bus_generic_print_child), 342 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 343 344 /* MII interface */ 345 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 346 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 347 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 348 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 349 350 { 0, 0 } 351 }; 352 353 static driver_t dc_driver = { 354 "dc", 355 dc_methods, 356 sizeof(struct dc_softc) 357 }; 358 359 static devclass_t dc_devclass; 360 361 DRIVER_MODULE(dc, pci, dc_driver, dc_devclass, 0, 0); 362 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 363 364 #define DC_SETBIT(sc, reg, x) \ 365 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 366 367 #define DC_CLRBIT(sc, reg, x) \ 368 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 369 370 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 371 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 372 373 static void 374 dc_delay(struct dc_softc *sc) 375 { 376 int idx; 377 378 for (idx = (300 / 33) + 1; idx > 0; idx--) 379 CSR_READ_4(sc, DC_BUSCTL); 380 } 381 382 static void 383 dc_eeprom_width(struct dc_softc *sc) 384 { 385 int i; 386 387 /* Force EEPROM to idle state. */ 388 dc_eeprom_idle(sc); 389 390 /* Enter EEPROM access mode. */ 391 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 392 dc_delay(sc); 393 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 394 dc_delay(sc); 395 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 396 dc_delay(sc); 397 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 398 dc_delay(sc); 399 400 for (i = 3; i--;) { 401 if (6 & (1 << i)) 402 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 403 else 404 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 405 dc_delay(sc); 406 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 407 dc_delay(sc); 408 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 409 dc_delay(sc); 410 } 411 412 for (i = 1; i <= 12; i++) { 413 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 414 dc_delay(sc); 415 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { 416 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 417 dc_delay(sc); 418 break; 419 } 420 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 421 dc_delay(sc); 422 } 423 424 /* Turn off EEPROM access mode. */ 425 dc_eeprom_idle(sc); 426 427 if (i < 4 || i > 12) 428 sc->dc_romwidth = 6; 429 else 430 sc->dc_romwidth = i; 431 432 /* Enter EEPROM access mode. */ 433 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 434 dc_delay(sc); 435 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 436 dc_delay(sc); 437 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 438 dc_delay(sc); 439 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 440 dc_delay(sc); 441 442 /* Turn off EEPROM access mode. */ 443 dc_eeprom_idle(sc); 444 } 445 446 static void 447 dc_eeprom_idle(struct dc_softc *sc) 448 { 449 int i; 450 451 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 452 dc_delay(sc); 453 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 454 dc_delay(sc); 455 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 456 dc_delay(sc); 457 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 458 dc_delay(sc); 459 460 for (i = 0; i < 25; i++) { 461 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 462 dc_delay(sc); 463 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 464 dc_delay(sc); 465 } 466 467 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 468 dc_delay(sc); 469 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 470 dc_delay(sc); 471 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 472 } 473 474 /* 475 * Send a read command and address to the EEPROM, check for ACK. 476 */ 477 static void 478 dc_eeprom_putbyte(struct dc_softc *sc, int addr) 479 { 480 int d, i; 481 482 d = DC_EECMD_READ >> 6; 483 for (i = 3; i--; ) { 484 if (d & (1 << i)) 485 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 486 else 487 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 488 dc_delay(sc); 489 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 490 dc_delay(sc); 491 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 492 dc_delay(sc); 493 } 494 495 /* 496 * Feed in each bit and strobe the clock. 497 */ 498 for (i = sc->dc_romwidth; i--;) { 499 if (addr & (1 << i)) { 500 SIO_SET(DC_SIO_EE_DATAIN); 501 } else { 502 SIO_CLR(DC_SIO_EE_DATAIN); 503 } 504 dc_delay(sc); 505 SIO_SET(DC_SIO_EE_CLK); 506 dc_delay(sc); 507 SIO_CLR(DC_SIO_EE_CLK); 508 dc_delay(sc); 509 } 510 } 511 512 /* 513 * Read a word of data stored in the EEPROM at address 'addr.' 514 * The PNIC 82c168/82c169 has its own non-standard way to read 515 * the EEPROM. 516 */ 517 static void 518 dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, uint16_t *dest) 519 { 520 int i; 521 uint32_t r; 522 523 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr); 524 525 for (i = 0; i < DC_TIMEOUT; i++) { 526 DELAY(1); 527 r = CSR_READ_4(sc, DC_SIO); 528 if (!(r & DC_PN_SIOCTL_BUSY)) { 529 *dest = (uint16_t)(r & 0xFFFF); 530 return; 531 } 532 } 533 } 534 535 /* 536 * Read a word of data stored in the EEPROM at address 'addr.' 537 * The Xircom X3201 has its own non-standard way to read 538 * the EEPROM, too. 539 */ 540 static void 541 dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, uint16_t *dest) 542 { 543 544 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 545 546 addr *= 2; 547 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 548 *dest = (uint16_t)CSR_READ_4(sc, DC_SIO) & 0xff; 549 addr += 1; 550 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 551 *dest |= ((uint16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8; 552 553 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 554 } 555 556 /* 557 * Read a word of data stored in the EEPROM at address 'addr.' 558 */ 559 static void 560 dc_eeprom_getword(struct dc_softc *sc, int addr, uint16_t *dest) 561 { 562 int i; 563 uint16_t word = 0; 564 565 /* Force EEPROM to idle state. */ 566 dc_eeprom_idle(sc); 567 568 /* Enter EEPROM access mode. */ 569 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 570 dc_delay(sc); 571 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 572 dc_delay(sc); 573 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 574 dc_delay(sc); 575 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 576 dc_delay(sc); 577 578 /* 579 * Send address of word we want to read. 580 */ 581 dc_eeprom_putbyte(sc, addr); 582 583 /* 584 * Start reading bits from EEPROM. 585 */ 586 for (i = 0x8000; i; i >>= 1) { 587 SIO_SET(DC_SIO_EE_CLK); 588 dc_delay(sc); 589 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 590 word |= i; 591 dc_delay(sc); 592 SIO_CLR(DC_SIO_EE_CLK); 593 dc_delay(sc); 594 } 595 596 /* Turn off EEPROM access mode. */ 597 dc_eeprom_idle(sc); 598 599 *dest = word; 600 } 601 602 /* 603 * Read a sequence of words from the EEPROM. 604 */ 605 static void 606 dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int be) 607 { 608 int i; 609 uint16_t word = 0, *ptr; 610 611 for (i = 0; i < cnt; i++) { 612 if (DC_IS_PNIC(sc)) 613 dc_eeprom_getword_pnic(sc, off + i, &word); 614 else if (DC_IS_XIRCOM(sc)) 615 dc_eeprom_getword_xircom(sc, off + i, &word); 616 else 617 dc_eeprom_getword(sc, off + i, &word); 618 ptr = (uint16_t *)(dest + (i * 2)); 619 if (be) 620 *ptr = be16toh(word); 621 else 622 *ptr = le16toh(word); 623 } 624 } 625 626 /* 627 * Write the MII serial port for the MII bit-bang module. 628 */ 629 static void 630 dc_mii_bitbang_write(device_t dev, uint32_t val) 631 { 632 struct dc_softc *sc; 633 634 sc = device_get_softc(dev); 635 636 CSR_WRITE_4(sc, DC_SIO, val); 637 CSR_BARRIER_4(sc, DC_SIO, 638 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 639 } 640 641 /* 642 * Read the MII serial port for the MII bit-bang module. 643 */ 644 static uint32_t 645 dc_mii_bitbang_read(device_t dev) 646 { 647 struct dc_softc *sc; 648 uint32_t val; 649 650 sc = device_get_softc(dev); 651 652 val = CSR_READ_4(sc, DC_SIO); 653 CSR_BARRIER_4(sc, DC_SIO, 654 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 655 656 return (val); 657 } 658 659 static int 660 dc_miibus_readreg(device_t dev, int phy, int reg) 661 { 662 struct dc_softc *sc; 663 int i, rval, phy_reg = 0; 664 665 sc = device_get_softc(dev); 666 667 if (sc->dc_pmode != DC_PMODE_MII) { 668 if (phy == (MII_NPHY - 1)) { 669 switch (reg) { 670 case MII_BMSR: 671 /* 672 * Fake something to make the probe 673 * code think there's a PHY here. 674 */ 675 return (BMSR_MEDIAMASK); 676 break; 677 case MII_PHYIDR1: 678 if (DC_IS_PNIC(sc)) 679 return (DC_VENDORID_LO); 680 return (DC_VENDORID_DEC); 681 break; 682 case MII_PHYIDR2: 683 if (DC_IS_PNIC(sc)) 684 return (DC_DEVICEID_82C168); 685 return (DC_DEVICEID_21143); 686 break; 687 default: 688 return (0); 689 break; 690 } 691 } else 692 return (0); 693 } 694 695 if (DC_IS_PNIC(sc)) { 696 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 697 (phy << 23) | (reg << 18)); 698 for (i = 0; i < DC_TIMEOUT; i++) { 699 DELAY(1); 700 rval = CSR_READ_4(sc, DC_PN_MII); 701 if (!(rval & DC_PN_MII_BUSY)) { 702 rval &= 0xFFFF; 703 return (rval == 0xFFFF ? 0 : rval); 704 } 705 } 706 return (0); 707 } 708 709 if (sc->dc_type == DC_TYPE_ULI_M5263) { 710 CSR_WRITE_4(sc, DC_ROM, 711 ((phy << DC_ULI_PHY_ADDR_SHIFT) & DC_ULI_PHY_ADDR_MASK) | 712 ((reg << DC_ULI_PHY_REG_SHIFT) & DC_ULI_PHY_REG_MASK) | 713 DC_ULI_PHY_OP_READ); 714 for (i = 0; i < DC_TIMEOUT; i++) { 715 DELAY(1); 716 rval = CSR_READ_4(sc, DC_ROM); 717 if ((rval & DC_ULI_PHY_OP_DONE) != 0) { 718 return (rval & DC_ULI_PHY_DATA_MASK); 719 } 720 } 721 if (i == DC_TIMEOUT) 722 device_printf(dev, "phy read timed out\n"); 723 return (0); 724 } 725 726 if (DC_IS_COMET(sc)) { 727 switch (reg) { 728 case MII_BMCR: 729 phy_reg = DC_AL_BMCR; 730 break; 731 case MII_BMSR: 732 phy_reg = DC_AL_BMSR; 733 break; 734 case MII_PHYIDR1: 735 phy_reg = DC_AL_VENID; 736 break; 737 case MII_PHYIDR2: 738 phy_reg = DC_AL_DEVID; 739 break; 740 case MII_ANAR: 741 phy_reg = DC_AL_ANAR; 742 break; 743 case MII_ANLPAR: 744 phy_reg = DC_AL_LPAR; 745 break; 746 case MII_ANER: 747 phy_reg = DC_AL_ANER; 748 break; 749 default: 750 device_printf(dev, "phy_read: bad phy register %x\n", 751 reg); 752 return (0); 753 break; 754 } 755 756 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 757 if (rval == 0xFFFF) 758 return (0); 759 return (rval); 760 } 761 762 if (sc->dc_type == DC_TYPE_98713) { 763 phy_reg = CSR_READ_4(sc, DC_NETCFG); 764 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 765 } 766 rval = mii_bitbang_readreg(dev, &dc_mii_bitbang_ops, phy, reg); 767 if (sc->dc_type == DC_TYPE_98713) 768 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 769 770 return (rval); 771 } 772 773 static int 774 dc_miibus_writereg(device_t dev, int phy, int reg, int data) 775 { 776 struct dc_softc *sc; 777 int i, phy_reg = 0; 778 779 sc = device_get_softc(dev); 780 781 if (DC_IS_PNIC(sc)) { 782 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 783 (phy << 23) | (reg << 10) | data); 784 for (i = 0; i < DC_TIMEOUT; i++) { 785 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 786 break; 787 } 788 return (0); 789 } 790 791 if (sc->dc_type == DC_TYPE_ULI_M5263) { 792 CSR_WRITE_4(sc, DC_ROM, 793 ((phy << DC_ULI_PHY_ADDR_SHIFT) & DC_ULI_PHY_ADDR_MASK) | 794 ((reg << DC_ULI_PHY_REG_SHIFT) & DC_ULI_PHY_REG_MASK) | 795 ((data << DC_ULI_PHY_DATA_SHIFT) & DC_ULI_PHY_DATA_MASK) | 796 DC_ULI_PHY_OP_WRITE); 797 DELAY(1); 798 return (0); 799 } 800 801 if (DC_IS_COMET(sc)) { 802 switch (reg) { 803 case MII_BMCR: 804 phy_reg = DC_AL_BMCR; 805 break; 806 case MII_BMSR: 807 phy_reg = DC_AL_BMSR; 808 break; 809 case MII_PHYIDR1: 810 phy_reg = DC_AL_VENID; 811 break; 812 case MII_PHYIDR2: 813 phy_reg = DC_AL_DEVID; 814 break; 815 case MII_ANAR: 816 phy_reg = DC_AL_ANAR; 817 break; 818 case MII_ANLPAR: 819 phy_reg = DC_AL_LPAR; 820 break; 821 case MII_ANER: 822 phy_reg = DC_AL_ANER; 823 break; 824 default: 825 device_printf(dev, "phy_write: bad phy register %x\n", 826 reg); 827 return (0); 828 break; 829 } 830 831 CSR_WRITE_4(sc, phy_reg, data); 832 return (0); 833 } 834 835 if (sc->dc_type == DC_TYPE_98713) { 836 phy_reg = CSR_READ_4(sc, DC_NETCFG); 837 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 838 } 839 mii_bitbang_writereg(dev, &dc_mii_bitbang_ops, phy, reg, data); 840 if (sc->dc_type == DC_TYPE_98713) 841 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 842 843 return (0); 844 } 845 846 static void 847 dc_miibus_statchg(device_t dev) 848 { 849 struct dc_softc *sc; 850 struct ifnet *ifp; 851 struct mii_data *mii; 852 struct ifmedia *ifm; 853 854 sc = device_get_softc(dev); 855 856 mii = device_get_softc(sc->dc_miibus); 857 ifp = sc->dc_ifp; 858 if (mii == NULL || ifp == NULL || 859 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 860 return; 861 862 ifm = &mii->mii_media; 863 if (DC_IS_DAVICOM(sc) && 864 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 865 dc_setcfg(sc, ifm->ifm_media); 866 sc->dc_if_media = ifm->ifm_media; 867 return; 868 } 869 870 sc->dc_link = 0; 871 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 872 (IFM_ACTIVE | IFM_AVALID)) { 873 switch (IFM_SUBTYPE(mii->mii_media_active)) { 874 case IFM_10_T: 875 case IFM_100_TX: 876 sc->dc_link = 1; 877 break; 878 default: 879 break; 880 } 881 } 882 if (sc->dc_link == 0) 883 return; 884 885 sc->dc_if_media = mii->mii_media_active; 886 if (DC_IS_ADMTEK(sc)) 887 return; 888 dc_setcfg(sc, mii->mii_media_active); 889 } 890 891 /* 892 * Special support for DM9102A cards with HomePNA PHYs. Note: 893 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 894 * to be impossible to talk to the management interface of the DM9801 895 * PHY (its MDIO pin is not connected to anything). Consequently, 896 * the driver has to just 'know' about the additional mode and deal 897 * with it itself. *sigh* 898 */ 899 static void 900 dc_miibus_mediainit(device_t dev) 901 { 902 struct dc_softc *sc; 903 struct mii_data *mii; 904 struct ifmedia *ifm; 905 int rev; 906 907 rev = pci_get_revid(dev); 908 909 sc = device_get_softc(dev); 910 mii = device_get_softc(sc->dc_miibus); 911 ifm = &mii->mii_media; 912 913 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 914 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL); 915 } 916 917 #define DC_BITS_512 9 918 #define DC_BITS_128 7 919 #define DC_BITS_64 6 920 921 static uint32_t 922 dc_mchash_le(struct dc_softc *sc, const uint8_t *addr) 923 { 924 uint32_t crc; 925 926 /* Compute CRC for the address value. */ 927 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 928 929 /* 930 * The hash table on the PNIC II and the MX98715AEC-C/D/E 931 * chips is only 128 bits wide. 932 */ 933 if (sc->dc_flags & DC_128BIT_HASH) 934 return (crc & ((1 << DC_BITS_128) - 1)); 935 936 /* The hash table on the MX98715BEC is only 64 bits wide. */ 937 if (sc->dc_flags & DC_64BIT_HASH) 938 return (crc & ((1 << DC_BITS_64) - 1)); 939 940 /* Xircom's hash filtering table is different (read: weird) */ 941 /* Xircom uses the LEAST significant bits */ 942 if (DC_IS_XIRCOM(sc)) { 943 if ((crc & 0x180) == 0x180) 944 return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4)); 945 else 946 return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 + 947 (12 << 4)); 948 } 949 950 return (crc & ((1 << DC_BITS_512) - 1)); 951 } 952 953 /* 954 * Calculate CRC of a multicast group address, return the lower 6 bits. 955 */ 956 static uint32_t 957 dc_mchash_be(const uint8_t *addr) 958 { 959 uint32_t crc; 960 961 /* Compute CRC for the address value. */ 962 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 963 964 /* Return the filter bit position. */ 965 return ((crc >> 26) & 0x0000003F); 966 } 967 968 /* 969 * 21143-style RX filter setup routine. Filter programming is done by 970 * downloading a special setup frame into the TX engine. 21143, Macronix, 971 * PNIC, PNIC II and Davicom chips are programmed this way. 972 * 973 * We always program the chip using 'hash perfect' mode, i.e. one perfect 974 * address (our node address) and a 512-bit hash filter for multicast 975 * frames. We also sneak the broadcast address into the hash filter since 976 * we need that too. 977 */ 978 static void 979 dc_setfilt_21143(struct dc_softc *sc) 980 { 981 uint16_t eaddr[(ETHER_ADDR_LEN+1)/2]; 982 struct dc_desc *sframe; 983 uint32_t h, *sp; 984 struct ifmultiaddr *ifma; 985 struct ifnet *ifp; 986 int i; 987 988 ifp = sc->dc_ifp; 989 990 i = sc->dc_cdata.dc_tx_prod; 991 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 992 sc->dc_cdata.dc_tx_cnt++; 993 sframe = &sc->dc_ldata.dc_tx_list[i]; 994 sp = sc->dc_cdata.dc_sbuf; 995 bzero(sp, DC_SFRAME_LEN); 996 997 sframe->dc_data = htole32(DC_ADDR_LO(sc->dc_saddr)); 998 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 999 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1000 1001 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1002 1003 /* If we want promiscuous mode, set the allframes bit. */ 1004 if (ifp->if_flags & IFF_PROMISC) 1005 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1006 else 1007 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1008 1009 if (ifp->if_flags & IFF_ALLMULTI) 1010 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1011 else 1012 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1013 1014 if_maddr_rlock(ifp); 1015 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1016 if (ifma->ifma_addr->sa_family != AF_LINK) 1017 continue; 1018 h = dc_mchash_le(sc, 1019 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1020 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1021 } 1022 if_maddr_runlock(ifp); 1023 1024 if (ifp->if_flags & IFF_BROADCAST) { 1025 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1026 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1027 } 1028 1029 /* Set our MAC address. */ 1030 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1031 sp[39] = DC_SP_MAC(eaddr[0]); 1032 sp[40] = DC_SP_MAC(eaddr[1]); 1033 sp[41] = DC_SP_MAC(eaddr[2]); 1034 1035 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1036 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, BUS_DMASYNC_PREREAD | 1037 BUS_DMASYNC_PREWRITE); 1038 bus_dmamap_sync(sc->dc_stag, sc->dc_smap, BUS_DMASYNC_PREWRITE); 1039 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1040 1041 /* 1042 * The PNIC takes an exceedingly long time to process its 1043 * setup frame; wait 10ms after posting the setup frame 1044 * before proceeding, just so it has time to swallow its 1045 * medicine. 1046 */ 1047 DELAY(10000); 1048 1049 sc->dc_wdog_timer = 5; 1050 } 1051 1052 static void 1053 dc_setfilt_admtek(struct dc_softc *sc) 1054 { 1055 uint8_t eaddr[ETHER_ADDR_LEN]; 1056 struct ifnet *ifp; 1057 struct ifmultiaddr *ifma; 1058 int h = 0; 1059 uint32_t hashes[2] = { 0, 0 }; 1060 1061 ifp = sc->dc_ifp; 1062 1063 /* Init our MAC address. */ 1064 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1065 CSR_WRITE_4(sc, DC_AL_PAR0, eaddr[3] << 24 | eaddr[2] << 16 | 1066 eaddr[1] << 8 | eaddr[0]); 1067 CSR_WRITE_4(sc, DC_AL_PAR1, eaddr[5] << 8 | eaddr[4]); 1068 1069 /* If we want promiscuous mode, set the allframes bit. */ 1070 if (ifp->if_flags & IFF_PROMISC) 1071 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1072 else 1073 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1074 1075 if (ifp->if_flags & IFF_ALLMULTI) 1076 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1077 else 1078 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1079 1080 /* First, zot all the existing hash bits. */ 1081 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1082 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1083 1084 /* 1085 * If we're already in promisc or allmulti mode, we 1086 * don't have to bother programming the multicast filter. 1087 */ 1088 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1089 return; 1090 1091 /* Now program new ones. */ 1092 if_maddr_rlock(ifp); 1093 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1094 if (ifma->ifma_addr->sa_family != AF_LINK) 1095 continue; 1096 if (DC_IS_CENTAUR(sc)) 1097 h = dc_mchash_le(sc, 1098 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1099 else 1100 h = dc_mchash_be( 1101 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1102 if (h < 32) 1103 hashes[0] |= (1 << h); 1104 else 1105 hashes[1] |= (1 << (h - 32)); 1106 } 1107 if_maddr_runlock(ifp); 1108 1109 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1110 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1111 } 1112 1113 static void 1114 dc_setfilt_asix(struct dc_softc *sc) 1115 { 1116 uint32_t eaddr[(ETHER_ADDR_LEN+3)/4]; 1117 struct ifnet *ifp; 1118 struct ifmultiaddr *ifma; 1119 int h = 0; 1120 uint32_t hashes[2] = { 0, 0 }; 1121 1122 ifp = sc->dc_ifp; 1123 1124 /* Init our MAC address. */ 1125 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1126 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1127 CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[0]); 1128 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1129 CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[1]); 1130 1131 /* If we want promiscuous mode, set the allframes bit. */ 1132 if (ifp->if_flags & IFF_PROMISC) 1133 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1134 else 1135 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1136 1137 if (ifp->if_flags & IFF_ALLMULTI) 1138 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1139 else 1140 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1141 1142 /* 1143 * The ASIX chip has a special bit to enable reception 1144 * of broadcast frames. 1145 */ 1146 if (ifp->if_flags & IFF_BROADCAST) 1147 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1148 else 1149 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1150 1151 /* first, zot all the existing hash bits */ 1152 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1153 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1154 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1155 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1156 1157 /* 1158 * If we're already in promisc or allmulti mode, we 1159 * don't have to bother programming the multicast filter. 1160 */ 1161 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1162 return; 1163 1164 /* now program new ones */ 1165 if_maddr_rlock(ifp); 1166 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1167 if (ifma->ifma_addr->sa_family != AF_LINK) 1168 continue; 1169 h = dc_mchash_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1170 if (h < 32) 1171 hashes[0] |= (1 << h); 1172 else 1173 hashes[1] |= (1 << (h - 32)); 1174 } 1175 if_maddr_runlock(ifp); 1176 1177 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1178 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1179 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1180 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1181 } 1182 1183 static void 1184 dc_setfilt_uli(struct dc_softc *sc) 1185 { 1186 uint8_t eaddr[ETHER_ADDR_LEN]; 1187 struct ifnet *ifp; 1188 struct ifmultiaddr *ifma; 1189 struct dc_desc *sframe; 1190 uint32_t filter, *sp; 1191 uint8_t *ma; 1192 int i, mcnt; 1193 1194 ifp = sc->dc_ifp; 1195 1196 i = sc->dc_cdata.dc_tx_prod; 1197 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1198 sc->dc_cdata.dc_tx_cnt++; 1199 sframe = &sc->dc_ldata.dc_tx_list[i]; 1200 sp = sc->dc_cdata.dc_sbuf; 1201 bzero(sp, DC_SFRAME_LEN); 1202 1203 sframe->dc_data = htole32(DC_ADDR_LO(sc->dc_saddr)); 1204 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1205 DC_TXCTL_TLINK | DC_FILTER_PERFECT | DC_TXCTL_FINT); 1206 1207 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1208 1209 /* Set station address. */ 1210 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1211 *sp++ = DC_SP_MAC(eaddr[1] << 8 | eaddr[0]); 1212 *sp++ = DC_SP_MAC(eaddr[3] << 8 | eaddr[2]); 1213 *sp++ = DC_SP_MAC(eaddr[5] << 8 | eaddr[4]); 1214 1215 /* Set broadcast address. */ 1216 *sp++ = DC_SP_MAC(0xFFFF); 1217 *sp++ = DC_SP_MAC(0xFFFF); 1218 *sp++ = DC_SP_MAC(0xFFFF); 1219 1220 /* Extract current filter configuration. */ 1221 filter = CSR_READ_4(sc, DC_NETCFG); 1222 filter &= ~(DC_NETCFG_RX_PROMISC | DC_NETCFG_RX_ALLMULTI); 1223 1224 /* Now build perfect filters. */ 1225 mcnt = 0; 1226 if_maddr_rlock(ifp); 1227 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1228 if (ifma->ifma_addr->sa_family != AF_LINK) 1229 continue; 1230 if (mcnt >= DC_ULI_FILTER_NPERF) { 1231 filter |= DC_NETCFG_RX_ALLMULTI; 1232 break; 1233 } 1234 ma = LLADDR((struct sockaddr_dl *)ifma->ifma_addr); 1235 *sp++ = DC_SP_MAC(ma[1] << 8 | ma[0]); 1236 *sp++ = DC_SP_MAC(ma[3] << 8 | ma[2]); 1237 *sp++ = DC_SP_MAC(ma[5] << 8 | ma[4]); 1238 mcnt++; 1239 } 1240 if_maddr_runlock(ifp); 1241 1242 for (; mcnt < DC_ULI_FILTER_NPERF; mcnt++) { 1243 *sp++ = DC_SP_MAC(0xFFFF); 1244 *sp++ = DC_SP_MAC(0xFFFF); 1245 *sp++ = DC_SP_MAC(0xFFFF); 1246 } 1247 1248 if (filter & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) 1249 CSR_WRITE_4(sc, DC_NETCFG, 1250 filter & ~(DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1251 if (ifp->if_flags & IFF_PROMISC) 1252 filter |= DC_NETCFG_RX_PROMISC | DC_NETCFG_RX_ALLMULTI; 1253 if (ifp->if_flags & IFF_ALLMULTI) 1254 filter |= DC_NETCFG_RX_ALLMULTI; 1255 CSR_WRITE_4(sc, DC_NETCFG, 1256 filter & ~(DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1257 if (filter & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) 1258 CSR_WRITE_4(sc, DC_NETCFG, filter); 1259 1260 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1261 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, BUS_DMASYNC_PREREAD | 1262 BUS_DMASYNC_PREWRITE); 1263 bus_dmamap_sync(sc->dc_stag, sc->dc_smap, BUS_DMASYNC_PREWRITE); 1264 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1265 1266 /* 1267 * Wait some time... 1268 */ 1269 DELAY(1000); 1270 1271 sc->dc_wdog_timer = 5; 1272 } 1273 1274 static void 1275 dc_setfilt_xircom(struct dc_softc *sc) 1276 { 1277 uint16_t eaddr[(ETHER_ADDR_LEN+1)/2]; 1278 struct ifnet *ifp; 1279 struct ifmultiaddr *ifma; 1280 struct dc_desc *sframe; 1281 uint32_t h, *sp; 1282 int i; 1283 1284 ifp = sc->dc_ifp; 1285 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1286 1287 i = sc->dc_cdata.dc_tx_prod; 1288 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1289 sc->dc_cdata.dc_tx_cnt++; 1290 sframe = &sc->dc_ldata.dc_tx_list[i]; 1291 sp = sc->dc_cdata.dc_sbuf; 1292 bzero(sp, DC_SFRAME_LEN); 1293 1294 sframe->dc_data = htole32(DC_ADDR_LO(sc->dc_saddr)); 1295 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1296 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1297 1298 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1299 1300 /* If we want promiscuous mode, set the allframes bit. */ 1301 if (ifp->if_flags & IFF_PROMISC) 1302 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1303 else 1304 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1305 1306 if (ifp->if_flags & IFF_ALLMULTI) 1307 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1308 else 1309 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1310 1311 if_maddr_rlock(ifp); 1312 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1313 if (ifma->ifma_addr->sa_family != AF_LINK) 1314 continue; 1315 h = dc_mchash_le(sc, 1316 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1317 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1318 } 1319 if_maddr_runlock(ifp); 1320 1321 if (ifp->if_flags & IFF_BROADCAST) { 1322 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1323 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1324 } 1325 1326 /* Set our MAC address. */ 1327 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1328 sp[0] = DC_SP_MAC(eaddr[0]); 1329 sp[1] = DC_SP_MAC(eaddr[1]); 1330 sp[2] = DC_SP_MAC(eaddr[2]); 1331 1332 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1333 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1334 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1335 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, BUS_DMASYNC_PREREAD | 1336 BUS_DMASYNC_PREWRITE); 1337 bus_dmamap_sync(sc->dc_stag, sc->dc_smap, BUS_DMASYNC_PREWRITE); 1338 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1339 1340 /* 1341 * Wait some time... 1342 */ 1343 DELAY(1000); 1344 1345 sc->dc_wdog_timer = 5; 1346 } 1347 1348 static void 1349 dc_setfilt(struct dc_softc *sc) 1350 { 1351 1352 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1353 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1354 dc_setfilt_21143(sc); 1355 1356 if (DC_IS_ASIX(sc)) 1357 dc_setfilt_asix(sc); 1358 1359 if (DC_IS_ADMTEK(sc)) 1360 dc_setfilt_admtek(sc); 1361 1362 if (DC_IS_ULI(sc)) 1363 dc_setfilt_uli(sc); 1364 1365 if (DC_IS_XIRCOM(sc)) 1366 dc_setfilt_xircom(sc); 1367 } 1368 1369 static void 1370 dc_netcfg_wait(struct dc_softc *sc) 1371 { 1372 uint32_t isr; 1373 int i; 1374 1375 for (i = 0; i < DC_TIMEOUT; i++) { 1376 isr = CSR_READ_4(sc, DC_ISR); 1377 if (isr & DC_ISR_TX_IDLE && 1378 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1379 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT)) 1380 break; 1381 DELAY(10); 1382 } 1383 if (i == DC_TIMEOUT && bus_child_present(sc->dc_dev)) { 1384 if (!(isr & DC_ISR_TX_IDLE) && !DC_IS_ASIX(sc)) 1385 device_printf(sc->dc_dev, 1386 "%s: failed to force tx to idle state\n", __func__); 1387 if (!((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1388 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT) && 1389 !DC_HAS_BROKEN_RXSTATE(sc)) 1390 device_printf(sc->dc_dev, 1391 "%s: failed to force rx to idle state\n", __func__); 1392 } 1393 } 1394 1395 /* 1396 * In order to fiddle with the 'full-duplex' and '100Mbps' bits in 1397 * the netconfig register, we first have to put the transmit and/or 1398 * receive logic in the idle state. 1399 */ 1400 static void 1401 dc_setcfg(struct dc_softc *sc, int media) 1402 { 1403 int restart = 0, watchdogreg; 1404 1405 if (IFM_SUBTYPE(media) == IFM_NONE) 1406 return; 1407 1408 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) { 1409 restart = 1; 1410 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1411 dc_netcfg_wait(sc); 1412 } 1413 1414 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1415 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1416 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1417 if (sc->dc_pmode == DC_PMODE_MII) { 1418 if (DC_IS_INTEL(sc)) { 1419 /* There's a write enable bit here that reads as 1. */ 1420 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1421 watchdogreg &= ~DC_WDOG_CTLWREN; 1422 watchdogreg |= DC_WDOG_JABBERDIS; 1423 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1424 } else { 1425 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1426 } 1427 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1428 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1429 if (sc->dc_type == DC_TYPE_98713) 1430 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1431 DC_NETCFG_SCRAMBLER)); 1432 if (!DC_IS_DAVICOM(sc)) 1433 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1434 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1435 } else { 1436 if (DC_IS_PNIC(sc)) { 1437 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1438 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1439 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1440 } 1441 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1442 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1443 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1444 } 1445 } 1446 1447 if (IFM_SUBTYPE(media) == IFM_10_T) { 1448 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1449 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1450 if (sc->dc_pmode == DC_PMODE_MII) { 1451 /* There's a write enable bit here that reads as 1. */ 1452 if (DC_IS_INTEL(sc)) { 1453 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1454 watchdogreg &= ~DC_WDOG_CTLWREN; 1455 watchdogreg |= DC_WDOG_JABBERDIS; 1456 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1457 } else { 1458 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1459 } 1460 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1461 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1462 if (sc->dc_type == DC_TYPE_98713) 1463 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1464 if (!DC_IS_DAVICOM(sc)) 1465 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1466 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1467 } else { 1468 if (DC_IS_PNIC(sc)) { 1469 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1470 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1471 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1472 } 1473 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1474 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1475 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1476 if (DC_IS_INTEL(sc)) { 1477 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1478 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1479 if ((media & IFM_GMASK) == IFM_FDX) 1480 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1481 else 1482 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1483 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1484 DC_CLRBIT(sc, DC_10BTCTRL, 1485 DC_TCTL_AUTONEGENBL); 1486 DELAY(20000); 1487 } 1488 } 1489 } 1490 1491 /* 1492 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1493 * PHY and we want HomePNA mode, set the portsel bit to turn 1494 * on the external MII port. 1495 */ 1496 if (DC_IS_DAVICOM(sc)) { 1497 if (IFM_SUBTYPE(media) == IFM_HPNA_1) { 1498 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1499 sc->dc_link = 1; 1500 } else { 1501 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1502 } 1503 } 1504 1505 if ((media & IFM_GMASK) == IFM_FDX) { 1506 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1507 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1508 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1509 } else { 1510 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1511 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1512 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1513 } 1514 1515 if (restart) 1516 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON | DC_NETCFG_RX_ON); 1517 } 1518 1519 static void 1520 dc_reset(struct dc_softc *sc) 1521 { 1522 int i; 1523 1524 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1525 1526 for (i = 0; i < DC_TIMEOUT; i++) { 1527 DELAY(10); 1528 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1529 break; 1530 } 1531 1532 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) || 1533 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc) || DC_IS_ULI(sc)) { 1534 DELAY(10000); 1535 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1536 i = 0; 1537 } 1538 1539 if (i == DC_TIMEOUT) 1540 device_printf(sc->dc_dev, "reset never completed!\n"); 1541 1542 /* Wait a little while for the chip to get its brains in order. */ 1543 DELAY(1000); 1544 1545 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1546 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1547 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1548 1549 /* 1550 * Bring the SIA out of reset. In some cases, it looks 1551 * like failing to unreset the SIA soon enough gets it 1552 * into a state where it will never come out of reset 1553 * until we reset the whole chip again. 1554 */ 1555 if (DC_IS_INTEL(sc)) { 1556 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1557 CSR_WRITE_4(sc, DC_10BTCTRL, 0xFFFFFFFF); 1558 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1559 } 1560 } 1561 1562 static const struct dc_type * 1563 dc_devtype(device_t dev) 1564 { 1565 const struct dc_type *t; 1566 uint32_t devid; 1567 uint8_t rev; 1568 1569 t = dc_devs; 1570 devid = pci_get_devid(dev); 1571 rev = pci_get_revid(dev); 1572 1573 while (t->dc_name != NULL) { 1574 if (devid == t->dc_devid && rev >= t->dc_minrev) 1575 return (t); 1576 t++; 1577 } 1578 1579 return (NULL); 1580 } 1581 1582 /* 1583 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1584 * IDs against our list and return a device name if we find a match. 1585 * We do a little bit of extra work to identify the exact type of 1586 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1587 * but different revision IDs. The same is true for 98715/98715A 1588 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1589 * cases, the exact chip revision affects driver behavior. 1590 */ 1591 static int 1592 dc_probe(device_t dev) 1593 { 1594 const struct dc_type *t; 1595 1596 t = dc_devtype(dev); 1597 1598 if (t != NULL) { 1599 device_set_desc(dev, t->dc_name); 1600 return (BUS_PROBE_DEFAULT); 1601 } 1602 1603 return (ENXIO); 1604 } 1605 1606 static void 1607 dc_apply_fixup(struct dc_softc *sc, int media) 1608 { 1609 struct dc_mediainfo *m; 1610 uint8_t *p; 1611 int i; 1612 uint32_t reg; 1613 1614 m = sc->dc_mi; 1615 1616 while (m != NULL) { 1617 if (m->dc_media == media) 1618 break; 1619 m = m->dc_next; 1620 } 1621 1622 if (m == NULL) 1623 return; 1624 1625 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1626 reg = (p[0] | (p[1] << 8)) << 16; 1627 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1628 } 1629 1630 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1631 reg = (p[0] | (p[1] << 8)) << 16; 1632 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1633 } 1634 } 1635 1636 static int 1637 dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l) 1638 { 1639 struct dc_mediainfo *m; 1640 1641 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1642 if (m == NULL) { 1643 device_printf(sc->dc_dev, "Could not allocate mediainfo\n"); 1644 return (ENOMEM); 1645 } 1646 switch (l->dc_sia_code & ~DC_SIA_CODE_EXT) { 1647 case DC_SIA_CODE_10BT: 1648 m->dc_media = IFM_10_T; 1649 break; 1650 case DC_SIA_CODE_10BT_FDX: 1651 m->dc_media = IFM_10_T | IFM_FDX; 1652 break; 1653 case DC_SIA_CODE_10B2: 1654 m->dc_media = IFM_10_2; 1655 break; 1656 case DC_SIA_CODE_10B5: 1657 m->dc_media = IFM_10_5; 1658 break; 1659 default: 1660 break; 1661 } 1662 1663 /* 1664 * We need to ignore CSR13, CSR14, CSR15 for SIA mode. 1665 * Things apparently already work for cards that do 1666 * supply Media Specific Data. 1667 */ 1668 if (l->dc_sia_code & DC_SIA_CODE_EXT) { 1669 m->dc_gp_len = 2; 1670 m->dc_gp_ptr = 1671 (uint8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl; 1672 } else { 1673 m->dc_gp_len = 2; 1674 m->dc_gp_ptr = 1675 (uint8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl; 1676 } 1677 1678 m->dc_next = sc->dc_mi; 1679 sc->dc_mi = m; 1680 1681 sc->dc_pmode = DC_PMODE_SIA; 1682 return (0); 1683 } 1684 1685 static int 1686 dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l) 1687 { 1688 struct dc_mediainfo *m; 1689 1690 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1691 if (m == NULL) { 1692 device_printf(sc->dc_dev, "Could not allocate mediainfo\n"); 1693 return (ENOMEM); 1694 } 1695 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1696 m->dc_media = IFM_100_TX; 1697 1698 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1699 m->dc_media = IFM_100_TX | IFM_FDX; 1700 1701 m->dc_gp_len = 2; 1702 m->dc_gp_ptr = (uint8_t *)&l->dc_sym_gpio_ctl; 1703 1704 m->dc_next = sc->dc_mi; 1705 sc->dc_mi = m; 1706 1707 sc->dc_pmode = DC_PMODE_SYM; 1708 return (0); 1709 } 1710 1711 static int 1712 dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l) 1713 { 1714 struct dc_mediainfo *m; 1715 uint8_t *p; 1716 1717 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1718 if (m == NULL) { 1719 device_printf(sc->dc_dev, "Could not allocate mediainfo\n"); 1720 return (ENOMEM); 1721 } 1722 /* We abuse IFM_AUTO to represent MII. */ 1723 m->dc_media = IFM_AUTO; 1724 m->dc_gp_len = l->dc_gpr_len; 1725 1726 p = (uint8_t *)l; 1727 p += sizeof(struct dc_eblock_mii); 1728 m->dc_gp_ptr = p; 1729 p += 2 * l->dc_gpr_len; 1730 m->dc_reset_len = *p; 1731 p++; 1732 m->dc_reset_ptr = p; 1733 1734 m->dc_next = sc->dc_mi; 1735 sc->dc_mi = m; 1736 return (0); 1737 } 1738 1739 static int 1740 dc_read_srom(struct dc_softc *sc, int bits) 1741 { 1742 int size; 1743 1744 size = DC_ROM_SIZE(bits); 1745 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO); 1746 if (sc->dc_srom == NULL) { 1747 device_printf(sc->dc_dev, "Could not allocate SROM buffer\n"); 1748 return (ENOMEM); 1749 } 1750 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); 1751 return (0); 1752 } 1753 1754 static int 1755 dc_parse_21143_srom(struct dc_softc *sc) 1756 { 1757 struct dc_leaf_hdr *lhdr; 1758 struct dc_eblock_hdr *hdr; 1759 int error, have_mii, i, loff; 1760 char *ptr; 1761 1762 have_mii = 0; 1763 loff = sc->dc_srom[27]; 1764 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1765 1766 ptr = (char *)lhdr; 1767 ptr += sizeof(struct dc_leaf_hdr) - 1; 1768 /* 1769 * Look if we got a MII media block. 1770 */ 1771 for (i = 0; i < lhdr->dc_mcnt; i++) { 1772 hdr = (struct dc_eblock_hdr *)ptr; 1773 if (hdr->dc_type == DC_EBLOCK_MII) 1774 have_mii++; 1775 1776 ptr += (hdr->dc_len & 0x7F); 1777 ptr++; 1778 } 1779 1780 /* 1781 * Do the same thing again. Only use SIA and SYM media 1782 * blocks if no MII media block is available. 1783 */ 1784 ptr = (char *)lhdr; 1785 ptr += sizeof(struct dc_leaf_hdr) - 1; 1786 error = 0; 1787 for (i = 0; i < lhdr->dc_mcnt; i++) { 1788 hdr = (struct dc_eblock_hdr *)ptr; 1789 switch (hdr->dc_type) { 1790 case DC_EBLOCK_MII: 1791 error = dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1792 break; 1793 case DC_EBLOCK_SIA: 1794 if (! have_mii) 1795 error = dc_decode_leaf_sia(sc, 1796 (struct dc_eblock_sia *)hdr); 1797 break; 1798 case DC_EBLOCK_SYM: 1799 if (! have_mii) 1800 error = dc_decode_leaf_sym(sc, 1801 (struct dc_eblock_sym *)hdr); 1802 break; 1803 default: 1804 /* Don't care. Yet. */ 1805 break; 1806 } 1807 ptr += (hdr->dc_len & 0x7F); 1808 ptr++; 1809 } 1810 return (error); 1811 } 1812 1813 static void 1814 dc_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1815 { 1816 bus_addr_t *paddr; 1817 1818 KASSERT(nseg == 1, 1819 ("%s: wrong number of segments (%d)", __func__, nseg)); 1820 paddr = arg; 1821 *paddr = segs->ds_addr; 1822 } 1823 1824 static int 1825 dc_dma_alloc(struct dc_softc *sc) 1826 { 1827 int error, i; 1828 1829 error = bus_dma_tag_create(bus_get_dma_tag(sc->dc_dev), 1, 0, 1830 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1831 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, 1832 NULL, NULL, &sc->dc_ptag); 1833 if (error) { 1834 device_printf(sc->dc_dev, 1835 "failed to allocate parent DMA tag\n"); 1836 goto fail; 1837 } 1838 1839 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */ 1840 error = bus_dma_tag_create(sc->dc_ptag, DC_LIST_ALIGN, 0, 1841 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, DC_RX_LIST_SZ, 1, 1842 DC_RX_LIST_SZ, 0, NULL, NULL, &sc->dc_rx_ltag); 1843 if (error) { 1844 device_printf(sc->dc_dev, "failed to create RX list DMA tag\n"); 1845 goto fail; 1846 } 1847 1848 error = bus_dma_tag_create(sc->dc_ptag, DC_LIST_ALIGN, 0, 1849 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, DC_TX_LIST_SZ, 1, 1850 DC_TX_LIST_SZ, 0, NULL, NULL, &sc->dc_tx_ltag); 1851 if (error) { 1852 device_printf(sc->dc_dev, "failed to create TX list DMA tag\n"); 1853 goto fail; 1854 } 1855 1856 /* RX descriptor list. */ 1857 error = bus_dmamem_alloc(sc->dc_rx_ltag, 1858 (void **)&sc->dc_ldata.dc_rx_list, BUS_DMA_NOWAIT | 1859 BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->dc_rx_lmap); 1860 if (error) { 1861 device_printf(sc->dc_dev, 1862 "failed to allocate DMA'able memory for RX list\n"); 1863 goto fail; 1864 } 1865 error = bus_dmamap_load(sc->dc_rx_ltag, sc->dc_rx_lmap, 1866 sc->dc_ldata.dc_rx_list, DC_RX_LIST_SZ, dc_dma_map_addr, 1867 &sc->dc_ldata.dc_rx_list_paddr, BUS_DMA_NOWAIT); 1868 if (error) { 1869 device_printf(sc->dc_dev, 1870 "failed to load DMA'able memory for RX list\n"); 1871 goto fail; 1872 } 1873 /* TX descriptor list. */ 1874 error = bus_dmamem_alloc(sc->dc_tx_ltag, 1875 (void **)&sc->dc_ldata.dc_tx_list, BUS_DMA_NOWAIT | 1876 BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->dc_tx_lmap); 1877 if (error) { 1878 device_printf(sc->dc_dev, 1879 "failed to allocate DMA'able memory for TX list\n"); 1880 goto fail; 1881 } 1882 error = bus_dmamap_load(sc->dc_tx_ltag, sc->dc_tx_lmap, 1883 sc->dc_ldata.dc_tx_list, DC_TX_LIST_SZ, dc_dma_map_addr, 1884 &sc->dc_ldata.dc_tx_list_paddr, BUS_DMA_NOWAIT); 1885 if (error) { 1886 device_printf(sc->dc_dev, 1887 "cannot load DMA'able memory for TX list\n"); 1888 goto fail; 1889 } 1890 1891 /* 1892 * Allocate a busdma tag and DMA safe memory for the multicast 1893 * setup frame. 1894 */ 1895 error = bus_dma_tag_create(sc->dc_ptag, DC_LIST_ALIGN, 0, 1896 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1897 DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1, DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1898 0, NULL, NULL, &sc->dc_stag); 1899 if (error) { 1900 device_printf(sc->dc_dev, 1901 "failed to create DMA tag for setup frame\n"); 1902 goto fail; 1903 } 1904 error = bus_dmamem_alloc(sc->dc_stag, (void **)&sc->dc_cdata.dc_sbuf, 1905 BUS_DMA_NOWAIT, &sc->dc_smap); 1906 if (error) { 1907 device_printf(sc->dc_dev, 1908 "failed to allocate DMA'able memory for setup frame\n"); 1909 goto fail; 1910 } 1911 error = bus_dmamap_load(sc->dc_stag, sc->dc_smap, sc->dc_cdata.dc_sbuf, 1912 DC_SFRAME_LEN, dc_dma_map_addr, &sc->dc_saddr, BUS_DMA_NOWAIT); 1913 if (error) { 1914 device_printf(sc->dc_dev, 1915 "cannot load DMA'able memory for setup frame\n"); 1916 goto fail; 1917 } 1918 1919 /* Allocate a busdma tag for RX mbufs. */ 1920 error = bus_dma_tag_create(sc->dc_ptag, DC_RXBUF_ALIGN, 0, 1921 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1922 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->dc_rx_mtag); 1923 if (error) { 1924 device_printf(sc->dc_dev, "failed to create RX mbuf tag\n"); 1925 goto fail; 1926 } 1927 1928 /* Allocate a busdma tag for TX mbufs. */ 1929 error = bus_dma_tag_create(sc->dc_ptag, 1, 0, 1930 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1931 MCLBYTES * DC_MAXFRAGS, DC_MAXFRAGS, MCLBYTES, 1932 0, NULL, NULL, &sc->dc_tx_mtag); 1933 if (error) { 1934 device_printf(sc->dc_dev, "failed to create TX mbuf tag\n"); 1935 goto fail; 1936 } 1937 1938 /* Create the TX/RX busdma maps. */ 1939 for (i = 0; i < DC_TX_LIST_CNT; i++) { 1940 error = bus_dmamap_create(sc->dc_tx_mtag, 0, 1941 &sc->dc_cdata.dc_tx_map[i]); 1942 if (error) { 1943 device_printf(sc->dc_dev, 1944 "failed to create TX mbuf dmamap\n"); 1945 goto fail; 1946 } 1947 } 1948 for (i = 0; i < DC_RX_LIST_CNT; i++) { 1949 error = bus_dmamap_create(sc->dc_rx_mtag, 0, 1950 &sc->dc_cdata.dc_rx_map[i]); 1951 if (error) { 1952 device_printf(sc->dc_dev, 1953 "failed to create RX mbuf dmamap\n"); 1954 goto fail; 1955 } 1956 } 1957 error = bus_dmamap_create(sc->dc_rx_mtag, 0, &sc->dc_sparemap); 1958 if (error) { 1959 device_printf(sc->dc_dev, 1960 "failed to create spare RX mbuf dmamap\n"); 1961 goto fail; 1962 } 1963 1964 fail: 1965 return (error); 1966 } 1967 1968 static void 1969 dc_dma_free(struct dc_softc *sc) 1970 { 1971 int i; 1972 1973 /* RX buffers. */ 1974 if (sc->dc_rx_mtag != NULL) { 1975 for (i = 0; i < DC_RX_LIST_CNT; i++) { 1976 if (sc->dc_cdata.dc_rx_map[i] != NULL) 1977 bus_dmamap_destroy(sc->dc_rx_mtag, 1978 sc->dc_cdata.dc_rx_map[i]); 1979 } 1980 if (sc->dc_sparemap != NULL) 1981 bus_dmamap_destroy(sc->dc_rx_mtag, sc->dc_sparemap); 1982 bus_dma_tag_destroy(sc->dc_rx_mtag); 1983 } 1984 1985 /* TX buffers. */ 1986 if (sc->dc_rx_mtag != NULL) { 1987 for (i = 0; i < DC_TX_LIST_CNT; i++) { 1988 if (sc->dc_cdata.dc_tx_map[i] != NULL) 1989 bus_dmamap_destroy(sc->dc_tx_mtag, 1990 sc->dc_cdata.dc_tx_map[i]); 1991 } 1992 bus_dma_tag_destroy(sc->dc_tx_mtag); 1993 } 1994 1995 /* RX descriptor list. */ 1996 if (sc->dc_rx_ltag) { 1997 if (sc->dc_rx_lmap != NULL) 1998 bus_dmamap_unload(sc->dc_rx_ltag, sc->dc_rx_lmap); 1999 if (sc->dc_rx_lmap != NULL && sc->dc_ldata.dc_rx_list != NULL) 2000 bus_dmamem_free(sc->dc_rx_ltag, sc->dc_ldata.dc_rx_list, 2001 sc->dc_rx_lmap); 2002 bus_dma_tag_destroy(sc->dc_rx_ltag); 2003 } 2004 2005 /* TX descriptor list. */ 2006 if (sc->dc_tx_ltag) { 2007 if (sc->dc_tx_lmap != NULL) 2008 bus_dmamap_unload(sc->dc_tx_ltag, sc->dc_tx_lmap); 2009 if (sc->dc_tx_lmap != NULL && sc->dc_ldata.dc_tx_list != NULL) 2010 bus_dmamem_free(sc->dc_tx_ltag, sc->dc_ldata.dc_tx_list, 2011 sc->dc_tx_lmap); 2012 bus_dma_tag_destroy(sc->dc_tx_ltag); 2013 } 2014 2015 /* multicast setup frame. */ 2016 if (sc->dc_stag) { 2017 if (sc->dc_smap != NULL) 2018 bus_dmamap_unload(sc->dc_stag, sc->dc_smap); 2019 if (sc->dc_smap != NULL && sc->dc_cdata.dc_sbuf != NULL) 2020 bus_dmamem_free(sc->dc_stag, sc->dc_cdata.dc_sbuf, 2021 sc->dc_smap); 2022 bus_dma_tag_destroy(sc->dc_stag); 2023 } 2024 } 2025 2026 /* 2027 * Attach the interface. Allocate softc structures, do ifmedia 2028 * setup and ethernet/BPF attach. 2029 */ 2030 static int 2031 dc_attach(device_t dev) 2032 { 2033 uint32_t eaddr[(ETHER_ADDR_LEN+3)/4]; 2034 uint32_t command; 2035 struct dc_softc *sc; 2036 struct ifnet *ifp; 2037 struct dc_mediainfo *m; 2038 uint32_t reg, revision; 2039 uint16_t *srom; 2040 int error, mac_offset, n, phy, rid, tmp; 2041 uint8_t *mac; 2042 2043 sc = device_get_softc(dev); 2044 sc->dc_dev = dev; 2045 2046 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 2047 MTX_DEF); 2048 2049 /* 2050 * Map control/status registers. 2051 */ 2052 pci_enable_busmaster(dev); 2053 2054 rid = DC_RID; 2055 sc->dc_res = bus_alloc_resource_any(dev, DC_RES, &rid, RF_ACTIVE); 2056 2057 if (sc->dc_res == NULL) { 2058 device_printf(dev, "couldn't map ports/memory\n"); 2059 error = ENXIO; 2060 goto fail; 2061 } 2062 2063 sc->dc_btag = rman_get_bustag(sc->dc_res); 2064 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 2065 2066 /* Allocate interrupt. */ 2067 rid = 0; 2068 sc->dc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 2069 RF_SHAREABLE | RF_ACTIVE); 2070 2071 if (sc->dc_irq == NULL) { 2072 device_printf(dev, "couldn't map interrupt\n"); 2073 error = ENXIO; 2074 goto fail; 2075 } 2076 2077 /* Need this info to decide on a chip type. */ 2078 sc->dc_info = dc_devtype(dev); 2079 revision = pci_get_revid(dev); 2080 2081 error = 0; 2082 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */ 2083 if (sc->dc_info->dc_devid != 2084 DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168) && 2085 sc->dc_info->dc_devid != 2086 DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201)) 2087 dc_eeprom_width(sc); 2088 2089 switch (sc->dc_info->dc_devid) { 2090 case DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143): 2091 sc->dc_type = DC_TYPE_21143; 2092 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 2093 sc->dc_flags |= DC_REDUCED_MII_POLL; 2094 /* Save EEPROM contents so we can parse them later. */ 2095 error = dc_read_srom(sc, sc->dc_romwidth); 2096 if (error != 0) 2097 goto fail; 2098 break; 2099 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009): 2100 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100): 2101 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102): 2102 sc->dc_type = DC_TYPE_DM9102; 2103 sc->dc_flags |= DC_TX_COALESCE | DC_TX_INTR_ALWAYS; 2104 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_TX_STORENFWD; 2105 sc->dc_flags |= DC_TX_ALIGN; 2106 sc->dc_pmode = DC_PMODE_MII; 2107 2108 /* Increase the latency timer value. */ 2109 pci_write_config(dev, PCIR_LATTIMER, 0x80, 1); 2110 break; 2111 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981): 2112 sc->dc_type = DC_TYPE_AL981; 2113 sc->dc_flags |= DC_TX_USE_TX_INTR; 2114 sc->dc_flags |= DC_TX_ADMTEK_WAR; 2115 sc->dc_pmode = DC_PMODE_MII; 2116 error = dc_read_srom(sc, sc->dc_romwidth); 2117 if (error != 0) 2118 goto fail; 2119 break; 2120 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN983): 2121 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985): 2122 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511): 2123 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513): 2124 case DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD): 2125 case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500): 2126 case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX): 2127 case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242): 2128 case DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX): 2129 case DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T): 2130 case DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB): 2131 case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120): 2132 case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130): 2133 case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08): 2134 case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09): 2135 sc->dc_type = DC_TYPE_AN983; 2136 sc->dc_flags |= DC_64BIT_HASH; 2137 sc->dc_flags |= DC_TX_USE_TX_INTR; 2138 sc->dc_flags |= DC_TX_ADMTEK_WAR; 2139 sc->dc_pmode = DC_PMODE_MII; 2140 /* Don't read SROM for - auto-loaded on reset */ 2141 break; 2142 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713): 2143 case DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP): 2144 if (revision < DC_REVISION_98713A) { 2145 sc->dc_type = DC_TYPE_98713; 2146 } 2147 if (revision >= DC_REVISION_98713A) { 2148 sc->dc_type = DC_TYPE_98713A; 2149 sc->dc_flags |= DC_21143_NWAY; 2150 } 2151 sc->dc_flags |= DC_REDUCED_MII_POLL; 2152 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 2153 break; 2154 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5): 2155 case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217): 2156 /* 2157 * Macronix MX98715AEC-C/D/E parts have only a 2158 * 128-bit hash table. We need to deal with these 2159 * in the same manner as the PNIC II so that we 2160 * get the right number of bits out of the 2161 * CRC routine. 2162 */ 2163 if (revision >= DC_REVISION_98715AEC_C && 2164 revision < DC_REVISION_98725) 2165 sc->dc_flags |= DC_128BIT_HASH; 2166 sc->dc_type = DC_TYPE_987x5; 2167 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 2168 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 2169 break; 2170 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727): 2171 sc->dc_type = DC_TYPE_987x5; 2172 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 2173 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 2174 break; 2175 case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115): 2176 sc->dc_type = DC_TYPE_PNICII; 2177 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR | DC_128BIT_HASH; 2178 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 2179 break; 2180 case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168): 2181 sc->dc_type = DC_TYPE_PNIC; 2182 sc->dc_flags |= DC_TX_STORENFWD | DC_TX_INTR_ALWAYS; 2183 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 2184 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 2185 if (sc->dc_pnic_rx_buf == NULL) { 2186 device_printf(sc->dc_dev, 2187 "Could not allocate PNIC RX buffer\n"); 2188 error = ENOMEM; 2189 goto fail; 2190 } 2191 if (revision < DC_REVISION_82C169) 2192 sc->dc_pmode = DC_PMODE_SYM; 2193 break; 2194 case DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A): 2195 sc->dc_type = DC_TYPE_ASIX; 2196 sc->dc_flags |= DC_TX_USE_TX_INTR | DC_TX_INTR_FIRSTFRAG; 2197 sc->dc_flags |= DC_REDUCED_MII_POLL; 2198 sc->dc_pmode = DC_PMODE_MII; 2199 break; 2200 case DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201): 2201 sc->dc_type = DC_TYPE_XIRCOM; 2202 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 2203 DC_TX_ALIGN; 2204 /* 2205 * We don't actually need to coalesce, but we're doing 2206 * it to obtain a double word aligned buffer. 2207 * The DC_TX_COALESCE flag is required. 2208 */ 2209 sc->dc_pmode = DC_PMODE_MII; 2210 break; 2211 case DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112): 2212 sc->dc_type = DC_TYPE_CONEXANT; 2213 sc->dc_flags |= DC_TX_INTR_ALWAYS; 2214 sc->dc_flags |= DC_REDUCED_MII_POLL; 2215 sc->dc_pmode = DC_PMODE_MII; 2216 error = dc_read_srom(sc, sc->dc_romwidth); 2217 if (error != 0) 2218 goto fail; 2219 break; 2220 case DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5261): 2221 case DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5263): 2222 if (sc->dc_info->dc_devid == 2223 DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5261)) 2224 sc->dc_type = DC_TYPE_ULI_M5261; 2225 else 2226 sc->dc_type = DC_TYPE_ULI_M5263; 2227 /* TX buffers should be aligned on 4 byte boundary. */ 2228 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 2229 DC_TX_ALIGN; 2230 sc->dc_pmode = DC_PMODE_MII; 2231 error = dc_read_srom(sc, sc->dc_romwidth); 2232 if (error != 0) 2233 goto fail; 2234 break; 2235 default: 2236 device_printf(dev, "unknown device: %x\n", 2237 sc->dc_info->dc_devid); 2238 break; 2239 } 2240 2241 /* Save the cache line size. */ 2242 if (DC_IS_DAVICOM(sc)) 2243 sc->dc_cachesize = 0; 2244 else 2245 sc->dc_cachesize = pci_get_cachelnsz(dev); 2246 2247 /* Reset the adapter. */ 2248 dc_reset(sc); 2249 2250 /* Take 21143 out of snooze mode */ 2251 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 2252 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2253 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 2254 pci_write_config(dev, DC_PCI_CFDD, command, 4); 2255 } 2256 2257 /* 2258 * Try to learn something about the supported media. 2259 * We know that ASIX and ADMtek and Davicom devices 2260 * will *always* be using MII media, so that's a no-brainer. 2261 * The tricky ones are the Macronix/PNIC II and the 2262 * Intel 21143. 2263 */ 2264 if (DC_IS_INTEL(sc)) { 2265 error = dc_parse_21143_srom(sc); 2266 if (error != 0) 2267 goto fail; 2268 } else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2269 if (sc->dc_type == DC_TYPE_98713) 2270 sc->dc_pmode = DC_PMODE_MII; 2271 else 2272 sc->dc_pmode = DC_PMODE_SYM; 2273 } else if (!sc->dc_pmode) 2274 sc->dc_pmode = DC_PMODE_MII; 2275 2276 /* 2277 * Get station address from the EEPROM. 2278 */ 2279 switch(sc->dc_type) { 2280 case DC_TYPE_98713: 2281 case DC_TYPE_98713A: 2282 case DC_TYPE_987x5: 2283 case DC_TYPE_PNICII: 2284 dc_read_eeprom(sc, (caddr_t)&mac_offset, 2285 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2286 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2287 break; 2288 case DC_TYPE_PNIC: 2289 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2290 break; 2291 case DC_TYPE_DM9102: 2292 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2293 #ifdef __sparc64__ 2294 /* 2295 * If this is an onboard dc(4) the station address read from 2296 * the EEPROM is all zero and we have to get it from the FCode. 2297 */ 2298 if (eaddr[0] == 0 && (eaddr[1] & ~0xffff) == 0) 2299 OF_getetheraddr(dev, (caddr_t)&eaddr); 2300 #endif 2301 break; 2302 case DC_TYPE_21143: 2303 case DC_TYPE_ASIX: 2304 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2305 break; 2306 case DC_TYPE_AL981: 2307 case DC_TYPE_AN983: 2308 reg = CSR_READ_4(sc, DC_AL_PAR0); 2309 mac = (uint8_t *)&eaddr[0]; 2310 mac[0] = (reg >> 0) & 0xff; 2311 mac[1] = (reg >> 8) & 0xff; 2312 mac[2] = (reg >> 16) & 0xff; 2313 mac[3] = (reg >> 24) & 0xff; 2314 reg = CSR_READ_4(sc, DC_AL_PAR1); 2315 mac[4] = (reg >> 0) & 0xff; 2316 mac[5] = (reg >> 8) & 0xff; 2317 break; 2318 case DC_TYPE_CONEXANT: 2319 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 2320 ETHER_ADDR_LEN); 2321 break; 2322 case DC_TYPE_XIRCOM: 2323 /* The MAC comes from the CIS. */ 2324 mac = pci_get_ether(dev); 2325 if (!mac) { 2326 device_printf(dev, "No station address in CIS!\n"); 2327 error = ENXIO; 2328 goto fail; 2329 } 2330 bcopy(mac, eaddr, ETHER_ADDR_LEN); 2331 break; 2332 case DC_TYPE_ULI_M5261: 2333 case DC_TYPE_ULI_M5263: 2334 srom = (uint16_t *)sc->dc_srom; 2335 if (srom == NULL || *srom == 0xFFFF || *srom == 0) { 2336 /* 2337 * No valid SROM present, read station address 2338 * from ID Table. 2339 */ 2340 device_printf(dev, 2341 "Reading station address from ID Table.\n"); 2342 CSR_WRITE_4(sc, DC_BUSCTL, 0x10000); 2343 CSR_WRITE_4(sc, DC_SIARESET, 0x01C0); 2344 CSR_WRITE_4(sc, DC_10BTCTRL, 0x0000); 2345 CSR_WRITE_4(sc, DC_10BTCTRL, 0x0010); 2346 CSR_WRITE_4(sc, DC_10BTCTRL, 0x0000); 2347 CSR_WRITE_4(sc, DC_SIARESET, 0x0000); 2348 CSR_WRITE_4(sc, DC_SIARESET, 0x01B0); 2349 mac = (uint8_t *)eaddr; 2350 for (n = 0; n < ETHER_ADDR_LEN; n++) 2351 mac[n] = (uint8_t)CSR_READ_4(sc, DC_10BTCTRL); 2352 CSR_WRITE_4(sc, DC_SIARESET, 0x0000); 2353 CSR_WRITE_4(sc, DC_BUSCTL, 0x0000); 2354 DELAY(10); 2355 } else 2356 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 2357 0); 2358 break; 2359 default: 2360 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2361 break; 2362 } 2363 2364 bcopy(eaddr, sc->dc_eaddr, sizeof(eaddr)); 2365 /* 2366 * If we still have invalid station address, see whether we can 2367 * find station address for chip 0. Some multi-port controllers 2368 * just store station address for chip 0 if they have a shared 2369 * SROM. 2370 */ 2371 if ((sc->dc_eaddr[0] == 0 && (sc->dc_eaddr[1] & ~0xffff) == 0) || 2372 (sc->dc_eaddr[0] == 0xffffffff && 2373 (sc->dc_eaddr[1] & 0xffff) == 0xffff)) { 2374 error = dc_check_multiport(sc); 2375 if (error == 0) { 2376 bcopy(sc->dc_eaddr, eaddr, sizeof(eaddr)); 2377 /* Extract media information. */ 2378 if (DC_IS_INTEL(sc) && sc->dc_srom != NULL) { 2379 while (sc->dc_mi != NULL) { 2380 m = sc->dc_mi->dc_next; 2381 free(sc->dc_mi, M_DEVBUF); 2382 sc->dc_mi = m; 2383 } 2384 error = dc_parse_21143_srom(sc); 2385 if (error != 0) 2386 goto fail; 2387 } 2388 } else if (error == ENOMEM) 2389 goto fail; 2390 else 2391 error = 0; 2392 } 2393 2394 if ((error = dc_dma_alloc(sc)) != 0) 2395 goto fail; 2396 2397 ifp = sc->dc_ifp = if_alloc(IFT_ETHER); 2398 if (ifp == NULL) { 2399 device_printf(dev, "can not if_alloc()\n"); 2400 error = ENOSPC; 2401 goto fail; 2402 } 2403 ifp->if_softc = sc; 2404 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2405 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2406 ifp->if_ioctl = dc_ioctl; 2407 ifp->if_start = dc_start; 2408 ifp->if_init = dc_init; 2409 IFQ_SET_MAXLEN(&ifp->if_snd, DC_TX_LIST_CNT - 1); 2410 ifp->if_snd.ifq_drv_maxlen = DC_TX_LIST_CNT - 1; 2411 IFQ_SET_READY(&ifp->if_snd); 2412 2413 /* 2414 * Do MII setup. If this is a 21143, check for a PHY on the 2415 * MII bus after applying any necessary fixups to twiddle the 2416 * GPIO bits. If we don't end up finding a PHY, restore the 2417 * old selection (SIA only or SIA/SYM) and attach the dcphy 2418 * driver instead. 2419 */ 2420 tmp = 0; 2421 if (DC_IS_INTEL(sc)) { 2422 dc_apply_fixup(sc, IFM_AUTO); 2423 tmp = sc->dc_pmode; 2424 sc->dc_pmode = DC_PMODE_MII; 2425 } 2426 2427 /* 2428 * Setup General Purpose port mode and data so the tulip can talk 2429 * to the MII. This needs to be done before mii_attach so that 2430 * we can actually see them. 2431 */ 2432 if (DC_IS_XIRCOM(sc)) { 2433 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2434 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2435 DELAY(10); 2436 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2437 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2438 DELAY(10); 2439 } 2440 2441 phy = MII_PHY_ANY; 2442 /* 2443 * Note: both the AL981 and AN983 have internal PHYs, however the 2444 * AL981 provides direct access to the PHY registers while the AN983 2445 * uses a serial MII interface. The AN983's MII interface is also 2446 * buggy in that you can read from any MII address (0 to 31), but 2447 * only address 1 behaves normally. To deal with both cases, we 2448 * pretend that the PHY is at MII address 1. 2449 */ 2450 if (DC_IS_ADMTEK(sc)) 2451 phy = DC_ADMTEK_PHYADDR; 2452 2453 /* 2454 * Note: the ukphy probes of the RS7112 report a PHY at MII address 2455 * 0 (possibly HomePNA?) and 1 (ethernet) so we only respond to the 2456 * correct one. 2457 */ 2458 if (DC_IS_CONEXANT(sc)) 2459 phy = DC_CONEXANT_PHYADDR; 2460 2461 error = mii_attach(dev, &sc->dc_miibus, ifp, dc_ifmedia_upd, 2462 dc_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0); 2463 2464 if (error && DC_IS_INTEL(sc)) { 2465 sc->dc_pmode = tmp; 2466 if (sc->dc_pmode != DC_PMODE_SIA) 2467 sc->dc_pmode = DC_PMODE_SYM; 2468 sc->dc_flags |= DC_21143_NWAY; 2469 mii_attach(dev, &sc->dc_miibus, ifp, dc_ifmedia_upd, 2470 dc_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, 2471 MII_OFFSET_ANY, 0); 2472 /* 2473 * For non-MII cards, we need to have the 21143 2474 * drive the LEDs. Except there are some systems 2475 * like the NEC VersaPro NoteBook PC which have no 2476 * LEDs, and twiddling these bits has adverse effects 2477 * on them. (I.e. you suddenly can't get a link.) 2478 */ 2479 if (!(pci_get_subvendor(dev) == 0x1033 && 2480 pci_get_subdevice(dev) == 0x8028)) 2481 sc->dc_flags |= DC_TULIP_LEDS; 2482 error = 0; 2483 } 2484 2485 if (error) { 2486 device_printf(dev, "attaching PHYs failed\n"); 2487 goto fail; 2488 } 2489 2490 if (DC_IS_ADMTEK(sc)) { 2491 /* 2492 * Set automatic TX underrun recovery for the ADMtek chips 2493 */ 2494 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); 2495 } 2496 2497 /* 2498 * Tell the upper layer(s) we support long frames. 2499 */ 2500 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2501 ifp->if_capabilities |= IFCAP_VLAN_MTU; 2502 ifp->if_capenable = ifp->if_capabilities; 2503 #ifdef DEVICE_POLLING 2504 ifp->if_capabilities |= IFCAP_POLLING; 2505 #endif 2506 2507 callout_init_mtx(&sc->dc_stat_ch, &sc->dc_mtx, 0); 2508 callout_init_mtx(&sc->dc_wdog_ch, &sc->dc_mtx, 0); 2509 2510 /* 2511 * Call MI attach routine. 2512 */ 2513 ether_ifattach(ifp, (caddr_t)eaddr); 2514 2515 /* Hook interrupt last to avoid having to lock softc */ 2516 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | INTR_MPSAFE, 2517 NULL, dc_intr, sc, &sc->dc_intrhand); 2518 2519 if (error) { 2520 device_printf(dev, "couldn't set up irq\n"); 2521 ether_ifdetach(ifp); 2522 goto fail; 2523 } 2524 2525 fail: 2526 if (error) 2527 dc_detach(dev); 2528 return (error); 2529 } 2530 2531 /* 2532 * Shutdown hardware and free up resources. This can be called any 2533 * time after the mutex has been initialized. It is called in both 2534 * the error case in attach and the normal detach case so it needs 2535 * to be careful about only freeing resources that have actually been 2536 * allocated. 2537 */ 2538 static int 2539 dc_detach(device_t dev) 2540 { 2541 struct dc_softc *sc; 2542 struct ifnet *ifp; 2543 struct dc_mediainfo *m; 2544 2545 sc = device_get_softc(dev); 2546 KASSERT(mtx_initialized(&sc->dc_mtx), ("dc mutex not initialized")); 2547 2548 ifp = sc->dc_ifp; 2549 2550 #ifdef DEVICE_POLLING 2551 if (ifp->if_capenable & IFCAP_POLLING) 2552 ether_poll_deregister(ifp); 2553 #endif 2554 2555 /* These should only be active if attach succeeded */ 2556 if (device_is_attached(dev)) { 2557 DC_LOCK(sc); 2558 dc_stop(sc); 2559 DC_UNLOCK(sc); 2560 callout_drain(&sc->dc_stat_ch); 2561 callout_drain(&sc->dc_wdog_ch); 2562 ether_ifdetach(ifp); 2563 } 2564 if (sc->dc_miibus) 2565 device_delete_child(dev, sc->dc_miibus); 2566 bus_generic_detach(dev); 2567 2568 if (sc->dc_intrhand) 2569 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2570 if (sc->dc_irq) 2571 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2572 if (sc->dc_res) 2573 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2574 2575 if (ifp) 2576 if_free(ifp); 2577 2578 dc_dma_free(sc); 2579 2580 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2581 2582 while (sc->dc_mi != NULL) { 2583 m = sc->dc_mi->dc_next; 2584 free(sc->dc_mi, M_DEVBUF); 2585 sc->dc_mi = m; 2586 } 2587 free(sc->dc_srom, M_DEVBUF); 2588 2589 mtx_destroy(&sc->dc_mtx); 2590 2591 return (0); 2592 } 2593 2594 /* 2595 * Initialize the transmit descriptors. 2596 */ 2597 static int 2598 dc_list_tx_init(struct dc_softc *sc) 2599 { 2600 struct dc_chain_data *cd; 2601 struct dc_list_data *ld; 2602 int i, nexti; 2603 2604 cd = &sc->dc_cdata; 2605 ld = &sc->dc_ldata; 2606 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2607 if (i == DC_TX_LIST_CNT - 1) 2608 nexti = 0; 2609 else 2610 nexti = i + 1; 2611 ld->dc_tx_list[i].dc_status = 0; 2612 ld->dc_tx_list[i].dc_ctl = 0; 2613 ld->dc_tx_list[i].dc_data = 0; 2614 ld->dc_tx_list[i].dc_next = htole32(DC_TXDESC(sc, nexti)); 2615 cd->dc_tx_chain[i] = NULL; 2616 } 2617 2618 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2619 cd->dc_tx_pkts = 0; 2620 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, 2621 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2622 return (0); 2623 } 2624 2625 2626 /* 2627 * Initialize the RX descriptors and allocate mbufs for them. Note that 2628 * we arrange the descriptors in a closed ring, so that the last descriptor 2629 * points back to the first. 2630 */ 2631 static int 2632 dc_list_rx_init(struct dc_softc *sc) 2633 { 2634 struct dc_chain_data *cd; 2635 struct dc_list_data *ld; 2636 int i, nexti; 2637 2638 cd = &sc->dc_cdata; 2639 ld = &sc->dc_ldata; 2640 2641 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2642 if (dc_newbuf(sc, i) != 0) 2643 return (ENOBUFS); 2644 if (i == DC_RX_LIST_CNT - 1) 2645 nexti = 0; 2646 else 2647 nexti = i + 1; 2648 ld->dc_rx_list[i].dc_next = htole32(DC_RXDESC(sc, nexti)); 2649 } 2650 2651 cd->dc_rx_prod = 0; 2652 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, 2653 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2654 return (0); 2655 } 2656 2657 /* 2658 * Initialize an RX descriptor and attach an MBUF cluster. 2659 */ 2660 static int 2661 dc_newbuf(struct dc_softc *sc, int i) 2662 { 2663 struct mbuf *m; 2664 bus_dmamap_t map; 2665 bus_dma_segment_t segs[1]; 2666 int error, nseg; 2667 2668 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2669 if (m == NULL) 2670 return (ENOBUFS); 2671 m->m_len = m->m_pkthdr.len = MCLBYTES; 2672 m_adj(m, sizeof(u_int64_t)); 2673 2674 /* 2675 * If this is a PNIC chip, zero the buffer. This is part 2676 * of the workaround for the receive bug in the 82c168 and 2677 * 82c169 chips. 2678 */ 2679 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2680 bzero(mtod(m, char *), m->m_len); 2681 2682 error = bus_dmamap_load_mbuf_sg(sc->dc_rx_mtag, sc->dc_sparemap, 2683 m, segs, &nseg, 0); 2684 if (error) { 2685 m_freem(m); 2686 return (error); 2687 } 2688 KASSERT(nseg == 1, ("%s: wrong number of segments (%d)", __func__, 2689 nseg)); 2690 if (sc->dc_cdata.dc_rx_chain[i] != NULL) 2691 bus_dmamap_unload(sc->dc_rx_mtag, sc->dc_cdata.dc_rx_map[i]); 2692 2693 map = sc->dc_cdata.dc_rx_map[i]; 2694 sc->dc_cdata.dc_rx_map[i] = sc->dc_sparemap; 2695 sc->dc_sparemap = map; 2696 sc->dc_cdata.dc_rx_chain[i] = m; 2697 bus_dmamap_sync(sc->dc_rx_mtag, sc->dc_cdata.dc_rx_map[i], 2698 BUS_DMASYNC_PREREAD); 2699 2700 sc->dc_ldata.dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN); 2701 sc->dc_ldata.dc_rx_list[i].dc_data = 2702 htole32(DC_ADDR_LO(segs[0].ds_addr)); 2703 sc->dc_ldata.dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN); 2704 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, 2705 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2706 return (0); 2707 } 2708 2709 /* 2710 * Grrrrr. 2711 * The PNIC chip has a terrible bug in it that manifests itself during 2712 * periods of heavy activity. The exact mode of failure if difficult to 2713 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2714 * will happen on slow machines. The bug is that sometimes instead of 2715 * uploading one complete frame during reception, it uploads what looks 2716 * like the entire contents of its FIFO memory. The frame we want is at 2717 * the end of the whole mess, but we never know exactly how much data has 2718 * been uploaded, so salvaging the frame is hard. 2719 * 2720 * There is only one way to do it reliably, and it's disgusting. 2721 * Here's what we know: 2722 * 2723 * - We know there will always be somewhere between one and three extra 2724 * descriptors uploaded. 2725 * 2726 * - We know the desired received frame will always be at the end of the 2727 * total data upload. 2728 * 2729 * - We know the size of the desired received frame because it will be 2730 * provided in the length field of the status word in the last descriptor. 2731 * 2732 * Here's what we do: 2733 * 2734 * - When we allocate buffers for the receive ring, we bzero() them. 2735 * This means that we know that the buffer contents should be all 2736 * zeros, except for data uploaded by the chip. 2737 * 2738 * - We also force the PNIC chip to upload frames that include the 2739 * ethernet CRC at the end. 2740 * 2741 * - We gather all of the bogus frame data into a single buffer. 2742 * 2743 * - We then position a pointer at the end of this buffer and scan 2744 * backwards until we encounter the first non-zero byte of data. 2745 * This is the end of the received frame. We know we will encounter 2746 * some data at the end of the frame because the CRC will always be 2747 * there, so even if the sender transmits a packet of all zeros, 2748 * we won't be fooled. 2749 * 2750 * - We know the size of the actual received frame, so we subtract 2751 * that value from the current pointer location. This brings us 2752 * to the start of the actual received packet. 2753 * 2754 * - We copy this into an mbuf and pass it on, along with the actual 2755 * frame length. 2756 * 2757 * The performance hit is tremendous, but it beats dropping frames all 2758 * the time. 2759 */ 2760 2761 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG | DC_RXSTAT_LASTFRAG) 2762 static void 2763 dc_pnic_rx_bug_war(struct dc_softc *sc, int idx) 2764 { 2765 struct dc_desc *cur_rx; 2766 struct dc_desc *c = NULL; 2767 struct mbuf *m = NULL; 2768 unsigned char *ptr; 2769 int i, total_len; 2770 uint32_t rxstat = 0; 2771 2772 i = sc->dc_pnic_rx_bug_save; 2773 cur_rx = &sc->dc_ldata.dc_rx_list[idx]; 2774 ptr = sc->dc_pnic_rx_buf; 2775 bzero(ptr, DC_RXLEN * 5); 2776 2777 /* Copy all the bytes from the bogus buffers. */ 2778 while (1) { 2779 c = &sc->dc_ldata.dc_rx_list[i]; 2780 rxstat = le32toh(c->dc_status); 2781 m = sc->dc_cdata.dc_rx_chain[i]; 2782 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2783 ptr += DC_RXLEN; 2784 /* If this is the last buffer, break out. */ 2785 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2786 break; 2787 dc_discard_rxbuf(sc, i); 2788 DC_INC(i, DC_RX_LIST_CNT); 2789 } 2790 2791 /* Find the length of the actual receive frame. */ 2792 total_len = DC_RXBYTES(rxstat); 2793 2794 /* Scan backwards until we hit a non-zero byte. */ 2795 while (*ptr == 0x00) 2796 ptr--; 2797 2798 /* Round off. */ 2799 if ((uintptr_t)(ptr) & 0x3) 2800 ptr -= 1; 2801 2802 /* Now find the start of the frame. */ 2803 ptr -= total_len; 2804 if (ptr < sc->dc_pnic_rx_buf) 2805 ptr = sc->dc_pnic_rx_buf; 2806 2807 /* 2808 * Now copy the salvaged frame to the last mbuf and fake up 2809 * the status word to make it look like a successful 2810 * frame reception. 2811 */ 2812 bcopy(ptr, mtod(m, char *), total_len); 2813 cur_rx->dc_status = htole32(rxstat | DC_RXSTAT_FIRSTFRAG); 2814 } 2815 2816 /* 2817 * This routine searches the RX ring for dirty descriptors in the 2818 * event that the rxeof routine falls out of sync with the chip's 2819 * current descriptor pointer. This may happen sometimes as a result 2820 * of a "no RX buffer available" condition that happens when the chip 2821 * consumes all of the RX buffers before the driver has a chance to 2822 * process the RX ring. This routine may need to be called more than 2823 * once to bring the driver back in sync with the chip, however we 2824 * should still be getting RX DONE interrupts to drive the search 2825 * for new packets in the RX ring, so we should catch up eventually. 2826 */ 2827 static int 2828 dc_rx_resync(struct dc_softc *sc) 2829 { 2830 struct dc_desc *cur_rx; 2831 int i, pos; 2832 2833 pos = sc->dc_cdata.dc_rx_prod; 2834 2835 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2836 cur_rx = &sc->dc_ldata.dc_rx_list[pos]; 2837 if (!(le32toh(cur_rx->dc_status) & DC_RXSTAT_OWN)) 2838 break; 2839 DC_INC(pos, DC_RX_LIST_CNT); 2840 } 2841 2842 /* If the ring really is empty, then just return. */ 2843 if (i == DC_RX_LIST_CNT) 2844 return (0); 2845 2846 /* We've fallen behing the chip: catch it. */ 2847 sc->dc_cdata.dc_rx_prod = pos; 2848 2849 return (EAGAIN); 2850 } 2851 2852 static void 2853 dc_discard_rxbuf(struct dc_softc *sc, int i) 2854 { 2855 struct mbuf *m; 2856 2857 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2858 m = sc->dc_cdata.dc_rx_chain[i]; 2859 bzero(mtod(m, char *), m->m_len); 2860 } 2861 2862 sc->dc_ldata.dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN); 2863 sc->dc_ldata.dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN); 2864 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, BUS_DMASYNC_PREREAD | 2865 BUS_DMASYNC_PREWRITE); 2866 } 2867 2868 /* 2869 * A frame has been uploaded: pass the resulting mbuf chain up to 2870 * the higher level protocols. 2871 */ 2872 static int 2873 dc_rxeof(struct dc_softc *sc) 2874 { 2875 struct mbuf *m; 2876 struct ifnet *ifp; 2877 struct dc_desc *cur_rx; 2878 int i, total_len, rx_npkts; 2879 uint32_t rxstat; 2880 2881 DC_LOCK_ASSERT(sc); 2882 2883 ifp = sc->dc_ifp; 2884 rx_npkts = 0; 2885 2886 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, BUS_DMASYNC_POSTREAD | 2887 BUS_DMASYNC_POSTWRITE); 2888 for (i = sc->dc_cdata.dc_rx_prod; 2889 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0; 2890 DC_INC(i, DC_RX_LIST_CNT)) { 2891 #ifdef DEVICE_POLLING 2892 if (ifp->if_capenable & IFCAP_POLLING) { 2893 if (sc->rxcycles <= 0) 2894 break; 2895 sc->rxcycles--; 2896 } 2897 #endif 2898 cur_rx = &sc->dc_ldata.dc_rx_list[i]; 2899 rxstat = le32toh(cur_rx->dc_status); 2900 if ((rxstat & DC_RXSTAT_OWN) != 0) 2901 break; 2902 m = sc->dc_cdata.dc_rx_chain[i]; 2903 bus_dmamap_sync(sc->dc_rx_mtag, sc->dc_cdata.dc_rx_map[i], 2904 BUS_DMASYNC_POSTREAD); 2905 total_len = DC_RXBYTES(rxstat); 2906 rx_npkts++; 2907 2908 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2909 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2910 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2911 sc->dc_pnic_rx_bug_save = i; 2912 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) 2913 continue; 2914 dc_pnic_rx_bug_war(sc, i); 2915 rxstat = le32toh(cur_rx->dc_status); 2916 total_len = DC_RXBYTES(rxstat); 2917 } 2918 } 2919 2920 /* 2921 * If an error occurs, update stats, clear the 2922 * status word and leave the mbuf cluster in place: 2923 * it should simply get re-used next time this descriptor 2924 * comes up in the ring. However, don't report long 2925 * frames as errors since they could be vlans. 2926 */ 2927 if ((rxstat & DC_RXSTAT_RXERR)) { 2928 if (!(rxstat & DC_RXSTAT_GIANT) || 2929 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2930 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2931 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2932 ifp->if_ierrors++; 2933 if (rxstat & DC_RXSTAT_COLLSEEN) 2934 ifp->if_collisions++; 2935 dc_discard_rxbuf(sc, i); 2936 if (rxstat & DC_RXSTAT_CRCERR) 2937 continue; 2938 else { 2939 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2940 dc_init_locked(sc); 2941 return (rx_npkts); 2942 } 2943 } 2944 } 2945 2946 /* No errors; receive the packet. */ 2947 total_len -= ETHER_CRC_LEN; 2948 #ifdef __NO_STRICT_ALIGNMENT 2949 /* 2950 * On architectures without alignment problems we try to 2951 * allocate a new buffer for the receive ring, and pass up 2952 * the one where the packet is already, saving the expensive 2953 * copy done in m_devget(). 2954 * If we are on an architecture with alignment problems, or 2955 * if the allocation fails, then use m_devget and leave the 2956 * existing buffer in the receive ring. 2957 */ 2958 if (dc_newbuf(sc, i) != 0) { 2959 dc_discard_rxbuf(sc, i); 2960 ifp->if_iqdrops++; 2961 continue; 2962 } 2963 m->m_pkthdr.rcvif = ifp; 2964 m->m_pkthdr.len = m->m_len = total_len; 2965 #else 2966 { 2967 struct mbuf *m0; 2968 2969 m0 = m_devget(mtod(m, char *), total_len, 2970 ETHER_ALIGN, ifp, NULL); 2971 dc_discard_rxbuf(sc, i); 2972 if (m0 == NULL) { 2973 ifp->if_iqdrops++; 2974 continue; 2975 } 2976 m = m0; 2977 } 2978 #endif 2979 2980 ifp->if_ipackets++; 2981 DC_UNLOCK(sc); 2982 (*ifp->if_input)(ifp, m); 2983 DC_LOCK(sc); 2984 } 2985 2986 sc->dc_cdata.dc_rx_prod = i; 2987 return (rx_npkts); 2988 } 2989 2990 /* 2991 * A frame was downloaded to the chip. It's safe for us to clean up 2992 * the list buffers. 2993 */ 2994 static void 2995 dc_txeof(struct dc_softc *sc) 2996 { 2997 struct dc_desc *cur_tx; 2998 struct ifnet *ifp; 2999 int idx, setup; 3000 uint32_t ctl, txstat; 3001 3002 if (sc->dc_cdata.dc_tx_cnt == 0) 3003 return; 3004 3005 ifp = sc->dc_ifp; 3006 3007 /* 3008 * Go through our tx list and free mbufs for those 3009 * frames that have been transmitted. 3010 */ 3011 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, BUS_DMASYNC_POSTREAD | 3012 BUS_DMASYNC_POSTWRITE); 3013 setup = 0; 3014 for (idx = sc->dc_cdata.dc_tx_cons; idx != sc->dc_cdata.dc_tx_prod; 3015 DC_INC(idx, DC_TX_LIST_CNT), sc->dc_cdata.dc_tx_cnt--) { 3016 cur_tx = &sc->dc_ldata.dc_tx_list[idx]; 3017 txstat = le32toh(cur_tx->dc_status); 3018 ctl = le32toh(cur_tx->dc_ctl); 3019 3020 if (txstat & DC_TXSTAT_OWN) 3021 break; 3022 3023 if (sc->dc_cdata.dc_tx_chain[idx] == NULL) 3024 continue; 3025 3026 if (ctl & DC_TXCTL_SETUP) { 3027 cur_tx->dc_ctl = htole32(ctl & ~DC_TXCTL_SETUP); 3028 setup++; 3029 bus_dmamap_sync(sc->dc_stag, sc->dc_smap, 3030 BUS_DMASYNC_POSTWRITE); 3031 /* 3032 * Yes, the PNIC is so brain damaged 3033 * that it will sometimes generate a TX 3034 * underrun error while DMAing the RX 3035 * filter setup frame. If we detect this, 3036 * we have to send the setup frame again, 3037 * or else the filter won't be programmed 3038 * correctly. 3039 */ 3040 if (DC_IS_PNIC(sc)) { 3041 if (txstat & DC_TXSTAT_ERRSUM) 3042 dc_setfilt(sc); 3043 } 3044 sc->dc_cdata.dc_tx_chain[idx] = NULL; 3045 continue; 3046 } 3047 3048 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) { 3049 /* 3050 * XXX: Why does my Xircom taunt me so? 3051 * For some reason it likes setting the CARRLOST flag 3052 * even when the carrier is there. wtf?!? 3053 * Who knows, but Conexant chips have the 3054 * same problem. Maybe they took lessons 3055 * from Xircom. 3056 */ 3057 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 3058 sc->dc_pmode == DC_PMODE_MII && 3059 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 3060 DC_TXSTAT_NOCARRIER))) 3061 txstat &= ~DC_TXSTAT_ERRSUM; 3062 } else { 3063 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 3064 sc->dc_pmode == DC_PMODE_MII && 3065 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 3066 DC_TXSTAT_NOCARRIER | DC_TXSTAT_CARRLOST))) 3067 txstat &= ~DC_TXSTAT_ERRSUM; 3068 } 3069 3070 if (txstat & DC_TXSTAT_ERRSUM) { 3071 ifp->if_oerrors++; 3072 if (txstat & DC_TXSTAT_EXCESSCOLL) 3073 ifp->if_collisions++; 3074 if (txstat & DC_TXSTAT_LATECOLL) 3075 ifp->if_collisions++; 3076 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 3077 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3078 dc_init_locked(sc); 3079 return; 3080 } 3081 } else 3082 ifp->if_opackets++; 3083 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 3084 3085 bus_dmamap_sync(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx], 3086 BUS_DMASYNC_POSTWRITE); 3087 bus_dmamap_unload(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx]); 3088 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 3089 sc->dc_cdata.dc_tx_chain[idx] = NULL; 3090 } 3091 sc->dc_cdata.dc_tx_cons = idx; 3092 3093 if (sc->dc_cdata.dc_tx_cnt <= DC_TX_LIST_CNT - DC_TX_LIST_RSVD) { 3094 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3095 if (sc->dc_cdata.dc_tx_cnt == 0) 3096 sc->dc_wdog_timer = 0; 3097 } 3098 if (setup > 0) 3099 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, 3100 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3101 } 3102 3103 static void 3104 dc_tick(void *xsc) 3105 { 3106 struct dc_softc *sc; 3107 struct mii_data *mii; 3108 struct ifnet *ifp; 3109 uint32_t r; 3110 3111 sc = xsc; 3112 DC_LOCK_ASSERT(sc); 3113 ifp = sc->dc_ifp; 3114 mii = device_get_softc(sc->dc_miibus); 3115 3116 /* 3117 * Reclaim transmitted frames for controllers that do 3118 * not generate TX completion interrupt for every frame. 3119 */ 3120 if (sc->dc_flags & DC_TX_USE_TX_INTR) 3121 dc_txeof(sc); 3122 3123 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 3124 if (sc->dc_flags & DC_21143_NWAY) { 3125 r = CSR_READ_4(sc, DC_10BTSTAT); 3126 if (IFM_SUBTYPE(mii->mii_media_active) == 3127 IFM_100_TX && (r & DC_TSTAT_LS100)) { 3128 sc->dc_link = 0; 3129 mii_mediachg(mii); 3130 } 3131 if (IFM_SUBTYPE(mii->mii_media_active) == 3132 IFM_10_T && (r & DC_TSTAT_LS10)) { 3133 sc->dc_link = 0; 3134 mii_mediachg(mii); 3135 } 3136 if (sc->dc_link == 0) 3137 mii_tick(mii); 3138 } else { 3139 /* 3140 * For NICs which never report DC_RXSTATE_WAIT, we 3141 * have to bite the bullet... 3142 */ 3143 if ((DC_HAS_BROKEN_RXSTATE(sc) || (CSR_READ_4(sc, 3144 DC_ISR) & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT) && 3145 sc->dc_cdata.dc_tx_cnt == 0) 3146 mii_tick(mii); 3147 } 3148 } else 3149 mii_tick(mii); 3150 3151 /* 3152 * When the init routine completes, we expect to be able to send 3153 * packets right away, and in fact the network code will send a 3154 * gratuitous ARP the moment the init routine marks the interface 3155 * as running. However, even though the MAC may have been initialized, 3156 * there may be a delay of a few seconds before the PHY completes 3157 * autonegotiation and the link is brought up. Any transmissions 3158 * made during that delay will be lost. Dealing with this is tricky: 3159 * we can't just pause in the init routine while waiting for the 3160 * PHY to come ready since that would bring the whole system to 3161 * a screeching halt for several seconds. 3162 * 3163 * What we do here is prevent the TX start routine from sending 3164 * any packets until a link has been established. After the 3165 * interface has been initialized, the tick routine will poll 3166 * the state of the PHY until the IFM_ACTIVE flag is set. Until 3167 * that time, packets will stay in the send queue, and once the 3168 * link comes up, they will be flushed out to the wire. 3169 */ 3170 if (sc->dc_link != 0 && !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3171 dc_start_locked(ifp); 3172 3173 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 3174 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3175 else 3176 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3177 } 3178 3179 /* 3180 * A transmit underrun has occurred. Back off the transmit threshold, 3181 * or switch to store and forward mode if we have to. 3182 */ 3183 static void 3184 dc_tx_underrun(struct dc_softc *sc) 3185 { 3186 uint32_t netcfg, isr; 3187 int i, reinit; 3188 3189 reinit = 0; 3190 netcfg = CSR_READ_4(sc, DC_NETCFG); 3191 device_printf(sc->dc_dev, "TX underrun -- "); 3192 if ((sc->dc_flags & DC_TX_STORENFWD) == 0) { 3193 if (sc->dc_txthresh + DC_TXTHRESH_INC > DC_TXTHRESH_MAX) { 3194 printf("using store and forward mode\n"); 3195 netcfg |= DC_NETCFG_STORENFWD; 3196 } else { 3197 printf("increasing TX threshold\n"); 3198 sc->dc_txthresh += DC_TXTHRESH_INC; 3199 netcfg &= ~DC_NETCFG_TX_THRESH; 3200 netcfg |= sc->dc_txthresh; 3201 } 3202 3203 if (DC_IS_INTEL(sc)) { 3204 /* 3205 * The real 21143 requires that the transmitter be idle 3206 * in order to change the transmit threshold or store 3207 * and forward state. 3208 */ 3209 CSR_WRITE_4(sc, DC_NETCFG, netcfg & ~DC_NETCFG_TX_ON); 3210 3211 for (i = 0; i < DC_TIMEOUT; i++) { 3212 isr = CSR_READ_4(sc, DC_ISR); 3213 if (isr & DC_ISR_TX_IDLE) 3214 break; 3215 DELAY(10); 3216 } 3217 if (i == DC_TIMEOUT) { 3218 device_printf(sc->dc_dev, 3219 "%s: failed to force tx to idle state\n", 3220 __func__); 3221 reinit++; 3222 } 3223 } 3224 } else { 3225 printf("resetting\n"); 3226 reinit++; 3227 } 3228 3229 if (reinit == 0) { 3230 CSR_WRITE_4(sc, DC_NETCFG, netcfg); 3231 if (DC_IS_INTEL(sc)) 3232 CSR_WRITE_4(sc, DC_NETCFG, netcfg | DC_NETCFG_TX_ON); 3233 } else { 3234 sc->dc_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3235 dc_init_locked(sc); 3236 } 3237 } 3238 3239 #ifdef DEVICE_POLLING 3240 static poll_handler_t dc_poll; 3241 3242 static int 3243 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 3244 { 3245 struct dc_softc *sc = ifp->if_softc; 3246 int rx_npkts = 0; 3247 3248 DC_LOCK(sc); 3249 3250 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3251 DC_UNLOCK(sc); 3252 return (rx_npkts); 3253 } 3254 3255 sc->rxcycles = count; 3256 rx_npkts = dc_rxeof(sc); 3257 dc_txeof(sc); 3258 if (!IFQ_IS_EMPTY(&ifp->if_snd) && 3259 !(ifp->if_drv_flags & IFF_DRV_OACTIVE)) 3260 dc_start_locked(ifp); 3261 3262 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 3263 uint32_t status; 3264 3265 status = CSR_READ_4(sc, DC_ISR); 3266 status &= (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF | 3267 DC_ISR_TX_NOBUF | DC_ISR_TX_IDLE | DC_ISR_TX_UNDERRUN | 3268 DC_ISR_BUS_ERR); 3269 if (!status) { 3270 DC_UNLOCK(sc); 3271 return (rx_npkts); 3272 } 3273 /* ack what we have */ 3274 CSR_WRITE_4(sc, DC_ISR, status); 3275 3276 if (status & (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF)) { 3277 uint32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 3278 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 3279 3280 if (dc_rx_resync(sc)) 3281 dc_rxeof(sc); 3282 } 3283 /* restart transmit unit if necessary */ 3284 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 3285 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3286 3287 if (status & DC_ISR_TX_UNDERRUN) 3288 dc_tx_underrun(sc); 3289 3290 if (status & DC_ISR_BUS_ERR) { 3291 if_printf(ifp, "%s: bus error\n", __func__); 3292 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3293 dc_init_locked(sc); 3294 } 3295 } 3296 DC_UNLOCK(sc); 3297 return (rx_npkts); 3298 } 3299 #endif /* DEVICE_POLLING */ 3300 3301 static void 3302 dc_intr(void *arg) 3303 { 3304 struct dc_softc *sc; 3305 struct ifnet *ifp; 3306 uint32_t r, status; 3307 int n; 3308 3309 sc = arg; 3310 3311 if (sc->suspended) 3312 return; 3313 3314 DC_LOCK(sc); 3315 status = CSR_READ_4(sc, DC_ISR); 3316 if (status == 0xFFFFFFFF || (status & DC_INTRS) == 0) { 3317 DC_UNLOCK(sc); 3318 return; 3319 } 3320 ifp = sc->dc_ifp; 3321 #ifdef DEVICE_POLLING 3322 if (ifp->if_capenable & IFCAP_POLLING) { 3323 DC_UNLOCK(sc); 3324 return; 3325 } 3326 #endif 3327 /* Disable interrupts. */ 3328 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3329 3330 for (n = 16; n > 0; n--) { 3331 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 3332 break; 3333 /* Ack interrupts. */ 3334 CSR_WRITE_4(sc, DC_ISR, status); 3335 3336 if (status & DC_ISR_RX_OK) { 3337 if (dc_rxeof(sc) == 0) { 3338 while (dc_rx_resync(sc)) 3339 dc_rxeof(sc); 3340 } 3341 } 3342 3343 if (status & (DC_ISR_TX_OK | DC_ISR_TX_NOBUF)) 3344 dc_txeof(sc); 3345 3346 if (status & DC_ISR_TX_IDLE) { 3347 dc_txeof(sc); 3348 if (sc->dc_cdata.dc_tx_cnt) { 3349 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3350 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3351 } 3352 } 3353 3354 if (status & DC_ISR_TX_UNDERRUN) 3355 dc_tx_underrun(sc); 3356 3357 if ((status & DC_ISR_RX_WATDOGTIMEO) 3358 || (status & DC_ISR_RX_NOBUF)) { 3359 r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 3360 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 3361 if (dc_rxeof(sc) == 0) { 3362 while (dc_rx_resync(sc)) 3363 dc_rxeof(sc); 3364 } 3365 } 3366 3367 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3368 dc_start_locked(ifp); 3369 3370 if (status & DC_ISR_BUS_ERR) { 3371 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3372 dc_init_locked(sc); 3373 DC_UNLOCK(sc); 3374 return; 3375 } 3376 status = CSR_READ_4(sc, DC_ISR); 3377 if (status == 0xFFFFFFFF || (status & DC_INTRS) == 0) 3378 break; 3379 } 3380 3381 /* Re-enable interrupts. */ 3382 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3383 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3384 3385 DC_UNLOCK(sc); 3386 } 3387 3388 /* 3389 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 3390 * pointers to the fragment pointers. 3391 */ 3392 static int 3393 dc_encap(struct dc_softc *sc, struct mbuf **m_head) 3394 { 3395 bus_dma_segment_t segs[DC_MAXFRAGS]; 3396 bus_dmamap_t map; 3397 struct dc_desc *f; 3398 struct mbuf *m; 3399 int cur, defragged, error, first, frag, i, idx, nseg; 3400 3401 m = NULL; 3402 defragged = 0; 3403 if (sc->dc_flags & DC_TX_COALESCE && 3404 ((*m_head)->m_next != NULL || sc->dc_flags & DC_TX_ALIGN)) { 3405 m = m_defrag(*m_head, M_DONTWAIT); 3406 defragged = 1; 3407 } else { 3408 /* 3409 * Count the number of frags in this chain to see if we 3410 * need to m_collapse. Since the descriptor list is shared 3411 * by all packets, we'll m_collapse long chains so that they 3412 * do not use up the entire list, even if they would fit. 3413 */ 3414 i = 0; 3415 for (m = *m_head; m != NULL; m = m->m_next) 3416 i++; 3417 if (i > DC_TX_LIST_CNT / 4 || 3418 DC_TX_LIST_CNT - i + sc->dc_cdata.dc_tx_cnt <= 3419 DC_TX_LIST_RSVD) { 3420 m = m_collapse(*m_head, M_DONTWAIT, DC_MAXFRAGS); 3421 defragged = 1; 3422 } 3423 } 3424 if (defragged != 0) { 3425 if (m == NULL) { 3426 m_freem(*m_head); 3427 *m_head = NULL; 3428 return (ENOBUFS); 3429 } 3430 *m_head = m; 3431 } 3432 3433 idx = sc->dc_cdata.dc_tx_prod; 3434 error = bus_dmamap_load_mbuf_sg(sc->dc_tx_mtag, 3435 sc->dc_cdata.dc_tx_map[idx], *m_head, segs, &nseg, 0); 3436 if (error == EFBIG) { 3437 if (defragged != 0 || (m = m_collapse(*m_head, M_DONTWAIT, 3438 DC_MAXFRAGS)) == NULL) { 3439 m_freem(*m_head); 3440 *m_head = NULL; 3441 return (defragged != 0 ? error : ENOBUFS); 3442 } 3443 *m_head = m; 3444 error = bus_dmamap_load_mbuf_sg(sc->dc_tx_mtag, 3445 sc->dc_cdata.dc_tx_map[idx], *m_head, segs, &nseg, 0); 3446 if (error != 0) { 3447 m_freem(*m_head); 3448 *m_head = NULL; 3449 return (error); 3450 } 3451 } else if (error != 0) 3452 return (error); 3453 KASSERT(nseg <= DC_MAXFRAGS, 3454 ("%s: wrong number of segments (%d)", __func__, nseg)); 3455 if (nseg == 0) { 3456 m_freem(*m_head); 3457 *m_head = NULL; 3458 return (EIO); 3459 } 3460 3461 /* Check descriptor overruns. */ 3462 if (sc->dc_cdata.dc_tx_cnt + nseg > DC_TX_LIST_CNT - DC_TX_LIST_RSVD) { 3463 bus_dmamap_unload(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx]); 3464 return (ENOBUFS); 3465 } 3466 bus_dmamap_sync(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx], 3467 BUS_DMASYNC_PREWRITE); 3468 3469 first = cur = frag = sc->dc_cdata.dc_tx_prod; 3470 for (i = 0; i < nseg; i++) { 3471 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) && 3472 (frag == (DC_TX_LIST_CNT - 1)) && 3473 (first != sc->dc_cdata.dc_tx_first)) { 3474 bus_dmamap_unload(sc->dc_tx_mtag, 3475 sc->dc_cdata.dc_tx_map[first]); 3476 m_freem(*m_head); 3477 *m_head = NULL; 3478 return (ENOBUFS); 3479 } 3480 3481 f = &sc->dc_ldata.dc_tx_list[frag]; 3482 f->dc_ctl = htole32(DC_TXCTL_TLINK | segs[i].ds_len); 3483 if (i == 0) { 3484 f->dc_status = 0; 3485 f->dc_ctl |= htole32(DC_TXCTL_FIRSTFRAG); 3486 } else 3487 f->dc_status = htole32(DC_TXSTAT_OWN); 3488 f->dc_data = htole32(DC_ADDR_LO(segs[i].ds_addr)); 3489 cur = frag; 3490 DC_INC(frag, DC_TX_LIST_CNT); 3491 } 3492 3493 sc->dc_cdata.dc_tx_prod = frag; 3494 sc->dc_cdata.dc_tx_cnt += nseg; 3495 sc->dc_cdata.dc_tx_chain[cur] = *m_head; 3496 sc->dc_ldata.dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_LASTFRAG); 3497 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 3498 sc->dc_ldata.dc_tx_list[first].dc_ctl |= 3499 htole32(DC_TXCTL_FINT); 3500 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 3501 sc->dc_ldata.dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3502 if (sc->dc_flags & DC_TX_USE_TX_INTR && 3503 ++sc->dc_cdata.dc_tx_pkts >= 8) { 3504 sc->dc_cdata.dc_tx_pkts = 0; 3505 sc->dc_ldata.dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3506 } 3507 sc->dc_ldata.dc_tx_list[first].dc_status = htole32(DC_TXSTAT_OWN); 3508 3509 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, 3510 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3511 3512 /* 3513 * Swap the last and the first dmamaps to ensure the map for 3514 * this transmission is placed at the last descriptor. 3515 */ 3516 map = sc->dc_cdata.dc_tx_map[cur]; 3517 sc->dc_cdata.dc_tx_map[cur] = sc->dc_cdata.dc_tx_map[first]; 3518 sc->dc_cdata.dc_tx_map[first] = map; 3519 3520 return (0); 3521 } 3522 3523 static void 3524 dc_start(struct ifnet *ifp) 3525 { 3526 struct dc_softc *sc; 3527 3528 sc = ifp->if_softc; 3529 DC_LOCK(sc); 3530 dc_start_locked(ifp); 3531 DC_UNLOCK(sc); 3532 } 3533 3534 /* 3535 * Main transmit routine 3536 * To avoid having to do mbuf copies, we put pointers to the mbuf data 3537 * regions directly in the transmit lists. We also save a copy of the 3538 * pointers since the transmit list fragment pointers are physical 3539 * addresses. 3540 */ 3541 static void 3542 dc_start_locked(struct ifnet *ifp) 3543 { 3544 struct dc_softc *sc; 3545 struct mbuf *m_head; 3546 int queued; 3547 3548 sc = ifp->if_softc; 3549 3550 DC_LOCK_ASSERT(sc); 3551 3552 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 3553 IFF_DRV_RUNNING || sc->dc_link == 0) 3554 return; 3555 3556 sc->dc_cdata.dc_tx_first = sc->dc_cdata.dc_tx_prod; 3557 3558 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 3559 /* 3560 * If there's no way we can send any packets, return now. 3561 */ 3562 if (sc->dc_cdata.dc_tx_cnt > DC_TX_LIST_CNT - DC_TX_LIST_RSVD) { 3563 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3564 break; 3565 } 3566 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 3567 if (m_head == NULL) 3568 break; 3569 3570 if (dc_encap(sc, &m_head)) { 3571 if (m_head == NULL) 3572 break; 3573 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3574 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3575 break; 3576 } 3577 3578 queued++; 3579 /* 3580 * If there's a BPF listener, bounce a copy of this frame 3581 * to him. 3582 */ 3583 BPF_MTAP(ifp, m_head); 3584 } 3585 3586 if (queued > 0) { 3587 /* Transmit */ 3588 if (!(sc->dc_flags & DC_TX_POLL)) 3589 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3590 3591 /* 3592 * Set a timeout in case the chip goes out to lunch. 3593 */ 3594 sc->dc_wdog_timer = 5; 3595 } 3596 } 3597 3598 static void 3599 dc_init(void *xsc) 3600 { 3601 struct dc_softc *sc = xsc; 3602 3603 DC_LOCK(sc); 3604 dc_init_locked(sc); 3605 DC_UNLOCK(sc); 3606 } 3607 3608 static void 3609 dc_init_locked(struct dc_softc *sc) 3610 { 3611 struct ifnet *ifp = sc->dc_ifp; 3612 struct mii_data *mii; 3613 struct ifmedia *ifm; 3614 3615 DC_LOCK_ASSERT(sc); 3616 3617 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3618 return; 3619 3620 mii = device_get_softc(sc->dc_miibus); 3621 3622 /* 3623 * Cancel pending I/O and free all RX/TX buffers. 3624 */ 3625 dc_stop(sc); 3626 dc_reset(sc); 3627 if (DC_IS_INTEL(sc)) { 3628 ifm = &mii->mii_media; 3629 dc_apply_fixup(sc, ifm->ifm_media); 3630 } 3631 3632 /* 3633 * Set cache alignment and burst length. 3634 */ 3635 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc) || DC_IS_ULI(sc)) 3636 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3637 else 3638 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME | DC_BUSCTL_MRLE); 3639 /* 3640 * Evenly share the bus between receive and transmit process. 3641 */ 3642 if (DC_IS_INTEL(sc)) 3643 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3644 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3645 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3646 } else { 3647 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3648 } 3649 if (sc->dc_flags & DC_TX_POLL) 3650 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3651 switch(sc->dc_cachesize) { 3652 case 32: 3653 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3654 break; 3655 case 16: 3656 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3657 break; 3658 case 8: 3659 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3660 break; 3661 case 0: 3662 default: 3663 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3664 break; 3665 } 3666 3667 if (sc->dc_flags & DC_TX_STORENFWD) 3668 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3669 else { 3670 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3671 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3672 } else { 3673 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3674 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3675 } 3676 } 3677 3678 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3679 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3680 3681 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3682 /* 3683 * The app notes for the 98713 and 98715A say that 3684 * in order to have the chips operate properly, a magic 3685 * number must be written to CSR16. Macronix does not 3686 * document the meaning of these bits so there's no way 3687 * to know exactly what they do. The 98713 has a magic 3688 * number all its own; the rest all use a different one. 3689 */ 3690 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3691 if (sc->dc_type == DC_TYPE_98713) 3692 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3693 else 3694 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3695 } 3696 3697 if (DC_IS_XIRCOM(sc)) { 3698 /* 3699 * setup General Purpose Port mode and data so the tulip 3700 * can talk to the MII. 3701 */ 3702 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3703 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3704 DELAY(10); 3705 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3706 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3707 DELAY(10); 3708 } 3709 3710 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3711 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3712 3713 /* Init circular RX list. */ 3714 if (dc_list_rx_init(sc) == ENOBUFS) { 3715 device_printf(sc->dc_dev, 3716 "initialization failed: no memory for rx buffers\n"); 3717 dc_stop(sc); 3718 return; 3719 } 3720 3721 /* 3722 * Init TX descriptors. 3723 */ 3724 dc_list_tx_init(sc); 3725 3726 /* 3727 * Load the address of the RX list. 3728 */ 3729 CSR_WRITE_4(sc, DC_RXADDR, DC_RXDESC(sc, 0)); 3730 CSR_WRITE_4(sc, DC_TXADDR, DC_TXDESC(sc, 0)); 3731 3732 /* 3733 * Enable interrupts. 3734 */ 3735 #ifdef DEVICE_POLLING 3736 /* 3737 * ... but only if we are not polling, and make sure they are off in 3738 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3739 * after a reset. 3740 */ 3741 if (ifp->if_capenable & IFCAP_POLLING) 3742 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3743 else 3744 #endif 3745 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3746 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3747 3748 /* Initialize TX jabber and RX watchdog timer. */ 3749 if (DC_IS_ULI(sc)) 3750 CSR_WRITE_4(sc, DC_WATCHDOG, DC_WDOG_JABBERCLK | 3751 DC_WDOG_HOSTUNJAB); 3752 3753 /* Enable transmitter. */ 3754 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3755 3756 /* 3757 * If this is an Intel 21143 and we're not using the 3758 * MII port, program the LED control pins so we get 3759 * link and activity indications. 3760 */ 3761 if (sc->dc_flags & DC_TULIP_LEDS) { 3762 CSR_WRITE_4(sc, DC_WATCHDOG, 3763 DC_WDOG_CTLWREN | DC_WDOG_LINK | DC_WDOG_ACTIVITY); 3764 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3765 } 3766 3767 /* 3768 * Load the RX/multicast filter. We do this sort of late 3769 * because the filter programming scheme on the 21143 and 3770 * some clones requires DMAing a setup frame via the TX 3771 * engine, and we need the transmitter enabled for that. 3772 */ 3773 dc_setfilt(sc); 3774 3775 /* Enable receiver. */ 3776 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3777 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3778 3779 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3780 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3781 3782 dc_ifmedia_upd_locked(sc); 3783 3784 /* Clear missed frames and overflow counter. */ 3785 CSR_READ_4(sc, DC_FRAMESDISCARDED); 3786 3787 /* Don't start the ticker if this is a homePNA link. */ 3788 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) 3789 sc->dc_link = 1; 3790 else { 3791 if (sc->dc_flags & DC_21143_NWAY) 3792 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3793 else 3794 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3795 } 3796 3797 sc->dc_wdog_timer = 0; 3798 callout_reset(&sc->dc_wdog_ch, hz, dc_watchdog, sc); 3799 } 3800 3801 /* 3802 * Set media options. 3803 */ 3804 static int 3805 dc_ifmedia_upd(struct ifnet *ifp) 3806 { 3807 struct dc_softc *sc; 3808 int error; 3809 3810 sc = ifp->if_softc; 3811 DC_LOCK(sc); 3812 error = dc_ifmedia_upd_locked(sc); 3813 DC_UNLOCK(sc); 3814 return (error); 3815 } 3816 3817 static int 3818 dc_ifmedia_upd_locked(struct dc_softc *sc) 3819 { 3820 struct mii_data *mii; 3821 struct ifmedia *ifm; 3822 int error; 3823 3824 DC_LOCK_ASSERT(sc); 3825 3826 sc->dc_link = 0; 3827 mii = device_get_softc(sc->dc_miibus); 3828 error = mii_mediachg(mii); 3829 if (error == 0) { 3830 ifm = &mii->mii_media; 3831 if (DC_IS_INTEL(sc)) 3832 dc_setcfg(sc, ifm->ifm_media); 3833 else if (DC_IS_DAVICOM(sc) && 3834 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) 3835 dc_setcfg(sc, ifm->ifm_media); 3836 } 3837 3838 return (error); 3839 } 3840 3841 /* 3842 * Report current media status. 3843 */ 3844 static void 3845 dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3846 { 3847 struct dc_softc *sc; 3848 struct mii_data *mii; 3849 struct ifmedia *ifm; 3850 3851 sc = ifp->if_softc; 3852 mii = device_get_softc(sc->dc_miibus); 3853 DC_LOCK(sc); 3854 mii_pollstat(mii); 3855 ifm = &mii->mii_media; 3856 if (DC_IS_DAVICOM(sc)) { 3857 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 3858 ifmr->ifm_active = ifm->ifm_media; 3859 ifmr->ifm_status = 0; 3860 DC_UNLOCK(sc); 3861 return; 3862 } 3863 } 3864 ifmr->ifm_active = mii->mii_media_active; 3865 ifmr->ifm_status = mii->mii_media_status; 3866 DC_UNLOCK(sc); 3867 } 3868 3869 static int 3870 dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3871 { 3872 struct dc_softc *sc = ifp->if_softc; 3873 struct ifreq *ifr = (struct ifreq *)data; 3874 struct mii_data *mii; 3875 int error = 0; 3876 3877 switch (command) { 3878 case SIOCSIFFLAGS: 3879 DC_LOCK(sc); 3880 if (ifp->if_flags & IFF_UP) { 3881 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) & 3882 (IFF_PROMISC | IFF_ALLMULTI); 3883 3884 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3885 if (need_setfilt) 3886 dc_setfilt(sc); 3887 } else { 3888 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3889 dc_init_locked(sc); 3890 } 3891 } else { 3892 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3893 dc_stop(sc); 3894 } 3895 sc->dc_if_flags = ifp->if_flags; 3896 DC_UNLOCK(sc); 3897 break; 3898 case SIOCADDMULTI: 3899 case SIOCDELMULTI: 3900 DC_LOCK(sc); 3901 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3902 dc_setfilt(sc); 3903 DC_UNLOCK(sc); 3904 break; 3905 case SIOCGIFMEDIA: 3906 case SIOCSIFMEDIA: 3907 mii = device_get_softc(sc->dc_miibus); 3908 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3909 break; 3910 case SIOCSIFCAP: 3911 #ifdef DEVICE_POLLING 3912 if (ifr->ifr_reqcap & IFCAP_POLLING && 3913 !(ifp->if_capenable & IFCAP_POLLING)) { 3914 error = ether_poll_register(dc_poll, ifp); 3915 if (error) 3916 return(error); 3917 DC_LOCK(sc); 3918 /* Disable interrupts */ 3919 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3920 ifp->if_capenable |= IFCAP_POLLING; 3921 DC_UNLOCK(sc); 3922 return (error); 3923 } 3924 if (!(ifr->ifr_reqcap & IFCAP_POLLING) && 3925 ifp->if_capenable & IFCAP_POLLING) { 3926 error = ether_poll_deregister(ifp); 3927 /* Enable interrupts. */ 3928 DC_LOCK(sc); 3929 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3930 ifp->if_capenable &= ~IFCAP_POLLING; 3931 DC_UNLOCK(sc); 3932 return (error); 3933 } 3934 #endif /* DEVICE_POLLING */ 3935 break; 3936 default: 3937 error = ether_ioctl(ifp, command, data); 3938 break; 3939 } 3940 3941 return (error); 3942 } 3943 3944 static void 3945 dc_watchdog(void *xsc) 3946 { 3947 struct dc_softc *sc = xsc; 3948 struct ifnet *ifp; 3949 3950 DC_LOCK_ASSERT(sc); 3951 3952 if (sc->dc_wdog_timer == 0 || --sc->dc_wdog_timer != 0) { 3953 callout_reset(&sc->dc_wdog_ch, hz, dc_watchdog, sc); 3954 return; 3955 } 3956 3957 ifp = sc->dc_ifp; 3958 ifp->if_oerrors++; 3959 device_printf(sc->dc_dev, "watchdog timeout\n"); 3960 3961 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3962 dc_init_locked(sc); 3963 3964 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3965 dc_start_locked(ifp); 3966 } 3967 3968 /* 3969 * Stop the adapter and free any mbufs allocated to the 3970 * RX and TX lists. 3971 */ 3972 static void 3973 dc_stop(struct dc_softc *sc) 3974 { 3975 struct ifnet *ifp; 3976 struct dc_list_data *ld; 3977 struct dc_chain_data *cd; 3978 int i; 3979 uint32_t ctl, netcfg; 3980 3981 DC_LOCK_ASSERT(sc); 3982 3983 ifp = sc->dc_ifp; 3984 ld = &sc->dc_ldata; 3985 cd = &sc->dc_cdata; 3986 3987 callout_stop(&sc->dc_stat_ch); 3988 callout_stop(&sc->dc_wdog_ch); 3989 sc->dc_wdog_timer = 0; 3990 sc->dc_link = 0; 3991 3992 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3993 3994 netcfg = CSR_READ_4(sc, DC_NETCFG); 3995 if (netcfg & (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)) 3996 CSR_WRITE_4(sc, DC_NETCFG, 3997 netcfg & ~(DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)); 3998 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3999 /* Wait the completion of TX/RX SM. */ 4000 if (netcfg & (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)) 4001 dc_netcfg_wait(sc); 4002 4003 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 4004 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 4005 4006 /* 4007 * Free data in the RX lists. 4008 */ 4009 for (i = 0; i < DC_RX_LIST_CNT; i++) { 4010 if (cd->dc_rx_chain[i] != NULL) { 4011 bus_dmamap_sync(sc->dc_rx_mtag, 4012 cd->dc_rx_map[i], BUS_DMASYNC_POSTREAD); 4013 bus_dmamap_unload(sc->dc_rx_mtag, 4014 cd->dc_rx_map[i]); 4015 m_freem(cd->dc_rx_chain[i]); 4016 cd->dc_rx_chain[i] = NULL; 4017 } 4018 } 4019 bzero(ld->dc_rx_list, DC_RX_LIST_SZ); 4020 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, 4021 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4022 4023 /* 4024 * Free the TX list buffers. 4025 */ 4026 for (i = 0; i < DC_TX_LIST_CNT; i++) { 4027 if (cd->dc_tx_chain[i] != NULL) { 4028 ctl = le32toh(ld->dc_tx_list[i].dc_ctl); 4029 if (ctl & DC_TXCTL_SETUP) { 4030 bus_dmamap_sync(sc->dc_stag, sc->dc_smap, 4031 BUS_DMASYNC_POSTWRITE); 4032 } else { 4033 bus_dmamap_sync(sc->dc_tx_mtag, 4034 cd->dc_tx_map[i], BUS_DMASYNC_POSTWRITE); 4035 bus_dmamap_unload(sc->dc_tx_mtag, 4036 cd->dc_tx_map[i]); 4037 m_freem(cd->dc_tx_chain[i]); 4038 } 4039 cd->dc_tx_chain[i] = NULL; 4040 } 4041 } 4042 bzero(ld->dc_tx_list, DC_TX_LIST_SZ); 4043 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, 4044 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4045 } 4046 4047 /* 4048 * Device suspend routine. Stop the interface and save some PCI 4049 * settings in case the BIOS doesn't restore them properly on 4050 * resume. 4051 */ 4052 static int 4053 dc_suspend(device_t dev) 4054 { 4055 struct dc_softc *sc; 4056 4057 sc = device_get_softc(dev); 4058 DC_LOCK(sc); 4059 dc_stop(sc); 4060 sc->suspended = 1; 4061 DC_UNLOCK(sc); 4062 4063 return (0); 4064 } 4065 4066 /* 4067 * Device resume routine. Restore some PCI settings in case the BIOS 4068 * doesn't, re-enable busmastering, and restart the interface if 4069 * appropriate. 4070 */ 4071 static int 4072 dc_resume(device_t dev) 4073 { 4074 struct dc_softc *sc; 4075 struct ifnet *ifp; 4076 4077 sc = device_get_softc(dev); 4078 ifp = sc->dc_ifp; 4079 4080 /* reinitialize interface if necessary */ 4081 DC_LOCK(sc); 4082 if (ifp->if_flags & IFF_UP) 4083 dc_init_locked(sc); 4084 4085 sc->suspended = 0; 4086 DC_UNLOCK(sc); 4087 4088 return (0); 4089 } 4090 4091 /* 4092 * Stop all chip I/O so that the kernel's probe routines don't 4093 * get confused by errant DMAs when rebooting. 4094 */ 4095 static int 4096 dc_shutdown(device_t dev) 4097 { 4098 struct dc_softc *sc; 4099 4100 sc = device_get_softc(dev); 4101 4102 DC_LOCK(sc); 4103 dc_stop(sc); 4104 DC_UNLOCK(sc); 4105 4106 return (0); 4107 } 4108 4109 static int 4110 dc_check_multiport(struct dc_softc *sc) 4111 { 4112 struct dc_softc *dsc; 4113 devclass_t dc; 4114 device_t child; 4115 uint8_t *eaddr; 4116 int unit; 4117 4118 dc = devclass_find("dc"); 4119 for (unit = 0; unit < devclass_get_maxunit(dc); unit++) { 4120 child = devclass_get_device(dc, unit); 4121 if (child == NULL) 4122 continue; 4123 if (child == sc->dc_dev) 4124 continue; 4125 if (device_get_parent(child) != device_get_parent(sc->dc_dev)) 4126 continue; 4127 if (unit > device_get_unit(sc->dc_dev)) 4128 continue; 4129 if (device_is_attached(child) == 0) 4130 continue; 4131 dsc = device_get_softc(child); 4132 device_printf(sc->dc_dev, 4133 "Using station address of %s as base\n", 4134 device_get_nameunit(child)); 4135 bcopy(dsc->dc_eaddr, sc->dc_eaddr, ETHER_ADDR_LEN); 4136 eaddr = (uint8_t *)sc->dc_eaddr; 4137 eaddr[5]++; 4138 /* Prepare SROM to parse again. */ 4139 if (DC_IS_INTEL(sc) && dsc->dc_srom != NULL && 4140 sc->dc_romwidth != 0) { 4141 free(sc->dc_srom, M_DEVBUF); 4142 sc->dc_romwidth = dsc->dc_romwidth; 4143 sc->dc_srom = malloc(DC_ROM_SIZE(sc->dc_romwidth), 4144 M_DEVBUF, M_NOWAIT); 4145 if (sc->dc_srom == NULL) { 4146 device_printf(sc->dc_dev, 4147 "Could not allocate SROM buffer\n"); 4148 return (ENOMEM); 4149 } 4150 bcopy(dsc->dc_srom, sc->dc_srom, 4151 DC_ROM_SIZE(sc->dc_romwidth)); 4152 } 4153 return (0); 4154 } 4155 return (ENOENT); 4156 } 4157