1 /*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 1997, 1998, 1999 5 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __FBSDID("$FreeBSD$"); 37 38 /* 39 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 40 * series chips and several workalikes including the following: 41 * 42 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 43 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 44 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 45 * ASIX Electronics AX88140A (www.asix.com.tw) 46 * ASIX Electronics AX88141 (www.asix.com.tw) 47 * ADMtek AL981 (www.admtek.com.tw) 48 * ADMtek AN983 (www.admtek.com.tw) 49 * ADMtek CardBus AN985 (www.admtek.com.tw) 50 * Netgear FA511 (www.netgear.com) Appears to be rebadged ADMTek CardBus AN985 51 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 52 * Accton EN1217 (www.accton.com) 53 * Xircom X3201 (www.xircom.com) 54 * Abocom FE2500 55 * Conexant LANfinity (www.conexant.com) 56 * 3Com OfficeConnect 10/100B 3CSOHO100B (www.3com.com) 57 * 58 * Datasheets for the 21143 are available at developer.intel.com. 59 * Datasheets for the clone parts can be found at their respective sites. 60 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 61 * The PNIC II is essentially a Macronix 98715A chip; the only difference 62 * worth noting is that its multicast hash table is only 128 bits wide 63 * instead of 512. 64 * 65 * Written by Bill Paul <wpaul@ee.columbia.edu> 66 * Electrical Engineering Department 67 * Columbia University, New York City 68 */ 69 /* 70 * The Intel 21143 is the successor to the DEC 21140. It is basically 71 * the same as the 21140 but with a few new features. The 21143 supports 72 * three kinds of media attachments: 73 * 74 * o MII port, for 10Mbps and 100Mbps support and NWAY 75 * autonegotiation provided by an external PHY. 76 * o SYM port, for symbol mode 100Mbps support. 77 * o 10baseT port. 78 * o AUI/BNC port. 79 * 80 * The 100Mbps SYM port and 10baseT port can be used together in 81 * combination with the internal NWAY support to create a 10/100 82 * autosensing configuration. 83 * 84 * Note that not all tulip workalikes are handled in this driver: we only 85 * deal with those which are relatively well behaved. The Winbond is 86 * handled separately due to its different register offsets and the 87 * special handling needed for its various bugs. The PNIC is handled 88 * here, but I'm not thrilled about it. 89 * 90 * All of the workalike chips use some form of MII transceiver support 91 * with the exception of the Macronix chips, which also have a SYM port. 92 * The ASIX AX88140A is also documented to have a SYM port, but all 93 * the cards I've seen use an MII transceiver, probably because the 94 * AX88140A doesn't support internal NWAY. 95 */ 96 97 #ifdef HAVE_KERNEL_OPTION_HEADERS 98 #include "opt_device_polling.h" 99 #endif 100 101 #include <sys/param.h> 102 #include <sys/endian.h> 103 #include <sys/systm.h> 104 #include <sys/sockio.h> 105 #include <sys/mbuf.h> 106 #include <sys/malloc.h> 107 #include <sys/kernel.h> 108 #include <sys/module.h> 109 #include <sys/socket.h> 110 111 #include <net/if.h> 112 #include <net/if_var.h> 113 #include <net/if_arp.h> 114 #include <net/ethernet.h> 115 #include <net/if_dl.h> 116 #include <net/if_media.h> 117 #include <net/if_types.h> 118 #include <net/if_vlan_var.h> 119 120 #include <net/bpf.h> 121 122 #include <machine/bus.h> 123 #include <machine/resource.h> 124 #include <sys/bus.h> 125 #include <sys/rman.h> 126 127 #include <dev/mii/mii.h> 128 #include <dev/mii/mii_bitbang.h> 129 #include <dev/mii/miivar.h> 130 131 #include <dev/pci/pcireg.h> 132 #include <dev/pci/pcivar.h> 133 134 #define DC_USEIOSPACE 135 136 #include <dev/dc/if_dcreg.h> 137 138 #ifdef __sparc64__ 139 #include <dev/ofw/openfirm.h> 140 #include <machine/ofw_machdep.h> 141 #endif 142 143 MODULE_DEPEND(dc, pci, 1, 1, 1); 144 MODULE_DEPEND(dc, ether, 1, 1, 1); 145 MODULE_DEPEND(dc, miibus, 1, 1, 1); 146 147 /* 148 * "device miibus" is required in kernel config. See GENERIC if you get 149 * errors here. 150 */ 151 #include "miibus_if.h" 152 153 /* 154 * Various supported device vendors/types and their names. 155 */ 156 static const struct dc_type dc_devs[] = { 157 { DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143), 0, 158 "Intel 21143 10/100BaseTX" }, 159 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009), 0, 160 "Davicom DM9009 10/100BaseTX" }, 161 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100), 0, 162 "Davicom DM9100 10/100BaseTX" }, 163 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), DC_REVISION_DM9102A, 164 "Davicom DM9102A 10/100BaseTX" }, 165 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), 0, 166 "Davicom DM9102 10/100BaseTX" }, 167 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981), 0, 168 "ADMtek AL981 10/100BaseTX" }, 169 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN983), 0, 170 "ADMtek AN983 10/100BaseTX" }, 171 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985), 0, 172 "ADMtek AN985 CardBus 10/100BaseTX or clone" }, 173 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511), 0, 174 "ADMtek ADM9511 10/100BaseTX" }, 175 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513), 0, 176 "ADMtek ADM9513 10/100BaseTX" }, 177 { DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), DC_REVISION_88141, 178 "ASIX AX88141 10/100BaseTX" }, 179 { DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), 0, 180 "ASIX AX88140A 10/100BaseTX" }, 181 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), DC_REVISION_98713A, 182 "Macronix 98713A 10/100BaseTX" }, 183 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), 0, 184 "Macronix 98713 10/100BaseTX" }, 185 { DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), DC_REVISION_98713A, 186 "Compex RL100-TX 10/100BaseTX" }, 187 { DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), 0, 188 "Compex RL100-TX 10/100BaseTX" }, 189 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98725, 190 "Macronix 98725 10/100BaseTX" }, 191 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98715AEC_C, 192 "Macronix 98715AEC-C 10/100BaseTX" }, 193 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), 0, 194 "Macronix 98715/98715A 10/100BaseTX" }, 195 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727), 0, 196 "Macronix 98727/98732 10/100BaseTX" }, 197 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115), 0, 198 "LC82C115 PNIC II 10/100BaseTX" }, 199 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), DC_REVISION_82C169, 200 "82c169 PNIC 10/100BaseTX" }, 201 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), 0, 202 "82c168 PNIC 10/100BaseTX" }, 203 { DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217), 0, 204 "Accton EN1217 10/100BaseTX" }, 205 { DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242), 0, 206 "Accton EN2242 MiniPCI 10/100BaseTX" }, 207 { DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201), 0, 208 "Xircom X3201 10/100BaseTX" }, 209 { DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD), 0, 210 "Neteasy DRP-32TXD Cardbus 10/100" }, 211 { DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500), 0, 212 "Abocom FE2500 10/100BaseTX" }, 213 { DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX), 0, 214 "Abocom FE2500MX 10/100BaseTX" }, 215 { DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112), 0, 216 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 217 { DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX), 0, 218 "Hawking CB102 CardBus 10/100" }, 219 { DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T), 0, 220 "PlaneX FNW-3602-T CardBus 10/100" }, 221 { DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB), 0, 222 "3Com OfficeConnect 10/100B" }, 223 { DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120), 0, 224 "Microsoft MN-120 CardBus 10/100" }, 225 { DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130), 0, 226 "Microsoft MN-130 10/100" }, 227 { DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08), 0, 228 "Linksys PCMPC200 CardBus 10/100" }, 229 { DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09), 0, 230 "Linksys PCMPC200 CardBus 10/100" }, 231 { DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5261), 0, 232 "ULi M5261 FastEthernet" }, 233 { DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5263), 0, 234 "ULi M5263 FastEthernet" }, 235 { 0, 0, NULL } 236 }; 237 238 static int dc_probe(device_t); 239 static int dc_attach(device_t); 240 static int dc_detach(device_t); 241 static int dc_suspend(device_t); 242 static int dc_resume(device_t); 243 static const struct dc_type *dc_devtype(device_t); 244 static void dc_discard_rxbuf(struct dc_softc *, int); 245 static int dc_newbuf(struct dc_softc *, int); 246 static int dc_encap(struct dc_softc *, struct mbuf **); 247 static void dc_pnic_rx_bug_war(struct dc_softc *, int); 248 static int dc_rx_resync(struct dc_softc *); 249 static int dc_rxeof(struct dc_softc *); 250 static void dc_txeof(struct dc_softc *); 251 static void dc_tick(void *); 252 static void dc_tx_underrun(struct dc_softc *); 253 static void dc_intr(void *); 254 static void dc_start(struct ifnet *); 255 static void dc_start_locked(struct ifnet *); 256 static int dc_ioctl(struct ifnet *, u_long, caddr_t); 257 static void dc_init(void *); 258 static void dc_init_locked(struct dc_softc *); 259 static void dc_stop(struct dc_softc *); 260 static void dc_watchdog(void *); 261 static int dc_shutdown(device_t); 262 static int dc_ifmedia_upd(struct ifnet *); 263 static int dc_ifmedia_upd_locked(struct dc_softc *); 264 static void dc_ifmedia_sts(struct ifnet *, struct ifmediareq *); 265 266 static int dc_dma_alloc(struct dc_softc *); 267 static void dc_dma_free(struct dc_softc *); 268 static void dc_dma_map_addr(void *, bus_dma_segment_t *, int, int); 269 270 static void dc_delay(struct dc_softc *); 271 static void dc_eeprom_idle(struct dc_softc *); 272 static void dc_eeprom_putbyte(struct dc_softc *, int); 273 static void dc_eeprom_getword(struct dc_softc *, int, uint16_t *); 274 static void dc_eeprom_getword_pnic(struct dc_softc *, int, uint16_t *); 275 static void dc_eeprom_getword_xircom(struct dc_softc *, int, uint16_t *); 276 static void dc_eeprom_width(struct dc_softc *); 277 static void dc_read_eeprom(struct dc_softc *, caddr_t, int, int, int); 278 279 static int dc_miibus_readreg(device_t, int, int); 280 static int dc_miibus_writereg(device_t, int, int, int); 281 static void dc_miibus_statchg(device_t); 282 static void dc_miibus_mediainit(device_t); 283 284 static void dc_setcfg(struct dc_softc *, int); 285 static void dc_netcfg_wait(struct dc_softc *); 286 static uint32_t dc_mchash_le(struct dc_softc *, const uint8_t *); 287 static uint32_t dc_mchash_be(const uint8_t *); 288 static void dc_setfilt_21143(struct dc_softc *); 289 static void dc_setfilt_asix(struct dc_softc *); 290 static void dc_setfilt_admtek(struct dc_softc *); 291 static void dc_setfilt_uli(struct dc_softc *); 292 static void dc_setfilt_xircom(struct dc_softc *); 293 294 static void dc_setfilt(struct dc_softc *); 295 296 static void dc_reset(struct dc_softc *); 297 static int dc_list_rx_init(struct dc_softc *); 298 static int dc_list_tx_init(struct dc_softc *); 299 300 static int dc_read_srom(struct dc_softc *, int); 301 static int dc_parse_21143_srom(struct dc_softc *); 302 static int dc_decode_leaf_sia(struct dc_softc *, struct dc_eblock_sia *); 303 static int dc_decode_leaf_mii(struct dc_softc *, struct dc_eblock_mii *); 304 static int dc_decode_leaf_sym(struct dc_softc *, struct dc_eblock_sym *); 305 static void dc_apply_fixup(struct dc_softc *, int); 306 static int dc_check_multiport(struct dc_softc *); 307 308 /* 309 * MII bit-bang glue 310 */ 311 static uint32_t dc_mii_bitbang_read(device_t); 312 static void dc_mii_bitbang_write(device_t, uint32_t); 313 314 static const struct mii_bitbang_ops dc_mii_bitbang_ops = { 315 dc_mii_bitbang_read, 316 dc_mii_bitbang_write, 317 { 318 DC_SIO_MII_DATAOUT, /* MII_BIT_MDO */ 319 DC_SIO_MII_DATAIN, /* MII_BIT_MDI */ 320 DC_SIO_MII_CLK, /* MII_BIT_MDC */ 321 0, /* MII_BIT_DIR_HOST_PHY */ 322 DC_SIO_MII_DIR, /* MII_BIT_DIR_PHY_HOST */ 323 } 324 }; 325 326 #ifdef DC_USEIOSPACE 327 #define DC_RES SYS_RES_IOPORT 328 #define DC_RID DC_PCI_CFBIO 329 #else 330 #define DC_RES SYS_RES_MEMORY 331 #define DC_RID DC_PCI_CFBMA 332 #endif 333 334 static device_method_t dc_methods[] = { 335 /* Device interface */ 336 DEVMETHOD(device_probe, dc_probe), 337 DEVMETHOD(device_attach, dc_attach), 338 DEVMETHOD(device_detach, dc_detach), 339 DEVMETHOD(device_suspend, dc_suspend), 340 DEVMETHOD(device_resume, dc_resume), 341 DEVMETHOD(device_shutdown, dc_shutdown), 342 343 /* MII interface */ 344 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 345 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 346 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 347 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 348 349 DEVMETHOD_END 350 }; 351 352 static driver_t dc_driver = { 353 "dc", 354 dc_methods, 355 sizeof(struct dc_softc) 356 }; 357 358 static devclass_t dc_devclass; 359 360 DRIVER_MODULE_ORDERED(dc, pci, dc_driver, dc_devclass, NULL, NULL, 361 SI_ORDER_ANY); 362 MODULE_PNP_INFO("W32:vendor/device;U8:revision;D:#", pci, dc, dc_devs, 363 nitems(dc_devs) - 1); 364 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, NULL, NULL); 365 366 #define DC_SETBIT(sc, reg, x) \ 367 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 368 369 #define DC_CLRBIT(sc, reg, x) \ 370 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 371 372 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 373 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 374 375 static void 376 dc_delay(struct dc_softc *sc) 377 { 378 int idx; 379 380 for (idx = (300 / 33) + 1; idx > 0; idx--) 381 CSR_READ_4(sc, DC_BUSCTL); 382 } 383 384 static void 385 dc_eeprom_width(struct dc_softc *sc) 386 { 387 int i; 388 389 /* Force EEPROM to idle state. */ 390 dc_eeprom_idle(sc); 391 392 /* Enter EEPROM access mode. */ 393 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 394 dc_delay(sc); 395 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 396 dc_delay(sc); 397 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 398 dc_delay(sc); 399 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 400 dc_delay(sc); 401 402 for (i = 3; i--;) { 403 if (6 & (1 << i)) 404 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 405 else 406 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 407 dc_delay(sc); 408 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 409 dc_delay(sc); 410 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 411 dc_delay(sc); 412 } 413 414 for (i = 1; i <= 12; i++) { 415 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 416 dc_delay(sc); 417 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { 418 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 419 dc_delay(sc); 420 break; 421 } 422 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 423 dc_delay(sc); 424 } 425 426 /* Turn off EEPROM access mode. */ 427 dc_eeprom_idle(sc); 428 429 if (i < 4 || i > 12) 430 sc->dc_romwidth = 6; 431 else 432 sc->dc_romwidth = i; 433 434 /* Enter EEPROM access mode. */ 435 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 436 dc_delay(sc); 437 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 438 dc_delay(sc); 439 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 440 dc_delay(sc); 441 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 442 dc_delay(sc); 443 444 /* Turn off EEPROM access mode. */ 445 dc_eeprom_idle(sc); 446 } 447 448 static void 449 dc_eeprom_idle(struct dc_softc *sc) 450 { 451 int i; 452 453 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 454 dc_delay(sc); 455 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 456 dc_delay(sc); 457 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 458 dc_delay(sc); 459 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 460 dc_delay(sc); 461 462 for (i = 0; i < 25; i++) { 463 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 464 dc_delay(sc); 465 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 466 dc_delay(sc); 467 } 468 469 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 470 dc_delay(sc); 471 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 472 dc_delay(sc); 473 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 474 } 475 476 /* 477 * Send a read command and address to the EEPROM, check for ACK. 478 */ 479 static void 480 dc_eeprom_putbyte(struct dc_softc *sc, int addr) 481 { 482 int d, i; 483 484 d = DC_EECMD_READ >> 6; 485 for (i = 3; i--; ) { 486 if (d & (1 << i)) 487 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 488 else 489 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 490 dc_delay(sc); 491 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 492 dc_delay(sc); 493 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 494 dc_delay(sc); 495 } 496 497 /* 498 * Feed in each bit and strobe the clock. 499 */ 500 for (i = sc->dc_romwidth; i--;) { 501 if (addr & (1 << i)) { 502 SIO_SET(DC_SIO_EE_DATAIN); 503 } else { 504 SIO_CLR(DC_SIO_EE_DATAIN); 505 } 506 dc_delay(sc); 507 SIO_SET(DC_SIO_EE_CLK); 508 dc_delay(sc); 509 SIO_CLR(DC_SIO_EE_CLK); 510 dc_delay(sc); 511 } 512 } 513 514 /* 515 * Read a word of data stored in the EEPROM at address 'addr.' 516 * The PNIC 82c168/82c169 has its own non-standard way to read 517 * the EEPROM. 518 */ 519 static void 520 dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, uint16_t *dest) 521 { 522 int i; 523 uint32_t r; 524 525 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr); 526 527 for (i = 0; i < DC_TIMEOUT; i++) { 528 DELAY(1); 529 r = CSR_READ_4(sc, DC_SIO); 530 if (!(r & DC_PN_SIOCTL_BUSY)) { 531 *dest = (uint16_t)(r & 0xFFFF); 532 return; 533 } 534 } 535 } 536 537 /* 538 * Read a word of data stored in the EEPROM at address 'addr.' 539 * The Xircom X3201 has its own non-standard way to read 540 * the EEPROM, too. 541 */ 542 static void 543 dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, uint16_t *dest) 544 { 545 546 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 547 548 addr *= 2; 549 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 550 *dest = (uint16_t)CSR_READ_4(sc, DC_SIO) & 0xff; 551 addr += 1; 552 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 553 *dest |= ((uint16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8; 554 555 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 556 } 557 558 /* 559 * Read a word of data stored in the EEPROM at address 'addr.' 560 */ 561 static void 562 dc_eeprom_getword(struct dc_softc *sc, int addr, uint16_t *dest) 563 { 564 int i; 565 uint16_t word = 0; 566 567 /* Force EEPROM to idle state. */ 568 dc_eeprom_idle(sc); 569 570 /* Enter EEPROM access mode. */ 571 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 572 dc_delay(sc); 573 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 574 dc_delay(sc); 575 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 576 dc_delay(sc); 577 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 578 dc_delay(sc); 579 580 /* 581 * Send address of word we want to read. 582 */ 583 dc_eeprom_putbyte(sc, addr); 584 585 /* 586 * Start reading bits from EEPROM. 587 */ 588 for (i = 0x8000; i; i >>= 1) { 589 SIO_SET(DC_SIO_EE_CLK); 590 dc_delay(sc); 591 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 592 word |= i; 593 dc_delay(sc); 594 SIO_CLR(DC_SIO_EE_CLK); 595 dc_delay(sc); 596 } 597 598 /* Turn off EEPROM access mode. */ 599 dc_eeprom_idle(sc); 600 601 *dest = word; 602 } 603 604 /* 605 * Read a sequence of words from the EEPROM. 606 */ 607 static void 608 dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int be) 609 { 610 int i; 611 uint16_t word = 0, *ptr; 612 613 for (i = 0; i < cnt; i++) { 614 if (DC_IS_PNIC(sc)) 615 dc_eeprom_getword_pnic(sc, off + i, &word); 616 else if (DC_IS_XIRCOM(sc)) 617 dc_eeprom_getword_xircom(sc, off + i, &word); 618 else 619 dc_eeprom_getword(sc, off + i, &word); 620 ptr = (uint16_t *)(dest + (i * 2)); 621 if (be) 622 *ptr = be16toh(word); 623 else 624 *ptr = le16toh(word); 625 } 626 } 627 628 /* 629 * Write the MII serial port for the MII bit-bang module. 630 */ 631 static void 632 dc_mii_bitbang_write(device_t dev, uint32_t val) 633 { 634 struct dc_softc *sc; 635 636 sc = device_get_softc(dev); 637 638 CSR_WRITE_4(sc, DC_SIO, val); 639 CSR_BARRIER_4(sc, DC_SIO, 640 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 641 } 642 643 /* 644 * Read the MII serial port for the MII bit-bang module. 645 */ 646 static uint32_t 647 dc_mii_bitbang_read(device_t dev) 648 { 649 struct dc_softc *sc; 650 uint32_t val; 651 652 sc = device_get_softc(dev); 653 654 val = CSR_READ_4(sc, DC_SIO); 655 CSR_BARRIER_4(sc, DC_SIO, 656 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 657 658 return (val); 659 } 660 661 static int 662 dc_miibus_readreg(device_t dev, int phy, int reg) 663 { 664 struct dc_softc *sc; 665 int i, rval, phy_reg = 0; 666 667 sc = device_get_softc(dev); 668 669 if (sc->dc_pmode != DC_PMODE_MII) { 670 if (phy == (MII_NPHY - 1)) { 671 switch (reg) { 672 case MII_BMSR: 673 /* 674 * Fake something to make the probe 675 * code think there's a PHY here. 676 */ 677 return (BMSR_MEDIAMASK); 678 case MII_PHYIDR1: 679 if (DC_IS_PNIC(sc)) 680 return (DC_VENDORID_LO); 681 return (DC_VENDORID_DEC); 682 case MII_PHYIDR2: 683 if (DC_IS_PNIC(sc)) 684 return (DC_DEVICEID_82C168); 685 return (DC_DEVICEID_21143); 686 default: 687 return (0); 688 } 689 } else 690 return (0); 691 } 692 693 if (DC_IS_PNIC(sc)) { 694 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 695 (phy << 23) | (reg << 18)); 696 for (i = 0; i < DC_TIMEOUT; i++) { 697 DELAY(1); 698 rval = CSR_READ_4(sc, DC_PN_MII); 699 if (!(rval & DC_PN_MII_BUSY)) { 700 rval &= 0xFFFF; 701 return (rval == 0xFFFF ? 0 : rval); 702 } 703 } 704 return (0); 705 } 706 707 if (sc->dc_type == DC_TYPE_ULI_M5263) { 708 CSR_WRITE_4(sc, DC_ROM, 709 ((phy << DC_ULI_PHY_ADDR_SHIFT) & DC_ULI_PHY_ADDR_MASK) | 710 ((reg << DC_ULI_PHY_REG_SHIFT) & DC_ULI_PHY_REG_MASK) | 711 DC_ULI_PHY_OP_READ); 712 for (i = 0; i < DC_TIMEOUT; i++) { 713 DELAY(1); 714 rval = CSR_READ_4(sc, DC_ROM); 715 if ((rval & DC_ULI_PHY_OP_DONE) != 0) { 716 return (rval & DC_ULI_PHY_DATA_MASK); 717 } 718 } 719 if (i == DC_TIMEOUT) 720 device_printf(dev, "phy read timed out\n"); 721 return (0); 722 } 723 724 if (DC_IS_COMET(sc)) { 725 switch (reg) { 726 case MII_BMCR: 727 phy_reg = DC_AL_BMCR; 728 break; 729 case MII_BMSR: 730 phy_reg = DC_AL_BMSR; 731 break; 732 case MII_PHYIDR1: 733 phy_reg = DC_AL_VENID; 734 break; 735 case MII_PHYIDR2: 736 phy_reg = DC_AL_DEVID; 737 break; 738 case MII_ANAR: 739 phy_reg = DC_AL_ANAR; 740 break; 741 case MII_ANLPAR: 742 phy_reg = DC_AL_LPAR; 743 break; 744 case MII_ANER: 745 phy_reg = DC_AL_ANER; 746 break; 747 default: 748 device_printf(dev, "phy_read: bad phy register %x\n", 749 reg); 750 return (0); 751 } 752 753 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 754 if (rval == 0xFFFF) 755 return (0); 756 return (rval); 757 } 758 759 if (sc->dc_type == DC_TYPE_98713) { 760 phy_reg = CSR_READ_4(sc, DC_NETCFG); 761 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 762 } 763 rval = mii_bitbang_readreg(dev, &dc_mii_bitbang_ops, phy, reg); 764 if (sc->dc_type == DC_TYPE_98713) 765 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 766 767 return (rval); 768 } 769 770 static int 771 dc_miibus_writereg(device_t dev, int phy, int reg, int data) 772 { 773 struct dc_softc *sc; 774 int i, phy_reg = 0; 775 776 sc = device_get_softc(dev); 777 778 if (DC_IS_PNIC(sc)) { 779 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 780 (phy << 23) | (reg << 10) | data); 781 for (i = 0; i < DC_TIMEOUT; i++) { 782 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 783 break; 784 } 785 return (0); 786 } 787 788 if (sc->dc_type == DC_TYPE_ULI_M5263) { 789 CSR_WRITE_4(sc, DC_ROM, 790 ((phy << DC_ULI_PHY_ADDR_SHIFT) & DC_ULI_PHY_ADDR_MASK) | 791 ((reg << DC_ULI_PHY_REG_SHIFT) & DC_ULI_PHY_REG_MASK) | 792 ((data << DC_ULI_PHY_DATA_SHIFT) & DC_ULI_PHY_DATA_MASK) | 793 DC_ULI_PHY_OP_WRITE); 794 DELAY(1); 795 return (0); 796 } 797 798 if (DC_IS_COMET(sc)) { 799 switch (reg) { 800 case MII_BMCR: 801 phy_reg = DC_AL_BMCR; 802 break; 803 case MII_BMSR: 804 phy_reg = DC_AL_BMSR; 805 break; 806 case MII_PHYIDR1: 807 phy_reg = DC_AL_VENID; 808 break; 809 case MII_PHYIDR2: 810 phy_reg = DC_AL_DEVID; 811 break; 812 case MII_ANAR: 813 phy_reg = DC_AL_ANAR; 814 break; 815 case MII_ANLPAR: 816 phy_reg = DC_AL_LPAR; 817 break; 818 case MII_ANER: 819 phy_reg = DC_AL_ANER; 820 break; 821 default: 822 device_printf(dev, "phy_write: bad phy register %x\n", 823 reg); 824 return (0); 825 break; 826 } 827 828 CSR_WRITE_4(sc, phy_reg, data); 829 return (0); 830 } 831 832 if (sc->dc_type == DC_TYPE_98713) { 833 phy_reg = CSR_READ_4(sc, DC_NETCFG); 834 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 835 } 836 mii_bitbang_writereg(dev, &dc_mii_bitbang_ops, phy, reg, data); 837 if (sc->dc_type == DC_TYPE_98713) 838 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 839 840 return (0); 841 } 842 843 static void 844 dc_miibus_statchg(device_t dev) 845 { 846 struct dc_softc *sc; 847 struct ifnet *ifp; 848 struct mii_data *mii; 849 struct ifmedia *ifm; 850 851 sc = device_get_softc(dev); 852 853 mii = device_get_softc(sc->dc_miibus); 854 ifp = sc->dc_ifp; 855 if (mii == NULL || ifp == NULL || 856 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 857 return; 858 859 ifm = &mii->mii_media; 860 if (DC_IS_DAVICOM(sc) && IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 861 dc_setcfg(sc, ifm->ifm_media); 862 return; 863 } else if (!DC_IS_ADMTEK(sc)) 864 dc_setcfg(sc, mii->mii_media_active); 865 866 sc->dc_link = 0; 867 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 868 (IFM_ACTIVE | IFM_AVALID)) { 869 switch (IFM_SUBTYPE(mii->mii_media_active)) { 870 case IFM_10_T: 871 case IFM_100_TX: 872 sc->dc_link = 1; 873 break; 874 } 875 } 876 } 877 878 /* 879 * Special support for DM9102A cards with HomePNA PHYs. Note: 880 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 881 * to be impossible to talk to the management interface of the DM9801 882 * PHY (its MDIO pin is not connected to anything). Consequently, 883 * the driver has to just 'know' about the additional mode and deal 884 * with it itself. *sigh* 885 */ 886 static void 887 dc_miibus_mediainit(device_t dev) 888 { 889 struct dc_softc *sc; 890 struct mii_data *mii; 891 struct ifmedia *ifm; 892 int rev; 893 894 rev = pci_get_revid(dev); 895 896 sc = device_get_softc(dev); 897 mii = device_get_softc(sc->dc_miibus); 898 ifm = &mii->mii_media; 899 900 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 901 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL); 902 } 903 904 #define DC_BITS_512 9 905 #define DC_BITS_128 7 906 #define DC_BITS_64 6 907 908 static uint32_t 909 dc_mchash_le(struct dc_softc *sc, const uint8_t *addr) 910 { 911 uint32_t crc; 912 913 /* Compute CRC for the address value. */ 914 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 915 916 /* 917 * The hash table on the PNIC II and the MX98715AEC-C/D/E 918 * chips is only 128 bits wide. 919 */ 920 if (sc->dc_flags & DC_128BIT_HASH) 921 return (crc & ((1 << DC_BITS_128) - 1)); 922 923 /* The hash table on the MX98715BEC is only 64 bits wide. */ 924 if (sc->dc_flags & DC_64BIT_HASH) 925 return (crc & ((1 << DC_BITS_64) - 1)); 926 927 /* Xircom's hash filtering table is different (read: weird) */ 928 /* Xircom uses the LEAST significant bits */ 929 if (DC_IS_XIRCOM(sc)) { 930 if ((crc & 0x180) == 0x180) 931 return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4)); 932 else 933 return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 + 934 (12 << 4)); 935 } 936 937 return (crc & ((1 << DC_BITS_512) - 1)); 938 } 939 940 /* 941 * Calculate CRC of a multicast group address, return the lower 6 bits. 942 */ 943 static uint32_t 944 dc_mchash_be(const uint8_t *addr) 945 { 946 uint32_t crc; 947 948 /* Compute CRC for the address value. */ 949 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 950 951 /* Return the filter bit position. */ 952 return ((crc >> 26) & 0x0000003F); 953 } 954 955 /* 956 * 21143-style RX filter setup routine. Filter programming is done by 957 * downloading a special setup frame into the TX engine. 21143, Macronix, 958 * PNIC, PNIC II and Davicom chips are programmed this way. 959 * 960 * We always program the chip using 'hash perfect' mode, i.e. one perfect 961 * address (our node address) and a 512-bit hash filter for multicast 962 * frames. We also sneak the broadcast address into the hash filter since 963 * we need that too. 964 */ 965 static u_int 966 dc_hash_maddr_21143(void *arg, struct sockaddr_dl *sdl, u_int cnt) 967 { 968 struct dc_softc *sc = arg; 969 uint32_t h; 970 971 h = dc_mchash_le(sc, LLADDR(sdl)); 972 sc->dc_cdata.dc_sbuf[h >> 4] |= htole32(1 << (h & 0xF)); 973 974 return (1); 975 } 976 977 static void 978 dc_setfilt_21143(struct dc_softc *sc) 979 { 980 uint16_t eaddr[(ETHER_ADDR_LEN+1)/2]; 981 struct dc_desc *sframe; 982 uint32_t h, *sp; 983 struct ifnet *ifp; 984 int i; 985 986 ifp = sc->dc_ifp; 987 988 i = sc->dc_cdata.dc_tx_prod; 989 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 990 sc->dc_cdata.dc_tx_cnt++; 991 sframe = &sc->dc_ldata.dc_tx_list[i]; 992 sp = sc->dc_cdata.dc_sbuf; 993 bzero(sp, DC_SFRAME_LEN); 994 995 sframe->dc_data = htole32(DC_ADDR_LO(sc->dc_saddr)); 996 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 997 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 998 999 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1000 1001 /* If we want promiscuous mode, set the allframes bit. */ 1002 if (ifp->if_flags & IFF_PROMISC) 1003 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1004 else 1005 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1006 1007 if (ifp->if_flags & IFF_ALLMULTI) 1008 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1009 else 1010 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1011 1012 if_foreach_llmaddr(ifp, dc_hash_maddr_21143, sp); 1013 1014 if (ifp->if_flags & IFF_BROADCAST) { 1015 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1016 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1017 } 1018 1019 /* Set our MAC address. */ 1020 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1021 sp[39] = DC_SP_MAC(eaddr[0]); 1022 sp[40] = DC_SP_MAC(eaddr[1]); 1023 sp[41] = DC_SP_MAC(eaddr[2]); 1024 1025 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1026 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, BUS_DMASYNC_PREREAD | 1027 BUS_DMASYNC_PREWRITE); 1028 bus_dmamap_sync(sc->dc_stag, sc->dc_smap, BUS_DMASYNC_PREWRITE); 1029 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1030 1031 /* 1032 * The PNIC takes an exceedingly long time to process its 1033 * setup frame; wait 10ms after posting the setup frame 1034 * before proceeding, just so it has time to swallow its 1035 * medicine. 1036 */ 1037 DELAY(10000); 1038 1039 sc->dc_wdog_timer = 5; 1040 } 1041 1042 static u_int 1043 dc_hash_maddr_admtek_be(void *arg, struct sockaddr_dl *sdl, u_int cnt) 1044 { 1045 uint32_t *hashes = arg; 1046 int h = 0; 1047 1048 h = dc_mchash_be(LLADDR(sdl)); 1049 if (h < 32) 1050 hashes[0] |= (1 << h); 1051 else 1052 hashes[1] |= (1 << (h - 32)); 1053 1054 return (1); 1055 } 1056 1057 struct dc_hash_maddr_admtek_le_ctx { 1058 struct dc_softc *sc; 1059 uint32_t hashes[2]; 1060 }; 1061 1062 static u_int 1063 dc_hash_maddr_admtek_le(void *arg, struct sockaddr_dl *sdl, u_int cnt) 1064 { 1065 struct dc_hash_maddr_admtek_le_ctx *ctx = arg; 1066 int h = 0; 1067 1068 h = dc_mchash_le(ctx->sc, LLADDR(sdl)); 1069 if (h < 32) 1070 ctx->hashes[0] |= (1 << h); 1071 else 1072 ctx->hashes[1] |= (1 << (h - 32)); 1073 1074 return (1); 1075 } 1076 1077 static void 1078 dc_setfilt_admtek(struct dc_softc *sc) 1079 { 1080 uint8_t eaddr[ETHER_ADDR_LEN]; 1081 struct ifnet *ifp; 1082 struct dc_hash_maddr_admtek_le_ctx ctx = { sc, { 0, 0 }}; 1083 1084 ifp = sc->dc_ifp; 1085 1086 /* Init our MAC address. */ 1087 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1088 CSR_WRITE_4(sc, DC_AL_PAR0, eaddr[3] << 24 | eaddr[2] << 16 | 1089 eaddr[1] << 8 | eaddr[0]); 1090 CSR_WRITE_4(sc, DC_AL_PAR1, eaddr[5] << 8 | eaddr[4]); 1091 1092 /* If we want promiscuous mode, set the allframes bit. */ 1093 if (ifp->if_flags & IFF_PROMISC) 1094 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1095 else 1096 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1097 1098 if (ifp->if_flags & IFF_ALLMULTI) 1099 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1100 else 1101 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1102 1103 /* First, zot all the existing hash bits. */ 1104 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1105 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1106 1107 /* 1108 * If we're already in promisc or allmulti mode, we 1109 * don't have to bother programming the multicast filter. 1110 */ 1111 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1112 return; 1113 1114 /* Now program new ones. */ 1115 if (DC_IS_CENTAUR(sc)) 1116 if_foreach_llmaddr(ifp, dc_hash_maddr_admtek_le, &ctx); 1117 else 1118 if_foreach_llmaddr(ifp, dc_hash_maddr_admtek_be, &ctx.hashes); 1119 1120 CSR_WRITE_4(sc, DC_AL_MAR0, ctx.hashes[0]); 1121 CSR_WRITE_4(sc, DC_AL_MAR1, ctx.hashes[1]); 1122 } 1123 1124 static void 1125 dc_setfilt_asix(struct dc_softc *sc) 1126 { 1127 uint32_t eaddr[(ETHER_ADDR_LEN+3)/4]; 1128 struct ifnet *ifp; 1129 uint32_t hashes[2] = { 0, 0 }; 1130 1131 ifp = sc->dc_ifp; 1132 1133 /* Init our MAC address. */ 1134 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1135 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1136 CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[0]); 1137 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1138 CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[1]); 1139 1140 /* If we want promiscuous mode, set the allframes bit. */ 1141 if (ifp->if_flags & IFF_PROMISC) 1142 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1143 else 1144 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1145 1146 if (ifp->if_flags & IFF_ALLMULTI) 1147 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1148 else 1149 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1150 1151 /* 1152 * The ASIX chip has a special bit to enable reception 1153 * of broadcast frames. 1154 */ 1155 if (ifp->if_flags & IFF_BROADCAST) 1156 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1157 else 1158 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1159 1160 /* first, zot all the existing hash bits */ 1161 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1162 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1163 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1164 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1165 1166 /* 1167 * If we're already in promisc or allmulti mode, we 1168 * don't have to bother programming the multicast filter. 1169 */ 1170 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1171 return; 1172 1173 /* now program new ones */ 1174 if_foreach_llmaddr(ifp, dc_hash_maddr_admtek_be, hashes); 1175 1176 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1177 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1178 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1179 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1180 } 1181 1182 static u_int 1183 dc_hash_maddr_uli(void *arg, struct sockaddr_dl *sdl, u_int mcnt) 1184 { 1185 uint32_t **sp = arg; 1186 uint8_t *ma; 1187 1188 if (mcnt == DC_ULI_FILTER_NPERF) 1189 return (0); 1190 ma = LLADDR(sdl); 1191 *(*sp)++ = DC_SP_MAC(ma[1] << 8 | ma[0]); 1192 *(*sp)++ = DC_SP_MAC(ma[3] << 8 | ma[2]); 1193 *(*sp)++ = DC_SP_MAC(ma[5] << 8 | ma[4]); 1194 1195 return (1); 1196 } 1197 1198 static void 1199 dc_setfilt_uli(struct dc_softc *sc) 1200 { 1201 uint8_t eaddr[ETHER_ADDR_LEN]; 1202 struct ifnet *ifp; 1203 struct dc_desc *sframe; 1204 uint32_t filter, *sp; 1205 int i, mcnt; 1206 1207 ifp = sc->dc_ifp; 1208 1209 i = sc->dc_cdata.dc_tx_prod; 1210 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1211 sc->dc_cdata.dc_tx_cnt++; 1212 sframe = &sc->dc_ldata.dc_tx_list[i]; 1213 sp = sc->dc_cdata.dc_sbuf; 1214 bzero(sp, DC_SFRAME_LEN); 1215 1216 sframe->dc_data = htole32(DC_ADDR_LO(sc->dc_saddr)); 1217 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1218 DC_TXCTL_TLINK | DC_FILTER_PERFECT | DC_TXCTL_FINT); 1219 1220 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1221 1222 /* Set station address. */ 1223 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1224 *sp++ = DC_SP_MAC(eaddr[1] << 8 | eaddr[0]); 1225 *sp++ = DC_SP_MAC(eaddr[3] << 8 | eaddr[2]); 1226 *sp++ = DC_SP_MAC(eaddr[5] << 8 | eaddr[4]); 1227 1228 /* Set broadcast address. */ 1229 *sp++ = DC_SP_MAC(0xFFFF); 1230 *sp++ = DC_SP_MAC(0xFFFF); 1231 *sp++ = DC_SP_MAC(0xFFFF); 1232 1233 /* Extract current filter configuration. */ 1234 filter = CSR_READ_4(sc, DC_NETCFG); 1235 filter &= ~(DC_NETCFG_RX_PROMISC | DC_NETCFG_RX_ALLMULTI); 1236 1237 /* Now build perfect filters. */ 1238 mcnt = if_foreach_llmaddr(ifp, dc_hash_maddr_uli, &sp); 1239 1240 if (mcnt == DC_ULI_FILTER_NPERF) 1241 filter |= DC_NETCFG_RX_ALLMULTI; 1242 else 1243 for (; mcnt < DC_ULI_FILTER_NPERF; mcnt++) { 1244 *sp++ = DC_SP_MAC(0xFFFF); 1245 *sp++ = DC_SP_MAC(0xFFFF); 1246 *sp++ = DC_SP_MAC(0xFFFF); 1247 } 1248 1249 if (filter & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) 1250 CSR_WRITE_4(sc, DC_NETCFG, 1251 filter & ~(DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1252 if (ifp->if_flags & IFF_PROMISC) 1253 filter |= DC_NETCFG_RX_PROMISC | DC_NETCFG_RX_ALLMULTI; 1254 if (ifp->if_flags & IFF_ALLMULTI) 1255 filter |= DC_NETCFG_RX_ALLMULTI; 1256 CSR_WRITE_4(sc, DC_NETCFG, 1257 filter & ~(DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1258 if (filter & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) 1259 CSR_WRITE_4(sc, DC_NETCFG, filter); 1260 1261 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1262 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, BUS_DMASYNC_PREREAD | 1263 BUS_DMASYNC_PREWRITE); 1264 bus_dmamap_sync(sc->dc_stag, sc->dc_smap, BUS_DMASYNC_PREWRITE); 1265 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1266 1267 /* 1268 * Wait some time... 1269 */ 1270 DELAY(1000); 1271 1272 sc->dc_wdog_timer = 5; 1273 } 1274 1275 static u_int 1276 dc_hash_maddr_xircom(void *arg, struct sockaddr_dl *sdl, u_int cnt) 1277 { 1278 struct dc_softc *sc = arg; 1279 uint32_t h; 1280 1281 h = dc_mchash_le(sc, LLADDR(sdl)); 1282 sc->dc_cdata.dc_sbuf[h >> 4] |= htole32(1 << (h & 0xF)); 1283 return (1); 1284 } 1285 1286 static void 1287 dc_setfilt_xircom(struct dc_softc *sc) 1288 { 1289 uint16_t eaddr[(ETHER_ADDR_LEN+1)/2]; 1290 struct ifnet *ifp; 1291 struct dc_desc *sframe; 1292 uint32_t h, *sp; 1293 int i; 1294 1295 ifp = sc->dc_ifp; 1296 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1297 1298 i = sc->dc_cdata.dc_tx_prod; 1299 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1300 sc->dc_cdata.dc_tx_cnt++; 1301 sframe = &sc->dc_ldata.dc_tx_list[i]; 1302 sp = sc->dc_cdata.dc_sbuf; 1303 bzero(sp, DC_SFRAME_LEN); 1304 1305 sframe->dc_data = htole32(DC_ADDR_LO(sc->dc_saddr)); 1306 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1307 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1308 1309 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1310 1311 /* If we want promiscuous mode, set the allframes bit. */ 1312 if (ifp->if_flags & IFF_PROMISC) 1313 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1314 else 1315 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1316 1317 if (ifp->if_flags & IFF_ALLMULTI) 1318 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1319 else 1320 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1321 1322 if_foreach_llmaddr(ifp, dc_hash_maddr_xircom, &sp); 1323 1324 if (ifp->if_flags & IFF_BROADCAST) { 1325 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1326 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1327 } 1328 1329 /* Set our MAC address. */ 1330 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1331 sp[0] = DC_SP_MAC(eaddr[0]); 1332 sp[1] = DC_SP_MAC(eaddr[1]); 1333 sp[2] = DC_SP_MAC(eaddr[2]); 1334 1335 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1336 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1337 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1338 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, BUS_DMASYNC_PREREAD | 1339 BUS_DMASYNC_PREWRITE); 1340 bus_dmamap_sync(sc->dc_stag, sc->dc_smap, BUS_DMASYNC_PREWRITE); 1341 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1342 1343 /* 1344 * Wait some time... 1345 */ 1346 DELAY(1000); 1347 1348 sc->dc_wdog_timer = 5; 1349 } 1350 1351 static void 1352 dc_setfilt(struct dc_softc *sc) 1353 { 1354 1355 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1356 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1357 dc_setfilt_21143(sc); 1358 1359 if (DC_IS_ASIX(sc)) 1360 dc_setfilt_asix(sc); 1361 1362 if (DC_IS_ADMTEK(sc)) 1363 dc_setfilt_admtek(sc); 1364 1365 if (DC_IS_ULI(sc)) 1366 dc_setfilt_uli(sc); 1367 1368 if (DC_IS_XIRCOM(sc)) 1369 dc_setfilt_xircom(sc); 1370 } 1371 1372 static void 1373 dc_netcfg_wait(struct dc_softc *sc) 1374 { 1375 uint32_t isr; 1376 int i; 1377 1378 for (i = 0; i < DC_TIMEOUT; i++) { 1379 isr = CSR_READ_4(sc, DC_ISR); 1380 if (isr & DC_ISR_TX_IDLE && 1381 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1382 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT)) 1383 break; 1384 DELAY(10); 1385 } 1386 if (i == DC_TIMEOUT && bus_child_present(sc->dc_dev)) { 1387 if (!(isr & DC_ISR_TX_IDLE) && !DC_IS_ASIX(sc)) 1388 device_printf(sc->dc_dev, 1389 "%s: failed to force tx to idle state\n", __func__); 1390 if (!((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1391 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT) && 1392 !DC_HAS_BROKEN_RXSTATE(sc)) 1393 device_printf(sc->dc_dev, 1394 "%s: failed to force rx to idle state\n", __func__); 1395 } 1396 } 1397 1398 /* 1399 * In order to fiddle with the 'full-duplex' and '100Mbps' bits in 1400 * the netconfig register, we first have to put the transmit and/or 1401 * receive logic in the idle state. 1402 */ 1403 static void 1404 dc_setcfg(struct dc_softc *sc, int media) 1405 { 1406 int restart = 0, watchdogreg; 1407 1408 if (IFM_SUBTYPE(media) == IFM_NONE) 1409 return; 1410 1411 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) { 1412 restart = 1; 1413 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1414 dc_netcfg_wait(sc); 1415 } 1416 1417 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1418 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1419 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1420 if (sc->dc_pmode == DC_PMODE_MII) { 1421 if (DC_IS_INTEL(sc)) { 1422 /* There's a write enable bit here that reads as 1. */ 1423 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1424 watchdogreg &= ~DC_WDOG_CTLWREN; 1425 watchdogreg |= DC_WDOG_JABBERDIS; 1426 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1427 } else { 1428 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1429 } 1430 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1431 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1432 if (sc->dc_type == DC_TYPE_98713) 1433 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1434 DC_NETCFG_SCRAMBLER)); 1435 if (!DC_IS_DAVICOM(sc)) 1436 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1437 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1438 } else { 1439 if (DC_IS_PNIC(sc)) { 1440 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1441 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1442 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1443 } 1444 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1445 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1446 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1447 } 1448 } 1449 1450 if (IFM_SUBTYPE(media) == IFM_10_T) { 1451 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1452 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1453 if (sc->dc_pmode == DC_PMODE_MII) { 1454 /* There's a write enable bit here that reads as 1. */ 1455 if (DC_IS_INTEL(sc)) { 1456 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1457 watchdogreg &= ~DC_WDOG_CTLWREN; 1458 watchdogreg |= DC_WDOG_JABBERDIS; 1459 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1460 } else { 1461 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1462 } 1463 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1464 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1465 if (sc->dc_type == DC_TYPE_98713) 1466 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1467 if (!DC_IS_DAVICOM(sc)) 1468 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1469 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1470 } else { 1471 if (DC_IS_PNIC(sc)) { 1472 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1473 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1474 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1475 } 1476 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1477 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1478 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1479 if (DC_IS_INTEL(sc)) { 1480 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1481 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1482 if ((media & IFM_GMASK) == IFM_FDX) 1483 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1484 else 1485 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1486 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1487 DC_CLRBIT(sc, DC_10BTCTRL, 1488 DC_TCTL_AUTONEGENBL); 1489 DELAY(20000); 1490 } 1491 } 1492 } 1493 1494 /* 1495 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1496 * PHY and we want HomePNA mode, set the portsel bit to turn 1497 * on the external MII port. 1498 */ 1499 if (DC_IS_DAVICOM(sc)) { 1500 if (IFM_SUBTYPE(media) == IFM_HPNA_1) { 1501 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1502 sc->dc_link = 1; 1503 } else { 1504 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1505 } 1506 } 1507 1508 if ((media & IFM_GMASK) == IFM_FDX) { 1509 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1510 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1511 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1512 } else { 1513 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1514 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1515 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1516 } 1517 1518 if (restart) 1519 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON | DC_NETCFG_RX_ON); 1520 } 1521 1522 static void 1523 dc_reset(struct dc_softc *sc) 1524 { 1525 int i; 1526 1527 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1528 1529 for (i = 0; i < DC_TIMEOUT; i++) { 1530 DELAY(10); 1531 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1532 break; 1533 } 1534 1535 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) || 1536 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc) || DC_IS_ULI(sc)) { 1537 DELAY(10000); 1538 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1539 i = 0; 1540 } 1541 1542 if (i == DC_TIMEOUT) 1543 device_printf(sc->dc_dev, "reset never completed!\n"); 1544 1545 /* Wait a little while for the chip to get its brains in order. */ 1546 DELAY(1000); 1547 1548 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1549 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1550 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1551 1552 /* 1553 * Bring the SIA out of reset. In some cases, it looks 1554 * like failing to unreset the SIA soon enough gets it 1555 * into a state where it will never come out of reset 1556 * until we reset the whole chip again. 1557 */ 1558 if (DC_IS_INTEL(sc)) { 1559 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1560 CSR_WRITE_4(sc, DC_10BTCTRL, 0xFFFFFFFF); 1561 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1562 } 1563 } 1564 1565 static const struct dc_type * 1566 dc_devtype(device_t dev) 1567 { 1568 const struct dc_type *t; 1569 uint32_t devid; 1570 uint8_t rev; 1571 1572 t = dc_devs; 1573 devid = pci_get_devid(dev); 1574 rev = pci_get_revid(dev); 1575 1576 while (t->dc_name != NULL) { 1577 if (devid == t->dc_devid && rev >= t->dc_minrev) 1578 return (t); 1579 t++; 1580 } 1581 1582 return (NULL); 1583 } 1584 1585 /* 1586 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1587 * IDs against our list and return a device name if we find a match. 1588 * We do a little bit of extra work to identify the exact type of 1589 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1590 * but different revision IDs. The same is true for 98715/98715A 1591 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1592 * cases, the exact chip revision affects driver behavior. 1593 */ 1594 static int 1595 dc_probe(device_t dev) 1596 { 1597 const struct dc_type *t; 1598 1599 t = dc_devtype(dev); 1600 1601 if (t != NULL) { 1602 device_set_desc(dev, t->dc_name); 1603 return (BUS_PROBE_DEFAULT); 1604 } 1605 1606 return (ENXIO); 1607 } 1608 1609 static void 1610 dc_apply_fixup(struct dc_softc *sc, int media) 1611 { 1612 struct dc_mediainfo *m; 1613 uint8_t *p; 1614 int i; 1615 uint32_t reg; 1616 1617 m = sc->dc_mi; 1618 1619 while (m != NULL) { 1620 if (m->dc_media == media) 1621 break; 1622 m = m->dc_next; 1623 } 1624 1625 if (m == NULL) 1626 return; 1627 1628 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1629 reg = (p[0] | (p[1] << 8)) << 16; 1630 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1631 } 1632 1633 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1634 reg = (p[0] | (p[1] << 8)) << 16; 1635 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1636 } 1637 } 1638 1639 static int 1640 dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l) 1641 { 1642 struct dc_mediainfo *m; 1643 1644 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1645 if (m == NULL) { 1646 device_printf(sc->dc_dev, "Could not allocate mediainfo\n"); 1647 return (ENOMEM); 1648 } 1649 switch (l->dc_sia_code & ~DC_SIA_CODE_EXT) { 1650 case DC_SIA_CODE_10BT: 1651 m->dc_media = IFM_10_T; 1652 break; 1653 case DC_SIA_CODE_10BT_FDX: 1654 m->dc_media = IFM_10_T | IFM_FDX; 1655 break; 1656 case DC_SIA_CODE_10B2: 1657 m->dc_media = IFM_10_2; 1658 break; 1659 case DC_SIA_CODE_10B5: 1660 m->dc_media = IFM_10_5; 1661 break; 1662 default: 1663 break; 1664 } 1665 1666 /* 1667 * We need to ignore CSR13, CSR14, CSR15 for SIA mode. 1668 * Things apparently already work for cards that do 1669 * supply Media Specific Data. 1670 */ 1671 if (l->dc_sia_code & DC_SIA_CODE_EXT) { 1672 m->dc_gp_len = 2; 1673 m->dc_gp_ptr = 1674 (uint8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl; 1675 } else { 1676 m->dc_gp_len = 2; 1677 m->dc_gp_ptr = 1678 (uint8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl; 1679 } 1680 1681 m->dc_next = sc->dc_mi; 1682 sc->dc_mi = m; 1683 1684 sc->dc_pmode = DC_PMODE_SIA; 1685 return (0); 1686 } 1687 1688 static int 1689 dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l) 1690 { 1691 struct dc_mediainfo *m; 1692 1693 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1694 if (m == NULL) { 1695 device_printf(sc->dc_dev, "Could not allocate mediainfo\n"); 1696 return (ENOMEM); 1697 } 1698 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1699 m->dc_media = IFM_100_TX; 1700 1701 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1702 m->dc_media = IFM_100_TX | IFM_FDX; 1703 1704 m->dc_gp_len = 2; 1705 m->dc_gp_ptr = (uint8_t *)&l->dc_sym_gpio_ctl; 1706 1707 m->dc_next = sc->dc_mi; 1708 sc->dc_mi = m; 1709 1710 sc->dc_pmode = DC_PMODE_SYM; 1711 return (0); 1712 } 1713 1714 static int 1715 dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l) 1716 { 1717 struct dc_mediainfo *m; 1718 uint8_t *p; 1719 1720 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1721 if (m == NULL) { 1722 device_printf(sc->dc_dev, "Could not allocate mediainfo\n"); 1723 return (ENOMEM); 1724 } 1725 /* We abuse IFM_AUTO to represent MII. */ 1726 m->dc_media = IFM_AUTO; 1727 m->dc_gp_len = l->dc_gpr_len; 1728 1729 p = (uint8_t *)l; 1730 p += sizeof(struct dc_eblock_mii); 1731 m->dc_gp_ptr = p; 1732 p += 2 * l->dc_gpr_len; 1733 m->dc_reset_len = *p; 1734 p++; 1735 m->dc_reset_ptr = p; 1736 1737 m->dc_next = sc->dc_mi; 1738 sc->dc_mi = m; 1739 return (0); 1740 } 1741 1742 static int 1743 dc_read_srom(struct dc_softc *sc, int bits) 1744 { 1745 int size; 1746 1747 size = DC_ROM_SIZE(bits); 1748 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO); 1749 if (sc->dc_srom == NULL) { 1750 device_printf(sc->dc_dev, "Could not allocate SROM buffer\n"); 1751 return (ENOMEM); 1752 } 1753 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); 1754 return (0); 1755 } 1756 1757 static int 1758 dc_parse_21143_srom(struct dc_softc *sc) 1759 { 1760 struct dc_leaf_hdr *lhdr; 1761 struct dc_eblock_hdr *hdr; 1762 int error, have_mii, i, loff; 1763 char *ptr; 1764 1765 have_mii = 0; 1766 loff = sc->dc_srom[27]; 1767 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1768 1769 ptr = (char *)lhdr; 1770 ptr += sizeof(struct dc_leaf_hdr) - 1; 1771 /* 1772 * Look if we got a MII media block. 1773 */ 1774 for (i = 0; i < lhdr->dc_mcnt; i++) { 1775 hdr = (struct dc_eblock_hdr *)ptr; 1776 if (hdr->dc_type == DC_EBLOCK_MII) 1777 have_mii++; 1778 1779 ptr += (hdr->dc_len & 0x7F); 1780 ptr++; 1781 } 1782 1783 /* 1784 * Do the same thing again. Only use SIA and SYM media 1785 * blocks if no MII media block is available. 1786 */ 1787 ptr = (char *)lhdr; 1788 ptr += sizeof(struct dc_leaf_hdr) - 1; 1789 error = 0; 1790 for (i = 0; i < lhdr->dc_mcnt; i++) { 1791 hdr = (struct dc_eblock_hdr *)ptr; 1792 switch (hdr->dc_type) { 1793 case DC_EBLOCK_MII: 1794 error = dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1795 break; 1796 case DC_EBLOCK_SIA: 1797 if (! have_mii) 1798 error = dc_decode_leaf_sia(sc, 1799 (struct dc_eblock_sia *)hdr); 1800 break; 1801 case DC_EBLOCK_SYM: 1802 if (! have_mii) 1803 error = dc_decode_leaf_sym(sc, 1804 (struct dc_eblock_sym *)hdr); 1805 break; 1806 default: 1807 /* Don't care. Yet. */ 1808 break; 1809 } 1810 ptr += (hdr->dc_len & 0x7F); 1811 ptr++; 1812 } 1813 return (error); 1814 } 1815 1816 static void 1817 dc_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1818 { 1819 bus_addr_t *paddr; 1820 1821 KASSERT(nseg == 1, 1822 ("%s: wrong number of segments (%d)", __func__, nseg)); 1823 paddr = arg; 1824 *paddr = segs->ds_addr; 1825 } 1826 1827 static int 1828 dc_dma_alloc(struct dc_softc *sc) 1829 { 1830 int error, i; 1831 1832 error = bus_dma_tag_create(bus_get_dma_tag(sc->dc_dev), 1, 0, 1833 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1834 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, 1835 NULL, NULL, &sc->dc_ptag); 1836 if (error) { 1837 device_printf(sc->dc_dev, 1838 "failed to allocate parent DMA tag\n"); 1839 goto fail; 1840 } 1841 1842 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */ 1843 error = bus_dma_tag_create(sc->dc_ptag, DC_LIST_ALIGN, 0, 1844 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, DC_RX_LIST_SZ, 1, 1845 DC_RX_LIST_SZ, 0, NULL, NULL, &sc->dc_rx_ltag); 1846 if (error) { 1847 device_printf(sc->dc_dev, "failed to create RX list DMA tag\n"); 1848 goto fail; 1849 } 1850 1851 error = bus_dma_tag_create(sc->dc_ptag, DC_LIST_ALIGN, 0, 1852 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, DC_TX_LIST_SZ, 1, 1853 DC_TX_LIST_SZ, 0, NULL, NULL, &sc->dc_tx_ltag); 1854 if (error) { 1855 device_printf(sc->dc_dev, "failed to create TX list DMA tag\n"); 1856 goto fail; 1857 } 1858 1859 /* RX descriptor list. */ 1860 error = bus_dmamem_alloc(sc->dc_rx_ltag, 1861 (void **)&sc->dc_ldata.dc_rx_list, BUS_DMA_NOWAIT | 1862 BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->dc_rx_lmap); 1863 if (error) { 1864 device_printf(sc->dc_dev, 1865 "failed to allocate DMA'able memory for RX list\n"); 1866 goto fail; 1867 } 1868 error = bus_dmamap_load(sc->dc_rx_ltag, sc->dc_rx_lmap, 1869 sc->dc_ldata.dc_rx_list, DC_RX_LIST_SZ, dc_dma_map_addr, 1870 &sc->dc_ldata.dc_rx_list_paddr, BUS_DMA_NOWAIT); 1871 if (error) { 1872 device_printf(sc->dc_dev, 1873 "failed to load DMA'able memory for RX list\n"); 1874 goto fail; 1875 } 1876 /* TX descriptor list. */ 1877 error = bus_dmamem_alloc(sc->dc_tx_ltag, 1878 (void **)&sc->dc_ldata.dc_tx_list, BUS_DMA_NOWAIT | 1879 BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->dc_tx_lmap); 1880 if (error) { 1881 device_printf(sc->dc_dev, 1882 "failed to allocate DMA'able memory for TX list\n"); 1883 goto fail; 1884 } 1885 error = bus_dmamap_load(sc->dc_tx_ltag, sc->dc_tx_lmap, 1886 sc->dc_ldata.dc_tx_list, DC_TX_LIST_SZ, dc_dma_map_addr, 1887 &sc->dc_ldata.dc_tx_list_paddr, BUS_DMA_NOWAIT); 1888 if (error) { 1889 device_printf(sc->dc_dev, 1890 "cannot load DMA'able memory for TX list\n"); 1891 goto fail; 1892 } 1893 1894 /* 1895 * Allocate a busdma tag and DMA safe memory for the multicast 1896 * setup frame. 1897 */ 1898 error = bus_dma_tag_create(sc->dc_ptag, DC_LIST_ALIGN, 0, 1899 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1900 DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1, DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1901 0, NULL, NULL, &sc->dc_stag); 1902 if (error) { 1903 device_printf(sc->dc_dev, 1904 "failed to create DMA tag for setup frame\n"); 1905 goto fail; 1906 } 1907 error = bus_dmamem_alloc(sc->dc_stag, (void **)&sc->dc_cdata.dc_sbuf, 1908 BUS_DMA_NOWAIT, &sc->dc_smap); 1909 if (error) { 1910 device_printf(sc->dc_dev, 1911 "failed to allocate DMA'able memory for setup frame\n"); 1912 goto fail; 1913 } 1914 error = bus_dmamap_load(sc->dc_stag, sc->dc_smap, sc->dc_cdata.dc_sbuf, 1915 DC_SFRAME_LEN, dc_dma_map_addr, &sc->dc_saddr, BUS_DMA_NOWAIT); 1916 if (error) { 1917 device_printf(sc->dc_dev, 1918 "cannot load DMA'able memory for setup frame\n"); 1919 goto fail; 1920 } 1921 1922 /* Allocate a busdma tag for RX mbufs. */ 1923 error = bus_dma_tag_create(sc->dc_ptag, DC_RXBUF_ALIGN, 0, 1924 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1925 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->dc_rx_mtag); 1926 if (error) { 1927 device_printf(sc->dc_dev, "failed to create RX mbuf tag\n"); 1928 goto fail; 1929 } 1930 1931 /* Allocate a busdma tag for TX mbufs. */ 1932 error = bus_dma_tag_create(sc->dc_ptag, 1, 0, 1933 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1934 MCLBYTES * DC_MAXFRAGS, DC_MAXFRAGS, MCLBYTES, 1935 0, NULL, NULL, &sc->dc_tx_mtag); 1936 if (error) { 1937 device_printf(sc->dc_dev, "failed to create TX mbuf tag\n"); 1938 goto fail; 1939 } 1940 1941 /* Create the TX/RX busdma maps. */ 1942 for (i = 0; i < DC_TX_LIST_CNT; i++) { 1943 error = bus_dmamap_create(sc->dc_tx_mtag, 0, 1944 &sc->dc_cdata.dc_tx_map[i]); 1945 if (error) { 1946 device_printf(sc->dc_dev, 1947 "failed to create TX mbuf dmamap\n"); 1948 goto fail; 1949 } 1950 } 1951 for (i = 0; i < DC_RX_LIST_CNT; i++) { 1952 error = bus_dmamap_create(sc->dc_rx_mtag, 0, 1953 &sc->dc_cdata.dc_rx_map[i]); 1954 if (error) { 1955 device_printf(sc->dc_dev, 1956 "failed to create RX mbuf dmamap\n"); 1957 goto fail; 1958 } 1959 } 1960 error = bus_dmamap_create(sc->dc_rx_mtag, 0, &sc->dc_sparemap); 1961 if (error) { 1962 device_printf(sc->dc_dev, 1963 "failed to create spare RX mbuf dmamap\n"); 1964 goto fail; 1965 } 1966 1967 fail: 1968 return (error); 1969 } 1970 1971 static void 1972 dc_dma_free(struct dc_softc *sc) 1973 { 1974 int i; 1975 1976 /* RX buffers. */ 1977 if (sc->dc_rx_mtag != NULL) { 1978 for (i = 0; i < DC_RX_LIST_CNT; i++) { 1979 if (sc->dc_cdata.dc_rx_map[i] != NULL) 1980 bus_dmamap_destroy(sc->dc_rx_mtag, 1981 sc->dc_cdata.dc_rx_map[i]); 1982 } 1983 if (sc->dc_sparemap != NULL) 1984 bus_dmamap_destroy(sc->dc_rx_mtag, sc->dc_sparemap); 1985 bus_dma_tag_destroy(sc->dc_rx_mtag); 1986 } 1987 1988 /* TX buffers. */ 1989 if (sc->dc_rx_mtag != NULL) { 1990 for (i = 0; i < DC_TX_LIST_CNT; i++) { 1991 if (sc->dc_cdata.dc_tx_map[i] != NULL) 1992 bus_dmamap_destroy(sc->dc_tx_mtag, 1993 sc->dc_cdata.dc_tx_map[i]); 1994 } 1995 bus_dma_tag_destroy(sc->dc_tx_mtag); 1996 } 1997 1998 /* RX descriptor list. */ 1999 if (sc->dc_rx_ltag) { 2000 if (sc->dc_ldata.dc_rx_list_paddr != 0) 2001 bus_dmamap_unload(sc->dc_rx_ltag, sc->dc_rx_lmap); 2002 if (sc->dc_ldata.dc_rx_list != NULL) 2003 bus_dmamem_free(sc->dc_rx_ltag, sc->dc_ldata.dc_rx_list, 2004 sc->dc_rx_lmap); 2005 bus_dma_tag_destroy(sc->dc_rx_ltag); 2006 } 2007 2008 /* TX descriptor list. */ 2009 if (sc->dc_tx_ltag) { 2010 if (sc->dc_ldata.dc_tx_list_paddr != 0) 2011 bus_dmamap_unload(sc->dc_tx_ltag, sc->dc_tx_lmap); 2012 if (sc->dc_ldata.dc_tx_list != NULL) 2013 bus_dmamem_free(sc->dc_tx_ltag, sc->dc_ldata.dc_tx_list, 2014 sc->dc_tx_lmap); 2015 bus_dma_tag_destroy(sc->dc_tx_ltag); 2016 } 2017 2018 /* multicast setup frame. */ 2019 if (sc->dc_stag) { 2020 if (sc->dc_saddr != 0) 2021 bus_dmamap_unload(sc->dc_stag, sc->dc_smap); 2022 if (sc->dc_cdata.dc_sbuf != NULL) 2023 bus_dmamem_free(sc->dc_stag, sc->dc_cdata.dc_sbuf, 2024 sc->dc_smap); 2025 bus_dma_tag_destroy(sc->dc_stag); 2026 } 2027 } 2028 2029 /* 2030 * Attach the interface. Allocate softc structures, do ifmedia 2031 * setup and ethernet/BPF attach. 2032 */ 2033 static int 2034 dc_attach(device_t dev) 2035 { 2036 uint32_t eaddr[(ETHER_ADDR_LEN+3)/4]; 2037 uint32_t command; 2038 struct dc_softc *sc; 2039 struct ifnet *ifp; 2040 struct dc_mediainfo *m; 2041 uint32_t reg, revision; 2042 uint16_t *srom; 2043 int error, mac_offset, n, phy, rid, tmp; 2044 uint8_t *mac; 2045 2046 sc = device_get_softc(dev); 2047 sc->dc_dev = dev; 2048 2049 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 2050 MTX_DEF); 2051 2052 /* 2053 * Map control/status registers. 2054 */ 2055 pci_enable_busmaster(dev); 2056 2057 rid = DC_RID; 2058 sc->dc_res = bus_alloc_resource_any(dev, DC_RES, &rid, RF_ACTIVE); 2059 2060 if (sc->dc_res == NULL) { 2061 device_printf(dev, "couldn't map ports/memory\n"); 2062 error = ENXIO; 2063 goto fail; 2064 } 2065 2066 sc->dc_btag = rman_get_bustag(sc->dc_res); 2067 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 2068 2069 /* Allocate interrupt. */ 2070 rid = 0; 2071 sc->dc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 2072 RF_SHAREABLE | RF_ACTIVE); 2073 2074 if (sc->dc_irq == NULL) { 2075 device_printf(dev, "couldn't map interrupt\n"); 2076 error = ENXIO; 2077 goto fail; 2078 } 2079 2080 /* Need this info to decide on a chip type. */ 2081 sc->dc_info = dc_devtype(dev); 2082 revision = pci_get_revid(dev); 2083 2084 error = 0; 2085 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */ 2086 if (sc->dc_info->dc_devid != 2087 DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168) && 2088 sc->dc_info->dc_devid != 2089 DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201)) 2090 dc_eeprom_width(sc); 2091 2092 switch (sc->dc_info->dc_devid) { 2093 case DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143): 2094 sc->dc_type = DC_TYPE_21143; 2095 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 2096 sc->dc_flags |= DC_REDUCED_MII_POLL; 2097 /* Save EEPROM contents so we can parse them later. */ 2098 error = dc_read_srom(sc, sc->dc_romwidth); 2099 if (error != 0) 2100 goto fail; 2101 break; 2102 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009): 2103 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100): 2104 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102): 2105 sc->dc_type = DC_TYPE_DM9102; 2106 sc->dc_flags |= DC_TX_COALESCE | DC_TX_INTR_ALWAYS; 2107 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_TX_STORENFWD; 2108 sc->dc_flags |= DC_TX_ALIGN; 2109 sc->dc_pmode = DC_PMODE_MII; 2110 2111 /* Increase the latency timer value. */ 2112 pci_write_config(dev, PCIR_LATTIMER, 0x80, 1); 2113 break; 2114 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981): 2115 sc->dc_type = DC_TYPE_AL981; 2116 sc->dc_flags |= DC_TX_USE_TX_INTR; 2117 sc->dc_flags |= DC_TX_ADMTEK_WAR; 2118 sc->dc_pmode = DC_PMODE_MII; 2119 error = dc_read_srom(sc, sc->dc_romwidth); 2120 if (error != 0) 2121 goto fail; 2122 break; 2123 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN983): 2124 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985): 2125 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511): 2126 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513): 2127 case DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD): 2128 case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500): 2129 case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX): 2130 case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242): 2131 case DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX): 2132 case DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T): 2133 case DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB): 2134 case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120): 2135 case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130): 2136 case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08): 2137 case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09): 2138 sc->dc_type = DC_TYPE_AN983; 2139 sc->dc_flags |= DC_64BIT_HASH; 2140 sc->dc_flags |= DC_TX_USE_TX_INTR; 2141 sc->dc_flags |= DC_TX_ADMTEK_WAR; 2142 sc->dc_pmode = DC_PMODE_MII; 2143 /* Don't read SROM for - auto-loaded on reset */ 2144 break; 2145 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713): 2146 case DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP): 2147 if (revision < DC_REVISION_98713A) { 2148 sc->dc_type = DC_TYPE_98713; 2149 } 2150 if (revision >= DC_REVISION_98713A) { 2151 sc->dc_type = DC_TYPE_98713A; 2152 sc->dc_flags |= DC_21143_NWAY; 2153 } 2154 sc->dc_flags |= DC_REDUCED_MII_POLL; 2155 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 2156 break; 2157 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5): 2158 case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217): 2159 /* 2160 * Macronix MX98715AEC-C/D/E parts have only a 2161 * 128-bit hash table. We need to deal with these 2162 * in the same manner as the PNIC II so that we 2163 * get the right number of bits out of the 2164 * CRC routine. 2165 */ 2166 if (revision >= DC_REVISION_98715AEC_C && 2167 revision < DC_REVISION_98725) 2168 sc->dc_flags |= DC_128BIT_HASH; 2169 sc->dc_type = DC_TYPE_987x5; 2170 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 2171 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 2172 break; 2173 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727): 2174 sc->dc_type = DC_TYPE_987x5; 2175 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 2176 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 2177 break; 2178 case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115): 2179 sc->dc_type = DC_TYPE_PNICII; 2180 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR | DC_128BIT_HASH; 2181 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 2182 break; 2183 case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168): 2184 sc->dc_type = DC_TYPE_PNIC; 2185 sc->dc_flags |= DC_TX_STORENFWD | DC_TX_INTR_ALWAYS; 2186 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 2187 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 2188 if (sc->dc_pnic_rx_buf == NULL) { 2189 device_printf(sc->dc_dev, 2190 "Could not allocate PNIC RX buffer\n"); 2191 error = ENOMEM; 2192 goto fail; 2193 } 2194 if (revision < DC_REVISION_82C169) 2195 sc->dc_pmode = DC_PMODE_SYM; 2196 break; 2197 case DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A): 2198 sc->dc_type = DC_TYPE_ASIX; 2199 sc->dc_flags |= DC_TX_USE_TX_INTR | DC_TX_INTR_FIRSTFRAG; 2200 sc->dc_flags |= DC_REDUCED_MII_POLL; 2201 sc->dc_pmode = DC_PMODE_MII; 2202 break; 2203 case DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201): 2204 sc->dc_type = DC_TYPE_XIRCOM; 2205 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 2206 DC_TX_ALIGN; 2207 /* 2208 * We don't actually need to coalesce, but we're doing 2209 * it to obtain a double word aligned buffer. 2210 * The DC_TX_COALESCE flag is required. 2211 */ 2212 sc->dc_pmode = DC_PMODE_MII; 2213 break; 2214 case DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112): 2215 sc->dc_type = DC_TYPE_CONEXANT; 2216 sc->dc_flags |= DC_TX_INTR_ALWAYS; 2217 sc->dc_flags |= DC_REDUCED_MII_POLL; 2218 sc->dc_pmode = DC_PMODE_MII; 2219 error = dc_read_srom(sc, sc->dc_romwidth); 2220 if (error != 0) 2221 goto fail; 2222 break; 2223 case DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5261): 2224 case DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5263): 2225 if (sc->dc_info->dc_devid == 2226 DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5261)) 2227 sc->dc_type = DC_TYPE_ULI_M5261; 2228 else 2229 sc->dc_type = DC_TYPE_ULI_M5263; 2230 /* TX buffers should be aligned on 4 byte boundary. */ 2231 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 2232 DC_TX_ALIGN; 2233 sc->dc_pmode = DC_PMODE_MII; 2234 error = dc_read_srom(sc, sc->dc_romwidth); 2235 if (error != 0) 2236 goto fail; 2237 break; 2238 default: 2239 device_printf(dev, "unknown device: %x\n", 2240 sc->dc_info->dc_devid); 2241 break; 2242 } 2243 2244 /* Save the cache line size. */ 2245 if (DC_IS_DAVICOM(sc)) 2246 sc->dc_cachesize = 0; 2247 else 2248 sc->dc_cachesize = pci_get_cachelnsz(dev); 2249 2250 /* Reset the adapter. */ 2251 dc_reset(sc); 2252 2253 /* Take 21143 out of snooze mode */ 2254 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 2255 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2256 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 2257 pci_write_config(dev, DC_PCI_CFDD, command, 4); 2258 } 2259 2260 /* 2261 * Try to learn something about the supported media. 2262 * We know that ASIX and ADMtek and Davicom devices 2263 * will *always* be using MII media, so that's a no-brainer. 2264 * The tricky ones are the Macronix/PNIC II and the 2265 * Intel 21143. 2266 */ 2267 if (DC_IS_INTEL(sc)) { 2268 error = dc_parse_21143_srom(sc); 2269 if (error != 0) 2270 goto fail; 2271 } else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2272 if (sc->dc_type == DC_TYPE_98713) 2273 sc->dc_pmode = DC_PMODE_MII; 2274 else 2275 sc->dc_pmode = DC_PMODE_SYM; 2276 } else if (!sc->dc_pmode) 2277 sc->dc_pmode = DC_PMODE_MII; 2278 2279 /* 2280 * Get station address from the EEPROM. 2281 */ 2282 switch(sc->dc_type) { 2283 case DC_TYPE_98713: 2284 case DC_TYPE_98713A: 2285 case DC_TYPE_987x5: 2286 case DC_TYPE_PNICII: 2287 dc_read_eeprom(sc, (caddr_t)&mac_offset, 2288 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2289 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2290 break; 2291 case DC_TYPE_PNIC: 2292 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2293 break; 2294 case DC_TYPE_DM9102: 2295 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2296 #ifdef __sparc64__ 2297 /* 2298 * If this is an onboard dc(4) the station address read from 2299 * the EEPROM is all zero and we have to get it from the FCode. 2300 */ 2301 if (eaddr[0] == 0 && (eaddr[1] & ~0xffff) == 0) 2302 OF_getetheraddr(dev, (caddr_t)&eaddr); 2303 #endif 2304 break; 2305 case DC_TYPE_21143: 2306 case DC_TYPE_ASIX: 2307 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2308 break; 2309 case DC_TYPE_AL981: 2310 case DC_TYPE_AN983: 2311 reg = CSR_READ_4(sc, DC_AL_PAR0); 2312 mac = (uint8_t *)&eaddr[0]; 2313 mac[0] = (reg >> 0) & 0xff; 2314 mac[1] = (reg >> 8) & 0xff; 2315 mac[2] = (reg >> 16) & 0xff; 2316 mac[3] = (reg >> 24) & 0xff; 2317 reg = CSR_READ_4(sc, DC_AL_PAR1); 2318 mac[4] = (reg >> 0) & 0xff; 2319 mac[5] = (reg >> 8) & 0xff; 2320 break; 2321 case DC_TYPE_CONEXANT: 2322 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 2323 ETHER_ADDR_LEN); 2324 break; 2325 case DC_TYPE_XIRCOM: 2326 /* The MAC comes from the CIS. */ 2327 mac = pci_get_ether(dev); 2328 if (!mac) { 2329 device_printf(dev, "No station address in CIS!\n"); 2330 error = ENXIO; 2331 goto fail; 2332 } 2333 bcopy(mac, eaddr, ETHER_ADDR_LEN); 2334 break; 2335 case DC_TYPE_ULI_M5261: 2336 case DC_TYPE_ULI_M5263: 2337 srom = (uint16_t *)sc->dc_srom; 2338 if (srom == NULL || *srom == 0xFFFF || *srom == 0) { 2339 /* 2340 * No valid SROM present, read station address 2341 * from ID Table. 2342 */ 2343 device_printf(dev, 2344 "Reading station address from ID Table.\n"); 2345 CSR_WRITE_4(sc, DC_BUSCTL, 0x10000); 2346 CSR_WRITE_4(sc, DC_SIARESET, 0x01C0); 2347 CSR_WRITE_4(sc, DC_10BTCTRL, 0x0000); 2348 CSR_WRITE_4(sc, DC_10BTCTRL, 0x0010); 2349 CSR_WRITE_4(sc, DC_10BTCTRL, 0x0000); 2350 CSR_WRITE_4(sc, DC_SIARESET, 0x0000); 2351 CSR_WRITE_4(sc, DC_SIARESET, 0x01B0); 2352 mac = (uint8_t *)eaddr; 2353 for (n = 0; n < ETHER_ADDR_LEN; n++) 2354 mac[n] = (uint8_t)CSR_READ_4(sc, DC_10BTCTRL); 2355 CSR_WRITE_4(sc, DC_SIARESET, 0x0000); 2356 CSR_WRITE_4(sc, DC_BUSCTL, 0x0000); 2357 DELAY(10); 2358 } else 2359 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 2360 0); 2361 break; 2362 default: 2363 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2364 break; 2365 } 2366 2367 bcopy(eaddr, sc->dc_eaddr, sizeof(eaddr)); 2368 /* 2369 * If we still have invalid station address, see whether we can 2370 * find station address for chip 0. Some multi-port controllers 2371 * just store station address for chip 0 if they have a shared 2372 * SROM. 2373 */ 2374 if ((sc->dc_eaddr[0] == 0 && (sc->dc_eaddr[1] & ~0xffff) == 0) || 2375 (sc->dc_eaddr[0] == 0xffffffff && 2376 (sc->dc_eaddr[1] & 0xffff) == 0xffff)) { 2377 error = dc_check_multiport(sc); 2378 if (error == 0) { 2379 bcopy(sc->dc_eaddr, eaddr, sizeof(eaddr)); 2380 /* Extract media information. */ 2381 if (DC_IS_INTEL(sc) && sc->dc_srom != NULL) { 2382 while (sc->dc_mi != NULL) { 2383 m = sc->dc_mi->dc_next; 2384 free(sc->dc_mi, M_DEVBUF); 2385 sc->dc_mi = m; 2386 } 2387 error = dc_parse_21143_srom(sc); 2388 if (error != 0) 2389 goto fail; 2390 } 2391 } else if (error == ENOMEM) 2392 goto fail; 2393 else 2394 error = 0; 2395 } 2396 2397 if ((error = dc_dma_alloc(sc)) != 0) 2398 goto fail; 2399 2400 ifp = sc->dc_ifp = if_alloc(IFT_ETHER); 2401 if (ifp == NULL) { 2402 device_printf(dev, "can not if_alloc()\n"); 2403 error = ENOSPC; 2404 goto fail; 2405 } 2406 ifp->if_softc = sc; 2407 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2408 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2409 ifp->if_ioctl = dc_ioctl; 2410 ifp->if_start = dc_start; 2411 ifp->if_init = dc_init; 2412 IFQ_SET_MAXLEN(&ifp->if_snd, DC_TX_LIST_CNT - 1); 2413 ifp->if_snd.ifq_drv_maxlen = DC_TX_LIST_CNT - 1; 2414 IFQ_SET_READY(&ifp->if_snd); 2415 2416 /* 2417 * Do MII setup. If this is a 21143, check for a PHY on the 2418 * MII bus after applying any necessary fixups to twiddle the 2419 * GPIO bits. If we don't end up finding a PHY, restore the 2420 * old selection (SIA only or SIA/SYM) and attach the dcphy 2421 * driver instead. 2422 */ 2423 tmp = 0; 2424 if (DC_IS_INTEL(sc)) { 2425 dc_apply_fixup(sc, IFM_AUTO); 2426 tmp = sc->dc_pmode; 2427 sc->dc_pmode = DC_PMODE_MII; 2428 } 2429 2430 /* 2431 * Setup General Purpose port mode and data so the tulip can talk 2432 * to the MII. This needs to be done before mii_attach so that 2433 * we can actually see them. 2434 */ 2435 if (DC_IS_XIRCOM(sc)) { 2436 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2437 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2438 DELAY(10); 2439 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2440 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2441 DELAY(10); 2442 } 2443 2444 phy = MII_PHY_ANY; 2445 /* 2446 * Note: both the AL981 and AN983 have internal PHYs, however the 2447 * AL981 provides direct access to the PHY registers while the AN983 2448 * uses a serial MII interface. The AN983's MII interface is also 2449 * buggy in that you can read from any MII address (0 to 31), but 2450 * only address 1 behaves normally. To deal with both cases, we 2451 * pretend that the PHY is at MII address 1. 2452 */ 2453 if (DC_IS_ADMTEK(sc)) 2454 phy = DC_ADMTEK_PHYADDR; 2455 2456 /* 2457 * Note: the ukphy probes of the RS7112 report a PHY at MII address 2458 * 0 (possibly HomePNA?) and 1 (ethernet) so we only respond to the 2459 * correct one. 2460 */ 2461 if (DC_IS_CONEXANT(sc)) 2462 phy = DC_CONEXANT_PHYADDR; 2463 2464 error = mii_attach(dev, &sc->dc_miibus, ifp, dc_ifmedia_upd, 2465 dc_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0); 2466 2467 if (error && DC_IS_INTEL(sc)) { 2468 sc->dc_pmode = tmp; 2469 if (sc->dc_pmode != DC_PMODE_SIA) 2470 sc->dc_pmode = DC_PMODE_SYM; 2471 sc->dc_flags |= DC_21143_NWAY; 2472 /* 2473 * For non-MII cards, we need to have the 21143 2474 * drive the LEDs. Except there are some systems 2475 * like the NEC VersaPro NoteBook PC which have no 2476 * LEDs, and twiddling these bits has adverse effects 2477 * on them. (I.e. you suddenly can't get a link.) 2478 */ 2479 if (!(pci_get_subvendor(dev) == 0x1033 && 2480 pci_get_subdevice(dev) == 0x8028)) 2481 sc->dc_flags |= DC_TULIP_LEDS; 2482 error = mii_attach(dev, &sc->dc_miibus, ifp, dc_ifmedia_upd, 2483 dc_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, 2484 MII_OFFSET_ANY, 0); 2485 } 2486 2487 if (error) { 2488 device_printf(dev, "attaching PHYs failed\n"); 2489 goto fail; 2490 } 2491 2492 if (DC_IS_ADMTEK(sc)) { 2493 /* 2494 * Set automatic TX underrun recovery for the ADMtek chips 2495 */ 2496 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); 2497 } 2498 2499 /* 2500 * Tell the upper layer(s) we support long frames. 2501 */ 2502 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 2503 ifp->if_capabilities |= IFCAP_VLAN_MTU; 2504 ifp->if_capenable = ifp->if_capabilities; 2505 #ifdef DEVICE_POLLING 2506 ifp->if_capabilities |= IFCAP_POLLING; 2507 #endif 2508 2509 callout_init_mtx(&sc->dc_stat_ch, &sc->dc_mtx, 0); 2510 callout_init_mtx(&sc->dc_wdog_ch, &sc->dc_mtx, 0); 2511 2512 /* 2513 * Call MI attach routine. 2514 */ 2515 ether_ifattach(ifp, (caddr_t)eaddr); 2516 2517 /* Hook interrupt last to avoid having to lock softc */ 2518 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | INTR_MPSAFE, 2519 NULL, dc_intr, sc, &sc->dc_intrhand); 2520 2521 if (error) { 2522 device_printf(dev, "couldn't set up irq\n"); 2523 ether_ifdetach(ifp); 2524 goto fail; 2525 } 2526 2527 fail: 2528 if (error) 2529 dc_detach(dev); 2530 return (error); 2531 } 2532 2533 /* 2534 * Shutdown hardware and free up resources. This can be called any 2535 * time after the mutex has been initialized. It is called in both 2536 * the error case in attach and the normal detach case so it needs 2537 * to be careful about only freeing resources that have actually been 2538 * allocated. 2539 */ 2540 static int 2541 dc_detach(device_t dev) 2542 { 2543 struct dc_softc *sc; 2544 struct ifnet *ifp; 2545 struct dc_mediainfo *m; 2546 2547 sc = device_get_softc(dev); 2548 KASSERT(mtx_initialized(&sc->dc_mtx), ("dc mutex not initialized")); 2549 2550 ifp = sc->dc_ifp; 2551 2552 #ifdef DEVICE_POLLING 2553 if (ifp != NULL && ifp->if_capenable & IFCAP_POLLING) 2554 ether_poll_deregister(ifp); 2555 #endif 2556 2557 /* These should only be active if attach succeeded */ 2558 if (device_is_attached(dev)) { 2559 DC_LOCK(sc); 2560 dc_stop(sc); 2561 DC_UNLOCK(sc); 2562 callout_drain(&sc->dc_stat_ch); 2563 callout_drain(&sc->dc_wdog_ch); 2564 ether_ifdetach(ifp); 2565 } 2566 if (sc->dc_miibus) 2567 device_delete_child(dev, sc->dc_miibus); 2568 bus_generic_detach(dev); 2569 2570 if (sc->dc_intrhand) 2571 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2572 if (sc->dc_irq) 2573 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2574 if (sc->dc_res) 2575 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2576 2577 if (ifp != NULL) 2578 if_free(ifp); 2579 2580 dc_dma_free(sc); 2581 2582 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2583 2584 while (sc->dc_mi != NULL) { 2585 m = sc->dc_mi->dc_next; 2586 free(sc->dc_mi, M_DEVBUF); 2587 sc->dc_mi = m; 2588 } 2589 free(sc->dc_srom, M_DEVBUF); 2590 2591 mtx_destroy(&sc->dc_mtx); 2592 2593 return (0); 2594 } 2595 2596 /* 2597 * Initialize the transmit descriptors. 2598 */ 2599 static int 2600 dc_list_tx_init(struct dc_softc *sc) 2601 { 2602 struct dc_chain_data *cd; 2603 struct dc_list_data *ld; 2604 int i, nexti; 2605 2606 cd = &sc->dc_cdata; 2607 ld = &sc->dc_ldata; 2608 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2609 if (i == DC_TX_LIST_CNT - 1) 2610 nexti = 0; 2611 else 2612 nexti = i + 1; 2613 ld->dc_tx_list[i].dc_status = 0; 2614 ld->dc_tx_list[i].dc_ctl = 0; 2615 ld->dc_tx_list[i].dc_data = 0; 2616 ld->dc_tx_list[i].dc_next = htole32(DC_TXDESC(sc, nexti)); 2617 cd->dc_tx_chain[i] = NULL; 2618 } 2619 2620 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2621 cd->dc_tx_pkts = 0; 2622 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, 2623 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2624 return (0); 2625 } 2626 2627 /* 2628 * Initialize the RX descriptors and allocate mbufs for them. Note that 2629 * we arrange the descriptors in a closed ring, so that the last descriptor 2630 * points back to the first. 2631 */ 2632 static int 2633 dc_list_rx_init(struct dc_softc *sc) 2634 { 2635 struct dc_chain_data *cd; 2636 struct dc_list_data *ld; 2637 int i, nexti; 2638 2639 cd = &sc->dc_cdata; 2640 ld = &sc->dc_ldata; 2641 2642 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2643 if (dc_newbuf(sc, i) != 0) 2644 return (ENOBUFS); 2645 if (i == DC_RX_LIST_CNT - 1) 2646 nexti = 0; 2647 else 2648 nexti = i + 1; 2649 ld->dc_rx_list[i].dc_next = htole32(DC_RXDESC(sc, nexti)); 2650 } 2651 2652 cd->dc_rx_prod = 0; 2653 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, 2654 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2655 return (0); 2656 } 2657 2658 /* 2659 * Initialize an RX descriptor and attach an MBUF cluster. 2660 */ 2661 static int 2662 dc_newbuf(struct dc_softc *sc, int i) 2663 { 2664 struct mbuf *m; 2665 bus_dmamap_t map; 2666 bus_dma_segment_t segs[1]; 2667 int error, nseg; 2668 2669 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 2670 if (m == NULL) 2671 return (ENOBUFS); 2672 m->m_len = m->m_pkthdr.len = MCLBYTES; 2673 m_adj(m, sizeof(u_int64_t)); 2674 2675 /* 2676 * If this is a PNIC chip, zero the buffer. This is part 2677 * of the workaround for the receive bug in the 82c168 and 2678 * 82c169 chips. 2679 */ 2680 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2681 bzero(mtod(m, char *), m->m_len); 2682 2683 error = bus_dmamap_load_mbuf_sg(sc->dc_rx_mtag, sc->dc_sparemap, 2684 m, segs, &nseg, 0); 2685 if (error) { 2686 m_freem(m); 2687 return (error); 2688 } 2689 KASSERT(nseg == 1, ("%s: wrong number of segments (%d)", __func__, 2690 nseg)); 2691 if (sc->dc_cdata.dc_rx_chain[i] != NULL) 2692 bus_dmamap_unload(sc->dc_rx_mtag, sc->dc_cdata.dc_rx_map[i]); 2693 2694 map = sc->dc_cdata.dc_rx_map[i]; 2695 sc->dc_cdata.dc_rx_map[i] = sc->dc_sparemap; 2696 sc->dc_sparemap = map; 2697 sc->dc_cdata.dc_rx_chain[i] = m; 2698 bus_dmamap_sync(sc->dc_rx_mtag, sc->dc_cdata.dc_rx_map[i], 2699 BUS_DMASYNC_PREREAD); 2700 2701 sc->dc_ldata.dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN); 2702 sc->dc_ldata.dc_rx_list[i].dc_data = 2703 htole32(DC_ADDR_LO(segs[0].ds_addr)); 2704 sc->dc_ldata.dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN); 2705 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, 2706 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2707 return (0); 2708 } 2709 2710 /* 2711 * Grrrrr. 2712 * The PNIC chip has a terrible bug in it that manifests itself during 2713 * periods of heavy activity. The exact mode of failure if difficult to 2714 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2715 * will happen on slow machines. The bug is that sometimes instead of 2716 * uploading one complete frame during reception, it uploads what looks 2717 * like the entire contents of its FIFO memory. The frame we want is at 2718 * the end of the whole mess, but we never know exactly how much data has 2719 * been uploaded, so salvaging the frame is hard. 2720 * 2721 * There is only one way to do it reliably, and it's disgusting. 2722 * Here's what we know: 2723 * 2724 * - We know there will always be somewhere between one and three extra 2725 * descriptors uploaded. 2726 * 2727 * - We know the desired received frame will always be at the end of the 2728 * total data upload. 2729 * 2730 * - We know the size of the desired received frame because it will be 2731 * provided in the length field of the status word in the last descriptor. 2732 * 2733 * Here's what we do: 2734 * 2735 * - When we allocate buffers for the receive ring, we bzero() them. 2736 * This means that we know that the buffer contents should be all 2737 * zeros, except for data uploaded by the chip. 2738 * 2739 * - We also force the PNIC chip to upload frames that include the 2740 * ethernet CRC at the end. 2741 * 2742 * - We gather all of the bogus frame data into a single buffer. 2743 * 2744 * - We then position a pointer at the end of this buffer and scan 2745 * backwards until we encounter the first non-zero byte of data. 2746 * This is the end of the received frame. We know we will encounter 2747 * some data at the end of the frame because the CRC will always be 2748 * there, so even if the sender transmits a packet of all zeros, 2749 * we won't be fooled. 2750 * 2751 * - We know the size of the actual received frame, so we subtract 2752 * that value from the current pointer location. This brings us 2753 * to the start of the actual received packet. 2754 * 2755 * - We copy this into an mbuf and pass it on, along with the actual 2756 * frame length. 2757 * 2758 * The performance hit is tremendous, but it beats dropping frames all 2759 * the time. 2760 */ 2761 2762 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG | DC_RXSTAT_LASTFRAG) 2763 static void 2764 dc_pnic_rx_bug_war(struct dc_softc *sc, int idx) 2765 { 2766 struct dc_desc *cur_rx; 2767 struct dc_desc *c = NULL; 2768 struct mbuf *m = NULL; 2769 unsigned char *ptr; 2770 int i, total_len; 2771 uint32_t rxstat = 0; 2772 2773 i = sc->dc_pnic_rx_bug_save; 2774 cur_rx = &sc->dc_ldata.dc_rx_list[idx]; 2775 ptr = sc->dc_pnic_rx_buf; 2776 bzero(ptr, DC_RXLEN * 5); 2777 2778 /* Copy all the bytes from the bogus buffers. */ 2779 while (1) { 2780 c = &sc->dc_ldata.dc_rx_list[i]; 2781 rxstat = le32toh(c->dc_status); 2782 m = sc->dc_cdata.dc_rx_chain[i]; 2783 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2784 ptr += DC_RXLEN; 2785 /* If this is the last buffer, break out. */ 2786 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2787 break; 2788 dc_discard_rxbuf(sc, i); 2789 DC_INC(i, DC_RX_LIST_CNT); 2790 } 2791 2792 /* Find the length of the actual receive frame. */ 2793 total_len = DC_RXBYTES(rxstat); 2794 2795 /* Scan backwards until we hit a non-zero byte. */ 2796 while (*ptr == 0x00) 2797 ptr--; 2798 2799 /* Round off. */ 2800 if ((uintptr_t)(ptr) & 0x3) 2801 ptr -= 1; 2802 2803 /* Now find the start of the frame. */ 2804 ptr -= total_len; 2805 if (ptr < sc->dc_pnic_rx_buf) 2806 ptr = sc->dc_pnic_rx_buf; 2807 2808 /* 2809 * Now copy the salvaged frame to the last mbuf and fake up 2810 * the status word to make it look like a successful 2811 * frame reception. 2812 */ 2813 bcopy(ptr, mtod(m, char *), total_len); 2814 cur_rx->dc_status = htole32(rxstat | DC_RXSTAT_FIRSTFRAG); 2815 } 2816 2817 /* 2818 * This routine searches the RX ring for dirty descriptors in the 2819 * event that the rxeof routine falls out of sync with the chip's 2820 * current descriptor pointer. This may happen sometimes as a result 2821 * of a "no RX buffer available" condition that happens when the chip 2822 * consumes all of the RX buffers before the driver has a chance to 2823 * process the RX ring. This routine may need to be called more than 2824 * once to bring the driver back in sync with the chip, however we 2825 * should still be getting RX DONE interrupts to drive the search 2826 * for new packets in the RX ring, so we should catch up eventually. 2827 */ 2828 static int 2829 dc_rx_resync(struct dc_softc *sc) 2830 { 2831 struct dc_desc *cur_rx; 2832 int i, pos; 2833 2834 pos = sc->dc_cdata.dc_rx_prod; 2835 2836 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2837 cur_rx = &sc->dc_ldata.dc_rx_list[pos]; 2838 if (!(le32toh(cur_rx->dc_status) & DC_RXSTAT_OWN)) 2839 break; 2840 DC_INC(pos, DC_RX_LIST_CNT); 2841 } 2842 2843 /* If the ring really is empty, then just return. */ 2844 if (i == DC_RX_LIST_CNT) 2845 return (0); 2846 2847 /* We've fallen behing the chip: catch it. */ 2848 sc->dc_cdata.dc_rx_prod = pos; 2849 2850 return (EAGAIN); 2851 } 2852 2853 static void 2854 dc_discard_rxbuf(struct dc_softc *sc, int i) 2855 { 2856 struct mbuf *m; 2857 2858 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2859 m = sc->dc_cdata.dc_rx_chain[i]; 2860 bzero(mtod(m, char *), m->m_len); 2861 } 2862 2863 sc->dc_ldata.dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN); 2864 sc->dc_ldata.dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN); 2865 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, BUS_DMASYNC_PREREAD | 2866 BUS_DMASYNC_PREWRITE); 2867 } 2868 2869 /* 2870 * A frame has been uploaded: pass the resulting mbuf chain up to 2871 * the higher level protocols. 2872 */ 2873 static int 2874 dc_rxeof(struct dc_softc *sc) 2875 { 2876 struct mbuf *m; 2877 struct ifnet *ifp; 2878 struct dc_desc *cur_rx; 2879 int i, total_len, rx_npkts; 2880 uint32_t rxstat; 2881 2882 DC_LOCK_ASSERT(sc); 2883 2884 ifp = sc->dc_ifp; 2885 rx_npkts = 0; 2886 2887 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, BUS_DMASYNC_POSTREAD | 2888 BUS_DMASYNC_POSTWRITE); 2889 for (i = sc->dc_cdata.dc_rx_prod; 2890 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0; 2891 DC_INC(i, DC_RX_LIST_CNT)) { 2892 #ifdef DEVICE_POLLING 2893 if (ifp->if_capenable & IFCAP_POLLING) { 2894 if (sc->rxcycles <= 0) 2895 break; 2896 sc->rxcycles--; 2897 } 2898 #endif 2899 cur_rx = &sc->dc_ldata.dc_rx_list[i]; 2900 rxstat = le32toh(cur_rx->dc_status); 2901 if ((rxstat & DC_RXSTAT_OWN) != 0) 2902 break; 2903 m = sc->dc_cdata.dc_rx_chain[i]; 2904 bus_dmamap_sync(sc->dc_rx_mtag, sc->dc_cdata.dc_rx_map[i], 2905 BUS_DMASYNC_POSTREAD); 2906 total_len = DC_RXBYTES(rxstat); 2907 rx_npkts++; 2908 2909 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2910 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2911 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2912 sc->dc_pnic_rx_bug_save = i; 2913 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) 2914 continue; 2915 dc_pnic_rx_bug_war(sc, i); 2916 rxstat = le32toh(cur_rx->dc_status); 2917 total_len = DC_RXBYTES(rxstat); 2918 } 2919 } 2920 2921 /* 2922 * If an error occurs, update stats, clear the 2923 * status word and leave the mbuf cluster in place: 2924 * it should simply get re-used next time this descriptor 2925 * comes up in the ring. However, don't report long 2926 * frames as errors since they could be vlans. 2927 */ 2928 if ((rxstat & DC_RXSTAT_RXERR)) { 2929 if (!(rxstat & DC_RXSTAT_GIANT) || 2930 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2931 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2932 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2933 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2934 if (rxstat & DC_RXSTAT_COLLSEEN) 2935 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1); 2936 dc_discard_rxbuf(sc, i); 2937 if (rxstat & DC_RXSTAT_CRCERR) 2938 continue; 2939 else { 2940 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2941 dc_init_locked(sc); 2942 return (rx_npkts); 2943 } 2944 } 2945 } 2946 2947 /* No errors; receive the packet. */ 2948 total_len -= ETHER_CRC_LEN; 2949 #ifdef __NO_STRICT_ALIGNMENT 2950 /* 2951 * On architectures without alignment problems we try to 2952 * allocate a new buffer for the receive ring, and pass up 2953 * the one where the packet is already, saving the expensive 2954 * copy done in m_devget(). 2955 * If we are on an architecture with alignment problems, or 2956 * if the allocation fails, then use m_devget and leave the 2957 * existing buffer in the receive ring. 2958 */ 2959 if (dc_newbuf(sc, i) != 0) { 2960 dc_discard_rxbuf(sc, i); 2961 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2962 continue; 2963 } 2964 m->m_pkthdr.rcvif = ifp; 2965 m->m_pkthdr.len = m->m_len = total_len; 2966 #else 2967 { 2968 struct mbuf *m0; 2969 2970 m0 = m_devget(mtod(m, char *), total_len, 2971 ETHER_ALIGN, ifp, NULL); 2972 dc_discard_rxbuf(sc, i); 2973 if (m0 == NULL) { 2974 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2975 continue; 2976 } 2977 m = m0; 2978 } 2979 #endif 2980 2981 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 2982 DC_UNLOCK(sc); 2983 (*ifp->if_input)(ifp, m); 2984 DC_LOCK(sc); 2985 } 2986 2987 sc->dc_cdata.dc_rx_prod = i; 2988 return (rx_npkts); 2989 } 2990 2991 /* 2992 * A frame was downloaded to the chip. It's safe for us to clean up 2993 * the list buffers. 2994 */ 2995 static void 2996 dc_txeof(struct dc_softc *sc) 2997 { 2998 struct dc_desc *cur_tx; 2999 struct ifnet *ifp; 3000 int idx, setup; 3001 uint32_t ctl, txstat; 3002 3003 if (sc->dc_cdata.dc_tx_cnt == 0) 3004 return; 3005 3006 ifp = sc->dc_ifp; 3007 3008 /* 3009 * Go through our tx list and free mbufs for those 3010 * frames that have been transmitted. 3011 */ 3012 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, BUS_DMASYNC_POSTREAD | 3013 BUS_DMASYNC_POSTWRITE); 3014 setup = 0; 3015 for (idx = sc->dc_cdata.dc_tx_cons; idx != sc->dc_cdata.dc_tx_prod; 3016 DC_INC(idx, DC_TX_LIST_CNT), sc->dc_cdata.dc_tx_cnt--) { 3017 cur_tx = &sc->dc_ldata.dc_tx_list[idx]; 3018 txstat = le32toh(cur_tx->dc_status); 3019 ctl = le32toh(cur_tx->dc_ctl); 3020 3021 if (txstat & DC_TXSTAT_OWN) 3022 break; 3023 3024 if (sc->dc_cdata.dc_tx_chain[idx] == NULL) 3025 continue; 3026 3027 if (ctl & DC_TXCTL_SETUP) { 3028 cur_tx->dc_ctl = htole32(ctl & ~DC_TXCTL_SETUP); 3029 setup++; 3030 bus_dmamap_sync(sc->dc_stag, sc->dc_smap, 3031 BUS_DMASYNC_POSTWRITE); 3032 /* 3033 * Yes, the PNIC is so brain damaged 3034 * that it will sometimes generate a TX 3035 * underrun error while DMAing the RX 3036 * filter setup frame. If we detect this, 3037 * we have to send the setup frame again, 3038 * or else the filter won't be programmed 3039 * correctly. 3040 */ 3041 if (DC_IS_PNIC(sc)) { 3042 if (txstat & DC_TXSTAT_ERRSUM) 3043 dc_setfilt(sc); 3044 } 3045 sc->dc_cdata.dc_tx_chain[idx] = NULL; 3046 continue; 3047 } 3048 3049 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) { 3050 /* 3051 * XXX: Why does my Xircom taunt me so? 3052 * For some reason it likes setting the CARRLOST flag 3053 * even when the carrier is there. wtf?!? 3054 * Who knows, but Conexant chips have the 3055 * same problem. Maybe they took lessons 3056 * from Xircom. 3057 */ 3058 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 3059 sc->dc_pmode == DC_PMODE_MII && 3060 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 3061 DC_TXSTAT_NOCARRIER))) 3062 txstat &= ~DC_TXSTAT_ERRSUM; 3063 } else { 3064 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 3065 sc->dc_pmode == DC_PMODE_MII && 3066 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 3067 DC_TXSTAT_NOCARRIER | DC_TXSTAT_CARRLOST))) 3068 txstat &= ~DC_TXSTAT_ERRSUM; 3069 } 3070 3071 if (txstat & DC_TXSTAT_ERRSUM) { 3072 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 3073 if (txstat & DC_TXSTAT_EXCESSCOLL) 3074 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1); 3075 if (txstat & DC_TXSTAT_LATECOLL) 3076 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1); 3077 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 3078 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3079 dc_init_locked(sc); 3080 return; 3081 } 3082 } else 3083 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 3084 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, (txstat & DC_TXSTAT_COLLCNT) >> 3); 3085 3086 bus_dmamap_sync(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx], 3087 BUS_DMASYNC_POSTWRITE); 3088 bus_dmamap_unload(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx]); 3089 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 3090 sc->dc_cdata.dc_tx_chain[idx] = NULL; 3091 } 3092 sc->dc_cdata.dc_tx_cons = idx; 3093 3094 if (sc->dc_cdata.dc_tx_cnt <= DC_TX_LIST_CNT - DC_TX_LIST_RSVD) { 3095 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3096 if (sc->dc_cdata.dc_tx_cnt == 0) 3097 sc->dc_wdog_timer = 0; 3098 } 3099 if (setup > 0) 3100 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, 3101 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3102 } 3103 3104 static void 3105 dc_tick(void *xsc) 3106 { 3107 struct dc_softc *sc; 3108 struct mii_data *mii; 3109 struct ifnet *ifp; 3110 uint32_t r; 3111 3112 sc = xsc; 3113 DC_LOCK_ASSERT(sc); 3114 ifp = sc->dc_ifp; 3115 mii = device_get_softc(sc->dc_miibus); 3116 3117 /* 3118 * Reclaim transmitted frames for controllers that do 3119 * not generate TX completion interrupt for every frame. 3120 */ 3121 if (sc->dc_flags & DC_TX_USE_TX_INTR) 3122 dc_txeof(sc); 3123 3124 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 3125 if (sc->dc_flags & DC_21143_NWAY) { 3126 r = CSR_READ_4(sc, DC_10BTSTAT); 3127 if (IFM_SUBTYPE(mii->mii_media_active) == 3128 IFM_100_TX && (r & DC_TSTAT_LS100)) { 3129 sc->dc_link = 0; 3130 mii_mediachg(mii); 3131 } 3132 if (IFM_SUBTYPE(mii->mii_media_active) == 3133 IFM_10_T && (r & DC_TSTAT_LS10)) { 3134 sc->dc_link = 0; 3135 mii_mediachg(mii); 3136 } 3137 if (sc->dc_link == 0) 3138 mii_tick(mii); 3139 } else { 3140 /* 3141 * For NICs which never report DC_RXSTATE_WAIT, we 3142 * have to bite the bullet... 3143 */ 3144 if ((DC_HAS_BROKEN_RXSTATE(sc) || (CSR_READ_4(sc, 3145 DC_ISR) & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT) && 3146 sc->dc_cdata.dc_tx_cnt == 0) 3147 mii_tick(mii); 3148 } 3149 } else 3150 mii_tick(mii); 3151 3152 /* 3153 * When the init routine completes, we expect to be able to send 3154 * packets right away, and in fact the network code will send a 3155 * gratuitous ARP the moment the init routine marks the interface 3156 * as running. However, even though the MAC may have been initialized, 3157 * there may be a delay of a few seconds before the PHY completes 3158 * autonegotiation and the link is brought up. Any transmissions 3159 * made during that delay will be lost. Dealing with this is tricky: 3160 * we can't just pause in the init routine while waiting for the 3161 * PHY to come ready since that would bring the whole system to 3162 * a screeching halt for several seconds. 3163 * 3164 * What we do here is prevent the TX start routine from sending 3165 * any packets until a link has been established. After the 3166 * interface has been initialized, the tick routine will poll 3167 * the state of the PHY until the IFM_ACTIVE flag is set. Until 3168 * that time, packets will stay in the send queue, and once the 3169 * link comes up, they will be flushed out to the wire. 3170 */ 3171 if (sc->dc_link != 0 && !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3172 dc_start_locked(ifp); 3173 3174 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 3175 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3176 else 3177 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3178 } 3179 3180 /* 3181 * A transmit underrun has occurred. Back off the transmit threshold, 3182 * or switch to store and forward mode if we have to. 3183 */ 3184 static void 3185 dc_tx_underrun(struct dc_softc *sc) 3186 { 3187 uint32_t netcfg, isr; 3188 int i, reinit; 3189 3190 reinit = 0; 3191 netcfg = CSR_READ_4(sc, DC_NETCFG); 3192 device_printf(sc->dc_dev, "TX underrun -- "); 3193 if ((sc->dc_flags & DC_TX_STORENFWD) == 0) { 3194 if (sc->dc_txthresh + DC_TXTHRESH_INC > DC_TXTHRESH_MAX) { 3195 printf("using store and forward mode\n"); 3196 netcfg |= DC_NETCFG_STORENFWD; 3197 } else { 3198 printf("increasing TX threshold\n"); 3199 sc->dc_txthresh += DC_TXTHRESH_INC; 3200 netcfg &= ~DC_NETCFG_TX_THRESH; 3201 netcfg |= sc->dc_txthresh; 3202 } 3203 3204 if (DC_IS_INTEL(sc)) { 3205 /* 3206 * The real 21143 requires that the transmitter be idle 3207 * in order to change the transmit threshold or store 3208 * and forward state. 3209 */ 3210 CSR_WRITE_4(sc, DC_NETCFG, netcfg & ~DC_NETCFG_TX_ON); 3211 3212 for (i = 0; i < DC_TIMEOUT; i++) { 3213 isr = CSR_READ_4(sc, DC_ISR); 3214 if (isr & DC_ISR_TX_IDLE) 3215 break; 3216 DELAY(10); 3217 } 3218 if (i == DC_TIMEOUT) { 3219 device_printf(sc->dc_dev, 3220 "%s: failed to force tx to idle state\n", 3221 __func__); 3222 reinit++; 3223 } 3224 } 3225 } else { 3226 printf("resetting\n"); 3227 reinit++; 3228 } 3229 3230 if (reinit == 0) { 3231 CSR_WRITE_4(sc, DC_NETCFG, netcfg); 3232 if (DC_IS_INTEL(sc)) 3233 CSR_WRITE_4(sc, DC_NETCFG, netcfg | DC_NETCFG_TX_ON); 3234 } else { 3235 sc->dc_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3236 dc_init_locked(sc); 3237 } 3238 } 3239 3240 #ifdef DEVICE_POLLING 3241 static poll_handler_t dc_poll; 3242 3243 static int 3244 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 3245 { 3246 struct dc_softc *sc = ifp->if_softc; 3247 int rx_npkts = 0; 3248 3249 DC_LOCK(sc); 3250 3251 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3252 DC_UNLOCK(sc); 3253 return (rx_npkts); 3254 } 3255 3256 sc->rxcycles = count; 3257 rx_npkts = dc_rxeof(sc); 3258 dc_txeof(sc); 3259 if (!IFQ_IS_EMPTY(&ifp->if_snd) && 3260 !(ifp->if_drv_flags & IFF_DRV_OACTIVE)) 3261 dc_start_locked(ifp); 3262 3263 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 3264 uint32_t status; 3265 3266 status = CSR_READ_4(sc, DC_ISR); 3267 status &= (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF | 3268 DC_ISR_TX_NOBUF | DC_ISR_TX_IDLE | DC_ISR_TX_UNDERRUN | 3269 DC_ISR_BUS_ERR); 3270 if (!status) { 3271 DC_UNLOCK(sc); 3272 return (rx_npkts); 3273 } 3274 /* ack what we have */ 3275 CSR_WRITE_4(sc, DC_ISR, status); 3276 3277 if (status & (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF)) { 3278 uint32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 3279 if_inc_counter(ifp, IFCOUNTER_IERRORS, (r & 0xffff) + ((r >> 17) & 0x7ff)); 3280 3281 if (dc_rx_resync(sc)) 3282 dc_rxeof(sc); 3283 } 3284 /* restart transmit unit if necessary */ 3285 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 3286 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3287 3288 if (status & DC_ISR_TX_UNDERRUN) 3289 dc_tx_underrun(sc); 3290 3291 if (status & DC_ISR_BUS_ERR) { 3292 if_printf(ifp, "%s: bus error\n", __func__); 3293 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3294 dc_init_locked(sc); 3295 } 3296 } 3297 DC_UNLOCK(sc); 3298 return (rx_npkts); 3299 } 3300 #endif /* DEVICE_POLLING */ 3301 3302 static void 3303 dc_intr(void *arg) 3304 { 3305 struct dc_softc *sc; 3306 struct ifnet *ifp; 3307 uint32_t r, status; 3308 int n; 3309 3310 sc = arg; 3311 3312 if (sc->suspended) 3313 return; 3314 3315 DC_LOCK(sc); 3316 status = CSR_READ_4(sc, DC_ISR); 3317 if (status == 0xFFFFFFFF || (status & DC_INTRS) == 0) { 3318 DC_UNLOCK(sc); 3319 return; 3320 } 3321 ifp = sc->dc_ifp; 3322 #ifdef DEVICE_POLLING 3323 if (ifp->if_capenable & IFCAP_POLLING) { 3324 DC_UNLOCK(sc); 3325 return; 3326 } 3327 #endif 3328 /* Disable interrupts. */ 3329 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3330 3331 for (n = 16; n > 0; n--) { 3332 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 3333 break; 3334 /* Ack interrupts. */ 3335 CSR_WRITE_4(sc, DC_ISR, status); 3336 3337 if (status & DC_ISR_RX_OK) { 3338 if (dc_rxeof(sc) == 0) { 3339 while (dc_rx_resync(sc)) 3340 dc_rxeof(sc); 3341 } 3342 } 3343 3344 if (status & (DC_ISR_TX_OK | DC_ISR_TX_NOBUF)) 3345 dc_txeof(sc); 3346 3347 if (status & DC_ISR_TX_IDLE) { 3348 dc_txeof(sc); 3349 if (sc->dc_cdata.dc_tx_cnt) { 3350 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3351 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3352 } 3353 } 3354 3355 if (status & DC_ISR_TX_UNDERRUN) 3356 dc_tx_underrun(sc); 3357 3358 if ((status & DC_ISR_RX_WATDOGTIMEO) 3359 || (status & DC_ISR_RX_NOBUF)) { 3360 r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 3361 if_inc_counter(ifp, IFCOUNTER_IERRORS, (r & 0xffff) + ((r >> 17) & 0x7ff)); 3362 if (dc_rxeof(sc) == 0) { 3363 while (dc_rx_resync(sc)) 3364 dc_rxeof(sc); 3365 } 3366 } 3367 3368 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3369 dc_start_locked(ifp); 3370 3371 if (status & DC_ISR_BUS_ERR) { 3372 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3373 dc_init_locked(sc); 3374 DC_UNLOCK(sc); 3375 return; 3376 } 3377 status = CSR_READ_4(sc, DC_ISR); 3378 if (status == 0xFFFFFFFF || (status & DC_INTRS) == 0) 3379 break; 3380 } 3381 3382 /* Re-enable interrupts. */ 3383 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3384 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3385 3386 DC_UNLOCK(sc); 3387 } 3388 3389 /* 3390 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 3391 * pointers to the fragment pointers. 3392 */ 3393 static int 3394 dc_encap(struct dc_softc *sc, struct mbuf **m_head) 3395 { 3396 bus_dma_segment_t segs[DC_MAXFRAGS]; 3397 bus_dmamap_t map; 3398 struct dc_desc *f; 3399 struct mbuf *m; 3400 int cur, defragged, error, first, frag, i, idx, nseg; 3401 3402 m = NULL; 3403 defragged = 0; 3404 if (sc->dc_flags & DC_TX_COALESCE && 3405 ((*m_head)->m_next != NULL || sc->dc_flags & DC_TX_ALIGN)) { 3406 m = m_defrag(*m_head, M_NOWAIT); 3407 defragged = 1; 3408 } else { 3409 /* 3410 * Count the number of frags in this chain to see if we 3411 * need to m_collapse. Since the descriptor list is shared 3412 * by all packets, we'll m_collapse long chains so that they 3413 * do not use up the entire list, even if they would fit. 3414 */ 3415 i = 0; 3416 for (m = *m_head; m != NULL; m = m->m_next) 3417 i++; 3418 if (i > DC_TX_LIST_CNT / 4 || 3419 DC_TX_LIST_CNT - i + sc->dc_cdata.dc_tx_cnt <= 3420 DC_TX_LIST_RSVD) { 3421 m = m_collapse(*m_head, M_NOWAIT, DC_MAXFRAGS); 3422 defragged = 1; 3423 } 3424 } 3425 if (defragged != 0) { 3426 if (m == NULL) { 3427 m_freem(*m_head); 3428 *m_head = NULL; 3429 return (ENOBUFS); 3430 } 3431 *m_head = m; 3432 } 3433 3434 idx = sc->dc_cdata.dc_tx_prod; 3435 error = bus_dmamap_load_mbuf_sg(sc->dc_tx_mtag, 3436 sc->dc_cdata.dc_tx_map[idx], *m_head, segs, &nseg, 0); 3437 if (error == EFBIG) { 3438 if (defragged != 0 || (m = m_collapse(*m_head, M_NOWAIT, 3439 DC_MAXFRAGS)) == NULL) { 3440 m_freem(*m_head); 3441 *m_head = NULL; 3442 return (defragged != 0 ? error : ENOBUFS); 3443 } 3444 *m_head = m; 3445 error = bus_dmamap_load_mbuf_sg(sc->dc_tx_mtag, 3446 sc->dc_cdata.dc_tx_map[idx], *m_head, segs, &nseg, 0); 3447 if (error != 0) { 3448 m_freem(*m_head); 3449 *m_head = NULL; 3450 return (error); 3451 } 3452 } else if (error != 0) 3453 return (error); 3454 KASSERT(nseg <= DC_MAXFRAGS, 3455 ("%s: wrong number of segments (%d)", __func__, nseg)); 3456 if (nseg == 0) { 3457 m_freem(*m_head); 3458 *m_head = NULL; 3459 return (EIO); 3460 } 3461 3462 /* Check descriptor overruns. */ 3463 if (sc->dc_cdata.dc_tx_cnt + nseg > DC_TX_LIST_CNT - DC_TX_LIST_RSVD) { 3464 bus_dmamap_unload(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx]); 3465 return (ENOBUFS); 3466 } 3467 bus_dmamap_sync(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx], 3468 BUS_DMASYNC_PREWRITE); 3469 3470 first = cur = frag = sc->dc_cdata.dc_tx_prod; 3471 for (i = 0; i < nseg; i++) { 3472 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) && 3473 (frag == (DC_TX_LIST_CNT - 1)) && 3474 (first != sc->dc_cdata.dc_tx_first)) { 3475 bus_dmamap_unload(sc->dc_tx_mtag, 3476 sc->dc_cdata.dc_tx_map[first]); 3477 m_freem(*m_head); 3478 *m_head = NULL; 3479 return (ENOBUFS); 3480 } 3481 3482 f = &sc->dc_ldata.dc_tx_list[frag]; 3483 f->dc_ctl = htole32(DC_TXCTL_TLINK | segs[i].ds_len); 3484 if (i == 0) { 3485 f->dc_status = 0; 3486 f->dc_ctl |= htole32(DC_TXCTL_FIRSTFRAG); 3487 } else 3488 f->dc_status = htole32(DC_TXSTAT_OWN); 3489 f->dc_data = htole32(DC_ADDR_LO(segs[i].ds_addr)); 3490 cur = frag; 3491 DC_INC(frag, DC_TX_LIST_CNT); 3492 } 3493 3494 sc->dc_cdata.dc_tx_prod = frag; 3495 sc->dc_cdata.dc_tx_cnt += nseg; 3496 sc->dc_cdata.dc_tx_chain[cur] = *m_head; 3497 sc->dc_ldata.dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_LASTFRAG); 3498 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 3499 sc->dc_ldata.dc_tx_list[first].dc_ctl |= 3500 htole32(DC_TXCTL_FINT); 3501 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 3502 sc->dc_ldata.dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3503 if (sc->dc_flags & DC_TX_USE_TX_INTR && 3504 ++sc->dc_cdata.dc_tx_pkts >= 8) { 3505 sc->dc_cdata.dc_tx_pkts = 0; 3506 sc->dc_ldata.dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3507 } 3508 sc->dc_ldata.dc_tx_list[first].dc_status = htole32(DC_TXSTAT_OWN); 3509 3510 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, 3511 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3512 3513 /* 3514 * Swap the last and the first dmamaps to ensure the map for 3515 * this transmission is placed at the last descriptor. 3516 */ 3517 map = sc->dc_cdata.dc_tx_map[cur]; 3518 sc->dc_cdata.dc_tx_map[cur] = sc->dc_cdata.dc_tx_map[first]; 3519 sc->dc_cdata.dc_tx_map[first] = map; 3520 3521 return (0); 3522 } 3523 3524 static void 3525 dc_start(struct ifnet *ifp) 3526 { 3527 struct dc_softc *sc; 3528 3529 sc = ifp->if_softc; 3530 DC_LOCK(sc); 3531 dc_start_locked(ifp); 3532 DC_UNLOCK(sc); 3533 } 3534 3535 /* 3536 * Main transmit routine 3537 * To avoid having to do mbuf copies, we put pointers to the mbuf data 3538 * regions directly in the transmit lists. We also save a copy of the 3539 * pointers since the transmit list fragment pointers are physical 3540 * addresses. 3541 */ 3542 static void 3543 dc_start_locked(struct ifnet *ifp) 3544 { 3545 struct dc_softc *sc; 3546 struct mbuf *m_head; 3547 int queued; 3548 3549 sc = ifp->if_softc; 3550 3551 DC_LOCK_ASSERT(sc); 3552 3553 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 3554 IFF_DRV_RUNNING || sc->dc_link == 0) 3555 return; 3556 3557 sc->dc_cdata.dc_tx_first = sc->dc_cdata.dc_tx_prod; 3558 3559 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 3560 /* 3561 * If there's no way we can send any packets, return now. 3562 */ 3563 if (sc->dc_cdata.dc_tx_cnt > DC_TX_LIST_CNT - DC_TX_LIST_RSVD) { 3564 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3565 break; 3566 } 3567 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 3568 if (m_head == NULL) 3569 break; 3570 3571 if (dc_encap(sc, &m_head)) { 3572 if (m_head == NULL) 3573 break; 3574 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3575 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3576 break; 3577 } 3578 3579 queued++; 3580 /* 3581 * If there's a BPF listener, bounce a copy of this frame 3582 * to him. 3583 */ 3584 BPF_MTAP(ifp, m_head); 3585 } 3586 3587 if (queued > 0) { 3588 /* Transmit */ 3589 if (!(sc->dc_flags & DC_TX_POLL)) 3590 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3591 3592 /* 3593 * Set a timeout in case the chip goes out to lunch. 3594 */ 3595 sc->dc_wdog_timer = 5; 3596 } 3597 } 3598 3599 static void 3600 dc_init(void *xsc) 3601 { 3602 struct dc_softc *sc = xsc; 3603 3604 DC_LOCK(sc); 3605 dc_init_locked(sc); 3606 DC_UNLOCK(sc); 3607 } 3608 3609 static void 3610 dc_init_locked(struct dc_softc *sc) 3611 { 3612 struct ifnet *ifp = sc->dc_ifp; 3613 struct mii_data *mii; 3614 struct ifmedia *ifm; 3615 3616 DC_LOCK_ASSERT(sc); 3617 3618 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3619 return; 3620 3621 mii = device_get_softc(sc->dc_miibus); 3622 3623 /* 3624 * Cancel pending I/O and free all RX/TX buffers. 3625 */ 3626 dc_stop(sc); 3627 dc_reset(sc); 3628 if (DC_IS_INTEL(sc)) { 3629 ifm = &mii->mii_media; 3630 dc_apply_fixup(sc, ifm->ifm_media); 3631 } 3632 3633 /* 3634 * Set cache alignment and burst length. 3635 */ 3636 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc) || DC_IS_ULI(sc)) 3637 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3638 else 3639 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME | DC_BUSCTL_MRLE); 3640 /* 3641 * Evenly share the bus between receive and transmit process. 3642 */ 3643 if (DC_IS_INTEL(sc)) 3644 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3645 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3646 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3647 } else { 3648 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3649 } 3650 if (sc->dc_flags & DC_TX_POLL) 3651 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3652 switch(sc->dc_cachesize) { 3653 case 32: 3654 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3655 break; 3656 case 16: 3657 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3658 break; 3659 case 8: 3660 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3661 break; 3662 case 0: 3663 default: 3664 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3665 break; 3666 } 3667 3668 if (sc->dc_flags & DC_TX_STORENFWD) 3669 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3670 else { 3671 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3672 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3673 } else { 3674 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3675 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3676 } 3677 } 3678 3679 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3680 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3681 3682 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3683 /* 3684 * The app notes for the 98713 and 98715A say that 3685 * in order to have the chips operate properly, a magic 3686 * number must be written to CSR16. Macronix does not 3687 * document the meaning of these bits so there's no way 3688 * to know exactly what they do. The 98713 has a magic 3689 * number all its own; the rest all use a different one. 3690 */ 3691 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3692 if (sc->dc_type == DC_TYPE_98713) 3693 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3694 else 3695 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3696 } 3697 3698 if (DC_IS_XIRCOM(sc)) { 3699 /* 3700 * setup General Purpose Port mode and data so the tulip 3701 * can talk to the MII. 3702 */ 3703 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3704 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3705 DELAY(10); 3706 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3707 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3708 DELAY(10); 3709 } 3710 3711 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3712 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3713 3714 /* Init circular RX list. */ 3715 if (dc_list_rx_init(sc) == ENOBUFS) { 3716 device_printf(sc->dc_dev, 3717 "initialization failed: no memory for rx buffers\n"); 3718 dc_stop(sc); 3719 return; 3720 } 3721 3722 /* 3723 * Init TX descriptors. 3724 */ 3725 dc_list_tx_init(sc); 3726 3727 /* 3728 * Load the address of the RX list. 3729 */ 3730 CSR_WRITE_4(sc, DC_RXADDR, DC_RXDESC(sc, 0)); 3731 CSR_WRITE_4(sc, DC_TXADDR, DC_TXDESC(sc, 0)); 3732 3733 /* 3734 * Enable interrupts. 3735 */ 3736 #ifdef DEVICE_POLLING 3737 /* 3738 * ... but only if we are not polling, and make sure they are off in 3739 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3740 * after a reset. 3741 */ 3742 if (ifp->if_capenable & IFCAP_POLLING) 3743 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3744 else 3745 #endif 3746 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3747 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3748 3749 /* Initialize TX jabber and RX watchdog timer. */ 3750 if (DC_IS_ULI(sc)) 3751 CSR_WRITE_4(sc, DC_WATCHDOG, DC_WDOG_JABBERCLK | 3752 DC_WDOG_HOSTUNJAB); 3753 3754 /* Enable transmitter. */ 3755 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3756 3757 /* 3758 * If this is an Intel 21143 and we're not using the 3759 * MII port, program the LED control pins so we get 3760 * link and activity indications. 3761 */ 3762 if (sc->dc_flags & DC_TULIP_LEDS) { 3763 CSR_WRITE_4(sc, DC_WATCHDOG, 3764 DC_WDOG_CTLWREN | DC_WDOG_LINK | DC_WDOG_ACTIVITY); 3765 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3766 } 3767 3768 /* 3769 * Load the RX/multicast filter. We do this sort of late 3770 * because the filter programming scheme on the 21143 and 3771 * some clones requires DMAing a setup frame via the TX 3772 * engine, and we need the transmitter enabled for that. 3773 */ 3774 dc_setfilt(sc); 3775 3776 /* Enable receiver. */ 3777 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3778 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3779 3780 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3781 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3782 3783 dc_ifmedia_upd_locked(sc); 3784 3785 /* Clear missed frames and overflow counter. */ 3786 CSR_READ_4(sc, DC_FRAMESDISCARDED); 3787 3788 /* Don't start the ticker if this is a homePNA link. */ 3789 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) 3790 sc->dc_link = 1; 3791 else { 3792 if (sc->dc_flags & DC_21143_NWAY) 3793 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3794 else 3795 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3796 } 3797 3798 sc->dc_wdog_timer = 0; 3799 callout_reset(&sc->dc_wdog_ch, hz, dc_watchdog, sc); 3800 } 3801 3802 /* 3803 * Set media options. 3804 */ 3805 static int 3806 dc_ifmedia_upd(struct ifnet *ifp) 3807 { 3808 struct dc_softc *sc; 3809 int error; 3810 3811 sc = ifp->if_softc; 3812 DC_LOCK(sc); 3813 error = dc_ifmedia_upd_locked(sc); 3814 DC_UNLOCK(sc); 3815 return (error); 3816 } 3817 3818 static int 3819 dc_ifmedia_upd_locked(struct dc_softc *sc) 3820 { 3821 struct mii_data *mii; 3822 struct ifmedia *ifm; 3823 int error; 3824 3825 DC_LOCK_ASSERT(sc); 3826 3827 sc->dc_link = 0; 3828 mii = device_get_softc(sc->dc_miibus); 3829 error = mii_mediachg(mii); 3830 if (error == 0) { 3831 ifm = &mii->mii_media; 3832 if (DC_IS_INTEL(sc)) 3833 dc_setcfg(sc, ifm->ifm_media); 3834 else if (DC_IS_DAVICOM(sc) && 3835 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) 3836 dc_setcfg(sc, ifm->ifm_media); 3837 } 3838 3839 return (error); 3840 } 3841 3842 /* 3843 * Report current media status. 3844 */ 3845 static void 3846 dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3847 { 3848 struct dc_softc *sc; 3849 struct mii_data *mii; 3850 struct ifmedia *ifm; 3851 3852 sc = ifp->if_softc; 3853 mii = device_get_softc(sc->dc_miibus); 3854 DC_LOCK(sc); 3855 mii_pollstat(mii); 3856 ifm = &mii->mii_media; 3857 if (DC_IS_DAVICOM(sc)) { 3858 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 3859 ifmr->ifm_active = ifm->ifm_media; 3860 ifmr->ifm_status = 0; 3861 DC_UNLOCK(sc); 3862 return; 3863 } 3864 } 3865 ifmr->ifm_active = mii->mii_media_active; 3866 ifmr->ifm_status = mii->mii_media_status; 3867 DC_UNLOCK(sc); 3868 } 3869 3870 static int 3871 dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3872 { 3873 struct dc_softc *sc = ifp->if_softc; 3874 struct ifreq *ifr = (struct ifreq *)data; 3875 struct mii_data *mii; 3876 int error = 0; 3877 3878 switch (command) { 3879 case SIOCSIFFLAGS: 3880 DC_LOCK(sc); 3881 if (ifp->if_flags & IFF_UP) { 3882 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) & 3883 (IFF_PROMISC | IFF_ALLMULTI); 3884 3885 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3886 if (need_setfilt) 3887 dc_setfilt(sc); 3888 } else { 3889 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3890 dc_init_locked(sc); 3891 } 3892 } else { 3893 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3894 dc_stop(sc); 3895 } 3896 sc->dc_if_flags = ifp->if_flags; 3897 DC_UNLOCK(sc); 3898 break; 3899 case SIOCADDMULTI: 3900 case SIOCDELMULTI: 3901 DC_LOCK(sc); 3902 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3903 dc_setfilt(sc); 3904 DC_UNLOCK(sc); 3905 break; 3906 case SIOCGIFMEDIA: 3907 case SIOCSIFMEDIA: 3908 mii = device_get_softc(sc->dc_miibus); 3909 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3910 break; 3911 case SIOCSIFCAP: 3912 #ifdef DEVICE_POLLING 3913 if (ifr->ifr_reqcap & IFCAP_POLLING && 3914 !(ifp->if_capenable & IFCAP_POLLING)) { 3915 error = ether_poll_register(dc_poll, ifp); 3916 if (error) 3917 return(error); 3918 DC_LOCK(sc); 3919 /* Disable interrupts */ 3920 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3921 ifp->if_capenable |= IFCAP_POLLING; 3922 DC_UNLOCK(sc); 3923 return (error); 3924 } 3925 if (!(ifr->ifr_reqcap & IFCAP_POLLING) && 3926 ifp->if_capenable & IFCAP_POLLING) { 3927 error = ether_poll_deregister(ifp); 3928 /* Enable interrupts. */ 3929 DC_LOCK(sc); 3930 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3931 ifp->if_capenable &= ~IFCAP_POLLING; 3932 DC_UNLOCK(sc); 3933 return (error); 3934 } 3935 #endif /* DEVICE_POLLING */ 3936 break; 3937 default: 3938 error = ether_ioctl(ifp, command, data); 3939 break; 3940 } 3941 3942 return (error); 3943 } 3944 3945 static void 3946 dc_watchdog(void *xsc) 3947 { 3948 struct dc_softc *sc = xsc; 3949 struct ifnet *ifp; 3950 3951 DC_LOCK_ASSERT(sc); 3952 3953 if (sc->dc_wdog_timer == 0 || --sc->dc_wdog_timer != 0) { 3954 callout_reset(&sc->dc_wdog_ch, hz, dc_watchdog, sc); 3955 return; 3956 } 3957 3958 ifp = sc->dc_ifp; 3959 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 3960 device_printf(sc->dc_dev, "watchdog timeout\n"); 3961 3962 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3963 dc_init_locked(sc); 3964 3965 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3966 dc_start_locked(ifp); 3967 } 3968 3969 /* 3970 * Stop the adapter and free any mbufs allocated to the 3971 * RX and TX lists. 3972 */ 3973 static void 3974 dc_stop(struct dc_softc *sc) 3975 { 3976 struct ifnet *ifp; 3977 struct dc_list_data *ld; 3978 struct dc_chain_data *cd; 3979 int i; 3980 uint32_t ctl, netcfg; 3981 3982 DC_LOCK_ASSERT(sc); 3983 3984 ifp = sc->dc_ifp; 3985 ld = &sc->dc_ldata; 3986 cd = &sc->dc_cdata; 3987 3988 callout_stop(&sc->dc_stat_ch); 3989 callout_stop(&sc->dc_wdog_ch); 3990 sc->dc_wdog_timer = 0; 3991 sc->dc_link = 0; 3992 3993 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3994 3995 netcfg = CSR_READ_4(sc, DC_NETCFG); 3996 if (netcfg & (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)) 3997 CSR_WRITE_4(sc, DC_NETCFG, 3998 netcfg & ~(DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)); 3999 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 4000 /* Wait the completion of TX/RX SM. */ 4001 if (netcfg & (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)) 4002 dc_netcfg_wait(sc); 4003 4004 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 4005 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 4006 4007 /* 4008 * Free data in the RX lists. 4009 */ 4010 for (i = 0; i < DC_RX_LIST_CNT; i++) { 4011 if (cd->dc_rx_chain[i] != NULL) { 4012 bus_dmamap_sync(sc->dc_rx_mtag, 4013 cd->dc_rx_map[i], BUS_DMASYNC_POSTREAD); 4014 bus_dmamap_unload(sc->dc_rx_mtag, 4015 cd->dc_rx_map[i]); 4016 m_freem(cd->dc_rx_chain[i]); 4017 cd->dc_rx_chain[i] = NULL; 4018 } 4019 } 4020 bzero(ld->dc_rx_list, DC_RX_LIST_SZ); 4021 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, 4022 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4023 4024 /* 4025 * Free the TX list buffers. 4026 */ 4027 for (i = 0; i < DC_TX_LIST_CNT; i++) { 4028 if (cd->dc_tx_chain[i] != NULL) { 4029 ctl = le32toh(ld->dc_tx_list[i].dc_ctl); 4030 if (ctl & DC_TXCTL_SETUP) { 4031 bus_dmamap_sync(sc->dc_stag, sc->dc_smap, 4032 BUS_DMASYNC_POSTWRITE); 4033 } else { 4034 bus_dmamap_sync(sc->dc_tx_mtag, 4035 cd->dc_tx_map[i], BUS_DMASYNC_POSTWRITE); 4036 bus_dmamap_unload(sc->dc_tx_mtag, 4037 cd->dc_tx_map[i]); 4038 m_freem(cd->dc_tx_chain[i]); 4039 } 4040 cd->dc_tx_chain[i] = NULL; 4041 } 4042 } 4043 bzero(ld->dc_tx_list, DC_TX_LIST_SZ); 4044 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, 4045 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4046 } 4047 4048 /* 4049 * Device suspend routine. Stop the interface and save some PCI 4050 * settings in case the BIOS doesn't restore them properly on 4051 * resume. 4052 */ 4053 static int 4054 dc_suspend(device_t dev) 4055 { 4056 struct dc_softc *sc; 4057 4058 sc = device_get_softc(dev); 4059 DC_LOCK(sc); 4060 dc_stop(sc); 4061 sc->suspended = 1; 4062 DC_UNLOCK(sc); 4063 4064 return (0); 4065 } 4066 4067 /* 4068 * Device resume routine. Restore some PCI settings in case the BIOS 4069 * doesn't, re-enable busmastering, and restart the interface if 4070 * appropriate. 4071 */ 4072 static int 4073 dc_resume(device_t dev) 4074 { 4075 struct dc_softc *sc; 4076 struct ifnet *ifp; 4077 4078 sc = device_get_softc(dev); 4079 ifp = sc->dc_ifp; 4080 4081 /* reinitialize interface if necessary */ 4082 DC_LOCK(sc); 4083 if (ifp->if_flags & IFF_UP) 4084 dc_init_locked(sc); 4085 4086 sc->suspended = 0; 4087 DC_UNLOCK(sc); 4088 4089 return (0); 4090 } 4091 4092 /* 4093 * Stop all chip I/O so that the kernel's probe routines don't 4094 * get confused by errant DMAs when rebooting. 4095 */ 4096 static int 4097 dc_shutdown(device_t dev) 4098 { 4099 struct dc_softc *sc; 4100 4101 sc = device_get_softc(dev); 4102 4103 DC_LOCK(sc); 4104 dc_stop(sc); 4105 DC_UNLOCK(sc); 4106 4107 return (0); 4108 } 4109 4110 static int 4111 dc_check_multiport(struct dc_softc *sc) 4112 { 4113 struct dc_softc *dsc; 4114 devclass_t dc; 4115 device_t child; 4116 uint8_t *eaddr; 4117 int unit; 4118 4119 dc = devclass_find("dc"); 4120 for (unit = 0; unit < devclass_get_maxunit(dc); unit++) { 4121 child = devclass_get_device(dc, unit); 4122 if (child == NULL) 4123 continue; 4124 if (child == sc->dc_dev) 4125 continue; 4126 if (device_get_parent(child) != device_get_parent(sc->dc_dev)) 4127 continue; 4128 if (unit > device_get_unit(sc->dc_dev)) 4129 continue; 4130 if (device_is_attached(child) == 0) 4131 continue; 4132 dsc = device_get_softc(child); 4133 device_printf(sc->dc_dev, 4134 "Using station address of %s as base\n", 4135 device_get_nameunit(child)); 4136 bcopy(dsc->dc_eaddr, sc->dc_eaddr, ETHER_ADDR_LEN); 4137 eaddr = (uint8_t *)sc->dc_eaddr; 4138 eaddr[5]++; 4139 /* Prepare SROM to parse again. */ 4140 if (DC_IS_INTEL(sc) && dsc->dc_srom != NULL && 4141 sc->dc_romwidth != 0) { 4142 free(sc->dc_srom, M_DEVBUF); 4143 sc->dc_romwidth = dsc->dc_romwidth; 4144 sc->dc_srom = malloc(DC_ROM_SIZE(sc->dc_romwidth), 4145 M_DEVBUF, M_NOWAIT); 4146 if (sc->dc_srom == NULL) { 4147 device_printf(sc->dc_dev, 4148 "Could not allocate SROM buffer\n"); 4149 return (ENOMEM); 4150 } 4151 bcopy(dsc->dc_srom, sc->dc_srom, 4152 DC_ROM_SIZE(sc->dc_romwidth)); 4153 } 4154 return (0); 4155 } 4156 return (ENOENT); 4157 } 4158