1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 */ 34 35 /* 36 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 37 * series chips and several workalikes including the following: 38 * 39 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 40 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 41 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 42 * ASIX Electronics AX88140A (www.asix.com.tw) 43 * ASIX Electronics AX88141 (www.asix.com.tw) 44 * ADMtek AL981 (www.admtek.com.tw) 45 * ADMtek AN985 (www.admtek.com.tw) 46 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 47 * Accton EN1217 (www.accton.com) 48 * 49 * Datasheets for the 21143 are available at developer.intel.com. 50 * Datasheets for the clone parts can be found at their respective sites. 51 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 52 * The PNIC II is essentially a Macronix 98715A chip; the only difference 53 * worth noting is that its multicast hash table is only 128 bits wide 54 * instead of 512. 55 * 56 * Written by Bill Paul <wpaul@ee.columbia.edu> 57 * Electrical Engineering Department 58 * Columbia University, New York City 59 */ 60 61 /* 62 * The Intel 21143 is the successor to the DEC 21140. It is basically 63 * the same as the 21140 but with a few new features. The 21143 supports 64 * three kinds of media attachments: 65 * 66 * o MII port, for 10Mbps and 100Mbps support and NWAY 67 * autonegotiation provided by an external PHY. 68 * o SYM port, for symbol mode 100Mbps support. 69 * o 10baseT port. 70 * o AUI/BNC port. 71 * 72 * The 100Mbps SYM port and 10baseT port can be used together in 73 * combination with the internal NWAY support to create a 10/100 74 * autosensing configuration. 75 * 76 * Knowing which media is available on a given card is tough: you're 77 * supposed to go slogging through the EEPROM looking for media 78 * description structures. Unfortunately, some card vendors that use 79 * the 21143 don't obey the DEC SROM spec correctly, which means that 80 * what you find in the EEPROM may not agree with reality. Fortunately, 81 * the 21143 provides us a way to get around this issue: lurking in 82 * PCI configuration space is the Configuration Wake-Up Command Register. 83 * This register is loaded with a value from the EEPROM when wake on LAN 84 * mode is enabled; this value tells us quite clearly what kind of media 85 * is attached to the NIC. The main purpose of this register is to tell 86 * the NIC what media to scan when in wake on LAN mode, however by 87 * forcibly enabling wake on LAN mode, we can use to learn what kind of 88 * media a given NIC has available and adapt ourselves accordingly. 89 * 90 * Of course, if the media description blocks in the EEPROM are bogus. 91 * what are the odds that the CWUC aren't bogus as well, right? Well, 92 * the CWUC value is more likely to be correct since wake on LAN mode 93 * won't work correctly without it, and wake on LAN is a big selling 94 * point these days. It's also harder to screw up a single byte than 95 * a whole media descriptor block. 96 * 97 * Note that not all tulip workalikes are handled in this driver: we only 98 * deal with those which are relatively well behaved. The Winbond is 99 * handled separately due to its different register offsets and the 100 * special handling needed for its various bugs. The PNIC is handled 101 * here, but I'm not thrilled about it. 102 * 103 * All of the workalike chips use some form of MII transceiver support 104 * with the exception of the Macronix chips, which also have a SYM port. 105 * The ASIX AX88140A is also documented to have a SYM port, but all 106 * the cards I've seen use an MII transceiver, probably because the 107 * AX88140A doesn't support internal NWAY. 108 */ 109 110 #include <sys/param.h> 111 #include <sys/systm.h> 112 #include <sys/sockio.h> 113 #include <sys/mbuf.h> 114 #include <sys/malloc.h> 115 #include <sys/kernel.h> 116 #include <sys/socket.h> 117 118 #include <net/if.h> 119 #include <net/if_arp.h> 120 #include <net/ethernet.h> 121 #include <net/if_dl.h> 122 #include <net/if_media.h> 123 124 #include <net/bpf.h> 125 126 #include <vm/vm.h> /* for vtophys */ 127 #include <vm/pmap.h> /* for vtophys */ 128 #include <machine/clock.h> /* for DELAY */ 129 #include <machine/bus_pio.h> 130 #include <machine/bus_memio.h> 131 #include <machine/bus.h> 132 #include <machine/resource.h> 133 #include <sys/bus.h> 134 #include <sys/rman.h> 135 136 #include <dev/mii/mii.h> 137 #include <dev/mii/miivar.h> 138 139 #include <pci/pcireg.h> 140 #include <pci/pcivar.h> 141 142 #define DC_USEIOSPACE 143 144 #include <pci/if_dcreg.h> 145 146 MODULE_DEPEND(dc, miibus, 1, 1, 1); 147 148 /* "controller miibus0" required. See GENERIC if you get errors here. */ 149 #include "miibus_if.h" 150 151 #ifndef lint 152 static const char rcsid[] = 153 "$FreeBSD$"; 154 #endif 155 156 /* 157 * Various supported device vendors/types and their names. 158 */ 159 static struct dc_type dc_devs[] = { 160 { DC_VENDORID_DEC, DC_DEVICEID_21143, 161 "Intel 21143 10/100BaseTX" }, 162 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 163 "Davicom DM9100 10/100BaseTX" }, 164 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 165 "Davicom DM9102 10/100BaseTX" }, 166 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 167 "Davicom DM9102A 10/100BaseTX" }, 168 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 169 "ADMtek AL981 10/100BaseTX" }, 170 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 171 "ADMtek AN985 10/100BaseTX" }, 172 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 173 "ASIX AX88140A 10/100BaseTX" }, 174 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 175 "ASIX AX88141 10/100BaseTX" }, 176 { DC_VENDORID_MX, DC_DEVICEID_98713, 177 "Macronix 98713 10/100BaseTX" }, 178 { DC_VENDORID_MX, DC_DEVICEID_98713, 179 "Macronix 98713A 10/100BaseTX" }, 180 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 181 "Compex RL100-TX 10/100BaseTX" }, 182 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 183 "Compex RL100-TX 10/100BaseTX" }, 184 { DC_VENDORID_MX, DC_DEVICEID_987x5, 185 "Macronix 98715/98715A 10/100BaseTX" }, 186 { DC_VENDORID_MX, DC_DEVICEID_987x5, 187 "Macronix 98715AEC-C 10/100BaseTX" }, 188 { DC_VENDORID_MX, DC_DEVICEID_987x5, 189 "Macronix 98725 10/100BaseTX" }, 190 { DC_VENDORID_MX, DC_DEVICEID_98727, 191 "Macronix 98727/98732 10/100BaseTX" }, 192 { DC_VENDORID_LO, DC_DEVICEID_82C115, 193 "LC82C115 PNIC II 10/100BaseTX" }, 194 { DC_VENDORID_LO, DC_DEVICEID_82C168, 195 "82c168 PNIC 10/100BaseTX" }, 196 { DC_VENDORID_LO, DC_DEVICEID_82C168, 197 "82c169 PNIC 10/100BaseTX" }, 198 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217, 199 "Accton EN1217 10/100BaseTX" }, 200 { 0, 0, NULL } 201 }; 202 203 static int dc_probe __P((device_t)); 204 static int dc_attach __P((device_t)); 205 static int dc_detach __P((device_t)); 206 static void dc_acpi __P((device_t)); 207 static struct dc_type *dc_devtype __P((device_t)); 208 static int dc_newbuf __P((struct dc_softc *, int, struct mbuf *)); 209 static int dc_encap __P((struct dc_softc *, struct mbuf *, 210 u_int32_t *)); 211 static int dc_coal __P((struct dc_softc *, struct mbuf **)); 212 static void dc_pnic_rx_bug_war __P((struct dc_softc *, int)); 213 static int dc_rx_resync __P((struct dc_softc *)); 214 static void dc_rxeof __P((struct dc_softc *)); 215 static void dc_txeof __P((struct dc_softc *)); 216 static void dc_tick __P((void *)); 217 static void dc_intr __P((void *)); 218 static void dc_start __P((struct ifnet *)); 219 static int dc_ioctl __P((struct ifnet *, u_long, caddr_t)); 220 static void dc_init __P((void *)); 221 static void dc_stop __P((struct dc_softc *)); 222 static void dc_watchdog __P((struct ifnet *)); 223 static void dc_shutdown __P((device_t)); 224 static int dc_ifmedia_upd __P((struct ifnet *)); 225 static void dc_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 226 227 static void dc_delay __P((struct dc_softc *)); 228 static void dc_eeprom_idle __P((struct dc_softc *)); 229 static void dc_eeprom_putbyte __P((struct dc_softc *, int)); 230 static void dc_eeprom_getword __P((struct dc_softc *, int, u_int16_t *)); 231 static void dc_eeprom_getword_pnic 232 __P((struct dc_softc *, int, u_int16_t *)); 233 static void dc_read_eeprom __P((struct dc_softc *, caddr_t, int, 234 int, int)); 235 236 static void dc_mii_writebit __P((struct dc_softc *, int)); 237 static int dc_mii_readbit __P((struct dc_softc *)); 238 static void dc_mii_sync __P((struct dc_softc *)); 239 static void dc_mii_send __P((struct dc_softc *, u_int32_t, int)); 240 static int dc_mii_readreg __P((struct dc_softc *, struct dc_mii_frame *)); 241 static int dc_mii_writereg __P((struct dc_softc *, struct dc_mii_frame *)); 242 static int dc_miibus_readreg __P((device_t, int, int)); 243 static int dc_miibus_writereg __P((device_t, int, int, int)); 244 static void dc_miibus_statchg __P((device_t)); 245 static void dc_miibus_mediainit __P((device_t)); 246 247 static void dc_setcfg __P((struct dc_softc *, int)); 248 static u_int32_t dc_crc_le __P((struct dc_softc *, caddr_t)); 249 static u_int32_t dc_crc_be __P((caddr_t)); 250 static void dc_setfilt_21143 __P((struct dc_softc *)); 251 static void dc_setfilt_asix __P((struct dc_softc *)); 252 static void dc_setfilt_admtek __P((struct dc_softc *)); 253 254 static void dc_setfilt __P((struct dc_softc *)); 255 256 static void dc_reset __P((struct dc_softc *)); 257 static int dc_list_rx_init __P((struct dc_softc *)); 258 static int dc_list_tx_init __P((struct dc_softc *)); 259 260 #ifdef DC_USEIOSPACE 261 #define DC_RES SYS_RES_IOPORT 262 #define DC_RID DC_PCI_CFBIO 263 #else 264 #define DC_RES SYS_RES_MEMORY 265 #define DC_RID DC_PCI_CFBMA 266 #endif 267 268 static device_method_t dc_methods[] = { 269 /* Device interface */ 270 DEVMETHOD(device_probe, dc_probe), 271 DEVMETHOD(device_attach, dc_attach), 272 DEVMETHOD(device_detach, dc_detach), 273 DEVMETHOD(device_shutdown, dc_shutdown), 274 275 /* bus interface */ 276 DEVMETHOD(bus_print_child, bus_generic_print_child), 277 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 278 279 /* MII interface */ 280 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 281 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 282 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 283 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 284 285 { 0, 0 } 286 }; 287 288 static driver_t dc_driver = { 289 "dc", 290 dc_methods, 291 sizeof(struct dc_softc) 292 }; 293 294 static devclass_t dc_devclass; 295 296 DRIVER_MODULE(if_dc, pci, dc_driver, dc_devclass, 0, 0); 297 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 298 299 #define DC_SETBIT(sc, reg, x) \ 300 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 301 302 #define DC_CLRBIT(sc, reg, x) \ 303 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 304 305 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 306 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 307 308 static void dc_delay(sc) 309 struct dc_softc *sc; 310 { 311 int idx; 312 313 for (idx = (300 / 33) + 1; idx > 0; idx--) 314 CSR_READ_4(sc, DC_BUSCTL); 315 } 316 317 static void dc_eeprom_idle(sc) 318 struct dc_softc *sc; 319 { 320 register int i; 321 322 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 323 dc_delay(sc); 324 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 325 dc_delay(sc); 326 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 327 dc_delay(sc); 328 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 329 dc_delay(sc); 330 331 for (i = 0; i < 25; i++) { 332 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 333 dc_delay(sc); 334 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 335 dc_delay(sc); 336 } 337 338 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 339 dc_delay(sc); 340 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 341 dc_delay(sc); 342 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 343 344 return; 345 } 346 347 /* 348 * Send a read command and address to the EEPROM, check for ACK. 349 */ 350 static void dc_eeprom_putbyte(sc, addr) 351 struct dc_softc *sc; 352 int addr; 353 { 354 register int d, i; 355 356 /* 357 * The AN985 has a 93C66 EEPROM on it instead of 358 * a 93C46. It uses a different bit sequence for 359 * specifying the "read" opcode. 360 */ 361 if (DC_IS_CENTAUR(sc)) 362 d = addr | (DC_EECMD_READ << 2); 363 else 364 d = addr | DC_EECMD_READ; 365 366 /* 367 * Feed in each bit and strobe the clock. 368 */ 369 for (i = 0x400; i; i >>= 1) { 370 if (d & i) { 371 SIO_SET(DC_SIO_EE_DATAIN); 372 } else { 373 SIO_CLR(DC_SIO_EE_DATAIN); 374 } 375 dc_delay(sc); 376 SIO_SET(DC_SIO_EE_CLK); 377 dc_delay(sc); 378 SIO_CLR(DC_SIO_EE_CLK); 379 dc_delay(sc); 380 } 381 382 return; 383 } 384 385 /* 386 * Read a word of data stored in the EEPROM at address 'addr.' 387 * The PNIC 82c168/82c169 has its own non-standard way to read 388 * the EEPROM. 389 */ 390 static void dc_eeprom_getword_pnic(sc, addr, dest) 391 struct dc_softc *sc; 392 int addr; 393 u_int16_t *dest; 394 { 395 register int i; 396 u_int32_t r; 397 398 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ|addr); 399 400 for (i = 0; i < DC_TIMEOUT; i++) { 401 DELAY(1); 402 r = CSR_READ_4(sc, DC_SIO); 403 if (!(r & DC_PN_SIOCTL_BUSY)) { 404 *dest = (u_int16_t)(r & 0xFFFF); 405 return; 406 } 407 } 408 409 return; 410 } 411 412 /* 413 * Read a word of data stored in the EEPROM at address 'addr.' 414 */ 415 static void dc_eeprom_getword(sc, addr, dest) 416 struct dc_softc *sc; 417 int addr; 418 u_int16_t *dest; 419 { 420 register int i; 421 u_int16_t word = 0; 422 423 /* Force EEPROM to idle state. */ 424 dc_eeprom_idle(sc); 425 426 /* Enter EEPROM access mode. */ 427 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 428 dc_delay(sc); 429 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 430 dc_delay(sc); 431 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 432 dc_delay(sc); 433 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 434 dc_delay(sc); 435 436 /* 437 * Send address of word we want to read. 438 */ 439 dc_eeprom_putbyte(sc, addr); 440 441 /* 442 * Start reading bits from EEPROM. 443 */ 444 for (i = 0x8000; i; i >>= 1) { 445 SIO_SET(DC_SIO_EE_CLK); 446 dc_delay(sc); 447 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 448 word |= i; 449 dc_delay(sc); 450 SIO_CLR(DC_SIO_EE_CLK); 451 dc_delay(sc); 452 } 453 454 /* Turn off EEPROM access mode. */ 455 dc_eeprom_idle(sc); 456 457 *dest = word; 458 459 return; 460 } 461 462 /* 463 * Read a sequence of words from the EEPROM. 464 */ 465 static void dc_read_eeprom(sc, dest, off, cnt, swap) 466 struct dc_softc *sc; 467 caddr_t dest; 468 int off; 469 int cnt; 470 int swap; 471 { 472 int i; 473 u_int16_t word = 0, *ptr; 474 475 for (i = 0; i < cnt; i++) { 476 if (DC_IS_PNIC(sc)) 477 dc_eeprom_getword_pnic(sc, off + i, &word); 478 else 479 dc_eeprom_getword(sc, off + i, &word); 480 ptr = (u_int16_t *)(dest + (i * 2)); 481 if (swap) 482 *ptr = ntohs(word); 483 else 484 *ptr = word; 485 } 486 487 return; 488 } 489 490 /* 491 * The following two routines are taken from the Macronix 98713 492 * Application Notes pp.19-21. 493 */ 494 /* 495 * Write a bit to the MII bus. 496 */ 497 static void dc_mii_writebit(sc, bit) 498 struct dc_softc *sc; 499 int bit; 500 { 501 if (bit) 502 CSR_WRITE_4(sc, DC_SIO, 503 DC_SIO_ROMCTL_WRITE|DC_SIO_MII_DATAOUT); 504 else 505 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 506 507 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 508 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 509 510 return; 511 } 512 513 /* 514 * Read a bit from the MII bus. 515 */ 516 static int dc_mii_readbit(sc) 517 struct dc_softc *sc; 518 { 519 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ|DC_SIO_MII_DIR); 520 CSR_READ_4(sc, DC_SIO); 521 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 522 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 523 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 524 return(1); 525 526 return(0); 527 } 528 529 /* 530 * Sync the PHYs by setting data bit and strobing the clock 32 times. 531 */ 532 static void dc_mii_sync(sc) 533 struct dc_softc *sc; 534 { 535 register int i; 536 537 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 538 539 for (i = 0; i < 32; i++) 540 dc_mii_writebit(sc, 1); 541 542 return; 543 } 544 545 /* 546 * Clock a series of bits through the MII. 547 */ 548 static void dc_mii_send(sc, bits, cnt) 549 struct dc_softc *sc; 550 u_int32_t bits; 551 int cnt; 552 { 553 int i; 554 555 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 556 dc_mii_writebit(sc, bits & i); 557 } 558 559 /* 560 * Read an PHY register through the MII. 561 */ 562 static int dc_mii_readreg(sc, frame) 563 struct dc_softc *sc; 564 struct dc_mii_frame *frame; 565 566 { 567 int i, ack, s; 568 569 s = splimp(); 570 571 /* 572 * Set up frame for RX. 573 */ 574 frame->mii_stdelim = DC_MII_STARTDELIM; 575 frame->mii_opcode = DC_MII_READOP; 576 frame->mii_turnaround = 0; 577 frame->mii_data = 0; 578 579 /* 580 * Sync the PHYs. 581 */ 582 dc_mii_sync(sc); 583 584 /* 585 * Send command/address info. 586 */ 587 dc_mii_send(sc, frame->mii_stdelim, 2); 588 dc_mii_send(sc, frame->mii_opcode, 2); 589 dc_mii_send(sc, frame->mii_phyaddr, 5); 590 dc_mii_send(sc, frame->mii_regaddr, 5); 591 592 #ifdef notdef 593 /* Idle bit */ 594 dc_mii_writebit(sc, 1); 595 dc_mii_writebit(sc, 0); 596 #endif 597 598 /* Check for ack */ 599 ack = dc_mii_readbit(sc); 600 601 /* 602 * Now try reading data bits. If the ack failed, we still 603 * need to clock through 16 cycles to keep the PHY(s) in sync. 604 */ 605 if (ack) { 606 for(i = 0; i < 16; i++) { 607 dc_mii_readbit(sc); 608 } 609 goto fail; 610 } 611 612 for (i = 0x8000; i; i >>= 1) { 613 if (!ack) { 614 if (dc_mii_readbit(sc)) 615 frame->mii_data |= i; 616 } 617 } 618 619 fail: 620 621 dc_mii_writebit(sc, 0); 622 dc_mii_writebit(sc, 0); 623 624 splx(s); 625 626 if (ack) 627 return(1); 628 return(0); 629 } 630 631 /* 632 * Write to a PHY register through the MII. 633 */ 634 static int dc_mii_writereg(sc, frame) 635 struct dc_softc *sc; 636 struct dc_mii_frame *frame; 637 638 { 639 int s; 640 641 s = splimp(); 642 /* 643 * Set up frame for TX. 644 */ 645 646 frame->mii_stdelim = DC_MII_STARTDELIM; 647 frame->mii_opcode = DC_MII_WRITEOP; 648 frame->mii_turnaround = DC_MII_TURNAROUND; 649 650 /* 651 * Sync the PHYs. 652 */ 653 dc_mii_sync(sc); 654 655 dc_mii_send(sc, frame->mii_stdelim, 2); 656 dc_mii_send(sc, frame->mii_opcode, 2); 657 dc_mii_send(sc, frame->mii_phyaddr, 5); 658 dc_mii_send(sc, frame->mii_regaddr, 5); 659 dc_mii_send(sc, frame->mii_turnaround, 2); 660 dc_mii_send(sc, frame->mii_data, 16); 661 662 /* Idle bit. */ 663 dc_mii_writebit(sc, 0); 664 dc_mii_writebit(sc, 0); 665 666 splx(s); 667 668 return(0); 669 } 670 671 static int dc_miibus_readreg(dev, phy, reg) 672 device_t dev; 673 int phy, reg; 674 { 675 struct dc_mii_frame frame; 676 struct dc_softc *sc; 677 int i, rval, phy_reg; 678 679 sc = device_get_softc(dev); 680 bzero((char *)&frame, sizeof(frame)); 681 682 /* 683 * Note: both the AL981 and AN985 have internal PHYs, 684 * however the AL981 provides direct access to the PHY 685 * registers while the AN985 uses a serial MII interface. 686 * The AN985's MII interface is also buggy in that you 687 * can read from any MII address (0 to 31), but only address 1 688 * behaves normally. To deal with both cases, we pretend 689 * that the PHY is at MII address 1. 690 */ 691 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 692 return(0); 693 694 if (sc->dc_pmode == DC_PMODE_SYM) { 695 if (phy == (MII_NPHY - 1)) { 696 switch(reg) { 697 case MII_BMSR: 698 /* 699 * Fake something to make the probe 700 * code think there's a PHY here. 701 */ 702 return(BMSR_MEDIAMASK); 703 break; 704 case MII_PHYIDR1: 705 if (DC_IS_PNIC(sc)) 706 return(DC_VENDORID_LO); 707 return(DC_VENDORID_DEC); 708 break; 709 case MII_PHYIDR2: 710 if (DC_IS_PNIC(sc)) 711 return(DC_DEVICEID_82C168); 712 return(DC_DEVICEID_21143); 713 break; 714 default: 715 return(0); 716 break; 717 } 718 } else 719 return(0); 720 } 721 722 if (DC_IS_PNIC(sc)) { 723 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 724 (phy << 23) | (reg << 18)); 725 for (i = 0; i < DC_TIMEOUT; i++) { 726 DELAY(1); 727 rval = CSR_READ_4(sc, DC_PN_MII); 728 if (!(rval & DC_PN_MII_BUSY)) { 729 rval &= 0xFFFF; 730 return(rval == 0xFFFF ? 0 : rval); 731 } 732 } 733 return(0); 734 } 735 736 if (DC_IS_COMET(sc)) { 737 switch(reg) { 738 case MII_BMCR: 739 phy_reg = DC_AL_BMCR; 740 break; 741 case MII_BMSR: 742 phy_reg = DC_AL_BMSR; 743 break; 744 case MII_PHYIDR1: 745 phy_reg = DC_AL_VENID; 746 break; 747 case MII_PHYIDR2: 748 phy_reg = DC_AL_DEVID; 749 break; 750 case MII_ANAR: 751 phy_reg = DC_AL_ANAR; 752 break; 753 case MII_ANLPAR: 754 phy_reg = DC_AL_LPAR; 755 break; 756 case MII_ANER: 757 phy_reg = DC_AL_ANER; 758 break; 759 default: 760 printf("dc%d: phy_read: bad phy register %x\n", 761 sc->dc_unit, reg); 762 return(0); 763 break; 764 } 765 766 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 767 768 if (rval == 0xFFFF) 769 return(0); 770 return(rval); 771 } 772 773 frame.mii_phyaddr = phy; 774 frame.mii_regaddr = reg; 775 phy_reg = CSR_READ_4(sc, DC_NETCFG); 776 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 777 dc_mii_readreg(sc, &frame); 778 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 779 780 return(frame.mii_data); 781 } 782 783 static int dc_miibus_writereg(dev, phy, reg, data) 784 device_t dev; 785 int phy, reg, data; 786 { 787 struct dc_softc *sc; 788 struct dc_mii_frame frame; 789 int i, phy_reg; 790 791 sc = device_get_softc(dev); 792 bzero((char *)&frame, sizeof(frame)); 793 794 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 795 return(0); 796 797 if (DC_IS_PNIC(sc)) { 798 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 799 (phy << 23) | (reg << 10) | data); 800 for (i = 0; i < DC_TIMEOUT; i++) { 801 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 802 break; 803 } 804 return(0); 805 } 806 807 if (DC_IS_COMET(sc)) { 808 switch(reg) { 809 case MII_BMCR: 810 phy_reg = DC_AL_BMCR; 811 break; 812 case MII_BMSR: 813 phy_reg = DC_AL_BMSR; 814 break; 815 case MII_PHYIDR1: 816 phy_reg = DC_AL_VENID; 817 break; 818 case MII_PHYIDR2: 819 phy_reg = DC_AL_DEVID; 820 break; 821 case MII_ANAR: 822 phy_reg = DC_AL_ANAR; 823 break; 824 case MII_ANLPAR: 825 phy_reg = DC_AL_LPAR; 826 break; 827 case MII_ANER: 828 phy_reg = DC_AL_ANER; 829 break; 830 default: 831 printf("dc%d: phy_write: bad phy register %x\n", 832 sc->dc_unit, reg); 833 return(0); 834 break; 835 } 836 837 CSR_WRITE_4(sc, phy_reg, data); 838 return(0); 839 } 840 841 frame.mii_phyaddr = phy; 842 frame.mii_regaddr = reg; 843 frame.mii_data = data; 844 845 phy_reg = CSR_READ_4(sc, DC_NETCFG); 846 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 847 dc_mii_writereg(sc, &frame); 848 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 849 850 return(0); 851 } 852 853 static void dc_miibus_statchg(dev) 854 device_t dev; 855 { 856 struct dc_softc *sc; 857 struct mii_data *mii; 858 struct ifmedia *ifm; 859 860 sc = device_get_softc(dev); 861 if (DC_IS_ADMTEK(sc)) 862 return; 863 mii = device_get_softc(sc->dc_miibus); 864 ifm = &mii->mii_media; 865 if (DC_IS_DAVICOM(sc) && 866 IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) { 867 dc_setcfg(sc, ifm->ifm_media); 868 sc->dc_if_media = ifm->ifm_media; 869 } else { 870 dc_setcfg(sc, mii->mii_media_active); 871 sc->dc_if_media = mii->mii_media_active; 872 } 873 874 return; 875 } 876 877 /* 878 * Special support for DM9102A cards with HomePNA PHYs. Note: 879 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 880 * to be impossible to talk to the management interface of the DM9801 881 * PHY (its MDIO pin is not connected to anything). Consequently, 882 * the driver has to just 'know' about the additional mode and deal 883 * with it itself. *sigh* 884 */ 885 static void dc_miibus_mediainit(dev) 886 device_t dev; 887 { 888 struct dc_softc *sc; 889 struct mii_data *mii; 890 struct ifmedia *ifm; 891 int rev; 892 893 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 894 895 sc = device_get_softc(dev); 896 mii = device_get_softc(sc->dc_miibus); 897 ifm = &mii->mii_media; 898 899 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 900 ifmedia_add(ifm, IFM_ETHER|IFM_homePNA, 0, NULL); 901 902 return; 903 } 904 905 #define DC_POLY 0xEDB88320 906 #define DC_BITS_512 9 907 #define DC_BITS_128 7 908 #define DC_BITS_64 6 909 910 static u_int32_t dc_crc_le(sc, addr) 911 struct dc_softc *sc; 912 caddr_t addr; 913 { 914 u_int32_t idx, bit, data, crc; 915 916 /* Compute CRC for the address value. */ 917 crc = 0xFFFFFFFF; /* initial value */ 918 919 for (idx = 0; idx < 6; idx++) { 920 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 921 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 922 } 923 924 /* 925 * The hash table on the PNIC II and the MX98715AEC-C/D/E 926 * chips is only 128 bits wide. 927 */ 928 if (sc->dc_flags & DC_128BIT_HASH) 929 return (crc & ((1 << DC_BITS_128) - 1)); 930 931 /* The hash table on the MX98715BEC is only 64 bits wide. */ 932 if (sc->dc_flags & DC_64BIT_HASH) 933 return (crc & ((1 << DC_BITS_64) - 1)); 934 935 return (crc & ((1 << DC_BITS_512) - 1)); 936 } 937 938 /* 939 * Calculate CRC of a multicast group address, return the lower 6 bits. 940 */ 941 static u_int32_t dc_crc_be(addr) 942 caddr_t addr; 943 { 944 u_int32_t crc, carry; 945 int i, j; 946 u_int8_t c; 947 948 /* Compute CRC for the address value. */ 949 crc = 0xFFFFFFFF; /* initial value */ 950 951 for (i = 0; i < 6; i++) { 952 c = *(addr + i); 953 for (j = 0; j < 8; j++) { 954 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 955 crc <<= 1; 956 c >>= 1; 957 if (carry) 958 crc = (crc ^ 0x04c11db6) | carry; 959 } 960 } 961 962 /* return the filter bit position */ 963 return((crc >> 26) & 0x0000003F); 964 } 965 966 /* 967 * 21143-style RX filter setup routine. Filter programming is done by 968 * downloading a special setup frame into the TX engine. 21143, Macronix, 969 * PNIC, PNIC II and Davicom chips are programmed this way. 970 * 971 * We always program the chip using 'hash perfect' mode, i.e. one perfect 972 * address (our node address) and a 512-bit hash filter for multicast 973 * frames. We also sneak the broadcast address into the hash filter since 974 * we need that too. 975 */ 976 void dc_setfilt_21143(sc) 977 struct dc_softc *sc; 978 { 979 struct dc_desc *sframe; 980 u_int32_t h, *sp; 981 struct ifmultiaddr *ifma; 982 struct ifnet *ifp; 983 int i; 984 985 ifp = &sc->arpcom.ac_if; 986 987 i = sc->dc_cdata.dc_tx_prod; 988 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 989 sc->dc_cdata.dc_tx_cnt++; 990 sframe = &sc->dc_ldata->dc_tx_list[i]; 991 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 992 bzero((char *)sp, DC_SFRAME_LEN); 993 994 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 995 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 996 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 997 998 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 999 1000 /* If we want promiscuous mode, set the allframes bit. */ 1001 if (ifp->if_flags & IFF_PROMISC) 1002 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1003 else 1004 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1005 1006 if (ifp->if_flags & IFF_ALLMULTI) 1007 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1008 else 1009 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1010 1011 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1012 ifma = ifma->ifma_link.le_next) { 1013 if (ifma->ifma_addr->sa_family != AF_LINK) 1014 continue; 1015 h = dc_crc_le(sc, 1016 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1017 sp[h >> 4] |= 1 << (h & 0xF); 1018 } 1019 1020 if (ifp->if_flags & IFF_BROADCAST) { 1021 h = dc_crc_le(sc, (caddr_t)ðerbroadcastaddr); 1022 sp[h >> 4] |= 1 << (h & 0xF); 1023 } 1024 1025 /* Set our MAC address */ 1026 sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1027 sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1028 sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1029 1030 sframe->dc_status = DC_TXSTAT_OWN; 1031 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1032 1033 /* 1034 * The PNIC takes an exceedingly long time to process its 1035 * setup frame; wait 10ms after posting the setup frame 1036 * before proceeding, just so it has time to swallow its 1037 * medicine. 1038 */ 1039 DELAY(10000); 1040 1041 ifp->if_timer = 5; 1042 1043 return; 1044 } 1045 1046 void dc_setfilt_admtek(sc) 1047 struct dc_softc *sc; 1048 { 1049 struct ifnet *ifp; 1050 int h = 0; 1051 u_int32_t hashes[2] = { 0, 0 }; 1052 struct ifmultiaddr *ifma; 1053 1054 ifp = &sc->arpcom.ac_if; 1055 1056 /* Init our MAC address */ 1057 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1058 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1059 1060 /* If we want promiscuous mode, set the allframes bit. */ 1061 if (ifp->if_flags & IFF_PROMISC) 1062 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1063 else 1064 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1065 1066 if (ifp->if_flags & IFF_ALLMULTI) 1067 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1068 else 1069 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1070 1071 /* first, zot all the existing hash bits */ 1072 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1073 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1074 1075 /* 1076 * If we're already in promisc or allmulti mode, we 1077 * don't have to bother programming the multicast filter. 1078 */ 1079 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1080 return; 1081 1082 /* now program new ones */ 1083 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1084 ifma = ifma->ifma_link.le_next) { 1085 if (ifma->ifma_addr->sa_family != AF_LINK) 1086 continue; 1087 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1088 if (h < 32) 1089 hashes[0] |= (1 << h); 1090 else 1091 hashes[1] |= (1 << (h - 32)); 1092 } 1093 1094 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1095 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1096 1097 return; 1098 } 1099 1100 void dc_setfilt_asix(sc) 1101 struct dc_softc *sc; 1102 { 1103 struct ifnet *ifp; 1104 int h = 0; 1105 u_int32_t hashes[2] = { 0, 0 }; 1106 struct ifmultiaddr *ifma; 1107 1108 ifp = &sc->arpcom.ac_if; 1109 1110 /* Init our MAC address */ 1111 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1112 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1113 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1114 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1115 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1116 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1117 1118 /* If we want promiscuous mode, set the allframes bit. */ 1119 if (ifp->if_flags & IFF_PROMISC) 1120 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1121 else 1122 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1123 1124 if (ifp->if_flags & IFF_ALLMULTI) 1125 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1126 else 1127 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1128 1129 /* 1130 * The ASIX chip has a special bit to enable reception 1131 * of broadcast frames. 1132 */ 1133 if (ifp->if_flags & IFF_BROADCAST) 1134 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1135 else 1136 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1137 1138 /* first, zot all the existing hash bits */ 1139 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1140 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1141 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1142 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1143 1144 /* 1145 * If we're already in promisc or allmulti mode, we 1146 * don't have to bother programming the multicast filter. 1147 */ 1148 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1149 return; 1150 1151 /* now program new ones */ 1152 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1153 ifma = ifma->ifma_link.le_next) { 1154 if (ifma->ifma_addr->sa_family != AF_LINK) 1155 continue; 1156 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1157 if (h < 32) 1158 hashes[0] |= (1 << h); 1159 else 1160 hashes[1] |= (1 << (h - 32)); 1161 } 1162 1163 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1164 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1165 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1166 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1167 1168 return; 1169 } 1170 1171 static void dc_setfilt(sc) 1172 struct dc_softc *sc; 1173 { 1174 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1175 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc)) 1176 dc_setfilt_21143(sc); 1177 1178 if (DC_IS_ASIX(sc)) 1179 dc_setfilt_asix(sc); 1180 1181 if (DC_IS_ADMTEK(sc)) 1182 dc_setfilt_admtek(sc); 1183 1184 return; 1185 } 1186 1187 /* 1188 * In order to fiddle with the 1189 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 1190 * first have to put the transmit and/or receive logic in the idle state. 1191 */ 1192 static void dc_setcfg(sc, media) 1193 struct dc_softc *sc; 1194 int media; 1195 { 1196 int i, restart = 0; 1197 u_int32_t isr; 1198 1199 if (IFM_SUBTYPE(media) == IFM_NONE) 1200 return; 1201 1202 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)) { 1203 restart = 1; 1204 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1205 1206 for (i = 0; i < DC_TIMEOUT; i++) { 1207 DELAY(10); 1208 isr = CSR_READ_4(sc, DC_ISR); 1209 if (isr & DC_ISR_TX_IDLE || 1210 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED) 1211 break; 1212 } 1213 1214 if (i == DC_TIMEOUT) 1215 printf("dc%d: failed to force tx and " 1216 "rx to idle state\n", sc->dc_unit); 1217 1218 } 1219 1220 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1221 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1222 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1223 if (sc->dc_pmode == DC_PMODE_MII) { 1224 int watchdogreg; 1225 1226 if (DC_IS_INTEL(sc)) { 1227 /* there's a write enable bit here that reads as 1 */ 1228 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1229 watchdogreg &= ~DC_WDOG_CTLWREN; 1230 watchdogreg |= DC_WDOG_JABBERDIS; 1231 } else { 1232 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1233 } 1234 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1235 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1236 if (sc->dc_type == DC_TYPE_98713) 1237 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1238 DC_NETCFG_SCRAMBLER)); 1239 if (!DC_IS_DAVICOM(sc)) 1240 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1241 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1242 } else { 1243 if (DC_IS_PNIC(sc)) { 1244 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1245 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1246 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1247 } 1248 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1249 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1250 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1251 } 1252 } 1253 1254 if (IFM_SUBTYPE(media) == IFM_10_T) { 1255 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1256 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1257 if (sc->dc_pmode == DC_PMODE_MII) { 1258 int watchdogreg; 1259 1260 /* there's a write enable bit here that reads as 1 */ 1261 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1262 watchdogreg &= ~DC_WDOG_CTLWREN; 1263 watchdogreg |= DC_WDOG_JABBERDIS; 1264 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1265 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1266 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1267 if (sc->dc_type == DC_TYPE_98713) 1268 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1269 if (!DC_IS_DAVICOM(sc)) 1270 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1271 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1272 } else { 1273 if (DC_IS_PNIC(sc)) { 1274 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1275 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1276 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1277 } 1278 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1279 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1280 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1281 } 1282 } 1283 1284 /* 1285 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1286 * PHY and we want HomePNA mode, set the portsel bit to turn 1287 * on the external MII port. 1288 */ 1289 if (DC_IS_DAVICOM(sc)) { 1290 if (IFM_SUBTYPE(media) == IFM_homePNA) { 1291 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1292 sc->dc_link = 1; 1293 } else { 1294 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1295 } 1296 } 1297 1298 if ((media & IFM_GMASK) == IFM_FDX) { 1299 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1300 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1301 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1302 } else { 1303 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1304 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1305 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1306 } 1307 1308 if (restart) 1309 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON|DC_NETCFG_RX_ON); 1310 1311 return; 1312 } 1313 1314 static void dc_reset(sc) 1315 struct dc_softc *sc; 1316 { 1317 register int i; 1318 1319 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1320 1321 for (i = 0; i < DC_TIMEOUT; i++) { 1322 DELAY(10); 1323 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1324 break; 1325 } 1326 1327 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc)) { 1328 DELAY(10000); 1329 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1330 i = 0; 1331 } 1332 1333 if (i == DC_TIMEOUT) 1334 printf("dc%d: reset never completed!\n", sc->dc_unit); 1335 1336 /* Wait a little while for the chip to get its brains in order. */ 1337 DELAY(1000); 1338 1339 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1340 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1341 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1342 1343 /* 1344 * Bring the SIA out of reset. In some cases, it looks 1345 * like failing to unreset the SIA soon enough gets it 1346 * into a state where it will never come out of reset 1347 * until we reset the whole chip again. 1348 */ 1349 if (DC_IS_INTEL(sc)) 1350 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1351 1352 return; 1353 } 1354 1355 static struct dc_type *dc_devtype(dev) 1356 device_t dev; 1357 { 1358 struct dc_type *t; 1359 u_int32_t rev; 1360 1361 t = dc_devs; 1362 1363 while(t->dc_name != NULL) { 1364 if ((pci_get_vendor(dev) == t->dc_vid) && 1365 (pci_get_device(dev) == t->dc_did)) { 1366 /* Check the PCI revision */ 1367 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1368 if (t->dc_did == DC_DEVICEID_98713 && 1369 rev >= DC_REVISION_98713A) 1370 t++; 1371 if (t->dc_did == DC_DEVICEID_98713_CP && 1372 rev >= DC_REVISION_98713A) 1373 t++; 1374 if (t->dc_did == DC_DEVICEID_987x5 && 1375 rev >= DC_REVISION_98715AEC_C) 1376 t++; 1377 if (t->dc_did == DC_DEVICEID_987x5 && 1378 rev >= DC_REVISION_98725) 1379 t++; 1380 if (t->dc_did == DC_DEVICEID_AX88140A && 1381 rev >= DC_REVISION_88141) 1382 t++; 1383 if (t->dc_did == DC_DEVICEID_82C168 && 1384 rev >= DC_REVISION_82C169) 1385 t++; 1386 if (t->dc_did == DC_DEVICEID_DM9102 && 1387 rev >= DC_REVISION_DM9102A) 1388 t++; 1389 return(t); 1390 } 1391 t++; 1392 } 1393 1394 return(NULL); 1395 } 1396 1397 /* 1398 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1399 * IDs against our list and return a device name if we find a match. 1400 * We do a little bit of extra work to identify the exact type of 1401 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1402 * but different revision IDs. The same is true for 98715/98715A 1403 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1404 * cases, the exact chip revision affects driver behavior. 1405 */ 1406 static int dc_probe(dev) 1407 device_t dev; 1408 { 1409 struct dc_type *t; 1410 1411 t = dc_devtype(dev); 1412 1413 if (t != NULL) { 1414 device_set_desc(dev, t->dc_name); 1415 return(0); 1416 } 1417 1418 return(ENXIO); 1419 } 1420 1421 static void dc_acpi(dev) 1422 device_t dev; 1423 { 1424 u_int32_t r, cptr; 1425 int unit; 1426 1427 unit = device_get_unit(dev); 1428 1429 /* Find the location of the capabilities block */ 1430 cptr = pci_read_config(dev, DC_PCI_CCAP, 4) & 0xFF; 1431 1432 r = pci_read_config(dev, cptr, 4) & 0xFF; 1433 if (r == 0x01) { 1434 1435 r = pci_read_config(dev, cptr + 4, 4); 1436 if (r & DC_PSTATE_D3) { 1437 u_int32_t iobase, membase, irq; 1438 1439 /* Save important PCI config data. */ 1440 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4); 1441 membase = pci_read_config(dev, DC_PCI_CFBMA, 4); 1442 irq = pci_read_config(dev, DC_PCI_CFIT, 4); 1443 1444 /* Reset the power state. */ 1445 printf("dc%d: chip is in D%d power mode " 1446 "-- setting to D0\n", unit, r & DC_PSTATE_D3); 1447 r &= 0xFFFFFFFC; 1448 pci_write_config(dev, cptr + 4, r, 4); 1449 1450 /* Restore PCI config data. */ 1451 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4); 1452 pci_write_config(dev, DC_PCI_CFBMA, membase, 4); 1453 pci_write_config(dev, DC_PCI_CFIT, irq, 4); 1454 } 1455 } 1456 return; 1457 } 1458 1459 /* 1460 * Attach the interface. Allocate softc structures, do ifmedia 1461 * setup and ethernet/BPF attach. 1462 */ 1463 static int dc_attach(dev) 1464 device_t dev; 1465 { 1466 int s; 1467 u_char eaddr[ETHER_ADDR_LEN]; 1468 u_int32_t command; 1469 struct dc_softc *sc; 1470 struct ifnet *ifp; 1471 u_int32_t revision; 1472 int unit, error = 0, rid, mac_offset; 1473 1474 s = splimp(); 1475 1476 sc = device_get_softc(dev); 1477 unit = device_get_unit(dev); 1478 bzero(sc, sizeof(struct dc_softc)); 1479 1480 /* 1481 * Handle power management nonsense. 1482 */ 1483 dc_acpi(dev); 1484 1485 /* 1486 * Map control/status registers. 1487 */ 1488 command = pci_read_config(dev, PCIR_COMMAND, 4); 1489 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1490 pci_write_config(dev, PCIR_COMMAND, command, 4); 1491 command = pci_read_config(dev, PCIR_COMMAND, 4); 1492 1493 #ifdef DC_USEIOSPACE 1494 if (!(command & PCIM_CMD_PORTEN)) { 1495 printf("dc%d: failed to enable I/O ports!\n", unit); 1496 error = ENXIO; 1497 goto fail; 1498 } 1499 #else 1500 if (!(command & PCIM_CMD_MEMEN)) { 1501 printf("dc%d: failed to enable memory mapping!\n", unit); 1502 error = ENXIO; 1503 goto fail; 1504 } 1505 #endif 1506 1507 rid = DC_RID; 1508 sc->dc_res = bus_alloc_resource(dev, DC_RES, &rid, 1509 0, ~0, 1, RF_ACTIVE); 1510 1511 if (sc->dc_res == NULL) { 1512 printf("dc%d: couldn't map ports/memory\n", unit); 1513 error = ENXIO; 1514 goto fail; 1515 } 1516 1517 sc->dc_btag = rman_get_bustag(sc->dc_res); 1518 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1519 1520 /* Allocate interrupt */ 1521 rid = 0; 1522 sc->dc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1523 RF_SHAREABLE | RF_ACTIVE); 1524 1525 if (sc->dc_irq == NULL) { 1526 printf("dc%d: couldn't map interrupt\n", unit); 1527 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1528 error = ENXIO; 1529 goto fail; 1530 } 1531 1532 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET, 1533 dc_intr, sc, &sc->dc_intrhand); 1534 1535 if (error) { 1536 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 1537 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1538 printf("dc%d: couldn't set up irq\n", unit); 1539 goto fail; 1540 } 1541 1542 /* Need this info to decide on a chip type. */ 1543 sc->dc_info = dc_devtype(dev); 1544 revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF; 1545 1546 switch(sc->dc_info->dc_did) { 1547 case DC_DEVICEID_21143: 1548 sc->dc_type = DC_TYPE_21143; 1549 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1550 sc->dc_flags |= DC_REDUCED_MII_POLL; 1551 break; 1552 case DC_DEVICEID_DM9100: 1553 case DC_DEVICEID_DM9102: 1554 sc->dc_type = DC_TYPE_DM9102; 1555 sc->dc_flags |= DC_TX_COALESCE|DC_TX_USE_TX_INTR; 1556 sc->dc_flags |= DC_REDUCED_MII_POLL; 1557 sc->dc_pmode = DC_PMODE_MII; 1558 break; 1559 case DC_DEVICEID_AL981: 1560 sc->dc_type = DC_TYPE_AL981; 1561 sc->dc_flags |= DC_TX_USE_TX_INTR; 1562 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1563 sc->dc_pmode = DC_PMODE_MII; 1564 break; 1565 case DC_DEVICEID_AN985: 1566 sc->dc_type = DC_TYPE_AN985; 1567 sc->dc_flags |= DC_TX_USE_TX_INTR; 1568 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1569 sc->dc_pmode = DC_PMODE_MII; 1570 break; 1571 case DC_DEVICEID_98713: 1572 case DC_DEVICEID_98713_CP: 1573 if (revision < DC_REVISION_98713A) { 1574 sc->dc_type = DC_TYPE_98713; 1575 } 1576 if (revision >= DC_REVISION_98713A) { 1577 sc->dc_type = DC_TYPE_98713A; 1578 sc->dc_flags |= DC_21143_NWAY; 1579 } 1580 sc->dc_flags |= DC_REDUCED_MII_POLL; 1581 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1582 break; 1583 case DC_DEVICEID_987x5: 1584 case DC_DEVICEID_EN1217: 1585 /* 1586 * Macronix MX98715AEC-C/D/E parts have only a 1587 * 128-bit hash table. We need to deal with these 1588 * in the same manner as the PNIC II so that we 1589 * get the right number of bits out of the 1590 * CRC routine. 1591 */ 1592 if (revision >= DC_REVISION_98715AEC_C && 1593 revision < DC_REVISION_98725) 1594 sc->dc_flags |= DC_128BIT_HASH; 1595 sc->dc_type = DC_TYPE_987x5; 1596 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1597 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1598 break; 1599 case DC_DEVICEID_98727: 1600 sc->dc_type = DC_TYPE_987x5; 1601 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1602 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1603 break; 1604 case DC_DEVICEID_82C115: 1605 sc->dc_type = DC_TYPE_PNICII; 1606 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR|DC_128BIT_HASH; 1607 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1608 break; 1609 case DC_DEVICEID_82C168: 1610 sc->dc_type = DC_TYPE_PNIC; 1611 sc->dc_flags |= DC_TX_STORENFWD|DC_TX_INTR_ALWAYS; 1612 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 1613 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 1614 if (revision < DC_REVISION_82C169) 1615 sc->dc_pmode = DC_PMODE_SYM; 1616 break; 1617 case DC_DEVICEID_AX88140A: 1618 sc->dc_type = DC_TYPE_ASIX; 1619 sc->dc_flags |= DC_TX_USE_TX_INTR|DC_TX_INTR_FIRSTFRAG; 1620 sc->dc_flags |= DC_REDUCED_MII_POLL; 1621 sc->dc_pmode = DC_PMODE_MII; 1622 break; 1623 default: 1624 printf("dc%d: unknown device: %x\n", sc->dc_unit, 1625 sc->dc_info->dc_did); 1626 break; 1627 } 1628 1629 /* Save the cache line size. */ 1630 if (DC_IS_DAVICOM(sc)) 1631 sc->dc_cachesize = 0; 1632 else 1633 sc->dc_cachesize = pci_read_config(dev, 1634 DC_PCI_CFLT, 4) & 0xFF; 1635 1636 /* Reset the adapter. */ 1637 dc_reset(sc); 1638 1639 /* Take 21143 out of snooze mode */ 1640 if (DC_IS_INTEL(sc)) { 1641 command = pci_read_config(dev, DC_PCI_CFDD, 4); 1642 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 1643 pci_write_config(dev, DC_PCI_CFDD, command, 4); 1644 } 1645 1646 /* 1647 * Try to learn something about the supported media. 1648 * We know that ASIX and ADMtek and Davicom devices 1649 * will *always* be using MII media, so that's a no-brainer. 1650 * The tricky ones are the Macronix/PNIC II and the 1651 * Intel 21143. 1652 */ 1653 if (DC_IS_INTEL(sc)) { 1654 u_int32_t media, cwuc; 1655 cwuc = pci_read_config(dev, DC_PCI_CWUC, 4); 1656 cwuc |= DC_CWUC_FORCE_WUL; 1657 pci_write_config(dev, DC_PCI_CWUC, cwuc, 4); 1658 DELAY(10000); 1659 media = pci_read_config(dev, DC_PCI_CWUC, 4); 1660 cwuc &= ~DC_CWUC_FORCE_WUL; 1661 pci_write_config(dev, DC_PCI_CWUC, cwuc, 4); 1662 DELAY(10000); 1663 if (media & DC_CWUC_MII_ABILITY) 1664 sc->dc_pmode = DC_PMODE_MII; 1665 if (media & DC_CWUC_SYM_ABILITY) { 1666 sc->dc_pmode = DC_PMODE_SYM; 1667 sc->dc_flags |= DC_21143_NWAY; 1668 } 1669 /* 1670 * If none of the bits are set, then this NIC 1671 * isn't meant to support 'wake up LAN' mode. 1672 * This is usually only the case on multiport 1673 * cards, and these cards almost always have 1674 * MII transceivers. 1675 */ 1676 if (media == 0) 1677 sc->dc_pmode = DC_PMODE_MII; 1678 } else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 1679 if (sc->dc_type == DC_TYPE_98713) 1680 sc->dc_pmode = DC_PMODE_MII; 1681 else 1682 sc->dc_pmode = DC_PMODE_SYM; 1683 } else if (!sc->dc_pmode) 1684 sc->dc_pmode = DC_PMODE_MII; 1685 1686 /* 1687 * Get station address from the EEPROM. 1688 */ 1689 switch(sc->dc_type) { 1690 case DC_TYPE_98713: 1691 case DC_TYPE_98713A: 1692 case DC_TYPE_987x5: 1693 case DC_TYPE_PNICII: 1694 dc_read_eeprom(sc, (caddr_t)&mac_offset, 1695 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 1696 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 1697 break; 1698 case DC_TYPE_PNIC: 1699 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 1700 break; 1701 case DC_TYPE_DM9102: 1702 case DC_TYPE_21143: 1703 case DC_TYPE_ASIX: 1704 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 1705 break; 1706 case DC_TYPE_AL981: 1707 case DC_TYPE_AN985: 1708 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_AL_EE_NODEADDR, 3, 0); 1709 break; 1710 default: 1711 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 1712 break; 1713 } 1714 1715 /* 1716 * A 21143 or clone chip was detected. Inform the world. 1717 */ 1718 printf("dc%d: Ethernet address: %6D\n", unit, eaddr, ":"); 1719 1720 sc->dc_unit = unit; 1721 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 1722 1723 sc->dc_ldata = contigmalloc(sizeof(struct dc_list_data), M_DEVBUF, 1724 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1725 1726 if (sc->dc_ldata == NULL) { 1727 printf("dc%d: no memory for list buffers!\n", unit); 1728 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 1729 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 1730 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1731 error = ENXIO; 1732 goto fail; 1733 } 1734 1735 bzero(sc->dc_ldata, sizeof(struct dc_list_data)); 1736 1737 ifp = &sc->arpcom.ac_if; 1738 ifp->if_softc = sc; 1739 ifp->if_unit = unit; 1740 ifp->if_name = "dc"; 1741 ifp->if_mtu = ETHERMTU; 1742 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1743 ifp->if_ioctl = dc_ioctl; 1744 ifp->if_output = ether_output; 1745 ifp->if_start = dc_start; 1746 ifp->if_watchdog = dc_watchdog; 1747 ifp->if_init = dc_init; 1748 ifp->if_baudrate = 10000000; 1749 ifp->if_snd.ifq_maxlen = DC_TX_LIST_CNT - 1; 1750 1751 /* 1752 * Do MII setup. 1753 */ 1754 error = mii_phy_probe(dev, &sc->dc_miibus, 1755 dc_ifmedia_upd, dc_ifmedia_sts); 1756 1757 if (error && DC_IS_INTEL(sc)) { 1758 sc->dc_pmode = DC_PMODE_SYM; 1759 sc->dc_flags |= DC_21143_NWAY; 1760 mii_phy_probe(dev, &sc->dc_miibus, 1761 dc_ifmedia_upd, dc_ifmedia_sts); 1762 error = 0; 1763 } 1764 1765 if (error) { 1766 printf("dc%d: MII without any PHY!\n", sc->dc_unit); 1767 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 1768 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 1769 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1770 error = ENXIO; 1771 goto fail; 1772 } 1773 1774 /* 1775 * Call MI attach routine. 1776 */ 1777 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 1778 callout_handle_init(&sc->dc_stat_ch); 1779 1780 #ifdef __alpha__ 1781 sc->dc_srm_media = 0; 1782 1783 /* Remember the SRM console media setting */ 1784 if (DC_IS_INTEL(sc)) { 1785 command = pci_read_config(dev, DC_PCI_CFDD, 4); 1786 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 1787 switch ((command >> 8) & 0xff) { 1788 case 3: 1789 sc->dc_srm_media = IFM_10_T; 1790 break; 1791 case 4: 1792 sc->dc_srm_media = IFM_10_T | IFM_FDX; 1793 break; 1794 case 5: 1795 sc->dc_srm_media = IFM_100_TX; 1796 break; 1797 case 6: 1798 sc->dc_srm_media = IFM_100_TX | IFM_FDX; 1799 break; 1800 } 1801 if (sc->dc_srm_media) 1802 sc->dc_srm_media |= IFM_ACTIVE | IFM_ETHER; 1803 } 1804 #endif 1805 1806 1807 fail: 1808 splx(s); 1809 1810 return(error); 1811 } 1812 1813 static int dc_detach(dev) 1814 device_t dev; 1815 { 1816 struct dc_softc *sc; 1817 struct ifnet *ifp; 1818 int s; 1819 1820 s = splimp(); 1821 1822 sc = device_get_softc(dev); 1823 ifp = &sc->arpcom.ac_if; 1824 1825 dc_stop(sc); 1826 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 1827 1828 bus_generic_detach(dev); 1829 device_delete_child(dev, sc->dc_miibus); 1830 1831 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 1832 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 1833 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1834 1835 contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF); 1836 if (sc->dc_pnic_rx_buf != NULL) 1837 free(sc->dc_pnic_rx_buf, M_DEVBUF); 1838 1839 splx(s); 1840 1841 return(0); 1842 } 1843 1844 /* 1845 * Initialize the transmit descriptors. 1846 */ 1847 static int dc_list_tx_init(sc) 1848 struct dc_softc *sc; 1849 { 1850 struct dc_chain_data *cd; 1851 struct dc_list_data *ld; 1852 int i; 1853 1854 cd = &sc->dc_cdata; 1855 ld = sc->dc_ldata; 1856 for (i = 0; i < DC_TX_LIST_CNT; i++) { 1857 if (i == (DC_TX_LIST_CNT - 1)) { 1858 ld->dc_tx_list[i].dc_next = 1859 vtophys(&ld->dc_tx_list[0]); 1860 } else { 1861 ld->dc_tx_list[i].dc_next = 1862 vtophys(&ld->dc_tx_list[i + 1]); 1863 } 1864 cd->dc_tx_chain[i] = NULL; 1865 ld->dc_tx_list[i].dc_data = 0; 1866 ld->dc_tx_list[i].dc_ctl = 0; 1867 } 1868 1869 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 1870 1871 return(0); 1872 } 1873 1874 1875 /* 1876 * Initialize the RX descriptors and allocate mbufs for them. Note that 1877 * we arrange the descriptors in a closed ring, so that the last descriptor 1878 * points back to the first. 1879 */ 1880 static int dc_list_rx_init(sc) 1881 struct dc_softc *sc; 1882 { 1883 struct dc_chain_data *cd; 1884 struct dc_list_data *ld; 1885 int i; 1886 1887 cd = &sc->dc_cdata; 1888 ld = sc->dc_ldata; 1889 1890 for (i = 0; i < DC_RX_LIST_CNT; i++) { 1891 if (dc_newbuf(sc, i, NULL) == ENOBUFS) 1892 return(ENOBUFS); 1893 if (i == (DC_RX_LIST_CNT - 1)) { 1894 ld->dc_rx_list[i].dc_next = 1895 vtophys(&ld->dc_rx_list[0]); 1896 } else { 1897 ld->dc_rx_list[i].dc_next = 1898 vtophys(&ld->dc_rx_list[i + 1]); 1899 } 1900 } 1901 1902 cd->dc_rx_prod = 0; 1903 1904 return(0); 1905 } 1906 1907 /* 1908 * Initialize an RX descriptor and attach an MBUF cluster. 1909 */ 1910 static int dc_newbuf(sc, i, m) 1911 struct dc_softc *sc; 1912 int i; 1913 struct mbuf *m; 1914 { 1915 struct mbuf *m_new = NULL; 1916 struct dc_desc *c; 1917 1918 c = &sc->dc_ldata->dc_rx_list[i]; 1919 1920 if (m == NULL) { 1921 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1922 if (m_new == NULL) { 1923 printf("dc%d: no memory for rx list " 1924 "-- packet dropped!\n", sc->dc_unit); 1925 return(ENOBUFS); 1926 } 1927 1928 MCLGET(m_new, M_DONTWAIT); 1929 if (!(m_new->m_flags & M_EXT)) { 1930 printf("dc%d: no memory for rx list " 1931 "-- packet dropped!\n", sc->dc_unit); 1932 m_freem(m_new); 1933 return(ENOBUFS); 1934 } 1935 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1936 } else { 1937 m_new = m; 1938 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1939 m_new->m_data = m_new->m_ext.ext_buf; 1940 } 1941 1942 m_adj(m_new, sizeof(u_int64_t)); 1943 1944 /* 1945 * If this is a PNIC chip, zero the buffer. This is part 1946 * of the workaround for the receive bug in the 82c168 and 1947 * 82c169 chips. 1948 */ 1949 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 1950 bzero((char *)mtod(m_new, char *), m_new->m_len); 1951 1952 sc->dc_cdata.dc_rx_chain[i] = m_new; 1953 c->dc_data = vtophys(mtod(m_new, caddr_t)); 1954 c->dc_ctl = DC_RXCTL_RLINK | DC_RXLEN; 1955 c->dc_status = DC_RXSTAT_OWN; 1956 1957 return(0); 1958 } 1959 1960 /* 1961 * Grrrrr. 1962 * The PNIC chip has a terrible bug in it that manifests itself during 1963 * periods of heavy activity. The exact mode of failure if difficult to 1964 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 1965 * will happen on slow machines. The bug is that sometimes instead of 1966 * uploading one complete frame during reception, it uploads what looks 1967 * like the entire contents of its FIFO memory. The frame we want is at 1968 * the end of the whole mess, but we never know exactly how much data has 1969 * been uploaded, so salvaging the frame is hard. 1970 * 1971 * There is only one way to do it reliably, and it's disgusting. 1972 * Here's what we know: 1973 * 1974 * - We know there will always be somewhere between one and three extra 1975 * descriptors uploaded. 1976 * 1977 * - We know the desired received frame will always be at the end of the 1978 * total data upload. 1979 * 1980 * - We know the size of the desired received frame because it will be 1981 * provided in the length field of the status word in the last descriptor. 1982 * 1983 * Here's what we do: 1984 * 1985 * - When we allocate buffers for the receive ring, we bzero() them. 1986 * This means that we know that the buffer contents should be all 1987 * zeros, except for data uploaded by the chip. 1988 * 1989 * - We also force the PNIC chip to upload frames that include the 1990 * ethernet CRC at the end. 1991 * 1992 * - We gather all of the bogus frame data into a single buffer. 1993 * 1994 * - We then position a pointer at the end of this buffer and scan 1995 * backwards until we encounter the first non-zero byte of data. 1996 * This is the end of the received frame. We know we will encounter 1997 * some data at the end of the frame because the CRC will always be 1998 * there, so even if the sender transmits a packet of all zeros, 1999 * we won't be fooled. 2000 * 2001 * - We know the size of the actual received frame, so we subtract 2002 * that value from the current pointer location. This brings us 2003 * to the start of the actual received packet. 2004 * 2005 * - We copy this into an mbuf and pass it on, along with the actual 2006 * frame length. 2007 * 2008 * The performance hit is tremendous, but it beats dropping frames all 2009 * the time. 2010 */ 2011 2012 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG) 2013 static void dc_pnic_rx_bug_war(sc, idx) 2014 struct dc_softc *sc; 2015 int idx; 2016 { 2017 struct dc_desc *cur_rx; 2018 struct dc_desc *c = NULL; 2019 struct mbuf *m = NULL; 2020 unsigned char *ptr; 2021 int i, total_len; 2022 u_int32_t rxstat = 0; 2023 2024 i = sc->dc_pnic_rx_bug_save; 2025 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2026 ptr = sc->dc_pnic_rx_buf; 2027 bzero(ptr, sizeof(DC_RXLEN * 5)); 2028 2029 /* Copy all the bytes from the bogus buffers. */ 2030 while (1) { 2031 c = &sc->dc_ldata->dc_rx_list[i]; 2032 rxstat = c->dc_status; 2033 m = sc->dc_cdata.dc_rx_chain[i]; 2034 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2035 ptr += DC_RXLEN; 2036 /* If this is the last buffer, break out. */ 2037 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2038 break; 2039 dc_newbuf(sc, i, m); 2040 DC_INC(i, DC_RX_LIST_CNT); 2041 } 2042 2043 /* Find the length of the actual receive frame. */ 2044 total_len = DC_RXBYTES(rxstat); 2045 2046 /* Scan backwards until we hit a non-zero byte. */ 2047 while(*ptr == 0x00) 2048 ptr--; 2049 2050 /* Round off. */ 2051 if ((uintptr_t)(ptr) & 0x3) 2052 ptr -= 1; 2053 2054 /* Now find the start of the frame. */ 2055 ptr -= total_len; 2056 if (ptr < sc->dc_pnic_rx_buf) 2057 ptr = sc->dc_pnic_rx_buf; 2058 2059 /* 2060 * Now copy the salvaged frame to the last mbuf and fake up 2061 * the status word to make it look like a successful 2062 * frame reception. 2063 */ 2064 dc_newbuf(sc, i, m); 2065 bcopy(ptr, mtod(m, char *), total_len); 2066 cur_rx->dc_status = rxstat | DC_RXSTAT_FIRSTFRAG; 2067 2068 return; 2069 } 2070 2071 /* 2072 * This routine searches the RX ring for dirty descriptors in the 2073 * event that the rxeof routine falls out of sync with the chip's 2074 * current descriptor pointer. This may happen sometimes as a result 2075 * of a "no RX buffer available" condition that happens when the chip 2076 * consumes all of the RX buffers before the driver has a chance to 2077 * process the RX ring. This routine may need to be called more than 2078 * once to bring the driver back in sync with the chip, however we 2079 * should still be getting RX DONE interrupts to drive the search 2080 * for new packets in the RX ring, so we should catch up eventually. 2081 */ 2082 static int dc_rx_resync(sc) 2083 struct dc_softc *sc; 2084 { 2085 int i, pos; 2086 struct dc_desc *cur_rx; 2087 2088 pos = sc->dc_cdata.dc_rx_prod; 2089 2090 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2091 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2092 if (!(cur_rx->dc_status & DC_RXSTAT_OWN)) 2093 break; 2094 DC_INC(pos, DC_RX_LIST_CNT); 2095 } 2096 2097 /* If the ring really is empty, then just return. */ 2098 if (i == DC_RX_LIST_CNT) 2099 return(0); 2100 2101 /* We've fallen behing the chip: catch it. */ 2102 sc->dc_cdata.dc_rx_prod = pos; 2103 2104 return(EAGAIN); 2105 } 2106 2107 /* 2108 * A frame has been uploaded: pass the resulting mbuf chain up to 2109 * the higher level protocols. 2110 */ 2111 static void dc_rxeof(sc) 2112 struct dc_softc *sc; 2113 { 2114 struct ether_header *eh; 2115 struct mbuf *m; 2116 struct ifnet *ifp; 2117 struct dc_desc *cur_rx; 2118 int i, total_len = 0; 2119 u_int32_t rxstat; 2120 2121 ifp = &sc->arpcom.ac_if; 2122 i = sc->dc_cdata.dc_rx_prod; 2123 2124 while(!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) { 2125 struct mbuf *m0 = NULL; 2126 2127 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2128 rxstat = cur_rx->dc_status; 2129 m = sc->dc_cdata.dc_rx_chain[i]; 2130 total_len = DC_RXBYTES(rxstat); 2131 2132 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2133 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2134 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2135 sc->dc_pnic_rx_bug_save = i; 2136 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2137 DC_INC(i, DC_RX_LIST_CNT); 2138 continue; 2139 } 2140 dc_pnic_rx_bug_war(sc, i); 2141 rxstat = cur_rx->dc_status; 2142 total_len = DC_RXBYTES(rxstat); 2143 } 2144 } 2145 2146 sc->dc_cdata.dc_rx_chain[i] = NULL; 2147 2148 /* 2149 * If an error occurs, update stats, clear the 2150 * status word and leave the mbuf cluster in place: 2151 * it should simply get re-used next time this descriptor 2152 * comes up in the ring. 2153 */ 2154 if (rxstat & DC_RXSTAT_RXERR) { 2155 ifp->if_ierrors++; 2156 if (rxstat & DC_RXSTAT_COLLSEEN) 2157 ifp->if_collisions++; 2158 dc_newbuf(sc, i, m); 2159 if (rxstat & DC_RXSTAT_CRCERR) { 2160 DC_INC(i, DC_RX_LIST_CNT); 2161 continue; 2162 } else { 2163 dc_init(sc); 2164 return; 2165 } 2166 } 2167 2168 /* No errors; receive the packet. */ 2169 total_len -= ETHER_CRC_LEN; 2170 2171 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 2172 total_len + ETHER_ALIGN, 0, ifp, NULL); 2173 dc_newbuf(sc, i, m); 2174 DC_INC(i, DC_RX_LIST_CNT); 2175 if (m0 == NULL) { 2176 ifp->if_ierrors++; 2177 continue; 2178 } 2179 m_adj(m0, ETHER_ALIGN); 2180 m = m0; 2181 2182 ifp->if_ipackets++; 2183 eh = mtod(m, struct ether_header *); 2184 2185 /* Remove header from mbuf and pass it on. */ 2186 m_adj(m, sizeof(struct ether_header)); 2187 ether_input(ifp, eh, m); 2188 } 2189 2190 sc->dc_cdata.dc_rx_prod = i; 2191 } 2192 2193 /* 2194 * A frame was downloaded to the chip. It's safe for us to clean up 2195 * the list buffers. 2196 */ 2197 2198 static void dc_txeof(sc) 2199 struct dc_softc *sc; 2200 { 2201 struct dc_desc *cur_tx = NULL; 2202 struct ifnet *ifp; 2203 int idx; 2204 2205 ifp = &sc->arpcom.ac_if; 2206 2207 /* Clear the timeout timer. */ 2208 ifp->if_timer = 0; 2209 2210 /* 2211 * Go through our tx list and free mbufs for those 2212 * frames that have been transmitted. 2213 */ 2214 idx = sc->dc_cdata.dc_tx_cons; 2215 while(idx != sc->dc_cdata.dc_tx_prod) { 2216 u_int32_t txstat; 2217 2218 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2219 txstat = cur_tx->dc_status; 2220 2221 if (txstat & DC_TXSTAT_OWN) 2222 break; 2223 2224 if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) || 2225 cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2226 sc->dc_cdata.dc_tx_cnt--; 2227 if (cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2228 /* 2229 * Yes, the PNIC is so brain damaged 2230 * that it will sometimes generate a TX 2231 * underrun error while DMAing the RX 2232 * filter setup frame. If we detect this, 2233 * we have to send the setup frame again, 2234 * or else the filter won't be programmed 2235 * correctly. 2236 */ 2237 if (DC_IS_PNIC(sc)) { 2238 if (txstat & DC_TXSTAT_ERRSUM) 2239 dc_setfilt(sc); 2240 } 2241 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2242 } 2243 DC_INC(idx, DC_TX_LIST_CNT); 2244 continue; 2245 } 2246 2247 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2248 sc->dc_pmode == DC_PMODE_MII && 2249 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2250 DC_TXSTAT_NOCARRIER|DC_TXSTAT_CARRLOST))) 2251 txstat &= ~DC_TXSTAT_ERRSUM; 2252 2253 if (txstat & DC_TXSTAT_ERRSUM) { 2254 ifp->if_oerrors++; 2255 if (txstat & DC_TXSTAT_EXCESSCOLL) 2256 ifp->if_collisions++; 2257 if (txstat & DC_TXSTAT_LATECOLL) 2258 ifp->if_collisions++; 2259 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2260 dc_init(sc); 2261 return; 2262 } 2263 } 2264 2265 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2266 2267 ifp->if_opackets++; 2268 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2269 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2270 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2271 } 2272 2273 sc->dc_cdata.dc_tx_cnt--; 2274 DC_INC(idx, DC_TX_LIST_CNT); 2275 } 2276 2277 sc->dc_cdata.dc_tx_cons = idx; 2278 if (cur_tx != NULL) 2279 ifp->if_flags &= ~IFF_OACTIVE; 2280 2281 return; 2282 } 2283 2284 static void dc_tick(xsc) 2285 void *xsc; 2286 { 2287 struct dc_softc *sc; 2288 struct mii_data *mii; 2289 struct ifnet *ifp; 2290 int s; 2291 u_int32_t r; 2292 2293 s = splimp(); 2294 2295 sc = xsc; 2296 ifp = &sc->arpcom.ac_if; 2297 mii = device_get_softc(sc->dc_miibus); 2298 2299 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2300 if (sc->dc_flags & DC_21143_NWAY) { 2301 r = CSR_READ_4(sc, DC_10BTSTAT); 2302 if (IFM_SUBTYPE(mii->mii_media_active) == 2303 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2304 sc->dc_link = 0; 2305 mii_mediachg(mii); 2306 } 2307 if (IFM_SUBTYPE(mii->mii_media_active) == 2308 IFM_10_T && (r & DC_TSTAT_LS10)) { 2309 sc->dc_link = 0; 2310 mii_mediachg(mii); 2311 } 2312 if (sc->dc_link == 0) 2313 mii_tick(mii); 2314 } else { 2315 r = CSR_READ_4(sc, DC_ISR); 2316 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2317 sc->dc_cdata.dc_tx_cnt == 0) 2318 mii_tick(mii); 2319 if (!(mii->mii_media_status & IFM_ACTIVE)) 2320 sc->dc_link = 0; 2321 } 2322 } else 2323 mii_tick(mii); 2324 2325 /* 2326 * When the init routine completes, we expect to be able to send 2327 * packets right away, and in fact the network code will send a 2328 * gratuitous ARP the moment the init routine marks the interface 2329 * as running. However, even though the MAC may have been initialized, 2330 * there may be a delay of a few seconds before the PHY completes 2331 * autonegotiation and the link is brought up. Any transmissions 2332 * made during that delay will be lost. Dealing with this is tricky: 2333 * we can't just pause in the init routine while waiting for the 2334 * PHY to come ready since that would bring the whole system to 2335 * a screeching halt for several seconds. 2336 * 2337 * What we do here is prevent the TX start routine from sending 2338 * any packets until a link has been established. After the 2339 * interface has been initialized, the tick routine will poll 2340 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2341 * that time, packets will stay in the send queue, and once the 2342 * link comes up, they will be flushed out to the wire. 2343 */ 2344 if (!sc->dc_link) { 2345 mii_pollstat(mii); 2346 if (mii->mii_media_status & IFM_ACTIVE && 2347 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2348 sc->dc_link++; 2349 if (ifp->if_snd.ifq_head != NULL) 2350 dc_start(ifp); 2351 } 2352 } 2353 2354 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 2355 sc->dc_stat_ch = timeout(dc_tick, sc, hz/10); 2356 else 2357 sc->dc_stat_ch = timeout(dc_tick, sc, hz); 2358 2359 splx(s); 2360 2361 return; 2362 } 2363 2364 static void dc_intr(arg) 2365 void *arg; 2366 { 2367 struct dc_softc *sc; 2368 struct ifnet *ifp; 2369 u_int32_t status; 2370 2371 sc = arg; 2372 ifp = &sc->arpcom.ac_if; 2373 2374 /* Supress unwanted interrupts */ 2375 if (!(ifp->if_flags & IFF_UP)) { 2376 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 2377 dc_stop(sc); 2378 return; 2379 } 2380 2381 /* Disable interrupts. */ 2382 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2383 2384 while((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) { 2385 2386 CSR_WRITE_4(sc, DC_ISR, status); 2387 2388 if (status & DC_ISR_RX_OK) { 2389 int curpkts; 2390 curpkts = ifp->if_ipackets; 2391 dc_rxeof(sc); 2392 if (curpkts == ifp->if_ipackets) { 2393 while(dc_rx_resync(sc)) 2394 dc_rxeof(sc); 2395 } 2396 } 2397 2398 if (status & (DC_ISR_TX_OK|DC_ISR_TX_NOBUF)) 2399 dc_txeof(sc); 2400 2401 if (status & DC_ISR_TX_IDLE) { 2402 dc_txeof(sc); 2403 if (sc->dc_cdata.dc_tx_cnt) { 2404 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2405 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2406 } 2407 } 2408 2409 if (status & DC_ISR_TX_UNDERRUN) { 2410 u_int32_t cfg; 2411 2412 printf("dc%d: TX underrun -- ", sc->dc_unit); 2413 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) 2414 dc_init(sc); 2415 cfg = CSR_READ_4(sc, DC_NETCFG); 2416 cfg &= ~DC_NETCFG_TX_THRESH; 2417 if (sc->dc_txthresh == DC_TXTHRESH_160BYTES) { 2418 printf("using store and forward mode\n"); 2419 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2420 } else if (sc->dc_flags & DC_TX_STORENFWD) { 2421 printf("resetting\n"); 2422 } else { 2423 sc->dc_txthresh += 0x4000; 2424 printf("increasing TX threshold\n"); 2425 CSR_WRITE_4(sc, DC_NETCFG, cfg); 2426 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2427 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2428 } 2429 } 2430 2431 if ((status & DC_ISR_RX_WATDOGTIMEO) 2432 || (status & DC_ISR_RX_NOBUF)) { 2433 int curpkts; 2434 curpkts = ifp->if_ipackets; 2435 dc_rxeof(sc); 2436 if (curpkts == ifp->if_ipackets) { 2437 while(dc_rx_resync(sc)) 2438 dc_rxeof(sc); 2439 } 2440 } 2441 2442 if (status & DC_ISR_BUS_ERR) { 2443 dc_reset(sc); 2444 dc_init(sc); 2445 } 2446 } 2447 2448 /* Re-enable interrupts. */ 2449 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2450 2451 if (ifp->if_snd.ifq_head != NULL) 2452 dc_start(ifp); 2453 2454 return; 2455 } 2456 2457 /* 2458 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2459 * pointers to the fragment pointers. 2460 */ 2461 static int dc_encap(sc, m_head, txidx) 2462 struct dc_softc *sc; 2463 struct mbuf *m_head; 2464 u_int32_t *txidx; 2465 { 2466 struct dc_desc *f = NULL; 2467 struct mbuf *m; 2468 int frag, cur, cnt = 0; 2469 2470 /* 2471 * Start packing the mbufs in this chain into 2472 * the fragment pointers. Stop when we run out 2473 * of fragments or hit the end of the mbuf chain. 2474 */ 2475 m = m_head; 2476 cur = frag = *txidx; 2477 2478 for (m = m_head; m != NULL; m = m->m_next) { 2479 if (m->m_len != 0) { 2480 if (sc->dc_flags & DC_TX_ADMTEK_WAR) { 2481 if (*txidx != sc->dc_cdata.dc_tx_prod && 2482 frag == (DC_TX_LIST_CNT - 1)) 2483 return(ENOBUFS); 2484 } 2485 if ((DC_TX_LIST_CNT - 2486 (sc->dc_cdata.dc_tx_cnt + cnt)) < 5) 2487 return(ENOBUFS); 2488 2489 f = &sc->dc_ldata->dc_tx_list[frag]; 2490 f->dc_ctl = DC_TXCTL_TLINK | m->m_len; 2491 if (cnt == 0) { 2492 f->dc_status = 0; 2493 f->dc_ctl |= DC_TXCTL_FIRSTFRAG; 2494 } else 2495 f->dc_status = DC_TXSTAT_OWN; 2496 f->dc_data = vtophys(mtod(m, vm_offset_t)); 2497 cur = frag; 2498 DC_INC(frag, DC_TX_LIST_CNT); 2499 cnt++; 2500 } 2501 } 2502 2503 if (m != NULL) 2504 return(ENOBUFS); 2505 2506 sc->dc_cdata.dc_tx_cnt += cnt; 2507 sc->dc_cdata.dc_tx_chain[cur] = m_head; 2508 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_LASTFRAG; 2509 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 2510 sc->dc_ldata->dc_tx_list[*txidx].dc_ctl |= DC_TXCTL_FINT; 2511 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 2512 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 2513 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 2514 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 2515 sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN; 2516 *txidx = frag; 2517 2518 return(0); 2519 } 2520 2521 /* 2522 * Coalesce an mbuf chain into a single mbuf cluster buffer. 2523 * Needed for some really badly behaved chips that just can't 2524 * do scatter/gather correctly. 2525 */ 2526 static int dc_coal(sc, m_head) 2527 struct dc_softc *sc; 2528 struct mbuf **m_head; 2529 { 2530 struct mbuf *m_new, *m; 2531 2532 m = *m_head; 2533 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 2534 if (m_new == NULL) { 2535 printf("dc%d: no memory for tx list", sc->dc_unit); 2536 return(ENOBUFS); 2537 } 2538 if (m->m_pkthdr.len > MHLEN) { 2539 MCLGET(m_new, M_DONTWAIT); 2540 if (!(m_new->m_flags & M_EXT)) { 2541 m_freem(m_new); 2542 printf("dc%d: no memory for tx list", sc->dc_unit); 2543 return(ENOBUFS); 2544 } 2545 } 2546 m_copydata(m, 0, m->m_pkthdr.len, mtod(m_new, caddr_t)); 2547 m_new->m_pkthdr.len = m_new->m_len = m->m_pkthdr.len; 2548 m_freem(m); 2549 *m_head = m_new; 2550 2551 return(0); 2552 } 2553 2554 /* 2555 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2556 * to the mbuf data regions directly in the transmit lists. We also save a 2557 * copy of the pointers since the transmit list fragment pointers are 2558 * physical addresses. 2559 */ 2560 2561 static void dc_start(ifp) 2562 struct ifnet *ifp; 2563 { 2564 struct dc_softc *sc; 2565 struct mbuf *m_head = NULL; 2566 int idx; 2567 2568 sc = ifp->if_softc; 2569 2570 if (!sc->dc_link) 2571 return; 2572 2573 if (ifp->if_flags & IFF_OACTIVE) 2574 return; 2575 2576 idx = sc->dc_cdata.dc_tx_prod; 2577 2578 while(sc->dc_cdata.dc_tx_chain[idx] == NULL) { 2579 IF_DEQUEUE(&ifp->if_snd, m_head); 2580 if (m_head == NULL) 2581 break; 2582 2583 if (sc->dc_flags & DC_TX_COALESCE) { 2584 if (dc_coal(sc, &m_head)) { 2585 IF_PREPEND(&ifp->if_snd, m_head); 2586 ifp->if_flags |= IFF_OACTIVE; 2587 break; 2588 } 2589 } 2590 2591 if (dc_encap(sc, m_head, &idx)) { 2592 IF_PREPEND(&ifp->if_snd, m_head); 2593 ifp->if_flags |= IFF_OACTIVE; 2594 break; 2595 } 2596 2597 /* 2598 * If there's a BPF listener, bounce a copy of this frame 2599 * to him. 2600 */ 2601 if (ifp->if_bpf) 2602 bpf_mtap(ifp, m_head); 2603 } 2604 2605 /* Transmit */ 2606 sc->dc_cdata.dc_tx_prod = idx; 2607 if (!(sc->dc_flags & DC_TX_POLL)) 2608 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2609 2610 /* 2611 * Set a timeout in case the chip goes out to lunch. 2612 */ 2613 ifp->if_timer = 5; 2614 2615 return; 2616 } 2617 2618 static void dc_init(xsc) 2619 void *xsc; 2620 { 2621 struct dc_softc *sc = xsc; 2622 struct ifnet *ifp = &sc->arpcom.ac_if; 2623 struct mii_data *mii; 2624 int s; 2625 2626 s = splimp(); 2627 2628 mii = device_get_softc(sc->dc_miibus); 2629 2630 /* 2631 * Cancel pending I/O and free all RX/TX buffers. 2632 */ 2633 dc_stop(sc); 2634 dc_reset(sc); 2635 2636 /* 2637 * Set cache alignment and burst length. 2638 */ 2639 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 2640 CSR_WRITE_4(sc, DC_BUSCTL, 0); 2641 else 2642 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE); 2643 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 2644 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 2645 } else { 2646 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 2647 } 2648 if (sc->dc_flags & DC_TX_POLL) 2649 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 2650 switch(sc->dc_cachesize) { 2651 case 32: 2652 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 2653 break; 2654 case 16: 2655 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 2656 break; 2657 case 8: 2658 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 2659 break; 2660 case 0: 2661 default: 2662 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 2663 break; 2664 } 2665 2666 if (sc->dc_flags & DC_TX_STORENFWD) 2667 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2668 else { 2669 if (sc->dc_txthresh == DC_TXTHRESH_160BYTES) { 2670 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2671 } else { 2672 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2673 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2674 } 2675 } 2676 2677 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 2678 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 2679 2680 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2681 /* 2682 * The app notes for the 98713 and 98715A say that 2683 * in order to have the chips operate properly, a magic 2684 * number must be written to CSR16. Macronix does not 2685 * document the meaning of these bits so there's no way 2686 * to know exactly what they do. The 98713 has a magic 2687 * number all its own; the rest all use a different one. 2688 */ 2689 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 2690 if (sc->dc_type == DC_TYPE_98713) 2691 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 2692 else 2693 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 2694 } 2695 2696 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 2697 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_72BYTES); 2698 2699 /* Init circular RX list. */ 2700 if (dc_list_rx_init(sc) == ENOBUFS) { 2701 printf("dc%d: initialization failed: no " 2702 "memory for rx buffers\n", sc->dc_unit); 2703 dc_stop(sc); 2704 (void)splx(s); 2705 return; 2706 } 2707 2708 /* 2709 * Init tx descriptors. 2710 */ 2711 dc_list_tx_init(sc); 2712 2713 /* 2714 * Load the address of the RX list. 2715 */ 2716 CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0])); 2717 CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0])); 2718 2719 /* 2720 * Enable interrupts. 2721 */ 2722 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2723 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 2724 2725 /* Enable transmitter. */ 2726 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2727 2728 /* 2729 * Load the RX/multicast filter. We do this sort of late 2730 * because the filter programming scheme on the 21143 and 2731 * some clones requires DMAing a setup frame via the TX 2732 * engine, and we need the transmitter enabled for that. 2733 */ 2734 dc_setfilt(sc); 2735 2736 /* Enable receiver. */ 2737 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 2738 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 2739 2740 mii_mediachg(mii); 2741 dc_setcfg(sc, sc->dc_if_media); 2742 2743 ifp->if_flags |= IFF_RUNNING; 2744 ifp->if_flags &= ~IFF_OACTIVE; 2745 2746 (void)splx(s); 2747 2748 if (sc->dc_flags & DC_21143_NWAY) 2749 sc->dc_stat_ch = timeout(dc_tick, sc, hz/10); 2750 else 2751 sc->dc_stat_ch = timeout(dc_tick, sc, hz); 2752 2753 #ifdef __alpha__ 2754 if(sc->dc_srm_media) { 2755 struct ifreq ifr; 2756 2757 ifr.ifr_media = sc->dc_srm_media; 2758 ifmedia_ioctl(ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA); 2759 sc->dc_srm_media = 0; 2760 } 2761 #endif 2762 return; 2763 } 2764 2765 /* 2766 * Set media options. 2767 */ 2768 static int dc_ifmedia_upd(ifp) 2769 struct ifnet *ifp; 2770 { 2771 struct dc_softc *sc; 2772 struct mii_data *mii; 2773 struct ifmedia *ifm; 2774 2775 sc = ifp->if_softc; 2776 mii = device_get_softc(sc->dc_miibus); 2777 mii_mediachg(mii); 2778 ifm = &mii->mii_media; 2779 2780 if (DC_IS_DAVICOM(sc) && 2781 IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) 2782 dc_setcfg(sc, ifm->ifm_media); 2783 else 2784 sc->dc_link = 0; 2785 2786 return(0); 2787 } 2788 2789 /* 2790 * Report current media status. 2791 */ 2792 static void dc_ifmedia_sts(ifp, ifmr) 2793 struct ifnet *ifp; 2794 struct ifmediareq *ifmr; 2795 { 2796 struct dc_softc *sc; 2797 struct mii_data *mii; 2798 struct ifmedia *ifm; 2799 2800 sc = ifp->if_softc; 2801 mii = device_get_softc(sc->dc_miibus); 2802 mii_pollstat(mii); 2803 ifm = &mii->mii_media; 2804 if (DC_IS_DAVICOM(sc)) { 2805 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) { 2806 ifmr->ifm_active = ifm->ifm_media; 2807 ifmr->ifm_status = 0; 2808 return; 2809 } 2810 } 2811 ifmr->ifm_active = mii->mii_media_active; 2812 ifmr->ifm_status = mii->mii_media_status; 2813 2814 return; 2815 } 2816 2817 static int dc_ioctl(ifp, command, data) 2818 struct ifnet *ifp; 2819 u_long command; 2820 caddr_t data; 2821 { 2822 struct dc_softc *sc = ifp->if_softc; 2823 struct ifreq *ifr = (struct ifreq *) data; 2824 struct mii_data *mii; 2825 int s, error = 0; 2826 2827 s = splimp(); 2828 2829 switch(command) { 2830 case SIOCSIFADDR: 2831 case SIOCGIFADDR: 2832 case SIOCSIFMTU: 2833 error = ether_ioctl(ifp, command, data); 2834 break; 2835 case SIOCSIFFLAGS: 2836 if (ifp->if_flags & IFF_UP) { 2837 if (ifp->if_flags & IFF_RUNNING && 2838 ifp->if_flags & IFF_PROMISC && 2839 !(sc->dc_if_flags & IFF_PROMISC)) { 2840 dc_setfilt(sc); 2841 } else if (ifp->if_flags & IFF_RUNNING && 2842 !(ifp->if_flags & IFF_PROMISC) && 2843 sc->dc_if_flags & IFF_PROMISC) { 2844 dc_setfilt(sc); 2845 } else if (!(ifp->if_flags & IFF_RUNNING)) { 2846 sc->dc_txthresh = 0; 2847 dc_init(sc); 2848 } 2849 } else { 2850 if (ifp->if_flags & IFF_RUNNING) 2851 dc_stop(sc); 2852 } 2853 sc->dc_if_flags = ifp->if_flags; 2854 error = 0; 2855 break; 2856 case SIOCADDMULTI: 2857 case SIOCDELMULTI: 2858 dc_setfilt(sc); 2859 error = 0; 2860 break; 2861 case SIOCGIFMEDIA: 2862 case SIOCSIFMEDIA: 2863 mii = device_get_softc(sc->dc_miibus); 2864 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2865 #ifdef __alpha__ 2866 if (sc->dc_srm_media) 2867 sc->dc_srm_media = 0; 2868 #endif 2869 break; 2870 default: 2871 error = EINVAL; 2872 break; 2873 } 2874 2875 (void)splx(s); 2876 2877 return(error); 2878 } 2879 2880 static void dc_watchdog(ifp) 2881 struct ifnet *ifp; 2882 { 2883 struct dc_softc *sc; 2884 2885 sc = ifp->if_softc; 2886 2887 ifp->if_oerrors++; 2888 printf("dc%d: watchdog timeout\n", sc->dc_unit); 2889 2890 dc_stop(sc); 2891 dc_reset(sc); 2892 dc_init(sc); 2893 2894 if (ifp->if_snd.ifq_head != NULL) 2895 dc_start(ifp); 2896 2897 return; 2898 } 2899 2900 /* 2901 * Stop the adapter and free any mbufs allocated to the 2902 * RX and TX lists. 2903 */ 2904 static void dc_stop(sc) 2905 struct dc_softc *sc; 2906 { 2907 register int i; 2908 struct ifnet *ifp; 2909 2910 ifp = &sc->arpcom.ac_if; 2911 ifp->if_timer = 0; 2912 2913 untimeout(dc_tick, sc, sc->dc_stat_ch); 2914 2915 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON|DC_NETCFG_TX_ON)); 2916 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2917 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 2918 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 2919 sc->dc_link = 0; 2920 2921 /* 2922 * Free data in the RX lists. 2923 */ 2924 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2925 if (sc->dc_cdata.dc_rx_chain[i] != NULL) { 2926 m_freem(sc->dc_cdata.dc_rx_chain[i]); 2927 sc->dc_cdata.dc_rx_chain[i] = NULL; 2928 } 2929 } 2930 bzero((char *)&sc->dc_ldata->dc_rx_list, 2931 sizeof(sc->dc_ldata->dc_rx_list)); 2932 2933 /* 2934 * Free the TX list buffers. 2935 */ 2936 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2937 if (sc->dc_cdata.dc_tx_chain[i] != NULL) { 2938 if (sc->dc_ldata->dc_tx_list[i].dc_ctl & 2939 DC_TXCTL_SETUP) { 2940 sc->dc_cdata.dc_tx_chain[i] = NULL; 2941 continue; 2942 } 2943 m_freem(sc->dc_cdata.dc_tx_chain[i]); 2944 sc->dc_cdata.dc_tx_chain[i] = NULL; 2945 } 2946 } 2947 2948 bzero((char *)&sc->dc_ldata->dc_tx_list, 2949 sizeof(sc->dc_ldata->dc_tx_list)); 2950 2951 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2952 2953 return; 2954 } 2955 2956 /* 2957 * Stop all chip I/O so that the kernel's probe routines don't 2958 * get confused by errant DMAs when rebooting. 2959 */ 2960 static void dc_shutdown(dev) 2961 device_t dev; 2962 { 2963 struct dc_softc *sc; 2964 2965 sc = device_get_softc(dev); 2966 2967 dc_stop(sc); 2968 2969 return; 2970 } 2971