1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 35 * series chips and several workalikes including the following: 36 * 37 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 38 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 39 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 40 * ASIX Electronics AX88140A (www.asix.com.tw) 41 * ASIX Electronics AX88141 (www.asix.com.tw) 42 * ADMtek AL981 (www.admtek.com.tw) 43 * ADMtek AN985 (www.admtek.com.tw) 44 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 45 * Accton EN1217 (www.accton.com) 46 * Xircom X3201 (www.xircom.com) 47 * Abocom FE2500 48 * Conexant LANfinity (www.conexant.com) 49 * 3Com OfficeConnect 10/100B 3CSOHO100B (www.3com.com) 50 * 51 * Datasheets for the 21143 are available at developer.intel.com. 52 * Datasheets for the clone parts can be found at their respective sites. 53 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 54 * The PNIC II is essentially a Macronix 98715A chip; the only difference 55 * worth noting is that its multicast hash table is only 128 bits wide 56 * instead of 512. 57 * 58 * Written by Bill Paul <wpaul@ee.columbia.edu> 59 * Electrical Engineering Department 60 * Columbia University, New York City 61 */ 62 63 /* 64 * The Intel 21143 is the successor to the DEC 21140. It is basically 65 * the same as the 21140 but with a few new features. The 21143 supports 66 * three kinds of media attachments: 67 * 68 * o MII port, for 10Mbps and 100Mbps support and NWAY 69 * autonegotiation provided by an external PHY. 70 * o SYM port, for symbol mode 100Mbps support. 71 * o 10baseT port. 72 * o AUI/BNC port. 73 * 74 * The 100Mbps SYM port and 10baseT port can be used together in 75 * combination with the internal NWAY support to create a 10/100 76 * autosensing configuration. 77 * 78 * Note that not all tulip workalikes are handled in this driver: we only 79 * deal with those which are relatively well behaved. The Winbond is 80 * handled separately due to its different register offsets and the 81 * special handling needed for its various bugs. The PNIC is handled 82 * here, but I'm not thrilled about it. 83 * 84 * All of the workalike chips use some form of MII transceiver support 85 * with the exception of the Macronix chips, which also have a SYM port. 86 * The ASIX AX88140A is also documented to have a SYM port, but all 87 * the cards I've seen use an MII transceiver, probably because the 88 * AX88140A doesn't support internal NWAY. 89 */ 90 91 #include <sys/cdefs.h> 92 __FBSDID("$FreeBSD$"); 93 94 #include <sys/param.h> 95 #include <sys/systm.h> 96 #include <sys/sockio.h> 97 #include <sys/mbuf.h> 98 #include <sys/malloc.h> 99 #include <sys/kernel.h> 100 #include <sys/socket.h> 101 #include <sys/sysctl.h> 102 103 #include <net/if.h> 104 #include <net/if_arp.h> 105 #include <net/ethernet.h> 106 #include <net/if_dl.h> 107 #include <net/if_media.h> 108 #include <net/if_types.h> 109 #include <net/if_vlan_var.h> 110 111 #include <net/bpf.h> 112 113 #include <vm/vm.h> /* for vtophys */ 114 #include <vm/pmap.h> /* for vtophys */ 115 #include <machine/bus_pio.h> 116 #include <machine/bus_memio.h> 117 #include <machine/bus.h> 118 #include <machine/resource.h> 119 #include <sys/bus.h> 120 #include <sys/rman.h> 121 122 #include <dev/mii/mii.h> 123 #include <dev/mii/miivar.h> 124 125 #include <pci/pcireg.h> 126 #include <pci/pcivar.h> 127 128 #define DC_USEIOSPACE 129 #ifdef __alpha__ 130 #define SRM_MEDIA 131 #endif 132 133 #include <pci/if_dcreg.h> 134 135 MODULE_DEPEND(dc, pci, 1, 1, 1); 136 MODULE_DEPEND(dc, ether, 1, 1, 1); 137 MODULE_DEPEND(dc, miibus, 1, 1, 1); 138 139 /* "controller miibus0" required. See GENERIC if you get errors here. */ 140 #include "miibus_if.h" 141 142 /* 143 * Various supported device vendors/types and their names. 144 */ 145 static struct dc_type dc_devs[] = { 146 { DC_VENDORID_DEC, DC_DEVICEID_21143, 147 "Intel 21143 10/100BaseTX" }, 148 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009, 149 "Davicom DM9009 10/100BaseTX" }, 150 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 151 "Davicom DM9100 10/100BaseTX" }, 152 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 153 "Davicom DM9102 10/100BaseTX" }, 154 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 155 "Davicom DM9102A 10/100BaseTX" }, 156 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 157 "ADMtek AL981 10/100BaseTX" }, 158 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 159 "ADMtek AN985 10/100BaseTX" }, 160 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511, 161 "ADMtek ADM9511 10/100BaseTX" }, 162 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513, 163 "ADMtek ADM9513 10/100BaseTX" }, 164 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 165 "ASIX AX88140A 10/100BaseTX" }, 166 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 167 "ASIX AX88141 10/100BaseTX" }, 168 { DC_VENDORID_MX, DC_DEVICEID_98713, 169 "Macronix 98713 10/100BaseTX" }, 170 { DC_VENDORID_MX, DC_DEVICEID_98713, 171 "Macronix 98713A 10/100BaseTX" }, 172 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 173 "Compex RL100-TX 10/100BaseTX" }, 174 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 175 "Compex RL100-TX 10/100BaseTX" }, 176 { DC_VENDORID_MX, DC_DEVICEID_987x5, 177 "Macronix 98715/98715A 10/100BaseTX" }, 178 { DC_VENDORID_MX, DC_DEVICEID_987x5, 179 "Macronix 98715AEC-C 10/100BaseTX" }, 180 { DC_VENDORID_MX, DC_DEVICEID_987x5, 181 "Macronix 98725 10/100BaseTX" }, 182 { DC_VENDORID_MX, DC_DEVICEID_98727, 183 "Macronix 98727/98732 10/100BaseTX" }, 184 { DC_VENDORID_LO, DC_DEVICEID_82C115, 185 "LC82C115 PNIC II 10/100BaseTX" }, 186 { DC_VENDORID_LO, DC_DEVICEID_82C168, 187 "82c168 PNIC 10/100BaseTX" }, 188 { DC_VENDORID_LO, DC_DEVICEID_82C168, 189 "82c169 PNIC 10/100BaseTX" }, 190 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217, 191 "Accton EN1217 10/100BaseTX" }, 192 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242, 193 "Accton EN2242 MiniPCI 10/100BaseTX" }, 194 { DC_VENDORID_XIRCOM, DC_DEVICEID_X3201, 195 "Xircom X3201 10/100BaseTX" }, 196 { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500, 197 "Abocom FE2500 10/100BaseTX" }, 198 { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112, 199 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 200 { DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX, 201 "Hawking CB102 CardBus 10/100" }, 202 { DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T, 203 "PlaneX FNW-3602-T CardBus 10/100" }, 204 { DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB, 205 "3Com OfficeConnect 10/100B" }, 206 { 0, 0, NULL } 207 }; 208 209 static int dc_probe (device_t); 210 static int dc_attach (device_t); 211 static int dc_detach (device_t); 212 static int dc_suspend (device_t); 213 static int dc_resume (device_t); 214 #ifndef BURN_BRIDGES 215 static void dc_acpi (device_t); 216 #endif 217 static struct dc_type *dc_devtype (device_t); 218 static int dc_newbuf (struct dc_softc *, int, struct mbuf *); 219 static int dc_encap (struct dc_softc *, struct mbuf *, u_int32_t *); 220 static void dc_pnic_rx_bug_war (struct dc_softc *, int); 221 static int dc_rx_resync (struct dc_softc *); 222 static void dc_rxeof (struct dc_softc *); 223 static void dc_txeof (struct dc_softc *); 224 static void dc_tick (void *); 225 static void dc_tx_underrun (struct dc_softc *); 226 static void dc_intr (void *); 227 static void dc_start (struct ifnet *); 228 static int dc_ioctl (struct ifnet *, u_long, caddr_t); 229 static void dc_init (void *); 230 static void dc_stop (struct dc_softc *); 231 static void dc_watchdog (struct ifnet *); 232 static void dc_shutdown (device_t); 233 static int dc_ifmedia_upd (struct ifnet *); 234 static void dc_ifmedia_sts (struct ifnet *, struct ifmediareq *); 235 236 static void dc_delay (struct dc_softc *); 237 static void dc_eeprom_idle (struct dc_softc *); 238 static void dc_eeprom_putbyte (struct dc_softc *, int); 239 static void dc_eeprom_getword (struct dc_softc *, int, u_int16_t *); 240 static void dc_eeprom_getword_pnic 241 (struct dc_softc *, int, u_int16_t *); 242 static void dc_eeprom_getword_xircom 243 (struct dc_softc *, int, u_int16_t *); 244 static void dc_eeprom_width (struct dc_softc *); 245 static void dc_read_eeprom (struct dc_softc *, caddr_t, int, int, int); 246 247 static void dc_mii_writebit (struct dc_softc *, int); 248 static int dc_mii_readbit (struct dc_softc *); 249 static void dc_mii_sync (struct dc_softc *); 250 static void dc_mii_send (struct dc_softc *, u_int32_t, int); 251 static int dc_mii_readreg (struct dc_softc *, struct dc_mii_frame *); 252 static int dc_mii_writereg (struct dc_softc *, struct dc_mii_frame *); 253 static int dc_miibus_readreg (device_t, int, int); 254 static int dc_miibus_writereg (device_t, int, int, int); 255 static void dc_miibus_statchg (device_t); 256 static void dc_miibus_mediainit (device_t); 257 258 static void dc_setcfg (struct dc_softc *, int); 259 static u_int32_t dc_crc_le (struct dc_softc *, caddr_t); 260 static u_int32_t dc_crc_be (caddr_t); 261 static void dc_setfilt_21143 (struct dc_softc *); 262 static void dc_setfilt_asix (struct dc_softc *); 263 static void dc_setfilt_admtek (struct dc_softc *); 264 static void dc_setfilt_xircom (struct dc_softc *); 265 266 static void dc_setfilt (struct dc_softc *); 267 268 static void dc_reset (struct dc_softc *); 269 static int dc_list_rx_init (struct dc_softc *); 270 static int dc_list_tx_init (struct dc_softc *); 271 272 static void dc_read_srom (struct dc_softc *, int); 273 static void dc_parse_21143_srom (struct dc_softc *); 274 static void dc_decode_leaf_sia (struct dc_softc *, struct dc_eblock_sia *); 275 static void dc_decode_leaf_mii (struct dc_softc *, struct dc_eblock_mii *); 276 static void dc_decode_leaf_sym (struct dc_softc *, struct dc_eblock_sym *); 277 static void dc_apply_fixup (struct dc_softc *, int); 278 279 #ifdef DC_USEIOSPACE 280 #define DC_RES SYS_RES_IOPORT 281 #define DC_RID DC_PCI_CFBIO 282 #else 283 #define DC_RES SYS_RES_MEMORY 284 #define DC_RID DC_PCI_CFBMA 285 #endif 286 287 static device_method_t dc_methods[] = { 288 /* Device interface */ 289 DEVMETHOD(device_probe, dc_probe), 290 DEVMETHOD(device_attach, dc_attach), 291 DEVMETHOD(device_detach, dc_detach), 292 DEVMETHOD(device_suspend, dc_suspend), 293 DEVMETHOD(device_resume, dc_resume), 294 DEVMETHOD(device_shutdown, dc_shutdown), 295 296 /* bus interface */ 297 DEVMETHOD(bus_print_child, bus_generic_print_child), 298 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 299 300 /* MII interface */ 301 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 302 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 303 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 304 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 305 306 { 0, 0 } 307 }; 308 309 static driver_t dc_driver = { 310 "dc", 311 dc_methods, 312 sizeof(struct dc_softc) 313 }; 314 315 static devclass_t dc_devclass; 316 #ifdef __i386__ 317 static int dc_quick = 1; 318 SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW, &dc_quick, 0, 319 "do not mdevget in dc driver"); 320 #endif 321 322 DRIVER_MODULE(dc, cardbus, dc_driver, dc_devclass, 0, 0); 323 DRIVER_MODULE(dc, pci, dc_driver, dc_devclass, 0, 0); 324 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 325 326 #define DC_SETBIT(sc, reg, x) \ 327 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 328 329 #define DC_CLRBIT(sc, reg, x) \ 330 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 331 332 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 333 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 334 335 #define IS_MPSAFE 0 336 337 static void 338 dc_delay(struct dc_softc *sc) 339 { 340 int idx; 341 342 for (idx = (300 / 33) + 1; idx > 0; idx--) 343 CSR_READ_4(sc, DC_BUSCTL); 344 } 345 346 static void 347 dc_eeprom_width(struct dc_softc *sc) 348 { 349 int i; 350 351 /* Force EEPROM to idle state. */ 352 dc_eeprom_idle(sc); 353 354 /* Enter EEPROM access mode. */ 355 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 356 dc_delay(sc); 357 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 358 dc_delay(sc); 359 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 360 dc_delay(sc); 361 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 362 dc_delay(sc); 363 364 for (i = 3; i--;) { 365 if (6 & (1 << i)) 366 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 367 else 368 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 369 dc_delay(sc); 370 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 371 dc_delay(sc); 372 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 373 dc_delay(sc); 374 } 375 376 for (i = 1; i <= 12; i++) { 377 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 378 dc_delay(sc); 379 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { 380 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 381 dc_delay(sc); 382 break; 383 } 384 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 385 dc_delay(sc); 386 } 387 388 /* Turn off EEPROM access mode. */ 389 dc_eeprom_idle(sc); 390 391 if (i < 4 || i > 12) 392 sc->dc_romwidth = 6; 393 else 394 sc->dc_romwidth = i; 395 396 /* Enter EEPROM access mode. */ 397 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 398 dc_delay(sc); 399 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 400 dc_delay(sc); 401 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 402 dc_delay(sc); 403 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 404 dc_delay(sc); 405 406 /* Turn off EEPROM access mode. */ 407 dc_eeprom_idle(sc); 408 } 409 410 static void 411 dc_eeprom_idle(struct dc_softc *sc) 412 { 413 int i; 414 415 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 416 dc_delay(sc); 417 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 418 dc_delay(sc); 419 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 420 dc_delay(sc); 421 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 422 dc_delay(sc); 423 424 for (i = 0; i < 25; i++) { 425 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 426 dc_delay(sc); 427 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 428 dc_delay(sc); 429 } 430 431 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 432 dc_delay(sc); 433 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 434 dc_delay(sc); 435 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 436 } 437 438 /* 439 * Send a read command and address to the EEPROM, check for ACK. 440 */ 441 static void 442 dc_eeprom_putbyte(struct dc_softc *sc, int addr) 443 { 444 int d, i; 445 446 d = DC_EECMD_READ >> 6; 447 for (i = 3; i--; ) { 448 if (d & (1 << i)) 449 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 450 else 451 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 452 dc_delay(sc); 453 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 454 dc_delay(sc); 455 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 456 dc_delay(sc); 457 } 458 459 /* 460 * Feed in each bit and strobe the clock. 461 */ 462 for (i = sc->dc_romwidth; i--;) { 463 if (addr & (1 << i)) { 464 SIO_SET(DC_SIO_EE_DATAIN); 465 } else { 466 SIO_CLR(DC_SIO_EE_DATAIN); 467 } 468 dc_delay(sc); 469 SIO_SET(DC_SIO_EE_CLK); 470 dc_delay(sc); 471 SIO_CLR(DC_SIO_EE_CLK); 472 dc_delay(sc); 473 } 474 } 475 476 /* 477 * Read a word of data stored in the EEPROM at address 'addr.' 478 * The PNIC 82c168/82c169 has its own non-standard way to read 479 * the EEPROM. 480 */ 481 static void 482 dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, u_int16_t *dest) 483 { 484 int i; 485 u_int32_t r; 486 487 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr); 488 489 for (i = 0; i < DC_TIMEOUT; i++) { 490 DELAY(1); 491 r = CSR_READ_4(sc, DC_SIO); 492 if (!(r & DC_PN_SIOCTL_BUSY)) { 493 *dest = (u_int16_t)(r & 0xFFFF); 494 return; 495 } 496 } 497 } 498 499 /* 500 * Read a word of data stored in the EEPROM at address 'addr.' 501 * The Xircom X3201 has its own non-standard way to read 502 * the EEPROM, too. 503 */ 504 static void 505 dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, u_int16_t *dest) 506 { 507 508 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 509 510 addr *= 2; 511 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 512 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff; 513 addr += 1; 514 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 515 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8; 516 517 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 518 } 519 520 /* 521 * Read a word of data stored in the EEPROM at address 'addr.' 522 */ 523 static void 524 dc_eeprom_getword(struct dc_softc *sc, int addr, u_int16_t *dest) 525 { 526 int i; 527 u_int16_t word = 0; 528 529 /* Force EEPROM to idle state. */ 530 dc_eeprom_idle(sc); 531 532 /* Enter EEPROM access mode. */ 533 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 534 dc_delay(sc); 535 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 536 dc_delay(sc); 537 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 538 dc_delay(sc); 539 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 540 dc_delay(sc); 541 542 /* 543 * Send address of word we want to read. 544 */ 545 dc_eeprom_putbyte(sc, addr); 546 547 /* 548 * Start reading bits from EEPROM. 549 */ 550 for (i = 0x8000; i; i >>= 1) { 551 SIO_SET(DC_SIO_EE_CLK); 552 dc_delay(sc); 553 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 554 word |= i; 555 dc_delay(sc); 556 SIO_CLR(DC_SIO_EE_CLK); 557 dc_delay(sc); 558 } 559 560 /* Turn off EEPROM access mode. */ 561 dc_eeprom_idle(sc); 562 563 *dest = word; 564 } 565 566 /* 567 * Read a sequence of words from the EEPROM. 568 */ 569 static void 570 dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int swap) 571 { 572 int i; 573 u_int16_t word = 0, *ptr; 574 575 for (i = 0; i < cnt; i++) { 576 if (DC_IS_PNIC(sc)) 577 dc_eeprom_getword_pnic(sc, off + i, &word); 578 else if (DC_IS_XIRCOM(sc)) 579 dc_eeprom_getword_xircom(sc, off + i, &word); 580 else 581 dc_eeprom_getword(sc, off + i, &word); 582 ptr = (u_int16_t *)(dest + (i * 2)); 583 if (swap) 584 *ptr = ntohs(word); 585 else 586 *ptr = word; 587 } 588 } 589 590 /* 591 * The following two routines are taken from the Macronix 98713 592 * Application Notes pp.19-21. 593 */ 594 /* 595 * Write a bit to the MII bus. 596 */ 597 static void 598 dc_mii_writebit(struct dc_softc *sc, int bit) 599 { 600 601 if (bit) 602 CSR_WRITE_4(sc, DC_SIO, 603 DC_SIO_ROMCTL_WRITE | DC_SIO_MII_DATAOUT); 604 else 605 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 606 607 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 608 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 609 } 610 611 /* 612 * Read a bit from the MII bus. 613 */ 614 static int 615 dc_mii_readbit(struct dc_softc *sc) 616 { 617 618 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ | DC_SIO_MII_DIR); 619 CSR_READ_4(sc, DC_SIO); 620 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 621 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 622 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 623 return (1); 624 625 return (0); 626 } 627 628 /* 629 * Sync the PHYs by setting data bit and strobing the clock 32 times. 630 */ 631 static void 632 dc_mii_sync(struct dc_softc *sc) 633 { 634 int i; 635 636 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 637 638 for (i = 0; i < 32; i++) 639 dc_mii_writebit(sc, 1); 640 } 641 642 /* 643 * Clock a series of bits through the MII. 644 */ 645 static void 646 dc_mii_send(struct dc_softc *sc, u_int32_t bits, int cnt) 647 { 648 int i; 649 650 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 651 dc_mii_writebit(sc, bits & i); 652 } 653 654 /* 655 * Read an PHY register through the MII. 656 */ 657 static int 658 dc_mii_readreg(struct dc_softc *sc, struct dc_mii_frame *frame) 659 { 660 int i, ack; 661 662 DC_LOCK(sc); 663 664 /* 665 * Set up frame for RX. 666 */ 667 frame->mii_stdelim = DC_MII_STARTDELIM; 668 frame->mii_opcode = DC_MII_READOP; 669 frame->mii_turnaround = 0; 670 frame->mii_data = 0; 671 672 /* 673 * Sync the PHYs. 674 */ 675 dc_mii_sync(sc); 676 677 /* 678 * Send command/address info. 679 */ 680 dc_mii_send(sc, frame->mii_stdelim, 2); 681 dc_mii_send(sc, frame->mii_opcode, 2); 682 dc_mii_send(sc, frame->mii_phyaddr, 5); 683 dc_mii_send(sc, frame->mii_regaddr, 5); 684 685 #ifdef notdef 686 /* Idle bit */ 687 dc_mii_writebit(sc, 1); 688 dc_mii_writebit(sc, 0); 689 #endif 690 691 /* Check for ack. */ 692 ack = dc_mii_readbit(sc); 693 694 /* 695 * Now try reading data bits. If the ack failed, we still 696 * need to clock through 16 cycles to keep the PHY(s) in sync. 697 */ 698 if (ack) { 699 for (i = 0; i < 16; i++) 700 dc_mii_readbit(sc); 701 goto fail; 702 } 703 704 for (i = 0x8000; i; i >>= 1) { 705 if (!ack) { 706 if (dc_mii_readbit(sc)) 707 frame->mii_data |= i; 708 } 709 } 710 711 fail: 712 713 dc_mii_writebit(sc, 0); 714 dc_mii_writebit(sc, 0); 715 716 DC_UNLOCK(sc); 717 718 if (ack) 719 return (1); 720 return (0); 721 } 722 723 /* 724 * Write to a PHY register through the MII. 725 */ 726 static int 727 dc_mii_writereg(struct dc_softc *sc, struct dc_mii_frame *frame) 728 { 729 730 DC_LOCK(sc); 731 /* 732 * Set up frame for TX. 733 */ 734 735 frame->mii_stdelim = DC_MII_STARTDELIM; 736 frame->mii_opcode = DC_MII_WRITEOP; 737 frame->mii_turnaround = DC_MII_TURNAROUND; 738 739 /* 740 * Sync the PHYs. 741 */ 742 dc_mii_sync(sc); 743 744 dc_mii_send(sc, frame->mii_stdelim, 2); 745 dc_mii_send(sc, frame->mii_opcode, 2); 746 dc_mii_send(sc, frame->mii_phyaddr, 5); 747 dc_mii_send(sc, frame->mii_regaddr, 5); 748 dc_mii_send(sc, frame->mii_turnaround, 2); 749 dc_mii_send(sc, frame->mii_data, 16); 750 751 /* Idle bit. */ 752 dc_mii_writebit(sc, 0); 753 dc_mii_writebit(sc, 0); 754 755 DC_UNLOCK(sc); 756 757 return (0); 758 } 759 760 static int 761 dc_miibus_readreg(device_t dev, int phy, int reg) 762 { 763 struct dc_mii_frame frame; 764 struct dc_softc *sc; 765 int i, rval, phy_reg = 0; 766 767 sc = device_get_softc(dev); 768 bzero(&frame, sizeof(frame)); 769 770 /* 771 * Note: both the AL981 and AN985 have internal PHYs, 772 * however the AL981 provides direct access to the PHY 773 * registers while the AN985 uses a serial MII interface. 774 * The AN985's MII interface is also buggy in that you 775 * can read from any MII address (0 to 31), but only address 1 776 * behaves normally. To deal with both cases, we pretend 777 * that the PHY is at MII address 1. 778 */ 779 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 780 return (0); 781 782 /* 783 * Note: the ukphy probes of the RS7112 report a PHY at 784 * MII address 0 (possibly HomePNA?) and 1 (ethernet) 785 * so we only respond to correct one. 786 */ 787 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 788 return (0); 789 790 if (sc->dc_pmode != DC_PMODE_MII) { 791 if (phy == (MII_NPHY - 1)) { 792 switch (reg) { 793 case MII_BMSR: 794 /* 795 * Fake something to make the probe 796 * code think there's a PHY here. 797 */ 798 return (BMSR_MEDIAMASK); 799 break; 800 case MII_PHYIDR1: 801 if (DC_IS_PNIC(sc)) 802 return (DC_VENDORID_LO); 803 return (DC_VENDORID_DEC); 804 break; 805 case MII_PHYIDR2: 806 if (DC_IS_PNIC(sc)) 807 return (DC_DEVICEID_82C168); 808 return (DC_DEVICEID_21143); 809 break; 810 default: 811 return (0); 812 break; 813 } 814 } else 815 return (0); 816 } 817 818 if (DC_IS_PNIC(sc)) { 819 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 820 (phy << 23) | (reg << 18)); 821 for (i = 0; i < DC_TIMEOUT; i++) { 822 DELAY(1); 823 rval = CSR_READ_4(sc, DC_PN_MII); 824 if (!(rval & DC_PN_MII_BUSY)) { 825 rval &= 0xFFFF; 826 return (rval == 0xFFFF ? 0 : rval); 827 } 828 } 829 return (0); 830 } 831 832 if (DC_IS_COMET(sc)) { 833 switch (reg) { 834 case MII_BMCR: 835 phy_reg = DC_AL_BMCR; 836 break; 837 case MII_BMSR: 838 phy_reg = DC_AL_BMSR; 839 break; 840 case MII_PHYIDR1: 841 phy_reg = DC_AL_VENID; 842 break; 843 case MII_PHYIDR2: 844 phy_reg = DC_AL_DEVID; 845 break; 846 case MII_ANAR: 847 phy_reg = DC_AL_ANAR; 848 break; 849 case MII_ANLPAR: 850 phy_reg = DC_AL_LPAR; 851 break; 852 case MII_ANER: 853 phy_reg = DC_AL_ANER; 854 break; 855 default: 856 printf("dc%d: phy_read: bad phy register %x\n", 857 sc->dc_unit, reg); 858 return (0); 859 break; 860 } 861 862 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 863 864 if (rval == 0xFFFF) 865 return (0); 866 return (rval); 867 } 868 869 frame.mii_phyaddr = phy; 870 frame.mii_regaddr = reg; 871 if (sc->dc_type == DC_TYPE_98713) { 872 phy_reg = CSR_READ_4(sc, DC_NETCFG); 873 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 874 } 875 dc_mii_readreg(sc, &frame); 876 if (sc->dc_type == DC_TYPE_98713) 877 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 878 879 return (frame.mii_data); 880 } 881 882 static int 883 dc_miibus_writereg(device_t dev, int phy, int reg, int data) 884 { 885 struct dc_softc *sc; 886 struct dc_mii_frame frame; 887 int i, phy_reg = 0; 888 889 sc = device_get_softc(dev); 890 bzero(&frame, sizeof(frame)); 891 892 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 893 return (0); 894 895 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 896 return (0); 897 898 if (DC_IS_PNIC(sc)) { 899 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 900 (phy << 23) | (reg << 10) | data); 901 for (i = 0; i < DC_TIMEOUT; i++) { 902 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 903 break; 904 } 905 return (0); 906 } 907 908 if (DC_IS_COMET(sc)) { 909 switch (reg) { 910 case MII_BMCR: 911 phy_reg = DC_AL_BMCR; 912 break; 913 case MII_BMSR: 914 phy_reg = DC_AL_BMSR; 915 break; 916 case MII_PHYIDR1: 917 phy_reg = DC_AL_VENID; 918 break; 919 case MII_PHYIDR2: 920 phy_reg = DC_AL_DEVID; 921 break; 922 case MII_ANAR: 923 phy_reg = DC_AL_ANAR; 924 break; 925 case MII_ANLPAR: 926 phy_reg = DC_AL_LPAR; 927 break; 928 case MII_ANER: 929 phy_reg = DC_AL_ANER; 930 break; 931 default: 932 printf("dc%d: phy_write: bad phy register %x\n", 933 sc->dc_unit, reg); 934 return (0); 935 break; 936 } 937 938 CSR_WRITE_4(sc, phy_reg, data); 939 return (0); 940 } 941 942 frame.mii_phyaddr = phy; 943 frame.mii_regaddr = reg; 944 frame.mii_data = data; 945 946 if (sc->dc_type == DC_TYPE_98713) { 947 phy_reg = CSR_READ_4(sc, DC_NETCFG); 948 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 949 } 950 dc_mii_writereg(sc, &frame); 951 if (sc->dc_type == DC_TYPE_98713) 952 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 953 954 return (0); 955 } 956 957 static void 958 dc_miibus_statchg(device_t dev) 959 { 960 struct dc_softc *sc; 961 struct mii_data *mii; 962 struct ifmedia *ifm; 963 964 sc = device_get_softc(dev); 965 if (DC_IS_ADMTEK(sc)) 966 return; 967 968 mii = device_get_softc(sc->dc_miibus); 969 ifm = &mii->mii_media; 970 if (DC_IS_DAVICOM(sc) && 971 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 972 dc_setcfg(sc, ifm->ifm_media); 973 sc->dc_if_media = ifm->ifm_media; 974 } else { 975 dc_setcfg(sc, mii->mii_media_active); 976 sc->dc_if_media = mii->mii_media_active; 977 } 978 } 979 980 /* 981 * Special support for DM9102A cards with HomePNA PHYs. Note: 982 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 983 * to be impossible to talk to the management interface of the DM9801 984 * PHY (its MDIO pin is not connected to anything). Consequently, 985 * the driver has to just 'know' about the additional mode and deal 986 * with it itself. *sigh* 987 */ 988 static void 989 dc_miibus_mediainit(device_t dev) 990 { 991 struct dc_softc *sc; 992 struct mii_data *mii; 993 struct ifmedia *ifm; 994 int rev; 995 996 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 997 998 sc = device_get_softc(dev); 999 mii = device_get_softc(sc->dc_miibus); 1000 ifm = &mii->mii_media; 1001 1002 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 1003 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL); 1004 } 1005 1006 #define DC_POLY 0xEDB88320 1007 #define DC_BITS_512 9 1008 #define DC_BITS_128 7 1009 #define DC_BITS_64 6 1010 1011 static u_int32_t 1012 dc_crc_le(struct dc_softc *sc, caddr_t addr) 1013 { 1014 u_int32_t idx, bit, data, crc; 1015 1016 /* Compute CRC for the address value. */ 1017 crc = 0xFFFFFFFF; /* initial value */ 1018 1019 for (idx = 0; idx < 6; idx++) { 1020 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 1021 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 1022 } 1023 1024 /* 1025 * The hash table on the PNIC II and the MX98715AEC-C/D/E 1026 * chips is only 128 bits wide. 1027 */ 1028 if (sc->dc_flags & DC_128BIT_HASH) 1029 return (crc & ((1 << DC_BITS_128) - 1)); 1030 1031 /* The hash table on the MX98715BEC is only 64 bits wide. */ 1032 if (sc->dc_flags & DC_64BIT_HASH) 1033 return (crc & ((1 << DC_BITS_64) - 1)); 1034 1035 /* Xircom's hash filtering table is different (read: weird) */ 1036 /* Xircom uses the LEAST significant bits */ 1037 if (DC_IS_XIRCOM(sc)) { 1038 if ((crc & 0x180) == 0x180) 1039 return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4)); 1040 else 1041 return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 + 1042 (12 << 4)); 1043 } 1044 1045 return (crc & ((1 << DC_BITS_512) - 1)); 1046 } 1047 1048 /* 1049 * Calculate CRC of a multicast group address, return the lower 6 bits. 1050 */ 1051 static u_int32_t 1052 dc_crc_be(caddr_t addr) 1053 { 1054 u_int32_t crc, carry; 1055 int i, j; 1056 u_int8_t c; 1057 1058 /* Compute CRC for the address value. */ 1059 crc = 0xFFFFFFFF; /* initial value */ 1060 1061 for (i = 0; i < 6; i++) { 1062 c = *(addr + i); 1063 for (j = 0; j < 8; j++) { 1064 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 1065 crc <<= 1; 1066 c >>= 1; 1067 if (carry) 1068 crc = (crc ^ 0x04c11db6) | carry; 1069 } 1070 } 1071 1072 /* Return the filter bit position. */ 1073 return ((crc >> 26) & 0x0000003F); 1074 } 1075 1076 /* 1077 * 21143-style RX filter setup routine. Filter programming is done by 1078 * downloading a special setup frame into the TX engine. 21143, Macronix, 1079 * PNIC, PNIC II and Davicom chips are programmed this way. 1080 * 1081 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1082 * address (our node address) and a 512-bit hash filter for multicast 1083 * frames. We also sneak the broadcast address into the hash filter since 1084 * we need that too. 1085 */ 1086 static void 1087 dc_setfilt_21143(struct dc_softc *sc) 1088 { 1089 struct dc_desc *sframe; 1090 u_int32_t h, *sp; 1091 struct ifmultiaddr *ifma; 1092 struct ifnet *ifp; 1093 int i; 1094 1095 ifp = &sc->arpcom.ac_if; 1096 1097 i = sc->dc_cdata.dc_tx_prod; 1098 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1099 sc->dc_cdata.dc_tx_cnt++; 1100 sframe = &sc->dc_ldata->dc_tx_list[i]; 1101 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1102 bzero(sp, DC_SFRAME_LEN); 1103 1104 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1105 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1106 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1107 1108 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1109 1110 /* If we want promiscuous mode, set the allframes bit. */ 1111 if (ifp->if_flags & IFF_PROMISC) 1112 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1113 else 1114 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1115 1116 if (ifp->if_flags & IFF_ALLMULTI) 1117 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1118 else 1119 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1120 1121 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1122 if (ifma->ifma_addr->sa_family != AF_LINK) 1123 continue; 1124 h = dc_crc_le(sc, 1125 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1126 sp[h >> 4] |= 1 << (h & 0xF); 1127 } 1128 1129 if (ifp->if_flags & IFF_BROADCAST) { 1130 h = dc_crc_le(sc, (caddr_t)ifp->if_broadcastaddr); 1131 sp[h >> 4] |= 1 << (h & 0xF); 1132 } 1133 1134 /* Set our MAC address */ 1135 sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1136 sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1137 sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1138 1139 sframe->dc_status = DC_TXSTAT_OWN; 1140 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1141 1142 /* 1143 * The PNIC takes an exceedingly long time to process its 1144 * setup frame; wait 10ms after posting the setup frame 1145 * before proceeding, just so it has time to swallow its 1146 * medicine. 1147 */ 1148 DELAY(10000); 1149 1150 ifp->if_timer = 5; 1151 } 1152 1153 static void 1154 dc_setfilt_admtek(struct dc_softc *sc) 1155 { 1156 struct ifnet *ifp; 1157 struct ifmultiaddr *ifma; 1158 int h = 0; 1159 u_int32_t hashes[2] = { 0, 0 }; 1160 1161 ifp = &sc->arpcom.ac_if; 1162 1163 /* Init our MAC address. */ 1164 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1165 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1166 1167 /* If we want promiscuous mode, set the allframes bit. */ 1168 if (ifp->if_flags & IFF_PROMISC) 1169 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1170 else 1171 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1172 1173 if (ifp->if_flags & IFF_ALLMULTI) 1174 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1175 else 1176 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1177 1178 /* First, zot all the existing hash bits. */ 1179 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1180 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1181 1182 /* 1183 * If we're already in promisc or allmulti mode, we 1184 * don't have to bother programming the multicast filter. 1185 */ 1186 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1187 return; 1188 1189 /* Now program new ones. */ 1190 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1191 if (ifma->ifma_addr->sa_family != AF_LINK) 1192 continue; 1193 if (DC_IS_CENTAUR(sc)) 1194 h = dc_crc_le(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1195 else 1196 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1197 if (h < 32) 1198 hashes[0] |= (1 << h); 1199 else 1200 hashes[1] |= (1 << (h - 32)); 1201 } 1202 1203 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1204 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1205 } 1206 1207 static void 1208 dc_setfilt_asix(struct dc_softc *sc) 1209 { 1210 struct ifnet *ifp; 1211 struct ifmultiaddr *ifma; 1212 int h = 0; 1213 u_int32_t hashes[2] = { 0, 0 }; 1214 1215 ifp = &sc->arpcom.ac_if; 1216 1217 /* Init our MAC address */ 1218 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1219 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1220 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1221 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1222 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1223 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1224 1225 /* If we want promiscuous mode, set the allframes bit. */ 1226 if (ifp->if_flags & IFF_PROMISC) 1227 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1228 else 1229 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1230 1231 if (ifp->if_flags & IFF_ALLMULTI) 1232 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1233 else 1234 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1235 1236 /* 1237 * The ASIX chip has a special bit to enable reception 1238 * of broadcast frames. 1239 */ 1240 if (ifp->if_flags & IFF_BROADCAST) 1241 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1242 else 1243 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1244 1245 /* first, zot all the existing hash bits */ 1246 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1247 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1248 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1249 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1250 1251 /* 1252 * If we're already in promisc or allmulti mode, we 1253 * don't have to bother programming the multicast filter. 1254 */ 1255 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1256 return; 1257 1258 /* now program new ones */ 1259 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1260 if (ifma->ifma_addr->sa_family != AF_LINK) 1261 continue; 1262 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1263 if (h < 32) 1264 hashes[0] |= (1 << h); 1265 else 1266 hashes[1] |= (1 << (h - 32)); 1267 } 1268 1269 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1270 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1271 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1272 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1273 } 1274 1275 static void 1276 dc_setfilt_xircom(struct dc_softc *sc) 1277 { 1278 struct ifnet *ifp; 1279 struct ifmultiaddr *ifma; 1280 struct dc_desc *sframe; 1281 u_int32_t h, *sp; 1282 int i; 1283 1284 ifp = &sc->arpcom.ac_if; 1285 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1286 1287 i = sc->dc_cdata.dc_tx_prod; 1288 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1289 sc->dc_cdata.dc_tx_cnt++; 1290 sframe = &sc->dc_ldata->dc_tx_list[i]; 1291 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1292 bzero(sp, DC_SFRAME_LEN); 1293 1294 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1295 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1296 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1297 1298 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1299 1300 /* If we want promiscuous mode, set the allframes bit. */ 1301 if (ifp->if_flags & IFF_PROMISC) 1302 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1303 else 1304 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1305 1306 if (ifp->if_flags & IFF_ALLMULTI) 1307 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1308 else 1309 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1310 1311 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1312 if (ifma->ifma_addr->sa_family != AF_LINK) 1313 continue; 1314 h = dc_crc_le(sc, 1315 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1316 sp[h >> 4] |= 1 << (h & 0xF); 1317 } 1318 1319 if (ifp->if_flags & IFF_BROADCAST) { 1320 h = dc_crc_le(sc, (caddr_t)ifp->if_broadcastaddr); 1321 sp[h >> 4] |= 1 << (h & 0xF); 1322 } 1323 1324 /* Set our MAC address */ 1325 sp[0] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1326 sp[1] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1327 sp[2] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1328 1329 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1330 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1331 ifp->if_flags |= IFF_RUNNING; 1332 sframe->dc_status = DC_TXSTAT_OWN; 1333 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1334 1335 /* 1336 * Wait some time... 1337 */ 1338 DELAY(1000); 1339 1340 ifp->if_timer = 5; 1341 } 1342 1343 static void 1344 dc_setfilt(struct dc_softc *sc) 1345 { 1346 1347 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1348 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1349 dc_setfilt_21143(sc); 1350 1351 if (DC_IS_ASIX(sc)) 1352 dc_setfilt_asix(sc); 1353 1354 if (DC_IS_ADMTEK(sc)) 1355 dc_setfilt_admtek(sc); 1356 1357 if (DC_IS_XIRCOM(sc)) 1358 dc_setfilt_xircom(sc); 1359 } 1360 1361 /* 1362 * In order to fiddle with the 'full-duplex' and '100Mbps' bits in 1363 * the netconfig register, we first have to put the transmit and/or 1364 * receive logic in the idle state. 1365 */ 1366 static void 1367 dc_setcfg(struct dc_softc *sc, int media) 1368 { 1369 int i, restart = 0, watchdogreg; 1370 u_int32_t isr; 1371 1372 if (IFM_SUBTYPE(media) == IFM_NONE) 1373 return; 1374 1375 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) { 1376 restart = 1; 1377 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1378 1379 for (i = 0; i < DC_TIMEOUT; i++) { 1380 isr = CSR_READ_4(sc, DC_ISR); 1381 if (isr & DC_ISR_TX_IDLE && 1382 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1383 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT)) 1384 break; 1385 DELAY(10); 1386 } 1387 1388 if (i == DC_TIMEOUT) 1389 printf("dc%d: failed to force tx and " 1390 "rx to idle state\n", sc->dc_unit); 1391 } 1392 1393 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1394 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1395 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1396 if (sc->dc_pmode == DC_PMODE_MII) { 1397 if (DC_IS_INTEL(sc)) { 1398 /* There's a write enable bit here that reads as 1. */ 1399 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1400 watchdogreg &= ~DC_WDOG_CTLWREN; 1401 watchdogreg |= DC_WDOG_JABBERDIS; 1402 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1403 } else { 1404 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1405 } 1406 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1407 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1408 if (sc->dc_type == DC_TYPE_98713) 1409 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1410 DC_NETCFG_SCRAMBLER)); 1411 if (!DC_IS_DAVICOM(sc)) 1412 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1413 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1414 if (DC_IS_INTEL(sc)) 1415 dc_apply_fixup(sc, IFM_AUTO); 1416 } else { 1417 if (DC_IS_PNIC(sc)) { 1418 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1419 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1420 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1421 } 1422 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1423 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1424 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1425 if (DC_IS_INTEL(sc)) 1426 dc_apply_fixup(sc, 1427 (media & IFM_GMASK) == IFM_FDX ? 1428 IFM_100_TX | IFM_FDX : IFM_100_TX); 1429 } 1430 } 1431 1432 if (IFM_SUBTYPE(media) == IFM_10_T) { 1433 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1434 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1435 if (sc->dc_pmode == DC_PMODE_MII) { 1436 /* There's a write enable bit here that reads as 1. */ 1437 if (DC_IS_INTEL(sc)) { 1438 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1439 watchdogreg &= ~DC_WDOG_CTLWREN; 1440 watchdogreg |= DC_WDOG_JABBERDIS; 1441 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1442 } else { 1443 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1444 } 1445 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1446 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1447 if (sc->dc_type == DC_TYPE_98713) 1448 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1449 if (!DC_IS_DAVICOM(sc)) 1450 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1451 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1452 if (DC_IS_INTEL(sc)) 1453 dc_apply_fixup(sc, IFM_AUTO); 1454 } else { 1455 if (DC_IS_PNIC(sc)) { 1456 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1457 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1458 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1459 } 1460 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1461 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1462 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1463 if (DC_IS_INTEL(sc)) { 1464 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1465 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1466 if ((media & IFM_GMASK) == IFM_FDX) 1467 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1468 else 1469 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1470 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1471 DC_CLRBIT(sc, DC_10BTCTRL, 1472 DC_TCTL_AUTONEGENBL); 1473 dc_apply_fixup(sc, 1474 (media & IFM_GMASK) == IFM_FDX ? 1475 IFM_10_T | IFM_FDX : IFM_10_T); 1476 DELAY(20000); 1477 } 1478 } 1479 } 1480 1481 /* 1482 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1483 * PHY and we want HomePNA mode, set the portsel bit to turn 1484 * on the external MII port. 1485 */ 1486 if (DC_IS_DAVICOM(sc)) { 1487 if (IFM_SUBTYPE(media) == IFM_HPNA_1) { 1488 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1489 sc->dc_link = 1; 1490 } else { 1491 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1492 } 1493 } 1494 1495 if ((media & IFM_GMASK) == IFM_FDX) { 1496 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1497 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1498 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1499 } else { 1500 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1501 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1502 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1503 } 1504 1505 if (restart) 1506 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON | DC_NETCFG_RX_ON); 1507 } 1508 1509 static void 1510 dc_reset(struct dc_softc *sc) 1511 { 1512 int i; 1513 1514 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1515 1516 for (i = 0; i < DC_TIMEOUT; i++) { 1517 DELAY(10); 1518 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1519 break; 1520 } 1521 1522 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) || 1523 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) { 1524 DELAY(10000); 1525 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1526 i = 0; 1527 } 1528 1529 if (i == DC_TIMEOUT) 1530 printf("dc%d: reset never completed!\n", sc->dc_unit); 1531 1532 /* Wait a little while for the chip to get its brains in order. */ 1533 DELAY(1000); 1534 1535 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1536 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1537 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1538 1539 /* 1540 * Bring the SIA out of reset. In some cases, it looks 1541 * like failing to unreset the SIA soon enough gets it 1542 * into a state where it will never come out of reset 1543 * until we reset the whole chip again. 1544 */ 1545 if (DC_IS_INTEL(sc)) { 1546 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1547 CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1548 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1549 } 1550 } 1551 1552 static struct dc_type * 1553 dc_devtype(device_t dev) 1554 { 1555 struct dc_type *t; 1556 u_int32_t rev; 1557 1558 t = dc_devs; 1559 1560 while (t->dc_name != NULL) { 1561 if ((pci_get_vendor(dev) == t->dc_vid) && 1562 (pci_get_device(dev) == t->dc_did)) { 1563 /* Check the PCI revision */ 1564 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1565 if (t->dc_did == DC_DEVICEID_98713 && 1566 rev >= DC_REVISION_98713A) 1567 t++; 1568 if (t->dc_did == DC_DEVICEID_98713_CP && 1569 rev >= DC_REVISION_98713A) 1570 t++; 1571 if (t->dc_did == DC_DEVICEID_987x5 && 1572 rev >= DC_REVISION_98715AEC_C) 1573 t++; 1574 if (t->dc_did == DC_DEVICEID_987x5 && 1575 rev >= DC_REVISION_98725) 1576 t++; 1577 if (t->dc_did == DC_DEVICEID_AX88140A && 1578 rev >= DC_REVISION_88141) 1579 t++; 1580 if (t->dc_did == DC_DEVICEID_82C168 && 1581 rev >= DC_REVISION_82C169) 1582 t++; 1583 if (t->dc_did == DC_DEVICEID_DM9102 && 1584 rev >= DC_REVISION_DM9102A) 1585 t++; 1586 return (t); 1587 } 1588 t++; 1589 } 1590 1591 return (NULL); 1592 } 1593 1594 /* 1595 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1596 * IDs against our list and return a device name if we find a match. 1597 * We do a little bit of extra work to identify the exact type of 1598 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1599 * but different revision IDs. The same is true for 98715/98715A 1600 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1601 * cases, the exact chip revision affects driver behavior. 1602 */ 1603 static int 1604 dc_probe(device_t dev) 1605 { 1606 struct dc_type *t; 1607 1608 t = dc_devtype(dev); 1609 1610 if (t != NULL) { 1611 device_set_desc(dev, t->dc_name); 1612 return (0); 1613 } 1614 1615 return (ENXIO); 1616 } 1617 1618 #ifndef BURN_BRIDGES 1619 static void 1620 dc_acpi(device_t dev) 1621 { 1622 int unit; 1623 u_int32_t iobase, membase, irq; 1624 1625 unit = device_get_unit(dev); 1626 1627 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1628 /* Save important PCI config data. */ 1629 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4); 1630 membase = pci_read_config(dev, DC_PCI_CFBMA, 4); 1631 irq = pci_read_config(dev, DC_PCI_CFIT, 4); 1632 1633 /* Reset the power state. */ 1634 printf("dc%d: chip is in D%d power mode " 1635 "-- setting to D0\n", unit, 1636 pci_get_powerstate(dev)); 1637 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1638 1639 /* Restore PCI config data. */ 1640 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4); 1641 pci_write_config(dev, DC_PCI_CFBMA, membase, 4); 1642 pci_write_config(dev, DC_PCI_CFIT, irq, 4); 1643 } 1644 } 1645 #endif 1646 1647 static void 1648 dc_apply_fixup(struct dc_softc *sc, int media) 1649 { 1650 struct dc_mediainfo *m; 1651 u_int8_t *p; 1652 int i; 1653 u_int32_t reg; 1654 1655 m = sc->dc_mi; 1656 1657 while (m != NULL) { 1658 if (m->dc_media == media) 1659 break; 1660 m = m->dc_next; 1661 } 1662 1663 if (m == NULL) 1664 return; 1665 1666 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1667 reg = (p[0] | (p[1] << 8)) << 16; 1668 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1669 } 1670 1671 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1672 reg = (p[0] | (p[1] << 8)) << 16; 1673 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1674 } 1675 } 1676 1677 static void 1678 dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l) 1679 { 1680 struct dc_mediainfo *m; 1681 1682 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1683 if (l->dc_sia_code == DC_SIA_CODE_10BT) 1684 m->dc_media = IFM_10_T; 1685 1686 if (l->dc_sia_code == DC_SIA_CODE_10BT_FDX) 1687 m->dc_media = IFM_10_T | IFM_FDX; 1688 1689 if (l->dc_sia_code == DC_SIA_CODE_10B2) 1690 m->dc_media = IFM_10_2; 1691 1692 if (l->dc_sia_code == DC_SIA_CODE_10B5) 1693 m->dc_media = IFM_10_5; 1694 1695 m->dc_gp_len = 2; 1696 m->dc_gp_ptr = (u_int8_t *)&l->dc_sia_gpio_ctl; 1697 1698 m->dc_next = sc->dc_mi; 1699 sc->dc_mi = m; 1700 1701 sc->dc_pmode = DC_PMODE_SIA; 1702 } 1703 1704 static void 1705 dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l) 1706 { 1707 struct dc_mediainfo *m; 1708 1709 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1710 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1711 m->dc_media = IFM_100_TX; 1712 1713 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1714 m->dc_media = IFM_100_TX | IFM_FDX; 1715 1716 m->dc_gp_len = 2; 1717 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1718 1719 m->dc_next = sc->dc_mi; 1720 sc->dc_mi = m; 1721 1722 sc->dc_pmode = DC_PMODE_SYM; 1723 } 1724 1725 static void 1726 dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l) 1727 { 1728 struct dc_mediainfo *m; 1729 u_int8_t *p; 1730 1731 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1732 /* We abuse IFM_AUTO to represent MII. */ 1733 m->dc_media = IFM_AUTO; 1734 m->dc_gp_len = l->dc_gpr_len; 1735 1736 p = (u_int8_t *)l; 1737 p += sizeof(struct dc_eblock_mii); 1738 m->dc_gp_ptr = p; 1739 p += 2 * l->dc_gpr_len; 1740 m->dc_reset_len = *p; 1741 p++; 1742 m->dc_reset_ptr = p; 1743 1744 m->dc_next = sc->dc_mi; 1745 sc->dc_mi = m; 1746 } 1747 1748 static void 1749 dc_read_srom(struct dc_softc *sc, int bits) 1750 { 1751 int size; 1752 1753 size = 2 << bits; 1754 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT); 1755 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); 1756 } 1757 1758 static void 1759 dc_parse_21143_srom(struct dc_softc *sc) 1760 { 1761 struct dc_leaf_hdr *lhdr; 1762 struct dc_eblock_hdr *hdr; 1763 int have_mii, i, loff; 1764 char *ptr; 1765 1766 have_mii = 0; 1767 loff = sc->dc_srom[27]; 1768 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1769 1770 ptr = (char *)lhdr; 1771 ptr += sizeof(struct dc_leaf_hdr) - 1; 1772 /* 1773 * Look if we got a MII media block. 1774 */ 1775 for (i = 0; i < lhdr->dc_mcnt; i++) { 1776 hdr = (struct dc_eblock_hdr *)ptr; 1777 if (hdr->dc_type == DC_EBLOCK_MII) 1778 have_mii++; 1779 1780 ptr += (hdr->dc_len & 0x7F); 1781 ptr++; 1782 } 1783 1784 /* 1785 * Do the same thing again. Only use SIA and SYM media 1786 * blocks if no MII media block is available. 1787 */ 1788 ptr = (char *)lhdr; 1789 ptr += sizeof(struct dc_leaf_hdr) - 1; 1790 for (i = 0; i < lhdr->dc_mcnt; i++) { 1791 hdr = (struct dc_eblock_hdr *)ptr; 1792 switch (hdr->dc_type) { 1793 case DC_EBLOCK_MII: 1794 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1795 break; 1796 case DC_EBLOCK_SIA: 1797 if (! have_mii) 1798 dc_decode_leaf_sia(sc, 1799 (struct dc_eblock_sia *)hdr); 1800 break; 1801 case DC_EBLOCK_SYM: 1802 if (! have_mii) 1803 dc_decode_leaf_sym(sc, 1804 (struct dc_eblock_sym *)hdr); 1805 break; 1806 default: 1807 /* Don't care. Yet. */ 1808 break; 1809 } 1810 ptr += (hdr->dc_len & 0x7F); 1811 ptr++; 1812 } 1813 } 1814 1815 /* 1816 * Attach the interface. Allocate softc structures, do ifmedia 1817 * setup and ethernet/BPF attach. 1818 */ 1819 static int 1820 dc_attach(device_t dev) 1821 { 1822 int tmp = 0; 1823 u_char eaddr[ETHER_ADDR_LEN]; 1824 u_int32_t command; 1825 struct dc_softc *sc; 1826 struct ifnet *ifp; 1827 u_int32_t revision; 1828 int unit, error = 0, rid, mac_offset; 1829 u_int8_t *mac; 1830 1831 sc = device_get_softc(dev); 1832 unit = device_get_unit(dev); 1833 1834 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1835 MTX_DEF | MTX_RECURSE); 1836 #ifndef BURN_BRIDGES 1837 /* 1838 * Handle power management nonsense. 1839 */ 1840 dc_acpi(dev); 1841 #endif 1842 /* 1843 * Map control/status registers. 1844 */ 1845 pci_enable_busmaster(dev); 1846 1847 rid = DC_RID; 1848 sc->dc_res = bus_alloc_resource(dev, DC_RES, &rid, 1849 0, ~0, 1, RF_ACTIVE); 1850 1851 if (sc->dc_res == NULL) { 1852 printf("dc%d: couldn't map ports/memory\n", unit); 1853 error = ENXIO; 1854 goto fail; 1855 } 1856 1857 sc->dc_btag = rman_get_bustag(sc->dc_res); 1858 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1859 1860 /* Allocate interrupt. */ 1861 rid = 0; 1862 sc->dc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1863 RF_SHAREABLE | RF_ACTIVE); 1864 1865 if (sc->dc_irq == NULL) { 1866 printf("dc%d: couldn't map interrupt\n", unit); 1867 error = ENXIO; 1868 goto fail; 1869 } 1870 1871 /* Need this info to decide on a chip type. */ 1872 sc->dc_info = dc_devtype(dev); 1873 revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF; 1874 1875 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */ 1876 if (sc->dc_info->dc_did != DC_DEVICEID_82C168 && 1877 sc->dc_info->dc_did != DC_DEVICEID_X3201) 1878 dc_eeprom_width(sc); 1879 1880 switch (sc->dc_info->dc_did) { 1881 case DC_DEVICEID_21143: 1882 sc->dc_type = DC_TYPE_21143; 1883 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1884 sc->dc_flags |= DC_REDUCED_MII_POLL; 1885 /* Save EEPROM contents so we can parse them later. */ 1886 dc_read_srom(sc, sc->dc_romwidth); 1887 break; 1888 case DC_DEVICEID_DM9009: 1889 case DC_DEVICEID_DM9100: 1890 case DC_DEVICEID_DM9102: 1891 sc->dc_type = DC_TYPE_DM9102; 1892 sc->dc_flags |= DC_TX_COALESCE | DC_TX_INTR_ALWAYS; 1893 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_TX_STORENFWD; 1894 sc->dc_pmode = DC_PMODE_MII; 1895 /* Increase the latency timer value. */ 1896 command = pci_read_config(dev, DC_PCI_CFLT, 4); 1897 command &= 0xFFFF00FF; 1898 command |= 0x00008000; 1899 pci_write_config(dev, DC_PCI_CFLT, command, 4); 1900 break; 1901 case DC_DEVICEID_AL981: 1902 sc->dc_type = DC_TYPE_AL981; 1903 sc->dc_flags |= DC_TX_USE_TX_INTR; 1904 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1905 sc->dc_pmode = DC_PMODE_MII; 1906 dc_read_srom(sc, sc->dc_romwidth); 1907 break; 1908 case DC_DEVICEID_AN985: 1909 case DC_DEVICEID_ADM9511: 1910 case DC_DEVICEID_ADM9513: 1911 case DC_DEVICEID_FE2500: 1912 case DC_DEVICEID_EN2242: 1913 case DC_DEVICEID_HAWKING_PN672TX: 1914 case DC_DEVICEID_3CSOHOB: 1915 sc->dc_type = DC_TYPE_AN985; 1916 sc->dc_flags |= DC_64BIT_HASH; 1917 sc->dc_flags |= DC_TX_USE_TX_INTR; 1918 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1919 sc->dc_pmode = DC_PMODE_MII; 1920 dc_read_srom(sc, sc->dc_romwidth); 1921 break; 1922 case DC_DEVICEID_98713: 1923 case DC_DEVICEID_98713_CP: 1924 if (revision < DC_REVISION_98713A) { 1925 sc->dc_type = DC_TYPE_98713; 1926 } 1927 if (revision >= DC_REVISION_98713A) { 1928 sc->dc_type = DC_TYPE_98713A; 1929 sc->dc_flags |= DC_21143_NWAY; 1930 } 1931 sc->dc_flags |= DC_REDUCED_MII_POLL; 1932 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1933 break; 1934 case DC_DEVICEID_987x5: 1935 case DC_DEVICEID_EN1217: 1936 /* 1937 * Macronix MX98715AEC-C/D/E parts have only a 1938 * 128-bit hash table. We need to deal with these 1939 * in the same manner as the PNIC II so that we 1940 * get the right number of bits out of the 1941 * CRC routine. 1942 */ 1943 if (revision >= DC_REVISION_98715AEC_C && 1944 revision < DC_REVISION_98725) 1945 sc->dc_flags |= DC_128BIT_HASH; 1946 sc->dc_type = DC_TYPE_987x5; 1947 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1948 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1949 break; 1950 case DC_DEVICEID_98727: 1951 sc->dc_type = DC_TYPE_987x5; 1952 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1953 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1954 break; 1955 case DC_DEVICEID_82C115: 1956 sc->dc_type = DC_TYPE_PNICII; 1957 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR | DC_128BIT_HASH; 1958 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1959 break; 1960 case DC_DEVICEID_82C168: 1961 sc->dc_type = DC_TYPE_PNIC; 1962 sc->dc_flags |= DC_TX_STORENFWD | DC_TX_INTR_ALWAYS; 1963 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 1964 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 1965 if (revision < DC_REVISION_82C169) 1966 sc->dc_pmode = DC_PMODE_SYM; 1967 break; 1968 case DC_DEVICEID_AX88140A: 1969 sc->dc_type = DC_TYPE_ASIX; 1970 sc->dc_flags |= DC_TX_USE_TX_INTR | DC_TX_INTR_FIRSTFRAG; 1971 sc->dc_flags |= DC_REDUCED_MII_POLL; 1972 sc->dc_pmode = DC_PMODE_MII; 1973 break; 1974 case DC_DEVICEID_X3201: 1975 sc->dc_type = DC_TYPE_XIRCOM; 1976 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 1977 DC_TX_ALIGN; 1978 /* 1979 * We don't actually need to coalesce, but we're doing 1980 * it to obtain a double word aligned buffer. 1981 * The DC_TX_COALESCE flag is required. 1982 */ 1983 sc->dc_pmode = DC_PMODE_MII; 1984 break; 1985 case DC_DEVICEID_RS7112: 1986 sc->dc_type = DC_TYPE_CONEXANT; 1987 sc->dc_flags |= DC_TX_INTR_ALWAYS; 1988 sc->dc_flags |= DC_REDUCED_MII_POLL; 1989 sc->dc_pmode = DC_PMODE_MII; 1990 dc_read_srom(sc, sc->dc_romwidth); 1991 break; 1992 default: 1993 printf("dc%d: unknown device: %x\n", sc->dc_unit, 1994 sc->dc_info->dc_did); 1995 break; 1996 } 1997 1998 /* Save the cache line size. */ 1999 if (DC_IS_DAVICOM(sc)) 2000 sc->dc_cachesize = 0; 2001 else 2002 sc->dc_cachesize = pci_read_config(dev, 2003 DC_PCI_CFLT, 4) & 0xFF; 2004 2005 /* Reset the adapter. */ 2006 dc_reset(sc); 2007 2008 /* Take 21143 out of snooze mode */ 2009 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 2010 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2011 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 2012 pci_write_config(dev, DC_PCI_CFDD, command, 4); 2013 } 2014 2015 /* 2016 * Try to learn something about the supported media. 2017 * We know that ASIX and ADMtek and Davicom devices 2018 * will *always* be using MII media, so that's a no-brainer. 2019 * The tricky ones are the Macronix/PNIC II and the 2020 * Intel 21143. 2021 */ 2022 if (DC_IS_INTEL(sc)) 2023 dc_parse_21143_srom(sc); 2024 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2025 if (sc->dc_type == DC_TYPE_98713) 2026 sc->dc_pmode = DC_PMODE_MII; 2027 else 2028 sc->dc_pmode = DC_PMODE_SYM; 2029 } else if (!sc->dc_pmode) 2030 sc->dc_pmode = DC_PMODE_MII; 2031 2032 /* 2033 * Get station address from the EEPROM. 2034 */ 2035 switch(sc->dc_type) { 2036 case DC_TYPE_98713: 2037 case DC_TYPE_98713A: 2038 case DC_TYPE_987x5: 2039 case DC_TYPE_PNICII: 2040 dc_read_eeprom(sc, (caddr_t)&mac_offset, 2041 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2042 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2043 break; 2044 case DC_TYPE_PNIC: 2045 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2046 break; 2047 case DC_TYPE_DM9102: 2048 case DC_TYPE_21143: 2049 case DC_TYPE_ASIX: 2050 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2051 break; 2052 case DC_TYPE_AL981: 2053 case DC_TYPE_AN985: 2054 bcopy(sc->dc_srom + DC_AL_EE_NODEADDR, &eaddr, 2055 ETHER_ADDR_LEN); 2056 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_AL_EE_NODEADDR, 3, 0); 2057 break; 2058 case DC_TYPE_CONEXANT: 2059 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 2060 ETHER_ADDR_LEN); 2061 break; 2062 case DC_TYPE_XIRCOM: 2063 /* The MAC comes from the CIS. */ 2064 mac = pci_get_ether(dev); 2065 if (!mac) { 2066 device_printf(dev, "No station address in CIS!\n"); 2067 error = ENXIO; 2068 goto fail; 2069 } 2070 bcopy(mac, eaddr, ETHER_ADDR_LEN); 2071 break; 2072 default: 2073 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2074 break; 2075 } 2076 2077 /* 2078 * A 21143 or clone chip was detected. Inform the world. 2079 */ 2080 printf("dc%d: Ethernet address: %6D\n", unit, eaddr, ":"); 2081 2082 sc->dc_unit = unit; 2083 bcopy(eaddr, &sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 2084 2085 sc->dc_ldata = contigmalloc(sizeof(struct dc_list_data), M_DEVBUF, 2086 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 2087 2088 if (sc->dc_ldata == NULL) { 2089 printf("dc%d: no memory for list buffers!\n", unit); 2090 error = ENXIO; 2091 goto fail; 2092 } 2093 2094 bzero(sc->dc_ldata, sizeof(struct dc_list_data)); 2095 2096 ifp = &sc->arpcom.ac_if; 2097 ifp->if_softc = sc; 2098 ifp->if_unit = unit; 2099 ifp->if_name = "dc"; 2100 /* XXX: bleah, MTU gets overwritten in ether_ifattach() */ 2101 ifp->if_mtu = ETHERMTU; 2102 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2103 ifp->if_ioctl = dc_ioctl; 2104 ifp->if_start = dc_start; 2105 ifp->if_watchdog = dc_watchdog; 2106 ifp->if_init = dc_init; 2107 ifp->if_baudrate = 10000000; 2108 ifp->if_snd.ifq_maxlen = DC_TX_LIST_CNT - 1; 2109 2110 /* 2111 * Do MII setup. If this is a 21143, check for a PHY on the 2112 * MII bus after applying any necessary fixups to twiddle the 2113 * GPIO bits. If we don't end up finding a PHY, restore the 2114 * old selection (SIA only or SIA/SYM) and attach the dcphy 2115 * driver instead. 2116 */ 2117 if (DC_IS_INTEL(sc)) { 2118 dc_apply_fixup(sc, IFM_AUTO); 2119 tmp = sc->dc_pmode; 2120 sc->dc_pmode = DC_PMODE_MII; 2121 } 2122 2123 error = mii_phy_probe(dev, &sc->dc_miibus, 2124 dc_ifmedia_upd, dc_ifmedia_sts); 2125 2126 if (error && DC_IS_INTEL(sc)) { 2127 sc->dc_pmode = tmp; 2128 if (sc->dc_pmode != DC_PMODE_SIA) 2129 sc->dc_pmode = DC_PMODE_SYM; 2130 sc->dc_flags |= DC_21143_NWAY; 2131 mii_phy_probe(dev, &sc->dc_miibus, 2132 dc_ifmedia_upd, dc_ifmedia_sts); 2133 /* 2134 * For non-MII cards, we need to have the 21143 2135 * drive the LEDs. Except there are some systems 2136 * like the NEC VersaPro NoteBook PC which have no 2137 * LEDs, and twiddling these bits has adverse effects 2138 * on them. (I.e. you suddenly can't get a link.) 2139 */ 2140 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033) 2141 sc->dc_flags |= DC_TULIP_LEDS; 2142 error = 0; 2143 } 2144 2145 if (error) { 2146 printf("dc%d: MII without any PHY!\n", sc->dc_unit); 2147 goto fail; 2148 } 2149 2150 if (DC_IS_XIRCOM(sc)) { 2151 /* 2152 * setup General Purpose Port mode and data so the tulip 2153 * can talk to the MII. 2154 */ 2155 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2156 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2157 DELAY(10); 2158 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2159 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2160 DELAY(10); 2161 } 2162 2163 if (DC_IS_ADMTEK(sc)) { 2164 /* 2165 * Set automatic TX underrun recovery for the ADMtek chips 2166 */ 2167 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); 2168 } 2169 2170 /* 2171 * Tell the upper layer(s) we support long frames. 2172 */ 2173 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2174 ifp->if_capabilities |= IFCAP_VLAN_MTU; 2175 2176 callout_init(&sc->dc_stat_ch, IS_MPSAFE); 2177 2178 #ifdef SRM_MEDIA 2179 sc->dc_srm_media = 0; 2180 2181 /* Remember the SRM console media setting */ 2182 if (DC_IS_INTEL(sc)) { 2183 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2184 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 2185 switch ((command >> 8) & 0xff) { 2186 case 3: 2187 sc->dc_srm_media = IFM_10_T; 2188 break; 2189 case 4: 2190 sc->dc_srm_media = IFM_10_T | IFM_FDX; 2191 break; 2192 case 5: 2193 sc->dc_srm_media = IFM_100_TX; 2194 break; 2195 case 6: 2196 sc->dc_srm_media = IFM_100_TX | IFM_FDX; 2197 break; 2198 } 2199 if (sc->dc_srm_media) 2200 sc->dc_srm_media |= IFM_ACTIVE | IFM_ETHER; 2201 } 2202 #endif 2203 2204 /* 2205 * Call MI attach routine. 2206 */ 2207 ether_ifattach(ifp, eaddr); 2208 2209 /* Hook interrupt last to avoid having to lock softc */ 2210 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | 2211 (IS_MPSAFE ? INTR_MPSAFE : 0), 2212 dc_intr, sc, &sc->dc_intrhand); 2213 2214 if (error) { 2215 printf("dc%d: couldn't set up irq\n", unit); 2216 ether_ifdetach(ifp); 2217 goto fail; 2218 } 2219 2220 fail: 2221 if (error) 2222 dc_detach(dev); 2223 return (error); 2224 } 2225 2226 /* 2227 * Shutdown hardware and free up resources. This can be called any 2228 * time after the mutex has been initialized. It is called in both 2229 * the error case in attach and the normal detach case so it needs 2230 * to be careful about only freeing resources that have actually been 2231 * allocated. 2232 */ 2233 static int 2234 dc_detach(device_t dev) 2235 { 2236 struct dc_softc *sc; 2237 struct ifnet *ifp; 2238 struct dc_mediainfo *m; 2239 2240 sc = device_get_softc(dev); 2241 KASSERT(mtx_initialized(&sc->dc_mtx), ("dc mutex not initialized")); 2242 DC_LOCK(sc); 2243 2244 ifp = &sc->arpcom.ac_if; 2245 2246 /* These should only be active if attach succeeded */ 2247 if (device_is_attached(dev)) { 2248 dc_stop(sc); 2249 ether_ifdetach(ifp); 2250 } 2251 if (sc->dc_miibus) 2252 device_delete_child(dev, sc->dc_miibus); 2253 bus_generic_detach(dev); 2254 2255 if (sc->dc_intrhand) 2256 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2257 if (sc->dc_irq) 2258 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2259 if (sc->dc_res) 2260 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2261 2262 if (sc->dc_ldata) 2263 contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF); 2264 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2265 2266 while (sc->dc_mi != NULL) { 2267 m = sc->dc_mi->dc_next; 2268 free(sc->dc_mi, M_DEVBUF); 2269 sc->dc_mi = m; 2270 } 2271 free(sc->dc_srom, M_DEVBUF); 2272 2273 DC_UNLOCK(sc); 2274 mtx_destroy(&sc->dc_mtx); 2275 2276 return (0); 2277 } 2278 2279 /* 2280 * Initialize the transmit descriptors. 2281 */ 2282 static int 2283 dc_list_tx_init(struct dc_softc *sc) 2284 { 2285 struct dc_chain_data *cd; 2286 struct dc_list_data *ld; 2287 int i, nexti; 2288 2289 cd = &sc->dc_cdata; 2290 ld = sc->dc_ldata; 2291 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2292 if (i == DC_TX_LIST_CNT - 1) 2293 nexti = 0; 2294 else 2295 nexti = i + 1; 2296 ld->dc_tx_list[i].dc_next = vtophys(&ld->dc_tx_list[nexti]); 2297 cd->dc_tx_chain[i] = NULL; 2298 ld->dc_tx_list[i].dc_data = 0; 2299 ld->dc_tx_list[i].dc_ctl = 0; 2300 } 2301 2302 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2303 2304 return (0); 2305 } 2306 2307 2308 /* 2309 * Initialize the RX descriptors and allocate mbufs for them. Note that 2310 * we arrange the descriptors in a closed ring, so that the last descriptor 2311 * points back to the first. 2312 */ 2313 static int 2314 dc_list_rx_init(struct dc_softc *sc) 2315 { 2316 struct dc_chain_data *cd; 2317 struct dc_list_data *ld; 2318 int i, nexti; 2319 2320 cd = &sc->dc_cdata; 2321 ld = sc->dc_ldata; 2322 2323 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2324 if (dc_newbuf(sc, i, NULL) == ENOBUFS) 2325 return (ENOBUFS); 2326 if (i == DC_RX_LIST_CNT - 1) 2327 nexti = 0; 2328 else 2329 nexti = i + 1; 2330 ld->dc_rx_list[i].dc_next = vtophys(&ld->dc_rx_list[nexti]); 2331 } 2332 2333 cd->dc_rx_prod = 0; 2334 2335 return (0); 2336 } 2337 2338 /* 2339 * Initialize an RX descriptor and attach an MBUF cluster. 2340 */ 2341 static int 2342 dc_newbuf(struct dc_softc *sc, int i, struct mbuf *m) 2343 { 2344 struct mbuf *m_new = NULL; 2345 struct dc_desc *c; 2346 2347 c = &sc->dc_ldata->dc_rx_list[i]; 2348 2349 if (m == NULL) { 2350 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 2351 if (m_new == NULL) 2352 return (ENOBUFS); 2353 2354 MCLGET(m_new, M_DONTWAIT); 2355 if (!(m_new->m_flags & M_EXT)) { 2356 m_freem(m_new); 2357 return (ENOBUFS); 2358 } 2359 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2360 } else { 2361 m_new = m; 2362 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2363 m_new->m_data = m_new->m_ext.ext_buf; 2364 } 2365 2366 m_adj(m_new, sizeof(u_int64_t)); 2367 2368 /* 2369 * If this is a PNIC chip, zero the buffer. This is part 2370 * of the workaround for the receive bug in the 82c168 and 2371 * 82c169 chips. 2372 */ 2373 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2374 bzero(mtod(m_new, char *), m_new->m_len); 2375 2376 sc->dc_cdata.dc_rx_chain[i] = m_new; 2377 c->dc_data = vtophys(mtod(m_new, caddr_t)); 2378 c->dc_ctl = DC_RXCTL_RLINK | DC_RXLEN; 2379 c->dc_status = DC_RXSTAT_OWN; 2380 2381 return (0); 2382 } 2383 2384 /* 2385 * Grrrrr. 2386 * The PNIC chip has a terrible bug in it that manifests itself during 2387 * periods of heavy activity. The exact mode of failure if difficult to 2388 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2389 * will happen on slow machines. The bug is that sometimes instead of 2390 * uploading one complete frame during reception, it uploads what looks 2391 * like the entire contents of its FIFO memory. The frame we want is at 2392 * the end of the whole mess, but we never know exactly how much data has 2393 * been uploaded, so salvaging the frame is hard. 2394 * 2395 * There is only one way to do it reliably, and it's disgusting. 2396 * Here's what we know: 2397 * 2398 * - We know there will always be somewhere between one and three extra 2399 * descriptors uploaded. 2400 * 2401 * - We know the desired received frame will always be at the end of the 2402 * total data upload. 2403 * 2404 * - We know the size of the desired received frame because it will be 2405 * provided in the length field of the status word in the last descriptor. 2406 * 2407 * Here's what we do: 2408 * 2409 * - When we allocate buffers for the receive ring, we bzero() them. 2410 * This means that we know that the buffer contents should be all 2411 * zeros, except for data uploaded by the chip. 2412 * 2413 * - We also force the PNIC chip to upload frames that include the 2414 * ethernet CRC at the end. 2415 * 2416 * - We gather all of the bogus frame data into a single buffer. 2417 * 2418 * - We then position a pointer at the end of this buffer and scan 2419 * backwards until we encounter the first non-zero byte of data. 2420 * This is the end of the received frame. We know we will encounter 2421 * some data at the end of the frame because the CRC will always be 2422 * there, so even if the sender transmits a packet of all zeros, 2423 * we won't be fooled. 2424 * 2425 * - We know the size of the actual received frame, so we subtract 2426 * that value from the current pointer location. This brings us 2427 * to the start of the actual received packet. 2428 * 2429 * - We copy this into an mbuf and pass it on, along with the actual 2430 * frame length. 2431 * 2432 * The performance hit is tremendous, but it beats dropping frames all 2433 * the time. 2434 */ 2435 2436 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG | DC_RXSTAT_LASTFRAG) 2437 static void 2438 dc_pnic_rx_bug_war(struct dc_softc *sc, int idx) 2439 { 2440 struct dc_desc *cur_rx; 2441 struct dc_desc *c = NULL; 2442 struct mbuf *m = NULL; 2443 unsigned char *ptr; 2444 int i, total_len; 2445 u_int32_t rxstat = 0; 2446 2447 i = sc->dc_pnic_rx_bug_save; 2448 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2449 ptr = sc->dc_pnic_rx_buf; 2450 bzero(ptr, DC_RXLEN * 5); 2451 2452 /* Copy all the bytes from the bogus buffers. */ 2453 while (1) { 2454 c = &sc->dc_ldata->dc_rx_list[i]; 2455 rxstat = c->dc_status; 2456 m = sc->dc_cdata.dc_rx_chain[i]; 2457 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2458 ptr += DC_RXLEN; 2459 /* If this is the last buffer, break out. */ 2460 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2461 break; 2462 dc_newbuf(sc, i, m); 2463 DC_INC(i, DC_RX_LIST_CNT); 2464 } 2465 2466 /* Find the length of the actual receive frame. */ 2467 total_len = DC_RXBYTES(rxstat); 2468 2469 /* Scan backwards until we hit a non-zero byte. */ 2470 while (*ptr == 0x00) 2471 ptr--; 2472 2473 /* Round off. */ 2474 if ((uintptr_t)(ptr) & 0x3) 2475 ptr -= 1; 2476 2477 /* Now find the start of the frame. */ 2478 ptr -= total_len; 2479 if (ptr < sc->dc_pnic_rx_buf) 2480 ptr = sc->dc_pnic_rx_buf; 2481 2482 /* 2483 * Now copy the salvaged frame to the last mbuf and fake up 2484 * the status word to make it look like a successful 2485 * frame reception. 2486 */ 2487 dc_newbuf(sc, i, m); 2488 bcopy(ptr, mtod(m, char *), total_len); 2489 cur_rx->dc_status = rxstat | DC_RXSTAT_FIRSTFRAG; 2490 } 2491 2492 /* 2493 * This routine searches the RX ring for dirty descriptors in the 2494 * event that the rxeof routine falls out of sync with the chip's 2495 * current descriptor pointer. This may happen sometimes as a result 2496 * of a "no RX buffer available" condition that happens when the chip 2497 * consumes all of the RX buffers before the driver has a chance to 2498 * process the RX ring. This routine may need to be called more than 2499 * once to bring the driver back in sync with the chip, however we 2500 * should still be getting RX DONE interrupts to drive the search 2501 * for new packets in the RX ring, so we should catch up eventually. 2502 */ 2503 static int 2504 dc_rx_resync(struct dc_softc *sc) 2505 { 2506 struct dc_desc *cur_rx; 2507 int i, pos; 2508 2509 pos = sc->dc_cdata.dc_rx_prod; 2510 2511 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2512 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2513 if (!(cur_rx->dc_status & DC_RXSTAT_OWN)) 2514 break; 2515 DC_INC(pos, DC_RX_LIST_CNT); 2516 } 2517 2518 /* If the ring really is empty, then just return. */ 2519 if (i == DC_RX_LIST_CNT) 2520 return (0); 2521 2522 /* We've fallen behing the chip: catch it. */ 2523 sc->dc_cdata.dc_rx_prod = pos; 2524 2525 return (EAGAIN); 2526 } 2527 2528 /* 2529 * A frame has been uploaded: pass the resulting mbuf chain up to 2530 * the higher level protocols. 2531 */ 2532 static void 2533 dc_rxeof(struct dc_softc *sc) 2534 { 2535 struct mbuf *m; 2536 struct ifnet *ifp; 2537 struct dc_desc *cur_rx; 2538 int i, total_len = 0; 2539 u_int32_t rxstat; 2540 2541 ifp = &sc->arpcom.ac_if; 2542 i = sc->dc_cdata.dc_rx_prod; 2543 2544 while (!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) { 2545 #ifdef DEVICE_POLLING 2546 if (ifp->if_flags & IFF_POLLING) { 2547 if (sc->rxcycles <= 0) 2548 break; 2549 sc->rxcycles--; 2550 } 2551 #endif 2552 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2553 rxstat = cur_rx->dc_status; 2554 m = sc->dc_cdata.dc_rx_chain[i]; 2555 total_len = DC_RXBYTES(rxstat); 2556 2557 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2558 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2559 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2560 sc->dc_pnic_rx_bug_save = i; 2561 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2562 DC_INC(i, DC_RX_LIST_CNT); 2563 continue; 2564 } 2565 dc_pnic_rx_bug_war(sc, i); 2566 rxstat = cur_rx->dc_status; 2567 total_len = DC_RXBYTES(rxstat); 2568 } 2569 } 2570 2571 sc->dc_cdata.dc_rx_chain[i] = NULL; 2572 2573 /* 2574 * If an error occurs, update stats, clear the 2575 * status word and leave the mbuf cluster in place: 2576 * it should simply get re-used next time this descriptor 2577 * comes up in the ring. However, don't report long 2578 * frames as errors since they could be vlans. 2579 */ 2580 if ((rxstat & DC_RXSTAT_RXERR)) { 2581 if (!(rxstat & DC_RXSTAT_GIANT) || 2582 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2583 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2584 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2585 ifp->if_ierrors++; 2586 if (rxstat & DC_RXSTAT_COLLSEEN) 2587 ifp->if_collisions++; 2588 dc_newbuf(sc, i, m); 2589 if (rxstat & DC_RXSTAT_CRCERR) { 2590 DC_INC(i, DC_RX_LIST_CNT); 2591 continue; 2592 } else { 2593 dc_init(sc); 2594 return; 2595 } 2596 } 2597 } 2598 2599 /* No errors; receive the packet. */ 2600 total_len -= ETHER_CRC_LEN; 2601 #ifdef __i386__ 2602 /* 2603 * On the x86 we do not have alignment problems, so try to 2604 * allocate a new buffer for the receive ring, and pass up 2605 * the one where the packet is already, saving the expensive 2606 * copy done in m_devget(). 2607 * If we are on an architecture with alignment problems, or 2608 * if the allocation fails, then use m_devget and leave the 2609 * existing buffer in the receive ring. 2610 */ 2611 if (dc_quick && dc_newbuf(sc, i, NULL) == 0) { 2612 m->m_pkthdr.rcvif = ifp; 2613 m->m_pkthdr.len = m->m_len = total_len; 2614 DC_INC(i, DC_RX_LIST_CNT); 2615 } else 2616 #endif 2617 { 2618 struct mbuf *m0; 2619 2620 m0 = m_devget(mtod(m, char *), total_len, 2621 ETHER_ALIGN, ifp, NULL); 2622 dc_newbuf(sc, i, m); 2623 DC_INC(i, DC_RX_LIST_CNT); 2624 if (m0 == NULL) { 2625 ifp->if_ierrors++; 2626 continue; 2627 } 2628 m = m0; 2629 } 2630 2631 ifp->if_ipackets++; 2632 (*ifp->if_input)(ifp, m); 2633 } 2634 2635 sc->dc_cdata.dc_rx_prod = i; 2636 } 2637 2638 /* 2639 * A frame was downloaded to the chip. It's safe for us to clean up 2640 * the list buffers. 2641 */ 2642 2643 static void 2644 dc_txeof(struct dc_softc *sc) 2645 { 2646 struct dc_desc *cur_tx = NULL; 2647 struct ifnet *ifp; 2648 int idx; 2649 u_int32_t txstat; 2650 2651 ifp = &sc->arpcom.ac_if; 2652 2653 /* 2654 * Go through our tx list and free mbufs for those 2655 * frames that have been transmitted. 2656 */ 2657 idx = sc->dc_cdata.dc_tx_cons; 2658 while (idx != sc->dc_cdata.dc_tx_prod) { 2659 2660 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2661 txstat = cur_tx->dc_status; 2662 2663 if (txstat & DC_TXSTAT_OWN) 2664 break; 2665 2666 if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) || 2667 cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2668 if (cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2669 /* 2670 * Yes, the PNIC is so brain damaged 2671 * that it will sometimes generate a TX 2672 * underrun error while DMAing the RX 2673 * filter setup frame. If we detect this, 2674 * we have to send the setup frame again, 2675 * or else the filter won't be programmed 2676 * correctly. 2677 */ 2678 if (DC_IS_PNIC(sc)) { 2679 if (txstat & DC_TXSTAT_ERRSUM) 2680 dc_setfilt(sc); 2681 } 2682 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2683 } 2684 sc->dc_cdata.dc_tx_cnt--; 2685 DC_INC(idx, DC_TX_LIST_CNT); 2686 continue; 2687 } 2688 2689 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) { 2690 /* 2691 * XXX: Why does my Xircom taunt me so? 2692 * For some reason it likes setting the CARRLOST flag 2693 * even when the carrier is there. wtf?!? 2694 * Who knows, but Conexant chips have the 2695 * same problem. Maybe they took lessons 2696 * from Xircom. 2697 */ 2698 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2699 sc->dc_pmode == DC_PMODE_MII && 2700 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 2701 DC_TXSTAT_NOCARRIER))) 2702 txstat &= ~DC_TXSTAT_ERRSUM; 2703 } else { 2704 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2705 sc->dc_pmode == DC_PMODE_MII && 2706 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 2707 DC_TXSTAT_NOCARRIER | DC_TXSTAT_CARRLOST))) 2708 txstat &= ~DC_TXSTAT_ERRSUM; 2709 } 2710 2711 if (txstat & DC_TXSTAT_ERRSUM) { 2712 ifp->if_oerrors++; 2713 if (txstat & DC_TXSTAT_EXCESSCOLL) 2714 ifp->if_collisions++; 2715 if (txstat & DC_TXSTAT_LATECOLL) 2716 ifp->if_collisions++; 2717 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2718 dc_init(sc); 2719 return; 2720 } 2721 } 2722 2723 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2724 2725 ifp->if_opackets++; 2726 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2727 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2728 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2729 } 2730 2731 sc->dc_cdata.dc_tx_cnt--; 2732 DC_INC(idx, DC_TX_LIST_CNT); 2733 } 2734 2735 if (idx != sc->dc_cdata.dc_tx_cons) { 2736 /* Some buffers have been freed. */ 2737 sc->dc_cdata.dc_tx_cons = idx; 2738 ifp->if_flags &= ~IFF_OACTIVE; 2739 } 2740 ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5; 2741 } 2742 2743 static void 2744 dc_tick(void *xsc) 2745 { 2746 struct dc_softc *sc; 2747 struct mii_data *mii; 2748 struct ifnet *ifp; 2749 u_int32_t r; 2750 2751 sc = xsc; 2752 DC_LOCK(sc); 2753 ifp = &sc->arpcom.ac_if; 2754 mii = device_get_softc(sc->dc_miibus); 2755 2756 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2757 if (sc->dc_flags & DC_21143_NWAY) { 2758 r = CSR_READ_4(sc, DC_10BTSTAT); 2759 if (IFM_SUBTYPE(mii->mii_media_active) == 2760 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2761 sc->dc_link = 0; 2762 mii_mediachg(mii); 2763 } 2764 if (IFM_SUBTYPE(mii->mii_media_active) == 2765 IFM_10_T && (r & DC_TSTAT_LS10)) { 2766 sc->dc_link = 0; 2767 mii_mediachg(mii); 2768 } 2769 if (sc->dc_link == 0) 2770 mii_tick(mii); 2771 } else { 2772 r = CSR_READ_4(sc, DC_ISR); 2773 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2774 sc->dc_cdata.dc_tx_cnt == 0) { 2775 mii_tick(mii); 2776 if (!(mii->mii_media_status & IFM_ACTIVE)) 2777 sc->dc_link = 0; 2778 } 2779 } 2780 } else 2781 mii_tick(mii); 2782 2783 /* 2784 * When the init routine completes, we expect to be able to send 2785 * packets right away, and in fact the network code will send a 2786 * gratuitous ARP the moment the init routine marks the interface 2787 * as running. However, even though the MAC may have been initialized, 2788 * there may be a delay of a few seconds before the PHY completes 2789 * autonegotiation and the link is brought up. Any transmissions 2790 * made during that delay will be lost. Dealing with this is tricky: 2791 * we can't just pause in the init routine while waiting for the 2792 * PHY to come ready since that would bring the whole system to 2793 * a screeching halt for several seconds. 2794 * 2795 * What we do here is prevent the TX start routine from sending 2796 * any packets until a link has been established. After the 2797 * interface has been initialized, the tick routine will poll 2798 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2799 * that time, packets will stay in the send queue, and once the 2800 * link comes up, they will be flushed out to the wire. 2801 */ 2802 if (!sc->dc_link && mii->mii_media_status & IFM_ACTIVE && 2803 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2804 sc->dc_link++; 2805 if (ifp->if_snd.ifq_head != NULL) 2806 dc_start(ifp); 2807 } 2808 2809 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 2810 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 2811 else 2812 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 2813 2814 DC_UNLOCK(sc); 2815 } 2816 2817 /* 2818 * A transmit underrun has occurred. Back off the transmit threshold, 2819 * or switch to store and forward mode if we have to. 2820 */ 2821 static void 2822 dc_tx_underrun(struct dc_softc *sc) 2823 { 2824 u_int32_t isr; 2825 int i; 2826 2827 if (DC_IS_DAVICOM(sc)) 2828 dc_init(sc); 2829 2830 if (DC_IS_INTEL(sc)) { 2831 /* 2832 * The real 21143 requires that the transmitter be idle 2833 * in order to change the transmit threshold or store 2834 * and forward state. 2835 */ 2836 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2837 2838 for (i = 0; i < DC_TIMEOUT; i++) { 2839 isr = CSR_READ_4(sc, DC_ISR); 2840 if (isr & DC_ISR_TX_IDLE) 2841 break; 2842 DELAY(10); 2843 } 2844 if (i == DC_TIMEOUT) { 2845 printf("dc%d: failed to force tx to idle state\n", 2846 sc->dc_unit); 2847 dc_init(sc); 2848 } 2849 } 2850 2851 printf("dc%d: TX underrun -- ", sc->dc_unit); 2852 sc->dc_txthresh += DC_TXTHRESH_INC; 2853 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 2854 printf("using store and forward mode\n"); 2855 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2856 } else { 2857 printf("increasing TX threshold\n"); 2858 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 2859 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2860 } 2861 2862 if (DC_IS_INTEL(sc)) 2863 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2864 } 2865 2866 #ifdef DEVICE_POLLING 2867 static poll_handler_t dc_poll; 2868 2869 static void 2870 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2871 { 2872 struct dc_softc *sc = ifp->if_softc; 2873 2874 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 2875 /* Re-enable interrupts. */ 2876 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2877 return; 2878 } 2879 sc->rxcycles = count; 2880 dc_rxeof(sc); 2881 dc_txeof(sc); 2882 if (ifp->if_snd.ifq_head != NULL && !(ifp->if_flags & IFF_OACTIVE)) 2883 dc_start(ifp); 2884 2885 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2886 u_int32_t status; 2887 2888 status = CSR_READ_4(sc, DC_ISR); 2889 status &= (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF | 2890 DC_ISR_TX_NOBUF | DC_ISR_TX_IDLE | DC_ISR_TX_UNDERRUN | 2891 DC_ISR_BUS_ERR); 2892 if (!status) 2893 return; 2894 /* ack what we have */ 2895 CSR_WRITE_4(sc, DC_ISR, status); 2896 2897 if (status & (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF)) { 2898 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 2899 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 2900 2901 if (dc_rx_resync(sc)) 2902 dc_rxeof(sc); 2903 } 2904 /* restart transmit unit if necessary */ 2905 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 2906 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2907 2908 if (status & DC_ISR_TX_UNDERRUN) 2909 dc_tx_underrun(sc); 2910 2911 if (status & DC_ISR_BUS_ERR) { 2912 printf("dc_poll: dc%d bus error\n", sc->dc_unit); 2913 dc_reset(sc); 2914 dc_init(sc); 2915 } 2916 } 2917 } 2918 #endif /* DEVICE_POLLING */ 2919 2920 static void 2921 dc_intr(void *arg) 2922 { 2923 struct dc_softc *sc; 2924 struct ifnet *ifp; 2925 u_int32_t status; 2926 2927 sc = arg; 2928 2929 if (sc->suspended) 2930 return; 2931 2932 if ((CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) 2933 return; 2934 2935 DC_LOCK(sc); 2936 ifp = &sc->arpcom.ac_if; 2937 #ifdef DEVICE_POLLING 2938 if (ifp->if_flags & IFF_POLLING) 2939 goto done; 2940 if (ether_poll_register(dc_poll, ifp)) { /* ok, disable interrupts */ 2941 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2942 goto done; 2943 } 2944 #endif 2945 2946 /* Suppress unwanted interrupts */ 2947 if (!(ifp->if_flags & IFF_UP)) { 2948 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 2949 dc_stop(sc); 2950 DC_UNLOCK(sc); 2951 return; 2952 } 2953 2954 /* Disable interrupts. */ 2955 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2956 2957 while (((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) 2958 && status != 0xFFFFFFFF) { 2959 2960 CSR_WRITE_4(sc, DC_ISR, status); 2961 2962 if (status & DC_ISR_RX_OK) { 2963 int curpkts; 2964 curpkts = ifp->if_ipackets; 2965 dc_rxeof(sc); 2966 if (curpkts == ifp->if_ipackets) { 2967 while (dc_rx_resync(sc)) 2968 dc_rxeof(sc); 2969 } 2970 } 2971 2972 if (status & (DC_ISR_TX_OK | DC_ISR_TX_NOBUF)) 2973 dc_txeof(sc); 2974 2975 if (status & DC_ISR_TX_IDLE) { 2976 dc_txeof(sc); 2977 if (sc->dc_cdata.dc_tx_cnt) { 2978 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2979 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2980 } 2981 } 2982 2983 if (status & DC_ISR_TX_UNDERRUN) 2984 dc_tx_underrun(sc); 2985 2986 if ((status & DC_ISR_RX_WATDOGTIMEO) 2987 || (status & DC_ISR_RX_NOBUF)) { 2988 int curpkts; 2989 curpkts = ifp->if_ipackets; 2990 dc_rxeof(sc); 2991 if (curpkts == ifp->if_ipackets) { 2992 while (dc_rx_resync(sc)) 2993 dc_rxeof(sc); 2994 } 2995 } 2996 2997 if (status & DC_ISR_BUS_ERR) { 2998 dc_reset(sc); 2999 dc_init(sc); 3000 } 3001 } 3002 3003 /* Re-enable interrupts. */ 3004 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3005 3006 if (ifp->if_snd.ifq_head != NULL) 3007 dc_start(ifp); 3008 3009 #ifdef DEVICE_POLLING 3010 done: 3011 #endif 3012 3013 DC_UNLOCK(sc); 3014 } 3015 3016 /* 3017 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 3018 * pointers to the fragment pointers. 3019 */ 3020 static int 3021 dc_encap(struct dc_softc *sc, struct mbuf *m_head, u_int32_t *txidx) 3022 { 3023 struct dc_desc *f = NULL; 3024 struct mbuf *m; 3025 int frag, cur, cnt = 0, chainlen = 0; 3026 3027 /* 3028 * If there's no way we can send any packets, return now. 3029 */ 3030 if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt < 6) 3031 return (ENOBUFS); 3032 3033 /* 3034 * Count the number of frags in this chain to see if 3035 * we need to m_defrag. Since the descriptor list is shared 3036 * by all packets, we'll m_defrag long chains so that they 3037 * do not use up the entire list, even if they would fit. 3038 */ 3039 3040 for (m = m_head; m != NULL; m = m->m_next) 3041 chainlen++; 3042 3043 if ((chainlen > DC_TX_LIST_CNT / 4) || 3044 ((DC_TX_LIST_CNT - (chainlen + sc->dc_cdata.dc_tx_cnt)) < 6)) { 3045 m = m_defrag(m_head, M_DONTWAIT); 3046 if (m == NULL) 3047 return (ENOBUFS); 3048 m_head = m; 3049 } 3050 3051 /* 3052 * Start packing the mbufs in this chain into 3053 * the fragment pointers. Stop when we run out 3054 * of fragments or hit the end of the mbuf chain. 3055 */ 3056 m = m_head; 3057 cur = frag = *txidx; 3058 3059 for (m = m_head; m != NULL; m = m->m_next) { 3060 if (m->m_len != 0) { 3061 if (sc->dc_flags & DC_TX_ADMTEK_WAR) { 3062 if (*txidx != sc->dc_cdata.dc_tx_prod && 3063 frag == (DC_TX_LIST_CNT - 1)) 3064 return (ENOBUFS); 3065 } 3066 if ((DC_TX_LIST_CNT - 3067 (sc->dc_cdata.dc_tx_cnt + cnt)) < 5) 3068 return (ENOBUFS); 3069 3070 f = &sc->dc_ldata->dc_tx_list[frag]; 3071 f->dc_ctl = DC_TXCTL_TLINK | m->m_len; 3072 if (cnt == 0) { 3073 f->dc_status = 0; 3074 f->dc_ctl |= DC_TXCTL_FIRSTFRAG; 3075 } else 3076 f->dc_status = DC_TXSTAT_OWN; 3077 f->dc_data = vtophys(mtod(m, vm_offset_t)); 3078 cur = frag; 3079 DC_INC(frag, DC_TX_LIST_CNT); 3080 cnt++; 3081 } 3082 } 3083 3084 if (m != NULL) 3085 return (ENOBUFS); 3086 3087 sc->dc_cdata.dc_tx_cnt += cnt; 3088 sc->dc_cdata.dc_tx_chain[cur] = m_head; 3089 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_LASTFRAG; 3090 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 3091 sc->dc_ldata->dc_tx_list[*txidx].dc_ctl |= DC_TXCTL_FINT; 3092 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 3093 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 3094 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 3095 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 3096 sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN; 3097 *txidx = frag; 3098 3099 return (0); 3100 } 3101 3102 /* 3103 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3104 * to the mbuf data regions directly in the transmit lists. We also save a 3105 * copy of the pointers since the transmit list fragment pointers are 3106 * physical addresses. 3107 */ 3108 3109 static void 3110 dc_start(struct ifnet *ifp) 3111 { 3112 struct dc_softc *sc; 3113 struct mbuf *m_head = NULL, *m; 3114 int idx; 3115 3116 sc = ifp->if_softc; 3117 3118 DC_LOCK(sc); 3119 3120 if (!sc->dc_link && ifp->if_snd.ifq_len < 10) { 3121 DC_UNLOCK(sc); 3122 return; 3123 } 3124 3125 if (ifp->if_flags & IFF_OACTIVE) { 3126 DC_UNLOCK(sc); 3127 return; 3128 } 3129 3130 idx = sc->dc_cdata.dc_tx_prod; 3131 3132 while (sc->dc_cdata.dc_tx_chain[idx] == NULL) { 3133 IF_DEQUEUE(&ifp->if_snd, m_head); 3134 if (m_head == NULL) 3135 break; 3136 3137 if (sc->dc_flags & DC_TX_COALESCE && 3138 (m_head->m_next != NULL || 3139 sc->dc_flags & DC_TX_ALIGN)) { 3140 m = m_defrag(m_head, M_DONTWAIT); 3141 if (m == NULL) { 3142 IF_PREPEND(&ifp->if_snd, m_head); 3143 ifp->if_flags |= IFF_OACTIVE; 3144 break; 3145 } else { 3146 m_head = m; 3147 } 3148 } 3149 3150 if (dc_encap(sc, m_head, &idx)) { 3151 IF_PREPEND(&ifp->if_snd, m_head); 3152 ifp->if_flags |= IFF_OACTIVE; 3153 break; 3154 } 3155 3156 /* 3157 * If there's a BPF listener, bounce a copy of this frame 3158 * to him. 3159 */ 3160 BPF_MTAP(ifp, m_head); 3161 3162 if (sc->dc_flags & DC_TX_ONE) { 3163 ifp->if_flags |= IFF_OACTIVE; 3164 break; 3165 } 3166 } 3167 3168 /* Transmit */ 3169 sc->dc_cdata.dc_tx_prod = idx; 3170 if (!(sc->dc_flags & DC_TX_POLL)) 3171 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3172 3173 /* 3174 * Set a timeout in case the chip goes out to lunch. 3175 */ 3176 ifp->if_timer = 5; 3177 3178 DC_UNLOCK(sc); 3179 } 3180 3181 static void 3182 dc_init(void *xsc) 3183 { 3184 struct dc_softc *sc = xsc; 3185 struct ifnet *ifp = &sc->arpcom.ac_if; 3186 struct mii_data *mii; 3187 3188 DC_LOCK(sc); 3189 3190 mii = device_get_softc(sc->dc_miibus); 3191 3192 /* 3193 * Cancel pending I/O and free all RX/TX buffers. 3194 */ 3195 dc_stop(sc); 3196 dc_reset(sc); 3197 3198 /* 3199 * Set cache alignment and burst length. 3200 */ 3201 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 3202 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3203 else 3204 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME | DC_BUSCTL_MRLE); 3205 /* 3206 * Evenly share the bus between receive and transmit process. 3207 */ 3208 if (DC_IS_INTEL(sc)) 3209 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3210 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3211 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3212 } else { 3213 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3214 } 3215 if (sc->dc_flags & DC_TX_POLL) 3216 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3217 switch(sc->dc_cachesize) { 3218 case 32: 3219 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3220 break; 3221 case 16: 3222 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3223 break; 3224 case 8: 3225 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3226 break; 3227 case 0: 3228 default: 3229 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3230 break; 3231 } 3232 3233 if (sc->dc_flags & DC_TX_STORENFWD) 3234 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3235 else { 3236 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3237 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3238 } else { 3239 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3240 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3241 } 3242 } 3243 3244 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3245 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3246 3247 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3248 /* 3249 * The app notes for the 98713 and 98715A say that 3250 * in order to have the chips operate properly, a magic 3251 * number must be written to CSR16. Macronix does not 3252 * document the meaning of these bits so there's no way 3253 * to know exactly what they do. The 98713 has a magic 3254 * number all its own; the rest all use a different one. 3255 */ 3256 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3257 if (sc->dc_type == DC_TYPE_98713) 3258 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3259 else 3260 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3261 } 3262 3263 if (DC_IS_XIRCOM(sc)) { 3264 /* 3265 * setup General Purpose Port mode and data so the tulip 3266 * can talk to the MII. 3267 */ 3268 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3269 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3270 DELAY(10); 3271 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3272 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3273 DELAY(10); 3274 } 3275 3276 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3277 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3278 3279 /* Init circular RX list. */ 3280 if (dc_list_rx_init(sc) == ENOBUFS) { 3281 printf("dc%d: initialization failed: no " 3282 "memory for rx buffers\n", sc->dc_unit); 3283 dc_stop(sc); 3284 DC_UNLOCK(sc); 3285 return; 3286 } 3287 3288 /* 3289 * Init tx descriptors. 3290 */ 3291 dc_list_tx_init(sc); 3292 3293 /* 3294 * Load the address of the RX list. 3295 */ 3296 CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0])); 3297 CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0])); 3298 3299 /* 3300 * Enable interrupts. 3301 */ 3302 #ifdef DEVICE_POLLING 3303 /* 3304 * ... but only if we are not polling, and make sure they are off in 3305 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3306 * after a reset. 3307 */ 3308 if (ifp->if_flags & IFF_POLLING) 3309 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3310 else 3311 #endif 3312 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3313 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3314 3315 /* Enable transmitter. */ 3316 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3317 3318 /* 3319 * If this is an Intel 21143 and we're not using the 3320 * MII port, program the LED control pins so we get 3321 * link and activity indications. 3322 */ 3323 if (sc->dc_flags & DC_TULIP_LEDS) { 3324 CSR_WRITE_4(sc, DC_WATCHDOG, 3325 DC_WDOG_CTLWREN | DC_WDOG_LINK | DC_WDOG_ACTIVITY); 3326 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3327 } 3328 3329 /* 3330 * Load the RX/multicast filter. We do this sort of late 3331 * because the filter programming scheme on the 21143 and 3332 * some clones requires DMAing a setup frame via the TX 3333 * engine, and we need the transmitter enabled for that. 3334 */ 3335 dc_setfilt(sc); 3336 3337 /* Enable receiver. */ 3338 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3339 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3340 3341 mii_mediachg(mii); 3342 dc_setcfg(sc, sc->dc_if_media); 3343 3344 ifp->if_flags |= IFF_RUNNING; 3345 ifp->if_flags &= ~IFF_OACTIVE; 3346 3347 /* Don't start the ticker if this is a homePNA link. */ 3348 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) 3349 sc->dc_link = 1; 3350 else { 3351 if (sc->dc_flags & DC_21143_NWAY) 3352 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3353 else 3354 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3355 } 3356 3357 #ifdef SRM_MEDIA 3358 if(sc->dc_srm_media) { 3359 struct ifreq ifr; 3360 3361 ifr.ifr_media = sc->dc_srm_media; 3362 ifmedia_ioctl(ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA); 3363 sc->dc_srm_media = 0; 3364 } 3365 #endif 3366 DC_UNLOCK(sc); 3367 } 3368 3369 /* 3370 * Set media options. 3371 */ 3372 static int 3373 dc_ifmedia_upd(struct ifnet *ifp) 3374 { 3375 struct dc_softc *sc; 3376 struct mii_data *mii; 3377 struct ifmedia *ifm; 3378 3379 sc = ifp->if_softc; 3380 mii = device_get_softc(sc->dc_miibus); 3381 mii_mediachg(mii); 3382 ifm = &mii->mii_media; 3383 3384 if (DC_IS_DAVICOM(sc) && 3385 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) 3386 dc_setcfg(sc, ifm->ifm_media); 3387 else 3388 sc->dc_link = 0; 3389 3390 return (0); 3391 } 3392 3393 /* 3394 * Report current media status. 3395 */ 3396 static void 3397 dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3398 { 3399 struct dc_softc *sc; 3400 struct mii_data *mii; 3401 struct ifmedia *ifm; 3402 3403 sc = ifp->if_softc; 3404 mii = device_get_softc(sc->dc_miibus); 3405 mii_pollstat(mii); 3406 ifm = &mii->mii_media; 3407 if (DC_IS_DAVICOM(sc)) { 3408 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 3409 ifmr->ifm_active = ifm->ifm_media; 3410 ifmr->ifm_status = 0; 3411 return; 3412 } 3413 } 3414 ifmr->ifm_active = mii->mii_media_active; 3415 ifmr->ifm_status = mii->mii_media_status; 3416 } 3417 3418 static int 3419 dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3420 { 3421 struct dc_softc *sc = ifp->if_softc; 3422 struct ifreq *ifr = (struct ifreq *)data; 3423 struct mii_data *mii; 3424 int error = 0; 3425 3426 DC_LOCK(sc); 3427 3428 switch (command) { 3429 case SIOCSIFFLAGS: 3430 if (ifp->if_flags & IFF_UP) { 3431 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) & 3432 (IFF_PROMISC | IFF_ALLMULTI); 3433 3434 if (ifp->if_flags & IFF_RUNNING) { 3435 if (need_setfilt) 3436 dc_setfilt(sc); 3437 } else { 3438 sc->dc_txthresh = 0; 3439 dc_init(sc); 3440 } 3441 } else { 3442 if (ifp->if_flags & IFF_RUNNING) 3443 dc_stop(sc); 3444 } 3445 sc->dc_if_flags = ifp->if_flags; 3446 error = 0; 3447 break; 3448 case SIOCADDMULTI: 3449 case SIOCDELMULTI: 3450 dc_setfilt(sc); 3451 error = 0; 3452 break; 3453 case SIOCGIFMEDIA: 3454 case SIOCSIFMEDIA: 3455 mii = device_get_softc(sc->dc_miibus); 3456 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3457 #ifdef SRM_MEDIA 3458 if (sc->dc_srm_media) 3459 sc->dc_srm_media = 0; 3460 #endif 3461 break; 3462 default: 3463 error = ether_ioctl(ifp, command, data); 3464 break; 3465 } 3466 3467 DC_UNLOCK(sc); 3468 3469 return (error); 3470 } 3471 3472 static void 3473 dc_watchdog(struct ifnet *ifp) 3474 { 3475 struct dc_softc *sc; 3476 3477 sc = ifp->if_softc; 3478 3479 DC_LOCK(sc); 3480 3481 ifp->if_oerrors++; 3482 printf("dc%d: watchdog timeout\n", sc->dc_unit); 3483 3484 dc_stop(sc); 3485 dc_reset(sc); 3486 dc_init(sc); 3487 3488 if (ifp->if_snd.ifq_head != NULL) 3489 dc_start(ifp); 3490 3491 DC_UNLOCK(sc); 3492 } 3493 3494 /* 3495 * Stop the adapter and free any mbufs allocated to the 3496 * RX and TX lists. 3497 */ 3498 static void 3499 dc_stop(struct dc_softc *sc) 3500 { 3501 struct ifnet *ifp; 3502 struct dc_list_data *ld; 3503 struct dc_chain_data *cd; 3504 int i; 3505 3506 DC_LOCK(sc); 3507 3508 ifp = &sc->arpcom.ac_if; 3509 ifp->if_timer = 0; 3510 ld = sc->dc_ldata; 3511 cd = &sc->dc_cdata; 3512 3513 callout_stop(&sc->dc_stat_ch); 3514 3515 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3516 #ifdef DEVICE_POLLING 3517 ether_poll_deregister(ifp); 3518 #endif 3519 3520 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)); 3521 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3522 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3523 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3524 sc->dc_link = 0; 3525 3526 /* 3527 * Free data in the RX lists. 3528 */ 3529 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3530 if (cd->dc_rx_chain[i] != NULL) { 3531 m_freem(sc->dc_cdata.dc_rx_chain[i]); 3532 sc->dc_cdata.dc_rx_chain[i] = NULL; 3533 } 3534 } 3535 bzero(&ld->dc_rx_list, sizeof(ld->dc_rx_list)); 3536 3537 /* 3538 * Free the TX list buffers. 3539 */ 3540 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3541 if (cd->dc_tx_chain[i] != NULL) { 3542 if ((ld->dc_tx_list[i].dc_ctl & DC_TXCTL_SETUP) || 3543 !(ld->dc_tx_list[i].dc_ctl & DC_TXCTL_LASTFRAG)) { 3544 cd->dc_tx_chain[i] = NULL; 3545 continue; 3546 } 3547 m_freem(sc->dc_cdata.dc_tx_chain[i]); 3548 cd->dc_tx_chain[i] = NULL; 3549 } 3550 } 3551 bzero(&ld->dc_tx_list, sizeof(ld->dc_tx_list)); 3552 3553 DC_UNLOCK(sc); 3554 } 3555 3556 /* 3557 * Device suspend routine. Stop the interface and save some PCI 3558 * settings in case the BIOS doesn't restore them properly on 3559 * resume. 3560 */ 3561 static int 3562 dc_suspend(device_t dev) 3563 { 3564 struct dc_softc *sc; 3565 int i, s; 3566 3567 s = splimp(); 3568 3569 sc = device_get_softc(dev); 3570 3571 dc_stop(sc); 3572 3573 for (i = 0; i < 5; i++) 3574 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 3575 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 3576 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 3577 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 3578 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 3579 3580 sc->suspended = 1; 3581 3582 splx(s); 3583 return (0); 3584 } 3585 3586 /* 3587 * Device resume routine. Restore some PCI settings in case the BIOS 3588 * doesn't, re-enable busmastering, and restart the interface if 3589 * appropriate. 3590 */ 3591 static int 3592 dc_resume(device_t dev) 3593 { 3594 struct dc_softc *sc; 3595 struct ifnet *ifp; 3596 int i, s; 3597 3598 s = splimp(); 3599 3600 sc = device_get_softc(dev); 3601 ifp = &sc->arpcom.ac_if; 3602 #ifndef BURN_BRIDGES 3603 dc_acpi(dev); 3604 #endif 3605 /* better way to do this? */ 3606 for (i = 0; i < 5; i++) 3607 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 3608 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 3609 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 3610 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 3611 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 3612 3613 /* reenable busmastering */ 3614 pci_enable_busmaster(dev); 3615 pci_enable_io(dev, DC_RES); 3616 3617 /* reinitialize interface if necessary */ 3618 if (ifp->if_flags & IFF_UP) 3619 dc_init(sc); 3620 3621 sc->suspended = 0; 3622 3623 splx(s); 3624 return (0); 3625 } 3626 3627 /* 3628 * Stop all chip I/O so that the kernel's probe routines don't 3629 * get confused by errant DMAs when rebooting. 3630 */ 3631 static void 3632 dc_shutdown(device_t dev) 3633 { 3634 struct dc_softc *sc; 3635 3636 sc = device_get_softc(dev); 3637 3638 dc_stop(sc); 3639 } 3640