196f2e892SBill Paul /* 296f2e892SBill Paul * Copyright (c) 1997, 1998, 1999 396f2e892SBill Paul * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 496f2e892SBill Paul * 596f2e892SBill Paul * Redistribution and use in source and binary forms, with or without 696f2e892SBill Paul * modification, are permitted provided that the following conditions 796f2e892SBill Paul * are met: 896f2e892SBill Paul * 1. Redistributions of source code must retain the above copyright 996f2e892SBill Paul * notice, this list of conditions and the following disclaimer. 1096f2e892SBill Paul * 2. Redistributions in binary form must reproduce the above copyright 1196f2e892SBill Paul * notice, this list of conditions and the following disclaimer in the 1296f2e892SBill Paul * documentation and/or other materials provided with the distribution. 1396f2e892SBill Paul * 3. All advertising materials mentioning features or use of this software 1496f2e892SBill Paul * must display the following acknowledgement: 1596f2e892SBill Paul * This product includes software developed by Bill Paul. 1696f2e892SBill Paul * 4. Neither the name of the author nor the names of any co-contributors 1796f2e892SBill Paul * may be used to endorse or promote products derived from this software 1896f2e892SBill Paul * without specific prior written permission. 1996f2e892SBill Paul * 2096f2e892SBill Paul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2196f2e892SBill Paul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2296f2e892SBill Paul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2396f2e892SBill Paul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2496f2e892SBill Paul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2596f2e892SBill Paul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2696f2e892SBill Paul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2796f2e892SBill Paul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2896f2e892SBill Paul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2996f2e892SBill Paul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3096f2e892SBill Paul * THE POSSIBILITY OF SUCH DAMAGE. 3196f2e892SBill Paul */ 3296f2e892SBill Paul 334dc52c32SDavid E. O'Brien #include <sys/cdefs.h> 344dc52c32SDavid E. O'Brien __FBSDID("$FreeBSD$"); 354dc52c32SDavid E. O'Brien 3696f2e892SBill Paul /* 3796f2e892SBill Paul * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 3896f2e892SBill Paul * series chips and several workalikes including the following: 3996f2e892SBill Paul * 40ead7cde9SBill Paul * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 4196f2e892SBill Paul * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 4296f2e892SBill Paul * Lite-On 82c168/82c169 PNIC (www.litecom.com) 4396f2e892SBill Paul * ASIX Electronics AX88140A (www.asix.com.tw) 4496f2e892SBill Paul * ASIX Electronics AX88141 (www.asix.com.tw) 4596f2e892SBill Paul * ADMtek AL981 (www.admtek.com.tw) 4696f2e892SBill Paul * ADMtek AN985 (www.admtek.com.tw) 474c16d09eSWarner Losh * Netgear FA511 (www.netgear.com) Appears to be rebadged ADMTek AN985 4888d739dcSBill Paul * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 499ca710f6SJeroen Ruigrok van der Werven * Accton EN1217 (www.accton.com) 50feb78939SJonathan Chen * Xircom X3201 (www.xircom.com) 511d5e5310SBill Paul * Abocom FE2500 521af8bec7SBill Paul * Conexant LANfinity (www.conexant.com) 537eac366bSMartin Blapp * 3Com OfficeConnect 10/100B 3CSOHO100B (www.3com.com) 5496f2e892SBill Paul * 5596f2e892SBill Paul * Datasheets for the 21143 are available at developer.intel.com. 5696f2e892SBill Paul * Datasheets for the clone parts can be found at their respective sites. 5796f2e892SBill Paul * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 5896f2e892SBill Paul * The PNIC II is essentially a Macronix 98715A chip; the only difference 5996f2e892SBill Paul * worth noting is that its multicast hash table is only 128 bits wide 6096f2e892SBill Paul * instead of 512. 6196f2e892SBill Paul * 6296f2e892SBill Paul * Written by Bill Paul <wpaul@ee.columbia.edu> 6396f2e892SBill Paul * Electrical Engineering Department 6496f2e892SBill Paul * Columbia University, New York City 6596f2e892SBill Paul */ 6696f2e892SBill Paul /* 6796f2e892SBill Paul * The Intel 21143 is the successor to the DEC 21140. It is basically 6896f2e892SBill Paul * the same as the 21140 but with a few new features. The 21143 supports 6996f2e892SBill Paul * three kinds of media attachments: 7096f2e892SBill Paul * 7196f2e892SBill Paul * o MII port, for 10Mbps and 100Mbps support and NWAY 7296f2e892SBill Paul * autonegotiation provided by an external PHY. 7396f2e892SBill Paul * o SYM port, for symbol mode 100Mbps support. 7496f2e892SBill Paul * o 10baseT port. 7596f2e892SBill Paul * o AUI/BNC port. 7696f2e892SBill Paul * 7796f2e892SBill Paul * The 100Mbps SYM port and 10baseT port can be used together in 7896f2e892SBill Paul * combination with the internal NWAY support to create a 10/100 7996f2e892SBill Paul * autosensing configuration. 8096f2e892SBill Paul * 8196f2e892SBill Paul * Note that not all tulip workalikes are handled in this driver: we only 8296f2e892SBill Paul * deal with those which are relatively well behaved. The Winbond is 8396f2e892SBill Paul * handled separately due to its different register offsets and the 8496f2e892SBill Paul * special handling needed for its various bugs. The PNIC is handled 8596f2e892SBill Paul * here, but I'm not thrilled about it. 8696f2e892SBill Paul * 8796f2e892SBill Paul * All of the workalike chips use some form of MII transceiver support 8896f2e892SBill Paul * with the exception of the Macronix chips, which also have a SYM port. 8996f2e892SBill Paul * The ASIX AX88140A is also documented to have a SYM port, but all 9096f2e892SBill Paul * the cards I've seen use an MII transceiver, probably because the 9196f2e892SBill Paul * AX88140A doesn't support internal NWAY. 9296f2e892SBill Paul */ 9396f2e892SBill Paul 9496f2e892SBill Paul #include <sys/param.h> 95af4358c7SMaxime Henrion #include <sys/endian.h> 9696f2e892SBill Paul #include <sys/systm.h> 9796f2e892SBill Paul #include <sys/sockio.h> 9896f2e892SBill Paul #include <sys/mbuf.h> 9996f2e892SBill Paul #include <sys/malloc.h> 10096f2e892SBill Paul #include <sys/kernel.h> 10196f2e892SBill Paul #include <sys/socket.h> 10201faf54bSLuigi Rizzo #include <sys/sysctl.h> 10396f2e892SBill Paul 10496f2e892SBill Paul #include <net/if.h> 10596f2e892SBill Paul #include <net/if_arp.h> 10696f2e892SBill Paul #include <net/ethernet.h> 10796f2e892SBill Paul #include <net/if_dl.h> 10896f2e892SBill Paul #include <net/if_media.h> 109db40c1aeSDoug Ambrisko #include <net/if_types.h> 110db40c1aeSDoug Ambrisko #include <net/if_vlan_var.h> 11196f2e892SBill Paul 11296f2e892SBill Paul #include <net/bpf.h> 11396f2e892SBill Paul 11496f2e892SBill Paul #include <machine/bus_pio.h> 11596f2e892SBill Paul #include <machine/bus_memio.h> 11696f2e892SBill Paul #include <machine/bus.h> 11796f2e892SBill Paul #include <machine/resource.h> 11896f2e892SBill Paul #include <sys/bus.h> 11996f2e892SBill Paul #include <sys/rman.h> 12096f2e892SBill Paul 12196f2e892SBill Paul #include <dev/mii/mii.h> 12296f2e892SBill Paul #include <dev/mii/miivar.h> 12396f2e892SBill Paul 12419b7ffd1SWarner Losh #include <dev/pci/pcireg.h> 12519b7ffd1SWarner Losh #include <dev/pci/pcivar.h> 12696f2e892SBill Paul 12796f2e892SBill Paul #define DC_USEIOSPACE 1285c1cfac4SBill Paul #ifdef __alpha__ 1295c1cfac4SBill Paul #define SRM_MEDIA 1305c1cfac4SBill Paul #endif 13196f2e892SBill Paul 13296f2e892SBill Paul #include <pci/if_dcreg.h> 13396f2e892SBill Paul 134ec6a7299SMaxime Henrion #ifdef __sparc64__ 135ec6a7299SMaxime Henrion #include <dev/ofw/openfirm.h> 136ec6a7299SMaxime Henrion #include <machine/ofw_machdep.h> 137ec6a7299SMaxime Henrion #endif 138ec6a7299SMaxime Henrion 139f246e4a1SMatthew N. Dodd MODULE_DEPEND(dc, pci, 1, 1, 1); 140f246e4a1SMatthew N. Dodd MODULE_DEPEND(dc, ether, 1, 1, 1); 14195a16455SPeter Wemm MODULE_DEPEND(dc, miibus, 1, 1, 1); 14295a16455SPeter Wemm 14396f2e892SBill Paul /* "controller miibus0" required. See GENERIC if you get errors here. */ 14496f2e892SBill Paul #include "miibus_if.h" 14596f2e892SBill Paul 14696f2e892SBill Paul /* 14796f2e892SBill Paul * Various supported device vendors/types and their names. 14896f2e892SBill Paul */ 14996f2e892SBill Paul static struct dc_type dc_devs[] = { 15096f2e892SBill Paul { DC_VENDORID_DEC, DC_DEVICEID_21143, 15196f2e892SBill Paul "Intel 21143 10/100BaseTX" }, 15238deb45fSTom Rhodes { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009, 15338deb45fSTom Rhodes "Davicom DM9009 10/100BaseTX" }, 15496f2e892SBill Paul { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 15596f2e892SBill Paul "Davicom DM9100 10/100BaseTX" }, 15696f2e892SBill Paul { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 15796f2e892SBill Paul "Davicom DM9102 10/100BaseTX" }, 15888d739dcSBill Paul { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 15988d739dcSBill Paul "Davicom DM9102A 10/100BaseTX" }, 16096f2e892SBill Paul { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 16196f2e892SBill Paul "ADMtek AL981 10/100BaseTX" }, 16296f2e892SBill Paul { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 16396f2e892SBill Paul "ADMtek AN985 10/100BaseTX" }, 164e351d778SMartin Blapp { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511, 165e351d778SMartin Blapp "ADMtek ADM9511 10/100BaseTX" }, 166e351d778SMartin Blapp { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513, 167e351d778SMartin Blapp "ADMtek ADM9513 10/100BaseTX" }, 1684c16d09eSWarner Losh { DC_VENDORID_ADMTEK, DC_DEVICEID_FA511, 1694c16d09eSWarner Losh "Netgear FA511 10/100BaseTX" }, 17096f2e892SBill Paul { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 17196f2e892SBill Paul "ASIX AX88140A 10/100BaseTX" }, 17296f2e892SBill Paul { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 17396f2e892SBill Paul "ASIX AX88141 10/100BaseTX" }, 17496f2e892SBill Paul { DC_VENDORID_MX, DC_DEVICEID_98713, 17596f2e892SBill Paul "Macronix 98713 10/100BaseTX" }, 17696f2e892SBill Paul { DC_VENDORID_MX, DC_DEVICEID_98713, 17796f2e892SBill Paul "Macronix 98713A 10/100BaseTX" }, 17896f2e892SBill Paul { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 17996f2e892SBill Paul "Compex RL100-TX 10/100BaseTX" }, 18096f2e892SBill Paul { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 18196f2e892SBill Paul "Compex RL100-TX 10/100BaseTX" }, 18296f2e892SBill Paul { DC_VENDORID_MX, DC_DEVICEID_987x5, 18396f2e892SBill Paul "Macronix 98715/98715A 10/100BaseTX" }, 18496f2e892SBill Paul { DC_VENDORID_MX, DC_DEVICEID_987x5, 18579d11e09SBill Paul "Macronix 98715AEC-C 10/100BaseTX" }, 18679d11e09SBill Paul { DC_VENDORID_MX, DC_DEVICEID_987x5, 18796f2e892SBill Paul "Macronix 98725 10/100BaseTX" }, 188ead7cde9SBill Paul { DC_VENDORID_MX, DC_DEVICEID_98727, 189ead7cde9SBill Paul "Macronix 98727/98732 10/100BaseTX" }, 19096f2e892SBill Paul { DC_VENDORID_LO, DC_DEVICEID_82C115, 19196f2e892SBill Paul "LC82C115 PNIC II 10/100BaseTX" }, 19296f2e892SBill Paul { DC_VENDORID_LO, DC_DEVICEID_82C168, 19396f2e892SBill Paul "82c168 PNIC 10/100BaseTX" }, 19496f2e892SBill Paul { DC_VENDORID_LO, DC_DEVICEID_82C168, 19596f2e892SBill Paul "82c169 PNIC 10/100BaseTX" }, 1969ca710f6SJeroen Ruigrok van der Werven { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217, 1979ca710f6SJeroen Ruigrok van der Werven "Accton EN1217 10/100BaseTX" }, 198fa167b8eSBill Paul { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242, 199fa167b8eSBill Paul "Accton EN2242 MiniPCI 10/100BaseTX" }, 200feb78939SJonathan Chen { DC_VENDORID_XIRCOM, DC_DEVICEID_X3201, 201feb78939SJonathan Chen "Xircom X3201 10/100BaseTX" }, 2021d5e5310SBill Paul { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500, 2031d5e5310SBill Paul "Abocom FE2500 10/100BaseTX" }, 204773c505fSMIHIRA Sanpei Yoshiro { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX, 205773c505fSMIHIRA Sanpei Yoshiro "Abocom FE2500MX 10/100BaseTX" }, 2061af8bec7SBill Paul { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112, 2071af8bec7SBill Paul "Conexant LANfinity MiniPCI 10/100BaseTX" }, 208948c244dSWarner Losh { DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX, 209948c244dSWarner Losh "Hawking CB102 CardBus 10/100" }, 21097f91728SMIHIRA Sanpei Yoshiro { DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T, 21197f91728SMIHIRA Sanpei Yoshiro "PlaneX FNW-3602-T CardBus 10/100" }, 2127eac366bSMartin Blapp { DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB, 2137eac366bSMartin Blapp "3Com OfficeConnect 10/100B" }, 214e7b9ab3aSBill Paul { DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120, 215e7b9ab3aSBill Paul "Microsoft MN-120 CardBus 10/100" }, 216e7b9ab3aSBill Paul { DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130, 217e7b9ab3aSBill Paul "Microsoft MN-130 10/100" }, 218e7b9ab3aSBill Paul { DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130_FAKE, 219e7b9ab3aSBill Paul "Microsoft MN-130 10/100" }, 22096f2e892SBill Paul { 0, 0, NULL } 22196f2e892SBill Paul }; 22296f2e892SBill Paul 223e51a25f8SAlfred Perlstein static int dc_probe (device_t); 224e51a25f8SAlfred Perlstein static int dc_attach (device_t); 225e51a25f8SAlfred Perlstein static int dc_detach (device_t); 226e8388e14SMitsuru IWASAKI static int dc_suspend (device_t); 227e8388e14SMitsuru IWASAKI static int dc_resume (device_t); 228b84e866aSWarner Losh #ifndef BURN_BRIDGES 229e51a25f8SAlfred Perlstein static void dc_acpi (device_t); 230b84e866aSWarner Losh #endif 231e51a25f8SAlfred Perlstein static struct dc_type *dc_devtype (device_t); 23256e5e7aeSMaxime Henrion static int dc_newbuf (struct dc_softc *, int, int); 233a10c0e45SMike Silbersack static int dc_encap (struct dc_softc *, struct mbuf **); 234e51a25f8SAlfred Perlstein static void dc_pnic_rx_bug_war (struct dc_softc *, int); 235e51a25f8SAlfred Perlstein static int dc_rx_resync (struct dc_softc *); 236e51a25f8SAlfred Perlstein static void dc_rxeof (struct dc_softc *); 237e51a25f8SAlfred Perlstein static void dc_txeof (struct dc_softc *); 238e51a25f8SAlfred Perlstein static void dc_tick (void *); 239e51a25f8SAlfred Perlstein static void dc_tx_underrun (struct dc_softc *); 240e51a25f8SAlfred Perlstein static void dc_intr (void *); 241e51a25f8SAlfred Perlstein static void dc_start (struct ifnet *); 242e51a25f8SAlfred Perlstein static int dc_ioctl (struct ifnet *, u_long, caddr_t); 243e51a25f8SAlfred Perlstein static void dc_init (void *); 244e51a25f8SAlfred Perlstein static void dc_stop (struct dc_softc *); 245e51a25f8SAlfred Perlstein static void dc_watchdog (struct ifnet *); 246e51a25f8SAlfred Perlstein static void dc_shutdown (device_t); 247e51a25f8SAlfred Perlstein static int dc_ifmedia_upd (struct ifnet *); 248e51a25f8SAlfred Perlstein static void dc_ifmedia_sts (struct ifnet *, struct ifmediareq *); 24996f2e892SBill Paul 250e51a25f8SAlfred Perlstein static void dc_delay (struct dc_softc *); 251e51a25f8SAlfred Perlstein static void dc_eeprom_idle (struct dc_softc *); 252e51a25f8SAlfred Perlstein static void dc_eeprom_putbyte (struct dc_softc *, int); 253e51a25f8SAlfred Perlstein static void dc_eeprom_getword (struct dc_softc *, int, u_int16_t *); 25496f2e892SBill Paul static void dc_eeprom_getword_pnic 255e51a25f8SAlfred Perlstein (struct dc_softc *, int, u_int16_t *); 256feb78939SJonathan Chen static void dc_eeprom_getword_xircom 257e51a25f8SAlfred Perlstein (struct dc_softc *, int, u_int16_t *); 2583097aa70SWarner Losh static void dc_eeprom_width (struct dc_softc *); 259e51a25f8SAlfred Perlstein static void dc_read_eeprom (struct dc_softc *, caddr_t, int, int, int); 26096f2e892SBill Paul 261e51a25f8SAlfred Perlstein static void dc_mii_writebit (struct dc_softc *, int); 262e51a25f8SAlfred Perlstein static int dc_mii_readbit (struct dc_softc *); 263e51a25f8SAlfred Perlstein static void dc_mii_sync (struct dc_softc *); 264e51a25f8SAlfred Perlstein static void dc_mii_send (struct dc_softc *, u_int32_t, int); 265e51a25f8SAlfred Perlstein static int dc_mii_readreg (struct dc_softc *, struct dc_mii_frame *); 266e51a25f8SAlfred Perlstein static int dc_mii_writereg (struct dc_softc *, struct dc_mii_frame *); 267e51a25f8SAlfred Perlstein static int dc_miibus_readreg (device_t, int, int); 268e51a25f8SAlfred Perlstein static int dc_miibus_writereg (device_t, int, int, int); 269e51a25f8SAlfred Perlstein static void dc_miibus_statchg (device_t); 270e51a25f8SAlfred Perlstein static void dc_miibus_mediainit (device_t); 27196f2e892SBill Paul 272e51a25f8SAlfred Perlstein static void dc_setcfg (struct dc_softc *, int); 2733373489bSWarner Losh static uint32_t dc_mchash_le (struct dc_softc *, const uint8_t *); 2743373489bSWarner Losh static uint32_t dc_mchash_be (const uint8_t *); 275e51a25f8SAlfred Perlstein static void dc_setfilt_21143 (struct dc_softc *); 276e51a25f8SAlfred Perlstein static void dc_setfilt_asix (struct dc_softc *); 277e51a25f8SAlfred Perlstein static void dc_setfilt_admtek (struct dc_softc *); 278e51a25f8SAlfred Perlstein static void dc_setfilt_xircom (struct dc_softc *); 27996f2e892SBill Paul 280e51a25f8SAlfred Perlstein static void dc_setfilt (struct dc_softc *); 28196f2e892SBill Paul 282e51a25f8SAlfred Perlstein static void dc_reset (struct dc_softc *); 283e51a25f8SAlfred Perlstein static int dc_list_rx_init (struct dc_softc *); 284e51a25f8SAlfred Perlstein static int dc_list_tx_init (struct dc_softc *); 28596f2e892SBill Paul 2863097aa70SWarner Losh static void dc_read_srom (struct dc_softc *, int); 287e51a25f8SAlfred Perlstein static void dc_parse_21143_srom (struct dc_softc *); 288e51a25f8SAlfred Perlstein static void dc_decode_leaf_sia (struct dc_softc *, struct dc_eblock_sia *); 289e51a25f8SAlfred Perlstein static void dc_decode_leaf_mii (struct dc_softc *, struct dc_eblock_mii *); 290e51a25f8SAlfred Perlstein static void dc_decode_leaf_sym (struct dc_softc *, struct dc_eblock_sym *); 291e51a25f8SAlfred Perlstein static void dc_apply_fixup (struct dc_softc *, int); 2925c1cfac4SBill Paul 29356e5e7aeSMaxime Henrion static void dc_dma_map_txbuf (void *, bus_dma_segment_t *, int, bus_size_t, 29456e5e7aeSMaxime Henrion int); 29556e5e7aeSMaxime Henrion static void dc_dma_map_rxbuf (void *, bus_dma_segment_t *, int, bus_size_t, 29656e5e7aeSMaxime Henrion int); 29756e5e7aeSMaxime Henrion 29896f2e892SBill Paul #ifdef DC_USEIOSPACE 29996f2e892SBill Paul #define DC_RES SYS_RES_IOPORT 30096f2e892SBill Paul #define DC_RID DC_PCI_CFBIO 30196f2e892SBill Paul #else 30296f2e892SBill Paul #define DC_RES SYS_RES_MEMORY 30396f2e892SBill Paul #define DC_RID DC_PCI_CFBMA 30496f2e892SBill Paul #endif 30596f2e892SBill Paul 30696f2e892SBill Paul static device_method_t dc_methods[] = { 30796f2e892SBill Paul /* Device interface */ 30896f2e892SBill Paul DEVMETHOD(device_probe, dc_probe), 30996f2e892SBill Paul DEVMETHOD(device_attach, dc_attach), 31096f2e892SBill Paul DEVMETHOD(device_detach, dc_detach), 311e8388e14SMitsuru IWASAKI DEVMETHOD(device_suspend, dc_suspend), 312e8388e14SMitsuru IWASAKI DEVMETHOD(device_resume, dc_resume), 31396f2e892SBill Paul DEVMETHOD(device_shutdown, dc_shutdown), 31496f2e892SBill Paul 31596f2e892SBill Paul /* bus interface */ 31696f2e892SBill Paul DEVMETHOD(bus_print_child, bus_generic_print_child), 31796f2e892SBill Paul DEVMETHOD(bus_driver_added, bus_generic_driver_added), 31896f2e892SBill Paul 31996f2e892SBill Paul /* MII interface */ 32096f2e892SBill Paul DEVMETHOD(miibus_readreg, dc_miibus_readreg), 32196f2e892SBill Paul DEVMETHOD(miibus_writereg, dc_miibus_writereg), 32296f2e892SBill Paul DEVMETHOD(miibus_statchg, dc_miibus_statchg), 323f43d9309SBill Paul DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 32496f2e892SBill Paul 32596f2e892SBill Paul { 0, 0 } 32696f2e892SBill Paul }; 32796f2e892SBill Paul 32896f2e892SBill Paul static driver_t dc_driver = { 32996f2e892SBill Paul "dc", 33096f2e892SBill Paul dc_methods, 33196f2e892SBill Paul sizeof(struct dc_softc) 33296f2e892SBill Paul }; 33396f2e892SBill Paul 33496f2e892SBill Paul static devclass_t dc_devclass; 33501faf54bSLuigi Rizzo #ifdef __i386__ 33601faf54bSLuigi Rizzo static int dc_quick = 1; 337b3811c95SMaxime Henrion SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW, &dc_quick, 0, 33805992bb5SRuslan Ermilov "do not m_devget() in dc driver"); 33901faf54bSLuigi Rizzo #endif 34096f2e892SBill Paul 341347934faSWarner Losh DRIVER_MODULE(dc, cardbus, dc_driver, dc_devclass, 0, 0); 342f246e4a1SMatthew N. Dodd DRIVER_MODULE(dc, pci, dc_driver, dc_devclass, 0, 0); 34396f2e892SBill Paul DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 34496f2e892SBill Paul 34596f2e892SBill Paul #define DC_SETBIT(sc, reg, x) \ 34696f2e892SBill Paul CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 34796f2e892SBill Paul 34896f2e892SBill Paul #define DC_CLRBIT(sc, reg, x) \ 34996f2e892SBill Paul CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 35096f2e892SBill Paul 35196f2e892SBill Paul #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 35296f2e892SBill Paul #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 35396f2e892SBill Paul 354b50c6312SJonathan Lemon #define IS_MPSAFE 0 355b50c6312SJonathan Lemon 356e3d2833aSAlfred Perlstein static void 3570934f18aSMaxime Henrion dc_delay(struct dc_softc *sc) 35896f2e892SBill Paul { 35996f2e892SBill Paul int idx; 36096f2e892SBill Paul 36196f2e892SBill Paul for (idx = (300 / 33) + 1; idx > 0; idx--) 36296f2e892SBill Paul CSR_READ_4(sc, DC_BUSCTL); 36396f2e892SBill Paul } 36496f2e892SBill Paul 3652c876e15SPoul-Henning Kamp static void 3660934f18aSMaxime Henrion dc_eeprom_width(struct dc_softc *sc) 3673097aa70SWarner Losh { 3683097aa70SWarner Losh int i; 3693097aa70SWarner Losh 3703097aa70SWarner Losh /* Force EEPROM to idle state. */ 3713097aa70SWarner Losh dc_eeprom_idle(sc); 3723097aa70SWarner Losh 3733097aa70SWarner Losh /* Enter EEPROM access mode. */ 3743097aa70SWarner Losh CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 3753097aa70SWarner Losh dc_delay(sc); 3763097aa70SWarner Losh DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 3773097aa70SWarner Losh dc_delay(sc); 3783097aa70SWarner Losh DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 3793097aa70SWarner Losh dc_delay(sc); 3803097aa70SWarner Losh DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 3813097aa70SWarner Losh dc_delay(sc); 3823097aa70SWarner Losh 3833097aa70SWarner Losh for (i = 3; i--;) { 3843097aa70SWarner Losh if (6 & (1 << i)) 3853097aa70SWarner Losh DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 3863097aa70SWarner Losh else 3873097aa70SWarner Losh DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 3883097aa70SWarner Losh dc_delay(sc); 3893097aa70SWarner Losh DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 3903097aa70SWarner Losh dc_delay(sc); 3913097aa70SWarner Losh DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 3923097aa70SWarner Losh dc_delay(sc); 3933097aa70SWarner Losh } 3943097aa70SWarner Losh 3953097aa70SWarner Losh for (i = 1; i <= 12; i++) { 3963097aa70SWarner Losh DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 3973097aa70SWarner Losh dc_delay(sc); 3983097aa70SWarner Losh if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { 3993097aa70SWarner Losh DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 4003097aa70SWarner Losh dc_delay(sc); 4013097aa70SWarner Losh break; 4023097aa70SWarner Losh } 4033097aa70SWarner Losh DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 4043097aa70SWarner Losh dc_delay(sc); 4053097aa70SWarner Losh } 4063097aa70SWarner Losh 4073097aa70SWarner Losh /* Turn off EEPROM access mode. */ 4083097aa70SWarner Losh dc_eeprom_idle(sc); 4093097aa70SWarner Losh 4103097aa70SWarner Losh if (i < 4 || i > 12) 4113097aa70SWarner Losh sc->dc_romwidth = 6; 4123097aa70SWarner Losh else 4133097aa70SWarner Losh sc->dc_romwidth = i; 4143097aa70SWarner Losh 4153097aa70SWarner Losh /* Enter EEPROM access mode. */ 4163097aa70SWarner Losh CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 4173097aa70SWarner Losh dc_delay(sc); 4183097aa70SWarner Losh DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 4193097aa70SWarner Losh dc_delay(sc); 4203097aa70SWarner Losh DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 4213097aa70SWarner Losh dc_delay(sc); 4223097aa70SWarner Losh DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 4233097aa70SWarner Losh dc_delay(sc); 4243097aa70SWarner Losh 4253097aa70SWarner Losh /* Turn off EEPROM access mode. */ 4263097aa70SWarner Losh dc_eeprom_idle(sc); 4273097aa70SWarner Losh } 4283097aa70SWarner Losh 429e3d2833aSAlfred Perlstein static void 4300934f18aSMaxime Henrion dc_eeprom_idle(struct dc_softc *sc) 43196f2e892SBill Paul { 4320934f18aSMaxime Henrion int i; 43396f2e892SBill Paul 43496f2e892SBill Paul CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 43596f2e892SBill Paul dc_delay(sc); 43696f2e892SBill Paul DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 43796f2e892SBill Paul dc_delay(sc); 43896f2e892SBill Paul DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 43996f2e892SBill Paul dc_delay(sc); 44096f2e892SBill Paul DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 44196f2e892SBill Paul dc_delay(sc); 44296f2e892SBill Paul 44396f2e892SBill Paul for (i = 0; i < 25; i++) { 44496f2e892SBill Paul DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 44596f2e892SBill Paul dc_delay(sc); 44696f2e892SBill Paul DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 44796f2e892SBill Paul dc_delay(sc); 44896f2e892SBill Paul } 44996f2e892SBill Paul 45096f2e892SBill Paul DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 45196f2e892SBill Paul dc_delay(sc); 45296f2e892SBill Paul DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 45396f2e892SBill Paul dc_delay(sc); 45496f2e892SBill Paul CSR_WRITE_4(sc, DC_SIO, 0x00000000); 45596f2e892SBill Paul } 45696f2e892SBill Paul 45796f2e892SBill Paul /* 45896f2e892SBill Paul * Send a read command and address to the EEPROM, check for ACK. 45996f2e892SBill Paul */ 460e3d2833aSAlfred Perlstein static void 4610934f18aSMaxime Henrion dc_eeprom_putbyte(struct dc_softc *sc, int addr) 46296f2e892SBill Paul { 4630934f18aSMaxime Henrion int d, i; 46496f2e892SBill Paul 4653097aa70SWarner Losh d = DC_EECMD_READ >> 6; 4663097aa70SWarner Losh for (i = 3; i--; ) { 4673097aa70SWarner Losh if (d & (1 << i)) 4683097aa70SWarner Losh DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 46996f2e892SBill Paul else 4703097aa70SWarner Losh DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 4713097aa70SWarner Losh dc_delay(sc); 4723097aa70SWarner Losh DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 4733097aa70SWarner Losh dc_delay(sc); 4743097aa70SWarner Losh DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 4753097aa70SWarner Losh dc_delay(sc); 4763097aa70SWarner Losh } 47796f2e892SBill Paul 47896f2e892SBill Paul /* 47996f2e892SBill Paul * Feed in each bit and strobe the clock. 48096f2e892SBill Paul */ 4813097aa70SWarner Losh for (i = sc->dc_romwidth; i--;) { 4823097aa70SWarner Losh if (addr & (1 << i)) { 48396f2e892SBill Paul SIO_SET(DC_SIO_EE_DATAIN); 48496f2e892SBill Paul } else { 48596f2e892SBill Paul SIO_CLR(DC_SIO_EE_DATAIN); 48696f2e892SBill Paul } 48796f2e892SBill Paul dc_delay(sc); 48896f2e892SBill Paul SIO_SET(DC_SIO_EE_CLK); 48996f2e892SBill Paul dc_delay(sc); 49096f2e892SBill Paul SIO_CLR(DC_SIO_EE_CLK); 49196f2e892SBill Paul dc_delay(sc); 49296f2e892SBill Paul } 49396f2e892SBill Paul } 49496f2e892SBill Paul 49596f2e892SBill Paul /* 49696f2e892SBill Paul * Read a word of data stored in the EEPROM at address 'addr.' 49796f2e892SBill Paul * The PNIC 82c168/82c169 has its own non-standard way to read 49896f2e892SBill Paul * the EEPROM. 49996f2e892SBill Paul */ 500e3d2833aSAlfred Perlstein static void 5010934f18aSMaxime Henrion dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, u_int16_t *dest) 50296f2e892SBill Paul { 5030934f18aSMaxime Henrion int i; 50496f2e892SBill Paul u_int32_t r; 50596f2e892SBill Paul 50696f2e892SBill Paul CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr); 50796f2e892SBill Paul 50896f2e892SBill Paul for (i = 0; i < DC_TIMEOUT; i++) { 50996f2e892SBill Paul DELAY(1); 51096f2e892SBill Paul r = CSR_READ_4(sc, DC_SIO); 51196f2e892SBill Paul if (!(r & DC_PN_SIOCTL_BUSY)) { 51296f2e892SBill Paul *dest = (u_int16_t)(r & 0xFFFF); 51396f2e892SBill Paul return; 51496f2e892SBill Paul } 51596f2e892SBill Paul } 51696f2e892SBill Paul } 51796f2e892SBill Paul 51896f2e892SBill Paul /* 51996f2e892SBill Paul * Read a word of data stored in the EEPROM at address 'addr.' 520feb78939SJonathan Chen * The Xircom X3201 has its own non-standard way to read 521feb78939SJonathan Chen * the EEPROM, too. 522feb78939SJonathan Chen */ 523e3d2833aSAlfred Perlstein static void 5240934f18aSMaxime Henrion dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, u_int16_t *dest) 525feb78939SJonathan Chen { 5260934f18aSMaxime Henrion 527feb78939SJonathan Chen SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 528feb78939SJonathan Chen 529feb78939SJonathan Chen addr *= 2; 530feb78939SJonathan Chen CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 531feb78939SJonathan Chen *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff; 532feb78939SJonathan Chen addr += 1; 533feb78939SJonathan Chen CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 534feb78939SJonathan Chen *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8; 535feb78939SJonathan Chen 536feb78939SJonathan Chen SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 537feb78939SJonathan Chen } 538feb78939SJonathan Chen 539feb78939SJonathan Chen /* 540feb78939SJonathan Chen * Read a word of data stored in the EEPROM at address 'addr.' 54196f2e892SBill Paul */ 542e3d2833aSAlfred Perlstein static void 5430934f18aSMaxime Henrion dc_eeprom_getword(struct dc_softc *sc, int addr, u_int16_t *dest) 54496f2e892SBill Paul { 5450934f18aSMaxime Henrion int i; 54696f2e892SBill Paul u_int16_t word = 0; 54796f2e892SBill Paul 54896f2e892SBill Paul /* Force EEPROM to idle state. */ 54996f2e892SBill Paul dc_eeprom_idle(sc); 55096f2e892SBill Paul 55196f2e892SBill Paul /* Enter EEPROM access mode. */ 55296f2e892SBill Paul CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 55396f2e892SBill Paul dc_delay(sc); 55496f2e892SBill Paul DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 55596f2e892SBill Paul dc_delay(sc); 55696f2e892SBill Paul DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 55796f2e892SBill Paul dc_delay(sc); 55896f2e892SBill Paul DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 55996f2e892SBill Paul dc_delay(sc); 56096f2e892SBill Paul 56196f2e892SBill Paul /* 56296f2e892SBill Paul * Send address of word we want to read. 56396f2e892SBill Paul */ 56496f2e892SBill Paul dc_eeprom_putbyte(sc, addr); 56596f2e892SBill Paul 56696f2e892SBill Paul /* 56796f2e892SBill Paul * Start reading bits from EEPROM. 56896f2e892SBill Paul */ 56996f2e892SBill Paul for (i = 0x8000; i; i >>= 1) { 57096f2e892SBill Paul SIO_SET(DC_SIO_EE_CLK); 57196f2e892SBill Paul dc_delay(sc); 57296f2e892SBill Paul if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 57396f2e892SBill Paul word |= i; 57496f2e892SBill Paul dc_delay(sc); 57596f2e892SBill Paul SIO_CLR(DC_SIO_EE_CLK); 57696f2e892SBill Paul dc_delay(sc); 57796f2e892SBill Paul } 57896f2e892SBill Paul 57996f2e892SBill Paul /* Turn off EEPROM access mode. */ 58096f2e892SBill Paul dc_eeprom_idle(sc); 58196f2e892SBill Paul 58296f2e892SBill Paul *dest = word; 58396f2e892SBill Paul } 58496f2e892SBill Paul 58596f2e892SBill Paul /* 58696f2e892SBill Paul * Read a sequence of words from the EEPROM. 58796f2e892SBill Paul */ 588e3d2833aSAlfred Perlstein static void 5890934f18aSMaxime Henrion dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int swap) 59096f2e892SBill Paul { 59196f2e892SBill Paul int i; 59296f2e892SBill Paul u_int16_t word = 0, *ptr; 59396f2e892SBill Paul 59496f2e892SBill Paul for (i = 0; i < cnt; i++) { 59596f2e892SBill Paul if (DC_IS_PNIC(sc)) 59696f2e892SBill Paul dc_eeprom_getword_pnic(sc, off + i, &word); 597feb78939SJonathan Chen else if (DC_IS_XIRCOM(sc)) 598feb78939SJonathan Chen dc_eeprom_getword_xircom(sc, off + i, &word); 59996f2e892SBill Paul else 60096f2e892SBill Paul dc_eeprom_getword(sc, off + i, &word); 60196f2e892SBill Paul ptr = (u_int16_t *)(dest + (i * 2)); 60296f2e892SBill Paul if (swap) 60396f2e892SBill Paul *ptr = ntohs(word); 60496f2e892SBill Paul else 60596f2e892SBill Paul *ptr = word; 60696f2e892SBill Paul } 60796f2e892SBill Paul } 60896f2e892SBill Paul 60996f2e892SBill Paul /* 61096f2e892SBill Paul * The following two routines are taken from the Macronix 98713 61196f2e892SBill Paul * Application Notes pp.19-21. 61296f2e892SBill Paul */ 61396f2e892SBill Paul /* 61496f2e892SBill Paul * Write a bit to the MII bus. 61596f2e892SBill Paul */ 616e3d2833aSAlfred Perlstein static void 6170934f18aSMaxime Henrion dc_mii_writebit(struct dc_softc *sc, int bit) 61896f2e892SBill Paul { 6190934f18aSMaxime Henrion 62096f2e892SBill Paul if (bit) 62196f2e892SBill Paul CSR_WRITE_4(sc, DC_SIO, 62296f2e892SBill Paul DC_SIO_ROMCTL_WRITE | DC_SIO_MII_DATAOUT); 62396f2e892SBill Paul else 62496f2e892SBill Paul CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 62596f2e892SBill Paul 62696f2e892SBill Paul DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 62796f2e892SBill Paul DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 62896f2e892SBill Paul } 62996f2e892SBill Paul 63096f2e892SBill Paul /* 63196f2e892SBill Paul * Read a bit from the MII bus. 63296f2e892SBill Paul */ 633e3d2833aSAlfred Perlstein static int 6340934f18aSMaxime Henrion dc_mii_readbit(struct dc_softc *sc) 63596f2e892SBill Paul { 6360934f18aSMaxime Henrion 63796f2e892SBill Paul CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ | DC_SIO_MII_DIR); 63896f2e892SBill Paul CSR_READ_4(sc, DC_SIO); 63996f2e892SBill Paul DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 64096f2e892SBill Paul DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 64196f2e892SBill Paul if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 64296f2e892SBill Paul return (1); 64396f2e892SBill Paul 64496f2e892SBill Paul return (0); 64596f2e892SBill Paul } 64696f2e892SBill Paul 64796f2e892SBill Paul /* 64896f2e892SBill Paul * Sync the PHYs by setting data bit and strobing the clock 32 times. 64996f2e892SBill Paul */ 650e3d2833aSAlfred Perlstein static void 6510934f18aSMaxime Henrion dc_mii_sync(struct dc_softc *sc) 65296f2e892SBill Paul { 6530934f18aSMaxime Henrion int i; 65496f2e892SBill Paul 65596f2e892SBill Paul CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 65696f2e892SBill Paul 65796f2e892SBill Paul for (i = 0; i < 32; i++) 65896f2e892SBill Paul dc_mii_writebit(sc, 1); 65996f2e892SBill Paul } 66096f2e892SBill Paul 66196f2e892SBill Paul /* 66296f2e892SBill Paul * Clock a series of bits through the MII. 66396f2e892SBill Paul */ 664e3d2833aSAlfred Perlstein static void 6650934f18aSMaxime Henrion dc_mii_send(struct dc_softc *sc, u_int32_t bits, int cnt) 66696f2e892SBill Paul { 66796f2e892SBill Paul int i; 66896f2e892SBill Paul 66996f2e892SBill Paul for (i = (0x1 << (cnt - 1)); i; i >>= 1) 67096f2e892SBill Paul dc_mii_writebit(sc, bits & i); 67196f2e892SBill Paul } 67296f2e892SBill Paul 67396f2e892SBill Paul /* 67496f2e892SBill Paul * Read an PHY register through the MII. 67596f2e892SBill Paul */ 676e3d2833aSAlfred Perlstein static int 6770934f18aSMaxime Henrion dc_mii_readreg(struct dc_softc *sc, struct dc_mii_frame *frame) 67896f2e892SBill Paul { 679d1ce9105SBill Paul int i, ack; 68096f2e892SBill Paul 681d1ce9105SBill Paul DC_LOCK(sc); 68296f2e892SBill Paul 68396f2e892SBill Paul /* 68496f2e892SBill Paul * Set up frame for RX. 68596f2e892SBill Paul */ 68696f2e892SBill Paul frame->mii_stdelim = DC_MII_STARTDELIM; 68796f2e892SBill Paul frame->mii_opcode = DC_MII_READOP; 68896f2e892SBill Paul frame->mii_turnaround = 0; 68996f2e892SBill Paul frame->mii_data = 0; 69096f2e892SBill Paul 69196f2e892SBill Paul /* 69296f2e892SBill Paul * Sync the PHYs. 69396f2e892SBill Paul */ 69496f2e892SBill Paul dc_mii_sync(sc); 69596f2e892SBill Paul 69696f2e892SBill Paul /* 69796f2e892SBill Paul * Send command/address info. 69896f2e892SBill Paul */ 69996f2e892SBill Paul dc_mii_send(sc, frame->mii_stdelim, 2); 70096f2e892SBill Paul dc_mii_send(sc, frame->mii_opcode, 2); 70196f2e892SBill Paul dc_mii_send(sc, frame->mii_phyaddr, 5); 70296f2e892SBill Paul dc_mii_send(sc, frame->mii_regaddr, 5); 70396f2e892SBill Paul 70496f2e892SBill Paul #ifdef notdef 70596f2e892SBill Paul /* Idle bit */ 70696f2e892SBill Paul dc_mii_writebit(sc, 1); 70796f2e892SBill Paul dc_mii_writebit(sc, 0); 70896f2e892SBill Paul #endif 70996f2e892SBill Paul 7100934f18aSMaxime Henrion /* Check for ack. */ 71196f2e892SBill Paul ack = dc_mii_readbit(sc); 71296f2e892SBill Paul 71396f2e892SBill Paul /* 71496f2e892SBill Paul * Now try reading data bits. If the ack failed, we still 71596f2e892SBill Paul * need to clock through 16 cycles to keep the PHY(s) in sync. 71696f2e892SBill Paul */ 71796f2e892SBill Paul if (ack) { 7180934f18aSMaxime Henrion for (i = 0; i < 16; i++) 71996f2e892SBill Paul dc_mii_readbit(sc); 72096f2e892SBill Paul goto fail; 72196f2e892SBill Paul } 72296f2e892SBill Paul 72396f2e892SBill Paul for (i = 0x8000; i; i >>= 1) { 72496f2e892SBill Paul if (!ack) { 72596f2e892SBill Paul if (dc_mii_readbit(sc)) 72696f2e892SBill Paul frame->mii_data |= i; 72796f2e892SBill Paul } 72896f2e892SBill Paul } 72996f2e892SBill Paul 73096f2e892SBill Paul fail: 73196f2e892SBill Paul 73296f2e892SBill Paul dc_mii_writebit(sc, 0); 73396f2e892SBill Paul dc_mii_writebit(sc, 0); 73496f2e892SBill Paul 735d1ce9105SBill Paul DC_UNLOCK(sc); 73696f2e892SBill Paul 73796f2e892SBill Paul if (ack) 73896f2e892SBill Paul return (1); 73996f2e892SBill Paul return (0); 74096f2e892SBill Paul } 74196f2e892SBill Paul 74296f2e892SBill Paul /* 74396f2e892SBill Paul * Write to a PHY register through the MII. 74496f2e892SBill Paul */ 745e3d2833aSAlfred Perlstein static int 7460934f18aSMaxime Henrion dc_mii_writereg(struct dc_softc *sc, struct dc_mii_frame *frame) 74796f2e892SBill Paul { 7480934f18aSMaxime Henrion 749d1ce9105SBill Paul DC_LOCK(sc); 75096f2e892SBill Paul /* 75196f2e892SBill Paul * Set up frame for TX. 75296f2e892SBill Paul */ 75396f2e892SBill Paul 75496f2e892SBill Paul frame->mii_stdelim = DC_MII_STARTDELIM; 75596f2e892SBill Paul frame->mii_opcode = DC_MII_WRITEOP; 75696f2e892SBill Paul frame->mii_turnaround = DC_MII_TURNAROUND; 75796f2e892SBill Paul 75896f2e892SBill Paul /* 75996f2e892SBill Paul * Sync the PHYs. 76096f2e892SBill Paul */ 76196f2e892SBill Paul dc_mii_sync(sc); 76296f2e892SBill Paul 76396f2e892SBill Paul dc_mii_send(sc, frame->mii_stdelim, 2); 76496f2e892SBill Paul dc_mii_send(sc, frame->mii_opcode, 2); 76596f2e892SBill Paul dc_mii_send(sc, frame->mii_phyaddr, 5); 76696f2e892SBill Paul dc_mii_send(sc, frame->mii_regaddr, 5); 76796f2e892SBill Paul dc_mii_send(sc, frame->mii_turnaround, 2); 76896f2e892SBill Paul dc_mii_send(sc, frame->mii_data, 16); 76996f2e892SBill Paul 77096f2e892SBill Paul /* Idle bit. */ 77196f2e892SBill Paul dc_mii_writebit(sc, 0); 77296f2e892SBill Paul dc_mii_writebit(sc, 0); 77396f2e892SBill Paul 774d1ce9105SBill Paul DC_UNLOCK(sc); 77596f2e892SBill Paul 77696f2e892SBill Paul return (0); 77796f2e892SBill Paul } 77896f2e892SBill Paul 779e3d2833aSAlfred Perlstein static int 7800934f18aSMaxime Henrion dc_miibus_readreg(device_t dev, int phy, int reg) 78196f2e892SBill Paul { 78296f2e892SBill Paul struct dc_mii_frame frame; 78396f2e892SBill Paul struct dc_softc *sc; 784c85c4667SBill Paul int i, rval, phy_reg = 0; 78596f2e892SBill Paul 78696f2e892SBill Paul sc = device_get_softc(dev); 7870934f18aSMaxime Henrion bzero(&frame, sizeof(frame)); 78896f2e892SBill Paul 78996f2e892SBill Paul /* 79096f2e892SBill Paul * Note: both the AL981 and AN985 have internal PHYs, 79196f2e892SBill Paul * however the AL981 provides direct access to the PHY 79296f2e892SBill Paul * registers while the AN985 uses a serial MII interface. 79396f2e892SBill Paul * The AN985's MII interface is also buggy in that you 79496f2e892SBill Paul * can read from any MII address (0 to 31), but only address 1 79596f2e892SBill Paul * behaves normally. To deal with both cases, we pretend 79696f2e892SBill Paul * that the PHY is at MII address 1. 79796f2e892SBill Paul */ 79896f2e892SBill Paul if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 79996f2e892SBill Paul return (0); 80096f2e892SBill Paul 8011af8bec7SBill Paul /* 8021af8bec7SBill Paul * Note: the ukphy probes of the RS7112 report a PHY at 8031af8bec7SBill Paul * MII address 0 (possibly HomePNA?) and 1 (ethernet) 8041af8bec7SBill Paul * so we only respond to correct one. 8051af8bec7SBill Paul */ 8061af8bec7SBill Paul if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 8071af8bec7SBill Paul return (0); 8081af8bec7SBill Paul 8095c1cfac4SBill Paul if (sc->dc_pmode != DC_PMODE_MII) { 81096f2e892SBill Paul if (phy == (MII_NPHY - 1)) { 81196f2e892SBill Paul switch (reg) { 81296f2e892SBill Paul case MII_BMSR: 81396f2e892SBill Paul /* 81496f2e892SBill Paul * Fake something to make the probe 81596f2e892SBill Paul * code think there's a PHY here. 81696f2e892SBill Paul */ 81796f2e892SBill Paul return (BMSR_MEDIAMASK); 81896f2e892SBill Paul break; 81996f2e892SBill Paul case MII_PHYIDR1: 82096f2e892SBill Paul if (DC_IS_PNIC(sc)) 82196f2e892SBill Paul return (DC_VENDORID_LO); 82296f2e892SBill Paul return (DC_VENDORID_DEC); 82396f2e892SBill Paul break; 82496f2e892SBill Paul case MII_PHYIDR2: 82596f2e892SBill Paul if (DC_IS_PNIC(sc)) 82696f2e892SBill Paul return (DC_DEVICEID_82C168); 82796f2e892SBill Paul return (DC_DEVICEID_21143); 82896f2e892SBill Paul break; 82996f2e892SBill Paul default: 83096f2e892SBill Paul return (0); 83196f2e892SBill Paul break; 83296f2e892SBill Paul } 83396f2e892SBill Paul } else 83496f2e892SBill Paul return (0); 83596f2e892SBill Paul } 83696f2e892SBill Paul 83796f2e892SBill Paul if (DC_IS_PNIC(sc)) { 83896f2e892SBill Paul CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 83996f2e892SBill Paul (phy << 23) | (reg << 18)); 84096f2e892SBill Paul for (i = 0; i < DC_TIMEOUT; i++) { 84196f2e892SBill Paul DELAY(1); 84296f2e892SBill Paul rval = CSR_READ_4(sc, DC_PN_MII); 84396f2e892SBill Paul if (!(rval & DC_PN_MII_BUSY)) { 84496f2e892SBill Paul rval &= 0xFFFF; 84596f2e892SBill Paul return (rval == 0xFFFF ? 0 : rval); 84696f2e892SBill Paul } 84796f2e892SBill Paul } 84896f2e892SBill Paul return (0); 84996f2e892SBill Paul } 85096f2e892SBill Paul 85196f2e892SBill Paul if (DC_IS_COMET(sc)) { 85296f2e892SBill Paul switch (reg) { 85396f2e892SBill Paul case MII_BMCR: 85496f2e892SBill Paul phy_reg = DC_AL_BMCR; 85596f2e892SBill Paul break; 85696f2e892SBill Paul case MII_BMSR: 85796f2e892SBill Paul phy_reg = DC_AL_BMSR; 85896f2e892SBill Paul break; 85996f2e892SBill Paul case MII_PHYIDR1: 86096f2e892SBill Paul phy_reg = DC_AL_VENID; 86196f2e892SBill Paul break; 86296f2e892SBill Paul case MII_PHYIDR2: 86396f2e892SBill Paul phy_reg = DC_AL_DEVID; 86496f2e892SBill Paul break; 86596f2e892SBill Paul case MII_ANAR: 86696f2e892SBill Paul phy_reg = DC_AL_ANAR; 86796f2e892SBill Paul break; 86896f2e892SBill Paul case MII_ANLPAR: 86996f2e892SBill Paul phy_reg = DC_AL_LPAR; 87096f2e892SBill Paul break; 87196f2e892SBill Paul case MII_ANER: 87296f2e892SBill Paul phy_reg = DC_AL_ANER; 87396f2e892SBill Paul break; 87496f2e892SBill Paul default: 87596f2e892SBill Paul printf("dc%d: phy_read: bad phy register %x\n", 87696f2e892SBill Paul sc->dc_unit, reg); 87796f2e892SBill Paul return (0); 87896f2e892SBill Paul break; 87996f2e892SBill Paul } 88096f2e892SBill Paul 88196f2e892SBill Paul rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 88296f2e892SBill Paul 88396f2e892SBill Paul if (rval == 0xFFFF) 88496f2e892SBill Paul return (0); 88596f2e892SBill Paul return (rval); 88696f2e892SBill Paul } 88796f2e892SBill Paul 88896f2e892SBill Paul frame.mii_phyaddr = phy; 88996f2e892SBill Paul frame.mii_regaddr = reg; 890419146d9SBill Paul if (sc->dc_type == DC_TYPE_98713) { 891f43d9309SBill Paul phy_reg = CSR_READ_4(sc, DC_NETCFG); 892f43d9309SBill Paul CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 893419146d9SBill Paul } 89496f2e892SBill Paul dc_mii_readreg(sc, &frame); 895419146d9SBill Paul if (sc->dc_type == DC_TYPE_98713) 896f43d9309SBill Paul CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 89796f2e892SBill Paul 89896f2e892SBill Paul return (frame.mii_data); 89996f2e892SBill Paul } 90096f2e892SBill Paul 901e3d2833aSAlfred Perlstein static int 9020934f18aSMaxime Henrion dc_miibus_writereg(device_t dev, int phy, int reg, int data) 90396f2e892SBill Paul { 90496f2e892SBill Paul struct dc_softc *sc; 90596f2e892SBill Paul struct dc_mii_frame frame; 906c85c4667SBill Paul int i, phy_reg = 0; 90796f2e892SBill Paul 90896f2e892SBill Paul sc = device_get_softc(dev); 9090934f18aSMaxime Henrion bzero(&frame, sizeof(frame)); 91096f2e892SBill Paul 91196f2e892SBill Paul if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 91296f2e892SBill Paul return (0); 91396f2e892SBill Paul 9141af8bec7SBill Paul if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 9151af8bec7SBill Paul return (0); 9161af8bec7SBill Paul 91796f2e892SBill Paul if (DC_IS_PNIC(sc)) { 91896f2e892SBill Paul CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 91996f2e892SBill Paul (phy << 23) | (reg << 10) | data); 92096f2e892SBill Paul for (i = 0; i < DC_TIMEOUT; i++) { 92196f2e892SBill Paul if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 92296f2e892SBill Paul break; 92396f2e892SBill Paul } 92496f2e892SBill Paul return (0); 92596f2e892SBill Paul } 92696f2e892SBill Paul 92796f2e892SBill Paul if (DC_IS_COMET(sc)) { 92896f2e892SBill Paul switch (reg) { 92996f2e892SBill Paul case MII_BMCR: 93096f2e892SBill Paul phy_reg = DC_AL_BMCR; 93196f2e892SBill Paul break; 93296f2e892SBill Paul case MII_BMSR: 93396f2e892SBill Paul phy_reg = DC_AL_BMSR; 93496f2e892SBill Paul break; 93596f2e892SBill Paul case MII_PHYIDR1: 93696f2e892SBill Paul phy_reg = DC_AL_VENID; 93796f2e892SBill Paul break; 93896f2e892SBill Paul case MII_PHYIDR2: 93996f2e892SBill Paul phy_reg = DC_AL_DEVID; 94096f2e892SBill Paul break; 94196f2e892SBill Paul case MII_ANAR: 94296f2e892SBill Paul phy_reg = DC_AL_ANAR; 94396f2e892SBill Paul break; 94496f2e892SBill Paul case MII_ANLPAR: 94596f2e892SBill Paul phy_reg = DC_AL_LPAR; 94696f2e892SBill Paul break; 94796f2e892SBill Paul case MII_ANER: 94896f2e892SBill Paul phy_reg = DC_AL_ANER; 94996f2e892SBill Paul break; 95096f2e892SBill Paul default: 95196f2e892SBill Paul printf("dc%d: phy_write: bad phy register %x\n", 95296f2e892SBill Paul sc->dc_unit, reg); 95396f2e892SBill Paul return (0); 95496f2e892SBill Paul break; 95596f2e892SBill Paul } 95696f2e892SBill Paul 95796f2e892SBill Paul CSR_WRITE_4(sc, phy_reg, data); 95896f2e892SBill Paul return (0); 95996f2e892SBill Paul } 96096f2e892SBill Paul 96196f2e892SBill Paul frame.mii_phyaddr = phy; 96296f2e892SBill Paul frame.mii_regaddr = reg; 96396f2e892SBill Paul frame.mii_data = data; 96496f2e892SBill Paul 965419146d9SBill Paul if (sc->dc_type == DC_TYPE_98713) { 966f43d9309SBill Paul phy_reg = CSR_READ_4(sc, DC_NETCFG); 967f43d9309SBill Paul CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 968419146d9SBill Paul } 96996f2e892SBill Paul dc_mii_writereg(sc, &frame); 970419146d9SBill Paul if (sc->dc_type == DC_TYPE_98713) 971f43d9309SBill Paul CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 97296f2e892SBill Paul 97396f2e892SBill Paul return (0); 97496f2e892SBill Paul } 97596f2e892SBill Paul 976e3d2833aSAlfred Perlstein static void 9770934f18aSMaxime Henrion dc_miibus_statchg(device_t dev) 97896f2e892SBill Paul { 97996f2e892SBill Paul struct dc_softc *sc; 98096f2e892SBill Paul struct mii_data *mii; 981f43d9309SBill Paul struct ifmedia *ifm; 98296f2e892SBill Paul 98396f2e892SBill Paul sc = device_get_softc(dev); 98496f2e892SBill Paul if (DC_IS_ADMTEK(sc)) 98596f2e892SBill Paul return; 9865c1cfac4SBill Paul 98796f2e892SBill Paul mii = device_get_softc(sc->dc_miibus); 988f43d9309SBill Paul ifm = &mii->mii_media; 989f43d9309SBill Paul if (DC_IS_DAVICOM(sc) && 99045521525SPoul-Henning Kamp IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 991f43d9309SBill Paul dc_setcfg(sc, ifm->ifm_media); 992f43d9309SBill Paul sc->dc_if_media = ifm->ifm_media; 993f43d9309SBill Paul } else { 99496f2e892SBill Paul dc_setcfg(sc, mii->mii_media_active); 99596f2e892SBill Paul sc->dc_if_media = mii->mii_media_active; 996f43d9309SBill Paul } 997f43d9309SBill Paul } 998f43d9309SBill Paul 999f43d9309SBill Paul /* 1000f43d9309SBill Paul * Special support for DM9102A cards with HomePNA PHYs. Note: 1001f43d9309SBill Paul * with the Davicom DM9102A/DM9801 eval board that I have, it seems 1002f43d9309SBill Paul * to be impossible to talk to the management interface of the DM9801 1003f43d9309SBill Paul * PHY (its MDIO pin is not connected to anything). Consequently, 1004f43d9309SBill Paul * the driver has to just 'know' about the additional mode and deal 1005f43d9309SBill Paul * with it itself. *sigh* 1006f43d9309SBill Paul */ 1007e3d2833aSAlfred Perlstein static void 10080934f18aSMaxime Henrion dc_miibus_mediainit(device_t dev) 1009f43d9309SBill Paul { 1010f43d9309SBill Paul struct dc_softc *sc; 1011f43d9309SBill Paul struct mii_data *mii; 1012f43d9309SBill Paul struct ifmedia *ifm; 1013f43d9309SBill Paul int rev; 1014f43d9309SBill Paul 1015f43d9309SBill Paul rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1016f43d9309SBill Paul 1017f43d9309SBill Paul sc = device_get_softc(dev); 1018f43d9309SBill Paul mii = device_get_softc(sc->dc_miibus); 1019f43d9309SBill Paul ifm = &mii->mii_media; 1020f43d9309SBill Paul 1021f43d9309SBill Paul if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 102245521525SPoul-Henning Kamp ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL); 102396f2e892SBill Paul } 102496f2e892SBill Paul 102596f2e892SBill Paul #define DC_POLY 0xEDB88320 102679d11e09SBill Paul #define DC_BITS_512 9 102779d11e09SBill Paul #define DC_BITS_128 7 102879d11e09SBill Paul #define DC_BITS_64 6 102996f2e892SBill Paul 10303373489bSWarner Losh static uint32_t 10313373489bSWarner Losh dc_mchash_le(struct dc_softc *sc, const uint8_t *addr) 103296f2e892SBill Paul { 10333373489bSWarner Losh uint32_t crc; 1034aa825502SDavid E. O'Brien int idx, bit; 10353373489bSWarner Losh uint8_t data; 103696f2e892SBill Paul 103796f2e892SBill Paul /* Compute CRC for the address value. */ 103896f2e892SBill Paul crc = 0xFFFFFFFF; /* initial value */ 103996f2e892SBill Paul 104096f2e892SBill Paul for (idx = 0; idx < 6; idx++) { 104196f2e892SBill Paul for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 104296f2e892SBill Paul crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 104396f2e892SBill Paul } 104496f2e892SBill Paul 104579d11e09SBill Paul /* 104679d11e09SBill Paul * The hash table on the PNIC II and the MX98715AEC-C/D/E 104779d11e09SBill Paul * chips is only 128 bits wide. 104879d11e09SBill Paul */ 104979d11e09SBill Paul if (sc->dc_flags & DC_128BIT_HASH) 105079d11e09SBill Paul return (crc & ((1 << DC_BITS_128) - 1)); 105196f2e892SBill Paul 105279d11e09SBill Paul /* The hash table on the MX98715BEC is only 64 bits wide. */ 105379d11e09SBill Paul if (sc->dc_flags & DC_64BIT_HASH) 105479d11e09SBill Paul return (crc & ((1 << DC_BITS_64) - 1)); 105579d11e09SBill Paul 1056feb78939SJonathan Chen /* Xircom's hash filtering table is different (read: weird) */ 1057feb78939SJonathan Chen /* Xircom uses the LEAST significant bits */ 1058feb78939SJonathan Chen if (DC_IS_XIRCOM(sc)) { 1059feb78939SJonathan Chen if ((crc & 0x180) == 0x180) 10600934f18aSMaxime Henrion return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4)); 1061feb78939SJonathan Chen else 10620934f18aSMaxime Henrion return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 + 10630934f18aSMaxime Henrion (12 << 4)); 1064feb78939SJonathan Chen } 1065feb78939SJonathan Chen 106679d11e09SBill Paul return (crc & ((1 << DC_BITS_512) - 1)); 106796f2e892SBill Paul } 106896f2e892SBill Paul 106996f2e892SBill Paul /* 107096f2e892SBill Paul * Calculate CRC of a multicast group address, return the lower 6 bits. 107196f2e892SBill Paul */ 10723373489bSWarner Losh static uint32_t 10733373489bSWarner Losh dc_mchash_be(const uint8_t *addr) 107496f2e892SBill Paul { 10753373489bSWarner Losh uint32_t crc, carry; 1076aa825502SDavid E. O'Brien int idx, bit; 10773373489bSWarner Losh uint8_t data; 107896f2e892SBill Paul 107996f2e892SBill Paul /* Compute CRC for the address value. */ 108096f2e892SBill Paul crc = 0xFFFFFFFF; /* initial value */ 108196f2e892SBill Paul 1082aa825502SDavid E. O'Brien for (idx = 0; idx < 6; idx++) { 1083aa825502SDavid E. O'Brien for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) { 1084aa825502SDavid E. O'Brien carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01); 1085aa825502SDavid E. O'Brien data >>= 1; 108696f2e892SBill Paul crc <<= 1; 108796f2e892SBill Paul if (carry) 108896f2e892SBill Paul crc = (crc ^ 0x04c11db6) | carry; 108996f2e892SBill Paul } 109096f2e892SBill Paul } 109196f2e892SBill Paul 10920934f18aSMaxime Henrion /* Return the filter bit position. */ 109396f2e892SBill Paul return ((crc >> 26) & 0x0000003F); 109496f2e892SBill Paul } 109596f2e892SBill Paul 109696f2e892SBill Paul /* 109796f2e892SBill Paul * 21143-style RX filter setup routine. Filter programming is done by 109896f2e892SBill Paul * downloading a special setup frame into the TX engine. 21143, Macronix, 109996f2e892SBill Paul * PNIC, PNIC II and Davicom chips are programmed this way. 110096f2e892SBill Paul * 110196f2e892SBill Paul * We always program the chip using 'hash perfect' mode, i.e. one perfect 110296f2e892SBill Paul * address (our node address) and a 512-bit hash filter for multicast 110396f2e892SBill Paul * frames. We also sneak the broadcast address into the hash filter since 110496f2e892SBill Paul * we need that too. 110596f2e892SBill Paul */ 11062c876e15SPoul-Henning Kamp static void 11070934f18aSMaxime Henrion dc_setfilt_21143(struct dc_softc *sc) 110896f2e892SBill Paul { 110996f2e892SBill Paul struct dc_desc *sframe; 111096f2e892SBill Paul u_int32_t h, *sp; 111196f2e892SBill Paul struct ifmultiaddr *ifma; 111296f2e892SBill Paul struct ifnet *ifp; 111396f2e892SBill Paul int i; 111496f2e892SBill Paul 111596f2e892SBill Paul ifp = &sc->arpcom.ac_if; 111696f2e892SBill Paul 111796f2e892SBill Paul i = sc->dc_cdata.dc_tx_prod; 111896f2e892SBill Paul DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 111996f2e892SBill Paul sc->dc_cdata.dc_tx_cnt++; 112096f2e892SBill Paul sframe = &sc->dc_ldata->dc_tx_list[i]; 112156e5e7aeSMaxime Henrion sp = sc->dc_cdata.dc_sbuf; 11220934f18aSMaxime Henrion bzero(sp, DC_SFRAME_LEN); 112396f2e892SBill Paul 1124af4358c7SMaxime Henrion sframe->dc_data = htole32(sc->dc_saddr); 1125af4358c7SMaxime Henrion sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1126af4358c7SMaxime Henrion DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 112796f2e892SBill Paul 112856e5e7aeSMaxime Henrion sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 112996f2e892SBill Paul 113096f2e892SBill Paul /* If we want promiscuous mode, set the allframes bit. */ 113196f2e892SBill Paul if (ifp->if_flags & IFF_PROMISC) 113296f2e892SBill Paul DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 113396f2e892SBill Paul else 113496f2e892SBill Paul DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 113596f2e892SBill Paul 113696f2e892SBill Paul if (ifp->if_flags & IFF_ALLMULTI) 113796f2e892SBill Paul DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 113896f2e892SBill Paul else 113996f2e892SBill Paul DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 114096f2e892SBill Paul 11416817526dSPoul-Henning Kamp TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 114296f2e892SBill Paul if (ifma->ifma_addr->sa_family != AF_LINK) 114396f2e892SBill Paul continue; 1144aa825502SDavid E. O'Brien h = dc_mchash_le(sc, 114596f2e892SBill Paul LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1146af4358c7SMaxime Henrion sp[h >> 4] |= htole32(1 << (h & 0xF)); 114796f2e892SBill Paul } 114896f2e892SBill Paul 114996f2e892SBill Paul if (ifp->if_flags & IFF_BROADCAST) { 1150aa825502SDavid E. O'Brien h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1151af4358c7SMaxime Henrion sp[h >> 4] |= htole32(1 << (h & 0xF)); 115296f2e892SBill Paul } 115396f2e892SBill Paul 115496f2e892SBill Paul /* Set our MAC address */ 1155af4358c7SMaxime Henrion sp[39] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1156af4358c7SMaxime Henrion sp[40] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1157af4358c7SMaxime Henrion sp[41] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 115896f2e892SBill Paul 1159af4358c7SMaxime Henrion sframe->dc_status = htole32(DC_TXSTAT_OWN); 116096f2e892SBill Paul CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 116196f2e892SBill Paul 116296f2e892SBill Paul /* 116396f2e892SBill Paul * The PNIC takes an exceedingly long time to process its 116496f2e892SBill Paul * setup frame; wait 10ms after posting the setup frame 116596f2e892SBill Paul * before proceeding, just so it has time to swallow its 116696f2e892SBill Paul * medicine. 116796f2e892SBill Paul */ 116896f2e892SBill Paul DELAY(10000); 116996f2e892SBill Paul 117096f2e892SBill Paul ifp->if_timer = 5; 117196f2e892SBill Paul } 117296f2e892SBill Paul 11732c876e15SPoul-Henning Kamp static void 11740934f18aSMaxime Henrion dc_setfilt_admtek(struct dc_softc *sc) 117596f2e892SBill Paul { 117696f2e892SBill Paul struct ifnet *ifp; 11770934f18aSMaxime Henrion struct ifmultiaddr *ifma; 117896f2e892SBill Paul int h = 0; 117996f2e892SBill Paul u_int32_t hashes[2] = { 0, 0 }; 118096f2e892SBill Paul 118196f2e892SBill Paul ifp = &sc->arpcom.ac_if; 118296f2e892SBill Paul 11830934f18aSMaxime Henrion /* Init our MAC address. */ 118496f2e892SBill Paul CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 118596f2e892SBill Paul CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 118696f2e892SBill Paul 118796f2e892SBill Paul /* If we want promiscuous mode, set the allframes bit. */ 118896f2e892SBill Paul if (ifp->if_flags & IFF_PROMISC) 118996f2e892SBill Paul DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 119096f2e892SBill Paul else 119196f2e892SBill Paul DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 119296f2e892SBill Paul 119396f2e892SBill Paul if (ifp->if_flags & IFF_ALLMULTI) 119496f2e892SBill Paul DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 119596f2e892SBill Paul else 119696f2e892SBill Paul DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 119796f2e892SBill Paul 11980934f18aSMaxime Henrion /* First, zot all the existing hash bits. */ 119996f2e892SBill Paul CSR_WRITE_4(sc, DC_AL_MAR0, 0); 120096f2e892SBill Paul CSR_WRITE_4(sc, DC_AL_MAR1, 0); 120196f2e892SBill Paul 120296f2e892SBill Paul /* 120396f2e892SBill Paul * If we're already in promisc or allmulti mode, we 120496f2e892SBill Paul * don't have to bother programming the multicast filter. 120596f2e892SBill Paul */ 120696f2e892SBill Paul if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 120796f2e892SBill Paul return; 120896f2e892SBill Paul 12090934f18aSMaxime Henrion /* Now program new ones. */ 12106817526dSPoul-Henning Kamp TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 121196f2e892SBill Paul if (ifma->ifma_addr->sa_family != AF_LINK) 121296f2e892SBill Paul continue; 1213acc1bcccSMartin Blapp if (DC_IS_CENTAUR(sc)) 1214aa825502SDavid E. O'Brien h = dc_mchash_le(sc, 1215aa825502SDavid E. O'Brien LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1216acc1bcccSMartin Blapp else 1217aa825502SDavid E. O'Brien h = dc_mchash_be( 1218aa825502SDavid E. O'Brien LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 121996f2e892SBill Paul if (h < 32) 122096f2e892SBill Paul hashes[0] |= (1 << h); 122196f2e892SBill Paul else 122296f2e892SBill Paul hashes[1] |= (1 << (h - 32)); 122396f2e892SBill Paul } 122496f2e892SBill Paul 122596f2e892SBill Paul CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 122696f2e892SBill Paul CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 122796f2e892SBill Paul } 122896f2e892SBill Paul 12292c876e15SPoul-Henning Kamp static void 12300934f18aSMaxime Henrion dc_setfilt_asix(struct dc_softc *sc) 123196f2e892SBill Paul { 123296f2e892SBill Paul struct ifnet *ifp; 12330934f18aSMaxime Henrion struct ifmultiaddr *ifma; 123496f2e892SBill Paul int h = 0; 123596f2e892SBill Paul u_int32_t hashes[2] = { 0, 0 }; 123696f2e892SBill Paul 123796f2e892SBill Paul ifp = &sc->arpcom.ac_if; 123896f2e892SBill Paul 123996f2e892SBill Paul /* Init our MAC address */ 124096f2e892SBill Paul CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 124196f2e892SBill Paul CSR_WRITE_4(sc, DC_AX_FILTDATA, 124296f2e892SBill Paul *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 124396f2e892SBill Paul CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 124496f2e892SBill Paul CSR_WRITE_4(sc, DC_AX_FILTDATA, 124596f2e892SBill Paul *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 124696f2e892SBill Paul 124796f2e892SBill Paul /* If we want promiscuous mode, set the allframes bit. */ 124896f2e892SBill Paul if (ifp->if_flags & IFF_PROMISC) 124996f2e892SBill Paul DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 125096f2e892SBill Paul else 125196f2e892SBill Paul DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 125296f2e892SBill Paul 125396f2e892SBill Paul if (ifp->if_flags & IFF_ALLMULTI) 125496f2e892SBill Paul DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 125596f2e892SBill Paul else 125696f2e892SBill Paul DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 125796f2e892SBill Paul 125896f2e892SBill Paul /* 125996f2e892SBill Paul * The ASIX chip has a special bit to enable reception 126096f2e892SBill Paul * of broadcast frames. 126196f2e892SBill Paul */ 126296f2e892SBill Paul if (ifp->if_flags & IFF_BROADCAST) 126396f2e892SBill Paul DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 126496f2e892SBill Paul else 126596f2e892SBill Paul DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 126696f2e892SBill Paul 126796f2e892SBill Paul /* first, zot all the existing hash bits */ 126896f2e892SBill Paul CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 126996f2e892SBill Paul CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 127096f2e892SBill Paul CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 127196f2e892SBill Paul CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 127296f2e892SBill Paul 127396f2e892SBill Paul /* 127496f2e892SBill Paul * If we're already in promisc or allmulti mode, we 127596f2e892SBill Paul * don't have to bother programming the multicast filter. 127696f2e892SBill Paul */ 127796f2e892SBill Paul if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 127896f2e892SBill Paul return; 127996f2e892SBill Paul 128096f2e892SBill Paul /* now program new ones */ 12816817526dSPoul-Henning Kamp TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 128296f2e892SBill Paul if (ifma->ifma_addr->sa_family != AF_LINK) 128396f2e892SBill Paul continue; 1284aa825502SDavid E. O'Brien h = dc_mchash_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 128596f2e892SBill Paul if (h < 32) 128696f2e892SBill Paul hashes[0] |= (1 << h); 128796f2e892SBill Paul else 128896f2e892SBill Paul hashes[1] |= (1 << (h - 32)); 128996f2e892SBill Paul } 129096f2e892SBill Paul 129196f2e892SBill Paul CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 129296f2e892SBill Paul CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 129396f2e892SBill Paul CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 129496f2e892SBill Paul CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 129596f2e892SBill Paul } 129696f2e892SBill Paul 12972c876e15SPoul-Henning Kamp static void 12980934f18aSMaxime Henrion dc_setfilt_xircom(struct dc_softc *sc) 1299feb78939SJonathan Chen { 13000934f18aSMaxime Henrion struct ifnet *ifp; 13010934f18aSMaxime Henrion struct ifmultiaddr *ifma; 1302feb78939SJonathan Chen struct dc_desc *sframe; 1303feb78939SJonathan Chen u_int32_t h, *sp; 1304feb78939SJonathan Chen int i; 1305feb78939SJonathan Chen 1306feb78939SJonathan Chen ifp = &sc->arpcom.ac_if; 1307feb78939SJonathan Chen DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1308feb78939SJonathan Chen 1309feb78939SJonathan Chen i = sc->dc_cdata.dc_tx_prod; 1310feb78939SJonathan Chen DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1311feb78939SJonathan Chen sc->dc_cdata.dc_tx_cnt++; 1312feb78939SJonathan Chen sframe = &sc->dc_ldata->dc_tx_list[i]; 131356e5e7aeSMaxime Henrion sp = sc->dc_cdata.dc_sbuf; 13140934f18aSMaxime Henrion bzero(sp, DC_SFRAME_LEN); 1315feb78939SJonathan Chen 1316af4358c7SMaxime Henrion sframe->dc_data = htole32(sc->dc_saddr); 1317af4358c7SMaxime Henrion sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1318af4358c7SMaxime Henrion DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1319feb78939SJonathan Chen 132056e5e7aeSMaxime Henrion sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1321feb78939SJonathan Chen 1322feb78939SJonathan Chen /* If we want promiscuous mode, set the allframes bit. */ 1323feb78939SJonathan Chen if (ifp->if_flags & IFF_PROMISC) 1324feb78939SJonathan Chen DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1325feb78939SJonathan Chen else 1326feb78939SJonathan Chen DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1327feb78939SJonathan Chen 1328feb78939SJonathan Chen if (ifp->if_flags & IFF_ALLMULTI) 1329feb78939SJonathan Chen DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1330feb78939SJonathan Chen else 1331feb78939SJonathan Chen DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1332feb78939SJonathan Chen 13336817526dSPoul-Henning Kamp TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1334feb78939SJonathan Chen if (ifma->ifma_addr->sa_family != AF_LINK) 1335feb78939SJonathan Chen continue; 1336aa825502SDavid E. O'Brien h = dc_mchash_le(sc, 13371d5e5310SBill Paul LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1338af4358c7SMaxime Henrion sp[h >> 4] |= htole32(1 << (h & 0xF)); 1339feb78939SJonathan Chen } 1340feb78939SJonathan Chen 1341feb78939SJonathan Chen if (ifp->if_flags & IFF_BROADCAST) { 1342aa825502SDavid E. O'Brien h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1343af4358c7SMaxime Henrion sp[h >> 4] |= htole32(1 << (h & 0xF)); 1344feb78939SJonathan Chen } 1345feb78939SJonathan Chen 1346feb78939SJonathan Chen /* Set our MAC address */ 1347af4358c7SMaxime Henrion sp[0] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1348af4358c7SMaxime Henrion sp[1] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1349af4358c7SMaxime Henrion sp[2] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1350feb78939SJonathan Chen 1351feb78939SJonathan Chen DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1352feb78939SJonathan Chen DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1353feb78939SJonathan Chen ifp->if_flags |= IFF_RUNNING; 1354af4358c7SMaxime Henrion sframe->dc_status = htole32(DC_TXSTAT_OWN); 1355feb78939SJonathan Chen CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1356feb78939SJonathan Chen 1357feb78939SJonathan Chen /* 13580934f18aSMaxime Henrion * Wait some time... 1359feb78939SJonathan Chen */ 1360feb78939SJonathan Chen DELAY(1000); 1361feb78939SJonathan Chen 1362feb78939SJonathan Chen ifp->if_timer = 5; 1363feb78939SJonathan Chen } 1364feb78939SJonathan Chen 1365e3d2833aSAlfred Perlstein static void 13660934f18aSMaxime Henrion dc_setfilt(struct dc_softc *sc) 136796f2e892SBill Paul { 13680934f18aSMaxime Henrion 136996f2e892SBill Paul if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 13701af8bec7SBill Paul DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 137196f2e892SBill Paul dc_setfilt_21143(sc); 137296f2e892SBill Paul 137396f2e892SBill Paul if (DC_IS_ASIX(sc)) 137496f2e892SBill Paul dc_setfilt_asix(sc); 137596f2e892SBill Paul 137696f2e892SBill Paul if (DC_IS_ADMTEK(sc)) 137796f2e892SBill Paul dc_setfilt_admtek(sc); 137896f2e892SBill Paul 1379feb78939SJonathan Chen if (DC_IS_XIRCOM(sc)) 1380feb78939SJonathan Chen dc_setfilt_xircom(sc); 138196f2e892SBill Paul } 138296f2e892SBill Paul 138396f2e892SBill Paul /* 13840934f18aSMaxime Henrion * In order to fiddle with the 'full-duplex' and '100Mbps' bits in 13850934f18aSMaxime Henrion * the netconfig register, we first have to put the transmit and/or 13860934f18aSMaxime Henrion * receive logic in the idle state. 138796f2e892SBill Paul */ 1388e3d2833aSAlfred Perlstein static void 13890934f18aSMaxime Henrion dc_setcfg(struct dc_softc *sc, int media) 139096f2e892SBill Paul { 13910934f18aSMaxime Henrion int i, restart = 0, watchdogreg; 139296f2e892SBill Paul u_int32_t isr; 139396f2e892SBill Paul 139496f2e892SBill Paul if (IFM_SUBTYPE(media) == IFM_NONE) 139596f2e892SBill Paul return; 139696f2e892SBill Paul 139796f2e892SBill Paul if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) { 139896f2e892SBill Paul restart = 1; 139996f2e892SBill Paul DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 140096f2e892SBill Paul 140196f2e892SBill Paul for (i = 0; i < DC_TIMEOUT; i++) { 140296f2e892SBill Paul isr = CSR_READ_4(sc, DC_ISR); 1403d467c136SBill Paul if (isr & DC_ISR_TX_IDLE && 1404351267c1SMartin Blapp ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1405351267c1SMartin Blapp (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT)) 140696f2e892SBill Paul break; 1407d467c136SBill Paul DELAY(10); 140896f2e892SBill Paul } 140996f2e892SBill Paul 141096f2e892SBill Paul if (i == DC_TIMEOUT) 141196f2e892SBill Paul printf("dc%d: failed to force tx and " 141296f2e892SBill Paul "rx to idle state\n", sc->dc_unit); 141396f2e892SBill Paul } 141496f2e892SBill Paul 141596f2e892SBill Paul if (IFM_SUBTYPE(media) == IFM_100_TX) { 1416042c8f6eSBill Paul DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1417042c8f6eSBill Paul DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 141896f2e892SBill Paul if (sc->dc_pmode == DC_PMODE_MII) { 1419bf645417SBill Paul if (DC_IS_INTEL(sc)) { 14200934f18aSMaxime Henrion /* There's a write enable bit here that reads as 1. */ 14218273d5f8SBill Paul watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 14228273d5f8SBill Paul watchdogreg &= ~DC_WDOG_CTLWREN; 14238273d5f8SBill Paul watchdogreg |= DC_WDOG_JABBERDIS; 14244c2efe27SBill Paul CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1425bf645417SBill Paul } else { 1426bf645417SBill Paul DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1427bf645417SBill Paul } 142896f2e892SBill Paul DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 142996f2e892SBill Paul DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 143096f2e892SBill Paul if (sc->dc_type == DC_TYPE_98713) 143196f2e892SBill Paul DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 143296f2e892SBill Paul DC_NETCFG_SCRAMBLER)); 143388d739dcSBill Paul if (!DC_IS_DAVICOM(sc)) 143496f2e892SBill Paul DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 143596f2e892SBill Paul DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1436e99285a4SBill Paul if (DC_IS_INTEL(sc)) 1437e99285a4SBill Paul dc_apply_fixup(sc, IFM_AUTO); 143896f2e892SBill Paul } else { 143996f2e892SBill Paul if (DC_IS_PNIC(sc)) { 144096f2e892SBill Paul DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 144196f2e892SBill Paul DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 144296f2e892SBill Paul DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 144396f2e892SBill Paul } 1444318b02fdSBill Paul DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1445318b02fdSBill Paul DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1446318b02fdSBill Paul DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 14475c1cfac4SBill Paul if (DC_IS_INTEL(sc)) 14485c1cfac4SBill Paul dc_apply_fixup(sc, 14495c1cfac4SBill Paul (media & IFM_GMASK) == IFM_FDX ? 14505c1cfac4SBill Paul IFM_100_TX | IFM_FDX : IFM_100_TX); 145196f2e892SBill Paul } 145296f2e892SBill Paul } 145396f2e892SBill Paul 145496f2e892SBill Paul if (IFM_SUBTYPE(media) == IFM_10_T) { 1455042c8f6eSBill Paul DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1456042c8f6eSBill Paul DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 145796f2e892SBill Paul if (sc->dc_pmode == DC_PMODE_MII) { 14580934f18aSMaxime Henrion /* There's a write enable bit here that reads as 1. */ 14594c2efe27SBill Paul if (DC_IS_INTEL(sc)) { 14608273d5f8SBill Paul watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 14618273d5f8SBill Paul watchdogreg &= ~DC_WDOG_CTLWREN; 14628273d5f8SBill Paul watchdogreg |= DC_WDOG_JABBERDIS; 14638273d5f8SBill Paul CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 14644c2efe27SBill Paul } else { 14654c2efe27SBill Paul DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 14664c2efe27SBill Paul } 146796f2e892SBill Paul DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 146896f2e892SBill Paul DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 146996f2e892SBill Paul if (sc->dc_type == DC_TYPE_98713) 147096f2e892SBill Paul DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 147188d739dcSBill Paul if (!DC_IS_DAVICOM(sc)) 147296f2e892SBill Paul DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 147396f2e892SBill Paul DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1474e99285a4SBill Paul if (DC_IS_INTEL(sc)) 1475e99285a4SBill Paul dc_apply_fixup(sc, IFM_AUTO); 147696f2e892SBill Paul } else { 147796f2e892SBill Paul if (DC_IS_PNIC(sc)) { 147896f2e892SBill Paul DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 147996f2e892SBill Paul DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 148096f2e892SBill Paul DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 148196f2e892SBill Paul } 148296f2e892SBill Paul DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1483318b02fdSBill Paul DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 148496f2e892SBill Paul DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 14855c1cfac4SBill Paul if (DC_IS_INTEL(sc)) { 14865c1cfac4SBill Paul DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 14875c1cfac4SBill Paul DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 14885c1cfac4SBill Paul if ((media & IFM_GMASK) == IFM_FDX) 14895c1cfac4SBill Paul DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 14905c1cfac4SBill Paul else 14915c1cfac4SBill Paul DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 14925c1cfac4SBill Paul DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 14935c1cfac4SBill Paul DC_CLRBIT(sc, DC_10BTCTRL, 14945c1cfac4SBill Paul DC_TCTL_AUTONEGENBL); 14955c1cfac4SBill Paul dc_apply_fixup(sc, 14965c1cfac4SBill Paul (media & IFM_GMASK) == IFM_FDX ? 14975c1cfac4SBill Paul IFM_10_T | IFM_FDX : IFM_10_T); 14985c1cfac4SBill Paul DELAY(20000); 14995c1cfac4SBill Paul } 150096f2e892SBill Paul } 150196f2e892SBill Paul } 150296f2e892SBill Paul 1503f43d9309SBill Paul /* 1504f43d9309SBill Paul * If this is a Davicom DM9102A card with a DM9801 HomePNA 1505f43d9309SBill Paul * PHY and we want HomePNA mode, set the portsel bit to turn 1506f43d9309SBill Paul * on the external MII port. 1507f43d9309SBill Paul */ 1508f43d9309SBill Paul if (DC_IS_DAVICOM(sc)) { 150945521525SPoul-Henning Kamp if (IFM_SUBTYPE(media) == IFM_HPNA_1) { 1510f43d9309SBill Paul DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1511f43d9309SBill Paul sc->dc_link = 1; 1512f43d9309SBill Paul } else { 1513f43d9309SBill Paul DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1514f43d9309SBill Paul } 1515f43d9309SBill Paul } 1516f43d9309SBill Paul 151796f2e892SBill Paul if ((media & IFM_GMASK) == IFM_FDX) { 151896f2e892SBill Paul DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 151996f2e892SBill Paul if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 152096f2e892SBill Paul DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 152196f2e892SBill Paul } else { 152296f2e892SBill Paul DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 152396f2e892SBill Paul if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 152496f2e892SBill Paul DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 152596f2e892SBill Paul } 152696f2e892SBill Paul 152796f2e892SBill Paul if (restart) 152896f2e892SBill Paul DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON | DC_NETCFG_RX_ON); 152996f2e892SBill Paul } 153096f2e892SBill Paul 1531e3d2833aSAlfred Perlstein static void 15320934f18aSMaxime Henrion dc_reset(struct dc_softc *sc) 153396f2e892SBill Paul { 15340934f18aSMaxime Henrion int i; 153596f2e892SBill Paul 153696f2e892SBill Paul DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 153796f2e892SBill Paul 153896f2e892SBill Paul for (i = 0; i < DC_TIMEOUT; i++) { 153996f2e892SBill Paul DELAY(10); 154096f2e892SBill Paul if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 154196f2e892SBill Paul break; 154296f2e892SBill Paul } 154396f2e892SBill Paul 15441af8bec7SBill Paul if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) || 15451d5e5310SBill Paul DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) { 154696f2e892SBill Paul DELAY(10000); 154796f2e892SBill Paul DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 154896f2e892SBill Paul i = 0; 154996f2e892SBill Paul } 155096f2e892SBill Paul 155196f2e892SBill Paul if (i == DC_TIMEOUT) 155296f2e892SBill Paul printf("dc%d: reset never completed!\n", sc->dc_unit); 155396f2e892SBill Paul 155496f2e892SBill Paul /* Wait a little while for the chip to get its brains in order. */ 155596f2e892SBill Paul DELAY(1000); 155696f2e892SBill Paul 155796f2e892SBill Paul CSR_WRITE_4(sc, DC_IMR, 0x00000000); 155896f2e892SBill Paul CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 155996f2e892SBill Paul CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 156096f2e892SBill Paul 156191cc2adbSBill Paul /* 156291cc2adbSBill Paul * Bring the SIA out of reset. In some cases, it looks 156391cc2adbSBill Paul * like failing to unreset the SIA soon enough gets it 156491cc2adbSBill Paul * into a state where it will never come out of reset 156591cc2adbSBill Paul * until we reset the whole chip again. 156691cc2adbSBill Paul */ 15675c1cfac4SBill Paul if (DC_IS_INTEL(sc)) { 156891cc2adbSBill Paul DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 15695c1cfac4SBill Paul CSR_WRITE_4(sc, DC_10BTCTRL, 0); 15705c1cfac4SBill Paul CSR_WRITE_4(sc, DC_WATCHDOG, 0); 15715c1cfac4SBill Paul } 157296f2e892SBill Paul } 157396f2e892SBill Paul 1574e3d2833aSAlfred Perlstein static struct dc_type * 15750934f18aSMaxime Henrion dc_devtype(device_t dev) 157696f2e892SBill Paul { 157796f2e892SBill Paul struct dc_type *t; 157896f2e892SBill Paul u_int32_t rev; 157996f2e892SBill Paul 158096f2e892SBill Paul t = dc_devs; 158196f2e892SBill Paul 158296f2e892SBill Paul while (t->dc_name != NULL) { 158396f2e892SBill Paul if ((pci_get_vendor(dev) == t->dc_vid) && 158496f2e892SBill Paul (pci_get_device(dev) == t->dc_did)) { 158596f2e892SBill Paul /* Check the PCI revision */ 158696f2e892SBill Paul rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 158796f2e892SBill Paul if (t->dc_did == DC_DEVICEID_98713 && 158896f2e892SBill Paul rev >= DC_REVISION_98713A) 158996f2e892SBill Paul t++; 159096f2e892SBill Paul if (t->dc_did == DC_DEVICEID_98713_CP && 159196f2e892SBill Paul rev >= DC_REVISION_98713A) 159296f2e892SBill Paul t++; 159396f2e892SBill Paul if (t->dc_did == DC_DEVICEID_987x5 && 159479d11e09SBill Paul rev >= DC_REVISION_98715AEC_C) 159579d11e09SBill Paul t++; 159679d11e09SBill Paul if (t->dc_did == DC_DEVICEID_987x5 && 159796f2e892SBill Paul rev >= DC_REVISION_98725) 159896f2e892SBill Paul t++; 159996f2e892SBill Paul if (t->dc_did == DC_DEVICEID_AX88140A && 160096f2e892SBill Paul rev >= DC_REVISION_88141) 160196f2e892SBill Paul t++; 160296f2e892SBill Paul if (t->dc_did == DC_DEVICEID_82C168 && 160396f2e892SBill Paul rev >= DC_REVISION_82C169) 160496f2e892SBill Paul t++; 160588d739dcSBill Paul if (t->dc_did == DC_DEVICEID_DM9102 && 160688d739dcSBill Paul rev >= DC_REVISION_DM9102A) 160788d739dcSBill Paul t++; 1608e7b9ab3aSBill Paul /* 1609e7b9ab3aSBill Paul * The Microsoft MN-130 has a device ID of 0x0002, 1610e7b9ab3aSBill Paul * which happens to be the same as the PNIC 82c168. 1611e7b9ab3aSBill Paul * To keep dc_attach() from getting confused, we 1612e7b9ab3aSBill Paul * pretend its ID is something different. 1613e7b9ab3aSBill Paul * XXX: ideally, dc_attach() should be checking 1614e7b9ab3aSBill Paul * vendorid+deviceid together to avoid such 1615e7b9ab3aSBill Paul * collisions. 1616e7b9ab3aSBill Paul */ 1617e7b9ab3aSBill Paul if (t->dc_vid == DC_VENDORID_MICROSOFT && 1618e7b9ab3aSBill Paul t->dc_did == DC_DEVICEID_MSMN130) 1619e7b9ab3aSBill Paul t++; 162096f2e892SBill Paul return (t); 162196f2e892SBill Paul } 162296f2e892SBill Paul t++; 162396f2e892SBill Paul } 162496f2e892SBill Paul 162596f2e892SBill Paul return (NULL); 162696f2e892SBill Paul } 162796f2e892SBill Paul 162896f2e892SBill Paul /* 162996f2e892SBill Paul * Probe for a 21143 or clone chip. Check the PCI vendor and device 163096f2e892SBill Paul * IDs against our list and return a device name if we find a match. 163196f2e892SBill Paul * We do a little bit of extra work to identify the exact type of 163296f2e892SBill Paul * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 163396f2e892SBill Paul * but different revision IDs. The same is true for 98715/98715A 163496f2e892SBill Paul * chips and the 98725, as well as the ASIX and ADMtek chips. In some 163596f2e892SBill Paul * cases, the exact chip revision affects driver behavior. 163696f2e892SBill Paul */ 1637e3d2833aSAlfred Perlstein static int 16380934f18aSMaxime Henrion dc_probe(device_t dev) 163996f2e892SBill Paul { 164096f2e892SBill Paul struct dc_type *t; 164196f2e892SBill Paul 164296f2e892SBill Paul t = dc_devtype(dev); 164396f2e892SBill Paul 164496f2e892SBill Paul if (t != NULL) { 164596f2e892SBill Paul device_set_desc(dev, t->dc_name); 164696f2e892SBill Paul return (0); 164796f2e892SBill Paul } 164896f2e892SBill Paul 164996f2e892SBill Paul return (ENXIO); 165096f2e892SBill Paul } 165196f2e892SBill Paul 1652b84e866aSWarner Losh #ifndef BURN_BRIDGES 1653e3d2833aSAlfred Perlstein static void 16540934f18aSMaxime Henrion dc_acpi(device_t dev) 165596f2e892SBill Paul { 165696f2e892SBill Paul int unit; 16570934f18aSMaxime Henrion u_int32_t iobase, membase, irq; 165896f2e892SBill Paul 165996f2e892SBill Paul unit = device_get_unit(dev); 166096f2e892SBill Paul 166114a00c6cSBill Paul if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 166296f2e892SBill Paul /* Save important PCI config data. */ 166396f2e892SBill Paul iobase = pci_read_config(dev, DC_PCI_CFBIO, 4); 166496f2e892SBill Paul membase = pci_read_config(dev, DC_PCI_CFBMA, 4); 166596f2e892SBill Paul irq = pci_read_config(dev, DC_PCI_CFIT, 4); 166696f2e892SBill Paul 166796f2e892SBill Paul /* Reset the power state. */ 166896f2e892SBill Paul printf("dc%d: chip is in D%d power mode " 166914a00c6cSBill Paul "-- setting to D0\n", unit, 167014a00c6cSBill Paul pci_get_powerstate(dev)); 167114a00c6cSBill Paul pci_set_powerstate(dev, PCI_POWERSTATE_D0); 167296f2e892SBill Paul 167396f2e892SBill Paul /* Restore PCI config data. */ 167496f2e892SBill Paul pci_write_config(dev, DC_PCI_CFBIO, iobase, 4); 167596f2e892SBill Paul pci_write_config(dev, DC_PCI_CFBMA, membase, 4); 167696f2e892SBill Paul pci_write_config(dev, DC_PCI_CFIT, irq, 4); 167796f2e892SBill Paul } 167896f2e892SBill Paul } 1679b84e866aSWarner Losh #endif 168096f2e892SBill Paul 1681e3d2833aSAlfred Perlstein static void 16820934f18aSMaxime Henrion dc_apply_fixup(struct dc_softc *sc, int media) 16835c1cfac4SBill Paul { 16845c1cfac4SBill Paul struct dc_mediainfo *m; 16855c1cfac4SBill Paul u_int8_t *p; 16865c1cfac4SBill Paul int i; 16875d801891SBill Paul u_int32_t reg; 16885c1cfac4SBill Paul 16895c1cfac4SBill Paul m = sc->dc_mi; 16905c1cfac4SBill Paul 16915c1cfac4SBill Paul while (m != NULL) { 16925c1cfac4SBill Paul if (m->dc_media == media) 16935c1cfac4SBill Paul break; 16945c1cfac4SBill Paul m = m->dc_next; 16955c1cfac4SBill Paul } 16965c1cfac4SBill Paul 16975c1cfac4SBill Paul if (m == NULL) 16985c1cfac4SBill Paul return; 16995c1cfac4SBill Paul 17005c1cfac4SBill Paul for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 17015c1cfac4SBill Paul reg = (p[0] | (p[1] << 8)) << 16; 17025c1cfac4SBill Paul CSR_WRITE_4(sc, DC_WATCHDOG, reg); 17035c1cfac4SBill Paul } 17045c1cfac4SBill Paul 17055c1cfac4SBill Paul for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 17065c1cfac4SBill Paul reg = (p[0] | (p[1] << 8)) << 16; 17075c1cfac4SBill Paul CSR_WRITE_4(sc, DC_WATCHDOG, reg); 17085c1cfac4SBill Paul } 17095c1cfac4SBill Paul } 17105c1cfac4SBill Paul 1711e3d2833aSAlfred Perlstein static void 17120934f18aSMaxime Henrion dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l) 17135c1cfac4SBill Paul { 17145c1cfac4SBill Paul struct dc_mediainfo *m; 17155c1cfac4SBill Paul 17160934f18aSMaxime Henrion m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 171787f4fa15SMartin Blapp switch (l->dc_sia_code & ~DC_SIA_CODE_EXT) { 171887f4fa15SMartin Blapp case DC_SIA_CODE_10BT: 17195c1cfac4SBill Paul m->dc_media = IFM_10_T; 172087f4fa15SMartin Blapp break; 172187f4fa15SMartin Blapp case DC_SIA_CODE_10BT_FDX: 17225c1cfac4SBill Paul m->dc_media = IFM_10_T | IFM_FDX; 172387f4fa15SMartin Blapp break; 172487f4fa15SMartin Blapp case DC_SIA_CODE_10B2: 17255c1cfac4SBill Paul m->dc_media = IFM_10_2; 172687f4fa15SMartin Blapp break; 172787f4fa15SMartin Blapp case DC_SIA_CODE_10B5: 17285c1cfac4SBill Paul m->dc_media = IFM_10_5; 172987f4fa15SMartin Blapp break; 173087f4fa15SMartin Blapp default: 173187f4fa15SMartin Blapp break; 173287f4fa15SMartin Blapp } 17335c1cfac4SBill Paul 173487f4fa15SMartin Blapp /* 173587f4fa15SMartin Blapp * We need to ignore CSR13, CSR14, CSR15 for SIA mode. 173687f4fa15SMartin Blapp * Things apparently already work for cards that do 173787f4fa15SMartin Blapp * supply Media Specific Data. 173887f4fa15SMartin Blapp */ 173987f4fa15SMartin Blapp if (l->dc_sia_code & DC_SIA_CODE_EXT) { 17405c1cfac4SBill Paul m->dc_gp_len = 2; 174187f4fa15SMartin Blapp m->dc_gp_ptr = 174287f4fa15SMartin Blapp (u_int8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl; 174387f4fa15SMartin Blapp } else { 174487f4fa15SMartin Blapp m->dc_gp_len = 2; 174587f4fa15SMartin Blapp m->dc_gp_ptr = 174687f4fa15SMartin Blapp (u_int8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl; 174787f4fa15SMartin Blapp } 17485c1cfac4SBill Paul 17495c1cfac4SBill Paul m->dc_next = sc->dc_mi; 17505c1cfac4SBill Paul sc->dc_mi = m; 17515c1cfac4SBill Paul 17525c1cfac4SBill Paul sc->dc_pmode = DC_PMODE_SIA; 17535c1cfac4SBill Paul } 17545c1cfac4SBill Paul 1755e3d2833aSAlfred Perlstein static void 17560934f18aSMaxime Henrion dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l) 17575c1cfac4SBill Paul { 17585c1cfac4SBill Paul struct dc_mediainfo *m; 17595c1cfac4SBill Paul 17600934f18aSMaxime Henrion m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 17615c1cfac4SBill Paul if (l->dc_sym_code == DC_SYM_CODE_100BT) 17625c1cfac4SBill Paul m->dc_media = IFM_100_TX; 17635c1cfac4SBill Paul 17645c1cfac4SBill Paul if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 17655c1cfac4SBill Paul m->dc_media = IFM_100_TX | IFM_FDX; 17665c1cfac4SBill Paul 17675c1cfac4SBill Paul m->dc_gp_len = 2; 17685c1cfac4SBill Paul m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 17695c1cfac4SBill Paul 17705c1cfac4SBill Paul m->dc_next = sc->dc_mi; 17715c1cfac4SBill Paul sc->dc_mi = m; 17725c1cfac4SBill Paul 17735c1cfac4SBill Paul sc->dc_pmode = DC_PMODE_SYM; 17745c1cfac4SBill Paul } 17755c1cfac4SBill Paul 1776e3d2833aSAlfred Perlstein static void 17770934f18aSMaxime Henrion dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l) 17785c1cfac4SBill Paul { 17795c1cfac4SBill Paul struct dc_mediainfo *m; 17800934f18aSMaxime Henrion u_int8_t *p; 17815c1cfac4SBill Paul 17820934f18aSMaxime Henrion m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 17835c1cfac4SBill Paul /* We abuse IFM_AUTO to represent MII. */ 17845c1cfac4SBill Paul m->dc_media = IFM_AUTO; 17855c1cfac4SBill Paul m->dc_gp_len = l->dc_gpr_len; 17865c1cfac4SBill Paul 17875c1cfac4SBill Paul p = (u_int8_t *)l; 17885c1cfac4SBill Paul p += sizeof(struct dc_eblock_mii); 17895c1cfac4SBill Paul m->dc_gp_ptr = p; 17905c1cfac4SBill Paul p += 2 * l->dc_gpr_len; 17915c1cfac4SBill Paul m->dc_reset_len = *p; 17925c1cfac4SBill Paul p++; 17935c1cfac4SBill Paul m->dc_reset_ptr = p; 17945c1cfac4SBill Paul 17955c1cfac4SBill Paul m->dc_next = sc->dc_mi; 17965c1cfac4SBill Paul sc->dc_mi = m; 17975c1cfac4SBill Paul } 17985c1cfac4SBill Paul 17992c876e15SPoul-Henning Kamp static void 18000934f18aSMaxime Henrion dc_read_srom(struct dc_softc *sc, int bits) 18013097aa70SWarner Losh { 18023097aa70SWarner Losh int size; 18033097aa70SWarner Losh 18043097aa70SWarner Losh size = 2 << bits; 18053097aa70SWarner Losh sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT); 18063097aa70SWarner Losh dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); 18073097aa70SWarner Losh } 18083097aa70SWarner Losh 1809e3d2833aSAlfred Perlstein static void 18100934f18aSMaxime Henrion dc_parse_21143_srom(struct dc_softc *sc) 18115c1cfac4SBill Paul { 18125c1cfac4SBill Paul struct dc_leaf_hdr *lhdr; 18135c1cfac4SBill Paul struct dc_eblock_hdr *hdr; 18140934f18aSMaxime Henrion int have_mii, i, loff; 18155c1cfac4SBill Paul char *ptr; 18165c1cfac4SBill Paul 1817f956e0b3SMartin Blapp have_mii = 0; 18185c1cfac4SBill Paul loff = sc->dc_srom[27]; 18195c1cfac4SBill Paul lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 18205c1cfac4SBill Paul 18215c1cfac4SBill Paul ptr = (char *)lhdr; 18225c1cfac4SBill Paul ptr += sizeof(struct dc_leaf_hdr) - 1; 1823f956e0b3SMartin Blapp /* 1824f956e0b3SMartin Blapp * Look if we got a MII media block. 1825f956e0b3SMartin Blapp */ 1826f956e0b3SMartin Blapp for (i = 0; i < lhdr->dc_mcnt; i++) { 1827f956e0b3SMartin Blapp hdr = (struct dc_eblock_hdr *)ptr; 1828f956e0b3SMartin Blapp if (hdr->dc_type == DC_EBLOCK_MII) 1829f956e0b3SMartin Blapp have_mii++; 1830f956e0b3SMartin Blapp 1831f956e0b3SMartin Blapp ptr += (hdr->dc_len & 0x7F); 1832f956e0b3SMartin Blapp ptr++; 1833f956e0b3SMartin Blapp } 1834f956e0b3SMartin Blapp 1835f956e0b3SMartin Blapp /* 1836f956e0b3SMartin Blapp * Do the same thing again. Only use SIA and SYM media 1837f956e0b3SMartin Blapp * blocks if no MII media block is available. 1838f956e0b3SMartin Blapp */ 1839f956e0b3SMartin Blapp ptr = (char *)lhdr; 1840f956e0b3SMartin Blapp ptr += sizeof(struct dc_leaf_hdr) - 1; 18415c1cfac4SBill Paul for (i = 0; i < lhdr->dc_mcnt; i++) { 18425c1cfac4SBill Paul hdr = (struct dc_eblock_hdr *)ptr; 18435c1cfac4SBill Paul switch (hdr->dc_type) { 18445c1cfac4SBill Paul case DC_EBLOCK_MII: 18455c1cfac4SBill Paul dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 18465c1cfac4SBill Paul break; 18475c1cfac4SBill Paul case DC_EBLOCK_SIA: 1848f956e0b3SMartin Blapp if (! have_mii) 1849f956e0b3SMartin Blapp dc_decode_leaf_sia(sc, 1850f956e0b3SMartin Blapp (struct dc_eblock_sia *)hdr); 18515c1cfac4SBill Paul break; 18525c1cfac4SBill Paul case DC_EBLOCK_SYM: 1853f956e0b3SMartin Blapp if (! have_mii) 1854f956e0b3SMartin Blapp dc_decode_leaf_sym(sc, 1855f956e0b3SMartin Blapp (struct dc_eblock_sym *)hdr); 18565c1cfac4SBill Paul break; 18575c1cfac4SBill Paul default: 18585c1cfac4SBill Paul /* Don't care. Yet. */ 18595c1cfac4SBill Paul break; 18605c1cfac4SBill Paul } 18615c1cfac4SBill Paul ptr += (hdr->dc_len & 0x7F); 18625c1cfac4SBill Paul ptr++; 18635c1cfac4SBill Paul } 18645c1cfac4SBill Paul } 18655c1cfac4SBill Paul 186656e5e7aeSMaxime Henrion static void 186756e5e7aeSMaxime Henrion dc_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 186856e5e7aeSMaxime Henrion { 186956e5e7aeSMaxime Henrion u_int32_t *paddr; 187056e5e7aeSMaxime Henrion 187156e5e7aeSMaxime Henrion KASSERT(nseg == 1, ("wrong number of segments, should be 1")); 187256e5e7aeSMaxime Henrion paddr = arg; 187356e5e7aeSMaxime Henrion *paddr = segs->ds_addr; 187456e5e7aeSMaxime Henrion } 187556e5e7aeSMaxime Henrion 187696f2e892SBill Paul /* 187796f2e892SBill Paul * Attach the interface. Allocate softc structures, do ifmedia 187896f2e892SBill Paul * setup and ethernet/BPF attach. 187996f2e892SBill Paul */ 1880e3d2833aSAlfred Perlstein static int 18810934f18aSMaxime Henrion dc_attach(device_t dev) 188296f2e892SBill Paul { 1883d1ce9105SBill Paul int tmp = 0; 188496f2e892SBill Paul u_char eaddr[ETHER_ADDR_LEN]; 188596f2e892SBill Paul u_int32_t command; 188696f2e892SBill Paul struct dc_softc *sc; 188796f2e892SBill Paul struct ifnet *ifp; 188896f2e892SBill Paul u_int32_t revision; 188996f2e892SBill Paul int unit, error = 0, rid, mac_offset; 189056e5e7aeSMaxime Henrion int i; 1891e7b01d07SWarner Losh u_int8_t *mac; 189296f2e892SBill Paul 189396f2e892SBill Paul sc = device_get_softc(dev); 189496f2e892SBill Paul unit = device_get_unit(dev); 189596f2e892SBill Paul 18966008862bSJohn Baldwin mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 18976008862bSJohn Baldwin MTX_DEF | MTX_RECURSE); 1898b84e866aSWarner Losh #ifndef BURN_BRIDGES 189996f2e892SBill Paul /* 190096f2e892SBill Paul * Handle power management nonsense. 190196f2e892SBill Paul */ 190296f2e892SBill Paul dc_acpi(dev); 1903b84e866aSWarner Losh #endif 190496f2e892SBill Paul /* 190596f2e892SBill Paul * Map control/status registers. 190696f2e892SBill Paul */ 190707f65363SBill Paul pci_enable_busmaster(dev); 190896f2e892SBill Paul 190996f2e892SBill Paul rid = DC_RID; 191096f2e892SBill Paul sc->dc_res = bus_alloc_resource(dev, DC_RES, &rid, 191196f2e892SBill Paul 0, ~0, 1, RF_ACTIVE); 191296f2e892SBill Paul 191396f2e892SBill Paul if (sc->dc_res == NULL) { 191496f2e892SBill Paul printf("dc%d: couldn't map ports/memory\n", unit); 191596f2e892SBill Paul error = ENXIO; 1916608654d4SNate Lawson goto fail; 191796f2e892SBill Paul } 191896f2e892SBill Paul 191996f2e892SBill Paul sc->dc_btag = rman_get_bustag(sc->dc_res); 192096f2e892SBill Paul sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 192196f2e892SBill Paul 19220934f18aSMaxime Henrion /* Allocate interrupt. */ 192354f1f1d1SNate Lawson rid = 0; 192454f1f1d1SNate Lawson sc->dc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 192554f1f1d1SNate Lawson RF_SHAREABLE | RF_ACTIVE); 192654f1f1d1SNate Lawson 192754f1f1d1SNate Lawson if (sc->dc_irq == NULL) { 192854f1f1d1SNate Lawson printf("dc%d: couldn't map interrupt\n", unit); 192954f1f1d1SNate Lawson error = ENXIO; 193054f1f1d1SNate Lawson goto fail; 193154f1f1d1SNate Lawson } 193254f1f1d1SNate Lawson 193396f2e892SBill Paul /* Need this info to decide on a chip type. */ 193496f2e892SBill Paul sc->dc_info = dc_devtype(dev); 193596f2e892SBill Paul revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF; 193696f2e892SBill Paul 19376d0dd931SWarner Losh /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */ 1938eecb3844SMartin Blapp if (sc->dc_info->dc_did != DC_DEVICEID_82C168 && 1939eecb3844SMartin Blapp sc->dc_info->dc_did != DC_DEVICEID_X3201) 1940eecb3844SMartin Blapp dc_eeprom_width(sc); 1941eecb3844SMartin Blapp 194296f2e892SBill Paul switch (sc->dc_info->dc_did) { 194396f2e892SBill Paul case DC_DEVICEID_21143: 194496f2e892SBill Paul sc->dc_type = DC_TYPE_21143; 194596f2e892SBill Paul sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1946042c8f6eSBill Paul sc->dc_flags |= DC_REDUCED_MII_POLL; 19475c1cfac4SBill Paul /* Save EEPROM contents so we can parse them later. */ 19483097aa70SWarner Losh dc_read_srom(sc, sc->dc_romwidth); 194996f2e892SBill Paul break; 195038deb45fSTom Rhodes case DC_DEVICEID_DM9009: 195196f2e892SBill Paul case DC_DEVICEID_DM9100: 195296f2e892SBill Paul case DC_DEVICEID_DM9102: 195396f2e892SBill Paul sc->dc_type = DC_TYPE_DM9102; 1954318a72d7SBill Paul sc->dc_flags |= DC_TX_COALESCE | DC_TX_INTR_ALWAYS; 1955318a72d7SBill Paul sc->dc_flags |= DC_REDUCED_MII_POLL | DC_TX_STORENFWD; 19567dfdc26cSMartin Blapp sc->dc_flags |= DC_TX_ALIGN; 19574a80e74bSMartin Blapp sc->dc_pmode = DC_PMODE_MII; 19580a46b1dcSBill Paul /* Increase the latency timer value. */ 19590a46b1dcSBill Paul command = pci_read_config(dev, DC_PCI_CFLT, 4); 19600a46b1dcSBill Paul command &= 0xFFFF00FF; 19610a46b1dcSBill Paul command |= 0x00008000; 19620a46b1dcSBill Paul pci_write_config(dev, DC_PCI_CFLT, command, 4); 196396f2e892SBill Paul break; 196496f2e892SBill Paul case DC_DEVICEID_AL981: 196596f2e892SBill Paul sc->dc_type = DC_TYPE_AL981; 196696f2e892SBill Paul sc->dc_flags |= DC_TX_USE_TX_INTR; 196796f2e892SBill Paul sc->dc_flags |= DC_TX_ADMTEK_WAR; 196896f2e892SBill Paul sc->dc_pmode = DC_PMODE_MII; 19693097aa70SWarner Losh dc_read_srom(sc, sc->dc_romwidth); 197096f2e892SBill Paul break; 197196f2e892SBill Paul case DC_DEVICEID_AN985: 1972e351d778SMartin Blapp case DC_DEVICEID_ADM9511: 1973e351d778SMartin Blapp case DC_DEVICEID_ADM9513: 19744c16d09eSWarner Losh case DC_DEVICEID_FA511: 197541fced74SPeter Wemm case DC_DEVICEID_FE2500: 1976fa167b8eSBill Paul case DC_DEVICEID_EN2242: 1977948c244dSWarner Losh case DC_DEVICEID_HAWKING_PN672TX: 19787eac366bSMartin Blapp case DC_DEVICEID_3CSOHOB: 1979e7b9ab3aSBill Paul case DC_DEVICEID_MSMN120: 1980e7b9ab3aSBill Paul case DC_DEVICEID_MSMN130_FAKE: /* XXX avoid collision with PNIC*/ 198196f2e892SBill Paul sc->dc_type = DC_TYPE_AN985; 1982acc1bcccSMartin Blapp sc->dc_flags |= DC_64BIT_HASH; 198396f2e892SBill Paul sc->dc_flags |= DC_TX_USE_TX_INTR; 198496f2e892SBill Paul sc->dc_flags |= DC_TX_ADMTEK_WAR; 198596f2e892SBill Paul sc->dc_pmode = DC_PMODE_MII; 1986129eaf79SMartin Blapp /* Don't read SROM for - auto-loaded on reset */ 198796f2e892SBill Paul break; 198896f2e892SBill Paul case DC_DEVICEID_98713: 198996f2e892SBill Paul case DC_DEVICEID_98713_CP: 199096f2e892SBill Paul if (revision < DC_REVISION_98713A) { 199196f2e892SBill Paul sc->dc_type = DC_TYPE_98713; 199296f2e892SBill Paul } 1993318b02fdSBill Paul if (revision >= DC_REVISION_98713A) { 199496f2e892SBill Paul sc->dc_type = DC_TYPE_98713A; 1995318b02fdSBill Paul sc->dc_flags |= DC_21143_NWAY; 1996318b02fdSBill Paul } 1997318b02fdSBill Paul sc->dc_flags |= DC_REDUCED_MII_POLL; 199896f2e892SBill Paul sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 199996f2e892SBill Paul break; 200096f2e892SBill Paul case DC_DEVICEID_987x5: 20019ca710f6SJeroen Ruigrok van der Werven case DC_DEVICEID_EN1217: 200279d11e09SBill Paul /* 200379d11e09SBill Paul * Macronix MX98715AEC-C/D/E parts have only a 200479d11e09SBill Paul * 128-bit hash table. We need to deal with these 200579d11e09SBill Paul * in the same manner as the PNIC II so that we 200679d11e09SBill Paul * get the right number of bits out of the 200779d11e09SBill Paul * CRC routine. 200879d11e09SBill Paul */ 200979d11e09SBill Paul if (revision >= DC_REVISION_98715AEC_C && 201079d11e09SBill Paul revision < DC_REVISION_98725) 201179d11e09SBill Paul sc->dc_flags |= DC_128BIT_HASH; 201296f2e892SBill Paul sc->dc_type = DC_TYPE_987x5; 201396f2e892SBill Paul sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 2014318b02fdSBill Paul sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 201596f2e892SBill Paul break; 2016ead7cde9SBill Paul case DC_DEVICEID_98727: 2017ead7cde9SBill Paul sc->dc_type = DC_TYPE_987x5; 2018ead7cde9SBill Paul sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 2019ead7cde9SBill Paul sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 2020ead7cde9SBill Paul break; 202196f2e892SBill Paul case DC_DEVICEID_82C115: 202296f2e892SBill Paul sc->dc_type = DC_TYPE_PNICII; 202379d11e09SBill Paul sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR | DC_128BIT_HASH; 2024318b02fdSBill Paul sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 202596f2e892SBill Paul break; 202696f2e892SBill Paul case DC_DEVICEID_82C168: 202796f2e892SBill Paul sc->dc_type = DC_TYPE_PNIC; 202891cc2adbSBill Paul sc->dc_flags |= DC_TX_STORENFWD | DC_TX_INTR_ALWAYS; 202996f2e892SBill Paul sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 203096f2e892SBill Paul sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 203196f2e892SBill Paul if (revision < DC_REVISION_82C169) 203296f2e892SBill Paul sc->dc_pmode = DC_PMODE_SYM; 203396f2e892SBill Paul break; 203496f2e892SBill Paul case DC_DEVICEID_AX88140A: 203596f2e892SBill Paul sc->dc_type = DC_TYPE_ASIX; 203696f2e892SBill Paul sc->dc_flags |= DC_TX_USE_TX_INTR | DC_TX_INTR_FIRSTFRAG; 203796f2e892SBill Paul sc->dc_flags |= DC_REDUCED_MII_POLL; 203896f2e892SBill Paul sc->dc_pmode = DC_PMODE_MII; 203996f2e892SBill Paul break; 2040feb78939SJonathan Chen case DC_DEVICEID_X3201: 2041feb78939SJonathan Chen sc->dc_type = DC_TYPE_XIRCOM; 20422dfc960aSLuigi Rizzo sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 20432dfc960aSLuigi Rizzo DC_TX_ALIGN; 2044feb78939SJonathan Chen /* 2045feb78939SJonathan Chen * We don't actually need to coalesce, but we're doing 2046feb78939SJonathan Chen * it to obtain a double word aligned buffer. 20472dfc960aSLuigi Rizzo * The DC_TX_COALESCE flag is required. 2048feb78939SJonathan Chen */ 20493097aa70SWarner Losh sc->dc_pmode = DC_PMODE_MII; 2050feb78939SJonathan Chen break; 20511af8bec7SBill Paul case DC_DEVICEID_RS7112: 20521af8bec7SBill Paul sc->dc_type = DC_TYPE_CONEXANT; 20531af8bec7SBill Paul sc->dc_flags |= DC_TX_INTR_ALWAYS; 20541af8bec7SBill Paul sc->dc_flags |= DC_REDUCED_MII_POLL; 20551af8bec7SBill Paul sc->dc_pmode = DC_PMODE_MII; 20563097aa70SWarner Losh dc_read_srom(sc, sc->dc_romwidth); 20571af8bec7SBill Paul break; 205896f2e892SBill Paul default: 205996f2e892SBill Paul printf("dc%d: unknown device: %x\n", sc->dc_unit, 206096f2e892SBill Paul sc->dc_info->dc_did); 206196f2e892SBill Paul break; 206296f2e892SBill Paul } 206396f2e892SBill Paul 206496f2e892SBill Paul /* Save the cache line size. */ 206588d739dcSBill Paul if (DC_IS_DAVICOM(sc)) 206688d739dcSBill Paul sc->dc_cachesize = 0; 206788d739dcSBill Paul else 206888d739dcSBill Paul sc->dc_cachesize = pci_read_config(dev, 206988d739dcSBill Paul DC_PCI_CFLT, 4) & 0xFF; 207096f2e892SBill Paul 207196f2e892SBill Paul /* Reset the adapter. */ 207296f2e892SBill Paul dc_reset(sc); 207396f2e892SBill Paul 207496f2e892SBill Paul /* Take 21143 out of snooze mode */ 2075feb78939SJonathan Chen if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 207696f2e892SBill Paul command = pci_read_config(dev, DC_PCI_CFDD, 4); 207796f2e892SBill Paul command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 207896f2e892SBill Paul pci_write_config(dev, DC_PCI_CFDD, command, 4); 207996f2e892SBill Paul } 208096f2e892SBill Paul 208196f2e892SBill Paul /* 208296f2e892SBill Paul * Try to learn something about the supported media. 208396f2e892SBill Paul * We know that ASIX and ADMtek and Davicom devices 208496f2e892SBill Paul * will *always* be using MII media, so that's a no-brainer. 208596f2e892SBill Paul * The tricky ones are the Macronix/PNIC II and the 208696f2e892SBill Paul * Intel 21143. 208796f2e892SBill Paul */ 20885c1cfac4SBill Paul if (DC_IS_INTEL(sc)) 20895c1cfac4SBill Paul dc_parse_21143_srom(sc); 20905c1cfac4SBill Paul else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 209196f2e892SBill Paul if (sc->dc_type == DC_TYPE_98713) 209296f2e892SBill Paul sc->dc_pmode = DC_PMODE_MII; 209396f2e892SBill Paul else 209496f2e892SBill Paul sc->dc_pmode = DC_PMODE_SYM; 209596f2e892SBill Paul } else if (!sc->dc_pmode) 209696f2e892SBill Paul sc->dc_pmode = DC_PMODE_MII; 209796f2e892SBill Paul 209896f2e892SBill Paul /* 209996f2e892SBill Paul * Get station address from the EEPROM. 210096f2e892SBill Paul */ 210196f2e892SBill Paul switch(sc->dc_type) { 210296f2e892SBill Paul case DC_TYPE_98713: 210396f2e892SBill Paul case DC_TYPE_98713A: 210496f2e892SBill Paul case DC_TYPE_987x5: 210596f2e892SBill Paul case DC_TYPE_PNICII: 210696f2e892SBill Paul dc_read_eeprom(sc, (caddr_t)&mac_offset, 210796f2e892SBill Paul (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 210896f2e892SBill Paul dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 210996f2e892SBill Paul break; 211096f2e892SBill Paul case DC_TYPE_PNIC: 211196f2e892SBill Paul dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 211296f2e892SBill Paul break; 211396f2e892SBill Paul case DC_TYPE_DM9102: 2114ec6a7299SMaxime Henrion dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2115ec6a7299SMaxime Henrion #ifdef __sparc64__ 2116ec6a7299SMaxime Henrion /* 2117ec6a7299SMaxime Henrion * If this is an onboard dc(4) the station address read from 2118ec6a7299SMaxime Henrion * the EEPROM is all zero and we have to get it from the fcode. 2119ec6a7299SMaxime Henrion */ 2120ec6a7299SMaxime Henrion for (i = 0; i < ETHER_ADDR_LEN; i++) 2121ec6a7299SMaxime Henrion if (eaddr[i] != 0x00) 2122ec6a7299SMaxime Henrion break; 2123ec6a7299SMaxime Henrion if (i >= ETHER_ADDR_LEN && OF_getetheraddr2(dev, eaddr) == -1) 2124ec6a7299SMaxime Henrion OF_getetheraddr(dev, eaddr); 2125ec6a7299SMaxime Henrion #endif 2126ec6a7299SMaxime Henrion break; 212796f2e892SBill Paul case DC_TYPE_21143: 212896f2e892SBill Paul case DC_TYPE_ASIX: 212996f2e892SBill Paul dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 213096f2e892SBill Paul break; 213196f2e892SBill Paul case DC_TYPE_AL981: 213296f2e892SBill Paul case DC_TYPE_AN985: 2133129eaf79SMartin Blapp *(u_int32_t *)(&eaddr[0]) = CSR_READ_4(sc, DC_AL_PAR0); 2134129eaf79SMartin Blapp *(u_int16_t *)(&eaddr[4]) = CSR_READ_4(sc, DC_AL_PAR1); 213596f2e892SBill Paul break; 21361af8bec7SBill Paul case DC_TYPE_CONEXANT: 21370934f18aSMaxime Henrion bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 21380934f18aSMaxime Henrion ETHER_ADDR_LEN); 21391af8bec7SBill Paul break; 2140feb78939SJonathan Chen case DC_TYPE_XIRCOM: 21410934f18aSMaxime Henrion /* The MAC comes from the CIS. */ 2142e7b01d07SWarner Losh mac = pci_get_ether(dev); 2143e7b01d07SWarner Losh if (!mac) { 2144e7b01d07SWarner Losh device_printf(dev, "No station address in CIS!\n"); 2145608654d4SNate Lawson error = ENXIO; 2146e7b01d07SWarner Losh goto fail; 2147e7b01d07SWarner Losh } 2148e7b01d07SWarner Losh bcopy(mac, eaddr, ETHER_ADDR_LEN); 2149feb78939SJonathan Chen break; 215096f2e892SBill Paul default: 215196f2e892SBill Paul dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 215296f2e892SBill Paul break; 215396f2e892SBill Paul } 215496f2e892SBill Paul 215596f2e892SBill Paul /* 215696f2e892SBill Paul * A 21143 or clone chip was detected. Inform the world. 215796f2e892SBill Paul */ 215896f2e892SBill Paul printf("dc%d: Ethernet address: %6D\n", unit, eaddr, ":"); 215996f2e892SBill Paul 216096f2e892SBill Paul sc->dc_unit = unit; 21610934f18aSMaxime Henrion bcopy(eaddr, &sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 216296f2e892SBill Paul 216356e5e7aeSMaxime Henrion /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */ 216456e5e7aeSMaxime Henrion error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 216556e5e7aeSMaxime Henrion BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct dc_list_data), 1, 216656e5e7aeSMaxime Henrion sizeof(struct dc_list_data), 0, NULL, NULL, &sc->dc_ltag); 216756e5e7aeSMaxime Henrion if (error) { 216856e5e7aeSMaxime Henrion printf("dc%d: failed to allocate busdma tag\n", unit); 216956e5e7aeSMaxime Henrion error = ENXIO; 217056e5e7aeSMaxime Henrion goto fail; 217156e5e7aeSMaxime Henrion } 217256e5e7aeSMaxime Henrion error = bus_dmamem_alloc(sc->dc_ltag, (void **)&sc->dc_ldata, 2173aafb3ebbSMaxime Henrion BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->dc_lmap); 217456e5e7aeSMaxime Henrion if (error) { 217556e5e7aeSMaxime Henrion printf("dc%d: failed to allocate DMA safe memory\n", unit); 217656e5e7aeSMaxime Henrion error = ENXIO; 217756e5e7aeSMaxime Henrion goto fail; 217856e5e7aeSMaxime Henrion } 217956e5e7aeSMaxime Henrion error = bus_dmamap_load(sc->dc_ltag, sc->dc_lmap, sc->dc_ldata, 218056e5e7aeSMaxime Henrion sizeof(struct dc_list_data), dc_dma_map_addr, &sc->dc_laddr, 218156e5e7aeSMaxime Henrion BUS_DMA_NOWAIT); 218256e5e7aeSMaxime Henrion if (error) { 218356e5e7aeSMaxime Henrion printf("dc%d: cannot get address of the descriptors\n", unit); 218456e5e7aeSMaxime Henrion error = ENXIO; 218556e5e7aeSMaxime Henrion goto fail; 218656e5e7aeSMaxime Henrion } 218796f2e892SBill Paul 218856e5e7aeSMaxime Henrion /* 218956e5e7aeSMaxime Henrion * Allocate a busdma tag and DMA safe memory for the multicast 219056e5e7aeSMaxime Henrion * setup frame. 219156e5e7aeSMaxime Henrion */ 219256e5e7aeSMaxime Henrion error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 219356e5e7aeSMaxime Henrion BUS_SPACE_MAXADDR, NULL, NULL, DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1, 219456e5e7aeSMaxime Henrion DC_SFRAME_LEN + DC_MIN_FRAMELEN, 0, NULL, NULL, &sc->dc_stag); 219556e5e7aeSMaxime Henrion if (error) { 219656e5e7aeSMaxime Henrion printf("dc%d: failed to allocate busdma tag\n", unit); 219756e5e7aeSMaxime Henrion error = ENXIO; 219856e5e7aeSMaxime Henrion goto fail; 219956e5e7aeSMaxime Henrion } 220056e5e7aeSMaxime Henrion error = bus_dmamem_alloc(sc->dc_stag, (void **)&sc->dc_cdata.dc_sbuf, 220156e5e7aeSMaxime Henrion BUS_DMA_NOWAIT, &sc->dc_smap); 220256e5e7aeSMaxime Henrion if (error) { 220356e5e7aeSMaxime Henrion printf("dc%d: failed to allocate DMA safe memory\n", unit); 220456e5e7aeSMaxime Henrion error = ENXIO; 220556e5e7aeSMaxime Henrion goto fail; 220656e5e7aeSMaxime Henrion } 220756e5e7aeSMaxime Henrion error = bus_dmamap_load(sc->dc_stag, sc->dc_smap, sc->dc_cdata.dc_sbuf, 220856e5e7aeSMaxime Henrion DC_SFRAME_LEN, dc_dma_map_addr, &sc->dc_saddr, BUS_DMA_NOWAIT); 220956e5e7aeSMaxime Henrion if (error) { 221056e5e7aeSMaxime Henrion printf("dc%d: cannot get address of the descriptors\n", unit); 221196f2e892SBill Paul error = ENXIO; 221296f2e892SBill Paul goto fail; 221396f2e892SBill Paul } 221496f2e892SBill Paul 221556e5e7aeSMaxime Henrion /* Allocate a busdma tag for mbufs. */ 221656e5e7aeSMaxime Henrion error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 221756e5e7aeSMaxime Henrion BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * DC_TX_LIST_CNT, 221856e5e7aeSMaxime Henrion DC_TX_LIST_CNT, MCLBYTES, 0, NULL, NULL, &sc->dc_mtag); 221956e5e7aeSMaxime Henrion if (error) { 222056e5e7aeSMaxime Henrion printf("dc%d: failed to allocate busdma tag\n", unit); 222156e5e7aeSMaxime Henrion error = ENXIO; 222256e5e7aeSMaxime Henrion goto fail; 222356e5e7aeSMaxime Henrion } 222456e5e7aeSMaxime Henrion 222556e5e7aeSMaxime Henrion /* Create the TX/RX busdma maps. */ 222656e5e7aeSMaxime Henrion for (i = 0; i < DC_TX_LIST_CNT; i++) { 222756e5e7aeSMaxime Henrion error = bus_dmamap_create(sc->dc_mtag, 0, 222856e5e7aeSMaxime Henrion &sc->dc_cdata.dc_tx_map[i]); 222956e5e7aeSMaxime Henrion if (error) { 223056e5e7aeSMaxime Henrion printf("dc%d: failed to init TX ring\n", unit); 223156e5e7aeSMaxime Henrion error = ENXIO; 223256e5e7aeSMaxime Henrion goto fail; 223356e5e7aeSMaxime Henrion } 223456e5e7aeSMaxime Henrion } 223556e5e7aeSMaxime Henrion for (i = 0; i < DC_RX_LIST_CNT; i++) { 223656e5e7aeSMaxime Henrion error = bus_dmamap_create(sc->dc_mtag, 0, 223756e5e7aeSMaxime Henrion &sc->dc_cdata.dc_rx_map[i]); 223856e5e7aeSMaxime Henrion if (error) { 223956e5e7aeSMaxime Henrion printf("dc%d: failed to init RX ring\n", unit); 224056e5e7aeSMaxime Henrion error = ENXIO; 224156e5e7aeSMaxime Henrion goto fail; 224256e5e7aeSMaxime Henrion } 224356e5e7aeSMaxime Henrion } 224456e5e7aeSMaxime Henrion error = bus_dmamap_create(sc->dc_mtag, 0, &sc->dc_sparemap); 224556e5e7aeSMaxime Henrion if (error) { 224656e5e7aeSMaxime Henrion printf("dc%d: failed to init RX ring\n", unit); 224756e5e7aeSMaxime Henrion error = ENXIO; 224856e5e7aeSMaxime Henrion goto fail; 224956e5e7aeSMaxime Henrion } 225096f2e892SBill Paul 225196f2e892SBill Paul ifp = &sc->arpcom.ac_if; 225296f2e892SBill Paul ifp->if_softc = sc; 22539bf40edeSBrooks Davis if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2254feb78939SJonathan Chen /* XXX: bleah, MTU gets overwritten in ether_ifattach() */ 225596f2e892SBill Paul ifp->if_mtu = ETHERMTU; 225696f2e892SBill Paul ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 225796f2e892SBill Paul ifp->if_ioctl = dc_ioctl; 225896f2e892SBill Paul ifp->if_start = dc_start; 225996f2e892SBill Paul ifp->if_watchdog = dc_watchdog; 226096f2e892SBill Paul ifp->if_init = dc_init; 226196f2e892SBill Paul ifp->if_baudrate = 10000000; 226296f2e892SBill Paul ifp->if_snd.ifq_maxlen = DC_TX_LIST_CNT - 1; 226396f2e892SBill Paul 226496f2e892SBill Paul /* 22655c1cfac4SBill Paul * Do MII setup. If this is a 21143, check for a PHY on the 22665c1cfac4SBill Paul * MII bus after applying any necessary fixups to twiddle the 22675c1cfac4SBill Paul * GPIO bits. If we don't end up finding a PHY, restore the 22685c1cfac4SBill Paul * old selection (SIA only or SIA/SYM) and attach the dcphy 22695c1cfac4SBill Paul * driver instead. 227096f2e892SBill Paul */ 22715c1cfac4SBill Paul if (DC_IS_INTEL(sc)) { 22725c1cfac4SBill Paul dc_apply_fixup(sc, IFM_AUTO); 22735c1cfac4SBill Paul tmp = sc->dc_pmode; 22745c1cfac4SBill Paul sc->dc_pmode = DC_PMODE_MII; 22755c1cfac4SBill Paul } 22765c1cfac4SBill Paul 227796f2e892SBill Paul error = mii_phy_probe(dev, &sc->dc_miibus, 227896f2e892SBill Paul dc_ifmedia_upd, dc_ifmedia_sts); 227996f2e892SBill Paul 228096f2e892SBill Paul if (error && DC_IS_INTEL(sc)) { 22815c1cfac4SBill Paul sc->dc_pmode = tmp; 22825c1cfac4SBill Paul if (sc->dc_pmode != DC_PMODE_SIA) 228396f2e892SBill Paul sc->dc_pmode = DC_PMODE_SYM; 2284042c8f6eSBill Paul sc->dc_flags |= DC_21143_NWAY; 228596f2e892SBill Paul mii_phy_probe(dev, &sc->dc_miibus, 228696f2e892SBill Paul dc_ifmedia_upd, dc_ifmedia_sts); 228778999dd1SBill Paul /* 228878999dd1SBill Paul * For non-MII cards, we need to have the 21143 228978999dd1SBill Paul * drive the LEDs. Except there are some systems 229078999dd1SBill Paul * like the NEC VersaPro NoteBook PC which have no 229178999dd1SBill Paul * LEDs, and twiddling these bits has adverse effects 229278999dd1SBill Paul * on them. (I.e. you suddenly can't get a link.) 229378999dd1SBill Paul */ 229478999dd1SBill Paul if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033) 229578999dd1SBill Paul sc->dc_flags |= DC_TULIP_LEDS; 229696f2e892SBill Paul error = 0; 229796f2e892SBill Paul } 229896f2e892SBill Paul 229996f2e892SBill Paul if (error) { 230096f2e892SBill Paul printf("dc%d: MII without any PHY!\n", sc->dc_unit); 230196f2e892SBill Paul goto fail; 230296f2e892SBill Paul } 230396f2e892SBill Paul 2304feb78939SJonathan Chen if (DC_IS_XIRCOM(sc)) { 2305feb78939SJonathan Chen /* 2306feb78939SJonathan Chen * setup General Purpose Port mode and data so the tulip 2307feb78939SJonathan Chen * can talk to the MII. 2308feb78939SJonathan Chen */ 2309feb78939SJonathan Chen CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2310feb78939SJonathan Chen DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2311feb78939SJonathan Chen DELAY(10); 2312feb78939SJonathan Chen CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2313feb78939SJonathan Chen DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2314feb78939SJonathan Chen DELAY(10); 2315feb78939SJonathan Chen } 2316feb78939SJonathan Chen 2317028a8491SMartin Blapp if (DC_IS_ADMTEK(sc)) { 2318028a8491SMartin Blapp /* 2319028a8491SMartin Blapp * Set automatic TX underrun recovery for the ADMtek chips 2320028a8491SMartin Blapp */ 2321028a8491SMartin Blapp DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); 2322028a8491SMartin Blapp } 2323028a8491SMartin Blapp 232496f2e892SBill Paul /* 2325db40c1aeSDoug Ambrisko * Tell the upper layer(s) we support long frames. 2326db40c1aeSDoug Ambrisko */ 2327db40c1aeSDoug Ambrisko ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 23289ef8b520SSam Leffler ifp->if_capabilities |= IFCAP_VLAN_MTU; 2329db40c1aeSDoug Ambrisko 2330c06eb4e2SSam Leffler callout_init(&sc->dc_stat_ch, IS_MPSAFE ? CALLOUT_MPSAFE : 0); 233196f2e892SBill Paul 23325c1cfac4SBill Paul #ifdef SRM_MEDIA 2333510a809eSMike Smith sc->dc_srm_media = 0; 2334510a809eSMike Smith 2335510a809eSMike Smith /* Remember the SRM console media setting */ 2336510a809eSMike Smith if (DC_IS_INTEL(sc)) { 2337510a809eSMike Smith command = pci_read_config(dev, DC_PCI_CFDD, 4); 2338510a809eSMike Smith command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 2339510a809eSMike Smith switch ((command >> 8) & 0xff) { 2340510a809eSMike Smith case 3: 2341510a809eSMike Smith sc->dc_srm_media = IFM_10_T; 2342510a809eSMike Smith break; 2343510a809eSMike Smith case 4: 2344510a809eSMike Smith sc->dc_srm_media = IFM_10_T | IFM_FDX; 2345510a809eSMike Smith break; 2346510a809eSMike Smith case 5: 2347510a809eSMike Smith sc->dc_srm_media = IFM_100_TX; 2348510a809eSMike Smith break; 2349510a809eSMike Smith case 6: 2350510a809eSMike Smith sc->dc_srm_media = IFM_100_TX | IFM_FDX; 2351510a809eSMike Smith break; 2352510a809eSMike Smith } 2353510a809eSMike Smith if (sc->dc_srm_media) 2354510a809eSMike Smith sc->dc_srm_media |= IFM_ACTIVE | IFM_ETHER; 2355510a809eSMike Smith } 2356510a809eSMike Smith #endif 2357510a809eSMike Smith 2358608654d4SNate Lawson /* 2359608654d4SNate Lawson * Call MI attach routine. 2360608654d4SNate Lawson */ 2361608654d4SNate Lawson ether_ifattach(ifp, eaddr); 2362608654d4SNate Lawson 236354f1f1d1SNate Lawson /* Hook interrupt last to avoid having to lock softc */ 2364608654d4SNate Lawson error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | 2365608654d4SNate Lawson (IS_MPSAFE ? INTR_MPSAFE : 0), 2366608654d4SNate Lawson dc_intr, sc, &sc->dc_intrhand); 2367608654d4SNate Lawson 2368608654d4SNate Lawson if (error) { 2369608654d4SNate Lawson printf("dc%d: couldn't set up irq\n", unit); 2370693f4477SNate Lawson ether_ifdetach(ifp); 237154f1f1d1SNate Lawson goto fail; 2372608654d4SNate Lawson } 2373510a809eSMike Smith 237496f2e892SBill Paul fail: 237554f1f1d1SNate Lawson if (error) 237654f1f1d1SNate Lawson dc_detach(dev); 237796f2e892SBill Paul return (error); 237896f2e892SBill Paul } 237996f2e892SBill Paul 2380693f4477SNate Lawson /* 2381693f4477SNate Lawson * Shutdown hardware and free up resources. This can be called any 2382693f4477SNate Lawson * time after the mutex has been initialized. It is called in both 2383693f4477SNate Lawson * the error case in attach and the normal detach case so it needs 2384693f4477SNate Lawson * to be careful about only freeing resources that have actually been 2385693f4477SNate Lawson * allocated. 2386693f4477SNate Lawson */ 2387e3d2833aSAlfred Perlstein static int 23880934f18aSMaxime Henrion dc_detach(device_t dev) 238996f2e892SBill Paul { 239096f2e892SBill Paul struct dc_softc *sc; 239196f2e892SBill Paul struct ifnet *ifp; 23925c1cfac4SBill Paul struct dc_mediainfo *m; 239356e5e7aeSMaxime Henrion int i; 239496f2e892SBill Paul 239596f2e892SBill Paul sc = device_get_softc(dev); 239659f47d29SJohn Baldwin KASSERT(mtx_initialized(&sc->dc_mtx), ("dc mutex not initialized")); 2397d1ce9105SBill Paul DC_LOCK(sc); 2398d1ce9105SBill Paul 239996f2e892SBill Paul ifp = &sc->arpcom.ac_if; 240096f2e892SBill Paul 2401693f4477SNate Lawson /* These should only be active if attach succeeded */ 2402214073e5SWarner Losh if (device_is_attached(dev)) { 240396f2e892SBill Paul dc_stop(sc); 24049ef8b520SSam Leffler ether_ifdetach(ifp); 2405693f4477SNate Lawson } 2406693f4477SNate Lawson if (sc->dc_miibus) 240796f2e892SBill Paul device_delete_child(dev, sc->dc_miibus); 240854f1f1d1SNate Lawson bus_generic_detach(dev); 240996f2e892SBill Paul 241054f1f1d1SNate Lawson if (sc->dc_intrhand) 241196f2e892SBill Paul bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 241254f1f1d1SNate Lawson if (sc->dc_irq) 241396f2e892SBill Paul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 241454f1f1d1SNate Lawson if (sc->dc_res) 241596f2e892SBill Paul bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 241696f2e892SBill Paul 241756e5e7aeSMaxime Henrion if (sc->dc_cdata.dc_sbuf != NULL) 241856e5e7aeSMaxime Henrion bus_dmamem_free(sc->dc_stag, sc->dc_cdata.dc_sbuf, sc->dc_smap); 241956e5e7aeSMaxime Henrion if (sc->dc_ldata != NULL) 242056e5e7aeSMaxime Henrion bus_dmamem_free(sc->dc_ltag, sc->dc_ldata, sc->dc_lmap); 242156e5e7aeSMaxime Henrion for (i = 0; i < DC_TX_LIST_CNT; i++) 242256e5e7aeSMaxime Henrion bus_dmamap_destroy(sc->dc_mtag, sc->dc_cdata.dc_tx_map[i]); 242356e5e7aeSMaxime Henrion for (i = 0; i < DC_RX_LIST_CNT; i++) 242456e5e7aeSMaxime Henrion bus_dmamap_destroy(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i]); 242556e5e7aeSMaxime Henrion bus_dmamap_destroy(sc->dc_mtag, sc->dc_sparemap); 242656e5e7aeSMaxime Henrion if (sc->dc_stag) 242756e5e7aeSMaxime Henrion bus_dma_tag_destroy(sc->dc_stag); 242856e5e7aeSMaxime Henrion if (sc->dc_mtag) 242956e5e7aeSMaxime Henrion bus_dma_tag_destroy(sc->dc_mtag); 243056e5e7aeSMaxime Henrion if (sc->dc_ltag) 243156e5e7aeSMaxime Henrion bus_dma_tag_destroy(sc->dc_ltag); 243256e5e7aeSMaxime Henrion 243396f2e892SBill Paul free(sc->dc_pnic_rx_buf, M_DEVBUF); 243496f2e892SBill Paul 24355c1cfac4SBill Paul while (sc->dc_mi != NULL) { 24365c1cfac4SBill Paul m = sc->dc_mi->dc_next; 24375c1cfac4SBill Paul free(sc->dc_mi, M_DEVBUF); 24385c1cfac4SBill Paul sc->dc_mi = m; 24395c1cfac4SBill Paul } 24407efff076SWarner Losh free(sc->dc_srom, M_DEVBUF); 24415c1cfac4SBill Paul 2442d1ce9105SBill Paul DC_UNLOCK(sc); 2443d1ce9105SBill Paul mtx_destroy(&sc->dc_mtx); 244496f2e892SBill Paul 244596f2e892SBill Paul return (0); 244696f2e892SBill Paul } 244796f2e892SBill Paul 244896f2e892SBill Paul /* 244996f2e892SBill Paul * Initialize the transmit descriptors. 245096f2e892SBill Paul */ 2451e3d2833aSAlfred Perlstein static int 24520934f18aSMaxime Henrion dc_list_tx_init(struct dc_softc *sc) 245396f2e892SBill Paul { 245496f2e892SBill Paul struct dc_chain_data *cd; 245596f2e892SBill Paul struct dc_list_data *ld; 245601faf54bSLuigi Rizzo int i, nexti; 245796f2e892SBill Paul 245896f2e892SBill Paul cd = &sc->dc_cdata; 245996f2e892SBill Paul ld = sc->dc_ldata; 246096f2e892SBill Paul for (i = 0; i < DC_TX_LIST_CNT; i++) { 2461b3811c95SMaxime Henrion if (i == DC_TX_LIST_CNT - 1) 2462b3811c95SMaxime Henrion nexti = 0; 2463b3811c95SMaxime Henrion else 2464b3811c95SMaxime Henrion nexti = i + 1; 2465af4358c7SMaxime Henrion ld->dc_tx_list[i].dc_next = htole32(DC_TXDESC(sc, nexti)); 246696f2e892SBill Paul cd->dc_tx_chain[i] = NULL; 246796f2e892SBill Paul ld->dc_tx_list[i].dc_data = 0; 246896f2e892SBill Paul ld->dc_tx_list[i].dc_ctl = 0; 246996f2e892SBill Paul } 247096f2e892SBill Paul 247196f2e892SBill Paul cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 247256e5e7aeSMaxime Henrion bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 247356e5e7aeSMaxime Henrion BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 247496f2e892SBill Paul return (0); 247596f2e892SBill Paul } 247696f2e892SBill Paul 247796f2e892SBill Paul 247896f2e892SBill Paul /* 247996f2e892SBill Paul * Initialize the RX descriptors and allocate mbufs for them. Note that 248096f2e892SBill Paul * we arrange the descriptors in a closed ring, so that the last descriptor 248196f2e892SBill Paul * points back to the first. 248296f2e892SBill Paul */ 2483e3d2833aSAlfred Perlstein static int 24840934f18aSMaxime Henrion dc_list_rx_init(struct dc_softc *sc) 248596f2e892SBill Paul { 248696f2e892SBill Paul struct dc_chain_data *cd; 248796f2e892SBill Paul struct dc_list_data *ld; 248801faf54bSLuigi Rizzo int i, nexti; 248996f2e892SBill Paul 249096f2e892SBill Paul cd = &sc->dc_cdata; 249196f2e892SBill Paul ld = sc->dc_ldata; 249296f2e892SBill Paul 249396f2e892SBill Paul for (i = 0; i < DC_RX_LIST_CNT; i++) { 249456e5e7aeSMaxime Henrion if (dc_newbuf(sc, i, 1) != 0) 249596f2e892SBill Paul return (ENOBUFS); 2496b3811c95SMaxime Henrion if (i == DC_RX_LIST_CNT - 1) 2497b3811c95SMaxime Henrion nexti = 0; 2498b3811c95SMaxime Henrion else 2499b3811c95SMaxime Henrion nexti = i + 1; 2500af4358c7SMaxime Henrion ld->dc_rx_list[i].dc_next = htole32(DC_RXDESC(sc, nexti)); 250196f2e892SBill Paul } 250296f2e892SBill Paul 250396f2e892SBill Paul cd->dc_rx_prod = 0; 250456e5e7aeSMaxime Henrion bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 250556e5e7aeSMaxime Henrion BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 250696f2e892SBill Paul return (0); 250796f2e892SBill Paul } 250896f2e892SBill Paul 250956e5e7aeSMaxime Henrion static void 251056e5e7aeSMaxime Henrion dc_dma_map_rxbuf(arg, segs, nseg, mapsize, error) 251156e5e7aeSMaxime Henrion void *arg; 251256e5e7aeSMaxime Henrion bus_dma_segment_t *segs; 251356e5e7aeSMaxime Henrion int nseg; 251456e5e7aeSMaxime Henrion bus_size_t mapsize; 251556e5e7aeSMaxime Henrion int error; 251656e5e7aeSMaxime Henrion { 251756e5e7aeSMaxime Henrion struct dc_softc *sc; 251856e5e7aeSMaxime Henrion struct dc_desc *c; 251956e5e7aeSMaxime Henrion 252056e5e7aeSMaxime Henrion sc = arg; 252156e5e7aeSMaxime Henrion c = &sc->dc_ldata->dc_rx_list[sc->dc_cdata.dc_rx_cur]; 252256e5e7aeSMaxime Henrion if (error) { 252356e5e7aeSMaxime Henrion sc->dc_cdata.dc_rx_err = error; 252456e5e7aeSMaxime Henrion return; 252556e5e7aeSMaxime Henrion } 252656e5e7aeSMaxime Henrion 252756e5e7aeSMaxime Henrion KASSERT(nseg == 1, ("wrong number of segments, should be 1")); 252856e5e7aeSMaxime Henrion sc->dc_cdata.dc_rx_err = 0; 2529af4358c7SMaxime Henrion c->dc_data = htole32(segs->ds_addr); 253056e5e7aeSMaxime Henrion } 253156e5e7aeSMaxime Henrion 253296f2e892SBill Paul /* 253396f2e892SBill Paul * Initialize an RX descriptor and attach an MBUF cluster. 253496f2e892SBill Paul */ 2535e3d2833aSAlfred Perlstein static int 253656e5e7aeSMaxime Henrion dc_newbuf(struct dc_softc *sc, int i, int alloc) 253796f2e892SBill Paul { 253856e5e7aeSMaxime Henrion struct mbuf *m_new; 253956e5e7aeSMaxime Henrion bus_dmamap_t tmp; 254056e5e7aeSMaxime Henrion int error; 254196f2e892SBill Paul 254256e5e7aeSMaxime Henrion if (alloc) { 254356e5e7aeSMaxime Henrion m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 254440129585SLuigi Rizzo if (m_new == NULL) 254596f2e892SBill Paul return (ENOBUFS); 254696f2e892SBill Paul } else { 254756e5e7aeSMaxime Henrion m_new = sc->dc_cdata.dc_rx_chain[i]; 254896f2e892SBill Paul m_new->m_data = m_new->m_ext.ext_buf; 254996f2e892SBill Paul } 255056e5e7aeSMaxime Henrion m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 255196f2e892SBill Paul m_adj(m_new, sizeof(u_int64_t)); 255296f2e892SBill Paul 255396f2e892SBill Paul /* 255496f2e892SBill Paul * If this is a PNIC chip, zero the buffer. This is part 255596f2e892SBill Paul * of the workaround for the receive bug in the 82c168 and 255696f2e892SBill Paul * 82c169 chips. 255796f2e892SBill Paul */ 255896f2e892SBill Paul if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 25590934f18aSMaxime Henrion bzero(mtod(m_new, char *), m_new->m_len); 256096f2e892SBill Paul 256156e5e7aeSMaxime Henrion /* No need to remap the mbuf if we're reusing it. */ 256256e5e7aeSMaxime Henrion if (alloc) { 256356e5e7aeSMaxime Henrion sc->dc_cdata.dc_rx_cur = i; 256456e5e7aeSMaxime Henrion error = bus_dmamap_load_mbuf(sc->dc_mtag, sc->dc_sparemap, 256556e5e7aeSMaxime Henrion m_new, dc_dma_map_rxbuf, sc, 0); 256656e5e7aeSMaxime Henrion if (error) { 256756e5e7aeSMaxime Henrion m_freem(m_new); 256856e5e7aeSMaxime Henrion return (error); 256956e5e7aeSMaxime Henrion } 257056e5e7aeSMaxime Henrion if (sc->dc_cdata.dc_rx_err != 0) { 257156e5e7aeSMaxime Henrion m_freem(m_new); 257256e5e7aeSMaxime Henrion return (sc->dc_cdata.dc_rx_err); 257356e5e7aeSMaxime Henrion } 257456e5e7aeSMaxime Henrion bus_dmamap_unload(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i]); 257556e5e7aeSMaxime Henrion tmp = sc->dc_cdata.dc_rx_map[i]; 257656e5e7aeSMaxime Henrion sc->dc_cdata.dc_rx_map[i] = sc->dc_sparemap; 257756e5e7aeSMaxime Henrion sc->dc_sparemap = tmp; 257896f2e892SBill Paul sc->dc_cdata.dc_rx_chain[i] = m_new; 257956e5e7aeSMaxime Henrion } 258096f2e892SBill Paul 2581af4358c7SMaxime Henrion sc->dc_ldata->dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN); 2582af4358c7SMaxime Henrion sc->dc_ldata->dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN); 258356e5e7aeSMaxime Henrion bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i], 258456e5e7aeSMaxime Henrion BUS_DMASYNC_PREREAD); 258556e5e7aeSMaxime Henrion bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 258656e5e7aeSMaxime Henrion BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 258796f2e892SBill Paul return (0); 258896f2e892SBill Paul } 258996f2e892SBill Paul 259096f2e892SBill Paul /* 259196f2e892SBill Paul * Grrrrr. 259296f2e892SBill Paul * The PNIC chip has a terrible bug in it that manifests itself during 259396f2e892SBill Paul * periods of heavy activity. The exact mode of failure if difficult to 259496f2e892SBill Paul * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 259596f2e892SBill Paul * will happen on slow machines. The bug is that sometimes instead of 259696f2e892SBill Paul * uploading one complete frame during reception, it uploads what looks 259796f2e892SBill Paul * like the entire contents of its FIFO memory. The frame we want is at 259896f2e892SBill Paul * the end of the whole mess, but we never know exactly how much data has 259996f2e892SBill Paul * been uploaded, so salvaging the frame is hard. 260096f2e892SBill Paul * 260196f2e892SBill Paul * There is only one way to do it reliably, and it's disgusting. 260296f2e892SBill Paul * Here's what we know: 260396f2e892SBill Paul * 260496f2e892SBill Paul * - We know there will always be somewhere between one and three extra 260596f2e892SBill Paul * descriptors uploaded. 260696f2e892SBill Paul * 260796f2e892SBill Paul * - We know the desired received frame will always be at the end of the 260896f2e892SBill Paul * total data upload. 260996f2e892SBill Paul * 261096f2e892SBill Paul * - We know the size of the desired received frame because it will be 261196f2e892SBill Paul * provided in the length field of the status word in the last descriptor. 261296f2e892SBill Paul * 261396f2e892SBill Paul * Here's what we do: 261496f2e892SBill Paul * 261596f2e892SBill Paul * - When we allocate buffers for the receive ring, we bzero() them. 261696f2e892SBill Paul * This means that we know that the buffer contents should be all 261796f2e892SBill Paul * zeros, except for data uploaded by the chip. 261896f2e892SBill Paul * 261996f2e892SBill Paul * - We also force the PNIC chip to upload frames that include the 262096f2e892SBill Paul * ethernet CRC at the end. 262196f2e892SBill Paul * 262296f2e892SBill Paul * - We gather all of the bogus frame data into a single buffer. 262396f2e892SBill Paul * 262496f2e892SBill Paul * - We then position a pointer at the end of this buffer and scan 262596f2e892SBill Paul * backwards until we encounter the first non-zero byte of data. 262696f2e892SBill Paul * This is the end of the received frame. We know we will encounter 262796f2e892SBill Paul * some data at the end of the frame because the CRC will always be 262896f2e892SBill Paul * there, so even if the sender transmits a packet of all zeros, 262996f2e892SBill Paul * we won't be fooled. 263096f2e892SBill Paul * 263196f2e892SBill Paul * - We know the size of the actual received frame, so we subtract 263296f2e892SBill Paul * that value from the current pointer location. This brings us 263396f2e892SBill Paul * to the start of the actual received packet. 263496f2e892SBill Paul * 263596f2e892SBill Paul * - We copy this into an mbuf and pass it on, along with the actual 263696f2e892SBill Paul * frame length. 263796f2e892SBill Paul * 263896f2e892SBill Paul * The performance hit is tremendous, but it beats dropping frames all 263996f2e892SBill Paul * the time. 264096f2e892SBill Paul */ 264196f2e892SBill Paul 264296f2e892SBill Paul #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG | DC_RXSTAT_LASTFRAG) 2643e3d2833aSAlfred Perlstein static void 26440934f18aSMaxime Henrion dc_pnic_rx_bug_war(struct dc_softc *sc, int idx) 264596f2e892SBill Paul { 264696f2e892SBill Paul struct dc_desc *cur_rx; 264796f2e892SBill Paul struct dc_desc *c = NULL; 264896f2e892SBill Paul struct mbuf *m = NULL; 264996f2e892SBill Paul unsigned char *ptr; 265096f2e892SBill Paul int i, total_len; 265196f2e892SBill Paul u_int32_t rxstat = 0; 265296f2e892SBill Paul 265396f2e892SBill Paul i = sc->dc_pnic_rx_bug_save; 265496f2e892SBill Paul cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 265596f2e892SBill Paul ptr = sc->dc_pnic_rx_buf; 26561edc4c46SMaxime Henrion bzero(ptr, DC_RXLEN * 5); 265796f2e892SBill Paul 265896f2e892SBill Paul /* Copy all the bytes from the bogus buffers. */ 265996f2e892SBill Paul while (1) { 266096f2e892SBill Paul c = &sc->dc_ldata->dc_rx_list[i]; 2661af4358c7SMaxime Henrion rxstat = le32toh(c->dc_status); 266296f2e892SBill Paul m = sc->dc_cdata.dc_rx_chain[i]; 266396f2e892SBill Paul bcopy(mtod(m, char *), ptr, DC_RXLEN); 266496f2e892SBill Paul ptr += DC_RXLEN; 266596f2e892SBill Paul /* If this is the last buffer, break out. */ 266696f2e892SBill Paul if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 266796f2e892SBill Paul break; 266856e5e7aeSMaxime Henrion dc_newbuf(sc, i, 0); 266996f2e892SBill Paul DC_INC(i, DC_RX_LIST_CNT); 267096f2e892SBill Paul } 267196f2e892SBill Paul 267296f2e892SBill Paul /* Find the length of the actual receive frame. */ 267396f2e892SBill Paul total_len = DC_RXBYTES(rxstat); 267496f2e892SBill Paul 267596f2e892SBill Paul /* Scan backwards until we hit a non-zero byte. */ 267696f2e892SBill Paul while (*ptr == 0x00) 267796f2e892SBill Paul ptr--; 267896f2e892SBill Paul 267996f2e892SBill Paul /* Round off. */ 268096f2e892SBill Paul if ((uintptr_t)(ptr) & 0x3) 268196f2e892SBill Paul ptr -= 1; 268296f2e892SBill Paul 268396f2e892SBill Paul /* Now find the start of the frame. */ 268496f2e892SBill Paul ptr -= total_len; 268596f2e892SBill Paul if (ptr < sc->dc_pnic_rx_buf) 268696f2e892SBill Paul ptr = sc->dc_pnic_rx_buf; 268796f2e892SBill Paul 268896f2e892SBill Paul /* 268996f2e892SBill Paul * Now copy the salvaged frame to the last mbuf and fake up 269096f2e892SBill Paul * the status word to make it look like a successful 269196f2e892SBill Paul * frame reception. 269296f2e892SBill Paul */ 269356e5e7aeSMaxime Henrion dc_newbuf(sc, i, 0); 269496f2e892SBill Paul bcopy(ptr, mtod(m, char *), total_len); 2695af4358c7SMaxime Henrion cur_rx->dc_status = htole32(rxstat | DC_RXSTAT_FIRSTFRAG); 269696f2e892SBill Paul } 269796f2e892SBill Paul 269896f2e892SBill Paul /* 269973bf949cSBill Paul * This routine searches the RX ring for dirty descriptors in the 270073bf949cSBill Paul * event that the rxeof routine falls out of sync with the chip's 270173bf949cSBill Paul * current descriptor pointer. This may happen sometimes as a result 270273bf949cSBill Paul * of a "no RX buffer available" condition that happens when the chip 270373bf949cSBill Paul * consumes all of the RX buffers before the driver has a chance to 270473bf949cSBill Paul * process the RX ring. This routine may need to be called more than 270573bf949cSBill Paul * once to bring the driver back in sync with the chip, however we 270673bf949cSBill Paul * should still be getting RX DONE interrupts to drive the search 270773bf949cSBill Paul * for new packets in the RX ring, so we should catch up eventually. 270873bf949cSBill Paul */ 2709e3d2833aSAlfred Perlstein static int 27100934f18aSMaxime Henrion dc_rx_resync(struct dc_softc *sc) 271173bf949cSBill Paul { 271273bf949cSBill Paul struct dc_desc *cur_rx; 27130934f18aSMaxime Henrion int i, pos; 271473bf949cSBill Paul 271573bf949cSBill Paul pos = sc->dc_cdata.dc_rx_prod; 271673bf949cSBill Paul 271773bf949cSBill Paul for (i = 0; i < DC_RX_LIST_CNT; i++) { 271873bf949cSBill Paul cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2719af4358c7SMaxime Henrion if (!(le32toh(cur_rx->dc_status) & DC_RXSTAT_OWN)) 272073bf949cSBill Paul break; 272173bf949cSBill Paul DC_INC(pos, DC_RX_LIST_CNT); 272273bf949cSBill Paul } 272373bf949cSBill Paul 272473bf949cSBill Paul /* If the ring really is empty, then just return. */ 272573bf949cSBill Paul if (i == DC_RX_LIST_CNT) 272673bf949cSBill Paul return (0); 272773bf949cSBill Paul 272873bf949cSBill Paul /* We've fallen behing the chip: catch it. */ 272973bf949cSBill Paul sc->dc_cdata.dc_rx_prod = pos; 273073bf949cSBill Paul 273173bf949cSBill Paul return (EAGAIN); 273273bf949cSBill Paul } 273373bf949cSBill Paul 273473bf949cSBill Paul /* 273596f2e892SBill Paul * A frame has been uploaded: pass the resulting mbuf chain up to 273696f2e892SBill Paul * the higher level protocols. 273796f2e892SBill Paul */ 2738e3d2833aSAlfred Perlstein static void 27390934f18aSMaxime Henrion dc_rxeof(struct dc_softc *sc) 274096f2e892SBill Paul { 274196f2e892SBill Paul struct mbuf *m; 274296f2e892SBill Paul struct ifnet *ifp; 274396f2e892SBill Paul struct dc_desc *cur_rx; 274496f2e892SBill Paul int i, total_len = 0; 274596f2e892SBill Paul u_int32_t rxstat; 274696f2e892SBill Paul 27475120abbfSSam Leffler DC_LOCK_ASSERT(sc); 27485120abbfSSam Leffler 274996f2e892SBill Paul ifp = &sc->arpcom.ac_if; 275096f2e892SBill Paul i = sc->dc_cdata.dc_rx_prod; 275196f2e892SBill Paul 275256e5e7aeSMaxime Henrion bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD); 2753af4358c7SMaxime Henrion while (!(le32toh(sc->dc_ldata->dc_rx_list[i].dc_status) & 2754af4358c7SMaxime Henrion DC_RXSTAT_OWN)) { 2755e4fc250cSLuigi Rizzo #ifdef DEVICE_POLLING 275662f76486SMaxim Sobolev if (ifp->if_flags & IFF_POLLING) { 2757e4fc250cSLuigi Rizzo if (sc->rxcycles <= 0) 2758e4fc250cSLuigi Rizzo break; 2759e4fc250cSLuigi Rizzo sc->rxcycles--; 2760e4fc250cSLuigi Rizzo } 27610934f18aSMaxime Henrion #endif 276296f2e892SBill Paul cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2763af4358c7SMaxime Henrion rxstat = le32toh(cur_rx->dc_status); 276496f2e892SBill Paul m = sc->dc_cdata.dc_rx_chain[i]; 276556e5e7aeSMaxime Henrion bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i], 276656e5e7aeSMaxime Henrion BUS_DMASYNC_POSTREAD); 276796f2e892SBill Paul total_len = DC_RXBYTES(rxstat); 276896f2e892SBill Paul 276996f2e892SBill Paul if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 277096f2e892SBill Paul if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 277196f2e892SBill Paul if (rxstat & DC_RXSTAT_FIRSTFRAG) 277296f2e892SBill Paul sc->dc_pnic_rx_bug_save = i; 277396f2e892SBill Paul if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 277496f2e892SBill Paul DC_INC(i, DC_RX_LIST_CNT); 277596f2e892SBill Paul continue; 277696f2e892SBill Paul } 277796f2e892SBill Paul dc_pnic_rx_bug_war(sc, i); 2778af4358c7SMaxime Henrion rxstat = le32toh(cur_rx->dc_status); 277996f2e892SBill Paul total_len = DC_RXBYTES(rxstat); 278096f2e892SBill Paul } 278196f2e892SBill Paul } 278296f2e892SBill Paul 278396f2e892SBill Paul /* 278496f2e892SBill Paul * If an error occurs, update stats, clear the 278596f2e892SBill Paul * status word and leave the mbuf cluster in place: 278696f2e892SBill Paul * it should simply get re-used next time this descriptor 2787db40c1aeSDoug Ambrisko * comes up in the ring. However, don't report long 27880934f18aSMaxime Henrion * frames as errors since they could be vlans. 278996f2e892SBill Paul */ 2790db40c1aeSDoug Ambrisko if ((rxstat & DC_RXSTAT_RXERR)) { 2791db40c1aeSDoug Ambrisko if (!(rxstat & DC_RXSTAT_GIANT) || 2792db40c1aeSDoug Ambrisko (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2793db40c1aeSDoug Ambrisko DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2794db40c1aeSDoug Ambrisko DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 279596f2e892SBill Paul ifp->if_ierrors++; 279696f2e892SBill Paul if (rxstat & DC_RXSTAT_COLLSEEN) 279796f2e892SBill Paul ifp->if_collisions++; 279856e5e7aeSMaxime Henrion dc_newbuf(sc, i, 0); 279996f2e892SBill Paul if (rxstat & DC_RXSTAT_CRCERR) { 280096f2e892SBill Paul DC_INC(i, DC_RX_LIST_CNT); 280196f2e892SBill Paul continue; 280296f2e892SBill Paul } else { 280396f2e892SBill Paul dc_init(sc); 280496f2e892SBill Paul return; 280596f2e892SBill Paul } 280696f2e892SBill Paul } 2807db40c1aeSDoug Ambrisko } 280896f2e892SBill Paul 280996f2e892SBill Paul /* No errors; receive the packet. */ 281096f2e892SBill Paul total_len -= ETHER_CRC_LEN; 281101faf54bSLuigi Rizzo #ifdef __i386__ 281201faf54bSLuigi Rizzo /* 281301faf54bSLuigi Rizzo * On the x86 we do not have alignment problems, so try to 281401faf54bSLuigi Rizzo * allocate a new buffer for the receive ring, and pass up 281501faf54bSLuigi Rizzo * the one where the packet is already, saving the expensive 281601faf54bSLuigi Rizzo * copy done in m_devget(). 281701faf54bSLuigi Rizzo * If we are on an architecture with alignment problems, or 281801faf54bSLuigi Rizzo * if the allocation fails, then use m_devget and leave the 281901faf54bSLuigi Rizzo * existing buffer in the receive ring. 282001faf54bSLuigi Rizzo */ 282156e5e7aeSMaxime Henrion if (dc_quick && dc_newbuf(sc, i, 1) == 0) { 282201faf54bSLuigi Rizzo m->m_pkthdr.rcvif = ifp; 282301faf54bSLuigi Rizzo m->m_pkthdr.len = m->m_len = total_len; 282401faf54bSLuigi Rizzo DC_INC(i, DC_RX_LIST_CNT); 282501faf54bSLuigi Rizzo } else 282601faf54bSLuigi Rizzo #endif 282701faf54bSLuigi Rizzo { 282801faf54bSLuigi Rizzo struct mbuf *m0; 282996f2e892SBill Paul 283001faf54bSLuigi Rizzo m0 = m_devget(mtod(m, char *), total_len, 283101faf54bSLuigi Rizzo ETHER_ALIGN, ifp, NULL); 283256e5e7aeSMaxime Henrion dc_newbuf(sc, i, 0); 283396f2e892SBill Paul DC_INC(i, DC_RX_LIST_CNT); 283496f2e892SBill Paul if (m0 == NULL) { 283596f2e892SBill Paul ifp->if_ierrors++; 283696f2e892SBill Paul continue; 283796f2e892SBill Paul } 283896f2e892SBill Paul m = m0; 283901faf54bSLuigi Rizzo } 284096f2e892SBill Paul 284196f2e892SBill Paul ifp->if_ipackets++; 28425120abbfSSam Leffler DC_UNLOCK(sc); 28439ef8b520SSam Leffler (*ifp->if_input)(ifp, m); 28445120abbfSSam Leffler DC_LOCK(sc); 284596f2e892SBill Paul } 284696f2e892SBill Paul 284796f2e892SBill Paul sc->dc_cdata.dc_rx_prod = i; 284896f2e892SBill Paul } 284996f2e892SBill Paul 285096f2e892SBill Paul /* 285196f2e892SBill Paul * A frame was downloaded to the chip. It's safe for us to clean up 285296f2e892SBill Paul * the list buffers. 285396f2e892SBill Paul */ 285496f2e892SBill Paul 2855e3d2833aSAlfred Perlstein static void 28560934f18aSMaxime Henrion dc_txeof(struct dc_softc *sc) 285796f2e892SBill Paul { 285896f2e892SBill Paul struct dc_desc *cur_tx = NULL; 285996f2e892SBill Paul struct ifnet *ifp; 286096f2e892SBill Paul int idx; 2861af4358c7SMaxime Henrion u_int32_t ctl, txstat; 286296f2e892SBill Paul 286396f2e892SBill Paul ifp = &sc->arpcom.ac_if; 286496f2e892SBill Paul 286596f2e892SBill Paul /* 286696f2e892SBill Paul * Go through our tx list and free mbufs for those 286796f2e892SBill Paul * frames that have been transmitted. 286896f2e892SBill Paul */ 286956e5e7aeSMaxime Henrion bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD); 287096f2e892SBill Paul idx = sc->dc_cdata.dc_tx_cons; 287196f2e892SBill Paul while (idx != sc->dc_cdata.dc_tx_prod) { 287296f2e892SBill Paul 287396f2e892SBill Paul cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2874af4358c7SMaxime Henrion txstat = le32toh(cur_tx->dc_status); 2875af4358c7SMaxime Henrion ctl = le32toh(cur_tx->dc_ctl); 287696f2e892SBill Paul 287796f2e892SBill Paul if (txstat & DC_TXSTAT_OWN) 287896f2e892SBill Paul break; 287996f2e892SBill Paul 28804ff4a9beSDon Lewis if (!(ctl & DC_TXCTL_LASTFRAG) || ctl & DC_TXCTL_SETUP) { 2881af4358c7SMaxime Henrion if (ctl & DC_TXCTL_SETUP) { 288296f2e892SBill Paul /* 288396f2e892SBill Paul * Yes, the PNIC is so brain damaged 288496f2e892SBill Paul * that it will sometimes generate a TX 288596f2e892SBill Paul * underrun error while DMAing the RX 288696f2e892SBill Paul * filter setup frame. If we detect this, 288796f2e892SBill Paul * we have to send the setup frame again, 288896f2e892SBill Paul * or else the filter won't be programmed 288996f2e892SBill Paul * correctly. 289096f2e892SBill Paul */ 289196f2e892SBill Paul if (DC_IS_PNIC(sc)) { 289296f2e892SBill Paul if (txstat & DC_TXSTAT_ERRSUM) 289396f2e892SBill Paul dc_setfilt(sc); 289496f2e892SBill Paul } 289596f2e892SBill Paul sc->dc_cdata.dc_tx_chain[idx] = NULL; 289696f2e892SBill Paul } 2897bcb9ef4fSLuigi Rizzo sc->dc_cdata.dc_tx_cnt--; 289896f2e892SBill Paul DC_INC(idx, DC_TX_LIST_CNT); 289996f2e892SBill Paul continue; 290096f2e892SBill Paul } 290196f2e892SBill Paul 290229a2220aSBill Paul if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) { 2903feb78939SJonathan Chen /* 2904feb78939SJonathan Chen * XXX: Why does my Xircom taunt me so? 2905feb78939SJonathan Chen * For some reason it likes setting the CARRLOST flag 290629a2220aSBill Paul * even when the carrier is there. wtf?!? 290729a2220aSBill Paul * Who knows, but Conexant chips have the 290829a2220aSBill Paul * same problem. Maybe they took lessons 290929a2220aSBill Paul * from Xircom. 291029a2220aSBill Paul */ 2911feb78939SJonathan Chen if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2912feb78939SJonathan Chen sc->dc_pmode == DC_PMODE_MII && 2913feb78939SJonathan Chen ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 2914feb78939SJonathan Chen DC_TXSTAT_NOCARRIER))) 2915feb78939SJonathan Chen txstat &= ~DC_TXSTAT_ERRSUM; 2916feb78939SJonathan Chen } else { 291796f2e892SBill Paul if (/*sc->dc_type == DC_TYPE_21143 &&*/ 291896f2e892SBill Paul sc->dc_pmode == DC_PMODE_MII && 291996f2e892SBill Paul ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 292096f2e892SBill Paul DC_TXSTAT_NOCARRIER | DC_TXSTAT_CARRLOST))) 292196f2e892SBill Paul txstat &= ~DC_TXSTAT_ERRSUM; 2922feb78939SJonathan Chen } 292396f2e892SBill Paul 292496f2e892SBill Paul if (txstat & DC_TXSTAT_ERRSUM) { 292596f2e892SBill Paul ifp->if_oerrors++; 292696f2e892SBill Paul if (txstat & DC_TXSTAT_EXCESSCOLL) 292796f2e892SBill Paul ifp->if_collisions++; 292896f2e892SBill Paul if (txstat & DC_TXSTAT_LATECOLL) 292996f2e892SBill Paul ifp->if_collisions++; 293096f2e892SBill Paul if (!(txstat & DC_TXSTAT_UNDERRUN)) { 293196f2e892SBill Paul dc_init(sc); 293296f2e892SBill Paul return; 293396f2e892SBill Paul } 293496f2e892SBill Paul } 293596f2e892SBill Paul 293696f2e892SBill Paul ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 293796f2e892SBill Paul 293896f2e892SBill Paul ifp->if_opackets++; 293996f2e892SBill Paul if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 294056e5e7aeSMaxime Henrion bus_dmamap_sync(sc->dc_mtag, 294156e5e7aeSMaxime Henrion sc->dc_cdata.dc_tx_map[idx], 294256e5e7aeSMaxime Henrion BUS_DMASYNC_POSTWRITE); 294356e5e7aeSMaxime Henrion bus_dmamap_unload(sc->dc_mtag, 294456e5e7aeSMaxime Henrion sc->dc_cdata.dc_tx_map[idx]); 294596f2e892SBill Paul m_freem(sc->dc_cdata.dc_tx_chain[idx]); 294696f2e892SBill Paul sc->dc_cdata.dc_tx_chain[idx] = NULL; 294796f2e892SBill Paul } 294896f2e892SBill Paul 294996f2e892SBill Paul sc->dc_cdata.dc_tx_cnt--; 295096f2e892SBill Paul DC_INC(idx, DC_TX_LIST_CNT); 295196f2e892SBill Paul } 295296f2e892SBill Paul 2953bcb9ef4fSLuigi Rizzo if (idx != sc->dc_cdata.dc_tx_cons) { 29540934f18aSMaxime Henrion /* Some buffers have been freed. */ 295596f2e892SBill Paul sc->dc_cdata.dc_tx_cons = idx; 295696f2e892SBill Paul ifp->if_flags &= ~IFF_OACTIVE; 2957bcb9ef4fSLuigi Rizzo } 2958bcb9ef4fSLuigi Rizzo ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5; 295996f2e892SBill Paul } 296096f2e892SBill Paul 2961e3d2833aSAlfred Perlstein static void 29620934f18aSMaxime Henrion dc_tick(void *xsc) 296396f2e892SBill Paul { 296496f2e892SBill Paul struct dc_softc *sc; 296596f2e892SBill Paul struct mii_data *mii; 296696f2e892SBill Paul struct ifnet *ifp; 296796f2e892SBill Paul u_int32_t r; 296896f2e892SBill Paul 296996f2e892SBill Paul sc = xsc; 2970d1ce9105SBill Paul DC_LOCK(sc); 297196f2e892SBill Paul ifp = &sc->arpcom.ac_if; 297296f2e892SBill Paul mii = device_get_softc(sc->dc_miibus); 297396f2e892SBill Paul 297496f2e892SBill Paul if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2975318b02fdSBill Paul if (sc->dc_flags & DC_21143_NWAY) { 2976318b02fdSBill Paul r = CSR_READ_4(sc, DC_10BTSTAT); 2977318b02fdSBill Paul if (IFM_SUBTYPE(mii->mii_media_active) == 2978318b02fdSBill Paul IFM_100_TX && (r & DC_TSTAT_LS100)) { 297996f2e892SBill Paul sc->dc_link = 0; 2980318b02fdSBill Paul mii_mediachg(mii); 2981318b02fdSBill Paul } 2982318b02fdSBill Paul if (IFM_SUBTYPE(mii->mii_media_active) == 2983318b02fdSBill Paul IFM_10_T && (r & DC_TSTAT_LS10)) { 2984318b02fdSBill Paul sc->dc_link = 0; 2985318b02fdSBill Paul mii_mediachg(mii); 2986318b02fdSBill Paul } 2987d675147eSBill Paul if (sc->dc_link == 0) 298896f2e892SBill Paul mii_tick(mii); 298996f2e892SBill Paul } else { 2990318b02fdSBill Paul r = CSR_READ_4(sc, DC_ISR); 299196f2e892SBill Paul if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2992259b8d84SMartin Blapp sc->dc_cdata.dc_tx_cnt == 0) { 299396f2e892SBill Paul mii_tick(mii); 2994042c8f6eSBill Paul if (!(mii->mii_media_status & IFM_ACTIVE)) 2995042c8f6eSBill Paul sc->dc_link = 0; 299696f2e892SBill Paul } 2997259b8d84SMartin Blapp } 299896f2e892SBill Paul } else 299996f2e892SBill Paul mii_tick(mii); 300096f2e892SBill Paul 300196f2e892SBill Paul /* 300296f2e892SBill Paul * When the init routine completes, we expect to be able to send 300396f2e892SBill Paul * packets right away, and in fact the network code will send a 300496f2e892SBill Paul * gratuitous ARP the moment the init routine marks the interface 300596f2e892SBill Paul * as running. However, even though the MAC may have been initialized, 300696f2e892SBill Paul * there may be a delay of a few seconds before the PHY completes 300796f2e892SBill Paul * autonegotiation and the link is brought up. Any transmissions 300896f2e892SBill Paul * made during that delay will be lost. Dealing with this is tricky: 300996f2e892SBill Paul * we can't just pause in the init routine while waiting for the 301096f2e892SBill Paul * PHY to come ready since that would bring the whole system to 301196f2e892SBill Paul * a screeching halt for several seconds. 301296f2e892SBill Paul * 301396f2e892SBill Paul * What we do here is prevent the TX start routine from sending 301496f2e892SBill Paul * any packets until a link has been established. After the 301596f2e892SBill Paul * interface has been initialized, the tick routine will poll 301696f2e892SBill Paul * the state of the PHY until the IFM_ACTIVE flag is set. Until 301796f2e892SBill Paul * that time, packets will stay in the send queue, and once the 301896f2e892SBill Paul * link comes up, they will be flushed out to the wire. 301996f2e892SBill Paul */ 3020cd62a9cbSJonathan Lemon if (!sc->dc_link && mii->mii_media_status & IFM_ACTIVE && 302196f2e892SBill Paul IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 302296f2e892SBill Paul sc->dc_link++; 302396f2e892SBill Paul if (ifp->if_snd.ifq_head != NULL) 302496f2e892SBill Paul dc_start(ifp); 302596f2e892SBill Paul } 302696f2e892SBill Paul 3027318b02fdSBill Paul if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 3028b50c6312SJonathan Lemon callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3029318b02fdSBill Paul else 3030b50c6312SJonathan Lemon callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 303196f2e892SBill Paul 3032d1ce9105SBill Paul DC_UNLOCK(sc); 303396f2e892SBill Paul } 303496f2e892SBill Paul 3035d467c136SBill Paul /* 3036d467c136SBill Paul * A transmit underrun has occurred. Back off the transmit threshold, 3037d467c136SBill Paul * or switch to store and forward mode if we have to. 3038d467c136SBill Paul */ 3039e3d2833aSAlfred Perlstein static void 30400934f18aSMaxime Henrion dc_tx_underrun(struct dc_softc *sc) 3041d467c136SBill Paul { 3042d467c136SBill Paul u_int32_t isr; 3043d467c136SBill Paul int i; 3044d467c136SBill Paul 3045d467c136SBill Paul if (DC_IS_DAVICOM(sc)) 3046d467c136SBill Paul dc_init(sc); 3047d467c136SBill Paul 3048d467c136SBill Paul if (DC_IS_INTEL(sc)) { 3049d467c136SBill Paul /* 3050d467c136SBill Paul * The real 21143 requires that the transmitter be idle 3051d467c136SBill Paul * in order to change the transmit threshold or store 3052d467c136SBill Paul * and forward state. 3053d467c136SBill Paul */ 3054d467c136SBill Paul DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3055d467c136SBill Paul 3056d467c136SBill Paul for (i = 0; i < DC_TIMEOUT; i++) { 3057d467c136SBill Paul isr = CSR_READ_4(sc, DC_ISR); 3058d467c136SBill Paul if (isr & DC_ISR_TX_IDLE) 3059d467c136SBill Paul break; 3060d467c136SBill Paul DELAY(10); 3061d467c136SBill Paul } 3062d467c136SBill Paul if (i == DC_TIMEOUT) { 3063d467c136SBill Paul printf("dc%d: failed to force tx to idle state\n", 3064d467c136SBill Paul sc->dc_unit); 3065d467c136SBill Paul dc_init(sc); 3066d467c136SBill Paul } 3067d467c136SBill Paul } 3068d467c136SBill Paul 3069d467c136SBill Paul printf("dc%d: TX underrun -- ", sc->dc_unit); 3070d467c136SBill Paul sc->dc_txthresh += DC_TXTHRESH_INC; 3071d467c136SBill Paul if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3072d467c136SBill Paul printf("using store and forward mode\n"); 3073d467c136SBill Paul DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3074d467c136SBill Paul } else { 3075d467c136SBill Paul printf("increasing TX threshold\n"); 3076d467c136SBill Paul DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3077d467c136SBill Paul DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3078d467c136SBill Paul } 3079d467c136SBill Paul 3080d467c136SBill Paul if (DC_IS_INTEL(sc)) 3081d467c136SBill Paul DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3082d467c136SBill Paul } 3083d467c136SBill Paul 3084e4fc250cSLuigi Rizzo #ifdef DEVICE_POLLING 3085e4fc250cSLuigi Rizzo static poll_handler_t dc_poll; 3086e4fc250cSLuigi Rizzo 3087e4fc250cSLuigi Rizzo static void 3088e4fc250cSLuigi Rizzo dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 3089e4fc250cSLuigi Rizzo { 3090e4fc250cSLuigi Rizzo struct dc_softc *sc = ifp->if_softc; 3091e4fc250cSLuigi Rizzo 3092e4fc250cSLuigi Rizzo if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 3093e4fc250cSLuigi Rizzo /* Re-enable interrupts. */ 3094e4fc250cSLuigi Rizzo CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3095e4fc250cSLuigi Rizzo return; 3096e4fc250cSLuigi Rizzo } 30975120abbfSSam Leffler DC_LOCK(sc); 3098e4fc250cSLuigi Rizzo sc->rxcycles = count; 3099e4fc250cSLuigi Rizzo dc_rxeof(sc); 3100e4fc250cSLuigi Rizzo dc_txeof(sc); 3101e4fc250cSLuigi Rizzo if (ifp->if_snd.ifq_head != NULL && !(ifp->if_flags & IFF_OACTIVE)) 3102e4fc250cSLuigi Rizzo dc_start(ifp); 3103e4fc250cSLuigi Rizzo 3104e4fc250cSLuigi Rizzo if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 3105e4fc250cSLuigi Rizzo u_int32_t status; 3106e4fc250cSLuigi Rizzo 3107e4fc250cSLuigi Rizzo status = CSR_READ_4(sc, DC_ISR); 3108e4fc250cSLuigi Rizzo status &= (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF | 3109e4fc250cSLuigi Rizzo DC_ISR_TX_NOBUF | DC_ISR_TX_IDLE | DC_ISR_TX_UNDERRUN | 3110e4fc250cSLuigi Rizzo DC_ISR_BUS_ERR); 31115120abbfSSam Leffler if (!status) { 31125120abbfSSam Leffler DC_UNLOCK(sc); 3113e4fc250cSLuigi Rizzo return; 31145120abbfSSam Leffler } 3115e4fc250cSLuigi Rizzo /* ack what we have */ 3116e4fc250cSLuigi Rizzo CSR_WRITE_4(sc, DC_ISR, status); 3117e4fc250cSLuigi Rizzo 3118e4fc250cSLuigi Rizzo if (status & (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF)) { 3119e4fc250cSLuigi Rizzo u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 3120e4fc250cSLuigi Rizzo ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 3121e4fc250cSLuigi Rizzo 3122e4fc250cSLuigi Rizzo if (dc_rx_resync(sc)) 3123e4fc250cSLuigi Rizzo dc_rxeof(sc); 3124e4fc250cSLuigi Rizzo } 3125e4fc250cSLuigi Rizzo /* restart transmit unit if necessary */ 3126e4fc250cSLuigi Rizzo if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 3127e4fc250cSLuigi Rizzo CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3128e4fc250cSLuigi Rizzo 3129e4fc250cSLuigi Rizzo if (status & DC_ISR_TX_UNDERRUN) 3130e4fc250cSLuigi Rizzo dc_tx_underrun(sc); 3131e4fc250cSLuigi Rizzo 3132e4fc250cSLuigi Rizzo if (status & DC_ISR_BUS_ERR) { 3133e4fc250cSLuigi Rizzo printf("dc_poll: dc%d bus error\n", sc->dc_unit); 3134e4fc250cSLuigi Rizzo dc_reset(sc); 3135e4fc250cSLuigi Rizzo dc_init(sc); 3136e4fc250cSLuigi Rizzo } 3137e4fc250cSLuigi Rizzo } 31385120abbfSSam Leffler DC_UNLOCK(sc); 3139e4fc250cSLuigi Rizzo } 3140e4fc250cSLuigi Rizzo #endif /* DEVICE_POLLING */ 3141e4fc250cSLuigi Rizzo 3142e3d2833aSAlfred Perlstein static void 31430934f18aSMaxime Henrion dc_intr(void *arg) 314496f2e892SBill Paul { 314596f2e892SBill Paul struct dc_softc *sc; 314696f2e892SBill Paul struct ifnet *ifp; 314796f2e892SBill Paul u_int32_t status; 314896f2e892SBill Paul 314996f2e892SBill Paul sc = arg; 3150d2a1864bSWarner Losh 31510934f18aSMaxime Henrion if (sc->suspended) 3152e8388e14SMitsuru IWASAKI return; 3153e8388e14SMitsuru IWASAKI 3154d2a1864bSWarner Losh if ((CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) 3155d2a1864bSWarner Losh return; 3156d2a1864bSWarner Losh 3157d1ce9105SBill Paul DC_LOCK(sc); 315896f2e892SBill Paul ifp = &sc->arpcom.ac_if; 3159e4fc250cSLuigi Rizzo #ifdef DEVICE_POLLING 316062f76486SMaxim Sobolev if (ifp->if_flags & IFF_POLLING) 3161e4fc250cSLuigi Rizzo goto done; 3162e4fc250cSLuigi Rizzo if (ether_poll_register(dc_poll, ifp)) { /* ok, disable interrupts */ 3163e4fc250cSLuigi Rizzo CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3164e4fc250cSLuigi Rizzo goto done; 3165e4fc250cSLuigi Rizzo } 31660934f18aSMaxime Henrion #endif 316796f2e892SBill Paul 3168d88a358cSLuigi Rizzo /* Suppress unwanted interrupts */ 316996f2e892SBill Paul if (!(ifp->if_flags & IFF_UP)) { 317096f2e892SBill Paul if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 317196f2e892SBill Paul dc_stop(sc); 3172d1ce9105SBill Paul DC_UNLOCK(sc); 317396f2e892SBill Paul return; 317496f2e892SBill Paul } 317596f2e892SBill Paul 317696f2e892SBill Paul /* Disable interrupts. */ 317796f2e892SBill Paul CSR_WRITE_4(sc, DC_IMR, 0x00000000); 317896f2e892SBill Paul 3179feb78939SJonathan Chen while (((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) 3180feb78939SJonathan Chen && status != 0xFFFFFFFF) { 318196f2e892SBill Paul 318296f2e892SBill Paul CSR_WRITE_4(sc, DC_ISR, status); 318396f2e892SBill Paul 318473bf949cSBill Paul if (status & DC_ISR_RX_OK) { 318573bf949cSBill Paul int curpkts; 318673bf949cSBill Paul curpkts = ifp->if_ipackets; 318796f2e892SBill Paul dc_rxeof(sc); 318873bf949cSBill Paul if (curpkts == ifp->if_ipackets) { 318973bf949cSBill Paul while (dc_rx_resync(sc)) 319073bf949cSBill Paul dc_rxeof(sc); 319173bf949cSBill Paul } 319273bf949cSBill Paul } 319396f2e892SBill Paul 319496f2e892SBill Paul if (status & (DC_ISR_TX_OK | DC_ISR_TX_NOBUF)) 319596f2e892SBill Paul dc_txeof(sc); 319696f2e892SBill Paul 319796f2e892SBill Paul if (status & DC_ISR_TX_IDLE) { 319896f2e892SBill Paul dc_txeof(sc); 319996f2e892SBill Paul if (sc->dc_cdata.dc_tx_cnt) { 320096f2e892SBill Paul DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 320196f2e892SBill Paul CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 320296f2e892SBill Paul } 320396f2e892SBill Paul } 320496f2e892SBill Paul 3205d467c136SBill Paul if (status & DC_ISR_TX_UNDERRUN) 3206d467c136SBill Paul dc_tx_underrun(sc); 320796f2e892SBill Paul 320896f2e892SBill Paul if ((status & DC_ISR_RX_WATDOGTIMEO) 320973bf949cSBill Paul || (status & DC_ISR_RX_NOBUF)) { 321073bf949cSBill Paul int curpkts; 321173bf949cSBill Paul curpkts = ifp->if_ipackets; 321296f2e892SBill Paul dc_rxeof(sc); 321373bf949cSBill Paul if (curpkts == ifp->if_ipackets) { 321473bf949cSBill Paul while (dc_rx_resync(sc)) 321573bf949cSBill Paul dc_rxeof(sc); 321673bf949cSBill Paul } 321773bf949cSBill Paul } 321896f2e892SBill Paul 321996f2e892SBill Paul if (status & DC_ISR_BUS_ERR) { 322096f2e892SBill Paul dc_reset(sc); 322196f2e892SBill Paul dc_init(sc); 322296f2e892SBill Paul } 322396f2e892SBill Paul } 322496f2e892SBill Paul 322596f2e892SBill Paul /* Re-enable interrupts. */ 322696f2e892SBill Paul CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 322796f2e892SBill Paul 322896f2e892SBill Paul if (ifp->if_snd.ifq_head != NULL) 322996f2e892SBill Paul dc_start(ifp); 323096f2e892SBill Paul 3231d9700bb5SBill Paul #ifdef DEVICE_POLLING 3232e4fc250cSLuigi Rizzo done: 32330934f18aSMaxime Henrion #endif 3234d9700bb5SBill Paul 3235d1ce9105SBill Paul DC_UNLOCK(sc); 323696f2e892SBill Paul } 323796f2e892SBill Paul 323856e5e7aeSMaxime Henrion static void 323956e5e7aeSMaxime Henrion dc_dma_map_txbuf(arg, segs, nseg, mapsize, error) 324056e5e7aeSMaxime Henrion void *arg; 324156e5e7aeSMaxime Henrion bus_dma_segment_t *segs; 324256e5e7aeSMaxime Henrion int nseg; 324356e5e7aeSMaxime Henrion bus_size_t mapsize; 324456e5e7aeSMaxime Henrion int error; 324556e5e7aeSMaxime Henrion { 324656e5e7aeSMaxime Henrion struct dc_softc *sc; 324756e5e7aeSMaxime Henrion struct dc_desc *f; 324856e5e7aeSMaxime Henrion int cur, first, frag, i; 324956e5e7aeSMaxime Henrion 325056e5e7aeSMaxime Henrion sc = arg; 325156e5e7aeSMaxime Henrion if (error) { 325256e5e7aeSMaxime Henrion sc->dc_cdata.dc_tx_err = error; 325356e5e7aeSMaxime Henrion return; 325456e5e7aeSMaxime Henrion } 325556e5e7aeSMaxime Henrion 325656e5e7aeSMaxime Henrion first = cur = frag = sc->dc_cdata.dc_tx_prod; 325756e5e7aeSMaxime Henrion for (i = 0; i < nseg; i++) { 325856e5e7aeSMaxime Henrion if ((sc->dc_flags & DC_TX_ADMTEK_WAR) && 325956e5e7aeSMaxime Henrion (frag == (DC_TX_LIST_CNT - 1)) && 326056e5e7aeSMaxime Henrion (first != sc->dc_cdata.dc_tx_first)) { 326156e5e7aeSMaxime Henrion bus_dmamap_unload(sc->dc_mtag, 326256e5e7aeSMaxime Henrion sc->dc_cdata.dc_tx_map[first]); 326356e5e7aeSMaxime Henrion sc->dc_cdata.dc_tx_err = ENOBUFS; 326456e5e7aeSMaxime Henrion return; 326556e5e7aeSMaxime Henrion } 326656e5e7aeSMaxime Henrion 326756e5e7aeSMaxime Henrion f = &sc->dc_ldata->dc_tx_list[frag]; 3268af4358c7SMaxime Henrion f->dc_ctl = htole32(DC_TXCTL_TLINK | segs[i].ds_len); 326956e5e7aeSMaxime Henrion if (i == 0) { 327056e5e7aeSMaxime Henrion f->dc_status = 0; 3271af4358c7SMaxime Henrion f->dc_ctl |= htole32(DC_TXCTL_FIRSTFRAG); 327256e5e7aeSMaxime Henrion } else 3273af4358c7SMaxime Henrion f->dc_status = htole32(DC_TXSTAT_OWN); 3274af4358c7SMaxime Henrion f->dc_data = htole32(segs[i].ds_addr); 327556e5e7aeSMaxime Henrion cur = frag; 327656e5e7aeSMaxime Henrion DC_INC(frag, DC_TX_LIST_CNT); 327756e5e7aeSMaxime Henrion } 327856e5e7aeSMaxime Henrion 327956e5e7aeSMaxime Henrion sc->dc_cdata.dc_tx_err = 0; 328056e5e7aeSMaxime Henrion sc->dc_cdata.dc_tx_prod = frag; 328156e5e7aeSMaxime Henrion sc->dc_cdata.dc_tx_cnt += nseg; 3282af4358c7SMaxime Henrion sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_LASTFRAG); 32834ff4a9beSDon Lewis sc->dc_cdata.dc_tx_chain[cur] = sc->dc_cdata.dc_tx_mapping; 328456e5e7aeSMaxime Henrion if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 3285af4358c7SMaxime Henrion sc->dc_ldata->dc_tx_list[first].dc_ctl |= 3286af4358c7SMaxime Henrion htole32(DC_TXCTL_FINT); 328756e5e7aeSMaxime Henrion if (sc->dc_flags & DC_TX_INTR_ALWAYS) 3288af4358c7SMaxime Henrion sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 328956e5e7aeSMaxime Henrion if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 3290af4358c7SMaxime Henrion sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3291af4358c7SMaxime Henrion sc->dc_ldata->dc_tx_list[first].dc_status = htole32(DC_TXSTAT_OWN); 329256e5e7aeSMaxime Henrion } 329356e5e7aeSMaxime Henrion 329496f2e892SBill Paul /* 329596f2e892SBill Paul * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 329696f2e892SBill Paul * pointers to the fragment pointers. 329796f2e892SBill Paul */ 3298e3d2833aSAlfred Perlstein static int 3299a10c0e45SMike Silbersack dc_encap(struct dc_softc *sc, struct mbuf **m_head) 330096f2e892SBill Paul { 330196f2e892SBill Paul struct mbuf *m; 330256e5e7aeSMaxime Henrion int error, idx, chainlen = 0; 3303cda97c50SMike Silbersack 3304cda97c50SMike Silbersack /* 3305cda97c50SMike Silbersack * If there's no way we can send any packets, return now. 3306cda97c50SMike Silbersack */ 3307cda97c50SMike Silbersack if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt < 6) 3308cda97c50SMike Silbersack return (ENOBUFS); 3309cda97c50SMike Silbersack 3310cda97c50SMike Silbersack /* 3311cda97c50SMike Silbersack * Count the number of frags in this chain to see if 3312cda97c50SMike Silbersack * we need to m_defrag. Since the descriptor list is shared 3313cda97c50SMike Silbersack * by all packets, we'll m_defrag long chains so that they 3314cda97c50SMike Silbersack * do not use up the entire list, even if they would fit. 3315cda97c50SMike Silbersack */ 3316a10c0e45SMike Silbersack for (m = *m_head; m != NULL; m = m->m_next) 3317cda97c50SMike Silbersack chainlen++; 3318cda97c50SMike Silbersack 3319cda97c50SMike Silbersack if ((chainlen > DC_TX_LIST_CNT / 4) || 3320cda97c50SMike Silbersack ((DC_TX_LIST_CNT - (chainlen + sc->dc_cdata.dc_tx_cnt)) < 6)) { 3321a10c0e45SMike Silbersack m = m_defrag(*m_head, M_DONTWAIT); 3322cda97c50SMike Silbersack if (m == NULL) 3323cda97c50SMike Silbersack return (ENOBUFS); 3324a10c0e45SMike Silbersack *m_head = m; 3325cda97c50SMike Silbersack } 332696f2e892SBill Paul 332796f2e892SBill Paul /* 332896f2e892SBill Paul * Start packing the mbufs in this chain into 332996f2e892SBill Paul * the fragment pointers. Stop when we run out 333096f2e892SBill Paul * of fragments or hit the end of the mbuf chain. 333196f2e892SBill Paul */ 333256e5e7aeSMaxime Henrion idx = sc->dc_cdata.dc_tx_prod; 33334ff4a9beSDon Lewis sc->dc_cdata.dc_tx_mapping = *m_head; 333456e5e7aeSMaxime Henrion error = bus_dmamap_load_mbuf(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx], 3335a10c0e45SMike Silbersack *m_head, dc_dma_map_txbuf, sc, 0); 333656e5e7aeSMaxime Henrion if (error) 333756e5e7aeSMaxime Henrion return (error); 333856e5e7aeSMaxime Henrion if (sc->dc_cdata.dc_tx_err != 0) 333956e5e7aeSMaxime Henrion return (sc->dc_cdata.dc_tx_err); 334056e5e7aeSMaxime Henrion bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx], 334156e5e7aeSMaxime Henrion BUS_DMASYNC_PREWRITE); 334256e5e7aeSMaxime Henrion bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 334356e5e7aeSMaxime Henrion BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 334496f2e892SBill Paul return (0); 334596f2e892SBill Paul } 334696f2e892SBill Paul 334796f2e892SBill Paul /* 334896f2e892SBill Paul * Main transmit routine. To avoid having to do mbuf copies, we put pointers 334996f2e892SBill Paul * to the mbuf data regions directly in the transmit lists. We also save a 335096f2e892SBill Paul * copy of the pointers since the transmit list fragment pointers are 335196f2e892SBill Paul * physical addresses. 335296f2e892SBill Paul */ 335396f2e892SBill Paul 3354e3d2833aSAlfred Perlstein static void 33550934f18aSMaxime Henrion dc_start(struct ifnet *ifp) 335696f2e892SBill Paul { 335796f2e892SBill Paul struct dc_softc *sc; 3358cda97c50SMike Silbersack struct mbuf *m_head = NULL, *m; 335996f2e892SBill Paul int idx; 336096f2e892SBill Paul 336196f2e892SBill Paul sc = ifp->if_softc; 336296f2e892SBill Paul 3363d1ce9105SBill Paul DC_LOCK(sc); 336496f2e892SBill Paul 3365e7be9f9aSBill Paul if (!sc->dc_link && ifp->if_snd.ifq_len < 10) { 3366d1ce9105SBill Paul DC_UNLOCK(sc); 336796f2e892SBill Paul return; 3368d1ce9105SBill Paul } 3369d1ce9105SBill Paul 3370d1ce9105SBill Paul if (ifp->if_flags & IFF_OACTIVE) { 3371d1ce9105SBill Paul DC_UNLOCK(sc); 3372d1ce9105SBill Paul return; 3373d1ce9105SBill Paul } 337496f2e892SBill Paul 337556e5e7aeSMaxime Henrion idx = sc->dc_cdata.dc_tx_first = sc->dc_cdata.dc_tx_prod; 337696f2e892SBill Paul 337796f2e892SBill Paul while (sc->dc_cdata.dc_tx_chain[idx] == NULL) { 337896f2e892SBill Paul IF_DEQUEUE(&ifp->if_snd, m_head); 337996f2e892SBill Paul if (m_head == NULL) 338096f2e892SBill Paul break; 338196f2e892SBill Paul 33822dfc960aSLuigi Rizzo if (sc->dc_flags & DC_TX_COALESCE && 33832dfc960aSLuigi Rizzo (m_head->m_next != NULL || 33842dfc960aSLuigi Rizzo sc->dc_flags & DC_TX_ALIGN)) { 3385cda97c50SMike Silbersack m = m_defrag(m_head, M_DONTWAIT); 3386cda97c50SMike Silbersack if (m == NULL) { 3387fda39fd0SBill Paul IF_PREPEND(&ifp->if_snd, m_head); 3388fda39fd0SBill Paul ifp->if_flags |= IFF_OACTIVE; 3389fda39fd0SBill Paul break; 3390cda97c50SMike Silbersack } else { 3391cda97c50SMike Silbersack m_head = m; 3392fda39fd0SBill Paul } 3393fda39fd0SBill Paul } 3394fda39fd0SBill Paul 3395a10c0e45SMike Silbersack if (dc_encap(sc, &m_head)) { 339696f2e892SBill Paul IF_PREPEND(&ifp->if_snd, m_head); 339796f2e892SBill Paul ifp->if_flags |= IFF_OACTIVE; 339896f2e892SBill Paul break; 339996f2e892SBill Paul } 340056e5e7aeSMaxime Henrion idx = sc->dc_cdata.dc_tx_prod; 340196f2e892SBill Paul 340296f2e892SBill Paul /* 340396f2e892SBill Paul * If there's a BPF listener, bounce a copy of this frame 340496f2e892SBill Paul * to him. 340596f2e892SBill Paul */ 34069ef8b520SSam Leffler BPF_MTAP(ifp, m_head); 34075c1cfac4SBill Paul 34085c1cfac4SBill Paul if (sc->dc_flags & DC_TX_ONE) { 34095c1cfac4SBill Paul ifp->if_flags |= IFF_OACTIVE; 34105c1cfac4SBill Paul break; 34115c1cfac4SBill Paul } 341296f2e892SBill Paul } 341396f2e892SBill Paul 341496f2e892SBill Paul /* Transmit */ 341596f2e892SBill Paul if (!(sc->dc_flags & DC_TX_POLL)) 341696f2e892SBill Paul CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 341796f2e892SBill Paul 341896f2e892SBill Paul /* 341996f2e892SBill Paul * Set a timeout in case the chip goes out to lunch. 342096f2e892SBill Paul */ 342196f2e892SBill Paul ifp->if_timer = 5; 342296f2e892SBill Paul 3423d1ce9105SBill Paul DC_UNLOCK(sc); 342496f2e892SBill Paul } 342596f2e892SBill Paul 3426e3d2833aSAlfred Perlstein static void 34270934f18aSMaxime Henrion dc_init(void *xsc) 342896f2e892SBill Paul { 342996f2e892SBill Paul struct dc_softc *sc = xsc; 343096f2e892SBill Paul struct ifnet *ifp = &sc->arpcom.ac_if; 343196f2e892SBill Paul struct mii_data *mii; 343296f2e892SBill Paul 3433d1ce9105SBill Paul DC_LOCK(sc); 343496f2e892SBill Paul 343596f2e892SBill Paul mii = device_get_softc(sc->dc_miibus); 343696f2e892SBill Paul 343796f2e892SBill Paul /* 343896f2e892SBill Paul * Cancel pending I/O and free all RX/TX buffers. 343996f2e892SBill Paul */ 344096f2e892SBill Paul dc_stop(sc); 344196f2e892SBill Paul dc_reset(sc); 344296f2e892SBill Paul 344396f2e892SBill Paul /* 344496f2e892SBill Paul * Set cache alignment and burst length. 344596f2e892SBill Paul */ 344688d739dcSBill Paul if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 344796f2e892SBill Paul CSR_WRITE_4(sc, DC_BUSCTL, 0); 344896f2e892SBill Paul else 344996f2e892SBill Paul CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME | DC_BUSCTL_MRLE); 3450935fe010SLuigi Rizzo /* 3451935fe010SLuigi Rizzo * Evenly share the bus between receive and transmit process. 3452935fe010SLuigi Rizzo */ 3453935fe010SLuigi Rizzo if (DC_IS_INTEL(sc)) 3454935fe010SLuigi Rizzo DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 345596f2e892SBill Paul if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 345696f2e892SBill Paul DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 345796f2e892SBill Paul } else { 345896f2e892SBill Paul DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 345996f2e892SBill Paul } 346096f2e892SBill Paul if (sc->dc_flags & DC_TX_POLL) 346196f2e892SBill Paul DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 346296f2e892SBill Paul switch(sc->dc_cachesize) { 346396f2e892SBill Paul case 32: 346496f2e892SBill Paul DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 346596f2e892SBill Paul break; 346696f2e892SBill Paul case 16: 346796f2e892SBill Paul DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 346896f2e892SBill Paul break; 346996f2e892SBill Paul case 8: 347096f2e892SBill Paul DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 347196f2e892SBill Paul break; 347296f2e892SBill Paul case 0: 347396f2e892SBill Paul default: 347496f2e892SBill Paul DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 347596f2e892SBill Paul break; 347696f2e892SBill Paul } 347796f2e892SBill Paul 347896f2e892SBill Paul if (sc->dc_flags & DC_TX_STORENFWD) 347996f2e892SBill Paul DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 348096f2e892SBill Paul else { 3481d467c136SBill Paul if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 348296f2e892SBill Paul DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 348396f2e892SBill Paul } else { 348496f2e892SBill Paul DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 348596f2e892SBill Paul DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 348696f2e892SBill Paul } 348796f2e892SBill Paul } 348896f2e892SBill Paul 348996f2e892SBill Paul DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 349096f2e892SBill Paul DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 349196f2e892SBill Paul 349296f2e892SBill Paul if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 349396f2e892SBill Paul /* 349496f2e892SBill Paul * The app notes for the 98713 and 98715A say that 349596f2e892SBill Paul * in order to have the chips operate properly, a magic 349696f2e892SBill Paul * number must be written to CSR16. Macronix does not 349796f2e892SBill Paul * document the meaning of these bits so there's no way 349896f2e892SBill Paul * to know exactly what they do. The 98713 has a magic 349996f2e892SBill Paul * number all its own; the rest all use a different one. 350096f2e892SBill Paul */ 350196f2e892SBill Paul DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 350296f2e892SBill Paul if (sc->dc_type == DC_TYPE_98713) 350396f2e892SBill Paul DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 350496f2e892SBill Paul else 350596f2e892SBill Paul DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 350696f2e892SBill Paul } 350796f2e892SBill Paul 3508feb78939SJonathan Chen if (DC_IS_XIRCOM(sc)) { 3509feb78939SJonathan Chen /* 3510feb78939SJonathan Chen * setup General Purpose Port mode and data so the tulip 3511feb78939SJonathan Chen * can talk to the MII. 3512feb78939SJonathan Chen */ 3513feb78939SJonathan Chen CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3514feb78939SJonathan Chen DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3515feb78939SJonathan Chen DELAY(10); 3516feb78939SJonathan Chen CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3517feb78939SJonathan Chen DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3518feb78939SJonathan Chen DELAY(10); 3519feb78939SJonathan Chen } 3520feb78939SJonathan Chen 352196f2e892SBill Paul DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3522d467c136SBill Paul DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 352396f2e892SBill Paul 352496f2e892SBill Paul /* Init circular RX list. */ 352596f2e892SBill Paul if (dc_list_rx_init(sc) == ENOBUFS) { 352696f2e892SBill Paul printf("dc%d: initialization failed: no " 352796f2e892SBill Paul "memory for rx buffers\n", sc->dc_unit); 352896f2e892SBill Paul dc_stop(sc); 3529d1ce9105SBill Paul DC_UNLOCK(sc); 353096f2e892SBill Paul return; 353196f2e892SBill Paul } 353296f2e892SBill Paul 353396f2e892SBill Paul /* 353456e5e7aeSMaxime Henrion * Init TX descriptors. 353596f2e892SBill Paul */ 353696f2e892SBill Paul dc_list_tx_init(sc); 353796f2e892SBill Paul 353896f2e892SBill Paul /* 353996f2e892SBill Paul * Load the address of the RX list. 354096f2e892SBill Paul */ 354156e5e7aeSMaxime Henrion CSR_WRITE_4(sc, DC_RXADDR, DC_RXDESC(sc, 0)); 354256e5e7aeSMaxime Henrion CSR_WRITE_4(sc, DC_TXADDR, DC_TXDESC(sc, 0)); 354396f2e892SBill Paul 354496f2e892SBill Paul /* 354596f2e892SBill Paul * Enable interrupts. 354696f2e892SBill Paul */ 3547e4fc250cSLuigi Rizzo #ifdef DEVICE_POLLING 3548e4fc250cSLuigi Rizzo /* 3549e4fc250cSLuigi Rizzo * ... but only if we are not polling, and make sure they are off in 3550e4fc250cSLuigi Rizzo * the case of polling. Some cards (e.g. fxp) turn interrupts on 3551e4fc250cSLuigi Rizzo * after a reset. 3552e4fc250cSLuigi Rizzo */ 355362f76486SMaxim Sobolev if (ifp->if_flags & IFF_POLLING) 3554e4fc250cSLuigi Rizzo CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3555e4fc250cSLuigi Rizzo else 3556e4fc250cSLuigi Rizzo #endif 355796f2e892SBill Paul CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 355896f2e892SBill Paul CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 355996f2e892SBill Paul 356096f2e892SBill Paul /* Enable transmitter. */ 356196f2e892SBill Paul DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 356296f2e892SBill Paul 356396f2e892SBill Paul /* 3564918434c8SBill Paul * If this is an Intel 21143 and we're not using the 3565918434c8SBill Paul * MII port, program the LED control pins so we get 3566918434c8SBill Paul * link and activity indications. 3567918434c8SBill Paul */ 356878999dd1SBill Paul if (sc->dc_flags & DC_TULIP_LEDS) { 3569918434c8SBill Paul CSR_WRITE_4(sc, DC_WATCHDOG, 3570918434c8SBill Paul DC_WDOG_CTLWREN | DC_WDOG_LINK | DC_WDOG_ACTIVITY); 357178999dd1SBill Paul CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3572918434c8SBill Paul } 3573918434c8SBill Paul 3574918434c8SBill Paul /* 357596f2e892SBill Paul * Load the RX/multicast filter. We do this sort of late 357696f2e892SBill Paul * because the filter programming scheme on the 21143 and 357796f2e892SBill Paul * some clones requires DMAing a setup frame via the TX 357896f2e892SBill Paul * engine, and we need the transmitter enabled for that. 357996f2e892SBill Paul */ 358096f2e892SBill Paul dc_setfilt(sc); 358196f2e892SBill Paul 358296f2e892SBill Paul /* Enable receiver. */ 358396f2e892SBill Paul DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 358496f2e892SBill Paul CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 358596f2e892SBill Paul 358696f2e892SBill Paul mii_mediachg(mii); 358796f2e892SBill Paul dc_setcfg(sc, sc->dc_if_media); 358896f2e892SBill Paul 358996f2e892SBill Paul ifp->if_flags |= IFF_RUNNING; 359096f2e892SBill Paul ifp->if_flags &= ~IFF_OACTIVE; 359196f2e892SBill Paul 3592857fd445SBill Paul /* Don't start the ticker if this is a homePNA link. */ 359345521525SPoul-Henning Kamp if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) 3594857fd445SBill Paul sc->dc_link = 1; 3595857fd445SBill Paul else { 3596318b02fdSBill Paul if (sc->dc_flags & DC_21143_NWAY) 3597b50c6312SJonathan Lemon callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3598318b02fdSBill Paul else 3599b50c6312SJonathan Lemon callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3600857fd445SBill Paul } 360196f2e892SBill Paul 36025c1cfac4SBill Paul #ifdef SRM_MEDIA 3603510a809eSMike Smith if(sc->dc_srm_media) { 3604510a809eSMike Smith struct ifreq ifr; 3605510a809eSMike Smith 3606510a809eSMike Smith ifr.ifr_media = sc->dc_srm_media; 3607510a809eSMike Smith ifmedia_ioctl(ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA); 3608510a809eSMike Smith sc->dc_srm_media = 0; 3609510a809eSMike Smith } 3610510a809eSMike Smith #endif 3611d1ce9105SBill Paul DC_UNLOCK(sc); 361296f2e892SBill Paul } 361396f2e892SBill Paul 361496f2e892SBill Paul /* 361596f2e892SBill Paul * Set media options. 361696f2e892SBill Paul */ 3617e3d2833aSAlfred Perlstein static int 36180934f18aSMaxime Henrion dc_ifmedia_upd(struct ifnet *ifp) 361996f2e892SBill Paul { 362096f2e892SBill Paul struct dc_softc *sc; 362196f2e892SBill Paul struct mii_data *mii; 3622f43d9309SBill Paul struct ifmedia *ifm; 362396f2e892SBill Paul 362496f2e892SBill Paul sc = ifp->if_softc; 362596f2e892SBill Paul mii = device_get_softc(sc->dc_miibus); 362696f2e892SBill Paul mii_mediachg(mii); 3627f43d9309SBill Paul ifm = &mii->mii_media; 3628f43d9309SBill Paul 3629f43d9309SBill Paul if (DC_IS_DAVICOM(sc) && 363045521525SPoul-Henning Kamp IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) 3631f43d9309SBill Paul dc_setcfg(sc, ifm->ifm_media); 3632f43d9309SBill Paul else 363396f2e892SBill Paul sc->dc_link = 0; 363496f2e892SBill Paul 363596f2e892SBill Paul return (0); 363696f2e892SBill Paul } 363796f2e892SBill Paul 363896f2e892SBill Paul /* 363996f2e892SBill Paul * Report current media status. 364096f2e892SBill Paul */ 3641e3d2833aSAlfred Perlstein static void 36420934f18aSMaxime Henrion dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 364396f2e892SBill Paul { 364496f2e892SBill Paul struct dc_softc *sc; 364596f2e892SBill Paul struct mii_data *mii; 3646f43d9309SBill Paul struct ifmedia *ifm; 364796f2e892SBill Paul 364896f2e892SBill Paul sc = ifp->if_softc; 364996f2e892SBill Paul mii = device_get_softc(sc->dc_miibus); 365096f2e892SBill Paul mii_pollstat(mii); 3651f43d9309SBill Paul ifm = &mii->mii_media; 3652f43d9309SBill Paul if (DC_IS_DAVICOM(sc)) { 365345521525SPoul-Henning Kamp if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 3654f43d9309SBill Paul ifmr->ifm_active = ifm->ifm_media; 3655f43d9309SBill Paul ifmr->ifm_status = 0; 3656f43d9309SBill Paul return; 3657f43d9309SBill Paul } 3658f43d9309SBill Paul } 365996f2e892SBill Paul ifmr->ifm_active = mii->mii_media_active; 366096f2e892SBill Paul ifmr->ifm_status = mii->mii_media_status; 366196f2e892SBill Paul } 366296f2e892SBill Paul 3663e3d2833aSAlfred Perlstein static int 36640934f18aSMaxime Henrion dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 366596f2e892SBill Paul { 366696f2e892SBill Paul struct dc_softc *sc = ifp->if_softc; 366796f2e892SBill Paul struct ifreq *ifr = (struct ifreq *)data; 366896f2e892SBill Paul struct mii_data *mii; 3669d1ce9105SBill Paul int error = 0; 367096f2e892SBill Paul 3671d1ce9105SBill Paul DC_LOCK(sc); 367296f2e892SBill Paul 367396f2e892SBill Paul switch (command) { 367496f2e892SBill Paul case SIOCSIFFLAGS: 367596f2e892SBill Paul if (ifp->if_flags & IFF_UP) { 36765d6dfbbbSLuigi Rizzo int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) & 36775d6dfbbbSLuigi Rizzo (IFF_PROMISC | IFF_ALLMULTI); 36785d6dfbbbSLuigi Rizzo 36795d6dfbbbSLuigi Rizzo if (ifp->if_flags & IFF_RUNNING) { 36805d6dfbbbSLuigi Rizzo if (need_setfilt) 368196f2e892SBill Paul dc_setfilt(sc); 36825d6dfbbbSLuigi Rizzo } else { 368396f2e892SBill Paul sc->dc_txthresh = 0; 368496f2e892SBill Paul dc_init(sc); 368596f2e892SBill Paul } 368696f2e892SBill Paul } else { 368796f2e892SBill Paul if (ifp->if_flags & IFF_RUNNING) 368896f2e892SBill Paul dc_stop(sc); 368996f2e892SBill Paul } 369096f2e892SBill Paul sc->dc_if_flags = ifp->if_flags; 369196f2e892SBill Paul error = 0; 369296f2e892SBill Paul break; 369396f2e892SBill Paul case SIOCADDMULTI: 369496f2e892SBill Paul case SIOCDELMULTI: 369596f2e892SBill Paul dc_setfilt(sc); 369696f2e892SBill Paul error = 0; 369796f2e892SBill Paul break; 369896f2e892SBill Paul case SIOCGIFMEDIA: 369996f2e892SBill Paul case SIOCSIFMEDIA: 370096f2e892SBill Paul mii = device_get_softc(sc->dc_miibus); 370196f2e892SBill Paul error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 37025c1cfac4SBill Paul #ifdef SRM_MEDIA 3703510a809eSMike Smith if (sc->dc_srm_media) 3704510a809eSMike Smith sc->dc_srm_media = 0; 3705510a809eSMike Smith #endif 370696f2e892SBill Paul break; 370796f2e892SBill Paul default: 37089ef8b520SSam Leffler error = ether_ioctl(ifp, command, data); 370996f2e892SBill Paul break; 371096f2e892SBill Paul } 371196f2e892SBill Paul 3712d1ce9105SBill Paul DC_UNLOCK(sc); 371396f2e892SBill Paul 371496f2e892SBill Paul return (error); 371596f2e892SBill Paul } 371696f2e892SBill Paul 3717e3d2833aSAlfred Perlstein static void 37180934f18aSMaxime Henrion dc_watchdog(struct ifnet *ifp) 371996f2e892SBill Paul { 372096f2e892SBill Paul struct dc_softc *sc; 372196f2e892SBill Paul 372296f2e892SBill Paul sc = ifp->if_softc; 372396f2e892SBill Paul 3724d1ce9105SBill Paul DC_LOCK(sc); 3725d1ce9105SBill Paul 372696f2e892SBill Paul ifp->if_oerrors++; 372796f2e892SBill Paul printf("dc%d: watchdog timeout\n", sc->dc_unit); 372896f2e892SBill Paul 372996f2e892SBill Paul dc_stop(sc); 373096f2e892SBill Paul dc_reset(sc); 373196f2e892SBill Paul dc_init(sc); 373296f2e892SBill Paul 373396f2e892SBill Paul if (ifp->if_snd.ifq_head != NULL) 373496f2e892SBill Paul dc_start(ifp); 373596f2e892SBill Paul 3736d1ce9105SBill Paul DC_UNLOCK(sc); 373796f2e892SBill Paul } 373896f2e892SBill Paul 373996f2e892SBill Paul /* 374096f2e892SBill Paul * Stop the adapter and free any mbufs allocated to the 374196f2e892SBill Paul * RX and TX lists. 374296f2e892SBill Paul */ 3743e3d2833aSAlfred Perlstein static void 37440934f18aSMaxime Henrion dc_stop(struct dc_softc *sc) 374596f2e892SBill Paul { 374696f2e892SBill Paul struct ifnet *ifp; 3747b3811c95SMaxime Henrion struct dc_list_data *ld; 3748b3811c95SMaxime Henrion struct dc_chain_data *cd; 3749b3811c95SMaxime Henrion int i; 3750af4358c7SMaxime Henrion u_int32_t ctl; 375196f2e892SBill Paul 3752d1ce9105SBill Paul DC_LOCK(sc); 3753d1ce9105SBill Paul 375496f2e892SBill Paul ifp = &sc->arpcom.ac_if; 375596f2e892SBill Paul ifp->if_timer = 0; 3756b3811c95SMaxime Henrion ld = sc->dc_ldata; 3757b3811c95SMaxime Henrion cd = &sc->dc_cdata; 375896f2e892SBill Paul 3759b50c6312SJonathan Lemon callout_stop(&sc->dc_stat_ch); 376096f2e892SBill Paul 37613b3ec200SPeter Wemm ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3762e4fc250cSLuigi Rizzo #ifdef DEVICE_POLLING 3763e4fc250cSLuigi Rizzo ether_poll_deregister(ifp); 3764e4fc250cSLuigi Rizzo #endif 37653b3ec200SPeter Wemm 376696f2e892SBill Paul DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)); 376796f2e892SBill Paul CSR_WRITE_4(sc, DC_IMR, 0x00000000); 376896f2e892SBill Paul CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 376996f2e892SBill Paul CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 377096f2e892SBill Paul sc->dc_link = 0; 377196f2e892SBill Paul 377296f2e892SBill Paul /* 377396f2e892SBill Paul * Free data in the RX lists. 377496f2e892SBill Paul */ 377596f2e892SBill Paul for (i = 0; i < DC_RX_LIST_CNT; i++) { 3776b3811c95SMaxime Henrion if (cd->dc_rx_chain[i] != NULL) { 377756e5e7aeSMaxime Henrion m_freem(cd->dc_rx_chain[i]); 377856e5e7aeSMaxime Henrion cd->dc_rx_chain[i] = NULL; 377996f2e892SBill Paul } 378096f2e892SBill Paul } 3781b3811c95SMaxime Henrion bzero(&ld->dc_rx_list, sizeof(ld->dc_rx_list)); 378296f2e892SBill Paul 378396f2e892SBill Paul /* 378496f2e892SBill Paul * Free the TX list buffers. 378596f2e892SBill Paul */ 378696f2e892SBill Paul for (i = 0; i < DC_TX_LIST_CNT; i++) { 3787b3811c95SMaxime Henrion if (cd->dc_tx_chain[i] != NULL) { 3788af4358c7SMaxime Henrion ctl = le32toh(ld->dc_tx_list[i].dc_ctl); 3789af4358c7SMaxime Henrion if ((ctl & DC_TXCTL_SETUP) || 37904ff4a9beSDon Lewis !(ctl & DC_TXCTL_LASTFRAG)) { 3791b3811c95SMaxime Henrion cd->dc_tx_chain[i] = NULL; 379296f2e892SBill Paul continue; 379396f2e892SBill Paul } 379456e5e7aeSMaxime Henrion bus_dmamap_unload(sc->dc_mtag, cd->dc_tx_map[i]); 379556e5e7aeSMaxime Henrion m_freem(cd->dc_tx_chain[i]); 3796b3811c95SMaxime Henrion cd->dc_tx_chain[i] = NULL; 379796f2e892SBill Paul } 379896f2e892SBill Paul } 3799b3811c95SMaxime Henrion bzero(&ld->dc_tx_list, sizeof(ld->dc_tx_list)); 380096f2e892SBill Paul 3801d1ce9105SBill Paul DC_UNLOCK(sc); 380296f2e892SBill Paul } 380396f2e892SBill Paul 380496f2e892SBill Paul /* 3805e8388e14SMitsuru IWASAKI * Device suspend routine. Stop the interface and save some PCI 3806e8388e14SMitsuru IWASAKI * settings in case the BIOS doesn't restore them properly on 3807e8388e14SMitsuru IWASAKI * resume. 3808e8388e14SMitsuru IWASAKI */ 3809e3d2833aSAlfred Perlstein static int 38100934f18aSMaxime Henrion dc_suspend(device_t dev) 3811e8388e14SMitsuru IWASAKI { 3812e8388e14SMitsuru IWASAKI struct dc_softc *sc; 38130934f18aSMaxime Henrion int i, s; 3814e8388e14SMitsuru IWASAKI 3815e8388e14SMitsuru IWASAKI s = splimp(); 3816e8388e14SMitsuru IWASAKI 3817e8388e14SMitsuru IWASAKI sc = device_get_softc(dev); 3818e8388e14SMitsuru IWASAKI 3819e8388e14SMitsuru IWASAKI dc_stop(sc); 3820e8388e14SMitsuru IWASAKI 3821e8388e14SMitsuru IWASAKI for (i = 0; i < 5; i++) 3822e27951b2SJohn Baldwin sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4); 3823e8388e14SMitsuru IWASAKI sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 3824e8388e14SMitsuru IWASAKI sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 3825e8388e14SMitsuru IWASAKI sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 3826e8388e14SMitsuru IWASAKI sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 3827e8388e14SMitsuru IWASAKI 3828e8388e14SMitsuru IWASAKI sc->suspended = 1; 3829e8388e14SMitsuru IWASAKI 3830e8388e14SMitsuru IWASAKI splx(s); 3831e8388e14SMitsuru IWASAKI return (0); 3832e8388e14SMitsuru IWASAKI } 3833e8388e14SMitsuru IWASAKI 3834e8388e14SMitsuru IWASAKI /* 3835e8388e14SMitsuru IWASAKI * Device resume routine. Restore some PCI settings in case the BIOS 3836e8388e14SMitsuru IWASAKI * doesn't, re-enable busmastering, and restart the interface if 3837e8388e14SMitsuru IWASAKI * appropriate. 3838e8388e14SMitsuru IWASAKI */ 3839e3d2833aSAlfred Perlstein static int 38400934f18aSMaxime Henrion dc_resume(device_t dev) 3841e8388e14SMitsuru IWASAKI { 3842e8388e14SMitsuru IWASAKI struct dc_softc *sc; 3843e8388e14SMitsuru IWASAKI struct ifnet *ifp; 38440934f18aSMaxime Henrion int i, s; 3845e8388e14SMitsuru IWASAKI 3846e8388e14SMitsuru IWASAKI s = splimp(); 3847e8388e14SMitsuru IWASAKI 3848e8388e14SMitsuru IWASAKI sc = device_get_softc(dev); 3849e8388e14SMitsuru IWASAKI ifp = &sc->arpcom.ac_if; 3850b84e866aSWarner Losh #ifndef BURN_BRIDGES 3851e8388e14SMitsuru IWASAKI dc_acpi(dev); 3852b84e866aSWarner Losh #endif 3853e8388e14SMitsuru IWASAKI /* better way to do this? */ 3854e8388e14SMitsuru IWASAKI for (i = 0; i < 5; i++) 3855e27951b2SJohn Baldwin pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4); 3856e8388e14SMitsuru IWASAKI pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 3857e8388e14SMitsuru IWASAKI pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 3858e8388e14SMitsuru IWASAKI pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 3859e8388e14SMitsuru IWASAKI pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 3860e8388e14SMitsuru IWASAKI 3861e8388e14SMitsuru IWASAKI /* reenable busmastering */ 3862e8388e14SMitsuru IWASAKI pci_enable_busmaster(dev); 3863e8388e14SMitsuru IWASAKI pci_enable_io(dev, DC_RES); 3864e8388e14SMitsuru IWASAKI 3865e8388e14SMitsuru IWASAKI /* reinitialize interface if necessary */ 3866e8388e14SMitsuru IWASAKI if (ifp->if_flags & IFF_UP) 3867e8388e14SMitsuru IWASAKI dc_init(sc); 3868e8388e14SMitsuru IWASAKI 3869e8388e14SMitsuru IWASAKI sc->suspended = 0; 3870e8388e14SMitsuru IWASAKI 3871e8388e14SMitsuru IWASAKI splx(s); 3872e8388e14SMitsuru IWASAKI return (0); 3873e8388e14SMitsuru IWASAKI } 3874e8388e14SMitsuru IWASAKI 3875e8388e14SMitsuru IWASAKI /* 387696f2e892SBill Paul * Stop all chip I/O so that the kernel's probe routines don't 387796f2e892SBill Paul * get confused by errant DMAs when rebooting. 387896f2e892SBill Paul */ 3879e3d2833aSAlfred Perlstein static void 38800934f18aSMaxime Henrion dc_shutdown(device_t dev) 388196f2e892SBill Paul { 388296f2e892SBill Paul struct dc_softc *sc; 388396f2e892SBill Paul 388496f2e892SBill Paul sc = device_get_softc(dev); 388596f2e892SBill Paul 388696f2e892SBill Paul dc_stop(sc); 388796f2e892SBill Paul } 3888