xref: /freebsd/sys/dev/dc/if_dc.c (revision 1e2e70b1d6bf54cf50f6deb49e386a9ad52214fe)
160727d8bSWarner Losh /*-
296f2e892SBill Paul  * Copyright (c) 1997, 1998, 1999
396f2e892SBill Paul  *	Bill Paul <wpaul@ee.columbia.edu>.  All rights reserved.
496f2e892SBill Paul  *
596f2e892SBill Paul  * Redistribution and use in source and binary forms, with or without
696f2e892SBill Paul  * modification, are permitted provided that the following conditions
796f2e892SBill Paul  * are met:
896f2e892SBill Paul  * 1. Redistributions of source code must retain the above copyright
996f2e892SBill Paul  *    notice, this list of conditions and the following disclaimer.
1096f2e892SBill Paul  * 2. Redistributions in binary form must reproduce the above copyright
1196f2e892SBill Paul  *    notice, this list of conditions and the following disclaimer in the
1296f2e892SBill Paul  *    documentation and/or other materials provided with the distribution.
1396f2e892SBill Paul  * 3. All advertising materials mentioning features or use of this software
1496f2e892SBill Paul  *    must display the following acknowledgement:
1596f2e892SBill Paul  *	This product includes software developed by Bill Paul.
1696f2e892SBill Paul  * 4. Neither the name of the author nor the names of any co-contributors
1796f2e892SBill Paul  *    may be used to endorse or promote products derived from this software
1896f2e892SBill Paul  *    without specific prior written permission.
1996f2e892SBill Paul  *
2096f2e892SBill Paul  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
2196f2e892SBill Paul  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
2296f2e892SBill Paul  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
2396f2e892SBill Paul  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
2496f2e892SBill Paul  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
2596f2e892SBill Paul  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
2696f2e892SBill Paul  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
2796f2e892SBill Paul  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
2896f2e892SBill Paul  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
2996f2e892SBill Paul  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
3096f2e892SBill Paul  * THE POSSIBILITY OF SUCH DAMAGE.
3196f2e892SBill Paul  */
3296f2e892SBill Paul 
334dc52c32SDavid E. O'Brien #include <sys/cdefs.h>
344dc52c32SDavid E. O'Brien __FBSDID("$FreeBSD$");
354dc52c32SDavid E. O'Brien 
3696f2e892SBill Paul /*
3796f2e892SBill Paul  * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143
3896f2e892SBill Paul  * series chips and several workalikes including the following:
3996f2e892SBill Paul  *
40ead7cde9SBill Paul  * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com)
4196f2e892SBill Paul  * Macronix/Lite-On 82c115 PNIC II (www.macronix.com)
4296f2e892SBill Paul  * Lite-On 82c168/82c169 PNIC (www.litecom.com)
4396f2e892SBill Paul  * ASIX Electronics AX88140A (www.asix.com.tw)
4496f2e892SBill Paul  * ASIX Electronics AX88141 (www.asix.com.tw)
4596f2e892SBill Paul  * ADMtek AL981 (www.admtek.com.tw)
4696f2e892SBill Paul  * ADMtek AN985 (www.admtek.com.tw)
474c16d09eSWarner Losh  * Netgear FA511 (www.netgear.com) Appears to be rebadged ADMTek AN985
4888d739dcSBill Paul  * Davicom DM9100, DM9102, DM9102A (www.davicom8.com)
499ca710f6SJeroen Ruigrok van der Werven  * Accton EN1217 (www.accton.com)
50feb78939SJonathan Chen  * Xircom X3201 (www.xircom.com)
511d5e5310SBill Paul  * Abocom FE2500
521af8bec7SBill Paul  * Conexant LANfinity (www.conexant.com)
537eac366bSMartin Blapp  * 3Com OfficeConnect 10/100B 3CSOHO100B (www.3com.com)
5496f2e892SBill Paul  *
5596f2e892SBill Paul  * Datasheets for the 21143 are available at developer.intel.com.
5696f2e892SBill Paul  * Datasheets for the clone parts can be found at their respective sites.
5796f2e892SBill Paul  * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.)
5896f2e892SBill Paul  * The PNIC II is essentially a Macronix 98715A chip; the only difference
5996f2e892SBill Paul  * worth noting is that its multicast hash table is only 128 bits wide
6096f2e892SBill Paul  * instead of 512.
6196f2e892SBill Paul  *
6296f2e892SBill Paul  * Written by Bill Paul <wpaul@ee.columbia.edu>
6396f2e892SBill Paul  * Electrical Engineering Department
6496f2e892SBill Paul  * Columbia University, New York City
6596f2e892SBill Paul  */
6696f2e892SBill Paul /*
6796f2e892SBill Paul  * The Intel 21143 is the successor to the DEC 21140. It is basically
6896f2e892SBill Paul  * the same as the 21140 but with a few new features. The 21143 supports
6996f2e892SBill Paul  * three kinds of media attachments:
7096f2e892SBill Paul  *
7196f2e892SBill Paul  * o MII port, for 10Mbps and 100Mbps support and NWAY
7296f2e892SBill Paul  *   autonegotiation provided by an external PHY.
7396f2e892SBill Paul  * o SYM port, for symbol mode 100Mbps support.
7496f2e892SBill Paul  * o 10baseT port.
7596f2e892SBill Paul  * o AUI/BNC port.
7696f2e892SBill Paul  *
7796f2e892SBill Paul  * The 100Mbps SYM port and 10baseT port can be used together in
7896f2e892SBill Paul  * combination with the internal NWAY support to create a 10/100
7996f2e892SBill Paul  * autosensing configuration.
8096f2e892SBill Paul  *
8196f2e892SBill Paul  * Note that not all tulip workalikes are handled in this driver: we only
8296f2e892SBill Paul  * deal with those which are relatively well behaved. The Winbond is
8396f2e892SBill Paul  * handled separately due to its different register offsets and the
8496f2e892SBill Paul  * special handling needed for its various bugs. The PNIC is handled
8596f2e892SBill Paul  * here, but I'm not thrilled about it.
8696f2e892SBill Paul  *
8796f2e892SBill Paul  * All of the workalike chips use some form of MII transceiver support
8896f2e892SBill Paul  * with the exception of the Macronix chips, which also have a SYM port.
8996f2e892SBill Paul  * The ASIX AX88140A is also documented to have a SYM port, but all
9096f2e892SBill Paul  * the cards I've seen use an MII transceiver, probably because the
9196f2e892SBill Paul  * AX88140A doesn't support internal NWAY.
9296f2e892SBill Paul  */
9396f2e892SBill Paul 
94f0796cd2SGleb Smirnoff #ifdef HAVE_KERNEL_OPTION_HEADERS
95f0796cd2SGleb Smirnoff #include "opt_device_polling.h"
96f0796cd2SGleb Smirnoff #endif
97f0796cd2SGleb Smirnoff 
9896f2e892SBill Paul #include <sys/param.h>
99af4358c7SMaxime Henrion #include <sys/endian.h>
10096f2e892SBill Paul #include <sys/systm.h>
10196f2e892SBill Paul #include <sys/sockio.h>
10296f2e892SBill Paul #include <sys/mbuf.h>
10396f2e892SBill Paul #include <sys/malloc.h>
10496f2e892SBill Paul #include <sys/kernel.h>
105f11d01c3SPoul-Henning Kamp #include <sys/module.h>
10696f2e892SBill Paul #include <sys/socket.h>
10701faf54bSLuigi Rizzo #include <sys/sysctl.h>
10896f2e892SBill Paul 
10996f2e892SBill Paul #include <net/if.h>
11096f2e892SBill Paul #include <net/if_arp.h>
11196f2e892SBill Paul #include <net/ethernet.h>
11296f2e892SBill Paul #include <net/if_dl.h>
11396f2e892SBill Paul #include <net/if_media.h>
114db40c1aeSDoug Ambrisko #include <net/if_types.h>
115db40c1aeSDoug Ambrisko #include <net/if_vlan_var.h>
11696f2e892SBill Paul 
11796f2e892SBill Paul #include <net/bpf.h>
11896f2e892SBill Paul 
11996f2e892SBill Paul #include <machine/bus.h>
12096f2e892SBill Paul #include <machine/resource.h>
12196f2e892SBill Paul #include <sys/bus.h>
12296f2e892SBill Paul #include <sys/rman.h>
12396f2e892SBill Paul 
12496f2e892SBill Paul #include <dev/mii/mii.h>
12596f2e892SBill Paul #include <dev/mii/miivar.h>
12696f2e892SBill Paul 
12719b7ffd1SWarner Losh #include <dev/pci/pcireg.h>
12819b7ffd1SWarner Losh #include <dev/pci/pcivar.h>
12996f2e892SBill Paul 
13096f2e892SBill Paul #define DC_USEIOSPACE
13196f2e892SBill Paul 
1326a3033a8SWarner Losh #include <dev/dc/if_dcreg.h>
13396f2e892SBill Paul 
134ec6a7299SMaxime Henrion #ifdef __sparc64__
135ec6a7299SMaxime Henrion #include <dev/ofw/openfirm.h>
136ec6a7299SMaxime Henrion #include <machine/ofw_machdep.h>
137ec6a7299SMaxime Henrion #endif
138ec6a7299SMaxime Henrion 
139f246e4a1SMatthew N. Dodd MODULE_DEPEND(dc, pci, 1, 1, 1);
140f246e4a1SMatthew N. Dodd MODULE_DEPEND(dc, ether, 1, 1, 1);
14195a16455SPeter Wemm MODULE_DEPEND(dc, miibus, 1, 1, 1);
14295a16455SPeter Wemm 
143919ccba7SWarner Losh /*
144919ccba7SWarner Losh  * "device miibus" is required in kernel config.  See GENERIC if you get
145919ccba7SWarner Losh  * errors here.
146919ccba7SWarner Losh  */
14796f2e892SBill Paul #include "miibus_if.h"
14896f2e892SBill Paul 
14996f2e892SBill Paul /*
15096f2e892SBill Paul  * Various supported device vendors/types and their names.
15196f2e892SBill Paul  */
15296f2e892SBill Paul static struct dc_type dc_devs[] = {
1531e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143), 0,
15496f2e892SBill Paul 		"Intel 21143 10/100BaseTX" },
1551e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009), 0,
15638deb45fSTom Rhodes 		"Davicom DM9009 10/100BaseTX" },
1571e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100), 0,
15896f2e892SBill Paul 		"Davicom DM9100 10/100BaseTX" },
1591e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), DC_REVISION_DM9102A,
16088d739dcSBill Paul 		"Davicom DM9102A 10/100BaseTX" },
1611e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), 0,
1621e2e70b1SJohn Baldwin 		"Davicom DM9102 10/100BaseTX" },
1631e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981), 0,
16496f2e892SBill Paul 		"ADMtek AL981 10/100BaseTX" },
1651e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985), 0,
16696f2e892SBill Paul 		"ADMtek AN985 10/100BaseTX" },
1671e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511), 0,
168e351d778SMartin Blapp 		"ADMtek ADM9511 10/100BaseTX" },
1691e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513), 0,
170e351d778SMartin Blapp 		"ADMtek ADM9513 10/100BaseTX" },
1711e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_FA511), 0,
1724c16d09eSWarner Losh 		"Netgear FA511 10/100BaseTX" },
1731e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), DC_REVISION_88141,
17496f2e892SBill Paul 		"ASIX AX88141 10/100BaseTX" },
1751e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), 0,
1761e2e70b1SJohn Baldwin 		"ASIX AX88140A 10/100BaseTX" },
1771e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), DC_REVISION_98713A,
17896f2e892SBill Paul 		"Macronix 98713A 10/100BaseTX" },
1791e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), 0,
1801e2e70b1SJohn Baldwin 		"Macronix 98713 10/100BaseTX" },
1811e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), DC_REVISION_98713A,
18296f2e892SBill Paul 		"Compex RL100-TX 10/100BaseTX" },
1831e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), 0,
18496f2e892SBill Paul 		"Compex RL100-TX 10/100BaseTX" },
1851e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98725,
18696f2e892SBill Paul 		"Macronix 98725 10/100BaseTX" },
1871e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98715AEC_C,
1881e2e70b1SJohn Baldwin 		"Macronix 98715AEC-C 10/100BaseTX" },
1891e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), 0,
1901e2e70b1SJohn Baldwin 		"Macronix 98715/98715A 10/100BaseTX" },
1911e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727), 0,
192ead7cde9SBill Paul 		"Macronix 98727/98732 10/100BaseTX" },
1931e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115), 0,
19496f2e892SBill Paul 		"LC82C115 PNIC II 10/100BaseTX" },
1951e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), DC_REVISION_82C169,
19696f2e892SBill Paul 		"82c169 PNIC 10/100BaseTX" },
1971e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), 0,
1981e2e70b1SJohn Baldwin 		"82c168 PNIC 10/100BaseTX" },
1991e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217), 0,
2009ca710f6SJeroen Ruigrok van der Werven 		"Accton EN1217 10/100BaseTX" },
2011e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242), 0,
202fa167b8eSBill Paul 		"Accton EN2242 MiniPCI 10/100BaseTX" },
2031e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201), 0,
204feb78939SJonathan Chen 	  	"Xircom X3201 10/100BaseTX" },
2051e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD), 0,
2069be0993cSJohn Baldwin 		"Neteasy DRP-32TXD Cardbus 10/100" },
2071e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500), 0,
2081d5e5310SBill Paul 		"Abocom FE2500 10/100BaseTX" },
2091e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX), 0,
210773c505fSMIHIRA Sanpei Yoshiro 		"Abocom FE2500MX 10/100BaseTX" },
2111e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112), 0,
2121af8bec7SBill Paul 		"Conexant LANfinity MiniPCI 10/100BaseTX" },
2131e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX), 0,
214948c244dSWarner Losh 		"Hawking CB102 CardBus 10/100" },
2151e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T), 0,
21697f91728SMIHIRA Sanpei Yoshiro 		"PlaneX FNW-3602-T CardBus 10/100" },
2171e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB), 0,
2187eac366bSMartin Blapp 		"3Com OfficeConnect 10/100B" },
2191e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120), 0,
220e7b9ab3aSBill Paul 		"Microsoft MN-120 CardBus 10/100" },
2211e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130), 0,
222e7b9ab3aSBill Paul 		"Microsoft MN-130 10/100" },
22396f2e892SBill Paul 	{ 0, 0, NULL }
22496f2e892SBill Paul };
22596f2e892SBill Paul 
226e51a25f8SAlfred Perlstein static int dc_probe(device_t);
227e51a25f8SAlfred Perlstein static int dc_attach(device_t);
228e51a25f8SAlfred Perlstein static int dc_detach(device_t);
229e8388e14SMitsuru IWASAKI static int dc_suspend(device_t);
230e8388e14SMitsuru IWASAKI static int dc_resume(device_t);
231e51a25f8SAlfred Perlstein static struct dc_type *dc_devtype(device_t);
23256e5e7aeSMaxime Henrion static int dc_newbuf(struct dc_softc *, int, int);
233a10c0e45SMike Silbersack static int dc_encap(struct dc_softc *, struct mbuf **);
234e51a25f8SAlfred Perlstein static void dc_pnic_rx_bug_war(struct dc_softc *, int);
235e51a25f8SAlfred Perlstein static int dc_rx_resync(struct dc_softc *);
236e51a25f8SAlfred Perlstein static void dc_rxeof(struct dc_softc *);
237e51a25f8SAlfred Perlstein static void dc_txeof(struct dc_softc *);
238e51a25f8SAlfred Perlstein static void dc_tick(void *);
239e51a25f8SAlfred Perlstein static void dc_tx_underrun(struct dc_softc *);
240e51a25f8SAlfred Perlstein static void dc_intr(void *);
241e51a25f8SAlfred Perlstein static void dc_start(struct ifnet *);
242c8b27acaSJohn Baldwin static void dc_start_locked(struct ifnet *);
243e51a25f8SAlfred Perlstein static int dc_ioctl(struct ifnet *, u_long, caddr_t);
244e51a25f8SAlfred Perlstein static void dc_init(void *);
245c8b27acaSJohn Baldwin static void dc_init_locked(struct dc_softc *);
246e51a25f8SAlfred Perlstein static void dc_stop(struct dc_softc *);
247e51a25f8SAlfred Perlstein static void dc_watchdog(struct ifnet *);
248e51a25f8SAlfred Perlstein static void dc_shutdown(device_t);
249e51a25f8SAlfred Perlstein static int dc_ifmedia_upd(struct ifnet *);
250e51a25f8SAlfred Perlstein static void dc_ifmedia_sts(struct ifnet *, struct ifmediareq *);
25196f2e892SBill Paul 
252e51a25f8SAlfred Perlstein static void dc_delay(struct dc_softc *);
253e51a25f8SAlfred Perlstein static void dc_eeprom_idle(struct dc_softc *);
254e51a25f8SAlfred Perlstein static void dc_eeprom_putbyte(struct dc_softc *, int);
255e51a25f8SAlfred Perlstein static void dc_eeprom_getword(struct dc_softc *, int, u_int16_t *);
256d24ae19dSWarner Losh static void dc_eeprom_getword_pnic(struct dc_softc *, int, u_int16_t *);
257d24ae19dSWarner Losh static void dc_eeprom_getword_xircom(struct dc_softc *, int, u_int16_t *);
2583097aa70SWarner Losh static void dc_eeprom_width(struct dc_softc *);
259e51a25f8SAlfred Perlstein static void dc_read_eeprom(struct dc_softc *, caddr_t, int, int, int);
26096f2e892SBill Paul 
261e51a25f8SAlfred Perlstein static void dc_mii_writebit(struct dc_softc *, int);
262e51a25f8SAlfred Perlstein static int dc_mii_readbit(struct dc_softc *);
263e51a25f8SAlfred Perlstein static void dc_mii_sync(struct dc_softc *);
264e51a25f8SAlfred Perlstein static void dc_mii_send(struct dc_softc *, u_int32_t, int);
265e51a25f8SAlfred Perlstein static int dc_mii_readreg(struct dc_softc *, struct dc_mii_frame *);
266e51a25f8SAlfred Perlstein static int dc_mii_writereg(struct dc_softc *, struct dc_mii_frame *);
267e51a25f8SAlfred Perlstein static int dc_miibus_readreg(device_t, int, int);
268e51a25f8SAlfred Perlstein static int dc_miibus_writereg(device_t, int, int, int);
269e51a25f8SAlfred Perlstein static void dc_miibus_statchg(device_t);
270e51a25f8SAlfred Perlstein static void dc_miibus_mediainit(device_t);
27196f2e892SBill Paul 
272e51a25f8SAlfred Perlstein static void dc_setcfg(struct dc_softc *, int);
2733373489bSWarner Losh static uint32_t dc_mchash_le(struct dc_softc *, const uint8_t *);
2743373489bSWarner Losh static uint32_t dc_mchash_be(const uint8_t *);
275e51a25f8SAlfred Perlstein static void dc_setfilt_21143(struct dc_softc *);
276e51a25f8SAlfred Perlstein static void dc_setfilt_asix(struct dc_softc *);
277e51a25f8SAlfred Perlstein static void dc_setfilt_admtek(struct dc_softc *);
278e51a25f8SAlfred Perlstein static void dc_setfilt_xircom(struct dc_softc *);
27996f2e892SBill Paul 
280e51a25f8SAlfred Perlstein static void dc_setfilt(struct dc_softc *);
28196f2e892SBill Paul 
282e51a25f8SAlfred Perlstein static void dc_reset(struct dc_softc *);
283e51a25f8SAlfred Perlstein static int dc_list_rx_init(struct dc_softc *);
284e51a25f8SAlfred Perlstein static int dc_list_tx_init(struct dc_softc *);
28596f2e892SBill Paul 
2863097aa70SWarner Losh static void dc_read_srom(struct dc_softc *, int);
287e51a25f8SAlfred Perlstein static void dc_parse_21143_srom(struct dc_softc *);
288e51a25f8SAlfred Perlstein static void dc_decode_leaf_sia(struct dc_softc *, struct dc_eblock_sia *);
289e51a25f8SAlfred Perlstein static void dc_decode_leaf_mii(struct dc_softc *, struct dc_eblock_mii *);
290e51a25f8SAlfred Perlstein static void dc_decode_leaf_sym(struct dc_softc *, struct dc_eblock_sym *);
291e51a25f8SAlfred Perlstein static void dc_apply_fixup(struct dc_softc *, int);
2925c1cfac4SBill Paul 
293d24ae19dSWarner Losh static void dc_dma_map_txbuf(void *, bus_dma_segment_t *, int, bus_size_t, int);
294d24ae19dSWarner Losh static void dc_dma_map_rxbuf(void *, bus_dma_segment_t *, int, bus_size_t, int);
29556e5e7aeSMaxime Henrion 
29696f2e892SBill Paul #ifdef DC_USEIOSPACE
29796f2e892SBill Paul #define DC_RES			SYS_RES_IOPORT
29896f2e892SBill Paul #define DC_RID			DC_PCI_CFBIO
29996f2e892SBill Paul #else
30096f2e892SBill Paul #define DC_RES			SYS_RES_MEMORY
30196f2e892SBill Paul #define DC_RID			DC_PCI_CFBMA
30296f2e892SBill Paul #endif
30396f2e892SBill Paul 
30496f2e892SBill Paul static device_method_t dc_methods[] = {
30596f2e892SBill Paul 	/* Device interface */
30696f2e892SBill Paul 	DEVMETHOD(device_probe,		dc_probe),
30796f2e892SBill Paul 	DEVMETHOD(device_attach,	dc_attach),
30896f2e892SBill Paul 	DEVMETHOD(device_detach,	dc_detach),
309e8388e14SMitsuru IWASAKI 	DEVMETHOD(device_suspend,	dc_suspend),
310e8388e14SMitsuru IWASAKI 	DEVMETHOD(device_resume,	dc_resume),
31196f2e892SBill Paul 	DEVMETHOD(device_shutdown,	dc_shutdown),
31296f2e892SBill Paul 
31396f2e892SBill Paul 	/* bus interface */
31496f2e892SBill Paul 	DEVMETHOD(bus_print_child,	bus_generic_print_child),
31596f2e892SBill Paul 	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
31696f2e892SBill Paul 
31796f2e892SBill Paul 	/* MII interface */
31896f2e892SBill Paul 	DEVMETHOD(miibus_readreg,	dc_miibus_readreg),
31996f2e892SBill Paul 	DEVMETHOD(miibus_writereg,	dc_miibus_writereg),
32096f2e892SBill Paul 	DEVMETHOD(miibus_statchg,	dc_miibus_statchg),
321f43d9309SBill Paul 	DEVMETHOD(miibus_mediainit,	dc_miibus_mediainit),
32296f2e892SBill Paul 
32396f2e892SBill Paul 	{ 0, 0 }
32496f2e892SBill Paul };
32596f2e892SBill Paul 
32696f2e892SBill Paul static driver_t dc_driver = {
32796f2e892SBill Paul 	"dc",
32896f2e892SBill Paul 	dc_methods,
32996f2e892SBill Paul 	sizeof(struct dc_softc)
33096f2e892SBill Paul };
33196f2e892SBill Paul 
33296f2e892SBill Paul static devclass_t dc_devclass;
33301faf54bSLuigi Rizzo #ifdef __i386__
33401faf54bSLuigi Rizzo static int dc_quick = 1;
335b3811c95SMaxime Henrion SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW, &dc_quick, 0,
33605992bb5SRuslan Ermilov     "do not m_devget() in dc driver");
33701faf54bSLuigi Rizzo #endif
33896f2e892SBill Paul 
339347934faSWarner Losh DRIVER_MODULE(dc, cardbus, dc_driver, dc_devclass, 0, 0);
340f246e4a1SMatthew N. Dodd DRIVER_MODULE(dc, pci, dc_driver, dc_devclass, 0, 0);
34196f2e892SBill Paul DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0);
34296f2e892SBill Paul 
34396f2e892SBill Paul #define DC_SETBIT(sc, reg, x)				\
34496f2e892SBill Paul 	CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
34596f2e892SBill Paul 
34696f2e892SBill Paul #define DC_CLRBIT(sc, reg, x)				\
34796f2e892SBill Paul 	CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
34896f2e892SBill Paul 
34996f2e892SBill Paul #define SIO_SET(x)	DC_SETBIT(sc, DC_SIO, (x))
35096f2e892SBill Paul #define SIO_CLR(x)	DC_CLRBIT(sc, DC_SIO, (x))
35196f2e892SBill Paul 
352e3d2833aSAlfred Perlstein static void
3530934f18aSMaxime Henrion dc_delay(struct dc_softc *sc)
35496f2e892SBill Paul {
35596f2e892SBill Paul 	int idx;
35696f2e892SBill Paul 
35796f2e892SBill Paul 	for (idx = (300 / 33) + 1; idx > 0; idx--)
35896f2e892SBill Paul 		CSR_READ_4(sc, DC_BUSCTL);
35996f2e892SBill Paul }
36096f2e892SBill Paul 
3612c876e15SPoul-Henning Kamp static void
3620934f18aSMaxime Henrion dc_eeprom_width(struct dc_softc *sc)
3633097aa70SWarner Losh {
3643097aa70SWarner Losh 	int i;
3653097aa70SWarner Losh 
3663097aa70SWarner Losh 	/* Force EEPROM to idle state. */
3673097aa70SWarner Losh 	dc_eeprom_idle(sc);
3683097aa70SWarner Losh 
3693097aa70SWarner Losh 	/* Enter EEPROM access mode. */
3703097aa70SWarner Losh 	CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
3713097aa70SWarner Losh 	dc_delay(sc);
3723097aa70SWarner Losh 	DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
3733097aa70SWarner Losh 	dc_delay(sc);
3743097aa70SWarner Losh 	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
3753097aa70SWarner Losh 	dc_delay(sc);
3763097aa70SWarner Losh 	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
3773097aa70SWarner Losh 	dc_delay(sc);
3783097aa70SWarner Losh 
3793097aa70SWarner Losh 	for (i = 3; i--;) {
3803097aa70SWarner Losh 		if (6 & (1 << i))
3813097aa70SWarner Losh 			DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
3823097aa70SWarner Losh 		else
3833097aa70SWarner Losh 			DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
3843097aa70SWarner Losh 		dc_delay(sc);
3853097aa70SWarner Losh 		DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
3863097aa70SWarner Losh 		dc_delay(sc);
3873097aa70SWarner Losh 		DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
3883097aa70SWarner Losh 		dc_delay(sc);
3893097aa70SWarner Losh 	}
3903097aa70SWarner Losh 
3913097aa70SWarner Losh 	for (i = 1; i <= 12; i++) {
3923097aa70SWarner Losh 		DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
3933097aa70SWarner Losh 		dc_delay(sc);
3943097aa70SWarner Losh 		if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) {
3953097aa70SWarner Losh 			DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
3963097aa70SWarner Losh 			dc_delay(sc);
3973097aa70SWarner Losh 			break;
3983097aa70SWarner Losh 		}
3993097aa70SWarner Losh 		DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
4003097aa70SWarner Losh 		dc_delay(sc);
4013097aa70SWarner Losh 	}
4023097aa70SWarner Losh 
4033097aa70SWarner Losh 	/* Turn off EEPROM access mode. */
4043097aa70SWarner Losh 	dc_eeprom_idle(sc);
4053097aa70SWarner Losh 
4063097aa70SWarner Losh 	if (i < 4 || i > 12)
4073097aa70SWarner Losh 		sc->dc_romwidth = 6;
4083097aa70SWarner Losh 	else
4093097aa70SWarner Losh 		sc->dc_romwidth = i;
4103097aa70SWarner Losh 
4113097aa70SWarner Losh 	/* Enter EEPROM access mode. */
4123097aa70SWarner Losh 	CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
4133097aa70SWarner Losh 	dc_delay(sc);
4143097aa70SWarner Losh 	DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
4153097aa70SWarner Losh 	dc_delay(sc);
4163097aa70SWarner Losh 	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
4173097aa70SWarner Losh 	dc_delay(sc);
4183097aa70SWarner Losh 	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
4193097aa70SWarner Losh 	dc_delay(sc);
4203097aa70SWarner Losh 
4213097aa70SWarner Losh 	/* Turn off EEPROM access mode. */
4223097aa70SWarner Losh 	dc_eeprom_idle(sc);
4233097aa70SWarner Losh }
4243097aa70SWarner Losh 
425e3d2833aSAlfred Perlstein static void
4260934f18aSMaxime Henrion dc_eeprom_idle(struct dc_softc *sc)
42796f2e892SBill Paul {
4280934f18aSMaxime Henrion 	int i;
42996f2e892SBill Paul 
43096f2e892SBill Paul 	CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
43196f2e892SBill Paul 	dc_delay(sc);
43296f2e892SBill Paul 	DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
43396f2e892SBill Paul 	dc_delay(sc);
43496f2e892SBill Paul 	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
43596f2e892SBill Paul 	dc_delay(sc);
43696f2e892SBill Paul 	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
43796f2e892SBill Paul 	dc_delay(sc);
43896f2e892SBill Paul 
43996f2e892SBill Paul 	for (i = 0; i < 25; i++) {
44096f2e892SBill Paul 		DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
44196f2e892SBill Paul 		dc_delay(sc);
44296f2e892SBill Paul 		DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
44396f2e892SBill Paul 		dc_delay(sc);
44496f2e892SBill Paul 	}
44596f2e892SBill Paul 
44696f2e892SBill Paul 	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
44796f2e892SBill Paul 	dc_delay(sc);
44896f2e892SBill Paul 	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS);
44996f2e892SBill Paul 	dc_delay(sc);
45096f2e892SBill Paul 	CSR_WRITE_4(sc, DC_SIO, 0x00000000);
45196f2e892SBill Paul }
45296f2e892SBill Paul 
45396f2e892SBill Paul /*
45496f2e892SBill Paul  * Send a read command and address to the EEPROM, check for ACK.
45596f2e892SBill Paul  */
456e3d2833aSAlfred Perlstein static void
4570934f18aSMaxime Henrion dc_eeprom_putbyte(struct dc_softc *sc, int addr)
45896f2e892SBill Paul {
4590934f18aSMaxime Henrion 	int d, i;
46096f2e892SBill Paul 
4613097aa70SWarner Losh 	d = DC_EECMD_READ >> 6;
4623097aa70SWarner Losh 	for (i = 3; i--; ) {
4633097aa70SWarner Losh 		if (d & (1 << i))
4643097aa70SWarner Losh 			DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
46596f2e892SBill Paul 		else
4663097aa70SWarner Losh 			DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
4673097aa70SWarner Losh 		dc_delay(sc);
4683097aa70SWarner Losh 		DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
4693097aa70SWarner Losh 		dc_delay(sc);
4703097aa70SWarner Losh 		DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
4713097aa70SWarner Losh 		dc_delay(sc);
4723097aa70SWarner Losh 	}
47396f2e892SBill Paul 
47496f2e892SBill Paul 	/*
47596f2e892SBill Paul 	 * Feed in each bit and strobe the clock.
47696f2e892SBill Paul 	 */
4773097aa70SWarner Losh 	for (i = sc->dc_romwidth; i--;) {
4783097aa70SWarner Losh 		if (addr & (1 << i)) {
47996f2e892SBill Paul 			SIO_SET(DC_SIO_EE_DATAIN);
48096f2e892SBill Paul 		} else {
48196f2e892SBill Paul 			SIO_CLR(DC_SIO_EE_DATAIN);
48296f2e892SBill Paul 		}
48396f2e892SBill Paul 		dc_delay(sc);
48496f2e892SBill Paul 		SIO_SET(DC_SIO_EE_CLK);
48596f2e892SBill Paul 		dc_delay(sc);
48696f2e892SBill Paul 		SIO_CLR(DC_SIO_EE_CLK);
48796f2e892SBill Paul 		dc_delay(sc);
48896f2e892SBill Paul 	}
48996f2e892SBill Paul }
49096f2e892SBill Paul 
49196f2e892SBill Paul /*
49296f2e892SBill Paul  * Read a word of data stored in the EEPROM at address 'addr.'
49396f2e892SBill Paul  * The PNIC 82c168/82c169 has its own non-standard way to read
49496f2e892SBill Paul  * the EEPROM.
49596f2e892SBill Paul  */
496e3d2833aSAlfred Perlstein static void
4970934f18aSMaxime Henrion dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, u_int16_t *dest)
49896f2e892SBill Paul {
4990934f18aSMaxime Henrion 	int i;
50096f2e892SBill Paul 	u_int32_t r;
50196f2e892SBill Paul 
50296f2e892SBill Paul 	CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr);
50396f2e892SBill Paul 
50496f2e892SBill Paul 	for (i = 0; i < DC_TIMEOUT; i++) {
50596f2e892SBill Paul 		DELAY(1);
50696f2e892SBill Paul 		r = CSR_READ_4(sc, DC_SIO);
50796f2e892SBill Paul 		if (!(r & DC_PN_SIOCTL_BUSY)) {
50896f2e892SBill Paul 			*dest = (u_int16_t)(r & 0xFFFF);
50996f2e892SBill Paul 			return;
51096f2e892SBill Paul 		}
51196f2e892SBill Paul 	}
51296f2e892SBill Paul }
51396f2e892SBill Paul 
51496f2e892SBill Paul /*
51596f2e892SBill Paul  * Read a word of data stored in the EEPROM at address 'addr.'
516feb78939SJonathan Chen  * The Xircom X3201 has its own non-standard way to read
517feb78939SJonathan Chen  * the EEPROM, too.
518feb78939SJonathan Chen  */
519e3d2833aSAlfred Perlstein static void
5200934f18aSMaxime Henrion dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, u_int16_t *dest)
521feb78939SJonathan Chen {
5220934f18aSMaxime Henrion 
523feb78939SJonathan Chen 	SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ);
524feb78939SJonathan Chen 
525feb78939SJonathan Chen 	addr *= 2;
526feb78939SJonathan Chen 	CSR_WRITE_4(sc, DC_ROM, addr | 0x160);
527feb78939SJonathan Chen 	*dest = (u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff;
528feb78939SJonathan Chen 	addr += 1;
529feb78939SJonathan Chen 	CSR_WRITE_4(sc, DC_ROM, addr | 0x160);
530feb78939SJonathan Chen 	*dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8;
531feb78939SJonathan Chen 
532feb78939SJonathan Chen 	SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ);
533feb78939SJonathan Chen }
534feb78939SJonathan Chen 
535feb78939SJonathan Chen /*
536feb78939SJonathan Chen  * Read a word of data stored in the EEPROM at address 'addr.'
53796f2e892SBill Paul  */
538e3d2833aSAlfred Perlstein static void
5390934f18aSMaxime Henrion dc_eeprom_getword(struct dc_softc *sc, int addr, u_int16_t *dest)
54096f2e892SBill Paul {
5410934f18aSMaxime Henrion 	int i;
54296f2e892SBill Paul 	u_int16_t word = 0;
54396f2e892SBill Paul 
54496f2e892SBill Paul 	/* Force EEPROM to idle state. */
54596f2e892SBill Paul 	dc_eeprom_idle(sc);
54696f2e892SBill Paul 
54796f2e892SBill Paul 	/* Enter EEPROM access mode. */
54896f2e892SBill Paul 	CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
54996f2e892SBill Paul 	dc_delay(sc);
55096f2e892SBill Paul 	DC_SETBIT(sc, DC_SIO,  DC_SIO_ROMCTL_READ);
55196f2e892SBill Paul 	dc_delay(sc);
55296f2e892SBill Paul 	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
55396f2e892SBill Paul 	dc_delay(sc);
55496f2e892SBill Paul 	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
55596f2e892SBill Paul 	dc_delay(sc);
55696f2e892SBill Paul 
55796f2e892SBill Paul 	/*
55896f2e892SBill Paul 	 * Send address of word we want to read.
55996f2e892SBill Paul 	 */
56096f2e892SBill Paul 	dc_eeprom_putbyte(sc, addr);
56196f2e892SBill Paul 
56296f2e892SBill Paul 	/*
56396f2e892SBill Paul 	 * Start reading bits from EEPROM.
56496f2e892SBill Paul 	 */
56596f2e892SBill Paul 	for (i = 0x8000; i; i >>= 1) {
56696f2e892SBill Paul 		SIO_SET(DC_SIO_EE_CLK);
56796f2e892SBill Paul 		dc_delay(sc);
56896f2e892SBill Paul 		if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)
56996f2e892SBill Paul 			word |= i;
57096f2e892SBill Paul 		dc_delay(sc);
57196f2e892SBill Paul 		SIO_CLR(DC_SIO_EE_CLK);
57296f2e892SBill Paul 		dc_delay(sc);
57396f2e892SBill Paul 	}
57496f2e892SBill Paul 
57596f2e892SBill Paul 	/* Turn off EEPROM access mode. */
57696f2e892SBill Paul 	dc_eeprom_idle(sc);
57796f2e892SBill Paul 
57896f2e892SBill Paul 	*dest = word;
57996f2e892SBill Paul }
58096f2e892SBill Paul 
58196f2e892SBill Paul /*
58296f2e892SBill Paul  * Read a sequence of words from the EEPROM.
58396f2e892SBill Paul  */
584e3d2833aSAlfred Perlstein static void
5858c7ff1f3SMaxime Henrion dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int be)
58696f2e892SBill Paul {
58796f2e892SBill Paul 	int i;
58896f2e892SBill Paul 	u_int16_t word = 0, *ptr;
58996f2e892SBill Paul 
59096f2e892SBill Paul 	for (i = 0; i < cnt; i++) {
59196f2e892SBill Paul 		if (DC_IS_PNIC(sc))
59296f2e892SBill Paul 			dc_eeprom_getword_pnic(sc, off + i, &word);
593feb78939SJonathan Chen 		else if (DC_IS_XIRCOM(sc))
594feb78939SJonathan Chen 			dc_eeprom_getword_xircom(sc, off + i, &word);
59596f2e892SBill Paul 		else
59696f2e892SBill Paul 			dc_eeprom_getword(sc, off + i, &word);
59796f2e892SBill Paul 		ptr = (u_int16_t *)(dest + (i * 2));
5988c7ff1f3SMaxime Henrion 		if (be)
5998c7ff1f3SMaxime Henrion 			*ptr = be16toh(word);
60096f2e892SBill Paul 		else
6018c7ff1f3SMaxime Henrion 			*ptr = le16toh(word);
60296f2e892SBill Paul 	}
60396f2e892SBill Paul }
60496f2e892SBill Paul 
60596f2e892SBill Paul /*
60696f2e892SBill Paul  * The following two routines are taken from the Macronix 98713
60796f2e892SBill Paul  * Application Notes pp.19-21.
60896f2e892SBill Paul  */
60996f2e892SBill Paul /*
61096f2e892SBill Paul  * Write a bit to the MII bus.
61196f2e892SBill Paul  */
612e3d2833aSAlfred Perlstein static void
6130934f18aSMaxime Henrion dc_mii_writebit(struct dc_softc *sc, int bit)
61496f2e892SBill Paul {
6150934f18aSMaxime Henrion 
61696f2e892SBill Paul 	if (bit)
61796f2e892SBill Paul 		CSR_WRITE_4(sc, DC_SIO,
61896f2e892SBill Paul 		    DC_SIO_ROMCTL_WRITE | DC_SIO_MII_DATAOUT);
61996f2e892SBill Paul 	else
62096f2e892SBill Paul 		CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE);
62196f2e892SBill Paul 
62296f2e892SBill Paul 	DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK);
62396f2e892SBill Paul 	DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK);
62496f2e892SBill Paul }
62596f2e892SBill Paul 
62696f2e892SBill Paul /*
62796f2e892SBill Paul  * Read a bit from the MII bus.
62896f2e892SBill Paul  */
629e3d2833aSAlfred Perlstein static int
6300934f18aSMaxime Henrion dc_mii_readbit(struct dc_softc *sc)
63196f2e892SBill Paul {
6320934f18aSMaxime Henrion 
63396f2e892SBill Paul 	CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ | DC_SIO_MII_DIR);
63496f2e892SBill Paul 	CSR_READ_4(sc, DC_SIO);
63596f2e892SBill Paul 	DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK);
63696f2e892SBill Paul 	DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK);
63796f2e892SBill Paul 	if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN)
63896f2e892SBill Paul 		return (1);
63996f2e892SBill Paul 
64096f2e892SBill Paul 	return (0);
64196f2e892SBill Paul }
64296f2e892SBill Paul 
64396f2e892SBill Paul /*
64496f2e892SBill Paul  * Sync the PHYs by setting data bit and strobing the clock 32 times.
64596f2e892SBill Paul  */
646e3d2833aSAlfred Perlstein static void
6470934f18aSMaxime Henrion dc_mii_sync(struct dc_softc *sc)
64896f2e892SBill Paul {
6490934f18aSMaxime Henrion 	int i;
65096f2e892SBill Paul 
65196f2e892SBill Paul 	CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE);
65296f2e892SBill Paul 
65396f2e892SBill Paul 	for (i = 0; i < 32; i++)
65496f2e892SBill Paul 		dc_mii_writebit(sc, 1);
65596f2e892SBill Paul }
65696f2e892SBill Paul 
65796f2e892SBill Paul /*
65896f2e892SBill Paul  * Clock a series of bits through the MII.
65996f2e892SBill Paul  */
660e3d2833aSAlfred Perlstein static void
6610934f18aSMaxime Henrion dc_mii_send(struct dc_softc *sc, u_int32_t bits, int cnt)
66296f2e892SBill Paul {
66396f2e892SBill Paul 	int i;
66496f2e892SBill Paul 
66596f2e892SBill Paul 	for (i = (0x1 << (cnt - 1)); i; i >>= 1)
66696f2e892SBill Paul 		dc_mii_writebit(sc, bits & i);
66796f2e892SBill Paul }
66896f2e892SBill Paul 
66996f2e892SBill Paul /*
67096f2e892SBill Paul  * Read an PHY register through the MII.
67196f2e892SBill Paul  */
672e3d2833aSAlfred Perlstein static int
6730934f18aSMaxime Henrion dc_mii_readreg(struct dc_softc *sc, struct dc_mii_frame *frame)
67496f2e892SBill Paul {
675d1ce9105SBill Paul 	int i, ack;
67696f2e892SBill Paul 
67796f2e892SBill Paul 	/*
67896f2e892SBill Paul 	 * Set up frame for RX.
67996f2e892SBill Paul 	 */
68096f2e892SBill Paul 	frame->mii_stdelim = DC_MII_STARTDELIM;
68196f2e892SBill Paul 	frame->mii_opcode = DC_MII_READOP;
68296f2e892SBill Paul 	frame->mii_turnaround = 0;
68396f2e892SBill Paul 	frame->mii_data = 0;
68496f2e892SBill Paul 
68596f2e892SBill Paul 	/*
68696f2e892SBill Paul 	 * Sync the PHYs.
68796f2e892SBill Paul 	 */
68896f2e892SBill Paul 	dc_mii_sync(sc);
68996f2e892SBill Paul 
69096f2e892SBill Paul 	/*
69196f2e892SBill Paul 	 * Send command/address info.
69296f2e892SBill Paul 	 */
69396f2e892SBill Paul 	dc_mii_send(sc, frame->mii_stdelim, 2);
69496f2e892SBill Paul 	dc_mii_send(sc, frame->mii_opcode, 2);
69596f2e892SBill Paul 	dc_mii_send(sc, frame->mii_phyaddr, 5);
69696f2e892SBill Paul 	dc_mii_send(sc, frame->mii_regaddr, 5);
69796f2e892SBill Paul 
69896f2e892SBill Paul #ifdef notdef
69996f2e892SBill Paul 	/* Idle bit */
70096f2e892SBill Paul 	dc_mii_writebit(sc, 1);
70196f2e892SBill Paul 	dc_mii_writebit(sc, 0);
70296f2e892SBill Paul #endif
70396f2e892SBill Paul 
7040934f18aSMaxime Henrion 	/* Check for ack. */
70596f2e892SBill Paul 	ack = dc_mii_readbit(sc);
70696f2e892SBill Paul 
70796f2e892SBill Paul 	/*
70896f2e892SBill Paul 	 * Now try reading data bits. If the ack failed, we still
70996f2e892SBill Paul 	 * need to clock through 16 cycles to keep the PHY(s) in sync.
71096f2e892SBill Paul 	 */
71196f2e892SBill Paul 	if (ack) {
7120934f18aSMaxime Henrion 		for (i = 0; i < 16; i++)
71396f2e892SBill Paul 			dc_mii_readbit(sc);
71496f2e892SBill Paul 		goto fail;
71596f2e892SBill Paul 	}
71696f2e892SBill Paul 
71796f2e892SBill Paul 	for (i = 0x8000; i; i >>= 1) {
71896f2e892SBill Paul 		if (!ack) {
71996f2e892SBill Paul 			if (dc_mii_readbit(sc))
72096f2e892SBill Paul 				frame->mii_data |= i;
72196f2e892SBill Paul 		}
72296f2e892SBill Paul 	}
72396f2e892SBill Paul 
72496f2e892SBill Paul fail:
72596f2e892SBill Paul 
72696f2e892SBill Paul 	dc_mii_writebit(sc, 0);
72796f2e892SBill Paul 	dc_mii_writebit(sc, 0);
72896f2e892SBill Paul 
72996f2e892SBill Paul 	if (ack)
73096f2e892SBill Paul 		return (1);
73196f2e892SBill Paul 	return (0);
73296f2e892SBill Paul }
73396f2e892SBill Paul 
73496f2e892SBill Paul /*
73596f2e892SBill Paul  * Write to a PHY register through the MII.
73696f2e892SBill Paul  */
737e3d2833aSAlfred Perlstein static int
7380934f18aSMaxime Henrion dc_mii_writereg(struct dc_softc *sc, struct dc_mii_frame *frame)
73996f2e892SBill Paul {
7400934f18aSMaxime Henrion 
74196f2e892SBill Paul 	/*
74296f2e892SBill Paul 	 * Set up frame for TX.
74396f2e892SBill Paul 	 */
74496f2e892SBill Paul 
74596f2e892SBill Paul 	frame->mii_stdelim = DC_MII_STARTDELIM;
74696f2e892SBill Paul 	frame->mii_opcode = DC_MII_WRITEOP;
74796f2e892SBill Paul 	frame->mii_turnaround = DC_MII_TURNAROUND;
74896f2e892SBill Paul 
74996f2e892SBill Paul 	/*
75096f2e892SBill Paul 	 * Sync the PHYs.
75196f2e892SBill Paul 	 */
75296f2e892SBill Paul 	dc_mii_sync(sc);
75396f2e892SBill Paul 
75496f2e892SBill Paul 	dc_mii_send(sc, frame->mii_stdelim, 2);
75596f2e892SBill Paul 	dc_mii_send(sc, frame->mii_opcode, 2);
75696f2e892SBill Paul 	dc_mii_send(sc, frame->mii_phyaddr, 5);
75796f2e892SBill Paul 	dc_mii_send(sc, frame->mii_regaddr, 5);
75896f2e892SBill Paul 	dc_mii_send(sc, frame->mii_turnaround, 2);
75996f2e892SBill Paul 	dc_mii_send(sc, frame->mii_data, 16);
76096f2e892SBill Paul 
76196f2e892SBill Paul 	/* Idle bit. */
76296f2e892SBill Paul 	dc_mii_writebit(sc, 0);
76396f2e892SBill Paul 	dc_mii_writebit(sc, 0);
76496f2e892SBill Paul 
76596f2e892SBill Paul 	return (0);
76696f2e892SBill Paul }
76796f2e892SBill Paul 
768e3d2833aSAlfred Perlstein static int
7690934f18aSMaxime Henrion dc_miibus_readreg(device_t dev, int phy, int reg)
77096f2e892SBill Paul {
77196f2e892SBill Paul 	struct dc_mii_frame frame;
77296f2e892SBill Paul 	struct dc_softc	 *sc;
773c85c4667SBill Paul 	int i, rval, phy_reg = 0;
77496f2e892SBill Paul 
77596f2e892SBill Paul 	sc = device_get_softc(dev);
7760934f18aSMaxime Henrion 	bzero(&frame, sizeof(frame));
77796f2e892SBill Paul 
77896f2e892SBill Paul 	/*
77996f2e892SBill Paul 	 * Note: both the AL981 and AN985 have internal PHYs,
78096f2e892SBill Paul 	 * however the AL981 provides direct access to the PHY
78196f2e892SBill Paul 	 * registers while the AN985 uses a serial MII interface.
78296f2e892SBill Paul 	 * The AN985's MII interface is also buggy in that you
78396f2e892SBill Paul 	 * can read from any MII address (0 to 31), but only address 1
78496f2e892SBill Paul 	 * behaves normally. To deal with both cases, we pretend
78596f2e892SBill Paul 	 * that the PHY is at MII address 1.
78696f2e892SBill Paul 	 */
78796f2e892SBill Paul 	if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR)
78896f2e892SBill Paul 		return (0);
78996f2e892SBill Paul 
7901af8bec7SBill Paul 	/*
7911af8bec7SBill Paul 	 * Note: the ukphy probes of the RS7112 report a PHY at
7921af8bec7SBill Paul 	 * MII address 0 (possibly HomePNA?) and 1 (ethernet)
7931af8bec7SBill Paul 	 * so we only respond to correct one.
7941af8bec7SBill Paul 	 */
7951af8bec7SBill Paul 	if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR)
7961af8bec7SBill Paul 		return (0);
7971af8bec7SBill Paul 
7985c1cfac4SBill Paul 	if (sc->dc_pmode != DC_PMODE_MII) {
79996f2e892SBill Paul 		if (phy == (MII_NPHY - 1)) {
80096f2e892SBill Paul 			switch (reg) {
80196f2e892SBill Paul 			case MII_BMSR:
80296f2e892SBill Paul 			/*
80396f2e892SBill Paul 			 * Fake something to make the probe
80496f2e892SBill Paul 			 * code think there's a PHY here.
80596f2e892SBill Paul 			 */
80696f2e892SBill Paul 				return (BMSR_MEDIAMASK);
80796f2e892SBill Paul 				break;
80896f2e892SBill Paul 			case MII_PHYIDR1:
80996f2e892SBill Paul 				if (DC_IS_PNIC(sc))
81096f2e892SBill Paul 					return (DC_VENDORID_LO);
81196f2e892SBill Paul 				return (DC_VENDORID_DEC);
81296f2e892SBill Paul 				break;
81396f2e892SBill Paul 			case MII_PHYIDR2:
81496f2e892SBill Paul 				if (DC_IS_PNIC(sc))
81596f2e892SBill Paul 					return (DC_DEVICEID_82C168);
81696f2e892SBill Paul 				return (DC_DEVICEID_21143);
81796f2e892SBill Paul 				break;
81896f2e892SBill Paul 			default:
81996f2e892SBill Paul 				return (0);
82096f2e892SBill Paul 				break;
82196f2e892SBill Paul 			}
82296f2e892SBill Paul 		} else
82396f2e892SBill Paul 			return (0);
82496f2e892SBill Paul 	}
82596f2e892SBill Paul 
82696f2e892SBill Paul 	if (DC_IS_PNIC(sc)) {
82796f2e892SBill Paul 		CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ |
82896f2e892SBill Paul 		    (phy << 23) | (reg << 18));
82996f2e892SBill Paul 		for (i = 0; i < DC_TIMEOUT; i++) {
83096f2e892SBill Paul 			DELAY(1);
83196f2e892SBill Paul 			rval = CSR_READ_4(sc, DC_PN_MII);
83296f2e892SBill Paul 			if (!(rval & DC_PN_MII_BUSY)) {
83396f2e892SBill Paul 				rval &= 0xFFFF;
83496f2e892SBill Paul 				return (rval == 0xFFFF ? 0 : rval);
83596f2e892SBill Paul 			}
83696f2e892SBill Paul 		}
83796f2e892SBill Paul 		return (0);
83896f2e892SBill Paul 	}
83996f2e892SBill Paul 
84096f2e892SBill Paul 	if (DC_IS_COMET(sc)) {
84196f2e892SBill Paul 		switch (reg) {
84296f2e892SBill Paul 		case MII_BMCR:
84396f2e892SBill Paul 			phy_reg = DC_AL_BMCR;
84496f2e892SBill Paul 			break;
84596f2e892SBill Paul 		case MII_BMSR:
84696f2e892SBill Paul 			phy_reg = DC_AL_BMSR;
84796f2e892SBill Paul 			break;
84896f2e892SBill Paul 		case MII_PHYIDR1:
84996f2e892SBill Paul 			phy_reg = DC_AL_VENID;
85096f2e892SBill Paul 			break;
85196f2e892SBill Paul 		case MII_PHYIDR2:
85296f2e892SBill Paul 			phy_reg = DC_AL_DEVID;
85396f2e892SBill Paul 			break;
85496f2e892SBill Paul 		case MII_ANAR:
85596f2e892SBill Paul 			phy_reg = DC_AL_ANAR;
85696f2e892SBill Paul 			break;
85796f2e892SBill Paul 		case MII_ANLPAR:
85896f2e892SBill Paul 			phy_reg = DC_AL_LPAR;
85996f2e892SBill Paul 			break;
86096f2e892SBill Paul 		case MII_ANER:
86196f2e892SBill Paul 			phy_reg = DC_AL_ANER;
86296f2e892SBill Paul 			break;
86396f2e892SBill Paul 		default:
86422f6205dSJohn Baldwin 			device_printf(dev, "phy_read: bad phy register %x\n",
86522f6205dSJohn Baldwin 			    reg);
86696f2e892SBill Paul 			return (0);
86796f2e892SBill Paul 			break;
86896f2e892SBill Paul 		}
86996f2e892SBill Paul 
87096f2e892SBill Paul 		rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF;
87196f2e892SBill Paul 
87296f2e892SBill Paul 		if (rval == 0xFFFF)
87396f2e892SBill Paul 			return (0);
87496f2e892SBill Paul 		return (rval);
87596f2e892SBill Paul 	}
87696f2e892SBill Paul 
87796f2e892SBill Paul 	frame.mii_phyaddr = phy;
87896f2e892SBill Paul 	frame.mii_regaddr = reg;
879419146d9SBill Paul 	if (sc->dc_type == DC_TYPE_98713) {
880f43d9309SBill Paul 		phy_reg = CSR_READ_4(sc, DC_NETCFG);
881f43d9309SBill Paul 		CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
882419146d9SBill Paul 	}
88396f2e892SBill Paul 	dc_mii_readreg(sc, &frame);
884419146d9SBill Paul 	if (sc->dc_type == DC_TYPE_98713)
885f43d9309SBill Paul 		CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
88696f2e892SBill Paul 
88796f2e892SBill Paul 	return (frame.mii_data);
88896f2e892SBill Paul }
88996f2e892SBill Paul 
890e3d2833aSAlfred Perlstein static int
8910934f18aSMaxime Henrion dc_miibus_writereg(device_t dev, int phy, int reg, int data)
89296f2e892SBill Paul {
89396f2e892SBill Paul 	struct dc_softc *sc;
89496f2e892SBill Paul 	struct dc_mii_frame frame;
895c85c4667SBill Paul 	int i, phy_reg = 0;
89696f2e892SBill Paul 
89796f2e892SBill Paul 	sc = device_get_softc(dev);
8980934f18aSMaxime Henrion 	bzero(&frame, sizeof(frame));
89996f2e892SBill Paul 
90096f2e892SBill Paul 	if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR)
90196f2e892SBill Paul 		return (0);
90296f2e892SBill Paul 
9031af8bec7SBill Paul 	if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR)
9041af8bec7SBill Paul 		return (0);
9051af8bec7SBill Paul 
90696f2e892SBill Paul 	if (DC_IS_PNIC(sc)) {
90796f2e892SBill Paul 		CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE |
90896f2e892SBill Paul 		    (phy << 23) | (reg << 10) | data);
90996f2e892SBill Paul 		for (i = 0; i < DC_TIMEOUT; i++) {
91096f2e892SBill Paul 			if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY))
91196f2e892SBill Paul 				break;
91296f2e892SBill Paul 		}
91396f2e892SBill Paul 		return (0);
91496f2e892SBill Paul 	}
91596f2e892SBill Paul 
91696f2e892SBill Paul 	if (DC_IS_COMET(sc)) {
91796f2e892SBill Paul 		switch (reg) {
91896f2e892SBill Paul 		case MII_BMCR:
91996f2e892SBill Paul 			phy_reg = DC_AL_BMCR;
92096f2e892SBill Paul 			break;
92196f2e892SBill Paul 		case MII_BMSR:
92296f2e892SBill Paul 			phy_reg = DC_AL_BMSR;
92396f2e892SBill Paul 			break;
92496f2e892SBill Paul 		case MII_PHYIDR1:
92596f2e892SBill Paul 			phy_reg = DC_AL_VENID;
92696f2e892SBill Paul 			break;
92796f2e892SBill Paul 		case MII_PHYIDR2:
92896f2e892SBill Paul 			phy_reg = DC_AL_DEVID;
92996f2e892SBill Paul 			break;
93096f2e892SBill Paul 		case MII_ANAR:
93196f2e892SBill Paul 			phy_reg = DC_AL_ANAR;
93296f2e892SBill Paul 			break;
93396f2e892SBill Paul 		case MII_ANLPAR:
93496f2e892SBill Paul 			phy_reg = DC_AL_LPAR;
93596f2e892SBill Paul 			break;
93696f2e892SBill Paul 		case MII_ANER:
93796f2e892SBill Paul 			phy_reg = DC_AL_ANER;
93896f2e892SBill Paul 			break;
93996f2e892SBill Paul 		default:
94022f6205dSJohn Baldwin 			device_printf(dev, "phy_write: bad phy register %x\n",
94122f6205dSJohn Baldwin 			    reg);
94296f2e892SBill Paul 			return (0);
94396f2e892SBill Paul 			break;
94496f2e892SBill Paul 		}
94596f2e892SBill Paul 
94696f2e892SBill Paul 		CSR_WRITE_4(sc, phy_reg, data);
94796f2e892SBill Paul 		return (0);
94896f2e892SBill Paul 	}
94996f2e892SBill Paul 
95096f2e892SBill Paul 	frame.mii_phyaddr = phy;
95196f2e892SBill Paul 	frame.mii_regaddr = reg;
95296f2e892SBill Paul 	frame.mii_data = data;
95396f2e892SBill Paul 
954419146d9SBill Paul 	if (sc->dc_type == DC_TYPE_98713) {
955f43d9309SBill Paul 		phy_reg = CSR_READ_4(sc, DC_NETCFG);
956f43d9309SBill Paul 		CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
957419146d9SBill Paul 	}
95896f2e892SBill Paul 	dc_mii_writereg(sc, &frame);
959419146d9SBill Paul 	if (sc->dc_type == DC_TYPE_98713)
960f43d9309SBill Paul 		CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
96196f2e892SBill Paul 
96296f2e892SBill Paul 	return (0);
96396f2e892SBill Paul }
96496f2e892SBill Paul 
965e3d2833aSAlfred Perlstein static void
9660934f18aSMaxime Henrion dc_miibus_statchg(device_t dev)
96796f2e892SBill Paul {
96896f2e892SBill Paul 	struct dc_softc *sc;
96996f2e892SBill Paul 	struct mii_data *mii;
970f43d9309SBill Paul 	struct ifmedia *ifm;
97196f2e892SBill Paul 
97296f2e892SBill Paul 	sc = device_get_softc(dev);
97396f2e892SBill Paul 	if (DC_IS_ADMTEK(sc))
97496f2e892SBill Paul 		return;
9755c1cfac4SBill Paul 
97696f2e892SBill Paul 	mii = device_get_softc(sc->dc_miibus);
977f43d9309SBill Paul 	ifm = &mii->mii_media;
978f43d9309SBill Paul 	if (DC_IS_DAVICOM(sc) &&
97945521525SPoul-Henning Kamp 	    IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) {
980f43d9309SBill Paul 		dc_setcfg(sc, ifm->ifm_media);
981f43d9309SBill Paul 		sc->dc_if_media = ifm->ifm_media;
982f43d9309SBill Paul 	} else {
98396f2e892SBill Paul 		dc_setcfg(sc, mii->mii_media_active);
98496f2e892SBill Paul 		sc->dc_if_media = mii->mii_media_active;
985f43d9309SBill Paul 	}
986f43d9309SBill Paul }
987f43d9309SBill Paul 
988f43d9309SBill Paul /*
989f43d9309SBill Paul  * Special support for DM9102A cards with HomePNA PHYs. Note:
990f43d9309SBill Paul  * with the Davicom DM9102A/DM9801 eval board that I have, it seems
991f43d9309SBill Paul  * to be impossible to talk to the management interface of the DM9801
992f43d9309SBill Paul  * PHY (its MDIO pin is not connected to anything). Consequently,
993f43d9309SBill Paul  * the driver has to just 'know' about the additional mode and deal
994f43d9309SBill Paul  * with it itself. *sigh*
995f43d9309SBill Paul  */
996e3d2833aSAlfred Perlstein static void
9970934f18aSMaxime Henrion dc_miibus_mediainit(device_t dev)
998f43d9309SBill Paul {
999f43d9309SBill Paul 	struct dc_softc *sc;
1000f43d9309SBill Paul 	struct mii_data *mii;
1001f43d9309SBill Paul 	struct ifmedia *ifm;
1002f43d9309SBill Paul 	int rev;
1003f43d9309SBill Paul 
10041e2e70b1SJohn Baldwin 	rev = pci_get_revid(dev);
1005f43d9309SBill Paul 
1006f43d9309SBill Paul 	sc = device_get_softc(dev);
1007f43d9309SBill Paul 	mii = device_get_softc(sc->dc_miibus);
1008f43d9309SBill Paul 	ifm = &mii->mii_media;
1009f43d9309SBill Paul 
1010f43d9309SBill Paul 	if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A)
101145521525SPoul-Henning Kamp 		ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL);
101296f2e892SBill Paul }
101396f2e892SBill Paul 
101479d11e09SBill Paul #define DC_BITS_512	9
101579d11e09SBill Paul #define DC_BITS_128	7
101679d11e09SBill Paul #define DC_BITS_64	6
101796f2e892SBill Paul 
10183373489bSWarner Losh static uint32_t
10193373489bSWarner Losh dc_mchash_le(struct dc_softc *sc, const uint8_t *addr)
102096f2e892SBill Paul {
10213373489bSWarner Losh 	uint32_t crc;
102296f2e892SBill Paul 
102396f2e892SBill Paul 	/* Compute CRC for the address value. */
10240e939c0cSChristian Weisgerber 	crc = ether_crc32_le(addr, ETHER_ADDR_LEN);
102596f2e892SBill Paul 
102679d11e09SBill Paul 	/*
102779d11e09SBill Paul 	 * The hash table on the PNIC II and the MX98715AEC-C/D/E
102879d11e09SBill Paul 	 * chips is only 128 bits wide.
102979d11e09SBill Paul 	 */
103079d11e09SBill Paul 	if (sc->dc_flags & DC_128BIT_HASH)
103179d11e09SBill Paul 		return (crc & ((1 << DC_BITS_128) - 1));
103296f2e892SBill Paul 
103379d11e09SBill Paul 	/* The hash table on the MX98715BEC is only 64 bits wide. */
103479d11e09SBill Paul 	if (sc->dc_flags & DC_64BIT_HASH)
103579d11e09SBill Paul 		return (crc & ((1 << DC_BITS_64) - 1));
103679d11e09SBill Paul 
1037feb78939SJonathan Chen 	/* Xircom's hash filtering table is different (read: weird) */
1038feb78939SJonathan Chen 	/* Xircom uses the LEAST significant bits */
1039feb78939SJonathan Chen 	if (DC_IS_XIRCOM(sc)) {
1040feb78939SJonathan Chen 		if ((crc & 0x180) == 0x180)
10410934f18aSMaxime Henrion 			return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4));
1042feb78939SJonathan Chen 		else
10430934f18aSMaxime Henrion 			return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 +
10440934f18aSMaxime Henrion 			    (12 << 4));
1045feb78939SJonathan Chen 	}
1046feb78939SJonathan Chen 
104779d11e09SBill Paul 	return (crc & ((1 << DC_BITS_512) - 1));
104896f2e892SBill Paul }
104996f2e892SBill Paul 
105096f2e892SBill Paul /*
105196f2e892SBill Paul  * Calculate CRC of a multicast group address, return the lower 6 bits.
105296f2e892SBill Paul  */
10533373489bSWarner Losh static uint32_t
10543373489bSWarner Losh dc_mchash_be(const uint8_t *addr)
105596f2e892SBill Paul {
10560e939c0cSChristian Weisgerber 	uint32_t crc;
105796f2e892SBill Paul 
105896f2e892SBill Paul 	/* Compute CRC for the address value. */
10590e939c0cSChristian Weisgerber 	crc = ether_crc32_be(addr, ETHER_ADDR_LEN);
106096f2e892SBill Paul 
10610934f18aSMaxime Henrion 	/* Return the filter bit position. */
106296f2e892SBill Paul 	return ((crc >> 26) & 0x0000003F);
106396f2e892SBill Paul }
106496f2e892SBill Paul 
106596f2e892SBill Paul /*
106696f2e892SBill Paul  * 21143-style RX filter setup routine. Filter programming is done by
106796f2e892SBill Paul  * downloading a special setup frame into the TX engine. 21143, Macronix,
106896f2e892SBill Paul  * PNIC, PNIC II and Davicom chips are programmed this way.
106996f2e892SBill Paul  *
107096f2e892SBill Paul  * We always program the chip using 'hash perfect' mode, i.e. one perfect
107196f2e892SBill Paul  * address (our node address) and a 512-bit hash filter for multicast
107296f2e892SBill Paul  * frames. We also sneak the broadcast address into the hash filter since
107396f2e892SBill Paul  * we need that too.
107496f2e892SBill Paul  */
10752c876e15SPoul-Henning Kamp static void
10760934f18aSMaxime Henrion dc_setfilt_21143(struct dc_softc *sc)
107796f2e892SBill Paul {
10788df1ebe9SMarcel Moolenaar 	uint16_t eaddr[(ETHER_ADDR_LEN+1)/2];
107996f2e892SBill Paul 	struct dc_desc *sframe;
108096f2e892SBill Paul 	u_int32_t h, *sp;
108196f2e892SBill Paul 	struct ifmultiaddr *ifma;
108296f2e892SBill Paul 	struct ifnet *ifp;
108396f2e892SBill Paul 	int i;
108496f2e892SBill Paul 
1085fc74a9f9SBrooks Davis 	ifp = sc->dc_ifp;
108696f2e892SBill Paul 
108796f2e892SBill Paul 	i = sc->dc_cdata.dc_tx_prod;
108896f2e892SBill Paul 	DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT);
108996f2e892SBill Paul 	sc->dc_cdata.dc_tx_cnt++;
109096f2e892SBill Paul 	sframe = &sc->dc_ldata->dc_tx_list[i];
109156e5e7aeSMaxime Henrion 	sp = sc->dc_cdata.dc_sbuf;
10920934f18aSMaxime Henrion 	bzero(sp, DC_SFRAME_LEN);
109396f2e892SBill Paul 
1094af4358c7SMaxime Henrion 	sframe->dc_data = htole32(sc->dc_saddr);
1095af4358c7SMaxime Henrion 	sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP |
1096af4358c7SMaxime Henrion 	    DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT);
109796f2e892SBill Paul 
109856e5e7aeSMaxime Henrion 	sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf;
109996f2e892SBill Paul 
110096f2e892SBill Paul 	/* If we want promiscuous mode, set the allframes bit. */
110196f2e892SBill Paul 	if (ifp->if_flags & IFF_PROMISC)
110296f2e892SBill Paul 		DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
110396f2e892SBill Paul 	else
110496f2e892SBill Paul 		DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
110596f2e892SBill Paul 
110696f2e892SBill Paul 	if (ifp->if_flags & IFF_ALLMULTI)
110796f2e892SBill Paul 		DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
110896f2e892SBill Paul 	else
110996f2e892SBill Paul 		DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
111096f2e892SBill Paul 
111113b203d0SRobert Watson 	IF_ADDR_LOCK(ifp);
11126817526dSPoul-Henning Kamp 	TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
111396f2e892SBill Paul 		if (ifma->ifma_addr->sa_family != AF_LINK)
111496f2e892SBill Paul 			continue;
1115aa825502SDavid E. O'Brien 		h = dc_mchash_le(sc,
111696f2e892SBill Paul 		    LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1117af4358c7SMaxime Henrion 		sp[h >> 4] |= htole32(1 << (h & 0xF));
111896f2e892SBill Paul 	}
111913b203d0SRobert Watson 	IF_ADDR_UNLOCK(ifp);
112096f2e892SBill Paul 
112196f2e892SBill Paul 	if (ifp->if_flags & IFF_BROADCAST) {
1122aa825502SDavid E. O'Brien 		h = dc_mchash_le(sc, ifp->if_broadcastaddr);
1123af4358c7SMaxime Henrion 		sp[h >> 4] |= htole32(1 << (h & 0xF));
112496f2e892SBill Paul 	}
112596f2e892SBill Paul 
11268df1ebe9SMarcel Moolenaar 	/* Set our MAC address. */
11278df1ebe9SMarcel Moolenaar 	bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN);
11288df1ebe9SMarcel Moolenaar 	sp[39] = DC_SP_MAC(eaddr[0]);
11298df1ebe9SMarcel Moolenaar 	sp[40] = DC_SP_MAC(eaddr[1]);
11308df1ebe9SMarcel Moolenaar 	sp[41] = DC_SP_MAC(eaddr[2]);
113196f2e892SBill Paul 
1132af4358c7SMaxime Henrion 	sframe->dc_status = htole32(DC_TXSTAT_OWN);
113396f2e892SBill Paul 	CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
113496f2e892SBill Paul 
113596f2e892SBill Paul 	/*
113696f2e892SBill Paul 	 * The PNIC takes an exceedingly long time to process its
113796f2e892SBill Paul 	 * setup frame; wait 10ms after posting the setup frame
113896f2e892SBill Paul 	 * before proceeding, just so it has time to swallow its
113996f2e892SBill Paul 	 * medicine.
114096f2e892SBill Paul 	 */
114196f2e892SBill Paul 	DELAY(10000);
114296f2e892SBill Paul 
114396f2e892SBill Paul 	ifp->if_timer = 5;
114496f2e892SBill Paul }
114596f2e892SBill Paul 
11462c876e15SPoul-Henning Kamp static void
11470934f18aSMaxime Henrion dc_setfilt_admtek(struct dc_softc *sc)
114896f2e892SBill Paul {
11498df1ebe9SMarcel Moolenaar 	uint32_t eaddr[(ETHER_ADDR_LEN+3)/4];
115096f2e892SBill Paul 	struct ifnet *ifp;
11510934f18aSMaxime Henrion 	struct ifmultiaddr *ifma;
115296f2e892SBill Paul 	int h = 0;
115396f2e892SBill Paul 	u_int32_t hashes[2] = { 0, 0 };
115496f2e892SBill Paul 
1155fc74a9f9SBrooks Davis 	ifp = sc->dc_ifp;
115696f2e892SBill Paul 
11570934f18aSMaxime Henrion 	/* Init our MAC address. */
11588df1ebe9SMarcel Moolenaar 	bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN);
11598df1ebe9SMarcel Moolenaar 	CSR_WRITE_4(sc, DC_AL_PAR0, eaddr[0]);
11608df1ebe9SMarcel Moolenaar 	CSR_WRITE_4(sc, DC_AL_PAR1, eaddr[1]);
116196f2e892SBill Paul 
116296f2e892SBill Paul 	/* If we want promiscuous mode, set the allframes bit. */
116396f2e892SBill Paul 	if (ifp->if_flags & IFF_PROMISC)
116496f2e892SBill Paul 		DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
116596f2e892SBill Paul 	else
116696f2e892SBill Paul 		DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
116796f2e892SBill Paul 
116896f2e892SBill Paul 	if (ifp->if_flags & IFF_ALLMULTI)
116996f2e892SBill Paul 		DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
117096f2e892SBill Paul 	else
117196f2e892SBill Paul 		DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
117296f2e892SBill Paul 
11730934f18aSMaxime Henrion 	/* First, zot all the existing hash bits. */
117496f2e892SBill Paul 	CSR_WRITE_4(sc, DC_AL_MAR0, 0);
117596f2e892SBill Paul 	CSR_WRITE_4(sc, DC_AL_MAR1, 0);
117696f2e892SBill Paul 
117796f2e892SBill Paul 	/*
117896f2e892SBill Paul 	 * If we're already in promisc or allmulti mode, we
117996f2e892SBill Paul 	 * don't have to bother programming the multicast filter.
118096f2e892SBill Paul 	 */
118196f2e892SBill Paul 	if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI))
118296f2e892SBill Paul 		return;
118396f2e892SBill Paul 
11840934f18aSMaxime Henrion 	/* Now program new ones. */
118513b203d0SRobert Watson 	IF_ADDR_LOCK(ifp);
11866817526dSPoul-Henning Kamp 	TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
118796f2e892SBill Paul 		if (ifma->ifma_addr->sa_family != AF_LINK)
118896f2e892SBill Paul 			continue;
1189acc1bcccSMartin Blapp 		if (DC_IS_CENTAUR(sc))
1190aa825502SDavid E. O'Brien 			h = dc_mchash_le(sc,
1191aa825502SDavid E. O'Brien 			    LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1192acc1bcccSMartin Blapp 		else
1193aa825502SDavid E. O'Brien 			h = dc_mchash_be(
1194aa825502SDavid E. O'Brien 			    LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
119596f2e892SBill Paul 		if (h < 32)
119696f2e892SBill Paul 			hashes[0] |= (1 << h);
119796f2e892SBill Paul 		else
119896f2e892SBill Paul 			hashes[1] |= (1 << (h - 32));
119996f2e892SBill Paul 	}
120013b203d0SRobert Watson 	IF_ADDR_UNLOCK(ifp);
120196f2e892SBill Paul 
120296f2e892SBill Paul 	CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]);
120396f2e892SBill Paul 	CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]);
120496f2e892SBill Paul }
120596f2e892SBill Paul 
12062c876e15SPoul-Henning Kamp static void
12070934f18aSMaxime Henrion dc_setfilt_asix(struct dc_softc *sc)
120896f2e892SBill Paul {
12098df1ebe9SMarcel Moolenaar 	uint32_t eaddr[(ETHER_ADDR_LEN+3)/4];
121096f2e892SBill Paul 	struct ifnet *ifp;
12110934f18aSMaxime Henrion 	struct ifmultiaddr *ifma;
121296f2e892SBill Paul 	int h = 0;
121396f2e892SBill Paul 	u_int32_t hashes[2] = { 0, 0 };
121496f2e892SBill Paul 
1215fc74a9f9SBrooks Davis 	ifp = sc->dc_ifp;
121696f2e892SBill Paul 
12178df1ebe9SMarcel Moolenaar 	/* Init our MAC address. */
12188df1ebe9SMarcel Moolenaar 	bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN);
121996f2e892SBill Paul 	CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0);
12208df1ebe9SMarcel Moolenaar 	CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[0]);
122196f2e892SBill Paul 	CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1);
12228df1ebe9SMarcel Moolenaar 	CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[1]);
122396f2e892SBill Paul 
122496f2e892SBill Paul 	/* If we want promiscuous mode, set the allframes bit. */
122596f2e892SBill Paul 	if (ifp->if_flags & IFF_PROMISC)
122696f2e892SBill Paul 		DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
122796f2e892SBill Paul 	else
122896f2e892SBill Paul 		DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
122996f2e892SBill Paul 
123096f2e892SBill Paul 	if (ifp->if_flags & IFF_ALLMULTI)
123196f2e892SBill Paul 		DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
123296f2e892SBill Paul 	else
123396f2e892SBill Paul 		DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
123496f2e892SBill Paul 
123596f2e892SBill Paul 	/*
123696f2e892SBill Paul 	 * The ASIX chip has a special bit to enable reception
123796f2e892SBill Paul 	 * of broadcast frames.
123896f2e892SBill Paul 	 */
123996f2e892SBill Paul 	if (ifp->if_flags & IFF_BROADCAST)
124096f2e892SBill Paul 		DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD);
124196f2e892SBill Paul 	else
124296f2e892SBill Paul 		DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD);
124396f2e892SBill Paul 
124496f2e892SBill Paul 	/* first, zot all the existing hash bits */
124596f2e892SBill Paul 	CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0);
124696f2e892SBill Paul 	CSR_WRITE_4(sc, DC_AX_FILTDATA, 0);
124796f2e892SBill Paul 	CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1);
124896f2e892SBill Paul 	CSR_WRITE_4(sc, DC_AX_FILTDATA, 0);
124996f2e892SBill Paul 
125096f2e892SBill Paul 	/*
125196f2e892SBill Paul 	 * If we're already in promisc or allmulti mode, we
125296f2e892SBill Paul 	 * don't have to bother programming the multicast filter.
125396f2e892SBill Paul 	 */
125496f2e892SBill Paul 	if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI))
125596f2e892SBill Paul 		return;
125696f2e892SBill Paul 
125796f2e892SBill Paul 	/* now program new ones */
125813b203d0SRobert Watson 	IF_ADDR_LOCK(ifp);
12596817526dSPoul-Henning Kamp 	TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
126096f2e892SBill Paul 		if (ifma->ifma_addr->sa_family != AF_LINK)
126196f2e892SBill Paul 			continue;
1262aa825502SDavid E. O'Brien 		h = dc_mchash_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
126396f2e892SBill Paul 		if (h < 32)
126496f2e892SBill Paul 			hashes[0] |= (1 << h);
126596f2e892SBill Paul 		else
126696f2e892SBill Paul 			hashes[1] |= (1 << (h - 32));
126796f2e892SBill Paul 	}
126813b203d0SRobert Watson 	IF_ADDR_UNLOCK(ifp);
126996f2e892SBill Paul 
127096f2e892SBill Paul 	CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0);
127196f2e892SBill Paul 	CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]);
127296f2e892SBill Paul 	CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1);
127396f2e892SBill Paul 	CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]);
127496f2e892SBill Paul }
127596f2e892SBill Paul 
12762c876e15SPoul-Henning Kamp static void
12770934f18aSMaxime Henrion dc_setfilt_xircom(struct dc_softc *sc)
1278feb78939SJonathan Chen {
12798df1ebe9SMarcel Moolenaar 	uint16_t eaddr[(ETHER_ADDR_LEN+1)/2];
12800934f18aSMaxime Henrion 	struct ifnet *ifp;
12810934f18aSMaxime Henrion 	struct ifmultiaddr *ifma;
1282feb78939SJonathan Chen 	struct dc_desc *sframe;
1283feb78939SJonathan Chen 	u_int32_t h, *sp;
1284feb78939SJonathan Chen 	int i;
1285feb78939SJonathan Chen 
1286fc74a9f9SBrooks Davis 	ifp = sc->dc_ifp;
1287feb78939SJonathan Chen 	DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON));
1288feb78939SJonathan Chen 
1289feb78939SJonathan Chen 	i = sc->dc_cdata.dc_tx_prod;
1290feb78939SJonathan Chen 	DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT);
1291feb78939SJonathan Chen 	sc->dc_cdata.dc_tx_cnt++;
1292feb78939SJonathan Chen 	sframe = &sc->dc_ldata->dc_tx_list[i];
129356e5e7aeSMaxime Henrion 	sp = sc->dc_cdata.dc_sbuf;
12940934f18aSMaxime Henrion 	bzero(sp, DC_SFRAME_LEN);
1295feb78939SJonathan Chen 
1296af4358c7SMaxime Henrion 	sframe->dc_data = htole32(sc->dc_saddr);
1297af4358c7SMaxime Henrion 	sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP |
1298af4358c7SMaxime Henrion 	    DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT);
1299feb78939SJonathan Chen 
130056e5e7aeSMaxime Henrion 	sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf;
1301feb78939SJonathan Chen 
1302feb78939SJonathan Chen 	/* If we want promiscuous mode, set the allframes bit. */
1303feb78939SJonathan Chen 	if (ifp->if_flags & IFF_PROMISC)
1304feb78939SJonathan Chen 		DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1305feb78939SJonathan Chen 	else
1306feb78939SJonathan Chen 		DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1307feb78939SJonathan Chen 
1308feb78939SJonathan Chen 	if (ifp->if_flags & IFF_ALLMULTI)
1309feb78939SJonathan Chen 		DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1310feb78939SJonathan Chen 	else
1311feb78939SJonathan Chen 		DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1312feb78939SJonathan Chen 
131313b203d0SRobert Watson 	IF_ADDR_LOCK(ifp);
13146817526dSPoul-Henning Kamp 	TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1315feb78939SJonathan Chen 		if (ifma->ifma_addr->sa_family != AF_LINK)
1316feb78939SJonathan Chen 			continue;
1317aa825502SDavid E. O'Brien 		h = dc_mchash_le(sc,
13181d5e5310SBill Paul 		    LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1319af4358c7SMaxime Henrion 		sp[h >> 4] |= htole32(1 << (h & 0xF));
1320feb78939SJonathan Chen 	}
132113b203d0SRobert Watson 	IF_ADDR_UNLOCK(ifp);
1322feb78939SJonathan Chen 
1323feb78939SJonathan Chen 	if (ifp->if_flags & IFF_BROADCAST) {
1324aa825502SDavid E. O'Brien 		h = dc_mchash_le(sc, ifp->if_broadcastaddr);
1325af4358c7SMaxime Henrion 		sp[h >> 4] |= htole32(1 << (h & 0xF));
1326feb78939SJonathan Chen 	}
1327feb78939SJonathan Chen 
13288df1ebe9SMarcel Moolenaar 	/* Set our MAC address. */
13298df1ebe9SMarcel Moolenaar 	bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN);
13308df1ebe9SMarcel Moolenaar 	sp[0] = DC_SP_MAC(eaddr[0]);
13318df1ebe9SMarcel Moolenaar 	sp[1] = DC_SP_MAC(eaddr[1]);
13328df1ebe9SMarcel Moolenaar 	sp[2] = DC_SP_MAC(eaddr[2]);
1333feb78939SJonathan Chen 
1334feb78939SJonathan Chen 	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
1335feb78939SJonathan Chen 	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON);
133613f4c340SRobert Watson 	ifp->if_drv_flags |= IFF_DRV_RUNNING;
1337af4358c7SMaxime Henrion 	sframe->dc_status = htole32(DC_TXSTAT_OWN);
1338feb78939SJonathan Chen 	CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
1339feb78939SJonathan Chen 
1340feb78939SJonathan Chen 	/*
13410934f18aSMaxime Henrion 	 * Wait some time...
1342feb78939SJonathan Chen 	 */
1343feb78939SJonathan Chen 	DELAY(1000);
1344feb78939SJonathan Chen 
1345feb78939SJonathan Chen 	ifp->if_timer = 5;
1346feb78939SJonathan Chen }
1347feb78939SJonathan Chen 
1348e3d2833aSAlfred Perlstein static void
13490934f18aSMaxime Henrion dc_setfilt(struct dc_softc *sc)
135096f2e892SBill Paul {
13510934f18aSMaxime Henrion 
135296f2e892SBill Paul 	if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) ||
13531af8bec7SBill Paul 	    DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc))
135496f2e892SBill Paul 		dc_setfilt_21143(sc);
135596f2e892SBill Paul 
135696f2e892SBill Paul 	if (DC_IS_ASIX(sc))
135796f2e892SBill Paul 		dc_setfilt_asix(sc);
135896f2e892SBill Paul 
135996f2e892SBill Paul 	if (DC_IS_ADMTEK(sc))
136096f2e892SBill Paul 		dc_setfilt_admtek(sc);
136196f2e892SBill Paul 
1362feb78939SJonathan Chen 	if (DC_IS_XIRCOM(sc))
1363feb78939SJonathan Chen 		dc_setfilt_xircom(sc);
136496f2e892SBill Paul }
136596f2e892SBill Paul 
136696f2e892SBill Paul /*
13670934f18aSMaxime Henrion  * In order to fiddle with the 'full-duplex' and '100Mbps' bits in
13680934f18aSMaxime Henrion  * the netconfig register, we first have to put the transmit and/or
13690934f18aSMaxime Henrion  * receive logic in the idle state.
137096f2e892SBill Paul  */
1371e3d2833aSAlfred Perlstein static void
13720934f18aSMaxime Henrion dc_setcfg(struct dc_softc *sc, int media)
137396f2e892SBill Paul {
13740934f18aSMaxime Henrion 	int i, restart = 0, watchdogreg;
137596f2e892SBill Paul 	u_int32_t isr;
137696f2e892SBill Paul 
137796f2e892SBill Paul 	if (IFM_SUBTYPE(media) == IFM_NONE)
137896f2e892SBill Paul 		return;
137996f2e892SBill Paul 
138096f2e892SBill Paul 	if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) {
138196f2e892SBill Paul 		restart = 1;
138296f2e892SBill Paul 		DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON));
138396f2e892SBill Paul 
138496f2e892SBill Paul 		for (i = 0; i < DC_TIMEOUT; i++) {
138596f2e892SBill Paul 			isr = CSR_READ_4(sc, DC_ISR);
1386d467c136SBill Paul 			if (isr & DC_ISR_TX_IDLE &&
1387351267c1SMartin Blapp 			    ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED ||
1388351267c1SMartin Blapp 			    (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT))
138996f2e892SBill Paul 				break;
1390d467c136SBill Paul 			DELAY(10);
139196f2e892SBill Paul 		}
139296f2e892SBill Paul 
139396f2e892SBill Paul 		if (i == DC_TIMEOUT)
139422f6205dSJohn Baldwin 			if_printf(sc->dc_ifp,
139522f6205dSJohn Baldwin 			    "failed to force tx and rx to idle state\n");
139696f2e892SBill Paul 	}
139796f2e892SBill Paul 
139896f2e892SBill Paul 	if (IFM_SUBTYPE(media) == IFM_100_TX) {
1399042c8f6eSBill Paul 		DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1400042c8f6eSBill Paul 		DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
140196f2e892SBill Paul 		if (sc->dc_pmode == DC_PMODE_MII) {
1402bf645417SBill Paul 			if (DC_IS_INTEL(sc)) {
14030934f18aSMaxime Henrion 			/* There's a write enable bit here that reads as 1. */
14048273d5f8SBill Paul 				watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
14058273d5f8SBill Paul 				watchdogreg &= ~DC_WDOG_CTLWREN;
14068273d5f8SBill Paul 				watchdogreg |= DC_WDOG_JABBERDIS;
14074c2efe27SBill Paul 				CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
1408bf645417SBill Paul 			} else {
1409bf645417SBill Paul 				DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
1410bf645417SBill Paul 			}
141196f2e892SBill Paul 			DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS |
141296f2e892SBill Paul 			    DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER));
141396f2e892SBill Paul 			if (sc->dc_type == DC_TYPE_98713)
141496f2e892SBill Paul 				DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS |
141596f2e892SBill Paul 				    DC_NETCFG_SCRAMBLER));
141688d739dcSBill Paul 			if (!DC_IS_DAVICOM(sc))
141796f2e892SBill Paul 				DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
141896f2e892SBill Paul 			DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1419e99285a4SBill Paul 			if (DC_IS_INTEL(sc))
1420e99285a4SBill Paul 				dc_apply_fixup(sc, IFM_AUTO);
142196f2e892SBill Paul 		} else {
142296f2e892SBill Paul 			if (DC_IS_PNIC(sc)) {
142396f2e892SBill Paul 				DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL);
142496f2e892SBill Paul 				DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
142596f2e892SBill Paul 				DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
142696f2e892SBill Paul 			}
1427318b02fdSBill Paul 			DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1428318b02fdSBill Paul 			DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1429318b02fdSBill Paul 			DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
14305c1cfac4SBill Paul 			if (DC_IS_INTEL(sc))
14315c1cfac4SBill Paul 				dc_apply_fixup(sc,
14325c1cfac4SBill Paul 				    (media & IFM_GMASK) == IFM_FDX ?
14335c1cfac4SBill Paul 				    IFM_100_TX | IFM_FDX : IFM_100_TX);
143496f2e892SBill Paul 		}
143596f2e892SBill Paul 	}
143696f2e892SBill Paul 
143796f2e892SBill Paul 	if (IFM_SUBTYPE(media) == IFM_10_T) {
1438042c8f6eSBill Paul 		DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1439042c8f6eSBill Paul 		DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
144096f2e892SBill Paul 		if (sc->dc_pmode == DC_PMODE_MII) {
14410934f18aSMaxime Henrion 			/* There's a write enable bit here that reads as 1. */
14424c2efe27SBill Paul 			if (DC_IS_INTEL(sc)) {
14438273d5f8SBill Paul 				watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
14448273d5f8SBill Paul 				watchdogreg &= ~DC_WDOG_CTLWREN;
14458273d5f8SBill Paul 				watchdogreg |= DC_WDOG_JABBERDIS;
14468273d5f8SBill Paul 				CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
14474c2efe27SBill Paul 			} else {
14484c2efe27SBill Paul 				DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
14494c2efe27SBill Paul 			}
145096f2e892SBill Paul 			DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS |
145196f2e892SBill Paul 			    DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER));
145296f2e892SBill Paul 			if (sc->dc_type == DC_TYPE_98713)
145396f2e892SBill Paul 				DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
145488d739dcSBill Paul 			if (!DC_IS_DAVICOM(sc))
145596f2e892SBill Paul 				DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
145696f2e892SBill Paul 			DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1457e99285a4SBill Paul 			if (DC_IS_INTEL(sc))
1458e99285a4SBill Paul 				dc_apply_fixup(sc, IFM_AUTO);
145996f2e892SBill Paul 		} else {
146096f2e892SBill Paul 			if (DC_IS_PNIC(sc)) {
146196f2e892SBill Paul 				DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL);
146296f2e892SBill Paul 				DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
146396f2e892SBill Paul 				DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
146496f2e892SBill Paul 			}
146596f2e892SBill Paul 			DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1466318b02fdSBill Paul 			DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
146796f2e892SBill Paul 			DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
14685c1cfac4SBill Paul 			if (DC_IS_INTEL(sc)) {
14695c1cfac4SBill Paul 				DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET);
14705c1cfac4SBill Paul 				DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
14715c1cfac4SBill Paul 				if ((media & IFM_GMASK) == IFM_FDX)
14725c1cfac4SBill Paul 					DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D);
14735c1cfac4SBill Paul 				else
14745c1cfac4SBill Paul 					DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F);
14755c1cfac4SBill Paul 				DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
14765c1cfac4SBill Paul 				DC_CLRBIT(sc, DC_10BTCTRL,
14775c1cfac4SBill Paul 				    DC_TCTL_AUTONEGENBL);
14785c1cfac4SBill Paul 				dc_apply_fixup(sc,
14795c1cfac4SBill Paul 				    (media & IFM_GMASK) == IFM_FDX ?
14805c1cfac4SBill Paul 				    IFM_10_T | IFM_FDX : IFM_10_T);
14815c1cfac4SBill Paul 				DELAY(20000);
14825c1cfac4SBill Paul 			}
148396f2e892SBill Paul 		}
148496f2e892SBill Paul 	}
148596f2e892SBill Paul 
1486f43d9309SBill Paul 	/*
1487f43d9309SBill Paul 	 * If this is a Davicom DM9102A card with a DM9801 HomePNA
1488f43d9309SBill Paul 	 * PHY and we want HomePNA mode, set the portsel bit to turn
1489f43d9309SBill Paul 	 * on the external MII port.
1490f43d9309SBill Paul 	 */
1491f43d9309SBill Paul 	if (DC_IS_DAVICOM(sc)) {
149245521525SPoul-Henning Kamp 		if (IFM_SUBTYPE(media) == IFM_HPNA_1) {
1493f43d9309SBill Paul 			DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1494f43d9309SBill Paul 			sc->dc_link = 1;
1495f43d9309SBill Paul 		} else {
1496f43d9309SBill Paul 			DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1497f43d9309SBill Paul 		}
1498f43d9309SBill Paul 	}
1499f43d9309SBill Paul 
150096f2e892SBill Paul 	if ((media & IFM_GMASK) == IFM_FDX) {
150196f2e892SBill Paul 		DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
150296f2e892SBill Paul 		if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
150396f2e892SBill Paul 			DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
150496f2e892SBill Paul 	} else {
150596f2e892SBill Paul 		DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
150696f2e892SBill Paul 		if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
150796f2e892SBill Paul 			DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
150896f2e892SBill Paul 	}
150996f2e892SBill Paul 
151096f2e892SBill Paul 	if (restart)
151196f2e892SBill Paul 		DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON | DC_NETCFG_RX_ON);
151296f2e892SBill Paul }
151396f2e892SBill Paul 
1514e3d2833aSAlfred Perlstein static void
15150934f18aSMaxime Henrion dc_reset(struct dc_softc *sc)
151696f2e892SBill Paul {
15170934f18aSMaxime Henrion 	int i;
151896f2e892SBill Paul 
151996f2e892SBill Paul 	DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
152096f2e892SBill Paul 
152196f2e892SBill Paul 	for (i = 0; i < DC_TIMEOUT; i++) {
152296f2e892SBill Paul 		DELAY(10);
152396f2e892SBill Paul 		if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET))
152496f2e892SBill Paul 			break;
152596f2e892SBill Paul 	}
152696f2e892SBill Paul 
15271af8bec7SBill Paul 	if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) ||
15281d5e5310SBill Paul 	    DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) {
152996f2e892SBill Paul 		DELAY(10000);
153096f2e892SBill Paul 		DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
153196f2e892SBill Paul 		i = 0;
153296f2e892SBill Paul 	}
153396f2e892SBill Paul 
153496f2e892SBill Paul 	if (i == DC_TIMEOUT)
153522f6205dSJohn Baldwin 		if_printf(sc->dc_ifp, "reset never completed!\n");
153696f2e892SBill Paul 
153796f2e892SBill Paul 	/* Wait a little while for the chip to get its brains in order. */
153896f2e892SBill Paul 	DELAY(1000);
153996f2e892SBill Paul 
154096f2e892SBill Paul 	CSR_WRITE_4(sc, DC_IMR, 0x00000000);
154196f2e892SBill Paul 	CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000);
154296f2e892SBill Paul 	CSR_WRITE_4(sc, DC_NETCFG, 0x00000000);
154396f2e892SBill Paul 
154491cc2adbSBill Paul 	/*
154591cc2adbSBill Paul 	 * Bring the SIA out of reset. In some cases, it looks
154691cc2adbSBill Paul 	 * like failing to unreset the SIA soon enough gets it
154791cc2adbSBill Paul 	 * into a state where it will never come out of reset
154891cc2adbSBill Paul 	 * until we reset the whole chip again.
154991cc2adbSBill Paul 	 */
15505c1cfac4SBill Paul 	if (DC_IS_INTEL(sc)) {
155191cc2adbSBill Paul 		DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
15525c1cfac4SBill Paul 		CSR_WRITE_4(sc, DC_10BTCTRL, 0);
15535c1cfac4SBill Paul 		CSR_WRITE_4(sc, DC_WATCHDOG, 0);
15545c1cfac4SBill Paul 	}
155596f2e892SBill Paul }
155696f2e892SBill Paul 
1557e3d2833aSAlfred Perlstein static struct dc_type *
15580934f18aSMaxime Henrion dc_devtype(device_t dev)
155996f2e892SBill Paul {
156096f2e892SBill Paul 	struct dc_type *t;
15611e2e70b1SJohn Baldwin 	u_int32_t devid;
15621e2e70b1SJohn Baldwin 	u_int8_t rev;
156396f2e892SBill Paul 
156496f2e892SBill Paul 	t = dc_devs;
15651e2e70b1SJohn Baldwin 	devid = pci_get_devid(dev);
15661e2e70b1SJohn Baldwin 	rev = pci_get_revid(dev);
156796f2e892SBill Paul 
156896f2e892SBill Paul 	while (t->dc_name != NULL) {
15691e2e70b1SJohn Baldwin 		if (devid == t->dc_devid && rev >= t->dc_minrev)
157096f2e892SBill Paul 			return (t);
157196f2e892SBill Paul 		t++;
157296f2e892SBill Paul 	}
157396f2e892SBill Paul 
157496f2e892SBill Paul 	return (NULL);
157596f2e892SBill Paul }
157696f2e892SBill Paul 
157796f2e892SBill Paul /*
157896f2e892SBill Paul  * Probe for a 21143 or clone chip. Check the PCI vendor and device
157996f2e892SBill Paul  * IDs against our list and return a device name if we find a match.
158096f2e892SBill Paul  * We do a little bit of extra work to identify the exact type of
158196f2e892SBill Paul  * chip. The MX98713 and MX98713A have the same PCI vendor/device ID,
158296f2e892SBill Paul  * but different revision IDs. The same is true for 98715/98715A
158396f2e892SBill Paul  * chips and the 98725, as well as the ASIX and ADMtek chips. In some
158496f2e892SBill Paul  * cases, the exact chip revision affects driver behavior.
158596f2e892SBill Paul  */
1586e3d2833aSAlfred Perlstein static int
15870934f18aSMaxime Henrion dc_probe(device_t dev)
158896f2e892SBill Paul {
158996f2e892SBill Paul 	struct dc_type *t;
159096f2e892SBill Paul 
159196f2e892SBill Paul 	t = dc_devtype(dev);
159296f2e892SBill Paul 
159396f2e892SBill Paul 	if (t != NULL) {
159496f2e892SBill Paul 		device_set_desc(dev, t->dc_name);
1595d701c913SWarner Losh 		return (BUS_PROBE_DEFAULT);
159696f2e892SBill Paul 	}
159796f2e892SBill Paul 
159896f2e892SBill Paul 	return (ENXIO);
159996f2e892SBill Paul }
160096f2e892SBill Paul 
1601e3d2833aSAlfred Perlstein static void
16020934f18aSMaxime Henrion dc_apply_fixup(struct dc_softc *sc, int media)
16035c1cfac4SBill Paul {
16045c1cfac4SBill Paul 	struct dc_mediainfo *m;
16055c1cfac4SBill Paul 	u_int8_t *p;
16065c1cfac4SBill Paul 	int i;
16075d801891SBill Paul 	u_int32_t reg;
16085c1cfac4SBill Paul 
16095c1cfac4SBill Paul 	m = sc->dc_mi;
16105c1cfac4SBill Paul 
16115c1cfac4SBill Paul 	while (m != NULL) {
16125c1cfac4SBill Paul 		if (m->dc_media == media)
16135c1cfac4SBill Paul 			break;
16145c1cfac4SBill Paul 		m = m->dc_next;
16155c1cfac4SBill Paul 	}
16165c1cfac4SBill Paul 
16175c1cfac4SBill Paul 	if (m == NULL)
16185c1cfac4SBill Paul 		return;
16195c1cfac4SBill Paul 
16205c1cfac4SBill Paul 	for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) {
16215c1cfac4SBill Paul 		reg = (p[0] | (p[1] << 8)) << 16;
16225c1cfac4SBill Paul 		CSR_WRITE_4(sc, DC_WATCHDOG, reg);
16235c1cfac4SBill Paul 	}
16245c1cfac4SBill Paul 
16255c1cfac4SBill Paul 	for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) {
16265c1cfac4SBill Paul 		reg = (p[0] | (p[1] << 8)) << 16;
16275c1cfac4SBill Paul 		CSR_WRITE_4(sc, DC_WATCHDOG, reg);
16285c1cfac4SBill Paul 	}
16295c1cfac4SBill Paul }
16305c1cfac4SBill Paul 
1631e3d2833aSAlfred Perlstein static void
16320934f18aSMaxime Henrion dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l)
16335c1cfac4SBill Paul {
16345c1cfac4SBill Paul 	struct dc_mediainfo *m;
16355c1cfac4SBill Paul 
16360934f18aSMaxime Henrion 	m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO);
163787f4fa15SMartin Blapp 	switch (l->dc_sia_code & ~DC_SIA_CODE_EXT) {
163887f4fa15SMartin Blapp 	case DC_SIA_CODE_10BT:
16395c1cfac4SBill Paul 		m->dc_media = IFM_10_T;
164087f4fa15SMartin Blapp 		break;
164187f4fa15SMartin Blapp 	case DC_SIA_CODE_10BT_FDX:
16425c1cfac4SBill Paul 		m->dc_media = IFM_10_T | IFM_FDX;
164387f4fa15SMartin Blapp 		break;
164487f4fa15SMartin Blapp 	case DC_SIA_CODE_10B2:
16455c1cfac4SBill Paul 		m->dc_media = IFM_10_2;
164687f4fa15SMartin Blapp 		break;
164787f4fa15SMartin Blapp 	case DC_SIA_CODE_10B5:
16485c1cfac4SBill Paul 		m->dc_media = IFM_10_5;
164987f4fa15SMartin Blapp 		break;
165087f4fa15SMartin Blapp 	default:
165187f4fa15SMartin Blapp 		break;
165287f4fa15SMartin Blapp 	}
16535c1cfac4SBill Paul 
165487f4fa15SMartin Blapp 	/*
165587f4fa15SMartin Blapp 	 * We need to ignore CSR13, CSR14, CSR15 for SIA mode.
165687f4fa15SMartin Blapp 	 * Things apparently already work for cards that do
165787f4fa15SMartin Blapp 	 * supply Media Specific Data.
165887f4fa15SMartin Blapp 	 */
165987f4fa15SMartin Blapp 	if (l->dc_sia_code & DC_SIA_CODE_EXT) {
16605c1cfac4SBill Paul 		m->dc_gp_len = 2;
166187f4fa15SMartin Blapp 		m->dc_gp_ptr =
166287f4fa15SMartin Blapp 		(u_int8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl;
166387f4fa15SMartin Blapp 	} else {
166487f4fa15SMartin Blapp 		m->dc_gp_len = 2;
166587f4fa15SMartin Blapp 		m->dc_gp_ptr =
166687f4fa15SMartin Blapp 		(u_int8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl;
166787f4fa15SMartin Blapp 	}
16685c1cfac4SBill Paul 
16695c1cfac4SBill Paul 	m->dc_next = sc->dc_mi;
16705c1cfac4SBill Paul 	sc->dc_mi = m;
16715c1cfac4SBill Paul 
16725c1cfac4SBill Paul 	sc->dc_pmode = DC_PMODE_SIA;
16735c1cfac4SBill Paul }
16745c1cfac4SBill Paul 
1675e3d2833aSAlfred Perlstein static void
16760934f18aSMaxime Henrion dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l)
16775c1cfac4SBill Paul {
16785c1cfac4SBill Paul 	struct dc_mediainfo *m;
16795c1cfac4SBill Paul 
16800934f18aSMaxime Henrion 	m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO);
16815c1cfac4SBill Paul 	if (l->dc_sym_code == DC_SYM_CODE_100BT)
16825c1cfac4SBill Paul 		m->dc_media = IFM_100_TX;
16835c1cfac4SBill Paul 
16845c1cfac4SBill Paul 	if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX)
16855c1cfac4SBill Paul 		m->dc_media = IFM_100_TX | IFM_FDX;
16865c1cfac4SBill Paul 
16875c1cfac4SBill Paul 	m->dc_gp_len = 2;
16885c1cfac4SBill Paul 	m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl;
16895c1cfac4SBill Paul 
16905c1cfac4SBill Paul 	m->dc_next = sc->dc_mi;
16915c1cfac4SBill Paul 	sc->dc_mi = m;
16925c1cfac4SBill Paul 
16935c1cfac4SBill Paul 	sc->dc_pmode = DC_PMODE_SYM;
16945c1cfac4SBill Paul }
16955c1cfac4SBill Paul 
1696e3d2833aSAlfred Perlstein static void
16970934f18aSMaxime Henrion dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l)
16985c1cfac4SBill Paul {
16995c1cfac4SBill Paul 	struct dc_mediainfo *m;
17000934f18aSMaxime Henrion 	u_int8_t *p;
17015c1cfac4SBill Paul 
17020934f18aSMaxime Henrion 	m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO);
17035c1cfac4SBill Paul 	/* We abuse IFM_AUTO to represent MII. */
17045c1cfac4SBill Paul 	m->dc_media = IFM_AUTO;
17055c1cfac4SBill Paul 	m->dc_gp_len = l->dc_gpr_len;
17065c1cfac4SBill Paul 
17075c1cfac4SBill Paul 	p = (u_int8_t *)l;
17085c1cfac4SBill Paul 	p += sizeof(struct dc_eblock_mii);
17095c1cfac4SBill Paul 	m->dc_gp_ptr = p;
17105c1cfac4SBill Paul 	p += 2 * l->dc_gpr_len;
17115c1cfac4SBill Paul 	m->dc_reset_len = *p;
17125c1cfac4SBill Paul 	p++;
17135c1cfac4SBill Paul 	m->dc_reset_ptr = p;
17145c1cfac4SBill Paul 
17155c1cfac4SBill Paul 	m->dc_next = sc->dc_mi;
17165c1cfac4SBill Paul 	sc->dc_mi = m;
17175c1cfac4SBill Paul }
17185c1cfac4SBill Paul 
17192c876e15SPoul-Henning Kamp static void
17200934f18aSMaxime Henrion dc_read_srom(struct dc_softc *sc, int bits)
17213097aa70SWarner Losh {
17223097aa70SWarner Losh 	int size;
17233097aa70SWarner Losh 
17243097aa70SWarner Losh 	size = 2 << bits;
17253097aa70SWarner Losh 	sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT);
17263097aa70SWarner Losh 	dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0);
17273097aa70SWarner Losh }
17283097aa70SWarner Losh 
1729e3d2833aSAlfred Perlstein static void
17300934f18aSMaxime Henrion dc_parse_21143_srom(struct dc_softc *sc)
17315c1cfac4SBill Paul {
17325c1cfac4SBill Paul 	struct dc_leaf_hdr *lhdr;
17335c1cfac4SBill Paul 	struct dc_eblock_hdr *hdr;
17340934f18aSMaxime Henrion 	int have_mii, i, loff;
17355c1cfac4SBill Paul 	char *ptr;
17365c1cfac4SBill Paul 
1737f956e0b3SMartin Blapp 	have_mii = 0;
17385c1cfac4SBill Paul 	loff = sc->dc_srom[27];
17395c1cfac4SBill Paul 	lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]);
17405c1cfac4SBill Paul 
17415c1cfac4SBill Paul 	ptr = (char *)lhdr;
17425c1cfac4SBill Paul 	ptr += sizeof(struct dc_leaf_hdr) - 1;
1743f956e0b3SMartin Blapp 	/*
1744f956e0b3SMartin Blapp 	 * Look if we got a MII media block.
1745f956e0b3SMartin Blapp 	 */
1746f956e0b3SMartin Blapp 	for (i = 0; i < lhdr->dc_mcnt; i++) {
1747f956e0b3SMartin Blapp 		hdr = (struct dc_eblock_hdr *)ptr;
1748f956e0b3SMartin Blapp 		if (hdr->dc_type == DC_EBLOCK_MII)
1749f956e0b3SMartin Blapp 		    have_mii++;
1750f956e0b3SMartin Blapp 
1751f956e0b3SMartin Blapp 		ptr += (hdr->dc_len & 0x7F);
1752f956e0b3SMartin Blapp 		ptr++;
1753f956e0b3SMartin Blapp 	}
1754f956e0b3SMartin Blapp 
1755f956e0b3SMartin Blapp 	/*
1756f956e0b3SMartin Blapp 	 * Do the same thing again. Only use SIA and SYM media
1757f956e0b3SMartin Blapp 	 * blocks if no MII media block is available.
1758f956e0b3SMartin Blapp 	 */
1759f956e0b3SMartin Blapp 	ptr = (char *)lhdr;
1760f956e0b3SMartin Blapp 	ptr += sizeof(struct dc_leaf_hdr) - 1;
17615c1cfac4SBill Paul 	for (i = 0; i < lhdr->dc_mcnt; i++) {
17625c1cfac4SBill Paul 		hdr = (struct dc_eblock_hdr *)ptr;
17635c1cfac4SBill Paul 		switch (hdr->dc_type) {
17645c1cfac4SBill Paul 		case DC_EBLOCK_MII:
17655c1cfac4SBill Paul 			dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr);
17665c1cfac4SBill Paul 			break;
17675c1cfac4SBill Paul 		case DC_EBLOCK_SIA:
1768f956e0b3SMartin Blapp 			if (! have_mii)
1769f956e0b3SMartin Blapp 				dc_decode_leaf_sia(sc,
1770f956e0b3SMartin Blapp 				    (struct dc_eblock_sia *)hdr);
17715c1cfac4SBill Paul 			break;
17725c1cfac4SBill Paul 		case DC_EBLOCK_SYM:
1773f956e0b3SMartin Blapp 			if (! have_mii)
1774f956e0b3SMartin Blapp 				dc_decode_leaf_sym(sc,
1775f956e0b3SMartin Blapp 				    (struct dc_eblock_sym *)hdr);
17765c1cfac4SBill Paul 			break;
17775c1cfac4SBill Paul 		default:
17785c1cfac4SBill Paul 			/* Don't care. Yet. */
17795c1cfac4SBill Paul 			break;
17805c1cfac4SBill Paul 		}
17815c1cfac4SBill Paul 		ptr += (hdr->dc_len & 0x7F);
17825c1cfac4SBill Paul 		ptr++;
17835c1cfac4SBill Paul 	}
17845c1cfac4SBill Paul }
17855c1cfac4SBill Paul 
178656e5e7aeSMaxime Henrion static void
178756e5e7aeSMaxime Henrion dc_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
178856e5e7aeSMaxime Henrion {
178956e5e7aeSMaxime Henrion 	u_int32_t *paddr;
179056e5e7aeSMaxime Henrion 
179156e5e7aeSMaxime Henrion 	KASSERT(nseg == 1, ("wrong number of segments, should be 1"));
179256e5e7aeSMaxime Henrion 	paddr = arg;
179356e5e7aeSMaxime Henrion 	*paddr = segs->ds_addr;
179456e5e7aeSMaxime Henrion }
179556e5e7aeSMaxime Henrion 
179696f2e892SBill Paul /*
179796f2e892SBill Paul  * Attach the interface. Allocate softc structures, do ifmedia
179896f2e892SBill Paul  * setup and ethernet/BPF attach.
179996f2e892SBill Paul  */
1800e3d2833aSAlfred Perlstein static int
18010934f18aSMaxime Henrion dc_attach(device_t dev)
180296f2e892SBill Paul {
1803d1ce9105SBill Paul 	int tmp = 0;
18048df1ebe9SMarcel Moolenaar 	uint32_t eaddr[(ETHER_ADDR_LEN+3)/4];
180596f2e892SBill Paul 	u_int32_t command;
180696f2e892SBill Paul 	struct dc_softc *sc;
180796f2e892SBill Paul 	struct ifnet *ifp;
180896f2e892SBill Paul 	u_int32_t revision;
180922f6205dSJohn Baldwin 	int error = 0, rid, mac_offset;
181056e5e7aeSMaxime Henrion 	int i;
1811e7b01d07SWarner Losh 	u_int8_t *mac;
181296f2e892SBill Paul 
181396f2e892SBill Paul 	sc = device_get_softc(dev);
181496f2e892SBill Paul 
18156008862bSJohn Baldwin 	mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1816c8b27acaSJohn Baldwin 	    MTX_DEF);
1817c3e7434fSWarner Losh 
181896f2e892SBill Paul 	/*
181996f2e892SBill Paul 	 * Map control/status registers.
182096f2e892SBill Paul 	 */
182107f65363SBill Paul 	pci_enable_busmaster(dev);
182296f2e892SBill Paul 
182396f2e892SBill Paul 	rid = DC_RID;
18245f96beb9SNate Lawson 	sc->dc_res = bus_alloc_resource_any(dev, DC_RES, &rid, RF_ACTIVE);
182596f2e892SBill Paul 
182696f2e892SBill Paul 	if (sc->dc_res == NULL) {
182722f6205dSJohn Baldwin 		device_printf(dev, "couldn't map ports/memory\n");
182896f2e892SBill Paul 		error = ENXIO;
1829608654d4SNate Lawson 		goto fail;
183096f2e892SBill Paul 	}
183196f2e892SBill Paul 
183296f2e892SBill Paul 	sc->dc_btag = rman_get_bustag(sc->dc_res);
183396f2e892SBill Paul 	sc->dc_bhandle = rman_get_bushandle(sc->dc_res);
183496f2e892SBill Paul 
18350934f18aSMaxime Henrion 	/* Allocate interrupt. */
183654f1f1d1SNate Lawson 	rid = 0;
18375f96beb9SNate Lawson 	sc->dc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
183854f1f1d1SNate Lawson 	    RF_SHAREABLE | RF_ACTIVE);
183954f1f1d1SNate Lawson 
184054f1f1d1SNate Lawson 	if (sc->dc_irq == NULL) {
184122f6205dSJohn Baldwin 		device_printf(dev, "couldn't map interrupt\n");
184254f1f1d1SNate Lawson 		error = ENXIO;
184354f1f1d1SNate Lawson 		goto fail;
184454f1f1d1SNate Lawson 	}
184554f1f1d1SNate Lawson 
184696f2e892SBill Paul 	/* Need this info to decide on a chip type. */
184796f2e892SBill Paul 	sc->dc_info = dc_devtype(dev);
18481e2e70b1SJohn Baldwin 	revision = pci_get_revid(dev);
184996f2e892SBill Paul 
18506d0dd931SWarner Losh 	/* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */
18511e2e70b1SJohn Baldwin 	if (sc->dc_info->dc_devid !=
18521e2e70b1SJohn Baldwin 	    DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168) &&
18531e2e70b1SJohn Baldwin 	    sc->dc_info->dc_devid !=
18541e2e70b1SJohn Baldwin 	    DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201))
1855eecb3844SMartin Blapp 		dc_eeprom_width(sc);
1856eecb3844SMartin Blapp 
18571e2e70b1SJohn Baldwin 	switch (sc->dc_info->dc_devid) {
18581e2e70b1SJohn Baldwin 	case DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143):
185996f2e892SBill Paul 		sc->dc_type = DC_TYPE_21143;
186096f2e892SBill Paul 		sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR;
1861042c8f6eSBill Paul 		sc->dc_flags |= DC_REDUCED_MII_POLL;
18625c1cfac4SBill Paul 		/* Save EEPROM contents so we can parse them later. */
18633097aa70SWarner Losh 		dc_read_srom(sc, sc->dc_romwidth);
186496f2e892SBill Paul 		break;
18651e2e70b1SJohn Baldwin 	case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009):
18661e2e70b1SJohn Baldwin 	case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100):
18671e2e70b1SJohn Baldwin 	case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102):
186896f2e892SBill Paul 		sc->dc_type = DC_TYPE_DM9102;
1869318a72d7SBill Paul 		sc->dc_flags |= DC_TX_COALESCE | DC_TX_INTR_ALWAYS;
1870318a72d7SBill Paul 		sc->dc_flags |= DC_REDUCED_MII_POLL | DC_TX_STORENFWD;
18717dfdc26cSMartin Blapp 		sc->dc_flags |= DC_TX_ALIGN;
18724a80e74bSMartin Blapp 		sc->dc_pmode = DC_PMODE_MII;
18731e2e70b1SJohn Baldwin 
18740a46b1dcSBill Paul 		/* Increase the latency timer value. */
18751e2e70b1SJohn Baldwin 		pci_write_config(dev, PCIR_LATTIMER, 0x80, 1);
187696f2e892SBill Paul 		break;
18771e2e70b1SJohn Baldwin 	case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981):
187896f2e892SBill Paul 		sc->dc_type = DC_TYPE_AL981;
187996f2e892SBill Paul 		sc->dc_flags |= DC_TX_USE_TX_INTR;
188096f2e892SBill Paul 		sc->dc_flags |= DC_TX_ADMTEK_WAR;
188196f2e892SBill Paul 		sc->dc_pmode = DC_PMODE_MII;
18823097aa70SWarner Losh 		dc_read_srom(sc, sc->dc_romwidth);
188396f2e892SBill Paul 		break;
18841e2e70b1SJohn Baldwin 	case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985):
18851e2e70b1SJohn Baldwin 	case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511):
18861e2e70b1SJohn Baldwin 	case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513):
18871e2e70b1SJohn Baldwin 	case DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD):
18881e2e70b1SJohn Baldwin 	case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_FA511):
18891e2e70b1SJohn Baldwin 	case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500):
18901e2e70b1SJohn Baldwin 	case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX):
18911e2e70b1SJohn Baldwin 	case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242):
18921e2e70b1SJohn Baldwin 	case DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX):
18931e2e70b1SJohn Baldwin 	case DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T):
18941e2e70b1SJohn Baldwin 	case DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB):
18951e2e70b1SJohn Baldwin 	case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120):
18961e2e70b1SJohn Baldwin 	case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130):
189796f2e892SBill Paul 		sc->dc_type = DC_TYPE_AN985;
1898acc1bcccSMartin Blapp 		sc->dc_flags |= DC_64BIT_HASH;
189996f2e892SBill Paul 		sc->dc_flags |= DC_TX_USE_TX_INTR;
190096f2e892SBill Paul 		sc->dc_flags |= DC_TX_ADMTEK_WAR;
190196f2e892SBill Paul 		sc->dc_pmode = DC_PMODE_MII;
1902129eaf79SMartin Blapp 		/* Don't read SROM for - auto-loaded on reset */
190396f2e892SBill Paul 		break;
19041e2e70b1SJohn Baldwin 	case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713):
19051e2e70b1SJohn Baldwin 	case DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP):
190696f2e892SBill Paul 		if (revision < DC_REVISION_98713A) {
190796f2e892SBill Paul 			sc->dc_type = DC_TYPE_98713;
190896f2e892SBill Paul 		}
1909318b02fdSBill Paul 		if (revision >= DC_REVISION_98713A) {
191096f2e892SBill Paul 			sc->dc_type = DC_TYPE_98713A;
1911318b02fdSBill Paul 			sc->dc_flags |= DC_21143_NWAY;
1912318b02fdSBill Paul 		}
1913318b02fdSBill Paul 		sc->dc_flags |= DC_REDUCED_MII_POLL;
191496f2e892SBill Paul 		sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR;
191596f2e892SBill Paul 		break;
19161e2e70b1SJohn Baldwin 	case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5):
19171e2e70b1SJohn Baldwin 	case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217):
191879d11e09SBill Paul 		/*
191979d11e09SBill Paul 		 * Macronix MX98715AEC-C/D/E parts have only a
192079d11e09SBill Paul 		 * 128-bit hash table. We need to deal with these
192179d11e09SBill Paul 		 * in the same manner as the PNIC II so that we
192279d11e09SBill Paul 		 * get the right number of bits out of the
192379d11e09SBill Paul 		 * CRC routine.
192479d11e09SBill Paul 		 */
192579d11e09SBill Paul 		if (revision >= DC_REVISION_98715AEC_C &&
192679d11e09SBill Paul 		    revision < DC_REVISION_98725)
192779d11e09SBill Paul 			sc->dc_flags |= DC_128BIT_HASH;
192896f2e892SBill Paul 		sc->dc_type = DC_TYPE_987x5;
192996f2e892SBill Paul 		sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR;
1930318b02fdSBill Paul 		sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY;
193196f2e892SBill Paul 		break;
19321e2e70b1SJohn Baldwin 	case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727):
1933ead7cde9SBill Paul 		sc->dc_type = DC_TYPE_987x5;
1934ead7cde9SBill Paul 		sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR;
1935ead7cde9SBill Paul 		sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY;
1936ead7cde9SBill Paul 		break;
19371e2e70b1SJohn Baldwin 	case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115):
193896f2e892SBill Paul 		sc->dc_type = DC_TYPE_PNICII;
193979d11e09SBill Paul 		sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR | DC_128BIT_HASH;
1940318b02fdSBill Paul 		sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY;
194196f2e892SBill Paul 		break;
19421e2e70b1SJohn Baldwin 	case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168):
194396f2e892SBill Paul 		sc->dc_type = DC_TYPE_PNIC;
194491cc2adbSBill Paul 		sc->dc_flags |= DC_TX_STORENFWD | DC_TX_INTR_ALWAYS;
194596f2e892SBill Paul 		sc->dc_flags |= DC_PNIC_RX_BUG_WAR;
194696f2e892SBill Paul 		sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT);
194796f2e892SBill Paul 		if (revision < DC_REVISION_82C169)
194896f2e892SBill Paul 			sc->dc_pmode = DC_PMODE_SYM;
194996f2e892SBill Paul 		break;
19501e2e70b1SJohn Baldwin 	case DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A):
195196f2e892SBill Paul 		sc->dc_type = DC_TYPE_ASIX;
195296f2e892SBill Paul 		sc->dc_flags |= DC_TX_USE_TX_INTR | DC_TX_INTR_FIRSTFRAG;
195396f2e892SBill Paul 		sc->dc_flags |= DC_REDUCED_MII_POLL;
195496f2e892SBill Paul 		sc->dc_pmode = DC_PMODE_MII;
195596f2e892SBill Paul 		break;
19561e2e70b1SJohn Baldwin 	case DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201):
1957feb78939SJonathan Chen 		sc->dc_type = DC_TYPE_XIRCOM;
19582dfc960aSLuigi Rizzo 		sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE |
19592dfc960aSLuigi Rizzo 				DC_TX_ALIGN;
1960feb78939SJonathan Chen 		/*
1961feb78939SJonathan Chen 		 * We don't actually need to coalesce, but we're doing
1962feb78939SJonathan Chen 		 * it to obtain a double word aligned buffer.
19632dfc960aSLuigi Rizzo 		 * The DC_TX_COALESCE flag is required.
1964feb78939SJonathan Chen 		 */
19653097aa70SWarner Losh 		sc->dc_pmode = DC_PMODE_MII;
1966feb78939SJonathan Chen 		break;
19671e2e70b1SJohn Baldwin 	case DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112):
19681af8bec7SBill Paul 		sc->dc_type = DC_TYPE_CONEXANT;
19691af8bec7SBill Paul 		sc->dc_flags |= DC_TX_INTR_ALWAYS;
19701af8bec7SBill Paul 		sc->dc_flags |= DC_REDUCED_MII_POLL;
19711af8bec7SBill Paul 		sc->dc_pmode = DC_PMODE_MII;
19723097aa70SWarner Losh 		dc_read_srom(sc, sc->dc_romwidth);
19731af8bec7SBill Paul 		break;
197496f2e892SBill Paul 	default:
19751e2e70b1SJohn Baldwin 		device_printf(dev, "unknown device: %x\n",
19761e2e70b1SJohn Baldwin 		    sc->dc_info->dc_devid);
197796f2e892SBill Paul 		break;
197896f2e892SBill Paul 	}
197996f2e892SBill Paul 
198096f2e892SBill Paul 	/* Save the cache line size. */
198188d739dcSBill Paul 	if (DC_IS_DAVICOM(sc))
198288d739dcSBill Paul 		sc->dc_cachesize = 0;
198388d739dcSBill Paul 	else
19841e2e70b1SJohn Baldwin 		sc->dc_cachesize = pci_get_cachelnsz(dev);
198596f2e892SBill Paul 
198696f2e892SBill Paul 	/* Reset the adapter. */
198796f2e892SBill Paul 	dc_reset(sc);
198896f2e892SBill Paul 
198996f2e892SBill Paul 	/* Take 21143 out of snooze mode */
1990feb78939SJonathan Chen 	if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) {
199196f2e892SBill Paul 		command = pci_read_config(dev, DC_PCI_CFDD, 4);
199296f2e892SBill Paul 		command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE);
199396f2e892SBill Paul 		pci_write_config(dev, DC_PCI_CFDD, command, 4);
199496f2e892SBill Paul 	}
199596f2e892SBill Paul 
199696f2e892SBill Paul 	/*
199796f2e892SBill Paul 	 * Try to learn something about the supported media.
199896f2e892SBill Paul 	 * We know that ASIX and ADMtek and Davicom devices
199996f2e892SBill Paul 	 * will *always* be using MII media, so that's a no-brainer.
200096f2e892SBill Paul 	 * The tricky ones are the Macronix/PNIC II and the
200196f2e892SBill Paul 	 * Intel 21143.
200296f2e892SBill Paul 	 */
20035c1cfac4SBill Paul 	if (DC_IS_INTEL(sc))
20045c1cfac4SBill Paul 		dc_parse_21143_srom(sc);
20055c1cfac4SBill Paul 	else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) {
200696f2e892SBill Paul 		if (sc->dc_type == DC_TYPE_98713)
200796f2e892SBill Paul 			sc->dc_pmode = DC_PMODE_MII;
200896f2e892SBill Paul 		else
200996f2e892SBill Paul 			sc->dc_pmode = DC_PMODE_SYM;
201096f2e892SBill Paul 	} else if (!sc->dc_pmode)
201196f2e892SBill Paul 		sc->dc_pmode = DC_PMODE_MII;
201296f2e892SBill Paul 
201396f2e892SBill Paul 	/*
201496f2e892SBill Paul 	 * Get station address from the EEPROM.
201596f2e892SBill Paul 	 */
201696f2e892SBill Paul 	switch(sc->dc_type) {
201796f2e892SBill Paul 	case DC_TYPE_98713:
201896f2e892SBill Paul 	case DC_TYPE_98713A:
201996f2e892SBill Paul 	case DC_TYPE_987x5:
202096f2e892SBill Paul 	case DC_TYPE_PNICII:
202196f2e892SBill Paul 		dc_read_eeprom(sc, (caddr_t)&mac_offset,
202296f2e892SBill Paul 		    (DC_EE_NODEADDR_OFFSET / 2), 1, 0);
202396f2e892SBill Paul 		dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0);
202496f2e892SBill Paul 		break;
202596f2e892SBill Paul 	case DC_TYPE_PNIC:
202696f2e892SBill Paul 		dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1);
202796f2e892SBill Paul 		break;
202896f2e892SBill Paul 	case DC_TYPE_DM9102:
2029ec6a7299SMaxime Henrion 		dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2030ec6a7299SMaxime Henrion #ifdef __sparc64__
2031ec6a7299SMaxime Henrion 		/*
2032ec6a7299SMaxime Henrion 		 * If this is an onboard dc(4) the station address read from
2033802cab03SMarius Strobl 		 * the EEPROM is all zero and we have to get it from the FCode.
2034ec6a7299SMaxime Henrion 		 */
2035802cab03SMarius Strobl 		if (eaddr[0] == 0 && (eaddr[1] & ~0xffff) == 0)
20368069c79dSRuslan Ermilov 			OF_getetheraddr(dev, (caddr_t)&eaddr);
2037ec6a7299SMaxime Henrion #endif
2038ec6a7299SMaxime Henrion 		break;
203996f2e892SBill Paul 	case DC_TYPE_21143:
204096f2e892SBill Paul 	case DC_TYPE_ASIX:
204196f2e892SBill Paul 		dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
204296f2e892SBill Paul 		break;
204396f2e892SBill Paul 	case DC_TYPE_AL981:
204496f2e892SBill Paul 	case DC_TYPE_AN985:
20458df1ebe9SMarcel Moolenaar 		eaddr[0] = CSR_READ_4(sc, DC_AL_PAR0);
20468df1ebe9SMarcel Moolenaar 		eaddr[1] = CSR_READ_4(sc, DC_AL_PAR1);
204796f2e892SBill Paul 		break;
20481af8bec7SBill Paul 	case DC_TYPE_CONEXANT:
20490934f18aSMaxime Henrion 		bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr,
20500934f18aSMaxime Henrion 		    ETHER_ADDR_LEN);
20511af8bec7SBill Paul 		break;
2052feb78939SJonathan Chen 	case DC_TYPE_XIRCOM:
20530934f18aSMaxime Henrion 		/* The MAC comes from the CIS. */
2054e7b01d07SWarner Losh 		mac = pci_get_ether(dev);
2055e7b01d07SWarner Losh 		if (!mac) {
2056e7b01d07SWarner Losh 			device_printf(dev, "No station address in CIS!\n");
2057608654d4SNate Lawson 			error = ENXIO;
2058e7b01d07SWarner Losh 			goto fail;
2059e7b01d07SWarner Losh 		}
2060e7b01d07SWarner Losh 		bcopy(mac, eaddr, ETHER_ADDR_LEN);
2061feb78939SJonathan Chen 		break;
206296f2e892SBill Paul 	default:
206396f2e892SBill Paul 		dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
206496f2e892SBill Paul 		break;
206596f2e892SBill Paul 	}
206696f2e892SBill Paul 
206756e5e7aeSMaxime Henrion 	/* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */
206856e5e7aeSMaxime Henrion 	error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT,
206956e5e7aeSMaxime Henrion 	    BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct dc_list_data), 1,
207056e5e7aeSMaxime Henrion 	    sizeof(struct dc_list_data), 0, NULL, NULL, &sc->dc_ltag);
207156e5e7aeSMaxime Henrion 	if (error) {
207222f6205dSJohn Baldwin 		device_printf(dev, "failed to allocate busdma tag\n");
207356e5e7aeSMaxime Henrion 		error = ENXIO;
207456e5e7aeSMaxime Henrion 		goto fail;
207556e5e7aeSMaxime Henrion 	}
207656e5e7aeSMaxime Henrion 	error = bus_dmamem_alloc(sc->dc_ltag, (void **)&sc->dc_ldata,
2077aafb3ebbSMaxime Henrion 	    BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->dc_lmap);
207856e5e7aeSMaxime Henrion 	if (error) {
207922f6205dSJohn Baldwin 		device_printf(dev, "failed to allocate DMA safe memory\n");
208056e5e7aeSMaxime Henrion 		error = ENXIO;
208156e5e7aeSMaxime Henrion 		goto fail;
208256e5e7aeSMaxime Henrion 	}
208356e5e7aeSMaxime Henrion 	error = bus_dmamap_load(sc->dc_ltag, sc->dc_lmap, sc->dc_ldata,
208456e5e7aeSMaxime Henrion 	    sizeof(struct dc_list_data), dc_dma_map_addr, &sc->dc_laddr,
208556e5e7aeSMaxime Henrion 	    BUS_DMA_NOWAIT);
208656e5e7aeSMaxime Henrion 	if (error) {
208722f6205dSJohn Baldwin 		device_printf(dev, "cannot get address of the descriptors\n");
208856e5e7aeSMaxime Henrion 		error = ENXIO;
208956e5e7aeSMaxime Henrion 		goto fail;
209056e5e7aeSMaxime Henrion 	}
209196f2e892SBill Paul 
209256e5e7aeSMaxime Henrion 	/*
209356e5e7aeSMaxime Henrion 	 * Allocate a busdma tag and DMA safe memory for the multicast
209456e5e7aeSMaxime Henrion 	 * setup frame.
209556e5e7aeSMaxime Henrion 	 */
209656e5e7aeSMaxime Henrion 	error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT,
209756e5e7aeSMaxime Henrion 	    BUS_SPACE_MAXADDR, NULL, NULL, DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1,
209856e5e7aeSMaxime Henrion 	    DC_SFRAME_LEN + DC_MIN_FRAMELEN, 0, NULL, NULL, &sc->dc_stag);
209956e5e7aeSMaxime Henrion 	if (error) {
210022f6205dSJohn Baldwin 		device_printf(dev, "failed to allocate busdma tag\n");
210156e5e7aeSMaxime Henrion 		error = ENXIO;
210256e5e7aeSMaxime Henrion 		goto fail;
210356e5e7aeSMaxime Henrion 	}
210456e5e7aeSMaxime Henrion 	error = bus_dmamem_alloc(sc->dc_stag, (void **)&sc->dc_cdata.dc_sbuf,
210556e5e7aeSMaxime Henrion 	    BUS_DMA_NOWAIT, &sc->dc_smap);
210656e5e7aeSMaxime Henrion 	if (error) {
210722f6205dSJohn Baldwin 		device_printf(dev, "failed to allocate DMA safe memory\n");
210856e5e7aeSMaxime Henrion 		error = ENXIO;
210956e5e7aeSMaxime Henrion 		goto fail;
211056e5e7aeSMaxime Henrion 	}
211156e5e7aeSMaxime Henrion 	error = bus_dmamap_load(sc->dc_stag, sc->dc_smap, sc->dc_cdata.dc_sbuf,
211256e5e7aeSMaxime Henrion 	    DC_SFRAME_LEN, dc_dma_map_addr, &sc->dc_saddr, BUS_DMA_NOWAIT);
211356e5e7aeSMaxime Henrion 	if (error) {
211422f6205dSJohn Baldwin 		device_printf(dev, "cannot get address of the descriptors\n");
211596f2e892SBill Paul 		error = ENXIO;
211696f2e892SBill Paul 		goto fail;
211796f2e892SBill Paul 	}
211896f2e892SBill Paul 
211956e5e7aeSMaxime Henrion 	/* Allocate a busdma tag for mbufs. */
2120c1b677aaSScott Long 	error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT,
2121ab0d8702SScott Long 	    BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, DC_TX_LIST_CNT, MCLBYTES,
2122c1b677aaSScott Long 	    0, NULL, NULL, &sc->dc_mtag);
212356e5e7aeSMaxime Henrion 	if (error) {
212422f6205dSJohn Baldwin 		device_printf(dev, "failed to allocate busdma tag\n");
212556e5e7aeSMaxime Henrion 		error = ENXIO;
212656e5e7aeSMaxime Henrion 		goto fail;
212756e5e7aeSMaxime Henrion 	}
212856e5e7aeSMaxime Henrion 
212956e5e7aeSMaxime Henrion 	/* Create the TX/RX busdma maps. */
213056e5e7aeSMaxime Henrion 	for (i = 0; i < DC_TX_LIST_CNT; i++) {
213156e5e7aeSMaxime Henrion 		error = bus_dmamap_create(sc->dc_mtag, 0,
213256e5e7aeSMaxime Henrion 		    &sc->dc_cdata.dc_tx_map[i]);
213356e5e7aeSMaxime Henrion 		if (error) {
213422f6205dSJohn Baldwin 			device_printf(dev, "failed to init TX ring\n");
213556e5e7aeSMaxime Henrion 			error = ENXIO;
213656e5e7aeSMaxime Henrion 			goto fail;
213756e5e7aeSMaxime Henrion 		}
213856e5e7aeSMaxime Henrion 	}
213956e5e7aeSMaxime Henrion 	for (i = 0; i < DC_RX_LIST_CNT; i++) {
214056e5e7aeSMaxime Henrion 		error = bus_dmamap_create(sc->dc_mtag, 0,
214156e5e7aeSMaxime Henrion 		    &sc->dc_cdata.dc_rx_map[i]);
214256e5e7aeSMaxime Henrion 		if (error) {
214322f6205dSJohn Baldwin 			device_printf(dev, "failed to init RX ring\n");
214456e5e7aeSMaxime Henrion 			error = ENXIO;
214556e5e7aeSMaxime Henrion 			goto fail;
214656e5e7aeSMaxime Henrion 		}
214756e5e7aeSMaxime Henrion 	}
214856e5e7aeSMaxime Henrion 	error = bus_dmamap_create(sc->dc_mtag, 0, &sc->dc_sparemap);
214956e5e7aeSMaxime Henrion 	if (error) {
215022f6205dSJohn Baldwin 		device_printf(dev, "failed to init RX ring\n");
215156e5e7aeSMaxime Henrion 		error = ENXIO;
215256e5e7aeSMaxime Henrion 		goto fail;
215356e5e7aeSMaxime Henrion 	}
215496f2e892SBill Paul 
2155fc74a9f9SBrooks Davis 	ifp = sc->dc_ifp = if_alloc(IFT_ETHER);
2156fc74a9f9SBrooks Davis 	if (ifp == NULL) {
215722f6205dSJohn Baldwin 		device_printf(dev, "can not if_alloc()\n");
2158fc74a9f9SBrooks Davis 		error = ENOSPC;
2159fc74a9f9SBrooks Davis 		goto fail;
2160fc74a9f9SBrooks Davis 	}
216196f2e892SBill Paul 	ifp->if_softc = sc;
21629bf40edeSBrooks Davis 	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2163feb78939SJonathan Chen 	/* XXX: bleah, MTU gets overwritten in ether_ifattach() */
216496f2e892SBill Paul 	ifp->if_mtu = ETHERMTU;
21653d57a2e5SBrian Feldman 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
216696f2e892SBill Paul 	ifp->if_ioctl = dc_ioctl;
216796f2e892SBill Paul 	ifp->if_start = dc_start;
216896f2e892SBill Paul 	ifp->if_watchdog = dc_watchdog;
216996f2e892SBill Paul 	ifp->if_init = dc_init;
2170cbaf877fSBrian Feldman 	IFQ_SET_MAXLEN(&ifp->if_snd, DC_TX_LIST_CNT - 1);
2171cbaf877fSBrian Feldman 	ifp->if_snd.ifq_drv_maxlen = DC_TX_LIST_CNT - 1;
2172cbaf877fSBrian Feldman 	IFQ_SET_READY(&ifp->if_snd);
217396f2e892SBill Paul 
217496f2e892SBill Paul 	/*
21755c1cfac4SBill Paul 	 * Do MII setup. If this is a 21143, check for a PHY on the
21765c1cfac4SBill Paul 	 * MII bus after applying any necessary fixups to twiddle the
21775c1cfac4SBill Paul 	 * GPIO bits. If we don't end up finding a PHY, restore the
21785c1cfac4SBill Paul 	 * old selection (SIA only or SIA/SYM) and attach the dcphy
21795c1cfac4SBill Paul 	 * driver instead.
218096f2e892SBill Paul 	 */
21815c1cfac4SBill Paul 	if (DC_IS_INTEL(sc)) {
21825c1cfac4SBill Paul 		dc_apply_fixup(sc, IFM_AUTO);
21835c1cfac4SBill Paul 		tmp = sc->dc_pmode;
21845c1cfac4SBill Paul 		sc->dc_pmode = DC_PMODE_MII;
21855c1cfac4SBill Paul 	}
21865c1cfac4SBill Paul 
21876d431b17SWarner Losh 	/*
21886d431b17SWarner Losh 	 * Setup General Purpose port mode and data so the tulip can talk
21896d431b17SWarner Losh 	 * to the MII.  This needs to be done before mii_phy_probe so that
21906d431b17SWarner Losh 	 * we can actually see them.
21916d431b17SWarner Losh 	 */
21926d431b17SWarner Losh 	if (DC_IS_XIRCOM(sc)) {
21936d431b17SWarner Losh 		CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN |
21946d431b17SWarner Losh 		    DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
21956d431b17SWarner Losh 		DELAY(10);
21966d431b17SWarner Losh 		CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN |
21976d431b17SWarner Losh 		    DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
21986d431b17SWarner Losh 		DELAY(10);
21996d431b17SWarner Losh 	}
22006d431b17SWarner Losh 
220196f2e892SBill Paul 	error = mii_phy_probe(dev, &sc->dc_miibus,
220296f2e892SBill Paul 	    dc_ifmedia_upd, dc_ifmedia_sts);
220396f2e892SBill Paul 
220496f2e892SBill Paul 	if (error && DC_IS_INTEL(sc)) {
22055c1cfac4SBill Paul 		sc->dc_pmode = tmp;
22065c1cfac4SBill Paul 		if (sc->dc_pmode != DC_PMODE_SIA)
220796f2e892SBill Paul 			sc->dc_pmode = DC_PMODE_SYM;
2208042c8f6eSBill Paul 		sc->dc_flags |= DC_21143_NWAY;
220996f2e892SBill Paul 		mii_phy_probe(dev, &sc->dc_miibus,
221096f2e892SBill Paul 		    dc_ifmedia_upd, dc_ifmedia_sts);
221178999dd1SBill Paul 		/*
221278999dd1SBill Paul 		 * For non-MII cards, we need to have the 21143
221378999dd1SBill Paul 		 * drive the LEDs. Except there are some systems
221478999dd1SBill Paul 		 * like the NEC VersaPro NoteBook PC which have no
221578999dd1SBill Paul 		 * LEDs, and twiddling these bits has adverse effects
221678999dd1SBill Paul 		 * on them. (I.e. you suddenly can't get a link.)
221778999dd1SBill Paul 		 */
22181e2e70b1SJohn Baldwin 		if (!(pci_get_subvendor(dev) == 0x1033 &&
22191e2e70b1SJohn Baldwin 		    pci_get_subdevice(dev) == 0x8028))
222078999dd1SBill Paul 			sc->dc_flags |= DC_TULIP_LEDS;
222196f2e892SBill Paul 		error = 0;
222296f2e892SBill Paul 	}
222396f2e892SBill Paul 
222496f2e892SBill Paul 	if (error) {
222522f6205dSJohn Baldwin 		device_printf(dev, "MII without any PHY!\n");
222696f2e892SBill Paul 		goto fail;
222796f2e892SBill Paul 	}
222896f2e892SBill Paul 
2229028a8491SMartin Blapp 	if (DC_IS_ADMTEK(sc)) {
2230028a8491SMartin Blapp 		/*
2231028a8491SMartin Blapp 		 * Set automatic TX underrun recovery for the ADMtek chips
2232028a8491SMartin Blapp 		 */
2233028a8491SMartin Blapp 		DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR);
2234028a8491SMartin Blapp 	}
2235028a8491SMartin Blapp 
223696f2e892SBill Paul 	/*
2237db40c1aeSDoug Ambrisko 	 * Tell the upper layer(s) we support long frames.
2238db40c1aeSDoug Ambrisko 	 */
2239db40c1aeSDoug Ambrisko 	ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
22409ef8b520SSam Leffler 	ifp->if_capabilities |= IFCAP_VLAN_MTU;
224140929967SGleb Smirnoff 	ifp->if_capenable = ifp->if_capabilities;
2242e695984eSRuslan Ermilov #ifdef DEVICE_POLLING
2243e695984eSRuslan Ermilov 	ifp->if_capabilities |= IFCAP_POLLING;
2244e695984eSRuslan Ermilov #endif
2245db40c1aeSDoug Ambrisko 
2246c8b27acaSJohn Baldwin 	callout_init_mtx(&sc->dc_stat_ch, &sc->dc_mtx, 0);
224796f2e892SBill Paul 
2248608654d4SNate Lawson 	/*
2249608654d4SNate Lawson 	 * Call MI attach routine.
2250608654d4SNate Lawson 	 */
22518df1ebe9SMarcel Moolenaar 	ether_ifattach(ifp, (caddr_t)eaddr);
2252608654d4SNate Lawson 
225354f1f1d1SNate Lawson 	/* Hook interrupt last to avoid having to lock softc */
2254c8b27acaSJohn Baldwin 	error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | INTR_MPSAFE,
2255608654d4SNate Lawson 	    dc_intr, sc, &sc->dc_intrhand);
2256608654d4SNate Lawson 
2257608654d4SNate Lawson 	if (error) {
225822f6205dSJohn Baldwin 		device_printf(dev, "couldn't set up irq\n");
2259693f4477SNate Lawson 		ether_ifdetach(ifp);
226054f1f1d1SNate Lawson 		goto fail;
2261608654d4SNate Lawson 	}
2262510a809eSMike Smith 
226396f2e892SBill Paul fail:
226454f1f1d1SNate Lawson 	if (error)
226554f1f1d1SNate Lawson 		dc_detach(dev);
226696f2e892SBill Paul 	return (error);
226796f2e892SBill Paul }
226896f2e892SBill Paul 
2269693f4477SNate Lawson /*
2270693f4477SNate Lawson  * Shutdown hardware and free up resources. This can be called any
2271693f4477SNate Lawson  * time after the mutex has been initialized. It is called in both
2272693f4477SNate Lawson  * the error case in attach and the normal detach case so it needs
2273693f4477SNate Lawson  * to be careful about only freeing resources that have actually been
2274693f4477SNate Lawson  * allocated.
2275693f4477SNate Lawson  */
2276e3d2833aSAlfred Perlstein static int
22770934f18aSMaxime Henrion dc_detach(device_t dev)
227896f2e892SBill Paul {
227996f2e892SBill Paul 	struct dc_softc *sc;
228096f2e892SBill Paul 	struct ifnet *ifp;
22815c1cfac4SBill Paul 	struct dc_mediainfo *m;
228256e5e7aeSMaxime Henrion 	int i;
228396f2e892SBill Paul 
228496f2e892SBill Paul 	sc = device_get_softc(dev);
228559f47d29SJohn Baldwin 	KASSERT(mtx_initialized(&sc->dc_mtx), ("dc mutex not initialized"));
2286d1ce9105SBill Paul 
2287fc74a9f9SBrooks Davis 	ifp = sc->dc_ifp;
228896f2e892SBill Paul 
228940929967SGleb Smirnoff #ifdef DEVICE_POLLING
229040929967SGleb Smirnoff 	if (ifp->if_capenable & IFCAP_POLLING)
229140929967SGleb Smirnoff 		ether_poll_deregister(ifp);
229240929967SGleb Smirnoff #endif
229340929967SGleb Smirnoff 
2294693f4477SNate Lawson 	/* These should only be active if attach succeeded */
2295214073e5SWarner Losh 	if (device_is_attached(dev)) {
2296c8b27acaSJohn Baldwin 		DC_LOCK(sc);
229796f2e892SBill Paul 		dc_stop(sc);
2298c8b27acaSJohn Baldwin 		DC_UNLOCK(sc);
2299c8b27acaSJohn Baldwin 		callout_drain(&sc->dc_stat_ch);
23009ef8b520SSam Leffler 		ether_ifdetach(ifp);
2301693f4477SNate Lawson 	}
2302693f4477SNate Lawson 	if (sc->dc_miibus)
230396f2e892SBill Paul 		device_delete_child(dev, sc->dc_miibus);
230454f1f1d1SNate Lawson 	bus_generic_detach(dev);
230596f2e892SBill Paul 
230654f1f1d1SNate Lawson 	if (sc->dc_intrhand)
230796f2e892SBill Paul 		bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand);
230854f1f1d1SNate Lawson 	if (sc->dc_irq)
230996f2e892SBill Paul 		bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
231054f1f1d1SNate Lawson 	if (sc->dc_res)
231196f2e892SBill Paul 		bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
231296f2e892SBill Paul 
23136a3033a8SWarner Losh 	if (ifp)
23146a3033a8SWarner Losh 		if_free(ifp);
23156a3033a8SWarner Losh 
231656e5e7aeSMaxime Henrion 	if (sc->dc_cdata.dc_sbuf != NULL)
231756e5e7aeSMaxime Henrion 		bus_dmamem_free(sc->dc_stag, sc->dc_cdata.dc_sbuf, sc->dc_smap);
231856e5e7aeSMaxime Henrion 	if (sc->dc_ldata != NULL)
231956e5e7aeSMaxime Henrion 		bus_dmamem_free(sc->dc_ltag, sc->dc_ldata, sc->dc_lmap);
23204f867c2dSGiorgos Keramidas 	if (sc->dc_mtag) {
232156e5e7aeSMaxime Henrion 		for (i = 0; i < DC_TX_LIST_CNT; i++)
23224f867c2dSGiorgos Keramidas 			if (sc->dc_cdata.dc_tx_map[i] != NULL)
23234f867c2dSGiorgos Keramidas 				bus_dmamap_destroy(sc->dc_mtag,
23244f867c2dSGiorgos Keramidas 				    sc->dc_cdata.dc_tx_map[i]);
232556e5e7aeSMaxime Henrion 		for (i = 0; i < DC_RX_LIST_CNT; i++)
23264f867c2dSGiorgos Keramidas 			if (sc->dc_cdata.dc_rx_map[i] != NULL)
23274f867c2dSGiorgos Keramidas 				bus_dmamap_destroy(sc->dc_mtag,
23284f867c2dSGiorgos Keramidas 				    sc->dc_cdata.dc_rx_map[i]);
232956e5e7aeSMaxime Henrion 		bus_dmamap_destroy(sc->dc_mtag, sc->dc_sparemap);
23304f867c2dSGiorgos Keramidas 	}
233156e5e7aeSMaxime Henrion 	if (sc->dc_stag)
233256e5e7aeSMaxime Henrion 		bus_dma_tag_destroy(sc->dc_stag);
233356e5e7aeSMaxime Henrion 	if (sc->dc_mtag)
233456e5e7aeSMaxime Henrion 		bus_dma_tag_destroy(sc->dc_mtag);
233556e5e7aeSMaxime Henrion 	if (sc->dc_ltag)
233656e5e7aeSMaxime Henrion 		bus_dma_tag_destroy(sc->dc_ltag);
233756e5e7aeSMaxime Henrion 
233896f2e892SBill Paul 	free(sc->dc_pnic_rx_buf, M_DEVBUF);
233996f2e892SBill Paul 
23405c1cfac4SBill Paul 	while (sc->dc_mi != NULL) {
23415c1cfac4SBill Paul 		m = sc->dc_mi->dc_next;
23425c1cfac4SBill Paul 		free(sc->dc_mi, M_DEVBUF);
23435c1cfac4SBill Paul 		sc->dc_mi = m;
23445c1cfac4SBill Paul 	}
23457efff076SWarner Losh 	free(sc->dc_srom, M_DEVBUF);
23465c1cfac4SBill Paul 
2347d1ce9105SBill Paul 	mtx_destroy(&sc->dc_mtx);
234896f2e892SBill Paul 
234996f2e892SBill Paul 	return (0);
235096f2e892SBill Paul }
235196f2e892SBill Paul 
235296f2e892SBill Paul /*
235396f2e892SBill Paul  * Initialize the transmit descriptors.
235496f2e892SBill Paul  */
2355e3d2833aSAlfred Perlstein static int
23560934f18aSMaxime Henrion dc_list_tx_init(struct dc_softc *sc)
235796f2e892SBill Paul {
235896f2e892SBill Paul 	struct dc_chain_data *cd;
235996f2e892SBill Paul 	struct dc_list_data *ld;
236001faf54bSLuigi Rizzo 	int i, nexti;
236196f2e892SBill Paul 
236296f2e892SBill Paul 	cd = &sc->dc_cdata;
236396f2e892SBill Paul 	ld = sc->dc_ldata;
236496f2e892SBill Paul 	for (i = 0; i < DC_TX_LIST_CNT; i++) {
2365b3811c95SMaxime Henrion 		if (i == DC_TX_LIST_CNT - 1)
2366b3811c95SMaxime Henrion 			nexti = 0;
2367b3811c95SMaxime Henrion 		else
2368b3811c95SMaxime Henrion 			nexti = i + 1;
2369af4358c7SMaxime Henrion 		ld->dc_tx_list[i].dc_next = htole32(DC_TXDESC(sc, nexti));
237096f2e892SBill Paul 		cd->dc_tx_chain[i] = NULL;
237196f2e892SBill Paul 		ld->dc_tx_list[i].dc_data = 0;
237296f2e892SBill Paul 		ld->dc_tx_list[i].dc_ctl = 0;
237396f2e892SBill Paul 	}
237496f2e892SBill Paul 
237596f2e892SBill Paul 	cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0;
237656e5e7aeSMaxime Henrion 	bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap,
237756e5e7aeSMaxime Henrion 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
237896f2e892SBill Paul 	return (0);
237996f2e892SBill Paul }
238096f2e892SBill Paul 
238196f2e892SBill Paul 
238296f2e892SBill Paul /*
238396f2e892SBill Paul  * Initialize the RX descriptors and allocate mbufs for them. Note that
238496f2e892SBill Paul  * we arrange the descriptors in a closed ring, so that the last descriptor
238596f2e892SBill Paul  * points back to the first.
238696f2e892SBill Paul  */
2387e3d2833aSAlfred Perlstein static int
23880934f18aSMaxime Henrion dc_list_rx_init(struct dc_softc *sc)
238996f2e892SBill Paul {
239096f2e892SBill Paul 	struct dc_chain_data *cd;
239196f2e892SBill Paul 	struct dc_list_data *ld;
239201faf54bSLuigi Rizzo 	int i, nexti;
239396f2e892SBill Paul 
239496f2e892SBill Paul 	cd = &sc->dc_cdata;
239596f2e892SBill Paul 	ld = sc->dc_ldata;
239696f2e892SBill Paul 
239796f2e892SBill Paul 	for (i = 0; i < DC_RX_LIST_CNT; i++) {
239856e5e7aeSMaxime Henrion 		if (dc_newbuf(sc, i, 1) != 0)
239996f2e892SBill Paul 			return (ENOBUFS);
2400b3811c95SMaxime Henrion 		if (i == DC_RX_LIST_CNT - 1)
2401b3811c95SMaxime Henrion 			nexti = 0;
2402b3811c95SMaxime Henrion 		else
2403b3811c95SMaxime Henrion 			nexti = i + 1;
2404af4358c7SMaxime Henrion 		ld->dc_rx_list[i].dc_next = htole32(DC_RXDESC(sc, nexti));
240596f2e892SBill Paul 	}
240696f2e892SBill Paul 
240796f2e892SBill Paul 	cd->dc_rx_prod = 0;
240856e5e7aeSMaxime Henrion 	bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap,
240956e5e7aeSMaxime Henrion 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
241096f2e892SBill Paul 	return (0);
241196f2e892SBill Paul }
241296f2e892SBill Paul 
241356e5e7aeSMaxime Henrion static void
241456e5e7aeSMaxime Henrion dc_dma_map_rxbuf(arg, segs, nseg, mapsize, error)
241556e5e7aeSMaxime Henrion 	void *arg;
241656e5e7aeSMaxime Henrion 	bus_dma_segment_t *segs;
241756e5e7aeSMaxime Henrion 	int nseg;
241856e5e7aeSMaxime Henrion 	bus_size_t mapsize;
241956e5e7aeSMaxime Henrion 	int error;
242056e5e7aeSMaxime Henrion {
242156e5e7aeSMaxime Henrion 	struct dc_softc *sc;
242256e5e7aeSMaxime Henrion 	struct dc_desc *c;
242356e5e7aeSMaxime Henrion 
242456e5e7aeSMaxime Henrion 	sc = arg;
242556e5e7aeSMaxime Henrion 	c = &sc->dc_ldata->dc_rx_list[sc->dc_cdata.dc_rx_cur];
242656e5e7aeSMaxime Henrion 	if (error) {
242756e5e7aeSMaxime Henrion 		sc->dc_cdata.dc_rx_err = error;
242856e5e7aeSMaxime Henrion 		return;
242956e5e7aeSMaxime Henrion 	}
243056e5e7aeSMaxime Henrion 
243156e5e7aeSMaxime Henrion 	KASSERT(nseg == 1, ("wrong number of segments, should be 1"));
243256e5e7aeSMaxime Henrion 	sc->dc_cdata.dc_rx_err = 0;
2433af4358c7SMaxime Henrion 	c->dc_data = htole32(segs->ds_addr);
243456e5e7aeSMaxime Henrion }
243556e5e7aeSMaxime Henrion 
243696f2e892SBill Paul /*
243796f2e892SBill Paul  * Initialize an RX descriptor and attach an MBUF cluster.
243896f2e892SBill Paul  */
2439e3d2833aSAlfred Perlstein static int
244056e5e7aeSMaxime Henrion dc_newbuf(struct dc_softc *sc, int i, int alloc)
244196f2e892SBill Paul {
244256e5e7aeSMaxime Henrion 	struct mbuf *m_new;
244356e5e7aeSMaxime Henrion 	bus_dmamap_t tmp;
244456e5e7aeSMaxime Henrion 	int error;
244596f2e892SBill Paul 
244656e5e7aeSMaxime Henrion 	if (alloc) {
244756e5e7aeSMaxime Henrion 		m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
244840129585SLuigi Rizzo 		if (m_new == NULL)
244996f2e892SBill Paul 			return (ENOBUFS);
245096f2e892SBill Paul 	} else {
245156e5e7aeSMaxime Henrion 		m_new = sc->dc_cdata.dc_rx_chain[i];
245296f2e892SBill Paul 		m_new->m_data = m_new->m_ext.ext_buf;
245396f2e892SBill Paul 	}
245456e5e7aeSMaxime Henrion 	m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
245596f2e892SBill Paul 	m_adj(m_new, sizeof(u_int64_t));
245696f2e892SBill Paul 
245796f2e892SBill Paul 	/*
245896f2e892SBill Paul 	 * If this is a PNIC chip, zero the buffer. This is part
245996f2e892SBill Paul 	 * of the workaround for the receive bug in the 82c168 and
246096f2e892SBill Paul 	 * 82c169 chips.
246196f2e892SBill Paul 	 */
246296f2e892SBill Paul 	if (sc->dc_flags & DC_PNIC_RX_BUG_WAR)
24630934f18aSMaxime Henrion 		bzero(mtod(m_new, char *), m_new->m_len);
246496f2e892SBill Paul 
246556e5e7aeSMaxime Henrion 	/* No need to remap the mbuf if we're reusing it. */
246656e5e7aeSMaxime Henrion 	if (alloc) {
246756e5e7aeSMaxime Henrion 		sc->dc_cdata.dc_rx_cur = i;
246856e5e7aeSMaxime Henrion 		error = bus_dmamap_load_mbuf(sc->dc_mtag, sc->dc_sparemap,
246956e5e7aeSMaxime Henrion 		    m_new, dc_dma_map_rxbuf, sc, 0);
247056e5e7aeSMaxime Henrion 		if (error) {
247156e5e7aeSMaxime Henrion 			m_freem(m_new);
247256e5e7aeSMaxime Henrion 			return (error);
247356e5e7aeSMaxime Henrion 		}
247456e5e7aeSMaxime Henrion 		if (sc->dc_cdata.dc_rx_err != 0) {
247556e5e7aeSMaxime Henrion 			m_freem(m_new);
247656e5e7aeSMaxime Henrion 			return (sc->dc_cdata.dc_rx_err);
247756e5e7aeSMaxime Henrion 		}
247856e5e7aeSMaxime Henrion 		bus_dmamap_unload(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i]);
247956e5e7aeSMaxime Henrion 		tmp = sc->dc_cdata.dc_rx_map[i];
248056e5e7aeSMaxime Henrion 		sc->dc_cdata.dc_rx_map[i] = sc->dc_sparemap;
248156e5e7aeSMaxime Henrion 		sc->dc_sparemap = tmp;
248296f2e892SBill Paul 		sc->dc_cdata.dc_rx_chain[i] = m_new;
248356e5e7aeSMaxime Henrion 	}
248496f2e892SBill Paul 
2485af4358c7SMaxime Henrion 	sc->dc_ldata->dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN);
2486af4358c7SMaxime Henrion 	sc->dc_ldata->dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN);
248756e5e7aeSMaxime Henrion 	bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i],
248856e5e7aeSMaxime Henrion 	    BUS_DMASYNC_PREREAD);
248956e5e7aeSMaxime Henrion 	bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap,
249056e5e7aeSMaxime Henrion 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
249196f2e892SBill Paul 	return (0);
249296f2e892SBill Paul }
249396f2e892SBill Paul 
249496f2e892SBill Paul /*
249596f2e892SBill Paul  * Grrrrr.
249696f2e892SBill Paul  * The PNIC chip has a terrible bug in it that manifests itself during
249796f2e892SBill Paul  * periods of heavy activity. The exact mode of failure if difficult to
249896f2e892SBill Paul  * pinpoint: sometimes it only happens in promiscuous mode, sometimes it
249996f2e892SBill Paul  * will happen on slow machines. The bug is that sometimes instead of
250096f2e892SBill Paul  * uploading one complete frame during reception, it uploads what looks
250196f2e892SBill Paul  * like the entire contents of its FIFO memory. The frame we want is at
250296f2e892SBill Paul  * the end of the whole mess, but we never know exactly how much data has
250396f2e892SBill Paul  * been uploaded, so salvaging the frame is hard.
250496f2e892SBill Paul  *
250596f2e892SBill Paul  * There is only one way to do it reliably, and it's disgusting.
250696f2e892SBill Paul  * Here's what we know:
250796f2e892SBill Paul  *
250896f2e892SBill Paul  * - We know there will always be somewhere between one and three extra
250996f2e892SBill Paul  *   descriptors uploaded.
251096f2e892SBill Paul  *
251196f2e892SBill Paul  * - We know the desired received frame will always be at the end of the
251296f2e892SBill Paul  *   total data upload.
251396f2e892SBill Paul  *
251496f2e892SBill Paul  * - We know the size of the desired received frame because it will be
251596f2e892SBill Paul  *   provided in the length field of the status word in the last descriptor.
251696f2e892SBill Paul  *
251796f2e892SBill Paul  * Here's what we do:
251896f2e892SBill Paul  *
251996f2e892SBill Paul  * - When we allocate buffers for the receive ring, we bzero() them.
252096f2e892SBill Paul  *   This means that we know that the buffer contents should be all
252196f2e892SBill Paul  *   zeros, except for data uploaded by the chip.
252296f2e892SBill Paul  *
252396f2e892SBill Paul  * - We also force the PNIC chip to upload frames that include the
252496f2e892SBill Paul  *   ethernet CRC at the end.
252596f2e892SBill Paul  *
252696f2e892SBill Paul  * - We gather all of the bogus frame data into a single buffer.
252796f2e892SBill Paul  *
252896f2e892SBill Paul  * - We then position a pointer at the end of this buffer and scan
252996f2e892SBill Paul  *   backwards until we encounter the first non-zero byte of data.
253096f2e892SBill Paul  *   This is the end of the received frame. We know we will encounter
253196f2e892SBill Paul  *   some data at the end of the frame because the CRC will always be
253296f2e892SBill Paul  *   there, so even if the sender transmits a packet of all zeros,
253396f2e892SBill Paul  *   we won't be fooled.
253496f2e892SBill Paul  *
253596f2e892SBill Paul  * - We know the size of the actual received frame, so we subtract
253696f2e892SBill Paul  *   that value from the current pointer location. This brings us
253796f2e892SBill Paul  *   to the start of the actual received packet.
253896f2e892SBill Paul  *
253996f2e892SBill Paul  * - We copy this into an mbuf and pass it on, along with the actual
254096f2e892SBill Paul  *   frame length.
254196f2e892SBill Paul  *
254296f2e892SBill Paul  * The performance hit is tremendous, but it beats dropping frames all
254396f2e892SBill Paul  * the time.
254496f2e892SBill Paul  */
254596f2e892SBill Paul 
254696f2e892SBill Paul #define DC_WHOLEFRAME	(DC_RXSTAT_FIRSTFRAG | DC_RXSTAT_LASTFRAG)
2547e3d2833aSAlfred Perlstein static void
25480934f18aSMaxime Henrion dc_pnic_rx_bug_war(struct dc_softc *sc, int idx)
254996f2e892SBill Paul {
255096f2e892SBill Paul 	struct dc_desc *cur_rx;
255196f2e892SBill Paul 	struct dc_desc *c = NULL;
255296f2e892SBill Paul 	struct mbuf *m = NULL;
255396f2e892SBill Paul 	unsigned char *ptr;
255496f2e892SBill Paul 	int i, total_len;
255596f2e892SBill Paul 	u_int32_t rxstat = 0;
255696f2e892SBill Paul 
255796f2e892SBill Paul 	i = sc->dc_pnic_rx_bug_save;
255896f2e892SBill Paul 	cur_rx = &sc->dc_ldata->dc_rx_list[idx];
255996f2e892SBill Paul 	ptr = sc->dc_pnic_rx_buf;
25601edc4c46SMaxime Henrion 	bzero(ptr, DC_RXLEN * 5);
256196f2e892SBill Paul 
256296f2e892SBill Paul 	/* Copy all the bytes from the bogus buffers. */
256396f2e892SBill Paul 	while (1) {
256496f2e892SBill Paul 		c = &sc->dc_ldata->dc_rx_list[i];
2565af4358c7SMaxime Henrion 		rxstat = le32toh(c->dc_status);
256696f2e892SBill Paul 		m = sc->dc_cdata.dc_rx_chain[i];
256796f2e892SBill Paul 		bcopy(mtod(m, char *), ptr, DC_RXLEN);
256896f2e892SBill Paul 		ptr += DC_RXLEN;
256996f2e892SBill Paul 		/* If this is the last buffer, break out. */
257096f2e892SBill Paul 		if (i == idx || rxstat & DC_RXSTAT_LASTFRAG)
257196f2e892SBill Paul 			break;
257256e5e7aeSMaxime Henrion 		dc_newbuf(sc, i, 0);
257396f2e892SBill Paul 		DC_INC(i, DC_RX_LIST_CNT);
257496f2e892SBill Paul 	}
257596f2e892SBill Paul 
257696f2e892SBill Paul 	/* Find the length of the actual receive frame. */
257796f2e892SBill Paul 	total_len = DC_RXBYTES(rxstat);
257896f2e892SBill Paul 
257996f2e892SBill Paul 	/* Scan backwards until we hit a non-zero byte. */
258096f2e892SBill Paul 	while (*ptr == 0x00)
258196f2e892SBill Paul 		ptr--;
258296f2e892SBill Paul 
258396f2e892SBill Paul 	/* Round off. */
258496f2e892SBill Paul 	if ((uintptr_t)(ptr) & 0x3)
258596f2e892SBill Paul 		ptr -= 1;
258696f2e892SBill Paul 
258796f2e892SBill Paul 	/* Now find the start of the frame. */
258896f2e892SBill Paul 	ptr -= total_len;
258996f2e892SBill Paul 	if (ptr < sc->dc_pnic_rx_buf)
259096f2e892SBill Paul 		ptr = sc->dc_pnic_rx_buf;
259196f2e892SBill Paul 
259296f2e892SBill Paul 	/*
259396f2e892SBill Paul 	 * Now copy the salvaged frame to the last mbuf and fake up
259496f2e892SBill Paul 	 * the status word to make it look like a successful
259596f2e892SBill Paul 	 * frame reception.
259696f2e892SBill Paul 	 */
259756e5e7aeSMaxime Henrion 	dc_newbuf(sc, i, 0);
259896f2e892SBill Paul 	bcopy(ptr, mtod(m, char *), total_len);
2599af4358c7SMaxime Henrion 	cur_rx->dc_status = htole32(rxstat | DC_RXSTAT_FIRSTFRAG);
260096f2e892SBill Paul }
260196f2e892SBill Paul 
260296f2e892SBill Paul /*
260373bf949cSBill Paul  * This routine searches the RX ring for dirty descriptors in the
260473bf949cSBill Paul  * event that the rxeof routine falls out of sync with the chip's
260573bf949cSBill Paul  * current descriptor pointer. This may happen sometimes as a result
260673bf949cSBill Paul  * of a "no RX buffer available" condition that happens when the chip
260773bf949cSBill Paul  * consumes all of the RX buffers before the driver has a chance to
260873bf949cSBill Paul  * process the RX ring. This routine may need to be called more than
260973bf949cSBill Paul  * once to bring the driver back in sync with the chip, however we
261073bf949cSBill Paul  * should still be getting RX DONE interrupts to drive the search
261173bf949cSBill Paul  * for new packets in the RX ring, so we should catch up eventually.
261273bf949cSBill Paul  */
2613e3d2833aSAlfred Perlstein static int
26140934f18aSMaxime Henrion dc_rx_resync(struct dc_softc *sc)
261573bf949cSBill Paul {
261673bf949cSBill Paul 	struct dc_desc *cur_rx;
26170934f18aSMaxime Henrion 	int i, pos;
261873bf949cSBill Paul 
261973bf949cSBill Paul 	pos = sc->dc_cdata.dc_rx_prod;
262073bf949cSBill Paul 
262173bf949cSBill Paul 	for (i = 0; i < DC_RX_LIST_CNT; i++) {
262273bf949cSBill Paul 		cur_rx = &sc->dc_ldata->dc_rx_list[pos];
2623af4358c7SMaxime Henrion 		if (!(le32toh(cur_rx->dc_status) & DC_RXSTAT_OWN))
262473bf949cSBill Paul 			break;
262573bf949cSBill Paul 		DC_INC(pos, DC_RX_LIST_CNT);
262673bf949cSBill Paul 	}
262773bf949cSBill Paul 
262873bf949cSBill Paul 	/* If the ring really is empty, then just return. */
262973bf949cSBill Paul 	if (i == DC_RX_LIST_CNT)
263073bf949cSBill Paul 		return (0);
263173bf949cSBill Paul 
263273bf949cSBill Paul 	/* We've fallen behing the chip: catch it. */
263373bf949cSBill Paul 	sc->dc_cdata.dc_rx_prod = pos;
263473bf949cSBill Paul 
263573bf949cSBill Paul 	return (EAGAIN);
263673bf949cSBill Paul }
263773bf949cSBill Paul 
263873bf949cSBill Paul /*
263996f2e892SBill Paul  * A frame has been uploaded: pass the resulting mbuf chain up to
264096f2e892SBill Paul  * the higher level protocols.
264196f2e892SBill Paul  */
2642e3d2833aSAlfred Perlstein static void
26430934f18aSMaxime Henrion dc_rxeof(struct dc_softc *sc)
264496f2e892SBill Paul {
264596f2e892SBill Paul 	struct mbuf *m;
264696f2e892SBill Paul 	struct ifnet *ifp;
264796f2e892SBill Paul 	struct dc_desc *cur_rx;
264896f2e892SBill Paul 	int i, total_len = 0;
264996f2e892SBill Paul 	u_int32_t rxstat;
265096f2e892SBill Paul 
26515120abbfSSam Leffler 	DC_LOCK_ASSERT(sc);
26525120abbfSSam Leffler 
2653fc74a9f9SBrooks Davis 	ifp = sc->dc_ifp;
265496f2e892SBill Paul 	i = sc->dc_cdata.dc_rx_prod;
265596f2e892SBill Paul 
265656e5e7aeSMaxime Henrion 	bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD);
2657af4358c7SMaxime Henrion 	while (!(le32toh(sc->dc_ldata->dc_rx_list[i].dc_status) &
2658af4358c7SMaxime Henrion 	    DC_RXSTAT_OWN)) {
2659e4fc250cSLuigi Rizzo #ifdef DEVICE_POLLING
266040929967SGleb Smirnoff 		if (ifp->if_capenable & IFCAP_POLLING) {
2661e4fc250cSLuigi Rizzo 			if (sc->rxcycles <= 0)
2662e4fc250cSLuigi Rizzo 				break;
2663e4fc250cSLuigi Rizzo 			sc->rxcycles--;
2664e4fc250cSLuigi Rizzo 		}
26650934f18aSMaxime Henrion #endif
266696f2e892SBill Paul 		cur_rx = &sc->dc_ldata->dc_rx_list[i];
2667af4358c7SMaxime Henrion 		rxstat = le32toh(cur_rx->dc_status);
266896f2e892SBill Paul 		m = sc->dc_cdata.dc_rx_chain[i];
266956e5e7aeSMaxime Henrion 		bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i],
267056e5e7aeSMaxime Henrion 		    BUS_DMASYNC_POSTREAD);
267196f2e892SBill Paul 		total_len = DC_RXBYTES(rxstat);
267296f2e892SBill Paul 
267396f2e892SBill Paul 		if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) {
267496f2e892SBill Paul 			if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) {
267596f2e892SBill Paul 				if (rxstat & DC_RXSTAT_FIRSTFRAG)
267696f2e892SBill Paul 					sc->dc_pnic_rx_bug_save = i;
267796f2e892SBill Paul 				if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) {
267896f2e892SBill Paul 					DC_INC(i, DC_RX_LIST_CNT);
267996f2e892SBill Paul 					continue;
268096f2e892SBill Paul 				}
268196f2e892SBill Paul 				dc_pnic_rx_bug_war(sc, i);
2682af4358c7SMaxime Henrion 				rxstat = le32toh(cur_rx->dc_status);
268396f2e892SBill Paul 				total_len = DC_RXBYTES(rxstat);
268496f2e892SBill Paul 			}
268596f2e892SBill Paul 		}
268696f2e892SBill Paul 
268796f2e892SBill Paul 		/*
268896f2e892SBill Paul 		 * If an error occurs, update stats, clear the
268996f2e892SBill Paul 		 * status word and leave the mbuf cluster in place:
269096f2e892SBill Paul 		 * it should simply get re-used next time this descriptor
2691db40c1aeSDoug Ambrisko 		 * comes up in the ring.  However, don't report long
26920934f18aSMaxime Henrion 		 * frames as errors since they could be vlans.
269396f2e892SBill Paul 		 */
2694db40c1aeSDoug Ambrisko 		if ((rxstat & DC_RXSTAT_RXERR)) {
2695db40c1aeSDoug Ambrisko 			if (!(rxstat & DC_RXSTAT_GIANT) ||
2696db40c1aeSDoug Ambrisko 			    (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE |
2697db40c1aeSDoug Ambrisko 				       DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN |
2698db40c1aeSDoug Ambrisko 				       DC_RXSTAT_RUNT   | DC_RXSTAT_DE))) {
269996f2e892SBill Paul 				ifp->if_ierrors++;
270096f2e892SBill Paul 				if (rxstat & DC_RXSTAT_COLLSEEN)
270196f2e892SBill Paul 					ifp->if_collisions++;
270256e5e7aeSMaxime Henrion 				dc_newbuf(sc, i, 0);
270396f2e892SBill Paul 				if (rxstat & DC_RXSTAT_CRCERR) {
270496f2e892SBill Paul 					DC_INC(i, DC_RX_LIST_CNT);
270596f2e892SBill Paul 					continue;
270696f2e892SBill Paul 				} else {
2707c8b27acaSJohn Baldwin 					dc_init_locked(sc);
270896f2e892SBill Paul 					return;
270996f2e892SBill Paul 				}
271096f2e892SBill Paul 			}
2711db40c1aeSDoug Ambrisko 		}
271296f2e892SBill Paul 
271396f2e892SBill Paul 		/* No errors; receive the packet. */
271496f2e892SBill Paul 		total_len -= ETHER_CRC_LEN;
271501faf54bSLuigi Rizzo #ifdef __i386__
271601faf54bSLuigi Rizzo 		/*
271701faf54bSLuigi Rizzo 		 * On the x86 we do not have alignment problems, so try to
271801faf54bSLuigi Rizzo 		 * allocate a new buffer for the receive ring, and pass up
271901faf54bSLuigi Rizzo 		 * the one where the packet is already, saving the expensive
272001faf54bSLuigi Rizzo 		 * copy done in m_devget().
272101faf54bSLuigi Rizzo 		 * If we are on an architecture with alignment problems, or
272201faf54bSLuigi Rizzo 		 * if the allocation fails, then use m_devget and leave the
272301faf54bSLuigi Rizzo 		 * existing buffer in the receive ring.
272401faf54bSLuigi Rizzo 		 */
272556e5e7aeSMaxime Henrion 		if (dc_quick && dc_newbuf(sc, i, 1) == 0) {
272601faf54bSLuigi Rizzo 			m->m_pkthdr.rcvif = ifp;
272701faf54bSLuigi Rizzo 			m->m_pkthdr.len = m->m_len = total_len;
272801faf54bSLuigi Rizzo 			DC_INC(i, DC_RX_LIST_CNT);
272901faf54bSLuigi Rizzo 		} else
273001faf54bSLuigi Rizzo #endif
273101faf54bSLuigi Rizzo 		{
273201faf54bSLuigi Rizzo 			struct mbuf *m0;
273396f2e892SBill Paul 
273401faf54bSLuigi Rizzo 			m0 = m_devget(mtod(m, char *), total_len,
273501faf54bSLuigi Rizzo 				ETHER_ALIGN, ifp, NULL);
273656e5e7aeSMaxime Henrion 			dc_newbuf(sc, i, 0);
273796f2e892SBill Paul 			DC_INC(i, DC_RX_LIST_CNT);
273896f2e892SBill Paul 			if (m0 == NULL) {
273996f2e892SBill Paul 				ifp->if_ierrors++;
274096f2e892SBill Paul 				continue;
274196f2e892SBill Paul 			}
274296f2e892SBill Paul 			m = m0;
274301faf54bSLuigi Rizzo 		}
274496f2e892SBill Paul 
274596f2e892SBill Paul 		ifp->if_ipackets++;
27465120abbfSSam Leffler 		DC_UNLOCK(sc);
27479ef8b520SSam Leffler 		(*ifp->if_input)(ifp, m);
27485120abbfSSam Leffler 		DC_LOCK(sc);
274996f2e892SBill Paul 	}
275096f2e892SBill Paul 
275196f2e892SBill Paul 	sc->dc_cdata.dc_rx_prod = i;
275296f2e892SBill Paul }
275396f2e892SBill Paul 
275496f2e892SBill Paul /*
275596f2e892SBill Paul  * A frame was downloaded to the chip. It's safe for us to clean up
275696f2e892SBill Paul  * the list buffers.
275796f2e892SBill Paul  */
275896f2e892SBill Paul 
2759e3d2833aSAlfred Perlstein static void
27600934f18aSMaxime Henrion dc_txeof(struct dc_softc *sc)
276196f2e892SBill Paul {
276296f2e892SBill Paul 	struct dc_desc *cur_tx = NULL;
276396f2e892SBill Paul 	struct ifnet *ifp;
276496f2e892SBill Paul 	int idx;
2765af4358c7SMaxime Henrion 	u_int32_t ctl, txstat;
276696f2e892SBill Paul 
2767fc74a9f9SBrooks Davis 	ifp = sc->dc_ifp;
276896f2e892SBill Paul 
276996f2e892SBill Paul 	/*
277096f2e892SBill Paul 	 * Go through our tx list and free mbufs for those
277196f2e892SBill Paul 	 * frames that have been transmitted.
277296f2e892SBill Paul 	 */
277356e5e7aeSMaxime Henrion 	bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD);
277496f2e892SBill Paul 	idx = sc->dc_cdata.dc_tx_cons;
277596f2e892SBill Paul 	while (idx != sc->dc_cdata.dc_tx_prod) {
277696f2e892SBill Paul 
277796f2e892SBill Paul 		cur_tx = &sc->dc_ldata->dc_tx_list[idx];
2778af4358c7SMaxime Henrion 		txstat = le32toh(cur_tx->dc_status);
2779af4358c7SMaxime Henrion 		ctl = le32toh(cur_tx->dc_ctl);
278096f2e892SBill Paul 
278196f2e892SBill Paul 		if (txstat & DC_TXSTAT_OWN)
278296f2e892SBill Paul 			break;
278396f2e892SBill Paul 
27844ff4a9beSDon Lewis 		if (!(ctl & DC_TXCTL_LASTFRAG) || ctl & DC_TXCTL_SETUP) {
2785af4358c7SMaxime Henrion 			if (ctl & DC_TXCTL_SETUP) {
278696f2e892SBill Paul 				/*
278796f2e892SBill Paul 				 * Yes, the PNIC is so brain damaged
278896f2e892SBill Paul 				 * that it will sometimes generate a TX
278996f2e892SBill Paul 				 * underrun error while DMAing the RX
279096f2e892SBill Paul 				 * filter setup frame. If we detect this,
279196f2e892SBill Paul 				 * we have to send the setup frame again,
279296f2e892SBill Paul 				 * or else the filter won't be programmed
279396f2e892SBill Paul 				 * correctly.
279496f2e892SBill Paul 				 */
279596f2e892SBill Paul 				if (DC_IS_PNIC(sc)) {
279696f2e892SBill Paul 					if (txstat & DC_TXSTAT_ERRSUM)
279796f2e892SBill Paul 						dc_setfilt(sc);
279896f2e892SBill Paul 				}
279996f2e892SBill Paul 				sc->dc_cdata.dc_tx_chain[idx] = NULL;
280096f2e892SBill Paul 			}
2801bcb9ef4fSLuigi Rizzo 			sc->dc_cdata.dc_tx_cnt--;
280296f2e892SBill Paul 			DC_INC(idx, DC_TX_LIST_CNT);
280396f2e892SBill Paul 			continue;
280496f2e892SBill Paul 		}
280596f2e892SBill Paul 
280629a2220aSBill Paul 		if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) {
2807feb78939SJonathan Chen 			/*
2808feb78939SJonathan Chen 			 * XXX: Why does my Xircom taunt me so?
2809feb78939SJonathan Chen 			 * For some reason it likes setting the CARRLOST flag
281029a2220aSBill Paul 			 * even when the carrier is there. wtf?!?
281129a2220aSBill Paul 			 * Who knows, but Conexant chips have the
281229a2220aSBill Paul 			 * same problem. Maybe they took lessons
281329a2220aSBill Paul 			 * from Xircom.
281429a2220aSBill Paul 			 */
2815feb78939SJonathan Chen 			if (/*sc->dc_type == DC_TYPE_21143 &&*/
2816feb78939SJonathan Chen 			    sc->dc_pmode == DC_PMODE_MII &&
2817feb78939SJonathan Chen 			    ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM |
2818feb78939SJonathan Chen 			    DC_TXSTAT_NOCARRIER)))
2819feb78939SJonathan Chen 				txstat &= ~DC_TXSTAT_ERRSUM;
2820feb78939SJonathan Chen 		} else {
282196f2e892SBill Paul 			if (/*sc->dc_type == DC_TYPE_21143 &&*/
282296f2e892SBill Paul 			    sc->dc_pmode == DC_PMODE_MII &&
282396f2e892SBill Paul 			    ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM |
282496f2e892SBill Paul 			    DC_TXSTAT_NOCARRIER | DC_TXSTAT_CARRLOST)))
282596f2e892SBill Paul 				txstat &= ~DC_TXSTAT_ERRSUM;
2826feb78939SJonathan Chen 		}
282796f2e892SBill Paul 
282896f2e892SBill Paul 		if (txstat & DC_TXSTAT_ERRSUM) {
282996f2e892SBill Paul 			ifp->if_oerrors++;
283096f2e892SBill Paul 			if (txstat & DC_TXSTAT_EXCESSCOLL)
283196f2e892SBill Paul 				ifp->if_collisions++;
283296f2e892SBill Paul 			if (txstat & DC_TXSTAT_LATECOLL)
283396f2e892SBill Paul 				ifp->if_collisions++;
283496f2e892SBill Paul 			if (!(txstat & DC_TXSTAT_UNDERRUN)) {
2835c8b27acaSJohn Baldwin 				dc_init_locked(sc);
283696f2e892SBill Paul 				return;
283796f2e892SBill Paul 			}
283896f2e892SBill Paul 		}
283996f2e892SBill Paul 
284096f2e892SBill Paul 		ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3;
284196f2e892SBill Paul 
284296f2e892SBill Paul 		ifp->if_opackets++;
284396f2e892SBill Paul 		if (sc->dc_cdata.dc_tx_chain[idx] != NULL) {
284456e5e7aeSMaxime Henrion 			bus_dmamap_sync(sc->dc_mtag,
284556e5e7aeSMaxime Henrion 			    sc->dc_cdata.dc_tx_map[idx],
284656e5e7aeSMaxime Henrion 			    BUS_DMASYNC_POSTWRITE);
284756e5e7aeSMaxime Henrion 			bus_dmamap_unload(sc->dc_mtag,
284856e5e7aeSMaxime Henrion 			    sc->dc_cdata.dc_tx_map[idx]);
284996f2e892SBill Paul 			m_freem(sc->dc_cdata.dc_tx_chain[idx]);
285096f2e892SBill Paul 			sc->dc_cdata.dc_tx_chain[idx] = NULL;
285196f2e892SBill Paul 		}
285296f2e892SBill Paul 
285396f2e892SBill Paul 		sc->dc_cdata.dc_tx_cnt--;
285496f2e892SBill Paul 		DC_INC(idx, DC_TX_LIST_CNT);
285596f2e892SBill Paul 	}
285696f2e892SBill Paul 
2857bcb9ef4fSLuigi Rizzo 	if (idx != sc->dc_cdata.dc_tx_cons) {
28580934f18aSMaxime Henrion 	    	/* Some buffers have been freed. */
285996f2e892SBill Paul 		sc->dc_cdata.dc_tx_cons = idx;
286013f4c340SRobert Watson 		ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2861bcb9ef4fSLuigi Rizzo 	}
2862bcb9ef4fSLuigi Rizzo 	ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5;
286396f2e892SBill Paul }
286496f2e892SBill Paul 
2865e3d2833aSAlfred Perlstein static void
28660934f18aSMaxime Henrion dc_tick(void *xsc)
286796f2e892SBill Paul {
286896f2e892SBill Paul 	struct dc_softc *sc;
286996f2e892SBill Paul 	struct mii_data *mii;
287096f2e892SBill Paul 	struct ifnet *ifp;
287196f2e892SBill Paul 	u_int32_t r;
287296f2e892SBill Paul 
287396f2e892SBill Paul 	sc = xsc;
2874c8b27acaSJohn Baldwin 	DC_LOCK_ASSERT(sc);
2875fc74a9f9SBrooks Davis 	ifp = sc->dc_ifp;
287696f2e892SBill Paul 	mii = device_get_softc(sc->dc_miibus);
287796f2e892SBill Paul 
287896f2e892SBill Paul 	if (sc->dc_flags & DC_REDUCED_MII_POLL) {
2879318b02fdSBill Paul 		if (sc->dc_flags & DC_21143_NWAY) {
2880318b02fdSBill Paul 			r = CSR_READ_4(sc, DC_10BTSTAT);
2881318b02fdSBill Paul 			if (IFM_SUBTYPE(mii->mii_media_active) ==
2882318b02fdSBill Paul 			    IFM_100_TX && (r & DC_TSTAT_LS100)) {
288396f2e892SBill Paul 				sc->dc_link = 0;
2884318b02fdSBill Paul 				mii_mediachg(mii);
2885318b02fdSBill Paul 			}
2886318b02fdSBill Paul 			if (IFM_SUBTYPE(mii->mii_media_active) ==
2887318b02fdSBill Paul 			    IFM_10_T && (r & DC_TSTAT_LS10)) {
2888318b02fdSBill Paul 				sc->dc_link = 0;
2889318b02fdSBill Paul 				mii_mediachg(mii);
2890318b02fdSBill Paul 			}
2891d675147eSBill Paul 			if (sc->dc_link == 0)
289296f2e892SBill Paul 				mii_tick(mii);
289396f2e892SBill Paul 		} else {
2894318b02fdSBill Paul 			r = CSR_READ_4(sc, DC_ISR);
289596f2e892SBill Paul 			if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT &&
2896259b8d84SMartin Blapp 			    sc->dc_cdata.dc_tx_cnt == 0) {
289796f2e892SBill Paul 				mii_tick(mii);
2898042c8f6eSBill Paul 				if (!(mii->mii_media_status & IFM_ACTIVE))
2899042c8f6eSBill Paul 					sc->dc_link = 0;
290096f2e892SBill Paul 			}
2901259b8d84SMartin Blapp 		}
290296f2e892SBill Paul 	} else
290396f2e892SBill Paul 		mii_tick(mii);
290496f2e892SBill Paul 
290596f2e892SBill Paul 	/*
290696f2e892SBill Paul 	 * When the init routine completes, we expect to be able to send
290796f2e892SBill Paul 	 * packets right away, and in fact the network code will send a
290896f2e892SBill Paul 	 * gratuitous ARP the moment the init routine marks the interface
290996f2e892SBill Paul 	 * as running. However, even though the MAC may have been initialized,
291096f2e892SBill Paul 	 * there may be a delay of a few seconds before the PHY completes
291196f2e892SBill Paul 	 * autonegotiation and the link is brought up. Any transmissions
291296f2e892SBill Paul 	 * made during that delay will be lost. Dealing with this is tricky:
291396f2e892SBill Paul 	 * we can't just pause in the init routine while waiting for the
291496f2e892SBill Paul 	 * PHY to come ready since that would bring the whole system to
291596f2e892SBill Paul 	 * a screeching halt for several seconds.
291696f2e892SBill Paul 	 *
291796f2e892SBill Paul 	 * What we do here is prevent the TX start routine from sending
291896f2e892SBill Paul 	 * any packets until a link has been established. After the
291996f2e892SBill Paul 	 * interface has been initialized, the tick routine will poll
292096f2e892SBill Paul 	 * the state of the PHY until the IFM_ACTIVE flag is set. Until
292196f2e892SBill Paul 	 * that time, packets will stay in the send queue, and once the
292296f2e892SBill Paul 	 * link comes up, they will be flushed out to the wire.
292396f2e892SBill Paul 	 */
2924cd62a9cbSJonathan Lemon 	if (!sc->dc_link && mii->mii_media_status & IFM_ACTIVE &&
292596f2e892SBill Paul 	    IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
292696f2e892SBill Paul 		sc->dc_link++;
2927cbaf877fSBrian Feldman 		if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2928c8b27acaSJohn Baldwin 			dc_start_locked(ifp);
292996f2e892SBill Paul 	}
293096f2e892SBill Paul 
2931318b02fdSBill Paul 	if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link)
2932b50c6312SJonathan Lemon 		callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc);
2933318b02fdSBill Paul 	else
2934b50c6312SJonathan Lemon 		callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc);
293596f2e892SBill Paul }
293696f2e892SBill Paul 
2937d467c136SBill Paul /*
2938d467c136SBill Paul  * A transmit underrun has occurred.  Back off the transmit threshold,
2939d467c136SBill Paul  * or switch to store and forward mode if we have to.
2940d467c136SBill Paul  */
2941e3d2833aSAlfred Perlstein static void
29420934f18aSMaxime Henrion dc_tx_underrun(struct dc_softc *sc)
2943d467c136SBill Paul {
2944d467c136SBill Paul 	u_int32_t isr;
2945d467c136SBill Paul 	int i;
2946d467c136SBill Paul 
2947d467c136SBill Paul 	if (DC_IS_DAVICOM(sc))
2948c8b27acaSJohn Baldwin 		dc_init_locked(sc);
2949d467c136SBill Paul 
2950d467c136SBill Paul 	if (DC_IS_INTEL(sc)) {
2951d467c136SBill Paul 		/*
2952d467c136SBill Paul 		 * The real 21143 requires that the transmitter be idle
2953d467c136SBill Paul 		 * in order to change the transmit threshold or store
2954d467c136SBill Paul 		 * and forward state.
2955d467c136SBill Paul 		 */
2956d467c136SBill Paul 		DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
2957d467c136SBill Paul 
2958d467c136SBill Paul 		for (i = 0; i < DC_TIMEOUT; i++) {
2959d467c136SBill Paul 			isr = CSR_READ_4(sc, DC_ISR);
2960d467c136SBill Paul 			if (isr & DC_ISR_TX_IDLE)
2961d467c136SBill Paul 				break;
2962d467c136SBill Paul 			DELAY(10);
2963d467c136SBill Paul 		}
2964d467c136SBill Paul 		if (i == DC_TIMEOUT) {
296522f6205dSJohn Baldwin 			if_printf(sc->dc_ifp,
296622f6205dSJohn Baldwin 			    "failed to force tx to idle state\n");
2967c8b27acaSJohn Baldwin 			dc_init_locked(sc);
2968d467c136SBill Paul 		}
2969d467c136SBill Paul 	}
2970d467c136SBill Paul 
297122f6205dSJohn Baldwin 	if_printf(sc->dc_ifp, "TX underrun -- ");
2972d467c136SBill Paul 	sc->dc_txthresh += DC_TXTHRESH_INC;
2973d467c136SBill Paul 	if (sc->dc_txthresh > DC_TXTHRESH_MAX) {
2974d467c136SBill Paul 		printf("using store and forward mode\n");
2975d467c136SBill Paul 		DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
2976d467c136SBill Paul 	} else {
2977d467c136SBill Paul 		printf("increasing TX threshold\n");
2978d467c136SBill Paul 		DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH);
2979d467c136SBill Paul 		DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh);
2980d467c136SBill Paul 	}
2981d467c136SBill Paul 
2982d467c136SBill Paul 	if (DC_IS_INTEL(sc))
2983d467c136SBill Paul 		DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
2984d467c136SBill Paul }
2985d467c136SBill Paul 
2986e4fc250cSLuigi Rizzo #ifdef DEVICE_POLLING
2987e4fc250cSLuigi Rizzo static poll_handler_t dc_poll;
2988e4fc250cSLuigi Rizzo 
2989e4fc250cSLuigi Rizzo static void
2990e4fc250cSLuigi Rizzo dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2991e4fc250cSLuigi Rizzo {
2992e4fc250cSLuigi Rizzo 	struct dc_softc *sc = ifp->if_softc;
2993e4fc250cSLuigi Rizzo 
299440929967SGleb Smirnoff 	DC_LOCK(sc);
299540929967SGleb Smirnoff 
299640929967SGleb Smirnoff 	if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
299740929967SGleb Smirnoff 		DC_UNLOCK(sc);
2998e4fc250cSLuigi Rizzo 		return;
2999e4fc250cSLuigi Rizzo 	}
300040929967SGleb Smirnoff 
3001e4fc250cSLuigi Rizzo 	sc->rxcycles = count;
3002e4fc250cSLuigi Rizzo 	dc_rxeof(sc);
3003e4fc250cSLuigi Rizzo 	dc_txeof(sc);
300413f4c340SRobert Watson 	if (!IFQ_IS_EMPTY(&ifp->if_snd) &&
300513f4c340SRobert Watson 	    !(ifp->if_drv_flags & IFF_DRV_OACTIVE))
3006c8b27acaSJohn Baldwin 		dc_start_locked(ifp);
3007e4fc250cSLuigi Rizzo 
3008e4fc250cSLuigi Rizzo 	if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
3009e4fc250cSLuigi Rizzo 		u_int32_t	status;
3010e4fc250cSLuigi Rizzo 
3011e4fc250cSLuigi Rizzo 		status = CSR_READ_4(sc, DC_ISR);
3012e4fc250cSLuigi Rizzo 		status &= (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF |
3013e4fc250cSLuigi Rizzo 			DC_ISR_TX_NOBUF | DC_ISR_TX_IDLE | DC_ISR_TX_UNDERRUN |
3014e4fc250cSLuigi Rizzo 			DC_ISR_BUS_ERR);
30155120abbfSSam Leffler 		if (!status) {
30165120abbfSSam Leffler 			DC_UNLOCK(sc);
3017e4fc250cSLuigi Rizzo 			return;
30185120abbfSSam Leffler 		}
3019e4fc250cSLuigi Rizzo 		/* ack what we have */
3020e4fc250cSLuigi Rizzo 		CSR_WRITE_4(sc, DC_ISR, status);
3021e4fc250cSLuigi Rizzo 
3022e4fc250cSLuigi Rizzo 		if (status & (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF)) {
3023e4fc250cSLuigi Rizzo 			u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED);
3024e4fc250cSLuigi Rizzo 			ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff);
3025e4fc250cSLuigi Rizzo 
3026e4fc250cSLuigi Rizzo 			if (dc_rx_resync(sc))
3027e4fc250cSLuigi Rizzo 				dc_rxeof(sc);
3028e4fc250cSLuigi Rizzo 		}
3029e4fc250cSLuigi Rizzo 		/* restart transmit unit if necessary */
3030e4fc250cSLuigi Rizzo 		if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt)
3031e4fc250cSLuigi Rizzo 			CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3032e4fc250cSLuigi Rizzo 
3033e4fc250cSLuigi Rizzo 		if (status & DC_ISR_TX_UNDERRUN)
3034e4fc250cSLuigi Rizzo 			dc_tx_underrun(sc);
3035e4fc250cSLuigi Rizzo 
3036e4fc250cSLuigi Rizzo 		if (status & DC_ISR_BUS_ERR) {
303722f6205dSJohn Baldwin 			if_printf(ifp, "dc_poll: bus error\n");
3038e4fc250cSLuigi Rizzo 			dc_reset(sc);
3039c8b27acaSJohn Baldwin 			dc_init_locked(sc);
3040e4fc250cSLuigi Rizzo 		}
3041e4fc250cSLuigi Rizzo 	}
30425120abbfSSam Leffler 	DC_UNLOCK(sc);
3043e4fc250cSLuigi Rizzo }
3044e4fc250cSLuigi Rizzo #endif /* DEVICE_POLLING */
3045e4fc250cSLuigi Rizzo 
3046e3d2833aSAlfred Perlstein static void
30470934f18aSMaxime Henrion dc_intr(void *arg)
304896f2e892SBill Paul {
304996f2e892SBill Paul 	struct dc_softc *sc;
305096f2e892SBill Paul 	struct ifnet *ifp;
305196f2e892SBill Paul 	u_int32_t status;
305296f2e892SBill Paul 
305396f2e892SBill Paul 	sc = arg;
3054d2a1864bSWarner Losh 
30550934f18aSMaxime Henrion 	if (sc->suspended)
3056e8388e14SMitsuru IWASAKI 		return;
3057e8388e14SMitsuru IWASAKI 
3058d2a1864bSWarner Losh 	if ((CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0)
3059d2a1864bSWarner Losh 		return;
3060d2a1864bSWarner Losh 
3061d1ce9105SBill Paul 	DC_LOCK(sc);
3062fc74a9f9SBrooks Davis 	ifp = sc->dc_ifp;
3063e4fc250cSLuigi Rizzo #ifdef DEVICE_POLLING
306440929967SGleb Smirnoff 	if (ifp->if_capenable & IFCAP_POLLING) {
306540929967SGleb Smirnoff 		DC_UNLOCK(sc);
306640929967SGleb Smirnoff 		return;
3067e4fc250cSLuigi Rizzo 	}
30680934f18aSMaxime Henrion #endif
306996f2e892SBill Paul 
3070d88a358cSLuigi Rizzo 	/* Suppress unwanted interrupts */
307196f2e892SBill Paul 	if (!(ifp->if_flags & IFF_UP)) {
307296f2e892SBill Paul 		if (CSR_READ_4(sc, DC_ISR) & DC_INTRS)
307396f2e892SBill Paul 			dc_stop(sc);
3074d1ce9105SBill Paul 		DC_UNLOCK(sc);
307596f2e892SBill Paul 		return;
307696f2e892SBill Paul 	}
307796f2e892SBill Paul 
307896f2e892SBill Paul 	/* Disable interrupts. */
307996f2e892SBill Paul 	CSR_WRITE_4(sc, DC_IMR, 0x00000000);
308096f2e892SBill Paul 
30817ed2454cSGleb Smirnoff 	while (((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) &&
30827ed2454cSGleb Smirnoff 	    status != 0xFFFFFFFF &&
30835108cc56SGleb Smirnoff 	    (ifp->if_drv_flags & IFF_DRV_RUNNING)) {
308496f2e892SBill Paul 
308596f2e892SBill Paul 		CSR_WRITE_4(sc, DC_ISR, status);
308696f2e892SBill Paul 
308773bf949cSBill Paul 		if (status & DC_ISR_RX_OK) {
308873bf949cSBill Paul 			int		curpkts;
308973bf949cSBill Paul 			curpkts = ifp->if_ipackets;
309096f2e892SBill Paul 			dc_rxeof(sc);
309173bf949cSBill Paul 			if (curpkts == ifp->if_ipackets) {
309273bf949cSBill Paul 				while (dc_rx_resync(sc))
309373bf949cSBill Paul 					dc_rxeof(sc);
309473bf949cSBill Paul 			}
309573bf949cSBill Paul 		}
309696f2e892SBill Paul 
309796f2e892SBill Paul 		if (status & (DC_ISR_TX_OK | DC_ISR_TX_NOBUF))
309896f2e892SBill Paul 			dc_txeof(sc);
309996f2e892SBill Paul 
310096f2e892SBill Paul 		if (status & DC_ISR_TX_IDLE) {
310196f2e892SBill Paul 			dc_txeof(sc);
310296f2e892SBill Paul 			if (sc->dc_cdata.dc_tx_cnt) {
310396f2e892SBill Paul 				DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
310496f2e892SBill Paul 				CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
310596f2e892SBill Paul 			}
310696f2e892SBill Paul 		}
310796f2e892SBill Paul 
3108d467c136SBill Paul 		if (status & DC_ISR_TX_UNDERRUN)
3109d467c136SBill Paul 			dc_tx_underrun(sc);
311096f2e892SBill Paul 
311196f2e892SBill Paul 		if ((status & DC_ISR_RX_WATDOGTIMEO)
311273bf949cSBill Paul 		    || (status & DC_ISR_RX_NOBUF)) {
311373bf949cSBill Paul 			int		curpkts;
311473bf949cSBill Paul 			curpkts = ifp->if_ipackets;
311596f2e892SBill Paul 			dc_rxeof(sc);
311673bf949cSBill Paul 			if (curpkts == ifp->if_ipackets) {
311773bf949cSBill Paul 				while (dc_rx_resync(sc))
311873bf949cSBill Paul 					dc_rxeof(sc);
311973bf949cSBill Paul 			}
312073bf949cSBill Paul 		}
312196f2e892SBill Paul 
312296f2e892SBill Paul 		if (status & DC_ISR_BUS_ERR) {
312396f2e892SBill Paul 			dc_reset(sc);
3124c8b27acaSJohn Baldwin 			dc_init_locked(sc);
312596f2e892SBill Paul 		}
312696f2e892SBill Paul 	}
312796f2e892SBill Paul 
312896f2e892SBill Paul 	/* Re-enable interrupts. */
312996f2e892SBill Paul 	CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
313096f2e892SBill Paul 
3131cbaf877fSBrian Feldman 	if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3132c8b27acaSJohn Baldwin 		dc_start_locked(ifp);
313396f2e892SBill Paul 
3134d1ce9105SBill Paul 	DC_UNLOCK(sc);
313596f2e892SBill Paul }
313696f2e892SBill Paul 
313756e5e7aeSMaxime Henrion static void
313856e5e7aeSMaxime Henrion dc_dma_map_txbuf(arg, segs, nseg, mapsize, error)
313956e5e7aeSMaxime Henrion 	void *arg;
314056e5e7aeSMaxime Henrion 	bus_dma_segment_t *segs;
314156e5e7aeSMaxime Henrion 	int nseg;
314256e5e7aeSMaxime Henrion 	bus_size_t mapsize;
314356e5e7aeSMaxime Henrion 	int error;
314456e5e7aeSMaxime Henrion {
314556e5e7aeSMaxime Henrion 	struct dc_softc *sc;
314656e5e7aeSMaxime Henrion 	struct dc_desc *f;
314756e5e7aeSMaxime Henrion 	int cur, first, frag, i;
314856e5e7aeSMaxime Henrion 
314956e5e7aeSMaxime Henrion 	sc = arg;
315056e5e7aeSMaxime Henrion 	if (error) {
315156e5e7aeSMaxime Henrion 		sc->dc_cdata.dc_tx_err = error;
315256e5e7aeSMaxime Henrion 		return;
315356e5e7aeSMaxime Henrion 	}
315456e5e7aeSMaxime Henrion 
315556e5e7aeSMaxime Henrion 	first = cur = frag = sc->dc_cdata.dc_tx_prod;
315656e5e7aeSMaxime Henrion 	for (i = 0; i < nseg; i++) {
315756e5e7aeSMaxime Henrion 		if ((sc->dc_flags & DC_TX_ADMTEK_WAR) &&
315856e5e7aeSMaxime Henrion 		    (frag == (DC_TX_LIST_CNT - 1)) &&
315956e5e7aeSMaxime Henrion 		    (first != sc->dc_cdata.dc_tx_first)) {
316056e5e7aeSMaxime Henrion 			bus_dmamap_unload(sc->dc_mtag,
316156e5e7aeSMaxime Henrion 			    sc->dc_cdata.dc_tx_map[first]);
316256e5e7aeSMaxime Henrion 			sc->dc_cdata.dc_tx_err = ENOBUFS;
316356e5e7aeSMaxime Henrion 			return;
316456e5e7aeSMaxime Henrion 		}
316556e5e7aeSMaxime Henrion 
316656e5e7aeSMaxime Henrion 		f = &sc->dc_ldata->dc_tx_list[frag];
3167af4358c7SMaxime Henrion 		f->dc_ctl = htole32(DC_TXCTL_TLINK | segs[i].ds_len);
316856e5e7aeSMaxime Henrion 		if (i == 0) {
316956e5e7aeSMaxime Henrion 			f->dc_status = 0;
3170af4358c7SMaxime Henrion 			f->dc_ctl |= htole32(DC_TXCTL_FIRSTFRAG);
317156e5e7aeSMaxime Henrion 		} else
3172af4358c7SMaxime Henrion 			f->dc_status = htole32(DC_TXSTAT_OWN);
3173af4358c7SMaxime Henrion 		f->dc_data = htole32(segs[i].ds_addr);
317456e5e7aeSMaxime Henrion 		cur = frag;
317556e5e7aeSMaxime Henrion 		DC_INC(frag, DC_TX_LIST_CNT);
317656e5e7aeSMaxime Henrion 	}
317756e5e7aeSMaxime Henrion 
317856e5e7aeSMaxime Henrion 	sc->dc_cdata.dc_tx_err = 0;
317956e5e7aeSMaxime Henrion 	sc->dc_cdata.dc_tx_prod = frag;
318056e5e7aeSMaxime Henrion 	sc->dc_cdata.dc_tx_cnt += nseg;
3181af4358c7SMaxime Henrion 	sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_LASTFRAG);
31824ff4a9beSDon Lewis 	sc->dc_cdata.dc_tx_chain[cur] = sc->dc_cdata.dc_tx_mapping;
318356e5e7aeSMaxime Henrion 	if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG)
3184af4358c7SMaxime Henrion 		sc->dc_ldata->dc_tx_list[first].dc_ctl |=
3185af4358c7SMaxime Henrion 		    htole32(DC_TXCTL_FINT);
318656e5e7aeSMaxime Henrion 	if (sc->dc_flags & DC_TX_INTR_ALWAYS)
3187af4358c7SMaxime Henrion 		sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT);
318856e5e7aeSMaxime Henrion 	if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64)
3189af4358c7SMaxime Henrion 		sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT);
3190af4358c7SMaxime Henrion 	sc->dc_ldata->dc_tx_list[first].dc_status = htole32(DC_TXSTAT_OWN);
319156e5e7aeSMaxime Henrion }
319256e5e7aeSMaxime Henrion 
319396f2e892SBill Paul /*
319496f2e892SBill Paul  * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
319596f2e892SBill Paul  * pointers to the fragment pointers.
319696f2e892SBill Paul  */
3197e3d2833aSAlfred Perlstein static int
3198a10c0e45SMike Silbersack dc_encap(struct dc_softc *sc, struct mbuf **m_head)
319996f2e892SBill Paul {
320096f2e892SBill Paul 	struct mbuf *m;
320156e5e7aeSMaxime Henrion 	int error, idx, chainlen = 0;
3202cda97c50SMike Silbersack 
3203cda97c50SMike Silbersack 	/*
3204cda97c50SMike Silbersack 	 * If there's no way we can send any packets, return now.
3205cda97c50SMike Silbersack 	 */
3206cda97c50SMike Silbersack 	if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt < 6)
3207cda97c50SMike Silbersack 		return (ENOBUFS);
3208cda97c50SMike Silbersack 
3209cda97c50SMike Silbersack 	/*
3210cda97c50SMike Silbersack 	 * Count the number of frags in this chain to see if
3211cda97c50SMike Silbersack 	 * we need to m_defrag.  Since the descriptor list is shared
3212cda97c50SMike Silbersack 	 * by all packets, we'll m_defrag long chains so that they
3213cda97c50SMike Silbersack 	 * do not use up the entire list, even if they would fit.
3214cda97c50SMike Silbersack 	 */
3215a10c0e45SMike Silbersack 	for (m = *m_head; m != NULL; m = m->m_next)
3216cda97c50SMike Silbersack 		chainlen++;
3217cda97c50SMike Silbersack 
3218cda97c50SMike Silbersack 	if ((chainlen > DC_TX_LIST_CNT / 4) ||
3219cda97c50SMike Silbersack 	    ((DC_TX_LIST_CNT - (chainlen + sc->dc_cdata.dc_tx_cnt)) < 6)) {
3220a10c0e45SMike Silbersack 		m = m_defrag(*m_head, M_DONTWAIT);
3221cda97c50SMike Silbersack 		if (m == NULL)
3222cda97c50SMike Silbersack 			return (ENOBUFS);
3223a10c0e45SMike Silbersack 		*m_head = m;
3224cda97c50SMike Silbersack 	}
322596f2e892SBill Paul 
322696f2e892SBill Paul 	/*
322796f2e892SBill Paul 	 * Start packing the mbufs in this chain into
322896f2e892SBill Paul 	 * the fragment pointers. Stop when we run out
322996f2e892SBill Paul 	 * of fragments or hit the end of the mbuf chain.
323096f2e892SBill Paul 	 */
323156e5e7aeSMaxime Henrion 	idx = sc->dc_cdata.dc_tx_prod;
32324ff4a9beSDon Lewis 	sc->dc_cdata.dc_tx_mapping = *m_head;
323356e5e7aeSMaxime Henrion 	error = bus_dmamap_load_mbuf(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx],
3234a10c0e45SMike Silbersack 	    *m_head, dc_dma_map_txbuf, sc, 0);
323556e5e7aeSMaxime Henrion 	if (error)
323656e5e7aeSMaxime Henrion 		return (error);
323756e5e7aeSMaxime Henrion 	if (sc->dc_cdata.dc_tx_err != 0)
323856e5e7aeSMaxime Henrion 		return (sc->dc_cdata.dc_tx_err);
323956e5e7aeSMaxime Henrion 	bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx],
324056e5e7aeSMaxime Henrion 	    BUS_DMASYNC_PREWRITE);
324156e5e7aeSMaxime Henrion 	bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap,
324256e5e7aeSMaxime Henrion 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
324396f2e892SBill Paul 	return (0);
324496f2e892SBill Paul }
324596f2e892SBill Paul 
324696f2e892SBill Paul /*
324796f2e892SBill Paul  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
324896f2e892SBill Paul  * to the mbuf data regions directly in the transmit lists. We also save a
324996f2e892SBill Paul  * copy of the pointers since the transmit list fragment pointers are
325096f2e892SBill Paul  * physical addresses.
325196f2e892SBill Paul  */
325296f2e892SBill Paul 
3253e3d2833aSAlfred Perlstein static void
32540934f18aSMaxime Henrion dc_start(struct ifnet *ifp)
325596f2e892SBill Paul {
325696f2e892SBill Paul 	struct dc_softc *sc;
3257c8b27acaSJohn Baldwin 
3258c8b27acaSJohn Baldwin 	sc = ifp->if_softc;
3259c8b27acaSJohn Baldwin 	DC_LOCK(sc);
3260c8b27acaSJohn Baldwin 	dc_start_locked(ifp);
3261c8b27acaSJohn Baldwin 	DC_UNLOCK(sc);
3262c8b27acaSJohn Baldwin }
3263c8b27acaSJohn Baldwin 
3264c8b27acaSJohn Baldwin static void
3265c8b27acaSJohn Baldwin dc_start_locked(struct ifnet *ifp)
3266c8b27acaSJohn Baldwin {
3267c8b27acaSJohn Baldwin 	struct dc_softc *sc;
3268cda97c50SMike Silbersack 	struct mbuf *m_head = NULL, *m;
3269cbaf877fSBrian Feldman 	unsigned int queued = 0;
327096f2e892SBill Paul 	int idx;
327196f2e892SBill Paul 
327296f2e892SBill Paul 	sc = ifp->if_softc;
327396f2e892SBill Paul 
3274c8b27acaSJohn Baldwin 	DC_LOCK_ASSERT(sc);
327596f2e892SBill Paul 
3276c8b27acaSJohn Baldwin 	if (!sc->dc_link && ifp->if_snd.ifq_len < 10)
327796f2e892SBill Paul 		return;
3278d1ce9105SBill Paul 
3279c8b27acaSJohn Baldwin 	if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
3280d1ce9105SBill Paul 		return;
328196f2e892SBill Paul 
328256e5e7aeSMaxime Henrion 	idx = sc->dc_cdata.dc_tx_first = sc->dc_cdata.dc_tx_prod;
328396f2e892SBill Paul 
328496f2e892SBill Paul 	while (sc->dc_cdata.dc_tx_chain[idx] == NULL) {
3285cbaf877fSBrian Feldman 		IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
328696f2e892SBill Paul 		if (m_head == NULL)
328796f2e892SBill Paul 			break;
328896f2e892SBill Paul 
32892dfc960aSLuigi Rizzo 		if (sc->dc_flags & DC_TX_COALESCE &&
32902dfc960aSLuigi Rizzo 		    (m_head->m_next != NULL ||
32912dfc960aSLuigi Rizzo 		     sc->dc_flags & DC_TX_ALIGN)) {
3292cda97c50SMike Silbersack 			m = m_defrag(m_head, M_DONTWAIT);
3293cda97c50SMike Silbersack 			if (m == NULL) {
3294cbaf877fSBrian Feldman 				IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
329513f4c340SRobert Watson 				ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3296fda39fd0SBill Paul 				break;
3297cda97c50SMike Silbersack 			} else {
3298cda97c50SMike Silbersack 				m_head = m;
3299fda39fd0SBill Paul 			}
3300fda39fd0SBill Paul 		}
3301fda39fd0SBill Paul 
3302a10c0e45SMike Silbersack 		if (dc_encap(sc, &m_head)) {
3303cbaf877fSBrian Feldman 			IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
330413f4c340SRobert Watson 			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
330596f2e892SBill Paul 			break;
330696f2e892SBill Paul 		}
330756e5e7aeSMaxime Henrion 		idx = sc->dc_cdata.dc_tx_prod;
330896f2e892SBill Paul 
3309cbaf877fSBrian Feldman 		queued++;
331096f2e892SBill Paul 		/*
331196f2e892SBill Paul 		 * If there's a BPF listener, bounce a copy of this frame
331296f2e892SBill Paul 		 * to him.
331396f2e892SBill Paul 		 */
33149ef8b520SSam Leffler 		BPF_MTAP(ifp, m_head);
33155c1cfac4SBill Paul 
33165c1cfac4SBill Paul 		if (sc->dc_flags & DC_TX_ONE) {
331713f4c340SRobert Watson 			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
33185c1cfac4SBill Paul 			break;
33195c1cfac4SBill Paul 		}
332096f2e892SBill Paul 	}
332196f2e892SBill Paul 
3322cbaf877fSBrian Feldman 	if (queued > 0) {
332396f2e892SBill Paul 		/* Transmit */
332496f2e892SBill Paul 		if (!(sc->dc_flags & DC_TX_POLL))
332596f2e892SBill Paul 			CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
332696f2e892SBill Paul 
332796f2e892SBill Paul 		/*
332896f2e892SBill Paul 		 * Set a timeout in case the chip goes out to lunch.
332996f2e892SBill Paul 		 */
333096f2e892SBill Paul 		ifp->if_timer = 5;
3331cbaf877fSBrian Feldman 	}
333296f2e892SBill Paul }
333396f2e892SBill Paul 
3334e3d2833aSAlfred Perlstein static void
33350934f18aSMaxime Henrion dc_init(void *xsc)
333696f2e892SBill Paul {
333796f2e892SBill Paul 	struct dc_softc *sc = xsc;
3338c8b27acaSJohn Baldwin 
3339c8b27acaSJohn Baldwin 	DC_LOCK(sc);
3340c8b27acaSJohn Baldwin 	dc_init_locked(sc);
3341c8b27acaSJohn Baldwin 	DC_UNLOCK(sc);
3342c8b27acaSJohn Baldwin }
3343c8b27acaSJohn Baldwin 
3344c8b27acaSJohn Baldwin static void
3345c8b27acaSJohn Baldwin dc_init_locked(struct dc_softc *sc)
3346c8b27acaSJohn Baldwin {
3347fc74a9f9SBrooks Davis 	struct ifnet *ifp = sc->dc_ifp;
334896f2e892SBill Paul 	struct mii_data *mii;
334996f2e892SBill Paul 
3350c8b27acaSJohn Baldwin 	DC_LOCK_ASSERT(sc);
335196f2e892SBill Paul 
335296f2e892SBill Paul 	mii = device_get_softc(sc->dc_miibus);
335396f2e892SBill Paul 
335496f2e892SBill Paul 	/*
335596f2e892SBill Paul 	 * Cancel pending I/O and free all RX/TX buffers.
335696f2e892SBill Paul 	 */
335796f2e892SBill Paul 	dc_stop(sc);
335896f2e892SBill Paul 	dc_reset(sc);
335996f2e892SBill Paul 
336096f2e892SBill Paul 	/*
336196f2e892SBill Paul 	 * Set cache alignment and burst length.
336296f2e892SBill Paul 	 */
336388d739dcSBill Paul 	if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc))
336496f2e892SBill Paul 		CSR_WRITE_4(sc, DC_BUSCTL, 0);
336596f2e892SBill Paul 	else
336696f2e892SBill Paul 		CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME | DC_BUSCTL_MRLE);
3367935fe010SLuigi Rizzo 	/*
3368935fe010SLuigi Rizzo 	 * Evenly share the bus between receive and transmit process.
3369935fe010SLuigi Rizzo 	 */
3370935fe010SLuigi Rizzo 	if (DC_IS_INTEL(sc))
3371935fe010SLuigi Rizzo 		DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION);
337296f2e892SBill Paul 	if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) {
337396f2e892SBill Paul 		DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA);
337496f2e892SBill Paul 	} else {
337596f2e892SBill Paul 		DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG);
337696f2e892SBill Paul 	}
337796f2e892SBill Paul 	if (sc->dc_flags & DC_TX_POLL)
337896f2e892SBill Paul 		DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1);
337996f2e892SBill Paul 	switch(sc->dc_cachesize) {
338096f2e892SBill Paul 	case 32:
338196f2e892SBill Paul 		DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG);
338296f2e892SBill Paul 		break;
338396f2e892SBill Paul 	case 16:
338496f2e892SBill Paul 		DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG);
338596f2e892SBill Paul 		break;
338696f2e892SBill Paul 	case 8:
338796f2e892SBill Paul 		DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG);
338896f2e892SBill Paul 		break;
338996f2e892SBill Paul 	case 0:
339096f2e892SBill Paul 	default:
339196f2e892SBill Paul 		DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE);
339296f2e892SBill Paul 		break;
339396f2e892SBill Paul 	}
339496f2e892SBill Paul 
339596f2e892SBill Paul 	if (sc->dc_flags & DC_TX_STORENFWD)
339696f2e892SBill Paul 		DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
339796f2e892SBill Paul 	else {
3398d467c136SBill Paul 		if (sc->dc_txthresh > DC_TXTHRESH_MAX) {
339996f2e892SBill Paul 			DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
340096f2e892SBill Paul 		} else {
340196f2e892SBill Paul 			DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
340296f2e892SBill Paul 			DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh);
340396f2e892SBill Paul 		}
340496f2e892SBill Paul 	}
340596f2e892SBill Paul 
340696f2e892SBill Paul 	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC);
340796f2e892SBill Paul 	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF);
340896f2e892SBill Paul 
340996f2e892SBill Paul 	if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) {
341096f2e892SBill Paul 		/*
341196f2e892SBill Paul 		 * The app notes for the 98713 and 98715A say that
341296f2e892SBill Paul 		 * in order to have the chips operate properly, a magic
341396f2e892SBill Paul 		 * number must be written to CSR16. Macronix does not
341496f2e892SBill Paul 		 * document the meaning of these bits so there's no way
341596f2e892SBill Paul 		 * to know exactly what they do. The 98713 has a magic
341696f2e892SBill Paul 		 * number all its own; the rest all use a different one.
341796f2e892SBill Paul 		 */
341896f2e892SBill Paul 		DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000);
341996f2e892SBill Paul 		if (sc->dc_type == DC_TYPE_98713)
342096f2e892SBill Paul 			DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713);
342196f2e892SBill Paul 		else
342296f2e892SBill Paul 			DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715);
342396f2e892SBill Paul 	}
342496f2e892SBill Paul 
3425feb78939SJonathan Chen 	if (DC_IS_XIRCOM(sc)) {
3426feb78939SJonathan Chen 		/*
3427feb78939SJonathan Chen 		 * setup General Purpose Port mode and data so the tulip
3428feb78939SJonathan Chen 		 * can talk to the MII.
3429feb78939SJonathan Chen 		 */
3430feb78939SJonathan Chen 		CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN |
3431feb78939SJonathan Chen 			   DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
3432feb78939SJonathan Chen 		DELAY(10);
3433feb78939SJonathan Chen 		CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN |
3434feb78939SJonathan Chen 			   DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
3435feb78939SJonathan Chen 		DELAY(10);
3436feb78939SJonathan Chen 	}
3437feb78939SJonathan Chen 
343896f2e892SBill Paul 	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH);
3439d467c136SBill Paul 	DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN);
344096f2e892SBill Paul 
344196f2e892SBill Paul 	/* Init circular RX list. */
344296f2e892SBill Paul 	if (dc_list_rx_init(sc) == ENOBUFS) {
344322f6205dSJohn Baldwin 		if_printf(ifp,
344422f6205dSJohn Baldwin 		    "initialization failed: no memory for rx buffers\n");
344596f2e892SBill Paul 		dc_stop(sc);
344696f2e892SBill Paul 		return;
344796f2e892SBill Paul 	}
344896f2e892SBill Paul 
344996f2e892SBill Paul 	/*
345056e5e7aeSMaxime Henrion 	 * Init TX descriptors.
345196f2e892SBill Paul 	 */
345296f2e892SBill Paul 	dc_list_tx_init(sc);
345396f2e892SBill Paul 
345496f2e892SBill Paul 	/*
345596f2e892SBill Paul 	 * Load the address of the RX list.
345696f2e892SBill Paul 	 */
345756e5e7aeSMaxime Henrion 	CSR_WRITE_4(sc, DC_RXADDR, DC_RXDESC(sc, 0));
345856e5e7aeSMaxime Henrion 	CSR_WRITE_4(sc, DC_TXADDR, DC_TXDESC(sc, 0));
345996f2e892SBill Paul 
346096f2e892SBill Paul 	/*
346196f2e892SBill Paul 	 * Enable interrupts.
346296f2e892SBill Paul 	 */
3463e4fc250cSLuigi Rizzo #ifdef DEVICE_POLLING
3464e4fc250cSLuigi Rizzo 	/*
3465e4fc250cSLuigi Rizzo 	 * ... but only if we are not polling, and make sure they are off in
3466e4fc250cSLuigi Rizzo 	 * the case of polling. Some cards (e.g. fxp) turn interrupts on
3467e4fc250cSLuigi Rizzo 	 * after a reset.
3468e4fc250cSLuigi Rizzo 	 */
346940929967SGleb Smirnoff 	if (ifp->if_capenable & IFCAP_POLLING)
3470e4fc250cSLuigi Rizzo 		CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3471e4fc250cSLuigi Rizzo 	else
3472e4fc250cSLuigi Rizzo #endif
347396f2e892SBill Paul 	CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
347496f2e892SBill Paul 	CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF);
347596f2e892SBill Paul 
347696f2e892SBill Paul 	/* Enable transmitter. */
347796f2e892SBill Paul 	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
347896f2e892SBill Paul 
347996f2e892SBill Paul 	/*
3480918434c8SBill Paul 	 * If this is an Intel 21143 and we're not using the
3481918434c8SBill Paul 	 * MII port, program the LED control pins so we get
3482918434c8SBill Paul 	 * link and activity indications.
3483918434c8SBill Paul 	 */
348478999dd1SBill Paul 	if (sc->dc_flags & DC_TULIP_LEDS) {
3485918434c8SBill Paul 		CSR_WRITE_4(sc, DC_WATCHDOG,
3486918434c8SBill Paul 		    DC_WDOG_CTLWREN | DC_WDOG_LINK | DC_WDOG_ACTIVITY);
348778999dd1SBill Paul 		CSR_WRITE_4(sc, DC_WATCHDOG, 0);
3488918434c8SBill Paul 	}
3489918434c8SBill Paul 
3490918434c8SBill Paul 	/*
349196f2e892SBill Paul 	 * Load the RX/multicast filter. We do this sort of late
349296f2e892SBill Paul 	 * because the filter programming scheme on the 21143 and
349396f2e892SBill Paul 	 * some clones requires DMAing a setup frame via the TX
349496f2e892SBill Paul 	 * engine, and we need the transmitter enabled for that.
349596f2e892SBill Paul 	 */
349696f2e892SBill Paul 	dc_setfilt(sc);
349796f2e892SBill Paul 
349896f2e892SBill Paul 	/* Enable receiver. */
349996f2e892SBill Paul 	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON);
350096f2e892SBill Paul 	CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF);
350196f2e892SBill Paul 
350296f2e892SBill Paul 	mii_mediachg(mii);
350396f2e892SBill Paul 	dc_setcfg(sc, sc->dc_if_media);
350496f2e892SBill Paul 
350513f4c340SRobert Watson 	ifp->if_drv_flags |= IFF_DRV_RUNNING;
350613f4c340SRobert Watson 	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
350796f2e892SBill Paul 
3508857fd445SBill Paul 	/* Don't start the ticker if this is a homePNA link. */
350945521525SPoul-Henning Kamp 	if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1)
3510857fd445SBill Paul 		sc->dc_link = 1;
3511857fd445SBill Paul 	else {
3512318b02fdSBill Paul 		if (sc->dc_flags & DC_21143_NWAY)
3513b50c6312SJonathan Lemon 			callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc);
3514318b02fdSBill Paul 		else
3515b50c6312SJonathan Lemon 			callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc);
3516857fd445SBill Paul 	}
351796f2e892SBill Paul }
351896f2e892SBill Paul 
351996f2e892SBill Paul /*
352096f2e892SBill Paul  * Set media options.
352196f2e892SBill Paul  */
3522e3d2833aSAlfred Perlstein static int
35230934f18aSMaxime Henrion dc_ifmedia_upd(struct ifnet *ifp)
352496f2e892SBill Paul {
352596f2e892SBill Paul 	struct dc_softc *sc;
352696f2e892SBill Paul 	struct mii_data *mii;
3527f43d9309SBill Paul 	struct ifmedia *ifm;
352896f2e892SBill Paul 
352996f2e892SBill Paul 	sc = ifp->if_softc;
353096f2e892SBill Paul 	mii = device_get_softc(sc->dc_miibus);
3531c8b27acaSJohn Baldwin 	DC_LOCK(sc);
353296f2e892SBill Paul 	mii_mediachg(mii);
3533f43d9309SBill Paul 	ifm = &mii->mii_media;
3534f43d9309SBill Paul 
3535f43d9309SBill Paul 	if (DC_IS_DAVICOM(sc) &&
353645521525SPoul-Henning Kamp 	    IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1)
3537f43d9309SBill Paul 		dc_setcfg(sc, ifm->ifm_media);
3538f43d9309SBill Paul 	else
353996f2e892SBill Paul 		sc->dc_link = 0;
3540c8b27acaSJohn Baldwin 	DC_UNLOCK(sc);
354196f2e892SBill Paul 
354296f2e892SBill Paul 	return (0);
354396f2e892SBill Paul }
354496f2e892SBill Paul 
354596f2e892SBill Paul /*
354696f2e892SBill Paul  * Report current media status.
354796f2e892SBill Paul  */
3548e3d2833aSAlfred Perlstein static void
35490934f18aSMaxime Henrion dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
355096f2e892SBill Paul {
355196f2e892SBill Paul 	struct dc_softc *sc;
355296f2e892SBill Paul 	struct mii_data *mii;
3553f43d9309SBill Paul 	struct ifmedia *ifm;
355496f2e892SBill Paul 
355596f2e892SBill Paul 	sc = ifp->if_softc;
355696f2e892SBill Paul 	mii = device_get_softc(sc->dc_miibus);
3557c8b27acaSJohn Baldwin 	DC_LOCK(sc);
355896f2e892SBill Paul 	mii_pollstat(mii);
3559f43d9309SBill Paul 	ifm = &mii->mii_media;
3560f43d9309SBill Paul 	if (DC_IS_DAVICOM(sc)) {
356145521525SPoul-Henning Kamp 		if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) {
3562f43d9309SBill Paul 			ifmr->ifm_active = ifm->ifm_media;
3563f43d9309SBill Paul 			ifmr->ifm_status = 0;
3564f43d9309SBill Paul 			return;
3565f43d9309SBill Paul 		}
3566f43d9309SBill Paul 	}
356796f2e892SBill Paul 	ifmr->ifm_active = mii->mii_media_active;
356896f2e892SBill Paul 	ifmr->ifm_status = mii->mii_media_status;
3569c8b27acaSJohn Baldwin 	DC_UNLOCK(sc);
357096f2e892SBill Paul }
357196f2e892SBill Paul 
3572e3d2833aSAlfred Perlstein static int
35730934f18aSMaxime Henrion dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
357496f2e892SBill Paul {
357596f2e892SBill Paul 	struct dc_softc *sc = ifp->if_softc;
357696f2e892SBill Paul 	struct ifreq *ifr = (struct ifreq *)data;
357796f2e892SBill Paul 	struct mii_data *mii;
3578d1ce9105SBill Paul 	int error = 0;
357996f2e892SBill Paul 
358096f2e892SBill Paul 	switch (command) {
358196f2e892SBill Paul 	case SIOCSIFFLAGS:
3582c8b27acaSJohn Baldwin 		DC_LOCK(sc);
358396f2e892SBill Paul 		if (ifp->if_flags & IFF_UP) {
35845d6dfbbbSLuigi Rizzo 			int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) &
35855d6dfbbbSLuigi Rizzo 				(IFF_PROMISC | IFF_ALLMULTI);
35865d6dfbbbSLuigi Rizzo 
358713f4c340SRobert Watson 			if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
35885d6dfbbbSLuigi Rizzo 				if (need_setfilt)
358996f2e892SBill Paul 					dc_setfilt(sc);
35905d6dfbbbSLuigi Rizzo 			} else {
359196f2e892SBill Paul 				sc->dc_txthresh = 0;
3592c8b27acaSJohn Baldwin 				dc_init_locked(sc);
359396f2e892SBill Paul 			}
359496f2e892SBill Paul 		} else {
359513f4c340SRobert Watson 			if (ifp->if_drv_flags & IFF_DRV_RUNNING)
359696f2e892SBill Paul 				dc_stop(sc);
359796f2e892SBill Paul 		}
359896f2e892SBill Paul 		sc->dc_if_flags = ifp->if_flags;
3599c8b27acaSJohn Baldwin 		DC_UNLOCK(sc);
360096f2e892SBill Paul 		error = 0;
360196f2e892SBill Paul 		break;
360296f2e892SBill Paul 	case SIOCADDMULTI:
360396f2e892SBill Paul 	case SIOCDELMULTI:
3604c8b27acaSJohn Baldwin 		DC_LOCK(sc);
360596f2e892SBill Paul 		dc_setfilt(sc);
3606c8b27acaSJohn Baldwin 		DC_UNLOCK(sc);
360796f2e892SBill Paul 		error = 0;
360896f2e892SBill Paul 		break;
360996f2e892SBill Paul 	case SIOCGIFMEDIA:
361096f2e892SBill Paul 	case SIOCSIFMEDIA:
361196f2e892SBill Paul 		mii = device_get_softc(sc->dc_miibus);
361296f2e892SBill Paul 		error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
361396f2e892SBill Paul 		break;
3614e695984eSRuslan Ermilov 	case SIOCSIFCAP:
361540929967SGleb Smirnoff #ifdef DEVICE_POLLING
361640929967SGleb Smirnoff 		if (ifr->ifr_reqcap & IFCAP_POLLING &&
361740929967SGleb Smirnoff 		    !(ifp->if_capenable & IFCAP_POLLING)) {
361840929967SGleb Smirnoff 			error = ether_poll_register(dc_poll, ifp);
361940929967SGleb Smirnoff 			if (error)
362040929967SGleb Smirnoff 				return(error);
3621c8b27acaSJohn Baldwin 			DC_LOCK(sc);
362240929967SGleb Smirnoff 			/* Disable interrupts */
362340929967SGleb Smirnoff 			CSR_WRITE_4(sc, DC_IMR, 0x00000000);
362440929967SGleb Smirnoff 			ifp->if_capenable |= IFCAP_POLLING;
3625c8b27acaSJohn Baldwin 			DC_UNLOCK(sc);
362640929967SGleb Smirnoff 			return (error);
362740929967SGleb Smirnoff 
362840929967SGleb Smirnoff 		}
362940929967SGleb Smirnoff 		if (!(ifr->ifr_reqcap & IFCAP_POLLING) &&
363040929967SGleb Smirnoff 		    ifp->if_capenable & IFCAP_POLLING) {
363140929967SGleb Smirnoff 			error = ether_poll_deregister(ifp);
363240929967SGleb Smirnoff 			/* Enable interrupts. */
363340929967SGleb Smirnoff 			DC_LOCK(sc);
363440929967SGleb Smirnoff 			CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
363540929967SGleb Smirnoff 			ifp->if_capenable &= ~IFCAP_POLLING;
363640929967SGleb Smirnoff 			DC_UNLOCK(sc);
363740929967SGleb Smirnoff 			return (error);
363840929967SGleb Smirnoff 		}
363940929967SGleb Smirnoff #endif /* DEVICE_POLLING */
3640e695984eSRuslan Ermilov 		break;
364196f2e892SBill Paul 	default:
36429ef8b520SSam Leffler 		error = ether_ioctl(ifp, command, data);
364396f2e892SBill Paul 		break;
364496f2e892SBill Paul 	}
364596f2e892SBill Paul 
364696f2e892SBill Paul 	return (error);
364796f2e892SBill Paul }
364896f2e892SBill Paul 
3649e3d2833aSAlfred Perlstein static void
36500934f18aSMaxime Henrion dc_watchdog(struct ifnet *ifp)
365196f2e892SBill Paul {
365296f2e892SBill Paul 	struct dc_softc *sc;
365396f2e892SBill Paul 
365496f2e892SBill Paul 	sc = ifp->if_softc;
365596f2e892SBill Paul 
3656d1ce9105SBill Paul 	DC_LOCK(sc);
3657d1ce9105SBill Paul 
365896f2e892SBill Paul 	ifp->if_oerrors++;
365922f6205dSJohn Baldwin 	if_printf(ifp, "watchdog timeout\n");
366096f2e892SBill Paul 
366196f2e892SBill Paul 	dc_stop(sc);
366296f2e892SBill Paul 	dc_reset(sc);
3663c8b27acaSJohn Baldwin 	dc_init_locked(sc);
366496f2e892SBill Paul 
3665cbaf877fSBrian Feldman 	if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3666c8b27acaSJohn Baldwin 		dc_start_locked(ifp);
366796f2e892SBill Paul 
3668d1ce9105SBill Paul 	DC_UNLOCK(sc);
366996f2e892SBill Paul }
367096f2e892SBill Paul 
367196f2e892SBill Paul /*
367296f2e892SBill Paul  * Stop the adapter and free any mbufs allocated to the
367396f2e892SBill Paul  * RX and TX lists.
367496f2e892SBill Paul  */
3675e3d2833aSAlfred Perlstein static void
36760934f18aSMaxime Henrion dc_stop(struct dc_softc *sc)
367796f2e892SBill Paul {
367896f2e892SBill Paul 	struct ifnet *ifp;
3679b3811c95SMaxime Henrion 	struct dc_list_data *ld;
3680b3811c95SMaxime Henrion 	struct dc_chain_data *cd;
3681b3811c95SMaxime Henrion 	int i;
3682af4358c7SMaxime Henrion 	u_int32_t ctl;
368396f2e892SBill Paul 
3684c8b27acaSJohn Baldwin 	DC_LOCK_ASSERT(sc);
3685d1ce9105SBill Paul 
3686fc74a9f9SBrooks Davis 	ifp = sc->dc_ifp;
368796f2e892SBill Paul 	ifp->if_timer = 0;
3688b3811c95SMaxime Henrion 	ld = sc->dc_ldata;
3689b3811c95SMaxime Henrion 	cd = &sc->dc_cdata;
369096f2e892SBill Paul 
3691b50c6312SJonathan Lemon 	callout_stop(&sc->dc_stat_ch);
369296f2e892SBill Paul 
369313f4c340SRobert Watson 	ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
36943b3ec200SPeter Wemm 
369596f2e892SBill Paul 	DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON));
369696f2e892SBill Paul 	CSR_WRITE_4(sc, DC_IMR, 0x00000000);
369796f2e892SBill Paul 	CSR_WRITE_4(sc, DC_TXADDR, 0x00000000);
369896f2e892SBill Paul 	CSR_WRITE_4(sc, DC_RXADDR, 0x00000000);
369996f2e892SBill Paul 	sc->dc_link = 0;
370096f2e892SBill Paul 
370196f2e892SBill Paul 	/*
370296f2e892SBill Paul 	 * Free data in the RX lists.
370396f2e892SBill Paul 	 */
370496f2e892SBill Paul 	for (i = 0; i < DC_RX_LIST_CNT; i++) {
3705b3811c95SMaxime Henrion 		if (cd->dc_rx_chain[i] != NULL) {
370656e5e7aeSMaxime Henrion 			m_freem(cd->dc_rx_chain[i]);
370756e5e7aeSMaxime Henrion 			cd->dc_rx_chain[i] = NULL;
370896f2e892SBill Paul 		}
370996f2e892SBill Paul 	}
3710b3811c95SMaxime Henrion 	bzero(&ld->dc_rx_list, sizeof(ld->dc_rx_list));
371196f2e892SBill Paul 
371296f2e892SBill Paul 	/*
371396f2e892SBill Paul 	 * Free the TX list buffers.
371496f2e892SBill Paul 	 */
371596f2e892SBill Paul 	for (i = 0; i < DC_TX_LIST_CNT; i++) {
3716b3811c95SMaxime Henrion 		if (cd->dc_tx_chain[i] != NULL) {
3717af4358c7SMaxime Henrion 			ctl = le32toh(ld->dc_tx_list[i].dc_ctl);
3718af4358c7SMaxime Henrion 			if ((ctl & DC_TXCTL_SETUP) ||
37194ff4a9beSDon Lewis 			    !(ctl & DC_TXCTL_LASTFRAG)) {
3720b3811c95SMaxime Henrion 				cd->dc_tx_chain[i] = NULL;
372196f2e892SBill Paul 				continue;
372296f2e892SBill Paul 			}
372356e5e7aeSMaxime Henrion 			bus_dmamap_unload(sc->dc_mtag, cd->dc_tx_map[i]);
372456e5e7aeSMaxime Henrion 			m_freem(cd->dc_tx_chain[i]);
3725b3811c95SMaxime Henrion 			cd->dc_tx_chain[i] = NULL;
372696f2e892SBill Paul 		}
372796f2e892SBill Paul 	}
3728b3811c95SMaxime Henrion 	bzero(&ld->dc_tx_list, sizeof(ld->dc_tx_list));
372996f2e892SBill Paul }
373096f2e892SBill Paul 
373196f2e892SBill Paul /*
3732e8388e14SMitsuru IWASAKI  * Device suspend routine.  Stop the interface and save some PCI
3733e8388e14SMitsuru IWASAKI  * settings in case the BIOS doesn't restore them properly on
3734e8388e14SMitsuru IWASAKI  * resume.
3735e8388e14SMitsuru IWASAKI  */
3736e3d2833aSAlfred Perlstein static int
37370934f18aSMaxime Henrion dc_suspend(device_t dev)
3738e8388e14SMitsuru IWASAKI {
3739e8388e14SMitsuru IWASAKI 	struct dc_softc *sc;
3740e8388e14SMitsuru IWASAKI 
3741e8388e14SMitsuru IWASAKI 	sc = device_get_softc(dev);
3742c8b27acaSJohn Baldwin 	DC_LOCK(sc);
3743e8388e14SMitsuru IWASAKI 	dc_stop(sc);
3744e8388e14SMitsuru IWASAKI 	sc->suspended = 1;
3745c8b27acaSJohn Baldwin 	DC_UNLOCK(sc);
3746e8388e14SMitsuru IWASAKI 
3747e8388e14SMitsuru IWASAKI 	return (0);
3748e8388e14SMitsuru IWASAKI }
3749e8388e14SMitsuru IWASAKI 
3750e8388e14SMitsuru IWASAKI /*
3751e8388e14SMitsuru IWASAKI  * Device resume routine.  Restore some PCI settings in case the BIOS
3752e8388e14SMitsuru IWASAKI  * doesn't, re-enable busmastering, and restart the interface if
3753e8388e14SMitsuru IWASAKI  * appropriate.
3754e8388e14SMitsuru IWASAKI  */
3755e3d2833aSAlfred Perlstein static int
37560934f18aSMaxime Henrion dc_resume(device_t dev)
3757e8388e14SMitsuru IWASAKI {
3758e8388e14SMitsuru IWASAKI 	struct dc_softc *sc;
3759e8388e14SMitsuru IWASAKI 	struct ifnet *ifp;
3760e8388e14SMitsuru IWASAKI 
3761e8388e14SMitsuru IWASAKI 	sc = device_get_softc(dev);
3762fc74a9f9SBrooks Davis 	ifp = sc->dc_ifp;
3763e8388e14SMitsuru IWASAKI 
3764e8388e14SMitsuru IWASAKI 	/* reinitialize interface if necessary */
3765c8b27acaSJohn Baldwin 	DC_LOCK(sc);
3766e8388e14SMitsuru IWASAKI 	if (ifp->if_flags & IFF_UP)
3767c8b27acaSJohn Baldwin 		dc_init_locked(sc);
3768e8388e14SMitsuru IWASAKI 
3769e8388e14SMitsuru IWASAKI 	sc->suspended = 0;
3770c8b27acaSJohn Baldwin 	DC_UNLOCK(sc);
3771e8388e14SMitsuru IWASAKI 
3772e8388e14SMitsuru IWASAKI 	return (0);
3773e8388e14SMitsuru IWASAKI }
3774e8388e14SMitsuru IWASAKI 
3775e8388e14SMitsuru IWASAKI /*
377696f2e892SBill Paul  * Stop all chip I/O so that the kernel's probe routines don't
377796f2e892SBill Paul  * get confused by errant DMAs when rebooting.
377896f2e892SBill Paul  */
3779e3d2833aSAlfred Perlstein static void
37800934f18aSMaxime Henrion dc_shutdown(device_t dev)
378196f2e892SBill Paul {
378296f2e892SBill Paul 	struct dc_softc *sc;
378396f2e892SBill Paul 
378496f2e892SBill Paul 	sc = device_get_softc(dev);
378596f2e892SBill Paul 
3786c8b27acaSJohn Baldwin 	DC_LOCK(sc);
378796f2e892SBill Paul 	dc_stop(sc);
3788c8b27acaSJohn Baldwin 	DC_UNLOCK(sc);
378996f2e892SBill Paul }
3790