xref: /freebsd/sys/dev/dc/if_dc.c (revision 155781198a1e5f675dbb3bb8b4df4ecc182c67f9)
160727d8bSWarner Losh /*-
296f2e892SBill Paul  * Copyright (c) 1997, 1998, 1999
396f2e892SBill Paul  *	Bill Paul <wpaul@ee.columbia.edu>.  All rights reserved.
496f2e892SBill Paul  *
596f2e892SBill Paul  * Redistribution and use in source and binary forms, with or without
696f2e892SBill Paul  * modification, are permitted provided that the following conditions
796f2e892SBill Paul  * are met:
896f2e892SBill Paul  * 1. Redistributions of source code must retain the above copyright
996f2e892SBill Paul  *    notice, this list of conditions and the following disclaimer.
1096f2e892SBill Paul  * 2. Redistributions in binary form must reproduce the above copyright
1196f2e892SBill Paul  *    notice, this list of conditions and the following disclaimer in the
1296f2e892SBill Paul  *    documentation and/or other materials provided with the distribution.
1396f2e892SBill Paul  * 3. All advertising materials mentioning features or use of this software
1496f2e892SBill Paul  *    must display the following acknowledgement:
1596f2e892SBill Paul  *	This product includes software developed by Bill Paul.
1696f2e892SBill Paul  * 4. Neither the name of the author nor the names of any co-contributors
1796f2e892SBill Paul  *    may be used to endorse or promote products derived from this software
1896f2e892SBill Paul  *    without specific prior written permission.
1996f2e892SBill Paul  *
2096f2e892SBill Paul  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
2196f2e892SBill Paul  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
2296f2e892SBill Paul  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
2396f2e892SBill Paul  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
2496f2e892SBill Paul  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
2596f2e892SBill Paul  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
2696f2e892SBill Paul  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
2796f2e892SBill Paul  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
2896f2e892SBill Paul  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
2996f2e892SBill Paul  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
3096f2e892SBill Paul  * THE POSSIBILITY OF SUCH DAMAGE.
3196f2e892SBill Paul  */
3296f2e892SBill Paul 
334dc52c32SDavid E. O'Brien #include <sys/cdefs.h>
344dc52c32SDavid E. O'Brien __FBSDID("$FreeBSD$");
354dc52c32SDavid E. O'Brien 
3696f2e892SBill Paul /*
3796f2e892SBill Paul  * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143
3896f2e892SBill Paul  * series chips and several workalikes including the following:
3996f2e892SBill Paul  *
40ead7cde9SBill Paul  * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com)
4196f2e892SBill Paul  * Macronix/Lite-On 82c115 PNIC II (www.macronix.com)
4296f2e892SBill Paul  * Lite-On 82c168/82c169 PNIC (www.litecom.com)
4396f2e892SBill Paul  * ASIX Electronics AX88140A (www.asix.com.tw)
4496f2e892SBill Paul  * ASIX Electronics AX88141 (www.asix.com.tw)
4596f2e892SBill Paul  * ADMtek AL981 (www.admtek.com.tw)
4696f2e892SBill Paul  * ADMtek AN985 (www.admtek.com.tw)
474c16d09eSWarner Losh  * Netgear FA511 (www.netgear.com) Appears to be rebadged ADMTek AN985
4888d739dcSBill Paul  * Davicom DM9100, DM9102, DM9102A (www.davicom8.com)
499ca710f6SJeroen Ruigrok van der Werven  * Accton EN1217 (www.accton.com)
50feb78939SJonathan Chen  * Xircom X3201 (www.xircom.com)
511d5e5310SBill Paul  * Abocom FE2500
521af8bec7SBill Paul  * Conexant LANfinity (www.conexant.com)
537eac366bSMartin Blapp  * 3Com OfficeConnect 10/100B 3CSOHO100B (www.3com.com)
5496f2e892SBill Paul  *
5596f2e892SBill Paul  * Datasheets for the 21143 are available at developer.intel.com.
5696f2e892SBill Paul  * Datasheets for the clone parts can be found at their respective sites.
5796f2e892SBill Paul  * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.)
5896f2e892SBill Paul  * The PNIC II is essentially a Macronix 98715A chip; the only difference
5996f2e892SBill Paul  * worth noting is that its multicast hash table is only 128 bits wide
6096f2e892SBill Paul  * instead of 512.
6196f2e892SBill Paul  *
6296f2e892SBill Paul  * Written by Bill Paul <wpaul@ee.columbia.edu>
6396f2e892SBill Paul  * Electrical Engineering Department
6496f2e892SBill Paul  * Columbia University, New York City
6596f2e892SBill Paul  */
6696f2e892SBill Paul /*
6796f2e892SBill Paul  * The Intel 21143 is the successor to the DEC 21140. It is basically
6896f2e892SBill Paul  * the same as the 21140 but with a few new features. The 21143 supports
6996f2e892SBill Paul  * three kinds of media attachments:
7096f2e892SBill Paul  *
7196f2e892SBill Paul  * o MII port, for 10Mbps and 100Mbps support and NWAY
7296f2e892SBill Paul  *   autonegotiation provided by an external PHY.
7396f2e892SBill Paul  * o SYM port, for symbol mode 100Mbps support.
7496f2e892SBill Paul  * o 10baseT port.
7596f2e892SBill Paul  * o AUI/BNC port.
7696f2e892SBill Paul  *
7796f2e892SBill Paul  * The 100Mbps SYM port and 10baseT port can be used together in
7896f2e892SBill Paul  * combination with the internal NWAY support to create a 10/100
7996f2e892SBill Paul  * autosensing configuration.
8096f2e892SBill Paul  *
8196f2e892SBill Paul  * Note that not all tulip workalikes are handled in this driver: we only
8296f2e892SBill Paul  * deal with those which are relatively well behaved. The Winbond is
8396f2e892SBill Paul  * handled separately due to its different register offsets and the
8496f2e892SBill Paul  * special handling needed for its various bugs. The PNIC is handled
8596f2e892SBill Paul  * here, but I'm not thrilled about it.
8696f2e892SBill Paul  *
8796f2e892SBill Paul  * All of the workalike chips use some form of MII transceiver support
8896f2e892SBill Paul  * with the exception of the Macronix chips, which also have a SYM port.
8996f2e892SBill Paul  * The ASIX AX88140A is also documented to have a SYM port, but all
9096f2e892SBill Paul  * the cards I've seen use an MII transceiver, probably because the
9196f2e892SBill Paul  * AX88140A doesn't support internal NWAY.
9296f2e892SBill Paul  */
9396f2e892SBill Paul 
94f0796cd2SGleb Smirnoff #ifdef HAVE_KERNEL_OPTION_HEADERS
95f0796cd2SGleb Smirnoff #include "opt_device_polling.h"
96f0796cd2SGleb Smirnoff #endif
97f0796cd2SGleb Smirnoff 
9896f2e892SBill Paul #include <sys/param.h>
99af4358c7SMaxime Henrion #include <sys/endian.h>
10096f2e892SBill Paul #include <sys/systm.h>
10196f2e892SBill Paul #include <sys/sockio.h>
10296f2e892SBill Paul #include <sys/mbuf.h>
10396f2e892SBill Paul #include <sys/malloc.h>
10496f2e892SBill Paul #include <sys/kernel.h>
105f11d01c3SPoul-Henning Kamp #include <sys/module.h>
10696f2e892SBill Paul #include <sys/socket.h>
10796f2e892SBill Paul 
10896f2e892SBill Paul #include <net/if.h>
10996f2e892SBill Paul #include <net/if_arp.h>
11096f2e892SBill Paul #include <net/ethernet.h>
11196f2e892SBill Paul #include <net/if_dl.h>
11296f2e892SBill Paul #include <net/if_media.h>
113db40c1aeSDoug Ambrisko #include <net/if_types.h>
114db40c1aeSDoug Ambrisko #include <net/if_vlan_var.h>
11596f2e892SBill Paul 
11696f2e892SBill Paul #include <net/bpf.h>
11796f2e892SBill Paul 
11896f2e892SBill Paul #include <machine/bus.h>
11996f2e892SBill Paul #include <machine/resource.h>
12096f2e892SBill Paul #include <sys/bus.h>
12196f2e892SBill Paul #include <sys/rman.h>
12296f2e892SBill Paul 
12396f2e892SBill Paul #include <dev/mii/mii.h>
12496f2e892SBill Paul #include <dev/mii/miivar.h>
12596f2e892SBill Paul 
12619b7ffd1SWarner Losh #include <dev/pci/pcireg.h>
12719b7ffd1SWarner Losh #include <dev/pci/pcivar.h>
12896f2e892SBill Paul 
12996f2e892SBill Paul #define DC_USEIOSPACE
13096f2e892SBill Paul 
1316a3033a8SWarner Losh #include <dev/dc/if_dcreg.h>
13296f2e892SBill Paul 
133ec6a7299SMaxime Henrion #ifdef __sparc64__
134ec6a7299SMaxime Henrion #include <dev/ofw/openfirm.h>
135ec6a7299SMaxime Henrion #include <machine/ofw_machdep.h>
136ec6a7299SMaxime Henrion #endif
137ec6a7299SMaxime Henrion 
138f246e4a1SMatthew N. Dodd MODULE_DEPEND(dc, pci, 1, 1, 1);
139f246e4a1SMatthew N. Dodd MODULE_DEPEND(dc, ether, 1, 1, 1);
14095a16455SPeter Wemm MODULE_DEPEND(dc, miibus, 1, 1, 1);
14195a16455SPeter Wemm 
142919ccba7SWarner Losh /*
143919ccba7SWarner Losh  * "device miibus" is required in kernel config.  See GENERIC if you get
144919ccba7SWarner Losh  * errors here.
145919ccba7SWarner Losh  */
14696f2e892SBill Paul #include "miibus_if.h"
14796f2e892SBill Paul 
14896f2e892SBill Paul /*
14996f2e892SBill Paul  * Various supported device vendors/types and their names.
15096f2e892SBill Paul  */
151ebc284ccSMarius Strobl static const struct dc_type dc_devs[] = {
1521e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143), 0,
15396f2e892SBill Paul 		"Intel 21143 10/100BaseTX" },
1541e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009), 0,
15538deb45fSTom Rhodes 		"Davicom DM9009 10/100BaseTX" },
1561e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100), 0,
15796f2e892SBill Paul 		"Davicom DM9100 10/100BaseTX" },
1581e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), DC_REVISION_DM9102A,
15988d739dcSBill Paul 		"Davicom DM9102A 10/100BaseTX" },
1601e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), 0,
1611e2e70b1SJohn Baldwin 		"Davicom DM9102 10/100BaseTX" },
1621e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981), 0,
16396f2e892SBill Paul 		"ADMtek AL981 10/100BaseTX" },
1641e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985), 0,
16596f2e892SBill Paul 		"ADMtek AN985 10/100BaseTX" },
1661e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511), 0,
167e351d778SMartin Blapp 		"ADMtek ADM9511 10/100BaseTX" },
1681e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513), 0,
169e351d778SMartin Blapp 		"ADMtek ADM9513 10/100BaseTX" },
1701e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_FA511), 0,
1714c16d09eSWarner Losh 		"Netgear FA511 10/100BaseTX" },
1721e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), DC_REVISION_88141,
17396f2e892SBill Paul 		"ASIX AX88141 10/100BaseTX" },
1741e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), 0,
1751e2e70b1SJohn Baldwin 		"ASIX AX88140A 10/100BaseTX" },
1761e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), DC_REVISION_98713A,
17796f2e892SBill Paul 		"Macronix 98713A 10/100BaseTX" },
1781e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), 0,
1791e2e70b1SJohn Baldwin 		"Macronix 98713 10/100BaseTX" },
1801e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), DC_REVISION_98713A,
18196f2e892SBill Paul 		"Compex RL100-TX 10/100BaseTX" },
1821e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), 0,
18396f2e892SBill Paul 		"Compex RL100-TX 10/100BaseTX" },
1841e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98725,
18596f2e892SBill Paul 		"Macronix 98725 10/100BaseTX" },
1861e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98715AEC_C,
1871e2e70b1SJohn Baldwin 		"Macronix 98715AEC-C 10/100BaseTX" },
1881e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), 0,
1891e2e70b1SJohn Baldwin 		"Macronix 98715/98715A 10/100BaseTX" },
1901e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727), 0,
191ead7cde9SBill Paul 		"Macronix 98727/98732 10/100BaseTX" },
1921e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115), 0,
19396f2e892SBill Paul 		"LC82C115 PNIC II 10/100BaseTX" },
1941e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), DC_REVISION_82C169,
19596f2e892SBill Paul 		"82c169 PNIC 10/100BaseTX" },
1961e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), 0,
1971e2e70b1SJohn Baldwin 		"82c168 PNIC 10/100BaseTX" },
1981e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217), 0,
1999ca710f6SJeroen Ruigrok van der Werven 		"Accton EN1217 10/100BaseTX" },
2001e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242), 0,
201fa167b8eSBill Paul 		"Accton EN2242 MiniPCI 10/100BaseTX" },
2021e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201), 0,
203feb78939SJonathan Chen 		"Xircom X3201 10/100BaseTX" },
2041e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD), 0,
2059be0993cSJohn Baldwin 		"Neteasy DRP-32TXD Cardbus 10/100" },
2061e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500), 0,
2071d5e5310SBill Paul 		"Abocom FE2500 10/100BaseTX" },
2081e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX), 0,
209773c505fSMIHIRA Sanpei Yoshiro 		"Abocom FE2500MX 10/100BaseTX" },
2101e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112), 0,
2111af8bec7SBill Paul 		"Conexant LANfinity MiniPCI 10/100BaseTX" },
2121e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX), 0,
213948c244dSWarner Losh 		"Hawking CB102 CardBus 10/100" },
2141e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T), 0,
21597f91728SMIHIRA Sanpei Yoshiro 		"PlaneX FNW-3602-T CardBus 10/100" },
2161e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB), 0,
2177eac366bSMartin Blapp 		"3Com OfficeConnect 10/100B" },
2181e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120), 0,
219e7b9ab3aSBill Paul 		"Microsoft MN-120 CardBus 10/100" },
2201e2e70b1SJohn Baldwin 	{ DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130), 0,
221e7b9ab3aSBill Paul 		"Microsoft MN-130 10/100" },
22217762569SGleb Smirnoff 	{ DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08), 0,
22317762569SGleb Smirnoff 		"Linksys PCMPC200 CardBus 10/100" },
22417762569SGleb Smirnoff 	{ DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09), 0,
22517762569SGleb Smirnoff 		"Linksys PCMPC200 CardBus 10/100" },
22696f2e892SBill Paul 	{ 0, 0, NULL }
22796f2e892SBill Paul };
22896f2e892SBill Paul 
229e51a25f8SAlfred Perlstein static int dc_probe(device_t);
230e51a25f8SAlfred Perlstein static int dc_attach(device_t);
231e51a25f8SAlfred Perlstein static int dc_detach(device_t);
232e8388e14SMitsuru IWASAKI static int dc_suspend(device_t);
233e8388e14SMitsuru IWASAKI static int dc_resume(device_t);
234ebc284ccSMarius Strobl static const struct dc_type *dc_devtype(device_t);
23556e5e7aeSMaxime Henrion static int dc_newbuf(struct dc_softc *, int, int);
236a10c0e45SMike Silbersack static int dc_encap(struct dc_softc *, struct mbuf **);
237e51a25f8SAlfred Perlstein static void dc_pnic_rx_bug_war(struct dc_softc *, int);
238e51a25f8SAlfred Perlstein static int dc_rx_resync(struct dc_softc *);
239e51a25f8SAlfred Perlstein static void dc_rxeof(struct dc_softc *);
240e51a25f8SAlfred Perlstein static void dc_txeof(struct dc_softc *);
241e51a25f8SAlfred Perlstein static void dc_tick(void *);
242e51a25f8SAlfred Perlstein static void dc_tx_underrun(struct dc_softc *);
243e51a25f8SAlfred Perlstein static void dc_intr(void *);
244e51a25f8SAlfred Perlstein static void dc_start(struct ifnet *);
245c8b27acaSJohn Baldwin static void dc_start_locked(struct ifnet *);
246e51a25f8SAlfred Perlstein static int dc_ioctl(struct ifnet *, u_long, caddr_t);
247e51a25f8SAlfred Perlstein static void dc_init(void *);
248c8b27acaSJohn Baldwin static void dc_init_locked(struct dc_softc *);
249e51a25f8SAlfred Perlstein static void dc_stop(struct dc_softc *);
250b1d16143SMarius Strobl static void dc_watchdog(void *);
2516a087a87SPyun YongHyeon static int dc_shutdown(device_t);
252e51a25f8SAlfred Perlstein static int dc_ifmedia_upd(struct ifnet *);
253e51a25f8SAlfred Perlstein static void dc_ifmedia_sts(struct ifnet *, struct ifmediareq *);
25496f2e892SBill Paul 
255e51a25f8SAlfred Perlstein static void dc_delay(struct dc_softc *);
256e51a25f8SAlfred Perlstein static void dc_eeprom_idle(struct dc_softc *);
257e51a25f8SAlfred Perlstein static void dc_eeprom_putbyte(struct dc_softc *, int);
258e51a25f8SAlfred Perlstein static void dc_eeprom_getword(struct dc_softc *, int, u_int16_t *);
259d24ae19dSWarner Losh static void dc_eeprom_getword_pnic(struct dc_softc *, int, u_int16_t *);
260d24ae19dSWarner Losh static void dc_eeprom_getword_xircom(struct dc_softc *, int, u_int16_t *);
2613097aa70SWarner Losh static void dc_eeprom_width(struct dc_softc *);
262e51a25f8SAlfred Perlstein static void dc_read_eeprom(struct dc_softc *, caddr_t, int, int, int);
26396f2e892SBill Paul 
264e51a25f8SAlfred Perlstein static void dc_mii_writebit(struct dc_softc *, int);
265e51a25f8SAlfred Perlstein static int dc_mii_readbit(struct dc_softc *);
266e51a25f8SAlfred Perlstein static void dc_mii_sync(struct dc_softc *);
267e51a25f8SAlfred Perlstein static void dc_mii_send(struct dc_softc *, u_int32_t, int);
268e51a25f8SAlfred Perlstein static int dc_mii_readreg(struct dc_softc *, struct dc_mii_frame *);
269e51a25f8SAlfred Perlstein static int dc_mii_writereg(struct dc_softc *, struct dc_mii_frame *);
270e51a25f8SAlfred Perlstein static int dc_miibus_readreg(device_t, int, int);
271e51a25f8SAlfred Perlstein static int dc_miibus_writereg(device_t, int, int, int);
272e51a25f8SAlfred Perlstein static void dc_miibus_statchg(device_t);
273e51a25f8SAlfred Perlstein static void dc_miibus_mediainit(device_t);
27496f2e892SBill Paul 
275e51a25f8SAlfred Perlstein static void dc_setcfg(struct dc_softc *, int);
2763373489bSWarner Losh static uint32_t dc_mchash_le(struct dc_softc *, const uint8_t *);
2773373489bSWarner Losh static uint32_t dc_mchash_be(const uint8_t *);
278e51a25f8SAlfred Perlstein static void dc_setfilt_21143(struct dc_softc *);
279e51a25f8SAlfred Perlstein static void dc_setfilt_asix(struct dc_softc *);
280e51a25f8SAlfred Perlstein static void dc_setfilt_admtek(struct dc_softc *);
281e51a25f8SAlfred Perlstein static void dc_setfilt_xircom(struct dc_softc *);
28296f2e892SBill Paul 
283e51a25f8SAlfred Perlstein static void dc_setfilt(struct dc_softc *);
28496f2e892SBill Paul 
285e51a25f8SAlfred Perlstein static void dc_reset(struct dc_softc *);
286e51a25f8SAlfred Perlstein static int dc_list_rx_init(struct dc_softc *);
287e51a25f8SAlfred Perlstein static int dc_list_tx_init(struct dc_softc *);
28896f2e892SBill Paul 
2893097aa70SWarner Losh static void dc_read_srom(struct dc_softc *, int);
290e51a25f8SAlfred Perlstein static void dc_parse_21143_srom(struct dc_softc *);
291e51a25f8SAlfred Perlstein static void dc_decode_leaf_sia(struct dc_softc *, struct dc_eblock_sia *);
292e51a25f8SAlfred Perlstein static void dc_decode_leaf_mii(struct dc_softc *, struct dc_eblock_mii *);
293e51a25f8SAlfred Perlstein static void dc_decode_leaf_sym(struct dc_softc *, struct dc_eblock_sym *);
294e51a25f8SAlfred Perlstein static void dc_apply_fixup(struct dc_softc *, int);
2955c1cfac4SBill Paul 
29696f2e892SBill Paul #ifdef DC_USEIOSPACE
29796f2e892SBill Paul #define DC_RES			SYS_RES_IOPORT
29896f2e892SBill Paul #define DC_RID			DC_PCI_CFBIO
29996f2e892SBill Paul #else
30096f2e892SBill Paul #define DC_RES			SYS_RES_MEMORY
30196f2e892SBill Paul #define DC_RID			DC_PCI_CFBMA
30296f2e892SBill Paul #endif
30396f2e892SBill Paul 
30496f2e892SBill Paul static device_method_t dc_methods[] = {
30596f2e892SBill Paul 	/* Device interface */
30696f2e892SBill Paul 	DEVMETHOD(device_probe,		dc_probe),
30796f2e892SBill Paul 	DEVMETHOD(device_attach,	dc_attach),
30896f2e892SBill Paul 	DEVMETHOD(device_detach,	dc_detach),
309e8388e14SMitsuru IWASAKI 	DEVMETHOD(device_suspend,	dc_suspend),
310e8388e14SMitsuru IWASAKI 	DEVMETHOD(device_resume,	dc_resume),
31196f2e892SBill Paul 	DEVMETHOD(device_shutdown,	dc_shutdown),
31296f2e892SBill Paul 
31396f2e892SBill Paul 	/* bus interface */
31496f2e892SBill Paul 	DEVMETHOD(bus_print_child,	bus_generic_print_child),
31596f2e892SBill Paul 	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
31696f2e892SBill Paul 
31796f2e892SBill Paul 	/* MII interface */
31896f2e892SBill Paul 	DEVMETHOD(miibus_readreg,	dc_miibus_readreg),
31996f2e892SBill Paul 	DEVMETHOD(miibus_writereg,	dc_miibus_writereg),
32096f2e892SBill Paul 	DEVMETHOD(miibus_statchg,	dc_miibus_statchg),
321f43d9309SBill Paul 	DEVMETHOD(miibus_mediainit,	dc_miibus_mediainit),
32296f2e892SBill Paul 
32396f2e892SBill Paul 	{ 0, 0 }
32496f2e892SBill Paul };
32596f2e892SBill Paul 
32696f2e892SBill Paul static driver_t dc_driver = {
32796f2e892SBill Paul 	"dc",
32896f2e892SBill Paul 	dc_methods,
32996f2e892SBill Paul 	sizeof(struct dc_softc)
33096f2e892SBill Paul };
33196f2e892SBill Paul 
33296f2e892SBill Paul static devclass_t dc_devclass;
33396f2e892SBill Paul 
334347934faSWarner Losh DRIVER_MODULE(dc, cardbus, dc_driver, dc_devclass, 0, 0);
335f246e4a1SMatthew N. Dodd DRIVER_MODULE(dc, pci, dc_driver, dc_devclass, 0, 0);
33696f2e892SBill Paul DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0);
33796f2e892SBill Paul 
33896f2e892SBill Paul #define DC_SETBIT(sc, reg, x)				\
33996f2e892SBill Paul 	CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
34096f2e892SBill Paul 
34196f2e892SBill Paul #define DC_CLRBIT(sc, reg, x)				\
34296f2e892SBill Paul 	CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
34396f2e892SBill Paul 
34496f2e892SBill Paul #define SIO_SET(x)	DC_SETBIT(sc, DC_SIO, (x))
34596f2e892SBill Paul #define SIO_CLR(x)	DC_CLRBIT(sc, DC_SIO, (x))
34696f2e892SBill Paul 
347e3d2833aSAlfred Perlstein static void
3480934f18aSMaxime Henrion dc_delay(struct dc_softc *sc)
34996f2e892SBill Paul {
35096f2e892SBill Paul 	int idx;
35196f2e892SBill Paul 
35296f2e892SBill Paul 	for (idx = (300 / 33) + 1; idx > 0; idx--)
35396f2e892SBill Paul 		CSR_READ_4(sc, DC_BUSCTL);
35496f2e892SBill Paul }
35596f2e892SBill Paul 
3562c876e15SPoul-Henning Kamp static void
3570934f18aSMaxime Henrion dc_eeprom_width(struct dc_softc *sc)
3583097aa70SWarner Losh {
3593097aa70SWarner Losh 	int i;
3603097aa70SWarner Losh 
3613097aa70SWarner Losh 	/* Force EEPROM to idle state. */
3623097aa70SWarner Losh 	dc_eeprom_idle(sc);
3633097aa70SWarner Losh 
3643097aa70SWarner Losh 	/* Enter EEPROM access mode. */
3653097aa70SWarner Losh 	CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
3663097aa70SWarner Losh 	dc_delay(sc);
3673097aa70SWarner Losh 	DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
3683097aa70SWarner Losh 	dc_delay(sc);
3693097aa70SWarner Losh 	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
3703097aa70SWarner Losh 	dc_delay(sc);
3713097aa70SWarner Losh 	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
3723097aa70SWarner Losh 	dc_delay(sc);
3733097aa70SWarner Losh 
3743097aa70SWarner Losh 	for (i = 3; i--;) {
3753097aa70SWarner Losh 		if (6 & (1 << i))
3763097aa70SWarner Losh 			DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
3773097aa70SWarner Losh 		else
3783097aa70SWarner Losh 			DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
3793097aa70SWarner Losh 		dc_delay(sc);
3803097aa70SWarner Losh 		DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
3813097aa70SWarner Losh 		dc_delay(sc);
3823097aa70SWarner Losh 		DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
3833097aa70SWarner Losh 		dc_delay(sc);
3843097aa70SWarner Losh 	}
3853097aa70SWarner Losh 
3863097aa70SWarner Losh 	for (i = 1; i <= 12; i++) {
3873097aa70SWarner Losh 		DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
3883097aa70SWarner Losh 		dc_delay(sc);
3893097aa70SWarner Losh 		if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) {
3903097aa70SWarner Losh 			DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
3913097aa70SWarner Losh 			dc_delay(sc);
3923097aa70SWarner Losh 			break;
3933097aa70SWarner Losh 		}
3943097aa70SWarner Losh 		DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
3953097aa70SWarner Losh 		dc_delay(sc);
3963097aa70SWarner Losh 	}
3973097aa70SWarner Losh 
3983097aa70SWarner Losh 	/* Turn off EEPROM access mode. */
3993097aa70SWarner Losh 	dc_eeprom_idle(sc);
4003097aa70SWarner Losh 
4013097aa70SWarner Losh 	if (i < 4 || i > 12)
4023097aa70SWarner Losh 		sc->dc_romwidth = 6;
4033097aa70SWarner Losh 	else
4043097aa70SWarner Losh 		sc->dc_romwidth = i;
4053097aa70SWarner Losh 
4063097aa70SWarner Losh 	/* Enter EEPROM access mode. */
4073097aa70SWarner Losh 	CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
4083097aa70SWarner Losh 	dc_delay(sc);
4093097aa70SWarner Losh 	DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
4103097aa70SWarner Losh 	dc_delay(sc);
4113097aa70SWarner Losh 	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
4123097aa70SWarner Losh 	dc_delay(sc);
4133097aa70SWarner Losh 	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
4143097aa70SWarner Losh 	dc_delay(sc);
4153097aa70SWarner Losh 
4163097aa70SWarner Losh 	/* Turn off EEPROM access mode. */
4173097aa70SWarner Losh 	dc_eeprom_idle(sc);
4183097aa70SWarner Losh }
4193097aa70SWarner Losh 
420e3d2833aSAlfred Perlstein static void
4210934f18aSMaxime Henrion dc_eeprom_idle(struct dc_softc *sc)
42296f2e892SBill Paul {
4230934f18aSMaxime Henrion 	int i;
42496f2e892SBill Paul 
42596f2e892SBill Paul 	CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
42696f2e892SBill Paul 	dc_delay(sc);
42796f2e892SBill Paul 	DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
42896f2e892SBill Paul 	dc_delay(sc);
42996f2e892SBill Paul 	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
43096f2e892SBill Paul 	dc_delay(sc);
43196f2e892SBill Paul 	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
43296f2e892SBill Paul 	dc_delay(sc);
43396f2e892SBill Paul 
43496f2e892SBill Paul 	for (i = 0; i < 25; i++) {
43596f2e892SBill Paul 		DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
43696f2e892SBill Paul 		dc_delay(sc);
43796f2e892SBill Paul 		DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
43896f2e892SBill Paul 		dc_delay(sc);
43996f2e892SBill Paul 	}
44096f2e892SBill Paul 
44196f2e892SBill Paul 	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
44296f2e892SBill Paul 	dc_delay(sc);
44396f2e892SBill Paul 	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS);
44496f2e892SBill Paul 	dc_delay(sc);
44596f2e892SBill Paul 	CSR_WRITE_4(sc, DC_SIO, 0x00000000);
44696f2e892SBill Paul }
44796f2e892SBill Paul 
44896f2e892SBill Paul /*
44996f2e892SBill Paul  * Send a read command and address to the EEPROM, check for ACK.
45096f2e892SBill Paul  */
451e3d2833aSAlfred Perlstein static void
4520934f18aSMaxime Henrion dc_eeprom_putbyte(struct dc_softc *sc, int addr)
45396f2e892SBill Paul {
4540934f18aSMaxime Henrion 	int d, i;
45596f2e892SBill Paul 
4563097aa70SWarner Losh 	d = DC_EECMD_READ >> 6;
4573097aa70SWarner Losh 	for (i = 3; i--; ) {
4583097aa70SWarner Losh 		if (d & (1 << i))
4593097aa70SWarner Losh 			DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
46096f2e892SBill Paul 		else
4613097aa70SWarner Losh 			DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
4623097aa70SWarner Losh 		dc_delay(sc);
4633097aa70SWarner Losh 		DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
4643097aa70SWarner Losh 		dc_delay(sc);
4653097aa70SWarner Losh 		DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
4663097aa70SWarner Losh 		dc_delay(sc);
4673097aa70SWarner Losh 	}
46896f2e892SBill Paul 
46996f2e892SBill Paul 	/*
47096f2e892SBill Paul 	 * Feed in each bit and strobe the clock.
47196f2e892SBill Paul 	 */
4723097aa70SWarner Losh 	for (i = sc->dc_romwidth; i--;) {
4733097aa70SWarner Losh 		if (addr & (1 << i)) {
47496f2e892SBill Paul 			SIO_SET(DC_SIO_EE_DATAIN);
47596f2e892SBill Paul 		} else {
47696f2e892SBill Paul 			SIO_CLR(DC_SIO_EE_DATAIN);
47796f2e892SBill Paul 		}
47896f2e892SBill Paul 		dc_delay(sc);
47996f2e892SBill Paul 		SIO_SET(DC_SIO_EE_CLK);
48096f2e892SBill Paul 		dc_delay(sc);
48196f2e892SBill Paul 		SIO_CLR(DC_SIO_EE_CLK);
48296f2e892SBill Paul 		dc_delay(sc);
48396f2e892SBill Paul 	}
48496f2e892SBill Paul }
48596f2e892SBill Paul 
48696f2e892SBill Paul /*
48796f2e892SBill Paul  * Read a word of data stored in the EEPROM at address 'addr.'
48896f2e892SBill Paul  * The PNIC 82c168/82c169 has its own non-standard way to read
48996f2e892SBill Paul  * the EEPROM.
49096f2e892SBill Paul  */
491e3d2833aSAlfred Perlstein static void
4920934f18aSMaxime Henrion dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, u_int16_t *dest)
49396f2e892SBill Paul {
4940934f18aSMaxime Henrion 	int i;
49596f2e892SBill Paul 	u_int32_t r;
49696f2e892SBill Paul 
49796f2e892SBill Paul 	CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr);
49896f2e892SBill Paul 
49996f2e892SBill Paul 	for (i = 0; i < DC_TIMEOUT; i++) {
50096f2e892SBill Paul 		DELAY(1);
50196f2e892SBill Paul 		r = CSR_READ_4(sc, DC_SIO);
50296f2e892SBill Paul 		if (!(r & DC_PN_SIOCTL_BUSY)) {
50396f2e892SBill Paul 			*dest = (u_int16_t)(r & 0xFFFF);
50496f2e892SBill Paul 			return;
50596f2e892SBill Paul 		}
50696f2e892SBill Paul 	}
50796f2e892SBill Paul }
50896f2e892SBill Paul 
50996f2e892SBill Paul /*
51096f2e892SBill Paul  * Read a word of data stored in the EEPROM at address 'addr.'
511feb78939SJonathan Chen  * The Xircom X3201 has its own non-standard way to read
512feb78939SJonathan Chen  * the EEPROM, too.
513feb78939SJonathan Chen  */
514e3d2833aSAlfred Perlstein static void
5150934f18aSMaxime Henrion dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, u_int16_t *dest)
516feb78939SJonathan Chen {
5170934f18aSMaxime Henrion 
518feb78939SJonathan Chen 	SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ);
519feb78939SJonathan Chen 
520feb78939SJonathan Chen 	addr *= 2;
521feb78939SJonathan Chen 	CSR_WRITE_4(sc, DC_ROM, addr | 0x160);
522feb78939SJonathan Chen 	*dest = (u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff;
523feb78939SJonathan Chen 	addr += 1;
524feb78939SJonathan Chen 	CSR_WRITE_4(sc, DC_ROM, addr | 0x160);
525feb78939SJonathan Chen 	*dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8;
526feb78939SJonathan Chen 
527feb78939SJonathan Chen 	SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ);
528feb78939SJonathan Chen }
529feb78939SJonathan Chen 
530feb78939SJonathan Chen /*
531feb78939SJonathan Chen  * Read a word of data stored in the EEPROM at address 'addr.'
53296f2e892SBill Paul  */
533e3d2833aSAlfred Perlstein static void
5340934f18aSMaxime Henrion dc_eeprom_getword(struct dc_softc *sc, int addr, u_int16_t *dest)
53596f2e892SBill Paul {
5360934f18aSMaxime Henrion 	int i;
53796f2e892SBill Paul 	u_int16_t word = 0;
53896f2e892SBill Paul 
53996f2e892SBill Paul 	/* Force EEPROM to idle state. */
54096f2e892SBill Paul 	dc_eeprom_idle(sc);
54196f2e892SBill Paul 
54296f2e892SBill Paul 	/* Enter EEPROM access mode. */
54396f2e892SBill Paul 	CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
54496f2e892SBill Paul 	dc_delay(sc);
54596f2e892SBill Paul 	DC_SETBIT(sc, DC_SIO,  DC_SIO_ROMCTL_READ);
54696f2e892SBill Paul 	dc_delay(sc);
54796f2e892SBill Paul 	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
54896f2e892SBill Paul 	dc_delay(sc);
54996f2e892SBill Paul 	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
55096f2e892SBill Paul 	dc_delay(sc);
55196f2e892SBill Paul 
55296f2e892SBill Paul 	/*
55396f2e892SBill Paul 	 * Send address of word we want to read.
55496f2e892SBill Paul 	 */
55596f2e892SBill Paul 	dc_eeprom_putbyte(sc, addr);
55696f2e892SBill Paul 
55796f2e892SBill Paul 	/*
55896f2e892SBill Paul 	 * Start reading bits from EEPROM.
55996f2e892SBill Paul 	 */
56096f2e892SBill Paul 	for (i = 0x8000; i; i >>= 1) {
56196f2e892SBill Paul 		SIO_SET(DC_SIO_EE_CLK);
56296f2e892SBill Paul 		dc_delay(sc);
56396f2e892SBill Paul 		if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)
56496f2e892SBill Paul 			word |= i;
56596f2e892SBill Paul 		dc_delay(sc);
56696f2e892SBill Paul 		SIO_CLR(DC_SIO_EE_CLK);
56796f2e892SBill Paul 		dc_delay(sc);
56896f2e892SBill Paul 	}
56996f2e892SBill Paul 
57096f2e892SBill Paul 	/* Turn off EEPROM access mode. */
57196f2e892SBill Paul 	dc_eeprom_idle(sc);
57296f2e892SBill Paul 
57396f2e892SBill Paul 	*dest = word;
57496f2e892SBill Paul }
57596f2e892SBill Paul 
57696f2e892SBill Paul /*
57796f2e892SBill Paul  * Read a sequence of words from the EEPROM.
57896f2e892SBill Paul  */
579e3d2833aSAlfred Perlstein static void
5808c7ff1f3SMaxime Henrion dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int be)
58196f2e892SBill Paul {
58296f2e892SBill Paul 	int i;
58396f2e892SBill Paul 	u_int16_t word = 0, *ptr;
58496f2e892SBill Paul 
58596f2e892SBill Paul 	for (i = 0; i < cnt; i++) {
58696f2e892SBill Paul 		if (DC_IS_PNIC(sc))
58796f2e892SBill Paul 			dc_eeprom_getword_pnic(sc, off + i, &word);
588feb78939SJonathan Chen 		else if (DC_IS_XIRCOM(sc))
589feb78939SJonathan Chen 			dc_eeprom_getword_xircom(sc, off + i, &word);
59096f2e892SBill Paul 		else
59196f2e892SBill Paul 			dc_eeprom_getword(sc, off + i, &word);
59296f2e892SBill Paul 		ptr = (u_int16_t *)(dest + (i * 2));
5938c7ff1f3SMaxime Henrion 		if (be)
5948c7ff1f3SMaxime Henrion 			*ptr = be16toh(word);
59596f2e892SBill Paul 		else
5968c7ff1f3SMaxime Henrion 			*ptr = le16toh(word);
59796f2e892SBill Paul 	}
59896f2e892SBill Paul }
59996f2e892SBill Paul 
60096f2e892SBill Paul /*
60196f2e892SBill Paul  * The following two routines are taken from the Macronix 98713
60296f2e892SBill Paul  * Application Notes pp.19-21.
60396f2e892SBill Paul  */
60496f2e892SBill Paul /*
60596f2e892SBill Paul  * Write a bit to the MII bus.
60696f2e892SBill Paul  */
607e3d2833aSAlfred Perlstein static void
6080934f18aSMaxime Henrion dc_mii_writebit(struct dc_softc *sc, int bit)
60996f2e892SBill Paul {
61015578119SMarius Strobl 	uint32_t reg;
6110934f18aSMaxime Henrion 
61215578119SMarius Strobl 	reg = DC_SIO_ROMCTL_WRITE | (bit != 0 ? DC_SIO_MII_DATAOUT : 0);
61315578119SMarius Strobl 	CSR_WRITE_4(sc, DC_SIO, reg);
61415578119SMarius Strobl 	CSR_BARRIER_4(sc, DC_SIO,
61515578119SMarius Strobl 	    BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
61615578119SMarius Strobl 	DELAY(1);
61796f2e892SBill Paul 
61815578119SMarius Strobl 	CSR_WRITE_4(sc, DC_SIO, reg | DC_SIO_MII_CLK);
61915578119SMarius Strobl 	CSR_BARRIER_4(sc, DC_SIO,
62015578119SMarius Strobl 	    BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
62115578119SMarius Strobl 	DELAY(1);
62215578119SMarius Strobl 	CSR_WRITE_4(sc, DC_SIO, reg);
62315578119SMarius Strobl 	CSR_BARRIER_4(sc, DC_SIO,
62415578119SMarius Strobl 	    BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
62515578119SMarius Strobl 	DELAY(1);
62696f2e892SBill Paul }
62796f2e892SBill Paul 
62896f2e892SBill Paul /*
62996f2e892SBill Paul  * Read a bit from the MII bus.
63096f2e892SBill Paul  */
631e3d2833aSAlfred Perlstein static int
6320934f18aSMaxime Henrion dc_mii_readbit(struct dc_softc *sc)
63396f2e892SBill Paul {
63415578119SMarius Strobl 	uint32_t reg;
6350934f18aSMaxime Henrion 
63615578119SMarius Strobl 	reg = DC_SIO_ROMCTL_READ | DC_SIO_MII_DIR;
63715578119SMarius Strobl 	CSR_WRITE_4(sc, DC_SIO, reg);
63815578119SMarius Strobl 	CSR_BARRIER_4(sc, DC_SIO,
63915578119SMarius Strobl 	    BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
64015578119SMarius Strobl 	DELAY(1);
64115578119SMarius Strobl 	(void)CSR_READ_4(sc, DC_SIO);
64215578119SMarius Strobl 	CSR_WRITE_4(sc, DC_SIO, reg | DC_SIO_MII_CLK);
64315578119SMarius Strobl 	CSR_BARRIER_4(sc, DC_SIO,
64415578119SMarius Strobl 	    BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
64515578119SMarius Strobl 	DELAY(1);
64615578119SMarius Strobl 	CSR_WRITE_4(sc, DC_SIO, reg);
64715578119SMarius Strobl 	CSR_BARRIER_4(sc, DC_SIO,
64815578119SMarius Strobl 	    BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
64915578119SMarius Strobl 	DELAY(1);
65096f2e892SBill Paul 	if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN)
65196f2e892SBill Paul 		return (1);
65296f2e892SBill Paul 
65396f2e892SBill Paul 	return (0);
65496f2e892SBill Paul }
65596f2e892SBill Paul 
65696f2e892SBill Paul /*
65796f2e892SBill Paul  * Sync the PHYs by setting data bit and strobing the clock 32 times.
65896f2e892SBill Paul  */
659e3d2833aSAlfred Perlstein static void
6600934f18aSMaxime Henrion dc_mii_sync(struct dc_softc *sc)
66196f2e892SBill Paul {
6620934f18aSMaxime Henrion 	int i;
66396f2e892SBill Paul 
66496f2e892SBill Paul 	CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE);
66515578119SMarius Strobl 	CSR_BARRIER_4(sc, DC_SIO,
66615578119SMarius Strobl 	    BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
66715578119SMarius Strobl 	DELAY(1);
66896f2e892SBill Paul 
66996f2e892SBill Paul 	for (i = 0; i < 32; i++)
67096f2e892SBill Paul 		dc_mii_writebit(sc, 1);
67196f2e892SBill Paul }
67296f2e892SBill Paul 
67396f2e892SBill Paul /*
67496f2e892SBill Paul  * Clock a series of bits through the MII.
67596f2e892SBill Paul  */
676e3d2833aSAlfred Perlstein static void
6770934f18aSMaxime Henrion dc_mii_send(struct dc_softc *sc, u_int32_t bits, int cnt)
67896f2e892SBill Paul {
67996f2e892SBill Paul 	int i;
68096f2e892SBill Paul 
68196f2e892SBill Paul 	for (i = (0x1 << (cnt - 1)); i; i >>= 1)
68296f2e892SBill Paul 		dc_mii_writebit(sc, bits & i);
68396f2e892SBill Paul }
68496f2e892SBill Paul 
68596f2e892SBill Paul /*
68696f2e892SBill Paul  * Read an PHY register through the MII.
68796f2e892SBill Paul  */
688e3d2833aSAlfred Perlstein static int
6890934f18aSMaxime Henrion dc_mii_readreg(struct dc_softc *sc, struct dc_mii_frame *frame)
69096f2e892SBill Paul {
69115578119SMarius Strobl 	int i;
69296f2e892SBill Paul 
69396f2e892SBill Paul 	/*
69496f2e892SBill Paul 	 * Set up frame for RX.
69596f2e892SBill Paul 	 */
69696f2e892SBill Paul 	frame->mii_stdelim = DC_MII_STARTDELIM;
69796f2e892SBill Paul 	frame->mii_opcode = DC_MII_READOP;
69896f2e892SBill Paul 
69996f2e892SBill Paul 	/*
70096f2e892SBill Paul 	 * Sync the PHYs.
70196f2e892SBill Paul 	 */
70296f2e892SBill Paul 	dc_mii_sync(sc);
70396f2e892SBill Paul 
70496f2e892SBill Paul 	/*
70596f2e892SBill Paul 	 * Send command/address info.
70696f2e892SBill Paul 	 */
70796f2e892SBill Paul 	dc_mii_send(sc, frame->mii_stdelim, 2);
70896f2e892SBill Paul 	dc_mii_send(sc, frame->mii_opcode, 2);
70996f2e892SBill Paul 	dc_mii_send(sc, frame->mii_phyaddr, 5);
71096f2e892SBill Paul 	dc_mii_send(sc, frame->mii_regaddr, 5);
71196f2e892SBill Paul 
71296f2e892SBill Paul 	/*
71315578119SMarius Strobl 	 * Now try reading data bits.  If the turnaround failed, we still
71496f2e892SBill Paul 	 * need to clock through 16 cycles to keep the PHY(s) in sync.
71596f2e892SBill Paul 	 */
71615578119SMarius Strobl 	frame->mii_turnaround = dc_mii_readbit(sc);
71715578119SMarius Strobl 	if (frame->mii_turnaround != 0) {
7180934f18aSMaxime Henrion 		for (i = 0; i < 16; i++)
71996f2e892SBill Paul 			dc_mii_readbit(sc);
72096f2e892SBill Paul 		goto fail;
72196f2e892SBill Paul 	}
72296f2e892SBill Paul 	for (i = 0x8000; i; i >>= 1) {
72396f2e892SBill Paul 		if (dc_mii_readbit(sc))
72496f2e892SBill Paul 			frame->mii_data |= i;
72596f2e892SBill Paul 	}
72696f2e892SBill Paul 
72796f2e892SBill Paul fail:
72896f2e892SBill Paul 
72915578119SMarius Strobl 	/* Clock the idle bits. */
73096f2e892SBill Paul 	dc_mii_writebit(sc, 0);
73196f2e892SBill Paul 	dc_mii_writebit(sc, 0);
73296f2e892SBill Paul 
73315578119SMarius Strobl 	if (frame->mii_turnaround != 0)
73496f2e892SBill Paul 		return (1);
73596f2e892SBill Paul 	return (0);
73696f2e892SBill Paul }
73796f2e892SBill Paul 
73896f2e892SBill Paul /*
73996f2e892SBill Paul  * Write to a PHY register through the MII.
74096f2e892SBill Paul  */
741e3d2833aSAlfred Perlstein static int
7420934f18aSMaxime Henrion dc_mii_writereg(struct dc_softc *sc, struct dc_mii_frame *frame)
74396f2e892SBill Paul {
7440934f18aSMaxime Henrion 
74596f2e892SBill Paul 	/*
74696f2e892SBill Paul 	 * Set up frame for TX.
74796f2e892SBill Paul 	 */
74896f2e892SBill Paul 	frame->mii_stdelim = DC_MII_STARTDELIM;
74996f2e892SBill Paul 	frame->mii_opcode = DC_MII_WRITEOP;
75096f2e892SBill Paul 	frame->mii_turnaround = DC_MII_TURNAROUND;
75196f2e892SBill Paul 
75296f2e892SBill Paul 	/*
75396f2e892SBill Paul 	 * Sync the PHYs.
75496f2e892SBill Paul 	 */
75596f2e892SBill Paul 	dc_mii_sync(sc);
75696f2e892SBill Paul 
75796f2e892SBill Paul 	dc_mii_send(sc, frame->mii_stdelim, 2);
75896f2e892SBill Paul 	dc_mii_send(sc, frame->mii_opcode, 2);
75996f2e892SBill Paul 	dc_mii_send(sc, frame->mii_phyaddr, 5);
76096f2e892SBill Paul 	dc_mii_send(sc, frame->mii_regaddr, 5);
76196f2e892SBill Paul 	dc_mii_send(sc, frame->mii_turnaround, 2);
76296f2e892SBill Paul 	dc_mii_send(sc, frame->mii_data, 16);
76396f2e892SBill Paul 
76415578119SMarius Strobl 	/* Clock the idle bits. */
76596f2e892SBill Paul 	dc_mii_writebit(sc, 0);
76696f2e892SBill Paul 	dc_mii_writebit(sc, 0);
76796f2e892SBill Paul 
76896f2e892SBill Paul 	return (0);
76996f2e892SBill Paul }
77096f2e892SBill Paul 
771e3d2833aSAlfred Perlstein static int
7720934f18aSMaxime Henrion dc_miibus_readreg(device_t dev, int phy, int reg)
77396f2e892SBill Paul {
77496f2e892SBill Paul 	struct dc_mii_frame frame;
77596f2e892SBill Paul 	struct dc_softc	 *sc;
776c85c4667SBill Paul 	int i, rval, phy_reg = 0;
77796f2e892SBill Paul 
77896f2e892SBill Paul 	sc = device_get_softc(dev);
7790934f18aSMaxime Henrion 	bzero(&frame, sizeof(frame));
78096f2e892SBill Paul 
78196f2e892SBill Paul 	/*
78296f2e892SBill Paul 	 * Note: both the AL981 and AN985 have internal PHYs,
78396f2e892SBill Paul 	 * however the AL981 provides direct access to the PHY
78496f2e892SBill Paul 	 * registers while the AN985 uses a serial MII interface.
78596f2e892SBill Paul 	 * The AN985's MII interface is also buggy in that you
78696f2e892SBill Paul 	 * can read from any MII address (0 to 31), but only address 1
78796f2e892SBill Paul 	 * behaves normally. To deal with both cases, we pretend
78896f2e892SBill Paul 	 * that the PHY is at MII address 1.
78996f2e892SBill Paul 	 */
79096f2e892SBill Paul 	if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR)
79196f2e892SBill Paul 		return (0);
79296f2e892SBill Paul 
7931af8bec7SBill Paul 	/*
7941af8bec7SBill Paul 	 * Note: the ukphy probes of the RS7112 report a PHY at
7951af8bec7SBill Paul 	 * MII address 0 (possibly HomePNA?) and 1 (ethernet)
7961af8bec7SBill Paul 	 * so we only respond to correct one.
7971af8bec7SBill Paul 	 */
7981af8bec7SBill Paul 	if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR)
7991af8bec7SBill Paul 		return (0);
8001af8bec7SBill Paul 
8015c1cfac4SBill Paul 	if (sc->dc_pmode != DC_PMODE_MII) {
80296f2e892SBill Paul 		if (phy == (MII_NPHY - 1)) {
80396f2e892SBill Paul 			switch (reg) {
80496f2e892SBill Paul 			case MII_BMSR:
80596f2e892SBill Paul 			/*
80696f2e892SBill Paul 			 * Fake something to make the probe
80796f2e892SBill Paul 			 * code think there's a PHY here.
80896f2e892SBill Paul 			 */
80996f2e892SBill Paul 				return (BMSR_MEDIAMASK);
81096f2e892SBill Paul 				break;
81196f2e892SBill Paul 			case MII_PHYIDR1:
81296f2e892SBill Paul 				if (DC_IS_PNIC(sc))
81396f2e892SBill Paul 					return (DC_VENDORID_LO);
81496f2e892SBill Paul 				return (DC_VENDORID_DEC);
81596f2e892SBill Paul 				break;
81696f2e892SBill Paul 			case MII_PHYIDR2:
81796f2e892SBill Paul 				if (DC_IS_PNIC(sc))
81896f2e892SBill Paul 					return (DC_DEVICEID_82C168);
81996f2e892SBill Paul 				return (DC_DEVICEID_21143);
82096f2e892SBill Paul 				break;
82196f2e892SBill Paul 			default:
82296f2e892SBill Paul 				return (0);
82396f2e892SBill Paul 				break;
82496f2e892SBill Paul 			}
82596f2e892SBill Paul 		} else
82696f2e892SBill Paul 			return (0);
82796f2e892SBill Paul 	}
82896f2e892SBill Paul 
82996f2e892SBill Paul 	if (DC_IS_PNIC(sc)) {
83096f2e892SBill Paul 		CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ |
83196f2e892SBill Paul 		    (phy << 23) | (reg << 18));
83296f2e892SBill Paul 		for (i = 0; i < DC_TIMEOUT; i++) {
83396f2e892SBill Paul 			DELAY(1);
83496f2e892SBill Paul 			rval = CSR_READ_4(sc, DC_PN_MII);
83596f2e892SBill Paul 			if (!(rval & DC_PN_MII_BUSY)) {
83696f2e892SBill Paul 				rval &= 0xFFFF;
83796f2e892SBill Paul 				return (rval == 0xFFFF ? 0 : rval);
83896f2e892SBill Paul 			}
83996f2e892SBill Paul 		}
84096f2e892SBill Paul 		return (0);
84196f2e892SBill Paul 	}
84296f2e892SBill Paul 
84396f2e892SBill Paul 	if (DC_IS_COMET(sc)) {
84496f2e892SBill Paul 		switch (reg) {
84596f2e892SBill Paul 		case MII_BMCR:
84696f2e892SBill Paul 			phy_reg = DC_AL_BMCR;
84796f2e892SBill Paul 			break;
84896f2e892SBill Paul 		case MII_BMSR:
84996f2e892SBill Paul 			phy_reg = DC_AL_BMSR;
85096f2e892SBill Paul 			break;
85196f2e892SBill Paul 		case MII_PHYIDR1:
85296f2e892SBill Paul 			phy_reg = DC_AL_VENID;
85396f2e892SBill Paul 			break;
85496f2e892SBill Paul 		case MII_PHYIDR2:
85596f2e892SBill Paul 			phy_reg = DC_AL_DEVID;
85696f2e892SBill Paul 			break;
85796f2e892SBill Paul 		case MII_ANAR:
85896f2e892SBill Paul 			phy_reg = DC_AL_ANAR;
85996f2e892SBill Paul 			break;
86096f2e892SBill Paul 		case MII_ANLPAR:
86196f2e892SBill Paul 			phy_reg = DC_AL_LPAR;
86296f2e892SBill Paul 			break;
86396f2e892SBill Paul 		case MII_ANER:
86496f2e892SBill Paul 			phy_reg = DC_AL_ANER;
86596f2e892SBill Paul 			break;
86696f2e892SBill Paul 		default:
86722f6205dSJohn Baldwin 			device_printf(dev, "phy_read: bad phy register %x\n",
86822f6205dSJohn Baldwin 			    reg);
86996f2e892SBill Paul 			return (0);
87096f2e892SBill Paul 			break;
87196f2e892SBill Paul 		}
87296f2e892SBill Paul 
87396f2e892SBill Paul 		rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF;
87496f2e892SBill Paul 
87596f2e892SBill Paul 		if (rval == 0xFFFF)
87696f2e892SBill Paul 			return (0);
87796f2e892SBill Paul 		return (rval);
87896f2e892SBill Paul 	}
87996f2e892SBill Paul 
88096f2e892SBill Paul 	frame.mii_phyaddr = phy;
88196f2e892SBill Paul 	frame.mii_regaddr = reg;
882419146d9SBill Paul 	if (sc->dc_type == DC_TYPE_98713) {
883f43d9309SBill Paul 		phy_reg = CSR_READ_4(sc, DC_NETCFG);
884f43d9309SBill Paul 		CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
885419146d9SBill Paul 	}
88696f2e892SBill Paul 	dc_mii_readreg(sc, &frame);
887419146d9SBill Paul 	if (sc->dc_type == DC_TYPE_98713)
888f43d9309SBill Paul 		CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
88996f2e892SBill Paul 
89096f2e892SBill Paul 	return (frame.mii_data);
89196f2e892SBill Paul }
89296f2e892SBill Paul 
893e3d2833aSAlfred Perlstein static int
8940934f18aSMaxime Henrion dc_miibus_writereg(device_t dev, int phy, int reg, int data)
89596f2e892SBill Paul {
89696f2e892SBill Paul 	struct dc_softc *sc;
89796f2e892SBill Paul 	struct dc_mii_frame frame;
898c85c4667SBill Paul 	int i, phy_reg = 0;
89996f2e892SBill Paul 
90096f2e892SBill Paul 	sc = device_get_softc(dev);
9010934f18aSMaxime Henrion 	bzero(&frame, sizeof(frame));
90296f2e892SBill Paul 
90396f2e892SBill Paul 	if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR)
90496f2e892SBill Paul 		return (0);
90596f2e892SBill Paul 
9061af8bec7SBill Paul 	if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR)
9071af8bec7SBill Paul 		return (0);
9081af8bec7SBill Paul 
90996f2e892SBill Paul 	if (DC_IS_PNIC(sc)) {
91096f2e892SBill Paul 		CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE |
91196f2e892SBill Paul 		    (phy << 23) | (reg << 10) | data);
91296f2e892SBill Paul 		for (i = 0; i < DC_TIMEOUT; i++) {
91396f2e892SBill Paul 			if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY))
91496f2e892SBill Paul 				break;
91596f2e892SBill Paul 		}
91696f2e892SBill Paul 		return (0);
91796f2e892SBill Paul 	}
91896f2e892SBill Paul 
91996f2e892SBill Paul 	if (DC_IS_COMET(sc)) {
92096f2e892SBill Paul 		switch (reg) {
92196f2e892SBill Paul 		case MII_BMCR:
92296f2e892SBill Paul 			phy_reg = DC_AL_BMCR;
92396f2e892SBill Paul 			break;
92496f2e892SBill Paul 		case MII_BMSR:
92596f2e892SBill Paul 			phy_reg = DC_AL_BMSR;
92696f2e892SBill Paul 			break;
92796f2e892SBill Paul 		case MII_PHYIDR1:
92896f2e892SBill Paul 			phy_reg = DC_AL_VENID;
92996f2e892SBill Paul 			break;
93096f2e892SBill Paul 		case MII_PHYIDR2:
93196f2e892SBill Paul 			phy_reg = DC_AL_DEVID;
93296f2e892SBill Paul 			break;
93396f2e892SBill Paul 		case MII_ANAR:
93496f2e892SBill Paul 			phy_reg = DC_AL_ANAR;
93596f2e892SBill Paul 			break;
93696f2e892SBill Paul 		case MII_ANLPAR:
93796f2e892SBill Paul 			phy_reg = DC_AL_LPAR;
93896f2e892SBill Paul 			break;
93996f2e892SBill Paul 		case MII_ANER:
94096f2e892SBill Paul 			phy_reg = DC_AL_ANER;
94196f2e892SBill Paul 			break;
94296f2e892SBill Paul 		default:
94322f6205dSJohn Baldwin 			device_printf(dev, "phy_write: bad phy register %x\n",
94422f6205dSJohn Baldwin 			    reg);
94596f2e892SBill Paul 			return (0);
94696f2e892SBill Paul 			break;
94796f2e892SBill Paul 		}
94896f2e892SBill Paul 
94996f2e892SBill Paul 		CSR_WRITE_4(sc, phy_reg, data);
95096f2e892SBill Paul 		return (0);
95196f2e892SBill Paul 	}
95296f2e892SBill Paul 
95396f2e892SBill Paul 	frame.mii_phyaddr = phy;
95496f2e892SBill Paul 	frame.mii_regaddr = reg;
95596f2e892SBill Paul 	frame.mii_data = data;
95696f2e892SBill Paul 
957419146d9SBill Paul 	if (sc->dc_type == DC_TYPE_98713) {
958f43d9309SBill Paul 		phy_reg = CSR_READ_4(sc, DC_NETCFG);
959f43d9309SBill Paul 		CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
960419146d9SBill Paul 	}
96196f2e892SBill Paul 	dc_mii_writereg(sc, &frame);
962419146d9SBill Paul 	if (sc->dc_type == DC_TYPE_98713)
963f43d9309SBill Paul 		CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
96496f2e892SBill Paul 
96596f2e892SBill Paul 	return (0);
96696f2e892SBill Paul }
96796f2e892SBill Paul 
968e3d2833aSAlfred Perlstein static void
9690934f18aSMaxime Henrion dc_miibus_statchg(device_t dev)
97096f2e892SBill Paul {
97196f2e892SBill Paul 	struct dc_softc *sc;
97296f2e892SBill Paul 	struct mii_data *mii;
973f43d9309SBill Paul 	struct ifmedia *ifm;
97496f2e892SBill Paul 
97596f2e892SBill Paul 	sc = device_get_softc(dev);
97696f2e892SBill Paul 	if (DC_IS_ADMTEK(sc))
97796f2e892SBill Paul 		return;
9785c1cfac4SBill Paul 
97996f2e892SBill Paul 	mii = device_get_softc(sc->dc_miibus);
980f43d9309SBill Paul 	ifm = &mii->mii_media;
981f43d9309SBill Paul 	if (DC_IS_DAVICOM(sc) &&
98245521525SPoul-Henning Kamp 	    IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) {
983f43d9309SBill Paul 		dc_setcfg(sc, ifm->ifm_media);
984f43d9309SBill Paul 		sc->dc_if_media = ifm->ifm_media;
985f43d9309SBill Paul 	} else {
98696f2e892SBill Paul 		dc_setcfg(sc, mii->mii_media_active);
98796f2e892SBill Paul 		sc->dc_if_media = mii->mii_media_active;
988f43d9309SBill Paul 	}
989f43d9309SBill Paul }
990f43d9309SBill Paul 
991f43d9309SBill Paul /*
992f43d9309SBill Paul  * Special support for DM9102A cards with HomePNA PHYs. Note:
993f43d9309SBill Paul  * with the Davicom DM9102A/DM9801 eval board that I have, it seems
994f43d9309SBill Paul  * to be impossible to talk to the management interface of the DM9801
995f43d9309SBill Paul  * PHY (its MDIO pin is not connected to anything). Consequently,
996f43d9309SBill Paul  * the driver has to just 'know' about the additional mode and deal
997f43d9309SBill Paul  * with it itself. *sigh*
998f43d9309SBill Paul  */
999e3d2833aSAlfred Perlstein static void
10000934f18aSMaxime Henrion dc_miibus_mediainit(device_t dev)
1001f43d9309SBill Paul {
1002f43d9309SBill Paul 	struct dc_softc *sc;
1003f43d9309SBill Paul 	struct mii_data *mii;
1004f43d9309SBill Paul 	struct ifmedia *ifm;
1005f43d9309SBill Paul 	int rev;
1006f43d9309SBill Paul 
10071e2e70b1SJohn Baldwin 	rev = pci_get_revid(dev);
1008f43d9309SBill Paul 
1009f43d9309SBill Paul 	sc = device_get_softc(dev);
1010f43d9309SBill Paul 	mii = device_get_softc(sc->dc_miibus);
1011f43d9309SBill Paul 	ifm = &mii->mii_media;
1012f43d9309SBill Paul 
1013f43d9309SBill Paul 	if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A)
101445521525SPoul-Henning Kamp 		ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL);
101596f2e892SBill Paul }
101696f2e892SBill Paul 
101779d11e09SBill Paul #define DC_BITS_512	9
101879d11e09SBill Paul #define DC_BITS_128	7
101979d11e09SBill Paul #define DC_BITS_64	6
102096f2e892SBill Paul 
10213373489bSWarner Losh static uint32_t
10223373489bSWarner Losh dc_mchash_le(struct dc_softc *sc, const uint8_t *addr)
102396f2e892SBill Paul {
10243373489bSWarner Losh 	uint32_t crc;
102596f2e892SBill Paul 
102696f2e892SBill Paul 	/* Compute CRC for the address value. */
10270e939c0cSChristian Weisgerber 	crc = ether_crc32_le(addr, ETHER_ADDR_LEN);
102896f2e892SBill Paul 
102979d11e09SBill Paul 	/*
103079d11e09SBill Paul 	 * The hash table on the PNIC II and the MX98715AEC-C/D/E
103179d11e09SBill Paul 	 * chips is only 128 bits wide.
103279d11e09SBill Paul 	 */
103379d11e09SBill Paul 	if (sc->dc_flags & DC_128BIT_HASH)
103479d11e09SBill Paul 		return (crc & ((1 << DC_BITS_128) - 1));
103596f2e892SBill Paul 
103679d11e09SBill Paul 	/* The hash table on the MX98715BEC is only 64 bits wide. */
103779d11e09SBill Paul 	if (sc->dc_flags & DC_64BIT_HASH)
103879d11e09SBill Paul 		return (crc & ((1 << DC_BITS_64) - 1));
103979d11e09SBill Paul 
1040feb78939SJonathan Chen 	/* Xircom's hash filtering table is different (read: weird) */
1041feb78939SJonathan Chen 	/* Xircom uses the LEAST significant bits */
1042feb78939SJonathan Chen 	if (DC_IS_XIRCOM(sc)) {
1043feb78939SJonathan Chen 		if ((crc & 0x180) == 0x180)
10440934f18aSMaxime Henrion 			return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4));
1045feb78939SJonathan Chen 		else
10460934f18aSMaxime Henrion 			return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 +
10470934f18aSMaxime Henrion 			    (12 << 4));
1048feb78939SJonathan Chen 	}
1049feb78939SJonathan Chen 
105079d11e09SBill Paul 	return (crc & ((1 << DC_BITS_512) - 1));
105196f2e892SBill Paul }
105296f2e892SBill Paul 
105396f2e892SBill Paul /*
105496f2e892SBill Paul  * Calculate CRC of a multicast group address, return the lower 6 bits.
105596f2e892SBill Paul  */
10563373489bSWarner Losh static uint32_t
10573373489bSWarner Losh dc_mchash_be(const uint8_t *addr)
105896f2e892SBill Paul {
10590e939c0cSChristian Weisgerber 	uint32_t crc;
106096f2e892SBill Paul 
106196f2e892SBill Paul 	/* Compute CRC for the address value. */
10620e939c0cSChristian Weisgerber 	crc = ether_crc32_be(addr, ETHER_ADDR_LEN);
106396f2e892SBill Paul 
10640934f18aSMaxime Henrion 	/* Return the filter bit position. */
106596f2e892SBill Paul 	return ((crc >> 26) & 0x0000003F);
106696f2e892SBill Paul }
106796f2e892SBill Paul 
106896f2e892SBill Paul /*
106996f2e892SBill Paul  * 21143-style RX filter setup routine. Filter programming is done by
107096f2e892SBill Paul  * downloading a special setup frame into the TX engine. 21143, Macronix,
107196f2e892SBill Paul  * PNIC, PNIC II and Davicom chips are programmed this way.
107296f2e892SBill Paul  *
107396f2e892SBill Paul  * We always program the chip using 'hash perfect' mode, i.e. one perfect
107496f2e892SBill Paul  * address (our node address) and a 512-bit hash filter for multicast
107596f2e892SBill Paul  * frames. We also sneak the broadcast address into the hash filter since
107696f2e892SBill Paul  * we need that too.
107796f2e892SBill Paul  */
10782c876e15SPoul-Henning Kamp static void
10790934f18aSMaxime Henrion dc_setfilt_21143(struct dc_softc *sc)
108096f2e892SBill Paul {
10818df1ebe9SMarcel Moolenaar 	uint16_t eaddr[(ETHER_ADDR_LEN+1)/2];
108296f2e892SBill Paul 	struct dc_desc *sframe;
108396f2e892SBill Paul 	u_int32_t h, *sp;
108496f2e892SBill Paul 	struct ifmultiaddr *ifma;
108596f2e892SBill Paul 	struct ifnet *ifp;
108696f2e892SBill Paul 	int i;
108796f2e892SBill Paul 
1088fc74a9f9SBrooks Davis 	ifp = sc->dc_ifp;
108996f2e892SBill Paul 
109096f2e892SBill Paul 	i = sc->dc_cdata.dc_tx_prod;
109196f2e892SBill Paul 	DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT);
109296f2e892SBill Paul 	sc->dc_cdata.dc_tx_cnt++;
109396f2e892SBill Paul 	sframe = &sc->dc_ldata->dc_tx_list[i];
109456e5e7aeSMaxime Henrion 	sp = sc->dc_cdata.dc_sbuf;
10950934f18aSMaxime Henrion 	bzero(sp, DC_SFRAME_LEN);
109696f2e892SBill Paul 
1097af4358c7SMaxime Henrion 	sframe->dc_data = htole32(sc->dc_saddr);
1098af4358c7SMaxime Henrion 	sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP |
1099af4358c7SMaxime Henrion 	    DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT);
110096f2e892SBill Paul 
110156e5e7aeSMaxime Henrion 	sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf;
110296f2e892SBill Paul 
110396f2e892SBill Paul 	/* If we want promiscuous mode, set the allframes bit. */
110496f2e892SBill Paul 	if (ifp->if_flags & IFF_PROMISC)
110596f2e892SBill Paul 		DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
110696f2e892SBill Paul 	else
110796f2e892SBill Paul 		DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
110896f2e892SBill Paul 
110996f2e892SBill Paul 	if (ifp->if_flags & IFF_ALLMULTI)
111096f2e892SBill Paul 		DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
111196f2e892SBill Paul 	else
111296f2e892SBill Paul 		DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
111396f2e892SBill Paul 
111413b203d0SRobert Watson 	IF_ADDR_LOCK(ifp);
11156817526dSPoul-Henning Kamp 	TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
111696f2e892SBill Paul 		if (ifma->ifma_addr->sa_family != AF_LINK)
111796f2e892SBill Paul 			continue;
1118aa825502SDavid E. O'Brien 		h = dc_mchash_le(sc,
111996f2e892SBill Paul 		    LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1120af4358c7SMaxime Henrion 		sp[h >> 4] |= htole32(1 << (h & 0xF));
112196f2e892SBill Paul 	}
112213b203d0SRobert Watson 	IF_ADDR_UNLOCK(ifp);
112396f2e892SBill Paul 
112496f2e892SBill Paul 	if (ifp->if_flags & IFF_BROADCAST) {
1125aa825502SDavid E. O'Brien 		h = dc_mchash_le(sc, ifp->if_broadcastaddr);
1126af4358c7SMaxime Henrion 		sp[h >> 4] |= htole32(1 << (h & 0xF));
112796f2e892SBill Paul 	}
112896f2e892SBill Paul 
11298df1ebe9SMarcel Moolenaar 	/* Set our MAC address. */
11308df1ebe9SMarcel Moolenaar 	bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN);
11318df1ebe9SMarcel Moolenaar 	sp[39] = DC_SP_MAC(eaddr[0]);
11328df1ebe9SMarcel Moolenaar 	sp[40] = DC_SP_MAC(eaddr[1]);
11338df1ebe9SMarcel Moolenaar 	sp[41] = DC_SP_MAC(eaddr[2]);
113496f2e892SBill Paul 
1135af4358c7SMaxime Henrion 	sframe->dc_status = htole32(DC_TXSTAT_OWN);
113696f2e892SBill Paul 	CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
113796f2e892SBill Paul 
113896f2e892SBill Paul 	/*
113996f2e892SBill Paul 	 * The PNIC takes an exceedingly long time to process its
114096f2e892SBill Paul 	 * setup frame; wait 10ms after posting the setup frame
114196f2e892SBill Paul 	 * before proceeding, just so it has time to swallow its
114296f2e892SBill Paul 	 * medicine.
114396f2e892SBill Paul 	 */
114496f2e892SBill Paul 	DELAY(10000);
114596f2e892SBill Paul 
1146b1d16143SMarius Strobl 	sc->dc_wdog_timer = 5;
114796f2e892SBill Paul }
114896f2e892SBill Paul 
11492c876e15SPoul-Henning Kamp static void
11500934f18aSMaxime Henrion dc_setfilt_admtek(struct dc_softc *sc)
115196f2e892SBill Paul {
11522e3d4b79SPyun YongHyeon 	uint8_t eaddr[ETHER_ADDR_LEN];
115396f2e892SBill Paul 	struct ifnet *ifp;
11540934f18aSMaxime Henrion 	struct ifmultiaddr *ifma;
115596f2e892SBill Paul 	int h = 0;
115696f2e892SBill Paul 	u_int32_t hashes[2] = { 0, 0 };
115796f2e892SBill Paul 
1158fc74a9f9SBrooks Davis 	ifp = sc->dc_ifp;
115996f2e892SBill Paul 
11600934f18aSMaxime Henrion 	/* Init our MAC address. */
11618df1ebe9SMarcel Moolenaar 	bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN);
11622e3d4b79SPyun YongHyeon 	CSR_WRITE_4(sc, DC_AL_PAR0, eaddr[3] << 24 | eaddr[2] << 16 |
11632e3d4b79SPyun YongHyeon 	    eaddr[1] << 8 | eaddr[0]);
11642e3d4b79SPyun YongHyeon 	CSR_WRITE_4(sc, DC_AL_PAR1, eaddr[5] << 8 | eaddr[4]);
116596f2e892SBill Paul 
116696f2e892SBill Paul 	/* If we want promiscuous mode, set the allframes bit. */
116796f2e892SBill Paul 	if (ifp->if_flags & IFF_PROMISC)
116896f2e892SBill Paul 		DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
116996f2e892SBill Paul 	else
117096f2e892SBill Paul 		DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
117196f2e892SBill Paul 
117296f2e892SBill Paul 	if (ifp->if_flags & IFF_ALLMULTI)
117396f2e892SBill Paul 		DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
117496f2e892SBill Paul 	else
117596f2e892SBill Paul 		DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
117696f2e892SBill Paul 
11770934f18aSMaxime Henrion 	/* First, zot all the existing hash bits. */
117896f2e892SBill Paul 	CSR_WRITE_4(sc, DC_AL_MAR0, 0);
117996f2e892SBill Paul 	CSR_WRITE_4(sc, DC_AL_MAR1, 0);
118096f2e892SBill Paul 
118196f2e892SBill Paul 	/*
118296f2e892SBill Paul 	 * If we're already in promisc or allmulti mode, we
118396f2e892SBill Paul 	 * don't have to bother programming the multicast filter.
118496f2e892SBill Paul 	 */
118596f2e892SBill Paul 	if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI))
118696f2e892SBill Paul 		return;
118796f2e892SBill Paul 
11880934f18aSMaxime Henrion 	/* Now program new ones. */
118913b203d0SRobert Watson 	IF_ADDR_LOCK(ifp);
11906817526dSPoul-Henning Kamp 	TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
119196f2e892SBill Paul 		if (ifma->ifma_addr->sa_family != AF_LINK)
119296f2e892SBill Paul 			continue;
1193acc1bcccSMartin Blapp 		if (DC_IS_CENTAUR(sc))
1194aa825502SDavid E. O'Brien 			h = dc_mchash_le(sc,
1195aa825502SDavid E. O'Brien 			    LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1196acc1bcccSMartin Blapp 		else
1197aa825502SDavid E. O'Brien 			h = dc_mchash_be(
1198aa825502SDavid E. O'Brien 			    LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
119996f2e892SBill Paul 		if (h < 32)
120096f2e892SBill Paul 			hashes[0] |= (1 << h);
120196f2e892SBill Paul 		else
120296f2e892SBill Paul 			hashes[1] |= (1 << (h - 32));
120396f2e892SBill Paul 	}
120413b203d0SRobert Watson 	IF_ADDR_UNLOCK(ifp);
120596f2e892SBill Paul 
120696f2e892SBill Paul 	CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]);
120796f2e892SBill Paul 	CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]);
120896f2e892SBill Paul }
120996f2e892SBill Paul 
12102c876e15SPoul-Henning Kamp static void
12110934f18aSMaxime Henrion dc_setfilt_asix(struct dc_softc *sc)
121296f2e892SBill Paul {
12138df1ebe9SMarcel Moolenaar 	uint32_t eaddr[(ETHER_ADDR_LEN+3)/4];
121496f2e892SBill Paul 	struct ifnet *ifp;
12150934f18aSMaxime Henrion 	struct ifmultiaddr *ifma;
121696f2e892SBill Paul 	int h = 0;
121796f2e892SBill Paul 	u_int32_t hashes[2] = { 0, 0 };
121896f2e892SBill Paul 
1219fc74a9f9SBrooks Davis 	ifp = sc->dc_ifp;
122096f2e892SBill Paul 
12218df1ebe9SMarcel Moolenaar 	/* Init our MAC address. */
12228df1ebe9SMarcel Moolenaar 	bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN);
122396f2e892SBill Paul 	CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0);
12248df1ebe9SMarcel Moolenaar 	CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[0]);
122596f2e892SBill Paul 	CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1);
12268df1ebe9SMarcel Moolenaar 	CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[1]);
122796f2e892SBill Paul 
122896f2e892SBill Paul 	/* If we want promiscuous mode, set the allframes bit. */
122996f2e892SBill Paul 	if (ifp->if_flags & IFF_PROMISC)
123096f2e892SBill Paul 		DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
123196f2e892SBill Paul 	else
123296f2e892SBill Paul 		DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
123396f2e892SBill Paul 
123496f2e892SBill Paul 	if (ifp->if_flags & IFF_ALLMULTI)
123596f2e892SBill Paul 		DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
123696f2e892SBill Paul 	else
123796f2e892SBill Paul 		DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
123896f2e892SBill Paul 
123996f2e892SBill Paul 	/*
124096f2e892SBill Paul 	 * The ASIX chip has a special bit to enable reception
124196f2e892SBill Paul 	 * of broadcast frames.
124296f2e892SBill Paul 	 */
124396f2e892SBill Paul 	if (ifp->if_flags & IFF_BROADCAST)
124496f2e892SBill Paul 		DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD);
124596f2e892SBill Paul 	else
124696f2e892SBill Paul 		DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD);
124796f2e892SBill Paul 
124896f2e892SBill Paul 	/* first, zot all the existing hash bits */
124996f2e892SBill Paul 	CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0);
125096f2e892SBill Paul 	CSR_WRITE_4(sc, DC_AX_FILTDATA, 0);
125196f2e892SBill Paul 	CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1);
125296f2e892SBill Paul 	CSR_WRITE_4(sc, DC_AX_FILTDATA, 0);
125396f2e892SBill Paul 
125496f2e892SBill Paul 	/*
125596f2e892SBill Paul 	 * If we're already in promisc or allmulti mode, we
125696f2e892SBill Paul 	 * don't have to bother programming the multicast filter.
125796f2e892SBill Paul 	 */
125896f2e892SBill Paul 	if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI))
125996f2e892SBill Paul 		return;
126096f2e892SBill Paul 
126196f2e892SBill Paul 	/* now program new ones */
126213b203d0SRobert Watson 	IF_ADDR_LOCK(ifp);
12636817526dSPoul-Henning Kamp 	TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
126496f2e892SBill Paul 		if (ifma->ifma_addr->sa_family != AF_LINK)
126596f2e892SBill Paul 			continue;
1266aa825502SDavid E. O'Brien 		h = dc_mchash_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
126796f2e892SBill Paul 		if (h < 32)
126896f2e892SBill Paul 			hashes[0] |= (1 << h);
126996f2e892SBill Paul 		else
127096f2e892SBill Paul 			hashes[1] |= (1 << (h - 32));
127196f2e892SBill Paul 	}
127213b203d0SRobert Watson 	IF_ADDR_UNLOCK(ifp);
127396f2e892SBill Paul 
127496f2e892SBill Paul 	CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0);
127596f2e892SBill Paul 	CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]);
127696f2e892SBill Paul 	CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1);
127796f2e892SBill Paul 	CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]);
127896f2e892SBill Paul }
127996f2e892SBill Paul 
12802c876e15SPoul-Henning Kamp static void
12810934f18aSMaxime Henrion dc_setfilt_xircom(struct dc_softc *sc)
1282feb78939SJonathan Chen {
12838df1ebe9SMarcel Moolenaar 	uint16_t eaddr[(ETHER_ADDR_LEN+1)/2];
12840934f18aSMaxime Henrion 	struct ifnet *ifp;
12850934f18aSMaxime Henrion 	struct ifmultiaddr *ifma;
1286feb78939SJonathan Chen 	struct dc_desc *sframe;
1287feb78939SJonathan Chen 	u_int32_t h, *sp;
1288feb78939SJonathan Chen 	int i;
1289feb78939SJonathan Chen 
1290fc74a9f9SBrooks Davis 	ifp = sc->dc_ifp;
1291feb78939SJonathan Chen 	DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON));
1292feb78939SJonathan Chen 
1293feb78939SJonathan Chen 	i = sc->dc_cdata.dc_tx_prod;
1294feb78939SJonathan Chen 	DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT);
1295feb78939SJonathan Chen 	sc->dc_cdata.dc_tx_cnt++;
1296feb78939SJonathan Chen 	sframe = &sc->dc_ldata->dc_tx_list[i];
129756e5e7aeSMaxime Henrion 	sp = sc->dc_cdata.dc_sbuf;
12980934f18aSMaxime Henrion 	bzero(sp, DC_SFRAME_LEN);
1299feb78939SJonathan Chen 
1300af4358c7SMaxime Henrion 	sframe->dc_data = htole32(sc->dc_saddr);
1301af4358c7SMaxime Henrion 	sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP |
1302af4358c7SMaxime Henrion 	    DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT);
1303feb78939SJonathan Chen 
130456e5e7aeSMaxime Henrion 	sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf;
1305feb78939SJonathan Chen 
1306feb78939SJonathan Chen 	/* If we want promiscuous mode, set the allframes bit. */
1307feb78939SJonathan Chen 	if (ifp->if_flags & IFF_PROMISC)
1308feb78939SJonathan Chen 		DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1309feb78939SJonathan Chen 	else
1310feb78939SJonathan Chen 		DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1311feb78939SJonathan Chen 
1312feb78939SJonathan Chen 	if (ifp->if_flags & IFF_ALLMULTI)
1313feb78939SJonathan Chen 		DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1314feb78939SJonathan Chen 	else
1315feb78939SJonathan Chen 		DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1316feb78939SJonathan Chen 
131713b203d0SRobert Watson 	IF_ADDR_LOCK(ifp);
13186817526dSPoul-Henning Kamp 	TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1319feb78939SJonathan Chen 		if (ifma->ifma_addr->sa_family != AF_LINK)
1320feb78939SJonathan Chen 			continue;
1321aa825502SDavid E. O'Brien 		h = dc_mchash_le(sc,
13221d5e5310SBill Paul 		    LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1323af4358c7SMaxime Henrion 		sp[h >> 4] |= htole32(1 << (h & 0xF));
1324feb78939SJonathan Chen 	}
132513b203d0SRobert Watson 	IF_ADDR_UNLOCK(ifp);
1326feb78939SJonathan Chen 
1327feb78939SJonathan Chen 	if (ifp->if_flags & IFF_BROADCAST) {
1328aa825502SDavid E. O'Brien 		h = dc_mchash_le(sc, ifp->if_broadcastaddr);
1329af4358c7SMaxime Henrion 		sp[h >> 4] |= htole32(1 << (h & 0xF));
1330feb78939SJonathan Chen 	}
1331feb78939SJonathan Chen 
13328df1ebe9SMarcel Moolenaar 	/* Set our MAC address. */
13338df1ebe9SMarcel Moolenaar 	bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN);
13348df1ebe9SMarcel Moolenaar 	sp[0] = DC_SP_MAC(eaddr[0]);
13358df1ebe9SMarcel Moolenaar 	sp[1] = DC_SP_MAC(eaddr[1]);
13368df1ebe9SMarcel Moolenaar 	sp[2] = DC_SP_MAC(eaddr[2]);
1337feb78939SJonathan Chen 
1338feb78939SJonathan Chen 	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
1339feb78939SJonathan Chen 	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON);
134013f4c340SRobert Watson 	ifp->if_drv_flags |= IFF_DRV_RUNNING;
1341af4358c7SMaxime Henrion 	sframe->dc_status = htole32(DC_TXSTAT_OWN);
1342feb78939SJonathan Chen 	CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
1343feb78939SJonathan Chen 
1344feb78939SJonathan Chen 	/*
13450934f18aSMaxime Henrion 	 * Wait some time...
1346feb78939SJonathan Chen 	 */
1347feb78939SJonathan Chen 	DELAY(1000);
1348feb78939SJonathan Chen 
1349b1d16143SMarius Strobl 	sc->dc_wdog_timer = 5;
1350feb78939SJonathan Chen }
1351feb78939SJonathan Chen 
1352e3d2833aSAlfred Perlstein static void
13530934f18aSMaxime Henrion dc_setfilt(struct dc_softc *sc)
135496f2e892SBill Paul {
13550934f18aSMaxime Henrion 
135696f2e892SBill Paul 	if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) ||
13571af8bec7SBill Paul 	    DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc))
135896f2e892SBill Paul 		dc_setfilt_21143(sc);
135996f2e892SBill Paul 
136096f2e892SBill Paul 	if (DC_IS_ASIX(sc))
136196f2e892SBill Paul 		dc_setfilt_asix(sc);
136296f2e892SBill Paul 
136396f2e892SBill Paul 	if (DC_IS_ADMTEK(sc))
136496f2e892SBill Paul 		dc_setfilt_admtek(sc);
136596f2e892SBill Paul 
1366feb78939SJonathan Chen 	if (DC_IS_XIRCOM(sc))
1367feb78939SJonathan Chen 		dc_setfilt_xircom(sc);
136896f2e892SBill Paul }
136996f2e892SBill Paul 
137096f2e892SBill Paul /*
13710934f18aSMaxime Henrion  * In order to fiddle with the 'full-duplex' and '100Mbps' bits in
13720934f18aSMaxime Henrion  * the netconfig register, we first have to put the transmit and/or
13730934f18aSMaxime Henrion  * receive logic in the idle state.
137496f2e892SBill Paul  */
1375e3d2833aSAlfred Perlstein static void
13760934f18aSMaxime Henrion dc_setcfg(struct dc_softc *sc, int media)
137796f2e892SBill Paul {
13780934f18aSMaxime Henrion 	int i, restart = 0, watchdogreg;
137996f2e892SBill Paul 	u_int32_t isr;
138096f2e892SBill Paul 
138196f2e892SBill Paul 	if (IFM_SUBTYPE(media) == IFM_NONE)
138296f2e892SBill Paul 		return;
138396f2e892SBill Paul 
138496f2e892SBill Paul 	if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) {
138596f2e892SBill Paul 		restart = 1;
138696f2e892SBill Paul 		DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON));
138796f2e892SBill Paul 
138896f2e892SBill Paul 		for (i = 0; i < DC_TIMEOUT; i++) {
138996f2e892SBill Paul 			isr = CSR_READ_4(sc, DC_ISR);
1390d467c136SBill Paul 			if (isr & DC_ISR_TX_IDLE &&
1391351267c1SMartin Blapp 			    ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED ||
1392351267c1SMartin Blapp 			    (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT))
139396f2e892SBill Paul 				break;
1394d467c136SBill Paul 			DELAY(10);
139596f2e892SBill Paul 		}
139696f2e892SBill Paul 
1397432120f2SMarius Strobl 		if (i == DC_TIMEOUT) {
1398432120f2SMarius Strobl 			if (!(isr & DC_ISR_TX_IDLE) && !DC_IS_ASIX(sc))
13996b9f5c94SGleb Smirnoff 				device_printf(sc->dc_dev,
1400432120f2SMarius Strobl 				    "%s: failed to force tx to idle state\n",
1401432120f2SMarius Strobl 				    __func__);
1402432120f2SMarius Strobl 			if (!((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED ||
1403432120f2SMarius Strobl 			    (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT) &&
1404d0d67284SMarius Strobl 			    !DC_HAS_BROKEN_RXSTATE(sc))
1405432120f2SMarius Strobl 				device_printf(sc->dc_dev,
1406432120f2SMarius Strobl 				    "%s: failed to force rx to idle state\n",
1407432120f2SMarius Strobl 				    __func__);
1408432120f2SMarius Strobl 		}
140996f2e892SBill Paul 	}
141096f2e892SBill Paul 
141196f2e892SBill Paul 	if (IFM_SUBTYPE(media) == IFM_100_TX) {
1412042c8f6eSBill Paul 		DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1413042c8f6eSBill Paul 		DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
141496f2e892SBill Paul 		if (sc->dc_pmode == DC_PMODE_MII) {
1415bf645417SBill Paul 			if (DC_IS_INTEL(sc)) {
14160934f18aSMaxime Henrion 			/* There's a write enable bit here that reads as 1. */
14178273d5f8SBill Paul 				watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
14188273d5f8SBill Paul 				watchdogreg &= ~DC_WDOG_CTLWREN;
14198273d5f8SBill Paul 				watchdogreg |= DC_WDOG_JABBERDIS;
14204c2efe27SBill Paul 				CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
1421bf645417SBill Paul 			} else {
1422bf645417SBill Paul 				DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
1423bf645417SBill Paul 			}
142496f2e892SBill Paul 			DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS |
142596f2e892SBill Paul 			    DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER));
142696f2e892SBill Paul 			if (sc->dc_type == DC_TYPE_98713)
142796f2e892SBill Paul 				DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS |
142896f2e892SBill Paul 				    DC_NETCFG_SCRAMBLER));
142988d739dcSBill Paul 			if (!DC_IS_DAVICOM(sc))
143096f2e892SBill Paul 				DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
143196f2e892SBill Paul 			DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1432e99285a4SBill Paul 			if (DC_IS_INTEL(sc))
1433e99285a4SBill Paul 				dc_apply_fixup(sc, IFM_AUTO);
143496f2e892SBill Paul 		} else {
143596f2e892SBill Paul 			if (DC_IS_PNIC(sc)) {
143696f2e892SBill Paul 				DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL);
143796f2e892SBill Paul 				DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
143896f2e892SBill Paul 				DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
143996f2e892SBill Paul 			}
1440318b02fdSBill Paul 			DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1441318b02fdSBill Paul 			DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1442318b02fdSBill Paul 			DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
14435c1cfac4SBill Paul 			if (DC_IS_INTEL(sc))
14445c1cfac4SBill Paul 				dc_apply_fixup(sc,
14455c1cfac4SBill Paul 				    (media & IFM_GMASK) == IFM_FDX ?
14465c1cfac4SBill Paul 				    IFM_100_TX | IFM_FDX : IFM_100_TX);
144796f2e892SBill Paul 		}
144896f2e892SBill Paul 	}
144996f2e892SBill Paul 
145096f2e892SBill Paul 	if (IFM_SUBTYPE(media) == IFM_10_T) {
1451042c8f6eSBill Paul 		DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1452042c8f6eSBill Paul 		DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
145396f2e892SBill Paul 		if (sc->dc_pmode == DC_PMODE_MII) {
14540934f18aSMaxime Henrion 			/* There's a write enable bit here that reads as 1. */
14554c2efe27SBill Paul 			if (DC_IS_INTEL(sc)) {
14568273d5f8SBill Paul 				watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
14578273d5f8SBill Paul 				watchdogreg &= ~DC_WDOG_CTLWREN;
14588273d5f8SBill Paul 				watchdogreg |= DC_WDOG_JABBERDIS;
14598273d5f8SBill Paul 				CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
14604c2efe27SBill Paul 			} else {
14614c2efe27SBill Paul 				DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
14624c2efe27SBill Paul 			}
146396f2e892SBill Paul 			DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS |
146496f2e892SBill Paul 			    DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER));
146596f2e892SBill Paul 			if (sc->dc_type == DC_TYPE_98713)
146696f2e892SBill Paul 				DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
146788d739dcSBill Paul 			if (!DC_IS_DAVICOM(sc))
146896f2e892SBill Paul 				DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
146996f2e892SBill Paul 			DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1470e99285a4SBill Paul 			if (DC_IS_INTEL(sc))
1471e99285a4SBill Paul 				dc_apply_fixup(sc, IFM_AUTO);
147296f2e892SBill Paul 		} else {
147396f2e892SBill Paul 			if (DC_IS_PNIC(sc)) {
147496f2e892SBill Paul 				DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL);
147596f2e892SBill Paul 				DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
147696f2e892SBill Paul 				DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
147796f2e892SBill Paul 			}
147896f2e892SBill Paul 			DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1479318b02fdSBill Paul 			DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
148096f2e892SBill Paul 			DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
14815c1cfac4SBill Paul 			if (DC_IS_INTEL(sc)) {
14825c1cfac4SBill Paul 				DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET);
14835c1cfac4SBill Paul 				DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
14845c1cfac4SBill Paul 				if ((media & IFM_GMASK) == IFM_FDX)
14855c1cfac4SBill Paul 					DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D);
14865c1cfac4SBill Paul 				else
14875c1cfac4SBill Paul 					DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F);
14885c1cfac4SBill Paul 				DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
14895c1cfac4SBill Paul 				DC_CLRBIT(sc, DC_10BTCTRL,
14905c1cfac4SBill Paul 				    DC_TCTL_AUTONEGENBL);
14915c1cfac4SBill Paul 				dc_apply_fixup(sc,
14925c1cfac4SBill Paul 				    (media & IFM_GMASK) == IFM_FDX ?
14935c1cfac4SBill Paul 				    IFM_10_T | IFM_FDX : IFM_10_T);
14945c1cfac4SBill Paul 				DELAY(20000);
14955c1cfac4SBill Paul 			}
149696f2e892SBill Paul 		}
149796f2e892SBill Paul 	}
149896f2e892SBill Paul 
1499f43d9309SBill Paul 	/*
1500f43d9309SBill Paul 	 * If this is a Davicom DM9102A card with a DM9801 HomePNA
1501f43d9309SBill Paul 	 * PHY and we want HomePNA mode, set the portsel bit to turn
1502f43d9309SBill Paul 	 * on the external MII port.
1503f43d9309SBill Paul 	 */
1504f43d9309SBill Paul 	if (DC_IS_DAVICOM(sc)) {
150545521525SPoul-Henning Kamp 		if (IFM_SUBTYPE(media) == IFM_HPNA_1) {
1506f43d9309SBill Paul 			DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1507f43d9309SBill Paul 			sc->dc_link = 1;
1508f43d9309SBill Paul 		} else {
1509f43d9309SBill Paul 			DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1510f43d9309SBill Paul 		}
1511f43d9309SBill Paul 	}
1512f43d9309SBill Paul 
151396f2e892SBill Paul 	if ((media & IFM_GMASK) == IFM_FDX) {
151496f2e892SBill Paul 		DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
151596f2e892SBill Paul 		if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
151696f2e892SBill Paul 			DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
151796f2e892SBill Paul 	} else {
151896f2e892SBill Paul 		DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
151996f2e892SBill Paul 		if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
152096f2e892SBill Paul 			DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
152196f2e892SBill Paul 	}
152296f2e892SBill Paul 
152396f2e892SBill Paul 	if (restart)
152496f2e892SBill Paul 		DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON | DC_NETCFG_RX_ON);
152596f2e892SBill Paul }
152696f2e892SBill Paul 
1527e3d2833aSAlfred Perlstein static void
15280934f18aSMaxime Henrion dc_reset(struct dc_softc *sc)
152996f2e892SBill Paul {
15300934f18aSMaxime Henrion 	int i;
153196f2e892SBill Paul 
153296f2e892SBill Paul 	DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
153396f2e892SBill Paul 
153496f2e892SBill Paul 	for (i = 0; i < DC_TIMEOUT; i++) {
153596f2e892SBill Paul 		DELAY(10);
153696f2e892SBill Paul 		if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET))
153796f2e892SBill Paul 			break;
153896f2e892SBill Paul 	}
153996f2e892SBill Paul 
15401af8bec7SBill Paul 	if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) ||
15411d5e5310SBill Paul 	    DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) {
154296f2e892SBill Paul 		DELAY(10000);
154396f2e892SBill Paul 		DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
154496f2e892SBill Paul 		i = 0;
154596f2e892SBill Paul 	}
154696f2e892SBill Paul 
154796f2e892SBill Paul 	if (i == DC_TIMEOUT)
15486b9f5c94SGleb Smirnoff 		device_printf(sc->dc_dev, "reset never completed!\n");
154996f2e892SBill Paul 
155096f2e892SBill Paul 	/* Wait a little while for the chip to get its brains in order. */
155196f2e892SBill Paul 	DELAY(1000);
155296f2e892SBill Paul 
155396f2e892SBill Paul 	CSR_WRITE_4(sc, DC_IMR, 0x00000000);
155496f2e892SBill Paul 	CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000);
155596f2e892SBill Paul 	CSR_WRITE_4(sc, DC_NETCFG, 0x00000000);
155696f2e892SBill Paul 
155791cc2adbSBill Paul 	/*
155891cc2adbSBill Paul 	 * Bring the SIA out of reset. In some cases, it looks
155991cc2adbSBill Paul 	 * like failing to unreset the SIA soon enough gets it
156091cc2adbSBill Paul 	 * into a state where it will never come out of reset
156191cc2adbSBill Paul 	 * until we reset the whole chip again.
156291cc2adbSBill Paul 	 */
15635c1cfac4SBill Paul 	if (DC_IS_INTEL(sc)) {
156491cc2adbSBill Paul 		DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
15655c1cfac4SBill Paul 		CSR_WRITE_4(sc, DC_10BTCTRL, 0);
15665c1cfac4SBill Paul 		CSR_WRITE_4(sc, DC_WATCHDOG, 0);
15675c1cfac4SBill Paul 	}
156896f2e892SBill Paul }
156996f2e892SBill Paul 
1570ebc284ccSMarius Strobl static const struct dc_type *
15710934f18aSMaxime Henrion dc_devtype(device_t dev)
157296f2e892SBill Paul {
1573ebc284ccSMarius Strobl 	const struct dc_type *t;
15741e2e70b1SJohn Baldwin 	u_int32_t devid;
15751e2e70b1SJohn Baldwin 	u_int8_t rev;
157696f2e892SBill Paul 
157796f2e892SBill Paul 	t = dc_devs;
15781e2e70b1SJohn Baldwin 	devid = pci_get_devid(dev);
15791e2e70b1SJohn Baldwin 	rev = pci_get_revid(dev);
158096f2e892SBill Paul 
158196f2e892SBill Paul 	while (t->dc_name != NULL) {
15821e2e70b1SJohn Baldwin 		if (devid == t->dc_devid && rev >= t->dc_minrev)
158396f2e892SBill Paul 			return (t);
158496f2e892SBill Paul 		t++;
158596f2e892SBill Paul 	}
158696f2e892SBill Paul 
158796f2e892SBill Paul 	return (NULL);
158896f2e892SBill Paul }
158996f2e892SBill Paul 
159096f2e892SBill Paul /*
159196f2e892SBill Paul  * Probe for a 21143 or clone chip. Check the PCI vendor and device
159296f2e892SBill Paul  * IDs against our list and return a device name if we find a match.
159396f2e892SBill Paul  * We do a little bit of extra work to identify the exact type of
159496f2e892SBill Paul  * chip. The MX98713 and MX98713A have the same PCI vendor/device ID,
159596f2e892SBill Paul  * but different revision IDs. The same is true for 98715/98715A
159696f2e892SBill Paul  * chips and the 98725, as well as the ASIX and ADMtek chips. In some
159796f2e892SBill Paul  * cases, the exact chip revision affects driver behavior.
159896f2e892SBill Paul  */
1599e3d2833aSAlfred Perlstein static int
16000934f18aSMaxime Henrion dc_probe(device_t dev)
160196f2e892SBill Paul {
1602ebc284ccSMarius Strobl 	const struct dc_type *t;
160396f2e892SBill Paul 
160496f2e892SBill Paul 	t = dc_devtype(dev);
160596f2e892SBill Paul 
160696f2e892SBill Paul 	if (t != NULL) {
160796f2e892SBill Paul 		device_set_desc(dev, t->dc_name);
1608d701c913SWarner Losh 		return (BUS_PROBE_DEFAULT);
160996f2e892SBill Paul 	}
161096f2e892SBill Paul 
161196f2e892SBill Paul 	return (ENXIO);
161296f2e892SBill Paul }
161396f2e892SBill Paul 
1614e3d2833aSAlfred Perlstein static void
16150934f18aSMaxime Henrion dc_apply_fixup(struct dc_softc *sc, int media)
16165c1cfac4SBill Paul {
16175c1cfac4SBill Paul 	struct dc_mediainfo *m;
16185c1cfac4SBill Paul 	u_int8_t *p;
16195c1cfac4SBill Paul 	int i;
16205d801891SBill Paul 	u_int32_t reg;
16215c1cfac4SBill Paul 
16225c1cfac4SBill Paul 	m = sc->dc_mi;
16235c1cfac4SBill Paul 
16245c1cfac4SBill Paul 	while (m != NULL) {
16255c1cfac4SBill Paul 		if (m->dc_media == media)
16265c1cfac4SBill Paul 			break;
16275c1cfac4SBill Paul 		m = m->dc_next;
16285c1cfac4SBill Paul 	}
16295c1cfac4SBill Paul 
16305c1cfac4SBill Paul 	if (m == NULL)
16315c1cfac4SBill Paul 		return;
16325c1cfac4SBill Paul 
16335c1cfac4SBill Paul 	for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) {
16345c1cfac4SBill Paul 		reg = (p[0] | (p[1] << 8)) << 16;
16355c1cfac4SBill Paul 		CSR_WRITE_4(sc, DC_WATCHDOG, reg);
16365c1cfac4SBill Paul 	}
16375c1cfac4SBill Paul 
16385c1cfac4SBill Paul 	for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) {
16395c1cfac4SBill Paul 		reg = (p[0] | (p[1] << 8)) << 16;
16405c1cfac4SBill Paul 		CSR_WRITE_4(sc, DC_WATCHDOG, reg);
16415c1cfac4SBill Paul 	}
16425c1cfac4SBill Paul }
16435c1cfac4SBill Paul 
1644e3d2833aSAlfred Perlstein static void
16450934f18aSMaxime Henrion dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l)
16465c1cfac4SBill Paul {
16475c1cfac4SBill Paul 	struct dc_mediainfo *m;
16485c1cfac4SBill Paul 
16490934f18aSMaxime Henrion 	m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO);
165087f4fa15SMartin Blapp 	switch (l->dc_sia_code & ~DC_SIA_CODE_EXT) {
165187f4fa15SMartin Blapp 	case DC_SIA_CODE_10BT:
16525c1cfac4SBill Paul 		m->dc_media = IFM_10_T;
165387f4fa15SMartin Blapp 		break;
165487f4fa15SMartin Blapp 	case DC_SIA_CODE_10BT_FDX:
16555c1cfac4SBill Paul 		m->dc_media = IFM_10_T | IFM_FDX;
165687f4fa15SMartin Blapp 		break;
165787f4fa15SMartin Blapp 	case DC_SIA_CODE_10B2:
16585c1cfac4SBill Paul 		m->dc_media = IFM_10_2;
165987f4fa15SMartin Blapp 		break;
166087f4fa15SMartin Blapp 	case DC_SIA_CODE_10B5:
16615c1cfac4SBill Paul 		m->dc_media = IFM_10_5;
166287f4fa15SMartin Blapp 		break;
166387f4fa15SMartin Blapp 	default:
166487f4fa15SMartin Blapp 		break;
166587f4fa15SMartin Blapp 	}
16665c1cfac4SBill Paul 
166787f4fa15SMartin Blapp 	/*
166887f4fa15SMartin Blapp 	 * We need to ignore CSR13, CSR14, CSR15 for SIA mode.
166987f4fa15SMartin Blapp 	 * Things apparently already work for cards that do
167087f4fa15SMartin Blapp 	 * supply Media Specific Data.
167187f4fa15SMartin Blapp 	 */
167287f4fa15SMartin Blapp 	if (l->dc_sia_code & DC_SIA_CODE_EXT) {
16735c1cfac4SBill Paul 		m->dc_gp_len = 2;
167487f4fa15SMartin Blapp 		m->dc_gp_ptr =
167587f4fa15SMartin Blapp 		(u_int8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl;
167687f4fa15SMartin Blapp 	} else {
167787f4fa15SMartin Blapp 		m->dc_gp_len = 2;
167887f4fa15SMartin Blapp 		m->dc_gp_ptr =
167987f4fa15SMartin Blapp 		(u_int8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl;
168087f4fa15SMartin Blapp 	}
16815c1cfac4SBill Paul 
16825c1cfac4SBill Paul 	m->dc_next = sc->dc_mi;
16835c1cfac4SBill Paul 	sc->dc_mi = m;
16845c1cfac4SBill Paul 
16855c1cfac4SBill Paul 	sc->dc_pmode = DC_PMODE_SIA;
16865c1cfac4SBill Paul }
16875c1cfac4SBill Paul 
1688e3d2833aSAlfred Perlstein static void
16890934f18aSMaxime Henrion dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l)
16905c1cfac4SBill Paul {
16915c1cfac4SBill Paul 	struct dc_mediainfo *m;
16925c1cfac4SBill Paul 
16930934f18aSMaxime Henrion 	m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO);
16945c1cfac4SBill Paul 	if (l->dc_sym_code == DC_SYM_CODE_100BT)
16955c1cfac4SBill Paul 		m->dc_media = IFM_100_TX;
16965c1cfac4SBill Paul 
16975c1cfac4SBill Paul 	if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX)
16985c1cfac4SBill Paul 		m->dc_media = IFM_100_TX | IFM_FDX;
16995c1cfac4SBill Paul 
17005c1cfac4SBill Paul 	m->dc_gp_len = 2;
17015c1cfac4SBill Paul 	m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl;
17025c1cfac4SBill Paul 
17035c1cfac4SBill Paul 	m->dc_next = sc->dc_mi;
17045c1cfac4SBill Paul 	sc->dc_mi = m;
17055c1cfac4SBill Paul 
17065c1cfac4SBill Paul 	sc->dc_pmode = DC_PMODE_SYM;
17075c1cfac4SBill Paul }
17085c1cfac4SBill Paul 
1709e3d2833aSAlfred Perlstein static void
17100934f18aSMaxime Henrion dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l)
17115c1cfac4SBill Paul {
17125c1cfac4SBill Paul 	struct dc_mediainfo *m;
17130934f18aSMaxime Henrion 	u_int8_t *p;
17145c1cfac4SBill Paul 
17150934f18aSMaxime Henrion 	m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO);
17165c1cfac4SBill Paul 	/* We abuse IFM_AUTO to represent MII. */
17175c1cfac4SBill Paul 	m->dc_media = IFM_AUTO;
17185c1cfac4SBill Paul 	m->dc_gp_len = l->dc_gpr_len;
17195c1cfac4SBill Paul 
17205c1cfac4SBill Paul 	p = (u_int8_t *)l;
17215c1cfac4SBill Paul 	p += sizeof(struct dc_eblock_mii);
17225c1cfac4SBill Paul 	m->dc_gp_ptr = p;
17235c1cfac4SBill Paul 	p += 2 * l->dc_gpr_len;
17245c1cfac4SBill Paul 	m->dc_reset_len = *p;
17255c1cfac4SBill Paul 	p++;
17265c1cfac4SBill Paul 	m->dc_reset_ptr = p;
17275c1cfac4SBill Paul 
17285c1cfac4SBill Paul 	m->dc_next = sc->dc_mi;
17295c1cfac4SBill Paul 	sc->dc_mi = m;
17305c1cfac4SBill Paul }
17315c1cfac4SBill Paul 
17322c876e15SPoul-Henning Kamp static void
17330934f18aSMaxime Henrion dc_read_srom(struct dc_softc *sc, int bits)
17343097aa70SWarner Losh {
17353097aa70SWarner Losh 	int size;
17363097aa70SWarner Losh 
17373097aa70SWarner Losh 	size = 2 << bits;
17383097aa70SWarner Losh 	sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT);
17393097aa70SWarner Losh 	dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0);
17403097aa70SWarner Losh }
17413097aa70SWarner Losh 
1742e3d2833aSAlfred Perlstein static void
17430934f18aSMaxime Henrion dc_parse_21143_srom(struct dc_softc *sc)
17445c1cfac4SBill Paul {
17455c1cfac4SBill Paul 	struct dc_leaf_hdr *lhdr;
17465c1cfac4SBill Paul 	struct dc_eblock_hdr *hdr;
17470934f18aSMaxime Henrion 	int have_mii, i, loff;
17485c1cfac4SBill Paul 	char *ptr;
17495c1cfac4SBill Paul 
1750f956e0b3SMartin Blapp 	have_mii = 0;
17515c1cfac4SBill Paul 	loff = sc->dc_srom[27];
17525c1cfac4SBill Paul 	lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]);
17535c1cfac4SBill Paul 
17545c1cfac4SBill Paul 	ptr = (char *)lhdr;
17555c1cfac4SBill Paul 	ptr += sizeof(struct dc_leaf_hdr) - 1;
1756f956e0b3SMartin Blapp 	/*
1757f956e0b3SMartin Blapp 	 * Look if we got a MII media block.
1758f956e0b3SMartin Blapp 	 */
1759f956e0b3SMartin Blapp 	for (i = 0; i < lhdr->dc_mcnt; i++) {
1760f956e0b3SMartin Blapp 		hdr = (struct dc_eblock_hdr *)ptr;
1761f956e0b3SMartin Blapp 		if (hdr->dc_type == DC_EBLOCK_MII)
1762f956e0b3SMartin Blapp 		    have_mii++;
1763f956e0b3SMartin Blapp 
1764f956e0b3SMartin Blapp 		ptr += (hdr->dc_len & 0x7F);
1765f956e0b3SMartin Blapp 		ptr++;
1766f956e0b3SMartin Blapp 	}
1767f956e0b3SMartin Blapp 
1768f956e0b3SMartin Blapp 	/*
1769f956e0b3SMartin Blapp 	 * Do the same thing again. Only use SIA and SYM media
1770f956e0b3SMartin Blapp 	 * blocks if no MII media block is available.
1771f956e0b3SMartin Blapp 	 */
1772f956e0b3SMartin Blapp 	ptr = (char *)lhdr;
1773f956e0b3SMartin Blapp 	ptr += sizeof(struct dc_leaf_hdr) - 1;
17745c1cfac4SBill Paul 	for (i = 0; i < lhdr->dc_mcnt; i++) {
17755c1cfac4SBill Paul 		hdr = (struct dc_eblock_hdr *)ptr;
17765c1cfac4SBill Paul 		switch (hdr->dc_type) {
17775c1cfac4SBill Paul 		case DC_EBLOCK_MII:
17785c1cfac4SBill Paul 			dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr);
17795c1cfac4SBill Paul 			break;
17805c1cfac4SBill Paul 		case DC_EBLOCK_SIA:
1781f956e0b3SMartin Blapp 			if (! have_mii)
1782f956e0b3SMartin Blapp 				dc_decode_leaf_sia(sc,
1783f956e0b3SMartin Blapp 				    (struct dc_eblock_sia *)hdr);
17845c1cfac4SBill Paul 			break;
17855c1cfac4SBill Paul 		case DC_EBLOCK_SYM:
1786f956e0b3SMartin Blapp 			if (! have_mii)
1787f956e0b3SMartin Blapp 				dc_decode_leaf_sym(sc,
1788f956e0b3SMartin Blapp 				    (struct dc_eblock_sym *)hdr);
17895c1cfac4SBill Paul 			break;
17905c1cfac4SBill Paul 		default:
17915c1cfac4SBill Paul 			/* Don't care. Yet. */
17925c1cfac4SBill Paul 			break;
17935c1cfac4SBill Paul 		}
17945c1cfac4SBill Paul 		ptr += (hdr->dc_len & 0x7F);
17955c1cfac4SBill Paul 		ptr++;
17965c1cfac4SBill Paul 	}
17975c1cfac4SBill Paul }
17985c1cfac4SBill Paul 
179956e5e7aeSMaxime Henrion static void
180056e5e7aeSMaxime Henrion dc_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
180156e5e7aeSMaxime Henrion {
180256e5e7aeSMaxime Henrion 	u_int32_t *paddr;
180356e5e7aeSMaxime Henrion 
1804ebc284ccSMarius Strobl 	KASSERT(nseg == 1,
1805ebc284ccSMarius Strobl 	    ("%s: wrong number of segments (%d)", __func__, nseg));
180656e5e7aeSMaxime Henrion 	paddr = arg;
180756e5e7aeSMaxime Henrion 	*paddr = segs->ds_addr;
180856e5e7aeSMaxime Henrion }
180956e5e7aeSMaxime Henrion 
181096f2e892SBill Paul /*
181196f2e892SBill Paul  * Attach the interface. Allocate softc structures, do ifmedia
181296f2e892SBill Paul  * setup and ethernet/BPF attach.
181396f2e892SBill Paul  */
1814e3d2833aSAlfred Perlstein static int
18150934f18aSMaxime Henrion dc_attach(device_t dev)
181696f2e892SBill Paul {
1817d1ce9105SBill Paul 	int tmp = 0;
18188df1ebe9SMarcel Moolenaar 	uint32_t eaddr[(ETHER_ADDR_LEN+3)/4];
181996f2e892SBill Paul 	u_int32_t command;
182096f2e892SBill Paul 	struct dc_softc *sc;
182196f2e892SBill Paul 	struct ifnet *ifp;
18222e3d4b79SPyun YongHyeon 	u_int32_t reg, revision;
182322f6205dSJohn Baldwin 	int error = 0, rid, mac_offset;
182456e5e7aeSMaxime Henrion 	int i;
1825e7b01d07SWarner Losh 	u_int8_t *mac;
182696f2e892SBill Paul 
182796f2e892SBill Paul 	sc = device_get_softc(dev);
18286b9f5c94SGleb Smirnoff 	sc->dc_dev = dev;
182996f2e892SBill Paul 
18306008862bSJohn Baldwin 	mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1831c8b27acaSJohn Baldwin 	    MTX_DEF);
1832c3e7434fSWarner Losh 
183396f2e892SBill Paul 	/*
183496f2e892SBill Paul 	 * Map control/status registers.
183596f2e892SBill Paul 	 */
183607f65363SBill Paul 	pci_enable_busmaster(dev);
183796f2e892SBill Paul 
183896f2e892SBill Paul 	rid = DC_RID;
18395f96beb9SNate Lawson 	sc->dc_res = bus_alloc_resource_any(dev, DC_RES, &rid, RF_ACTIVE);
184096f2e892SBill Paul 
184196f2e892SBill Paul 	if (sc->dc_res == NULL) {
184222f6205dSJohn Baldwin 		device_printf(dev, "couldn't map ports/memory\n");
184396f2e892SBill Paul 		error = ENXIO;
1844608654d4SNate Lawson 		goto fail;
184596f2e892SBill Paul 	}
184696f2e892SBill Paul 
184796f2e892SBill Paul 	sc->dc_btag = rman_get_bustag(sc->dc_res);
184896f2e892SBill Paul 	sc->dc_bhandle = rman_get_bushandle(sc->dc_res);
184996f2e892SBill Paul 
18500934f18aSMaxime Henrion 	/* Allocate interrupt. */
185154f1f1d1SNate Lawson 	rid = 0;
18525f96beb9SNate Lawson 	sc->dc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
185354f1f1d1SNate Lawson 	    RF_SHAREABLE | RF_ACTIVE);
185454f1f1d1SNate Lawson 
185554f1f1d1SNate Lawson 	if (sc->dc_irq == NULL) {
185622f6205dSJohn Baldwin 		device_printf(dev, "couldn't map interrupt\n");
185754f1f1d1SNate Lawson 		error = ENXIO;
185854f1f1d1SNate Lawson 		goto fail;
185954f1f1d1SNate Lawson 	}
186054f1f1d1SNate Lawson 
186196f2e892SBill Paul 	/* Need this info to decide on a chip type. */
186296f2e892SBill Paul 	sc->dc_info = dc_devtype(dev);
18631e2e70b1SJohn Baldwin 	revision = pci_get_revid(dev);
186496f2e892SBill Paul 
18656d0dd931SWarner Losh 	/* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */
18661e2e70b1SJohn Baldwin 	if (sc->dc_info->dc_devid !=
18671e2e70b1SJohn Baldwin 	    DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168) &&
18681e2e70b1SJohn Baldwin 	    sc->dc_info->dc_devid !=
18691e2e70b1SJohn Baldwin 	    DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201))
1870eecb3844SMartin Blapp 		dc_eeprom_width(sc);
1871eecb3844SMartin Blapp 
18721e2e70b1SJohn Baldwin 	switch (sc->dc_info->dc_devid) {
18731e2e70b1SJohn Baldwin 	case DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143):
187496f2e892SBill Paul 		sc->dc_type = DC_TYPE_21143;
187596f2e892SBill Paul 		sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR;
1876042c8f6eSBill Paul 		sc->dc_flags |= DC_REDUCED_MII_POLL;
18775c1cfac4SBill Paul 		/* Save EEPROM contents so we can parse them later. */
18783097aa70SWarner Losh 		dc_read_srom(sc, sc->dc_romwidth);
187996f2e892SBill Paul 		break;
18801e2e70b1SJohn Baldwin 	case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009):
18811e2e70b1SJohn Baldwin 	case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100):
18821e2e70b1SJohn Baldwin 	case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102):
188396f2e892SBill Paul 		sc->dc_type = DC_TYPE_DM9102;
1884318a72d7SBill Paul 		sc->dc_flags |= DC_TX_COALESCE | DC_TX_INTR_ALWAYS;
1885318a72d7SBill Paul 		sc->dc_flags |= DC_REDUCED_MII_POLL | DC_TX_STORENFWD;
18867dfdc26cSMartin Blapp 		sc->dc_flags |= DC_TX_ALIGN;
18874a80e74bSMartin Blapp 		sc->dc_pmode = DC_PMODE_MII;
18881e2e70b1SJohn Baldwin 
18890a46b1dcSBill Paul 		/* Increase the latency timer value. */
18901e2e70b1SJohn Baldwin 		pci_write_config(dev, PCIR_LATTIMER, 0x80, 1);
189196f2e892SBill Paul 		break;
18921e2e70b1SJohn Baldwin 	case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981):
189396f2e892SBill Paul 		sc->dc_type = DC_TYPE_AL981;
189496f2e892SBill Paul 		sc->dc_flags |= DC_TX_USE_TX_INTR;
189596f2e892SBill Paul 		sc->dc_flags |= DC_TX_ADMTEK_WAR;
189696f2e892SBill Paul 		sc->dc_pmode = DC_PMODE_MII;
18973097aa70SWarner Losh 		dc_read_srom(sc, sc->dc_romwidth);
189896f2e892SBill Paul 		break;
18991e2e70b1SJohn Baldwin 	case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985):
19001e2e70b1SJohn Baldwin 	case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511):
19011e2e70b1SJohn Baldwin 	case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513):
19021e2e70b1SJohn Baldwin 	case DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD):
19031e2e70b1SJohn Baldwin 	case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_FA511):
19041e2e70b1SJohn Baldwin 	case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500):
19051e2e70b1SJohn Baldwin 	case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX):
19061e2e70b1SJohn Baldwin 	case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242):
19071e2e70b1SJohn Baldwin 	case DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX):
19081e2e70b1SJohn Baldwin 	case DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T):
19091e2e70b1SJohn Baldwin 	case DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB):
19101e2e70b1SJohn Baldwin 	case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120):
19111e2e70b1SJohn Baldwin 	case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130):
191217762569SGleb Smirnoff 	case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08):
191317762569SGleb Smirnoff 	case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09):
191496f2e892SBill Paul 		sc->dc_type = DC_TYPE_AN985;
1915acc1bcccSMartin Blapp 		sc->dc_flags |= DC_64BIT_HASH;
191696f2e892SBill Paul 		sc->dc_flags |= DC_TX_USE_TX_INTR;
191796f2e892SBill Paul 		sc->dc_flags |= DC_TX_ADMTEK_WAR;
191896f2e892SBill Paul 		sc->dc_pmode = DC_PMODE_MII;
1919129eaf79SMartin Blapp 		/* Don't read SROM for - auto-loaded on reset */
192096f2e892SBill Paul 		break;
19211e2e70b1SJohn Baldwin 	case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713):
19221e2e70b1SJohn Baldwin 	case DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP):
192396f2e892SBill Paul 		if (revision < DC_REVISION_98713A) {
192496f2e892SBill Paul 			sc->dc_type = DC_TYPE_98713;
192596f2e892SBill Paul 		}
1926318b02fdSBill Paul 		if (revision >= DC_REVISION_98713A) {
192796f2e892SBill Paul 			sc->dc_type = DC_TYPE_98713A;
1928318b02fdSBill Paul 			sc->dc_flags |= DC_21143_NWAY;
1929318b02fdSBill Paul 		}
1930318b02fdSBill Paul 		sc->dc_flags |= DC_REDUCED_MII_POLL;
193196f2e892SBill Paul 		sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR;
193296f2e892SBill Paul 		break;
19331e2e70b1SJohn Baldwin 	case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5):
19341e2e70b1SJohn Baldwin 	case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217):
193579d11e09SBill Paul 		/*
193679d11e09SBill Paul 		 * Macronix MX98715AEC-C/D/E parts have only a
193779d11e09SBill Paul 		 * 128-bit hash table. We need to deal with these
193879d11e09SBill Paul 		 * in the same manner as the PNIC II so that we
193979d11e09SBill Paul 		 * get the right number of bits out of the
194079d11e09SBill Paul 		 * CRC routine.
194179d11e09SBill Paul 		 */
194279d11e09SBill Paul 		if (revision >= DC_REVISION_98715AEC_C &&
194379d11e09SBill Paul 		    revision < DC_REVISION_98725)
194479d11e09SBill Paul 			sc->dc_flags |= DC_128BIT_HASH;
194596f2e892SBill Paul 		sc->dc_type = DC_TYPE_987x5;
194696f2e892SBill Paul 		sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR;
1947318b02fdSBill Paul 		sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY;
194896f2e892SBill Paul 		break;
19491e2e70b1SJohn Baldwin 	case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727):
1950ead7cde9SBill Paul 		sc->dc_type = DC_TYPE_987x5;
1951ead7cde9SBill Paul 		sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR;
1952ead7cde9SBill Paul 		sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY;
1953ead7cde9SBill Paul 		break;
19541e2e70b1SJohn Baldwin 	case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115):
195596f2e892SBill Paul 		sc->dc_type = DC_TYPE_PNICII;
195679d11e09SBill Paul 		sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR | DC_128BIT_HASH;
1957318b02fdSBill Paul 		sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY;
195896f2e892SBill Paul 		break;
19591e2e70b1SJohn Baldwin 	case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168):
196096f2e892SBill Paul 		sc->dc_type = DC_TYPE_PNIC;
196191cc2adbSBill Paul 		sc->dc_flags |= DC_TX_STORENFWD | DC_TX_INTR_ALWAYS;
196296f2e892SBill Paul 		sc->dc_flags |= DC_PNIC_RX_BUG_WAR;
196396f2e892SBill Paul 		sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT);
196496f2e892SBill Paul 		if (revision < DC_REVISION_82C169)
196596f2e892SBill Paul 			sc->dc_pmode = DC_PMODE_SYM;
196696f2e892SBill Paul 		break;
19671e2e70b1SJohn Baldwin 	case DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A):
196896f2e892SBill Paul 		sc->dc_type = DC_TYPE_ASIX;
196996f2e892SBill Paul 		sc->dc_flags |= DC_TX_USE_TX_INTR | DC_TX_INTR_FIRSTFRAG;
197096f2e892SBill Paul 		sc->dc_flags |= DC_REDUCED_MII_POLL;
197196f2e892SBill Paul 		sc->dc_pmode = DC_PMODE_MII;
197296f2e892SBill Paul 		break;
19731e2e70b1SJohn Baldwin 	case DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201):
1974feb78939SJonathan Chen 		sc->dc_type = DC_TYPE_XIRCOM;
19752dfc960aSLuigi Rizzo 		sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE |
19762dfc960aSLuigi Rizzo 				DC_TX_ALIGN;
1977feb78939SJonathan Chen 		/*
1978feb78939SJonathan Chen 		 * We don't actually need to coalesce, but we're doing
1979feb78939SJonathan Chen 		 * it to obtain a double word aligned buffer.
19802dfc960aSLuigi Rizzo 		 * The DC_TX_COALESCE flag is required.
1981feb78939SJonathan Chen 		 */
19823097aa70SWarner Losh 		sc->dc_pmode = DC_PMODE_MII;
1983feb78939SJonathan Chen 		break;
19841e2e70b1SJohn Baldwin 	case DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112):
19851af8bec7SBill Paul 		sc->dc_type = DC_TYPE_CONEXANT;
19861af8bec7SBill Paul 		sc->dc_flags |= DC_TX_INTR_ALWAYS;
19871af8bec7SBill Paul 		sc->dc_flags |= DC_REDUCED_MII_POLL;
19881af8bec7SBill Paul 		sc->dc_pmode = DC_PMODE_MII;
19893097aa70SWarner Losh 		dc_read_srom(sc, sc->dc_romwidth);
19901af8bec7SBill Paul 		break;
199196f2e892SBill Paul 	default:
19921e2e70b1SJohn Baldwin 		device_printf(dev, "unknown device: %x\n",
19931e2e70b1SJohn Baldwin 		    sc->dc_info->dc_devid);
199496f2e892SBill Paul 		break;
199596f2e892SBill Paul 	}
199696f2e892SBill Paul 
199796f2e892SBill Paul 	/* Save the cache line size. */
199888d739dcSBill Paul 	if (DC_IS_DAVICOM(sc))
199988d739dcSBill Paul 		sc->dc_cachesize = 0;
200088d739dcSBill Paul 	else
20011e2e70b1SJohn Baldwin 		sc->dc_cachesize = pci_get_cachelnsz(dev);
200296f2e892SBill Paul 
200396f2e892SBill Paul 	/* Reset the adapter. */
200496f2e892SBill Paul 	dc_reset(sc);
200596f2e892SBill Paul 
200696f2e892SBill Paul 	/* Take 21143 out of snooze mode */
2007feb78939SJonathan Chen 	if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) {
200896f2e892SBill Paul 		command = pci_read_config(dev, DC_PCI_CFDD, 4);
200996f2e892SBill Paul 		command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE);
201096f2e892SBill Paul 		pci_write_config(dev, DC_PCI_CFDD, command, 4);
201196f2e892SBill Paul 	}
201296f2e892SBill Paul 
201396f2e892SBill Paul 	/*
201496f2e892SBill Paul 	 * Try to learn something about the supported media.
201596f2e892SBill Paul 	 * We know that ASIX and ADMtek and Davicom devices
201696f2e892SBill Paul 	 * will *always* be using MII media, so that's a no-brainer.
201796f2e892SBill Paul 	 * The tricky ones are the Macronix/PNIC II and the
201896f2e892SBill Paul 	 * Intel 21143.
201996f2e892SBill Paul 	 */
20205c1cfac4SBill Paul 	if (DC_IS_INTEL(sc))
20215c1cfac4SBill Paul 		dc_parse_21143_srom(sc);
20225c1cfac4SBill Paul 	else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) {
202396f2e892SBill Paul 		if (sc->dc_type == DC_TYPE_98713)
202496f2e892SBill Paul 			sc->dc_pmode = DC_PMODE_MII;
202596f2e892SBill Paul 		else
202696f2e892SBill Paul 			sc->dc_pmode = DC_PMODE_SYM;
202796f2e892SBill Paul 	} else if (!sc->dc_pmode)
202896f2e892SBill Paul 		sc->dc_pmode = DC_PMODE_MII;
202996f2e892SBill Paul 
203096f2e892SBill Paul 	/*
203196f2e892SBill Paul 	 * Get station address from the EEPROM.
203296f2e892SBill Paul 	 */
203396f2e892SBill Paul 	switch(sc->dc_type) {
203496f2e892SBill Paul 	case DC_TYPE_98713:
203596f2e892SBill Paul 	case DC_TYPE_98713A:
203696f2e892SBill Paul 	case DC_TYPE_987x5:
203796f2e892SBill Paul 	case DC_TYPE_PNICII:
203896f2e892SBill Paul 		dc_read_eeprom(sc, (caddr_t)&mac_offset,
203996f2e892SBill Paul 		    (DC_EE_NODEADDR_OFFSET / 2), 1, 0);
204096f2e892SBill Paul 		dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0);
204196f2e892SBill Paul 		break;
204296f2e892SBill Paul 	case DC_TYPE_PNIC:
204396f2e892SBill Paul 		dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1);
204496f2e892SBill Paul 		break;
204596f2e892SBill Paul 	case DC_TYPE_DM9102:
2046ec6a7299SMaxime Henrion 		dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2047ec6a7299SMaxime Henrion #ifdef __sparc64__
2048ec6a7299SMaxime Henrion 		/*
2049ec6a7299SMaxime Henrion 		 * If this is an onboard dc(4) the station address read from
2050802cab03SMarius Strobl 		 * the EEPROM is all zero and we have to get it from the FCode.
2051ec6a7299SMaxime Henrion 		 */
2052802cab03SMarius Strobl 		if (eaddr[0] == 0 && (eaddr[1] & ~0xffff) == 0)
20538069c79dSRuslan Ermilov 			OF_getetheraddr(dev, (caddr_t)&eaddr);
2054ec6a7299SMaxime Henrion #endif
2055ec6a7299SMaxime Henrion 		break;
205696f2e892SBill Paul 	case DC_TYPE_21143:
205796f2e892SBill Paul 	case DC_TYPE_ASIX:
205896f2e892SBill Paul 		dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
205996f2e892SBill Paul 		break;
206096f2e892SBill Paul 	case DC_TYPE_AL981:
206196f2e892SBill Paul 	case DC_TYPE_AN985:
20622e3d4b79SPyun YongHyeon 		reg = CSR_READ_4(sc, DC_AL_PAR0);
20632e3d4b79SPyun YongHyeon 		mac = (uint8_t *)&eaddr[0];
20642e3d4b79SPyun YongHyeon 		mac[0] = (reg >> 0) & 0xff;
20652e3d4b79SPyun YongHyeon 		mac[1] = (reg >> 8) & 0xff;
20662e3d4b79SPyun YongHyeon 		mac[2] = (reg >> 16) & 0xff;
20672e3d4b79SPyun YongHyeon 		mac[3] = (reg >> 24) & 0xff;
20682e3d4b79SPyun YongHyeon 		reg = CSR_READ_4(sc, DC_AL_PAR1);
20692e3d4b79SPyun YongHyeon 		mac[4] = (reg >> 0) & 0xff;
20702e3d4b79SPyun YongHyeon 		mac[5] = (reg >> 8) & 0xff;
207196f2e892SBill Paul 		break;
20721af8bec7SBill Paul 	case DC_TYPE_CONEXANT:
20730934f18aSMaxime Henrion 		bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr,
20740934f18aSMaxime Henrion 		    ETHER_ADDR_LEN);
20751af8bec7SBill Paul 		break;
2076feb78939SJonathan Chen 	case DC_TYPE_XIRCOM:
20770934f18aSMaxime Henrion 		/* The MAC comes from the CIS. */
2078e7b01d07SWarner Losh 		mac = pci_get_ether(dev);
2079e7b01d07SWarner Losh 		if (!mac) {
2080e7b01d07SWarner Losh 			device_printf(dev, "No station address in CIS!\n");
2081608654d4SNate Lawson 			error = ENXIO;
2082e7b01d07SWarner Losh 			goto fail;
2083e7b01d07SWarner Losh 		}
2084e7b01d07SWarner Losh 		bcopy(mac, eaddr, ETHER_ADDR_LEN);
2085feb78939SJonathan Chen 		break;
208696f2e892SBill Paul 	default:
208796f2e892SBill Paul 		dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
208896f2e892SBill Paul 		break;
208996f2e892SBill Paul 	}
209096f2e892SBill Paul 
209156e5e7aeSMaxime Henrion 	/* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */
2092b1d16143SMarius Strobl 	error = bus_dma_tag_create(bus_get_dma_tag(dev), PAGE_SIZE, 0,
2093b1d16143SMarius Strobl 	    BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
2094b1d16143SMarius Strobl 	    sizeof(struct dc_list_data), 1, sizeof(struct dc_list_data),
2095b1d16143SMarius Strobl 	    0, NULL, NULL, &sc->dc_ltag);
209656e5e7aeSMaxime Henrion 	if (error) {
209722f6205dSJohn Baldwin 		device_printf(dev, "failed to allocate busdma tag\n");
209856e5e7aeSMaxime Henrion 		error = ENXIO;
209956e5e7aeSMaxime Henrion 		goto fail;
210056e5e7aeSMaxime Henrion 	}
210156e5e7aeSMaxime Henrion 	error = bus_dmamem_alloc(sc->dc_ltag, (void **)&sc->dc_ldata,
2102aafb3ebbSMaxime Henrion 	    BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->dc_lmap);
210356e5e7aeSMaxime Henrion 	if (error) {
210422f6205dSJohn Baldwin 		device_printf(dev, "failed to allocate DMA safe memory\n");
210556e5e7aeSMaxime Henrion 		error = ENXIO;
210656e5e7aeSMaxime Henrion 		goto fail;
210756e5e7aeSMaxime Henrion 	}
210856e5e7aeSMaxime Henrion 	error = bus_dmamap_load(sc->dc_ltag, sc->dc_lmap, sc->dc_ldata,
210956e5e7aeSMaxime Henrion 	    sizeof(struct dc_list_data), dc_dma_map_addr, &sc->dc_laddr,
211056e5e7aeSMaxime Henrion 	    BUS_DMA_NOWAIT);
211156e5e7aeSMaxime Henrion 	if (error) {
211222f6205dSJohn Baldwin 		device_printf(dev, "cannot get address of the descriptors\n");
211356e5e7aeSMaxime Henrion 		error = ENXIO;
211456e5e7aeSMaxime Henrion 		goto fail;
211556e5e7aeSMaxime Henrion 	}
211696f2e892SBill Paul 
211756e5e7aeSMaxime Henrion 	/*
211856e5e7aeSMaxime Henrion 	 * Allocate a busdma tag and DMA safe memory for the multicast
211956e5e7aeSMaxime Henrion 	 * setup frame.
212056e5e7aeSMaxime Henrion 	 */
2121b1d16143SMarius Strobl 	error = bus_dma_tag_create(bus_get_dma_tag(dev), PAGE_SIZE, 0,
2122b1d16143SMarius Strobl 	    BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
2123b1d16143SMarius Strobl 	    DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1, DC_SFRAME_LEN + DC_MIN_FRAMELEN,
2124b1d16143SMarius Strobl 	    0, NULL, NULL, &sc->dc_stag);
212556e5e7aeSMaxime Henrion 	if (error) {
212622f6205dSJohn Baldwin 		device_printf(dev, "failed to allocate busdma tag\n");
212756e5e7aeSMaxime Henrion 		error = ENXIO;
212856e5e7aeSMaxime Henrion 		goto fail;
212956e5e7aeSMaxime Henrion 	}
213056e5e7aeSMaxime Henrion 	error = bus_dmamem_alloc(sc->dc_stag, (void **)&sc->dc_cdata.dc_sbuf,
213156e5e7aeSMaxime Henrion 	    BUS_DMA_NOWAIT, &sc->dc_smap);
213256e5e7aeSMaxime Henrion 	if (error) {
213322f6205dSJohn Baldwin 		device_printf(dev, "failed to allocate DMA safe memory\n");
213456e5e7aeSMaxime Henrion 		error = ENXIO;
213556e5e7aeSMaxime Henrion 		goto fail;
213656e5e7aeSMaxime Henrion 	}
213756e5e7aeSMaxime Henrion 	error = bus_dmamap_load(sc->dc_stag, sc->dc_smap, sc->dc_cdata.dc_sbuf,
213856e5e7aeSMaxime Henrion 	    DC_SFRAME_LEN, dc_dma_map_addr, &sc->dc_saddr, BUS_DMA_NOWAIT);
213956e5e7aeSMaxime Henrion 	if (error) {
214022f6205dSJohn Baldwin 		device_printf(dev, "cannot get address of the descriptors\n");
214196f2e892SBill Paul 		error = ENXIO;
214296f2e892SBill Paul 		goto fail;
214396f2e892SBill Paul 	}
214496f2e892SBill Paul 
214556e5e7aeSMaxime Henrion 	/* Allocate a busdma tag for mbufs. */
2146b1d16143SMarius Strobl 	error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
2147b1d16143SMarius Strobl 	    BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
2148ebc284ccSMarius Strobl 	    MCLBYTES * DC_MAXFRAGS, DC_MAXFRAGS, MCLBYTES,
2149c1b677aaSScott Long 	    0, NULL, NULL, &sc->dc_mtag);
215056e5e7aeSMaxime Henrion 	if (error) {
215122f6205dSJohn Baldwin 		device_printf(dev, "failed to allocate busdma tag\n");
215256e5e7aeSMaxime Henrion 		error = ENXIO;
215356e5e7aeSMaxime Henrion 		goto fail;
215456e5e7aeSMaxime Henrion 	}
215556e5e7aeSMaxime Henrion 
215656e5e7aeSMaxime Henrion 	/* Create the TX/RX busdma maps. */
215756e5e7aeSMaxime Henrion 	for (i = 0; i < DC_TX_LIST_CNT; i++) {
215856e5e7aeSMaxime Henrion 		error = bus_dmamap_create(sc->dc_mtag, 0,
215956e5e7aeSMaxime Henrion 		    &sc->dc_cdata.dc_tx_map[i]);
216056e5e7aeSMaxime Henrion 		if (error) {
216122f6205dSJohn Baldwin 			device_printf(dev, "failed to init TX ring\n");
216256e5e7aeSMaxime Henrion 			error = ENXIO;
216356e5e7aeSMaxime Henrion 			goto fail;
216456e5e7aeSMaxime Henrion 		}
216556e5e7aeSMaxime Henrion 	}
216656e5e7aeSMaxime Henrion 	for (i = 0; i < DC_RX_LIST_CNT; i++) {
216756e5e7aeSMaxime Henrion 		error = bus_dmamap_create(sc->dc_mtag, 0,
216856e5e7aeSMaxime Henrion 		    &sc->dc_cdata.dc_rx_map[i]);
216956e5e7aeSMaxime Henrion 		if (error) {
217022f6205dSJohn Baldwin 			device_printf(dev, "failed to init RX ring\n");
217156e5e7aeSMaxime Henrion 			error = ENXIO;
217256e5e7aeSMaxime Henrion 			goto fail;
217356e5e7aeSMaxime Henrion 		}
217456e5e7aeSMaxime Henrion 	}
217556e5e7aeSMaxime Henrion 	error = bus_dmamap_create(sc->dc_mtag, 0, &sc->dc_sparemap);
217656e5e7aeSMaxime Henrion 	if (error) {
217722f6205dSJohn Baldwin 		device_printf(dev, "failed to init RX ring\n");
217856e5e7aeSMaxime Henrion 		error = ENXIO;
217956e5e7aeSMaxime Henrion 		goto fail;
218056e5e7aeSMaxime Henrion 	}
218196f2e892SBill Paul 
2182fc74a9f9SBrooks Davis 	ifp = sc->dc_ifp = if_alloc(IFT_ETHER);
2183fc74a9f9SBrooks Davis 	if (ifp == NULL) {
218422f6205dSJohn Baldwin 		device_printf(dev, "can not if_alloc()\n");
2185fc74a9f9SBrooks Davis 		error = ENOSPC;
2186fc74a9f9SBrooks Davis 		goto fail;
2187fc74a9f9SBrooks Davis 	}
218896f2e892SBill Paul 	ifp->if_softc = sc;
21899bf40edeSBrooks Davis 	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
21903d57a2e5SBrian Feldman 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
219196f2e892SBill Paul 	ifp->if_ioctl = dc_ioctl;
219296f2e892SBill Paul 	ifp->if_start = dc_start;
219396f2e892SBill Paul 	ifp->if_init = dc_init;
2194cbaf877fSBrian Feldman 	IFQ_SET_MAXLEN(&ifp->if_snd, DC_TX_LIST_CNT - 1);
2195cbaf877fSBrian Feldman 	ifp->if_snd.ifq_drv_maxlen = DC_TX_LIST_CNT - 1;
2196cbaf877fSBrian Feldman 	IFQ_SET_READY(&ifp->if_snd);
219796f2e892SBill Paul 
219896f2e892SBill Paul 	/*
21995c1cfac4SBill Paul 	 * Do MII setup. If this is a 21143, check for a PHY on the
22005c1cfac4SBill Paul 	 * MII bus after applying any necessary fixups to twiddle the
22015c1cfac4SBill Paul 	 * GPIO bits. If we don't end up finding a PHY, restore the
22025c1cfac4SBill Paul 	 * old selection (SIA only or SIA/SYM) and attach the dcphy
22035c1cfac4SBill Paul 	 * driver instead.
220496f2e892SBill Paul 	 */
22055c1cfac4SBill Paul 	if (DC_IS_INTEL(sc)) {
22065c1cfac4SBill Paul 		dc_apply_fixup(sc, IFM_AUTO);
22075c1cfac4SBill Paul 		tmp = sc->dc_pmode;
22085c1cfac4SBill Paul 		sc->dc_pmode = DC_PMODE_MII;
22095c1cfac4SBill Paul 	}
22105c1cfac4SBill Paul 
22116d431b17SWarner Losh 	/*
22126d431b17SWarner Losh 	 * Setup General Purpose port mode and data so the tulip can talk
22136d431b17SWarner Losh 	 * to the MII.  This needs to be done before mii_phy_probe so that
22146d431b17SWarner Losh 	 * we can actually see them.
22156d431b17SWarner Losh 	 */
22166d431b17SWarner Losh 	if (DC_IS_XIRCOM(sc)) {
22176d431b17SWarner Losh 		CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN |
22186d431b17SWarner Losh 		    DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
22196d431b17SWarner Losh 		DELAY(10);
22206d431b17SWarner Losh 		CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN |
22216d431b17SWarner Losh 		    DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
22226d431b17SWarner Losh 		DELAY(10);
22236d431b17SWarner Losh 	}
22246d431b17SWarner Losh 
222596f2e892SBill Paul 	error = mii_phy_probe(dev, &sc->dc_miibus,
222696f2e892SBill Paul 	    dc_ifmedia_upd, dc_ifmedia_sts);
222796f2e892SBill Paul 
222896f2e892SBill Paul 	if (error && DC_IS_INTEL(sc)) {
22295c1cfac4SBill Paul 		sc->dc_pmode = tmp;
22305c1cfac4SBill Paul 		if (sc->dc_pmode != DC_PMODE_SIA)
223196f2e892SBill Paul 			sc->dc_pmode = DC_PMODE_SYM;
2232042c8f6eSBill Paul 		sc->dc_flags |= DC_21143_NWAY;
223396f2e892SBill Paul 		mii_phy_probe(dev, &sc->dc_miibus,
223496f2e892SBill Paul 		    dc_ifmedia_upd, dc_ifmedia_sts);
223578999dd1SBill Paul 		/*
223678999dd1SBill Paul 		 * For non-MII cards, we need to have the 21143
223778999dd1SBill Paul 		 * drive the LEDs. Except there are some systems
223878999dd1SBill Paul 		 * like the NEC VersaPro NoteBook PC which have no
223978999dd1SBill Paul 		 * LEDs, and twiddling these bits has adverse effects
224078999dd1SBill Paul 		 * on them. (I.e. you suddenly can't get a link.)
224178999dd1SBill Paul 		 */
22421e2e70b1SJohn Baldwin 		if (!(pci_get_subvendor(dev) == 0x1033 &&
22431e2e70b1SJohn Baldwin 		    pci_get_subdevice(dev) == 0x8028))
224478999dd1SBill Paul 			sc->dc_flags |= DC_TULIP_LEDS;
224596f2e892SBill Paul 		error = 0;
224696f2e892SBill Paul 	}
224796f2e892SBill Paul 
224896f2e892SBill Paul 	if (error) {
224922f6205dSJohn Baldwin 		device_printf(dev, "MII without any PHY!\n");
225096f2e892SBill Paul 		goto fail;
225196f2e892SBill Paul 	}
225296f2e892SBill Paul 
2253028a8491SMartin Blapp 	if (DC_IS_ADMTEK(sc)) {
2254028a8491SMartin Blapp 		/*
2255028a8491SMartin Blapp 		 * Set automatic TX underrun recovery for the ADMtek chips
2256028a8491SMartin Blapp 		 */
2257028a8491SMartin Blapp 		DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR);
2258028a8491SMartin Blapp 	}
2259028a8491SMartin Blapp 
226096f2e892SBill Paul 	/*
2261db40c1aeSDoug Ambrisko 	 * Tell the upper layer(s) we support long frames.
2262db40c1aeSDoug Ambrisko 	 */
2263db40c1aeSDoug Ambrisko 	ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
22649ef8b520SSam Leffler 	ifp->if_capabilities |= IFCAP_VLAN_MTU;
226540929967SGleb Smirnoff 	ifp->if_capenable = ifp->if_capabilities;
2266e695984eSRuslan Ermilov #ifdef DEVICE_POLLING
2267e695984eSRuslan Ermilov 	ifp->if_capabilities |= IFCAP_POLLING;
2268e695984eSRuslan Ermilov #endif
2269db40c1aeSDoug Ambrisko 
2270c8b27acaSJohn Baldwin 	callout_init_mtx(&sc->dc_stat_ch, &sc->dc_mtx, 0);
2271b1d16143SMarius Strobl 	callout_init_mtx(&sc->dc_wdog_ch, &sc->dc_mtx, 0);
227296f2e892SBill Paul 
2273608654d4SNate Lawson 	/*
2274608654d4SNate Lawson 	 * Call MI attach routine.
2275608654d4SNate Lawson 	 */
22768df1ebe9SMarcel Moolenaar 	ether_ifattach(ifp, (caddr_t)eaddr);
2277608654d4SNate Lawson 
227854f1f1d1SNate Lawson 	/* Hook interrupt last to avoid having to lock softc */
2279c8b27acaSJohn Baldwin 	error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | INTR_MPSAFE,
2280ef544f63SPaolo Pisati 	    NULL, dc_intr, sc, &sc->dc_intrhand);
2281608654d4SNate Lawson 
2282608654d4SNate Lawson 	if (error) {
228322f6205dSJohn Baldwin 		device_printf(dev, "couldn't set up irq\n");
2284693f4477SNate Lawson 		ether_ifdetach(ifp);
228554f1f1d1SNate Lawson 		goto fail;
2286608654d4SNate Lawson 	}
2287510a809eSMike Smith 
228896f2e892SBill Paul fail:
228954f1f1d1SNate Lawson 	if (error)
229054f1f1d1SNate Lawson 		dc_detach(dev);
229196f2e892SBill Paul 	return (error);
229296f2e892SBill Paul }
229396f2e892SBill Paul 
2294693f4477SNate Lawson /*
2295693f4477SNate Lawson  * Shutdown hardware and free up resources. This can be called any
2296693f4477SNate Lawson  * time after the mutex has been initialized. It is called in both
2297693f4477SNate Lawson  * the error case in attach and the normal detach case so it needs
2298693f4477SNate Lawson  * to be careful about only freeing resources that have actually been
2299693f4477SNate Lawson  * allocated.
2300693f4477SNate Lawson  */
2301e3d2833aSAlfred Perlstein static int
23020934f18aSMaxime Henrion dc_detach(device_t dev)
230396f2e892SBill Paul {
230496f2e892SBill Paul 	struct dc_softc *sc;
230596f2e892SBill Paul 	struct ifnet *ifp;
23065c1cfac4SBill Paul 	struct dc_mediainfo *m;
230756e5e7aeSMaxime Henrion 	int i;
230896f2e892SBill Paul 
230996f2e892SBill Paul 	sc = device_get_softc(dev);
231059f47d29SJohn Baldwin 	KASSERT(mtx_initialized(&sc->dc_mtx), ("dc mutex not initialized"));
2311d1ce9105SBill Paul 
2312fc74a9f9SBrooks Davis 	ifp = sc->dc_ifp;
231396f2e892SBill Paul 
231440929967SGleb Smirnoff #ifdef DEVICE_POLLING
231540929967SGleb Smirnoff 	if (ifp->if_capenable & IFCAP_POLLING)
231640929967SGleb Smirnoff 		ether_poll_deregister(ifp);
231740929967SGleb Smirnoff #endif
231840929967SGleb Smirnoff 
2319693f4477SNate Lawson 	/* These should only be active if attach succeeded */
2320214073e5SWarner Losh 	if (device_is_attached(dev)) {
2321c8b27acaSJohn Baldwin 		DC_LOCK(sc);
232296f2e892SBill Paul 		dc_stop(sc);
2323c8b27acaSJohn Baldwin 		DC_UNLOCK(sc);
2324c8b27acaSJohn Baldwin 		callout_drain(&sc->dc_stat_ch);
2325b1d16143SMarius Strobl 		callout_drain(&sc->dc_wdog_ch);
23269ef8b520SSam Leffler 		ether_ifdetach(ifp);
2327693f4477SNate Lawson 	}
2328693f4477SNate Lawson 	if (sc->dc_miibus)
232996f2e892SBill Paul 		device_delete_child(dev, sc->dc_miibus);
233054f1f1d1SNate Lawson 	bus_generic_detach(dev);
233196f2e892SBill Paul 
233254f1f1d1SNate Lawson 	if (sc->dc_intrhand)
233396f2e892SBill Paul 		bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand);
233454f1f1d1SNate Lawson 	if (sc->dc_irq)
233596f2e892SBill Paul 		bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
233654f1f1d1SNate Lawson 	if (sc->dc_res)
233796f2e892SBill Paul 		bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
233896f2e892SBill Paul 
23396a3033a8SWarner Losh 	if (ifp)
23406a3033a8SWarner Losh 		if_free(ifp);
23416a3033a8SWarner Losh 
234256e5e7aeSMaxime Henrion 	if (sc->dc_cdata.dc_sbuf != NULL)
234356e5e7aeSMaxime Henrion 		bus_dmamem_free(sc->dc_stag, sc->dc_cdata.dc_sbuf, sc->dc_smap);
234456e5e7aeSMaxime Henrion 	if (sc->dc_ldata != NULL)
234556e5e7aeSMaxime Henrion 		bus_dmamem_free(sc->dc_ltag, sc->dc_ldata, sc->dc_lmap);
23464f867c2dSGiorgos Keramidas 	if (sc->dc_mtag) {
234756e5e7aeSMaxime Henrion 		for (i = 0; i < DC_TX_LIST_CNT; i++)
23484f867c2dSGiorgos Keramidas 			if (sc->dc_cdata.dc_tx_map[i] != NULL)
23494f867c2dSGiorgos Keramidas 				bus_dmamap_destroy(sc->dc_mtag,
23504f867c2dSGiorgos Keramidas 				    sc->dc_cdata.dc_tx_map[i]);
235156e5e7aeSMaxime Henrion 		for (i = 0; i < DC_RX_LIST_CNT; i++)
23524f867c2dSGiorgos Keramidas 			if (sc->dc_cdata.dc_rx_map[i] != NULL)
23534f867c2dSGiorgos Keramidas 				bus_dmamap_destroy(sc->dc_mtag,
23544f867c2dSGiorgos Keramidas 				    sc->dc_cdata.dc_rx_map[i]);
235556e5e7aeSMaxime Henrion 		bus_dmamap_destroy(sc->dc_mtag, sc->dc_sparemap);
23564f867c2dSGiorgos Keramidas 	}
235756e5e7aeSMaxime Henrion 	if (sc->dc_stag)
235856e5e7aeSMaxime Henrion 		bus_dma_tag_destroy(sc->dc_stag);
235956e5e7aeSMaxime Henrion 	if (sc->dc_mtag)
236056e5e7aeSMaxime Henrion 		bus_dma_tag_destroy(sc->dc_mtag);
236156e5e7aeSMaxime Henrion 	if (sc->dc_ltag)
236256e5e7aeSMaxime Henrion 		bus_dma_tag_destroy(sc->dc_ltag);
236356e5e7aeSMaxime Henrion 
236496f2e892SBill Paul 	free(sc->dc_pnic_rx_buf, M_DEVBUF);
236596f2e892SBill Paul 
23665c1cfac4SBill Paul 	while (sc->dc_mi != NULL) {
23675c1cfac4SBill Paul 		m = sc->dc_mi->dc_next;
23685c1cfac4SBill Paul 		free(sc->dc_mi, M_DEVBUF);
23695c1cfac4SBill Paul 		sc->dc_mi = m;
23705c1cfac4SBill Paul 	}
23717efff076SWarner Losh 	free(sc->dc_srom, M_DEVBUF);
23725c1cfac4SBill Paul 
2373d1ce9105SBill Paul 	mtx_destroy(&sc->dc_mtx);
237496f2e892SBill Paul 
237596f2e892SBill Paul 	return (0);
237696f2e892SBill Paul }
237796f2e892SBill Paul 
237896f2e892SBill Paul /*
237996f2e892SBill Paul  * Initialize the transmit descriptors.
238096f2e892SBill Paul  */
2381e3d2833aSAlfred Perlstein static int
23820934f18aSMaxime Henrion dc_list_tx_init(struct dc_softc *sc)
238396f2e892SBill Paul {
238496f2e892SBill Paul 	struct dc_chain_data *cd;
238596f2e892SBill Paul 	struct dc_list_data *ld;
238601faf54bSLuigi Rizzo 	int i, nexti;
238796f2e892SBill Paul 
238896f2e892SBill Paul 	cd = &sc->dc_cdata;
238996f2e892SBill Paul 	ld = sc->dc_ldata;
239096f2e892SBill Paul 	for (i = 0; i < DC_TX_LIST_CNT; i++) {
2391b3811c95SMaxime Henrion 		if (i == DC_TX_LIST_CNT - 1)
2392b3811c95SMaxime Henrion 			nexti = 0;
2393b3811c95SMaxime Henrion 		else
2394b3811c95SMaxime Henrion 			nexti = i + 1;
2395af4358c7SMaxime Henrion 		ld->dc_tx_list[i].dc_next = htole32(DC_TXDESC(sc, nexti));
239696f2e892SBill Paul 		cd->dc_tx_chain[i] = NULL;
239796f2e892SBill Paul 		ld->dc_tx_list[i].dc_data = 0;
239896f2e892SBill Paul 		ld->dc_tx_list[i].dc_ctl = 0;
239996f2e892SBill Paul 	}
240096f2e892SBill Paul 
240196f2e892SBill Paul 	cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0;
240256e5e7aeSMaxime Henrion 	bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap,
240356e5e7aeSMaxime Henrion 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
240496f2e892SBill Paul 	return (0);
240596f2e892SBill Paul }
240696f2e892SBill Paul 
240796f2e892SBill Paul 
240896f2e892SBill Paul /*
240996f2e892SBill Paul  * Initialize the RX descriptors and allocate mbufs for them. Note that
241096f2e892SBill Paul  * we arrange the descriptors in a closed ring, so that the last descriptor
241196f2e892SBill Paul  * points back to the first.
241296f2e892SBill Paul  */
2413e3d2833aSAlfred Perlstein static int
24140934f18aSMaxime Henrion dc_list_rx_init(struct dc_softc *sc)
241596f2e892SBill Paul {
241696f2e892SBill Paul 	struct dc_chain_data *cd;
241796f2e892SBill Paul 	struct dc_list_data *ld;
241801faf54bSLuigi Rizzo 	int i, nexti;
241996f2e892SBill Paul 
242096f2e892SBill Paul 	cd = &sc->dc_cdata;
242196f2e892SBill Paul 	ld = sc->dc_ldata;
242296f2e892SBill Paul 
242396f2e892SBill Paul 	for (i = 0; i < DC_RX_LIST_CNT; i++) {
242456e5e7aeSMaxime Henrion 		if (dc_newbuf(sc, i, 1) != 0)
242596f2e892SBill Paul 			return (ENOBUFS);
2426b3811c95SMaxime Henrion 		if (i == DC_RX_LIST_CNT - 1)
2427b3811c95SMaxime Henrion 			nexti = 0;
2428b3811c95SMaxime Henrion 		else
2429b3811c95SMaxime Henrion 			nexti = i + 1;
2430af4358c7SMaxime Henrion 		ld->dc_rx_list[i].dc_next = htole32(DC_RXDESC(sc, nexti));
243196f2e892SBill Paul 	}
243296f2e892SBill Paul 
243396f2e892SBill Paul 	cd->dc_rx_prod = 0;
243456e5e7aeSMaxime Henrion 	bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap,
243556e5e7aeSMaxime Henrion 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
243696f2e892SBill Paul 	return (0);
243796f2e892SBill Paul }
243896f2e892SBill Paul 
243996f2e892SBill Paul /*
244096f2e892SBill Paul  * Initialize an RX descriptor and attach an MBUF cluster.
244196f2e892SBill Paul  */
2442e3d2833aSAlfred Perlstein static int
244356e5e7aeSMaxime Henrion dc_newbuf(struct dc_softc *sc, int i, int alloc)
244496f2e892SBill Paul {
244556e5e7aeSMaxime Henrion 	struct mbuf *m_new;
244656e5e7aeSMaxime Henrion 	bus_dmamap_t tmp;
244782a67a70SMarius Strobl 	bus_dma_segment_t segs[1];
244882a67a70SMarius Strobl 	int error, nseg;
244996f2e892SBill Paul 
245056e5e7aeSMaxime Henrion 	if (alloc) {
245156e5e7aeSMaxime Henrion 		m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
245240129585SLuigi Rizzo 		if (m_new == NULL)
245396f2e892SBill Paul 			return (ENOBUFS);
245496f2e892SBill Paul 	} else {
245556e5e7aeSMaxime Henrion 		m_new = sc->dc_cdata.dc_rx_chain[i];
245696f2e892SBill Paul 		m_new->m_data = m_new->m_ext.ext_buf;
245796f2e892SBill Paul 	}
245856e5e7aeSMaxime Henrion 	m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
245996f2e892SBill Paul 	m_adj(m_new, sizeof(u_int64_t));
246096f2e892SBill Paul 
246196f2e892SBill Paul 	/*
246296f2e892SBill Paul 	 * If this is a PNIC chip, zero the buffer. This is part
246396f2e892SBill Paul 	 * of the workaround for the receive bug in the 82c168 and
246496f2e892SBill Paul 	 * 82c169 chips.
246596f2e892SBill Paul 	 */
246696f2e892SBill Paul 	if (sc->dc_flags & DC_PNIC_RX_BUG_WAR)
24670934f18aSMaxime Henrion 		bzero(mtod(m_new, char *), m_new->m_len);
246896f2e892SBill Paul 
246956e5e7aeSMaxime Henrion 	/* No need to remap the mbuf if we're reusing it. */
247056e5e7aeSMaxime Henrion 	if (alloc) {
247182a67a70SMarius Strobl 		error = bus_dmamap_load_mbuf_sg(sc->dc_mtag, sc->dc_sparemap,
247282a67a70SMarius Strobl 		    m_new, segs, &nseg, 0);
247356e5e7aeSMaxime Henrion 		if (error) {
247456e5e7aeSMaxime Henrion 			m_freem(m_new);
247556e5e7aeSMaxime Henrion 			return (error);
247656e5e7aeSMaxime Henrion 		}
2477ebc284ccSMarius Strobl 		KASSERT(nseg == 1,
2478ebc284ccSMarius Strobl 		    ("%s: wrong number of segments (%d)", __func__, nseg));
247982a67a70SMarius Strobl 		sc->dc_ldata->dc_rx_list[i].dc_data = htole32(segs->ds_addr);
248056e5e7aeSMaxime Henrion 		bus_dmamap_unload(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i]);
248156e5e7aeSMaxime Henrion 		tmp = sc->dc_cdata.dc_rx_map[i];
248256e5e7aeSMaxime Henrion 		sc->dc_cdata.dc_rx_map[i] = sc->dc_sparemap;
248356e5e7aeSMaxime Henrion 		sc->dc_sparemap = tmp;
248496f2e892SBill Paul 		sc->dc_cdata.dc_rx_chain[i] = m_new;
248556e5e7aeSMaxime Henrion 	}
248696f2e892SBill Paul 
2487af4358c7SMaxime Henrion 	sc->dc_ldata->dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN);
2488af4358c7SMaxime Henrion 	sc->dc_ldata->dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN);
248956e5e7aeSMaxime Henrion 	bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i],
249056e5e7aeSMaxime Henrion 	    BUS_DMASYNC_PREREAD);
249156e5e7aeSMaxime Henrion 	bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap,
249256e5e7aeSMaxime Henrion 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
249396f2e892SBill Paul 	return (0);
249496f2e892SBill Paul }
249596f2e892SBill Paul 
249696f2e892SBill Paul /*
249796f2e892SBill Paul  * Grrrrr.
249896f2e892SBill Paul  * The PNIC chip has a terrible bug in it that manifests itself during
249996f2e892SBill Paul  * periods of heavy activity. The exact mode of failure if difficult to
250096f2e892SBill Paul  * pinpoint: sometimes it only happens in promiscuous mode, sometimes it
250196f2e892SBill Paul  * will happen on slow machines. The bug is that sometimes instead of
250296f2e892SBill Paul  * uploading one complete frame during reception, it uploads what looks
250396f2e892SBill Paul  * like the entire contents of its FIFO memory. The frame we want is at
250496f2e892SBill Paul  * the end of the whole mess, but we never know exactly how much data has
250596f2e892SBill Paul  * been uploaded, so salvaging the frame is hard.
250696f2e892SBill Paul  *
250796f2e892SBill Paul  * There is only one way to do it reliably, and it's disgusting.
250896f2e892SBill Paul  * Here's what we know:
250996f2e892SBill Paul  *
251096f2e892SBill Paul  * - We know there will always be somewhere between one and three extra
251196f2e892SBill Paul  *   descriptors uploaded.
251296f2e892SBill Paul  *
251396f2e892SBill Paul  * - We know the desired received frame will always be at the end of the
251496f2e892SBill Paul  *   total data upload.
251596f2e892SBill Paul  *
251696f2e892SBill Paul  * - We know the size of the desired received frame because it will be
251796f2e892SBill Paul  *   provided in the length field of the status word in the last descriptor.
251896f2e892SBill Paul  *
251996f2e892SBill Paul  * Here's what we do:
252096f2e892SBill Paul  *
252196f2e892SBill Paul  * - When we allocate buffers for the receive ring, we bzero() them.
252296f2e892SBill Paul  *   This means that we know that the buffer contents should be all
252396f2e892SBill Paul  *   zeros, except for data uploaded by the chip.
252496f2e892SBill Paul  *
252596f2e892SBill Paul  * - We also force the PNIC chip to upload frames that include the
252696f2e892SBill Paul  *   ethernet CRC at the end.
252796f2e892SBill Paul  *
252896f2e892SBill Paul  * - We gather all of the bogus frame data into a single buffer.
252996f2e892SBill Paul  *
253096f2e892SBill Paul  * - We then position a pointer at the end of this buffer and scan
253196f2e892SBill Paul  *   backwards until we encounter the first non-zero byte of data.
253296f2e892SBill Paul  *   This is the end of the received frame. We know we will encounter
253396f2e892SBill Paul  *   some data at the end of the frame because the CRC will always be
253496f2e892SBill Paul  *   there, so even if the sender transmits a packet of all zeros,
253596f2e892SBill Paul  *   we won't be fooled.
253696f2e892SBill Paul  *
253796f2e892SBill Paul  * - We know the size of the actual received frame, so we subtract
253896f2e892SBill Paul  *   that value from the current pointer location. This brings us
253996f2e892SBill Paul  *   to the start of the actual received packet.
254096f2e892SBill Paul  *
254196f2e892SBill Paul  * - We copy this into an mbuf and pass it on, along with the actual
254296f2e892SBill Paul  *   frame length.
254396f2e892SBill Paul  *
254496f2e892SBill Paul  * The performance hit is tremendous, but it beats dropping frames all
254596f2e892SBill Paul  * the time.
254696f2e892SBill Paul  */
254796f2e892SBill Paul 
254896f2e892SBill Paul #define DC_WHOLEFRAME	(DC_RXSTAT_FIRSTFRAG | DC_RXSTAT_LASTFRAG)
2549e3d2833aSAlfred Perlstein static void
25500934f18aSMaxime Henrion dc_pnic_rx_bug_war(struct dc_softc *sc, int idx)
255196f2e892SBill Paul {
255296f2e892SBill Paul 	struct dc_desc *cur_rx;
255396f2e892SBill Paul 	struct dc_desc *c = NULL;
255496f2e892SBill Paul 	struct mbuf *m = NULL;
255596f2e892SBill Paul 	unsigned char *ptr;
255696f2e892SBill Paul 	int i, total_len;
255796f2e892SBill Paul 	u_int32_t rxstat = 0;
255896f2e892SBill Paul 
255996f2e892SBill Paul 	i = sc->dc_pnic_rx_bug_save;
256096f2e892SBill Paul 	cur_rx = &sc->dc_ldata->dc_rx_list[idx];
256196f2e892SBill Paul 	ptr = sc->dc_pnic_rx_buf;
25621edc4c46SMaxime Henrion 	bzero(ptr, DC_RXLEN * 5);
256396f2e892SBill Paul 
256496f2e892SBill Paul 	/* Copy all the bytes from the bogus buffers. */
256596f2e892SBill Paul 	while (1) {
256696f2e892SBill Paul 		c = &sc->dc_ldata->dc_rx_list[i];
2567af4358c7SMaxime Henrion 		rxstat = le32toh(c->dc_status);
256896f2e892SBill Paul 		m = sc->dc_cdata.dc_rx_chain[i];
256996f2e892SBill Paul 		bcopy(mtod(m, char *), ptr, DC_RXLEN);
257096f2e892SBill Paul 		ptr += DC_RXLEN;
257196f2e892SBill Paul 		/* If this is the last buffer, break out. */
257296f2e892SBill Paul 		if (i == idx || rxstat & DC_RXSTAT_LASTFRAG)
257396f2e892SBill Paul 			break;
257456e5e7aeSMaxime Henrion 		dc_newbuf(sc, i, 0);
257596f2e892SBill Paul 		DC_INC(i, DC_RX_LIST_CNT);
257696f2e892SBill Paul 	}
257796f2e892SBill Paul 
257896f2e892SBill Paul 	/* Find the length of the actual receive frame. */
257996f2e892SBill Paul 	total_len = DC_RXBYTES(rxstat);
258096f2e892SBill Paul 
258196f2e892SBill Paul 	/* Scan backwards until we hit a non-zero byte. */
258296f2e892SBill Paul 	while (*ptr == 0x00)
258396f2e892SBill Paul 		ptr--;
258496f2e892SBill Paul 
258596f2e892SBill Paul 	/* Round off. */
258696f2e892SBill Paul 	if ((uintptr_t)(ptr) & 0x3)
258796f2e892SBill Paul 		ptr -= 1;
258896f2e892SBill Paul 
258996f2e892SBill Paul 	/* Now find the start of the frame. */
259096f2e892SBill Paul 	ptr -= total_len;
259196f2e892SBill Paul 	if (ptr < sc->dc_pnic_rx_buf)
259296f2e892SBill Paul 		ptr = sc->dc_pnic_rx_buf;
259396f2e892SBill Paul 
259496f2e892SBill Paul 	/*
259596f2e892SBill Paul 	 * Now copy the salvaged frame to the last mbuf and fake up
259696f2e892SBill Paul 	 * the status word to make it look like a successful
259796f2e892SBill Paul 	 * frame reception.
259896f2e892SBill Paul 	 */
259956e5e7aeSMaxime Henrion 	dc_newbuf(sc, i, 0);
260096f2e892SBill Paul 	bcopy(ptr, mtod(m, char *), total_len);
2601af4358c7SMaxime Henrion 	cur_rx->dc_status = htole32(rxstat | DC_RXSTAT_FIRSTFRAG);
260296f2e892SBill Paul }
260396f2e892SBill Paul 
260496f2e892SBill Paul /*
260573bf949cSBill Paul  * This routine searches the RX ring for dirty descriptors in the
260673bf949cSBill Paul  * event that the rxeof routine falls out of sync with the chip's
260773bf949cSBill Paul  * current descriptor pointer. This may happen sometimes as a result
260873bf949cSBill Paul  * of a "no RX buffer available" condition that happens when the chip
260973bf949cSBill Paul  * consumes all of the RX buffers before the driver has a chance to
261073bf949cSBill Paul  * process the RX ring. This routine may need to be called more than
261173bf949cSBill Paul  * once to bring the driver back in sync with the chip, however we
261273bf949cSBill Paul  * should still be getting RX DONE interrupts to drive the search
261373bf949cSBill Paul  * for new packets in the RX ring, so we should catch up eventually.
261473bf949cSBill Paul  */
2615e3d2833aSAlfred Perlstein static int
26160934f18aSMaxime Henrion dc_rx_resync(struct dc_softc *sc)
261773bf949cSBill Paul {
261873bf949cSBill Paul 	struct dc_desc *cur_rx;
26190934f18aSMaxime Henrion 	int i, pos;
262073bf949cSBill Paul 
262173bf949cSBill Paul 	pos = sc->dc_cdata.dc_rx_prod;
262273bf949cSBill Paul 
262373bf949cSBill Paul 	for (i = 0; i < DC_RX_LIST_CNT; i++) {
262473bf949cSBill Paul 		cur_rx = &sc->dc_ldata->dc_rx_list[pos];
2625af4358c7SMaxime Henrion 		if (!(le32toh(cur_rx->dc_status) & DC_RXSTAT_OWN))
262673bf949cSBill Paul 			break;
262773bf949cSBill Paul 		DC_INC(pos, DC_RX_LIST_CNT);
262873bf949cSBill Paul 	}
262973bf949cSBill Paul 
263073bf949cSBill Paul 	/* If the ring really is empty, then just return. */
263173bf949cSBill Paul 	if (i == DC_RX_LIST_CNT)
263273bf949cSBill Paul 		return (0);
263373bf949cSBill Paul 
263473bf949cSBill Paul 	/* We've fallen behing the chip: catch it. */
263573bf949cSBill Paul 	sc->dc_cdata.dc_rx_prod = pos;
263673bf949cSBill Paul 
263773bf949cSBill Paul 	return (EAGAIN);
263873bf949cSBill Paul }
263973bf949cSBill Paul 
264073bf949cSBill Paul /*
264196f2e892SBill Paul  * A frame has been uploaded: pass the resulting mbuf chain up to
264296f2e892SBill Paul  * the higher level protocols.
264396f2e892SBill Paul  */
2644e3d2833aSAlfred Perlstein static void
26450934f18aSMaxime Henrion dc_rxeof(struct dc_softc *sc)
264696f2e892SBill Paul {
2647432120f2SMarius Strobl 	struct mbuf *m, *m0;
264896f2e892SBill Paul 	struct ifnet *ifp;
264996f2e892SBill Paul 	struct dc_desc *cur_rx;
265096f2e892SBill Paul 	int i, total_len = 0;
265196f2e892SBill Paul 	u_int32_t rxstat;
265296f2e892SBill Paul 
26535120abbfSSam Leffler 	DC_LOCK_ASSERT(sc);
26545120abbfSSam Leffler 
2655fc74a9f9SBrooks Davis 	ifp = sc->dc_ifp;
265696f2e892SBill Paul 	i = sc->dc_cdata.dc_rx_prod;
265796f2e892SBill Paul 
265856e5e7aeSMaxime Henrion 	bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD);
2659af4358c7SMaxime Henrion 	while (!(le32toh(sc->dc_ldata->dc_rx_list[i].dc_status) &
2660af4358c7SMaxime Henrion 	    DC_RXSTAT_OWN)) {
2661e4fc250cSLuigi Rizzo #ifdef DEVICE_POLLING
266240929967SGleb Smirnoff 		if (ifp->if_capenable & IFCAP_POLLING) {
2663e4fc250cSLuigi Rizzo 			if (sc->rxcycles <= 0)
2664e4fc250cSLuigi Rizzo 				break;
2665e4fc250cSLuigi Rizzo 			sc->rxcycles--;
2666e4fc250cSLuigi Rizzo 		}
26670934f18aSMaxime Henrion #endif
266896f2e892SBill Paul 		cur_rx = &sc->dc_ldata->dc_rx_list[i];
2669af4358c7SMaxime Henrion 		rxstat = le32toh(cur_rx->dc_status);
267096f2e892SBill Paul 		m = sc->dc_cdata.dc_rx_chain[i];
267156e5e7aeSMaxime Henrion 		bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i],
267256e5e7aeSMaxime Henrion 		    BUS_DMASYNC_POSTREAD);
267396f2e892SBill Paul 		total_len = DC_RXBYTES(rxstat);
267496f2e892SBill Paul 
267596f2e892SBill Paul 		if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) {
267696f2e892SBill Paul 			if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) {
267796f2e892SBill Paul 				if (rxstat & DC_RXSTAT_FIRSTFRAG)
267896f2e892SBill Paul 					sc->dc_pnic_rx_bug_save = i;
267996f2e892SBill Paul 				if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) {
268096f2e892SBill Paul 					DC_INC(i, DC_RX_LIST_CNT);
268196f2e892SBill Paul 					continue;
268296f2e892SBill Paul 				}
268396f2e892SBill Paul 				dc_pnic_rx_bug_war(sc, i);
2684af4358c7SMaxime Henrion 				rxstat = le32toh(cur_rx->dc_status);
268596f2e892SBill Paul 				total_len = DC_RXBYTES(rxstat);
268696f2e892SBill Paul 			}
268796f2e892SBill Paul 		}
268896f2e892SBill Paul 
268996f2e892SBill Paul 		/*
269096f2e892SBill Paul 		 * If an error occurs, update stats, clear the
269196f2e892SBill Paul 		 * status word and leave the mbuf cluster in place:
269296f2e892SBill Paul 		 * it should simply get re-used next time this descriptor
2693db40c1aeSDoug Ambrisko 		 * comes up in the ring.  However, don't report long
26940934f18aSMaxime Henrion 		 * frames as errors since they could be vlans.
269596f2e892SBill Paul 		 */
2696db40c1aeSDoug Ambrisko 		if ((rxstat & DC_RXSTAT_RXERR)) {
2697db40c1aeSDoug Ambrisko 			if (!(rxstat & DC_RXSTAT_GIANT) ||
2698db40c1aeSDoug Ambrisko 			    (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE |
2699db40c1aeSDoug Ambrisko 				       DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN |
2700db40c1aeSDoug Ambrisko 				       DC_RXSTAT_RUNT   | DC_RXSTAT_DE))) {
270196f2e892SBill Paul 				ifp->if_ierrors++;
270296f2e892SBill Paul 				if (rxstat & DC_RXSTAT_COLLSEEN)
270396f2e892SBill Paul 					ifp->if_collisions++;
270456e5e7aeSMaxime Henrion 				dc_newbuf(sc, i, 0);
270596f2e892SBill Paul 				if (rxstat & DC_RXSTAT_CRCERR) {
270696f2e892SBill Paul 					DC_INC(i, DC_RX_LIST_CNT);
270796f2e892SBill Paul 					continue;
270896f2e892SBill Paul 				} else {
2709c8b27acaSJohn Baldwin 					dc_init_locked(sc);
271096f2e892SBill Paul 					return;
271196f2e892SBill Paul 				}
271296f2e892SBill Paul 			}
2713db40c1aeSDoug Ambrisko 		}
271496f2e892SBill Paul 
271596f2e892SBill Paul 		/* No errors; receive the packet. */
271696f2e892SBill Paul 		total_len -= ETHER_CRC_LEN;
2717432120f2SMarius Strobl #ifdef __NO_STRICT_ALIGNMENT
271801faf54bSLuigi Rizzo 		/*
2719432120f2SMarius Strobl 		 * On architectures without alignment problems we try to
272001faf54bSLuigi Rizzo 		 * allocate a new buffer for the receive ring, and pass up
272101faf54bSLuigi Rizzo 		 * the one where the packet is already, saving the expensive
272201faf54bSLuigi Rizzo 		 * copy done in m_devget().
272301faf54bSLuigi Rizzo 		 * If we are on an architecture with alignment problems, or
272401faf54bSLuigi Rizzo 		 * if the allocation fails, then use m_devget and leave the
272501faf54bSLuigi Rizzo 		 * existing buffer in the receive ring.
272601faf54bSLuigi Rizzo 		 */
2727432120f2SMarius Strobl 		if (dc_newbuf(sc, i, 1) == 0) {
272801faf54bSLuigi Rizzo 			m->m_pkthdr.rcvif = ifp;
272901faf54bSLuigi Rizzo 			m->m_pkthdr.len = m->m_len = total_len;
273001faf54bSLuigi Rizzo 			DC_INC(i, DC_RX_LIST_CNT);
273101faf54bSLuigi Rizzo 		} else
273201faf54bSLuigi Rizzo #endif
273301faf54bSLuigi Rizzo 		{
273401faf54bSLuigi Rizzo 			m0 = m_devget(mtod(m, char *), total_len,
273501faf54bSLuigi Rizzo 				ETHER_ALIGN, ifp, NULL);
273656e5e7aeSMaxime Henrion 			dc_newbuf(sc, i, 0);
273796f2e892SBill Paul 			DC_INC(i, DC_RX_LIST_CNT);
273896f2e892SBill Paul 			if (m0 == NULL) {
273996f2e892SBill Paul 				ifp->if_ierrors++;
274096f2e892SBill Paul 				continue;
274196f2e892SBill Paul 			}
274296f2e892SBill Paul 			m = m0;
274301faf54bSLuigi Rizzo 		}
274496f2e892SBill Paul 
274596f2e892SBill Paul 		ifp->if_ipackets++;
27465120abbfSSam Leffler 		DC_UNLOCK(sc);
27479ef8b520SSam Leffler 		(*ifp->if_input)(ifp, m);
27485120abbfSSam Leffler 		DC_LOCK(sc);
274996f2e892SBill Paul 	}
275096f2e892SBill Paul 
275196f2e892SBill Paul 	sc->dc_cdata.dc_rx_prod = i;
275296f2e892SBill Paul }
275396f2e892SBill Paul 
275496f2e892SBill Paul /*
275596f2e892SBill Paul  * A frame was downloaded to the chip. It's safe for us to clean up
275696f2e892SBill Paul  * the list buffers.
275796f2e892SBill Paul  */
2758e3d2833aSAlfred Perlstein static void
27590934f18aSMaxime Henrion dc_txeof(struct dc_softc *sc)
276096f2e892SBill Paul {
276196f2e892SBill Paul 	struct dc_desc *cur_tx = NULL;
276296f2e892SBill Paul 	struct ifnet *ifp;
276396f2e892SBill Paul 	int idx;
2764af4358c7SMaxime Henrion 	u_int32_t ctl, txstat;
276596f2e892SBill Paul 
2766fc74a9f9SBrooks Davis 	ifp = sc->dc_ifp;
276796f2e892SBill Paul 
276896f2e892SBill Paul 	/*
276996f2e892SBill Paul 	 * Go through our tx list and free mbufs for those
277096f2e892SBill Paul 	 * frames that have been transmitted.
277196f2e892SBill Paul 	 */
277256e5e7aeSMaxime Henrion 	bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD);
277396f2e892SBill Paul 	idx = sc->dc_cdata.dc_tx_cons;
277496f2e892SBill Paul 	while (idx != sc->dc_cdata.dc_tx_prod) {
277596f2e892SBill Paul 
277696f2e892SBill Paul 		cur_tx = &sc->dc_ldata->dc_tx_list[idx];
2777af4358c7SMaxime Henrion 		txstat = le32toh(cur_tx->dc_status);
2778af4358c7SMaxime Henrion 		ctl = le32toh(cur_tx->dc_ctl);
277996f2e892SBill Paul 
278096f2e892SBill Paul 		if (txstat & DC_TXSTAT_OWN)
278196f2e892SBill Paul 			break;
278296f2e892SBill Paul 
27834ff4a9beSDon Lewis 		if (!(ctl & DC_TXCTL_LASTFRAG) || ctl & DC_TXCTL_SETUP) {
2784af4358c7SMaxime Henrion 			if (ctl & DC_TXCTL_SETUP) {
278596f2e892SBill Paul 				/*
278696f2e892SBill Paul 				 * Yes, the PNIC is so brain damaged
278796f2e892SBill Paul 				 * that it will sometimes generate a TX
278896f2e892SBill Paul 				 * underrun error while DMAing the RX
278996f2e892SBill Paul 				 * filter setup frame. If we detect this,
279096f2e892SBill Paul 				 * we have to send the setup frame again,
279196f2e892SBill Paul 				 * or else the filter won't be programmed
279296f2e892SBill Paul 				 * correctly.
279396f2e892SBill Paul 				 */
279496f2e892SBill Paul 				if (DC_IS_PNIC(sc)) {
279596f2e892SBill Paul 					if (txstat & DC_TXSTAT_ERRSUM)
279696f2e892SBill Paul 						dc_setfilt(sc);
279796f2e892SBill Paul 				}
279896f2e892SBill Paul 				sc->dc_cdata.dc_tx_chain[idx] = NULL;
279996f2e892SBill Paul 			}
2800bcb9ef4fSLuigi Rizzo 			sc->dc_cdata.dc_tx_cnt--;
280196f2e892SBill Paul 			DC_INC(idx, DC_TX_LIST_CNT);
280296f2e892SBill Paul 			continue;
280396f2e892SBill Paul 		}
280496f2e892SBill Paul 
280529a2220aSBill Paul 		if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) {
2806feb78939SJonathan Chen 			/*
2807feb78939SJonathan Chen 			 * XXX: Why does my Xircom taunt me so?
2808feb78939SJonathan Chen 			 * For some reason it likes setting the CARRLOST flag
280929a2220aSBill Paul 			 * even when the carrier is there. wtf?!?
281029a2220aSBill Paul 			 * Who knows, but Conexant chips have the
281129a2220aSBill Paul 			 * same problem. Maybe they took lessons
281229a2220aSBill Paul 			 * from Xircom.
281329a2220aSBill Paul 			 */
2814feb78939SJonathan Chen 			if (/*sc->dc_type == DC_TYPE_21143 &&*/
2815feb78939SJonathan Chen 			    sc->dc_pmode == DC_PMODE_MII &&
2816feb78939SJonathan Chen 			    ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM |
2817feb78939SJonathan Chen 			    DC_TXSTAT_NOCARRIER)))
2818feb78939SJonathan Chen 				txstat &= ~DC_TXSTAT_ERRSUM;
2819feb78939SJonathan Chen 		} else {
282096f2e892SBill Paul 			if (/*sc->dc_type == DC_TYPE_21143 &&*/
282196f2e892SBill Paul 			    sc->dc_pmode == DC_PMODE_MII &&
282296f2e892SBill Paul 			    ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM |
282396f2e892SBill Paul 			    DC_TXSTAT_NOCARRIER | DC_TXSTAT_CARRLOST)))
282496f2e892SBill Paul 				txstat &= ~DC_TXSTAT_ERRSUM;
2825feb78939SJonathan Chen 		}
282696f2e892SBill Paul 
282796f2e892SBill Paul 		if (txstat & DC_TXSTAT_ERRSUM) {
282896f2e892SBill Paul 			ifp->if_oerrors++;
282996f2e892SBill Paul 			if (txstat & DC_TXSTAT_EXCESSCOLL)
283096f2e892SBill Paul 				ifp->if_collisions++;
283196f2e892SBill Paul 			if (txstat & DC_TXSTAT_LATECOLL)
283296f2e892SBill Paul 				ifp->if_collisions++;
283396f2e892SBill Paul 			if (!(txstat & DC_TXSTAT_UNDERRUN)) {
2834c8b27acaSJohn Baldwin 				dc_init_locked(sc);
283596f2e892SBill Paul 				return;
283696f2e892SBill Paul 			}
283796f2e892SBill Paul 		}
283896f2e892SBill Paul 
283996f2e892SBill Paul 		ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3;
284096f2e892SBill Paul 
284196f2e892SBill Paul 		ifp->if_opackets++;
284296f2e892SBill Paul 		if (sc->dc_cdata.dc_tx_chain[idx] != NULL) {
284356e5e7aeSMaxime Henrion 			bus_dmamap_sync(sc->dc_mtag,
284456e5e7aeSMaxime Henrion 			    sc->dc_cdata.dc_tx_map[idx],
284556e5e7aeSMaxime Henrion 			    BUS_DMASYNC_POSTWRITE);
284656e5e7aeSMaxime Henrion 			bus_dmamap_unload(sc->dc_mtag,
284756e5e7aeSMaxime Henrion 			    sc->dc_cdata.dc_tx_map[idx]);
284896f2e892SBill Paul 			m_freem(sc->dc_cdata.dc_tx_chain[idx]);
284996f2e892SBill Paul 			sc->dc_cdata.dc_tx_chain[idx] = NULL;
285096f2e892SBill Paul 		}
285196f2e892SBill Paul 
285296f2e892SBill Paul 		sc->dc_cdata.dc_tx_cnt--;
285396f2e892SBill Paul 		DC_INC(idx, DC_TX_LIST_CNT);
285496f2e892SBill Paul 	}
285596f2e892SBill Paul 	sc->dc_cdata.dc_tx_cons = idx;
285682a67a70SMarius Strobl 
285782a67a70SMarius Strobl 	if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt > DC_TX_LIST_RSVD)
285813f4c340SRobert Watson 		ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
285982a67a70SMarius Strobl 
28603e0e6726SMarius Strobl 	if (sc->dc_cdata.dc_tx_cnt == 0)
28613e0e6726SMarius Strobl 		sc->dc_wdog_timer = 0;
286296f2e892SBill Paul }
286396f2e892SBill Paul 
2864e3d2833aSAlfred Perlstein static void
28650934f18aSMaxime Henrion dc_tick(void *xsc)
286696f2e892SBill Paul {
286796f2e892SBill Paul 	struct dc_softc *sc;
286896f2e892SBill Paul 	struct mii_data *mii;
286996f2e892SBill Paul 	struct ifnet *ifp;
287096f2e892SBill Paul 	u_int32_t r;
287196f2e892SBill Paul 
287296f2e892SBill Paul 	sc = xsc;
2873c8b27acaSJohn Baldwin 	DC_LOCK_ASSERT(sc);
2874fc74a9f9SBrooks Davis 	ifp = sc->dc_ifp;
287596f2e892SBill Paul 	mii = device_get_softc(sc->dc_miibus);
287696f2e892SBill Paul 
287796f2e892SBill Paul 	if (sc->dc_flags & DC_REDUCED_MII_POLL) {
2878318b02fdSBill Paul 		if (sc->dc_flags & DC_21143_NWAY) {
2879318b02fdSBill Paul 			r = CSR_READ_4(sc, DC_10BTSTAT);
2880318b02fdSBill Paul 			if (IFM_SUBTYPE(mii->mii_media_active) ==
2881318b02fdSBill Paul 			    IFM_100_TX && (r & DC_TSTAT_LS100)) {
288296f2e892SBill Paul 				sc->dc_link = 0;
2883318b02fdSBill Paul 				mii_mediachg(mii);
2884318b02fdSBill Paul 			}
2885318b02fdSBill Paul 			if (IFM_SUBTYPE(mii->mii_media_active) ==
2886318b02fdSBill Paul 			    IFM_10_T && (r & DC_TSTAT_LS10)) {
2887318b02fdSBill Paul 				sc->dc_link = 0;
2888318b02fdSBill Paul 				mii_mediachg(mii);
2889318b02fdSBill Paul 			}
2890d675147eSBill Paul 			if (sc->dc_link == 0)
289196f2e892SBill Paul 				mii_tick(mii);
289296f2e892SBill Paul 		} else {
2893d0d67284SMarius Strobl 			/*
2894d0d67284SMarius Strobl 			 * For NICs which never report DC_RXSTATE_WAIT, we
2895d0d67284SMarius Strobl 			 * have to bite the bullet...
2896d0d67284SMarius Strobl 			 */
2897d0d67284SMarius Strobl 			if ((DC_HAS_BROKEN_RXSTATE(sc) || (CSR_READ_4(sc,
2898d0d67284SMarius Strobl 			    DC_ISR) & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT) &&
2899259b8d84SMartin Blapp 			    sc->dc_cdata.dc_tx_cnt == 0) {
290096f2e892SBill Paul 				mii_tick(mii);
2901042c8f6eSBill Paul 				if (!(mii->mii_media_status & IFM_ACTIVE))
2902042c8f6eSBill Paul 					sc->dc_link = 0;
290396f2e892SBill Paul 			}
2904259b8d84SMartin Blapp 		}
290596f2e892SBill Paul 	} else
290696f2e892SBill Paul 		mii_tick(mii);
290796f2e892SBill Paul 
290896f2e892SBill Paul 	/*
290996f2e892SBill Paul 	 * When the init routine completes, we expect to be able to send
291096f2e892SBill Paul 	 * packets right away, and in fact the network code will send a
291196f2e892SBill Paul 	 * gratuitous ARP the moment the init routine marks the interface
291296f2e892SBill Paul 	 * as running. However, even though the MAC may have been initialized,
291396f2e892SBill Paul 	 * there may be a delay of a few seconds before the PHY completes
291496f2e892SBill Paul 	 * autonegotiation and the link is brought up. Any transmissions
291596f2e892SBill Paul 	 * made during that delay will be lost. Dealing with this is tricky:
291696f2e892SBill Paul 	 * we can't just pause in the init routine while waiting for the
291796f2e892SBill Paul 	 * PHY to come ready since that would bring the whole system to
291896f2e892SBill Paul 	 * a screeching halt for several seconds.
291996f2e892SBill Paul 	 *
292096f2e892SBill Paul 	 * What we do here is prevent the TX start routine from sending
292196f2e892SBill Paul 	 * any packets until a link has been established. After the
292296f2e892SBill Paul 	 * interface has been initialized, the tick routine will poll
292396f2e892SBill Paul 	 * the state of the PHY until the IFM_ACTIVE flag is set. Until
292496f2e892SBill Paul 	 * that time, packets will stay in the send queue, and once the
292596f2e892SBill Paul 	 * link comes up, they will be flushed out to the wire.
292696f2e892SBill Paul 	 */
2927cd62a9cbSJonathan Lemon 	if (!sc->dc_link && mii->mii_media_status & IFM_ACTIVE &&
292896f2e892SBill Paul 	    IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
292996f2e892SBill Paul 		sc->dc_link++;
2930cbaf877fSBrian Feldman 		if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2931c8b27acaSJohn Baldwin 			dc_start_locked(ifp);
293296f2e892SBill Paul 	}
293396f2e892SBill Paul 
2934318b02fdSBill Paul 	if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link)
2935b50c6312SJonathan Lemon 		callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc);
2936318b02fdSBill Paul 	else
2937b50c6312SJonathan Lemon 		callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc);
293896f2e892SBill Paul }
293996f2e892SBill Paul 
2940d467c136SBill Paul /*
2941d467c136SBill Paul  * A transmit underrun has occurred.  Back off the transmit threshold,
2942d467c136SBill Paul  * or switch to store and forward mode if we have to.
2943d467c136SBill Paul  */
2944e3d2833aSAlfred Perlstein static void
29450934f18aSMaxime Henrion dc_tx_underrun(struct dc_softc *sc)
2946d467c136SBill Paul {
2947d467c136SBill Paul 	u_int32_t isr;
2948d467c136SBill Paul 	int i;
2949d467c136SBill Paul 
2950d467c136SBill Paul 	if (DC_IS_DAVICOM(sc))
2951c8b27acaSJohn Baldwin 		dc_init_locked(sc);
2952d467c136SBill Paul 
2953d467c136SBill Paul 	if (DC_IS_INTEL(sc)) {
2954d467c136SBill Paul 		/*
2955d467c136SBill Paul 		 * The real 21143 requires that the transmitter be idle
2956d467c136SBill Paul 		 * in order to change the transmit threshold or store
2957d467c136SBill Paul 		 * and forward state.
2958d467c136SBill Paul 		 */
2959d467c136SBill Paul 		DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
2960d467c136SBill Paul 
2961d467c136SBill Paul 		for (i = 0; i < DC_TIMEOUT; i++) {
2962d467c136SBill Paul 			isr = CSR_READ_4(sc, DC_ISR);
2963d467c136SBill Paul 			if (isr & DC_ISR_TX_IDLE)
2964d467c136SBill Paul 				break;
2965d467c136SBill Paul 			DELAY(10);
2966d467c136SBill Paul 		}
2967d467c136SBill Paul 		if (i == DC_TIMEOUT) {
29686b9f5c94SGleb Smirnoff 			device_printf(sc->dc_dev,
2969432120f2SMarius Strobl 			    "%s: failed to force tx to idle state\n",
2970432120f2SMarius Strobl 			    __func__);
2971c8b27acaSJohn Baldwin 			dc_init_locked(sc);
2972d467c136SBill Paul 		}
2973d467c136SBill Paul 	}
2974d467c136SBill Paul 
29756b9f5c94SGleb Smirnoff 	device_printf(sc->dc_dev, "TX underrun -- ");
2976d467c136SBill Paul 	sc->dc_txthresh += DC_TXTHRESH_INC;
2977d467c136SBill Paul 	if (sc->dc_txthresh > DC_TXTHRESH_MAX) {
2978d467c136SBill Paul 		printf("using store and forward mode\n");
2979d467c136SBill Paul 		DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
2980d467c136SBill Paul 	} else {
2981d467c136SBill Paul 		printf("increasing TX threshold\n");
2982d467c136SBill Paul 		DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH);
2983d467c136SBill Paul 		DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh);
2984d467c136SBill Paul 	}
2985d467c136SBill Paul 
2986d467c136SBill Paul 	if (DC_IS_INTEL(sc))
2987d467c136SBill Paul 		DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
2988d467c136SBill Paul }
2989d467c136SBill Paul 
2990e4fc250cSLuigi Rizzo #ifdef DEVICE_POLLING
2991e4fc250cSLuigi Rizzo static poll_handler_t dc_poll;
2992e4fc250cSLuigi Rizzo 
2993e4fc250cSLuigi Rizzo static void
2994e4fc250cSLuigi Rizzo dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2995e4fc250cSLuigi Rizzo {
2996e4fc250cSLuigi Rizzo 	struct dc_softc *sc = ifp->if_softc;
2997e4fc250cSLuigi Rizzo 
299840929967SGleb Smirnoff 	DC_LOCK(sc);
299940929967SGleb Smirnoff 
300040929967SGleb Smirnoff 	if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
300140929967SGleb Smirnoff 		DC_UNLOCK(sc);
3002e4fc250cSLuigi Rizzo 		return;
3003e4fc250cSLuigi Rizzo 	}
300440929967SGleb Smirnoff 
3005e4fc250cSLuigi Rizzo 	sc->rxcycles = count;
3006e4fc250cSLuigi Rizzo 	dc_rxeof(sc);
3007e4fc250cSLuigi Rizzo 	dc_txeof(sc);
300813f4c340SRobert Watson 	if (!IFQ_IS_EMPTY(&ifp->if_snd) &&
300913f4c340SRobert Watson 	    !(ifp->if_drv_flags & IFF_DRV_OACTIVE))
3010c8b27acaSJohn Baldwin 		dc_start_locked(ifp);
3011e4fc250cSLuigi Rizzo 
3012e4fc250cSLuigi Rizzo 	if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
3013e4fc250cSLuigi Rizzo 		u_int32_t	status;
3014e4fc250cSLuigi Rizzo 
3015e4fc250cSLuigi Rizzo 		status = CSR_READ_4(sc, DC_ISR);
3016e4fc250cSLuigi Rizzo 		status &= (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF |
3017e4fc250cSLuigi Rizzo 			DC_ISR_TX_NOBUF | DC_ISR_TX_IDLE | DC_ISR_TX_UNDERRUN |
3018e4fc250cSLuigi Rizzo 			DC_ISR_BUS_ERR);
30195120abbfSSam Leffler 		if (!status) {
30205120abbfSSam Leffler 			DC_UNLOCK(sc);
3021e4fc250cSLuigi Rizzo 			return;
30225120abbfSSam Leffler 		}
3023e4fc250cSLuigi Rizzo 		/* ack what we have */
3024e4fc250cSLuigi Rizzo 		CSR_WRITE_4(sc, DC_ISR, status);
3025e4fc250cSLuigi Rizzo 
3026e4fc250cSLuigi Rizzo 		if (status & (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF)) {
3027e4fc250cSLuigi Rizzo 			u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED);
3028e4fc250cSLuigi Rizzo 			ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff);
3029e4fc250cSLuigi Rizzo 
3030e4fc250cSLuigi Rizzo 			if (dc_rx_resync(sc))
3031e4fc250cSLuigi Rizzo 				dc_rxeof(sc);
3032e4fc250cSLuigi Rizzo 		}
3033e4fc250cSLuigi Rizzo 		/* restart transmit unit if necessary */
3034e4fc250cSLuigi Rizzo 		if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt)
3035e4fc250cSLuigi Rizzo 			CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3036e4fc250cSLuigi Rizzo 
3037e4fc250cSLuigi Rizzo 		if (status & DC_ISR_TX_UNDERRUN)
3038e4fc250cSLuigi Rizzo 			dc_tx_underrun(sc);
3039e4fc250cSLuigi Rizzo 
3040e4fc250cSLuigi Rizzo 		if (status & DC_ISR_BUS_ERR) {
30416b9f5c94SGleb Smirnoff 			if_printf(ifp, "%s: bus error\n", __func__);
3042e4fc250cSLuigi Rizzo 			dc_reset(sc);
3043c8b27acaSJohn Baldwin 			dc_init_locked(sc);
3044e4fc250cSLuigi Rizzo 		}
3045e4fc250cSLuigi Rizzo 	}
30465120abbfSSam Leffler 	DC_UNLOCK(sc);
3047e4fc250cSLuigi Rizzo }
3048e4fc250cSLuigi Rizzo #endif /* DEVICE_POLLING */
3049e4fc250cSLuigi Rizzo 
3050e3d2833aSAlfred Perlstein static void
30510934f18aSMaxime Henrion dc_intr(void *arg)
305296f2e892SBill Paul {
305396f2e892SBill Paul 	struct dc_softc *sc;
305496f2e892SBill Paul 	struct ifnet *ifp;
305596f2e892SBill Paul 	u_int32_t status;
305696f2e892SBill Paul 
305796f2e892SBill Paul 	sc = arg;
3058d2a1864bSWarner Losh 
30590934f18aSMaxime Henrion 	if (sc->suspended)
3060e8388e14SMitsuru IWASAKI 		return;
3061e8388e14SMitsuru IWASAKI 
3062d2a1864bSWarner Losh 	if ((CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0)
3063d2a1864bSWarner Losh 		return;
3064d2a1864bSWarner Losh 
3065d1ce9105SBill Paul 	DC_LOCK(sc);
3066fc74a9f9SBrooks Davis 	ifp = sc->dc_ifp;
3067e4fc250cSLuigi Rizzo #ifdef DEVICE_POLLING
306840929967SGleb Smirnoff 	if (ifp->if_capenable & IFCAP_POLLING) {
306940929967SGleb Smirnoff 		DC_UNLOCK(sc);
307040929967SGleb Smirnoff 		return;
3071e4fc250cSLuigi Rizzo 	}
30720934f18aSMaxime Henrion #endif
307396f2e892SBill Paul 
3074d88a358cSLuigi Rizzo 	/* Suppress unwanted interrupts */
307596f2e892SBill Paul 	if (!(ifp->if_flags & IFF_UP)) {
307696f2e892SBill Paul 		if (CSR_READ_4(sc, DC_ISR) & DC_INTRS)
307796f2e892SBill Paul 			dc_stop(sc);
3078d1ce9105SBill Paul 		DC_UNLOCK(sc);
307996f2e892SBill Paul 		return;
308096f2e892SBill Paul 	}
308196f2e892SBill Paul 
308296f2e892SBill Paul 	/* Disable interrupts. */
308396f2e892SBill Paul 	CSR_WRITE_4(sc, DC_IMR, 0x00000000);
308496f2e892SBill Paul 
30857ed2454cSGleb Smirnoff 	while (((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) &&
30867ed2454cSGleb Smirnoff 	    status != 0xFFFFFFFF &&
30875108cc56SGleb Smirnoff 	    (ifp->if_drv_flags & IFF_DRV_RUNNING)) {
308896f2e892SBill Paul 
308996f2e892SBill Paul 		CSR_WRITE_4(sc, DC_ISR, status);
309096f2e892SBill Paul 
309173bf949cSBill Paul 		if (status & DC_ISR_RX_OK) {
309273bf949cSBill Paul 			int		curpkts;
309373bf949cSBill Paul 			curpkts = ifp->if_ipackets;
309496f2e892SBill Paul 			dc_rxeof(sc);
309573bf949cSBill Paul 			if (curpkts == ifp->if_ipackets) {
309673bf949cSBill Paul 				while (dc_rx_resync(sc))
309773bf949cSBill Paul 					dc_rxeof(sc);
309873bf949cSBill Paul 			}
309973bf949cSBill Paul 		}
310096f2e892SBill Paul 
310196f2e892SBill Paul 		if (status & (DC_ISR_TX_OK | DC_ISR_TX_NOBUF))
310296f2e892SBill Paul 			dc_txeof(sc);
310396f2e892SBill Paul 
310496f2e892SBill Paul 		if (status & DC_ISR_TX_IDLE) {
310596f2e892SBill Paul 			dc_txeof(sc);
310696f2e892SBill Paul 			if (sc->dc_cdata.dc_tx_cnt) {
310796f2e892SBill Paul 				DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
310896f2e892SBill Paul 				CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
310996f2e892SBill Paul 			}
311096f2e892SBill Paul 		}
311196f2e892SBill Paul 
3112d467c136SBill Paul 		if (status & DC_ISR_TX_UNDERRUN)
3113d467c136SBill Paul 			dc_tx_underrun(sc);
311496f2e892SBill Paul 
311596f2e892SBill Paul 		if ((status & DC_ISR_RX_WATDOGTIMEO)
311673bf949cSBill Paul 		    || (status & DC_ISR_RX_NOBUF)) {
311773bf949cSBill Paul 			int		curpkts;
311873bf949cSBill Paul 			curpkts = ifp->if_ipackets;
311996f2e892SBill Paul 			dc_rxeof(sc);
312073bf949cSBill Paul 			if (curpkts == ifp->if_ipackets) {
312173bf949cSBill Paul 				while (dc_rx_resync(sc))
312273bf949cSBill Paul 					dc_rxeof(sc);
312373bf949cSBill Paul 			}
312473bf949cSBill Paul 		}
312596f2e892SBill Paul 
312696f2e892SBill Paul 		if (status & DC_ISR_BUS_ERR) {
312796f2e892SBill Paul 			dc_reset(sc);
3128c8b27acaSJohn Baldwin 			dc_init_locked(sc);
312996f2e892SBill Paul 		}
313096f2e892SBill Paul 	}
313196f2e892SBill Paul 
313296f2e892SBill Paul 	/* Re-enable interrupts. */
313396f2e892SBill Paul 	CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
313496f2e892SBill Paul 
3135cbaf877fSBrian Feldman 	if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3136c8b27acaSJohn Baldwin 		dc_start_locked(ifp);
313796f2e892SBill Paul 
3138d1ce9105SBill Paul 	DC_UNLOCK(sc);
313996f2e892SBill Paul }
314096f2e892SBill Paul 
314196f2e892SBill Paul /*
314296f2e892SBill Paul  * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
314396f2e892SBill Paul  * pointers to the fragment pointers.
314496f2e892SBill Paul  */
3145e3d2833aSAlfred Perlstein static int
3146a10c0e45SMike Silbersack dc_encap(struct dc_softc *sc, struct mbuf **m_head)
314796f2e892SBill Paul {
3148ebc284ccSMarius Strobl 	bus_dma_segment_t segs[DC_MAXFRAGS];
3149ebc284ccSMarius Strobl 	struct dc_desc *f;
315096f2e892SBill Paul 	struct mbuf *m;
3151993a741aSMarius Strobl 	int cur, defragged, error, first, frag, i, idx, nseg;
3152cda97c50SMike Silbersack 
3153cda97c50SMike Silbersack 	/*
3154cda97c50SMike Silbersack 	 * If there's no way we can send any packets, return now.
3155cda97c50SMike Silbersack 	 */
315682a67a70SMarius Strobl 	if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt <= DC_TX_LIST_RSVD)
3157cda97c50SMike Silbersack 		return (ENOBUFS);
3158cda97c50SMike Silbersack 
3159993a741aSMarius Strobl 	m = NULL;
3160993a741aSMarius Strobl 	defragged = 0;
3161993a741aSMarius Strobl 	if (sc->dc_flags & DC_TX_COALESCE &&
3162993a741aSMarius Strobl 	    ((*m_head)->m_next != NULL || sc->dc_flags & DC_TX_ALIGN)) {
3163993a741aSMarius Strobl 		m = m_defrag(*m_head, M_DONTWAIT);
3164993a741aSMarius Strobl 		defragged = 1;
3165993a741aSMarius Strobl 	} else {
3166cda97c50SMike Silbersack 		/*
3167993a741aSMarius Strobl 		 * Count the number of frags in this chain to see if we
3168993a741aSMarius Strobl 		 * need to m_collapse.  Since the descriptor list is shared
3169993a741aSMarius Strobl 		 * by all packets, we'll m_collapse long chains so that they
3170cda97c50SMike Silbersack 		 * do not use up the entire list, even if they would fit.
3171cda97c50SMike Silbersack 		 */
3172993a741aSMarius Strobl 		i = 0;
3173a10c0e45SMike Silbersack 		for (m = *m_head; m != NULL; m = m->m_next)
3174993a741aSMarius Strobl 			i++;
3175993a741aSMarius Strobl 		if (i > DC_TX_LIST_CNT / 4 ||
3176993a741aSMarius Strobl 		    DC_TX_LIST_CNT - i + sc->dc_cdata.dc_tx_cnt <=
3177993a741aSMarius Strobl 		    DC_TX_LIST_RSVD) {
3178993a741aSMarius Strobl 			m = m_collapse(*m_head, M_DONTWAIT, DC_MAXFRAGS);
3179993a741aSMarius Strobl 			defragged = 1;
3180993a741aSMarius Strobl 		}
3181993a741aSMarius Strobl 	}
3182993a741aSMarius Strobl 	if (defragged != 0) {
318382a67a70SMarius Strobl 		if (m == NULL) {
318482a67a70SMarius Strobl 			m_freem(*m_head);
318582a67a70SMarius Strobl 			*m_head = NULL;
3186cda97c50SMike Silbersack 			return (ENOBUFS);
318782a67a70SMarius Strobl 		}
3188a10c0e45SMike Silbersack 		*m_head = m;
3189cda97c50SMike Silbersack 	}
3190993a741aSMarius Strobl 
319156e5e7aeSMaxime Henrion 	idx = sc->dc_cdata.dc_tx_prod;
3192ebc284ccSMarius Strobl 	error = bus_dmamap_load_mbuf_sg(sc->dc_mtag,
3193ebc284ccSMarius Strobl 	    sc->dc_cdata.dc_tx_map[idx], *m_head, segs, &nseg, 0);
3194ebc284ccSMarius Strobl 	if (error == EFBIG) {
3195993a741aSMarius Strobl 		if (defragged != 0 || (m = m_collapse(*m_head, M_DONTWAIT,
3196993a741aSMarius Strobl 		    DC_MAXFRAGS)) == NULL) {
3197ebc284ccSMarius Strobl 			m_freem(*m_head);
319882a67a70SMarius Strobl 			*m_head = NULL;
3199993a741aSMarius Strobl 			return (defragged != 0 ? error : ENOBUFS);
320082a67a70SMarius Strobl 		}
3201ebc284ccSMarius Strobl 		*m_head = m;
3202ebc284ccSMarius Strobl 		error = bus_dmamap_load_mbuf_sg(sc->dc_mtag,
3203ebc284ccSMarius Strobl 		    sc->dc_cdata.dc_tx_map[idx], *m_head, segs, &nseg, 0);
3204ebc284ccSMarius Strobl 		if (error != 0) {
3205ebc284ccSMarius Strobl 			m_freem(*m_head);
3206ebc284ccSMarius Strobl 			*m_head = NULL;
3207ebc284ccSMarius Strobl 			return (error);
320882a67a70SMarius Strobl 		}
3209ebc284ccSMarius Strobl 	} else if (error != 0)
3210ebc284ccSMarius Strobl 		return (error);
3211ebc284ccSMarius Strobl 	KASSERT(nseg <= DC_MAXFRAGS,
3212ebc284ccSMarius Strobl 	    ("%s: wrong number of segments (%d)", __func__, nseg));
3213ebc284ccSMarius Strobl 	if (nseg == 0) {
3214ebc284ccSMarius Strobl 		m_freem(*m_head);
3215ebc284ccSMarius Strobl 		*m_head = NULL;
3216ebc284ccSMarius Strobl 		return (EIO);
3217ebc284ccSMarius Strobl 	}
3218ebc284ccSMarius Strobl 
3219ebc284ccSMarius Strobl 	first = cur = frag = sc->dc_cdata.dc_tx_prod;
3220ebc284ccSMarius Strobl 	for (i = 0; i < nseg; i++) {
3221ebc284ccSMarius Strobl 		if ((sc->dc_flags & DC_TX_ADMTEK_WAR) &&
3222ebc284ccSMarius Strobl 		    (frag == (DC_TX_LIST_CNT - 1)) &&
3223ebc284ccSMarius Strobl 		    (first != sc->dc_cdata.dc_tx_first)) {
3224ebc284ccSMarius Strobl 			bus_dmamap_unload(sc->dc_mtag,
3225ebc284ccSMarius Strobl 			    sc->dc_cdata.dc_tx_map[first]);
3226ebc284ccSMarius Strobl 			m_freem(*m_head);
3227ebc284ccSMarius Strobl 			*m_head = NULL;
3228ebc284ccSMarius Strobl 			return (ENOBUFS);
3229ebc284ccSMarius Strobl 		}
3230ebc284ccSMarius Strobl 
3231ebc284ccSMarius Strobl 		f = &sc->dc_ldata->dc_tx_list[frag];
3232ebc284ccSMarius Strobl 		f->dc_ctl = htole32(DC_TXCTL_TLINK | segs[i].ds_len);
3233ebc284ccSMarius Strobl 		if (i == 0) {
3234ebc284ccSMarius Strobl 			f->dc_status = 0;
3235ebc284ccSMarius Strobl 			f->dc_ctl |= htole32(DC_TXCTL_FIRSTFRAG);
3236ebc284ccSMarius Strobl 		} else
3237ebc284ccSMarius Strobl 			f->dc_status = htole32(DC_TXSTAT_OWN);
3238ebc284ccSMarius Strobl 		f->dc_data = htole32(segs[i].ds_addr);
3239ebc284ccSMarius Strobl 		cur = frag;
3240ebc284ccSMarius Strobl 		DC_INC(frag, DC_TX_LIST_CNT);
3241ebc284ccSMarius Strobl 	}
3242ebc284ccSMarius Strobl 
3243ebc284ccSMarius Strobl 	sc->dc_cdata.dc_tx_prod = frag;
3244ebc284ccSMarius Strobl 	sc->dc_cdata.dc_tx_cnt += nseg;
3245ebc284ccSMarius Strobl 	sc->dc_cdata.dc_tx_chain[cur] = *m_head;
3246ebc284ccSMarius Strobl 	sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_LASTFRAG);
3247ebc284ccSMarius Strobl 	if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG)
3248ebc284ccSMarius Strobl 		sc->dc_ldata->dc_tx_list[first].dc_ctl |=
3249ebc284ccSMarius Strobl 		    htole32(DC_TXCTL_FINT);
3250ebc284ccSMarius Strobl 	if (sc->dc_flags & DC_TX_INTR_ALWAYS)
3251ebc284ccSMarius Strobl 		sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT);
3252ebc284ccSMarius Strobl 	if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64)
3253ebc284ccSMarius Strobl 		sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT);
3254ebc284ccSMarius Strobl 	sc->dc_ldata->dc_tx_list[first].dc_status = htole32(DC_TXSTAT_OWN);
3255ebc284ccSMarius Strobl 
325656e5e7aeSMaxime Henrion 	bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx],
325756e5e7aeSMaxime Henrion 	    BUS_DMASYNC_PREWRITE);
325856e5e7aeSMaxime Henrion 	bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap,
325956e5e7aeSMaxime Henrion 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
326096f2e892SBill Paul 	return (0);
326196f2e892SBill Paul }
326296f2e892SBill Paul 
3263e3d2833aSAlfred Perlstein static void
32640934f18aSMaxime Henrion dc_start(struct ifnet *ifp)
326596f2e892SBill Paul {
326696f2e892SBill Paul 	struct dc_softc *sc;
3267c8b27acaSJohn Baldwin 
3268c8b27acaSJohn Baldwin 	sc = ifp->if_softc;
3269c8b27acaSJohn Baldwin 	DC_LOCK(sc);
3270c8b27acaSJohn Baldwin 	dc_start_locked(ifp);
3271c8b27acaSJohn Baldwin 	DC_UNLOCK(sc);
3272c8b27acaSJohn Baldwin }
3273c8b27acaSJohn Baldwin 
3274ebc284ccSMarius Strobl /*
3275ebc284ccSMarius Strobl  * Main transmit routine
3276ebc284ccSMarius Strobl  * To avoid having to do mbuf copies, we put pointers to the mbuf data
3277ebc284ccSMarius Strobl  * regions directly in the transmit lists.  We also save a copy of the
3278ebc284ccSMarius Strobl  * pointers since the transmit list fragment pointers are physical
3279ebc284ccSMarius Strobl  * addresses.
3280ebc284ccSMarius Strobl  */
3281c8b27acaSJohn Baldwin static void
3282c8b27acaSJohn Baldwin dc_start_locked(struct ifnet *ifp)
3283c8b27acaSJohn Baldwin {
3284c8b27acaSJohn Baldwin 	struct dc_softc *sc;
328582a67a70SMarius Strobl 	struct mbuf *m_head = NULL;
3286cbaf877fSBrian Feldman 	unsigned int queued = 0;
328796f2e892SBill Paul 	int idx;
328896f2e892SBill Paul 
328996f2e892SBill Paul 	sc = ifp->if_softc;
329096f2e892SBill Paul 
3291c8b27acaSJohn Baldwin 	DC_LOCK_ASSERT(sc);
329296f2e892SBill Paul 
3293c8b27acaSJohn Baldwin 	if (!sc->dc_link && ifp->if_snd.ifq_len < 10)
329496f2e892SBill Paul 		return;
3295d1ce9105SBill Paul 
3296c8b27acaSJohn Baldwin 	if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
3297d1ce9105SBill Paul 		return;
329896f2e892SBill Paul 
329956e5e7aeSMaxime Henrion 	idx = sc->dc_cdata.dc_tx_first = sc->dc_cdata.dc_tx_prod;
330096f2e892SBill Paul 
330196f2e892SBill Paul 	while (sc->dc_cdata.dc_tx_chain[idx] == NULL) {
3302cbaf877fSBrian Feldman 		IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
330396f2e892SBill Paul 		if (m_head == NULL)
330496f2e892SBill Paul 			break;
330596f2e892SBill Paul 
3306a10c0e45SMike Silbersack 		if (dc_encap(sc, &m_head)) {
330782a67a70SMarius Strobl 			if (m_head == NULL)
330882a67a70SMarius Strobl 				break;
3309cbaf877fSBrian Feldman 			IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
331013f4c340SRobert Watson 			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
331196f2e892SBill Paul 			break;
331296f2e892SBill Paul 		}
331356e5e7aeSMaxime Henrion 		idx = sc->dc_cdata.dc_tx_prod;
331496f2e892SBill Paul 
3315cbaf877fSBrian Feldman 		queued++;
331696f2e892SBill Paul 		/*
331796f2e892SBill Paul 		 * If there's a BPF listener, bounce a copy of this frame
331896f2e892SBill Paul 		 * to him.
331996f2e892SBill Paul 		 */
33209ef8b520SSam Leffler 		BPF_MTAP(ifp, m_head);
33215c1cfac4SBill Paul 
33225c1cfac4SBill Paul 		if (sc->dc_flags & DC_TX_ONE) {
332313f4c340SRobert Watson 			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
33245c1cfac4SBill Paul 			break;
33255c1cfac4SBill Paul 		}
332696f2e892SBill Paul 	}
332796f2e892SBill Paul 
3328cbaf877fSBrian Feldman 	if (queued > 0) {
332996f2e892SBill Paul 		/* Transmit */
333096f2e892SBill Paul 		if (!(sc->dc_flags & DC_TX_POLL))
333196f2e892SBill Paul 			CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
333296f2e892SBill Paul 
333396f2e892SBill Paul 		/*
333496f2e892SBill Paul 		 * Set a timeout in case the chip goes out to lunch.
333596f2e892SBill Paul 		 */
3336b1d16143SMarius Strobl 		sc->dc_wdog_timer = 5;
3337cbaf877fSBrian Feldman 	}
333896f2e892SBill Paul }
333996f2e892SBill Paul 
3340e3d2833aSAlfred Perlstein static void
33410934f18aSMaxime Henrion dc_init(void *xsc)
334296f2e892SBill Paul {
334396f2e892SBill Paul 	struct dc_softc *sc = xsc;
3344c8b27acaSJohn Baldwin 
3345c8b27acaSJohn Baldwin 	DC_LOCK(sc);
3346c8b27acaSJohn Baldwin 	dc_init_locked(sc);
3347c8b27acaSJohn Baldwin 	DC_UNLOCK(sc);
3348c8b27acaSJohn Baldwin }
3349c8b27acaSJohn Baldwin 
3350c8b27acaSJohn Baldwin static void
3351c8b27acaSJohn Baldwin dc_init_locked(struct dc_softc *sc)
3352c8b27acaSJohn Baldwin {
3353fc74a9f9SBrooks Davis 	struct ifnet *ifp = sc->dc_ifp;
335496f2e892SBill Paul 	struct mii_data *mii;
335596f2e892SBill Paul 
3356c8b27acaSJohn Baldwin 	DC_LOCK_ASSERT(sc);
335796f2e892SBill Paul 
335896f2e892SBill Paul 	mii = device_get_softc(sc->dc_miibus);
335996f2e892SBill Paul 
336096f2e892SBill Paul 	/*
336196f2e892SBill Paul 	 * Cancel pending I/O and free all RX/TX buffers.
336296f2e892SBill Paul 	 */
336396f2e892SBill Paul 	dc_stop(sc);
336496f2e892SBill Paul 	dc_reset(sc);
336596f2e892SBill Paul 
336696f2e892SBill Paul 	/*
336796f2e892SBill Paul 	 * Set cache alignment and burst length.
336896f2e892SBill Paul 	 */
336988d739dcSBill Paul 	if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc))
337096f2e892SBill Paul 		CSR_WRITE_4(sc, DC_BUSCTL, 0);
337196f2e892SBill Paul 	else
337296f2e892SBill Paul 		CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME | DC_BUSCTL_MRLE);
3373935fe010SLuigi Rizzo 	/*
3374935fe010SLuigi Rizzo 	 * Evenly share the bus between receive and transmit process.
3375935fe010SLuigi Rizzo 	 */
3376935fe010SLuigi Rizzo 	if (DC_IS_INTEL(sc))
3377935fe010SLuigi Rizzo 		DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION);
337896f2e892SBill Paul 	if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) {
337996f2e892SBill Paul 		DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA);
338096f2e892SBill Paul 	} else {
338196f2e892SBill Paul 		DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG);
338296f2e892SBill Paul 	}
338396f2e892SBill Paul 	if (sc->dc_flags & DC_TX_POLL)
338496f2e892SBill Paul 		DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1);
338596f2e892SBill Paul 	switch(sc->dc_cachesize) {
338696f2e892SBill Paul 	case 32:
338796f2e892SBill Paul 		DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG);
338896f2e892SBill Paul 		break;
338996f2e892SBill Paul 	case 16:
339096f2e892SBill Paul 		DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG);
339196f2e892SBill Paul 		break;
339296f2e892SBill Paul 	case 8:
339396f2e892SBill Paul 		DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG);
339496f2e892SBill Paul 		break;
339596f2e892SBill Paul 	case 0:
339696f2e892SBill Paul 	default:
339796f2e892SBill Paul 		DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE);
339896f2e892SBill Paul 		break;
339996f2e892SBill Paul 	}
340096f2e892SBill Paul 
340196f2e892SBill Paul 	if (sc->dc_flags & DC_TX_STORENFWD)
340296f2e892SBill Paul 		DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
340396f2e892SBill Paul 	else {
3404d467c136SBill Paul 		if (sc->dc_txthresh > DC_TXTHRESH_MAX) {
340596f2e892SBill Paul 			DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
340696f2e892SBill Paul 		} else {
340796f2e892SBill Paul 			DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
340896f2e892SBill Paul 			DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh);
340996f2e892SBill Paul 		}
341096f2e892SBill Paul 	}
341196f2e892SBill Paul 
341296f2e892SBill Paul 	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC);
341396f2e892SBill Paul 	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF);
341496f2e892SBill Paul 
341596f2e892SBill Paul 	if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) {
341696f2e892SBill Paul 		/*
341796f2e892SBill Paul 		 * The app notes for the 98713 and 98715A say that
341896f2e892SBill Paul 		 * in order to have the chips operate properly, a magic
341996f2e892SBill Paul 		 * number must be written to CSR16. Macronix does not
342096f2e892SBill Paul 		 * document the meaning of these bits so there's no way
342196f2e892SBill Paul 		 * to know exactly what they do. The 98713 has a magic
342296f2e892SBill Paul 		 * number all its own; the rest all use a different one.
342396f2e892SBill Paul 		 */
342496f2e892SBill Paul 		DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000);
342596f2e892SBill Paul 		if (sc->dc_type == DC_TYPE_98713)
342696f2e892SBill Paul 			DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713);
342796f2e892SBill Paul 		else
342896f2e892SBill Paul 			DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715);
342996f2e892SBill Paul 	}
343096f2e892SBill Paul 
3431feb78939SJonathan Chen 	if (DC_IS_XIRCOM(sc)) {
3432feb78939SJonathan Chen 		/*
3433feb78939SJonathan Chen 		 * setup General Purpose Port mode and data so the tulip
3434feb78939SJonathan Chen 		 * can talk to the MII.
3435feb78939SJonathan Chen 		 */
3436feb78939SJonathan Chen 		CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN |
3437feb78939SJonathan Chen 			   DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
3438feb78939SJonathan Chen 		DELAY(10);
3439feb78939SJonathan Chen 		CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN |
3440feb78939SJonathan Chen 			   DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
3441feb78939SJonathan Chen 		DELAY(10);
3442feb78939SJonathan Chen 	}
3443feb78939SJonathan Chen 
344496f2e892SBill Paul 	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH);
3445d467c136SBill Paul 	DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN);
344696f2e892SBill Paul 
344796f2e892SBill Paul 	/* Init circular RX list. */
344896f2e892SBill Paul 	if (dc_list_rx_init(sc) == ENOBUFS) {
34496b9f5c94SGleb Smirnoff 		device_printf(sc->dc_dev,
345022f6205dSJohn Baldwin 		    "initialization failed: no memory for rx buffers\n");
345196f2e892SBill Paul 		dc_stop(sc);
345296f2e892SBill Paul 		return;
345396f2e892SBill Paul 	}
345496f2e892SBill Paul 
345596f2e892SBill Paul 	/*
345656e5e7aeSMaxime Henrion 	 * Init TX descriptors.
345796f2e892SBill Paul 	 */
345896f2e892SBill Paul 	dc_list_tx_init(sc);
345996f2e892SBill Paul 
346096f2e892SBill Paul 	/*
346196f2e892SBill Paul 	 * Load the address of the RX list.
346296f2e892SBill Paul 	 */
346356e5e7aeSMaxime Henrion 	CSR_WRITE_4(sc, DC_RXADDR, DC_RXDESC(sc, 0));
346456e5e7aeSMaxime Henrion 	CSR_WRITE_4(sc, DC_TXADDR, DC_TXDESC(sc, 0));
346596f2e892SBill Paul 
346696f2e892SBill Paul 	/*
346796f2e892SBill Paul 	 * Enable interrupts.
346896f2e892SBill Paul 	 */
3469e4fc250cSLuigi Rizzo #ifdef DEVICE_POLLING
3470e4fc250cSLuigi Rizzo 	/*
3471e4fc250cSLuigi Rizzo 	 * ... but only if we are not polling, and make sure they are off in
3472e4fc250cSLuigi Rizzo 	 * the case of polling. Some cards (e.g. fxp) turn interrupts on
3473e4fc250cSLuigi Rizzo 	 * after a reset.
3474e4fc250cSLuigi Rizzo 	 */
347540929967SGleb Smirnoff 	if (ifp->if_capenable & IFCAP_POLLING)
3476e4fc250cSLuigi Rizzo 		CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3477e4fc250cSLuigi Rizzo 	else
3478e4fc250cSLuigi Rizzo #endif
347996f2e892SBill Paul 	CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
348096f2e892SBill Paul 	CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF);
348196f2e892SBill Paul 
348296f2e892SBill Paul 	/* Enable transmitter. */
348396f2e892SBill Paul 	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
348496f2e892SBill Paul 
348596f2e892SBill Paul 	/*
3486918434c8SBill Paul 	 * If this is an Intel 21143 and we're not using the
3487918434c8SBill Paul 	 * MII port, program the LED control pins so we get
3488918434c8SBill Paul 	 * link and activity indications.
3489918434c8SBill Paul 	 */
349078999dd1SBill Paul 	if (sc->dc_flags & DC_TULIP_LEDS) {
3491918434c8SBill Paul 		CSR_WRITE_4(sc, DC_WATCHDOG,
3492918434c8SBill Paul 		    DC_WDOG_CTLWREN | DC_WDOG_LINK | DC_WDOG_ACTIVITY);
349378999dd1SBill Paul 		CSR_WRITE_4(sc, DC_WATCHDOG, 0);
3494918434c8SBill Paul 	}
3495918434c8SBill Paul 
3496918434c8SBill Paul 	/*
349796f2e892SBill Paul 	 * Load the RX/multicast filter. We do this sort of late
349896f2e892SBill Paul 	 * because the filter programming scheme on the 21143 and
349996f2e892SBill Paul 	 * some clones requires DMAing a setup frame via the TX
350096f2e892SBill Paul 	 * engine, and we need the transmitter enabled for that.
350196f2e892SBill Paul 	 */
350296f2e892SBill Paul 	dc_setfilt(sc);
350396f2e892SBill Paul 
350496f2e892SBill Paul 	/* Enable receiver. */
350596f2e892SBill Paul 	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON);
350696f2e892SBill Paul 	CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF);
350796f2e892SBill Paul 
350896f2e892SBill Paul 	mii_mediachg(mii);
350996f2e892SBill Paul 	dc_setcfg(sc, sc->dc_if_media);
351096f2e892SBill Paul 
351113f4c340SRobert Watson 	ifp->if_drv_flags |= IFF_DRV_RUNNING;
351213f4c340SRobert Watson 	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
351396f2e892SBill Paul 
3514857fd445SBill Paul 	/* Don't start the ticker if this is a homePNA link. */
351545521525SPoul-Henning Kamp 	if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1)
3516857fd445SBill Paul 		sc->dc_link = 1;
3517857fd445SBill Paul 	else {
3518318b02fdSBill Paul 		if (sc->dc_flags & DC_21143_NWAY)
3519b50c6312SJonathan Lemon 			callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc);
3520318b02fdSBill Paul 		else
3521b50c6312SJonathan Lemon 			callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc);
3522857fd445SBill Paul 	}
3523b1d16143SMarius Strobl 
3524b1d16143SMarius Strobl 	sc->dc_wdog_timer = 0;
3525b1d16143SMarius Strobl 	callout_reset(&sc->dc_wdog_ch, hz, dc_watchdog, sc);
352696f2e892SBill Paul }
352796f2e892SBill Paul 
352896f2e892SBill Paul /*
352996f2e892SBill Paul  * Set media options.
353096f2e892SBill Paul  */
3531e3d2833aSAlfred Perlstein static int
35320934f18aSMaxime Henrion dc_ifmedia_upd(struct ifnet *ifp)
353396f2e892SBill Paul {
353496f2e892SBill Paul 	struct dc_softc *sc;
353596f2e892SBill Paul 	struct mii_data *mii;
3536f43d9309SBill Paul 	struct ifmedia *ifm;
353796f2e892SBill Paul 
353896f2e892SBill Paul 	sc = ifp->if_softc;
353996f2e892SBill Paul 	mii = device_get_softc(sc->dc_miibus);
3540c8b27acaSJohn Baldwin 	DC_LOCK(sc);
354196f2e892SBill Paul 	mii_mediachg(mii);
3542f43d9309SBill Paul 	ifm = &mii->mii_media;
3543f43d9309SBill Paul 
3544f43d9309SBill Paul 	if (DC_IS_DAVICOM(sc) &&
354545521525SPoul-Henning Kamp 	    IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1)
3546f43d9309SBill Paul 		dc_setcfg(sc, ifm->ifm_media);
3547f43d9309SBill Paul 	else
354896f2e892SBill Paul 		sc->dc_link = 0;
3549c8b27acaSJohn Baldwin 	DC_UNLOCK(sc);
355096f2e892SBill Paul 
355196f2e892SBill Paul 	return (0);
355296f2e892SBill Paul }
355396f2e892SBill Paul 
355496f2e892SBill Paul /*
355596f2e892SBill Paul  * Report current media status.
355696f2e892SBill Paul  */
3557e3d2833aSAlfred Perlstein static void
35580934f18aSMaxime Henrion dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
355996f2e892SBill Paul {
356096f2e892SBill Paul 	struct dc_softc *sc;
356196f2e892SBill Paul 	struct mii_data *mii;
3562f43d9309SBill Paul 	struct ifmedia *ifm;
356396f2e892SBill Paul 
356496f2e892SBill Paul 	sc = ifp->if_softc;
356596f2e892SBill Paul 	mii = device_get_softc(sc->dc_miibus);
3566c8b27acaSJohn Baldwin 	DC_LOCK(sc);
356796f2e892SBill Paul 	mii_pollstat(mii);
3568f43d9309SBill Paul 	ifm = &mii->mii_media;
3569f43d9309SBill Paul 	if (DC_IS_DAVICOM(sc)) {
357045521525SPoul-Henning Kamp 		if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) {
3571f43d9309SBill Paul 			ifmr->ifm_active = ifm->ifm_media;
3572f43d9309SBill Paul 			ifmr->ifm_status = 0;
3573432120f2SMarius Strobl 			DC_UNLOCK(sc);
3574f43d9309SBill Paul 			return;
3575f43d9309SBill Paul 		}
3576f43d9309SBill Paul 	}
357796f2e892SBill Paul 	ifmr->ifm_active = mii->mii_media_active;
357896f2e892SBill Paul 	ifmr->ifm_status = mii->mii_media_status;
3579c8b27acaSJohn Baldwin 	DC_UNLOCK(sc);
358096f2e892SBill Paul }
358196f2e892SBill Paul 
3582e3d2833aSAlfred Perlstein static int
35830934f18aSMaxime Henrion dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
358496f2e892SBill Paul {
358596f2e892SBill Paul 	struct dc_softc *sc = ifp->if_softc;
358696f2e892SBill Paul 	struct ifreq *ifr = (struct ifreq *)data;
358796f2e892SBill Paul 	struct mii_data *mii;
3588d1ce9105SBill Paul 	int error = 0;
358996f2e892SBill Paul 
359096f2e892SBill Paul 	switch (command) {
359196f2e892SBill Paul 	case SIOCSIFFLAGS:
3592c8b27acaSJohn Baldwin 		DC_LOCK(sc);
359396f2e892SBill Paul 		if (ifp->if_flags & IFF_UP) {
35945d6dfbbbSLuigi Rizzo 			int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) &
35955d6dfbbbSLuigi Rizzo 				(IFF_PROMISC | IFF_ALLMULTI);
35965d6dfbbbSLuigi Rizzo 
359713f4c340SRobert Watson 			if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
35985d6dfbbbSLuigi Rizzo 				if (need_setfilt)
359996f2e892SBill Paul 					dc_setfilt(sc);
36005d6dfbbbSLuigi Rizzo 			} else {
360196f2e892SBill Paul 				sc->dc_txthresh = 0;
3602c8b27acaSJohn Baldwin 				dc_init_locked(sc);
360396f2e892SBill Paul 			}
360496f2e892SBill Paul 		} else {
360513f4c340SRobert Watson 			if (ifp->if_drv_flags & IFF_DRV_RUNNING)
360696f2e892SBill Paul 				dc_stop(sc);
360796f2e892SBill Paul 		}
360896f2e892SBill Paul 		sc->dc_if_flags = ifp->if_flags;
3609c8b27acaSJohn Baldwin 		DC_UNLOCK(sc);
361096f2e892SBill Paul 		error = 0;
361196f2e892SBill Paul 		break;
361296f2e892SBill Paul 	case SIOCADDMULTI:
361396f2e892SBill Paul 	case SIOCDELMULTI:
3614c8b27acaSJohn Baldwin 		DC_LOCK(sc);
361596f2e892SBill Paul 		dc_setfilt(sc);
3616c8b27acaSJohn Baldwin 		DC_UNLOCK(sc);
361796f2e892SBill Paul 		error = 0;
361896f2e892SBill Paul 		break;
361996f2e892SBill Paul 	case SIOCGIFMEDIA:
362096f2e892SBill Paul 	case SIOCSIFMEDIA:
362196f2e892SBill Paul 		mii = device_get_softc(sc->dc_miibus);
362296f2e892SBill Paul 		error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
362396f2e892SBill Paul 		break;
3624e695984eSRuslan Ermilov 	case SIOCSIFCAP:
362540929967SGleb Smirnoff #ifdef DEVICE_POLLING
362640929967SGleb Smirnoff 		if (ifr->ifr_reqcap & IFCAP_POLLING &&
362740929967SGleb Smirnoff 		    !(ifp->if_capenable & IFCAP_POLLING)) {
362840929967SGleb Smirnoff 			error = ether_poll_register(dc_poll, ifp);
362940929967SGleb Smirnoff 			if (error)
363040929967SGleb Smirnoff 				return(error);
3631c8b27acaSJohn Baldwin 			DC_LOCK(sc);
363240929967SGleb Smirnoff 			/* Disable interrupts */
363340929967SGleb Smirnoff 			CSR_WRITE_4(sc, DC_IMR, 0x00000000);
363440929967SGleb Smirnoff 			ifp->if_capenable |= IFCAP_POLLING;
3635c8b27acaSJohn Baldwin 			DC_UNLOCK(sc);
363640929967SGleb Smirnoff 			return (error);
363740929967SGleb Smirnoff 		}
363840929967SGleb Smirnoff 		if (!(ifr->ifr_reqcap & IFCAP_POLLING) &&
363940929967SGleb Smirnoff 		    ifp->if_capenable & IFCAP_POLLING) {
364040929967SGleb Smirnoff 			error = ether_poll_deregister(ifp);
364140929967SGleb Smirnoff 			/* Enable interrupts. */
364240929967SGleb Smirnoff 			DC_LOCK(sc);
364340929967SGleb Smirnoff 			CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
364440929967SGleb Smirnoff 			ifp->if_capenable &= ~IFCAP_POLLING;
364540929967SGleb Smirnoff 			DC_UNLOCK(sc);
364640929967SGleb Smirnoff 			return (error);
364740929967SGleb Smirnoff 		}
364840929967SGleb Smirnoff #endif /* DEVICE_POLLING */
3649e695984eSRuslan Ermilov 		break;
365096f2e892SBill Paul 	default:
36519ef8b520SSam Leffler 		error = ether_ioctl(ifp, command, data);
365296f2e892SBill Paul 		break;
365396f2e892SBill Paul 	}
365496f2e892SBill Paul 
365596f2e892SBill Paul 	return (error);
365696f2e892SBill Paul }
365796f2e892SBill Paul 
3658e3d2833aSAlfred Perlstein static void
3659b1d16143SMarius Strobl dc_watchdog(void *xsc)
366096f2e892SBill Paul {
3661b1d16143SMarius Strobl 	struct dc_softc *sc = xsc;
3662b1d16143SMarius Strobl 	struct ifnet *ifp;
366396f2e892SBill Paul 
3664b1d16143SMarius Strobl 	DC_LOCK_ASSERT(sc);
366596f2e892SBill Paul 
3666b1d16143SMarius Strobl 	if (sc->dc_wdog_timer == 0 || --sc->dc_wdog_timer != 0) {
3667b1d16143SMarius Strobl 		callout_reset(&sc->dc_wdog_ch, hz, dc_watchdog, sc);
3668b1d16143SMarius Strobl 		return;
3669b1d16143SMarius Strobl 	}
3670d1ce9105SBill Paul 
3671b1d16143SMarius Strobl 	ifp = sc->dc_ifp;
367296f2e892SBill Paul 	ifp->if_oerrors++;
3673b1d16143SMarius Strobl 	device_printf(sc->dc_dev, "watchdog timeout\n");
367496f2e892SBill Paul 
367596f2e892SBill Paul 	dc_stop(sc);
367696f2e892SBill Paul 	dc_reset(sc);
3677c8b27acaSJohn Baldwin 	dc_init_locked(sc);
367896f2e892SBill Paul 
3679cbaf877fSBrian Feldman 	if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3680c8b27acaSJohn Baldwin 		dc_start_locked(ifp);
368196f2e892SBill Paul }
368296f2e892SBill Paul 
368396f2e892SBill Paul /*
368496f2e892SBill Paul  * Stop the adapter and free any mbufs allocated to the
368596f2e892SBill Paul  * RX and TX lists.
368696f2e892SBill Paul  */
3687e3d2833aSAlfred Perlstein static void
36880934f18aSMaxime Henrion dc_stop(struct dc_softc *sc)
368996f2e892SBill Paul {
369096f2e892SBill Paul 	struct ifnet *ifp;
3691b3811c95SMaxime Henrion 	struct dc_list_data *ld;
3692b3811c95SMaxime Henrion 	struct dc_chain_data *cd;
3693b3811c95SMaxime Henrion 	int i;
3694af4358c7SMaxime Henrion 	u_int32_t ctl;
369596f2e892SBill Paul 
3696c8b27acaSJohn Baldwin 	DC_LOCK_ASSERT(sc);
3697d1ce9105SBill Paul 
3698fc74a9f9SBrooks Davis 	ifp = sc->dc_ifp;
3699b3811c95SMaxime Henrion 	ld = sc->dc_ldata;
3700b3811c95SMaxime Henrion 	cd = &sc->dc_cdata;
370196f2e892SBill Paul 
3702b50c6312SJonathan Lemon 	callout_stop(&sc->dc_stat_ch);
3703b1d16143SMarius Strobl 	callout_stop(&sc->dc_wdog_ch);
3704b1d16143SMarius Strobl 	sc->dc_wdog_timer = 0;
370596f2e892SBill Paul 
370613f4c340SRobert Watson 	ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
37073b3ec200SPeter Wemm 
370896f2e892SBill Paul 	DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON));
370996f2e892SBill Paul 	CSR_WRITE_4(sc, DC_IMR, 0x00000000);
371096f2e892SBill Paul 	CSR_WRITE_4(sc, DC_TXADDR, 0x00000000);
371196f2e892SBill Paul 	CSR_WRITE_4(sc, DC_RXADDR, 0x00000000);
371296f2e892SBill Paul 	sc->dc_link = 0;
371396f2e892SBill Paul 
371496f2e892SBill Paul 	/*
371596f2e892SBill Paul 	 * Free data in the RX lists.
371696f2e892SBill Paul 	 */
371796f2e892SBill Paul 	for (i = 0; i < DC_RX_LIST_CNT; i++) {
3718b3811c95SMaxime Henrion 		if (cd->dc_rx_chain[i] != NULL) {
371956e5e7aeSMaxime Henrion 			m_freem(cd->dc_rx_chain[i]);
372056e5e7aeSMaxime Henrion 			cd->dc_rx_chain[i] = NULL;
372196f2e892SBill Paul 		}
372296f2e892SBill Paul 	}
3723b3811c95SMaxime Henrion 	bzero(&ld->dc_rx_list, sizeof(ld->dc_rx_list));
372496f2e892SBill Paul 
372596f2e892SBill Paul 	/*
372696f2e892SBill Paul 	 * Free the TX list buffers.
372796f2e892SBill Paul 	 */
372896f2e892SBill Paul 	for (i = 0; i < DC_TX_LIST_CNT; i++) {
3729b3811c95SMaxime Henrion 		if (cd->dc_tx_chain[i] != NULL) {
3730af4358c7SMaxime Henrion 			ctl = le32toh(ld->dc_tx_list[i].dc_ctl);
3731af4358c7SMaxime Henrion 			if ((ctl & DC_TXCTL_SETUP) ||
37324ff4a9beSDon Lewis 			    !(ctl & DC_TXCTL_LASTFRAG)) {
3733b3811c95SMaxime Henrion 				cd->dc_tx_chain[i] = NULL;
373496f2e892SBill Paul 				continue;
373596f2e892SBill Paul 			}
373656e5e7aeSMaxime Henrion 			bus_dmamap_unload(sc->dc_mtag, cd->dc_tx_map[i]);
373756e5e7aeSMaxime Henrion 			m_freem(cd->dc_tx_chain[i]);
3738b3811c95SMaxime Henrion 			cd->dc_tx_chain[i] = NULL;
373996f2e892SBill Paul 		}
374096f2e892SBill Paul 	}
3741b3811c95SMaxime Henrion 	bzero(&ld->dc_tx_list, sizeof(ld->dc_tx_list));
374296f2e892SBill Paul }
374396f2e892SBill Paul 
374496f2e892SBill Paul /*
3745e8388e14SMitsuru IWASAKI  * Device suspend routine.  Stop the interface and save some PCI
3746e8388e14SMitsuru IWASAKI  * settings in case the BIOS doesn't restore them properly on
3747e8388e14SMitsuru IWASAKI  * resume.
3748e8388e14SMitsuru IWASAKI  */
3749e3d2833aSAlfred Perlstein static int
37500934f18aSMaxime Henrion dc_suspend(device_t dev)
3751e8388e14SMitsuru IWASAKI {
3752e8388e14SMitsuru IWASAKI 	struct dc_softc *sc;
3753e8388e14SMitsuru IWASAKI 
3754e8388e14SMitsuru IWASAKI 	sc = device_get_softc(dev);
3755c8b27acaSJohn Baldwin 	DC_LOCK(sc);
3756e8388e14SMitsuru IWASAKI 	dc_stop(sc);
3757e8388e14SMitsuru IWASAKI 	sc->suspended = 1;
3758c8b27acaSJohn Baldwin 	DC_UNLOCK(sc);
3759e8388e14SMitsuru IWASAKI 
3760e8388e14SMitsuru IWASAKI 	return (0);
3761e8388e14SMitsuru IWASAKI }
3762e8388e14SMitsuru IWASAKI 
3763e8388e14SMitsuru IWASAKI /*
3764e8388e14SMitsuru IWASAKI  * Device resume routine.  Restore some PCI settings in case the BIOS
3765e8388e14SMitsuru IWASAKI  * doesn't, re-enable busmastering, and restart the interface if
3766e8388e14SMitsuru IWASAKI  * appropriate.
3767e8388e14SMitsuru IWASAKI  */
3768e3d2833aSAlfred Perlstein static int
37690934f18aSMaxime Henrion dc_resume(device_t dev)
3770e8388e14SMitsuru IWASAKI {
3771e8388e14SMitsuru IWASAKI 	struct dc_softc *sc;
3772e8388e14SMitsuru IWASAKI 	struct ifnet *ifp;
3773e8388e14SMitsuru IWASAKI 
3774e8388e14SMitsuru IWASAKI 	sc = device_get_softc(dev);
3775fc74a9f9SBrooks Davis 	ifp = sc->dc_ifp;
3776e8388e14SMitsuru IWASAKI 
3777e8388e14SMitsuru IWASAKI 	/* reinitialize interface if necessary */
3778c8b27acaSJohn Baldwin 	DC_LOCK(sc);
3779e8388e14SMitsuru IWASAKI 	if (ifp->if_flags & IFF_UP)
3780c8b27acaSJohn Baldwin 		dc_init_locked(sc);
3781e8388e14SMitsuru IWASAKI 
3782e8388e14SMitsuru IWASAKI 	sc->suspended = 0;
3783c8b27acaSJohn Baldwin 	DC_UNLOCK(sc);
3784e8388e14SMitsuru IWASAKI 
3785e8388e14SMitsuru IWASAKI 	return (0);
3786e8388e14SMitsuru IWASAKI }
3787e8388e14SMitsuru IWASAKI 
3788e8388e14SMitsuru IWASAKI /*
378996f2e892SBill Paul  * Stop all chip I/O so that the kernel's probe routines don't
379096f2e892SBill Paul  * get confused by errant DMAs when rebooting.
379196f2e892SBill Paul  */
37926a087a87SPyun YongHyeon static int
37930934f18aSMaxime Henrion dc_shutdown(device_t dev)
379496f2e892SBill Paul {
379596f2e892SBill Paul 	struct dc_softc *sc;
379696f2e892SBill Paul 
379796f2e892SBill Paul 	sc = device_get_softc(dev);
379896f2e892SBill Paul 
3799c8b27acaSJohn Baldwin 	DC_LOCK(sc);
380096f2e892SBill Paul 	dc_stop(sc);
3801c8b27acaSJohn Baldwin 	DC_UNLOCK(sc);
38026a087a87SPyun YongHyeon 
38036a087a87SPyun YongHyeon 	return (0);
380496f2e892SBill Paul }
3805