160727d8bSWarner Losh /*- 296f2e892SBill Paul * Copyright (c) 1997, 1998, 1999 396f2e892SBill Paul * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 496f2e892SBill Paul * 596f2e892SBill Paul * Redistribution and use in source and binary forms, with or without 696f2e892SBill Paul * modification, are permitted provided that the following conditions 796f2e892SBill Paul * are met: 896f2e892SBill Paul * 1. Redistributions of source code must retain the above copyright 996f2e892SBill Paul * notice, this list of conditions and the following disclaimer. 1096f2e892SBill Paul * 2. Redistributions in binary form must reproduce the above copyright 1196f2e892SBill Paul * notice, this list of conditions and the following disclaimer in the 1296f2e892SBill Paul * documentation and/or other materials provided with the distribution. 1396f2e892SBill Paul * 3. All advertising materials mentioning features or use of this software 1496f2e892SBill Paul * must display the following acknowledgement: 1596f2e892SBill Paul * This product includes software developed by Bill Paul. 1696f2e892SBill Paul * 4. Neither the name of the author nor the names of any co-contributors 1796f2e892SBill Paul * may be used to endorse or promote products derived from this software 1896f2e892SBill Paul * without specific prior written permission. 1996f2e892SBill Paul * 2096f2e892SBill Paul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2196f2e892SBill Paul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2296f2e892SBill Paul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2396f2e892SBill Paul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2496f2e892SBill Paul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2596f2e892SBill Paul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2696f2e892SBill Paul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2796f2e892SBill Paul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2896f2e892SBill Paul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2996f2e892SBill Paul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3096f2e892SBill Paul * THE POSSIBILITY OF SUCH DAMAGE. 3196f2e892SBill Paul */ 3296f2e892SBill Paul 334dc52c32SDavid E. O'Brien #include <sys/cdefs.h> 344dc52c32SDavid E. O'Brien __FBSDID("$FreeBSD$"); 354dc52c32SDavid E. O'Brien 3696f2e892SBill Paul /* 3796f2e892SBill Paul * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 3896f2e892SBill Paul * series chips and several workalikes including the following: 3996f2e892SBill Paul * 40ead7cde9SBill Paul * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 4196f2e892SBill Paul * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 4296f2e892SBill Paul * Lite-On 82c168/82c169 PNIC (www.litecom.com) 4396f2e892SBill Paul * ASIX Electronics AX88140A (www.asix.com.tw) 4496f2e892SBill Paul * ASIX Electronics AX88141 (www.asix.com.tw) 4596f2e892SBill Paul * ADMtek AL981 (www.admtek.com.tw) 46593a1aeaSMartin Blapp * ADMtek AN983 (www.admtek.com.tw) 47a2d61e43SWarner Losh * ADMtek CardBus AN985 (www.admtek.com.tw) 48a2d61e43SWarner Losh * Netgear FA511 (www.netgear.com) Appears to be rebadged ADMTek CardBus AN985 4988d739dcSBill Paul * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 509ca710f6SJeroen Ruigrok van der Werven * Accton EN1217 (www.accton.com) 51feb78939SJonathan Chen * Xircom X3201 (www.xircom.com) 521d5e5310SBill Paul * Abocom FE2500 531af8bec7SBill Paul * Conexant LANfinity (www.conexant.com) 547eac366bSMartin Blapp * 3Com OfficeConnect 10/100B 3CSOHO100B (www.3com.com) 5596f2e892SBill Paul * 5696f2e892SBill Paul * Datasheets for the 21143 are available at developer.intel.com. 5796f2e892SBill Paul * Datasheets for the clone parts can be found at their respective sites. 5896f2e892SBill Paul * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 5996f2e892SBill Paul * The PNIC II is essentially a Macronix 98715A chip; the only difference 6096f2e892SBill Paul * worth noting is that its multicast hash table is only 128 bits wide 6196f2e892SBill Paul * instead of 512. 6296f2e892SBill Paul * 6396f2e892SBill Paul * Written by Bill Paul <wpaul@ee.columbia.edu> 6496f2e892SBill Paul * Electrical Engineering Department 6596f2e892SBill Paul * Columbia University, New York City 6696f2e892SBill Paul */ 6796f2e892SBill Paul /* 6896f2e892SBill Paul * The Intel 21143 is the successor to the DEC 21140. It is basically 6996f2e892SBill Paul * the same as the 21140 but with a few new features. The 21143 supports 7096f2e892SBill Paul * three kinds of media attachments: 7196f2e892SBill Paul * 7296f2e892SBill Paul * o MII port, for 10Mbps and 100Mbps support and NWAY 7396f2e892SBill Paul * autonegotiation provided by an external PHY. 7496f2e892SBill Paul * o SYM port, for symbol mode 100Mbps support. 7596f2e892SBill Paul * o 10baseT port. 7696f2e892SBill Paul * o AUI/BNC port. 7796f2e892SBill Paul * 7896f2e892SBill Paul * The 100Mbps SYM port and 10baseT port can be used together in 7996f2e892SBill Paul * combination with the internal NWAY support to create a 10/100 8096f2e892SBill Paul * autosensing configuration. 8196f2e892SBill Paul * 8296f2e892SBill Paul * Note that not all tulip workalikes are handled in this driver: we only 8396f2e892SBill Paul * deal with those which are relatively well behaved. The Winbond is 8496f2e892SBill Paul * handled separately due to its different register offsets and the 8596f2e892SBill Paul * special handling needed for its various bugs. The PNIC is handled 8696f2e892SBill Paul * here, but I'm not thrilled about it. 8796f2e892SBill Paul * 8896f2e892SBill Paul * All of the workalike chips use some form of MII transceiver support 8996f2e892SBill Paul * with the exception of the Macronix chips, which also have a SYM port. 9096f2e892SBill Paul * The ASIX AX88140A is also documented to have a SYM port, but all 9196f2e892SBill Paul * the cards I've seen use an MII transceiver, probably because the 9296f2e892SBill Paul * AX88140A doesn't support internal NWAY. 9396f2e892SBill Paul */ 9496f2e892SBill Paul 95f0796cd2SGleb Smirnoff #ifdef HAVE_KERNEL_OPTION_HEADERS 96f0796cd2SGleb Smirnoff #include "opt_device_polling.h" 97f0796cd2SGleb Smirnoff #endif 98f0796cd2SGleb Smirnoff 9996f2e892SBill Paul #include <sys/param.h> 100af4358c7SMaxime Henrion #include <sys/endian.h> 10196f2e892SBill Paul #include <sys/systm.h> 10296f2e892SBill Paul #include <sys/sockio.h> 10396f2e892SBill Paul #include <sys/mbuf.h> 10496f2e892SBill Paul #include <sys/malloc.h> 10596f2e892SBill Paul #include <sys/kernel.h> 106f11d01c3SPoul-Henning Kamp #include <sys/module.h> 10796f2e892SBill Paul #include <sys/socket.h> 10896f2e892SBill Paul 10996f2e892SBill Paul #include <net/if.h> 11096f2e892SBill Paul #include <net/if_arp.h> 11196f2e892SBill Paul #include <net/ethernet.h> 11296f2e892SBill Paul #include <net/if_dl.h> 11396f2e892SBill Paul #include <net/if_media.h> 114db40c1aeSDoug Ambrisko #include <net/if_types.h> 115db40c1aeSDoug Ambrisko #include <net/if_vlan_var.h> 11696f2e892SBill Paul 11796f2e892SBill Paul #include <net/bpf.h> 11896f2e892SBill Paul 11996f2e892SBill Paul #include <machine/bus.h> 12096f2e892SBill Paul #include <machine/resource.h> 12196f2e892SBill Paul #include <sys/bus.h> 12296f2e892SBill Paul #include <sys/rman.h> 12396f2e892SBill Paul 12496f2e892SBill Paul #include <dev/mii/mii.h> 12596f2e892SBill Paul #include <dev/mii/miivar.h> 12696f2e892SBill Paul 12719b7ffd1SWarner Losh #include <dev/pci/pcireg.h> 12819b7ffd1SWarner Losh #include <dev/pci/pcivar.h> 12996f2e892SBill Paul 13096f2e892SBill Paul #define DC_USEIOSPACE 13196f2e892SBill Paul 1326a3033a8SWarner Losh #include <dev/dc/if_dcreg.h> 13396f2e892SBill Paul 134ec6a7299SMaxime Henrion #ifdef __sparc64__ 135ec6a7299SMaxime Henrion #include <dev/ofw/openfirm.h> 136ec6a7299SMaxime Henrion #include <machine/ofw_machdep.h> 137ec6a7299SMaxime Henrion #endif 138ec6a7299SMaxime Henrion 139f246e4a1SMatthew N. Dodd MODULE_DEPEND(dc, pci, 1, 1, 1); 140f246e4a1SMatthew N. Dodd MODULE_DEPEND(dc, ether, 1, 1, 1); 14195a16455SPeter Wemm MODULE_DEPEND(dc, miibus, 1, 1, 1); 14295a16455SPeter Wemm 143919ccba7SWarner Losh /* 144919ccba7SWarner Losh * "device miibus" is required in kernel config. See GENERIC if you get 145919ccba7SWarner Losh * errors here. 146919ccba7SWarner Losh */ 14796f2e892SBill Paul #include "miibus_if.h" 14896f2e892SBill Paul 14996f2e892SBill Paul /* 15096f2e892SBill Paul * Various supported device vendors/types and their names. 15196f2e892SBill Paul */ 152ebc284ccSMarius Strobl static const struct dc_type dc_devs[] = { 1531e2e70b1SJohn Baldwin { DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143), 0, 15496f2e892SBill Paul "Intel 21143 10/100BaseTX" }, 1551e2e70b1SJohn Baldwin { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009), 0, 15638deb45fSTom Rhodes "Davicom DM9009 10/100BaseTX" }, 1571e2e70b1SJohn Baldwin { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100), 0, 15896f2e892SBill Paul "Davicom DM9100 10/100BaseTX" }, 1591e2e70b1SJohn Baldwin { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), DC_REVISION_DM9102A, 16088d739dcSBill Paul "Davicom DM9102A 10/100BaseTX" }, 1611e2e70b1SJohn Baldwin { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), 0, 1621e2e70b1SJohn Baldwin "Davicom DM9102 10/100BaseTX" }, 1631e2e70b1SJohn Baldwin { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981), 0, 16496f2e892SBill Paul "ADMtek AL981 10/100BaseTX" }, 165593a1aeaSMartin Blapp { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN983), 0, 166593a1aeaSMartin Blapp "ADMtek AN983 10/100BaseTX" }, 1671e2e70b1SJohn Baldwin { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985), 0, 168a2d61e43SWarner Losh "ADMtek AN985 CardBus 10/100BaseTX or clone" }, 1691e2e70b1SJohn Baldwin { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511), 0, 170e351d778SMartin Blapp "ADMtek ADM9511 10/100BaseTX" }, 1711e2e70b1SJohn Baldwin { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513), 0, 172e351d778SMartin Blapp "ADMtek ADM9513 10/100BaseTX" }, 1731e2e70b1SJohn Baldwin { DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), DC_REVISION_88141, 17496f2e892SBill Paul "ASIX AX88141 10/100BaseTX" }, 1751e2e70b1SJohn Baldwin { DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), 0, 1761e2e70b1SJohn Baldwin "ASIX AX88140A 10/100BaseTX" }, 1771e2e70b1SJohn Baldwin { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), DC_REVISION_98713A, 17896f2e892SBill Paul "Macronix 98713A 10/100BaseTX" }, 1791e2e70b1SJohn Baldwin { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), 0, 1801e2e70b1SJohn Baldwin "Macronix 98713 10/100BaseTX" }, 1811e2e70b1SJohn Baldwin { DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), DC_REVISION_98713A, 18296f2e892SBill Paul "Compex RL100-TX 10/100BaseTX" }, 1831e2e70b1SJohn Baldwin { DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), 0, 18496f2e892SBill Paul "Compex RL100-TX 10/100BaseTX" }, 1851e2e70b1SJohn Baldwin { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98725, 18696f2e892SBill Paul "Macronix 98725 10/100BaseTX" }, 1871e2e70b1SJohn Baldwin { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98715AEC_C, 1881e2e70b1SJohn Baldwin "Macronix 98715AEC-C 10/100BaseTX" }, 1891e2e70b1SJohn Baldwin { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), 0, 1901e2e70b1SJohn Baldwin "Macronix 98715/98715A 10/100BaseTX" }, 1911e2e70b1SJohn Baldwin { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727), 0, 192ead7cde9SBill Paul "Macronix 98727/98732 10/100BaseTX" }, 1931e2e70b1SJohn Baldwin { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115), 0, 19496f2e892SBill Paul "LC82C115 PNIC II 10/100BaseTX" }, 1951e2e70b1SJohn Baldwin { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), DC_REVISION_82C169, 19696f2e892SBill Paul "82c169 PNIC 10/100BaseTX" }, 1971e2e70b1SJohn Baldwin { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), 0, 1981e2e70b1SJohn Baldwin "82c168 PNIC 10/100BaseTX" }, 1991e2e70b1SJohn Baldwin { DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217), 0, 2009ca710f6SJeroen Ruigrok van der Werven "Accton EN1217 10/100BaseTX" }, 2011e2e70b1SJohn Baldwin { DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242), 0, 202fa167b8eSBill Paul "Accton EN2242 MiniPCI 10/100BaseTX" }, 2031e2e70b1SJohn Baldwin { DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201), 0, 204feb78939SJonathan Chen "Xircom X3201 10/100BaseTX" }, 2051e2e70b1SJohn Baldwin { DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD), 0, 2069be0993cSJohn Baldwin "Neteasy DRP-32TXD Cardbus 10/100" }, 2071e2e70b1SJohn Baldwin { DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500), 0, 2081d5e5310SBill Paul "Abocom FE2500 10/100BaseTX" }, 2091e2e70b1SJohn Baldwin { DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX), 0, 210773c505fSMIHIRA Sanpei Yoshiro "Abocom FE2500MX 10/100BaseTX" }, 2111e2e70b1SJohn Baldwin { DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112), 0, 2121af8bec7SBill Paul "Conexant LANfinity MiniPCI 10/100BaseTX" }, 2131e2e70b1SJohn Baldwin { DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX), 0, 214948c244dSWarner Losh "Hawking CB102 CardBus 10/100" }, 2151e2e70b1SJohn Baldwin { DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T), 0, 21697f91728SMIHIRA Sanpei Yoshiro "PlaneX FNW-3602-T CardBus 10/100" }, 2171e2e70b1SJohn Baldwin { DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB), 0, 2187eac366bSMartin Blapp "3Com OfficeConnect 10/100B" }, 2191e2e70b1SJohn Baldwin { DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120), 0, 220e7b9ab3aSBill Paul "Microsoft MN-120 CardBus 10/100" }, 2211e2e70b1SJohn Baldwin { DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130), 0, 222e7b9ab3aSBill Paul "Microsoft MN-130 10/100" }, 22317762569SGleb Smirnoff { DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08), 0, 22417762569SGleb Smirnoff "Linksys PCMPC200 CardBus 10/100" }, 22517762569SGleb Smirnoff { DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09), 0, 22617762569SGleb Smirnoff "Linksys PCMPC200 CardBus 10/100" }, 22796f2e892SBill Paul { 0, 0, NULL } 22896f2e892SBill Paul }; 22996f2e892SBill Paul 230e51a25f8SAlfred Perlstein static int dc_probe(device_t); 231e51a25f8SAlfred Perlstein static int dc_attach(device_t); 232e51a25f8SAlfred Perlstein static int dc_detach(device_t); 233e8388e14SMitsuru IWASAKI static int dc_suspend(device_t); 234e8388e14SMitsuru IWASAKI static int dc_resume(device_t); 235ebc284ccSMarius Strobl static const struct dc_type *dc_devtype(device_t); 23656e5e7aeSMaxime Henrion static int dc_newbuf(struct dc_softc *, int, int); 237a10c0e45SMike Silbersack static int dc_encap(struct dc_softc *, struct mbuf **); 238e51a25f8SAlfred Perlstein static void dc_pnic_rx_bug_war(struct dc_softc *, int); 239e51a25f8SAlfred Perlstein static int dc_rx_resync(struct dc_softc *); 2401abcdbd1SAttilio Rao static int dc_rxeof(struct dc_softc *); 241e51a25f8SAlfred Perlstein static void dc_txeof(struct dc_softc *); 242e51a25f8SAlfred Perlstein static void dc_tick(void *); 243e51a25f8SAlfred Perlstein static void dc_tx_underrun(struct dc_softc *); 244e51a25f8SAlfred Perlstein static void dc_intr(void *); 245e51a25f8SAlfred Perlstein static void dc_start(struct ifnet *); 246c8b27acaSJohn Baldwin static void dc_start_locked(struct ifnet *); 247e51a25f8SAlfred Perlstein static int dc_ioctl(struct ifnet *, u_long, caddr_t); 248e51a25f8SAlfred Perlstein static void dc_init(void *); 249c8b27acaSJohn Baldwin static void dc_init_locked(struct dc_softc *); 250e51a25f8SAlfred Perlstein static void dc_stop(struct dc_softc *); 251b1d16143SMarius Strobl static void dc_watchdog(void *); 2526a087a87SPyun YongHyeon static int dc_shutdown(device_t); 253e51a25f8SAlfred Perlstein static int dc_ifmedia_upd(struct ifnet *); 254e51a25f8SAlfred Perlstein static void dc_ifmedia_sts(struct ifnet *, struct ifmediareq *); 25596f2e892SBill Paul 256e51a25f8SAlfred Perlstein static void dc_delay(struct dc_softc *); 257e51a25f8SAlfred Perlstein static void dc_eeprom_idle(struct dc_softc *); 258e51a25f8SAlfred Perlstein static void dc_eeprom_putbyte(struct dc_softc *, int); 259e51a25f8SAlfred Perlstein static void dc_eeprom_getword(struct dc_softc *, int, u_int16_t *); 260d24ae19dSWarner Losh static void dc_eeprom_getword_pnic(struct dc_softc *, int, u_int16_t *); 261d24ae19dSWarner Losh static void dc_eeprom_getword_xircom(struct dc_softc *, int, u_int16_t *); 2623097aa70SWarner Losh static void dc_eeprom_width(struct dc_softc *); 263e51a25f8SAlfred Perlstein static void dc_read_eeprom(struct dc_softc *, caddr_t, int, int, int); 26496f2e892SBill Paul 265e51a25f8SAlfred Perlstein static void dc_mii_writebit(struct dc_softc *, int); 266e51a25f8SAlfred Perlstein static int dc_mii_readbit(struct dc_softc *); 267e51a25f8SAlfred Perlstein static void dc_mii_sync(struct dc_softc *); 268e51a25f8SAlfred Perlstein static void dc_mii_send(struct dc_softc *, u_int32_t, int); 269e51a25f8SAlfred Perlstein static int dc_mii_readreg(struct dc_softc *, struct dc_mii_frame *); 270e51a25f8SAlfred Perlstein static int dc_mii_writereg(struct dc_softc *, struct dc_mii_frame *); 271e51a25f8SAlfred Perlstein static int dc_miibus_readreg(device_t, int, int); 272e51a25f8SAlfred Perlstein static int dc_miibus_writereg(device_t, int, int, int); 273e51a25f8SAlfred Perlstein static void dc_miibus_statchg(device_t); 274e51a25f8SAlfred Perlstein static void dc_miibus_mediainit(device_t); 27596f2e892SBill Paul 276e51a25f8SAlfred Perlstein static void dc_setcfg(struct dc_softc *, int); 2773373489bSWarner Losh static uint32_t dc_mchash_le(struct dc_softc *, const uint8_t *); 2783373489bSWarner Losh static uint32_t dc_mchash_be(const uint8_t *); 279e51a25f8SAlfred Perlstein static void dc_setfilt_21143(struct dc_softc *); 280e51a25f8SAlfred Perlstein static void dc_setfilt_asix(struct dc_softc *); 281e51a25f8SAlfred Perlstein static void dc_setfilt_admtek(struct dc_softc *); 282e51a25f8SAlfred Perlstein static void dc_setfilt_xircom(struct dc_softc *); 28396f2e892SBill Paul 284e51a25f8SAlfred Perlstein static void dc_setfilt(struct dc_softc *); 28596f2e892SBill Paul 286e51a25f8SAlfred Perlstein static void dc_reset(struct dc_softc *); 287e51a25f8SAlfred Perlstein static int dc_list_rx_init(struct dc_softc *); 288e51a25f8SAlfred Perlstein static int dc_list_tx_init(struct dc_softc *); 28996f2e892SBill Paul 290abe4e865SPyun YongHyeon static int dc_read_srom(struct dc_softc *, int); 291abe4e865SPyun YongHyeon static int dc_parse_21143_srom(struct dc_softc *); 292abe4e865SPyun YongHyeon static int dc_decode_leaf_sia(struct dc_softc *, struct dc_eblock_sia *); 293abe4e865SPyun YongHyeon static int dc_decode_leaf_mii(struct dc_softc *, struct dc_eblock_mii *); 294abe4e865SPyun YongHyeon static int dc_decode_leaf_sym(struct dc_softc *, struct dc_eblock_sym *); 295e51a25f8SAlfred Perlstein static void dc_apply_fixup(struct dc_softc *, int); 29639d76ed6SPyun YongHyeon static int dc_check_multiport(struct dc_softc *); 2975c1cfac4SBill Paul 29896f2e892SBill Paul #ifdef DC_USEIOSPACE 29996f2e892SBill Paul #define DC_RES SYS_RES_IOPORT 30096f2e892SBill Paul #define DC_RID DC_PCI_CFBIO 30196f2e892SBill Paul #else 30296f2e892SBill Paul #define DC_RES SYS_RES_MEMORY 30396f2e892SBill Paul #define DC_RID DC_PCI_CFBMA 30496f2e892SBill Paul #endif 30596f2e892SBill Paul 30696f2e892SBill Paul static device_method_t dc_methods[] = { 30796f2e892SBill Paul /* Device interface */ 30896f2e892SBill Paul DEVMETHOD(device_probe, dc_probe), 30996f2e892SBill Paul DEVMETHOD(device_attach, dc_attach), 31096f2e892SBill Paul DEVMETHOD(device_detach, dc_detach), 311e8388e14SMitsuru IWASAKI DEVMETHOD(device_suspend, dc_suspend), 312e8388e14SMitsuru IWASAKI DEVMETHOD(device_resume, dc_resume), 31396f2e892SBill Paul DEVMETHOD(device_shutdown, dc_shutdown), 31496f2e892SBill Paul 31596f2e892SBill Paul /* bus interface */ 31696f2e892SBill Paul DEVMETHOD(bus_print_child, bus_generic_print_child), 31796f2e892SBill Paul DEVMETHOD(bus_driver_added, bus_generic_driver_added), 31896f2e892SBill Paul 31996f2e892SBill Paul /* MII interface */ 32096f2e892SBill Paul DEVMETHOD(miibus_readreg, dc_miibus_readreg), 32196f2e892SBill Paul DEVMETHOD(miibus_writereg, dc_miibus_writereg), 32296f2e892SBill Paul DEVMETHOD(miibus_statchg, dc_miibus_statchg), 323f43d9309SBill Paul DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 32496f2e892SBill Paul 32596f2e892SBill Paul { 0, 0 } 32696f2e892SBill Paul }; 32796f2e892SBill Paul 32896f2e892SBill Paul static driver_t dc_driver = { 32996f2e892SBill Paul "dc", 33096f2e892SBill Paul dc_methods, 33196f2e892SBill Paul sizeof(struct dc_softc) 33296f2e892SBill Paul }; 33396f2e892SBill Paul 33496f2e892SBill Paul static devclass_t dc_devclass; 33596f2e892SBill Paul 336f246e4a1SMatthew N. Dodd DRIVER_MODULE(dc, pci, dc_driver, dc_devclass, 0, 0); 33796f2e892SBill Paul DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 33896f2e892SBill Paul 33996f2e892SBill Paul #define DC_SETBIT(sc, reg, x) \ 34096f2e892SBill Paul CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 34196f2e892SBill Paul 34296f2e892SBill Paul #define DC_CLRBIT(sc, reg, x) \ 34396f2e892SBill Paul CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 34496f2e892SBill Paul 34596f2e892SBill Paul #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 34696f2e892SBill Paul #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 34796f2e892SBill Paul 348e3d2833aSAlfred Perlstein static void 3490934f18aSMaxime Henrion dc_delay(struct dc_softc *sc) 35096f2e892SBill Paul { 35196f2e892SBill Paul int idx; 35296f2e892SBill Paul 35396f2e892SBill Paul for (idx = (300 / 33) + 1; idx > 0; idx--) 35496f2e892SBill Paul CSR_READ_4(sc, DC_BUSCTL); 35596f2e892SBill Paul } 35696f2e892SBill Paul 3572c876e15SPoul-Henning Kamp static void 3580934f18aSMaxime Henrion dc_eeprom_width(struct dc_softc *sc) 3593097aa70SWarner Losh { 3603097aa70SWarner Losh int i; 3613097aa70SWarner Losh 3623097aa70SWarner Losh /* Force EEPROM to idle state. */ 3633097aa70SWarner Losh dc_eeprom_idle(sc); 3643097aa70SWarner Losh 3653097aa70SWarner Losh /* Enter EEPROM access mode. */ 3663097aa70SWarner Losh CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 3673097aa70SWarner Losh dc_delay(sc); 3683097aa70SWarner Losh DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 3693097aa70SWarner Losh dc_delay(sc); 3703097aa70SWarner Losh DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 3713097aa70SWarner Losh dc_delay(sc); 3723097aa70SWarner Losh DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 3733097aa70SWarner Losh dc_delay(sc); 3743097aa70SWarner Losh 3753097aa70SWarner Losh for (i = 3; i--;) { 3763097aa70SWarner Losh if (6 & (1 << i)) 3773097aa70SWarner Losh DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 3783097aa70SWarner Losh else 3793097aa70SWarner Losh DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 3803097aa70SWarner Losh dc_delay(sc); 3813097aa70SWarner Losh DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 3823097aa70SWarner Losh dc_delay(sc); 3833097aa70SWarner Losh DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 3843097aa70SWarner Losh dc_delay(sc); 3853097aa70SWarner Losh } 3863097aa70SWarner Losh 3873097aa70SWarner Losh for (i = 1; i <= 12; i++) { 3883097aa70SWarner Losh DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 3893097aa70SWarner Losh dc_delay(sc); 3903097aa70SWarner Losh if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { 3913097aa70SWarner Losh DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 3923097aa70SWarner Losh dc_delay(sc); 3933097aa70SWarner Losh break; 3943097aa70SWarner Losh } 3953097aa70SWarner Losh DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 3963097aa70SWarner Losh dc_delay(sc); 3973097aa70SWarner Losh } 3983097aa70SWarner Losh 3993097aa70SWarner Losh /* Turn off EEPROM access mode. */ 4003097aa70SWarner Losh dc_eeprom_idle(sc); 4013097aa70SWarner Losh 4023097aa70SWarner Losh if (i < 4 || i > 12) 4033097aa70SWarner Losh sc->dc_romwidth = 6; 4043097aa70SWarner Losh else 4053097aa70SWarner Losh sc->dc_romwidth = i; 4063097aa70SWarner Losh 4073097aa70SWarner Losh /* Enter EEPROM access mode. */ 4083097aa70SWarner Losh CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 4093097aa70SWarner Losh dc_delay(sc); 4103097aa70SWarner Losh DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 4113097aa70SWarner Losh dc_delay(sc); 4123097aa70SWarner Losh DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 4133097aa70SWarner Losh dc_delay(sc); 4143097aa70SWarner Losh DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 4153097aa70SWarner Losh dc_delay(sc); 4163097aa70SWarner Losh 4173097aa70SWarner Losh /* Turn off EEPROM access mode. */ 4183097aa70SWarner Losh dc_eeprom_idle(sc); 4193097aa70SWarner Losh } 4203097aa70SWarner Losh 421e3d2833aSAlfred Perlstein static void 4220934f18aSMaxime Henrion dc_eeprom_idle(struct dc_softc *sc) 42396f2e892SBill Paul { 4240934f18aSMaxime Henrion int i; 42596f2e892SBill Paul 42696f2e892SBill Paul CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 42796f2e892SBill Paul dc_delay(sc); 42896f2e892SBill Paul DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 42996f2e892SBill Paul dc_delay(sc); 43096f2e892SBill Paul DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 43196f2e892SBill Paul dc_delay(sc); 43296f2e892SBill Paul DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 43396f2e892SBill Paul dc_delay(sc); 43496f2e892SBill Paul 43596f2e892SBill Paul for (i = 0; i < 25; i++) { 43696f2e892SBill Paul DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 43796f2e892SBill Paul dc_delay(sc); 43896f2e892SBill Paul DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 43996f2e892SBill Paul dc_delay(sc); 44096f2e892SBill Paul } 44196f2e892SBill Paul 44296f2e892SBill Paul DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 44396f2e892SBill Paul dc_delay(sc); 44496f2e892SBill Paul DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 44596f2e892SBill Paul dc_delay(sc); 44696f2e892SBill Paul CSR_WRITE_4(sc, DC_SIO, 0x00000000); 44796f2e892SBill Paul } 44896f2e892SBill Paul 44996f2e892SBill Paul /* 45096f2e892SBill Paul * Send a read command and address to the EEPROM, check for ACK. 45196f2e892SBill Paul */ 452e3d2833aSAlfred Perlstein static void 4530934f18aSMaxime Henrion dc_eeprom_putbyte(struct dc_softc *sc, int addr) 45496f2e892SBill Paul { 4550934f18aSMaxime Henrion int d, i; 45696f2e892SBill Paul 4573097aa70SWarner Losh d = DC_EECMD_READ >> 6; 4583097aa70SWarner Losh for (i = 3; i--; ) { 4593097aa70SWarner Losh if (d & (1 << i)) 4603097aa70SWarner Losh DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 46196f2e892SBill Paul else 4623097aa70SWarner Losh DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 4633097aa70SWarner Losh dc_delay(sc); 4643097aa70SWarner Losh DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 4653097aa70SWarner Losh dc_delay(sc); 4663097aa70SWarner Losh DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 4673097aa70SWarner Losh dc_delay(sc); 4683097aa70SWarner Losh } 46996f2e892SBill Paul 47096f2e892SBill Paul /* 47196f2e892SBill Paul * Feed in each bit and strobe the clock. 47296f2e892SBill Paul */ 4733097aa70SWarner Losh for (i = sc->dc_romwidth; i--;) { 4743097aa70SWarner Losh if (addr & (1 << i)) { 47596f2e892SBill Paul SIO_SET(DC_SIO_EE_DATAIN); 47696f2e892SBill Paul } else { 47796f2e892SBill Paul SIO_CLR(DC_SIO_EE_DATAIN); 47896f2e892SBill Paul } 47996f2e892SBill Paul dc_delay(sc); 48096f2e892SBill Paul SIO_SET(DC_SIO_EE_CLK); 48196f2e892SBill Paul dc_delay(sc); 48296f2e892SBill Paul SIO_CLR(DC_SIO_EE_CLK); 48396f2e892SBill Paul dc_delay(sc); 48496f2e892SBill Paul } 48596f2e892SBill Paul } 48696f2e892SBill Paul 48796f2e892SBill Paul /* 48896f2e892SBill Paul * Read a word of data stored in the EEPROM at address 'addr.' 48996f2e892SBill Paul * The PNIC 82c168/82c169 has its own non-standard way to read 49096f2e892SBill Paul * the EEPROM. 49196f2e892SBill Paul */ 492e3d2833aSAlfred Perlstein static void 4930934f18aSMaxime Henrion dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, u_int16_t *dest) 49496f2e892SBill Paul { 4950934f18aSMaxime Henrion int i; 49696f2e892SBill Paul u_int32_t r; 49796f2e892SBill Paul 49896f2e892SBill Paul CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr); 49996f2e892SBill Paul 50096f2e892SBill Paul for (i = 0; i < DC_TIMEOUT; i++) { 50196f2e892SBill Paul DELAY(1); 50296f2e892SBill Paul r = CSR_READ_4(sc, DC_SIO); 50396f2e892SBill Paul if (!(r & DC_PN_SIOCTL_BUSY)) { 50496f2e892SBill Paul *dest = (u_int16_t)(r & 0xFFFF); 50596f2e892SBill Paul return; 50696f2e892SBill Paul } 50796f2e892SBill Paul } 50896f2e892SBill Paul } 50996f2e892SBill Paul 51096f2e892SBill Paul /* 51196f2e892SBill Paul * Read a word of data stored in the EEPROM at address 'addr.' 512feb78939SJonathan Chen * The Xircom X3201 has its own non-standard way to read 513feb78939SJonathan Chen * the EEPROM, too. 514feb78939SJonathan Chen */ 515e3d2833aSAlfred Perlstein static void 5160934f18aSMaxime Henrion dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, u_int16_t *dest) 517feb78939SJonathan Chen { 5180934f18aSMaxime Henrion 519feb78939SJonathan Chen SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 520feb78939SJonathan Chen 521feb78939SJonathan Chen addr *= 2; 522feb78939SJonathan Chen CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 523feb78939SJonathan Chen *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff; 524feb78939SJonathan Chen addr += 1; 525feb78939SJonathan Chen CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 526feb78939SJonathan Chen *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8; 527feb78939SJonathan Chen 528feb78939SJonathan Chen SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 529feb78939SJonathan Chen } 530feb78939SJonathan Chen 531feb78939SJonathan Chen /* 532feb78939SJonathan Chen * Read a word of data stored in the EEPROM at address 'addr.' 53396f2e892SBill Paul */ 534e3d2833aSAlfred Perlstein static void 5350934f18aSMaxime Henrion dc_eeprom_getword(struct dc_softc *sc, int addr, u_int16_t *dest) 53696f2e892SBill Paul { 5370934f18aSMaxime Henrion int i; 53896f2e892SBill Paul u_int16_t word = 0; 53996f2e892SBill Paul 54096f2e892SBill Paul /* Force EEPROM to idle state. */ 54196f2e892SBill Paul dc_eeprom_idle(sc); 54296f2e892SBill Paul 54396f2e892SBill Paul /* Enter EEPROM access mode. */ 54496f2e892SBill Paul CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 54596f2e892SBill Paul dc_delay(sc); 54696f2e892SBill Paul DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 54796f2e892SBill Paul dc_delay(sc); 54896f2e892SBill Paul DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 54996f2e892SBill Paul dc_delay(sc); 55096f2e892SBill Paul DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 55196f2e892SBill Paul dc_delay(sc); 55296f2e892SBill Paul 55396f2e892SBill Paul /* 55496f2e892SBill Paul * Send address of word we want to read. 55596f2e892SBill Paul */ 55696f2e892SBill Paul dc_eeprom_putbyte(sc, addr); 55796f2e892SBill Paul 55896f2e892SBill Paul /* 55996f2e892SBill Paul * Start reading bits from EEPROM. 56096f2e892SBill Paul */ 56196f2e892SBill Paul for (i = 0x8000; i; i >>= 1) { 56296f2e892SBill Paul SIO_SET(DC_SIO_EE_CLK); 56396f2e892SBill Paul dc_delay(sc); 56496f2e892SBill Paul if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 56596f2e892SBill Paul word |= i; 56696f2e892SBill Paul dc_delay(sc); 56796f2e892SBill Paul SIO_CLR(DC_SIO_EE_CLK); 56896f2e892SBill Paul dc_delay(sc); 56996f2e892SBill Paul } 57096f2e892SBill Paul 57196f2e892SBill Paul /* Turn off EEPROM access mode. */ 57296f2e892SBill Paul dc_eeprom_idle(sc); 57396f2e892SBill Paul 57496f2e892SBill Paul *dest = word; 57596f2e892SBill Paul } 57696f2e892SBill Paul 57796f2e892SBill Paul /* 57896f2e892SBill Paul * Read a sequence of words from the EEPROM. 57996f2e892SBill Paul */ 580e3d2833aSAlfred Perlstein static void 5818c7ff1f3SMaxime Henrion dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int be) 58296f2e892SBill Paul { 58396f2e892SBill Paul int i; 58496f2e892SBill Paul u_int16_t word = 0, *ptr; 58596f2e892SBill Paul 58696f2e892SBill Paul for (i = 0; i < cnt; i++) { 58796f2e892SBill Paul if (DC_IS_PNIC(sc)) 58896f2e892SBill Paul dc_eeprom_getword_pnic(sc, off + i, &word); 589feb78939SJonathan Chen else if (DC_IS_XIRCOM(sc)) 590feb78939SJonathan Chen dc_eeprom_getword_xircom(sc, off + i, &word); 59196f2e892SBill Paul else 59296f2e892SBill Paul dc_eeprom_getword(sc, off + i, &word); 59396f2e892SBill Paul ptr = (u_int16_t *)(dest + (i * 2)); 5948c7ff1f3SMaxime Henrion if (be) 5958c7ff1f3SMaxime Henrion *ptr = be16toh(word); 59696f2e892SBill Paul else 5978c7ff1f3SMaxime Henrion *ptr = le16toh(word); 59896f2e892SBill Paul } 59996f2e892SBill Paul } 60096f2e892SBill Paul 60196f2e892SBill Paul /* 60296f2e892SBill Paul * The following two routines are taken from the Macronix 98713 60396f2e892SBill Paul * Application Notes pp.19-21. 60496f2e892SBill Paul */ 60596f2e892SBill Paul /* 60696f2e892SBill Paul * Write a bit to the MII bus. 60796f2e892SBill Paul */ 608e3d2833aSAlfred Perlstein static void 6090934f18aSMaxime Henrion dc_mii_writebit(struct dc_softc *sc, int bit) 61096f2e892SBill Paul { 61115578119SMarius Strobl uint32_t reg; 6120934f18aSMaxime Henrion 61315578119SMarius Strobl reg = DC_SIO_ROMCTL_WRITE | (bit != 0 ? DC_SIO_MII_DATAOUT : 0); 61415578119SMarius Strobl CSR_WRITE_4(sc, DC_SIO, reg); 61515578119SMarius Strobl CSR_BARRIER_4(sc, DC_SIO, 61615578119SMarius Strobl BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 61715578119SMarius Strobl DELAY(1); 61896f2e892SBill Paul 61915578119SMarius Strobl CSR_WRITE_4(sc, DC_SIO, reg | DC_SIO_MII_CLK); 62015578119SMarius Strobl CSR_BARRIER_4(sc, DC_SIO, 62115578119SMarius Strobl BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 62215578119SMarius Strobl DELAY(1); 62315578119SMarius Strobl CSR_WRITE_4(sc, DC_SIO, reg); 62415578119SMarius Strobl CSR_BARRIER_4(sc, DC_SIO, 62515578119SMarius Strobl BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 62615578119SMarius Strobl DELAY(1); 62796f2e892SBill Paul } 62896f2e892SBill Paul 62996f2e892SBill Paul /* 63096f2e892SBill Paul * Read a bit from the MII bus. 63196f2e892SBill Paul */ 632e3d2833aSAlfred Perlstein static int 6330934f18aSMaxime Henrion dc_mii_readbit(struct dc_softc *sc) 63496f2e892SBill Paul { 63515578119SMarius Strobl uint32_t reg; 6360934f18aSMaxime Henrion 63715578119SMarius Strobl reg = DC_SIO_ROMCTL_READ | DC_SIO_MII_DIR; 63815578119SMarius Strobl CSR_WRITE_4(sc, DC_SIO, reg); 63915578119SMarius Strobl CSR_BARRIER_4(sc, DC_SIO, 64015578119SMarius Strobl BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 64115578119SMarius Strobl DELAY(1); 64215578119SMarius Strobl (void)CSR_READ_4(sc, DC_SIO); 64315578119SMarius Strobl CSR_WRITE_4(sc, DC_SIO, reg | DC_SIO_MII_CLK); 64415578119SMarius Strobl CSR_BARRIER_4(sc, DC_SIO, 64515578119SMarius Strobl BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 64615578119SMarius Strobl DELAY(1); 64715578119SMarius Strobl CSR_WRITE_4(sc, DC_SIO, reg); 64815578119SMarius Strobl CSR_BARRIER_4(sc, DC_SIO, 64915578119SMarius Strobl BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 65015578119SMarius Strobl DELAY(1); 65196f2e892SBill Paul if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 65296f2e892SBill Paul return (1); 65396f2e892SBill Paul 65496f2e892SBill Paul return (0); 65596f2e892SBill Paul } 65696f2e892SBill Paul 65796f2e892SBill Paul /* 65896f2e892SBill Paul * Sync the PHYs by setting data bit and strobing the clock 32 times. 65996f2e892SBill Paul */ 660e3d2833aSAlfred Perlstein static void 6610934f18aSMaxime Henrion dc_mii_sync(struct dc_softc *sc) 66296f2e892SBill Paul { 6630934f18aSMaxime Henrion int i; 66496f2e892SBill Paul 66596f2e892SBill Paul CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 66615578119SMarius Strobl CSR_BARRIER_4(sc, DC_SIO, 66715578119SMarius Strobl BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 66815578119SMarius Strobl DELAY(1); 66996f2e892SBill Paul 67096f2e892SBill Paul for (i = 0; i < 32; i++) 67196f2e892SBill Paul dc_mii_writebit(sc, 1); 67296f2e892SBill Paul } 67396f2e892SBill Paul 67496f2e892SBill Paul /* 67596f2e892SBill Paul * Clock a series of bits through the MII. 67696f2e892SBill Paul */ 677e3d2833aSAlfred Perlstein static void 6780934f18aSMaxime Henrion dc_mii_send(struct dc_softc *sc, u_int32_t bits, int cnt) 67996f2e892SBill Paul { 68096f2e892SBill Paul int i; 68196f2e892SBill Paul 68296f2e892SBill Paul for (i = (0x1 << (cnt - 1)); i; i >>= 1) 68396f2e892SBill Paul dc_mii_writebit(sc, bits & i); 68496f2e892SBill Paul } 68596f2e892SBill Paul 68696f2e892SBill Paul /* 68796f2e892SBill Paul * Read an PHY register through the MII. 68896f2e892SBill Paul */ 689e3d2833aSAlfred Perlstein static int 6900934f18aSMaxime Henrion dc_mii_readreg(struct dc_softc *sc, struct dc_mii_frame *frame) 69196f2e892SBill Paul { 69215578119SMarius Strobl int i; 69396f2e892SBill Paul 69496f2e892SBill Paul /* 69596f2e892SBill Paul * Set up frame for RX. 69696f2e892SBill Paul */ 69796f2e892SBill Paul frame->mii_stdelim = DC_MII_STARTDELIM; 69896f2e892SBill Paul frame->mii_opcode = DC_MII_READOP; 69996f2e892SBill Paul 70096f2e892SBill Paul /* 70196f2e892SBill Paul * Sync the PHYs. 70296f2e892SBill Paul */ 70396f2e892SBill Paul dc_mii_sync(sc); 70496f2e892SBill Paul 70596f2e892SBill Paul /* 70696f2e892SBill Paul * Send command/address info. 70796f2e892SBill Paul */ 70896f2e892SBill Paul dc_mii_send(sc, frame->mii_stdelim, 2); 70996f2e892SBill Paul dc_mii_send(sc, frame->mii_opcode, 2); 71096f2e892SBill Paul dc_mii_send(sc, frame->mii_phyaddr, 5); 71196f2e892SBill Paul dc_mii_send(sc, frame->mii_regaddr, 5); 71296f2e892SBill Paul 71396f2e892SBill Paul /* 71415578119SMarius Strobl * Now try reading data bits. If the turnaround failed, we still 71596f2e892SBill Paul * need to clock through 16 cycles to keep the PHY(s) in sync. 71696f2e892SBill Paul */ 71715578119SMarius Strobl frame->mii_turnaround = dc_mii_readbit(sc); 71815578119SMarius Strobl if (frame->mii_turnaround != 0) { 7190934f18aSMaxime Henrion for (i = 0; i < 16; i++) 72096f2e892SBill Paul dc_mii_readbit(sc); 72196f2e892SBill Paul goto fail; 72296f2e892SBill Paul } 72396f2e892SBill Paul for (i = 0x8000; i; i >>= 1) { 72496f2e892SBill Paul if (dc_mii_readbit(sc)) 72596f2e892SBill Paul frame->mii_data |= i; 72696f2e892SBill Paul } 72796f2e892SBill Paul 72896f2e892SBill Paul fail: 72996f2e892SBill Paul 73015578119SMarius Strobl /* Clock the idle bits. */ 73196f2e892SBill Paul dc_mii_writebit(sc, 0); 73296f2e892SBill Paul dc_mii_writebit(sc, 0); 73396f2e892SBill Paul 73415578119SMarius Strobl if (frame->mii_turnaround != 0) 73596f2e892SBill Paul return (1); 73696f2e892SBill Paul return (0); 73796f2e892SBill Paul } 73896f2e892SBill Paul 73996f2e892SBill Paul /* 74096f2e892SBill Paul * Write to a PHY register through the MII. 74196f2e892SBill Paul */ 742e3d2833aSAlfred Perlstein static int 7430934f18aSMaxime Henrion dc_mii_writereg(struct dc_softc *sc, struct dc_mii_frame *frame) 74496f2e892SBill Paul { 7450934f18aSMaxime Henrion 74696f2e892SBill Paul /* 74796f2e892SBill Paul * Set up frame for TX. 74896f2e892SBill Paul */ 74996f2e892SBill Paul frame->mii_stdelim = DC_MII_STARTDELIM; 75096f2e892SBill Paul frame->mii_opcode = DC_MII_WRITEOP; 75196f2e892SBill Paul frame->mii_turnaround = DC_MII_TURNAROUND; 75296f2e892SBill Paul 75396f2e892SBill Paul /* 75496f2e892SBill Paul * Sync the PHYs. 75596f2e892SBill Paul */ 75696f2e892SBill Paul dc_mii_sync(sc); 75796f2e892SBill Paul 75896f2e892SBill Paul dc_mii_send(sc, frame->mii_stdelim, 2); 75996f2e892SBill Paul dc_mii_send(sc, frame->mii_opcode, 2); 76096f2e892SBill Paul dc_mii_send(sc, frame->mii_phyaddr, 5); 76196f2e892SBill Paul dc_mii_send(sc, frame->mii_regaddr, 5); 76296f2e892SBill Paul dc_mii_send(sc, frame->mii_turnaround, 2); 76396f2e892SBill Paul dc_mii_send(sc, frame->mii_data, 16); 76496f2e892SBill Paul 76515578119SMarius Strobl /* Clock the idle bits. */ 76696f2e892SBill Paul dc_mii_writebit(sc, 0); 76796f2e892SBill Paul dc_mii_writebit(sc, 0); 76896f2e892SBill Paul 76996f2e892SBill Paul return (0); 77096f2e892SBill Paul } 77196f2e892SBill Paul 772e3d2833aSAlfred Perlstein static int 7730934f18aSMaxime Henrion dc_miibus_readreg(device_t dev, int phy, int reg) 77496f2e892SBill Paul { 77596f2e892SBill Paul struct dc_mii_frame frame; 77696f2e892SBill Paul struct dc_softc *sc; 777c85c4667SBill Paul int i, rval, phy_reg = 0; 77896f2e892SBill Paul 77996f2e892SBill Paul sc = device_get_softc(dev); 7800934f18aSMaxime Henrion bzero(&frame, sizeof(frame)); 78196f2e892SBill Paul 7825c1cfac4SBill Paul if (sc->dc_pmode != DC_PMODE_MII) { 78396f2e892SBill Paul if (phy == (MII_NPHY - 1)) { 78496f2e892SBill Paul switch (reg) { 78596f2e892SBill Paul case MII_BMSR: 78696f2e892SBill Paul /* 78796f2e892SBill Paul * Fake something to make the probe 78896f2e892SBill Paul * code think there's a PHY here. 78996f2e892SBill Paul */ 79096f2e892SBill Paul return (BMSR_MEDIAMASK); 79196f2e892SBill Paul break; 79296f2e892SBill Paul case MII_PHYIDR1: 79396f2e892SBill Paul if (DC_IS_PNIC(sc)) 79496f2e892SBill Paul return (DC_VENDORID_LO); 79596f2e892SBill Paul return (DC_VENDORID_DEC); 79696f2e892SBill Paul break; 79796f2e892SBill Paul case MII_PHYIDR2: 79896f2e892SBill Paul if (DC_IS_PNIC(sc)) 79996f2e892SBill Paul return (DC_DEVICEID_82C168); 80096f2e892SBill Paul return (DC_DEVICEID_21143); 80196f2e892SBill Paul break; 80296f2e892SBill Paul default: 80396f2e892SBill Paul return (0); 80496f2e892SBill Paul break; 80596f2e892SBill Paul } 80696f2e892SBill Paul } else 80796f2e892SBill Paul return (0); 80896f2e892SBill Paul } 80996f2e892SBill Paul 81096f2e892SBill Paul if (DC_IS_PNIC(sc)) { 81196f2e892SBill Paul CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 81296f2e892SBill Paul (phy << 23) | (reg << 18)); 81396f2e892SBill Paul for (i = 0; i < DC_TIMEOUT; i++) { 81496f2e892SBill Paul DELAY(1); 81596f2e892SBill Paul rval = CSR_READ_4(sc, DC_PN_MII); 81696f2e892SBill Paul if (!(rval & DC_PN_MII_BUSY)) { 81796f2e892SBill Paul rval &= 0xFFFF; 81896f2e892SBill Paul return (rval == 0xFFFF ? 0 : rval); 81996f2e892SBill Paul } 82096f2e892SBill Paul } 82196f2e892SBill Paul return (0); 82296f2e892SBill Paul } 82396f2e892SBill Paul 82496f2e892SBill Paul if (DC_IS_COMET(sc)) { 82596f2e892SBill Paul switch (reg) { 82696f2e892SBill Paul case MII_BMCR: 82796f2e892SBill Paul phy_reg = DC_AL_BMCR; 82896f2e892SBill Paul break; 82996f2e892SBill Paul case MII_BMSR: 83096f2e892SBill Paul phy_reg = DC_AL_BMSR; 83196f2e892SBill Paul break; 83296f2e892SBill Paul case MII_PHYIDR1: 83396f2e892SBill Paul phy_reg = DC_AL_VENID; 83496f2e892SBill Paul break; 83596f2e892SBill Paul case MII_PHYIDR2: 83696f2e892SBill Paul phy_reg = DC_AL_DEVID; 83796f2e892SBill Paul break; 83896f2e892SBill Paul case MII_ANAR: 83996f2e892SBill Paul phy_reg = DC_AL_ANAR; 84096f2e892SBill Paul break; 84196f2e892SBill Paul case MII_ANLPAR: 84296f2e892SBill Paul phy_reg = DC_AL_LPAR; 84396f2e892SBill Paul break; 84496f2e892SBill Paul case MII_ANER: 84596f2e892SBill Paul phy_reg = DC_AL_ANER; 84696f2e892SBill Paul break; 84796f2e892SBill Paul default: 84822f6205dSJohn Baldwin device_printf(dev, "phy_read: bad phy register %x\n", 84922f6205dSJohn Baldwin reg); 85096f2e892SBill Paul return (0); 85196f2e892SBill Paul break; 85296f2e892SBill Paul } 85396f2e892SBill Paul 85496f2e892SBill Paul rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 85596f2e892SBill Paul 85696f2e892SBill Paul if (rval == 0xFFFF) 85796f2e892SBill Paul return (0); 85896f2e892SBill Paul return (rval); 85996f2e892SBill Paul } 86096f2e892SBill Paul 86196f2e892SBill Paul frame.mii_phyaddr = phy; 86296f2e892SBill Paul frame.mii_regaddr = reg; 863419146d9SBill Paul if (sc->dc_type == DC_TYPE_98713) { 864f43d9309SBill Paul phy_reg = CSR_READ_4(sc, DC_NETCFG); 865f43d9309SBill Paul CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 866419146d9SBill Paul } 86796f2e892SBill Paul dc_mii_readreg(sc, &frame); 868419146d9SBill Paul if (sc->dc_type == DC_TYPE_98713) 869f43d9309SBill Paul CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 87096f2e892SBill Paul 87196f2e892SBill Paul return (frame.mii_data); 87296f2e892SBill Paul } 87396f2e892SBill Paul 874e3d2833aSAlfred Perlstein static int 8750934f18aSMaxime Henrion dc_miibus_writereg(device_t dev, int phy, int reg, int data) 87696f2e892SBill Paul { 87796f2e892SBill Paul struct dc_softc *sc; 87896f2e892SBill Paul struct dc_mii_frame frame; 879c85c4667SBill Paul int i, phy_reg = 0; 88096f2e892SBill Paul 88196f2e892SBill Paul sc = device_get_softc(dev); 8820934f18aSMaxime Henrion bzero(&frame, sizeof(frame)); 88396f2e892SBill Paul 88496f2e892SBill Paul if (DC_IS_PNIC(sc)) { 88596f2e892SBill Paul CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 88696f2e892SBill Paul (phy << 23) | (reg << 10) | data); 88796f2e892SBill Paul for (i = 0; i < DC_TIMEOUT; i++) { 88896f2e892SBill Paul if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 88996f2e892SBill Paul break; 89096f2e892SBill Paul } 89196f2e892SBill Paul return (0); 89296f2e892SBill Paul } 89396f2e892SBill Paul 89496f2e892SBill Paul if (DC_IS_COMET(sc)) { 89596f2e892SBill Paul switch (reg) { 89696f2e892SBill Paul case MII_BMCR: 89796f2e892SBill Paul phy_reg = DC_AL_BMCR; 89896f2e892SBill Paul break; 89996f2e892SBill Paul case MII_BMSR: 90096f2e892SBill Paul phy_reg = DC_AL_BMSR; 90196f2e892SBill Paul break; 90296f2e892SBill Paul case MII_PHYIDR1: 90396f2e892SBill Paul phy_reg = DC_AL_VENID; 90496f2e892SBill Paul break; 90596f2e892SBill Paul case MII_PHYIDR2: 90696f2e892SBill Paul phy_reg = DC_AL_DEVID; 90796f2e892SBill Paul break; 90896f2e892SBill Paul case MII_ANAR: 90996f2e892SBill Paul phy_reg = DC_AL_ANAR; 91096f2e892SBill Paul break; 91196f2e892SBill Paul case MII_ANLPAR: 91296f2e892SBill Paul phy_reg = DC_AL_LPAR; 91396f2e892SBill Paul break; 91496f2e892SBill Paul case MII_ANER: 91596f2e892SBill Paul phy_reg = DC_AL_ANER; 91696f2e892SBill Paul break; 91796f2e892SBill Paul default: 91822f6205dSJohn Baldwin device_printf(dev, "phy_write: bad phy register %x\n", 91922f6205dSJohn Baldwin reg); 92096f2e892SBill Paul return (0); 92196f2e892SBill Paul break; 92296f2e892SBill Paul } 92396f2e892SBill Paul 92496f2e892SBill Paul CSR_WRITE_4(sc, phy_reg, data); 92596f2e892SBill Paul return (0); 92696f2e892SBill Paul } 92796f2e892SBill Paul 92896f2e892SBill Paul frame.mii_phyaddr = phy; 92996f2e892SBill Paul frame.mii_regaddr = reg; 93096f2e892SBill Paul frame.mii_data = data; 93196f2e892SBill Paul 932419146d9SBill Paul if (sc->dc_type == DC_TYPE_98713) { 933f43d9309SBill Paul phy_reg = CSR_READ_4(sc, DC_NETCFG); 934f43d9309SBill Paul CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 935419146d9SBill Paul } 93696f2e892SBill Paul dc_mii_writereg(sc, &frame); 937419146d9SBill Paul if (sc->dc_type == DC_TYPE_98713) 938f43d9309SBill Paul CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 93996f2e892SBill Paul 94096f2e892SBill Paul return (0); 94196f2e892SBill Paul } 94296f2e892SBill Paul 943e3d2833aSAlfred Perlstein static void 9440934f18aSMaxime Henrion dc_miibus_statchg(device_t dev) 94596f2e892SBill Paul { 94696f2e892SBill Paul struct dc_softc *sc; 947d314ebf5SPyun YongHyeon struct ifnet *ifp; 94896f2e892SBill Paul struct mii_data *mii; 949f43d9309SBill Paul struct ifmedia *ifm; 95096f2e892SBill Paul 95196f2e892SBill Paul sc = device_get_softc(dev); 9525c1cfac4SBill Paul 95396f2e892SBill Paul mii = device_get_softc(sc->dc_miibus); 954d314ebf5SPyun YongHyeon ifp = sc->dc_ifp; 955d314ebf5SPyun YongHyeon if (mii == NULL || ifp == NULL || 956d314ebf5SPyun YongHyeon (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 957d314ebf5SPyun YongHyeon return; 958d314ebf5SPyun YongHyeon 959f43d9309SBill Paul ifm = &mii->mii_media; 960f43d9309SBill Paul if (DC_IS_DAVICOM(sc) && 96145521525SPoul-Henning Kamp IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 962f43d9309SBill Paul dc_setcfg(sc, ifm->ifm_media); 963f43d9309SBill Paul sc->dc_if_media = ifm->ifm_media; 964d314ebf5SPyun YongHyeon return; 965f43d9309SBill Paul } 966d314ebf5SPyun YongHyeon 967d314ebf5SPyun YongHyeon sc->dc_link = 0; 968d314ebf5SPyun YongHyeon if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 969d314ebf5SPyun YongHyeon (IFM_ACTIVE | IFM_AVALID)) { 970d314ebf5SPyun YongHyeon switch (IFM_SUBTYPE(mii->mii_media_active)) { 971d314ebf5SPyun YongHyeon case IFM_10_T: 972d314ebf5SPyun YongHyeon case IFM_100_TX: 973d314ebf5SPyun YongHyeon sc->dc_link = 1; 974d314ebf5SPyun YongHyeon break; 975d314ebf5SPyun YongHyeon default: 976d314ebf5SPyun YongHyeon break; 977d314ebf5SPyun YongHyeon } 978d314ebf5SPyun YongHyeon } 979d314ebf5SPyun YongHyeon if (sc->dc_link == 0) 980d314ebf5SPyun YongHyeon return; 981d314ebf5SPyun YongHyeon 982d314ebf5SPyun YongHyeon sc->dc_if_media = mii->mii_media_active; 983d314ebf5SPyun YongHyeon if (DC_IS_ADMTEK(sc)) 984d314ebf5SPyun YongHyeon return; 985d314ebf5SPyun YongHyeon dc_setcfg(sc, mii->mii_media_active); 986f43d9309SBill Paul } 987f43d9309SBill Paul 988f43d9309SBill Paul /* 989f43d9309SBill Paul * Special support for DM9102A cards with HomePNA PHYs. Note: 990f43d9309SBill Paul * with the Davicom DM9102A/DM9801 eval board that I have, it seems 991f43d9309SBill Paul * to be impossible to talk to the management interface of the DM9801 992f43d9309SBill Paul * PHY (its MDIO pin is not connected to anything). Consequently, 993f43d9309SBill Paul * the driver has to just 'know' about the additional mode and deal 994f43d9309SBill Paul * with it itself. *sigh* 995f43d9309SBill Paul */ 996e3d2833aSAlfred Perlstein static void 9970934f18aSMaxime Henrion dc_miibus_mediainit(device_t dev) 998f43d9309SBill Paul { 999f43d9309SBill Paul struct dc_softc *sc; 1000f43d9309SBill Paul struct mii_data *mii; 1001f43d9309SBill Paul struct ifmedia *ifm; 1002f43d9309SBill Paul int rev; 1003f43d9309SBill Paul 10041e2e70b1SJohn Baldwin rev = pci_get_revid(dev); 1005f43d9309SBill Paul 1006f43d9309SBill Paul sc = device_get_softc(dev); 1007f43d9309SBill Paul mii = device_get_softc(sc->dc_miibus); 1008f43d9309SBill Paul ifm = &mii->mii_media; 1009f43d9309SBill Paul 1010f43d9309SBill Paul if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 101145521525SPoul-Henning Kamp ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL); 101296f2e892SBill Paul } 101396f2e892SBill Paul 101479d11e09SBill Paul #define DC_BITS_512 9 101579d11e09SBill Paul #define DC_BITS_128 7 101679d11e09SBill Paul #define DC_BITS_64 6 101796f2e892SBill Paul 10183373489bSWarner Losh static uint32_t 10193373489bSWarner Losh dc_mchash_le(struct dc_softc *sc, const uint8_t *addr) 102096f2e892SBill Paul { 10213373489bSWarner Losh uint32_t crc; 102296f2e892SBill Paul 102396f2e892SBill Paul /* Compute CRC for the address value. */ 10240e939c0cSChristian Weisgerber crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 102596f2e892SBill Paul 102679d11e09SBill Paul /* 102779d11e09SBill Paul * The hash table on the PNIC II and the MX98715AEC-C/D/E 102879d11e09SBill Paul * chips is only 128 bits wide. 102979d11e09SBill Paul */ 103079d11e09SBill Paul if (sc->dc_flags & DC_128BIT_HASH) 103179d11e09SBill Paul return (crc & ((1 << DC_BITS_128) - 1)); 103296f2e892SBill Paul 103379d11e09SBill Paul /* The hash table on the MX98715BEC is only 64 bits wide. */ 103479d11e09SBill Paul if (sc->dc_flags & DC_64BIT_HASH) 103579d11e09SBill Paul return (crc & ((1 << DC_BITS_64) - 1)); 103679d11e09SBill Paul 1037feb78939SJonathan Chen /* Xircom's hash filtering table is different (read: weird) */ 1038feb78939SJonathan Chen /* Xircom uses the LEAST significant bits */ 1039feb78939SJonathan Chen if (DC_IS_XIRCOM(sc)) { 1040feb78939SJonathan Chen if ((crc & 0x180) == 0x180) 10410934f18aSMaxime Henrion return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4)); 1042feb78939SJonathan Chen else 10430934f18aSMaxime Henrion return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 + 10440934f18aSMaxime Henrion (12 << 4)); 1045feb78939SJonathan Chen } 1046feb78939SJonathan Chen 104779d11e09SBill Paul return (crc & ((1 << DC_BITS_512) - 1)); 104896f2e892SBill Paul } 104996f2e892SBill Paul 105096f2e892SBill Paul /* 105196f2e892SBill Paul * Calculate CRC of a multicast group address, return the lower 6 bits. 105296f2e892SBill Paul */ 10533373489bSWarner Losh static uint32_t 10543373489bSWarner Losh dc_mchash_be(const uint8_t *addr) 105596f2e892SBill Paul { 10560e939c0cSChristian Weisgerber uint32_t crc; 105796f2e892SBill Paul 105896f2e892SBill Paul /* Compute CRC for the address value. */ 10590e939c0cSChristian Weisgerber crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 106096f2e892SBill Paul 10610934f18aSMaxime Henrion /* Return the filter bit position. */ 106296f2e892SBill Paul return ((crc >> 26) & 0x0000003F); 106396f2e892SBill Paul } 106496f2e892SBill Paul 106596f2e892SBill Paul /* 106696f2e892SBill Paul * 21143-style RX filter setup routine. Filter programming is done by 106796f2e892SBill Paul * downloading a special setup frame into the TX engine. 21143, Macronix, 106896f2e892SBill Paul * PNIC, PNIC II and Davicom chips are programmed this way. 106996f2e892SBill Paul * 107096f2e892SBill Paul * We always program the chip using 'hash perfect' mode, i.e. one perfect 107196f2e892SBill Paul * address (our node address) and a 512-bit hash filter for multicast 107296f2e892SBill Paul * frames. We also sneak the broadcast address into the hash filter since 107396f2e892SBill Paul * we need that too. 107496f2e892SBill Paul */ 10752c876e15SPoul-Henning Kamp static void 10760934f18aSMaxime Henrion dc_setfilt_21143(struct dc_softc *sc) 107796f2e892SBill Paul { 10788df1ebe9SMarcel Moolenaar uint16_t eaddr[(ETHER_ADDR_LEN+1)/2]; 107996f2e892SBill Paul struct dc_desc *sframe; 108096f2e892SBill Paul u_int32_t h, *sp; 108196f2e892SBill Paul struct ifmultiaddr *ifma; 108296f2e892SBill Paul struct ifnet *ifp; 108396f2e892SBill Paul int i; 108496f2e892SBill Paul 1085fc74a9f9SBrooks Davis ifp = sc->dc_ifp; 108696f2e892SBill Paul 108796f2e892SBill Paul i = sc->dc_cdata.dc_tx_prod; 108896f2e892SBill Paul DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 108996f2e892SBill Paul sc->dc_cdata.dc_tx_cnt++; 109096f2e892SBill Paul sframe = &sc->dc_ldata->dc_tx_list[i]; 109156e5e7aeSMaxime Henrion sp = sc->dc_cdata.dc_sbuf; 10920934f18aSMaxime Henrion bzero(sp, DC_SFRAME_LEN); 109396f2e892SBill Paul 1094af4358c7SMaxime Henrion sframe->dc_data = htole32(sc->dc_saddr); 1095af4358c7SMaxime Henrion sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1096af4358c7SMaxime Henrion DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 109796f2e892SBill Paul 109856e5e7aeSMaxime Henrion sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 109996f2e892SBill Paul 110096f2e892SBill Paul /* If we want promiscuous mode, set the allframes bit. */ 110196f2e892SBill Paul if (ifp->if_flags & IFF_PROMISC) 110296f2e892SBill Paul DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 110396f2e892SBill Paul else 110496f2e892SBill Paul DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 110596f2e892SBill Paul 110696f2e892SBill Paul if (ifp->if_flags & IFF_ALLMULTI) 110796f2e892SBill Paul DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 110896f2e892SBill Paul else 110996f2e892SBill Paul DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 111096f2e892SBill Paul 1111eb956cd0SRobert Watson if_maddr_rlock(ifp); 11126817526dSPoul-Henning Kamp TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 111396f2e892SBill Paul if (ifma->ifma_addr->sa_family != AF_LINK) 111496f2e892SBill Paul continue; 1115aa825502SDavid E. O'Brien h = dc_mchash_le(sc, 111696f2e892SBill Paul LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1117af4358c7SMaxime Henrion sp[h >> 4] |= htole32(1 << (h & 0xF)); 111896f2e892SBill Paul } 1119eb956cd0SRobert Watson if_maddr_runlock(ifp); 112096f2e892SBill Paul 112196f2e892SBill Paul if (ifp->if_flags & IFF_BROADCAST) { 1122aa825502SDavid E. O'Brien h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1123af4358c7SMaxime Henrion sp[h >> 4] |= htole32(1 << (h & 0xF)); 112496f2e892SBill Paul } 112596f2e892SBill Paul 11268df1ebe9SMarcel Moolenaar /* Set our MAC address. */ 11278df1ebe9SMarcel Moolenaar bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 11288df1ebe9SMarcel Moolenaar sp[39] = DC_SP_MAC(eaddr[0]); 11298df1ebe9SMarcel Moolenaar sp[40] = DC_SP_MAC(eaddr[1]); 11308df1ebe9SMarcel Moolenaar sp[41] = DC_SP_MAC(eaddr[2]); 113196f2e892SBill Paul 1132af4358c7SMaxime Henrion sframe->dc_status = htole32(DC_TXSTAT_OWN); 113396f2e892SBill Paul CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 113496f2e892SBill Paul 113596f2e892SBill Paul /* 113696f2e892SBill Paul * The PNIC takes an exceedingly long time to process its 113796f2e892SBill Paul * setup frame; wait 10ms after posting the setup frame 113896f2e892SBill Paul * before proceeding, just so it has time to swallow its 113996f2e892SBill Paul * medicine. 114096f2e892SBill Paul */ 114196f2e892SBill Paul DELAY(10000); 114296f2e892SBill Paul 1143b1d16143SMarius Strobl sc->dc_wdog_timer = 5; 114496f2e892SBill Paul } 114596f2e892SBill Paul 11462c876e15SPoul-Henning Kamp static void 11470934f18aSMaxime Henrion dc_setfilt_admtek(struct dc_softc *sc) 114896f2e892SBill Paul { 11492e3d4b79SPyun YongHyeon uint8_t eaddr[ETHER_ADDR_LEN]; 115096f2e892SBill Paul struct ifnet *ifp; 11510934f18aSMaxime Henrion struct ifmultiaddr *ifma; 115296f2e892SBill Paul int h = 0; 115396f2e892SBill Paul u_int32_t hashes[2] = { 0, 0 }; 115496f2e892SBill Paul 1155fc74a9f9SBrooks Davis ifp = sc->dc_ifp; 115696f2e892SBill Paul 11570934f18aSMaxime Henrion /* Init our MAC address. */ 11588df1ebe9SMarcel Moolenaar bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 11592e3d4b79SPyun YongHyeon CSR_WRITE_4(sc, DC_AL_PAR0, eaddr[3] << 24 | eaddr[2] << 16 | 11602e3d4b79SPyun YongHyeon eaddr[1] << 8 | eaddr[0]); 11612e3d4b79SPyun YongHyeon CSR_WRITE_4(sc, DC_AL_PAR1, eaddr[5] << 8 | eaddr[4]); 116296f2e892SBill Paul 116396f2e892SBill Paul /* If we want promiscuous mode, set the allframes bit. */ 116496f2e892SBill Paul if (ifp->if_flags & IFF_PROMISC) 116596f2e892SBill Paul DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 116696f2e892SBill Paul else 116796f2e892SBill Paul DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 116896f2e892SBill Paul 116996f2e892SBill Paul if (ifp->if_flags & IFF_ALLMULTI) 117096f2e892SBill Paul DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 117196f2e892SBill Paul else 117296f2e892SBill Paul DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 117396f2e892SBill Paul 11740934f18aSMaxime Henrion /* First, zot all the existing hash bits. */ 117596f2e892SBill Paul CSR_WRITE_4(sc, DC_AL_MAR0, 0); 117696f2e892SBill Paul CSR_WRITE_4(sc, DC_AL_MAR1, 0); 117796f2e892SBill Paul 117896f2e892SBill Paul /* 117996f2e892SBill Paul * If we're already in promisc or allmulti mode, we 118096f2e892SBill Paul * don't have to bother programming the multicast filter. 118196f2e892SBill Paul */ 118296f2e892SBill Paul if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 118396f2e892SBill Paul return; 118496f2e892SBill Paul 11850934f18aSMaxime Henrion /* Now program new ones. */ 1186eb956cd0SRobert Watson if_maddr_rlock(ifp); 11876817526dSPoul-Henning Kamp TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 118896f2e892SBill Paul if (ifma->ifma_addr->sa_family != AF_LINK) 118996f2e892SBill Paul continue; 1190acc1bcccSMartin Blapp if (DC_IS_CENTAUR(sc)) 1191aa825502SDavid E. O'Brien h = dc_mchash_le(sc, 1192aa825502SDavid E. O'Brien LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1193acc1bcccSMartin Blapp else 1194aa825502SDavid E. O'Brien h = dc_mchash_be( 1195aa825502SDavid E. O'Brien LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 119696f2e892SBill Paul if (h < 32) 119796f2e892SBill Paul hashes[0] |= (1 << h); 119896f2e892SBill Paul else 119996f2e892SBill Paul hashes[1] |= (1 << (h - 32)); 120096f2e892SBill Paul } 1201eb956cd0SRobert Watson if_maddr_runlock(ifp); 120296f2e892SBill Paul 120396f2e892SBill Paul CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 120496f2e892SBill Paul CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 120596f2e892SBill Paul } 120696f2e892SBill Paul 12072c876e15SPoul-Henning Kamp static void 12080934f18aSMaxime Henrion dc_setfilt_asix(struct dc_softc *sc) 120996f2e892SBill Paul { 12108df1ebe9SMarcel Moolenaar uint32_t eaddr[(ETHER_ADDR_LEN+3)/4]; 121196f2e892SBill Paul struct ifnet *ifp; 12120934f18aSMaxime Henrion struct ifmultiaddr *ifma; 121396f2e892SBill Paul int h = 0; 121496f2e892SBill Paul u_int32_t hashes[2] = { 0, 0 }; 121596f2e892SBill Paul 1216fc74a9f9SBrooks Davis ifp = sc->dc_ifp; 121796f2e892SBill Paul 12188df1ebe9SMarcel Moolenaar /* Init our MAC address. */ 12198df1ebe9SMarcel Moolenaar bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 122096f2e892SBill Paul CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 12218df1ebe9SMarcel Moolenaar CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[0]); 122296f2e892SBill Paul CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 12238df1ebe9SMarcel Moolenaar CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[1]); 122496f2e892SBill Paul 122596f2e892SBill Paul /* If we want promiscuous mode, set the allframes bit. */ 122696f2e892SBill Paul if (ifp->if_flags & IFF_PROMISC) 122796f2e892SBill Paul DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 122896f2e892SBill Paul else 122996f2e892SBill Paul DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 123096f2e892SBill Paul 123196f2e892SBill Paul if (ifp->if_flags & IFF_ALLMULTI) 123296f2e892SBill Paul DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 123396f2e892SBill Paul else 123496f2e892SBill Paul DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 123596f2e892SBill Paul 123696f2e892SBill Paul /* 123796f2e892SBill Paul * The ASIX chip has a special bit to enable reception 123896f2e892SBill Paul * of broadcast frames. 123996f2e892SBill Paul */ 124096f2e892SBill Paul if (ifp->if_flags & IFF_BROADCAST) 124196f2e892SBill Paul DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 124296f2e892SBill Paul else 124396f2e892SBill Paul DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 124496f2e892SBill Paul 124596f2e892SBill Paul /* first, zot all the existing hash bits */ 124696f2e892SBill Paul CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 124796f2e892SBill Paul CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 124896f2e892SBill Paul CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 124996f2e892SBill Paul CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 125096f2e892SBill Paul 125196f2e892SBill Paul /* 125296f2e892SBill Paul * If we're already in promisc or allmulti mode, we 125396f2e892SBill Paul * don't have to bother programming the multicast filter. 125496f2e892SBill Paul */ 125596f2e892SBill Paul if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 125696f2e892SBill Paul return; 125796f2e892SBill Paul 125896f2e892SBill Paul /* now program new ones */ 1259eb956cd0SRobert Watson if_maddr_rlock(ifp); 12606817526dSPoul-Henning Kamp TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 126196f2e892SBill Paul if (ifma->ifma_addr->sa_family != AF_LINK) 126296f2e892SBill Paul continue; 1263aa825502SDavid E. O'Brien h = dc_mchash_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 126496f2e892SBill Paul if (h < 32) 126596f2e892SBill Paul hashes[0] |= (1 << h); 126696f2e892SBill Paul else 126796f2e892SBill Paul hashes[1] |= (1 << (h - 32)); 126896f2e892SBill Paul } 1269eb956cd0SRobert Watson if_maddr_runlock(ifp); 127096f2e892SBill Paul 127196f2e892SBill Paul CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 127296f2e892SBill Paul CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 127396f2e892SBill Paul CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 127496f2e892SBill Paul CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 127596f2e892SBill Paul } 127696f2e892SBill Paul 12772c876e15SPoul-Henning Kamp static void 12780934f18aSMaxime Henrion dc_setfilt_xircom(struct dc_softc *sc) 1279feb78939SJonathan Chen { 12808df1ebe9SMarcel Moolenaar uint16_t eaddr[(ETHER_ADDR_LEN+1)/2]; 12810934f18aSMaxime Henrion struct ifnet *ifp; 12820934f18aSMaxime Henrion struct ifmultiaddr *ifma; 1283feb78939SJonathan Chen struct dc_desc *sframe; 1284feb78939SJonathan Chen u_int32_t h, *sp; 1285feb78939SJonathan Chen int i; 1286feb78939SJonathan Chen 1287fc74a9f9SBrooks Davis ifp = sc->dc_ifp; 1288feb78939SJonathan Chen DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1289feb78939SJonathan Chen 1290feb78939SJonathan Chen i = sc->dc_cdata.dc_tx_prod; 1291feb78939SJonathan Chen DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1292feb78939SJonathan Chen sc->dc_cdata.dc_tx_cnt++; 1293feb78939SJonathan Chen sframe = &sc->dc_ldata->dc_tx_list[i]; 129456e5e7aeSMaxime Henrion sp = sc->dc_cdata.dc_sbuf; 12950934f18aSMaxime Henrion bzero(sp, DC_SFRAME_LEN); 1296feb78939SJonathan Chen 1297af4358c7SMaxime Henrion sframe->dc_data = htole32(sc->dc_saddr); 1298af4358c7SMaxime Henrion sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1299af4358c7SMaxime Henrion DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1300feb78939SJonathan Chen 130156e5e7aeSMaxime Henrion sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1302feb78939SJonathan Chen 1303feb78939SJonathan Chen /* If we want promiscuous mode, set the allframes bit. */ 1304feb78939SJonathan Chen if (ifp->if_flags & IFF_PROMISC) 1305feb78939SJonathan Chen DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1306feb78939SJonathan Chen else 1307feb78939SJonathan Chen DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1308feb78939SJonathan Chen 1309feb78939SJonathan Chen if (ifp->if_flags & IFF_ALLMULTI) 1310feb78939SJonathan Chen DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1311feb78939SJonathan Chen else 1312feb78939SJonathan Chen DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1313feb78939SJonathan Chen 1314eb956cd0SRobert Watson if_maddr_rlock(ifp); 13156817526dSPoul-Henning Kamp TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1316feb78939SJonathan Chen if (ifma->ifma_addr->sa_family != AF_LINK) 1317feb78939SJonathan Chen continue; 1318aa825502SDavid E. O'Brien h = dc_mchash_le(sc, 13191d5e5310SBill Paul LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1320af4358c7SMaxime Henrion sp[h >> 4] |= htole32(1 << (h & 0xF)); 1321feb78939SJonathan Chen } 1322eb956cd0SRobert Watson if_maddr_runlock(ifp); 1323feb78939SJonathan Chen 1324feb78939SJonathan Chen if (ifp->if_flags & IFF_BROADCAST) { 1325aa825502SDavid E. O'Brien h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1326af4358c7SMaxime Henrion sp[h >> 4] |= htole32(1 << (h & 0xF)); 1327feb78939SJonathan Chen } 1328feb78939SJonathan Chen 13298df1ebe9SMarcel Moolenaar /* Set our MAC address. */ 13308df1ebe9SMarcel Moolenaar bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 13318df1ebe9SMarcel Moolenaar sp[0] = DC_SP_MAC(eaddr[0]); 13328df1ebe9SMarcel Moolenaar sp[1] = DC_SP_MAC(eaddr[1]); 13338df1ebe9SMarcel Moolenaar sp[2] = DC_SP_MAC(eaddr[2]); 1334feb78939SJonathan Chen 1335feb78939SJonathan Chen DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1336feb78939SJonathan Chen DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 133713f4c340SRobert Watson ifp->if_drv_flags |= IFF_DRV_RUNNING; 1338af4358c7SMaxime Henrion sframe->dc_status = htole32(DC_TXSTAT_OWN); 1339feb78939SJonathan Chen CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1340feb78939SJonathan Chen 1341feb78939SJonathan Chen /* 13420934f18aSMaxime Henrion * Wait some time... 1343feb78939SJonathan Chen */ 1344feb78939SJonathan Chen DELAY(1000); 1345feb78939SJonathan Chen 1346b1d16143SMarius Strobl sc->dc_wdog_timer = 5; 1347feb78939SJonathan Chen } 1348feb78939SJonathan Chen 1349e3d2833aSAlfred Perlstein static void 13500934f18aSMaxime Henrion dc_setfilt(struct dc_softc *sc) 135196f2e892SBill Paul { 13520934f18aSMaxime Henrion 135396f2e892SBill Paul if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 13541af8bec7SBill Paul DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 135596f2e892SBill Paul dc_setfilt_21143(sc); 135696f2e892SBill Paul 135796f2e892SBill Paul if (DC_IS_ASIX(sc)) 135896f2e892SBill Paul dc_setfilt_asix(sc); 135996f2e892SBill Paul 136096f2e892SBill Paul if (DC_IS_ADMTEK(sc)) 136196f2e892SBill Paul dc_setfilt_admtek(sc); 136296f2e892SBill Paul 1363feb78939SJonathan Chen if (DC_IS_XIRCOM(sc)) 1364feb78939SJonathan Chen dc_setfilt_xircom(sc); 136596f2e892SBill Paul } 136696f2e892SBill Paul 136796f2e892SBill Paul /* 13680934f18aSMaxime Henrion * In order to fiddle with the 'full-duplex' and '100Mbps' bits in 13690934f18aSMaxime Henrion * the netconfig register, we first have to put the transmit and/or 13700934f18aSMaxime Henrion * receive logic in the idle state. 137196f2e892SBill Paul */ 1372e3d2833aSAlfred Perlstein static void 13730934f18aSMaxime Henrion dc_setcfg(struct dc_softc *sc, int media) 137496f2e892SBill Paul { 13750934f18aSMaxime Henrion int i, restart = 0, watchdogreg; 137696f2e892SBill Paul u_int32_t isr; 137796f2e892SBill Paul 137896f2e892SBill Paul if (IFM_SUBTYPE(media) == IFM_NONE) 137996f2e892SBill Paul return; 138096f2e892SBill Paul 138196f2e892SBill Paul if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) { 138296f2e892SBill Paul restart = 1; 138396f2e892SBill Paul DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 138496f2e892SBill Paul 138596f2e892SBill Paul for (i = 0; i < DC_TIMEOUT; i++) { 138696f2e892SBill Paul isr = CSR_READ_4(sc, DC_ISR); 1387d467c136SBill Paul if (isr & DC_ISR_TX_IDLE && 1388351267c1SMartin Blapp ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1389351267c1SMartin Blapp (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT)) 139096f2e892SBill Paul break; 1391d467c136SBill Paul DELAY(10); 139296f2e892SBill Paul } 139396f2e892SBill Paul 1394432120f2SMarius Strobl if (i == DC_TIMEOUT) { 1395432120f2SMarius Strobl if (!(isr & DC_ISR_TX_IDLE) && !DC_IS_ASIX(sc)) 13966b9f5c94SGleb Smirnoff device_printf(sc->dc_dev, 1397432120f2SMarius Strobl "%s: failed to force tx to idle state\n", 1398432120f2SMarius Strobl __func__); 1399432120f2SMarius Strobl if (!((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1400432120f2SMarius Strobl (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT) && 1401d0d67284SMarius Strobl !DC_HAS_BROKEN_RXSTATE(sc)) 1402432120f2SMarius Strobl device_printf(sc->dc_dev, 1403432120f2SMarius Strobl "%s: failed to force rx to idle state\n", 1404432120f2SMarius Strobl __func__); 1405432120f2SMarius Strobl } 140696f2e892SBill Paul } 140796f2e892SBill Paul 140896f2e892SBill Paul if (IFM_SUBTYPE(media) == IFM_100_TX) { 1409042c8f6eSBill Paul DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1410042c8f6eSBill Paul DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 141196f2e892SBill Paul if (sc->dc_pmode == DC_PMODE_MII) { 1412bf645417SBill Paul if (DC_IS_INTEL(sc)) { 14130934f18aSMaxime Henrion /* There's a write enable bit here that reads as 1. */ 14148273d5f8SBill Paul watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 14158273d5f8SBill Paul watchdogreg &= ~DC_WDOG_CTLWREN; 14168273d5f8SBill Paul watchdogreg |= DC_WDOG_JABBERDIS; 14174c2efe27SBill Paul CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1418bf645417SBill Paul } else { 1419bf645417SBill Paul DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1420bf645417SBill Paul } 142196f2e892SBill Paul DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 142296f2e892SBill Paul DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 142396f2e892SBill Paul if (sc->dc_type == DC_TYPE_98713) 142496f2e892SBill Paul DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 142596f2e892SBill Paul DC_NETCFG_SCRAMBLER)); 142688d739dcSBill Paul if (!DC_IS_DAVICOM(sc)) 142796f2e892SBill Paul DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 142896f2e892SBill Paul DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 142996f2e892SBill Paul } else { 143096f2e892SBill Paul if (DC_IS_PNIC(sc)) { 143196f2e892SBill Paul DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 143296f2e892SBill Paul DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 143396f2e892SBill Paul DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 143496f2e892SBill Paul } 1435318b02fdSBill Paul DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1436318b02fdSBill Paul DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1437318b02fdSBill Paul DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 143896f2e892SBill Paul } 143996f2e892SBill Paul } 144096f2e892SBill Paul 144196f2e892SBill Paul if (IFM_SUBTYPE(media) == IFM_10_T) { 1442042c8f6eSBill Paul DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1443042c8f6eSBill Paul DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 144496f2e892SBill Paul if (sc->dc_pmode == DC_PMODE_MII) { 14450934f18aSMaxime Henrion /* There's a write enable bit here that reads as 1. */ 14464c2efe27SBill Paul if (DC_IS_INTEL(sc)) { 14478273d5f8SBill Paul watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 14488273d5f8SBill Paul watchdogreg &= ~DC_WDOG_CTLWREN; 14498273d5f8SBill Paul watchdogreg |= DC_WDOG_JABBERDIS; 14508273d5f8SBill Paul CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 14514c2efe27SBill Paul } else { 14524c2efe27SBill Paul DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 14534c2efe27SBill Paul } 145496f2e892SBill Paul DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 145596f2e892SBill Paul DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 145696f2e892SBill Paul if (sc->dc_type == DC_TYPE_98713) 145796f2e892SBill Paul DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 145888d739dcSBill Paul if (!DC_IS_DAVICOM(sc)) 145996f2e892SBill Paul DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 146096f2e892SBill Paul DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 146196f2e892SBill Paul } else { 146296f2e892SBill Paul if (DC_IS_PNIC(sc)) { 146396f2e892SBill Paul DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 146496f2e892SBill Paul DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 146596f2e892SBill Paul DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 146696f2e892SBill Paul } 146796f2e892SBill Paul DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1468318b02fdSBill Paul DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 146996f2e892SBill Paul DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 14705c1cfac4SBill Paul if (DC_IS_INTEL(sc)) { 14715c1cfac4SBill Paul DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 14725c1cfac4SBill Paul DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 14735c1cfac4SBill Paul if ((media & IFM_GMASK) == IFM_FDX) 14745c1cfac4SBill Paul DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 14755c1cfac4SBill Paul else 14765c1cfac4SBill Paul DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 14775c1cfac4SBill Paul DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 14785c1cfac4SBill Paul DC_CLRBIT(sc, DC_10BTCTRL, 14795c1cfac4SBill Paul DC_TCTL_AUTONEGENBL); 14805c1cfac4SBill Paul DELAY(20000); 14815c1cfac4SBill Paul } 148296f2e892SBill Paul } 148396f2e892SBill Paul } 148496f2e892SBill Paul 1485f43d9309SBill Paul /* 1486f43d9309SBill Paul * If this is a Davicom DM9102A card with a DM9801 HomePNA 1487f43d9309SBill Paul * PHY and we want HomePNA mode, set the portsel bit to turn 1488f43d9309SBill Paul * on the external MII port. 1489f43d9309SBill Paul */ 1490f43d9309SBill Paul if (DC_IS_DAVICOM(sc)) { 149145521525SPoul-Henning Kamp if (IFM_SUBTYPE(media) == IFM_HPNA_1) { 1492f43d9309SBill Paul DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1493f43d9309SBill Paul sc->dc_link = 1; 1494f43d9309SBill Paul } else { 1495f43d9309SBill Paul DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1496f43d9309SBill Paul } 1497f43d9309SBill Paul } 1498f43d9309SBill Paul 149996f2e892SBill Paul if ((media & IFM_GMASK) == IFM_FDX) { 150096f2e892SBill Paul DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 150196f2e892SBill Paul if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 150296f2e892SBill Paul DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 150396f2e892SBill Paul } else { 150496f2e892SBill Paul DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 150596f2e892SBill Paul if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 150696f2e892SBill Paul DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 150796f2e892SBill Paul } 150896f2e892SBill Paul 150996f2e892SBill Paul if (restart) 151096f2e892SBill Paul DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON | DC_NETCFG_RX_ON); 151196f2e892SBill Paul } 151296f2e892SBill Paul 1513e3d2833aSAlfred Perlstein static void 15140934f18aSMaxime Henrion dc_reset(struct dc_softc *sc) 151596f2e892SBill Paul { 15160934f18aSMaxime Henrion int i; 151796f2e892SBill Paul 151896f2e892SBill Paul DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 151996f2e892SBill Paul 152096f2e892SBill Paul for (i = 0; i < DC_TIMEOUT; i++) { 152196f2e892SBill Paul DELAY(10); 152296f2e892SBill Paul if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 152396f2e892SBill Paul break; 152496f2e892SBill Paul } 152596f2e892SBill Paul 15261af8bec7SBill Paul if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) || 15271d5e5310SBill Paul DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) { 152896f2e892SBill Paul DELAY(10000); 152996f2e892SBill Paul DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 153096f2e892SBill Paul i = 0; 153196f2e892SBill Paul } 153296f2e892SBill Paul 153396f2e892SBill Paul if (i == DC_TIMEOUT) 15346b9f5c94SGleb Smirnoff device_printf(sc->dc_dev, "reset never completed!\n"); 153596f2e892SBill Paul 153696f2e892SBill Paul /* Wait a little while for the chip to get its brains in order. */ 153796f2e892SBill Paul DELAY(1000); 153896f2e892SBill Paul 153996f2e892SBill Paul CSR_WRITE_4(sc, DC_IMR, 0x00000000); 154096f2e892SBill Paul CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 154196f2e892SBill Paul CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 154296f2e892SBill Paul 154391cc2adbSBill Paul /* 154491cc2adbSBill Paul * Bring the SIA out of reset. In some cases, it looks 154591cc2adbSBill Paul * like failing to unreset the SIA soon enough gets it 154691cc2adbSBill Paul * into a state where it will never come out of reset 154791cc2adbSBill Paul * until we reset the whole chip again. 154891cc2adbSBill Paul */ 15495c1cfac4SBill Paul if (DC_IS_INTEL(sc)) { 155091cc2adbSBill Paul DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1551d314ebf5SPyun YongHyeon CSR_WRITE_4(sc, DC_10BTCTRL, 0xFFFFFFFF); 15525c1cfac4SBill Paul CSR_WRITE_4(sc, DC_WATCHDOG, 0); 15535c1cfac4SBill Paul } 155496f2e892SBill Paul } 155596f2e892SBill Paul 1556ebc284ccSMarius Strobl static const struct dc_type * 15570934f18aSMaxime Henrion dc_devtype(device_t dev) 155896f2e892SBill Paul { 1559ebc284ccSMarius Strobl const struct dc_type *t; 15601e2e70b1SJohn Baldwin u_int32_t devid; 15611e2e70b1SJohn Baldwin u_int8_t rev; 156296f2e892SBill Paul 156396f2e892SBill Paul t = dc_devs; 15641e2e70b1SJohn Baldwin devid = pci_get_devid(dev); 15651e2e70b1SJohn Baldwin rev = pci_get_revid(dev); 156696f2e892SBill Paul 156796f2e892SBill Paul while (t->dc_name != NULL) { 15681e2e70b1SJohn Baldwin if (devid == t->dc_devid && rev >= t->dc_minrev) 156996f2e892SBill Paul return (t); 157096f2e892SBill Paul t++; 157196f2e892SBill Paul } 157296f2e892SBill Paul 157396f2e892SBill Paul return (NULL); 157496f2e892SBill Paul } 157596f2e892SBill Paul 157696f2e892SBill Paul /* 157796f2e892SBill Paul * Probe for a 21143 or clone chip. Check the PCI vendor and device 157896f2e892SBill Paul * IDs against our list and return a device name if we find a match. 157996f2e892SBill Paul * We do a little bit of extra work to identify the exact type of 158096f2e892SBill Paul * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 158196f2e892SBill Paul * but different revision IDs. The same is true for 98715/98715A 158296f2e892SBill Paul * chips and the 98725, as well as the ASIX and ADMtek chips. In some 158396f2e892SBill Paul * cases, the exact chip revision affects driver behavior. 158496f2e892SBill Paul */ 1585e3d2833aSAlfred Perlstein static int 15860934f18aSMaxime Henrion dc_probe(device_t dev) 158796f2e892SBill Paul { 1588ebc284ccSMarius Strobl const struct dc_type *t; 158996f2e892SBill Paul 159096f2e892SBill Paul t = dc_devtype(dev); 159196f2e892SBill Paul 159296f2e892SBill Paul if (t != NULL) { 159396f2e892SBill Paul device_set_desc(dev, t->dc_name); 1594d701c913SWarner Losh return (BUS_PROBE_DEFAULT); 159596f2e892SBill Paul } 159696f2e892SBill Paul 159796f2e892SBill Paul return (ENXIO); 159896f2e892SBill Paul } 159996f2e892SBill Paul 1600e3d2833aSAlfred Perlstein static void 16010934f18aSMaxime Henrion dc_apply_fixup(struct dc_softc *sc, int media) 16025c1cfac4SBill Paul { 16035c1cfac4SBill Paul struct dc_mediainfo *m; 16045c1cfac4SBill Paul u_int8_t *p; 16055c1cfac4SBill Paul int i; 16065d801891SBill Paul u_int32_t reg; 16075c1cfac4SBill Paul 16085c1cfac4SBill Paul m = sc->dc_mi; 16095c1cfac4SBill Paul 16105c1cfac4SBill Paul while (m != NULL) { 16115c1cfac4SBill Paul if (m->dc_media == media) 16125c1cfac4SBill Paul break; 16135c1cfac4SBill Paul m = m->dc_next; 16145c1cfac4SBill Paul } 16155c1cfac4SBill Paul 16165c1cfac4SBill Paul if (m == NULL) 16175c1cfac4SBill Paul return; 16185c1cfac4SBill Paul 16195c1cfac4SBill Paul for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 16205c1cfac4SBill Paul reg = (p[0] | (p[1] << 8)) << 16; 16215c1cfac4SBill Paul CSR_WRITE_4(sc, DC_WATCHDOG, reg); 16225c1cfac4SBill Paul } 16235c1cfac4SBill Paul 16245c1cfac4SBill Paul for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 16255c1cfac4SBill Paul reg = (p[0] | (p[1] << 8)) << 16; 16265c1cfac4SBill Paul CSR_WRITE_4(sc, DC_WATCHDOG, reg); 16275c1cfac4SBill Paul } 16285c1cfac4SBill Paul } 16295c1cfac4SBill Paul 1630abe4e865SPyun YongHyeon static int 16310934f18aSMaxime Henrion dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l) 16325c1cfac4SBill Paul { 16335c1cfac4SBill Paul struct dc_mediainfo *m; 16345c1cfac4SBill Paul 16350934f18aSMaxime Henrion m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1636abe4e865SPyun YongHyeon if (m == NULL) { 1637abe4e865SPyun YongHyeon device_printf(sc->dc_dev, "Could not allocate mediainfo\n"); 1638abe4e865SPyun YongHyeon return (ENOMEM); 1639abe4e865SPyun YongHyeon } 164087f4fa15SMartin Blapp switch (l->dc_sia_code & ~DC_SIA_CODE_EXT) { 164187f4fa15SMartin Blapp case DC_SIA_CODE_10BT: 16425c1cfac4SBill Paul m->dc_media = IFM_10_T; 164387f4fa15SMartin Blapp break; 164487f4fa15SMartin Blapp case DC_SIA_CODE_10BT_FDX: 16455c1cfac4SBill Paul m->dc_media = IFM_10_T | IFM_FDX; 164687f4fa15SMartin Blapp break; 164787f4fa15SMartin Blapp case DC_SIA_CODE_10B2: 16485c1cfac4SBill Paul m->dc_media = IFM_10_2; 164987f4fa15SMartin Blapp break; 165087f4fa15SMartin Blapp case DC_SIA_CODE_10B5: 16515c1cfac4SBill Paul m->dc_media = IFM_10_5; 165287f4fa15SMartin Blapp break; 165387f4fa15SMartin Blapp default: 165487f4fa15SMartin Blapp break; 165587f4fa15SMartin Blapp } 16565c1cfac4SBill Paul 165787f4fa15SMartin Blapp /* 165887f4fa15SMartin Blapp * We need to ignore CSR13, CSR14, CSR15 for SIA mode. 165987f4fa15SMartin Blapp * Things apparently already work for cards that do 166087f4fa15SMartin Blapp * supply Media Specific Data. 166187f4fa15SMartin Blapp */ 166287f4fa15SMartin Blapp if (l->dc_sia_code & DC_SIA_CODE_EXT) { 16635c1cfac4SBill Paul m->dc_gp_len = 2; 166487f4fa15SMartin Blapp m->dc_gp_ptr = 166587f4fa15SMartin Blapp (u_int8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl; 166687f4fa15SMartin Blapp } else { 166787f4fa15SMartin Blapp m->dc_gp_len = 2; 166887f4fa15SMartin Blapp m->dc_gp_ptr = 166987f4fa15SMartin Blapp (u_int8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl; 167087f4fa15SMartin Blapp } 16715c1cfac4SBill Paul 16725c1cfac4SBill Paul m->dc_next = sc->dc_mi; 16735c1cfac4SBill Paul sc->dc_mi = m; 16745c1cfac4SBill Paul 16755c1cfac4SBill Paul sc->dc_pmode = DC_PMODE_SIA; 1676abe4e865SPyun YongHyeon return (0); 16775c1cfac4SBill Paul } 16785c1cfac4SBill Paul 1679abe4e865SPyun YongHyeon static int 16800934f18aSMaxime Henrion dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l) 16815c1cfac4SBill Paul { 16825c1cfac4SBill Paul struct dc_mediainfo *m; 16835c1cfac4SBill Paul 16840934f18aSMaxime Henrion m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1685abe4e865SPyun YongHyeon if (m == NULL) { 1686abe4e865SPyun YongHyeon device_printf(sc->dc_dev, "Could not allocate mediainfo\n"); 1687abe4e865SPyun YongHyeon return (ENOMEM); 1688abe4e865SPyun YongHyeon } 16895c1cfac4SBill Paul if (l->dc_sym_code == DC_SYM_CODE_100BT) 16905c1cfac4SBill Paul m->dc_media = IFM_100_TX; 16915c1cfac4SBill Paul 16925c1cfac4SBill Paul if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 16935c1cfac4SBill Paul m->dc_media = IFM_100_TX | IFM_FDX; 16945c1cfac4SBill Paul 16955c1cfac4SBill Paul m->dc_gp_len = 2; 16965c1cfac4SBill Paul m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 16975c1cfac4SBill Paul 16985c1cfac4SBill Paul m->dc_next = sc->dc_mi; 16995c1cfac4SBill Paul sc->dc_mi = m; 17005c1cfac4SBill Paul 17015c1cfac4SBill Paul sc->dc_pmode = DC_PMODE_SYM; 1702abe4e865SPyun YongHyeon return (0); 17035c1cfac4SBill Paul } 17045c1cfac4SBill Paul 1705abe4e865SPyun YongHyeon static int 17060934f18aSMaxime Henrion dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l) 17075c1cfac4SBill Paul { 17085c1cfac4SBill Paul struct dc_mediainfo *m; 17090934f18aSMaxime Henrion u_int8_t *p; 17105c1cfac4SBill Paul 17110934f18aSMaxime Henrion m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1712abe4e865SPyun YongHyeon if (m == NULL) { 1713abe4e865SPyun YongHyeon device_printf(sc->dc_dev, "Could not allocate mediainfo\n"); 1714abe4e865SPyun YongHyeon return (ENOMEM); 1715abe4e865SPyun YongHyeon } 17165c1cfac4SBill Paul /* We abuse IFM_AUTO to represent MII. */ 17175c1cfac4SBill Paul m->dc_media = IFM_AUTO; 17185c1cfac4SBill Paul m->dc_gp_len = l->dc_gpr_len; 17195c1cfac4SBill Paul 17205c1cfac4SBill Paul p = (u_int8_t *)l; 17215c1cfac4SBill Paul p += sizeof(struct dc_eblock_mii); 17225c1cfac4SBill Paul m->dc_gp_ptr = p; 17235c1cfac4SBill Paul p += 2 * l->dc_gpr_len; 17245c1cfac4SBill Paul m->dc_reset_len = *p; 17255c1cfac4SBill Paul p++; 17265c1cfac4SBill Paul m->dc_reset_ptr = p; 17275c1cfac4SBill Paul 17285c1cfac4SBill Paul m->dc_next = sc->dc_mi; 17295c1cfac4SBill Paul sc->dc_mi = m; 1730abe4e865SPyun YongHyeon return (0); 17315c1cfac4SBill Paul } 17325c1cfac4SBill Paul 1733abe4e865SPyun YongHyeon static int 17340934f18aSMaxime Henrion dc_read_srom(struct dc_softc *sc, int bits) 17353097aa70SWarner Losh { 17363097aa70SWarner Losh int size; 17373097aa70SWarner Losh 1738abe4e865SPyun YongHyeon size = DC_ROM_SIZE(bits); 17393097aa70SWarner Losh sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT); 1740abe4e865SPyun YongHyeon if (sc->dc_srom == NULL) { 1741abe4e865SPyun YongHyeon device_printf(sc->dc_dev, "Could not allocate SROM buffer\n"); 1742abe4e865SPyun YongHyeon return (ENOMEM); 1743abe4e865SPyun YongHyeon } 17443097aa70SWarner Losh dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); 1745abe4e865SPyun YongHyeon return (0); 17463097aa70SWarner Losh } 17473097aa70SWarner Losh 1748abe4e865SPyun YongHyeon static int 17490934f18aSMaxime Henrion dc_parse_21143_srom(struct dc_softc *sc) 17505c1cfac4SBill Paul { 17515c1cfac4SBill Paul struct dc_leaf_hdr *lhdr; 17525c1cfac4SBill Paul struct dc_eblock_hdr *hdr; 1753abe4e865SPyun YongHyeon int error, have_mii, i, loff; 17545c1cfac4SBill Paul char *ptr; 17555c1cfac4SBill Paul 1756f956e0b3SMartin Blapp have_mii = 0; 17575c1cfac4SBill Paul loff = sc->dc_srom[27]; 17585c1cfac4SBill Paul lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 17595c1cfac4SBill Paul 17605c1cfac4SBill Paul ptr = (char *)lhdr; 17615c1cfac4SBill Paul ptr += sizeof(struct dc_leaf_hdr) - 1; 1762f956e0b3SMartin Blapp /* 1763f956e0b3SMartin Blapp * Look if we got a MII media block. 1764f956e0b3SMartin Blapp */ 1765f956e0b3SMartin Blapp for (i = 0; i < lhdr->dc_mcnt; i++) { 1766f956e0b3SMartin Blapp hdr = (struct dc_eblock_hdr *)ptr; 1767f956e0b3SMartin Blapp if (hdr->dc_type == DC_EBLOCK_MII) 1768f956e0b3SMartin Blapp have_mii++; 1769f956e0b3SMartin Blapp 1770f956e0b3SMartin Blapp ptr += (hdr->dc_len & 0x7F); 1771f956e0b3SMartin Blapp ptr++; 1772f956e0b3SMartin Blapp } 1773f956e0b3SMartin Blapp 1774f956e0b3SMartin Blapp /* 1775f956e0b3SMartin Blapp * Do the same thing again. Only use SIA and SYM media 1776f956e0b3SMartin Blapp * blocks if no MII media block is available. 1777f956e0b3SMartin Blapp */ 1778f956e0b3SMartin Blapp ptr = (char *)lhdr; 1779f956e0b3SMartin Blapp ptr += sizeof(struct dc_leaf_hdr) - 1; 1780abe4e865SPyun YongHyeon error = 0; 17815c1cfac4SBill Paul for (i = 0; i < lhdr->dc_mcnt; i++) { 17825c1cfac4SBill Paul hdr = (struct dc_eblock_hdr *)ptr; 17835c1cfac4SBill Paul switch (hdr->dc_type) { 17845c1cfac4SBill Paul case DC_EBLOCK_MII: 1785abe4e865SPyun YongHyeon error = dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 17865c1cfac4SBill Paul break; 17875c1cfac4SBill Paul case DC_EBLOCK_SIA: 1788f956e0b3SMartin Blapp if (! have_mii) 1789abe4e865SPyun YongHyeon error = dc_decode_leaf_sia(sc, 1790f956e0b3SMartin Blapp (struct dc_eblock_sia *)hdr); 17915c1cfac4SBill Paul break; 17925c1cfac4SBill Paul case DC_EBLOCK_SYM: 1793f956e0b3SMartin Blapp if (! have_mii) 1794abe4e865SPyun YongHyeon error = dc_decode_leaf_sym(sc, 1795f956e0b3SMartin Blapp (struct dc_eblock_sym *)hdr); 17965c1cfac4SBill Paul break; 17975c1cfac4SBill Paul default: 17985c1cfac4SBill Paul /* Don't care. Yet. */ 17995c1cfac4SBill Paul break; 18005c1cfac4SBill Paul } 18015c1cfac4SBill Paul ptr += (hdr->dc_len & 0x7F); 18025c1cfac4SBill Paul ptr++; 18035c1cfac4SBill Paul } 1804abe4e865SPyun YongHyeon return (error); 18055c1cfac4SBill Paul } 18065c1cfac4SBill Paul 180756e5e7aeSMaxime Henrion static void 180856e5e7aeSMaxime Henrion dc_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 180956e5e7aeSMaxime Henrion { 181056e5e7aeSMaxime Henrion u_int32_t *paddr; 181156e5e7aeSMaxime Henrion 1812ebc284ccSMarius Strobl KASSERT(nseg == 1, 1813ebc284ccSMarius Strobl ("%s: wrong number of segments (%d)", __func__, nseg)); 181456e5e7aeSMaxime Henrion paddr = arg; 181556e5e7aeSMaxime Henrion *paddr = segs->ds_addr; 181656e5e7aeSMaxime Henrion } 181756e5e7aeSMaxime Henrion 181896f2e892SBill Paul /* 181996f2e892SBill Paul * Attach the interface. Allocate softc structures, do ifmedia 182096f2e892SBill Paul * setup and ethernet/BPF attach. 182196f2e892SBill Paul */ 1822e3d2833aSAlfred Perlstein static int 18230934f18aSMaxime Henrion dc_attach(device_t dev) 182496f2e892SBill Paul { 18258df1ebe9SMarcel Moolenaar uint32_t eaddr[(ETHER_ADDR_LEN+3)/4]; 182696f2e892SBill Paul u_int32_t command; 182796f2e892SBill Paul struct dc_softc *sc; 182896f2e892SBill Paul struct ifnet *ifp; 1829b289c607SPyun YongHyeon struct dc_mediainfo *m; 18302e3d4b79SPyun YongHyeon u_int32_t reg, revision; 18318e5d93dbSMarius Strobl int error, i, mac_offset, phy, rid, tmp; 1832e7b01d07SWarner Losh u_int8_t *mac; 183396f2e892SBill Paul 183496f2e892SBill Paul sc = device_get_softc(dev); 18356b9f5c94SGleb Smirnoff sc->dc_dev = dev; 183696f2e892SBill Paul 18376008862bSJohn Baldwin mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1838c8b27acaSJohn Baldwin MTX_DEF); 1839c3e7434fSWarner Losh 184096f2e892SBill Paul /* 184196f2e892SBill Paul * Map control/status registers. 184296f2e892SBill Paul */ 184307f65363SBill Paul pci_enable_busmaster(dev); 184496f2e892SBill Paul 184596f2e892SBill Paul rid = DC_RID; 18465f96beb9SNate Lawson sc->dc_res = bus_alloc_resource_any(dev, DC_RES, &rid, RF_ACTIVE); 184796f2e892SBill Paul 184896f2e892SBill Paul if (sc->dc_res == NULL) { 184922f6205dSJohn Baldwin device_printf(dev, "couldn't map ports/memory\n"); 185096f2e892SBill Paul error = ENXIO; 1851608654d4SNate Lawson goto fail; 185296f2e892SBill Paul } 185396f2e892SBill Paul 185496f2e892SBill Paul sc->dc_btag = rman_get_bustag(sc->dc_res); 185596f2e892SBill Paul sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 185696f2e892SBill Paul 18570934f18aSMaxime Henrion /* Allocate interrupt. */ 185854f1f1d1SNate Lawson rid = 0; 18595f96beb9SNate Lawson sc->dc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 186054f1f1d1SNate Lawson RF_SHAREABLE | RF_ACTIVE); 186154f1f1d1SNate Lawson 186254f1f1d1SNate Lawson if (sc->dc_irq == NULL) { 186322f6205dSJohn Baldwin device_printf(dev, "couldn't map interrupt\n"); 186454f1f1d1SNate Lawson error = ENXIO; 186554f1f1d1SNate Lawson goto fail; 186654f1f1d1SNate Lawson } 186754f1f1d1SNate Lawson 186896f2e892SBill Paul /* Need this info to decide on a chip type. */ 186996f2e892SBill Paul sc->dc_info = dc_devtype(dev); 18701e2e70b1SJohn Baldwin revision = pci_get_revid(dev); 187196f2e892SBill Paul 1872abe4e865SPyun YongHyeon error = 0; 18736d0dd931SWarner Losh /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */ 18741e2e70b1SJohn Baldwin if (sc->dc_info->dc_devid != 18751e2e70b1SJohn Baldwin DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168) && 18761e2e70b1SJohn Baldwin sc->dc_info->dc_devid != 18771e2e70b1SJohn Baldwin DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201)) 1878eecb3844SMartin Blapp dc_eeprom_width(sc); 1879eecb3844SMartin Blapp 18801e2e70b1SJohn Baldwin switch (sc->dc_info->dc_devid) { 18811e2e70b1SJohn Baldwin case DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143): 188296f2e892SBill Paul sc->dc_type = DC_TYPE_21143; 188396f2e892SBill Paul sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1884042c8f6eSBill Paul sc->dc_flags |= DC_REDUCED_MII_POLL; 18855c1cfac4SBill Paul /* Save EEPROM contents so we can parse them later. */ 1886abe4e865SPyun YongHyeon error = dc_read_srom(sc, sc->dc_romwidth); 1887abe4e865SPyun YongHyeon if (error != 0) 1888abe4e865SPyun YongHyeon goto fail; 188996f2e892SBill Paul break; 18901e2e70b1SJohn Baldwin case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009): 18911e2e70b1SJohn Baldwin case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100): 18921e2e70b1SJohn Baldwin case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102): 189396f2e892SBill Paul sc->dc_type = DC_TYPE_DM9102; 1894318a72d7SBill Paul sc->dc_flags |= DC_TX_COALESCE | DC_TX_INTR_ALWAYS; 1895318a72d7SBill Paul sc->dc_flags |= DC_REDUCED_MII_POLL | DC_TX_STORENFWD; 18967dfdc26cSMartin Blapp sc->dc_flags |= DC_TX_ALIGN; 18974a80e74bSMartin Blapp sc->dc_pmode = DC_PMODE_MII; 18981e2e70b1SJohn Baldwin 18990a46b1dcSBill Paul /* Increase the latency timer value. */ 19001e2e70b1SJohn Baldwin pci_write_config(dev, PCIR_LATTIMER, 0x80, 1); 190196f2e892SBill Paul break; 19021e2e70b1SJohn Baldwin case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981): 190396f2e892SBill Paul sc->dc_type = DC_TYPE_AL981; 190496f2e892SBill Paul sc->dc_flags |= DC_TX_USE_TX_INTR; 190596f2e892SBill Paul sc->dc_flags |= DC_TX_ADMTEK_WAR; 190696f2e892SBill Paul sc->dc_pmode = DC_PMODE_MII; 1907abe4e865SPyun YongHyeon error = dc_read_srom(sc, sc->dc_romwidth); 1908abe4e865SPyun YongHyeon if (error != 0) 1909abe4e865SPyun YongHyeon goto fail; 191096f2e892SBill Paul break; 1911593a1aeaSMartin Blapp case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN983): 19121e2e70b1SJohn Baldwin case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985): 19131e2e70b1SJohn Baldwin case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511): 19141e2e70b1SJohn Baldwin case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513): 19151e2e70b1SJohn Baldwin case DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD): 19161e2e70b1SJohn Baldwin case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500): 19171e2e70b1SJohn Baldwin case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX): 19181e2e70b1SJohn Baldwin case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242): 19191e2e70b1SJohn Baldwin case DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX): 19201e2e70b1SJohn Baldwin case DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T): 19211e2e70b1SJohn Baldwin case DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB): 19221e2e70b1SJohn Baldwin case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120): 19231e2e70b1SJohn Baldwin case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130): 192417762569SGleb Smirnoff case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08): 192517762569SGleb Smirnoff case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09): 1926593a1aeaSMartin Blapp sc->dc_type = DC_TYPE_AN983; 1927acc1bcccSMartin Blapp sc->dc_flags |= DC_64BIT_HASH; 192896f2e892SBill Paul sc->dc_flags |= DC_TX_USE_TX_INTR; 192996f2e892SBill Paul sc->dc_flags |= DC_TX_ADMTEK_WAR; 193096f2e892SBill Paul sc->dc_pmode = DC_PMODE_MII; 1931129eaf79SMartin Blapp /* Don't read SROM for - auto-loaded on reset */ 193296f2e892SBill Paul break; 19331e2e70b1SJohn Baldwin case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713): 19341e2e70b1SJohn Baldwin case DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP): 193596f2e892SBill Paul if (revision < DC_REVISION_98713A) { 193696f2e892SBill Paul sc->dc_type = DC_TYPE_98713; 193796f2e892SBill Paul } 1938318b02fdSBill Paul if (revision >= DC_REVISION_98713A) { 193996f2e892SBill Paul sc->dc_type = DC_TYPE_98713A; 1940318b02fdSBill Paul sc->dc_flags |= DC_21143_NWAY; 1941318b02fdSBill Paul } 1942318b02fdSBill Paul sc->dc_flags |= DC_REDUCED_MII_POLL; 194396f2e892SBill Paul sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 194496f2e892SBill Paul break; 19451e2e70b1SJohn Baldwin case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5): 19461e2e70b1SJohn Baldwin case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217): 194779d11e09SBill Paul /* 194879d11e09SBill Paul * Macronix MX98715AEC-C/D/E parts have only a 194979d11e09SBill Paul * 128-bit hash table. We need to deal with these 195079d11e09SBill Paul * in the same manner as the PNIC II so that we 195179d11e09SBill Paul * get the right number of bits out of the 195279d11e09SBill Paul * CRC routine. 195379d11e09SBill Paul */ 195479d11e09SBill Paul if (revision >= DC_REVISION_98715AEC_C && 195579d11e09SBill Paul revision < DC_REVISION_98725) 195679d11e09SBill Paul sc->dc_flags |= DC_128BIT_HASH; 195796f2e892SBill Paul sc->dc_type = DC_TYPE_987x5; 195896f2e892SBill Paul sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1959318b02fdSBill Paul sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 196096f2e892SBill Paul break; 19611e2e70b1SJohn Baldwin case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727): 1962ead7cde9SBill Paul sc->dc_type = DC_TYPE_987x5; 1963ead7cde9SBill Paul sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1964ead7cde9SBill Paul sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1965ead7cde9SBill Paul break; 19661e2e70b1SJohn Baldwin case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115): 196796f2e892SBill Paul sc->dc_type = DC_TYPE_PNICII; 196879d11e09SBill Paul sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR | DC_128BIT_HASH; 1969318b02fdSBill Paul sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 197096f2e892SBill Paul break; 19711e2e70b1SJohn Baldwin case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168): 197296f2e892SBill Paul sc->dc_type = DC_TYPE_PNIC; 197391cc2adbSBill Paul sc->dc_flags |= DC_TX_STORENFWD | DC_TX_INTR_ALWAYS; 197496f2e892SBill Paul sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 197596f2e892SBill Paul sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 1976abe4e865SPyun YongHyeon if (sc->dc_pnic_rx_buf == NULL) { 1977abe4e865SPyun YongHyeon device_printf(sc->dc_dev, 1978abe4e865SPyun YongHyeon "Could not allocate PNIC RX buffer\n"); 1979abe4e865SPyun YongHyeon error = ENOMEM; 1980abe4e865SPyun YongHyeon goto fail; 1981abe4e865SPyun YongHyeon } 198296f2e892SBill Paul if (revision < DC_REVISION_82C169) 198396f2e892SBill Paul sc->dc_pmode = DC_PMODE_SYM; 198496f2e892SBill Paul break; 19851e2e70b1SJohn Baldwin case DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A): 198696f2e892SBill Paul sc->dc_type = DC_TYPE_ASIX; 198796f2e892SBill Paul sc->dc_flags |= DC_TX_USE_TX_INTR | DC_TX_INTR_FIRSTFRAG; 198896f2e892SBill Paul sc->dc_flags |= DC_REDUCED_MII_POLL; 198996f2e892SBill Paul sc->dc_pmode = DC_PMODE_MII; 199096f2e892SBill Paul break; 19911e2e70b1SJohn Baldwin case DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201): 1992feb78939SJonathan Chen sc->dc_type = DC_TYPE_XIRCOM; 19932dfc960aSLuigi Rizzo sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 19942dfc960aSLuigi Rizzo DC_TX_ALIGN; 1995feb78939SJonathan Chen /* 1996feb78939SJonathan Chen * We don't actually need to coalesce, but we're doing 1997feb78939SJonathan Chen * it to obtain a double word aligned buffer. 19982dfc960aSLuigi Rizzo * The DC_TX_COALESCE flag is required. 1999feb78939SJonathan Chen */ 20003097aa70SWarner Losh sc->dc_pmode = DC_PMODE_MII; 2001feb78939SJonathan Chen break; 20021e2e70b1SJohn Baldwin case DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112): 20031af8bec7SBill Paul sc->dc_type = DC_TYPE_CONEXANT; 20041af8bec7SBill Paul sc->dc_flags |= DC_TX_INTR_ALWAYS; 20051af8bec7SBill Paul sc->dc_flags |= DC_REDUCED_MII_POLL; 20061af8bec7SBill Paul sc->dc_pmode = DC_PMODE_MII; 2007abe4e865SPyun YongHyeon error = dc_read_srom(sc, sc->dc_romwidth); 2008abe4e865SPyun YongHyeon if (error != 0) 2009abe4e865SPyun YongHyeon goto fail; 20101af8bec7SBill Paul break; 201196f2e892SBill Paul default: 20121e2e70b1SJohn Baldwin device_printf(dev, "unknown device: %x\n", 20131e2e70b1SJohn Baldwin sc->dc_info->dc_devid); 201496f2e892SBill Paul break; 201596f2e892SBill Paul } 201696f2e892SBill Paul 201796f2e892SBill Paul /* Save the cache line size. */ 201888d739dcSBill Paul if (DC_IS_DAVICOM(sc)) 201988d739dcSBill Paul sc->dc_cachesize = 0; 202088d739dcSBill Paul else 20211e2e70b1SJohn Baldwin sc->dc_cachesize = pci_get_cachelnsz(dev); 202296f2e892SBill Paul 202396f2e892SBill Paul /* Reset the adapter. */ 202496f2e892SBill Paul dc_reset(sc); 202596f2e892SBill Paul 202696f2e892SBill Paul /* Take 21143 out of snooze mode */ 2027feb78939SJonathan Chen if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 202896f2e892SBill Paul command = pci_read_config(dev, DC_PCI_CFDD, 4); 202996f2e892SBill Paul command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 203096f2e892SBill Paul pci_write_config(dev, DC_PCI_CFDD, command, 4); 203196f2e892SBill Paul } 203296f2e892SBill Paul 203396f2e892SBill Paul /* 203496f2e892SBill Paul * Try to learn something about the supported media. 203596f2e892SBill Paul * We know that ASIX and ADMtek and Davicom devices 203696f2e892SBill Paul * will *always* be using MII media, so that's a no-brainer. 203796f2e892SBill Paul * The tricky ones are the Macronix/PNIC II and the 203896f2e892SBill Paul * Intel 21143. 203996f2e892SBill Paul */ 2040abe4e865SPyun YongHyeon if (DC_IS_INTEL(sc)) { 2041abe4e865SPyun YongHyeon error = dc_parse_21143_srom(sc); 2042abe4e865SPyun YongHyeon if (error != 0) 2043abe4e865SPyun YongHyeon goto fail; 2044abe4e865SPyun YongHyeon } else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 204596f2e892SBill Paul if (sc->dc_type == DC_TYPE_98713) 204696f2e892SBill Paul sc->dc_pmode = DC_PMODE_MII; 204796f2e892SBill Paul else 204896f2e892SBill Paul sc->dc_pmode = DC_PMODE_SYM; 204996f2e892SBill Paul } else if (!sc->dc_pmode) 205096f2e892SBill Paul sc->dc_pmode = DC_PMODE_MII; 205196f2e892SBill Paul 205296f2e892SBill Paul /* 205396f2e892SBill Paul * Get station address from the EEPROM. 205496f2e892SBill Paul */ 205596f2e892SBill Paul switch(sc->dc_type) { 205696f2e892SBill Paul case DC_TYPE_98713: 205796f2e892SBill Paul case DC_TYPE_98713A: 205896f2e892SBill Paul case DC_TYPE_987x5: 205996f2e892SBill Paul case DC_TYPE_PNICII: 206096f2e892SBill Paul dc_read_eeprom(sc, (caddr_t)&mac_offset, 206196f2e892SBill Paul (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 206296f2e892SBill Paul dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 206396f2e892SBill Paul break; 206496f2e892SBill Paul case DC_TYPE_PNIC: 206596f2e892SBill Paul dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 206696f2e892SBill Paul break; 206796f2e892SBill Paul case DC_TYPE_DM9102: 2068ec6a7299SMaxime Henrion dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2069ec6a7299SMaxime Henrion #ifdef __sparc64__ 2070ec6a7299SMaxime Henrion /* 2071ec6a7299SMaxime Henrion * If this is an onboard dc(4) the station address read from 2072802cab03SMarius Strobl * the EEPROM is all zero and we have to get it from the FCode. 2073ec6a7299SMaxime Henrion */ 2074802cab03SMarius Strobl if (eaddr[0] == 0 && (eaddr[1] & ~0xffff) == 0) 20758069c79dSRuslan Ermilov OF_getetheraddr(dev, (caddr_t)&eaddr); 2076ec6a7299SMaxime Henrion #endif 2077ec6a7299SMaxime Henrion break; 207896f2e892SBill Paul case DC_TYPE_21143: 207996f2e892SBill Paul case DC_TYPE_ASIX: 208096f2e892SBill Paul dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 208196f2e892SBill Paul break; 208296f2e892SBill Paul case DC_TYPE_AL981: 2083593a1aeaSMartin Blapp case DC_TYPE_AN983: 20842e3d4b79SPyun YongHyeon reg = CSR_READ_4(sc, DC_AL_PAR0); 20852e3d4b79SPyun YongHyeon mac = (uint8_t *)&eaddr[0]; 20862e3d4b79SPyun YongHyeon mac[0] = (reg >> 0) & 0xff; 20872e3d4b79SPyun YongHyeon mac[1] = (reg >> 8) & 0xff; 20882e3d4b79SPyun YongHyeon mac[2] = (reg >> 16) & 0xff; 20892e3d4b79SPyun YongHyeon mac[3] = (reg >> 24) & 0xff; 20902e3d4b79SPyun YongHyeon reg = CSR_READ_4(sc, DC_AL_PAR1); 20912e3d4b79SPyun YongHyeon mac[4] = (reg >> 0) & 0xff; 20922e3d4b79SPyun YongHyeon mac[5] = (reg >> 8) & 0xff; 209396f2e892SBill Paul break; 20941af8bec7SBill Paul case DC_TYPE_CONEXANT: 20950934f18aSMaxime Henrion bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 20960934f18aSMaxime Henrion ETHER_ADDR_LEN); 20971af8bec7SBill Paul break; 2098feb78939SJonathan Chen case DC_TYPE_XIRCOM: 20990934f18aSMaxime Henrion /* The MAC comes from the CIS. */ 2100e7b01d07SWarner Losh mac = pci_get_ether(dev); 2101e7b01d07SWarner Losh if (!mac) { 2102e7b01d07SWarner Losh device_printf(dev, "No station address in CIS!\n"); 2103608654d4SNate Lawson error = ENXIO; 2104e7b01d07SWarner Losh goto fail; 2105e7b01d07SWarner Losh } 2106e7b01d07SWarner Losh bcopy(mac, eaddr, ETHER_ADDR_LEN); 2107feb78939SJonathan Chen break; 210896f2e892SBill Paul default: 210996f2e892SBill Paul dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 211096f2e892SBill Paul break; 211196f2e892SBill Paul } 211296f2e892SBill Paul 211339d76ed6SPyun YongHyeon bcopy(eaddr, sc->dc_eaddr, sizeof(eaddr)); 211439d76ed6SPyun YongHyeon /* 211539d76ed6SPyun YongHyeon * If we still have invalid station address, see whether we can 211639d76ed6SPyun YongHyeon * find station address for chip 0. Some multi-port controllers 211739d76ed6SPyun YongHyeon * just store station address for chip 0 if they have a shared 211839d76ed6SPyun YongHyeon * SROM. 211939d76ed6SPyun YongHyeon */ 212039d76ed6SPyun YongHyeon if ((sc->dc_eaddr[0] == 0 && (sc->dc_eaddr[1] & ~0xffff) == 0) || 212139d76ed6SPyun YongHyeon (sc->dc_eaddr[0] == 0xffffffff && 212239d76ed6SPyun YongHyeon (sc->dc_eaddr[1] & 0xffff) == 0xffff)) { 2123b289c607SPyun YongHyeon error = dc_check_multiport(sc); 2124b289c607SPyun YongHyeon if (error == 0) { 212539d76ed6SPyun YongHyeon bcopy(sc->dc_eaddr, eaddr, sizeof(eaddr)); 2126b289c607SPyun YongHyeon /* Extract media information. */ 2127b289c607SPyun YongHyeon if (DC_IS_INTEL(sc) && sc->dc_srom != NULL) { 2128b289c607SPyun YongHyeon while (sc->dc_mi != NULL) { 2129b289c607SPyun YongHyeon m = sc->dc_mi->dc_next; 2130b289c607SPyun YongHyeon free(sc->dc_mi, M_DEVBUF); 2131b289c607SPyun YongHyeon sc->dc_mi = m; 2132b289c607SPyun YongHyeon } 2133b289c607SPyun YongHyeon error = dc_parse_21143_srom(sc); 2134b289c607SPyun YongHyeon if (error != 0) 2135b289c607SPyun YongHyeon goto fail; 2136b289c607SPyun YongHyeon } 2137b289c607SPyun YongHyeon } else if (error == ENOMEM) 2138b289c607SPyun YongHyeon goto fail; 2139b289c607SPyun YongHyeon else 2140b289c607SPyun YongHyeon error = 0; 214139d76ed6SPyun YongHyeon } 214239d76ed6SPyun YongHyeon 214356e5e7aeSMaxime Henrion /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */ 2144b1d16143SMarius Strobl error = bus_dma_tag_create(bus_get_dma_tag(dev), PAGE_SIZE, 0, 2145b1d16143SMarius Strobl BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 2146b1d16143SMarius Strobl sizeof(struct dc_list_data), 1, sizeof(struct dc_list_data), 2147b1d16143SMarius Strobl 0, NULL, NULL, &sc->dc_ltag); 214856e5e7aeSMaxime Henrion if (error) { 214922f6205dSJohn Baldwin device_printf(dev, "failed to allocate busdma tag\n"); 215056e5e7aeSMaxime Henrion error = ENXIO; 215156e5e7aeSMaxime Henrion goto fail; 215256e5e7aeSMaxime Henrion } 215356e5e7aeSMaxime Henrion error = bus_dmamem_alloc(sc->dc_ltag, (void **)&sc->dc_ldata, 2154aafb3ebbSMaxime Henrion BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->dc_lmap); 215556e5e7aeSMaxime Henrion if (error) { 215622f6205dSJohn Baldwin device_printf(dev, "failed to allocate DMA safe memory\n"); 215756e5e7aeSMaxime Henrion error = ENXIO; 215856e5e7aeSMaxime Henrion goto fail; 215956e5e7aeSMaxime Henrion } 216056e5e7aeSMaxime Henrion error = bus_dmamap_load(sc->dc_ltag, sc->dc_lmap, sc->dc_ldata, 216156e5e7aeSMaxime Henrion sizeof(struct dc_list_data), dc_dma_map_addr, &sc->dc_laddr, 216256e5e7aeSMaxime Henrion BUS_DMA_NOWAIT); 216356e5e7aeSMaxime Henrion if (error) { 216422f6205dSJohn Baldwin device_printf(dev, "cannot get address of the descriptors\n"); 216556e5e7aeSMaxime Henrion error = ENXIO; 216656e5e7aeSMaxime Henrion goto fail; 216756e5e7aeSMaxime Henrion } 216896f2e892SBill Paul 216956e5e7aeSMaxime Henrion /* 217056e5e7aeSMaxime Henrion * Allocate a busdma tag and DMA safe memory for the multicast 217156e5e7aeSMaxime Henrion * setup frame. 217256e5e7aeSMaxime Henrion */ 2173b1d16143SMarius Strobl error = bus_dma_tag_create(bus_get_dma_tag(dev), PAGE_SIZE, 0, 2174b1d16143SMarius Strobl BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 2175b1d16143SMarius Strobl DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1, DC_SFRAME_LEN + DC_MIN_FRAMELEN, 2176b1d16143SMarius Strobl 0, NULL, NULL, &sc->dc_stag); 217756e5e7aeSMaxime Henrion if (error) { 217822f6205dSJohn Baldwin device_printf(dev, "failed to allocate busdma tag\n"); 217956e5e7aeSMaxime Henrion error = ENXIO; 218056e5e7aeSMaxime Henrion goto fail; 218156e5e7aeSMaxime Henrion } 218256e5e7aeSMaxime Henrion error = bus_dmamem_alloc(sc->dc_stag, (void **)&sc->dc_cdata.dc_sbuf, 218356e5e7aeSMaxime Henrion BUS_DMA_NOWAIT, &sc->dc_smap); 218456e5e7aeSMaxime Henrion if (error) { 218522f6205dSJohn Baldwin device_printf(dev, "failed to allocate DMA safe memory\n"); 218656e5e7aeSMaxime Henrion error = ENXIO; 218756e5e7aeSMaxime Henrion goto fail; 218856e5e7aeSMaxime Henrion } 218956e5e7aeSMaxime Henrion error = bus_dmamap_load(sc->dc_stag, sc->dc_smap, sc->dc_cdata.dc_sbuf, 219056e5e7aeSMaxime Henrion DC_SFRAME_LEN, dc_dma_map_addr, &sc->dc_saddr, BUS_DMA_NOWAIT); 219156e5e7aeSMaxime Henrion if (error) { 219222f6205dSJohn Baldwin device_printf(dev, "cannot get address of the descriptors\n"); 219396f2e892SBill Paul error = ENXIO; 219496f2e892SBill Paul goto fail; 219596f2e892SBill Paul } 219696f2e892SBill Paul 219756e5e7aeSMaxime Henrion /* Allocate a busdma tag for mbufs. */ 2198b1d16143SMarius Strobl error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 2199b1d16143SMarius Strobl BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 2200ebc284ccSMarius Strobl MCLBYTES * DC_MAXFRAGS, DC_MAXFRAGS, MCLBYTES, 2201c1b677aaSScott Long 0, NULL, NULL, &sc->dc_mtag); 220256e5e7aeSMaxime Henrion if (error) { 220322f6205dSJohn Baldwin device_printf(dev, "failed to allocate busdma tag\n"); 220456e5e7aeSMaxime Henrion error = ENXIO; 220556e5e7aeSMaxime Henrion goto fail; 220656e5e7aeSMaxime Henrion } 220756e5e7aeSMaxime Henrion 220856e5e7aeSMaxime Henrion /* Create the TX/RX busdma maps. */ 220956e5e7aeSMaxime Henrion for (i = 0; i < DC_TX_LIST_CNT; i++) { 221056e5e7aeSMaxime Henrion error = bus_dmamap_create(sc->dc_mtag, 0, 221156e5e7aeSMaxime Henrion &sc->dc_cdata.dc_tx_map[i]); 221256e5e7aeSMaxime Henrion if (error) { 221322f6205dSJohn Baldwin device_printf(dev, "failed to init TX ring\n"); 221456e5e7aeSMaxime Henrion error = ENXIO; 221556e5e7aeSMaxime Henrion goto fail; 221656e5e7aeSMaxime Henrion } 221756e5e7aeSMaxime Henrion } 221856e5e7aeSMaxime Henrion for (i = 0; i < DC_RX_LIST_CNT; i++) { 221956e5e7aeSMaxime Henrion error = bus_dmamap_create(sc->dc_mtag, 0, 222056e5e7aeSMaxime Henrion &sc->dc_cdata.dc_rx_map[i]); 222156e5e7aeSMaxime Henrion if (error) { 222222f6205dSJohn Baldwin device_printf(dev, "failed to init RX ring\n"); 222356e5e7aeSMaxime Henrion error = ENXIO; 222456e5e7aeSMaxime Henrion goto fail; 222556e5e7aeSMaxime Henrion } 222656e5e7aeSMaxime Henrion } 222756e5e7aeSMaxime Henrion error = bus_dmamap_create(sc->dc_mtag, 0, &sc->dc_sparemap); 222856e5e7aeSMaxime Henrion if (error) { 222922f6205dSJohn Baldwin device_printf(dev, "failed to init RX ring\n"); 223056e5e7aeSMaxime Henrion error = ENXIO; 223156e5e7aeSMaxime Henrion goto fail; 223256e5e7aeSMaxime Henrion } 223396f2e892SBill Paul 2234fc74a9f9SBrooks Davis ifp = sc->dc_ifp = if_alloc(IFT_ETHER); 2235fc74a9f9SBrooks Davis if (ifp == NULL) { 223622f6205dSJohn Baldwin device_printf(dev, "can not if_alloc()\n"); 2237fc74a9f9SBrooks Davis error = ENOSPC; 2238fc74a9f9SBrooks Davis goto fail; 2239fc74a9f9SBrooks Davis } 224096f2e892SBill Paul ifp->if_softc = sc; 22419bf40edeSBrooks Davis if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 22423d57a2e5SBrian Feldman ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 224396f2e892SBill Paul ifp->if_ioctl = dc_ioctl; 224496f2e892SBill Paul ifp->if_start = dc_start; 224596f2e892SBill Paul ifp->if_init = dc_init; 2246cbaf877fSBrian Feldman IFQ_SET_MAXLEN(&ifp->if_snd, DC_TX_LIST_CNT - 1); 2247cbaf877fSBrian Feldman ifp->if_snd.ifq_drv_maxlen = DC_TX_LIST_CNT - 1; 2248cbaf877fSBrian Feldman IFQ_SET_READY(&ifp->if_snd); 224996f2e892SBill Paul 225096f2e892SBill Paul /* 22515c1cfac4SBill Paul * Do MII setup. If this is a 21143, check for a PHY on the 22525c1cfac4SBill Paul * MII bus after applying any necessary fixups to twiddle the 22535c1cfac4SBill Paul * GPIO bits. If we don't end up finding a PHY, restore the 22545c1cfac4SBill Paul * old selection (SIA only or SIA/SYM) and attach the dcphy 22555c1cfac4SBill Paul * driver instead. 225696f2e892SBill Paul */ 22578e5d93dbSMarius Strobl tmp = 0; 22585c1cfac4SBill Paul if (DC_IS_INTEL(sc)) { 22595c1cfac4SBill Paul dc_apply_fixup(sc, IFM_AUTO); 22605c1cfac4SBill Paul tmp = sc->dc_pmode; 22615c1cfac4SBill Paul sc->dc_pmode = DC_PMODE_MII; 22625c1cfac4SBill Paul } 22635c1cfac4SBill Paul 22646d431b17SWarner Losh /* 22656d431b17SWarner Losh * Setup General Purpose port mode and data so the tulip can talk 22668e5d93dbSMarius Strobl * to the MII. This needs to be done before mii_attach so that 22676d431b17SWarner Losh * we can actually see them. 22686d431b17SWarner Losh */ 22696d431b17SWarner Losh if (DC_IS_XIRCOM(sc)) { 22706d431b17SWarner Losh CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 22716d431b17SWarner Losh DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 22726d431b17SWarner Losh DELAY(10); 22736d431b17SWarner Losh CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 22746d431b17SWarner Losh DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 22756d431b17SWarner Losh DELAY(10); 22766d431b17SWarner Losh } 22776d431b17SWarner Losh 22788e5d93dbSMarius Strobl phy = MII_PHY_ANY; 22798e5d93dbSMarius Strobl /* 22808e5d93dbSMarius Strobl * Note: both the AL981 and AN983 have internal PHYs, however the 22818e5d93dbSMarius Strobl * AL981 provides direct access to the PHY registers while the AN983 22828e5d93dbSMarius Strobl * uses a serial MII interface. The AN983's MII interface is also 22838e5d93dbSMarius Strobl * buggy in that you can read from any MII address (0 to 31), but 22848e5d93dbSMarius Strobl * only address 1 behaves normally. To deal with both cases, we 22858e5d93dbSMarius Strobl * pretend that the PHY is at MII address 1. 22868e5d93dbSMarius Strobl */ 22878e5d93dbSMarius Strobl if (DC_IS_ADMTEK(sc)) 22888e5d93dbSMarius Strobl phy = DC_ADMTEK_PHYADDR; 22898e5d93dbSMarius Strobl 22908e5d93dbSMarius Strobl /* 22918e5d93dbSMarius Strobl * Note: the ukphy probes of the RS7112 report a PHY at MII address 22928e5d93dbSMarius Strobl * 0 (possibly HomePNA?) and 1 (ethernet) so we only respond to the 22938e5d93dbSMarius Strobl * correct one. 22948e5d93dbSMarius Strobl */ 22958e5d93dbSMarius Strobl if (DC_IS_CONEXANT(sc)) 22968e5d93dbSMarius Strobl phy = DC_CONEXANT_PHYADDR; 22978e5d93dbSMarius Strobl 22988e5d93dbSMarius Strobl error = mii_attach(dev, &sc->dc_miibus, ifp, dc_ifmedia_upd, 22998e5d93dbSMarius Strobl dc_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0); 230096f2e892SBill Paul 230196f2e892SBill Paul if (error && DC_IS_INTEL(sc)) { 23025c1cfac4SBill Paul sc->dc_pmode = tmp; 23035c1cfac4SBill Paul if (sc->dc_pmode != DC_PMODE_SIA) 230496f2e892SBill Paul sc->dc_pmode = DC_PMODE_SYM; 2305042c8f6eSBill Paul sc->dc_flags |= DC_21143_NWAY; 23068e5d93dbSMarius Strobl mii_attach(dev, &sc->dc_miibus, ifp, dc_ifmedia_upd, 23078e5d93dbSMarius Strobl dc_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, 23088e5d93dbSMarius Strobl MII_OFFSET_ANY, 0); 230978999dd1SBill Paul /* 231078999dd1SBill Paul * For non-MII cards, we need to have the 21143 231178999dd1SBill Paul * drive the LEDs. Except there are some systems 231278999dd1SBill Paul * like the NEC VersaPro NoteBook PC which have no 231378999dd1SBill Paul * LEDs, and twiddling these bits has adverse effects 231478999dd1SBill Paul * on them. (I.e. you suddenly can't get a link.) 231578999dd1SBill Paul */ 23161e2e70b1SJohn Baldwin if (!(pci_get_subvendor(dev) == 0x1033 && 23171e2e70b1SJohn Baldwin pci_get_subdevice(dev) == 0x8028)) 231878999dd1SBill Paul sc->dc_flags |= DC_TULIP_LEDS; 231996f2e892SBill Paul error = 0; 232096f2e892SBill Paul } 232196f2e892SBill Paul 232296f2e892SBill Paul if (error) { 23238e5d93dbSMarius Strobl device_printf(dev, "attaching PHYs failed\n"); 232496f2e892SBill Paul goto fail; 232596f2e892SBill Paul } 232696f2e892SBill Paul 2327028a8491SMartin Blapp if (DC_IS_ADMTEK(sc)) { 2328028a8491SMartin Blapp /* 2329028a8491SMartin Blapp * Set automatic TX underrun recovery for the ADMtek chips 2330028a8491SMartin Blapp */ 2331028a8491SMartin Blapp DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); 2332028a8491SMartin Blapp } 2333028a8491SMartin Blapp 233496f2e892SBill Paul /* 2335db40c1aeSDoug Ambrisko * Tell the upper layer(s) we support long frames. 2336db40c1aeSDoug Ambrisko */ 2337db40c1aeSDoug Ambrisko ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 23389ef8b520SSam Leffler ifp->if_capabilities |= IFCAP_VLAN_MTU; 233940929967SGleb Smirnoff ifp->if_capenable = ifp->if_capabilities; 2340e695984eSRuslan Ermilov #ifdef DEVICE_POLLING 2341e695984eSRuslan Ermilov ifp->if_capabilities |= IFCAP_POLLING; 2342e695984eSRuslan Ermilov #endif 2343db40c1aeSDoug Ambrisko 2344c8b27acaSJohn Baldwin callout_init_mtx(&sc->dc_stat_ch, &sc->dc_mtx, 0); 2345b1d16143SMarius Strobl callout_init_mtx(&sc->dc_wdog_ch, &sc->dc_mtx, 0); 234696f2e892SBill Paul 2347608654d4SNate Lawson /* 2348608654d4SNate Lawson * Call MI attach routine. 2349608654d4SNate Lawson */ 23508df1ebe9SMarcel Moolenaar ether_ifattach(ifp, (caddr_t)eaddr); 2351608654d4SNate Lawson 235254f1f1d1SNate Lawson /* Hook interrupt last to avoid having to lock softc */ 2353c8b27acaSJohn Baldwin error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | INTR_MPSAFE, 2354ef544f63SPaolo Pisati NULL, dc_intr, sc, &sc->dc_intrhand); 2355608654d4SNate Lawson 2356608654d4SNate Lawson if (error) { 235722f6205dSJohn Baldwin device_printf(dev, "couldn't set up irq\n"); 2358693f4477SNate Lawson ether_ifdetach(ifp); 235954f1f1d1SNate Lawson goto fail; 2360608654d4SNate Lawson } 2361510a809eSMike Smith 236296f2e892SBill Paul fail: 236354f1f1d1SNate Lawson if (error) 236454f1f1d1SNate Lawson dc_detach(dev); 236596f2e892SBill Paul return (error); 236696f2e892SBill Paul } 236796f2e892SBill Paul 2368693f4477SNate Lawson /* 2369693f4477SNate Lawson * Shutdown hardware and free up resources. This can be called any 2370693f4477SNate Lawson * time after the mutex has been initialized. It is called in both 2371693f4477SNate Lawson * the error case in attach and the normal detach case so it needs 2372693f4477SNate Lawson * to be careful about only freeing resources that have actually been 2373693f4477SNate Lawson * allocated. 2374693f4477SNate Lawson */ 2375e3d2833aSAlfred Perlstein static int 23760934f18aSMaxime Henrion dc_detach(device_t dev) 237796f2e892SBill Paul { 237896f2e892SBill Paul struct dc_softc *sc; 237996f2e892SBill Paul struct ifnet *ifp; 23805c1cfac4SBill Paul struct dc_mediainfo *m; 238156e5e7aeSMaxime Henrion int i; 238296f2e892SBill Paul 238396f2e892SBill Paul sc = device_get_softc(dev); 238459f47d29SJohn Baldwin KASSERT(mtx_initialized(&sc->dc_mtx), ("dc mutex not initialized")); 2385d1ce9105SBill Paul 2386fc74a9f9SBrooks Davis ifp = sc->dc_ifp; 238796f2e892SBill Paul 238840929967SGleb Smirnoff #ifdef DEVICE_POLLING 238940929967SGleb Smirnoff if (ifp->if_capenable & IFCAP_POLLING) 239040929967SGleb Smirnoff ether_poll_deregister(ifp); 239140929967SGleb Smirnoff #endif 239240929967SGleb Smirnoff 2393693f4477SNate Lawson /* These should only be active if attach succeeded */ 2394214073e5SWarner Losh if (device_is_attached(dev)) { 2395c8b27acaSJohn Baldwin DC_LOCK(sc); 239696f2e892SBill Paul dc_stop(sc); 2397c8b27acaSJohn Baldwin DC_UNLOCK(sc); 2398c8b27acaSJohn Baldwin callout_drain(&sc->dc_stat_ch); 2399b1d16143SMarius Strobl callout_drain(&sc->dc_wdog_ch); 24009ef8b520SSam Leffler ether_ifdetach(ifp); 2401693f4477SNate Lawson } 2402693f4477SNate Lawson if (sc->dc_miibus) 240396f2e892SBill Paul device_delete_child(dev, sc->dc_miibus); 240454f1f1d1SNate Lawson bus_generic_detach(dev); 240596f2e892SBill Paul 240654f1f1d1SNate Lawson if (sc->dc_intrhand) 240796f2e892SBill Paul bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 240854f1f1d1SNate Lawson if (sc->dc_irq) 240996f2e892SBill Paul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 241054f1f1d1SNate Lawson if (sc->dc_res) 241196f2e892SBill Paul bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 241296f2e892SBill Paul 24136a3033a8SWarner Losh if (ifp) 24146a3033a8SWarner Losh if_free(ifp); 24156a3033a8SWarner Losh 241656e5e7aeSMaxime Henrion if (sc->dc_cdata.dc_sbuf != NULL) 241756e5e7aeSMaxime Henrion bus_dmamem_free(sc->dc_stag, sc->dc_cdata.dc_sbuf, sc->dc_smap); 241856e5e7aeSMaxime Henrion if (sc->dc_ldata != NULL) 241956e5e7aeSMaxime Henrion bus_dmamem_free(sc->dc_ltag, sc->dc_ldata, sc->dc_lmap); 24204f867c2dSGiorgos Keramidas if (sc->dc_mtag) { 242156e5e7aeSMaxime Henrion for (i = 0; i < DC_TX_LIST_CNT; i++) 24224f867c2dSGiorgos Keramidas if (sc->dc_cdata.dc_tx_map[i] != NULL) 24234f867c2dSGiorgos Keramidas bus_dmamap_destroy(sc->dc_mtag, 24244f867c2dSGiorgos Keramidas sc->dc_cdata.dc_tx_map[i]); 242556e5e7aeSMaxime Henrion for (i = 0; i < DC_RX_LIST_CNT; i++) 24264f867c2dSGiorgos Keramidas if (sc->dc_cdata.dc_rx_map[i] != NULL) 24274f867c2dSGiorgos Keramidas bus_dmamap_destroy(sc->dc_mtag, 24284f867c2dSGiorgos Keramidas sc->dc_cdata.dc_rx_map[i]); 242956e5e7aeSMaxime Henrion bus_dmamap_destroy(sc->dc_mtag, sc->dc_sparemap); 24304f867c2dSGiorgos Keramidas } 243156e5e7aeSMaxime Henrion if (sc->dc_stag) 243256e5e7aeSMaxime Henrion bus_dma_tag_destroy(sc->dc_stag); 243356e5e7aeSMaxime Henrion if (sc->dc_mtag) 243456e5e7aeSMaxime Henrion bus_dma_tag_destroy(sc->dc_mtag); 243556e5e7aeSMaxime Henrion if (sc->dc_ltag) 243656e5e7aeSMaxime Henrion bus_dma_tag_destroy(sc->dc_ltag); 243756e5e7aeSMaxime Henrion 243896f2e892SBill Paul free(sc->dc_pnic_rx_buf, M_DEVBUF); 243996f2e892SBill Paul 24405c1cfac4SBill Paul while (sc->dc_mi != NULL) { 24415c1cfac4SBill Paul m = sc->dc_mi->dc_next; 24425c1cfac4SBill Paul free(sc->dc_mi, M_DEVBUF); 24435c1cfac4SBill Paul sc->dc_mi = m; 24445c1cfac4SBill Paul } 24457efff076SWarner Losh free(sc->dc_srom, M_DEVBUF); 24465c1cfac4SBill Paul 2447d1ce9105SBill Paul mtx_destroy(&sc->dc_mtx); 244896f2e892SBill Paul 244996f2e892SBill Paul return (0); 245096f2e892SBill Paul } 245196f2e892SBill Paul 245296f2e892SBill Paul /* 245396f2e892SBill Paul * Initialize the transmit descriptors. 245496f2e892SBill Paul */ 2455e3d2833aSAlfred Perlstein static int 24560934f18aSMaxime Henrion dc_list_tx_init(struct dc_softc *sc) 245796f2e892SBill Paul { 245896f2e892SBill Paul struct dc_chain_data *cd; 245996f2e892SBill Paul struct dc_list_data *ld; 246001faf54bSLuigi Rizzo int i, nexti; 246196f2e892SBill Paul 246296f2e892SBill Paul cd = &sc->dc_cdata; 246396f2e892SBill Paul ld = sc->dc_ldata; 246496f2e892SBill Paul for (i = 0; i < DC_TX_LIST_CNT; i++) { 2465b3811c95SMaxime Henrion if (i == DC_TX_LIST_CNT - 1) 2466b3811c95SMaxime Henrion nexti = 0; 2467b3811c95SMaxime Henrion else 2468b3811c95SMaxime Henrion nexti = i + 1; 2469af4358c7SMaxime Henrion ld->dc_tx_list[i].dc_next = htole32(DC_TXDESC(sc, nexti)); 247096f2e892SBill Paul cd->dc_tx_chain[i] = NULL; 247196f2e892SBill Paul ld->dc_tx_list[i].dc_data = 0; 247296f2e892SBill Paul ld->dc_tx_list[i].dc_ctl = 0; 247396f2e892SBill Paul } 247496f2e892SBill Paul 247596f2e892SBill Paul cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2476*06d23883SPyun YongHyeon cd->dc_tx_pkts = 0; 247756e5e7aeSMaxime Henrion bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 247856e5e7aeSMaxime Henrion BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 247996f2e892SBill Paul return (0); 248096f2e892SBill Paul } 248196f2e892SBill Paul 248296f2e892SBill Paul 248396f2e892SBill Paul /* 248496f2e892SBill Paul * Initialize the RX descriptors and allocate mbufs for them. Note that 248596f2e892SBill Paul * we arrange the descriptors in a closed ring, so that the last descriptor 248696f2e892SBill Paul * points back to the first. 248796f2e892SBill Paul */ 2488e3d2833aSAlfred Perlstein static int 24890934f18aSMaxime Henrion dc_list_rx_init(struct dc_softc *sc) 249096f2e892SBill Paul { 249196f2e892SBill Paul struct dc_chain_data *cd; 249296f2e892SBill Paul struct dc_list_data *ld; 249301faf54bSLuigi Rizzo int i, nexti; 249496f2e892SBill Paul 249596f2e892SBill Paul cd = &sc->dc_cdata; 249696f2e892SBill Paul ld = sc->dc_ldata; 249796f2e892SBill Paul 249896f2e892SBill Paul for (i = 0; i < DC_RX_LIST_CNT; i++) { 249956e5e7aeSMaxime Henrion if (dc_newbuf(sc, i, 1) != 0) 250096f2e892SBill Paul return (ENOBUFS); 2501b3811c95SMaxime Henrion if (i == DC_RX_LIST_CNT - 1) 2502b3811c95SMaxime Henrion nexti = 0; 2503b3811c95SMaxime Henrion else 2504b3811c95SMaxime Henrion nexti = i + 1; 2505af4358c7SMaxime Henrion ld->dc_rx_list[i].dc_next = htole32(DC_RXDESC(sc, nexti)); 250696f2e892SBill Paul } 250796f2e892SBill Paul 250896f2e892SBill Paul cd->dc_rx_prod = 0; 250956e5e7aeSMaxime Henrion bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 251056e5e7aeSMaxime Henrion BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 251196f2e892SBill Paul return (0); 251296f2e892SBill Paul } 251396f2e892SBill Paul 251496f2e892SBill Paul /* 251596f2e892SBill Paul * Initialize an RX descriptor and attach an MBUF cluster. 251696f2e892SBill Paul */ 2517e3d2833aSAlfred Perlstein static int 251856e5e7aeSMaxime Henrion dc_newbuf(struct dc_softc *sc, int i, int alloc) 251996f2e892SBill Paul { 252056e5e7aeSMaxime Henrion struct mbuf *m_new; 252156e5e7aeSMaxime Henrion bus_dmamap_t tmp; 252282a67a70SMarius Strobl bus_dma_segment_t segs[1]; 252382a67a70SMarius Strobl int error, nseg; 252496f2e892SBill Paul 252556e5e7aeSMaxime Henrion if (alloc) { 252656e5e7aeSMaxime Henrion m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 252740129585SLuigi Rizzo if (m_new == NULL) 252896f2e892SBill Paul return (ENOBUFS); 252996f2e892SBill Paul } else { 253056e5e7aeSMaxime Henrion m_new = sc->dc_cdata.dc_rx_chain[i]; 253196f2e892SBill Paul m_new->m_data = m_new->m_ext.ext_buf; 253296f2e892SBill Paul } 253356e5e7aeSMaxime Henrion m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 253496f2e892SBill Paul m_adj(m_new, sizeof(u_int64_t)); 253596f2e892SBill Paul 253696f2e892SBill Paul /* 253796f2e892SBill Paul * If this is a PNIC chip, zero the buffer. This is part 253896f2e892SBill Paul * of the workaround for the receive bug in the 82c168 and 253996f2e892SBill Paul * 82c169 chips. 254096f2e892SBill Paul */ 254196f2e892SBill Paul if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 25420934f18aSMaxime Henrion bzero(mtod(m_new, char *), m_new->m_len); 254396f2e892SBill Paul 254456e5e7aeSMaxime Henrion /* No need to remap the mbuf if we're reusing it. */ 254556e5e7aeSMaxime Henrion if (alloc) { 254682a67a70SMarius Strobl error = bus_dmamap_load_mbuf_sg(sc->dc_mtag, sc->dc_sparemap, 254782a67a70SMarius Strobl m_new, segs, &nseg, 0); 254856e5e7aeSMaxime Henrion if (error) { 254956e5e7aeSMaxime Henrion m_freem(m_new); 255056e5e7aeSMaxime Henrion return (error); 255156e5e7aeSMaxime Henrion } 2552ebc284ccSMarius Strobl KASSERT(nseg == 1, 2553ebc284ccSMarius Strobl ("%s: wrong number of segments (%d)", __func__, nseg)); 255482a67a70SMarius Strobl sc->dc_ldata->dc_rx_list[i].dc_data = htole32(segs->ds_addr); 255556e5e7aeSMaxime Henrion bus_dmamap_unload(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i]); 255656e5e7aeSMaxime Henrion tmp = sc->dc_cdata.dc_rx_map[i]; 255756e5e7aeSMaxime Henrion sc->dc_cdata.dc_rx_map[i] = sc->dc_sparemap; 255856e5e7aeSMaxime Henrion sc->dc_sparemap = tmp; 255996f2e892SBill Paul sc->dc_cdata.dc_rx_chain[i] = m_new; 256056e5e7aeSMaxime Henrion } 256196f2e892SBill Paul 2562af4358c7SMaxime Henrion sc->dc_ldata->dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN); 2563af4358c7SMaxime Henrion sc->dc_ldata->dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN); 256456e5e7aeSMaxime Henrion bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i], 256556e5e7aeSMaxime Henrion BUS_DMASYNC_PREREAD); 256656e5e7aeSMaxime Henrion bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 256756e5e7aeSMaxime Henrion BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 256896f2e892SBill Paul return (0); 256996f2e892SBill Paul } 257096f2e892SBill Paul 257196f2e892SBill Paul /* 257296f2e892SBill Paul * Grrrrr. 257396f2e892SBill Paul * The PNIC chip has a terrible bug in it that manifests itself during 257496f2e892SBill Paul * periods of heavy activity. The exact mode of failure if difficult to 257596f2e892SBill Paul * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 257696f2e892SBill Paul * will happen on slow machines. The bug is that sometimes instead of 257796f2e892SBill Paul * uploading one complete frame during reception, it uploads what looks 257896f2e892SBill Paul * like the entire contents of its FIFO memory. The frame we want is at 257996f2e892SBill Paul * the end of the whole mess, but we never know exactly how much data has 258096f2e892SBill Paul * been uploaded, so salvaging the frame is hard. 258196f2e892SBill Paul * 258296f2e892SBill Paul * There is only one way to do it reliably, and it's disgusting. 258396f2e892SBill Paul * Here's what we know: 258496f2e892SBill Paul * 258596f2e892SBill Paul * - We know there will always be somewhere between one and three extra 258696f2e892SBill Paul * descriptors uploaded. 258796f2e892SBill Paul * 258896f2e892SBill Paul * - We know the desired received frame will always be at the end of the 258996f2e892SBill Paul * total data upload. 259096f2e892SBill Paul * 259196f2e892SBill Paul * - We know the size of the desired received frame because it will be 259296f2e892SBill Paul * provided in the length field of the status word in the last descriptor. 259396f2e892SBill Paul * 259496f2e892SBill Paul * Here's what we do: 259596f2e892SBill Paul * 259696f2e892SBill Paul * - When we allocate buffers for the receive ring, we bzero() them. 259796f2e892SBill Paul * This means that we know that the buffer contents should be all 259896f2e892SBill Paul * zeros, except for data uploaded by the chip. 259996f2e892SBill Paul * 260096f2e892SBill Paul * - We also force the PNIC chip to upload frames that include the 260196f2e892SBill Paul * ethernet CRC at the end. 260296f2e892SBill Paul * 260396f2e892SBill Paul * - We gather all of the bogus frame data into a single buffer. 260496f2e892SBill Paul * 260596f2e892SBill Paul * - We then position a pointer at the end of this buffer and scan 260696f2e892SBill Paul * backwards until we encounter the first non-zero byte of data. 260796f2e892SBill Paul * This is the end of the received frame. We know we will encounter 260896f2e892SBill Paul * some data at the end of the frame because the CRC will always be 260996f2e892SBill Paul * there, so even if the sender transmits a packet of all zeros, 261096f2e892SBill Paul * we won't be fooled. 261196f2e892SBill Paul * 261296f2e892SBill Paul * - We know the size of the actual received frame, so we subtract 261396f2e892SBill Paul * that value from the current pointer location. This brings us 261496f2e892SBill Paul * to the start of the actual received packet. 261596f2e892SBill Paul * 261696f2e892SBill Paul * - We copy this into an mbuf and pass it on, along with the actual 261796f2e892SBill Paul * frame length. 261896f2e892SBill Paul * 261996f2e892SBill Paul * The performance hit is tremendous, but it beats dropping frames all 262096f2e892SBill Paul * the time. 262196f2e892SBill Paul */ 262296f2e892SBill Paul 262396f2e892SBill Paul #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG | DC_RXSTAT_LASTFRAG) 2624e3d2833aSAlfred Perlstein static void 26250934f18aSMaxime Henrion dc_pnic_rx_bug_war(struct dc_softc *sc, int idx) 262696f2e892SBill Paul { 262796f2e892SBill Paul struct dc_desc *cur_rx; 262896f2e892SBill Paul struct dc_desc *c = NULL; 262996f2e892SBill Paul struct mbuf *m = NULL; 263096f2e892SBill Paul unsigned char *ptr; 263196f2e892SBill Paul int i, total_len; 263296f2e892SBill Paul u_int32_t rxstat = 0; 263396f2e892SBill Paul 263496f2e892SBill Paul i = sc->dc_pnic_rx_bug_save; 263596f2e892SBill Paul cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 263696f2e892SBill Paul ptr = sc->dc_pnic_rx_buf; 26371edc4c46SMaxime Henrion bzero(ptr, DC_RXLEN * 5); 263896f2e892SBill Paul 263996f2e892SBill Paul /* Copy all the bytes from the bogus buffers. */ 264096f2e892SBill Paul while (1) { 264196f2e892SBill Paul c = &sc->dc_ldata->dc_rx_list[i]; 2642af4358c7SMaxime Henrion rxstat = le32toh(c->dc_status); 264396f2e892SBill Paul m = sc->dc_cdata.dc_rx_chain[i]; 264496f2e892SBill Paul bcopy(mtod(m, char *), ptr, DC_RXLEN); 264596f2e892SBill Paul ptr += DC_RXLEN; 264696f2e892SBill Paul /* If this is the last buffer, break out. */ 264796f2e892SBill Paul if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 264896f2e892SBill Paul break; 264956e5e7aeSMaxime Henrion dc_newbuf(sc, i, 0); 265096f2e892SBill Paul DC_INC(i, DC_RX_LIST_CNT); 265196f2e892SBill Paul } 265296f2e892SBill Paul 265396f2e892SBill Paul /* Find the length of the actual receive frame. */ 265496f2e892SBill Paul total_len = DC_RXBYTES(rxstat); 265596f2e892SBill Paul 265696f2e892SBill Paul /* Scan backwards until we hit a non-zero byte. */ 265796f2e892SBill Paul while (*ptr == 0x00) 265896f2e892SBill Paul ptr--; 265996f2e892SBill Paul 266096f2e892SBill Paul /* Round off. */ 266196f2e892SBill Paul if ((uintptr_t)(ptr) & 0x3) 266296f2e892SBill Paul ptr -= 1; 266396f2e892SBill Paul 266496f2e892SBill Paul /* Now find the start of the frame. */ 266596f2e892SBill Paul ptr -= total_len; 266696f2e892SBill Paul if (ptr < sc->dc_pnic_rx_buf) 266796f2e892SBill Paul ptr = sc->dc_pnic_rx_buf; 266896f2e892SBill Paul 266996f2e892SBill Paul /* 267096f2e892SBill Paul * Now copy the salvaged frame to the last mbuf and fake up 267196f2e892SBill Paul * the status word to make it look like a successful 267296f2e892SBill Paul * frame reception. 267396f2e892SBill Paul */ 267456e5e7aeSMaxime Henrion dc_newbuf(sc, i, 0); 267596f2e892SBill Paul bcopy(ptr, mtod(m, char *), total_len); 2676af4358c7SMaxime Henrion cur_rx->dc_status = htole32(rxstat | DC_RXSTAT_FIRSTFRAG); 267796f2e892SBill Paul } 267896f2e892SBill Paul 267996f2e892SBill Paul /* 268073bf949cSBill Paul * This routine searches the RX ring for dirty descriptors in the 268173bf949cSBill Paul * event that the rxeof routine falls out of sync with the chip's 268273bf949cSBill Paul * current descriptor pointer. This may happen sometimes as a result 268373bf949cSBill Paul * of a "no RX buffer available" condition that happens when the chip 268473bf949cSBill Paul * consumes all of the RX buffers before the driver has a chance to 268573bf949cSBill Paul * process the RX ring. This routine may need to be called more than 268673bf949cSBill Paul * once to bring the driver back in sync with the chip, however we 268773bf949cSBill Paul * should still be getting RX DONE interrupts to drive the search 268873bf949cSBill Paul * for new packets in the RX ring, so we should catch up eventually. 268973bf949cSBill Paul */ 2690e3d2833aSAlfred Perlstein static int 26910934f18aSMaxime Henrion dc_rx_resync(struct dc_softc *sc) 269273bf949cSBill Paul { 269373bf949cSBill Paul struct dc_desc *cur_rx; 26940934f18aSMaxime Henrion int i, pos; 269573bf949cSBill Paul 269673bf949cSBill Paul pos = sc->dc_cdata.dc_rx_prod; 269773bf949cSBill Paul 269873bf949cSBill Paul for (i = 0; i < DC_RX_LIST_CNT; i++) { 269973bf949cSBill Paul cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2700af4358c7SMaxime Henrion if (!(le32toh(cur_rx->dc_status) & DC_RXSTAT_OWN)) 270173bf949cSBill Paul break; 270273bf949cSBill Paul DC_INC(pos, DC_RX_LIST_CNT); 270373bf949cSBill Paul } 270473bf949cSBill Paul 270573bf949cSBill Paul /* If the ring really is empty, then just return. */ 270673bf949cSBill Paul if (i == DC_RX_LIST_CNT) 270773bf949cSBill Paul return (0); 270873bf949cSBill Paul 270973bf949cSBill Paul /* We've fallen behing the chip: catch it. */ 271073bf949cSBill Paul sc->dc_cdata.dc_rx_prod = pos; 271173bf949cSBill Paul 271273bf949cSBill Paul return (EAGAIN); 271373bf949cSBill Paul } 271473bf949cSBill Paul 271573bf949cSBill Paul /* 271696f2e892SBill Paul * A frame has been uploaded: pass the resulting mbuf chain up to 271796f2e892SBill Paul * the higher level protocols. 271896f2e892SBill Paul */ 27191abcdbd1SAttilio Rao static int 27200934f18aSMaxime Henrion dc_rxeof(struct dc_softc *sc) 272196f2e892SBill Paul { 2722432120f2SMarius Strobl struct mbuf *m, *m0; 272396f2e892SBill Paul struct ifnet *ifp; 272496f2e892SBill Paul struct dc_desc *cur_rx; 27251abcdbd1SAttilio Rao int i, total_len, rx_npkts; 272696f2e892SBill Paul u_int32_t rxstat; 272796f2e892SBill Paul 27285120abbfSSam Leffler DC_LOCK_ASSERT(sc); 27295120abbfSSam Leffler 2730fc74a9f9SBrooks Davis ifp = sc->dc_ifp; 273196f2e892SBill Paul i = sc->dc_cdata.dc_rx_prod; 27321abcdbd1SAttilio Rao total_len = 0; 27331abcdbd1SAttilio Rao rx_npkts = 0; 273496f2e892SBill Paul 273556e5e7aeSMaxime Henrion bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD); 2736af4358c7SMaxime Henrion while (!(le32toh(sc->dc_ldata->dc_rx_list[i].dc_status) & 2737af4358c7SMaxime Henrion DC_RXSTAT_OWN)) { 2738e4fc250cSLuigi Rizzo #ifdef DEVICE_POLLING 273940929967SGleb Smirnoff if (ifp->if_capenable & IFCAP_POLLING) { 2740e4fc250cSLuigi Rizzo if (sc->rxcycles <= 0) 2741e4fc250cSLuigi Rizzo break; 2742e4fc250cSLuigi Rizzo sc->rxcycles--; 2743e4fc250cSLuigi Rizzo } 27440934f18aSMaxime Henrion #endif 274596f2e892SBill Paul cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2746af4358c7SMaxime Henrion rxstat = le32toh(cur_rx->dc_status); 274796f2e892SBill Paul m = sc->dc_cdata.dc_rx_chain[i]; 274856e5e7aeSMaxime Henrion bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i], 274956e5e7aeSMaxime Henrion BUS_DMASYNC_POSTREAD); 275096f2e892SBill Paul total_len = DC_RXBYTES(rxstat); 275196f2e892SBill Paul 275296f2e892SBill Paul if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 275396f2e892SBill Paul if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 275496f2e892SBill Paul if (rxstat & DC_RXSTAT_FIRSTFRAG) 275596f2e892SBill Paul sc->dc_pnic_rx_bug_save = i; 275696f2e892SBill Paul if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 275796f2e892SBill Paul DC_INC(i, DC_RX_LIST_CNT); 275896f2e892SBill Paul continue; 275996f2e892SBill Paul } 276096f2e892SBill Paul dc_pnic_rx_bug_war(sc, i); 2761af4358c7SMaxime Henrion rxstat = le32toh(cur_rx->dc_status); 276296f2e892SBill Paul total_len = DC_RXBYTES(rxstat); 276396f2e892SBill Paul } 276496f2e892SBill Paul } 276596f2e892SBill Paul 276696f2e892SBill Paul /* 276796f2e892SBill Paul * If an error occurs, update stats, clear the 276896f2e892SBill Paul * status word and leave the mbuf cluster in place: 276996f2e892SBill Paul * it should simply get re-used next time this descriptor 2770db40c1aeSDoug Ambrisko * comes up in the ring. However, don't report long 27710934f18aSMaxime Henrion * frames as errors since they could be vlans. 277296f2e892SBill Paul */ 2773db40c1aeSDoug Ambrisko if ((rxstat & DC_RXSTAT_RXERR)) { 2774db40c1aeSDoug Ambrisko if (!(rxstat & DC_RXSTAT_GIANT) || 2775db40c1aeSDoug Ambrisko (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2776db40c1aeSDoug Ambrisko DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2777db40c1aeSDoug Ambrisko DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 277896f2e892SBill Paul ifp->if_ierrors++; 277996f2e892SBill Paul if (rxstat & DC_RXSTAT_COLLSEEN) 278096f2e892SBill Paul ifp->if_collisions++; 278156e5e7aeSMaxime Henrion dc_newbuf(sc, i, 0); 278296f2e892SBill Paul if (rxstat & DC_RXSTAT_CRCERR) { 278396f2e892SBill Paul DC_INC(i, DC_RX_LIST_CNT); 278496f2e892SBill Paul continue; 278596f2e892SBill Paul } else { 2786c8b27acaSJohn Baldwin dc_init_locked(sc); 27871abcdbd1SAttilio Rao return (rx_npkts); 278896f2e892SBill Paul } 278996f2e892SBill Paul } 2790db40c1aeSDoug Ambrisko } 279196f2e892SBill Paul 279296f2e892SBill Paul /* No errors; receive the packet. */ 279396f2e892SBill Paul total_len -= ETHER_CRC_LEN; 2794432120f2SMarius Strobl #ifdef __NO_STRICT_ALIGNMENT 279501faf54bSLuigi Rizzo /* 2796432120f2SMarius Strobl * On architectures without alignment problems we try to 279701faf54bSLuigi Rizzo * allocate a new buffer for the receive ring, and pass up 279801faf54bSLuigi Rizzo * the one where the packet is already, saving the expensive 279901faf54bSLuigi Rizzo * copy done in m_devget(). 280001faf54bSLuigi Rizzo * If we are on an architecture with alignment problems, or 280101faf54bSLuigi Rizzo * if the allocation fails, then use m_devget and leave the 280201faf54bSLuigi Rizzo * existing buffer in the receive ring. 280301faf54bSLuigi Rizzo */ 2804432120f2SMarius Strobl if (dc_newbuf(sc, i, 1) == 0) { 280501faf54bSLuigi Rizzo m->m_pkthdr.rcvif = ifp; 280601faf54bSLuigi Rizzo m->m_pkthdr.len = m->m_len = total_len; 280701faf54bSLuigi Rizzo DC_INC(i, DC_RX_LIST_CNT); 280801faf54bSLuigi Rizzo } else 280901faf54bSLuigi Rizzo #endif 281001faf54bSLuigi Rizzo { 281101faf54bSLuigi Rizzo m0 = m_devget(mtod(m, char *), total_len, 281201faf54bSLuigi Rizzo ETHER_ALIGN, ifp, NULL); 281356e5e7aeSMaxime Henrion dc_newbuf(sc, i, 0); 281496f2e892SBill Paul DC_INC(i, DC_RX_LIST_CNT); 281596f2e892SBill Paul if (m0 == NULL) { 281696f2e892SBill Paul ifp->if_ierrors++; 281796f2e892SBill Paul continue; 281896f2e892SBill Paul } 281996f2e892SBill Paul m = m0; 282001faf54bSLuigi Rizzo } 282196f2e892SBill Paul 282296f2e892SBill Paul ifp->if_ipackets++; 28235120abbfSSam Leffler DC_UNLOCK(sc); 28249ef8b520SSam Leffler (*ifp->if_input)(ifp, m); 28255120abbfSSam Leffler DC_LOCK(sc); 28261abcdbd1SAttilio Rao rx_npkts++; 282796f2e892SBill Paul } 282896f2e892SBill Paul 282996f2e892SBill Paul sc->dc_cdata.dc_rx_prod = i; 28301abcdbd1SAttilio Rao return (rx_npkts); 283196f2e892SBill Paul } 283296f2e892SBill Paul 283396f2e892SBill Paul /* 283496f2e892SBill Paul * A frame was downloaded to the chip. It's safe for us to clean up 283596f2e892SBill Paul * the list buffers. 283696f2e892SBill Paul */ 2837e3d2833aSAlfred Perlstein static void 28380934f18aSMaxime Henrion dc_txeof(struct dc_softc *sc) 283996f2e892SBill Paul { 284096f2e892SBill Paul struct dc_desc *cur_tx = NULL; 284196f2e892SBill Paul struct ifnet *ifp; 284296f2e892SBill Paul int idx; 2843af4358c7SMaxime Henrion u_int32_t ctl, txstat; 284496f2e892SBill Paul 2845*06d23883SPyun YongHyeon if (sc->dc_cdata.dc_tx_cnt == 0) 2846*06d23883SPyun YongHyeon return; 2847*06d23883SPyun YongHyeon 2848fc74a9f9SBrooks Davis ifp = sc->dc_ifp; 284996f2e892SBill Paul 285096f2e892SBill Paul /* 285196f2e892SBill Paul * Go through our tx list and free mbufs for those 285296f2e892SBill Paul * frames that have been transmitted. 285396f2e892SBill Paul */ 285456e5e7aeSMaxime Henrion bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD); 285596f2e892SBill Paul idx = sc->dc_cdata.dc_tx_cons; 285696f2e892SBill Paul while (idx != sc->dc_cdata.dc_tx_prod) { 285796f2e892SBill Paul 285896f2e892SBill Paul cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2859af4358c7SMaxime Henrion txstat = le32toh(cur_tx->dc_status); 2860af4358c7SMaxime Henrion ctl = le32toh(cur_tx->dc_ctl); 286196f2e892SBill Paul 286296f2e892SBill Paul if (txstat & DC_TXSTAT_OWN) 286396f2e892SBill Paul break; 286496f2e892SBill Paul 28654ff4a9beSDon Lewis if (!(ctl & DC_TXCTL_LASTFRAG) || ctl & DC_TXCTL_SETUP) { 2866af4358c7SMaxime Henrion if (ctl & DC_TXCTL_SETUP) { 286796f2e892SBill Paul /* 286896f2e892SBill Paul * Yes, the PNIC is so brain damaged 286996f2e892SBill Paul * that it will sometimes generate a TX 287096f2e892SBill Paul * underrun error while DMAing the RX 287196f2e892SBill Paul * filter setup frame. If we detect this, 287296f2e892SBill Paul * we have to send the setup frame again, 287396f2e892SBill Paul * or else the filter won't be programmed 287496f2e892SBill Paul * correctly. 287596f2e892SBill Paul */ 287696f2e892SBill Paul if (DC_IS_PNIC(sc)) { 287796f2e892SBill Paul if (txstat & DC_TXSTAT_ERRSUM) 287896f2e892SBill Paul dc_setfilt(sc); 287996f2e892SBill Paul } 288096f2e892SBill Paul sc->dc_cdata.dc_tx_chain[idx] = NULL; 288196f2e892SBill Paul } 2882bcb9ef4fSLuigi Rizzo sc->dc_cdata.dc_tx_cnt--; 288396f2e892SBill Paul DC_INC(idx, DC_TX_LIST_CNT); 288496f2e892SBill Paul continue; 288596f2e892SBill Paul } 288696f2e892SBill Paul 288729a2220aSBill Paul if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) { 2888feb78939SJonathan Chen /* 2889feb78939SJonathan Chen * XXX: Why does my Xircom taunt me so? 2890feb78939SJonathan Chen * For some reason it likes setting the CARRLOST flag 289129a2220aSBill Paul * even when the carrier is there. wtf?!? 289229a2220aSBill Paul * Who knows, but Conexant chips have the 289329a2220aSBill Paul * same problem. Maybe they took lessons 289429a2220aSBill Paul * from Xircom. 289529a2220aSBill Paul */ 2896feb78939SJonathan Chen if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2897feb78939SJonathan Chen sc->dc_pmode == DC_PMODE_MII && 2898feb78939SJonathan Chen ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 2899feb78939SJonathan Chen DC_TXSTAT_NOCARRIER))) 2900feb78939SJonathan Chen txstat &= ~DC_TXSTAT_ERRSUM; 2901feb78939SJonathan Chen } else { 290296f2e892SBill Paul if (/*sc->dc_type == DC_TYPE_21143 &&*/ 290396f2e892SBill Paul sc->dc_pmode == DC_PMODE_MII && 290496f2e892SBill Paul ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 290596f2e892SBill Paul DC_TXSTAT_NOCARRIER | DC_TXSTAT_CARRLOST))) 290696f2e892SBill Paul txstat &= ~DC_TXSTAT_ERRSUM; 2907feb78939SJonathan Chen } 290896f2e892SBill Paul 290996f2e892SBill Paul if (txstat & DC_TXSTAT_ERRSUM) { 291096f2e892SBill Paul ifp->if_oerrors++; 291196f2e892SBill Paul if (txstat & DC_TXSTAT_EXCESSCOLL) 291296f2e892SBill Paul ifp->if_collisions++; 291396f2e892SBill Paul if (txstat & DC_TXSTAT_LATECOLL) 291496f2e892SBill Paul ifp->if_collisions++; 291596f2e892SBill Paul if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2916c8b27acaSJohn Baldwin dc_init_locked(sc); 291796f2e892SBill Paul return; 291896f2e892SBill Paul } 291996f2e892SBill Paul } 292096f2e892SBill Paul 292196f2e892SBill Paul ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 292296f2e892SBill Paul 292396f2e892SBill Paul ifp->if_opackets++; 292496f2e892SBill Paul if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 292556e5e7aeSMaxime Henrion bus_dmamap_sync(sc->dc_mtag, 292656e5e7aeSMaxime Henrion sc->dc_cdata.dc_tx_map[idx], 292756e5e7aeSMaxime Henrion BUS_DMASYNC_POSTWRITE); 292856e5e7aeSMaxime Henrion bus_dmamap_unload(sc->dc_mtag, 292956e5e7aeSMaxime Henrion sc->dc_cdata.dc_tx_map[idx]); 293096f2e892SBill Paul m_freem(sc->dc_cdata.dc_tx_chain[idx]); 293196f2e892SBill Paul sc->dc_cdata.dc_tx_chain[idx] = NULL; 293296f2e892SBill Paul } 293396f2e892SBill Paul 293496f2e892SBill Paul sc->dc_cdata.dc_tx_cnt--; 293596f2e892SBill Paul DC_INC(idx, DC_TX_LIST_CNT); 293696f2e892SBill Paul } 293796f2e892SBill Paul sc->dc_cdata.dc_tx_cons = idx; 293882a67a70SMarius Strobl 293982a67a70SMarius Strobl if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt > DC_TX_LIST_RSVD) 294013f4c340SRobert Watson ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 294182a67a70SMarius Strobl 29423e0e6726SMarius Strobl if (sc->dc_cdata.dc_tx_cnt == 0) 29433e0e6726SMarius Strobl sc->dc_wdog_timer = 0; 294496f2e892SBill Paul } 294596f2e892SBill Paul 2946e3d2833aSAlfred Perlstein static void 29470934f18aSMaxime Henrion dc_tick(void *xsc) 294896f2e892SBill Paul { 294996f2e892SBill Paul struct dc_softc *sc; 295096f2e892SBill Paul struct mii_data *mii; 295196f2e892SBill Paul struct ifnet *ifp; 295296f2e892SBill Paul u_int32_t r; 295396f2e892SBill Paul 295496f2e892SBill Paul sc = xsc; 2955c8b27acaSJohn Baldwin DC_LOCK_ASSERT(sc); 2956fc74a9f9SBrooks Davis ifp = sc->dc_ifp; 295796f2e892SBill Paul mii = device_get_softc(sc->dc_miibus); 295896f2e892SBill Paul 2959*06d23883SPyun YongHyeon /* 2960*06d23883SPyun YongHyeon * Reclaim transmitted frames for controllers that do 2961*06d23883SPyun YongHyeon * not generate TX completion interrupt for every frame. 2962*06d23883SPyun YongHyeon */ 2963*06d23883SPyun YongHyeon if (sc->dc_flags & DC_TX_USE_TX_INTR) 2964*06d23883SPyun YongHyeon dc_txeof(sc); 2965*06d23883SPyun YongHyeon 296696f2e892SBill Paul if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2967318b02fdSBill Paul if (sc->dc_flags & DC_21143_NWAY) { 2968318b02fdSBill Paul r = CSR_READ_4(sc, DC_10BTSTAT); 2969318b02fdSBill Paul if (IFM_SUBTYPE(mii->mii_media_active) == 2970318b02fdSBill Paul IFM_100_TX && (r & DC_TSTAT_LS100)) { 297196f2e892SBill Paul sc->dc_link = 0; 2972318b02fdSBill Paul mii_mediachg(mii); 2973318b02fdSBill Paul } 2974318b02fdSBill Paul if (IFM_SUBTYPE(mii->mii_media_active) == 2975318b02fdSBill Paul IFM_10_T && (r & DC_TSTAT_LS10)) { 2976318b02fdSBill Paul sc->dc_link = 0; 2977318b02fdSBill Paul mii_mediachg(mii); 2978318b02fdSBill Paul } 2979d675147eSBill Paul if (sc->dc_link == 0) 298096f2e892SBill Paul mii_tick(mii); 298196f2e892SBill Paul } else { 2982d0d67284SMarius Strobl /* 2983d0d67284SMarius Strobl * For NICs which never report DC_RXSTATE_WAIT, we 2984d0d67284SMarius Strobl * have to bite the bullet... 2985d0d67284SMarius Strobl */ 2986d0d67284SMarius Strobl if ((DC_HAS_BROKEN_RXSTATE(sc) || (CSR_READ_4(sc, 2987d0d67284SMarius Strobl DC_ISR) & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT) && 2988d314ebf5SPyun YongHyeon sc->dc_cdata.dc_tx_cnt == 0) 298996f2e892SBill Paul mii_tick(mii); 2990259b8d84SMartin Blapp } 299196f2e892SBill Paul } else 299296f2e892SBill Paul mii_tick(mii); 299396f2e892SBill Paul 299496f2e892SBill Paul /* 299596f2e892SBill Paul * When the init routine completes, we expect to be able to send 299696f2e892SBill Paul * packets right away, and in fact the network code will send a 299796f2e892SBill Paul * gratuitous ARP the moment the init routine marks the interface 299896f2e892SBill Paul * as running. However, even though the MAC may have been initialized, 299996f2e892SBill Paul * there may be a delay of a few seconds before the PHY completes 300096f2e892SBill Paul * autonegotiation and the link is brought up. Any transmissions 300196f2e892SBill Paul * made during that delay will be lost. Dealing with this is tricky: 300296f2e892SBill Paul * we can't just pause in the init routine while waiting for the 300396f2e892SBill Paul * PHY to come ready since that would bring the whole system to 300496f2e892SBill Paul * a screeching halt for several seconds. 300596f2e892SBill Paul * 300696f2e892SBill Paul * What we do here is prevent the TX start routine from sending 300796f2e892SBill Paul * any packets until a link has been established. After the 300896f2e892SBill Paul * interface has been initialized, the tick routine will poll 300996f2e892SBill Paul * the state of the PHY until the IFM_ACTIVE flag is set. Until 301096f2e892SBill Paul * that time, packets will stay in the send queue, and once the 301196f2e892SBill Paul * link comes up, they will be flushed out to the wire. 301296f2e892SBill Paul */ 3013d314ebf5SPyun YongHyeon if (sc->dc_link != 0 && !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3014c8b27acaSJohn Baldwin dc_start_locked(ifp); 301596f2e892SBill Paul 3016318b02fdSBill Paul if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 3017b50c6312SJonathan Lemon callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3018318b02fdSBill Paul else 3019b50c6312SJonathan Lemon callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 302096f2e892SBill Paul } 302196f2e892SBill Paul 3022d467c136SBill Paul /* 3023d467c136SBill Paul * A transmit underrun has occurred. Back off the transmit threshold, 3024d467c136SBill Paul * or switch to store and forward mode if we have to. 3025d467c136SBill Paul */ 3026e3d2833aSAlfred Perlstein static void 30270934f18aSMaxime Henrion dc_tx_underrun(struct dc_softc *sc) 3028d467c136SBill Paul { 3029d467c136SBill Paul u_int32_t isr; 3030d467c136SBill Paul int i; 3031d467c136SBill Paul 3032d467c136SBill Paul if (DC_IS_DAVICOM(sc)) 3033c8b27acaSJohn Baldwin dc_init_locked(sc); 3034d467c136SBill Paul 3035d467c136SBill Paul if (DC_IS_INTEL(sc)) { 3036d467c136SBill Paul /* 3037d467c136SBill Paul * The real 21143 requires that the transmitter be idle 3038d467c136SBill Paul * in order to change the transmit threshold or store 3039d467c136SBill Paul * and forward state. 3040d467c136SBill Paul */ 3041d467c136SBill Paul DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3042d467c136SBill Paul 3043d467c136SBill Paul for (i = 0; i < DC_TIMEOUT; i++) { 3044d467c136SBill Paul isr = CSR_READ_4(sc, DC_ISR); 3045d467c136SBill Paul if (isr & DC_ISR_TX_IDLE) 3046d467c136SBill Paul break; 3047d467c136SBill Paul DELAY(10); 3048d467c136SBill Paul } 3049d467c136SBill Paul if (i == DC_TIMEOUT) { 30506b9f5c94SGleb Smirnoff device_printf(sc->dc_dev, 3051432120f2SMarius Strobl "%s: failed to force tx to idle state\n", 3052432120f2SMarius Strobl __func__); 3053c8b27acaSJohn Baldwin dc_init_locked(sc); 3054d467c136SBill Paul } 3055d467c136SBill Paul } 3056d467c136SBill Paul 30576b9f5c94SGleb Smirnoff device_printf(sc->dc_dev, "TX underrun -- "); 3058d467c136SBill Paul sc->dc_txthresh += DC_TXTHRESH_INC; 3059d467c136SBill Paul if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3060d467c136SBill Paul printf("using store and forward mode\n"); 3061d467c136SBill Paul DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3062d467c136SBill Paul } else { 3063d467c136SBill Paul printf("increasing TX threshold\n"); 3064d467c136SBill Paul DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3065d467c136SBill Paul DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3066d467c136SBill Paul } 3067d467c136SBill Paul 3068d467c136SBill Paul if (DC_IS_INTEL(sc)) 3069d467c136SBill Paul DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3070d467c136SBill Paul } 3071d467c136SBill Paul 3072e4fc250cSLuigi Rizzo #ifdef DEVICE_POLLING 3073e4fc250cSLuigi Rizzo static poll_handler_t dc_poll; 3074e4fc250cSLuigi Rizzo 30751abcdbd1SAttilio Rao static int 3076e4fc250cSLuigi Rizzo dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 3077e4fc250cSLuigi Rizzo { 3078e4fc250cSLuigi Rizzo struct dc_softc *sc = ifp->if_softc; 30791abcdbd1SAttilio Rao int rx_npkts = 0; 3080e4fc250cSLuigi Rizzo 308140929967SGleb Smirnoff DC_LOCK(sc); 308240929967SGleb Smirnoff 308340929967SGleb Smirnoff if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 308440929967SGleb Smirnoff DC_UNLOCK(sc); 30851abcdbd1SAttilio Rao return (rx_npkts); 3086e4fc250cSLuigi Rizzo } 308740929967SGleb Smirnoff 3088e4fc250cSLuigi Rizzo sc->rxcycles = count; 30891abcdbd1SAttilio Rao rx_npkts = dc_rxeof(sc); 3090e4fc250cSLuigi Rizzo dc_txeof(sc); 309113f4c340SRobert Watson if (!IFQ_IS_EMPTY(&ifp->if_snd) && 309213f4c340SRobert Watson !(ifp->if_drv_flags & IFF_DRV_OACTIVE)) 3093c8b27acaSJohn Baldwin dc_start_locked(ifp); 3094e4fc250cSLuigi Rizzo 3095e4fc250cSLuigi Rizzo if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 3096e4fc250cSLuigi Rizzo u_int32_t status; 3097e4fc250cSLuigi Rizzo 3098e4fc250cSLuigi Rizzo status = CSR_READ_4(sc, DC_ISR); 3099e4fc250cSLuigi Rizzo status &= (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF | 3100e4fc250cSLuigi Rizzo DC_ISR_TX_NOBUF | DC_ISR_TX_IDLE | DC_ISR_TX_UNDERRUN | 3101e4fc250cSLuigi Rizzo DC_ISR_BUS_ERR); 31025120abbfSSam Leffler if (!status) { 31035120abbfSSam Leffler DC_UNLOCK(sc); 31041abcdbd1SAttilio Rao return (rx_npkts); 31055120abbfSSam Leffler } 3106e4fc250cSLuigi Rizzo /* ack what we have */ 3107e4fc250cSLuigi Rizzo CSR_WRITE_4(sc, DC_ISR, status); 3108e4fc250cSLuigi Rizzo 3109e4fc250cSLuigi Rizzo if (status & (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF)) { 3110e4fc250cSLuigi Rizzo u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 3111e4fc250cSLuigi Rizzo ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 3112e4fc250cSLuigi Rizzo 3113e4fc250cSLuigi Rizzo if (dc_rx_resync(sc)) 3114e4fc250cSLuigi Rizzo dc_rxeof(sc); 3115e4fc250cSLuigi Rizzo } 3116e4fc250cSLuigi Rizzo /* restart transmit unit if necessary */ 3117e4fc250cSLuigi Rizzo if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 3118e4fc250cSLuigi Rizzo CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3119e4fc250cSLuigi Rizzo 3120e4fc250cSLuigi Rizzo if (status & DC_ISR_TX_UNDERRUN) 3121e4fc250cSLuigi Rizzo dc_tx_underrun(sc); 3122e4fc250cSLuigi Rizzo 3123e4fc250cSLuigi Rizzo if (status & DC_ISR_BUS_ERR) { 31246b9f5c94SGleb Smirnoff if_printf(ifp, "%s: bus error\n", __func__); 3125e4fc250cSLuigi Rizzo dc_reset(sc); 3126c8b27acaSJohn Baldwin dc_init_locked(sc); 3127e4fc250cSLuigi Rizzo } 3128e4fc250cSLuigi Rizzo } 31295120abbfSSam Leffler DC_UNLOCK(sc); 31301abcdbd1SAttilio Rao return (rx_npkts); 3131e4fc250cSLuigi Rizzo } 3132e4fc250cSLuigi Rizzo #endif /* DEVICE_POLLING */ 3133e4fc250cSLuigi Rizzo 3134e3d2833aSAlfred Perlstein static void 31350934f18aSMaxime Henrion dc_intr(void *arg) 313696f2e892SBill Paul { 313796f2e892SBill Paul struct dc_softc *sc; 313896f2e892SBill Paul struct ifnet *ifp; 313996f2e892SBill Paul u_int32_t status; 314096f2e892SBill Paul 314196f2e892SBill Paul sc = arg; 3142d2a1864bSWarner Losh 31430934f18aSMaxime Henrion if (sc->suspended) 3144e8388e14SMitsuru IWASAKI return; 3145e8388e14SMitsuru IWASAKI 3146d2a1864bSWarner Losh if ((CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) 3147d2a1864bSWarner Losh return; 3148d2a1864bSWarner Losh 3149d1ce9105SBill Paul DC_LOCK(sc); 3150fc74a9f9SBrooks Davis ifp = sc->dc_ifp; 3151e4fc250cSLuigi Rizzo #ifdef DEVICE_POLLING 315240929967SGleb Smirnoff if (ifp->if_capenable & IFCAP_POLLING) { 315340929967SGleb Smirnoff DC_UNLOCK(sc); 315440929967SGleb Smirnoff return; 3155e4fc250cSLuigi Rizzo } 31560934f18aSMaxime Henrion #endif 315796f2e892SBill Paul 3158d88a358cSLuigi Rizzo /* Suppress unwanted interrupts */ 315996f2e892SBill Paul if (!(ifp->if_flags & IFF_UP)) { 316096f2e892SBill Paul if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 316196f2e892SBill Paul dc_stop(sc); 3162d1ce9105SBill Paul DC_UNLOCK(sc); 316396f2e892SBill Paul return; 316496f2e892SBill Paul } 316596f2e892SBill Paul 316696f2e892SBill Paul /* Disable interrupts. */ 316796f2e892SBill Paul CSR_WRITE_4(sc, DC_IMR, 0x00000000); 316896f2e892SBill Paul 31697ed2454cSGleb Smirnoff while (((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) && 31707ed2454cSGleb Smirnoff status != 0xFFFFFFFF && 31715108cc56SGleb Smirnoff (ifp->if_drv_flags & IFF_DRV_RUNNING)) { 317296f2e892SBill Paul 317396f2e892SBill Paul CSR_WRITE_4(sc, DC_ISR, status); 317496f2e892SBill Paul 317573bf949cSBill Paul if (status & DC_ISR_RX_OK) { 317673bf949cSBill Paul int curpkts; 317773bf949cSBill Paul curpkts = ifp->if_ipackets; 317896f2e892SBill Paul dc_rxeof(sc); 317973bf949cSBill Paul if (curpkts == ifp->if_ipackets) { 318073bf949cSBill Paul while (dc_rx_resync(sc)) 318173bf949cSBill Paul dc_rxeof(sc); 318273bf949cSBill Paul } 318373bf949cSBill Paul } 318496f2e892SBill Paul 318596f2e892SBill Paul if (status & (DC_ISR_TX_OK | DC_ISR_TX_NOBUF)) 318696f2e892SBill Paul dc_txeof(sc); 318796f2e892SBill Paul 318896f2e892SBill Paul if (status & DC_ISR_TX_IDLE) { 318996f2e892SBill Paul dc_txeof(sc); 319096f2e892SBill Paul if (sc->dc_cdata.dc_tx_cnt) { 319196f2e892SBill Paul DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 319296f2e892SBill Paul CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 319396f2e892SBill Paul } 319496f2e892SBill Paul } 319596f2e892SBill Paul 3196d467c136SBill Paul if (status & DC_ISR_TX_UNDERRUN) 3197d467c136SBill Paul dc_tx_underrun(sc); 319896f2e892SBill Paul 319996f2e892SBill Paul if ((status & DC_ISR_RX_WATDOGTIMEO) 320073bf949cSBill Paul || (status & DC_ISR_RX_NOBUF)) { 320173bf949cSBill Paul int curpkts; 320273bf949cSBill Paul curpkts = ifp->if_ipackets; 320396f2e892SBill Paul dc_rxeof(sc); 320473bf949cSBill Paul if (curpkts == ifp->if_ipackets) { 320573bf949cSBill Paul while (dc_rx_resync(sc)) 320673bf949cSBill Paul dc_rxeof(sc); 320773bf949cSBill Paul } 320873bf949cSBill Paul } 320996f2e892SBill Paul 321096f2e892SBill Paul if (status & DC_ISR_BUS_ERR) { 321196f2e892SBill Paul dc_reset(sc); 3212c8b27acaSJohn Baldwin dc_init_locked(sc); 321396f2e892SBill Paul } 321496f2e892SBill Paul } 321596f2e892SBill Paul 321696f2e892SBill Paul /* Re-enable interrupts. */ 321796f2e892SBill Paul CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 321896f2e892SBill Paul 3219cbaf877fSBrian Feldman if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3220c8b27acaSJohn Baldwin dc_start_locked(ifp); 322196f2e892SBill Paul 3222d1ce9105SBill Paul DC_UNLOCK(sc); 322396f2e892SBill Paul } 322496f2e892SBill Paul 322596f2e892SBill Paul /* 322696f2e892SBill Paul * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 322796f2e892SBill Paul * pointers to the fragment pointers. 322896f2e892SBill Paul */ 3229e3d2833aSAlfred Perlstein static int 3230a10c0e45SMike Silbersack dc_encap(struct dc_softc *sc, struct mbuf **m_head) 323196f2e892SBill Paul { 3232ebc284ccSMarius Strobl bus_dma_segment_t segs[DC_MAXFRAGS]; 3233ebc284ccSMarius Strobl struct dc_desc *f; 323496f2e892SBill Paul struct mbuf *m; 3235993a741aSMarius Strobl int cur, defragged, error, first, frag, i, idx, nseg; 3236cda97c50SMike Silbersack 3237cda97c50SMike Silbersack /* 3238cda97c50SMike Silbersack * If there's no way we can send any packets, return now. 3239cda97c50SMike Silbersack */ 324082a67a70SMarius Strobl if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt <= DC_TX_LIST_RSVD) 3241cda97c50SMike Silbersack return (ENOBUFS); 3242cda97c50SMike Silbersack 3243993a741aSMarius Strobl m = NULL; 3244993a741aSMarius Strobl defragged = 0; 3245993a741aSMarius Strobl if (sc->dc_flags & DC_TX_COALESCE && 3246993a741aSMarius Strobl ((*m_head)->m_next != NULL || sc->dc_flags & DC_TX_ALIGN)) { 3247993a741aSMarius Strobl m = m_defrag(*m_head, M_DONTWAIT); 3248993a741aSMarius Strobl defragged = 1; 3249993a741aSMarius Strobl } else { 3250cda97c50SMike Silbersack /* 3251993a741aSMarius Strobl * Count the number of frags in this chain to see if we 3252993a741aSMarius Strobl * need to m_collapse. Since the descriptor list is shared 3253993a741aSMarius Strobl * by all packets, we'll m_collapse long chains so that they 3254cda97c50SMike Silbersack * do not use up the entire list, even if they would fit. 3255cda97c50SMike Silbersack */ 3256993a741aSMarius Strobl i = 0; 3257a10c0e45SMike Silbersack for (m = *m_head; m != NULL; m = m->m_next) 3258993a741aSMarius Strobl i++; 3259993a741aSMarius Strobl if (i > DC_TX_LIST_CNT / 4 || 3260993a741aSMarius Strobl DC_TX_LIST_CNT - i + sc->dc_cdata.dc_tx_cnt <= 3261993a741aSMarius Strobl DC_TX_LIST_RSVD) { 3262993a741aSMarius Strobl m = m_collapse(*m_head, M_DONTWAIT, DC_MAXFRAGS); 3263993a741aSMarius Strobl defragged = 1; 3264993a741aSMarius Strobl } 3265993a741aSMarius Strobl } 3266993a741aSMarius Strobl if (defragged != 0) { 326782a67a70SMarius Strobl if (m == NULL) { 326882a67a70SMarius Strobl m_freem(*m_head); 326982a67a70SMarius Strobl *m_head = NULL; 3270cda97c50SMike Silbersack return (ENOBUFS); 327182a67a70SMarius Strobl } 3272a10c0e45SMike Silbersack *m_head = m; 3273cda97c50SMike Silbersack } 3274993a741aSMarius Strobl 327556e5e7aeSMaxime Henrion idx = sc->dc_cdata.dc_tx_prod; 3276ebc284ccSMarius Strobl error = bus_dmamap_load_mbuf_sg(sc->dc_mtag, 3277ebc284ccSMarius Strobl sc->dc_cdata.dc_tx_map[idx], *m_head, segs, &nseg, 0); 3278ebc284ccSMarius Strobl if (error == EFBIG) { 3279993a741aSMarius Strobl if (defragged != 0 || (m = m_collapse(*m_head, M_DONTWAIT, 3280993a741aSMarius Strobl DC_MAXFRAGS)) == NULL) { 3281ebc284ccSMarius Strobl m_freem(*m_head); 328282a67a70SMarius Strobl *m_head = NULL; 3283993a741aSMarius Strobl return (defragged != 0 ? error : ENOBUFS); 328482a67a70SMarius Strobl } 3285ebc284ccSMarius Strobl *m_head = m; 3286ebc284ccSMarius Strobl error = bus_dmamap_load_mbuf_sg(sc->dc_mtag, 3287ebc284ccSMarius Strobl sc->dc_cdata.dc_tx_map[idx], *m_head, segs, &nseg, 0); 3288ebc284ccSMarius Strobl if (error != 0) { 3289ebc284ccSMarius Strobl m_freem(*m_head); 3290ebc284ccSMarius Strobl *m_head = NULL; 3291ebc284ccSMarius Strobl return (error); 329282a67a70SMarius Strobl } 3293ebc284ccSMarius Strobl } else if (error != 0) 3294ebc284ccSMarius Strobl return (error); 3295ebc284ccSMarius Strobl KASSERT(nseg <= DC_MAXFRAGS, 3296ebc284ccSMarius Strobl ("%s: wrong number of segments (%d)", __func__, nseg)); 3297ebc284ccSMarius Strobl if (nseg == 0) { 3298ebc284ccSMarius Strobl m_freem(*m_head); 3299ebc284ccSMarius Strobl *m_head = NULL; 3300ebc284ccSMarius Strobl return (EIO); 3301ebc284ccSMarius Strobl } 3302ebc284ccSMarius Strobl 3303ebc284ccSMarius Strobl first = cur = frag = sc->dc_cdata.dc_tx_prod; 3304ebc284ccSMarius Strobl for (i = 0; i < nseg; i++) { 3305ebc284ccSMarius Strobl if ((sc->dc_flags & DC_TX_ADMTEK_WAR) && 3306ebc284ccSMarius Strobl (frag == (DC_TX_LIST_CNT - 1)) && 3307ebc284ccSMarius Strobl (first != sc->dc_cdata.dc_tx_first)) { 3308ebc284ccSMarius Strobl bus_dmamap_unload(sc->dc_mtag, 3309ebc284ccSMarius Strobl sc->dc_cdata.dc_tx_map[first]); 3310ebc284ccSMarius Strobl m_freem(*m_head); 3311ebc284ccSMarius Strobl *m_head = NULL; 3312ebc284ccSMarius Strobl return (ENOBUFS); 3313ebc284ccSMarius Strobl } 3314ebc284ccSMarius Strobl 3315ebc284ccSMarius Strobl f = &sc->dc_ldata->dc_tx_list[frag]; 3316ebc284ccSMarius Strobl f->dc_ctl = htole32(DC_TXCTL_TLINK | segs[i].ds_len); 3317ebc284ccSMarius Strobl if (i == 0) { 3318ebc284ccSMarius Strobl f->dc_status = 0; 3319ebc284ccSMarius Strobl f->dc_ctl |= htole32(DC_TXCTL_FIRSTFRAG); 3320ebc284ccSMarius Strobl } else 3321ebc284ccSMarius Strobl f->dc_status = htole32(DC_TXSTAT_OWN); 3322ebc284ccSMarius Strobl f->dc_data = htole32(segs[i].ds_addr); 3323ebc284ccSMarius Strobl cur = frag; 3324ebc284ccSMarius Strobl DC_INC(frag, DC_TX_LIST_CNT); 3325ebc284ccSMarius Strobl } 3326ebc284ccSMarius Strobl 3327ebc284ccSMarius Strobl sc->dc_cdata.dc_tx_prod = frag; 3328ebc284ccSMarius Strobl sc->dc_cdata.dc_tx_cnt += nseg; 3329ebc284ccSMarius Strobl sc->dc_cdata.dc_tx_chain[cur] = *m_head; 3330ebc284ccSMarius Strobl sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_LASTFRAG); 3331ebc284ccSMarius Strobl if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 3332ebc284ccSMarius Strobl sc->dc_ldata->dc_tx_list[first].dc_ctl |= 3333ebc284ccSMarius Strobl htole32(DC_TXCTL_FINT); 3334ebc284ccSMarius Strobl if (sc->dc_flags & DC_TX_INTR_ALWAYS) 3335ebc284ccSMarius Strobl sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3336*06d23883SPyun YongHyeon if (sc->dc_flags & DC_TX_USE_TX_INTR && 3337*06d23883SPyun YongHyeon ++sc->dc_cdata.dc_tx_pkts >= 8) { 3338*06d23883SPyun YongHyeon sc->dc_cdata.dc_tx_pkts = 0; 3339ebc284ccSMarius Strobl sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3340*06d23883SPyun YongHyeon } 3341ebc284ccSMarius Strobl sc->dc_ldata->dc_tx_list[first].dc_status = htole32(DC_TXSTAT_OWN); 3342ebc284ccSMarius Strobl 334356e5e7aeSMaxime Henrion bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx], 334456e5e7aeSMaxime Henrion BUS_DMASYNC_PREWRITE); 334556e5e7aeSMaxime Henrion bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 334656e5e7aeSMaxime Henrion BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 334796f2e892SBill Paul return (0); 334896f2e892SBill Paul } 334996f2e892SBill Paul 3350e3d2833aSAlfred Perlstein static void 33510934f18aSMaxime Henrion dc_start(struct ifnet *ifp) 335296f2e892SBill Paul { 335396f2e892SBill Paul struct dc_softc *sc; 3354c8b27acaSJohn Baldwin 3355c8b27acaSJohn Baldwin sc = ifp->if_softc; 3356c8b27acaSJohn Baldwin DC_LOCK(sc); 3357c8b27acaSJohn Baldwin dc_start_locked(ifp); 3358c8b27acaSJohn Baldwin DC_UNLOCK(sc); 3359c8b27acaSJohn Baldwin } 3360c8b27acaSJohn Baldwin 3361ebc284ccSMarius Strobl /* 3362ebc284ccSMarius Strobl * Main transmit routine 3363ebc284ccSMarius Strobl * To avoid having to do mbuf copies, we put pointers to the mbuf data 3364ebc284ccSMarius Strobl * regions directly in the transmit lists. We also save a copy of the 3365ebc284ccSMarius Strobl * pointers since the transmit list fragment pointers are physical 3366ebc284ccSMarius Strobl * addresses. 3367ebc284ccSMarius Strobl */ 3368c8b27acaSJohn Baldwin static void 3369c8b27acaSJohn Baldwin dc_start_locked(struct ifnet *ifp) 3370c8b27acaSJohn Baldwin { 3371c8b27acaSJohn Baldwin struct dc_softc *sc; 337282a67a70SMarius Strobl struct mbuf *m_head = NULL; 3373cbaf877fSBrian Feldman unsigned int queued = 0; 337496f2e892SBill Paul int idx; 337596f2e892SBill Paul 337696f2e892SBill Paul sc = ifp->if_softc; 337796f2e892SBill Paul 3378c8b27acaSJohn Baldwin DC_LOCK_ASSERT(sc); 337996f2e892SBill Paul 3380c8b27acaSJohn Baldwin if (!sc->dc_link && ifp->if_snd.ifq_len < 10) 338196f2e892SBill Paul return; 3382d1ce9105SBill Paul 3383c8b27acaSJohn Baldwin if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 3384d1ce9105SBill Paul return; 338596f2e892SBill Paul 338656e5e7aeSMaxime Henrion idx = sc->dc_cdata.dc_tx_first = sc->dc_cdata.dc_tx_prod; 338796f2e892SBill Paul 338896f2e892SBill Paul while (sc->dc_cdata.dc_tx_chain[idx] == NULL) { 3389cbaf877fSBrian Feldman IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 339096f2e892SBill Paul if (m_head == NULL) 339196f2e892SBill Paul break; 339296f2e892SBill Paul 3393a10c0e45SMike Silbersack if (dc_encap(sc, &m_head)) { 339482a67a70SMarius Strobl if (m_head == NULL) 339582a67a70SMarius Strobl break; 3396cbaf877fSBrian Feldman IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 339713f4c340SRobert Watson ifp->if_drv_flags |= IFF_DRV_OACTIVE; 339896f2e892SBill Paul break; 339996f2e892SBill Paul } 340056e5e7aeSMaxime Henrion idx = sc->dc_cdata.dc_tx_prod; 340196f2e892SBill Paul 3402cbaf877fSBrian Feldman queued++; 340396f2e892SBill Paul /* 340496f2e892SBill Paul * If there's a BPF listener, bounce a copy of this frame 340596f2e892SBill Paul * to him. 340696f2e892SBill Paul */ 34079ef8b520SSam Leffler BPF_MTAP(ifp, m_head); 340896f2e892SBill Paul } 340996f2e892SBill Paul 3410cbaf877fSBrian Feldman if (queued > 0) { 341196f2e892SBill Paul /* Transmit */ 341296f2e892SBill Paul if (!(sc->dc_flags & DC_TX_POLL)) 341396f2e892SBill Paul CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 341496f2e892SBill Paul 341596f2e892SBill Paul /* 341696f2e892SBill Paul * Set a timeout in case the chip goes out to lunch. 341796f2e892SBill Paul */ 3418b1d16143SMarius Strobl sc->dc_wdog_timer = 5; 3419cbaf877fSBrian Feldman } 342096f2e892SBill Paul } 342196f2e892SBill Paul 3422e3d2833aSAlfred Perlstein static void 34230934f18aSMaxime Henrion dc_init(void *xsc) 342496f2e892SBill Paul { 342596f2e892SBill Paul struct dc_softc *sc = xsc; 3426c8b27acaSJohn Baldwin 3427c8b27acaSJohn Baldwin DC_LOCK(sc); 3428c8b27acaSJohn Baldwin dc_init_locked(sc); 3429c8b27acaSJohn Baldwin DC_UNLOCK(sc); 3430c8b27acaSJohn Baldwin } 3431c8b27acaSJohn Baldwin 3432c8b27acaSJohn Baldwin static void 3433c8b27acaSJohn Baldwin dc_init_locked(struct dc_softc *sc) 3434c8b27acaSJohn Baldwin { 3435fc74a9f9SBrooks Davis struct ifnet *ifp = sc->dc_ifp; 343696f2e892SBill Paul struct mii_data *mii; 3437d314ebf5SPyun YongHyeon struct ifmedia *ifm; 343896f2e892SBill Paul 3439c8b27acaSJohn Baldwin DC_LOCK_ASSERT(sc); 344096f2e892SBill Paul 344196f2e892SBill Paul mii = device_get_softc(sc->dc_miibus); 344296f2e892SBill Paul 344396f2e892SBill Paul /* 344496f2e892SBill Paul * Cancel pending I/O and free all RX/TX buffers. 344596f2e892SBill Paul */ 344696f2e892SBill Paul dc_stop(sc); 344796f2e892SBill Paul dc_reset(sc); 3448d314ebf5SPyun YongHyeon if (DC_IS_INTEL(sc)) { 3449d314ebf5SPyun YongHyeon ifm = &mii->mii_media; 3450d314ebf5SPyun YongHyeon dc_apply_fixup(sc, ifm->ifm_media); 3451d314ebf5SPyun YongHyeon } 345296f2e892SBill Paul 345396f2e892SBill Paul /* 345496f2e892SBill Paul * Set cache alignment and burst length. 345596f2e892SBill Paul */ 345688d739dcSBill Paul if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 345796f2e892SBill Paul CSR_WRITE_4(sc, DC_BUSCTL, 0); 345896f2e892SBill Paul else 345996f2e892SBill Paul CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME | DC_BUSCTL_MRLE); 3460935fe010SLuigi Rizzo /* 3461935fe010SLuigi Rizzo * Evenly share the bus between receive and transmit process. 3462935fe010SLuigi Rizzo */ 3463935fe010SLuigi Rizzo if (DC_IS_INTEL(sc)) 3464935fe010SLuigi Rizzo DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 346596f2e892SBill Paul if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 346696f2e892SBill Paul DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 346796f2e892SBill Paul } else { 346896f2e892SBill Paul DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 346996f2e892SBill Paul } 347096f2e892SBill Paul if (sc->dc_flags & DC_TX_POLL) 347196f2e892SBill Paul DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 347296f2e892SBill Paul switch(sc->dc_cachesize) { 347396f2e892SBill Paul case 32: 347496f2e892SBill Paul DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 347596f2e892SBill Paul break; 347696f2e892SBill Paul case 16: 347796f2e892SBill Paul DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 347896f2e892SBill Paul break; 347996f2e892SBill Paul case 8: 348096f2e892SBill Paul DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 348196f2e892SBill Paul break; 348296f2e892SBill Paul case 0: 348396f2e892SBill Paul default: 348496f2e892SBill Paul DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 348596f2e892SBill Paul break; 348696f2e892SBill Paul } 348796f2e892SBill Paul 348896f2e892SBill Paul if (sc->dc_flags & DC_TX_STORENFWD) 348996f2e892SBill Paul DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 349096f2e892SBill Paul else { 3491d467c136SBill Paul if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 349296f2e892SBill Paul DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 349396f2e892SBill Paul } else { 349496f2e892SBill Paul DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 349596f2e892SBill Paul DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 349696f2e892SBill Paul } 349796f2e892SBill Paul } 349896f2e892SBill Paul 349996f2e892SBill Paul DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 350096f2e892SBill Paul DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 350196f2e892SBill Paul 350296f2e892SBill Paul if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 350396f2e892SBill Paul /* 350496f2e892SBill Paul * The app notes for the 98713 and 98715A say that 350596f2e892SBill Paul * in order to have the chips operate properly, a magic 350696f2e892SBill Paul * number must be written to CSR16. Macronix does not 350796f2e892SBill Paul * document the meaning of these bits so there's no way 350896f2e892SBill Paul * to know exactly what they do. The 98713 has a magic 350996f2e892SBill Paul * number all its own; the rest all use a different one. 351096f2e892SBill Paul */ 351196f2e892SBill Paul DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 351296f2e892SBill Paul if (sc->dc_type == DC_TYPE_98713) 351396f2e892SBill Paul DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 351496f2e892SBill Paul else 351596f2e892SBill Paul DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 351696f2e892SBill Paul } 351796f2e892SBill Paul 3518feb78939SJonathan Chen if (DC_IS_XIRCOM(sc)) { 3519feb78939SJonathan Chen /* 3520feb78939SJonathan Chen * setup General Purpose Port mode and data so the tulip 3521feb78939SJonathan Chen * can talk to the MII. 3522feb78939SJonathan Chen */ 3523feb78939SJonathan Chen CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3524feb78939SJonathan Chen DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3525feb78939SJonathan Chen DELAY(10); 3526feb78939SJonathan Chen CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3527feb78939SJonathan Chen DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3528feb78939SJonathan Chen DELAY(10); 3529feb78939SJonathan Chen } 3530feb78939SJonathan Chen 353196f2e892SBill Paul DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3532d467c136SBill Paul DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 353396f2e892SBill Paul 353496f2e892SBill Paul /* Init circular RX list. */ 353596f2e892SBill Paul if (dc_list_rx_init(sc) == ENOBUFS) { 35366b9f5c94SGleb Smirnoff device_printf(sc->dc_dev, 353722f6205dSJohn Baldwin "initialization failed: no memory for rx buffers\n"); 353896f2e892SBill Paul dc_stop(sc); 353996f2e892SBill Paul return; 354096f2e892SBill Paul } 354196f2e892SBill Paul 354296f2e892SBill Paul /* 354356e5e7aeSMaxime Henrion * Init TX descriptors. 354496f2e892SBill Paul */ 354596f2e892SBill Paul dc_list_tx_init(sc); 354696f2e892SBill Paul 354796f2e892SBill Paul /* 354896f2e892SBill Paul * Load the address of the RX list. 354996f2e892SBill Paul */ 355056e5e7aeSMaxime Henrion CSR_WRITE_4(sc, DC_RXADDR, DC_RXDESC(sc, 0)); 355156e5e7aeSMaxime Henrion CSR_WRITE_4(sc, DC_TXADDR, DC_TXDESC(sc, 0)); 355296f2e892SBill Paul 355396f2e892SBill Paul /* 355496f2e892SBill Paul * Enable interrupts. 355596f2e892SBill Paul */ 3556e4fc250cSLuigi Rizzo #ifdef DEVICE_POLLING 3557e4fc250cSLuigi Rizzo /* 3558e4fc250cSLuigi Rizzo * ... but only if we are not polling, and make sure they are off in 3559e4fc250cSLuigi Rizzo * the case of polling. Some cards (e.g. fxp) turn interrupts on 3560e4fc250cSLuigi Rizzo * after a reset. 3561e4fc250cSLuigi Rizzo */ 356240929967SGleb Smirnoff if (ifp->if_capenable & IFCAP_POLLING) 3563e4fc250cSLuigi Rizzo CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3564e4fc250cSLuigi Rizzo else 3565e4fc250cSLuigi Rizzo #endif 356696f2e892SBill Paul CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 356796f2e892SBill Paul CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 356896f2e892SBill Paul 356996f2e892SBill Paul /* Enable transmitter. */ 357096f2e892SBill Paul DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 357196f2e892SBill Paul 357296f2e892SBill Paul /* 3573918434c8SBill Paul * If this is an Intel 21143 and we're not using the 3574918434c8SBill Paul * MII port, program the LED control pins so we get 3575918434c8SBill Paul * link and activity indications. 3576918434c8SBill Paul */ 357778999dd1SBill Paul if (sc->dc_flags & DC_TULIP_LEDS) { 3578918434c8SBill Paul CSR_WRITE_4(sc, DC_WATCHDOG, 3579918434c8SBill Paul DC_WDOG_CTLWREN | DC_WDOG_LINK | DC_WDOG_ACTIVITY); 358078999dd1SBill Paul CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3581918434c8SBill Paul } 3582918434c8SBill Paul 3583918434c8SBill Paul /* 358496f2e892SBill Paul * Load the RX/multicast filter. We do this sort of late 358596f2e892SBill Paul * because the filter programming scheme on the 21143 and 358696f2e892SBill Paul * some clones requires DMAing a setup frame via the TX 358796f2e892SBill Paul * engine, and we need the transmitter enabled for that. 358896f2e892SBill Paul */ 358996f2e892SBill Paul dc_setfilt(sc); 359096f2e892SBill Paul 359196f2e892SBill Paul /* Enable receiver. */ 359296f2e892SBill Paul DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 359396f2e892SBill Paul CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 359496f2e892SBill Paul 359513f4c340SRobert Watson ifp->if_drv_flags |= IFF_DRV_RUNNING; 359613f4c340SRobert Watson ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 359796f2e892SBill Paul 3598d314ebf5SPyun YongHyeon mii_mediachg(mii); 3599d314ebf5SPyun YongHyeon dc_setcfg(sc, sc->dc_if_media); 3600d314ebf5SPyun YongHyeon 3601857fd445SBill Paul /* Don't start the ticker if this is a homePNA link. */ 360245521525SPoul-Henning Kamp if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) 3603857fd445SBill Paul sc->dc_link = 1; 3604857fd445SBill Paul else { 3605318b02fdSBill Paul if (sc->dc_flags & DC_21143_NWAY) 3606b50c6312SJonathan Lemon callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3607318b02fdSBill Paul else 3608b50c6312SJonathan Lemon callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3609857fd445SBill Paul } 3610b1d16143SMarius Strobl 3611b1d16143SMarius Strobl sc->dc_wdog_timer = 0; 3612b1d16143SMarius Strobl callout_reset(&sc->dc_wdog_ch, hz, dc_watchdog, sc); 361396f2e892SBill Paul } 361496f2e892SBill Paul 361596f2e892SBill Paul /* 361696f2e892SBill Paul * Set media options. 361796f2e892SBill Paul */ 3618e3d2833aSAlfred Perlstein static int 36190934f18aSMaxime Henrion dc_ifmedia_upd(struct ifnet *ifp) 362096f2e892SBill Paul { 362196f2e892SBill Paul struct dc_softc *sc; 362296f2e892SBill Paul struct mii_data *mii; 3623f43d9309SBill Paul struct ifmedia *ifm; 362496f2e892SBill Paul 362596f2e892SBill Paul sc = ifp->if_softc; 362696f2e892SBill Paul mii = device_get_softc(sc->dc_miibus); 3627c8b27acaSJohn Baldwin DC_LOCK(sc); 362896f2e892SBill Paul mii_mediachg(mii); 3629f43d9309SBill Paul ifm = &mii->mii_media; 3630f43d9309SBill Paul 3631d314ebf5SPyun YongHyeon if (DC_IS_INTEL(sc)) 3632d314ebf5SPyun YongHyeon dc_setcfg(sc, ifm->ifm_media); 3633d314ebf5SPyun YongHyeon else if (DC_IS_DAVICOM(sc) && 363445521525SPoul-Henning Kamp IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) 3635f43d9309SBill Paul dc_setcfg(sc, ifm->ifm_media); 3636f43d9309SBill Paul else 363796f2e892SBill Paul sc->dc_link = 0; 3638c8b27acaSJohn Baldwin DC_UNLOCK(sc); 363996f2e892SBill Paul 364096f2e892SBill Paul return (0); 364196f2e892SBill Paul } 364296f2e892SBill Paul 364396f2e892SBill Paul /* 364496f2e892SBill Paul * Report current media status. 364596f2e892SBill Paul */ 3646e3d2833aSAlfred Perlstein static void 36470934f18aSMaxime Henrion dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 364896f2e892SBill Paul { 364996f2e892SBill Paul struct dc_softc *sc; 365096f2e892SBill Paul struct mii_data *mii; 3651f43d9309SBill Paul struct ifmedia *ifm; 365296f2e892SBill Paul 365396f2e892SBill Paul sc = ifp->if_softc; 365496f2e892SBill Paul mii = device_get_softc(sc->dc_miibus); 3655c8b27acaSJohn Baldwin DC_LOCK(sc); 365696f2e892SBill Paul mii_pollstat(mii); 3657f43d9309SBill Paul ifm = &mii->mii_media; 3658f43d9309SBill Paul if (DC_IS_DAVICOM(sc)) { 365945521525SPoul-Henning Kamp if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 3660f43d9309SBill Paul ifmr->ifm_active = ifm->ifm_media; 3661f43d9309SBill Paul ifmr->ifm_status = 0; 3662432120f2SMarius Strobl DC_UNLOCK(sc); 3663f43d9309SBill Paul return; 3664f43d9309SBill Paul } 3665f43d9309SBill Paul } 366696f2e892SBill Paul ifmr->ifm_active = mii->mii_media_active; 366796f2e892SBill Paul ifmr->ifm_status = mii->mii_media_status; 3668c8b27acaSJohn Baldwin DC_UNLOCK(sc); 366996f2e892SBill Paul } 367096f2e892SBill Paul 3671e3d2833aSAlfred Perlstein static int 36720934f18aSMaxime Henrion dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 367396f2e892SBill Paul { 367496f2e892SBill Paul struct dc_softc *sc = ifp->if_softc; 367596f2e892SBill Paul struct ifreq *ifr = (struct ifreq *)data; 367696f2e892SBill Paul struct mii_data *mii; 3677d1ce9105SBill Paul int error = 0; 367896f2e892SBill Paul 367996f2e892SBill Paul switch (command) { 368096f2e892SBill Paul case SIOCSIFFLAGS: 3681c8b27acaSJohn Baldwin DC_LOCK(sc); 368296f2e892SBill Paul if (ifp->if_flags & IFF_UP) { 36835d6dfbbbSLuigi Rizzo int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) & 36845d6dfbbbSLuigi Rizzo (IFF_PROMISC | IFF_ALLMULTI); 36855d6dfbbbSLuigi Rizzo 368613f4c340SRobert Watson if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 36875d6dfbbbSLuigi Rizzo if (need_setfilt) 368896f2e892SBill Paul dc_setfilt(sc); 36895d6dfbbbSLuigi Rizzo } else { 369096f2e892SBill Paul sc->dc_txthresh = 0; 3691c8b27acaSJohn Baldwin dc_init_locked(sc); 369296f2e892SBill Paul } 369396f2e892SBill Paul } else { 369413f4c340SRobert Watson if (ifp->if_drv_flags & IFF_DRV_RUNNING) 369596f2e892SBill Paul dc_stop(sc); 369696f2e892SBill Paul } 369796f2e892SBill Paul sc->dc_if_flags = ifp->if_flags; 3698c8b27acaSJohn Baldwin DC_UNLOCK(sc); 369996f2e892SBill Paul error = 0; 370096f2e892SBill Paul break; 370196f2e892SBill Paul case SIOCADDMULTI: 370296f2e892SBill Paul case SIOCDELMULTI: 3703c8b27acaSJohn Baldwin DC_LOCK(sc); 370496f2e892SBill Paul dc_setfilt(sc); 3705c8b27acaSJohn Baldwin DC_UNLOCK(sc); 370696f2e892SBill Paul error = 0; 370796f2e892SBill Paul break; 370896f2e892SBill Paul case SIOCGIFMEDIA: 370996f2e892SBill Paul case SIOCSIFMEDIA: 371096f2e892SBill Paul mii = device_get_softc(sc->dc_miibus); 371196f2e892SBill Paul error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 371296f2e892SBill Paul break; 3713e695984eSRuslan Ermilov case SIOCSIFCAP: 371440929967SGleb Smirnoff #ifdef DEVICE_POLLING 371540929967SGleb Smirnoff if (ifr->ifr_reqcap & IFCAP_POLLING && 371640929967SGleb Smirnoff !(ifp->if_capenable & IFCAP_POLLING)) { 371740929967SGleb Smirnoff error = ether_poll_register(dc_poll, ifp); 371840929967SGleb Smirnoff if (error) 371940929967SGleb Smirnoff return(error); 3720c8b27acaSJohn Baldwin DC_LOCK(sc); 372140929967SGleb Smirnoff /* Disable interrupts */ 372240929967SGleb Smirnoff CSR_WRITE_4(sc, DC_IMR, 0x00000000); 372340929967SGleb Smirnoff ifp->if_capenable |= IFCAP_POLLING; 3724c8b27acaSJohn Baldwin DC_UNLOCK(sc); 372540929967SGleb Smirnoff return (error); 372640929967SGleb Smirnoff } 372740929967SGleb Smirnoff if (!(ifr->ifr_reqcap & IFCAP_POLLING) && 372840929967SGleb Smirnoff ifp->if_capenable & IFCAP_POLLING) { 372940929967SGleb Smirnoff error = ether_poll_deregister(ifp); 373040929967SGleb Smirnoff /* Enable interrupts. */ 373140929967SGleb Smirnoff DC_LOCK(sc); 373240929967SGleb Smirnoff CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 373340929967SGleb Smirnoff ifp->if_capenable &= ~IFCAP_POLLING; 373440929967SGleb Smirnoff DC_UNLOCK(sc); 373540929967SGleb Smirnoff return (error); 373640929967SGleb Smirnoff } 373740929967SGleb Smirnoff #endif /* DEVICE_POLLING */ 3738e695984eSRuslan Ermilov break; 373996f2e892SBill Paul default: 37409ef8b520SSam Leffler error = ether_ioctl(ifp, command, data); 374196f2e892SBill Paul break; 374296f2e892SBill Paul } 374396f2e892SBill Paul 374496f2e892SBill Paul return (error); 374596f2e892SBill Paul } 374696f2e892SBill Paul 3747e3d2833aSAlfred Perlstein static void 3748b1d16143SMarius Strobl dc_watchdog(void *xsc) 374996f2e892SBill Paul { 3750b1d16143SMarius Strobl struct dc_softc *sc = xsc; 3751b1d16143SMarius Strobl struct ifnet *ifp; 375296f2e892SBill Paul 3753b1d16143SMarius Strobl DC_LOCK_ASSERT(sc); 375496f2e892SBill Paul 3755b1d16143SMarius Strobl if (sc->dc_wdog_timer == 0 || --sc->dc_wdog_timer != 0) { 3756b1d16143SMarius Strobl callout_reset(&sc->dc_wdog_ch, hz, dc_watchdog, sc); 3757b1d16143SMarius Strobl return; 3758b1d16143SMarius Strobl } 3759d1ce9105SBill Paul 3760b1d16143SMarius Strobl ifp = sc->dc_ifp; 376196f2e892SBill Paul ifp->if_oerrors++; 3762b1d16143SMarius Strobl device_printf(sc->dc_dev, "watchdog timeout\n"); 376396f2e892SBill Paul 376496f2e892SBill Paul dc_stop(sc); 376596f2e892SBill Paul dc_reset(sc); 3766c8b27acaSJohn Baldwin dc_init_locked(sc); 376796f2e892SBill Paul 3768cbaf877fSBrian Feldman if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3769c8b27acaSJohn Baldwin dc_start_locked(ifp); 377096f2e892SBill Paul } 377196f2e892SBill Paul 377296f2e892SBill Paul /* 377396f2e892SBill Paul * Stop the adapter and free any mbufs allocated to the 377496f2e892SBill Paul * RX and TX lists. 377596f2e892SBill Paul */ 3776e3d2833aSAlfred Perlstein static void 37770934f18aSMaxime Henrion dc_stop(struct dc_softc *sc) 377896f2e892SBill Paul { 377996f2e892SBill Paul struct ifnet *ifp; 3780b3811c95SMaxime Henrion struct dc_list_data *ld; 3781b3811c95SMaxime Henrion struct dc_chain_data *cd; 3782b3811c95SMaxime Henrion int i; 3783af4358c7SMaxime Henrion u_int32_t ctl; 378496f2e892SBill Paul 3785c8b27acaSJohn Baldwin DC_LOCK_ASSERT(sc); 3786d1ce9105SBill Paul 3787fc74a9f9SBrooks Davis ifp = sc->dc_ifp; 3788b3811c95SMaxime Henrion ld = sc->dc_ldata; 3789b3811c95SMaxime Henrion cd = &sc->dc_cdata; 379096f2e892SBill Paul 3791b50c6312SJonathan Lemon callout_stop(&sc->dc_stat_ch); 3792b1d16143SMarius Strobl callout_stop(&sc->dc_wdog_ch); 3793b1d16143SMarius Strobl sc->dc_wdog_timer = 0; 379496f2e892SBill Paul 379513f4c340SRobert Watson ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 37963b3ec200SPeter Wemm 379796f2e892SBill Paul DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)); 379896f2e892SBill Paul CSR_WRITE_4(sc, DC_IMR, 0x00000000); 379996f2e892SBill Paul CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 380096f2e892SBill Paul CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 380196f2e892SBill Paul sc->dc_link = 0; 380296f2e892SBill Paul 380396f2e892SBill Paul /* 380496f2e892SBill Paul * Free data in the RX lists. 380596f2e892SBill Paul */ 380696f2e892SBill Paul for (i = 0; i < DC_RX_LIST_CNT; i++) { 3807b3811c95SMaxime Henrion if (cd->dc_rx_chain[i] != NULL) { 380856e5e7aeSMaxime Henrion m_freem(cd->dc_rx_chain[i]); 380956e5e7aeSMaxime Henrion cd->dc_rx_chain[i] = NULL; 381096f2e892SBill Paul } 381196f2e892SBill Paul } 3812b3811c95SMaxime Henrion bzero(&ld->dc_rx_list, sizeof(ld->dc_rx_list)); 381396f2e892SBill Paul 381496f2e892SBill Paul /* 381596f2e892SBill Paul * Free the TX list buffers. 381696f2e892SBill Paul */ 381796f2e892SBill Paul for (i = 0; i < DC_TX_LIST_CNT; i++) { 3818b3811c95SMaxime Henrion if (cd->dc_tx_chain[i] != NULL) { 3819af4358c7SMaxime Henrion ctl = le32toh(ld->dc_tx_list[i].dc_ctl); 3820af4358c7SMaxime Henrion if ((ctl & DC_TXCTL_SETUP) || 38214ff4a9beSDon Lewis !(ctl & DC_TXCTL_LASTFRAG)) { 3822b3811c95SMaxime Henrion cd->dc_tx_chain[i] = NULL; 382396f2e892SBill Paul continue; 382496f2e892SBill Paul } 382556e5e7aeSMaxime Henrion bus_dmamap_unload(sc->dc_mtag, cd->dc_tx_map[i]); 382656e5e7aeSMaxime Henrion m_freem(cd->dc_tx_chain[i]); 3827b3811c95SMaxime Henrion cd->dc_tx_chain[i] = NULL; 382896f2e892SBill Paul } 382996f2e892SBill Paul } 3830b3811c95SMaxime Henrion bzero(&ld->dc_tx_list, sizeof(ld->dc_tx_list)); 383196f2e892SBill Paul } 383296f2e892SBill Paul 383396f2e892SBill Paul /* 3834e8388e14SMitsuru IWASAKI * Device suspend routine. Stop the interface and save some PCI 3835e8388e14SMitsuru IWASAKI * settings in case the BIOS doesn't restore them properly on 3836e8388e14SMitsuru IWASAKI * resume. 3837e8388e14SMitsuru IWASAKI */ 3838e3d2833aSAlfred Perlstein static int 38390934f18aSMaxime Henrion dc_suspend(device_t dev) 3840e8388e14SMitsuru IWASAKI { 3841e8388e14SMitsuru IWASAKI struct dc_softc *sc; 3842e8388e14SMitsuru IWASAKI 3843e8388e14SMitsuru IWASAKI sc = device_get_softc(dev); 3844c8b27acaSJohn Baldwin DC_LOCK(sc); 3845e8388e14SMitsuru IWASAKI dc_stop(sc); 3846e8388e14SMitsuru IWASAKI sc->suspended = 1; 3847c8b27acaSJohn Baldwin DC_UNLOCK(sc); 3848e8388e14SMitsuru IWASAKI 3849e8388e14SMitsuru IWASAKI return (0); 3850e8388e14SMitsuru IWASAKI } 3851e8388e14SMitsuru IWASAKI 3852e8388e14SMitsuru IWASAKI /* 3853e8388e14SMitsuru IWASAKI * Device resume routine. Restore some PCI settings in case the BIOS 3854e8388e14SMitsuru IWASAKI * doesn't, re-enable busmastering, and restart the interface if 3855e8388e14SMitsuru IWASAKI * appropriate. 3856e8388e14SMitsuru IWASAKI */ 3857e3d2833aSAlfred Perlstein static int 38580934f18aSMaxime Henrion dc_resume(device_t dev) 3859e8388e14SMitsuru IWASAKI { 3860e8388e14SMitsuru IWASAKI struct dc_softc *sc; 3861e8388e14SMitsuru IWASAKI struct ifnet *ifp; 3862e8388e14SMitsuru IWASAKI 3863e8388e14SMitsuru IWASAKI sc = device_get_softc(dev); 3864fc74a9f9SBrooks Davis ifp = sc->dc_ifp; 3865e8388e14SMitsuru IWASAKI 3866e8388e14SMitsuru IWASAKI /* reinitialize interface if necessary */ 3867c8b27acaSJohn Baldwin DC_LOCK(sc); 3868e8388e14SMitsuru IWASAKI if (ifp->if_flags & IFF_UP) 3869c8b27acaSJohn Baldwin dc_init_locked(sc); 3870e8388e14SMitsuru IWASAKI 3871e8388e14SMitsuru IWASAKI sc->suspended = 0; 3872c8b27acaSJohn Baldwin DC_UNLOCK(sc); 3873e8388e14SMitsuru IWASAKI 3874e8388e14SMitsuru IWASAKI return (0); 3875e8388e14SMitsuru IWASAKI } 3876e8388e14SMitsuru IWASAKI 3877e8388e14SMitsuru IWASAKI /* 387896f2e892SBill Paul * Stop all chip I/O so that the kernel's probe routines don't 387996f2e892SBill Paul * get confused by errant DMAs when rebooting. 388096f2e892SBill Paul */ 38816a087a87SPyun YongHyeon static int 38820934f18aSMaxime Henrion dc_shutdown(device_t dev) 388396f2e892SBill Paul { 388496f2e892SBill Paul struct dc_softc *sc; 388596f2e892SBill Paul 388696f2e892SBill Paul sc = device_get_softc(dev); 388796f2e892SBill Paul 3888c8b27acaSJohn Baldwin DC_LOCK(sc); 388996f2e892SBill Paul dc_stop(sc); 3890c8b27acaSJohn Baldwin DC_UNLOCK(sc); 38916a087a87SPyun YongHyeon 38926a087a87SPyun YongHyeon return (0); 389396f2e892SBill Paul } 389439d76ed6SPyun YongHyeon 389539d76ed6SPyun YongHyeon static int 389639d76ed6SPyun YongHyeon dc_check_multiport(struct dc_softc *sc) 389739d76ed6SPyun YongHyeon { 389839d76ed6SPyun YongHyeon struct dc_softc *dsc; 389939d76ed6SPyun YongHyeon devclass_t dc; 390039d76ed6SPyun YongHyeon device_t child; 390139d76ed6SPyun YongHyeon uint8_t *eaddr; 390239d76ed6SPyun YongHyeon int unit; 390339d76ed6SPyun YongHyeon 390439d76ed6SPyun YongHyeon dc = devclass_find("dc"); 390539d76ed6SPyun YongHyeon for (unit = 0; unit < devclass_get_maxunit(dc); unit++) { 390639d76ed6SPyun YongHyeon child = devclass_get_device(dc, unit); 390739d76ed6SPyun YongHyeon if (child == NULL) 390839d76ed6SPyun YongHyeon continue; 390939d76ed6SPyun YongHyeon if (child == sc->dc_dev) 391039d76ed6SPyun YongHyeon continue; 391139d76ed6SPyun YongHyeon if (device_get_parent(child) != device_get_parent(sc->dc_dev)) 391239d76ed6SPyun YongHyeon continue; 391339d76ed6SPyun YongHyeon if (unit > device_get_unit(sc->dc_dev)) 391439d76ed6SPyun YongHyeon continue; 3915b289c607SPyun YongHyeon if (device_is_attached(child) == 0) 3916b289c607SPyun YongHyeon continue; 391739d76ed6SPyun YongHyeon dsc = device_get_softc(child); 3918b289c607SPyun YongHyeon device_printf(sc->dc_dev, 3919b289c607SPyun YongHyeon "Using station address of %s as base\n", 392039d76ed6SPyun YongHyeon device_get_nameunit(child)); 392139d76ed6SPyun YongHyeon bcopy(dsc->dc_eaddr, sc->dc_eaddr, ETHER_ADDR_LEN); 392239d76ed6SPyun YongHyeon eaddr = (uint8_t *)sc->dc_eaddr; 392339d76ed6SPyun YongHyeon eaddr[5]++; 3924b289c607SPyun YongHyeon /* Prepare SROM to parse again. */ 3925b289c607SPyun YongHyeon if (DC_IS_INTEL(sc) && dsc->dc_srom != NULL && 3926b289c607SPyun YongHyeon sc->dc_romwidth != 0) { 3927b289c607SPyun YongHyeon free(sc->dc_srom, M_DEVBUF); 3928b289c607SPyun YongHyeon sc->dc_romwidth = dsc->dc_romwidth; 3929b289c607SPyun YongHyeon sc->dc_srom = malloc(DC_ROM_SIZE(sc->dc_romwidth), 3930b289c607SPyun YongHyeon M_DEVBUF, M_NOWAIT); 3931b289c607SPyun YongHyeon if (sc->dc_srom == NULL) { 3932b289c607SPyun YongHyeon device_printf(sc->dc_dev, 3933b289c607SPyun YongHyeon "Could not allocate SROM buffer\n"); 3934b289c607SPyun YongHyeon return (ENOMEM); 3935b289c607SPyun YongHyeon } 3936b289c607SPyun YongHyeon bcopy(dsc->dc_srom, sc->dc_srom, 3937b289c607SPyun YongHyeon DC_ROM_SIZE(sc->dc_romwidth)); 3938b289c607SPyun YongHyeon } 393939d76ed6SPyun YongHyeon return (0); 394039d76ed6SPyun YongHyeon } 394139d76ed6SPyun YongHyeon return (ENOENT); 394239d76ed6SPyun YongHyeon } 3943