1 /*- 2 * Copyright (c) 2016 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: John Baldwin <jhb@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/conf.h> 37 #include <sys/kernel.h> 38 #include <sys/module.h> 39 #include <sys/priv.h> 40 #include <dev/pci/pcivar.h> 41 #if defined(__i386__) || defined(__amd64__) 42 #include <vm/vm.h> 43 #include <vm/pmap.h> 44 #endif 45 46 #include "common/common.h" 47 #include "common/t4_regs.h" 48 #include "t4_ioctl.h" 49 #include "t4_mp_ring.h" 50 51 /* 52 * Some notes: 53 * 54 * The Virtual Interfaces are connected to an internal switch on the chip 55 * which allows VIs attached to the same port to talk to each other even when 56 * the port link is down. As a result, we might want to always report a 57 * VF's link as being "up". 58 * 59 * XXX: Add a TUNABLE and possible per-device sysctl for this? 60 */ 61 62 struct intrs_and_queues { 63 uint16_t intr_type; /* MSI, or MSI-X */ 64 uint16_t nirq; /* Total # of vectors */ 65 uint16_t ntxq; /* # of NIC txq's for each port */ 66 uint16_t nrxq; /* # of NIC rxq's for each port */ 67 }; 68 69 struct { 70 uint16_t device; 71 char *desc; 72 } t4vf_pciids[] = { 73 {0x4800, "Chelsio T440-dbg VF"}, 74 {0x4801, "Chelsio T420-CR VF"}, 75 {0x4802, "Chelsio T422-CR VF"}, 76 {0x4803, "Chelsio T440-CR VF"}, 77 {0x4804, "Chelsio T420-BCH VF"}, 78 {0x4805, "Chelsio T440-BCH VF"}, 79 {0x4806, "Chelsio T440-CH VF"}, 80 {0x4807, "Chelsio T420-SO VF"}, 81 {0x4808, "Chelsio T420-CX VF"}, 82 {0x4809, "Chelsio T420-BT VF"}, 83 {0x480a, "Chelsio T404-BT VF"}, 84 {0x480e, "Chelsio T440-LP-CR VF"}, 85 }, t5vf_pciids[] = { 86 {0x5800, "Chelsio T580-dbg VF"}, 87 {0x5801, "Chelsio T520-CR VF"}, /* 2 x 10G */ 88 {0x5802, "Chelsio T522-CR VF"}, /* 2 x 10G, 2 X 1G */ 89 {0x5803, "Chelsio T540-CR VF"}, /* 4 x 10G */ 90 {0x5807, "Chelsio T520-SO VF"}, /* 2 x 10G, nomem */ 91 {0x5809, "Chelsio T520-BT VF"}, /* 2 x 10GBaseT */ 92 {0x580a, "Chelsio T504-BT VF"}, /* 4 x 1G */ 93 {0x580d, "Chelsio T580-CR VF"}, /* 2 x 40G */ 94 {0x580e, "Chelsio T540-LP-CR VF"}, /* 4 x 10G */ 95 {0x5810, "Chelsio T580-LP-CR VF"}, /* 2 x 40G */ 96 {0x5811, "Chelsio T520-LL-CR VF"}, /* 2 x 10G */ 97 {0x5812, "Chelsio T560-CR VF"}, /* 1 x 40G, 2 x 10G */ 98 {0x5814, "Chelsio T580-LP-SO-CR VF"}, /* 2 x 40G, nomem */ 99 {0x5815, "Chelsio T502-BT VF"}, /* 2 x 1G */ 100 {0x5818, "Chelsio T540-BT VF"}, /* 4 x 10GBaseT */ 101 {0x5819, "Chelsio T540-LP-BT VF"}, /* 4 x 10GBaseT */ 102 {0x581a, "Chelsio T540-SO-BT VF"}, /* 4 x 10GBaseT, nomem */ 103 {0x581b, "Chelsio T540-SO-CR VF"}, /* 4 x 10G, nomem */ 104 }, t6vf_pciids[] = { 105 {0x6800, "Chelsio T6-DBG-25 VF"}, /* 2 x 10/25G, debug */ 106 {0x6801, "Chelsio T6225-CR VF"}, /* 2 x 10/25G */ 107 {0x6802, "Chelsio T6225-SO-CR VF"}, /* 2 x 10/25G, nomem */ 108 {0x6803, "Chelsio T6425-CR VF"}, /* 4 x 10/25G */ 109 {0x6804, "Chelsio T6425-SO-CR VF"}, /* 4 x 10/25G, nomem */ 110 {0x6805, "Chelsio T6225-OCP-SO VF"}, /* 2 x 10/25G, nomem */ 111 {0x6806, "Chelsio T62100-OCP-SO VF"}, /* 2 x 40/50/100G, nomem */ 112 {0x6807, "Chelsio T62100-LP-CR VF"}, /* 2 x 40/50/100G */ 113 {0x6808, "Chelsio T62100-SO-CR VF"}, /* 2 x 40/50/100G, nomem */ 114 {0x6809, "Chelsio T6210-BT VF"}, /* 2 x 10GBASE-T */ 115 {0x680d, "Chelsio T62100-CR VF"}, /* 2 x 40/50/100G */ 116 {0x6810, "Chelsio T6-DBG-100 VF"}, /* 2 x 40/50/100G, debug */ 117 {0x6811, "Chelsio T6225-LL-CR VF"}, /* 2 x 10/25G */ 118 {0x6814, "Chelsio T61100-OCP-SO VF"}, /* 1 x 40/50/100G, nomem */ 119 {0x6815, "Chelsio T6201-BT VF"}, /* 2 x 1000BASE-T */ 120 121 /* Custom */ 122 {0x6880, "Chelsio T6225 80 VF"}, 123 {0x6881, "Chelsio T62100 81 VF"}, 124 {0x6882, "Chelsio T6225-CR 82 VF"}, 125 {0x6883, "Chelsio T62100-CR 83 VF"}, 126 {0x6884, "Chelsio T64100-CR 84 VF"}, 127 {0x6885, "Chelsio T6240-SO 85 VF"}, 128 {0x6886, "Chelsio T6225-SO-CR 86 VF"}, 129 {0x6887, "Chelsio T6225-CR 87 VF"}, 130 }; 131 132 static d_ioctl_t t4vf_ioctl; 133 134 static struct cdevsw t4vf_cdevsw = { 135 .d_version = D_VERSION, 136 .d_ioctl = t4vf_ioctl, 137 .d_name = "t4vf", 138 }; 139 140 static int 141 t4vf_probe(device_t dev) 142 { 143 uint16_t d; 144 size_t i; 145 146 d = pci_get_device(dev); 147 for (i = 0; i < nitems(t4vf_pciids); i++) { 148 if (d == t4vf_pciids[i].device) { 149 device_set_desc(dev, t4vf_pciids[i].desc); 150 return (BUS_PROBE_DEFAULT); 151 } 152 } 153 return (ENXIO); 154 } 155 156 static int 157 t5vf_probe(device_t dev) 158 { 159 uint16_t d; 160 size_t i; 161 162 d = pci_get_device(dev); 163 for (i = 0; i < nitems(t5vf_pciids); i++) { 164 if (d == t5vf_pciids[i].device) { 165 device_set_desc(dev, t5vf_pciids[i].desc); 166 return (BUS_PROBE_DEFAULT); 167 } 168 } 169 return (ENXIO); 170 } 171 172 static int 173 t6vf_probe(device_t dev) 174 { 175 uint16_t d; 176 size_t i; 177 178 d = pci_get_device(dev); 179 for (i = 0; i < nitems(t6vf_pciids); i++) { 180 if (d == t6vf_pciids[i].device) { 181 device_set_desc(dev, t6vf_pciids[i].desc); 182 return (BUS_PROBE_DEFAULT); 183 } 184 } 185 return (ENXIO); 186 } 187 188 #define FW_PARAM_DEV(param) \ 189 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \ 190 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param)) 191 #define FW_PARAM_PFVF(param) \ 192 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \ 193 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param)) 194 195 static int 196 get_params__pre_init(struct adapter *sc) 197 { 198 int rc; 199 uint32_t param[3], val[3]; 200 201 param[0] = FW_PARAM_DEV(FWREV); 202 param[1] = FW_PARAM_DEV(TPREV); 203 param[2] = FW_PARAM_DEV(CCLK); 204 rc = -t4vf_query_params(sc, nitems(param), param, val); 205 if (rc != 0) { 206 device_printf(sc->dev, 207 "failed to query parameters (pre_init): %d.\n", rc); 208 return (rc); 209 } 210 211 sc->params.fw_vers = val[0]; 212 sc->params.tp_vers = val[1]; 213 sc->params.vpd.cclk = val[2]; 214 215 snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u", 216 G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers), 217 G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers), 218 G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers), 219 G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers)); 220 221 snprintf(sc->tp_version, sizeof(sc->tp_version), "%u.%u.%u.%u", 222 G_FW_HDR_FW_VER_MAJOR(sc->params.tp_vers), 223 G_FW_HDR_FW_VER_MINOR(sc->params.tp_vers), 224 G_FW_HDR_FW_VER_MICRO(sc->params.tp_vers), 225 G_FW_HDR_FW_VER_BUILD(sc->params.tp_vers)); 226 227 return (0); 228 } 229 230 static int 231 get_params__post_init(struct adapter *sc) 232 { 233 int rc; 234 uint32_t param, val; 235 236 rc = -t4vf_get_sge_params(sc); 237 if (rc != 0) { 238 device_printf(sc->dev, 239 "unable to retrieve adapter SGE parameters: %d\n", rc); 240 return (rc); 241 } 242 243 rc = -t4vf_get_rss_glb_config(sc); 244 if (rc != 0) { 245 device_printf(sc->dev, 246 "unable to retrieve adapter RSS parameters: %d\n", rc); 247 return (rc); 248 } 249 if (sc->params.rss.mode != FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) { 250 device_printf(sc->dev, 251 "unable to operate with global RSS mode %d\n", 252 sc->params.rss.mode); 253 return (EINVAL); 254 } 255 256 rc = t4_read_chip_settings(sc); 257 if (rc != 0) 258 return (rc); 259 260 /* 261 * Grab our Virtual Interface resource allocation, extract the 262 * features that we're interested in and do a bit of sanity testing on 263 * what we discover. 264 */ 265 rc = -t4vf_get_vfres(sc); 266 if (rc != 0) { 267 device_printf(sc->dev, 268 "unable to get virtual interface resources: %d\n", rc); 269 return (rc); 270 } 271 272 /* 273 * Check for various parameter sanity issues. 274 */ 275 if (sc->params.vfres.pmask == 0) { 276 device_printf(sc->dev, "no port access configured/usable!\n"); 277 return (EINVAL); 278 } 279 if (sc->params.vfres.nvi == 0) { 280 device_printf(sc->dev, 281 "no virtual interfaces configured/usable!\n"); 282 return (EINVAL); 283 } 284 sc->params.portvec = sc->params.vfres.pmask; 285 286 param = FW_PARAM_PFVF(MAX_PKTS_PER_ETH_TX_PKTS_WR); 287 rc = -t4vf_query_params(sc, 1, ¶m, &val); 288 if (rc == 0) 289 sc->params.max_pkts_per_eth_tx_pkts_wr = val; 290 else 291 sc->params.max_pkts_per_eth_tx_pkts_wr = 14; 292 293 return (0); 294 } 295 296 static int 297 set_params__post_init(struct adapter *sc) 298 { 299 uint32_t param, val; 300 301 /* ask for encapsulated CPLs */ 302 param = FW_PARAM_PFVF(CPLFW4MSG_ENCAP); 303 val = 1; 304 (void)t4vf_set_params(sc, 1, ¶m, &val); 305 306 /* Enable 32b port caps if the firmware supports it. */ 307 param = FW_PARAM_PFVF(PORT_CAPS32); 308 val = 1; 309 if (t4vf_set_params(sc, 1, ¶m, &val) == 0) 310 sc->params.port_caps32 = 1; 311 312 return (0); 313 } 314 315 #undef FW_PARAM_PFVF 316 #undef FW_PARAM_DEV 317 318 static int 319 cfg_itype_and_nqueues(struct adapter *sc, struct intrs_and_queues *iaq) 320 { 321 struct vf_resources *vfres; 322 int nrxq, ntxq, nports; 323 int itype, iq_avail, navail, rc; 324 325 /* 326 * Figure out the layout of queues across our VIs and ensure 327 * we can allocate enough interrupts for our layout. 328 */ 329 vfres = &sc->params.vfres; 330 nports = sc->params.nports; 331 bzero(iaq, sizeof(*iaq)); 332 333 for (itype = INTR_MSIX; itype != 0; itype >>= 1) { 334 if (itype == INTR_INTX) 335 continue; 336 337 if (itype == INTR_MSIX) 338 navail = pci_msix_count(sc->dev); 339 else 340 navail = pci_msi_count(sc->dev); 341 342 if (navail == 0) 343 continue; 344 345 iaq->intr_type = itype; 346 347 /* 348 * XXX: The Linux driver reserves an Ingress Queue for 349 * forwarded interrupts when using MSI (but not MSI-X). 350 * It seems it just always asks for 2 interrupts and 351 * forwards all rxqs to the forwarded interrupt. 352 * 353 * We must reserve one IRQ for the for the firmware 354 * event queue. 355 * 356 * Every rxq requires an ingress queue with a free 357 * list and interrupts and an egress queue. Every txq 358 * requires an ETH egress queue. 359 */ 360 iaq->nirq = T4VF_EXTRA_INTR; 361 362 /* 363 * First, determine how many queues we can allocate. 364 * Start by finding the upper bound on rxqs from the 365 * limit on ingress queues. 366 */ 367 iq_avail = vfres->niqflint - iaq->nirq; 368 if (iq_avail < nports) { 369 device_printf(sc->dev, 370 "Not enough ingress queues (%d) for %d ports\n", 371 vfres->niqflint, nports); 372 return (ENXIO); 373 } 374 375 /* 376 * Try to honor the cap on interrupts. If there aren't 377 * enough interrupts for at least one interrupt per 378 * port, then don't bother, we will just forward all 379 * interrupts to one interrupt in that case. 380 */ 381 if (iaq->nirq + nports <= navail) { 382 if (iq_avail > navail - iaq->nirq) 383 iq_avail = navail - iaq->nirq; 384 } 385 386 nrxq = nports * t4_nrxq; 387 if (nrxq > iq_avail) { 388 /* 389 * Too many ingress queues. Use what we can. 390 */ 391 nrxq = (iq_avail / nports) * nports; 392 } 393 KASSERT(nrxq <= iq_avail, ("too many ingress queues")); 394 395 /* 396 * Next, determine the upper bound on txqs from the limit 397 * on ETH queues. 398 */ 399 if (vfres->nethctrl < nports) { 400 device_printf(sc->dev, 401 "Not enough ETH queues (%d) for %d ports\n", 402 vfres->nethctrl, nports); 403 return (ENXIO); 404 } 405 406 ntxq = nports * t4_ntxq; 407 if (ntxq > vfres->nethctrl) { 408 /* 409 * Too many ETH queues. Use what we can. 410 */ 411 ntxq = (vfres->nethctrl / nports) * nports; 412 } 413 KASSERT(ntxq <= vfres->nethctrl, ("too many ETH queues")); 414 415 /* 416 * Finally, ensure we have enough egress queues. 417 */ 418 if (vfres->neq < nports * 2) { 419 device_printf(sc->dev, 420 "Not enough egress queues (%d) for %d ports\n", 421 vfres->neq, nports); 422 return (ENXIO); 423 } 424 if (nrxq + ntxq > vfres->neq) { 425 /* Just punt and use 1 for everything. */ 426 nrxq = ntxq = nports; 427 } 428 KASSERT(nrxq <= iq_avail, ("too many ingress queues")); 429 KASSERT(ntxq <= vfres->nethctrl, ("too many ETH queues")); 430 KASSERT(nrxq + ntxq <= vfres->neq, ("too many egress queues")); 431 432 /* 433 * Do we have enough interrupts? For MSI the interrupts 434 * have to be a power of 2 as well. 435 */ 436 iaq->nirq += nrxq; 437 iaq->ntxq = ntxq; 438 iaq->nrxq = nrxq; 439 if (iaq->nirq <= navail && 440 (itype != INTR_MSI || powerof2(iaq->nirq))) { 441 navail = iaq->nirq; 442 if (itype == INTR_MSIX) 443 rc = pci_alloc_msix(sc->dev, &navail); 444 else 445 rc = pci_alloc_msi(sc->dev, &navail); 446 if (rc != 0) { 447 device_printf(sc->dev, 448 "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n", 449 itype, rc, iaq->nirq, navail); 450 return (rc); 451 } 452 if (navail == iaq->nirq) { 453 return (0); 454 } 455 pci_release_msi(sc->dev); 456 } 457 458 /* Fall back to a single interrupt. */ 459 iaq->nirq = 1; 460 navail = iaq->nirq; 461 if (itype == INTR_MSIX) 462 rc = pci_alloc_msix(sc->dev, &navail); 463 else 464 rc = pci_alloc_msi(sc->dev, &navail); 465 if (rc != 0) 466 device_printf(sc->dev, 467 "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n", 468 itype, rc, iaq->nirq, navail); 469 return (rc); 470 } 471 472 device_printf(sc->dev, 473 "failed to find a usable interrupt type. " 474 "allowed=%d, msi-x=%d, msi=%d, intx=1", t4_intr_types, 475 pci_msix_count(sc->dev), pci_msi_count(sc->dev)); 476 477 return (ENXIO); 478 } 479 480 static int 481 t4vf_attach(device_t dev) 482 { 483 struct adapter *sc; 484 int rc = 0, i, j, rqidx, tqidx, n, p, pmask; 485 struct make_dev_args mda; 486 struct intrs_and_queues iaq; 487 struct sge *s; 488 489 sc = device_get_softc(dev); 490 sc->dev = dev; 491 pci_enable_busmaster(dev); 492 pci_set_max_read_req(dev, 4096); 493 sc->params.pci.mps = pci_get_max_payload(dev); 494 495 sc->flags |= IS_VF; 496 TUNABLE_INT_FETCH("hw.cxgbe.dflags", &sc->debug_flags); 497 498 sc->sge_gts_reg = VF_SGE_REG(A_SGE_VF_GTS); 499 sc->sge_kdoorbell_reg = VF_SGE_REG(A_SGE_VF_KDOORBELL); 500 snprintf(sc->lockname, sizeof(sc->lockname), "%s", 501 device_get_nameunit(dev)); 502 mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF); 503 t4_add_adapter(sc); 504 505 mtx_init(&sc->sfl_lock, "starving freelists", 0, MTX_DEF); 506 TAILQ_INIT(&sc->sfl); 507 callout_init_mtx(&sc->sfl_callout, &sc->sfl_lock, 0); 508 509 mtx_init(&sc->reg_lock, "indirect register access", 0, MTX_DEF); 510 511 rc = t4_map_bars_0_and_4(sc); 512 if (rc != 0) 513 goto done; /* error message displayed already */ 514 515 rc = -t4vf_prep_adapter(sc); 516 if (rc != 0) 517 goto done; 518 519 t4_init_devnames(sc); 520 if (sc->names == NULL) { 521 rc = ENOTSUP; 522 goto done; /* error message displayed already */ 523 } 524 525 /* 526 * Leave the 'pf' and 'mbox' values as zero. This ensures 527 * that various firmware messages do not set the fields which 528 * is the correct thing to do for a VF. 529 */ 530 531 memset(sc->chan_map, 0xff, sizeof(sc->chan_map)); 532 533 make_dev_args_init(&mda); 534 mda.mda_devsw = &t4vf_cdevsw; 535 mda.mda_uid = UID_ROOT; 536 mda.mda_gid = GID_WHEEL; 537 mda.mda_mode = 0600; 538 mda.mda_si_drv1 = sc; 539 rc = make_dev_s(&mda, &sc->cdev, "%s", device_get_nameunit(dev)); 540 if (rc != 0) 541 device_printf(dev, "failed to create nexus char device: %d.\n", 542 rc); 543 544 #if defined(__i386__) 545 if ((cpu_feature & CPUID_CX8) == 0) { 546 device_printf(dev, "64 bit atomics not available.\n"); 547 rc = ENOTSUP; 548 goto done; 549 } 550 #endif 551 552 /* 553 * Some environments do not properly handle PCIE FLRs -- e.g. in Linux 554 * 2.6.31 and later we can't call pci_reset_function() in order to 555 * issue an FLR because of a self- deadlock on the device semaphore. 556 * Meanwhile, the OS infrastructure doesn't issue FLRs in all the 557 * cases where they're needed -- for instance, some versions of KVM 558 * fail to reset "Assigned Devices" when the VM reboots. Therefore we 559 * use the firmware based reset in order to reset any per function 560 * state. 561 */ 562 rc = -t4vf_fw_reset(sc); 563 if (rc != 0) { 564 device_printf(dev, "FW reset failed: %d\n", rc); 565 goto done; 566 } 567 sc->flags |= FW_OK; 568 569 /* 570 * Grab basic operational parameters. These will predominantly have 571 * been set up by the Physical Function Driver or will be hard coded 572 * into the adapter. We just have to live with them ... Note that 573 * we _must_ get our VPD parameters before our SGE parameters because 574 * we need to know the adapter's core clock from the VPD in order to 575 * properly decode the SGE Timer Values. 576 */ 577 rc = get_params__pre_init(sc); 578 if (rc != 0) 579 goto done; /* error message displayed already */ 580 rc = get_params__post_init(sc); 581 if (rc != 0) 582 goto done; /* error message displayed already */ 583 584 rc = set_params__post_init(sc); 585 if (rc != 0) 586 goto done; /* error message displayed already */ 587 588 rc = t4_map_bar_2(sc); 589 if (rc != 0) 590 goto done; /* error message displayed already */ 591 592 rc = t4_create_dma_tag(sc); 593 if (rc != 0) 594 goto done; /* error message displayed already */ 595 596 /* 597 * The number of "ports" which we support is equal to the number of 598 * Virtual Interfaces with which we've been provisioned. 599 */ 600 sc->params.nports = imin(sc->params.vfres.nvi, MAX_NPORTS); 601 602 /* 603 * We may have been provisioned with more VIs than the number of 604 * ports we're allowed to access (our Port Access Rights Mask). 605 * Just use a single VI for each port. 606 */ 607 sc->params.nports = imin(sc->params.nports, 608 bitcount32(sc->params.vfres.pmask)); 609 610 #ifdef notyet 611 /* 612 * XXX: The Linux VF driver will lower nports if it thinks there 613 * are too few resources in vfres (niqflint, nethctrl, neq). 614 */ 615 #endif 616 617 /* 618 * First pass over all the ports - allocate VIs and initialize some 619 * basic parameters like mac address, port type, etc. 620 */ 621 pmask = sc->params.vfres.pmask; 622 for_each_port(sc, i) { 623 struct port_info *pi; 624 uint8_t mac[ETHER_ADDR_LEN]; 625 626 pi = malloc(sizeof(*pi), M_CXGBE, M_ZERO | M_WAITOK); 627 sc->port[i] = pi; 628 629 /* These must be set before t4_port_init */ 630 pi->adapter = sc; 631 pi->port_id = i; 632 pi->nvi = 1; 633 pi->vi = malloc(sizeof(struct vi_info) * pi->nvi, M_CXGBE, 634 M_ZERO | M_WAITOK); 635 636 /* 637 * Allocate the "main" VI and initialize parameters 638 * like mac addr. 639 */ 640 rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i); 641 if (rc != 0) { 642 device_printf(dev, "unable to initialize port %d: %d\n", 643 i, rc); 644 free(pi->vi, M_CXGBE); 645 free(pi, M_CXGBE); 646 sc->port[i] = NULL; 647 goto done; 648 } 649 650 /* Prefer the MAC address set by the PF, if there is one. */ 651 n = 1; 652 p = ffs(pmask) - 1; 653 MPASS(p >= 0); 654 rc = t4vf_get_vf_mac(sc, p, &n, mac); 655 if (rc == 0 && n == 1) 656 t4_os_set_hw_addr(pi, mac); 657 pmask &= ~(1 << p); 658 659 /* No t4_link_start. */ 660 661 snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d", 662 device_get_nameunit(dev), i); 663 mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF); 664 sc->chan_map[pi->tx_chan] = i; 665 666 /* All VIs on this port share this media. */ 667 ifmedia_init(&pi->media, IFM_IMASK, cxgbe_media_change, 668 cxgbe_media_status); 669 670 pi->dev = device_add_child(dev, sc->names->vf_ifnet_name, -1); 671 if (pi->dev == NULL) { 672 device_printf(dev, 673 "failed to add device for port %d.\n", i); 674 rc = ENXIO; 675 goto done; 676 } 677 pi->vi[0].dev = pi->dev; 678 device_set_softc(pi->dev, pi); 679 } 680 681 /* 682 * Interrupt type, # of interrupts, # of rx/tx queues, etc. 683 */ 684 rc = cfg_itype_and_nqueues(sc, &iaq); 685 if (rc != 0) 686 goto done; /* error message displayed already */ 687 688 sc->intr_type = iaq.intr_type; 689 sc->intr_count = iaq.nirq; 690 691 s = &sc->sge; 692 s->nrxq = sc->params.nports * iaq.nrxq; 693 s->ntxq = sc->params.nports * iaq.ntxq; 694 s->neq = s->ntxq + s->nrxq; /* the free list in an rxq is an eq */ 695 s->neq += sc->params.nports; /* ctrl queues: 1 per port */ 696 s->niq = s->nrxq + 1; /* 1 extra for firmware event queue */ 697 698 s->iqmap_sz = s->niq; 699 s->eqmap_sz = s->neq; 700 701 s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE, 702 M_ZERO | M_WAITOK); 703 s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE, 704 M_ZERO | M_WAITOK); 705 s->iqmap = malloc(s->iqmap_sz * sizeof(struct sge_iq *), M_CXGBE, 706 M_ZERO | M_WAITOK); 707 s->eqmap = malloc(s->eqmap_sz * sizeof(struct sge_eq *), M_CXGBE, 708 M_ZERO | M_WAITOK); 709 710 sc->irq = malloc(sc->intr_count * sizeof(struct irq), M_CXGBE, 711 M_ZERO | M_WAITOK); 712 713 /* 714 * Second pass over the ports. This time we know the number of rx and 715 * tx queues that each port should get. 716 */ 717 rqidx = tqidx = 0; 718 for_each_port(sc, i) { 719 struct port_info *pi = sc->port[i]; 720 struct vi_info *vi; 721 722 if (pi == NULL) 723 continue; 724 725 for_each_vi(pi, j, vi) { 726 vi->pi = pi; 727 vi->adapter = sc; 728 vi->qsize_rxq = t4_qsize_rxq; 729 vi->qsize_txq = t4_qsize_txq; 730 731 vi->first_rxq = rqidx; 732 vi->first_txq = tqidx; 733 vi->tmr_idx = t4_tmr_idx; 734 vi->pktc_idx = t4_pktc_idx; 735 vi->nrxq = j == 0 ? iaq.nrxq: 1; 736 vi->ntxq = j == 0 ? iaq.ntxq: 1; 737 738 rqidx += vi->nrxq; 739 tqidx += vi->ntxq; 740 741 vi->rsrv_noflowq = 0; 742 } 743 } 744 745 rc = t4_setup_intr_handlers(sc); 746 if (rc != 0) { 747 device_printf(dev, 748 "failed to setup interrupt handlers: %d\n", rc); 749 goto done; 750 } 751 752 rc = bus_generic_attach(dev); 753 if (rc != 0) { 754 device_printf(dev, 755 "failed to attach all child ports: %d\n", rc); 756 goto done; 757 } 758 759 device_printf(dev, 760 "%d ports, %d %s interrupt%s, %d eq, %d iq\n", 761 sc->params.nports, sc->intr_count, sc->intr_type == INTR_MSIX ? 762 "MSI-X" : "MSI", sc->intr_count > 1 ? "s" : "", sc->sge.neq, 763 sc->sge.niq); 764 765 done: 766 if (rc != 0) 767 t4_detach_common(dev); 768 else 769 t4_sysctls(sc); 770 771 return (rc); 772 } 773 774 static void 775 get_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf) 776 { 777 778 /* 0x3f is used as the revision for VFs. */ 779 regs->version = chip_id(sc) | (0x3f << 10); 780 t4_get_regs(sc, buf, regs->len); 781 } 782 783 static void 784 t4_clr_vi_stats(struct adapter *sc) 785 { 786 int reg; 787 788 for (reg = A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L; 789 reg <= A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H; reg += 4) 790 t4_write_reg(sc, VF_MPS_REG(reg), 0); 791 } 792 793 static int 794 t4vf_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag, 795 struct thread *td) 796 { 797 int rc; 798 struct adapter *sc = dev->si_drv1; 799 800 rc = priv_check(td, PRIV_DRIVER); 801 if (rc != 0) 802 return (rc); 803 804 switch (cmd) { 805 case CHELSIO_T4_GETREG: { 806 struct t4_reg *edata = (struct t4_reg *)data; 807 808 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 809 return (EFAULT); 810 811 if (edata->size == 4) 812 edata->val = t4_read_reg(sc, edata->addr); 813 else if (edata->size == 8) 814 edata->val = t4_read_reg64(sc, edata->addr); 815 else 816 return (EINVAL); 817 818 break; 819 } 820 case CHELSIO_T4_SETREG: { 821 struct t4_reg *edata = (struct t4_reg *)data; 822 823 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 824 return (EFAULT); 825 826 if (edata->size == 4) { 827 if (edata->val & 0xffffffff00000000) 828 return (EINVAL); 829 t4_write_reg(sc, edata->addr, (uint32_t) edata->val); 830 } else if (edata->size == 8) 831 t4_write_reg64(sc, edata->addr, edata->val); 832 else 833 return (EINVAL); 834 break; 835 } 836 case CHELSIO_T4_REGDUMP: { 837 struct t4_regdump *regs = (struct t4_regdump *)data; 838 int reglen = t4_get_regs_len(sc); 839 uint8_t *buf; 840 841 if (regs->len < reglen) { 842 regs->len = reglen; /* hint to the caller */ 843 return (ENOBUFS); 844 } 845 846 regs->len = reglen; 847 buf = malloc(reglen, M_CXGBE, M_WAITOK | M_ZERO); 848 get_regs(sc, regs, buf); 849 rc = copyout(buf, regs->data, reglen); 850 free(buf, M_CXGBE); 851 break; 852 } 853 case CHELSIO_T4_CLEAR_STATS: { 854 int i, v; 855 u_int port_id = *(uint32_t *)data; 856 struct port_info *pi; 857 struct vi_info *vi; 858 859 if (port_id >= sc->params.nports) 860 return (EINVAL); 861 pi = sc->port[port_id]; 862 863 /* MAC stats */ 864 pi->tx_parse_error = 0; 865 t4_clr_vi_stats(sc); 866 867 /* 868 * Since this command accepts a port, clear stats for 869 * all VIs on this port. 870 */ 871 for_each_vi(pi, v, vi) { 872 if (vi->flags & VI_INIT_DONE) { 873 struct sge_rxq *rxq; 874 struct sge_txq *txq; 875 876 for_each_rxq(vi, i, rxq) { 877 #if defined(INET) || defined(INET6) 878 rxq->lro.lro_queued = 0; 879 rxq->lro.lro_flushed = 0; 880 #endif 881 rxq->rxcsum = 0; 882 rxq->vlan_extraction = 0; 883 } 884 885 for_each_txq(vi, i, txq) { 886 txq->txcsum = 0; 887 txq->tso_wrs = 0; 888 txq->vlan_insertion = 0; 889 txq->imm_wrs = 0; 890 txq->sgl_wrs = 0; 891 txq->txpkt_wrs = 0; 892 txq->txpkts0_wrs = 0; 893 txq->txpkts1_wrs = 0; 894 txq->txpkts0_pkts = 0; 895 txq->txpkts1_pkts = 0; 896 mp_ring_reset_stats(txq->r); 897 } 898 } 899 } 900 break; 901 } 902 case CHELSIO_T4_SCHED_CLASS: 903 rc = t4_set_sched_class(sc, (struct t4_sched_params *)data); 904 break; 905 case CHELSIO_T4_SCHED_QUEUE: 906 rc = t4_set_sched_queue(sc, (struct t4_sched_queue *)data); 907 break; 908 default: 909 rc = ENOTTY; 910 } 911 912 return (rc); 913 } 914 915 static device_method_t t4vf_methods[] = { 916 DEVMETHOD(device_probe, t4vf_probe), 917 DEVMETHOD(device_attach, t4vf_attach), 918 DEVMETHOD(device_detach, t4_detach_common), 919 920 DEVMETHOD_END 921 }; 922 923 static driver_t t4vf_driver = { 924 "t4vf", 925 t4vf_methods, 926 sizeof(struct adapter) 927 }; 928 929 static device_method_t t5vf_methods[] = { 930 DEVMETHOD(device_probe, t5vf_probe), 931 DEVMETHOD(device_attach, t4vf_attach), 932 DEVMETHOD(device_detach, t4_detach_common), 933 934 DEVMETHOD_END 935 }; 936 937 static driver_t t5vf_driver = { 938 "t5vf", 939 t5vf_methods, 940 sizeof(struct adapter) 941 }; 942 943 static device_method_t t6vf_methods[] = { 944 DEVMETHOD(device_probe, t6vf_probe), 945 DEVMETHOD(device_attach, t4vf_attach), 946 DEVMETHOD(device_detach, t4_detach_common), 947 948 DEVMETHOD_END 949 }; 950 951 static driver_t t6vf_driver = { 952 "t6vf", 953 t6vf_methods, 954 sizeof(struct adapter) 955 }; 956 957 static driver_t cxgbev_driver = { 958 "cxgbev", 959 cxgbe_methods, 960 sizeof(struct port_info) 961 }; 962 963 static driver_t cxlv_driver = { 964 "cxlv", 965 cxgbe_methods, 966 sizeof(struct port_info) 967 }; 968 969 static driver_t ccv_driver = { 970 "ccv", 971 cxgbe_methods, 972 sizeof(struct port_info) 973 }; 974 975 static devclass_t t4vf_devclass, t5vf_devclass, t6vf_devclass; 976 static devclass_t cxgbev_devclass, cxlv_devclass, ccv_devclass; 977 978 DRIVER_MODULE(t4vf, pci, t4vf_driver, t4vf_devclass, 0, 0); 979 MODULE_VERSION(t4vf, 1); 980 MODULE_DEPEND(t4vf, t4nex, 1, 1, 1); 981 982 DRIVER_MODULE(t5vf, pci, t5vf_driver, t5vf_devclass, 0, 0); 983 MODULE_VERSION(t5vf, 1); 984 MODULE_DEPEND(t5vf, t5nex, 1, 1, 1); 985 986 DRIVER_MODULE(t6vf, pci, t6vf_driver, t6vf_devclass, 0, 0); 987 MODULE_VERSION(t6vf, 1); 988 MODULE_DEPEND(t6vf, t6nex, 1, 1, 1); 989 990 DRIVER_MODULE(cxgbev, t4vf, cxgbev_driver, cxgbev_devclass, 0, 0); 991 MODULE_VERSION(cxgbev, 1); 992 993 DRIVER_MODULE(cxlv, t5vf, cxlv_driver, cxlv_devclass, 0, 0); 994 MODULE_VERSION(cxlv, 1); 995 996 DRIVER_MODULE(ccv, t6vf, ccv_driver, ccv_devclass, 0, 0); 997 MODULE_VERSION(ccv, 1); 998