1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2018 Chelsio Communications, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30 #ifndef __T4_SMT_H 31 #define __T4_SMT_H 32 33 /* identifies sync vs async SMT_WRITE_REQs */ 34 #define S_SYNC_WR 12 35 #define V_SYNC_WR(x) ((x) << S_SYNC_WR) 36 #define F_SYNC_WR V_SYNC_WR(1) 37 38 enum { SMT_SIZE = 256 }; /* # of SMT entries */ 39 40 enum { 41 SMT_STATE_SWITCHING, /* entry is being used by a switching filter */ 42 SMT_STATE_UNUSED, /* entry not in use */ 43 SMT_STATE_ERROR /* entry is in error state */ 44 }; 45 46 struct smt_entry { 47 uint16_t state; /* entry state */ 48 uint16_t idx; /* entry index */ 49 uint32_t iqid; /* iqid for reply to write_sme */ 50 struct sge_wrq *wrq; /* queue to use for write_sme */ 51 uint16_t pfvf; /* pfvf number */ 52 volatile int refcnt; /* entry reference count */ 53 uint8_t smac[ETHER_ADDR_LEN]; /* source MAC address */ 54 struct mtx lock; 55 }; 56 57 struct smt_data { 58 struct rwlock lock; 59 u_int smt_size; 60 struct smt_entry smtab[]; 61 }; 62 63 64 int t4_init_smt(struct adapter *, int); 65 int t4_free_smt(struct smt_data *); 66 struct smt_entry *t4_find_or_alloc_sme(struct smt_data *, uint8_t *); 67 struct smt_entry *t4_smt_alloc_switching(struct smt_data *, uint8_t *); 68 int t4_smt_set_switching(struct adapter *, struct smt_entry *, 69 uint16_t, uint8_t *); 70 int t4_write_sme(struct smt_entry *); 71 int do_smt_write_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 72 73 static inline void 74 t4_smt_release(struct smt_entry *e) 75 { 76 MPASS(e != NULL); 77 if (atomic_fetchadd_int(&e->refcnt, -1) == 1) { 78 mtx_lock(&e->lock); 79 e->state = SMT_STATE_UNUSED; 80 mtx_unlock(&e->lock); 81 } 82 83 } 84 85 int sysctl_smt(SYSCTL_HANDLER_ARGS); 86 87 #endif /* __T4_SMT_H */ 88