1 /*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 34 #include <sys/types.h> 35 #include <sys/eventhandler.h> 36 #include <sys/mbuf.h> 37 #include <sys/socket.h> 38 #include <sys/kernel.h> 39 #include <sys/malloc.h> 40 #include <sys/queue.h> 41 #include <sys/sbuf.h> 42 #include <sys/taskqueue.h> 43 #include <sys/time.h> 44 #include <sys/sglist.h> 45 #include <sys/sysctl.h> 46 #include <sys/smp.h> 47 #include <sys/counter.h> 48 #include <net/bpf.h> 49 #include <net/ethernet.h> 50 #include <net/if.h> 51 #include <net/if_vlan_var.h> 52 #include <netinet/in.h> 53 #include <netinet/ip.h> 54 #include <netinet/ip6.h> 55 #include <netinet/tcp.h> 56 #include <machine/md_var.h> 57 #include <vm/vm.h> 58 #include <vm/pmap.h> 59 #ifdef DEV_NETMAP 60 #include <machine/bus.h> 61 #include <sys/selinfo.h> 62 #include <net/if_var.h> 63 #include <net/netmap.h> 64 #include <dev/netmap/netmap_kern.h> 65 #endif 66 67 #include "common/common.h" 68 #include "common/t4_regs.h" 69 #include "common/t4_regs_values.h" 70 #include "common/t4_msg.h" 71 #include "t4_mp_ring.h" 72 73 #ifdef T4_PKT_TIMESTAMP 74 #define RX_COPY_THRESHOLD (MINCLSIZE - 8) 75 #else 76 #define RX_COPY_THRESHOLD MINCLSIZE 77 #endif 78 79 /* 80 * Ethernet frames are DMA'd at this byte offset into the freelist buffer. 81 * 0-7 are valid values. 82 */ 83 int fl_pktshift = 2; 84 TUNABLE_INT("hw.cxgbe.fl_pktshift", &fl_pktshift); 85 86 /* 87 * Pad ethernet payload up to this boundary. 88 * -1: driver should figure out a good value. 89 * 0: disable padding. 90 * Any power of 2 from 32 to 4096 (both inclusive) is also a valid value. 91 */ 92 int fl_pad = -1; 93 TUNABLE_INT("hw.cxgbe.fl_pad", &fl_pad); 94 95 /* 96 * Status page length. 97 * -1: driver should figure out a good value. 98 * 64 or 128 are the only other valid values. 99 */ 100 int spg_len = -1; 101 TUNABLE_INT("hw.cxgbe.spg_len", &spg_len); 102 103 /* 104 * Congestion drops. 105 * -1: no congestion feedback (not recommended). 106 * 0: backpressure the channel instead of dropping packets right away. 107 * 1: no backpressure, drop packets for the congested queue immediately. 108 */ 109 static int cong_drop = 0; 110 TUNABLE_INT("hw.cxgbe.cong_drop", &cong_drop); 111 112 /* 113 * Deliver multiple frames in the same free list buffer if they fit. 114 * -1: let the driver decide whether to enable buffer packing or not. 115 * 0: disable buffer packing. 116 * 1: enable buffer packing. 117 */ 118 static int buffer_packing = -1; 119 TUNABLE_INT("hw.cxgbe.buffer_packing", &buffer_packing); 120 121 /* 122 * Start next frame in a packed buffer at this boundary. 123 * -1: driver should figure out a good value. 124 * T4: driver will ignore this and use the same value as fl_pad above. 125 * T5: 16, or a power of 2 from 64 to 4096 (both inclusive) is a valid value. 126 */ 127 static int fl_pack = -1; 128 TUNABLE_INT("hw.cxgbe.fl_pack", &fl_pack); 129 130 /* 131 * Allow the driver to create mbuf(s) in a cluster allocated for rx. 132 * 0: never; always allocate mbufs from the zone_mbuf UMA zone. 133 * 1: ok to create mbuf(s) within a cluster if there is room. 134 */ 135 static int allow_mbufs_in_cluster = 1; 136 TUNABLE_INT("hw.cxgbe.allow_mbufs_in_cluster", &allow_mbufs_in_cluster); 137 138 /* 139 * Largest rx cluster size that the driver is allowed to allocate. 140 */ 141 static int largest_rx_cluster = MJUM16BYTES; 142 TUNABLE_INT("hw.cxgbe.largest_rx_cluster", &largest_rx_cluster); 143 144 /* 145 * Size of cluster allocation that's most likely to succeed. The driver will 146 * fall back to this size if it fails to allocate clusters larger than this. 147 */ 148 static int safest_rx_cluster = PAGE_SIZE; 149 TUNABLE_INT("hw.cxgbe.safest_rx_cluster", &safest_rx_cluster); 150 151 struct txpkts { 152 u_int wr_type; /* type 0 or type 1 */ 153 u_int npkt; /* # of packets in this work request */ 154 u_int plen; /* total payload (sum of all packets) */ 155 u_int len16; /* # of 16B pieces used by this work request */ 156 }; 157 158 /* A packet's SGL. This + m_pkthdr has all info needed for tx */ 159 struct sgl { 160 struct sglist sg; 161 struct sglist_seg seg[TX_SGL_SEGS]; 162 }; 163 164 static int service_iq(struct sge_iq *, int); 165 static struct mbuf *get_fl_payload(struct adapter *, struct sge_fl *, uint32_t); 166 static int t4_eth_rx(struct sge_iq *, const struct rss_header *, struct mbuf *); 167 static inline void init_iq(struct sge_iq *, struct adapter *, int, int, int); 168 static inline void init_fl(struct adapter *, struct sge_fl *, int, int, char *); 169 static inline void init_eq(struct sge_eq *, int, int, uint8_t, uint16_t, 170 char *); 171 static int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *, 172 bus_addr_t *, void **); 173 static int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 174 void *); 175 static int alloc_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *, 176 int, int); 177 static int free_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *); 178 static void add_fl_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *, 179 struct sge_fl *); 180 static int alloc_fwq(struct adapter *); 181 static int free_fwq(struct adapter *); 182 static int alloc_mgmtq(struct adapter *); 183 static int free_mgmtq(struct adapter *); 184 static int alloc_rxq(struct vi_info *, struct sge_rxq *, int, int, 185 struct sysctl_oid *); 186 static int free_rxq(struct vi_info *, struct sge_rxq *); 187 #ifdef TCP_OFFLOAD 188 static int alloc_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *, int, int, 189 struct sysctl_oid *); 190 static int free_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *); 191 #endif 192 #ifdef DEV_NETMAP 193 static int alloc_nm_rxq(struct vi_info *, struct sge_nm_rxq *, int, int, 194 struct sysctl_oid *); 195 static int free_nm_rxq(struct vi_info *, struct sge_nm_rxq *); 196 static int alloc_nm_txq(struct vi_info *, struct sge_nm_txq *, int, int, 197 struct sysctl_oid *); 198 static int free_nm_txq(struct vi_info *, struct sge_nm_txq *); 199 #endif 200 static int ctrl_eq_alloc(struct adapter *, struct sge_eq *); 201 static int eth_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *); 202 #ifdef TCP_OFFLOAD 203 static int ofld_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *); 204 #endif 205 static int alloc_eq(struct adapter *, struct vi_info *, struct sge_eq *); 206 static int free_eq(struct adapter *, struct sge_eq *); 207 static int alloc_wrq(struct adapter *, struct vi_info *, struct sge_wrq *, 208 struct sysctl_oid *); 209 static int free_wrq(struct adapter *, struct sge_wrq *); 210 static int alloc_txq(struct vi_info *, struct sge_txq *, int, 211 struct sysctl_oid *); 212 static int free_txq(struct vi_info *, struct sge_txq *); 213 static void oneseg_dma_callback(void *, bus_dma_segment_t *, int, int); 214 static inline void ring_fl_db(struct adapter *, struct sge_fl *); 215 static int refill_fl(struct adapter *, struct sge_fl *, int); 216 static void refill_sfl(void *); 217 static int alloc_fl_sdesc(struct sge_fl *); 218 static void free_fl_sdesc(struct adapter *, struct sge_fl *); 219 static void find_best_refill_source(struct adapter *, struct sge_fl *, int); 220 static void find_safe_refill_source(struct adapter *, struct sge_fl *); 221 static void add_fl_to_sfl(struct adapter *, struct sge_fl *); 222 223 static inline void get_pkt_gl(struct mbuf *, struct sglist *); 224 static inline u_int txpkt_len16(u_int, u_int); 225 static inline u_int txpkts0_len16(u_int); 226 static inline u_int txpkts1_len16(void); 227 static u_int write_txpkt_wr(struct sge_txq *, struct fw_eth_tx_pkt_wr *, 228 struct mbuf *, u_int); 229 static int try_txpkts(struct mbuf *, struct mbuf *, struct txpkts *, u_int); 230 static int add_to_txpkts(struct mbuf *, struct txpkts *, u_int); 231 static u_int write_txpkts_wr(struct sge_txq *, struct fw_eth_tx_pkts_wr *, 232 struct mbuf *, const struct txpkts *, u_int); 233 static void write_gl_to_txd(struct sge_txq *, struct mbuf *, caddr_t *, int); 234 static inline void copy_to_txd(struct sge_eq *, caddr_t, caddr_t *, int); 235 static inline void ring_eq_db(struct adapter *, struct sge_eq *, u_int); 236 static inline uint16_t read_hw_cidx(struct sge_eq *); 237 static inline u_int reclaimable_tx_desc(struct sge_eq *); 238 static inline u_int total_available_tx_desc(struct sge_eq *); 239 static u_int reclaim_tx_descs(struct sge_txq *, u_int); 240 static void tx_reclaim(void *, int); 241 static __be64 get_flit(struct sglist_seg *, int, int); 242 static int handle_sge_egr_update(struct sge_iq *, const struct rss_header *, 243 struct mbuf *); 244 static int handle_fw_msg(struct sge_iq *, const struct rss_header *, 245 struct mbuf *); 246 static void wrq_tx_drain(void *, int); 247 static void drain_wrq_wr_list(struct adapter *, struct sge_wrq *); 248 249 static int sysctl_uint16(SYSCTL_HANDLER_ARGS); 250 static int sysctl_bufsizes(SYSCTL_HANDLER_ARGS); 251 252 static counter_u64_t extfree_refs; 253 static counter_u64_t extfree_rels; 254 255 /* 256 * Called on MOD_LOAD. Validates and calculates the SGE tunables. 257 */ 258 void 259 t4_sge_modload(void) 260 { 261 262 if (fl_pktshift < 0 || fl_pktshift > 7) { 263 printf("Invalid hw.cxgbe.fl_pktshift value (%d)," 264 " using 2 instead.\n", fl_pktshift); 265 fl_pktshift = 2; 266 } 267 268 if (spg_len != 64 && spg_len != 128) { 269 int len; 270 271 #if defined(__i386__) || defined(__amd64__) 272 len = cpu_clflush_line_size > 64 ? 128 : 64; 273 #else 274 len = 64; 275 #endif 276 if (spg_len != -1) { 277 printf("Invalid hw.cxgbe.spg_len value (%d)," 278 " using %d instead.\n", spg_len, len); 279 } 280 spg_len = len; 281 } 282 283 if (cong_drop < -1 || cong_drop > 1) { 284 printf("Invalid hw.cxgbe.cong_drop value (%d)," 285 " using 0 instead.\n", cong_drop); 286 cong_drop = 0; 287 } 288 289 extfree_refs = counter_u64_alloc(M_WAITOK); 290 extfree_rels = counter_u64_alloc(M_WAITOK); 291 counter_u64_zero(extfree_refs); 292 counter_u64_zero(extfree_rels); 293 } 294 295 void 296 t4_sge_modunload(void) 297 { 298 299 counter_u64_free(extfree_refs); 300 counter_u64_free(extfree_rels); 301 } 302 303 uint64_t 304 t4_sge_extfree_refs(void) 305 { 306 uint64_t refs, rels; 307 308 rels = counter_u64_fetch(extfree_rels); 309 refs = counter_u64_fetch(extfree_refs); 310 311 return (refs - rels); 312 } 313 314 void 315 t4_init_sge_cpl_handlers(struct adapter *sc) 316 { 317 318 t4_register_cpl_handler(sc, CPL_FW4_MSG, handle_fw_msg); 319 t4_register_cpl_handler(sc, CPL_FW6_MSG, handle_fw_msg); 320 t4_register_cpl_handler(sc, CPL_SGE_EGR_UPDATE, handle_sge_egr_update); 321 t4_register_cpl_handler(sc, CPL_RX_PKT, t4_eth_rx); 322 t4_register_fw_msg_handler(sc, FW6_TYPE_CMD_RPL, t4_handle_fw_rpl); 323 } 324 325 static inline void 326 setup_pad_and_pack_boundaries(struct adapter *sc) 327 { 328 uint32_t v, m; 329 int pad, pack; 330 331 pad = fl_pad; 332 if (fl_pad < 32 || fl_pad > 4096 || !powerof2(fl_pad)) { 333 /* 334 * If there is any chance that we might use buffer packing and 335 * the chip is a T4, then pick 64 as the pad/pack boundary. Set 336 * it to 32 in all other cases. 337 */ 338 pad = is_t4(sc) && buffer_packing ? 64 : 32; 339 340 /* 341 * For fl_pad = 0 we'll still write a reasonable value to the 342 * register but all the freelists will opt out of padding. 343 * We'll complain here only if the user tried to set it to a 344 * value greater than 0 that was invalid. 345 */ 346 if (fl_pad > 0) { 347 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pad value" 348 " (%d), using %d instead.\n", fl_pad, pad); 349 } 350 } 351 m = V_INGPADBOUNDARY(M_INGPADBOUNDARY); 352 v = V_INGPADBOUNDARY(ilog2(pad) - 5); 353 t4_set_reg_field(sc, A_SGE_CONTROL, m, v); 354 355 if (is_t4(sc)) { 356 if (fl_pack != -1 && fl_pack != pad) { 357 /* Complain but carry on. */ 358 device_printf(sc->dev, "hw.cxgbe.fl_pack (%d) ignored," 359 " using %d instead.\n", fl_pack, pad); 360 } 361 return; 362 } 363 364 pack = fl_pack; 365 if (fl_pack < 16 || fl_pack == 32 || fl_pack > 4096 || 366 !powerof2(fl_pack)) { 367 pack = max(sc->params.pci.mps, CACHE_LINE_SIZE); 368 MPASS(powerof2(pack)); 369 if (pack < 16) 370 pack = 16; 371 if (pack == 32) 372 pack = 64; 373 if (pack > 4096) 374 pack = 4096; 375 if (fl_pack != -1) { 376 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pack value" 377 " (%d), using %d instead.\n", fl_pack, pack); 378 } 379 } 380 m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY); 381 if (pack == 16) 382 v = V_INGPACKBOUNDARY(0); 383 else 384 v = V_INGPACKBOUNDARY(ilog2(pack) - 5); 385 386 MPASS(!is_t4(sc)); /* T4 doesn't have SGE_CONTROL2 */ 387 t4_set_reg_field(sc, A_SGE_CONTROL2, m, v); 388 } 389 390 /* 391 * adap->params.vpd.cclk must be set up before this is called. 392 */ 393 void 394 t4_tweak_chip_settings(struct adapter *sc) 395 { 396 int i; 397 uint32_t v, m; 398 int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200}; 399 int timer_max = M_TIMERVALUE0 * 1000 / sc->params.vpd.cclk; 400 int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */ 401 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 402 static int sge_flbuf_sizes[] = { 403 MCLBYTES, 404 #if MJUMPAGESIZE != MCLBYTES 405 MJUMPAGESIZE, 406 MJUMPAGESIZE - CL_METADATA_SIZE, 407 MJUMPAGESIZE - 2 * MSIZE - CL_METADATA_SIZE, 408 #endif 409 MJUM9BYTES, 410 MJUM16BYTES, 411 MCLBYTES - MSIZE - CL_METADATA_SIZE, 412 MJUM9BYTES - CL_METADATA_SIZE, 413 MJUM16BYTES - CL_METADATA_SIZE, 414 }; 415 416 KASSERT(sc->flags & MASTER_PF, 417 ("%s: trying to change chip settings when not master.", __func__)); 418 419 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE; 420 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE | 421 V_EGRSTATUSPAGESIZE(spg_len == 128); 422 t4_set_reg_field(sc, A_SGE_CONTROL, m, v); 423 424 setup_pad_and_pack_boundaries(sc); 425 426 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) | 427 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) | 428 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) | 429 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) | 430 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) | 431 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) | 432 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) | 433 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10); 434 t4_write_reg(sc, A_SGE_HOST_PAGE_SIZE, v); 435 436 KASSERT(nitems(sge_flbuf_sizes) <= SGE_FLBUF_SIZES, 437 ("%s: hw buffer size table too big", __func__)); 438 for (i = 0; i < min(nitems(sge_flbuf_sizes), SGE_FLBUF_SIZES); i++) { 439 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0 + (4 * i), 440 sge_flbuf_sizes[i]); 441 } 442 443 v = V_THRESHOLD_0(intr_pktcount[0]) | V_THRESHOLD_1(intr_pktcount[1]) | 444 V_THRESHOLD_2(intr_pktcount[2]) | V_THRESHOLD_3(intr_pktcount[3]); 445 t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD, v); 446 447 KASSERT(intr_timer[0] <= timer_max, 448 ("%s: not a single usable timer (%d, %d)", __func__, intr_timer[0], 449 timer_max)); 450 for (i = 1; i < nitems(intr_timer); i++) { 451 KASSERT(intr_timer[i] >= intr_timer[i - 1], 452 ("%s: timers not listed in increasing order (%d)", 453 __func__, i)); 454 455 while (intr_timer[i] > timer_max) { 456 if (i == nitems(intr_timer) - 1) { 457 intr_timer[i] = timer_max; 458 break; 459 } 460 intr_timer[i] += intr_timer[i - 1]; 461 intr_timer[i] /= 2; 462 } 463 } 464 465 v = V_TIMERVALUE0(us_to_core_ticks(sc, intr_timer[0])) | 466 V_TIMERVALUE1(us_to_core_ticks(sc, intr_timer[1])); 467 t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1, v); 468 v = V_TIMERVALUE2(us_to_core_ticks(sc, intr_timer[2])) | 469 V_TIMERVALUE3(us_to_core_ticks(sc, intr_timer[3])); 470 t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3, v); 471 v = V_TIMERVALUE4(us_to_core_ticks(sc, intr_timer[4])) | 472 V_TIMERVALUE5(us_to_core_ticks(sc, intr_timer[5])); 473 t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5, v); 474 475 /* 4K, 16K, 64K, 256K DDP "page sizes" */ 476 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 477 t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, v); 478 479 m = v = F_TDDPTAGTCB; 480 t4_set_reg_field(sc, A_ULP_RX_CTL, m, v); 481 482 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 483 F_RESETDDPOFFSET; 484 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 485 t4_set_reg_field(sc, A_TP_PARA_REG5, m, v); 486 } 487 488 /* 489 * SGE wants the buffer to be at least 64B and then a multiple of 16. If 490 * padding is is use the buffer's start and end need to be aligned to the pad 491 * boundary as well. We'll just make sure that the size is a multiple of the 492 * boundary here, it is up to the buffer allocation code to make sure the start 493 * of the buffer is aligned as well. 494 */ 495 static inline int 496 hwsz_ok(struct adapter *sc, int hwsz) 497 { 498 int mask = fl_pad ? sc->sge.pad_boundary - 1 : 16 - 1; 499 500 return (hwsz >= 64 && (hwsz & mask) == 0); 501 } 502 503 /* 504 * XXX: driver really should be able to deal with unexpected settings. 505 */ 506 int 507 t4_read_chip_settings(struct adapter *sc) 508 { 509 struct sge *s = &sc->sge; 510 int i, j, n, rc = 0; 511 uint32_t m, v, r; 512 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 513 static int sw_buf_sizes[] = { /* Sorted by size */ 514 MCLBYTES, 515 #if MJUMPAGESIZE != MCLBYTES 516 MJUMPAGESIZE, 517 #endif 518 MJUM9BYTES, 519 MJUM16BYTES 520 }; 521 struct sw_zone_info *swz, *safe_swz; 522 struct hw_buf_info *hwb; 523 524 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE; 525 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE | 526 V_EGRSTATUSPAGESIZE(spg_len == 128); 527 r = t4_read_reg(sc, A_SGE_CONTROL); 528 if ((r & m) != v) { 529 device_printf(sc->dev, "invalid SGE_CONTROL(0x%x)\n", r); 530 rc = EINVAL; 531 } 532 s->pad_boundary = 1 << (G_INGPADBOUNDARY(r) + 5); 533 534 if (is_t4(sc)) 535 s->pack_boundary = s->pad_boundary; 536 else { 537 r = t4_read_reg(sc, A_SGE_CONTROL2); 538 if (G_INGPACKBOUNDARY(r) == 0) 539 s->pack_boundary = 16; 540 else 541 s->pack_boundary = 1 << (G_INGPACKBOUNDARY(r) + 5); 542 } 543 544 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) | 545 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) | 546 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) | 547 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) | 548 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) | 549 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) | 550 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) | 551 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10); 552 r = t4_read_reg(sc, A_SGE_HOST_PAGE_SIZE); 553 if (r != v) { 554 device_printf(sc->dev, "invalid SGE_HOST_PAGE_SIZE(0x%x)\n", r); 555 rc = EINVAL; 556 } 557 558 /* Filter out unusable hw buffer sizes entirely (mark with -2). */ 559 hwb = &s->hw_buf_info[0]; 560 for (i = 0; i < nitems(s->hw_buf_info); i++, hwb++) { 561 r = t4_read_reg(sc, A_SGE_FL_BUFFER_SIZE0 + (4 * i)); 562 hwb->size = r; 563 hwb->zidx = hwsz_ok(sc, r) ? -1 : -2; 564 hwb->next = -1; 565 } 566 567 /* 568 * Create a sorted list in decreasing order of hw buffer sizes (and so 569 * increasing order of spare area) for each software zone. 570 * 571 * If padding is enabled then the start and end of the buffer must align 572 * to the pad boundary; if packing is enabled then they must align with 573 * the pack boundary as well. Allocations from the cluster zones are 574 * aligned to min(size, 4K), so the buffer starts at that alignment and 575 * ends at hwb->size alignment. If mbuf inlining is allowed the 576 * starting alignment will be reduced to MSIZE and the driver will 577 * exercise appropriate caution when deciding on the best buffer layout 578 * to use. 579 */ 580 n = 0; /* no usable buffer size to begin with */ 581 swz = &s->sw_zone_info[0]; 582 safe_swz = NULL; 583 for (i = 0; i < SW_ZONE_SIZES; i++, swz++) { 584 int8_t head = -1, tail = -1; 585 586 swz->size = sw_buf_sizes[i]; 587 swz->zone = m_getzone(swz->size); 588 swz->type = m_gettype(swz->size); 589 590 if (swz->size < PAGE_SIZE) { 591 MPASS(powerof2(swz->size)); 592 if (fl_pad && (swz->size % sc->sge.pad_boundary != 0)) 593 continue; 594 } 595 596 if (swz->size == safest_rx_cluster) 597 safe_swz = swz; 598 599 hwb = &s->hw_buf_info[0]; 600 for (j = 0; j < SGE_FLBUF_SIZES; j++, hwb++) { 601 if (hwb->zidx != -1 || hwb->size > swz->size) 602 continue; 603 #ifdef INVARIANTS 604 if (fl_pad) 605 MPASS(hwb->size % sc->sge.pad_boundary == 0); 606 #endif 607 hwb->zidx = i; 608 if (head == -1) 609 head = tail = j; 610 else if (hwb->size < s->hw_buf_info[tail].size) { 611 s->hw_buf_info[tail].next = j; 612 tail = j; 613 } else { 614 int8_t *cur; 615 struct hw_buf_info *t; 616 617 for (cur = &head; *cur != -1; cur = &t->next) { 618 t = &s->hw_buf_info[*cur]; 619 if (hwb->size == t->size) { 620 hwb->zidx = -2; 621 break; 622 } 623 if (hwb->size > t->size) { 624 hwb->next = *cur; 625 *cur = j; 626 break; 627 } 628 } 629 } 630 } 631 swz->head_hwidx = head; 632 swz->tail_hwidx = tail; 633 634 if (tail != -1) { 635 n++; 636 if (swz->size - s->hw_buf_info[tail].size >= 637 CL_METADATA_SIZE) 638 sc->flags |= BUF_PACKING_OK; 639 } 640 } 641 if (n == 0) { 642 device_printf(sc->dev, "no usable SGE FL buffer size.\n"); 643 rc = EINVAL; 644 } 645 646 s->safe_hwidx1 = -1; 647 s->safe_hwidx2 = -1; 648 if (safe_swz != NULL) { 649 s->safe_hwidx1 = safe_swz->head_hwidx; 650 for (i = safe_swz->head_hwidx; i != -1; i = hwb->next) { 651 int spare; 652 653 hwb = &s->hw_buf_info[i]; 654 #ifdef INVARIANTS 655 if (fl_pad) 656 MPASS(hwb->size % sc->sge.pad_boundary == 0); 657 #endif 658 spare = safe_swz->size - hwb->size; 659 if (spare >= CL_METADATA_SIZE) { 660 s->safe_hwidx2 = i; 661 break; 662 } 663 } 664 } 665 666 r = t4_read_reg(sc, A_SGE_INGRESS_RX_THRESHOLD); 667 s->counter_val[0] = G_THRESHOLD_0(r); 668 s->counter_val[1] = G_THRESHOLD_1(r); 669 s->counter_val[2] = G_THRESHOLD_2(r); 670 s->counter_val[3] = G_THRESHOLD_3(r); 671 672 r = t4_read_reg(sc, A_SGE_TIMER_VALUE_0_AND_1); 673 s->timer_val[0] = G_TIMERVALUE0(r) / core_ticks_per_usec(sc); 674 s->timer_val[1] = G_TIMERVALUE1(r) / core_ticks_per_usec(sc); 675 r = t4_read_reg(sc, A_SGE_TIMER_VALUE_2_AND_3); 676 s->timer_val[2] = G_TIMERVALUE2(r) / core_ticks_per_usec(sc); 677 s->timer_val[3] = G_TIMERVALUE3(r) / core_ticks_per_usec(sc); 678 r = t4_read_reg(sc, A_SGE_TIMER_VALUE_4_AND_5); 679 s->timer_val[4] = G_TIMERVALUE4(r) / core_ticks_per_usec(sc); 680 s->timer_val[5] = G_TIMERVALUE5(r) / core_ticks_per_usec(sc); 681 682 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 683 r = t4_read_reg(sc, A_ULP_RX_TDDP_PSZ); 684 if (r != v) { 685 device_printf(sc->dev, "invalid ULP_RX_TDDP_PSZ(0x%x)\n", r); 686 rc = EINVAL; 687 } 688 689 m = v = F_TDDPTAGTCB; 690 r = t4_read_reg(sc, A_ULP_RX_CTL); 691 if ((r & m) != v) { 692 device_printf(sc->dev, "invalid ULP_RX_CTL(0x%x)\n", r); 693 rc = EINVAL; 694 } 695 696 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 697 F_RESETDDPOFFSET; 698 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 699 r = t4_read_reg(sc, A_TP_PARA_REG5); 700 if ((r & m) != v) { 701 device_printf(sc->dev, "invalid TP_PARA_REG5(0x%x)\n", r); 702 rc = EINVAL; 703 } 704 705 r = t4_read_reg(sc, A_SGE_CONM_CTRL); 706 s->fl_starve_threshold = G_EGRTHRESHOLD(r) * 2 + 1; 707 if (is_t4(sc)) 708 s->fl_starve_threshold2 = s->fl_starve_threshold; 709 else 710 s->fl_starve_threshold2 = G_EGRTHRESHOLDPACKING(r) * 2 + 1; 711 712 /* egress queues: log2 of # of doorbells per BAR2 page */ 713 r = t4_read_reg(sc, A_SGE_EGRESS_QUEUES_PER_PAGE_PF); 714 r >>= S_QUEUESPERPAGEPF0 + 715 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * sc->pf; 716 s->eq_s_qpp = r & M_QUEUESPERPAGEPF0; 717 718 /* ingress queues: log2 of # of doorbells per BAR2 page */ 719 r = t4_read_reg(sc, A_SGE_INGRESS_QUEUES_PER_PAGE_PF); 720 r >>= S_QUEUESPERPAGEPF0 + 721 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * sc->pf; 722 s->iq_s_qpp = r & M_QUEUESPERPAGEPF0; 723 724 t4_init_tp_params(sc); 725 726 t4_read_mtu_tbl(sc, sc->params.mtus, NULL); 727 t4_load_mtus(sc, sc->params.mtus, sc->params.a_wnd, sc->params.b_wnd); 728 729 return (rc); 730 } 731 732 int 733 t4_create_dma_tag(struct adapter *sc) 734 { 735 int rc; 736 737 rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0, 738 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE, 739 BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL, 740 NULL, &sc->dmat); 741 if (rc != 0) { 742 device_printf(sc->dev, 743 "failed to create main DMA tag: %d\n", rc); 744 } 745 746 return (rc); 747 } 748 749 void 750 t4_sge_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx, 751 struct sysctl_oid_list *children) 752 { 753 754 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "buffer_sizes", 755 CTLTYPE_STRING | CTLFLAG_RD, &sc->sge, 0, sysctl_bufsizes, "A", 756 "freelist buffer sizes"); 757 758 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pktshift", CTLFLAG_RD, 759 NULL, fl_pktshift, "payload DMA offset in rx buffer (bytes)"); 760 761 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pad", CTLFLAG_RD, 762 NULL, sc->sge.pad_boundary, "payload pad boundary (bytes)"); 763 764 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "spg_len", CTLFLAG_RD, 765 NULL, spg_len, "status page size (bytes)"); 766 767 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_drop", CTLFLAG_RD, 768 NULL, cong_drop, "congestion drop setting"); 769 770 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pack", CTLFLAG_RD, 771 NULL, sc->sge.pack_boundary, "payload pack boundary (bytes)"); 772 } 773 774 int 775 t4_destroy_dma_tag(struct adapter *sc) 776 { 777 if (sc->dmat) 778 bus_dma_tag_destroy(sc->dmat); 779 780 return (0); 781 } 782 783 /* 784 * Allocate and initialize the firmware event queue and the management queue. 785 * 786 * Returns errno on failure. Resources allocated up to that point may still be 787 * allocated. Caller is responsible for cleanup in case this function fails. 788 */ 789 int 790 t4_setup_adapter_queues(struct adapter *sc) 791 { 792 int rc; 793 794 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 795 796 sysctl_ctx_init(&sc->ctx); 797 sc->flags |= ADAP_SYSCTL_CTX; 798 799 /* 800 * Firmware event queue 801 */ 802 rc = alloc_fwq(sc); 803 if (rc != 0) 804 return (rc); 805 806 /* 807 * Management queue. This is just a control queue that uses the fwq as 808 * its associated iq. 809 */ 810 rc = alloc_mgmtq(sc); 811 812 return (rc); 813 } 814 815 /* 816 * Idempotent 817 */ 818 int 819 t4_teardown_adapter_queues(struct adapter *sc) 820 { 821 822 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 823 824 /* Do this before freeing the queue */ 825 if (sc->flags & ADAP_SYSCTL_CTX) { 826 sysctl_ctx_free(&sc->ctx); 827 sc->flags &= ~ADAP_SYSCTL_CTX; 828 } 829 830 free_mgmtq(sc); 831 free_fwq(sc); 832 833 return (0); 834 } 835 836 static inline int 837 first_vector(struct vi_info *vi) 838 { 839 struct adapter *sc = vi->pi->adapter; 840 841 if (sc->intr_count == 1) 842 return (0); 843 844 return (vi->first_intr); 845 } 846 847 /* 848 * Given an arbitrary "index," come up with an iq that can be used by other 849 * queues (of this VI) for interrupt forwarding, SGE egress updates, etc. 850 * The iq returned is guaranteed to be something that takes direct interrupts. 851 */ 852 static struct sge_iq * 853 vi_intr_iq(struct vi_info *vi, int idx) 854 { 855 struct adapter *sc = vi->pi->adapter; 856 struct sge *s = &sc->sge; 857 struct sge_iq *iq = NULL; 858 int nintr, i; 859 860 if (sc->intr_count == 1) 861 return (&sc->sge.fwq); 862 863 KASSERT(!(vi->flags & VI_NETMAP), 864 ("%s: called on netmap VI", __func__)); 865 nintr = vi->nintr; 866 KASSERT(nintr != 0, 867 ("%s: vi %p has no exclusive interrupts, total interrupts = %d", 868 __func__, vi, sc->intr_count)); 869 i = idx % nintr; 870 871 if (vi->flags & INTR_RXQ) { 872 if (i < vi->nrxq) { 873 iq = &s->rxq[vi->first_rxq + i].iq; 874 goto done; 875 } 876 i -= vi->nrxq; 877 } 878 #ifdef TCP_OFFLOAD 879 if (vi->flags & INTR_OFLD_RXQ) { 880 if (i < vi->nofldrxq) { 881 iq = &s->ofld_rxq[vi->first_ofld_rxq + i].iq; 882 goto done; 883 } 884 i -= vi->nofldrxq; 885 } 886 #endif 887 panic("%s: vi %p, intr_flags 0x%lx, idx %d, total intr %d\n", __func__, 888 vi, vi->flags & INTR_ALL, idx, nintr); 889 done: 890 MPASS(iq != NULL); 891 KASSERT(iq->flags & IQ_INTR, 892 ("%s: iq %p (vi %p, intr_flags 0x%lx, idx %d)", __func__, iq, vi, 893 vi->flags & INTR_ALL, idx)); 894 return (iq); 895 } 896 897 /* Maximum payload that can be delivered with a single iq descriptor */ 898 static inline int 899 mtu_to_max_payload(struct adapter *sc, int mtu, const int toe) 900 { 901 int payload; 902 903 #ifdef TCP_OFFLOAD 904 if (toe) { 905 payload = sc->tt.rx_coalesce ? 906 G_RXCOALESCESIZE(t4_read_reg(sc, A_TP_PARA_REG2)) : mtu; 907 } else { 908 #endif 909 /* large enough even when hw VLAN extraction is disabled */ 910 payload = fl_pktshift + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 911 mtu; 912 #ifdef TCP_OFFLOAD 913 } 914 #endif 915 916 return (payload); 917 } 918 919 int 920 t4_setup_vi_queues(struct vi_info *vi) 921 { 922 int rc = 0, i, j, intr_idx, iqid; 923 struct sge_rxq *rxq; 924 struct sge_txq *txq; 925 struct sge_wrq *ctrlq; 926 #ifdef TCP_OFFLOAD 927 struct sge_ofld_rxq *ofld_rxq; 928 struct sge_wrq *ofld_txq; 929 #endif 930 #ifdef DEV_NETMAP 931 struct sge_nm_rxq *nm_rxq; 932 struct sge_nm_txq *nm_txq; 933 #endif 934 char name[16]; 935 struct port_info *pi = vi->pi; 936 struct adapter *sc = pi->adapter; 937 struct ifnet *ifp = vi->ifp; 938 struct sysctl_oid *oid = device_get_sysctl_tree(vi->dev); 939 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 940 int maxp, mtu = ifp->if_mtu; 941 942 /* Interrupt vector to start from (when using multiple vectors) */ 943 intr_idx = first_vector(vi); 944 945 #ifdef DEV_NETMAP 946 if (vi->flags & VI_NETMAP) { 947 /* 948 * We don't have buffers to back the netmap rx queues 949 * right now so we create the queues in a way that 950 * doesn't set off any congestion signal in the chip. 951 */ 952 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "rxq", 953 CTLFLAG_RD, NULL, "rx queues"); 954 for_each_nm_rxq(vi, i, nm_rxq) { 955 rc = alloc_nm_rxq(vi, nm_rxq, intr_idx, i, oid); 956 if (rc != 0) 957 goto done; 958 intr_idx++; 959 } 960 961 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "txq", 962 CTLFLAG_RD, NULL, "tx queues"); 963 for_each_nm_txq(vi, i, nm_txq) { 964 iqid = vi->first_rxq + (i % vi->nrxq); 965 rc = alloc_nm_txq(vi, nm_txq, iqid, i, oid); 966 if (rc != 0) 967 goto done; 968 } 969 goto done; 970 } 971 #endif 972 973 /* 974 * First pass over all NIC and TOE rx queues: 975 * a) initialize iq and fl 976 * b) allocate queue iff it will take direct interrupts. 977 */ 978 maxp = mtu_to_max_payload(sc, mtu, 0); 979 if (vi->flags & INTR_RXQ) { 980 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "rxq", 981 CTLFLAG_RD, NULL, "rx queues"); 982 } 983 for_each_rxq(vi, i, rxq) { 984 985 init_iq(&rxq->iq, sc, vi->tmr_idx, vi->pktc_idx, vi->qsize_rxq); 986 987 snprintf(name, sizeof(name), "%s rxq%d-fl", 988 device_get_nameunit(vi->dev), i); 989 init_fl(sc, &rxq->fl, vi->qsize_rxq / 8, maxp, name); 990 991 if (vi->flags & INTR_RXQ) { 992 rxq->iq.flags |= IQ_INTR; 993 rc = alloc_rxq(vi, rxq, intr_idx, i, oid); 994 if (rc != 0) 995 goto done; 996 intr_idx++; 997 } 998 } 999 #ifdef TCP_OFFLOAD 1000 maxp = mtu_to_max_payload(sc, mtu, 1); 1001 if (vi->flags & INTR_OFLD_RXQ) { 1002 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_rxq", 1003 CTLFLAG_RD, NULL, 1004 "rx queues for offloaded TCP connections"); 1005 } 1006 for_each_ofld_rxq(vi, i, ofld_rxq) { 1007 1008 init_iq(&ofld_rxq->iq, sc, vi->tmr_idx, vi->pktc_idx, 1009 vi->qsize_rxq); 1010 1011 snprintf(name, sizeof(name), "%s ofld_rxq%d-fl", 1012 device_get_nameunit(vi->dev), i); 1013 init_fl(sc, &ofld_rxq->fl, vi->qsize_rxq / 8, maxp, name); 1014 1015 if (vi->flags & INTR_OFLD_RXQ) { 1016 ofld_rxq->iq.flags |= IQ_INTR; 1017 rc = alloc_ofld_rxq(vi, ofld_rxq, intr_idx, i, oid); 1018 if (rc != 0) 1019 goto done; 1020 intr_idx++; 1021 } 1022 } 1023 #endif 1024 1025 /* 1026 * Second pass over all NIC and TOE rx queues. The queues forwarding 1027 * their interrupts are allocated now. 1028 */ 1029 j = 0; 1030 if (!(vi->flags & INTR_RXQ)) { 1031 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "rxq", 1032 CTLFLAG_RD, NULL, "rx queues"); 1033 for_each_rxq(vi, i, rxq) { 1034 MPASS(!(rxq->iq.flags & IQ_INTR)); 1035 1036 intr_idx = vi_intr_iq(vi, j)->abs_id; 1037 1038 rc = alloc_rxq(vi, rxq, intr_idx, i, oid); 1039 if (rc != 0) 1040 goto done; 1041 j++; 1042 } 1043 } 1044 #ifdef TCP_OFFLOAD 1045 if (vi->nofldrxq != 0 && !(vi->flags & INTR_OFLD_RXQ)) { 1046 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_rxq", 1047 CTLFLAG_RD, NULL, 1048 "rx queues for offloaded TCP connections"); 1049 for_each_ofld_rxq(vi, i, ofld_rxq) { 1050 MPASS(!(ofld_rxq->iq.flags & IQ_INTR)); 1051 1052 intr_idx = vi_intr_iq(vi, j)->abs_id; 1053 1054 rc = alloc_ofld_rxq(vi, ofld_rxq, intr_idx, i, oid); 1055 if (rc != 0) 1056 goto done; 1057 j++; 1058 } 1059 } 1060 #endif 1061 1062 /* 1063 * Now the tx queues. Only one pass needed. 1064 */ 1065 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "txq", CTLFLAG_RD, 1066 NULL, "tx queues"); 1067 j = 0; 1068 for_each_txq(vi, i, txq) { 1069 iqid = vi_intr_iq(vi, j)->cntxt_id; 1070 snprintf(name, sizeof(name), "%s txq%d", 1071 device_get_nameunit(vi->dev), i); 1072 init_eq(&txq->eq, EQ_ETH, vi->qsize_txq, pi->tx_chan, iqid, 1073 name); 1074 1075 rc = alloc_txq(vi, txq, i, oid); 1076 if (rc != 0) 1077 goto done; 1078 j++; 1079 } 1080 #ifdef TCP_OFFLOAD 1081 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_txq", 1082 CTLFLAG_RD, NULL, "tx queues for offloaded TCP connections"); 1083 for_each_ofld_txq(vi, i, ofld_txq) { 1084 struct sysctl_oid *oid2; 1085 1086 iqid = vi_intr_iq(vi, j)->cntxt_id; 1087 snprintf(name, sizeof(name), "%s ofld_txq%d", 1088 device_get_nameunit(vi->dev), i); 1089 init_eq(&ofld_txq->eq, EQ_OFLD, vi->qsize_txq, pi->tx_chan, 1090 iqid, name); 1091 1092 snprintf(name, sizeof(name), "%d", i); 1093 oid2 = SYSCTL_ADD_NODE(&vi->ctx, SYSCTL_CHILDREN(oid), OID_AUTO, 1094 name, CTLFLAG_RD, NULL, "offload tx queue"); 1095 1096 rc = alloc_wrq(sc, vi, ofld_txq, oid2); 1097 if (rc != 0) 1098 goto done; 1099 j++; 1100 } 1101 #endif 1102 1103 /* 1104 * Finally, the control queue. 1105 */ 1106 if (!IS_MAIN_VI(vi)) 1107 goto done; 1108 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ctrlq", CTLFLAG_RD, 1109 NULL, "ctrl queue"); 1110 ctrlq = &sc->sge.ctrlq[pi->port_id]; 1111 iqid = vi_intr_iq(vi, 0)->cntxt_id; 1112 snprintf(name, sizeof(name), "%s ctrlq", device_get_nameunit(vi->dev)); 1113 init_eq(&ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE, pi->tx_chan, iqid, name); 1114 rc = alloc_wrq(sc, vi, ctrlq, oid); 1115 1116 done: 1117 if (rc) 1118 t4_teardown_vi_queues(vi); 1119 1120 return (rc); 1121 } 1122 1123 /* 1124 * Idempotent 1125 */ 1126 int 1127 t4_teardown_vi_queues(struct vi_info *vi) 1128 { 1129 int i; 1130 struct port_info *pi = vi->pi; 1131 struct adapter *sc = pi->adapter; 1132 struct sge_rxq *rxq; 1133 struct sge_txq *txq; 1134 #ifdef TCP_OFFLOAD 1135 struct sge_ofld_rxq *ofld_rxq; 1136 struct sge_wrq *ofld_txq; 1137 #endif 1138 #ifdef DEV_NETMAP 1139 struct sge_nm_rxq *nm_rxq; 1140 struct sge_nm_txq *nm_txq; 1141 #endif 1142 1143 /* Do this before freeing the queues */ 1144 if (vi->flags & VI_SYSCTL_CTX) { 1145 sysctl_ctx_free(&vi->ctx); 1146 vi->flags &= ~VI_SYSCTL_CTX; 1147 } 1148 1149 #ifdef DEV_NETMAP 1150 if (vi->flags & VI_NETMAP) { 1151 for_each_nm_txq(vi, i, nm_txq) { 1152 free_nm_txq(vi, nm_txq); 1153 } 1154 1155 for_each_nm_rxq(vi, i, nm_rxq) { 1156 free_nm_rxq(vi, nm_rxq); 1157 } 1158 return (0); 1159 } 1160 #endif 1161 1162 /* 1163 * Take down all the tx queues first, as they reference the rx queues 1164 * (for egress updates, etc.). 1165 */ 1166 1167 if (IS_MAIN_VI(vi)) 1168 free_wrq(sc, &sc->sge.ctrlq[pi->port_id]); 1169 1170 for_each_txq(vi, i, txq) { 1171 free_txq(vi, txq); 1172 } 1173 #ifdef TCP_OFFLOAD 1174 for_each_ofld_txq(vi, i, ofld_txq) { 1175 free_wrq(sc, ofld_txq); 1176 } 1177 #endif 1178 1179 /* 1180 * Then take down the rx queues that forward their interrupts, as they 1181 * reference other rx queues. 1182 */ 1183 1184 for_each_rxq(vi, i, rxq) { 1185 if ((rxq->iq.flags & IQ_INTR) == 0) 1186 free_rxq(vi, rxq); 1187 } 1188 #ifdef TCP_OFFLOAD 1189 for_each_ofld_rxq(vi, i, ofld_rxq) { 1190 if ((ofld_rxq->iq.flags & IQ_INTR) == 0) 1191 free_ofld_rxq(vi, ofld_rxq); 1192 } 1193 #endif 1194 1195 /* 1196 * Then take down the rx queues that take direct interrupts. 1197 */ 1198 1199 for_each_rxq(vi, i, rxq) { 1200 if (rxq->iq.flags & IQ_INTR) 1201 free_rxq(vi, rxq); 1202 } 1203 #ifdef TCP_OFFLOAD 1204 for_each_ofld_rxq(vi, i, ofld_rxq) { 1205 if (ofld_rxq->iq.flags & IQ_INTR) 1206 free_ofld_rxq(vi, ofld_rxq); 1207 } 1208 #endif 1209 1210 return (0); 1211 } 1212 1213 /* 1214 * Deals with errors and the firmware event queue. All data rx queues forward 1215 * their interrupt to the firmware event queue. 1216 */ 1217 void 1218 t4_intr_all(void *arg) 1219 { 1220 struct adapter *sc = arg; 1221 struct sge_iq *fwq = &sc->sge.fwq; 1222 1223 t4_intr_err(arg); 1224 if (atomic_cmpset_int(&fwq->state, IQS_IDLE, IQS_BUSY)) { 1225 service_iq(fwq, 0); 1226 atomic_cmpset_int(&fwq->state, IQS_BUSY, IQS_IDLE); 1227 } 1228 } 1229 1230 /* Deals with error interrupts */ 1231 void 1232 t4_intr_err(void *arg) 1233 { 1234 struct adapter *sc = arg; 1235 1236 t4_write_reg(sc, MYPF_REG(A_PCIE_PF_CLI), 0); 1237 t4_slow_intr_handler(sc); 1238 } 1239 1240 void 1241 t4_intr_evt(void *arg) 1242 { 1243 struct sge_iq *iq = arg; 1244 1245 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 1246 service_iq(iq, 0); 1247 atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 1248 } 1249 } 1250 1251 void 1252 t4_intr(void *arg) 1253 { 1254 struct sge_iq *iq = arg; 1255 1256 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 1257 service_iq(iq, 0); 1258 atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 1259 } 1260 } 1261 1262 /* 1263 * Deals with anything and everything on the given ingress queue. 1264 */ 1265 static int 1266 service_iq(struct sge_iq *iq, int budget) 1267 { 1268 struct sge_iq *q; 1269 struct sge_rxq *rxq = iq_to_rxq(iq); /* Use iff iq is part of rxq */ 1270 struct sge_fl *fl; /* Use iff IQ_HAS_FL */ 1271 struct adapter *sc = iq->adapter; 1272 struct iq_desc *d = &iq->desc[iq->cidx]; 1273 int ndescs = 0, limit; 1274 int rsp_type, refill; 1275 uint32_t lq; 1276 uint16_t fl_hw_cidx; 1277 struct mbuf *m0; 1278 STAILQ_HEAD(, sge_iq) iql = STAILQ_HEAD_INITIALIZER(iql); 1279 #if defined(INET) || defined(INET6) 1280 const struct timeval lro_timeout = {0, sc->lro_timeout}; 1281 #endif 1282 1283 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq)); 1284 1285 limit = budget ? budget : iq->qsize / 16; 1286 1287 if (iq->flags & IQ_HAS_FL) { 1288 fl = &rxq->fl; 1289 fl_hw_cidx = fl->hw_cidx; /* stable snapshot */ 1290 } else { 1291 fl = NULL; 1292 fl_hw_cidx = 0; /* to silence gcc warning */ 1293 } 1294 1295 /* 1296 * We always come back and check the descriptor ring for new indirect 1297 * interrupts and other responses after running a single handler. 1298 */ 1299 for (;;) { 1300 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) { 1301 1302 rmb(); 1303 1304 refill = 0; 1305 m0 = NULL; 1306 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen); 1307 lq = be32toh(d->rsp.pldbuflen_qid); 1308 1309 switch (rsp_type) { 1310 case X_RSPD_TYPE_FLBUF: 1311 1312 KASSERT(iq->flags & IQ_HAS_FL, 1313 ("%s: data for an iq (%p) with no freelist", 1314 __func__, iq)); 1315 1316 m0 = get_fl_payload(sc, fl, lq); 1317 if (__predict_false(m0 == NULL)) 1318 goto process_iql; 1319 refill = IDXDIFF(fl->hw_cidx, fl_hw_cidx, fl->sidx) > 2; 1320 #ifdef T4_PKT_TIMESTAMP 1321 /* 1322 * 60 bit timestamp for the payload is 1323 * *(uint64_t *)m0->m_pktdat. Note that it is 1324 * in the leading free-space in the mbuf. The 1325 * kernel can clobber it during a pullup, 1326 * m_copymdata, etc. You need to make sure that 1327 * the mbuf reaches you unmolested if you care 1328 * about the timestamp. 1329 */ 1330 *(uint64_t *)m0->m_pktdat = 1331 be64toh(ctrl->u.last_flit) & 1332 0xfffffffffffffff; 1333 #endif 1334 1335 /* fall through */ 1336 1337 case X_RSPD_TYPE_CPL: 1338 KASSERT(d->rss.opcode < NUM_CPL_CMDS, 1339 ("%s: bad opcode %02x.", __func__, 1340 d->rss.opcode)); 1341 sc->cpl_handler[d->rss.opcode](iq, &d->rss, m0); 1342 break; 1343 1344 case X_RSPD_TYPE_INTR: 1345 1346 /* 1347 * Interrupts should be forwarded only to queues 1348 * that are not forwarding their interrupts. 1349 * This means service_iq can recurse but only 1 1350 * level deep. 1351 */ 1352 KASSERT(budget == 0, 1353 ("%s: budget %u, rsp_type %u", __func__, 1354 budget, rsp_type)); 1355 1356 /* 1357 * There are 1K interrupt-capable queues (qids 0 1358 * through 1023). A response type indicating a 1359 * forwarded interrupt with a qid >= 1K is an 1360 * iWARP async notification. 1361 */ 1362 if (lq >= 1024) { 1363 sc->an_handler(iq, &d->rsp); 1364 break; 1365 } 1366 1367 q = sc->sge.iqmap[lq - sc->sge.iq_start]; 1368 if (atomic_cmpset_int(&q->state, IQS_IDLE, 1369 IQS_BUSY)) { 1370 if (service_iq(q, q->qsize / 16) == 0) { 1371 atomic_cmpset_int(&q->state, 1372 IQS_BUSY, IQS_IDLE); 1373 } else { 1374 STAILQ_INSERT_TAIL(&iql, q, 1375 link); 1376 } 1377 } 1378 break; 1379 1380 default: 1381 KASSERT(0, 1382 ("%s: illegal response type %d on iq %p", 1383 __func__, rsp_type, iq)); 1384 log(LOG_ERR, 1385 "%s: illegal response type %d on iq %p", 1386 device_get_nameunit(sc->dev), rsp_type, iq); 1387 break; 1388 } 1389 1390 d++; 1391 if (__predict_false(++iq->cidx == iq->sidx)) { 1392 iq->cidx = 0; 1393 iq->gen ^= F_RSPD_GEN; 1394 d = &iq->desc[0]; 1395 } 1396 if (__predict_false(++ndescs == limit)) { 1397 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), 1398 V_CIDXINC(ndescs) | 1399 V_INGRESSQID(iq->cntxt_id) | 1400 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); 1401 ndescs = 0; 1402 1403 #if defined(INET) || defined(INET6) 1404 if (iq->flags & IQ_LRO_ENABLED && 1405 sc->lro_timeout != 0) { 1406 tcp_lro_flush_inactive(&rxq->lro, 1407 &lro_timeout); 1408 } 1409 #endif 1410 1411 if (budget) { 1412 if (iq->flags & IQ_HAS_FL) { 1413 FL_LOCK(fl); 1414 refill_fl(sc, fl, 32); 1415 FL_UNLOCK(fl); 1416 } 1417 return (EINPROGRESS); 1418 } 1419 } 1420 if (refill) { 1421 FL_LOCK(fl); 1422 refill_fl(sc, fl, 32); 1423 FL_UNLOCK(fl); 1424 fl_hw_cidx = fl->hw_cidx; 1425 } 1426 } 1427 1428 process_iql: 1429 if (STAILQ_EMPTY(&iql)) 1430 break; 1431 1432 /* 1433 * Process the head only, and send it to the back of the list if 1434 * it's still not done. 1435 */ 1436 q = STAILQ_FIRST(&iql); 1437 STAILQ_REMOVE_HEAD(&iql, link); 1438 if (service_iq(q, q->qsize / 8) == 0) 1439 atomic_cmpset_int(&q->state, IQS_BUSY, IQS_IDLE); 1440 else 1441 STAILQ_INSERT_TAIL(&iql, q, link); 1442 } 1443 1444 #if defined(INET) || defined(INET6) 1445 if (iq->flags & IQ_LRO_ENABLED) { 1446 struct lro_ctrl *lro = &rxq->lro; 1447 struct lro_entry *l; 1448 1449 while (!SLIST_EMPTY(&lro->lro_active)) { 1450 l = SLIST_FIRST(&lro->lro_active); 1451 SLIST_REMOVE_HEAD(&lro->lro_active, next); 1452 tcp_lro_flush(lro, l); 1453 } 1454 } 1455 #endif 1456 1457 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), V_CIDXINC(ndescs) | 1458 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params)); 1459 1460 if (iq->flags & IQ_HAS_FL) { 1461 int starved; 1462 1463 FL_LOCK(fl); 1464 starved = refill_fl(sc, fl, 64); 1465 FL_UNLOCK(fl); 1466 if (__predict_false(starved != 0)) 1467 add_fl_to_sfl(sc, fl); 1468 } 1469 1470 return (0); 1471 } 1472 1473 static inline int 1474 cl_has_metadata(struct sge_fl *fl, struct cluster_layout *cll) 1475 { 1476 int rc = fl->flags & FL_BUF_PACKING || cll->region1 > 0; 1477 1478 if (rc) 1479 MPASS(cll->region3 >= CL_METADATA_SIZE); 1480 1481 return (rc); 1482 } 1483 1484 static inline struct cluster_metadata * 1485 cl_metadata(struct adapter *sc, struct sge_fl *fl, struct cluster_layout *cll, 1486 caddr_t cl) 1487 { 1488 1489 if (cl_has_metadata(fl, cll)) { 1490 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx]; 1491 1492 return ((struct cluster_metadata *)(cl + swz->size) - 1); 1493 } 1494 return (NULL); 1495 } 1496 1497 static void 1498 rxb_free(struct mbuf *m, void *arg1, void *arg2) 1499 { 1500 uma_zone_t zone = arg1; 1501 caddr_t cl = arg2; 1502 1503 uma_zfree(zone, cl); 1504 counter_u64_add(extfree_rels, 1); 1505 } 1506 1507 /* 1508 * The mbuf returned by this function could be allocated from zone_mbuf or 1509 * constructed in spare room in the cluster. 1510 * 1511 * The mbuf carries the payload in one of these ways 1512 * a) frame inside the mbuf (mbuf from zone_mbuf) 1513 * b) m_cljset (for clusters without metadata) zone_mbuf 1514 * c) m_extaddref (cluster with metadata) inline mbuf 1515 * d) m_extaddref (cluster with metadata) zone_mbuf 1516 */ 1517 static struct mbuf * 1518 get_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset, 1519 int remaining) 1520 { 1521 struct mbuf *m; 1522 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 1523 struct cluster_layout *cll = &sd->cll; 1524 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx]; 1525 struct hw_buf_info *hwb = &sc->sge.hw_buf_info[cll->hwidx]; 1526 struct cluster_metadata *clm = cl_metadata(sc, fl, cll, sd->cl); 1527 int len, blen; 1528 caddr_t payload; 1529 1530 blen = hwb->size - fl->rx_offset; /* max possible in this buf */ 1531 len = min(remaining, blen); 1532 payload = sd->cl + cll->region1 + fl->rx_offset; 1533 if (fl->flags & FL_BUF_PACKING) { 1534 const u_int l = fr_offset + len; 1535 const u_int pad = roundup2(l, fl->buf_boundary) - l; 1536 1537 if (fl->rx_offset + len + pad < hwb->size) 1538 blen = len + pad; 1539 MPASS(fl->rx_offset + blen <= hwb->size); 1540 } else { 1541 MPASS(fl->rx_offset == 0); /* not packing */ 1542 } 1543 1544 1545 if (sc->sc_do_rxcopy && len < RX_COPY_THRESHOLD) { 1546 1547 /* 1548 * Copy payload into a freshly allocated mbuf. 1549 */ 1550 1551 m = fr_offset == 0 ? 1552 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA); 1553 if (m == NULL) 1554 return (NULL); 1555 fl->mbuf_allocated++; 1556 #ifdef T4_PKT_TIMESTAMP 1557 /* Leave room for a timestamp */ 1558 m->m_data += 8; 1559 #endif 1560 /* copy data to mbuf */ 1561 bcopy(payload, mtod(m, caddr_t), len); 1562 1563 } else if (sd->nmbuf * MSIZE < cll->region1) { 1564 1565 /* 1566 * There's spare room in the cluster for an mbuf. Create one 1567 * and associate it with the payload that's in the cluster. 1568 */ 1569 1570 MPASS(clm != NULL); 1571 m = (struct mbuf *)(sd->cl + sd->nmbuf * MSIZE); 1572 /* No bzero required */ 1573 if (m_init(m, M_NOWAIT, MT_DATA, 1574 fr_offset == 0 ? M_PKTHDR | M_NOFREE : M_NOFREE)) 1575 return (NULL); 1576 fl->mbuf_inlined++; 1577 m_extaddref(m, payload, blen, &clm->refcount, rxb_free, 1578 swz->zone, sd->cl); 1579 if (sd->nmbuf++ == 0) 1580 counter_u64_add(extfree_refs, 1); 1581 1582 } else { 1583 1584 /* 1585 * Grab an mbuf from zone_mbuf and associate it with the 1586 * payload in the cluster. 1587 */ 1588 1589 m = fr_offset == 0 ? 1590 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA); 1591 if (m == NULL) 1592 return (NULL); 1593 fl->mbuf_allocated++; 1594 if (clm != NULL) { 1595 m_extaddref(m, payload, blen, &clm->refcount, 1596 rxb_free, swz->zone, sd->cl); 1597 if (sd->nmbuf++ == 0) 1598 counter_u64_add(extfree_refs, 1); 1599 } else { 1600 m_cljset(m, sd->cl, swz->type); 1601 sd->cl = NULL; /* consumed, not a recycle candidate */ 1602 } 1603 } 1604 if (fr_offset == 0) 1605 m->m_pkthdr.len = remaining; 1606 m->m_len = len; 1607 1608 if (fl->flags & FL_BUF_PACKING) { 1609 fl->rx_offset += blen; 1610 MPASS(fl->rx_offset <= hwb->size); 1611 if (fl->rx_offset < hwb->size) 1612 return (m); /* without advancing the cidx */ 1613 } 1614 1615 if (__predict_false(++fl->cidx % 8 == 0)) { 1616 uint16_t cidx = fl->cidx / 8; 1617 1618 if (__predict_false(cidx == fl->sidx)) 1619 fl->cidx = cidx = 0; 1620 fl->hw_cidx = cidx; 1621 } 1622 fl->rx_offset = 0; 1623 1624 return (m); 1625 } 1626 1627 static struct mbuf * 1628 get_fl_payload(struct adapter *sc, struct sge_fl *fl, uint32_t len_newbuf) 1629 { 1630 struct mbuf *m0, *m, **pnext; 1631 u_int remaining; 1632 const u_int total = G_RSPD_LEN(len_newbuf); 1633 1634 if (__predict_false(fl->flags & FL_BUF_RESUME)) { 1635 M_ASSERTPKTHDR(fl->m0); 1636 MPASS(fl->m0->m_pkthdr.len == total); 1637 MPASS(fl->remaining < total); 1638 1639 m0 = fl->m0; 1640 pnext = fl->pnext; 1641 remaining = fl->remaining; 1642 fl->flags &= ~FL_BUF_RESUME; 1643 goto get_segment; 1644 } 1645 1646 if (fl->rx_offset > 0 && len_newbuf & F_RSPD_NEWBUF) { 1647 fl->rx_offset = 0; 1648 if (__predict_false(++fl->cidx % 8 == 0)) { 1649 uint16_t cidx = fl->cidx / 8; 1650 1651 if (__predict_false(cidx == fl->sidx)) 1652 fl->cidx = cidx = 0; 1653 fl->hw_cidx = cidx; 1654 } 1655 } 1656 1657 /* 1658 * Payload starts at rx_offset in the current hw buffer. Its length is 1659 * 'len' and it may span multiple hw buffers. 1660 */ 1661 1662 m0 = get_scatter_segment(sc, fl, 0, total); 1663 if (m0 == NULL) 1664 return (NULL); 1665 remaining = total - m0->m_len; 1666 pnext = &m0->m_next; 1667 while (remaining > 0) { 1668 get_segment: 1669 MPASS(fl->rx_offset == 0); 1670 m = get_scatter_segment(sc, fl, total - remaining, remaining); 1671 if (__predict_false(m == NULL)) { 1672 fl->m0 = m0; 1673 fl->pnext = pnext; 1674 fl->remaining = remaining; 1675 fl->flags |= FL_BUF_RESUME; 1676 return (NULL); 1677 } 1678 *pnext = m; 1679 pnext = &m->m_next; 1680 remaining -= m->m_len; 1681 } 1682 *pnext = NULL; 1683 1684 M_ASSERTPKTHDR(m0); 1685 return (m0); 1686 } 1687 1688 static int 1689 t4_eth_rx(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0) 1690 { 1691 struct sge_rxq *rxq = iq_to_rxq(iq); 1692 struct ifnet *ifp = rxq->ifp; 1693 const struct cpl_rx_pkt *cpl = (const void *)(rss + 1); 1694 #if defined(INET) || defined(INET6) 1695 struct lro_ctrl *lro = &rxq->lro; 1696 #endif 1697 static const int sw_hashtype[4][2] = { 1698 {M_HASHTYPE_NONE, M_HASHTYPE_NONE}, 1699 {M_HASHTYPE_RSS_IPV4, M_HASHTYPE_RSS_IPV6}, 1700 {M_HASHTYPE_RSS_TCP_IPV4, M_HASHTYPE_RSS_TCP_IPV6}, 1701 {M_HASHTYPE_RSS_UDP_IPV4, M_HASHTYPE_RSS_UDP_IPV6}, 1702 }; 1703 1704 KASSERT(m0 != NULL, ("%s: no payload with opcode %02x", __func__, 1705 rss->opcode)); 1706 1707 m0->m_pkthdr.len -= fl_pktshift; 1708 m0->m_len -= fl_pktshift; 1709 m0->m_data += fl_pktshift; 1710 1711 m0->m_pkthdr.rcvif = ifp; 1712 M_HASHTYPE_SET(m0, sw_hashtype[rss->hash_type][rss->ipv6]); 1713 m0->m_pkthdr.flowid = be32toh(rss->hash_val); 1714 1715 if (cpl->csum_calc && !cpl->err_vec) { 1716 if (ifp->if_capenable & IFCAP_RXCSUM && 1717 cpl->l2info & htobe32(F_RXF_IP)) { 1718 m0->m_pkthdr.csum_flags = (CSUM_IP_CHECKED | 1719 CSUM_IP_VALID | CSUM_DATA_VALID | CSUM_PSEUDO_HDR); 1720 rxq->rxcsum++; 1721 } else if (ifp->if_capenable & IFCAP_RXCSUM_IPV6 && 1722 cpl->l2info & htobe32(F_RXF_IP6)) { 1723 m0->m_pkthdr.csum_flags = (CSUM_DATA_VALID_IPV6 | 1724 CSUM_PSEUDO_HDR); 1725 rxq->rxcsum++; 1726 } 1727 1728 if (__predict_false(cpl->ip_frag)) 1729 m0->m_pkthdr.csum_data = be16toh(cpl->csum); 1730 else 1731 m0->m_pkthdr.csum_data = 0xffff; 1732 } 1733 1734 if (cpl->vlan_ex) { 1735 m0->m_pkthdr.ether_vtag = be16toh(cpl->vlan); 1736 m0->m_flags |= M_VLANTAG; 1737 rxq->vlan_extraction++; 1738 } 1739 1740 #if defined(INET) || defined(INET6) 1741 if (cpl->l2info & htobe32(F_RXF_LRO) && 1742 iq->flags & IQ_LRO_ENABLED && 1743 tcp_lro_rx(lro, m0, 0) == 0) { 1744 /* queued for LRO */ 1745 } else 1746 #endif 1747 ifp->if_input(ifp, m0); 1748 1749 return (0); 1750 } 1751 1752 /* 1753 * Must drain the wrq or make sure that someone else will. 1754 */ 1755 static void 1756 wrq_tx_drain(void *arg, int n) 1757 { 1758 struct sge_wrq *wrq = arg; 1759 struct sge_eq *eq = &wrq->eq; 1760 1761 EQ_LOCK(eq); 1762 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 1763 drain_wrq_wr_list(wrq->adapter, wrq); 1764 EQ_UNLOCK(eq); 1765 } 1766 1767 static void 1768 drain_wrq_wr_list(struct adapter *sc, struct sge_wrq *wrq) 1769 { 1770 struct sge_eq *eq = &wrq->eq; 1771 u_int available, dbdiff; /* # of hardware descriptors */ 1772 u_int n; 1773 struct wrqe *wr; 1774 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */ 1775 1776 EQ_LOCK_ASSERT_OWNED(eq); 1777 MPASS(TAILQ_EMPTY(&wrq->incomplete_wrs)); 1778 wr = STAILQ_FIRST(&wrq->wr_list); 1779 MPASS(wr != NULL); /* Must be called with something useful to do */ 1780 dbdiff = IDXDIFF(eq->pidx, eq->dbidx, eq->sidx); 1781 1782 do { 1783 eq->cidx = read_hw_cidx(eq); 1784 if (eq->pidx == eq->cidx) 1785 available = eq->sidx - 1; 1786 else 1787 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 1788 1789 MPASS(wr->wrq == wrq); 1790 n = howmany(wr->wr_len, EQ_ESIZE); 1791 if (available < n) 1792 return; 1793 1794 dst = (void *)&eq->desc[eq->pidx]; 1795 if (__predict_true(eq->sidx - eq->pidx > n)) { 1796 /* Won't wrap, won't end exactly at the status page. */ 1797 bcopy(&wr->wr[0], dst, wr->wr_len); 1798 eq->pidx += n; 1799 } else { 1800 int first_portion = (eq->sidx - eq->pidx) * EQ_ESIZE; 1801 1802 bcopy(&wr->wr[0], dst, first_portion); 1803 if (wr->wr_len > first_portion) { 1804 bcopy(&wr->wr[first_portion], &eq->desc[0], 1805 wr->wr_len - first_portion); 1806 } 1807 eq->pidx = n - (eq->sidx - eq->pidx); 1808 } 1809 1810 if (available < eq->sidx / 4 && 1811 atomic_cmpset_int(&eq->equiq, 0, 1)) { 1812 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ | 1813 F_FW_WR_EQUEQ); 1814 eq->equeqidx = eq->pidx; 1815 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 32) { 1816 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ); 1817 eq->equeqidx = eq->pidx; 1818 } 1819 1820 dbdiff += n; 1821 if (dbdiff >= 16) { 1822 ring_eq_db(sc, eq, dbdiff); 1823 dbdiff = 0; 1824 } 1825 1826 STAILQ_REMOVE_HEAD(&wrq->wr_list, link); 1827 free_wrqe(wr); 1828 MPASS(wrq->nwr_pending > 0); 1829 wrq->nwr_pending--; 1830 MPASS(wrq->ndesc_needed >= n); 1831 wrq->ndesc_needed -= n; 1832 } while ((wr = STAILQ_FIRST(&wrq->wr_list)) != NULL); 1833 1834 if (dbdiff) 1835 ring_eq_db(sc, eq, dbdiff); 1836 } 1837 1838 /* 1839 * Doesn't fail. Holds on to work requests it can't send right away. 1840 */ 1841 void 1842 t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, struct wrqe *wr) 1843 { 1844 #ifdef INVARIANTS 1845 struct sge_eq *eq = &wrq->eq; 1846 #endif 1847 1848 EQ_LOCK_ASSERT_OWNED(eq); 1849 MPASS(wr != NULL); 1850 MPASS(wr->wr_len > 0 && wr->wr_len <= SGE_MAX_WR_LEN); 1851 MPASS((wr->wr_len & 0x7) == 0); 1852 1853 STAILQ_INSERT_TAIL(&wrq->wr_list, wr, link); 1854 wrq->nwr_pending++; 1855 wrq->ndesc_needed += howmany(wr->wr_len, EQ_ESIZE); 1856 1857 if (!TAILQ_EMPTY(&wrq->incomplete_wrs)) 1858 return; /* commit_wrq_wr will drain wr_list as well. */ 1859 1860 drain_wrq_wr_list(sc, wrq); 1861 1862 /* Doorbell must have caught up to the pidx. */ 1863 MPASS(eq->pidx == eq->dbidx); 1864 } 1865 1866 void 1867 t4_update_fl_bufsize(struct ifnet *ifp) 1868 { 1869 struct vi_info *vi = ifp->if_softc; 1870 struct adapter *sc = vi->pi->adapter; 1871 struct sge_rxq *rxq; 1872 #ifdef TCP_OFFLOAD 1873 struct sge_ofld_rxq *ofld_rxq; 1874 #endif 1875 struct sge_fl *fl; 1876 int i, maxp, mtu = ifp->if_mtu; 1877 1878 maxp = mtu_to_max_payload(sc, mtu, 0); 1879 for_each_rxq(vi, i, rxq) { 1880 fl = &rxq->fl; 1881 1882 FL_LOCK(fl); 1883 find_best_refill_source(sc, fl, maxp); 1884 FL_UNLOCK(fl); 1885 } 1886 #ifdef TCP_OFFLOAD 1887 maxp = mtu_to_max_payload(sc, mtu, 1); 1888 for_each_ofld_rxq(vi, i, ofld_rxq) { 1889 fl = &ofld_rxq->fl; 1890 1891 FL_LOCK(fl); 1892 find_best_refill_source(sc, fl, maxp); 1893 FL_UNLOCK(fl); 1894 } 1895 #endif 1896 } 1897 1898 static inline int 1899 mbuf_nsegs(struct mbuf *m) 1900 { 1901 1902 M_ASSERTPKTHDR(m); 1903 KASSERT(m->m_pkthdr.l5hlen > 0, 1904 ("%s: mbuf %p missing information on # of segments.", __func__, m)); 1905 1906 return (m->m_pkthdr.l5hlen); 1907 } 1908 1909 static inline void 1910 set_mbuf_nsegs(struct mbuf *m, uint8_t nsegs) 1911 { 1912 1913 M_ASSERTPKTHDR(m); 1914 m->m_pkthdr.l5hlen = nsegs; 1915 } 1916 1917 static inline int 1918 mbuf_len16(struct mbuf *m) 1919 { 1920 int n; 1921 1922 M_ASSERTPKTHDR(m); 1923 n = m->m_pkthdr.PH_loc.eight[0]; 1924 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16); 1925 1926 return (n); 1927 } 1928 1929 static inline void 1930 set_mbuf_len16(struct mbuf *m, uint8_t len16) 1931 { 1932 1933 M_ASSERTPKTHDR(m); 1934 m->m_pkthdr.PH_loc.eight[0] = len16; 1935 } 1936 1937 static inline int 1938 needs_tso(struct mbuf *m) 1939 { 1940 1941 M_ASSERTPKTHDR(m); 1942 1943 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 1944 KASSERT(m->m_pkthdr.tso_segsz > 0, 1945 ("%s: TSO requested in mbuf %p but MSS not provided", 1946 __func__, m)); 1947 return (1); 1948 } 1949 1950 return (0); 1951 } 1952 1953 static inline int 1954 needs_l3_csum(struct mbuf *m) 1955 { 1956 1957 M_ASSERTPKTHDR(m); 1958 1959 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TSO)) 1960 return (1); 1961 return (0); 1962 } 1963 1964 static inline int 1965 needs_l4_csum(struct mbuf *m) 1966 { 1967 1968 M_ASSERTPKTHDR(m); 1969 1970 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_UDP_IPV6 | 1971 CSUM_TCP_IPV6 | CSUM_TSO)) 1972 return (1); 1973 return (0); 1974 } 1975 1976 static inline int 1977 needs_vlan_insertion(struct mbuf *m) 1978 { 1979 1980 M_ASSERTPKTHDR(m); 1981 1982 if (m->m_flags & M_VLANTAG) { 1983 KASSERT(m->m_pkthdr.ether_vtag != 0, 1984 ("%s: HWVLAN requested in mbuf %p but tag not provided", 1985 __func__, m)); 1986 return (1); 1987 } 1988 return (0); 1989 } 1990 1991 static void * 1992 m_advance(struct mbuf **pm, int *poffset, int len) 1993 { 1994 struct mbuf *m = *pm; 1995 int offset = *poffset; 1996 uintptr_t p = 0; 1997 1998 MPASS(len > 0); 1999 2000 while (len) { 2001 if (offset + len < m->m_len) { 2002 offset += len; 2003 p = mtod(m, uintptr_t) + offset; 2004 break; 2005 } 2006 len -= m->m_len - offset; 2007 m = m->m_next; 2008 offset = 0; 2009 MPASS(m != NULL); 2010 } 2011 *poffset = offset; 2012 *pm = m; 2013 return ((void *)p); 2014 } 2015 2016 static inline int 2017 same_paddr(char *a, char *b) 2018 { 2019 2020 if (a == b) 2021 return (1); 2022 else if (a != NULL && b != NULL) { 2023 vm_offset_t x = (vm_offset_t)a; 2024 vm_offset_t y = (vm_offset_t)b; 2025 2026 if ((x & PAGE_MASK) == (y & PAGE_MASK) && 2027 pmap_kextract(x) == pmap_kextract(y)) 2028 return (1); 2029 } 2030 2031 return (0); 2032 } 2033 2034 /* 2035 * Can deal with empty mbufs in the chain that have m_len = 0, but the chain 2036 * must have at least one mbuf that's not empty. 2037 */ 2038 static inline int 2039 count_mbuf_nsegs(struct mbuf *m) 2040 { 2041 char *prev_end, *start; 2042 int len, nsegs; 2043 2044 MPASS(m != NULL); 2045 2046 nsegs = 0; 2047 prev_end = NULL; 2048 for (; m; m = m->m_next) { 2049 2050 len = m->m_len; 2051 if (__predict_false(len == 0)) 2052 continue; 2053 start = mtod(m, char *); 2054 2055 nsegs += sglist_count(start, len); 2056 if (same_paddr(prev_end, start)) 2057 nsegs--; 2058 prev_end = start + len; 2059 } 2060 2061 MPASS(nsegs > 0); 2062 return (nsegs); 2063 } 2064 2065 /* 2066 * Analyze the mbuf to determine its tx needs. The mbuf passed in may change: 2067 * a) caller can assume it's been freed if this function returns with an error. 2068 * b) it may get defragged up if the gather list is too long for the hardware. 2069 */ 2070 int 2071 parse_pkt(struct mbuf **mp) 2072 { 2073 struct mbuf *m0 = *mp, *m; 2074 int rc, nsegs, defragged = 0, offset; 2075 struct ether_header *eh; 2076 void *l3hdr; 2077 #if defined(INET) || defined(INET6) 2078 struct tcphdr *tcp; 2079 #endif 2080 uint16_t eh_type; 2081 2082 M_ASSERTPKTHDR(m0); 2083 if (__predict_false(m0->m_pkthdr.len < ETHER_HDR_LEN)) { 2084 rc = EINVAL; 2085 fail: 2086 m_freem(m0); 2087 *mp = NULL; 2088 return (rc); 2089 } 2090 restart: 2091 /* 2092 * First count the number of gather list segments in the payload. 2093 * Defrag the mbuf if nsegs exceeds the hardware limit. 2094 */ 2095 M_ASSERTPKTHDR(m0); 2096 MPASS(m0->m_pkthdr.len > 0); 2097 nsegs = count_mbuf_nsegs(m0); 2098 if (nsegs > (needs_tso(m0) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS)) { 2099 if (defragged++ > 0 || (m = m_defrag(m0, M_NOWAIT)) == NULL) { 2100 rc = EFBIG; 2101 goto fail; 2102 } 2103 *mp = m0 = m; /* update caller's copy after defrag */ 2104 goto restart; 2105 } 2106 2107 if (__predict_false(nsegs > 2 && m0->m_pkthdr.len <= MHLEN)) { 2108 m0 = m_pullup(m0, m0->m_pkthdr.len); 2109 if (m0 == NULL) { 2110 /* Should have left well enough alone. */ 2111 rc = EFBIG; 2112 goto fail; 2113 } 2114 *mp = m0; /* update caller's copy after pullup */ 2115 goto restart; 2116 } 2117 set_mbuf_nsegs(m0, nsegs); 2118 set_mbuf_len16(m0, txpkt_len16(nsegs, needs_tso(m0))); 2119 2120 if (!needs_tso(m0)) 2121 return (0); 2122 2123 m = m0; 2124 eh = mtod(m, struct ether_header *); 2125 eh_type = ntohs(eh->ether_type); 2126 if (eh_type == ETHERTYPE_VLAN) { 2127 struct ether_vlan_header *evh = (void *)eh; 2128 2129 eh_type = ntohs(evh->evl_proto); 2130 m0->m_pkthdr.l2hlen = sizeof(*evh); 2131 } else 2132 m0->m_pkthdr.l2hlen = sizeof(*eh); 2133 2134 offset = 0; 2135 l3hdr = m_advance(&m, &offset, m0->m_pkthdr.l2hlen); 2136 2137 switch (eh_type) { 2138 #ifdef INET6 2139 case ETHERTYPE_IPV6: 2140 { 2141 struct ip6_hdr *ip6 = l3hdr; 2142 2143 MPASS(ip6->ip6_nxt == IPPROTO_TCP); 2144 2145 m0->m_pkthdr.l3hlen = sizeof(*ip6); 2146 break; 2147 } 2148 #endif 2149 #ifdef INET 2150 case ETHERTYPE_IP: 2151 { 2152 struct ip *ip = l3hdr; 2153 2154 m0->m_pkthdr.l3hlen = ip->ip_hl * 4; 2155 break; 2156 } 2157 #endif 2158 default: 2159 panic("%s: ethertype 0x%04x unknown. if_cxgbe must be compiled" 2160 " with the same INET/INET6 options as the kernel.", 2161 __func__, eh_type); 2162 } 2163 2164 #if defined(INET) || defined(INET6) 2165 tcp = m_advance(&m, &offset, m0->m_pkthdr.l3hlen); 2166 m0->m_pkthdr.l4hlen = tcp->th_off * 4; 2167 #endif 2168 MPASS(m0 == *mp); 2169 return (0); 2170 } 2171 2172 void * 2173 start_wrq_wr(struct sge_wrq *wrq, int len16, struct wrq_cookie *cookie) 2174 { 2175 struct sge_eq *eq = &wrq->eq; 2176 struct adapter *sc = wrq->adapter; 2177 int ndesc, available; 2178 struct wrqe *wr; 2179 void *w; 2180 2181 MPASS(len16 > 0); 2182 ndesc = howmany(len16, EQ_ESIZE / 16); 2183 MPASS(ndesc > 0 && ndesc <= SGE_MAX_WR_NDESC); 2184 2185 EQ_LOCK(eq); 2186 2187 if (!STAILQ_EMPTY(&wrq->wr_list)) 2188 drain_wrq_wr_list(sc, wrq); 2189 2190 if (!STAILQ_EMPTY(&wrq->wr_list)) { 2191 slowpath: 2192 EQ_UNLOCK(eq); 2193 wr = alloc_wrqe(len16 * 16, wrq); 2194 if (__predict_false(wr == NULL)) 2195 return (NULL); 2196 cookie->pidx = -1; 2197 cookie->ndesc = ndesc; 2198 return (&wr->wr); 2199 } 2200 2201 eq->cidx = read_hw_cidx(eq); 2202 if (eq->pidx == eq->cidx) 2203 available = eq->sidx - 1; 2204 else 2205 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2206 if (available < ndesc) 2207 goto slowpath; 2208 2209 cookie->pidx = eq->pidx; 2210 cookie->ndesc = ndesc; 2211 TAILQ_INSERT_TAIL(&wrq->incomplete_wrs, cookie, link); 2212 2213 w = &eq->desc[eq->pidx]; 2214 IDXINCR(eq->pidx, ndesc, eq->sidx); 2215 if (__predict_false(eq->pidx < ndesc - 1)) { 2216 w = &wrq->ss[0]; 2217 wrq->ss_pidx = cookie->pidx; 2218 wrq->ss_len = len16 * 16; 2219 } 2220 2221 EQ_UNLOCK(eq); 2222 2223 return (w); 2224 } 2225 2226 void 2227 commit_wrq_wr(struct sge_wrq *wrq, void *w, struct wrq_cookie *cookie) 2228 { 2229 struct sge_eq *eq = &wrq->eq; 2230 struct adapter *sc = wrq->adapter; 2231 int ndesc, pidx; 2232 struct wrq_cookie *prev, *next; 2233 2234 if (cookie->pidx == -1) { 2235 struct wrqe *wr = __containerof(w, struct wrqe, wr); 2236 2237 t4_wrq_tx(sc, wr); 2238 return; 2239 } 2240 2241 ndesc = cookie->ndesc; /* Can be more than SGE_MAX_WR_NDESC here. */ 2242 pidx = cookie->pidx; 2243 MPASS(pidx >= 0 && pidx < eq->sidx); 2244 if (__predict_false(w == &wrq->ss[0])) { 2245 int n = (eq->sidx - wrq->ss_pidx) * EQ_ESIZE; 2246 2247 MPASS(wrq->ss_len > n); /* WR had better wrap around. */ 2248 bcopy(&wrq->ss[0], &eq->desc[wrq->ss_pidx], n); 2249 bcopy(&wrq->ss[n], &eq->desc[0], wrq->ss_len - n); 2250 wrq->tx_wrs_ss++; 2251 } else 2252 wrq->tx_wrs_direct++; 2253 2254 EQ_LOCK(eq); 2255 prev = TAILQ_PREV(cookie, wrq_incomplete_wrs, link); 2256 next = TAILQ_NEXT(cookie, link); 2257 if (prev == NULL) { 2258 MPASS(pidx == eq->dbidx); 2259 if (next == NULL || ndesc >= 16) 2260 ring_eq_db(wrq->adapter, eq, ndesc); 2261 else { 2262 MPASS(IDXDIFF(next->pidx, pidx, eq->sidx) == ndesc); 2263 next->pidx = pidx; 2264 next->ndesc += ndesc; 2265 } 2266 } else { 2267 MPASS(IDXDIFF(pidx, prev->pidx, eq->sidx) == prev->ndesc); 2268 prev->ndesc += ndesc; 2269 } 2270 TAILQ_REMOVE(&wrq->incomplete_wrs, cookie, link); 2271 2272 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 2273 drain_wrq_wr_list(sc, wrq); 2274 2275 #ifdef INVARIANTS 2276 if (TAILQ_EMPTY(&wrq->incomplete_wrs)) { 2277 /* Doorbell must have caught up to the pidx. */ 2278 MPASS(wrq->eq.pidx == wrq->eq.dbidx); 2279 } 2280 #endif 2281 EQ_UNLOCK(eq); 2282 } 2283 2284 static u_int 2285 can_resume_eth_tx(struct mp_ring *r) 2286 { 2287 struct sge_eq *eq = r->cookie; 2288 2289 return (total_available_tx_desc(eq) > eq->sidx / 8); 2290 } 2291 2292 static inline int 2293 cannot_use_txpkts(struct mbuf *m) 2294 { 2295 /* maybe put a GL limit too, to avoid silliness? */ 2296 2297 return (needs_tso(m)); 2298 } 2299 2300 /* 2301 * r->items[cidx] to r->items[pidx], with a wraparound at r->size, are ready to 2302 * be consumed. Return the actual number consumed. 0 indicates a stall. 2303 */ 2304 static u_int 2305 eth_tx(struct mp_ring *r, u_int cidx, u_int pidx) 2306 { 2307 struct sge_txq *txq = r->cookie; 2308 struct sge_eq *eq = &txq->eq; 2309 struct ifnet *ifp = txq->ifp; 2310 struct vi_info *vi = ifp->if_softc; 2311 struct port_info *pi = vi->pi; 2312 struct adapter *sc = pi->adapter; 2313 u_int total, remaining; /* # of packets */ 2314 u_int available, dbdiff; /* # of hardware descriptors */ 2315 u_int n, next_cidx; 2316 struct mbuf *m0, *tail; 2317 struct txpkts txp; 2318 struct fw_eth_tx_pkts_wr *wr; /* any fw WR struct will do */ 2319 2320 remaining = IDXDIFF(pidx, cidx, r->size); 2321 MPASS(remaining > 0); /* Must not be called without work to do. */ 2322 total = 0; 2323 2324 TXQ_LOCK(txq); 2325 if (__predict_false((eq->flags & EQ_ENABLED) == 0)) { 2326 while (cidx != pidx) { 2327 m0 = r->items[cidx]; 2328 m_freem(m0); 2329 if (++cidx == r->size) 2330 cidx = 0; 2331 } 2332 reclaim_tx_descs(txq, 2048); 2333 total = remaining; 2334 goto done; 2335 } 2336 2337 /* How many hardware descriptors do we have readily available. */ 2338 if (eq->pidx == eq->cidx) 2339 available = eq->sidx - 1; 2340 else 2341 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2342 dbdiff = IDXDIFF(eq->pidx, eq->dbidx, eq->sidx); 2343 2344 while (remaining > 0) { 2345 2346 m0 = r->items[cidx]; 2347 M_ASSERTPKTHDR(m0); 2348 MPASS(m0->m_nextpkt == NULL); 2349 2350 if (available < SGE_MAX_WR_NDESC) { 2351 available += reclaim_tx_descs(txq, 64); 2352 if (available < howmany(mbuf_len16(m0), EQ_ESIZE / 16)) 2353 break; /* out of descriptors */ 2354 } 2355 2356 next_cidx = cidx + 1; 2357 if (__predict_false(next_cidx == r->size)) 2358 next_cidx = 0; 2359 2360 wr = (void *)&eq->desc[eq->pidx]; 2361 if (remaining > 1 && 2362 try_txpkts(m0, r->items[next_cidx], &txp, available) == 0) { 2363 2364 /* pkts at cidx, next_cidx should both be in txp. */ 2365 MPASS(txp.npkt == 2); 2366 tail = r->items[next_cidx]; 2367 MPASS(tail->m_nextpkt == NULL); 2368 ETHER_BPF_MTAP(ifp, m0); 2369 ETHER_BPF_MTAP(ifp, tail); 2370 m0->m_nextpkt = tail; 2371 2372 if (__predict_false(++next_cidx == r->size)) 2373 next_cidx = 0; 2374 2375 while (next_cidx != pidx) { 2376 if (add_to_txpkts(r->items[next_cidx], &txp, 2377 available) != 0) 2378 break; 2379 tail->m_nextpkt = r->items[next_cidx]; 2380 tail = tail->m_nextpkt; 2381 ETHER_BPF_MTAP(ifp, tail); 2382 if (__predict_false(++next_cidx == r->size)) 2383 next_cidx = 0; 2384 } 2385 2386 n = write_txpkts_wr(txq, wr, m0, &txp, available); 2387 total += txp.npkt; 2388 remaining -= txp.npkt; 2389 } else { 2390 total++; 2391 remaining--; 2392 n = write_txpkt_wr(txq, (void *)wr, m0, available); 2393 ETHER_BPF_MTAP(ifp, m0); 2394 } 2395 MPASS(n >= 1 && n <= available && n <= SGE_MAX_WR_NDESC); 2396 2397 available -= n; 2398 dbdiff += n; 2399 IDXINCR(eq->pidx, n, eq->sidx); 2400 2401 if (total_available_tx_desc(eq) < eq->sidx / 4 && 2402 atomic_cmpset_int(&eq->equiq, 0, 1)) { 2403 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ | 2404 F_FW_WR_EQUEQ); 2405 eq->equeqidx = eq->pidx; 2406 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 32) { 2407 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ); 2408 eq->equeqidx = eq->pidx; 2409 } 2410 2411 if (dbdiff >= 16 && remaining >= 4) { 2412 ring_eq_db(sc, eq, dbdiff); 2413 available += reclaim_tx_descs(txq, 4 * dbdiff); 2414 dbdiff = 0; 2415 } 2416 2417 cidx = next_cidx; 2418 } 2419 if (dbdiff != 0) { 2420 ring_eq_db(sc, eq, dbdiff); 2421 reclaim_tx_descs(txq, 32); 2422 } 2423 done: 2424 TXQ_UNLOCK(txq); 2425 2426 return (total); 2427 } 2428 2429 static inline void 2430 init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int pktc_idx, 2431 int qsize) 2432 { 2433 2434 KASSERT(tmr_idx >= 0 && tmr_idx < SGE_NTIMERS, 2435 ("%s: bad tmr_idx %d", __func__, tmr_idx)); 2436 KASSERT(pktc_idx < SGE_NCOUNTERS, /* -ve is ok, means don't use */ 2437 ("%s: bad pktc_idx %d", __func__, pktc_idx)); 2438 2439 iq->flags = 0; 2440 iq->adapter = sc; 2441 iq->intr_params = V_QINTR_TIMER_IDX(tmr_idx); 2442 iq->intr_pktc_idx = SGE_NCOUNTERS - 1; 2443 if (pktc_idx >= 0) { 2444 iq->intr_params |= F_QINTR_CNT_EN; 2445 iq->intr_pktc_idx = pktc_idx; 2446 } 2447 iq->qsize = roundup2(qsize, 16); /* See FW_IQ_CMD/iqsize */ 2448 iq->sidx = iq->qsize - spg_len / IQ_ESIZE; 2449 } 2450 2451 static inline void 2452 init_fl(struct adapter *sc, struct sge_fl *fl, int qsize, int maxp, char *name) 2453 { 2454 2455 fl->qsize = qsize; 2456 fl->sidx = qsize - spg_len / EQ_ESIZE; 2457 strlcpy(fl->lockname, name, sizeof(fl->lockname)); 2458 if (sc->flags & BUF_PACKING_OK && 2459 ((!is_t4(sc) && buffer_packing) || /* T5+: enabled unless 0 */ 2460 (is_t4(sc) && buffer_packing == 1)))/* T4: disabled unless 1 */ 2461 fl->flags |= FL_BUF_PACKING; 2462 find_best_refill_source(sc, fl, maxp); 2463 find_safe_refill_source(sc, fl); 2464 } 2465 2466 static inline void 2467 init_eq(struct sge_eq *eq, int eqtype, int qsize, uint8_t tx_chan, 2468 uint16_t iqid, char *name) 2469 { 2470 KASSERT(eqtype <= EQ_TYPEMASK, ("%s: bad qtype %d", __func__, eqtype)); 2471 2472 eq->flags = eqtype & EQ_TYPEMASK; 2473 eq->tx_chan = tx_chan; 2474 eq->iqid = iqid; 2475 eq->sidx = qsize - spg_len / EQ_ESIZE; 2476 strlcpy(eq->lockname, name, sizeof(eq->lockname)); 2477 } 2478 2479 static int 2480 alloc_ring(struct adapter *sc, size_t len, bus_dma_tag_t *tag, 2481 bus_dmamap_t *map, bus_addr_t *pa, void **va) 2482 { 2483 int rc; 2484 2485 rc = bus_dma_tag_create(sc->dmat, 512, 0, BUS_SPACE_MAXADDR, 2486 BUS_SPACE_MAXADDR, NULL, NULL, len, 1, len, 0, NULL, NULL, tag); 2487 if (rc != 0) { 2488 device_printf(sc->dev, "cannot allocate DMA tag: %d\n", rc); 2489 goto done; 2490 } 2491 2492 rc = bus_dmamem_alloc(*tag, va, 2493 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, map); 2494 if (rc != 0) { 2495 device_printf(sc->dev, "cannot allocate DMA memory: %d\n", rc); 2496 goto done; 2497 } 2498 2499 rc = bus_dmamap_load(*tag, *map, *va, len, oneseg_dma_callback, pa, 0); 2500 if (rc != 0) { 2501 device_printf(sc->dev, "cannot load DMA map: %d\n", rc); 2502 goto done; 2503 } 2504 done: 2505 if (rc) 2506 free_ring(sc, *tag, *map, *pa, *va); 2507 2508 return (rc); 2509 } 2510 2511 static int 2512 free_ring(struct adapter *sc, bus_dma_tag_t tag, bus_dmamap_t map, 2513 bus_addr_t pa, void *va) 2514 { 2515 if (pa) 2516 bus_dmamap_unload(tag, map); 2517 if (va) 2518 bus_dmamem_free(tag, va, map); 2519 if (tag) 2520 bus_dma_tag_destroy(tag); 2521 2522 return (0); 2523 } 2524 2525 /* 2526 * Allocates the ring for an ingress queue and an optional freelist. If the 2527 * freelist is specified it will be allocated and then associated with the 2528 * ingress queue. 2529 * 2530 * Returns errno on failure. Resources allocated up to that point may still be 2531 * allocated. Caller is responsible for cleanup in case this function fails. 2532 * 2533 * If the ingress queue will take interrupts directly (iq->flags & IQ_INTR) then 2534 * the intr_idx specifies the vector, starting from 0. Otherwise it specifies 2535 * the abs_id of the ingress queue to which its interrupts should be forwarded. 2536 */ 2537 static int 2538 alloc_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl, 2539 int intr_idx, int cong) 2540 { 2541 int rc, i, cntxt_id; 2542 size_t len; 2543 struct fw_iq_cmd c; 2544 struct port_info *pi = vi->pi; 2545 struct adapter *sc = iq->adapter; 2546 __be32 v = 0; 2547 2548 len = iq->qsize * IQ_ESIZE; 2549 rc = alloc_ring(sc, len, &iq->desc_tag, &iq->desc_map, &iq->ba, 2550 (void **)&iq->desc); 2551 if (rc != 0) 2552 return (rc); 2553 2554 bzero(&c, sizeof(c)); 2555 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 2556 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) | 2557 V_FW_IQ_CMD_VFN(0)); 2558 2559 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART | 2560 FW_LEN16(c)); 2561 2562 /* Special handling for firmware event queue */ 2563 if (iq == &sc->sge.fwq) 2564 v |= F_FW_IQ_CMD_IQASYNCH; 2565 2566 if (iq->flags & IQ_INTR) { 2567 KASSERT(intr_idx < sc->intr_count, 2568 ("%s: invalid direct intr_idx %d", __func__, intr_idx)); 2569 } else 2570 v |= F_FW_IQ_CMD_IQANDST; 2571 v |= V_FW_IQ_CMD_IQANDSTINDEX(intr_idx); 2572 2573 c.type_to_iqandstindex = htobe32(v | 2574 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) | 2575 V_FW_IQ_CMD_VIID(vi->viid) | 2576 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT)); 2577 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->tx_chan) | 2578 F_FW_IQ_CMD_IQGTSMODE | 2579 V_FW_IQ_CMD_IQINTCNTTHRESH(iq->intr_pktc_idx) | 2580 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4)); 2581 c.iqsize = htobe16(iq->qsize); 2582 c.iqaddr = htobe64(iq->ba); 2583 if (cong >= 0) 2584 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN); 2585 2586 if (fl) { 2587 mtx_init(&fl->fl_lock, fl->lockname, NULL, MTX_DEF); 2588 2589 len = fl->qsize * EQ_ESIZE; 2590 rc = alloc_ring(sc, len, &fl->desc_tag, &fl->desc_map, 2591 &fl->ba, (void **)&fl->desc); 2592 if (rc) 2593 return (rc); 2594 2595 /* Allocate space for one software descriptor per buffer. */ 2596 rc = alloc_fl_sdesc(fl); 2597 if (rc != 0) { 2598 device_printf(sc->dev, 2599 "failed to setup fl software descriptors: %d\n", 2600 rc); 2601 return (rc); 2602 } 2603 2604 if (fl->flags & FL_BUF_PACKING) { 2605 fl->lowat = roundup2(sc->sge.fl_starve_threshold2, 8); 2606 fl->buf_boundary = sc->sge.pack_boundary; 2607 } else { 2608 fl->lowat = roundup2(sc->sge.fl_starve_threshold, 8); 2609 fl->buf_boundary = 16; 2610 } 2611 if (fl_pad && fl->buf_boundary < sc->sge.pad_boundary) 2612 fl->buf_boundary = sc->sge.pad_boundary; 2613 2614 c.iqns_to_fl0congen |= 2615 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) | 2616 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO | 2617 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) | 2618 (fl->flags & FL_BUF_PACKING ? F_FW_IQ_CMD_FL0PACKEN : 2619 0)); 2620 if (cong >= 0) { 2621 c.iqns_to_fl0congen |= 2622 htobe32(V_FW_IQ_CMD_FL0CNGCHMAP(cong) | 2623 F_FW_IQ_CMD_FL0CONGCIF | 2624 F_FW_IQ_CMD_FL0CONGEN); 2625 } 2626 c.fl0dcaen_to_fl0cidxfthresh = 2627 htobe16(V_FW_IQ_CMD_FL0FBMIN(X_FETCHBURSTMIN_128B) | 2628 V_FW_IQ_CMD_FL0FBMAX(X_FETCHBURSTMAX_512B)); 2629 c.fl0size = htobe16(fl->qsize); 2630 c.fl0addr = htobe64(fl->ba); 2631 } 2632 2633 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 2634 if (rc != 0) { 2635 device_printf(sc->dev, 2636 "failed to create ingress queue: %d\n", rc); 2637 return (rc); 2638 } 2639 2640 iq->cidx = 0; 2641 iq->gen = F_RSPD_GEN; 2642 iq->intr_next = iq->intr_params; 2643 iq->cntxt_id = be16toh(c.iqid); 2644 iq->abs_id = be16toh(c.physiqid); 2645 iq->flags |= IQ_ALLOCATED; 2646 2647 cntxt_id = iq->cntxt_id - sc->sge.iq_start; 2648 if (cntxt_id >= sc->sge.niq) { 2649 panic ("%s: iq->cntxt_id (%d) more than the max (%d)", __func__, 2650 cntxt_id, sc->sge.niq - 1); 2651 } 2652 sc->sge.iqmap[cntxt_id] = iq; 2653 2654 if (fl) { 2655 u_int qid; 2656 2657 iq->flags |= IQ_HAS_FL; 2658 fl->cntxt_id = be16toh(c.fl0id); 2659 fl->pidx = fl->cidx = 0; 2660 2661 cntxt_id = fl->cntxt_id - sc->sge.eq_start; 2662 if (cntxt_id >= sc->sge.neq) { 2663 panic("%s: fl->cntxt_id (%d) more than the max (%d)", 2664 __func__, cntxt_id, sc->sge.neq - 1); 2665 } 2666 sc->sge.eqmap[cntxt_id] = (void *)fl; 2667 2668 qid = fl->cntxt_id; 2669 if (isset(&sc->doorbells, DOORBELL_UDB)) { 2670 uint32_t s_qpp = sc->sge.eq_s_qpp; 2671 uint32_t mask = (1 << s_qpp) - 1; 2672 volatile uint8_t *udb; 2673 2674 udb = sc->udbs_base + UDBS_DB_OFFSET; 2675 udb += (qid >> s_qpp) << PAGE_SHIFT; 2676 qid &= mask; 2677 if (qid < PAGE_SIZE / UDBS_SEG_SIZE) { 2678 udb += qid << UDBS_SEG_SHIFT; 2679 qid = 0; 2680 } 2681 fl->udb = (volatile void *)udb; 2682 } 2683 fl->dbval = V_QID(qid) | sc->chip_params->sge_fl_db; 2684 2685 FL_LOCK(fl); 2686 /* Enough to make sure the SGE doesn't think it's starved */ 2687 refill_fl(sc, fl, fl->lowat); 2688 FL_UNLOCK(fl); 2689 } 2690 2691 if (is_t5(sc) && cong >= 0) { 2692 uint32_t param, val; 2693 2694 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 2695 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) | 2696 V_FW_PARAMS_PARAM_YZ(iq->cntxt_id); 2697 if (cong == 0) 2698 val = 1 << 19; 2699 else { 2700 val = 2 << 19; 2701 for (i = 0; i < 4; i++) { 2702 if (cong & (1 << i)) 2703 val |= 1 << (i << 2); 2704 } 2705 } 2706 2707 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 2708 if (rc != 0) { 2709 /* report error but carry on */ 2710 device_printf(sc->dev, 2711 "failed to set congestion manager context for " 2712 "ingress queue %d: %d\n", iq->cntxt_id, rc); 2713 } 2714 } 2715 2716 /* Enable IQ interrupts */ 2717 atomic_store_rel_int(&iq->state, IQS_IDLE); 2718 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), V_SEINTARM(iq->intr_params) | 2719 V_INGRESSQID(iq->cntxt_id)); 2720 2721 return (0); 2722 } 2723 2724 static int 2725 free_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl) 2726 { 2727 int rc; 2728 struct adapter *sc = iq->adapter; 2729 device_t dev; 2730 2731 if (sc == NULL) 2732 return (0); /* nothing to do */ 2733 2734 dev = vi ? vi->dev : sc->dev; 2735 2736 if (iq->flags & IQ_ALLOCATED) { 2737 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0, 2738 FW_IQ_TYPE_FL_INT_CAP, iq->cntxt_id, 2739 fl ? fl->cntxt_id : 0xffff, 0xffff); 2740 if (rc != 0) { 2741 device_printf(dev, 2742 "failed to free queue %p: %d\n", iq, rc); 2743 return (rc); 2744 } 2745 iq->flags &= ~IQ_ALLOCATED; 2746 } 2747 2748 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, iq->desc); 2749 2750 bzero(iq, sizeof(*iq)); 2751 2752 if (fl) { 2753 free_ring(sc, fl->desc_tag, fl->desc_map, fl->ba, 2754 fl->desc); 2755 2756 if (fl->sdesc) 2757 free_fl_sdesc(sc, fl); 2758 2759 if (mtx_initialized(&fl->fl_lock)) 2760 mtx_destroy(&fl->fl_lock); 2761 2762 bzero(fl, sizeof(*fl)); 2763 } 2764 2765 return (0); 2766 } 2767 2768 static void 2769 add_fl_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid, 2770 struct sge_fl *fl) 2771 { 2772 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 2773 2774 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL, 2775 "freelist"); 2776 children = SYSCTL_CHILDREN(oid); 2777 2778 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 2779 CTLTYPE_INT | CTLFLAG_RD, &fl->cntxt_id, 0, sysctl_uint16, "I", 2780 "SGE context id of the freelist"); 2781 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "padding", CTLFLAG_RD, NULL, 2782 fl_pad ? 1 : 0, "padding enabled"); 2783 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "packing", CTLFLAG_RD, NULL, 2784 fl->flags & FL_BUF_PACKING ? 1 : 0, "packing enabled"); 2785 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &fl->cidx, 2786 0, "consumer index"); 2787 if (fl->flags & FL_BUF_PACKING) { 2788 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rx_offset", 2789 CTLFLAG_RD, &fl->rx_offset, 0, "packing rx offset"); 2790 } 2791 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &fl->pidx, 2792 0, "producer index"); 2793 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_allocated", 2794 CTLFLAG_RD, &fl->mbuf_allocated, "# of mbuf allocated"); 2795 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_inlined", 2796 CTLFLAG_RD, &fl->mbuf_inlined, "# of mbuf inlined in clusters"); 2797 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_allocated", 2798 CTLFLAG_RD, &fl->cl_allocated, "# of clusters allocated"); 2799 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_recycled", 2800 CTLFLAG_RD, &fl->cl_recycled, "# of clusters recycled"); 2801 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_fast_recycled", 2802 CTLFLAG_RD, &fl->cl_fast_recycled, "# of clusters recycled (fast)"); 2803 } 2804 2805 static int 2806 alloc_fwq(struct adapter *sc) 2807 { 2808 int rc, intr_idx; 2809 struct sge_iq *fwq = &sc->sge.fwq; 2810 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev); 2811 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 2812 2813 init_iq(fwq, sc, 0, 0, FW_IQ_QSIZE); 2814 fwq->flags |= IQ_INTR; /* always */ 2815 intr_idx = sc->intr_count > 1 ? 1 : 0; 2816 rc = alloc_iq_fl(&sc->port[0]->vi[0], fwq, NULL, intr_idx, -1); 2817 if (rc != 0) { 2818 device_printf(sc->dev, 2819 "failed to create firmware event queue: %d\n", rc); 2820 return (rc); 2821 } 2822 2823 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "fwq", CTLFLAG_RD, 2824 NULL, "firmware event queue"); 2825 children = SYSCTL_CHILDREN(oid); 2826 2827 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "abs_id", 2828 CTLTYPE_INT | CTLFLAG_RD, &fwq->abs_id, 0, sysctl_uint16, "I", 2829 "absolute id of the queue"); 2830 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "cntxt_id", 2831 CTLTYPE_INT | CTLFLAG_RD, &fwq->cntxt_id, 0, sysctl_uint16, "I", 2832 "SGE context id of the queue"); 2833 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "cidx", 2834 CTLTYPE_INT | CTLFLAG_RD, &fwq->cidx, 0, sysctl_uint16, "I", 2835 "consumer index"); 2836 2837 return (0); 2838 } 2839 2840 static int 2841 free_fwq(struct adapter *sc) 2842 { 2843 return free_iq_fl(NULL, &sc->sge.fwq, NULL); 2844 } 2845 2846 static int 2847 alloc_mgmtq(struct adapter *sc) 2848 { 2849 int rc; 2850 struct sge_wrq *mgmtq = &sc->sge.mgmtq; 2851 char name[16]; 2852 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev); 2853 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 2854 2855 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "mgmtq", CTLFLAG_RD, 2856 NULL, "management queue"); 2857 2858 snprintf(name, sizeof(name), "%s mgmtq", device_get_nameunit(sc->dev)); 2859 init_eq(&mgmtq->eq, EQ_CTRL, CTRL_EQ_QSIZE, sc->port[0]->tx_chan, 2860 sc->sge.fwq.cntxt_id, name); 2861 rc = alloc_wrq(sc, NULL, mgmtq, oid); 2862 if (rc != 0) { 2863 device_printf(sc->dev, 2864 "failed to create management queue: %d\n", rc); 2865 return (rc); 2866 } 2867 2868 return (0); 2869 } 2870 2871 static int 2872 free_mgmtq(struct adapter *sc) 2873 { 2874 2875 return free_wrq(sc, &sc->sge.mgmtq); 2876 } 2877 2878 int 2879 tnl_cong(struct port_info *pi, int drop) 2880 { 2881 2882 if (drop == -1) 2883 return (-1); 2884 else if (drop == 1) 2885 return (0); 2886 else 2887 return (pi->rx_chan_map); 2888 } 2889 2890 static int 2891 alloc_rxq(struct vi_info *vi, struct sge_rxq *rxq, int intr_idx, int idx, 2892 struct sysctl_oid *oid) 2893 { 2894 int rc; 2895 struct sysctl_oid_list *children; 2896 char name[16]; 2897 2898 rc = alloc_iq_fl(vi, &rxq->iq, &rxq->fl, intr_idx, 2899 tnl_cong(vi->pi, cong_drop)); 2900 if (rc != 0) 2901 return (rc); 2902 2903 /* 2904 * The freelist is just barely above the starvation threshold right now, 2905 * fill it up a bit more. 2906 */ 2907 FL_LOCK(&rxq->fl); 2908 refill_fl(vi->pi->adapter, &rxq->fl, 128); 2909 FL_UNLOCK(&rxq->fl); 2910 2911 #if defined(INET) || defined(INET6) 2912 rc = tcp_lro_init(&rxq->lro); 2913 if (rc != 0) 2914 return (rc); 2915 rxq->lro.ifp = vi->ifp; /* also indicates LRO init'ed */ 2916 2917 if (vi->ifp->if_capenable & IFCAP_LRO) 2918 rxq->iq.flags |= IQ_LRO_ENABLED; 2919 #endif 2920 rxq->ifp = vi->ifp; 2921 2922 children = SYSCTL_CHILDREN(oid); 2923 2924 snprintf(name, sizeof(name), "%d", idx); 2925 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 2926 NULL, "rx queue"); 2927 children = SYSCTL_CHILDREN(oid); 2928 2929 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "abs_id", 2930 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.abs_id, 0, sysctl_uint16, "I", 2931 "absolute id of the queue"); 2932 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cntxt_id", 2933 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.cntxt_id, 0, sysctl_uint16, "I", 2934 "SGE context id of the queue"); 2935 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx", 2936 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.cidx, 0, sysctl_uint16, "I", 2937 "consumer index"); 2938 #if defined(INET) || defined(INET6) 2939 SYSCTL_ADD_U64(&vi->ctx, children, OID_AUTO, "lro_queued", CTLFLAG_RD, 2940 &rxq->lro.lro_queued, 0, NULL); 2941 SYSCTL_ADD_U64(&vi->ctx, children, OID_AUTO, "lro_flushed", CTLFLAG_RD, 2942 &rxq->lro.lro_flushed, 0, NULL); 2943 #endif 2944 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "rxcsum", CTLFLAG_RD, 2945 &rxq->rxcsum, "# of times hardware assisted with checksum"); 2946 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_extraction", 2947 CTLFLAG_RD, &rxq->vlan_extraction, 2948 "# of times hardware extracted 802.1Q tag"); 2949 2950 add_fl_sysctls(&vi->ctx, oid, &rxq->fl); 2951 2952 return (rc); 2953 } 2954 2955 static int 2956 free_rxq(struct vi_info *vi, struct sge_rxq *rxq) 2957 { 2958 int rc; 2959 2960 #if defined(INET) || defined(INET6) 2961 if (rxq->lro.ifp) { 2962 tcp_lro_free(&rxq->lro); 2963 rxq->lro.ifp = NULL; 2964 } 2965 #endif 2966 2967 rc = free_iq_fl(vi, &rxq->iq, &rxq->fl); 2968 if (rc == 0) 2969 bzero(rxq, sizeof(*rxq)); 2970 2971 return (rc); 2972 } 2973 2974 #ifdef TCP_OFFLOAD 2975 static int 2976 alloc_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq, 2977 int intr_idx, int idx, struct sysctl_oid *oid) 2978 { 2979 int rc; 2980 struct sysctl_oid_list *children; 2981 char name[16]; 2982 2983 rc = alloc_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl, intr_idx, 2984 vi->pi->rx_chan_map); 2985 if (rc != 0) 2986 return (rc); 2987 2988 children = SYSCTL_CHILDREN(oid); 2989 2990 snprintf(name, sizeof(name), "%d", idx); 2991 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 2992 NULL, "rx queue"); 2993 children = SYSCTL_CHILDREN(oid); 2994 2995 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "abs_id", 2996 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.abs_id, 0, sysctl_uint16, 2997 "I", "absolute id of the queue"); 2998 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cntxt_id", 2999 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.cntxt_id, 0, sysctl_uint16, 3000 "I", "SGE context id of the queue"); 3001 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx", 3002 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.cidx, 0, sysctl_uint16, "I", 3003 "consumer index"); 3004 3005 add_fl_sysctls(&vi->ctx, oid, &ofld_rxq->fl); 3006 3007 return (rc); 3008 } 3009 3010 static int 3011 free_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq) 3012 { 3013 int rc; 3014 3015 rc = free_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl); 3016 if (rc == 0) 3017 bzero(ofld_rxq, sizeof(*ofld_rxq)); 3018 3019 return (rc); 3020 } 3021 #endif 3022 3023 #ifdef DEV_NETMAP 3024 static int 3025 alloc_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq, int intr_idx, 3026 int idx, struct sysctl_oid *oid) 3027 { 3028 int rc; 3029 struct sysctl_oid_list *children; 3030 struct sysctl_ctx_list *ctx; 3031 char name[16]; 3032 size_t len; 3033 struct adapter *sc = vi->pi->adapter; 3034 struct netmap_adapter *na = NA(vi->ifp); 3035 3036 MPASS(na != NULL); 3037 3038 len = vi->qsize_rxq * IQ_ESIZE; 3039 rc = alloc_ring(sc, len, &nm_rxq->iq_desc_tag, &nm_rxq->iq_desc_map, 3040 &nm_rxq->iq_ba, (void **)&nm_rxq->iq_desc); 3041 if (rc != 0) 3042 return (rc); 3043 3044 len = na->num_rx_desc * EQ_ESIZE + spg_len; 3045 rc = alloc_ring(sc, len, &nm_rxq->fl_desc_tag, &nm_rxq->fl_desc_map, 3046 &nm_rxq->fl_ba, (void **)&nm_rxq->fl_desc); 3047 if (rc != 0) 3048 return (rc); 3049 3050 nm_rxq->vi = vi; 3051 nm_rxq->nid = idx; 3052 nm_rxq->iq_cidx = 0; 3053 nm_rxq->iq_sidx = vi->qsize_rxq - spg_len / IQ_ESIZE; 3054 nm_rxq->iq_gen = F_RSPD_GEN; 3055 nm_rxq->fl_pidx = nm_rxq->fl_cidx = 0; 3056 nm_rxq->fl_sidx = na->num_rx_desc; 3057 nm_rxq->intr_idx = intr_idx; 3058 3059 ctx = &vi->ctx; 3060 children = SYSCTL_CHILDREN(oid); 3061 3062 snprintf(name, sizeof(name), "%d", idx); 3063 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, name, CTLFLAG_RD, NULL, 3064 "rx queue"); 3065 children = SYSCTL_CHILDREN(oid); 3066 3067 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "abs_id", 3068 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_abs_id, 0, sysctl_uint16, 3069 "I", "absolute id of the queue"); 3070 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 3071 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cntxt_id, 0, sysctl_uint16, 3072 "I", "SGE context id of the queue"); 3073 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx", 3074 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cidx, 0, sysctl_uint16, "I", 3075 "consumer index"); 3076 3077 children = SYSCTL_CHILDREN(oid); 3078 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL, 3079 "freelist"); 3080 children = SYSCTL_CHILDREN(oid); 3081 3082 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 3083 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->fl_cntxt_id, 0, sysctl_uint16, 3084 "I", "SGE context id of the freelist"); 3085 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, 3086 &nm_rxq->fl_cidx, 0, "consumer index"); 3087 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, 3088 &nm_rxq->fl_pidx, 0, "producer index"); 3089 3090 return (rc); 3091 } 3092 3093 3094 static int 3095 free_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq) 3096 { 3097 struct adapter *sc = vi->pi->adapter; 3098 3099 free_ring(sc, nm_rxq->iq_desc_tag, nm_rxq->iq_desc_map, nm_rxq->iq_ba, 3100 nm_rxq->iq_desc); 3101 free_ring(sc, nm_rxq->fl_desc_tag, nm_rxq->fl_desc_map, nm_rxq->fl_ba, 3102 nm_rxq->fl_desc); 3103 3104 return (0); 3105 } 3106 3107 static int 3108 alloc_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq, int iqidx, int idx, 3109 struct sysctl_oid *oid) 3110 { 3111 int rc; 3112 size_t len; 3113 struct port_info *pi = vi->pi; 3114 struct adapter *sc = pi->adapter; 3115 struct netmap_adapter *na = NA(vi->ifp); 3116 char name[16]; 3117 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3118 3119 len = na->num_tx_desc * EQ_ESIZE + spg_len; 3120 rc = alloc_ring(sc, len, &nm_txq->desc_tag, &nm_txq->desc_map, 3121 &nm_txq->ba, (void **)&nm_txq->desc); 3122 if (rc) 3123 return (rc); 3124 3125 nm_txq->pidx = nm_txq->cidx = 0; 3126 nm_txq->sidx = na->num_tx_desc; 3127 nm_txq->nid = idx; 3128 nm_txq->iqidx = iqidx; 3129 nm_txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) | 3130 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_VF_VLD(1) | 3131 V_TXPKT_VF(vi->viid)); 3132 3133 snprintf(name, sizeof(name), "%d", idx); 3134 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 3135 NULL, "netmap tx queue"); 3136 children = SYSCTL_CHILDREN(oid); 3137 3138 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 3139 &nm_txq->cntxt_id, 0, "SGE context id of the queue"); 3140 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx", 3141 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->cidx, 0, sysctl_uint16, "I", 3142 "consumer index"); 3143 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "pidx", 3144 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->pidx, 0, sysctl_uint16, "I", 3145 "producer index"); 3146 3147 return (rc); 3148 } 3149 3150 static int 3151 free_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq) 3152 { 3153 struct adapter *sc = vi->pi->adapter; 3154 3155 free_ring(sc, nm_txq->desc_tag, nm_txq->desc_map, nm_txq->ba, 3156 nm_txq->desc); 3157 3158 return (0); 3159 } 3160 #endif 3161 3162 static int 3163 ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq) 3164 { 3165 int rc, cntxt_id; 3166 struct fw_eq_ctrl_cmd c; 3167 int qsize = eq->sidx + spg_len / EQ_ESIZE; 3168 3169 bzero(&c, sizeof(c)); 3170 3171 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | F_FW_CMD_REQUEST | 3172 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_CTRL_CMD_PFN(sc->pf) | 3173 V_FW_EQ_CTRL_CMD_VFN(0)); 3174 c.alloc_to_len16 = htobe32(F_FW_EQ_CTRL_CMD_ALLOC | 3175 F_FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c)); 3176 c.cmpliqid_eqid = htonl(V_FW_EQ_CTRL_CMD_CMPLIQID(eq->iqid)); 3177 c.physeqid_pkd = htobe32(0); 3178 c.fetchszm_to_iqid = 3179 htobe32(V_FW_EQ_CTRL_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) | 3180 V_FW_EQ_CTRL_CMD_PCIECHN(eq->tx_chan) | 3181 F_FW_EQ_CTRL_CMD_FETCHRO | V_FW_EQ_CTRL_CMD_IQID(eq->iqid)); 3182 c.dcaen_to_eqsize = 3183 htobe32(V_FW_EQ_CTRL_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 3184 V_FW_EQ_CTRL_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 3185 V_FW_EQ_CTRL_CMD_EQSIZE(qsize)); 3186 c.eqaddr = htobe64(eq->ba); 3187 3188 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3189 if (rc != 0) { 3190 device_printf(sc->dev, 3191 "failed to create control queue %d: %d\n", eq->tx_chan, rc); 3192 return (rc); 3193 } 3194 eq->flags |= EQ_ALLOCATED; 3195 3196 eq->cntxt_id = G_FW_EQ_CTRL_CMD_EQID(be32toh(c.cmpliqid_eqid)); 3197 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 3198 if (cntxt_id >= sc->sge.neq) 3199 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 3200 cntxt_id, sc->sge.neq - 1); 3201 sc->sge.eqmap[cntxt_id] = eq; 3202 3203 return (rc); 3204 } 3205 3206 static int 3207 eth_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 3208 { 3209 int rc, cntxt_id; 3210 struct fw_eq_eth_cmd c; 3211 int qsize = eq->sidx + spg_len / EQ_ESIZE; 3212 3213 bzero(&c, sizeof(c)); 3214 3215 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST | 3216 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) | 3217 V_FW_EQ_ETH_CMD_VFN(0)); 3218 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC | 3219 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c)); 3220 c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE | 3221 F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(vi->viid)); 3222 c.fetchszm_to_iqid = 3223 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) | 3224 V_FW_EQ_ETH_CMD_PCIECHN(eq->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO | 3225 V_FW_EQ_ETH_CMD_IQID(eq->iqid)); 3226 c.dcaen_to_eqsize = htobe32(V_FW_EQ_ETH_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 3227 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 3228 V_FW_EQ_ETH_CMD_EQSIZE(qsize)); 3229 c.eqaddr = htobe64(eq->ba); 3230 3231 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3232 if (rc != 0) { 3233 device_printf(vi->dev, 3234 "failed to create Ethernet egress queue: %d\n", rc); 3235 return (rc); 3236 } 3237 eq->flags |= EQ_ALLOCATED; 3238 3239 eq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd)); 3240 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 3241 if (cntxt_id >= sc->sge.neq) 3242 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 3243 cntxt_id, sc->sge.neq - 1); 3244 sc->sge.eqmap[cntxt_id] = eq; 3245 3246 return (rc); 3247 } 3248 3249 #ifdef TCP_OFFLOAD 3250 static int 3251 ofld_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 3252 { 3253 int rc, cntxt_id; 3254 struct fw_eq_ofld_cmd c; 3255 int qsize = eq->sidx + spg_len / EQ_ESIZE; 3256 3257 bzero(&c, sizeof(c)); 3258 3259 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | F_FW_CMD_REQUEST | 3260 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_OFLD_CMD_PFN(sc->pf) | 3261 V_FW_EQ_OFLD_CMD_VFN(0)); 3262 c.alloc_to_len16 = htonl(F_FW_EQ_OFLD_CMD_ALLOC | 3263 F_FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c)); 3264 c.fetchszm_to_iqid = 3265 htonl(V_FW_EQ_OFLD_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) | 3266 V_FW_EQ_OFLD_CMD_PCIECHN(eq->tx_chan) | 3267 F_FW_EQ_OFLD_CMD_FETCHRO | V_FW_EQ_OFLD_CMD_IQID(eq->iqid)); 3268 c.dcaen_to_eqsize = 3269 htobe32(V_FW_EQ_OFLD_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 3270 V_FW_EQ_OFLD_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 3271 V_FW_EQ_OFLD_CMD_EQSIZE(qsize)); 3272 c.eqaddr = htobe64(eq->ba); 3273 3274 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3275 if (rc != 0) { 3276 device_printf(vi->dev, 3277 "failed to create egress queue for TCP offload: %d\n", rc); 3278 return (rc); 3279 } 3280 eq->flags |= EQ_ALLOCATED; 3281 3282 eq->cntxt_id = G_FW_EQ_OFLD_CMD_EQID(be32toh(c.eqid_pkd)); 3283 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 3284 if (cntxt_id >= sc->sge.neq) 3285 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 3286 cntxt_id, sc->sge.neq - 1); 3287 sc->sge.eqmap[cntxt_id] = eq; 3288 3289 return (rc); 3290 } 3291 #endif 3292 3293 static int 3294 alloc_eq(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 3295 { 3296 int rc, qsize; 3297 size_t len; 3298 3299 mtx_init(&eq->eq_lock, eq->lockname, NULL, MTX_DEF); 3300 3301 qsize = eq->sidx + spg_len / EQ_ESIZE; 3302 len = qsize * EQ_ESIZE; 3303 rc = alloc_ring(sc, len, &eq->desc_tag, &eq->desc_map, 3304 &eq->ba, (void **)&eq->desc); 3305 if (rc) 3306 return (rc); 3307 3308 eq->pidx = eq->cidx = 0; 3309 eq->equeqidx = eq->dbidx = 0; 3310 eq->doorbells = sc->doorbells; 3311 3312 switch (eq->flags & EQ_TYPEMASK) { 3313 case EQ_CTRL: 3314 rc = ctrl_eq_alloc(sc, eq); 3315 break; 3316 3317 case EQ_ETH: 3318 rc = eth_eq_alloc(sc, vi, eq); 3319 break; 3320 3321 #ifdef TCP_OFFLOAD 3322 case EQ_OFLD: 3323 rc = ofld_eq_alloc(sc, vi, eq); 3324 break; 3325 #endif 3326 3327 default: 3328 panic("%s: invalid eq type %d.", __func__, 3329 eq->flags & EQ_TYPEMASK); 3330 } 3331 if (rc != 0) { 3332 device_printf(sc->dev, 3333 "failed to allocate egress queue(%d): %d\n", 3334 eq->flags & EQ_TYPEMASK, rc); 3335 } 3336 3337 if (isset(&eq->doorbells, DOORBELL_UDB) || 3338 isset(&eq->doorbells, DOORBELL_UDBWC) || 3339 isset(&eq->doorbells, DOORBELL_WCWR)) { 3340 uint32_t s_qpp = sc->sge.eq_s_qpp; 3341 uint32_t mask = (1 << s_qpp) - 1; 3342 volatile uint8_t *udb; 3343 3344 udb = sc->udbs_base + UDBS_DB_OFFSET; 3345 udb += (eq->cntxt_id >> s_qpp) << PAGE_SHIFT; /* pg offset */ 3346 eq->udb_qid = eq->cntxt_id & mask; /* id in page */ 3347 if (eq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE) 3348 clrbit(&eq->doorbells, DOORBELL_WCWR); 3349 else { 3350 udb += eq->udb_qid << UDBS_SEG_SHIFT; /* seg offset */ 3351 eq->udb_qid = 0; 3352 } 3353 eq->udb = (volatile void *)udb; 3354 } 3355 3356 return (rc); 3357 } 3358 3359 static int 3360 free_eq(struct adapter *sc, struct sge_eq *eq) 3361 { 3362 int rc; 3363 3364 if (eq->flags & EQ_ALLOCATED) { 3365 switch (eq->flags & EQ_TYPEMASK) { 3366 case EQ_CTRL: 3367 rc = -t4_ctrl_eq_free(sc, sc->mbox, sc->pf, 0, 3368 eq->cntxt_id); 3369 break; 3370 3371 case EQ_ETH: 3372 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0, 3373 eq->cntxt_id); 3374 break; 3375 3376 #ifdef TCP_OFFLOAD 3377 case EQ_OFLD: 3378 rc = -t4_ofld_eq_free(sc, sc->mbox, sc->pf, 0, 3379 eq->cntxt_id); 3380 break; 3381 #endif 3382 3383 default: 3384 panic("%s: invalid eq type %d.", __func__, 3385 eq->flags & EQ_TYPEMASK); 3386 } 3387 if (rc != 0) { 3388 device_printf(sc->dev, 3389 "failed to free egress queue (%d): %d\n", 3390 eq->flags & EQ_TYPEMASK, rc); 3391 return (rc); 3392 } 3393 eq->flags &= ~EQ_ALLOCATED; 3394 } 3395 3396 free_ring(sc, eq->desc_tag, eq->desc_map, eq->ba, eq->desc); 3397 3398 if (mtx_initialized(&eq->eq_lock)) 3399 mtx_destroy(&eq->eq_lock); 3400 3401 bzero(eq, sizeof(*eq)); 3402 return (0); 3403 } 3404 3405 static int 3406 alloc_wrq(struct adapter *sc, struct vi_info *vi, struct sge_wrq *wrq, 3407 struct sysctl_oid *oid) 3408 { 3409 int rc; 3410 struct sysctl_ctx_list *ctx = vi ? &vi->ctx : &sc->ctx; 3411 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3412 3413 rc = alloc_eq(sc, vi, &wrq->eq); 3414 if (rc) 3415 return (rc); 3416 3417 wrq->adapter = sc; 3418 TASK_INIT(&wrq->wrq_tx_task, 0, wrq_tx_drain, wrq); 3419 TAILQ_INIT(&wrq->incomplete_wrs); 3420 STAILQ_INIT(&wrq->wr_list); 3421 wrq->nwr_pending = 0; 3422 wrq->ndesc_needed = 0; 3423 3424 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 3425 &wrq->eq.cntxt_id, 0, "SGE context id of the queue"); 3426 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx", 3427 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.cidx, 0, sysctl_uint16, "I", 3428 "consumer index"); 3429 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pidx", 3430 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.pidx, 0, sysctl_uint16, "I", 3431 "producer index"); 3432 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_direct", CTLFLAG_RD, 3433 &wrq->tx_wrs_direct, "# of work requests (direct)"); 3434 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_copied", CTLFLAG_RD, 3435 &wrq->tx_wrs_copied, "# of work requests (copied)"); 3436 3437 return (rc); 3438 } 3439 3440 static int 3441 free_wrq(struct adapter *sc, struct sge_wrq *wrq) 3442 { 3443 int rc; 3444 3445 rc = free_eq(sc, &wrq->eq); 3446 if (rc) 3447 return (rc); 3448 3449 bzero(wrq, sizeof(*wrq)); 3450 return (0); 3451 } 3452 3453 static int 3454 alloc_txq(struct vi_info *vi, struct sge_txq *txq, int idx, 3455 struct sysctl_oid *oid) 3456 { 3457 int rc; 3458 struct port_info *pi = vi->pi; 3459 struct adapter *sc = pi->adapter; 3460 struct sge_eq *eq = &txq->eq; 3461 char name[16]; 3462 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3463 3464 rc = mp_ring_alloc(&txq->r, eq->sidx, txq, eth_tx, can_resume_eth_tx, 3465 M_CXGBE, M_WAITOK); 3466 if (rc != 0) { 3467 device_printf(sc->dev, "failed to allocate mp_ring: %d\n", rc); 3468 return (rc); 3469 } 3470 3471 rc = alloc_eq(sc, vi, eq); 3472 if (rc != 0) { 3473 mp_ring_free(txq->r); 3474 txq->r = NULL; 3475 return (rc); 3476 } 3477 3478 /* Can't fail after this point. */ 3479 3480 TASK_INIT(&txq->tx_reclaim_task, 0, tx_reclaim, eq); 3481 txq->ifp = vi->ifp; 3482 txq->gl = sglist_alloc(TX_SGL_SEGS, M_WAITOK); 3483 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) | 3484 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_VF_VLD(1) | 3485 V_TXPKT_VF(vi->viid)); 3486 txq->sdesc = malloc(eq->sidx * sizeof(struct tx_sdesc), M_CXGBE, 3487 M_ZERO | M_WAITOK); 3488 3489 snprintf(name, sizeof(name), "%d", idx); 3490 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 3491 NULL, "tx queue"); 3492 children = SYSCTL_CHILDREN(oid); 3493 3494 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 3495 &eq->cntxt_id, 0, "SGE context id of the queue"); 3496 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx", 3497 CTLTYPE_INT | CTLFLAG_RD, &eq->cidx, 0, sysctl_uint16, "I", 3498 "consumer index"); 3499 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "pidx", 3500 CTLTYPE_INT | CTLFLAG_RD, &eq->pidx, 0, sysctl_uint16, "I", 3501 "producer index"); 3502 3503 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txcsum", CTLFLAG_RD, 3504 &txq->txcsum, "# of times hardware assisted with checksum"); 3505 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_insertion", 3506 CTLFLAG_RD, &txq->vlan_insertion, 3507 "# of times hardware inserted 802.1Q tag"); 3508 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "tso_wrs", CTLFLAG_RD, 3509 &txq->tso_wrs, "# of TSO work requests"); 3510 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "imm_wrs", CTLFLAG_RD, 3511 &txq->imm_wrs, "# of work requests with immediate data"); 3512 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "sgl_wrs", CTLFLAG_RD, 3513 &txq->sgl_wrs, "# of work requests with direct SGL"); 3514 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkt_wrs", CTLFLAG_RD, 3515 &txq->txpkt_wrs, "# of txpkt work requests (one pkt/WR)"); 3516 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_wrs", 3517 CTLFLAG_RD, &txq->txpkts0_wrs, 3518 "# of txpkts (type 0) work requests"); 3519 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_wrs", 3520 CTLFLAG_RD, &txq->txpkts1_wrs, 3521 "# of txpkts (type 1) work requests"); 3522 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_pkts", 3523 CTLFLAG_RD, &txq->txpkts0_pkts, 3524 "# of frames tx'd using type0 txpkts work requests"); 3525 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_pkts", 3526 CTLFLAG_RD, &txq->txpkts1_pkts, 3527 "# of frames tx'd using type1 txpkts work requests"); 3528 3529 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_enqueues", 3530 CTLFLAG_RD, &txq->r->enqueues, 3531 "# of enqueues to the mp_ring for this queue"); 3532 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_drops", 3533 CTLFLAG_RD, &txq->r->drops, 3534 "# of drops in the mp_ring for this queue"); 3535 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_starts", 3536 CTLFLAG_RD, &txq->r->starts, 3537 "# of normal consumer starts in the mp_ring for this queue"); 3538 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_stalls", 3539 CTLFLAG_RD, &txq->r->stalls, 3540 "# of consumer stalls in the mp_ring for this queue"); 3541 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_restarts", 3542 CTLFLAG_RD, &txq->r->restarts, 3543 "# of consumer restarts in the mp_ring for this queue"); 3544 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_abdications", 3545 CTLFLAG_RD, &txq->r->abdications, 3546 "# of consumer abdications in the mp_ring for this queue"); 3547 3548 return (0); 3549 } 3550 3551 static int 3552 free_txq(struct vi_info *vi, struct sge_txq *txq) 3553 { 3554 int rc; 3555 struct adapter *sc = vi->pi->adapter; 3556 struct sge_eq *eq = &txq->eq; 3557 3558 rc = free_eq(sc, eq); 3559 if (rc) 3560 return (rc); 3561 3562 sglist_free(txq->gl); 3563 free(txq->sdesc, M_CXGBE); 3564 mp_ring_free(txq->r); 3565 3566 bzero(txq, sizeof(*txq)); 3567 return (0); 3568 } 3569 3570 static void 3571 oneseg_dma_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3572 { 3573 bus_addr_t *ba = arg; 3574 3575 KASSERT(nseg == 1, 3576 ("%s meant for single segment mappings only.", __func__)); 3577 3578 *ba = error ? 0 : segs->ds_addr; 3579 } 3580 3581 static inline void 3582 ring_fl_db(struct adapter *sc, struct sge_fl *fl) 3583 { 3584 uint32_t n, v; 3585 3586 n = IDXDIFF(fl->pidx / 8, fl->dbidx, fl->sidx); 3587 MPASS(n > 0); 3588 3589 wmb(); 3590 v = fl->dbval | V_PIDX(n); 3591 if (fl->udb) 3592 *fl->udb = htole32(v); 3593 else 3594 t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL), v); 3595 IDXINCR(fl->dbidx, n, fl->sidx); 3596 } 3597 3598 /* 3599 * Fills up the freelist by allocating upto 'n' buffers. Buffers that are 3600 * recycled do not count towards this allocation budget. 3601 * 3602 * Returns non-zero to indicate that this freelist should be added to the list 3603 * of starving freelists. 3604 */ 3605 static int 3606 refill_fl(struct adapter *sc, struct sge_fl *fl, int n) 3607 { 3608 __be64 *d; 3609 struct fl_sdesc *sd; 3610 uintptr_t pa; 3611 caddr_t cl; 3612 struct cluster_layout *cll; 3613 struct sw_zone_info *swz; 3614 struct cluster_metadata *clm; 3615 uint16_t max_pidx; 3616 uint16_t hw_cidx = fl->hw_cidx; /* stable snapshot */ 3617 3618 FL_LOCK_ASSERT_OWNED(fl); 3619 3620 /* 3621 * We always stop at the begining of the hardware descriptor that's just 3622 * before the one with the hw cidx. This is to avoid hw pidx = hw cidx, 3623 * which would mean an empty freelist to the chip. 3624 */ 3625 max_pidx = __predict_false(hw_cidx == 0) ? fl->sidx - 1 : hw_cidx - 1; 3626 if (fl->pidx == max_pidx * 8) 3627 return (0); 3628 3629 d = &fl->desc[fl->pidx]; 3630 sd = &fl->sdesc[fl->pidx]; 3631 cll = &fl->cll_def; /* default layout */ 3632 swz = &sc->sge.sw_zone_info[cll->zidx]; 3633 3634 while (n > 0) { 3635 3636 if (sd->cl != NULL) { 3637 3638 if (sd->nmbuf == 0) { 3639 /* 3640 * Fast recycle without involving any atomics on 3641 * the cluster's metadata (if the cluster has 3642 * metadata). This happens when all frames 3643 * received in the cluster were small enough to 3644 * fit within a single mbuf each. 3645 */ 3646 fl->cl_fast_recycled++; 3647 #ifdef INVARIANTS 3648 clm = cl_metadata(sc, fl, &sd->cll, sd->cl); 3649 if (clm != NULL) 3650 MPASS(clm->refcount == 1); 3651 #endif 3652 goto recycled_fast; 3653 } 3654 3655 /* 3656 * Cluster is guaranteed to have metadata. Clusters 3657 * without metadata always take the fast recycle path 3658 * when they're recycled. 3659 */ 3660 clm = cl_metadata(sc, fl, &sd->cll, sd->cl); 3661 MPASS(clm != NULL); 3662 3663 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) { 3664 fl->cl_recycled++; 3665 counter_u64_add(extfree_rels, 1); 3666 goto recycled; 3667 } 3668 sd->cl = NULL; /* gave up my reference */ 3669 } 3670 MPASS(sd->cl == NULL); 3671 alloc: 3672 cl = uma_zalloc(swz->zone, M_NOWAIT); 3673 if (__predict_false(cl == NULL)) { 3674 if (cll == &fl->cll_alt || fl->cll_alt.zidx == -1 || 3675 fl->cll_def.zidx == fl->cll_alt.zidx) 3676 break; 3677 3678 /* fall back to the safe zone */ 3679 cll = &fl->cll_alt; 3680 swz = &sc->sge.sw_zone_info[cll->zidx]; 3681 goto alloc; 3682 } 3683 fl->cl_allocated++; 3684 n--; 3685 3686 pa = pmap_kextract((vm_offset_t)cl); 3687 pa += cll->region1; 3688 sd->cl = cl; 3689 sd->cll = *cll; 3690 *d = htobe64(pa | cll->hwidx); 3691 clm = cl_metadata(sc, fl, cll, cl); 3692 if (clm != NULL) { 3693 recycled: 3694 #ifdef INVARIANTS 3695 clm->sd = sd; 3696 #endif 3697 clm->refcount = 1; 3698 } 3699 sd->nmbuf = 0; 3700 recycled_fast: 3701 d++; 3702 sd++; 3703 if (__predict_false(++fl->pidx % 8 == 0)) { 3704 uint16_t pidx = fl->pidx / 8; 3705 3706 if (__predict_false(pidx == fl->sidx)) { 3707 fl->pidx = 0; 3708 pidx = 0; 3709 sd = fl->sdesc; 3710 d = fl->desc; 3711 } 3712 if (pidx == max_pidx) 3713 break; 3714 3715 if (IDXDIFF(pidx, fl->dbidx, fl->sidx) >= 4) 3716 ring_fl_db(sc, fl); 3717 } 3718 } 3719 3720 if (fl->pidx / 8 != fl->dbidx) 3721 ring_fl_db(sc, fl); 3722 3723 return (FL_RUNNING_LOW(fl) && !(fl->flags & FL_STARVING)); 3724 } 3725 3726 /* 3727 * Attempt to refill all starving freelists. 3728 */ 3729 static void 3730 refill_sfl(void *arg) 3731 { 3732 struct adapter *sc = arg; 3733 struct sge_fl *fl, *fl_temp; 3734 3735 mtx_assert(&sc->sfl_lock, MA_OWNED); 3736 TAILQ_FOREACH_SAFE(fl, &sc->sfl, link, fl_temp) { 3737 FL_LOCK(fl); 3738 refill_fl(sc, fl, 64); 3739 if (FL_NOT_RUNNING_LOW(fl) || fl->flags & FL_DOOMED) { 3740 TAILQ_REMOVE(&sc->sfl, fl, link); 3741 fl->flags &= ~FL_STARVING; 3742 } 3743 FL_UNLOCK(fl); 3744 } 3745 3746 if (!TAILQ_EMPTY(&sc->sfl)) 3747 callout_schedule(&sc->sfl_callout, hz / 5); 3748 } 3749 3750 static int 3751 alloc_fl_sdesc(struct sge_fl *fl) 3752 { 3753 3754 fl->sdesc = malloc(fl->sidx * 8 * sizeof(struct fl_sdesc), M_CXGBE, 3755 M_ZERO | M_WAITOK); 3756 3757 return (0); 3758 } 3759 3760 static void 3761 free_fl_sdesc(struct adapter *sc, struct sge_fl *fl) 3762 { 3763 struct fl_sdesc *sd; 3764 struct cluster_metadata *clm; 3765 struct cluster_layout *cll; 3766 int i; 3767 3768 sd = fl->sdesc; 3769 for (i = 0; i < fl->sidx * 8; i++, sd++) { 3770 if (sd->cl == NULL) 3771 continue; 3772 3773 cll = &sd->cll; 3774 clm = cl_metadata(sc, fl, cll, sd->cl); 3775 if (sd->nmbuf == 0) 3776 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl); 3777 else if (clm && atomic_fetchadd_int(&clm->refcount, -1) == 1) { 3778 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl); 3779 counter_u64_add(extfree_rels, 1); 3780 } 3781 sd->cl = NULL; 3782 } 3783 3784 free(fl->sdesc, M_CXGBE); 3785 fl->sdesc = NULL; 3786 } 3787 3788 static inline void 3789 get_pkt_gl(struct mbuf *m, struct sglist *gl) 3790 { 3791 int rc; 3792 3793 M_ASSERTPKTHDR(m); 3794 3795 sglist_reset(gl); 3796 rc = sglist_append_mbuf(gl, m); 3797 if (__predict_false(rc != 0)) { 3798 panic("%s: mbuf %p (%d segs) was vetted earlier but now fails " 3799 "with %d.", __func__, m, mbuf_nsegs(m), rc); 3800 } 3801 3802 KASSERT(gl->sg_nseg == mbuf_nsegs(m), 3803 ("%s: nsegs changed for mbuf %p from %d to %d", __func__, m, 3804 mbuf_nsegs(m), gl->sg_nseg)); 3805 KASSERT(gl->sg_nseg > 0 && 3806 gl->sg_nseg <= (needs_tso(m) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS), 3807 ("%s: %d segments, should have been 1 <= nsegs <= %d", __func__, 3808 gl->sg_nseg, needs_tso(m) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS)); 3809 } 3810 3811 /* 3812 * len16 for a txpkt WR with a GL. Includes the firmware work request header. 3813 */ 3814 static inline u_int 3815 txpkt_len16(u_int nsegs, u_int tso) 3816 { 3817 u_int n; 3818 3819 MPASS(nsegs > 0); 3820 3821 nsegs--; /* first segment is part of ulptx_sgl */ 3822 n = sizeof(struct fw_eth_tx_pkt_wr) + sizeof(struct cpl_tx_pkt_core) + 3823 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 3824 if (tso) 3825 n += sizeof(struct cpl_tx_pkt_lso_core); 3826 3827 return (howmany(n, 16)); 3828 } 3829 3830 /* 3831 * len16 for a txpkts type 0 WR with a GL. Does not include the firmware work 3832 * request header. 3833 */ 3834 static inline u_int 3835 txpkts0_len16(u_int nsegs) 3836 { 3837 u_int n; 3838 3839 MPASS(nsegs > 0); 3840 3841 nsegs--; /* first segment is part of ulptx_sgl */ 3842 n = sizeof(struct ulp_txpkt) + sizeof(struct ulptx_idata) + 3843 sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl) + 3844 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 3845 3846 return (howmany(n, 16)); 3847 } 3848 3849 /* 3850 * len16 for a txpkts type 1 WR with a GL. Does not include the firmware work 3851 * request header. 3852 */ 3853 static inline u_int 3854 txpkts1_len16(void) 3855 { 3856 u_int n; 3857 3858 n = sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl); 3859 3860 return (howmany(n, 16)); 3861 } 3862 3863 static inline u_int 3864 imm_payload(u_int ndesc) 3865 { 3866 u_int n; 3867 3868 n = ndesc * EQ_ESIZE - sizeof(struct fw_eth_tx_pkt_wr) - 3869 sizeof(struct cpl_tx_pkt_core); 3870 3871 return (n); 3872 } 3873 3874 /* 3875 * Write a txpkt WR for this packet to the hardware descriptors, update the 3876 * software descriptor, and advance the pidx. It is guaranteed that enough 3877 * descriptors are available. 3878 * 3879 * The return value is the # of hardware descriptors used. 3880 */ 3881 static u_int 3882 write_txpkt_wr(struct sge_txq *txq, struct fw_eth_tx_pkt_wr *wr, 3883 struct mbuf *m0, u_int available) 3884 { 3885 struct sge_eq *eq = &txq->eq; 3886 struct tx_sdesc *txsd; 3887 struct cpl_tx_pkt_core *cpl; 3888 uint32_t ctrl; /* used in many unrelated places */ 3889 uint64_t ctrl1; 3890 int len16, ndesc, pktlen, nsegs; 3891 caddr_t dst; 3892 3893 TXQ_LOCK_ASSERT_OWNED(txq); 3894 M_ASSERTPKTHDR(m0); 3895 MPASS(available > 0 && available < eq->sidx); 3896 3897 len16 = mbuf_len16(m0); 3898 nsegs = mbuf_nsegs(m0); 3899 pktlen = m0->m_pkthdr.len; 3900 ctrl = sizeof(struct cpl_tx_pkt_core); 3901 if (needs_tso(m0)) 3902 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 3903 else if (pktlen <= imm_payload(2) && available >= 2) { 3904 /* Immediate data. Recalculate len16 and set nsegs to 0. */ 3905 ctrl += pktlen; 3906 len16 = howmany(sizeof(struct fw_eth_tx_pkt_wr) + 3907 sizeof(struct cpl_tx_pkt_core) + pktlen, 16); 3908 nsegs = 0; 3909 } 3910 ndesc = howmany(len16, EQ_ESIZE / 16); 3911 MPASS(ndesc <= available); 3912 3913 /* Firmware work request header */ 3914 MPASS(wr == (void *)&eq->desc[eq->pidx]); 3915 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_WR) | 3916 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl)); 3917 3918 ctrl = V_FW_WR_LEN16(len16); 3919 wr->equiq_to_len16 = htobe32(ctrl); 3920 wr->r3 = 0; 3921 3922 if (needs_tso(m0)) { 3923 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1); 3924 3925 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 3926 m0->m_pkthdr.l4hlen > 0, 3927 ("%s: mbuf %p needs TSO but missing header lengths", 3928 __func__, m0)); 3929 3930 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE | 3931 F_LSO_LAST_SLICE | V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) 3932 | V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2); 3933 if (m0->m_pkthdr.l2hlen == sizeof(struct ether_vlan_header)) 3934 ctrl |= V_LSO_ETHHDR_LEN(1); 3935 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 3936 ctrl |= F_LSO_IPV6; 3937 3938 lso->lso_ctrl = htobe32(ctrl); 3939 lso->ipid_ofst = htobe16(0); 3940 lso->mss = htobe16(m0->m_pkthdr.tso_segsz); 3941 lso->seqno_offset = htobe32(0); 3942 lso->len = htobe32(pktlen); 3943 3944 cpl = (void *)(lso + 1); 3945 3946 txq->tso_wrs++; 3947 } else 3948 cpl = (void *)(wr + 1); 3949 3950 /* Checksum offload */ 3951 ctrl1 = 0; 3952 if (needs_l3_csum(m0) == 0) 3953 ctrl1 |= F_TXPKT_IPCSUM_DIS; 3954 if (needs_l4_csum(m0) == 0) 3955 ctrl1 |= F_TXPKT_L4CSUM_DIS; 3956 if (m0->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | 3957 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO)) 3958 txq->txcsum++; /* some hardware assistance provided */ 3959 3960 /* VLAN tag insertion */ 3961 if (needs_vlan_insertion(m0)) { 3962 ctrl1 |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 3963 txq->vlan_insertion++; 3964 } 3965 3966 /* CPL header */ 3967 cpl->ctrl0 = txq->cpl_ctrl0; 3968 cpl->pack = 0; 3969 cpl->len = htobe16(pktlen); 3970 cpl->ctrl1 = htobe64(ctrl1); 3971 3972 /* SGL */ 3973 dst = (void *)(cpl + 1); 3974 if (nsegs > 0) { 3975 3976 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx); 3977 txq->sgl_wrs++; 3978 } else { 3979 struct mbuf *m; 3980 3981 for (m = m0; m != NULL; m = m->m_next) { 3982 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len); 3983 #ifdef INVARIANTS 3984 pktlen -= m->m_len; 3985 #endif 3986 } 3987 #ifdef INVARIANTS 3988 KASSERT(pktlen == 0, ("%s: %d bytes left.", __func__, pktlen)); 3989 #endif 3990 txq->imm_wrs++; 3991 } 3992 3993 txq->txpkt_wrs++; 3994 3995 txsd = &txq->sdesc[eq->pidx]; 3996 txsd->m = m0; 3997 txsd->desc_used = ndesc; 3998 3999 return (ndesc); 4000 } 4001 4002 static int 4003 try_txpkts(struct mbuf *m, struct mbuf *n, struct txpkts *txp, u_int available) 4004 { 4005 u_int needed, nsegs1, nsegs2, l1, l2; 4006 4007 if (cannot_use_txpkts(m) || cannot_use_txpkts(n)) 4008 return (1); 4009 4010 nsegs1 = mbuf_nsegs(m); 4011 nsegs2 = mbuf_nsegs(n); 4012 if (nsegs1 + nsegs2 == 2) { 4013 txp->wr_type = 1; 4014 l1 = l2 = txpkts1_len16(); 4015 } else { 4016 txp->wr_type = 0; 4017 l1 = txpkts0_len16(nsegs1); 4018 l2 = txpkts0_len16(nsegs2); 4019 } 4020 txp->len16 = howmany(sizeof(struct fw_eth_tx_pkts_wr), 16) + l1 + l2; 4021 needed = howmany(txp->len16, EQ_ESIZE / 16); 4022 if (needed > SGE_MAX_WR_NDESC || needed > available) 4023 return (1); 4024 4025 txp->plen = m->m_pkthdr.len + n->m_pkthdr.len; 4026 if (txp->plen > 65535) 4027 return (1); 4028 4029 txp->npkt = 2; 4030 set_mbuf_len16(m, l1); 4031 set_mbuf_len16(n, l2); 4032 4033 return (0); 4034 } 4035 4036 static int 4037 add_to_txpkts(struct mbuf *m, struct txpkts *txp, u_int available) 4038 { 4039 u_int plen, len16, needed, nsegs; 4040 4041 MPASS(txp->wr_type == 0 || txp->wr_type == 1); 4042 4043 nsegs = mbuf_nsegs(m); 4044 if (needs_tso(m) || (txp->wr_type == 1 && nsegs != 1)) 4045 return (1); 4046 4047 plen = txp->plen + m->m_pkthdr.len; 4048 if (plen > 65535) 4049 return (1); 4050 4051 if (txp->wr_type == 0) 4052 len16 = txpkts0_len16(nsegs); 4053 else 4054 len16 = txpkts1_len16(); 4055 needed = howmany(txp->len16 + len16, EQ_ESIZE / 16); 4056 if (needed > SGE_MAX_WR_NDESC || needed > available) 4057 return (1); 4058 4059 txp->npkt++; 4060 txp->plen = plen; 4061 txp->len16 += len16; 4062 set_mbuf_len16(m, len16); 4063 4064 return (0); 4065 } 4066 4067 /* 4068 * Write a txpkts WR for the packets in txp to the hardware descriptors, update 4069 * the software descriptor, and advance the pidx. It is guaranteed that enough 4070 * descriptors are available. 4071 * 4072 * The return value is the # of hardware descriptors used. 4073 */ 4074 static u_int 4075 write_txpkts_wr(struct sge_txq *txq, struct fw_eth_tx_pkts_wr *wr, 4076 struct mbuf *m0, const struct txpkts *txp, u_int available) 4077 { 4078 struct sge_eq *eq = &txq->eq; 4079 struct tx_sdesc *txsd; 4080 struct cpl_tx_pkt_core *cpl; 4081 uint32_t ctrl; 4082 uint64_t ctrl1; 4083 int ndesc, checkwrap; 4084 struct mbuf *m; 4085 void *flitp; 4086 4087 TXQ_LOCK_ASSERT_OWNED(txq); 4088 MPASS(txp->npkt > 0); 4089 MPASS(txp->plen < 65536); 4090 MPASS(m0 != NULL); 4091 MPASS(m0->m_nextpkt != NULL); 4092 MPASS(txp->len16 <= howmany(SGE_MAX_WR_LEN, 16)); 4093 MPASS(available > 0 && available < eq->sidx); 4094 4095 ndesc = howmany(txp->len16, EQ_ESIZE / 16); 4096 MPASS(ndesc <= available); 4097 4098 MPASS(wr == (void *)&eq->desc[eq->pidx]); 4099 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR)); 4100 ctrl = V_FW_WR_LEN16(txp->len16); 4101 wr->equiq_to_len16 = htobe32(ctrl); 4102 wr->plen = htobe16(txp->plen); 4103 wr->npkt = txp->npkt; 4104 wr->r3 = 0; 4105 wr->type = txp->wr_type; 4106 flitp = wr + 1; 4107 4108 /* 4109 * At this point we are 16B into a hardware descriptor. If checkwrap is 4110 * set then we know the WR is going to wrap around somewhere. We'll 4111 * check for that at appropriate points. 4112 */ 4113 checkwrap = eq->sidx - ndesc < eq->pidx; 4114 for (m = m0; m != NULL; m = m->m_nextpkt) { 4115 if (txp->wr_type == 0) { 4116 struct ulp_txpkt *ulpmc; 4117 struct ulptx_idata *ulpsc; 4118 4119 /* ULP master command */ 4120 ulpmc = flitp; 4121 ulpmc->cmd_dest = htobe32(V_ULPTX_CMD(ULP_TX_PKT) | 4122 V_ULP_TXPKT_DEST(0) | V_ULP_TXPKT_FID(eq->iqid)); 4123 ulpmc->len = htobe32(mbuf_len16(m)); 4124 4125 /* ULP subcommand */ 4126 ulpsc = (void *)(ulpmc + 1); 4127 ulpsc->cmd_more = htobe32(V_ULPTX_CMD(ULP_TX_SC_IMM) | 4128 F_ULP_TX_SC_MORE); 4129 ulpsc->len = htobe32(sizeof(struct cpl_tx_pkt_core)); 4130 4131 cpl = (void *)(ulpsc + 1); 4132 if (checkwrap && 4133 (uintptr_t)cpl == (uintptr_t)&eq->desc[eq->sidx]) 4134 cpl = (void *)&eq->desc[0]; 4135 txq->txpkts0_pkts += txp->npkt; 4136 txq->txpkts0_wrs++; 4137 } else { 4138 cpl = flitp; 4139 txq->txpkts1_pkts += txp->npkt; 4140 txq->txpkts1_wrs++; 4141 } 4142 4143 /* Checksum offload */ 4144 ctrl1 = 0; 4145 if (needs_l3_csum(m) == 0) 4146 ctrl1 |= F_TXPKT_IPCSUM_DIS; 4147 if (needs_l4_csum(m) == 0) 4148 ctrl1 |= F_TXPKT_L4CSUM_DIS; 4149 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | 4150 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO)) 4151 txq->txcsum++; /* some hardware assistance provided */ 4152 4153 /* VLAN tag insertion */ 4154 if (needs_vlan_insertion(m)) { 4155 ctrl1 |= F_TXPKT_VLAN_VLD | 4156 V_TXPKT_VLAN(m->m_pkthdr.ether_vtag); 4157 txq->vlan_insertion++; 4158 } 4159 4160 /* CPL header */ 4161 cpl->ctrl0 = txq->cpl_ctrl0; 4162 cpl->pack = 0; 4163 cpl->len = htobe16(m->m_pkthdr.len); 4164 cpl->ctrl1 = htobe64(ctrl1); 4165 4166 flitp = cpl + 1; 4167 if (checkwrap && 4168 (uintptr_t)flitp == (uintptr_t)&eq->desc[eq->sidx]) 4169 flitp = (void *)&eq->desc[0]; 4170 4171 write_gl_to_txd(txq, m, (caddr_t *)(&flitp), checkwrap); 4172 4173 } 4174 4175 txsd = &txq->sdesc[eq->pidx]; 4176 txsd->m = m0; 4177 txsd->desc_used = ndesc; 4178 4179 return (ndesc); 4180 } 4181 4182 /* 4183 * If the SGL ends on an address that is not 16 byte aligned, this function will 4184 * add a 0 filled flit at the end. 4185 */ 4186 static void 4187 write_gl_to_txd(struct sge_txq *txq, struct mbuf *m, caddr_t *to, int checkwrap) 4188 { 4189 struct sge_eq *eq = &txq->eq; 4190 struct sglist *gl = txq->gl; 4191 struct sglist_seg *seg; 4192 __be64 *flitp, *wrap; 4193 struct ulptx_sgl *usgl; 4194 int i, nflits, nsegs; 4195 4196 KASSERT(((uintptr_t)(*to) & 0xf) == 0, 4197 ("%s: SGL must start at a 16 byte boundary: %p", __func__, *to)); 4198 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]); 4199 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]); 4200 4201 get_pkt_gl(m, gl); 4202 nsegs = gl->sg_nseg; 4203 MPASS(nsegs > 0); 4204 4205 nflits = (3 * (nsegs - 1)) / 2 + ((nsegs - 1) & 1) + 2; 4206 flitp = (__be64 *)(*to); 4207 wrap = (__be64 *)(&eq->desc[eq->sidx]); 4208 seg = &gl->sg_segs[0]; 4209 usgl = (void *)flitp; 4210 4211 /* 4212 * We start at a 16 byte boundary somewhere inside the tx descriptor 4213 * ring, so we're at least 16 bytes away from the status page. There is 4214 * no chance of a wrap around in the middle of usgl (which is 16 bytes). 4215 */ 4216 4217 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 4218 V_ULPTX_NSGE(nsegs)); 4219 usgl->len0 = htobe32(seg->ss_len); 4220 usgl->addr0 = htobe64(seg->ss_paddr); 4221 seg++; 4222 4223 if (checkwrap == 0 || (uintptr_t)(flitp + nflits) <= (uintptr_t)wrap) { 4224 4225 /* Won't wrap around at all */ 4226 4227 for (i = 0; i < nsegs - 1; i++, seg++) { 4228 usgl->sge[i / 2].len[i & 1] = htobe32(seg->ss_len); 4229 usgl->sge[i / 2].addr[i & 1] = htobe64(seg->ss_paddr); 4230 } 4231 if (i & 1) 4232 usgl->sge[i / 2].len[1] = htobe32(0); 4233 flitp += nflits; 4234 } else { 4235 4236 /* Will wrap somewhere in the rest of the SGL */ 4237 4238 /* 2 flits already written, write the rest flit by flit */ 4239 flitp = (void *)(usgl + 1); 4240 for (i = 0; i < nflits - 2; i++) { 4241 if (flitp == wrap) 4242 flitp = (void *)eq->desc; 4243 *flitp++ = get_flit(seg, nsegs - 1, i); 4244 } 4245 } 4246 4247 if (nflits & 1) { 4248 MPASS(((uintptr_t)flitp) & 0xf); 4249 *flitp++ = 0; 4250 } 4251 4252 MPASS((((uintptr_t)flitp) & 0xf) == 0); 4253 if (__predict_false(flitp == wrap)) 4254 *to = (void *)eq->desc; 4255 else 4256 *to = (void *)flitp; 4257 } 4258 4259 static inline void 4260 copy_to_txd(struct sge_eq *eq, caddr_t from, caddr_t *to, int len) 4261 { 4262 4263 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]); 4264 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]); 4265 4266 if (__predict_true((uintptr_t)(*to) + len <= 4267 (uintptr_t)&eq->desc[eq->sidx])) { 4268 bcopy(from, *to, len); 4269 (*to) += len; 4270 } else { 4271 int portion = (uintptr_t)&eq->desc[eq->sidx] - (uintptr_t)(*to); 4272 4273 bcopy(from, *to, portion); 4274 from += portion; 4275 portion = len - portion; /* remaining */ 4276 bcopy(from, (void *)eq->desc, portion); 4277 (*to) = (caddr_t)eq->desc + portion; 4278 } 4279 } 4280 4281 static inline void 4282 ring_eq_db(struct adapter *sc, struct sge_eq *eq, u_int n) 4283 { 4284 u_int db; 4285 4286 MPASS(n > 0); 4287 4288 db = eq->doorbells; 4289 if (n > 1) 4290 clrbit(&db, DOORBELL_WCWR); 4291 wmb(); 4292 4293 switch (ffs(db) - 1) { 4294 case DOORBELL_UDB: 4295 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n)); 4296 break; 4297 4298 case DOORBELL_WCWR: { 4299 volatile uint64_t *dst, *src; 4300 int i; 4301 4302 /* 4303 * Queues whose 128B doorbell segment fits in the page do not 4304 * use relative qid (udb_qid is always 0). Only queues with 4305 * doorbell segments can do WCWR. 4306 */ 4307 KASSERT(eq->udb_qid == 0 && n == 1, 4308 ("%s: inappropriate doorbell (0x%x, %d, %d) for eq %p", 4309 __func__, eq->doorbells, n, eq->dbidx, eq)); 4310 4311 dst = (volatile void *)((uintptr_t)eq->udb + UDBS_WR_OFFSET - 4312 UDBS_DB_OFFSET); 4313 i = eq->dbidx; 4314 src = (void *)&eq->desc[i]; 4315 while (src != (void *)&eq->desc[i + 1]) 4316 *dst++ = *src++; 4317 wmb(); 4318 break; 4319 } 4320 4321 case DOORBELL_UDBWC: 4322 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n)); 4323 wmb(); 4324 break; 4325 4326 case DOORBELL_KDB: 4327 t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL), 4328 V_QID(eq->cntxt_id) | V_PIDX(n)); 4329 break; 4330 } 4331 4332 IDXINCR(eq->dbidx, n, eq->sidx); 4333 } 4334 4335 static inline u_int 4336 reclaimable_tx_desc(struct sge_eq *eq) 4337 { 4338 uint16_t hw_cidx; 4339 4340 hw_cidx = read_hw_cidx(eq); 4341 return (IDXDIFF(hw_cidx, eq->cidx, eq->sidx)); 4342 } 4343 4344 static inline u_int 4345 total_available_tx_desc(struct sge_eq *eq) 4346 { 4347 uint16_t hw_cidx, pidx; 4348 4349 hw_cidx = read_hw_cidx(eq); 4350 pidx = eq->pidx; 4351 4352 if (pidx == hw_cidx) 4353 return (eq->sidx - 1); 4354 else 4355 return (IDXDIFF(hw_cidx, pidx, eq->sidx) - 1); 4356 } 4357 4358 static inline uint16_t 4359 read_hw_cidx(struct sge_eq *eq) 4360 { 4361 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx]; 4362 uint16_t cidx = spg->cidx; /* stable snapshot */ 4363 4364 return (be16toh(cidx)); 4365 } 4366 4367 /* 4368 * Reclaim 'n' descriptors approximately. 4369 */ 4370 static u_int 4371 reclaim_tx_descs(struct sge_txq *txq, u_int n) 4372 { 4373 struct tx_sdesc *txsd; 4374 struct sge_eq *eq = &txq->eq; 4375 u_int can_reclaim, reclaimed; 4376 4377 TXQ_LOCK_ASSERT_OWNED(txq); 4378 MPASS(n > 0); 4379 4380 reclaimed = 0; 4381 can_reclaim = reclaimable_tx_desc(eq); 4382 while (can_reclaim && reclaimed < n) { 4383 int ndesc; 4384 struct mbuf *m, *nextpkt; 4385 4386 txsd = &txq->sdesc[eq->cidx]; 4387 ndesc = txsd->desc_used; 4388 4389 /* Firmware doesn't return "partial" credits. */ 4390 KASSERT(can_reclaim >= ndesc, 4391 ("%s: unexpected number of credits: %d, %d", 4392 __func__, can_reclaim, ndesc)); 4393 4394 for (m = txsd->m; m != NULL; m = nextpkt) { 4395 nextpkt = m->m_nextpkt; 4396 m->m_nextpkt = NULL; 4397 m_freem(m); 4398 } 4399 reclaimed += ndesc; 4400 can_reclaim -= ndesc; 4401 IDXINCR(eq->cidx, ndesc, eq->sidx); 4402 } 4403 4404 return (reclaimed); 4405 } 4406 4407 static void 4408 tx_reclaim(void *arg, int n) 4409 { 4410 struct sge_txq *txq = arg; 4411 struct sge_eq *eq = &txq->eq; 4412 4413 do { 4414 if (TXQ_TRYLOCK(txq) == 0) 4415 break; 4416 n = reclaim_tx_descs(txq, 32); 4417 if (eq->cidx == eq->pidx) 4418 eq->equeqidx = eq->pidx; 4419 TXQ_UNLOCK(txq); 4420 } while (n > 0); 4421 } 4422 4423 static __be64 4424 get_flit(struct sglist_seg *segs, int nsegs, int idx) 4425 { 4426 int i = (idx / 3) * 2; 4427 4428 switch (idx % 3) { 4429 case 0: { 4430 __be64 rc; 4431 4432 rc = htobe32(segs[i].ss_len); 4433 if (i + 1 < nsegs) 4434 rc |= (uint64_t)htobe32(segs[i + 1].ss_len) << 32; 4435 4436 return (rc); 4437 } 4438 case 1: 4439 return (htobe64(segs[i].ss_paddr)); 4440 case 2: 4441 return (htobe64(segs[i + 1].ss_paddr)); 4442 } 4443 4444 return (0); 4445 } 4446 4447 static void 4448 find_best_refill_source(struct adapter *sc, struct sge_fl *fl, int maxp) 4449 { 4450 int8_t zidx, hwidx, idx; 4451 uint16_t region1, region3; 4452 int spare, spare_needed, n; 4453 struct sw_zone_info *swz; 4454 struct hw_buf_info *hwb, *hwb_list = &sc->sge.hw_buf_info[0]; 4455 4456 /* 4457 * Buffer Packing: Look for PAGE_SIZE or larger zone which has a bufsize 4458 * large enough for the max payload and cluster metadata. Otherwise 4459 * settle for the largest bufsize that leaves enough room in the cluster 4460 * for metadata. 4461 * 4462 * Without buffer packing: Look for the smallest zone which has a 4463 * bufsize large enough for the max payload. Settle for the largest 4464 * bufsize available if there's nothing big enough for max payload. 4465 */ 4466 spare_needed = fl->flags & FL_BUF_PACKING ? CL_METADATA_SIZE : 0; 4467 swz = &sc->sge.sw_zone_info[0]; 4468 hwidx = -1; 4469 for (zidx = 0; zidx < SW_ZONE_SIZES; zidx++, swz++) { 4470 if (swz->size > largest_rx_cluster) { 4471 if (__predict_true(hwidx != -1)) 4472 break; 4473 4474 /* 4475 * This is a misconfiguration. largest_rx_cluster is 4476 * preventing us from finding a refill source. See 4477 * dev.t5nex.<n>.buffer_sizes to figure out why. 4478 */ 4479 device_printf(sc->dev, "largest_rx_cluster=%u leaves no" 4480 " refill source for fl %p (dma %u). Ignored.\n", 4481 largest_rx_cluster, fl, maxp); 4482 } 4483 for (idx = swz->head_hwidx; idx != -1; idx = hwb->next) { 4484 hwb = &hwb_list[idx]; 4485 spare = swz->size - hwb->size; 4486 if (spare < spare_needed) 4487 continue; 4488 4489 hwidx = idx; /* best option so far */ 4490 if (hwb->size >= maxp) { 4491 4492 if ((fl->flags & FL_BUF_PACKING) == 0) 4493 goto done; /* stop looking (not packing) */ 4494 4495 if (swz->size >= safest_rx_cluster) 4496 goto done; /* stop looking (packing) */ 4497 } 4498 break; /* keep looking, next zone */ 4499 } 4500 } 4501 done: 4502 /* A usable hwidx has been located. */ 4503 MPASS(hwidx != -1); 4504 hwb = &hwb_list[hwidx]; 4505 zidx = hwb->zidx; 4506 swz = &sc->sge.sw_zone_info[zidx]; 4507 region1 = 0; 4508 region3 = swz->size - hwb->size; 4509 4510 /* 4511 * Stay within this zone and see if there is a better match when mbuf 4512 * inlining is allowed. Remember that the hwidx's are sorted in 4513 * decreasing order of size (so in increasing order of spare area). 4514 */ 4515 for (idx = hwidx; idx != -1; idx = hwb->next) { 4516 hwb = &hwb_list[idx]; 4517 spare = swz->size - hwb->size; 4518 4519 if (allow_mbufs_in_cluster == 0 || hwb->size < maxp) 4520 break; 4521 4522 /* 4523 * Do not inline mbufs if doing so would violate the pad/pack 4524 * boundary alignment requirement. 4525 */ 4526 if (fl_pad && (MSIZE % sc->sge.pad_boundary) != 0) 4527 continue; 4528 if (fl->flags & FL_BUF_PACKING && 4529 (MSIZE % sc->sge.pack_boundary) != 0) 4530 continue; 4531 4532 if (spare < CL_METADATA_SIZE + MSIZE) 4533 continue; 4534 n = (spare - CL_METADATA_SIZE) / MSIZE; 4535 if (n > howmany(hwb->size, maxp)) 4536 break; 4537 4538 hwidx = idx; 4539 if (fl->flags & FL_BUF_PACKING) { 4540 region1 = n * MSIZE; 4541 region3 = spare - region1; 4542 } else { 4543 region1 = MSIZE; 4544 region3 = spare - region1; 4545 break; 4546 } 4547 } 4548 4549 KASSERT(zidx >= 0 && zidx < SW_ZONE_SIZES, 4550 ("%s: bad zone %d for fl %p, maxp %d", __func__, zidx, fl, maxp)); 4551 KASSERT(hwidx >= 0 && hwidx <= SGE_FLBUF_SIZES, 4552 ("%s: bad hwidx %d for fl %p, maxp %d", __func__, hwidx, fl, maxp)); 4553 KASSERT(region1 + sc->sge.hw_buf_info[hwidx].size + region3 == 4554 sc->sge.sw_zone_info[zidx].size, 4555 ("%s: bad buffer layout for fl %p, maxp %d. " 4556 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp, 4557 sc->sge.sw_zone_info[zidx].size, region1, 4558 sc->sge.hw_buf_info[hwidx].size, region3)); 4559 if (fl->flags & FL_BUF_PACKING || region1 > 0) { 4560 KASSERT(region3 >= CL_METADATA_SIZE, 4561 ("%s: no room for metadata. fl %p, maxp %d; " 4562 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp, 4563 sc->sge.sw_zone_info[zidx].size, region1, 4564 sc->sge.hw_buf_info[hwidx].size, region3)); 4565 KASSERT(region1 % MSIZE == 0, 4566 ("%s: bad mbuf region for fl %p, maxp %d. " 4567 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp, 4568 sc->sge.sw_zone_info[zidx].size, region1, 4569 sc->sge.hw_buf_info[hwidx].size, region3)); 4570 } 4571 4572 fl->cll_def.zidx = zidx; 4573 fl->cll_def.hwidx = hwidx; 4574 fl->cll_def.region1 = region1; 4575 fl->cll_def.region3 = region3; 4576 } 4577 4578 static void 4579 find_safe_refill_source(struct adapter *sc, struct sge_fl *fl) 4580 { 4581 struct sge *s = &sc->sge; 4582 struct hw_buf_info *hwb; 4583 struct sw_zone_info *swz; 4584 int spare; 4585 int8_t hwidx; 4586 4587 if (fl->flags & FL_BUF_PACKING) 4588 hwidx = s->safe_hwidx2; /* with room for metadata */ 4589 else if (allow_mbufs_in_cluster && s->safe_hwidx2 != -1) { 4590 hwidx = s->safe_hwidx2; 4591 hwb = &s->hw_buf_info[hwidx]; 4592 swz = &s->sw_zone_info[hwb->zidx]; 4593 spare = swz->size - hwb->size; 4594 4595 /* no good if there isn't room for an mbuf as well */ 4596 if (spare < CL_METADATA_SIZE + MSIZE) 4597 hwidx = s->safe_hwidx1; 4598 } else 4599 hwidx = s->safe_hwidx1; 4600 4601 if (hwidx == -1) { 4602 /* No fallback source */ 4603 fl->cll_alt.hwidx = -1; 4604 fl->cll_alt.zidx = -1; 4605 4606 return; 4607 } 4608 4609 hwb = &s->hw_buf_info[hwidx]; 4610 swz = &s->sw_zone_info[hwb->zidx]; 4611 spare = swz->size - hwb->size; 4612 fl->cll_alt.hwidx = hwidx; 4613 fl->cll_alt.zidx = hwb->zidx; 4614 if (allow_mbufs_in_cluster && 4615 (fl_pad == 0 || (MSIZE % sc->sge.pad_boundary) == 0)) 4616 fl->cll_alt.region1 = ((spare - CL_METADATA_SIZE) / MSIZE) * MSIZE; 4617 else 4618 fl->cll_alt.region1 = 0; 4619 fl->cll_alt.region3 = spare - fl->cll_alt.region1; 4620 } 4621 4622 static void 4623 add_fl_to_sfl(struct adapter *sc, struct sge_fl *fl) 4624 { 4625 mtx_lock(&sc->sfl_lock); 4626 FL_LOCK(fl); 4627 if ((fl->flags & FL_DOOMED) == 0) { 4628 fl->flags |= FL_STARVING; 4629 TAILQ_INSERT_TAIL(&sc->sfl, fl, link); 4630 callout_reset(&sc->sfl_callout, hz / 5, refill_sfl, sc); 4631 } 4632 FL_UNLOCK(fl); 4633 mtx_unlock(&sc->sfl_lock); 4634 } 4635 4636 static void 4637 handle_wrq_egr_update(struct adapter *sc, struct sge_eq *eq) 4638 { 4639 struct sge_wrq *wrq = (void *)eq; 4640 4641 atomic_readandclear_int(&eq->equiq); 4642 taskqueue_enqueue(sc->tq[eq->tx_chan], &wrq->wrq_tx_task); 4643 } 4644 4645 static void 4646 handle_eth_egr_update(struct adapter *sc, struct sge_eq *eq) 4647 { 4648 struct sge_txq *txq = (void *)eq; 4649 4650 MPASS((eq->flags & EQ_TYPEMASK) == EQ_ETH); 4651 4652 atomic_readandclear_int(&eq->equiq); 4653 mp_ring_check_drainage(txq->r, 0); 4654 taskqueue_enqueue(sc->tq[eq->tx_chan], &txq->tx_reclaim_task); 4655 } 4656 4657 static int 4658 handle_sge_egr_update(struct sge_iq *iq, const struct rss_header *rss, 4659 struct mbuf *m) 4660 { 4661 const struct cpl_sge_egr_update *cpl = (const void *)(rss + 1); 4662 unsigned int qid = G_EGR_QID(ntohl(cpl->opcode_qid)); 4663 struct adapter *sc = iq->adapter; 4664 struct sge *s = &sc->sge; 4665 struct sge_eq *eq; 4666 static void (*h[])(struct adapter *, struct sge_eq *) = {NULL, 4667 &handle_wrq_egr_update, &handle_eth_egr_update, 4668 &handle_wrq_egr_update}; 4669 4670 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 4671 rss->opcode)); 4672 4673 eq = s->eqmap[qid - s->eq_start]; 4674 (*h[eq->flags & EQ_TYPEMASK])(sc, eq); 4675 4676 return (0); 4677 } 4678 4679 /* handle_fw_msg works for both fw4_msg and fw6_msg because this is valid */ 4680 CTASSERT(offsetof(struct cpl_fw4_msg, data) == \ 4681 offsetof(struct cpl_fw6_msg, data)); 4682 4683 static int 4684 handle_fw_msg(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 4685 { 4686 struct adapter *sc = iq->adapter; 4687 const struct cpl_fw6_msg *cpl = (const void *)(rss + 1); 4688 4689 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 4690 rss->opcode)); 4691 4692 if (cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL) { 4693 const struct rss_header *rss2; 4694 4695 rss2 = (const struct rss_header *)&cpl->data[0]; 4696 return (sc->cpl_handler[rss2->opcode](iq, rss2, m)); 4697 } 4698 4699 return (sc->fw_msg_handler[cpl->type](sc, &cpl->data[0])); 4700 } 4701 4702 static int 4703 sysctl_uint16(SYSCTL_HANDLER_ARGS) 4704 { 4705 uint16_t *id = arg1; 4706 int i = *id; 4707 4708 return sysctl_handle_int(oidp, &i, 0, req); 4709 } 4710 4711 static int 4712 sysctl_bufsizes(SYSCTL_HANDLER_ARGS) 4713 { 4714 struct sge *s = arg1; 4715 struct hw_buf_info *hwb = &s->hw_buf_info[0]; 4716 struct sw_zone_info *swz = &s->sw_zone_info[0]; 4717 int i, rc; 4718 struct sbuf sb; 4719 char c; 4720 4721 sbuf_new(&sb, NULL, 32, SBUF_AUTOEXTEND); 4722 for (i = 0; i < SGE_FLBUF_SIZES; i++, hwb++) { 4723 if (hwb->zidx >= 0 && swz[hwb->zidx].size <= largest_rx_cluster) 4724 c = '*'; 4725 else 4726 c = '\0'; 4727 4728 sbuf_printf(&sb, "%u%c ", hwb->size, c); 4729 } 4730 sbuf_trim(&sb); 4731 sbuf_finish(&sb); 4732 rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req); 4733 sbuf_delete(&sb); 4734 return (rc); 4735 } 4736