1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 Chelsio Communications, Inc. 5 * All rights reserved. 6 * Written by: Navdeep Parhar <np@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include "opt_inet.h" 34 #include "opt_inet6.h" 35 #include "opt_ratelimit.h" 36 37 #include <sys/types.h> 38 #include <sys/eventhandler.h> 39 #include <sys/mbuf.h> 40 #include <sys/socket.h> 41 #include <sys/kernel.h> 42 #include <sys/malloc.h> 43 #include <sys/queue.h> 44 #include <sys/sbuf.h> 45 #include <sys/taskqueue.h> 46 #include <sys/time.h> 47 #include <sys/sglist.h> 48 #include <sys/sysctl.h> 49 #include <sys/smp.h> 50 #include <sys/counter.h> 51 #include <net/bpf.h> 52 #include <net/ethernet.h> 53 #include <net/if.h> 54 #include <net/if_vlan_var.h> 55 #include <netinet/in.h> 56 #include <netinet/ip.h> 57 #include <netinet/ip6.h> 58 #include <netinet/tcp.h> 59 #include <netinet/udp.h> 60 #include <machine/in_cksum.h> 61 #include <machine/md_var.h> 62 #include <vm/vm.h> 63 #include <vm/pmap.h> 64 #ifdef DEV_NETMAP 65 #include <machine/bus.h> 66 #include <sys/selinfo.h> 67 #include <net/if_var.h> 68 #include <net/netmap.h> 69 #include <dev/netmap/netmap_kern.h> 70 #endif 71 72 #include "common/common.h" 73 #include "common/t4_regs.h" 74 #include "common/t4_regs_values.h" 75 #include "common/t4_msg.h" 76 #include "t4_l2t.h" 77 #include "t4_mp_ring.h" 78 79 #ifdef T4_PKT_TIMESTAMP 80 #define RX_COPY_THRESHOLD (MINCLSIZE - 8) 81 #else 82 #define RX_COPY_THRESHOLD MINCLSIZE 83 #endif 84 85 /* Internal mbuf flags stored in PH_loc.eight[1]. */ 86 #define MC_NOMAP 0x01 87 #define MC_RAW_WR 0x02 88 89 /* 90 * Ethernet frames are DMA'd at this byte offset into the freelist buffer. 91 * 0-7 are valid values. 92 */ 93 static int fl_pktshift = 0; 94 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pktshift, CTLFLAG_RDTUN, &fl_pktshift, 0, 95 "payload DMA offset in rx buffer (bytes)"); 96 97 /* 98 * Pad ethernet payload up to this boundary. 99 * -1: driver should figure out a good value. 100 * 0: disable padding. 101 * Any power of 2 from 32 to 4096 (both inclusive) is also a valid value. 102 */ 103 int fl_pad = -1; 104 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pad, CTLFLAG_RDTUN, &fl_pad, 0, 105 "payload pad boundary (bytes)"); 106 107 /* 108 * Status page length. 109 * -1: driver should figure out a good value. 110 * 64 or 128 are the only other valid values. 111 */ 112 static int spg_len = -1; 113 SYSCTL_INT(_hw_cxgbe, OID_AUTO, spg_len, CTLFLAG_RDTUN, &spg_len, 0, 114 "status page size (bytes)"); 115 116 /* 117 * Congestion drops. 118 * -1: no congestion feedback (not recommended). 119 * 0: backpressure the channel instead of dropping packets right away. 120 * 1: no backpressure, drop packets for the congested queue immediately. 121 */ 122 static int cong_drop = 0; 123 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cong_drop, CTLFLAG_RDTUN, &cong_drop, 0, 124 "Congestion control for RX queues (0 = backpressure, 1 = drop"); 125 126 /* 127 * Deliver multiple frames in the same free list buffer if they fit. 128 * -1: let the driver decide whether to enable buffer packing or not. 129 * 0: disable buffer packing. 130 * 1: enable buffer packing. 131 */ 132 static int buffer_packing = -1; 133 SYSCTL_INT(_hw_cxgbe, OID_AUTO, buffer_packing, CTLFLAG_RDTUN, &buffer_packing, 134 0, "Enable buffer packing"); 135 136 /* 137 * Start next frame in a packed buffer at this boundary. 138 * -1: driver should figure out a good value. 139 * T4: driver will ignore this and use the same value as fl_pad above. 140 * T5: 16, or a power of 2 from 64 to 4096 (both inclusive) is a valid value. 141 */ 142 static int fl_pack = -1; 143 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pack, CTLFLAG_RDTUN, &fl_pack, 0, 144 "payload pack boundary (bytes)"); 145 146 /* 147 * Allow the driver to create mbuf(s) in a cluster allocated for rx. 148 * 0: never; always allocate mbufs from the zone_mbuf UMA zone. 149 * 1: ok to create mbuf(s) within a cluster if there is room. 150 */ 151 static int allow_mbufs_in_cluster = 1; 152 SYSCTL_INT(_hw_cxgbe, OID_AUTO, allow_mbufs_in_cluster, CTLFLAG_RDTUN, 153 &allow_mbufs_in_cluster, 0, 154 "Allow driver to create mbufs within a rx cluster"); 155 156 /* 157 * Largest rx cluster size that the driver is allowed to allocate. 158 */ 159 static int largest_rx_cluster = MJUM16BYTES; 160 SYSCTL_INT(_hw_cxgbe, OID_AUTO, largest_rx_cluster, CTLFLAG_RDTUN, 161 &largest_rx_cluster, 0, "Largest rx cluster (bytes)"); 162 163 /* 164 * Size of cluster allocation that's most likely to succeed. The driver will 165 * fall back to this size if it fails to allocate clusters larger than this. 166 */ 167 static int safest_rx_cluster = PAGE_SIZE; 168 SYSCTL_INT(_hw_cxgbe, OID_AUTO, safest_rx_cluster, CTLFLAG_RDTUN, 169 &safest_rx_cluster, 0, "Safe rx cluster (bytes)"); 170 171 #ifdef RATELIMIT 172 /* 173 * Knob to control TCP timestamp rewriting, and the granularity of the tick used 174 * for rewriting. -1 and 0-3 are all valid values. 175 * -1: hardware should leave the TCP timestamps alone. 176 * 0: 1ms 177 * 1: 100us 178 * 2: 10us 179 * 3: 1us 180 */ 181 static int tsclk = -1; 182 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tsclk, CTLFLAG_RDTUN, &tsclk, 0, 183 "Control TCP timestamp rewriting when using pacing"); 184 185 static int eo_max_backlog = 1024 * 1024; 186 SYSCTL_INT(_hw_cxgbe, OID_AUTO, eo_max_backlog, CTLFLAG_RDTUN, &eo_max_backlog, 187 0, "Maximum backlog of ratelimited data per flow"); 188 #endif 189 190 /* 191 * The interrupt holdoff timers are multiplied by this value on T6+. 192 * 1 and 3-17 (both inclusive) are legal values. 193 */ 194 static int tscale = 1; 195 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tscale, CTLFLAG_RDTUN, &tscale, 0, 196 "Interrupt holdoff timer scale on T6+"); 197 198 /* 199 * Number of LRO entries in the lro_ctrl structure per rx queue. 200 */ 201 static int lro_entries = TCP_LRO_ENTRIES; 202 SYSCTL_INT(_hw_cxgbe, OID_AUTO, lro_entries, CTLFLAG_RDTUN, &lro_entries, 0, 203 "Number of LRO entries per RX queue"); 204 205 /* 206 * This enables presorting of frames before they're fed into tcp_lro_rx. 207 */ 208 static int lro_mbufs = 0; 209 SYSCTL_INT(_hw_cxgbe, OID_AUTO, lro_mbufs, CTLFLAG_RDTUN, &lro_mbufs, 0, 210 "Enable presorting of LRO frames"); 211 212 struct txpkts { 213 u_int wr_type; /* type 0 or type 1 */ 214 u_int npkt; /* # of packets in this work request */ 215 u_int plen; /* total payload (sum of all packets) */ 216 u_int len16; /* # of 16B pieces used by this work request */ 217 }; 218 219 /* A packet's SGL. This + m_pkthdr has all info needed for tx */ 220 struct sgl { 221 struct sglist sg; 222 struct sglist_seg seg[TX_SGL_SEGS]; 223 }; 224 225 static int service_iq(struct sge_iq *, int); 226 static int service_iq_fl(struct sge_iq *, int); 227 static struct mbuf *get_fl_payload(struct adapter *, struct sge_fl *, uint32_t); 228 static int t4_eth_rx(struct sge_iq *, const struct rss_header *, struct mbuf *); 229 static inline void init_iq(struct sge_iq *, struct adapter *, int, int, int); 230 static inline void init_fl(struct adapter *, struct sge_fl *, int, int, char *); 231 static inline void init_eq(struct adapter *, struct sge_eq *, int, int, uint8_t, 232 uint16_t, char *); 233 static int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *, 234 bus_addr_t *, void **); 235 static int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 236 void *); 237 static int alloc_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *, 238 int, int); 239 static int free_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *); 240 static void add_iq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *, 241 struct sge_iq *); 242 static void add_fl_sysctls(struct adapter *, struct sysctl_ctx_list *, 243 struct sysctl_oid *, struct sge_fl *); 244 static int alloc_fwq(struct adapter *); 245 static int free_fwq(struct adapter *); 246 static int alloc_ctrlq(struct adapter *, struct sge_wrq *, int, 247 struct sysctl_oid *); 248 static int alloc_rxq(struct vi_info *, struct sge_rxq *, int, int, 249 struct sysctl_oid *); 250 static int free_rxq(struct vi_info *, struct sge_rxq *); 251 #ifdef TCP_OFFLOAD 252 static int alloc_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *, int, int, 253 struct sysctl_oid *); 254 static int free_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *); 255 #endif 256 #ifdef DEV_NETMAP 257 static int alloc_nm_rxq(struct vi_info *, struct sge_nm_rxq *, int, int, 258 struct sysctl_oid *); 259 static int free_nm_rxq(struct vi_info *, struct sge_nm_rxq *); 260 static int alloc_nm_txq(struct vi_info *, struct sge_nm_txq *, int, int, 261 struct sysctl_oid *); 262 static int free_nm_txq(struct vi_info *, struct sge_nm_txq *); 263 #endif 264 static int ctrl_eq_alloc(struct adapter *, struct sge_eq *); 265 static int eth_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *); 266 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 267 static int ofld_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *); 268 #endif 269 static int alloc_eq(struct adapter *, struct vi_info *, struct sge_eq *); 270 static int free_eq(struct adapter *, struct sge_eq *); 271 static int alloc_wrq(struct adapter *, struct vi_info *, struct sge_wrq *, 272 struct sysctl_oid *); 273 static int free_wrq(struct adapter *, struct sge_wrq *); 274 static int alloc_txq(struct vi_info *, struct sge_txq *, int, 275 struct sysctl_oid *); 276 static int free_txq(struct vi_info *, struct sge_txq *); 277 static void oneseg_dma_callback(void *, bus_dma_segment_t *, int, int); 278 static inline void ring_fl_db(struct adapter *, struct sge_fl *); 279 static int refill_fl(struct adapter *, struct sge_fl *, int); 280 static void refill_sfl(void *); 281 static int alloc_fl_sdesc(struct sge_fl *); 282 static void free_fl_sdesc(struct adapter *, struct sge_fl *); 283 static void find_best_refill_source(struct adapter *, struct sge_fl *, int); 284 static void find_safe_refill_source(struct adapter *, struct sge_fl *); 285 static void add_fl_to_sfl(struct adapter *, struct sge_fl *); 286 287 static inline void get_pkt_gl(struct mbuf *, struct sglist *); 288 static inline u_int txpkt_len16(u_int, u_int); 289 static inline u_int txpkt_vm_len16(u_int, u_int); 290 static inline u_int txpkts0_len16(u_int); 291 static inline u_int txpkts1_len16(void); 292 static u_int write_raw_wr(struct sge_txq *, void *, struct mbuf *, u_int); 293 static u_int write_txpkt_wr(struct sge_txq *, struct fw_eth_tx_pkt_wr *, 294 struct mbuf *, u_int); 295 static u_int write_txpkt_vm_wr(struct adapter *, struct sge_txq *, 296 struct fw_eth_tx_pkt_vm_wr *, struct mbuf *, u_int); 297 static int try_txpkts(struct mbuf *, struct mbuf *, struct txpkts *, u_int); 298 static int add_to_txpkts(struct mbuf *, struct txpkts *, u_int); 299 static u_int write_txpkts_wr(struct sge_txq *, struct fw_eth_tx_pkts_wr *, 300 struct mbuf *, const struct txpkts *, u_int); 301 static void write_gl_to_txd(struct sge_txq *, struct mbuf *, caddr_t *, int); 302 static inline void copy_to_txd(struct sge_eq *, caddr_t, caddr_t *, int); 303 static inline void ring_eq_db(struct adapter *, struct sge_eq *, u_int); 304 static inline uint16_t read_hw_cidx(struct sge_eq *); 305 static inline u_int reclaimable_tx_desc(struct sge_eq *); 306 static inline u_int total_available_tx_desc(struct sge_eq *); 307 static u_int reclaim_tx_descs(struct sge_txq *, u_int); 308 static void tx_reclaim(void *, int); 309 static __be64 get_flit(struct sglist_seg *, int, int); 310 static int handle_sge_egr_update(struct sge_iq *, const struct rss_header *, 311 struct mbuf *); 312 static int handle_fw_msg(struct sge_iq *, const struct rss_header *, 313 struct mbuf *); 314 static int t4_handle_wrerr_rpl(struct adapter *, const __be64 *); 315 static void wrq_tx_drain(void *, int); 316 static void drain_wrq_wr_list(struct adapter *, struct sge_wrq *); 317 318 static int sysctl_uint16(SYSCTL_HANDLER_ARGS); 319 static int sysctl_bufsizes(SYSCTL_HANDLER_ARGS); 320 #ifdef RATELIMIT 321 static inline u_int txpkt_eo_len16(u_int, u_int, u_int); 322 static int ethofld_fw4_ack(struct sge_iq *, const struct rss_header *, 323 struct mbuf *); 324 #endif 325 326 static counter_u64_t extfree_refs; 327 static counter_u64_t extfree_rels; 328 329 an_handler_t t4_an_handler; 330 fw_msg_handler_t t4_fw_msg_handler[NUM_FW6_TYPES]; 331 cpl_handler_t t4_cpl_handler[NUM_CPL_CMDS]; 332 cpl_handler_t set_tcb_rpl_handlers[NUM_CPL_COOKIES]; 333 cpl_handler_t l2t_write_rpl_handlers[NUM_CPL_COOKIES]; 334 cpl_handler_t act_open_rpl_handlers[NUM_CPL_COOKIES]; 335 cpl_handler_t abort_rpl_rss_handlers[NUM_CPL_COOKIES]; 336 cpl_handler_t fw4_ack_handlers[NUM_CPL_COOKIES]; 337 338 void 339 t4_register_an_handler(an_handler_t h) 340 { 341 uintptr_t *loc; 342 343 MPASS(h == NULL || t4_an_handler == NULL); 344 345 loc = (uintptr_t *)&t4_an_handler; 346 atomic_store_rel_ptr(loc, (uintptr_t)h); 347 } 348 349 void 350 t4_register_fw_msg_handler(int type, fw_msg_handler_t h) 351 { 352 uintptr_t *loc; 353 354 MPASS(type < nitems(t4_fw_msg_handler)); 355 MPASS(h == NULL || t4_fw_msg_handler[type] == NULL); 356 /* 357 * These are dispatched by the handler for FW{4|6}_CPL_MSG using the CPL 358 * handler dispatch table. Reject any attempt to install a handler for 359 * this subtype. 360 */ 361 MPASS(type != FW_TYPE_RSSCPL); 362 MPASS(type != FW6_TYPE_RSSCPL); 363 364 loc = (uintptr_t *)&t4_fw_msg_handler[type]; 365 atomic_store_rel_ptr(loc, (uintptr_t)h); 366 } 367 368 void 369 t4_register_cpl_handler(int opcode, cpl_handler_t h) 370 { 371 uintptr_t *loc; 372 373 MPASS(opcode < nitems(t4_cpl_handler)); 374 MPASS(h == NULL || t4_cpl_handler[opcode] == NULL); 375 376 loc = (uintptr_t *)&t4_cpl_handler[opcode]; 377 atomic_store_rel_ptr(loc, (uintptr_t)h); 378 } 379 380 static int 381 set_tcb_rpl_handler(struct sge_iq *iq, const struct rss_header *rss, 382 struct mbuf *m) 383 { 384 const struct cpl_set_tcb_rpl *cpl = (const void *)(rss + 1); 385 u_int tid; 386 int cookie; 387 388 MPASS(m == NULL); 389 390 tid = GET_TID(cpl); 391 if (is_hpftid(iq->adapter, tid) || is_ftid(iq->adapter, tid)) { 392 /* 393 * The return code for filter-write is put in the CPL cookie so 394 * we have to rely on the hardware tid (is_ftid) to determine 395 * that this is a response to a filter. 396 */ 397 cookie = CPL_COOKIE_FILTER; 398 } else { 399 cookie = G_COOKIE(cpl->cookie); 400 } 401 MPASS(cookie > CPL_COOKIE_RESERVED); 402 MPASS(cookie < nitems(set_tcb_rpl_handlers)); 403 404 return (set_tcb_rpl_handlers[cookie](iq, rss, m)); 405 } 406 407 static int 408 l2t_write_rpl_handler(struct sge_iq *iq, const struct rss_header *rss, 409 struct mbuf *m) 410 { 411 const struct cpl_l2t_write_rpl *rpl = (const void *)(rss + 1); 412 unsigned int cookie; 413 414 MPASS(m == NULL); 415 416 cookie = GET_TID(rpl) & F_SYNC_WR ? CPL_COOKIE_TOM : CPL_COOKIE_FILTER; 417 return (l2t_write_rpl_handlers[cookie](iq, rss, m)); 418 } 419 420 static int 421 act_open_rpl_handler(struct sge_iq *iq, const struct rss_header *rss, 422 struct mbuf *m) 423 { 424 const struct cpl_act_open_rpl *cpl = (const void *)(rss + 1); 425 u_int cookie = G_TID_COOKIE(G_AOPEN_ATID(be32toh(cpl->atid_status))); 426 427 MPASS(m == NULL); 428 MPASS(cookie != CPL_COOKIE_RESERVED); 429 430 return (act_open_rpl_handlers[cookie](iq, rss, m)); 431 } 432 433 static int 434 abort_rpl_rss_handler(struct sge_iq *iq, const struct rss_header *rss, 435 struct mbuf *m) 436 { 437 struct adapter *sc = iq->adapter; 438 u_int cookie; 439 440 MPASS(m == NULL); 441 if (is_hashfilter(sc)) 442 cookie = CPL_COOKIE_HASHFILTER; 443 else 444 cookie = CPL_COOKIE_TOM; 445 446 return (abort_rpl_rss_handlers[cookie](iq, rss, m)); 447 } 448 449 static int 450 fw4_ack_handler(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 451 { 452 struct adapter *sc = iq->adapter; 453 const struct cpl_fw4_ack *cpl = (const void *)(rss + 1); 454 unsigned int tid = G_CPL_FW4_ACK_FLOWID(be32toh(OPCODE_TID(cpl))); 455 u_int cookie; 456 457 MPASS(m == NULL); 458 if (is_etid(sc, tid)) 459 cookie = CPL_COOKIE_ETHOFLD; 460 else 461 cookie = CPL_COOKIE_TOM; 462 463 return (fw4_ack_handlers[cookie](iq, rss, m)); 464 } 465 466 static void 467 t4_init_shared_cpl_handlers(void) 468 { 469 470 t4_register_cpl_handler(CPL_SET_TCB_RPL, set_tcb_rpl_handler); 471 t4_register_cpl_handler(CPL_L2T_WRITE_RPL, l2t_write_rpl_handler); 472 t4_register_cpl_handler(CPL_ACT_OPEN_RPL, act_open_rpl_handler); 473 t4_register_cpl_handler(CPL_ABORT_RPL_RSS, abort_rpl_rss_handler); 474 t4_register_cpl_handler(CPL_FW4_ACK, fw4_ack_handler); 475 } 476 477 void 478 t4_register_shared_cpl_handler(int opcode, cpl_handler_t h, int cookie) 479 { 480 uintptr_t *loc; 481 482 MPASS(opcode < nitems(t4_cpl_handler)); 483 MPASS(cookie > CPL_COOKIE_RESERVED); 484 MPASS(cookie < NUM_CPL_COOKIES); 485 MPASS(t4_cpl_handler[opcode] != NULL); 486 487 switch (opcode) { 488 case CPL_SET_TCB_RPL: 489 loc = (uintptr_t *)&set_tcb_rpl_handlers[cookie]; 490 break; 491 case CPL_L2T_WRITE_RPL: 492 loc = (uintptr_t *)&l2t_write_rpl_handlers[cookie]; 493 break; 494 case CPL_ACT_OPEN_RPL: 495 loc = (uintptr_t *)&act_open_rpl_handlers[cookie]; 496 break; 497 case CPL_ABORT_RPL_RSS: 498 loc = (uintptr_t *)&abort_rpl_rss_handlers[cookie]; 499 break; 500 case CPL_FW4_ACK: 501 loc = (uintptr_t *)&fw4_ack_handlers[cookie]; 502 break; 503 default: 504 MPASS(0); 505 return; 506 } 507 MPASS(h == NULL || *loc == (uintptr_t)NULL); 508 atomic_store_rel_ptr(loc, (uintptr_t)h); 509 } 510 511 /* 512 * Called on MOD_LOAD. Validates and calculates the SGE tunables. 513 */ 514 void 515 t4_sge_modload(void) 516 { 517 518 if (fl_pktshift < 0 || fl_pktshift > 7) { 519 printf("Invalid hw.cxgbe.fl_pktshift value (%d)," 520 " using 0 instead.\n", fl_pktshift); 521 fl_pktshift = 0; 522 } 523 524 if (spg_len != 64 && spg_len != 128) { 525 int len; 526 527 #if defined(__i386__) || defined(__amd64__) 528 len = cpu_clflush_line_size > 64 ? 128 : 64; 529 #else 530 len = 64; 531 #endif 532 if (spg_len != -1) { 533 printf("Invalid hw.cxgbe.spg_len value (%d)," 534 " using %d instead.\n", spg_len, len); 535 } 536 spg_len = len; 537 } 538 539 if (cong_drop < -1 || cong_drop > 1) { 540 printf("Invalid hw.cxgbe.cong_drop value (%d)," 541 " using 0 instead.\n", cong_drop); 542 cong_drop = 0; 543 } 544 545 if (tscale != 1 && (tscale < 3 || tscale > 17)) { 546 printf("Invalid hw.cxgbe.tscale value (%d)," 547 " using 1 instead.\n", tscale); 548 tscale = 1; 549 } 550 551 extfree_refs = counter_u64_alloc(M_WAITOK); 552 extfree_rels = counter_u64_alloc(M_WAITOK); 553 counter_u64_zero(extfree_refs); 554 counter_u64_zero(extfree_rels); 555 556 t4_init_shared_cpl_handlers(); 557 t4_register_cpl_handler(CPL_FW4_MSG, handle_fw_msg); 558 t4_register_cpl_handler(CPL_FW6_MSG, handle_fw_msg); 559 t4_register_cpl_handler(CPL_SGE_EGR_UPDATE, handle_sge_egr_update); 560 t4_register_cpl_handler(CPL_RX_PKT, t4_eth_rx); 561 #ifdef RATELIMIT 562 t4_register_shared_cpl_handler(CPL_FW4_ACK, ethofld_fw4_ack, 563 CPL_COOKIE_ETHOFLD); 564 #endif 565 t4_register_fw_msg_handler(FW6_TYPE_CMD_RPL, t4_handle_fw_rpl); 566 t4_register_fw_msg_handler(FW6_TYPE_WRERR_RPL, t4_handle_wrerr_rpl); 567 } 568 569 void 570 t4_sge_modunload(void) 571 { 572 573 counter_u64_free(extfree_refs); 574 counter_u64_free(extfree_rels); 575 } 576 577 uint64_t 578 t4_sge_extfree_refs(void) 579 { 580 uint64_t refs, rels; 581 582 rels = counter_u64_fetch(extfree_rels); 583 refs = counter_u64_fetch(extfree_refs); 584 585 return (refs - rels); 586 } 587 588 static inline void 589 setup_pad_and_pack_boundaries(struct adapter *sc) 590 { 591 uint32_t v, m; 592 int pad, pack, pad_shift; 593 594 pad_shift = chip_id(sc) > CHELSIO_T5 ? X_T6_INGPADBOUNDARY_SHIFT : 595 X_INGPADBOUNDARY_SHIFT; 596 pad = fl_pad; 597 if (fl_pad < (1 << pad_shift) || 598 fl_pad > (1 << (pad_shift + M_INGPADBOUNDARY)) || 599 !powerof2(fl_pad)) { 600 /* 601 * If there is any chance that we might use buffer packing and 602 * the chip is a T4, then pick 64 as the pad/pack boundary. Set 603 * it to the minimum allowed in all other cases. 604 */ 605 pad = is_t4(sc) && buffer_packing ? 64 : 1 << pad_shift; 606 607 /* 608 * For fl_pad = 0 we'll still write a reasonable value to the 609 * register but all the freelists will opt out of padding. 610 * We'll complain here only if the user tried to set it to a 611 * value greater than 0 that was invalid. 612 */ 613 if (fl_pad > 0) { 614 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pad value" 615 " (%d), using %d instead.\n", fl_pad, pad); 616 } 617 } 618 m = V_INGPADBOUNDARY(M_INGPADBOUNDARY); 619 v = V_INGPADBOUNDARY(ilog2(pad) - pad_shift); 620 t4_set_reg_field(sc, A_SGE_CONTROL, m, v); 621 622 if (is_t4(sc)) { 623 if (fl_pack != -1 && fl_pack != pad) { 624 /* Complain but carry on. */ 625 device_printf(sc->dev, "hw.cxgbe.fl_pack (%d) ignored," 626 " using %d instead.\n", fl_pack, pad); 627 } 628 return; 629 } 630 631 pack = fl_pack; 632 if (fl_pack < 16 || fl_pack == 32 || fl_pack > 4096 || 633 !powerof2(fl_pack)) { 634 pack = max(sc->params.pci.mps, CACHE_LINE_SIZE); 635 MPASS(powerof2(pack)); 636 if (pack < 16) 637 pack = 16; 638 if (pack == 32) 639 pack = 64; 640 if (pack > 4096) 641 pack = 4096; 642 if (fl_pack != -1) { 643 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pack value" 644 " (%d), using %d instead.\n", fl_pack, pack); 645 } 646 } 647 m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY); 648 if (pack == 16) 649 v = V_INGPACKBOUNDARY(0); 650 else 651 v = V_INGPACKBOUNDARY(ilog2(pack) - 5); 652 653 MPASS(!is_t4(sc)); /* T4 doesn't have SGE_CONTROL2 */ 654 t4_set_reg_field(sc, A_SGE_CONTROL2, m, v); 655 } 656 657 /* 658 * adap->params.vpd.cclk must be set up before this is called. 659 */ 660 void 661 t4_tweak_chip_settings(struct adapter *sc) 662 { 663 int i; 664 uint32_t v, m; 665 int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200}; 666 int timer_max = M_TIMERVALUE0 * 1000 / sc->params.vpd.cclk; 667 int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */ 668 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 669 static int sge_flbuf_sizes[] = { 670 MCLBYTES, 671 #if MJUMPAGESIZE != MCLBYTES 672 MJUMPAGESIZE, 673 MJUMPAGESIZE - CL_METADATA_SIZE, 674 MJUMPAGESIZE - 2 * MSIZE - CL_METADATA_SIZE, 675 #endif 676 MJUM9BYTES, 677 MJUM16BYTES, 678 MCLBYTES - MSIZE - CL_METADATA_SIZE, 679 MJUM9BYTES - CL_METADATA_SIZE, 680 MJUM16BYTES - CL_METADATA_SIZE, 681 }; 682 683 KASSERT(sc->flags & MASTER_PF, 684 ("%s: trying to change chip settings when not master.", __func__)); 685 686 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE; 687 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE | 688 V_EGRSTATUSPAGESIZE(spg_len == 128); 689 t4_set_reg_field(sc, A_SGE_CONTROL, m, v); 690 691 setup_pad_and_pack_boundaries(sc); 692 693 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) | 694 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) | 695 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) | 696 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) | 697 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) | 698 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) | 699 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) | 700 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10); 701 t4_write_reg(sc, A_SGE_HOST_PAGE_SIZE, v); 702 703 KASSERT(nitems(sge_flbuf_sizes) <= SGE_FLBUF_SIZES, 704 ("%s: hw buffer size table too big", __func__)); 705 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0, 4096); 706 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE1, 65536); 707 for (i = 0; i < min(nitems(sge_flbuf_sizes), SGE_FLBUF_SIZES); i++) { 708 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE15 - (4 * i), 709 sge_flbuf_sizes[i]); 710 } 711 712 v = V_THRESHOLD_0(intr_pktcount[0]) | V_THRESHOLD_1(intr_pktcount[1]) | 713 V_THRESHOLD_2(intr_pktcount[2]) | V_THRESHOLD_3(intr_pktcount[3]); 714 t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD, v); 715 716 KASSERT(intr_timer[0] <= timer_max, 717 ("%s: not a single usable timer (%d, %d)", __func__, intr_timer[0], 718 timer_max)); 719 for (i = 1; i < nitems(intr_timer); i++) { 720 KASSERT(intr_timer[i] >= intr_timer[i - 1], 721 ("%s: timers not listed in increasing order (%d)", 722 __func__, i)); 723 724 while (intr_timer[i] > timer_max) { 725 if (i == nitems(intr_timer) - 1) { 726 intr_timer[i] = timer_max; 727 break; 728 } 729 intr_timer[i] += intr_timer[i - 1]; 730 intr_timer[i] /= 2; 731 } 732 } 733 734 v = V_TIMERVALUE0(us_to_core_ticks(sc, intr_timer[0])) | 735 V_TIMERVALUE1(us_to_core_ticks(sc, intr_timer[1])); 736 t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1, v); 737 v = V_TIMERVALUE2(us_to_core_ticks(sc, intr_timer[2])) | 738 V_TIMERVALUE3(us_to_core_ticks(sc, intr_timer[3])); 739 t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3, v); 740 v = V_TIMERVALUE4(us_to_core_ticks(sc, intr_timer[4])) | 741 V_TIMERVALUE5(us_to_core_ticks(sc, intr_timer[5])); 742 t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5, v); 743 744 if (chip_id(sc) >= CHELSIO_T6) { 745 m = V_TSCALE(M_TSCALE); 746 if (tscale == 1) 747 v = 0; 748 else 749 v = V_TSCALE(tscale - 2); 750 t4_set_reg_field(sc, A_SGE_ITP_CONTROL, m, v); 751 752 if (sc->debug_flags & DF_DISABLE_TCB_CACHE) { 753 m = V_RDTHRESHOLD(M_RDTHRESHOLD) | F_WRTHRTHRESHEN | 754 V_WRTHRTHRESH(M_WRTHRTHRESH); 755 t4_tp_pio_read(sc, &v, 1, A_TP_CMM_CONFIG, 1); 756 v &= ~m; 757 v |= V_RDTHRESHOLD(1) | F_WRTHRTHRESHEN | 758 V_WRTHRTHRESH(16); 759 t4_tp_pio_write(sc, &v, 1, A_TP_CMM_CONFIG, 1); 760 } 761 } 762 763 /* 4K, 16K, 64K, 256K DDP "page sizes" for TDDP */ 764 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 765 t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, v); 766 767 /* 768 * 4K, 8K, 16K, 64K DDP "page sizes" for iSCSI DDP. These have been 769 * chosen with MAXPHYS = 128K in mind. The largest DDP buffer that we 770 * may have to deal with is MAXPHYS + 1 page. 771 */ 772 v = V_HPZ0(0) | V_HPZ1(1) | V_HPZ2(2) | V_HPZ3(4); 773 t4_write_reg(sc, A_ULP_RX_ISCSI_PSZ, v); 774 775 /* We use multiple DDP page sizes both in plain-TOE and ISCSI modes. */ 776 m = v = F_TDDPTAGTCB | F_ISCSITAGTCB; 777 t4_set_reg_field(sc, A_ULP_RX_CTL, m, v); 778 779 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 780 F_RESETDDPOFFSET; 781 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 782 t4_set_reg_field(sc, A_TP_PARA_REG5, m, v); 783 } 784 785 /* 786 * SGE wants the buffer to be at least 64B and then a multiple of 16. If 787 * padding is in use, the buffer's start and end need to be aligned to the pad 788 * boundary as well. We'll just make sure that the size is a multiple of the 789 * boundary here, it is up to the buffer allocation code to make sure the start 790 * of the buffer is aligned as well. 791 */ 792 static inline int 793 hwsz_ok(struct adapter *sc, int hwsz) 794 { 795 int mask = fl_pad ? sc->params.sge.pad_boundary - 1 : 16 - 1; 796 797 return (hwsz >= 64 && (hwsz & mask) == 0); 798 } 799 800 /* 801 * XXX: driver really should be able to deal with unexpected settings. 802 */ 803 int 804 t4_read_chip_settings(struct adapter *sc) 805 { 806 struct sge *s = &sc->sge; 807 struct sge_params *sp = &sc->params.sge; 808 int i, j, n, rc = 0; 809 uint32_t m, v, r; 810 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 811 static int sw_buf_sizes[] = { /* Sorted by size */ 812 MCLBYTES, 813 #if MJUMPAGESIZE != MCLBYTES 814 MJUMPAGESIZE, 815 #endif 816 MJUM9BYTES, 817 MJUM16BYTES 818 }; 819 struct sw_zone_info *swz, *safe_swz; 820 struct hw_buf_info *hwb; 821 822 m = F_RXPKTCPLMODE; 823 v = F_RXPKTCPLMODE; 824 r = sc->params.sge.sge_control; 825 if ((r & m) != v) { 826 device_printf(sc->dev, "invalid SGE_CONTROL(0x%x)\n", r); 827 rc = EINVAL; 828 } 829 830 /* 831 * If this changes then every single use of PAGE_SHIFT in the driver 832 * needs to be carefully reviewed for PAGE_SHIFT vs sp->page_shift. 833 */ 834 if (sp->page_shift != PAGE_SHIFT) { 835 device_printf(sc->dev, "invalid SGE_HOST_PAGE_SIZE(0x%x)\n", r); 836 rc = EINVAL; 837 } 838 839 /* Filter out unusable hw buffer sizes entirely (mark with -2). */ 840 hwb = &s->hw_buf_info[0]; 841 for (i = 0; i < nitems(s->hw_buf_info); i++, hwb++) { 842 r = sc->params.sge.sge_fl_buffer_size[i]; 843 hwb->size = r; 844 hwb->zidx = hwsz_ok(sc, r) ? -1 : -2; 845 hwb->next = -1; 846 } 847 848 /* 849 * Create a sorted list in decreasing order of hw buffer sizes (and so 850 * increasing order of spare area) for each software zone. 851 * 852 * If padding is enabled then the start and end of the buffer must align 853 * to the pad boundary; if packing is enabled then they must align with 854 * the pack boundary as well. Allocations from the cluster zones are 855 * aligned to min(size, 4K), so the buffer starts at that alignment and 856 * ends at hwb->size alignment. If mbuf inlining is allowed the 857 * starting alignment will be reduced to MSIZE and the driver will 858 * exercise appropriate caution when deciding on the best buffer layout 859 * to use. 860 */ 861 n = 0; /* no usable buffer size to begin with */ 862 swz = &s->sw_zone_info[0]; 863 safe_swz = NULL; 864 for (i = 0; i < SW_ZONE_SIZES; i++, swz++) { 865 int8_t head = -1, tail = -1; 866 867 swz->size = sw_buf_sizes[i]; 868 swz->zone = m_getzone(swz->size); 869 swz->type = m_gettype(swz->size); 870 871 if (swz->size < PAGE_SIZE) { 872 MPASS(powerof2(swz->size)); 873 if (fl_pad && (swz->size % sp->pad_boundary != 0)) 874 continue; 875 } 876 877 if (swz->size == safest_rx_cluster) 878 safe_swz = swz; 879 880 hwb = &s->hw_buf_info[0]; 881 for (j = 0; j < SGE_FLBUF_SIZES; j++, hwb++) { 882 if (hwb->zidx != -1 || hwb->size > swz->size) 883 continue; 884 #ifdef INVARIANTS 885 if (fl_pad) 886 MPASS(hwb->size % sp->pad_boundary == 0); 887 #endif 888 hwb->zidx = i; 889 if (head == -1) 890 head = tail = j; 891 else if (hwb->size < s->hw_buf_info[tail].size) { 892 s->hw_buf_info[tail].next = j; 893 tail = j; 894 } else { 895 int8_t *cur; 896 struct hw_buf_info *t; 897 898 for (cur = &head; *cur != -1; cur = &t->next) { 899 t = &s->hw_buf_info[*cur]; 900 if (hwb->size == t->size) { 901 hwb->zidx = -2; 902 break; 903 } 904 if (hwb->size > t->size) { 905 hwb->next = *cur; 906 *cur = j; 907 break; 908 } 909 } 910 } 911 } 912 swz->head_hwidx = head; 913 swz->tail_hwidx = tail; 914 915 if (tail != -1) { 916 n++; 917 if (swz->size - s->hw_buf_info[tail].size >= 918 CL_METADATA_SIZE) 919 sc->flags |= BUF_PACKING_OK; 920 } 921 } 922 if (n == 0) { 923 device_printf(sc->dev, "no usable SGE FL buffer size.\n"); 924 rc = EINVAL; 925 } 926 927 s->safe_hwidx1 = -1; 928 s->safe_hwidx2 = -1; 929 if (safe_swz != NULL) { 930 s->safe_hwidx1 = safe_swz->head_hwidx; 931 for (i = safe_swz->head_hwidx; i != -1; i = hwb->next) { 932 int spare; 933 934 hwb = &s->hw_buf_info[i]; 935 #ifdef INVARIANTS 936 if (fl_pad) 937 MPASS(hwb->size % sp->pad_boundary == 0); 938 #endif 939 spare = safe_swz->size - hwb->size; 940 if (spare >= CL_METADATA_SIZE) { 941 s->safe_hwidx2 = i; 942 break; 943 } 944 } 945 } 946 947 if (sc->flags & IS_VF) 948 return (0); 949 950 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 951 r = t4_read_reg(sc, A_ULP_RX_TDDP_PSZ); 952 if (r != v) { 953 device_printf(sc->dev, "invalid ULP_RX_TDDP_PSZ(0x%x)\n", r); 954 rc = EINVAL; 955 } 956 957 m = v = F_TDDPTAGTCB; 958 r = t4_read_reg(sc, A_ULP_RX_CTL); 959 if ((r & m) != v) { 960 device_printf(sc->dev, "invalid ULP_RX_CTL(0x%x)\n", r); 961 rc = EINVAL; 962 } 963 964 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 965 F_RESETDDPOFFSET; 966 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 967 r = t4_read_reg(sc, A_TP_PARA_REG5); 968 if ((r & m) != v) { 969 device_printf(sc->dev, "invalid TP_PARA_REG5(0x%x)\n", r); 970 rc = EINVAL; 971 } 972 973 t4_init_tp_params(sc, 1); 974 975 t4_read_mtu_tbl(sc, sc->params.mtus, NULL); 976 t4_load_mtus(sc, sc->params.mtus, sc->params.a_wnd, sc->params.b_wnd); 977 978 return (rc); 979 } 980 981 int 982 t4_create_dma_tag(struct adapter *sc) 983 { 984 int rc; 985 986 rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0, 987 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE, 988 BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL, 989 NULL, &sc->dmat); 990 if (rc != 0) { 991 device_printf(sc->dev, 992 "failed to create main DMA tag: %d\n", rc); 993 } 994 995 return (rc); 996 } 997 998 void 999 t4_sge_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx, 1000 struct sysctl_oid_list *children) 1001 { 1002 struct sge_params *sp = &sc->params.sge; 1003 1004 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "buffer_sizes", 1005 CTLTYPE_STRING | CTLFLAG_RD, &sc->sge, 0, sysctl_bufsizes, "A", 1006 "freelist buffer sizes"); 1007 1008 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pktshift", CTLFLAG_RD, 1009 NULL, sp->fl_pktshift, "payload DMA offset in rx buffer (bytes)"); 1010 1011 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pad", CTLFLAG_RD, 1012 NULL, sp->pad_boundary, "payload pad boundary (bytes)"); 1013 1014 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "spg_len", CTLFLAG_RD, 1015 NULL, sp->spg_len, "status page size (bytes)"); 1016 1017 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_drop", CTLFLAG_RD, 1018 NULL, cong_drop, "congestion drop setting"); 1019 1020 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pack", CTLFLAG_RD, 1021 NULL, sp->pack_boundary, "payload pack boundary (bytes)"); 1022 } 1023 1024 int 1025 t4_destroy_dma_tag(struct adapter *sc) 1026 { 1027 if (sc->dmat) 1028 bus_dma_tag_destroy(sc->dmat); 1029 1030 return (0); 1031 } 1032 1033 /* 1034 * Allocate and initialize the firmware event queue, control queues, and special 1035 * purpose rx queues owned by the adapter. 1036 * 1037 * Returns errno on failure. Resources allocated up to that point may still be 1038 * allocated. Caller is responsible for cleanup in case this function fails. 1039 */ 1040 int 1041 t4_setup_adapter_queues(struct adapter *sc) 1042 { 1043 struct sysctl_oid *oid; 1044 struct sysctl_oid_list *children; 1045 int rc, i; 1046 1047 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 1048 1049 sysctl_ctx_init(&sc->ctx); 1050 sc->flags |= ADAP_SYSCTL_CTX; 1051 1052 /* 1053 * Firmware event queue 1054 */ 1055 rc = alloc_fwq(sc); 1056 if (rc != 0) 1057 return (rc); 1058 1059 /* 1060 * That's all for the VF driver. 1061 */ 1062 if (sc->flags & IS_VF) 1063 return (rc); 1064 1065 oid = device_get_sysctl_tree(sc->dev); 1066 children = SYSCTL_CHILDREN(oid); 1067 1068 /* 1069 * XXX: General purpose rx queues, one per port. 1070 */ 1071 1072 /* 1073 * Control queues, one per port. 1074 */ 1075 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "ctrlq", 1076 CTLFLAG_RD, NULL, "control queues"); 1077 for_each_port(sc, i) { 1078 struct sge_wrq *ctrlq = &sc->sge.ctrlq[i]; 1079 1080 rc = alloc_ctrlq(sc, ctrlq, i, oid); 1081 if (rc != 0) 1082 return (rc); 1083 } 1084 1085 return (rc); 1086 } 1087 1088 /* 1089 * Idempotent 1090 */ 1091 int 1092 t4_teardown_adapter_queues(struct adapter *sc) 1093 { 1094 int i; 1095 1096 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 1097 1098 /* Do this before freeing the queue */ 1099 if (sc->flags & ADAP_SYSCTL_CTX) { 1100 sysctl_ctx_free(&sc->ctx); 1101 sc->flags &= ~ADAP_SYSCTL_CTX; 1102 } 1103 1104 if (!(sc->flags & IS_VF)) { 1105 for_each_port(sc, i) 1106 free_wrq(sc, &sc->sge.ctrlq[i]); 1107 } 1108 free_fwq(sc); 1109 1110 return (0); 1111 } 1112 1113 /* Maximum payload that can be delivered with a single iq descriptor */ 1114 static inline int 1115 mtu_to_max_payload(struct adapter *sc, int mtu) 1116 { 1117 1118 /* large enough even when hw VLAN extraction is disabled */ 1119 return (sc->params.sge.fl_pktshift + ETHER_HDR_LEN + 1120 ETHER_VLAN_ENCAP_LEN + mtu); 1121 } 1122 1123 int 1124 t4_setup_vi_queues(struct vi_info *vi) 1125 { 1126 int rc = 0, i, intr_idx, iqidx; 1127 struct sge_rxq *rxq; 1128 struct sge_txq *txq; 1129 #ifdef TCP_OFFLOAD 1130 struct sge_ofld_rxq *ofld_rxq; 1131 #endif 1132 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1133 struct sge_wrq *ofld_txq; 1134 #endif 1135 #ifdef DEV_NETMAP 1136 int saved_idx; 1137 struct sge_nm_rxq *nm_rxq; 1138 struct sge_nm_txq *nm_txq; 1139 #endif 1140 char name[16]; 1141 struct port_info *pi = vi->pi; 1142 struct adapter *sc = pi->adapter; 1143 struct ifnet *ifp = vi->ifp; 1144 struct sysctl_oid *oid = device_get_sysctl_tree(vi->dev); 1145 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 1146 int maxp, mtu = ifp->if_mtu; 1147 1148 /* Interrupt vector to start from (when using multiple vectors) */ 1149 intr_idx = vi->first_intr; 1150 1151 #ifdef DEV_NETMAP 1152 saved_idx = intr_idx; 1153 if (ifp->if_capabilities & IFCAP_NETMAP) { 1154 1155 /* netmap is supported with direct interrupts only. */ 1156 MPASS(!forwarding_intr_to_fwq(sc)); 1157 1158 /* 1159 * We don't have buffers to back the netmap rx queues 1160 * right now so we create the queues in a way that 1161 * doesn't set off any congestion signal in the chip. 1162 */ 1163 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "nm_rxq", 1164 CTLFLAG_RD, NULL, "rx queues"); 1165 for_each_nm_rxq(vi, i, nm_rxq) { 1166 rc = alloc_nm_rxq(vi, nm_rxq, intr_idx, i, oid); 1167 if (rc != 0) 1168 goto done; 1169 intr_idx++; 1170 } 1171 1172 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "nm_txq", 1173 CTLFLAG_RD, NULL, "tx queues"); 1174 for_each_nm_txq(vi, i, nm_txq) { 1175 iqidx = vi->first_nm_rxq + (i % vi->nnmrxq); 1176 rc = alloc_nm_txq(vi, nm_txq, iqidx, i, oid); 1177 if (rc != 0) 1178 goto done; 1179 } 1180 } 1181 1182 /* Normal rx queues and netmap rx queues share the same interrupts. */ 1183 intr_idx = saved_idx; 1184 #endif 1185 1186 /* 1187 * Allocate rx queues first because a default iqid is required when 1188 * creating a tx queue. 1189 */ 1190 maxp = mtu_to_max_payload(sc, mtu); 1191 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "rxq", 1192 CTLFLAG_RD, NULL, "rx queues"); 1193 for_each_rxq(vi, i, rxq) { 1194 1195 init_iq(&rxq->iq, sc, vi->tmr_idx, vi->pktc_idx, vi->qsize_rxq); 1196 1197 snprintf(name, sizeof(name), "%s rxq%d-fl", 1198 device_get_nameunit(vi->dev), i); 1199 init_fl(sc, &rxq->fl, vi->qsize_rxq / 8, maxp, name); 1200 1201 rc = alloc_rxq(vi, rxq, 1202 forwarding_intr_to_fwq(sc) ? -1 : intr_idx, i, oid); 1203 if (rc != 0) 1204 goto done; 1205 intr_idx++; 1206 } 1207 #ifdef DEV_NETMAP 1208 if (ifp->if_capabilities & IFCAP_NETMAP) 1209 intr_idx = saved_idx + max(vi->nrxq, vi->nnmrxq); 1210 #endif 1211 #ifdef TCP_OFFLOAD 1212 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_rxq", 1213 CTLFLAG_RD, NULL, "rx queues for offloaded TCP connections"); 1214 for_each_ofld_rxq(vi, i, ofld_rxq) { 1215 1216 init_iq(&ofld_rxq->iq, sc, vi->ofld_tmr_idx, vi->ofld_pktc_idx, 1217 vi->qsize_rxq); 1218 1219 snprintf(name, sizeof(name), "%s ofld_rxq%d-fl", 1220 device_get_nameunit(vi->dev), i); 1221 init_fl(sc, &ofld_rxq->fl, vi->qsize_rxq / 8, maxp, name); 1222 1223 rc = alloc_ofld_rxq(vi, ofld_rxq, 1224 forwarding_intr_to_fwq(sc) ? -1 : intr_idx, i, oid); 1225 if (rc != 0) 1226 goto done; 1227 intr_idx++; 1228 } 1229 #endif 1230 1231 /* 1232 * Now the tx queues. 1233 */ 1234 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "txq", CTLFLAG_RD, 1235 NULL, "tx queues"); 1236 for_each_txq(vi, i, txq) { 1237 iqidx = vi->first_rxq + (i % vi->nrxq); 1238 snprintf(name, sizeof(name), "%s txq%d", 1239 device_get_nameunit(vi->dev), i); 1240 init_eq(sc, &txq->eq, EQ_ETH, vi->qsize_txq, pi->tx_chan, 1241 sc->sge.rxq[iqidx].iq.cntxt_id, name); 1242 1243 rc = alloc_txq(vi, txq, i, oid); 1244 if (rc != 0) 1245 goto done; 1246 } 1247 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1248 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_txq", 1249 CTLFLAG_RD, NULL, "tx queues for TOE/ETHOFLD"); 1250 for_each_ofld_txq(vi, i, ofld_txq) { 1251 struct sysctl_oid *oid2; 1252 1253 snprintf(name, sizeof(name), "%s ofld_txq%d", 1254 device_get_nameunit(vi->dev), i); 1255 if (vi->nofldrxq > 0) { 1256 iqidx = vi->first_ofld_rxq + (i % vi->nofldrxq); 1257 init_eq(sc, &ofld_txq->eq, EQ_OFLD, vi->qsize_txq, 1258 pi->tx_chan, sc->sge.ofld_rxq[iqidx].iq.cntxt_id, 1259 name); 1260 } else { 1261 iqidx = vi->first_rxq + (i % vi->nrxq); 1262 init_eq(sc, &ofld_txq->eq, EQ_OFLD, vi->qsize_txq, 1263 pi->tx_chan, sc->sge.rxq[iqidx].iq.cntxt_id, name); 1264 } 1265 1266 snprintf(name, sizeof(name), "%d", i); 1267 oid2 = SYSCTL_ADD_NODE(&vi->ctx, SYSCTL_CHILDREN(oid), OID_AUTO, 1268 name, CTLFLAG_RD, NULL, "offload tx queue"); 1269 1270 rc = alloc_wrq(sc, vi, ofld_txq, oid2); 1271 if (rc != 0) 1272 goto done; 1273 } 1274 #endif 1275 done: 1276 if (rc) 1277 t4_teardown_vi_queues(vi); 1278 1279 return (rc); 1280 } 1281 1282 /* 1283 * Idempotent 1284 */ 1285 int 1286 t4_teardown_vi_queues(struct vi_info *vi) 1287 { 1288 int i; 1289 struct sge_rxq *rxq; 1290 struct sge_txq *txq; 1291 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1292 struct port_info *pi = vi->pi; 1293 struct adapter *sc = pi->adapter; 1294 struct sge_wrq *ofld_txq; 1295 #endif 1296 #ifdef TCP_OFFLOAD 1297 struct sge_ofld_rxq *ofld_rxq; 1298 #endif 1299 #ifdef DEV_NETMAP 1300 struct sge_nm_rxq *nm_rxq; 1301 struct sge_nm_txq *nm_txq; 1302 #endif 1303 1304 /* Do this before freeing the queues */ 1305 if (vi->flags & VI_SYSCTL_CTX) { 1306 sysctl_ctx_free(&vi->ctx); 1307 vi->flags &= ~VI_SYSCTL_CTX; 1308 } 1309 1310 #ifdef DEV_NETMAP 1311 if (vi->ifp->if_capabilities & IFCAP_NETMAP) { 1312 for_each_nm_txq(vi, i, nm_txq) { 1313 free_nm_txq(vi, nm_txq); 1314 } 1315 1316 for_each_nm_rxq(vi, i, nm_rxq) { 1317 free_nm_rxq(vi, nm_rxq); 1318 } 1319 } 1320 #endif 1321 1322 /* 1323 * Take down all the tx queues first, as they reference the rx queues 1324 * (for egress updates, etc.). 1325 */ 1326 1327 for_each_txq(vi, i, txq) { 1328 free_txq(vi, txq); 1329 } 1330 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1331 for_each_ofld_txq(vi, i, ofld_txq) { 1332 free_wrq(sc, ofld_txq); 1333 } 1334 #endif 1335 1336 /* 1337 * Then take down the rx queues. 1338 */ 1339 1340 for_each_rxq(vi, i, rxq) { 1341 free_rxq(vi, rxq); 1342 } 1343 #ifdef TCP_OFFLOAD 1344 for_each_ofld_rxq(vi, i, ofld_rxq) { 1345 free_ofld_rxq(vi, ofld_rxq); 1346 } 1347 #endif 1348 1349 return (0); 1350 } 1351 1352 /* 1353 * Interrupt handler when the driver is using only 1 interrupt. This is a very 1354 * unusual scenario. 1355 * 1356 * a) Deals with errors, if any. 1357 * b) Services firmware event queue, which is taking interrupts for all other 1358 * queues. 1359 */ 1360 void 1361 t4_intr_all(void *arg) 1362 { 1363 struct adapter *sc = arg; 1364 struct sge_iq *fwq = &sc->sge.fwq; 1365 1366 MPASS(sc->intr_count == 1); 1367 1368 if (sc->intr_type == INTR_INTX) 1369 t4_write_reg(sc, MYPF_REG(A_PCIE_PF_CLI), 0); 1370 1371 t4_intr_err(arg); 1372 t4_intr_evt(fwq); 1373 } 1374 1375 /* 1376 * Interrupt handler for errors (installed directly when multiple interrupts are 1377 * being used, or called by t4_intr_all). 1378 */ 1379 void 1380 t4_intr_err(void *arg) 1381 { 1382 struct adapter *sc = arg; 1383 uint32_t v; 1384 const bool verbose = (sc->debug_flags & DF_VERBOSE_SLOWINTR) != 0; 1385 1386 if (sc->flags & ADAP_ERR) 1387 return; 1388 1389 v = t4_read_reg(sc, MYPF_REG(A_PL_PF_INT_CAUSE)); 1390 if (v & F_PFSW) { 1391 sc->swintr++; 1392 t4_write_reg(sc, MYPF_REG(A_PL_PF_INT_CAUSE), v); 1393 } 1394 1395 t4_slow_intr_handler(sc, verbose); 1396 } 1397 1398 /* 1399 * Interrupt handler for iq-only queues. The firmware event queue is the only 1400 * such queue right now. 1401 */ 1402 void 1403 t4_intr_evt(void *arg) 1404 { 1405 struct sge_iq *iq = arg; 1406 1407 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 1408 service_iq(iq, 0); 1409 (void) atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 1410 } 1411 } 1412 1413 /* 1414 * Interrupt handler for iq+fl queues. 1415 */ 1416 void 1417 t4_intr(void *arg) 1418 { 1419 struct sge_iq *iq = arg; 1420 1421 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 1422 service_iq_fl(iq, 0); 1423 (void) atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 1424 } 1425 } 1426 1427 #ifdef DEV_NETMAP 1428 /* 1429 * Interrupt handler for netmap rx queues. 1430 */ 1431 void 1432 t4_nm_intr(void *arg) 1433 { 1434 struct sge_nm_rxq *nm_rxq = arg; 1435 1436 if (atomic_cmpset_int(&nm_rxq->nm_state, NM_ON, NM_BUSY)) { 1437 service_nm_rxq(nm_rxq); 1438 (void) atomic_cmpset_int(&nm_rxq->nm_state, NM_BUSY, NM_ON); 1439 } 1440 } 1441 1442 /* 1443 * Interrupt handler for vectors shared between NIC and netmap rx queues. 1444 */ 1445 void 1446 t4_vi_intr(void *arg) 1447 { 1448 struct irq *irq = arg; 1449 1450 MPASS(irq->nm_rxq != NULL); 1451 t4_nm_intr(irq->nm_rxq); 1452 1453 MPASS(irq->rxq != NULL); 1454 t4_intr(irq->rxq); 1455 } 1456 #endif 1457 1458 /* 1459 * Deals with interrupts on an iq-only (no freelist) queue. 1460 */ 1461 static int 1462 service_iq(struct sge_iq *iq, int budget) 1463 { 1464 struct sge_iq *q; 1465 struct adapter *sc = iq->adapter; 1466 struct iq_desc *d = &iq->desc[iq->cidx]; 1467 int ndescs = 0, limit; 1468 int rsp_type; 1469 uint32_t lq; 1470 STAILQ_HEAD(, sge_iq) iql = STAILQ_HEAD_INITIALIZER(iql); 1471 1472 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq)); 1473 KASSERT((iq->flags & IQ_HAS_FL) == 0, 1474 ("%s: called for iq %p with fl (iq->flags 0x%x)", __func__, iq, 1475 iq->flags)); 1476 MPASS((iq->flags & IQ_ADJ_CREDIT) == 0); 1477 MPASS((iq->flags & IQ_LRO_ENABLED) == 0); 1478 1479 limit = budget ? budget : iq->qsize / 16; 1480 1481 /* 1482 * We always come back and check the descriptor ring for new indirect 1483 * interrupts and other responses after running a single handler. 1484 */ 1485 for (;;) { 1486 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) { 1487 1488 rmb(); 1489 1490 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen); 1491 lq = be32toh(d->rsp.pldbuflen_qid); 1492 1493 switch (rsp_type) { 1494 case X_RSPD_TYPE_FLBUF: 1495 panic("%s: data for an iq (%p) with no freelist", 1496 __func__, iq); 1497 1498 /* NOTREACHED */ 1499 1500 case X_RSPD_TYPE_CPL: 1501 KASSERT(d->rss.opcode < NUM_CPL_CMDS, 1502 ("%s: bad opcode %02x.", __func__, 1503 d->rss.opcode)); 1504 t4_cpl_handler[d->rss.opcode](iq, &d->rss, NULL); 1505 break; 1506 1507 case X_RSPD_TYPE_INTR: 1508 /* 1509 * There are 1K interrupt-capable queues (qids 0 1510 * through 1023). A response type indicating a 1511 * forwarded interrupt with a qid >= 1K is an 1512 * iWARP async notification. 1513 */ 1514 if (__predict_true(lq >= 1024)) { 1515 t4_an_handler(iq, &d->rsp); 1516 break; 1517 } 1518 1519 q = sc->sge.iqmap[lq - sc->sge.iq_start - 1520 sc->sge.iq_base]; 1521 if (atomic_cmpset_int(&q->state, IQS_IDLE, 1522 IQS_BUSY)) { 1523 if (service_iq_fl(q, q->qsize / 16) == 0) { 1524 (void) atomic_cmpset_int(&q->state, 1525 IQS_BUSY, IQS_IDLE); 1526 } else { 1527 STAILQ_INSERT_TAIL(&iql, q, 1528 link); 1529 } 1530 } 1531 break; 1532 1533 default: 1534 KASSERT(0, 1535 ("%s: illegal response type %d on iq %p", 1536 __func__, rsp_type, iq)); 1537 log(LOG_ERR, 1538 "%s: illegal response type %d on iq %p", 1539 device_get_nameunit(sc->dev), rsp_type, iq); 1540 break; 1541 } 1542 1543 d++; 1544 if (__predict_false(++iq->cidx == iq->sidx)) { 1545 iq->cidx = 0; 1546 iq->gen ^= F_RSPD_GEN; 1547 d = &iq->desc[0]; 1548 } 1549 if (__predict_false(++ndescs == limit)) { 1550 t4_write_reg(sc, sc->sge_gts_reg, 1551 V_CIDXINC(ndescs) | 1552 V_INGRESSQID(iq->cntxt_id) | 1553 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); 1554 ndescs = 0; 1555 1556 if (budget) { 1557 return (EINPROGRESS); 1558 } 1559 } 1560 } 1561 1562 if (STAILQ_EMPTY(&iql)) 1563 break; 1564 1565 /* 1566 * Process the head only, and send it to the back of the list if 1567 * it's still not done. 1568 */ 1569 q = STAILQ_FIRST(&iql); 1570 STAILQ_REMOVE_HEAD(&iql, link); 1571 if (service_iq_fl(q, q->qsize / 8) == 0) 1572 (void) atomic_cmpset_int(&q->state, IQS_BUSY, IQS_IDLE); 1573 else 1574 STAILQ_INSERT_TAIL(&iql, q, link); 1575 } 1576 1577 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) | 1578 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params)); 1579 1580 return (0); 1581 } 1582 1583 static inline int 1584 sort_before_lro(struct lro_ctrl *lro) 1585 { 1586 1587 return (lro->lro_mbuf_max != 0); 1588 } 1589 1590 static inline uint64_t 1591 last_flit_to_ns(struct adapter *sc, uint64_t lf) 1592 { 1593 uint64_t n = be64toh(lf) & 0xfffffffffffffff; /* 60b, not 64b. */ 1594 1595 if (n > UINT64_MAX / 1000000) 1596 return (n / sc->params.vpd.cclk * 1000000); 1597 else 1598 return (n * 1000000 / sc->params.vpd.cclk); 1599 } 1600 1601 /* 1602 * Deals with interrupts on an iq+fl queue. 1603 */ 1604 static int 1605 service_iq_fl(struct sge_iq *iq, int budget) 1606 { 1607 struct sge_rxq *rxq = iq_to_rxq(iq); 1608 struct sge_fl *fl; 1609 struct adapter *sc = iq->adapter; 1610 struct iq_desc *d = &iq->desc[iq->cidx]; 1611 int ndescs = 0, limit; 1612 int rsp_type, refill, starved; 1613 uint32_t lq; 1614 uint16_t fl_hw_cidx; 1615 struct mbuf *m0; 1616 #if defined(INET) || defined(INET6) 1617 const struct timeval lro_timeout = {0, sc->lro_timeout}; 1618 struct lro_ctrl *lro = &rxq->lro; 1619 #endif 1620 1621 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq)); 1622 MPASS(iq->flags & IQ_HAS_FL); 1623 1624 limit = budget ? budget : iq->qsize / 16; 1625 fl = &rxq->fl; 1626 fl_hw_cidx = fl->hw_cidx; /* stable snapshot */ 1627 1628 #if defined(INET) || defined(INET6) 1629 if (iq->flags & IQ_ADJ_CREDIT) { 1630 MPASS(sort_before_lro(lro)); 1631 iq->flags &= ~IQ_ADJ_CREDIT; 1632 if ((d->rsp.u.type_gen & F_RSPD_GEN) != iq->gen) { 1633 tcp_lro_flush_all(lro); 1634 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(1) | 1635 V_INGRESSQID((u32)iq->cntxt_id) | 1636 V_SEINTARM(iq->intr_params)); 1637 return (0); 1638 } 1639 ndescs = 1; 1640 } 1641 #else 1642 MPASS((iq->flags & IQ_ADJ_CREDIT) == 0); 1643 #endif 1644 1645 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) { 1646 1647 rmb(); 1648 1649 refill = 0; 1650 m0 = NULL; 1651 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen); 1652 lq = be32toh(d->rsp.pldbuflen_qid); 1653 1654 switch (rsp_type) { 1655 case X_RSPD_TYPE_FLBUF: 1656 1657 m0 = get_fl_payload(sc, fl, lq); 1658 if (__predict_false(m0 == NULL)) 1659 goto out; 1660 refill = IDXDIFF(fl->hw_cidx, fl_hw_cidx, fl->sidx) > 2; 1661 1662 if (iq->flags & IQ_RX_TIMESTAMP) { 1663 /* 1664 * Fill up rcv_tstmp but do not set M_TSTMP. 1665 * rcv_tstmp is not in the format that the 1666 * kernel expects and we don't want to mislead 1667 * it. For now this is only for custom code 1668 * that knows how to interpret cxgbe's stamp. 1669 */ 1670 m0->m_pkthdr.rcv_tstmp = 1671 last_flit_to_ns(sc, d->rsp.u.last_flit); 1672 #ifdef notyet 1673 m0->m_flags |= M_TSTMP; 1674 #endif 1675 } 1676 1677 /* fall through */ 1678 1679 case X_RSPD_TYPE_CPL: 1680 KASSERT(d->rss.opcode < NUM_CPL_CMDS, 1681 ("%s: bad opcode %02x.", __func__, d->rss.opcode)); 1682 t4_cpl_handler[d->rss.opcode](iq, &d->rss, m0); 1683 break; 1684 1685 case X_RSPD_TYPE_INTR: 1686 1687 /* 1688 * There are 1K interrupt-capable queues (qids 0 1689 * through 1023). A response type indicating a 1690 * forwarded interrupt with a qid >= 1K is an 1691 * iWARP async notification. That is the only 1692 * acceptable indirect interrupt on this queue. 1693 */ 1694 if (__predict_false(lq < 1024)) { 1695 panic("%s: indirect interrupt on iq_fl %p " 1696 "with qid %u", __func__, iq, lq); 1697 } 1698 1699 t4_an_handler(iq, &d->rsp); 1700 break; 1701 1702 default: 1703 KASSERT(0, ("%s: illegal response type %d on iq %p", 1704 __func__, rsp_type, iq)); 1705 log(LOG_ERR, "%s: illegal response type %d on iq %p", 1706 device_get_nameunit(sc->dev), rsp_type, iq); 1707 break; 1708 } 1709 1710 d++; 1711 if (__predict_false(++iq->cidx == iq->sidx)) { 1712 iq->cidx = 0; 1713 iq->gen ^= F_RSPD_GEN; 1714 d = &iq->desc[0]; 1715 } 1716 if (__predict_false(++ndescs == limit)) { 1717 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) | 1718 V_INGRESSQID(iq->cntxt_id) | 1719 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); 1720 ndescs = 0; 1721 1722 #if defined(INET) || defined(INET6) 1723 if (iq->flags & IQ_LRO_ENABLED && 1724 !sort_before_lro(lro) && 1725 sc->lro_timeout != 0) { 1726 tcp_lro_flush_inactive(lro, &lro_timeout); 1727 } 1728 #endif 1729 if (budget) { 1730 FL_LOCK(fl); 1731 refill_fl(sc, fl, 32); 1732 FL_UNLOCK(fl); 1733 1734 return (EINPROGRESS); 1735 } 1736 } 1737 if (refill) { 1738 FL_LOCK(fl); 1739 refill_fl(sc, fl, 32); 1740 FL_UNLOCK(fl); 1741 fl_hw_cidx = fl->hw_cidx; 1742 } 1743 } 1744 out: 1745 #if defined(INET) || defined(INET6) 1746 if (iq->flags & IQ_LRO_ENABLED) { 1747 if (ndescs > 0 && lro->lro_mbuf_count > 8) { 1748 MPASS(sort_before_lro(lro)); 1749 /* hold back one credit and don't flush LRO state */ 1750 iq->flags |= IQ_ADJ_CREDIT; 1751 ndescs--; 1752 } else { 1753 tcp_lro_flush_all(lro); 1754 } 1755 } 1756 #endif 1757 1758 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) | 1759 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params)); 1760 1761 FL_LOCK(fl); 1762 starved = refill_fl(sc, fl, 64); 1763 FL_UNLOCK(fl); 1764 if (__predict_false(starved != 0)) 1765 add_fl_to_sfl(sc, fl); 1766 1767 return (0); 1768 } 1769 1770 static inline int 1771 cl_has_metadata(struct sge_fl *fl, struct cluster_layout *cll) 1772 { 1773 int rc = fl->flags & FL_BUF_PACKING || cll->region1 > 0; 1774 1775 if (rc) 1776 MPASS(cll->region3 >= CL_METADATA_SIZE); 1777 1778 return (rc); 1779 } 1780 1781 static inline struct cluster_metadata * 1782 cl_metadata(struct adapter *sc, struct sge_fl *fl, struct cluster_layout *cll, 1783 caddr_t cl) 1784 { 1785 1786 if (cl_has_metadata(fl, cll)) { 1787 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx]; 1788 1789 return ((struct cluster_metadata *)(cl + swz->size) - 1); 1790 } 1791 return (NULL); 1792 } 1793 1794 static void 1795 rxb_free(struct mbuf *m) 1796 { 1797 uma_zone_t zone = m->m_ext.ext_arg1; 1798 void *cl = m->m_ext.ext_arg2; 1799 1800 uma_zfree(zone, cl); 1801 counter_u64_add(extfree_rels, 1); 1802 } 1803 1804 /* 1805 * The mbuf returned by this function could be allocated from zone_mbuf or 1806 * constructed in spare room in the cluster. 1807 * 1808 * The mbuf carries the payload in one of these ways 1809 * a) frame inside the mbuf (mbuf from zone_mbuf) 1810 * b) m_cljset (for clusters without metadata) zone_mbuf 1811 * c) m_extaddref (cluster with metadata) inline mbuf 1812 * d) m_extaddref (cluster with metadata) zone_mbuf 1813 */ 1814 static struct mbuf * 1815 get_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset, 1816 int remaining) 1817 { 1818 struct mbuf *m; 1819 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 1820 struct cluster_layout *cll = &sd->cll; 1821 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx]; 1822 struct hw_buf_info *hwb = &sc->sge.hw_buf_info[cll->hwidx]; 1823 struct cluster_metadata *clm = cl_metadata(sc, fl, cll, sd->cl); 1824 int len, blen; 1825 caddr_t payload; 1826 1827 blen = hwb->size - fl->rx_offset; /* max possible in this buf */ 1828 len = min(remaining, blen); 1829 payload = sd->cl + cll->region1 + fl->rx_offset; 1830 if (fl->flags & FL_BUF_PACKING) { 1831 const u_int l = fr_offset + len; 1832 const u_int pad = roundup2(l, fl->buf_boundary) - l; 1833 1834 if (fl->rx_offset + len + pad < hwb->size) 1835 blen = len + pad; 1836 MPASS(fl->rx_offset + blen <= hwb->size); 1837 } else { 1838 MPASS(fl->rx_offset == 0); /* not packing */ 1839 } 1840 1841 1842 if (sc->sc_do_rxcopy && len < RX_COPY_THRESHOLD) { 1843 1844 /* 1845 * Copy payload into a freshly allocated mbuf. 1846 */ 1847 1848 m = fr_offset == 0 ? 1849 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA); 1850 if (m == NULL) 1851 return (NULL); 1852 fl->mbuf_allocated++; 1853 1854 /* copy data to mbuf */ 1855 bcopy(payload, mtod(m, caddr_t), len); 1856 1857 } else if (sd->nmbuf * MSIZE < cll->region1) { 1858 1859 /* 1860 * There's spare room in the cluster for an mbuf. Create one 1861 * and associate it with the payload that's in the cluster. 1862 */ 1863 1864 MPASS(clm != NULL); 1865 m = (struct mbuf *)(sd->cl + sd->nmbuf * MSIZE); 1866 /* No bzero required */ 1867 if (m_init(m, M_NOWAIT, MT_DATA, 1868 fr_offset == 0 ? M_PKTHDR | M_NOFREE : M_NOFREE)) 1869 return (NULL); 1870 fl->mbuf_inlined++; 1871 m_extaddref(m, payload, blen, &clm->refcount, rxb_free, 1872 swz->zone, sd->cl); 1873 if (sd->nmbuf++ == 0) 1874 counter_u64_add(extfree_refs, 1); 1875 1876 } else { 1877 1878 /* 1879 * Grab an mbuf from zone_mbuf and associate it with the 1880 * payload in the cluster. 1881 */ 1882 1883 m = fr_offset == 0 ? 1884 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA); 1885 if (m == NULL) 1886 return (NULL); 1887 fl->mbuf_allocated++; 1888 if (clm != NULL) { 1889 m_extaddref(m, payload, blen, &clm->refcount, 1890 rxb_free, swz->zone, sd->cl); 1891 if (sd->nmbuf++ == 0) 1892 counter_u64_add(extfree_refs, 1); 1893 } else { 1894 m_cljset(m, sd->cl, swz->type); 1895 sd->cl = NULL; /* consumed, not a recycle candidate */ 1896 } 1897 } 1898 if (fr_offset == 0) 1899 m->m_pkthdr.len = remaining; 1900 m->m_len = len; 1901 1902 if (fl->flags & FL_BUF_PACKING) { 1903 fl->rx_offset += blen; 1904 MPASS(fl->rx_offset <= hwb->size); 1905 if (fl->rx_offset < hwb->size) 1906 return (m); /* without advancing the cidx */ 1907 } 1908 1909 if (__predict_false(++fl->cidx % 8 == 0)) { 1910 uint16_t cidx = fl->cidx / 8; 1911 1912 if (__predict_false(cidx == fl->sidx)) 1913 fl->cidx = cidx = 0; 1914 fl->hw_cidx = cidx; 1915 } 1916 fl->rx_offset = 0; 1917 1918 return (m); 1919 } 1920 1921 static struct mbuf * 1922 get_fl_payload(struct adapter *sc, struct sge_fl *fl, uint32_t len_newbuf) 1923 { 1924 struct mbuf *m0, *m, **pnext; 1925 u_int remaining; 1926 const u_int total = G_RSPD_LEN(len_newbuf); 1927 1928 if (__predict_false(fl->flags & FL_BUF_RESUME)) { 1929 M_ASSERTPKTHDR(fl->m0); 1930 MPASS(fl->m0->m_pkthdr.len == total); 1931 MPASS(fl->remaining < total); 1932 1933 m0 = fl->m0; 1934 pnext = fl->pnext; 1935 remaining = fl->remaining; 1936 fl->flags &= ~FL_BUF_RESUME; 1937 goto get_segment; 1938 } 1939 1940 if (fl->rx_offset > 0 && len_newbuf & F_RSPD_NEWBUF) { 1941 fl->rx_offset = 0; 1942 if (__predict_false(++fl->cidx % 8 == 0)) { 1943 uint16_t cidx = fl->cidx / 8; 1944 1945 if (__predict_false(cidx == fl->sidx)) 1946 fl->cidx = cidx = 0; 1947 fl->hw_cidx = cidx; 1948 } 1949 } 1950 1951 /* 1952 * Payload starts at rx_offset in the current hw buffer. Its length is 1953 * 'len' and it may span multiple hw buffers. 1954 */ 1955 1956 m0 = get_scatter_segment(sc, fl, 0, total); 1957 if (m0 == NULL) 1958 return (NULL); 1959 remaining = total - m0->m_len; 1960 pnext = &m0->m_next; 1961 while (remaining > 0) { 1962 get_segment: 1963 MPASS(fl->rx_offset == 0); 1964 m = get_scatter_segment(sc, fl, total - remaining, remaining); 1965 if (__predict_false(m == NULL)) { 1966 fl->m0 = m0; 1967 fl->pnext = pnext; 1968 fl->remaining = remaining; 1969 fl->flags |= FL_BUF_RESUME; 1970 return (NULL); 1971 } 1972 *pnext = m; 1973 pnext = &m->m_next; 1974 remaining -= m->m_len; 1975 } 1976 *pnext = NULL; 1977 1978 M_ASSERTPKTHDR(m0); 1979 return (m0); 1980 } 1981 1982 static int 1983 t4_eth_rx(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0) 1984 { 1985 struct sge_rxq *rxq = iq_to_rxq(iq); 1986 struct ifnet *ifp = rxq->ifp; 1987 struct adapter *sc = iq->adapter; 1988 const struct cpl_rx_pkt *cpl = (const void *)(rss + 1); 1989 #if defined(INET) || defined(INET6) 1990 struct lro_ctrl *lro = &rxq->lro; 1991 #endif 1992 static const int sw_hashtype[4][2] = { 1993 {M_HASHTYPE_NONE, M_HASHTYPE_NONE}, 1994 {M_HASHTYPE_RSS_IPV4, M_HASHTYPE_RSS_IPV6}, 1995 {M_HASHTYPE_RSS_TCP_IPV4, M_HASHTYPE_RSS_TCP_IPV6}, 1996 {M_HASHTYPE_RSS_UDP_IPV4, M_HASHTYPE_RSS_UDP_IPV6}, 1997 }; 1998 1999 KASSERT(m0 != NULL, ("%s: no payload with opcode %02x", __func__, 2000 rss->opcode)); 2001 2002 m0->m_pkthdr.len -= sc->params.sge.fl_pktshift; 2003 m0->m_len -= sc->params.sge.fl_pktshift; 2004 m0->m_data += sc->params.sge.fl_pktshift; 2005 2006 m0->m_pkthdr.rcvif = ifp; 2007 M_HASHTYPE_SET(m0, sw_hashtype[rss->hash_type][rss->ipv6]); 2008 m0->m_pkthdr.flowid = be32toh(rss->hash_val); 2009 2010 if (cpl->csum_calc && !(cpl->err_vec & sc->params.tp.err_vec_mask)) { 2011 if (ifp->if_capenable & IFCAP_RXCSUM && 2012 cpl->l2info & htobe32(F_RXF_IP)) { 2013 m0->m_pkthdr.csum_flags = (CSUM_IP_CHECKED | 2014 CSUM_IP_VALID | CSUM_DATA_VALID | CSUM_PSEUDO_HDR); 2015 rxq->rxcsum++; 2016 } else if (ifp->if_capenable & IFCAP_RXCSUM_IPV6 && 2017 cpl->l2info & htobe32(F_RXF_IP6)) { 2018 m0->m_pkthdr.csum_flags = (CSUM_DATA_VALID_IPV6 | 2019 CSUM_PSEUDO_HDR); 2020 rxq->rxcsum++; 2021 } 2022 2023 if (__predict_false(cpl->ip_frag)) 2024 m0->m_pkthdr.csum_data = be16toh(cpl->csum); 2025 else 2026 m0->m_pkthdr.csum_data = 0xffff; 2027 } 2028 2029 if (cpl->vlan_ex) { 2030 m0->m_pkthdr.ether_vtag = be16toh(cpl->vlan); 2031 m0->m_flags |= M_VLANTAG; 2032 rxq->vlan_extraction++; 2033 } 2034 2035 #ifdef NUMA 2036 m0->m_pkthdr.numa_domain = ifp->if_numa_domain; 2037 #endif 2038 #if defined(INET) || defined(INET6) 2039 if (iq->flags & IQ_LRO_ENABLED) { 2040 if (sort_before_lro(lro)) { 2041 tcp_lro_queue_mbuf(lro, m0); 2042 return (0); /* queued for sort, then LRO */ 2043 } 2044 if (tcp_lro_rx(lro, m0, 0) == 0) 2045 return (0); /* queued for LRO */ 2046 } 2047 #endif 2048 ifp->if_input(ifp, m0); 2049 2050 return (0); 2051 } 2052 2053 /* 2054 * Must drain the wrq or make sure that someone else will. 2055 */ 2056 static void 2057 wrq_tx_drain(void *arg, int n) 2058 { 2059 struct sge_wrq *wrq = arg; 2060 struct sge_eq *eq = &wrq->eq; 2061 2062 EQ_LOCK(eq); 2063 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 2064 drain_wrq_wr_list(wrq->adapter, wrq); 2065 EQ_UNLOCK(eq); 2066 } 2067 2068 static void 2069 drain_wrq_wr_list(struct adapter *sc, struct sge_wrq *wrq) 2070 { 2071 struct sge_eq *eq = &wrq->eq; 2072 u_int available, dbdiff; /* # of hardware descriptors */ 2073 u_int n; 2074 struct wrqe *wr; 2075 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */ 2076 2077 EQ_LOCK_ASSERT_OWNED(eq); 2078 MPASS(TAILQ_EMPTY(&wrq->incomplete_wrs)); 2079 wr = STAILQ_FIRST(&wrq->wr_list); 2080 MPASS(wr != NULL); /* Must be called with something useful to do */ 2081 MPASS(eq->pidx == eq->dbidx); 2082 dbdiff = 0; 2083 2084 do { 2085 eq->cidx = read_hw_cidx(eq); 2086 if (eq->pidx == eq->cidx) 2087 available = eq->sidx - 1; 2088 else 2089 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2090 2091 MPASS(wr->wrq == wrq); 2092 n = howmany(wr->wr_len, EQ_ESIZE); 2093 if (available < n) 2094 break; 2095 2096 dst = (void *)&eq->desc[eq->pidx]; 2097 if (__predict_true(eq->sidx - eq->pidx > n)) { 2098 /* Won't wrap, won't end exactly at the status page. */ 2099 bcopy(&wr->wr[0], dst, wr->wr_len); 2100 eq->pidx += n; 2101 } else { 2102 int first_portion = (eq->sidx - eq->pidx) * EQ_ESIZE; 2103 2104 bcopy(&wr->wr[0], dst, first_portion); 2105 if (wr->wr_len > first_portion) { 2106 bcopy(&wr->wr[first_portion], &eq->desc[0], 2107 wr->wr_len - first_portion); 2108 } 2109 eq->pidx = n - (eq->sidx - eq->pidx); 2110 } 2111 wrq->tx_wrs_copied++; 2112 2113 if (available < eq->sidx / 4 && 2114 atomic_cmpset_int(&eq->equiq, 0, 1)) { 2115 /* 2116 * XXX: This is not 100% reliable with some 2117 * types of WRs. But this is a very unusual 2118 * situation for an ofld/ctrl queue anyway. 2119 */ 2120 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ | 2121 F_FW_WR_EQUEQ); 2122 } 2123 2124 dbdiff += n; 2125 if (dbdiff >= 16) { 2126 ring_eq_db(sc, eq, dbdiff); 2127 dbdiff = 0; 2128 } 2129 2130 STAILQ_REMOVE_HEAD(&wrq->wr_list, link); 2131 free_wrqe(wr); 2132 MPASS(wrq->nwr_pending > 0); 2133 wrq->nwr_pending--; 2134 MPASS(wrq->ndesc_needed >= n); 2135 wrq->ndesc_needed -= n; 2136 } while ((wr = STAILQ_FIRST(&wrq->wr_list)) != NULL); 2137 2138 if (dbdiff) 2139 ring_eq_db(sc, eq, dbdiff); 2140 } 2141 2142 /* 2143 * Doesn't fail. Holds on to work requests it can't send right away. 2144 */ 2145 void 2146 t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, struct wrqe *wr) 2147 { 2148 #ifdef INVARIANTS 2149 struct sge_eq *eq = &wrq->eq; 2150 #endif 2151 2152 EQ_LOCK_ASSERT_OWNED(eq); 2153 MPASS(wr != NULL); 2154 MPASS(wr->wr_len > 0 && wr->wr_len <= SGE_MAX_WR_LEN); 2155 MPASS((wr->wr_len & 0x7) == 0); 2156 2157 STAILQ_INSERT_TAIL(&wrq->wr_list, wr, link); 2158 wrq->nwr_pending++; 2159 wrq->ndesc_needed += howmany(wr->wr_len, EQ_ESIZE); 2160 2161 if (!TAILQ_EMPTY(&wrq->incomplete_wrs)) 2162 return; /* commit_wrq_wr will drain wr_list as well. */ 2163 2164 drain_wrq_wr_list(sc, wrq); 2165 2166 /* Doorbell must have caught up to the pidx. */ 2167 MPASS(eq->pidx == eq->dbidx); 2168 } 2169 2170 void 2171 t4_update_fl_bufsize(struct ifnet *ifp) 2172 { 2173 struct vi_info *vi = ifp->if_softc; 2174 struct adapter *sc = vi->pi->adapter; 2175 struct sge_rxq *rxq; 2176 #ifdef TCP_OFFLOAD 2177 struct sge_ofld_rxq *ofld_rxq; 2178 #endif 2179 struct sge_fl *fl; 2180 int i, maxp, mtu = ifp->if_mtu; 2181 2182 maxp = mtu_to_max_payload(sc, mtu); 2183 for_each_rxq(vi, i, rxq) { 2184 fl = &rxq->fl; 2185 2186 FL_LOCK(fl); 2187 find_best_refill_source(sc, fl, maxp); 2188 FL_UNLOCK(fl); 2189 } 2190 #ifdef TCP_OFFLOAD 2191 for_each_ofld_rxq(vi, i, ofld_rxq) { 2192 fl = &ofld_rxq->fl; 2193 2194 FL_LOCK(fl); 2195 find_best_refill_source(sc, fl, maxp); 2196 FL_UNLOCK(fl); 2197 } 2198 #endif 2199 } 2200 2201 static inline int 2202 mbuf_nsegs(struct mbuf *m) 2203 { 2204 2205 M_ASSERTPKTHDR(m); 2206 KASSERT(m->m_pkthdr.l5hlen > 0, 2207 ("%s: mbuf %p missing information on # of segments.", __func__, m)); 2208 2209 return (m->m_pkthdr.l5hlen); 2210 } 2211 2212 static inline void 2213 set_mbuf_nsegs(struct mbuf *m, uint8_t nsegs) 2214 { 2215 2216 M_ASSERTPKTHDR(m); 2217 m->m_pkthdr.l5hlen = nsegs; 2218 } 2219 2220 static inline int 2221 mbuf_cflags(struct mbuf *m) 2222 { 2223 2224 M_ASSERTPKTHDR(m); 2225 return (m->m_pkthdr.PH_loc.eight[4]); 2226 } 2227 2228 static inline void 2229 set_mbuf_cflags(struct mbuf *m, uint8_t flags) 2230 { 2231 2232 M_ASSERTPKTHDR(m); 2233 m->m_pkthdr.PH_loc.eight[4] = flags; 2234 } 2235 2236 static inline int 2237 mbuf_len16(struct mbuf *m) 2238 { 2239 int n; 2240 2241 M_ASSERTPKTHDR(m); 2242 n = m->m_pkthdr.PH_loc.eight[0]; 2243 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16); 2244 2245 return (n); 2246 } 2247 2248 static inline void 2249 set_mbuf_len16(struct mbuf *m, uint8_t len16) 2250 { 2251 2252 M_ASSERTPKTHDR(m); 2253 m->m_pkthdr.PH_loc.eight[0] = len16; 2254 } 2255 2256 #ifdef RATELIMIT 2257 static inline int 2258 mbuf_eo_nsegs(struct mbuf *m) 2259 { 2260 2261 M_ASSERTPKTHDR(m); 2262 return (m->m_pkthdr.PH_loc.eight[1]); 2263 } 2264 2265 static inline void 2266 set_mbuf_eo_nsegs(struct mbuf *m, uint8_t nsegs) 2267 { 2268 2269 M_ASSERTPKTHDR(m); 2270 m->m_pkthdr.PH_loc.eight[1] = nsegs; 2271 } 2272 2273 static inline int 2274 mbuf_eo_len16(struct mbuf *m) 2275 { 2276 int n; 2277 2278 M_ASSERTPKTHDR(m); 2279 n = m->m_pkthdr.PH_loc.eight[2]; 2280 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16); 2281 2282 return (n); 2283 } 2284 2285 static inline void 2286 set_mbuf_eo_len16(struct mbuf *m, uint8_t len16) 2287 { 2288 2289 M_ASSERTPKTHDR(m); 2290 m->m_pkthdr.PH_loc.eight[2] = len16; 2291 } 2292 2293 static inline int 2294 mbuf_eo_tsclk_tsoff(struct mbuf *m) 2295 { 2296 2297 M_ASSERTPKTHDR(m); 2298 return (m->m_pkthdr.PH_loc.eight[3]); 2299 } 2300 2301 static inline void 2302 set_mbuf_eo_tsclk_tsoff(struct mbuf *m, uint8_t tsclk_tsoff) 2303 { 2304 2305 M_ASSERTPKTHDR(m); 2306 m->m_pkthdr.PH_loc.eight[3] = tsclk_tsoff; 2307 } 2308 2309 static inline int 2310 needs_eo(struct mbuf *m) 2311 { 2312 2313 return (m->m_pkthdr.csum_flags & CSUM_SND_TAG); 2314 } 2315 #endif 2316 2317 /* 2318 * Try to allocate an mbuf to contain a raw work request. To make it 2319 * easy to construct the work request, don't allocate a chain but a 2320 * single mbuf. 2321 */ 2322 struct mbuf * 2323 alloc_wr_mbuf(int len, int how) 2324 { 2325 struct mbuf *m; 2326 2327 if (len <= MHLEN) 2328 m = m_gethdr(how, MT_DATA); 2329 else if (len <= MCLBYTES) 2330 m = m_getcl(how, MT_DATA, M_PKTHDR); 2331 else 2332 m = NULL; 2333 if (m == NULL) 2334 return (NULL); 2335 m->m_pkthdr.len = len; 2336 m->m_len = len; 2337 set_mbuf_cflags(m, MC_RAW_WR); 2338 set_mbuf_len16(m, howmany(len, 16)); 2339 return (m); 2340 } 2341 2342 static inline int 2343 needs_tso(struct mbuf *m) 2344 { 2345 2346 M_ASSERTPKTHDR(m); 2347 2348 return (m->m_pkthdr.csum_flags & CSUM_TSO); 2349 } 2350 2351 static inline int 2352 needs_l3_csum(struct mbuf *m) 2353 { 2354 2355 M_ASSERTPKTHDR(m); 2356 2357 return (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TSO)); 2358 } 2359 2360 static inline int 2361 needs_l4_csum(struct mbuf *m) 2362 { 2363 2364 M_ASSERTPKTHDR(m); 2365 2366 return (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_UDP_IPV6 | 2367 CSUM_TCP_IPV6 | CSUM_TSO)); 2368 } 2369 2370 static inline int 2371 needs_tcp_csum(struct mbuf *m) 2372 { 2373 2374 M_ASSERTPKTHDR(m); 2375 return (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_TCP_IPV6 | CSUM_TSO)); 2376 } 2377 2378 #ifdef RATELIMIT 2379 static inline int 2380 needs_udp_csum(struct mbuf *m) 2381 { 2382 2383 M_ASSERTPKTHDR(m); 2384 return (m->m_pkthdr.csum_flags & (CSUM_UDP | CSUM_UDP_IPV6)); 2385 } 2386 #endif 2387 2388 static inline int 2389 needs_vlan_insertion(struct mbuf *m) 2390 { 2391 2392 M_ASSERTPKTHDR(m); 2393 2394 return (m->m_flags & M_VLANTAG); 2395 } 2396 2397 static void * 2398 m_advance(struct mbuf **pm, int *poffset, int len) 2399 { 2400 struct mbuf *m = *pm; 2401 int offset = *poffset; 2402 uintptr_t p = 0; 2403 2404 MPASS(len > 0); 2405 2406 for (;;) { 2407 if (offset + len < m->m_len) { 2408 offset += len; 2409 p = mtod(m, uintptr_t) + offset; 2410 break; 2411 } 2412 len -= m->m_len - offset; 2413 m = m->m_next; 2414 offset = 0; 2415 MPASS(m != NULL); 2416 } 2417 *poffset = offset; 2418 *pm = m; 2419 return ((void *)p); 2420 } 2421 2422 static inline int 2423 count_mbuf_ext_pgs(struct mbuf *m, int skip, vm_paddr_t *nextaddr) 2424 { 2425 struct mbuf_ext_pgs *ext_pgs; 2426 vm_paddr_t paddr; 2427 int i, len, off, pglen, pgoff, seglen, segoff; 2428 int nsegs = 0; 2429 2430 MBUF_EXT_PGS_ASSERT(m); 2431 ext_pgs = m->m_ext.ext_pgs; 2432 off = mtod(m, vm_offset_t); 2433 len = m->m_len; 2434 off += skip; 2435 len -= skip; 2436 2437 if (ext_pgs->hdr_len != 0) { 2438 if (off >= ext_pgs->hdr_len) { 2439 off -= ext_pgs->hdr_len; 2440 } else { 2441 seglen = ext_pgs->hdr_len - off; 2442 segoff = off; 2443 seglen = min(seglen, len); 2444 off = 0; 2445 len -= seglen; 2446 paddr = pmap_kextract( 2447 (vm_offset_t)&ext_pgs->hdr[segoff]); 2448 if (*nextaddr != paddr) 2449 nsegs++; 2450 *nextaddr = paddr + seglen; 2451 } 2452 } 2453 pgoff = ext_pgs->first_pg_off; 2454 for (i = 0; i < ext_pgs->npgs && len > 0; i++) { 2455 pglen = mbuf_ext_pg_len(ext_pgs, i, pgoff); 2456 if (off >= pglen) { 2457 off -= pglen; 2458 pgoff = 0; 2459 continue; 2460 } 2461 seglen = pglen - off; 2462 segoff = pgoff + off; 2463 off = 0; 2464 seglen = min(seglen, len); 2465 len -= seglen; 2466 paddr = ext_pgs->pa[i] + segoff; 2467 if (*nextaddr != paddr) 2468 nsegs++; 2469 *nextaddr = paddr + seglen; 2470 pgoff = 0; 2471 }; 2472 if (len != 0) { 2473 seglen = min(len, ext_pgs->trail_len - off); 2474 len -= seglen; 2475 paddr = pmap_kextract((vm_offset_t)&ext_pgs->trail[off]); 2476 if (*nextaddr != paddr) 2477 nsegs++; 2478 *nextaddr = paddr + seglen; 2479 } 2480 2481 return (nsegs); 2482 } 2483 2484 2485 /* 2486 * Can deal with empty mbufs in the chain that have m_len = 0, but the chain 2487 * must have at least one mbuf that's not empty. It is possible for this 2488 * routine to return 0 if skip accounts for all the contents of the mbuf chain. 2489 */ 2490 static inline int 2491 count_mbuf_nsegs(struct mbuf *m, int skip, uint8_t *cflags) 2492 { 2493 vm_paddr_t nextaddr, paddr; 2494 vm_offset_t va; 2495 int len, nsegs; 2496 2497 M_ASSERTPKTHDR(m); 2498 MPASS(m->m_pkthdr.len > 0); 2499 MPASS(m->m_pkthdr.len >= skip); 2500 2501 nsegs = 0; 2502 nextaddr = 0; 2503 for (; m; m = m->m_next) { 2504 len = m->m_len; 2505 if (__predict_false(len == 0)) 2506 continue; 2507 if (skip >= len) { 2508 skip -= len; 2509 continue; 2510 } 2511 if ((m->m_flags & M_NOMAP) != 0) { 2512 *cflags |= MC_NOMAP; 2513 nsegs += count_mbuf_ext_pgs(m, skip, &nextaddr); 2514 skip = 0; 2515 continue; 2516 } 2517 va = mtod(m, vm_offset_t) + skip; 2518 len -= skip; 2519 skip = 0; 2520 paddr = pmap_kextract(va); 2521 nsegs += sglist_count((void *)(uintptr_t)va, len); 2522 if (paddr == nextaddr) 2523 nsegs--; 2524 nextaddr = pmap_kextract(va + len - 1) + 1; 2525 } 2526 2527 return (nsegs); 2528 } 2529 2530 /* 2531 * Analyze the mbuf to determine its tx needs. The mbuf passed in may change: 2532 * a) caller can assume it's been freed if this function returns with an error. 2533 * b) it may get defragged up if the gather list is too long for the hardware. 2534 */ 2535 int 2536 parse_pkt(struct adapter *sc, struct mbuf **mp) 2537 { 2538 struct mbuf *m0 = *mp, *m; 2539 int rc, nsegs, defragged = 0, offset; 2540 struct ether_header *eh; 2541 void *l3hdr; 2542 #if defined(INET) || defined(INET6) 2543 struct tcphdr *tcp; 2544 #endif 2545 uint16_t eh_type; 2546 uint8_t cflags; 2547 2548 cflags = 0; 2549 M_ASSERTPKTHDR(m0); 2550 if (__predict_false(m0->m_pkthdr.len < ETHER_HDR_LEN)) { 2551 rc = EINVAL; 2552 fail: 2553 m_freem(m0); 2554 *mp = NULL; 2555 return (rc); 2556 } 2557 restart: 2558 /* 2559 * First count the number of gather list segments in the payload. 2560 * Defrag the mbuf if nsegs exceeds the hardware limit. 2561 */ 2562 M_ASSERTPKTHDR(m0); 2563 MPASS(m0->m_pkthdr.len > 0); 2564 nsegs = count_mbuf_nsegs(m0, 0, &cflags); 2565 if (nsegs > (needs_tso(m0) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS)) { 2566 if (defragged++ > 0 || (m = m_defrag(m0, M_NOWAIT)) == NULL) { 2567 rc = EFBIG; 2568 goto fail; 2569 } 2570 *mp = m0 = m; /* update caller's copy after defrag */ 2571 goto restart; 2572 } 2573 2574 if (__predict_false(nsegs > 2 && m0->m_pkthdr.len <= MHLEN && 2575 !(cflags & MC_NOMAP))) { 2576 m0 = m_pullup(m0, m0->m_pkthdr.len); 2577 if (m0 == NULL) { 2578 /* Should have left well enough alone. */ 2579 rc = EFBIG; 2580 goto fail; 2581 } 2582 *mp = m0; /* update caller's copy after pullup */ 2583 goto restart; 2584 } 2585 set_mbuf_nsegs(m0, nsegs); 2586 set_mbuf_cflags(m0, cflags); 2587 if (sc->flags & IS_VF) 2588 set_mbuf_len16(m0, txpkt_vm_len16(nsegs, needs_tso(m0))); 2589 else 2590 set_mbuf_len16(m0, txpkt_len16(nsegs, needs_tso(m0))); 2591 2592 #ifdef RATELIMIT 2593 /* 2594 * Ethofld is limited to TCP and UDP for now, and only when L4 hw 2595 * checksumming is enabled. needs_l4_csum happens to check for all the 2596 * right things. 2597 */ 2598 if (__predict_false(needs_eo(m0) && !needs_l4_csum(m0))) { 2599 m_snd_tag_rele(m0->m_pkthdr.snd_tag); 2600 m0->m_pkthdr.snd_tag = NULL; 2601 m0->m_pkthdr.csum_flags &= ~CSUM_SND_TAG; 2602 } 2603 #endif 2604 2605 if (!needs_tso(m0) && 2606 #ifdef RATELIMIT 2607 !needs_eo(m0) && 2608 #endif 2609 !(sc->flags & IS_VF && (needs_l3_csum(m0) || needs_l4_csum(m0)))) 2610 return (0); 2611 2612 m = m0; 2613 eh = mtod(m, struct ether_header *); 2614 eh_type = ntohs(eh->ether_type); 2615 if (eh_type == ETHERTYPE_VLAN) { 2616 struct ether_vlan_header *evh = (void *)eh; 2617 2618 eh_type = ntohs(evh->evl_proto); 2619 m0->m_pkthdr.l2hlen = sizeof(*evh); 2620 } else 2621 m0->m_pkthdr.l2hlen = sizeof(*eh); 2622 2623 offset = 0; 2624 l3hdr = m_advance(&m, &offset, m0->m_pkthdr.l2hlen); 2625 2626 switch (eh_type) { 2627 #ifdef INET6 2628 case ETHERTYPE_IPV6: 2629 { 2630 struct ip6_hdr *ip6 = l3hdr; 2631 2632 MPASS(!needs_tso(m0) || ip6->ip6_nxt == IPPROTO_TCP); 2633 2634 m0->m_pkthdr.l3hlen = sizeof(*ip6); 2635 break; 2636 } 2637 #endif 2638 #ifdef INET 2639 case ETHERTYPE_IP: 2640 { 2641 struct ip *ip = l3hdr; 2642 2643 m0->m_pkthdr.l3hlen = ip->ip_hl * 4; 2644 break; 2645 } 2646 #endif 2647 default: 2648 panic("%s: ethertype 0x%04x unknown. if_cxgbe must be compiled" 2649 " with the same INET/INET6 options as the kernel.", 2650 __func__, eh_type); 2651 } 2652 2653 #if defined(INET) || defined(INET6) 2654 if (needs_tcp_csum(m0)) { 2655 tcp = m_advance(&m, &offset, m0->m_pkthdr.l3hlen); 2656 m0->m_pkthdr.l4hlen = tcp->th_off * 4; 2657 #ifdef RATELIMIT 2658 if (tsclk >= 0 && *(uint32_t *)(tcp + 1) == ntohl(0x0101080a)) { 2659 set_mbuf_eo_tsclk_tsoff(m0, 2660 V_FW_ETH_TX_EO_WR_TSCLK(tsclk) | 2661 V_FW_ETH_TX_EO_WR_TSOFF(sizeof(*tcp) / 2 + 1)); 2662 } else 2663 set_mbuf_eo_tsclk_tsoff(m0, 0); 2664 } else if (needs_udp_csum(m)) { 2665 m0->m_pkthdr.l4hlen = sizeof(struct udphdr); 2666 #endif 2667 } 2668 #ifdef RATELIMIT 2669 if (needs_eo(m0)) { 2670 u_int immhdrs; 2671 2672 /* EO WRs have the headers in the WR and not the GL. */ 2673 immhdrs = m0->m_pkthdr.l2hlen + m0->m_pkthdr.l3hlen + 2674 m0->m_pkthdr.l4hlen; 2675 cflags = 0; 2676 nsegs = count_mbuf_nsegs(m0, immhdrs, &cflags); 2677 MPASS(cflags == mbuf_cflags(m0)); 2678 set_mbuf_eo_nsegs(m0, nsegs); 2679 set_mbuf_eo_len16(m0, 2680 txpkt_eo_len16(nsegs, immhdrs, needs_tso(m0))); 2681 } 2682 #endif 2683 #endif 2684 MPASS(m0 == *mp); 2685 return (0); 2686 } 2687 2688 void * 2689 start_wrq_wr(struct sge_wrq *wrq, int len16, struct wrq_cookie *cookie) 2690 { 2691 struct sge_eq *eq = &wrq->eq; 2692 struct adapter *sc = wrq->adapter; 2693 int ndesc, available; 2694 struct wrqe *wr; 2695 void *w; 2696 2697 MPASS(len16 > 0); 2698 ndesc = howmany(len16, EQ_ESIZE / 16); 2699 MPASS(ndesc > 0 && ndesc <= SGE_MAX_WR_NDESC); 2700 2701 EQ_LOCK(eq); 2702 2703 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 2704 drain_wrq_wr_list(sc, wrq); 2705 2706 if (!STAILQ_EMPTY(&wrq->wr_list)) { 2707 slowpath: 2708 EQ_UNLOCK(eq); 2709 wr = alloc_wrqe(len16 * 16, wrq); 2710 if (__predict_false(wr == NULL)) 2711 return (NULL); 2712 cookie->pidx = -1; 2713 cookie->ndesc = ndesc; 2714 return (&wr->wr); 2715 } 2716 2717 eq->cidx = read_hw_cidx(eq); 2718 if (eq->pidx == eq->cidx) 2719 available = eq->sidx - 1; 2720 else 2721 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2722 if (available < ndesc) 2723 goto slowpath; 2724 2725 cookie->pidx = eq->pidx; 2726 cookie->ndesc = ndesc; 2727 TAILQ_INSERT_TAIL(&wrq->incomplete_wrs, cookie, link); 2728 2729 w = &eq->desc[eq->pidx]; 2730 IDXINCR(eq->pidx, ndesc, eq->sidx); 2731 if (__predict_false(cookie->pidx + ndesc > eq->sidx)) { 2732 w = &wrq->ss[0]; 2733 wrq->ss_pidx = cookie->pidx; 2734 wrq->ss_len = len16 * 16; 2735 } 2736 2737 EQ_UNLOCK(eq); 2738 2739 return (w); 2740 } 2741 2742 void 2743 commit_wrq_wr(struct sge_wrq *wrq, void *w, struct wrq_cookie *cookie) 2744 { 2745 struct sge_eq *eq = &wrq->eq; 2746 struct adapter *sc = wrq->adapter; 2747 int ndesc, pidx; 2748 struct wrq_cookie *prev, *next; 2749 2750 if (cookie->pidx == -1) { 2751 struct wrqe *wr = __containerof(w, struct wrqe, wr); 2752 2753 t4_wrq_tx(sc, wr); 2754 return; 2755 } 2756 2757 if (__predict_false(w == &wrq->ss[0])) { 2758 int n = (eq->sidx - wrq->ss_pidx) * EQ_ESIZE; 2759 2760 MPASS(wrq->ss_len > n); /* WR had better wrap around. */ 2761 bcopy(&wrq->ss[0], &eq->desc[wrq->ss_pidx], n); 2762 bcopy(&wrq->ss[n], &eq->desc[0], wrq->ss_len - n); 2763 wrq->tx_wrs_ss++; 2764 } else 2765 wrq->tx_wrs_direct++; 2766 2767 EQ_LOCK(eq); 2768 ndesc = cookie->ndesc; /* Can be more than SGE_MAX_WR_NDESC here. */ 2769 pidx = cookie->pidx; 2770 MPASS(pidx >= 0 && pidx < eq->sidx); 2771 prev = TAILQ_PREV(cookie, wrq_incomplete_wrs, link); 2772 next = TAILQ_NEXT(cookie, link); 2773 if (prev == NULL) { 2774 MPASS(pidx == eq->dbidx); 2775 if (next == NULL || ndesc >= 16) { 2776 int available; 2777 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */ 2778 2779 /* 2780 * Note that the WR via which we'll request tx updates 2781 * is at pidx and not eq->pidx, which has moved on 2782 * already. 2783 */ 2784 dst = (void *)&eq->desc[pidx]; 2785 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2786 if (available < eq->sidx / 4 && 2787 atomic_cmpset_int(&eq->equiq, 0, 1)) { 2788 /* 2789 * XXX: This is not 100% reliable with some 2790 * types of WRs. But this is a very unusual 2791 * situation for an ofld/ctrl queue anyway. 2792 */ 2793 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ | 2794 F_FW_WR_EQUEQ); 2795 } 2796 2797 ring_eq_db(wrq->adapter, eq, ndesc); 2798 } else { 2799 MPASS(IDXDIFF(next->pidx, pidx, eq->sidx) == ndesc); 2800 next->pidx = pidx; 2801 next->ndesc += ndesc; 2802 } 2803 } else { 2804 MPASS(IDXDIFF(pidx, prev->pidx, eq->sidx) == prev->ndesc); 2805 prev->ndesc += ndesc; 2806 } 2807 TAILQ_REMOVE(&wrq->incomplete_wrs, cookie, link); 2808 2809 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 2810 drain_wrq_wr_list(sc, wrq); 2811 2812 #ifdef INVARIANTS 2813 if (TAILQ_EMPTY(&wrq->incomplete_wrs)) { 2814 /* Doorbell must have caught up to the pidx. */ 2815 MPASS(wrq->eq.pidx == wrq->eq.dbidx); 2816 } 2817 #endif 2818 EQ_UNLOCK(eq); 2819 } 2820 2821 static u_int 2822 can_resume_eth_tx(struct mp_ring *r) 2823 { 2824 struct sge_eq *eq = r->cookie; 2825 2826 return (total_available_tx_desc(eq) > eq->sidx / 8); 2827 } 2828 2829 static inline int 2830 cannot_use_txpkts(struct mbuf *m) 2831 { 2832 /* maybe put a GL limit too, to avoid silliness? */ 2833 2834 return (needs_tso(m) || (mbuf_cflags(m) & MC_RAW_WR) != 0); 2835 } 2836 2837 static inline int 2838 discard_tx(struct sge_eq *eq) 2839 { 2840 2841 return ((eq->flags & (EQ_ENABLED | EQ_QFLUSH)) != EQ_ENABLED); 2842 } 2843 2844 static inline int 2845 wr_can_update_eq(struct fw_eth_tx_pkts_wr *wr) 2846 { 2847 2848 switch (G_FW_WR_OP(be32toh(wr->op_pkd))) { 2849 case FW_ULPTX_WR: 2850 case FW_ETH_TX_PKT_WR: 2851 case FW_ETH_TX_PKTS_WR: 2852 case FW_ETH_TX_PKTS2_WR: 2853 case FW_ETH_TX_PKT_VM_WR: 2854 return (1); 2855 default: 2856 return (0); 2857 } 2858 } 2859 2860 /* 2861 * r->items[cidx] to r->items[pidx], with a wraparound at r->size, are ready to 2862 * be consumed. Return the actual number consumed. 0 indicates a stall. 2863 */ 2864 static u_int 2865 eth_tx(struct mp_ring *r, u_int cidx, u_int pidx) 2866 { 2867 struct sge_txq *txq = r->cookie; 2868 struct sge_eq *eq = &txq->eq; 2869 struct ifnet *ifp = txq->ifp; 2870 struct vi_info *vi = ifp->if_softc; 2871 struct port_info *pi = vi->pi; 2872 struct adapter *sc = pi->adapter; 2873 u_int total, remaining; /* # of packets */ 2874 u_int available, dbdiff; /* # of hardware descriptors */ 2875 u_int n, next_cidx; 2876 struct mbuf *m0, *tail; 2877 struct txpkts txp; 2878 struct fw_eth_tx_pkts_wr *wr; /* any fw WR struct will do */ 2879 2880 remaining = IDXDIFF(pidx, cidx, r->size); 2881 MPASS(remaining > 0); /* Must not be called without work to do. */ 2882 total = 0; 2883 2884 TXQ_LOCK(txq); 2885 if (__predict_false(discard_tx(eq))) { 2886 while (cidx != pidx) { 2887 m0 = r->items[cidx]; 2888 m_freem(m0); 2889 if (++cidx == r->size) 2890 cidx = 0; 2891 } 2892 reclaim_tx_descs(txq, 2048); 2893 total = remaining; 2894 goto done; 2895 } 2896 2897 /* How many hardware descriptors do we have readily available. */ 2898 if (eq->pidx == eq->cidx) 2899 available = eq->sidx - 1; 2900 else 2901 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2902 dbdiff = IDXDIFF(eq->pidx, eq->dbidx, eq->sidx); 2903 2904 while (remaining > 0) { 2905 2906 m0 = r->items[cidx]; 2907 M_ASSERTPKTHDR(m0); 2908 MPASS(m0->m_nextpkt == NULL); 2909 2910 if (available < SGE_MAX_WR_NDESC) { 2911 available += reclaim_tx_descs(txq, 64); 2912 if (available < howmany(mbuf_len16(m0), EQ_ESIZE / 16)) 2913 break; /* out of descriptors */ 2914 } 2915 2916 next_cidx = cidx + 1; 2917 if (__predict_false(next_cidx == r->size)) 2918 next_cidx = 0; 2919 2920 wr = (void *)&eq->desc[eq->pidx]; 2921 if (sc->flags & IS_VF) { 2922 total++; 2923 remaining--; 2924 ETHER_BPF_MTAP(ifp, m0); 2925 n = write_txpkt_vm_wr(sc, txq, (void *)wr, m0, 2926 available); 2927 } else if (remaining > 1 && 2928 try_txpkts(m0, r->items[next_cidx], &txp, available) == 0) { 2929 2930 /* pkts at cidx, next_cidx should both be in txp. */ 2931 MPASS(txp.npkt == 2); 2932 tail = r->items[next_cidx]; 2933 MPASS(tail->m_nextpkt == NULL); 2934 ETHER_BPF_MTAP(ifp, m0); 2935 ETHER_BPF_MTAP(ifp, tail); 2936 m0->m_nextpkt = tail; 2937 2938 if (__predict_false(++next_cidx == r->size)) 2939 next_cidx = 0; 2940 2941 while (next_cidx != pidx) { 2942 if (add_to_txpkts(r->items[next_cidx], &txp, 2943 available) != 0) 2944 break; 2945 tail->m_nextpkt = r->items[next_cidx]; 2946 tail = tail->m_nextpkt; 2947 ETHER_BPF_MTAP(ifp, tail); 2948 if (__predict_false(++next_cidx == r->size)) 2949 next_cidx = 0; 2950 } 2951 2952 n = write_txpkts_wr(txq, wr, m0, &txp, available); 2953 total += txp.npkt; 2954 remaining -= txp.npkt; 2955 } else if (mbuf_cflags(m0) & MC_RAW_WR) { 2956 total++; 2957 remaining--; 2958 n = write_raw_wr(txq, (void *)wr, m0, available); 2959 } else { 2960 total++; 2961 remaining--; 2962 ETHER_BPF_MTAP(ifp, m0); 2963 n = write_txpkt_wr(txq, (void *)wr, m0, available); 2964 } 2965 MPASS(n >= 1 && n <= available && n <= SGE_MAX_WR_NDESC); 2966 2967 available -= n; 2968 dbdiff += n; 2969 IDXINCR(eq->pidx, n, eq->sidx); 2970 2971 if (wr_can_update_eq(wr)) { 2972 if (total_available_tx_desc(eq) < eq->sidx / 4 && 2973 atomic_cmpset_int(&eq->equiq, 0, 1)) { 2974 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ | 2975 F_FW_WR_EQUEQ); 2976 eq->equeqidx = eq->pidx; 2977 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 2978 32) { 2979 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ); 2980 eq->equeqidx = eq->pidx; 2981 } 2982 } 2983 2984 if (dbdiff >= 16 && remaining >= 4) { 2985 ring_eq_db(sc, eq, dbdiff); 2986 available += reclaim_tx_descs(txq, 4 * dbdiff); 2987 dbdiff = 0; 2988 } 2989 2990 cidx = next_cidx; 2991 } 2992 if (dbdiff != 0) { 2993 ring_eq_db(sc, eq, dbdiff); 2994 reclaim_tx_descs(txq, 32); 2995 } 2996 done: 2997 TXQ_UNLOCK(txq); 2998 2999 return (total); 3000 } 3001 3002 static inline void 3003 init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int pktc_idx, 3004 int qsize) 3005 { 3006 3007 KASSERT(tmr_idx >= 0 && tmr_idx < SGE_NTIMERS, 3008 ("%s: bad tmr_idx %d", __func__, tmr_idx)); 3009 KASSERT(pktc_idx < SGE_NCOUNTERS, /* -ve is ok, means don't use */ 3010 ("%s: bad pktc_idx %d", __func__, pktc_idx)); 3011 3012 iq->flags = 0; 3013 iq->adapter = sc; 3014 iq->intr_params = V_QINTR_TIMER_IDX(tmr_idx); 3015 iq->intr_pktc_idx = SGE_NCOUNTERS - 1; 3016 if (pktc_idx >= 0) { 3017 iq->intr_params |= F_QINTR_CNT_EN; 3018 iq->intr_pktc_idx = pktc_idx; 3019 } 3020 iq->qsize = roundup2(qsize, 16); /* See FW_IQ_CMD/iqsize */ 3021 iq->sidx = iq->qsize - sc->params.sge.spg_len / IQ_ESIZE; 3022 } 3023 3024 static inline void 3025 init_fl(struct adapter *sc, struct sge_fl *fl, int qsize, int maxp, char *name) 3026 { 3027 3028 fl->qsize = qsize; 3029 fl->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE; 3030 strlcpy(fl->lockname, name, sizeof(fl->lockname)); 3031 if (sc->flags & BUF_PACKING_OK && 3032 ((!is_t4(sc) && buffer_packing) || /* T5+: enabled unless 0 */ 3033 (is_t4(sc) && buffer_packing == 1)))/* T4: disabled unless 1 */ 3034 fl->flags |= FL_BUF_PACKING; 3035 find_best_refill_source(sc, fl, maxp); 3036 find_safe_refill_source(sc, fl); 3037 } 3038 3039 static inline void 3040 init_eq(struct adapter *sc, struct sge_eq *eq, int eqtype, int qsize, 3041 uint8_t tx_chan, uint16_t iqid, char *name) 3042 { 3043 KASSERT(eqtype <= EQ_TYPEMASK, ("%s: bad qtype %d", __func__, eqtype)); 3044 3045 eq->flags = eqtype & EQ_TYPEMASK; 3046 eq->tx_chan = tx_chan; 3047 eq->iqid = iqid; 3048 eq->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE; 3049 strlcpy(eq->lockname, name, sizeof(eq->lockname)); 3050 } 3051 3052 static int 3053 alloc_ring(struct adapter *sc, size_t len, bus_dma_tag_t *tag, 3054 bus_dmamap_t *map, bus_addr_t *pa, void **va) 3055 { 3056 int rc; 3057 3058 rc = bus_dma_tag_create(sc->dmat, 512, 0, BUS_SPACE_MAXADDR, 3059 BUS_SPACE_MAXADDR, NULL, NULL, len, 1, len, 0, NULL, NULL, tag); 3060 if (rc != 0) { 3061 device_printf(sc->dev, "cannot allocate DMA tag: %d\n", rc); 3062 goto done; 3063 } 3064 3065 rc = bus_dmamem_alloc(*tag, va, 3066 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, map); 3067 if (rc != 0) { 3068 device_printf(sc->dev, "cannot allocate DMA memory: %d\n", rc); 3069 goto done; 3070 } 3071 3072 rc = bus_dmamap_load(*tag, *map, *va, len, oneseg_dma_callback, pa, 0); 3073 if (rc != 0) { 3074 device_printf(sc->dev, "cannot load DMA map: %d\n", rc); 3075 goto done; 3076 } 3077 done: 3078 if (rc) 3079 free_ring(sc, *tag, *map, *pa, *va); 3080 3081 return (rc); 3082 } 3083 3084 static int 3085 free_ring(struct adapter *sc, bus_dma_tag_t tag, bus_dmamap_t map, 3086 bus_addr_t pa, void *va) 3087 { 3088 if (pa) 3089 bus_dmamap_unload(tag, map); 3090 if (va) 3091 bus_dmamem_free(tag, va, map); 3092 if (tag) 3093 bus_dma_tag_destroy(tag); 3094 3095 return (0); 3096 } 3097 3098 /* 3099 * Allocates the ring for an ingress queue and an optional freelist. If the 3100 * freelist is specified it will be allocated and then associated with the 3101 * ingress queue. 3102 * 3103 * Returns errno on failure. Resources allocated up to that point may still be 3104 * allocated. Caller is responsible for cleanup in case this function fails. 3105 * 3106 * If the ingress queue will take interrupts directly then the intr_idx 3107 * specifies the vector, starting from 0. -1 means the interrupts for this 3108 * queue should be forwarded to the fwq. 3109 */ 3110 static int 3111 alloc_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl, 3112 int intr_idx, int cong) 3113 { 3114 int rc, i, cntxt_id; 3115 size_t len; 3116 struct fw_iq_cmd c; 3117 struct port_info *pi = vi->pi; 3118 struct adapter *sc = iq->adapter; 3119 struct sge_params *sp = &sc->params.sge; 3120 __be32 v = 0; 3121 3122 len = iq->qsize * IQ_ESIZE; 3123 rc = alloc_ring(sc, len, &iq->desc_tag, &iq->desc_map, &iq->ba, 3124 (void **)&iq->desc); 3125 if (rc != 0) 3126 return (rc); 3127 3128 bzero(&c, sizeof(c)); 3129 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 3130 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) | 3131 V_FW_IQ_CMD_VFN(0)); 3132 3133 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART | 3134 FW_LEN16(c)); 3135 3136 /* Special handling for firmware event queue */ 3137 if (iq == &sc->sge.fwq) 3138 v |= F_FW_IQ_CMD_IQASYNCH; 3139 3140 if (intr_idx < 0) { 3141 /* Forwarded interrupts, all headed to fwq */ 3142 v |= F_FW_IQ_CMD_IQANDST; 3143 v |= V_FW_IQ_CMD_IQANDSTINDEX(sc->sge.fwq.cntxt_id); 3144 } else { 3145 KASSERT(intr_idx < sc->intr_count, 3146 ("%s: invalid direct intr_idx %d", __func__, intr_idx)); 3147 v |= V_FW_IQ_CMD_IQANDSTINDEX(intr_idx); 3148 } 3149 3150 c.type_to_iqandstindex = htobe32(v | 3151 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) | 3152 V_FW_IQ_CMD_VIID(vi->viid) | 3153 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT)); 3154 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->tx_chan) | 3155 F_FW_IQ_CMD_IQGTSMODE | 3156 V_FW_IQ_CMD_IQINTCNTTHRESH(iq->intr_pktc_idx) | 3157 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4)); 3158 c.iqsize = htobe16(iq->qsize); 3159 c.iqaddr = htobe64(iq->ba); 3160 if (cong >= 0) 3161 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN); 3162 3163 if (fl) { 3164 mtx_init(&fl->fl_lock, fl->lockname, NULL, MTX_DEF); 3165 3166 len = fl->qsize * EQ_ESIZE; 3167 rc = alloc_ring(sc, len, &fl->desc_tag, &fl->desc_map, 3168 &fl->ba, (void **)&fl->desc); 3169 if (rc) 3170 return (rc); 3171 3172 /* Allocate space for one software descriptor per buffer. */ 3173 rc = alloc_fl_sdesc(fl); 3174 if (rc != 0) { 3175 device_printf(sc->dev, 3176 "failed to setup fl software descriptors: %d\n", 3177 rc); 3178 return (rc); 3179 } 3180 3181 if (fl->flags & FL_BUF_PACKING) { 3182 fl->lowat = roundup2(sp->fl_starve_threshold2, 8); 3183 fl->buf_boundary = sp->pack_boundary; 3184 } else { 3185 fl->lowat = roundup2(sp->fl_starve_threshold, 8); 3186 fl->buf_boundary = 16; 3187 } 3188 if (fl_pad && fl->buf_boundary < sp->pad_boundary) 3189 fl->buf_boundary = sp->pad_boundary; 3190 3191 c.iqns_to_fl0congen |= 3192 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) | 3193 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO | 3194 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) | 3195 (fl->flags & FL_BUF_PACKING ? F_FW_IQ_CMD_FL0PACKEN : 3196 0)); 3197 if (cong >= 0) { 3198 c.iqns_to_fl0congen |= 3199 htobe32(V_FW_IQ_CMD_FL0CNGCHMAP(cong) | 3200 F_FW_IQ_CMD_FL0CONGCIF | 3201 F_FW_IQ_CMD_FL0CONGEN); 3202 } 3203 c.fl0dcaen_to_fl0cidxfthresh = 3204 htobe16(V_FW_IQ_CMD_FL0FBMIN(chip_id(sc) <= CHELSIO_T5 ? 3205 X_FETCHBURSTMIN_128B : X_FETCHBURSTMIN_64B) | 3206 V_FW_IQ_CMD_FL0FBMAX(chip_id(sc) <= CHELSIO_T5 ? 3207 X_FETCHBURSTMAX_512B : X_FETCHBURSTMAX_256B)); 3208 c.fl0size = htobe16(fl->qsize); 3209 c.fl0addr = htobe64(fl->ba); 3210 } 3211 3212 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3213 if (rc != 0) { 3214 device_printf(sc->dev, 3215 "failed to create ingress queue: %d\n", rc); 3216 return (rc); 3217 } 3218 3219 iq->cidx = 0; 3220 iq->gen = F_RSPD_GEN; 3221 iq->intr_next = iq->intr_params; 3222 iq->cntxt_id = be16toh(c.iqid); 3223 iq->abs_id = be16toh(c.physiqid); 3224 iq->flags |= IQ_ALLOCATED; 3225 3226 cntxt_id = iq->cntxt_id - sc->sge.iq_start; 3227 if (cntxt_id >= sc->sge.niq) { 3228 panic ("%s: iq->cntxt_id (%d) more than the max (%d)", __func__, 3229 cntxt_id, sc->sge.niq - 1); 3230 } 3231 sc->sge.iqmap[cntxt_id] = iq; 3232 3233 if (fl) { 3234 u_int qid; 3235 3236 iq->flags |= IQ_HAS_FL; 3237 fl->cntxt_id = be16toh(c.fl0id); 3238 fl->pidx = fl->cidx = 0; 3239 3240 cntxt_id = fl->cntxt_id - sc->sge.eq_start; 3241 if (cntxt_id >= sc->sge.neq) { 3242 panic("%s: fl->cntxt_id (%d) more than the max (%d)", 3243 __func__, cntxt_id, sc->sge.neq - 1); 3244 } 3245 sc->sge.eqmap[cntxt_id] = (void *)fl; 3246 3247 qid = fl->cntxt_id; 3248 if (isset(&sc->doorbells, DOORBELL_UDB)) { 3249 uint32_t s_qpp = sc->params.sge.eq_s_qpp; 3250 uint32_t mask = (1 << s_qpp) - 1; 3251 volatile uint8_t *udb; 3252 3253 udb = sc->udbs_base + UDBS_DB_OFFSET; 3254 udb += (qid >> s_qpp) << PAGE_SHIFT; 3255 qid &= mask; 3256 if (qid < PAGE_SIZE / UDBS_SEG_SIZE) { 3257 udb += qid << UDBS_SEG_SHIFT; 3258 qid = 0; 3259 } 3260 fl->udb = (volatile void *)udb; 3261 } 3262 fl->dbval = V_QID(qid) | sc->chip_params->sge_fl_db; 3263 3264 FL_LOCK(fl); 3265 /* Enough to make sure the SGE doesn't think it's starved */ 3266 refill_fl(sc, fl, fl->lowat); 3267 FL_UNLOCK(fl); 3268 } 3269 3270 if (chip_id(sc) >= CHELSIO_T5 && !(sc->flags & IS_VF) && cong >= 0) { 3271 uint32_t param, val; 3272 3273 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 3274 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) | 3275 V_FW_PARAMS_PARAM_YZ(iq->cntxt_id); 3276 if (cong == 0) 3277 val = 1 << 19; 3278 else { 3279 val = 2 << 19; 3280 for (i = 0; i < 4; i++) { 3281 if (cong & (1 << i)) 3282 val |= 1 << (i << 2); 3283 } 3284 } 3285 3286 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 3287 if (rc != 0) { 3288 /* report error but carry on */ 3289 device_printf(sc->dev, 3290 "failed to set congestion manager context for " 3291 "ingress queue %d: %d\n", iq->cntxt_id, rc); 3292 } 3293 } 3294 3295 /* Enable IQ interrupts */ 3296 atomic_store_rel_int(&iq->state, IQS_IDLE); 3297 t4_write_reg(sc, sc->sge_gts_reg, V_SEINTARM(iq->intr_params) | 3298 V_INGRESSQID(iq->cntxt_id)); 3299 3300 return (0); 3301 } 3302 3303 static int 3304 free_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl) 3305 { 3306 int rc; 3307 struct adapter *sc = iq->adapter; 3308 device_t dev; 3309 3310 if (sc == NULL) 3311 return (0); /* nothing to do */ 3312 3313 dev = vi ? vi->dev : sc->dev; 3314 3315 if (iq->flags & IQ_ALLOCATED) { 3316 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0, 3317 FW_IQ_TYPE_FL_INT_CAP, iq->cntxt_id, 3318 fl ? fl->cntxt_id : 0xffff, 0xffff); 3319 if (rc != 0) { 3320 device_printf(dev, 3321 "failed to free queue %p: %d\n", iq, rc); 3322 return (rc); 3323 } 3324 iq->flags &= ~IQ_ALLOCATED; 3325 } 3326 3327 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, iq->desc); 3328 3329 bzero(iq, sizeof(*iq)); 3330 3331 if (fl) { 3332 free_ring(sc, fl->desc_tag, fl->desc_map, fl->ba, 3333 fl->desc); 3334 3335 if (fl->sdesc) 3336 free_fl_sdesc(sc, fl); 3337 3338 if (mtx_initialized(&fl->fl_lock)) 3339 mtx_destroy(&fl->fl_lock); 3340 3341 bzero(fl, sizeof(*fl)); 3342 } 3343 3344 return (0); 3345 } 3346 3347 static void 3348 add_iq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid, 3349 struct sge_iq *iq) 3350 { 3351 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3352 3353 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, &iq->ba, 3354 "bus address of descriptor ring"); 3355 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3356 iq->qsize * IQ_ESIZE, "descriptor ring size in bytes"); 3357 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "abs_id", 3358 CTLTYPE_INT | CTLFLAG_RD, &iq->abs_id, 0, sysctl_uint16, "I", 3359 "absolute id of the queue"); 3360 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 3361 CTLTYPE_INT | CTLFLAG_RD, &iq->cntxt_id, 0, sysctl_uint16, "I", 3362 "SGE context id of the queue"); 3363 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx", 3364 CTLTYPE_INT | CTLFLAG_RD, &iq->cidx, 0, sysctl_uint16, "I", 3365 "consumer index"); 3366 } 3367 3368 static void 3369 add_fl_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx, 3370 struct sysctl_oid *oid, struct sge_fl *fl) 3371 { 3372 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3373 3374 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL, 3375 "freelist"); 3376 children = SYSCTL_CHILDREN(oid); 3377 3378 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, 3379 &fl->ba, "bus address of descriptor ring"); 3380 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3381 fl->sidx * EQ_ESIZE + sc->params.sge.spg_len, 3382 "desc ring size in bytes"); 3383 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 3384 CTLTYPE_INT | CTLFLAG_RD, &fl->cntxt_id, 0, sysctl_uint16, "I", 3385 "SGE context id of the freelist"); 3386 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "padding", CTLFLAG_RD, NULL, 3387 fl_pad ? 1 : 0, "padding enabled"); 3388 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "packing", CTLFLAG_RD, NULL, 3389 fl->flags & FL_BUF_PACKING ? 1 : 0, "packing enabled"); 3390 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &fl->cidx, 3391 0, "consumer index"); 3392 if (fl->flags & FL_BUF_PACKING) { 3393 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rx_offset", 3394 CTLFLAG_RD, &fl->rx_offset, 0, "packing rx offset"); 3395 } 3396 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &fl->pidx, 3397 0, "producer index"); 3398 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_allocated", 3399 CTLFLAG_RD, &fl->mbuf_allocated, "# of mbuf allocated"); 3400 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_inlined", 3401 CTLFLAG_RD, &fl->mbuf_inlined, "# of mbuf inlined in clusters"); 3402 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_allocated", 3403 CTLFLAG_RD, &fl->cl_allocated, "# of clusters allocated"); 3404 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_recycled", 3405 CTLFLAG_RD, &fl->cl_recycled, "# of clusters recycled"); 3406 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_fast_recycled", 3407 CTLFLAG_RD, &fl->cl_fast_recycled, "# of clusters recycled (fast)"); 3408 } 3409 3410 static int 3411 alloc_fwq(struct adapter *sc) 3412 { 3413 int rc, intr_idx; 3414 struct sge_iq *fwq = &sc->sge.fwq; 3415 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev); 3416 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3417 3418 init_iq(fwq, sc, 0, 0, FW_IQ_QSIZE); 3419 if (sc->flags & IS_VF) 3420 intr_idx = 0; 3421 else 3422 intr_idx = sc->intr_count > 1 ? 1 : 0; 3423 rc = alloc_iq_fl(&sc->port[0]->vi[0], fwq, NULL, intr_idx, -1); 3424 if (rc != 0) { 3425 device_printf(sc->dev, 3426 "failed to create firmware event queue: %d\n", rc); 3427 return (rc); 3428 } 3429 3430 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "fwq", CTLFLAG_RD, 3431 NULL, "firmware event queue"); 3432 add_iq_sysctls(&sc->ctx, oid, fwq); 3433 3434 return (0); 3435 } 3436 3437 static int 3438 free_fwq(struct adapter *sc) 3439 { 3440 return free_iq_fl(NULL, &sc->sge.fwq, NULL); 3441 } 3442 3443 static int 3444 alloc_ctrlq(struct adapter *sc, struct sge_wrq *ctrlq, int idx, 3445 struct sysctl_oid *oid) 3446 { 3447 int rc; 3448 char name[16]; 3449 struct sysctl_oid_list *children; 3450 3451 snprintf(name, sizeof(name), "%s ctrlq%d", device_get_nameunit(sc->dev), 3452 idx); 3453 init_eq(sc, &ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE, sc->port[idx]->tx_chan, 3454 sc->sge.fwq.cntxt_id, name); 3455 3456 children = SYSCTL_CHILDREN(oid); 3457 snprintf(name, sizeof(name), "%d", idx); 3458 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, name, CTLFLAG_RD, 3459 NULL, "ctrl queue"); 3460 rc = alloc_wrq(sc, NULL, ctrlq, oid); 3461 3462 return (rc); 3463 } 3464 3465 int 3466 tnl_cong(struct port_info *pi, int drop) 3467 { 3468 3469 if (drop == -1) 3470 return (-1); 3471 else if (drop == 1) 3472 return (0); 3473 else 3474 return (pi->rx_e_chan_map); 3475 } 3476 3477 static int 3478 alloc_rxq(struct vi_info *vi, struct sge_rxq *rxq, int intr_idx, int idx, 3479 struct sysctl_oid *oid) 3480 { 3481 int rc; 3482 struct adapter *sc = vi->pi->adapter; 3483 struct sysctl_oid_list *children; 3484 char name[16]; 3485 3486 rc = alloc_iq_fl(vi, &rxq->iq, &rxq->fl, intr_idx, 3487 tnl_cong(vi->pi, cong_drop)); 3488 if (rc != 0) 3489 return (rc); 3490 3491 if (idx == 0) 3492 sc->sge.iq_base = rxq->iq.abs_id - rxq->iq.cntxt_id; 3493 else 3494 KASSERT(rxq->iq.cntxt_id + sc->sge.iq_base == rxq->iq.abs_id, 3495 ("iq_base mismatch")); 3496 KASSERT(sc->sge.iq_base == 0 || sc->flags & IS_VF, 3497 ("PF with non-zero iq_base")); 3498 3499 /* 3500 * The freelist is just barely above the starvation threshold right now, 3501 * fill it up a bit more. 3502 */ 3503 FL_LOCK(&rxq->fl); 3504 refill_fl(sc, &rxq->fl, 128); 3505 FL_UNLOCK(&rxq->fl); 3506 3507 #if defined(INET) || defined(INET6) 3508 rc = tcp_lro_init_args(&rxq->lro, vi->ifp, lro_entries, lro_mbufs); 3509 if (rc != 0) 3510 return (rc); 3511 MPASS(rxq->lro.ifp == vi->ifp); /* also indicates LRO init'ed */ 3512 3513 if (vi->ifp->if_capenable & IFCAP_LRO) 3514 rxq->iq.flags |= IQ_LRO_ENABLED; 3515 #endif 3516 if (vi->ifp->if_capenable & IFCAP_HWRXTSTMP) 3517 rxq->iq.flags |= IQ_RX_TIMESTAMP; 3518 rxq->ifp = vi->ifp; 3519 3520 children = SYSCTL_CHILDREN(oid); 3521 3522 snprintf(name, sizeof(name), "%d", idx); 3523 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 3524 NULL, "rx queue"); 3525 children = SYSCTL_CHILDREN(oid); 3526 3527 add_iq_sysctls(&vi->ctx, oid, &rxq->iq); 3528 #if defined(INET) || defined(INET6) 3529 SYSCTL_ADD_U64(&vi->ctx, children, OID_AUTO, "lro_queued", CTLFLAG_RD, 3530 &rxq->lro.lro_queued, 0, NULL); 3531 SYSCTL_ADD_U64(&vi->ctx, children, OID_AUTO, "lro_flushed", CTLFLAG_RD, 3532 &rxq->lro.lro_flushed, 0, NULL); 3533 #endif 3534 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "rxcsum", CTLFLAG_RD, 3535 &rxq->rxcsum, "# of times hardware assisted with checksum"); 3536 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_extraction", 3537 CTLFLAG_RD, &rxq->vlan_extraction, 3538 "# of times hardware extracted 802.1Q tag"); 3539 3540 add_fl_sysctls(sc, &vi->ctx, oid, &rxq->fl); 3541 3542 return (rc); 3543 } 3544 3545 static int 3546 free_rxq(struct vi_info *vi, struct sge_rxq *rxq) 3547 { 3548 int rc; 3549 3550 #if defined(INET) || defined(INET6) 3551 if (rxq->lro.ifp) { 3552 tcp_lro_free(&rxq->lro); 3553 rxq->lro.ifp = NULL; 3554 } 3555 #endif 3556 3557 rc = free_iq_fl(vi, &rxq->iq, &rxq->fl); 3558 if (rc == 0) 3559 bzero(rxq, sizeof(*rxq)); 3560 3561 return (rc); 3562 } 3563 3564 #ifdef TCP_OFFLOAD 3565 static int 3566 alloc_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq, 3567 int intr_idx, int idx, struct sysctl_oid *oid) 3568 { 3569 struct port_info *pi = vi->pi; 3570 int rc; 3571 struct sysctl_oid_list *children; 3572 char name[16]; 3573 3574 rc = alloc_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl, intr_idx, 0); 3575 if (rc != 0) 3576 return (rc); 3577 3578 children = SYSCTL_CHILDREN(oid); 3579 3580 snprintf(name, sizeof(name), "%d", idx); 3581 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 3582 NULL, "rx queue"); 3583 add_iq_sysctls(&vi->ctx, oid, &ofld_rxq->iq); 3584 add_fl_sysctls(pi->adapter, &vi->ctx, oid, &ofld_rxq->fl); 3585 3586 return (rc); 3587 } 3588 3589 static int 3590 free_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq) 3591 { 3592 int rc; 3593 3594 rc = free_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl); 3595 if (rc == 0) 3596 bzero(ofld_rxq, sizeof(*ofld_rxq)); 3597 3598 return (rc); 3599 } 3600 #endif 3601 3602 #ifdef DEV_NETMAP 3603 static int 3604 alloc_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq, int intr_idx, 3605 int idx, struct sysctl_oid *oid) 3606 { 3607 int rc; 3608 struct sysctl_oid_list *children; 3609 struct sysctl_ctx_list *ctx; 3610 char name[16]; 3611 size_t len; 3612 struct adapter *sc = vi->pi->adapter; 3613 struct netmap_adapter *na = NA(vi->ifp); 3614 3615 MPASS(na != NULL); 3616 3617 len = vi->qsize_rxq * IQ_ESIZE; 3618 rc = alloc_ring(sc, len, &nm_rxq->iq_desc_tag, &nm_rxq->iq_desc_map, 3619 &nm_rxq->iq_ba, (void **)&nm_rxq->iq_desc); 3620 if (rc != 0) 3621 return (rc); 3622 3623 len = na->num_rx_desc * EQ_ESIZE + sc->params.sge.spg_len; 3624 rc = alloc_ring(sc, len, &nm_rxq->fl_desc_tag, &nm_rxq->fl_desc_map, 3625 &nm_rxq->fl_ba, (void **)&nm_rxq->fl_desc); 3626 if (rc != 0) 3627 return (rc); 3628 3629 nm_rxq->vi = vi; 3630 nm_rxq->nid = idx; 3631 nm_rxq->iq_cidx = 0; 3632 nm_rxq->iq_sidx = vi->qsize_rxq - sc->params.sge.spg_len / IQ_ESIZE; 3633 nm_rxq->iq_gen = F_RSPD_GEN; 3634 nm_rxq->fl_pidx = nm_rxq->fl_cidx = 0; 3635 nm_rxq->fl_sidx = na->num_rx_desc; 3636 nm_rxq->intr_idx = intr_idx; 3637 nm_rxq->iq_cntxt_id = INVALID_NM_RXQ_CNTXT_ID; 3638 3639 ctx = &vi->ctx; 3640 children = SYSCTL_CHILDREN(oid); 3641 3642 snprintf(name, sizeof(name), "%d", idx); 3643 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, name, CTLFLAG_RD, NULL, 3644 "rx queue"); 3645 children = SYSCTL_CHILDREN(oid); 3646 3647 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "abs_id", 3648 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_abs_id, 0, sysctl_uint16, 3649 "I", "absolute id of the queue"); 3650 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 3651 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cntxt_id, 0, sysctl_uint16, 3652 "I", "SGE context id of the queue"); 3653 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx", 3654 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cidx, 0, sysctl_uint16, "I", 3655 "consumer index"); 3656 3657 children = SYSCTL_CHILDREN(oid); 3658 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL, 3659 "freelist"); 3660 children = SYSCTL_CHILDREN(oid); 3661 3662 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 3663 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->fl_cntxt_id, 0, sysctl_uint16, 3664 "I", "SGE context id of the freelist"); 3665 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, 3666 &nm_rxq->fl_cidx, 0, "consumer index"); 3667 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, 3668 &nm_rxq->fl_pidx, 0, "producer index"); 3669 3670 return (rc); 3671 } 3672 3673 3674 static int 3675 free_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq) 3676 { 3677 struct adapter *sc = vi->pi->adapter; 3678 3679 if (vi->flags & VI_INIT_DONE) 3680 MPASS(nm_rxq->iq_cntxt_id == INVALID_NM_RXQ_CNTXT_ID); 3681 else 3682 MPASS(nm_rxq->iq_cntxt_id == 0); 3683 3684 free_ring(sc, nm_rxq->iq_desc_tag, nm_rxq->iq_desc_map, nm_rxq->iq_ba, 3685 nm_rxq->iq_desc); 3686 free_ring(sc, nm_rxq->fl_desc_tag, nm_rxq->fl_desc_map, nm_rxq->fl_ba, 3687 nm_rxq->fl_desc); 3688 3689 return (0); 3690 } 3691 3692 static int 3693 alloc_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq, int iqidx, int idx, 3694 struct sysctl_oid *oid) 3695 { 3696 int rc; 3697 size_t len; 3698 struct port_info *pi = vi->pi; 3699 struct adapter *sc = pi->adapter; 3700 struct netmap_adapter *na = NA(vi->ifp); 3701 char name[16]; 3702 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3703 3704 len = na->num_tx_desc * EQ_ESIZE + sc->params.sge.spg_len; 3705 rc = alloc_ring(sc, len, &nm_txq->desc_tag, &nm_txq->desc_map, 3706 &nm_txq->ba, (void **)&nm_txq->desc); 3707 if (rc) 3708 return (rc); 3709 3710 nm_txq->pidx = nm_txq->cidx = 0; 3711 nm_txq->sidx = na->num_tx_desc; 3712 nm_txq->nid = idx; 3713 nm_txq->iqidx = iqidx; 3714 nm_txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) | 3715 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(sc->pf) | 3716 V_TXPKT_VF(vi->vin) | V_TXPKT_VF_VLD(vi->vfvld)); 3717 nm_txq->cntxt_id = INVALID_NM_TXQ_CNTXT_ID; 3718 3719 snprintf(name, sizeof(name), "%d", idx); 3720 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 3721 NULL, "netmap tx queue"); 3722 children = SYSCTL_CHILDREN(oid); 3723 3724 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 3725 &nm_txq->cntxt_id, 0, "SGE context id of the queue"); 3726 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx", 3727 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->cidx, 0, sysctl_uint16, "I", 3728 "consumer index"); 3729 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "pidx", 3730 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->pidx, 0, sysctl_uint16, "I", 3731 "producer index"); 3732 3733 return (rc); 3734 } 3735 3736 static int 3737 free_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq) 3738 { 3739 struct adapter *sc = vi->pi->adapter; 3740 3741 if (vi->flags & VI_INIT_DONE) 3742 MPASS(nm_txq->cntxt_id == INVALID_NM_TXQ_CNTXT_ID); 3743 else 3744 MPASS(nm_txq->cntxt_id == 0); 3745 3746 free_ring(sc, nm_txq->desc_tag, nm_txq->desc_map, nm_txq->ba, 3747 nm_txq->desc); 3748 3749 return (0); 3750 } 3751 #endif 3752 3753 /* 3754 * Returns a reasonable automatic cidx flush threshold for a given queue size. 3755 */ 3756 static u_int 3757 qsize_to_fthresh(int qsize) 3758 { 3759 u_int fthresh; 3760 3761 while (!powerof2(qsize)) 3762 qsize++; 3763 fthresh = ilog2(qsize); 3764 if (fthresh > X_CIDXFLUSHTHRESH_128) 3765 fthresh = X_CIDXFLUSHTHRESH_128; 3766 3767 return (fthresh); 3768 } 3769 3770 static int 3771 ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq) 3772 { 3773 int rc, cntxt_id; 3774 struct fw_eq_ctrl_cmd c; 3775 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 3776 3777 bzero(&c, sizeof(c)); 3778 3779 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | F_FW_CMD_REQUEST | 3780 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_CTRL_CMD_PFN(sc->pf) | 3781 V_FW_EQ_CTRL_CMD_VFN(0)); 3782 c.alloc_to_len16 = htobe32(F_FW_EQ_CTRL_CMD_ALLOC | 3783 F_FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c)); 3784 c.cmpliqid_eqid = htonl(V_FW_EQ_CTRL_CMD_CMPLIQID(eq->iqid)); 3785 c.physeqid_pkd = htobe32(0); 3786 c.fetchszm_to_iqid = 3787 htobe32(V_FW_EQ_CTRL_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 3788 V_FW_EQ_CTRL_CMD_PCIECHN(eq->tx_chan) | 3789 F_FW_EQ_CTRL_CMD_FETCHRO | V_FW_EQ_CTRL_CMD_IQID(eq->iqid)); 3790 c.dcaen_to_eqsize = 3791 htobe32(V_FW_EQ_CTRL_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 3792 V_FW_EQ_CTRL_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 3793 V_FW_EQ_CTRL_CMD_CIDXFTHRESH(qsize_to_fthresh(qsize)) | 3794 V_FW_EQ_CTRL_CMD_EQSIZE(qsize)); 3795 c.eqaddr = htobe64(eq->ba); 3796 3797 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3798 if (rc != 0) { 3799 device_printf(sc->dev, 3800 "failed to create control queue %d: %d\n", eq->tx_chan, rc); 3801 return (rc); 3802 } 3803 eq->flags |= EQ_ALLOCATED; 3804 3805 eq->cntxt_id = G_FW_EQ_CTRL_CMD_EQID(be32toh(c.cmpliqid_eqid)); 3806 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 3807 if (cntxt_id >= sc->sge.neq) 3808 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 3809 cntxt_id, sc->sge.neq - 1); 3810 sc->sge.eqmap[cntxt_id] = eq; 3811 3812 return (rc); 3813 } 3814 3815 static int 3816 eth_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 3817 { 3818 int rc, cntxt_id; 3819 struct fw_eq_eth_cmd c; 3820 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 3821 3822 bzero(&c, sizeof(c)); 3823 3824 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST | 3825 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) | 3826 V_FW_EQ_ETH_CMD_VFN(0)); 3827 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC | 3828 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c)); 3829 c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE | 3830 F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(vi->viid)); 3831 c.fetchszm_to_iqid = 3832 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) | 3833 V_FW_EQ_ETH_CMD_PCIECHN(eq->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO | 3834 V_FW_EQ_ETH_CMD_IQID(eq->iqid)); 3835 c.dcaen_to_eqsize = htobe32(V_FW_EQ_ETH_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 3836 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 3837 V_FW_EQ_ETH_CMD_EQSIZE(qsize)); 3838 c.eqaddr = htobe64(eq->ba); 3839 3840 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3841 if (rc != 0) { 3842 device_printf(vi->dev, 3843 "failed to create Ethernet egress queue: %d\n", rc); 3844 return (rc); 3845 } 3846 eq->flags |= EQ_ALLOCATED; 3847 3848 eq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd)); 3849 eq->abs_id = G_FW_EQ_ETH_CMD_PHYSEQID(be32toh(c.physeqid_pkd)); 3850 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 3851 if (cntxt_id >= sc->sge.neq) 3852 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 3853 cntxt_id, sc->sge.neq - 1); 3854 sc->sge.eqmap[cntxt_id] = eq; 3855 3856 return (rc); 3857 } 3858 3859 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 3860 static int 3861 ofld_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 3862 { 3863 int rc, cntxt_id; 3864 struct fw_eq_ofld_cmd c; 3865 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 3866 3867 bzero(&c, sizeof(c)); 3868 3869 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | F_FW_CMD_REQUEST | 3870 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_OFLD_CMD_PFN(sc->pf) | 3871 V_FW_EQ_OFLD_CMD_VFN(0)); 3872 c.alloc_to_len16 = htonl(F_FW_EQ_OFLD_CMD_ALLOC | 3873 F_FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c)); 3874 c.fetchszm_to_iqid = 3875 htonl(V_FW_EQ_OFLD_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 3876 V_FW_EQ_OFLD_CMD_PCIECHN(eq->tx_chan) | 3877 F_FW_EQ_OFLD_CMD_FETCHRO | V_FW_EQ_OFLD_CMD_IQID(eq->iqid)); 3878 c.dcaen_to_eqsize = 3879 htobe32(V_FW_EQ_OFLD_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 3880 V_FW_EQ_OFLD_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 3881 V_FW_EQ_OFLD_CMD_CIDXFTHRESH(qsize_to_fthresh(qsize)) | 3882 V_FW_EQ_OFLD_CMD_EQSIZE(qsize)); 3883 c.eqaddr = htobe64(eq->ba); 3884 3885 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3886 if (rc != 0) { 3887 device_printf(vi->dev, 3888 "failed to create egress queue for TCP offload: %d\n", rc); 3889 return (rc); 3890 } 3891 eq->flags |= EQ_ALLOCATED; 3892 3893 eq->cntxt_id = G_FW_EQ_OFLD_CMD_EQID(be32toh(c.eqid_pkd)); 3894 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 3895 if (cntxt_id >= sc->sge.neq) 3896 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 3897 cntxt_id, sc->sge.neq - 1); 3898 sc->sge.eqmap[cntxt_id] = eq; 3899 3900 return (rc); 3901 } 3902 #endif 3903 3904 static int 3905 alloc_eq(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 3906 { 3907 int rc, qsize; 3908 size_t len; 3909 3910 mtx_init(&eq->eq_lock, eq->lockname, NULL, MTX_DEF); 3911 3912 qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 3913 len = qsize * EQ_ESIZE; 3914 rc = alloc_ring(sc, len, &eq->desc_tag, &eq->desc_map, 3915 &eq->ba, (void **)&eq->desc); 3916 if (rc) 3917 return (rc); 3918 3919 eq->pidx = eq->cidx = eq->dbidx = 0; 3920 /* Note that equeqidx is not used with sge_wrq (OFLD/CTRL) queues. */ 3921 eq->equeqidx = 0; 3922 eq->doorbells = sc->doorbells; 3923 3924 switch (eq->flags & EQ_TYPEMASK) { 3925 case EQ_CTRL: 3926 rc = ctrl_eq_alloc(sc, eq); 3927 break; 3928 3929 case EQ_ETH: 3930 rc = eth_eq_alloc(sc, vi, eq); 3931 break; 3932 3933 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 3934 case EQ_OFLD: 3935 rc = ofld_eq_alloc(sc, vi, eq); 3936 break; 3937 #endif 3938 3939 default: 3940 panic("%s: invalid eq type %d.", __func__, 3941 eq->flags & EQ_TYPEMASK); 3942 } 3943 if (rc != 0) { 3944 device_printf(sc->dev, 3945 "failed to allocate egress queue(%d): %d\n", 3946 eq->flags & EQ_TYPEMASK, rc); 3947 } 3948 3949 if (isset(&eq->doorbells, DOORBELL_UDB) || 3950 isset(&eq->doorbells, DOORBELL_UDBWC) || 3951 isset(&eq->doorbells, DOORBELL_WCWR)) { 3952 uint32_t s_qpp = sc->params.sge.eq_s_qpp; 3953 uint32_t mask = (1 << s_qpp) - 1; 3954 volatile uint8_t *udb; 3955 3956 udb = sc->udbs_base + UDBS_DB_OFFSET; 3957 udb += (eq->cntxt_id >> s_qpp) << PAGE_SHIFT; /* pg offset */ 3958 eq->udb_qid = eq->cntxt_id & mask; /* id in page */ 3959 if (eq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE) 3960 clrbit(&eq->doorbells, DOORBELL_WCWR); 3961 else { 3962 udb += eq->udb_qid << UDBS_SEG_SHIFT; /* seg offset */ 3963 eq->udb_qid = 0; 3964 } 3965 eq->udb = (volatile void *)udb; 3966 } 3967 3968 return (rc); 3969 } 3970 3971 static int 3972 free_eq(struct adapter *sc, struct sge_eq *eq) 3973 { 3974 int rc; 3975 3976 if (eq->flags & EQ_ALLOCATED) { 3977 switch (eq->flags & EQ_TYPEMASK) { 3978 case EQ_CTRL: 3979 rc = -t4_ctrl_eq_free(sc, sc->mbox, sc->pf, 0, 3980 eq->cntxt_id); 3981 break; 3982 3983 case EQ_ETH: 3984 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0, 3985 eq->cntxt_id); 3986 break; 3987 3988 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 3989 case EQ_OFLD: 3990 rc = -t4_ofld_eq_free(sc, sc->mbox, sc->pf, 0, 3991 eq->cntxt_id); 3992 break; 3993 #endif 3994 3995 default: 3996 panic("%s: invalid eq type %d.", __func__, 3997 eq->flags & EQ_TYPEMASK); 3998 } 3999 if (rc != 0) { 4000 device_printf(sc->dev, 4001 "failed to free egress queue (%d): %d\n", 4002 eq->flags & EQ_TYPEMASK, rc); 4003 return (rc); 4004 } 4005 eq->flags &= ~EQ_ALLOCATED; 4006 } 4007 4008 free_ring(sc, eq->desc_tag, eq->desc_map, eq->ba, eq->desc); 4009 4010 if (mtx_initialized(&eq->eq_lock)) 4011 mtx_destroy(&eq->eq_lock); 4012 4013 bzero(eq, sizeof(*eq)); 4014 return (0); 4015 } 4016 4017 static int 4018 alloc_wrq(struct adapter *sc, struct vi_info *vi, struct sge_wrq *wrq, 4019 struct sysctl_oid *oid) 4020 { 4021 int rc; 4022 struct sysctl_ctx_list *ctx = vi ? &vi->ctx : &sc->ctx; 4023 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 4024 4025 rc = alloc_eq(sc, vi, &wrq->eq); 4026 if (rc) 4027 return (rc); 4028 4029 wrq->adapter = sc; 4030 TASK_INIT(&wrq->wrq_tx_task, 0, wrq_tx_drain, wrq); 4031 TAILQ_INIT(&wrq->incomplete_wrs); 4032 STAILQ_INIT(&wrq->wr_list); 4033 wrq->nwr_pending = 0; 4034 wrq->ndesc_needed = 0; 4035 4036 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, 4037 &wrq->eq.ba, "bus address of descriptor ring"); 4038 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 4039 wrq->eq.sidx * EQ_ESIZE + sc->params.sge.spg_len, 4040 "desc ring size in bytes"); 4041 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 4042 &wrq->eq.cntxt_id, 0, "SGE context id of the queue"); 4043 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx", 4044 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.cidx, 0, sysctl_uint16, "I", 4045 "consumer index"); 4046 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pidx", 4047 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.pidx, 0, sysctl_uint16, "I", 4048 "producer index"); 4049 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL, 4050 wrq->eq.sidx, "status page index"); 4051 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_direct", CTLFLAG_RD, 4052 &wrq->tx_wrs_direct, "# of work requests (direct)"); 4053 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_copied", CTLFLAG_RD, 4054 &wrq->tx_wrs_copied, "# of work requests (copied)"); 4055 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_sspace", CTLFLAG_RD, 4056 &wrq->tx_wrs_ss, "# of work requests (copied from scratch space)"); 4057 4058 return (rc); 4059 } 4060 4061 static int 4062 free_wrq(struct adapter *sc, struct sge_wrq *wrq) 4063 { 4064 int rc; 4065 4066 rc = free_eq(sc, &wrq->eq); 4067 if (rc) 4068 return (rc); 4069 4070 bzero(wrq, sizeof(*wrq)); 4071 return (0); 4072 } 4073 4074 static int 4075 alloc_txq(struct vi_info *vi, struct sge_txq *txq, int idx, 4076 struct sysctl_oid *oid) 4077 { 4078 int rc; 4079 struct port_info *pi = vi->pi; 4080 struct adapter *sc = pi->adapter; 4081 struct sge_eq *eq = &txq->eq; 4082 char name[16]; 4083 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 4084 4085 rc = mp_ring_alloc(&txq->r, eq->sidx, txq, eth_tx, can_resume_eth_tx, 4086 M_CXGBE, M_WAITOK); 4087 if (rc != 0) { 4088 device_printf(sc->dev, "failed to allocate mp_ring: %d\n", rc); 4089 return (rc); 4090 } 4091 4092 rc = alloc_eq(sc, vi, eq); 4093 if (rc != 0) { 4094 mp_ring_free(txq->r); 4095 txq->r = NULL; 4096 return (rc); 4097 } 4098 4099 /* Can't fail after this point. */ 4100 4101 if (idx == 0) 4102 sc->sge.eq_base = eq->abs_id - eq->cntxt_id; 4103 else 4104 KASSERT(eq->cntxt_id + sc->sge.eq_base == eq->abs_id, 4105 ("eq_base mismatch")); 4106 KASSERT(sc->sge.eq_base == 0 || sc->flags & IS_VF, 4107 ("PF with non-zero eq_base")); 4108 4109 TASK_INIT(&txq->tx_reclaim_task, 0, tx_reclaim, eq); 4110 txq->ifp = vi->ifp; 4111 txq->gl = sglist_alloc(TX_SGL_SEGS, M_WAITOK); 4112 if (sc->flags & IS_VF) 4113 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) | 4114 V_TXPKT_INTF(pi->tx_chan)); 4115 else 4116 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) | 4117 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(sc->pf) | 4118 V_TXPKT_VF(vi->vin) | V_TXPKT_VF_VLD(vi->vfvld)); 4119 txq->tc_idx = -1; 4120 txq->sdesc = malloc(eq->sidx * sizeof(struct tx_sdesc), M_CXGBE, 4121 M_ZERO | M_WAITOK); 4122 4123 snprintf(name, sizeof(name), "%d", idx); 4124 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 4125 NULL, "tx queue"); 4126 children = SYSCTL_CHILDREN(oid); 4127 4128 SYSCTL_ADD_UAUTO(&vi->ctx, children, OID_AUTO, "ba", CTLFLAG_RD, 4129 &eq->ba, "bus address of descriptor ring"); 4130 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 4131 eq->sidx * EQ_ESIZE + sc->params.sge.spg_len, 4132 "desc ring size in bytes"); 4133 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "abs_id", CTLFLAG_RD, 4134 &eq->abs_id, 0, "absolute id of the queue"); 4135 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 4136 &eq->cntxt_id, 0, "SGE context id of the queue"); 4137 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx", 4138 CTLTYPE_INT | CTLFLAG_RD, &eq->cidx, 0, sysctl_uint16, "I", 4139 "consumer index"); 4140 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "pidx", 4141 CTLTYPE_INT | CTLFLAG_RD, &eq->pidx, 0, sysctl_uint16, "I", 4142 "producer index"); 4143 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL, 4144 eq->sidx, "status page index"); 4145 4146 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "tc", 4147 CTLTYPE_INT | CTLFLAG_RW, vi, idx, sysctl_tc, "I", 4148 "traffic class (-1 means none)"); 4149 4150 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txcsum", CTLFLAG_RD, 4151 &txq->txcsum, "# of times hardware assisted with checksum"); 4152 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_insertion", 4153 CTLFLAG_RD, &txq->vlan_insertion, 4154 "# of times hardware inserted 802.1Q tag"); 4155 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "tso_wrs", CTLFLAG_RD, 4156 &txq->tso_wrs, "# of TSO work requests"); 4157 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "imm_wrs", CTLFLAG_RD, 4158 &txq->imm_wrs, "# of work requests with immediate data"); 4159 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "sgl_wrs", CTLFLAG_RD, 4160 &txq->sgl_wrs, "# of work requests with direct SGL"); 4161 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkt_wrs", CTLFLAG_RD, 4162 &txq->txpkt_wrs, "# of txpkt work requests (one pkt/WR)"); 4163 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_wrs", 4164 CTLFLAG_RD, &txq->txpkts0_wrs, 4165 "# of txpkts (type 0) work requests"); 4166 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_wrs", 4167 CTLFLAG_RD, &txq->txpkts1_wrs, 4168 "# of txpkts (type 1) work requests"); 4169 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_pkts", 4170 CTLFLAG_RD, &txq->txpkts0_pkts, 4171 "# of frames tx'd using type0 txpkts work requests"); 4172 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_pkts", 4173 CTLFLAG_RD, &txq->txpkts1_pkts, 4174 "# of frames tx'd using type1 txpkts work requests"); 4175 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "raw_wrs", CTLFLAG_RD, 4176 &txq->raw_wrs, "# of raw work requests (non-packets)"); 4177 4178 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_enqueues", 4179 CTLFLAG_RD, &txq->r->enqueues, 4180 "# of enqueues to the mp_ring for this queue"); 4181 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_drops", 4182 CTLFLAG_RD, &txq->r->drops, 4183 "# of drops in the mp_ring for this queue"); 4184 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_starts", 4185 CTLFLAG_RD, &txq->r->starts, 4186 "# of normal consumer starts in the mp_ring for this queue"); 4187 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_stalls", 4188 CTLFLAG_RD, &txq->r->stalls, 4189 "# of consumer stalls in the mp_ring for this queue"); 4190 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_restarts", 4191 CTLFLAG_RD, &txq->r->restarts, 4192 "# of consumer restarts in the mp_ring for this queue"); 4193 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_abdications", 4194 CTLFLAG_RD, &txq->r->abdications, 4195 "# of consumer abdications in the mp_ring for this queue"); 4196 4197 return (0); 4198 } 4199 4200 static int 4201 free_txq(struct vi_info *vi, struct sge_txq *txq) 4202 { 4203 int rc; 4204 struct adapter *sc = vi->pi->adapter; 4205 struct sge_eq *eq = &txq->eq; 4206 4207 rc = free_eq(sc, eq); 4208 if (rc) 4209 return (rc); 4210 4211 sglist_free(txq->gl); 4212 free(txq->sdesc, M_CXGBE); 4213 mp_ring_free(txq->r); 4214 4215 bzero(txq, sizeof(*txq)); 4216 return (0); 4217 } 4218 4219 static void 4220 oneseg_dma_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error) 4221 { 4222 bus_addr_t *ba = arg; 4223 4224 KASSERT(nseg == 1, 4225 ("%s meant for single segment mappings only.", __func__)); 4226 4227 *ba = error ? 0 : segs->ds_addr; 4228 } 4229 4230 static inline void 4231 ring_fl_db(struct adapter *sc, struct sge_fl *fl) 4232 { 4233 uint32_t n, v; 4234 4235 n = IDXDIFF(fl->pidx / 8, fl->dbidx, fl->sidx); 4236 MPASS(n > 0); 4237 4238 wmb(); 4239 v = fl->dbval | V_PIDX(n); 4240 if (fl->udb) 4241 *fl->udb = htole32(v); 4242 else 4243 t4_write_reg(sc, sc->sge_kdoorbell_reg, v); 4244 IDXINCR(fl->dbidx, n, fl->sidx); 4245 } 4246 4247 /* 4248 * Fills up the freelist by allocating up to 'n' buffers. Buffers that are 4249 * recycled do not count towards this allocation budget. 4250 * 4251 * Returns non-zero to indicate that this freelist should be added to the list 4252 * of starving freelists. 4253 */ 4254 static int 4255 refill_fl(struct adapter *sc, struct sge_fl *fl, int n) 4256 { 4257 __be64 *d; 4258 struct fl_sdesc *sd; 4259 uintptr_t pa; 4260 caddr_t cl; 4261 struct cluster_layout *cll; 4262 struct sw_zone_info *swz; 4263 struct cluster_metadata *clm; 4264 uint16_t max_pidx; 4265 uint16_t hw_cidx = fl->hw_cidx; /* stable snapshot */ 4266 4267 FL_LOCK_ASSERT_OWNED(fl); 4268 4269 /* 4270 * We always stop at the beginning of the hardware descriptor that's just 4271 * before the one with the hw cidx. This is to avoid hw pidx = hw cidx, 4272 * which would mean an empty freelist to the chip. 4273 */ 4274 max_pidx = __predict_false(hw_cidx == 0) ? fl->sidx - 1 : hw_cidx - 1; 4275 if (fl->pidx == max_pidx * 8) 4276 return (0); 4277 4278 d = &fl->desc[fl->pidx]; 4279 sd = &fl->sdesc[fl->pidx]; 4280 cll = &fl->cll_def; /* default layout */ 4281 swz = &sc->sge.sw_zone_info[cll->zidx]; 4282 4283 while (n > 0) { 4284 4285 if (sd->cl != NULL) { 4286 4287 if (sd->nmbuf == 0) { 4288 /* 4289 * Fast recycle without involving any atomics on 4290 * the cluster's metadata (if the cluster has 4291 * metadata). This happens when all frames 4292 * received in the cluster were small enough to 4293 * fit within a single mbuf each. 4294 */ 4295 fl->cl_fast_recycled++; 4296 #ifdef INVARIANTS 4297 clm = cl_metadata(sc, fl, &sd->cll, sd->cl); 4298 if (clm != NULL) 4299 MPASS(clm->refcount == 1); 4300 #endif 4301 goto recycled_fast; 4302 } 4303 4304 /* 4305 * Cluster is guaranteed to have metadata. Clusters 4306 * without metadata always take the fast recycle path 4307 * when they're recycled. 4308 */ 4309 clm = cl_metadata(sc, fl, &sd->cll, sd->cl); 4310 MPASS(clm != NULL); 4311 4312 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) { 4313 fl->cl_recycled++; 4314 counter_u64_add(extfree_rels, 1); 4315 goto recycled; 4316 } 4317 sd->cl = NULL; /* gave up my reference */ 4318 } 4319 MPASS(sd->cl == NULL); 4320 alloc: 4321 cl = uma_zalloc(swz->zone, M_NOWAIT); 4322 if (__predict_false(cl == NULL)) { 4323 if (cll == &fl->cll_alt || fl->cll_alt.zidx == -1 || 4324 fl->cll_def.zidx == fl->cll_alt.zidx) 4325 break; 4326 4327 /* fall back to the safe zone */ 4328 cll = &fl->cll_alt; 4329 swz = &sc->sge.sw_zone_info[cll->zidx]; 4330 goto alloc; 4331 } 4332 fl->cl_allocated++; 4333 n--; 4334 4335 pa = pmap_kextract((vm_offset_t)cl); 4336 pa += cll->region1; 4337 sd->cl = cl; 4338 sd->cll = *cll; 4339 *d = htobe64(pa | cll->hwidx); 4340 clm = cl_metadata(sc, fl, cll, cl); 4341 if (clm != NULL) { 4342 recycled: 4343 #ifdef INVARIANTS 4344 clm->sd = sd; 4345 #endif 4346 clm->refcount = 1; 4347 } 4348 sd->nmbuf = 0; 4349 recycled_fast: 4350 d++; 4351 sd++; 4352 if (__predict_false(++fl->pidx % 8 == 0)) { 4353 uint16_t pidx = fl->pidx / 8; 4354 4355 if (__predict_false(pidx == fl->sidx)) { 4356 fl->pidx = 0; 4357 pidx = 0; 4358 sd = fl->sdesc; 4359 d = fl->desc; 4360 } 4361 if (pidx == max_pidx) 4362 break; 4363 4364 if (IDXDIFF(pidx, fl->dbidx, fl->sidx) >= 4) 4365 ring_fl_db(sc, fl); 4366 } 4367 } 4368 4369 if (fl->pidx / 8 != fl->dbidx) 4370 ring_fl_db(sc, fl); 4371 4372 return (FL_RUNNING_LOW(fl) && !(fl->flags & FL_STARVING)); 4373 } 4374 4375 /* 4376 * Attempt to refill all starving freelists. 4377 */ 4378 static void 4379 refill_sfl(void *arg) 4380 { 4381 struct adapter *sc = arg; 4382 struct sge_fl *fl, *fl_temp; 4383 4384 mtx_assert(&sc->sfl_lock, MA_OWNED); 4385 TAILQ_FOREACH_SAFE(fl, &sc->sfl, link, fl_temp) { 4386 FL_LOCK(fl); 4387 refill_fl(sc, fl, 64); 4388 if (FL_NOT_RUNNING_LOW(fl) || fl->flags & FL_DOOMED) { 4389 TAILQ_REMOVE(&sc->sfl, fl, link); 4390 fl->flags &= ~FL_STARVING; 4391 } 4392 FL_UNLOCK(fl); 4393 } 4394 4395 if (!TAILQ_EMPTY(&sc->sfl)) 4396 callout_schedule(&sc->sfl_callout, hz / 5); 4397 } 4398 4399 static int 4400 alloc_fl_sdesc(struct sge_fl *fl) 4401 { 4402 4403 fl->sdesc = malloc(fl->sidx * 8 * sizeof(struct fl_sdesc), M_CXGBE, 4404 M_ZERO | M_WAITOK); 4405 4406 return (0); 4407 } 4408 4409 static void 4410 free_fl_sdesc(struct adapter *sc, struct sge_fl *fl) 4411 { 4412 struct fl_sdesc *sd; 4413 struct cluster_metadata *clm; 4414 struct cluster_layout *cll; 4415 int i; 4416 4417 sd = fl->sdesc; 4418 for (i = 0; i < fl->sidx * 8; i++, sd++) { 4419 if (sd->cl == NULL) 4420 continue; 4421 4422 cll = &sd->cll; 4423 clm = cl_metadata(sc, fl, cll, sd->cl); 4424 if (sd->nmbuf == 0) 4425 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl); 4426 else if (clm && atomic_fetchadd_int(&clm->refcount, -1) == 1) { 4427 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl); 4428 counter_u64_add(extfree_rels, 1); 4429 } 4430 sd->cl = NULL; 4431 } 4432 4433 free(fl->sdesc, M_CXGBE); 4434 fl->sdesc = NULL; 4435 } 4436 4437 static inline void 4438 get_pkt_gl(struct mbuf *m, struct sglist *gl) 4439 { 4440 int rc; 4441 4442 M_ASSERTPKTHDR(m); 4443 4444 sglist_reset(gl); 4445 rc = sglist_append_mbuf(gl, m); 4446 if (__predict_false(rc != 0)) { 4447 panic("%s: mbuf %p (%d segs) was vetted earlier but now fails " 4448 "with %d.", __func__, m, mbuf_nsegs(m), rc); 4449 } 4450 4451 KASSERT(gl->sg_nseg == mbuf_nsegs(m), 4452 ("%s: nsegs changed for mbuf %p from %d to %d", __func__, m, 4453 mbuf_nsegs(m), gl->sg_nseg)); 4454 KASSERT(gl->sg_nseg > 0 && 4455 gl->sg_nseg <= (needs_tso(m) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS), 4456 ("%s: %d segments, should have been 1 <= nsegs <= %d", __func__, 4457 gl->sg_nseg, needs_tso(m) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS)); 4458 } 4459 4460 /* 4461 * len16 for a txpkt WR with a GL. Includes the firmware work request header. 4462 */ 4463 static inline u_int 4464 txpkt_len16(u_int nsegs, u_int tso) 4465 { 4466 u_int n; 4467 4468 MPASS(nsegs > 0); 4469 4470 nsegs--; /* first segment is part of ulptx_sgl */ 4471 n = sizeof(struct fw_eth_tx_pkt_wr) + sizeof(struct cpl_tx_pkt_core) + 4472 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 4473 if (tso) 4474 n += sizeof(struct cpl_tx_pkt_lso_core); 4475 4476 return (howmany(n, 16)); 4477 } 4478 4479 /* 4480 * len16 for a txpkt_vm WR with a GL. Includes the firmware work 4481 * request header. 4482 */ 4483 static inline u_int 4484 txpkt_vm_len16(u_int nsegs, u_int tso) 4485 { 4486 u_int n; 4487 4488 MPASS(nsegs > 0); 4489 4490 nsegs--; /* first segment is part of ulptx_sgl */ 4491 n = sizeof(struct fw_eth_tx_pkt_vm_wr) + 4492 sizeof(struct cpl_tx_pkt_core) + 4493 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 4494 if (tso) 4495 n += sizeof(struct cpl_tx_pkt_lso_core); 4496 4497 return (howmany(n, 16)); 4498 } 4499 4500 /* 4501 * len16 for a txpkts type 0 WR with a GL. Does not include the firmware work 4502 * request header. 4503 */ 4504 static inline u_int 4505 txpkts0_len16(u_int nsegs) 4506 { 4507 u_int n; 4508 4509 MPASS(nsegs > 0); 4510 4511 nsegs--; /* first segment is part of ulptx_sgl */ 4512 n = sizeof(struct ulp_txpkt) + sizeof(struct ulptx_idata) + 4513 sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl) + 4514 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 4515 4516 return (howmany(n, 16)); 4517 } 4518 4519 /* 4520 * len16 for a txpkts type 1 WR with a GL. Does not include the firmware work 4521 * request header. 4522 */ 4523 static inline u_int 4524 txpkts1_len16(void) 4525 { 4526 u_int n; 4527 4528 n = sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl); 4529 4530 return (howmany(n, 16)); 4531 } 4532 4533 static inline u_int 4534 imm_payload(u_int ndesc) 4535 { 4536 u_int n; 4537 4538 n = ndesc * EQ_ESIZE - sizeof(struct fw_eth_tx_pkt_wr) - 4539 sizeof(struct cpl_tx_pkt_core); 4540 4541 return (n); 4542 } 4543 4544 /* 4545 * Write a VM txpkt WR for this packet to the hardware descriptors, update the 4546 * software descriptor, and advance the pidx. It is guaranteed that enough 4547 * descriptors are available. 4548 * 4549 * The return value is the # of hardware descriptors used. 4550 */ 4551 static u_int 4552 write_txpkt_vm_wr(struct adapter *sc, struct sge_txq *txq, 4553 struct fw_eth_tx_pkt_vm_wr *wr, struct mbuf *m0, u_int available) 4554 { 4555 struct sge_eq *eq = &txq->eq; 4556 struct tx_sdesc *txsd; 4557 struct cpl_tx_pkt_core *cpl; 4558 uint32_t ctrl; /* used in many unrelated places */ 4559 uint64_t ctrl1; 4560 int csum_type, len16, ndesc, pktlen, nsegs; 4561 caddr_t dst; 4562 4563 TXQ_LOCK_ASSERT_OWNED(txq); 4564 M_ASSERTPKTHDR(m0); 4565 MPASS(available > 0 && available < eq->sidx); 4566 4567 len16 = mbuf_len16(m0); 4568 nsegs = mbuf_nsegs(m0); 4569 pktlen = m0->m_pkthdr.len; 4570 ctrl = sizeof(struct cpl_tx_pkt_core); 4571 if (needs_tso(m0)) 4572 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 4573 ndesc = howmany(len16, EQ_ESIZE / 16); 4574 MPASS(ndesc <= available); 4575 4576 /* Firmware work request header */ 4577 MPASS(wr == (void *)&eq->desc[eq->pidx]); 4578 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_VM_WR) | 4579 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl)); 4580 4581 ctrl = V_FW_WR_LEN16(len16); 4582 wr->equiq_to_len16 = htobe32(ctrl); 4583 wr->r3[0] = 0; 4584 wr->r3[1] = 0; 4585 4586 /* 4587 * Copy over ethmacdst, ethmacsrc, ethtype, and vlantci. 4588 * vlantci is ignored unless the ethtype is 0x8100, so it's 4589 * simpler to always copy it rather than making it 4590 * conditional. Also, it seems that we do not have to set 4591 * vlantci or fake the ethtype when doing VLAN tag insertion. 4592 */ 4593 m_copydata(m0, 0, sizeof(struct ether_header) + 2, wr->ethmacdst); 4594 4595 csum_type = -1; 4596 if (needs_tso(m0)) { 4597 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1); 4598 4599 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 4600 m0->m_pkthdr.l4hlen > 0, 4601 ("%s: mbuf %p needs TSO but missing header lengths", 4602 __func__, m0)); 4603 4604 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE | 4605 F_LSO_LAST_SLICE | V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) 4606 | V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2); 4607 if (m0->m_pkthdr.l2hlen == sizeof(struct ether_vlan_header)) 4608 ctrl |= V_LSO_ETHHDR_LEN(1); 4609 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 4610 ctrl |= F_LSO_IPV6; 4611 4612 lso->lso_ctrl = htobe32(ctrl); 4613 lso->ipid_ofst = htobe16(0); 4614 lso->mss = htobe16(m0->m_pkthdr.tso_segsz); 4615 lso->seqno_offset = htobe32(0); 4616 lso->len = htobe32(pktlen); 4617 4618 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 4619 csum_type = TX_CSUM_TCPIP6; 4620 else 4621 csum_type = TX_CSUM_TCPIP; 4622 4623 cpl = (void *)(lso + 1); 4624 4625 txq->tso_wrs++; 4626 } else { 4627 if (m0->m_pkthdr.csum_flags & CSUM_IP_TCP) 4628 csum_type = TX_CSUM_TCPIP; 4629 else if (m0->m_pkthdr.csum_flags & CSUM_IP_UDP) 4630 csum_type = TX_CSUM_UDPIP; 4631 else if (m0->m_pkthdr.csum_flags & CSUM_IP6_TCP) 4632 csum_type = TX_CSUM_TCPIP6; 4633 else if (m0->m_pkthdr.csum_flags & CSUM_IP6_UDP) 4634 csum_type = TX_CSUM_UDPIP6; 4635 #if defined(INET) 4636 else if (m0->m_pkthdr.csum_flags & CSUM_IP) { 4637 /* 4638 * XXX: The firmware appears to stomp on the 4639 * fragment/flags field of the IP header when 4640 * using TX_CSUM_IP. Fall back to doing 4641 * software checksums. 4642 */ 4643 u_short *sump; 4644 struct mbuf *m; 4645 int offset; 4646 4647 m = m0; 4648 offset = 0; 4649 sump = m_advance(&m, &offset, m0->m_pkthdr.l2hlen + 4650 offsetof(struct ip, ip_sum)); 4651 *sump = in_cksum_skip(m0, m0->m_pkthdr.l2hlen + 4652 m0->m_pkthdr.l3hlen, m0->m_pkthdr.l2hlen); 4653 m0->m_pkthdr.csum_flags &= ~CSUM_IP; 4654 } 4655 #endif 4656 4657 cpl = (void *)(wr + 1); 4658 } 4659 4660 /* Checksum offload */ 4661 ctrl1 = 0; 4662 if (needs_l3_csum(m0) == 0) 4663 ctrl1 |= F_TXPKT_IPCSUM_DIS; 4664 if (csum_type >= 0) { 4665 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0, 4666 ("%s: mbuf %p needs checksum offload but missing header lengths", 4667 __func__, m0)); 4668 4669 if (chip_id(sc) <= CHELSIO_T5) { 4670 ctrl1 |= V_TXPKT_ETHHDR_LEN(m0->m_pkthdr.l2hlen - 4671 ETHER_HDR_LEN); 4672 } else { 4673 ctrl1 |= V_T6_TXPKT_ETHHDR_LEN(m0->m_pkthdr.l2hlen - 4674 ETHER_HDR_LEN); 4675 } 4676 ctrl1 |= V_TXPKT_IPHDR_LEN(m0->m_pkthdr.l3hlen); 4677 ctrl1 |= V_TXPKT_CSUM_TYPE(csum_type); 4678 } else 4679 ctrl1 |= F_TXPKT_L4CSUM_DIS; 4680 if (m0->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | 4681 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO)) 4682 txq->txcsum++; /* some hardware assistance provided */ 4683 4684 /* VLAN tag insertion */ 4685 if (needs_vlan_insertion(m0)) { 4686 ctrl1 |= F_TXPKT_VLAN_VLD | 4687 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 4688 txq->vlan_insertion++; 4689 } 4690 4691 /* CPL header */ 4692 cpl->ctrl0 = txq->cpl_ctrl0; 4693 cpl->pack = 0; 4694 cpl->len = htobe16(pktlen); 4695 cpl->ctrl1 = htobe64(ctrl1); 4696 4697 /* SGL */ 4698 dst = (void *)(cpl + 1); 4699 4700 /* 4701 * A packet using TSO will use up an entire descriptor for the 4702 * firmware work request header, LSO CPL, and TX_PKT_XT CPL. 4703 * If this descriptor is the last descriptor in the ring, wrap 4704 * around to the front of the ring explicitly for the start of 4705 * the sgl. 4706 */ 4707 if (dst == (void *)&eq->desc[eq->sidx]) { 4708 dst = (void *)&eq->desc[0]; 4709 write_gl_to_txd(txq, m0, &dst, 0); 4710 } else 4711 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx); 4712 txq->sgl_wrs++; 4713 4714 txq->txpkt_wrs++; 4715 4716 txsd = &txq->sdesc[eq->pidx]; 4717 txsd->m = m0; 4718 txsd->desc_used = ndesc; 4719 4720 return (ndesc); 4721 } 4722 4723 /* 4724 * Write a raw WR to the hardware descriptors, update the software 4725 * descriptor, and advance the pidx. It is guaranteed that enough 4726 * descriptors are available. 4727 * 4728 * The return value is the # of hardware descriptors used. 4729 */ 4730 static u_int 4731 write_raw_wr(struct sge_txq *txq, void *wr, struct mbuf *m0, u_int available) 4732 { 4733 struct sge_eq *eq = &txq->eq; 4734 struct tx_sdesc *txsd; 4735 struct mbuf *m; 4736 caddr_t dst; 4737 int len16, ndesc; 4738 4739 len16 = mbuf_len16(m0); 4740 ndesc = howmany(len16, EQ_ESIZE / 16); 4741 MPASS(ndesc <= available); 4742 4743 dst = wr; 4744 for (m = m0; m != NULL; m = m->m_next) 4745 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len); 4746 4747 txq->raw_wrs++; 4748 4749 txsd = &txq->sdesc[eq->pidx]; 4750 txsd->m = m0; 4751 txsd->desc_used = ndesc; 4752 4753 return (ndesc); 4754 } 4755 4756 /* 4757 * Write a txpkt WR for this packet to the hardware descriptors, update the 4758 * software descriptor, and advance the pidx. It is guaranteed that enough 4759 * descriptors are available. 4760 * 4761 * The return value is the # of hardware descriptors used. 4762 */ 4763 static u_int 4764 write_txpkt_wr(struct sge_txq *txq, struct fw_eth_tx_pkt_wr *wr, 4765 struct mbuf *m0, u_int available) 4766 { 4767 struct sge_eq *eq = &txq->eq; 4768 struct tx_sdesc *txsd; 4769 struct cpl_tx_pkt_core *cpl; 4770 uint32_t ctrl; /* used in many unrelated places */ 4771 uint64_t ctrl1; 4772 int len16, ndesc, pktlen, nsegs; 4773 caddr_t dst; 4774 4775 TXQ_LOCK_ASSERT_OWNED(txq); 4776 M_ASSERTPKTHDR(m0); 4777 MPASS(available > 0 && available < eq->sidx); 4778 4779 len16 = mbuf_len16(m0); 4780 nsegs = mbuf_nsegs(m0); 4781 pktlen = m0->m_pkthdr.len; 4782 ctrl = sizeof(struct cpl_tx_pkt_core); 4783 if (needs_tso(m0)) 4784 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 4785 else if (!(mbuf_cflags(m0) & MC_NOMAP) && pktlen <= imm_payload(2) && 4786 available >= 2) { 4787 /* Immediate data. Recalculate len16 and set nsegs to 0. */ 4788 ctrl += pktlen; 4789 len16 = howmany(sizeof(struct fw_eth_tx_pkt_wr) + 4790 sizeof(struct cpl_tx_pkt_core) + pktlen, 16); 4791 nsegs = 0; 4792 } 4793 ndesc = howmany(len16, EQ_ESIZE / 16); 4794 MPASS(ndesc <= available); 4795 4796 /* Firmware work request header */ 4797 MPASS(wr == (void *)&eq->desc[eq->pidx]); 4798 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_WR) | 4799 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl)); 4800 4801 ctrl = V_FW_WR_LEN16(len16); 4802 wr->equiq_to_len16 = htobe32(ctrl); 4803 wr->r3 = 0; 4804 4805 if (needs_tso(m0)) { 4806 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1); 4807 4808 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 4809 m0->m_pkthdr.l4hlen > 0, 4810 ("%s: mbuf %p needs TSO but missing header lengths", 4811 __func__, m0)); 4812 4813 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE | 4814 F_LSO_LAST_SLICE | V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) 4815 | V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2); 4816 if (m0->m_pkthdr.l2hlen == sizeof(struct ether_vlan_header)) 4817 ctrl |= V_LSO_ETHHDR_LEN(1); 4818 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 4819 ctrl |= F_LSO_IPV6; 4820 4821 lso->lso_ctrl = htobe32(ctrl); 4822 lso->ipid_ofst = htobe16(0); 4823 lso->mss = htobe16(m0->m_pkthdr.tso_segsz); 4824 lso->seqno_offset = htobe32(0); 4825 lso->len = htobe32(pktlen); 4826 4827 cpl = (void *)(lso + 1); 4828 4829 txq->tso_wrs++; 4830 } else 4831 cpl = (void *)(wr + 1); 4832 4833 /* Checksum offload */ 4834 ctrl1 = 0; 4835 if (needs_l3_csum(m0) == 0) 4836 ctrl1 |= F_TXPKT_IPCSUM_DIS; 4837 if (needs_l4_csum(m0) == 0) 4838 ctrl1 |= F_TXPKT_L4CSUM_DIS; 4839 if (m0->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | 4840 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO)) 4841 txq->txcsum++; /* some hardware assistance provided */ 4842 4843 /* VLAN tag insertion */ 4844 if (needs_vlan_insertion(m0)) { 4845 ctrl1 |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 4846 txq->vlan_insertion++; 4847 } 4848 4849 /* CPL header */ 4850 cpl->ctrl0 = txq->cpl_ctrl0; 4851 cpl->pack = 0; 4852 cpl->len = htobe16(pktlen); 4853 cpl->ctrl1 = htobe64(ctrl1); 4854 4855 /* SGL */ 4856 dst = (void *)(cpl + 1); 4857 if (nsegs > 0) { 4858 4859 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx); 4860 txq->sgl_wrs++; 4861 } else { 4862 struct mbuf *m; 4863 4864 for (m = m0; m != NULL; m = m->m_next) { 4865 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len); 4866 #ifdef INVARIANTS 4867 pktlen -= m->m_len; 4868 #endif 4869 } 4870 #ifdef INVARIANTS 4871 KASSERT(pktlen == 0, ("%s: %d bytes left.", __func__, pktlen)); 4872 #endif 4873 txq->imm_wrs++; 4874 } 4875 4876 txq->txpkt_wrs++; 4877 4878 txsd = &txq->sdesc[eq->pidx]; 4879 txsd->m = m0; 4880 txsd->desc_used = ndesc; 4881 4882 return (ndesc); 4883 } 4884 4885 static int 4886 try_txpkts(struct mbuf *m, struct mbuf *n, struct txpkts *txp, u_int available) 4887 { 4888 u_int needed, nsegs1, nsegs2, l1, l2; 4889 4890 if (cannot_use_txpkts(m) || cannot_use_txpkts(n)) 4891 return (1); 4892 4893 nsegs1 = mbuf_nsegs(m); 4894 nsegs2 = mbuf_nsegs(n); 4895 if (nsegs1 + nsegs2 == 2) { 4896 txp->wr_type = 1; 4897 l1 = l2 = txpkts1_len16(); 4898 } else { 4899 txp->wr_type = 0; 4900 l1 = txpkts0_len16(nsegs1); 4901 l2 = txpkts0_len16(nsegs2); 4902 } 4903 txp->len16 = howmany(sizeof(struct fw_eth_tx_pkts_wr), 16) + l1 + l2; 4904 needed = howmany(txp->len16, EQ_ESIZE / 16); 4905 if (needed > SGE_MAX_WR_NDESC || needed > available) 4906 return (1); 4907 4908 txp->plen = m->m_pkthdr.len + n->m_pkthdr.len; 4909 if (txp->plen > 65535) 4910 return (1); 4911 4912 txp->npkt = 2; 4913 set_mbuf_len16(m, l1); 4914 set_mbuf_len16(n, l2); 4915 4916 return (0); 4917 } 4918 4919 static int 4920 add_to_txpkts(struct mbuf *m, struct txpkts *txp, u_int available) 4921 { 4922 u_int plen, len16, needed, nsegs; 4923 4924 MPASS(txp->wr_type == 0 || txp->wr_type == 1); 4925 4926 if (cannot_use_txpkts(m)) 4927 return (1); 4928 4929 nsegs = mbuf_nsegs(m); 4930 if (txp->wr_type == 1 && nsegs != 1) 4931 return (1); 4932 4933 plen = txp->plen + m->m_pkthdr.len; 4934 if (plen > 65535) 4935 return (1); 4936 4937 if (txp->wr_type == 0) 4938 len16 = txpkts0_len16(nsegs); 4939 else 4940 len16 = txpkts1_len16(); 4941 needed = howmany(txp->len16 + len16, EQ_ESIZE / 16); 4942 if (needed > SGE_MAX_WR_NDESC || needed > available) 4943 return (1); 4944 4945 txp->npkt++; 4946 txp->plen = plen; 4947 txp->len16 += len16; 4948 set_mbuf_len16(m, len16); 4949 4950 return (0); 4951 } 4952 4953 /* 4954 * Write a txpkts WR for the packets in txp to the hardware descriptors, update 4955 * the software descriptor, and advance the pidx. It is guaranteed that enough 4956 * descriptors are available. 4957 * 4958 * The return value is the # of hardware descriptors used. 4959 */ 4960 static u_int 4961 write_txpkts_wr(struct sge_txq *txq, struct fw_eth_tx_pkts_wr *wr, 4962 struct mbuf *m0, const struct txpkts *txp, u_int available) 4963 { 4964 struct sge_eq *eq = &txq->eq; 4965 struct tx_sdesc *txsd; 4966 struct cpl_tx_pkt_core *cpl; 4967 uint32_t ctrl; 4968 uint64_t ctrl1; 4969 int ndesc, checkwrap; 4970 struct mbuf *m; 4971 void *flitp; 4972 4973 TXQ_LOCK_ASSERT_OWNED(txq); 4974 MPASS(txp->npkt > 0); 4975 MPASS(txp->plen < 65536); 4976 MPASS(m0 != NULL); 4977 MPASS(m0->m_nextpkt != NULL); 4978 MPASS(txp->len16 <= howmany(SGE_MAX_WR_LEN, 16)); 4979 MPASS(available > 0 && available < eq->sidx); 4980 4981 ndesc = howmany(txp->len16, EQ_ESIZE / 16); 4982 MPASS(ndesc <= available); 4983 4984 MPASS(wr == (void *)&eq->desc[eq->pidx]); 4985 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR)); 4986 ctrl = V_FW_WR_LEN16(txp->len16); 4987 wr->equiq_to_len16 = htobe32(ctrl); 4988 wr->plen = htobe16(txp->plen); 4989 wr->npkt = txp->npkt; 4990 wr->r3 = 0; 4991 wr->type = txp->wr_type; 4992 flitp = wr + 1; 4993 4994 /* 4995 * At this point we are 16B into a hardware descriptor. If checkwrap is 4996 * set then we know the WR is going to wrap around somewhere. We'll 4997 * check for that at appropriate points. 4998 */ 4999 checkwrap = eq->sidx - ndesc < eq->pidx; 5000 for (m = m0; m != NULL; m = m->m_nextpkt) { 5001 if (txp->wr_type == 0) { 5002 struct ulp_txpkt *ulpmc; 5003 struct ulptx_idata *ulpsc; 5004 5005 /* ULP master command */ 5006 ulpmc = flitp; 5007 ulpmc->cmd_dest = htobe32(V_ULPTX_CMD(ULP_TX_PKT) | 5008 V_ULP_TXPKT_DEST(0) | V_ULP_TXPKT_FID(eq->iqid)); 5009 ulpmc->len = htobe32(mbuf_len16(m)); 5010 5011 /* ULP subcommand */ 5012 ulpsc = (void *)(ulpmc + 1); 5013 ulpsc->cmd_more = htobe32(V_ULPTX_CMD(ULP_TX_SC_IMM) | 5014 F_ULP_TX_SC_MORE); 5015 ulpsc->len = htobe32(sizeof(struct cpl_tx_pkt_core)); 5016 5017 cpl = (void *)(ulpsc + 1); 5018 if (checkwrap && 5019 (uintptr_t)cpl == (uintptr_t)&eq->desc[eq->sidx]) 5020 cpl = (void *)&eq->desc[0]; 5021 } else { 5022 cpl = flitp; 5023 } 5024 5025 /* Checksum offload */ 5026 ctrl1 = 0; 5027 if (needs_l3_csum(m) == 0) 5028 ctrl1 |= F_TXPKT_IPCSUM_DIS; 5029 if (needs_l4_csum(m) == 0) 5030 ctrl1 |= F_TXPKT_L4CSUM_DIS; 5031 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | 5032 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO)) 5033 txq->txcsum++; /* some hardware assistance provided */ 5034 5035 /* VLAN tag insertion */ 5036 if (needs_vlan_insertion(m)) { 5037 ctrl1 |= F_TXPKT_VLAN_VLD | 5038 V_TXPKT_VLAN(m->m_pkthdr.ether_vtag); 5039 txq->vlan_insertion++; 5040 } 5041 5042 /* CPL header */ 5043 cpl->ctrl0 = txq->cpl_ctrl0; 5044 cpl->pack = 0; 5045 cpl->len = htobe16(m->m_pkthdr.len); 5046 cpl->ctrl1 = htobe64(ctrl1); 5047 5048 flitp = cpl + 1; 5049 if (checkwrap && 5050 (uintptr_t)flitp == (uintptr_t)&eq->desc[eq->sidx]) 5051 flitp = (void *)&eq->desc[0]; 5052 5053 write_gl_to_txd(txq, m, (caddr_t *)(&flitp), checkwrap); 5054 5055 } 5056 5057 if (txp->wr_type == 0) { 5058 txq->txpkts0_pkts += txp->npkt; 5059 txq->txpkts0_wrs++; 5060 } else { 5061 txq->txpkts1_pkts += txp->npkt; 5062 txq->txpkts1_wrs++; 5063 } 5064 5065 txsd = &txq->sdesc[eq->pidx]; 5066 txsd->m = m0; 5067 txsd->desc_used = ndesc; 5068 5069 return (ndesc); 5070 } 5071 5072 /* 5073 * If the SGL ends on an address that is not 16 byte aligned, this function will 5074 * add a 0 filled flit at the end. 5075 */ 5076 static void 5077 write_gl_to_txd(struct sge_txq *txq, struct mbuf *m, caddr_t *to, int checkwrap) 5078 { 5079 struct sge_eq *eq = &txq->eq; 5080 struct sglist *gl = txq->gl; 5081 struct sglist_seg *seg; 5082 __be64 *flitp, *wrap; 5083 struct ulptx_sgl *usgl; 5084 int i, nflits, nsegs; 5085 5086 KASSERT(((uintptr_t)(*to) & 0xf) == 0, 5087 ("%s: SGL must start at a 16 byte boundary: %p", __func__, *to)); 5088 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]); 5089 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]); 5090 5091 get_pkt_gl(m, gl); 5092 nsegs = gl->sg_nseg; 5093 MPASS(nsegs > 0); 5094 5095 nflits = (3 * (nsegs - 1)) / 2 + ((nsegs - 1) & 1) + 2; 5096 flitp = (__be64 *)(*to); 5097 wrap = (__be64 *)(&eq->desc[eq->sidx]); 5098 seg = &gl->sg_segs[0]; 5099 usgl = (void *)flitp; 5100 5101 /* 5102 * We start at a 16 byte boundary somewhere inside the tx descriptor 5103 * ring, so we're at least 16 bytes away from the status page. There is 5104 * no chance of a wrap around in the middle of usgl (which is 16 bytes). 5105 */ 5106 5107 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 5108 V_ULPTX_NSGE(nsegs)); 5109 usgl->len0 = htobe32(seg->ss_len); 5110 usgl->addr0 = htobe64(seg->ss_paddr); 5111 seg++; 5112 5113 if (checkwrap == 0 || (uintptr_t)(flitp + nflits) <= (uintptr_t)wrap) { 5114 5115 /* Won't wrap around at all */ 5116 5117 for (i = 0; i < nsegs - 1; i++, seg++) { 5118 usgl->sge[i / 2].len[i & 1] = htobe32(seg->ss_len); 5119 usgl->sge[i / 2].addr[i & 1] = htobe64(seg->ss_paddr); 5120 } 5121 if (i & 1) 5122 usgl->sge[i / 2].len[1] = htobe32(0); 5123 flitp += nflits; 5124 } else { 5125 5126 /* Will wrap somewhere in the rest of the SGL */ 5127 5128 /* 2 flits already written, write the rest flit by flit */ 5129 flitp = (void *)(usgl + 1); 5130 for (i = 0; i < nflits - 2; i++) { 5131 if (flitp == wrap) 5132 flitp = (void *)eq->desc; 5133 *flitp++ = get_flit(seg, nsegs - 1, i); 5134 } 5135 } 5136 5137 if (nflits & 1) { 5138 MPASS(((uintptr_t)flitp) & 0xf); 5139 *flitp++ = 0; 5140 } 5141 5142 MPASS((((uintptr_t)flitp) & 0xf) == 0); 5143 if (__predict_false(flitp == wrap)) 5144 *to = (void *)eq->desc; 5145 else 5146 *to = (void *)flitp; 5147 } 5148 5149 static inline void 5150 copy_to_txd(struct sge_eq *eq, caddr_t from, caddr_t *to, int len) 5151 { 5152 5153 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]); 5154 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]); 5155 5156 if (__predict_true((uintptr_t)(*to) + len <= 5157 (uintptr_t)&eq->desc[eq->sidx])) { 5158 bcopy(from, *to, len); 5159 (*to) += len; 5160 } else { 5161 int portion = (uintptr_t)&eq->desc[eq->sidx] - (uintptr_t)(*to); 5162 5163 bcopy(from, *to, portion); 5164 from += portion; 5165 portion = len - portion; /* remaining */ 5166 bcopy(from, (void *)eq->desc, portion); 5167 (*to) = (caddr_t)eq->desc + portion; 5168 } 5169 } 5170 5171 static inline void 5172 ring_eq_db(struct adapter *sc, struct sge_eq *eq, u_int n) 5173 { 5174 u_int db; 5175 5176 MPASS(n > 0); 5177 5178 db = eq->doorbells; 5179 if (n > 1) 5180 clrbit(&db, DOORBELL_WCWR); 5181 wmb(); 5182 5183 switch (ffs(db) - 1) { 5184 case DOORBELL_UDB: 5185 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n)); 5186 break; 5187 5188 case DOORBELL_WCWR: { 5189 volatile uint64_t *dst, *src; 5190 int i; 5191 5192 /* 5193 * Queues whose 128B doorbell segment fits in the page do not 5194 * use relative qid (udb_qid is always 0). Only queues with 5195 * doorbell segments can do WCWR. 5196 */ 5197 KASSERT(eq->udb_qid == 0 && n == 1, 5198 ("%s: inappropriate doorbell (0x%x, %d, %d) for eq %p", 5199 __func__, eq->doorbells, n, eq->dbidx, eq)); 5200 5201 dst = (volatile void *)((uintptr_t)eq->udb + UDBS_WR_OFFSET - 5202 UDBS_DB_OFFSET); 5203 i = eq->dbidx; 5204 src = (void *)&eq->desc[i]; 5205 while (src != (void *)&eq->desc[i + 1]) 5206 *dst++ = *src++; 5207 wmb(); 5208 break; 5209 } 5210 5211 case DOORBELL_UDBWC: 5212 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n)); 5213 wmb(); 5214 break; 5215 5216 case DOORBELL_KDB: 5217 t4_write_reg(sc, sc->sge_kdoorbell_reg, 5218 V_QID(eq->cntxt_id) | V_PIDX(n)); 5219 break; 5220 } 5221 5222 IDXINCR(eq->dbidx, n, eq->sidx); 5223 } 5224 5225 static inline u_int 5226 reclaimable_tx_desc(struct sge_eq *eq) 5227 { 5228 uint16_t hw_cidx; 5229 5230 hw_cidx = read_hw_cidx(eq); 5231 return (IDXDIFF(hw_cidx, eq->cidx, eq->sidx)); 5232 } 5233 5234 static inline u_int 5235 total_available_tx_desc(struct sge_eq *eq) 5236 { 5237 uint16_t hw_cidx, pidx; 5238 5239 hw_cidx = read_hw_cidx(eq); 5240 pidx = eq->pidx; 5241 5242 if (pidx == hw_cidx) 5243 return (eq->sidx - 1); 5244 else 5245 return (IDXDIFF(hw_cidx, pidx, eq->sidx) - 1); 5246 } 5247 5248 static inline uint16_t 5249 read_hw_cidx(struct sge_eq *eq) 5250 { 5251 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx]; 5252 uint16_t cidx = spg->cidx; /* stable snapshot */ 5253 5254 return (be16toh(cidx)); 5255 } 5256 5257 /* 5258 * Reclaim 'n' descriptors approximately. 5259 */ 5260 static u_int 5261 reclaim_tx_descs(struct sge_txq *txq, u_int n) 5262 { 5263 struct tx_sdesc *txsd; 5264 struct sge_eq *eq = &txq->eq; 5265 u_int can_reclaim, reclaimed; 5266 5267 TXQ_LOCK_ASSERT_OWNED(txq); 5268 MPASS(n > 0); 5269 5270 reclaimed = 0; 5271 can_reclaim = reclaimable_tx_desc(eq); 5272 while (can_reclaim && reclaimed < n) { 5273 int ndesc; 5274 struct mbuf *m, *nextpkt; 5275 5276 txsd = &txq->sdesc[eq->cidx]; 5277 ndesc = txsd->desc_used; 5278 5279 /* Firmware doesn't return "partial" credits. */ 5280 KASSERT(can_reclaim >= ndesc, 5281 ("%s: unexpected number of credits: %d, %d", 5282 __func__, can_reclaim, ndesc)); 5283 KASSERT(ndesc != 0, 5284 ("%s: descriptor with no credits: cidx %d", 5285 __func__, eq->cidx)); 5286 5287 for (m = txsd->m; m != NULL; m = nextpkt) { 5288 nextpkt = m->m_nextpkt; 5289 m->m_nextpkt = NULL; 5290 m_freem(m); 5291 } 5292 reclaimed += ndesc; 5293 can_reclaim -= ndesc; 5294 IDXINCR(eq->cidx, ndesc, eq->sidx); 5295 } 5296 5297 return (reclaimed); 5298 } 5299 5300 static void 5301 tx_reclaim(void *arg, int n) 5302 { 5303 struct sge_txq *txq = arg; 5304 struct sge_eq *eq = &txq->eq; 5305 5306 do { 5307 if (TXQ_TRYLOCK(txq) == 0) 5308 break; 5309 n = reclaim_tx_descs(txq, 32); 5310 if (eq->cidx == eq->pidx) 5311 eq->equeqidx = eq->pidx; 5312 TXQ_UNLOCK(txq); 5313 } while (n > 0); 5314 } 5315 5316 static __be64 5317 get_flit(struct sglist_seg *segs, int nsegs, int idx) 5318 { 5319 int i = (idx / 3) * 2; 5320 5321 switch (idx % 3) { 5322 case 0: { 5323 uint64_t rc; 5324 5325 rc = (uint64_t)segs[i].ss_len << 32; 5326 if (i + 1 < nsegs) 5327 rc |= (uint64_t)(segs[i + 1].ss_len); 5328 5329 return (htobe64(rc)); 5330 } 5331 case 1: 5332 return (htobe64(segs[i].ss_paddr)); 5333 case 2: 5334 return (htobe64(segs[i + 1].ss_paddr)); 5335 } 5336 5337 return (0); 5338 } 5339 5340 static void 5341 find_best_refill_source(struct adapter *sc, struct sge_fl *fl, int maxp) 5342 { 5343 int8_t zidx, hwidx, idx; 5344 uint16_t region1, region3; 5345 int spare, spare_needed, n; 5346 struct sw_zone_info *swz; 5347 struct hw_buf_info *hwb, *hwb_list = &sc->sge.hw_buf_info[0]; 5348 5349 /* 5350 * Buffer Packing: Look for PAGE_SIZE or larger zone which has a bufsize 5351 * large enough for the max payload and cluster metadata. Otherwise 5352 * settle for the largest bufsize that leaves enough room in the cluster 5353 * for metadata. 5354 * 5355 * Without buffer packing: Look for the smallest zone which has a 5356 * bufsize large enough for the max payload. Settle for the largest 5357 * bufsize available if there's nothing big enough for max payload. 5358 */ 5359 spare_needed = fl->flags & FL_BUF_PACKING ? CL_METADATA_SIZE : 0; 5360 swz = &sc->sge.sw_zone_info[0]; 5361 hwidx = -1; 5362 for (zidx = 0; zidx < SW_ZONE_SIZES; zidx++, swz++) { 5363 if (swz->size > largest_rx_cluster) { 5364 if (__predict_true(hwidx != -1)) 5365 break; 5366 5367 /* 5368 * This is a misconfiguration. largest_rx_cluster is 5369 * preventing us from finding a refill source. See 5370 * dev.t5nex.<n>.buffer_sizes to figure out why. 5371 */ 5372 device_printf(sc->dev, "largest_rx_cluster=%u leaves no" 5373 " refill source for fl %p (dma %u). Ignored.\n", 5374 largest_rx_cluster, fl, maxp); 5375 } 5376 for (idx = swz->head_hwidx; idx != -1; idx = hwb->next) { 5377 hwb = &hwb_list[idx]; 5378 spare = swz->size - hwb->size; 5379 if (spare < spare_needed) 5380 continue; 5381 5382 hwidx = idx; /* best option so far */ 5383 if (hwb->size >= maxp) { 5384 5385 if ((fl->flags & FL_BUF_PACKING) == 0) 5386 goto done; /* stop looking (not packing) */ 5387 5388 if (swz->size >= safest_rx_cluster) 5389 goto done; /* stop looking (packing) */ 5390 } 5391 break; /* keep looking, next zone */ 5392 } 5393 } 5394 done: 5395 /* A usable hwidx has been located. */ 5396 MPASS(hwidx != -1); 5397 hwb = &hwb_list[hwidx]; 5398 zidx = hwb->zidx; 5399 swz = &sc->sge.sw_zone_info[zidx]; 5400 region1 = 0; 5401 region3 = swz->size - hwb->size; 5402 5403 /* 5404 * Stay within this zone and see if there is a better match when mbuf 5405 * inlining is allowed. Remember that the hwidx's are sorted in 5406 * decreasing order of size (so in increasing order of spare area). 5407 */ 5408 for (idx = hwidx; idx != -1; idx = hwb->next) { 5409 hwb = &hwb_list[idx]; 5410 spare = swz->size - hwb->size; 5411 5412 if (allow_mbufs_in_cluster == 0 || hwb->size < maxp) 5413 break; 5414 5415 /* 5416 * Do not inline mbufs if doing so would violate the pad/pack 5417 * boundary alignment requirement. 5418 */ 5419 if (fl_pad && (MSIZE % sc->params.sge.pad_boundary) != 0) 5420 continue; 5421 if (fl->flags & FL_BUF_PACKING && 5422 (MSIZE % sc->params.sge.pack_boundary) != 0) 5423 continue; 5424 5425 if (spare < CL_METADATA_SIZE + MSIZE) 5426 continue; 5427 n = (spare - CL_METADATA_SIZE) / MSIZE; 5428 if (n > howmany(hwb->size, maxp)) 5429 break; 5430 5431 hwidx = idx; 5432 if (fl->flags & FL_BUF_PACKING) { 5433 region1 = n * MSIZE; 5434 region3 = spare - region1; 5435 } else { 5436 region1 = MSIZE; 5437 region3 = spare - region1; 5438 break; 5439 } 5440 } 5441 5442 KASSERT(zidx >= 0 && zidx < SW_ZONE_SIZES, 5443 ("%s: bad zone %d for fl %p, maxp %d", __func__, zidx, fl, maxp)); 5444 KASSERT(hwidx >= 0 && hwidx <= SGE_FLBUF_SIZES, 5445 ("%s: bad hwidx %d for fl %p, maxp %d", __func__, hwidx, fl, maxp)); 5446 KASSERT(region1 + sc->sge.hw_buf_info[hwidx].size + region3 == 5447 sc->sge.sw_zone_info[zidx].size, 5448 ("%s: bad buffer layout for fl %p, maxp %d. " 5449 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp, 5450 sc->sge.sw_zone_info[zidx].size, region1, 5451 sc->sge.hw_buf_info[hwidx].size, region3)); 5452 if (fl->flags & FL_BUF_PACKING || region1 > 0) { 5453 KASSERT(region3 >= CL_METADATA_SIZE, 5454 ("%s: no room for metadata. fl %p, maxp %d; " 5455 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp, 5456 sc->sge.sw_zone_info[zidx].size, region1, 5457 sc->sge.hw_buf_info[hwidx].size, region3)); 5458 KASSERT(region1 % MSIZE == 0, 5459 ("%s: bad mbuf region for fl %p, maxp %d. " 5460 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp, 5461 sc->sge.sw_zone_info[zidx].size, region1, 5462 sc->sge.hw_buf_info[hwidx].size, region3)); 5463 } 5464 5465 fl->cll_def.zidx = zidx; 5466 fl->cll_def.hwidx = hwidx; 5467 fl->cll_def.region1 = region1; 5468 fl->cll_def.region3 = region3; 5469 } 5470 5471 static void 5472 find_safe_refill_source(struct adapter *sc, struct sge_fl *fl) 5473 { 5474 struct sge *s = &sc->sge; 5475 struct hw_buf_info *hwb; 5476 struct sw_zone_info *swz; 5477 int spare; 5478 int8_t hwidx; 5479 5480 if (fl->flags & FL_BUF_PACKING) 5481 hwidx = s->safe_hwidx2; /* with room for metadata */ 5482 else if (allow_mbufs_in_cluster && s->safe_hwidx2 != -1) { 5483 hwidx = s->safe_hwidx2; 5484 hwb = &s->hw_buf_info[hwidx]; 5485 swz = &s->sw_zone_info[hwb->zidx]; 5486 spare = swz->size - hwb->size; 5487 5488 /* no good if there isn't room for an mbuf as well */ 5489 if (spare < CL_METADATA_SIZE + MSIZE) 5490 hwidx = s->safe_hwidx1; 5491 } else 5492 hwidx = s->safe_hwidx1; 5493 5494 if (hwidx == -1) { 5495 /* No fallback source */ 5496 fl->cll_alt.hwidx = -1; 5497 fl->cll_alt.zidx = -1; 5498 5499 return; 5500 } 5501 5502 hwb = &s->hw_buf_info[hwidx]; 5503 swz = &s->sw_zone_info[hwb->zidx]; 5504 spare = swz->size - hwb->size; 5505 fl->cll_alt.hwidx = hwidx; 5506 fl->cll_alt.zidx = hwb->zidx; 5507 if (allow_mbufs_in_cluster && 5508 (fl_pad == 0 || (MSIZE % sc->params.sge.pad_boundary) == 0)) 5509 fl->cll_alt.region1 = ((spare - CL_METADATA_SIZE) / MSIZE) * MSIZE; 5510 else 5511 fl->cll_alt.region1 = 0; 5512 fl->cll_alt.region3 = spare - fl->cll_alt.region1; 5513 } 5514 5515 static void 5516 add_fl_to_sfl(struct adapter *sc, struct sge_fl *fl) 5517 { 5518 mtx_lock(&sc->sfl_lock); 5519 FL_LOCK(fl); 5520 if ((fl->flags & FL_DOOMED) == 0) { 5521 fl->flags |= FL_STARVING; 5522 TAILQ_INSERT_TAIL(&sc->sfl, fl, link); 5523 callout_reset(&sc->sfl_callout, hz / 5, refill_sfl, sc); 5524 } 5525 FL_UNLOCK(fl); 5526 mtx_unlock(&sc->sfl_lock); 5527 } 5528 5529 static void 5530 handle_wrq_egr_update(struct adapter *sc, struct sge_eq *eq) 5531 { 5532 struct sge_wrq *wrq = (void *)eq; 5533 5534 atomic_readandclear_int(&eq->equiq); 5535 taskqueue_enqueue(sc->tq[eq->tx_chan], &wrq->wrq_tx_task); 5536 } 5537 5538 static void 5539 handle_eth_egr_update(struct adapter *sc, struct sge_eq *eq) 5540 { 5541 struct sge_txq *txq = (void *)eq; 5542 5543 MPASS((eq->flags & EQ_TYPEMASK) == EQ_ETH); 5544 5545 atomic_readandclear_int(&eq->equiq); 5546 mp_ring_check_drainage(txq->r, 0); 5547 taskqueue_enqueue(sc->tq[eq->tx_chan], &txq->tx_reclaim_task); 5548 } 5549 5550 static int 5551 handle_sge_egr_update(struct sge_iq *iq, const struct rss_header *rss, 5552 struct mbuf *m) 5553 { 5554 const struct cpl_sge_egr_update *cpl = (const void *)(rss + 1); 5555 unsigned int qid = G_EGR_QID(ntohl(cpl->opcode_qid)); 5556 struct adapter *sc = iq->adapter; 5557 struct sge *s = &sc->sge; 5558 struct sge_eq *eq; 5559 static void (*h[])(struct adapter *, struct sge_eq *) = {NULL, 5560 &handle_wrq_egr_update, &handle_eth_egr_update, 5561 &handle_wrq_egr_update}; 5562 5563 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 5564 rss->opcode)); 5565 5566 eq = s->eqmap[qid - s->eq_start - s->eq_base]; 5567 (*h[eq->flags & EQ_TYPEMASK])(sc, eq); 5568 5569 return (0); 5570 } 5571 5572 /* handle_fw_msg works for both fw4_msg and fw6_msg because this is valid */ 5573 CTASSERT(offsetof(struct cpl_fw4_msg, data) == \ 5574 offsetof(struct cpl_fw6_msg, data)); 5575 5576 static int 5577 handle_fw_msg(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 5578 { 5579 struct adapter *sc = iq->adapter; 5580 const struct cpl_fw6_msg *cpl = (const void *)(rss + 1); 5581 5582 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 5583 rss->opcode)); 5584 5585 if (cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL) { 5586 const struct rss_header *rss2; 5587 5588 rss2 = (const struct rss_header *)&cpl->data[0]; 5589 return (t4_cpl_handler[rss2->opcode](iq, rss2, m)); 5590 } 5591 5592 return (t4_fw_msg_handler[cpl->type](sc, &cpl->data[0])); 5593 } 5594 5595 /** 5596 * t4_handle_wrerr_rpl - process a FW work request error message 5597 * @adap: the adapter 5598 * @rpl: start of the FW message 5599 */ 5600 static int 5601 t4_handle_wrerr_rpl(struct adapter *adap, const __be64 *rpl) 5602 { 5603 u8 opcode = *(const u8 *)rpl; 5604 const struct fw_error_cmd *e = (const void *)rpl; 5605 unsigned int i; 5606 5607 if (opcode != FW_ERROR_CMD) { 5608 log(LOG_ERR, 5609 "%s: Received WRERR_RPL message with opcode %#x\n", 5610 device_get_nameunit(adap->dev), opcode); 5611 return (EINVAL); 5612 } 5613 log(LOG_ERR, "%s: FW_ERROR (%s) ", device_get_nameunit(adap->dev), 5614 G_FW_ERROR_CMD_FATAL(be32toh(e->op_to_type)) ? "fatal" : 5615 "non-fatal"); 5616 switch (G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type))) { 5617 case FW_ERROR_TYPE_EXCEPTION: 5618 log(LOG_ERR, "exception info:\n"); 5619 for (i = 0; i < nitems(e->u.exception.info); i++) 5620 log(LOG_ERR, "%s%08x", i == 0 ? "\t" : " ", 5621 be32toh(e->u.exception.info[i])); 5622 log(LOG_ERR, "\n"); 5623 break; 5624 case FW_ERROR_TYPE_HWMODULE: 5625 log(LOG_ERR, "HW module regaddr %08x regval %08x\n", 5626 be32toh(e->u.hwmodule.regaddr), 5627 be32toh(e->u.hwmodule.regval)); 5628 break; 5629 case FW_ERROR_TYPE_WR: 5630 log(LOG_ERR, "WR cidx %d PF %d VF %d eqid %d hdr:\n", 5631 be16toh(e->u.wr.cidx), 5632 G_FW_ERROR_CMD_PFN(be16toh(e->u.wr.pfn_vfn)), 5633 G_FW_ERROR_CMD_VFN(be16toh(e->u.wr.pfn_vfn)), 5634 be32toh(e->u.wr.eqid)); 5635 for (i = 0; i < nitems(e->u.wr.wrhdr); i++) 5636 log(LOG_ERR, "%s%02x", i == 0 ? "\t" : " ", 5637 e->u.wr.wrhdr[i]); 5638 log(LOG_ERR, "\n"); 5639 break; 5640 case FW_ERROR_TYPE_ACL: 5641 log(LOG_ERR, "ACL cidx %d PF %d VF %d eqid %d %s", 5642 be16toh(e->u.acl.cidx), 5643 G_FW_ERROR_CMD_PFN(be16toh(e->u.acl.pfn_vfn)), 5644 G_FW_ERROR_CMD_VFN(be16toh(e->u.acl.pfn_vfn)), 5645 be32toh(e->u.acl.eqid), 5646 G_FW_ERROR_CMD_MV(be16toh(e->u.acl.mv_pkd)) ? "vlanid" : 5647 "MAC"); 5648 for (i = 0; i < nitems(e->u.acl.val); i++) 5649 log(LOG_ERR, " %02x", e->u.acl.val[i]); 5650 log(LOG_ERR, "\n"); 5651 break; 5652 default: 5653 log(LOG_ERR, "type %#x\n", 5654 G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type))); 5655 return (EINVAL); 5656 } 5657 return (0); 5658 } 5659 5660 static int 5661 sysctl_uint16(SYSCTL_HANDLER_ARGS) 5662 { 5663 uint16_t *id = arg1; 5664 int i = *id; 5665 5666 return sysctl_handle_int(oidp, &i, 0, req); 5667 } 5668 5669 static int 5670 sysctl_bufsizes(SYSCTL_HANDLER_ARGS) 5671 { 5672 struct sge *s = arg1; 5673 struct hw_buf_info *hwb = &s->hw_buf_info[0]; 5674 struct sw_zone_info *swz = &s->sw_zone_info[0]; 5675 int i, rc; 5676 struct sbuf sb; 5677 char c; 5678 5679 sbuf_new(&sb, NULL, 32, SBUF_AUTOEXTEND); 5680 for (i = 0; i < SGE_FLBUF_SIZES; i++, hwb++) { 5681 if (hwb->zidx >= 0 && swz[hwb->zidx].size <= largest_rx_cluster) 5682 c = '*'; 5683 else 5684 c = '\0'; 5685 5686 sbuf_printf(&sb, "%u%c ", hwb->size, c); 5687 } 5688 sbuf_trim(&sb); 5689 sbuf_finish(&sb); 5690 rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req); 5691 sbuf_delete(&sb); 5692 return (rc); 5693 } 5694 5695 #ifdef RATELIMIT 5696 /* 5697 * len16 for a txpkt WR with a GL. Includes the firmware work request header. 5698 */ 5699 static inline u_int 5700 txpkt_eo_len16(u_int nsegs, u_int immhdrs, u_int tso) 5701 { 5702 u_int n; 5703 5704 MPASS(immhdrs > 0); 5705 5706 n = roundup2(sizeof(struct fw_eth_tx_eo_wr) + 5707 sizeof(struct cpl_tx_pkt_core) + immhdrs, 16); 5708 if (__predict_false(nsegs == 0)) 5709 goto done; 5710 5711 nsegs--; /* first segment is part of ulptx_sgl */ 5712 n += sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 5713 if (tso) 5714 n += sizeof(struct cpl_tx_pkt_lso_core); 5715 5716 done: 5717 return (howmany(n, 16)); 5718 } 5719 5720 #define ETID_FLOWC_NPARAMS 6 5721 #define ETID_FLOWC_LEN (roundup2((sizeof(struct fw_flowc_wr) + \ 5722 ETID_FLOWC_NPARAMS * sizeof(struct fw_flowc_mnemval)), 16)) 5723 #define ETID_FLOWC_LEN16 (howmany(ETID_FLOWC_LEN, 16)) 5724 5725 static int 5726 send_etid_flowc_wr(struct cxgbe_snd_tag *cst, struct port_info *pi, 5727 struct vi_info *vi) 5728 { 5729 struct wrq_cookie cookie; 5730 u_int pfvf = pi->adapter->pf << S_FW_VIID_PFN; 5731 struct fw_flowc_wr *flowc; 5732 5733 mtx_assert(&cst->lock, MA_OWNED); 5734 MPASS((cst->flags & (EO_FLOWC_PENDING | EO_FLOWC_RPL_PENDING)) == 5735 EO_FLOWC_PENDING); 5736 5737 flowc = start_wrq_wr(cst->eo_txq, ETID_FLOWC_LEN16, &cookie); 5738 if (__predict_false(flowc == NULL)) 5739 return (ENOMEM); 5740 5741 bzero(flowc, ETID_FLOWC_LEN); 5742 flowc->op_to_nparams = htobe32(V_FW_WR_OP(FW_FLOWC_WR) | 5743 V_FW_FLOWC_WR_NPARAMS(ETID_FLOWC_NPARAMS) | V_FW_WR_COMPL(0)); 5744 flowc->flowid_len16 = htonl(V_FW_WR_LEN16(ETID_FLOWC_LEN16) | 5745 V_FW_WR_FLOWID(cst->etid)); 5746 flowc->mnemval[0].mnemonic = FW_FLOWC_MNEM_PFNVFN; 5747 flowc->mnemval[0].val = htobe32(pfvf); 5748 flowc->mnemval[1].mnemonic = FW_FLOWC_MNEM_CH; 5749 flowc->mnemval[1].val = htobe32(pi->tx_chan); 5750 flowc->mnemval[2].mnemonic = FW_FLOWC_MNEM_PORT; 5751 flowc->mnemval[2].val = htobe32(pi->tx_chan); 5752 flowc->mnemval[3].mnemonic = FW_FLOWC_MNEM_IQID; 5753 flowc->mnemval[3].val = htobe32(cst->iqid); 5754 flowc->mnemval[4].mnemonic = FW_FLOWC_MNEM_EOSTATE; 5755 flowc->mnemval[4].val = htobe32(FW_FLOWC_MNEM_EOSTATE_ESTABLISHED); 5756 flowc->mnemval[5].mnemonic = FW_FLOWC_MNEM_SCHEDCLASS; 5757 flowc->mnemval[5].val = htobe32(cst->schedcl); 5758 5759 commit_wrq_wr(cst->eo_txq, flowc, &cookie); 5760 5761 cst->flags &= ~EO_FLOWC_PENDING; 5762 cst->flags |= EO_FLOWC_RPL_PENDING; 5763 MPASS(cst->tx_credits >= ETID_FLOWC_LEN16); /* flowc is first WR. */ 5764 cst->tx_credits -= ETID_FLOWC_LEN16; 5765 5766 return (0); 5767 } 5768 5769 #define ETID_FLUSH_LEN16 (howmany(sizeof (struct fw_flowc_wr), 16)) 5770 5771 void 5772 send_etid_flush_wr(struct cxgbe_snd_tag *cst) 5773 { 5774 struct fw_flowc_wr *flowc; 5775 struct wrq_cookie cookie; 5776 5777 mtx_assert(&cst->lock, MA_OWNED); 5778 5779 flowc = start_wrq_wr(cst->eo_txq, ETID_FLUSH_LEN16, &cookie); 5780 if (__predict_false(flowc == NULL)) 5781 CXGBE_UNIMPLEMENTED(__func__); 5782 5783 bzero(flowc, ETID_FLUSH_LEN16 * 16); 5784 flowc->op_to_nparams = htobe32(V_FW_WR_OP(FW_FLOWC_WR) | 5785 V_FW_FLOWC_WR_NPARAMS(0) | F_FW_WR_COMPL); 5786 flowc->flowid_len16 = htobe32(V_FW_WR_LEN16(ETID_FLUSH_LEN16) | 5787 V_FW_WR_FLOWID(cst->etid)); 5788 5789 commit_wrq_wr(cst->eo_txq, flowc, &cookie); 5790 5791 cst->flags |= EO_FLUSH_RPL_PENDING; 5792 MPASS(cst->tx_credits >= ETID_FLUSH_LEN16); 5793 cst->tx_credits -= ETID_FLUSH_LEN16; 5794 cst->ncompl++; 5795 } 5796 5797 static void 5798 write_ethofld_wr(struct cxgbe_snd_tag *cst, struct fw_eth_tx_eo_wr *wr, 5799 struct mbuf *m0, int compl) 5800 { 5801 struct cpl_tx_pkt_core *cpl; 5802 uint64_t ctrl1; 5803 uint32_t ctrl; /* used in many unrelated places */ 5804 int len16, pktlen, nsegs, immhdrs; 5805 caddr_t dst; 5806 uintptr_t p; 5807 struct ulptx_sgl *usgl; 5808 struct sglist sg; 5809 struct sglist_seg segs[38]; /* XXX: find real limit. XXX: get off the stack */ 5810 5811 mtx_assert(&cst->lock, MA_OWNED); 5812 M_ASSERTPKTHDR(m0); 5813 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 5814 m0->m_pkthdr.l4hlen > 0, 5815 ("%s: ethofld mbuf %p is missing header lengths", __func__, m0)); 5816 5817 len16 = mbuf_eo_len16(m0); 5818 nsegs = mbuf_eo_nsegs(m0); 5819 pktlen = m0->m_pkthdr.len; 5820 ctrl = sizeof(struct cpl_tx_pkt_core); 5821 if (needs_tso(m0)) 5822 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 5823 immhdrs = m0->m_pkthdr.l2hlen + m0->m_pkthdr.l3hlen + m0->m_pkthdr.l4hlen; 5824 ctrl += immhdrs; 5825 5826 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_EO_WR) | 5827 V_FW_ETH_TX_EO_WR_IMMDLEN(ctrl) | V_FW_WR_COMPL(!!compl)); 5828 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(len16) | 5829 V_FW_WR_FLOWID(cst->etid)); 5830 wr->r3 = 0; 5831 if (needs_udp_csum(m0)) { 5832 wr->u.udpseg.type = FW_ETH_TX_EO_TYPE_UDPSEG; 5833 wr->u.udpseg.ethlen = m0->m_pkthdr.l2hlen; 5834 wr->u.udpseg.iplen = htobe16(m0->m_pkthdr.l3hlen); 5835 wr->u.udpseg.udplen = m0->m_pkthdr.l4hlen; 5836 wr->u.udpseg.rtplen = 0; 5837 wr->u.udpseg.r4 = 0; 5838 wr->u.udpseg.mss = htobe16(pktlen - immhdrs); 5839 wr->u.udpseg.schedpktsize = wr->u.udpseg.mss; 5840 wr->u.udpseg.plen = htobe32(pktlen - immhdrs); 5841 cpl = (void *)(wr + 1); 5842 } else { 5843 MPASS(needs_tcp_csum(m0)); 5844 wr->u.tcpseg.type = FW_ETH_TX_EO_TYPE_TCPSEG; 5845 wr->u.tcpseg.ethlen = m0->m_pkthdr.l2hlen; 5846 wr->u.tcpseg.iplen = htobe16(m0->m_pkthdr.l3hlen); 5847 wr->u.tcpseg.tcplen = m0->m_pkthdr.l4hlen; 5848 wr->u.tcpseg.tsclk_tsoff = mbuf_eo_tsclk_tsoff(m0); 5849 wr->u.tcpseg.r4 = 0; 5850 wr->u.tcpseg.r5 = 0; 5851 wr->u.tcpseg.plen = htobe32(pktlen - immhdrs); 5852 5853 if (needs_tso(m0)) { 5854 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1); 5855 5856 wr->u.tcpseg.mss = htobe16(m0->m_pkthdr.tso_segsz); 5857 5858 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | 5859 F_LSO_FIRST_SLICE | F_LSO_LAST_SLICE | 5860 V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) | 5861 V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2); 5862 if (m0->m_pkthdr.l2hlen == sizeof(struct ether_vlan_header)) 5863 ctrl |= V_LSO_ETHHDR_LEN(1); 5864 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 5865 ctrl |= F_LSO_IPV6; 5866 lso->lso_ctrl = htobe32(ctrl); 5867 lso->ipid_ofst = htobe16(0); 5868 lso->mss = htobe16(m0->m_pkthdr.tso_segsz); 5869 lso->seqno_offset = htobe32(0); 5870 lso->len = htobe32(pktlen); 5871 5872 cpl = (void *)(lso + 1); 5873 } else { 5874 wr->u.tcpseg.mss = htobe16(0xffff); 5875 cpl = (void *)(wr + 1); 5876 } 5877 } 5878 5879 /* Checksum offload must be requested for ethofld. */ 5880 ctrl1 = 0; 5881 MPASS(needs_l4_csum(m0)); 5882 5883 /* VLAN tag insertion */ 5884 if (needs_vlan_insertion(m0)) { 5885 ctrl1 |= F_TXPKT_VLAN_VLD | 5886 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 5887 } 5888 5889 /* CPL header */ 5890 cpl->ctrl0 = cst->ctrl0; 5891 cpl->pack = 0; 5892 cpl->len = htobe16(pktlen); 5893 cpl->ctrl1 = htobe64(ctrl1); 5894 5895 /* Copy Ethernet, IP & TCP/UDP hdrs as immediate data */ 5896 p = (uintptr_t)(cpl + 1); 5897 m_copydata(m0, 0, immhdrs, (void *)p); 5898 5899 /* SGL */ 5900 dst = (void *)(cpl + 1); 5901 if (nsegs > 0) { 5902 int i, pad; 5903 5904 /* zero-pad upto next 16Byte boundary, if not 16Byte aligned */ 5905 p += immhdrs; 5906 pad = 16 - (immhdrs & 0xf); 5907 bzero((void *)p, pad); 5908 5909 usgl = (void *)(p + pad); 5910 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 5911 V_ULPTX_NSGE(nsegs)); 5912 5913 sglist_init(&sg, nitems(segs), segs); 5914 for (; m0 != NULL; m0 = m0->m_next) { 5915 if (__predict_false(m0->m_len == 0)) 5916 continue; 5917 if (immhdrs >= m0->m_len) { 5918 immhdrs -= m0->m_len; 5919 continue; 5920 } 5921 5922 sglist_append(&sg, mtod(m0, char *) + immhdrs, 5923 m0->m_len - immhdrs); 5924 immhdrs = 0; 5925 } 5926 MPASS(sg.sg_nseg == nsegs); 5927 5928 /* 5929 * Zero pad last 8B in case the WR doesn't end on a 16B 5930 * boundary. 5931 */ 5932 *(uint64_t *)((char *)wr + len16 * 16 - 8) = 0; 5933 5934 usgl->len0 = htobe32(segs[0].ss_len); 5935 usgl->addr0 = htobe64(segs[0].ss_paddr); 5936 for (i = 0; i < nsegs - 1; i++) { 5937 usgl->sge[i / 2].len[i & 1] = htobe32(segs[i + 1].ss_len); 5938 usgl->sge[i / 2].addr[i & 1] = htobe64(segs[i + 1].ss_paddr); 5939 } 5940 if (i & 1) 5941 usgl->sge[i / 2].len[1] = htobe32(0); 5942 } 5943 5944 } 5945 5946 static void 5947 ethofld_tx(struct cxgbe_snd_tag *cst) 5948 { 5949 struct mbuf *m; 5950 struct wrq_cookie cookie; 5951 int next_credits, compl; 5952 struct fw_eth_tx_eo_wr *wr; 5953 5954 mtx_assert(&cst->lock, MA_OWNED); 5955 5956 while ((m = mbufq_first(&cst->pending_tx)) != NULL) { 5957 M_ASSERTPKTHDR(m); 5958 5959 /* How many len16 credits do we need to send this mbuf. */ 5960 next_credits = mbuf_eo_len16(m); 5961 MPASS(next_credits > 0); 5962 if (next_credits > cst->tx_credits) { 5963 /* 5964 * Tx will make progress eventually because there is at 5965 * least one outstanding fw4_ack that will return 5966 * credits and kick the tx. 5967 */ 5968 MPASS(cst->ncompl > 0); 5969 return; 5970 } 5971 wr = start_wrq_wr(cst->eo_txq, next_credits, &cookie); 5972 if (__predict_false(wr == NULL)) { 5973 /* XXX: wishful thinking, not a real assertion. */ 5974 MPASS(cst->ncompl > 0); 5975 return; 5976 } 5977 cst->tx_credits -= next_credits; 5978 cst->tx_nocompl += next_credits; 5979 compl = cst->ncompl == 0 || cst->tx_nocompl >= cst->tx_total / 2; 5980 ETHER_BPF_MTAP(cst->com.ifp, m); 5981 write_ethofld_wr(cst, wr, m, compl); 5982 commit_wrq_wr(cst->eo_txq, wr, &cookie); 5983 if (compl) { 5984 cst->ncompl++; 5985 cst->tx_nocompl = 0; 5986 } 5987 (void) mbufq_dequeue(&cst->pending_tx); 5988 5989 /* 5990 * Drop the mbuf's reference on the tag now rather 5991 * than waiting until m_freem(). This ensures that 5992 * cxgbe_snd_tag_free gets called when the inp drops 5993 * its reference on the tag and there are no more 5994 * mbufs in the pending_tx queue and can flush any 5995 * pending requests. Otherwise if the last mbuf 5996 * doesn't request a completion the etid will never be 5997 * released. 5998 */ 5999 m->m_pkthdr.snd_tag = NULL; 6000 m->m_pkthdr.csum_flags &= ~CSUM_SND_TAG; 6001 m_snd_tag_rele(&cst->com); 6002 6003 mbufq_enqueue(&cst->pending_fwack, m); 6004 } 6005 } 6006 6007 int 6008 ethofld_transmit(struct ifnet *ifp, struct mbuf *m0) 6009 { 6010 struct cxgbe_snd_tag *cst; 6011 int rc; 6012 6013 MPASS(m0->m_nextpkt == NULL); 6014 MPASS(m0->m_pkthdr.csum_flags & CSUM_SND_TAG); 6015 MPASS(m0->m_pkthdr.snd_tag != NULL); 6016 cst = mst_to_cst(m0->m_pkthdr.snd_tag); 6017 6018 mtx_lock(&cst->lock); 6019 MPASS(cst->flags & EO_SND_TAG_REF); 6020 6021 if (__predict_false(cst->flags & EO_FLOWC_PENDING)) { 6022 struct vi_info *vi = ifp->if_softc; 6023 struct port_info *pi = vi->pi; 6024 struct adapter *sc = pi->adapter; 6025 const uint32_t rss_mask = vi->rss_size - 1; 6026 uint32_t rss_hash; 6027 6028 cst->eo_txq = &sc->sge.ofld_txq[vi->first_ofld_txq]; 6029 if (M_HASHTYPE_ISHASH(m0)) 6030 rss_hash = m0->m_pkthdr.flowid; 6031 else 6032 rss_hash = arc4random(); 6033 /* We assume RSS hashing */ 6034 cst->iqid = vi->rss[rss_hash & rss_mask]; 6035 cst->eo_txq += rss_hash % vi->nofldtxq; 6036 rc = send_etid_flowc_wr(cst, pi, vi); 6037 if (rc != 0) 6038 goto done; 6039 } 6040 6041 if (__predict_false(cst->plen + m0->m_pkthdr.len > eo_max_backlog)) { 6042 rc = ENOBUFS; 6043 goto done; 6044 } 6045 6046 mbufq_enqueue(&cst->pending_tx, m0); 6047 cst->plen += m0->m_pkthdr.len; 6048 6049 /* 6050 * Hold an extra reference on the tag while generating work 6051 * requests to ensure that we don't try to free the tag during 6052 * ethofld_tx() in case we are sending the final mbuf after 6053 * the inp was freed. 6054 */ 6055 m_snd_tag_ref(&cst->com); 6056 ethofld_tx(cst); 6057 mtx_unlock(&cst->lock); 6058 m_snd_tag_rele(&cst->com); 6059 return (0); 6060 6061 done: 6062 mtx_unlock(&cst->lock); 6063 if (__predict_false(rc != 0)) 6064 m_freem(m0); 6065 return (rc); 6066 } 6067 6068 static int 6069 ethofld_fw4_ack(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0) 6070 { 6071 struct adapter *sc = iq->adapter; 6072 const struct cpl_fw4_ack *cpl = (const void *)(rss + 1); 6073 struct mbuf *m; 6074 u_int etid = G_CPL_FW4_ACK_FLOWID(be32toh(OPCODE_TID(cpl))); 6075 struct cxgbe_snd_tag *cst; 6076 uint8_t credits = cpl->credits; 6077 6078 cst = lookup_etid(sc, etid); 6079 mtx_lock(&cst->lock); 6080 if (__predict_false(cst->flags & EO_FLOWC_RPL_PENDING)) { 6081 MPASS(credits >= ETID_FLOWC_LEN16); 6082 credits -= ETID_FLOWC_LEN16; 6083 cst->flags &= ~EO_FLOWC_RPL_PENDING; 6084 } 6085 6086 KASSERT(cst->ncompl > 0, 6087 ("%s: etid %u (%p) wasn't expecting completion.", 6088 __func__, etid, cst)); 6089 cst->ncompl--; 6090 6091 while (credits > 0) { 6092 m = mbufq_dequeue(&cst->pending_fwack); 6093 if (__predict_false(m == NULL)) { 6094 /* 6095 * The remaining credits are for the final flush that 6096 * was issued when the tag was freed by the kernel. 6097 */ 6098 MPASS((cst->flags & 6099 (EO_FLUSH_RPL_PENDING | EO_SND_TAG_REF)) == 6100 EO_FLUSH_RPL_PENDING); 6101 MPASS(credits == ETID_FLUSH_LEN16); 6102 MPASS(cst->tx_credits + cpl->credits == cst->tx_total); 6103 MPASS(cst->ncompl == 0); 6104 6105 cst->flags &= ~EO_FLUSH_RPL_PENDING; 6106 cst->tx_credits += cpl->credits; 6107 cxgbe_snd_tag_free_locked(cst); 6108 return (0); /* cst is gone. */ 6109 } 6110 KASSERT(m != NULL, 6111 ("%s: too many credits (%u, %u)", __func__, cpl->credits, 6112 credits)); 6113 KASSERT(credits >= mbuf_eo_len16(m), 6114 ("%s: too few credits (%u, %u, %u)", __func__, 6115 cpl->credits, credits, mbuf_eo_len16(m))); 6116 credits -= mbuf_eo_len16(m); 6117 cst->plen -= m->m_pkthdr.len; 6118 m_freem(m); 6119 } 6120 6121 cst->tx_credits += cpl->credits; 6122 MPASS(cst->tx_credits <= cst->tx_total); 6123 6124 if (cst->flags & EO_SND_TAG_REF) { 6125 /* 6126 * As with ethofld_transmit(), hold an extra reference 6127 * so that the tag is stable across ethold_tx(). 6128 */ 6129 m_snd_tag_ref(&cst->com); 6130 m = mbufq_first(&cst->pending_tx); 6131 if (m != NULL && cst->tx_credits >= mbuf_eo_len16(m)) 6132 ethofld_tx(cst); 6133 mtx_unlock(&cst->lock); 6134 m_snd_tag_rele(&cst->com); 6135 } else { 6136 /* 6137 * There shouldn't be any pending packets if the tag 6138 * was freed by the kernel since any pending packet 6139 * should hold a reference to the tag. 6140 */ 6141 MPASS(mbufq_first(&cst->pending_tx) == NULL); 6142 mtx_unlock(&cst->lock); 6143 } 6144 6145 return (0); 6146 } 6147 #endif 6148