1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 Chelsio Communications, Inc. 5 * All rights reserved. 6 * Written by: Navdeep Parhar <np@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include "opt_inet.h" 34 #include "opt_inet6.h" 35 #include "opt_ratelimit.h" 36 37 #include <sys/types.h> 38 #include <sys/eventhandler.h> 39 #include <sys/mbuf.h> 40 #include <sys/socket.h> 41 #include <sys/kernel.h> 42 #include <sys/malloc.h> 43 #include <sys/queue.h> 44 #include <sys/sbuf.h> 45 #include <sys/taskqueue.h> 46 #include <sys/time.h> 47 #include <sys/sglist.h> 48 #include <sys/sysctl.h> 49 #include <sys/smp.h> 50 #include <sys/counter.h> 51 #include <net/bpf.h> 52 #include <net/ethernet.h> 53 #include <net/if.h> 54 #include <net/if_vlan_var.h> 55 #include <netinet/in.h> 56 #include <netinet/ip.h> 57 #include <netinet/ip6.h> 58 #include <netinet/tcp.h> 59 #include <netinet/udp.h> 60 #include <machine/in_cksum.h> 61 #include <machine/md_var.h> 62 #include <vm/vm.h> 63 #include <vm/pmap.h> 64 #ifdef DEV_NETMAP 65 #include <machine/bus.h> 66 #include <sys/selinfo.h> 67 #include <net/if_var.h> 68 #include <net/netmap.h> 69 #include <dev/netmap/netmap_kern.h> 70 #endif 71 72 #include "common/common.h" 73 #include "common/t4_regs.h" 74 #include "common/t4_regs_values.h" 75 #include "common/t4_msg.h" 76 #include "t4_l2t.h" 77 #include "t4_mp_ring.h" 78 79 #ifdef T4_PKT_TIMESTAMP 80 #define RX_COPY_THRESHOLD (MINCLSIZE - 8) 81 #else 82 #define RX_COPY_THRESHOLD MINCLSIZE 83 #endif 84 85 /* Internal mbuf flags stored in PH_loc.eight[1]. */ 86 #define MC_RAW_WR 0x02 87 88 /* 89 * Ethernet frames are DMA'd at this byte offset into the freelist buffer. 90 * 0-7 are valid values. 91 */ 92 static int fl_pktshift = 0; 93 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pktshift, CTLFLAG_RDTUN, &fl_pktshift, 0, 94 "payload DMA offset in rx buffer (bytes)"); 95 96 /* 97 * Pad ethernet payload up to this boundary. 98 * -1: driver should figure out a good value. 99 * 0: disable padding. 100 * Any power of 2 from 32 to 4096 (both inclusive) is also a valid value. 101 */ 102 int fl_pad = -1; 103 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pad, CTLFLAG_RDTUN, &fl_pad, 0, 104 "payload pad boundary (bytes)"); 105 106 /* 107 * Status page length. 108 * -1: driver should figure out a good value. 109 * 64 or 128 are the only other valid values. 110 */ 111 static int spg_len = -1; 112 SYSCTL_INT(_hw_cxgbe, OID_AUTO, spg_len, CTLFLAG_RDTUN, &spg_len, 0, 113 "status page size (bytes)"); 114 115 /* 116 * Congestion drops. 117 * -1: no congestion feedback (not recommended). 118 * 0: backpressure the channel instead of dropping packets right away. 119 * 1: no backpressure, drop packets for the congested queue immediately. 120 */ 121 static int cong_drop = 0; 122 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cong_drop, CTLFLAG_RDTUN, &cong_drop, 0, 123 "Congestion control for RX queues (0 = backpressure, 1 = drop"); 124 125 /* 126 * Deliver multiple frames in the same free list buffer if they fit. 127 * -1: let the driver decide whether to enable buffer packing or not. 128 * 0: disable buffer packing. 129 * 1: enable buffer packing. 130 */ 131 static int buffer_packing = -1; 132 SYSCTL_INT(_hw_cxgbe, OID_AUTO, buffer_packing, CTLFLAG_RDTUN, &buffer_packing, 133 0, "Enable buffer packing"); 134 135 /* 136 * Start next frame in a packed buffer at this boundary. 137 * -1: driver should figure out a good value. 138 * T4: driver will ignore this and use the same value as fl_pad above. 139 * T5: 16, or a power of 2 from 64 to 4096 (both inclusive) is a valid value. 140 */ 141 static int fl_pack = -1; 142 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pack, CTLFLAG_RDTUN, &fl_pack, 0, 143 "payload pack boundary (bytes)"); 144 145 /* 146 * Allow the driver to create mbuf(s) in a cluster allocated for rx. 147 * 0: never; always allocate mbufs from the zone_mbuf UMA zone. 148 * 1: ok to create mbuf(s) within a cluster if there is room. 149 */ 150 static int allow_mbufs_in_cluster = 1; 151 SYSCTL_INT(_hw_cxgbe, OID_AUTO, allow_mbufs_in_cluster, CTLFLAG_RDTUN, 152 &allow_mbufs_in_cluster, 0, 153 "Allow driver to create mbufs within a rx cluster"); 154 155 /* 156 * Largest rx cluster size that the driver is allowed to allocate. 157 */ 158 static int largest_rx_cluster = MJUM16BYTES; 159 SYSCTL_INT(_hw_cxgbe, OID_AUTO, largest_rx_cluster, CTLFLAG_RDTUN, 160 &largest_rx_cluster, 0, "Largest rx cluster (bytes)"); 161 162 /* 163 * Size of cluster allocation that's most likely to succeed. The driver will 164 * fall back to this size if it fails to allocate clusters larger than this. 165 */ 166 static int safest_rx_cluster = PAGE_SIZE; 167 SYSCTL_INT(_hw_cxgbe, OID_AUTO, safest_rx_cluster, CTLFLAG_RDTUN, 168 &safest_rx_cluster, 0, "Safe rx cluster (bytes)"); 169 170 #ifdef RATELIMIT 171 /* 172 * Knob to control TCP timestamp rewriting, and the granularity of the tick used 173 * for rewriting. -1 and 0-3 are all valid values. 174 * -1: hardware should leave the TCP timestamps alone. 175 * 0: 1ms 176 * 1: 100us 177 * 2: 10us 178 * 3: 1us 179 */ 180 static int tsclk = -1; 181 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tsclk, CTLFLAG_RDTUN, &tsclk, 0, 182 "Control TCP timestamp rewriting when using pacing"); 183 184 static int eo_max_backlog = 1024 * 1024; 185 SYSCTL_INT(_hw_cxgbe, OID_AUTO, eo_max_backlog, CTLFLAG_RDTUN, &eo_max_backlog, 186 0, "Maximum backlog of ratelimited data per flow"); 187 #endif 188 189 /* 190 * The interrupt holdoff timers are multiplied by this value on T6+. 191 * 1 and 3-17 (both inclusive) are legal values. 192 */ 193 static int tscale = 1; 194 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tscale, CTLFLAG_RDTUN, &tscale, 0, 195 "Interrupt holdoff timer scale on T6+"); 196 197 /* 198 * Number of LRO entries in the lro_ctrl structure per rx queue. 199 */ 200 static int lro_entries = TCP_LRO_ENTRIES; 201 SYSCTL_INT(_hw_cxgbe, OID_AUTO, lro_entries, CTLFLAG_RDTUN, &lro_entries, 0, 202 "Number of LRO entries per RX queue"); 203 204 /* 205 * This enables presorting of frames before they're fed into tcp_lro_rx. 206 */ 207 static int lro_mbufs = 0; 208 SYSCTL_INT(_hw_cxgbe, OID_AUTO, lro_mbufs, CTLFLAG_RDTUN, &lro_mbufs, 0, 209 "Enable presorting of LRO frames"); 210 211 struct txpkts { 212 u_int wr_type; /* type 0 or type 1 */ 213 u_int npkt; /* # of packets in this work request */ 214 u_int plen; /* total payload (sum of all packets) */ 215 u_int len16; /* # of 16B pieces used by this work request */ 216 }; 217 218 /* A packet's SGL. This + m_pkthdr has all info needed for tx */ 219 struct sgl { 220 struct sglist sg; 221 struct sglist_seg seg[TX_SGL_SEGS]; 222 }; 223 224 static int service_iq(struct sge_iq *, int); 225 static int service_iq_fl(struct sge_iq *, int); 226 static struct mbuf *get_fl_payload(struct adapter *, struct sge_fl *, uint32_t); 227 static int t4_eth_rx(struct sge_iq *, const struct rss_header *, struct mbuf *); 228 static inline void init_iq(struct sge_iq *, struct adapter *, int, int, int); 229 static inline void init_fl(struct adapter *, struct sge_fl *, int, int, char *); 230 static inline void init_eq(struct adapter *, struct sge_eq *, int, int, uint8_t, 231 uint16_t, char *); 232 static int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *, 233 bus_addr_t *, void **); 234 static int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 235 void *); 236 static int alloc_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *, 237 int, int); 238 static int free_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *); 239 static void add_iq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *, 240 struct sge_iq *); 241 static void add_fl_sysctls(struct adapter *, struct sysctl_ctx_list *, 242 struct sysctl_oid *, struct sge_fl *); 243 static int alloc_fwq(struct adapter *); 244 static int free_fwq(struct adapter *); 245 static int alloc_ctrlq(struct adapter *, struct sge_wrq *, int, 246 struct sysctl_oid *); 247 static int alloc_rxq(struct vi_info *, struct sge_rxq *, int, int, 248 struct sysctl_oid *); 249 static int free_rxq(struct vi_info *, struct sge_rxq *); 250 #ifdef TCP_OFFLOAD 251 static int alloc_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *, int, int, 252 struct sysctl_oid *); 253 static int free_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *); 254 #endif 255 #ifdef DEV_NETMAP 256 static int alloc_nm_rxq(struct vi_info *, struct sge_nm_rxq *, int, int, 257 struct sysctl_oid *); 258 static int free_nm_rxq(struct vi_info *, struct sge_nm_rxq *); 259 static int alloc_nm_txq(struct vi_info *, struct sge_nm_txq *, int, int, 260 struct sysctl_oid *); 261 static int free_nm_txq(struct vi_info *, struct sge_nm_txq *); 262 #endif 263 static int ctrl_eq_alloc(struct adapter *, struct sge_eq *); 264 static int eth_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *); 265 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 266 static int ofld_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *); 267 #endif 268 static int alloc_eq(struct adapter *, struct vi_info *, struct sge_eq *); 269 static int free_eq(struct adapter *, struct sge_eq *); 270 static int alloc_wrq(struct adapter *, struct vi_info *, struct sge_wrq *, 271 struct sysctl_oid *); 272 static int free_wrq(struct adapter *, struct sge_wrq *); 273 static int alloc_txq(struct vi_info *, struct sge_txq *, int, 274 struct sysctl_oid *); 275 static int free_txq(struct vi_info *, struct sge_txq *); 276 static void oneseg_dma_callback(void *, bus_dma_segment_t *, int, int); 277 static inline void ring_fl_db(struct adapter *, struct sge_fl *); 278 static int refill_fl(struct adapter *, struct sge_fl *, int); 279 static void refill_sfl(void *); 280 static int alloc_fl_sdesc(struct sge_fl *); 281 static void free_fl_sdesc(struct adapter *, struct sge_fl *); 282 static void find_best_refill_source(struct adapter *, struct sge_fl *, int); 283 static void find_safe_refill_source(struct adapter *, struct sge_fl *); 284 static void add_fl_to_sfl(struct adapter *, struct sge_fl *); 285 286 static inline void get_pkt_gl(struct mbuf *, struct sglist *); 287 static inline u_int txpkt_len16(u_int, u_int); 288 static inline u_int txpkt_vm_len16(u_int, u_int); 289 static inline u_int txpkts0_len16(u_int); 290 static inline u_int txpkts1_len16(void); 291 static u_int write_raw_wr(struct sge_txq *, void *, struct mbuf *, u_int); 292 static u_int write_txpkt_wr(struct sge_txq *, struct fw_eth_tx_pkt_wr *, 293 struct mbuf *, u_int); 294 static u_int write_txpkt_vm_wr(struct adapter *, struct sge_txq *, 295 struct fw_eth_tx_pkt_vm_wr *, struct mbuf *, u_int); 296 static int try_txpkts(struct mbuf *, struct mbuf *, struct txpkts *, u_int); 297 static int add_to_txpkts(struct mbuf *, struct txpkts *, u_int); 298 static u_int write_txpkts_wr(struct sge_txq *, struct fw_eth_tx_pkts_wr *, 299 struct mbuf *, const struct txpkts *, u_int); 300 static void write_gl_to_txd(struct sge_txq *, struct mbuf *, caddr_t *, int); 301 static inline void copy_to_txd(struct sge_eq *, caddr_t, caddr_t *, int); 302 static inline void ring_eq_db(struct adapter *, struct sge_eq *, u_int); 303 static inline uint16_t read_hw_cidx(struct sge_eq *); 304 static inline u_int reclaimable_tx_desc(struct sge_eq *); 305 static inline u_int total_available_tx_desc(struct sge_eq *); 306 static u_int reclaim_tx_descs(struct sge_txq *, u_int); 307 static void tx_reclaim(void *, int); 308 static __be64 get_flit(struct sglist_seg *, int, int); 309 static int handle_sge_egr_update(struct sge_iq *, const struct rss_header *, 310 struct mbuf *); 311 static int handle_fw_msg(struct sge_iq *, const struct rss_header *, 312 struct mbuf *); 313 static int t4_handle_wrerr_rpl(struct adapter *, const __be64 *); 314 static void wrq_tx_drain(void *, int); 315 static void drain_wrq_wr_list(struct adapter *, struct sge_wrq *); 316 317 static int sysctl_uint16(SYSCTL_HANDLER_ARGS); 318 static int sysctl_bufsizes(SYSCTL_HANDLER_ARGS); 319 #ifdef RATELIMIT 320 static inline u_int txpkt_eo_len16(u_int, u_int, u_int); 321 static int ethofld_fw4_ack(struct sge_iq *, const struct rss_header *, 322 struct mbuf *); 323 #endif 324 325 static counter_u64_t extfree_refs; 326 static counter_u64_t extfree_rels; 327 328 an_handler_t t4_an_handler; 329 fw_msg_handler_t t4_fw_msg_handler[NUM_FW6_TYPES]; 330 cpl_handler_t t4_cpl_handler[NUM_CPL_CMDS]; 331 cpl_handler_t set_tcb_rpl_handlers[NUM_CPL_COOKIES]; 332 cpl_handler_t l2t_write_rpl_handlers[NUM_CPL_COOKIES]; 333 cpl_handler_t act_open_rpl_handlers[NUM_CPL_COOKIES]; 334 cpl_handler_t abort_rpl_rss_handlers[NUM_CPL_COOKIES]; 335 cpl_handler_t fw4_ack_handlers[NUM_CPL_COOKIES]; 336 337 void 338 t4_register_an_handler(an_handler_t h) 339 { 340 uintptr_t *loc; 341 342 MPASS(h == NULL || t4_an_handler == NULL); 343 344 loc = (uintptr_t *)&t4_an_handler; 345 atomic_store_rel_ptr(loc, (uintptr_t)h); 346 } 347 348 void 349 t4_register_fw_msg_handler(int type, fw_msg_handler_t h) 350 { 351 uintptr_t *loc; 352 353 MPASS(type < nitems(t4_fw_msg_handler)); 354 MPASS(h == NULL || t4_fw_msg_handler[type] == NULL); 355 /* 356 * These are dispatched by the handler for FW{4|6}_CPL_MSG using the CPL 357 * handler dispatch table. Reject any attempt to install a handler for 358 * this subtype. 359 */ 360 MPASS(type != FW_TYPE_RSSCPL); 361 MPASS(type != FW6_TYPE_RSSCPL); 362 363 loc = (uintptr_t *)&t4_fw_msg_handler[type]; 364 atomic_store_rel_ptr(loc, (uintptr_t)h); 365 } 366 367 void 368 t4_register_cpl_handler(int opcode, cpl_handler_t h) 369 { 370 uintptr_t *loc; 371 372 MPASS(opcode < nitems(t4_cpl_handler)); 373 MPASS(h == NULL || t4_cpl_handler[opcode] == NULL); 374 375 loc = (uintptr_t *)&t4_cpl_handler[opcode]; 376 atomic_store_rel_ptr(loc, (uintptr_t)h); 377 } 378 379 static int 380 set_tcb_rpl_handler(struct sge_iq *iq, const struct rss_header *rss, 381 struct mbuf *m) 382 { 383 const struct cpl_set_tcb_rpl *cpl = (const void *)(rss + 1); 384 u_int tid; 385 int cookie; 386 387 MPASS(m == NULL); 388 389 tid = GET_TID(cpl); 390 if (is_hpftid(iq->adapter, tid) || is_ftid(iq->adapter, tid)) { 391 /* 392 * The return code for filter-write is put in the CPL cookie so 393 * we have to rely on the hardware tid (is_ftid) to determine 394 * that this is a response to a filter. 395 */ 396 cookie = CPL_COOKIE_FILTER; 397 } else { 398 cookie = G_COOKIE(cpl->cookie); 399 } 400 MPASS(cookie > CPL_COOKIE_RESERVED); 401 MPASS(cookie < nitems(set_tcb_rpl_handlers)); 402 403 return (set_tcb_rpl_handlers[cookie](iq, rss, m)); 404 } 405 406 static int 407 l2t_write_rpl_handler(struct sge_iq *iq, const struct rss_header *rss, 408 struct mbuf *m) 409 { 410 const struct cpl_l2t_write_rpl *rpl = (const void *)(rss + 1); 411 unsigned int cookie; 412 413 MPASS(m == NULL); 414 415 cookie = GET_TID(rpl) & F_SYNC_WR ? CPL_COOKIE_TOM : CPL_COOKIE_FILTER; 416 return (l2t_write_rpl_handlers[cookie](iq, rss, m)); 417 } 418 419 static int 420 act_open_rpl_handler(struct sge_iq *iq, const struct rss_header *rss, 421 struct mbuf *m) 422 { 423 const struct cpl_act_open_rpl *cpl = (const void *)(rss + 1); 424 u_int cookie = G_TID_COOKIE(G_AOPEN_ATID(be32toh(cpl->atid_status))); 425 426 MPASS(m == NULL); 427 MPASS(cookie != CPL_COOKIE_RESERVED); 428 429 return (act_open_rpl_handlers[cookie](iq, rss, m)); 430 } 431 432 static int 433 abort_rpl_rss_handler(struct sge_iq *iq, const struct rss_header *rss, 434 struct mbuf *m) 435 { 436 struct adapter *sc = iq->adapter; 437 u_int cookie; 438 439 MPASS(m == NULL); 440 if (is_hashfilter(sc)) 441 cookie = CPL_COOKIE_HASHFILTER; 442 else 443 cookie = CPL_COOKIE_TOM; 444 445 return (abort_rpl_rss_handlers[cookie](iq, rss, m)); 446 } 447 448 static int 449 fw4_ack_handler(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 450 { 451 struct adapter *sc = iq->adapter; 452 const struct cpl_fw4_ack *cpl = (const void *)(rss + 1); 453 unsigned int tid = G_CPL_FW4_ACK_FLOWID(be32toh(OPCODE_TID(cpl))); 454 u_int cookie; 455 456 MPASS(m == NULL); 457 if (is_etid(sc, tid)) 458 cookie = CPL_COOKIE_ETHOFLD; 459 else 460 cookie = CPL_COOKIE_TOM; 461 462 return (fw4_ack_handlers[cookie](iq, rss, m)); 463 } 464 465 static void 466 t4_init_shared_cpl_handlers(void) 467 { 468 469 t4_register_cpl_handler(CPL_SET_TCB_RPL, set_tcb_rpl_handler); 470 t4_register_cpl_handler(CPL_L2T_WRITE_RPL, l2t_write_rpl_handler); 471 t4_register_cpl_handler(CPL_ACT_OPEN_RPL, act_open_rpl_handler); 472 t4_register_cpl_handler(CPL_ABORT_RPL_RSS, abort_rpl_rss_handler); 473 t4_register_cpl_handler(CPL_FW4_ACK, fw4_ack_handler); 474 } 475 476 void 477 t4_register_shared_cpl_handler(int opcode, cpl_handler_t h, int cookie) 478 { 479 uintptr_t *loc; 480 481 MPASS(opcode < nitems(t4_cpl_handler)); 482 MPASS(cookie > CPL_COOKIE_RESERVED); 483 MPASS(cookie < NUM_CPL_COOKIES); 484 MPASS(t4_cpl_handler[opcode] != NULL); 485 486 switch (opcode) { 487 case CPL_SET_TCB_RPL: 488 loc = (uintptr_t *)&set_tcb_rpl_handlers[cookie]; 489 break; 490 case CPL_L2T_WRITE_RPL: 491 loc = (uintptr_t *)&l2t_write_rpl_handlers[cookie]; 492 break; 493 case CPL_ACT_OPEN_RPL: 494 loc = (uintptr_t *)&act_open_rpl_handlers[cookie]; 495 break; 496 case CPL_ABORT_RPL_RSS: 497 loc = (uintptr_t *)&abort_rpl_rss_handlers[cookie]; 498 break; 499 case CPL_FW4_ACK: 500 loc = (uintptr_t *)&fw4_ack_handlers[cookie]; 501 break; 502 default: 503 MPASS(0); 504 return; 505 } 506 MPASS(h == NULL || *loc == (uintptr_t)NULL); 507 atomic_store_rel_ptr(loc, (uintptr_t)h); 508 } 509 510 /* 511 * Called on MOD_LOAD. Validates and calculates the SGE tunables. 512 */ 513 void 514 t4_sge_modload(void) 515 { 516 517 if (fl_pktshift < 0 || fl_pktshift > 7) { 518 printf("Invalid hw.cxgbe.fl_pktshift value (%d)," 519 " using 0 instead.\n", fl_pktshift); 520 fl_pktshift = 0; 521 } 522 523 if (spg_len != 64 && spg_len != 128) { 524 int len; 525 526 #if defined(__i386__) || defined(__amd64__) 527 len = cpu_clflush_line_size > 64 ? 128 : 64; 528 #else 529 len = 64; 530 #endif 531 if (spg_len != -1) { 532 printf("Invalid hw.cxgbe.spg_len value (%d)," 533 " using %d instead.\n", spg_len, len); 534 } 535 spg_len = len; 536 } 537 538 if (cong_drop < -1 || cong_drop > 1) { 539 printf("Invalid hw.cxgbe.cong_drop value (%d)," 540 " using 0 instead.\n", cong_drop); 541 cong_drop = 0; 542 } 543 544 if (tscale != 1 && (tscale < 3 || tscale > 17)) { 545 printf("Invalid hw.cxgbe.tscale value (%d)," 546 " using 1 instead.\n", tscale); 547 tscale = 1; 548 } 549 550 extfree_refs = counter_u64_alloc(M_WAITOK); 551 extfree_rels = counter_u64_alloc(M_WAITOK); 552 counter_u64_zero(extfree_refs); 553 counter_u64_zero(extfree_rels); 554 555 t4_init_shared_cpl_handlers(); 556 t4_register_cpl_handler(CPL_FW4_MSG, handle_fw_msg); 557 t4_register_cpl_handler(CPL_FW6_MSG, handle_fw_msg); 558 t4_register_cpl_handler(CPL_SGE_EGR_UPDATE, handle_sge_egr_update); 559 t4_register_cpl_handler(CPL_RX_PKT, t4_eth_rx); 560 #ifdef RATELIMIT 561 t4_register_shared_cpl_handler(CPL_FW4_ACK, ethofld_fw4_ack, 562 CPL_COOKIE_ETHOFLD); 563 #endif 564 t4_register_fw_msg_handler(FW6_TYPE_CMD_RPL, t4_handle_fw_rpl); 565 t4_register_fw_msg_handler(FW6_TYPE_WRERR_RPL, t4_handle_wrerr_rpl); 566 } 567 568 void 569 t4_sge_modunload(void) 570 { 571 572 counter_u64_free(extfree_refs); 573 counter_u64_free(extfree_rels); 574 } 575 576 uint64_t 577 t4_sge_extfree_refs(void) 578 { 579 uint64_t refs, rels; 580 581 rels = counter_u64_fetch(extfree_rels); 582 refs = counter_u64_fetch(extfree_refs); 583 584 return (refs - rels); 585 } 586 587 static inline void 588 setup_pad_and_pack_boundaries(struct adapter *sc) 589 { 590 uint32_t v, m; 591 int pad, pack, pad_shift; 592 593 pad_shift = chip_id(sc) > CHELSIO_T5 ? X_T6_INGPADBOUNDARY_SHIFT : 594 X_INGPADBOUNDARY_SHIFT; 595 pad = fl_pad; 596 if (fl_pad < (1 << pad_shift) || 597 fl_pad > (1 << (pad_shift + M_INGPADBOUNDARY)) || 598 !powerof2(fl_pad)) { 599 /* 600 * If there is any chance that we might use buffer packing and 601 * the chip is a T4, then pick 64 as the pad/pack boundary. Set 602 * it to the minimum allowed in all other cases. 603 */ 604 pad = is_t4(sc) && buffer_packing ? 64 : 1 << pad_shift; 605 606 /* 607 * For fl_pad = 0 we'll still write a reasonable value to the 608 * register but all the freelists will opt out of padding. 609 * We'll complain here only if the user tried to set it to a 610 * value greater than 0 that was invalid. 611 */ 612 if (fl_pad > 0) { 613 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pad value" 614 " (%d), using %d instead.\n", fl_pad, pad); 615 } 616 } 617 m = V_INGPADBOUNDARY(M_INGPADBOUNDARY); 618 v = V_INGPADBOUNDARY(ilog2(pad) - pad_shift); 619 t4_set_reg_field(sc, A_SGE_CONTROL, m, v); 620 621 if (is_t4(sc)) { 622 if (fl_pack != -1 && fl_pack != pad) { 623 /* Complain but carry on. */ 624 device_printf(sc->dev, "hw.cxgbe.fl_pack (%d) ignored," 625 " using %d instead.\n", fl_pack, pad); 626 } 627 return; 628 } 629 630 pack = fl_pack; 631 if (fl_pack < 16 || fl_pack == 32 || fl_pack > 4096 || 632 !powerof2(fl_pack)) { 633 pack = max(sc->params.pci.mps, CACHE_LINE_SIZE); 634 MPASS(powerof2(pack)); 635 if (pack < 16) 636 pack = 16; 637 if (pack == 32) 638 pack = 64; 639 if (pack > 4096) 640 pack = 4096; 641 if (fl_pack != -1) { 642 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pack value" 643 " (%d), using %d instead.\n", fl_pack, pack); 644 } 645 } 646 m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY); 647 if (pack == 16) 648 v = V_INGPACKBOUNDARY(0); 649 else 650 v = V_INGPACKBOUNDARY(ilog2(pack) - 5); 651 652 MPASS(!is_t4(sc)); /* T4 doesn't have SGE_CONTROL2 */ 653 t4_set_reg_field(sc, A_SGE_CONTROL2, m, v); 654 } 655 656 /* 657 * adap->params.vpd.cclk must be set up before this is called. 658 */ 659 void 660 t4_tweak_chip_settings(struct adapter *sc) 661 { 662 int i; 663 uint32_t v, m; 664 int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200}; 665 int timer_max = M_TIMERVALUE0 * 1000 / sc->params.vpd.cclk; 666 int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */ 667 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 668 static int sge_flbuf_sizes[] = { 669 MCLBYTES, 670 #if MJUMPAGESIZE != MCLBYTES 671 MJUMPAGESIZE, 672 MJUMPAGESIZE - CL_METADATA_SIZE, 673 MJUMPAGESIZE - 2 * MSIZE - CL_METADATA_SIZE, 674 #endif 675 MJUM9BYTES, 676 MJUM16BYTES, 677 MCLBYTES - MSIZE - CL_METADATA_SIZE, 678 MJUM9BYTES - CL_METADATA_SIZE, 679 MJUM16BYTES - CL_METADATA_SIZE, 680 }; 681 682 KASSERT(sc->flags & MASTER_PF, 683 ("%s: trying to change chip settings when not master.", __func__)); 684 685 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE; 686 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE | 687 V_EGRSTATUSPAGESIZE(spg_len == 128); 688 t4_set_reg_field(sc, A_SGE_CONTROL, m, v); 689 690 setup_pad_and_pack_boundaries(sc); 691 692 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) | 693 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) | 694 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) | 695 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) | 696 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) | 697 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) | 698 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) | 699 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10); 700 t4_write_reg(sc, A_SGE_HOST_PAGE_SIZE, v); 701 702 KASSERT(nitems(sge_flbuf_sizes) <= SGE_FLBUF_SIZES, 703 ("%s: hw buffer size table too big", __func__)); 704 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0, 4096); 705 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE1, 65536); 706 for (i = 0; i < min(nitems(sge_flbuf_sizes), SGE_FLBUF_SIZES); i++) { 707 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE15 - (4 * i), 708 sge_flbuf_sizes[i]); 709 } 710 711 v = V_THRESHOLD_0(intr_pktcount[0]) | V_THRESHOLD_1(intr_pktcount[1]) | 712 V_THRESHOLD_2(intr_pktcount[2]) | V_THRESHOLD_3(intr_pktcount[3]); 713 t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD, v); 714 715 KASSERT(intr_timer[0] <= timer_max, 716 ("%s: not a single usable timer (%d, %d)", __func__, intr_timer[0], 717 timer_max)); 718 for (i = 1; i < nitems(intr_timer); i++) { 719 KASSERT(intr_timer[i] >= intr_timer[i - 1], 720 ("%s: timers not listed in increasing order (%d)", 721 __func__, i)); 722 723 while (intr_timer[i] > timer_max) { 724 if (i == nitems(intr_timer) - 1) { 725 intr_timer[i] = timer_max; 726 break; 727 } 728 intr_timer[i] += intr_timer[i - 1]; 729 intr_timer[i] /= 2; 730 } 731 } 732 733 v = V_TIMERVALUE0(us_to_core_ticks(sc, intr_timer[0])) | 734 V_TIMERVALUE1(us_to_core_ticks(sc, intr_timer[1])); 735 t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1, v); 736 v = V_TIMERVALUE2(us_to_core_ticks(sc, intr_timer[2])) | 737 V_TIMERVALUE3(us_to_core_ticks(sc, intr_timer[3])); 738 t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3, v); 739 v = V_TIMERVALUE4(us_to_core_ticks(sc, intr_timer[4])) | 740 V_TIMERVALUE5(us_to_core_ticks(sc, intr_timer[5])); 741 t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5, v); 742 743 if (chip_id(sc) >= CHELSIO_T6) { 744 m = V_TSCALE(M_TSCALE); 745 if (tscale == 1) 746 v = 0; 747 else 748 v = V_TSCALE(tscale - 2); 749 t4_set_reg_field(sc, A_SGE_ITP_CONTROL, m, v); 750 751 if (sc->debug_flags & DF_DISABLE_TCB_CACHE) { 752 m = V_RDTHRESHOLD(M_RDTHRESHOLD) | F_WRTHRTHRESHEN | 753 V_WRTHRTHRESH(M_WRTHRTHRESH); 754 t4_tp_pio_read(sc, &v, 1, A_TP_CMM_CONFIG, 1); 755 v &= ~m; 756 v |= V_RDTHRESHOLD(1) | F_WRTHRTHRESHEN | 757 V_WRTHRTHRESH(16); 758 t4_tp_pio_write(sc, &v, 1, A_TP_CMM_CONFIG, 1); 759 } 760 } 761 762 /* 4K, 16K, 64K, 256K DDP "page sizes" for TDDP */ 763 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 764 t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, v); 765 766 /* 767 * 4K, 8K, 16K, 64K DDP "page sizes" for iSCSI DDP. These have been 768 * chosen with MAXPHYS = 128K in mind. The largest DDP buffer that we 769 * may have to deal with is MAXPHYS + 1 page. 770 */ 771 v = V_HPZ0(0) | V_HPZ1(1) | V_HPZ2(2) | V_HPZ3(4); 772 t4_write_reg(sc, A_ULP_RX_ISCSI_PSZ, v); 773 774 /* We use multiple DDP page sizes both in plain-TOE and ISCSI modes. */ 775 m = v = F_TDDPTAGTCB | F_ISCSITAGTCB; 776 t4_set_reg_field(sc, A_ULP_RX_CTL, m, v); 777 778 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 779 F_RESETDDPOFFSET; 780 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 781 t4_set_reg_field(sc, A_TP_PARA_REG5, m, v); 782 } 783 784 /* 785 * SGE wants the buffer to be at least 64B and then a multiple of 16. If 786 * padding is in use, the buffer's start and end need to be aligned to the pad 787 * boundary as well. We'll just make sure that the size is a multiple of the 788 * boundary here, it is up to the buffer allocation code to make sure the start 789 * of the buffer is aligned as well. 790 */ 791 static inline int 792 hwsz_ok(struct adapter *sc, int hwsz) 793 { 794 int mask = fl_pad ? sc->params.sge.pad_boundary - 1 : 16 - 1; 795 796 return (hwsz >= 64 && (hwsz & mask) == 0); 797 } 798 799 /* 800 * XXX: driver really should be able to deal with unexpected settings. 801 */ 802 int 803 t4_read_chip_settings(struct adapter *sc) 804 { 805 struct sge *s = &sc->sge; 806 struct sge_params *sp = &sc->params.sge; 807 int i, j, n, rc = 0; 808 uint32_t m, v, r; 809 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 810 static int sw_buf_sizes[] = { /* Sorted by size */ 811 MCLBYTES, 812 #if MJUMPAGESIZE != MCLBYTES 813 MJUMPAGESIZE, 814 #endif 815 MJUM9BYTES, 816 MJUM16BYTES 817 }; 818 struct sw_zone_info *swz, *safe_swz; 819 struct hw_buf_info *hwb; 820 821 m = F_RXPKTCPLMODE; 822 v = F_RXPKTCPLMODE; 823 r = sc->params.sge.sge_control; 824 if ((r & m) != v) { 825 device_printf(sc->dev, "invalid SGE_CONTROL(0x%x)\n", r); 826 rc = EINVAL; 827 } 828 829 /* 830 * If this changes then every single use of PAGE_SHIFT in the driver 831 * needs to be carefully reviewed for PAGE_SHIFT vs sp->page_shift. 832 */ 833 if (sp->page_shift != PAGE_SHIFT) { 834 device_printf(sc->dev, "invalid SGE_HOST_PAGE_SIZE(0x%x)\n", r); 835 rc = EINVAL; 836 } 837 838 /* Filter out unusable hw buffer sizes entirely (mark with -2). */ 839 hwb = &s->hw_buf_info[0]; 840 for (i = 0; i < nitems(s->hw_buf_info); i++, hwb++) { 841 r = sc->params.sge.sge_fl_buffer_size[i]; 842 hwb->size = r; 843 hwb->zidx = hwsz_ok(sc, r) ? -1 : -2; 844 hwb->next = -1; 845 } 846 847 /* 848 * Create a sorted list in decreasing order of hw buffer sizes (and so 849 * increasing order of spare area) for each software zone. 850 * 851 * If padding is enabled then the start and end of the buffer must align 852 * to the pad boundary; if packing is enabled then they must align with 853 * the pack boundary as well. Allocations from the cluster zones are 854 * aligned to min(size, 4K), so the buffer starts at that alignment and 855 * ends at hwb->size alignment. If mbuf inlining is allowed the 856 * starting alignment will be reduced to MSIZE and the driver will 857 * exercise appropriate caution when deciding on the best buffer layout 858 * to use. 859 */ 860 n = 0; /* no usable buffer size to begin with */ 861 swz = &s->sw_zone_info[0]; 862 safe_swz = NULL; 863 for (i = 0; i < SW_ZONE_SIZES; i++, swz++) { 864 int8_t head = -1, tail = -1; 865 866 swz->size = sw_buf_sizes[i]; 867 swz->zone = m_getzone(swz->size); 868 swz->type = m_gettype(swz->size); 869 870 if (swz->size < PAGE_SIZE) { 871 MPASS(powerof2(swz->size)); 872 if (fl_pad && (swz->size % sp->pad_boundary != 0)) 873 continue; 874 } 875 876 if (swz->size == safest_rx_cluster) 877 safe_swz = swz; 878 879 hwb = &s->hw_buf_info[0]; 880 for (j = 0; j < SGE_FLBUF_SIZES; j++, hwb++) { 881 if (hwb->zidx != -1 || hwb->size > swz->size) 882 continue; 883 #ifdef INVARIANTS 884 if (fl_pad) 885 MPASS(hwb->size % sp->pad_boundary == 0); 886 #endif 887 hwb->zidx = i; 888 if (head == -1) 889 head = tail = j; 890 else if (hwb->size < s->hw_buf_info[tail].size) { 891 s->hw_buf_info[tail].next = j; 892 tail = j; 893 } else { 894 int8_t *cur; 895 struct hw_buf_info *t; 896 897 for (cur = &head; *cur != -1; cur = &t->next) { 898 t = &s->hw_buf_info[*cur]; 899 if (hwb->size == t->size) { 900 hwb->zidx = -2; 901 break; 902 } 903 if (hwb->size > t->size) { 904 hwb->next = *cur; 905 *cur = j; 906 break; 907 } 908 } 909 } 910 } 911 swz->head_hwidx = head; 912 swz->tail_hwidx = tail; 913 914 if (tail != -1) { 915 n++; 916 if (swz->size - s->hw_buf_info[tail].size >= 917 CL_METADATA_SIZE) 918 sc->flags |= BUF_PACKING_OK; 919 } 920 } 921 if (n == 0) { 922 device_printf(sc->dev, "no usable SGE FL buffer size.\n"); 923 rc = EINVAL; 924 } 925 926 s->safe_hwidx1 = -1; 927 s->safe_hwidx2 = -1; 928 if (safe_swz != NULL) { 929 s->safe_hwidx1 = safe_swz->head_hwidx; 930 for (i = safe_swz->head_hwidx; i != -1; i = hwb->next) { 931 int spare; 932 933 hwb = &s->hw_buf_info[i]; 934 #ifdef INVARIANTS 935 if (fl_pad) 936 MPASS(hwb->size % sp->pad_boundary == 0); 937 #endif 938 spare = safe_swz->size - hwb->size; 939 if (spare >= CL_METADATA_SIZE) { 940 s->safe_hwidx2 = i; 941 break; 942 } 943 } 944 } 945 946 if (sc->flags & IS_VF) 947 return (0); 948 949 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 950 r = t4_read_reg(sc, A_ULP_RX_TDDP_PSZ); 951 if (r != v) { 952 device_printf(sc->dev, "invalid ULP_RX_TDDP_PSZ(0x%x)\n", r); 953 rc = EINVAL; 954 } 955 956 m = v = F_TDDPTAGTCB; 957 r = t4_read_reg(sc, A_ULP_RX_CTL); 958 if ((r & m) != v) { 959 device_printf(sc->dev, "invalid ULP_RX_CTL(0x%x)\n", r); 960 rc = EINVAL; 961 } 962 963 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 964 F_RESETDDPOFFSET; 965 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 966 r = t4_read_reg(sc, A_TP_PARA_REG5); 967 if ((r & m) != v) { 968 device_printf(sc->dev, "invalid TP_PARA_REG5(0x%x)\n", r); 969 rc = EINVAL; 970 } 971 972 t4_init_tp_params(sc, 1); 973 974 t4_read_mtu_tbl(sc, sc->params.mtus, NULL); 975 t4_load_mtus(sc, sc->params.mtus, sc->params.a_wnd, sc->params.b_wnd); 976 977 return (rc); 978 } 979 980 int 981 t4_create_dma_tag(struct adapter *sc) 982 { 983 int rc; 984 985 rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0, 986 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE, 987 BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL, 988 NULL, &sc->dmat); 989 if (rc != 0) { 990 device_printf(sc->dev, 991 "failed to create main DMA tag: %d\n", rc); 992 } 993 994 return (rc); 995 } 996 997 void 998 t4_sge_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx, 999 struct sysctl_oid_list *children) 1000 { 1001 struct sge_params *sp = &sc->params.sge; 1002 1003 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "buffer_sizes", 1004 CTLTYPE_STRING | CTLFLAG_RD, &sc->sge, 0, sysctl_bufsizes, "A", 1005 "freelist buffer sizes"); 1006 1007 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pktshift", CTLFLAG_RD, 1008 NULL, sp->fl_pktshift, "payload DMA offset in rx buffer (bytes)"); 1009 1010 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pad", CTLFLAG_RD, 1011 NULL, sp->pad_boundary, "payload pad boundary (bytes)"); 1012 1013 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "spg_len", CTLFLAG_RD, 1014 NULL, sp->spg_len, "status page size (bytes)"); 1015 1016 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_drop", CTLFLAG_RD, 1017 NULL, cong_drop, "congestion drop setting"); 1018 1019 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pack", CTLFLAG_RD, 1020 NULL, sp->pack_boundary, "payload pack boundary (bytes)"); 1021 } 1022 1023 int 1024 t4_destroy_dma_tag(struct adapter *sc) 1025 { 1026 if (sc->dmat) 1027 bus_dma_tag_destroy(sc->dmat); 1028 1029 return (0); 1030 } 1031 1032 /* 1033 * Allocate and initialize the firmware event queue, control queues, and special 1034 * purpose rx queues owned by the adapter. 1035 * 1036 * Returns errno on failure. Resources allocated up to that point may still be 1037 * allocated. Caller is responsible for cleanup in case this function fails. 1038 */ 1039 int 1040 t4_setup_adapter_queues(struct adapter *sc) 1041 { 1042 struct sysctl_oid *oid; 1043 struct sysctl_oid_list *children; 1044 int rc, i; 1045 1046 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 1047 1048 sysctl_ctx_init(&sc->ctx); 1049 sc->flags |= ADAP_SYSCTL_CTX; 1050 1051 /* 1052 * Firmware event queue 1053 */ 1054 rc = alloc_fwq(sc); 1055 if (rc != 0) 1056 return (rc); 1057 1058 /* 1059 * That's all for the VF driver. 1060 */ 1061 if (sc->flags & IS_VF) 1062 return (rc); 1063 1064 oid = device_get_sysctl_tree(sc->dev); 1065 children = SYSCTL_CHILDREN(oid); 1066 1067 /* 1068 * XXX: General purpose rx queues, one per port. 1069 */ 1070 1071 /* 1072 * Control queues, one per port. 1073 */ 1074 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "ctrlq", 1075 CTLFLAG_RD, NULL, "control queues"); 1076 for_each_port(sc, i) { 1077 struct sge_wrq *ctrlq = &sc->sge.ctrlq[i]; 1078 1079 rc = alloc_ctrlq(sc, ctrlq, i, oid); 1080 if (rc != 0) 1081 return (rc); 1082 } 1083 1084 return (rc); 1085 } 1086 1087 /* 1088 * Idempotent 1089 */ 1090 int 1091 t4_teardown_adapter_queues(struct adapter *sc) 1092 { 1093 int i; 1094 1095 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 1096 1097 /* Do this before freeing the queue */ 1098 if (sc->flags & ADAP_SYSCTL_CTX) { 1099 sysctl_ctx_free(&sc->ctx); 1100 sc->flags &= ~ADAP_SYSCTL_CTX; 1101 } 1102 1103 if (!(sc->flags & IS_VF)) { 1104 for_each_port(sc, i) 1105 free_wrq(sc, &sc->sge.ctrlq[i]); 1106 } 1107 free_fwq(sc); 1108 1109 return (0); 1110 } 1111 1112 /* Maximum payload that can be delivered with a single iq descriptor */ 1113 static inline int 1114 mtu_to_max_payload(struct adapter *sc, int mtu, const int toe) 1115 { 1116 int payload; 1117 1118 #ifdef TCP_OFFLOAD 1119 if (toe) { 1120 int rxcs = G_RXCOALESCESIZE(t4_read_reg(sc, A_TP_PARA_REG2)); 1121 1122 /* Note that COP can set rx_coalesce on/off per connection. */ 1123 payload = max(mtu, rxcs); 1124 } else { 1125 #endif 1126 /* large enough even when hw VLAN extraction is disabled */ 1127 payload = sc->params.sge.fl_pktshift + ETHER_HDR_LEN + 1128 ETHER_VLAN_ENCAP_LEN + mtu; 1129 #ifdef TCP_OFFLOAD 1130 } 1131 #endif 1132 1133 return (payload); 1134 } 1135 1136 int 1137 t4_setup_vi_queues(struct vi_info *vi) 1138 { 1139 int rc = 0, i, intr_idx, iqidx; 1140 struct sge_rxq *rxq; 1141 struct sge_txq *txq; 1142 #ifdef TCP_OFFLOAD 1143 struct sge_ofld_rxq *ofld_rxq; 1144 #endif 1145 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1146 struct sge_wrq *ofld_txq; 1147 #endif 1148 #ifdef DEV_NETMAP 1149 int saved_idx; 1150 struct sge_nm_rxq *nm_rxq; 1151 struct sge_nm_txq *nm_txq; 1152 #endif 1153 char name[16]; 1154 struct port_info *pi = vi->pi; 1155 struct adapter *sc = pi->adapter; 1156 struct ifnet *ifp = vi->ifp; 1157 struct sysctl_oid *oid = device_get_sysctl_tree(vi->dev); 1158 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 1159 int maxp, mtu = ifp->if_mtu; 1160 1161 /* Interrupt vector to start from (when using multiple vectors) */ 1162 intr_idx = vi->first_intr; 1163 1164 #ifdef DEV_NETMAP 1165 saved_idx = intr_idx; 1166 if (ifp->if_capabilities & IFCAP_NETMAP) { 1167 1168 /* netmap is supported with direct interrupts only. */ 1169 MPASS(!forwarding_intr_to_fwq(sc)); 1170 1171 /* 1172 * We don't have buffers to back the netmap rx queues 1173 * right now so we create the queues in a way that 1174 * doesn't set off any congestion signal in the chip. 1175 */ 1176 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "nm_rxq", 1177 CTLFLAG_RD, NULL, "rx queues"); 1178 for_each_nm_rxq(vi, i, nm_rxq) { 1179 rc = alloc_nm_rxq(vi, nm_rxq, intr_idx, i, oid); 1180 if (rc != 0) 1181 goto done; 1182 intr_idx++; 1183 } 1184 1185 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "nm_txq", 1186 CTLFLAG_RD, NULL, "tx queues"); 1187 for_each_nm_txq(vi, i, nm_txq) { 1188 iqidx = vi->first_nm_rxq + (i % vi->nnmrxq); 1189 rc = alloc_nm_txq(vi, nm_txq, iqidx, i, oid); 1190 if (rc != 0) 1191 goto done; 1192 } 1193 } 1194 1195 /* Normal rx queues and netmap rx queues share the same interrupts. */ 1196 intr_idx = saved_idx; 1197 #endif 1198 1199 /* 1200 * Allocate rx queues first because a default iqid is required when 1201 * creating a tx queue. 1202 */ 1203 maxp = mtu_to_max_payload(sc, mtu, 0); 1204 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "rxq", 1205 CTLFLAG_RD, NULL, "rx queues"); 1206 for_each_rxq(vi, i, rxq) { 1207 1208 init_iq(&rxq->iq, sc, vi->tmr_idx, vi->pktc_idx, vi->qsize_rxq); 1209 1210 snprintf(name, sizeof(name), "%s rxq%d-fl", 1211 device_get_nameunit(vi->dev), i); 1212 init_fl(sc, &rxq->fl, vi->qsize_rxq / 8, maxp, name); 1213 1214 rc = alloc_rxq(vi, rxq, 1215 forwarding_intr_to_fwq(sc) ? -1 : intr_idx, i, oid); 1216 if (rc != 0) 1217 goto done; 1218 intr_idx++; 1219 } 1220 #ifdef DEV_NETMAP 1221 if (ifp->if_capabilities & IFCAP_NETMAP) 1222 intr_idx = saved_idx + max(vi->nrxq, vi->nnmrxq); 1223 #endif 1224 #ifdef TCP_OFFLOAD 1225 maxp = mtu_to_max_payload(sc, mtu, 1); 1226 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_rxq", 1227 CTLFLAG_RD, NULL, "rx queues for offloaded TCP connections"); 1228 for_each_ofld_rxq(vi, i, ofld_rxq) { 1229 1230 init_iq(&ofld_rxq->iq, sc, vi->ofld_tmr_idx, vi->ofld_pktc_idx, 1231 vi->qsize_rxq); 1232 1233 snprintf(name, sizeof(name), "%s ofld_rxq%d-fl", 1234 device_get_nameunit(vi->dev), i); 1235 init_fl(sc, &ofld_rxq->fl, vi->qsize_rxq / 8, maxp, name); 1236 1237 rc = alloc_ofld_rxq(vi, ofld_rxq, 1238 forwarding_intr_to_fwq(sc) ? -1 : intr_idx, i, oid); 1239 if (rc != 0) 1240 goto done; 1241 intr_idx++; 1242 } 1243 #endif 1244 1245 /* 1246 * Now the tx queues. 1247 */ 1248 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "txq", CTLFLAG_RD, 1249 NULL, "tx queues"); 1250 for_each_txq(vi, i, txq) { 1251 iqidx = vi->first_rxq + (i % vi->nrxq); 1252 snprintf(name, sizeof(name), "%s txq%d", 1253 device_get_nameunit(vi->dev), i); 1254 init_eq(sc, &txq->eq, EQ_ETH, vi->qsize_txq, pi->tx_chan, 1255 sc->sge.rxq[iqidx].iq.cntxt_id, name); 1256 1257 rc = alloc_txq(vi, txq, i, oid); 1258 if (rc != 0) 1259 goto done; 1260 } 1261 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1262 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_txq", 1263 CTLFLAG_RD, NULL, "tx queues for TOE/ETHOFLD"); 1264 for_each_ofld_txq(vi, i, ofld_txq) { 1265 struct sysctl_oid *oid2; 1266 1267 snprintf(name, sizeof(name), "%s ofld_txq%d", 1268 device_get_nameunit(vi->dev), i); 1269 if (vi->nofldrxq > 0) { 1270 iqidx = vi->first_ofld_rxq + (i % vi->nofldrxq); 1271 init_eq(sc, &ofld_txq->eq, EQ_OFLD, vi->qsize_txq, 1272 pi->tx_chan, sc->sge.ofld_rxq[iqidx].iq.cntxt_id, 1273 name); 1274 } else { 1275 iqidx = vi->first_rxq + (i % vi->nrxq); 1276 init_eq(sc, &ofld_txq->eq, EQ_OFLD, vi->qsize_txq, 1277 pi->tx_chan, sc->sge.rxq[iqidx].iq.cntxt_id, name); 1278 } 1279 1280 snprintf(name, sizeof(name), "%d", i); 1281 oid2 = SYSCTL_ADD_NODE(&vi->ctx, SYSCTL_CHILDREN(oid), OID_AUTO, 1282 name, CTLFLAG_RD, NULL, "offload tx queue"); 1283 1284 rc = alloc_wrq(sc, vi, ofld_txq, oid2); 1285 if (rc != 0) 1286 goto done; 1287 } 1288 #endif 1289 done: 1290 if (rc) 1291 t4_teardown_vi_queues(vi); 1292 1293 return (rc); 1294 } 1295 1296 /* 1297 * Idempotent 1298 */ 1299 int 1300 t4_teardown_vi_queues(struct vi_info *vi) 1301 { 1302 int i; 1303 struct sge_rxq *rxq; 1304 struct sge_txq *txq; 1305 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1306 struct port_info *pi = vi->pi; 1307 struct adapter *sc = pi->adapter; 1308 struct sge_wrq *ofld_txq; 1309 #endif 1310 #ifdef TCP_OFFLOAD 1311 struct sge_ofld_rxq *ofld_rxq; 1312 #endif 1313 #ifdef DEV_NETMAP 1314 struct sge_nm_rxq *nm_rxq; 1315 struct sge_nm_txq *nm_txq; 1316 #endif 1317 1318 /* Do this before freeing the queues */ 1319 if (vi->flags & VI_SYSCTL_CTX) { 1320 sysctl_ctx_free(&vi->ctx); 1321 vi->flags &= ~VI_SYSCTL_CTX; 1322 } 1323 1324 #ifdef DEV_NETMAP 1325 if (vi->ifp->if_capabilities & IFCAP_NETMAP) { 1326 for_each_nm_txq(vi, i, nm_txq) { 1327 free_nm_txq(vi, nm_txq); 1328 } 1329 1330 for_each_nm_rxq(vi, i, nm_rxq) { 1331 free_nm_rxq(vi, nm_rxq); 1332 } 1333 } 1334 #endif 1335 1336 /* 1337 * Take down all the tx queues first, as they reference the rx queues 1338 * (for egress updates, etc.). 1339 */ 1340 1341 for_each_txq(vi, i, txq) { 1342 free_txq(vi, txq); 1343 } 1344 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1345 for_each_ofld_txq(vi, i, ofld_txq) { 1346 free_wrq(sc, ofld_txq); 1347 } 1348 #endif 1349 1350 /* 1351 * Then take down the rx queues. 1352 */ 1353 1354 for_each_rxq(vi, i, rxq) { 1355 free_rxq(vi, rxq); 1356 } 1357 #ifdef TCP_OFFLOAD 1358 for_each_ofld_rxq(vi, i, ofld_rxq) { 1359 free_ofld_rxq(vi, ofld_rxq); 1360 } 1361 #endif 1362 1363 return (0); 1364 } 1365 1366 /* 1367 * Interrupt handler when the driver is using only 1 interrupt. This is a very 1368 * unusual scenario. 1369 * 1370 * a) Deals with errors, if any. 1371 * b) Services firmware event queue, which is taking interrupts for all other 1372 * queues. 1373 */ 1374 void 1375 t4_intr_all(void *arg) 1376 { 1377 struct adapter *sc = arg; 1378 struct sge_iq *fwq = &sc->sge.fwq; 1379 1380 MPASS(sc->intr_count == 1); 1381 1382 if (sc->intr_type == INTR_INTX) 1383 t4_write_reg(sc, MYPF_REG(A_PCIE_PF_CLI), 0); 1384 1385 t4_intr_err(arg); 1386 t4_intr_evt(fwq); 1387 } 1388 1389 /* 1390 * Interrupt handler for errors (installed directly when multiple interrupts are 1391 * being used, or called by t4_intr_all). 1392 */ 1393 void 1394 t4_intr_err(void *arg) 1395 { 1396 struct adapter *sc = arg; 1397 uint32_t v; 1398 const bool verbose = (sc->debug_flags & DF_VERBOSE_SLOWINTR) != 0; 1399 1400 if (sc->flags & ADAP_ERR) 1401 return; 1402 1403 v = t4_read_reg(sc, MYPF_REG(A_PL_PF_INT_CAUSE)); 1404 if (v & F_PFSW) { 1405 sc->swintr++; 1406 t4_write_reg(sc, MYPF_REG(A_PL_PF_INT_CAUSE), v); 1407 } 1408 1409 t4_slow_intr_handler(sc, verbose); 1410 } 1411 1412 /* 1413 * Interrupt handler for iq-only queues. The firmware event queue is the only 1414 * such queue right now. 1415 */ 1416 void 1417 t4_intr_evt(void *arg) 1418 { 1419 struct sge_iq *iq = arg; 1420 1421 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 1422 service_iq(iq, 0); 1423 (void) atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 1424 } 1425 } 1426 1427 /* 1428 * Interrupt handler for iq+fl queues. 1429 */ 1430 void 1431 t4_intr(void *arg) 1432 { 1433 struct sge_iq *iq = arg; 1434 1435 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 1436 service_iq_fl(iq, 0); 1437 (void) atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 1438 } 1439 } 1440 1441 #ifdef DEV_NETMAP 1442 /* 1443 * Interrupt handler for netmap rx queues. 1444 */ 1445 void 1446 t4_nm_intr(void *arg) 1447 { 1448 struct sge_nm_rxq *nm_rxq = arg; 1449 1450 if (atomic_cmpset_int(&nm_rxq->nm_state, NM_ON, NM_BUSY)) { 1451 service_nm_rxq(nm_rxq); 1452 (void) atomic_cmpset_int(&nm_rxq->nm_state, NM_BUSY, NM_ON); 1453 } 1454 } 1455 1456 /* 1457 * Interrupt handler for vectors shared between NIC and netmap rx queues. 1458 */ 1459 void 1460 t4_vi_intr(void *arg) 1461 { 1462 struct irq *irq = arg; 1463 1464 MPASS(irq->nm_rxq != NULL); 1465 t4_nm_intr(irq->nm_rxq); 1466 1467 MPASS(irq->rxq != NULL); 1468 t4_intr(irq->rxq); 1469 } 1470 #endif 1471 1472 /* 1473 * Deals with interrupts on an iq-only (no freelist) queue. 1474 */ 1475 static int 1476 service_iq(struct sge_iq *iq, int budget) 1477 { 1478 struct sge_iq *q; 1479 struct adapter *sc = iq->adapter; 1480 struct iq_desc *d = &iq->desc[iq->cidx]; 1481 int ndescs = 0, limit; 1482 int rsp_type; 1483 uint32_t lq; 1484 STAILQ_HEAD(, sge_iq) iql = STAILQ_HEAD_INITIALIZER(iql); 1485 1486 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq)); 1487 KASSERT((iq->flags & IQ_HAS_FL) == 0, 1488 ("%s: called for iq %p with fl (iq->flags 0x%x)", __func__, iq, 1489 iq->flags)); 1490 MPASS((iq->flags & IQ_ADJ_CREDIT) == 0); 1491 MPASS((iq->flags & IQ_LRO_ENABLED) == 0); 1492 1493 limit = budget ? budget : iq->qsize / 16; 1494 1495 /* 1496 * We always come back and check the descriptor ring for new indirect 1497 * interrupts and other responses after running a single handler. 1498 */ 1499 for (;;) { 1500 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) { 1501 1502 rmb(); 1503 1504 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen); 1505 lq = be32toh(d->rsp.pldbuflen_qid); 1506 1507 switch (rsp_type) { 1508 case X_RSPD_TYPE_FLBUF: 1509 panic("%s: data for an iq (%p) with no freelist", 1510 __func__, iq); 1511 1512 /* NOTREACHED */ 1513 1514 case X_RSPD_TYPE_CPL: 1515 KASSERT(d->rss.opcode < NUM_CPL_CMDS, 1516 ("%s: bad opcode %02x.", __func__, 1517 d->rss.opcode)); 1518 t4_cpl_handler[d->rss.opcode](iq, &d->rss, NULL); 1519 break; 1520 1521 case X_RSPD_TYPE_INTR: 1522 /* 1523 * There are 1K interrupt-capable queues (qids 0 1524 * through 1023). A response type indicating a 1525 * forwarded interrupt with a qid >= 1K is an 1526 * iWARP async notification. 1527 */ 1528 if (__predict_true(lq >= 1024)) { 1529 t4_an_handler(iq, &d->rsp); 1530 break; 1531 } 1532 1533 q = sc->sge.iqmap[lq - sc->sge.iq_start - 1534 sc->sge.iq_base]; 1535 if (atomic_cmpset_int(&q->state, IQS_IDLE, 1536 IQS_BUSY)) { 1537 if (service_iq_fl(q, q->qsize / 16) == 0) { 1538 (void) atomic_cmpset_int(&q->state, 1539 IQS_BUSY, IQS_IDLE); 1540 } else { 1541 STAILQ_INSERT_TAIL(&iql, q, 1542 link); 1543 } 1544 } 1545 break; 1546 1547 default: 1548 KASSERT(0, 1549 ("%s: illegal response type %d on iq %p", 1550 __func__, rsp_type, iq)); 1551 log(LOG_ERR, 1552 "%s: illegal response type %d on iq %p", 1553 device_get_nameunit(sc->dev), rsp_type, iq); 1554 break; 1555 } 1556 1557 d++; 1558 if (__predict_false(++iq->cidx == iq->sidx)) { 1559 iq->cidx = 0; 1560 iq->gen ^= F_RSPD_GEN; 1561 d = &iq->desc[0]; 1562 } 1563 if (__predict_false(++ndescs == limit)) { 1564 t4_write_reg(sc, sc->sge_gts_reg, 1565 V_CIDXINC(ndescs) | 1566 V_INGRESSQID(iq->cntxt_id) | 1567 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); 1568 ndescs = 0; 1569 1570 if (budget) { 1571 return (EINPROGRESS); 1572 } 1573 } 1574 } 1575 1576 if (STAILQ_EMPTY(&iql)) 1577 break; 1578 1579 /* 1580 * Process the head only, and send it to the back of the list if 1581 * it's still not done. 1582 */ 1583 q = STAILQ_FIRST(&iql); 1584 STAILQ_REMOVE_HEAD(&iql, link); 1585 if (service_iq_fl(q, q->qsize / 8) == 0) 1586 (void) atomic_cmpset_int(&q->state, IQS_BUSY, IQS_IDLE); 1587 else 1588 STAILQ_INSERT_TAIL(&iql, q, link); 1589 } 1590 1591 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) | 1592 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params)); 1593 1594 return (0); 1595 } 1596 1597 static inline int 1598 sort_before_lro(struct lro_ctrl *lro) 1599 { 1600 1601 return (lro->lro_mbuf_max != 0); 1602 } 1603 1604 static inline uint64_t 1605 last_flit_to_ns(struct adapter *sc, uint64_t lf) 1606 { 1607 uint64_t n = be64toh(lf) & 0xfffffffffffffff; /* 60b, not 64b. */ 1608 1609 if (n > UINT64_MAX / 1000000) 1610 return (n / sc->params.vpd.cclk * 1000000); 1611 else 1612 return (n * 1000000 / sc->params.vpd.cclk); 1613 } 1614 1615 /* 1616 * Deals with interrupts on an iq+fl queue. 1617 */ 1618 static int 1619 service_iq_fl(struct sge_iq *iq, int budget) 1620 { 1621 struct sge_rxq *rxq = iq_to_rxq(iq); 1622 struct sge_fl *fl; 1623 struct adapter *sc = iq->adapter; 1624 struct iq_desc *d = &iq->desc[iq->cidx]; 1625 int ndescs = 0, limit; 1626 int rsp_type, refill, starved; 1627 uint32_t lq; 1628 uint16_t fl_hw_cidx; 1629 struct mbuf *m0; 1630 #if defined(INET) || defined(INET6) 1631 const struct timeval lro_timeout = {0, sc->lro_timeout}; 1632 struct lro_ctrl *lro = &rxq->lro; 1633 #endif 1634 1635 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq)); 1636 MPASS(iq->flags & IQ_HAS_FL); 1637 1638 limit = budget ? budget : iq->qsize / 16; 1639 fl = &rxq->fl; 1640 fl_hw_cidx = fl->hw_cidx; /* stable snapshot */ 1641 1642 #if defined(INET) || defined(INET6) 1643 if (iq->flags & IQ_ADJ_CREDIT) { 1644 MPASS(sort_before_lro(lro)); 1645 iq->flags &= ~IQ_ADJ_CREDIT; 1646 if ((d->rsp.u.type_gen & F_RSPD_GEN) != iq->gen) { 1647 tcp_lro_flush_all(lro); 1648 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(1) | 1649 V_INGRESSQID((u32)iq->cntxt_id) | 1650 V_SEINTARM(iq->intr_params)); 1651 return (0); 1652 } 1653 ndescs = 1; 1654 } 1655 #else 1656 MPASS((iq->flags & IQ_ADJ_CREDIT) == 0); 1657 #endif 1658 1659 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) { 1660 1661 rmb(); 1662 1663 refill = 0; 1664 m0 = NULL; 1665 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen); 1666 lq = be32toh(d->rsp.pldbuflen_qid); 1667 1668 switch (rsp_type) { 1669 case X_RSPD_TYPE_FLBUF: 1670 1671 m0 = get_fl_payload(sc, fl, lq); 1672 if (__predict_false(m0 == NULL)) 1673 goto out; 1674 refill = IDXDIFF(fl->hw_cidx, fl_hw_cidx, fl->sidx) > 2; 1675 1676 if (iq->flags & IQ_RX_TIMESTAMP) { 1677 /* 1678 * Fill up rcv_tstmp but do not set M_TSTMP. 1679 * rcv_tstmp is not in the format that the 1680 * kernel expects and we don't want to mislead 1681 * it. For now this is only for custom code 1682 * that knows how to interpret cxgbe's stamp. 1683 */ 1684 m0->m_pkthdr.rcv_tstmp = 1685 last_flit_to_ns(sc, d->rsp.u.last_flit); 1686 #ifdef notyet 1687 m0->m_flags |= M_TSTMP; 1688 #endif 1689 } 1690 1691 /* fall through */ 1692 1693 case X_RSPD_TYPE_CPL: 1694 KASSERT(d->rss.opcode < NUM_CPL_CMDS, 1695 ("%s: bad opcode %02x.", __func__, d->rss.opcode)); 1696 t4_cpl_handler[d->rss.opcode](iq, &d->rss, m0); 1697 break; 1698 1699 case X_RSPD_TYPE_INTR: 1700 1701 /* 1702 * There are 1K interrupt-capable queues (qids 0 1703 * through 1023). A response type indicating a 1704 * forwarded interrupt with a qid >= 1K is an 1705 * iWARP async notification. That is the only 1706 * acceptable indirect interrupt on this queue. 1707 */ 1708 if (__predict_false(lq < 1024)) { 1709 panic("%s: indirect interrupt on iq_fl %p " 1710 "with qid %u", __func__, iq, lq); 1711 } 1712 1713 t4_an_handler(iq, &d->rsp); 1714 break; 1715 1716 default: 1717 KASSERT(0, ("%s: illegal response type %d on iq %p", 1718 __func__, rsp_type, iq)); 1719 log(LOG_ERR, "%s: illegal response type %d on iq %p", 1720 device_get_nameunit(sc->dev), rsp_type, iq); 1721 break; 1722 } 1723 1724 d++; 1725 if (__predict_false(++iq->cidx == iq->sidx)) { 1726 iq->cidx = 0; 1727 iq->gen ^= F_RSPD_GEN; 1728 d = &iq->desc[0]; 1729 } 1730 if (__predict_false(++ndescs == limit)) { 1731 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) | 1732 V_INGRESSQID(iq->cntxt_id) | 1733 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); 1734 ndescs = 0; 1735 1736 #if defined(INET) || defined(INET6) 1737 if (iq->flags & IQ_LRO_ENABLED && 1738 !sort_before_lro(lro) && 1739 sc->lro_timeout != 0) { 1740 tcp_lro_flush_inactive(lro, &lro_timeout); 1741 } 1742 #endif 1743 if (budget) { 1744 FL_LOCK(fl); 1745 refill_fl(sc, fl, 32); 1746 FL_UNLOCK(fl); 1747 1748 return (EINPROGRESS); 1749 } 1750 } 1751 if (refill) { 1752 FL_LOCK(fl); 1753 refill_fl(sc, fl, 32); 1754 FL_UNLOCK(fl); 1755 fl_hw_cidx = fl->hw_cidx; 1756 } 1757 } 1758 out: 1759 #if defined(INET) || defined(INET6) 1760 if (iq->flags & IQ_LRO_ENABLED) { 1761 if (ndescs > 0 && lro->lro_mbuf_count > 8) { 1762 MPASS(sort_before_lro(lro)); 1763 /* hold back one credit and don't flush LRO state */ 1764 iq->flags |= IQ_ADJ_CREDIT; 1765 ndescs--; 1766 } else { 1767 tcp_lro_flush_all(lro); 1768 } 1769 } 1770 #endif 1771 1772 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) | 1773 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params)); 1774 1775 FL_LOCK(fl); 1776 starved = refill_fl(sc, fl, 64); 1777 FL_UNLOCK(fl); 1778 if (__predict_false(starved != 0)) 1779 add_fl_to_sfl(sc, fl); 1780 1781 return (0); 1782 } 1783 1784 static inline int 1785 cl_has_metadata(struct sge_fl *fl, struct cluster_layout *cll) 1786 { 1787 int rc = fl->flags & FL_BUF_PACKING || cll->region1 > 0; 1788 1789 if (rc) 1790 MPASS(cll->region3 >= CL_METADATA_SIZE); 1791 1792 return (rc); 1793 } 1794 1795 static inline struct cluster_metadata * 1796 cl_metadata(struct adapter *sc, struct sge_fl *fl, struct cluster_layout *cll, 1797 caddr_t cl) 1798 { 1799 1800 if (cl_has_metadata(fl, cll)) { 1801 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx]; 1802 1803 return ((struct cluster_metadata *)(cl + swz->size) - 1); 1804 } 1805 return (NULL); 1806 } 1807 1808 static void 1809 rxb_free(struct mbuf *m) 1810 { 1811 uma_zone_t zone = m->m_ext.ext_arg1; 1812 void *cl = m->m_ext.ext_arg2; 1813 1814 uma_zfree(zone, cl); 1815 counter_u64_add(extfree_rels, 1); 1816 } 1817 1818 /* 1819 * The mbuf returned by this function could be allocated from zone_mbuf or 1820 * constructed in spare room in the cluster. 1821 * 1822 * The mbuf carries the payload in one of these ways 1823 * a) frame inside the mbuf (mbuf from zone_mbuf) 1824 * b) m_cljset (for clusters without metadata) zone_mbuf 1825 * c) m_extaddref (cluster with metadata) inline mbuf 1826 * d) m_extaddref (cluster with metadata) zone_mbuf 1827 */ 1828 static struct mbuf * 1829 get_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset, 1830 int remaining) 1831 { 1832 struct mbuf *m; 1833 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 1834 struct cluster_layout *cll = &sd->cll; 1835 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx]; 1836 struct hw_buf_info *hwb = &sc->sge.hw_buf_info[cll->hwidx]; 1837 struct cluster_metadata *clm = cl_metadata(sc, fl, cll, sd->cl); 1838 int len, blen; 1839 caddr_t payload; 1840 1841 blen = hwb->size - fl->rx_offset; /* max possible in this buf */ 1842 len = min(remaining, blen); 1843 payload = sd->cl + cll->region1 + fl->rx_offset; 1844 if (fl->flags & FL_BUF_PACKING) { 1845 const u_int l = fr_offset + len; 1846 const u_int pad = roundup2(l, fl->buf_boundary) - l; 1847 1848 if (fl->rx_offset + len + pad < hwb->size) 1849 blen = len + pad; 1850 MPASS(fl->rx_offset + blen <= hwb->size); 1851 } else { 1852 MPASS(fl->rx_offset == 0); /* not packing */ 1853 } 1854 1855 1856 if (sc->sc_do_rxcopy && len < RX_COPY_THRESHOLD) { 1857 1858 /* 1859 * Copy payload into a freshly allocated mbuf. 1860 */ 1861 1862 m = fr_offset == 0 ? 1863 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA); 1864 if (m == NULL) 1865 return (NULL); 1866 fl->mbuf_allocated++; 1867 1868 /* copy data to mbuf */ 1869 bcopy(payload, mtod(m, caddr_t), len); 1870 1871 } else if (sd->nmbuf * MSIZE < cll->region1) { 1872 1873 /* 1874 * There's spare room in the cluster for an mbuf. Create one 1875 * and associate it with the payload that's in the cluster. 1876 */ 1877 1878 MPASS(clm != NULL); 1879 m = (struct mbuf *)(sd->cl + sd->nmbuf * MSIZE); 1880 /* No bzero required */ 1881 if (m_init(m, M_NOWAIT, MT_DATA, 1882 fr_offset == 0 ? M_PKTHDR | M_NOFREE : M_NOFREE)) 1883 return (NULL); 1884 fl->mbuf_inlined++; 1885 m_extaddref(m, payload, blen, &clm->refcount, rxb_free, 1886 swz->zone, sd->cl); 1887 if (sd->nmbuf++ == 0) 1888 counter_u64_add(extfree_refs, 1); 1889 1890 } else { 1891 1892 /* 1893 * Grab an mbuf from zone_mbuf and associate it with the 1894 * payload in the cluster. 1895 */ 1896 1897 m = fr_offset == 0 ? 1898 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA); 1899 if (m == NULL) 1900 return (NULL); 1901 fl->mbuf_allocated++; 1902 if (clm != NULL) { 1903 m_extaddref(m, payload, blen, &clm->refcount, 1904 rxb_free, swz->zone, sd->cl); 1905 if (sd->nmbuf++ == 0) 1906 counter_u64_add(extfree_refs, 1); 1907 } else { 1908 m_cljset(m, sd->cl, swz->type); 1909 sd->cl = NULL; /* consumed, not a recycle candidate */ 1910 } 1911 } 1912 if (fr_offset == 0) 1913 m->m_pkthdr.len = remaining; 1914 m->m_len = len; 1915 1916 if (fl->flags & FL_BUF_PACKING) { 1917 fl->rx_offset += blen; 1918 MPASS(fl->rx_offset <= hwb->size); 1919 if (fl->rx_offset < hwb->size) 1920 return (m); /* without advancing the cidx */ 1921 } 1922 1923 if (__predict_false(++fl->cidx % 8 == 0)) { 1924 uint16_t cidx = fl->cidx / 8; 1925 1926 if (__predict_false(cidx == fl->sidx)) 1927 fl->cidx = cidx = 0; 1928 fl->hw_cidx = cidx; 1929 } 1930 fl->rx_offset = 0; 1931 1932 return (m); 1933 } 1934 1935 static struct mbuf * 1936 get_fl_payload(struct adapter *sc, struct sge_fl *fl, uint32_t len_newbuf) 1937 { 1938 struct mbuf *m0, *m, **pnext; 1939 u_int remaining; 1940 const u_int total = G_RSPD_LEN(len_newbuf); 1941 1942 if (__predict_false(fl->flags & FL_BUF_RESUME)) { 1943 M_ASSERTPKTHDR(fl->m0); 1944 MPASS(fl->m0->m_pkthdr.len == total); 1945 MPASS(fl->remaining < total); 1946 1947 m0 = fl->m0; 1948 pnext = fl->pnext; 1949 remaining = fl->remaining; 1950 fl->flags &= ~FL_BUF_RESUME; 1951 goto get_segment; 1952 } 1953 1954 if (fl->rx_offset > 0 && len_newbuf & F_RSPD_NEWBUF) { 1955 fl->rx_offset = 0; 1956 if (__predict_false(++fl->cidx % 8 == 0)) { 1957 uint16_t cidx = fl->cidx / 8; 1958 1959 if (__predict_false(cidx == fl->sidx)) 1960 fl->cidx = cidx = 0; 1961 fl->hw_cidx = cidx; 1962 } 1963 } 1964 1965 /* 1966 * Payload starts at rx_offset in the current hw buffer. Its length is 1967 * 'len' and it may span multiple hw buffers. 1968 */ 1969 1970 m0 = get_scatter_segment(sc, fl, 0, total); 1971 if (m0 == NULL) 1972 return (NULL); 1973 remaining = total - m0->m_len; 1974 pnext = &m0->m_next; 1975 while (remaining > 0) { 1976 get_segment: 1977 MPASS(fl->rx_offset == 0); 1978 m = get_scatter_segment(sc, fl, total - remaining, remaining); 1979 if (__predict_false(m == NULL)) { 1980 fl->m0 = m0; 1981 fl->pnext = pnext; 1982 fl->remaining = remaining; 1983 fl->flags |= FL_BUF_RESUME; 1984 return (NULL); 1985 } 1986 *pnext = m; 1987 pnext = &m->m_next; 1988 remaining -= m->m_len; 1989 } 1990 *pnext = NULL; 1991 1992 M_ASSERTPKTHDR(m0); 1993 return (m0); 1994 } 1995 1996 static int 1997 t4_eth_rx(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0) 1998 { 1999 struct sge_rxq *rxq = iq_to_rxq(iq); 2000 struct ifnet *ifp = rxq->ifp; 2001 struct adapter *sc = iq->adapter; 2002 const struct cpl_rx_pkt *cpl = (const void *)(rss + 1); 2003 #if defined(INET) || defined(INET6) 2004 struct lro_ctrl *lro = &rxq->lro; 2005 #endif 2006 static const int sw_hashtype[4][2] = { 2007 {M_HASHTYPE_NONE, M_HASHTYPE_NONE}, 2008 {M_HASHTYPE_RSS_IPV4, M_HASHTYPE_RSS_IPV6}, 2009 {M_HASHTYPE_RSS_TCP_IPV4, M_HASHTYPE_RSS_TCP_IPV6}, 2010 {M_HASHTYPE_RSS_UDP_IPV4, M_HASHTYPE_RSS_UDP_IPV6}, 2011 }; 2012 2013 KASSERT(m0 != NULL, ("%s: no payload with opcode %02x", __func__, 2014 rss->opcode)); 2015 2016 m0->m_pkthdr.len -= sc->params.sge.fl_pktshift; 2017 m0->m_len -= sc->params.sge.fl_pktshift; 2018 m0->m_data += sc->params.sge.fl_pktshift; 2019 2020 m0->m_pkthdr.rcvif = ifp; 2021 M_HASHTYPE_SET(m0, sw_hashtype[rss->hash_type][rss->ipv6]); 2022 m0->m_pkthdr.flowid = be32toh(rss->hash_val); 2023 2024 if (cpl->csum_calc && !(cpl->err_vec & sc->params.tp.err_vec_mask)) { 2025 if (ifp->if_capenable & IFCAP_RXCSUM && 2026 cpl->l2info & htobe32(F_RXF_IP)) { 2027 m0->m_pkthdr.csum_flags = (CSUM_IP_CHECKED | 2028 CSUM_IP_VALID | CSUM_DATA_VALID | CSUM_PSEUDO_HDR); 2029 rxq->rxcsum++; 2030 } else if (ifp->if_capenable & IFCAP_RXCSUM_IPV6 && 2031 cpl->l2info & htobe32(F_RXF_IP6)) { 2032 m0->m_pkthdr.csum_flags = (CSUM_DATA_VALID_IPV6 | 2033 CSUM_PSEUDO_HDR); 2034 rxq->rxcsum++; 2035 } 2036 2037 if (__predict_false(cpl->ip_frag)) 2038 m0->m_pkthdr.csum_data = be16toh(cpl->csum); 2039 else 2040 m0->m_pkthdr.csum_data = 0xffff; 2041 } 2042 2043 if (cpl->vlan_ex) { 2044 m0->m_pkthdr.ether_vtag = be16toh(cpl->vlan); 2045 m0->m_flags |= M_VLANTAG; 2046 rxq->vlan_extraction++; 2047 } 2048 2049 #ifdef NUMA 2050 m0->m_pkthdr.numa_domain = ifp->if_numa_domain; 2051 #endif 2052 #if defined(INET) || defined(INET6) 2053 if (iq->flags & IQ_LRO_ENABLED) { 2054 if (sort_before_lro(lro)) { 2055 tcp_lro_queue_mbuf(lro, m0); 2056 return (0); /* queued for sort, then LRO */ 2057 } 2058 if (tcp_lro_rx(lro, m0, 0) == 0) 2059 return (0); /* queued for LRO */ 2060 } 2061 #endif 2062 ifp->if_input(ifp, m0); 2063 2064 return (0); 2065 } 2066 2067 /* 2068 * Must drain the wrq or make sure that someone else will. 2069 */ 2070 static void 2071 wrq_tx_drain(void *arg, int n) 2072 { 2073 struct sge_wrq *wrq = arg; 2074 struct sge_eq *eq = &wrq->eq; 2075 2076 EQ_LOCK(eq); 2077 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 2078 drain_wrq_wr_list(wrq->adapter, wrq); 2079 EQ_UNLOCK(eq); 2080 } 2081 2082 static void 2083 drain_wrq_wr_list(struct adapter *sc, struct sge_wrq *wrq) 2084 { 2085 struct sge_eq *eq = &wrq->eq; 2086 u_int available, dbdiff; /* # of hardware descriptors */ 2087 u_int n; 2088 struct wrqe *wr; 2089 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */ 2090 2091 EQ_LOCK_ASSERT_OWNED(eq); 2092 MPASS(TAILQ_EMPTY(&wrq->incomplete_wrs)); 2093 wr = STAILQ_FIRST(&wrq->wr_list); 2094 MPASS(wr != NULL); /* Must be called with something useful to do */ 2095 MPASS(eq->pidx == eq->dbidx); 2096 dbdiff = 0; 2097 2098 do { 2099 eq->cidx = read_hw_cidx(eq); 2100 if (eq->pidx == eq->cidx) 2101 available = eq->sidx - 1; 2102 else 2103 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2104 2105 MPASS(wr->wrq == wrq); 2106 n = howmany(wr->wr_len, EQ_ESIZE); 2107 if (available < n) 2108 break; 2109 2110 dst = (void *)&eq->desc[eq->pidx]; 2111 if (__predict_true(eq->sidx - eq->pidx > n)) { 2112 /* Won't wrap, won't end exactly at the status page. */ 2113 bcopy(&wr->wr[0], dst, wr->wr_len); 2114 eq->pidx += n; 2115 } else { 2116 int first_portion = (eq->sidx - eq->pidx) * EQ_ESIZE; 2117 2118 bcopy(&wr->wr[0], dst, first_portion); 2119 if (wr->wr_len > first_portion) { 2120 bcopy(&wr->wr[first_portion], &eq->desc[0], 2121 wr->wr_len - first_portion); 2122 } 2123 eq->pidx = n - (eq->sidx - eq->pidx); 2124 } 2125 wrq->tx_wrs_copied++; 2126 2127 if (available < eq->sidx / 4 && 2128 atomic_cmpset_int(&eq->equiq, 0, 1)) { 2129 /* 2130 * XXX: This is not 100% reliable with some 2131 * types of WRs. But this is a very unusual 2132 * situation for an ofld/ctrl queue anyway. 2133 */ 2134 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ | 2135 F_FW_WR_EQUEQ); 2136 } 2137 2138 dbdiff += n; 2139 if (dbdiff >= 16) { 2140 ring_eq_db(sc, eq, dbdiff); 2141 dbdiff = 0; 2142 } 2143 2144 STAILQ_REMOVE_HEAD(&wrq->wr_list, link); 2145 free_wrqe(wr); 2146 MPASS(wrq->nwr_pending > 0); 2147 wrq->nwr_pending--; 2148 MPASS(wrq->ndesc_needed >= n); 2149 wrq->ndesc_needed -= n; 2150 } while ((wr = STAILQ_FIRST(&wrq->wr_list)) != NULL); 2151 2152 if (dbdiff) 2153 ring_eq_db(sc, eq, dbdiff); 2154 } 2155 2156 /* 2157 * Doesn't fail. Holds on to work requests it can't send right away. 2158 */ 2159 void 2160 t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, struct wrqe *wr) 2161 { 2162 #ifdef INVARIANTS 2163 struct sge_eq *eq = &wrq->eq; 2164 #endif 2165 2166 EQ_LOCK_ASSERT_OWNED(eq); 2167 MPASS(wr != NULL); 2168 MPASS(wr->wr_len > 0 && wr->wr_len <= SGE_MAX_WR_LEN); 2169 MPASS((wr->wr_len & 0x7) == 0); 2170 2171 STAILQ_INSERT_TAIL(&wrq->wr_list, wr, link); 2172 wrq->nwr_pending++; 2173 wrq->ndesc_needed += howmany(wr->wr_len, EQ_ESIZE); 2174 2175 if (!TAILQ_EMPTY(&wrq->incomplete_wrs)) 2176 return; /* commit_wrq_wr will drain wr_list as well. */ 2177 2178 drain_wrq_wr_list(sc, wrq); 2179 2180 /* Doorbell must have caught up to the pidx. */ 2181 MPASS(eq->pidx == eq->dbidx); 2182 } 2183 2184 void 2185 t4_update_fl_bufsize(struct ifnet *ifp) 2186 { 2187 struct vi_info *vi = ifp->if_softc; 2188 struct adapter *sc = vi->pi->adapter; 2189 struct sge_rxq *rxq; 2190 #ifdef TCP_OFFLOAD 2191 struct sge_ofld_rxq *ofld_rxq; 2192 #endif 2193 struct sge_fl *fl; 2194 int i, maxp, mtu = ifp->if_mtu; 2195 2196 maxp = mtu_to_max_payload(sc, mtu, 0); 2197 for_each_rxq(vi, i, rxq) { 2198 fl = &rxq->fl; 2199 2200 FL_LOCK(fl); 2201 find_best_refill_source(sc, fl, maxp); 2202 FL_UNLOCK(fl); 2203 } 2204 #ifdef TCP_OFFLOAD 2205 maxp = mtu_to_max_payload(sc, mtu, 1); 2206 for_each_ofld_rxq(vi, i, ofld_rxq) { 2207 fl = &ofld_rxq->fl; 2208 2209 FL_LOCK(fl); 2210 find_best_refill_source(sc, fl, maxp); 2211 FL_UNLOCK(fl); 2212 } 2213 #endif 2214 } 2215 2216 static inline int 2217 mbuf_nsegs(struct mbuf *m) 2218 { 2219 2220 M_ASSERTPKTHDR(m); 2221 KASSERT(m->m_pkthdr.l5hlen > 0, 2222 ("%s: mbuf %p missing information on # of segments.", __func__, m)); 2223 2224 return (m->m_pkthdr.l5hlen); 2225 } 2226 2227 static inline void 2228 set_mbuf_nsegs(struct mbuf *m, uint8_t nsegs) 2229 { 2230 2231 M_ASSERTPKTHDR(m); 2232 m->m_pkthdr.l5hlen = nsegs; 2233 } 2234 2235 static inline int 2236 mbuf_cflags(struct mbuf *m) 2237 { 2238 2239 M_ASSERTPKTHDR(m); 2240 return (m->m_pkthdr.PH_loc.eight[4]); 2241 } 2242 2243 static inline void 2244 set_mbuf_cflags(struct mbuf *m, uint8_t flags) 2245 { 2246 2247 M_ASSERTPKTHDR(m); 2248 m->m_pkthdr.PH_loc.eight[4] = flags; 2249 } 2250 2251 static inline int 2252 mbuf_len16(struct mbuf *m) 2253 { 2254 int n; 2255 2256 M_ASSERTPKTHDR(m); 2257 n = m->m_pkthdr.PH_loc.eight[0]; 2258 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16); 2259 2260 return (n); 2261 } 2262 2263 static inline void 2264 set_mbuf_len16(struct mbuf *m, uint8_t len16) 2265 { 2266 2267 M_ASSERTPKTHDR(m); 2268 m->m_pkthdr.PH_loc.eight[0] = len16; 2269 } 2270 2271 #ifdef RATELIMIT 2272 static inline int 2273 mbuf_eo_nsegs(struct mbuf *m) 2274 { 2275 2276 M_ASSERTPKTHDR(m); 2277 return (m->m_pkthdr.PH_loc.eight[1]); 2278 } 2279 2280 static inline void 2281 set_mbuf_eo_nsegs(struct mbuf *m, uint8_t nsegs) 2282 { 2283 2284 M_ASSERTPKTHDR(m); 2285 m->m_pkthdr.PH_loc.eight[1] = nsegs; 2286 } 2287 2288 static inline int 2289 mbuf_eo_len16(struct mbuf *m) 2290 { 2291 int n; 2292 2293 M_ASSERTPKTHDR(m); 2294 n = m->m_pkthdr.PH_loc.eight[2]; 2295 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16); 2296 2297 return (n); 2298 } 2299 2300 static inline void 2301 set_mbuf_eo_len16(struct mbuf *m, uint8_t len16) 2302 { 2303 2304 M_ASSERTPKTHDR(m); 2305 m->m_pkthdr.PH_loc.eight[2] = len16; 2306 } 2307 2308 static inline int 2309 mbuf_eo_tsclk_tsoff(struct mbuf *m) 2310 { 2311 2312 M_ASSERTPKTHDR(m); 2313 return (m->m_pkthdr.PH_loc.eight[3]); 2314 } 2315 2316 static inline void 2317 set_mbuf_eo_tsclk_tsoff(struct mbuf *m, uint8_t tsclk_tsoff) 2318 { 2319 2320 M_ASSERTPKTHDR(m); 2321 m->m_pkthdr.PH_loc.eight[3] = tsclk_tsoff; 2322 } 2323 2324 static inline int 2325 needs_eo(struct mbuf *m) 2326 { 2327 2328 return (m->m_pkthdr.snd_tag != NULL); 2329 } 2330 #endif 2331 2332 /* 2333 * Try to allocate an mbuf to contain a raw work request. To make it 2334 * easy to construct the work request, don't allocate a chain but a 2335 * single mbuf. 2336 */ 2337 struct mbuf * 2338 alloc_wr_mbuf(int len, int how) 2339 { 2340 struct mbuf *m; 2341 2342 if (len <= MHLEN) 2343 m = m_gethdr(how, MT_DATA); 2344 else if (len <= MCLBYTES) 2345 m = m_getcl(how, MT_DATA, M_PKTHDR); 2346 else 2347 m = NULL; 2348 if (m == NULL) 2349 return (NULL); 2350 m->m_pkthdr.len = len; 2351 m->m_len = len; 2352 set_mbuf_cflags(m, MC_RAW_WR); 2353 set_mbuf_len16(m, howmany(len, 16)); 2354 return (m); 2355 } 2356 2357 static inline int 2358 needs_tso(struct mbuf *m) 2359 { 2360 2361 M_ASSERTPKTHDR(m); 2362 2363 return (m->m_pkthdr.csum_flags & CSUM_TSO); 2364 } 2365 2366 static inline int 2367 needs_l3_csum(struct mbuf *m) 2368 { 2369 2370 M_ASSERTPKTHDR(m); 2371 2372 return (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TSO)); 2373 } 2374 2375 static inline int 2376 needs_l4_csum(struct mbuf *m) 2377 { 2378 2379 M_ASSERTPKTHDR(m); 2380 2381 return (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_UDP_IPV6 | 2382 CSUM_TCP_IPV6 | CSUM_TSO)); 2383 } 2384 2385 static inline int 2386 needs_tcp_csum(struct mbuf *m) 2387 { 2388 2389 M_ASSERTPKTHDR(m); 2390 return (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_TCP_IPV6 | CSUM_TSO)); 2391 } 2392 2393 #ifdef RATELIMIT 2394 static inline int 2395 needs_udp_csum(struct mbuf *m) 2396 { 2397 2398 M_ASSERTPKTHDR(m); 2399 return (m->m_pkthdr.csum_flags & (CSUM_UDP | CSUM_UDP_IPV6)); 2400 } 2401 #endif 2402 2403 static inline int 2404 needs_vlan_insertion(struct mbuf *m) 2405 { 2406 2407 M_ASSERTPKTHDR(m); 2408 2409 return (m->m_flags & M_VLANTAG); 2410 } 2411 2412 static void * 2413 m_advance(struct mbuf **pm, int *poffset, int len) 2414 { 2415 struct mbuf *m = *pm; 2416 int offset = *poffset; 2417 uintptr_t p = 0; 2418 2419 MPASS(len > 0); 2420 2421 for (;;) { 2422 if (offset + len < m->m_len) { 2423 offset += len; 2424 p = mtod(m, uintptr_t) + offset; 2425 break; 2426 } 2427 len -= m->m_len - offset; 2428 m = m->m_next; 2429 offset = 0; 2430 MPASS(m != NULL); 2431 } 2432 *poffset = offset; 2433 *pm = m; 2434 return ((void *)p); 2435 } 2436 2437 /* 2438 * Can deal with empty mbufs in the chain that have m_len = 0, but the chain 2439 * must have at least one mbuf that's not empty. It is possible for this 2440 * routine to return 0 if skip accounts for all the contents of the mbuf chain. 2441 */ 2442 static inline int 2443 count_mbuf_nsegs(struct mbuf *m, int skip) 2444 { 2445 vm_paddr_t lastb, next; 2446 vm_offset_t va; 2447 int len, nsegs; 2448 2449 M_ASSERTPKTHDR(m); 2450 MPASS(m->m_pkthdr.len > 0); 2451 MPASS(m->m_pkthdr.len >= skip); 2452 2453 nsegs = 0; 2454 lastb = 0; 2455 for (; m; m = m->m_next) { 2456 2457 len = m->m_len; 2458 if (__predict_false(len == 0)) 2459 continue; 2460 if (skip >= len) { 2461 skip -= len; 2462 continue; 2463 } 2464 va = mtod(m, vm_offset_t) + skip; 2465 len -= skip; 2466 skip = 0; 2467 next = pmap_kextract(va); 2468 nsegs += sglist_count((void *)(uintptr_t)va, len); 2469 if (lastb + 1 == next) 2470 nsegs--; 2471 lastb = pmap_kextract(va + len - 1); 2472 } 2473 2474 return (nsegs); 2475 } 2476 2477 /* 2478 * Analyze the mbuf to determine its tx needs. The mbuf passed in may change: 2479 * a) caller can assume it's been freed if this function returns with an error. 2480 * b) it may get defragged up if the gather list is too long for the hardware. 2481 */ 2482 int 2483 parse_pkt(struct adapter *sc, struct mbuf **mp) 2484 { 2485 struct mbuf *m0 = *mp, *m; 2486 int rc, nsegs, defragged = 0, offset; 2487 struct ether_header *eh; 2488 void *l3hdr; 2489 #if defined(INET) || defined(INET6) 2490 struct tcphdr *tcp; 2491 #endif 2492 uint16_t eh_type; 2493 2494 M_ASSERTPKTHDR(m0); 2495 if (__predict_false(m0->m_pkthdr.len < ETHER_HDR_LEN)) { 2496 rc = EINVAL; 2497 fail: 2498 m_freem(m0); 2499 *mp = NULL; 2500 return (rc); 2501 } 2502 restart: 2503 /* 2504 * First count the number of gather list segments in the payload. 2505 * Defrag the mbuf if nsegs exceeds the hardware limit. 2506 */ 2507 M_ASSERTPKTHDR(m0); 2508 MPASS(m0->m_pkthdr.len > 0); 2509 nsegs = count_mbuf_nsegs(m0, 0); 2510 if (nsegs > (needs_tso(m0) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS)) { 2511 if (defragged++ > 0 || (m = m_defrag(m0, M_NOWAIT)) == NULL) { 2512 rc = EFBIG; 2513 goto fail; 2514 } 2515 *mp = m0 = m; /* update caller's copy after defrag */ 2516 goto restart; 2517 } 2518 2519 if (__predict_false(nsegs > 2 && m0->m_pkthdr.len <= MHLEN)) { 2520 m0 = m_pullup(m0, m0->m_pkthdr.len); 2521 if (m0 == NULL) { 2522 /* Should have left well enough alone. */ 2523 rc = EFBIG; 2524 goto fail; 2525 } 2526 *mp = m0; /* update caller's copy after pullup */ 2527 goto restart; 2528 } 2529 set_mbuf_nsegs(m0, nsegs); 2530 set_mbuf_cflags(m0, 0); 2531 if (sc->flags & IS_VF) 2532 set_mbuf_len16(m0, txpkt_vm_len16(nsegs, needs_tso(m0))); 2533 else 2534 set_mbuf_len16(m0, txpkt_len16(nsegs, needs_tso(m0))); 2535 2536 #ifdef RATELIMIT 2537 /* 2538 * Ethofld is limited to TCP and UDP for now, and only when L4 hw 2539 * checksumming is enabled. needs_l4_csum happens to check for all the 2540 * right things. 2541 */ 2542 if (__predict_false(needs_eo(m0) && !needs_l4_csum(m0))) 2543 m0->m_pkthdr.snd_tag = NULL; 2544 #endif 2545 2546 if (!needs_tso(m0) && 2547 #ifdef RATELIMIT 2548 !needs_eo(m0) && 2549 #endif 2550 !(sc->flags & IS_VF && (needs_l3_csum(m0) || needs_l4_csum(m0)))) 2551 return (0); 2552 2553 m = m0; 2554 eh = mtod(m, struct ether_header *); 2555 eh_type = ntohs(eh->ether_type); 2556 if (eh_type == ETHERTYPE_VLAN) { 2557 struct ether_vlan_header *evh = (void *)eh; 2558 2559 eh_type = ntohs(evh->evl_proto); 2560 m0->m_pkthdr.l2hlen = sizeof(*evh); 2561 } else 2562 m0->m_pkthdr.l2hlen = sizeof(*eh); 2563 2564 offset = 0; 2565 l3hdr = m_advance(&m, &offset, m0->m_pkthdr.l2hlen); 2566 2567 switch (eh_type) { 2568 #ifdef INET6 2569 case ETHERTYPE_IPV6: 2570 { 2571 struct ip6_hdr *ip6 = l3hdr; 2572 2573 MPASS(!needs_tso(m0) || ip6->ip6_nxt == IPPROTO_TCP); 2574 2575 m0->m_pkthdr.l3hlen = sizeof(*ip6); 2576 break; 2577 } 2578 #endif 2579 #ifdef INET 2580 case ETHERTYPE_IP: 2581 { 2582 struct ip *ip = l3hdr; 2583 2584 m0->m_pkthdr.l3hlen = ip->ip_hl * 4; 2585 break; 2586 } 2587 #endif 2588 default: 2589 panic("%s: ethertype 0x%04x unknown. if_cxgbe must be compiled" 2590 " with the same INET/INET6 options as the kernel.", 2591 __func__, eh_type); 2592 } 2593 2594 #if defined(INET) || defined(INET6) 2595 if (needs_tcp_csum(m0)) { 2596 tcp = m_advance(&m, &offset, m0->m_pkthdr.l3hlen); 2597 m0->m_pkthdr.l4hlen = tcp->th_off * 4; 2598 #ifdef RATELIMIT 2599 if (tsclk >= 0 && *(uint32_t *)(tcp + 1) == ntohl(0x0101080a)) { 2600 set_mbuf_eo_tsclk_tsoff(m0, 2601 V_FW_ETH_TX_EO_WR_TSCLK(tsclk) | 2602 V_FW_ETH_TX_EO_WR_TSOFF(sizeof(*tcp) / 2 + 1)); 2603 } else 2604 set_mbuf_eo_tsclk_tsoff(m0, 0); 2605 } else if (needs_udp_csum(m)) { 2606 m0->m_pkthdr.l4hlen = sizeof(struct udphdr); 2607 #endif 2608 } 2609 #ifdef RATELIMIT 2610 if (needs_eo(m0)) { 2611 u_int immhdrs; 2612 2613 /* EO WRs have the headers in the WR and not the GL. */ 2614 immhdrs = m0->m_pkthdr.l2hlen + m0->m_pkthdr.l3hlen + 2615 m0->m_pkthdr.l4hlen; 2616 nsegs = count_mbuf_nsegs(m0, immhdrs); 2617 set_mbuf_eo_nsegs(m0, nsegs); 2618 set_mbuf_eo_len16(m0, 2619 txpkt_eo_len16(nsegs, immhdrs, needs_tso(m0))); 2620 } 2621 #endif 2622 #endif 2623 MPASS(m0 == *mp); 2624 return (0); 2625 } 2626 2627 void * 2628 start_wrq_wr(struct sge_wrq *wrq, int len16, struct wrq_cookie *cookie) 2629 { 2630 struct sge_eq *eq = &wrq->eq; 2631 struct adapter *sc = wrq->adapter; 2632 int ndesc, available; 2633 struct wrqe *wr; 2634 void *w; 2635 2636 MPASS(len16 > 0); 2637 ndesc = howmany(len16, EQ_ESIZE / 16); 2638 MPASS(ndesc > 0 && ndesc <= SGE_MAX_WR_NDESC); 2639 2640 EQ_LOCK(eq); 2641 2642 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 2643 drain_wrq_wr_list(sc, wrq); 2644 2645 if (!STAILQ_EMPTY(&wrq->wr_list)) { 2646 slowpath: 2647 EQ_UNLOCK(eq); 2648 wr = alloc_wrqe(len16 * 16, wrq); 2649 if (__predict_false(wr == NULL)) 2650 return (NULL); 2651 cookie->pidx = -1; 2652 cookie->ndesc = ndesc; 2653 return (&wr->wr); 2654 } 2655 2656 eq->cidx = read_hw_cidx(eq); 2657 if (eq->pidx == eq->cidx) 2658 available = eq->sidx - 1; 2659 else 2660 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2661 if (available < ndesc) 2662 goto slowpath; 2663 2664 cookie->pidx = eq->pidx; 2665 cookie->ndesc = ndesc; 2666 TAILQ_INSERT_TAIL(&wrq->incomplete_wrs, cookie, link); 2667 2668 w = &eq->desc[eq->pidx]; 2669 IDXINCR(eq->pidx, ndesc, eq->sidx); 2670 if (__predict_false(cookie->pidx + ndesc > eq->sidx)) { 2671 w = &wrq->ss[0]; 2672 wrq->ss_pidx = cookie->pidx; 2673 wrq->ss_len = len16 * 16; 2674 } 2675 2676 EQ_UNLOCK(eq); 2677 2678 return (w); 2679 } 2680 2681 void 2682 commit_wrq_wr(struct sge_wrq *wrq, void *w, struct wrq_cookie *cookie) 2683 { 2684 struct sge_eq *eq = &wrq->eq; 2685 struct adapter *sc = wrq->adapter; 2686 int ndesc, pidx; 2687 struct wrq_cookie *prev, *next; 2688 2689 if (cookie->pidx == -1) { 2690 struct wrqe *wr = __containerof(w, struct wrqe, wr); 2691 2692 t4_wrq_tx(sc, wr); 2693 return; 2694 } 2695 2696 if (__predict_false(w == &wrq->ss[0])) { 2697 int n = (eq->sidx - wrq->ss_pidx) * EQ_ESIZE; 2698 2699 MPASS(wrq->ss_len > n); /* WR had better wrap around. */ 2700 bcopy(&wrq->ss[0], &eq->desc[wrq->ss_pidx], n); 2701 bcopy(&wrq->ss[n], &eq->desc[0], wrq->ss_len - n); 2702 wrq->tx_wrs_ss++; 2703 } else 2704 wrq->tx_wrs_direct++; 2705 2706 EQ_LOCK(eq); 2707 ndesc = cookie->ndesc; /* Can be more than SGE_MAX_WR_NDESC here. */ 2708 pidx = cookie->pidx; 2709 MPASS(pidx >= 0 && pidx < eq->sidx); 2710 prev = TAILQ_PREV(cookie, wrq_incomplete_wrs, link); 2711 next = TAILQ_NEXT(cookie, link); 2712 if (prev == NULL) { 2713 MPASS(pidx == eq->dbidx); 2714 if (next == NULL || ndesc >= 16) { 2715 int available; 2716 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */ 2717 2718 /* 2719 * Note that the WR via which we'll request tx updates 2720 * is at pidx and not eq->pidx, which has moved on 2721 * already. 2722 */ 2723 dst = (void *)&eq->desc[pidx]; 2724 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2725 if (available < eq->sidx / 4 && 2726 atomic_cmpset_int(&eq->equiq, 0, 1)) { 2727 /* 2728 * XXX: This is not 100% reliable with some 2729 * types of WRs. But this is a very unusual 2730 * situation for an ofld/ctrl queue anyway. 2731 */ 2732 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ | 2733 F_FW_WR_EQUEQ); 2734 } 2735 2736 ring_eq_db(wrq->adapter, eq, ndesc); 2737 } else { 2738 MPASS(IDXDIFF(next->pidx, pidx, eq->sidx) == ndesc); 2739 next->pidx = pidx; 2740 next->ndesc += ndesc; 2741 } 2742 } else { 2743 MPASS(IDXDIFF(pidx, prev->pidx, eq->sidx) == prev->ndesc); 2744 prev->ndesc += ndesc; 2745 } 2746 TAILQ_REMOVE(&wrq->incomplete_wrs, cookie, link); 2747 2748 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 2749 drain_wrq_wr_list(sc, wrq); 2750 2751 #ifdef INVARIANTS 2752 if (TAILQ_EMPTY(&wrq->incomplete_wrs)) { 2753 /* Doorbell must have caught up to the pidx. */ 2754 MPASS(wrq->eq.pidx == wrq->eq.dbidx); 2755 } 2756 #endif 2757 EQ_UNLOCK(eq); 2758 } 2759 2760 static u_int 2761 can_resume_eth_tx(struct mp_ring *r) 2762 { 2763 struct sge_eq *eq = r->cookie; 2764 2765 return (total_available_tx_desc(eq) > eq->sidx / 8); 2766 } 2767 2768 static inline int 2769 cannot_use_txpkts(struct mbuf *m) 2770 { 2771 /* maybe put a GL limit too, to avoid silliness? */ 2772 2773 return (needs_tso(m) || (mbuf_cflags(m) & MC_RAW_WR) != 0); 2774 } 2775 2776 static inline int 2777 discard_tx(struct sge_eq *eq) 2778 { 2779 2780 return ((eq->flags & (EQ_ENABLED | EQ_QFLUSH)) != EQ_ENABLED); 2781 } 2782 2783 static inline int 2784 wr_can_update_eq(struct fw_eth_tx_pkts_wr *wr) 2785 { 2786 2787 switch (G_FW_WR_OP(be32toh(wr->op_pkd))) { 2788 case FW_ULPTX_WR: 2789 case FW_ETH_TX_PKT_WR: 2790 case FW_ETH_TX_PKTS_WR: 2791 case FW_ETH_TX_PKT_VM_WR: 2792 return (1); 2793 default: 2794 return (0); 2795 } 2796 } 2797 2798 /* 2799 * r->items[cidx] to r->items[pidx], with a wraparound at r->size, are ready to 2800 * be consumed. Return the actual number consumed. 0 indicates a stall. 2801 */ 2802 static u_int 2803 eth_tx(struct mp_ring *r, u_int cidx, u_int pidx) 2804 { 2805 struct sge_txq *txq = r->cookie; 2806 struct sge_eq *eq = &txq->eq; 2807 struct ifnet *ifp = txq->ifp; 2808 struct vi_info *vi = ifp->if_softc; 2809 struct port_info *pi = vi->pi; 2810 struct adapter *sc = pi->adapter; 2811 u_int total, remaining; /* # of packets */ 2812 u_int available, dbdiff; /* # of hardware descriptors */ 2813 u_int n, next_cidx; 2814 struct mbuf *m0, *tail; 2815 struct txpkts txp; 2816 struct fw_eth_tx_pkts_wr *wr; /* any fw WR struct will do */ 2817 2818 remaining = IDXDIFF(pidx, cidx, r->size); 2819 MPASS(remaining > 0); /* Must not be called without work to do. */ 2820 total = 0; 2821 2822 TXQ_LOCK(txq); 2823 if (__predict_false(discard_tx(eq))) { 2824 while (cidx != pidx) { 2825 m0 = r->items[cidx]; 2826 m_freem(m0); 2827 if (++cidx == r->size) 2828 cidx = 0; 2829 } 2830 reclaim_tx_descs(txq, 2048); 2831 total = remaining; 2832 goto done; 2833 } 2834 2835 /* How many hardware descriptors do we have readily available. */ 2836 if (eq->pidx == eq->cidx) 2837 available = eq->sidx - 1; 2838 else 2839 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2840 dbdiff = IDXDIFF(eq->pidx, eq->dbidx, eq->sidx); 2841 2842 while (remaining > 0) { 2843 2844 m0 = r->items[cidx]; 2845 M_ASSERTPKTHDR(m0); 2846 MPASS(m0->m_nextpkt == NULL); 2847 2848 if (available < SGE_MAX_WR_NDESC) { 2849 available += reclaim_tx_descs(txq, 64); 2850 if (available < howmany(mbuf_len16(m0), EQ_ESIZE / 16)) 2851 break; /* out of descriptors */ 2852 } 2853 2854 next_cidx = cidx + 1; 2855 if (__predict_false(next_cidx == r->size)) 2856 next_cidx = 0; 2857 2858 wr = (void *)&eq->desc[eq->pidx]; 2859 if (sc->flags & IS_VF) { 2860 total++; 2861 remaining--; 2862 ETHER_BPF_MTAP(ifp, m0); 2863 n = write_txpkt_vm_wr(sc, txq, (void *)wr, m0, 2864 available); 2865 } else if (remaining > 1 && 2866 try_txpkts(m0, r->items[next_cidx], &txp, available) == 0) { 2867 2868 /* pkts at cidx, next_cidx should both be in txp. */ 2869 MPASS(txp.npkt == 2); 2870 tail = r->items[next_cidx]; 2871 MPASS(tail->m_nextpkt == NULL); 2872 ETHER_BPF_MTAP(ifp, m0); 2873 ETHER_BPF_MTAP(ifp, tail); 2874 m0->m_nextpkt = tail; 2875 2876 if (__predict_false(++next_cidx == r->size)) 2877 next_cidx = 0; 2878 2879 while (next_cidx != pidx) { 2880 if (add_to_txpkts(r->items[next_cidx], &txp, 2881 available) != 0) 2882 break; 2883 tail->m_nextpkt = r->items[next_cidx]; 2884 tail = tail->m_nextpkt; 2885 ETHER_BPF_MTAP(ifp, tail); 2886 if (__predict_false(++next_cidx == r->size)) 2887 next_cidx = 0; 2888 } 2889 2890 n = write_txpkts_wr(txq, wr, m0, &txp, available); 2891 total += txp.npkt; 2892 remaining -= txp.npkt; 2893 } else if (mbuf_cflags(m0) & MC_RAW_WR) { 2894 total++; 2895 remaining--; 2896 n = write_raw_wr(txq, (void *)wr, m0, available); 2897 } else { 2898 total++; 2899 remaining--; 2900 ETHER_BPF_MTAP(ifp, m0); 2901 n = write_txpkt_wr(txq, (void *)wr, m0, available); 2902 } 2903 MPASS(n >= 1 && n <= available && n <= SGE_MAX_WR_NDESC); 2904 2905 available -= n; 2906 dbdiff += n; 2907 IDXINCR(eq->pidx, n, eq->sidx); 2908 2909 if (wr_can_update_eq(wr)) { 2910 if (total_available_tx_desc(eq) < eq->sidx / 4 && 2911 atomic_cmpset_int(&eq->equiq, 0, 1)) { 2912 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ | 2913 F_FW_WR_EQUEQ); 2914 eq->equeqidx = eq->pidx; 2915 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 2916 32) { 2917 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ); 2918 eq->equeqidx = eq->pidx; 2919 } 2920 } 2921 2922 if (dbdiff >= 16 && remaining >= 4) { 2923 ring_eq_db(sc, eq, dbdiff); 2924 available += reclaim_tx_descs(txq, 4 * dbdiff); 2925 dbdiff = 0; 2926 } 2927 2928 cidx = next_cidx; 2929 } 2930 if (dbdiff != 0) { 2931 ring_eq_db(sc, eq, dbdiff); 2932 reclaim_tx_descs(txq, 32); 2933 } 2934 done: 2935 TXQ_UNLOCK(txq); 2936 2937 return (total); 2938 } 2939 2940 static inline void 2941 init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int pktc_idx, 2942 int qsize) 2943 { 2944 2945 KASSERT(tmr_idx >= 0 && tmr_idx < SGE_NTIMERS, 2946 ("%s: bad tmr_idx %d", __func__, tmr_idx)); 2947 KASSERT(pktc_idx < SGE_NCOUNTERS, /* -ve is ok, means don't use */ 2948 ("%s: bad pktc_idx %d", __func__, pktc_idx)); 2949 2950 iq->flags = 0; 2951 iq->adapter = sc; 2952 iq->intr_params = V_QINTR_TIMER_IDX(tmr_idx); 2953 iq->intr_pktc_idx = SGE_NCOUNTERS - 1; 2954 if (pktc_idx >= 0) { 2955 iq->intr_params |= F_QINTR_CNT_EN; 2956 iq->intr_pktc_idx = pktc_idx; 2957 } 2958 iq->qsize = roundup2(qsize, 16); /* See FW_IQ_CMD/iqsize */ 2959 iq->sidx = iq->qsize - sc->params.sge.spg_len / IQ_ESIZE; 2960 } 2961 2962 static inline void 2963 init_fl(struct adapter *sc, struct sge_fl *fl, int qsize, int maxp, char *name) 2964 { 2965 2966 fl->qsize = qsize; 2967 fl->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE; 2968 strlcpy(fl->lockname, name, sizeof(fl->lockname)); 2969 if (sc->flags & BUF_PACKING_OK && 2970 ((!is_t4(sc) && buffer_packing) || /* T5+: enabled unless 0 */ 2971 (is_t4(sc) && buffer_packing == 1)))/* T4: disabled unless 1 */ 2972 fl->flags |= FL_BUF_PACKING; 2973 find_best_refill_source(sc, fl, maxp); 2974 find_safe_refill_source(sc, fl); 2975 } 2976 2977 static inline void 2978 init_eq(struct adapter *sc, struct sge_eq *eq, int eqtype, int qsize, 2979 uint8_t tx_chan, uint16_t iqid, char *name) 2980 { 2981 KASSERT(eqtype <= EQ_TYPEMASK, ("%s: bad qtype %d", __func__, eqtype)); 2982 2983 eq->flags = eqtype & EQ_TYPEMASK; 2984 eq->tx_chan = tx_chan; 2985 eq->iqid = iqid; 2986 eq->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE; 2987 strlcpy(eq->lockname, name, sizeof(eq->lockname)); 2988 } 2989 2990 static int 2991 alloc_ring(struct adapter *sc, size_t len, bus_dma_tag_t *tag, 2992 bus_dmamap_t *map, bus_addr_t *pa, void **va) 2993 { 2994 int rc; 2995 2996 rc = bus_dma_tag_create(sc->dmat, 512, 0, BUS_SPACE_MAXADDR, 2997 BUS_SPACE_MAXADDR, NULL, NULL, len, 1, len, 0, NULL, NULL, tag); 2998 if (rc != 0) { 2999 device_printf(sc->dev, "cannot allocate DMA tag: %d\n", rc); 3000 goto done; 3001 } 3002 3003 rc = bus_dmamem_alloc(*tag, va, 3004 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, map); 3005 if (rc != 0) { 3006 device_printf(sc->dev, "cannot allocate DMA memory: %d\n", rc); 3007 goto done; 3008 } 3009 3010 rc = bus_dmamap_load(*tag, *map, *va, len, oneseg_dma_callback, pa, 0); 3011 if (rc != 0) { 3012 device_printf(sc->dev, "cannot load DMA map: %d\n", rc); 3013 goto done; 3014 } 3015 done: 3016 if (rc) 3017 free_ring(sc, *tag, *map, *pa, *va); 3018 3019 return (rc); 3020 } 3021 3022 static int 3023 free_ring(struct adapter *sc, bus_dma_tag_t tag, bus_dmamap_t map, 3024 bus_addr_t pa, void *va) 3025 { 3026 if (pa) 3027 bus_dmamap_unload(tag, map); 3028 if (va) 3029 bus_dmamem_free(tag, va, map); 3030 if (tag) 3031 bus_dma_tag_destroy(tag); 3032 3033 return (0); 3034 } 3035 3036 /* 3037 * Allocates the ring for an ingress queue and an optional freelist. If the 3038 * freelist is specified it will be allocated and then associated with the 3039 * ingress queue. 3040 * 3041 * Returns errno on failure. Resources allocated up to that point may still be 3042 * allocated. Caller is responsible for cleanup in case this function fails. 3043 * 3044 * If the ingress queue will take interrupts directly then the intr_idx 3045 * specifies the vector, starting from 0. -1 means the interrupts for this 3046 * queue should be forwarded to the fwq. 3047 */ 3048 static int 3049 alloc_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl, 3050 int intr_idx, int cong) 3051 { 3052 int rc, i, cntxt_id; 3053 size_t len; 3054 struct fw_iq_cmd c; 3055 struct port_info *pi = vi->pi; 3056 struct adapter *sc = iq->adapter; 3057 struct sge_params *sp = &sc->params.sge; 3058 __be32 v = 0; 3059 3060 len = iq->qsize * IQ_ESIZE; 3061 rc = alloc_ring(sc, len, &iq->desc_tag, &iq->desc_map, &iq->ba, 3062 (void **)&iq->desc); 3063 if (rc != 0) 3064 return (rc); 3065 3066 bzero(&c, sizeof(c)); 3067 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 3068 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) | 3069 V_FW_IQ_CMD_VFN(0)); 3070 3071 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART | 3072 FW_LEN16(c)); 3073 3074 /* Special handling for firmware event queue */ 3075 if (iq == &sc->sge.fwq) 3076 v |= F_FW_IQ_CMD_IQASYNCH; 3077 3078 if (intr_idx < 0) { 3079 /* Forwarded interrupts, all headed to fwq */ 3080 v |= F_FW_IQ_CMD_IQANDST; 3081 v |= V_FW_IQ_CMD_IQANDSTINDEX(sc->sge.fwq.cntxt_id); 3082 } else { 3083 KASSERT(intr_idx < sc->intr_count, 3084 ("%s: invalid direct intr_idx %d", __func__, intr_idx)); 3085 v |= V_FW_IQ_CMD_IQANDSTINDEX(intr_idx); 3086 } 3087 3088 c.type_to_iqandstindex = htobe32(v | 3089 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) | 3090 V_FW_IQ_CMD_VIID(vi->viid) | 3091 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT)); 3092 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->tx_chan) | 3093 F_FW_IQ_CMD_IQGTSMODE | 3094 V_FW_IQ_CMD_IQINTCNTTHRESH(iq->intr_pktc_idx) | 3095 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4)); 3096 c.iqsize = htobe16(iq->qsize); 3097 c.iqaddr = htobe64(iq->ba); 3098 if (cong >= 0) 3099 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN); 3100 3101 if (fl) { 3102 mtx_init(&fl->fl_lock, fl->lockname, NULL, MTX_DEF); 3103 3104 len = fl->qsize * EQ_ESIZE; 3105 rc = alloc_ring(sc, len, &fl->desc_tag, &fl->desc_map, 3106 &fl->ba, (void **)&fl->desc); 3107 if (rc) 3108 return (rc); 3109 3110 /* Allocate space for one software descriptor per buffer. */ 3111 rc = alloc_fl_sdesc(fl); 3112 if (rc != 0) { 3113 device_printf(sc->dev, 3114 "failed to setup fl software descriptors: %d\n", 3115 rc); 3116 return (rc); 3117 } 3118 3119 if (fl->flags & FL_BUF_PACKING) { 3120 fl->lowat = roundup2(sp->fl_starve_threshold2, 8); 3121 fl->buf_boundary = sp->pack_boundary; 3122 } else { 3123 fl->lowat = roundup2(sp->fl_starve_threshold, 8); 3124 fl->buf_boundary = 16; 3125 } 3126 if (fl_pad && fl->buf_boundary < sp->pad_boundary) 3127 fl->buf_boundary = sp->pad_boundary; 3128 3129 c.iqns_to_fl0congen |= 3130 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) | 3131 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO | 3132 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) | 3133 (fl->flags & FL_BUF_PACKING ? F_FW_IQ_CMD_FL0PACKEN : 3134 0)); 3135 if (cong >= 0) { 3136 c.iqns_to_fl0congen |= 3137 htobe32(V_FW_IQ_CMD_FL0CNGCHMAP(cong) | 3138 F_FW_IQ_CMD_FL0CONGCIF | 3139 F_FW_IQ_CMD_FL0CONGEN); 3140 } 3141 c.fl0dcaen_to_fl0cidxfthresh = 3142 htobe16(V_FW_IQ_CMD_FL0FBMIN(chip_id(sc) <= CHELSIO_T5 ? 3143 X_FETCHBURSTMIN_128B : X_FETCHBURSTMIN_64B) | 3144 V_FW_IQ_CMD_FL0FBMAX(chip_id(sc) <= CHELSIO_T5 ? 3145 X_FETCHBURSTMAX_512B : X_FETCHBURSTMAX_256B)); 3146 c.fl0size = htobe16(fl->qsize); 3147 c.fl0addr = htobe64(fl->ba); 3148 } 3149 3150 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3151 if (rc != 0) { 3152 device_printf(sc->dev, 3153 "failed to create ingress queue: %d\n", rc); 3154 return (rc); 3155 } 3156 3157 iq->cidx = 0; 3158 iq->gen = F_RSPD_GEN; 3159 iq->intr_next = iq->intr_params; 3160 iq->cntxt_id = be16toh(c.iqid); 3161 iq->abs_id = be16toh(c.physiqid); 3162 iq->flags |= IQ_ALLOCATED; 3163 3164 cntxt_id = iq->cntxt_id - sc->sge.iq_start; 3165 if (cntxt_id >= sc->sge.niq) { 3166 panic ("%s: iq->cntxt_id (%d) more than the max (%d)", __func__, 3167 cntxt_id, sc->sge.niq - 1); 3168 } 3169 sc->sge.iqmap[cntxt_id] = iq; 3170 3171 if (fl) { 3172 u_int qid; 3173 3174 iq->flags |= IQ_HAS_FL; 3175 fl->cntxt_id = be16toh(c.fl0id); 3176 fl->pidx = fl->cidx = 0; 3177 3178 cntxt_id = fl->cntxt_id - sc->sge.eq_start; 3179 if (cntxt_id >= sc->sge.neq) { 3180 panic("%s: fl->cntxt_id (%d) more than the max (%d)", 3181 __func__, cntxt_id, sc->sge.neq - 1); 3182 } 3183 sc->sge.eqmap[cntxt_id] = (void *)fl; 3184 3185 qid = fl->cntxt_id; 3186 if (isset(&sc->doorbells, DOORBELL_UDB)) { 3187 uint32_t s_qpp = sc->params.sge.eq_s_qpp; 3188 uint32_t mask = (1 << s_qpp) - 1; 3189 volatile uint8_t *udb; 3190 3191 udb = sc->udbs_base + UDBS_DB_OFFSET; 3192 udb += (qid >> s_qpp) << PAGE_SHIFT; 3193 qid &= mask; 3194 if (qid < PAGE_SIZE / UDBS_SEG_SIZE) { 3195 udb += qid << UDBS_SEG_SHIFT; 3196 qid = 0; 3197 } 3198 fl->udb = (volatile void *)udb; 3199 } 3200 fl->dbval = V_QID(qid) | sc->chip_params->sge_fl_db; 3201 3202 FL_LOCK(fl); 3203 /* Enough to make sure the SGE doesn't think it's starved */ 3204 refill_fl(sc, fl, fl->lowat); 3205 FL_UNLOCK(fl); 3206 } 3207 3208 if (chip_id(sc) >= CHELSIO_T5 && !(sc->flags & IS_VF) && cong >= 0) { 3209 uint32_t param, val; 3210 3211 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 3212 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) | 3213 V_FW_PARAMS_PARAM_YZ(iq->cntxt_id); 3214 if (cong == 0) 3215 val = 1 << 19; 3216 else { 3217 val = 2 << 19; 3218 for (i = 0; i < 4; i++) { 3219 if (cong & (1 << i)) 3220 val |= 1 << (i << 2); 3221 } 3222 } 3223 3224 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 3225 if (rc != 0) { 3226 /* report error but carry on */ 3227 device_printf(sc->dev, 3228 "failed to set congestion manager context for " 3229 "ingress queue %d: %d\n", iq->cntxt_id, rc); 3230 } 3231 } 3232 3233 /* Enable IQ interrupts */ 3234 atomic_store_rel_int(&iq->state, IQS_IDLE); 3235 t4_write_reg(sc, sc->sge_gts_reg, V_SEINTARM(iq->intr_params) | 3236 V_INGRESSQID(iq->cntxt_id)); 3237 3238 return (0); 3239 } 3240 3241 static int 3242 free_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl) 3243 { 3244 int rc; 3245 struct adapter *sc = iq->adapter; 3246 device_t dev; 3247 3248 if (sc == NULL) 3249 return (0); /* nothing to do */ 3250 3251 dev = vi ? vi->dev : sc->dev; 3252 3253 if (iq->flags & IQ_ALLOCATED) { 3254 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0, 3255 FW_IQ_TYPE_FL_INT_CAP, iq->cntxt_id, 3256 fl ? fl->cntxt_id : 0xffff, 0xffff); 3257 if (rc != 0) { 3258 device_printf(dev, 3259 "failed to free queue %p: %d\n", iq, rc); 3260 return (rc); 3261 } 3262 iq->flags &= ~IQ_ALLOCATED; 3263 } 3264 3265 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, iq->desc); 3266 3267 bzero(iq, sizeof(*iq)); 3268 3269 if (fl) { 3270 free_ring(sc, fl->desc_tag, fl->desc_map, fl->ba, 3271 fl->desc); 3272 3273 if (fl->sdesc) 3274 free_fl_sdesc(sc, fl); 3275 3276 if (mtx_initialized(&fl->fl_lock)) 3277 mtx_destroy(&fl->fl_lock); 3278 3279 bzero(fl, sizeof(*fl)); 3280 } 3281 3282 return (0); 3283 } 3284 3285 static void 3286 add_iq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid, 3287 struct sge_iq *iq) 3288 { 3289 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3290 3291 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, &iq->ba, 3292 "bus address of descriptor ring"); 3293 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3294 iq->qsize * IQ_ESIZE, "descriptor ring size in bytes"); 3295 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "abs_id", 3296 CTLTYPE_INT | CTLFLAG_RD, &iq->abs_id, 0, sysctl_uint16, "I", 3297 "absolute id of the queue"); 3298 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 3299 CTLTYPE_INT | CTLFLAG_RD, &iq->cntxt_id, 0, sysctl_uint16, "I", 3300 "SGE context id of the queue"); 3301 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx", 3302 CTLTYPE_INT | CTLFLAG_RD, &iq->cidx, 0, sysctl_uint16, "I", 3303 "consumer index"); 3304 } 3305 3306 static void 3307 add_fl_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx, 3308 struct sysctl_oid *oid, struct sge_fl *fl) 3309 { 3310 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3311 3312 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL, 3313 "freelist"); 3314 children = SYSCTL_CHILDREN(oid); 3315 3316 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, 3317 &fl->ba, "bus address of descriptor ring"); 3318 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3319 fl->sidx * EQ_ESIZE + sc->params.sge.spg_len, 3320 "desc ring size in bytes"); 3321 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 3322 CTLTYPE_INT | CTLFLAG_RD, &fl->cntxt_id, 0, sysctl_uint16, "I", 3323 "SGE context id of the freelist"); 3324 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "padding", CTLFLAG_RD, NULL, 3325 fl_pad ? 1 : 0, "padding enabled"); 3326 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "packing", CTLFLAG_RD, NULL, 3327 fl->flags & FL_BUF_PACKING ? 1 : 0, "packing enabled"); 3328 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &fl->cidx, 3329 0, "consumer index"); 3330 if (fl->flags & FL_BUF_PACKING) { 3331 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rx_offset", 3332 CTLFLAG_RD, &fl->rx_offset, 0, "packing rx offset"); 3333 } 3334 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &fl->pidx, 3335 0, "producer index"); 3336 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_allocated", 3337 CTLFLAG_RD, &fl->mbuf_allocated, "# of mbuf allocated"); 3338 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_inlined", 3339 CTLFLAG_RD, &fl->mbuf_inlined, "# of mbuf inlined in clusters"); 3340 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_allocated", 3341 CTLFLAG_RD, &fl->cl_allocated, "# of clusters allocated"); 3342 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_recycled", 3343 CTLFLAG_RD, &fl->cl_recycled, "# of clusters recycled"); 3344 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_fast_recycled", 3345 CTLFLAG_RD, &fl->cl_fast_recycled, "# of clusters recycled (fast)"); 3346 } 3347 3348 static int 3349 alloc_fwq(struct adapter *sc) 3350 { 3351 int rc, intr_idx; 3352 struct sge_iq *fwq = &sc->sge.fwq; 3353 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev); 3354 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3355 3356 init_iq(fwq, sc, 0, 0, FW_IQ_QSIZE); 3357 if (sc->flags & IS_VF) 3358 intr_idx = 0; 3359 else 3360 intr_idx = sc->intr_count > 1 ? 1 : 0; 3361 rc = alloc_iq_fl(&sc->port[0]->vi[0], fwq, NULL, intr_idx, -1); 3362 if (rc != 0) { 3363 device_printf(sc->dev, 3364 "failed to create firmware event queue: %d\n", rc); 3365 return (rc); 3366 } 3367 3368 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "fwq", CTLFLAG_RD, 3369 NULL, "firmware event queue"); 3370 add_iq_sysctls(&sc->ctx, oid, fwq); 3371 3372 return (0); 3373 } 3374 3375 static int 3376 free_fwq(struct adapter *sc) 3377 { 3378 return free_iq_fl(NULL, &sc->sge.fwq, NULL); 3379 } 3380 3381 static int 3382 alloc_ctrlq(struct adapter *sc, struct sge_wrq *ctrlq, int idx, 3383 struct sysctl_oid *oid) 3384 { 3385 int rc; 3386 char name[16]; 3387 struct sysctl_oid_list *children; 3388 3389 snprintf(name, sizeof(name), "%s ctrlq%d", device_get_nameunit(sc->dev), 3390 idx); 3391 init_eq(sc, &ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE, sc->port[idx]->tx_chan, 3392 sc->sge.fwq.cntxt_id, name); 3393 3394 children = SYSCTL_CHILDREN(oid); 3395 snprintf(name, sizeof(name), "%d", idx); 3396 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, name, CTLFLAG_RD, 3397 NULL, "ctrl queue"); 3398 rc = alloc_wrq(sc, NULL, ctrlq, oid); 3399 3400 return (rc); 3401 } 3402 3403 int 3404 tnl_cong(struct port_info *pi, int drop) 3405 { 3406 3407 if (drop == -1) 3408 return (-1); 3409 else if (drop == 1) 3410 return (0); 3411 else 3412 return (pi->rx_e_chan_map); 3413 } 3414 3415 static int 3416 alloc_rxq(struct vi_info *vi, struct sge_rxq *rxq, int intr_idx, int idx, 3417 struct sysctl_oid *oid) 3418 { 3419 int rc; 3420 struct adapter *sc = vi->pi->adapter; 3421 struct sysctl_oid_list *children; 3422 char name[16]; 3423 3424 rc = alloc_iq_fl(vi, &rxq->iq, &rxq->fl, intr_idx, 3425 tnl_cong(vi->pi, cong_drop)); 3426 if (rc != 0) 3427 return (rc); 3428 3429 if (idx == 0) 3430 sc->sge.iq_base = rxq->iq.abs_id - rxq->iq.cntxt_id; 3431 else 3432 KASSERT(rxq->iq.cntxt_id + sc->sge.iq_base == rxq->iq.abs_id, 3433 ("iq_base mismatch")); 3434 KASSERT(sc->sge.iq_base == 0 || sc->flags & IS_VF, 3435 ("PF with non-zero iq_base")); 3436 3437 /* 3438 * The freelist is just barely above the starvation threshold right now, 3439 * fill it up a bit more. 3440 */ 3441 FL_LOCK(&rxq->fl); 3442 refill_fl(sc, &rxq->fl, 128); 3443 FL_UNLOCK(&rxq->fl); 3444 3445 #if defined(INET) || defined(INET6) 3446 rc = tcp_lro_init_args(&rxq->lro, vi->ifp, lro_entries, lro_mbufs); 3447 if (rc != 0) 3448 return (rc); 3449 MPASS(rxq->lro.ifp == vi->ifp); /* also indicates LRO init'ed */ 3450 3451 if (vi->ifp->if_capenable & IFCAP_LRO) 3452 rxq->iq.flags |= IQ_LRO_ENABLED; 3453 #endif 3454 if (vi->ifp->if_capenable & IFCAP_HWRXTSTMP) 3455 rxq->iq.flags |= IQ_RX_TIMESTAMP; 3456 rxq->ifp = vi->ifp; 3457 3458 children = SYSCTL_CHILDREN(oid); 3459 3460 snprintf(name, sizeof(name), "%d", idx); 3461 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 3462 NULL, "rx queue"); 3463 children = SYSCTL_CHILDREN(oid); 3464 3465 add_iq_sysctls(&vi->ctx, oid, &rxq->iq); 3466 #if defined(INET) || defined(INET6) 3467 SYSCTL_ADD_U64(&vi->ctx, children, OID_AUTO, "lro_queued", CTLFLAG_RD, 3468 &rxq->lro.lro_queued, 0, NULL); 3469 SYSCTL_ADD_U64(&vi->ctx, children, OID_AUTO, "lro_flushed", CTLFLAG_RD, 3470 &rxq->lro.lro_flushed, 0, NULL); 3471 #endif 3472 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "rxcsum", CTLFLAG_RD, 3473 &rxq->rxcsum, "# of times hardware assisted with checksum"); 3474 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_extraction", 3475 CTLFLAG_RD, &rxq->vlan_extraction, 3476 "# of times hardware extracted 802.1Q tag"); 3477 3478 add_fl_sysctls(sc, &vi->ctx, oid, &rxq->fl); 3479 3480 return (rc); 3481 } 3482 3483 static int 3484 free_rxq(struct vi_info *vi, struct sge_rxq *rxq) 3485 { 3486 int rc; 3487 3488 #if defined(INET) || defined(INET6) 3489 if (rxq->lro.ifp) { 3490 tcp_lro_free(&rxq->lro); 3491 rxq->lro.ifp = NULL; 3492 } 3493 #endif 3494 3495 rc = free_iq_fl(vi, &rxq->iq, &rxq->fl); 3496 if (rc == 0) 3497 bzero(rxq, sizeof(*rxq)); 3498 3499 return (rc); 3500 } 3501 3502 #ifdef TCP_OFFLOAD 3503 static int 3504 alloc_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq, 3505 int intr_idx, int idx, struct sysctl_oid *oid) 3506 { 3507 struct port_info *pi = vi->pi; 3508 int rc; 3509 struct sysctl_oid_list *children; 3510 char name[16]; 3511 3512 rc = alloc_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl, intr_idx, 0); 3513 if (rc != 0) 3514 return (rc); 3515 3516 children = SYSCTL_CHILDREN(oid); 3517 3518 snprintf(name, sizeof(name), "%d", idx); 3519 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 3520 NULL, "rx queue"); 3521 add_iq_sysctls(&vi->ctx, oid, &ofld_rxq->iq); 3522 add_fl_sysctls(pi->adapter, &vi->ctx, oid, &ofld_rxq->fl); 3523 3524 return (rc); 3525 } 3526 3527 static int 3528 free_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq) 3529 { 3530 int rc; 3531 3532 rc = free_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl); 3533 if (rc == 0) 3534 bzero(ofld_rxq, sizeof(*ofld_rxq)); 3535 3536 return (rc); 3537 } 3538 #endif 3539 3540 #ifdef DEV_NETMAP 3541 static int 3542 alloc_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq, int intr_idx, 3543 int idx, struct sysctl_oid *oid) 3544 { 3545 int rc; 3546 struct sysctl_oid_list *children; 3547 struct sysctl_ctx_list *ctx; 3548 char name[16]; 3549 size_t len; 3550 struct adapter *sc = vi->pi->adapter; 3551 struct netmap_adapter *na = NA(vi->ifp); 3552 3553 MPASS(na != NULL); 3554 3555 len = vi->qsize_rxq * IQ_ESIZE; 3556 rc = alloc_ring(sc, len, &nm_rxq->iq_desc_tag, &nm_rxq->iq_desc_map, 3557 &nm_rxq->iq_ba, (void **)&nm_rxq->iq_desc); 3558 if (rc != 0) 3559 return (rc); 3560 3561 len = na->num_rx_desc * EQ_ESIZE + sc->params.sge.spg_len; 3562 rc = alloc_ring(sc, len, &nm_rxq->fl_desc_tag, &nm_rxq->fl_desc_map, 3563 &nm_rxq->fl_ba, (void **)&nm_rxq->fl_desc); 3564 if (rc != 0) 3565 return (rc); 3566 3567 nm_rxq->vi = vi; 3568 nm_rxq->nid = idx; 3569 nm_rxq->iq_cidx = 0; 3570 nm_rxq->iq_sidx = vi->qsize_rxq - sc->params.sge.spg_len / IQ_ESIZE; 3571 nm_rxq->iq_gen = F_RSPD_GEN; 3572 nm_rxq->fl_pidx = nm_rxq->fl_cidx = 0; 3573 nm_rxq->fl_sidx = na->num_rx_desc; 3574 nm_rxq->intr_idx = intr_idx; 3575 nm_rxq->iq_cntxt_id = INVALID_NM_RXQ_CNTXT_ID; 3576 3577 ctx = &vi->ctx; 3578 children = SYSCTL_CHILDREN(oid); 3579 3580 snprintf(name, sizeof(name), "%d", idx); 3581 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, name, CTLFLAG_RD, NULL, 3582 "rx queue"); 3583 children = SYSCTL_CHILDREN(oid); 3584 3585 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "abs_id", 3586 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_abs_id, 0, sysctl_uint16, 3587 "I", "absolute id of the queue"); 3588 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 3589 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cntxt_id, 0, sysctl_uint16, 3590 "I", "SGE context id of the queue"); 3591 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx", 3592 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cidx, 0, sysctl_uint16, "I", 3593 "consumer index"); 3594 3595 children = SYSCTL_CHILDREN(oid); 3596 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL, 3597 "freelist"); 3598 children = SYSCTL_CHILDREN(oid); 3599 3600 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 3601 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->fl_cntxt_id, 0, sysctl_uint16, 3602 "I", "SGE context id of the freelist"); 3603 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, 3604 &nm_rxq->fl_cidx, 0, "consumer index"); 3605 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, 3606 &nm_rxq->fl_pidx, 0, "producer index"); 3607 3608 return (rc); 3609 } 3610 3611 3612 static int 3613 free_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq) 3614 { 3615 struct adapter *sc = vi->pi->adapter; 3616 3617 if (vi->flags & VI_INIT_DONE) 3618 MPASS(nm_rxq->iq_cntxt_id == INVALID_NM_RXQ_CNTXT_ID); 3619 else 3620 MPASS(nm_rxq->iq_cntxt_id == 0); 3621 3622 free_ring(sc, nm_rxq->iq_desc_tag, nm_rxq->iq_desc_map, nm_rxq->iq_ba, 3623 nm_rxq->iq_desc); 3624 free_ring(sc, nm_rxq->fl_desc_tag, nm_rxq->fl_desc_map, nm_rxq->fl_ba, 3625 nm_rxq->fl_desc); 3626 3627 return (0); 3628 } 3629 3630 static int 3631 alloc_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq, int iqidx, int idx, 3632 struct sysctl_oid *oid) 3633 { 3634 int rc; 3635 size_t len; 3636 struct port_info *pi = vi->pi; 3637 struct adapter *sc = pi->adapter; 3638 struct netmap_adapter *na = NA(vi->ifp); 3639 char name[16]; 3640 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3641 3642 len = na->num_tx_desc * EQ_ESIZE + sc->params.sge.spg_len; 3643 rc = alloc_ring(sc, len, &nm_txq->desc_tag, &nm_txq->desc_map, 3644 &nm_txq->ba, (void **)&nm_txq->desc); 3645 if (rc) 3646 return (rc); 3647 3648 nm_txq->pidx = nm_txq->cidx = 0; 3649 nm_txq->sidx = na->num_tx_desc; 3650 nm_txq->nid = idx; 3651 nm_txq->iqidx = iqidx; 3652 nm_txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) | 3653 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(sc->pf) | 3654 V_TXPKT_VF(vi->vin) | V_TXPKT_VF_VLD(vi->vfvld)); 3655 nm_txq->cntxt_id = INVALID_NM_TXQ_CNTXT_ID; 3656 3657 snprintf(name, sizeof(name), "%d", idx); 3658 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 3659 NULL, "netmap tx queue"); 3660 children = SYSCTL_CHILDREN(oid); 3661 3662 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 3663 &nm_txq->cntxt_id, 0, "SGE context id of the queue"); 3664 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx", 3665 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->cidx, 0, sysctl_uint16, "I", 3666 "consumer index"); 3667 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "pidx", 3668 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->pidx, 0, sysctl_uint16, "I", 3669 "producer index"); 3670 3671 return (rc); 3672 } 3673 3674 static int 3675 free_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq) 3676 { 3677 struct adapter *sc = vi->pi->adapter; 3678 3679 if (vi->flags & VI_INIT_DONE) 3680 MPASS(nm_txq->cntxt_id == INVALID_NM_TXQ_CNTXT_ID); 3681 else 3682 MPASS(nm_txq->cntxt_id == 0); 3683 3684 free_ring(sc, nm_txq->desc_tag, nm_txq->desc_map, nm_txq->ba, 3685 nm_txq->desc); 3686 3687 return (0); 3688 } 3689 #endif 3690 3691 /* 3692 * Returns a reasonable automatic cidx flush threshold for a given queue size. 3693 */ 3694 static u_int 3695 qsize_to_fthresh(int qsize) 3696 { 3697 u_int fthresh; 3698 3699 while (!powerof2(qsize)) 3700 qsize++; 3701 fthresh = ilog2(qsize); 3702 if (fthresh > X_CIDXFLUSHTHRESH_128) 3703 fthresh = X_CIDXFLUSHTHRESH_128; 3704 3705 return (fthresh); 3706 } 3707 3708 static int 3709 ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq) 3710 { 3711 int rc, cntxt_id; 3712 struct fw_eq_ctrl_cmd c; 3713 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 3714 3715 bzero(&c, sizeof(c)); 3716 3717 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | F_FW_CMD_REQUEST | 3718 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_CTRL_CMD_PFN(sc->pf) | 3719 V_FW_EQ_CTRL_CMD_VFN(0)); 3720 c.alloc_to_len16 = htobe32(F_FW_EQ_CTRL_CMD_ALLOC | 3721 F_FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c)); 3722 c.cmpliqid_eqid = htonl(V_FW_EQ_CTRL_CMD_CMPLIQID(eq->iqid)); 3723 c.physeqid_pkd = htobe32(0); 3724 c.fetchszm_to_iqid = 3725 htobe32(V_FW_EQ_CTRL_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 3726 V_FW_EQ_CTRL_CMD_PCIECHN(eq->tx_chan) | 3727 F_FW_EQ_CTRL_CMD_FETCHRO | V_FW_EQ_CTRL_CMD_IQID(eq->iqid)); 3728 c.dcaen_to_eqsize = 3729 htobe32(V_FW_EQ_CTRL_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 3730 V_FW_EQ_CTRL_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 3731 V_FW_EQ_CTRL_CMD_CIDXFTHRESH(qsize_to_fthresh(qsize)) | 3732 V_FW_EQ_CTRL_CMD_EQSIZE(qsize)); 3733 c.eqaddr = htobe64(eq->ba); 3734 3735 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3736 if (rc != 0) { 3737 device_printf(sc->dev, 3738 "failed to create control queue %d: %d\n", eq->tx_chan, rc); 3739 return (rc); 3740 } 3741 eq->flags |= EQ_ALLOCATED; 3742 3743 eq->cntxt_id = G_FW_EQ_CTRL_CMD_EQID(be32toh(c.cmpliqid_eqid)); 3744 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 3745 if (cntxt_id >= sc->sge.neq) 3746 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 3747 cntxt_id, sc->sge.neq - 1); 3748 sc->sge.eqmap[cntxt_id] = eq; 3749 3750 return (rc); 3751 } 3752 3753 static int 3754 eth_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 3755 { 3756 int rc, cntxt_id; 3757 struct fw_eq_eth_cmd c; 3758 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 3759 3760 bzero(&c, sizeof(c)); 3761 3762 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST | 3763 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) | 3764 V_FW_EQ_ETH_CMD_VFN(0)); 3765 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC | 3766 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c)); 3767 c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE | 3768 F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(vi->viid)); 3769 c.fetchszm_to_iqid = 3770 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) | 3771 V_FW_EQ_ETH_CMD_PCIECHN(eq->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO | 3772 V_FW_EQ_ETH_CMD_IQID(eq->iqid)); 3773 c.dcaen_to_eqsize = htobe32(V_FW_EQ_ETH_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 3774 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 3775 V_FW_EQ_ETH_CMD_EQSIZE(qsize)); 3776 c.eqaddr = htobe64(eq->ba); 3777 3778 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3779 if (rc != 0) { 3780 device_printf(vi->dev, 3781 "failed to create Ethernet egress queue: %d\n", rc); 3782 return (rc); 3783 } 3784 eq->flags |= EQ_ALLOCATED; 3785 3786 eq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd)); 3787 eq->abs_id = G_FW_EQ_ETH_CMD_PHYSEQID(be32toh(c.physeqid_pkd)); 3788 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 3789 if (cntxt_id >= sc->sge.neq) 3790 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 3791 cntxt_id, sc->sge.neq - 1); 3792 sc->sge.eqmap[cntxt_id] = eq; 3793 3794 return (rc); 3795 } 3796 3797 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 3798 static int 3799 ofld_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 3800 { 3801 int rc, cntxt_id; 3802 struct fw_eq_ofld_cmd c; 3803 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 3804 3805 bzero(&c, sizeof(c)); 3806 3807 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | F_FW_CMD_REQUEST | 3808 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_OFLD_CMD_PFN(sc->pf) | 3809 V_FW_EQ_OFLD_CMD_VFN(0)); 3810 c.alloc_to_len16 = htonl(F_FW_EQ_OFLD_CMD_ALLOC | 3811 F_FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c)); 3812 c.fetchszm_to_iqid = 3813 htonl(V_FW_EQ_OFLD_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 3814 V_FW_EQ_OFLD_CMD_PCIECHN(eq->tx_chan) | 3815 F_FW_EQ_OFLD_CMD_FETCHRO | V_FW_EQ_OFLD_CMD_IQID(eq->iqid)); 3816 c.dcaen_to_eqsize = 3817 htobe32(V_FW_EQ_OFLD_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 3818 V_FW_EQ_OFLD_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 3819 V_FW_EQ_OFLD_CMD_CIDXFTHRESH(qsize_to_fthresh(qsize)) | 3820 V_FW_EQ_OFLD_CMD_EQSIZE(qsize)); 3821 c.eqaddr = htobe64(eq->ba); 3822 3823 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3824 if (rc != 0) { 3825 device_printf(vi->dev, 3826 "failed to create egress queue for TCP offload: %d\n", rc); 3827 return (rc); 3828 } 3829 eq->flags |= EQ_ALLOCATED; 3830 3831 eq->cntxt_id = G_FW_EQ_OFLD_CMD_EQID(be32toh(c.eqid_pkd)); 3832 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 3833 if (cntxt_id >= sc->sge.neq) 3834 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 3835 cntxt_id, sc->sge.neq - 1); 3836 sc->sge.eqmap[cntxt_id] = eq; 3837 3838 return (rc); 3839 } 3840 #endif 3841 3842 static int 3843 alloc_eq(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 3844 { 3845 int rc, qsize; 3846 size_t len; 3847 3848 mtx_init(&eq->eq_lock, eq->lockname, NULL, MTX_DEF); 3849 3850 qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 3851 len = qsize * EQ_ESIZE; 3852 rc = alloc_ring(sc, len, &eq->desc_tag, &eq->desc_map, 3853 &eq->ba, (void **)&eq->desc); 3854 if (rc) 3855 return (rc); 3856 3857 eq->pidx = eq->cidx = eq->dbidx = 0; 3858 /* Note that equeqidx is not used with sge_wrq (OFLD/CTRL) queues. */ 3859 eq->equeqidx = 0; 3860 eq->doorbells = sc->doorbells; 3861 3862 switch (eq->flags & EQ_TYPEMASK) { 3863 case EQ_CTRL: 3864 rc = ctrl_eq_alloc(sc, eq); 3865 break; 3866 3867 case EQ_ETH: 3868 rc = eth_eq_alloc(sc, vi, eq); 3869 break; 3870 3871 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 3872 case EQ_OFLD: 3873 rc = ofld_eq_alloc(sc, vi, eq); 3874 break; 3875 #endif 3876 3877 default: 3878 panic("%s: invalid eq type %d.", __func__, 3879 eq->flags & EQ_TYPEMASK); 3880 } 3881 if (rc != 0) { 3882 device_printf(sc->dev, 3883 "failed to allocate egress queue(%d): %d\n", 3884 eq->flags & EQ_TYPEMASK, rc); 3885 } 3886 3887 if (isset(&eq->doorbells, DOORBELL_UDB) || 3888 isset(&eq->doorbells, DOORBELL_UDBWC) || 3889 isset(&eq->doorbells, DOORBELL_WCWR)) { 3890 uint32_t s_qpp = sc->params.sge.eq_s_qpp; 3891 uint32_t mask = (1 << s_qpp) - 1; 3892 volatile uint8_t *udb; 3893 3894 udb = sc->udbs_base + UDBS_DB_OFFSET; 3895 udb += (eq->cntxt_id >> s_qpp) << PAGE_SHIFT; /* pg offset */ 3896 eq->udb_qid = eq->cntxt_id & mask; /* id in page */ 3897 if (eq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE) 3898 clrbit(&eq->doorbells, DOORBELL_WCWR); 3899 else { 3900 udb += eq->udb_qid << UDBS_SEG_SHIFT; /* seg offset */ 3901 eq->udb_qid = 0; 3902 } 3903 eq->udb = (volatile void *)udb; 3904 } 3905 3906 return (rc); 3907 } 3908 3909 static int 3910 free_eq(struct adapter *sc, struct sge_eq *eq) 3911 { 3912 int rc; 3913 3914 if (eq->flags & EQ_ALLOCATED) { 3915 switch (eq->flags & EQ_TYPEMASK) { 3916 case EQ_CTRL: 3917 rc = -t4_ctrl_eq_free(sc, sc->mbox, sc->pf, 0, 3918 eq->cntxt_id); 3919 break; 3920 3921 case EQ_ETH: 3922 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0, 3923 eq->cntxt_id); 3924 break; 3925 3926 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 3927 case EQ_OFLD: 3928 rc = -t4_ofld_eq_free(sc, sc->mbox, sc->pf, 0, 3929 eq->cntxt_id); 3930 break; 3931 #endif 3932 3933 default: 3934 panic("%s: invalid eq type %d.", __func__, 3935 eq->flags & EQ_TYPEMASK); 3936 } 3937 if (rc != 0) { 3938 device_printf(sc->dev, 3939 "failed to free egress queue (%d): %d\n", 3940 eq->flags & EQ_TYPEMASK, rc); 3941 return (rc); 3942 } 3943 eq->flags &= ~EQ_ALLOCATED; 3944 } 3945 3946 free_ring(sc, eq->desc_tag, eq->desc_map, eq->ba, eq->desc); 3947 3948 if (mtx_initialized(&eq->eq_lock)) 3949 mtx_destroy(&eq->eq_lock); 3950 3951 bzero(eq, sizeof(*eq)); 3952 return (0); 3953 } 3954 3955 static int 3956 alloc_wrq(struct adapter *sc, struct vi_info *vi, struct sge_wrq *wrq, 3957 struct sysctl_oid *oid) 3958 { 3959 int rc; 3960 struct sysctl_ctx_list *ctx = vi ? &vi->ctx : &sc->ctx; 3961 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3962 3963 rc = alloc_eq(sc, vi, &wrq->eq); 3964 if (rc) 3965 return (rc); 3966 3967 wrq->adapter = sc; 3968 TASK_INIT(&wrq->wrq_tx_task, 0, wrq_tx_drain, wrq); 3969 TAILQ_INIT(&wrq->incomplete_wrs); 3970 STAILQ_INIT(&wrq->wr_list); 3971 wrq->nwr_pending = 0; 3972 wrq->ndesc_needed = 0; 3973 3974 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, 3975 &wrq->eq.ba, "bus address of descriptor ring"); 3976 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3977 wrq->eq.sidx * EQ_ESIZE + sc->params.sge.spg_len, 3978 "desc ring size in bytes"); 3979 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 3980 &wrq->eq.cntxt_id, 0, "SGE context id of the queue"); 3981 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx", 3982 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.cidx, 0, sysctl_uint16, "I", 3983 "consumer index"); 3984 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pidx", 3985 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.pidx, 0, sysctl_uint16, "I", 3986 "producer index"); 3987 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL, 3988 wrq->eq.sidx, "status page index"); 3989 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_direct", CTLFLAG_RD, 3990 &wrq->tx_wrs_direct, "# of work requests (direct)"); 3991 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_copied", CTLFLAG_RD, 3992 &wrq->tx_wrs_copied, "# of work requests (copied)"); 3993 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_sspace", CTLFLAG_RD, 3994 &wrq->tx_wrs_ss, "# of work requests (copied from scratch space)"); 3995 3996 return (rc); 3997 } 3998 3999 static int 4000 free_wrq(struct adapter *sc, struct sge_wrq *wrq) 4001 { 4002 int rc; 4003 4004 rc = free_eq(sc, &wrq->eq); 4005 if (rc) 4006 return (rc); 4007 4008 bzero(wrq, sizeof(*wrq)); 4009 return (0); 4010 } 4011 4012 static int 4013 alloc_txq(struct vi_info *vi, struct sge_txq *txq, int idx, 4014 struct sysctl_oid *oid) 4015 { 4016 int rc; 4017 struct port_info *pi = vi->pi; 4018 struct adapter *sc = pi->adapter; 4019 struct sge_eq *eq = &txq->eq; 4020 char name[16]; 4021 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 4022 4023 rc = mp_ring_alloc(&txq->r, eq->sidx, txq, eth_tx, can_resume_eth_tx, 4024 M_CXGBE, M_WAITOK); 4025 if (rc != 0) { 4026 device_printf(sc->dev, "failed to allocate mp_ring: %d\n", rc); 4027 return (rc); 4028 } 4029 4030 rc = alloc_eq(sc, vi, eq); 4031 if (rc != 0) { 4032 mp_ring_free(txq->r); 4033 txq->r = NULL; 4034 return (rc); 4035 } 4036 4037 /* Can't fail after this point. */ 4038 4039 if (idx == 0) 4040 sc->sge.eq_base = eq->abs_id - eq->cntxt_id; 4041 else 4042 KASSERT(eq->cntxt_id + sc->sge.eq_base == eq->abs_id, 4043 ("eq_base mismatch")); 4044 KASSERT(sc->sge.eq_base == 0 || sc->flags & IS_VF, 4045 ("PF with non-zero eq_base")); 4046 4047 TASK_INIT(&txq->tx_reclaim_task, 0, tx_reclaim, eq); 4048 txq->ifp = vi->ifp; 4049 txq->gl = sglist_alloc(TX_SGL_SEGS, M_WAITOK); 4050 if (sc->flags & IS_VF) 4051 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) | 4052 V_TXPKT_INTF(pi->tx_chan)); 4053 else 4054 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) | 4055 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(sc->pf) | 4056 V_TXPKT_VF(vi->vin) | V_TXPKT_VF_VLD(vi->vfvld)); 4057 txq->tc_idx = -1; 4058 txq->sdesc = malloc(eq->sidx * sizeof(struct tx_sdesc), M_CXGBE, 4059 M_ZERO | M_WAITOK); 4060 4061 snprintf(name, sizeof(name), "%d", idx); 4062 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 4063 NULL, "tx queue"); 4064 children = SYSCTL_CHILDREN(oid); 4065 4066 SYSCTL_ADD_UAUTO(&vi->ctx, children, OID_AUTO, "ba", CTLFLAG_RD, 4067 &eq->ba, "bus address of descriptor ring"); 4068 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 4069 eq->sidx * EQ_ESIZE + sc->params.sge.spg_len, 4070 "desc ring size in bytes"); 4071 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "abs_id", CTLFLAG_RD, 4072 &eq->abs_id, 0, "absolute id of the queue"); 4073 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 4074 &eq->cntxt_id, 0, "SGE context id of the queue"); 4075 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx", 4076 CTLTYPE_INT | CTLFLAG_RD, &eq->cidx, 0, sysctl_uint16, "I", 4077 "consumer index"); 4078 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "pidx", 4079 CTLTYPE_INT | CTLFLAG_RD, &eq->pidx, 0, sysctl_uint16, "I", 4080 "producer index"); 4081 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL, 4082 eq->sidx, "status page index"); 4083 4084 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "tc", 4085 CTLTYPE_INT | CTLFLAG_RW, vi, idx, sysctl_tc, "I", 4086 "traffic class (-1 means none)"); 4087 4088 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txcsum", CTLFLAG_RD, 4089 &txq->txcsum, "# of times hardware assisted with checksum"); 4090 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_insertion", 4091 CTLFLAG_RD, &txq->vlan_insertion, 4092 "# of times hardware inserted 802.1Q tag"); 4093 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "tso_wrs", CTLFLAG_RD, 4094 &txq->tso_wrs, "# of TSO work requests"); 4095 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "imm_wrs", CTLFLAG_RD, 4096 &txq->imm_wrs, "# of work requests with immediate data"); 4097 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "sgl_wrs", CTLFLAG_RD, 4098 &txq->sgl_wrs, "# of work requests with direct SGL"); 4099 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkt_wrs", CTLFLAG_RD, 4100 &txq->txpkt_wrs, "# of txpkt work requests (one pkt/WR)"); 4101 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_wrs", 4102 CTLFLAG_RD, &txq->txpkts0_wrs, 4103 "# of txpkts (type 0) work requests"); 4104 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_wrs", 4105 CTLFLAG_RD, &txq->txpkts1_wrs, 4106 "# of txpkts (type 1) work requests"); 4107 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_pkts", 4108 CTLFLAG_RD, &txq->txpkts0_pkts, 4109 "# of frames tx'd using type0 txpkts work requests"); 4110 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_pkts", 4111 CTLFLAG_RD, &txq->txpkts1_pkts, 4112 "# of frames tx'd using type1 txpkts work requests"); 4113 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "raw_wrs", CTLFLAG_RD, 4114 &txq->raw_wrs, "# of raw work requests (non-packets)"); 4115 4116 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_enqueues", 4117 CTLFLAG_RD, &txq->r->enqueues, 4118 "# of enqueues to the mp_ring for this queue"); 4119 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_drops", 4120 CTLFLAG_RD, &txq->r->drops, 4121 "# of drops in the mp_ring for this queue"); 4122 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_starts", 4123 CTLFLAG_RD, &txq->r->starts, 4124 "# of normal consumer starts in the mp_ring for this queue"); 4125 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_stalls", 4126 CTLFLAG_RD, &txq->r->stalls, 4127 "# of consumer stalls in the mp_ring for this queue"); 4128 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_restarts", 4129 CTLFLAG_RD, &txq->r->restarts, 4130 "# of consumer restarts in the mp_ring for this queue"); 4131 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_abdications", 4132 CTLFLAG_RD, &txq->r->abdications, 4133 "# of consumer abdications in the mp_ring for this queue"); 4134 4135 return (0); 4136 } 4137 4138 static int 4139 free_txq(struct vi_info *vi, struct sge_txq *txq) 4140 { 4141 int rc; 4142 struct adapter *sc = vi->pi->adapter; 4143 struct sge_eq *eq = &txq->eq; 4144 4145 rc = free_eq(sc, eq); 4146 if (rc) 4147 return (rc); 4148 4149 sglist_free(txq->gl); 4150 free(txq->sdesc, M_CXGBE); 4151 mp_ring_free(txq->r); 4152 4153 bzero(txq, sizeof(*txq)); 4154 return (0); 4155 } 4156 4157 static void 4158 oneseg_dma_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error) 4159 { 4160 bus_addr_t *ba = arg; 4161 4162 KASSERT(nseg == 1, 4163 ("%s meant for single segment mappings only.", __func__)); 4164 4165 *ba = error ? 0 : segs->ds_addr; 4166 } 4167 4168 static inline void 4169 ring_fl_db(struct adapter *sc, struct sge_fl *fl) 4170 { 4171 uint32_t n, v; 4172 4173 n = IDXDIFF(fl->pidx / 8, fl->dbidx, fl->sidx); 4174 MPASS(n > 0); 4175 4176 wmb(); 4177 v = fl->dbval | V_PIDX(n); 4178 if (fl->udb) 4179 *fl->udb = htole32(v); 4180 else 4181 t4_write_reg(sc, sc->sge_kdoorbell_reg, v); 4182 IDXINCR(fl->dbidx, n, fl->sidx); 4183 } 4184 4185 /* 4186 * Fills up the freelist by allocating up to 'n' buffers. Buffers that are 4187 * recycled do not count towards this allocation budget. 4188 * 4189 * Returns non-zero to indicate that this freelist should be added to the list 4190 * of starving freelists. 4191 */ 4192 static int 4193 refill_fl(struct adapter *sc, struct sge_fl *fl, int n) 4194 { 4195 __be64 *d; 4196 struct fl_sdesc *sd; 4197 uintptr_t pa; 4198 caddr_t cl; 4199 struct cluster_layout *cll; 4200 struct sw_zone_info *swz; 4201 struct cluster_metadata *clm; 4202 uint16_t max_pidx; 4203 uint16_t hw_cidx = fl->hw_cidx; /* stable snapshot */ 4204 4205 FL_LOCK_ASSERT_OWNED(fl); 4206 4207 /* 4208 * We always stop at the beginning of the hardware descriptor that's just 4209 * before the one with the hw cidx. This is to avoid hw pidx = hw cidx, 4210 * which would mean an empty freelist to the chip. 4211 */ 4212 max_pidx = __predict_false(hw_cidx == 0) ? fl->sidx - 1 : hw_cidx - 1; 4213 if (fl->pidx == max_pidx * 8) 4214 return (0); 4215 4216 d = &fl->desc[fl->pidx]; 4217 sd = &fl->sdesc[fl->pidx]; 4218 cll = &fl->cll_def; /* default layout */ 4219 swz = &sc->sge.sw_zone_info[cll->zidx]; 4220 4221 while (n > 0) { 4222 4223 if (sd->cl != NULL) { 4224 4225 if (sd->nmbuf == 0) { 4226 /* 4227 * Fast recycle without involving any atomics on 4228 * the cluster's metadata (if the cluster has 4229 * metadata). This happens when all frames 4230 * received in the cluster were small enough to 4231 * fit within a single mbuf each. 4232 */ 4233 fl->cl_fast_recycled++; 4234 #ifdef INVARIANTS 4235 clm = cl_metadata(sc, fl, &sd->cll, sd->cl); 4236 if (clm != NULL) 4237 MPASS(clm->refcount == 1); 4238 #endif 4239 goto recycled_fast; 4240 } 4241 4242 /* 4243 * Cluster is guaranteed to have metadata. Clusters 4244 * without metadata always take the fast recycle path 4245 * when they're recycled. 4246 */ 4247 clm = cl_metadata(sc, fl, &sd->cll, sd->cl); 4248 MPASS(clm != NULL); 4249 4250 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) { 4251 fl->cl_recycled++; 4252 counter_u64_add(extfree_rels, 1); 4253 goto recycled; 4254 } 4255 sd->cl = NULL; /* gave up my reference */ 4256 } 4257 MPASS(sd->cl == NULL); 4258 alloc: 4259 cl = uma_zalloc(swz->zone, M_NOWAIT); 4260 if (__predict_false(cl == NULL)) { 4261 if (cll == &fl->cll_alt || fl->cll_alt.zidx == -1 || 4262 fl->cll_def.zidx == fl->cll_alt.zidx) 4263 break; 4264 4265 /* fall back to the safe zone */ 4266 cll = &fl->cll_alt; 4267 swz = &sc->sge.sw_zone_info[cll->zidx]; 4268 goto alloc; 4269 } 4270 fl->cl_allocated++; 4271 n--; 4272 4273 pa = pmap_kextract((vm_offset_t)cl); 4274 pa += cll->region1; 4275 sd->cl = cl; 4276 sd->cll = *cll; 4277 *d = htobe64(pa | cll->hwidx); 4278 clm = cl_metadata(sc, fl, cll, cl); 4279 if (clm != NULL) { 4280 recycled: 4281 #ifdef INVARIANTS 4282 clm->sd = sd; 4283 #endif 4284 clm->refcount = 1; 4285 } 4286 sd->nmbuf = 0; 4287 recycled_fast: 4288 d++; 4289 sd++; 4290 if (__predict_false(++fl->pidx % 8 == 0)) { 4291 uint16_t pidx = fl->pidx / 8; 4292 4293 if (__predict_false(pidx == fl->sidx)) { 4294 fl->pidx = 0; 4295 pidx = 0; 4296 sd = fl->sdesc; 4297 d = fl->desc; 4298 } 4299 if (pidx == max_pidx) 4300 break; 4301 4302 if (IDXDIFF(pidx, fl->dbidx, fl->sidx) >= 4) 4303 ring_fl_db(sc, fl); 4304 } 4305 } 4306 4307 if (fl->pidx / 8 != fl->dbidx) 4308 ring_fl_db(sc, fl); 4309 4310 return (FL_RUNNING_LOW(fl) && !(fl->flags & FL_STARVING)); 4311 } 4312 4313 /* 4314 * Attempt to refill all starving freelists. 4315 */ 4316 static void 4317 refill_sfl(void *arg) 4318 { 4319 struct adapter *sc = arg; 4320 struct sge_fl *fl, *fl_temp; 4321 4322 mtx_assert(&sc->sfl_lock, MA_OWNED); 4323 TAILQ_FOREACH_SAFE(fl, &sc->sfl, link, fl_temp) { 4324 FL_LOCK(fl); 4325 refill_fl(sc, fl, 64); 4326 if (FL_NOT_RUNNING_LOW(fl) || fl->flags & FL_DOOMED) { 4327 TAILQ_REMOVE(&sc->sfl, fl, link); 4328 fl->flags &= ~FL_STARVING; 4329 } 4330 FL_UNLOCK(fl); 4331 } 4332 4333 if (!TAILQ_EMPTY(&sc->sfl)) 4334 callout_schedule(&sc->sfl_callout, hz / 5); 4335 } 4336 4337 static int 4338 alloc_fl_sdesc(struct sge_fl *fl) 4339 { 4340 4341 fl->sdesc = malloc(fl->sidx * 8 * sizeof(struct fl_sdesc), M_CXGBE, 4342 M_ZERO | M_WAITOK); 4343 4344 return (0); 4345 } 4346 4347 static void 4348 free_fl_sdesc(struct adapter *sc, struct sge_fl *fl) 4349 { 4350 struct fl_sdesc *sd; 4351 struct cluster_metadata *clm; 4352 struct cluster_layout *cll; 4353 int i; 4354 4355 sd = fl->sdesc; 4356 for (i = 0; i < fl->sidx * 8; i++, sd++) { 4357 if (sd->cl == NULL) 4358 continue; 4359 4360 cll = &sd->cll; 4361 clm = cl_metadata(sc, fl, cll, sd->cl); 4362 if (sd->nmbuf == 0) 4363 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl); 4364 else if (clm && atomic_fetchadd_int(&clm->refcount, -1) == 1) { 4365 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl); 4366 counter_u64_add(extfree_rels, 1); 4367 } 4368 sd->cl = NULL; 4369 } 4370 4371 free(fl->sdesc, M_CXGBE); 4372 fl->sdesc = NULL; 4373 } 4374 4375 static inline void 4376 get_pkt_gl(struct mbuf *m, struct sglist *gl) 4377 { 4378 int rc; 4379 4380 M_ASSERTPKTHDR(m); 4381 4382 sglist_reset(gl); 4383 rc = sglist_append_mbuf(gl, m); 4384 if (__predict_false(rc != 0)) { 4385 panic("%s: mbuf %p (%d segs) was vetted earlier but now fails " 4386 "with %d.", __func__, m, mbuf_nsegs(m), rc); 4387 } 4388 4389 KASSERT(gl->sg_nseg == mbuf_nsegs(m), 4390 ("%s: nsegs changed for mbuf %p from %d to %d", __func__, m, 4391 mbuf_nsegs(m), gl->sg_nseg)); 4392 KASSERT(gl->sg_nseg > 0 && 4393 gl->sg_nseg <= (needs_tso(m) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS), 4394 ("%s: %d segments, should have been 1 <= nsegs <= %d", __func__, 4395 gl->sg_nseg, needs_tso(m) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS)); 4396 } 4397 4398 /* 4399 * len16 for a txpkt WR with a GL. Includes the firmware work request header. 4400 */ 4401 static inline u_int 4402 txpkt_len16(u_int nsegs, u_int tso) 4403 { 4404 u_int n; 4405 4406 MPASS(nsegs > 0); 4407 4408 nsegs--; /* first segment is part of ulptx_sgl */ 4409 n = sizeof(struct fw_eth_tx_pkt_wr) + sizeof(struct cpl_tx_pkt_core) + 4410 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 4411 if (tso) 4412 n += sizeof(struct cpl_tx_pkt_lso_core); 4413 4414 return (howmany(n, 16)); 4415 } 4416 4417 /* 4418 * len16 for a txpkt_vm WR with a GL. Includes the firmware work 4419 * request header. 4420 */ 4421 static inline u_int 4422 txpkt_vm_len16(u_int nsegs, u_int tso) 4423 { 4424 u_int n; 4425 4426 MPASS(nsegs > 0); 4427 4428 nsegs--; /* first segment is part of ulptx_sgl */ 4429 n = sizeof(struct fw_eth_tx_pkt_vm_wr) + 4430 sizeof(struct cpl_tx_pkt_core) + 4431 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 4432 if (tso) 4433 n += sizeof(struct cpl_tx_pkt_lso_core); 4434 4435 return (howmany(n, 16)); 4436 } 4437 4438 /* 4439 * len16 for a txpkts type 0 WR with a GL. Does not include the firmware work 4440 * request header. 4441 */ 4442 static inline u_int 4443 txpkts0_len16(u_int nsegs) 4444 { 4445 u_int n; 4446 4447 MPASS(nsegs > 0); 4448 4449 nsegs--; /* first segment is part of ulptx_sgl */ 4450 n = sizeof(struct ulp_txpkt) + sizeof(struct ulptx_idata) + 4451 sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl) + 4452 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 4453 4454 return (howmany(n, 16)); 4455 } 4456 4457 /* 4458 * len16 for a txpkts type 1 WR with a GL. Does not include the firmware work 4459 * request header. 4460 */ 4461 static inline u_int 4462 txpkts1_len16(void) 4463 { 4464 u_int n; 4465 4466 n = sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl); 4467 4468 return (howmany(n, 16)); 4469 } 4470 4471 static inline u_int 4472 imm_payload(u_int ndesc) 4473 { 4474 u_int n; 4475 4476 n = ndesc * EQ_ESIZE - sizeof(struct fw_eth_tx_pkt_wr) - 4477 sizeof(struct cpl_tx_pkt_core); 4478 4479 return (n); 4480 } 4481 4482 /* 4483 * Write a VM txpkt WR for this packet to the hardware descriptors, update the 4484 * software descriptor, and advance the pidx. It is guaranteed that enough 4485 * descriptors are available. 4486 * 4487 * The return value is the # of hardware descriptors used. 4488 */ 4489 static u_int 4490 write_txpkt_vm_wr(struct adapter *sc, struct sge_txq *txq, 4491 struct fw_eth_tx_pkt_vm_wr *wr, struct mbuf *m0, u_int available) 4492 { 4493 struct sge_eq *eq = &txq->eq; 4494 struct tx_sdesc *txsd; 4495 struct cpl_tx_pkt_core *cpl; 4496 uint32_t ctrl; /* used in many unrelated places */ 4497 uint64_t ctrl1; 4498 int csum_type, len16, ndesc, pktlen, nsegs; 4499 caddr_t dst; 4500 4501 TXQ_LOCK_ASSERT_OWNED(txq); 4502 M_ASSERTPKTHDR(m0); 4503 MPASS(available > 0 && available < eq->sidx); 4504 4505 len16 = mbuf_len16(m0); 4506 nsegs = mbuf_nsegs(m0); 4507 pktlen = m0->m_pkthdr.len; 4508 ctrl = sizeof(struct cpl_tx_pkt_core); 4509 if (needs_tso(m0)) 4510 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 4511 ndesc = howmany(len16, EQ_ESIZE / 16); 4512 MPASS(ndesc <= available); 4513 4514 /* Firmware work request header */ 4515 MPASS(wr == (void *)&eq->desc[eq->pidx]); 4516 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_VM_WR) | 4517 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl)); 4518 4519 ctrl = V_FW_WR_LEN16(len16); 4520 wr->equiq_to_len16 = htobe32(ctrl); 4521 wr->r3[0] = 0; 4522 wr->r3[1] = 0; 4523 4524 /* 4525 * Copy over ethmacdst, ethmacsrc, ethtype, and vlantci. 4526 * vlantci is ignored unless the ethtype is 0x8100, so it's 4527 * simpler to always copy it rather than making it 4528 * conditional. Also, it seems that we do not have to set 4529 * vlantci or fake the ethtype when doing VLAN tag insertion. 4530 */ 4531 m_copydata(m0, 0, sizeof(struct ether_header) + 2, wr->ethmacdst); 4532 4533 csum_type = -1; 4534 if (needs_tso(m0)) { 4535 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1); 4536 4537 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 4538 m0->m_pkthdr.l4hlen > 0, 4539 ("%s: mbuf %p needs TSO but missing header lengths", 4540 __func__, m0)); 4541 4542 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE | 4543 F_LSO_LAST_SLICE | V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) 4544 | V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2); 4545 if (m0->m_pkthdr.l2hlen == sizeof(struct ether_vlan_header)) 4546 ctrl |= V_LSO_ETHHDR_LEN(1); 4547 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 4548 ctrl |= F_LSO_IPV6; 4549 4550 lso->lso_ctrl = htobe32(ctrl); 4551 lso->ipid_ofst = htobe16(0); 4552 lso->mss = htobe16(m0->m_pkthdr.tso_segsz); 4553 lso->seqno_offset = htobe32(0); 4554 lso->len = htobe32(pktlen); 4555 4556 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 4557 csum_type = TX_CSUM_TCPIP6; 4558 else 4559 csum_type = TX_CSUM_TCPIP; 4560 4561 cpl = (void *)(lso + 1); 4562 4563 txq->tso_wrs++; 4564 } else { 4565 if (m0->m_pkthdr.csum_flags & CSUM_IP_TCP) 4566 csum_type = TX_CSUM_TCPIP; 4567 else if (m0->m_pkthdr.csum_flags & CSUM_IP_UDP) 4568 csum_type = TX_CSUM_UDPIP; 4569 else if (m0->m_pkthdr.csum_flags & CSUM_IP6_TCP) 4570 csum_type = TX_CSUM_TCPIP6; 4571 else if (m0->m_pkthdr.csum_flags & CSUM_IP6_UDP) 4572 csum_type = TX_CSUM_UDPIP6; 4573 #if defined(INET) 4574 else if (m0->m_pkthdr.csum_flags & CSUM_IP) { 4575 /* 4576 * XXX: The firmware appears to stomp on the 4577 * fragment/flags field of the IP header when 4578 * using TX_CSUM_IP. Fall back to doing 4579 * software checksums. 4580 */ 4581 u_short *sump; 4582 struct mbuf *m; 4583 int offset; 4584 4585 m = m0; 4586 offset = 0; 4587 sump = m_advance(&m, &offset, m0->m_pkthdr.l2hlen + 4588 offsetof(struct ip, ip_sum)); 4589 *sump = in_cksum_skip(m0, m0->m_pkthdr.l2hlen + 4590 m0->m_pkthdr.l3hlen, m0->m_pkthdr.l2hlen); 4591 m0->m_pkthdr.csum_flags &= ~CSUM_IP; 4592 } 4593 #endif 4594 4595 cpl = (void *)(wr + 1); 4596 } 4597 4598 /* Checksum offload */ 4599 ctrl1 = 0; 4600 if (needs_l3_csum(m0) == 0) 4601 ctrl1 |= F_TXPKT_IPCSUM_DIS; 4602 if (csum_type >= 0) { 4603 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0, 4604 ("%s: mbuf %p needs checksum offload but missing header lengths", 4605 __func__, m0)); 4606 4607 if (chip_id(sc) <= CHELSIO_T5) { 4608 ctrl1 |= V_TXPKT_ETHHDR_LEN(m0->m_pkthdr.l2hlen - 4609 ETHER_HDR_LEN); 4610 } else { 4611 ctrl1 |= V_T6_TXPKT_ETHHDR_LEN(m0->m_pkthdr.l2hlen - 4612 ETHER_HDR_LEN); 4613 } 4614 ctrl1 |= V_TXPKT_IPHDR_LEN(m0->m_pkthdr.l3hlen); 4615 ctrl1 |= V_TXPKT_CSUM_TYPE(csum_type); 4616 } else 4617 ctrl1 |= F_TXPKT_L4CSUM_DIS; 4618 if (m0->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | 4619 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO)) 4620 txq->txcsum++; /* some hardware assistance provided */ 4621 4622 /* VLAN tag insertion */ 4623 if (needs_vlan_insertion(m0)) { 4624 ctrl1 |= F_TXPKT_VLAN_VLD | 4625 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 4626 txq->vlan_insertion++; 4627 } 4628 4629 /* CPL header */ 4630 cpl->ctrl0 = txq->cpl_ctrl0; 4631 cpl->pack = 0; 4632 cpl->len = htobe16(pktlen); 4633 cpl->ctrl1 = htobe64(ctrl1); 4634 4635 /* SGL */ 4636 dst = (void *)(cpl + 1); 4637 4638 /* 4639 * A packet using TSO will use up an entire descriptor for the 4640 * firmware work request header, LSO CPL, and TX_PKT_XT CPL. 4641 * If this descriptor is the last descriptor in the ring, wrap 4642 * around to the front of the ring explicitly for the start of 4643 * the sgl. 4644 */ 4645 if (dst == (void *)&eq->desc[eq->sidx]) { 4646 dst = (void *)&eq->desc[0]; 4647 write_gl_to_txd(txq, m0, &dst, 0); 4648 } else 4649 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx); 4650 txq->sgl_wrs++; 4651 4652 txq->txpkt_wrs++; 4653 4654 txsd = &txq->sdesc[eq->pidx]; 4655 txsd->m = m0; 4656 txsd->desc_used = ndesc; 4657 4658 return (ndesc); 4659 } 4660 4661 /* 4662 * Write a raw WR to the hardware descriptors, update the software 4663 * descriptor, and advance the pidx. It is guaranteed that enough 4664 * descriptors are available. 4665 * 4666 * The return value is the # of hardware descriptors used. 4667 */ 4668 static u_int 4669 write_raw_wr(struct sge_txq *txq, void *wr, struct mbuf *m0, u_int available) 4670 { 4671 struct sge_eq *eq = &txq->eq; 4672 struct tx_sdesc *txsd; 4673 struct mbuf *m; 4674 caddr_t dst; 4675 int len16, ndesc; 4676 4677 len16 = mbuf_len16(m0); 4678 ndesc = howmany(len16, EQ_ESIZE / 16); 4679 MPASS(ndesc <= available); 4680 4681 dst = wr; 4682 for (m = m0; m != NULL; m = m->m_next) 4683 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len); 4684 4685 txq->raw_wrs++; 4686 4687 txsd = &txq->sdesc[eq->pidx]; 4688 txsd->m = m0; 4689 txsd->desc_used = ndesc; 4690 4691 return (ndesc); 4692 } 4693 4694 /* 4695 * Write a txpkt WR for this packet to the hardware descriptors, update the 4696 * software descriptor, and advance the pidx. It is guaranteed that enough 4697 * descriptors are available. 4698 * 4699 * The return value is the # of hardware descriptors used. 4700 */ 4701 static u_int 4702 write_txpkt_wr(struct sge_txq *txq, struct fw_eth_tx_pkt_wr *wr, 4703 struct mbuf *m0, u_int available) 4704 { 4705 struct sge_eq *eq = &txq->eq; 4706 struct tx_sdesc *txsd; 4707 struct cpl_tx_pkt_core *cpl; 4708 uint32_t ctrl; /* used in many unrelated places */ 4709 uint64_t ctrl1; 4710 int len16, ndesc, pktlen, nsegs; 4711 caddr_t dst; 4712 4713 TXQ_LOCK_ASSERT_OWNED(txq); 4714 M_ASSERTPKTHDR(m0); 4715 MPASS(available > 0 && available < eq->sidx); 4716 4717 len16 = mbuf_len16(m0); 4718 nsegs = mbuf_nsegs(m0); 4719 pktlen = m0->m_pkthdr.len; 4720 ctrl = sizeof(struct cpl_tx_pkt_core); 4721 if (needs_tso(m0)) 4722 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 4723 else if (pktlen <= imm_payload(2) && available >= 2) { 4724 /* Immediate data. Recalculate len16 and set nsegs to 0. */ 4725 ctrl += pktlen; 4726 len16 = howmany(sizeof(struct fw_eth_tx_pkt_wr) + 4727 sizeof(struct cpl_tx_pkt_core) + pktlen, 16); 4728 nsegs = 0; 4729 } 4730 ndesc = howmany(len16, EQ_ESIZE / 16); 4731 MPASS(ndesc <= available); 4732 4733 /* Firmware work request header */ 4734 MPASS(wr == (void *)&eq->desc[eq->pidx]); 4735 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_WR) | 4736 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl)); 4737 4738 ctrl = V_FW_WR_LEN16(len16); 4739 wr->equiq_to_len16 = htobe32(ctrl); 4740 wr->r3 = 0; 4741 4742 if (needs_tso(m0)) { 4743 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1); 4744 4745 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 4746 m0->m_pkthdr.l4hlen > 0, 4747 ("%s: mbuf %p needs TSO but missing header lengths", 4748 __func__, m0)); 4749 4750 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE | 4751 F_LSO_LAST_SLICE | V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) 4752 | V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2); 4753 if (m0->m_pkthdr.l2hlen == sizeof(struct ether_vlan_header)) 4754 ctrl |= V_LSO_ETHHDR_LEN(1); 4755 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 4756 ctrl |= F_LSO_IPV6; 4757 4758 lso->lso_ctrl = htobe32(ctrl); 4759 lso->ipid_ofst = htobe16(0); 4760 lso->mss = htobe16(m0->m_pkthdr.tso_segsz); 4761 lso->seqno_offset = htobe32(0); 4762 lso->len = htobe32(pktlen); 4763 4764 cpl = (void *)(lso + 1); 4765 4766 txq->tso_wrs++; 4767 } else 4768 cpl = (void *)(wr + 1); 4769 4770 /* Checksum offload */ 4771 ctrl1 = 0; 4772 if (needs_l3_csum(m0) == 0) 4773 ctrl1 |= F_TXPKT_IPCSUM_DIS; 4774 if (needs_l4_csum(m0) == 0) 4775 ctrl1 |= F_TXPKT_L4CSUM_DIS; 4776 if (m0->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | 4777 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO)) 4778 txq->txcsum++; /* some hardware assistance provided */ 4779 4780 /* VLAN tag insertion */ 4781 if (needs_vlan_insertion(m0)) { 4782 ctrl1 |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 4783 txq->vlan_insertion++; 4784 } 4785 4786 /* CPL header */ 4787 cpl->ctrl0 = txq->cpl_ctrl0; 4788 cpl->pack = 0; 4789 cpl->len = htobe16(pktlen); 4790 cpl->ctrl1 = htobe64(ctrl1); 4791 4792 /* SGL */ 4793 dst = (void *)(cpl + 1); 4794 if (nsegs > 0) { 4795 4796 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx); 4797 txq->sgl_wrs++; 4798 } else { 4799 struct mbuf *m; 4800 4801 for (m = m0; m != NULL; m = m->m_next) { 4802 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len); 4803 #ifdef INVARIANTS 4804 pktlen -= m->m_len; 4805 #endif 4806 } 4807 #ifdef INVARIANTS 4808 KASSERT(pktlen == 0, ("%s: %d bytes left.", __func__, pktlen)); 4809 #endif 4810 txq->imm_wrs++; 4811 } 4812 4813 txq->txpkt_wrs++; 4814 4815 txsd = &txq->sdesc[eq->pidx]; 4816 txsd->m = m0; 4817 txsd->desc_used = ndesc; 4818 4819 return (ndesc); 4820 } 4821 4822 static int 4823 try_txpkts(struct mbuf *m, struct mbuf *n, struct txpkts *txp, u_int available) 4824 { 4825 u_int needed, nsegs1, nsegs2, l1, l2; 4826 4827 if (cannot_use_txpkts(m) || cannot_use_txpkts(n)) 4828 return (1); 4829 4830 nsegs1 = mbuf_nsegs(m); 4831 nsegs2 = mbuf_nsegs(n); 4832 if (nsegs1 + nsegs2 == 2) { 4833 txp->wr_type = 1; 4834 l1 = l2 = txpkts1_len16(); 4835 } else { 4836 txp->wr_type = 0; 4837 l1 = txpkts0_len16(nsegs1); 4838 l2 = txpkts0_len16(nsegs2); 4839 } 4840 txp->len16 = howmany(sizeof(struct fw_eth_tx_pkts_wr), 16) + l1 + l2; 4841 needed = howmany(txp->len16, EQ_ESIZE / 16); 4842 if (needed > SGE_MAX_WR_NDESC || needed > available) 4843 return (1); 4844 4845 txp->plen = m->m_pkthdr.len + n->m_pkthdr.len; 4846 if (txp->plen > 65535) 4847 return (1); 4848 4849 txp->npkt = 2; 4850 set_mbuf_len16(m, l1); 4851 set_mbuf_len16(n, l2); 4852 4853 return (0); 4854 } 4855 4856 static int 4857 add_to_txpkts(struct mbuf *m, struct txpkts *txp, u_int available) 4858 { 4859 u_int plen, len16, needed, nsegs; 4860 4861 MPASS(txp->wr_type == 0 || txp->wr_type == 1); 4862 4863 if (cannot_use_txpkts(m)) 4864 return (1); 4865 4866 nsegs = mbuf_nsegs(m); 4867 if (txp->wr_type == 1 && nsegs != 1) 4868 return (1); 4869 4870 plen = txp->plen + m->m_pkthdr.len; 4871 if (plen > 65535) 4872 return (1); 4873 4874 if (txp->wr_type == 0) 4875 len16 = txpkts0_len16(nsegs); 4876 else 4877 len16 = txpkts1_len16(); 4878 needed = howmany(txp->len16 + len16, EQ_ESIZE / 16); 4879 if (needed > SGE_MAX_WR_NDESC || needed > available) 4880 return (1); 4881 4882 txp->npkt++; 4883 txp->plen = plen; 4884 txp->len16 += len16; 4885 set_mbuf_len16(m, len16); 4886 4887 return (0); 4888 } 4889 4890 /* 4891 * Write a txpkts WR for the packets in txp to the hardware descriptors, update 4892 * the software descriptor, and advance the pidx. It is guaranteed that enough 4893 * descriptors are available. 4894 * 4895 * The return value is the # of hardware descriptors used. 4896 */ 4897 static u_int 4898 write_txpkts_wr(struct sge_txq *txq, struct fw_eth_tx_pkts_wr *wr, 4899 struct mbuf *m0, const struct txpkts *txp, u_int available) 4900 { 4901 struct sge_eq *eq = &txq->eq; 4902 struct tx_sdesc *txsd; 4903 struct cpl_tx_pkt_core *cpl; 4904 uint32_t ctrl; 4905 uint64_t ctrl1; 4906 int ndesc, checkwrap; 4907 struct mbuf *m; 4908 void *flitp; 4909 4910 TXQ_LOCK_ASSERT_OWNED(txq); 4911 MPASS(txp->npkt > 0); 4912 MPASS(txp->plen < 65536); 4913 MPASS(m0 != NULL); 4914 MPASS(m0->m_nextpkt != NULL); 4915 MPASS(txp->len16 <= howmany(SGE_MAX_WR_LEN, 16)); 4916 MPASS(available > 0 && available < eq->sidx); 4917 4918 ndesc = howmany(txp->len16, EQ_ESIZE / 16); 4919 MPASS(ndesc <= available); 4920 4921 MPASS(wr == (void *)&eq->desc[eq->pidx]); 4922 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR)); 4923 ctrl = V_FW_WR_LEN16(txp->len16); 4924 wr->equiq_to_len16 = htobe32(ctrl); 4925 wr->plen = htobe16(txp->plen); 4926 wr->npkt = txp->npkt; 4927 wr->r3 = 0; 4928 wr->type = txp->wr_type; 4929 flitp = wr + 1; 4930 4931 /* 4932 * At this point we are 16B into a hardware descriptor. If checkwrap is 4933 * set then we know the WR is going to wrap around somewhere. We'll 4934 * check for that at appropriate points. 4935 */ 4936 checkwrap = eq->sidx - ndesc < eq->pidx; 4937 for (m = m0; m != NULL; m = m->m_nextpkt) { 4938 if (txp->wr_type == 0) { 4939 struct ulp_txpkt *ulpmc; 4940 struct ulptx_idata *ulpsc; 4941 4942 /* ULP master command */ 4943 ulpmc = flitp; 4944 ulpmc->cmd_dest = htobe32(V_ULPTX_CMD(ULP_TX_PKT) | 4945 V_ULP_TXPKT_DEST(0) | V_ULP_TXPKT_FID(eq->iqid)); 4946 ulpmc->len = htobe32(mbuf_len16(m)); 4947 4948 /* ULP subcommand */ 4949 ulpsc = (void *)(ulpmc + 1); 4950 ulpsc->cmd_more = htobe32(V_ULPTX_CMD(ULP_TX_SC_IMM) | 4951 F_ULP_TX_SC_MORE); 4952 ulpsc->len = htobe32(sizeof(struct cpl_tx_pkt_core)); 4953 4954 cpl = (void *)(ulpsc + 1); 4955 if (checkwrap && 4956 (uintptr_t)cpl == (uintptr_t)&eq->desc[eq->sidx]) 4957 cpl = (void *)&eq->desc[0]; 4958 } else { 4959 cpl = flitp; 4960 } 4961 4962 /* Checksum offload */ 4963 ctrl1 = 0; 4964 if (needs_l3_csum(m) == 0) 4965 ctrl1 |= F_TXPKT_IPCSUM_DIS; 4966 if (needs_l4_csum(m) == 0) 4967 ctrl1 |= F_TXPKT_L4CSUM_DIS; 4968 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | 4969 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO)) 4970 txq->txcsum++; /* some hardware assistance provided */ 4971 4972 /* VLAN tag insertion */ 4973 if (needs_vlan_insertion(m)) { 4974 ctrl1 |= F_TXPKT_VLAN_VLD | 4975 V_TXPKT_VLAN(m->m_pkthdr.ether_vtag); 4976 txq->vlan_insertion++; 4977 } 4978 4979 /* CPL header */ 4980 cpl->ctrl0 = txq->cpl_ctrl0; 4981 cpl->pack = 0; 4982 cpl->len = htobe16(m->m_pkthdr.len); 4983 cpl->ctrl1 = htobe64(ctrl1); 4984 4985 flitp = cpl + 1; 4986 if (checkwrap && 4987 (uintptr_t)flitp == (uintptr_t)&eq->desc[eq->sidx]) 4988 flitp = (void *)&eq->desc[0]; 4989 4990 write_gl_to_txd(txq, m, (caddr_t *)(&flitp), checkwrap); 4991 4992 } 4993 4994 if (txp->wr_type == 0) { 4995 txq->txpkts0_pkts += txp->npkt; 4996 txq->txpkts0_wrs++; 4997 } else { 4998 txq->txpkts1_pkts += txp->npkt; 4999 txq->txpkts1_wrs++; 5000 } 5001 5002 txsd = &txq->sdesc[eq->pidx]; 5003 txsd->m = m0; 5004 txsd->desc_used = ndesc; 5005 5006 return (ndesc); 5007 } 5008 5009 /* 5010 * If the SGL ends on an address that is not 16 byte aligned, this function will 5011 * add a 0 filled flit at the end. 5012 */ 5013 static void 5014 write_gl_to_txd(struct sge_txq *txq, struct mbuf *m, caddr_t *to, int checkwrap) 5015 { 5016 struct sge_eq *eq = &txq->eq; 5017 struct sglist *gl = txq->gl; 5018 struct sglist_seg *seg; 5019 __be64 *flitp, *wrap; 5020 struct ulptx_sgl *usgl; 5021 int i, nflits, nsegs; 5022 5023 KASSERT(((uintptr_t)(*to) & 0xf) == 0, 5024 ("%s: SGL must start at a 16 byte boundary: %p", __func__, *to)); 5025 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]); 5026 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]); 5027 5028 get_pkt_gl(m, gl); 5029 nsegs = gl->sg_nseg; 5030 MPASS(nsegs > 0); 5031 5032 nflits = (3 * (nsegs - 1)) / 2 + ((nsegs - 1) & 1) + 2; 5033 flitp = (__be64 *)(*to); 5034 wrap = (__be64 *)(&eq->desc[eq->sidx]); 5035 seg = &gl->sg_segs[0]; 5036 usgl = (void *)flitp; 5037 5038 /* 5039 * We start at a 16 byte boundary somewhere inside the tx descriptor 5040 * ring, so we're at least 16 bytes away from the status page. There is 5041 * no chance of a wrap around in the middle of usgl (which is 16 bytes). 5042 */ 5043 5044 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 5045 V_ULPTX_NSGE(nsegs)); 5046 usgl->len0 = htobe32(seg->ss_len); 5047 usgl->addr0 = htobe64(seg->ss_paddr); 5048 seg++; 5049 5050 if (checkwrap == 0 || (uintptr_t)(flitp + nflits) <= (uintptr_t)wrap) { 5051 5052 /* Won't wrap around at all */ 5053 5054 for (i = 0; i < nsegs - 1; i++, seg++) { 5055 usgl->sge[i / 2].len[i & 1] = htobe32(seg->ss_len); 5056 usgl->sge[i / 2].addr[i & 1] = htobe64(seg->ss_paddr); 5057 } 5058 if (i & 1) 5059 usgl->sge[i / 2].len[1] = htobe32(0); 5060 flitp += nflits; 5061 } else { 5062 5063 /* Will wrap somewhere in the rest of the SGL */ 5064 5065 /* 2 flits already written, write the rest flit by flit */ 5066 flitp = (void *)(usgl + 1); 5067 for (i = 0; i < nflits - 2; i++) { 5068 if (flitp == wrap) 5069 flitp = (void *)eq->desc; 5070 *flitp++ = get_flit(seg, nsegs - 1, i); 5071 } 5072 } 5073 5074 if (nflits & 1) { 5075 MPASS(((uintptr_t)flitp) & 0xf); 5076 *flitp++ = 0; 5077 } 5078 5079 MPASS((((uintptr_t)flitp) & 0xf) == 0); 5080 if (__predict_false(flitp == wrap)) 5081 *to = (void *)eq->desc; 5082 else 5083 *to = (void *)flitp; 5084 } 5085 5086 static inline void 5087 copy_to_txd(struct sge_eq *eq, caddr_t from, caddr_t *to, int len) 5088 { 5089 5090 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]); 5091 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]); 5092 5093 if (__predict_true((uintptr_t)(*to) + len <= 5094 (uintptr_t)&eq->desc[eq->sidx])) { 5095 bcopy(from, *to, len); 5096 (*to) += len; 5097 } else { 5098 int portion = (uintptr_t)&eq->desc[eq->sidx] - (uintptr_t)(*to); 5099 5100 bcopy(from, *to, portion); 5101 from += portion; 5102 portion = len - portion; /* remaining */ 5103 bcopy(from, (void *)eq->desc, portion); 5104 (*to) = (caddr_t)eq->desc + portion; 5105 } 5106 } 5107 5108 static inline void 5109 ring_eq_db(struct adapter *sc, struct sge_eq *eq, u_int n) 5110 { 5111 u_int db; 5112 5113 MPASS(n > 0); 5114 5115 db = eq->doorbells; 5116 if (n > 1) 5117 clrbit(&db, DOORBELL_WCWR); 5118 wmb(); 5119 5120 switch (ffs(db) - 1) { 5121 case DOORBELL_UDB: 5122 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n)); 5123 break; 5124 5125 case DOORBELL_WCWR: { 5126 volatile uint64_t *dst, *src; 5127 int i; 5128 5129 /* 5130 * Queues whose 128B doorbell segment fits in the page do not 5131 * use relative qid (udb_qid is always 0). Only queues with 5132 * doorbell segments can do WCWR. 5133 */ 5134 KASSERT(eq->udb_qid == 0 && n == 1, 5135 ("%s: inappropriate doorbell (0x%x, %d, %d) for eq %p", 5136 __func__, eq->doorbells, n, eq->dbidx, eq)); 5137 5138 dst = (volatile void *)((uintptr_t)eq->udb + UDBS_WR_OFFSET - 5139 UDBS_DB_OFFSET); 5140 i = eq->dbidx; 5141 src = (void *)&eq->desc[i]; 5142 while (src != (void *)&eq->desc[i + 1]) 5143 *dst++ = *src++; 5144 wmb(); 5145 break; 5146 } 5147 5148 case DOORBELL_UDBWC: 5149 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n)); 5150 wmb(); 5151 break; 5152 5153 case DOORBELL_KDB: 5154 t4_write_reg(sc, sc->sge_kdoorbell_reg, 5155 V_QID(eq->cntxt_id) | V_PIDX(n)); 5156 break; 5157 } 5158 5159 IDXINCR(eq->dbidx, n, eq->sidx); 5160 } 5161 5162 static inline u_int 5163 reclaimable_tx_desc(struct sge_eq *eq) 5164 { 5165 uint16_t hw_cidx; 5166 5167 hw_cidx = read_hw_cidx(eq); 5168 return (IDXDIFF(hw_cidx, eq->cidx, eq->sidx)); 5169 } 5170 5171 static inline u_int 5172 total_available_tx_desc(struct sge_eq *eq) 5173 { 5174 uint16_t hw_cidx, pidx; 5175 5176 hw_cidx = read_hw_cidx(eq); 5177 pidx = eq->pidx; 5178 5179 if (pidx == hw_cidx) 5180 return (eq->sidx - 1); 5181 else 5182 return (IDXDIFF(hw_cidx, pidx, eq->sidx) - 1); 5183 } 5184 5185 static inline uint16_t 5186 read_hw_cidx(struct sge_eq *eq) 5187 { 5188 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx]; 5189 uint16_t cidx = spg->cidx; /* stable snapshot */ 5190 5191 return (be16toh(cidx)); 5192 } 5193 5194 /* 5195 * Reclaim 'n' descriptors approximately. 5196 */ 5197 static u_int 5198 reclaim_tx_descs(struct sge_txq *txq, u_int n) 5199 { 5200 struct tx_sdesc *txsd; 5201 struct sge_eq *eq = &txq->eq; 5202 u_int can_reclaim, reclaimed; 5203 5204 TXQ_LOCK_ASSERT_OWNED(txq); 5205 MPASS(n > 0); 5206 5207 reclaimed = 0; 5208 can_reclaim = reclaimable_tx_desc(eq); 5209 while (can_reclaim && reclaimed < n) { 5210 int ndesc; 5211 struct mbuf *m, *nextpkt; 5212 5213 txsd = &txq->sdesc[eq->cidx]; 5214 ndesc = txsd->desc_used; 5215 5216 /* Firmware doesn't return "partial" credits. */ 5217 KASSERT(can_reclaim >= ndesc, 5218 ("%s: unexpected number of credits: %d, %d", 5219 __func__, can_reclaim, ndesc)); 5220 KASSERT(ndesc != 0, 5221 ("%s: descriptor with no credits: cidx %d", 5222 __func__, eq->cidx)); 5223 5224 for (m = txsd->m; m != NULL; m = nextpkt) { 5225 nextpkt = m->m_nextpkt; 5226 m->m_nextpkt = NULL; 5227 m_freem(m); 5228 } 5229 reclaimed += ndesc; 5230 can_reclaim -= ndesc; 5231 IDXINCR(eq->cidx, ndesc, eq->sidx); 5232 } 5233 5234 return (reclaimed); 5235 } 5236 5237 static void 5238 tx_reclaim(void *arg, int n) 5239 { 5240 struct sge_txq *txq = arg; 5241 struct sge_eq *eq = &txq->eq; 5242 5243 do { 5244 if (TXQ_TRYLOCK(txq) == 0) 5245 break; 5246 n = reclaim_tx_descs(txq, 32); 5247 if (eq->cidx == eq->pidx) 5248 eq->equeqidx = eq->pidx; 5249 TXQ_UNLOCK(txq); 5250 } while (n > 0); 5251 } 5252 5253 static __be64 5254 get_flit(struct sglist_seg *segs, int nsegs, int idx) 5255 { 5256 int i = (idx / 3) * 2; 5257 5258 switch (idx % 3) { 5259 case 0: { 5260 uint64_t rc; 5261 5262 rc = (uint64_t)segs[i].ss_len << 32; 5263 if (i + 1 < nsegs) 5264 rc |= (uint64_t)(segs[i + 1].ss_len); 5265 5266 return (htobe64(rc)); 5267 } 5268 case 1: 5269 return (htobe64(segs[i].ss_paddr)); 5270 case 2: 5271 return (htobe64(segs[i + 1].ss_paddr)); 5272 } 5273 5274 return (0); 5275 } 5276 5277 static void 5278 find_best_refill_source(struct adapter *sc, struct sge_fl *fl, int maxp) 5279 { 5280 int8_t zidx, hwidx, idx; 5281 uint16_t region1, region3; 5282 int spare, spare_needed, n; 5283 struct sw_zone_info *swz; 5284 struct hw_buf_info *hwb, *hwb_list = &sc->sge.hw_buf_info[0]; 5285 5286 /* 5287 * Buffer Packing: Look for PAGE_SIZE or larger zone which has a bufsize 5288 * large enough for the max payload and cluster metadata. Otherwise 5289 * settle for the largest bufsize that leaves enough room in the cluster 5290 * for metadata. 5291 * 5292 * Without buffer packing: Look for the smallest zone which has a 5293 * bufsize large enough for the max payload. Settle for the largest 5294 * bufsize available if there's nothing big enough for max payload. 5295 */ 5296 spare_needed = fl->flags & FL_BUF_PACKING ? CL_METADATA_SIZE : 0; 5297 swz = &sc->sge.sw_zone_info[0]; 5298 hwidx = -1; 5299 for (zidx = 0; zidx < SW_ZONE_SIZES; zidx++, swz++) { 5300 if (swz->size > largest_rx_cluster) { 5301 if (__predict_true(hwidx != -1)) 5302 break; 5303 5304 /* 5305 * This is a misconfiguration. largest_rx_cluster is 5306 * preventing us from finding a refill source. See 5307 * dev.t5nex.<n>.buffer_sizes to figure out why. 5308 */ 5309 device_printf(sc->dev, "largest_rx_cluster=%u leaves no" 5310 " refill source for fl %p (dma %u). Ignored.\n", 5311 largest_rx_cluster, fl, maxp); 5312 } 5313 for (idx = swz->head_hwidx; idx != -1; idx = hwb->next) { 5314 hwb = &hwb_list[idx]; 5315 spare = swz->size - hwb->size; 5316 if (spare < spare_needed) 5317 continue; 5318 5319 hwidx = idx; /* best option so far */ 5320 if (hwb->size >= maxp) { 5321 5322 if ((fl->flags & FL_BUF_PACKING) == 0) 5323 goto done; /* stop looking (not packing) */ 5324 5325 if (swz->size >= safest_rx_cluster) 5326 goto done; /* stop looking (packing) */ 5327 } 5328 break; /* keep looking, next zone */ 5329 } 5330 } 5331 done: 5332 /* A usable hwidx has been located. */ 5333 MPASS(hwidx != -1); 5334 hwb = &hwb_list[hwidx]; 5335 zidx = hwb->zidx; 5336 swz = &sc->sge.sw_zone_info[zidx]; 5337 region1 = 0; 5338 region3 = swz->size - hwb->size; 5339 5340 /* 5341 * Stay within this zone and see if there is a better match when mbuf 5342 * inlining is allowed. Remember that the hwidx's are sorted in 5343 * decreasing order of size (so in increasing order of spare area). 5344 */ 5345 for (idx = hwidx; idx != -1; idx = hwb->next) { 5346 hwb = &hwb_list[idx]; 5347 spare = swz->size - hwb->size; 5348 5349 if (allow_mbufs_in_cluster == 0 || hwb->size < maxp) 5350 break; 5351 5352 /* 5353 * Do not inline mbufs if doing so would violate the pad/pack 5354 * boundary alignment requirement. 5355 */ 5356 if (fl_pad && (MSIZE % sc->params.sge.pad_boundary) != 0) 5357 continue; 5358 if (fl->flags & FL_BUF_PACKING && 5359 (MSIZE % sc->params.sge.pack_boundary) != 0) 5360 continue; 5361 5362 if (spare < CL_METADATA_SIZE + MSIZE) 5363 continue; 5364 n = (spare - CL_METADATA_SIZE) / MSIZE; 5365 if (n > howmany(hwb->size, maxp)) 5366 break; 5367 5368 hwidx = idx; 5369 if (fl->flags & FL_BUF_PACKING) { 5370 region1 = n * MSIZE; 5371 region3 = spare - region1; 5372 } else { 5373 region1 = MSIZE; 5374 region3 = spare - region1; 5375 break; 5376 } 5377 } 5378 5379 KASSERT(zidx >= 0 && zidx < SW_ZONE_SIZES, 5380 ("%s: bad zone %d for fl %p, maxp %d", __func__, zidx, fl, maxp)); 5381 KASSERT(hwidx >= 0 && hwidx <= SGE_FLBUF_SIZES, 5382 ("%s: bad hwidx %d for fl %p, maxp %d", __func__, hwidx, fl, maxp)); 5383 KASSERT(region1 + sc->sge.hw_buf_info[hwidx].size + region3 == 5384 sc->sge.sw_zone_info[zidx].size, 5385 ("%s: bad buffer layout for fl %p, maxp %d. " 5386 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp, 5387 sc->sge.sw_zone_info[zidx].size, region1, 5388 sc->sge.hw_buf_info[hwidx].size, region3)); 5389 if (fl->flags & FL_BUF_PACKING || region1 > 0) { 5390 KASSERT(region3 >= CL_METADATA_SIZE, 5391 ("%s: no room for metadata. fl %p, maxp %d; " 5392 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp, 5393 sc->sge.sw_zone_info[zidx].size, region1, 5394 sc->sge.hw_buf_info[hwidx].size, region3)); 5395 KASSERT(region1 % MSIZE == 0, 5396 ("%s: bad mbuf region for fl %p, maxp %d. " 5397 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp, 5398 sc->sge.sw_zone_info[zidx].size, region1, 5399 sc->sge.hw_buf_info[hwidx].size, region3)); 5400 } 5401 5402 fl->cll_def.zidx = zidx; 5403 fl->cll_def.hwidx = hwidx; 5404 fl->cll_def.region1 = region1; 5405 fl->cll_def.region3 = region3; 5406 } 5407 5408 static void 5409 find_safe_refill_source(struct adapter *sc, struct sge_fl *fl) 5410 { 5411 struct sge *s = &sc->sge; 5412 struct hw_buf_info *hwb; 5413 struct sw_zone_info *swz; 5414 int spare; 5415 int8_t hwidx; 5416 5417 if (fl->flags & FL_BUF_PACKING) 5418 hwidx = s->safe_hwidx2; /* with room for metadata */ 5419 else if (allow_mbufs_in_cluster && s->safe_hwidx2 != -1) { 5420 hwidx = s->safe_hwidx2; 5421 hwb = &s->hw_buf_info[hwidx]; 5422 swz = &s->sw_zone_info[hwb->zidx]; 5423 spare = swz->size - hwb->size; 5424 5425 /* no good if there isn't room for an mbuf as well */ 5426 if (spare < CL_METADATA_SIZE + MSIZE) 5427 hwidx = s->safe_hwidx1; 5428 } else 5429 hwidx = s->safe_hwidx1; 5430 5431 if (hwidx == -1) { 5432 /* No fallback source */ 5433 fl->cll_alt.hwidx = -1; 5434 fl->cll_alt.zidx = -1; 5435 5436 return; 5437 } 5438 5439 hwb = &s->hw_buf_info[hwidx]; 5440 swz = &s->sw_zone_info[hwb->zidx]; 5441 spare = swz->size - hwb->size; 5442 fl->cll_alt.hwidx = hwidx; 5443 fl->cll_alt.zidx = hwb->zidx; 5444 if (allow_mbufs_in_cluster && 5445 (fl_pad == 0 || (MSIZE % sc->params.sge.pad_boundary) == 0)) 5446 fl->cll_alt.region1 = ((spare - CL_METADATA_SIZE) / MSIZE) * MSIZE; 5447 else 5448 fl->cll_alt.region1 = 0; 5449 fl->cll_alt.region3 = spare - fl->cll_alt.region1; 5450 } 5451 5452 static void 5453 add_fl_to_sfl(struct adapter *sc, struct sge_fl *fl) 5454 { 5455 mtx_lock(&sc->sfl_lock); 5456 FL_LOCK(fl); 5457 if ((fl->flags & FL_DOOMED) == 0) { 5458 fl->flags |= FL_STARVING; 5459 TAILQ_INSERT_TAIL(&sc->sfl, fl, link); 5460 callout_reset(&sc->sfl_callout, hz / 5, refill_sfl, sc); 5461 } 5462 FL_UNLOCK(fl); 5463 mtx_unlock(&sc->sfl_lock); 5464 } 5465 5466 static void 5467 handle_wrq_egr_update(struct adapter *sc, struct sge_eq *eq) 5468 { 5469 struct sge_wrq *wrq = (void *)eq; 5470 5471 atomic_readandclear_int(&eq->equiq); 5472 taskqueue_enqueue(sc->tq[eq->tx_chan], &wrq->wrq_tx_task); 5473 } 5474 5475 static void 5476 handle_eth_egr_update(struct adapter *sc, struct sge_eq *eq) 5477 { 5478 struct sge_txq *txq = (void *)eq; 5479 5480 MPASS((eq->flags & EQ_TYPEMASK) == EQ_ETH); 5481 5482 atomic_readandclear_int(&eq->equiq); 5483 mp_ring_check_drainage(txq->r, 0); 5484 taskqueue_enqueue(sc->tq[eq->tx_chan], &txq->tx_reclaim_task); 5485 } 5486 5487 static int 5488 handle_sge_egr_update(struct sge_iq *iq, const struct rss_header *rss, 5489 struct mbuf *m) 5490 { 5491 const struct cpl_sge_egr_update *cpl = (const void *)(rss + 1); 5492 unsigned int qid = G_EGR_QID(ntohl(cpl->opcode_qid)); 5493 struct adapter *sc = iq->adapter; 5494 struct sge *s = &sc->sge; 5495 struct sge_eq *eq; 5496 static void (*h[])(struct adapter *, struct sge_eq *) = {NULL, 5497 &handle_wrq_egr_update, &handle_eth_egr_update, 5498 &handle_wrq_egr_update}; 5499 5500 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 5501 rss->opcode)); 5502 5503 eq = s->eqmap[qid - s->eq_start - s->eq_base]; 5504 (*h[eq->flags & EQ_TYPEMASK])(sc, eq); 5505 5506 return (0); 5507 } 5508 5509 /* handle_fw_msg works for both fw4_msg and fw6_msg because this is valid */ 5510 CTASSERT(offsetof(struct cpl_fw4_msg, data) == \ 5511 offsetof(struct cpl_fw6_msg, data)); 5512 5513 static int 5514 handle_fw_msg(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 5515 { 5516 struct adapter *sc = iq->adapter; 5517 const struct cpl_fw6_msg *cpl = (const void *)(rss + 1); 5518 5519 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 5520 rss->opcode)); 5521 5522 if (cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL) { 5523 const struct rss_header *rss2; 5524 5525 rss2 = (const struct rss_header *)&cpl->data[0]; 5526 return (t4_cpl_handler[rss2->opcode](iq, rss2, m)); 5527 } 5528 5529 return (t4_fw_msg_handler[cpl->type](sc, &cpl->data[0])); 5530 } 5531 5532 /** 5533 * t4_handle_wrerr_rpl - process a FW work request error message 5534 * @adap: the adapter 5535 * @rpl: start of the FW message 5536 */ 5537 static int 5538 t4_handle_wrerr_rpl(struct adapter *adap, const __be64 *rpl) 5539 { 5540 u8 opcode = *(const u8 *)rpl; 5541 const struct fw_error_cmd *e = (const void *)rpl; 5542 unsigned int i; 5543 5544 if (opcode != FW_ERROR_CMD) { 5545 log(LOG_ERR, 5546 "%s: Received WRERR_RPL message with opcode %#x\n", 5547 device_get_nameunit(adap->dev), opcode); 5548 return (EINVAL); 5549 } 5550 log(LOG_ERR, "%s: FW_ERROR (%s) ", device_get_nameunit(adap->dev), 5551 G_FW_ERROR_CMD_FATAL(be32toh(e->op_to_type)) ? "fatal" : 5552 "non-fatal"); 5553 switch (G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type))) { 5554 case FW_ERROR_TYPE_EXCEPTION: 5555 log(LOG_ERR, "exception info:\n"); 5556 for (i = 0; i < nitems(e->u.exception.info); i++) 5557 log(LOG_ERR, "%s%08x", i == 0 ? "\t" : " ", 5558 be32toh(e->u.exception.info[i])); 5559 log(LOG_ERR, "\n"); 5560 break; 5561 case FW_ERROR_TYPE_HWMODULE: 5562 log(LOG_ERR, "HW module regaddr %08x regval %08x\n", 5563 be32toh(e->u.hwmodule.regaddr), 5564 be32toh(e->u.hwmodule.regval)); 5565 break; 5566 case FW_ERROR_TYPE_WR: 5567 log(LOG_ERR, "WR cidx %d PF %d VF %d eqid %d hdr:\n", 5568 be16toh(e->u.wr.cidx), 5569 G_FW_ERROR_CMD_PFN(be16toh(e->u.wr.pfn_vfn)), 5570 G_FW_ERROR_CMD_VFN(be16toh(e->u.wr.pfn_vfn)), 5571 be32toh(e->u.wr.eqid)); 5572 for (i = 0; i < nitems(e->u.wr.wrhdr); i++) 5573 log(LOG_ERR, "%s%02x", i == 0 ? "\t" : " ", 5574 e->u.wr.wrhdr[i]); 5575 log(LOG_ERR, "\n"); 5576 break; 5577 case FW_ERROR_TYPE_ACL: 5578 log(LOG_ERR, "ACL cidx %d PF %d VF %d eqid %d %s", 5579 be16toh(e->u.acl.cidx), 5580 G_FW_ERROR_CMD_PFN(be16toh(e->u.acl.pfn_vfn)), 5581 G_FW_ERROR_CMD_VFN(be16toh(e->u.acl.pfn_vfn)), 5582 be32toh(e->u.acl.eqid), 5583 G_FW_ERROR_CMD_MV(be16toh(e->u.acl.mv_pkd)) ? "vlanid" : 5584 "MAC"); 5585 for (i = 0; i < nitems(e->u.acl.val); i++) 5586 log(LOG_ERR, " %02x", e->u.acl.val[i]); 5587 log(LOG_ERR, "\n"); 5588 break; 5589 default: 5590 log(LOG_ERR, "type %#x\n", 5591 G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type))); 5592 return (EINVAL); 5593 } 5594 return (0); 5595 } 5596 5597 static int 5598 sysctl_uint16(SYSCTL_HANDLER_ARGS) 5599 { 5600 uint16_t *id = arg1; 5601 int i = *id; 5602 5603 return sysctl_handle_int(oidp, &i, 0, req); 5604 } 5605 5606 static int 5607 sysctl_bufsizes(SYSCTL_HANDLER_ARGS) 5608 { 5609 struct sge *s = arg1; 5610 struct hw_buf_info *hwb = &s->hw_buf_info[0]; 5611 struct sw_zone_info *swz = &s->sw_zone_info[0]; 5612 int i, rc; 5613 struct sbuf sb; 5614 char c; 5615 5616 sbuf_new(&sb, NULL, 32, SBUF_AUTOEXTEND); 5617 for (i = 0; i < SGE_FLBUF_SIZES; i++, hwb++) { 5618 if (hwb->zidx >= 0 && swz[hwb->zidx].size <= largest_rx_cluster) 5619 c = '*'; 5620 else 5621 c = '\0'; 5622 5623 sbuf_printf(&sb, "%u%c ", hwb->size, c); 5624 } 5625 sbuf_trim(&sb); 5626 sbuf_finish(&sb); 5627 rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req); 5628 sbuf_delete(&sb); 5629 return (rc); 5630 } 5631 5632 #ifdef RATELIMIT 5633 /* 5634 * len16 for a txpkt WR with a GL. Includes the firmware work request header. 5635 */ 5636 static inline u_int 5637 txpkt_eo_len16(u_int nsegs, u_int immhdrs, u_int tso) 5638 { 5639 u_int n; 5640 5641 MPASS(immhdrs > 0); 5642 5643 n = roundup2(sizeof(struct fw_eth_tx_eo_wr) + 5644 sizeof(struct cpl_tx_pkt_core) + immhdrs, 16); 5645 if (__predict_false(nsegs == 0)) 5646 goto done; 5647 5648 nsegs--; /* first segment is part of ulptx_sgl */ 5649 n += sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 5650 if (tso) 5651 n += sizeof(struct cpl_tx_pkt_lso_core); 5652 5653 done: 5654 return (howmany(n, 16)); 5655 } 5656 5657 #define ETID_FLOWC_NPARAMS 6 5658 #define ETID_FLOWC_LEN (roundup2((sizeof(struct fw_flowc_wr) + \ 5659 ETID_FLOWC_NPARAMS * sizeof(struct fw_flowc_mnemval)), 16)) 5660 #define ETID_FLOWC_LEN16 (howmany(ETID_FLOWC_LEN, 16)) 5661 5662 static int 5663 send_etid_flowc_wr(struct cxgbe_snd_tag *cst, struct port_info *pi, 5664 struct vi_info *vi) 5665 { 5666 struct wrq_cookie cookie; 5667 u_int pfvf = pi->adapter->pf << S_FW_VIID_PFN; 5668 struct fw_flowc_wr *flowc; 5669 5670 mtx_assert(&cst->lock, MA_OWNED); 5671 MPASS((cst->flags & (EO_FLOWC_PENDING | EO_FLOWC_RPL_PENDING)) == 5672 EO_FLOWC_PENDING); 5673 5674 flowc = start_wrq_wr(cst->eo_txq, ETID_FLOWC_LEN16, &cookie); 5675 if (__predict_false(flowc == NULL)) 5676 return (ENOMEM); 5677 5678 bzero(flowc, ETID_FLOWC_LEN); 5679 flowc->op_to_nparams = htobe32(V_FW_WR_OP(FW_FLOWC_WR) | 5680 V_FW_FLOWC_WR_NPARAMS(ETID_FLOWC_NPARAMS) | V_FW_WR_COMPL(0)); 5681 flowc->flowid_len16 = htonl(V_FW_WR_LEN16(ETID_FLOWC_LEN16) | 5682 V_FW_WR_FLOWID(cst->etid)); 5683 flowc->mnemval[0].mnemonic = FW_FLOWC_MNEM_PFNVFN; 5684 flowc->mnemval[0].val = htobe32(pfvf); 5685 flowc->mnemval[1].mnemonic = FW_FLOWC_MNEM_CH; 5686 flowc->mnemval[1].val = htobe32(pi->tx_chan); 5687 flowc->mnemval[2].mnemonic = FW_FLOWC_MNEM_PORT; 5688 flowc->mnemval[2].val = htobe32(pi->tx_chan); 5689 flowc->mnemval[3].mnemonic = FW_FLOWC_MNEM_IQID; 5690 flowc->mnemval[3].val = htobe32(cst->iqid); 5691 flowc->mnemval[4].mnemonic = FW_FLOWC_MNEM_EOSTATE; 5692 flowc->mnemval[4].val = htobe32(FW_FLOWC_MNEM_EOSTATE_ESTABLISHED); 5693 flowc->mnemval[5].mnemonic = FW_FLOWC_MNEM_SCHEDCLASS; 5694 flowc->mnemval[5].val = htobe32(cst->schedcl); 5695 5696 commit_wrq_wr(cst->eo_txq, flowc, &cookie); 5697 5698 cst->flags &= ~EO_FLOWC_PENDING; 5699 cst->flags |= EO_FLOWC_RPL_PENDING; 5700 MPASS(cst->tx_credits >= ETID_FLOWC_LEN16); /* flowc is first WR. */ 5701 cst->tx_credits -= ETID_FLOWC_LEN16; 5702 5703 return (0); 5704 } 5705 5706 #define ETID_FLUSH_LEN16 (howmany(sizeof (struct fw_flowc_wr), 16)) 5707 5708 void 5709 send_etid_flush_wr(struct cxgbe_snd_tag *cst) 5710 { 5711 struct fw_flowc_wr *flowc; 5712 struct wrq_cookie cookie; 5713 5714 mtx_assert(&cst->lock, MA_OWNED); 5715 5716 flowc = start_wrq_wr(cst->eo_txq, ETID_FLUSH_LEN16, &cookie); 5717 if (__predict_false(flowc == NULL)) 5718 CXGBE_UNIMPLEMENTED(__func__); 5719 5720 bzero(flowc, ETID_FLUSH_LEN16 * 16); 5721 flowc->op_to_nparams = htobe32(V_FW_WR_OP(FW_FLOWC_WR) | 5722 V_FW_FLOWC_WR_NPARAMS(0) | F_FW_WR_COMPL); 5723 flowc->flowid_len16 = htobe32(V_FW_WR_LEN16(ETID_FLUSH_LEN16) | 5724 V_FW_WR_FLOWID(cst->etid)); 5725 5726 commit_wrq_wr(cst->eo_txq, flowc, &cookie); 5727 5728 cst->flags |= EO_FLUSH_RPL_PENDING; 5729 MPASS(cst->tx_credits >= ETID_FLUSH_LEN16); 5730 cst->tx_credits -= ETID_FLUSH_LEN16; 5731 cst->ncompl++; 5732 } 5733 5734 static void 5735 write_ethofld_wr(struct cxgbe_snd_tag *cst, struct fw_eth_tx_eo_wr *wr, 5736 struct mbuf *m0, int compl) 5737 { 5738 struct cpl_tx_pkt_core *cpl; 5739 uint64_t ctrl1; 5740 uint32_t ctrl; /* used in many unrelated places */ 5741 int len16, pktlen, nsegs, immhdrs; 5742 caddr_t dst; 5743 uintptr_t p; 5744 struct ulptx_sgl *usgl; 5745 struct sglist sg; 5746 struct sglist_seg segs[38]; /* XXX: find real limit. XXX: get off the stack */ 5747 5748 mtx_assert(&cst->lock, MA_OWNED); 5749 M_ASSERTPKTHDR(m0); 5750 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 5751 m0->m_pkthdr.l4hlen > 0, 5752 ("%s: ethofld mbuf %p is missing header lengths", __func__, m0)); 5753 5754 len16 = mbuf_eo_len16(m0); 5755 nsegs = mbuf_eo_nsegs(m0); 5756 pktlen = m0->m_pkthdr.len; 5757 ctrl = sizeof(struct cpl_tx_pkt_core); 5758 if (needs_tso(m0)) 5759 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 5760 immhdrs = m0->m_pkthdr.l2hlen + m0->m_pkthdr.l3hlen + m0->m_pkthdr.l4hlen; 5761 ctrl += immhdrs; 5762 5763 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_EO_WR) | 5764 V_FW_ETH_TX_EO_WR_IMMDLEN(ctrl) | V_FW_WR_COMPL(!!compl)); 5765 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(len16) | 5766 V_FW_WR_FLOWID(cst->etid)); 5767 wr->r3 = 0; 5768 if (needs_udp_csum(m0)) { 5769 wr->u.udpseg.type = FW_ETH_TX_EO_TYPE_UDPSEG; 5770 wr->u.udpseg.ethlen = m0->m_pkthdr.l2hlen; 5771 wr->u.udpseg.iplen = htobe16(m0->m_pkthdr.l3hlen); 5772 wr->u.udpseg.udplen = m0->m_pkthdr.l4hlen; 5773 wr->u.udpseg.rtplen = 0; 5774 wr->u.udpseg.r4 = 0; 5775 wr->u.udpseg.mss = htobe16(pktlen - immhdrs); 5776 wr->u.udpseg.schedpktsize = wr->u.udpseg.mss; 5777 wr->u.udpseg.plen = htobe32(pktlen - immhdrs); 5778 cpl = (void *)(wr + 1); 5779 } else { 5780 MPASS(needs_tcp_csum(m0)); 5781 wr->u.tcpseg.type = FW_ETH_TX_EO_TYPE_TCPSEG; 5782 wr->u.tcpseg.ethlen = m0->m_pkthdr.l2hlen; 5783 wr->u.tcpseg.iplen = htobe16(m0->m_pkthdr.l3hlen); 5784 wr->u.tcpseg.tcplen = m0->m_pkthdr.l4hlen; 5785 wr->u.tcpseg.tsclk_tsoff = mbuf_eo_tsclk_tsoff(m0); 5786 wr->u.tcpseg.r4 = 0; 5787 wr->u.tcpseg.r5 = 0; 5788 wr->u.tcpseg.plen = htobe32(pktlen - immhdrs); 5789 5790 if (needs_tso(m0)) { 5791 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1); 5792 5793 wr->u.tcpseg.mss = htobe16(m0->m_pkthdr.tso_segsz); 5794 5795 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | 5796 F_LSO_FIRST_SLICE | F_LSO_LAST_SLICE | 5797 V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) | 5798 V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2); 5799 if (m0->m_pkthdr.l2hlen == sizeof(struct ether_vlan_header)) 5800 ctrl |= V_LSO_ETHHDR_LEN(1); 5801 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 5802 ctrl |= F_LSO_IPV6; 5803 lso->lso_ctrl = htobe32(ctrl); 5804 lso->ipid_ofst = htobe16(0); 5805 lso->mss = htobe16(m0->m_pkthdr.tso_segsz); 5806 lso->seqno_offset = htobe32(0); 5807 lso->len = htobe32(pktlen); 5808 5809 cpl = (void *)(lso + 1); 5810 } else { 5811 wr->u.tcpseg.mss = htobe16(0xffff); 5812 cpl = (void *)(wr + 1); 5813 } 5814 } 5815 5816 /* Checksum offload must be requested for ethofld. */ 5817 ctrl1 = 0; 5818 MPASS(needs_l4_csum(m0)); 5819 5820 /* VLAN tag insertion */ 5821 if (needs_vlan_insertion(m0)) { 5822 ctrl1 |= F_TXPKT_VLAN_VLD | 5823 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 5824 } 5825 5826 /* CPL header */ 5827 cpl->ctrl0 = cst->ctrl0; 5828 cpl->pack = 0; 5829 cpl->len = htobe16(pktlen); 5830 cpl->ctrl1 = htobe64(ctrl1); 5831 5832 /* Copy Ethernet, IP & TCP/UDP hdrs as immediate data */ 5833 p = (uintptr_t)(cpl + 1); 5834 m_copydata(m0, 0, immhdrs, (void *)p); 5835 5836 /* SGL */ 5837 dst = (void *)(cpl + 1); 5838 if (nsegs > 0) { 5839 int i, pad; 5840 5841 /* zero-pad upto next 16Byte boundary, if not 16Byte aligned */ 5842 p += immhdrs; 5843 pad = 16 - (immhdrs & 0xf); 5844 bzero((void *)p, pad); 5845 5846 usgl = (void *)(p + pad); 5847 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 5848 V_ULPTX_NSGE(nsegs)); 5849 5850 sglist_init(&sg, nitems(segs), segs); 5851 for (; m0 != NULL; m0 = m0->m_next) { 5852 if (__predict_false(m0->m_len == 0)) 5853 continue; 5854 if (immhdrs >= m0->m_len) { 5855 immhdrs -= m0->m_len; 5856 continue; 5857 } 5858 5859 sglist_append(&sg, mtod(m0, char *) + immhdrs, 5860 m0->m_len - immhdrs); 5861 immhdrs = 0; 5862 } 5863 MPASS(sg.sg_nseg == nsegs); 5864 5865 /* 5866 * Zero pad last 8B in case the WR doesn't end on a 16B 5867 * boundary. 5868 */ 5869 *(uint64_t *)((char *)wr + len16 * 16 - 8) = 0; 5870 5871 usgl->len0 = htobe32(segs[0].ss_len); 5872 usgl->addr0 = htobe64(segs[0].ss_paddr); 5873 for (i = 0; i < nsegs - 1; i++) { 5874 usgl->sge[i / 2].len[i & 1] = htobe32(segs[i + 1].ss_len); 5875 usgl->sge[i / 2].addr[i & 1] = htobe64(segs[i + 1].ss_paddr); 5876 } 5877 if (i & 1) 5878 usgl->sge[i / 2].len[1] = htobe32(0); 5879 } 5880 5881 } 5882 5883 static void 5884 ethofld_tx(struct cxgbe_snd_tag *cst) 5885 { 5886 struct mbuf *m; 5887 struct wrq_cookie cookie; 5888 int next_credits, compl; 5889 struct fw_eth_tx_eo_wr *wr; 5890 5891 mtx_assert(&cst->lock, MA_OWNED); 5892 5893 while ((m = mbufq_first(&cst->pending_tx)) != NULL) { 5894 M_ASSERTPKTHDR(m); 5895 5896 /* How many len16 credits do we need to send this mbuf. */ 5897 next_credits = mbuf_eo_len16(m); 5898 MPASS(next_credits > 0); 5899 if (next_credits > cst->tx_credits) { 5900 /* 5901 * Tx will make progress eventually because there is at 5902 * least one outstanding fw4_ack that will return 5903 * credits and kick the tx. 5904 */ 5905 MPASS(cst->ncompl > 0); 5906 return; 5907 } 5908 wr = start_wrq_wr(cst->eo_txq, next_credits, &cookie); 5909 if (__predict_false(wr == NULL)) { 5910 /* XXX: wishful thinking, not a real assertion. */ 5911 MPASS(cst->ncompl > 0); 5912 return; 5913 } 5914 cst->tx_credits -= next_credits; 5915 cst->tx_nocompl += next_credits; 5916 compl = cst->ncompl == 0 || cst->tx_nocompl >= cst->tx_total / 2; 5917 ETHER_BPF_MTAP(cst->com.ifp, m); 5918 write_ethofld_wr(cst, wr, m, compl); 5919 commit_wrq_wr(cst->eo_txq, wr, &cookie); 5920 if (compl) { 5921 cst->ncompl++; 5922 cst->tx_nocompl = 0; 5923 } 5924 (void) mbufq_dequeue(&cst->pending_tx); 5925 mbufq_enqueue(&cst->pending_fwack, m); 5926 } 5927 } 5928 5929 int 5930 ethofld_transmit(struct ifnet *ifp, struct mbuf *m0) 5931 { 5932 struct cxgbe_snd_tag *cst; 5933 int rc; 5934 5935 MPASS(m0->m_nextpkt == NULL); 5936 MPASS(m0->m_pkthdr.snd_tag != NULL); 5937 cst = mst_to_cst(m0->m_pkthdr.snd_tag); 5938 5939 mtx_lock(&cst->lock); 5940 MPASS(cst->flags & EO_SND_TAG_REF); 5941 5942 if (__predict_false(cst->flags & EO_FLOWC_PENDING)) { 5943 struct vi_info *vi = ifp->if_softc; 5944 struct port_info *pi = vi->pi; 5945 struct adapter *sc = pi->adapter; 5946 const uint32_t rss_mask = vi->rss_size - 1; 5947 uint32_t rss_hash; 5948 5949 cst->eo_txq = &sc->sge.ofld_txq[vi->first_ofld_txq]; 5950 if (M_HASHTYPE_ISHASH(m0)) 5951 rss_hash = m0->m_pkthdr.flowid; 5952 else 5953 rss_hash = arc4random(); 5954 /* We assume RSS hashing */ 5955 cst->iqid = vi->rss[rss_hash & rss_mask]; 5956 cst->eo_txq += rss_hash % vi->nofldtxq; 5957 rc = send_etid_flowc_wr(cst, pi, vi); 5958 if (rc != 0) 5959 goto done; 5960 } 5961 5962 if (__predict_false(cst->plen + m0->m_pkthdr.len > eo_max_backlog)) { 5963 rc = ENOBUFS; 5964 goto done; 5965 } 5966 5967 mbufq_enqueue(&cst->pending_tx, m0); 5968 cst->plen += m0->m_pkthdr.len; 5969 5970 ethofld_tx(cst); 5971 rc = 0; 5972 done: 5973 mtx_unlock(&cst->lock); 5974 if (__predict_false(rc != 0)) 5975 m_freem(m0); 5976 return (rc); 5977 } 5978 5979 static int 5980 ethofld_fw4_ack(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0) 5981 { 5982 struct adapter *sc = iq->adapter; 5983 const struct cpl_fw4_ack *cpl = (const void *)(rss + 1); 5984 struct mbuf *m; 5985 u_int etid = G_CPL_FW4_ACK_FLOWID(be32toh(OPCODE_TID(cpl))); 5986 struct cxgbe_snd_tag *cst; 5987 uint8_t credits = cpl->credits; 5988 5989 cst = lookup_etid(sc, etid); 5990 mtx_lock(&cst->lock); 5991 if (__predict_false(cst->flags & EO_FLOWC_RPL_PENDING)) { 5992 MPASS(credits >= ETID_FLOWC_LEN16); 5993 credits -= ETID_FLOWC_LEN16; 5994 cst->flags &= ~EO_FLOWC_RPL_PENDING; 5995 } 5996 5997 KASSERT(cst->ncompl > 0, 5998 ("%s: etid %u (%p) wasn't expecting completion.", 5999 __func__, etid, cst)); 6000 cst->ncompl--; 6001 6002 while (credits > 0) { 6003 m = mbufq_dequeue(&cst->pending_fwack); 6004 if (__predict_false(m == NULL)) { 6005 /* 6006 * The remaining credits are for the final flush that 6007 * was issued when the tag was freed by the kernel. 6008 */ 6009 MPASS((cst->flags & 6010 (EO_FLUSH_RPL_PENDING | EO_SND_TAG_REF)) == 6011 EO_FLUSH_RPL_PENDING); 6012 MPASS(credits == ETID_FLUSH_LEN16); 6013 MPASS(cst->tx_credits + cpl->credits == cst->tx_total); 6014 MPASS(cst->ncompl == 0); 6015 6016 cst->flags &= ~EO_FLUSH_RPL_PENDING; 6017 cst->tx_credits += cpl->credits; 6018 freetag: 6019 cxgbe_snd_tag_free_locked(cst); 6020 return (0); /* cst is gone. */ 6021 } 6022 KASSERT(m != NULL, 6023 ("%s: too many credits (%u, %u)", __func__, cpl->credits, 6024 credits)); 6025 KASSERT(credits >= mbuf_eo_len16(m), 6026 ("%s: too few credits (%u, %u, %u)", __func__, 6027 cpl->credits, credits, mbuf_eo_len16(m))); 6028 credits -= mbuf_eo_len16(m); 6029 cst->plen -= m->m_pkthdr.len; 6030 m_freem(m); 6031 } 6032 6033 cst->tx_credits += cpl->credits; 6034 MPASS(cst->tx_credits <= cst->tx_total); 6035 6036 m = mbufq_first(&cst->pending_tx); 6037 if (m != NULL && cst->tx_credits >= mbuf_eo_len16(m)) 6038 ethofld_tx(cst); 6039 6040 if (__predict_false((cst->flags & EO_SND_TAG_REF) == 0) && 6041 cst->ncompl == 0) { 6042 if (cst->tx_credits == cst->tx_total) 6043 goto freetag; 6044 else { 6045 MPASS((cst->flags & EO_FLUSH_RPL_PENDING) == 0); 6046 send_etid_flush_wr(cst); 6047 } 6048 } 6049 6050 mtx_unlock(&cst->lock); 6051 6052 return (0); 6053 } 6054 #endif 6055