1 /*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 34 #include <sys/types.h> 35 #include <sys/eventhandler.h> 36 #include <sys/mbuf.h> 37 #include <sys/socket.h> 38 #include <sys/kernel.h> 39 #include <sys/kdb.h> 40 #include <sys/malloc.h> 41 #include <sys/queue.h> 42 #include <sys/sbuf.h> 43 #include <sys/taskqueue.h> 44 #include <sys/time.h> 45 #include <sys/sysctl.h> 46 #include <sys/smp.h> 47 #include <net/bpf.h> 48 #include <net/ethernet.h> 49 #include <net/if.h> 50 #include <net/if_vlan_var.h> 51 #include <netinet/in.h> 52 #include <netinet/ip.h> 53 #include <netinet/ip6.h> 54 #include <netinet/tcp.h> 55 #include <machine/md_var.h> 56 #include <vm/vm.h> 57 #include <vm/pmap.h> 58 #ifdef DEV_NETMAP 59 #include <machine/bus.h> 60 #include <sys/selinfo.h> 61 #include <net/if_var.h> 62 #include <net/netmap.h> 63 #include <dev/netmap/netmap_kern.h> 64 #endif 65 66 #include "common/common.h" 67 #include "common/t4_regs.h" 68 #include "common/t4_regs_values.h" 69 #include "common/t4_msg.h" 70 71 #ifdef T4_PKT_TIMESTAMP 72 #define RX_COPY_THRESHOLD (MINCLSIZE - 8) 73 #else 74 #define RX_COPY_THRESHOLD MINCLSIZE 75 #endif 76 77 /* 78 * Ethernet frames are DMA'd at this byte offset into the freelist buffer. 79 * 0-7 are valid values. 80 */ 81 int fl_pktshift = 2; 82 TUNABLE_INT("hw.cxgbe.fl_pktshift", &fl_pktshift); 83 84 /* 85 * Pad ethernet payload up to this boundary. 86 * -1: driver should figure out a good value. 87 * 0: disable padding. 88 * Any power of 2 from 32 to 4096 (both inclusive) is also a valid value. 89 */ 90 int fl_pad = -1; 91 TUNABLE_INT("hw.cxgbe.fl_pad", &fl_pad); 92 93 /* 94 * Status page length. 95 * -1: driver should figure out a good value. 96 * 64 or 128 are the only other valid values. 97 */ 98 int spg_len = -1; 99 TUNABLE_INT("hw.cxgbe.spg_len", &spg_len); 100 101 /* 102 * Congestion drops. 103 * -1: no congestion feedback (not recommended). 104 * 0: backpressure the channel instead of dropping packets right away. 105 * 1: no backpressure, drop packets for the congested queue immediately. 106 */ 107 static int cong_drop = 0; 108 TUNABLE_INT("hw.cxgbe.cong_drop", &cong_drop); 109 110 /* 111 * Deliver multiple frames in the same free list buffer if they fit. 112 * -1: let the driver decide whether to enable buffer packing or not. 113 * 0: disable buffer packing. 114 * 1: enable buffer packing. 115 */ 116 static int buffer_packing = -1; 117 TUNABLE_INT("hw.cxgbe.buffer_packing", &buffer_packing); 118 119 /* 120 * Start next frame in a packed buffer at this boundary. 121 * -1: driver should figure out a good value. 122 * T4: 123 * --- 124 * if fl_pad != 0 125 * value specified here will be overridden by fl_pad. 126 * else 127 * power of 2 from 32 to 4096 (both inclusive) is a valid value here. 128 * T5: 129 * --- 130 * 16, or a power of 2 from 64 to 4096 (both inclusive) is a valid value. 131 */ 132 static int fl_pack = -1; 133 static int t4_fl_pack; 134 static int t5_fl_pack; 135 TUNABLE_INT("hw.cxgbe.fl_pack", &fl_pack); 136 137 /* 138 * Allow the driver to create mbuf(s) in a cluster allocated for rx. 139 * 0: never; always allocate mbufs from the zone_mbuf UMA zone. 140 * 1: ok to create mbuf(s) within a cluster if there is room. 141 */ 142 static int allow_mbufs_in_cluster = 1; 143 TUNABLE_INT("hw.cxgbe.allow_mbufs_in_cluster", &allow_mbufs_in_cluster); 144 145 /* 146 * Largest rx cluster size that the driver is allowed to allocate. 147 */ 148 static int largest_rx_cluster = MJUM16BYTES; 149 TUNABLE_INT("hw.cxgbe.largest_rx_cluster", &largest_rx_cluster); 150 151 /* 152 * Size of cluster allocation that's most likely to succeed. The driver will 153 * fall back to this size if it fails to allocate clusters larger than this. 154 */ 155 static int safest_rx_cluster = PAGE_SIZE; 156 TUNABLE_INT("hw.cxgbe.safest_rx_cluster", &safest_rx_cluster); 157 158 /* Used to track coalesced tx work request */ 159 struct txpkts { 160 uint64_t *flitp; /* ptr to flit where next pkt should start */ 161 uint8_t npkt; /* # of packets in this work request */ 162 uint8_t nflits; /* # of flits used by this work request */ 163 uint16_t plen; /* total payload (sum of all packets) */ 164 }; 165 166 /* A packet's SGL. This + m_pkthdr has all info needed for tx */ 167 struct sgl { 168 int nsegs; /* # of segments in the SGL, 0 means imm. tx */ 169 int nflits; /* # of flits needed for the SGL */ 170 bus_dma_segment_t seg[TX_SGL_SEGS]; 171 }; 172 173 static int service_iq(struct sge_iq *, int); 174 static struct mbuf *get_fl_payload(struct adapter *, struct sge_fl *, uint32_t, 175 int *); 176 static int t4_eth_rx(struct sge_iq *, const struct rss_header *, struct mbuf *); 177 static inline void init_iq(struct sge_iq *, struct adapter *, int, int, int, 178 int); 179 static inline void init_fl(struct adapter *, struct sge_fl *, int, int, int, 180 char *); 181 static inline void init_eq(struct sge_eq *, int, int, uint8_t, uint16_t, 182 char *); 183 static int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *, 184 bus_addr_t *, void **); 185 static int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 186 void *); 187 static int alloc_iq_fl(struct port_info *, struct sge_iq *, struct sge_fl *, 188 int, int); 189 static int free_iq_fl(struct port_info *, struct sge_iq *, struct sge_fl *); 190 static void add_fl_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *, 191 struct sge_fl *); 192 static int alloc_fwq(struct adapter *); 193 static int free_fwq(struct adapter *); 194 static int alloc_mgmtq(struct adapter *); 195 static int free_mgmtq(struct adapter *); 196 static int alloc_rxq(struct port_info *, struct sge_rxq *, int, int, 197 struct sysctl_oid *); 198 static int free_rxq(struct port_info *, struct sge_rxq *); 199 #ifdef TCP_OFFLOAD 200 static int alloc_ofld_rxq(struct port_info *, struct sge_ofld_rxq *, int, int, 201 struct sysctl_oid *); 202 static int free_ofld_rxq(struct port_info *, struct sge_ofld_rxq *); 203 #endif 204 #ifdef DEV_NETMAP 205 static int alloc_nm_rxq(struct port_info *, struct sge_nm_rxq *, int, int, 206 struct sysctl_oid *); 207 static int free_nm_rxq(struct port_info *, struct sge_nm_rxq *); 208 static int alloc_nm_txq(struct port_info *, struct sge_nm_txq *, int, int, 209 struct sysctl_oid *); 210 static int free_nm_txq(struct port_info *, struct sge_nm_txq *); 211 #endif 212 static int ctrl_eq_alloc(struct adapter *, struct sge_eq *); 213 static int eth_eq_alloc(struct adapter *, struct port_info *, struct sge_eq *); 214 #ifdef TCP_OFFLOAD 215 static int ofld_eq_alloc(struct adapter *, struct port_info *, struct sge_eq *); 216 #endif 217 static int alloc_eq(struct adapter *, struct port_info *, struct sge_eq *); 218 static int free_eq(struct adapter *, struct sge_eq *); 219 static int alloc_wrq(struct adapter *, struct port_info *, struct sge_wrq *, 220 struct sysctl_oid *); 221 static int free_wrq(struct adapter *, struct sge_wrq *); 222 static int alloc_txq(struct port_info *, struct sge_txq *, int, 223 struct sysctl_oid *); 224 static int free_txq(struct port_info *, struct sge_txq *); 225 static void oneseg_dma_callback(void *, bus_dma_segment_t *, int, int); 226 static inline bool is_new_response(const struct sge_iq *, struct rsp_ctrl **); 227 static inline void iq_next(struct sge_iq *); 228 static inline void ring_fl_db(struct adapter *, struct sge_fl *); 229 static int refill_fl(struct adapter *, struct sge_fl *, int); 230 static void refill_sfl(void *); 231 static int alloc_fl_sdesc(struct sge_fl *); 232 static void free_fl_sdesc(struct adapter *, struct sge_fl *); 233 static void find_best_refill_source(struct adapter *, struct sge_fl *, int); 234 static void find_safe_refill_source(struct adapter *, struct sge_fl *); 235 static void add_fl_to_sfl(struct adapter *, struct sge_fl *); 236 237 static int get_pkt_sgl(struct sge_txq *, struct mbuf **, struct sgl *, int); 238 static int free_pkt_sgl(struct sge_txq *, struct sgl *); 239 static int write_txpkt_wr(struct port_info *, struct sge_txq *, struct mbuf *, 240 struct sgl *); 241 static int add_to_txpkts(struct port_info *, struct sge_txq *, struct txpkts *, 242 struct mbuf *, struct sgl *); 243 static void write_txpkts_wr(struct sge_txq *, struct txpkts *); 244 static inline void write_ulp_cpl_sgl(struct port_info *, struct sge_txq *, 245 struct txpkts *, struct mbuf *, struct sgl *); 246 static int write_sgl_to_txd(struct sge_eq *, struct sgl *, caddr_t *); 247 static inline void copy_to_txd(struct sge_eq *, caddr_t, caddr_t *, int); 248 static inline void ring_eq_db(struct adapter *, struct sge_eq *); 249 static inline int reclaimable(struct sge_eq *); 250 static int reclaim_tx_descs(struct sge_txq *, int, int); 251 static void write_eqflush_wr(struct sge_eq *); 252 static __be64 get_flit(bus_dma_segment_t *, int, int); 253 static int handle_sge_egr_update(struct sge_iq *, const struct rss_header *, 254 struct mbuf *); 255 static int handle_fw_msg(struct sge_iq *, const struct rss_header *, 256 struct mbuf *); 257 258 static int sysctl_uint16(SYSCTL_HANDLER_ARGS); 259 static int sysctl_bufsizes(SYSCTL_HANDLER_ARGS); 260 261 /* 262 * Called on MOD_LOAD. Validates and calculates the SGE tunables. 263 */ 264 void 265 t4_sge_modload(void) 266 { 267 int pad; 268 269 /* set pad to a reasonable powerof2 between 16 and 4096 (inclusive) */ 270 #if defined(__i386__) || defined(__amd64__) 271 pad = max(cpu_clflush_line_size, 16); 272 #else 273 pad = max(CACHE_LINE_SIZE, 16); 274 #endif 275 pad = min(pad, 4096); 276 277 if (fl_pktshift < 0 || fl_pktshift > 7) { 278 printf("Invalid hw.cxgbe.fl_pktshift value (%d)," 279 " using 2 instead.\n", fl_pktshift); 280 fl_pktshift = 2; 281 } 282 283 if (fl_pad != 0 && 284 (fl_pad < 32 || fl_pad > 4096 || !powerof2(fl_pad))) { 285 286 if (fl_pad != -1) { 287 printf("Invalid hw.cxgbe.fl_pad value (%d)," 288 " using %d instead.\n", fl_pad, max(pad, 32)); 289 } 290 fl_pad = max(pad, 32); 291 } 292 293 /* 294 * T4 has the same pad and pack boundary. If a pad boundary is set, 295 * pack boundary must be set to the same value. Otherwise take the 296 * specified value or auto-calculate something reasonable. 297 */ 298 if (fl_pad) 299 t4_fl_pack = fl_pad; 300 else if (fl_pack < 32 || fl_pack > 4096 || !powerof2(fl_pack)) 301 t4_fl_pack = max(pad, 32); 302 else 303 t4_fl_pack = fl_pack; 304 305 /* T5's pack boundary is independent of the pad boundary. */ 306 if (fl_pack < 16 || fl_pack == 32 || fl_pack > 4096 || 307 !powerof2(fl_pack)) 308 t5_fl_pack = max(pad, CACHE_LINE_SIZE); 309 else 310 t5_fl_pack = fl_pack; 311 312 if (spg_len != 64 && spg_len != 128) { 313 int len; 314 315 #if defined(__i386__) || defined(__amd64__) 316 len = cpu_clflush_line_size > 64 ? 128 : 64; 317 #else 318 len = 64; 319 #endif 320 if (spg_len != -1) { 321 printf("Invalid hw.cxgbe.spg_len value (%d)," 322 " using %d instead.\n", spg_len, len); 323 } 324 spg_len = len; 325 } 326 327 if (cong_drop < -1 || cong_drop > 1) { 328 printf("Invalid hw.cxgbe.cong_drop value (%d)," 329 " using 0 instead.\n", cong_drop); 330 cong_drop = 0; 331 } 332 } 333 334 void 335 t4_init_sge_cpl_handlers(struct adapter *sc) 336 { 337 338 t4_register_cpl_handler(sc, CPL_FW4_MSG, handle_fw_msg); 339 t4_register_cpl_handler(sc, CPL_FW6_MSG, handle_fw_msg); 340 t4_register_cpl_handler(sc, CPL_SGE_EGR_UPDATE, handle_sge_egr_update); 341 t4_register_cpl_handler(sc, CPL_RX_PKT, t4_eth_rx); 342 t4_register_fw_msg_handler(sc, FW6_TYPE_CMD_RPL, t4_handle_fw_rpl); 343 } 344 345 /* 346 * adap->params.vpd.cclk must be set up before this is called. 347 */ 348 void 349 t4_tweak_chip_settings(struct adapter *sc) 350 { 351 int i; 352 uint32_t v, m; 353 int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200}; 354 int timer_max = M_TIMERVALUE0 * 1000 / sc->params.vpd.cclk; 355 int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */ 356 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 357 static int sge_flbuf_sizes[] = { 358 MCLBYTES, 359 #if MJUMPAGESIZE != MCLBYTES 360 MJUMPAGESIZE, 361 MJUMPAGESIZE - CL_METADATA_SIZE, 362 MJUMPAGESIZE - 2 * MSIZE - CL_METADATA_SIZE, 363 #endif 364 MJUM9BYTES, 365 MJUM16BYTES, 366 MCLBYTES - MSIZE - CL_METADATA_SIZE, 367 MJUM9BYTES - CL_METADATA_SIZE, 368 MJUM16BYTES - CL_METADATA_SIZE, 369 }; 370 371 KASSERT(sc->flags & MASTER_PF, 372 ("%s: trying to change chip settings when not master.", __func__)); 373 374 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE; 375 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE | 376 V_EGRSTATUSPAGESIZE(spg_len == 128); 377 if (is_t4(sc) && (fl_pad || buffer_packing)) { 378 /* t4_fl_pack has the correct value even when fl_pad = 0 */ 379 m |= V_INGPADBOUNDARY(M_INGPADBOUNDARY); 380 v |= V_INGPADBOUNDARY(ilog2(t4_fl_pack) - 5); 381 } else if (is_t5(sc) && fl_pad) { 382 m |= V_INGPADBOUNDARY(M_INGPADBOUNDARY); 383 v |= V_INGPADBOUNDARY(ilog2(fl_pad) - 5); 384 } 385 t4_set_reg_field(sc, A_SGE_CONTROL, m, v); 386 387 if (is_t5(sc) && buffer_packing) { 388 m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY); 389 if (t5_fl_pack == 16) 390 v = V_INGPACKBOUNDARY(0); 391 else 392 v = V_INGPACKBOUNDARY(ilog2(t5_fl_pack) - 5); 393 t4_set_reg_field(sc, A_SGE_CONTROL2, m, v); 394 } 395 396 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) | 397 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) | 398 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) | 399 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) | 400 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) | 401 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) | 402 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) | 403 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10); 404 t4_write_reg(sc, A_SGE_HOST_PAGE_SIZE, v); 405 406 KASSERT(nitems(sge_flbuf_sizes) <= SGE_FLBUF_SIZES, 407 ("%s: hw buffer size table too big", __func__)); 408 for (i = 0; i < min(nitems(sge_flbuf_sizes), SGE_FLBUF_SIZES); i++) { 409 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0 + (4 * i), 410 sge_flbuf_sizes[i]); 411 } 412 413 v = V_THRESHOLD_0(intr_pktcount[0]) | V_THRESHOLD_1(intr_pktcount[1]) | 414 V_THRESHOLD_2(intr_pktcount[2]) | V_THRESHOLD_3(intr_pktcount[3]); 415 t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD, v); 416 417 KASSERT(intr_timer[0] <= timer_max, 418 ("%s: not a single usable timer (%d, %d)", __func__, intr_timer[0], 419 timer_max)); 420 for (i = 1; i < nitems(intr_timer); i++) { 421 KASSERT(intr_timer[i] >= intr_timer[i - 1], 422 ("%s: timers not listed in increasing order (%d)", 423 __func__, i)); 424 425 while (intr_timer[i] > timer_max) { 426 if (i == nitems(intr_timer) - 1) { 427 intr_timer[i] = timer_max; 428 break; 429 } 430 intr_timer[i] += intr_timer[i - 1]; 431 intr_timer[i] /= 2; 432 } 433 } 434 435 v = V_TIMERVALUE0(us_to_core_ticks(sc, intr_timer[0])) | 436 V_TIMERVALUE1(us_to_core_ticks(sc, intr_timer[1])); 437 t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1, v); 438 v = V_TIMERVALUE2(us_to_core_ticks(sc, intr_timer[2])) | 439 V_TIMERVALUE3(us_to_core_ticks(sc, intr_timer[3])); 440 t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3, v); 441 v = V_TIMERVALUE4(us_to_core_ticks(sc, intr_timer[4])) | 442 V_TIMERVALUE5(us_to_core_ticks(sc, intr_timer[5])); 443 t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5, v); 444 445 if (cong_drop == 0) { 446 m = F_TUNNELCNGDROP0 | F_TUNNELCNGDROP1 | F_TUNNELCNGDROP2 | 447 F_TUNNELCNGDROP3; 448 t4_set_reg_field(sc, A_TP_PARA_REG3, m, 0); 449 } 450 451 /* 4K, 16K, 64K, 256K DDP "page sizes" */ 452 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 453 t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, v); 454 455 m = v = F_TDDPTAGTCB; 456 t4_set_reg_field(sc, A_ULP_RX_CTL, m, v); 457 458 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 459 F_RESETDDPOFFSET; 460 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 461 t4_set_reg_field(sc, A_TP_PARA_REG5, m, v); 462 } 463 464 /* 465 * SGE wants the buffer to be at least 64B and then a multiple of the pad 466 * boundary or 16, whichever is greater. 467 */ 468 static inline int 469 hwsz_ok(int hwsz) 470 { 471 int mask = max(fl_pad, 16) - 1; 472 473 return (hwsz >= 64 && (hwsz & mask) == 0); 474 } 475 476 /* 477 * XXX: driver really should be able to deal with unexpected settings. 478 */ 479 int 480 t4_read_chip_settings(struct adapter *sc) 481 { 482 struct sge *s = &sc->sge; 483 int i, j, n, rc = 0; 484 uint32_t m, v, r; 485 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 486 static int sw_buf_sizes[] = { /* Sorted by size */ 487 MCLBYTES, 488 #if MJUMPAGESIZE != MCLBYTES 489 MJUMPAGESIZE, 490 #endif 491 MJUM9BYTES, 492 MJUM16BYTES 493 }; 494 struct sw_zone_info *swz, *safe_swz; 495 struct hw_buf_info *hwb; 496 497 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE; 498 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE | 499 V_EGRSTATUSPAGESIZE(spg_len == 128); 500 if (is_t4(sc) && (fl_pad || buffer_packing)) { 501 m |= V_INGPADBOUNDARY(M_INGPADBOUNDARY); 502 v |= V_INGPADBOUNDARY(ilog2(t4_fl_pack) - 5); 503 } else if (is_t5(sc) && fl_pad) { 504 m |= V_INGPADBOUNDARY(M_INGPADBOUNDARY); 505 v |= V_INGPADBOUNDARY(ilog2(fl_pad) - 5); 506 } 507 r = t4_read_reg(sc, A_SGE_CONTROL); 508 if ((r & m) != v) { 509 device_printf(sc->dev, "invalid SGE_CONTROL(0x%x)\n", r); 510 rc = EINVAL; 511 } 512 513 if (is_t5(sc) && buffer_packing) { 514 m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY); 515 if (t5_fl_pack == 16) 516 v = V_INGPACKBOUNDARY(0); 517 else 518 v = V_INGPACKBOUNDARY(ilog2(t5_fl_pack) - 5); 519 r = t4_read_reg(sc, A_SGE_CONTROL2); 520 if ((r & m) != v) { 521 device_printf(sc->dev, 522 "invalid SGE_CONTROL2(0x%x)\n", r); 523 rc = EINVAL; 524 } 525 } 526 s->pack_boundary = is_t4(sc) ? t4_fl_pack : t5_fl_pack; 527 528 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) | 529 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) | 530 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) | 531 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) | 532 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) | 533 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) | 534 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) | 535 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10); 536 r = t4_read_reg(sc, A_SGE_HOST_PAGE_SIZE); 537 if (r != v) { 538 device_printf(sc->dev, "invalid SGE_HOST_PAGE_SIZE(0x%x)\n", r); 539 rc = EINVAL; 540 } 541 542 /* Filter out unusable hw buffer sizes entirely (mark with -2). */ 543 hwb = &s->hw_buf_info[0]; 544 for (i = 0; i < nitems(s->hw_buf_info); i++, hwb++) { 545 r = t4_read_reg(sc, A_SGE_FL_BUFFER_SIZE0 + (4 * i)); 546 hwb->size = r; 547 hwb->zidx = hwsz_ok(r) ? -1 : -2; 548 hwb->next = -1; 549 } 550 551 /* 552 * Create a sorted list in decreasing order of hw buffer sizes (and so 553 * increasing order of spare area) for each software zone. 554 */ 555 n = 0; /* no usable buffer size to begin with */ 556 swz = &s->sw_zone_info[0]; 557 safe_swz = NULL; 558 for (i = 0; i < SW_ZONE_SIZES; i++, swz++) { 559 int8_t head = -1, tail = -1; 560 561 swz->size = sw_buf_sizes[i]; 562 swz->zone = m_getzone(swz->size); 563 swz->type = m_gettype(swz->size); 564 565 if (swz->size == safest_rx_cluster) 566 safe_swz = swz; 567 568 hwb = &s->hw_buf_info[0]; 569 for (j = 0; j < SGE_FLBUF_SIZES; j++, hwb++) { 570 if (hwb->zidx != -1 || hwb->size > swz->size) 571 continue; 572 hwb->zidx = i; 573 if (head == -1) 574 head = tail = j; 575 else if (hwb->size < s->hw_buf_info[tail].size) { 576 s->hw_buf_info[tail].next = j; 577 tail = j; 578 } else { 579 int8_t *cur; 580 struct hw_buf_info *t; 581 582 for (cur = &head; *cur != -1; cur = &t->next) { 583 t = &s->hw_buf_info[*cur]; 584 if (hwb->size == t->size) { 585 hwb->zidx = -2; 586 break; 587 } 588 if (hwb->size > t->size) { 589 hwb->next = *cur; 590 *cur = j; 591 break; 592 } 593 } 594 } 595 } 596 swz->head_hwidx = head; 597 swz->tail_hwidx = tail; 598 599 if (tail != -1) { 600 n++; 601 if (swz->size - s->hw_buf_info[tail].size >= 602 CL_METADATA_SIZE) 603 sc->flags |= BUF_PACKING_OK; 604 } 605 } 606 if (n == 0) { 607 device_printf(sc->dev, "no usable SGE FL buffer size.\n"); 608 rc = EINVAL; 609 } 610 611 s->safe_hwidx1 = -1; 612 s->safe_hwidx2 = -1; 613 if (safe_swz != NULL) { 614 s->safe_hwidx1 = safe_swz->head_hwidx; 615 for (i = safe_swz->head_hwidx; i != -1; i = hwb->next) { 616 int spare; 617 618 hwb = &s->hw_buf_info[i]; 619 spare = safe_swz->size - hwb->size; 620 if (spare < CL_METADATA_SIZE) 621 continue; 622 if (s->safe_hwidx2 == -1 || 623 spare == CL_METADATA_SIZE + MSIZE) 624 s->safe_hwidx2 = i; 625 if (spare >= CL_METADATA_SIZE + MSIZE) 626 break; 627 } 628 } 629 630 r = t4_read_reg(sc, A_SGE_INGRESS_RX_THRESHOLD); 631 s->counter_val[0] = G_THRESHOLD_0(r); 632 s->counter_val[1] = G_THRESHOLD_1(r); 633 s->counter_val[2] = G_THRESHOLD_2(r); 634 s->counter_val[3] = G_THRESHOLD_3(r); 635 636 r = t4_read_reg(sc, A_SGE_TIMER_VALUE_0_AND_1); 637 s->timer_val[0] = G_TIMERVALUE0(r) / core_ticks_per_usec(sc); 638 s->timer_val[1] = G_TIMERVALUE1(r) / core_ticks_per_usec(sc); 639 r = t4_read_reg(sc, A_SGE_TIMER_VALUE_2_AND_3); 640 s->timer_val[2] = G_TIMERVALUE2(r) / core_ticks_per_usec(sc); 641 s->timer_val[3] = G_TIMERVALUE3(r) / core_ticks_per_usec(sc); 642 r = t4_read_reg(sc, A_SGE_TIMER_VALUE_4_AND_5); 643 s->timer_val[4] = G_TIMERVALUE4(r) / core_ticks_per_usec(sc); 644 s->timer_val[5] = G_TIMERVALUE5(r) / core_ticks_per_usec(sc); 645 646 if (cong_drop == 0) { 647 m = F_TUNNELCNGDROP0 | F_TUNNELCNGDROP1 | F_TUNNELCNGDROP2 | 648 F_TUNNELCNGDROP3; 649 r = t4_read_reg(sc, A_TP_PARA_REG3); 650 if (r & m) { 651 device_printf(sc->dev, 652 "invalid TP_PARA_REG3(0x%x)\n", r); 653 rc = EINVAL; 654 } 655 } 656 657 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 658 r = t4_read_reg(sc, A_ULP_RX_TDDP_PSZ); 659 if (r != v) { 660 device_printf(sc->dev, "invalid ULP_RX_TDDP_PSZ(0x%x)\n", r); 661 rc = EINVAL; 662 } 663 664 m = v = F_TDDPTAGTCB; 665 r = t4_read_reg(sc, A_ULP_RX_CTL); 666 if ((r & m) != v) { 667 device_printf(sc->dev, "invalid ULP_RX_CTL(0x%x)\n", r); 668 rc = EINVAL; 669 } 670 671 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 672 F_RESETDDPOFFSET; 673 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 674 r = t4_read_reg(sc, A_TP_PARA_REG5); 675 if ((r & m) != v) { 676 device_printf(sc->dev, "invalid TP_PARA_REG5(0x%x)\n", r); 677 rc = EINVAL; 678 } 679 680 r = t4_read_reg(sc, A_SGE_CONM_CTRL); 681 s->fl_starve_threshold = G_EGRTHRESHOLD(r) * 2 + 1; 682 if (is_t4(sc)) 683 s->fl_starve_threshold2 = s->fl_starve_threshold; 684 else 685 s->fl_starve_threshold2 = G_EGRTHRESHOLDPACKING(r) * 2 + 1; 686 687 /* egress queues: log2 of # of doorbells per BAR2 page */ 688 r = t4_read_reg(sc, A_SGE_EGRESS_QUEUES_PER_PAGE_PF); 689 r >>= S_QUEUESPERPAGEPF0 + 690 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * sc->pf; 691 s->eq_s_qpp = r & M_QUEUESPERPAGEPF0; 692 693 /* ingress queues: log2 of # of doorbells per BAR2 page */ 694 r = t4_read_reg(sc, A_SGE_INGRESS_QUEUES_PER_PAGE_PF); 695 r >>= S_QUEUESPERPAGEPF0 + 696 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * sc->pf; 697 s->iq_s_qpp = r & M_QUEUESPERPAGEPF0; 698 699 t4_init_tp_params(sc); 700 701 t4_read_mtu_tbl(sc, sc->params.mtus, NULL); 702 t4_load_mtus(sc, sc->params.mtus, sc->params.a_wnd, sc->params.b_wnd); 703 704 return (rc); 705 } 706 707 int 708 t4_create_dma_tag(struct adapter *sc) 709 { 710 int rc; 711 712 rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0, 713 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE, 714 BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL, 715 NULL, &sc->dmat); 716 if (rc != 0) { 717 device_printf(sc->dev, 718 "failed to create main DMA tag: %d\n", rc); 719 } 720 721 return (rc); 722 } 723 724 static inline int 725 enable_buffer_packing(struct adapter *sc) 726 { 727 728 if (sc->flags & BUF_PACKING_OK && 729 ((is_t5(sc) && buffer_packing) || /* 1 or -1 both ok for T5 */ 730 (is_t4(sc) && buffer_packing == 1))) 731 return (1); 732 return (0); 733 } 734 735 void 736 t4_sge_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx, 737 struct sysctl_oid_list *children) 738 { 739 740 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "buffer_sizes", 741 CTLTYPE_STRING | CTLFLAG_RD, &sc->sge, 0, sysctl_bufsizes, "A", 742 "freelist buffer sizes"); 743 744 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pktshift", CTLFLAG_RD, 745 NULL, fl_pktshift, "payload DMA offset in rx buffer (bytes)"); 746 747 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pad", CTLFLAG_RD, 748 NULL, fl_pad, "payload pad boundary (bytes)"); 749 750 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "spg_len", CTLFLAG_RD, 751 NULL, spg_len, "status page size (bytes)"); 752 753 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_drop", CTLFLAG_RD, 754 NULL, cong_drop, "congestion drop setting"); 755 756 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "buffer_packing", CTLFLAG_RD, 757 NULL, enable_buffer_packing(sc), 758 "pack multiple frames in one fl buffer"); 759 760 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pack", CTLFLAG_RD, 761 NULL, sc->sge.pack_boundary, "payload pack boundary (bytes)"); 762 } 763 764 int 765 t4_destroy_dma_tag(struct adapter *sc) 766 { 767 if (sc->dmat) 768 bus_dma_tag_destroy(sc->dmat); 769 770 return (0); 771 } 772 773 /* 774 * Allocate and initialize the firmware event queue and the management queue. 775 * 776 * Returns errno on failure. Resources allocated up to that point may still be 777 * allocated. Caller is responsible for cleanup in case this function fails. 778 */ 779 int 780 t4_setup_adapter_queues(struct adapter *sc) 781 { 782 int rc; 783 784 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 785 786 sysctl_ctx_init(&sc->ctx); 787 sc->flags |= ADAP_SYSCTL_CTX; 788 789 /* 790 * Firmware event queue 791 */ 792 rc = alloc_fwq(sc); 793 if (rc != 0) 794 return (rc); 795 796 /* 797 * Management queue. This is just a control queue that uses the fwq as 798 * its associated iq. 799 */ 800 rc = alloc_mgmtq(sc); 801 802 return (rc); 803 } 804 805 /* 806 * Idempotent 807 */ 808 int 809 t4_teardown_adapter_queues(struct adapter *sc) 810 { 811 812 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 813 814 /* Do this before freeing the queue */ 815 if (sc->flags & ADAP_SYSCTL_CTX) { 816 sysctl_ctx_free(&sc->ctx); 817 sc->flags &= ~ADAP_SYSCTL_CTX; 818 } 819 820 free_mgmtq(sc); 821 free_fwq(sc); 822 823 return (0); 824 } 825 826 static inline int 827 port_intr_count(struct port_info *pi) 828 { 829 int rc = 0; 830 831 if (pi->flags & INTR_RXQ) 832 rc += pi->nrxq; 833 #ifdef TCP_OFFLOAD 834 if (pi->flags & INTR_OFLD_RXQ) 835 rc += pi->nofldrxq; 836 #endif 837 #ifdef DEV_NETMAP 838 if (pi->flags & INTR_NM_RXQ) 839 rc += pi->nnmrxq; 840 #endif 841 return (rc); 842 } 843 844 static inline int 845 first_vector(struct port_info *pi) 846 { 847 struct adapter *sc = pi->adapter; 848 int rc = T4_EXTRA_INTR, i; 849 850 if (sc->intr_count == 1) 851 return (0); 852 853 for_each_port(sc, i) { 854 if (i == pi->port_id) 855 break; 856 857 rc += port_intr_count(sc->port[i]); 858 } 859 860 return (rc); 861 } 862 863 /* 864 * Given an arbitrary "index," come up with an iq that can be used by other 865 * queues (of this port) for interrupt forwarding, SGE egress updates, etc. 866 * The iq returned is guaranteed to be something that takes direct interrupts. 867 */ 868 static struct sge_iq * 869 port_intr_iq(struct port_info *pi, int idx) 870 { 871 struct adapter *sc = pi->adapter; 872 struct sge *s = &sc->sge; 873 struct sge_iq *iq = NULL; 874 int nintr, i; 875 876 if (sc->intr_count == 1) 877 return (&sc->sge.fwq); 878 879 nintr = port_intr_count(pi); 880 KASSERT(nintr != 0, 881 ("%s: pi %p has no exclusive interrupts, total interrupts = %d", 882 __func__, pi, sc->intr_count)); 883 #ifdef DEV_NETMAP 884 /* Exclude netmap queues as they can't take anyone else's interrupts */ 885 if (pi->flags & INTR_NM_RXQ) 886 nintr -= pi->nnmrxq; 887 KASSERT(nintr > 0, 888 ("%s: pi %p has nintr %d after netmap adjustment of %d", __func__, 889 pi, nintr, pi->nnmrxq)); 890 #endif 891 i = idx % nintr; 892 893 if (pi->flags & INTR_RXQ) { 894 if (i < pi->nrxq) { 895 iq = &s->rxq[pi->first_rxq + i].iq; 896 goto done; 897 } 898 i -= pi->nrxq; 899 } 900 #ifdef TCP_OFFLOAD 901 if (pi->flags & INTR_OFLD_RXQ) { 902 if (i < pi->nofldrxq) { 903 iq = &s->ofld_rxq[pi->first_ofld_rxq + i].iq; 904 goto done; 905 } 906 i -= pi->nofldrxq; 907 } 908 #endif 909 panic("%s: pi %p, intr_flags 0x%lx, idx %d, total intr %d\n", __func__, 910 pi, pi->flags & INTR_ALL, idx, nintr); 911 done: 912 MPASS(iq != NULL); 913 KASSERT(iq->flags & IQ_INTR, 914 ("%s: iq %p (port %p, intr_flags 0x%lx, idx %d)", __func__, iq, pi, 915 pi->flags & INTR_ALL, idx)); 916 return (iq); 917 } 918 919 /* Maximum payload that can be delivered with a single iq descriptor */ 920 static inline int 921 mtu_to_max_payload(struct adapter *sc, int mtu, const int toe) 922 { 923 int payload; 924 925 #ifdef TCP_OFFLOAD 926 if (toe) { 927 payload = sc->tt.rx_coalesce ? 928 G_RXCOALESCESIZE(t4_read_reg(sc, A_TP_PARA_REG2)) : mtu; 929 } else { 930 #endif 931 /* large enough even when hw VLAN extraction is disabled */ 932 payload = fl_pktshift + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 933 mtu; 934 #ifdef TCP_OFFLOAD 935 } 936 #endif 937 payload = roundup2(payload, fl_pad); 938 939 return (payload); 940 } 941 942 int 943 t4_setup_port_queues(struct port_info *pi) 944 { 945 int rc = 0, i, j, intr_idx, iqid; 946 struct sge_rxq *rxq; 947 struct sge_txq *txq; 948 struct sge_wrq *ctrlq; 949 #ifdef TCP_OFFLOAD 950 struct sge_ofld_rxq *ofld_rxq; 951 struct sge_wrq *ofld_txq; 952 #endif 953 #ifdef DEV_NETMAP 954 struct sge_nm_rxq *nm_rxq; 955 struct sge_nm_txq *nm_txq; 956 #endif 957 char name[16]; 958 struct adapter *sc = pi->adapter; 959 struct ifnet *ifp = pi->ifp; 960 struct sysctl_oid *oid = device_get_sysctl_tree(pi->dev); 961 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 962 int maxp, pack, mtu = ifp->if_mtu; 963 964 /* Interrupt vector to start from (when using multiple vectors) */ 965 intr_idx = first_vector(pi); 966 967 /* 968 * First pass over all NIC and TOE rx queues: 969 * a) initialize iq and fl 970 * b) allocate queue iff it will take direct interrupts. 971 */ 972 maxp = mtu_to_max_payload(sc, mtu, 0); 973 pack = enable_buffer_packing(sc); 974 if (pi->flags & INTR_RXQ) { 975 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "rxq", 976 CTLFLAG_RD, NULL, "rx queues"); 977 } 978 for_each_rxq(pi, i, rxq) { 979 980 init_iq(&rxq->iq, sc, pi->tmr_idx, pi->pktc_idx, pi->qsize_rxq, 981 RX_IQ_ESIZE); 982 983 snprintf(name, sizeof(name), "%s rxq%d-fl", 984 device_get_nameunit(pi->dev), i); 985 init_fl(sc, &rxq->fl, pi->qsize_rxq / 8, maxp, pack, name); 986 987 if (pi->flags & INTR_RXQ) { 988 rxq->iq.flags |= IQ_INTR; 989 rc = alloc_rxq(pi, rxq, intr_idx, i, oid); 990 if (rc != 0) 991 goto done; 992 intr_idx++; 993 } 994 } 995 #ifdef TCP_OFFLOAD 996 maxp = mtu_to_max_payload(sc, mtu, 1); 997 if (is_offload(sc) && pi->flags & INTR_OFLD_RXQ) { 998 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "ofld_rxq", 999 CTLFLAG_RD, NULL, 1000 "rx queues for offloaded TCP connections"); 1001 } 1002 for_each_ofld_rxq(pi, i, ofld_rxq) { 1003 1004 init_iq(&ofld_rxq->iq, sc, pi->tmr_idx, pi->pktc_idx, 1005 pi->qsize_rxq, RX_IQ_ESIZE); 1006 1007 snprintf(name, sizeof(name), "%s ofld_rxq%d-fl", 1008 device_get_nameunit(pi->dev), i); 1009 init_fl(sc, &ofld_rxq->fl, pi->qsize_rxq / 8, maxp, pack, name); 1010 1011 if (pi->flags & INTR_OFLD_RXQ) { 1012 ofld_rxq->iq.flags |= IQ_INTR; 1013 rc = alloc_ofld_rxq(pi, ofld_rxq, intr_idx, i, oid); 1014 if (rc != 0) 1015 goto done; 1016 intr_idx++; 1017 } 1018 } 1019 #endif 1020 #ifdef DEV_NETMAP 1021 /* 1022 * We don't have buffers to back the netmap rx queues right now so we 1023 * create the queues in a way that doesn't set off any congestion signal 1024 * in the chip. 1025 */ 1026 if (pi->flags & INTR_NM_RXQ) { 1027 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "nm_rxq", 1028 CTLFLAG_RD, NULL, "rx queues for netmap"); 1029 for_each_nm_rxq(pi, i, nm_rxq) { 1030 rc = alloc_nm_rxq(pi, nm_rxq, intr_idx, i, oid); 1031 if (rc != 0) 1032 goto done; 1033 intr_idx++; 1034 } 1035 } 1036 #endif 1037 1038 /* 1039 * Second pass over all NIC and TOE rx queues. The queues forwarding 1040 * their interrupts are allocated now. 1041 */ 1042 j = 0; 1043 if (!(pi->flags & INTR_RXQ)) { 1044 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "rxq", 1045 CTLFLAG_RD, NULL, "rx queues"); 1046 for_each_rxq(pi, i, rxq) { 1047 MPASS(!(rxq->iq.flags & IQ_INTR)); 1048 1049 intr_idx = port_intr_iq(pi, j)->abs_id; 1050 1051 rc = alloc_rxq(pi, rxq, intr_idx, i, oid); 1052 if (rc != 0) 1053 goto done; 1054 j++; 1055 } 1056 } 1057 #ifdef TCP_OFFLOAD 1058 if (is_offload(sc) && !(pi->flags & INTR_OFLD_RXQ)) { 1059 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "ofld_rxq", 1060 CTLFLAG_RD, NULL, 1061 "rx queues for offloaded TCP connections"); 1062 for_each_ofld_rxq(pi, i, ofld_rxq) { 1063 MPASS(!(ofld_rxq->iq.flags & IQ_INTR)); 1064 1065 intr_idx = port_intr_iq(pi, j)->abs_id; 1066 1067 rc = alloc_ofld_rxq(pi, ofld_rxq, intr_idx, i, oid); 1068 if (rc != 0) 1069 goto done; 1070 j++; 1071 } 1072 } 1073 #endif 1074 #ifdef DEV_NETMAP 1075 if (!(pi->flags & INTR_NM_RXQ)) 1076 CXGBE_UNIMPLEMENTED(__func__); 1077 #endif 1078 1079 /* 1080 * Now the tx queues. Only one pass needed. 1081 */ 1082 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "txq", CTLFLAG_RD, 1083 NULL, "tx queues"); 1084 j = 0; 1085 for_each_txq(pi, i, txq) { 1086 iqid = port_intr_iq(pi, j)->cntxt_id; 1087 snprintf(name, sizeof(name), "%s txq%d", 1088 device_get_nameunit(pi->dev), i); 1089 init_eq(&txq->eq, EQ_ETH, pi->qsize_txq, pi->tx_chan, iqid, 1090 name); 1091 1092 rc = alloc_txq(pi, txq, i, oid); 1093 if (rc != 0) 1094 goto done; 1095 j++; 1096 } 1097 #ifdef TCP_OFFLOAD 1098 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "ofld_txq", 1099 CTLFLAG_RD, NULL, "tx queues for offloaded TCP connections"); 1100 for_each_ofld_txq(pi, i, ofld_txq) { 1101 struct sysctl_oid *oid2; 1102 1103 iqid = port_intr_iq(pi, j)->cntxt_id; 1104 snprintf(name, sizeof(name), "%s ofld_txq%d", 1105 device_get_nameunit(pi->dev), i); 1106 init_eq(&ofld_txq->eq, EQ_OFLD, pi->qsize_txq, pi->tx_chan, 1107 iqid, name); 1108 1109 snprintf(name, sizeof(name), "%d", i); 1110 oid2 = SYSCTL_ADD_NODE(&pi->ctx, SYSCTL_CHILDREN(oid), OID_AUTO, 1111 name, CTLFLAG_RD, NULL, "offload tx queue"); 1112 1113 rc = alloc_wrq(sc, pi, ofld_txq, oid2); 1114 if (rc != 0) 1115 goto done; 1116 j++; 1117 } 1118 #endif 1119 #ifdef DEV_NETMAP 1120 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "nm_txq", 1121 CTLFLAG_RD, NULL, "tx queues for netmap use"); 1122 for_each_nm_txq(pi, i, nm_txq) { 1123 iqid = pi->first_nm_rxq + (j % pi->nnmrxq); 1124 rc = alloc_nm_txq(pi, nm_txq, iqid, i, oid); 1125 if (rc != 0) 1126 goto done; 1127 j++; 1128 } 1129 #endif 1130 1131 /* 1132 * Finally, the control queue. 1133 */ 1134 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "ctrlq", CTLFLAG_RD, 1135 NULL, "ctrl queue"); 1136 ctrlq = &sc->sge.ctrlq[pi->port_id]; 1137 iqid = port_intr_iq(pi, 0)->cntxt_id; 1138 snprintf(name, sizeof(name), "%s ctrlq", device_get_nameunit(pi->dev)); 1139 init_eq(&ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE, pi->tx_chan, iqid, name); 1140 rc = alloc_wrq(sc, pi, ctrlq, oid); 1141 1142 done: 1143 if (rc) 1144 t4_teardown_port_queues(pi); 1145 1146 return (rc); 1147 } 1148 1149 /* 1150 * Idempotent 1151 */ 1152 int 1153 t4_teardown_port_queues(struct port_info *pi) 1154 { 1155 int i; 1156 struct adapter *sc = pi->adapter; 1157 struct sge_rxq *rxq; 1158 struct sge_txq *txq; 1159 #ifdef TCP_OFFLOAD 1160 struct sge_ofld_rxq *ofld_rxq; 1161 struct sge_wrq *ofld_txq; 1162 #endif 1163 #ifdef DEV_NETMAP 1164 struct sge_nm_rxq *nm_rxq; 1165 struct sge_nm_txq *nm_txq; 1166 #endif 1167 1168 /* Do this before freeing the queues */ 1169 if (pi->flags & PORT_SYSCTL_CTX) { 1170 sysctl_ctx_free(&pi->ctx); 1171 pi->flags &= ~PORT_SYSCTL_CTX; 1172 } 1173 1174 /* 1175 * Take down all the tx queues first, as they reference the rx queues 1176 * (for egress updates, etc.). 1177 */ 1178 1179 free_wrq(sc, &sc->sge.ctrlq[pi->port_id]); 1180 1181 for_each_txq(pi, i, txq) { 1182 free_txq(pi, txq); 1183 } 1184 #ifdef TCP_OFFLOAD 1185 for_each_ofld_txq(pi, i, ofld_txq) { 1186 free_wrq(sc, ofld_txq); 1187 } 1188 #endif 1189 #ifdef DEV_NETMAP 1190 for_each_nm_txq(pi, i, nm_txq) 1191 free_nm_txq(pi, nm_txq); 1192 #endif 1193 1194 /* 1195 * Then take down the rx queues that forward their interrupts, as they 1196 * reference other rx queues. 1197 */ 1198 1199 for_each_rxq(pi, i, rxq) { 1200 if ((rxq->iq.flags & IQ_INTR) == 0) 1201 free_rxq(pi, rxq); 1202 } 1203 #ifdef TCP_OFFLOAD 1204 for_each_ofld_rxq(pi, i, ofld_rxq) { 1205 if ((ofld_rxq->iq.flags & IQ_INTR) == 0) 1206 free_ofld_rxq(pi, ofld_rxq); 1207 } 1208 #endif 1209 #ifdef DEV_NETMAP 1210 for_each_nm_rxq(pi, i, nm_rxq) 1211 free_nm_rxq(pi, nm_rxq); 1212 #endif 1213 1214 /* 1215 * Then take down the rx queues that take direct interrupts. 1216 */ 1217 1218 for_each_rxq(pi, i, rxq) { 1219 if (rxq->iq.flags & IQ_INTR) 1220 free_rxq(pi, rxq); 1221 } 1222 #ifdef TCP_OFFLOAD 1223 for_each_ofld_rxq(pi, i, ofld_rxq) { 1224 if (ofld_rxq->iq.flags & IQ_INTR) 1225 free_ofld_rxq(pi, ofld_rxq); 1226 } 1227 #endif 1228 #ifdef DEV_NETMAP 1229 CXGBE_UNIMPLEMENTED(__func__); 1230 #endif 1231 1232 return (0); 1233 } 1234 1235 /* 1236 * Deals with errors and the firmware event queue. All data rx queues forward 1237 * their interrupt to the firmware event queue. 1238 */ 1239 void 1240 t4_intr_all(void *arg) 1241 { 1242 struct adapter *sc = arg; 1243 struct sge_iq *fwq = &sc->sge.fwq; 1244 1245 t4_intr_err(arg); 1246 if (atomic_cmpset_int(&fwq->state, IQS_IDLE, IQS_BUSY)) { 1247 service_iq(fwq, 0); 1248 atomic_cmpset_int(&fwq->state, IQS_BUSY, IQS_IDLE); 1249 } 1250 } 1251 1252 /* Deals with error interrupts */ 1253 void 1254 t4_intr_err(void *arg) 1255 { 1256 struct adapter *sc = arg; 1257 1258 t4_write_reg(sc, MYPF_REG(A_PCIE_PF_CLI), 0); 1259 t4_slow_intr_handler(sc); 1260 } 1261 1262 void 1263 t4_intr_evt(void *arg) 1264 { 1265 struct sge_iq *iq = arg; 1266 1267 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 1268 service_iq(iq, 0); 1269 atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 1270 } 1271 } 1272 1273 void 1274 t4_intr(void *arg) 1275 { 1276 struct sge_iq *iq = arg; 1277 1278 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 1279 service_iq(iq, 0); 1280 atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 1281 } 1282 } 1283 1284 /* 1285 * Deals with anything and everything on the given ingress queue. 1286 */ 1287 static int 1288 service_iq(struct sge_iq *iq, int budget) 1289 { 1290 struct sge_iq *q; 1291 struct sge_rxq *rxq = iq_to_rxq(iq); /* Use iff iq is part of rxq */ 1292 struct sge_fl *fl = &rxq->fl; /* Use iff IQ_HAS_FL */ 1293 struct adapter *sc = iq->adapter; 1294 struct rsp_ctrl *ctrl; 1295 const struct rss_header *rss; 1296 int ndescs = 0, limit, fl_bufs_used = 0; 1297 int rsp_type; 1298 uint32_t lq; 1299 struct mbuf *m0; 1300 STAILQ_HEAD(, sge_iq) iql = STAILQ_HEAD_INITIALIZER(iql); 1301 #if defined(INET) || defined(INET6) 1302 const struct timeval lro_timeout = {0, sc->lro_timeout}; 1303 #endif 1304 1305 limit = budget ? budget : iq->qsize / 8; 1306 1307 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq)); 1308 1309 /* 1310 * We always come back and check the descriptor ring for new indirect 1311 * interrupts and other responses after running a single handler. 1312 */ 1313 for (;;) { 1314 while (is_new_response(iq, &ctrl)) { 1315 1316 rmb(); 1317 1318 m0 = NULL; 1319 rsp_type = G_RSPD_TYPE(ctrl->u.type_gen); 1320 lq = be32toh(ctrl->pldbuflen_qid); 1321 rss = (const void *)iq->cdesc; 1322 1323 switch (rsp_type) { 1324 case X_RSPD_TYPE_FLBUF: 1325 1326 KASSERT(iq->flags & IQ_HAS_FL, 1327 ("%s: data for an iq (%p) with no freelist", 1328 __func__, iq)); 1329 1330 m0 = get_fl_payload(sc, fl, lq, &fl_bufs_used); 1331 if (__predict_false(m0 == NULL)) 1332 goto process_iql; 1333 #ifdef T4_PKT_TIMESTAMP 1334 /* 1335 * 60 bit timestamp for the payload is 1336 * *(uint64_t *)m0->m_pktdat. Note that it is 1337 * in the leading free-space in the mbuf. The 1338 * kernel can clobber it during a pullup, 1339 * m_copymdata, etc. You need to make sure that 1340 * the mbuf reaches you unmolested if you care 1341 * about the timestamp. 1342 */ 1343 *(uint64_t *)m0->m_pktdat = 1344 be64toh(ctrl->u.last_flit) & 1345 0xfffffffffffffff; 1346 #endif 1347 1348 /* fall through */ 1349 1350 case X_RSPD_TYPE_CPL: 1351 KASSERT(rss->opcode < NUM_CPL_CMDS, 1352 ("%s: bad opcode %02x.", __func__, 1353 rss->opcode)); 1354 sc->cpl_handler[rss->opcode](iq, rss, m0); 1355 break; 1356 1357 case X_RSPD_TYPE_INTR: 1358 1359 /* 1360 * Interrupts should be forwarded only to queues 1361 * that are not forwarding their interrupts. 1362 * This means service_iq can recurse but only 1 1363 * level deep. 1364 */ 1365 KASSERT(budget == 0, 1366 ("%s: budget %u, rsp_type %u", __func__, 1367 budget, rsp_type)); 1368 1369 /* 1370 * There are 1K interrupt-capable queues (qids 0 1371 * through 1023). A response type indicating a 1372 * forwarded interrupt with a qid >= 1K is an 1373 * iWARP async notification. 1374 */ 1375 if (lq >= 1024) { 1376 sc->an_handler(iq, ctrl); 1377 break; 1378 } 1379 1380 q = sc->sge.iqmap[lq - sc->sge.iq_start]; 1381 if (atomic_cmpset_int(&q->state, IQS_IDLE, 1382 IQS_BUSY)) { 1383 if (service_iq(q, q->qsize / 8) == 0) { 1384 atomic_cmpset_int(&q->state, 1385 IQS_BUSY, IQS_IDLE); 1386 } else { 1387 STAILQ_INSERT_TAIL(&iql, q, 1388 link); 1389 } 1390 } 1391 break; 1392 1393 default: 1394 KASSERT(0, 1395 ("%s: illegal response type %d on iq %p", 1396 __func__, rsp_type, iq)); 1397 log(LOG_ERR, 1398 "%s: illegal response type %d on iq %p", 1399 device_get_nameunit(sc->dev), rsp_type, iq); 1400 break; 1401 } 1402 1403 if (fl_bufs_used >= 16) { 1404 FL_LOCK(fl); 1405 fl->needed += fl_bufs_used; 1406 refill_fl(sc, fl, 32); 1407 FL_UNLOCK(fl); 1408 fl_bufs_used = 0; 1409 } 1410 1411 iq_next(iq); 1412 if (++ndescs == limit) { 1413 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), 1414 V_CIDXINC(ndescs) | 1415 V_INGRESSQID(iq->cntxt_id) | 1416 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); 1417 ndescs = 0; 1418 1419 #if defined(INET) || defined(INET6) 1420 if (iq->flags & IQ_LRO_ENABLED && 1421 sc->lro_timeout != 0) { 1422 tcp_lro_flush_inactive(&rxq->lro, 1423 &lro_timeout); 1424 } 1425 #endif 1426 1427 if (budget) 1428 return (EINPROGRESS); 1429 } 1430 } 1431 1432 process_iql: 1433 if (STAILQ_EMPTY(&iql)) 1434 break; 1435 1436 /* 1437 * Process the head only, and send it to the back of the list if 1438 * it's still not done. 1439 */ 1440 q = STAILQ_FIRST(&iql); 1441 STAILQ_REMOVE_HEAD(&iql, link); 1442 if (service_iq(q, q->qsize / 8) == 0) 1443 atomic_cmpset_int(&q->state, IQS_BUSY, IQS_IDLE); 1444 else 1445 STAILQ_INSERT_TAIL(&iql, q, link); 1446 } 1447 1448 #if defined(INET) || defined(INET6) 1449 if (iq->flags & IQ_LRO_ENABLED) { 1450 struct lro_ctrl *lro = &rxq->lro; 1451 struct lro_entry *l; 1452 1453 while (!SLIST_EMPTY(&lro->lro_active)) { 1454 l = SLIST_FIRST(&lro->lro_active); 1455 SLIST_REMOVE_HEAD(&lro->lro_active, next); 1456 tcp_lro_flush(lro, l); 1457 } 1458 } 1459 #endif 1460 1461 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), V_CIDXINC(ndescs) | 1462 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params)); 1463 1464 if (iq->flags & IQ_HAS_FL) { 1465 int starved; 1466 1467 FL_LOCK(fl); 1468 fl->needed += fl_bufs_used; 1469 starved = refill_fl(sc, fl, 64); 1470 FL_UNLOCK(fl); 1471 if (__predict_false(starved != 0)) 1472 add_fl_to_sfl(sc, fl); 1473 } 1474 1475 return (0); 1476 } 1477 1478 static inline int 1479 cl_has_metadata(struct sge_fl *fl, struct cluster_layout *cll) 1480 { 1481 int rc = fl->flags & FL_BUF_PACKING || cll->region1 > 0; 1482 1483 if (rc) 1484 MPASS(cll->region3 >= CL_METADATA_SIZE); 1485 1486 return (rc); 1487 } 1488 1489 static inline struct cluster_metadata * 1490 cl_metadata(struct adapter *sc, struct sge_fl *fl, struct cluster_layout *cll, 1491 caddr_t cl) 1492 { 1493 1494 if (cl_has_metadata(fl, cll)) { 1495 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx]; 1496 1497 return ((struct cluster_metadata *)(cl + swz->size) - 1); 1498 } 1499 return (NULL); 1500 } 1501 1502 static int 1503 rxb_free(struct mbuf *m, void *arg1, void *arg2) 1504 { 1505 uma_zone_t zone = arg1; 1506 caddr_t cl = arg2; 1507 1508 uma_zfree(zone, cl); 1509 1510 return (EXT_FREE_OK); 1511 } 1512 1513 /* 1514 * The mbuf returned by this function could be allocated from zone_mbuf or 1515 * constructed in spare room in the cluster. 1516 * 1517 * The mbuf carries the payload in one of these ways 1518 * a) frame inside the mbuf (mbuf from zone_mbuf) 1519 * b) m_cljset (for clusters without metadata) zone_mbuf 1520 * c) m_extaddref (cluster with metadata) inline mbuf 1521 * d) m_extaddref (cluster with metadata) zone_mbuf 1522 */ 1523 static struct mbuf * 1524 get_scatter_segment(struct adapter *sc, struct sge_fl *fl, int total, int flags) 1525 { 1526 struct mbuf *m; 1527 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 1528 struct cluster_layout *cll = &sd->cll; 1529 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx]; 1530 struct hw_buf_info *hwb = &sc->sge.hw_buf_info[cll->hwidx]; 1531 struct cluster_metadata *clm = cl_metadata(sc, fl, cll, sd->cl); 1532 int len, padded_len; 1533 caddr_t payload; 1534 1535 len = min(total, hwb->size - fl->rx_offset); 1536 padded_len = roundup2(len, fl_pad); 1537 payload = sd->cl + cll->region1 + fl->rx_offset; 1538 1539 if (sc->sc_do_rxcopy && len < RX_COPY_THRESHOLD) { 1540 1541 /* 1542 * Copy payload into a freshly allocated mbuf. 1543 */ 1544 1545 m = flags & M_PKTHDR ? 1546 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA); 1547 if (m == NULL) 1548 return (NULL); 1549 fl->mbuf_allocated++; 1550 #ifdef T4_PKT_TIMESTAMP 1551 /* Leave room for a timestamp */ 1552 m->m_data += 8; 1553 #endif 1554 /* copy data to mbuf */ 1555 bcopy(payload, mtod(m, caddr_t), len); 1556 1557 } else if (sd->nmbuf * MSIZE < cll->region1) { 1558 1559 /* 1560 * There's spare room in the cluster for an mbuf. Create one 1561 * and associate it with the payload that's in the cluster too. 1562 */ 1563 1564 MPASS(clm != NULL); 1565 m = (struct mbuf *)(sd->cl + sd->nmbuf * MSIZE); 1566 /* No bzero required */ 1567 if (m_init(m, NULL, 0, M_NOWAIT, MT_DATA, flags | M_NOFREE)) 1568 return (NULL); 1569 fl->mbuf_inlined++; 1570 m_extaddref(m, payload, padded_len, &clm->refcount, rxb_free, 1571 swz->zone, sd->cl); 1572 sd->nmbuf++; 1573 1574 } else { 1575 1576 /* 1577 * Grab an mbuf from zone_mbuf and associate it with the 1578 * payload in the cluster. 1579 */ 1580 1581 m = flags & M_PKTHDR ? 1582 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA); 1583 if (m == NULL) 1584 return (NULL); 1585 fl->mbuf_allocated++; 1586 if (clm != NULL) 1587 m_extaddref(m, payload, padded_len, &clm->refcount, 1588 rxb_free, swz->zone, sd->cl); 1589 else { 1590 m_cljset(m, sd->cl, swz->type); 1591 sd->cl = NULL; /* consumed, not a recycle candidate */ 1592 } 1593 } 1594 if (flags & M_PKTHDR) 1595 m->m_pkthdr.len = total; 1596 m->m_len = len; 1597 1598 if (fl->flags & FL_BUF_PACKING) { 1599 fl->rx_offset += roundup2(padded_len, sc->sge.pack_boundary); 1600 MPASS(fl->rx_offset <= hwb->size); 1601 if (fl->rx_offset < hwb->size) 1602 return (m); /* without advancing the cidx */ 1603 } 1604 1605 if (__predict_false(++fl->cidx == fl->cap)) 1606 fl->cidx = 0; 1607 fl->rx_offset = 0; 1608 1609 return (m); 1610 } 1611 1612 static struct mbuf * 1613 get_fl_payload(struct adapter *sc, struct sge_fl *fl, uint32_t len_newbuf, 1614 int *fl_bufs_used) 1615 { 1616 struct mbuf *m0, *m, **pnext; 1617 u_int nbuf, len; 1618 1619 /* 1620 * No assertion for the fl lock because we don't need it. This routine 1621 * is called only from the rx interrupt handler and it only updates 1622 * fl->cidx. (Contrast that with fl->pidx/fl->needed which could be 1623 * updated in the rx interrupt handler or the starvation helper routine. 1624 * That's why code that manipulates fl->pidx/fl->needed needs the fl 1625 * lock but this routine does not). 1626 */ 1627 1628 nbuf = 0; 1629 len = G_RSPD_LEN(len_newbuf); 1630 if (__predict_false(fl->m0 != NULL)) { 1631 M_ASSERTPKTHDR(fl->m0); 1632 MPASS(len == fl->m0->m_pkthdr.len); 1633 MPASS(fl->remaining < len); 1634 1635 m0 = fl->m0; 1636 pnext = fl->pnext; 1637 len = fl->remaining; 1638 fl->m0 = NULL; 1639 goto get_segment; 1640 } 1641 1642 if (fl->rx_offset > 0 && len_newbuf & F_RSPD_NEWBUF) { 1643 nbuf++; 1644 fl->rx_offset = 0; 1645 if (__predict_false(++fl->cidx == fl->cap)) 1646 fl->cidx = 0; 1647 } 1648 1649 /* 1650 * Payload starts at rx_offset in the current hw buffer. Its length is 1651 * 'len' and it may span multiple hw buffers. 1652 */ 1653 1654 m0 = get_scatter_segment(sc, fl, len, M_PKTHDR); 1655 if (m0 == NULL) 1656 goto done; 1657 len -= m0->m_len; 1658 pnext = &m0->m_next; 1659 while (len > 0) { 1660 nbuf++; 1661 get_segment: 1662 MPASS(fl->rx_offset == 0); 1663 m = get_scatter_segment(sc, fl, len, 0); 1664 if (m == NULL) { 1665 fl->m0 = m0; 1666 fl->pnext = pnext; 1667 fl->remaining = len; 1668 m0 = NULL; 1669 goto done; 1670 } 1671 *pnext = m; 1672 pnext = &m->m_next; 1673 len -= m->m_len; 1674 } 1675 *pnext = NULL; 1676 if (fl->rx_offset == 0) 1677 nbuf++; 1678 done: 1679 (*fl_bufs_used) += nbuf; 1680 return (m0); 1681 } 1682 1683 static int 1684 t4_eth_rx(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0) 1685 { 1686 struct sge_rxq *rxq = iq_to_rxq(iq); 1687 struct ifnet *ifp = rxq->ifp; 1688 const struct cpl_rx_pkt *cpl = (const void *)(rss + 1); 1689 #if defined(INET) || defined(INET6) 1690 struct lro_ctrl *lro = &rxq->lro; 1691 #endif 1692 1693 KASSERT(m0 != NULL, ("%s: no payload with opcode %02x", __func__, 1694 rss->opcode)); 1695 1696 m0->m_pkthdr.len -= fl_pktshift; 1697 m0->m_len -= fl_pktshift; 1698 m0->m_data += fl_pktshift; 1699 1700 m0->m_pkthdr.rcvif = ifp; 1701 m0->m_flags |= M_FLOWID; 1702 m0->m_pkthdr.flowid = be32toh(rss->hash_val); 1703 1704 if (cpl->csum_calc && !cpl->err_vec) { 1705 if (ifp->if_capenable & IFCAP_RXCSUM && 1706 cpl->l2info & htobe32(F_RXF_IP)) { 1707 m0->m_pkthdr.csum_flags = (CSUM_IP_CHECKED | 1708 CSUM_IP_VALID | CSUM_DATA_VALID | CSUM_PSEUDO_HDR); 1709 rxq->rxcsum++; 1710 } else if (ifp->if_capenable & IFCAP_RXCSUM_IPV6 && 1711 cpl->l2info & htobe32(F_RXF_IP6)) { 1712 m0->m_pkthdr.csum_flags = (CSUM_DATA_VALID_IPV6 | 1713 CSUM_PSEUDO_HDR); 1714 rxq->rxcsum++; 1715 } 1716 1717 if (__predict_false(cpl->ip_frag)) 1718 m0->m_pkthdr.csum_data = be16toh(cpl->csum); 1719 else 1720 m0->m_pkthdr.csum_data = 0xffff; 1721 } 1722 1723 if (cpl->vlan_ex) { 1724 m0->m_pkthdr.ether_vtag = be16toh(cpl->vlan); 1725 m0->m_flags |= M_VLANTAG; 1726 rxq->vlan_extraction++; 1727 } 1728 1729 #if defined(INET) || defined(INET6) 1730 if (cpl->l2info & htobe32(F_RXF_LRO) && 1731 iq->flags & IQ_LRO_ENABLED && 1732 tcp_lro_rx(lro, m0, 0) == 0) { 1733 /* queued for LRO */ 1734 } else 1735 #endif 1736 ifp->if_input(ifp, m0); 1737 1738 return (0); 1739 } 1740 1741 /* 1742 * Doesn't fail. Holds on to work requests it can't send right away. 1743 */ 1744 void 1745 t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, struct wrqe *wr) 1746 { 1747 struct sge_eq *eq = &wrq->eq; 1748 int can_reclaim; 1749 caddr_t dst; 1750 1751 TXQ_LOCK_ASSERT_OWNED(wrq); 1752 #ifdef TCP_OFFLOAD 1753 KASSERT((eq->flags & EQ_TYPEMASK) == EQ_OFLD || 1754 (eq->flags & EQ_TYPEMASK) == EQ_CTRL, 1755 ("%s: eq type %d", __func__, eq->flags & EQ_TYPEMASK)); 1756 #else 1757 KASSERT((eq->flags & EQ_TYPEMASK) == EQ_CTRL, 1758 ("%s: eq type %d", __func__, eq->flags & EQ_TYPEMASK)); 1759 #endif 1760 1761 if (__predict_true(wr != NULL)) 1762 STAILQ_INSERT_TAIL(&wrq->wr_list, wr, link); 1763 1764 can_reclaim = reclaimable(eq); 1765 if (__predict_false(eq->flags & EQ_STALLED)) { 1766 if (can_reclaim < tx_resume_threshold(eq)) 1767 return; 1768 eq->flags &= ~EQ_STALLED; 1769 eq->unstalled++; 1770 } 1771 eq->cidx += can_reclaim; 1772 eq->avail += can_reclaim; 1773 if (__predict_false(eq->cidx >= eq->cap)) 1774 eq->cidx -= eq->cap; 1775 1776 while ((wr = STAILQ_FIRST(&wrq->wr_list)) != NULL) { 1777 int ndesc; 1778 1779 if (__predict_false(wr->wr_len < 0 || 1780 wr->wr_len > SGE_MAX_WR_LEN || (wr->wr_len & 0x7))) { 1781 1782 #ifdef INVARIANTS 1783 panic("%s: work request with length %d", __func__, 1784 wr->wr_len); 1785 #endif 1786 #ifdef KDB 1787 kdb_backtrace(); 1788 #endif 1789 log(LOG_ERR, "%s: %s work request with length %d", 1790 device_get_nameunit(sc->dev), __func__, wr->wr_len); 1791 STAILQ_REMOVE_HEAD(&wrq->wr_list, link); 1792 free_wrqe(wr); 1793 continue; 1794 } 1795 1796 ndesc = howmany(wr->wr_len, EQ_ESIZE); 1797 if (eq->avail < ndesc) { 1798 wrq->no_desc++; 1799 break; 1800 } 1801 1802 dst = (void *)&eq->desc[eq->pidx]; 1803 copy_to_txd(eq, wrtod(wr), &dst, wr->wr_len); 1804 1805 eq->pidx += ndesc; 1806 eq->avail -= ndesc; 1807 if (__predict_false(eq->pidx >= eq->cap)) 1808 eq->pidx -= eq->cap; 1809 1810 eq->pending += ndesc; 1811 if (eq->pending >= 8) 1812 ring_eq_db(sc, eq); 1813 1814 wrq->tx_wrs++; 1815 STAILQ_REMOVE_HEAD(&wrq->wr_list, link); 1816 free_wrqe(wr); 1817 1818 if (eq->avail < 8) { 1819 can_reclaim = reclaimable(eq); 1820 eq->cidx += can_reclaim; 1821 eq->avail += can_reclaim; 1822 if (__predict_false(eq->cidx >= eq->cap)) 1823 eq->cidx -= eq->cap; 1824 } 1825 } 1826 1827 if (eq->pending) 1828 ring_eq_db(sc, eq); 1829 1830 if (wr != NULL) { 1831 eq->flags |= EQ_STALLED; 1832 if (callout_pending(&eq->tx_callout) == 0) 1833 callout_reset(&eq->tx_callout, 1, t4_tx_callout, eq); 1834 } 1835 } 1836 1837 /* Per-packet header in a coalesced tx WR, before the SGL starts (in flits) */ 1838 #define TXPKTS_PKT_HDR ((\ 1839 sizeof(struct ulp_txpkt) + \ 1840 sizeof(struct ulptx_idata) + \ 1841 sizeof(struct cpl_tx_pkt_core) \ 1842 ) / 8) 1843 1844 /* Header of a coalesced tx WR, before SGL of first packet (in flits) */ 1845 #define TXPKTS_WR_HDR (\ 1846 sizeof(struct fw_eth_tx_pkts_wr) / 8 + \ 1847 TXPKTS_PKT_HDR) 1848 1849 /* Header of a tx WR, before SGL of first packet (in flits) */ 1850 #define TXPKT_WR_HDR ((\ 1851 sizeof(struct fw_eth_tx_pkt_wr) + \ 1852 sizeof(struct cpl_tx_pkt_core) \ 1853 ) / 8 ) 1854 1855 /* Header of a tx LSO WR, before SGL of first packet (in flits) */ 1856 #define TXPKT_LSO_WR_HDR ((\ 1857 sizeof(struct fw_eth_tx_pkt_wr) + \ 1858 sizeof(struct cpl_tx_pkt_lso_core) + \ 1859 sizeof(struct cpl_tx_pkt_core) \ 1860 ) / 8 ) 1861 1862 int 1863 t4_eth_tx(struct ifnet *ifp, struct sge_txq *txq, struct mbuf *m) 1864 { 1865 struct port_info *pi = (void *)ifp->if_softc; 1866 struct adapter *sc = pi->adapter; 1867 struct sge_eq *eq = &txq->eq; 1868 struct buf_ring *br = txq->br; 1869 struct mbuf *next; 1870 int rc, coalescing, can_reclaim; 1871 struct txpkts txpkts; 1872 struct sgl sgl; 1873 1874 TXQ_LOCK_ASSERT_OWNED(txq); 1875 KASSERT(m, ("%s: called with nothing to do.", __func__)); 1876 KASSERT((eq->flags & EQ_TYPEMASK) == EQ_ETH, 1877 ("%s: eq type %d", __func__, eq->flags & EQ_TYPEMASK)); 1878 1879 prefetch(&eq->desc[eq->pidx]); 1880 prefetch(&txq->sdesc[eq->pidx]); 1881 1882 txpkts.npkt = 0;/* indicates there's nothing in txpkts */ 1883 coalescing = 0; 1884 1885 can_reclaim = reclaimable(eq); 1886 if (__predict_false(eq->flags & EQ_STALLED)) { 1887 if (can_reclaim < tx_resume_threshold(eq)) { 1888 txq->m = m; 1889 return (0); 1890 } 1891 eq->flags &= ~EQ_STALLED; 1892 eq->unstalled++; 1893 } 1894 1895 if (__predict_false(eq->flags & EQ_DOOMED)) { 1896 m_freem(m); 1897 while ((m = buf_ring_dequeue_sc(txq->br)) != NULL) 1898 m_freem(m); 1899 return (ENETDOWN); 1900 } 1901 1902 if (eq->avail < 8 && can_reclaim) 1903 reclaim_tx_descs(txq, can_reclaim, 32); 1904 1905 for (; m; m = next ? next : drbr_dequeue(ifp, br)) { 1906 1907 if (eq->avail < 8) 1908 break; 1909 1910 next = m->m_nextpkt; 1911 m->m_nextpkt = NULL; 1912 1913 if (next || buf_ring_peek(br)) 1914 coalescing = 1; 1915 1916 rc = get_pkt_sgl(txq, &m, &sgl, coalescing); 1917 if (rc != 0) { 1918 if (rc == ENOMEM) { 1919 1920 /* Short of resources, suspend tx */ 1921 1922 m->m_nextpkt = next; 1923 break; 1924 } 1925 1926 /* 1927 * Unrecoverable error for this packet, throw it away 1928 * and move on to the next. get_pkt_sgl may already 1929 * have freed m (it will be NULL in that case and the 1930 * m_freem here is still safe). 1931 */ 1932 1933 m_freem(m); 1934 continue; 1935 } 1936 1937 if (coalescing && 1938 add_to_txpkts(pi, txq, &txpkts, m, &sgl) == 0) { 1939 1940 /* Successfully absorbed into txpkts */ 1941 1942 write_ulp_cpl_sgl(pi, txq, &txpkts, m, &sgl); 1943 goto doorbell; 1944 } 1945 1946 /* 1947 * We weren't coalescing to begin with, or current frame could 1948 * not be coalesced (add_to_txpkts flushes txpkts if a frame 1949 * given to it can't be coalesced). Either way there should be 1950 * nothing in txpkts. 1951 */ 1952 KASSERT(txpkts.npkt == 0, 1953 ("%s: txpkts not empty: %d", __func__, txpkts.npkt)); 1954 1955 /* We're sending out individual packets now */ 1956 coalescing = 0; 1957 1958 if (eq->avail < 8) 1959 reclaim_tx_descs(txq, 0, 8); 1960 rc = write_txpkt_wr(pi, txq, m, &sgl); 1961 if (rc != 0) { 1962 1963 /* Short of hardware descriptors, suspend tx */ 1964 1965 /* 1966 * This is an unlikely but expensive failure. We've 1967 * done all the hard work (DMA mappings etc.) and now we 1968 * can't send out the packet. What's worse, we have to 1969 * spend even more time freeing up everything in sgl. 1970 */ 1971 txq->no_desc++; 1972 free_pkt_sgl(txq, &sgl); 1973 1974 m->m_nextpkt = next; 1975 break; 1976 } 1977 1978 ETHER_BPF_MTAP(ifp, m); 1979 if (sgl.nsegs == 0) 1980 m_freem(m); 1981 doorbell: 1982 if (eq->pending >= 8) 1983 ring_eq_db(sc, eq); 1984 1985 can_reclaim = reclaimable(eq); 1986 if (can_reclaim >= 32) 1987 reclaim_tx_descs(txq, can_reclaim, 64); 1988 } 1989 1990 if (txpkts.npkt > 0) 1991 write_txpkts_wr(txq, &txpkts); 1992 1993 /* 1994 * m not NULL means there was an error but we haven't thrown it away. 1995 * This can happen when we're short of tx descriptors (no_desc) or maybe 1996 * even DMA maps (no_dmamap). Either way, a credit flush and reclaim 1997 * will get things going again. 1998 */ 1999 if (m && !(eq->flags & EQ_CRFLUSHED)) { 2000 struct tx_sdesc *txsd = &txq->sdesc[eq->pidx]; 2001 2002 /* 2003 * If EQ_CRFLUSHED is not set then we know we have at least one 2004 * available descriptor because any WR that reduces eq->avail to 2005 * 0 also sets EQ_CRFLUSHED. 2006 */ 2007 KASSERT(eq->avail > 0, ("%s: no space for eqflush.", __func__)); 2008 2009 txsd->desc_used = 1; 2010 txsd->credits = 0; 2011 write_eqflush_wr(eq); 2012 } 2013 txq->m = m; 2014 2015 if (eq->pending) 2016 ring_eq_db(sc, eq); 2017 2018 reclaim_tx_descs(txq, 0, 128); 2019 2020 if (eq->flags & EQ_STALLED && callout_pending(&eq->tx_callout) == 0) 2021 callout_reset(&eq->tx_callout, 1, t4_tx_callout, eq); 2022 2023 return (0); 2024 } 2025 2026 void 2027 t4_update_fl_bufsize(struct ifnet *ifp) 2028 { 2029 struct port_info *pi = ifp->if_softc; 2030 struct adapter *sc = pi->adapter; 2031 struct sge_rxq *rxq; 2032 #ifdef TCP_OFFLOAD 2033 struct sge_ofld_rxq *ofld_rxq; 2034 #endif 2035 struct sge_fl *fl; 2036 int i, maxp, mtu = ifp->if_mtu; 2037 2038 maxp = mtu_to_max_payload(sc, mtu, 0); 2039 for_each_rxq(pi, i, rxq) { 2040 fl = &rxq->fl; 2041 2042 FL_LOCK(fl); 2043 find_best_refill_source(sc, fl, maxp); 2044 FL_UNLOCK(fl); 2045 } 2046 #ifdef TCP_OFFLOAD 2047 maxp = mtu_to_max_payload(sc, mtu, 1); 2048 for_each_ofld_rxq(pi, i, ofld_rxq) { 2049 fl = &ofld_rxq->fl; 2050 2051 FL_LOCK(fl); 2052 find_best_refill_source(sc, fl, maxp); 2053 FL_UNLOCK(fl); 2054 } 2055 #endif 2056 } 2057 2058 int 2059 can_resume_tx(struct sge_eq *eq) 2060 { 2061 return (reclaimable(eq) >= tx_resume_threshold(eq)); 2062 } 2063 2064 static inline void 2065 init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int pktc_idx, 2066 int qsize, int esize) 2067 { 2068 KASSERT(tmr_idx >= 0 && tmr_idx < SGE_NTIMERS, 2069 ("%s: bad tmr_idx %d", __func__, tmr_idx)); 2070 KASSERT(pktc_idx < SGE_NCOUNTERS, /* -ve is ok, means don't use */ 2071 ("%s: bad pktc_idx %d", __func__, pktc_idx)); 2072 2073 iq->flags = 0; 2074 iq->adapter = sc; 2075 iq->intr_params = V_QINTR_TIMER_IDX(tmr_idx); 2076 iq->intr_pktc_idx = SGE_NCOUNTERS - 1; 2077 if (pktc_idx >= 0) { 2078 iq->intr_params |= F_QINTR_CNT_EN; 2079 iq->intr_pktc_idx = pktc_idx; 2080 } 2081 iq->qsize = roundup2(qsize, 16); /* See FW_IQ_CMD/iqsize */ 2082 iq->esize = max(esize, 16); /* See FW_IQ_CMD/iqesize */ 2083 } 2084 2085 static inline void 2086 init_fl(struct adapter *sc, struct sge_fl *fl, int qsize, int maxp, int pack, 2087 char *name) 2088 { 2089 2090 fl->qsize = qsize; 2091 strlcpy(fl->lockname, name, sizeof(fl->lockname)); 2092 if (pack) 2093 fl->flags |= FL_BUF_PACKING; 2094 find_best_refill_source(sc, fl, maxp); 2095 find_safe_refill_source(sc, fl); 2096 } 2097 2098 static inline void 2099 init_eq(struct sge_eq *eq, int eqtype, int qsize, uint8_t tx_chan, 2100 uint16_t iqid, char *name) 2101 { 2102 KASSERT(tx_chan < NCHAN, ("%s: bad tx channel %d", __func__, tx_chan)); 2103 KASSERT(eqtype <= EQ_TYPEMASK, ("%s: bad qtype %d", __func__, eqtype)); 2104 2105 eq->flags = eqtype & EQ_TYPEMASK; 2106 eq->tx_chan = tx_chan; 2107 eq->iqid = iqid; 2108 eq->qsize = qsize; 2109 strlcpy(eq->lockname, name, sizeof(eq->lockname)); 2110 2111 TASK_INIT(&eq->tx_task, 0, t4_tx_task, eq); 2112 callout_init(&eq->tx_callout, CALLOUT_MPSAFE); 2113 } 2114 2115 static int 2116 alloc_ring(struct adapter *sc, size_t len, bus_dma_tag_t *tag, 2117 bus_dmamap_t *map, bus_addr_t *pa, void **va) 2118 { 2119 int rc; 2120 2121 rc = bus_dma_tag_create(sc->dmat, 512, 0, BUS_SPACE_MAXADDR, 2122 BUS_SPACE_MAXADDR, NULL, NULL, len, 1, len, 0, NULL, NULL, tag); 2123 if (rc != 0) { 2124 device_printf(sc->dev, "cannot allocate DMA tag: %d\n", rc); 2125 goto done; 2126 } 2127 2128 rc = bus_dmamem_alloc(*tag, va, 2129 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, map); 2130 if (rc != 0) { 2131 device_printf(sc->dev, "cannot allocate DMA memory: %d\n", rc); 2132 goto done; 2133 } 2134 2135 rc = bus_dmamap_load(*tag, *map, *va, len, oneseg_dma_callback, pa, 0); 2136 if (rc != 0) { 2137 device_printf(sc->dev, "cannot load DMA map: %d\n", rc); 2138 goto done; 2139 } 2140 done: 2141 if (rc) 2142 free_ring(sc, *tag, *map, *pa, *va); 2143 2144 return (rc); 2145 } 2146 2147 static int 2148 free_ring(struct adapter *sc, bus_dma_tag_t tag, bus_dmamap_t map, 2149 bus_addr_t pa, void *va) 2150 { 2151 if (pa) 2152 bus_dmamap_unload(tag, map); 2153 if (va) 2154 bus_dmamem_free(tag, va, map); 2155 if (tag) 2156 bus_dma_tag_destroy(tag); 2157 2158 return (0); 2159 } 2160 2161 /* 2162 * Allocates the ring for an ingress queue and an optional freelist. If the 2163 * freelist is specified it will be allocated and then associated with the 2164 * ingress queue. 2165 * 2166 * Returns errno on failure. Resources allocated up to that point may still be 2167 * allocated. Caller is responsible for cleanup in case this function fails. 2168 * 2169 * If the ingress queue will take interrupts directly (iq->flags & IQ_INTR) then 2170 * the intr_idx specifies the vector, starting from 0. Otherwise it specifies 2171 * the abs_id of the ingress queue to which its interrupts should be forwarded. 2172 */ 2173 static int 2174 alloc_iq_fl(struct port_info *pi, struct sge_iq *iq, struct sge_fl *fl, 2175 int intr_idx, int cong) 2176 { 2177 int rc, i, cntxt_id; 2178 size_t len; 2179 struct fw_iq_cmd c; 2180 struct adapter *sc = iq->adapter; 2181 __be32 v = 0; 2182 2183 len = iq->qsize * iq->esize; 2184 rc = alloc_ring(sc, len, &iq->desc_tag, &iq->desc_map, &iq->ba, 2185 (void **)&iq->desc); 2186 if (rc != 0) 2187 return (rc); 2188 2189 bzero(&c, sizeof(c)); 2190 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 2191 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) | 2192 V_FW_IQ_CMD_VFN(0)); 2193 2194 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART | 2195 FW_LEN16(c)); 2196 2197 /* Special handling for firmware event queue */ 2198 if (iq == &sc->sge.fwq) 2199 v |= F_FW_IQ_CMD_IQASYNCH; 2200 2201 if (iq->flags & IQ_INTR) { 2202 KASSERT(intr_idx < sc->intr_count, 2203 ("%s: invalid direct intr_idx %d", __func__, intr_idx)); 2204 } else 2205 v |= F_FW_IQ_CMD_IQANDST; 2206 v |= V_FW_IQ_CMD_IQANDSTINDEX(intr_idx); 2207 2208 c.type_to_iqandstindex = htobe32(v | 2209 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) | 2210 V_FW_IQ_CMD_VIID(pi->viid) | 2211 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT)); 2212 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->tx_chan) | 2213 F_FW_IQ_CMD_IQGTSMODE | 2214 V_FW_IQ_CMD_IQINTCNTTHRESH(iq->intr_pktc_idx) | 2215 V_FW_IQ_CMD_IQESIZE(ilog2(iq->esize) - 4)); 2216 c.iqsize = htobe16(iq->qsize); 2217 c.iqaddr = htobe64(iq->ba); 2218 if (cong >= 0) 2219 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN); 2220 2221 if (fl) { 2222 mtx_init(&fl->fl_lock, fl->lockname, NULL, MTX_DEF); 2223 2224 len = fl->qsize * RX_FL_ESIZE; 2225 rc = alloc_ring(sc, len, &fl->desc_tag, &fl->desc_map, 2226 &fl->ba, (void **)&fl->desc); 2227 if (rc) 2228 return (rc); 2229 2230 /* Allocate space for one software descriptor per buffer. */ 2231 fl->cap = (fl->qsize - spg_len / RX_FL_ESIZE) * 8; 2232 rc = alloc_fl_sdesc(fl); 2233 if (rc != 0) { 2234 device_printf(sc->dev, 2235 "failed to setup fl software descriptors: %d\n", 2236 rc); 2237 return (rc); 2238 } 2239 fl->needed = fl->cap; 2240 fl->lowat = fl->flags & FL_BUF_PACKING ? 2241 roundup2(sc->sge.fl_starve_threshold2, 8) : 2242 roundup2(sc->sge.fl_starve_threshold, 8); 2243 2244 c.iqns_to_fl0congen |= 2245 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) | 2246 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO | 2247 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) | 2248 (fl->flags & FL_BUF_PACKING ? F_FW_IQ_CMD_FL0PACKEN : 2249 0)); 2250 if (cong >= 0) { 2251 c.iqns_to_fl0congen |= 2252 htobe32(V_FW_IQ_CMD_FL0CNGCHMAP(cong) | 2253 F_FW_IQ_CMD_FL0CONGCIF | 2254 F_FW_IQ_CMD_FL0CONGEN); 2255 } 2256 c.fl0dcaen_to_fl0cidxfthresh = 2257 htobe16(V_FW_IQ_CMD_FL0FBMIN(X_FETCHBURSTMIN_64B) | 2258 V_FW_IQ_CMD_FL0FBMAX(X_FETCHBURSTMAX_512B)); 2259 c.fl0size = htobe16(fl->qsize); 2260 c.fl0addr = htobe64(fl->ba); 2261 } 2262 2263 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 2264 if (rc != 0) { 2265 device_printf(sc->dev, 2266 "failed to create ingress queue: %d\n", rc); 2267 return (rc); 2268 } 2269 2270 iq->cdesc = iq->desc; 2271 iq->cidx = 0; 2272 iq->gen = 1; 2273 iq->intr_next = iq->intr_params; 2274 iq->cntxt_id = be16toh(c.iqid); 2275 iq->abs_id = be16toh(c.physiqid); 2276 iq->flags |= IQ_ALLOCATED; 2277 2278 cntxt_id = iq->cntxt_id - sc->sge.iq_start; 2279 if (cntxt_id >= sc->sge.niq) { 2280 panic ("%s: iq->cntxt_id (%d) more than the max (%d)", __func__, 2281 cntxt_id, sc->sge.niq - 1); 2282 } 2283 sc->sge.iqmap[cntxt_id] = iq; 2284 2285 if (fl) { 2286 fl->cntxt_id = be16toh(c.fl0id); 2287 fl->pidx = fl->cidx = 0; 2288 2289 cntxt_id = fl->cntxt_id - sc->sge.eq_start; 2290 if (cntxt_id >= sc->sge.neq) { 2291 panic("%s: fl->cntxt_id (%d) more than the max (%d)", 2292 __func__, cntxt_id, sc->sge.neq - 1); 2293 } 2294 sc->sge.eqmap[cntxt_id] = (void *)fl; 2295 2296 FL_LOCK(fl); 2297 /* Enough to make sure the SGE doesn't think it's starved */ 2298 refill_fl(sc, fl, fl->lowat); 2299 FL_UNLOCK(fl); 2300 2301 iq->flags |= IQ_HAS_FL; 2302 } 2303 2304 if (is_t5(sc) && cong >= 0) { 2305 uint32_t param, val; 2306 2307 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 2308 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) | 2309 V_FW_PARAMS_PARAM_YZ(iq->cntxt_id); 2310 if (cong == 0) 2311 val = 1 << 19; 2312 else { 2313 val = 2 << 19; 2314 for (i = 0; i < 4; i++) { 2315 if (cong & (1 << i)) 2316 val |= 1 << (i << 2); 2317 } 2318 } 2319 2320 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 2321 if (rc != 0) { 2322 /* report error but carry on */ 2323 device_printf(sc->dev, 2324 "failed to set congestion manager context for " 2325 "ingress queue %d: %d\n", iq->cntxt_id, rc); 2326 } 2327 } 2328 2329 /* Enable IQ interrupts */ 2330 atomic_store_rel_int(&iq->state, IQS_IDLE); 2331 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), V_SEINTARM(iq->intr_params) | 2332 V_INGRESSQID(iq->cntxt_id)); 2333 2334 return (0); 2335 } 2336 2337 static int 2338 free_iq_fl(struct port_info *pi, struct sge_iq *iq, struct sge_fl *fl) 2339 { 2340 int rc; 2341 struct adapter *sc = iq->adapter; 2342 device_t dev; 2343 2344 if (sc == NULL) 2345 return (0); /* nothing to do */ 2346 2347 dev = pi ? pi->dev : sc->dev; 2348 2349 if (iq->flags & IQ_ALLOCATED) { 2350 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0, 2351 FW_IQ_TYPE_FL_INT_CAP, iq->cntxt_id, 2352 fl ? fl->cntxt_id : 0xffff, 0xffff); 2353 if (rc != 0) { 2354 device_printf(dev, 2355 "failed to free queue %p: %d\n", iq, rc); 2356 return (rc); 2357 } 2358 iq->flags &= ~IQ_ALLOCATED; 2359 } 2360 2361 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, iq->desc); 2362 2363 bzero(iq, sizeof(*iq)); 2364 2365 if (fl) { 2366 free_ring(sc, fl->desc_tag, fl->desc_map, fl->ba, 2367 fl->desc); 2368 2369 if (fl->sdesc) 2370 free_fl_sdesc(sc, fl); 2371 2372 if (mtx_initialized(&fl->fl_lock)) 2373 mtx_destroy(&fl->fl_lock); 2374 2375 bzero(fl, sizeof(*fl)); 2376 } 2377 2378 return (0); 2379 } 2380 2381 static void 2382 add_fl_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid, 2383 struct sge_fl *fl) 2384 { 2385 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 2386 2387 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL, 2388 "freelist"); 2389 children = SYSCTL_CHILDREN(oid); 2390 2391 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 2392 CTLTYPE_INT | CTLFLAG_RD, &fl->cntxt_id, 0, sysctl_uint16, "I", 2393 "SGE context id of the freelist"); 2394 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &fl->cidx, 2395 0, "consumer index"); 2396 if (fl->flags & FL_BUF_PACKING) { 2397 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rx_offset", 2398 CTLFLAG_RD, &fl->rx_offset, 0, "packing rx offset"); 2399 } 2400 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &fl->pidx, 2401 0, "producer index"); 2402 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_allocated", 2403 CTLFLAG_RD, &fl->mbuf_allocated, "# of mbuf allocated"); 2404 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_inlined", 2405 CTLFLAG_RD, &fl->mbuf_inlined, "# of mbuf inlined in clusters"); 2406 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_allocated", 2407 CTLFLAG_RD, &fl->cl_allocated, "# of clusters allocated"); 2408 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_recycled", 2409 CTLFLAG_RD, &fl->cl_recycled, "# of clusters recycled"); 2410 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_fast_recycled", 2411 CTLFLAG_RD, &fl->cl_fast_recycled, "# of clusters recycled (fast)"); 2412 } 2413 2414 static int 2415 alloc_fwq(struct adapter *sc) 2416 { 2417 int rc, intr_idx; 2418 struct sge_iq *fwq = &sc->sge.fwq; 2419 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev); 2420 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 2421 2422 init_iq(fwq, sc, 0, 0, FW_IQ_QSIZE, FW_IQ_ESIZE); 2423 fwq->flags |= IQ_INTR; /* always */ 2424 intr_idx = sc->intr_count > 1 ? 1 : 0; 2425 rc = alloc_iq_fl(sc->port[0], fwq, NULL, intr_idx, -1); 2426 if (rc != 0) { 2427 device_printf(sc->dev, 2428 "failed to create firmware event queue: %d\n", rc); 2429 return (rc); 2430 } 2431 2432 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "fwq", CTLFLAG_RD, 2433 NULL, "firmware event queue"); 2434 children = SYSCTL_CHILDREN(oid); 2435 2436 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "abs_id", 2437 CTLTYPE_INT | CTLFLAG_RD, &fwq->abs_id, 0, sysctl_uint16, "I", 2438 "absolute id of the queue"); 2439 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "cntxt_id", 2440 CTLTYPE_INT | CTLFLAG_RD, &fwq->cntxt_id, 0, sysctl_uint16, "I", 2441 "SGE context id of the queue"); 2442 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "cidx", 2443 CTLTYPE_INT | CTLFLAG_RD, &fwq->cidx, 0, sysctl_uint16, "I", 2444 "consumer index"); 2445 2446 return (0); 2447 } 2448 2449 static int 2450 free_fwq(struct adapter *sc) 2451 { 2452 return free_iq_fl(NULL, &sc->sge.fwq, NULL); 2453 } 2454 2455 static int 2456 alloc_mgmtq(struct adapter *sc) 2457 { 2458 int rc; 2459 struct sge_wrq *mgmtq = &sc->sge.mgmtq; 2460 char name[16]; 2461 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev); 2462 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 2463 2464 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "mgmtq", CTLFLAG_RD, 2465 NULL, "management queue"); 2466 2467 snprintf(name, sizeof(name), "%s mgmtq", device_get_nameunit(sc->dev)); 2468 init_eq(&mgmtq->eq, EQ_CTRL, CTRL_EQ_QSIZE, sc->port[0]->tx_chan, 2469 sc->sge.fwq.cntxt_id, name); 2470 rc = alloc_wrq(sc, NULL, mgmtq, oid); 2471 if (rc != 0) { 2472 device_printf(sc->dev, 2473 "failed to create management queue: %d\n", rc); 2474 return (rc); 2475 } 2476 2477 return (0); 2478 } 2479 2480 static int 2481 free_mgmtq(struct adapter *sc) 2482 { 2483 2484 return free_wrq(sc, &sc->sge.mgmtq); 2485 } 2486 2487 static inline int 2488 tnl_cong(struct port_info *pi) 2489 { 2490 2491 if (cong_drop == -1) 2492 return (-1); 2493 else if (cong_drop == 1) 2494 return (0); 2495 else 2496 return (pi->rx_chan_map); 2497 } 2498 2499 static int 2500 alloc_rxq(struct port_info *pi, struct sge_rxq *rxq, int intr_idx, int idx, 2501 struct sysctl_oid *oid) 2502 { 2503 int rc; 2504 struct sysctl_oid_list *children; 2505 char name[16]; 2506 2507 rc = alloc_iq_fl(pi, &rxq->iq, &rxq->fl, intr_idx, tnl_cong(pi)); 2508 if (rc != 0) 2509 return (rc); 2510 2511 FL_LOCK(&rxq->fl); 2512 refill_fl(pi->adapter, &rxq->fl, rxq->fl.needed / 8); 2513 FL_UNLOCK(&rxq->fl); 2514 2515 #if defined(INET) || defined(INET6) 2516 rc = tcp_lro_init(&rxq->lro); 2517 if (rc != 0) 2518 return (rc); 2519 rxq->lro.ifp = pi->ifp; /* also indicates LRO init'ed */ 2520 2521 if (pi->ifp->if_capenable & IFCAP_LRO) 2522 rxq->iq.flags |= IQ_LRO_ENABLED; 2523 #endif 2524 rxq->ifp = pi->ifp; 2525 2526 children = SYSCTL_CHILDREN(oid); 2527 2528 snprintf(name, sizeof(name), "%d", idx); 2529 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 2530 NULL, "rx queue"); 2531 children = SYSCTL_CHILDREN(oid); 2532 2533 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "abs_id", 2534 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.abs_id, 0, sysctl_uint16, "I", 2535 "absolute id of the queue"); 2536 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cntxt_id", 2537 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.cntxt_id, 0, sysctl_uint16, "I", 2538 "SGE context id of the queue"); 2539 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cidx", 2540 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.cidx, 0, sysctl_uint16, "I", 2541 "consumer index"); 2542 #if defined(INET) || defined(INET6) 2543 SYSCTL_ADD_INT(&pi->ctx, children, OID_AUTO, "lro_queued", CTLFLAG_RD, 2544 &rxq->lro.lro_queued, 0, NULL); 2545 SYSCTL_ADD_INT(&pi->ctx, children, OID_AUTO, "lro_flushed", CTLFLAG_RD, 2546 &rxq->lro.lro_flushed, 0, NULL); 2547 #endif 2548 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "rxcsum", CTLFLAG_RD, 2549 &rxq->rxcsum, "# of times hardware assisted with checksum"); 2550 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "vlan_extraction", 2551 CTLFLAG_RD, &rxq->vlan_extraction, 2552 "# of times hardware extracted 802.1Q tag"); 2553 2554 add_fl_sysctls(&pi->ctx, oid, &rxq->fl); 2555 2556 return (rc); 2557 } 2558 2559 static int 2560 free_rxq(struct port_info *pi, struct sge_rxq *rxq) 2561 { 2562 int rc; 2563 2564 #if defined(INET) || defined(INET6) 2565 if (rxq->lro.ifp) { 2566 tcp_lro_free(&rxq->lro); 2567 rxq->lro.ifp = NULL; 2568 } 2569 #endif 2570 2571 rc = free_iq_fl(pi, &rxq->iq, &rxq->fl); 2572 if (rc == 0) 2573 bzero(rxq, sizeof(*rxq)); 2574 2575 return (rc); 2576 } 2577 2578 #ifdef TCP_OFFLOAD 2579 static int 2580 alloc_ofld_rxq(struct port_info *pi, struct sge_ofld_rxq *ofld_rxq, 2581 int intr_idx, int idx, struct sysctl_oid *oid) 2582 { 2583 int rc; 2584 struct sysctl_oid_list *children; 2585 char name[16]; 2586 2587 rc = alloc_iq_fl(pi, &ofld_rxq->iq, &ofld_rxq->fl, intr_idx, 2588 pi->rx_chan_map); 2589 if (rc != 0) 2590 return (rc); 2591 2592 children = SYSCTL_CHILDREN(oid); 2593 2594 snprintf(name, sizeof(name), "%d", idx); 2595 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 2596 NULL, "rx queue"); 2597 children = SYSCTL_CHILDREN(oid); 2598 2599 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "abs_id", 2600 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.abs_id, 0, sysctl_uint16, 2601 "I", "absolute id of the queue"); 2602 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cntxt_id", 2603 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.cntxt_id, 0, sysctl_uint16, 2604 "I", "SGE context id of the queue"); 2605 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cidx", 2606 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.cidx, 0, sysctl_uint16, "I", 2607 "consumer index"); 2608 2609 add_fl_sysctls(&pi->ctx, oid, &ofld_rxq->fl); 2610 2611 return (rc); 2612 } 2613 2614 static int 2615 free_ofld_rxq(struct port_info *pi, struct sge_ofld_rxq *ofld_rxq) 2616 { 2617 int rc; 2618 2619 rc = free_iq_fl(pi, &ofld_rxq->iq, &ofld_rxq->fl); 2620 if (rc == 0) 2621 bzero(ofld_rxq, sizeof(*ofld_rxq)); 2622 2623 return (rc); 2624 } 2625 #endif 2626 2627 #ifdef DEV_NETMAP 2628 static int 2629 alloc_nm_rxq(struct port_info *pi, struct sge_nm_rxq *nm_rxq, int intr_idx, 2630 int idx, struct sysctl_oid *oid) 2631 { 2632 int rc; 2633 struct sysctl_oid_list *children; 2634 struct sysctl_ctx_list *ctx; 2635 char name[16]; 2636 size_t len; 2637 struct adapter *sc = pi->adapter; 2638 struct netmap_adapter *na = NA(pi->nm_ifp); 2639 2640 MPASS(na != NULL); 2641 2642 len = pi->qsize_rxq * RX_IQ_ESIZE; 2643 rc = alloc_ring(sc, len, &nm_rxq->iq_desc_tag, &nm_rxq->iq_desc_map, 2644 &nm_rxq->iq_ba, (void **)&nm_rxq->iq_desc); 2645 if (rc != 0) 2646 return (rc); 2647 2648 len = na->num_rx_desc * RX_FL_ESIZE + spg_len; 2649 rc = alloc_ring(sc, len, &nm_rxq->fl_desc_tag, &nm_rxq->fl_desc_map, 2650 &nm_rxq->fl_ba, (void **)&nm_rxq->fl_desc); 2651 if (rc != 0) 2652 return (rc); 2653 2654 nm_rxq->pi = pi; 2655 nm_rxq->nid = idx; 2656 nm_rxq->iq_cidx = 0; 2657 nm_rxq->iq_sidx = pi->qsize_rxq - spg_len / RX_IQ_ESIZE; 2658 nm_rxq->iq_gen = F_RSPD_GEN; 2659 nm_rxq->fl_pidx = nm_rxq->fl_cidx = 0; 2660 nm_rxq->fl_sidx = na->num_rx_desc; 2661 nm_rxq->intr_idx = intr_idx; 2662 2663 ctx = &pi->ctx; 2664 children = SYSCTL_CHILDREN(oid); 2665 2666 snprintf(name, sizeof(name), "%d", idx); 2667 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, name, CTLFLAG_RD, NULL, 2668 "rx queue"); 2669 children = SYSCTL_CHILDREN(oid); 2670 2671 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "abs_id", 2672 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_abs_id, 0, sysctl_uint16, 2673 "I", "absolute id of the queue"); 2674 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 2675 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cntxt_id, 0, sysctl_uint16, 2676 "I", "SGE context id of the queue"); 2677 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx", 2678 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cidx, 0, sysctl_uint16, "I", 2679 "consumer index"); 2680 2681 children = SYSCTL_CHILDREN(oid); 2682 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL, 2683 "freelist"); 2684 children = SYSCTL_CHILDREN(oid); 2685 2686 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 2687 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->fl_cntxt_id, 0, sysctl_uint16, 2688 "I", "SGE context id of the freelist"); 2689 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, 2690 &nm_rxq->fl_cidx, 0, "consumer index"); 2691 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, 2692 &nm_rxq->fl_pidx, 0, "producer index"); 2693 2694 return (rc); 2695 } 2696 2697 2698 static int 2699 free_nm_rxq(struct port_info *pi, struct sge_nm_rxq *nm_rxq) 2700 { 2701 struct adapter *sc = pi->adapter; 2702 2703 free_ring(sc, nm_rxq->iq_desc_tag, nm_rxq->iq_desc_map, nm_rxq->iq_ba, 2704 nm_rxq->iq_desc); 2705 free_ring(sc, nm_rxq->fl_desc_tag, nm_rxq->fl_desc_map, nm_rxq->fl_ba, 2706 nm_rxq->fl_desc); 2707 2708 return (0); 2709 } 2710 2711 static int 2712 alloc_nm_txq(struct port_info *pi, struct sge_nm_txq *nm_txq, int iqidx, int idx, 2713 struct sysctl_oid *oid) 2714 { 2715 int rc; 2716 size_t len; 2717 struct adapter *sc = pi->adapter; 2718 struct netmap_adapter *na = NA(pi->nm_ifp); 2719 char name[16]; 2720 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 2721 2722 len = na->num_tx_desc * EQ_ESIZE + spg_len; 2723 rc = alloc_ring(sc, len, &nm_txq->desc_tag, &nm_txq->desc_map, 2724 &nm_txq->ba, (void **)&nm_txq->desc); 2725 if (rc) 2726 return (rc); 2727 2728 nm_txq->pidx = nm_txq->cidx = 0; 2729 nm_txq->sidx = na->num_tx_desc; 2730 nm_txq->nid = idx; 2731 nm_txq->iqidx = iqidx; 2732 nm_txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) | 2733 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(sc->pf)); 2734 2735 snprintf(name, sizeof(name), "%d", idx); 2736 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 2737 NULL, "netmap tx queue"); 2738 children = SYSCTL_CHILDREN(oid); 2739 2740 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 2741 &nm_txq->cntxt_id, 0, "SGE context id of the queue"); 2742 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cidx", 2743 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->cidx, 0, sysctl_uint16, "I", 2744 "consumer index"); 2745 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "pidx", 2746 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->pidx, 0, sysctl_uint16, "I", 2747 "producer index"); 2748 2749 return (rc); 2750 } 2751 2752 static int 2753 free_nm_txq(struct port_info *pi, struct sge_nm_txq *nm_txq) 2754 { 2755 struct adapter *sc = pi->adapter; 2756 2757 free_ring(sc, nm_txq->desc_tag, nm_txq->desc_map, nm_txq->ba, 2758 nm_txq->desc); 2759 2760 return (0); 2761 } 2762 #endif 2763 2764 static int 2765 ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq) 2766 { 2767 int rc, cntxt_id; 2768 struct fw_eq_ctrl_cmd c; 2769 2770 bzero(&c, sizeof(c)); 2771 2772 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | F_FW_CMD_REQUEST | 2773 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_CTRL_CMD_PFN(sc->pf) | 2774 V_FW_EQ_CTRL_CMD_VFN(0)); 2775 c.alloc_to_len16 = htobe32(F_FW_EQ_CTRL_CMD_ALLOC | 2776 F_FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c)); 2777 c.cmpliqid_eqid = htonl(V_FW_EQ_CTRL_CMD_CMPLIQID(eq->iqid)); /* XXX */ 2778 c.physeqid_pkd = htobe32(0); 2779 c.fetchszm_to_iqid = 2780 htobe32(V_FW_EQ_CTRL_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 2781 V_FW_EQ_CTRL_CMD_PCIECHN(eq->tx_chan) | 2782 F_FW_EQ_CTRL_CMD_FETCHRO | V_FW_EQ_CTRL_CMD_IQID(eq->iqid)); 2783 c.dcaen_to_eqsize = 2784 htobe32(V_FW_EQ_CTRL_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 2785 V_FW_EQ_CTRL_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 2786 V_FW_EQ_CTRL_CMD_CIDXFTHRESH(X_CIDXFLUSHTHRESH_32) | 2787 V_FW_EQ_CTRL_CMD_EQSIZE(eq->qsize)); 2788 c.eqaddr = htobe64(eq->ba); 2789 2790 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 2791 if (rc != 0) { 2792 device_printf(sc->dev, 2793 "failed to create control queue %d: %d\n", eq->tx_chan, rc); 2794 return (rc); 2795 } 2796 eq->flags |= EQ_ALLOCATED; 2797 2798 eq->cntxt_id = G_FW_EQ_CTRL_CMD_EQID(be32toh(c.cmpliqid_eqid)); 2799 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 2800 if (cntxt_id >= sc->sge.neq) 2801 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 2802 cntxt_id, sc->sge.neq - 1); 2803 sc->sge.eqmap[cntxt_id] = eq; 2804 2805 return (rc); 2806 } 2807 2808 static int 2809 eth_eq_alloc(struct adapter *sc, struct port_info *pi, struct sge_eq *eq) 2810 { 2811 int rc, cntxt_id; 2812 struct fw_eq_eth_cmd c; 2813 2814 bzero(&c, sizeof(c)); 2815 2816 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST | 2817 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) | 2818 V_FW_EQ_ETH_CMD_VFN(0)); 2819 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC | 2820 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c)); 2821 c.viid_pkd = htobe32(V_FW_EQ_ETH_CMD_VIID(pi->viid)); 2822 c.fetchszm_to_iqid = 2823 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 2824 V_FW_EQ_ETH_CMD_PCIECHN(eq->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO | 2825 V_FW_EQ_ETH_CMD_IQID(eq->iqid)); 2826 c.dcaen_to_eqsize = htobe32(V_FW_EQ_ETH_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 2827 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 2828 V_FW_EQ_ETH_CMD_CIDXFTHRESH(X_CIDXFLUSHTHRESH_32) | 2829 V_FW_EQ_ETH_CMD_EQSIZE(eq->qsize)); 2830 c.eqaddr = htobe64(eq->ba); 2831 2832 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 2833 if (rc != 0) { 2834 device_printf(pi->dev, 2835 "failed to create Ethernet egress queue: %d\n", rc); 2836 return (rc); 2837 } 2838 eq->flags |= EQ_ALLOCATED; 2839 2840 eq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd)); 2841 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 2842 if (cntxt_id >= sc->sge.neq) 2843 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 2844 cntxt_id, sc->sge.neq - 1); 2845 sc->sge.eqmap[cntxt_id] = eq; 2846 2847 return (rc); 2848 } 2849 2850 #ifdef TCP_OFFLOAD 2851 static int 2852 ofld_eq_alloc(struct adapter *sc, struct port_info *pi, struct sge_eq *eq) 2853 { 2854 int rc, cntxt_id; 2855 struct fw_eq_ofld_cmd c; 2856 2857 bzero(&c, sizeof(c)); 2858 2859 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | F_FW_CMD_REQUEST | 2860 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_OFLD_CMD_PFN(sc->pf) | 2861 V_FW_EQ_OFLD_CMD_VFN(0)); 2862 c.alloc_to_len16 = htonl(F_FW_EQ_OFLD_CMD_ALLOC | 2863 F_FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c)); 2864 c.fetchszm_to_iqid = 2865 htonl(V_FW_EQ_OFLD_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 2866 V_FW_EQ_OFLD_CMD_PCIECHN(eq->tx_chan) | 2867 F_FW_EQ_OFLD_CMD_FETCHRO | V_FW_EQ_OFLD_CMD_IQID(eq->iqid)); 2868 c.dcaen_to_eqsize = 2869 htobe32(V_FW_EQ_OFLD_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 2870 V_FW_EQ_OFLD_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 2871 V_FW_EQ_OFLD_CMD_CIDXFTHRESH(X_CIDXFLUSHTHRESH_32) | 2872 V_FW_EQ_OFLD_CMD_EQSIZE(eq->qsize)); 2873 c.eqaddr = htobe64(eq->ba); 2874 2875 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 2876 if (rc != 0) { 2877 device_printf(pi->dev, 2878 "failed to create egress queue for TCP offload: %d\n", rc); 2879 return (rc); 2880 } 2881 eq->flags |= EQ_ALLOCATED; 2882 2883 eq->cntxt_id = G_FW_EQ_OFLD_CMD_EQID(be32toh(c.eqid_pkd)); 2884 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 2885 if (cntxt_id >= sc->sge.neq) 2886 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 2887 cntxt_id, sc->sge.neq - 1); 2888 sc->sge.eqmap[cntxt_id] = eq; 2889 2890 return (rc); 2891 } 2892 #endif 2893 2894 static int 2895 alloc_eq(struct adapter *sc, struct port_info *pi, struct sge_eq *eq) 2896 { 2897 int rc; 2898 size_t len; 2899 2900 mtx_init(&eq->eq_lock, eq->lockname, NULL, MTX_DEF); 2901 2902 len = eq->qsize * EQ_ESIZE; 2903 rc = alloc_ring(sc, len, &eq->desc_tag, &eq->desc_map, 2904 &eq->ba, (void **)&eq->desc); 2905 if (rc) 2906 return (rc); 2907 2908 eq->cap = eq->qsize - spg_len / EQ_ESIZE; 2909 eq->spg = (void *)&eq->desc[eq->cap]; 2910 eq->avail = eq->cap - 1; /* one less to avoid cidx = pidx */ 2911 eq->pidx = eq->cidx = 0; 2912 eq->doorbells = sc->doorbells; 2913 2914 switch (eq->flags & EQ_TYPEMASK) { 2915 case EQ_CTRL: 2916 rc = ctrl_eq_alloc(sc, eq); 2917 break; 2918 2919 case EQ_ETH: 2920 rc = eth_eq_alloc(sc, pi, eq); 2921 break; 2922 2923 #ifdef TCP_OFFLOAD 2924 case EQ_OFLD: 2925 rc = ofld_eq_alloc(sc, pi, eq); 2926 break; 2927 #endif 2928 2929 default: 2930 panic("%s: invalid eq type %d.", __func__, 2931 eq->flags & EQ_TYPEMASK); 2932 } 2933 if (rc != 0) { 2934 device_printf(sc->dev, 2935 "failed to allocate egress queue(%d): %d", 2936 eq->flags & EQ_TYPEMASK, rc); 2937 } 2938 2939 eq->tx_callout.c_cpu = eq->cntxt_id % mp_ncpus; 2940 2941 if (isset(&eq->doorbells, DOORBELL_UDB) || 2942 isset(&eq->doorbells, DOORBELL_UDBWC) || 2943 isset(&eq->doorbells, DOORBELL_WCWR)) { 2944 uint32_t s_qpp = sc->sge.eq_s_qpp; 2945 uint32_t mask = (1 << s_qpp) - 1; 2946 volatile uint8_t *udb; 2947 2948 udb = sc->udbs_base + UDBS_DB_OFFSET; 2949 udb += (eq->cntxt_id >> s_qpp) << PAGE_SHIFT; /* pg offset */ 2950 eq->udb_qid = eq->cntxt_id & mask; /* id in page */ 2951 if (eq->udb_qid > PAGE_SIZE / UDBS_SEG_SIZE) 2952 clrbit(&eq->doorbells, DOORBELL_WCWR); 2953 else { 2954 udb += eq->udb_qid << UDBS_SEG_SHIFT; /* seg offset */ 2955 eq->udb_qid = 0; 2956 } 2957 eq->udb = (volatile void *)udb; 2958 } 2959 2960 return (rc); 2961 } 2962 2963 static int 2964 free_eq(struct adapter *sc, struct sge_eq *eq) 2965 { 2966 int rc; 2967 2968 if (eq->flags & EQ_ALLOCATED) { 2969 switch (eq->flags & EQ_TYPEMASK) { 2970 case EQ_CTRL: 2971 rc = -t4_ctrl_eq_free(sc, sc->mbox, sc->pf, 0, 2972 eq->cntxt_id); 2973 break; 2974 2975 case EQ_ETH: 2976 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0, 2977 eq->cntxt_id); 2978 break; 2979 2980 #ifdef TCP_OFFLOAD 2981 case EQ_OFLD: 2982 rc = -t4_ofld_eq_free(sc, sc->mbox, sc->pf, 0, 2983 eq->cntxt_id); 2984 break; 2985 #endif 2986 2987 default: 2988 panic("%s: invalid eq type %d.", __func__, 2989 eq->flags & EQ_TYPEMASK); 2990 } 2991 if (rc != 0) { 2992 device_printf(sc->dev, 2993 "failed to free egress queue (%d): %d\n", 2994 eq->flags & EQ_TYPEMASK, rc); 2995 return (rc); 2996 } 2997 eq->flags &= ~EQ_ALLOCATED; 2998 } 2999 3000 free_ring(sc, eq->desc_tag, eq->desc_map, eq->ba, eq->desc); 3001 3002 if (mtx_initialized(&eq->eq_lock)) 3003 mtx_destroy(&eq->eq_lock); 3004 3005 bzero(eq, sizeof(*eq)); 3006 return (0); 3007 } 3008 3009 static int 3010 alloc_wrq(struct adapter *sc, struct port_info *pi, struct sge_wrq *wrq, 3011 struct sysctl_oid *oid) 3012 { 3013 int rc; 3014 struct sysctl_ctx_list *ctx = pi ? &pi->ctx : &sc->ctx; 3015 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3016 3017 rc = alloc_eq(sc, pi, &wrq->eq); 3018 if (rc) 3019 return (rc); 3020 3021 wrq->adapter = sc; 3022 STAILQ_INIT(&wrq->wr_list); 3023 3024 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 3025 &wrq->eq.cntxt_id, 0, "SGE context id of the queue"); 3026 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx", 3027 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.cidx, 0, sysctl_uint16, "I", 3028 "consumer index"); 3029 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pidx", 3030 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.pidx, 0, sysctl_uint16, "I", 3031 "producer index"); 3032 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs", CTLFLAG_RD, 3033 &wrq->tx_wrs, "# of work requests"); 3034 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "no_desc", CTLFLAG_RD, 3035 &wrq->no_desc, 0, 3036 "# of times queue ran out of hardware descriptors"); 3037 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "unstalled", CTLFLAG_RD, 3038 &wrq->eq.unstalled, 0, "# of times queue recovered after stall"); 3039 3040 return (rc); 3041 } 3042 3043 static int 3044 free_wrq(struct adapter *sc, struct sge_wrq *wrq) 3045 { 3046 int rc; 3047 3048 rc = free_eq(sc, &wrq->eq); 3049 if (rc) 3050 return (rc); 3051 3052 bzero(wrq, sizeof(*wrq)); 3053 return (0); 3054 } 3055 3056 static int 3057 alloc_txq(struct port_info *pi, struct sge_txq *txq, int idx, 3058 struct sysctl_oid *oid) 3059 { 3060 int rc; 3061 struct adapter *sc = pi->adapter; 3062 struct sge_eq *eq = &txq->eq; 3063 char name[16]; 3064 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3065 3066 rc = alloc_eq(sc, pi, eq); 3067 if (rc) 3068 return (rc); 3069 3070 txq->ifp = pi->ifp; 3071 3072 txq->sdesc = malloc(eq->cap * sizeof(struct tx_sdesc), M_CXGBE, 3073 M_ZERO | M_WAITOK); 3074 txq->br = buf_ring_alloc(eq->qsize, M_CXGBE, M_WAITOK, &eq->eq_lock); 3075 3076 rc = bus_dma_tag_create(sc->dmat, 1, 0, BUS_SPACE_MAXADDR, 3077 BUS_SPACE_MAXADDR, NULL, NULL, 64 * 1024, TX_SGL_SEGS, 3078 BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL, NULL, &txq->tx_tag); 3079 if (rc != 0) { 3080 device_printf(sc->dev, 3081 "failed to create tx DMA tag: %d\n", rc); 3082 return (rc); 3083 } 3084 3085 /* 3086 * We can stuff ~10 frames in an 8-descriptor txpkts WR (8 is the SGE 3087 * limit for any WR). txq->no_dmamap events shouldn't occur if maps is 3088 * sized for the worst case. 3089 */ 3090 rc = t4_alloc_tx_maps(&txq->txmaps, txq->tx_tag, eq->qsize * 10 / 8, 3091 M_WAITOK); 3092 if (rc != 0) { 3093 device_printf(sc->dev, "failed to setup tx DMA maps: %d\n", rc); 3094 return (rc); 3095 } 3096 3097 snprintf(name, sizeof(name), "%d", idx); 3098 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 3099 NULL, "tx queue"); 3100 children = SYSCTL_CHILDREN(oid); 3101 3102 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 3103 &eq->cntxt_id, 0, "SGE context id of the queue"); 3104 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cidx", 3105 CTLTYPE_INT | CTLFLAG_RD, &eq->cidx, 0, sysctl_uint16, "I", 3106 "consumer index"); 3107 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "pidx", 3108 CTLTYPE_INT | CTLFLAG_RD, &eq->pidx, 0, sysctl_uint16, "I", 3109 "producer index"); 3110 3111 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "txcsum", CTLFLAG_RD, 3112 &txq->txcsum, "# of times hardware assisted with checksum"); 3113 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "vlan_insertion", 3114 CTLFLAG_RD, &txq->vlan_insertion, 3115 "# of times hardware inserted 802.1Q tag"); 3116 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "tso_wrs", CTLFLAG_RD, 3117 &txq->tso_wrs, "# of TSO work requests"); 3118 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "imm_wrs", CTLFLAG_RD, 3119 &txq->imm_wrs, "# of work requests with immediate data"); 3120 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "sgl_wrs", CTLFLAG_RD, 3121 &txq->sgl_wrs, "# of work requests with direct SGL"); 3122 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "txpkt_wrs", CTLFLAG_RD, 3123 &txq->txpkt_wrs, "# of txpkt work requests (one pkt/WR)"); 3124 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "txpkts_wrs", CTLFLAG_RD, 3125 &txq->txpkts_wrs, "# of txpkts work requests (multiple pkts/WR)"); 3126 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "txpkts_pkts", CTLFLAG_RD, 3127 &txq->txpkts_pkts, "# of frames tx'd using txpkts work requests"); 3128 3129 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "br_drops", CTLFLAG_RD, 3130 &txq->br->br_drops, "# of drops in the buf_ring for this queue"); 3131 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "no_dmamap", CTLFLAG_RD, 3132 &txq->no_dmamap, 0, "# of times txq ran out of DMA maps"); 3133 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "no_desc", CTLFLAG_RD, 3134 &txq->no_desc, 0, "# of times txq ran out of hardware descriptors"); 3135 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "egr_update", CTLFLAG_RD, 3136 &eq->egr_update, 0, "egress update notifications from the SGE"); 3137 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "unstalled", CTLFLAG_RD, 3138 &eq->unstalled, 0, "# of times txq recovered after stall"); 3139 3140 return (rc); 3141 } 3142 3143 static int 3144 free_txq(struct port_info *pi, struct sge_txq *txq) 3145 { 3146 int rc; 3147 struct adapter *sc = pi->adapter; 3148 struct sge_eq *eq = &txq->eq; 3149 3150 rc = free_eq(sc, eq); 3151 if (rc) 3152 return (rc); 3153 3154 free(txq->sdesc, M_CXGBE); 3155 3156 if (txq->txmaps.maps) 3157 t4_free_tx_maps(&txq->txmaps, txq->tx_tag); 3158 3159 buf_ring_free(txq->br, M_CXGBE); 3160 3161 if (txq->tx_tag) 3162 bus_dma_tag_destroy(txq->tx_tag); 3163 3164 bzero(txq, sizeof(*txq)); 3165 return (0); 3166 } 3167 3168 static void 3169 oneseg_dma_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3170 { 3171 bus_addr_t *ba = arg; 3172 3173 KASSERT(nseg == 1, 3174 ("%s meant for single segment mappings only.", __func__)); 3175 3176 *ba = error ? 0 : segs->ds_addr; 3177 } 3178 3179 static inline bool 3180 is_new_response(const struct sge_iq *iq, struct rsp_ctrl **ctrl) 3181 { 3182 *ctrl = (void *)((uintptr_t)iq->cdesc + 3183 (iq->esize - sizeof(struct rsp_ctrl))); 3184 3185 return (((*ctrl)->u.type_gen >> S_RSPD_GEN) == iq->gen); 3186 } 3187 3188 static inline void 3189 iq_next(struct sge_iq *iq) 3190 { 3191 iq->cdesc = (void *) ((uintptr_t)iq->cdesc + iq->esize); 3192 if (__predict_false(++iq->cidx == iq->qsize - spg_len / iq->esize)) { 3193 iq->cidx = 0; 3194 iq->gen ^= 1; 3195 iq->cdesc = iq->desc; 3196 } 3197 } 3198 3199 #define FL_HW_IDX(x) ((x) >> 3) 3200 static inline void 3201 ring_fl_db(struct adapter *sc, struct sge_fl *fl) 3202 { 3203 int ndesc = fl->pending / 8; 3204 uint32_t v; 3205 3206 if (FL_HW_IDX(fl->pidx) == FL_HW_IDX(fl->cidx)) 3207 ndesc--; /* hold back one credit */ 3208 3209 if (ndesc <= 0) 3210 return; /* nothing to do */ 3211 3212 v = F_DBPRIO | V_QID(fl->cntxt_id) | V_PIDX(ndesc); 3213 if (is_t5(sc)) 3214 v |= F_DBTYPE; 3215 3216 wmb(); 3217 3218 t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL), v); 3219 fl->pending -= ndesc * 8; 3220 } 3221 3222 /* 3223 * Fill up the freelist by upto nbufs and maybe ring its doorbell. 3224 * 3225 * Returns non-zero to indicate that it should be added to the list of starving 3226 * freelists. 3227 */ 3228 static int 3229 refill_fl(struct adapter *sc, struct sge_fl *fl, int nbufs) 3230 { 3231 __be64 *d = &fl->desc[fl->pidx]; 3232 struct fl_sdesc *sd = &fl->sdesc[fl->pidx]; 3233 uintptr_t pa; 3234 caddr_t cl; 3235 struct cluster_layout *cll = &fl->cll_def; /* default layout */ 3236 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx]; 3237 struct cluster_metadata *clm; 3238 3239 FL_LOCK_ASSERT_OWNED(fl); 3240 3241 if (nbufs > fl->needed) 3242 nbufs = fl->needed; 3243 nbufs -= (fl->pidx + nbufs) % 8; 3244 3245 while (nbufs--) { 3246 3247 if (sd->cl != NULL) { 3248 3249 if (sd->nmbuf == 0) { 3250 /* 3251 * Fast recycle without involving any atomics on 3252 * the cluster's metadata (if the cluster has 3253 * metadata). This happens when all frames 3254 * received in the cluster were small enough to 3255 * fit within a single mbuf each. 3256 */ 3257 fl->cl_fast_recycled++; 3258 goto recycled_fast; 3259 } 3260 3261 /* 3262 * Cluster is guaranteed to have metadata. Clusters 3263 * without metadata always take the fast recycle path 3264 * when they're recycled. 3265 */ 3266 clm = cl_metadata(sc, fl, &sd->cll, sd->cl); 3267 MPASS(clm != NULL); 3268 3269 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) { 3270 fl->cl_recycled++; 3271 goto recycled; 3272 } 3273 sd->cl = NULL; /* gave up my reference */ 3274 } 3275 MPASS(sd->cl == NULL); 3276 alloc: 3277 cl = uma_zalloc(swz->zone, M_NOWAIT); 3278 if (__predict_false(cl == NULL)) { 3279 if (cll == &fl->cll_alt || fl->cll_alt.zidx == -1 || 3280 fl->cll_def.zidx == fl->cll_alt.zidx) 3281 break; 3282 3283 /* fall back to the safe zone */ 3284 cll = &fl->cll_alt; 3285 swz = &sc->sge.sw_zone_info[cll->zidx]; 3286 goto alloc; 3287 } 3288 fl->cl_allocated++; 3289 3290 pa = pmap_kextract((vm_offset_t)cl); 3291 pa += cll->region1; 3292 sd->cl = cl; 3293 sd->cll = *cll; 3294 *d = htobe64(pa | cll->hwidx); 3295 clm = cl_metadata(sc, fl, cll, cl); 3296 if (clm != NULL) { 3297 recycled: 3298 #ifdef INVARIANTS 3299 clm->sd = sd; 3300 #endif 3301 clm->refcount = 1; 3302 } 3303 sd->nmbuf = 0; 3304 recycled_fast: 3305 fl->pending++; 3306 fl->needed--; 3307 d++; 3308 sd++; 3309 if (__predict_false(++fl->pidx == fl->cap)) { 3310 fl->pidx = 0; 3311 sd = fl->sdesc; 3312 d = fl->desc; 3313 } 3314 } 3315 3316 if (fl->pending >= 8) 3317 ring_fl_db(sc, fl); 3318 3319 return (FL_RUNNING_LOW(fl) && !(fl->flags & FL_STARVING)); 3320 } 3321 3322 /* 3323 * Attempt to refill all starving freelists. 3324 */ 3325 static void 3326 refill_sfl(void *arg) 3327 { 3328 struct adapter *sc = arg; 3329 struct sge_fl *fl, *fl_temp; 3330 3331 mtx_lock(&sc->sfl_lock); 3332 TAILQ_FOREACH_SAFE(fl, &sc->sfl, link, fl_temp) { 3333 FL_LOCK(fl); 3334 refill_fl(sc, fl, 64); 3335 if (FL_NOT_RUNNING_LOW(fl) || fl->flags & FL_DOOMED) { 3336 TAILQ_REMOVE(&sc->sfl, fl, link); 3337 fl->flags &= ~FL_STARVING; 3338 } 3339 FL_UNLOCK(fl); 3340 } 3341 3342 if (!TAILQ_EMPTY(&sc->sfl)) 3343 callout_schedule(&sc->sfl_callout, hz / 5); 3344 mtx_unlock(&sc->sfl_lock); 3345 } 3346 3347 static int 3348 alloc_fl_sdesc(struct sge_fl *fl) 3349 { 3350 3351 fl->sdesc = malloc(fl->cap * sizeof(struct fl_sdesc), M_CXGBE, 3352 M_ZERO | M_WAITOK); 3353 3354 return (0); 3355 } 3356 3357 static void 3358 free_fl_sdesc(struct adapter *sc, struct sge_fl *fl) 3359 { 3360 struct fl_sdesc *sd; 3361 struct cluster_metadata *clm; 3362 struct cluster_layout *cll; 3363 int i; 3364 3365 sd = fl->sdesc; 3366 for (i = 0; i < fl->cap; i++, sd++) { 3367 if (sd->cl == NULL) 3368 continue; 3369 3370 cll = &sd->cll; 3371 clm = cl_metadata(sc, fl, cll, sd->cl); 3372 if (sd->nmbuf == 0 || 3373 (clm && atomic_fetchadd_int(&clm->refcount, -1) == 1)) { 3374 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl); 3375 } 3376 sd->cl = NULL; 3377 } 3378 3379 free(fl->sdesc, M_CXGBE); 3380 fl->sdesc = NULL; 3381 } 3382 3383 int 3384 t4_alloc_tx_maps(struct tx_maps *txmaps, bus_dma_tag_t tx_tag, int count, 3385 int flags) 3386 { 3387 struct tx_map *txm; 3388 int i, rc; 3389 3390 txmaps->map_total = txmaps->map_avail = count; 3391 txmaps->map_cidx = txmaps->map_pidx = 0; 3392 3393 txmaps->maps = malloc(count * sizeof(struct tx_map), M_CXGBE, 3394 M_ZERO | flags); 3395 3396 txm = txmaps->maps; 3397 for (i = 0; i < count; i++, txm++) { 3398 rc = bus_dmamap_create(tx_tag, 0, &txm->map); 3399 if (rc != 0) 3400 goto failed; 3401 } 3402 3403 return (0); 3404 failed: 3405 while (--i >= 0) { 3406 txm--; 3407 bus_dmamap_destroy(tx_tag, txm->map); 3408 } 3409 KASSERT(txm == txmaps->maps, ("%s: EDOOFUS", __func__)); 3410 3411 free(txmaps->maps, M_CXGBE); 3412 txmaps->maps = NULL; 3413 3414 return (rc); 3415 } 3416 3417 void 3418 t4_free_tx_maps(struct tx_maps *txmaps, bus_dma_tag_t tx_tag) 3419 { 3420 struct tx_map *txm; 3421 int i; 3422 3423 txm = txmaps->maps; 3424 for (i = 0; i < txmaps->map_total; i++, txm++) { 3425 3426 if (txm->m) { 3427 bus_dmamap_unload(tx_tag, txm->map); 3428 m_freem(txm->m); 3429 txm->m = NULL; 3430 } 3431 3432 bus_dmamap_destroy(tx_tag, txm->map); 3433 } 3434 3435 free(txmaps->maps, M_CXGBE); 3436 txmaps->maps = NULL; 3437 } 3438 3439 /* 3440 * We'll do immediate data tx for non-TSO, but only when not coalescing. We're 3441 * willing to use upto 2 hardware descriptors which means a maximum of 96 bytes 3442 * of immediate data. 3443 */ 3444 #define IMM_LEN ( \ 3445 2 * EQ_ESIZE \ 3446 - sizeof(struct fw_eth_tx_pkt_wr) \ 3447 - sizeof(struct cpl_tx_pkt_core)) 3448 3449 /* 3450 * Returns non-zero on failure, no need to cleanup anything in that case. 3451 * 3452 * Note 1: We always try to defrag the mbuf if required and return EFBIG only 3453 * if the resulting chain still won't fit in a tx descriptor. 3454 * 3455 * Note 2: We'll pullup the mbuf chain if TSO is requested and the first mbuf 3456 * does not have the TCP header in it. 3457 */ 3458 static int 3459 get_pkt_sgl(struct sge_txq *txq, struct mbuf **fp, struct sgl *sgl, 3460 int sgl_only) 3461 { 3462 struct mbuf *m = *fp; 3463 struct tx_maps *txmaps; 3464 struct tx_map *txm; 3465 int rc, defragged = 0, n; 3466 3467 TXQ_LOCK_ASSERT_OWNED(txq); 3468 3469 if (m->m_pkthdr.tso_segsz) 3470 sgl_only = 1; /* Do not allow immediate data with LSO */ 3471 3472 start: sgl->nsegs = 0; 3473 3474 if (m->m_pkthdr.len <= IMM_LEN && !sgl_only) 3475 return (0); /* nsegs = 0 tells caller to use imm. tx */ 3476 3477 txmaps = &txq->txmaps; 3478 if (txmaps->map_avail == 0) { 3479 txq->no_dmamap++; 3480 return (ENOMEM); 3481 } 3482 txm = &txmaps->maps[txmaps->map_pidx]; 3483 3484 if (m->m_pkthdr.tso_segsz && m->m_len < 50) { 3485 *fp = m_pullup(m, 50); 3486 m = *fp; 3487 if (m == NULL) 3488 return (ENOBUFS); 3489 } 3490 3491 rc = bus_dmamap_load_mbuf_sg(txq->tx_tag, txm->map, m, sgl->seg, 3492 &sgl->nsegs, BUS_DMA_NOWAIT); 3493 if (rc == EFBIG && defragged == 0) { 3494 m = m_defrag(m, M_NOWAIT); 3495 if (m == NULL) 3496 return (EFBIG); 3497 3498 defragged = 1; 3499 *fp = m; 3500 goto start; 3501 } 3502 if (rc != 0) 3503 return (rc); 3504 3505 txm->m = m; 3506 txmaps->map_avail--; 3507 if (++txmaps->map_pidx == txmaps->map_total) 3508 txmaps->map_pidx = 0; 3509 3510 KASSERT(sgl->nsegs > 0 && sgl->nsegs <= TX_SGL_SEGS, 3511 ("%s: bad DMA mapping (%d segments)", __func__, sgl->nsegs)); 3512 3513 /* 3514 * Store the # of flits required to hold this frame's SGL in nflits. An 3515 * SGL has a (ULPTX header + len0, addr0) tuple optionally followed by 3516 * multiple (len0 + len1, addr0, addr1) tuples. If addr1 is not used 3517 * then len1 must be set to 0. 3518 */ 3519 n = sgl->nsegs - 1; 3520 sgl->nflits = (3 * n) / 2 + (n & 1) + 2; 3521 3522 return (0); 3523 } 3524 3525 3526 /* 3527 * Releases all the txq resources used up in the specified sgl. 3528 */ 3529 static int 3530 free_pkt_sgl(struct sge_txq *txq, struct sgl *sgl) 3531 { 3532 struct tx_maps *txmaps; 3533 struct tx_map *txm; 3534 3535 TXQ_LOCK_ASSERT_OWNED(txq); 3536 3537 if (sgl->nsegs == 0) 3538 return (0); /* didn't use any map */ 3539 3540 txmaps = &txq->txmaps; 3541 3542 /* 1 pkt uses exactly 1 map, back it out */ 3543 3544 txmaps->map_avail++; 3545 if (txmaps->map_pidx > 0) 3546 txmaps->map_pidx--; 3547 else 3548 txmaps->map_pidx = txmaps->map_total - 1; 3549 3550 txm = &txmaps->maps[txmaps->map_pidx]; 3551 bus_dmamap_unload(txq->tx_tag, txm->map); 3552 txm->m = NULL; 3553 3554 return (0); 3555 } 3556 3557 static int 3558 write_txpkt_wr(struct port_info *pi, struct sge_txq *txq, struct mbuf *m, 3559 struct sgl *sgl) 3560 { 3561 struct sge_eq *eq = &txq->eq; 3562 struct fw_eth_tx_pkt_wr *wr; 3563 struct cpl_tx_pkt_core *cpl; 3564 uint32_t ctrl; /* used in many unrelated places */ 3565 uint64_t ctrl1; 3566 int nflits, ndesc, pktlen; 3567 struct tx_sdesc *txsd; 3568 caddr_t dst; 3569 3570 TXQ_LOCK_ASSERT_OWNED(txq); 3571 3572 pktlen = m->m_pkthdr.len; 3573 3574 /* 3575 * Do we have enough flits to send this frame out? 3576 */ 3577 ctrl = sizeof(struct cpl_tx_pkt_core); 3578 if (m->m_pkthdr.tso_segsz) { 3579 nflits = TXPKT_LSO_WR_HDR; 3580 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 3581 } else 3582 nflits = TXPKT_WR_HDR; 3583 if (sgl->nsegs > 0) 3584 nflits += sgl->nflits; 3585 else { 3586 nflits += howmany(pktlen, 8); 3587 ctrl += pktlen; 3588 } 3589 ndesc = howmany(nflits, 8); 3590 if (ndesc > eq->avail) 3591 return (ENOMEM); 3592 3593 /* Firmware work request header */ 3594 wr = (void *)&eq->desc[eq->pidx]; 3595 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_WR) | 3596 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl)); 3597 ctrl = V_FW_WR_LEN16(howmany(nflits, 2)); 3598 if (eq->avail == ndesc) { 3599 if (!(eq->flags & EQ_CRFLUSHED)) { 3600 ctrl |= F_FW_WR_EQUEQ | F_FW_WR_EQUIQ; 3601 eq->flags |= EQ_CRFLUSHED; 3602 } 3603 eq->flags |= EQ_STALLED; 3604 } 3605 3606 wr->equiq_to_len16 = htobe32(ctrl); 3607 wr->r3 = 0; 3608 3609 if (m->m_pkthdr.tso_segsz) { 3610 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1); 3611 struct ether_header *eh; 3612 void *l3hdr; 3613 #if defined(INET) || defined(INET6) 3614 struct tcphdr *tcp; 3615 #endif 3616 uint16_t eh_type; 3617 3618 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE | 3619 F_LSO_LAST_SLICE; 3620 3621 eh = mtod(m, struct ether_header *); 3622 eh_type = ntohs(eh->ether_type); 3623 if (eh_type == ETHERTYPE_VLAN) { 3624 struct ether_vlan_header *evh = (void *)eh; 3625 3626 ctrl |= V_LSO_ETHHDR_LEN(1); 3627 l3hdr = evh + 1; 3628 eh_type = ntohs(evh->evl_proto); 3629 } else 3630 l3hdr = eh + 1; 3631 3632 switch (eh_type) { 3633 #ifdef INET6 3634 case ETHERTYPE_IPV6: 3635 { 3636 struct ip6_hdr *ip6 = l3hdr; 3637 3638 /* 3639 * XXX-BZ For now we do not pretend to support 3640 * IPv6 extension headers. 3641 */ 3642 KASSERT(ip6->ip6_nxt == IPPROTO_TCP, ("%s: CSUM_TSO " 3643 "with ip6_nxt != TCP: %u", __func__, ip6->ip6_nxt)); 3644 tcp = (struct tcphdr *)(ip6 + 1); 3645 ctrl |= F_LSO_IPV6; 3646 ctrl |= V_LSO_IPHDR_LEN(sizeof(*ip6) >> 2) | 3647 V_LSO_TCPHDR_LEN(tcp->th_off); 3648 break; 3649 } 3650 #endif 3651 #ifdef INET 3652 case ETHERTYPE_IP: 3653 { 3654 struct ip *ip = l3hdr; 3655 3656 tcp = (void *)((uintptr_t)ip + ip->ip_hl * 4); 3657 ctrl |= V_LSO_IPHDR_LEN(ip->ip_hl) | 3658 V_LSO_TCPHDR_LEN(tcp->th_off); 3659 break; 3660 } 3661 #endif 3662 default: 3663 panic("%s: CSUM_TSO but no supported IP version " 3664 "(0x%04x)", __func__, eh_type); 3665 } 3666 3667 lso->lso_ctrl = htobe32(ctrl); 3668 lso->ipid_ofst = htobe16(0); 3669 lso->mss = htobe16(m->m_pkthdr.tso_segsz); 3670 lso->seqno_offset = htobe32(0); 3671 lso->len = htobe32(pktlen); 3672 3673 cpl = (void *)(lso + 1); 3674 3675 txq->tso_wrs++; 3676 } else 3677 cpl = (void *)(wr + 1); 3678 3679 /* Checksum offload */ 3680 ctrl1 = 0; 3681 if (!(m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TSO))) 3682 ctrl1 |= F_TXPKT_IPCSUM_DIS; 3683 if (!(m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_UDP_IPV6 | 3684 CSUM_TCP_IPV6 | CSUM_TSO))) 3685 ctrl1 |= F_TXPKT_L4CSUM_DIS; 3686 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | 3687 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO)) 3688 txq->txcsum++; /* some hardware assistance provided */ 3689 3690 /* VLAN tag insertion */ 3691 if (m->m_flags & M_VLANTAG) { 3692 ctrl1 |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(m->m_pkthdr.ether_vtag); 3693 txq->vlan_insertion++; 3694 } 3695 3696 /* CPL header */ 3697 cpl->ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) | 3698 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(pi->adapter->pf)); 3699 cpl->pack = 0; 3700 cpl->len = htobe16(pktlen); 3701 cpl->ctrl1 = htobe64(ctrl1); 3702 3703 /* Software descriptor */ 3704 txsd = &txq->sdesc[eq->pidx]; 3705 txsd->desc_used = ndesc; 3706 3707 eq->pending += ndesc; 3708 eq->avail -= ndesc; 3709 eq->pidx += ndesc; 3710 if (eq->pidx >= eq->cap) 3711 eq->pidx -= eq->cap; 3712 3713 /* SGL */ 3714 dst = (void *)(cpl + 1); 3715 if (sgl->nsegs > 0) { 3716 txsd->credits = 1; 3717 txq->sgl_wrs++; 3718 write_sgl_to_txd(eq, sgl, &dst); 3719 } else { 3720 txsd->credits = 0; 3721 txq->imm_wrs++; 3722 for (; m; m = m->m_next) { 3723 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len); 3724 #ifdef INVARIANTS 3725 pktlen -= m->m_len; 3726 #endif 3727 } 3728 #ifdef INVARIANTS 3729 KASSERT(pktlen == 0, ("%s: %d bytes left.", __func__, pktlen)); 3730 #endif 3731 3732 } 3733 3734 txq->txpkt_wrs++; 3735 return (0); 3736 } 3737 3738 /* 3739 * Returns 0 to indicate that m has been accepted into a coalesced tx work 3740 * request. It has either been folded into txpkts or txpkts was flushed and m 3741 * has started a new coalesced work request (as the first frame in a fresh 3742 * txpkts). 3743 * 3744 * Returns non-zero to indicate a failure - caller is responsible for 3745 * transmitting m, if there was anything in txpkts it has been flushed. 3746 */ 3747 static int 3748 add_to_txpkts(struct port_info *pi, struct sge_txq *txq, struct txpkts *txpkts, 3749 struct mbuf *m, struct sgl *sgl) 3750 { 3751 struct sge_eq *eq = &txq->eq; 3752 int can_coalesce; 3753 struct tx_sdesc *txsd; 3754 int flits; 3755 3756 TXQ_LOCK_ASSERT_OWNED(txq); 3757 3758 KASSERT(sgl->nsegs, ("%s: can't coalesce imm data", __func__)); 3759 3760 if (txpkts->npkt > 0) { 3761 flits = TXPKTS_PKT_HDR + sgl->nflits; 3762 can_coalesce = m->m_pkthdr.tso_segsz == 0 && 3763 txpkts->nflits + flits <= TX_WR_FLITS && 3764 txpkts->nflits + flits <= eq->avail * 8 && 3765 txpkts->plen + m->m_pkthdr.len < 65536; 3766 3767 if (can_coalesce) { 3768 txpkts->npkt++; 3769 txpkts->nflits += flits; 3770 txpkts->plen += m->m_pkthdr.len; 3771 3772 txsd = &txq->sdesc[eq->pidx]; 3773 txsd->credits++; 3774 3775 return (0); 3776 } 3777 3778 /* 3779 * Couldn't coalesce m into txpkts. The first order of business 3780 * is to send txpkts on its way. Then we'll revisit m. 3781 */ 3782 write_txpkts_wr(txq, txpkts); 3783 } 3784 3785 /* 3786 * Check if we can start a new coalesced tx work request with m as 3787 * the first packet in it. 3788 */ 3789 3790 KASSERT(txpkts->npkt == 0, ("%s: txpkts not empty", __func__)); 3791 3792 flits = TXPKTS_WR_HDR + sgl->nflits; 3793 can_coalesce = m->m_pkthdr.tso_segsz == 0 && 3794 flits <= eq->avail * 8 && flits <= TX_WR_FLITS; 3795 3796 if (can_coalesce == 0) 3797 return (EINVAL); 3798 3799 /* 3800 * Start a fresh coalesced tx WR with m as the first frame in it. 3801 */ 3802 txpkts->npkt = 1; 3803 txpkts->nflits = flits; 3804 txpkts->flitp = &eq->desc[eq->pidx].flit[2]; 3805 txpkts->plen = m->m_pkthdr.len; 3806 3807 txsd = &txq->sdesc[eq->pidx]; 3808 txsd->credits = 1; 3809 3810 return (0); 3811 } 3812 3813 /* 3814 * Note that write_txpkts_wr can never run out of hardware descriptors (but 3815 * write_txpkt_wr can). add_to_txpkts ensures that a frame is accepted for 3816 * coalescing only if sufficient hardware descriptors are available. 3817 */ 3818 static void 3819 write_txpkts_wr(struct sge_txq *txq, struct txpkts *txpkts) 3820 { 3821 struct sge_eq *eq = &txq->eq; 3822 struct fw_eth_tx_pkts_wr *wr; 3823 struct tx_sdesc *txsd; 3824 uint32_t ctrl; 3825 int ndesc; 3826 3827 TXQ_LOCK_ASSERT_OWNED(txq); 3828 3829 ndesc = howmany(txpkts->nflits, 8); 3830 3831 wr = (void *)&eq->desc[eq->pidx]; 3832 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR)); 3833 ctrl = V_FW_WR_LEN16(howmany(txpkts->nflits, 2)); 3834 if (eq->avail == ndesc) { 3835 if (!(eq->flags & EQ_CRFLUSHED)) { 3836 ctrl |= F_FW_WR_EQUEQ | F_FW_WR_EQUIQ; 3837 eq->flags |= EQ_CRFLUSHED; 3838 } 3839 eq->flags |= EQ_STALLED; 3840 } 3841 wr->equiq_to_len16 = htobe32(ctrl); 3842 wr->plen = htobe16(txpkts->plen); 3843 wr->npkt = txpkts->npkt; 3844 wr->r3 = wr->type = 0; 3845 3846 /* Everything else already written */ 3847 3848 txsd = &txq->sdesc[eq->pidx]; 3849 txsd->desc_used = ndesc; 3850 3851 KASSERT(eq->avail >= ndesc, ("%s: out of descriptors", __func__)); 3852 3853 eq->pending += ndesc; 3854 eq->avail -= ndesc; 3855 eq->pidx += ndesc; 3856 if (eq->pidx >= eq->cap) 3857 eq->pidx -= eq->cap; 3858 3859 txq->txpkts_pkts += txpkts->npkt; 3860 txq->txpkts_wrs++; 3861 txpkts->npkt = 0; /* emptied */ 3862 } 3863 3864 static inline void 3865 write_ulp_cpl_sgl(struct port_info *pi, struct sge_txq *txq, 3866 struct txpkts *txpkts, struct mbuf *m, struct sgl *sgl) 3867 { 3868 struct ulp_txpkt *ulpmc; 3869 struct ulptx_idata *ulpsc; 3870 struct cpl_tx_pkt_core *cpl; 3871 struct sge_eq *eq = &txq->eq; 3872 uintptr_t flitp, start, end; 3873 uint64_t ctrl; 3874 caddr_t dst; 3875 3876 KASSERT(txpkts->npkt > 0, ("%s: txpkts is empty", __func__)); 3877 3878 start = (uintptr_t)eq->desc; 3879 end = (uintptr_t)eq->spg; 3880 3881 /* Checksum offload */ 3882 ctrl = 0; 3883 if (!(m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TSO))) 3884 ctrl |= F_TXPKT_IPCSUM_DIS; 3885 if (!(m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_UDP_IPV6 | 3886 CSUM_TCP_IPV6 | CSUM_TSO))) 3887 ctrl |= F_TXPKT_L4CSUM_DIS; 3888 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | 3889 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO)) 3890 txq->txcsum++; /* some hardware assistance provided */ 3891 3892 /* VLAN tag insertion */ 3893 if (m->m_flags & M_VLANTAG) { 3894 ctrl |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(m->m_pkthdr.ether_vtag); 3895 txq->vlan_insertion++; 3896 } 3897 3898 /* 3899 * The previous packet's SGL must have ended at a 16 byte boundary (this 3900 * is required by the firmware/hardware). It follows that flitp cannot 3901 * wrap around between the ULPTX master command and ULPTX subcommand (8 3902 * bytes each), and that it can not wrap around in the middle of the 3903 * cpl_tx_pkt_core either. 3904 */ 3905 flitp = (uintptr_t)txpkts->flitp; 3906 KASSERT((flitp & 0xf) == 0, 3907 ("%s: last SGL did not end at 16 byte boundary: %p", 3908 __func__, txpkts->flitp)); 3909 3910 /* ULP master command */ 3911 ulpmc = (void *)flitp; 3912 ulpmc->cmd_dest = htonl(V_ULPTX_CMD(ULP_TX_PKT) | V_ULP_TXPKT_DEST(0) | 3913 V_ULP_TXPKT_FID(eq->iqid)); 3914 ulpmc->len = htonl(howmany(sizeof(*ulpmc) + sizeof(*ulpsc) + 3915 sizeof(*cpl) + 8 * sgl->nflits, 16)); 3916 3917 /* ULP subcommand */ 3918 ulpsc = (void *)(ulpmc + 1); 3919 ulpsc->cmd_more = htobe32(V_ULPTX_CMD((u32)ULP_TX_SC_IMM) | 3920 F_ULP_TX_SC_MORE); 3921 ulpsc->len = htobe32(sizeof(struct cpl_tx_pkt_core)); 3922 3923 flitp += sizeof(*ulpmc) + sizeof(*ulpsc); 3924 if (flitp == end) 3925 flitp = start; 3926 3927 /* CPL_TX_PKT */ 3928 cpl = (void *)flitp; 3929 cpl->ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) | 3930 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(pi->adapter->pf)); 3931 cpl->pack = 0; 3932 cpl->len = htobe16(m->m_pkthdr.len); 3933 cpl->ctrl1 = htobe64(ctrl); 3934 3935 flitp += sizeof(*cpl); 3936 if (flitp == end) 3937 flitp = start; 3938 3939 /* SGL for this frame */ 3940 dst = (caddr_t)flitp; 3941 txpkts->nflits += write_sgl_to_txd(eq, sgl, &dst); 3942 txpkts->flitp = (void *)dst; 3943 3944 KASSERT(((uintptr_t)dst & 0xf) == 0, 3945 ("%s: SGL ends at %p (not a 16 byte boundary)", __func__, dst)); 3946 } 3947 3948 /* 3949 * If the SGL ends on an address that is not 16 byte aligned, this function will 3950 * add a 0 filled flit at the end. It returns 1 in that case. 3951 */ 3952 static int 3953 write_sgl_to_txd(struct sge_eq *eq, struct sgl *sgl, caddr_t *to) 3954 { 3955 __be64 *flitp, *end; 3956 struct ulptx_sgl *usgl; 3957 bus_dma_segment_t *seg; 3958 int i, padded; 3959 3960 KASSERT(sgl->nsegs > 0 && sgl->nflits > 0, 3961 ("%s: bad SGL - nsegs=%d, nflits=%d", 3962 __func__, sgl->nsegs, sgl->nflits)); 3963 3964 KASSERT(((uintptr_t)(*to) & 0xf) == 0, 3965 ("%s: SGL must start at a 16 byte boundary: %p", __func__, *to)); 3966 3967 flitp = (__be64 *)(*to); 3968 end = flitp + sgl->nflits; 3969 seg = &sgl->seg[0]; 3970 usgl = (void *)flitp; 3971 3972 /* 3973 * We start at a 16 byte boundary somewhere inside the tx descriptor 3974 * ring, so we're at least 16 bytes away from the status page. There is 3975 * no chance of a wrap around in the middle of usgl (which is 16 bytes). 3976 */ 3977 3978 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 3979 V_ULPTX_NSGE(sgl->nsegs)); 3980 usgl->len0 = htobe32(seg->ds_len); 3981 usgl->addr0 = htobe64(seg->ds_addr); 3982 seg++; 3983 3984 if ((uintptr_t)end <= (uintptr_t)eq->spg) { 3985 3986 /* Won't wrap around at all */ 3987 3988 for (i = 0; i < sgl->nsegs - 1; i++, seg++) { 3989 usgl->sge[i / 2].len[i & 1] = htobe32(seg->ds_len); 3990 usgl->sge[i / 2].addr[i & 1] = htobe64(seg->ds_addr); 3991 } 3992 if (i & 1) 3993 usgl->sge[i / 2].len[1] = htobe32(0); 3994 } else { 3995 3996 /* Will wrap somewhere in the rest of the SGL */ 3997 3998 /* 2 flits already written, write the rest flit by flit */ 3999 flitp = (void *)(usgl + 1); 4000 for (i = 0; i < sgl->nflits - 2; i++) { 4001 if ((uintptr_t)flitp == (uintptr_t)eq->spg) 4002 flitp = (void *)eq->desc; 4003 *flitp++ = get_flit(seg, sgl->nsegs - 1, i); 4004 } 4005 end = flitp; 4006 } 4007 4008 if ((uintptr_t)end & 0xf) { 4009 *(uint64_t *)end = 0; 4010 end++; 4011 padded = 1; 4012 } else 4013 padded = 0; 4014 4015 if ((uintptr_t)end == (uintptr_t)eq->spg) 4016 *to = (void *)eq->desc; 4017 else 4018 *to = (void *)end; 4019 4020 return (padded); 4021 } 4022 4023 static inline void 4024 copy_to_txd(struct sge_eq *eq, caddr_t from, caddr_t *to, int len) 4025 { 4026 if (__predict_true((uintptr_t)(*to) + len <= (uintptr_t)eq->spg)) { 4027 bcopy(from, *to, len); 4028 (*to) += len; 4029 } else { 4030 int portion = (uintptr_t)eq->spg - (uintptr_t)(*to); 4031 4032 bcopy(from, *to, portion); 4033 from += portion; 4034 portion = len - portion; /* remaining */ 4035 bcopy(from, (void *)eq->desc, portion); 4036 (*to) = (caddr_t)eq->desc + portion; 4037 } 4038 } 4039 4040 static inline void 4041 ring_eq_db(struct adapter *sc, struct sge_eq *eq) 4042 { 4043 u_int db, pending; 4044 4045 db = eq->doorbells; 4046 pending = eq->pending; 4047 if (pending > 1) 4048 clrbit(&db, DOORBELL_WCWR); 4049 eq->pending = 0; 4050 wmb(); 4051 4052 switch (ffs(db) - 1) { 4053 case DOORBELL_UDB: 4054 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(pending)); 4055 return; 4056 4057 case DOORBELL_WCWR: { 4058 volatile uint64_t *dst, *src; 4059 int i; 4060 4061 /* 4062 * Queues whose 128B doorbell segment fits in the page do not 4063 * use relative qid (udb_qid is always 0). Only queues with 4064 * doorbell segments can do WCWR. 4065 */ 4066 KASSERT(eq->udb_qid == 0 && pending == 1, 4067 ("%s: inappropriate doorbell (0x%x, %d, %d) for eq %p", 4068 __func__, eq->doorbells, pending, eq->pidx, eq)); 4069 4070 dst = (volatile void *)((uintptr_t)eq->udb + UDBS_WR_OFFSET - 4071 UDBS_DB_OFFSET); 4072 i = eq->pidx ? eq->pidx - 1 : eq->cap - 1; 4073 src = (void *)&eq->desc[i]; 4074 while (src != (void *)&eq->desc[i + 1]) 4075 *dst++ = *src++; 4076 wmb(); 4077 return; 4078 } 4079 4080 case DOORBELL_UDBWC: 4081 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(pending)); 4082 wmb(); 4083 return; 4084 4085 case DOORBELL_KDB: 4086 t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL), 4087 V_QID(eq->cntxt_id) | V_PIDX(pending)); 4088 return; 4089 } 4090 } 4091 4092 static inline int 4093 reclaimable(struct sge_eq *eq) 4094 { 4095 unsigned int cidx; 4096 4097 cidx = eq->spg->cidx; /* stable snapshot */ 4098 cidx = be16toh(cidx); 4099 4100 if (cidx >= eq->cidx) 4101 return (cidx - eq->cidx); 4102 else 4103 return (cidx + eq->cap - eq->cidx); 4104 } 4105 4106 /* 4107 * There are "can_reclaim" tx descriptors ready to be reclaimed. Reclaim as 4108 * many as possible but stop when there are around "n" mbufs to free. 4109 * 4110 * The actual number reclaimed is provided as the return value. 4111 */ 4112 static int 4113 reclaim_tx_descs(struct sge_txq *txq, int can_reclaim, int n) 4114 { 4115 struct tx_sdesc *txsd; 4116 struct tx_maps *txmaps; 4117 struct tx_map *txm; 4118 unsigned int reclaimed, maps; 4119 struct sge_eq *eq = &txq->eq; 4120 4121 TXQ_LOCK_ASSERT_OWNED(txq); 4122 4123 if (can_reclaim == 0) 4124 can_reclaim = reclaimable(eq); 4125 4126 maps = reclaimed = 0; 4127 while (can_reclaim && maps < n) { 4128 int ndesc; 4129 4130 txsd = &txq->sdesc[eq->cidx]; 4131 ndesc = txsd->desc_used; 4132 4133 /* Firmware doesn't return "partial" credits. */ 4134 KASSERT(can_reclaim >= ndesc, 4135 ("%s: unexpected number of credits: %d, %d", 4136 __func__, can_reclaim, ndesc)); 4137 4138 maps += txsd->credits; 4139 4140 reclaimed += ndesc; 4141 can_reclaim -= ndesc; 4142 4143 eq->cidx += ndesc; 4144 if (__predict_false(eq->cidx >= eq->cap)) 4145 eq->cidx -= eq->cap; 4146 } 4147 4148 txmaps = &txq->txmaps; 4149 txm = &txmaps->maps[txmaps->map_cidx]; 4150 if (maps) 4151 prefetch(txm->m); 4152 4153 eq->avail += reclaimed; 4154 KASSERT(eq->avail < eq->cap, /* avail tops out at (cap - 1) */ 4155 ("%s: too many descriptors available", __func__)); 4156 4157 txmaps->map_avail += maps; 4158 KASSERT(txmaps->map_avail <= txmaps->map_total, 4159 ("%s: too many maps available", __func__)); 4160 4161 while (maps--) { 4162 struct tx_map *next; 4163 4164 next = txm + 1; 4165 if (__predict_false(txmaps->map_cidx + 1 == txmaps->map_total)) 4166 next = txmaps->maps; 4167 prefetch(next->m); 4168 4169 bus_dmamap_unload(txq->tx_tag, txm->map); 4170 m_freem(txm->m); 4171 txm->m = NULL; 4172 4173 txm = next; 4174 if (__predict_false(++txmaps->map_cidx == txmaps->map_total)) 4175 txmaps->map_cidx = 0; 4176 } 4177 4178 return (reclaimed); 4179 } 4180 4181 static void 4182 write_eqflush_wr(struct sge_eq *eq) 4183 { 4184 struct fw_eq_flush_wr *wr; 4185 4186 EQ_LOCK_ASSERT_OWNED(eq); 4187 KASSERT(eq->avail > 0, ("%s: no descriptors left.", __func__)); 4188 KASSERT(!(eq->flags & EQ_CRFLUSHED), ("%s: flushed already", __func__)); 4189 4190 wr = (void *)&eq->desc[eq->pidx]; 4191 bzero(wr, sizeof(*wr)); 4192 wr->opcode = FW_EQ_FLUSH_WR; 4193 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(sizeof(*wr) / 16) | 4194 F_FW_WR_EQUEQ | F_FW_WR_EQUIQ); 4195 4196 eq->flags |= (EQ_CRFLUSHED | EQ_STALLED); 4197 eq->pending++; 4198 eq->avail--; 4199 if (++eq->pidx == eq->cap) 4200 eq->pidx = 0; 4201 } 4202 4203 static __be64 4204 get_flit(bus_dma_segment_t *sgl, int nsegs, int idx) 4205 { 4206 int i = (idx / 3) * 2; 4207 4208 switch (idx % 3) { 4209 case 0: { 4210 __be64 rc; 4211 4212 rc = htobe32(sgl[i].ds_len); 4213 if (i + 1 < nsegs) 4214 rc |= (uint64_t)htobe32(sgl[i + 1].ds_len) << 32; 4215 4216 return (rc); 4217 } 4218 case 1: 4219 return htobe64(sgl[i].ds_addr); 4220 case 2: 4221 return htobe64(sgl[i + 1].ds_addr); 4222 } 4223 4224 return (0); 4225 } 4226 4227 static void 4228 find_best_refill_source(struct adapter *sc, struct sge_fl *fl, int maxp) 4229 { 4230 int8_t zidx, hwidx, idx; 4231 uint16_t region1, region3; 4232 int spare, spare_needed, n; 4233 struct sw_zone_info *swz; 4234 struct hw_buf_info *hwb, *hwb_list = &sc->sge.hw_buf_info[0]; 4235 4236 /* 4237 * Buffer Packing: Look for PAGE_SIZE or larger zone which has a bufsize 4238 * large enough for the max payload and cluster metadata. Otherwise 4239 * settle for the largest bufsize that leaves enough room in the cluster 4240 * for metadata. 4241 * 4242 * Without buffer packing: Look for the smallest zone which has a 4243 * bufsize large enough for the max payload. Settle for the largest 4244 * bufsize available if there's nothing big enough for max payload. 4245 */ 4246 spare_needed = fl->flags & FL_BUF_PACKING ? CL_METADATA_SIZE : 0; 4247 swz = &sc->sge.sw_zone_info[0]; 4248 hwidx = -1; 4249 for (zidx = 0; zidx < SW_ZONE_SIZES; zidx++, swz++) { 4250 if (swz->size > largest_rx_cluster) { 4251 if (__predict_true(hwidx != -1)) 4252 break; 4253 4254 /* 4255 * This is a misconfiguration. largest_rx_cluster is 4256 * preventing us from finding a refill source. See 4257 * dev.t5nex.<n>.buffer_sizes to figure out why. 4258 */ 4259 device_printf(sc->dev, "largest_rx_cluster=%u leaves no" 4260 " refill source for fl %p (dma %u). Ignored.\n", 4261 largest_rx_cluster, fl, maxp); 4262 } 4263 for (idx = swz->head_hwidx; idx != -1; idx = hwb->next) { 4264 hwb = &hwb_list[idx]; 4265 spare = swz->size - hwb->size; 4266 if (spare < spare_needed) 4267 continue; 4268 4269 hwidx = idx; /* best option so far */ 4270 if (hwb->size >= maxp) { 4271 4272 if ((fl->flags & FL_BUF_PACKING) == 0) 4273 goto done; /* stop looking (not packing) */ 4274 4275 if (swz->size >= safest_rx_cluster) 4276 goto done; /* stop looking (packing) */ 4277 } 4278 break; /* keep looking, next zone */ 4279 } 4280 } 4281 done: 4282 /* A usable hwidx has been located. */ 4283 MPASS(hwidx != -1); 4284 hwb = &hwb_list[hwidx]; 4285 zidx = hwb->zidx; 4286 swz = &sc->sge.sw_zone_info[zidx]; 4287 region1 = 0; 4288 region3 = swz->size - hwb->size; 4289 4290 /* 4291 * Stay within this zone and see if there is a better match when mbuf 4292 * inlining is allowed. Remember that the hwidx's are sorted in 4293 * decreasing order of size (so in increasing order of spare area). 4294 */ 4295 for (idx = hwidx; idx != -1; idx = hwb->next) { 4296 hwb = &hwb_list[idx]; 4297 spare = swz->size - hwb->size; 4298 4299 if (allow_mbufs_in_cluster == 0 || hwb->size < maxp) 4300 break; 4301 if (spare < CL_METADATA_SIZE + MSIZE) 4302 continue; 4303 n = (spare - CL_METADATA_SIZE) / MSIZE; 4304 if (n > howmany(hwb->size, maxp)) 4305 break; 4306 4307 hwidx = idx; 4308 if (fl->flags & FL_BUF_PACKING) { 4309 region1 = n * MSIZE; 4310 region3 = spare - region1; 4311 } else { 4312 region1 = MSIZE; 4313 region3 = spare - region1; 4314 break; 4315 } 4316 } 4317 4318 KASSERT(zidx >= 0 && zidx < SW_ZONE_SIZES, 4319 ("%s: bad zone %d for fl %p, maxp %d", __func__, zidx, fl, maxp)); 4320 KASSERT(hwidx >= 0 && hwidx <= SGE_FLBUF_SIZES, 4321 ("%s: bad hwidx %d for fl %p, maxp %d", __func__, hwidx, fl, maxp)); 4322 KASSERT(region1 + sc->sge.hw_buf_info[hwidx].size + region3 == 4323 sc->sge.sw_zone_info[zidx].size, 4324 ("%s: bad buffer layout for fl %p, maxp %d. " 4325 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp, 4326 sc->sge.sw_zone_info[zidx].size, region1, 4327 sc->sge.hw_buf_info[hwidx].size, region3)); 4328 if (fl->flags & FL_BUF_PACKING || region1 > 0) { 4329 KASSERT(region3 >= CL_METADATA_SIZE, 4330 ("%s: no room for metadata. fl %p, maxp %d; " 4331 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp, 4332 sc->sge.sw_zone_info[zidx].size, region1, 4333 sc->sge.hw_buf_info[hwidx].size, region3)); 4334 KASSERT(region1 % MSIZE == 0, 4335 ("%s: bad mbuf region for fl %p, maxp %d. " 4336 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp, 4337 sc->sge.sw_zone_info[zidx].size, region1, 4338 sc->sge.hw_buf_info[hwidx].size, region3)); 4339 } 4340 4341 fl->cll_def.zidx = zidx; 4342 fl->cll_def.hwidx = hwidx; 4343 fl->cll_def.region1 = region1; 4344 fl->cll_def.region3 = region3; 4345 } 4346 4347 static void 4348 find_safe_refill_source(struct adapter *sc, struct sge_fl *fl) 4349 { 4350 struct sge *s = &sc->sge; 4351 struct hw_buf_info *hwb; 4352 struct sw_zone_info *swz; 4353 int spare; 4354 int8_t hwidx; 4355 4356 if (fl->flags & FL_BUF_PACKING) 4357 hwidx = s->safe_hwidx2; /* with room for metadata */ 4358 else if (allow_mbufs_in_cluster && s->safe_hwidx2 != -1) { 4359 hwidx = s->safe_hwidx2; 4360 hwb = &s->hw_buf_info[hwidx]; 4361 swz = &s->sw_zone_info[hwb->zidx]; 4362 spare = swz->size - hwb->size; 4363 4364 /* no good if there isn't room for an mbuf as well */ 4365 if (spare < CL_METADATA_SIZE + MSIZE) 4366 hwidx = s->safe_hwidx1; 4367 } else 4368 hwidx = s->safe_hwidx1; 4369 4370 if (hwidx == -1) { 4371 /* No fallback source */ 4372 fl->cll_alt.hwidx = -1; 4373 fl->cll_alt.zidx = -1; 4374 4375 return; 4376 } 4377 4378 hwb = &s->hw_buf_info[hwidx]; 4379 swz = &s->sw_zone_info[hwb->zidx]; 4380 spare = swz->size - hwb->size; 4381 fl->cll_alt.hwidx = hwidx; 4382 fl->cll_alt.zidx = hwb->zidx; 4383 if (allow_mbufs_in_cluster) 4384 fl->cll_alt.region1 = ((spare - CL_METADATA_SIZE) / MSIZE) * MSIZE; 4385 else 4386 fl->cll_alt.region1 = 0; 4387 fl->cll_alt.region3 = spare - fl->cll_alt.region1; 4388 } 4389 4390 static void 4391 add_fl_to_sfl(struct adapter *sc, struct sge_fl *fl) 4392 { 4393 mtx_lock(&sc->sfl_lock); 4394 FL_LOCK(fl); 4395 if ((fl->flags & FL_DOOMED) == 0) { 4396 fl->flags |= FL_STARVING; 4397 TAILQ_INSERT_TAIL(&sc->sfl, fl, link); 4398 callout_reset(&sc->sfl_callout, hz / 5, refill_sfl, sc); 4399 } 4400 FL_UNLOCK(fl); 4401 mtx_unlock(&sc->sfl_lock); 4402 } 4403 4404 static int 4405 handle_sge_egr_update(struct sge_iq *iq, const struct rss_header *rss, 4406 struct mbuf *m) 4407 { 4408 const struct cpl_sge_egr_update *cpl = (const void *)(rss + 1); 4409 unsigned int qid = G_EGR_QID(ntohl(cpl->opcode_qid)); 4410 struct adapter *sc = iq->adapter; 4411 struct sge *s = &sc->sge; 4412 struct sge_eq *eq; 4413 4414 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 4415 rss->opcode)); 4416 4417 eq = s->eqmap[qid - s->eq_start]; 4418 EQ_LOCK(eq); 4419 KASSERT(eq->flags & EQ_CRFLUSHED, 4420 ("%s: unsolicited egress update", __func__)); 4421 eq->flags &= ~EQ_CRFLUSHED; 4422 eq->egr_update++; 4423 4424 if (__predict_false(eq->flags & EQ_DOOMED)) 4425 wakeup_one(eq); 4426 else if (eq->flags & EQ_STALLED && can_resume_tx(eq)) 4427 taskqueue_enqueue(sc->tq[eq->tx_chan], &eq->tx_task); 4428 EQ_UNLOCK(eq); 4429 4430 return (0); 4431 } 4432 4433 /* handle_fw_msg works for both fw4_msg and fw6_msg because this is valid */ 4434 CTASSERT(offsetof(struct cpl_fw4_msg, data) == \ 4435 offsetof(struct cpl_fw6_msg, data)); 4436 4437 static int 4438 handle_fw_msg(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 4439 { 4440 struct adapter *sc = iq->adapter; 4441 const struct cpl_fw6_msg *cpl = (const void *)(rss + 1); 4442 4443 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 4444 rss->opcode)); 4445 4446 if (cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL) { 4447 const struct rss_header *rss2; 4448 4449 rss2 = (const struct rss_header *)&cpl->data[0]; 4450 return (sc->cpl_handler[rss2->opcode](iq, rss2, m)); 4451 } 4452 4453 return (sc->fw_msg_handler[cpl->type](sc, &cpl->data[0])); 4454 } 4455 4456 static int 4457 sysctl_uint16(SYSCTL_HANDLER_ARGS) 4458 { 4459 uint16_t *id = arg1; 4460 int i = *id; 4461 4462 return sysctl_handle_int(oidp, &i, 0, req); 4463 } 4464 4465 static int 4466 sysctl_bufsizes(SYSCTL_HANDLER_ARGS) 4467 { 4468 struct sge *s = arg1; 4469 struct hw_buf_info *hwb = &s->hw_buf_info[0]; 4470 struct sw_zone_info *swz = &s->sw_zone_info[0]; 4471 int i, rc; 4472 struct sbuf sb; 4473 char c; 4474 4475 sbuf_new(&sb, NULL, 32, SBUF_AUTOEXTEND); 4476 for (i = 0; i < SGE_FLBUF_SIZES; i++, hwb++) { 4477 if (hwb->zidx >= 0 && swz[hwb->zidx].size <= largest_rx_cluster) 4478 c = '*'; 4479 else 4480 c = '\0'; 4481 4482 sbuf_printf(&sb, "%u%c ", hwb->size, c); 4483 } 4484 sbuf_trim(&sb); 4485 sbuf_finish(&sb); 4486 rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req); 4487 sbuf_delete(&sb); 4488 return (rc); 4489 } 4490