1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 Chelsio Communications, Inc. 5 * All rights reserved. 6 * Written by: Navdeep Parhar <np@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include "opt_inet.h" 34 #include "opt_inet6.h" 35 #include "opt_kern_tls.h" 36 #include "opt_ratelimit.h" 37 38 #include <sys/types.h> 39 #include <sys/eventhandler.h> 40 #include <sys/mbuf.h> 41 #include <sys/socket.h> 42 #include <sys/kernel.h> 43 #include <sys/ktls.h> 44 #include <sys/malloc.h> 45 #include <sys/queue.h> 46 #include <sys/sbuf.h> 47 #include <sys/taskqueue.h> 48 #include <sys/time.h> 49 #include <sys/sglist.h> 50 #include <sys/sysctl.h> 51 #include <sys/smp.h> 52 #include <sys/socketvar.h> 53 #include <sys/counter.h> 54 #include <net/bpf.h> 55 #include <net/ethernet.h> 56 #include <net/if.h> 57 #include <net/if_vlan_var.h> 58 #include <net/if_vxlan.h> 59 #include <netinet/in.h> 60 #include <netinet/ip.h> 61 #include <netinet/ip6.h> 62 #include <netinet/tcp.h> 63 #include <netinet/udp.h> 64 #include <machine/in_cksum.h> 65 #include <machine/md_var.h> 66 #include <vm/vm.h> 67 #include <vm/pmap.h> 68 #ifdef DEV_NETMAP 69 #include <machine/bus.h> 70 #include <sys/selinfo.h> 71 #include <net/if_var.h> 72 #include <net/netmap.h> 73 #include <dev/netmap/netmap_kern.h> 74 #endif 75 76 #include "common/common.h" 77 #include "common/t4_regs.h" 78 #include "common/t4_regs_values.h" 79 #include "common/t4_msg.h" 80 #include "t4_l2t.h" 81 #include "t4_mp_ring.h" 82 83 #ifdef T4_PKT_TIMESTAMP 84 #define RX_COPY_THRESHOLD (MINCLSIZE - 8) 85 #else 86 #define RX_COPY_THRESHOLD MINCLSIZE 87 #endif 88 89 /* Internal mbuf flags stored in PH_loc.eight[1]. */ 90 #define MC_NOMAP 0x01 91 #define MC_RAW_WR 0x02 92 #define MC_TLS 0x04 93 94 /* 95 * Ethernet frames are DMA'd at this byte offset into the freelist buffer. 96 * 0-7 are valid values. 97 */ 98 static int fl_pktshift = 0; 99 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pktshift, CTLFLAG_RDTUN, &fl_pktshift, 0, 100 "payload DMA offset in rx buffer (bytes)"); 101 102 /* 103 * Pad ethernet payload up to this boundary. 104 * -1: driver should figure out a good value. 105 * 0: disable padding. 106 * Any power of 2 from 32 to 4096 (both inclusive) is also a valid value. 107 */ 108 int fl_pad = -1; 109 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pad, CTLFLAG_RDTUN, &fl_pad, 0, 110 "payload pad boundary (bytes)"); 111 112 /* 113 * Status page length. 114 * -1: driver should figure out a good value. 115 * 64 or 128 are the only other valid values. 116 */ 117 static int spg_len = -1; 118 SYSCTL_INT(_hw_cxgbe, OID_AUTO, spg_len, CTLFLAG_RDTUN, &spg_len, 0, 119 "status page size (bytes)"); 120 121 /* 122 * Congestion drops. 123 * -1: no congestion feedback (not recommended). 124 * 0: backpressure the channel instead of dropping packets right away. 125 * 1: no backpressure, drop packets for the congested queue immediately. 126 */ 127 static int cong_drop = 0; 128 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cong_drop, CTLFLAG_RDTUN, &cong_drop, 0, 129 "Congestion control for RX queues (0 = backpressure, 1 = drop"); 130 131 /* 132 * Deliver multiple frames in the same free list buffer if they fit. 133 * -1: let the driver decide whether to enable buffer packing or not. 134 * 0: disable buffer packing. 135 * 1: enable buffer packing. 136 */ 137 static int buffer_packing = -1; 138 SYSCTL_INT(_hw_cxgbe, OID_AUTO, buffer_packing, CTLFLAG_RDTUN, &buffer_packing, 139 0, "Enable buffer packing"); 140 141 /* 142 * Start next frame in a packed buffer at this boundary. 143 * -1: driver should figure out a good value. 144 * T4: driver will ignore this and use the same value as fl_pad above. 145 * T5: 16, or a power of 2 from 64 to 4096 (both inclusive) is a valid value. 146 */ 147 static int fl_pack = -1; 148 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pack, CTLFLAG_RDTUN, &fl_pack, 0, 149 "payload pack boundary (bytes)"); 150 151 /* 152 * Largest rx cluster size that the driver is allowed to allocate. 153 */ 154 static int largest_rx_cluster = MJUM16BYTES; 155 SYSCTL_INT(_hw_cxgbe, OID_AUTO, largest_rx_cluster, CTLFLAG_RDTUN, 156 &largest_rx_cluster, 0, "Largest rx cluster (bytes)"); 157 158 /* 159 * Size of cluster allocation that's most likely to succeed. The driver will 160 * fall back to this size if it fails to allocate clusters larger than this. 161 */ 162 static int safest_rx_cluster = PAGE_SIZE; 163 SYSCTL_INT(_hw_cxgbe, OID_AUTO, safest_rx_cluster, CTLFLAG_RDTUN, 164 &safest_rx_cluster, 0, "Safe rx cluster (bytes)"); 165 166 #ifdef RATELIMIT 167 /* 168 * Knob to control TCP timestamp rewriting, and the granularity of the tick used 169 * for rewriting. -1 and 0-3 are all valid values. 170 * -1: hardware should leave the TCP timestamps alone. 171 * 0: 1ms 172 * 1: 100us 173 * 2: 10us 174 * 3: 1us 175 */ 176 static int tsclk = -1; 177 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tsclk, CTLFLAG_RDTUN, &tsclk, 0, 178 "Control TCP timestamp rewriting when using pacing"); 179 180 static int eo_max_backlog = 1024 * 1024; 181 SYSCTL_INT(_hw_cxgbe, OID_AUTO, eo_max_backlog, CTLFLAG_RDTUN, &eo_max_backlog, 182 0, "Maximum backlog of ratelimited data per flow"); 183 #endif 184 185 /* 186 * The interrupt holdoff timers are multiplied by this value on T6+. 187 * 1 and 3-17 (both inclusive) are legal values. 188 */ 189 static int tscale = 1; 190 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tscale, CTLFLAG_RDTUN, &tscale, 0, 191 "Interrupt holdoff timer scale on T6+"); 192 193 /* 194 * Number of LRO entries in the lro_ctrl structure per rx queue. 195 */ 196 static int lro_entries = TCP_LRO_ENTRIES; 197 SYSCTL_INT(_hw_cxgbe, OID_AUTO, lro_entries, CTLFLAG_RDTUN, &lro_entries, 0, 198 "Number of LRO entries per RX queue"); 199 200 /* 201 * This enables presorting of frames before they're fed into tcp_lro_rx. 202 */ 203 static int lro_mbufs = 0; 204 SYSCTL_INT(_hw_cxgbe, OID_AUTO, lro_mbufs, CTLFLAG_RDTUN, &lro_mbufs, 0, 205 "Enable presorting of LRO frames"); 206 207 static counter_u64_t pullups; 208 SYSCTL_COUNTER_U64(_hw_cxgbe, OID_AUTO, pullups, CTLFLAG_RD, &pullups, 209 "Number of mbuf pullups performed"); 210 211 static counter_u64_t defrags; 212 SYSCTL_COUNTER_U64(_hw_cxgbe, OID_AUTO, defrags, CTLFLAG_RD, &defrags, 213 "Number of mbuf defrags performed"); 214 215 216 static int service_iq(struct sge_iq *, int); 217 static int service_iq_fl(struct sge_iq *, int); 218 static struct mbuf *get_fl_payload(struct adapter *, struct sge_fl *, uint32_t); 219 static int eth_rx(struct adapter *, struct sge_rxq *, const struct iq_desc *, 220 u_int); 221 static inline void init_iq(struct sge_iq *, struct adapter *, int, int, int); 222 static inline void init_fl(struct adapter *, struct sge_fl *, int, int, char *); 223 static inline void init_eq(struct adapter *, struct sge_eq *, int, int, uint8_t, 224 uint16_t, char *); 225 static int alloc_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *, 226 int, int); 227 static int free_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *); 228 static void add_iq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *, 229 struct sge_iq *); 230 static void add_fl_sysctls(struct adapter *, struct sysctl_ctx_list *, 231 struct sysctl_oid *, struct sge_fl *); 232 static int alloc_fwq(struct adapter *); 233 static int free_fwq(struct adapter *); 234 static int alloc_ctrlq(struct adapter *, struct sge_wrq *, int, 235 struct sysctl_oid *); 236 static int alloc_rxq(struct vi_info *, struct sge_rxq *, int, int, 237 struct sysctl_oid *); 238 static int free_rxq(struct vi_info *, struct sge_rxq *); 239 #ifdef TCP_OFFLOAD 240 static int alloc_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *, int, int, 241 struct sysctl_oid *); 242 static int free_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *); 243 #endif 244 static int ctrl_eq_alloc(struct adapter *, struct sge_eq *); 245 static int eth_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *); 246 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 247 static int ofld_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *); 248 #endif 249 static int alloc_eq(struct adapter *, struct vi_info *, struct sge_eq *); 250 static int free_eq(struct adapter *, struct sge_eq *); 251 static int alloc_wrq(struct adapter *, struct vi_info *, struct sge_wrq *, 252 struct sysctl_oid *); 253 static int free_wrq(struct adapter *, struct sge_wrq *); 254 static int alloc_txq(struct vi_info *, struct sge_txq *, int, 255 struct sysctl_oid *); 256 static int free_txq(struct vi_info *, struct sge_txq *); 257 static void oneseg_dma_callback(void *, bus_dma_segment_t *, int, int); 258 static inline void ring_fl_db(struct adapter *, struct sge_fl *); 259 static int refill_fl(struct adapter *, struct sge_fl *, int); 260 static void refill_sfl(void *); 261 static int alloc_fl_sdesc(struct sge_fl *); 262 static void free_fl_sdesc(struct adapter *, struct sge_fl *); 263 static int find_refill_source(struct adapter *, int, bool); 264 static void add_fl_to_sfl(struct adapter *, struct sge_fl *); 265 266 static inline void get_pkt_gl(struct mbuf *, struct sglist *); 267 static inline u_int txpkt_len16(u_int, const u_int); 268 static inline u_int txpkt_vm_len16(u_int, const u_int); 269 static inline void calculate_mbuf_len16(struct mbuf *, bool); 270 static inline u_int txpkts0_len16(u_int); 271 static inline u_int txpkts1_len16(void); 272 static u_int write_raw_wr(struct sge_txq *, void *, struct mbuf *, u_int); 273 static u_int write_txpkt_wr(struct adapter *, struct sge_txq *, struct mbuf *, 274 u_int); 275 static u_int write_txpkt_vm_wr(struct adapter *, struct sge_txq *, 276 struct mbuf *); 277 static int add_to_txpkts_vf(struct adapter *, struct sge_txq *, struct mbuf *, 278 int, bool *); 279 static int add_to_txpkts_pf(struct adapter *, struct sge_txq *, struct mbuf *, 280 int, bool *); 281 static u_int write_txpkts_wr(struct adapter *, struct sge_txq *); 282 static u_int write_txpkts_vm_wr(struct adapter *, struct sge_txq *); 283 static void write_gl_to_txd(struct sge_txq *, struct mbuf *, caddr_t *, int); 284 static inline void copy_to_txd(struct sge_eq *, caddr_t, caddr_t *, int); 285 static inline void ring_eq_db(struct adapter *, struct sge_eq *, u_int); 286 static inline uint16_t read_hw_cidx(struct sge_eq *); 287 static inline u_int reclaimable_tx_desc(struct sge_eq *); 288 static inline u_int total_available_tx_desc(struct sge_eq *); 289 static u_int reclaim_tx_descs(struct sge_txq *, u_int); 290 static void tx_reclaim(void *, int); 291 static __be64 get_flit(struct sglist_seg *, int, int); 292 static int handle_sge_egr_update(struct sge_iq *, const struct rss_header *, 293 struct mbuf *); 294 static int handle_fw_msg(struct sge_iq *, const struct rss_header *, 295 struct mbuf *); 296 static int t4_handle_wrerr_rpl(struct adapter *, const __be64 *); 297 static void wrq_tx_drain(void *, int); 298 static void drain_wrq_wr_list(struct adapter *, struct sge_wrq *); 299 300 static int sysctl_bufsizes(SYSCTL_HANDLER_ARGS); 301 #ifdef RATELIMIT 302 static inline u_int txpkt_eo_len16(u_int, u_int, u_int); 303 static int ethofld_fw4_ack(struct sge_iq *, const struct rss_header *, 304 struct mbuf *); 305 #endif 306 307 static counter_u64_t extfree_refs; 308 static counter_u64_t extfree_rels; 309 310 an_handler_t t4_an_handler; 311 fw_msg_handler_t t4_fw_msg_handler[NUM_FW6_TYPES]; 312 cpl_handler_t t4_cpl_handler[NUM_CPL_CMDS]; 313 cpl_handler_t set_tcb_rpl_handlers[NUM_CPL_COOKIES]; 314 cpl_handler_t l2t_write_rpl_handlers[NUM_CPL_COOKIES]; 315 cpl_handler_t act_open_rpl_handlers[NUM_CPL_COOKIES]; 316 cpl_handler_t abort_rpl_rss_handlers[NUM_CPL_COOKIES]; 317 cpl_handler_t fw4_ack_handlers[NUM_CPL_COOKIES]; 318 319 void 320 t4_register_an_handler(an_handler_t h) 321 { 322 uintptr_t *loc; 323 324 MPASS(h == NULL || t4_an_handler == NULL); 325 326 loc = (uintptr_t *)&t4_an_handler; 327 atomic_store_rel_ptr(loc, (uintptr_t)h); 328 } 329 330 void 331 t4_register_fw_msg_handler(int type, fw_msg_handler_t h) 332 { 333 uintptr_t *loc; 334 335 MPASS(type < nitems(t4_fw_msg_handler)); 336 MPASS(h == NULL || t4_fw_msg_handler[type] == NULL); 337 /* 338 * These are dispatched by the handler for FW{4|6}_CPL_MSG using the CPL 339 * handler dispatch table. Reject any attempt to install a handler for 340 * this subtype. 341 */ 342 MPASS(type != FW_TYPE_RSSCPL); 343 MPASS(type != FW6_TYPE_RSSCPL); 344 345 loc = (uintptr_t *)&t4_fw_msg_handler[type]; 346 atomic_store_rel_ptr(loc, (uintptr_t)h); 347 } 348 349 void 350 t4_register_cpl_handler(int opcode, cpl_handler_t h) 351 { 352 uintptr_t *loc; 353 354 MPASS(opcode < nitems(t4_cpl_handler)); 355 MPASS(h == NULL || t4_cpl_handler[opcode] == NULL); 356 357 loc = (uintptr_t *)&t4_cpl_handler[opcode]; 358 atomic_store_rel_ptr(loc, (uintptr_t)h); 359 } 360 361 static int 362 set_tcb_rpl_handler(struct sge_iq *iq, const struct rss_header *rss, 363 struct mbuf *m) 364 { 365 const struct cpl_set_tcb_rpl *cpl = (const void *)(rss + 1); 366 u_int tid; 367 int cookie; 368 369 MPASS(m == NULL); 370 371 tid = GET_TID(cpl); 372 if (is_hpftid(iq->adapter, tid) || is_ftid(iq->adapter, tid)) { 373 /* 374 * The return code for filter-write is put in the CPL cookie so 375 * we have to rely on the hardware tid (is_ftid) to determine 376 * that this is a response to a filter. 377 */ 378 cookie = CPL_COOKIE_FILTER; 379 } else { 380 cookie = G_COOKIE(cpl->cookie); 381 } 382 MPASS(cookie > CPL_COOKIE_RESERVED); 383 MPASS(cookie < nitems(set_tcb_rpl_handlers)); 384 385 return (set_tcb_rpl_handlers[cookie](iq, rss, m)); 386 } 387 388 static int 389 l2t_write_rpl_handler(struct sge_iq *iq, const struct rss_header *rss, 390 struct mbuf *m) 391 { 392 const struct cpl_l2t_write_rpl *rpl = (const void *)(rss + 1); 393 unsigned int cookie; 394 395 MPASS(m == NULL); 396 397 cookie = GET_TID(rpl) & F_SYNC_WR ? CPL_COOKIE_TOM : CPL_COOKIE_FILTER; 398 return (l2t_write_rpl_handlers[cookie](iq, rss, m)); 399 } 400 401 static int 402 act_open_rpl_handler(struct sge_iq *iq, const struct rss_header *rss, 403 struct mbuf *m) 404 { 405 const struct cpl_act_open_rpl *cpl = (const void *)(rss + 1); 406 u_int cookie = G_TID_COOKIE(G_AOPEN_ATID(be32toh(cpl->atid_status))); 407 408 MPASS(m == NULL); 409 MPASS(cookie != CPL_COOKIE_RESERVED); 410 411 return (act_open_rpl_handlers[cookie](iq, rss, m)); 412 } 413 414 static int 415 abort_rpl_rss_handler(struct sge_iq *iq, const struct rss_header *rss, 416 struct mbuf *m) 417 { 418 struct adapter *sc = iq->adapter; 419 u_int cookie; 420 421 MPASS(m == NULL); 422 if (is_hashfilter(sc)) 423 cookie = CPL_COOKIE_HASHFILTER; 424 else 425 cookie = CPL_COOKIE_TOM; 426 427 return (abort_rpl_rss_handlers[cookie](iq, rss, m)); 428 } 429 430 static int 431 fw4_ack_handler(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 432 { 433 struct adapter *sc = iq->adapter; 434 const struct cpl_fw4_ack *cpl = (const void *)(rss + 1); 435 unsigned int tid = G_CPL_FW4_ACK_FLOWID(be32toh(OPCODE_TID(cpl))); 436 u_int cookie; 437 438 MPASS(m == NULL); 439 if (is_etid(sc, tid)) 440 cookie = CPL_COOKIE_ETHOFLD; 441 else 442 cookie = CPL_COOKIE_TOM; 443 444 return (fw4_ack_handlers[cookie](iq, rss, m)); 445 } 446 447 static void 448 t4_init_shared_cpl_handlers(void) 449 { 450 451 t4_register_cpl_handler(CPL_SET_TCB_RPL, set_tcb_rpl_handler); 452 t4_register_cpl_handler(CPL_L2T_WRITE_RPL, l2t_write_rpl_handler); 453 t4_register_cpl_handler(CPL_ACT_OPEN_RPL, act_open_rpl_handler); 454 t4_register_cpl_handler(CPL_ABORT_RPL_RSS, abort_rpl_rss_handler); 455 t4_register_cpl_handler(CPL_FW4_ACK, fw4_ack_handler); 456 } 457 458 void 459 t4_register_shared_cpl_handler(int opcode, cpl_handler_t h, int cookie) 460 { 461 uintptr_t *loc; 462 463 MPASS(opcode < nitems(t4_cpl_handler)); 464 MPASS(cookie > CPL_COOKIE_RESERVED); 465 MPASS(cookie < NUM_CPL_COOKIES); 466 MPASS(t4_cpl_handler[opcode] != NULL); 467 468 switch (opcode) { 469 case CPL_SET_TCB_RPL: 470 loc = (uintptr_t *)&set_tcb_rpl_handlers[cookie]; 471 break; 472 case CPL_L2T_WRITE_RPL: 473 loc = (uintptr_t *)&l2t_write_rpl_handlers[cookie]; 474 break; 475 case CPL_ACT_OPEN_RPL: 476 loc = (uintptr_t *)&act_open_rpl_handlers[cookie]; 477 break; 478 case CPL_ABORT_RPL_RSS: 479 loc = (uintptr_t *)&abort_rpl_rss_handlers[cookie]; 480 break; 481 case CPL_FW4_ACK: 482 loc = (uintptr_t *)&fw4_ack_handlers[cookie]; 483 break; 484 default: 485 MPASS(0); 486 return; 487 } 488 MPASS(h == NULL || *loc == (uintptr_t)NULL); 489 atomic_store_rel_ptr(loc, (uintptr_t)h); 490 } 491 492 /* 493 * Called on MOD_LOAD. Validates and calculates the SGE tunables. 494 */ 495 void 496 t4_sge_modload(void) 497 { 498 499 if (fl_pktshift < 0 || fl_pktshift > 7) { 500 printf("Invalid hw.cxgbe.fl_pktshift value (%d)," 501 " using 0 instead.\n", fl_pktshift); 502 fl_pktshift = 0; 503 } 504 505 if (spg_len != 64 && spg_len != 128) { 506 int len; 507 508 #if defined(__i386__) || defined(__amd64__) 509 len = cpu_clflush_line_size > 64 ? 128 : 64; 510 #else 511 len = 64; 512 #endif 513 if (spg_len != -1) { 514 printf("Invalid hw.cxgbe.spg_len value (%d)," 515 " using %d instead.\n", spg_len, len); 516 } 517 spg_len = len; 518 } 519 520 if (cong_drop < -1 || cong_drop > 1) { 521 printf("Invalid hw.cxgbe.cong_drop value (%d)," 522 " using 0 instead.\n", cong_drop); 523 cong_drop = 0; 524 } 525 526 if (tscale != 1 && (tscale < 3 || tscale > 17)) { 527 printf("Invalid hw.cxgbe.tscale value (%d)," 528 " using 1 instead.\n", tscale); 529 tscale = 1; 530 } 531 532 if (largest_rx_cluster != MCLBYTES && 533 #if MJUMPAGESIZE != MCLBYTES 534 largest_rx_cluster != MJUMPAGESIZE && 535 #endif 536 largest_rx_cluster != MJUM9BYTES && 537 largest_rx_cluster != MJUM16BYTES) { 538 printf("Invalid hw.cxgbe.largest_rx_cluster value (%d)," 539 " using %d instead.\n", largest_rx_cluster, MJUM16BYTES); 540 largest_rx_cluster = MJUM16BYTES; 541 } 542 543 if (safest_rx_cluster != MCLBYTES && 544 #if MJUMPAGESIZE != MCLBYTES 545 safest_rx_cluster != MJUMPAGESIZE && 546 #endif 547 safest_rx_cluster != MJUM9BYTES && 548 safest_rx_cluster != MJUM16BYTES) { 549 printf("Invalid hw.cxgbe.safest_rx_cluster value (%d)," 550 " using %d instead.\n", safest_rx_cluster, MJUMPAGESIZE); 551 safest_rx_cluster = MJUMPAGESIZE; 552 } 553 554 extfree_refs = counter_u64_alloc(M_WAITOK); 555 extfree_rels = counter_u64_alloc(M_WAITOK); 556 pullups = counter_u64_alloc(M_WAITOK); 557 defrags = counter_u64_alloc(M_WAITOK); 558 counter_u64_zero(extfree_refs); 559 counter_u64_zero(extfree_rels); 560 counter_u64_zero(pullups); 561 counter_u64_zero(defrags); 562 563 t4_init_shared_cpl_handlers(); 564 t4_register_cpl_handler(CPL_FW4_MSG, handle_fw_msg); 565 t4_register_cpl_handler(CPL_FW6_MSG, handle_fw_msg); 566 t4_register_cpl_handler(CPL_SGE_EGR_UPDATE, handle_sge_egr_update); 567 #ifdef RATELIMIT 568 t4_register_shared_cpl_handler(CPL_FW4_ACK, ethofld_fw4_ack, 569 CPL_COOKIE_ETHOFLD); 570 #endif 571 t4_register_fw_msg_handler(FW6_TYPE_CMD_RPL, t4_handle_fw_rpl); 572 t4_register_fw_msg_handler(FW6_TYPE_WRERR_RPL, t4_handle_wrerr_rpl); 573 } 574 575 void 576 t4_sge_modunload(void) 577 { 578 579 counter_u64_free(extfree_refs); 580 counter_u64_free(extfree_rels); 581 counter_u64_free(pullups); 582 counter_u64_free(defrags); 583 } 584 585 uint64_t 586 t4_sge_extfree_refs(void) 587 { 588 uint64_t refs, rels; 589 590 rels = counter_u64_fetch(extfree_rels); 591 refs = counter_u64_fetch(extfree_refs); 592 593 return (refs - rels); 594 } 595 596 /* max 4096 */ 597 #define MAX_PACK_BOUNDARY 512 598 599 static inline void 600 setup_pad_and_pack_boundaries(struct adapter *sc) 601 { 602 uint32_t v, m; 603 int pad, pack, pad_shift; 604 605 pad_shift = chip_id(sc) > CHELSIO_T5 ? X_T6_INGPADBOUNDARY_SHIFT : 606 X_INGPADBOUNDARY_SHIFT; 607 pad = fl_pad; 608 if (fl_pad < (1 << pad_shift) || 609 fl_pad > (1 << (pad_shift + M_INGPADBOUNDARY)) || 610 !powerof2(fl_pad)) { 611 /* 612 * If there is any chance that we might use buffer packing and 613 * the chip is a T4, then pick 64 as the pad/pack boundary. Set 614 * it to the minimum allowed in all other cases. 615 */ 616 pad = is_t4(sc) && buffer_packing ? 64 : 1 << pad_shift; 617 618 /* 619 * For fl_pad = 0 we'll still write a reasonable value to the 620 * register but all the freelists will opt out of padding. 621 * We'll complain here only if the user tried to set it to a 622 * value greater than 0 that was invalid. 623 */ 624 if (fl_pad > 0) { 625 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pad value" 626 " (%d), using %d instead.\n", fl_pad, pad); 627 } 628 } 629 m = V_INGPADBOUNDARY(M_INGPADBOUNDARY); 630 v = V_INGPADBOUNDARY(ilog2(pad) - pad_shift); 631 t4_set_reg_field(sc, A_SGE_CONTROL, m, v); 632 633 if (is_t4(sc)) { 634 if (fl_pack != -1 && fl_pack != pad) { 635 /* Complain but carry on. */ 636 device_printf(sc->dev, "hw.cxgbe.fl_pack (%d) ignored," 637 " using %d instead.\n", fl_pack, pad); 638 } 639 return; 640 } 641 642 pack = fl_pack; 643 if (fl_pack < 16 || fl_pack == 32 || fl_pack > 4096 || 644 !powerof2(fl_pack)) { 645 if (sc->params.pci.mps > MAX_PACK_BOUNDARY) 646 pack = MAX_PACK_BOUNDARY; 647 else 648 pack = max(sc->params.pci.mps, CACHE_LINE_SIZE); 649 MPASS(powerof2(pack)); 650 if (pack < 16) 651 pack = 16; 652 if (pack == 32) 653 pack = 64; 654 if (pack > 4096) 655 pack = 4096; 656 if (fl_pack != -1) { 657 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pack value" 658 " (%d), using %d instead.\n", fl_pack, pack); 659 } 660 } 661 m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY); 662 if (pack == 16) 663 v = V_INGPACKBOUNDARY(0); 664 else 665 v = V_INGPACKBOUNDARY(ilog2(pack) - 5); 666 667 MPASS(!is_t4(sc)); /* T4 doesn't have SGE_CONTROL2 */ 668 t4_set_reg_field(sc, A_SGE_CONTROL2, m, v); 669 } 670 671 /* 672 * adap->params.vpd.cclk must be set up before this is called. 673 */ 674 void 675 t4_tweak_chip_settings(struct adapter *sc) 676 { 677 int i, reg; 678 uint32_t v, m; 679 int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200}; 680 int timer_max = M_TIMERVALUE0 * 1000 / sc->params.vpd.cclk; 681 int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */ 682 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 683 static int sw_buf_sizes[] = { 684 MCLBYTES, 685 #if MJUMPAGESIZE != MCLBYTES 686 MJUMPAGESIZE, 687 #endif 688 MJUM9BYTES, 689 MJUM16BYTES 690 }; 691 692 KASSERT(sc->flags & MASTER_PF, 693 ("%s: trying to change chip settings when not master.", __func__)); 694 695 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE; 696 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE | 697 V_EGRSTATUSPAGESIZE(spg_len == 128); 698 t4_set_reg_field(sc, A_SGE_CONTROL, m, v); 699 700 setup_pad_and_pack_boundaries(sc); 701 702 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) | 703 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) | 704 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) | 705 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) | 706 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) | 707 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) | 708 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) | 709 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10); 710 t4_write_reg(sc, A_SGE_HOST_PAGE_SIZE, v); 711 712 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0, 4096); 713 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE1, 65536); 714 reg = A_SGE_FL_BUFFER_SIZE2; 715 for (i = 0; i < nitems(sw_buf_sizes); i++) { 716 MPASS(reg <= A_SGE_FL_BUFFER_SIZE15); 717 t4_write_reg(sc, reg, sw_buf_sizes[i]); 718 reg += 4; 719 MPASS(reg <= A_SGE_FL_BUFFER_SIZE15); 720 t4_write_reg(sc, reg, sw_buf_sizes[i] - CL_METADATA_SIZE); 721 reg += 4; 722 } 723 724 v = V_THRESHOLD_0(intr_pktcount[0]) | V_THRESHOLD_1(intr_pktcount[1]) | 725 V_THRESHOLD_2(intr_pktcount[2]) | V_THRESHOLD_3(intr_pktcount[3]); 726 t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD, v); 727 728 KASSERT(intr_timer[0] <= timer_max, 729 ("%s: not a single usable timer (%d, %d)", __func__, intr_timer[0], 730 timer_max)); 731 for (i = 1; i < nitems(intr_timer); i++) { 732 KASSERT(intr_timer[i] >= intr_timer[i - 1], 733 ("%s: timers not listed in increasing order (%d)", 734 __func__, i)); 735 736 while (intr_timer[i] > timer_max) { 737 if (i == nitems(intr_timer) - 1) { 738 intr_timer[i] = timer_max; 739 break; 740 } 741 intr_timer[i] += intr_timer[i - 1]; 742 intr_timer[i] /= 2; 743 } 744 } 745 746 v = V_TIMERVALUE0(us_to_core_ticks(sc, intr_timer[0])) | 747 V_TIMERVALUE1(us_to_core_ticks(sc, intr_timer[1])); 748 t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1, v); 749 v = V_TIMERVALUE2(us_to_core_ticks(sc, intr_timer[2])) | 750 V_TIMERVALUE3(us_to_core_ticks(sc, intr_timer[3])); 751 t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3, v); 752 v = V_TIMERVALUE4(us_to_core_ticks(sc, intr_timer[4])) | 753 V_TIMERVALUE5(us_to_core_ticks(sc, intr_timer[5])); 754 t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5, v); 755 756 if (chip_id(sc) >= CHELSIO_T6) { 757 m = V_TSCALE(M_TSCALE); 758 if (tscale == 1) 759 v = 0; 760 else 761 v = V_TSCALE(tscale - 2); 762 t4_set_reg_field(sc, A_SGE_ITP_CONTROL, m, v); 763 764 if (sc->debug_flags & DF_DISABLE_TCB_CACHE) { 765 m = V_RDTHRESHOLD(M_RDTHRESHOLD) | F_WRTHRTHRESHEN | 766 V_WRTHRTHRESH(M_WRTHRTHRESH); 767 t4_tp_pio_read(sc, &v, 1, A_TP_CMM_CONFIG, 1); 768 v &= ~m; 769 v |= V_RDTHRESHOLD(1) | F_WRTHRTHRESHEN | 770 V_WRTHRTHRESH(16); 771 t4_tp_pio_write(sc, &v, 1, A_TP_CMM_CONFIG, 1); 772 } 773 } 774 775 /* 4K, 16K, 64K, 256K DDP "page sizes" for TDDP */ 776 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 777 t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, v); 778 779 /* 780 * 4K, 8K, 16K, 64K DDP "page sizes" for iSCSI DDP. These have been 781 * chosen with MAXPHYS = 128K in mind. The largest DDP buffer that we 782 * may have to deal with is MAXPHYS + 1 page. 783 */ 784 v = V_HPZ0(0) | V_HPZ1(1) | V_HPZ2(2) | V_HPZ3(4); 785 t4_write_reg(sc, A_ULP_RX_ISCSI_PSZ, v); 786 787 /* We use multiple DDP page sizes both in plain-TOE and ISCSI modes. */ 788 m = v = F_TDDPTAGTCB | F_ISCSITAGTCB; 789 t4_set_reg_field(sc, A_ULP_RX_CTL, m, v); 790 791 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 792 F_RESETDDPOFFSET; 793 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 794 t4_set_reg_field(sc, A_TP_PARA_REG5, m, v); 795 } 796 797 /* 798 * SGE wants the buffer to be at least 64B and then a multiple of 16. Its 799 * address mut be 16B aligned. If padding is in use the buffer's start and end 800 * need to be aligned to the pad boundary as well. We'll just make sure that 801 * the size is a multiple of the pad boundary here, it is up to the buffer 802 * allocation code to make sure the start of the buffer is aligned. 803 */ 804 static inline int 805 hwsz_ok(struct adapter *sc, int hwsz) 806 { 807 int mask = fl_pad ? sc->params.sge.pad_boundary - 1 : 16 - 1; 808 809 return (hwsz >= 64 && (hwsz & mask) == 0); 810 } 811 812 /* 813 * XXX: driver really should be able to deal with unexpected settings. 814 */ 815 int 816 t4_read_chip_settings(struct adapter *sc) 817 { 818 struct sge *s = &sc->sge; 819 struct sge_params *sp = &sc->params.sge; 820 int i, j, n, rc = 0; 821 uint32_t m, v, r; 822 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 823 static int sw_buf_sizes[] = { /* Sorted by size */ 824 MCLBYTES, 825 #if MJUMPAGESIZE != MCLBYTES 826 MJUMPAGESIZE, 827 #endif 828 MJUM9BYTES, 829 MJUM16BYTES 830 }; 831 struct rx_buf_info *rxb; 832 833 m = F_RXPKTCPLMODE; 834 v = F_RXPKTCPLMODE; 835 r = sc->params.sge.sge_control; 836 if ((r & m) != v) { 837 device_printf(sc->dev, "invalid SGE_CONTROL(0x%x)\n", r); 838 rc = EINVAL; 839 } 840 841 /* 842 * If this changes then every single use of PAGE_SHIFT in the driver 843 * needs to be carefully reviewed for PAGE_SHIFT vs sp->page_shift. 844 */ 845 if (sp->page_shift != PAGE_SHIFT) { 846 device_printf(sc->dev, "invalid SGE_HOST_PAGE_SIZE(0x%x)\n", r); 847 rc = EINVAL; 848 } 849 850 s->safe_zidx = -1; 851 rxb = &s->rx_buf_info[0]; 852 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) { 853 rxb->size1 = sw_buf_sizes[i]; 854 rxb->zone = m_getzone(rxb->size1); 855 rxb->type = m_gettype(rxb->size1); 856 rxb->size2 = 0; 857 rxb->hwidx1 = -1; 858 rxb->hwidx2 = -1; 859 for (j = 0; j < SGE_FLBUF_SIZES; j++) { 860 int hwsize = sp->sge_fl_buffer_size[j]; 861 862 if (!hwsz_ok(sc, hwsize)) 863 continue; 864 865 /* hwidx for size1 */ 866 if (rxb->hwidx1 == -1 && rxb->size1 == hwsize) 867 rxb->hwidx1 = j; 868 869 /* hwidx for size2 (buffer packing) */ 870 if (rxb->size1 - CL_METADATA_SIZE < hwsize) 871 continue; 872 n = rxb->size1 - hwsize - CL_METADATA_SIZE; 873 if (n == 0) { 874 rxb->hwidx2 = j; 875 rxb->size2 = hwsize; 876 break; /* stop looking */ 877 } 878 if (rxb->hwidx2 != -1) { 879 if (n < sp->sge_fl_buffer_size[rxb->hwidx2] - 880 hwsize - CL_METADATA_SIZE) { 881 rxb->hwidx2 = j; 882 rxb->size2 = hwsize; 883 } 884 } else if (n <= 2 * CL_METADATA_SIZE) { 885 rxb->hwidx2 = j; 886 rxb->size2 = hwsize; 887 } 888 } 889 if (rxb->hwidx2 != -1) 890 sc->flags |= BUF_PACKING_OK; 891 if (s->safe_zidx == -1 && rxb->size1 == safest_rx_cluster) 892 s->safe_zidx = i; 893 } 894 895 if (sc->flags & IS_VF) 896 return (0); 897 898 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 899 r = t4_read_reg(sc, A_ULP_RX_TDDP_PSZ); 900 if (r != v) { 901 device_printf(sc->dev, "invalid ULP_RX_TDDP_PSZ(0x%x)\n", r); 902 rc = EINVAL; 903 } 904 905 m = v = F_TDDPTAGTCB; 906 r = t4_read_reg(sc, A_ULP_RX_CTL); 907 if ((r & m) != v) { 908 device_printf(sc->dev, "invalid ULP_RX_CTL(0x%x)\n", r); 909 rc = EINVAL; 910 } 911 912 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 913 F_RESETDDPOFFSET; 914 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 915 r = t4_read_reg(sc, A_TP_PARA_REG5); 916 if ((r & m) != v) { 917 device_printf(sc->dev, "invalid TP_PARA_REG5(0x%x)\n", r); 918 rc = EINVAL; 919 } 920 921 t4_init_tp_params(sc, 1); 922 923 t4_read_mtu_tbl(sc, sc->params.mtus, NULL); 924 t4_load_mtus(sc, sc->params.mtus, sc->params.a_wnd, sc->params.b_wnd); 925 926 return (rc); 927 } 928 929 int 930 t4_create_dma_tag(struct adapter *sc) 931 { 932 int rc; 933 934 rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0, 935 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE, 936 BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL, 937 NULL, &sc->dmat); 938 if (rc != 0) { 939 device_printf(sc->dev, 940 "failed to create main DMA tag: %d\n", rc); 941 } 942 943 return (rc); 944 } 945 946 void 947 t4_sge_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx, 948 struct sysctl_oid_list *children) 949 { 950 struct sge_params *sp = &sc->params.sge; 951 952 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "buffer_sizes", 953 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 954 sysctl_bufsizes, "A", "freelist buffer sizes"); 955 956 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pktshift", CTLFLAG_RD, 957 NULL, sp->fl_pktshift, "payload DMA offset in rx buffer (bytes)"); 958 959 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pad", CTLFLAG_RD, 960 NULL, sp->pad_boundary, "payload pad boundary (bytes)"); 961 962 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "spg_len", CTLFLAG_RD, 963 NULL, sp->spg_len, "status page size (bytes)"); 964 965 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_drop", CTLFLAG_RD, 966 NULL, cong_drop, "congestion drop setting"); 967 968 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pack", CTLFLAG_RD, 969 NULL, sp->pack_boundary, "payload pack boundary (bytes)"); 970 } 971 972 int 973 t4_destroy_dma_tag(struct adapter *sc) 974 { 975 if (sc->dmat) 976 bus_dma_tag_destroy(sc->dmat); 977 978 return (0); 979 } 980 981 /* 982 * Allocate and initialize the firmware event queue, control queues, and special 983 * purpose rx queues owned by the adapter. 984 * 985 * Returns errno on failure. Resources allocated up to that point may still be 986 * allocated. Caller is responsible for cleanup in case this function fails. 987 */ 988 int 989 t4_setup_adapter_queues(struct adapter *sc) 990 { 991 struct sysctl_oid *oid; 992 struct sysctl_oid_list *children; 993 int rc, i; 994 995 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 996 997 sysctl_ctx_init(&sc->ctx); 998 sc->flags |= ADAP_SYSCTL_CTX; 999 1000 /* 1001 * Firmware event queue 1002 */ 1003 rc = alloc_fwq(sc); 1004 if (rc != 0) 1005 return (rc); 1006 1007 /* 1008 * That's all for the VF driver. 1009 */ 1010 if (sc->flags & IS_VF) 1011 return (rc); 1012 1013 oid = device_get_sysctl_tree(sc->dev); 1014 children = SYSCTL_CHILDREN(oid); 1015 1016 /* 1017 * XXX: General purpose rx queues, one per port. 1018 */ 1019 1020 /* 1021 * Control queues, one per port. 1022 */ 1023 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "ctrlq", 1024 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "control queues"); 1025 for_each_port(sc, i) { 1026 struct sge_wrq *ctrlq = &sc->sge.ctrlq[i]; 1027 1028 rc = alloc_ctrlq(sc, ctrlq, i, oid); 1029 if (rc != 0) 1030 return (rc); 1031 } 1032 1033 return (rc); 1034 } 1035 1036 /* 1037 * Idempotent 1038 */ 1039 int 1040 t4_teardown_adapter_queues(struct adapter *sc) 1041 { 1042 int i; 1043 1044 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 1045 1046 /* Do this before freeing the queue */ 1047 if (sc->flags & ADAP_SYSCTL_CTX) { 1048 sysctl_ctx_free(&sc->ctx); 1049 sc->flags &= ~ADAP_SYSCTL_CTX; 1050 } 1051 1052 if (!(sc->flags & IS_VF)) { 1053 for_each_port(sc, i) 1054 free_wrq(sc, &sc->sge.ctrlq[i]); 1055 } 1056 free_fwq(sc); 1057 1058 return (0); 1059 } 1060 1061 /* Maximum payload that could arrive with a single iq descriptor. */ 1062 static inline int 1063 max_rx_payload(struct adapter *sc, struct ifnet *ifp, const bool ofld) 1064 { 1065 int maxp; 1066 1067 /* large enough even when hw VLAN extraction is disabled */ 1068 maxp = sc->params.sge.fl_pktshift + ETHER_HDR_LEN + 1069 ETHER_VLAN_ENCAP_LEN + ifp->if_mtu; 1070 if (ofld && sc->tt.tls && sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS && 1071 maxp < sc->params.tp.max_rx_pdu) 1072 maxp = sc->params.tp.max_rx_pdu; 1073 return (maxp); 1074 } 1075 1076 int 1077 t4_setup_vi_queues(struct vi_info *vi) 1078 { 1079 int rc = 0, i, intr_idx, iqidx; 1080 struct sge_rxq *rxq; 1081 struct sge_txq *txq; 1082 #ifdef TCP_OFFLOAD 1083 struct sge_ofld_rxq *ofld_rxq; 1084 #endif 1085 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1086 struct sge_wrq *ofld_txq; 1087 #endif 1088 #ifdef DEV_NETMAP 1089 int saved_idx; 1090 struct sge_nm_rxq *nm_rxq; 1091 struct sge_nm_txq *nm_txq; 1092 #endif 1093 char name[16]; 1094 struct port_info *pi = vi->pi; 1095 struct adapter *sc = pi->adapter; 1096 struct ifnet *ifp = vi->ifp; 1097 struct sysctl_oid *oid = device_get_sysctl_tree(vi->dev); 1098 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 1099 int maxp; 1100 1101 /* Interrupt vector to start from (when using multiple vectors) */ 1102 intr_idx = vi->first_intr; 1103 1104 #ifdef DEV_NETMAP 1105 saved_idx = intr_idx; 1106 if (ifp->if_capabilities & IFCAP_NETMAP) { 1107 1108 /* netmap is supported with direct interrupts only. */ 1109 MPASS(!forwarding_intr_to_fwq(sc)); 1110 1111 /* 1112 * We don't have buffers to back the netmap rx queues 1113 * right now so we create the queues in a way that 1114 * doesn't set off any congestion signal in the chip. 1115 */ 1116 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "nm_rxq", 1117 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "rx queues"); 1118 for_each_nm_rxq(vi, i, nm_rxq) { 1119 rc = alloc_nm_rxq(vi, nm_rxq, intr_idx, i, oid); 1120 if (rc != 0) 1121 goto done; 1122 intr_idx++; 1123 } 1124 1125 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "nm_txq", 1126 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "tx queues"); 1127 for_each_nm_txq(vi, i, nm_txq) { 1128 iqidx = vi->first_nm_rxq + (i % vi->nnmrxq); 1129 rc = alloc_nm_txq(vi, nm_txq, iqidx, i, oid); 1130 if (rc != 0) 1131 goto done; 1132 } 1133 } 1134 1135 /* Normal rx queues and netmap rx queues share the same interrupts. */ 1136 intr_idx = saved_idx; 1137 #endif 1138 1139 /* 1140 * Allocate rx queues first because a default iqid is required when 1141 * creating a tx queue. 1142 */ 1143 maxp = max_rx_payload(sc, ifp, false); 1144 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "rxq", 1145 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "rx queues"); 1146 for_each_rxq(vi, i, rxq) { 1147 1148 init_iq(&rxq->iq, sc, vi->tmr_idx, vi->pktc_idx, vi->qsize_rxq); 1149 1150 snprintf(name, sizeof(name), "%s rxq%d-fl", 1151 device_get_nameunit(vi->dev), i); 1152 init_fl(sc, &rxq->fl, vi->qsize_rxq / 8, maxp, name); 1153 1154 rc = alloc_rxq(vi, rxq, 1155 forwarding_intr_to_fwq(sc) ? -1 : intr_idx, i, oid); 1156 if (rc != 0) 1157 goto done; 1158 intr_idx++; 1159 } 1160 #ifdef DEV_NETMAP 1161 if (ifp->if_capabilities & IFCAP_NETMAP) 1162 intr_idx = saved_idx + max(vi->nrxq, vi->nnmrxq); 1163 #endif 1164 #ifdef TCP_OFFLOAD 1165 maxp = max_rx_payload(sc, ifp, true); 1166 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_rxq", 1167 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "rx queues for offloaded TCP connections"); 1168 for_each_ofld_rxq(vi, i, ofld_rxq) { 1169 1170 init_iq(&ofld_rxq->iq, sc, vi->ofld_tmr_idx, vi->ofld_pktc_idx, 1171 vi->qsize_rxq); 1172 1173 snprintf(name, sizeof(name), "%s ofld_rxq%d-fl", 1174 device_get_nameunit(vi->dev), i); 1175 init_fl(sc, &ofld_rxq->fl, vi->qsize_rxq / 8, maxp, name); 1176 1177 rc = alloc_ofld_rxq(vi, ofld_rxq, 1178 forwarding_intr_to_fwq(sc) ? -1 : intr_idx, i, oid); 1179 if (rc != 0) 1180 goto done; 1181 intr_idx++; 1182 } 1183 #endif 1184 1185 /* 1186 * Now the tx queues. 1187 */ 1188 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "txq", 1189 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "tx queues"); 1190 for_each_txq(vi, i, txq) { 1191 iqidx = vi->first_rxq + (i % vi->nrxq); 1192 snprintf(name, sizeof(name), "%s txq%d", 1193 device_get_nameunit(vi->dev), i); 1194 init_eq(sc, &txq->eq, EQ_ETH, vi->qsize_txq, pi->tx_chan, 1195 sc->sge.rxq[iqidx].iq.cntxt_id, name); 1196 1197 rc = alloc_txq(vi, txq, i, oid); 1198 if (rc != 0) 1199 goto done; 1200 } 1201 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1202 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_txq", 1203 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "tx queues for TOE/ETHOFLD"); 1204 for_each_ofld_txq(vi, i, ofld_txq) { 1205 struct sysctl_oid *oid2; 1206 1207 snprintf(name, sizeof(name), "%s ofld_txq%d", 1208 device_get_nameunit(vi->dev), i); 1209 if (vi->nofldrxq > 0) { 1210 iqidx = vi->first_ofld_rxq + (i % vi->nofldrxq); 1211 init_eq(sc, &ofld_txq->eq, EQ_OFLD, vi->qsize_txq, 1212 pi->tx_chan, sc->sge.ofld_rxq[iqidx].iq.cntxt_id, 1213 name); 1214 } else { 1215 iqidx = vi->first_rxq + (i % vi->nrxq); 1216 init_eq(sc, &ofld_txq->eq, EQ_OFLD, vi->qsize_txq, 1217 pi->tx_chan, sc->sge.rxq[iqidx].iq.cntxt_id, name); 1218 } 1219 1220 snprintf(name, sizeof(name), "%d", i); 1221 oid2 = SYSCTL_ADD_NODE(&vi->ctx, SYSCTL_CHILDREN(oid), OID_AUTO, 1222 name, CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "offload tx queue"); 1223 1224 rc = alloc_wrq(sc, vi, ofld_txq, oid2); 1225 if (rc != 0) 1226 goto done; 1227 } 1228 #endif 1229 done: 1230 if (rc) 1231 t4_teardown_vi_queues(vi); 1232 1233 return (rc); 1234 } 1235 1236 /* 1237 * Idempotent 1238 */ 1239 int 1240 t4_teardown_vi_queues(struct vi_info *vi) 1241 { 1242 int i; 1243 struct sge_rxq *rxq; 1244 struct sge_txq *txq; 1245 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1246 struct port_info *pi = vi->pi; 1247 struct adapter *sc = pi->adapter; 1248 struct sge_wrq *ofld_txq; 1249 #endif 1250 #ifdef TCP_OFFLOAD 1251 struct sge_ofld_rxq *ofld_rxq; 1252 #endif 1253 #ifdef DEV_NETMAP 1254 struct sge_nm_rxq *nm_rxq; 1255 struct sge_nm_txq *nm_txq; 1256 #endif 1257 1258 /* Do this before freeing the queues */ 1259 if (vi->flags & VI_SYSCTL_CTX) { 1260 sysctl_ctx_free(&vi->ctx); 1261 vi->flags &= ~VI_SYSCTL_CTX; 1262 } 1263 1264 #ifdef DEV_NETMAP 1265 if (vi->ifp->if_capabilities & IFCAP_NETMAP) { 1266 for_each_nm_txq(vi, i, nm_txq) { 1267 free_nm_txq(vi, nm_txq); 1268 } 1269 1270 for_each_nm_rxq(vi, i, nm_rxq) { 1271 free_nm_rxq(vi, nm_rxq); 1272 } 1273 } 1274 #endif 1275 1276 /* 1277 * Take down all the tx queues first, as they reference the rx queues 1278 * (for egress updates, etc.). 1279 */ 1280 1281 for_each_txq(vi, i, txq) { 1282 free_txq(vi, txq); 1283 } 1284 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1285 for_each_ofld_txq(vi, i, ofld_txq) { 1286 free_wrq(sc, ofld_txq); 1287 } 1288 #endif 1289 1290 /* 1291 * Then take down the rx queues. 1292 */ 1293 1294 for_each_rxq(vi, i, rxq) { 1295 free_rxq(vi, rxq); 1296 } 1297 #ifdef TCP_OFFLOAD 1298 for_each_ofld_rxq(vi, i, ofld_rxq) { 1299 free_ofld_rxq(vi, ofld_rxq); 1300 } 1301 #endif 1302 1303 return (0); 1304 } 1305 1306 /* 1307 * Interrupt handler when the driver is using only 1 interrupt. This is a very 1308 * unusual scenario. 1309 * 1310 * a) Deals with errors, if any. 1311 * b) Services firmware event queue, which is taking interrupts for all other 1312 * queues. 1313 */ 1314 void 1315 t4_intr_all(void *arg) 1316 { 1317 struct adapter *sc = arg; 1318 struct sge_iq *fwq = &sc->sge.fwq; 1319 1320 MPASS(sc->intr_count == 1); 1321 1322 if (sc->intr_type == INTR_INTX) 1323 t4_write_reg(sc, MYPF_REG(A_PCIE_PF_CLI), 0); 1324 1325 t4_intr_err(arg); 1326 t4_intr_evt(fwq); 1327 } 1328 1329 /* 1330 * Interrupt handler for errors (installed directly when multiple interrupts are 1331 * being used, or called by t4_intr_all). 1332 */ 1333 void 1334 t4_intr_err(void *arg) 1335 { 1336 struct adapter *sc = arg; 1337 uint32_t v; 1338 const bool verbose = (sc->debug_flags & DF_VERBOSE_SLOWINTR) != 0; 1339 1340 if (sc->flags & ADAP_ERR) 1341 return; 1342 1343 v = t4_read_reg(sc, MYPF_REG(A_PL_PF_INT_CAUSE)); 1344 if (v & F_PFSW) { 1345 sc->swintr++; 1346 t4_write_reg(sc, MYPF_REG(A_PL_PF_INT_CAUSE), v); 1347 } 1348 1349 t4_slow_intr_handler(sc, verbose); 1350 } 1351 1352 /* 1353 * Interrupt handler for iq-only queues. The firmware event queue is the only 1354 * such queue right now. 1355 */ 1356 void 1357 t4_intr_evt(void *arg) 1358 { 1359 struct sge_iq *iq = arg; 1360 1361 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 1362 service_iq(iq, 0); 1363 (void) atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 1364 } 1365 } 1366 1367 /* 1368 * Interrupt handler for iq+fl queues. 1369 */ 1370 void 1371 t4_intr(void *arg) 1372 { 1373 struct sge_iq *iq = arg; 1374 1375 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 1376 service_iq_fl(iq, 0); 1377 (void) atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 1378 } 1379 } 1380 1381 #ifdef DEV_NETMAP 1382 /* 1383 * Interrupt handler for netmap rx queues. 1384 */ 1385 void 1386 t4_nm_intr(void *arg) 1387 { 1388 struct sge_nm_rxq *nm_rxq = arg; 1389 1390 if (atomic_cmpset_int(&nm_rxq->nm_state, NM_ON, NM_BUSY)) { 1391 service_nm_rxq(nm_rxq); 1392 (void) atomic_cmpset_int(&nm_rxq->nm_state, NM_BUSY, NM_ON); 1393 } 1394 } 1395 1396 /* 1397 * Interrupt handler for vectors shared between NIC and netmap rx queues. 1398 */ 1399 void 1400 t4_vi_intr(void *arg) 1401 { 1402 struct irq *irq = arg; 1403 1404 MPASS(irq->nm_rxq != NULL); 1405 t4_nm_intr(irq->nm_rxq); 1406 1407 MPASS(irq->rxq != NULL); 1408 t4_intr(irq->rxq); 1409 } 1410 #endif 1411 1412 /* 1413 * Deals with interrupts on an iq-only (no freelist) queue. 1414 */ 1415 static int 1416 service_iq(struct sge_iq *iq, int budget) 1417 { 1418 struct sge_iq *q; 1419 struct adapter *sc = iq->adapter; 1420 struct iq_desc *d = &iq->desc[iq->cidx]; 1421 int ndescs = 0, limit; 1422 int rsp_type; 1423 uint32_t lq; 1424 STAILQ_HEAD(, sge_iq) iql = STAILQ_HEAD_INITIALIZER(iql); 1425 1426 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq)); 1427 KASSERT((iq->flags & IQ_HAS_FL) == 0, 1428 ("%s: called for iq %p with fl (iq->flags 0x%x)", __func__, iq, 1429 iq->flags)); 1430 MPASS((iq->flags & IQ_ADJ_CREDIT) == 0); 1431 MPASS((iq->flags & IQ_LRO_ENABLED) == 0); 1432 1433 limit = budget ? budget : iq->qsize / 16; 1434 1435 /* 1436 * We always come back and check the descriptor ring for new indirect 1437 * interrupts and other responses after running a single handler. 1438 */ 1439 for (;;) { 1440 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) { 1441 1442 rmb(); 1443 1444 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen); 1445 lq = be32toh(d->rsp.pldbuflen_qid); 1446 1447 switch (rsp_type) { 1448 case X_RSPD_TYPE_FLBUF: 1449 panic("%s: data for an iq (%p) with no freelist", 1450 __func__, iq); 1451 1452 /* NOTREACHED */ 1453 1454 case X_RSPD_TYPE_CPL: 1455 KASSERT(d->rss.opcode < NUM_CPL_CMDS, 1456 ("%s: bad opcode %02x.", __func__, 1457 d->rss.opcode)); 1458 t4_cpl_handler[d->rss.opcode](iq, &d->rss, NULL); 1459 break; 1460 1461 case X_RSPD_TYPE_INTR: 1462 /* 1463 * There are 1K interrupt-capable queues (qids 0 1464 * through 1023). A response type indicating a 1465 * forwarded interrupt with a qid >= 1K is an 1466 * iWARP async notification. 1467 */ 1468 if (__predict_true(lq >= 1024)) { 1469 t4_an_handler(iq, &d->rsp); 1470 break; 1471 } 1472 1473 q = sc->sge.iqmap[lq - sc->sge.iq_start - 1474 sc->sge.iq_base]; 1475 if (atomic_cmpset_int(&q->state, IQS_IDLE, 1476 IQS_BUSY)) { 1477 if (service_iq_fl(q, q->qsize / 16) == 0) { 1478 (void) atomic_cmpset_int(&q->state, 1479 IQS_BUSY, IQS_IDLE); 1480 } else { 1481 STAILQ_INSERT_TAIL(&iql, q, 1482 link); 1483 } 1484 } 1485 break; 1486 1487 default: 1488 KASSERT(0, 1489 ("%s: illegal response type %d on iq %p", 1490 __func__, rsp_type, iq)); 1491 log(LOG_ERR, 1492 "%s: illegal response type %d on iq %p", 1493 device_get_nameunit(sc->dev), rsp_type, iq); 1494 break; 1495 } 1496 1497 d++; 1498 if (__predict_false(++iq->cidx == iq->sidx)) { 1499 iq->cidx = 0; 1500 iq->gen ^= F_RSPD_GEN; 1501 d = &iq->desc[0]; 1502 } 1503 if (__predict_false(++ndescs == limit)) { 1504 t4_write_reg(sc, sc->sge_gts_reg, 1505 V_CIDXINC(ndescs) | 1506 V_INGRESSQID(iq->cntxt_id) | 1507 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); 1508 ndescs = 0; 1509 1510 if (budget) { 1511 return (EINPROGRESS); 1512 } 1513 } 1514 } 1515 1516 if (STAILQ_EMPTY(&iql)) 1517 break; 1518 1519 /* 1520 * Process the head only, and send it to the back of the list if 1521 * it's still not done. 1522 */ 1523 q = STAILQ_FIRST(&iql); 1524 STAILQ_REMOVE_HEAD(&iql, link); 1525 if (service_iq_fl(q, q->qsize / 8) == 0) 1526 (void) atomic_cmpset_int(&q->state, IQS_BUSY, IQS_IDLE); 1527 else 1528 STAILQ_INSERT_TAIL(&iql, q, link); 1529 } 1530 1531 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) | 1532 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params)); 1533 1534 return (0); 1535 } 1536 1537 static inline int 1538 sort_before_lro(struct lro_ctrl *lro) 1539 { 1540 1541 return (lro->lro_mbuf_max != 0); 1542 } 1543 1544 static inline uint64_t 1545 last_flit_to_ns(struct adapter *sc, uint64_t lf) 1546 { 1547 uint64_t n = be64toh(lf) & 0xfffffffffffffff; /* 60b, not 64b. */ 1548 1549 if (n > UINT64_MAX / 1000000) 1550 return (n / sc->params.vpd.cclk * 1000000); 1551 else 1552 return (n * 1000000 / sc->params.vpd.cclk); 1553 } 1554 1555 static inline void 1556 move_to_next_rxbuf(struct sge_fl *fl) 1557 { 1558 1559 fl->rx_offset = 0; 1560 if (__predict_false((++fl->cidx & 7) == 0)) { 1561 uint16_t cidx = fl->cidx >> 3; 1562 1563 if (__predict_false(cidx == fl->sidx)) 1564 fl->cidx = cidx = 0; 1565 fl->hw_cidx = cidx; 1566 } 1567 } 1568 1569 /* 1570 * Deals with interrupts on an iq+fl queue. 1571 */ 1572 static int 1573 service_iq_fl(struct sge_iq *iq, int budget) 1574 { 1575 struct sge_rxq *rxq = iq_to_rxq(iq); 1576 struct sge_fl *fl; 1577 struct adapter *sc = iq->adapter; 1578 struct iq_desc *d = &iq->desc[iq->cidx]; 1579 int ndescs, limit; 1580 int rsp_type, starved; 1581 uint32_t lq; 1582 uint16_t fl_hw_cidx; 1583 struct mbuf *m0; 1584 #if defined(INET) || defined(INET6) 1585 const struct timeval lro_timeout = {0, sc->lro_timeout}; 1586 struct lro_ctrl *lro = &rxq->lro; 1587 #endif 1588 1589 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq)); 1590 MPASS(iq->flags & IQ_HAS_FL); 1591 1592 ndescs = 0; 1593 #if defined(INET) || defined(INET6) 1594 if (iq->flags & IQ_ADJ_CREDIT) { 1595 MPASS(sort_before_lro(lro)); 1596 iq->flags &= ~IQ_ADJ_CREDIT; 1597 if ((d->rsp.u.type_gen & F_RSPD_GEN) != iq->gen) { 1598 tcp_lro_flush_all(lro); 1599 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(1) | 1600 V_INGRESSQID((u32)iq->cntxt_id) | 1601 V_SEINTARM(iq->intr_params)); 1602 return (0); 1603 } 1604 ndescs = 1; 1605 } 1606 #else 1607 MPASS((iq->flags & IQ_ADJ_CREDIT) == 0); 1608 #endif 1609 1610 limit = budget ? budget : iq->qsize / 16; 1611 fl = &rxq->fl; 1612 fl_hw_cidx = fl->hw_cidx; /* stable snapshot */ 1613 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) { 1614 1615 rmb(); 1616 1617 m0 = NULL; 1618 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen); 1619 lq = be32toh(d->rsp.pldbuflen_qid); 1620 1621 switch (rsp_type) { 1622 case X_RSPD_TYPE_FLBUF: 1623 if (lq & F_RSPD_NEWBUF) { 1624 if (fl->rx_offset > 0) 1625 move_to_next_rxbuf(fl); 1626 lq = G_RSPD_LEN(lq); 1627 } 1628 if (IDXDIFF(fl->hw_cidx, fl_hw_cidx, fl->sidx) > 4) { 1629 FL_LOCK(fl); 1630 refill_fl(sc, fl, 64); 1631 FL_UNLOCK(fl); 1632 fl_hw_cidx = fl->hw_cidx; 1633 } 1634 1635 if (d->rss.opcode == CPL_RX_PKT) { 1636 if (__predict_true(eth_rx(sc, rxq, d, lq) == 0)) 1637 break; 1638 goto out; 1639 } 1640 m0 = get_fl_payload(sc, fl, lq); 1641 if (__predict_false(m0 == NULL)) 1642 goto out; 1643 1644 /* fall through */ 1645 1646 case X_RSPD_TYPE_CPL: 1647 KASSERT(d->rss.opcode < NUM_CPL_CMDS, 1648 ("%s: bad opcode %02x.", __func__, d->rss.opcode)); 1649 t4_cpl_handler[d->rss.opcode](iq, &d->rss, m0); 1650 break; 1651 1652 case X_RSPD_TYPE_INTR: 1653 1654 /* 1655 * There are 1K interrupt-capable queues (qids 0 1656 * through 1023). A response type indicating a 1657 * forwarded interrupt with a qid >= 1K is an 1658 * iWARP async notification. That is the only 1659 * acceptable indirect interrupt on this queue. 1660 */ 1661 if (__predict_false(lq < 1024)) { 1662 panic("%s: indirect interrupt on iq_fl %p " 1663 "with qid %u", __func__, iq, lq); 1664 } 1665 1666 t4_an_handler(iq, &d->rsp); 1667 break; 1668 1669 default: 1670 KASSERT(0, ("%s: illegal response type %d on iq %p", 1671 __func__, rsp_type, iq)); 1672 log(LOG_ERR, "%s: illegal response type %d on iq %p", 1673 device_get_nameunit(sc->dev), rsp_type, iq); 1674 break; 1675 } 1676 1677 d++; 1678 if (__predict_false(++iq->cidx == iq->sidx)) { 1679 iq->cidx = 0; 1680 iq->gen ^= F_RSPD_GEN; 1681 d = &iq->desc[0]; 1682 } 1683 if (__predict_false(++ndescs == limit)) { 1684 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) | 1685 V_INGRESSQID(iq->cntxt_id) | 1686 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); 1687 1688 #if defined(INET) || defined(INET6) 1689 if (iq->flags & IQ_LRO_ENABLED && 1690 !sort_before_lro(lro) && 1691 sc->lro_timeout != 0) { 1692 tcp_lro_flush_inactive(lro, &lro_timeout); 1693 } 1694 #endif 1695 if (budget) 1696 return (EINPROGRESS); 1697 ndescs = 0; 1698 } 1699 } 1700 out: 1701 #if defined(INET) || defined(INET6) 1702 if (iq->flags & IQ_LRO_ENABLED) { 1703 if (ndescs > 0 && lro->lro_mbuf_count > 8) { 1704 MPASS(sort_before_lro(lro)); 1705 /* hold back one credit and don't flush LRO state */ 1706 iq->flags |= IQ_ADJ_CREDIT; 1707 ndescs--; 1708 } else { 1709 tcp_lro_flush_all(lro); 1710 } 1711 } 1712 #endif 1713 1714 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) | 1715 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params)); 1716 1717 FL_LOCK(fl); 1718 starved = refill_fl(sc, fl, 64); 1719 FL_UNLOCK(fl); 1720 if (__predict_false(starved != 0)) 1721 add_fl_to_sfl(sc, fl); 1722 1723 return (0); 1724 } 1725 1726 static inline struct cluster_metadata * 1727 cl_metadata(struct fl_sdesc *sd) 1728 { 1729 1730 return ((void *)(sd->cl + sd->moff)); 1731 } 1732 1733 static void 1734 rxb_free(struct mbuf *m) 1735 { 1736 struct cluster_metadata *clm = m->m_ext.ext_arg1; 1737 1738 uma_zfree(clm->zone, clm->cl); 1739 counter_u64_add(extfree_rels, 1); 1740 } 1741 1742 /* 1743 * The mbuf returned comes from zone_muf and carries the payload in one of these 1744 * ways 1745 * a) complete frame inside the mbuf 1746 * b) m_cljset (for clusters without metadata) 1747 * d) m_extaddref (cluster with metadata) 1748 */ 1749 static struct mbuf * 1750 get_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset, 1751 int remaining) 1752 { 1753 struct mbuf *m; 1754 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 1755 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[sd->zidx]; 1756 struct cluster_metadata *clm; 1757 int len, blen; 1758 caddr_t payload; 1759 1760 if (fl->flags & FL_BUF_PACKING) { 1761 u_int l, pad; 1762 1763 blen = rxb->size2 - fl->rx_offset; /* max possible in this buf */ 1764 len = min(remaining, blen); 1765 payload = sd->cl + fl->rx_offset; 1766 1767 l = fr_offset + len; 1768 pad = roundup2(l, fl->buf_boundary) - l; 1769 if (fl->rx_offset + len + pad < rxb->size2) 1770 blen = len + pad; 1771 MPASS(fl->rx_offset + blen <= rxb->size2); 1772 } else { 1773 MPASS(fl->rx_offset == 0); /* not packing */ 1774 blen = rxb->size1; 1775 len = min(remaining, blen); 1776 payload = sd->cl; 1777 } 1778 1779 if (fr_offset == 0) { 1780 m = m_gethdr(M_NOWAIT, MT_DATA); 1781 if (__predict_false(m == NULL)) 1782 return (NULL); 1783 m->m_pkthdr.len = remaining; 1784 } else { 1785 m = m_get(M_NOWAIT, MT_DATA); 1786 if (__predict_false(m == NULL)) 1787 return (NULL); 1788 } 1789 m->m_len = len; 1790 1791 if (sc->sc_do_rxcopy && len < RX_COPY_THRESHOLD) { 1792 /* copy data to mbuf */ 1793 bcopy(payload, mtod(m, caddr_t), len); 1794 if (fl->flags & FL_BUF_PACKING) { 1795 fl->rx_offset += blen; 1796 MPASS(fl->rx_offset <= rxb->size2); 1797 if (fl->rx_offset < rxb->size2) 1798 return (m); /* without advancing the cidx */ 1799 } 1800 } else if (fl->flags & FL_BUF_PACKING) { 1801 clm = cl_metadata(sd); 1802 if (sd->nmbuf++ == 0) { 1803 clm->refcount = 1; 1804 clm->zone = rxb->zone; 1805 clm->cl = sd->cl; 1806 counter_u64_add(extfree_refs, 1); 1807 } 1808 m_extaddref(m, payload, blen, &clm->refcount, rxb_free, clm, 1809 NULL); 1810 1811 fl->rx_offset += blen; 1812 MPASS(fl->rx_offset <= rxb->size2); 1813 if (fl->rx_offset < rxb->size2) 1814 return (m); /* without advancing the cidx */ 1815 } else { 1816 m_cljset(m, sd->cl, rxb->type); 1817 sd->cl = NULL; /* consumed, not a recycle candidate */ 1818 } 1819 1820 move_to_next_rxbuf(fl); 1821 1822 return (m); 1823 } 1824 1825 static struct mbuf * 1826 get_fl_payload(struct adapter *sc, struct sge_fl *fl, const u_int plen) 1827 { 1828 struct mbuf *m0, *m, **pnext; 1829 u_int remaining; 1830 1831 if (__predict_false(fl->flags & FL_BUF_RESUME)) { 1832 M_ASSERTPKTHDR(fl->m0); 1833 MPASS(fl->m0->m_pkthdr.len == plen); 1834 MPASS(fl->remaining < plen); 1835 1836 m0 = fl->m0; 1837 pnext = fl->pnext; 1838 remaining = fl->remaining; 1839 fl->flags &= ~FL_BUF_RESUME; 1840 goto get_segment; 1841 } 1842 1843 /* 1844 * Payload starts at rx_offset in the current hw buffer. Its length is 1845 * 'len' and it may span multiple hw buffers. 1846 */ 1847 1848 m0 = get_scatter_segment(sc, fl, 0, plen); 1849 if (m0 == NULL) 1850 return (NULL); 1851 remaining = plen - m0->m_len; 1852 pnext = &m0->m_next; 1853 while (remaining > 0) { 1854 get_segment: 1855 MPASS(fl->rx_offset == 0); 1856 m = get_scatter_segment(sc, fl, plen - remaining, remaining); 1857 if (__predict_false(m == NULL)) { 1858 fl->m0 = m0; 1859 fl->pnext = pnext; 1860 fl->remaining = remaining; 1861 fl->flags |= FL_BUF_RESUME; 1862 return (NULL); 1863 } 1864 *pnext = m; 1865 pnext = &m->m_next; 1866 remaining -= m->m_len; 1867 } 1868 *pnext = NULL; 1869 1870 M_ASSERTPKTHDR(m0); 1871 return (m0); 1872 } 1873 1874 static int 1875 skip_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset, 1876 int remaining) 1877 { 1878 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 1879 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[sd->zidx]; 1880 int len, blen; 1881 1882 if (fl->flags & FL_BUF_PACKING) { 1883 u_int l, pad; 1884 1885 blen = rxb->size2 - fl->rx_offset; /* max possible in this buf */ 1886 len = min(remaining, blen); 1887 1888 l = fr_offset + len; 1889 pad = roundup2(l, fl->buf_boundary) - l; 1890 if (fl->rx_offset + len + pad < rxb->size2) 1891 blen = len + pad; 1892 fl->rx_offset += blen; 1893 MPASS(fl->rx_offset <= rxb->size2); 1894 if (fl->rx_offset < rxb->size2) 1895 return (len); /* without advancing the cidx */ 1896 } else { 1897 MPASS(fl->rx_offset == 0); /* not packing */ 1898 blen = rxb->size1; 1899 len = min(remaining, blen); 1900 } 1901 move_to_next_rxbuf(fl); 1902 return (len); 1903 } 1904 1905 static inline void 1906 skip_fl_payload(struct adapter *sc, struct sge_fl *fl, int plen) 1907 { 1908 int remaining, fr_offset, len; 1909 1910 fr_offset = 0; 1911 remaining = plen; 1912 while (remaining > 0) { 1913 len = skip_scatter_segment(sc, fl, fr_offset, remaining); 1914 fr_offset += len; 1915 remaining -= len; 1916 } 1917 } 1918 1919 static inline int 1920 get_segment_len(struct adapter *sc, struct sge_fl *fl, int plen) 1921 { 1922 int len; 1923 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 1924 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[sd->zidx]; 1925 1926 if (fl->flags & FL_BUF_PACKING) 1927 len = rxb->size2 - fl->rx_offset; 1928 else 1929 len = rxb->size1; 1930 1931 return (min(plen, len)); 1932 } 1933 1934 static int 1935 eth_rx(struct adapter *sc, struct sge_rxq *rxq, const struct iq_desc *d, 1936 u_int plen) 1937 { 1938 struct mbuf *m0; 1939 struct ifnet *ifp = rxq->ifp; 1940 struct sge_fl *fl = &rxq->fl; 1941 struct vi_info *vi = ifp->if_softc; 1942 const struct cpl_rx_pkt *cpl; 1943 #if defined(INET) || defined(INET6) 1944 struct lro_ctrl *lro = &rxq->lro; 1945 #endif 1946 uint16_t err_vec, tnl_type, tnlhdr_len; 1947 static const int sw_hashtype[4][2] = { 1948 {M_HASHTYPE_NONE, M_HASHTYPE_NONE}, 1949 {M_HASHTYPE_RSS_IPV4, M_HASHTYPE_RSS_IPV6}, 1950 {M_HASHTYPE_RSS_TCP_IPV4, M_HASHTYPE_RSS_TCP_IPV6}, 1951 {M_HASHTYPE_RSS_UDP_IPV4, M_HASHTYPE_RSS_UDP_IPV6}, 1952 }; 1953 static const int sw_csum_flags[2][2] = { 1954 { 1955 /* IP, inner IP */ 1956 CSUM_ENCAP_VXLAN | 1957 CSUM_L3_CALC | CSUM_L3_VALID | 1958 CSUM_L4_CALC | CSUM_L4_VALID | 1959 CSUM_INNER_L3_CALC | CSUM_INNER_L3_VALID | 1960 CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID, 1961 1962 /* IP, inner IP6 */ 1963 CSUM_ENCAP_VXLAN | 1964 CSUM_L3_CALC | CSUM_L3_VALID | 1965 CSUM_L4_CALC | CSUM_L4_VALID | 1966 CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID, 1967 }, 1968 { 1969 /* IP6, inner IP */ 1970 CSUM_ENCAP_VXLAN | 1971 CSUM_L4_CALC | CSUM_L4_VALID | 1972 CSUM_INNER_L3_CALC | CSUM_INNER_L3_VALID | 1973 CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID, 1974 1975 /* IP6, inner IP6 */ 1976 CSUM_ENCAP_VXLAN | 1977 CSUM_L4_CALC | CSUM_L4_VALID | 1978 CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID, 1979 }, 1980 }; 1981 1982 MPASS(plen > sc->params.sge.fl_pktshift); 1983 if (vi->pfil != NULL && PFIL_HOOKED_IN(vi->pfil) && 1984 __predict_true((fl->flags & FL_BUF_RESUME) == 0)) { 1985 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 1986 caddr_t frame; 1987 int rc, slen; 1988 1989 slen = get_segment_len(sc, fl, plen) - 1990 sc->params.sge.fl_pktshift; 1991 frame = sd->cl + fl->rx_offset + sc->params.sge.fl_pktshift; 1992 CURVNET_SET_QUIET(ifp->if_vnet); 1993 rc = pfil_run_hooks(vi->pfil, frame, ifp, 1994 slen | PFIL_MEMPTR | PFIL_IN, NULL); 1995 CURVNET_RESTORE(); 1996 if (rc == PFIL_DROPPED || rc == PFIL_CONSUMED) { 1997 skip_fl_payload(sc, fl, plen); 1998 return (0); 1999 } 2000 if (rc == PFIL_REALLOCED) { 2001 skip_fl_payload(sc, fl, plen); 2002 m0 = pfil_mem2mbuf(frame); 2003 goto have_mbuf; 2004 } 2005 } 2006 2007 m0 = get_fl_payload(sc, fl, plen); 2008 if (__predict_false(m0 == NULL)) 2009 return (ENOMEM); 2010 2011 m0->m_pkthdr.len -= sc->params.sge.fl_pktshift; 2012 m0->m_len -= sc->params.sge.fl_pktshift; 2013 m0->m_data += sc->params.sge.fl_pktshift; 2014 2015 have_mbuf: 2016 m0->m_pkthdr.rcvif = ifp; 2017 M_HASHTYPE_SET(m0, sw_hashtype[d->rss.hash_type][d->rss.ipv6]); 2018 m0->m_pkthdr.flowid = be32toh(d->rss.hash_val); 2019 2020 cpl = (const void *)(&d->rss + 1); 2021 if (sc->params.tp.rx_pkt_encap) { 2022 const uint16_t ev = be16toh(cpl->err_vec); 2023 2024 err_vec = G_T6_COMPR_RXERR_VEC(ev); 2025 tnl_type = G_T6_RX_TNL_TYPE(ev); 2026 tnlhdr_len = G_T6_RX_TNLHDR_LEN(ev); 2027 } else { 2028 err_vec = be16toh(cpl->err_vec); 2029 tnl_type = 0; 2030 tnlhdr_len = 0; 2031 } 2032 if (cpl->csum_calc && err_vec == 0) { 2033 int ipv6 = !!(cpl->l2info & htobe32(F_RXF_IP6)); 2034 2035 /* checksum(s) calculated and found to be correct. */ 2036 2037 MPASS((cpl->l2info & htobe32(F_RXF_IP)) ^ 2038 (cpl->l2info & htobe32(F_RXF_IP6))); 2039 m0->m_pkthdr.csum_data = be16toh(cpl->csum); 2040 if (tnl_type == 0) { 2041 if (!ipv6 && ifp->if_capenable & IFCAP_RXCSUM) { 2042 m0->m_pkthdr.csum_flags = CSUM_L3_CALC | 2043 CSUM_L3_VALID | CSUM_L4_CALC | 2044 CSUM_L4_VALID; 2045 } else if (ipv6 && ifp->if_capenable & IFCAP_RXCSUM_IPV6) { 2046 m0->m_pkthdr.csum_flags = CSUM_L4_CALC | 2047 CSUM_L4_VALID; 2048 } 2049 rxq->rxcsum++; 2050 } else { 2051 MPASS(tnl_type == RX_PKT_TNL_TYPE_VXLAN); 2052 if (__predict_false(cpl->ip_frag)) { 2053 /* 2054 * csum_data is for the inner frame (which is an 2055 * IP fragment) and is not 0xffff. There is no 2056 * way to pass the inner csum_data to the stack. 2057 * We don't want the stack to use the inner 2058 * csum_data to validate the outer frame or it 2059 * will get rejected. So we fix csum_data here 2060 * and let sw do the checksum of inner IP 2061 * fragments. 2062 * 2063 * XXX: Need 32b for csum_data2 in an rx mbuf. 2064 * Maybe stuff it into rcv_tstmp? 2065 */ 2066 m0->m_pkthdr.csum_data = 0xffff; 2067 if (ipv6) { 2068 m0->m_pkthdr.csum_flags = CSUM_L4_CALC | 2069 CSUM_L4_VALID; 2070 } else { 2071 m0->m_pkthdr.csum_flags = CSUM_L3_CALC | 2072 CSUM_L3_VALID | CSUM_L4_CALC | 2073 CSUM_L4_VALID; 2074 } 2075 } else { 2076 int outer_ipv6; 2077 2078 MPASS(m0->m_pkthdr.csum_data == 0xffff); 2079 2080 outer_ipv6 = tnlhdr_len >= 2081 sizeof(struct ether_header) + 2082 sizeof(struct ip6_hdr); 2083 m0->m_pkthdr.csum_flags = 2084 sw_csum_flags[outer_ipv6][ipv6]; 2085 } 2086 rxq->vxlan_rxcsum++; 2087 } 2088 } 2089 2090 if (cpl->vlan_ex) { 2091 m0->m_pkthdr.ether_vtag = be16toh(cpl->vlan); 2092 m0->m_flags |= M_VLANTAG; 2093 rxq->vlan_extraction++; 2094 } 2095 2096 if (rxq->iq.flags & IQ_RX_TIMESTAMP) { 2097 /* 2098 * Fill up rcv_tstmp but do not set M_TSTMP. 2099 * rcv_tstmp is not in the format that the 2100 * kernel expects and we don't want to mislead 2101 * it. For now this is only for custom code 2102 * that knows how to interpret cxgbe's stamp. 2103 */ 2104 m0->m_pkthdr.rcv_tstmp = 2105 last_flit_to_ns(sc, d->rsp.u.last_flit); 2106 #ifdef notyet 2107 m0->m_flags |= M_TSTMP; 2108 #endif 2109 } 2110 2111 #ifdef NUMA 2112 m0->m_pkthdr.numa_domain = ifp->if_numa_domain; 2113 #endif 2114 #if defined(INET) || defined(INET6) 2115 if (rxq->iq.flags & IQ_LRO_ENABLED && tnl_type == 0 && 2116 (M_HASHTYPE_GET(m0) == M_HASHTYPE_RSS_TCP_IPV4 || 2117 M_HASHTYPE_GET(m0) == M_HASHTYPE_RSS_TCP_IPV6)) { 2118 if (sort_before_lro(lro)) { 2119 tcp_lro_queue_mbuf(lro, m0); 2120 return (0); /* queued for sort, then LRO */ 2121 } 2122 if (tcp_lro_rx(lro, m0, 0) == 0) 2123 return (0); /* queued for LRO */ 2124 } 2125 #endif 2126 ifp->if_input(ifp, m0); 2127 2128 return (0); 2129 } 2130 2131 /* 2132 * Must drain the wrq or make sure that someone else will. 2133 */ 2134 static void 2135 wrq_tx_drain(void *arg, int n) 2136 { 2137 struct sge_wrq *wrq = arg; 2138 struct sge_eq *eq = &wrq->eq; 2139 2140 EQ_LOCK(eq); 2141 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 2142 drain_wrq_wr_list(wrq->adapter, wrq); 2143 EQ_UNLOCK(eq); 2144 } 2145 2146 static void 2147 drain_wrq_wr_list(struct adapter *sc, struct sge_wrq *wrq) 2148 { 2149 struct sge_eq *eq = &wrq->eq; 2150 u_int available, dbdiff; /* # of hardware descriptors */ 2151 u_int n; 2152 struct wrqe *wr; 2153 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */ 2154 2155 EQ_LOCK_ASSERT_OWNED(eq); 2156 MPASS(TAILQ_EMPTY(&wrq->incomplete_wrs)); 2157 wr = STAILQ_FIRST(&wrq->wr_list); 2158 MPASS(wr != NULL); /* Must be called with something useful to do */ 2159 MPASS(eq->pidx == eq->dbidx); 2160 dbdiff = 0; 2161 2162 do { 2163 eq->cidx = read_hw_cidx(eq); 2164 if (eq->pidx == eq->cidx) 2165 available = eq->sidx - 1; 2166 else 2167 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2168 2169 MPASS(wr->wrq == wrq); 2170 n = howmany(wr->wr_len, EQ_ESIZE); 2171 if (available < n) 2172 break; 2173 2174 dst = (void *)&eq->desc[eq->pidx]; 2175 if (__predict_true(eq->sidx - eq->pidx > n)) { 2176 /* Won't wrap, won't end exactly at the status page. */ 2177 bcopy(&wr->wr[0], dst, wr->wr_len); 2178 eq->pidx += n; 2179 } else { 2180 int first_portion = (eq->sidx - eq->pidx) * EQ_ESIZE; 2181 2182 bcopy(&wr->wr[0], dst, first_portion); 2183 if (wr->wr_len > first_portion) { 2184 bcopy(&wr->wr[first_portion], &eq->desc[0], 2185 wr->wr_len - first_portion); 2186 } 2187 eq->pidx = n - (eq->sidx - eq->pidx); 2188 } 2189 wrq->tx_wrs_copied++; 2190 2191 if (available < eq->sidx / 4 && 2192 atomic_cmpset_int(&eq->equiq, 0, 1)) { 2193 /* 2194 * XXX: This is not 100% reliable with some 2195 * types of WRs. But this is a very unusual 2196 * situation for an ofld/ctrl queue anyway. 2197 */ 2198 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ | 2199 F_FW_WR_EQUEQ); 2200 } 2201 2202 dbdiff += n; 2203 if (dbdiff >= 16) { 2204 ring_eq_db(sc, eq, dbdiff); 2205 dbdiff = 0; 2206 } 2207 2208 STAILQ_REMOVE_HEAD(&wrq->wr_list, link); 2209 free_wrqe(wr); 2210 MPASS(wrq->nwr_pending > 0); 2211 wrq->nwr_pending--; 2212 MPASS(wrq->ndesc_needed >= n); 2213 wrq->ndesc_needed -= n; 2214 } while ((wr = STAILQ_FIRST(&wrq->wr_list)) != NULL); 2215 2216 if (dbdiff) 2217 ring_eq_db(sc, eq, dbdiff); 2218 } 2219 2220 /* 2221 * Doesn't fail. Holds on to work requests it can't send right away. 2222 */ 2223 void 2224 t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, struct wrqe *wr) 2225 { 2226 #ifdef INVARIANTS 2227 struct sge_eq *eq = &wrq->eq; 2228 #endif 2229 2230 EQ_LOCK_ASSERT_OWNED(eq); 2231 MPASS(wr != NULL); 2232 MPASS(wr->wr_len > 0 && wr->wr_len <= SGE_MAX_WR_LEN); 2233 MPASS((wr->wr_len & 0x7) == 0); 2234 2235 STAILQ_INSERT_TAIL(&wrq->wr_list, wr, link); 2236 wrq->nwr_pending++; 2237 wrq->ndesc_needed += howmany(wr->wr_len, EQ_ESIZE); 2238 2239 if (!TAILQ_EMPTY(&wrq->incomplete_wrs)) 2240 return; /* commit_wrq_wr will drain wr_list as well. */ 2241 2242 drain_wrq_wr_list(sc, wrq); 2243 2244 /* Doorbell must have caught up to the pidx. */ 2245 MPASS(eq->pidx == eq->dbidx); 2246 } 2247 2248 void 2249 t4_update_fl_bufsize(struct ifnet *ifp) 2250 { 2251 struct vi_info *vi = ifp->if_softc; 2252 struct adapter *sc = vi->adapter; 2253 struct sge_rxq *rxq; 2254 #ifdef TCP_OFFLOAD 2255 struct sge_ofld_rxq *ofld_rxq; 2256 #endif 2257 struct sge_fl *fl; 2258 int i, maxp; 2259 2260 maxp = max_rx_payload(sc, ifp, false); 2261 for_each_rxq(vi, i, rxq) { 2262 fl = &rxq->fl; 2263 2264 FL_LOCK(fl); 2265 fl->zidx = find_refill_source(sc, maxp, 2266 fl->flags & FL_BUF_PACKING); 2267 FL_UNLOCK(fl); 2268 } 2269 #ifdef TCP_OFFLOAD 2270 maxp = max_rx_payload(sc, ifp, true); 2271 for_each_ofld_rxq(vi, i, ofld_rxq) { 2272 fl = &ofld_rxq->fl; 2273 2274 FL_LOCK(fl); 2275 fl->zidx = find_refill_source(sc, maxp, 2276 fl->flags & FL_BUF_PACKING); 2277 FL_UNLOCK(fl); 2278 } 2279 #endif 2280 } 2281 2282 static inline int 2283 mbuf_nsegs(struct mbuf *m) 2284 { 2285 2286 M_ASSERTPKTHDR(m); 2287 KASSERT(m->m_pkthdr.inner_l5hlen > 0, 2288 ("%s: mbuf %p missing information on # of segments.", __func__, m)); 2289 2290 return (m->m_pkthdr.inner_l5hlen); 2291 } 2292 2293 static inline void 2294 set_mbuf_nsegs(struct mbuf *m, uint8_t nsegs) 2295 { 2296 2297 M_ASSERTPKTHDR(m); 2298 m->m_pkthdr.inner_l5hlen = nsegs; 2299 } 2300 2301 static inline int 2302 mbuf_cflags(struct mbuf *m) 2303 { 2304 2305 M_ASSERTPKTHDR(m); 2306 return (m->m_pkthdr.PH_loc.eight[4]); 2307 } 2308 2309 static inline void 2310 set_mbuf_cflags(struct mbuf *m, uint8_t flags) 2311 { 2312 2313 M_ASSERTPKTHDR(m); 2314 m->m_pkthdr.PH_loc.eight[4] = flags; 2315 } 2316 2317 static inline int 2318 mbuf_len16(struct mbuf *m) 2319 { 2320 int n; 2321 2322 M_ASSERTPKTHDR(m); 2323 n = m->m_pkthdr.PH_loc.eight[0]; 2324 if (!(mbuf_cflags(m) & MC_TLS)) 2325 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16); 2326 2327 return (n); 2328 } 2329 2330 static inline void 2331 set_mbuf_len16(struct mbuf *m, uint8_t len16) 2332 { 2333 2334 M_ASSERTPKTHDR(m); 2335 if (!(mbuf_cflags(m) & MC_TLS)) 2336 MPASS(len16 > 0 && len16 <= SGE_MAX_WR_LEN / 16); 2337 m->m_pkthdr.PH_loc.eight[0] = len16; 2338 } 2339 2340 #ifdef RATELIMIT 2341 static inline int 2342 mbuf_eo_nsegs(struct mbuf *m) 2343 { 2344 2345 M_ASSERTPKTHDR(m); 2346 return (m->m_pkthdr.PH_loc.eight[1]); 2347 } 2348 2349 static inline void 2350 set_mbuf_eo_nsegs(struct mbuf *m, uint8_t nsegs) 2351 { 2352 2353 M_ASSERTPKTHDR(m); 2354 m->m_pkthdr.PH_loc.eight[1] = nsegs; 2355 } 2356 2357 static inline int 2358 mbuf_eo_len16(struct mbuf *m) 2359 { 2360 int n; 2361 2362 M_ASSERTPKTHDR(m); 2363 n = m->m_pkthdr.PH_loc.eight[2]; 2364 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16); 2365 2366 return (n); 2367 } 2368 2369 static inline void 2370 set_mbuf_eo_len16(struct mbuf *m, uint8_t len16) 2371 { 2372 2373 M_ASSERTPKTHDR(m); 2374 m->m_pkthdr.PH_loc.eight[2] = len16; 2375 } 2376 2377 static inline int 2378 mbuf_eo_tsclk_tsoff(struct mbuf *m) 2379 { 2380 2381 M_ASSERTPKTHDR(m); 2382 return (m->m_pkthdr.PH_loc.eight[3]); 2383 } 2384 2385 static inline void 2386 set_mbuf_eo_tsclk_tsoff(struct mbuf *m, uint8_t tsclk_tsoff) 2387 { 2388 2389 M_ASSERTPKTHDR(m); 2390 m->m_pkthdr.PH_loc.eight[3] = tsclk_tsoff; 2391 } 2392 2393 static inline int 2394 needs_eo(struct m_snd_tag *mst) 2395 { 2396 2397 return (mst != NULL && mst->type == IF_SND_TAG_TYPE_RATE_LIMIT); 2398 } 2399 #endif 2400 2401 /* 2402 * Try to allocate an mbuf to contain a raw work request. To make it 2403 * easy to construct the work request, don't allocate a chain but a 2404 * single mbuf. 2405 */ 2406 struct mbuf * 2407 alloc_wr_mbuf(int len, int how) 2408 { 2409 struct mbuf *m; 2410 2411 if (len <= MHLEN) 2412 m = m_gethdr(how, MT_DATA); 2413 else if (len <= MCLBYTES) 2414 m = m_getcl(how, MT_DATA, M_PKTHDR); 2415 else 2416 m = NULL; 2417 if (m == NULL) 2418 return (NULL); 2419 m->m_pkthdr.len = len; 2420 m->m_len = len; 2421 set_mbuf_cflags(m, MC_RAW_WR); 2422 set_mbuf_len16(m, howmany(len, 16)); 2423 return (m); 2424 } 2425 2426 static inline bool 2427 needs_hwcsum(struct mbuf *m) 2428 { 2429 const uint32_t csum_flags = CSUM_IP | CSUM_IP_UDP | CSUM_IP_TCP | 2430 CSUM_IP_TSO | CSUM_INNER_IP | CSUM_INNER_IP_UDP | 2431 CSUM_INNER_IP_TCP | CSUM_INNER_IP_TSO | CSUM_IP6_UDP | 2432 CSUM_IP6_TCP | CSUM_IP6_TSO | CSUM_INNER_IP6_UDP | 2433 CSUM_INNER_IP6_TCP | CSUM_INNER_IP6_TSO; 2434 2435 M_ASSERTPKTHDR(m); 2436 2437 return (m->m_pkthdr.csum_flags & csum_flags); 2438 } 2439 2440 static inline bool 2441 needs_tso(struct mbuf *m) 2442 { 2443 const uint32_t csum_flags = CSUM_IP_TSO | CSUM_IP6_TSO | 2444 CSUM_INNER_IP_TSO | CSUM_INNER_IP6_TSO; 2445 2446 M_ASSERTPKTHDR(m); 2447 2448 return (m->m_pkthdr.csum_flags & csum_flags); 2449 } 2450 2451 static inline bool 2452 needs_vxlan_csum(struct mbuf *m) 2453 { 2454 2455 M_ASSERTPKTHDR(m); 2456 2457 return (m->m_pkthdr.csum_flags & CSUM_ENCAP_VXLAN); 2458 } 2459 2460 static inline bool 2461 needs_vxlan_tso(struct mbuf *m) 2462 { 2463 const uint32_t csum_flags = CSUM_ENCAP_VXLAN | CSUM_INNER_IP_TSO | 2464 CSUM_INNER_IP6_TSO; 2465 2466 M_ASSERTPKTHDR(m); 2467 2468 return ((m->m_pkthdr.csum_flags & csum_flags) != 0 && 2469 (m->m_pkthdr.csum_flags & csum_flags) != CSUM_ENCAP_VXLAN); 2470 } 2471 2472 static inline bool 2473 needs_inner_tcp_csum(struct mbuf *m) 2474 { 2475 const uint32_t csum_flags = CSUM_INNER_IP_TSO | CSUM_INNER_IP6_TSO; 2476 2477 M_ASSERTPKTHDR(m); 2478 2479 return (m->m_pkthdr.csum_flags & csum_flags); 2480 } 2481 2482 static inline bool 2483 needs_l3_csum(struct mbuf *m) 2484 { 2485 const uint32_t csum_flags = CSUM_IP | CSUM_IP_TSO | CSUM_INNER_IP | 2486 CSUM_INNER_IP_TSO; 2487 2488 M_ASSERTPKTHDR(m); 2489 2490 return (m->m_pkthdr.csum_flags & csum_flags); 2491 } 2492 2493 static inline bool 2494 needs_outer_tcp_csum(struct mbuf *m) 2495 { 2496 const uint32_t csum_flags = CSUM_IP_TCP | CSUM_IP_TSO | CSUM_IP6_TCP | 2497 CSUM_IP6_TSO; 2498 2499 M_ASSERTPKTHDR(m); 2500 2501 return (m->m_pkthdr.csum_flags & csum_flags); 2502 } 2503 2504 #ifdef RATELIMIT 2505 static inline bool 2506 needs_outer_l4_csum(struct mbuf *m) 2507 { 2508 const uint32_t csum_flags = CSUM_IP_UDP | CSUM_IP_TCP | CSUM_IP_TSO | 2509 CSUM_IP6_UDP | CSUM_IP6_TCP | CSUM_IP6_TSO; 2510 2511 M_ASSERTPKTHDR(m); 2512 2513 return (m->m_pkthdr.csum_flags & csum_flags); 2514 } 2515 2516 static inline bool 2517 needs_outer_udp_csum(struct mbuf *m) 2518 { 2519 const uint32_t csum_flags = CSUM_IP_UDP | CSUM_IP6_UDP; 2520 2521 M_ASSERTPKTHDR(m); 2522 2523 return (m->m_pkthdr.csum_flags & csum_flags); 2524 } 2525 #endif 2526 2527 static inline bool 2528 needs_vlan_insertion(struct mbuf *m) 2529 { 2530 2531 M_ASSERTPKTHDR(m); 2532 2533 return (m->m_flags & M_VLANTAG); 2534 } 2535 2536 static void * 2537 m_advance(struct mbuf **pm, int *poffset, int len) 2538 { 2539 struct mbuf *m = *pm; 2540 int offset = *poffset; 2541 uintptr_t p = 0; 2542 2543 MPASS(len > 0); 2544 2545 for (;;) { 2546 if (offset + len < m->m_len) { 2547 offset += len; 2548 p = mtod(m, uintptr_t) + offset; 2549 break; 2550 } 2551 len -= m->m_len - offset; 2552 m = m->m_next; 2553 offset = 0; 2554 MPASS(m != NULL); 2555 } 2556 *poffset = offset; 2557 *pm = m; 2558 return ((void *)p); 2559 } 2560 2561 static inline int 2562 count_mbuf_ext_pgs(struct mbuf *m, int skip, vm_paddr_t *nextaddr) 2563 { 2564 vm_paddr_t paddr; 2565 int i, len, off, pglen, pgoff, seglen, segoff; 2566 int nsegs = 0; 2567 2568 M_ASSERTEXTPG(m); 2569 off = mtod(m, vm_offset_t); 2570 len = m->m_len; 2571 off += skip; 2572 len -= skip; 2573 2574 if (m->m_epg_hdrlen != 0) { 2575 if (off >= m->m_epg_hdrlen) { 2576 off -= m->m_epg_hdrlen; 2577 } else { 2578 seglen = m->m_epg_hdrlen - off; 2579 segoff = off; 2580 seglen = min(seglen, len); 2581 off = 0; 2582 len -= seglen; 2583 paddr = pmap_kextract( 2584 (vm_offset_t)&m->m_epg_hdr[segoff]); 2585 if (*nextaddr != paddr) 2586 nsegs++; 2587 *nextaddr = paddr + seglen; 2588 } 2589 } 2590 pgoff = m->m_epg_1st_off; 2591 for (i = 0; i < m->m_epg_npgs && len > 0; i++) { 2592 pglen = m_epg_pagelen(m, i, pgoff); 2593 if (off >= pglen) { 2594 off -= pglen; 2595 pgoff = 0; 2596 continue; 2597 } 2598 seglen = pglen - off; 2599 segoff = pgoff + off; 2600 off = 0; 2601 seglen = min(seglen, len); 2602 len -= seglen; 2603 paddr = m->m_epg_pa[i] + segoff; 2604 if (*nextaddr != paddr) 2605 nsegs++; 2606 *nextaddr = paddr + seglen; 2607 pgoff = 0; 2608 }; 2609 if (len != 0) { 2610 seglen = min(len, m->m_epg_trllen - off); 2611 len -= seglen; 2612 paddr = pmap_kextract((vm_offset_t)&m->m_epg_trail[off]); 2613 if (*nextaddr != paddr) 2614 nsegs++; 2615 *nextaddr = paddr + seglen; 2616 } 2617 2618 return (nsegs); 2619 } 2620 2621 2622 /* 2623 * Can deal with empty mbufs in the chain that have m_len = 0, but the chain 2624 * must have at least one mbuf that's not empty. It is possible for this 2625 * routine to return 0 if skip accounts for all the contents of the mbuf chain. 2626 */ 2627 static inline int 2628 count_mbuf_nsegs(struct mbuf *m, int skip, uint8_t *cflags) 2629 { 2630 vm_paddr_t nextaddr, paddr; 2631 vm_offset_t va; 2632 int len, nsegs; 2633 2634 M_ASSERTPKTHDR(m); 2635 MPASS(m->m_pkthdr.len > 0); 2636 MPASS(m->m_pkthdr.len >= skip); 2637 2638 nsegs = 0; 2639 nextaddr = 0; 2640 for (; m; m = m->m_next) { 2641 len = m->m_len; 2642 if (__predict_false(len == 0)) 2643 continue; 2644 if (skip >= len) { 2645 skip -= len; 2646 continue; 2647 } 2648 if ((m->m_flags & M_EXTPG) != 0) { 2649 *cflags |= MC_NOMAP; 2650 nsegs += count_mbuf_ext_pgs(m, skip, &nextaddr); 2651 skip = 0; 2652 continue; 2653 } 2654 va = mtod(m, vm_offset_t) + skip; 2655 len -= skip; 2656 skip = 0; 2657 paddr = pmap_kextract(va); 2658 nsegs += sglist_count((void *)(uintptr_t)va, len); 2659 if (paddr == nextaddr) 2660 nsegs--; 2661 nextaddr = pmap_kextract(va + len - 1) + 1; 2662 } 2663 2664 return (nsegs); 2665 } 2666 2667 /* 2668 * The maximum number of segments that can fit in a WR. 2669 */ 2670 static int 2671 max_nsegs_allowed(struct mbuf *m, bool vm_wr) 2672 { 2673 2674 if (vm_wr) { 2675 if (needs_tso(m)) 2676 return (TX_SGL_SEGS_VM_TSO); 2677 return (TX_SGL_SEGS_VM); 2678 } 2679 2680 if (needs_tso(m)) { 2681 if (needs_vxlan_tso(m)) 2682 return (TX_SGL_SEGS_VXLAN_TSO); 2683 else 2684 return (TX_SGL_SEGS_TSO); 2685 } 2686 2687 return (TX_SGL_SEGS); 2688 } 2689 2690 /* 2691 * Analyze the mbuf to determine its tx needs. The mbuf passed in may change: 2692 * a) caller can assume it's been freed if this function returns with an error. 2693 * b) it may get defragged up if the gather list is too long for the hardware. 2694 */ 2695 int 2696 parse_pkt(struct mbuf **mp, bool vm_wr) 2697 { 2698 struct mbuf *m0 = *mp, *m; 2699 int rc, nsegs, defragged = 0, offset; 2700 struct ether_header *eh; 2701 void *l3hdr; 2702 #if defined(INET) || defined(INET6) 2703 struct tcphdr *tcp; 2704 #endif 2705 #if defined(KERN_TLS) || defined(RATELIMIT) 2706 struct m_snd_tag *mst; 2707 #endif 2708 uint16_t eh_type; 2709 uint8_t cflags; 2710 2711 cflags = 0; 2712 M_ASSERTPKTHDR(m0); 2713 if (__predict_false(m0->m_pkthdr.len < ETHER_HDR_LEN)) { 2714 rc = EINVAL; 2715 fail: 2716 m_freem(m0); 2717 *mp = NULL; 2718 return (rc); 2719 } 2720 restart: 2721 /* 2722 * First count the number of gather list segments in the payload. 2723 * Defrag the mbuf if nsegs exceeds the hardware limit. 2724 */ 2725 M_ASSERTPKTHDR(m0); 2726 MPASS(m0->m_pkthdr.len > 0); 2727 nsegs = count_mbuf_nsegs(m0, 0, &cflags); 2728 #if defined(KERN_TLS) || defined(RATELIMIT) 2729 if (m0->m_pkthdr.csum_flags & CSUM_SND_TAG) 2730 mst = m0->m_pkthdr.snd_tag; 2731 else 2732 mst = NULL; 2733 #endif 2734 #ifdef KERN_TLS 2735 if (mst != NULL && mst->type == IF_SND_TAG_TYPE_TLS) { 2736 int len16; 2737 2738 cflags |= MC_TLS; 2739 set_mbuf_cflags(m0, cflags); 2740 rc = t6_ktls_parse_pkt(m0, &nsegs, &len16); 2741 if (rc != 0) 2742 goto fail; 2743 set_mbuf_nsegs(m0, nsegs); 2744 set_mbuf_len16(m0, len16); 2745 return (0); 2746 } 2747 #endif 2748 if (nsegs > max_nsegs_allowed(m0, vm_wr)) { 2749 if (defragged++ > 0) { 2750 rc = EFBIG; 2751 goto fail; 2752 } 2753 counter_u64_add(defrags, 1); 2754 if ((m = m_defrag(m0, M_NOWAIT)) == NULL) { 2755 rc = ENOMEM; 2756 goto fail; 2757 } 2758 *mp = m0 = m; /* update caller's copy after defrag */ 2759 goto restart; 2760 } 2761 2762 if (__predict_false(nsegs > 2 && m0->m_pkthdr.len <= MHLEN && 2763 !(cflags & MC_NOMAP))) { 2764 counter_u64_add(pullups, 1); 2765 m0 = m_pullup(m0, m0->m_pkthdr.len); 2766 if (m0 == NULL) { 2767 /* Should have left well enough alone. */ 2768 rc = EFBIG; 2769 goto fail; 2770 } 2771 *mp = m0; /* update caller's copy after pullup */ 2772 goto restart; 2773 } 2774 set_mbuf_nsegs(m0, nsegs); 2775 set_mbuf_cflags(m0, cflags); 2776 calculate_mbuf_len16(m0, vm_wr); 2777 2778 #ifdef RATELIMIT 2779 /* 2780 * Ethofld is limited to TCP and UDP for now, and only when L4 hw 2781 * checksumming is enabled. needs_outer_l4_csum happens to check for 2782 * all the right things. 2783 */ 2784 if (__predict_false(needs_eo(mst) && !needs_outer_l4_csum(m0))) { 2785 m_snd_tag_rele(m0->m_pkthdr.snd_tag); 2786 m0->m_pkthdr.snd_tag = NULL; 2787 m0->m_pkthdr.csum_flags &= ~CSUM_SND_TAG; 2788 mst = NULL; 2789 } 2790 #endif 2791 2792 if (!needs_hwcsum(m0) 2793 #ifdef RATELIMIT 2794 && !needs_eo(mst) 2795 #endif 2796 ) 2797 return (0); 2798 2799 m = m0; 2800 eh = mtod(m, struct ether_header *); 2801 eh_type = ntohs(eh->ether_type); 2802 if (eh_type == ETHERTYPE_VLAN) { 2803 struct ether_vlan_header *evh = (void *)eh; 2804 2805 eh_type = ntohs(evh->evl_proto); 2806 m0->m_pkthdr.l2hlen = sizeof(*evh); 2807 } else 2808 m0->m_pkthdr.l2hlen = sizeof(*eh); 2809 2810 offset = 0; 2811 l3hdr = m_advance(&m, &offset, m0->m_pkthdr.l2hlen); 2812 2813 switch (eh_type) { 2814 #ifdef INET6 2815 case ETHERTYPE_IPV6: 2816 m0->m_pkthdr.l3hlen = sizeof(struct ip6_hdr); 2817 break; 2818 #endif 2819 #ifdef INET 2820 case ETHERTYPE_IP: 2821 { 2822 struct ip *ip = l3hdr; 2823 2824 if (needs_vxlan_csum(m0)) { 2825 /* Driver will do the outer IP hdr checksum. */ 2826 ip->ip_sum = 0; 2827 if (needs_vxlan_tso(m0)) { 2828 const uint16_t ipl = ip->ip_len; 2829 2830 ip->ip_len = 0; 2831 ip->ip_sum = ~in_cksum_hdr(ip); 2832 ip->ip_len = ipl; 2833 } else 2834 ip->ip_sum = in_cksum_hdr(ip); 2835 } 2836 m0->m_pkthdr.l3hlen = ip->ip_hl << 2; 2837 break; 2838 } 2839 #endif 2840 default: 2841 panic("%s: ethertype 0x%04x unknown. if_cxgbe must be compiled" 2842 " with the same INET/INET6 options as the kernel.", 2843 __func__, eh_type); 2844 } 2845 2846 if (needs_vxlan_csum(m0)) { 2847 m0->m_pkthdr.l4hlen = sizeof(struct udphdr); 2848 m0->m_pkthdr.l5hlen = sizeof(struct vxlan_header); 2849 2850 /* Inner headers. */ 2851 eh = m_advance(&m, &offset, m0->m_pkthdr.l3hlen + 2852 sizeof(struct udphdr) + sizeof(struct vxlan_header)); 2853 eh_type = ntohs(eh->ether_type); 2854 if (eh_type == ETHERTYPE_VLAN) { 2855 struct ether_vlan_header *evh = (void *)eh; 2856 2857 eh_type = ntohs(evh->evl_proto); 2858 m0->m_pkthdr.inner_l2hlen = sizeof(*evh); 2859 } else 2860 m0->m_pkthdr.inner_l2hlen = sizeof(*eh); 2861 l3hdr = m_advance(&m, &offset, m0->m_pkthdr.inner_l2hlen); 2862 2863 switch (eh_type) { 2864 #ifdef INET6 2865 case ETHERTYPE_IPV6: 2866 m0->m_pkthdr.inner_l3hlen = sizeof(struct ip6_hdr); 2867 break; 2868 #endif 2869 #ifdef INET 2870 case ETHERTYPE_IP: 2871 { 2872 struct ip *ip = l3hdr; 2873 2874 m0->m_pkthdr.inner_l3hlen = ip->ip_hl << 2; 2875 break; 2876 } 2877 #endif 2878 default: 2879 panic("%s: VXLAN hw offload requested with unknown " 2880 "ethertype 0x%04x. if_cxgbe must be compiled" 2881 " with the same INET/INET6 options as the kernel.", 2882 __func__, eh_type); 2883 } 2884 #if defined(INET) || defined(INET6) 2885 if (needs_inner_tcp_csum(m0)) { 2886 tcp = m_advance(&m, &offset, m0->m_pkthdr.inner_l3hlen); 2887 m0->m_pkthdr.inner_l4hlen = tcp->th_off * 4; 2888 } 2889 #endif 2890 MPASS((m0->m_pkthdr.csum_flags & CSUM_SND_TAG) == 0); 2891 m0->m_pkthdr.csum_flags &= CSUM_INNER_IP6_UDP | 2892 CSUM_INNER_IP6_TCP | CSUM_INNER_IP6_TSO | CSUM_INNER_IP | 2893 CSUM_INNER_IP_UDP | CSUM_INNER_IP_TCP | CSUM_INNER_IP_TSO | 2894 CSUM_ENCAP_VXLAN; 2895 } 2896 2897 #if defined(INET) || defined(INET6) 2898 if (needs_outer_tcp_csum(m0)) { 2899 tcp = m_advance(&m, &offset, m0->m_pkthdr.l3hlen); 2900 m0->m_pkthdr.l4hlen = tcp->th_off * 4; 2901 #ifdef RATELIMIT 2902 if (tsclk >= 0 && *(uint32_t *)(tcp + 1) == ntohl(0x0101080a)) { 2903 set_mbuf_eo_tsclk_tsoff(m0, 2904 V_FW_ETH_TX_EO_WR_TSCLK(tsclk) | 2905 V_FW_ETH_TX_EO_WR_TSOFF(sizeof(*tcp) / 2 + 1)); 2906 } else 2907 set_mbuf_eo_tsclk_tsoff(m0, 0); 2908 } else if (needs_outer_udp_csum(m0)) { 2909 m0->m_pkthdr.l4hlen = sizeof(struct udphdr); 2910 #endif 2911 } 2912 #ifdef RATELIMIT 2913 if (needs_eo(mst)) { 2914 u_int immhdrs; 2915 2916 /* EO WRs have the headers in the WR and not the GL. */ 2917 immhdrs = m0->m_pkthdr.l2hlen + m0->m_pkthdr.l3hlen + 2918 m0->m_pkthdr.l4hlen; 2919 cflags = 0; 2920 nsegs = count_mbuf_nsegs(m0, immhdrs, &cflags); 2921 MPASS(cflags == mbuf_cflags(m0)); 2922 set_mbuf_eo_nsegs(m0, nsegs); 2923 set_mbuf_eo_len16(m0, 2924 txpkt_eo_len16(nsegs, immhdrs, needs_tso(m0))); 2925 } 2926 #endif 2927 #endif 2928 MPASS(m0 == *mp); 2929 return (0); 2930 } 2931 2932 void * 2933 start_wrq_wr(struct sge_wrq *wrq, int len16, struct wrq_cookie *cookie) 2934 { 2935 struct sge_eq *eq = &wrq->eq; 2936 struct adapter *sc = wrq->adapter; 2937 int ndesc, available; 2938 struct wrqe *wr; 2939 void *w; 2940 2941 MPASS(len16 > 0); 2942 ndesc = tx_len16_to_desc(len16); 2943 MPASS(ndesc > 0 && ndesc <= SGE_MAX_WR_NDESC); 2944 2945 EQ_LOCK(eq); 2946 2947 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 2948 drain_wrq_wr_list(sc, wrq); 2949 2950 if (!STAILQ_EMPTY(&wrq->wr_list)) { 2951 slowpath: 2952 EQ_UNLOCK(eq); 2953 wr = alloc_wrqe(len16 * 16, wrq); 2954 if (__predict_false(wr == NULL)) 2955 return (NULL); 2956 cookie->pidx = -1; 2957 cookie->ndesc = ndesc; 2958 return (&wr->wr); 2959 } 2960 2961 eq->cidx = read_hw_cidx(eq); 2962 if (eq->pidx == eq->cidx) 2963 available = eq->sidx - 1; 2964 else 2965 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2966 if (available < ndesc) 2967 goto slowpath; 2968 2969 cookie->pidx = eq->pidx; 2970 cookie->ndesc = ndesc; 2971 TAILQ_INSERT_TAIL(&wrq->incomplete_wrs, cookie, link); 2972 2973 w = &eq->desc[eq->pidx]; 2974 IDXINCR(eq->pidx, ndesc, eq->sidx); 2975 if (__predict_false(cookie->pidx + ndesc > eq->sidx)) { 2976 w = &wrq->ss[0]; 2977 wrq->ss_pidx = cookie->pidx; 2978 wrq->ss_len = len16 * 16; 2979 } 2980 2981 EQ_UNLOCK(eq); 2982 2983 return (w); 2984 } 2985 2986 void 2987 commit_wrq_wr(struct sge_wrq *wrq, void *w, struct wrq_cookie *cookie) 2988 { 2989 struct sge_eq *eq = &wrq->eq; 2990 struct adapter *sc = wrq->adapter; 2991 int ndesc, pidx; 2992 struct wrq_cookie *prev, *next; 2993 2994 if (cookie->pidx == -1) { 2995 struct wrqe *wr = __containerof(w, struct wrqe, wr); 2996 2997 t4_wrq_tx(sc, wr); 2998 return; 2999 } 3000 3001 if (__predict_false(w == &wrq->ss[0])) { 3002 int n = (eq->sidx - wrq->ss_pidx) * EQ_ESIZE; 3003 3004 MPASS(wrq->ss_len > n); /* WR had better wrap around. */ 3005 bcopy(&wrq->ss[0], &eq->desc[wrq->ss_pidx], n); 3006 bcopy(&wrq->ss[n], &eq->desc[0], wrq->ss_len - n); 3007 wrq->tx_wrs_ss++; 3008 } else 3009 wrq->tx_wrs_direct++; 3010 3011 EQ_LOCK(eq); 3012 ndesc = cookie->ndesc; /* Can be more than SGE_MAX_WR_NDESC here. */ 3013 pidx = cookie->pidx; 3014 MPASS(pidx >= 0 && pidx < eq->sidx); 3015 prev = TAILQ_PREV(cookie, wrq_incomplete_wrs, link); 3016 next = TAILQ_NEXT(cookie, link); 3017 if (prev == NULL) { 3018 MPASS(pidx == eq->dbidx); 3019 if (next == NULL || ndesc >= 16) { 3020 int available; 3021 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */ 3022 3023 /* 3024 * Note that the WR via which we'll request tx updates 3025 * is at pidx and not eq->pidx, which has moved on 3026 * already. 3027 */ 3028 dst = (void *)&eq->desc[pidx]; 3029 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 3030 if (available < eq->sidx / 4 && 3031 atomic_cmpset_int(&eq->equiq, 0, 1)) { 3032 /* 3033 * XXX: This is not 100% reliable with some 3034 * types of WRs. But this is a very unusual 3035 * situation for an ofld/ctrl queue anyway. 3036 */ 3037 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ | 3038 F_FW_WR_EQUEQ); 3039 } 3040 3041 ring_eq_db(wrq->adapter, eq, ndesc); 3042 } else { 3043 MPASS(IDXDIFF(next->pidx, pidx, eq->sidx) == ndesc); 3044 next->pidx = pidx; 3045 next->ndesc += ndesc; 3046 } 3047 } else { 3048 MPASS(IDXDIFF(pidx, prev->pidx, eq->sidx) == prev->ndesc); 3049 prev->ndesc += ndesc; 3050 } 3051 TAILQ_REMOVE(&wrq->incomplete_wrs, cookie, link); 3052 3053 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 3054 drain_wrq_wr_list(sc, wrq); 3055 3056 #ifdef INVARIANTS 3057 if (TAILQ_EMPTY(&wrq->incomplete_wrs)) { 3058 /* Doorbell must have caught up to the pidx. */ 3059 MPASS(wrq->eq.pidx == wrq->eq.dbidx); 3060 } 3061 #endif 3062 EQ_UNLOCK(eq); 3063 } 3064 3065 static u_int 3066 can_resume_eth_tx(struct mp_ring *r) 3067 { 3068 struct sge_eq *eq = r->cookie; 3069 3070 return (total_available_tx_desc(eq) > eq->sidx / 8); 3071 } 3072 3073 static inline bool 3074 cannot_use_txpkts(struct mbuf *m) 3075 { 3076 /* maybe put a GL limit too, to avoid silliness? */ 3077 3078 return (needs_tso(m) || (mbuf_cflags(m) & (MC_RAW_WR | MC_TLS)) != 0); 3079 } 3080 3081 static inline int 3082 discard_tx(struct sge_eq *eq) 3083 { 3084 3085 return ((eq->flags & (EQ_ENABLED | EQ_QFLUSH)) != EQ_ENABLED); 3086 } 3087 3088 static inline int 3089 wr_can_update_eq(void *p) 3090 { 3091 struct fw_eth_tx_pkts_wr *wr = p; 3092 3093 switch (G_FW_WR_OP(be32toh(wr->op_pkd))) { 3094 case FW_ULPTX_WR: 3095 case FW_ETH_TX_PKT_WR: 3096 case FW_ETH_TX_PKTS_WR: 3097 case FW_ETH_TX_PKTS2_WR: 3098 case FW_ETH_TX_PKT_VM_WR: 3099 case FW_ETH_TX_PKTS_VM_WR: 3100 return (1); 3101 default: 3102 return (0); 3103 } 3104 } 3105 3106 static inline void 3107 set_txupdate_flags(struct sge_txq *txq, u_int avail, 3108 struct fw_eth_tx_pkt_wr *wr) 3109 { 3110 struct sge_eq *eq = &txq->eq; 3111 struct txpkts *txp = &txq->txp; 3112 3113 if ((txp->npkt > 0 || avail < eq->sidx / 2) && 3114 atomic_cmpset_int(&eq->equiq, 0, 1)) { 3115 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ | F_FW_WR_EQUIQ); 3116 eq->equeqidx = eq->pidx; 3117 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 32) { 3118 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ); 3119 eq->equeqidx = eq->pidx; 3120 } 3121 } 3122 3123 /* 3124 * r->items[cidx] to r->items[pidx], with a wraparound at r->size, are ready to 3125 * be consumed. Return the actual number consumed. 0 indicates a stall. 3126 */ 3127 static u_int 3128 eth_tx(struct mp_ring *r, u_int cidx, u_int pidx, bool *coalescing) 3129 { 3130 struct sge_txq *txq = r->cookie; 3131 struct ifnet *ifp = txq->ifp; 3132 struct sge_eq *eq = &txq->eq; 3133 struct txpkts *txp = &txq->txp; 3134 struct vi_info *vi = ifp->if_softc; 3135 struct adapter *sc = vi->adapter; 3136 u_int total, remaining; /* # of packets */ 3137 u_int n, avail, dbdiff; /* # of hardware descriptors */ 3138 int i, rc; 3139 struct mbuf *m0; 3140 bool snd; 3141 void *wr; /* start of the last WR written to the ring */ 3142 3143 TXQ_LOCK_ASSERT_OWNED(txq); 3144 3145 remaining = IDXDIFF(pidx, cidx, r->size); 3146 if (__predict_false(discard_tx(eq))) { 3147 for (i = 0; i < txp->npkt; i++) 3148 m_freem(txp->mb[i]); 3149 txp->npkt = 0; 3150 while (cidx != pidx) { 3151 m0 = r->items[cidx]; 3152 m_freem(m0); 3153 if (++cidx == r->size) 3154 cidx = 0; 3155 } 3156 reclaim_tx_descs(txq, eq->sidx); 3157 *coalescing = false; 3158 return (remaining); /* emptied */ 3159 } 3160 3161 /* How many hardware descriptors do we have readily available. */ 3162 if (eq->pidx == eq->cidx) { 3163 avail = eq->sidx - 1; 3164 if (txp->score++ >= 5) 3165 txp->score = 5; /* tx is completely idle, reset. */ 3166 } else 3167 avail = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 3168 3169 total = 0; 3170 if (remaining == 0) { 3171 if (txp->score-- == 1) /* egr_update had to drain txpkts */ 3172 txp->score = 1; 3173 goto send_txpkts; 3174 } 3175 3176 dbdiff = 0; 3177 MPASS(remaining > 0); 3178 while (remaining > 0) { 3179 m0 = r->items[cidx]; 3180 M_ASSERTPKTHDR(m0); 3181 MPASS(m0->m_nextpkt == NULL); 3182 3183 if (avail < 2 * SGE_MAX_WR_NDESC) 3184 avail += reclaim_tx_descs(txq, 64); 3185 3186 if (txp->npkt > 0 || remaining > 1 || txp->score > 3 || 3187 atomic_load_int(&txq->eq.equiq) != 0) { 3188 if (vi->flags & TX_USES_VM_WR) 3189 rc = add_to_txpkts_vf(sc, txq, m0, avail, &snd); 3190 else 3191 rc = add_to_txpkts_pf(sc, txq, m0, avail, &snd); 3192 } else { 3193 snd = false; 3194 rc = EINVAL; 3195 } 3196 if (snd) { 3197 MPASS(txp->npkt > 0); 3198 for (i = 0; i < txp->npkt; i++) 3199 ETHER_BPF_MTAP(ifp, txp->mb[i]); 3200 if (txp->npkt > 1) { 3201 if (txp->score++ >= 10) 3202 txp->score = 10; 3203 MPASS(avail >= tx_len16_to_desc(txp->len16)); 3204 if (vi->flags & TX_USES_VM_WR) 3205 n = write_txpkts_vm_wr(sc, txq); 3206 else 3207 n = write_txpkts_wr(sc, txq); 3208 } else { 3209 MPASS(avail >= 3210 tx_len16_to_desc(mbuf_len16(txp->mb[0]))); 3211 if (vi->flags & TX_USES_VM_WR) 3212 n = write_txpkt_vm_wr(sc, txq, 3213 txp->mb[0]); 3214 else 3215 n = write_txpkt_wr(sc, txq, txp->mb[0], 3216 avail); 3217 } 3218 MPASS(n <= SGE_MAX_WR_NDESC); 3219 avail -= n; 3220 dbdiff += n; 3221 wr = &eq->desc[eq->pidx]; 3222 IDXINCR(eq->pidx, n, eq->sidx); 3223 txp->npkt = 0; /* emptied */ 3224 } 3225 if (rc == 0) { 3226 /* m0 was coalesced into txq->txpkts. */ 3227 goto next_mbuf; 3228 } 3229 if (rc == EAGAIN) { 3230 /* 3231 * m0 is suitable for tx coalescing but could not be 3232 * combined with the existing txq->txpkts, which has now 3233 * been transmitted. Start a new txpkts with m0. 3234 */ 3235 MPASS(snd); 3236 MPASS(txp->npkt == 0); 3237 continue; 3238 } 3239 3240 MPASS(rc != 0 && rc != EAGAIN); 3241 MPASS(txp->npkt == 0); 3242 3243 n = tx_len16_to_desc(mbuf_len16(m0)); 3244 if (__predict_false(avail < n)) { 3245 avail += reclaim_tx_descs(txq, min(n, 32)); 3246 if (avail < n) 3247 break; /* out of descriptors */ 3248 } 3249 3250 wr = &eq->desc[eq->pidx]; 3251 if (mbuf_cflags(m0) & MC_RAW_WR) { 3252 n = write_raw_wr(txq, wr, m0, avail); 3253 #ifdef KERN_TLS 3254 } else if (mbuf_cflags(m0) & MC_TLS) { 3255 ETHER_BPF_MTAP(ifp, m0); 3256 n = t6_ktls_write_wr(txq, wr, m0, mbuf_nsegs(m0), 3257 avail); 3258 #endif 3259 } else { 3260 ETHER_BPF_MTAP(ifp, m0); 3261 if (vi->flags & TX_USES_VM_WR) 3262 n = write_txpkt_vm_wr(sc, txq, m0); 3263 else 3264 n = write_txpkt_wr(sc, txq, m0, avail); 3265 } 3266 MPASS(n >= 1 && n <= avail); 3267 if (!(mbuf_cflags(m0) & MC_TLS)) 3268 MPASS(n <= SGE_MAX_WR_NDESC); 3269 3270 avail -= n; 3271 dbdiff += n; 3272 IDXINCR(eq->pidx, n, eq->sidx); 3273 3274 if (dbdiff >= 512 / EQ_ESIZE) { /* X_FETCHBURSTMAX_512B */ 3275 if (wr_can_update_eq(wr)) 3276 set_txupdate_flags(txq, avail, wr); 3277 ring_eq_db(sc, eq, dbdiff); 3278 avail += reclaim_tx_descs(txq, 32); 3279 dbdiff = 0; 3280 } 3281 next_mbuf: 3282 total++; 3283 remaining--; 3284 if (__predict_false(++cidx == r->size)) 3285 cidx = 0; 3286 } 3287 if (dbdiff != 0) { 3288 if (wr_can_update_eq(wr)) 3289 set_txupdate_flags(txq, avail, wr); 3290 ring_eq_db(sc, eq, dbdiff); 3291 reclaim_tx_descs(txq, 32); 3292 } else if (eq->pidx == eq->cidx && txp->npkt > 0 && 3293 atomic_load_int(&txq->eq.equiq) == 0) { 3294 /* 3295 * If nothing was submitted to the chip for tx (it was coalesced 3296 * into txpkts instead) and there is no tx update outstanding 3297 * then we need to send txpkts now. 3298 */ 3299 send_txpkts: 3300 MPASS(txp->npkt > 0); 3301 for (i = 0; i < txp->npkt; i++) 3302 ETHER_BPF_MTAP(ifp, txp->mb[i]); 3303 if (txp->npkt > 1) { 3304 MPASS(avail >= tx_len16_to_desc(txp->len16)); 3305 if (vi->flags & TX_USES_VM_WR) 3306 n = write_txpkts_vm_wr(sc, txq); 3307 else 3308 n = write_txpkts_wr(sc, txq); 3309 } else { 3310 MPASS(avail >= 3311 tx_len16_to_desc(mbuf_len16(txp->mb[0]))); 3312 if (vi->flags & TX_USES_VM_WR) 3313 n = write_txpkt_vm_wr(sc, txq, txp->mb[0]); 3314 else 3315 n = write_txpkt_wr(sc, txq, txp->mb[0], avail); 3316 } 3317 MPASS(n <= SGE_MAX_WR_NDESC); 3318 wr = &eq->desc[eq->pidx]; 3319 IDXINCR(eq->pidx, n, eq->sidx); 3320 txp->npkt = 0; /* emptied */ 3321 3322 MPASS(wr_can_update_eq(wr)); 3323 set_txupdate_flags(txq, avail - n, wr); 3324 ring_eq_db(sc, eq, n); 3325 reclaim_tx_descs(txq, 32); 3326 } 3327 *coalescing = txp->npkt > 0; 3328 3329 return (total); 3330 } 3331 3332 static inline void 3333 init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int pktc_idx, 3334 int qsize) 3335 { 3336 3337 KASSERT(tmr_idx >= 0 && tmr_idx < SGE_NTIMERS, 3338 ("%s: bad tmr_idx %d", __func__, tmr_idx)); 3339 KASSERT(pktc_idx < SGE_NCOUNTERS, /* -ve is ok, means don't use */ 3340 ("%s: bad pktc_idx %d", __func__, pktc_idx)); 3341 3342 iq->flags = 0; 3343 iq->adapter = sc; 3344 iq->intr_params = V_QINTR_TIMER_IDX(tmr_idx); 3345 iq->intr_pktc_idx = SGE_NCOUNTERS - 1; 3346 if (pktc_idx >= 0) { 3347 iq->intr_params |= F_QINTR_CNT_EN; 3348 iq->intr_pktc_idx = pktc_idx; 3349 } 3350 iq->qsize = roundup2(qsize, 16); /* See FW_IQ_CMD/iqsize */ 3351 iq->sidx = iq->qsize - sc->params.sge.spg_len / IQ_ESIZE; 3352 } 3353 3354 static inline void 3355 init_fl(struct adapter *sc, struct sge_fl *fl, int qsize, int maxp, char *name) 3356 { 3357 3358 fl->qsize = qsize; 3359 fl->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE; 3360 strlcpy(fl->lockname, name, sizeof(fl->lockname)); 3361 if (sc->flags & BUF_PACKING_OK && 3362 ((!is_t4(sc) && buffer_packing) || /* T5+: enabled unless 0 */ 3363 (is_t4(sc) && buffer_packing == 1)))/* T4: disabled unless 1 */ 3364 fl->flags |= FL_BUF_PACKING; 3365 fl->zidx = find_refill_source(sc, maxp, fl->flags & FL_BUF_PACKING); 3366 fl->safe_zidx = sc->sge.safe_zidx; 3367 } 3368 3369 static inline void 3370 init_eq(struct adapter *sc, struct sge_eq *eq, int eqtype, int qsize, 3371 uint8_t tx_chan, uint16_t iqid, char *name) 3372 { 3373 KASSERT(eqtype <= EQ_TYPEMASK, ("%s: bad qtype %d", __func__, eqtype)); 3374 3375 eq->flags = eqtype & EQ_TYPEMASK; 3376 eq->tx_chan = tx_chan; 3377 eq->iqid = iqid; 3378 eq->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE; 3379 strlcpy(eq->lockname, name, sizeof(eq->lockname)); 3380 } 3381 3382 int 3383 alloc_ring(struct adapter *sc, size_t len, bus_dma_tag_t *tag, 3384 bus_dmamap_t *map, bus_addr_t *pa, void **va) 3385 { 3386 int rc; 3387 3388 rc = bus_dma_tag_create(sc->dmat, 512, 0, BUS_SPACE_MAXADDR, 3389 BUS_SPACE_MAXADDR, NULL, NULL, len, 1, len, 0, NULL, NULL, tag); 3390 if (rc != 0) { 3391 device_printf(sc->dev, "cannot allocate DMA tag: %d\n", rc); 3392 goto done; 3393 } 3394 3395 rc = bus_dmamem_alloc(*tag, va, 3396 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, map); 3397 if (rc != 0) { 3398 device_printf(sc->dev, "cannot allocate DMA memory: %d\n", rc); 3399 goto done; 3400 } 3401 3402 rc = bus_dmamap_load(*tag, *map, *va, len, oneseg_dma_callback, pa, 0); 3403 if (rc != 0) { 3404 device_printf(sc->dev, "cannot load DMA map: %d\n", rc); 3405 goto done; 3406 } 3407 done: 3408 if (rc) 3409 free_ring(sc, *tag, *map, *pa, *va); 3410 3411 return (rc); 3412 } 3413 3414 int 3415 free_ring(struct adapter *sc, bus_dma_tag_t tag, bus_dmamap_t map, 3416 bus_addr_t pa, void *va) 3417 { 3418 if (pa) 3419 bus_dmamap_unload(tag, map); 3420 if (va) 3421 bus_dmamem_free(tag, va, map); 3422 if (tag) 3423 bus_dma_tag_destroy(tag); 3424 3425 return (0); 3426 } 3427 3428 /* 3429 * Allocates the ring for an ingress queue and an optional freelist. If the 3430 * freelist is specified it will be allocated and then associated with the 3431 * ingress queue. 3432 * 3433 * Returns errno on failure. Resources allocated up to that point may still be 3434 * allocated. Caller is responsible for cleanup in case this function fails. 3435 * 3436 * If the ingress queue will take interrupts directly then the intr_idx 3437 * specifies the vector, starting from 0. -1 means the interrupts for this 3438 * queue should be forwarded to the fwq. 3439 */ 3440 static int 3441 alloc_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl, 3442 int intr_idx, int cong) 3443 { 3444 int rc, i, cntxt_id; 3445 size_t len; 3446 struct fw_iq_cmd c; 3447 struct port_info *pi = vi->pi; 3448 struct adapter *sc = iq->adapter; 3449 struct sge_params *sp = &sc->params.sge; 3450 __be32 v = 0; 3451 3452 len = iq->qsize * IQ_ESIZE; 3453 rc = alloc_ring(sc, len, &iq->desc_tag, &iq->desc_map, &iq->ba, 3454 (void **)&iq->desc); 3455 if (rc != 0) 3456 return (rc); 3457 3458 bzero(&c, sizeof(c)); 3459 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 3460 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) | 3461 V_FW_IQ_CMD_VFN(0)); 3462 3463 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART | 3464 FW_LEN16(c)); 3465 3466 /* Special handling for firmware event queue */ 3467 if (iq == &sc->sge.fwq) 3468 v |= F_FW_IQ_CMD_IQASYNCH; 3469 3470 if (intr_idx < 0) { 3471 /* Forwarded interrupts, all headed to fwq */ 3472 v |= F_FW_IQ_CMD_IQANDST; 3473 v |= V_FW_IQ_CMD_IQANDSTINDEX(sc->sge.fwq.cntxt_id); 3474 } else { 3475 KASSERT(intr_idx < sc->intr_count, 3476 ("%s: invalid direct intr_idx %d", __func__, intr_idx)); 3477 v |= V_FW_IQ_CMD_IQANDSTINDEX(intr_idx); 3478 } 3479 3480 c.type_to_iqandstindex = htobe32(v | 3481 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) | 3482 V_FW_IQ_CMD_VIID(vi->viid) | 3483 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT)); 3484 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->tx_chan) | 3485 F_FW_IQ_CMD_IQGTSMODE | 3486 V_FW_IQ_CMD_IQINTCNTTHRESH(iq->intr_pktc_idx) | 3487 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4)); 3488 c.iqsize = htobe16(iq->qsize); 3489 c.iqaddr = htobe64(iq->ba); 3490 if (cong >= 0) 3491 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN); 3492 3493 if (fl) { 3494 mtx_init(&fl->fl_lock, fl->lockname, NULL, MTX_DEF); 3495 3496 len = fl->qsize * EQ_ESIZE; 3497 rc = alloc_ring(sc, len, &fl->desc_tag, &fl->desc_map, 3498 &fl->ba, (void **)&fl->desc); 3499 if (rc) 3500 return (rc); 3501 3502 /* Allocate space for one software descriptor per buffer. */ 3503 rc = alloc_fl_sdesc(fl); 3504 if (rc != 0) { 3505 device_printf(sc->dev, 3506 "failed to setup fl software descriptors: %d\n", 3507 rc); 3508 return (rc); 3509 } 3510 3511 if (fl->flags & FL_BUF_PACKING) { 3512 fl->lowat = roundup2(sp->fl_starve_threshold2, 8); 3513 fl->buf_boundary = sp->pack_boundary; 3514 } else { 3515 fl->lowat = roundup2(sp->fl_starve_threshold, 8); 3516 fl->buf_boundary = 16; 3517 } 3518 if (fl_pad && fl->buf_boundary < sp->pad_boundary) 3519 fl->buf_boundary = sp->pad_boundary; 3520 3521 c.iqns_to_fl0congen |= 3522 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) | 3523 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO | 3524 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) | 3525 (fl->flags & FL_BUF_PACKING ? F_FW_IQ_CMD_FL0PACKEN : 3526 0)); 3527 if (cong >= 0) { 3528 c.iqns_to_fl0congen |= 3529 htobe32(V_FW_IQ_CMD_FL0CNGCHMAP(cong) | 3530 F_FW_IQ_CMD_FL0CONGCIF | 3531 F_FW_IQ_CMD_FL0CONGEN); 3532 } 3533 c.fl0dcaen_to_fl0cidxfthresh = 3534 htobe16(V_FW_IQ_CMD_FL0FBMIN(chip_id(sc) <= CHELSIO_T5 ? 3535 X_FETCHBURSTMIN_128B : X_FETCHBURSTMIN_64B_T6) | 3536 V_FW_IQ_CMD_FL0FBMAX(chip_id(sc) <= CHELSIO_T5 ? 3537 X_FETCHBURSTMAX_512B : X_FETCHBURSTMAX_256B)); 3538 c.fl0size = htobe16(fl->qsize); 3539 c.fl0addr = htobe64(fl->ba); 3540 } 3541 3542 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3543 if (rc != 0) { 3544 device_printf(sc->dev, 3545 "failed to create ingress queue: %d\n", rc); 3546 return (rc); 3547 } 3548 3549 iq->cidx = 0; 3550 iq->gen = F_RSPD_GEN; 3551 iq->intr_next = iq->intr_params; 3552 iq->cntxt_id = be16toh(c.iqid); 3553 iq->abs_id = be16toh(c.physiqid); 3554 iq->flags |= IQ_ALLOCATED; 3555 3556 cntxt_id = iq->cntxt_id - sc->sge.iq_start; 3557 if (cntxt_id >= sc->sge.iqmap_sz) { 3558 panic ("%s: iq->cntxt_id (%d) more than the max (%d)", __func__, 3559 cntxt_id, sc->sge.iqmap_sz - 1); 3560 } 3561 sc->sge.iqmap[cntxt_id] = iq; 3562 3563 if (fl) { 3564 u_int qid; 3565 3566 iq->flags |= IQ_HAS_FL; 3567 fl->cntxt_id = be16toh(c.fl0id); 3568 fl->pidx = fl->cidx = 0; 3569 3570 cntxt_id = fl->cntxt_id - sc->sge.eq_start; 3571 if (cntxt_id >= sc->sge.eqmap_sz) { 3572 panic("%s: fl->cntxt_id (%d) more than the max (%d)", 3573 __func__, cntxt_id, sc->sge.eqmap_sz - 1); 3574 } 3575 sc->sge.eqmap[cntxt_id] = (void *)fl; 3576 3577 qid = fl->cntxt_id; 3578 if (isset(&sc->doorbells, DOORBELL_UDB)) { 3579 uint32_t s_qpp = sc->params.sge.eq_s_qpp; 3580 uint32_t mask = (1 << s_qpp) - 1; 3581 volatile uint8_t *udb; 3582 3583 udb = sc->udbs_base + UDBS_DB_OFFSET; 3584 udb += (qid >> s_qpp) << PAGE_SHIFT; 3585 qid &= mask; 3586 if (qid < PAGE_SIZE / UDBS_SEG_SIZE) { 3587 udb += qid << UDBS_SEG_SHIFT; 3588 qid = 0; 3589 } 3590 fl->udb = (volatile void *)udb; 3591 } 3592 fl->dbval = V_QID(qid) | sc->chip_params->sge_fl_db; 3593 3594 FL_LOCK(fl); 3595 /* Enough to make sure the SGE doesn't think it's starved */ 3596 refill_fl(sc, fl, fl->lowat); 3597 FL_UNLOCK(fl); 3598 } 3599 3600 if (chip_id(sc) >= CHELSIO_T5 && !(sc->flags & IS_VF) && cong >= 0) { 3601 uint32_t param, val; 3602 3603 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 3604 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) | 3605 V_FW_PARAMS_PARAM_YZ(iq->cntxt_id); 3606 if (cong == 0) 3607 val = 1 << 19; 3608 else { 3609 val = 2 << 19; 3610 for (i = 0; i < 4; i++) { 3611 if (cong & (1 << i)) 3612 val |= 1 << (i << 2); 3613 } 3614 } 3615 3616 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 3617 if (rc != 0) { 3618 /* report error but carry on */ 3619 device_printf(sc->dev, 3620 "failed to set congestion manager context for " 3621 "ingress queue %d: %d\n", iq->cntxt_id, rc); 3622 } 3623 } 3624 3625 /* Enable IQ interrupts */ 3626 atomic_store_rel_int(&iq->state, IQS_IDLE); 3627 t4_write_reg(sc, sc->sge_gts_reg, V_SEINTARM(iq->intr_params) | 3628 V_INGRESSQID(iq->cntxt_id)); 3629 3630 return (0); 3631 } 3632 3633 static int 3634 free_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl) 3635 { 3636 int rc; 3637 struct adapter *sc = iq->adapter; 3638 device_t dev; 3639 3640 if (sc == NULL) 3641 return (0); /* nothing to do */ 3642 3643 dev = vi ? vi->dev : sc->dev; 3644 3645 if (iq->flags & IQ_ALLOCATED) { 3646 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0, 3647 FW_IQ_TYPE_FL_INT_CAP, iq->cntxt_id, 3648 fl ? fl->cntxt_id : 0xffff, 0xffff); 3649 if (rc != 0) { 3650 device_printf(dev, 3651 "failed to free queue %p: %d\n", iq, rc); 3652 return (rc); 3653 } 3654 iq->flags &= ~IQ_ALLOCATED; 3655 } 3656 3657 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, iq->desc); 3658 3659 bzero(iq, sizeof(*iq)); 3660 3661 if (fl) { 3662 free_ring(sc, fl->desc_tag, fl->desc_map, fl->ba, 3663 fl->desc); 3664 3665 if (fl->sdesc) 3666 free_fl_sdesc(sc, fl); 3667 3668 if (mtx_initialized(&fl->fl_lock)) 3669 mtx_destroy(&fl->fl_lock); 3670 3671 bzero(fl, sizeof(*fl)); 3672 } 3673 3674 return (0); 3675 } 3676 3677 static void 3678 add_iq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid, 3679 struct sge_iq *iq) 3680 { 3681 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3682 3683 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, &iq->ba, 3684 "bus address of descriptor ring"); 3685 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3686 iq->qsize * IQ_ESIZE, "descriptor ring size in bytes"); 3687 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "abs_id", 3688 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, &iq->abs_id, 0, 3689 sysctl_uint16, "I", "absolute id of the queue"); 3690 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 3691 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, &iq->cntxt_id, 0, 3692 sysctl_uint16, "I", "SGE context id of the queue"); 3693 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx", 3694 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, &iq->cidx, 0, 3695 sysctl_uint16, "I", "consumer index"); 3696 } 3697 3698 static void 3699 add_fl_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx, 3700 struct sysctl_oid *oid, struct sge_fl *fl) 3701 { 3702 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3703 3704 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", 3705 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "freelist"); 3706 children = SYSCTL_CHILDREN(oid); 3707 3708 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, 3709 &fl->ba, "bus address of descriptor ring"); 3710 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3711 fl->sidx * EQ_ESIZE + sc->params.sge.spg_len, 3712 "desc ring size in bytes"); 3713 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 3714 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, &fl->cntxt_id, 0, 3715 sysctl_uint16, "I", "SGE context id of the freelist"); 3716 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "padding", CTLFLAG_RD, NULL, 3717 fl_pad ? 1 : 0, "padding enabled"); 3718 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "packing", CTLFLAG_RD, NULL, 3719 fl->flags & FL_BUF_PACKING ? 1 : 0, "packing enabled"); 3720 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &fl->cidx, 3721 0, "consumer index"); 3722 if (fl->flags & FL_BUF_PACKING) { 3723 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rx_offset", 3724 CTLFLAG_RD, &fl->rx_offset, 0, "packing rx offset"); 3725 } 3726 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &fl->pidx, 3727 0, "producer index"); 3728 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_allocated", 3729 CTLFLAG_RD, &fl->cl_allocated, "# of clusters allocated"); 3730 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_recycled", 3731 CTLFLAG_RD, &fl->cl_recycled, "# of clusters recycled"); 3732 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_fast_recycled", 3733 CTLFLAG_RD, &fl->cl_fast_recycled, "# of clusters recycled (fast)"); 3734 } 3735 3736 static int 3737 alloc_fwq(struct adapter *sc) 3738 { 3739 int rc, intr_idx; 3740 struct sge_iq *fwq = &sc->sge.fwq; 3741 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev); 3742 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3743 3744 init_iq(fwq, sc, 0, 0, FW_IQ_QSIZE); 3745 if (sc->flags & IS_VF) 3746 intr_idx = 0; 3747 else 3748 intr_idx = sc->intr_count > 1 ? 1 : 0; 3749 rc = alloc_iq_fl(&sc->port[0]->vi[0], fwq, NULL, intr_idx, -1); 3750 if (rc != 0) { 3751 device_printf(sc->dev, 3752 "failed to create firmware event queue: %d\n", rc); 3753 return (rc); 3754 } 3755 3756 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "fwq", 3757 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "firmware event queue"); 3758 add_iq_sysctls(&sc->ctx, oid, fwq); 3759 3760 return (0); 3761 } 3762 3763 static int 3764 free_fwq(struct adapter *sc) 3765 { 3766 return free_iq_fl(NULL, &sc->sge.fwq, NULL); 3767 } 3768 3769 static int 3770 alloc_ctrlq(struct adapter *sc, struct sge_wrq *ctrlq, int idx, 3771 struct sysctl_oid *oid) 3772 { 3773 int rc; 3774 char name[16]; 3775 struct sysctl_oid_list *children; 3776 3777 snprintf(name, sizeof(name), "%s ctrlq%d", device_get_nameunit(sc->dev), 3778 idx); 3779 init_eq(sc, &ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE, sc->port[idx]->tx_chan, 3780 sc->sge.fwq.cntxt_id, name); 3781 3782 children = SYSCTL_CHILDREN(oid); 3783 snprintf(name, sizeof(name), "%d", idx); 3784 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, name, 3785 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "ctrl queue"); 3786 rc = alloc_wrq(sc, NULL, ctrlq, oid); 3787 3788 return (rc); 3789 } 3790 3791 int 3792 tnl_cong(struct port_info *pi, int drop) 3793 { 3794 3795 if (drop == -1) 3796 return (-1); 3797 else if (drop == 1) 3798 return (0); 3799 else 3800 return (pi->rx_e_chan_map); 3801 } 3802 3803 static int 3804 alloc_rxq(struct vi_info *vi, struct sge_rxq *rxq, int intr_idx, int idx, 3805 struct sysctl_oid *oid) 3806 { 3807 int rc; 3808 struct adapter *sc = vi->adapter; 3809 struct sysctl_oid_list *children; 3810 char name[16]; 3811 3812 rc = alloc_iq_fl(vi, &rxq->iq, &rxq->fl, intr_idx, 3813 tnl_cong(vi->pi, cong_drop)); 3814 if (rc != 0) 3815 return (rc); 3816 3817 if (idx == 0) 3818 sc->sge.iq_base = rxq->iq.abs_id - rxq->iq.cntxt_id; 3819 else 3820 KASSERT(rxq->iq.cntxt_id + sc->sge.iq_base == rxq->iq.abs_id, 3821 ("iq_base mismatch")); 3822 KASSERT(sc->sge.iq_base == 0 || sc->flags & IS_VF, 3823 ("PF with non-zero iq_base")); 3824 3825 /* 3826 * The freelist is just barely above the starvation threshold right now, 3827 * fill it up a bit more. 3828 */ 3829 FL_LOCK(&rxq->fl); 3830 refill_fl(sc, &rxq->fl, 128); 3831 FL_UNLOCK(&rxq->fl); 3832 3833 #if defined(INET) || defined(INET6) 3834 rc = tcp_lro_init_args(&rxq->lro, vi->ifp, lro_entries, lro_mbufs); 3835 if (rc != 0) 3836 return (rc); 3837 MPASS(rxq->lro.ifp == vi->ifp); /* also indicates LRO init'ed */ 3838 3839 if (vi->ifp->if_capenable & IFCAP_LRO) 3840 rxq->iq.flags |= IQ_LRO_ENABLED; 3841 #endif 3842 if (vi->ifp->if_capenable & IFCAP_HWRXTSTMP) 3843 rxq->iq.flags |= IQ_RX_TIMESTAMP; 3844 rxq->ifp = vi->ifp; 3845 3846 children = SYSCTL_CHILDREN(oid); 3847 3848 snprintf(name, sizeof(name), "%d", idx); 3849 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, 3850 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "rx queue"); 3851 children = SYSCTL_CHILDREN(oid); 3852 3853 add_iq_sysctls(&vi->ctx, oid, &rxq->iq); 3854 #if defined(INET) || defined(INET6) 3855 SYSCTL_ADD_U64(&vi->ctx, children, OID_AUTO, "lro_queued", CTLFLAG_RD, 3856 &rxq->lro.lro_queued, 0, NULL); 3857 SYSCTL_ADD_U64(&vi->ctx, children, OID_AUTO, "lro_flushed", CTLFLAG_RD, 3858 &rxq->lro.lro_flushed, 0, NULL); 3859 #endif 3860 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "rxcsum", CTLFLAG_RD, 3861 &rxq->rxcsum, "# of times hardware assisted with checksum"); 3862 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_extraction", 3863 CTLFLAG_RD, &rxq->vlan_extraction, 3864 "# of times hardware extracted 802.1Q tag"); 3865 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vxlan_rxcsum", 3866 CTLFLAG_RD, &rxq->vxlan_rxcsum, 3867 "# of times hardware assisted with inner checksum (VXLAN) "); 3868 3869 add_fl_sysctls(sc, &vi->ctx, oid, &rxq->fl); 3870 3871 return (rc); 3872 } 3873 3874 static int 3875 free_rxq(struct vi_info *vi, struct sge_rxq *rxq) 3876 { 3877 int rc; 3878 3879 #if defined(INET) || defined(INET6) 3880 if (rxq->lro.ifp) { 3881 tcp_lro_free(&rxq->lro); 3882 rxq->lro.ifp = NULL; 3883 } 3884 #endif 3885 3886 rc = free_iq_fl(vi, &rxq->iq, &rxq->fl); 3887 if (rc == 0) 3888 bzero(rxq, sizeof(*rxq)); 3889 3890 return (rc); 3891 } 3892 3893 #ifdef TCP_OFFLOAD 3894 static int 3895 alloc_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq, 3896 int intr_idx, int idx, struct sysctl_oid *oid) 3897 { 3898 struct port_info *pi = vi->pi; 3899 int rc; 3900 struct sysctl_oid_list *children; 3901 char name[16]; 3902 3903 rc = alloc_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl, intr_idx, 0); 3904 if (rc != 0) 3905 return (rc); 3906 3907 children = SYSCTL_CHILDREN(oid); 3908 3909 snprintf(name, sizeof(name), "%d", idx); 3910 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, 3911 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "rx queue"); 3912 add_iq_sysctls(&vi->ctx, oid, &ofld_rxq->iq); 3913 add_fl_sysctls(pi->adapter, &vi->ctx, oid, &ofld_rxq->fl); 3914 3915 return (rc); 3916 } 3917 3918 static int 3919 free_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq) 3920 { 3921 int rc; 3922 3923 rc = free_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl); 3924 if (rc == 0) 3925 bzero(ofld_rxq, sizeof(*ofld_rxq)); 3926 3927 return (rc); 3928 } 3929 #endif 3930 3931 /* 3932 * Returns a reasonable automatic cidx flush threshold for a given queue size. 3933 */ 3934 static u_int 3935 qsize_to_fthresh(int qsize) 3936 { 3937 u_int fthresh; 3938 3939 while (!powerof2(qsize)) 3940 qsize++; 3941 fthresh = ilog2(qsize); 3942 if (fthresh > X_CIDXFLUSHTHRESH_128) 3943 fthresh = X_CIDXFLUSHTHRESH_128; 3944 3945 return (fthresh); 3946 } 3947 3948 static int 3949 ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq) 3950 { 3951 int rc, cntxt_id; 3952 struct fw_eq_ctrl_cmd c; 3953 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 3954 3955 bzero(&c, sizeof(c)); 3956 3957 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | F_FW_CMD_REQUEST | 3958 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_CTRL_CMD_PFN(sc->pf) | 3959 V_FW_EQ_CTRL_CMD_VFN(0)); 3960 c.alloc_to_len16 = htobe32(F_FW_EQ_CTRL_CMD_ALLOC | 3961 F_FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c)); 3962 c.cmpliqid_eqid = htonl(V_FW_EQ_CTRL_CMD_CMPLIQID(eq->iqid)); 3963 c.physeqid_pkd = htobe32(0); 3964 c.fetchszm_to_iqid = 3965 htobe32(V_FW_EQ_CTRL_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 3966 V_FW_EQ_CTRL_CMD_PCIECHN(eq->tx_chan) | 3967 F_FW_EQ_CTRL_CMD_FETCHRO | V_FW_EQ_CTRL_CMD_IQID(eq->iqid)); 3968 c.dcaen_to_eqsize = 3969 htobe32(V_FW_EQ_CTRL_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ? 3970 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) | 3971 V_FW_EQ_CTRL_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 3972 V_FW_EQ_CTRL_CMD_CIDXFTHRESH(qsize_to_fthresh(qsize)) | 3973 V_FW_EQ_CTRL_CMD_EQSIZE(qsize)); 3974 c.eqaddr = htobe64(eq->ba); 3975 3976 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3977 if (rc != 0) { 3978 device_printf(sc->dev, 3979 "failed to create control queue %d: %d\n", eq->tx_chan, rc); 3980 return (rc); 3981 } 3982 eq->flags |= EQ_ALLOCATED; 3983 3984 eq->cntxt_id = G_FW_EQ_CTRL_CMD_EQID(be32toh(c.cmpliqid_eqid)); 3985 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 3986 if (cntxt_id >= sc->sge.eqmap_sz) 3987 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 3988 cntxt_id, sc->sge.eqmap_sz - 1); 3989 sc->sge.eqmap[cntxt_id] = eq; 3990 3991 return (rc); 3992 } 3993 3994 static int 3995 eth_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 3996 { 3997 int rc, cntxt_id; 3998 struct fw_eq_eth_cmd c; 3999 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 4000 4001 bzero(&c, sizeof(c)); 4002 4003 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST | 4004 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) | 4005 V_FW_EQ_ETH_CMD_VFN(0)); 4006 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC | 4007 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c)); 4008 c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE | 4009 F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(vi->viid)); 4010 c.fetchszm_to_iqid = 4011 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) | 4012 V_FW_EQ_ETH_CMD_PCIECHN(eq->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO | 4013 V_FW_EQ_ETH_CMD_IQID(eq->iqid)); 4014 c.dcaen_to_eqsize = 4015 htobe32(V_FW_EQ_ETH_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ? 4016 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) | 4017 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 4018 V_FW_EQ_ETH_CMD_EQSIZE(qsize)); 4019 c.eqaddr = htobe64(eq->ba); 4020 4021 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 4022 if (rc != 0) { 4023 device_printf(vi->dev, 4024 "failed to create Ethernet egress queue: %d\n", rc); 4025 return (rc); 4026 } 4027 eq->flags |= EQ_ALLOCATED; 4028 4029 eq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd)); 4030 eq->abs_id = G_FW_EQ_ETH_CMD_PHYSEQID(be32toh(c.physeqid_pkd)); 4031 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 4032 if (cntxt_id >= sc->sge.eqmap_sz) 4033 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 4034 cntxt_id, sc->sge.eqmap_sz - 1); 4035 sc->sge.eqmap[cntxt_id] = eq; 4036 4037 return (rc); 4038 } 4039 4040 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 4041 static int 4042 ofld_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 4043 { 4044 int rc, cntxt_id; 4045 struct fw_eq_ofld_cmd c; 4046 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 4047 4048 bzero(&c, sizeof(c)); 4049 4050 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | F_FW_CMD_REQUEST | 4051 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_OFLD_CMD_PFN(sc->pf) | 4052 V_FW_EQ_OFLD_CMD_VFN(0)); 4053 c.alloc_to_len16 = htonl(F_FW_EQ_OFLD_CMD_ALLOC | 4054 F_FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c)); 4055 c.fetchszm_to_iqid = 4056 htonl(V_FW_EQ_OFLD_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 4057 V_FW_EQ_OFLD_CMD_PCIECHN(eq->tx_chan) | 4058 F_FW_EQ_OFLD_CMD_FETCHRO | V_FW_EQ_OFLD_CMD_IQID(eq->iqid)); 4059 c.dcaen_to_eqsize = 4060 htobe32(V_FW_EQ_OFLD_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ? 4061 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) | 4062 V_FW_EQ_OFLD_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 4063 V_FW_EQ_OFLD_CMD_CIDXFTHRESH(qsize_to_fthresh(qsize)) | 4064 V_FW_EQ_OFLD_CMD_EQSIZE(qsize)); 4065 c.eqaddr = htobe64(eq->ba); 4066 4067 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 4068 if (rc != 0) { 4069 device_printf(vi->dev, 4070 "failed to create egress queue for TCP offload: %d\n", rc); 4071 return (rc); 4072 } 4073 eq->flags |= EQ_ALLOCATED; 4074 4075 eq->cntxt_id = G_FW_EQ_OFLD_CMD_EQID(be32toh(c.eqid_pkd)); 4076 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 4077 if (cntxt_id >= sc->sge.eqmap_sz) 4078 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 4079 cntxt_id, sc->sge.eqmap_sz - 1); 4080 sc->sge.eqmap[cntxt_id] = eq; 4081 4082 return (rc); 4083 } 4084 #endif 4085 4086 static int 4087 alloc_eq(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 4088 { 4089 int rc, qsize; 4090 size_t len; 4091 4092 mtx_init(&eq->eq_lock, eq->lockname, NULL, MTX_DEF); 4093 4094 qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 4095 len = qsize * EQ_ESIZE; 4096 rc = alloc_ring(sc, len, &eq->desc_tag, &eq->desc_map, 4097 &eq->ba, (void **)&eq->desc); 4098 if (rc) 4099 return (rc); 4100 4101 eq->pidx = eq->cidx = eq->dbidx = 0; 4102 /* Note that equeqidx is not used with sge_wrq (OFLD/CTRL) queues. */ 4103 eq->equeqidx = 0; 4104 eq->doorbells = sc->doorbells; 4105 4106 switch (eq->flags & EQ_TYPEMASK) { 4107 case EQ_CTRL: 4108 rc = ctrl_eq_alloc(sc, eq); 4109 break; 4110 4111 case EQ_ETH: 4112 rc = eth_eq_alloc(sc, vi, eq); 4113 break; 4114 4115 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 4116 case EQ_OFLD: 4117 rc = ofld_eq_alloc(sc, vi, eq); 4118 break; 4119 #endif 4120 4121 default: 4122 panic("%s: invalid eq type %d.", __func__, 4123 eq->flags & EQ_TYPEMASK); 4124 } 4125 if (rc != 0) { 4126 device_printf(sc->dev, 4127 "failed to allocate egress queue(%d): %d\n", 4128 eq->flags & EQ_TYPEMASK, rc); 4129 } 4130 4131 if (isset(&eq->doorbells, DOORBELL_UDB) || 4132 isset(&eq->doorbells, DOORBELL_UDBWC) || 4133 isset(&eq->doorbells, DOORBELL_WCWR)) { 4134 uint32_t s_qpp = sc->params.sge.eq_s_qpp; 4135 uint32_t mask = (1 << s_qpp) - 1; 4136 volatile uint8_t *udb; 4137 4138 udb = sc->udbs_base + UDBS_DB_OFFSET; 4139 udb += (eq->cntxt_id >> s_qpp) << PAGE_SHIFT; /* pg offset */ 4140 eq->udb_qid = eq->cntxt_id & mask; /* id in page */ 4141 if (eq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE) 4142 clrbit(&eq->doorbells, DOORBELL_WCWR); 4143 else { 4144 udb += eq->udb_qid << UDBS_SEG_SHIFT; /* seg offset */ 4145 eq->udb_qid = 0; 4146 } 4147 eq->udb = (volatile void *)udb; 4148 } 4149 4150 return (rc); 4151 } 4152 4153 static int 4154 free_eq(struct adapter *sc, struct sge_eq *eq) 4155 { 4156 int rc; 4157 4158 if (eq->flags & EQ_ALLOCATED) { 4159 switch (eq->flags & EQ_TYPEMASK) { 4160 case EQ_CTRL: 4161 rc = -t4_ctrl_eq_free(sc, sc->mbox, sc->pf, 0, 4162 eq->cntxt_id); 4163 break; 4164 4165 case EQ_ETH: 4166 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0, 4167 eq->cntxt_id); 4168 break; 4169 4170 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 4171 case EQ_OFLD: 4172 rc = -t4_ofld_eq_free(sc, sc->mbox, sc->pf, 0, 4173 eq->cntxt_id); 4174 break; 4175 #endif 4176 4177 default: 4178 panic("%s: invalid eq type %d.", __func__, 4179 eq->flags & EQ_TYPEMASK); 4180 } 4181 if (rc != 0) { 4182 device_printf(sc->dev, 4183 "failed to free egress queue (%d): %d\n", 4184 eq->flags & EQ_TYPEMASK, rc); 4185 return (rc); 4186 } 4187 eq->flags &= ~EQ_ALLOCATED; 4188 } 4189 4190 free_ring(sc, eq->desc_tag, eq->desc_map, eq->ba, eq->desc); 4191 4192 if (mtx_initialized(&eq->eq_lock)) 4193 mtx_destroy(&eq->eq_lock); 4194 4195 bzero(eq, sizeof(*eq)); 4196 return (0); 4197 } 4198 4199 static int 4200 alloc_wrq(struct adapter *sc, struct vi_info *vi, struct sge_wrq *wrq, 4201 struct sysctl_oid *oid) 4202 { 4203 int rc; 4204 struct sysctl_ctx_list *ctx = vi ? &vi->ctx : &sc->ctx; 4205 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 4206 4207 rc = alloc_eq(sc, vi, &wrq->eq); 4208 if (rc) 4209 return (rc); 4210 4211 wrq->adapter = sc; 4212 TASK_INIT(&wrq->wrq_tx_task, 0, wrq_tx_drain, wrq); 4213 TAILQ_INIT(&wrq->incomplete_wrs); 4214 STAILQ_INIT(&wrq->wr_list); 4215 wrq->nwr_pending = 0; 4216 wrq->ndesc_needed = 0; 4217 4218 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, 4219 &wrq->eq.ba, "bus address of descriptor ring"); 4220 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 4221 wrq->eq.sidx * EQ_ESIZE + sc->params.sge.spg_len, 4222 "desc ring size in bytes"); 4223 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 4224 &wrq->eq.cntxt_id, 0, "SGE context id of the queue"); 4225 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx", 4226 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, &wrq->eq.cidx, 0, 4227 sysctl_uint16, "I", "consumer index"); 4228 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pidx", 4229 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, &wrq->eq.pidx, 0, 4230 sysctl_uint16, "I", "producer index"); 4231 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL, 4232 wrq->eq.sidx, "status page index"); 4233 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_direct", CTLFLAG_RD, 4234 &wrq->tx_wrs_direct, "# of work requests (direct)"); 4235 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_copied", CTLFLAG_RD, 4236 &wrq->tx_wrs_copied, "# of work requests (copied)"); 4237 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_sspace", CTLFLAG_RD, 4238 &wrq->tx_wrs_ss, "# of work requests (copied from scratch space)"); 4239 4240 return (rc); 4241 } 4242 4243 static int 4244 free_wrq(struct adapter *sc, struct sge_wrq *wrq) 4245 { 4246 int rc; 4247 4248 rc = free_eq(sc, &wrq->eq); 4249 if (rc) 4250 return (rc); 4251 4252 bzero(wrq, sizeof(*wrq)); 4253 return (0); 4254 } 4255 4256 static int 4257 alloc_txq(struct vi_info *vi, struct sge_txq *txq, int idx, 4258 struct sysctl_oid *oid) 4259 { 4260 int rc; 4261 struct port_info *pi = vi->pi; 4262 struct adapter *sc = pi->adapter; 4263 struct sge_eq *eq = &txq->eq; 4264 struct txpkts *txp; 4265 char name[16]; 4266 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 4267 4268 rc = mp_ring_alloc(&txq->r, eq->sidx, txq, eth_tx, can_resume_eth_tx, 4269 M_CXGBE, &eq->eq_lock, M_WAITOK); 4270 if (rc != 0) { 4271 device_printf(sc->dev, "failed to allocate mp_ring: %d\n", rc); 4272 return (rc); 4273 } 4274 4275 rc = alloc_eq(sc, vi, eq); 4276 if (rc != 0) { 4277 mp_ring_free(txq->r); 4278 txq->r = NULL; 4279 return (rc); 4280 } 4281 4282 /* Can't fail after this point. */ 4283 4284 if (idx == 0) 4285 sc->sge.eq_base = eq->abs_id - eq->cntxt_id; 4286 else 4287 KASSERT(eq->cntxt_id + sc->sge.eq_base == eq->abs_id, 4288 ("eq_base mismatch")); 4289 KASSERT(sc->sge.eq_base == 0 || sc->flags & IS_VF, 4290 ("PF with non-zero eq_base")); 4291 4292 TASK_INIT(&txq->tx_reclaim_task, 0, tx_reclaim, eq); 4293 txq->ifp = vi->ifp; 4294 txq->gl = sglist_alloc(TX_SGL_SEGS, M_WAITOK); 4295 if (vi->flags & TX_USES_VM_WR) 4296 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) | 4297 V_TXPKT_INTF(pi->tx_chan)); 4298 else 4299 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) | 4300 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(sc->pf) | 4301 V_TXPKT_VF(vi->vin) | V_TXPKT_VF_VLD(vi->vfvld)); 4302 txq->tc_idx = -1; 4303 txq->sdesc = malloc(eq->sidx * sizeof(struct tx_sdesc), M_CXGBE, 4304 M_ZERO | M_WAITOK); 4305 4306 txp = &txq->txp; 4307 txp->score = 5; 4308 MPASS(nitems(txp->mb) >= sc->params.max_pkts_per_eth_tx_pkts_wr); 4309 txq->txp.max_npkt = min(nitems(txp->mb), 4310 sc->params.max_pkts_per_eth_tx_pkts_wr); 4311 if (vi->flags & TX_USES_VM_WR && !(sc->flags & IS_VF)) 4312 txq->txp.max_npkt--; 4313 4314 snprintf(name, sizeof(name), "%d", idx); 4315 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, 4316 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "tx queue"); 4317 children = SYSCTL_CHILDREN(oid); 4318 4319 SYSCTL_ADD_UAUTO(&vi->ctx, children, OID_AUTO, "ba", CTLFLAG_RD, 4320 &eq->ba, "bus address of descriptor ring"); 4321 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 4322 eq->sidx * EQ_ESIZE + sc->params.sge.spg_len, 4323 "desc ring size in bytes"); 4324 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "abs_id", CTLFLAG_RD, 4325 &eq->abs_id, 0, "absolute id of the queue"); 4326 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 4327 &eq->cntxt_id, 0, "SGE context id of the queue"); 4328 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx", 4329 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, &eq->cidx, 0, 4330 sysctl_uint16, "I", "consumer index"); 4331 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "pidx", 4332 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, &eq->pidx, 0, 4333 sysctl_uint16, "I", "producer index"); 4334 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL, 4335 eq->sidx, "status page index"); 4336 4337 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "tc", 4338 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, idx, sysctl_tc, 4339 "I", "traffic class (-1 means none)"); 4340 4341 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txcsum", CTLFLAG_RD, 4342 &txq->txcsum, "# of times hardware assisted with checksum"); 4343 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_insertion", 4344 CTLFLAG_RD, &txq->vlan_insertion, 4345 "# of times hardware inserted 802.1Q tag"); 4346 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "tso_wrs", CTLFLAG_RD, 4347 &txq->tso_wrs, "# of TSO work requests"); 4348 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "imm_wrs", CTLFLAG_RD, 4349 &txq->imm_wrs, "# of work requests with immediate data"); 4350 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "sgl_wrs", CTLFLAG_RD, 4351 &txq->sgl_wrs, "# of work requests with direct SGL"); 4352 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkt_wrs", CTLFLAG_RD, 4353 &txq->txpkt_wrs, "# of txpkt work requests (one pkt/WR)"); 4354 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_wrs", 4355 CTLFLAG_RD, &txq->txpkts0_wrs, 4356 "# of txpkts (type 0) work requests"); 4357 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_wrs", 4358 CTLFLAG_RD, &txq->txpkts1_wrs, 4359 "# of txpkts (type 1) work requests"); 4360 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_pkts", 4361 CTLFLAG_RD, &txq->txpkts0_pkts, 4362 "# of frames tx'd using type0 txpkts work requests"); 4363 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_pkts", 4364 CTLFLAG_RD, &txq->txpkts1_pkts, 4365 "# of frames tx'd using type1 txpkts work requests"); 4366 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "raw_wrs", CTLFLAG_RD, 4367 &txq->raw_wrs, "# of raw work requests (non-packets)"); 4368 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vxlan_tso_wrs", 4369 CTLFLAG_RD, &txq->vxlan_tso_wrs, "# of VXLAN TSO work requests"); 4370 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vxlan_txcsum", 4371 CTLFLAG_RD, &txq->vxlan_txcsum, 4372 "# of times hardware assisted with inner checksums (VXLAN)"); 4373 4374 #ifdef KERN_TLS 4375 if (sc->flags & KERN_TLS_OK) { 4376 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, 4377 "kern_tls_records", CTLFLAG_RD, &txq->kern_tls_records, 4378 "# of NIC TLS records transmitted"); 4379 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, 4380 "kern_tls_short", CTLFLAG_RD, &txq->kern_tls_short, 4381 "# of short NIC TLS records transmitted"); 4382 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, 4383 "kern_tls_partial", CTLFLAG_RD, &txq->kern_tls_partial, 4384 "# of partial NIC TLS records transmitted"); 4385 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, 4386 "kern_tls_full", CTLFLAG_RD, &txq->kern_tls_full, 4387 "# of full NIC TLS records transmitted"); 4388 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, 4389 "kern_tls_octets", CTLFLAG_RD, &txq->kern_tls_octets, 4390 "# of payload octets in transmitted NIC TLS records"); 4391 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, 4392 "kern_tls_waste", CTLFLAG_RD, &txq->kern_tls_waste, 4393 "# of octets DMAd but not transmitted in NIC TLS records"); 4394 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, 4395 "kern_tls_options", CTLFLAG_RD, &txq->kern_tls_options, 4396 "# of NIC TLS options-only packets transmitted"); 4397 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, 4398 "kern_tls_header", CTLFLAG_RD, &txq->kern_tls_header, 4399 "# of NIC TLS header-only packets transmitted"); 4400 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, 4401 "kern_tls_fin", CTLFLAG_RD, &txq->kern_tls_fin, 4402 "# of NIC TLS FIN-only packets transmitted"); 4403 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, 4404 "kern_tls_fin_short", CTLFLAG_RD, &txq->kern_tls_fin_short, 4405 "# of NIC TLS padded FIN packets on short TLS records"); 4406 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, 4407 "kern_tls_cbc", CTLFLAG_RD, &txq->kern_tls_cbc, 4408 "# of NIC TLS sessions using AES-CBC"); 4409 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, 4410 "kern_tls_gcm", CTLFLAG_RD, &txq->kern_tls_gcm, 4411 "# of NIC TLS sessions using AES-GCM"); 4412 } 4413 #endif 4414 mp_ring_sysctls(txq->r, &vi->ctx, children); 4415 4416 return (0); 4417 } 4418 4419 static int 4420 free_txq(struct vi_info *vi, struct sge_txq *txq) 4421 { 4422 int rc; 4423 struct adapter *sc = vi->adapter; 4424 struct sge_eq *eq = &txq->eq; 4425 4426 rc = free_eq(sc, eq); 4427 if (rc) 4428 return (rc); 4429 4430 sglist_free(txq->gl); 4431 free(txq->sdesc, M_CXGBE); 4432 mp_ring_free(txq->r); 4433 4434 bzero(txq, sizeof(*txq)); 4435 return (0); 4436 } 4437 4438 static void 4439 oneseg_dma_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error) 4440 { 4441 bus_addr_t *ba = arg; 4442 4443 KASSERT(nseg == 1, 4444 ("%s meant for single segment mappings only.", __func__)); 4445 4446 *ba = error ? 0 : segs->ds_addr; 4447 } 4448 4449 static inline void 4450 ring_fl_db(struct adapter *sc, struct sge_fl *fl) 4451 { 4452 uint32_t n, v; 4453 4454 n = IDXDIFF(fl->pidx >> 3, fl->dbidx, fl->sidx); 4455 MPASS(n > 0); 4456 4457 wmb(); 4458 v = fl->dbval | V_PIDX(n); 4459 if (fl->udb) 4460 *fl->udb = htole32(v); 4461 else 4462 t4_write_reg(sc, sc->sge_kdoorbell_reg, v); 4463 IDXINCR(fl->dbidx, n, fl->sidx); 4464 } 4465 4466 /* 4467 * Fills up the freelist by allocating up to 'n' buffers. Buffers that are 4468 * recycled do not count towards this allocation budget. 4469 * 4470 * Returns non-zero to indicate that this freelist should be added to the list 4471 * of starving freelists. 4472 */ 4473 static int 4474 refill_fl(struct adapter *sc, struct sge_fl *fl, int n) 4475 { 4476 __be64 *d; 4477 struct fl_sdesc *sd; 4478 uintptr_t pa; 4479 caddr_t cl; 4480 struct rx_buf_info *rxb; 4481 struct cluster_metadata *clm; 4482 uint16_t max_pidx; 4483 uint16_t hw_cidx = fl->hw_cidx; /* stable snapshot */ 4484 4485 FL_LOCK_ASSERT_OWNED(fl); 4486 4487 /* 4488 * We always stop at the beginning of the hardware descriptor that's just 4489 * before the one with the hw cidx. This is to avoid hw pidx = hw cidx, 4490 * which would mean an empty freelist to the chip. 4491 */ 4492 max_pidx = __predict_false(hw_cidx == 0) ? fl->sidx - 1 : hw_cidx - 1; 4493 if (fl->pidx == max_pidx * 8) 4494 return (0); 4495 4496 d = &fl->desc[fl->pidx]; 4497 sd = &fl->sdesc[fl->pidx]; 4498 4499 while (n > 0) { 4500 4501 if (sd->cl != NULL) { 4502 4503 if (sd->nmbuf == 0) { 4504 /* 4505 * Fast recycle without involving any atomics on 4506 * the cluster's metadata (if the cluster has 4507 * metadata). This happens when all frames 4508 * received in the cluster were small enough to 4509 * fit within a single mbuf each. 4510 */ 4511 fl->cl_fast_recycled++; 4512 goto recycled; 4513 } 4514 4515 /* 4516 * Cluster is guaranteed to have metadata. Clusters 4517 * without metadata always take the fast recycle path 4518 * when they're recycled. 4519 */ 4520 clm = cl_metadata(sd); 4521 MPASS(clm != NULL); 4522 4523 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) { 4524 fl->cl_recycled++; 4525 counter_u64_add(extfree_rels, 1); 4526 goto recycled; 4527 } 4528 sd->cl = NULL; /* gave up my reference */ 4529 } 4530 MPASS(sd->cl == NULL); 4531 rxb = &sc->sge.rx_buf_info[fl->zidx]; 4532 cl = uma_zalloc(rxb->zone, M_NOWAIT); 4533 if (__predict_false(cl == NULL)) { 4534 if (fl->zidx != fl->safe_zidx) { 4535 rxb = &sc->sge.rx_buf_info[fl->safe_zidx]; 4536 cl = uma_zalloc(rxb->zone, M_NOWAIT); 4537 } 4538 if (cl == NULL) 4539 break; 4540 } 4541 fl->cl_allocated++; 4542 n--; 4543 4544 pa = pmap_kextract((vm_offset_t)cl); 4545 sd->cl = cl; 4546 sd->zidx = fl->zidx; 4547 4548 if (fl->flags & FL_BUF_PACKING) { 4549 *d = htobe64(pa | rxb->hwidx2); 4550 sd->moff = rxb->size2; 4551 } else { 4552 *d = htobe64(pa | rxb->hwidx1); 4553 sd->moff = 0; 4554 } 4555 recycled: 4556 sd->nmbuf = 0; 4557 d++; 4558 sd++; 4559 if (__predict_false((++fl->pidx & 7) == 0)) { 4560 uint16_t pidx = fl->pidx >> 3; 4561 4562 if (__predict_false(pidx == fl->sidx)) { 4563 fl->pidx = 0; 4564 pidx = 0; 4565 sd = fl->sdesc; 4566 d = fl->desc; 4567 } 4568 if (n < 8 || pidx == max_pidx) 4569 break; 4570 4571 if (IDXDIFF(pidx, fl->dbidx, fl->sidx) >= 4) 4572 ring_fl_db(sc, fl); 4573 } 4574 } 4575 4576 if ((fl->pidx >> 3) != fl->dbidx) 4577 ring_fl_db(sc, fl); 4578 4579 return (FL_RUNNING_LOW(fl) && !(fl->flags & FL_STARVING)); 4580 } 4581 4582 /* 4583 * Attempt to refill all starving freelists. 4584 */ 4585 static void 4586 refill_sfl(void *arg) 4587 { 4588 struct adapter *sc = arg; 4589 struct sge_fl *fl, *fl_temp; 4590 4591 mtx_assert(&sc->sfl_lock, MA_OWNED); 4592 TAILQ_FOREACH_SAFE(fl, &sc->sfl, link, fl_temp) { 4593 FL_LOCK(fl); 4594 refill_fl(sc, fl, 64); 4595 if (FL_NOT_RUNNING_LOW(fl) || fl->flags & FL_DOOMED) { 4596 TAILQ_REMOVE(&sc->sfl, fl, link); 4597 fl->flags &= ~FL_STARVING; 4598 } 4599 FL_UNLOCK(fl); 4600 } 4601 4602 if (!TAILQ_EMPTY(&sc->sfl)) 4603 callout_schedule(&sc->sfl_callout, hz / 5); 4604 } 4605 4606 static int 4607 alloc_fl_sdesc(struct sge_fl *fl) 4608 { 4609 4610 fl->sdesc = malloc(fl->sidx * 8 * sizeof(struct fl_sdesc), M_CXGBE, 4611 M_ZERO | M_WAITOK); 4612 4613 return (0); 4614 } 4615 4616 static void 4617 free_fl_sdesc(struct adapter *sc, struct sge_fl *fl) 4618 { 4619 struct fl_sdesc *sd; 4620 struct cluster_metadata *clm; 4621 int i; 4622 4623 sd = fl->sdesc; 4624 for (i = 0; i < fl->sidx * 8; i++, sd++) { 4625 if (sd->cl == NULL) 4626 continue; 4627 4628 if (sd->nmbuf == 0) 4629 uma_zfree(sc->sge.rx_buf_info[sd->zidx].zone, sd->cl); 4630 else if (fl->flags & FL_BUF_PACKING) { 4631 clm = cl_metadata(sd); 4632 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) { 4633 uma_zfree(sc->sge.rx_buf_info[sd->zidx].zone, 4634 sd->cl); 4635 counter_u64_add(extfree_rels, 1); 4636 } 4637 } 4638 sd->cl = NULL; 4639 } 4640 4641 free(fl->sdesc, M_CXGBE); 4642 fl->sdesc = NULL; 4643 } 4644 4645 static inline void 4646 get_pkt_gl(struct mbuf *m, struct sglist *gl) 4647 { 4648 int rc; 4649 4650 M_ASSERTPKTHDR(m); 4651 4652 sglist_reset(gl); 4653 rc = sglist_append_mbuf(gl, m); 4654 if (__predict_false(rc != 0)) { 4655 panic("%s: mbuf %p (%d segs) was vetted earlier but now fails " 4656 "with %d.", __func__, m, mbuf_nsegs(m), rc); 4657 } 4658 4659 KASSERT(gl->sg_nseg == mbuf_nsegs(m), 4660 ("%s: nsegs changed for mbuf %p from %d to %d", __func__, m, 4661 mbuf_nsegs(m), gl->sg_nseg)); 4662 #if 0 /* vm_wr not readily available here. */ 4663 KASSERT(gl->sg_nseg > 0 && gl->sg_nseg <= max_nsegs_allowed(m, vm_wr), 4664 ("%s: %d segments, should have been 1 <= nsegs <= %d", __func__, 4665 gl->sg_nseg, max_nsegs_allowed(m, vm_wr))); 4666 #endif 4667 } 4668 4669 /* 4670 * len16 for a txpkt WR with a GL. Includes the firmware work request header. 4671 */ 4672 static inline u_int 4673 txpkt_len16(u_int nsegs, const u_int extra) 4674 { 4675 u_int n; 4676 4677 MPASS(nsegs > 0); 4678 4679 nsegs--; /* first segment is part of ulptx_sgl */ 4680 n = extra + sizeof(struct fw_eth_tx_pkt_wr) + 4681 sizeof(struct cpl_tx_pkt_core) + 4682 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 4683 4684 return (howmany(n, 16)); 4685 } 4686 4687 /* 4688 * len16 for a txpkt_vm WR with a GL. Includes the firmware work 4689 * request header. 4690 */ 4691 static inline u_int 4692 txpkt_vm_len16(u_int nsegs, const u_int extra) 4693 { 4694 u_int n; 4695 4696 MPASS(nsegs > 0); 4697 4698 nsegs--; /* first segment is part of ulptx_sgl */ 4699 n = extra + sizeof(struct fw_eth_tx_pkt_vm_wr) + 4700 sizeof(struct cpl_tx_pkt_core) + 4701 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 4702 4703 return (howmany(n, 16)); 4704 } 4705 4706 static inline void 4707 calculate_mbuf_len16(struct mbuf *m, bool vm_wr) 4708 { 4709 const int lso = sizeof(struct cpl_tx_pkt_lso_core); 4710 const int tnl_lso = sizeof(struct cpl_tx_tnl_lso); 4711 4712 if (vm_wr) { 4713 if (needs_tso(m)) 4714 set_mbuf_len16(m, txpkt_vm_len16(mbuf_nsegs(m), lso)); 4715 else 4716 set_mbuf_len16(m, txpkt_vm_len16(mbuf_nsegs(m), 0)); 4717 return; 4718 } 4719 4720 if (needs_tso(m)) { 4721 if (needs_vxlan_tso(m)) 4722 set_mbuf_len16(m, txpkt_len16(mbuf_nsegs(m), tnl_lso)); 4723 else 4724 set_mbuf_len16(m, txpkt_len16(mbuf_nsegs(m), lso)); 4725 } else 4726 set_mbuf_len16(m, txpkt_len16(mbuf_nsegs(m), 0)); 4727 } 4728 4729 /* 4730 * len16 for a txpkts type 0 WR with a GL. Does not include the firmware work 4731 * request header. 4732 */ 4733 static inline u_int 4734 txpkts0_len16(u_int nsegs) 4735 { 4736 u_int n; 4737 4738 MPASS(nsegs > 0); 4739 4740 nsegs--; /* first segment is part of ulptx_sgl */ 4741 n = sizeof(struct ulp_txpkt) + sizeof(struct ulptx_idata) + 4742 sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl) + 4743 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 4744 4745 return (howmany(n, 16)); 4746 } 4747 4748 /* 4749 * len16 for a txpkts type 1 WR with a GL. Does not include the firmware work 4750 * request header. 4751 */ 4752 static inline u_int 4753 txpkts1_len16(void) 4754 { 4755 u_int n; 4756 4757 n = sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl); 4758 4759 return (howmany(n, 16)); 4760 } 4761 4762 static inline u_int 4763 imm_payload(u_int ndesc) 4764 { 4765 u_int n; 4766 4767 n = ndesc * EQ_ESIZE - sizeof(struct fw_eth_tx_pkt_wr) - 4768 sizeof(struct cpl_tx_pkt_core); 4769 4770 return (n); 4771 } 4772 4773 static inline uint64_t 4774 csum_to_ctrl(struct adapter *sc, struct mbuf *m) 4775 { 4776 uint64_t ctrl; 4777 int csum_type, l2hlen, l3hlen; 4778 int x, y; 4779 static const int csum_types[3][2] = { 4780 {TX_CSUM_TCPIP, TX_CSUM_TCPIP6}, 4781 {TX_CSUM_UDPIP, TX_CSUM_UDPIP6}, 4782 {TX_CSUM_IP, 0} 4783 }; 4784 4785 M_ASSERTPKTHDR(m); 4786 4787 if (!needs_hwcsum(m)) 4788 return (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS); 4789 4790 MPASS(m->m_pkthdr.l2hlen >= ETHER_HDR_LEN); 4791 MPASS(m->m_pkthdr.l3hlen >= sizeof(struct ip)); 4792 4793 if (needs_vxlan_csum(m)) { 4794 MPASS(m->m_pkthdr.l4hlen > 0); 4795 MPASS(m->m_pkthdr.l5hlen > 0); 4796 MPASS(m->m_pkthdr.inner_l2hlen >= ETHER_HDR_LEN); 4797 MPASS(m->m_pkthdr.inner_l3hlen >= sizeof(struct ip)); 4798 4799 l2hlen = m->m_pkthdr.l2hlen + m->m_pkthdr.l3hlen + 4800 m->m_pkthdr.l4hlen + m->m_pkthdr.l5hlen + 4801 m->m_pkthdr.inner_l2hlen - ETHER_HDR_LEN; 4802 l3hlen = m->m_pkthdr.inner_l3hlen; 4803 } else { 4804 l2hlen = m->m_pkthdr.l2hlen - ETHER_HDR_LEN; 4805 l3hlen = m->m_pkthdr.l3hlen; 4806 } 4807 4808 ctrl = 0; 4809 if (!needs_l3_csum(m)) 4810 ctrl |= F_TXPKT_IPCSUM_DIS; 4811 4812 if (m->m_pkthdr.csum_flags & (CSUM_IP_TCP | CSUM_INNER_IP_TCP | 4813 CSUM_IP6_TCP | CSUM_INNER_IP6_TCP)) 4814 x = 0; /* TCP */ 4815 else if (m->m_pkthdr.csum_flags & (CSUM_IP_UDP | CSUM_INNER_IP_UDP | 4816 CSUM_IP6_UDP | CSUM_INNER_IP6_UDP)) 4817 x = 1; /* UDP */ 4818 else 4819 x = 2; 4820 4821 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_IP_TCP | CSUM_IP_UDP | 4822 CSUM_INNER_IP | CSUM_INNER_IP_TCP | CSUM_INNER_IP_UDP)) 4823 y = 0; /* IPv4 */ 4824 else { 4825 MPASS(m->m_pkthdr.csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | 4826 CSUM_INNER_IP6_TCP | CSUM_INNER_IP6_UDP)); 4827 y = 1; /* IPv6 */ 4828 } 4829 /* 4830 * needs_hwcsum returned true earlier so there must be some kind of 4831 * checksum to calculate. 4832 */ 4833 csum_type = csum_types[x][y]; 4834 MPASS(csum_type != 0); 4835 if (csum_type == TX_CSUM_IP) 4836 ctrl |= F_TXPKT_L4CSUM_DIS; 4837 ctrl |= V_TXPKT_CSUM_TYPE(csum_type) | V_TXPKT_IPHDR_LEN(l3hlen); 4838 if (chip_id(sc) <= CHELSIO_T5) 4839 ctrl |= V_TXPKT_ETHHDR_LEN(l2hlen); 4840 else 4841 ctrl |= V_T6_TXPKT_ETHHDR_LEN(l2hlen); 4842 4843 return (ctrl); 4844 } 4845 4846 static inline void * 4847 write_lso_cpl(void *cpl, struct mbuf *m0) 4848 { 4849 struct cpl_tx_pkt_lso_core *lso; 4850 uint32_t ctrl; 4851 4852 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 4853 m0->m_pkthdr.l4hlen > 0, 4854 ("%s: mbuf %p needs TSO but missing header lengths", 4855 __func__, m0)); 4856 4857 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | 4858 F_LSO_FIRST_SLICE | F_LSO_LAST_SLICE | 4859 V_LSO_ETHHDR_LEN((m0->m_pkthdr.l2hlen - ETHER_HDR_LEN) >> 2) | 4860 V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) | 4861 V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2); 4862 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 4863 ctrl |= F_LSO_IPV6; 4864 4865 lso = cpl; 4866 lso->lso_ctrl = htobe32(ctrl); 4867 lso->ipid_ofst = htobe16(0); 4868 lso->mss = htobe16(m0->m_pkthdr.tso_segsz); 4869 lso->seqno_offset = htobe32(0); 4870 lso->len = htobe32(m0->m_pkthdr.len); 4871 4872 return (lso + 1); 4873 } 4874 4875 static void * 4876 write_tnl_lso_cpl(void *cpl, struct mbuf *m0) 4877 { 4878 struct cpl_tx_tnl_lso *tnl_lso = cpl; 4879 uint32_t ctrl; 4880 4881 KASSERT(m0->m_pkthdr.inner_l2hlen > 0 && 4882 m0->m_pkthdr.inner_l3hlen > 0 && m0->m_pkthdr.inner_l4hlen > 0 && 4883 m0->m_pkthdr.inner_l5hlen > 0, 4884 ("%s: mbuf %p needs VXLAN_TSO but missing inner header lengths", 4885 __func__, m0)); 4886 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 4887 m0->m_pkthdr.l4hlen > 0 && m0->m_pkthdr.l5hlen > 0, 4888 ("%s: mbuf %p needs VXLAN_TSO but missing outer header lengths", 4889 __func__, m0)); 4890 4891 /* Outer headers. */ 4892 ctrl = V_CPL_TX_TNL_LSO_OPCODE(CPL_TX_TNL_LSO) | 4893 F_CPL_TX_TNL_LSO_FIRST | F_CPL_TX_TNL_LSO_LAST | 4894 V_CPL_TX_TNL_LSO_ETHHDRLENOUT( 4895 (m0->m_pkthdr.l2hlen - ETHER_HDR_LEN) >> 2) | 4896 V_CPL_TX_TNL_LSO_IPHDRLENOUT(m0->m_pkthdr.l3hlen >> 2) | 4897 F_CPL_TX_TNL_LSO_IPLENSETOUT; 4898 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 4899 ctrl |= F_CPL_TX_TNL_LSO_IPV6OUT; 4900 else { 4901 ctrl |= F_CPL_TX_TNL_LSO_IPHDRCHKOUT | 4902 F_CPL_TX_TNL_LSO_IPIDINCOUT; 4903 } 4904 tnl_lso->op_to_IpIdSplitOut = htobe32(ctrl); 4905 tnl_lso->IpIdOffsetOut = 0; 4906 tnl_lso->UdpLenSetOut_to_TnlHdrLen = 4907 htobe16(F_CPL_TX_TNL_LSO_UDPCHKCLROUT | 4908 F_CPL_TX_TNL_LSO_UDPLENSETOUT | 4909 V_CPL_TX_TNL_LSO_TNLHDRLEN(m0->m_pkthdr.l2hlen + 4910 m0->m_pkthdr.l3hlen + m0->m_pkthdr.l4hlen + 4911 m0->m_pkthdr.l5hlen) | 4912 V_CPL_TX_TNL_LSO_TNLTYPE(TX_TNL_TYPE_VXLAN)); 4913 tnl_lso->r1 = 0; 4914 4915 /* Inner headers. */ 4916 ctrl = V_CPL_TX_TNL_LSO_ETHHDRLEN( 4917 (m0->m_pkthdr.inner_l2hlen - ETHER_HDR_LEN) >> 2) | 4918 V_CPL_TX_TNL_LSO_IPHDRLEN(m0->m_pkthdr.inner_l3hlen >> 2) | 4919 V_CPL_TX_TNL_LSO_TCPHDRLEN(m0->m_pkthdr.inner_l4hlen >> 2); 4920 if (m0->m_pkthdr.inner_l3hlen == sizeof(struct ip6_hdr)) 4921 ctrl |= F_CPL_TX_TNL_LSO_IPV6; 4922 tnl_lso->Flow_to_TcpHdrLen = htobe32(ctrl); 4923 tnl_lso->IpIdOffset = 0; 4924 tnl_lso->IpIdSplit_to_Mss = 4925 htobe16(V_CPL_TX_TNL_LSO_MSS(m0->m_pkthdr.tso_segsz)); 4926 tnl_lso->TCPSeqOffset = 0; 4927 tnl_lso->EthLenOffset_Size = 4928 htobe32(V_CPL_TX_TNL_LSO_SIZE(m0->m_pkthdr.len)); 4929 4930 return (tnl_lso + 1); 4931 } 4932 4933 #define VM_TX_L2HDR_LEN 16 /* ethmacdst to vlantci */ 4934 4935 /* 4936 * Write a VM txpkt WR for this packet to the hardware descriptors, update the 4937 * software descriptor, and advance the pidx. It is guaranteed that enough 4938 * descriptors are available. 4939 * 4940 * The return value is the # of hardware descriptors used. 4941 */ 4942 static u_int 4943 write_txpkt_vm_wr(struct adapter *sc, struct sge_txq *txq, struct mbuf *m0) 4944 { 4945 struct sge_eq *eq; 4946 struct fw_eth_tx_pkt_vm_wr *wr; 4947 struct tx_sdesc *txsd; 4948 struct cpl_tx_pkt_core *cpl; 4949 uint32_t ctrl; /* used in many unrelated places */ 4950 uint64_t ctrl1; 4951 int len16, ndesc, pktlen, nsegs; 4952 caddr_t dst; 4953 4954 TXQ_LOCK_ASSERT_OWNED(txq); 4955 M_ASSERTPKTHDR(m0); 4956 4957 len16 = mbuf_len16(m0); 4958 nsegs = mbuf_nsegs(m0); 4959 pktlen = m0->m_pkthdr.len; 4960 ctrl = sizeof(struct cpl_tx_pkt_core); 4961 if (needs_tso(m0)) 4962 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 4963 ndesc = tx_len16_to_desc(len16); 4964 4965 /* Firmware work request header */ 4966 eq = &txq->eq; 4967 wr = (void *)&eq->desc[eq->pidx]; 4968 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_VM_WR) | 4969 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl)); 4970 4971 ctrl = V_FW_WR_LEN16(len16); 4972 wr->equiq_to_len16 = htobe32(ctrl); 4973 wr->r3[0] = 0; 4974 wr->r3[1] = 0; 4975 4976 /* 4977 * Copy over ethmacdst, ethmacsrc, ethtype, and vlantci. 4978 * vlantci is ignored unless the ethtype is 0x8100, so it's 4979 * simpler to always copy it rather than making it 4980 * conditional. Also, it seems that we do not have to set 4981 * vlantci or fake the ethtype when doing VLAN tag insertion. 4982 */ 4983 m_copydata(m0, 0, VM_TX_L2HDR_LEN, wr->ethmacdst); 4984 4985 if (needs_tso(m0)) { 4986 cpl = write_lso_cpl(wr + 1, m0); 4987 txq->tso_wrs++; 4988 } else 4989 cpl = (void *)(wr + 1); 4990 4991 /* Checksum offload */ 4992 ctrl1 = csum_to_ctrl(sc, m0); 4993 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS)) 4994 txq->txcsum++; /* some hardware assistance provided */ 4995 4996 /* VLAN tag insertion */ 4997 if (needs_vlan_insertion(m0)) { 4998 ctrl1 |= F_TXPKT_VLAN_VLD | 4999 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 5000 txq->vlan_insertion++; 5001 } 5002 5003 /* CPL header */ 5004 cpl->ctrl0 = txq->cpl_ctrl0; 5005 cpl->pack = 0; 5006 cpl->len = htobe16(pktlen); 5007 cpl->ctrl1 = htobe64(ctrl1); 5008 5009 /* SGL */ 5010 dst = (void *)(cpl + 1); 5011 5012 /* 5013 * A packet using TSO will use up an entire descriptor for the 5014 * firmware work request header, LSO CPL, and TX_PKT_XT CPL. 5015 * If this descriptor is the last descriptor in the ring, wrap 5016 * around to the front of the ring explicitly for the start of 5017 * the sgl. 5018 */ 5019 if (dst == (void *)&eq->desc[eq->sidx]) { 5020 dst = (void *)&eq->desc[0]; 5021 write_gl_to_txd(txq, m0, &dst, 0); 5022 } else 5023 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx); 5024 txq->sgl_wrs++; 5025 txq->txpkt_wrs++; 5026 5027 txsd = &txq->sdesc[eq->pidx]; 5028 txsd->m = m0; 5029 txsd->desc_used = ndesc; 5030 5031 return (ndesc); 5032 } 5033 5034 /* 5035 * Write a raw WR to the hardware descriptors, update the software 5036 * descriptor, and advance the pidx. It is guaranteed that enough 5037 * descriptors are available. 5038 * 5039 * The return value is the # of hardware descriptors used. 5040 */ 5041 static u_int 5042 write_raw_wr(struct sge_txq *txq, void *wr, struct mbuf *m0, u_int available) 5043 { 5044 struct sge_eq *eq = &txq->eq; 5045 struct tx_sdesc *txsd; 5046 struct mbuf *m; 5047 caddr_t dst; 5048 int len16, ndesc; 5049 5050 len16 = mbuf_len16(m0); 5051 ndesc = tx_len16_to_desc(len16); 5052 MPASS(ndesc <= available); 5053 5054 dst = wr; 5055 for (m = m0; m != NULL; m = m->m_next) 5056 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len); 5057 5058 txq->raw_wrs++; 5059 5060 txsd = &txq->sdesc[eq->pidx]; 5061 txsd->m = m0; 5062 txsd->desc_used = ndesc; 5063 5064 return (ndesc); 5065 } 5066 5067 /* 5068 * Write a txpkt WR for this packet to the hardware descriptors, update the 5069 * software descriptor, and advance the pidx. It is guaranteed that enough 5070 * descriptors are available. 5071 * 5072 * The return value is the # of hardware descriptors used. 5073 */ 5074 static u_int 5075 write_txpkt_wr(struct adapter *sc, struct sge_txq *txq, struct mbuf *m0, 5076 u_int available) 5077 { 5078 struct sge_eq *eq; 5079 struct fw_eth_tx_pkt_wr *wr; 5080 struct tx_sdesc *txsd; 5081 struct cpl_tx_pkt_core *cpl; 5082 uint32_t ctrl; /* used in many unrelated places */ 5083 uint64_t ctrl1; 5084 int len16, ndesc, pktlen, nsegs; 5085 caddr_t dst; 5086 5087 TXQ_LOCK_ASSERT_OWNED(txq); 5088 M_ASSERTPKTHDR(m0); 5089 5090 len16 = mbuf_len16(m0); 5091 nsegs = mbuf_nsegs(m0); 5092 pktlen = m0->m_pkthdr.len; 5093 ctrl = sizeof(struct cpl_tx_pkt_core); 5094 if (needs_tso(m0)) { 5095 if (needs_vxlan_tso(m0)) 5096 ctrl += sizeof(struct cpl_tx_tnl_lso); 5097 else 5098 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 5099 } else if (!(mbuf_cflags(m0) & MC_NOMAP) && pktlen <= imm_payload(2) && 5100 available >= 2) { 5101 /* Immediate data. Recalculate len16 and set nsegs to 0. */ 5102 ctrl += pktlen; 5103 len16 = howmany(sizeof(struct fw_eth_tx_pkt_wr) + 5104 sizeof(struct cpl_tx_pkt_core) + pktlen, 16); 5105 nsegs = 0; 5106 } 5107 ndesc = tx_len16_to_desc(len16); 5108 MPASS(ndesc <= available); 5109 5110 /* Firmware work request header */ 5111 eq = &txq->eq; 5112 wr = (void *)&eq->desc[eq->pidx]; 5113 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_WR) | 5114 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl)); 5115 5116 ctrl = V_FW_WR_LEN16(len16); 5117 wr->equiq_to_len16 = htobe32(ctrl); 5118 wr->r3 = 0; 5119 5120 if (needs_tso(m0)) { 5121 if (needs_vxlan_tso(m0)) { 5122 cpl = write_tnl_lso_cpl(wr + 1, m0); 5123 txq->vxlan_tso_wrs++; 5124 } else { 5125 cpl = write_lso_cpl(wr + 1, m0); 5126 txq->tso_wrs++; 5127 } 5128 } else 5129 cpl = (void *)(wr + 1); 5130 5131 /* Checksum offload */ 5132 ctrl1 = csum_to_ctrl(sc, m0); 5133 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS)) { 5134 /* some hardware assistance provided */ 5135 if (needs_vxlan_csum(m0)) 5136 txq->vxlan_txcsum++; 5137 else 5138 txq->txcsum++; 5139 } 5140 5141 /* VLAN tag insertion */ 5142 if (needs_vlan_insertion(m0)) { 5143 ctrl1 |= F_TXPKT_VLAN_VLD | 5144 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 5145 txq->vlan_insertion++; 5146 } 5147 5148 /* CPL header */ 5149 cpl->ctrl0 = txq->cpl_ctrl0; 5150 cpl->pack = 0; 5151 cpl->len = htobe16(pktlen); 5152 cpl->ctrl1 = htobe64(ctrl1); 5153 5154 /* SGL */ 5155 dst = (void *)(cpl + 1); 5156 if (__predict_false((uintptr_t)dst == (uintptr_t)&eq->desc[eq->sidx])) 5157 dst = (caddr_t)&eq->desc[0]; 5158 if (nsegs > 0) { 5159 5160 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx); 5161 txq->sgl_wrs++; 5162 } else { 5163 struct mbuf *m; 5164 5165 for (m = m0; m != NULL; m = m->m_next) { 5166 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len); 5167 #ifdef INVARIANTS 5168 pktlen -= m->m_len; 5169 #endif 5170 } 5171 #ifdef INVARIANTS 5172 KASSERT(pktlen == 0, ("%s: %d bytes left.", __func__, pktlen)); 5173 #endif 5174 txq->imm_wrs++; 5175 } 5176 5177 txq->txpkt_wrs++; 5178 5179 txsd = &txq->sdesc[eq->pidx]; 5180 txsd->m = m0; 5181 txsd->desc_used = ndesc; 5182 5183 return (ndesc); 5184 } 5185 5186 static inline bool 5187 cmp_l2hdr(struct txpkts *txp, struct mbuf *m) 5188 { 5189 int len; 5190 5191 MPASS(txp->npkt > 0); 5192 MPASS(m->m_len >= VM_TX_L2HDR_LEN); 5193 5194 if (txp->ethtype == be16toh(ETHERTYPE_VLAN)) 5195 len = VM_TX_L2HDR_LEN; 5196 else 5197 len = sizeof(struct ether_header); 5198 5199 return (memcmp(m->m_data, &txp->ethmacdst[0], len) != 0); 5200 } 5201 5202 static inline void 5203 save_l2hdr(struct txpkts *txp, struct mbuf *m) 5204 { 5205 MPASS(m->m_len >= VM_TX_L2HDR_LEN); 5206 5207 memcpy(&txp->ethmacdst[0], mtod(m, const void *), VM_TX_L2HDR_LEN); 5208 } 5209 5210 static int 5211 add_to_txpkts_vf(struct adapter *sc, struct sge_txq *txq, struct mbuf *m, 5212 int avail, bool *send) 5213 { 5214 struct txpkts *txp = &txq->txp; 5215 5216 /* Cannot have TSO and coalesce at the same time. */ 5217 if (cannot_use_txpkts(m)) { 5218 cannot_coalesce: 5219 *send = txp->npkt > 0; 5220 return (EINVAL); 5221 } 5222 5223 /* VF allows coalescing of type 1 (1 GL) only */ 5224 if (mbuf_nsegs(m) > 1) 5225 goto cannot_coalesce; 5226 5227 *send = false; 5228 if (txp->npkt > 0) { 5229 MPASS(tx_len16_to_desc(txp->len16) <= avail); 5230 MPASS(txp->npkt < txp->max_npkt); 5231 MPASS(txp->wr_type == 1); /* VF supports type 1 only */ 5232 5233 if (tx_len16_to_desc(txp->len16 + txpkts1_len16()) > avail) { 5234 retry_after_send: 5235 *send = true; 5236 return (EAGAIN); 5237 } 5238 if (m->m_pkthdr.len + txp->plen > 65535) 5239 goto retry_after_send; 5240 if (cmp_l2hdr(txp, m)) 5241 goto retry_after_send; 5242 5243 txp->len16 += txpkts1_len16(); 5244 txp->plen += m->m_pkthdr.len; 5245 txp->mb[txp->npkt++] = m; 5246 if (txp->npkt == txp->max_npkt) 5247 *send = true; 5248 } else { 5249 txp->len16 = howmany(sizeof(struct fw_eth_tx_pkts_vm_wr), 16) + 5250 txpkts1_len16(); 5251 if (tx_len16_to_desc(txp->len16) > avail) 5252 goto cannot_coalesce; 5253 txp->npkt = 1; 5254 txp->wr_type = 1; 5255 txp->plen = m->m_pkthdr.len; 5256 txp->mb[0] = m; 5257 save_l2hdr(txp, m); 5258 } 5259 return (0); 5260 } 5261 5262 static int 5263 add_to_txpkts_pf(struct adapter *sc, struct sge_txq *txq, struct mbuf *m, 5264 int avail, bool *send) 5265 { 5266 struct txpkts *txp = &txq->txp; 5267 int nsegs; 5268 5269 MPASS(!(sc->flags & IS_VF)); 5270 5271 /* Cannot have TSO and coalesce at the same time. */ 5272 if (cannot_use_txpkts(m)) { 5273 cannot_coalesce: 5274 *send = txp->npkt > 0; 5275 return (EINVAL); 5276 } 5277 5278 *send = false; 5279 nsegs = mbuf_nsegs(m); 5280 if (txp->npkt == 0) { 5281 if (m->m_pkthdr.len > 65535) 5282 goto cannot_coalesce; 5283 if (nsegs > 1) { 5284 txp->wr_type = 0; 5285 txp->len16 = 5286 howmany(sizeof(struct fw_eth_tx_pkts_wr), 16) + 5287 txpkts0_len16(nsegs); 5288 } else { 5289 txp->wr_type = 1; 5290 txp->len16 = 5291 howmany(sizeof(struct fw_eth_tx_pkts_wr), 16) + 5292 txpkts1_len16(); 5293 } 5294 if (tx_len16_to_desc(txp->len16) > avail) 5295 goto cannot_coalesce; 5296 txp->npkt = 1; 5297 txp->plen = m->m_pkthdr.len; 5298 txp->mb[0] = m; 5299 } else { 5300 MPASS(tx_len16_to_desc(txp->len16) <= avail); 5301 MPASS(txp->npkt < txp->max_npkt); 5302 5303 if (m->m_pkthdr.len + txp->plen > 65535) { 5304 retry_after_send: 5305 *send = true; 5306 return (EAGAIN); 5307 } 5308 5309 MPASS(txp->wr_type == 0 || txp->wr_type == 1); 5310 if (txp->wr_type == 0) { 5311 if (tx_len16_to_desc(txp->len16 + 5312 txpkts0_len16(nsegs)) > min(avail, SGE_MAX_WR_NDESC)) 5313 goto retry_after_send; 5314 txp->len16 += txpkts0_len16(nsegs); 5315 } else { 5316 if (nsegs != 1) 5317 goto retry_after_send; 5318 if (tx_len16_to_desc(txp->len16 + txpkts1_len16()) > 5319 avail) 5320 goto retry_after_send; 5321 txp->len16 += txpkts1_len16(); 5322 } 5323 5324 txp->plen += m->m_pkthdr.len; 5325 txp->mb[txp->npkt++] = m; 5326 if (txp->npkt == txp->max_npkt) 5327 *send = true; 5328 } 5329 return (0); 5330 } 5331 5332 /* 5333 * Write a txpkts WR for the packets in txp to the hardware descriptors, update 5334 * the software descriptor, and advance the pidx. It is guaranteed that enough 5335 * descriptors are available. 5336 * 5337 * The return value is the # of hardware descriptors used. 5338 */ 5339 static u_int 5340 write_txpkts_wr(struct adapter *sc, struct sge_txq *txq) 5341 { 5342 const struct txpkts *txp = &txq->txp; 5343 struct sge_eq *eq = &txq->eq; 5344 struct fw_eth_tx_pkts_wr *wr; 5345 struct tx_sdesc *txsd; 5346 struct cpl_tx_pkt_core *cpl; 5347 uint64_t ctrl1; 5348 int ndesc, i, checkwrap; 5349 struct mbuf *m, *last; 5350 void *flitp; 5351 5352 TXQ_LOCK_ASSERT_OWNED(txq); 5353 MPASS(txp->npkt > 0); 5354 MPASS(txp->len16 <= howmany(SGE_MAX_WR_LEN, 16)); 5355 5356 wr = (void *)&eq->desc[eq->pidx]; 5357 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR)); 5358 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(txp->len16)); 5359 wr->plen = htobe16(txp->plen); 5360 wr->npkt = txp->npkt; 5361 wr->r3 = 0; 5362 wr->type = txp->wr_type; 5363 flitp = wr + 1; 5364 5365 /* 5366 * At this point we are 16B into a hardware descriptor. If checkwrap is 5367 * set then we know the WR is going to wrap around somewhere. We'll 5368 * check for that at appropriate points. 5369 */ 5370 ndesc = tx_len16_to_desc(txp->len16); 5371 last = NULL; 5372 checkwrap = eq->sidx - ndesc < eq->pidx; 5373 for (i = 0; i < txp->npkt; i++) { 5374 m = txp->mb[i]; 5375 if (txp->wr_type == 0) { 5376 struct ulp_txpkt *ulpmc; 5377 struct ulptx_idata *ulpsc; 5378 5379 /* ULP master command */ 5380 ulpmc = flitp; 5381 ulpmc->cmd_dest = htobe32(V_ULPTX_CMD(ULP_TX_PKT) | 5382 V_ULP_TXPKT_DEST(0) | V_ULP_TXPKT_FID(eq->iqid)); 5383 ulpmc->len = htobe32(txpkts0_len16(mbuf_nsegs(m))); 5384 5385 /* ULP subcommand */ 5386 ulpsc = (void *)(ulpmc + 1); 5387 ulpsc->cmd_more = htobe32(V_ULPTX_CMD(ULP_TX_SC_IMM) | 5388 F_ULP_TX_SC_MORE); 5389 ulpsc->len = htobe32(sizeof(struct cpl_tx_pkt_core)); 5390 5391 cpl = (void *)(ulpsc + 1); 5392 if (checkwrap && 5393 (uintptr_t)cpl == (uintptr_t)&eq->desc[eq->sidx]) 5394 cpl = (void *)&eq->desc[0]; 5395 } else { 5396 cpl = flitp; 5397 } 5398 5399 /* Checksum offload */ 5400 ctrl1 = csum_to_ctrl(sc, m); 5401 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS)) { 5402 /* some hardware assistance provided */ 5403 if (needs_vxlan_csum(m)) 5404 txq->vxlan_txcsum++; 5405 else 5406 txq->txcsum++; 5407 } 5408 5409 /* VLAN tag insertion */ 5410 if (needs_vlan_insertion(m)) { 5411 ctrl1 |= F_TXPKT_VLAN_VLD | 5412 V_TXPKT_VLAN(m->m_pkthdr.ether_vtag); 5413 txq->vlan_insertion++; 5414 } 5415 5416 /* CPL header */ 5417 cpl->ctrl0 = txq->cpl_ctrl0; 5418 cpl->pack = 0; 5419 cpl->len = htobe16(m->m_pkthdr.len); 5420 cpl->ctrl1 = htobe64(ctrl1); 5421 5422 flitp = cpl + 1; 5423 if (checkwrap && 5424 (uintptr_t)flitp == (uintptr_t)&eq->desc[eq->sidx]) 5425 flitp = (void *)&eq->desc[0]; 5426 5427 write_gl_to_txd(txq, m, (caddr_t *)(&flitp), checkwrap); 5428 5429 if (last != NULL) 5430 last->m_nextpkt = m; 5431 last = m; 5432 } 5433 5434 txq->sgl_wrs++; 5435 if (txp->wr_type == 0) { 5436 txq->txpkts0_pkts += txp->npkt; 5437 txq->txpkts0_wrs++; 5438 } else { 5439 txq->txpkts1_pkts += txp->npkt; 5440 txq->txpkts1_wrs++; 5441 } 5442 5443 txsd = &txq->sdesc[eq->pidx]; 5444 txsd->m = txp->mb[0]; 5445 txsd->desc_used = ndesc; 5446 5447 return (ndesc); 5448 } 5449 5450 static u_int 5451 write_txpkts_vm_wr(struct adapter *sc, struct sge_txq *txq) 5452 { 5453 const struct txpkts *txp = &txq->txp; 5454 struct sge_eq *eq = &txq->eq; 5455 struct fw_eth_tx_pkts_vm_wr *wr; 5456 struct tx_sdesc *txsd; 5457 struct cpl_tx_pkt_core *cpl; 5458 uint64_t ctrl1; 5459 int ndesc, i; 5460 struct mbuf *m, *last; 5461 void *flitp; 5462 5463 TXQ_LOCK_ASSERT_OWNED(txq); 5464 MPASS(txp->npkt > 0); 5465 MPASS(txp->wr_type == 1); /* VF supports type 1 only */ 5466 MPASS(txp->mb[0] != NULL); 5467 MPASS(txp->len16 <= howmany(SGE_MAX_WR_LEN, 16)); 5468 5469 wr = (void *)&eq->desc[eq->pidx]; 5470 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_VM_WR)); 5471 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(txp->len16)); 5472 wr->r3 = 0; 5473 wr->plen = htobe16(txp->plen); 5474 wr->npkt = txp->npkt; 5475 wr->r4 = 0; 5476 memcpy(&wr->ethmacdst[0], &txp->ethmacdst[0], 16); 5477 flitp = wr + 1; 5478 5479 /* 5480 * At this point we are 32B into a hardware descriptor. Each mbuf in 5481 * the WR will take 32B so we check for the end of the descriptor ring 5482 * before writing odd mbufs (mb[1], 3, 5, ..) 5483 */ 5484 ndesc = tx_len16_to_desc(txp->len16); 5485 last = NULL; 5486 for (i = 0; i < txp->npkt; i++) { 5487 m = txp->mb[i]; 5488 if (i & 1 && (uintptr_t)flitp == (uintptr_t)&eq->desc[eq->sidx]) 5489 flitp = &eq->desc[0]; 5490 cpl = flitp; 5491 5492 /* Checksum offload */ 5493 ctrl1 = csum_to_ctrl(sc, m); 5494 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS)) 5495 txq->txcsum++; /* some hardware assistance provided */ 5496 5497 /* VLAN tag insertion */ 5498 if (needs_vlan_insertion(m)) { 5499 ctrl1 |= F_TXPKT_VLAN_VLD | 5500 V_TXPKT_VLAN(m->m_pkthdr.ether_vtag); 5501 txq->vlan_insertion++; 5502 } 5503 5504 /* CPL header */ 5505 cpl->ctrl0 = txq->cpl_ctrl0; 5506 cpl->pack = 0; 5507 cpl->len = htobe16(m->m_pkthdr.len); 5508 cpl->ctrl1 = htobe64(ctrl1); 5509 5510 flitp = cpl + 1; 5511 MPASS(mbuf_nsegs(m) == 1); 5512 write_gl_to_txd(txq, m, (caddr_t *)(&flitp), 0); 5513 5514 if (last != NULL) 5515 last->m_nextpkt = m; 5516 last = m; 5517 } 5518 5519 txq->sgl_wrs++; 5520 txq->txpkts1_pkts += txp->npkt; 5521 txq->txpkts1_wrs++; 5522 5523 txsd = &txq->sdesc[eq->pidx]; 5524 txsd->m = txp->mb[0]; 5525 txsd->desc_used = ndesc; 5526 5527 return (ndesc); 5528 } 5529 5530 /* 5531 * If the SGL ends on an address that is not 16 byte aligned, this function will 5532 * add a 0 filled flit at the end. 5533 */ 5534 static void 5535 write_gl_to_txd(struct sge_txq *txq, struct mbuf *m, caddr_t *to, int checkwrap) 5536 { 5537 struct sge_eq *eq = &txq->eq; 5538 struct sglist *gl = txq->gl; 5539 struct sglist_seg *seg; 5540 __be64 *flitp, *wrap; 5541 struct ulptx_sgl *usgl; 5542 int i, nflits, nsegs; 5543 5544 KASSERT(((uintptr_t)(*to) & 0xf) == 0, 5545 ("%s: SGL must start at a 16 byte boundary: %p", __func__, *to)); 5546 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]); 5547 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]); 5548 5549 get_pkt_gl(m, gl); 5550 nsegs = gl->sg_nseg; 5551 MPASS(nsegs > 0); 5552 5553 nflits = (3 * (nsegs - 1)) / 2 + ((nsegs - 1) & 1) + 2; 5554 flitp = (__be64 *)(*to); 5555 wrap = (__be64 *)(&eq->desc[eq->sidx]); 5556 seg = &gl->sg_segs[0]; 5557 usgl = (void *)flitp; 5558 5559 /* 5560 * We start at a 16 byte boundary somewhere inside the tx descriptor 5561 * ring, so we're at least 16 bytes away from the status page. There is 5562 * no chance of a wrap around in the middle of usgl (which is 16 bytes). 5563 */ 5564 5565 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 5566 V_ULPTX_NSGE(nsegs)); 5567 usgl->len0 = htobe32(seg->ss_len); 5568 usgl->addr0 = htobe64(seg->ss_paddr); 5569 seg++; 5570 5571 if (checkwrap == 0 || (uintptr_t)(flitp + nflits) <= (uintptr_t)wrap) { 5572 5573 /* Won't wrap around at all */ 5574 5575 for (i = 0; i < nsegs - 1; i++, seg++) { 5576 usgl->sge[i / 2].len[i & 1] = htobe32(seg->ss_len); 5577 usgl->sge[i / 2].addr[i & 1] = htobe64(seg->ss_paddr); 5578 } 5579 if (i & 1) 5580 usgl->sge[i / 2].len[1] = htobe32(0); 5581 flitp += nflits; 5582 } else { 5583 5584 /* Will wrap somewhere in the rest of the SGL */ 5585 5586 /* 2 flits already written, write the rest flit by flit */ 5587 flitp = (void *)(usgl + 1); 5588 for (i = 0; i < nflits - 2; i++) { 5589 if (flitp == wrap) 5590 flitp = (void *)eq->desc; 5591 *flitp++ = get_flit(seg, nsegs - 1, i); 5592 } 5593 } 5594 5595 if (nflits & 1) { 5596 MPASS(((uintptr_t)flitp) & 0xf); 5597 *flitp++ = 0; 5598 } 5599 5600 MPASS((((uintptr_t)flitp) & 0xf) == 0); 5601 if (__predict_false(flitp == wrap)) 5602 *to = (void *)eq->desc; 5603 else 5604 *to = (void *)flitp; 5605 } 5606 5607 static inline void 5608 copy_to_txd(struct sge_eq *eq, caddr_t from, caddr_t *to, int len) 5609 { 5610 5611 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]); 5612 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]); 5613 5614 if (__predict_true((uintptr_t)(*to) + len <= 5615 (uintptr_t)&eq->desc[eq->sidx])) { 5616 bcopy(from, *to, len); 5617 (*to) += len; 5618 } else { 5619 int portion = (uintptr_t)&eq->desc[eq->sidx] - (uintptr_t)(*to); 5620 5621 bcopy(from, *to, portion); 5622 from += portion; 5623 portion = len - portion; /* remaining */ 5624 bcopy(from, (void *)eq->desc, portion); 5625 (*to) = (caddr_t)eq->desc + portion; 5626 } 5627 } 5628 5629 static inline void 5630 ring_eq_db(struct adapter *sc, struct sge_eq *eq, u_int n) 5631 { 5632 u_int db; 5633 5634 MPASS(n > 0); 5635 5636 db = eq->doorbells; 5637 if (n > 1) 5638 clrbit(&db, DOORBELL_WCWR); 5639 wmb(); 5640 5641 switch (ffs(db) - 1) { 5642 case DOORBELL_UDB: 5643 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n)); 5644 break; 5645 5646 case DOORBELL_WCWR: { 5647 volatile uint64_t *dst, *src; 5648 int i; 5649 5650 /* 5651 * Queues whose 128B doorbell segment fits in the page do not 5652 * use relative qid (udb_qid is always 0). Only queues with 5653 * doorbell segments can do WCWR. 5654 */ 5655 KASSERT(eq->udb_qid == 0 && n == 1, 5656 ("%s: inappropriate doorbell (0x%x, %d, %d) for eq %p", 5657 __func__, eq->doorbells, n, eq->dbidx, eq)); 5658 5659 dst = (volatile void *)((uintptr_t)eq->udb + UDBS_WR_OFFSET - 5660 UDBS_DB_OFFSET); 5661 i = eq->dbidx; 5662 src = (void *)&eq->desc[i]; 5663 while (src != (void *)&eq->desc[i + 1]) 5664 *dst++ = *src++; 5665 wmb(); 5666 break; 5667 } 5668 5669 case DOORBELL_UDBWC: 5670 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n)); 5671 wmb(); 5672 break; 5673 5674 case DOORBELL_KDB: 5675 t4_write_reg(sc, sc->sge_kdoorbell_reg, 5676 V_QID(eq->cntxt_id) | V_PIDX(n)); 5677 break; 5678 } 5679 5680 IDXINCR(eq->dbidx, n, eq->sidx); 5681 } 5682 5683 static inline u_int 5684 reclaimable_tx_desc(struct sge_eq *eq) 5685 { 5686 uint16_t hw_cidx; 5687 5688 hw_cidx = read_hw_cidx(eq); 5689 return (IDXDIFF(hw_cidx, eq->cidx, eq->sidx)); 5690 } 5691 5692 static inline u_int 5693 total_available_tx_desc(struct sge_eq *eq) 5694 { 5695 uint16_t hw_cidx, pidx; 5696 5697 hw_cidx = read_hw_cidx(eq); 5698 pidx = eq->pidx; 5699 5700 if (pidx == hw_cidx) 5701 return (eq->sidx - 1); 5702 else 5703 return (IDXDIFF(hw_cidx, pidx, eq->sidx) - 1); 5704 } 5705 5706 static inline uint16_t 5707 read_hw_cidx(struct sge_eq *eq) 5708 { 5709 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx]; 5710 uint16_t cidx = spg->cidx; /* stable snapshot */ 5711 5712 return (be16toh(cidx)); 5713 } 5714 5715 /* 5716 * Reclaim 'n' descriptors approximately. 5717 */ 5718 static u_int 5719 reclaim_tx_descs(struct sge_txq *txq, u_int n) 5720 { 5721 struct tx_sdesc *txsd; 5722 struct sge_eq *eq = &txq->eq; 5723 u_int can_reclaim, reclaimed; 5724 5725 TXQ_LOCK_ASSERT_OWNED(txq); 5726 MPASS(n > 0); 5727 5728 reclaimed = 0; 5729 can_reclaim = reclaimable_tx_desc(eq); 5730 while (can_reclaim && reclaimed < n) { 5731 int ndesc; 5732 struct mbuf *m, *nextpkt; 5733 5734 txsd = &txq->sdesc[eq->cidx]; 5735 ndesc = txsd->desc_used; 5736 5737 /* Firmware doesn't return "partial" credits. */ 5738 KASSERT(can_reclaim >= ndesc, 5739 ("%s: unexpected number of credits: %d, %d", 5740 __func__, can_reclaim, ndesc)); 5741 KASSERT(ndesc != 0, 5742 ("%s: descriptor with no credits: cidx %d", 5743 __func__, eq->cidx)); 5744 5745 for (m = txsd->m; m != NULL; m = nextpkt) { 5746 nextpkt = m->m_nextpkt; 5747 m->m_nextpkt = NULL; 5748 m_freem(m); 5749 } 5750 reclaimed += ndesc; 5751 can_reclaim -= ndesc; 5752 IDXINCR(eq->cidx, ndesc, eq->sidx); 5753 } 5754 5755 return (reclaimed); 5756 } 5757 5758 static void 5759 tx_reclaim(void *arg, int n) 5760 { 5761 struct sge_txq *txq = arg; 5762 struct sge_eq *eq = &txq->eq; 5763 5764 do { 5765 if (TXQ_TRYLOCK(txq) == 0) 5766 break; 5767 n = reclaim_tx_descs(txq, 32); 5768 if (eq->cidx == eq->pidx) 5769 eq->equeqidx = eq->pidx; 5770 TXQ_UNLOCK(txq); 5771 } while (n > 0); 5772 } 5773 5774 static __be64 5775 get_flit(struct sglist_seg *segs, int nsegs, int idx) 5776 { 5777 int i = (idx / 3) * 2; 5778 5779 switch (idx % 3) { 5780 case 0: { 5781 uint64_t rc; 5782 5783 rc = (uint64_t)segs[i].ss_len << 32; 5784 if (i + 1 < nsegs) 5785 rc |= (uint64_t)(segs[i + 1].ss_len); 5786 5787 return (htobe64(rc)); 5788 } 5789 case 1: 5790 return (htobe64(segs[i].ss_paddr)); 5791 case 2: 5792 return (htobe64(segs[i + 1].ss_paddr)); 5793 } 5794 5795 return (0); 5796 } 5797 5798 static int 5799 find_refill_source(struct adapter *sc, int maxp, bool packing) 5800 { 5801 int i, zidx = -1; 5802 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[0]; 5803 5804 if (packing) { 5805 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) { 5806 if (rxb->hwidx2 == -1) 5807 continue; 5808 if (rxb->size1 < PAGE_SIZE && 5809 rxb->size1 < largest_rx_cluster) 5810 continue; 5811 if (rxb->size1 > largest_rx_cluster) 5812 break; 5813 MPASS(rxb->size1 - rxb->size2 >= CL_METADATA_SIZE); 5814 if (rxb->size2 >= maxp) 5815 return (i); 5816 zidx = i; 5817 } 5818 } else { 5819 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) { 5820 if (rxb->hwidx1 == -1) 5821 continue; 5822 if (rxb->size1 > largest_rx_cluster) 5823 break; 5824 if (rxb->size1 >= maxp) 5825 return (i); 5826 zidx = i; 5827 } 5828 } 5829 5830 return (zidx); 5831 } 5832 5833 static void 5834 add_fl_to_sfl(struct adapter *sc, struct sge_fl *fl) 5835 { 5836 mtx_lock(&sc->sfl_lock); 5837 FL_LOCK(fl); 5838 if ((fl->flags & FL_DOOMED) == 0) { 5839 fl->flags |= FL_STARVING; 5840 TAILQ_INSERT_TAIL(&sc->sfl, fl, link); 5841 callout_reset(&sc->sfl_callout, hz / 5, refill_sfl, sc); 5842 } 5843 FL_UNLOCK(fl); 5844 mtx_unlock(&sc->sfl_lock); 5845 } 5846 5847 static void 5848 handle_wrq_egr_update(struct adapter *sc, struct sge_eq *eq) 5849 { 5850 struct sge_wrq *wrq = (void *)eq; 5851 5852 atomic_readandclear_int(&eq->equiq); 5853 taskqueue_enqueue(sc->tq[eq->tx_chan], &wrq->wrq_tx_task); 5854 } 5855 5856 static void 5857 handle_eth_egr_update(struct adapter *sc, struct sge_eq *eq) 5858 { 5859 struct sge_txq *txq = (void *)eq; 5860 5861 MPASS((eq->flags & EQ_TYPEMASK) == EQ_ETH); 5862 5863 atomic_readandclear_int(&eq->equiq); 5864 if (mp_ring_is_idle(txq->r)) 5865 taskqueue_enqueue(sc->tq[eq->tx_chan], &txq->tx_reclaim_task); 5866 else 5867 mp_ring_check_drainage(txq->r, 64); 5868 } 5869 5870 static int 5871 handle_sge_egr_update(struct sge_iq *iq, const struct rss_header *rss, 5872 struct mbuf *m) 5873 { 5874 const struct cpl_sge_egr_update *cpl = (const void *)(rss + 1); 5875 unsigned int qid = G_EGR_QID(ntohl(cpl->opcode_qid)); 5876 struct adapter *sc = iq->adapter; 5877 struct sge *s = &sc->sge; 5878 struct sge_eq *eq; 5879 static void (*h[])(struct adapter *, struct sge_eq *) = {NULL, 5880 &handle_wrq_egr_update, &handle_eth_egr_update, 5881 &handle_wrq_egr_update}; 5882 5883 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 5884 rss->opcode)); 5885 5886 eq = s->eqmap[qid - s->eq_start - s->eq_base]; 5887 (*h[eq->flags & EQ_TYPEMASK])(sc, eq); 5888 5889 return (0); 5890 } 5891 5892 /* handle_fw_msg works for both fw4_msg and fw6_msg because this is valid */ 5893 CTASSERT(offsetof(struct cpl_fw4_msg, data) == \ 5894 offsetof(struct cpl_fw6_msg, data)); 5895 5896 static int 5897 handle_fw_msg(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 5898 { 5899 struct adapter *sc = iq->adapter; 5900 const struct cpl_fw6_msg *cpl = (const void *)(rss + 1); 5901 5902 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 5903 rss->opcode)); 5904 5905 if (cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL) { 5906 const struct rss_header *rss2; 5907 5908 rss2 = (const struct rss_header *)&cpl->data[0]; 5909 return (t4_cpl_handler[rss2->opcode](iq, rss2, m)); 5910 } 5911 5912 return (t4_fw_msg_handler[cpl->type](sc, &cpl->data[0])); 5913 } 5914 5915 /** 5916 * t4_handle_wrerr_rpl - process a FW work request error message 5917 * @adap: the adapter 5918 * @rpl: start of the FW message 5919 */ 5920 static int 5921 t4_handle_wrerr_rpl(struct adapter *adap, const __be64 *rpl) 5922 { 5923 u8 opcode = *(const u8 *)rpl; 5924 const struct fw_error_cmd *e = (const void *)rpl; 5925 unsigned int i; 5926 5927 if (opcode != FW_ERROR_CMD) { 5928 log(LOG_ERR, 5929 "%s: Received WRERR_RPL message with opcode %#x\n", 5930 device_get_nameunit(adap->dev), opcode); 5931 return (EINVAL); 5932 } 5933 log(LOG_ERR, "%s: FW_ERROR (%s) ", device_get_nameunit(adap->dev), 5934 G_FW_ERROR_CMD_FATAL(be32toh(e->op_to_type)) ? "fatal" : 5935 "non-fatal"); 5936 switch (G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type))) { 5937 case FW_ERROR_TYPE_EXCEPTION: 5938 log(LOG_ERR, "exception info:\n"); 5939 for (i = 0; i < nitems(e->u.exception.info); i++) 5940 log(LOG_ERR, "%s%08x", i == 0 ? "\t" : " ", 5941 be32toh(e->u.exception.info[i])); 5942 log(LOG_ERR, "\n"); 5943 break; 5944 case FW_ERROR_TYPE_HWMODULE: 5945 log(LOG_ERR, "HW module regaddr %08x regval %08x\n", 5946 be32toh(e->u.hwmodule.regaddr), 5947 be32toh(e->u.hwmodule.regval)); 5948 break; 5949 case FW_ERROR_TYPE_WR: 5950 log(LOG_ERR, "WR cidx %d PF %d VF %d eqid %d hdr:\n", 5951 be16toh(e->u.wr.cidx), 5952 G_FW_ERROR_CMD_PFN(be16toh(e->u.wr.pfn_vfn)), 5953 G_FW_ERROR_CMD_VFN(be16toh(e->u.wr.pfn_vfn)), 5954 be32toh(e->u.wr.eqid)); 5955 for (i = 0; i < nitems(e->u.wr.wrhdr); i++) 5956 log(LOG_ERR, "%s%02x", i == 0 ? "\t" : " ", 5957 e->u.wr.wrhdr[i]); 5958 log(LOG_ERR, "\n"); 5959 break; 5960 case FW_ERROR_TYPE_ACL: 5961 log(LOG_ERR, "ACL cidx %d PF %d VF %d eqid %d %s", 5962 be16toh(e->u.acl.cidx), 5963 G_FW_ERROR_CMD_PFN(be16toh(e->u.acl.pfn_vfn)), 5964 G_FW_ERROR_CMD_VFN(be16toh(e->u.acl.pfn_vfn)), 5965 be32toh(e->u.acl.eqid), 5966 G_FW_ERROR_CMD_MV(be16toh(e->u.acl.mv_pkd)) ? "vlanid" : 5967 "MAC"); 5968 for (i = 0; i < nitems(e->u.acl.val); i++) 5969 log(LOG_ERR, " %02x", e->u.acl.val[i]); 5970 log(LOG_ERR, "\n"); 5971 break; 5972 default: 5973 log(LOG_ERR, "type %#x\n", 5974 G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type))); 5975 return (EINVAL); 5976 } 5977 return (0); 5978 } 5979 5980 int 5981 sysctl_uint16(SYSCTL_HANDLER_ARGS) 5982 { 5983 uint16_t *id = arg1; 5984 int i = *id; 5985 5986 return sysctl_handle_int(oidp, &i, 0, req); 5987 } 5988 5989 static inline bool 5990 bufidx_used(struct adapter *sc, int idx) 5991 { 5992 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[0]; 5993 int i; 5994 5995 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) { 5996 if (rxb->size1 > largest_rx_cluster) 5997 continue; 5998 if (rxb->hwidx1 == idx || rxb->hwidx2 == idx) 5999 return (true); 6000 } 6001 6002 return (false); 6003 } 6004 6005 static int 6006 sysctl_bufsizes(SYSCTL_HANDLER_ARGS) 6007 { 6008 struct adapter *sc = arg1; 6009 struct sge_params *sp = &sc->params.sge; 6010 int i, rc; 6011 struct sbuf sb; 6012 char c; 6013 6014 sbuf_new(&sb, NULL, 128, SBUF_AUTOEXTEND); 6015 for (i = 0; i < SGE_FLBUF_SIZES; i++) { 6016 if (bufidx_used(sc, i)) 6017 c = '*'; 6018 else 6019 c = '\0'; 6020 6021 sbuf_printf(&sb, "%u%c ", sp->sge_fl_buffer_size[i], c); 6022 } 6023 sbuf_trim(&sb); 6024 sbuf_finish(&sb); 6025 rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req); 6026 sbuf_delete(&sb); 6027 return (rc); 6028 } 6029 6030 #ifdef RATELIMIT 6031 /* 6032 * len16 for a txpkt WR with a GL. Includes the firmware work request header. 6033 */ 6034 static inline u_int 6035 txpkt_eo_len16(u_int nsegs, u_int immhdrs, u_int tso) 6036 { 6037 u_int n; 6038 6039 MPASS(immhdrs > 0); 6040 6041 n = roundup2(sizeof(struct fw_eth_tx_eo_wr) + 6042 sizeof(struct cpl_tx_pkt_core) + immhdrs, 16); 6043 if (__predict_false(nsegs == 0)) 6044 goto done; 6045 6046 nsegs--; /* first segment is part of ulptx_sgl */ 6047 n += sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 6048 if (tso) 6049 n += sizeof(struct cpl_tx_pkt_lso_core); 6050 6051 done: 6052 return (howmany(n, 16)); 6053 } 6054 6055 #define ETID_FLOWC_NPARAMS 6 6056 #define ETID_FLOWC_LEN (roundup2((sizeof(struct fw_flowc_wr) + \ 6057 ETID_FLOWC_NPARAMS * sizeof(struct fw_flowc_mnemval)), 16)) 6058 #define ETID_FLOWC_LEN16 (howmany(ETID_FLOWC_LEN, 16)) 6059 6060 static int 6061 send_etid_flowc_wr(struct cxgbe_rate_tag *cst, struct port_info *pi, 6062 struct vi_info *vi) 6063 { 6064 struct wrq_cookie cookie; 6065 u_int pfvf = pi->adapter->pf << S_FW_VIID_PFN; 6066 struct fw_flowc_wr *flowc; 6067 6068 mtx_assert(&cst->lock, MA_OWNED); 6069 MPASS((cst->flags & (EO_FLOWC_PENDING | EO_FLOWC_RPL_PENDING)) == 6070 EO_FLOWC_PENDING); 6071 6072 flowc = start_wrq_wr(cst->eo_txq, ETID_FLOWC_LEN16, &cookie); 6073 if (__predict_false(flowc == NULL)) 6074 return (ENOMEM); 6075 6076 bzero(flowc, ETID_FLOWC_LEN); 6077 flowc->op_to_nparams = htobe32(V_FW_WR_OP(FW_FLOWC_WR) | 6078 V_FW_FLOWC_WR_NPARAMS(ETID_FLOWC_NPARAMS) | V_FW_WR_COMPL(0)); 6079 flowc->flowid_len16 = htonl(V_FW_WR_LEN16(ETID_FLOWC_LEN16) | 6080 V_FW_WR_FLOWID(cst->etid)); 6081 flowc->mnemval[0].mnemonic = FW_FLOWC_MNEM_PFNVFN; 6082 flowc->mnemval[0].val = htobe32(pfvf); 6083 flowc->mnemval[1].mnemonic = FW_FLOWC_MNEM_CH; 6084 flowc->mnemval[1].val = htobe32(pi->tx_chan); 6085 flowc->mnemval[2].mnemonic = FW_FLOWC_MNEM_PORT; 6086 flowc->mnemval[2].val = htobe32(pi->tx_chan); 6087 flowc->mnemval[3].mnemonic = FW_FLOWC_MNEM_IQID; 6088 flowc->mnemval[3].val = htobe32(cst->iqid); 6089 flowc->mnemval[4].mnemonic = FW_FLOWC_MNEM_EOSTATE; 6090 flowc->mnemval[4].val = htobe32(FW_FLOWC_MNEM_EOSTATE_ESTABLISHED); 6091 flowc->mnemval[5].mnemonic = FW_FLOWC_MNEM_SCHEDCLASS; 6092 flowc->mnemval[5].val = htobe32(cst->schedcl); 6093 6094 commit_wrq_wr(cst->eo_txq, flowc, &cookie); 6095 6096 cst->flags &= ~EO_FLOWC_PENDING; 6097 cst->flags |= EO_FLOWC_RPL_PENDING; 6098 MPASS(cst->tx_credits >= ETID_FLOWC_LEN16); /* flowc is first WR. */ 6099 cst->tx_credits -= ETID_FLOWC_LEN16; 6100 6101 return (0); 6102 } 6103 6104 #define ETID_FLUSH_LEN16 (howmany(sizeof (struct fw_flowc_wr), 16)) 6105 6106 void 6107 send_etid_flush_wr(struct cxgbe_rate_tag *cst) 6108 { 6109 struct fw_flowc_wr *flowc; 6110 struct wrq_cookie cookie; 6111 6112 mtx_assert(&cst->lock, MA_OWNED); 6113 6114 flowc = start_wrq_wr(cst->eo_txq, ETID_FLUSH_LEN16, &cookie); 6115 if (__predict_false(flowc == NULL)) 6116 CXGBE_UNIMPLEMENTED(__func__); 6117 6118 bzero(flowc, ETID_FLUSH_LEN16 * 16); 6119 flowc->op_to_nparams = htobe32(V_FW_WR_OP(FW_FLOWC_WR) | 6120 V_FW_FLOWC_WR_NPARAMS(0) | F_FW_WR_COMPL); 6121 flowc->flowid_len16 = htobe32(V_FW_WR_LEN16(ETID_FLUSH_LEN16) | 6122 V_FW_WR_FLOWID(cst->etid)); 6123 6124 commit_wrq_wr(cst->eo_txq, flowc, &cookie); 6125 6126 cst->flags |= EO_FLUSH_RPL_PENDING; 6127 MPASS(cst->tx_credits >= ETID_FLUSH_LEN16); 6128 cst->tx_credits -= ETID_FLUSH_LEN16; 6129 cst->ncompl++; 6130 } 6131 6132 static void 6133 write_ethofld_wr(struct cxgbe_rate_tag *cst, struct fw_eth_tx_eo_wr *wr, 6134 struct mbuf *m0, int compl) 6135 { 6136 struct cpl_tx_pkt_core *cpl; 6137 uint64_t ctrl1; 6138 uint32_t ctrl; /* used in many unrelated places */ 6139 int len16, pktlen, nsegs, immhdrs; 6140 caddr_t dst; 6141 uintptr_t p; 6142 struct ulptx_sgl *usgl; 6143 struct sglist sg; 6144 struct sglist_seg segs[38]; /* XXX: find real limit. XXX: get off the stack */ 6145 6146 mtx_assert(&cst->lock, MA_OWNED); 6147 M_ASSERTPKTHDR(m0); 6148 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 6149 m0->m_pkthdr.l4hlen > 0, 6150 ("%s: ethofld mbuf %p is missing header lengths", __func__, m0)); 6151 6152 len16 = mbuf_eo_len16(m0); 6153 nsegs = mbuf_eo_nsegs(m0); 6154 pktlen = m0->m_pkthdr.len; 6155 ctrl = sizeof(struct cpl_tx_pkt_core); 6156 if (needs_tso(m0)) 6157 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 6158 immhdrs = m0->m_pkthdr.l2hlen + m0->m_pkthdr.l3hlen + m0->m_pkthdr.l4hlen; 6159 ctrl += immhdrs; 6160 6161 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_EO_WR) | 6162 V_FW_ETH_TX_EO_WR_IMMDLEN(ctrl) | V_FW_WR_COMPL(!!compl)); 6163 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(len16) | 6164 V_FW_WR_FLOWID(cst->etid)); 6165 wr->r3 = 0; 6166 if (needs_outer_udp_csum(m0)) { 6167 wr->u.udpseg.type = FW_ETH_TX_EO_TYPE_UDPSEG; 6168 wr->u.udpseg.ethlen = m0->m_pkthdr.l2hlen; 6169 wr->u.udpseg.iplen = htobe16(m0->m_pkthdr.l3hlen); 6170 wr->u.udpseg.udplen = m0->m_pkthdr.l4hlen; 6171 wr->u.udpseg.rtplen = 0; 6172 wr->u.udpseg.r4 = 0; 6173 wr->u.udpseg.mss = htobe16(pktlen - immhdrs); 6174 wr->u.udpseg.schedpktsize = wr->u.udpseg.mss; 6175 wr->u.udpseg.plen = htobe32(pktlen - immhdrs); 6176 cpl = (void *)(wr + 1); 6177 } else { 6178 MPASS(needs_outer_tcp_csum(m0)); 6179 wr->u.tcpseg.type = FW_ETH_TX_EO_TYPE_TCPSEG; 6180 wr->u.tcpseg.ethlen = m0->m_pkthdr.l2hlen; 6181 wr->u.tcpseg.iplen = htobe16(m0->m_pkthdr.l3hlen); 6182 wr->u.tcpseg.tcplen = m0->m_pkthdr.l4hlen; 6183 wr->u.tcpseg.tsclk_tsoff = mbuf_eo_tsclk_tsoff(m0); 6184 wr->u.tcpseg.r4 = 0; 6185 wr->u.tcpseg.r5 = 0; 6186 wr->u.tcpseg.plen = htobe32(pktlen - immhdrs); 6187 6188 if (needs_tso(m0)) { 6189 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1); 6190 6191 wr->u.tcpseg.mss = htobe16(m0->m_pkthdr.tso_segsz); 6192 6193 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | 6194 F_LSO_FIRST_SLICE | F_LSO_LAST_SLICE | 6195 V_LSO_ETHHDR_LEN((m0->m_pkthdr.l2hlen - 6196 ETHER_HDR_LEN) >> 2) | 6197 V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) | 6198 V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2); 6199 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 6200 ctrl |= F_LSO_IPV6; 6201 lso->lso_ctrl = htobe32(ctrl); 6202 lso->ipid_ofst = htobe16(0); 6203 lso->mss = htobe16(m0->m_pkthdr.tso_segsz); 6204 lso->seqno_offset = htobe32(0); 6205 lso->len = htobe32(pktlen); 6206 6207 cpl = (void *)(lso + 1); 6208 } else { 6209 wr->u.tcpseg.mss = htobe16(0xffff); 6210 cpl = (void *)(wr + 1); 6211 } 6212 } 6213 6214 /* Checksum offload must be requested for ethofld. */ 6215 MPASS(needs_outer_l4_csum(m0)); 6216 ctrl1 = csum_to_ctrl(cst->adapter, m0); 6217 6218 /* VLAN tag insertion */ 6219 if (needs_vlan_insertion(m0)) { 6220 ctrl1 |= F_TXPKT_VLAN_VLD | 6221 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 6222 } 6223 6224 /* CPL header */ 6225 cpl->ctrl0 = cst->ctrl0; 6226 cpl->pack = 0; 6227 cpl->len = htobe16(pktlen); 6228 cpl->ctrl1 = htobe64(ctrl1); 6229 6230 /* Copy Ethernet, IP & TCP/UDP hdrs as immediate data */ 6231 p = (uintptr_t)(cpl + 1); 6232 m_copydata(m0, 0, immhdrs, (void *)p); 6233 6234 /* SGL */ 6235 dst = (void *)(cpl + 1); 6236 if (nsegs > 0) { 6237 int i, pad; 6238 6239 /* zero-pad upto next 16Byte boundary, if not 16Byte aligned */ 6240 p += immhdrs; 6241 pad = 16 - (immhdrs & 0xf); 6242 bzero((void *)p, pad); 6243 6244 usgl = (void *)(p + pad); 6245 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 6246 V_ULPTX_NSGE(nsegs)); 6247 6248 sglist_init(&sg, nitems(segs), segs); 6249 for (; m0 != NULL; m0 = m0->m_next) { 6250 if (__predict_false(m0->m_len == 0)) 6251 continue; 6252 if (immhdrs >= m0->m_len) { 6253 immhdrs -= m0->m_len; 6254 continue; 6255 } 6256 if (m0->m_flags & M_EXTPG) 6257 sglist_append_mbuf_epg(&sg, m0, 6258 mtod(m0, vm_offset_t), m0->m_len); 6259 else 6260 sglist_append(&sg, mtod(m0, char *) + immhdrs, 6261 m0->m_len - immhdrs); 6262 immhdrs = 0; 6263 } 6264 MPASS(sg.sg_nseg == nsegs); 6265 6266 /* 6267 * Zero pad last 8B in case the WR doesn't end on a 16B 6268 * boundary. 6269 */ 6270 *(uint64_t *)((char *)wr + len16 * 16 - 8) = 0; 6271 6272 usgl->len0 = htobe32(segs[0].ss_len); 6273 usgl->addr0 = htobe64(segs[0].ss_paddr); 6274 for (i = 0; i < nsegs - 1; i++) { 6275 usgl->sge[i / 2].len[i & 1] = htobe32(segs[i + 1].ss_len); 6276 usgl->sge[i / 2].addr[i & 1] = htobe64(segs[i + 1].ss_paddr); 6277 } 6278 if (i & 1) 6279 usgl->sge[i / 2].len[1] = htobe32(0); 6280 } 6281 6282 } 6283 6284 static void 6285 ethofld_tx(struct cxgbe_rate_tag *cst) 6286 { 6287 struct mbuf *m; 6288 struct wrq_cookie cookie; 6289 int next_credits, compl; 6290 struct fw_eth_tx_eo_wr *wr; 6291 6292 mtx_assert(&cst->lock, MA_OWNED); 6293 6294 while ((m = mbufq_first(&cst->pending_tx)) != NULL) { 6295 M_ASSERTPKTHDR(m); 6296 6297 /* How many len16 credits do we need to send this mbuf. */ 6298 next_credits = mbuf_eo_len16(m); 6299 MPASS(next_credits > 0); 6300 if (next_credits > cst->tx_credits) { 6301 /* 6302 * Tx will make progress eventually because there is at 6303 * least one outstanding fw4_ack that will return 6304 * credits and kick the tx. 6305 */ 6306 MPASS(cst->ncompl > 0); 6307 return; 6308 } 6309 wr = start_wrq_wr(cst->eo_txq, next_credits, &cookie); 6310 if (__predict_false(wr == NULL)) { 6311 /* XXX: wishful thinking, not a real assertion. */ 6312 MPASS(cst->ncompl > 0); 6313 return; 6314 } 6315 cst->tx_credits -= next_credits; 6316 cst->tx_nocompl += next_credits; 6317 compl = cst->ncompl == 0 || cst->tx_nocompl >= cst->tx_total / 2; 6318 ETHER_BPF_MTAP(cst->com.ifp, m); 6319 write_ethofld_wr(cst, wr, m, compl); 6320 commit_wrq_wr(cst->eo_txq, wr, &cookie); 6321 if (compl) { 6322 cst->ncompl++; 6323 cst->tx_nocompl = 0; 6324 } 6325 (void) mbufq_dequeue(&cst->pending_tx); 6326 6327 /* 6328 * Drop the mbuf's reference on the tag now rather 6329 * than waiting until m_freem(). This ensures that 6330 * cxgbe_rate_tag_free gets called when the inp drops 6331 * its reference on the tag and there are no more 6332 * mbufs in the pending_tx queue and can flush any 6333 * pending requests. Otherwise if the last mbuf 6334 * doesn't request a completion the etid will never be 6335 * released. 6336 */ 6337 m->m_pkthdr.snd_tag = NULL; 6338 m->m_pkthdr.csum_flags &= ~CSUM_SND_TAG; 6339 m_snd_tag_rele(&cst->com); 6340 6341 mbufq_enqueue(&cst->pending_fwack, m); 6342 } 6343 } 6344 6345 int 6346 ethofld_transmit(struct ifnet *ifp, struct mbuf *m0) 6347 { 6348 struct cxgbe_rate_tag *cst; 6349 int rc; 6350 6351 MPASS(m0->m_nextpkt == NULL); 6352 MPASS(m0->m_pkthdr.csum_flags & CSUM_SND_TAG); 6353 MPASS(m0->m_pkthdr.snd_tag != NULL); 6354 cst = mst_to_crt(m0->m_pkthdr.snd_tag); 6355 6356 mtx_lock(&cst->lock); 6357 MPASS(cst->flags & EO_SND_TAG_REF); 6358 6359 if (__predict_false(cst->flags & EO_FLOWC_PENDING)) { 6360 struct vi_info *vi = ifp->if_softc; 6361 struct port_info *pi = vi->pi; 6362 struct adapter *sc = pi->adapter; 6363 const uint32_t rss_mask = vi->rss_size - 1; 6364 uint32_t rss_hash; 6365 6366 cst->eo_txq = &sc->sge.ofld_txq[vi->first_ofld_txq]; 6367 if (M_HASHTYPE_ISHASH(m0)) 6368 rss_hash = m0->m_pkthdr.flowid; 6369 else 6370 rss_hash = arc4random(); 6371 /* We assume RSS hashing */ 6372 cst->iqid = vi->rss[rss_hash & rss_mask]; 6373 cst->eo_txq += rss_hash % vi->nofldtxq; 6374 rc = send_etid_flowc_wr(cst, pi, vi); 6375 if (rc != 0) 6376 goto done; 6377 } 6378 6379 if (__predict_false(cst->plen + m0->m_pkthdr.len > eo_max_backlog)) { 6380 rc = ENOBUFS; 6381 goto done; 6382 } 6383 6384 mbufq_enqueue(&cst->pending_tx, m0); 6385 cst->plen += m0->m_pkthdr.len; 6386 6387 /* 6388 * Hold an extra reference on the tag while generating work 6389 * requests to ensure that we don't try to free the tag during 6390 * ethofld_tx() in case we are sending the final mbuf after 6391 * the inp was freed. 6392 */ 6393 m_snd_tag_ref(&cst->com); 6394 ethofld_tx(cst); 6395 mtx_unlock(&cst->lock); 6396 m_snd_tag_rele(&cst->com); 6397 return (0); 6398 6399 done: 6400 mtx_unlock(&cst->lock); 6401 if (__predict_false(rc != 0)) 6402 m_freem(m0); 6403 return (rc); 6404 } 6405 6406 static int 6407 ethofld_fw4_ack(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0) 6408 { 6409 struct adapter *sc = iq->adapter; 6410 const struct cpl_fw4_ack *cpl = (const void *)(rss + 1); 6411 struct mbuf *m; 6412 u_int etid = G_CPL_FW4_ACK_FLOWID(be32toh(OPCODE_TID(cpl))); 6413 struct cxgbe_rate_tag *cst; 6414 uint8_t credits = cpl->credits; 6415 6416 cst = lookup_etid(sc, etid); 6417 mtx_lock(&cst->lock); 6418 if (__predict_false(cst->flags & EO_FLOWC_RPL_PENDING)) { 6419 MPASS(credits >= ETID_FLOWC_LEN16); 6420 credits -= ETID_FLOWC_LEN16; 6421 cst->flags &= ~EO_FLOWC_RPL_PENDING; 6422 } 6423 6424 KASSERT(cst->ncompl > 0, 6425 ("%s: etid %u (%p) wasn't expecting completion.", 6426 __func__, etid, cst)); 6427 cst->ncompl--; 6428 6429 while (credits > 0) { 6430 m = mbufq_dequeue(&cst->pending_fwack); 6431 if (__predict_false(m == NULL)) { 6432 /* 6433 * The remaining credits are for the final flush that 6434 * was issued when the tag was freed by the kernel. 6435 */ 6436 MPASS((cst->flags & 6437 (EO_FLUSH_RPL_PENDING | EO_SND_TAG_REF)) == 6438 EO_FLUSH_RPL_PENDING); 6439 MPASS(credits == ETID_FLUSH_LEN16); 6440 MPASS(cst->tx_credits + cpl->credits == cst->tx_total); 6441 MPASS(cst->ncompl == 0); 6442 6443 cst->flags &= ~EO_FLUSH_RPL_PENDING; 6444 cst->tx_credits += cpl->credits; 6445 cxgbe_rate_tag_free_locked(cst); 6446 return (0); /* cst is gone. */ 6447 } 6448 KASSERT(m != NULL, 6449 ("%s: too many credits (%u, %u)", __func__, cpl->credits, 6450 credits)); 6451 KASSERT(credits >= mbuf_eo_len16(m), 6452 ("%s: too few credits (%u, %u, %u)", __func__, 6453 cpl->credits, credits, mbuf_eo_len16(m))); 6454 credits -= mbuf_eo_len16(m); 6455 cst->plen -= m->m_pkthdr.len; 6456 m_freem(m); 6457 } 6458 6459 cst->tx_credits += cpl->credits; 6460 MPASS(cst->tx_credits <= cst->tx_total); 6461 6462 if (cst->flags & EO_SND_TAG_REF) { 6463 /* 6464 * As with ethofld_transmit(), hold an extra reference 6465 * so that the tag is stable across ethold_tx(). 6466 */ 6467 m_snd_tag_ref(&cst->com); 6468 m = mbufq_first(&cst->pending_tx); 6469 if (m != NULL && cst->tx_credits >= mbuf_eo_len16(m)) 6470 ethofld_tx(cst); 6471 mtx_unlock(&cst->lock); 6472 m_snd_tag_rele(&cst->com); 6473 } else { 6474 /* 6475 * There shouldn't be any pending packets if the tag 6476 * was freed by the kernel since any pending packet 6477 * should hold a reference to the tag. 6478 */ 6479 MPASS(mbufq_first(&cst->pending_tx) == NULL); 6480 mtx_unlock(&cst->lock); 6481 } 6482 6483 return (0); 6484 } 6485 #endif 6486