1 /*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 34 #include <sys/types.h> 35 #include <sys/eventhandler.h> 36 #include <sys/mbuf.h> 37 #include <sys/socket.h> 38 #include <sys/kernel.h> 39 #include <sys/malloc.h> 40 #include <sys/queue.h> 41 #include <sys/sbuf.h> 42 #include <sys/taskqueue.h> 43 #include <sys/time.h> 44 #include <sys/sglist.h> 45 #include <sys/sysctl.h> 46 #include <sys/smp.h> 47 #include <sys/counter.h> 48 #include <net/bpf.h> 49 #include <net/ethernet.h> 50 #include <net/if.h> 51 #include <net/if_vlan_var.h> 52 #include <netinet/in.h> 53 #include <netinet/ip.h> 54 #include <netinet/ip6.h> 55 #include <netinet/tcp.h> 56 #include <machine/in_cksum.h> 57 #include <machine/md_var.h> 58 #include <vm/vm.h> 59 #include <vm/pmap.h> 60 #ifdef DEV_NETMAP 61 #include <machine/bus.h> 62 #include <sys/selinfo.h> 63 #include <net/if_var.h> 64 #include <net/netmap.h> 65 #include <dev/netmap/netmap_kern.h> 66 #endif 67 68 #include "common/common.h" 69 #include "common/t4_regs.h" 70 #include "common/t4_regs_values.h" 71 #include "common/t4_msg.h" 72 #include "t4_l2t.h" 73 #include "t4_mp_ring.h" 74 75 #ifdef T4_PKT_TIMESTAMP 76 #define RX_COPY_THRESHOLD (MINCLSIZE - 8) 77 #else 78 #define RX_COPY_THRESHOLD MINCLSIZE 79 #endif 80 81 /* 82 * Ethernet frames are DMA'd at this byte offset into the freelist buffer. 83 * 0-7 are valid values. 84 */ 85 static int fl_pktshift = 2; 86 TUNABLE_INT("hw.cxgbe.fl_pktshift", &fl_pktshift); 87 88 /* 89 * Pad ethernet payload up to this boundary. 90 * -1: driver should figure out a good value. 91 * 0: disable padding. 92 * Any power of 2 from 32 to 4096 (both inclusive) is also a valid value. 93 */ 94 int fl_pad = -1; 95 TUNABLE_INT("hw.cxgbe.fl_pad", &fl_pad); 96 97 /* 98 * Status page length. 99 * -1: driver should figure out a good value. 100 * 64 or 128 are the only other valid values. 101 */ 102 static int spg_len = -1; 103 TUNABLE_INT("hw.cxgbe.spg_len", &spg_len); 104 105 /* 106 * Congestion drops. 107 * -1: no congestion feedback (not recommended). 108 * 0: backpressure the channel instead of dropping packets right away. 109 * 1: no backpressure, drop packets for the congested queue immediately. 110 */ 111 static int cong_drop = 0; 112 TUNABLE_INT("hw.cxgbe.cong_drop", &cong_drop); 113 114 /* 115 * Deliver multiple frames in the same free list buffer if they fit. 116 * -1: let the driver decide whether to enable buffer packing or not. 117 * 0: disable buffer packing. 118 * 1: enable buffer packing. 119 */ 120 static int buffer_packing = -1; 121 TUNABLE_INT("hw.cxgbe.buffer_packing", &buffer_packing); 122 123 /* 124 * Start next frame in a packed buffer at this boundary. 125 * -1: driver should figure out a good value. 126 * T4: driver will ignore this and use the same value as fl_pad above. 127 * T5: 16, or a power of 2 from 64 to 4096 (both inclusive) is a valid value. 128 */ 129 static int fl_pack = -1; 130 TUNABLE_INT("hw.cxgbe.fl_pack", &fl_pack); 131 132 /* 133 * Allow the driver to create mbuf(s) in a cluster allocated for rx. 134 * 0: never; always allocate mbufs from the zone_mbuf UMA zone. 135 * 1: ok to create mbuf(s) within a cluster if there is room. 136 */ 137 static int allow_mbufs_in_cluster = 1; 138 TUNABLE_INT("hw.cxgbe.allow_mbufs_in_cluster", &allow_mbufs_in_cluster); 139 140 /* 141 * Largest rx cluster size that the driver is allowed to allocate. 142 */ 143 static int largest_rx_cluster = MJUM16BYTES; 144 TUNABLE_INT("hw.cxgbe.largest_rx_cluster", &largest_rx_cluster); 145 146 /* 147 * Size of cluster allocation that's most likely to succeed. The driver will 148 * fall back to this size if it fails to allocate clusters larger than this. 149 */ 150 static int safest_rx_cluster = PAGE_SIZE; 151 TUNABLE_INT("hw.cxgbe.safest_rx_cluster", &safest_rx_cluster); 152 153 /* 154 * The interrupt holdoff timers are multiplied by this value on T6+. 155 * 1 and 3-17 (both inclusive) are legal values. 156 */ 157 static int tscale = 1; 158 TUNABLE_INT("hw.cxgbe.tscale", &tscale); 159 160 /* 161 * Number of LRO entries in the lro_ctrl structure per rx queue. 162 */ 163 static int lro_entries = TCP_LRO_ENTRIES; 164 TUNABLE_INT("hw.cxgbe.lro_entries", &lro_entries); 165 166 /* 167 * This enables presorting of frames before they're fed into tcp_lro_rx. 168 */ 169 static int lro_mbufs = 0; 170 TUNABLE_INT("hw.cxgbe.lro_mbufs", &lro_mbufs); 171 172 struct txpkts { 173 u_int wr_type; /* type 0 or type 1 */ 174 u_int npkt; /* # of packets in this work request */ 175 u_int plen; /* total payload (sum of all packets) */ 176 u_int len16; /* # of 16B pieces used by this work request */ 177 }; 178 179 /* A packet's SGL. This + m_pkthdr has all info needed for tx */ 180 struct sgl { 181 struct sglist sg; 182 struct sglist_seg seg[TX_SGL_SEGS]; 183 }; 184 185 static int service_iq(struct sge_iq *, int); 186 static struct mbuf *get_fl_payload(struct adapter *, struct sge_fl *, uint32_t); 187 static int t4_eth_rx(struct sge_iq *, const struct rss_header *, struct mbuf *); 188 static inline void init_iq(struct sge_iq *, struct adapter *, int, int, int); 189 static inline void init_fl(struct adapter *, struct sge_fl *, int, int, char *); 190 static inline void init_eq(struct adapter *, struct sge_eq *, int, int, uint8_t, 191 uint16_t, char *); 192 static int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *, 193 bus_addr_t *, void **); 194 static int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 195 void *); 196 static int alloc_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *, 197 int, int); 198 static int free_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *); 199 static void add_fl_sysctls(struct adapter *, struct sysctl_ctx_list *, 200 struct sysctl_oid *, struct sge_fl *); 201 static int alloc_fwq(struct adapter *); 202 static int free_fwq(struct adapter *); 203 static int alloc_mgmtq(struct adapter *); 204 static int free_mgmtq(struct adapter *); 205 static int alloc_rxq(struct vi_info *, struct sge_rxq *, int, int, 206 struct sysctl_oid *); 207 static int free_rxq(struct vi_info *, struct sge_rxq *); 208 #ifdef TCP_OFFLOAD 209 static int alloc_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *, int, int, 210 struct sysctl_oid *); 211 static int free_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *); 212 #endif 213 #ifdef DEV_NETMAP 214 static int alloc_nm_rxq(struct vi_info *, struct sge_nm_rxq *, int, int, 215 struct sysctl_oid *); 216 static int free_nm_rxq(struct vi_info *, struct sge_nm_rxq *); 217 static int alloc_nm_txq(struct vi_info *, struct sge_nm_txq *, int, int, 218 struct sysctl_oid *); 219 static int free_nm_txq(struct vi_info *, struct sge_nm_txq *); 220 #endif 221 static int ctrl_eq_alloc(struct adapter *, struct sge_eq *); 222 static int eth_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *); 223 #ifdef TCP_OFFLOAD 224 static int ofld_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *); 225 #endif 226 static int alloc_eq(struct adapter *, struct vi_info *, struct sge_eq *); 227 static int free_eq(struct adapter *, struct sge_eq *); 228 static int alloc_wrq(struct adapter *, struct vi_info *, struct sge_wrq *, 229 struct sysctl_oid *); 230 static int free_wrq(struct adapter *, struct sge_wrq *); 231 static int alloc_txq(struct vi_info *, struct sge_txq *, int, 232 struct sysctl_oid *); 233 static int free_txq(struct vi_info *, struct sge_txq *); 234 static void oneseg_dma_callback(void *, bus_dma_segment_t *, int, int); 235 static inline void ring_fl_db(struct adapter *, struct sge_fl *); 236 static int refill_fl(struct adapter *, struct sge_fl *, int); 237 static void refill_sfl(void *); 238 static int alloc_fl_sdesc(struct sge_fl *); 239 static void free_fl_sdesc(struct adapter *, struct sge_fl *); 240 static void find_best_refill_source(struct adapter *, struct sge_fl *, int); 241 static void find_safe_refill_source(struct adapter *, struct sge_fl *); 242 static void add_fl_to_sfl(struct adapter *, struct sge_fl *); 243 244 static inline void get_pkt_gl(struct mbuf *, struct sglist *); 245 static inline u_int txpkt_len16(u_int, u_int); 246 static inline u_int txpkt_vm_len16(u_int, u_int); 247 static inline u_int txpkts0_len16(u_int); 248 static inline u_int txpkts1_len16(void); 249 static u_int write_txpkt_wr(struct sge_txq *, struct fw_eth_tx_pkt_wr *, 250 struct mbuf *, u_int); 251 static u_int write_txpkt_vm_wr(struct adapter *, struct sge_txq *, 252 struct fw_eth_tx_pkt_vm_wr *, struct mbuf *, u_int); 253 static int try_txpkts(struct mbuf *, struct mbuf *, struct txpkts *, u_int); 254 static int add_to_txpkts(struct mbuf *, struct txpkts *, u_int); 255 static u_int write_txpkts_wr(struct sge_txq *, struct fw_eth_tx_pkts_wr *, 256 struct mbuf *, const struct txpkts *, u_int); 257 static void write_gl_to_txd(struct sge_txq *, struct mbuf *, caddr_t *, int); 258 static inline void copy_to_txd(struct sge_eq *, caddr_t, caddr_t *, int); 259 static inline void ring_eq_db(struct adapter *, struct sge_eq *, u_int); 260 static inline uint16_t read_hw_cidx(struct sge_eq *); 261 static inline u_int reclaimable_tx_desc(struct sge_eq *); 262 static inline u_int total_available_tx_desc(struct sge_eq *); 263 static u_int reclaim_tx_descs(struct sge_txq *, u_int); 264 static void tx_reclaim(void *, int); 265 static __be64 get_flit(struct sglist_seg *, int, int); 266 static int handle_sge_egr_update(struct sge_iq *, const struct rss_header *, 267 struct mbuf *); 268 static int handle_fw_msg(struct sge_iq *, const struct rss_header *, 269 struct mbuf *); 270 static int t4_handle_wrerr_rpl(struct adapter *, const __be64 *); 271 static void wrq_tx_drain(void *, int); 272 static void drain_wrq_wr_list(struct adapter *, struct sge_wrq *); 273 274 static int sysctl_uint16(SYSCTL_HANDLER_ARGS); 275 static int sysctl_bufsizes(SYSCTL_HANDLER_ARGS); 276 static int sysctl_tc(SYSCTL_HANDLER_ARGS); 277 278 static counter_u64_t extfree_refs; 279 static counter_u64_t extfree_rels; 280 281 an_handler_t t4_an_handler; 282 fw_msg_handler_t t4_fw_msg_handler[NUM_FW6_TYPES]; 283 cpl_handler_t t4_cpl_handler[NUM_CPL_CMDS]; 284 285 286 static int 287 an_not_handled(struct sge_iq *iq, const struct rsp_ctrl *ctrl) 288 { 289 290 #ifdef INVARIANTS 291 panic("%s: async notification on iq %p (ctrl %p)", __func__, iq, ctrl); 292 #else 293 log(LOG_ERR, "%s: async notification on iq %p (ctrl %p)\n", 294 __func__, iq, ctrl); 295 #endif 296 return (EDOOFUS); 297 } 298 299 int 300 t4_register_an_handler(an_handler_t h) 301 { 302 uintptr_t *loc, new; 303 304 new = h ? (uintptr_t)h : (uintptr_t)an_not_handled; 305 loc = (uintptr_t *) &t4_an_handler; 306 atomic_store_rel_ptr(loc, new); 307 308 return (0); 309 } 310 311 static int 312 fw_msg_not_handled(struct adapter *sc, const __be64 *rpl) 313 { 314 const struct cpl_fw6_msg *cpl = 315 __containerof(rpl, struct cpl_fw6_msg, data[0]); 316 317 #ifdef INVARIANTS 318 panic("%s: fw_msg type %d", __func__, cpl->type); 319 #else 320 log(LOG_ERR, "%s: fw_msg type %d\n", __func__, cpl->type); 321 #endif 322 return (EDOOFUS); 323 } 324 325 int 326 t4_register_fw_msg_handler(int type, fw_msg_handler_t h) 327 { 328 uintptr_t *loc, new; 329 330 if (type >= nitems(t4_fw_msg_handler)) 331 return (EINVAL); 332 333 /* 334 * These are dispatched by the handler for FW{4|6}_CPL_MSG using the CPL 335 * handler dispatch table. Reject any attempt to install a handler for 336 * this subtype. 337 */ 338 if (type == FW_TYPE_RSSCPL || type == FW6_TYPE_RSSCPL) 339 return (EINVAL); 340 341 new = h ? (uintptr_t)h : (uintptr_t)fw_msg_not_handled; 342 loc = (uintptr_t *) &t4_fw_msg_handler[type]; 343 atomic_store_rel_ptr(loc, new); 344 345 return (0); 346 } 347 348 static int 349 cpl_not_handled(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 350 { 351 352 #ifdef INVARIANTS 353 panic("%s: opcode 0x%02x on iq %p with payload %p", 354 __func__, rss->opcode, iq, m); 355 #else 356 log(LOG_ERR, "%s: opcode 0x%02x on iq %p with payload %p\n", 357 __func__, rss->opcode, iq, m); 358 m_freem(m); 359 #endif 360 return (EDOOFUS); 361 } 362 363 int 364 t4_register_cpl_handler(int opcode, cpl_handler_t h) 365 { 366 uintptr_t *loc, new; 367 368 if (opcode >= nitems(t4_cpl_handler)) 369 return (EINVAL); 370 371 new = h ? (uintptr_t)h : (uintptr_t)cpl_not_handled; 372 loc = (uintptr_t *) &t4_cpl_handler[opcode]; 373 atomic_store_rel_ptr(loc, new); 374 375 return (0); 376 } 377 378 /* 379 * Called on MOD_LOAD. Validates and calculates the SGE tunables. 380 */ 381 void 382 t4_sge_modload(void) 383 { 384 int i; 385 386 if (fl_pktshift < 0 || fl_pktshift > 7) { 387 printf("Invalid hw.cxgbe.fl_pktshift value (%d)," 388 " using 2 instead.\n", fl_pktshift); 389 fl_pktshift = 2; 390 } 391 392 if (spg_len != 64 && spg_len != 128) { 393 int len; 394 395 #if defined(__i386__) || defined(__amd64__) 396 len = cpu_clflush_line_size > 64 ? 128 : 64; 397 #else 398 len = 64; 399 #endif 400 if (spg_len != -1) { 401 printf("Invalid hw.cxgbe.spg_len value (%d)," 402 " using %d instead.\n", spg_len, len); 403 } 404 spg_len = len; 405 } 406 407 if (cong_drop < -1 || cong_drop > 1) { 408 printf("Invalid hw.cxgbe.cong_drop value (%d)," 409 " using 0 instead.\n", cong_drop); 410 cong_drop = 0; 411 } 412 413 if (tscale != 1 && (tscale < 3 || tscale > 17)) { 414 printf("Invalid hw.cxgbe.tscale value (%d)," 415 " using 1 instead.\n", tscale); 416 tscale = 1; 417 } 418 419 extfree_refs = counter_u64_alloc(M_WAITOK); 420 extfree_rels = counter_u64_alloc(M_WAITOK); 421 counter_u64_zero(extfree_refs); 422 counter_u64_zero(extfree_rels); 423 424 t4_an_handler = an_not_handled; 425 for (i = 0; i < nitems(t4_fw_msg_handler); i++) 426 t4_fw_msg_handler[i] = fw_msg_not_handled; 427 for (i = 0; i < nitems(t4_cpl_handler); i++) 428 t4_cpl_handler[i] = cpl_not_handled; 429 430 t4_register_cpl_handler(CPL_FW4_MSG, handle_fw_msg); 431 t4_register_cpl_handler(CPL_FW6_MSG, handle_fw_msg); 432 t4_register_cpl_handler(CPL_SGE_EGR_UPDATE, handle_sge_egr_update); 433 t4_register_cpl_handler(CPL_RX_PKT, t4_eth_rx); 434 t4_register_fw_msg_handler(FW6_TYPE_CMD_RPL, t4_handle_fw_rpl); 435 t4_register_fw_msg_handler(FW6_TYPE_WRERR_RPL, t4_handle_wrerr_rpl); 436 } 437 438 void 439 t4_sge_modunload(void) 440 { 441 442 counter_u64_free(extfree_refs); 443 counter_u64_free(extfree_rels); 444 } 445 446 uint64_t 447 t4_sge_extfree_refs(void) 448 { 449 uint64_t refs, rels; 450 451 rels = counter_u64_fetch(extfree_rels); 452 refs = counter_u64_fetch(extfree_refs); 453 454 return (refs - rels); 455 } 456 457 static inline void 458 setup_pad_and_pack_boundaries(struct adapter *sc) 459 { 460 uint32_t v, m; 461 int pad, pack, pad_shift; 462 463 pad_shift = chip_id(sc) > CHELSIO_T5 ? X_T6_INGPADBOUNDARY_SHIFT : 464 X_INGPADBOUNDARY_SHIFT; 465 pad = fl_pad; 466 if (fl_pad < (1 << pad_shift) || 467 fl_pad > (1 << (pad_shift + M_INGPADBOUNDARY)) || 468 !powerof2(fl_pad)) { 469 /* 470 * If there is any chance that we might use buffer packing and 471 * the chip is a T4, then pick 64 as the pad/pack boundary. Set 472 * it to the minimum allowed in all other cases. 473 */ 474 pad = is_t4(sc) && buffer_packing ? 64 : 1 << pad_shift; 475 476 /* 477 * For fl_pad = 0 we'll still write a reasonable value to the 478 * register but all the freelists will opt out of padding. 479 * We'll complain here only if the user tried to set it to a 480 * value greater than 0 that was invalid. 481 */ 482 if (fl_pad > 0) { 483 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pad value" 484 " (%d), using %d instead.\n", fl_pad, pad); 485 } 486 } 487 m = V_INGPADBOUNDARY(M_INGPADBOUNDARY); 488 v = V_INGPADBOUNDARY(ilog2(pad) - pad_shift); 489 t4_set_reg_field(sc, A_SGE_CONTROL, m, v); 490 491 if (is_t4(sc)) { 492 if (fl_pack != -1 && fl_pack != pad) { 493 /* Complain but carry on. */ 494 device_printf(sc->dev, "hw.cxgbe.fl_pack (%d) ignored," 495 " using %d instead.\n", fl_pack, pad); 496 } 497 return; 498 } 499 500 pack = fl_pack; 501 if (fl_pack < 16 || fl_pack == 32 || fl_pack > 4096 || 502 !powerof2(fl_pack)) { 503 pack = max(sc->params.pci.mps, CACHE_LINE_SIZE); 504 MPASS(powerof2(pack)); 505 if (pack < 16) 506 pack = 16; 507 if (pack == 32) 508 pack = 64; 509 if (pack > 4096) 510 pack = 4096; 511 if (fl_pack != -1) { 512 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pack value" 513 " (%d), using %d instead.\n", fl_pack, pack); 514 } 515 } 516 m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY); 517 if (pack == 16) 518 v = V_INGPACKBOUNDARY(0); 519 else 520 v = V_INGPACKBOUNDARY(ilog2(pack) - 5); 521 522 MPASS(!is_t4(sc)); /* T4 doesn't have SGE_CONTROL2 */ 523 t4_set_reg_field(sc, A_SGE_CONTROL2, m, v); 524 } 525 526 /* 527 * adap->params.vpd.cclk must be set up before this is called. 528 */ 529 void 530 t4_tweak_chip_settings(struct adapter *sc) 531 { 532 int i; 533 uint32_t v, m; 534 int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200}; 535 int timer_max = M_TIMERVALUE0 * 1000 / sc->params.vpd.cclk; 536 int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */ 537 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 538 static int sge_flbuf_sizes[] = { 539 MCLBYTES, 540 #if MJUMPAGESIZE != MCLBYTES 541 MJUMPAGESIZE, 542 MJUMPAGESIZE - CL_METADATA_SIZE, 543 MJUMPAGESIZE - 2 * MSIZE - CL_METADATA_SIZE, 544 #endif 545 MJUM9BYTES, 546 MJUM16BYTES, 547 MCLBYTES - MSIZE - CL_METADATA_SIZE, 548 MJUM9BYTES - CL_METADATA_SIZE, 549 MJUM16BYTES - CL_METADATA_SIZE, 550 }; 551 552 KASSERT(sc->flags & MASTER_PF, 553 ("%s: trying to change chip settings when not master.", __func__)); 554 555 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE; 556 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE | 557 V_EGRSTATUSPAGESIZE(spg_len == 128); 558 t4_set_reg_field(sc, A_SGE_CONTROL, m, v); 559 560 setup_pad_and_pack_boundaries(sc); 561 562 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) | 563 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) | 564 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) | 565 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) | 566 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) | 567 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) | 568 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) | 569 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10); 570 t4_write_reg(sc, A_SGE_HOST_PAGE_SIZE, v); 571 572 KASSERT(nitems(sge_flbuf_sizes) <= SGE_FLBUF_SIZES, 573 ("%s: hw buffer size table too big", __func__)); 574 for (i = 0; i < min(nitems(sge_flbuf_sizes), SGE_FLBUF_SIZES); i++) { 575 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0 + (4 * i), 576 sge_flbuf_sizes[i]); 577 } 578 579 v = V_THRESHOLD_0(intr_pktcount[0]) | V_THRESHOLD_1(intr_pktcount[1]) | 580 V_THRESHOLD_2(intr_pktcount[2]) | V_THRESHOLD_3(intr_pktcount[3]); 581 t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD, v); 582 583 KASSERT(intr_timer[0] <= timer_max, 584 ("%s: not a single usable timer (%d, %d)", __func__, intr_timer[0], 585 timer_max)); 586 for (i = 1; i < nitems(intr_timer); i++) { 587 KASSERT(intr_timer[i] >= intr_timer[i - 1], 588 ("%s: timers not listed in increasing order (%d)", 589 __func__, i)); 590 591 while (intr_timer[i] > timer_max) { 592 if (i == nitems(intr_timer) - 1) { 593 intr_timer[i] = timer_max; 594 break; 595 } 596 intr_timer[i] += intr_timer[i - 1]; 597 intr_timer[i] /= 2; 598 } 599 } 600 601 v = V_TIMERVALUE0(us_to_core_ticks(sc, intr_timer[0])) | 602 V_TIMERVALUE1(us_to_core_ticks(sc, intr_timer[1])); 603 t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1, v); 604 v = V_TIMERVALUE2(us_to_core_ticks(sc, intr_timer[2])) | 605 V_TIMERVALUE3(us_to_core_ticks(sc, intr_timer[3])); 606 t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3, v); 607 v = V_TIMERVALUE4(us_to_core_ticks(sc, intr_timer[4])) | 608 V_TIMERVALUE5(us_to_core_ticks(sc, intr_timer[5])); 609 t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5, v); 610 611 if (chip_id(sc) >= CHELSIO_T6) { 612 m = V_TSCALE(M_TSCALE); 613 if (tscale == 1) 614 v = 0; 615 else 616 v = V_TSCALE(tscale - 2); 617 t4_set_reg_field(sc, A_SGE_ITP_CONTROL, m, v); 618 619 if (sc->debug_flags & DF_DISABLE_TCB_CACHE) { 620 m = V_RDTHRESHOLD(M_RDTHRESHOLD) | F_WRTHRTHRESHEN | 621 V_WRTHRTHRESH(M_WRTHRTHRESH); 622 t4_tp_pio_read(sc, &v, 1, A_TP_CMM_CONFIG, 1); 623 v &= ~m; 624 v |= V_RDTHRESHOLD(1) | F_WRTHRTHRESHEN | 625 V_WRTHRTHRESH(16); 626 t4_tp_pio_write(sc, &v, 1, A_TP_CMM_CONFIG, 1); 627 } 628 } 629 630 /* 4K, 16K, 64K, 256K DDP "page sizes" for TDDP */ 631 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 632 t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, v); 633 634 /* 635 * 4K, 8K, 16K, 64K DDP "page sizes" for iSCSI DDP. These have been 636 * chosen with MAXPHYS = 128K in mind. The largest DDP buffer that we 637 * may have to deal with is MAXPHYS + 1 page. 638 */ 639 v = V_HPZ0(0) | V_HPZ1(1) | V_HPZ2(2) | V_HPZ3(4); 640 t4_write_reg(sc, A_ULP_RX_ISCSI_PSZ, v); 641 642 /* We use multiple DDP page sizes both in plain-TOE and ISCSI modes. */ 643 m = v = F_TDDPTAGTCB | F_ISCSITAGTCB; 644 t4_set_reg_field(sc, A_ULP_RX_CTL, m, v); 645 646 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 647 F_RESETDDPOFFSET; 648 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 649 t4_set_reg_field(sc, A_TP_PARA_REG5, m, v); 650 } 651 652 /* 653 * SGE wants the buffer to be at least 64B and then a multiple of 16. If 654 * padding is in use, the buffer's start and end need to be aligned to the pad 655 * boundary as well. We'll just make sure that the size is a multiple of the 656 * boundary here, it is up to the buffer allocation code to make sure the start 657 * of the buffer is aligned as well. 658 */ 659 static inline int 660 hwsz_ok(struct adapter *sc, int hwsz) 661 { 662 int mask = fl_pad ? sc->params.sge.pad_boundary - 1 : 16 - 1; 663 664 return (hwsz >= 64 && (hwsz & mask) == 0); 665 } 666 667 /* 668 * XXX: driver really should be able to deal with unexpected settings. 669 */ 670 int 671 t4_read_chip_settings(struct adapter *sc) 672 { 673 struct sge *s = &sc->sge; 674 struct sge_params *sp = &sc->params.sge; 675 int i, j, n, rc = 0; 676 uint32_t m, v, r; 677 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 678 static int sw_buf_sizes[] = { /* Sorted by size */ 679 MCLBYTES, 680 #if MJUMPAGESIZE != MCLBYTES 681 MJUMPAGESIZE, 682 #endif 683 MJUM9BYTES, 684 MJUM16BYTES 685 }; 686 struct sw_zone_info *swz, *safe_swz; 687 struct hw_buf_info *hwb; 688 689 m = F_RXPKTCPLMODE; 690 v = F_RXPKTCPLMODE; 691 r = sc->params.sge.sge_control; 692 if ((r & m) != v) { 693 device_printf(sc->dev, "invalid SGE_CONTROL(0x%x)\n", r); 694 rc = EINVAL; 695 } 696 697 /* 698 * If this changes then every single use of PAGE_SHIFT in the driver 699 * needs to be carefully reviewed for PAGE_SHIFT vs sp->page_shift. 700 */ 701 if (sp->page_shift != PAGE_SHIFT) { 702 device_printf(sc->dev, "invalid SGE_HOST_PAGE_SIZE(0x%x)\n", r); 703 rc = EINVAL; 704 } 705 706 /* Filter out unusable hw buffer sizes entirely (mark with -2). */ 707 hwb = &s->hw_buf_info[0]; 708 for (i = 0; i < nitems(s->hw_buf_info); i++, hwb++) { 709 r = sc->params.sge.sge_fl_buffer_size[i]; 710 hwb->size = r; 711 hwb->zidx = hwsz_ok(sc, r) ? -1 : -2; 712 hwb->next = -1; 713 } 714 715 /* 716 * Create a sorted list in decreasing order of hw buffer sizes (and so 717 * increasing order of spare area) for each software zone. 718 * 719 * If padding is enabled then the start and end of the buffer must align 720 * to the pad boundary; if packing is enabled then they must align with 721 * the pack boundary as well. Allocations from the cluster zones are 722 * aligned to min(size, 4K), so the buffer starts at that alignment and 723 * ends at hwb->size alignment. If mbuf inlining is allowed the 724 * starting alignment will be reduced to MSIZE and the driver will 725 * exercise appropriate caution when deciding on the best buffer layout 726 * to use. 727 */ 728 n = 0; /* no usable buffer size to begin with */ 729 swz = &s->sw_zone_info[0]; 730 safe_swz = NULL; 731 for (i = 0; i < SW_ZONE_SIZES; i++, swz++) { 732 int8_t head = -1, tail = -1; 733 734 swz->size = sw_buf_sizes[i]; 735 swz->zone = m_getzone(swz->size); 736 swz->type = m_gettype(swz->size); 737 738 if (swz->size < PAGE_SIZE) { 739 MPASS(powerof2(swz->size)); 740 if (fl_pad && (swz->size % sp->pad_boundary != 0)) 741 continue; 742 } 743 744 if (swz->size == safest_rx_cluster) 745 safe_swz = swz; 746 747 hwb = &s->hw_buf_info[0]; 748 for (j = 0; j < SGE_FLBUF_SIZES; j++, hwb++) { 749 if (hwb->zidx != -1 || hwb->size > swz->size) 750 continue; 751 #ifdef INVARIANTS 752 if (fl_pad) 753 MPASS(hwb->size % sp->pad_boundary == 0); 754 #endif 755 hwb->zidx = i; 756 if (head == -1) 757 head = tail = j; 758 else if (hwb->size < s->hw_buf_info[tail].size) { 759 s->hw_buf_info[tail].next = j; 760 tail = j; 761 } else { 762 int8_t *cur; 763 struct hw_buf_info *t; 764 765 for (cur = &head; *cur != -1; cur = &t->next) { 766 t = &s->hw_buf_info[*cur]; 767 if (hwb->size == t->size) { 768 hwb->zidx = -2; 769 break; 770 } 771 if (hwb->size > t->size) { 772 hwb->next = *cur; 773 *cur = j; 774 break; 775 } 776 } 777 } 778 } 779 swz->head_hwidx = head; 780 swz->tail_hwidx = tail; 781 782 if (tail != -1) { 783 n++; 784 if (swz->size - s->hw_buf_info[tail].size >= 785 CL_METADATA_SIZE) 786 sc->flags |= BUF_PACKING_OK; 787 } 788 } 789 if (n == 0) { 790 device_printf(sc->dev, "no usable SGE FL buffer size.\n"); 791 rc = EINVAL; 792 } 793 794 s->safe_hwidx1 = -1; 795 s->safe_hwidx2 = -1; 796 if (safe_swz != NULL) { 797 s->safe_hwidx1 = safe_swz->head_hwidx; 798 for (i = safe_swz->head_hwidx; i != -1; i = hwb->next) { 799 int spare; 800 801 hwb = &s->hw_buf_info[i]; 802 #ifdef INVARIANTS 803 if (fl_pad) 804 MPASS(hwb->size % sp->pad_boundary == 0); 805 #endif 806 spare = safe_swz->size - hwb->size; 807 if (spare >= CL_METADATA_SIZE) { 808 s->safe_hwidx2 = i; 809 break; 810 } 811 } 812 } 813 814 if (sc->flags & IS_VF) 815 return (0); 816 817 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 818 r = t4_read_reg(sc, A_ULP_RX_TDDP_PSZ); 819 if (r != v) { 820 device_printf(sc->dev, "invalid ULP_RX_TDDP_PSZ(0x%x)\n", r); 821 rc = EINVAL; 822 } 823 824 m = v = F_TDDPTAGTCB; 825 r = t4_read_reg(sc, A_ULP_RX_CTL); 826 if ((r & m) != v) { 827 device_printf(sc->dev, "invalid ULP_RX_CTL(0x%x)\n", r); 828 rc = EINVAL; 829 } 830 831 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 832 F_RESETDDPOFFSET; 833 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 834 r = t4_read_reg(sc, A_TP_PARA_REG5); 835 if ((r & m) != v) { 836 device_printf(sc->dev, "invalid TP_PARA_REG5(0x%x)\n", r); 837 rc = EINVAL; 838 } 839 840 t4_init_tp_params(sc, 1); 841 842 t4_read_mtu_tbl(sc, sc->params.mtus, NULL); 843 t4_load_mtus(sc, sc->params.mtus, sc->params.a_wnd, sc->params.b_wnd); 844 845 return (rc); 846 } 847 848 int 849 t4_create_dma_tag(struct adapter *sc) 850 { 851 int rc; 852 853 rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0, 854 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE, 855 BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL, 856 NULL, &sc->dmat); 857 if (rc != 0) { 858 device_printf(sc->dev, 859 "failed to create main DMA tag: %d\n", rc); 860 } 861 862 return (rc); 863 } 864 865 void 866 t4_sge_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx, 867 struct sysctl_oid_list *children) 868 { 869 struct sge_params *sp = &sc->params.sge; 870 871 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "buffer_sizes", 872 CTLTYPE_STRING | CTLFLAG_RD, &sc->sge, 0, sysctl_bufsizes, "A", 873 "freelist buffer sizes"); 874 875 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pktshift", CTLFLAG_RD, 876 NULL, sp->fl_pktshift, "payload DMA offset in rx buffer (bytes)"); 877 878 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pad", CTLFLAG_RD, 879 NULL, sp->pad_boundary, "payload pad boundary (bytes)"); 880 881 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "spg_len", CTLFLAG_RD, 882 NULL, sp->spg_len, "status page size (bytes)"); 883 884 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_drop", CTLFLAG_RD, 885 NULL, cong_drop, "congestion drop setting"); 886 887 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pack", CTLFLAG_RD, 888 NULL, sp->pack_boundary, "payload pack boundary (bytes)"); 889 } 890 891 int 892 t4_destroy_dma_tag(struct adapter *sc) 893 { 894 if (sc->dmat) 895 bus_dma_tag_destroy(sc->dmat); 896 897 return (0); 898 } 899 900 /* 901 * Allocate and initialize the firmware event queue and the management queue. 902 * 903 * Returns errno on failure. Resources allocated up to that point may still be 904 * allocated. Caller is responsible for cleanup in case this function fails. 905 */ 906 int 907 t4_setup_adapter_queues(struct adapter *sc) 908 { 909 int rc; 910 911 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 912 913 sysctl_ctx_init(&sc->ctx); 914 sc->flags |= ADAP_SYSCTL_CTX; 915 916 /* 917 * Firmware event queue 918 */ 919 rc = alloc_fwq(sc); 920 if (rc != 0) 921 return (rc); 922 923 /* 924 * Management queue. This is just a control queue that uses the fwq as 925 * its associated iq. 926 */ 927 if (!(sc->flags & IS_VF)) 928 rc = alloc_mgmtq(sc); 929 930 return (rc); 931 } 932 933 /* 934 * Idempotent 935 */ 936 int 937 t4_teardown_adapter_queues(struct adapter *sc) 938 { 939 940 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 941 942 /* Do this before freeing the queue */ 943 if (sc->flags & ADAP_SYSCTL_CTX) { 944 sysctl_ctx_free(&sc->ctx); 945 sc->flags &= ~ADAP_SYSCTL_CTX; 946 } 947 948 free_mgmtq(sc); 949 free_fwq(sc); 950 951 return (0); 952 } 953 954 static inline int 955 first_vector(struct vi_info *vi) 956 { 957 struct adapter *sc = vi->pi->adapter; 958 959 if (sc->intr_count == 1) 960 return (0); 961 962 return (vi->first_intr); 963 } 964 965 /* 966 * Given an arbitrary "index," come up with an iq that can be used by other 967 * queues (of this VI) for interrupt forwarding, SGE egress updates, etc. 968 * The iq returned is guaranteed to be something that takes direct interrupts. 969 */ 970 static struct sge_iq * 971 vi_intr_iq(struct vi_info *vi, int idx) 972 { 973 struct adapter *sc = vi->pi->adapter; 974 struct sge *s = &sc->sge; 975 struct sge_iq *iq = NULL; 976 int nintr, i; 977 978 if (sc->intr_count == 1) 979 return (&sc->sge.fwq); 980 981 nintr = vi->nintr; 982 #ifdef DEV_NETMAP 983 /* Do not consider any netmap-only interrupts */ 984 if (vi->flags & INTR_RXQ && vi->nnmrxq > vi->nrxq) 985 nintr -= vi->nnmrxq - vi->nrxq; 986 #endif 987 KASSERT(nintr != 0, 988 ("%s: vi %p has no exclusive interrupts, total interrupts = %d", 989 __func__, vi, sc->intr_count)); 990 i = idx % nintr; 991 992 if (vi->flags & INTR_RXQ) { 993 if (i < vi->nrxq) { 994 iq = &s->rxq[vi->first_rxq + i].iq; 995 goto done; 996 } 997 i -= vi->nrxq; 998 } 999 #ifdef TCP_OFFLOAD 1000 if (vi->flags & INTR_OFLD_RXQ) { 1001 if (i < vi->nofldrxq) { 1002 iq = &s->ofld_rxq[vi->first_ofld_rxq + i].iq; 1003 goto done; 1004 } 1005 i -= vi->nofldrxq; 1006 } 1007 #endif 1008 panic("%s: vi %p, intr_flags 0x%lx, idx %d, total intr %d\n", __func__, 1009 vi, vi->flags & INTR_ALL, idx, nintr); 1010 done: 1011 MPASS(iq != NULL); 1012 KASSERT(iq->flags & IQ_INTR, 1013 ("%s: iq %p (vi %p, intr_flags 0x%lx, idx %d)", __func__, iq, vi, 1014 vi->flags & INTR_ALL, idx)); 1015 return (iq); 1016 } 1017 1018 /* Maximum payload that can be delivered with a single iq descriptor */ 1019 static inline int 1020 mtu_to_max_payload(struct adapter *sc, int mtu, const int toe) 1021 { 1022 int payload; 1023 1024 #ifdef TCP_OFFLOAD 1025 if (toe) { 1026 payload = sc->tt.rx_coalesce ? 1027 G_RXCOALESCESIZE(t4_read_reg(sc, A_TP_PARA_REG2)) : mtu; 1028 } else { 1029 #endif 1030 /* large enough even when hw VLAN extraction is disabled */ 1031 payload = sc->params.sge.fl_pktshift + ETHER_HDR_LEN + 1032 ETHER_VLAN_ENCAP_LEN + mtu; 1033 #ifdef TCP_OFFLOAD 1034 } 1035 #endif 1036 1037 return (payload); 1038 } 1039 1040 int 1041 t4_setup_vi_queues(struct vi_info *vi) 1042 { 1043 int rc = 0, i, j, intr_idx, iqid; 1044 struct sge_rxq *rxq; 1045 struct sge_txq *txq; 1046 struct sge_wrq *ctrlq; 1047 #ifdef TCP_OFFLOAD 1048 struct sge_ofld_rxq *ofld_rxq; 1049 struct sge_wrq *ofld_txq; 1050 #endif 1051 #ifdef DEV_NETMAP 1052 int saved_idx; 1053 struct sge_nm_rxq *nm_rxq; 1054 struct sge_nm_txq *nm_txq; 1055 #endif 1056 char name[16]; 1057 struct port_info *pi = vi->pi; 1058 struct adapter *sc = pi->adapter; 1059 struct ifnet *ifp = vi->ifp; 1060 struct sysctl_oid *oid = device_get_sysctl_tree(vi->dev); 1061 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 1062 int maxp, mtu = ifp->if_mtu; 1063 1064 /* Interrupt vector to start from (when using multiple vectors) */ 1065 intr_idx = first_vector(vi); 1066 1067 #ifdef DEV_NETMAP 1068 saved_idx = intr_idx; 1069 if (ifp->if_capabilities & IFCAP_NETMAP) { 1070 1071 /* netmap is supported with direct interrupts only. */ 1072 MPASS(vi->flags & INTR_RXQ); 1073 1074 /* 1075 * We don't have buffers to back the netmap rx queues 1076 * right now so we create the queues in a way that 1077 * doesn't set off any congestion signal in the chip. 1078 */ 1079 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "nm_rxq", 1080 CTLFLAG_RD, NULL, "rx queues"); 1081 for_each_nm_rxq(vi, i, nm_rxq) { 1082 rc = alloc_nm_rxq(vi, nm_rxq, intr_idx, i, oid); 1083 if (rc != 0) 1084 goto done; 1085 intr_idx++; 1086 } 1087 1088 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "nm_txq", 1089 CTLFLAG_RD, NULL, "tx queues"); 1090 for_each_nm_txq(vi, i, nm_txq) { 1091 iqid = vi->first_nm_rxq + (i % vi->nnmrxq); 1092 rc = alloc_nm_txq(vi, nm_txq, iqid, i, oid); 1093 if (rc != 0) 1094 goto done; 1095 } 1096 } 1097 1098 /* Normal rx queues and netmap rx queues share the same interrupts. */ 1099 intr_idx = saved_idx; 1100 #endif 1101 1102 /* 1103 * First pass over all NIC and TOE rx queues: 1104 * a) initialize iq and fl 1105 * b) allocate queue iff it will take direct interrupts. 1106 */ 1107 maxp = mtu_to_max_payload(sc, mtu, 0); 1108 if (vi->flags & INTR_RXQ) { 1109 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "rxq", 1110 CTLFLAG_RD, NULL, "rx queues"); 1111 } 1112 for_each_rxq(vi, i, rxq) { 1113 1114 init_iq(&rxq->iq, sc, vi->tmr_idx, vi->pktc_idx, vi->qsize_rxq); 1115 1116 snprintf(name, sizeof(name), "%s rxq%d-fl", 1117 device_get_nameunit(vi->dev), i); 1118 init_fl(sc, &rxq->fl, vi->qsize_rxq / 8, maxp, name); 1119 1120 if (vi->flags & INTR_RXQ) { 1121 rxq->iq.flags |= IQ_INTR; 1122 rc = alloc_rxq(vi, rxq, intr_idx, i, oid); 1123 if (rc != 0) 1124 goto done; 1125 intr_idx++; 1126 } 1127 } 1128 #ifdef DEV_NETMAP 1129 if (ifp->if_capabilities & IFCAP_NETMAP) 1130 intr_idx = saved_idx + max(vi->nrxq, vi->nnmrxq); 1131 #endif 1132 #ifdef TCP_OFFLOAD 1133 maxp = mtu_to_max_payload(sc, mtu, 1); 1134 if (vi->flags & INTR_OFLD_RXQ) { 1135 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_rxq", 1136 CTLFLAG_RD, NULL, 1137 "rx queues for offloaded TCP connections"); 1138 } 1139 for_each_ofld_rxq(vi, i, ofld_rxq) { 1140 1141 init_iq(&ofld_rxq->iq, sc, vi->ofld_tmr_idx, vi->ofld_pktc_idx, 1142 vi->qsize_rxq); 1143 1144 snprintf(name, sizeof(name), "%s ofld_rxq%d-fl", 1145 device_get_nameunit(vi->dev), i); 1146 init_fl(sc, &ofld_rxq->fl, vi->qsize_rxq / 8, maxp, name); 1147 1148 if (vi->flags & INTR_OFLD_RXQ) { 1149 ofld_rxq->iq.flags |= IQ_INTR; 1150 rc = alloc_ofld_rxq(vi, ofld_rxq, intr_idx, i, oid); 1151 if (rc != 0) 1152 goto done; 1153 intr_idx++; 1154 } 1155 } 1156 #endif 1157 1158 /* 1159 * Second pass over all NIC and TOE rx queues. The queues forwarding 1160 * their interrupts are allocated now. 1161 */ 1162 j = 0; 1163 if (!(vi->flags & INTR_RXQ)) { 1164 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "rxq", 1165 CTLFLAG_RD, NULL, "rx queues"); 1166 for_each_rxq(vi, i, rxq) { 1167 MPASS(!(rxq->iq.flags & IQ_INTR)); 1168 1169 intr_idx = vi_intr_iq(vi, j)->abs_id; 1170 1171 rc = alloc_rxq(vi, rxq, intr_idx, i, oid); 1172 if (rc != 0) 1173 goto done; 1174 j++; 1175 } 1176 } 1177 #ifdef TCP_OFFLOAD 1178 if (vi->nofldrxq != 0 && !(vi->flags & INTR_OFLD_RXQ)) { 1179 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_rxq", 1180 CTLFLAG_RD, NULL, 1181 "rx queues for offloaded TCP connections"); 1182 for_each_ofld_rxq(vi, i, ofld_rxq) { 1183 MPASS(!(ofld_rxq->iq.flags & IQ_INTR)); 1184 1185 intr_idx = vi_intr_iq(vi, j)->abs_id; 1186 1187 rc = alloc_ofld_rxq(vi, ofld_rxq, intr_idx, i, oid); 1188 if (rc != 0) 1189 goto done; 1190 j++; 1191 } 1192 } 1193 #endif 1194 1195 /* 1196 * Now the tx queues. Only one pass needed. 1197 */ 1198 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "txq", CTLFLAG_RD, 1199 NULL, "tx queues"); 1200 j = 0; 1201 for_each_txq(vi, i, txq) { 1202 iqid = vi_intr_iq(vi, j)->cntxt_id; 1203 snprintf(name, sizeof(name), "%s txq%d", 1204 device_get_nameunit(vi->dev), i); 1205 init_eq(sc, &txq->eq, EQ_ETH, vi->qsize_txq, pi->tx_chan, iqid, 1206 name); 1207 1208 rc = alloc_txq(vi, txq, i, oid); 1209 if (rc != 0) 1210 goto done; 1211 j++; 1212 } 1213 #ifdef TCP_OFFLOAD 1214 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_txq", 1215 CTLFLAG_RD, NULL, "tx queues for offloaded TCP connections"); 1216 for_each_ofld_txq(vi, i, ofld_txq) { 1217 struct sysctl_oid *oid2; 1218 1219 iqid = vi_intr_iq(vi, j)->cntxt_id; 1220 snprintf(name, sizeof(name), "%s ofld_txq%d", 1221 device_get_nameunit(vi->dev), i); 1222 init_eq(sc, &ofld_txq->eq, EQ_OFLD, vi->qsize_txq, pi->tx_chan, 1223 iqid, name); 1224 1225 snprintf(name, sizeof(name), "%d", i); 1226 oid2 = SYSCTL_ADD_NODE(&vi->ctx, SYSCTL_CHILDREN(oid), OID_AUTO, 1227 name, CTLFLAG_RD, NULL, "offload tx queue"); 1228 1229 rc = alloc_wrq(sc, vi, ofld_txq, oid2); 1230 if (rc != 0) 1231 goto done; 1232 j++; 1233 } 1234 #endif 1235 1236 /* 1237 * Finally, the control queue. 1238 */ 1239 if (!IS_MAIN_VI(vi) || sc->flags & IS_VF) 1240 goto done; 1241 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ctrlq", CTLFLAG_RD, 1242 NULL, "ctrl queue"); 1243 ctrlq = &sc->sge.ctrlq[pi->port_id]; 1244 iqid = vi_intr_iq(vi, 0)->cntxt_id; 1245 snprintf(name, sizeof(name), "%s ctrlq", device_get_nameunit(vi->dev)); 1246 init_eq(sc, &ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE, pi->tx_chan, iqid, 1247 name); 1248 rc = alloc_wrq(sc, vi, ctrlq, oid); 1249 1250 done: 1251 if (rc) 1252 t4_teardown_vi_queues(vi); 1253 1254 return (rc); 1255 } 1256 1257 /* 1258 * Idempotent 1259 */ 1260 int 1261 t4_teardown_vi_queues(struct vi_info *vi) 1262 { 1263 int i; 1264 struct port_info *pi = vi->pi; 1265 struct adapter *sc = pi->adapter; 1266 struct sge_rxq *rxq; 1267 struct sge_txq *txq; 1268 #ifdef TCP_OFFLOAD 1269 struct sge_ofld_rxq *ofld_rxq; 1270 struct sge_wrq *ofld_txq; 1271 #endif 1272 #ifdef DEV_NETMAP 1273 struct sge_nm_rxq *nm_rxq; 1274 struct sge_nm_txq *nm_txq; 1275 #endif 1276 1277 /* Do this before freeing the queues */ 1278 if (vi->flags & VI_SYSCTL_CTX) { 1279 sysctl_ctx_free(&vi->ctx); 1280 vi->flags &= ~VI_SYSCTL_CTX; 1281 } 1282 1283 #ifdef DEV_NETMAP 1284 if (vi->ifp->if_capabilities & IFCAP_NETMAP) { 1285 for_each_nm_txq(vi, i, nm_txq) { 1286 free_nm_txq(vi, nm_txq); 1287 } 1288 1289 for_each_nm_rxq(vi, i, nm_rxq) { 1290 free_nm_rxq(vi, nm_rxq); 1291 } 1292 } 1293 #endif 1294 1295 /* 1296 * Take down all the tx queues first, as they reference the rx queues 1297 * (for egress updates, etc.). 1298 */ 1299 1300 if (IS_MAIN_VI(vi) && !(sc->flags & IS_VF)) 1301 free_wrq(sc, &sc->sge.ctrlq[pi->port_id]); 1302 1303 for_each_txq(vi, i, txq) { 1304 free_txq(vi, txq); 1305 } 1306 #ifdef TCP_OFFLOAD 1307 for_each_ofld_txq(vi, i, ofld_txq) { 1308 free_wrq(sc, ofld_txq); 1309 } 1310 #endif 1311 1312 /* 1313 * Then take down the rx queues that forward their interrupts, as they 1314 * reference other rx queues. 1315 */ 1316 1317 for_each_rxq(vi, i, rxq) { 1318 if ((rxq->iq.flags & IQ_INTR) == 0) 1319 free_rxq(vi, rxq); 1320 } 1321 #ifdef TCP_OFFLOAD 1322 for_each_ofld_rxq(vi, i, ofld_rxq) { 1323 if ((ofld_rxq->iq.flags & IQ_INTR) == 0) 1324 free_ofld_rxq(vi, ofld_rxq); 1325 } 1326 #endif 1327 1328 /* 1329 * Then take down the rx queues that take direct interrupts. 1330 */ 1331 1332 for_each_rxq(vi, i, rxq) { 1333 if (rxq->iq.flags & IQ_INTR) 1334 free_rxq(vi, rxq); 1335 } 1336 #ifdef TCP_OFFLOAD 1337 for_each_ofld_rxq(vi, i, ofld_rxq) { 1338 if (ofld_rxq->iq.flags & IQ_INTR) 1339 free_ofld_rxq(vi, ofld_rxq); 1340 } 1341 #endif 1342 1343 return (0); 1344 } 1345 1346 /* 1347 * Deals with errors and the firmware event queue. All data rx queues forward 1348 * their interrupt to the firmware event queue. 1349 */ 1350 void 1351 t4_intr_all(void *arg) 1352 { 1353 struct adapter *sc = arg; 1354 struct sge_iq *fwq = &sc->sge.fwq; 1355 1356 t4_intr_err(arg); 1357 if (atomic_cmpset_int(&fwq->state, IQS_IDLE, IQS_BUSY)) { 1358 service_iq(fwq, 0); 1359 atomic_cmpset_int(&fwq->state, IQS_BUSY, IQS_IDLE); 1360 } 1361 } 1362 1363 /* Deals with error interrupts */ 1364 void 1365 t4_intr_err(void *arg) 1366 { 1367 struct adapter *sc = arg; 1368 1369 t4_write_reg(sc, MYPF_REG(A_PCIE_PF_CLI), 0); 1370 t4_slow_intr_handler(sc); 1371 } 1372 1373 void 1374 t4_intr_evt(void *arg) 1375 { 1376 struct sge_iq *iq = arg; 1377 1378 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 1379 service_iq(iq, 0); 1380 atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 1381 } 1382 } 1383 1384 void 1385 t4_intr(void *arg) 1386 { 1387 struct sge_iq *iq = arg; 1388 1389 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 1390 service_iq(iq, 0); 1391 atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 1392 } 1393 } 1394 1395 void 1396 t4_vi_intr(void *arg) 1397 { 1398 struct irq *irq = arg; 1399 1400 #ifdef DEV_NETMAP 1401 if (atomic_cmpset_int(&irq->nm_state, NM_ON, NM_BUSY)) { 1402 t4_nm_intr(irq->nm_rxq); 1403 atomic_cmpset_int(&irq->nm_state, NM_BUSY, NM_ON); 1404 } 1405 #endif 1406 if (irq->rxq != NULL) 1407 t4_intr(irq->rxq); 1408 } 1409 1410 static inline int 1411 sort_before_lro(struct lro_ctrl *lro) 1412 { 1413 1414 return (lro->lro_mbuf_max != 0); 1415 } 1416 1417 /* 1418 * Deals with anything and everything on the given ingress queue. 1419 */ 1420 static int 1421 service_iq(struct sge_iq *iq, int budget) 1422 { 1423 struct sge_iq *q; 1424 struct sge_rxq *rxq = iq_to_rxq(iq); /* Use iff iq is part of rxq */ 1425 struct sge_fl *fl; /* Use iff IQ_HAS_FL */ 1426 struct adapter *sc = iq->adapter; 1427 struct iq_desc *d = &iq->desc[iq->cidx]; 1428 int ndescs = 0, limit; 1429 int rsp_type, refill; 1430 uint32_t lq; 1431 uint16_t fl_hw_cidx; 1432 struct mbuf *m0; 1433 STAILQ_HEAD(, sge_iq) iql = STAILQ_HEAD_INITIALIZER(iql); 1434 #if defined(INET) || defined(INET6) 1435 const struct timeval lro_timeout = {0, sc->lro_timeout}; 1436 struct lro_ctrl *lro = &rxq->lro; 1437 #endif 1438 1439 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq)); 1440 1441 limit = budget ? budget : iq->qsize / 16; 1442 1443 if (iq->flags & IQ_HAS_FL) { 1444 fl = &rxq->fl; 1445 fl_hw_cidx = fl->hw_cidx; /* stable snapshot */ 1446 } else { 1447 fl = NULL; 1448 fl_hw_cidx = 0; /* to silence gcc warning */ 1449 } 1450 1451 #if defined(INET) || defined(INET6) 1452 if (iq->flags & IQ_ADJ_CREDIT) { 1453 MPASS(sort_before_lro(lro)); 1454 iq->flags &= ~IQ_ADJ_CREDIT; 1455 if ((d->rsp.u.type_gen & F_RSPD_GEN) != iq->gen) { 1456 tcp_lro_flush_all(lro); 1457 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(1) | 1458 V_INGRESSQID((u32)iq->cntxt_id) | 1459 V_SEINTARM(iq->intr_params)); 1460 return (0); 1461 } 1462 ndescs = 1; 1463 } 1464 #else 1465 MPASS((iq->flags & IQ_ADJ_CREDIT) == 0); 1466 #endif 1467 1468 /* 1469 * We always come back and check the descriptor ring for new indirect 1470 * interrupts and other responses after running a single handler. 1471 */ 1472 for (;;) { 1473 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) { 1474 1475 rmb(); 1476 1477 refill = 0; 1478 m0 = NULL; 1479 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen); 1480 lq = be32toh(d->rsp.pldbuflen_qid); 1481 1482 switch (rsp_type) { 1483 case X_RSPD_TYPE_FLBUF: 1484 1485 KASSERT(iq->flags & IQ_HAS_FL, 1486 ("%s: data for an iq (%p) with no freelist", 1487 __func__, iq)); 1488 1489 m0 = get_fl_payload(sc, fl, lq); 1490 if (__predict_false(m0 == NULL)) 1491 goto process_iql; 1492 refill = IDXDIFF(fl->hw_cidx, fl_hw_cidx, fl->sidx) > 2; 1493 #ifdef T4_PKT_TIMESTAMP 1494 /* 1495 * 60 bit timestamp for the payload is 1496 * *(uint64_t *)m0->m_pktdat. Note that it is 1497 * in the leading free-space in the mbuf. The 1498 * kernel can clobber it during a pullup, 1499 * m_copymdata, etc. You need to make sure that 1500 * the mbuf reaches you unmolested if you care 1501 * about the timestamp. 1502 */ 1503 *(uint64_t *)m0->m_pktdat = 1504 be64toh(ctrl->u.last_flit) & 1505 0xfffffffffffffff; 1506 #endif 1507 1508 /* fall through */ 1509 1510 case X_RSPD_TYPE_CPL: 1511 KASSERT(d->rss.opcode < NUM_CPL_CMDS, 1512 ("%s: bad opcode %02x.", __func__, 1513 d->rss.opcode)); 1514 t4_cpl_handler[d->rss.opcode](iq, &d->rss, m0); 1515 break; 1516 1517 case X_RSPD_TYPE_INTR: 1518 1519 /* 1520 * Interrupts should be forwarded only to queues 1521 * that are not forwarding their interrupts. 1522 * This means service_iq can recurse but only 1 1523 * level deep. 1524 */ 1525 KASSERT(budget == 0, 1526 ("%s: budget %u, rsp_type %u", __func__, 1527 budget, rsp_type)); 1528 1529 /* 1530 * There are 1K interrupt-capable queues (qids 0 1531 * through 1023). A response type indicating a 1532 * forwarded interrupt with a qid >= 1K is an 1533 * iWARP async notification. 1534 */ 1535 if (lq >= 1024) { 1536 t4_an_handler(iq, &d->rsp); 1537 break; 1538 } 1539 1540 q = sc->sge.iqmap[lq - sc->sge.iq_start - 1541 sc->sge.iq_base]; 1542 if (atomic_cmpset_int(&q->state, IQS_IDLE, 1543 IQS_BUSY)) { 1544 if (service_iq(q, q->qsize / 16) == 0) { 1545 atomic_cmpset_int(&q->state, 1546 IQS_BUSY, IQS_IDLE); 1547 } else { 1548 STAILQ_INSERT_TAIL(&iql, q, 1549 link); 1550 } 1551 } 1552 break; 1553 1554 default: 1555 KASSERT(0, 1556 ("%s: illegal response type %d on iq %p", 1557 __func__, rsp_type, iq)); 1558 log(LOG_ERR, 1559 "%s: illegal response type %d on iq %p", 1560 device_get_nameunit(sc->dev), rsp_type, iq); 1561 break; 1562 } 1563 1564 d++; 1565 if (__predict_false(++iq->cidx == iq->sidx)) { 1566 iq->cidx = 0; 1567 iq->gen ^= F_RSPD_GEN; 1568 d = &iq->desc[0]; 1569 } 1570 if (__predict_false(++ndescs == limit)) { 1571 t4_write_reg(sc, sc->sge_gts_reg, 1572 V_CIDXINC(ndescs) | 1573 V_INGRESSQID(iq->cntxt_id) | 1574 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); 1575 ndescs = 0; 1576 1577 #if defined(INET) || defined(INET6) 1578 if (iq->flags & IQ_LRO_ENABLED && 1579 !sort_before_lro(lro) && 1580 sc->lro_timeout != 0) { 1581 tcp_lro_flush_inactive(lro, 1582 &lro_timeout); 1583 } 1584 #endif 1585 1586 if (budget) { 1587 if (iq->flags & IQ_HAS_FL) { 1588 FL_LOCK(fl); 1589 refill_fl(sc, fl, 32); 1590 FL_UNLOCK(fl); 1591 } 1592 return (EINPROGRESS); 1593 } 1594 } 1595 if (refill) { 1596 FL_LOCK(fl); 1597 refill_fl(sc, fl, 32); 1598 FL_UNLOCK(fl); 1599 fl_hw_cidx = fl->hw_cidx; 1600 } 1601 } 1602 1603 process_iql: 1604 if (STAILQ_EMPTY(&iql)) 1605 break; 1606 1607 /* 1608 * Process the head only, and send it to the back of the list if 1609 * it's still not done. 1610 */ 1611 q = STAILQ_FIRST(&iql); 1612 STAILQ_REMOVE_HEAD(&iql, link); 1613 if (service_iq(q, q->qsize / 8) == 0) 1614 atomic_cmpset_int(&q->state, IQS_BUSY, IQS_IDLE); 1615 else 1616 STAILQ_INSERT_TAIL(&iql, q, link); 1617 } 1618 1619 #if defined(INET) || defined(INET6) 1620 if (iq->flags & IQ_LRO_ENABLED) { 1621 if (ndescs > 0 && lro->lro_mbuf_count > 8) { 1622 MPASS(sort_before_lro(lro)); 1623 /* hold back one credit and don't flush LRO state */ 1624 iq->flags |= IQ_ADJ_CREDIT; 1625 ndescs--; 1626 } else { 1627 tcp_lro_flush_all(lro); 1628 } 1629 } 1630 #endif 1631 1632 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) | 1633 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params)); 1634 1635 if (iq->flags & IQ_HAS_FL) { 1636 int starved; 1637 1638 FL_LOCK(fl); 1639 starved = refill_fl(sc, fl, 64); 1640 FL_UNLOCK(fl); 1641 if (__predict_false(starved != 0)) 1642 add_fl_to_sfl(sc, fl); 1643 } 1644 1645 return (0); 1646 } 1647 1648 static inline int 1649 cl_has_metadata(struct sge_fl *fl, struct cluster_layout *cll) 1650 { 1651 int rc = fl->flags & FL_BUF_PACKING || cll->region1 > 0; 1652 1653 if (rc) 1654 MPASS(cll->region3 >= CL_METADATA_SIZE); 1655 1656 return (rc); 1657 } 1658 1659 static inline struct cluster_metadata * 1660 cl_metadata(struct adapter *sc, struct sge_fl *fl, struct cluster_layout *cll, 1661 caddr_t cl) 1662 { 1663 1664 if (cl_has_metadata(fl, cll)) { 1665 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx]; 1666 1667 return ((struct cluster_metadata *)(cl + swz->size) - 1); 1668 } 1669 return (NULL); 1670 } 1671 1672 static void 1673 rxb_free(struct mbuf *m) 1674 { 1675 uma_zone_t zone = m->m_ext.ext_arg1; 1676 void *cl = m->m_ext.ext_arg2; 1677 1678 uma_zfree(zone, cl); 1679 counter_u64_add(extfree_rels, 1); 1680 } 1681 1682 /* 1683 * The mbuf returned by this function could be allocated from zone_mbuf or 1684 * constructed in spare room in the cluster. 1685 * 1686 * The mbuf carries the payload in one of these ways 1687 * a) frame inside the mbuf (mbuf from zone_mbuf) 1688 * b) m_cljset (for clusters without metadata) zone_mbuf 1689 * c) m_extaddref (cluster with metadata) inline mbuf 1690 * d) m_extaddref (cluster with metadata) zone_mbuf 1691 */ 1692 static struct mbuf * 1693 get_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset, 1694 int remaining) 1695 { 1696 struct mbuf *m; 1697 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 1698 struct cluster_layout *cll = &sd->cll; 1699 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx]; 1700 struct hw_buf_info *hwb = &sc->sge.hw_buf_info[cll->hwidx]; 1701 struct cluster_metadata *clm = cl_metadata(sc, fl, cll, sd->cl); 1702 int len, blen; 1703 caddr_t payload; 1704 1705 blen = hwb->size - fl->rx_offset; /* max possible in this buf */ 1706 len = min(remaining, blen); 1707 payload = sd->cl + cll->region1 + fl->rx_offset; 1708 if (fl->flags & FL_BUF_PACKING) { 1709 const u_int l = fr_offset + len; 1710 const u_int pad = roundup2(l, fl->buf_boundary) - l; 1711 1712 if (fl->rx_offset + len + pad < hwb->size) 1713 blen = len + pad; 1714 MPASS(fl->rx_offset + blen <= hwb->size); 1715 } else { 1716 MPASS(fl->rx_offset == 0); /* not packing */ 1717 } 1718 1719 1720 if (sc->sc_do_rxcopy && len < RX_COPY_THRESHOLD) { 1721 1722 /* 1723 * Copy payload into a freshly allocated mbuf. 1724 */ 1725 1726 m = fr_offset == 0 ? 1727 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA); 1728 if (m == NULL) 1729 return (NULL); 1730 fl->mbuf_allocated++; 1731 #ifdef T4_PKT_TIMESTAMP 1732 /* Leave room for a timestamp */ 1733 m->m_data += 8; 1734 #endif 1735 /* copy data to mbuf */ 1736 bcopy(payload, mtod(m, caddr_t), len); 1737 1738 } else if (sd->nmbuf * MSIZE < cll->region1) { 1739 1740 /* 1741 * There's spare room in the cluster for an mbuf. Create one 1742 * and associate it with the payload that's in the cluster. 1743 */ 1744 1745 MPASS(clm != NULL); 1746 m = (struct mbuf *)(sd->cl + sd->nmbuf * MSIZE); 1747 /* No bzero required */ 1748 if (m_init(m, M_NOWAIT, MT_DATA, 1749 fr_offset == 0 ? M_PKTHDR | M_NOFREE : M_NOFREE)) 1750 return (NULL); 1751 fl->mbuf_inlined++; 1752 m_extaddref(m, payload, blen, &clm->refcount, rxb_free, 1753 swz->zone, sd->cl); 1754 if (sd->nmbuf++ == 0) 1755 counter_u64_add(extfree_refs, 1); 1756 1757 } else { 1758 1759 /* 1760 * Grab an mbuf from zone_mbuf and associate it with the 1761 * payload in the cluster. 1762 */ 1763 1764 m = fr_offset == 0 ? 1765 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA); 1766 if (m == NULL) 1767 return (NULL); 1768 fl->mbuf_allocated++; 1769 if (clm != NULL) { 1770 m_extaddref(m, payload, blen, &clm->refcount, 1771 rxb_free, swz->zone, sd->cl); 1772 if (sd->nmbuf++ == 0) 1773 counter_u64_add(extfree_refs, 1); 1774 } else { 1775 m_cljset(m, sd->cl, swz->type); 1776 sd->cl = NULL; /* consumed, not a recycle candidate */ 1777 } 1778 } 1779 if (fr_offset == 0) 1780 m->m_pkthdr.len = remaining; 1781 m->m_len = len; 1782 1783 if (fl->flags & FL_BUF_PACKING) { 1784 fl->rx_offset += blen; 1785 MPASS(fl->rx_offset <= hwb->size); 1786 if (fl->rx_offset < hwb->size) 1787 return (m); /* without advancing the cidx */ 1788 } 1789 1790 if (__predict_false(++fl->cidx % 8 == 0)) { 1791 uint16_t cidx = fl->cidx / 8; 1792 1793 if (__predict_false(cidx == fl->sidx)) 1794 fl->cidx = cidx = 0; 1795 fl->hw_cidx = cidx; 1796 } 1797 fl->rx_offset = 0; 1798 1799 return (m); 1800 } 1801 1802 static struct mbuf * 1803 get_fl_payload(struct adapter *sc, struct sge_fl *fl, uint32_t len_newbuf) 1804 { 1805 struct mbuf *m0, *m, **pnext; 1806 u_int remaining; 1807 const u_int total = G_RSPD_LEN(len_newbuf); 1808 1809 if (__predict_false(fl->flags & FL_BUF_RESUME)) { 1810 M_ASSERTPKTHDR(fl->m0); 1811 MPASS(fl->m0->m_pkthdr.len == total); 1812 MPASS(fl->remaining < total); 1813 1814 m0 = fl->m0; 1815 pnext = fl->pnext; 1816 remaining = fl->remaining; 1817 fl->flags &= ~FL_BUF_RESUME; 1818 goto get_segment; 1819 } 1820 1821 if (fl->rx_offset > 0 && len_newbuf & F_RSPD_NEWBUF) { 1822 fl->rx_offset = 0; 1823 if (__predict_false(++fl->cidx % 8 == 0)) { 1824 uint16_t cidx = fl->cidx / 8; 1825 1826 if (__predict_false(cidx == fl->sidx)) 1827 fl->cidx = cidx = 0; 1828 fl->hw_cidx = cidx; 1829 } 1830 } 1831 1832 /* 1833 * Payload starts at rx_offset in the current hw buffer. Its length is 1834 * 'len' and it may span multiple hw buffers. 1835 */ 1836 1837 m0 = get_scatter_segment(sc, fl, 0, total); 1838 if (m0 == NULL) 1839 return (NULL); 1840 remaining = total - m0->m_len; 1841 pnext = &m0->m_next; 1842 while (remaining > 0) { 1843 get_segment: 1844 MPASS(fl->rx_offset == 0); 1845 m = get_scatter_segment(sc, fl, total - remaining, remaining); 1846 if (__predict_false(m == NULL)) { 1847 fl->m0 = m0; 1848 fl->pnext = pnext; 1849 fl->remaining = remaining; 1850 fl->flags |= FL_BUF_RESUME; 1851 return (NULL); 1852 } 1853 *pnext = m; 1854 pnext = &m->m_next; 1855 remaining -= m->m_len; 1856 } 1857 *pnext = NULL; 1858 1859 M_ASSERTPKTHDR(m0); 1860 return (m0); 1861 } 1862 1863 static int 1864 t4_eth_rx(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0) 1865 { 1866 struct sge_rxq *rxq = iq_to_rxq(iq); 1867 struct ifnet *ifp = rxq->ifp; 1868 struct adapter *sc = iq->adapter; 1869 const struct cpl_rx_pkt *cpl = (const void *)(rss + 1); 1870 #if defined(INET) || defined(INET6) 1871 struct lro_ctrl *lro = &rxq->lro; 1872 #endif 1873 static const int sw_hashtype[4][2] = { 1874 {M_HASHTYPE_NONE, M_HASHTYPE_NONE}, 1875 {M_HASHTYPE_RSS_IPV4, M_HASHTYPE_RSS_IPV6}, 1876 {M_HASHTYPE_RSS_TCP_IPV4, M_HASHTYPE_RSS_TCP_IPV6}, 1877 {M_HASHTYPE_RSS_UDP_IPV4, M_HASHTYPE_RSS_UDP_IPV6}, 1878 }; 1879 1880 KASSERT(m0 != NULL, ("%s: no payload with opcode %02x", __func__, 1881 rss->opcode)); 1882 1883 m0->m_pkthdr.len -= sc->params.sge.fl_pktshift; 1884 m0->m_len -= sc->params.sge.fl_pktshift; 1885 m0->m_data += sc->params.sge.fl_pktshift; 1886 1887 m0->m_pkthdr.rcvif = ifp; 1888 M_HASHTYPE_SET(m0, sw_hashtype[rss->hash_type][rss->ipv6]); 1889 m0->m_pkthdr.flowid = be32toh(rss->hash_val); 1890 1891 if (cpl->csum_calc && !(cpl->err_vec & sc->params.tp.err_vec_mask)) { 1892 if (ifp->if_capenable & IFCAP_RXCSUM && 1893 cpl->l2info & htobe32(F_RXF_IP)) { 1894 m0->m_pkthdr.csum_flags = (CSUM_IP_CHECKED | 1895 CSUM_IP_VALID | CSUM_DATA_VALID | CSUM_PSEUDO_HDR); 1896 rxq->rxcsum++; 1897 } else if (ifp->if_capenable & IFCAP_RXCSUM_IPV6 && 1898 cpl->l2info & htobe32(F_RXF_IP6)) { 1899 m0->m_pkthdr.csum_flags = (CSUM_DATA_VALID_IPV6 | 1900 CSUM_PSEUDO_HDR); 1901 rxq->rxcsum++; 1902 } 1903 1904 if (__predict_false(cpl->ip_frag)) 1905 m0->m_pkthdr.csum_data = be16toh(cpl->csum); 1906 else 1907 m0->m_pkthdr.csum_data = 0xffff; 1908 } 1909 1910 if (cpl->vlan_ex) { 1911 m0->m_pkthdr.ether_vtag = be16toh(cpl->vlan); 1912 m0->m_flags |= M_VLANTAG; 1913 rxq->vlan_extraction++; 1914 } 1915 1916 #if defined(INET) || defined(INET6) 1917 if (iq->flags & IQ_LRO_ENABLED) { 1918 if (sort_before_lro(lro)) { 1919 tcp_lro_queue_mbuf(lro, m0); 1920 return (0); /* queued for sort, then LRO */ 1921 } 1922 if (tcp_lro_rx(lro, m0, 0) == 0) 1923 return (0); /* queued for LRO */ 1924 } 1925 #endif 1926 ifp->if_input(ifp, m0); 1927 1928 return (0); 1929 } 1930 1931 /* 1932 * Must drain the wrq or make sure that someone else will. 1933 */ 1934 static void 1935 wrq_tx_drain(void *arg, int n) 1936 { 1937 struct sge_wrq *wrq = arg; 1938 struct sge_eq *eq = &wrq->eq; 1939 1940 EQ_LOCK(eq); 1941 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 1942 drain_wrq_wr_list(wrq->adapter, wrq); 1943 EQ_UNLOCK(eq); 1944 } 1945 1946 static void 1947 drain_wrq_wr_list(struct adapter *sc, struct sge_wrq *wrq) 1948 { 1949 struct sge_eq *eq = &wrq->eq; 1950 u_int available, dbdiff; /* # of hardware descriptors */ 1951 u_int n; 1952 struct wrqe *wr; 1953 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */ 1954 1955 EQ_LOCK_ASSERT_OWNED(eq); 1956 MPASS(TAILQ_EMPTY(&wrq->incomplete_wrs)); 1957 wr = STAILQ_FIRST(&wrq->wr_list); 1958 MPASS(wr != NULL); /* Must be called with something useful to do */ 1959 MPASS(eq->pidx == eq->dbidx); 1960 dbdiff = 0; 1961 1962 do { 1963 eq->cidx = read_hw_cidx(eq); 1964 if (eq->pidx == eq->cidx) 1965 available = eq->sidx - 1; 1966 else 1967 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 1968 1969 MPASS(wr->wrq == wrq); 1970 n = howmany(wr->wr_len, EQ_ESIZE); 1971 if (available < n) 1972 break; 1973 1974 dst = (void *)&eq->desc[eq->pidx]; 1975 if (__predict_true(eq->sidx - eq->pidx > n)) { 1976 /* Won't wrap, won't end exactly at the status page. */ 1977 bcopy(&wr->wr[0], dst, wr->wr_len); 1978 eq->pidx += n; 1979 } else { 1980 int first_portion = (eq->sidx - eq->pidx) * EQ_ESIZE; 1981 1982 bcopy(&wr->wr[0], dst, first_portion); 1983 if (wr->wr_len > first_portion) { 1984 bcopy(&wr->wr[first_portion], &eq->desc[0], 1985 wr->wr_len - first_portion); 1986 } 1987 eq->pidx = n - (eq->sidx - eq->pidx); 1988 } 1989 wrq->tx_wrs_copied++; 1990 1991 if (available < eq->sidx / 4 && 1992 atomic_cmpset_int(&eq->equiq, 0, 1)) { 1993 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ | 1994 F_FW_WR_EQUEQ); 1995 eq->equeqidx = eq->pidx; 1996 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 32) { 1997 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ); 1998 eq->equeqidx = eq->pidx; 1999 } 2000 2001 dbdiff += n; 2002 if (dbdiff >= 16) { 2003 ring_eq_db(sc, eq, dbdiff); 2004 dbdiff = 0; 2005 } 2006 2007 STAILQ_REMOVE_HEAD(&wrq->wr_list, link); 2008 free_wrqe(wr); 2009 MPASS(wrq->nwr_pending > 0); 2010 wrq->nwr_pending--; 2011 MPASS(wrq->ndesc_needed >= n); 2012 wrq->ndesc_needed -= n; 2013 } while ((wr = STAILQ_FIRST(&wrq->wr_list)) != NULL); 2014 2015 if (dbdiff) 2016 ring_eq_db(sc, eq, dbdiff); 2017 } 2018 2019 /* 2020 * Doesn't fail. Holds on to work requests it can't send right away. 2021 */ 2022 void 2023 t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, struct wrqe *wr) 2024 { 2025 #ifdef INVARIANTS 2026 struct sge_eq *eq = &wrq->eq; 2027 #endif 2028 2029 EQ_LOCK_ASSERT_OWNED(eq); 2030 MPASS(wr != NULL); 2031 MPASS(wr->wr_len > 0 && wr->wr_len <= SGE_MAX_WR_LEN); 2032 MPASS((wr->wr_len & 0x7) == 0); 2033 2034 STAILQ_INSERT_TAIL(&wrq->wr_list, wr, link); 2035 wrq->nwr_pending++; 2036 wrq->ndesc_needed += howmany(wr->wr_len, EQ_ESIZE); 2037 2038 if (!TAILQ_EMPTY(&wrq->incomplete_wrs)) 2039 return; /* commit_wrq_wr will drain wr_list as well. */ 2040 2041 drain_wrq_wr_list(sc, wrq); 2042 2043 /* Doorbell must have caught up to the pidx. */ 2044 MPASS(eq->pidx == eq->dbidx); 2045 } 2046 2047 void 2048 t4_update_fl_bufsize(struct ifnet *ifp) 2049 { 2050 struct vi_info *vi = ifp->if_softc; 2051 struct adapter *sc = vi->pi->adapter; 2052 struct sge_rxq *rxq; 2053 #ifdef TCP_OFFLOAD 2054 struct sge_ofld_rxq *ofld_rxq; 2055 #endif 2056 struct sge_fl *fl; 2057 int i, maxp, mtu = ifp->if_mtu; 2058 2059 maxp = mtu_to_max_payload(sc, mtu, 0); 2060 for_each_rxq(vi, i, rxq) { 2061 fl = &rxq->fl; 2062 2063 FL_LOCK(fl); 2064 find_best_refill_source(sc, fl, maxp); 2065 FL_UNLOCK(fl); 2066 } 2067 #ifdef TCP_OFFLOAD 2068 maxp = mtu_to_max_payload(sc, mtu, 1); 2069 for_each_ofld_rxq(vi, i, ofld_rxq) { 2070 fl = &ofld_rxq->fl; 2071 2072 FL_LOCK(fl); 2073 find_best_refill_source(sc, fl, maxp); 2074 FL_UNLOCK(fl); 2075 } 2076 #endif 2077 } 2078 2079 static inline int 2080 mbuf_nsegs(struct mbuf *m) 2081 { 2082 2083 M_ASSERTPKTHDR(m); 2084 KASSERT(m->m_pkthdr.l5hlen > 0, 2085 ("%s: mbuf %p missing information on # of segments.", __func__, m)); 2086 2087 return (m->m_pkthdr.l5hlen); 2088 } 2089 2090 static inline void 2091 set_mbuf_nsegs(struct mbuf *m, uint8_t nsegs) 2092 { 2093 2094 M_ASSERTPKTHDR(m); 2095 m->m_pkthdr.l5hlen = nsegs; 2096 } 2097 2098 static inline int 2099 mbuf_len16(struct mbuf *m) 2100 { 2101 int n; 2102 2103 M_ASSERTPKTHDR(m); 2104 n = m->m_pkthdr.PH_loc.eight[0]; 2105 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16); 2106 2107 return (n); 2108 } 2109 2110 static inline void 2111 set_mbuf_len16(struct mbuf *m, uint8_t len16) 2112 { 2113 2114 M_ASSERTPKTHDR(m); 2115 m->m_pkthdr.PH_loc.eight[0] = len16; 2116 } 2117 2118 static inline int 2119 needs_tso(struct mbuf *m) 2120 { 2121 2122 M_ASSERTPKTHDR(m); 2123 2124 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 2125 KASSERT(m->m_pkthdr.tso_segsz > 0, 2126 ("%s: TSO requested in mbuf %p but MSS not provided", 2127 __func__, m)); 2128 return (1); 2129 } 2130 2131 return (0); 2132 } 2133 2134 static inline int 2135 needs_l3_csum(struct mbuf *m) 2136 { 2137 2138 M_ASSERTPKTHDR(m); 2139 2140 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TSO)) 2141 return (1); 2142 return (0); 2143 } 2144 2145 static inline int 2146 needs_l4_csum(struct mbuf *m) 2147 { 2148 2149 M_ASSERTPKTHDR(m); 2150 2151 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_UDP_IPV6 | 2152 CSUM_TCP_IPV6 | CSUM_TSO)) 2153 return (1); 2154 return (0); 2155 } 2156 2157 static inline int 2158 needs_vlan_insertion(struct mbuf *m) 2159 { 2160 2161 M_ASSERTPKTHDR(m); 2162 2163 if (m->m_flags & M_VLANTAG) { 2164 KASSERT(m->m_pkthdr.ether_vtag != 0, 2165 ("%s: HWVLAN requested in mbuf %p but tag not provided", 2166 __func__, m)); 2167 return (1); 2168 } 2169 return (0); 2170 } 2171 2172 static void * 2173 m_advance(struct mbuf **pm, int *poffset, int len) 2174 { 2175 struct mbuf *m = *pm; 2176 int offset = *poffset; 2177 uintptr_t p = 0; 2178 2179 MPASS(len > 0); 2180 2181 for (;;) { 2182 if (offset + len < m->m_len) { 2183 offset += len; 2184 p = mtod(m, uintptr_t) + offset; 2185 break; 2186 } 2187 len -= m->m_len - offset; 2188 m = m->m_next; 2189 offset = 0; 2190 MPASS(m != NULL); 2191 } 2192 *poffset = offset; 2193 *pm = m; 2194 return ((void *)p); 2195 } 2196 2197 /* 2198 * Can deal with empty mbufs in the chain that have m_len = 0, but the chain 2199 * must have at least one mbuf that's not empty. 2200 */ 2201 static inline int 2202 count_mbuf_nsegs(struct mbuf *m) 2203 { 2204 vm_paddr_t lastb, next; 2205 vm_offset_t va; 2206 int len, nsegs; 2207 2208 MPASS(m != NULL); 2209 2210 nsegs = 0; 2211 lastb = 0; 2212 for (; m; m = m->m_next) { 2213 2214 len = m->m_len; 2215 if (__predict_false(len == 0)) 2216 continue; 2217 va = mtod(m, vm_offset_t); 2218 next = pmap_kextract(va); 2219 nsegs += sglist_count(m->m_data, len); 2220 if (lastb + 1 == next) 2221 nsegs--; 2222 lastb = pmap_kextract(va + len - 1); 2223 } 2224 2225 MPASS(nsegs > 0); 2226 return (nsegs); 2227 } 2228 2229 /* 2230 * Analyze the mbuf to determine its tx needs. The mbuf passed in may change: 2231 * a) caller can assume it's been freed if this function returns with an error. 2232 * b) it may get defragged up if the gather list is too long for the hardware. 2233 */ 2234 int 2235 parse_pkt(struct adapter *sc, struct mbuf **mp) 2236 { 2237 struct mbuf *m0 = *mp, *m; 2238 int rc, nsegs, defragged = 0, offset; 2239 struct ether_header *eh; 2240 void *l3hdr; 2241 #if defined(INET) || defined(INET6) 2242 struct tcphdr *tcp; 2243 #endif 2244 uint16_t eh_type; 2245 2246 M_ASSERTPKTHDR(m0); 2247 if (__predict_false(m0->m_pkthdr.len < ETHER_HDR_LEN)) { 2248 rc = EINVAL; 2249 fail: 2250 m_freem(m0); 2251 *mp = NULL; 2252 return (rc); 2253 } 2254 restart: 2255 /* 2256 * First count the number of gather list segments in the payload. 2257 * Defrag the mbuf if nsegs exceeds the hardware limit. 2258 */ 2259 M_ASSERTPKTHDR(m0); 2260 MPASS(m0->m_pkthdr.len > 0); 2261 nsegs = count_mbuf_nsegs(m0); 2262 if (nsegs > (needs_tso(m0) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS)) { 2263 if (defragged++ > 0 || (m = m_defrag(m0, M_NOWAIT)) == NULL) { 2264 rc = EFBIG; 2265 goto fail; 2266 } 2267 *mp = m0 = m; /* update caller's copy after defrag */ 2268 goto restart; 2269 } 2270 2271 if (__predict_false(nsegs > 2 && m0->m_pkthdr.len <= MHLEN)) { 2272 m0 = m_pullup(m0, m0->m_pkthdr.len); 2273 if (m0 == NULL) { 2274 /* Should have left well enough alone. */ 2275 rc = EFBIG; 2276 goto fail; 2277 } 2278 *mp = m0; /* update caller's copy after pullup */ 2279 goto restart; 2280 } 2281 set_mbuf_nsegs(m0, nsegs); 2282 if (sc->flags & IS_VF) 2283 set_mbuf_len16(m0, txpkt_vm_len16(nsegs, needs_tso(m0))); 2284 else 2285 set_mbuf_len16(m0, txpkt_len16(nsegs, needs_tso(m0))); 2286 2287 if (!needs_tso(m0) && 2288 !(sc->flags & IS_VF && (needs_l3_csum(m0) || needs_l4_csum(m0)))) 2289 return (0); 2290 2291 m = m0; 2292 eh = mtod(m, struct ether_header *); 2293 eh_type = ntohs(eh->ether_type); 2294 if (eh_type == ETHERTYPE_VLAN) { 2295 struct ether_vlan_header *evh = (void *)eh; 2296 2297 eh_type = ntohs(evh->evl_proto); 2298 m0->m_pkthdr.l2hlen = sizeof(*evh); 2299 } else 2300 m0->m_pkthdr.l2hlen = sizeof(*eh); 2301 2302 offset = 0; 2303 l3hdr = m_advance(&m, &offset, m0->m_pkthdr.l2hlen); 2304 2305 switch (eh_type) { 2306 #ifdef INET6 2307 case ETHERTYPE_IPV6: 2308 { 2309 struct ip6_hdr *ip6 = l3hdr; 2310 2311 MPASS(!needs_tso(m0) || ip6->ip6_nxt == IPPROTO_TCP); 2312 2313 m0->m_pkthdr.l3hlen = sizeof(*ip6); 2314 break; 2315 } 2316 #endif 2317 #ifdef INET 2318 case ETHERTYPE_IP: 2319 { 2320 struct ip *ip = l3hdr; 2321 2322 m0->m_pkthdr.l3hlen = ip->ip_hl * 4; 2323 break; 2324 } 2325 #endif 2326 default: 2327 panic("%s: ethertype 0x%04x unknown. if_cxgbe must be compiled" 2328 " with the same INET/INET6 options as the kernel.", 2329 __func__, eh_type); 2330 } 2331 2332 #if defined(INET) || defined(INET6) 2333 if (needs_tso(m0)) { 2334 tcp = m_advance(&m, &offset, m0->m_pkthdr.l3hlen); 2335 m0->m_pkthdr.l4hlen = tcp->th_off * 4; 2336 } 2337 #endif 2338 MPASS(m0 == *mp); 2339 return (0); 2340 } 2341 2342 void * 2343 start_wrq_wr(struct sge_wrq *wrq, int len16, struct wrq_cookie *cookie) 2344 { 2345 struct sge_eq *eq = &wrq->eq; 2346 struct adapter *sc = wrq->adapter; 2347 int ndesc, available; 2348 struct wrqe *wr; 2349 void *w; 2350 2351 MPASS(len16 > 0); 2352 ndesc = howmany(len16, EQ_ESIZE / 16); 2353 MPASS(ndesc > 0 && ndesc <= SGE_MAX_WR_NDESC); 2354 2355 EQ_LOCK(eq); 2356 2357 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 2358 drain_wrq_wr_list(sc, wrq); 2359 2360 if (!STAILQ_EMPTY(&wrq->wr_list)) { 2361 slowpath: 2362 EQ_UNLOCK(eq); 2363 wr = alloc_wrqe(len16 * 16, wrq); 2364 if (__predict_false(wr == NULL)) 2365 return (NULL); 2366 cookie->pidx = -1; 2367 cookie->ndesc = ndesc; 2368 return (&wr->wr); 2369 } 2370 2371 eq->cidx = read_hw_cidx(eq); 2372 if (eq->pidx == eq->cidx) 2373 available = eq->sidx - 1; 2374 else 2375 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2376 if (available < ndesc) 2377 goto slowpath; 2378 2379 cookie->pidx = eq->pidx; 2380 cookie->ndesc = ndesc; 2381 TAILQ_INSERT_TAIL(&wrq->incomplete_wrs, cookie, link); 2382 2383 w = &eq->desc[eq->pidx]; 2384 IDXINCR(eq->pidx, ndesc, eq->sidx); 2385 if (__predict_false(cookie->pidx + ndesc > eq->sidx)) { 2386 w = &wrq->ss[0]; 2387 wrq->ss_pidx = cookie->pidx; 2388 wrq->ss_len = len16 * 16; 2389 } 2390 2391 EQ_UNLOCK(eq); 2392 2393 return (w); 2394 } 2395 2396 void 2397 commit_wrq_wr(struct sge_wrq *wrq, void *w, struct wrq_cookie *cookie) 2398 { 2399 struct sge_eq *eq = &wrq->eq; 2400 struct adapter *sc = wrq->adapter; 2401 int ndesc, pidx; 2402 struct wrq_cookie *prev, *next; 2403 2404 if (cookie->pidx == -1) { 2405 struct wrqe *wr = __containerof(w, struct wrqe, wr); 2406 2407 t4_wrq_tx(sc, wr); 2408 return; 2409 } 2410 2411 if (__predict_false(w == &wrq->ss[0])) { 2412 int n = (eq->sidx - wrq->ss_pidx) * EQ_ESIZE; 2413 2414 MPASS(wrq->ss_len > n); /* WR had better wrap around. */ 2415 bcopy(&wrq->ss[0], &eq->desc[wrq->ss_pidx], n); 2416 bcopy(&wrq->ss[n], &eq->desc[0], wrq->ss_len - n); 2417 wrq->tx_wrs_ss++; 2418 } else 2419 wrq->tx_wrs_direct++; 2420 2421 EQ_LOCK(eq); 2422 ndesc = cookie->ndesc; /* Can be more than SGE_MAX_WR_NDESC here. */ 2423 pidx = cookie->pidx; 2424 MPASS(pidx >= 0 && pidx < eq->sidx); 2425 prev = TAILQ_PREV(cookie, wrq_incomplete_wrs, link); 2426 next = TAILQ_NEXT(cookie, link); 2427 if (prev == NULL) { 2428 MPASS(pidx == eq->dbidx); 2429 if (next == NULL || ndesc >= 16) 2430 ring_eq_db(wrq->adapter, eq, ndesc); 2431 else { 2432 MPASS(IDXDIFF(next->pidx, pidx, eq->sidx) == ndesc); 2433 next->pidx = pidx; 2434 next->ndesc += ndesc; 2435 } 2436 } else { 2437 MPASS(IDXDIFF(pidx, prev->pidx, eq->sidx) == prev->ndesc); 2438 prev->ndesc += ndesc; 2439 } 2440 TAILQ_REMOVE(&wrq->incomplete_wrs, cookie, link); 2441 2442 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 2443 drain_wrq_wr_list(sc, wrq); 2444 2445 #ifdef INVARIANTS 2446 if (TAILQ_EMPTY(&wrq->incomplete_wrs)) { 2447 /* Doorbell must have caught up to the pidx. */ 2448 MPASS(wrq->eq.pidx == wrq->eq.dbidx); 2449 } 2450 #endif 2451 EQ_UNLOCK(eq); 2452 } 2453 2454 static u_int 2455 can_resume_eth_tx(struct mp_ring *r) 2456 { 2457 struct sge_eq *eq = r->cookie; 2458 2459 return (total_available_tx_desc(eq) > eq->sidx / 8); 2460 } 2461 2462 static inline int 2463 cannot_use_txpkts(struct mbuf *m) 2464 { 2465 /* maybe put a GL limit too, to avoid silliness? */ 2466 2467 return (needs_tso(m)); 2468 } 2469 2470 static inline int 2471 discard_tx(struct sge_eq *eq) 2472 { 2473 2474 return ((eq->flags & (EQ_ENABLED | EQ_QFLUSH)) != EQ_ENABLED); 2475 } 2476 2477 /* 2478 * r->items[cidx] to r->items[pidx], with a wraparound at r->size, are ready to 2479 * be consumed. Return the actual number consumed. 0 indicates a stall. 2480 */ 2481 static u_int 2482 eth_tx(struct mp_ring *r, u_int cidx, u_int pidx) 2483 { 2484 struct sge_txq *txq = r->cookie; 2485 struct sge_eq *eq = &txq->eq; 2486 struct ifnet *ifp = txq->ifp; 2487 struct vi_info *vi = ifp->if_softc; 2488 struct port_info *pi = vi->pi; 2489 struct adapter *sc = pi->adapter; 2490 u_int total, remaining; /* # of packets */ 2491 u_int available, dbdiff; /* # of hardware descriptors */ 2492 u_int n, next_cidx; 2493 struct mbuf *m0, *tail; 2494 struct txpkts txp; 2495 struct fw_eth_tx_pkts_wr *wr; /* any fw WR struct will do */ 2496 2497 remaining = IDXDIFF(pidx, cidx, r->size); 2498 MPASS(remaining > 0); /* Must not be called without work to do. */ 2499 total = 0; 2500 2501 TXQ_LOCK(txq); 2502 if (__predict_false(discard_tx(eq))) { 2503 while (cidx != pidx) { 2504 m0 = r->items[cidx]; 2505 m_freem(m0); 2506 if (++cidx == r->size) 2507 cidx = 0; 2508 } 2509 reclaim_tx_descs(txq, 2048); 2510 total = remaining; 2511 goto done; 2512 } 2513 2514 /* How many hardware descriptors do we have readily available. */ 2515 if (eq->pidx == eq->cidx) 2516 available = eq->sidx - 1; 2517 else 2518 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2519 dbdiff = IDXDIFF(eq->pidx, eq->dbidx, eq->sidx); 2520 2521 while (remaining > 0) { 2522 2523 m0 = r->items[cidx]; 2524 M_ASSERTPKTHDR(m0); 2525 MPASS(m0->m_nextpkt == NULL); 2526 2527 if (available < SGE_MAX_WR_NDESC) { 2528 available += reclaim_tx_descs(txq, 64); 2529 if (available < howmany(mbuf_len16(m0), EQ_ESIZE / 16)) 2530 break; /* out of descriptors */ 2531 } 2532 2533 next_cidx = cidx + 1; 2534 if (__predict_false(next_cidx == r->size)) 2535 next_cidx = 0; 2536 2537 wr = (void *)&eq->desc[eq->pidx]; 2538 if (sc->flags & IS_VF) { 2539 total++; 2540 remaining--; 2541 ETHER_BPF_MTAP(ifp, m0); 2542 n = write_txpkt_vm_wr(sc, txq, (void *)wr, m0, 2543 available); 2544 } else if (remaining > 1 && 2545 try_txpkts(m0, r->items[next_cidx], &txp, available) == 0) { 2546 2547 /* pkts at cidx, next_cidx should both be in txp. */ 2548 MPASS(txp.npkt == 2); 2549 tail = r->items[next_cidx]; 2550 MPASS(tail->m_nextpkt == NULL); 2551 ETHER_BPF_MTAP(ifp, m0); 2552 ETHER_BPF_MTAP(ifp, tail); 2553 m0->m_nextpkt = tail; 2554 2555 if (__predict_false(++next_cidx == r->size)) 2556 next_cidx = 0; 2557 2558 while (next_cidx != pidx) { 2559 if (add_to_txpkts(r->items[next_cidx], &txp, 2560 available) != 0) 2561 break; 2562 tail->m_nextpkt = r->items[next_cidx]; 2563 tail = tail->m_nextpkt; 2564 ETHER_BPF_MTAP(ifp, tail); 2565 if (__predict_false(++next_cidx == r->size)) 2566 next_cidx = 0; 2567 } 2568 2569 n = write_txpkts_wr(txq, wr, m0, &txp, available); 2570 total += txp.npkt; 2571 remaining -= txp.npkt; 2572 } else { 2573 total++; 2574 remaining--; 2575 ETHER_BPF_MTAP(ifp, m0); 2576 n = write_txpkt_wr(txq, (void *)wr, m0, available); 2577 } 2578 MPASS(n >= 1 && n <= available && n <= SGE_MAX_WR_NDESC); 2579 2580 available -= n; 2581 dbdiff += n; 2582 IDXINCR(eq->pidx, n, eq->sidx); 2583 2584 if (total_available_tx_desc(eq) < eq->sidx / 4 && 2585 atomic_cmpset_int(&eq->equiq, 0, 1)) { 2586 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ | 2587 F_FW_WR_EQUEQ); 2588 eq->equeqidx = eq->pidx; 2589 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 32) { 2590 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ); 2591 eq->equeqidx = eq->pidx; 2592 } 2593 2594 if (dbdiff >= 16 && remaining >= 4) { 2595 ring_eq_db(sc, eq, dbdiff); 2596 available += reclaim_tx_descs(txq, 4 * dbdiff); 2597 dbdiff = 0; 2598 } 2599 2600 cidx = next_cidx; 2601 } 2602 if (dbdiff != 0) { 2603 ring_eq_db(sc, eq, dbdiff); 2604 reclaim_tx_descs(txq, 32); 2605 } 2606 done: 2607 TXQ_UNLOCK(txq); 2608 2609 return (total); 2610 } 2611 2612 static inline void 2613 init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int pktc_idx, 2614 int qsize) 2615 { 2616 2617 KASSERT(tmr_idx >= 0 && tmr_idx < SGE_NTIMERS, 2618 ("%s: bad tmr_idx %d", __func__, tmr_idx)); 2619 KASSERT(pktc_idx < SGE_NCOUNTERS, /* -ve is ok, means don't use */ 2620 ("%s: bad pktc_idx %d", __func__, pktc_idx)); 2621 2622 iq->flags = 0; 2623 iq->adapter = sc; 2624 iq->intr_params = V_QINTR_TIMER_IDX(tmr_idx); 2625 iq->intr_pktc_idx = SGE_NCOUNTERS - 1; 2626 if (pktc_idx >= 0) { 2627 iq->intr_params |= F_QINTR_CNT_EN; 2628 iq->intr_pktc_idx = pktc_idx; 2629 } 2630 iq->qsize = roundup2(qsize, 16); /* See FW_IQ_CMD/iqsize */ 2631 iq->sidx = iq->qsize - sc->params.sge.spg_len / IQ_ESIZE; 2632 } 2633 2634 static inline void 2635 init_fl(struct adapter *sc, struct sge_fl *fl, int qsize, int maxp, char *name) 2636 { 2637 2638 fl->qsize = qsize; 2639 fl->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE; 2640 strlcpy(fl->lockname, name, sizeof(fl->lockname)); 2641 if (sc->flags & BUF_PACKING_OK && 2642 ((!is_t4(sc) && buffer_packing) || /* T5+: enabled unless 0 */ 2643 (is_t4(sc) && buffer_packing == 1)))/* T4: disabled unless 1 */ 2644 fl->flags |= FL_BUF_PACKING; 2645 find_best_refill_source(sc, fl, maxp); 2646 find_safe_refill_source(sc, fl); 2647 } 2648 2649 static inline void 2650 init_eq(struct adapter *sc, struct sge_eq *eq, int eqtype, int qsize, 2651 uint8_t tx_chan, uint16_t iqid, char *name) 2652 { 2653 KASSERT(eqtype <= EQ_TYPEMASK, ("%s: bad qtype %d", __func__, eqtype)); 2654 2655 eq->flags = eqtype & EQ_TYPEMASK; 2656 eq->tx_chan = tx_chan; 2657 eq->iqid = iqid; 2658 eq->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE; 2659 strlcpy(eq->lockname, name, sizeof(eq->lockname)); 2660 } 2661 2662 static int 2663 alloc_ring(struct adapter *sc, size_t len, bus_dma_tag_t *tag, 2664 bus_dmamap_t *map, bus_addr_t *pa, void **va) 2665 { 2666 int rc; 2667 2668 rc = bus_dma_tag_create(sc->dmat, 512, 0, BUS_SPACE_MAXADDR, 2669 BUS_SPACE_MAXADDR, NULL, NULL, len, 1, len, 0, NULL, NULL, tag); 2670 if (rc != 0) { 2671 device_printf(sc->dev, "cannot allocate DMA tag: %d\n", rc); 2672 goto done; 2673 } 2674 2675 rc = bus_dmamem_alloc(*tag, va, 2676 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, map); 2677 if (rc != 0) { 2678 device_printf(sc->dev, "cannot allocate DMA memory: %d\n", rc); 2679 goto done; 2680 } 2681 2682 rc = bus_dmamap_load(*tag, *map, *va, len, oneseg_dma_callback, pa, 0); 2683 if (rc != 0) { 2684 device_printf(sc->dev, "cannot load DMA map: %d\n", rc); 2685 goto done; 2686 } 2687 done: 2688 if (rc) 2689 free_ring(sc, *tag, *map, *pa, *va); 2690 2691 return (rc); 2692 } 2693 2694 static int 2695 free_ring(struct adapter *sc, bus_dma_tag_t tag, bus_dmamap_t map, 2696 bus_addr_t pa, void *va) 2697 { 2698 if (pa) 2699 bus_dmamap_unload(tag, map); 2700 if (va) 2701 bus_dmamem_free(tag, va, map); 2702 if (tag) 2703 bus_dma_tag_destroy(tag); 2704 2705 return (0); 2706 } 2707 2708 /* 2709 * Allocates the ring for an ingress queue and an optional freelist. If the 2710 * freelist is specified it will be allocated and then associated with the 2711 * ingress queue. 2712 * 2713 * Returns errno on failure. Resources allocated up to that point may still be 2714 * allocated. Caller is responsible for cleanup in case this function fails. 2715 * 2716 * If the ingress queue will take interrupts directly (iq->flags & IQ_INTR) then 2717 * the intr_idx specifies the vector, starting from 0. Otherwise it specifies 2718 * the abs_id of the ingress queue to which its interrupts should be forwarded. 2719 */ 2720 static int 2721 alloc_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl, 2722 int intr_idx, int cong) 2723 { 2724 int rc, i, cntxt_id; 2725 size_t len; 2726 struct fw_iq_cmd c; 2727 struct port_info *pi = vi->pi; 2728 struct adapter *sc = iq->adapter; 2729 struct sge_params *sp = &sc->params.sge; 2730 __be32 v = 0; 2731 2732 len = iq->qsize * IQ_ESIZE; 2733 rc = alloc_ring(sc, len, &iq->desc_tag, &iq->desc_map, &iq->ba, 2734 (void **)&iq->desc); 2735 if (rc != 0) 2736 return (rc); 2737 2738 bzero(&c, sizeof(c)); 2739 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 2740 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) | 2741 V_FW_IQ_CMD_VFN(0)); 2742 2743 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART | 2744 FW_LEN16(c)); 2745 2746 /* Special handling for firmware event queue */ 2747 if (iq == &sc->sge.fwq) 2748 v |= F_FW_IQ_CMD_IQASYNCH; 2749 2750 if (iq->flags & IQ_INTR) { 2751 KASSERT(intr_idx < sc->intr_count, 2752 ("%s: invalid direct intr_idx %d", __func__, intr_idx)); 2753 } else 2754 v |= F_FW_IQ_CMD_IQANDST; 2755 v |= V_FW_IQ_CMD_IQANDSTINDEX(intr_idx); 2756 2757 c.type_to_iqandstindex = htobe32(v | 2758 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) | 2759 V_FW_IQ_CMD_VIID(vi->viid) | 2760 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT)); 2761 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->tx_chan) | 2762 F_FW_IQ_CMD_IQGTSMODE | 2763 V_FW_IQ_CMD_IQINTCNTTHRESH(iq->intr_pktc_idx) | 2764 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4)); 2765 c.iqsize = htobe16(iq->qsize); 2766 c.iqaddr = htobe64(iq->ba); 2767 if (cong >= 0) 2768 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN); 2769 2770 if (fl) { 2771 mtx_init(&fl->fl_lock, fl->lockname, NULL, MTX_DEF); 2772 2773 len = fl->qsize * EQ_ESIZE; 2774 rc = alloc_ring(sc, len, &fl->desc_tag, &fl->desc_map, 2775 &fl->ba, (void **)&fl->desc); 2776 if (rc) 2777 return (rc); 2778 2779 /* Allocate space for one software descriptor per buffer. */ 2780 rc = alloc_fl_sdesc(fl); 2781 if (rc != 0) { 2782 device_printf(sc->dev, 2783 "failed to setup fl software descriptors: %d\n", 2784 rc); 2785 return (rc); 2786 } 2787 2788 if (fl->flags & FL_BUF_PACKING) { 2789 fl->lowat = roundup2(sp->fl_starve_threshold2, 8); 2790 fl->buf_boundary = sp->pack_boundary; 2791 } else { 2792 fl->lowat = roundup2(sp->fl_starve_threshold, 8); 2793 fl->buf_boundary = 16; 2794 } 2795 if (fl_pad && fl->buf_boundary < sp->pad_boundary) 2796 fl->buf_boundary = sp->pad_boundary; 2797 2798 c.iqns_to_fl0congen |= 2799 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) | 2800 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO | 2801 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) | 2802 (fl->flags & FL_BUF_PACKING ? F_FW_IQ_CMD_FL0PACKEN : 2803 0)); 2804 if (cong >= 0) { 2805 c.iqns_to_fl0congen |= 2806 htobe32(V_FW_IQ_CMD_FL0CNGCHMAP(cong) | 2807 F_FW_IQ_CMD_FL0CONGCIF | 2808 F_FW_IQ_CMD_FL0CONGEN); 2809 } 2810 c.fl0dcaen_to_fl0cidxfthresh = 2811 htobe16(V_FW_IQ_CMD_FL0FBMIN(chip_id(sc) <= CHELSIO_T5 ? 2812 X_FETCHBURSTMIN_128B : X_FETCHBURSTMIN_64B) | 2813 V_FW_IQ_CMD_FL0FBMAX(chip_id(sc) <= CHELSIO_T5 ? 2814 X_FETCHBURSTMAX_512B : X_FETCHBURSTMAX_256B)); 2815 c.fl0size = htobe16(fl->qsize); 2816 c.fl0addr = htobe64(fl->ba); 2817 } 2818 2819 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 2820 if (rc != 0) { 2821 device_printf(sc->dev, 2822 "failed to create ingress queue: %d\n", rc); 2823 return (rc); 2824 } 2825 2826 iq->cidx = 0; 2827 iq->gen = F_RSPD_GEN; 2828 iq->intr_next = iq->intr_params; 2829 iq->cntxt_id = be16toh(c.iqid); 2830 iq->abs_id = be16toh(c.physiqid); 2831 iq->flags |= IQ_ALLOCATED; 2832 2833 cntxt_id = iq->cntxt_id - sc->sge.iq_start; 2834 if (cntxt_id >= sc->sge.niq) { 2835 panic ("%s: iq->cntxt_id (%d) more than the max (%d)", __func__, 2836 cntxt_id, sc->sge.niq - 1); 2837 } 2838 sc->sge.iqmap[cntxt_id] = iq; 2839 2840 if (fl) { 2841 u_int qid; 2842 2843 iq->flags |= IQ_HAS_FL; 2844 fl->cntxt_id = be16toh(c.fl0id); 2845 fl->pidx = fl->cidx = 0; 2846 2847 cntxt_id = fl->cntxt_id - sc->sge.eq_start; 2848 if (cntxt_id >= sc->sge.neq) { 2849 panic("%s: fl->cntxt_id (%d) more than the max (%d)", 2850 __func__, cntxt_id, sc->sge.neq - 1); 2851 } 2852 sc->sge.eqmap[cntxt_id] = (void *)fl; 2853 2854 qid = fl->cntxt_id; 2855 if (isset(&sc->doorbells, DOORBELL_UDB)) { 2856 uint32_t s_qpp = sc->params.sge.eq_s_qpp; 2857 uint32_t mask = (1 << s_qpp) - 1; 2858 volatile uint8_t *udb; 2859 2860 udb = sc->udbs_base + UDBS_DB_OFFSET; 2861 udb += (qid >> s_qpp) << PAGE_SHIFT; 2862 qid &= mask; 2863 if (qid < PAGE_SIZE / UDBS_SEG_SIZE) { 2864 udb += qid << UDBS_SEG_SHIFT; 2865 qid = 0; 2866 } 2867 fl->udb = (volatile void *)udb; 2868 } 2869 fl->dbval = V_QID(qid) | sc->chip_params->sge_fl_db; 2870 2871 FL_LOCK(fl); 2872 /* Enough to make sure the SGE doesn't think it's starved */ 2873 refill_fl(sc, fl, fl->lowat); 2874 FL_UNLOCK(fl); 2875 } 2876 2877 if (chip_id(sc) >= CHELSIO_T5 && !(sc->flags & IS_VF) && cong >= 0) { 2878 uint32_t param, val; 2879 2880 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 2881 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) | 2882 V_FW_PARAMS_PARAM_YZ(iq->cntxt_id); 2883 if (cong == 0) 2884 val = 1 << 19; 2885 else { 2886 val = 2 << 19; 2887 for (i = 0; i < 4; i++) { 2888 if (cong & (1 << i)) 2889 val |= 1 << (i << 2); 2890 } 2891 } 2892 2893 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 2894 if (rc != 0) { 2895 /* report error but carry on */ 2896 device_printf(sc->dev, 2897 "failed to set congestion manager context for " 2898 "ingress queue %d: %d\n", iq->cntxt_id, rc); 2899 } 2900 } 2901 2902 /* Enable IQ interrupts */ 2903 atomic_store_rel_int(&iq->state, IQS_IDLE); 2904 t4_write_reg(sc, sc->sge_gts_reg, V_SEINTARM(iq->intr_params) | 2905 V_INGRESSQID(iq->cntxt_id)); 2906 2907 return (0); 2908 } 2909 2910 static int 2911 free_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl) 2912 { 2913 int rc; 2914 struct adapter *sc = iq->adapter; 2915 device_t dev; 2916 2917 if (sc == NULL) 2918 return (0); /* nothing to do */ 2919 2920 dev = vi ? vi->dev : sc->dev; 2921 2922 if (iq->flags & IQ_ALLOCATED) { 2923 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0, 2924 FW_IQ_TYPE_FL_INT_CAP, iq->cntxt_id, 2925 fl ? fl->cntxt_id : 0xffff, 0xffff); 2926 if (rc != 0) { 2927 device_printf(dev, 2928 "failed to free queue %p: %d\n", iq, rc); 2929 return (rc); 2930 } 2931 iq->flags &= ~IQ_ALLOCATED; 2932 } 2933 2934 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, iq->desc); 2935 2936 bzero(iq, sizeof(*iq)); 2937 2938 if (fl) { 2939 free_ring(sc, fl->desc_tag, fl->desc_map, fl->ba, 2940 fl->desc); 2941 2942 if (fl->sdesc) 2943 free_fl_sdesc(sc, fl); 2944 2945 if (mtx_initialized(&fl->fl_lock)) 2946 mtx_destroy(&fl->fl_lock); 2947 2948 bzero(fl, sizeof(*fl)); 2949 } 2950 2951 return (0); 2952 } 2953 2954 static void 2955 add_fl_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx, 2956 struct sysctl_oid *oid, struct sge_fl *fl) 2957 { 2958 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 2959 2960 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL, 2961 "freelist"); 2962 children = SYSCTL_CHILDREN(oid); 2963 2964 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, 2965 &fl->ba, "bus address of descriptor ring"); 2966 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 2967 fl->sidx * EQ_ESIZE + sc->params.sge.spg_len, 2968 "desc ring size in bytes"); 2969 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 2970 CTLTYPE_INT | CTLFLAG_RD, &fl->cntxt_id, 0, sysctl_uint16, "I", 2971 "SGE context id of the freelist"); 2972 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "padding", CTLFLAG_RD, NULL, 2973 fl_pad ? 1 : 0, "padding enabled"); 2974 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "packing", CTLFLAG_RD, NULL, 2975 fl->flags & FL_BUF_PACKING ? 1 : 0, "packing enabled"); 2976 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &fl->cidx, 2977 0, "consumer index"); 2978 if (fl->flags & FL_BUF_PACKING) { 2979 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rx_offset", 2980 CTLFLAG_RD, &fl->rx_offset, 0, "packing rx offset"); 2981 } 2982 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &fl->pidx, 2983 0, "producer index"); 2984 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_allocated", 2985 CTLFLAG_RD, &fl->mbuf_allocated, "# of mbuf allocated"); 2986 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_inlined", 2987 CTLFLAG_RD, &fl->mbuf_inlined, "# of mbuf inlined in clusters"); 2988 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_allocated", 2989 CTLFLAG_RD, &fl->cl_allocated, "# of clusters allocated"); 2990 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_recycled", 2991 CTLFLAG_RD, &fl->cl_recycled, "# of clusters recycled"); 2992 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_fast_recycled", 2993 CTLFLAG_RD, &fl->cl_fast_recycled, "# of clusters recycled (fast)"); 2994 } 2995 2996 static int 2997 alloc_fwq(struct adapter *sc) 2998 { 2999 int rc, intr_idx; 3000 struct sge_iq *fwq = &sc->sge.fwq; 3001 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev); 3002 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3003 3004 init_iq(fwq, sc, 0, 0, FW_IQ_QSIZE); 3005 fwq->flags |= IQ_INTR; /* always */ 3006 if (sc->flags & IS_VF) 3007 intr_idx = 0; 3008 else { 3009 intr_idx = sc->intr_count > 1 ? 1 : 0; 3010 fwq->set_tcb_rpl = t4_filter_rpl; 3011 fwq->l2t_write_rpl = do_l2t_write_rpl; 3012 } 3013 rc = alloc_iq_fl(&sc->port[0]->vi[0], fwq, NULL, intr_idx, -1); 3014 if (rc != 0) { 3015 device_printf(sc->dev, 3016 "failed to create firmware event queue: %d\n", rc); 3017 return (rc); 3018 } 3019 3020 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "fwq", CTLFLAG_RD, 3021 NULL, "firmware event queue"); 3022 children = SYSCTL_CHILDREN(oid); 3023 3024 SYSCTL_ADD_UAUTO(&sc->ctx, children, OID_AUTO, "ba", CTLFLAG_RD, 3025 &fwq->ba, "bus address of descriptor ring"); 3026 SYSCTL_ADD_INT(&sc->ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3027 fwq->qsize * IQ_ESIZE, "descriptor ring size in bytes"); 3028 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "abs_id", 3029 CTLTYPE_INT | CTLFLAG_RD, &fwq->abs_id, 0, sysctl_uint16, "I", 3030 "absolute id of the queue"); 3031 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "cntxt_id", 3032 CTLTYPE_INT | CTLFLAG_RD, &fwq->cntxt_id, 0, sysctl_uint16, "I", 3033 "SGE context id of the queue"); 3034 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "cidx", 3035 CTLTYPE_INT | CTLFLAG_RD, &fwq->cidx, 0, sysctl_uint16, "I", 3036 "consumer index"); 3037 3038 return (0); 3039 } 3040 3041 static int 3042 free_fwq(struct adapter *sc) 3043 { 3044 return free_iq_fl(NULL, &sc->sge.fwq, NULL); 3045 } 3046 3047 static int 3048 alloc_mgmtq(struct adapter *sc) 3049 { 3050 int rc; 3051 struct sge_wrq *mgmtq = &sc->sge.mgmtq; 3052 char name[16]; 3053 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev); 3054 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3055 3056 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "mgmtq", CTLFLAG_RD, 3057 NULL, "management queue"); 3058 3059 snprintf(name, sizeof(name), "%s mgmtq", device_get_nameunit(sc->dev)); 3060 init_eq(sc, &mgmtq->eq, EQ_CTRL, CTRL_EQ_QSIZE, sc->port[0]->tx_chan, 3061 sc->sge.fwq.cntxt_id, name); 3062 rc = alloc_wrq(sc, NULL, mgmtq, oid); 3063 if (rc != 0) { 3064 device_printf(sc->dev, 3065 "failed to create management queue: %d\n", rc); 3066 return (rc); 3067 } 3068 3069 return (0); 3070 } 3071 3072 static int 3073 free_mgmtq(struct adapter *sc) 3074 { 3075 3076 return free_wrq(sc, &sc->sge.mgmtq); 3077 } 3078 3079 int 3080 tnl_cong(struct port_info *pi, int drop) 3081 { 3082 3083 if (drop == -1) 3084 return (-1); 3085 else if (drop == 1) 3086 return (0); 3087 else 3088 return (pi->rx_e_chan_map); 3089 } 3090 3091 static int 3092 alloc_rxq(struct vi_info *vi, struct sge_rxq *rxq, int intr_idx, int idx, 3093 struct sysctl_oid *oid) 3094 { 3095 int rc; 3096 struct adapter *sc = vi->pi->adapter; 3097 struct sysctl_oid_list *children; 3098 char name[16]; 3099 3100 rc = alloc_iq_fl(vi, &rxq->iq, &rxq->fl, intr_idx, 3101 tnl_cong(vi->pi, cong_drop)); 3102 if (rc != 0) 3103 return (rc); 3104 3105 if (idx == 0) 3106 sc->sge.iq_base = rxq->iq.abs_id - rxq->iq.cntxt_id; 3107 else 3108 KASSERT(rxq->iq.cntxt_id + sc->sge.iq_base == rxq->iq.abs_id, 3109 ("iq_base mismatch")); 3110 KASSERT(sc->sge.iq_base == 0 || sc->flags & IS_VF, 3111 ("PF with non-zero iq_base")); 3112 3113 /* 3114 * The freelist is just barely above the starvation threshold right now, 3115 * fill it up a bit more. 3116 */ 3117 FL_LOCK(&rxq->fl); 3118 refill_fl(sc, &rxq->fl, 128); 3119 FL_UNLOCK(&rxq->fl); 3120 3121 #if defined(INET) || defined(INET6) 3122 rc = tcp_lro_init_args(&rxq->lro, vi->ifp, lro_entries, lro_mbufs); 3123 if (rc != 0) 3124 return (rc); 3125 MPASS(rxq->lro.ifp == vi->ifp); /* also indicates LRO init'ed */ 3126 3127 if (vi->ifp->if_capenable & IFCAP_LRO) 3128 rxq->iq.flags |= IQ_LRO_ENABLED; 3129 #endif 3130 rxq->ifp = vi->ifp; 3131 3132 children = SYSCTL_CHILDREN(oid); 3133 3134 snprintf(name, sizeof(name), "%d", idx); 3135 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 3136 NULL, "rx queue"); 3137 children = SYSCTL_CHILDREN(oid); 3138 3139 SYSCTL_ADD_UAUTO(&vi->ctx, children, OID_AUTO, "ba", CTLFLAG_RD, 3140 &rxq->iq.ba, "bus address of descriptor ring"); 3141 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3142 rxq->iq.qsize * IQ_ESIZE, "descriptor ring size in bytes"); 3143 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "abs_id", 3144 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.abs_id, 0, sysctl_uint16, "I", 3145 "absolute id of the queue"); 3146 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cntxt_id", 3147 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.cntxt_id, 0, sysctl_uint16, "I", 3148 "SGE context id of the queue"); 3149 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx", 3150 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.cidx, 0, sysctl_uint16, "I", 3151 "consumer index"); 3152 #if defined(INET) || defined(INET6) 3153 SYSCTL_ADD_U64(&vi->ctx, children, OID_AUTO, "lro_queued", CTLFLAG_RD, 3154 &rxq->lro.lro_queued, 0, NULL); 3155 SYSCTL_ADD_U64(&vi->ctx, children, OID_AUTO, "lro_flushed", CTLFLAG_RD, 3156 &rxq->lro.lro_flushed, 0, NULL); 3157 #endif 3158 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "rxcsum", CTLFLAG_RD, 3159 &rxq->rxcsum, "# of times hardware assisted with checksum"); 3160 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_extraction", 3161 CTLFLAG_RD, &rxq->vlan_extraction, 3162 "# of times hardware extracted 802.1Q tag"); 3163 3164 add_fl_sysctls(sc, &vi->ctx, oid, &rxq->fl); 3165 3166 return (rc); 3167 } 3168 3169 static int 3170 free_rxq(struct vi_info *vi, struct sge_rxq *rxq) 3171 { 3172 int rc; 3173 3174 #if defined(INET) || defined(INET6) 3175 if (rxq->lro.ifp) { 3176 tcp_lro_free(&rxq->lro); 3177 rxq->lro.ifp = NULL; 3178 } 3179 #endif 3180 3181 rc = free_iq_fl(vi, &rxq->iq, &rxq->fl); 3182 if (rc == 0) 3183 bzero(rxq, sizeof(*rxq)); 3184 3185 return (rc); 3186 } 3187 3188 #ifdef TCP_OFFLOAD 3189 static int 3190 alloc_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq, 3191 int intr_idx, int idx, struct sysctl_oid *oid) 3192 { 3193 struct port_info *pi = vi->pi; 3194 int rc; 3195 struct sysctl_oid_list *children; 3196 char name[16]; 3197 3198 rc = alloc_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl, intr_idx, 0); 3199 if (rc != 0) 3200 return (rc); 3201 3202 children = SYSCTL_CHILDREN(oid); 3203 3204 snprintf(name, sizeof(name), "%d", idx); 3205 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 3206 NULL, "rx queue"); 3207 children = SYSCTL_CHILDREN(oid); 3208 3209 SYSCTL_ADD_UAUTO(&vi->ctx, children, OID_AUTO, "ba", CTLFLAG_RD, 3210 &ofld_rxq->iq.ba, "bus address of descriptor ring"); 3211 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3212 ofld_rxq->iq.qsize * IQ_ESIZE, "descriptor ring size in bytes"); 3213 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "abs_id", 3214 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.abs_id, 0, sysctl_uint16, 3215 "I", "absolute id of the queue"); 3216 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cntxt_id", 3217 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.cntxt_id, 0, sysctl_uint16, 3218 "I", "SGE context id of the queue"); 3219 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx", 3220 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.cidx, 0, sysctl_uint16, "I", 3221 "consumer index"); 3222 3223 add_fl_sysctls(pi->adapter, &vi->ctx, oid, &ofld_rxq->fl); 3224 3225 return (rc); 3226 } 3227 3228 static int 3229 free_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq) 3230 { 3231 int rc; 3232 3233 rc = free_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl); 3234 if (rc == 0) 3235 bzero(ofld_rxq, sizeof(*ofld_rxq)); 3236 3237 return (rc); 3238 } 3239 #endif 3240 3241 #ifdef DEV_NETMAP 3242 static int 3243 alloc_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq, int intr_idx, 3244 int idx, struct sysctl_oid *oid) 3245 { 3246 int rc; 3247 struct sysctl_oid_list *children; 3248 struct sysctl_ctx_list *ctx; 3249 char name[16]; 3250 size_t len; 3251 struct adapter *sc = vi->pi->adapter; 3252 struct netmap_adapter *na = NA(vi->ifp); 3253 3254 MPASS(na != NULL); 3255 3256 len = vi->qsize_rxq * IQ_ESIZE; 3257 rc = alloc_ring(sc, len, &nm_rxq->iq_desc_tag, &nm_rxq->iq_desc_map, 3258 &nm_rxq->iq_ba, (void **)&nm_rxq->iq_desc); 3259 if (rc != 0) 3260 return (rc); 3261 3262 len = na->num_rx_desc * EQ_ESIZE + sc->params.sge.spg_len; 3263 rc = alloc_ring(sc, len, &nm_rxq->fl_desc_tag, &nm_rxq->fl_desc_map, 3264 &nm_rxq->fl_ba, (void **)&nm_rxq->fl_desc); 3265 if (rc != 0) 3266 return (rc); 3267 3268 nm_rxq->vi = vi; 3269 nm_rxq->nid = idx; 3270 nm_rxq->iq_cidx = 0; 3271 nm_rxq->iq_sidx = vi->qsize_rxq - sc->params.sge.spg_len / IQ_ESIZE; 3272 nm_rxq->iq_gen = F_RSPD_GEN; 3273 nm_rxq->fl_pidx = nm_rxq->fl_cidx = 0; 3274 nm_rxq->fl_sidx = na->num_rx_desc; 3275 nm_rxq->intr_idx = intr_idx; 3276 nm_rxq->iq_cntxt_id = INVALID_NM_RXQ_CNTXT_ID; 3277 3278 ctx = &vi->ctx; 3279 children = SYSCTL_CHILDREN(oid); 3280 3281 snprintf(name, sizeof(name), "%d", idx); 3282 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, name, CTLFLAG_RD, NULL, 3283 "rx queue"); 3284 children = SYSCTL_CHILDREN(oid); 3285 3286 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "abs_id", 3287 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_abs_id, 0, sysctl_uint16, 3288 "I", "absolute id of the queue"); 3289 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 3290 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cntxt_id, 0, sysctl_uint16, 3291 "I", "SGE context id of the queue"); 3292 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx", 3293 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cidx, 0, sysctl_uint16, "I", 3294 "consumer index"); 3295 3296 children = SYSCTL_CHILDREN(oid); 3297 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL, 3298 "freelist"); 3299 children = SYSCTL_CHILDREN(oid); 3300 3301 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 3302 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->fl_cntxt_id, 0, sysctl_uint16, 3303 "I", "SGE context id of the freelist"); 3304 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, 3305 &nm_rxq->fl_cidx, 0, "consumer index"); 3306 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, 3307 &nm_rxq->fl_pidx, 0, "producer index"); 3308 3309 return (rc); 3310 } 3311 3312 3313 static int 3314 free_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq) 3315 { 3316 struct adapter *sc = vi->pi->adapter; 3317 3318 if (vi->flags & VI_INIT_DONE) 3319 MPASS(nm_rxq->iq_cntxt_id == INVALID_NM_RXQ_CNTXT_ID); 3320 else 3321 MPASS(nm_rxq->iq_cntxt_id == 0); 3322 3323 free_ring(sc, nm_rxq->iq_desc_tag, nm_rxq->iq_desc_map, nm_rxq->iq_ba, 3324 nm_rxq->iq_desc); 3325 free_ring(sc, nm_rxq->fl_desc_tag, nm_rxq->fl_desc_map, nm_rxq->fl_ba, 3326 nm_rxq->fl_desc); 3327 3328 return (0); 3329 } 3330 3331 static int 3332 alloc_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq, int iqidx, int idx, 3333 struct sysctl_oid *oid) 3334 { 3335 int rc; 3336 size_t len; 3337 struct port_info *pi = vi->pi; 3338 struct adapter *sc = pi->adapter; 3339 struct netmap_adapter *na = NA(vi->ifp); 3340 char name[16]; 3341 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3342 3343 len = na->num_tx_desc * EQ_ESIZE + sc->params.sge.spg_len; 3344 rc = alloc_ring(sc, len, &nm_txq->desc_tag, &nm_txq->desc_map, 3345 &nm_txq->ba, (void **)&nm_txq->desc); 3346 if (rc) 3347 return (rc); 3348 3349 nm_txq->pidx = nm_txq->cidx = 0; 3350 nm_txq->sidx = na->num_tx_desc; 3351 nm_txq->nid = idx; 3352 nm_txq->iqidx = iqidx; 3353 nm_txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) | 3354 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(G_FW_VIID_PFN(vi->viid)) | 3355 V_TXPKT_VF(G_FW_VIID_VIN(vi->viid)) | 3356 V_TXPKT_VF_VLD(G_FW_VIID_VIVLD(vi->viid))); 3357 nm_txq->cntxt_id = INVALID_NM_TXQ_CNTXT_ID; 3358 3359 snprintf(name, sizeof(name), "%d", idx); 3360 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 3361 NULL, "netmap tx queue"); 3362 children = SYSCTL_CHILDREN(oid); 3363 3364 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 3365 &nm_txq->cntxt_id, 0, "SGE context id of the queue"); 3366 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx", 3367 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->cidx, 0, sysctl_uint16, "I", 3368 "consumer index"); 3369 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "pidx", 3370 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->pidx, 0, sysctl_uint16, "I", 3371 "producer index"); 3372 3373 return (rc); 3374 } 3375 3376 static int 3377 free_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq) 3378 { 3379 struct adapter *sc = vi->pi->adapter; 3380 3381 if (vi->flags & VI_INIT_DONE) 3382 MPASS(nm_txq->cntxt_id == INVALID_NM_TXQ_CNTXT_ID); 3383 else 3384 MPASS(nm_txq->cntxt_id == 0); 3385 3386 free_ring(sc, nm_txq->desc_tag, nm_txq->desc_map, nm_txq->ba, 3387 nm_txq->desc); 3388 3389 return (0); 3390 } 3391 #endif 3392 3393 static int 3394 ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq) 3395 { 3396 int rc, cntxt_id; 3397 struct fw_eq_ctrl_cmd c; 3398 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 3399 3400 bzero(&c, sizeof(c)); 3401 3402 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | F_FW_CMD_REQUEST | 3403 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_CTRL_CMD_PFN(sc->pf) | 3404 V_FW_EQ_CTRL_CMD_VFN(0)); 3405 c.alloc_to_len16 = htobe32(F_FW_EQ_CTRL_CMD_ALLOC | 3406 F_FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c)); 3407 c.cmpliqid_eqid = htonl(V_FW_EQ_CTRL_CMD_CMPLIQID(eq->iqid)); 3408 c.physeqid_pkd = htobe32(0); 3409 c.fetchszm_to_iqid = 3410 htobe32(V_FW_EQ_CTRL_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 3411 V_FW_EQ_CTRL_CMD_PCIECHN(eq->tx_chan) | 3412 F_FW_EQ_CTRL_CMD_FETCHRO | V_FW_EQ_CTRL_CMD_IQID(eq->iqid)); 3413 c.dcaen_to_eqsize = 3414 htobe32(V_FW_EQ_CTRL_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 3415 V_FW_EQ_CTRL_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 3416 V_FW_EQ_CTRL_CMD_CIDXFTHRESH(X_CIDXFLUSHTHRESH_32) | 3417 V_FW_EQ_CTRL_CMD_EQSIZE(qsize)); 3418 c.eqaddr = htobe64(eq->ba); 3419 3420 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3421 if (rc != 0) { 3422 device_printf(sc->dev, 3423 "failed to create control queue %d: %d\n", eq->tx_chan, rc); 3424 return (rc); 3425 } 3426 eq->flags |= EQ_ALLOCATED; 3427 3428 eq->cntxt_id = G_FW_EQ_CTRL_CMD_EQID(be32toh(c.cmpliqid_eqid)); 3429 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 3430 if (cntxt_id >= sc->sge.neq) 3431 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 3432 cntxt_id, sc->sge.neq - 1); 3433 sc->sge.eqmap[cntxt_id] = eq; 3434 3435 return (rc); 3436 } 3437 3438 static int 3439 eth_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 3440 { 3441 int rc, cntxt_id; 3442 struct fw_eq_eth_cmd c; 3443 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 3444 3445 bzero(&c, sizeof(c)); 3446 3447 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST | 3448 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) | 3449 V_FW_EQ_ETH_CMD_VFN(0)); 3450 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC | 3451 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c)); 3452 c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE | 3453 F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(vi->viid)); 3454 c.fetchszm_to_iqid = 3455 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) | 3456 V_FW_EQ_ETH_CMD_PCIECHN(eq->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO | 3457 V_FW_EQ_ETH_CMD_IQID(eq->iqid)); 3458 c.dcaen_to_eqsize = htobe32(V_FW_EQ_ETH_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 3459 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 3460 V_FW_EQ_ETH_CMD_EQSIZE(qsize)); 3461 c.eqaddr = htobe64(eq->ba); 3462 3463 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3464 if (rc != 0) { 3465 device_printf(vi->dev, 3466 "failed to create Ethernet egress queue: %d\n", rc); 3467 return (rc); 3468 } 3469 eq->flags |= EQ_ALLOCATED; 3470 3471 eq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd)); 3472 eq->abs_id = G_FW_EQ_ETH_CMD_PHYSEQID(be32toh(c.physeqid_pkd)); 3473 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 3474 if (cntxt_id >= sc->sge.neq) 3475 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 3476 cntxt_id, sc->sge.neq - 1); 3477 sc->sge.eqmap[cntxt_id] = eq; 3478 3479 return (rc); 3480 } 3481 3482 #ifdef TCP_OFFLOAD 3483 static int 3484 ofld_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 3485 { 3486 int rc, cntxt_id; 3487 struct fw_eq_ofld_cmd c; 3488 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 3489 3490 bzero(&c, sizeof(c)); 3491 3492 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | F_FW_CMD_REQUEST | 3493 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_OFLD_CMD_PFN(sc->pf) | 3494 V_FW_EQ_OFLD_CMD_VFN(0)); 3495 c.alloc_to_len16 = htonl(F_FW_EQ_OFLD_CMD_ALLOC | 3496 F_FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c)); 3497 c.fetchszm_to_iqid = 3498 htonl(V_FW_EQ_OFLD_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) | 3499 V_FW_EQ_OFLD_CMD_PCIECHN(eq->tx_chan) | 3500 F_FW_EQ_OFLD_CMD_FETCHRO | V_FW_EQ_OFLD_CMD_IQID(eq->iqid)); 3501 c.dcaen_to_eqsize = 3502 htobe32(V_FW_EQ_OFLD_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 3503 V_FW_EQ_OFLD_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 3504 V_FW_EQ_OFLD_CMD_EQSIZE(qsize)); 3505 c.eqaddr = htobe64(eq->ba); 3506 3507 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3508 if (rc != 0) { 3509 device_printf(vi->dev, 3510 "failed to create egress queue for TCP offload: %d\n", rc); 3511 return (rc); 3512 } 3513 eq->flags |= EQ_ALLOCATED; 3514 3515 eq->cntxt_id = G_FW_EQ_OFLD_CMD_EQID(be32toh(c.eqid_pkd)); 3516 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 3517 if (cntxt_id >= sc->sge.neq) 3518 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 3519 cntxt_id, sc->sge.neq - 1); 3520 sc->sge.eqmap[cntxt_id] = eq; 3521 3522 return (rc); 3523 } 3524 #endif 3525 3526 static int 3527 alloc_eq(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 3528 { 3529 int rc, qsize; 3530 size_t len; 3531 3532 mtx_init(&eq->eq_lock, eq->lockname, NULL, MTX_DEF); 3533 3534 qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 3535 len = qsize * EQ_ESIZE; 3536 rc = alloc_ring(sc, len, &eq->desc_tag, &eq->desc_map, 3537 &eq->ba, (void **)&eq->desc); 3538 if (rc) 3539 return (rc); 3540 3541 eq->pidx = eq->cidx = 0; 3542 eq->equeqidx = eq->dbidx = 0; 3543 eq->doorbells = sc->doorbells; 3544 3545 switch (eq->flags & EQ_TYPEMASK) { 3546 case EQ_CTRL: 3547 rc = ctrl_eq_alloc(sc, eq); 3548 break; 3549 3550 case EQ_ETH: 3551 rc = eth_eq_alloc(sc, vi, eq); 3552 break; 3553 3554 #ifdef TCP_OFFLOAD 3555 case EQ_OFLD: 3556 rc = ofld_eq_alloc(sc, vi, eq); 3557 break; 3558 #endif 3559 3560 default: 3561 panic("%s: invalid eq type %d.", __func__, 3562 eq->flags & EQ_TYPEMASK); 3563 } 3564 if (rc != 0) { 3565 device_printf(sc->dev, 3566 "failed to allocate egress queue(%d): %d\n", 3567 eq->flags & EQ_TYPEMASK, rc); 3568 } 3569 3570 if (isset(&eq->doorbells, DOORBELL_UDB) || 3571 isset(&eq->doorbells, DOORBELL_UDBWC) || 3572 isset(&eq->doorbells, DOORBELL_WCWR)) { 3573 uint32_t s_qpp = sc->params.sge.eq_s_qpp; 3574 uint32_t mask = (1 << s_qpp) - 1; 3575 volatile uint8_t *udb; 3576 3577 udb = sc->udbs_base + UDBS_DB_OFFSET; 3578 udb += (eq->cntxt_id >> s_qpp) << PAGE_SHIFT; /* pg offset */ 3579 eq->udb_qid = eq->cntxt_id & mask; /* id in page */ 3580 if (eq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE) 3581 clrbit(&eq->doorbells, DOORBELL_WCWR); 3582 else { 3583 udb += eq->udb_qid << UDBS_SEG_SHIFT; /* seg offset */ 3584 eq->udb_qid = 0; 3585 } 3586 eq->udb = (volatile void *)udb; 3587 } 3588 3589 return (rc); 3590 } 3591 3592 static int 3593 free_eq(struct adapter *sc, struct sge_eq *eq) 3594 { 3595 int rc; 3596 3597 if (eq->flags & EQ_ALLOCATED) { 3598 switch (eq->flags & EQ_TYPEMASK) { 3599 case EQ_CTRL: 3600 rc = -t4_ctrl_eq_free(sc, sc->mbox, sc->pf, 0, 3601 eq->cntxt_id); 3602 break; 3603 3604 case EQ_ETH: 3605 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0, 3606 eq->cntxt_id); 3607 break; 3608 3609 #ifdef TCP_OFFLOAD 3610 case EQ_OFLD: 3611 rc = -t4_ofld_eq_free(sc, sc->mbox, sc->pf, 0, 3612 eq->cntxt_id); 3613 break; 3614 #endif 3615 3616 default: 3617 panic("%s: invalid eq type %d.", __func__, 3618 eq->flags & EQ_TYPEMASK); 3619 } 3620 if (rc != 0) { 3621 device_printf(sc->dev, 3622 "failed to free egress queue (%d): %d\n", 3623 eq->flags & EQ_TYPEMASK, rc); 3624 return (rc); 3625 } 3626 eq->flags &= ~EQ_ALLOCATED; 3627 } 3628 3629 free_ring(sc, eq->desc_tag, eq->desc_map, eq->ba, eq->desc); 3630 3631 if (mtx_initialized(&eq->eq_lock)) 3632 mtx_destroy(&eq->eq_lock); 3633 3634 bzero(eq, sizeof(*eq)); 3635 return (0); 3636 } 3637 3638 static int 3639 alloc_wrq(struct adapter *sc, struct vi_info *vi, struct sge_wrq *wrq, 3640 struct sysctl_oid *oid) 3641 { 3642 int rc; 3643 struct sysctl_ctx_list *ctx = vi ? &vi->ctx : &sc->ctx; 3644 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3645 3646 rc = alloc_eq(sc, vi, &wrq->eq); 3647 if (rc) 3648 return (rc); 3649 3650 wrq->adapter = sc; 3651 TASK_INIT(&wrq->wrq_tx_task, 0, wrq_tx_drain, wrq); 3652 TAILQ_INIT(&wrq->incomplete_wrs); 3653 STAILQ_INIT(&wrq->wr_list); 3654 wrq->nwr_pending = 0; 3655 wrq->ndesc_needed = 0; 3656 3657 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, 3658 &wrq->eq.ba, "bus address of descriptor ring"); 3659 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3660 wrq->eq.sidx * EQ_ESIZE + sc->params.sge.spg_len, 3661 "desc ring size in bytes"); 3662 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 3663 &wrq->eq.cntxt_id, 0, "SGE context id of the queue"); 3664 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx", 3665 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.cidx, 0, sysctl_uint16, "I", 3666 "consumer index"); 3667 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pidx", 3668 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.pidx, 0, sysctl_uint16, "I", 3669 "producer index"); 3670 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL, 3671 wrq->eq.sidx, "status page index"); 3672 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_direct", CTLFLAG_RD, 3673 &wrq->tx_wrs_direct, "# of work requests (direct)"); 3674 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_copied", CTLFLAG_RD, 3675 &wrq->tx_wrs_copied, "# of work requests (copied)"); 3676 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_sspace", CTLFLAG_RD, 3677 &wrq->tx_wrs_ss, "# of work requests (copied from scratch space)"); 3678 3679 return (rc); 3680 } 3681 3682 static int 3683 free_wrq(struct adapter *sc, struct sge_wrq *wrq) 3684 { 3685 int rc; 3686 3687 rc = free_eq(sc, &wrq->eq); 3688 if (rc) 3689 return (rc); 3690 3691 bzero(wrq, sizeof(*wrq)); 3692 return (0); 3693 } 3694 3695 static int 3696 alloc_txq(struct vi_info *vi, struct sge_txq *txq, int idx, 3697 struct sysctl_oid *oid) 3698 { 3699 int rc; 3700 struct port_info *pi = vi->pi; 3701 struct adapter *sc = pi->adapter; 3702 struct sge_eq *eq = &txq->eq; 3703 char name[16]; 3704 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3705 3706 rc = mp_ring_alloc(&txq->r, eq->sidx, txq, eth_tx, can_resume_eth_tx, 3707 M_CXGBE, M_WAITOK); 3708 if (rc != 0) { 3709 device_printf(sc->dev, "failed to allocate mp_ring: %d\n", rc); 3710 return (rc); 3711 } 3712 3713 rc = alloc_eq(sc, vi, eq); 3714 if (rc != 0) { 3715 mp_ring_free(txq->r); 3716 txq->r = NULL; 3717 return (rc); 3718 } 3719 3720 /* Can't fail after this point. */ 3721 3722 if (idx == 0) 3723 sc->sge.eq_base = eq->abs_id - eq->cntxt_id; 3724 else 3725 KASSERT(eq->cntxt_id + sc->sge.eq_base == eq->abs_id, 3726 ("eq_base mismatch")); 3727 KASSERT(sc->sge.eq_base == 0 || sc->flags & IS_VF, 3728 ("PF with non-zero eq_base")); 3729 3730 TASK_INIT(&txq->tx_reclaim_task, 0, tx_reclaim, eq); 3731 txq->ifp = vi->ifp; 3732 txq->gl = sglist_alloc(TX_SGL_SEGS, M_WAITOK); 3733 if (sc->flags & IS_VF) 3734 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) | 3735 V_TXPKT_INTF(pi->tx_chan)); 3736 else 3737 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) | 3738 V_TXPKT_INTF(pi->tx_chan) | 3739 V_TXPKT_PF(G_FW_VIID_PFN(vi->viid)) | 3740 V_TXPKT_VF(G_FW_VIID_VIN(vi->viid)) | 3741 V_TXPKT_VF_VLD(G_FW_VIID_VIVLD(vi->viid))); 3742 txq->tc_idx = -1; 3743 txq->sdesc = malloc(eq->sidx * sizeof(struct tx_sdesc), M_CXGBE, 3744 M_ZERO | M_WAITOK); 3745 3746 snprintf(name, sizeof(name), "%d", idx); 3747 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 3748 NULL, "tx queue"); 3749 children = SYSCTL_CHILDREN(oid); 3750 3751 SYSCTL_ADD_UAUTO(&vi->ctx, children, OID_AUTO, "ba", CTLFLAG_RD, 3752 &eq->ba, "bus address of descriptor ring"); 3753 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3754 eq->sidx * EQ_ESIZE + sc->params.sge.spg_len, 3755 "desc ring size in bytes"); 3756 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "abs_id", CTLFLAG_RD, 3757 &eq->abs_id, 0, "absolute id of the queue"); 3758 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 3759 &eq->cntxt_id, 0, "SGE context id of the queue"); 3760 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx", 3761 CTLTYPE_INT | CTLFLAG_RD, &eq->cidx, 0, sysctl_uint16, "I", 3762 "consumer index"); 3763 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "pidx", 3764 CTLTYPE_INT | CTLFLAG_RD, &eq->pidx, 0, sysctl_uint16, "I", 3765 "producer index"); 3766 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL, 3767 eq->sidx, "status page index"); 3768 3769 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "tc", 3770 CTLTYPE_INT | CTLFLAG_RW, vi, idx, sysctl_tc, "I", 3771 "traffic class (-1 means none)"); 3772 3773 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txcsum", CTLFLAG_RD, 3774 &txq->txcsum, "# of times hardware assisted with checksum"); 3775 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_insertion", 3776 CTLFLAG_RD, &txq->vlan_insertion, 3777 "# of times hardware inserted 802.1Q tag"); 3778 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "tso_wrs", CTLFLAG_RD, 3779 &txq->tso_wrs, "# of TSO work requests"); 3780 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "imm_wrs", CTLFLAG_RD, 3781 &txq->imm_wrs, "# of work requests with immediate data"); 3782 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "sgl_wrs", CTLFLAG_RD, 3783 &txq->sgl_wrs, "# of work requests with direct SGL"); 3784 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkt_wrs", CTLFLAG_RD, 3785 &txq->txpkt_wrs, "# of txpkt work requests (one pkt/WR)"); 3786 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_wrs", 3787 CTLFLAG_RD, &txq->txpkts0_wrs, 3788 "# of txpkts (type 0) work requests"); 3789 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_wrs", 3790 CTLFLAG_RD, &txq->txpkts1_wrs, 3791 "# of txpkts (type 1) work requests"); 3792 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_pkts", 3793 CTLFLAG_RD, &txq->txpkts0_pkts, 3794 "# of frames tx'd using type0 txpkts work requests"); 3795 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_pkts", 3796 CTLFLAG_RD, &txq->txpkts1_pkts, 3797 "# of frames tx'd using type1 txpkts work requests"); 3798 3799 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_enqueues", 3800 CTLFLAG_RD, &txq->r->enqueues, 3801 "# of enqueues to the mp_ring for this queue"); 3802 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_drops", 3803 CTLFLAG_RD, &txq->r->drops, 3804 "# of drops in the mp_ring for this queue"); 3805 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_starts", 3806 CTLFLAG_RD, &txq->r->starts, 3807 "# of normal consumer starts in the mp_ring for this queue"); 3808 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_stalls", 3809 CTLFLAG_RD, &txq->r->stalls, 3810 "# of consumer stalls in the mp_ring for this queue"); 3811 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_restarts", 3812 CTLFLAG_RD, &txq->r->restarts, 3813 "# of consumer restarts in the mp_ring for this queue"); 3814 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_abdications", 3815 CTLFLAG_RD, &txq->r->abdications, 3816 "# of consumer abdications in the mp_ring for this queue"); 3817 3818 return (0); 3819 } 3820 3821 static int 3822 free_txq(struct vi_info *vi, struct sge_txq *txq) 3823 { 3824 int rc; 3825 struct adapter *sc = vi->pi->adapter; 3826 struct sge_eq *eq = &txq->eq; 3827 3828 rc = free_eq(sc, eq); 3829 if (rc) 3830 return (rc); 3831 3832 sglist_free(txq->gl); 3833 free(txq->sdesc, M_CXGBE); 3834 mp_ring_free(txq->r); 3835 3836 bzero(txq, sizeof(*txq)); 3837 return (0); 3838 } 3839 3840 static void 3841 oneseg_dma_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3842 { 3843 bus_addr_t *ba = arg; 3844 3845 KASSERT(nseg == 1, 3846 ("%s meant for single segment mappings only.", __func__)); 3847 3848 *ba = error ? 0 : segs->ds_addr; 3849 } 3850 3851 static inline void 3852 ring_fl_db(struct adapter *sc, struct sge_fl *fl) 3853 { 3854 uint32_t n, v; 3855 3856 n = IDXDIFF(fl->pidx / 8, fl->dbidx, fl->sidx); 3857 MPASS(n > 0); 3858 3859 wmb(); 3860 v = fl->dbval | V_PIDX(n); 3861 if (fl->udb) 3862 *fl->udb = htole32(v); 3863 else 3864 t4_write_reg(sc, sc->sge_kdoorbell_reg, v); 3865 IDXINCR(fl->dbidx, n, fl->sidx); 3866 } 3867 3868 /* 3869 * Fills up the freelist by allocating up to 'n' buffers. Buffers that are 3870 * recycled do not count towards this allocation budget. 3871 * 3872 * Returns non-zero to indicate that this freelist should be added to the list 3873 * of starving freelists. 3874 */ 3875 static int 3876 refill_fl(struct adapter *sc, struct sge_fl *fl, int n) 3877 { 3878 __be64 *d; 3879 struct fl_sdesc *sd; 3880 uintptr_t pa; 3881 caddr_t cl; 3882 struct cluster_layout *cll; 3883 struct sw_zone_info *swz; 3884 struct cluster_metadata *clm; 3885 uint16_t max_pidx; 3886 uint16_t hw_cidx = fl->hw_cidx; /* stable snapshot */ 3887 3888 FL_LOCK_ASSERT_OWNED(fl); 3889 3890 /* 3891 * We always stop at the beginning of the hardware descriptor that's just 3892 * before the one with the hw cidx. This is to avoid hw pidx = hw cidx, 3893 * which would mean an empty freelist to the chip. 3894 */ 3895 max_pidx = __predict_false(hw_cidx == 0) ? fl->sidx - 1 : hw_cidx - 1; 3896 if (fl->pidx == max_pidx * 8) 3897 return (0); 3898 3899 d = &fl->desc[fl->pidx]; 3900 sd = &fl->sdesc[fl->pidx]; 3901 cll = &fl->cll_def; /* default layout */ 3902 swz = &sc->sge.sw_zone_info[cll->zidx]; 3903 3904 while (n > 0) { 3905 3906 if (sd->cl != NULL) { 3907 3908 if (sd->nmbuf == 0) { 3909 /* 3910 * Fast recycle without involving any atomics on 3911 * the cluster's metadata (if the cluster has 3912 * metadata). This happens when all frames 3913 * received in the cluster were small enough to 3914 * fit within a single mbuf each. 3915 */ 3916 fl->cl_fast_recycled++; 3917 #ifdef INVARIANTS 3918 clm = cl_metadata(sc, fl, &sd->cll, sd->cl); 3919 if (clm != NULL) 3920 MPASS(clm->refcount == 1); 3921 #endif 3922 goto recycled_fast; 3923 } 3924 3925 /* 3926 * Cluster is guaranteed to have metadata. Clusters 3927 * without metadata always take the fast recycle path 3928 * when they're recycled. 3929 */ 3930 clm = cl_metadata(sc, fl, &sd->cll, sd->cl); 3931 MPASS(clm != NULL); 3932 3933 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) { 3934 fl->cl_recycled++; 3935 counter_u64_add(extfree_rels, 1); 3936 goto recycled; 3937 } 3938 sd->cl = NULL; /* gave up my reference */ 3939 } 3940 MPASS(sd->cl == NULL); 3941 alloc: 3942 cl = uma_zalloc(swz->zone, M_NOWAIT); 3943 if (__predict_false(cl == NULL)) { 3944 if (cll == &fl->cll_alt || fl->cll_alt.zidx == -1 || 3945 fl->cll_def.zidx == fl->cll_alt.zidx) 3946 break; 3947 3948 /* fall back to the safe zone */ 3949 cll = &fl->cll_alt; 3950 swz = &sc->sge.sw_zone_info[cll->zidx]; 3951 goto alloc; 3952 } 3953 fl->cl_allocated++; 3954 n--; 3955 3956 pa = pmap_kextract((vm_offset_t)cl); 3957 pa += cll->region1; 3958 sd->cl = cl; 3959 sd->cll = *cll; 3960 *d = htobe64(pa | cll->hwidx); 3961 clm = cl_metadata(sc, fl, cll, cl); 3962 if (clm != NULL) { 3963 recycled: 3964 #ifdef INVARIANTS 3965 clm->sd = sd; 3966 #endif 3967 clm->refcount = 1; 3968 } 3969 sd->nmbuf = 0; 3970 recycled_fast: 3971 d++; 3972 sd++; 3973 if (__predict_false(++fl->pidx % 8 == 0)) { 3974 uint16_t pidx = fl->pidx / 8; 3975 3976 if (__predict_false(pidx == fl->sidx)) { 3977 fl->pidx = 0; 3978 pidx = 0; 3979 sd = fl->sdesc; 3980 d = fl->desc; 3981 } 3982 if (pidx == max_pidx) 3983 break; 3984 3985 if (IDXDIFF(pidx, fl->dbidx, fl->sidx) >= 4) 3986 ring_fl_db(sc, fl); 3987 } 3988 } 3989 3990 if (fl->pidx / 8 != fl->dbidx) 3991 ring_fl_db(sc, fl); 3992 3993 return (FL_RUNNING_LOW(fl) && !(fl->flags & FL_STARVING)); 3994 } 3995 3996 /* 3997 * Attempt to refill all starving freelists. 3998 */ 3999 static void 4000 refill_sfl(void *arg) 4001 { 4002 struct adapter *sc = arg; 4003 struct sge_fl *fl, *fl_temp; 4004 4005 mtx_assert(&sc->sfl_lock, MA_OWNED); 4006 TAILQ_FOREACH_SAFE(fl, &sc->sfl, link, fl_temp) { 4007 FL_LOCK(fl); 4008 refill_fl(sc, fl, 64); 4009 if (FL_NOT_RUNNING_LOW(fl) || fl->flags & FL_DOOMED) { 4010 TAILQ_REMOVE(&sc->sfl, fl, link); 4011 fl->flags &= ~FL_STARVING; 4012 } 4013 FL_UNLOCK(fl); 4014 } 4015 4016 if (!TAILQ_EMPTY(&sc->sfl)) 4017 callout_schedule(&sc->sfl_callout, hz / 5); 4018 } 4019 4020 static int 4021 alloc_fl_sdesc(struct sge_fl *fl) 4022 { 4023 4024 fl->sdesc = malloc(fl->sidx * 8 * sizeof(struct fl_sdesc), M_CXGBE, 4025 M_ZERO | M_WAITOK); 4026 4027 return (0); 4028 } 4029 4030 static void 4031 free_fl_sdesc(struct adapter *sc, struct sge_fl *fl) 4032 { 4033 struct fl_sdesc *sd; 4034 struct cluster_metadata *clm; 4035 struct cluster_layout *cll; 4036 int i; 4037 4038 sd = fl->sdesc; 4039 for (i = 0; i < fl->sidx * 8; i++, sd++) { 4040 if (sd->cl == NULL) 4041 continue; 4042 4043 cll = &sd->cll; 4044 clm = cl_metadata(sc, fl, cll, sd->cl); 4045 if (sd->nmbuf == 0) 4046 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl); 4047 else if (clm && atomic_fetchadd_int(&clm->refcount, -1) == 1) { 4048 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl); 4049 counter_u64_add(extfree_rels, 1); 4050 } 4051 sd->cl = NULL; 4052 } 4053 4054 free(fl->sdesc, M_CXGBE); 4055 fl->sdesc = NULL; 4056 } 4057 4058 static inline void 4059 get_pkt_gl(struct mbuf *m, struct sglist *gl) 4060 { 4061 int rc; 4062 4063 M_ASSERTPKTHDR(m); 4064 4065 sglist_reset(gl); 4066 rc = sglist_append_mbuf(gl, m); 4067 if (__predict_false(rc != 0)) { 4068 panic("%s: mbuf %p (%d segs) was vetted earlier but now fails " 4069 "with %d.", __func__, m, mbuf_nsegs(m), rc); 4070 } 4071 4072 KASSERT(gl->sg_nseg == mbuf_nsegs(m), 4073 ("%s: nsegs changed for mbuf %p from %d to %d", __func__, m, 4074 mbuf_nsegs(m), gl->sg_nseg)); 4075 KASSERT(gl->sg_nseg > 0 && 4076 gl->sg_nseg <= (needs_tso(m) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS), 4077 ("%s: %d segments, should have been 1 <= nsegs <= %d", __func__, 4078 gl->sg_nseg, needs_tso(m) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS)); 4079 } 4080 4081 /* 4082 * len16 for a txpkt WR with a GL. Includes the firmware work request header. 4083 */ 4084 static inline u_int 4085 txpkt_len16(u_int nsegs, u_int tso) 4086 { 4087 u_int n; 4088 4089 MPASS(nsegs > 0); 4090 4091 nsegs--; /* first segment is part of ulptx_sgl */ 4092 n = sizeof(struct fw_eth_tx_pkt_wr) + sizeof(struct cpl_tx_pkt_core) + 4093 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 4094 if (tso) 4095 n += sizeof(struct cpl_tx_pkt_lso_core); 4096 4097 return (howmany(n, 16)); 4098 } 4099 4100 /* 4101 * len16 for a txpkt_vm WR with a GL. Includes the firmware work 4102 * request header. 4103 */ 4104 static inline u_int 4105 txpkt_vm_len16(u_int nsegs, u_int tso) 4106 { 4107 u_int n; 4108 4109 MPASS(nsegs > 0); 4110 4111 nsegs--; /* first segment is part of ulptx_sgl */ 4112 n = sizeof(struct fw_eth_tx_pkt_vm_wr) + 4113 sizeof(struct cpl_tx_pkt_core) + 4114 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 4115 if (tso) 4116 n += sizeof(struct cpl_tx_pkt_lso_core); 4117 4118 return (howmany(n, 16)); 4119 } 4120 4121 /* 4122 * len16 for a txpkts type 0 WR with a GL. Does not include the firmware work 4123 * request header. 4124 */ 4125 static inline u_int 4126 txpkts0_len16(u_int nsegs) 4127 { 4128 u_int n; 4129 4130 MPASS(nsegs > 0); 4131 4132 nsegs--; /* first segment is part of ulptx_sgl */ 4133 n = sizeof(struct ulp_txpkt) + sizeof(struct ulptx_idata) + 4134 sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl) + 4135 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 4136 4137 return (howmany(n, 16)); 4138 } 4139 4140 /* 4141 * len16 for a txpkts type 1 WR with a GL. Does not include the firmware work 4142 * request header. 4143 */ 4144 static inline u_int 4145 txpkts1_len16(void) 4146 { 4147 u_int n; 4148 4149 n = sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl); 4150 4151 return (howmany(n, 16)); 4152 } 4153 4154 static inline u_int 4155 imm_payload(u_int ndesc) 4156 { 4157 u_int n; 4158 4159 n = ndesc * EQ_ESIZE - sizeof(struct fw_eth_tx_pkt_wr) - 4160 sizeof(struct cpl_tx_pkt_core); 4161 4162 return (n); 4163 } 4164 4165 /* 4166 * Write a VM txpkt WR for this packet to the hardware descriptors, update the 4167 * software descriptor, and advance the pidx. It is guaranteed that enough 4168 * descriptors are available. 4169 * 4170 * The return value is the # of hardware descriptors used. 4171 */ 4172 static u_int 4173 write_txpkt_vm_wr(struct adapter *sc, struct sge_txq *txq, 4174 struct fw_eth_tx_pkt_vm_wr *wr, struct mbuf *m0, u_int available) 4175 { 4176 struct sge_eq *eq = &txq->eq; 4177 struct tx_sdesc *txsd; 4178 struct cpl_tx_pkt_core *cpl; 4179 uint32_t ctrl; /* used in many unrelated places */ 4180 uint64_t ctrl1; 4181 int csum_type, len16, ndesc, pktlen, nsegs; 4182 caddr_t dst; 4183 4184 TXQ_LOCK_ASSERT_OWNED(txq); 4185 M_ASSERTPKTHDR(m0); 4186 MPASS(available > 0 && available < eq->sidx); 4187 4188 len16 = mbuf_len16(m0); 4189 nsegs = mbuf_nsegs(m0); 4190 pktlen = m0->m_pkthdr.len; 4191 ctrl = sizeof(struct cpl_tx_pkt_core); 4192 if (needs_tso(m0)) 4193 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 4194 ndesc = howmany(len16, EQ_ESIZE / 16); 4195 MPASS(ndesc <= available); 4196 4197 /* Firmware work request header */ 4198 MPASS(wr == (void *)&eq->desc[eq->pidx]); 4199 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_VM_WR) | 4200 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl)); 4201 4202 ctrl = V_FW_WR_LEN16(len16); 4203 wr->equiq_to_len16 = htobe32(ctrl); 4204 wr->r3[0] = 0; 4205 wr->r3[1] = 0; 4206 4207 /* 4208 * Copy over ethmacdst, ethmacsrc, ethtype, and vlantci. 4209 * vlantci is ignored unless the ethtype is 0x8100, so it's 4210 * simpler to always copy it rather than making it 4211 * conditional. Also, it seems that we do not have to set 4212 * vlantci or fake the ethtype when doing VLAN tag insertion. 4213 */ 4214 m_copydata(m0, 0, sizeof(struct ether_header) + 2, wr->ethmacdst); 4215 4216 csum_type = -1; 4217 if (needs_tso(m0)) { 4218 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1); 4219 4220 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 4221 m0->m_pkthdr.l4hlen > 0, 4222 ("%s: mbuf %p needs TSO but missing header lengths", 4223 __func__, m0)); 4224 4225 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE | 4226 F_LSO_LAST_SLICE | V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) 4227 | V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2); 4228 if (m0->m_pkthdr.l2hlen == sizeof(struct ether_vlan_header)) 4229 ctrl |= V_LSO_ETHHDR_LEN(1); 4230 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 4231 ctrl |= F_LSO_IPV6; 4232 4233 lso->lso_ctrl = htobe32(ctrl); 4234 lso->ipid_ofst = htobe16(0); 4235 lso->mss = htobe16(m0->m_pkthdr.tso_segsz); 4236 lso->seqno_offset = htobe32(0); 4237 lso->len = htobe32(pktlen); 4238 4239 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 4240 csum_type = TX_CSUM_TCPIP6; 4241 else 4242 csum_type = TX_CSUM_TCPIP; 4243 4244 cpl = (void *)(lso + 1); 4245 4246 txq->tso_wrs++; 4247 } else { 4248 if (m0->m_pkthdr.csum_flags & CSUM_IP_TCP) 4249 csum_type = TX_CSUM_TCPIP; 4250 else if (m0->m_pkthdr.csum_flags & CSUM_IP_UDP) 4251 csum_type = TX_CSUM_UDPIP; 4252 else if (m0->m_pkthdr.csum_flags & CSUM_IP6_TCP) 4253 csum_type = TX_CSUM_TCPIP6; 4254 else if (m0->m_pkthdr.csum_flags & CSUM_IP6_UDP) 4255 csum_type = TX_CSUM_UDPIP6; 4256 #if defined(INET) 4257 else if (m0->m_pkthdr.csum_flags & CSUM_IP) { 4258 /* 4259 * XXX: The firmware appears to stomp on the 4260 * fragment/flags field of the IP header when 4261 * using TX_CSUM_IP. Fall back to doing 4262 * software checksums. 4263 */ 4264 u_short *sump; 4265 struct mbuf *m; 4266 int offset; 4267 4268 m = m0; 4269 offset = 0; 4270 sump = m_advance(&m, &offset, m0->m_pkthdr.l2hlen + 4271 offsetof(struct ip, ip_sum)); 4272 *sump = in_cksum_skip(m0, m0->m_pkthdr.l2hlen + 4273 m0->m_pkthdr.l3hlen, m0->m_pkthdr.l2hlen); 4274 m0->m_pkthdr.csum_flags &= ~CSUM_IP; 4275 } 4276 #endif 4277 4278 cpl = (void *)(wr + 1); 4279 } 4280 4281 /* Checksum offload */ 4282 ctrl1 = 0; 4283 if (needs_l3_csum(m0) == 0) 4284 ctrl1 |= F_TXPKT_IPCSUM_DIS; 4285 if (csum_type >= 0) { 4286 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0, 4287 ("%s: mbuf %p needs checksum offload but missing header lengths", 4288 __func__, m0)); 4289 4290 if (chip_id(sc) <= CHELSIO_T5) { 4291 ctrl1 |= V_TXPKT_ETHHDR_LEN(m0->m_pkthdr.l2hlen - 4292 ETHER_HDR_LEN); 4293 } else { 4294 ctrl1 |= V_T6_TXPKT_ETHHDR_LEN(m0->m_pkthdr.l2hlen - 4295 ETHER_HDR_LEN); 4296 } 4297 ctrl1 |= V_TXPKT_IPHDR_LEN(m0->m_pkthdr.l3hlen); 4298 ctrl1 |= V_TXPKT_CSUM_TYPE(csum_type); 4299 } else 4300 ctrl1 |= F_TXPKT_L4CSUM_DIS; 4301 if (m0->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | 4302 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO)) 4303 txq->txcsum++; /* some hardware assistance provided */ 4304 4305 /* VLAN tag insertion */ 4306 if (needs_vlan_insertion(m0)) { 4307 ctrl1 |= F_TXPKT_VLAN_VLD | 4308 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 4309 txq->vlan_insertion++; 4310 } 4311 4312 /* CPL header */ 4313 cpl->ctrl0 = txq->cpl_ctrl0; 4314 cpl->pack = 0; 4315 cpl->len = htobe16(pktlen); 4316 cpl->ctrl1 = htobe64(ctrl1); 4317 4318 /* SGL */ 4319 dst = (void *)(cpl + 1); 4320 4321 /* 4322 * A packet using TSO will use up an entire descriptor for the 4323 * firmware work request header, LSO CPL, and TX_PKT_XT CPL. 4324 * If this descriptor is the last descriptor in the ring, wrap 4325 * around to the front of the ring explicitly for the start of 4326 * the sgl. 4327 */ 4328 if (dst == (void *)&eq->desc[eq->sidx]) { 4329 dst = (void *)&eq->desc[0]; 4330 write_gl_to_txd(txq, m0, &dst, 0); 4331 } else 4332 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx); 4333 txq->sgl_wrs++; 4334 4335 txq->txpkt_wrs++; 4336 4337 txsd = &txq->sdesc[eq->pidx]; 4338 txsd->m = m0; 4339 txsd->desc_used = ndesc; 4340 4341 return (ndesc); 4342 } 4343 4344 /* 4345 * Write a txpkt WR for this packet to the hardware descriptors, update the 4346 * software descriptor, and advance the pidx. It is guaranteed that enough 4347 * descriptors are available. 4348 * 4349 * The return value is the # of hardware descriptors used. 4350 */ 4351 static u_int 4352 write_txpkt_wr(struct sge_txq *txq, struct fw_eth_tx_pkt_wr *wr, 4353 struct mbuf *m0, u_int available) 4354 { 4355 struct sge_eq *eq = &txq->eq; 4356 struct tx_sdesc *txsd; 4357 struct cpl_tx_pkt_core *cpl; 4358 uint32_t ctrl; /* used in many unrelated places */ 4359 uint64_t ctrl1; 4360 int len16, ndesc, pktlen, nsegs; 4361 caddr_t dst; 4362 4363 TXQ_LOCK_ASSERT_OWNED(txq); 4364 M_ASSERTPKTHDR(m0); 4365 MPASS(available > 0 && available < eq->sidx); 4366 4367 len16 = mbuf_len16(m0); 4368 nsegs = mbuf_nsegs(m0); 4369 pktlen = m0->m_pkthdr.len; 4370 ctrl = sizeof(struct cpl_tx_pkt_core); 4371 if (needs_tso(m0)) 4372 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 4373 else if (pktlen <= imm_payload(2) && available >= 2) { 4374 /* Immediate data. Recalculate len16 and set nsegs to 0. */ 4375 ctrl += pktlen; 4376 len16 = howmany(sizeof(struct fw_eth_tx_pkt_wr) + 4377 sizeof(struct cpl_tx_pkt_core) + pktlen, 16); 4378 nsegs = 0; 4379 } 4380 ndesc = howmany(len16, EQ_ESIZE / 16); 4381 MPASS(ndesc <= available); 4382 4383 /* Firmware work request header */ 4384 MPASS(wr == (void *)&eq->desc[eq->pidx]); 4385 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_WR) | 4386 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl)); 4387 4388 ctrl = V_FW_WR_LEN16(len16); 4389 wr->equiq_to_len16 = htobe32(ctrl); 4390 wr->r3 = 0; 4391 4392 if (needs_tso(m0)) { 4393 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1); 4394 4395 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 4396 m0->m_pkthdr.l4hlen > 0, 4397 ("%s: mbuf %p needs TSO but missing header lengths", 4398 __func__, m0)); 4399 4400 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE | 4401 F_LSO_LAST_SLICE | V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) 4402 | V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2); 4403 if (m0->m_pkthdr.l2hlen == sizeof(struct ether_vlan_header)) 4404 ctrl |= V_LSO_ETHHDR_LEN(1); 4405 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 4406 ctrl |= F_LSO_IPV6; 4407 4408 lso->lso_ctrl = htobe32(ctrl); 4409 lso->ipid_ofst = htobe16(0); 4410 lso->mss = htobe16(m0->m_pkthdr.tso_segsz); 4411 lso->seqno_offset = htobe32(0); 4412 lso->len = htobe32(pktlen); 4413 4414 cpl = (void *)(lso + 1); 4415 4416 txq->tso_wrs++; 4417 } else 4418 cpl = (void *)(wr + 1); 4419 4420 /* Checksum offload */ 4421 ctrl1 = 0; 4422 if (needs_l3_csum(m0) == 0) 4423 ctrl1 |= F_TXPKT_IPCSUM_DIS; 4424 if (needs_l4_csum(m0) == 0) 4425 ctrl1 |= F_TXPKT_L4CSUM_DIS; 4426 if (m0->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | 4427 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO)) 4428 txq->txcsum++; /* some hardware assistance provided */ 4429 4430 /* VLAN tag insertion */ 4431 if (needs_vlan_insertion(m0)) { 4432 ctrl1 |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 4433 txq->vlan_insertion++; 4434 } 4435 4436 /* CPL header */ 4437 cpl->ctrl0 = txq->cpl_ctrl0; 4438 cpl->pack = 0; 4439 cpl->len = htobe16(pktlen); 4440 cpl->ctrl1 = htobe64(ctrl1); 4441 4442 /* SGL */ 4443 dst = (void *)(cpl + 1); 4444 if (nsegs > 0) { 4445 4446 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx); 4447 txq->sgl_wrs++; 4448 } else { 4449 struct mbuf *m; 4450 4451 for (m = m0; m != NULL; m = m->m_next) { 4452 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len); 4453 #ifdef INVARIANTS 4454 pktlen -= m->m_len; 4455 #endif 4456 } 4457 #ifdef INVARIANTS 4458 KASSERT(pktlen == 0, ("%s: %d bytes left.", __func__, pktlen)); 4459 #endif 4460 txq->imm_wrs++; 4461 } 4462 4463 txq->txpkt_wrs++; 4464 4465 txsd = &txq->sdesc[eq->pidx]; 4466 txsd->m = m0; 4467 txsd->desc_used = ndesc; 4468 4469 return (ndesc); 4470 } 4471 4472 static int 4473 try_txpkts(struct mbuf *m, struct mbuf *n, struct txpkts *txp, u_int available) 4474 { 4475 u_int needed, nsegs1, nsegs2, l1, l2; 4476 4477 if (cannot_use_txpkts(m) || cannot_use_txpkts(n)) 4478 return (1); 4479 4480 nsegs1 = mbuf_nsegs(m); 4481 nsegs2 = mbuf_nsegs(n); 4482 if (nsegs1 + nsegs2 == 2) { 4483 txp->wr_type = 1; 4484 l1 = l2 = txpkts1_len16(); 4485 } else { 4486 txp->wr_type = 0; 4487 l1 = txpkts0_len16(nsegs1); 4488 l2 = txpkts0_len16(nsegs2); 4489 } 4490 txp->len16 = howmany(sizeof(struct fw_eth_tx_pkts_wr), 16) + l1 + l2; 4491 needed = howmany(txp->len16, EQ_ESIZE / 16); 4492 if (needed > SGE_MAX_WR_NDESC || needed > available) 4493 return (1); 4494 4495 txp->plen = m->m_pkthdr.len + n->m_pkthdr.len; 4496 if (txp->plen > 65535) 4497 return (1); 4498 4499 txp->npkt = 2; 4500 set_mbuf_len16(m, l1); 4501 set_mbuf_len16(n, l2); 4502 4503 return (0); 4504 } 4505 4506 static int 4507 add_to_txpkts(struct mbuf *m, struct txpkts *txp, u_int available) 4508 { 4509 u_int plen, len16, needed, nsegs; 4510 4511 MPASS(txp->wr_type == 0 || txp->wr_type == 1); 4512 4513 nsegs = mbuf_nsegs(m); 4514 if (needs_tso(m) || (txp->wr_type == 1 && nsegs != 1)) 4515 return (1); 4516 4517 plen = txp->plen + m->m_pkthdr.len; 4518 if (plen > 65535) 4519 return (1); 4520 4521 if (txp->wr_type == 0) 4522 len16 = txpkts0_len16(nsegs); 4523 else 4524 len16 = txpkts1_len16(); 4525 needed = howmany(txp->len16 + len16, EQ_ESIZE / 16); 4526 if (needed > SGE_MAX_WR_NDESC || needed > available) 4527 return (1); 4528 4529 txp->npkt++; 4530 txp->plen = plen; 4531 txp->len16 += len16; 4532 set_mbuf_len16(m, len16); 4533 4534 return (0); 4535 } 4536 4537 /* 4538 * Write a txpkts WR for the packets in txp to the hardware descriptors, update 4539 * the software descriptor, and advance the pidx. It is guaranteed that enough 4540 * descriptors are available. 4541 * 4542 * The return value is the # of hardware descriptors used. 4543 */ 4544 static u_int 4545 write_txpkts_wr(struct sge_txq *txq, struct fw_eth_tx_pkts_wr *wr, 4546 struct mbuf *m0, const struct txpkts *txp, u_int available) 4547 { 4548 struct sge_eq *eq = &txq->eq; 4549 struct tx_sdesc *txsd; 4550 struct cpl_tx_pkt_core *cpl; 4551 uint32_t ctrl; 4552 uint64_t ctrl1; 4553 int ndesc, checkwrap; 4554 struct mbuf *m; 4555 void *flitp; 4556 4557 TXQ_LOCK_ASSERT_OWNED(txq); 4558 MPASS(txp->npkt > 0); 4559 MPASS(txp->plen < 65536); 4560 MPASS(m0 != NULL); 4561 MPASS(m0->m_nextpkt != NULL); 4562 MPASS(txp->len16 <= howmany(SGE_MAX_WR_LEN, 16)); 4563 MPASS(available > 0 && available < eq->sidx); 4564 4565 ndesc = howmany(txp->len16, EQ_ESIZE / 16); 4566 MPASS(ndesc <= available); 4567 4568 MPASS(wr == (void *)&eq->desc[eq->pidx]); 4569 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR)); 4570 ctrl = V_FW_WR_LEN16(txp->len16); 4571 wr->equiq_to_len16 = htobe32(ctrl); 4572 wr->plen = htobe16(txp->plen); 4573 wr->npkt = txp->npkt; 4574 wr->r3 = 0; 4575 wr->type = txp->wr_type; 4576 flitp = wr + 1; 4577 4578 /* 4579 * At this point we are 16B into a hardware descriptor. If checkwrap is 4580 * set then we know the WR is going to wrap around somewhere. We'll 4581 * check for that at appropriate points. 4582 */ 4583 checkwrap = eq->sidx - ndesc < eq->pidx; 4584 for (m = m0; m != NULL; m = m->m_nextpkt) { 4585 if (txp->wr_type == 0) { 4586 struct ulp_txpkt *ulpmc; 4587 struct ulptx_idata *ulpsc; 4588 4589 /* ULP master command */ 4590 ulpmc = flitp; 4591 ulpmc->cmd_dest = htobe32(V_ULPTX_CMD(ULP_TX_PKT) | 4592 V_ULP_TXPKT_DEST(0) | V_ULP_TXPKT_FID(eq->iqid)); 4593 ulpmc->len = htobe32(mbuf_len16(m)); 4594 4595 /* ULP subcommand */ 4596 ulpsc = (void *)(ulpmc + 1); 4597 ulpsc->cmd_more = htobe32(V_ULPTX_CMD(ULP_TX_SC_IMM) | 4598 F_ULP_TX_SC_MORE); 4599 ulpsc->len = htobe32(sizeof(struct cpl_tx_pkt_core)); 4600 4601 cpl = (void *)(ulpsc + 1); 4602 if (checkwrap && 4603 (uintptr_t)cpl == (uintptr_t)&eq->desc[eq->sidx]) 4604 cpl = (void *)&eq->desc[0]; 4605 } else { 4606 cpl = flitp; 4607 } 4608 4609 /* Checksum offload */ 4610 ctrl1 = 0; 4611 if (needs_l3_csum(m) == 0) 4612 ctrl1 |= F_TXPKT_IPCSUM_DIS; 4613 if (needs_l4_csum(m) == 0) 4614 ctrl1 |= F_TXPKT_L4CSUM_DIS; 4615 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | 4616 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO)) 4617 txq->txcsum++; /* some hardware assistance provided */ 4618 4619 /* VLAN tag insertion */ 4620 if (needs_vlan_insertion(m)) { 4621 ctrl1 |= F_TXPKT_VLAN_VLD | 4622 V_TXPKT_VLAN(m->m_pkthdr.ether_vtag); 4623 txq->vlan_insertion++; 4624 } 4625 4626 /* CPL header */ 4627 cpl->ctrl0 = txq->cpl_ctrl0; 4628 cpl->pack = 0; 4629 cpl->len = htobe16(m->m_pkthdr.len); 4630 cpl->ctrl1 = htobe64(ctrl1); 4631 4632 flitp = cpl + 1; 4633 if (checkwrap && 4634 (uintptr_t)flitp == (uintptr_t)&eq->desc[eq->sidx]) 4635 flitp = (void *)&eq->desc[0]; 4636 4637 write_gl_to_txd(txq, m, (caddr_t *)(&flitp), checkwrap); 4638 4639 } 4640 4641 if (txp->wr_type == 0) { 4642 txq->txpkts0_pkts += txp->npkt; 4643 txq->txpkts0_wrs++; 4644 } else { 4645 txq->txpkts1_pkts += txp->npkt; 4646 txq->txpkts1_wrs++; 4647 } 4648 4649 txsd = &txq->sdesc[eq->pidx]; 4650 txsd->m = m0; 4651 txsd->desc_used = ndesc; 4652 4653 return (ndesc); 4654 } 4655 4656 /* 4657 * If the SGL ends on an address that is not 16 byte aligned, this function will 4658 * add a 0 filled flit at the end. 4659 */ 4660 static void 4661 write_gl_to_txd(struct sge_txq *txq, struct mbuf *m, caddr_t *to, int checkwrap) 4662 { 4663 struct sge_eq *eq = &txq->eq; 4664 struct sglist *gl = txq->gl; 4665 struct sglist_seg *seg; 4666 __be64 *flitp, *wrap; 4667 struct ulptx_sgl *usgl; 4668 int i, nflits, nsegs; 4669 4670 KASSERT(((uintptr_t)(*to) & 0xf) == 0, 4671 ("%s: SGL must start at a 16 byte boundary: %p", __func__, *to)); 4672 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]); 4673 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]); 4674 4675 get_pkt_gl(m, gl); 4676 nsegs = gl->sg_nseg; 4677 MPASS(nsegs > 0); 4678 4679 nflits = (3 * (nsegs - 1)) / 2 + ((nsegs - 1) & 1) + 2; 4680 flitp = (__be64 *)(*to); 4681 wrap = (__be64 *)(&eq->desc[eq->sidx]); 4682 seg = &gl->sg_segs[0]; 4683 usgl = (void *)flitp; 4684 4685 /* 4686 * We start at a 16 byte boundary somewhere inside the tx descriptor 4687 * ring, so we're at least 16 bytes away from the status page. There is 4688 * no chance of a wrap around in the middle of usgl (which is 16 bytes). 4689 */ 4690 4691 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 4692 V_ULPTX_NSGE(nsegs)); 4693 usgl->len0 = htobe32(seg->ss_len); 4694 usgl->addr0 = htobe64(seg->ss_paddr); 4695 seg++; 4696 4697 if (checkwrap == 0 || (uintptr_t)(flitp + nflits) <= (uintptr_t)wrap) { 4698 4699 /* Won't wrap around at all */ 4700 4701 for (i = 0; i < nsegs - 1; i++, seg++) { 4702 usgl->sge[i / 2].len[i & 1] = htobe32(seg->ss_len); 4703 usgl->sge[i / 2].addr[i & 1] = htobe64(seg->ss_paddr); 4704 } 4705 if (i & 1) 4706 usgl->sge[i / 2].len[1] = htobe32(0); 4707 flitp += nflits; 4708 } else { 4709 4710 /* Will wrap somewhere in the rest of the SGL */ 4711 4712 /* 2 flits already written, write the rest flit by flit */ 4713 flitp = (void *)(usgl + 1); 4714 for (i = 0; i < nflits - 2; i++) { 4715 if (flitp == wrap) 4716 flitp = (void *)eq->desc; 4717 *flitp++ = get_flit(seg, nsegs - 1, i); 4718 } 4719 } 4720 4721 if (nflits & 1) { 4722 MPASS(((uintptr_t)flitp) & 0xf); 4723 *flitp++ = 0; 4724 } 4725 4726 MPASS((((uintptr_t)flitp) & 0xf) == 0); 4727 if (__predict_false(flitp == wrap)) 4728 *to = (void *)eq->desc; 4729 else 4730 *to = (void *)flitp; 4731 } 4732 4733 static inline void 4734 copy_to_txd(struct sge_eq *eq, caddr_t from, caddr_t *to, int len) 4735 { 4736 4737 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]); 4738 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]); 4739 4740 if (__predict_true((uintptr_t)(*to) + len <= 4741 (uintptr_t)&eq->desc[eq->sidx])) { 4742 bcopy(from, *to, len); 4743 (*to) += len; 4744 } else { 4745 int portion = (uintptr_t)&eq->desc[eq->sidx] - (uintptr_t)(*to); 4746 4747 bcopy(from, *to, portion); 4748 from += portion; 4749 portion = len - portion; /* remaining */ 4750 bcopy(from, (void *)eq->desc, portion); 4751 (*to) = (caddr_t)eq->desc + portion; 4752 } 4753 } 4754 4755 static inline void 4756 ring_eq_db(struct adapter *sc, struct sge_eq *eq, u_int n) 4757 { 4758 u_int db; 4759 4760 MPASS(n > 0); 4761 4762 db = eq->doorbells; 4763 if (n > 1) 4764 clrbit(&db, DOORBELL_WCWR); 4765 wmb(); 4766 4767 switch (ffs(db) - 1) { 4768 case DOORBELL_UDB: 4769 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n)); 4770 break; 4771 4772 case DOORBELL_WCWR: { 4773 volatile uint64_t *dst, *src; 4774 int i; 4775 4776 /* 4777 * Queues whose 128B doorbell segment fits in the page do not 4778 * use relative qid (udb_qid is always 0). Only queues with 4779 * doorbell segments can do WCWR. 4780 */ 4781 KASSERT(eq->udb_qid == 0 && n == 1, 4782 ("%s: inappropriate doorbell (0x%x, %d, %d) for eq %p", 4783 __func__, eq->doorbells, n, eq->dbidx, eq)); 4784 4785 dst = (volatile void *)((uintptr_t)eq->udb + UDBS_WR_OFFSET - 4786 UDBS_DB_OFFSET); 4787 i = eq->dbidx; 4788 src = (void *)&eq->desc[i]; 4789 while (src != (void *)&eq->desc[i + 1]) 4790 *dst++ = *src++; 4791 wmb(); 4792 break; 4793 } 4794 4795 case DOORBELL_UDBWC: 4796 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n)); 4797 wmb(); 4798 break; 4799 4800 case DOORBELL_KDB: 4801 t4_write_reg(sc, sc->sge_kdoorbell_reg, 4802 V_QID(eq->cntxt_id) | V_PIDX(n)); 4803 break; 4804 } 4805 4806 IDXINCR(eq->dbidx, n, eq->sidx); 4807 } 4808 4809 static inline u_int 4810 reclaimable_tx_desc(struct sge_eq *eq) 4811 { 4812 uint16_t hw_cidx; 4813 4814 hw_cidx = read_hw_cidx(eq); 4815 return (IDXDIFF(hw_cidx, eq->cidx, eq->sidx)); 4816 } 4817 4818 static inline u_int 4819 total_available_tx_desc(struct sge_eq *eq) 4820 { 4821 uint16_t hw_cidx, pidx; 4822 4823 hw_cidx = read_hw_cidx(eq); 4824 pidx = eq->pidx; 4825 4826 if (pidx == hw_cidx) 4827 return (eq->sidx - 1); 4828 else 4829 return (IDXDIFF(hw_cidx, pidx, eq->sidx) - 1); 4830 } 4831 4832 static inline uint16_t 4833 read_hw_cidx(struct sge_eq *eq) 4834 { 4835 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx]; 4836 uint16_t cidx = spg->cidx; /* stable snapshot */ 4837 4838 return (be16toh(cidx)); 4839 } 4840 4841 /* 4842 * Reclaim 'n' descriptors approximately. 4843 */ 4844 static u_int 4845 reclaim_tx_descs(struct sge_txq *txq, u_int n) 4846 { 4847 struct tx_sdesc *txsd; 4848 struct sge_eq *eq = &txq->eq; 4849 u_int can_reclaim, reclaimed; 4850 4851 TXQ_LOCK_ASSERT_OWNED(txq); 4852 MPASS(n > 0); 4853 4854 reclaimed = 0; 4855 can_reclaim = reclaimable_tx_desc(eq); 4856 while (can_reclaim && reclaimed < n) { 4857 int ndesc; 4858 struct mbuf *m, *nextpkt; 4859 4860 txsd = &txq->sdesc[eq->cidx]; 4861 ndesc = txsd->desc_used; 4862 4863 /* Firmware doesn't return "partial" credits. */ 4864 KASSERT(can_reclaim >= ndesc, 4865 ("%s: unexpected number of credits: %d, %d", 4866 __func__, can_reclaim, ndesc)); 4867 4868 for (m = txsd->m; m != NULL; m = nextpkt) { 4869 nextpkt = m->m_nextpkt; 4870 m->m_nextpkt = NULL; 4871 m_freem(m); 4872 } 4873 reclaimed += ndesc; 4874 can_reclaim -= ndesc; 4875 IDXINCR(eq->cidx, ndesc, eq->sidx); 4876 } 4877 4878 return (reclaimed); 4879 } 4880 4881 static void 4882 tx_reclaim(void *arg, int n) 4883 { 4884 struct sge_txq *txq = arg; 4885 struct sge_eq *eq = &txq->eq; 4886 4887 do { 4888 if (TXQ_TRYLOCK(txq) == 0) 4889 break; 4890 n = reclaim_tx_descs(txq, 32); 4891 if (eq->cidx == eq->pidx) 4892 eq->equeqidx = eq->pidx; 4893 TXQ_UNLOCK(txq); 4894 } while (n > 0); 4895 } 4896 4897 static __be64 4898 get_flit(struct sglist_seg *segs, int nsegs, int idx) 4899 { 4900 int i = (idx / 3) * 2; 4901 4902 switch (idx % 3) { 4903 case 0: { 4904 __be64 rc; 4905 4906 rc = htobe32(segs[i].ss_len); 4907 if (i + 1 < nsegs) 4908 rc |= (uint64_t)htobe32(segs[i + 1].ss_len) << 32; 4909 4910 return (rc); 4911 } 4912 case 1: 4913 return (htobe64(segs[i].ss_paddr)); 4914 case 2: 4915 return (htobe64(segs[i + 1].ss_paddr)); 4916 } 4917 4918 return (0); 4919 } 4920 4921 static void 4922 find_best_refill_source(struct adapter *sc, struct sge_fl *fl, int maxp) 4923 { 4924 int8_t zidx, hwidx, idx; 4925 uint16_t region1, region3; 4926 int spare, spare_needed, n; 4927 struct sw_zone_info *swz; 4928 struct hw_buf_info *hwb, *hwb_list = &sc->sge.hw_buf_info[0]; 4929 4930 /* 4931 * Buffer Packing: Look for PAGE_SIZE or larger zone which has a bufsize 4932 * large enough for the max payload and cluster metadata. Otherwise 4933 * settle for the largest bufsize that leaves enough room in the cluster 4934 * for metadata. 4935 * 4936 * Without buffer packing: Look for the smallest zone which has a 4937 * bufsize large enough for the max payload. Settle for the largest 4938 * bufsize available if there's nothing big enough for max payload. 4939 */ 4940 spare_needed = fl->flags & FL_BUF_PACKING ? CL_METADATA_SIZE : 0; 4941 swz = &sc->sge.sw_zone_info[0]; 4942 hwidx = -1; 4943 for (zidx = 0; zidx < SW_ZONE_SIZES; zidx++, swz++) { 4944 if (swz->size > largest_rx_cluster) { 4945 if (__predict_true(hwidx != -1)) 4946 break; 4947 4948 /* 4949 * This is a misconfiguration. largest_rx_cluster is 4950 * preventing us from finding a refill source. See 4951 * dev.t5nex.<n>.buffer_sizes to figure out why. 4952 */ 4953 device_printf(sc->dev, "largest_rx_cluster=%u leaves no" 4954 " refill source for fl %p (dma %u). Ignored.\n", 4955 largest_rx_cluster, fl, maxp); 4956 } 4957 for (idx = swz->head_hwidx; idx != -1; idx = hwb->next) { 4958 hwb = &hwb_list[idx]; 4959 spare = swz->size - hwb->size; 4960 if (spare < spare_needed) 4961 continue; 4962 4963 hwidx = idx; /* best option so far */ 4964 if (hwb->size >= maxp) { 4965 4966 if ((fl->flags & FL_BUF_PACKING) == 0) 4967 goto done; /* stop looking (not packing) */ 4968 4969 if (swz->size >= safest_rx_cluster) 4970 goto done; /* stop looking (packing) */ 4971 } 4972 break; /* keep looking, next zone */ 4973 } 4974 } 4975 done: 4976 /* A usable hwidx has been located. */ 4977 MPASS(hwidx != -1); 4978 hwb = &hwb_list[hwidx]; 4979 zidx = hwb->zidx; 4980 swz = &sc->sge.sw_zone_info[zidx]; 4981 region1 = 0; 4982 region3 = swz->size - hwb->size; 4983 4984 /* 4985 * Stay within this zone and see if there is a better match when mbuf 4986 * inlining is allowed. Remember that the hwidx's are sorted in 4987 * decreasing order of size (so in increasing order of spare area). 4988 */ 4989 for (idx = hwidx; idx != -1; idx = hwb->next) { 4990 hwb = &hwb_list[idx]; 4991 spare = swz->size - hwb->size; 4992 4993 if (allow_mbufs_in_cluster == 0 || hwb->size < maxp) 4994 break; 4995 4996 /* 4997 * Do not inline mbufs if doing so would violate the pad/pack 4998 * boundary alignment requirement. 4999 */ 5000 if (fl_pad && (MSIZE % sc->params.sge.pad_boundary) != 0) 5001 continue; 5002 if (fl->flags & FL_BUF_PACKING && 5003 (MSIZE % sc->params.sge.pack_boundary) != 0) 5004 continue; 5005 5006 if (spare < CL_METADATA_SIZE + MSIZE) 5007 continue; 5008 n = (spare - CL_METADATA_SIZE) / MSIZE; 5009 if (n > howmany(hwb->size, maxp)) 5010 break; 5011 5012 hwidx = idx; 5013 if (fl->flags & FL_BUF_PACKING) { 5014 region1 = n * MSIZE; 5015 region3 = spare - region1; 5016 } else { 5017 region1 = MSIZE; 5018 region3 = spare - region1; 5019 break; 5020 } 5021 } 5022 5023 KASSERT(zidx >= 0 && zidx < SW_ZONE_SIZES, 5024 ("%s: bad zone %d for fl %p, maxp %d", __func__, zidx, fl, maxp)); 5025 KASSERT(hwidx >= 0 && hwidx <= SGE_FLBUF_SIZES, 5026 ("%s: bad hwidx %d for fl %p, maxp %d", __func__, hwidx, fl, maxp)); 5027 KASSERT(region1 + sc->sge.hw_buf_info[hwidx].size + region3 == 5028 sc->sge.sw_zone_info[zidx].size, 5029 ("%s: bad buffer layout for fl %p, maxp %d. " 5030 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp, 5031 sc->sge.sw_zone_info[zidx].size, region1, 5032 sc->sge.hw_buf_info[hwidx].size, region3)); 5033 if (fl->flags & FL_BUF_PACKING || region1 > 0) { 5034 KASSERT(region3 >= CL_METADATA_SIZE, 5035 ("%s: no room for metadata. fl %p, maxp %d; " 5036 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp, 5037 sc->sge.sw_zone_info[zidx].size, region1, 5038 sc->sge.hw_buf_info[hwidx].size, region3)); 5039 KASSERT(region1 % MSIZE == 0, 5040 ("%s: bad mbuf region for fl %p, maxp %d. " 5041 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp, 5042 sc->sge.sw_zone_info[zidx].size, region1, 5043 sc->sge.hw_buf_info[hwidx].size, region3)); 5044 } 5045 5046 fl->cll_def.zidx = zidx; 5047 fl->cll_def.hwidx = hwidx; 5048 fl->cll_def.region1 = region1; 5049 fl->cll_def.region3 = region3; 5050 } 5051 5052 static void 5053 find_safe_refill_source(struct adapter *sc, struct sge_fl *fl) 5054 { 5055 struct sge *s = &sc->sge; 5056 struct hw_buf_info *hwb; 5057 struct sw_zone_info *swz; 5058 int spare; 5059 int8_t hwidx; 5060 5061 if (fl->flags & FL_BUF_PACKING) 5062 hwidx = s->safe_hwidx2; /* with room for metadata */ 5063 else if (allow_mbufs_in_cluster && s->safe_hwidx2 != -1) { 5064 hwidx = s->safe_hwidx2; 5065 hwb = &s->hw_buf_info[hwidx]; 5066 swz = &s->sw_zone_info[hwb->zidx]; 5067 spare = swz->size - hwb->size; 5068 5069 /* no good if there isn't room for an mbuf as well */ 5070 if (spare < CL_METADATA_SIZE + MSIZE) 5071 hwidx = s->safe_hwidx1; 5072 } else 5073 hwidx = s->safe_hwidx1; 5074 5075 if (hwidx == -1) { 5076 /* No fallback source */ 5077 fl->cll_alt.hwidx = -1; 5078 fl->cll_alt.zidx = -1; 5079 5080 return; 5081 } 5082 5083 hwb = &s->hw_buf_info[hwidx]; 5084 swz = &s->sw_zone_info[hwb->zidx]; 5085 spare = swz->size - hwb->size; 5086 fl->cll_alt.hwidx = hwidx; 5087 fl->cll_alt.zidx = hwb->zidx; 5088 if (allow_mbufs_in_cluster && 5089 (fl_pad == 0 || (MSIZE % sc->params.sge.pad_boundary) == 0)) 5090 fl->cll_alt.region1 = ((spare - CL_METADATA_SIZE) / MSIZE) * MSIZE; 5091 else 5092 fl->cll_alt.region1 = 0; 5093 fl->cll_alt.region3 = spare - fl->cll_alt.region1; 5094 } 5095 5096 static void 5097 add_fl_to_sfl(struct adapter *sc, struct sge_fl *fl) 5098 { 5099 mtx_lock(&sc->sfl_lock); 5100 FL_LOCK(fl); 5101 if ((fl->flags & FL_DOOMED) == 0) { 5102 fl->flags |= FL_STARVING; 5103 TAILQ_INSERT_TAIL(&sc->sfl, fl, link); 5104 callout_reset(&sc->sfl_callout, hz / 5, refill_sfl, sc); 5105 } 5106 FL_UNLOCK(fl); 5107 mtx_unlock(&sc->sfl_lock); 5108 } 5109 5110 static void 5111 handle_wrq_egr_update(struct adapter *sc, struct sge_eq *eq) 5112 { 5113 struct sge_wrq *wrq = (void *)eq; 5114 5115 atomic_readandclear_int(&eq->equiq); 5116 taskqueue_enqueue(sc->tq[eq->tx_chan], &wrq->wrq_tx_task); 5117 } 5118 5119 static void 5120 handle_eth_egr_update(struct adapter *sc, struct sge_eq *eq) 5121 { 5122 struct sge_txq *txq = (void *)eq; 5123 5124 MPASS((eq->flags & EQ_TYPEMASK) == EQ_ETH); 5125 5126 atomic_readandclear_int(&eq->equiq); 5127 mp_ring_check_drainage(txq->r, 0); 5128 taskqueue_enqueue(sc->tq[eq->tx_chan], &txq->tx_reclaim_task); 5129 } 5130 5131 static int 5132 handle_sge_egr_update(struct sge_iq *iq, const struct rss_header *rss, 5133 struct mbuf *m) 5134 { 5135 const struct cpl_sge_egr_update *cpl = (const void *)(rss + 1); 5136 unsigned int qid = G_EGR_QID(ntohl(cpl->opcode_qid)); 5137 struct adapter *sc = iq->adapter; 5138 struct sge *s = &sc->sge; 5139 struct sge_eq *eq; 5140 static void (*h[])(struct adapter *, struct sge_eq *) = {NULL, 5141 &handle_wrq_egr_update, &handle_eth_egr_update, 5142 &handle_wrq_egr_update}; 5143 5144 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 5145 rss->opcode)); 5146 5147 eq = s->eqmap[qid - s->eq_start - s->eq_base]; 5148 (*h[eq->flags & EQ_TYPEMASK])(sc, eq); 5149 5150 return (0); 5151 } 5152 5153 /* handle_fw_msg works for both fw4_msg and fw6_msg because this is valid */ 5154 CTASSERT(offsetof(struct cpl_fw4_msg, data) == \ 5155 offsetof(struct cpl_fw6_msg, data)); 5156 5157 static int 5158 handle_fw_msg(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 5159 { 5160 struct adapter *sc = iq->adapter; 5161 const struct cpl_fw6_msg *cpl = (const void *)(rss + 1); 5162 5163 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 5164 rss->opcode)); 5165 5166 if (cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL) { 5167 const struct rss_header *rss2; 5168 5169 rss2 = (const struct rss_header *)&cpl->data[0]; 5170 return (t4_cpl_handler[rss2->opcode](iq, rss2, m)); 5171 } 5172 5173 return (t4_fw_msg_handler[cpl->type](sc, &cpl->data[0])); 5174 } 5175 5176 /** 5177 * t4_handle_wrerr_rpl - process a FW work request error message 5178 * @adap: the adapter 5179 * @rpl: start of the FW message 5180 */ 5181 static int 5182 t4_handle_wrerr_rpl(struct adapter *adap, const __be64 *rpl) 5183 { 5184 u8 opcode = *(const u8 *)rpl; 5185 const struct fw_error_cmd *e = (const void *)rpl; 5186 unsigned int i; 5187 5188 if (opcode != FW_ERROR_CMD) { 5189 log(LOG_ERR, 5190 "%s: Received WRERR_RPL message with opcode %#x\n", 5191 device_get_nameunit(adap->dev), opcode); 5192 return (EINVAL); 5193 } 5194 log(LOG_ERR, "%s: FW_ERROR (%s) ", device_get_nameunit(adap->dev), 5195 G_FW_ERROR_CMD_FATAL(be32toh(e->op_to_type)) ? "fatal" : 5196 "non-fatal"); 5197 switch (G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type))) { 5198 case FW_ERROR_TYPE_EXCEPTION: 5199 log(LOG_ERR, "exception info:\n"); 5200 for (i = 0; i < nitems(e->u.exception.info); i++) 5201 log(LOG_ERR, "%s%08x", i == 0 ? "\t" : " ", 5202 be32toh(e->u.exception.info[i])); 5203 log(LOG_ERR, "\n"); 5204 break; 5205 case FW_ERROR_TYPE_HWMODULE: 5206 log(LOG_ERR, "HW module regaddr %08x regval %08x\n", 5207 be32toh(e->u.hwmodule.regaddr), 5208 be32toh(e->u.hwmodule.regval)); 5209 break; 5210 case FW_ERROR_TYPE_WR: 5211 log(LOG_ERR, "WR cidx %d PF %d VF %d eqid %d hdr:\n", 5212 be16toh(e->u.wr.cidx), 5213 G_FW_ERROR_CMD_PFN(be16toh(e->u.wr.pfn_vfn)), 5214 G_FW_ERROR_CMD_VFN(be16toh(e->u.wr.pfn_vfn)), 5215 be32toh(e->u.wr.eqid)); 5216 for (i = 0; i < nitems(e->u.wr.wrhdr); i++) 5217 log(LOG_ERR, "%s%02x", i == 0 ? "\t" : " ", 5218 e->u.wr.wrhdr[i]); 5219 log(LOG_ERR, "\n"); 5220 break; 5221 case FW_ERROR_TYPE_ACL: 5222 log(LOG_ERR, "ACL cidx %d PF %d VF %d eqid %d %s", 5223 be16toh(e->u.acl.cidx), 5224 G_FW_ERROR_CMD_PFN(be16toh(e->u.acl.pfn_vfn)), 5225 G_FW_ERROR_CMD_VFN(be16toh(e->u.acl.pfn_vfn)), 5226 be32toh(e->u.acl.eqid), 5227 G_FW_ERROR_CMD_MV(be16toh(e->u.acl.mv_pkd)) ? "vlanid" : 5228 "MAC"); 5229 for (i = 0; i < nitems(e->u.acl.val); i++) 5230 log(LOG_ERR, " %02x", e->u.acl.val[i]); 5231 log(LOG_ERR, "\n"); 5232 break; 5233 default: 5234 log(LOG_ERR, "type %#x\n", 5235 G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type))); 5236 return (EINVAL); 5237 } 5238 return (0); 5239 } 5240 5241 static int 5242 sysctl_uint16(SYSCTL_HANDLER_ARGS) 5243 { 5244 uint16_t *id = arg1; 5245 int i = *id; 5246 5247 return sysctl_handle_int(oidp, &i, 0, req); 5248 } 5249 5250 static int 5251 sysctl_bufsizes(SYSCTL_HANDLER_ARGS) 5252 { 5253 struct sge *s = arg1; 5254 struct hw_buf_info *hwb = &s->hw_buf_info[0]; 5255 struct sw_zone_info *swz = &s->sw_zone_info[0]; 5256 int i, rc; 5257 struct sbuf sb; 5258 char c; 5259 5260 sbuf_new(&sb, NULL, 32, SBUF_AUTOEXTEND); 5261 for (i = 0; i < SGE_FLBUF_SIZES; i++, hwb++) { 5262 if (hwb->zidx >= 0 && swz[hwb->zidx].size <= largest_rx_cluster) 5263 c = '*'; 5264 else 5265 c = '\0'; 5266 5267 sbuf_printf(&sb, "%u%c ", hwb->size, c); 5268 } 5269 sbuf_trim(&sb); 5270 sbuf_finish(&sb); 5271 rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req); 5272 sbuf_delete(&sb); 5273 return (rc); 5274 } 5275 5276 static int 5277 sysctl_tc(SYSCTL_HANDLER_ARGS) 5278 { 5279 struct vi_info *vi = arg1; 5280 struct port_info *pi; 5281 struct adapter *sc; 5282 struct sge_txq *txq; 5283 struct tx_cl_rl_params *tc; 5284 int qidx = arg2, rc, tc_idx; 5285 uint32_t fw_queue, fw_class; 5286 5287 MPASS(qidx >= 0 && qidx < vi->ntxq); 5288 pi = vi->pi; 5289 sc = pi->adapter; 5290 txq = &sc->sge.txq[vi->first_txq + qidx]; 5291 5292 tc_idx = txq->tc_idx; 5293 rc = sysctl_handle_int(oidp, &tc_idx, 0, req); 5294 if (rc != 0 || req->newptr == NULL) 5295 return (rc); 5296 5297 if (sc->flags & IS_VF) 5298 return (EPERM); 5299 5300 /* Note that -1 is legitimate input (it means unbind). */ 5301 if (tc_idx < -1 || tc_idx >= sc->chip_params->nsched_cls) 5302 return (EINVAL); 5303 5304 mtx_lock(&sc->tc_lock); 5305 if (tc_idx == txq->tc_idx) { 5306 rc = 0; /* No change, nothing to do. */ 5307 goto done; 5308 } 5309 5310 fw_queue = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 5311 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH) | 5312 V_FW_PARAMS_PARAM_YZ(txq->eq.cntxt_id); 5313 5314 if (tc_idx == -1) 5315 fw_class = 0xffffffff; /* Unbind. */ 5316 else { 5317 /* 5318 * Bind to a different class. 5319 */ 5320 tc = &pi->sched_params->cl_rl[tc_idx]; 5321 if (tc->flags & TX_CLRL_ERROR) { 5322 /* Previous attempt to set the cl-rl params failed. */ 5323 rc = EIO; 5324 goto done; 5325 } else { 5326 /* 5327 * Ok to proceed. Place a reference on the new class 5328 * while still holding on to the reference on the 5329 * previous class, if any. 5330 */ 5331 fw_class = tc_idx; 5332 tc->refcount++; 5333 } 5334 } 5335 mtx_unlock(&sc->tc_lock); 5336 5337 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4stc"); 5338 if (rc) 5339 return (rc); 5340 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &fw_queue, &fw_class); 5341 end_synchronized_op(sc, 0); 5342 5343 mtx_lock(&sc->tc_lock); 5344 if (rc == 0) { 5345 if (txq->tc_idx != -1) { 5346 tc = &pi->sched_params->cl_rl[txq->tc_idx]; 5347 MPASS(tc->refcount > 0); 5348 tc->refcount--; 5349 } 5350 txq->tc_idx = tc_idx; 5351 } else if (tc_idx != -1) { 5352 tc = &pi->sched_params->cl_rl[tc_idx]; 5353 MPASS(tc->refcount > 0); 5354 tc->refcount--; 5355 } 5356 done: 5357 mtx_unlock(&sc->tc_lock); 5358 return (rc); 5359 } 5360