1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 Chelsio Communications, Inc. 5 * All rights reserved. 6 * Written by: Navdeep Parhar <np@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include "opt_inet.h" 34 #include "opt_inet6.h" 35 #include "opt_kern_tls.h" 36 #include "opt_ratelimit.h" 37 38 #include <sys/types.h> 39 #include <sys/eventhandler.h> 40 #include <sys/mbuf.h> 41 #include <sys/socket.h> 42 #include <sys/kernel.h> 43 #include <sys/ktls.h> 44 #include <sys/malloc.h> 45 #include <sys/msan.h> 46 #include <sys/queue.h> 47 #include <sys/sbuf.h> 48 #include <sys/taskqueue.h> 49 #include <sys/time.h> 50 #include <sys/sglist.h> 51 #include <sys/sysctl.h> 52 #include <sys/smp.h> 53 #include <sys/socketvar.h> 54 #include <sys/counter.h> 55 #include <net/bpf.h> 56 #include <net/ethernet.h> 57 #include <net/if.h> 58 #include <net/if_vlan_var.h> 59 #include <net/if_vxlan.h> 60 #include <netinet/in.h> 61 #include <netinet/ip.h> 62 #include <netinet/ip6.h> 63 #include <netinet/tcp.h> 64 #include <netinet/udp.h> 65 #include <machine/in_cksum.h> 66 #include <machine/md_var.h> 67 #include <vm/vm.h> 68 #include <vm/pmap.h> 69 #ifdef DEV_NETMAP 70 #include <machine/bus.h> 71 #include <sys/selinfo.h> 72 #include <net/if_var.h> 73 #include <net/netmap.h> 74 #include <dev/netmap/netmap_kern.h> 75 #endif 76 77 #include "common/common.h" 78 #include "common/t4_regs.h" 79 #include "common/t4_regs_values.h" 80 #include "common/t4_msg.h" 81 #include "t4_l2t.h" 82 #include "t4_mp_ring.h" 83 84 #ifdef T4_PKT_TIMESTAMP 85 #define RX_COPY_THRESHOLD (MINCLSIZE - 8) 86 #else 87 #define RX_COPY_THRESHOLD MINCLSIZE 88 #endif 89 90 /* Internal mbuf flags stored in PH_loc.eight[1]. */ 91 #define MC_NOMAP 0x01 92 #define MC_RAW_WR 0x02 93 #define MC_TLS 0x04 94 95 /* 96 * Ethernet frames are DMA'd at this byte offset into the freelist buffer. 97 * 0-7 are valid values. 98 */ 99 static int fl_pktshift = 0; 100 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pktshift, CTLFLAG_RDTUN, &fl_pktshift, 0, 101 "payload DMA offset in rx buffer (bytes)"); 102 103 /* 104 * Pad ethernet payload up to this boundary. 105 * -1: driver should figure out a good value. 106 * 0: disable padding. 107 * Any power of 2 from 32 to 4096 (both inclusive) is also a valid value. 108 */ 109 int fl_pad = -1; 110 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pad, CTLFLAG_RDTUN, &fl_pad, 0, 111 "payload pad boundary (bytes)"); 112 113 /* 114 * Status page length. 115 * -1: driver should figure out a good value. 116 * 64 or 128 are the only other valid values. 117 */ 118 static int spg_len = -1; 119 SYSCTL_INT(_hw_cxgbe, OID_AUTO, spg_len, CTLFLAG_RDTUN, &spg_len, 0, 120 "status page size (bytes)"); 121 122 /* 123 * Congestion drops. 124 * -1: no congestion feedback (not recommended). 125 * 0: backpressure the channel instead of dropping packets right away. 126 * 1: no backpressure, drop packets for the congested queue immediately. 127 * 2: both backpressure and drop. 128 */ 129 static int cong_drop = 0; 130 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cong_drop, CTLFLAG_RDTUN, &cong_drop, 0, 131 "Congestion control for NIC RX queues (0 = backpressure, 1 = drop, 2 = both"); 132 #ifdef TCP_OFFLOAD 133 static int ofld_cong_drop = 0; 134 SYSCTL_INT(_hw_cxgbe, OID_AUTO, ofld_cong_drop, CTLFLAG_RDTUN, &ofld_cong_drop, 0, 135 "Congestion control for TOE RX queues (0 = backpressure, 1 = drop, 2 = both"); 136 #endif 137 138 /* 139 * Deliver multiple frames in the same free list buffer if they fit. 140 * -1: let the driver decide whether to enable buffer packing or not. 141 * 0: disable buffer packing. 142 * 1: enable buffer packing. 143 */ 144 static int buffer_packing = -1; 145 SYSCTL_INT(_hw_cxgbe, OID_AUTO, buffer_packing, CTLFLAG_RDTUN, &buffer_packing, 146 0, "Enable buffer packing"); 147 148 /* 149 * Start next frame in a packed buffer at this boundary. 150 * -1: driver should figure out a good value. 151 * T4: driver will ignore this and use the same value as fl_pad above. 152 * T5: 16, or a power of 2 from 64 to 4096 (both inclusive) is a valid value. 153 */ 154 static int fl_pack = -1; 155 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pack, CTLFLAG_RDTUN, &fl_pack, 0, 156 "payload pack boundary (bytes)"); 157 158 /* 159 * Largest rx cluster size that the driver is allowed to allocate. 160 */ 161 static int largest_rx_cluster = MJUM16BYTES; 162 SYSCTL_INT(_hw_cxgbe, OID_AUTO, largest_rx_cluster, CTLFLAG_RDTUN, 163 &largest_rx_cluster, 0, "Largest rx cluster (bytes)"); 164 165 /* 166 * Size of cluster allocation that's most likely to succeed. The driver will 167 * fall back to this size if it fails to allocate clusters larger than this. 168 */ 169 static int safest_rx_cluster = PAGE_SIZE; 170 SYSCTL_INT(_hw_cxgbe, OID_AUTO, safest_rx_cluster, CTLFLAG_RDTUN, 171 &safest_rx_cluster, 0, "Safe rx cluster (bytes)"); 172 173 #ifdef RATELIMIT 174 /* 175 * Knob to control TCP timestamp rewriting, and the granularity of the tick used 176 * for rewriting. -1 and 0-3 are all valid values. 177 * -1: hardware should leave the TCP timestamps alone. 178 * 0: 1ms 179 * 1: 100us 180 * 2: 10us 181 * 3: 1us 182 */ 183 static int tsclk = -1; 184 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tsclk, CTLFLAG_RDTUN, &tsclk, 0, 185 "Control TCP timestamp rewriting when using pacing"); 186 187 static int eo_max_backlog = 1024 * 1024; 188 SYSCTL_INT(_hw_cxgbe, OID_AUTO, eo_max_backlog, CTLFLAG_RDTUN, &eo_max_backlog, 189 0, "Maximum backlog of ratelimited data per flow"); 190 #endif 191 192 /* 193 * The interrupt holdoff timers are multiplied by this value on T6+. 194 * 1 and 3-17 (both inclusive) are legal values. 195 */ 196 static int tscale = 1; 197 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tscale, CTLFLAG_RDTUN, &tscale, 0, 198 "Interrupt holdoff timer scale on T6+"); 199 200 /* 201 * Number of LRO entries in the lro_ctrl structure per rx queue. 202 */ 203 static int lro_entries = TCP_LRO_ENTRIES; 204 SYSCTL_INT(_hw_cxgbe, OID_AUTO, lro_entries, CTLFLAG_RDTUN, &lro_entries, 0, 205 "Number of LRO entries per RX queue"); 206 207 /* 208 * This enables presorting of frames before they're fed into tcp_lro_rx. 209 */ 210 static int lro_mbufs = 0; 211 SYSCTL_INT(_hw_cxgbe, OID_AUTO, lro_mbufs, CTLFLAG_RDTUN, &lro_mbufs, 0, 212 "Enable presorting of LRO frames"); 213 214 static counter_u64_t pullups; 215 SYSCTL_COUNTER_U64(_hw_cxgbe, OID_AUTO, pullups, CTLFLAG_RD, &pullups, 216 "Number of mbuf pullups performed"); 217 218 static counter_u64_t defrags; 219 SYSCTL_COUNTER_U64(_hw_cxgbe, OID_AUTO, defrags, CTLFLAG_RD, &defrags, 220 "Number of mbuf defrags performed"); 221 222 static int t4_tx_coalesce = 1; 223 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tx_coalesce, CTLFLAG_RWTUN, &t4_tx_coalesce, 0, 224 "tx coalescing allowed"); 225 226 /* 227 * The driver will make aggressive attempts at tx coalescing if it sees these 228 * many packets eligible for coalescing in quick succession, with no more than 229 * the specified gap in between the eth_tx calls that delivered the packets. 230 */ 231 static int t4_tx_coalesce_pkts = 32; 232 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tx_coalesce_pkts, CTLFLAG_RWTUN, 233 &t4_tx_coalesce_pkts, 0, 234 "# of consecutive packets (1 - 255) that will trigger tx coalescing"); 235 static int t4_tx_coalesce_gap = 5; 236 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tx_coalesce_gap, CTLFLAG_RWTUN, 237 &t4_tx_coalesce_gap, 0, "tx gap (in microseconds)"); 238 239 static int service_iq(struct sge_iq *, int); 240 static int service_iq_fl(struct sge_iq *, int); 241 static struct mbuf *get_fl_payload(struct adapter *, struct sge_fl *, uint32_t); 242 static int eth_rx(struct adapter *, struct sge_rxq *, const struct iq_desc *, 243 u_int); 244 static inline void init_iq(struct sge_iq *, struct adapter *, int, int, int, 245 int, int, int); 246 static inline void init_fl(struct adapter *, struct sge_fl *, int, int, char *); 247 static inline void init_eq(struct adapter *, struct sge_eq *, int, int, uint8_t, 248 struct sge_iq *, char *); 249 static int alloc_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *, 250 struct sysctl_ctx_list *, struct sysctl_oid *); 251 static void free_iq_fl(struct adapter *, struct sge_iq *, struct sge_fl *); 252 static void add_iq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *, 253 struct sge_iq *); 254 static void add_fl_sysctls(struct adapter *, struct sysctl_ctx_list *, 255 struct sysctl_oid *, struct sge_fl *); 256 static int alloc_iq_fl_hwq(struct vi_info *, struct sge_iq *, struct sge_fl *); 257 static int free_iq_fl_hwq(struct adapter *, struct sge_iq *, struct sge_fl *); 258 static int alloc_fwq(struct adapter *); 259 static void free_fwq(struct adapter *); 260 static int alloc_ctrlq(struct adapter *, int); 261 static void free_ctrlq(struct adapter *, int); 262 static int alloc_rxq(struct vi_info *, struct sge_rxq *, int, int, int); 263 static void free_rxq(struct vi_info *, struct sge_rxq *); 264 static void add_rxq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *, 265 struct sge_rxq *); 266 #ifdef TCP_OFFLOAD 267 static int alloc_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *, int, int, 268 int); 269 static void free_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *); 270 static void add_ofld_rxq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *, 271 struct sge_ofld_rxq *); 272 #endif 273 static int ctrl_eq_alloc(struct adapter *, struct sge_eq *); 274 static int eth_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *); 275 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 276 static int ofld_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *); 277 #endif 278 static int alloc_eq(struct adapter *, struct sge_eq *, struct sysctl_ctx_list *, 279 struct sysctl_oid *); 280 static void free_eq(struct adapter *, struct sge_eq *); 281 static void add_eq_sysctls(struct adapter *, struct sysctl_ctx_list *, 282 struct sysctl_oid *, struct sge_eq *); 283 static int alloc_eq_hwq(struct adapter *, struct vi_info *, struct sge_eq *); 284 static int free_eq_hwq(struct adapter *, struct vi_info *, struct sge_eq *); 285 static int alloc_wrq(struct adapter *, struct vi_info *, struct sge_wrq *, 286 struct sysctl_ctx_list *, struct sysctl_oid *); 287 static void free_wrq(struct adapter *, struct sge_wrq *); 288 static void add_wrq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *, 289 struct sge_wrq *); 290 static int alloc_txq(struct vi_info *, struct sge_txq *, int); 291 static void free_txq(struct vi_info *, struct sge_txq *); 292 static void add_txq_sysctls(struct vi_info *, struct sysctl_ctx_list *, 293 struct sysctl_oid *, struct sge_txq *); 294 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 295 static int alloc_ofld_txq(struct vi_info *, struct sge_ofld_txq *, int); 296 static void free_ofld_txq(struct vi_info *, struct sge_ofld_txq *); 297 static void add_ofld_txq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *, 298 struct sge_ofld_txq *); 299 #endif 300 static void oneseg_dma_callback(void *, bus_dma_segment_t *, int, int); 301 static inline void ring_fl_db(struct adapter *, struct sge_fl *); 302 static int refill_fl(struct adapter *, struct sge_fl *, int); 303 static void refill_sfl(void *); 304 static int find_refill_source(struct adapter *, int, bool); 305 static void add_fl_to_sfl(struct adapter *, struct sge_fl *); 306 307 static inline void get_pkt_gl(struct mbuf *, struct sglist *); 308 static inline u_int txpkt_len16(u_int, const u_int); 309 static inline u_int txpkt_vm_len16(u_int, const u_int); 310 static inline void calculate_mbuf_len16(struct mbuf *, bool); 311 static inline u_int txpkts0_len16(u_int); 312 static inline u_int txpkts1_len16(void); 313 static u_int write_raw_wr(struct sge_txq *, void *, struct mbuf *, u_int); 314 static u_int write_txpkt_wr(struct adapter *, struct sge_txq *, struct mbuf *, 315 u_int); 316 static u_int write_txpkt_vm_wr(struct adapter *, struct sge_txq *, 317 struct mbuf *); 318 static int add_to_txpkts_vf(struct adapter *, struct sge_txq *, struct mbuf *, 319 int, bool *); 320 static int add_to_txpkts_pf(struct adapter *, struct sge_txq *, struct mbuf *, 321 int, bool *); 322 static u_int write_txpkts_wr(struct adapter *, struct sge_txq *); 323 static u_int write_txpkts_vm_wr(struct adapter *, struct sge_txq *); 324 static void write_gl_to_txd(struct sge_txq *, struct mbuf *, caddr_t *, int); 325 static inline void copy_to_txd(struct sge_eq *, caddr_t, caddr_t *, int); 326 static inline void ring_eq_db(struct adapter *, struct sge_eq *, u_int); 327 static inline uint16_t read_hw_cidx(struct sge_eq *); 328 static inline u_int reclaimable_tx_desc(struct sge_eq *); 329 static inline u_int total_available_tx_desc(struct sge_eq *); 330 static u_int reclaim_tx_descs(struct sge_txq *, u_int); 331 static void tx_reclaim(void *, int); 332 static __be64 get_flit(struct sglist_seg *, int, int); 333 static int handle_sge_egr_update(struct sge_iq *, const struct rss_header *, 334 struct mbuf *); 335 static int handle_fw_msg(struct sge_iq *, const struct rss_header *, 336 struct mbuf *); 337 static int t4_handle_wrerr_rpl(struct adapter *, const __be64 *); 338 static void wrq_tx_drain(void *, int); 339 static void drain_wrq_wr_list(struct adapter *, struct sge_wrq *); 340 341 static int sysctl_bufsizes(SYSCTL_HANDLER_ARGS); 342 #ifdef RATELIMIT 343 #if defined(INET) || defined(INET6) 344 static inline u_int txpkt_eo_len16(u_int, u_int, u_int); 345 #endif 346 static int ethofld_fw4_ack(struct sge_iq *, const struct rss_header *, 347 struct mbuf *); 348 #endif 349 350 static counter_u64_t extfree_refs; 351 static counter_u64_t extfree_rels; 352 353 an_handler_t t4_an_handler; 354 fw_msg_handler_t t4_fw_msg_handler[NUM_FW6_TYPES]; 355 cpl_handler_t t4_cpl_handler[NUM_CPL_CMDS]; 356 cpl_handler_t set_tcb_rpl_handlers[NUM_CPL_COOKIES]; 357 cpl_handler_t l2t_write_rpl_handlers[NUM_CPL_COOKIES]; 358 cpl_handler_t act_open_rpl_handlers[NUM_CPL_COOKIES]; 359 cpl_handler_t abort_rpl_rss_handlers[NUM_CPL_COOKIES]; 360 cpl_handler_t fw4_ack_handlers[NUM_CPL_COOKIES]; 361 362 void 363 t4_register_an_handler(an_handler_t h) 364 { 365 uintptr_t *loc; 366 367 MPASS(h == NULL || t4_an_handler == NULL); 368 369 loc = (uintptr_t *)&t4_an_handler; 370 atomic_store_rel_ptr(loc, (uintptr_t)h); 371 } 372 373 void 374 t4_register_fw_msg_handler(int type, fw_msg_handler_t h) 375 { 376 uintptr_t *loc; 377 378 MPASS(type < nitems(t4_fw_msg_handler)); 379 MPASS(h == NULL || t4_fw_msg_handler[type] == NULL); 380 /* 381 * These are dispatched by the handler for FW{4|6}_CPL_MSG using the CPL 382 * handler dispatch table. Reject any attempt to install a handler for 383 * this subtype. 384 */ 385 MPASS(type != FW_TYPE_RSSCPL); 386 MPASS(type != FW6_TYPE_RSSCPL); 387 388 loc = (uintptr_t *)&t4_fw_msg_handler[type]; 389 atomic_store_rel_ptr(loc, (uintptr_t)h); 390 } 391 392 void 393 t4_register_cpl_handler(int opcode, cpl_handler_t h) 394 { 395 uintptr_t *loc; 396 397 MPASS(opcode < nitems(t4_cpl_handler)); 398 MPASS(h == NULL || t4_cpl_handler[opcode] == NULL); 399 400 loc = (uintptr_t *)&t4_cpl_handler[opcode]; 401 atomic_store_rel_ptr(loc, (uintptr_t)h); 402 } 403 404 static int 405 set_tcb_rpl_handler(struct sge_iq *iq, const struct rss_header *rss, 406 struct mbuf *m) 407 { 408 const struct cpl_set_tcb_rpl *cpl = (const void *)(rss + 1); 409 u_int tid; 410 int cookie; 411 412 MPASS(m == NULL); 413 414 tid = GET_TID(cpl); 415 if (is_hpftid(iq->adapter, tid) || is_ftid(iq->adapter, tid)) { 416 /* 417 * The return code for filter-write is put in the CPL cookie so 418 * we have to rely on the hardware tid (is_ftid) to determine 419 * that this is a response to a filter. 420 */ 421 cookie = CPL_COOKIE_FILTER; 422 } else { 423 cookie = G_COOKIE(cpl->cookie); 424 } 425 MPASS(cookie > CPL_COOKIE_RESERVED); 426 MPASS(cookie < nitems(set_tcb_rpl_handlers)); 427 428 return (set_tcb_rpl_handlers[cookie](iq, rss, m)); 429 } 430 431 static int 432 l2t_write_rpl_handler(struct sge_iq *iq, const struct rss_header *rss, 433 struct mbuf *m) 434 { 435 const struct cpl_l2t_write_rpl *rpl = (const void *)(rss + 1); 436 unsigned int cookie; 437 438 MPASS(m == NULL); 439 440 cookie = GET_TID(rpl) & F_SYNC_WR ? CPL_COOKIE_TOM : CPL_COOKIE_FILTER; 441 return (l2t_write_rpl_handlers[cookie](iq, rss, m)); 442 } 443 444 static int 445 act_open_rpl_handler(struct sge_iq *iq, const struct rss_header *rss, 446 struct mbuf *m) 447 { 448 const struct cpl_act_open_rpl *cpl = (const void *)(rss + 1); 449 u_int cookie = G_TID_COOKIE(G_AOPEN_ATID(be32toh(cpl->atid_status))); 450 451 MPASS(m == NULL); 452 MPASS(cookie != CPL_COOKIE_RESERVED); 453 454 return (act_open_rpl_handlers[cookie](iq, rss, m)); 455 } 456 457 static int 458 abort_rpl_rss_handler(struct sge_iq *iq, const struct rss_header *rss, 459 struct mbuf *m) 460 { 461 struct adapter *sc = iq->adapter; 462 u_int cookie; 463 464 MPASS(m == NULL); 465 if (is_hashfilter(sc)) 466 cookie = CPL_COOKIE_HASHFILTER; 467 else 468 cookie = CPL_COOKIE_TOM; 469 470 return (abort_rpl_rss_handlers[cookie](iq, rss, m)); 471 } 472 473 static int 474 fw4_ack_handler(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 475 { 476 struct adapter *sc = iq->adapter; 477 const struct cpl_fw4_ack *cpl = (const void *)(rss + 1); 478 unsigned int tid = G_CPL_FW4_ACK_FLOWID(be32toh(OPCODE_TID(cpl))); 479 u_int cookie; 480 481 MPASS(m == NULL); 482 if (is_etid(sc, tid)) 483 cookie = CPL_COOKIE_ETHOFLD; 484 else 485 cookie = CPL_COOKIE_TOM; 486 487 return (fw4_ack_handlers[cookie](iq, rss, m)); 488 } 489 490 static void 491 t4_init_shared_cpl_handlers(void) 492 { 493 494 t4_register_cpl_handler(CPL_SET_TCB_RPL, set_tcb_rpl_handler); 495 t4_register_cpl_handler(CPL_L2T_WRITE_RPL, l2t_write_rpl_handler); 496 t4_register_cpl_handler(CPL_ACT_OPEN_RPL, act_open_rpl_handler); 497 t4_register_cpl_handler(CPL_ABORT_RPL_RSS, abort_rpl_rss_handler); 498 t4_register_cpl_handler(CPL_FW4_ACK, fw4_ack_handler); 499 } 500 501 void 502 t4_register_shared_cpl_handler(int opcode, cpl_handler_t h, int cookie) 503 { 504 uintptr_t *loc; 505 506 MPASS(opcode < nitems(t4_cpl_handler)); 507 MPASS(cookie > CPL_COOKIE_RESERVED); 508 MPASS(cookie < NUM_CPL_COOKIES); 509 MPASS(t4_cpl_handler[opcode] != NULL); 510 511 switch (opcode) { 512 case CPL_SET_TCB_RPL: 513 loc = (uintptr_t *)&set_tcb_rpl_handlers[cookie]; 514 break; 515 case CPL_L2T_WRITE_RPL: 516 loc = (uintptr_t *)&l2t_write_rpl_handlers[cookie]; 517 break; 518 case CPL_ACT_OPEN_RPL: 519 loc = (uintptr_t *)&act_open_rpl_handlers[cookie]; 520 break; 521 case CPL_ABORT_RPL_RSS: 522 loc = (uintptr_t *)&abort_rpl_rss_handlers[cookie]; 523 break; 524 case CPL_FW4_ACK: 525 loc = (uintptr_t *)&fw4_ack_handlers[cookie]; 526 break; 527 default: 528 MPASS(0); 529 return; 530 } 531 MPASS(h == NULL || *loc == (uintptr_t)NULL); 532 atomic_store_rel_ptr(loc, (uintptr_t)h); 533 } 534 535 /* 536 * Called on MOD_LOAD. Validates and calculates the SGE tunables. 537 */ 538 void 539 t4_sge_modload(void) 540 { 541 542 if (fl_pktshift < 0 || fl_pktshift > 7) { 543 printf("Invalid hw.cxgbe.fl_pktshift value (%d)," 544 " using 0 instead.\n", fl_pktshift); 545 fl_pktshift = 0; 546 } 547 548 if (spg_len != 64 && spg_len != 128) { 549 int len; 550 551 #if defined(__i386__) || defined(__amd64__) 552 len = cpu_clflush_line_size > 64 ? 128 : 64; 553 #else 554 len = 64; 555 #endif 556 if (spg_len != -1) { 557 printf("Invalid hw.cxgbe.spg_len value (%d)," 558 " using %d instead.\n", spg_len, len); 559 } 560 spg_len = len; 561 } 562 563 if (cong_drop < -1 || cong_drop > 2) { 564 printf("Invalid hw.cxgbe.cong_drop value (%d)," 565 " using 0 instead.\n", cong_drop); 566 cong_drop = 0; 567 } 568 #ifdef TCP_OFFLOAD 569 if (ofld_cong_drop < -1 || ofld_cong_drop > 2) { 570 printf("Invalid hw.cxgbe.ofld_cong_drop value (%d)," 571 " using 0 instead.\n", ofld_cong_drop); 572 ofld_cong_drop = 0; 573 } 574 #endif 575 576 if (tscale != 1 && (tscale < 3 || tscale > 17)) { 577 printf("Invalid hw.cxgbe.tscale value (%d)," 578 " using 1 instead.\n", tscale); 579 tscale = 1; 580 } 581 582 if (largest_rx_cluster != MCLBYTES && 583 largest_rx_cluster != MJUMPAGESIZE && 584 largest_rx_cluster != MJUM9BYTES && 585 largest_rx_cluster != MJUM16BYTES) { 586 printf("Invalid hw.cxgbe.largest_rx_cluster value (%d)," 587 " using %d instead.\n", largest_rx_cluster, MJUM16BYTES); 588 largest_rx_cluster = MJUM16BYTES; 589 } 590 591 if (safest_rx_cluster != MCLBYTES && 592 safest_rx_cluster != MJUMPAGESIZE && 593 safest_rx_cluster != MJUM9BYTES && 594 safest_rx_cluster != MJUM16BYTES) { 595 printf("Invalid hw.cxgbe.safest_rx_cluster value (%d)," 596 " using %d instead.\n", safest_rx_cluster, MJUMPAGESIZE); 597 safest_rx_cluster = MJUMPAGESIZE; 598 } 599 600 extfree_refs = counter_u64_alloc(M_WAITOK); 601 extfree_rels = counter_u64_alloc(M_WAITOK); 602 pullups = counter_u64_alloc(M_WAITOK); 603 defrags = counter_u64_alloc(M_WAITOK); 604 counter_u64_zero(extfree_refs); 605 counter_u64_zero(extfree_rels); 606 counter_u64_zero(pullups); 607 counter_u64_zero(defrags); 608 609 t4_init_shared_cpl_handlers(); 610 t4_register_cpl_handler(CPL_FW4_MSG, handle_fw_msg); 611 t4_register_cpl_handler(CPL_FW6_MSG, handle_fw_msg); 612 t4_register_cpl_handler(CPL_SGE_EGR_UPDATE, handle_sge_egr_update); 613 #ifdef RATELIMIT 614 t4_register_shared_cpl_handler(CPL_FW4_ACK, ethofld_fw4_ack, 615 CPL_COOKIE_ETHOFLD); 616 #endif 617 t4_register_fw_msg_handler(FW6_TYPE_CMD_RPL, t4_handle_fw_rpl); 618 t4_register_fw_msg_handler(FW6_TYPE_WRERR_RPL, t4_handle_wrerr_rpl); 619 } 620 621 void 622 t4_sge_modunload(void) 623 { 624 625 counter_u64_free(extfree_refs); 626 counter_u64_free(extfree_rels); 627 counter_u64_free(pullups); 628 counter_u64_free(defrags); 629 } 630 631 uint64_t 632 t4_sge_extfree_refs(void) 633 { 634 uint64_t refs, rels; 635 636 rels = counter_u64_fetch(extfree_rels); 637 refs = counter_u64_fetch(extfree_refs); 638 639 return (refs - rels); 640 } 641 642 /* max 4096 */ 643 #define MAX_PACK_BOUNDARY 512 644 645 static inline void 646 setup_pad_and_pack_boundaries(struct adapter *sc) 647 { 648 uint32_t v, m; 649 int pad, pack, pad_shift; 650 651 pad_shift = chip_id(sc) > CHELSIO_T5 ? X_T6_INGPADBOUNDARY_SHIFT : 652 X_INGPADBOUNDARY_SHIFT; 653 pad = fl_pad; 654 if (fl_pad < (1 << pad_shift) || 655 fl_pad > (1 << (pad_shift + M_INGPADBOUNDARY)) || 656 !powerof2(fl_pad)) { 657 /* 658 * If there is any chance that we might use buffer packing and 659 * the chip is a T4, then pick 64 as the pad/pack boundary. Set 660 * it to the minimum allowed in all other cases. 661 */ 662 pad = is_t4(sc) && buffer_packing ? 64 : 1 << pad_shift; 663 664 /* 665 * For fl_pad = 0 we'll still write a reasonable value to the 666 * register but all the freelists will opt out of padding. 667 * We'll complain here only if the user tried to set it to a 668 * value greater than 0 that was invalid. 669 */ 670 if (fl_pad > 0) { 671 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pad value" 672 " (%d), using %d instead.\n", fl_pad, pad); 673 } 674 } 675 m = V_INGPADBOUNDARY(M_INGPADBOUNDARY); 676 v = V_INGPADBOUNDARY(ilog2(pad) - pad_shift); 677 t4_set_reg_field(sc, A_SGE_CONTROL, m, v); 678 679 if (is_t4(sc)) { 680 if (fl_pack != -1 && fl_pack != pad) { 681 /* Complain but carry on. */ 682 device_printf(sc->dev, "hw.cxgbe.fl_pack (%d) ignored," 683 " using %d instead.\n", fl_pack, pad); 684 } 685 return; 686 } 687 688 pack = fl_pack; 689 if (fl_pack < 16 || fl_pack == 32 || fl_pack > 4096 || 690 !powerof2(fl_pack)) { 691 if (sc->params.pci.mps > MAX_PACK_BOUNDARY) 692 pack = MAX_PACK_BOUNDARY; 693 else 694 pack = max(sc->params.pci.mps, CACHE_LINE_SIZE); 695 MPASS(powerof2(pack)); 696 if (pack < 16) 697 pack = 16; 698 if (pack == 32) 699 pack = 64; 700 if (pack > 4096) 701 pack = 4096; 702 if (fl_pack != -1) { 703 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pack value" 704 " (%d), using %d instead.\n", fl_pack, pack); 705 } 706 } 707 m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY); 708 if (pack == 16) 709 v = V_INGPACKBOUNDARY(0); 710 else 711 v = V_INGPACKBOUNDARY(ilog2(pack) - 5); 712 713 MPASS(!is_t4(sc)); /* T4 doesn't have SGE_CONTROL2 */ 714 t4_set_reg_field(sc, A_SGE_CONTROL2, m, v); 715 } 716 717 /* 718 * adap->params.vpd.cclk must be set up before this is called. 719 */ 720 void 721 t4_tweak_chip_settings(struct adapter *sc) 722 { 723 int i, reg; 724 uint32_t v, m; 725 int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200}; 726 int timer_max = M_TIMERVALUE0 * 1000 / sc->params.vpd.cclk; 727 int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */ 728 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 729 static int sw_buf_sizes[] = { 730 MCLBYTES, 731 MJUMPAGESIZE, 732 MJUM9BYTES, 733 MJUM16BYTES 734 }; 735 736 KASSERT(sc->flags & MASTER_PF, 737 ("%s: trying to change chip settings when not master.", __func__)); 738 739 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE; 740 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE | 741 V_EGRSTATUSPAGESIZE(spg_len == 128); 742 t4_set_reg_field(sc, A_SGE_CONTROL, m, v); 743 744 setup_pad_and_pack_boundaries(sc); 745 746 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) | 747 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) | 748 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) | 749 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) | 750 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) | 751 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) | 752 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) | 753 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10); 754 t4_write_reg(sc, A_SGE_HOST_PAGE_SIZE, v); 755 756 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0, 4096); 757 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE1, 65536); 758 reg = A_SGE_FL_BUFFER_SIZE2; 759 for (i = 0; i < nitems(sw_buf_sizes); i++) { 760 MPASS(reg <= A_SGE_FL_BUFFER_SIZE15); 761 t4_write_reg(sc, reg, sw_buf_sizes[i]); 762 reg += 4; 763 MPASS(reg <= A_SGE_FL_BUFFER_SIZE15); 764 t4_write_reg(sc, reg, sw_buf_sizes[i] - CL_METADATA_SIZE); 765 reg += 4; 766 } 767 768 v = V_THRESHOLD_0(intr_pktcount[0]) | V_THRESHOLD_1(intr_pktcount[1]) | 769 V_THRESHOLD_2(intr_pktcount[2]) | V_THRESHOLD_3(intr_pktcount[3]); 770 t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD, v); 771 772 KASSERT(intr_timer[0] <= timer_max, 773 ("%s: not a single usable timer (%d, %d)", __func__, intr_timer[0], 774 timer_max)); 775 for (i = 1; i < nitems(intr_timer); i++) { 776 KASSERT(intr_timer[i] >= intr_timer[i - 1], 777 ("%s: timers not listed in increasing order (%d)", 778 __func__, i)); 779 780 while (intr_timer[i] > timer_max) { 781 if (i == nitems(intr_timer) - 1) { 782 intr_timer[i] = timer_max; 783 break; 784 } 785 intr_timer[i] += intr_timer[i - 1]; 786 intr_timer[i] /= 2; 787 } 788 } 789 790 v = V_TIMERVALUE0(us_to_core_ticks(sc, intr_timer[0])) | 791 V_TIMERVALUE1(us_to_core_ticks(sc, intr_timer[1])); 792 t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1, v); 793 v = V_TIMERVALUE2(us_to_core_ticks(sc, intr_timer[2])) | 794 V_TIMERVALUE3(us_to_core_ticks(sc, intr_timer[3])); 795 t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3, v); 796 v = V_TIMERVALUE4(us_to_core_ticks(sc, intr_timer[4])) | 797 V_TIMERVALUE5(us_to_core_ticks(sc, intr_timer[5])); 798 t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5, v); 799 800 if (chip_id(sc) >= CHELSIO_T6) { 801 m = V_TSCALE(M_TSCALE); 802 if (tscale == 1) 803 v = 0; 804 else 805 v = V_TSCALE(tscale - 2); 806 t4_set_reg_field(sc, A_SGE_ITP_CONTROL, m, v); 807 808 if (sc->debug_flags & DF_DISABLE_TCB_CACHE) { 809 m = V_RDTHRESHOLD(M_RDTHRESHOLD) | F_WRTHRTHRESHEN | 810 V_WRTHRTHRESH(M_WRTHRTHRESH); 811 t4_tp_pio_read(sc, &v, 1, A_TP_CMM_CONFIG, 1); 812 v &= ~m; 813 v |= V_RDTHRESHOLD(1) | F_WRTHRTHRESHEN | 814 V_WRTHRTHRESH(16); 815 t4_tp_pio_write(sc, &v, 1, A_TP_CMM_CONFIG, 1); 816 } 817 } 818 819 /* 4K, 16K, 64K, 256K DDP "page sizes" for TDDP */ 820 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 821 t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, v); 822 823 /* 824 * 4K, 8K, 16K, 64K DDP "page sizes" for iSCSI DDP. These have been 825 * chosen with MAXPHYS = 128K in mind. The largest DDP buffer that we 826 * may have to deal with is MAXPHYS + 1 page. 827 */ 828 v = V_HPZ0(0) | V_HPZ1(1) | V_HPZ2(2) | V_HPZ3(4); 829 t4_write_reg(sc, A_ULP_RX_ISCSI_PSZ, v); 830 831 /* We use multiple DDP page sizes both in plain-TOE and ISCSI modes. */ 832 m = v = F_TDDPTAGTCB | F_ISCSITAGTCB; 833 t4_set_reg_field(sc, A_ULP_RX_CTL, m, v); 834 835 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 836 F_RESETDDPOFFSET; 837 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 838 t4_set_reg_field(sc, A_TP_PARA_REG5, m, v); 839 } 840 841 /* 842 * SGE wants the buffer to be at least 64B and then a multiple of 16. Its 843 * address mut be 16B aligned. If padding is in use the buffer's start and end 844 * need to be aligned to the pad boundary as well. We'll just make sure that 845 * the size is a multiple of the pad boundary here, it is up to the buffer 846 * allocation code to make sure the start of the buffer is aligned. 847 */ 848 static inline int 849 hwsz_ok(struct adapter *sc, int hwsz) 850 { 851 int mask = fl_pad ? sc->params.sge.pad_boundary - 1 : 16 - 1; 852 853 return (hwsz >= 64 && (hwsz & mask) == 0); 854 } 855 856 /* 857 * Initialize the rx buffer sizes and figure out which zones the buffers will 858 * be allocated from. 859 */ 860 void 861 t4_init_rx_buf_info(struct adapter *sc) 862 { 863 struct sge *s = &sc->sge; 864 struct sge_params *sp = &sc->params.sge; 865 int i, j, n; 866 static int sw_buf_sizes[] = { /* Sorted by size */ 867 MCLBYTES, 868 MJUMPAGESIZE, 869 MJUM9BYTES, 870 MJUM16BYTES 871 }; 872 struct rx_buf_info *rxb; 873 874 s->safe_zidx = -1; 875 rxb = &s->rx_buf_info[0]; 876 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) { 877 rxb->size1 = sw_buf_sizes[i]; 878 rxb->zone = m_getzone(rxb->size1); 879 rxb->type = m_gettype(rxb->size1); 880 rxb->size2 = 0; 881 rxb->hwidx1 = -1; 882 rxb->hwidx2 = -1; 883 for (j = 0; j < SGE_FLBUF_SIZES; j++) { 884 int hwsize = sp->sge_fl_buffer_size[j]; 885 886 if (!hwsz_ok(sc, hwsize)) 887 continue; 888 889 /* hwidx for size1 */ 890 if (rxb->hwidx1 == -1 && rxb->size1 == hwsize) 891 rxb->hwidx1 = j; 892 893 /* hwidx for size2 (buffer packing) */ 894 if (rxb->size1 - CL_METADATA_SIZE < hwsize) 895 continue; 896 n = rxb->size1 - hwsize - CL_METADATA_SIZE; 897 if (n == 0) { 898 rxb->hwidx2 = j; 899 rxb->size2 = hwsize; 900 break; /* stop looking */ 901 } 902 if (rxb->hwidx2 != -1) { 903 if (n < sp->sge_fl_buffer_size[rxb->hwidx2] - 904 hwsize - CL_METADATA_SIZE) { 905 rxb->hwidx2 = j; 906 rxb->size2 = hwsize; 907 } 908 } else if (n <= 2 * CL_METADATA_SIZE) { 909 rxb->hwidx2 = j; 910 rxb->size2 = hwsize; 911 } 912 } 913 if (rxb->hwidx2 != -1) 914 sc->flags |= BUF_PACKING_OK; 915 if (s->safe_zidx == -1 && rxb->size1 == safest_rx_cluster) 916 s->safe_zidx = i; 917 } 918 } 919 920 /* 921 * Verify some basic SGE settings for the PF and VF driver, and other 922 * miscellaneous settings for the PF driver. 923 */ 924 int 925 t4_verify_chip_settings(struct adapter *sc) 926 { 927 struct sge_params *sp = &sc->params.sge; 928 uint32_t m, v, r; 929 int rc = 0; 930 const uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 931 932 m = F_RXPKTCPLMODE; 933 v = F_RXPKTCPLMODE; 934 r = sp->sge_control; 935 if ((r & m) != v) { 936 device_printf(sc->dev, "invalid SGE_CONTROL(0x%x)\n", r); 937 rc = EINVAL; 938 } 939 940 /* 941 * If this changes then every single use of PAGE_SHIFT in the driver 942 * needs to be carefully reviewed for PAGE_SHIFT vs sp->page_shift. 943 */ 944 if (sp->page_shift != PAGE_SHIFT) { 945 device_printf(sc->dev, "invalid SGE_HOST_PAGE_SIZE(0x%x)\n", r); 946 rc = EINVAL; 947 } 948 949 if (sc->flags & IS_VF) 950 return (0); 951 952 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 953 r = t4_read_reg(sc, A_ULP_RX_TDDP_PSZ); 954 if (r != v) { 955 device_printf(sc->dev, "invalid ULP_RX_TDDP_PSZ(0x%x)\n", r); 956 if (sc->vres.ddp.size != 0) 957 rc = EINVAL; 958 } 959 960 m = v = F_TDDPTAGTCB; 961 r = t4_read_reg(sc, A_ULP_RX_CTL); 962 if ((r & m) != v) { 963 device_printf(sc->dev, "invalid ULP_RX_CTL(0x%x)\n", r); 964 if (sc->vres.ddp.size != 0) 965 rc = EINVAL; 966 } 967 968 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 969 F_RESETDDPOFFSET; 970 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 971 r = t4_read_reg(sc, A_TP_PARA_REG5); 972 if ((r & m) != v) { 973 device_printf(sc->dev, "invalid TP_PARA_REG5(0x%x)\n", r); 974 if (sc->vres.ddp.size != 0) 975 rc = EINVAL; 976 } 977 978 return (rc); 979 } 980 981 int 982 t4_create_dma_tag(struct adapter *sc) 983 { 984 int rc; 985 986 rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0, 987 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE, 988 BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL, 989 NULL, &sc->dmat); 990 if (rc != 0) { 991 device_printf(sc->dev, 992 "failed to create main DMA tag: %d\n", rc); 993 } 994 995 return (rc); 996 } 997 998 void 999 t4_sge_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx, 1000 struct sysctl_oid_list *children) 1001 { 1002 struct sge_params *sp = &sc->params.sge; 1003 1004 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "buffer_sizes", 1005 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 1006 sysctl_bufsizes, "A", "freelist buffer sizes"); 1007 1008 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pktshift", CTLFLAG_RD, 1009 NULL, sp->fl_pktshift, "payload DMA offset in rx buffer (bytes)"); 1010 1011 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pad", CTLFLAG_RD, 1012 NULL, sp->pad_boundary, "payload pad boundary (bytes)"); 1013 1014 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "spg_len", CTLFLAG_RD, 1015 NULL, sp->spg_len, "status page size (bytes)"); 1016 1017 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_drop", CTLFLAG_RD, 1018 NULL, cong_drop, "congestion drop setting"); 1019 #ifdef TCP_OFFLOAD 1020 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ofld_cong_drop", CTLFLAG_RD, 1021 NULL, ofld_cong_drop, "congestion drop setting"); 1022 #endif 1023 1024 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pack", CTLFLAG_RD, 1025 NULL, sp->pack_boundary, "payload pack boundary (bytes)"); 1026 } 1027 1028 int 1029 t4_destroy_dma_tag(struct adapter *sc) 1030 { 1031 if (sc->dmat) 1032 bus_dma_tag_destroy(sc->dmat); 1033 1034 return (0); 1035 } 1036 1037 /* 1038 * Allocate and initialize the firmware event queue, control queues, and special 1039 * purpose rx queues owned by the adapter. 1040 * 1041 * Returns errno on failure. Resources allocated up to that point may still be 1042 * allocated. Caller is responsible for cleanup in case this function fails. 1043 */ 1044 int 1045 t4_setup_adapter_queues(struct adapter *sc) 1046 { 1047 int rc, i; 1048 1049 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 1050 1051 /* 1052 * Firmware event queue 1053 */ 1054 rc = alloc_fwq(sc); 1055 if (rc != 0) 1056 return (rc); 1057 1058 /* 1059 * That's all for the VF driver. 1060 */ 1061 if (sc->flags & IS_VF) 1062 return (rc); 1063 1064 /* 1065 * XXX: General purpose rx queues, one per port. 1066 */ 1067 1068 /* 1069 * Control queues, one per port. 1070 */ 1071 for_each_port(sc, i) { 1072 rc = alloc_ctrlq(sc, i); 1073 if (rc != 0) 1074 return (rc); 1075 } 1076 1077 return (rc); 1078 } 1079 1080 /* 1081 * Idempotent 1082 */ 1083 int 1084 t4_teardown_adapter_queues(struct adapter *sc) 1085 { 1086 int i; 1087 1088 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 1089 1090 if (sc->sge.ctrlq != NULL) { 1091 MPASS(!(sc->flags & IS_VF)); /* VFs don't allocate ctrlq. */ 1092 for_each_port(sc, i) 1093 free_ctrlq(sc, i); 1094 } 1095 free_fwq(sc); 1096 1097 return (0); 1098 } 1099 1100 /* Maximum payload that could arrive with a single iq descriptor. */ 1101 static inline int 1102 max_rx_payload(struct adapter *sc, struct ifnet *ifp, const bool ofld) 1103 { 1104 int maxp; 1105 1106 /* large enough even when hw VLAN extraction is disabled */ 1107 maxp = sc->params.sge.fl_pktshift + ETHER_HDR_LEN + 1108 ETHER_VLAN_ENCAP_LEN + ifp->if_mtu; 1109 if (ofld && sc->tt.tls && sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS && 1110 maxp < sc->params.tp.max_rx_pdu) 1111 maxp = sc->params.tp.max_rx_pdu; 1112 return (maxp); 1113 } 1114 1115 int 1116 t4_setup_vi_queues(struct vi_info *vi) 1117 { 1118 int rc = 0, i, intr_idx; 1119 struct sge_rxq *rxq; 1120 struct sge_txq *txq; 1121 #ifdef TCP_OFFLOAD 1122 struct sge_ofld_rxq *ofld_rxq; 1123 #endif 1124 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1125 struct sge_ofld_txq *ofld_txq; 1126 #endif 1127 #ifdef DEV_NETMAP 1128 int saved_idx, iqidx; 1129 struct sge_nm_rxq *nm_rxq; 1130 struct sge_nm_txq *nm_txq; 1131 #endif 1132 struct adapter *sc = vi->adapter; 1133 struct ifnet *ifp = vi->ifp; 1134 int maxp; 1135 1136 /* Interrupt vector to start from (when using multiple vectors) */ 1137 intr_idx = vi->first_intr; 1138 1139 #ifdef DEV_NETMAP 1140 saved_idx = intr_idx; 1141 if (ifp->if_capabilities & IFCAP_NETMAP) { 1142 1143 /* netmap is supported with direct interrupts only. */ 1144 MPASS(!forwarding_intr_to_fwq(sc)); 1145 MPASS(vi->first_intr >= 0); 1146 1147 /* 1148 * We don't have buffers to back the netmap rx queues 1149 * right now so we create the queues in a way that 1150 * doesn't set off any congestion signal in the chip. 1151 */ 1152 for_each_nm_rxq(vi, i, nm_rxq) { 1153 rc = alloc_nm_rxq(vi, nm_rxq, intr_idx, i); 1154 if (rc != 0) 1155 goto done; 1156 intr_idx++; 1157 } 1158 1159 for_each_nm_txq(vi, i, nm_txq) { 1160 iqidx = vi->first_nm_rxq + (i % vi->nnmrxq); 1161 rc = alloc_nm_txq(vi, nm_txq, iqidx, i); 1162 if (rc != 0) 1163 goto done; 1164 } 1165 } 1166 1167 /* Normal rx queues and netmap rx queues share the same interrupts. */ 1168 intr_idx = saved_idx; 1169 #endif 1170 1171 /* 1172 * Allocate rx queues first because a default iqid is required when 1173 * creating a tx queue. 1174 */ 1175 maxp = max_rx_payload(sc, ifp, false); 1176 for_each_rxq(vi, i, rxq) { 1177 rc = alloc_rxq(vi, rxq, i, intr_idx, maxp); 1178 if (rc != 0) 1179 goto done; 1180 if (!forwarding_intr_to_fwq(sc)) 1181 intr_idx++; 1182 } 1183 #ifdef DEV_NETMAP 1184 if (ifp->if_capabilities & IFCAP_NETMAP) 1185 intr_idx = saved_idx + max(vi->nrxq, vi->nnmrxq); 1186 #endif 1187 #ifdef TCP_OFFLOAD 1188 maxp = max_rx_payload(sc, ifp, true); 1189 for_each_ofld_rxq(vi, i, ofld_rxq) { 1190 rc = alloc_ofld_rxq(vi, ofld_rxq, i, intr_idx, maxp); 1191 if (rc != 0) 1192 goto done; 1193 if (!forwarding_intr_to_fwq(sc)) 1194 intr_idx++; 1195 } 1196 #endif 1197 1198 /* 1199 * Now the tx queues. 1200 */ 1201 for_each_txq(vi, i, txq) { 1202 rc = alloc_txq(vi, txq, i); 1203 if (rc != 0) 1204 goto done; 1205 } 1206 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1207 for_each_ofld_txq(vi, i, ofld_txq) { 1208 rc = alloc_ofld_txq(vi, ofld_txq, i); 1209 if (rc != 0) 1210 goto done; 1211 } 1212 #endif 1213 done: 1214 if (rc) 1215 t4_teardown_vi_queues(vi); 1216 1217 return (rc); 1218 } 1219 1220 /* 1221 * Idempotent 1222 */ 1223 int 1224 t4_teardown_vi_queues(struct vi_info *vi) 1225 { 1226 int i; 1227 struct sge_rxq *rxq; 1228 struct sge_txq *txq; 1229 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1230 struct sge_ofld_txq *ofld_txq; 1231 #endif 1232 #ifdef TCP_OFFLOAD 1233 struct sge_ofld_rxq *ofld_rxq; 1234 #endif 1235 #ifdef DEV_NETMAP 1236 struct sge_nm_rxq *nm_rxq; 1237 struct sge_nm_txq *nm_txq; 1238 #endif 1239 1240 #ifdef DEV_NETMAP 1241 if (vi->ifp->if_capabilities & IFCAP_NETMAP) { 1242 for_each_nm_txq(vi, i, nm_txq) { 1243 free_nm_txq(vi, nm_txq); 1244 } 1245 1246 for_each_nm_rxq(vi, i, nm_rxq) { 1247 free_nm_rxq(vi, nm_rxq); 1248 } 1249 } 1250 #endif 1251 1252 /* 1253 * Take down all the tx queues first, as they reference the rx queues 1254 * (for egress updates, etc.). 1255 */ 1256 1257 for_each_txq(vi, i, txq) { 1258 free_txq(vi, txq); 1259 } 1260 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1261 for_each_ofld_txq(vi, i, ofld_txq) { 1262 free_ofld_txq(vi, ofld_txq); 1263 } 1264 #endif 1265 1266 /* 1267 * Then take down the rx queues. 1268 */ 1269 1270 for_each_rxq(vi, i, rxq) { 1271 free_rxq(vi, rxq); 1272 } 1273 #ifdef TCP_OFFLOAD 1274 for_each_ofld_rxq(vi, i, ofld_rxq) { 1275 free_ofld_rxq(vi, ofld_rxq); 1276 } 1277 #endif 1278 1279 return (0); 1280 } 1281 1282 /* 1283 * Interrupt handler when the driver is using only 1 interrupt. This is a very 1284 * unusual scenario. 1285 * 1286 * a) Deals with errors, if any. 1287 * b) Services firmware event queue, which is taking interrupts for all other 1288 * queues. 1289 */ 1290 void 1291 t4_intr_all(void *arg) 1292 { 1293 struct adapter *sc = arg; 1294 struct sge_iq *fwq = &sc->sge.fwq; 1295 1296 MPASS(sc->intr_count == 1); 1297 1298 if (sc->intr_type == INTR_INTX) 1299 t4_write_reg(sc, MYPF_REG(A_PCIE_PF_CLI), 0); 1300 1301 t4_intr_err(arg); 1302 t4_intr_evt(fwq); 1303 } 1304 1305 /* 1306 * Interrupt handler for errors (installed directly when multiple interrupts are 1307 * being used, or called by t4_intr_all). 1308 */ 1309 void 1310 t4_intr_err(void *arg) 1311 { 1312 struct adapter *sc = arg; 1313 uint32_t v; 1314 const bool verbose = (sc->debug_flags & DF_VERBOSE_SLOWINTR) != 0; 1315 1316 if (atomic_load_int(&sc->error_flags) & ADAP_FATAL_ERR) 1317 return; 1318 1319 v = t4_read_reg(sc, MYPF_REG(A_PL_PF_INT_CAUSE)); 1320 if (v & F_PFSW) { 1321 sc->swintr++; 1322 t4_write_reg(sc, MYPF_REG(A_PL_PF_INT_CAUSE), v); 1323 } 1324 1325 if (t4_slow_intr_handler(sc, verbose)) 1326 t4_fatal_err(sc, false); 1327 } 1328 1329 /* 1330 * Interrupt handler for iq-only queues. The firmware event queue is the only 1331 * such queue right now. 1332 */ 1333 void 1334 t4_intr_evt(void *arg) 1335 { 1336 struct sge_iq *iq = arg; 1337 1338 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 1339 service_iq(iq, 0); 1340 (void) atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 1341 } 1342 } 1343 1344 /* 1345 * Interrupt handler for iq+fl queues. 1346 */ 1347 void 1348 t4_intr(void *arg) 1349 { 1350 struct sge_iq *iq = arg; 1351 1352 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 1353 service_iq_fl(iq, 0); 1354 (void) atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 1355 } 1356 } 1357 1358 #ifdef DEV_NETMAP 1359 /* 1360 * Interrupt handler for netmap rx queues. 1361 */ 1362 void 1363 t4_nm_intr(void *arg) 1364 { 1365 struct sge_nm_rxq *nm_rxq = arg; 1366 1367 if (atomic_cmpset_int(&nm_rxq->nm_state, NM_ON, NM_BUSY)) { 1368 service_nm_rxq(nm_rxq); 1369 (void) atomic_cmpset_int(&nm_rxq->nm_state, NM_BUSY, NM_ON); 1370 } 1371 } 1372 1373 /* 1374 * Interrupt handler for vectors shared between NIC and netmap rx queues. 1375 */ 1376 void 1377 t4_vi_intr(void *arg) 1378 { 1379 struct irq *irq = arg; 1380 1381 MPASS(irq->nm_rxq != NULL); 1382 t4_nm_intr(irq->nm_rxq); 1383 1384 MPASS(irq->rxq != NULL); 1385 t4_intr(irq->rxq); 1386 } 1387 #endif 1388 1389 /* 1390 * Deals with interrupts on an iq-only (no freelist) queue. 1391 */ 1392 static int 1393 service_iq(struct sge_iq *iq, int budget) 1394 { 1395 struct sge_iq *q; 1396 struct adapter *sc = iq->adapter; 1397 struct iq_desc *d = &iq->desc[iq->cidx]; 1398 int ndescs = 0, limit; 1399 int rsp_type; 1400 uint32_t lq; 1401 STAILQ_HEAD(, sge_iq) iql = STAILQ_HEAD_INITIALIZER(iql); 1402 1403 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq)); 1404 KASSERT((iq->flags & IQ_HAS_FL) == 0, 1405 ("%s: called for iq %p with fl (iq->flags 0x%x)", __func__, iq, 1406 iq->flags)); 1407 MPASS((iq->flags & IQ_ADJ_CREDIT) == 0); 1408 MPASS((iq->flags & IQ_LRO_ENABLED) == 0); 1409 1410 limit = budget ? budget : iq->qsize / 16; 1411 1412 /* 1413 * We always come back and check the descriptor ring for new indirect 1414 * interrupts and other responses after running a single handler. 1415 */ 1416 for (;;) { 1417 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) { 1418 1419 rmb(); 1420 1421 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen); 1422 lq = be32toh(d->rsp.pldbuflen_qid); 1423 1424 switch (rsp_type) { 1425 case X_RSPD_TYPE_FLBUF: 1426 panic("%s: data for an iq (%p) with no freelist", 1427 __func__, iq); 1428 1429 /* NOTREACHED */ 1430 1431 case X_RSPD_TYPE_CPL: 1432 KASSERT(d->rss.opcode < NUM_CPL_CMDS, 1433 ("%s: bad opcode %02x.", __func__, 1434 d->rss.opcode)); 1435 t4_cpl_handler[d->rss.opcode](iq, &d->rss, NULL); 1436 break; 1437 1438 case X_RSPD_TYPE_INTR: 1439 /* 1440 * There are 1K interrupt-capable queues (qids 0 1441 * through 1023). A response type indicating a 1442 * forwarded interrupt with a qid >= 1K is an 1443 * iWARP async notification. 1444 */ 1445 if (__predict_true(lq >= 1024)) { 1446 t4_an_handler(iq, &d->rsp); 1447 break; 1448 } 1449 1450 q = sc->sge.iqmap[lq - sc->sge.iq_start - 1451 sc->sge.iq_base]; 1452 if (atomic_cmpset_int(&q->state, IQS_IDLE, 1453 IQS_BUSY)) { 1454 if (service_iq_fl(q, q->qsize / 16) == 0) { 1455 (void) atomic_cmpset_int(&q->state, 1456 IQS_BUSY, IQS_IDLE); 1457 } else { 1458 STAILQ_INSERT_TAIL(&iql, q, 1459 link); 1460 } 1461 } 1462 break; 1463 1464 default: 1465 KASSERT(0, 1466 ("%s: illegal response type %d on iq %p", 1467 __func__, rsp_type, iq)); 1468 log(LOG_ERR, 1469 "%s: illegal response type %d on iq %p", 1470 device_get_nameunit(sc->dev), rsp_type, iq); 1471 break; 1472 } 1473 1474 d++; 1475 if (__predict_false(++iq->cidx == iq->sidx)) { 1476 iq->cidx = 0; 1477 iq->gen ^= F_RSPD_GEN; 1478 d = &iq->desc[0]; 1479 } 1480 if (__predict_false(++ndescs == limit)) { 1481 t4_write_reg(sc, sc->sge_gts_reg, 1482 V_CIDXINC(ndescs) | 1483 V_INGRESSQID(iq->cntxt_id) | 1484 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); 1485 ndescs = 0; 1486 1487 if (budget) { 1488 return (EINPROGRESS); 1489 } 1490 } 1491 } 1492 1493 if (STAILQ_EMPTY(&iql)) 1494 break; 1495 1496 /* 1497 * Process the head only, and send it to the back of the list if 1498 * it's still not done. 1499 */ 1500 q = STAILQ_FIRST(&iql); 1501 STAILQ_REMOVE_HEAD(&iql, link); 1502 if (service_iq_fl(q, q->qsize / 8) == 0) 1503 (void) atomic_cmpset_int(&q->state, IQS_BUSY, IQS_IDLE); 1504 else 1505 STAILQ_INSERT_TAIL(&iql, q, link); 1506 } 1507 1508 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) | 1509 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params)); 1510 1511 return (0); 1512 } 1513 1514 #if defined(INET) || defined(INET6) 1515 static inline int 1516 sort_before_lro(struct lro_ctrl *lro) 1517 { 1518 1519 return (lro->lro_mbuf_max != 0); 1520 } 1521 #endif 1522 1523 #define CGBE_SHIFT_SCALE 10 1524 1525 static inline uint64_t 1526 t4_tstmp_to_ns(struct adapter *sc, uint64_t lf) 1527 { 1528 struct clock_sync *cur, dcur; 1529 uint64_t tstmp_sec, tstmp_nsec; 1530 uint64_t hw_clocks; 1531 uint64_t rt_cur_to_prev, res_s, res_n, res_s_modulo, res; 1532 uint64_t hw_clk_div, cclk; 1533 uint64_t hw_tstmp = lf & 0xfffffffffffffffULL; /* 60b, not 64b. */ 1534 uint32_t gen; 1535 1536 do { 1537 cur = &sc->cal_info[sc->cal_current]; 1538 gen = atomic_load_acq_int(&cur->gen); 1539 if (gen == 0) 1540 return (0); 1541 dcur = *cur; 1542 atomic_thread_fence_acq(); 1543 } while (gen != dcur.gen); 1544 1545 /* 1546 * Our goal here is to have a result that is: 1547 * 1548 * ( (cur_time - prev_time) ) 1549 * ((hw_tstmp - hw_prev) * ----------------------------- ) + prev_time 1550 * ( (hw_cur - hw_prev) ) 1551 * 1552 * With the constraints that we cannot use float and we 1553 * don't want to overflow the uint64_t numbers we are using. 1554 * 1555 * The plan is to take the clocking value of the hw timestamps 1556 * and split them into seconds and nanosecond equivalent portions. 1557 * Then we operate on the two portions seperately making sure to 1558 * bring back the carry over from the seconds when we divide. 1559 * 1560 * First up lets get the two divided into separate entities 1561 * i.e. the seconds. We use the clock frequency for this. 1562 * Note that vpd.cclk is in khz, we need it in raw hz so 1563 * convert to hz. 1564 */ 1565 cclk = sc->params.vpd.cclk * 1000; 1566 hw_clocks = hw_tstmp - dcur.hw_prev; 1567 tstmp_sec = hw_clocks / cclk; 1568 tstmp_nsec = hw_clocks % cclk; 1569 /* Now work with them separately */ 1570 rt_cur_to_prev = (dcur.rt_cur - dcur.rt_prev); 1571 res_s = tstmp_sec * rt_cur_to_prev; 1572 res_n = tstmp_nsec * rt_cur_to_prev; 1573 /* Now lets get our divider */ 1574 hw_clk_div = dcur.hw_cur - dcur.hw_prev; 1575 /* Make sure to save the remainder from the seconds divide */ 1576 res_s_modulo = res_s % hw_clk_div; 1577 res_s /= hw_clk_div; 1578 /* scale the remainder to where it should be */ 1579 res_s_modulo *= cclk; 1580 /* Now add in the remainder */ 1581 res_n += res_s_modulo; 1582 /* Now do the divide */ 1583 res_n /= hw_clk_div; 1584 res_s *= cclk; 1585 /* Recombine the two */ 1586 res = res_s + res_n; 1587 /* And now add in the base time to get to the real timestamp */ 1588 res += dcur.rt_prev; 1589 return (res); 1590 } 1591 1592 static inline void 1593 move_to_next_rxbuf(struct sge_fl *fl) 1594 { 1595 1596 fl->rx_offset = 0; 1597 if (__predict_false((++fl->cidx & 7) == 0)) { 1598 uint16_t cidx = fl->cidx >> 3; 1599 1600 if (__predict_false(cidx == fl->sidx)) 1601 fl->cidx = cidx = 0; 1602 fl->hw_cidx = cidx; 1603 } 1604 } 1605 1606 /* 1607 * Deals with interrupts on an iq+fl queue. 1608 */ 1609 static int 1610 service_iq_fl(struct sge_iq *iq, int budget) 1611 { 1612 struct sge_rxq *rxq = iq_to_rxq(iq); 1613 struct sge_fl *fl; 1614 struct adapter *sc = iq->adapter; 1615 struct iq_desc *d = &iq->desc[iq->cidx]; 1616 int ndescs, limit; 1617 int rsp_type, starved; 1618 uint32_t lq; 1619 uint16_t fl_hw_cidx; 1620 struct mbuf *m0; 1621 #if defined(INET) || defined(INET6) 1622 const struct timeval lro_timeout = {0, sc->lro_timeout}; 1623 struct lro_ctrl *lro = &rxq->lro; 1624 #endif 1625 1626 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq)); 1627 MPASS(iq->flags & IQ_HAS_FL); 1628 1629 ndescs = 0; 1630 #if defined(INET) || defined(INET6) 1631 if (iq->flags & IQ_ADJ_CREDIT) { 1632 MPASS(sort_before_lro(lro)); 1633 iq->flags &= ~IQ_ADJ_CREDIT; 1634 if ((d->rsp.u.type_gen & F_RSPD_GEN) != iq->gen) { 1635 tcp_lro_flush_all(lro); 1636 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(1) | 1637 V_INGRESSQID((u32)iq->cntxt_id) | 1638 V_SEINTARM(iq->intr_params)); 1639 return (0); 1640 } 1641 ndescs = 1; 1642 } 1643 #else 1644 MPASS((iq->flags & IQ_ADJ_CREDIT) == 0); 1645 #endif 1646 1647 limit = budget ? budget : iq->qsize / 16; 1648 fl = &rxq->fl; 1649 fl_hw_cidx = fl->hw_cidx; /* stable snapshot */ 1650 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) { 1651 1652 rmb(); 1653 1654 m0 = NULL; 1655 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen); 1656 lq = be32toh(d->rsp.pldbuflen_qid); 1657 1658 switch (rsp_type) { 1659 case X_RSPD_TYPE_FLBUF: 1660 if (lq & F_RSPD_NEWBUF) { 1661 if (fl->rx_offset > 0) 1662 move_to_next_rxbuf(fl); 1663 lq = G_RSPD_LEN(lq); 1664 } 1665 if (IDXDIFF(fl->hw_cidx, fl_hw_cidx, fl->sidx) > 4) { 1666 FL_LOCK(fl); 1667 refill_fl(sc, fl, 64); 1668 FL_UNLOCK(fl); 1669 fl_hw_cidx = fl->hw_cidx; 1670 } 1671 1672 if (d->rss.opcode == CPL_RX_PKT) { 1673 if (__predict_true(eth_rx(sc, rxq, d, lq) == 0)) 1674 break; 1675 goto out; 1676 } 1677 m0 = get_fl_payload(sc, fl, lq); 1678 if (__predict_false(m0 == NULL)) 1679 goto out; 1680 1681 /* fall through */ 1682 1683 case X_RSPD_TYPE_CPL: 1684 KASSERT(d->rss.opcode < NUM_CPL_CMDS, 1685 ("%s: bad opcode %02x.", __func__, d->rss.opcode)); 1686 t4_cpl_handler[d->rss.opcode](iq, &d->rss, m0); 1687 break; 1688 1689 case X_RSPD_TYPE_INTR: 1690 1691 /* 1692 * There are 1K interrupt-capable queues (qids 0 1693 * through 1023). A response type indicating a 1694 * forwarded interrupt with a qid >= 1K is an 1695 * iWARP async notification. That is the only 1696 * acceptable indirect interrupt on this queue. 1697 */ 1698 if (__predict_false(lq < 1024)) { 1699 panic("%s: indirect interrupt on iq_fl %p " 1700 "with qid %u", __func__, iq, lq); 1701 } 1702 1703 t4_an_handler(iq, &d->rsp); 1704 break; 1705 1706 default: 1707 KASSERT(0, ("%s: illegal response type %d on iq %p", 1708 __func__, rsp_type, iq)); 1709 log(LOG_ERR, "%s: illegal response type %d on iq %p", 1710 device_get_nameunit(sc->dev), rsp_type, iq); 1711 break; 1712 } 1713 1714 d++; 1715 if (__predict_false(++iq->cidx == iq->sidx)) { 1716 iq->cidx = 0; 1717 iq->gen ^= F_RSPD_GEN; 1718 d = &iq->desc[0]; 1719 } 1720 if (__predict_false(++ndescs == limit)) { 1721 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) | 1722 V_INGRESSQID(iq->cntxt_id) | 1723 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); 1724 1725 #if defined(INET) || defined(INET6) 1726 if (iq->flags & IQ_LRO_ENABLED && 1727 !sort_before_lro(lro) && 1728 sc->lro_timeout != 0) { 1729 tcp_lro_flush_inactive(lro, &lro_timeout); 1730 } 1731 #endif 1732 if (budget) 1733 return (EINPROGRESS); 1734 ndescs = 0; 1735 } 1736 } 1737 out: 1738 #if defined(INET) || defined(INET6) 1739 if (iq->flags & IQ_LRO_ENABLED) { 1740 if (ndescs > 0 && lro->lro_mbuf_count > 8) { 1741 MPASS(sort_before_lro(lro)); 1742 /* hold back one credit and don't flush LRO state */ 1743 iq->flags |= IQ_ADJ_CREDIT; 1744 ndescs--; 1745 } else { 1746 tcp_lro_flush_all(lro); 1747 } 1748 } 1749 #endif 1750 1751 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) | 1752 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params)); 1753 1754 FL_LOCK(fl); 1755 starved = refill_fl(sc, fl, 64); 1756 FL_UNLOCK(fl); 1757 if (__predict_false(starved != 0)) 1758 add_fl_to_sfl(sc, fl); 1759 1760 return (0); 1761 } 1762 1763 static inline struct cluster_metadata * 1764 cl_metadata(struct fl_sdesc *sd) 1765 { 1766 1767 return ((void *)(sd->cl + sd->moff)); 1768 } 1769 1770 static void 1771 rxb_free(struct mbuf *m) 1772 { 1773 struct cluster_metadata *clm = m->m_ext.ext_arg1; 1774 1775 uma_zfree(clm->zone, clm->cl); 1776 counter_u64_add(extfree_rels, 1); 1777 } 1778 1779 /* 1780 * The mbuf returned comes from zone_muf and carries the payload in one of these 1781 * ways 1782 * a) complete frame inside the mbuf 1783 * b) m_cljset (for clusters without metadata) 1784 * d) m_extaddref (cluster with metadata) 1785 */ 1786 static struct mbuf * 1787 get_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset, 1788 int remaining) 1789 { 1790 struct mbuf *m; 1791 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 1792 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[sd->zidx]; 1793 struct cluster_metadata *clm; 1794 int len, blen; 1795 caddr_t payload; 1796 1797 if (fl->flags & FL_BUF_PACKING) { 1798 u_int l, pad; 1799 1800 blen = rxb->size2 - fl->rx_offset; /* max possible in this buf */ 1801 len = min(remaining, blen); 1802 payload = sd->cl + fl->rx_offset; 1803 1804 l = fr_offset + len; 1805 pad = roundup2(l, fl->buf_boundary) - l; 1806 if (fl->rx_offset + len + pad < rxb->size2) 1807 blen = len + pad; 1808 MPASS(fl->rx_offset + blen <= rxb->size2); 1809 } else { 1810 MPASS(fl->rx_offset == 0); /* not packing */ 1811 blen = rxb->size1; 1812 len = min(remaining, blen); 1813 payload = sd->cl; 1814 } 1815 1816 if (fr_offset == 0) { 1817 m = m_gethdr(M_NOWAIT, MT_DATA); 1818 if (__predict_false(m == NULL)) 1819 return (NULL); 1820 m->m_pkthdr.len = remaining; 1821 } else { 1822 m = m_get(M_NOWAIT, MT_DATA); 1823 if (__predict_false(m == NULL)) 1824 return (NULL); 1825 } 1826 m->m_len = len; 1827 kmsan_mark(payload, len, KMSAN_STATE_INITED); 1828 1829 if (sc->sc_do_rxcopy && len < RX_COPY_THRESHOLD) { 1830 /* copy data to mbuf */ 1831 bcopy(payload, mtod(m, caddr_t), len); 1832 if (fl->flags & FL_BUF_PACKING) { 1833 fl->rx_offset += blen; 1834 MPASS(fl->rx_offset <= rxb->size2); 1835 if (fl->rx_offset < rxb->size2) 1836 return (m); /* without advancing the cidx */ 1837 } 1838 } else if (fl->flags & FL_BUF_PACKING) { 1839 clm = cl_metadata(sd); 1840 if (sd->nmbuf++ == 0) { 1841 clm->refcount = 1; 1842 clm->zone = rxb->zone; 1843 clm->cl = sd->cl; 1844 counter_u64_add(extfree_refs, 1); 1845 } 1846 m_extaddref(m, payload, blen, &clm->refcount, rxb_free, clm, 1847 NULL); 1848 1849 fl->rx_offset += blen; 1850 MPASS(fl->rx_offset <= rxb->size2); 1851 if (fl->rx_offset < rxb->size2) 1852 return (m); /* without advancing the cidx */ 1853 } else { 1854 m_cljset(m, sd->cl, rxb->type); 1855 sd->cl = NULL; /* consumed, not a recycle candidate */ 1856 } 1857 1858 move_to_next_rxbuf(fl); 1859 1860 return (m); 1861 } 1862 1863 static struct mbuf * 1864 get_fl_payload(struct adapter *sc, struct sge_fl *fl, const u_int plen) 1865 { 1866 struct mbuf *m0, *m, **pnext; 1867 u_int remaining; 1868 1869 if (__predict_false(fl->flags & FL_BUF_RESUME)) { 1870 M_ASSERTPKTHDR(fl->m0); 1871 MPASS(fl->m0->m_pkthdr.len == plen); 1872 MPASS(fl->remaining < plen); 1873 1874 m0 = fl->m0; 1875 pnext = fl->pnext; 1876 remaining = fl->remaining; 1877 fl->flags &= ~FL_BUF_RESUME; 1878 goto get_segment; 1879 } 1880 1881 /* 1882 * Payload starts at rx_offset in the current hw buffer. Its length is 1883 * 'len' and it may span multiple hw buffers. 1884 */ 1885 1886 m0 = get_scatter_segment(sc, fl, 0, plen); 1887 if (m0 == NULL) 1888 return (NULL); 1889 remaining = plen - m0->m_len; 1890 pnext = &m0->m_next; 1891 while (remaining > 0) { 1892 get_segment: 1893 MPASS(fl->rx_offset == 0); 1894 m = get_scatter_segment(sc, fl, plen - remaining, remaining); 1895 if (__predict_false(m == NULL)) { 1896 fl->m0 = m0; 1897 fl->pnext = pnext; 1898 fl->remaining = remaining; 1899 fl->flags |= FL_BUF_RESUME; 1900 return (NULL); 1901 } 1902 *pnext = m; 1903 pnext = &m->m_next; 1904 remaining -= m->m_len; 1905 } 1906 *pnext = NULL; 1907 1908 M_ASSERTPKTHDR(m0); 1909 return (m0); 1910 } 1911 1912 static int 1913 skip_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset, 1914 int remaining) 1915 { 1916 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 1917 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[sd->zidx]; 1918 int len, blen; 1919 1920 if (fl->flags & FL_BUF_PACKING) { 1921 u_int l, pad; 1922 1923 blen = rxb->size2 - fl->rx_offset; /* max possible in this buf */ 1924 len = min(remaining, blen); 1925 1926 l = fr_offset + len; 1927 pad = roundup2(l, fl->buf_boundary) - l; 1928 if (fl->rx_offset + len + pad < rxb->size2) 1929 blen = len + pad; 1930 fl->rx_offset += blen; 1931 MPASS(fl->rx_offset <= rxb->size2); 1932 if (fl->rx_offset < rxb->size2) 1933 return (len); /* without advancing the cidx */ 1934 } else { 1935 MPASS(fl->rx_offset == 0); /* not packing */ 1936 blen = rxb->size1; 1937 len = min(remaining, blen); 1938 } 1939 move_to_next_rxbuf(fl); 1940 return (len); 1941 } 1942 1943 static inline void 1944 skip_fl_payload(struct adapter *sc, struct sge_fl *fl, int plen) 1945 { 1946 int remaining, fr_offset, len; 1947 1948 fr_offset = 0; 1949 remaining = plen; 1950 while (remaining > 0) { 1951 len = skip_scatter_segment(sc, fl, fr_offset, remaining); 1952 fr_offset += len; 1953 remaining -= len; 1954 } 1955 } 1956 1957 static inline int 1958 get_segment_len(struct adapter *sc, struct sge_fl *fl, int plen) 1959 { 1960 int len; 1961 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 1962 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[sd->zidx]; 1963 1964 if (fl->flags & FL_BUF_PACKING) 1965 len = rxb->size2 - fl->rx_offset; 1966 else 1967 len = rxb->size1; 1968 1969 return (min(plen, len)); 1970 } 1971 1972 static int 1973 eth_rx(struct adapter *sc, struct sge_rxq *rxq, const struct iq_desc *d, 1974 u_int plen) 1975 { 1976 struct mbuf *m0; 1977 struct ifnet *ifp = rxq->ifp; 1978 struct sge_fl *fl = &rxq->fl; 1979 struct vi_info *vi = ifp->if_softc; 1980 const struct cpl_rx_pkt *cpl; 1981 #if defined(INET) || defined(INET6) 1982 struct lro_ctrl *lro = &rxq->lro; 1983 #endif 1984 uint16_t err_vec, tnl_type, tnlhdr_len; 1985 static const int sw_hashtype[4][2] = { 1986 {M_HASHTYPE_NONE, M_HASHTYPE_NONE}, 1987 {M_HASHTYPE_RSS_IPV4, M_HASHTYPE_RSS_IPV6}, 1988 {M_HASHTYPE_RSS_TCP_IPV4, M_HASHTYPE_RSS_TCP_IPV6}, 1989 {M_HASHTYPE_RSS_UDP_IPV4, M_HASHTYPE_RSS_UDP_IPV6}, 1990 }; 1991 static const int sw_csum_flags[2][2] = { 1992 { 1993 /* IP, inner IP */ 1994 CSUM_ENCAP_VXLAN | 1995 CSUM_L3_CALC | CSUM_L3_VALID | 1996 CSUM_L4_CALC | CSUM_L4_VALID | 1997 CSUM_INNER_L3_CALC | CSUM_INNER_L3_VALID | 1998 CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID, 1999 2000 /* IP, inner IP6 */ 2001 CSUM_ENCAP_VXLAN | 2002 CSUM_L3_CALC | CSUM_L3_VALID | 2003 CSUM_L4_CALC | CSUM_L4_VALID | 2004 CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID, 2005 }, 2006 { 2007 /* IP6, inner IP */ 2008 CSUM_ENCAP_VXLAN | 2009 CSUM_L4_CALC | CSUM_L4_VALID | 2010 CSUM_INNER_L3_CALC | CSUM_INNER_L3_VALID | 2011 CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID, 2012 2013 /* IP6, inner IP6 */ 2014 CSUM_ENCAP_VXLAN | 2015 CSUM_L4_CALC | CSUM_L4_VALID | 2016 CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID, 2017 }, 2018 }; 2019 2020 MPASS(plen > sc->params.sge.fl_pktshift); 2021 if (vi->pfil != NULL && PFIL_HOOKED_IN(vi->pfil) && 2022 __predict_true((fl->flags & FL_BUF_RESUME) == 0)) { 2023 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 2024 caddr_t frame; 2025 int rc, slen; 2026 2027 slen = get_segment_len(sc, fl, plen) - 2028 sc->params.sge.fl_pktshift; 2029 frame = sd->cl + fl->rx_offset + sc->params.sge.fl_pktshift; 2030 CURVNET_SET_QUIET(ifp->if_vnet); 2031 rc = pfil_run_hooks(vi->pfil, frame, ifp, 2032 slen | PFIL_MEMPTR | PFIL_IN, NULL); 2033 CURVNET_RESTORE(); 2034 if (rc == PFIL_DROPPED || rc == PFIL_CONSUMED) { 2035 skip_fl_payload(sc, fl, plen); 2036 return (0); 2037 } 2038 if (rc == PFIL_REALLOCED) { 2039 skip_fl_payload(sc, fl, plen); 2040 m0 = pfil_mem2mbuf(frame); 2041 goto have_mbuf; 2042 } 2043 } 2044 2045 m0 = get_fl_payload(sc, fl, plen); 2046 if (__predict_false(m0 == NULL)) 2047 return (ENOMEM); 2048 2049 m0->m_pkthdr.len -= sc->params.sge.fl_pktshift; 2050 m0->m_len -= sc->params.sge.fl_pktshift; 2051 m0->m_data += sc->params.sge.fl_pktshift; 2052 2053 have_mbuf: 2054 m0->m_pkthdr.rcvif = ifp; 2055 M_HASHTYPE_SET(m0, sw_hashtype[d->rss.hash_type][d->rss.ipv6]); 2056 m0->m_pkthdr.flowid = be32toh(d->rss.hash_val); 2057 2058 cpl = (const void *)(&d->rss + 1); 2059 if (sc->params.tp.rx_pkt_encap) { 2060 const uint16_t ev = be16toh(cpl->err_vec); 2061 2062 err_vec = G_T6_COMPR_RXERR_VEC(ev); 2063 tnl_type = G_T6_RX_TNL_TYPE(ev); 2064 tnlhdr_len = G_T6_RX_TNLHDR_LEN(ev); 2065 } else { 2066 err_vec = be16toh(cpl->err_vec); 2067 tnl_type = 0; 2068 tnlhdr_len = 0; 2069 } 2070 if (cpl->csum_calc && err_vec == 0) { 2071 int ipv6 = !!(cpl->l2info & htobe32(F_RXF_IP6)); 2072 2073 /* checksum(s) calculated and found to be correct. */ 2074 2075 MPASS((cpl->l2info & htobe32(F_RXF_IP)) ^ 2076 (cpl->l2info & htobe32(F_RXF_IP6))); 2077 m0->m_pkthdr.csum_data = be16toh(cpl->csum); 2078 if (tnl_type == 0) { 2079 if (!ipv6 && ifp->if_capenable & IFCAP_RXCSUM) { 2080 m0->m_pkthdr.csum_flags = CSUM_L3_CALC | 2081 CSUM_L3_VALID | CSUM_L4_CALC | 2082 CSUM_L4_VALID; 2083 } else if (ipv6 && ifp->if_capenable & IFCAP_RXCSUM_IPV6) { 2084 m0->m_pkthdr.csum_flags = CSUM_L4_CALC | 2085 CSUM_L4_VALID; 2086 } 2087 rxq->rxcsum++; 2088 } else { 2089 MPASS(tnl_type == RX_PKT_TNL_TYPE_VXLAN); 2090 2091 M_HASHTYPE_SETINNER(m0); 2092 if (__predict_false(cpl->ip_frag)) { 2093 /* 2094 * csum_data is for the inner frame (which is an 2095 * IP fragment) and is not 0xffff. There is no 2096 * way to pass the inner csum_data to the stack. 2097 * We don't want the stack to use the inner 2098 * csum_data to validate the outer frame or it 2099 * will get rejected. So we fix csum_data here 2100 * and let sw do the checksum of inner IP 2101 * fragments. 2102 * 2103 * XXX: Need 32b for csum_data2 in an rx mbuf. 2104 * Maybe stuff it into rcv_tstmp? 2105 */ 2106 m0->m_pkthdr.csum_data = 0xffff; 2107 if (ipv6) { 2108 m0->m_pkthdr.csum_flags = CSUM_L4_CALC | 2109 CSUM_L4_VALID; 2110 } else { 2111 m0->m_pkthdr.csum_flags = CSUM_L3_CALC | 2112 CSUM_L3_VALID | CSUM_L4_CALC | 2113 CSUM_L4_VALID; 2114 } 2115 } else { 2116 int outer_ipv6; 2117 2118 MPASS(m0->m_pkthdr.csum_data == 0xffff); 2119 2120 outer_ipv6 = tnlhdr_len >= 2121 sizeof(struct ether_header) + 2122 sizeof(struct ip6_hdr); 2123 m0->m_pkthdr.csum_flags = 2124 sw_csum_flags[outer_ipv6][ipv6]; 2125 } 2126 rxq->vxlan_rxcsum++; 2127 } 2128 } 2129 2130 if (cpl->vlan_ex) { 2131 m0->m_pkthdr.ether_vtag = be16toh(cpl->vlan); 2132 m0->m_flags |= M_VLANTAG; 2133 rxq->vlan_extraction++; 2134 } 2135 2136 if (rxq->iq.flags & IQ_RX_TIMESTAMP) { 2137 /* 2138 * Fill up rcv_tstmp but do not set M_TSTMP as 2139 * long as we get a non-zero back from t4_tstmp_to_ns(). 2140 */ 2141 m0->m_pkthdr.rcv_tstmp = t4_tstmp_to_ns(sc, 2142 be64toh(d->rsp.u.last_flit)); 2143 if (m0->m_pkthdr.rcv_tstmp != 0) 2144 m0->m_flags |= M_TSTMP; 2145 } 2146 2147 #ifdef NUMA 2148 m0->m_pkthdr.numa_domain = ifp->if_numa_domain; 2149 #endif 2150 #if defined(INET) || defined(INET6) 2151 if (rxq->iq.flags & IQ_LRO_ENABLED && tnl_type == 0 && 2152 (M_HASHTYPE_GET(m0) == M_HASHTYPE_RSS_TCP_IPV4 || 2153 M_HASHTYPE_GET(m0) == M_HASHTYPE_RSS_TCP_IPV6)) { 2154 if (sort_before_lro(lro)) { 2155 tcp_lro_queue_mbuf(lro, m0); 2156 return (0); /* queued for sort, then LRO */ 2157 } 2158 if (tcp_lro_rx(lro, m0, 0) == 0) 2159 return (0); /* queued for LRO */ 2160 } 2161 #endif 2162 ifp->if_input(ifp, m0); 2163 2164 return (0); 2165 } 2166 2167 /* 2168 * Must drain the wrq or make sure that someone else will. 2169 */ 2170 static void 2171 wrq_tx_drain(void *arg, int n) 2172 { 2173 struct sge_wrq *wrq = arg; 2174 struct sge_eq *eq = &wrq->eq; 2175 2176 EQ_LOCK(eq); 2177 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 2178 drain_wrq_wr_list(wrq->adapter, wrq); 2179 EQ_UNLOCK(eq); 2180 } 2181 2182 static void 2183 drain_wrq_wr_list(struct adapter *sc, struct sge_wrq *wrq) 2184 { 2185 struct sge_eq *eq = &wrq->eq; 2186 u_int available, dbdiff; /* # of hardware descriptors */ 2187 u_int n; 2188 struct wrqe *wr; 2189 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */ 2190 2191 EQ_LOCK_ASSERT_OWNED(eq); 2192 MPASS(TAILQ_EMPTY(&wrq->incomplete_wrs)); 2193 wr = STAILQ_FIRST(&wrq->wr_list); 2194 MPASS(wr != NULL); /* Must be called with something useful to do */ 2195 MPASS(eq->pidx == eq->dbidx); 2196 dbdiff = 0; 2197 2198 do { 2199 eq->cidx = read_hw_cidx(eq); 2200 if (eq->pidx == eq->cidx) 2201 available = eq->sidx - 1; 2202 else 2203 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2204 2205 MPASS(wr->wrq == wrq); 2206 n = howmany(wr->wr_len, EQ_ESIZE); 2207 if (available < n) 2208 break; 2209 2210 dst = (void *)&eq->desc[eq->pidx]; 2211 if (__predict_true(eq->sidx - eq->pidx > n)) { 2212 /* Won't wrap, won't end exactly at the status page. */ 2213 bcopy(&wr->wr[0], dst, wr->wr_len); 2214 eq->pidx += n; 2215 } else { 2216 int first_portion = (eq->sidx - eq->pidx) * EQ_ESIZE; 2217 2218 bcopy(&wr->wr[0], dst, first_portion); 2219 if (wr->wr_len > first_portion) { 2220 bcopy(&wr->wr[first_portion], &eq->desc[0], 2221 wr->wr_len - first_portion); 2222 } 2223 eq->pidx = n - (eq->sidx - eq->pidx); 2224 } 2225 wrq->tx_wrs_copied++; 2226 2227 if (available < eq->sidx / 4 && 2228 atomic_cmpset_int(&eq->equiq, 0, 1)) { 2229 /* 2230 * XXX: This is not 100% reliable with some 2231 * types of WRs. But this is a very unusual 2232 * situation for an ofld/ctrl queue anyway. 2233 */ 2234 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ | 2235 F_FW_WR_EQUEQ); 2236 } 2237 2238 dbdiff += n; 2239 if (dbdiff >= 16) { 2240 ring_eq_db(sc, eq, dbdiff); 2241 dbdiff = 0; 2242 } 2243 2244 STAILQ_REMOVE_HEAD(&wrq->wr_list, link); 2245 free_wrqe(wr); 2246 MPASS(wrq->nwr_pending > 0); 2247 wrq->nwr_pending--; 2248 MPASS(wrq->ndesc_needed >= n); 2249 wrq->ndesc_needed -= n; 2250 } while ((wr = STAILQ_FIRST(&wrq->wr_list)) != NULL); 2251 2252 if (dbdiff) 2253 ring_eq_db(sc, eq, dbdiff); 2254 } 2255 2256 /* 2257 * Doesn't fail. Holds on to work requests it can't send right away. 2258 */ 2259 void 2260 t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, struct wrqe *wr) 2261 { 2262 #ifdef INVARIANTS 2263 struct sge_eq *eq = &wrq->eq; 2264 #endif 2265 2266 EQ_LOCK_ASSERT_OWNED(eq); 2267 MPASS(wr != NULL); 2268 MPASS(wr->wr_len > 0 && wr->wr_len <= SGE_MAX_WR_LEN); 2269 MPASS((wr->wr_len & 0x7) == 0); 2270 2271 STAILQ_INSERT_TAIL(&wrq->wr_list, wr, link); 2272 wrq->nwr_pending++; 2273 wrq->ndesc_needed += howmany(wr->wr_len, EQ_ESIZE); 2274 2275 if (!TAILQ_EMPTY(&wrq->incomplete_wrs)) 2276 return; /* commit_wrq_wr will drain wr_list as well. */ 2277 2278 drain_wrq_wr_list(sc, wrq); 2279 2280 /* Doorbell must have caught up to the pidx. */ 2281 MPASS(eq->pidx == eq->dbidx); 2282 } 2283 2284 void 2285 t4_update_fl_bufsize(struct ifnet *ifp) 2286 { 2287 struct vi_info *vi = ifp->if_softc; 2288 struct adapter *sc = vi->adapter; 2289 struct sge_rxq *rxq; 2290 #ifdef TCP_OFFLOAD 2291 struct sge_ofld_rxq *ofld_rxq; 2292 #endif 2293 struct sge_fl *fl; 2294 int i, maxp; 2295 2296 maxp = max_rx_payload(sc, ifp, false); 2297 for_each_rxq(vi, i, rxq) { 2298 fl = &rxq->fl; 2299 2300 FL_LOCK(fl); 2301 fl->zidx = find_refill_source(sc, maxp, 2302 fl->flags & FL_BUF_PACKING); 2303 FL_UNLOCK(fl); 2304 } 2305 #ifdef TCP_OFFLOAD 2306 maxp = max_rx_payload(sc, ifp, true); 2307 for_each_ofld_rxq(vi, i, ofld_rxq) { 2308 fl = &ofld_rxq->fl; 2309 2310 FL_LOCK(fl); 2311 fl->zidx = find_refill_source(sc, maxp, 2312 fl->flags & FL_BUF_PACKING); 2313 FL_UNLOCK(fl); 2314 } 2315 #endif 2316 } 2317 2318 static inline int 2319 mbuf_nsegs(struct mbuf *m) 2320 { 2321 2322 M_ASSERTPKTHDR(m); 2323 KASSERT(m->m_pkthdr.inner_l5hlen > 0, 2324 ("%s: mbuf %p missing information on # of segments.", __func__, m)); 2325 2326 return (m->m_pkthdr.inner_l5hlen); 2327 } 2328 2329 static inline void 2330 set_mbuf_nsegs(struct mbuf *m, uint8_t nsegs) 2331 { 2332 2333 M_ASSERTPKTHDR(m); 2334 m->m_pkthdr.inner_l5hlen = nsegs; 2335 } 2336 2337 static inline int 2338 mbuf_cflags(struct mbuf *m) 2339 { 2340 2341 M_ASSERTPKTHDR(m); 2342 return (m->m_pkthdr.PH_loc.eight[4]); 2343 } 2344 2345 static inline void 2346 set_mbuf_cflags(struct mbuf *m, uint8_t flags) 2347 { 2348 2349 M_ASSERTPKTHDR(m); 2350 m->m_pkthdr.PH_loc.eight[4] = flags; 2351 } 2352 2353 static inline int 2354 mbuf_len16(struct mbuf *m) 2355 { 2356 int n; 2357 2358 M_ASSERTPKTHDR(m); 2359 n = m->m_pkthdr.PH_loc.eight[0]; 2360 if (!(mbuf_cflags(m) & MC_TLS)) 2361 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16); 2362 2363 return (n); 2364 } 2365 2366 static inline void 2367 set_mbuf_len16(struct mbuf *m, uint8_t len16) 2368 { 2369 2370 M_ASSERTPKTHDR(m); 2371 if (!(mbuf_cflags(m) & MC_TLS)) 2372 MPASS(len16 > 0 && len16 <= SGE_MAX_WR_LEN / 16); 2373 m->m_pkthdr.PH_loc.eight[0] = len16; 2374 } 2375 2376 #ifdef RATELIMIT 2377 static inline int 2378 mbuf_eo_nsegs(struct mbuf *m) 2379 { 2380 2381 M_ASSERTPKTHDR(m); 2382 return (m->m_pkthdr.PH_loc.eight[1]); 2383 } 2384 2385 #if defined(INET) || defined(INET6) 2386 static inline void 2387 set_mbuf_eo_nsegs(struct mbuf *m, uint8_t nsegs) 2388 { 2389 2390 M_ASSERTPKTHDR(m); 2391 m->m_pkthdr.PH_loc.eight[1] = nsegs; 2392 } 2393 #endif 2394 2395 static inline int 2396 mbuf_eo_len16(struct mbuf *m) 2397 { 2398 int n; 2399 2400 M_ASSERTPKTHDR(m); 2401 n = m->m_pkthdr.PH_loc.eight[2]; 2402 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16); 2403 2404 return (n); 2405 } 2406 2407 #if defined(INET) || defined(INET6) 2408 static inline void 2409 set_mbuf_eo_len16(struct mbuf *m, uint8_t len16) 2410 { 2411 2412 M_ASSERTPKTHDR(m); 2413 m->m_pkthdr.PH_loc.eight[2] = len16; 2414 } 2415 #endif 2416 2417 static inline int 2418 mbuf_eo_tsclk_tsoff(struct mbuf *m) 2419 { 2420 2421 M_ASSERTPKTHDR(m); 2422 return (m->m_pkthdr.PH_loc.eight[3]); 2423 } 2424 2425 #if defined(INET) || defined(INET6) 2426 static inline void 2427 set_mbuf_eo_tsclk_tsoff(struct mbuf *m, uint8_t tsclk_tsoff) 2428 { 2429 2430 M_ASSERTPKTHDR(m); 2431 m->m_pkthdr.PH_loc.eight[3] = tsclk_tsoff; 2432 } 2433 #endif 2434 2435 static inline int 2436 needs_eo(struct m_snd_tag *mst) 2437 { 2438 2439 return (mst != NULL && mst->sw->type == IF_SND_TAG_TYPE_RATE_LIMIT); 2440 } 2441 #endif 2442 2443 /* 2444 * Try to allocate an mbuf to contain a raw work request. To make it 2445 * easy to construct the work request, don't allocate a chain but a 2446 * single mbuf. 2447 */ 2448 struct mbuf * 2449 alloc_wr_mbuf(int len, int how) 2450 { 2451 struct mbuf *m; 2452 2453 if (len <= MHLEN) 2454 m = m_gethdr(how, MT_DATA); 2455 else if (len <= MCLBYTES) 2456 m = m_getcl(how, MT_DATA, M_PKTHDR); 2457 else 2458 m = NULL; 2459 if (m == NULL) 2460 return (NULL); 2461 m->m_pkthdr.len = len; 2462 m->m_len = len; 2463 set_mbuf_cflags(m, MC_RAW_WR); 2464 set_mbuf_len16(m, howmany(len, 16)); 2465 return (m); 2466 } 2467 2468 static inline bool 2469 needs_hwcsum(struct mbuf *m) 2470 { 2471 const uint32_t csum_flags = CSUM_IP | CSUM_IP_UDP | CSUM_IP_TCP | 2472 CSUM_IP_TSO | CSUM_INNER_IP | CSUM_INNER_IP_UDP | 2473 CSUM_INNER_IP_TCP | CSUM_INNER_IP_TSO | CSUM_IP6_UDP | 2474 CSUM_IP6_TCP | CSUM_IP6_TSO | CSUM_INNER_IP6_UDP | 2475 CSUM_INNER_IP6_TCP | CSUM_INNER_IP6_TSO; 2476 2477 M_ASSERTPKTHDR(m); 2478 2479 return (m->m_pkthdr.csum_flags & csum_flags); 2480 } 2481 2482 static inline bool 2483 needs_tso(struct mbuf *m) 2484 { 2485 const uint32_t csum_flags = CSUM_IP_TSO | CSUM_IP6_TSO | 2486 CSUM_INNER_IP_TSO | CSUM_INNER_IP6_TSO; 2487 2488 M_ASSERTPKTHDR(m); 2489 2490 return (m->m_pkthdr.csum_flags & csum_flags); 2491 } 2492 2493 static inline bool 2494 needs_vxlan_csum(struct mbuf *m) 2495 { 2496 2497 M_ASSERTPKTHDR(m); 2498 2499 return (m->m_pkthdr.csum_flags & CSUM_ENCAP_VXLAN); 2500 } 2501 2502 static inline bool 2503 needs_vxlan_tso(struct mbuf *m) 2504 { 2505 const uint32_t csum_flags = CSUM_ENCAP_VXLAN | CSUM_INNER_IP_TSO | 2506 CSUM_INNER_IP6_TSO; 2507 2508 M_ASSERTPKTHDR(m); 2509 2510 return ((m->m_pkthdr.csum_flags & csum_flags) != 0 && 2511 (m->m_pkthdr.csum_flags & csum_flags) != CSUM_ENCAP_VXLAN); 2512 } 2513 2514 #if defined(INET) || defined(INET6) 2515 static inline bool 2516 needs_inner_tcp_csum(struct mbuf *m) 2517 { 2518 const uint32_t csum_flags = CSUM_INNER_IP_TSO | CSUM_INNER_IP6_TSO; 2519 2520 M_ASSERTPKTHDR(m); 2521 2522 return (m->m_pkthdr.csum_flags & csum_flags); 2523 } 2524 #endif 2525 2526 static inline bool 2527 needs_l3_csum(struct mbuf *m) 2528 { 2529 const uint32_t csum_flags = CSUM_IP | CSUM_IP_TSO | CSUM_INNER_IP | 2530 CSUM_INNER_IP_TSO; 2531 2532 M_ASSERTPKTHDR(m); 2533 2534 return (m->m_pkthdr.csum_flags & csum_flags); 2535 } 2536 2537 static inline bool 2538 needs_outer_tcp_csum(struct mbuf *m) 2539 { 2540 const uint32_t csum_flags = CSUM_IP_TCP | CSUM_IP_TSO | CSUM_IP6_TCP | 2541 CSUM_IP6_TSO; 2542 2543 M_ASSERTPKTHDR(m); 2544 2545 return (m->m_pkthdr.csum_flags & csum_flags); 2546 } 2547 2548 #ifdef RATELIMIT 2549 static inline bool 2550 needs_outer_l4_csum(struct mbuf *m) 2551 { 2552 const uint32_t csum_flags = CSUM_IP_UDP | CSUM_IP_TCP | CSUM_IP_TSO | 2553 CSUM_IP6_UDP | CSUM_IP6_TCP | CSUM_IP6_TSO; 2554 2555 M_ASSERTPKTHDR(m); 2556 2557 return (m->m_pkthdr.csum_flags & csum_flags); 2558 } 2559 2560 static inline bool 2561 needs_outer_udp_csum(struct mbuf *m) 2562 { 2563 const uint32_t csum_flags = CSUM_IP_UDP | CSUM_IP6_UDP; 2564 2565 M_ASSERTPKTHDR(m); 2566 2567 return (m->m_pkthdr.csum_flags & csum_flags); 2568 } 2569 #endif 2570 2571 static inline bool 2572 needs_vlan_insertion(struct mbuf *m) 2573 { 2574 2575 M_ASSERTPKTHDR(m); 2576 2577 return (m->m_flags & M_VLANTAG); 2578 } 2579 2580 #if defined(INET) || defined(INET6) 2581 static void * 2582 m_advance(struct mbuf **pm, int *poffset, int len) 2583 { 2584 struct mbuf *m = *pm; 2585 int offset = *poffset; 2586 uintptr_t p = 0; 2587 2588 MPASS(len > 0); 2589 2590 for (;;) { 2591 if (offset + len < m->m_len) { 2592 offset += len; 2593 p = mtod(m, uintptr_t) + offset; 2594 break; 2595 } 2596 len -= m->m_len - offset; 2597 m = m->m_next; 2598 offset = 0; 2599 MPASS(m != NULL); 2600 } 2601 *poffset = offset; 2602 *pm = m; 2603 return ((void *)p); 2604 } 2605 #endif 2606 2607 static inline int 2608 count_mbuf_ext_pgs(struct mbuf *m, int skip, vm_paddr_t *nextaddr) 2609 { 2610 vm_paddr_t paddr; 2611 int i, len, off, pglen, pgoff, seglen, segoff; 2612 int nsegs = 0; 2613 2614 M_ASSERTEXTPG(m); 2615 off = mtod(m, vm_offset_t); 2616 len = m->m_len; 2617 off += skip; 2618 len -= skip; 2619 2620 if (m->m_epg_hdrlen != 0) { 2621 if (off >= m->m_epg_hdrlen) { 2622 off -= m->m_epg_hdrlen; 2623 } else { 2624 seglen = m->m_epg_hdrlen - off; 2625 segoff = off; 2626 seglen = min(seglen, len); 2627 off = 0; 2628 len -= seglen; 2629 paddr = pmap_kextract( 2630 (vm_offset_t)&m->m_epg_hdr[segoff]); 2631 if (*nextaddr != paddr) 2632 nsegs++; 2633 *nextaddr = paddr + seglen; 2634 } 2635 } 2636 pgoff = m->m_epg_1st_off; 2637 for (i = 0; i < m->m_epg_npgs && len > 0; i++) { 2638 pglen = m_epg_pagelen(m, i, pgoff); 2639 if (off >= pglen) { 2640 off -= pglen; 2641 pgoff = 0; 2642 continue; 2643 } 2644 seglen = pglen - off; 2645 segoff = pgoff + off; 2646 off = 0; 2647 seglen = min(seglen, len); 2648 len -= seglen; 2649 paddr = m->m_epg_pa[i] + segoff; 2650 if (*nextaddr != paddr) 2651 nsegs++; 2652 *nextaddr = paddr + seglen; 2653 pgoff = 0; 2654 }; 2655 if (len != 0) { 2656 seglen = min(len, m->m_epg_trllen - off); 2657 len -= seglen; 2658 paddr = pmap_kextract((vm_offset_t)&m->m_epg_trail[off]); 2659 if (*nextaddr != paddr) 2660 nsegs++; 2661 *nextaddr = paddr + seglen; 2662 } 2663 2664 return (nsegs); 2665 } 2666 2667 2668 /* 2669 * Can deal with empty mbufs in the chain that have m_len = 0, but the chain 2670 * must have at least one mbuf that's not empty. It is possible for this 2671 * routine to return 0 if skip accounts for all the contents of the mbuf chain. 2672 */ 2673 static inline int 2674 count_mbuf_nsegs(struct mbuf *m, int skip, uint8_t *cflags) 2675 { 2676 vm_paddr_t nextaddr, paddr; 2677 vm_offset_t va; 2678 int len, nsegs; 2679 2680 M_ASSERTPKTHDR(m); 2681 MPASS(m->m_pkthdr.len > 0); 2682 MPASS(m->m_pkthdr.len >= skip); 2683 2684 nsegs = 0; 2685 nextaddr = 0; 2686 for (; m; m = m->m_next) { 2687 len = m->m_len; 2688 if (__predict_false(len == 0)) 2689 continue; 2690 if (skip >= len) { 2691 skip -= len; 2692 continue; 2693 } 2694 if ((m->m_flags & M_EXTPG) != 0) { 2695 *cflags |= MC_NOMAP; 2696 nsegs += count_mbuf_ext_pgs(m, skip, &nextaddr); 2697 skip = 0; 2698 continue; 2699 } 2700 va = mtod(m, vm_offset_t) + skip; 2701 len -= skip; 2702 skip = 0; 2703 paddr = pmap_kextract(va); 2704 nsegs += sglist_count((void *)(uintptr_t)va, len); 2705 if (paddr == nextaddr) 2706 nsegs--; 2707 nextaddr = pmap_kextract(va + len - 1) + 1; 2708 } 2709 2710 return (nsegs); 2711 } 2712 2713 /* 2714 * The maximum number of segments that can fit in a WR. 2715 */ 2716 static int 2717 max_nsegs_allowed(struct mbuf *m, bool vm_wr) 2718 { 2719 2720 if (vm_wr) { 2721 if (needs_tso(m)) 2722 return (TX_SGL_SEGS_VM_TSO); 2723 return (TX_SGL_SEGS_VM); 2724 } 2725 2726 if (needs_tso(m)) { 2727 if (needs_vxlan_tso(m)) 2728 return (TX_SGL_SEGS_VXLAN_TSO); 2729 else 2730 return (TX_SGL_SEGS_TSO); 2731 } 2732 2733 return (TX_SGL_SEGS); 2734 } 2735 2736 static struct timeval txerr_ratecheck = {0}; 2737 static const struct timeval txerr_interval = {3, 0}; 2738 2739 /* 2740 * Analyze the mbuf to determine its tx needs. The mbuf passed in may change: 2741 * a) caller can assume it's been freed if this function returns with an error. 2742 * b) it may get defragged up if the gather list is too long for the hardware. 2743 */ 2744 int 2745 parse_pkt(struct mbuf **mp, bool vm_wr) 2746 { 2747 struct mbuf *m0 = *mp, *m; 2748 int rc, nsegs, defragged = 0; 2749 struct ether_header *eh; 2750 #ifdef INET 2751 void *l3hdr; 2752 #endif 2753 #if defined(INET) || defined(INET6) 2754 int offset; 2755 struct tcphdr *tcp; 2756 #endif 2757 #if defined(KERN_TLS) || defined(RATELIMIT) 2758 struct m_snd_tag *mst; 2759 #endif 2760 uint16_t eh_type; 2761 uint8_t cflags; 2762 2763 cflags = 0; 2764 M_ASSERTPKTHDR(m0); 2765 if (__predict_false(m0->m_pkthdr.len < ETHER_HDR_LEN)) { 2766 rc = EINVAL; 2767 fail: 2768 m_freem(m0); 2769 *mp = NULL; 2770 return (rc); 2771 } 2772 restart: 2773 /* 2774 * First count the number of gather list segments in the payload. 2775 * Defrag the mbuf if nsegs exceeds the hardware limit. 2776 */ 2777 M_ASSERTPKTHDR(m0); 2778 MPASS(m0->m_pkthdr.len > 0); 2779 nsegs = count_mbuf_nsegs(m0, 0, &cflags); 2780 #if defined(KERN_TLS) || defined(RATELIMIT) 2781 if (m0->m_pkthdr.csum_flags & CSUM_SND_TAG) 2782 mst = m0->m_pkthdr.snd_tag; 2783 else 2784 mst = NULL; 2785 #endif 2786 #ifdef KERN_TLS 2787 if (mst != NULL && mst->sw->type == IF_SND_TAG_TYPE_TLS) { 2788 int len16; 2789 2790 cflags |= MC_TLS; 2791 set_mbuf_cflags(m0, cflags); 2792 rc = t6_ktls_parse_pkt(m0, &nsegs, &len16); 2793 if (rc != 0) 2794 goto fail; 2795 set_mbuf_nsegs(m0, nsegs); 2796 set_mbuf_len16(m0, len16); 2797 return (0); 2798 } 2799 #endif 2800 if (nsegs > max_nsegs_allowed(m0, vm_wr)) { 2801 if (defragged++ > 0) { 2802 rc = EFBIG; 2803 goto fail; 2804 } 2805 counter_u64_add(defrags, 1); 2806 if ((m = m_defrag(m0, M_NOWAIT)) == NULL) { 2807 rc = ENOMEM; 2808 goto fail; 2809 } 2810 *mp = m0 = m; /* update caller's copy after defrag */ 2811 goto restart; 2812 } 2813 2814 if (__predict_false(nsegs > 2 && m0->m_pkthdr.len <= MHLEN && 2815 !(cflags & MC_NOMAP))) { 2816 counter_u64_add(pullups, 1); 2817 m0 = m_pullup(m0, m0->m_pkthdr.len); 2818 if (m0 == NULL) { 2819 /* Should have left well enough alone. */ 2820 rc = EFBIG; 2821 goto fail; 2822 } 2823 *mp = m0; /* update caller's copy after pullup */ 2824 goto restart; 2825 } 2826 set_mbuf_nsegs(m0, nsegs); 2827 set_mbuf_cflags(m0, cflags); 2828 calculate_mbuf_len16(m0, vm_wr); 2829 2830 #ifdef RATELIMIT 2831 /* 2832 * Ethofld is limited to TCP and UDP for now, and only when L4 hw 2833 * checksumming is enabled. needs_outer_l4_csum happens to check for 2834 * all the right things. 2835 */ 2836 if (__predict_false(needs_eo(mst) && !needs_outer_l4_csum(m0))) { 2837 m_snd_tag_rele(m0->m_pkthdr.snd_tag); 2838 m0->m_pkthdr.snd_tag = NULL; 2839 m0->m_pkthdr.csum_flags &= ~CSUM_SND_TAG; 2840 mst = NULL; 2841 } 2842 #endif 2843 2844 if (!needs_hwcsum(m0) 2845 #ifdef RATELIMIT 2846 && !needs_eo(mst) 2847 #endif 2848 ) 2849 return (0); 2850 2851 m = m0; 2852 eh = mtod(m, struct ether_header *); 2853 eh_type = ntohs(eh->ether_type); 2854 if (eh_type == ETHERTYPE_VLAN) { 2855 struct ether_vlan_header *evh = (void *)eh; 2856 2857 eh_type = ntohs(evh->evl_proto); 2858 m0->m_pkthdr.l2hlen = sizeof(*evh); 2859 } else 2860 m0->m_pkthdr.l2hlen = sizeof(*eh); 2861 2862 #if defined(INET) || defined(INET6) 2863 offset = 0; 2864 #ifdef INET 2865 l3hdr = m_advance(&m, &offset, m0->m_pkthdr.l2hlen); 2866 #else 2867 m_advance(&m, &offset, m0->m_pkthdr.l2hlen); 2868 #endif 2869 #endif 2870 2871 switch (eh_type) { 2872 #ifdef INET6 2873 case ETHERTYPE_IPV6: 2874 m0->m_pkthdr.l3hlen = sizeof(struct ip6_hdr); 2875 break; 2876 #endif 2877 #ifdef INET 2878 case ETHERTYPE_IP: 2879 { 2880 struct ip *ip = l3hdr; 2881 2882 if (needs_vxlan_csum(m0)) { 2883 /* Driver will do the outer IP hdr checksum. */ 2884 ip->ip_sum = 0; 2885 if (needs_vxlan_tso(m0)) { 2886 const uint16_t ipl = ip->ip_len; 2887 2888 ip->ip_len = 0; 2889 ip->ip_sum = ~in_cksum_hdr(ip); 2890 ip->ip_len = ipl; 2891 } else 2892 ip->ip_sum = in_cksum_hdr(ip); 2893 } 2894 m0->m_pkthdr.l3hlen = ip->ip_hl << 2; 2895 break; 2896 } 2897 #endif 2898 default: 2899 if (ratecheck(&txerr_ratecheck, &txerr_interval)) { 2900 log(LOG_ERR, "%s: ethertype 0x%04x unknown. " 2901 "if_cxgbe must be compiled with the same " 2902 "INET/INET6 options as the kernel.\n", __func__, 2903 eh_type); 2904 } 2905 rc = EINVAL; 2906 goto fail; 2907 } 2908 2909 #if defined(INET) || defined(INET6) 2910 if (needs_vxlan_csum(m0)) { 2911 m0->m_pkthdr.l4hlen = sizeof(struct udphdr); 2912 m0->m_pkthdr.l5hlen = sizeof(struct vxlan_header); 2913 2914 /* Inner headers. */ 2915 eh = m_advance(&m, &offset, m0->m_pkthdr.l3hlen + 2916 sizeof(struct udphdr) + sizeof(struct vxlan_header)); 2917 eh_type = ntohs(eh->ether_type); 2918 if (eh_type == ETHERTYPE_VLAN) { 2919 struct ether_vlan_header *evh = (void *)eh; 2920 2921 eh_type = ntohs(evh->evl_proto); 2922 m0->m_pkthdr.inner_l2hlen = sizeof(*evh); 2923 } else 2924 m0->m_pkthdr.inner_l2hlen = sizeof(*eh); 2925 #ifdef INET 2926 l3hdr = m_advance(&m, &offset, m0->m_pkthdr.inner_l2hlen); 2927 #else 2928 m_advance(&m, &offset, m0->m_pkthdr.inner_l2hlen); 2929 #endif 2930 2931 switch (eh_type) { 2932 #ifdef INET6 2933 case ETHERTYPE_IPV6: 2934 m0->m_pkthdr.inner_l3hlen = sizeof(struct ip6_hdr); 2935 break; 2936 #endif 2937 #ifdef INET 2938 case ETHERTYPE_IP: 2939 { 2940 struct ip *ip = l3hdr; 2941 2942 m0->m_pkthdr.inner_l3hlen = ip->ip_hl << 2; 2943 break; 2944 } 2945 #endif 2946 default: 2947 if (ratecheck(&txerr_ratecheck, &txerr_interval)) { 2948 log(LOG_ERR, "%s: VXLAN hw offload requested" 2949 "with unknown ethertype 0x%04x. if_cxgbe " 2950 "must be compiled with the same INET/INET6 " 2951 "options as the kernel.\n", __func__, 2952 eh_type); 2953 } 2954 rc = EINVAL; 2955 goto fail; 2956 } 2957 if (needs_inner_tcp_csum(m0)) { 2958 tcp = m_advance(&m, &offset, m0->m_pkthdr.inner_l3hlen); 2959 m0->m_pkthdr.inner_l4hlen = tcp->th_off * 4; 2960 } 2961 MPASS((m0->m_pkthdr.csum_flags & CSUM_SND_TAG) == 0); 2962 m0->m_pkthdr.csum_flags &= CSUM_INNER_IP6_UDP | 2963 CSUM_INNER_IP6_TCP | CSUM_INNER_IP6_TSO | CSUM_INNER_IP | 2964 CSUM_INNER_IP_UDP | CSUM_INNER_IP_TCP | CSUM_INNER_IP_TSO | 2965 CSUM_ENCAP_VXLAN; 2966 } 2967 2968 if (needs_outer_tcp_csum(m0)) { 2969 tcp = m_advance(&m, &offset, m0->m_pkthdr.l3hlen); 2970 m0->m_pkthdr.l4hlen = tcp->th_off * 4; 2971 #ifdef RATELIMIT 2972 if (tsclk >= 0 && *(uint32_t *)(tcp + 1) == ntohl(0x0101080a)) { 2973 set_mbuf_eo_tsclk_tsoff(m0, 2974 V_FW_ETH_TX_EO_WR_TSCLK(tsclk) | 2975 V_FW_ETH_TX_EO_WR_TSOFF(sizeof(*tcp) / 2 + 1)); 2976 } else 2977 set_mbuf_eo_tsclk_tsoff(m0, 0); 2978 } else if (needs_outer_udp_csum(m0)) { 2979 m0->m_pkthdr.l4hlen = sizeof(struct udphdr); 2980 #endif 2981 } 2982 #ifdef RATELIMIT 2983 if (needs_eo(mst)) { 2984 u_int immhdrs; 2985 2986 /* EO WRs have the headers in the WR and not the GL. */ 2987 immhdrs = m0->m_pkthdr.l2hlen + m0->m_pkthdr.l3hlen + 2988 m0->m_pkthdr.l4hlen; 2989 cflags = 0; 2990 nsegs = count_mbuf_nsegs(m0, immhdrs, &cflags); 2991 MPASS(cflags == mbuf_cflags(m0)); 2992 set_mbuf_eo_nsegs(m0, nsegs); 2993 set_mbuf_eo_len16(m0, 2994 txpkt_eo_len16(nsegs, immhdrs, needs_tso(m0))); 2995 } 2996 #endif 2997 #endif 2998 MPASS(m0 == *mp); 2999 return (0); 3000 } 3001 3002 void * 3003 start_wrq_wr(struct sge_wrq *wrq, int len16, struct wrq_cookie *cookie) 3004 { 3005 struct sge_eq *eq = &wrq->eq; 3006 struct adapter *sc = wrq->adapter; 3007 int ndesc, available; 3008 struct wrqe *wr; 3009 void *w; 3010 3011 MPASS(len16 > 0); 3012 ndesc = tx_len16_to_desc(len16); 3013 MPASS(ndesc > 0 && ndesc <= SGE_MAX_WR_NDESC); 3014 3015 EQ_LOCK(eq); 3016 3017 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 3018 drain_wrq_wr_list(sc, wrq); 3019 3020 if (!STAILQ_EMPTY(&wrq->wr_list)) { 3021 slowpath: 3022 EQ_UNLOCK(eq); 3023 wr = alloc_wrqe(len16 * 16, wrq); 3024 if (__predict_false(wr == NULL)) 3025 return (NULL); 3026 cookie->pidx = -1; 3027 cookie->ndesc = ndesc; 3028 return (&wr->wr); 3029 } 3030 3031 eq->cidx = read_hw_cidx(eq); 3032 if (eq->pidx == eq->cidx) 3033 available = eq->sidx - 1; 3034 else 3035 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 3036 if (available < ndesc) 3037 goto slowpath; 3038 3039 cookie->pidx = eq->pidx; 3040 cookie->ndesc = ndesc; 3041 TAILQ_INSERT_TAIL(&wrq->incomplete_wrs, cookie, link); 3042 3043 w = &eq->desc[eq->pidx]; 3044 IDXINCR(eq->pidx, ndesc, eq->sidx); 3045 if (__predict_false(cookie->pidx + ndesc > eq->sidx)) { 3046 w = &wrq->ss[0]; 3047 wrq->ss_pidx = cookie->pidx; 3048 wrq->ss_len = len16 * 16; 3049 } 3050 3051 EQ_UNLOCK(eq); 3052 3053 return (w); 3054 } 3055 3056 void 3057 commit_wrq_wr(struct sge_wrq *wrq, void *w, struct wrq_cookie *cookie) 3058 { 3059 struct sge_eq *eq = &wrq->eq; 3060 struct adapter *sc = wrq->adapter; 3061 int ndesc, pidx; 3062 struct wrq_cookie *prev, *next; 3063 3064 if (cookie->pidx == -1) { 3065 struct wrqe *wr = __containerof(w, struct wrqe, wr); 3066 3067 t4_wrq_tx(sc, wr); 3068 return; 3069 } 3070 3071 if (__predict_false(w == &wrq->ss[0])) { 3072 int n = (eq->sidx - wrq->ss_pidx) * EQ_ESIZE; 3073 3074 MPASS(wrq->ss_len > n); /* WR had better wrap around. */ 3075 bcopy(&wrq->ss[0], &eq->desc[wrq->ss_pidx], n); 3076 bcopy(&wrq->ss[n], &eq->desc[0], wrq->ss_len - n); 3077 wrq->tx_wrs_ss++; 3078 } else 3079 wrq->tx_wrs_direct++; 3080 3081 EQ_LOCK(eq); 3082 ndesc = cookie->ndesc; /* Can be more than SGE_MAX_WR_NDESC here. */ 3083 pidx = cookie->pidx; 3084 MPASS(pidx >= 0 && pidx < eq->sidx); 3085 prev = TAILQ_PREV(cookie, wrq_incomplete_wrs, link); 3086 next = TAILQ_NEXT(cookie, link); 3087 if (prev == NULL) { 3088 MPASS(pidx == eq->dbidx); 3089 if (next == NULL || ndesc >= 16) { 3090 int available; 3091 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */ 3092 3093 /* 3094 * Note that the WR via which we'll request tx updates 3095 * is at pidx and not eq->pidx, which has moved on 3096 * already. 3097 */ 3098 dst = (void *)&eq->desc[pidx]; 3099 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 3100 if (available < eq->sidx / 4 && 3101 atomic_cmpset_int(&eq->equiq, 0, 1)) { 3102 /* 3103 * XXX: This is not 100% reliable with some 3104 * types of WRs. But this is a very unusual 3105 * situation for an ofld/ctrl queue anyway. 3106 */ 3107 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ | 3108 F_FW_WR_EQUEQ); 3109 } 3110 3111 ring_eq_db(wrq->adapter, eq, ndesc); 3112 } else { 3113 MPASS(IDXDIFF(next->pidx, pidx, eq->sidx) == ndesc); 3114 next->pidx = pidx; 3115 next->ndesc += ndesc; 3116 } 3117 } else { 3118 MPASS(IDXDIFF(pidx, prev->pidx, eq->sidx) == prev->ndesc); 3119 prev->ndesc += ndesc; 3120 } 3121 TAILQ_REMOVE(&wrq->incomplete_wrs, cookie, link); 3122 3123 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 3124 drain_wrq_wr_list(sc, wrq); 3125 3126 #ifdef INVARIANTS 3127 if (TAILQ_EMPTY(&wrq->incomplete_wrs)) { 3128 /* Doorbell must have caught up to the pidx. */ 3129 MPASS(wrq->eq.pidx == wrq->eq.dbidx); 3130 } 3131 #endif 3132 EQ_UNLOCK(eq); 3133 } 3134 3135 static u_int 3136 can_resume_eth_tx(struct mp_ring *r) 3137 { 3138 struct sge_eq *eq = r->cookie; 3139 3140 return (total_available_tx_desc(eq) > eq->sidx / 8); 3141 } 3142 3143 static inline bool 3144 cannot_use_txpkts(struct mbuf *m) 3145 { 3146 /* maybe put a GL limit too, to avoid silliness? */ 3147 3148 return (needs_tso(m) || (mbuf_cflags(m) & (MC_RAW_WR | MC_TLS)) != 0); 3149 } 3150 3151 static inline int 3152 discard_tx(struct sge_eq *eq) 3153 { 3154 3155 return ((eq->flags & (EQ_ENABLED | EQ_QFLUSH)) != EQ_ENABLED); 3156 } 3157 3158 static inline int 3159 wr_can_update_eq(void *p) 3160 { 3161 struct fw_eth_tx_pkts_wr *wr = p; 3162 3163 switch (G_FW_WR_OP(be32toh(wr->op_pkd))) { 3164 case FW_ULPTX_WR: 3165 case FW_ETH_TX_PKT_WR: 3166 case FW_ETH_TX_PKTS_WR: 3167 case FW_ETH_TX_PKTS2_WR: 3168 case FW_ETH_TX_PKT_VM_WR: 3169 case FW_ETH_TX_PKTS_VM_WR: 3170 return (1); 3171 default: 3172 return (0); 3173 } 3174 } 3175 3176 static inline void 3177 set_txupdate_flags(struct sge_txq *txq, u_int avail, 3178 struct fw_eth_tx_pkt_wr *wr) 3179 { 3180 struct sge_eq *eq = &txq->eq; 3181 struct txpkts *txp = &txq->txp; 3182 3183 if ((txp->npkt > 0 || avail < eq->sidx / 2) && 3184 atomic_cmpset_int(&eq->equiq, 0, 1)) { 3185 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ | F_FW_WR_EQUIQ); 3186 eq->equeqidx = eq->pidx; 3187 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 32) { 3188 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ); 3189 eq->equeqidx = eq->pidx; 3190 } 3191 } 3192 3193 #if defined(__i386__) || defined(__amd64__) 3194 extern uint64_t tsc_freq; 3195 #endif 3196 3197 static inline bool 3198 record_eth_tx_time(struct sge_txq *txq) 3199 { 3200 const uint64_t cycles = get_cyclecount(); 3201 const uint64_t last_tx = txq->last_tx; 3202 #if defined(__i386__) || defined(__amd64__) 3203 const uint64_t itg = tsc_freq * t4_tx_coalesce_gap / 1000000; 3204 #else 3205 const uint64_t itg = 0; 3206 #endif 3207 3208 MPASS(cycles >= last_tx); 3209 txq->last_tx = cycles; 3210 return (cycles - last_tx < itg); 3211 } 3212 3213 /* 3214 * r->items[cidx] to r->items[pidx], with a wraparound at r->size, are ready to 3215 * be consumed. Return the actual number consumed. 0 indicates a stall. 3216 */ 3217 static u_int 3218 eth_tx(struct mp_ring *r, u_int cidx, u_int pidx, bool *coalescing) 3219 { 3220 struct sge_txq *txq = r->cookie; 3221 struct ifnet *ifp = txq->ifp; 3222 struct sge_eq *eq = &txq->eq; 3223 struct txpkts *txp = &txq->txp; 3224 struct vi_info *vi = ifp->if_softc; 3225 struct adapter *sc = vi->adapter; 3226 u_int total, remaining; /* # of packets */ 3227 u_int n, avail, dbdiff; /* # of hardware descriptors */ 3228 int i, rc; 3229 struct mbuf *m0; 3230 bool snd, recent_tx; 3231 void *wr; /* start of the last WR written to the ring */ 3232 3233 TXQ_LOCK_ASSERT_OWNED(txq); 3234 recent_tx = record_eth_tx_time(txq); 3235 3236 remaining = IDXDIFF(pidx, cidx, r->size); 3237 if (__predict_false(discard_tx(eq))) { 3238 for (i = 0; i < txp->npkt; i++) 3239 m_freem(txp->mb[i]); 3240 txp->npkt = 0; 3241 while (cidx != pidx) { 3242 m0 = r->items[cidx]; 3243 m_freem(m0); 3244 if (++cidx == r->size) 3245 cidx = 0; 3246 } 3247 reclaim_tx_descs(txq, eq->sidx); 3248 *coalescing = false; 3249 return (remaining); /* emptied */ 3250 } 3251 3252 /* How many hardware descriptors do we have readily available. */ 3253 if (eq->pidx == eq->cidx) 3254 avail = eq->sidx - 1; 3255 else 3256 avail = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 3257 3258 total = 0; 3259 if (remaining == 0) { 3260 txp->score = 0; 3261 txq->txpkts_flush++; 3262 goto send_txpkts; 3263 } 3264 3265 dbdiff = 0; 3266 MPASS(remaining > 0); 3267 while (remaining > 0) { 3268 m0 = r->items[cidx]; 3269 M_ASSERTPKTHDR(m0); 3270 MPASS(m0->m_nextpkt == NULL); 3271 3272 if (avail < 2 * SGE_MAX_WR_NDESC) 3273 avail += reclaim_tx_descs(txq, 64); 3274 3275 if (t4_tx_coalesce == 0 && txp->npkt == 0) 3276 goto skip_coalescing; 3277 if (cannot_use_txpkts(m0)) 3278 txp->score = 0; 3279 else if (recent_tx) { 3280 if (++txp->score == 0) 3281 txp->score = UINT8_MAX; 3282 } else 3283 txp->score = 1; 3284 if (txp->npkt > 0 || remaining > 1 || 3285 txp->score >= t4_tx_coalesce_pkts || 3286 atomic_load_int(&txq->eq.equiq) != 0) { 3287 if (vi->flags & TX_USES_VM_WR) 3288 rc = add_to_txpkts_vf(sc, txq, m0, avail, &snd); 3289 else 3290 rc = add_to_txpkts_pf(sc, txq, m0, avail, &snd); 3291 } else { 3292 snd = false; 3293 rc = EINVAL; 3294 } 3295 if (snd) { 3296 MPASS(txp->npkt > 0); 3297 for (i = 0; i < txp->npkt; i++) 3298 ETHER_BPF_MTAP(ifp, txp->mb[i]); 3299 if (txp->npkt > 1) { 3300 MPASS(avail >= tx_len16_to_desc(txp->len16)); 3301 if (vi->flags & TX_USES_VM_WR) 3302 n = write_txpkts_vm_wr(sc, txq); 3303 else 3304 n = write_txpkts_wr(sc, txq); 3305 } else { 3306 MPASS(avail >= 3307 tx_len16_to_desc(mbuf_len16(txp->mb[0]))); 3308 if (vi->flags & TX_USES_VM_WR) 3309 n = write_txpkt_vm_wr(sc, txq, 3310 txp->mb[0]); 3311 else 3312 n = write_txpkt_wr(sc, txq, txp->mb[0], 3313 avail); 3314 } 3315 MPASS(n <= SGE_MAX_WR_NDESC); 3316 avail -= n; 3317 dbdiff += n; 3318 wr = &eq->desc[eq->pidx]; 3319 IDXINCR(eq->pidx, n, eq->sidx); 3320 txp->npkt = 0; /* emptied */ 3321 } 3322 if (rc == 0) { 3323 /* m0 was coalesced into txq->txpkts. */ 3324 goto next_mbuf; 3325 } 3326 if (rc == EAGAIN) { 3327 /* 3328 * m0 is suitable for tx coalescing but could not be 3329 * combined with the existing txq->txpkts, which has now 3330 * been transmitted. Start a new txpkts with m0. 3331 */ 3332 MPASS(snd); 3333 MPASS(txp->npkt == 0); 3334 continue; 3335 } 3336 3337 MPASS(rc != 0 && rc != EAGAIN); 3338 MPASS(txp->npkt == 0); 3339 skip_coalescing: 3340 n = tx_len16_to_desc(mbuf_len16(m0)); 3341 if (__predict_false(avail < n)) { 3342 avail += reclaim_tx_descs(txq, min(n, 32)); 3343 if (avail < n) 3344 break; /* out of descriptors */ 3345 } 3346 3347 wr = &eq->desc[eq->pidx]; 3348 if (mbuf_cflags(m0) & MC_RAW_WR) { 3349 n = write_raw_wr(txq, wr, m0, avail); 3350 #ifdef KERN_TLS 3351 } else if (mbuf_cflags(m0) & MC_TLS) { 3352 ETHER_BPF_MTAP(ifp, m0); 3353 n = t6_ktls_write_wr(txq, wr, m0, mbuf_nsegs(m0), 3354 avail); 3355 #endif 3356 } else { 3357 ETHER_BPF_MTAP(ifp, m0); 3358 if (vi->flags & TX_USES_VM_WR) 3359 n = write_txpkt_vm_wr(sc, txq, m0); 3360 else 3361 n = write_txpkt_wr(sc, txq, m0, avail); 3362 } 3363 MPASS(n >= 1 && n <= avail); 3364 if (!(mbuf_cflags(m0) & MC_TLS)) 3365 MPASS(n <= SGE_MAX_WR_NDESC); 3366 3367 avail -= n; 3368 dbdiff += n; 3369 IDXINCR(eq->pidx, n, eq->sidx); 3370 3371 if (dbdiff >= 512 / EQ_ESIZE) { /* X_FETCHBURSTMAX_512B */ 3372 if (wr_can_update_eq(wr)) 3373 set_txupdate_flags(txq, avail, wr); 3374 ring_eq_db(sc, eq, dbdiff); 3375 avail += reclaim_tx_descs(txq, 32); 3376 dbdiff = 0; 3377 } 3378 next_mbuf: 3379 total++; 3380 remaining--; 3381 if (__predict_false(++cidx == r->size)) 3382 cidx = 0; 3383 } 3384 if (dbdiff != 0) { 3385 if (wr_can_update_eq(wr)) 3386 set_txupdate_flags(txq, avail, wr); 3387 ring_eq_db(sc, eq, dbdiff); 3388 reclaim_tx_descs(txq, 32); 3389 } else if (eq->pidx == eq->cidx && txp->npkt > 0 && 3390 atomic_load_int(&txq->eq.equiq) == 0) { 3391 /* 3392 * If nothing was submitted to the chip for tx (it was coalesced 3393 * into txpkts instead) and there is no tx update outstanding 3394 * then we need to send txpkts now. 3395 */ 3396 send_txpkts: 3397 MPASS(txp->npkt > 0); 3398 for (i = 0; i < txp->npkt; i++) 3399 ETHER_BPF_MTAP(ifp, txp->mb[i]); 3400 if (txp->npkt > 1) { 3401 MPASS(avail >= tx_len16_to_desc(txp->len16)); 3402 if (vi->flags & TX_USES_VM_WR) 3403 n = write_txpkts_vm_wr(sc, txq); 3404 else 3405 n = write_txpkts_wr(sc, txq); 3406 } else { 3407 MPASS(avail >= 3408 tx_len16_to_desc(mbuf_len16(txp->mb[0]))); 3409 if (vi->flags & TX_USES_VM_WR) 3410 n = write_txpkt_vm_wr(sc, txq, txp->mb[0]); 3411 else 3412 n = write_txpkt_wr(sc, txq, txp->mb[0], avail); 3413 } 3414 MPASS(n <= SGE_MAX_WR_NDESC); 3415 wr = &eq->desc[eq->pidx]; 3416 IDXINCR(eq->pidx, n, eq->sidx); 3417 txp->npkt = 0; /* emptied */ 3418 3419 MPASS(wr_can_update_eq(wr)); 3420 set_txupdate_flags(txq, avail - n, wr); 3421 ring_eq_db(sc, eq, n); 3422 reclaim_tx_descs(txq, 32); 3423 } 3424 *coalescing = txp->npkt > 0; 3425 3426 return (total); 3427 } 3428 3429 static inline void 3430 init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int pktc_idx, 3431 int qsize, int intr_idx, int cong, int qtype) 3432 { 3433 3434 KASSERT(tmr_idx >= 0 && tmr_idx < SGE_NTIMERS, 3435 ("%s: bad tmr_idx %d", __func__, tmr_idx)); 3436 KASSERT(pktc_idx < SGE_NCOUNTERS, /* -ve is ok, means don't use */ 3437 ("%s: bad pktc_idx %d", __func__, pktc_idx)); 3438 KASSERT(intr_idx >= -1 && intr_idx < sc->intr_count, 3439 ("%s: bad intr_idx %d", __func__, intr_idx)); 3440 KASSERT(qtype == FW_IQ_IQTYPE_OTHER || qtype == FW_IQ_IQTYPE_NIC || 3441 qtype == FW_IQ_IQTYPE_OFLD, ("%s: bad qtype %d", __func__, qtype)); 3442 3443 iq->flags = 0; 3444 iq->state = IQS_DISABLED; 3445 iq->adapter = sc; 3446 iq->qtype = qtype; 3447 iq->intr_params = V_QINTR_TIMER_IDX(tmr_idx); 3448 iq->intr_pktc_idx = SGE_NCOUNTERS - 1; 3449 if (pktc_idx >= 0) { 3450 iq->intr_params |= F_QINTR_CNT_EN; 3451 iq->intr_pktc_idx = pktc_idx; 3452 } 3453 iq->qsize = roundup2(qsize, 16); /* See FW_IQ_CMD/iqsize */ 3454 iq->sidx = iq->qsize - sc->params.sge.spg_len / IQ_ESIZE; 3455 iq->intr_idx = intr_idx; 3456 iq->cong_drop = cong; 3457 } 3458 3459 static inline void 3460 init_fl(struct adapter *sc, struct sge_fl *fl, int qsize, int maxp, char *name) 3461 { 3462 struct sge_params *sp = &sc->params.sge; 3463 3464 fl->qsize = qsize; 3465 fl->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE; 3466 strlcpy(fl->lockname, name, sizeof(fl->lockname)); 3467 mtx_init(&fl->fl_lock, fl->lockname, NULL, MTX_DEF); 3468 if (sc->flags & BUF_PACKING_OK && 3469 ((!is_t4(sc) && buffer_packing) || /* T5+: enabled unless 0 */ 3470 (is_t4(sc) && buffer_packing == 1)))/* T4: disabled unless 1 */ 3471 fl->flags |= FL_BUF_PACKING; 3472 fl->zidx = find_refill_source(sc, maxp, fl->flags & FL_BUF_PACKING); 3473 fl->safe_zidx = sc->sge.safe_zidx; 3474 if (fl->flags & FL_BUF_PACKING) { 3475 fl->lowat = roundup2(sp->fl_starve_threshold2, 8); 3476 fl->buf_boundary = sp->pack_boundary; 3477 } else { 3478 fl->lowat = roundup2(sp->fl_starve_threshold, 8); 3479 fl->buf_boundary = 16; 3480 } 3481 if (fl_pad && fl->buf_boundary < sp->pad_boundary) 3482 fl->buf_boundary = sp->pad_boundary; 3483 } 3484 3485 static inline void 3486 init_eq(struct adapter *sc, struct sge_eq *eq, int eqtype, int qsize, 3487 uint8_t tx_chan, struct sge_iq *iq, char *name) 3488 { 3489 KASSERT(eqtype >= EQ_CTRL && eqtype <= EQ_OFLD, 3490 ("%s: bad qtype %d", __func__, eqtype)); 3491 3492 eq->type = eqtype; 3493 eq->tx_chan = tx_chan; 3494 eq->iq = iq; 3495 eq->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE; 3496 strlcpy(eq->lockname, name, sizeof(eq->lockname)); 3497 mtx_init(&eq->eq_lock, eq->lockname, NULL, MTX_DEF); 3498 } 3499 3500 int 3501 alloc_ring(struct adapter *sc, size_t len, bus_dma_tag_t *tag, 3502 bus_dmamap_t *map, bus_addr_t *pa, void **va) 3503 { 3504 int rc; 3505 3506 rc = bus_dma_tag_create(sc->dmat, 512, 0, BUS_SPACE_MAXADDR, 3507 BUS_SPACE_MAXADDR, NULL, NULL, len, 1, len, 0, NULL, NULL, tag); 3508 if (rc != 0) { 3509 CH_ERR(sc, "cannot allocate DMA tag: %d\n", rc); 3510 goto done; 3511 } 3512 3513 rc = bus_dmamem_alloc(*tag, va, 3514 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, map); 3515 if (rc != 0) { 3516 CH_ERR(sc, "cannot allocate DMA memory: %d\n", rc); 3517 goto done; 3518 } 3519 3520 rc = bus_dmamap_load(*tag, *map, *va, len, oneseg_dma_callback, pa, 0); 3521 if (rc != 0) { 3522 CH_ERR(sc, "cannot load DMA map: %d\n", rc); 3523 goto done; 3524 } 3525 done: 3526 if (rc) 3527 free_ring(sc, *tag, *map, *pa, *va); 3528 3529 return (rc); 3530 } 3531 3532 int 3533 free_ring(struct adapter *sc, bus_dma_tag_t tag, bus_dmamap_t map, 3534 bus_addr_t pa, void *va) 3535 { 3536 if (pa) 3537 bus_dmamap_unload(tag, map); 3538 if (va) 3539 bus_dmamem_free(tag, va, map); 3540 if (tag) 3541 bus_dma_tag_destroy(tag); 3542 3543 return (0); 3544 } 3545 3546 /* 3547 * Allocates the software resources (mainly memory and sysctl nodes) for an 3548 * ingress queue and an optional freelist. 3549 * 3550 * Sets IQ_SW_ALLOCATED and returns 0 on success. 3551 */ 3552 static int 3553 alloc_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl, 3554 struct sysctl_ctx_list *ctx, struct sysctl_oid *oid) 3555 { 3556 int rc; 3557 size_t len; 3558 struct adapter *sc = vi->adapter; 3559 3560 MPASS(!(iq->flags & IQ_SW_ALLOCATED)); 3561 3562 len = iq->qsize * IQ_ESIZE; 3563 rc = alloc_ring(sc, len, &iq->desc_tag, &iq->desc_map, &iq->ba, 3564 (void **)&iq->desc); 3565 if (rc != 0) 3566 return (rc); 3567 3568 if (fl) { 3569 len = fl->qsize * EQ_ESIZE; 3570 rc = alloc_ring(sc, len, &fl->desc_tag, &fl->desc_map, 3571 &fl->ba, (void **)&fl->desc); 3572 if (rc) { 3573 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, 3574 iq->desc); 3575 return (rc); 3576 } 3577 3578 /* Allocate space for one software descriptor per buffer. */ 3579 fl->sdesc = malloc(fl->sidx * 8 * sizeof(struct fl_sdesc), 3580 M_CXGBE, M_ZERO | M_WAITOK); 3581 3582 add_fl_sysctls(sc, ctx, oid, fl); 3583 iq->flags |= IQ_HAS_FL; 3584 } 3585 add_iq_sysctls(ctx, oid, iq); 3586 iq->flags |= IQ_SW_ALLOCATED; 3587 3588 return (0); 3589 } 3590 3591 /* 3592 * Frees all software resources (memory and locks) associated with an ingress 3593 * queue and an optional freelist. 3594 */ 3595 static void 3596 free_iq_fl(struct adapter *sc, struct sge_iq *iq, struct sge_fl *fl) 3597 { 3598 MPASS(iq->flags & IQ_SW_ALLOCATED); 3599 3600 if (fl) { 3601 MPASS(iq->flags & IQ_HAS_FL); 3602 free_ring(sc, fl->desc_tag, fl->desc_map, fl->ba, fl->desc); 3603 free_fl_buffers(sc, fl); 3604 free(fl->sdesc, M_CXGBE); 3605 mtx_destroy(&fl->fl_lock); 3606 bzero(fl, sizeof(*fl)); 3607 } 3608 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, iq->desc); 3609 bzero(iq, sizeof(*iq)); 3610 } 3611 3612 /* 3613 * Allocates a hardware ingress queue and an optional freelist that will be 3614 * associated with it. 3615 * 3616 * Returns errno on failure. Resources allocated up to that point may still be 3617 * allocated. Caller is responsible for cleanup in case this function fails. 3618 */ 3619 static int 3620 alloc_iq_fl_hwq(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl) 3621 { 3622 int rc, cntxt_id, cong_map; 3623 struct fw_iq_cmd c; 3624 struct adapter *sc = vi->adapter; 3625 struct port_info *pi = vi->pi; 3626 __be32 v = 0; 3627 3628 MPASS (!(iq->flags & IQ_HW_ALLOCATED)); 3629 3630 bzero(&c, sizeof(c)); 3631 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 3632 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) | 3633 V_FW_IQ_CMD_VFN(0)); 3634 3635 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART | 3636 FW_LEN16(c)); 3637 3638 /* Special handling for firmware event queue */ 3639 if (iq == &sc->sge.fwq) 3640 v |= F_FW_IQ_CMD_IQASYNCH; 3641 3642 if (iq->intr_idx < 0) { 3643 /* Forwarded interrupts, all headed to fwq */ 3644 v |= F_FW_IQ_CMD_IQANDST; 3645 v |= V_FW_IQ_CMD_IQANDSTINDEX(sc->sge.fwq.cntxt_id); 3646 } else { 3647 KASSERT(iq->intr_idx < sc->intr_count, 3648 ("%s: invalid direct intr_idx %d", __func__, iq->intr_idx)); 3649 v |= V_FW_IQ_CMD_IQANDSTINDEX(iq->intr_idx); 3650 } 3651 3652 bzero(iq->desc, iq->qsize * IQ_ESIZE); 3653 c.type_to_iqandstindex = htobe32(v | 3654 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) | 3655 V_FW_IQ_CMD_VIID(vi->viid) | 3656 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT)); 3657 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->tx_chan) | 3658 F_FW_IQ_CMD_IQGTSMODE | 3659 V_FW_IQ_CMD_IQINTCNTTHRESH(iq->intr_pktc_idx) | 3660 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4)); 3661 c.iqsize = htobe16(iq->qsize); 3662 c.iqaddr = htobe64(iq->ba); 3663 c.iqns_to_fl0congen = htobe32(V_FW_IQ_CMD_IQTYPE(iq->qtype)); 3664 if (iq->cong_drop != -1) { 3665 cong_map = iq->qtype == IQ_ETH ? pi->rx_e_chan_map : 0; 3666 c.iqns_to_fl0congen |= htobe32(F_FW_IQ_CMD_IQFLINTCONGEN); 3667 } 3668 3669 if (fl) { 3670 bzero(fl->desc, fl->sidx * EQ_ESIZE + sc->params.sge.spg_len); 3671 c.iqns_to_fl0congen |= 3672 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) | 3673 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO | 3674 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) | 3675 (fl->flags & FL_BUF_PACKING ? F_FW_IQ_CMD_FL0PACKEN : 3676 0)); 3677 if (iq->cong_drop != -1) { 3678 c.iqns_to_fl0congen |= 3679 htobe32(V_FW_IQ_CMD_FL0CNGCHMAP(cong_map) | 3680 F_FW_IQ_CMD_FL0CONGCIF | 3681 F_FW_IQ_CMD_FL0CONGEN); 3682 } 3683 c.fl0dcaen_to_fl0cidxfthresh = 3684 htobe16(V_FW_IQ_CMD_FL0FBMIN(chip_id(sc) <= CHELSIO_T5 ? 3685 X_FETCHBURSTMIN_128B : X_FETCHBURSTMIN_64B_T6) | 3686 V_FW_IQ_CMD_FL0FBMAX(chip_id(sc) <= CHELSIO_T5 ? 3687 X_FETCHBURSTMAX_512B : X_FETCHBURSTMAX_256B)); 3688 c.fl0size = htobe16(fl->qsize); 3689 c.fl0addr = htobe64(fl->ba); 3690 } 3691 3692 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3693 if (rc != 0) { 3694 CH_ERR(sc, "failed to create hw ingress queue: %d\n", rc); 3695 return (rc); 3696 } 3697 3698 iq->cidx = 0; 3699 iq->gen = F_RSPD_GEN; 3700 iq->cntxt_id = be16toh(c.iqid); 3701 iq->abs_id = be16toh(c.physiqid); 3702 3703 cntxt_id = iq->cntxt_id - sc->sge.iq_start; 3704 if (cntxt_id >= sc->sge.iqmap_sz) { 3705 panic ("%s: iq->cntxt_id (%d) more than the max (%d)", __func__, 3706 cntxt_id, sc->sge.iqmap_sz - 1); 3707 } 3708 sc->sge.iqmap[cntxt_id] = iq; 3709 3710 if (fl) { 3711 u_int qid; 3712 #ifdef INVARIANTS 3713 int i; 3714 3715 MPASS(!(fl->flags & FL_BUF_RESUME)); 3716 for (i = 0; i < fl->sidx * 8; i++) 3717 MPASS(fl->sdesc[i].cl == NULL); 3718 #endif 3719 fl->cntxt_id = be16toh(c.fl0id); 3720 fl->pidx = fl->cidx = fl->hw_cidx = fl->dbidx = 0; 3721 fl->rx_offset = 0; 3722 fl->flags &= ~(FL_STARVING | FL_DOOMED); 3723 3724 cntxt_id = fl->cntxt_id - sc->sge.eq_start; 3725 if (cntxt_id >= sc->sge.eqmap_sz) { 3726 panic("%s: fl->cntxt_id (%d) more than the max (%d)", 3727 __func__, cntxt_id, sc->sge.eqmap_sz - 1); 3728 } 3729 sc->sge.eqmap[cntxt_id] = (void *)fl; 3730 3731 qid = fl->cntxt_id; 3732 if (isset(&sc->doorbells, DOORBELL_UDB)) { 3733 uint32_t s_qpp = sc->params.sge.eq_s_qpp; 3734 uint32_t mask = (1 << s_qpp) - 1; 3735 volatile uint8_t *udb; 3736 3737 udb = sc->udbs_base + UDBS_DB_OFFSET; 3738 udb += (qid >> s_qpp) << PAGE_SHIFT; 3739 qid &= mask; 3740 if (qid < PAGE_SIZE / UDBS_SEG_SIZE) { 3741 udb += qid << UDBS_SEG_SHIFT; 3742 qid = 0; 3743 } 3744 fl->udb = (volatile void *)udb; 3745 } 3746 fl->dbval = V_QID(qid) | sc->chip_params->sge_fl_db; 3747 3748 FL_LOCK(fl); 3749 /* Enough to make sure the SGE doesn't think it's starved */ 3750 refill_fl(sc, fl, fl->lowat); 3751 FL_UNLOCK(fl); 3752 } 3753 3754 if (chip_id(sc) >= CHELSIO_T5 && !(sc->flags & IS_VF) && 3755 iq->cong_drop != -1) { 3756 t4_sge_set_conm_context(sc, iq->cntxt_id, iq->cong_drop, 3757 cong_map); 3758 } 3759 3760 /* Enable IQ interrupts */ 3761 atomic_store_rel_int(&iq->state, IQS_IDLE); 3762 t4_write_reg(sc, sc->sge_gts_reg, V_SEINTARM(iq->intr_params) | 3763 V_INGRESSQID(iq->cntxt_id)); 3764 3765 iq->flags |= IQ_HW_ALLOCATED; 3766 3767 return (0); 3768 } 3769 3770 static int 3771 free_iq_fl_hwq(struct adapter *sc, struct sge_iq *iq, struct sge_fl *fl) 3772 { 3773 int rc; 3774 3775 MPASS(iq->flags & IQ_HW_ALLOCATED); 3776 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0, FW_IQ_TYPE_FL_INT_CAP, 3777 iq->cntxt_id, fl ? fl->cntxt_id : 0xffff, 0xffff); 3778 if (rc != 0) { 3779 CH_ERR(sc, "failed to free iq %p: %d\n", iq, rc); 3780 return (rc); 3781 } 3782 iq->flags &= ~IQ_HW_ALLOCATED; 3783 3784 return (0); 3785 } 3786 3787 static void 3788 add_iq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid, 3789 struct sge_iq *iq) 3790 { 3791 struct sysctl_oid_list *children; 3792 3793 if (ctx == NULL || oid == NULL) 3794 return; 3795 3796 children = SYSCTL_CHILDREN(oid); 3797 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, &iq->ba, 3798 "bus address of descriptor ring"); 3799 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3800 iq->qsize * IQ_ESIZE, "descriptor ring size in bytes"); 3801 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "abs_id", CTLFLAG_RD, 3802 &iq->abs_id, 0, "absolute id of the queue"); 3803 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 3804 &iq->cntxt_id, 0, "SGE context id of the queue"); 3805 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &iq->cidx, 3806 0, "consumer index"); 3807 } 3808 3809 static void 3810 add_fl_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx, 3811 struct sysctl_oid *oid, struct sge_fl *fl) 3812 { 3813 struct sysctl_oid_list *children; 3814 3815 if (ctx == NULL || oid == NULL) 3816 return; 3817 3818 children = SYSCTL_CHILDREN(oid); 3819 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", 3820 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "freelist"); 3821 children = SYSCTL_CHILDREN(oid); 3822 3823 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, 3824 &fl->ba, "bus address of descriptor ring"); 3825 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3826 fl->sidx * EQ_ESIZE + sc->params.sge.spg_len, 3827 "desc ring size in bytes"); 3828 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 3829 &fl->cntxt_id, 0, "SGE context id of the freelist"); 3830 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "padding", CTLFLAG_RD, NULL, 3831 fl_pad ? 1 : 0, "padding enabled"); 3832 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "packing", CTLFLAG_RD, NULL, 3833 fl->flags & FL_BUF_PACKING ? 1 : 0, "packing enabled"); 3834 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &fl->cidx, 3835 0, "consumer index"); 3836 if (fl->flags & FL_BUF_PACKING) { 3837 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rx_offset", 3838 CTLFLAG_RD, &fl->rx_offset, 0, "packing rx offset"); 3839 } 3840 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &fl->pidx, 3841 0, "producer index"); 3842 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_allocated", 3843 CTLFLAG_RD, &fl->cl_allocated, "# of clusters allocated"); 3844 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_recycled", 3845 CTLFLAG_RD, &fl->cl_recycled, "# of clusters recycled"); 3846 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_fast_recycled", 3847 CTLFLAG_RD, &fl->cl_fast_recycled, "# of clusters recycled (fast)"); 3848 } 3849 3850 /* 3851 * Idempotent. 3852 */ 3853 static int 3854 alloc_fwq(struct adapter *sc) 3855 { 3856 int rc, intr_idx; 3857 struct sge_iq *fwq = &sc->sge.fwq; 3858 struct vi_info *vi = &sc->port[0]->vi[0]; 3859 3860 if (!(fwq->flags & IQ_SW_ALLOCATED)) { 3861 MPASS(!(fwq->flags & IQ_HW_ALLOCATED)); 3862 3863 if (sc->flags & IS_VF) 3864 intr_idx = 0; 3865 else 3866 intr_idx = sc->intr_count > 1 ? 1 : 0; 3867 init_iq(fwq, sc, 0, 0, FW_IQ_QSIZE, intr_idx, -1, IQ_OTHER); 3868 rc = alloc_iq_fl(vi, fwq, NULL, &sc->ctx, sc->fwq_oid); 3869 if (rc != 0) { 3870 CH_ERR(sc, "failed to allocate fwq: %d\n", rc); 3871 return (rc); 3872 } 3873 MPASS(fwq->flags & IQ_SW_ALLOCATED); 3874 } 3875 3876 if (!(fwq->flags & IQ_HW_ALLOCATED)) { 3877 MPASS(fwq->flags & IQ_SW_ALLOCATED); 3878 3879 rc = alloc_iq_fl_hwq(vi, fwq, NULL); 3880 if (rc != 0) { 3881 CH_ERR(sc, "failed to create hw fwq: %d\n", rc); 3882 return (rc); 3883 } 3884 MPASS(fwq->flags & IQ_HW_ALLOCATED); 3885 } 3886 3887 return (0); 3888 } 3889 3890 /* 3891 * Idempotent. 3892 */ 3893 static void 3894 free_fwq(struct adapter *sc) 3895 { 3896 struct sge_iq *fwq = &sc->sge.fwq; 3897 3898 if (fwq->flags & IQ_HW_ALLOCATED) { 3899 MPASS(fwq->flags & IQ_SW_ALLOCATED); 3900 free_iq_fl_hwq(sc, fwq, NULL); 3901 MPASS(!(fwq->flags & IQ_HW_ALLOCATED)); 3902 } 3903 3904 if (fwq->flags & IQ_SW_ALLOCATED) { 3905 MPASS(!(fwq->flags & IQ_HW_ALLOCATED)); 3906 free_iq_fl(sc, fwq, NULL); 3907 MPASS(!(fwq->flags & IQ_SW_ALLOCATED)); 3908 } 3909 } 3910 3911 /* 3912 * Idempotent. 3913 */ 3914 static int 3915 alloc_ctrlq(struct adapter *sc, int idx) 3916 { 3917 int rc; 3918 char name[16]; 3919 struct sysctl_oid *oid; 3920 struct sge_wrq *ctrlq = &sc->sge.ctrlq[idx]; 3921 3922 MPASS(idx < sc->params.nports); 3923 3924 if (!(ctrlq->eq.flags & EQ_SW_ALLOCATED)) { 3925 MPASS(!(ctrlq->eq.flags & EQ_HW_ALLOCATED)); 3926 3927 snprintf(name, sizeof(name), "%d", idx); 3928 oid = SYSCTL_ADD_NODE(&sc->ctx, SYSCTL_CHILDREN(sc->ctrlq_oid), 3929 OID_AUTO, name, CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 3930 "ctrl queue"); 3931 3932 snprintf(name, sizeof(name), "%s ctrlq%d", 3933 device_get_nameunit(sc->dev), idx); 3934 init_eq(sc, &ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE, 3935 sc->port[idx]->tx_chan, &sc->sge.fwq, name); 3936 rc = alloc_wrq(sc, NULL, ctrlq, &sc->ctx, oid); 3937 if (rc != 0) { 3938 CH_ERR(sc, "failed to allocate ctrlq%d: %d\n", idx, rc); 3939 sysctl_remove_oid(oid, 1, 1); 3940 return (rc); 3941 } 3942 MPASS(ctrlq->eq.flags & EQ_SW_ALLOCATED); 3943 } 3944 3945 if (!(ctrlq->eq.flags & EQ_HW_ALLOCATED)) { 3946 MPASS(ctrlq->eq.flags & EQ_SW_ALLOCATED); 3947 3948 rc = alloc_eq_hwq(sc, NULL, &ctrlq->eq); 3949 if (rc != 0) { 3950 CH_ERR(sc, "failed to create hw ctrlq%d: %d\n", idx, rc); 3951 return (rc); 3952 } 3953 MPASS(ctrlq->eq.flags & EQ_HW_ALLOCATED); 3954 } 3955 3956 return (0); 3957 } 3958 3959 /* 3960 * Idempotent. 3961 */ 3962 static void 3963 free_ctrlq(struct adapter *sc, int idx) 3964 { 3965 struct sge_wrq *ctrlq = &sc->sge.ctrlq[idx]; 3966 3967 if (ctrlq->eq.flags & EQ_HW_ALLOCATED) { 3968 MPASS(ctrlq->eq.flags & EQ_SW_ALLOCATED); 3969 free_eq_hwq(sc, NULL, &ctrlq->eq); 3970 MPASS(!(ctrlq->eq.flags & EQ_HW_ALLOCATED)); 3971 } 3972 3973 if (ctrlq->eq.flags & EQ_SW_ALLOCATED) { 3974 MPASS(!(ctrlq->eq.flags & EQ_HW_ALLOCATED)); 3975 free_wrq(sc, ctrlq); 3976 MPASS(!(ctrlq->eq.flags & EQ_SW_ALLOCATED)); 3977 } 3978 } 3979 3980 int 3981 t4_sge_set_conm_context(struct adapter *sc, int cntxt_id, int cong_drop, 3982 int cong_map) 3983 { 3984 const int cng_ch_bits_log = sc->chip_params->cng_ch_bits_log; 3985 uint32_t param, val; 3986 uint16_t ch_map; 3987 int cong_mode, rc, i; 3988 3989 if (chip_id(sc) < CHELSIO_T5) 3990 return (ENOTSUP); 3991 3992 /* Convert the driver knob to the mode understood by the firmware. */ 3993 switch (cong_drop) { 3994 case -1: 3995 cong_mode = X_CONMCTXT_CNGTPMODE_DISABLE; 3996 break; 3997 case 0: 3998 cong_mode = X_CONMCTXT_CNGTPMODE_CHANNEL; 3999 break; 4000 case 1: 4001 cong_mode = X_CONMCTXT_CNGTPMODE_QUEUE; 4002 break; 4003 case 2: 4004 cong_mode = X_CONMCTXT_CNGTPMODE_BOTH; 4005 break; 4006 default: 4007 MPASS(0); 4008 CH_ERR(sc, "cong_drop = %d is invalid (ingress queue %d).\n", 4009 cong_drop, cntxt_id); 4010 return (EINVAL); 4011 } 4012 4013 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 4014 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) | 4015 V_FW_PARAMS_PARAM_YZ(cntxt_id); 4016 val = V_CONMCTXT_CNGTPMODE(cong_mode); 4017 if (cong_mode == X_CONMCTXT_CNGTPMODE_CHANNEL || 4018 cong_mode == X_CONMCTXT_CNGTPMODE_BOTH) { 4019 for (i = 0, ch_map = 0; i < 4; i++) { 4020 if (cong_map & (1 << i)) 4021 ch_map |= 1 << (i << cng_ch_bits_log); 4022 } 4023 val |= V_CONMCTXT_CNGCHMAP(ch_map); 4024 } 4025 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 4026 if (rc != 0) { 4027 CH_ERR(sc, "failed to set congestion manager context " 4028 "for ingress queue %d: %d\n", cntxt_id, rc); 4029 } 4030 4031 return (rc); 4032 } 4033 4034 /* 4035 * Idempotent. 4036 */ 4037 static int 4038 alloc_rxq(struct vi_info *vi, struct sge_rxq *rxq, int idx, int intr_idx, 4039 int maxp) 4040 { 4041 int rc; 4042 struct adapter *sc = vi->adapter; 4043 struct ifnet *ifp = vi->ifp; 4044 struct sysctl_oid *oid; 4045 char name[16]; 4046 4047 if (!(rxq->iq.flags & IQ_SW_ALLOCATED)) { 4048 MPASS(!(rxq->iq.flags & IQ_HW_ALLOCATED)); 4049 #if defined(INET) || defined(INET6) 4050 rc = tcp_lro_init_args(&rxq->lro, ifp, lro_entries, lro_mbufs); 4051 if (rc != 0) 4052 return (rc); 4053 MPASS(rxq->lro.ifp == ifp); /* also indicates LRO init'ed */ 4054 #endif 4055 rxq->ifp = ifp; 4056 4057 snprintf(name, sizeof(name), "%d", idx); 4058 oid = SYSCTL_ADD_NODE(&vi->ctx, SYSCTL_CHILDREN(vi->rxq_oid), 4059 OID_AUTO, name, CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 4060 "rx queue"); 4061 4062 init_iq(&rxq->iq, sc, vi->tmr_idx, vi->pktc_idx, vi->qsize_rxq, 4063 intr_idx, cong_drop, IQ_ETH); 4064 #if defined(INET) || defined(INET6) 4065 if (ifp->if_capenable & IFCAP_LRO) 4066 rxq->iq.flags |= IQ_LRO_ENABLED; 4067 #endif 4068 if (ifp->if_capenable & IFCAP_HWRXTSTMP) 4069 rxq->iq.flags |= IQ_RX_TIMESTAMP; 4070 snprintf(name, sizeof(name), "%s rxq%d-fl", 4071 device_get_nameunit(vi->dev), idx); 4072 init_fl(sc, &rxq->fl, vi->qsize_rxq / 8, maxp, name); 4073 rc = alloc_iq_fl(vi, &rxq->iq, &rxq->fl, &vi->ctx, oid); 4074 if (rc != 0) { 4075 CH_ERR(vi, "failed to allocate rxq%d: %d\n", idx, rc); 4076 sysctl_remove_oid(oid, 1, 1); 4077 #if defined(INET) || defined(INET6) 4078 tcp_lro_free(&rxq->lro); 4079 rxq->lro.ifp = NULL; 4080 #endif 4081 return (rc); 4082 } 4083 MPASS(rxq->iq.flags & IQ_SW_ALLOCATED); 4084 add_rxq_sysctls(&vi->ctx, oid, rxq); 4085 } 4086 4087 if (!(rxq->iq.flags & IQ_HW_ALLOCATED)) { 4088 MPASS(rxq->iq.flags & IQ_SW_ALLOCATED); 4089 rc = alloc_iq_fl_hwq(vi, &rxq->iq, &rxq->fl); 4090 if (rc != 0) { 4091 CH_ERR(vi, "failed to create hw rxq%d: %d\n", idx, rc); 4092 return (rc); 4093 } 4094 MPASS(rxq->iq.flags & IQ_HW_ALLOCATED); 4095 4096 if (idx == 0) 4097 sc->sge.iq_base = rxq->iq.abs_id - rxq->iq.cntxt_id; 4098 else 4099 KASSERT(rxq->iq.cntxt_id + sc->sge.iq_base == rxq->iq.abs_id, 4100 ("iq_base mismatch")); 4101 KASSERT(sc->sge.iq_base == 0 || sc->flags & IS_VF, 4102 ("PF with non-zero iq_base")); 4103 4104 /* 4105 * The freelist is just barely above the starvation threshold 4106 * right now, fill it up a bit more. 4107 */ 4108 FL_LOCK(&rxq->fl); 4109 refill_fl(sc, &rxq->fl, 128); 4110 FL_UNLOCK(&rxq->fl); 4111 } 4112 4113 return (0); 4114 } 4115 4116 /* 4117 * Idempotent. 4118 */ 4119 static void 4120 free_rxq(struct vi_info *vi, struct sge_rxq *rxq) 4121 { 4122 if (rxq->iq.flags & IQ_HW_ALLOCATED) { 4123 MPASS(rxq->iq.flags & IQ_SW_ALLOCATED); 4124 free_iq_fl_hwq(vi->adapter, &rxq->iq, &rxq->fl); 4125 MPASS(!(rxq->iq.flags & IQ_HW_ALLOCATED)); 4126 } 4127 4128 if (rxq->iq.flags & IQ_SW_ALLOCATED) { 4129 MPASS(!(rxq->iq.flags & IQ_HW_ALLOCATED)); 4130 #if defined(INET) || defined(INET6) 4131 tcp_lro_free(&rxq->lro); 4132 #endif 4133 free_iq_fl(vi->adapter, &rxq->iq, &rxq->fl); 4134 MPASS(!(rxq->iq.flags & IQ_SW_ALLOCATED)); 4135 bzero(rxq, sizeof(*rxq)); 4136 } 4137 } 4138 4139 static void 4140 add_rxq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid, 4141 struct sge_rxq *rxq) 4142 { 4143 struct sysctl_oid_list *children; 4144 4145 if (ctx == NULL || oid == NULL) 4146 return; 4147 4148 children = SYSCTL_CHILDREN(oid); 4149 #if defined(INET) || defined(INET6) 4150 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "lro_queued", CTLFLAG_RD, 4151 &rxq->lro.lro_queued, 0, NULL); 4152 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "lro_flushed", CTLFLAG_RD, 4153 &rxq->lro.lro_flushed, 0, NULL); 4154 #endif 4155 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "rxcsum", CTLFLAG_RD, 4156 &rxq->rxcsum, "# of times hardware assisted with checksum"); 4157 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "vlan_extraction", CTLFLAG_RD, 4158 &rxq->vlan_extraction, "# of times hardware extracted 802.1Q tag"); 4159 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "vxlan_rxcsum", CTLFLAG_RD, 4160 &rxq->vxlan_rxcsum, 4161 "# of times hardware assisted with inner checksum (VXLAN)"); 4162 } 4163 4164 #ifdef TCP_OFFLOAD 4165 /* 4166 * Idempotent. 4167 */ 4168 static int 4169 alloc_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq, int idx, 4170 int intr_idx, int maxp) 4171 { 4172 int rc; 4173 struct adapter *sc = vi->adapter; 4174 struct sysctl_oid *oid; 4175 char name[16]; 4176 4177 if (!(ofld_rxq->iq.flags & IQ_SW_ALLOCATED)) { 4178 MPASS(!(ofld_rxq->iq.flags & IQ_HW_ALLOCATED)); 4179 4180 snprintf(name, sizeof(name), "%d", idx); 4181 oid = SYSCTL_ADD_NODE(&vi->ctx, 4182 SYSCTL_CHILDREN(vi->ofld_rxq_oid), OID_AUTO, name, 4183 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "offload rx queue"); 4184 4185 init_iq(&ofld_rxq->iq, sc, vi->ofld_tmr_idx, vi->ofld_pktc_idx, 4186 vi->qsize_rxq, intr_idx, ofld_cong_drop, IQ_OFLD); 4187 snprintf(name, sizeof(name), "%s ofld_rxq%d-fl", 4188 device_get_nameunit(vi->dev), idx); 4189 init_fl(sc, &ofld_rxq->fl, vi->qsize_rxq / 8, maxp, name); 4190 rc = alloc_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl, &vi->ctx, 4191 oid); 4192 if (rc != 0) { 4193 CH_ERR(vi, "failed to allocate ofld_rxq%d: %d\n", idx, 4194 rc); 4195 sysctl_remove_oid(oid, 1, 1); 4196 return (rc); 4197 } 4198 MPASS(ofld_rxq->iq.flags & IQ_SW_ALLOCATED); 4199 ofld_rxq->rx_iscsi_ddp_setup_ok = counter_u64_alloc(M_WAITOK); 4200 ofld_rxq->rx_iscsi_ddp_setup_error = 4201 counter_u64_alloc(M_WAITOK); 4202 add_ofld_rxq_sysctls(&vi->ctx, oid, ofld_rxq); 4203 } 4204 4205 if (!(ofld_rxq->iq.flags & IQ_HW_ALLOCATED)) { 4206 MPASS(ofld_rxq->iq.flags & IQ_SW_ALLOCATED); 4207 rc = alloc_iq_fl_hwq(vi, &ofld_rxq->iq, &ofld_rxq->fl); 4208 if (rc != 0) { 4209 CH_ERR(vi, "failed to create hw ofld_rxq%d: %d\n", idx, 4210 rc); 4211 return (rc); 4212 } 4213 MPASS(ofld_rxq->iq.flags & IQ_HW_ALLOCATED); 4214 } 4215 return (rc); 4216 } 4217 4218 /* 4219 * Idempotent. 4220 */ 4221 static void 4222 free_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq) 4223 { 4224 if (ofld_rxq->iq.flags & IQ_HW_ALLOCATED) { 4225 MPASS(ofld_rxq->iq.flags & IQ_SW_ALLOCATED); 4226 free_iq_fl_hwq(vi->adapter, &ofld_rxq->iq, &ofld_rxq->fl); 4227 MPASS(!(ofld_rxq->iq.flags & IQ_HW_ALLOCATED)); 4228 } 4229 4230 if (ofld_rxq->iq.flags & IQ_SW_ALLOCATED) { 4231 MPASS(!(ofld_rxq->iq.flags & IQ_HW_ALLOCATED)); 4232 free_iq_fl(vi->adapter, &ofld_rxq->iq, &ofld_rxq->fl); 4233 MPASS(!(ofld_rxq->iq.flags & IQ_SW_ALLOCATED)); 4234 counter_u64_free(ofld_rxq->rx_iscsi_ddp_setup_ok); 4235 counter_u64_free(ofld_rxq->rx_iscsi_ddp_setup_error); 4236 bzero(ofld_rxq, sizeof(*ofld_rxq)); 4237 } 4238 } 4239 4240 static void 4241 add_ofld_rxq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid, 4242 struct sge_ofld_rxq *ofld_rxq) 4243 { 4244 struct sysctl_oid_list *children; 4245 4246 if (ctx == NULL || oid == NULL) 4247 return; 4248 4249 children = SYSCTL_CHILDREN(oid); 4250 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 4251 "rx_toe_tls_records", CTLFLAG_RD, &ofld_rxq->rx_toe_tls_records, 4252 "# of TOE TLS records received"); 4253 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 4254 "rx_toe_tls_octets", CTLFLAG_RD, &ofld_rxq->rx_toe_tls_octets, 4255 "# of payload octets in received TOE TLS records"); 4256 4257 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "iscsi", 4258 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TOE iSCSI statistics"); 4259 children = SYSCTL_CHILDREN(oid); 4260 4261 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "ddp_setup_ok", 4262 CTLFLAG_RD, &ofld_rxq->rx_iscsi_ddp_setup_ok, 4263 "# of times DDP buffer was setup successfully."); 4264 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "ddp_setup_error", 4265 CTLFLAG_RD, &ofld_rxq->rx_iscsi_ddp_setup_error, 4266 "# of times DDP buffer setup failed."); 4267 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "ddp_octets", 4268 CTLFLAG_RD, &ofld_rxq->rx_iscsi_ddp_octets, 0, 4269 "# of octets placed directly"); 4270 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "ddp_pdus", 4271 CTLFLAG_RD, &ofld_rxq->rx_iscsi_ddp_pdus, 0, 4272 "# of PDUs with data placed directly."); 4273 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "fl_octets", 4274 CTLFLAG_RD, &ofld_rxq->rx_iscsi_fl_octets, 0, 4275 "# of data octets delivered in freelist"); 4276 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "fl_pdus", 4277 CTLFLAG_RD, &ofld_rxq->rx_iscsi_fl_pdus, 0, 4278 "# of PDUs with data delivered in freelist"); 4279 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "padding_errors", 4280 CTLFLAG_RD, &ofld_rxq->rx_iscsi_padding_errors, 0, 4281 "# of PDUs with invalid padding"); 4282 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "header_digest_errors", 4283 CTLFLAG_RD, &ofld_rxq->rx_iscsi_header_digest_errors, 0, 4284 "# of PDUs with invalid header digests"); 4285 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "data_digest_errors", 4286 CTLFLAG_RD, &ofld_rxq->rx_iscsi_data_digest_errors, 0, 4287 "# of PDUs with invalid data digests"); 4288 } 4289 #endif 4290 4291 /* 4292 * Returns a reasonable automatic cidx flush threshold for a given queue size. 4293 */ 4294 static u_int 4295 qsize_to_fthresh(int qsize) 4296 { 4297 u_int fthresh; 4298 4299 while (!powerof2(qsize)) 4300 qsize++; 4301 fthresh = ilog2(qsize); 4302 if (fthresh > X_CIDXFLUSHTHRESH_128) 4303 fthresh = X_CIDXFLUSHTHRESH_128; 4304 4305 return (fthresh); 4306 } 4307 4308 static int 4309 ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq) 4310 { 4311 int rc, cntxt_id; 4312 struct fw_eq_ctrl_cmd c; 4313 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 4314 4315 bzero(&c, sizeof(c)); 4316 4317 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | F_FW_CMD_REQUEST | 4318 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_CTRL_CMD_PFN(sc->pf) | 4319 V_FW_EQ_CTRL_CMD_VFN(0)); 4320 c.alloc_to_len16 = htobe32(F_FW_EQ_CTRL_CMD_ALLOC | 4321 F_FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c)); 4322 c.cmpliqid_eqid = htonl(V_FW_EQ_CTRL_CMD_CMPLIQID(eq->iqid)); 4323 c.physeqid_pkd = htobe32(0); 4324 c.fetchszm_to_iqid = 4325 htobe32(V_FW_EQ_CTRL_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 4326 V_FW_EQ_CTRL_CMD_PCIECHN(eq->tx_chan) | 4327 F_FW_EQ_CTRL_CMD_FETCHRO | V_FW_EQ_CTRL_CMD_IQID(eq->iqid)); 4328 c.dcaen_to_eqsize = 4329 htobe32(V_FW_EQ_CTRL_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ? 4330 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) | 4331 V_FW_EQ_CTRL_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 4332 V_FW_EQ_CTRL_CMD_CIDXFTHRESH(qsize_to_fthresh(qsize)) | 4333 V_FW_EQ_CTRL_CMD_EQSIZE(qsize)); 4334 c.eqaddr = htobe64(eq->ba); 4335 4336 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 4337 if (rc != 0) { 4338 CH_ERR(sc, "failed to create hw ctrlq for tx_chan %d: %d\n", 4339 eq->tx_chan, rc); 4340 return (rc); 4341 } 4342 4343 eq->cntxt_id = G_FW_EQ_CTRL_CMD_EQID(be32toh(c.cmpliqid_eqid)); 4344 eq->abs_id = G_FW_EQ_CTRL_CMD_PHYSEQID(be32toh(c.physeqid_pkd)); 4345 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 4346 if (cntxt_id >= sc->sge.eqmap_sz) 4347 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 4348 cntxt_id, sc->sge.eqmap_sz - 1); 4349 sc->sge.eqmap[cntxt_id] = eq; 4350 4351 return (rc); 4352 } 4353 4354 static int 4355 eth_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 4356 { 4357 int rc, cntxt_id; 4358 struct fw_eq_eth_cmd c; 4359 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 4360 4361 bzero(&c, sizeof(c)); 4362 4363 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST | 4364 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) | 4365 V_FW_EQ_ETH_CMD_VFN(0)); 4366 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC | 4367 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c)); 4368 c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE | 4369 F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(vi->viid)); 4370 c.fetchszm_to_iqid = 4371 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) | 4372 V_FW_EQ_ETH_CMD_PCIECHN(eq->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO | 4373 V_FW_EQ_ETH_CMD_IQID(eq->iqid)); 4374 c.dcaen_to_eqsize = 4375 htobe32(V_FW_EQ_ETH_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ? 4376 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) | 4377 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 4378 V_FW_EQ_ETH_CMD_EQSIZE(qsize)); 4379 c.eqaddr = htobe64(eq->ba); 4380 4381 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 4382 if (rc != 0) { 4383 device_printf(vi->dev, 4384 "failed to create Ethernet egress queue: %d\n", rc); 4385 return (rc); 4386 } 4387 4388 eq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd)); 4389 eq->abs_id = G_FW_EQ_ETH_CMD_PHYSEQID(be32toh(c.physeqid_pkd)); 4390 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 4391 if (cntxt_id >= sc->sge.eqmap_sz) 4392 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 4393 cntxt_id, sc->sge.eqmap_sz - 1); 4394 sc->sge.eqmap[cntxt_id] = eq; 4395 4396 return (rc); 4397 } 4398 4399 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 4400 static int 4401 ofld_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 4402 { 4403 int rc, cntxt_id; 4404 struct fw_eq_ofld_cmd c; 4405 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 4406 4407 bzero(&c, sizeof(c)); 4408 4409 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | F_FW_CMD_REQUEST | 4410 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_OFLD_CMD_PFN(sc->pf) | 4411 V_FW_EQ_OFLD_CMD_VFN(0)); 4412 c.alloc_to_len16 = htonl(F_FW_EQ_OFLD_CMD_ALLOC | 4413 F_FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c)); 4414 c.fetchszm_to_iqid = 4415 htonl(V_FW_EQ_OFLD_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 4416 V_FW_EQ_OFLD_CMD_PCIECHN(eq->tx_chan) | 4417 F_FW_EQ_OFLD_CMD_FETCHRO | V_FW_EQ_OFLD_CMD_IQID(eq->iqid)); 4418 c.dcaen_to_eqsize = 4419 htobe32(V_FW_EQ_OFLD_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ? 4420 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) | 4421 V_FW_EQ_OFLD_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 4422 V_FW_EQ_OFLD_CMD_CIDXFTHRESH(qsize_to_fthresh(qsize)) | 4423 V_FW_EQ_OFLD_CMD_EQSIZE(qsize)); 4424 c.eqaddr = htobe64(eq->ba); 4425 4426 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 4427 if (rc != 0) { 4428 device_printf(vi->dev, 4429 "failed to create egress queue for TCP offload: %d\n", rc); 4430 return (rc); 4431 } 4432 4433 eq->cntxt_id = G_FW_EQ_OFLD_CMD_EQID(be32toh(c.eqid_pkd)); 4434 eq->abs_id = G_FW_EQ_OFLD_CMD_PHYSEQID(be32toh(c.physeqid_pkd)); 4435 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 4436 if (cntxt_id >= sc->sge.eqmap_sz) 4437 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 4438 cntxt_id, sc->sge.eqmap_sz - 1); 4439 sc->sge.eqmap[cntxt_id] = eq; 4440 4441 return (rc); 4442 } 4443 #endif 4444 4445 /* SW only */ 4446 static int 4447 alloc_eq(struct adapter *sc, struct sge_eq *eq, struct sysctl_ctx_list *ctx, 4448 struct sysctl_oid *oid) 4449 { 4450 int rc, qsize; 4451 size_t len; 4452 4453 MPASS(!(eq->flags & EQ_SW_ALLOCATED)); 4454 4455 qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 4456 len = qsize * EQ_ESIZE; 4457 rc = alloc_ring(sc, len, &eq->desc_tag, &eq->desc_map, &eq->ba, 4458 (void **)&eq->desc); 4459 if (rc) 4460 return (rc); 4461 if (ctx != NULL && oid != NULL) 4462 add_eq_sysctls(sc, ctx, oid, eq); 4463 eq->flags |= EQ_SW_ALLOCATED; 4464 4465 return (0); 4466 } 4467 4468 /* SW only */ 4469 static void 4470 free_eq(struct adapter *sc, struct sge_eq *eq) 4471 { 4472 MPASS(eq->flags & EQ_SW_ALLOCATED); 4473 if (eq->type == EQ_ETH) 4474 MPASS(eq->pidx == eq->cidx); 4475 4476 free_ring(sc, eq->desc_tag, eq->desc_map, eq->ba, eq->desc); 4477 mtx_destroy(&eq->eq_lock); 4478 bzero(eq, sizeof(*eq)); 4479 } 4480 4481 static void 4482 add_eq_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx, 4483 struct sysctl_oid *oid, struct sge_eq *eq) 4484 { 4485 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 4486 4487 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, &eq->ba, 4488 "bus address of descriptor ring"); 4489 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 4490 eq->sidx * EQ_ESIZE + sc->params.sge.spg_len, 4491 "desc ring size in bytes"); 4492 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "abs_id", CTLFLAG_RD, 4493 &eq->abs_id, 0, "absolute id of the queue"); 4494 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 4495 &eq->cntxt_id, 0, "SGE context id of the queue"); 4496 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &eq->cidx, 4497 0, "consumer index"); 4498 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &eq->pidx, 4499 0, "producer index"); 4500 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL, 4501 eq->sidx, "status page index"); 4502 } 4503 4504 static int 4505 alloc_eq_hwq(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 4506 { 4507 int rc; 4508 4509 MPASS(!(eq->flags & EQ_HW_ALLOCATED)); 4510 4511 eq->iqid = eq->iq->cntxt_id; 4512 eq->pidx = eq->cidx = eq->dbidx = 0; 4513 /* Note that equeqidx is not used with sge_wrq (OFLD/CTRL) queues. */ 4514 eq->equeqidx = 0; 4515 eq->doorbells = sc->doorbells; 4516 bzero(eq->desc, eq->sidx * EQ_ESIZE + sc->params.sge.spg_len); 4517 4518 switch (eq->type) { 4519 case EQ_CTRL: 4520 rc = ctrl_eq_alloc(sc, eq); 4521 break; 4522 4523 case EQ_ETH: 4524 rc = eth_eq_alloc(sc, vi, eq); 4525 break; 4526 4527 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 4528 case EQ_OFLD: 4529 rc = ofld_eq_alloc(sc, vi, eq); 4530 break; 4531 #endif 4532 4533 default: 4534 panic("%s: invalid eq type %d.", __func__, eq->type); 4535 } 4536 if (rc != 0) { 4537 CH_ERR(sc, "failed to allocate egress queue(%d): %d\n", 4538 eq->type, rc); 4539 return (rc); 4540 } 4541 4542 if (isset(&eq->doorbells, DOORBELL_UDB) || 4543 isset(&eq->doorbells, DOORBELL_UDBWC) || 4544 isset(&eq->doorbells, DOORBELL_WCWR)) { 4545 uint32_t s_qpp = sc->params.sge.eq_s_qpp; 4546 uint32_t mask = (1 << s_qpp) - 1; 4547 volatile uint8_t *udb; 4548 4549 udb = sc->udbs_base + UDBS_DB_OFFSET; 4550 udb += (eq->cntxt_id >> s_qpp) << PAGE_SHIFT; /* pg offset */ 4551 eq->udb_qid = eq->cntxt_id & mask; /* id in page */ 4552 if (eq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE) 4553 clrbit(&eq->doorbells, DOORBELL_WCWR); 4554 else { 4555 udb += eq->udb_qid << UDBS_SEG_SHIFT; /* seg offset */ 4556 eq->udb_qid = 0; 4557 } 4558 eq->udb = (volatile void *)udb; 4559 } 4560 4561 eq->flags |= EQ_HW_ALLOCATED; 4562 return (0); 4563 } 4564 4565 static int 4566 free_eq_hwq(struct adapter *sc, struct vi_info *vi __unused, struct sge_eq *eq) 4567 { 4568 int rc; 4569 4570 MPASS(eq->flags & EQ_HW_ALLOCATED); 4571 4572 switch (eq->type) { 4573 case EQ_CTRL: 4574 rc = -t4_ctrl_eq_free(sc, sc->mbox, sc->pf, 0, eq->cntxt_id); 4575 break; 4576 case EQ_ETH: 4577 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0, eq->cntxt_id); 4578 break; 4579 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 4580 case EQ_OFLD: 4581 rc = -t4_ofld_eq_free(sc, sc->mbox, sc->pf, 0, eq->cntxt_id); 4582 break; 4583 #endif 4584 default: 4585 panic("%s: invalid eq type %d.", __func__, eq->type); 4586 } 4587 if (rc != 0) { 4588 CH_ERR(sc, "failed to free eq (type %d): %d\n", eq->type, rc); 4589 return (rc); 4590 } 4591 eq->flags &= ~EQ_HW_ALLOCATED; 4592 4593 return (0); 4594 } 4595 4596 static int 4597 alloc_wrq(struct adapter *sc, struct vi_info *vi, struct sge_wrq *wrq, 4598 struct sysctl_ctx_list *ctx, struct sysctl_oid *oid) 4599 { 4600 struct sge_eq *eq = &wrq->eq; 4601 int rc; 4602 4603 MPASS(!(eq->flags & EQ_SW_ALLOCATED)); 4604 4605 rc = alloc_eq(sc, eq, ctx, oid); 4606 if (rc) 4607 return (rc); 4608 MPASS(eq->flags & EQ_SW_ALLOCATED); 4609 /* Can't fail after this. */ 4610 4611 wrq->adapter = sc; 4612 TASK_INIT(&wrq->wrq_tx_task, 0, wrq_tx_drain, wrq); 4613 TAILQ_INIT(&wrq->incomplete_wrs); 4614 STAILQ_INIT(&wrq->wr_list); 4615 wrq->nwr_pending = 0; 4616 wrq->ndesc_needed = 0; 4617 add_wrq_sysctls(ctx, oid, wrq); 4618 4619 return (0); 4620 } 4621 4622 static void 4623 free_wrq(struct adapter *sc, struct sge_wrq *wrq) 4624 { 4625 free_eq(sc, &wrq->eq); 4626 MPASS(wrq->nwr_pending == 0); 4627 MPASS(TAILQ_EMPTY(&wrq->incomplete_wrs)); 4628 MPASS(STAILQ_EMPTY(&wrq->wr_list)); 4629 bzero(wrq, sizeof(*wrq)); 4630 } 4631 4632 static void 4633 add_wrq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid, 4634 struct sge_wrq *wrq) 4635 { 4636 struct sysctl_oid_list *children; 4637 4638 if (ctx == NULL || oid == NULL) 4639 return; 4640 4641 children = SYSCTL_CHILDREN(oid); 4642 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_direct", CTLFLAG_RD, 4643 &wrq->tx_wrs_direct, "# of work requests (direct)"); 4644 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_copied", CTLFLAG_RD, 4645 &wrq->tx_wrs_copied, "# of work requests (copied)"); 4646 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_sspace", CTLFLAG_RD, 4647 &wrq->tx_wrs_ss, "# of work requests (copied from scratch space)"); 4648 } 4649 4650 /* 4651 * Idempotent. 4652 */ 4653 static int 4654 alloc_txq(struct vi_info *vi, struct sge_txq *txq, int idx) 4655 { 4656 int rc, iqidx; 4657 struct port_info *pi = vi->pi; 4658 struct adapter *sc = vi->adapter; 4659 struct sge_eq *eq = &txq->eq; 4660 struct txpkts *txp; 4661 char name[16]; 4662 struct sysctl_oid *oid; 4663 4664 if (!(eq->flags & EQ_SW_ALLOCATED)) { 4665 MPASS(!(eq->flags & EQ_HW_ALLOCATED)); 4666 4667 snprintf(name, sizeof(name), "%d", idx); 4668 oid = SYSCTL_ADD_NODE(&vi->ctx, SYSCTL_CHILDREN(vi->txq_oid), 4669 OID_AUTO, name, CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 4670 "tx queue"); 4671 4672 iqidx = vi->first_rxq + (idx % vi->nrxq); 4673 snprintf(name, sizeof(name), "%s txq%d", 4674 device_get_nameunit(vi->dev), idx); 4675 init_eq(sc, &txq->eq, EQ_ETH, vi->qsize_txq, pi->tx_chan, 4676 &sc->sge.rxq[iqidx].iq, name); 4677 4678 rc = mp_ring_alloc(&txq->r, eq->sidx, txq, eth_tx, 4679 can_resume_eth_tx, M_CXGBE, &eq->eq_lock, M_WAITOK); 4680 if (rc != 0) { 4681 CH_ERR(vi, "failed to allocate mp_ring for txq%d: %d\n", 4682 idx, rc); 4683 failed: 4684 sysctl_remove_oid(oid, 1, 1); 4685 return (rc); 4686 } 4687 4688 rc = alloc_eq(sc, eq, &vi->ctx, oid); 4689 if (rc) { 4690 CH_ERR(vi, "failed to allocate txq%d: %d\n", idx, rc); 4691 mp_ring_free(txq->r); 4692 goto failed; 4693 } 4694 MPASS(eq->flags & EQ_SW_ALLOCATED); 4695 /* Can't fail after this point. */ 4696 4697 TASK_INIT(&txq->tx_reclaim_task, 0, tx_reclaim, eq); 4698 txq->ifp = vi->ifp; 4699 txq->gl = sglist_alloc(TX_SGL_SEGS, M_WAITOK); 4700 txq->sdesc = malloc(eq->sidx * sizeof(struct tx_sdesc), M_CXGBE, 4701 M_ZERO | M_WAITOK); 4702 4703 add_txq_sysctls(vi, &vi->ctx, oid, txq); 4704 } 4705 4706 if (!(eq->flags & EQ_HW_ALLOCATED)) { 4707 MPASS(eq->flags & EQ_SW_ALLOCATED); 4708 rc = alloc_eq_hwq(sc, vi, eq); 4709 if (rc != 0) { 4710 CH_ERR(vi, "failed to create hw txq%d: %d\n", idx, rc); 4711 return (rc); 4712 } 4713 MPASS(eq->flags & EQ_HW_ALLOCATED); 4714 /* Can't fail after this point. */ 4715 4716 if (idx == 0) 4717 sc->sge.eq_base = eq->abs_id - eq->cntxt_id; 4718 else 4719 KASSERT(eq->cntxt_id + sc->sge.eq_base == eq->abs_id, 4720 ("eq_base mismatch")); 4721 KASSERT(sc->sge.eq_base == 0 || sc->flags & IS_VF, 4722 ("PF with non-zero eq_base")); 4723 4724 txp = &txq->txp; 4725 MPASS(nitems(txp->mb) >= sc->params.max_pkts_per_eth_tx_pkts_wr); 4726 txq->txp.max_npkt = min(nitems(txp->mb), 4727 sc->params.max_pkts_per_eth_tx_pkts_wr); 4728 if (vi->flags & TX_USES_VM_WR && !(sc->flags & IS_VF)) 4729 txq->txp.max_npkt--; 4730 4731 if (vi->flags & TX_USES_VM_WR) 4732 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) | 4733 V_TXPKT_INTF(pi->tx_chan)); 4734 else 4735 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) | 4736 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(sc->pf) | 4737 V_TXPKT_VF(vi->vin) | V_TXPKT_VF_VLD(vi->vfvld)); 4738 4739 txq->tc_idx = -1; 4740 } 4741 4742 return (0); 4743 } 4744 4745 /* 4746 * Idempotent. 4747 */ 4748 static void 4749 free_txq(struct vi_info *vi, struct sge_txq *txq) 4750 { 4751 struct adapter *sc = vi->adapter; 4752 struct sge_eq *eq = &txq->eq; 4753 4754 if (eq->flags & EQ_HW_ALLOCATED) { 4755 MPASS(eq->flags & EQ_SW_ALLOCATED); 4756 free_eq_hwq(sc, NULL, eq); 4757 MPASS(!(eq->flags & EQ_HW_ALLOCATED)); 4758 } 4759 4760 if (eq->flags & EQ_SW_ALLOCATED) { 4761 MPASS(!(eq->flags & EQ_HW_ALLOCATED)); 4762 sglist_free(txq->gl); 4763 free(txq->sdesc, M_CXGBE); 4764 mp_ring_free(txq->r); 4765 free_eq(sc, eq); 4766 MPASS(!(eq->flags & EQ_SW_ALLOCATED)); 4767 bzero(txq, sizeof(*txq)); 4768 } 4769 } 4770 4771 static void 4772 add_txq_sysctls(struct vi_info *vi, struct sysctl_ctx_list *ctx, 4773 struct sysctl_oid *oid, struct sge_txq *txq) 4774 { 4775 struct adapter *sc; 4776 struct sysctl_oid_list *children; 4777 4778 if (ctx == NULL || oid == NULL) 4779 return; 4780 4781 sc = vi->adapter; 4782 children = SYSCTL_CHILDREN(oid); 4783 4784 mp_ring_sysctls(txq->r, ctx, children); 4785 4786 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tc", 4787 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, txq - sc->sge.txq, 4788 sysctl_tc, "I", "traffic class (-1 means none)"); 4789 4790 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txcsum", CTLFLAG_RD, 4791 &txq->txcsum, "# of times hardware assisted with checksum"); 4792 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "vlan_insertion", CTLFLAG_RD, 4793 &txq->vlan_insertion, "# of times hardware inserted 802.1Q tag"); 4794 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tso_wrs", CTLFLAG_RD, 4795 &txq->tso_wrs, "# of TSO work requests"); 4796 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "imm_wrs", CTLFLAG_RD, 4797 &txq->imm_wrs, "# of work requests with immediate data"); 4798 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "sgl_wrs", CTLFLAG_RD, 4799 &txq->sgl_wrs, "# of work requests with direct SGL"); 4800 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkt_wrs", CTLFLAG_RD, 4801 &txq->txpkt_wrs, "# of txpkt work requests (one pkt/WR)"); 4802 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkts0_wrs", CTLFLAG_RD, 4803 &txq->txpkts0_wrs, "# of txpkts (type 0) work requests"); 4804 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkts1_wrs", CTLFLAG_RD, 4805 &txq->txpkts1_wrs, "# of txpkts (type 1) work requests"); 4806 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkts0_pkts", CTLFLAG_RD, 4807 &txq->txpkts0_pkts, 4808 "# of frames tx'd using type0 txpkts work requests"); 4809 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkts1_pkts", CTLFLAG_RD, 4810 &txq->txpkts1_pkts, 4811 "# of frames tx'd using type1 txpkts work requests"); 4812 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkts_flush", CTLFLAG_RD, 4813 &txq->txpkts_flush, 4814 "# of times txpkts had to be flushed out by an egress-update"); 4815 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "raw_wrs", CTLFLAG_RD, 4816 &txq->raw_wrs, "# of raw work requests (non-packets)"); 4817 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "vxlan_tso_wrs", CTLFLAG_RD, 4818 &txq->vxlan_tso_wrs, "# of VXLAN TSO work requests"); 4819 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "vxlan_txcsum", CTLFLAG_RD, 4820 &txq->vxlan_txcsum, 4821 "# of times hardware assisted with inner checksums (VXLAN)"); 4822 4823 #ifdef KERN_TLS 4824 if (is_ktls(sc)) { 4825 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_records", 4826 CTLFLAG_RD, &txq->kern_tls_records, 4827 "# of NIC TLS records transmitted"); 4828 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_short", 4829 CTLFLAG_RD, &txq->kern_tls_short, 4830 "# of short NIC TLS records transmitted"); 4831 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_partial", 4832 CTLFLAG_RD, &txq->kern_tls_partial, 4833 "# of partial NIC TLS records transmitted"); 4834 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_full", 4835 CTLFLAG_RD, &txq->kern_tls_full, 4836 "# of full NIC TLS records transmitted"); 4837 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_octets", 4838 CTLFLAG_RD, &txq->kern_tls_octets, 4839 "# of payload octets in transmitted NIC TLS records"); 4840 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_waste", 4841 CTLFLAG_RD, &txq->kern_tls_waste, 4842 "# of octets DMAd but not transmitted in NIC TLS records"); 4843 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_options", 4844 CTLFLAG_RD, &txq->kern_tls_options, 4845 "# of NIC TLS options-only packets transmitted"); 4846 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_header", 4847 CTLFLAG_RD, &txq->kern_tls_header, 4848 "# of NIC TLS header-only packets transmitted"); 4849 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_fin", 4850 CTLFLAG_RD, &txq->kern_tls_fin, 4851 "# of NIC TLS FIN-only packets transmitted"); 4852 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_fin_short", 4853 CTLFLAG_RD, &txq->kern_tls_fin_short, 4854 "# of NIC TLS padded FIN packets on short TLS records"); 4855 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_cbc", 4856 CTLFLAG_RD, &txq->kern_tls_cbc, 4857 "# of NIC TLS sessions using AES-CBC"); 4858 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_gcm", 4859 CTLFLAG_RD, &txq->kern_tls_gcm, 4860 "# of NIC TLS sessions using AES-GCM"); 4861 } 4862 #endif 4863 } 4864 4865 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 4866 /* 4867 * Idempotent. 4868 */ 4869 static int 4870 alloc_ofld_txq(struct vi_info *vi, struct sge_ofld_txq *ofld_txq, int idx) 4871 { 4872 struct sysctl_oid *oid; 4873 struct port_info *pi = vi->pi; 4874 struct adapter *sc = vi->adapter; 4875 struct sge_eq *eq = &ofld_txq->wrq.eq; 4876 int rc, iqidx; 4877 char name[16]; 4878 4879 MPASS(idx >= 0); 4880 MPASS(idx < vi->nofldtxq); 4881 4882 if (!(eq->flags & EQ_SW_ALLOCATED)) { 4883 snprintf(name, sizeof(name), "%d", idx); 4884 oid = SYSCTL_ADD_NODE(&vi->ctx, 4885 SYSCTL_CHILDREN(vi->ofld_txq_oid), OID_AUTO, name, 4886 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "offload tx queue"); 4887 4888 snprintf(name, sizeof(name), "%s ofld_txq%d", 4889 device_get_nameunit(vi->dev), idx); 4890 if (vi->nofldrxq > 0) { 4891 iqidx = vi->first_ofld_rxq + (idx % vi->nofldrxq); 4892 init_eq(sc, eq, EQ_OFLD, vi->qsize_txq, pi->tx_chan, 4893 &sc->sge.ofld_rxq[iqidx].iq, name); 4894 } else { 4895 iqidx = vi->first_rxq + (idx % vi->nrxq); 4896 init_eq(sc, eq, EQ_OFLD, vi->qsize_txq, pi->tx_chan, 4897 &sc->sge.rxq[iqidx].iq, name); 4898 } 4899 4900 rc = alloc_wrq(sc, vi, &ofld_txq->wrq, &vi->ctx, oid); 4901 if (rc != 0) { 4902 CH_ERR(vi, "failed to allocate ofld_txq%d: %d\n", idx, 4903 rc); 4904 sysctl_remove_oid(oid, 1, 1); 4905 return (rc); 4906 } 4907 MPASS(eq->flags & EQ_SW_ALLOCATED); 4908 /* Can't fail after this point. */ 4909 4910 ofld_txq->tx_iscsi_pdus = counter_u64_alloc(M_WAITOK); 4911 ofld_txq->tx_iscsi_octets = counter_u64_alloc(M_WAITOK); 4912 ofld_txq->tx_iscsi_iso_wrs = counter_u64_alloc(M_WAITOK); 4913 ofld_txq->tx_toe_tls_records = counter_u64_alloc(M_WAITOK); 4914 ofld_txq->tx_toe_tls_octets = counter_u64_alloc(M_WAITOK); 4915 add_ofld_txq_sysctls(&vi->ctx, oid, ofld_txq); 4916 } 4917 4918 if (!(eq->flags & EQ_HW_ALLOCATED)) { 4919 rc = alloc_eq_hwq(sc, vi, eq); 4920 if (rc != 0) { 4921 CH_ERR(vi, "failed to create hw ofld_txq%d: %d\n", idx, 4922 rc); 4923 return (rc); 4924 } 4925 MPASS(eq->flags & EQ_HW_ALLOCATED); 4926 } 4927 4928 return (0); 4929 } 4930 4931 /* 4932 * Idempotent. 4933 */ 4934 static void 4935 free_ofld_txq(struct vi_info *vi, struct sge_ofld_txq *ofld_txq) 4936 { 4937 struct adapter *sc = vi->adapter; 4938 struct sge_eq *eq = &ofld_txq->wrq.eq; 4939 4940 if (eq->flags & EQ_HW_ALLOCATED) { 4941 MPASS(eq->flags & EQ_SW_ALLOCATED); 4942 free_eq_hwq(sc, NULL, eq); 4943 MPASS(!(eq->flags & EQ_HW_ALLOCATED)); 4944 } 4945 4946 if (eq->flags & EQ_SW_ALLOCATED) { 4947 MPASS(!(eq->flags & EQ_HW_ALLOCATED)); 4948 counter_u64_free(ofld_txq->tx_iscsi_pdus); 4949 counter_u64_free(ofld_txq->tx_iscsi_octets); 4950 counter_u64_free(ofld_txq->tx_iscsi_iso_wrs); 4951 counter_u64_free(ofld_txq->tx_toe_tls_records); 4952 counter_u64_free(ofld_txq->tx_toe_tls_octets); 4953 free_wrq(sc, &ofld_txq->wrq); 4954 MPASS(!(eq->flags & EQ_SW_ALLOCATED)); 4955 bzero(ofld_txq, sizeof(*ofld_txq)); 4956 } 4957 } 4958 4959 static void 4960 add_ofld_txq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid, 4961 struct sge_ofld_txq *ofld_txq) 4962 { 4963 struct sysctl_oid_list *children; 4964 4965 if (ctx == NULL || oid == NULL) 4966 return; 4967 4968 children = SYSCTL_CHILDREN(oid); 4969 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_iscsi_pdus", 4970 CTLFLAG_RD, &ofld_txq->tx_iscsi_pdus, 4971 "# of iSCSI PDUs transmitted"); 4972 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_iscsi_octets", 4973 CTLFLAG_RD, &ofld_txq->tx_iscsi_octets, 4974 "# of payload octets in transmitted iSCSI PDUs"); 4975 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_iscsi_iso_wrs", 4976 CTLFLAG_RD, &ofld_txq->tx_iscsi_iso_wrs, 4977 "# of iSCSI segmentation offload work requests"); 4978 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_toe_tls_records", 4979 CTLFLAG_RD, &ofld_txq->tx_toe_tls_records, 4980 "# of TOE TLS records transmitted"); 4981 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_toe_tls_octets", 4982 CTLFLAG_RD, &ofld_txq->tx_toe_tls_octets, 4983 "# of payload octets in transmitted TOE TLS records"); 4984 } 4985 #endif 4986 4987 static void 4988 oneseg_dma_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error) 4989 { 4990 bus_addr_t *ba = arg; 4991 4992 KASSERT(nseg == 1, 4993 ("%s meant for single segment mappings only.", __func__)); 4994 4995 *ba = error ? 0 : segs->ds_addr; 4996 } 4997 4998 static inline void 4999 ring_fl_db(struct adapter *sc, struct sge_fl *fl) 5000 { 5001 uint32_t n, v; 5002 5003 n = IDXDIFF(fl->pidx >> 3, fl->dbidx, fl->sidx); 5004 MPASS(n > 0); 5005 5006 wmb(); 5007 v = fl->dbval | V_PIDX(n); 5008 if (fl->udb) 5009 *fl->udb = htole32(v); 5010 else 5011 t4_write_reg(sc, sc->sge_kdoorbell_reg, v); 5012 IDXINCR(fl->dbidx, n, fl->sidx); 5013 } 5014 5015 /* 5016 * Fills up the freelist by allocating up to 'n' buffers. Buffers that are 5017 * recycled do not count towards this allocation budget. 5018 * 5019 * Returns non-zero to indicate that this freelist should be added to the list 5020 * of starving freelists. 5021 */ 5022 static int 5023 refill_fl(struct adapter *sc, struct sge_fl *fl, int n) 5024 { 5025 __be64 *d; 5026 struct fl_sdesc *sd; 5027 uintptr_t pa; 5028 caddr_t cl; 5029 struct rx_buf_info *rxb; 5030 struct cluster_metadata *clm; 5031 uint16_t max_pidx, zidx = fl->zidx; 5032 uint16_t hw_cidx = fl->hw_cidx; /* stable snapshot */ 5033 5034 FL_LOCK_ASSERT_OWNED(fl); 5035 5036 /* 5037 * We always stop at the beginning of the hardware descriptor that's just 5038 * before the one with the hw cidx. This is to avoid hw pidx = hw cidx, 5039 * which would mean an empty freelist to the chip. 5040 */ 5041 max_pidx = __predict_false(hw_cidx == 0) ? fl->sidx - 1 : hw_cidx - 1; 5042 if (fl->pidx == max_pidx * 8) 5043 return (0); 5044 5045 d = &fl->desc[fl->pidx]; 5046 sd = &fl->sdesc[fl->pidx]; 5047 rxb = &sc->sge.rx_buf_info[zidx]; 5048 5049 while (n > 0) { 5050 5051 if (sd->cl != NULL) { 5052 5053 if (sd->nmbuf == 0) { 5054 /* 5055 * Fast recycle without involving any atomics on 5056 * the cluster's metadata (if the cluster has 5057 * metadata). This happens when all frames 5058 * received in the cluster were small enough to 5059 * fit within a single mbuf each. 5060 */ 5061 fl->cl_fast_recycled++; 5062 goto recycled; 5063 } 5064 5065 /* 5066 * Cluster is guaranteed to have metadata. Clusters 5067 * without metadata always take the fast recycle path 5068 * when they're recycled. 5069 */ 5070 clm = cl_metadata(sd); 5071 MPASS(clm != NULL); 5072 5073 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) { 5074 fl->cl_recycled++; 5075 counter_u64_add(extfree_rels, 1); 5076 goto recycled; 5077 } 5078 sd->cl = NULL; /* gave up my reference */ 5079 } 5080 MPASS(sd->cl == NULL); 5081 cl = uma_zalloc(rxb->zone, M_NOWAIT); 5082 if (__predict_false(cl == NULL)) { 5083 if (zidx != fl->safe_zidx) { 5084 zidx = fl->safe_zidx; 5085 rxb = &sc->sge.rx_buf_info[zidx]; 5086 cl = uma_zalloc(rxb->zone, M_NOWAIT); 5087 } 5088 if (cl == NULL) 5089 break; 5090 } 5091 fl->cl_allocated++; 5092 n--; 5093 5094 pa = pmap_kextract((vm_offset_t)cl); 5095 sd->cl = cl; 5096 sd->zidx = zidx; 5097 5098 if (fl->flags & FL_BUF_PACKING) { 5099 *d = htobe64(pa | rxb->hwidx2); 5100 sd->moff = rxb->size2; 5101 } else { 5102 *d = htobe64(pa | rxb->hwidx1); 5103 sd->moff = 0; 5104 } 5105 recycled: 5106 sd->nmbuf = 0; 5107 d++; 5108 sd++; 5109 if (__predict_false((++fl->pidx & 7) == 0)) { 5110 uint16_t pidx = fl->pidx >> 3; 5111 5112 if (__predict_false(pidx == fl->sidx)) { 5113 fl->pidx = 0; 5114 pidx = 0; 5115 sd = fl->sdesc; 5116 d = fl->desc; 5117 } 5118 if (n < 8 || pidx == max_pidx) 5119 break; 5120 5121 if (IDXDIFF(pidx, fl->dbidx, fl->sidx) >= 4) 5122 ring_fl_db(sc, fl); 5123 } 5124 } 5125 5126 if ((fl->pidx >> 3) != fl->dbidx) 5127 ring_fl_db(sc, fl); 5128 5129 return (FL_RUNNING_LOW(fl) && !(fl->flags & FL_STARVING)); 5130 } 5131 5132 /* 5133 * Attempt to refill all starving freelists. 5134 */ 5135 static void 5136 refill_sfl(void *arg) 5137 { 5138 struct adapter *sc = arg; 5139 struct sge_fl *fl, *fl_temp; 5140 5141 mtx_assert(&sc->sfl_lock, MA_OWNED); 5142 TAILQ_FOREACH_SAFE(fl, &sc->sfl, link, fl_temp) { 5143 FL_LOCK(fl); 5144 refill_fl(sc, fl, 64); 5145 if (FL_NOT_RUNNING_LOW(fl) || fl->flags & FL_DOOMED) { 5146 TAILQ_REMOVE(&sc->sfl, fl, link); 5147 fl->flags &= ~FL_STARVING; 5148 } 5149 FL_UNLOCK(fl); 5150 } 5151 5152 if (!TAILQ_EMPTY(&sc->sfl)) 5153 callout_schedule(&sc->sfl_callout, hz / 5); 5154 } 5155 5156 /* 5157 * Release the driver's reference on all buffers in the given freelist. Buffers 5158 * with kernel references cannot be freed and will prevent the driver from being 5159 * unloaded safely. 5160 */ 5161 void 5162 free_fl_buffers(struct adapter *sc, struct sge_fl *fl) 5163 { 5164 struct fl_sdesc *sd; 5165 struct cluster_metadata *clm; 5166 int i; 5167 5168 sd = fl->sdesc; 5169 for (i = 0; i < fl->sidx * 8; i++, sd++) { 5170 if (sd->cl == NULL) 5171 continue; 5172 5173 if (sd->nmbuf == 0) 5174 uma_zfree(sc->sge.rx_buf_info[sd->zidx].zone, sd->cl); 5175 else if (fl->flags & FL_BUF_PACKING) { 5176 clm = cl_metadata(sd); 5177 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) { 5178 uma_zfree(sc->sge.rx_buf_info[sd->zidx].zone, 5179 sd->cl); 5180 counter_u64_add(extfree_rels, 1); 5181 } 5182 } 5183 sd->cl = NULL; 5184 } 5185 5186 if (fl->flags & FL_BUF_RESUME) { 5187 m_freem(fl->m0); 5188 fl->flags &= ~FL_BUF_RESUME; 5189 } 5190 } 5191 5192 static inline void 5193 get_pkt_gl(struct mbuf *m, struct sglist *gl) 5194 { 5195 int rc; 5196 5197 M_ASSERTPKTHDR(m); 5198 5199 sglist_reset(gl); 5200 rc = sglist_append_mbuf(gl, m); 5201 if (__predict_false(rc != 0)) { 5202 panic("%s: mbuf %p (%d segs) was vetted earlier but now fails " 5203 "with %d.", __func__, m, mbuf_nsegs(m), rc); 5204 } 5205 5206 KASSERT(gl->sg_nseg == mbuf_nsegs(m), 5207 ("%s: nsegs changed for mbuf %p from %d to %d", __func__, m, 5208 mbuf_nsegs(m), gl->sg_nseg)); 5209 #if 0 /* vm_wr not readily available here. */ 5210 KASSERT(gl->sg_nseg > 0 && gl->sg_nseg <= max_nsegs_allowed(m, vm_wr), 5211 ("%s: %d segments, should have been 1 <= nsegs <= %d", __func__, 5212 gl->sg_nseg, max_nsegs_allowed(m, vm_wr))); 5213 #endif 5214 } 5215 5216 /* 5217 * len16 for a txpkt WR with a GL. Includes the firmware work request header. 5218 */ 5219 static inline u_int 5220 txpkt_len16(u_int nsegs, const u_int extra) 5221 { 5222 u_int n; 5223 5224 MPASS(nsegs > 0); 5225 5226 nsegs--; /* first segment is part of ulptx_sgl */ 5227 n = extra + sizeof(struct fw_eth_tx_pkt_wr) + 5228 sizeof(struct cpl_tx_pkt_core) + 5229 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 5230 5231 return (howmany(n, 16)); 5232 } 5233 5234 /* 5235 * len16 for a txpkt_vm WR with a GL. Includes the firmware work 5236 * request header. 5237 */ 5238 static inline u_int 5239 txpkt_vm_len16(u_int nsegs, const u_int extra) 5240 { 5241 u_int n; 5242 5243 MPASS(nsegs > 0); 5244 5245 nsegs--; /* first segment is part of ulptx_sgl */ 5246 n = extra + sizeof(struct fw_eth_tx_pkt_vm_wr) + 5247 sizeof(struct cpl_tx_pkt_core) + 5248 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 5249 5250 return (howmany(n, 16)); 5251 } 5252 5253 static inline void 5254 calculate_mbuf_len16(struct mbuf *m, bool vm_wr) 5255 { 5256 const int lso = sizeof(struct cpl_tx_pkt_lso_core); 5257 const int tnl_lso = sizeof(struct cpl_tx_tnl_lso); 5258 5259 if (vm_wr) { 5260 if (needs_tso(m)) 5261 set_mbuf_len16(m, txpkt_vm_len16(mbuf_nsegs(m), lso)); 5262 else 5263 set_mbuf_len16(m, txpkt_vm_len16(mbuf_nsegs(m), 0)); 5264 return; 5265 } 5266 5267 if (needs_tso(m)) { 5268 if (needs_vxlan_tso(m)) 5269 set_mbuf_len16(m, txpkt_len16(mbuf_nsegs(m), tnl_lso)); 5270 else 5271 set_mbuf_len16(m, txpkt_len16(mbuf_nsegs(m), lso)); 5272 } else 5273 set_mbuf_len16(m, txpkt_len16(mbuf_nsegs(m), 0)); 5274 } 5275 5276 /* 5277 * len16 for a txpkts type 0 WR with a GL. Does not include the firmware work 5278 * request header. 5279 */ 5280 static inline u_int 5281 txpkts0_len16(u_int nsegs) 5282 { 5283 u_int n; 5284 5285 MPASS(nsegs > 0); 5286 5287 nsegs--; /* first segment is part of ulptx_sgl */ 5288 n = sizeof(struct ulp_txpkt) + sizeof(struct ulptx_idata) + 5289 sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl) + 5290 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 5291 5292 return (howmany(n, 16)); 5293 } 5294 5295 /* 5296 * len16 for a txpkts type 1 WR with a GL. Does not include the firmware work 5297 * request header. 5298 */ 5299 static inline u_int 5300 txpkts1_len16(void) 5301 { 5302 u_int n; 5303 5304 n = sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl); 5305 5306 return (howmany(n, 16)); 5307 } 5308 5309 static inline u_int 5310 imm_payload(u_int ndesc) 5311 { 5312 u_int n; 5313 5314 n = ndesc * EQ_ESIZE - sizeof(struct fw_eth_tx_pkt_wr) - 5315 sizeof(struct cpl_tx_pkt_core); 5316 5317 return (n); 5318 } 5319 5320 static inline uint64_t 5321 csum_to_ctrl(struct adapter *sc, struct mbuf *m) 5322 { 5323 uint64_t ctrl; 5324 int csum_type, l2hlen, l3hlen; 5325 int x, y; 5326 static const int csum_types[3][2] = { 5327 {TX_CSUM_TCPIP, TX_CSUM_TCPIP6}, 5328 {TX_CSUM_UDPIP, TX_CSUM_UDPIP6}, 5329 {TX_CSUM_IP, 0} 5330 }; 5331 5332 M_ASSERTPKTHDR(m); 5333 5334 if (!needs_hwcsum(m)) 5335 return (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS); 5336 5337 MPASS(m->m_pkthdr.l2hlen >= ETHER_HDR_LEN); 5338 MPASS(m->m_pkthdr.l3hlen >= sizeof(struct ip)); 5339 5340 if (needs_vxlan_csum(m)) { 5341 MPASS(m->m_pkthdr.l4hlen > 0); 5342 MPASS(m->m_pkthdr.l5hlen > 0); 5343 MPASS(m->m_pkthdr.inner_l2hlen >= ETHER_HDR_LEN); 5344 MPASS(m->m_pkthdr.inner_l3hlen >= sizeof(struct ip)); 5345 5346 l2hlen = m->m_pkthdr.l2hlen + m->m_pkthdr.l3hlen + 5347 m->m_pkthdr.l4hlen + m->m_pkthdr.l5hlen + 5348 m->m_pkthdr.inner_l2hlen - ETHER_HDR_LEN; 5349 l3hlen = m->m_pkthdr.inner_l3hlen; 5350 } else { 5351 l2hlen = m->m_pkthdr.l2hlen - ETHER_HDR_LEN; 5352 l3hlen = m->m_pkthdr.l3hlen; 5353 } 5354 5355 ctrl = 0; 5356 if (!needs_l3_csum(m)) 5357 ctrl |= F_TXPKT_IPCSUM_DIS; 5358 5359 if (m->m_pkthdr.csum_flags & (CSUM_IP_TCP | CSUM_INNER_IP_TCP | 5360 CSUM_IP6_TCP | CSUM_INNER_IP6_TCP)) 5361 x = 0; /* TCP */ 5362 else if (m->m_pkthdr.csum_flags & (CSUM_IP_UDP | CSUM_INNER_IP_UDP | 5363 CSUM_IP6_UDP | CSUM_INNER_IP6_UDP)) 5364 x = 1; /* UDP */ 5365 else 5366 x = 2; 5367 5368 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_IP_TCP | CSUM_IP_UDP | 5369 CSUM_INNER_IP | CSUM_INNER_IP_TCP | CSUM_INNER_IP_UDP)) 5370 y = 0; /* IPv4 */ 5371 else { 5372 MPASS(m->m_pkthdr.csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | 5373 CSUM_INNER_IP6_TCP | CSUM_INNER_IP6_UDP)); 5374 y = 1; /* IPv6 */ 5375 } 5376 /* 5377 * needs_hwcsum returned true earlier so there must be some kind of 5378 * checksum to calculate. 5379 */ 5380 csum_type = csum_types[x][y]; 5381 MPASS(csum_type != 0); 5382 if (csum_type == TX_CSUM_IP) 5383 ctrl |= F_TXPKT_L4CSUM_DIS; 5384 ctrl |= V_TXPKT_CSUM_TYPE(csum_type) | V_TXPKT_IPHDR_LEN(l3hlen); 5385 if (chip_id(sc) <= CHELSIO_T5) 5386 ctrl |= V_TXPKT_ETHHDR_LEN(l2hlen); 5387 else 5388 ctrl |= V_T6_TXPKT_ETHHDR_LEN(l2hlen); 5389 5390 return (ctrl); 5391 } 5392 5393 static inline void * 5394 write_lso_cpl(void *cpl, struct mbuf *m0) 5395 { 5396 struct cpl_tx_pkt_lso_core *lso; 5397 uint32_t ctrl; 5398 5399 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 5400 m0->m_pkthdr.l4hlen > 0, 5401 ("%s: mbuf %p needs TSO but missing header lengths", 5402 __func__, m0)); 5403 5404 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | 5405 F_LSO_FIRST_SLICE | F_LSO_LAST_SLICE | 5406 V_LSO_ETHHDR_LEN((m0->m_pkthdr.l2hlen - ETHER_HDR_LEN) >> 2) | 5407 V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) | 5408 V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2); 5409 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 5410 ctrl |= F_LSO_IPV6; 5411 5412 lso = cpl; 5413 lso->lso_ctrl = htobe32(ctrl); 5414 lso->ipid_ofst = htobe16(0); 5415 lso->mss = htobe16(m0->m_pkthdr.tso_segsz); 5416 lso->seqno_offset = htobe32(0); 5417 lso->len = htobe32(m0->m_pkthdr.len); 5418 5419 return (lso + 1); 5420 } 5421 5422 static void * 5423 write_tnl_lso_cpl(void *cpl, struct mbuf *m0) 5424 { 5425 struct cpl_tx_tnl_lso *tnl_lso = cpl; 5426 uint32_t ctrl; 5427 5428 KASSERT(m0->m_pkthdr.inner_l2hlen > 0 && 5429 m0->m_pkthdr.inner_l3hlen > 0 && m0->m_pkthdr.inner_l4hlen > 0 && 5430 m0->m_pkthdr.inner_l5hlen > 0, 5431 ("%s: mbuf %p needs VXLAN_TSO but missing inner header lengths", 5432 __func__, m0)); 5433 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 5434 m0->m_pkthdr.l4hlen > 0 && m0->m_pkthdr.l5hlen > 0, 5435 ("%s: mbuf %p needs VXLAN_TSO but missing outer header lengths", 5436 __func__, m0)); 5437 5438 /* Outer headers. */ 5439 ctrl = V_CPL_TX_TNL_LSO_OPCODE(CPL_TX_TNL_LSO) | 5440 F_CPL_TX_TNL_LSO_FIRST | F_CPL_TX_TNL_LSO_LAST | 5441 V_CPL_TX_TNL_LSO_ETHHDRLENOUT( 5442 (m0->m_pkthdr.l2hlen - ETHER_HDR_LEN) >> 2) | 5443 V_CPL_TX_TNL_LSO_IPHDRLENOUT(m0->m_pkthdr.l3hlen >> 2) | 5444 F_CPL_TX_TNL_LSO_IPLENSETOUT; 5445 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 5446 ctrl |= F_CPL_TX_TNL_LSO_IPV6OUT; 5447 else { 5448 ctrl |= F_CPL_TX_TNL_LSO_IPHDRCHKOUT | 5449 F_CPL_TX_TNL_LSO_IPIDINCOUT; 5450 } 5451 tnl_lso->op_to_IpIdSplitOut = htobe32(ctrl); 5452 tnl_lso->IpIdOffsetOut = 0; 5453 tnl_lso->UdpLenSetOut_to_TnlHdrLen = 5454 htobe16(F_CPL_TX_TNL_LSO_UDPCHKCLROUT | 5455 F_CPL_TX_TNL_LSO_UDPLENSETOUT | 5456 V_CPL_TX_TNL_LSO_TNLHDRLEN(m0->m_pkthdr.l2hlen + 5457 m0->m_pkthdr.l3hlen + m0->m_pkthdr.l4hlen + 5458 m0->m_pkthdr.l5hlen) | 5459 V_CPL_TX_TNL_LSO_TNLTYPE(TX_TNL_TYPE_VXLAN)); 5460 tnl_lso->r1 = 0; 5461 5462 /* Inner headers. */ 5463 ctrl = V_CPL_TX_TNL_LSO_ETHHDRLEN( 5464 (m0->m_pkthdr.inner_l2hlen - ETHER_HDR_LEN) >> 2) | 5465 V_CPL_TX_TNL_LSO_IPHDRLEN(m0->m_pkthdr.inner_l3hlen >> 2) | 5466 V_CPL_TX_TNL_LSO_TCPHDRLEN(m0->m_pkthdr.inner_l4hlen >> 2); 5467 if (m0->m_pkthdr.inner_l3hlen == sizeof(struct ip6_hdr)) 5468 ctrl |= F_CPL_TX_TNL_LSO_IPV6; 5469 tnl_lso->Flow_to_TcpHdrLen = htobe32(ctrl); 5470 tnl_lso->IpIdOffset = 0; 5471 tnl_lso->IpIdSplit_to_Mss = 5472 htobe16(V_CPL_TX_TNL_LSO_MSS(m0->m_pkthdr.tso_segsz)); 5473 tnl_lso->TCPSeqOffset = 0; 5474 tnl_lso->EthLenOffset_Size = 5475 htobe32(V_CPL_TX_TNL_LSO_SIZE(m0->m_pkthdr.len)); 5476 5477 return (tnl_lso + 1); 5478 } 5479 5480 #define VM_TX_L2HDR_LEN 16 /* ethmacdst to vlantci */ 5481 5482 /* 5483 * Write a VM txpkt WR for this packet to the hardware descriptors, update the 5484 * software descriptor, and advance the pidx. It is guaranteed that enough 5485 * descriptors are available. 5486 * 5487 * The return value is the # of hardware descriptors used. 5488 */ 5489 static u_int 5490 write_txpkt_vm_wr(struct adapter *sc, struct sge_txq *txq, struct mbuf *m0) 5491 { 5492 struct sge_eq *eq; 5493 struct fw_eth_tx_pkt_vm_wr *wr; 5494 struct tx_sdesc *txsd; 5495 struct cpl_tx_pkt_core *cpl; 5496 uint32_t ctrl; /* used in many unrelated places */ 5497 uint64_t ctrl1; 5498 int len16, ndesc, pktlen; 5499 caddr_t dst; 5500 5501 TXQ_LOCK_ASSERT_OWNED(txq); 5502 M_ASSERTPKTHDR(m0); 5503 5504 len16 = mbuf_len16(m0); 5505 pktlen = m0->m_pkthdr.len; 5506 ctrl = sizeof(struct cpl_tx_pkt_core); 5507 if (needs_tso(m0)) 5508 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 5509 ndesc = tx_len16_to_desc(len16); 5510 5511 /* Firmware work request header */ 5512 eq = &txq->eq; 5513 wr = (void *)&eq->desc[eq->pidx]; 5514 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_VM_WR) | 5515 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl)); 5516 5517 ctrl = V_FW_WR_LEN16(len16); 5518 wr->equiq_to_len16 = htobe32(ctrl); 5519 wr->r3[0] = 0; 5520 wr->r3[1] = 0; 5521 5522 /* 5523 * Copy over ethmacdst, ethmacsrc, ethtype, and vlantci. 5524 * vlantci is ignored unless the ethtype is 0x8100, so it's 5525 * simpler to always copy it rather than making it 5526 * conditional. Also, it seems that we do not have to set 5527 * vlantci or fake the ethtype when doing VLAN tag insertion. 5528 */ 5529 m_copydata(m0, 0, VM_TX_L2HDR_LEN, wr->ethmacdst); 5530 5531 if (needs_tso(m0)) { 5532 cpl = write_lso_cpl(wr + 1, m0); 5533 txq->tso_wrs++; 5534 } else 5535 cpl = (void *)(wr + 1); 5536 5537 /* Checksum offload */ 5538 ctrl1 = csum_to_ctrl(sc, m0); 5539 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS)) 5540 txq->txcsum++; /* some hardware assistance provided */ 5541 5542 /* VLAN tag insertion */ 5543 if (needs_vlan_insertion(m0)) { 5544 ctrl1 |= F_TXPKT_VLAN_VLD | 5545 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 5546 txq->vlan_insertion++; 5547 } 5548 5549 /* CPL header */ 5550 cpl->ctrl0 = txq->cpl_ctrl0; 5551 cpl->pack = 0; 5552 cpl->len = htobe16(pktlen); 5553 cpl->ctrl1 = htobe64(ctrl1); 5554 5555 /* SGL */ 5556 dst = (void *)(cpl + 1); 5557 5558 /* 5559 * A packet using TSO will use up an entire descriptor for the 5560 * firmware work request header, LSO CPL, and TX_PKT_XT CPL. 5561 * If this descriptor is the last descriptor in the ring, wrap 5562 * around to the front of the ring explicitly for the start of 5563 * the sgl. 5564 */ 5565 if (dst == (void *)&eq->desc[eq->sidx]) { 5566 dst = (void *)&eq->desc[0]; 5567 write_gl_to_txd(txq, m0, &dst, 0); 5568 } else 5569 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx); 5570 txq->sgl_wrs++; 5571 txq->txpkt_wrs++; 5572 5573 txsd = &txq->sdesc[eq->pidx]; 5574 txsd->m = m0; 5575 txsd->desc_used = ndesc; 5576 5577 return (ndesc); 5578 } 5579 5580 /* 5581 * Write a raw WR to the hardware descriptors, update the software 5582 * descriptor, and advance the pidx. It is guaranteed that enough 5583 * descriptors are available. 5584 * 5585 * The return value is the # of hardware descriptors used. 5586 */ 5587 static u_int 5588 write_raw_wr(struct sge_txq *txq, void *wr, struct mbuf *m0, u_int available) 5589 { 5590 struct sge_eq *eq = &txq->eq; 5591 struct tx_sdesc *txsd; 5592 struct mbuf *m; 5593 caddr_t dst; 5594 int len16, ndesc; 5595 5596 len16 = mbuf_len16(m0); 5597 ndesc = tx_len16_to_desc(len16); 5598 MPASS(ndesc <= available); 5599 5600 dst = wr; 5601 for (m = m0; m != NULL; m = m->m_next) 5602 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len); 5603 5604 txq->raw_wrs++; 5605 5606 txsd = &txq->sdesc[eq->pidx]; 5607 txsd->m = m0; 5608 txsd->desc_used = ndesc; 5609 5610 return (ndesc); 5611 } 5612 5613 /* 5614 * Write a txpkt WR for this packet to the hardware descriptors, update the 5615 * software descriptor, and advance the pidx. It is guaranteed that enough 5616 * descriptors are available. 5617 * 5618 * The return value is the # of hardware descriptors used. 5619 */ 5620 static u_int 5621 write_txpkt_wr(struct adapter *sc, struct sge_txq *txq, struct mbuf *m0, 5622 u_int available) 5623 { 5624 struct sge_eq *eq; 5625 struct fw_eth_tx_pkt_wr *wr; 5626 struct tx_sdesc *txsd; 5627 struct cpl_tx_pkt_core *cpl; 5628 uint32_t ctrl; /* used in many unrelated places */ 5629 uint64_t ctrl1; 5630 int len16, ndesc, pktlen, nsegs; 5631 caddr_t dst; 5632 5633 TXQ_LOCK_ASSERT_OWNED(txq); 5634 M_ASSERTPKTHDR(m0); 5635 5636 len16 = mbuf_len16(m0); 5637 nsegs = mbuf_nsegs(m0); 5638 pktlen = m0->m_pkthdr.len; 5639 ctrl = sizeof(struct cpl_tx_pkt_core); 5640 if (needs_tso(m0)) { 5641 if (needs_vxlan_tso(m0)) 5642 ctrl += sizeof(struct cpl_tx_tnl_lso); 5643 else 5644 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 5645 } else if (!(mbuf_cflags(m0) & MC_NOMAP) && pktlen <= imm_payload(2) && 5646 available >= 2) { 5647 /* Immediate data. Recalculate len16 and set nsegs to 0. */ 5648 ctrl += pktlen; 5649 len16 = howmany(sizeof(struct fw_eth_tx_pkt_wr) + 5650 sizeof(struct cpl_tx_pkt_core) + pktlen, 16); 5651 nsegs = 0; 5652 } 5653 ndesc = tx_len16_to_desc(len16); 5654 MPASS(ndesc <= available); 5655 5656 /* Firmware work request header */ 5657 eq = &txq->eq; 5658 wr = (void *)&eq->desc[eq->pidx]; 5659 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_WR) | 5660 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl)); 5661 5662 ctrl = V_FW_WR_LEN16(len16); 5663 wr->equiq_to_len16 = htobe32(ctrl); 5664 wr->r3 = 0; 5665 5666 if (needs_tso(m0)) { 5667 if (needs_vxlan_tso(m0)) { 5668 cpl = write_tnl_lso_cpl(wr + 1, m0); 5669 txq->vxlan_tso_wrs++; 5670 } else { 5671 cpl = write_lso_cpl(wr + 1, m0); 5672 txq->tso_wrs++; 5673 } 5674 } else 5675 cpl = (void *)(wr + 1); 5676 5677 /* Checksum offload */ 5678 ctrl1 = csum_to_ctrl(sc, m0); 5679 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS)) { 5680 /* some hardware assistance provided */ 5681 if (needs_vxlan_csum(m0)) 5682 txq->vxlan_txcsum++; 5683 else 5684 txq->txcsum++; 5685 } 5686 5687 /* VLAN tag insertion */ 5688 if (needs_vlan_insertion(m0)) { 5689 ctrl1 |= F_TXPKT_VLAN_VLD | 5690 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 5691 txq->vlan_insertion++; 5692 } 5693 5694 /* CPL header */ 5695 cpl->ctrl0 = txq->cpl_ctrl0; 5696 cpl->pack = 0; 5697 cpl->len = htobe16(pktlen); 5698 cpl->ctrl1 = htobe64(ctrl1); 5699 5700 /* SGL */ 5701 dst = (void *)(cpl + 1); 5702 if (__predict_false((uintptr_t)dst == (uintptr_t)&eq->desc[eq->sidx])) 5703 dst = (caddr_t)&eq->desc[0]; 5704 if (nsegs > 0) { 5705 5706 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx); 5707 txq->sgl_wrs++; 5708 } else { 5709 struct mbuf *m; 5710 5711 for (m = m0; m != NULL; m = m->m_next) { 5712 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len); 5713 #ifdef INVARIANTS 5714 pktlen -= m->m_len; 5715 #endif 5716 } 5717 #ifdef INVARIANTS 5718 KASSERT(pktlen == 0, ("%s: %d bytes left.", __func__, pktlen)); 5719 #endif 5720 txq->imm_wrs++; 5721 } 5722 5723 txq->txpkt_wrs++; 5724 5725 txsd = &txq->sdesc[eq->pidx]; 5726 txsd->m = m0; 5727 txsd->desc_used = ndesc; 5728 5729 return (ndesc); 5730 } 5731 5732 static inline bool 5733 cmp_l2hdr(struct txpkts *txp, struct mbuf *m) 5734 { 5735 int len; 5736 5737 MPASS(txp->npkt > 0); 5738 MPASS(m->m_len >= VM_TX_L2HDR_LEN); 5739 5740 if (txp->ethtype == be16toh(ETHERTYPE_VLAN)) 5741 len = VM_TX_L2HDR_LEN; 5742 else 5743 len = sizeof(struct ether_header); 5744 5745 return (memcmp(m->m_data, &txp->ethmacdst[0], len) != 0); 5746 } 5747 5748 static inline void 5749 save_l2hdr(struct txpkts *txp, struct mbuf *m) 5750 { 5751 MPASS(m->m_len >= VM_TX_L2HDR_LEN); 5752 5753 memcpy(&txp->ethmacdst[0], mtod(m, const void *), VM_TX_L2HDR_LEN); 5754 } 5755 5756 static int 5757 add_to_txpkts_vf(struct adapter *sc, struct sge_txq *txq, struct mbuf *m, 5758 int avail, bool *send) 5759 { 5760 struct txpkts *txp = &txq->txp; 5761 5762 /* Cannot have TSO and coalesce at the same time. */ 5763 if (cannot_use_txpkts(m)) { 5764 cannot_coalesce: 5765 *send = txp->npkt > 0; 5766 return (EINVAL); 5767 } 5768 5769 /* VF allows coalescing of type 1 (1 GL) only */ 5770 if (mbuf_nsegs(m) > 1) 5771 goto cannot_coalesce; 5772 5773 *send = false; 5774 if (txp->npkt > 0) { 5775 MPASS(tx_len16_to_desc(txp->len16) <= avail); 5776 MPASS(txp->npkt < txp->max_npkt); 5777 MPASS(txp->wr_type == 1); /* VF supports type 1 only */ 5778 5779 if (tx_len16_to_desc(txp->len16 + txpkts1_len16()) > avail) { 5780 retry_after_send: 5781 *send = true; 5782 return (EAGAIN); 5783 } 5784 if (m->m_pkthdr.len + txp->plen > 65535) 5785 goto retry_after_send; 5786 if (cmp_l2hdr(txp, m)) 5787 goto retry_after_send; 5788 5789 txp->len16 += txpkts1_len16(); 5790 txp->plen += m->m_pkthdr.len; 5791 txp->mb[txp->npkt++] = m; 5792 if (txp->npkt == txp->max_npkt) 5793 *send = true; 5794 } else { 5795 txp->len16 = howmany(sizeof(struct fw_eth_tx_pkts_vm_wr), 16) + 5796 txpkts1_len16(); 5797 if (tx_len16_to_desc(txp->len16) > avail) 5798 goto cannot_coalesce; 5799 txp->npkt = 1; 5800 txp->wr_type = 1; 5801 txp->plen = m->m_pkthdr.len; 5802 txp->mb[0] = m; 5803 save_l2hdr(txp, m); 5804 } 5805 return (0); 5806 } 5807 5808 static int 5809 add_to_txpkts_pf(struct adapter *sc, struct sge_txq *txq, struct mbuf *m, 5810 int avail, bool *send) 5811 { 5812 struct txpkts *txp = &txq->txp; 5813 int nsegs; 5814 5815 MPASS(!(sc->flags & IS_VF)); 5816 5817 /* Cannot have TSO and coalesce at the same time. */ 5818 if (cannot_use_txpkts(m)) { 5819 cannot_coalesce: 5820 *send = txp->npkt > 0; 5821 return (EINVAL); 5822 } 5823 5824 *send = false; 5825 nsegs = mbuf_nsegs(m); 5826 if (txp->npkt == 0) { 5827 if (m->m_pkthdr.len > 65535) 5828 goto cannot_coalesce; 5829 if (nsegs > 1) { 5830 txp->wr_type = 0; 5831 txp->len16 = 5832 howmany(sizeof(struct fw_eth_tx_pkts_wr), 16) + 5833 txpkts0_len16(nsegs); 5834 } else { 5835 txp->wr_type = 1; 5836 txp->len16 = 5837 howmany(sizeof(struct fw_eth_tx_pkts_wr), 16) + 5838 txpkts1_len16(); 5839 } 5840 if (tx_len16_to_desc(txp->len16) > avail) 5841 goto cannot_coalesce; 5842 txp->npkt = 1; 5843 txp->plen = m->m_pkthdr.len; 5844 txp->mb[0] = m; 5845 } else { 5846 MPASS(tx_len16_to_desc(txp->len16) <= avail); 5847 MPASS(txp->npkt < txp->max_npkt); 5848 5849 if (m->m_pkthdr.len + txp->plen > 65535) { 5850 retry_after_send: 5851 *send = true; 5852 return (EAGAIN); 5853 } 5854 5855 MPASS(txp->wr_type == 0 || txp->wr_type == 1); 5856 if (txp->wr_type == 0) { 5857 if (tx_len16_to_desc(txp->len16 + 5858 txpkts0_len16(nsegs)) > min(avail, SGE_MAX_WR_NDESC)) 5859 goto retry_after_send; 5860 txp->len16 += txpkts0_len16(nsegs); 5861 } else { 5862 if (nsegs != 1) 5863 goto retry_after_send; 5864 if (tx_len16_to_desc(txp->len16 + txpkts1_len16()) > 5865 avail) 5866 goto retry_after_send; 5867 txp->len16 += txpkts1_len16(); 5868 } 5869 5870 txp->plen += m->m_pkthdr.len; 5871 txp->mb[txp->npkt++] = m; 5872 if (txp->npkt == txp->max_npkt) 5873 *send = true; 5874 } 5875 return (0); 5876 } 5877 5878 /* 5879 * Write a txpkts WR for the packets in txp to the hardware descriptors, update 5880 * the software descriptor, and advance the pidx. It is guaranteed that enough 5881 * descriptors are available. 5882 * 5883 * The return value is the # of hardware descriptors used. 5884 */ 5885 static u_int 5886 write_txpkts_wr(struct adapter *sc, struct sge_txq *txq) 5887 { 5888 const struct txpkts *txp = &txq->txp; 5889 struct sge_eq *eq = &txq->eq; 5890 struct fw_eth_tx_pkts_wr *wr; 5891 struct tx_sdesc *txsd; 5892 struct cpl_tx_pkt_core *cpl; 5893 uint64_t ctrl1; 5894 int ndesc, i, checkwrap; 5895 struct mbuf *m, *last; 5896 void *flitp; 5897 5898 TXQ_LOCK_ASSERT_OWNED(txq); 5899 MPASS(txp->npkt > 0); 5900 MPASS(txp->len16 <= howmany(SGE_MAX_WR_LEN, 16)); 5901 5902 wr = (void *)&eq->desc[eq->pidx]; 5903 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR)); 5904 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(txp->len16)); 5905 wr->plen = htobe16(txp->plen); 5906 wr->npkt = txp->npkt; 5907 wr->r3 = 0; 5908 wr->type = txp->wr_type; 5909 flitp = wr + 1; 5910 5911 /* 5912 * At this point we are 16B into a hardware descriptor. If checkwrap is 5913 * set then we know the WR is going to wrap around somewhere. We'll 5914 * check for that at appropriate points. 5915 */ 5916 ndesc = tx_len16_to_desc(txp->len16); 5917 last = NULL; 5918 checkwrap = eq->sidx - ndesc < eq->pidx; 5919 for (i = 0; i < txp->npkt; i++) { 5920 m = txp->mb[i]; 5921 if (txp->wr_type == 0) { 5922 struct ulp_txpkt *ulpmc; 5923 struct ulptx_idata *ulpsc; 5924 5925 /* ULP master command */ 5926 ulpmc = flitp; 5927 ulpmc->cmd_dest = htobe32(V_ULPTX_CMD(ULP_TX_PKT) | 5928 V_ULP_TXPKT_DEST(0) | V_ULP_TXPKT_FID(eq->iqid)); 5929 ulpmc->len = htobe32(txpkts0_len16(mbuf_nsegs(m))); 5930 5931 /* ULP subcommand */ 5932 ulpsc = (void *)(ulpmc + 1); 5933 ulpsc->cmd_more = htobe32(V_ULPTX_CMD(ULP_TX_SC_IMM) | 5934 F_ULP_TX_SC_MORE); 5935 ulpsc->len = htobe32(sizeof(struct cpl_tx_pkt_core)); 5936 5937 cpl = (void *)(ulpsc + 1); 5938 if (checkwrap && 5939 (uintptr_t)cpl == (uintptr_t)&eq->desc[eq->sidx]) 5940 cpl = (void *)&eq->desc[0]; 5941 } else { 5942 cpl = flitp; 5943 } 5944 5945 /* Checksum offload */ 5946 ctrl1 = csum_to_ctrl(sc, m); 5947 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS)) { 5948 /* some hardware assistance provided */ 5949 if (needs_vxlan_csum(m)) 5950 txq->vxlan_txcsum++; 5951 else 5952 txq->txcsum++; 5953 } 5954 5955 /* VLAN tag insertion */ 5956 if (needs_vlan_insertion(m)) { 5957 ctrl1 |= F_TXPKT_VLAN_VLD | 5958 V_TXPKT_VLAN(m->m_pkthdr.ether_vtag); 5959 txq->vlan_insertion++; 5960 } 5961 5962 /* CPL header */ 5963 cpl->ctrl0 = txq->cpl_ctrl0; 5964 cpl->pack = 0; 5965 cpl->len = htobe16(m->m_pkthdr.len); 5966 cpl->ctrl1 = htobe64(ctrl1); 5967 5968 flitp = cpl + 1; 5969 if (checkwrap && 5970 (uintptr_t)flitp == (uintptr_t)&eq->desc[eq->sidx]) 5971 flitp = (void *)&eq->desc[0]; 5972 5973 write_gl_to_txd(txq, m, (caddr_t *)(&flitp), checkwrap); 5974 5975 if (last != NULL) 5976 last->m_nextpkt = m; 5977 last = m; 5978 } 5979 5980 txq->sgl_wrs++; 5981 if (txp->wr_type == 0) { 5982 txq->txpkts0_pkts += txp->npkt; 5983 txq->txpkts0_wrs++; 5984 } else { 5985 txq->txpkts1_pkts += txp->npkt; 5986 txq->txpkts1_wrs++; 5987 } 5988 5989 txsd = &txq->sdesc[eq->pidx]; 5990 txsd->m = txp->mb[0]; 5991 txsd->desc_used = ndesc; 5992 5993 return (ndesc); 5994 } 5995 5996 static u_int 5997 write_txpkts_vm_wr(struct adapter *sc, struct sge_txq *txq) 5998 { 5999 const struct txpkts *txp = &txq->txp; 6000 struct sge_eq *eq = &txq->eq; 6001 struct fw_eth_tx_pkts_vm_wr *wr; 6002 struct tx_sdesc *txsd; 6003 struct cpl_tx_pkt_core *cpl; 6004 uint64_t ctrl1; 6005 int ndesc, i; 6006 struct mbuf *m, *last; 6007 void *flitp; 6008 6009 TXQ_LOCK_ASSERT_OWNED(txq); 6010 MPASS(txp->npkt > 0); 6011 MPASS(txp->wr_type == 1); /* VF supports type 1 only */ 6012 MPASS(txp->mb[0] != NULL); 6013 MPASS(txp->len16 <= howmany(SGE_MAX_WR_LEN, 16)); 6014 6015 wr = (void *)&eq->desc[eq->pidx]; 6016 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_VM_WR)); 6017 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(txp->len16)); 6018 wr->r3 = 0; 6019 wr->plen = htobe16(txp->plen); 6020 wr->npkt = txp->npkt; 6021 wr->r4 = 0; 6022 memcpy(&wr->ethmacdst[0], &txp->ethmacdst[0], 16); 6023 flitp = wr + 1; 6024 6025 /* 6026 * At this point we are 32B into a hardware descriptor. Each mbuf in 6027 * the WR will take 32B so we check for the end of the descriptor ring 6028 * before writing odd mbufs (mb[1], 3, 5, ..) 6029 */ 6030 ndesc = tx_len16_to_desc(txp->len16); 6031 last = NULL; 6032 for (i = 0; i < txp->npkt; i++) { 6033 m = txp->mb[i]; 6034 if (i & 1 && (uintptr_t)flitp == (uintptr_t)&eq->desc[eq->sidx]) 6035 flitp = &eq->desc[0]; 6036 cpl = flitp; 6037 6038 /* Checksum offload */ 6039 ctrl1 = csum_to_ctrl(sc, m); 6040 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS)) 6041 txq->txcsum++; /* some hardware assistance provided */ 6042 6043 /* VLAN tag insertion */ 6044 if (needs_vlan_insertion(m)) { 6045 ctrl1 |= F_TXPKT_VLAN_VLD | 6046 V_TXPKT_VLAN(m->m_pkthdr.ether_vtag); 6047 txq->vlan_insertion++; 6048 } 6049 6050 /* CPL header */ 6051 cpl->ctrl0 = txq->cpl_ctrl0; 6052 cpl->pack = 0; 6053 cpl->len = htobe16(m->m_pkthdr.len); 6054 cpl->ctrl1 = htobe64(ctrl1); 6055 6056 flitp = cpl + 1; 6057 MPASS(mbuf_nsegs(m) == 1); 6058 write_gl_to_txd(txq, m, (caddr_t *)(&flitp), 0); 6059 6060 if (last != NULL) 6061 last->m_nextpkt = m; 6062 last = m; 6063 } 6064 6065 txq->sgl_wrs++; 6066 txq->txpkts1_pkts += txp->npkt; 6067 txq->txpkts1_wrs++; 6068 6069 txsd = &txq->sdesc[eq->pidx]; 6070 txsd->m = txp->mb[0]; 6071 txsd->desc_used = ndesc; 6072 6073 return (ndesc); 6074 } 6075 6076 /* 6077 * If the SGL ends on an address that is not 16 byte aligned, this function will 6078 * add a 0 filled flit at the end. 6079 */ 6080 static void 6081 write_gl_to_txd(struct sge_txq *txq, struct mbuf *m, caddr_t *to, int checkwrap) 6082 { 6083 struct sge_eq *eq = &txq->eq; 6084 struct sglist *gl = txq->gl; 6085 struct sglist_seg *seg; 6086 __be64 *flitp, *wrap; 6087 struct ulptx_sgl *usgl; 6088 int i, nflits, nsegs; 6089 6090 KASSERT(((uintptr_t)(*to) & 0xf) == 0, 6091 ("%s: SGL must start at a 16 byte boundary: %p", __func__, *to)); 6092 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]); 6093 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]); 6094 6095 get_pkt_gl(m, gl); 6096 nsegs = gl->sg_nseg; 6097 MPASS(nsegs > 0); 6098 6099 nflits = (3 * (nsegs - 1)) / 2 + ((nsegs - 1) & 1) + 2; 6100 flitp = (__be64 *)(*to); 6101 wrap = (__be64 *)(&eq->desc[eq->sidx]); 6102 seg = &gl->sg_segs[0]; 6103 usgl = (void *)flitp; 6104 6105 /* 6106 * We start at a 16 byte boundary somewhere inside the tx descriptor 6107 * ring, so we're at least 16 bytes away from the status page. There is 6108 * no chance of a wrap around in the middle of usgl (which is 16 bytes). 6109 */ 6110 6111 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 6112 V_ULPTX_NSGE(nsegs)); 6113 usgl->len0 = htobe32(seg->ss_len); 6114 usgl->addr0 = htobe64(seg->ss_paddr); 6115 seg++; 6116 6117 if (checkwrap == 0 || (uintptr_t)(flitp + nflits) <= (uintptr_t)wrap) { 6118 6119 /* Won't wrap around at all */ 6120 6121 for (i = 0; i < nsegs - 1; i++, seg++) { 6122 usgl->sge[i / 2].len[i & 1] = htobe32(seg->ss_len); 6123 usgl->sge[i / 2].addr[i & 1] = htobe64(seg->ss_paddr); 6124 } 6125 if (i & 1) 6126 usgl->sge[i / 2].len[1] = htobe32(0); 6127 flitp += nflits; 6128 } else { 6129 6130 /* Will wrap somewhere in the rest of the SGL */ 6131 6132 /* 2 flits already written, write the rest flit by flit */ 6133 flitp = (void *)(usgl + 1); 6134 for (i = 0; i < nflits - 2; i++) { 6135 if (flitp == wrap) 6136 flitp = (void *)eq->desc; 6137 *flitp++ = get_flit(seg, nsegs - 1, i); 6138 } 6139 } 6140 6141 if (nflits & 1) { 6142 MPASS(((uintptr_t)flitp) & 0xf); 6143 *flitp++ = 0; 6144 } 6145 6146 MPASS((((uintptr_t)flitp) & 0xf) == 0); 6147 if (__predict_false(flitp == wrap)) 6148 *to = (void *)eq->desc; 6149 else 6150 *to = (void *)flitp; 6151 } 6152 6153 static inline void 6154 copy_to_txd(struct sge_eq *eq, caddr_t from, caddr_t *to, int len) 6155 { 6156 6157 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]); 6158 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]); 6159 6160 if (__predict_true((uintptr_t)(*to) + len <= 6161 (uintptr_t)&eq->desc[eq->sidx])) { 6162 bcopy(from, *to, len); 6163 (*to) += len; 6164 } else { 6165 int portion = (uintptr_t)&eq->desc[eq->sidx] - (uintptr_t)(*to); 6166 6167 bcopy(from, *to, portion); 6168 from += portion; 6169 portion = len - portion; /* remaining */ 6170 bcopy(from, (void *)eq->desc, portion); 6171 (*to) = (caddr_t)eq->desc + portion; 6172 } 6173 } 6174 6175 static inline void 6176 ring_eq_db(struct adapter *sc, struct sge_eq *eq, u_int n) 6177 { 6178 u_int db; 6179 6180 MPASS(n > 0); 6181 6182 db = eq->doorbells; 6183 if (n > 1) 6184 clrbit(&db, DOORBELL_WCWR); 6185 wmb(); 6186 6187 switch (ffs(db) - 1) { 6188 case DOORBELL_UDB: 6189 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n)); 6190 break; 6191 6192 case DOORBELL_WCWR: { 6193 volatile uint64_t *dst, *src; 6194 int i; 6195 6196 /* 6197 * Queues whose 128B doorbell segment fits in the page do not 6198 * use relative qid (udb_qid is always 0). Only queues with 6199 * doorbell segments can do WCWR. 6200 */ 6201 KASSERT(eq->udb_qid == 0 && n == 1, 6202 ("%s: inappropriate doorbell (0x%x, %d, %d) for eq %p", 6203 __func__, eq->doorbells, n, eq->dbidx, eq)); 6204 6205 dst = (volatile void *)((uintptr_t)eq->udb + UDBS_WR_OFFSET - 6206 UDBS_DB_OFFSET); 6207 i = eq->dbidx; 6208 src = (void *)&eq->desc[i]; 6209 while (src != (void *)&eq->desc[i + 1]) 6210 *dst++ = *src++; 6211 wmb(); 6212 break; 6213 } 6214 6215 case DOORBELL_UDBWC: 6216 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n)); 6217 wmb(); 6218 break; 6219 6220 case DOORBELL_KDB: 6221 t4_write_reg(sc, sc->sge_kdoorbell_reg, 6222 V_QID(eq->cntxt_id) | V_PIDX(n)); 6223 break; 6224 } 6225 6226 IDXINCR(eq->dbidx, n, eq->sidx); 6227 } 6228 6229 static inline u_int 6230 reclaimable_tx_desc(struct sge_eq *eq) 6231 { 6232 uint16_t hw_cidx; 6233 6234 hw_cidx = read_hw_cidx(eq); 6235 return (IDXDIFF(hw_cidx, eq->cidx, eq->sidx)); 6236 } 6237 6238 static inline u_int 6239 total_available_tx_desc(struct sge_eq *eq) 6240 { 6241 uint16_t hw_cidx, pidx; 6242 6243 hw_cidx = read_hw_cidx(eq); 6244 pidx = eq->pidx; 6245 6246 if (pidx == hw_cidx) 6247 return (eq->sidx - 1); 6248 else 6249 return (IDXDIFF(hw_cidx, pidx, eq->sidx) - 1); 6250 } 6251 6252 static inline uint16_t 6253 read_hw_cidx(struct sge_eq *eq) 6254 { 6255 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx]; 6256 uint16_t cidx = spg->cidx; /* stable snapshot */ 6257 6258 return (be16toh(cidx)); 6259 } 6260 6261 /* 6262 * Reclaim 'n' descriptors approximately. 6263 */ 6264 static u_int 6265 reclaim_tx_descs(struct sge_txq *txq, u_int n) 6266 { 6267 struct tx_sdesc *txsd; 6268 struct sge_eq *eq = &txq->eq; 6269 u_int can_reclaim, reclaimed; 6270 6271 TXQ_LOCK_ASSERT_OWNED(txq); 6272 MPASS(n > 0); 6273 6274 reclaimed = 0; 6275 can_reclaim = reclaimable_tx_desc(eq); 6276 while (can_reclaim && reclaimed < n) { 6277 int ndesc; 6278 struct mbuf *m, *nextpkt; 6279 6280 txsd = &txq->sdesc[eq->cidx]; 6281 ndesc = txsd->desc_used; 6282 6283 /* Firmware doesn't return "partial" credits. */ 6284 KASSERT(can_reclaim >= ndesc, 6285 ("%s: unexpected number of credits: %d, %d", 6286 __func__, can_reclaim, ndesc)); 6287 KASSERT(ndesc != 0, 6288 ("%s: descriptor with no credits: cidx %d", 6289 __func__, eq->cidx)); 6290 6291 for (m = txsd->m; m != NULL; m = nextpkt) { 6292 nextpkt = m->m_nextpkt; 6293 m->m_nextpkt = NULL; 6294 m_freem(m); 6295 } 6296 reclaimed += ndesc; 6297 can_reclaim -= ndesc; 6298 IDXINCR(eq->cidx, ndesc, eq->sidx); 6299 } 6300 6301 return (reclaimed); 6302 } 6303 6304 static void 6305 tx_reclaim(void *arg, int n) 6306 { 6307 struct sge_txq *txq = arg; 6308 struct sge_eq *eq = &txq->eq; 6309 6310 do { 6311 if (TXQ_TRYLOCK(txq) == 0) 6312 break; 6313 n = reclaim_tx_descs(txq, 32); 6314 if (eq->cidx == eq->pidx) 6315 eq->equeqidx = eq->pidx; 6316 TXQ_UNLOCK(txq); 6317 } while (n > 0); 6318 } 6319 6320 static __be64 6321 get_flit(struct sglist_seg *segs, int nsegs, int idx) 6322 { 6323 int i = (idx / 3) * 2; 6324 6325 switch (idx % 3) { 6326 case 0: { 6327 uint64_t rc; 6328 6329 rc = (uint64_t)segs[i].ss_len << 32; 6330 if (i + 1 < nsegs) 6331 rc |= (uint64_t)(segs[i + 1].ss_len); 6332 6333 return (htobe64(rc)); 6334 } 6335 case 1: 6336 return (htobe64(segs[i].ss_paddr)); 6337 case 2: 6338 return (htobe64(segs[i + 1].ss_paddr)); 6339 } 6340 6341 return (0); 6342 } 6343 6344 static int 6345 find_refill_source(struct adapter *sc, int maxp, bool packing) 6346 { 6347 int i, zidx = -1; 6348 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[0]; 6349 6350 if (packing) { 6351 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) { 6352 if (rxb->hwidx2 == -1) 6353 continue; 6354 if (rxb->size1 < PAGE_SIZE && 6355 rxb->size1 < largest_rx_cluster) 6356 continue; 6357 if (rxb->size1 > largest_rx_cluster) 6358 break; 6359 MPASS(rxb->size1 - rxb->size2 >= CL_METADATA_SIZE); 6360 if (rxb->size2 >= maxp) 6361 return (i); 6362 zidx = i; 6363 } 6364 } else { 6365 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) { 6366 if (rxb->hwidx1 == -1) 6367 continue; 6368 if (rxb->size1 > largest_rx_cluster) 6369 break; 6370 if (rxb->size1 >= maxp) 6371 return (i); 6372 zidx = i; 6373 } 6374 } 6375 6376 return (zidx); 6377 } 6378 6379 static void 6380 add_fl_to_sfl(struct adapter *sc, struct sge_fl *fl) 6381 { 6382 mtx_lock(&sc->sfl_lock); 6383 FL_LOCK(fl); 6384 if ((fl->flags & FL_DOOMED) == 0) { 6385 fl->flags |= FL_STARVING; 6386 TAILQ_INSERT_TAIL(&sc->sfl, fl, link); 6387 callout_reset(&sc->sfl_callout, hz / 5, refill_sfl, sc); 6388 } 6389 FL_UNLOCK(fl); 6390 mtx_unlock(&sc->sfl_lock); 6391 } 6392 6393 static void 6394 handle_wrq_egr_update(struct adapter *sc, struct sge_eq *eq) 6395 { 6396 struct sge_wrq *wrq = (void *)eq; 6397 6398 atomic_readandclear_int(&eq->equiq); 6399 taskqueue_enqueue(sc->tq[eq->tx_chan], &wrq->wrq_tx_task); 6400 } 6401 6402 static void 6403 handle_eth_egr_update(struct adapter *sc, struct sge_eq *eq) 6404 { 6405 struct sge_txq *txq = (void *)eq; 6406 6407 MPASS(eq->type == EQ_ETH); 6408 6409 atomic_readandclear_int(&eq->equiq); 6410 if (mp_ring_is_idle(txq->r)) 6411 taskqueue_enqueue(sc->tq[eq->tx_chan], &txq->tx_reclaim_task); 6412 else 6413 mp_ring_check_drainage(txq->r, 64); 6414 } 6415 6416 static int 6417 handle_sge_egr_update(struct sge_iq *iq, const struct rss_header *rss, 6418 struct mbuf *m) 6419 { 6420 const struct cpl_sge_egr_update *cpl = (const void *)(rss + 1); 6421 unsigned int qid = G_EGR_QID(ntohl(cpl->opcode_qid)); 6422 struct adapter *sc = iq->adapter; 6423 struct sge *s = &sc->sge; 6424 struct sge_eq *eq; 6425 static void (*h[])(struct adapter *, struct sge_eq *) = {NULL, 6426 &handle_wrq_egr_update, &handle_eth_egr_update, 6427 &handle_wrq_egr_update}; 6428 6429 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 6430 rss->opcode)); 6431 6432 eq = s->eqmap[qid - s->eq_start - s->eq_base]; 6433 (*h[eq->type])(sc, eq); 6434 6435 return (0); 6436 } 6437 6438 /* handle_fw_msg works for both fw4_msg and fw6_msg because this is valid */ 6439 CTASSERT(offsetof(struct cpl_fw4_msg, data) == \ 6440 offsetof(struct cpl_fw6_msg, data)); 6441 6442 static int 6443 handle_fw_msg(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 6444 { 6445 struct adapter *sc = iq->adapter; 6446 const struct cpl_fw6_msg *cpl = (const void *)(rss + 1); 6447 6448 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 6449 rss->opcode)); 6450 6451 if (cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL) { 6452 const struct rss_header *rss2; 6453 6454 rss2 = (const struct rss_header *)&cpl->data[0]; 6455 return (t4_cpl_handler[rss2->opcode](iq, rss2, m)); 6456 } 6457 6458 return (t4_fw_msg_handler[cpl->type](sc, &cpl->data[0])); 6459 } 6460 6461 /** 6462 * t4_handle_wrerr_rpl - process a FW work request error message 6463 * @adap: the adapter 6464 * @rpl: start of the FW message 6465 */ 6466 static int 6467 t4_handle_wrerr_rpl(struct adapter *adap, const __be64 *rpl) 6468 { 6469 u8 opcode = *(const u8 *)rpl; 6470 const struct fw_error_cmd *e = (const void *)rpl; 6471 unsigned int i; 6472 6473 if (opcode != FW_ERROR_CMD) { 6474 log(LOG_ERR, 6475 "%s: Received WRERR_RPL message with opcode %#x\n", 6476 device_get_nameunit(adap->dev), opcode); 6477 return (EINVAL); 6478 } 6479 log(LOG_ERR, "%s: FW_ERROR (%s) ", device_get_nameunit(adap->dev), 6480 G_FW_ERROR_CMD_FATAL(be32toh(e->op_to_type)) ? "fatal" : 6481 "non-fatal"); 6482 switch (G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type))) { 6483 case FW_ERROR_TYPE_EXCEPTION: 6484 log(LOG_ERR, "exception info:\n"); 6485 for (i = 0; i < nitems(e->u.exception.info); i++) 6486 log(LOG_ERR, "%s%08x", i == 0 ? "\t" : " ", 6487 be32toh(e->u.exception.info[i])); 6488 log(LOG_ERR, "\n"); 6489 break; 6490 case FW_ERROR_TYPE_HWMODULE: 6491 log(LOG_ERR, "HW module regaddr %08x regval %08x\n", 6492 be32toh(e->u.hwmodule.regaddr), 6493 be32toh(e->u.hwmodule.regval)); 6494 break; 6495 case FW_ERROR_TYPE_WR: 6496 log(LOG_ERR, "WR cidx %d PF %d VF %d eqid %d hdr:\n", 6497 be16toh(e->u.wr.cidx), 6498 G_FW_ERROR_CMD_PFN(be16toh(e->u.wr.pfn_vfn)), 6499 G_FW_ERROR_CMD_VFN(be16toh(e->u.wr.pfn_vfn)), 6500 be32toh(e->u.wr.eqid)); 6501 for (i = 0; i < nitems(e->u.wr.wrhdr); i++) 6502 log(LOG_ERR, "%s%02x", i == 0 ? "\t" : " ", 6503 e->u.wr.wrhdr[i]); 6504 log(LOG_ERR, "\n"); 6505 break; 6506 case FW_ERROR_TYPE_ACL: 6507 log(LOG_ERR, "ACL cidx %d PF %d VF %d eqid %d %s", 6508 be16toh(e->u.acl.cidx), 6509 G_FW_ERROR_CMD_PFN(be16toh(e->u.acl.pfn_vfn)), 6510 G_FW_ERROR_CMD_VFN(be16toh(e->u.acl.pfn_vfn)), 6511 be32toh(e->u.acl.eqid), 6512 G_FW_ERROR_CMD_MV(be16toh(e->u.acl.mv_pkd)) ? "vlanid" : 6513 "MAC"); 6514 for (i = 0; i < nitems(e->u.acl.val); i++) 6515 log(LOG_ERR, " %02x", e->u.acl.val[i]); 6516 log(LOG_ERR, "\n"); 6517 break; 6518 default: 6519 log(LOG_ERR, "type %#x\n", 6520 G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type))); 6521 return (EINVAL); 6522 } 6523 return (0); 6524 } 6525 6526 static inline bool 6527 bufidx_used(struct adapter *sc, int idx) 6528 { 6529 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[0]; 6530 int i; 6531 6532 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) { 6533 if (rxb->size1 > largest_rx_cluster) 6534 continue; 6535 if (rxb->hwidx1 == idx || rxb->hwidx2 == idx) 6536 return (true); 6537 } 6538 6539 return (false); 6540 } 6541 6542 static int 6543 sysctl_bufsizes(SYSCTL_HANDLER_ARGS) 6544 { 6545 struct adapter *sc = arg1; 6546 struct sge_params *sp = &sc->params.sge; 6547 int i, rc; 6548 struct sbuf sb; 6549 char c; 6550 6551 sbuf_new(&sb, NULL, 128, SBUF_AUTOEXTEND); 6552 for (i = 0; i < SGE_FLBUF_SIZES; i++) { 6553 if (bufidx_used(sc, i)) 6554 c = '*'; 6555 else 6556 c = '\0'; 6557 6558 sbuf_printf(&sb, "%u%c ", sp->sge_fl_buffer_size[i], c); 6559 } 6560 sbuf_trim(&sb); 6561 sbuf_finish(&sb); 6562 rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req); 6563 sbuf_delete(&sb); 6564 return (rc); 6565 } 6566 6567 #ifdef RATELIMIT 6568 #if defined(INET) || defined(INET6) 6569 /* 6570 * len16 for a txpkt WR with a GL. Includes the firmware work request header. 6571 */ 6572 static inline u_int 6573 txpkt_eo_len16(u_int nsegs, u_int immhdrs, u_int tso) 6574 { 6575 u_int n; 6576 6577 MPASS(immhdrs > 0); 6578 6579 n = roundup2(sizeof(struct fw_eth_tx_eo_wr) + 6580 sizeof(struct cpl_tx_pkt_core) + immhdrs, 16); 6581 if (__predict_false(nsegs == 0)) 6582 goto done; 6583 6584 nsegs--; /* first segment is part of ulptx_sgl */ 6585 n += sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 6586 if (tso) 6587 n += sizeof(struct cpl_tx_pkt_lso_core); 6588 6589 done: 6590 return (howmany(n, 16)); 6591 } 6592 #endif 6593 6594 #define ETID_FLOWC_NPARAMS 6 6595 #define ETID_FLOWC_LEN (roundup2((sizeof(struct fw_flowc_wr) + \ 6596 ETID_FLOWC_NPARAMS * sizeof(struct fw_flowc_mnemval)), 16)) 6597 #define ETID_FLOWC_LEN16 (howmany(ETID_FLOWC_LEN, 16)) 6598 6599 static int 6600 send_etid_flowc_wr(struct cxgbe_rate_tag *cst, struct port_info *pi, 6601 struct vi_info *vi) 6602 { 6603 struct wrq_cookie cookie; 6604 u_int pfvf = pi->adapter->pf << S_FW_VIID_PFN; 6605 struct fw_flowc_wr *flowc; 6606 6607 mtx_assert(&cst->lock, MA_OWNED); 6608 MPASS((cst->flags & (EO_FLOWC_PENDING | EO_FLOWC_RPL_PENDING)) == 6609 EO_FLOWC_PENDING); 6610 6611 flowc = start_wrq_wr(&cst->eo_txq->wrq, ETID_FLOWC_LEN16, &cookie); 6612 if (__predict_false(flowc == NULL)) 6613 return (ENOMEM); 6614 6615 bzero(flowc, ETID_FLOWC_LEN); 6616 flowc->op_to_nparams = htobe32(V_FW_WR_OP(FW_FLOWC_WR) | 6617 V_FW_FLOWC_WR_NPARAMS(ETID_FLOWC_NPARAMS) | V_FW_WR_COMPL(0)); 6618 flowc->flowid_len16 = htonl(V_FW_WR_LEN16(ETID_FLOWC_LEN16) | 6619 V_FW_WR_FLOWID(cst->etid)); 6620 flowc->mnemval[0].mnemonic = FW_FLOWC_MNEM_PFNVFN; 6621 flowc->mnemval[0].val = htobe32(pfvf); 6622 flowc->mnemval[1].mnemonic = FW_FLOWC_MNEM_CH; 6623 flowc->mnemval[1].val = htobe32(pi->tx_chan); 6624 flowc->mnemval[2].mnemonic = FW_FLOWC_MNEM_PORT; 6625 flowc->mnemval[2].val = htobe32(pi->tx_chan); 6626 flowc->mnemval[3].mnemonic = FW_FLOWC_MNEM_IQID; 6627 flowc->mnemval[3].val = htobe32(cst->iqid); 6628 flowc->mnemval[4].mnemonic = FW_FLOWC_MNEM_EOSTATE; 6629 flowc->mnemval[4].val = htobe32(FW_FLOWC_MNEM_EOSTATE_ESTABLISHED); 6630 flowc->mnemval[5].mnemonic = FW_FLOWC_MNEM_SCHEDCLASS; 6631 flowc->mnemval[5].val = htobe32(cst->schedcl); 6632 6633 commit_wrq_wr(&cst->eo_txq->wrq, flowc, &cookie); 6634 6635 cst->flags &= ~EO_FLOWC_PENDING; 6636 cst->flags |= EO_FLOWC_RPL_PENDING; 6637 MPASS(cst->tx_credits >= ETID_FLOWC_LEN16); /* flowc is first WR. */ 6638 cst->tx_credits -= ETID_FLOWC_LEN16; 6639 6640 return (0); 6641 } 6642 6643 #define ETID_FLUSH_LEN16 (howmany(sizeof (struct fw_flowc_wr), 16)) 6644 6645 void 6646 send_etid_flush_wr(struct cxgbe_rate_tag *cst) 6647 { 6648 struct fw_flowc_wr *flowc; 6649 struct wrq_cookie cookie; 6650 6651 mtx_assert(&cst->lock, MA_OWNED); 6652 6653 flowc = start_wrq_wr(&cst->eo_txq->wrq, ETID_FLUSH_LEN16, &cookie); 6654 if (__predict_false(flowc == NULL)) 6655 CXGBE_UNIMPLEMENTED(__func__); 6656 6657 bzero(flowc, ETID_FLUSH_LEN16 * 16); 6658 flowc->op_to_nparams = htobe32(V_FW_WR_OP(FW_FLOWC_WR) | 6659 V_FW_FLOWC_WR_NPARAMS(0) | F_FW_WR_COMPL); 6660 flowc->flowid_len16 = htobe32(V_FW_WR_LEN16(ETID_FLUSH_LEN16) | 6661 V_FW_WR_FLOWID(cst->etid)); 6662 6663 commit_wrq_wr(&cst->eo_txq->wrq, flowc, &cookie); 6664 6665 cst->flags |= EO_FLUSH_RPL_PENDING; 6666 MPASS(cst->tx_credits >= ETID_FLUSH_LEN16); 6667 cst->tx_credits -= ETID_FLUSH_LEN16; 6668 cst->ncompl++; 6669 } 6670 6671 static void 6672 write_ethofld_wr(struct cxgbe_rate_tag *cst, struct fw_eth_tx_eo_wr *wr, 6673 struct mbuf *m0, int compl) 6674 { 6675 struct cpl_tx_pkt_core *cpl; 6676 uint64_t ctrl1; 6677 uint32_t ctrl; /* used in many unrelated places */ 6678 int len16, pktlen, nsegs, immhdrs; 6679 uintptr_t p; 6680 struct ulptx_sgl *usgl; 6681 struct sglist sg; 6682 struct sglist_seg segs[38]; /* XXX: find real limit. XXX: get off the stack */ 6683 6684 mtx_assert(&cst->lock, MA_OWNED); 6685 M_ASSERTPKTHDR(m0); 6686 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 6687 m0->m_pkthdr.l4hlen > 0, 6688 ("%s: ethofld mbuf %p is missing header lengths", __func__, m0)); 6689 6690 len16 = mbuf_eo_len16(m0); 6691 nsegs = mbuf_eo_nsegs(m0); 6692 pktlen = m0->m_pkthdr.len; 6693 ctrl = sizeof(struct cpl_tx_pkt_core); 6694 if (needs_tso(m0)) 6695 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 6696 immhdrs = m0->m_pkthdr.l2hlen + m0->m_pkthdr.l3hlen + m0->m_pkthdr.l4hlen; 6697 ctrl += immhdrs; 6698 6699 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_EO_WR) | 6700 V_FW_ETH_TX_EO_WR_IMMDLEN(ctrl) | V_FW_WR_COMPL(!!compl)); 6701 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(len16) | 6702 V_FW_WR_FLOWID(cst->etid)); 6703 wr->r3 = 0; 6704 if (needs_outer_udp_csum(m0)) { 6705 wr->u.udpseg.type = FW_ETH_TX_EO_TYPE_UDPSEG; 6706 wr->u.udpseg.ethlen = m0->m_pkthdr.l2hlen; 6707 wr->u.udpseg.iplen = htobe16(m0->m_pkthdr.l3hlen); 6708 wr->u.udpseg.udplen = m0->m_pkthdr.l4hlen; 6709 wr->u.udpseg.rtplen = 0; 6710 wr->u.udpseg.r4 = 0; 6711 wr->u.udpseg.mss = htobe16(pktlen - immhdrs); 6712 wr->u.udpseg.schedpktsize = wr->u.udpseg.mss; 6713 wr->u.udpseg.plen = htobe32(pktlen - immhdrs); 6714 cpl = (void *)(wr + 1); 6715 } else { 6716 MPASS(needs_outer_tcp_csum(m0)); 6717 wr->u.tcpseg.type = FW_ETH_TX_EO_TYPE_TCPSEG; 6718 wr->u.tcpseg.ethlen = m0->m_pkthdr.l2hlen; 6719 wr->u.tcpseg.iplen = htobe16(m0->m_pkthdr.l3hlen); 6720 wr->u.tcpseg.tcplen = m0->m_pkthdr.l4hlen; 6721 wr->u.tcpseg.tsclk_tsoff = mbuf_eo_tsclk_tsoff(m0); 6722 wr->u.tcpseg.r4 = 0; 6723 wr->u.tcpseg.r5 = 0; 6724 wr->u.tcpseg.plen = htobe32(pktlen - immhdrs); 6725 6726 if (needs_tso(m0)) { 6727 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1); 6728 6729 wr->u.tcpseg.mss = htobe16(m0->m_pkthdr.tso_segsz); 6730 6731 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | 6732 F_LSO_FIRST_SLICE | F_LSO_LAST_SLICE | 6733 V_LSO_ETHHDR_LEN((m0->m_pkthdr.l2hlen - 6734 ETHER_HDR_LEN) >> 2) | 6735 V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) | 6736 V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2); 6737 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 6738 ctrl |= F_LSO_IPV6; 6739 lso->lso_ctrl = htobe32(ctrl); 6740 lso->ipid_ofst = htobe16(0); 6741 lso->mss = htobe16(m0->m_pkthdr.tso_segsz); 6742 lso->seqno_offset = htobe32(0); 6743 lso->len = htobe32(pktlen); 6744 6745 cpl = (void *)(lso + 1); 6746 } else { 6747 wr->u.tcpseg.mss = htobe16(0xffff); 6748 cpl = (void *)(wr + 1); 6749 } 6750 } 6751 6752 /* Checksum offload must be requested for ethofld. */ 6753 MPASS(needs_outer_l4_csum(m0)); 6754 ctrl1 = csum_to_ctrl(cst->adapter, m0); 6755 6756 /* VLAN tag insertion */ 6757 if (needs_vlan_insertion(m0)) { 6758 ctrl1 |= F_TXPKT_VLAN_VLD | 6759 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 6760 } 6761 6762 /* CPL header */ 6763 cpl->ctrl0 = cst->ctrl0; 6764 cpl->pack = 0; 6765 cpl->len = htobe16(pktlen); 6766 cpl->ctrl1 = htobe64(ctrl1); 6767 6768 /* Copy Ethernet, IP & TCP/UDP hdrs as immediate data */ 6769 p = (uintptr_t)(cpl + 1); 6770 m_copydata(m0, 0, immhdrs, (void *)p); 6771 6772 /* SGL */ 6773 if (nsegs > 0) { 6774 int i, pad; 6775 6776 /* zero-pad upto next 16Byte boundary, if not 16Byte aligned */ 6777 p += immhdrs; 6778 pad = 16 - (immhdrs & 0xf); 6779 bzero((void *)p, pad); 6780 6781 usgl = (void *)(p + pad); 6782 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 6783 V_ULPTX_NSGE(nsegs)); 6784 6785 sglist_init(&sg, nitems(segs), segs); 6786 for (; m0 != NULL; m0 = m0->m_next) { 6787 if (__predict_false(m0->m_len == 0)) 6788 continue; 6789 if (immhdrs >= m0->m_len) { 6790 immhdrs -= m0->m_len; 6791 continue; 6792 } 6793 if (m0->m_flags & M_EXTPG) 6794 sglist_append_mbuf_epg(&sg, m0, 6795 mtod(m0, vm_offset_t), m0->m_len); 6796 else 6797 sglist_append(&sg, mtod(m0, char *) + immhdrs, 6798 m0->m_len - immhdrs); 6799 immhdrs = 0; 6800 } 6801 MPASS(sg.sg_nseg == nsegs); 6802 6803 /* 6804 * Zero pad last 8B in case the WR doesn't end on a 16B 6805 * boundary. 6806 */ 6807 *(uint64_t *)((char *)wr + len16 * 16 - 8) = 0; 6808 6809 usgl->len0 = htobe32(segs[0].ss_len); 6810 usgl->addr0 = htobe64(segs[0].ss_paddr); 6811 for (i = 0; i < nsegs - 1; i++) { 6812 usgl->sge[i / 2].len[i & 1] = htobe32(segs[i + 1].ss_len); 6813 usgl->sge[i / 2].addr[i & 1] = htobe64(segs[i + 1].ss_paddr); 6814 } 6815 if (i & 1) 6816 usgl->sge[i / 2].len[1] = htobe32(0); 6817 } 6818 6819 } 6820 6821 static void 6822 ethofld_tx(struct cxgbe_rate_tag *cst) 6823 { 6824 struct mbuf *m; 6825 struct wrq_cookie cookie; 6826 int next_credits, compl; 6827 struct fw_eth_tx_eo_wr *wr; 6828 6829 mtx_assert(&cst->lock, MA_OWNED); 6830 6831 while ((m = mbufq_first(&cst->pending_tx)) != NULL) { 6832 M_ASSERTPKTHDR(m); 6833 6834 /* How many len16 credits do we need to send this mbuf. */ 6835 next_credits = mbuf_eo_len16(m); 6836 MPASS(next_credits > 0); 6837 if (next_credits > cst->tx_credits) { 6838 /* 6839 * Tx will make progress eventually because there is at 6840 * least one outstanding fw4_ack that will return 6841 * credits and kick the tx. 6842 */ 6843 MPASS(cst->ncompl > 0); 6844 return; 6845 } 6846 wr = start_wrq_wr(&cst->eo_txq->wrq, next_credits, &cookie); 6847 if (__predict_false(wr == NULL)) { 6848 /* XXX: wishful thinking, not a real assertion. */ 6849 MPASS(cst->ncompl > 0); 6850 return; 6851 } 6852 cst->tx_credits -= next_credits; 6853 cst->tx_nocompl += next_credits; 6854 compl = cst->ncompl == 0 || cst->tx_nocompl >= cst->tx_total / 2; 6855 ETHER_BPF_MTAP(cst->com.ifp, m); 6856 write_ethofld_wr(cst, wr, m, compl); 6857 commit_wrq_wr(&cst->eo_txq->wrq, wr, &cookie); 6858 if (compl) { 6859 cst->ncompl++; 6860 cst->tx_nocompl = 0; 6861 } 6862 (void) mbufq_dequeue(&cst->pending_tx); 6863 6864 /* 6865 * Drop the mbuf's reference on the tag now rather 6866 * than waiting until m_freem(). This ensures that 6867 * cxgbe_rate_tag_free gets called when the inp drops 6868 * its reference on the tag and there are no more 6869 * mbufs in the pending_tx queue and can flush any 6870 * pending requests. Otherwise if the last mbuf 6871 * doesn't request a completion the etid will never be 6872 * released. 6873 */ 6874 m->m_pkthdr.snd_tag = NULL; 6875 m->m_pkthdr.csum_flags &= ~CSUM_SND_TAG; 6876 m_snd_tag_rele(&cst->com); 6877 6878 mbufq_enqueue(&cst->pending_fwack, m); 6879 } 6880 } 6881 6882 int 6883 ethofld_transmit(struct ifnet *ifp, struct mbuf *m0) 6884 { 6885 struct cxgbe_rate_tag *cst; 6886 int rc; 6887 6888 MPASS(m0->m_nextpkt == NULL); 6889 MPASS(m0->m_pkthdr.csum_flags & CSUM_SND_TAG); 6890 MPASS(m0->m_pkthdr.snd_tag != NULL); 6891 cst = mst_to_crt(m0->m_pkthdr.snd_tag); 6892 6893 mtx_lock(&cst->lock); 6894 MPASS(cst->flags & EO_SND_TAG_REF); 6895 6896 if (__predict_false(cst->flags & EO_FLOWC_PENDING)) { 6897 struct vi_info *vi = ifp->if_softc; 6898 struct port_info *pi = vi->pi; 6899 struct adapter *sc = pi->adapter; 6900 const uint32_t rss_mask = vi->rss_size - 1; 6901 uint32_t rss_hash; 6902 6903 cst->eo_txq = &sc->sge.ofld_txq[vi->first_ofld_txq]; 6904 if (M_HASHTYPE_ISHASH(m0)) 6905 rss_hash = m0->m_pkthdr.flowid; 6906 else 6907 rss_hash = arc4random(); 6908 /* We assume RSS hashing */ 6909 cst->iqid = vi->rss[rss_hash & rss_mask]; 6910 cst->eo_txq += rss_hash % vi->nofldtxq; 6911 rc = send_etid_flowc_wr(cst, pi, vi); 6912 if (rc != 0) 6913 goto done; 6914 } 6915 6916 if (__predict_false(cst->plen + m0->m_pkthdr.len > eo_max_backlog)) { 6917 rc = ENOBUFS; 6918 goto done; 6919 } 6920 6921 mbufq_enqueue(&cst->pending_tx, m0); 6922 cst->plen += m0->m_pkthdr.len; 6923 6924 /* 6925 * Hold an extra reference on the tag while generating work 6926 * requests to ensure that we don't try to free the tag during 6927 * ethofld_tx() in case we are sending the final mbuf after 6928 * the inp was freed. 6929 */ 6930 m_snd_tag_ref(&cst->com); 6931 ethofld_tx(cst); 6932 mtx_unlock(&cst->lock); 6933 m_snd_tag_rele(&cst->com); 6934 return (0); 6935 6936 done: 6937 mtx_unlock(&cst->lock); 6938 if (__predict_false(rc != 0)) 6939 m_freem(m0); 6940 return (rc); 6941 } 6942 6943 static int 6944 ethofld_fw4_ack(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0) 6945 { 6946 struct adapter *sc = iq->adapter; 6947 const struct cpl_fw4_ack *cpl = (const void *)(rss + 1); 6948 struct mbuf *m; 6949 u_int etid = G_CPL_FW4_ACK_FLOWID(be32toh(OPCODE_TID(cpl))); 6950 struct cxgbe_rate_tag *cst; 6951 uint8_t credits = cpl->credits; 6952 6953 cst = lookup_etid(sc, etid); 6954 mtx_lock(&cst->lock); 6955 if (__predict_false(cst->flags & EO_FLOWC_RPL_PENDING)) { 6956 MPASS(credits >= ETID_FLOWC_LEN16); 6957 credits -= ETID_FLOWC_LEN16; 6958 cst->flags &= ~EO_FLOWC_RPL_PENDING; 6959 } 6960 6961 KASSERT(cst->ncompl > 0, 6962 ("%s: etid %u (%p) wasn't expecting completion.", 6963 __func__, etid, cst)); 6964 cst->ncompl--; 6965 6966 while (credits > 0) { 6967 m = mbufq_dequeue(&cst->pending_fwack); 6968 if (__predict_false(m == NULL)) { 6969 /* 6970 * The remaining credits are for the final flush that 6971 * was issued when the tag was freed by the kernel. 6972 */ 6973 MPASS((cst->flags & 6974 (EO_FLUSH_RPL_PENDING | EO_SND_TAG_REF)) == 6975 EO_FLUSH_RPL_PENDING); 6976 MPASS(credits == ETID_FLUSH_LEN16); 6977 MPASS(cst->tx_credits + cpl->credits == cst->tx_total); 6978 MPASS(cst->ncompl == 0); 6979 6980 cst->flags &= ~EO_FLUSH_RPL_PENDING; 6981 cst->tx_credits += cpl->credits; 6982 cxgbe_rate_tag_free_locked(cst); 6983 return (0); /* cst is gone. */ 6984 } 6985 KASSERT(m != NULL, 6986 ("%s: too many credits (%u, %u)", __func__, cpl->credits, 6987 credits)); 6988 KASSERT(credits >= mbuf_eo_len16(m), 6989 ("%s: too few credits (%u, %u, %u)", __func__, 6990 cpl->credits, credits, mbuf_eo_len16(m))); 6991 credits -= mbuf_eo_len16(m); 6992 cst->plen -= m->m_pkthdr.len; 6993 m_freem(m); 6994 } 6995 6996 cst->tx_credits += cpl->credits; 6997 MPASS(cst->tx_credits <= cst->tx_total); 6998 6999 if (cst->flags & EO_SND_TAG_REF) { 7000 /* 7001 * As with ethofld_transmit(), hold an extra reference 7002 * so that the tag is stable across ethold_tx(). 7003 */ 7004 m_snd_tag_ref(&cst->com); 7005 m = mbufq_first(&cst->pending_tx); 7006 if (m != NULL && cst->tx_credits >= mbuf_eo_len16(m)) 7007 ethofld_tx(cst); 7008 mtx_unlock(&cst->lock); 7009 m_snd_tag_rele(&cst->com); 7010 } else { 7011 /* 7012 * There shouldn't be any pending packets if the tag 7013 * was freed by the kernel since any pending packet 7014 * should hold a reference to the tag. 7015 */ 7016 MPASS(mbufq_first(&cst->pending_tx) == NULL); 7017 mtx_unlock(&cst->lock); 7018 } 7019 7020 return (0); 7021 } 7022 #endif 7023