1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 Chelsio Communications, Inc. 5 * All rights reserved. 6 * Written by: Navdeep Parhar <np@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include "opt_inet.h" 34 #include "opt_inet6.h" 35 #include "opt_ratelimit.h" 36 37 #include <sys/types.h> 38 #include <sys/eventhandler.h> 39 #include <sys/mbuf.h> 40 #include <sys/socket.h> 41 #include <sys/kernel.h> 42 #include <sys/malloc.h> 43 #include <sys/queue.h> 44 #include <sys/sbuf.h> 45 #include <sys/taskqueue.h> 46 #include <sys/time.h> 47 #include <sys/sglist.h> 48 #include <sys/sysctl.h> 49 #include <sys/smp.h> 50 #include <sys/counter.h> 51 #include <net/bpf.h> 52 #include <net/ethernet.h> 53 #include <net/if.h> 54 #include <net/if_vlan_var.h> 55 #include <netinet/in.h> 56 #include <netinet/ip.h> 57 #include <netinet/ip6.h> 58 #include <netinet/tcp.h> 59 #include <netinet/udp.h> 60 #include <machine/in_cksum.h> 61 #include <machine/md_var.h> 62 #include <vm/vm.h> 63 #include <vm/pmap.h> 64 #ifdef DEV_NETMAP 65 #include <machine/bus.h> 66 #include <sys/selinfo.h> 67 #include <net/if_var.h> 68 #include <net/netmap.h> 69 #include <dev/netmap/netmap_kern.h> 70 #endif 71 72 #include "common/common.h" 73 #include "common/t4_regs.h" 74 #include "common/t4_regs_values.h" 75 #include "common/t4_msg.h" 76 #include "t4_l2t.h" 77 #include "t4_mp_ring.h" 78 79 #ifdef T4_PKT_TIMESTAMP 80 #define RX_COPY_THRESHOLD (MINCLSIZE - 8) 81 #else 82 #define RX_COPY_THRESHOLD MINCLSIZE 83 #endif 84 85 /* 86 * Ethernet frames are DMA'd at this byte offset into the freelist buffer. 87 * 0-7 are valid values. 88 */ 89 static int fl_pktshift = 0; 90 TUNABLE_INT("hw.cxgbe.fl_pktshift", &fl_pktshift); 91 92 /* 93 * Pad ethernet payload up to this boundary. 94 * -1: driver should figure out a good value. 95 * 0: disable padding. 96 * Any power of 2 from 32 to 4096 (both inclusive) is also a valid value. 97 */ 98 int fl_pad = -1; 99 TUNABLE_INT("hw.cxgbe.fl_pad", &fl_pad); 100 101 /* 102 * Status page length. 103 * -1: driver should figure out a good value. 104 * 64 or 128 are the only other valid values. 105 */ 106 static int spg_len = -1; 107 TUNABLE_INT("hw.cxgbe.spg_len", &spg_len); 108 109 /* 110 * Congestion drops. 111 * -1: no congestion feedback (not recommended). 112 * 0: backpressure the channel instead of dropping packets right away. 113 * 1: no backpressure, drop packets for the congested queue immediately. 114 */ 115 static int cong_drop = 0; 116 TUNABLE_INT("hw.cxgbe.cong_drop", &cong_drop); 117 118 /* 119 * Deliver multiple frames in the same free list buffer if they fit. 120 * -1: let the driver decide whether to enable buffer packing or not. 121 * 0: disable buffer packing. 122 * 1: enable buffer packing. 123 */ 124 static int buffer_packing = -1; 125 TUNABLE_INT("hw.cxgbe.buffer_packing", &buffer_packing); 126 127 /* 128 * Start next frame in a packed buffer at this boundary. 129 * -1: driver should figure out a good value. 130 * T4: driver will ignore this and use the same value as fl_pad above. 131 * T5: 16, or a power of 2 from 64 to 4096 (both inclusive) is a valid value. 132 */ 133 static int fl_pack = -1; 134 TUNABLE_INT("hw.cxgbe.fl_pack", &fl_pack); 135 136 /* 137 * Allow the driver to create mbuf(s) in a cluster allocated for rx. 138 * 0: never; always allocate mbufs from the zone_mbuf UMA zone. 139 * 1: ok to create mbuf(s) within a cluster if there is room. 140 */ 141 static int allow_mbufs_in_cluster = 1; 142 TUNABLE_INT("hw.cxgbe.allow_mbufs_in_cluster", &allow_mbufs_in_cluster); 143 144 /* 145 * Largest rx cluster size that the driver is allowed to allocate. 146 */ 147 static int largest_rx_cluster = MJUM16BYTES; 148 TUNABLE_INT("hw.cxgbe.largest_rx_cluster", &largest_rx_cluster); 149 150 /* 151 * Size of cluster allocation that's most likely to succeed. The driver will 152 * fall back to this size if it fails to allocate clusters larger than this. 153 */ 154 static int safest_rx_cluster = PAGE_SIZE; 155 TUNABLE_INT("hw.cxgbe.safest_rx_cluster", &safest_rx_cluster); 156 157 #ifdef RATELIMIT 158 /* 159 * Knob to control TCP timestamp rewriting, and the granularity of the tick used 160 * for rewriting. -1 and 0-3 are all valid values. 161 * -1: hardware should leave the TCP timestamps alone. 162 * 0: 1ms 163 * 1: 100us 164 * 2: 10us 165 * 3: 1us 166 */ 167 static int tsclk = -1; 168 TUNABLE_INT("hw.cxgbe.tsclk", &tsclk); 169 170 static int eo_max_backlog = 1024 * 1024; 171 TUNABLE_INT("hw.cxgbe.eo_max_backlog", &eo_max_backlog); 172 #endif 173 174 /* 175 * The interrupt holdoff timers are multiplied by this value on T6+. 176 * 1 and 3-17 (both inclusive) are legal values. 177 */ 178 static int tscale = 1; 179 TUNABLE_INT("hw.cxgbe.tscale", &tscale); 180 181 /* 182 * Number of LRO entries in the lro_ctrl structure per rx queue. 183 */ 184 static int lro_entries = TCP_LRO_ENTRIES; 185 TUNABLE_INT("hw.cxgbe.lro_entries", &lro_entries); 186 187 /* 188 * This enables presorting of frames before they're fed into tcp_lro_rx. 189 */ 190 static int lro_mbufs = 0; 191 TUNABLE_INT("hw.cxgbe.lro_mbufs", &lro_mbufs); 192 193 struct txpkts { 194 u_int wr_type; /* type 0 or type 1 */ 195 u_int npkt; /* # of packets in this work request */ 196 u_int plen; /* total payload (sum of all packets) */ 197 u_int len16; /* # of 16B pieces used by this work request */ 198 }; 199 200 /* A packet's SGL. This + m_pkthdr has all info needed for tx */ 201 struct sgl { 202 struct sglist sg; 203 struct sglist_seg seg[TX_SGL_SEGS]; 204 }; 205 206 static int service_iq(struct sge_iq *, int); 207 static int service_iq_fl(struct sge_iq *, int); 208 static struct mbuf *get_fl_payload(struct adapter *, struct sge_fl *, uint32_t); 209 static int t4_eth_rx(struct sge_iq *, const struct rss_header *, struct mbuf *); 210 static inline void init_iq(struct sge_iq *, struct adapter *, int, int, int); 211 static inline void init_fl(struct adapter *, struct sge_fl *, int, int, char *); 212 static inline void init_eq(struct adapter *, struct sge_eq *, int, int, uint8_t, 213 uint16_t, char *); 214 static int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *, 215 bus_addr_t *, void **); 216 static int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 217 void *); 218 static int alloc_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *, 219 int, int); 220 static int free_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *); 221 static void add_iq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *, 222 struct sge_iq *); 223 static void add_fl_sysctls(struct adapter *, struct sysctl_ctx_list *, 224 struct sysctl_oid *, struct sge_fl *); 225 static int alloc_fwq(struct adapter *); 226 static int free_fwq(struct adapter *); 227 static int alloc_ctrlq(struct adapter *, struct sge_wrq *, int, 228 struct sysctl_oid *); 229 static int alloc_rxq(struct vi_info *, struct sge_rxq *, int, int, 230 struct sysctl_oid *); 231 static int free_rxq(struct vi_info *, struct sge_rxq *); 232 #ifdef TCP_OFFLOAD 233 static int alloc_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *, int, int, 234 struct sysctl_oid *); 235 static int free_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *); 236 #endif 237 #ifdef DEV_NETMAP 238 static int alloc_nm_rxq(struct vi_info *, struct sge_nm_rxq *, int, int, 239 struct sysctl_oid *); 240 static int free_nm_rxq(struct vi_info *, struct sge_nm_rxq *); 241 static int alloc_nm_txq(struct vi_info *, struct sge_nm_txq *, int, int, 242 struct sysctl_oid *); 243 static int free_nm_txq(struct vi_info *, struct sge_nm_txq *); 244 #endif 245 static int ctrl_eq_alloc(struct adapter *, struct sge_eq *); 246 static int eth_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *); 247 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 248 static int ofld_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *); 249 #endif 250 static int alloc_eq(struct adapter *, struct vi_info *, struct sge_eq *); 251 static int free_eq(struct adapter *, struct sge_eq *); 252 static int alloc_wrq(struct adapter *, struct vi_info *, struct sge_wrq *, 253 struct sysctl_oid *); 254 static int free_wrq(struct adapter *, struct sge_wrq *); 255 static int alloc_txq(struct vi_info *, struct sge_txq *, int, 256 struct sysctl_oid *); 257 static int free_txq(struct vi_info *, struct sge_txq *); 258 static void oneseg_dma_callback(void *, bus_dma_segment_t *, int, int); 259 static inline void ring_fl_db(struct adapter *, struct sge_fl *); 260 static int refill_fl(struct adapter *, struct sge_fl *, int); 261 static void refill_sfl(void *); 262 static int alloc_fl_sdesc(struct sge_fl *); 263 static void free_fl_sdesc(struct adapter *, struct sge_fl *); 264 static void find_best_refill_source(struct adapter *, struct sge_fl *, int); 265 static void find_safe_refill_source(struct adapter *, struct sge_fl *); 266 static void add_fl_to_sfl(struct adapter *, struct sge_fl *); 267 268 static inline void get_pkt_gl(struct mbuf *, struct sglist *); 269 static inline u_int txpkt_len16(u_int, u_int); 270 static inline u_int txpkt_vm_len16(u_int, u_int); 271 static inline u_int txpkts0_len16(u_int); 272 static inline u_int txpkts1_len16(void); 273 static u_int write_txpkt_wr(struct sge_txq *, struct fw_eth_tx_pkt_wr *, 274 struct mbuf *, u_int); 275 static u_int write_txpkt_vm_wr(struct adapter *, struct sge_txq *, 276 struct fw_eth_tx_pkt_vm_wr *, struct mbuf *, u_int); 277 static int try_txpkts(struct mbuf *, struct mbuf *, struct txpkts *, u_int); 278 static int add_to_txpkts(struct mbuf *, struct txpkts *, u_int); 279 static u_int write_txpkts_wr(struct sge_txq *, struct fw_eth_tx_pkts_wr *, 280 struct mbuf *, const struct txpkts *, u_int); 281 static void write_gl_to_txd(struct sge_txq *, struct mbuf *, caddr_t *, int); 282 static inline void copy_to_txd(struct sge_eq *, caddr_t, caddr_t *, int); 283 static inline void ring_eq_db(struct adapter *, struct sge_eq *, u_int); 284 static inline uint16_t read_hw_cidx(struct sge_eq *); 285 static inline u_int reclaimable_tx_desc(struct sge_eq *); 286 static inline u_int total_available_tx_desc(struct sge_eq *); 287 static u_int reclaim_tx_descs(struct sge_txq *, u_int); 288 static void tx_reclaim(void *, int); 289 static __be64 get_flit(struct sglist_seg *, int, int); 290 static int handle_sge_egr_update(struct sge_iq *, const struct rss_header *, 291 struct mbuf *); 292 static int handle_fw_msg(struct sge_iq *, const struct rss_header *, 293 struct mbuf *); 294 static int t4_handle_wrerr_rpl(struct adapter *, const __be64 *); 295 static void wrq_tx_drain(void *, int); 296 static void drain_wrq_wr_list(struct adapter *, struct sge_wrq *); 297 298 static int sysctl_uint16(SYSCTL_HANDLER_ARGS); 299 static int sysctl_bufsizes(SYSCTL_HANDLER_ARGS); 300 #ifdef RATELIMIT 301 static inline u_int txpkt_eo_len16(u_int, u_int, u_int); 302 static int ethofld_fw4_ack(struct sge_iq *, const struct rss_header *, 303 struct mbuf *); 304 #endif 305 306 static counter_u64_t extfree_refs; 307 static counter_u64_t extfree_rels; 308 309 an_handler_t t4_an_handler; 310 fw_msg_handler_t t4_fw_msg_handler[NUM_FW6_TYPES]; 311 cpl_handler_t t4_cpl_handler[NUM_CPL_CMDS]; 312 cpl_handler_t set_tcb_rpl_handlers[NUM_CPL_COOKIES]; 313 cpl_handler_t l2t_write_rpl_handlers[NUM_CPL_COOKIES]; 314 cpl_handler_t act_open_rpl_handlers[NUM_CPL_COOKIES]; 315 cpl_handler_t abort_rpl_rss_handlers[NUM_CPL_COOKIES]; 316 cpl_handler_t fw4_ack_handlers[NUM_CPL_COOKIES]; 317 318 void 319 t4_register_an_handler(an_handler_t h) 320 { 321 uintptr_t *loc; 322 323 MPASS(h == NULL || t4_an_handler == NULL); 324 325 loc = (uintptr_t *)&t4_an_handler; 326 atomic_store_rel_ptr(loc, (uintptr_t)h); 327 } 328 329 void 330 t4_register_fw_msg_handler(int type, fw_msg_handler_t h) 331 { 332 uintptr_t *loc; 333 334 MPASS(type < nitems(t4_fw_msg_handler)); 335 MPASS(h == NULL || t4_fw_msg_handler[type] == NULL); 336 /* 337 * These are dispatched by the handler for FW{4|6}_CPL_MSG using the CPL 338 * handler dispatch table. Reject any attempt to install a handler for 339 * this subtype. 340 */ 341 MPASS(type != FW_TYPE_RSSCPL); 342 MPASS(type != FW6_TYPE_RSSCPL); 343 344 loc = (uintptr_t *)&t4_fw_msg_handler[type]; 345 atomic_store_rel_ptr(loc, (uintptr_t)h); 346 } 347 348 void 349 t4_register_cpl_handler(int opcode, cpl_handler_t h) 350 { 351 uintptr_t *loc; 352 353 MPASS(opcode < nitems(t4_cpl_handler)); 354 MPASS(h == NULL || t4_cpl_handler[opcode] == NULL); 355 356 loc = (uintptr_t *)&t4_cpl_handler[opcode]; 357 atomic_store_rel_ptr(loc, (uintptr_t)h); 358 } 359 360 static int 361 set_tcb_rpl_handler(struct sge_iq *iq, const struct rss_header *rss, 362 struct mbuf *m) 363 { 364 const struct cpl_set_tcb_rpl *cpl = (const void *)(rss + 1); 365 u_int tid; 366 int cookie; 367 368 MPASS(m == NULL); 369 370 tid = GET_TID(cpl); 371 if (is_hpftid(iq->adapter, tid) || is_ftid(iq->adapter, tid)) { 372 /* 373 * The return code for filter-write is put in the CPL cookie so 374 * we have to rely on the hardware tid (is_ftid) to determine 375 * that this is a response to a filter. 376 */ 377 cookie = CPL_COOKIE_FILTER; 378 } else { 379 cookie = G_COOKIE(cpl->cookie); 380 } 381 MPASS(cookie > CPL_COOKIE_RESERVED); 382 MPASS(cookie < nitems(set_tcb_rpl_handlers)); 383 384 return (set_tcb_rpl_handlers[cookie](iq, rss, m)); 385 } 386 387 static int 388 l2t_write_rpl_handler(struct sge_iq *iq, const struct rss_header *rss, 389 struct mbuf *m) 390 { 391 const struct cpl_l2t_write_rpl *rpl = (const void *)(rss + 1); 392 unsigned int cookie; 393 394 MPASS(m == NULL); 395 396 cookie = GET_TID(rpl) & F_SYNC_WR ? CPL_COOKIE_TOM : CPL_COOKIE_FILTER; 397 return (l2t_write_rpl_handlers[cookie](iq, rss, m)); 398 } 399 400 static int 401 act_open_rpl_handler(struct sge_iq *iq, const struct rss_header *rss, 402 struct mbuf *m) 403 { 404 const struct cpl_act_open_rpl *cpl = (const void *)(rss + 1); 405 u_int cookie = G_TID_COOKIE(G_AOPEN_ATID(be32toh(cpl->atid_status))); 406 407 MPASS(m == NULL); 408 MPASS(cookie != CPL_COOKIE_RESERVED); 409 410 return (act_open_rpl_handlers[cookie](iq, rss, m)); 411 } 412 413 static int 414 abort_rpl_rss_handler(struct sge_iq *iq, const struct rss_header *rss, 415 struct mbuf *m) 416 { 417 struct adapter *sc = iq->adapter; 418 u_int cookie; 419 420 MPASS(m == NULL); 421 if (is_hashfilter(sc)) 422 cookie = CPL_COOKIE_HASHFILTER; 423 else 424 cookie = CPL_COOKIE_TOM; 425 426 return (abort_rpl_rss_handlers[cookie](iq, rss, m)); 427 } 428 429 static int 430 fw4_ack_handler(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 431 { 432 struct adapter *sc = iq->adapter; 433 const struct cpl_fw4_ack *cpl = (const void *)(rss + 1); 434 unsigned int tid = G_CPL_FW4_ACK_FLOWID(be32toh(OPCODE_TID(cpl))); 435 u_int cookie; 436 437 MPASS(m == NULL); 438 if (is_etid(sc, tid)) 439 cookie = CPL_COOKIE_ETHOFLD; 440 else 441 cookie = CPL_COOKIE_TOM; 442 443 return (fw4_ack_handlers[cookie](iq, rss, m)); 444 } 445 446 static void 447 t4_init_shared_cpl_handlers(void) 448 { 449 450 t4_register_cpl_handler(CPL_SET_TCB_RPL, set_tcb_rpl_handler); 451 t4_register_cpl_handler(CPL_L2T_WRITE_RPL, l2t_write_rpl_handler); 452 t4_register_cpl_handler(CPL_ACT_OPEN_RPL, act_open_rpl_handler); 453 t4_register_cpl_handler(CPL_ABORT_RPL_RSS, abort_rpl_rss_handler); 454 t4_register_cpl_handler(CPL_FW4_ACK, fw4_ack_handler); 455 } 456 457 void 458 t4_register_shared_cpl_handler(int opcode, cpl_handler_t h, int cookie) 459 { 460 uintptr_t *loc; 461 462 MPASS(opcode < nitems(t4_cpl_handler)); 463 MPASS(cookie > CPL_COOKIE_RESERVED); 464 MPASS(cookie < NUM_CPL_COOKIES); 465 MPASS(t4_cpl_handler[opcode] != NULL); 466 467 switch (opcode) { 468 case CPL_SET_TCB_RPL: 469 loc = (uintptr_t *)&set_tcb_rpl_handlers[cookie]; 470 break; 471 case CPL_L2T_WRITE_RPL: 472 loc = (uintptr_t *)&l2t_write_rpl_handlers[cookie]; 473 break; 474 case CPL_ACT_OPEN_RPL: 475 loc = (uintptr_t *)&act_open_rpl_handlers[cookie]; 476 break; 477 case CPL_ABORT_RPL_RSS: 478 loc = (uintptr_t *)&abort_rpl_rss_handlers[cookie]; 479 break; 480 case CPL_FW4_ACK: 481 loc = (uintptr_t *)&fw4_ack_handlers[cookie]; 482 break; 483 default: 484 MPASS(0); 485 return; 486 } 487 MPASS(h == NULL || *loc == (uintptr_t)NULL); 488 atomic_store_rel_ptr(loc, (uintptr_t)h); 489 } 490 491 /* 492 * Called on MOD_LOAD. Validates and calculates the SGE tunables. 493 */ 494 void 495 t4_sge_modload(void) 496 { 497 498 if (fl_pktshift < 0 || fl_pktshift > 7) { 499 printf("Invalid hw.cxgbe.fl_pktshift value (%d)," 500 " using 0 instead.\n", fl_pktshift); 501 fl_pktshift = 0; 502 } 503 504 if (spg_len != 64 && spg_len != 128) { 505 int len; 506 507 #if defined(__i386__) || defined(__amd64__) 508 len = cpu_clflush_line_size > 64 ? 128 : 64; 509 #else 510 len = 64; 511 #endif 512 if (spg_len != -1) { 513 printf("Invalid hw.cxgbe.spg_len value (%d)," 514 " using %d instead.\n", spg_len, len); 515 } 516 spg_len = len; 517 } 518 519 if (cong_drop < -1 || cong_drop > 1) { 520 printf("Invalid hw.cxgbe.cong_drop value (%d)," 521 " using 0 instead.\n", cong_drop); 522 cong_drop = 0; 523 } 524 525 if (tscale != 1 && (tscale < 3 || tscale > 17)) { 526 printf("Invalid hw.cxgbe.tscale value (%d)," 527 " using 1 instead.\n", tscale); 528 tscale = 1; 529 } 530 531 extfree_refs = counter_u64_alloc(M_WAITOK); 532 extfree_rels = counter_u64_alloc(M_WAITOK); 533 counter_u64_zero(extfree_refs); 534 counter_u64_zero(extfree_rels); 535 536 t4_init_shared_cpl_handlers(); 537 t4_register_cpl_handler(CPL_FW4_MSG, handle_fw_msg); 538 t4_register_cpl_handler(CPL_FW6_MSG, handle_fw_msg); 539 t4_register_cpl_handler(CPL_SGE_EGR_UPDATE, handle_sge_egr_update); 540 t4_register_cpl_handler(CPL_RX_PKT, t4_eth_rx); 541 #ifdef RATELIMIT 542 t4_register_shared_cpl_handler(CPL_FW4_ACK, ethofld_fw4_ack, 543 CPL_COOKIE_ETHOFLD); 544 #endif 545 t4_register_fw_msg_handler(FW6_TYPE_CMD_RPL, t4_handle_fw_rpl); 546 t4_register_fw_msg_handler(FW6_TYPE_WRERR_RPL, t4_handle_wrerr_rpl); 547 } 548 549 void 550 t4_sge_modunload(void) 551 { 552 553 counter_u64_free(extfree_refs); 554 counter_u64_free(extfree_rels); 555 } 556 557 uint64_t 558 t4_sge_extfree_refs(void) 559 { 560 uint64_t refs, rels; 561 562 rels = counter_u64_fetch(extfree_rels); 563 refs = counter_u64_fetch(extfree_refs); 564 565 return (refs - rels); 566 } 567 568 static inline void 569 setup_pad_and_pack_boundaries(struct adapter *sc) 570 { 571 uint32_t v, m; 572 int pad, pack, pad_shift; 573 574 pad_shift = chip_id(sc) > CHELSIO_T5 ? X_T6_INGPADBOUNDARY_SHIFT : 575 X_INGPADBOUNDARY_SHIFT; 576 pad = fl_pad; 577 if (fl_pad < (1 << pad_shift) || 578 fl_pad > (1 << (pad_shift + M_INGPADBOUNDARY)) || 579 !powerof2(fl_pad)) { 580 /* 581 * If there is any chance that we might use buffer packing and 582 * the chip is a T4, then pick 64 as the pad/pack boundary. Set 583 * it to the minimum allowed in all other cases. 584 */ 585 pad = is_t4(sc) && buffer_packing ? 64 : 1 << pad_shift; 586 587 /* 588 * For fl_pad = 0 we'll still write a reasonable value to the 589 * register but all the freelists will opt out of padding. 590 * We'll complain here only if the user tried to set it to a 591 * value greater than 0 that was invalid. 592 */ 593 if (fl_pad > 0) { 594 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pad value" 595 " (%d), using %d instead.\n", fl_pad, pad); 596 } 597 } 598 m = V_INGPADBOUNDARY(M_INGPADBOUNDARY); 599 v = V_INGPADBOUNDARY(ilog2(pad) - pad_shift); 600 t4_set_reg_field(sc, A_SGE_CONTROL, m, v); 601 602 if (is_t4(sc)) { 603 if (fl_pack != -1 && fl_pack != pad) { 604 /* Complain but carry on. */ 605 device_printf(sc->dev, "hw.cxgbe.fl_pack (%d) ignored," 606 " using %d instead.\n", fl_pack, pad); 607 } 608 return; 609 } 610 611 pack = fl_pack; 612 if (fl_pack < 16 || fl_pack == 32 || fl_pack > 4096 || 613 !powerof2(fl_pack)) { 614 pack = max(sc->params.pci.mps, CACHE_LINE_SIZE); 615 MPASS(powerof2(pack)); 616 if (pack < 16) 617 pack = 16; 618 if (pack == 32) 619 pack = 64; 620 if (pack > 4096) 621 pack = 4096; 622 if (fl_pack != -1) { 623 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pack value" 624 " (%d), using %d instead.\n", fl_pack, pack); 625 } 626 } 627 m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY); 628 if (pack == 16) 629 v = V_INGPACKBOUNDARY(0); 630 else 631 v = V_INGPACKBOUNDARY(ilog2(pack) - 5); 632 633 MPASS(!is_t4(sc)); /* T4 doesn't have SGE_CONTROL2 */ 634 t4_set_reg_field(sc, A_SGE_CONTROL2, m, v); 635 } 636 637 /* 638 * adap->params.vpd.cclk must be set up before this is called. 639 */ 640 void 641 t4_tweak_chip_settings(struct adapter *sc) 642 { 643 int i; 644 uint32_t v, m; 645 int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200}; 646 int timer_max = M_TIMERVALUE0 * 1000 / sc->params.vpd.cclk; 647 int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */ 648 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 649 static int sge_flbuf_sizes[] = { 650 MCLBYTES, 651 #if MJUMPAGESIZE != MCLBYTES 652 MJUMPAGESIZE, 653 MJUMPAGESIZE - CL_METADATA_SIZE, 654 MJUMPAGESIZE - 2 * MSIZE - CL_METADATA_SIZE, 655 #endif 656 MJUM9BYTES, 657 MJUM16BYTES, 658 MCLBYTES - MSIZE - CL_METADATA_SIZE, 659 MJUM9BYTES - CL_METADATA_SIZE, 660 MJUM16BYTES - CL_METADATA_SIZE, 661 }; 662 663 KASSERT(sc->flags & MASTER_PF, 664 ("%s: trying to change chip settings when not master.", __func__)); 665 666 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE; 667 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE | 668 V_EGRSTATUSPAGESIZE(spg_len == 128); 669 t4_set_reg_field(sc, A_SGE_CONTROL, m, v); 670 671 setup_pad_and_pack_boundaries(sc); 672 673 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) | 674 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) | 675 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) | 676 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) | 677 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) | 678 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) | 679 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) | 680 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10); 681 t4_write_reg(sc, A_SGE_HOST_PAGE_SIZE, v); 682 683 KASSERT(nitems(sge_flbuf_sizes) <= SGE_FLBUF_SIZES, 684 ("%s: hw buffer size table too big", __func__)); 685 for (i = 0; i < min(nitems(sge_flbuf_sizes), SGE_FLBUF_SIZES); i++) { 686 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0 + (4 * i), 687 sge_flbuf_sizes[i]); 688 } 689 690 v = V_THRESHOLD_0(intr_pktcount[0]) | V_THRESHOLD_1(intr_pktcount[1]) | 691 V_THRESHOLD_2(intr_pktcount[2]) | V_THRESHOLD_3(intr_pktcount[3]); 692 t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD, v); 693 694 KASSERT(intr_timer[0] <= timer_max, 695 ("%s: not a single usable timer (%d, %d)", __func__, intr_timer[0], 696 timer_max)); 697 for (i = 1; i < nitems(intr_timer); i++) { 698 KASSERT(intr_timer[i] >= intr_timer[i - 1], 699 ("%s: timers not listed in increasing order (%d)", 700 __func__, i)); 701 702 while (intr_timer[i] > timer_max) { 703 if (i == nitems(intr_timer) - 1) { 704 intr_timer[i] = timer_max; 705 break; 706 } 707 intr_timer[i] += intr_timer[i - 1]; 708 intr_timer[i] /= 2; 709 } 710 } 711 712 v = V_TIMERVALUE0(us_to_core_ticks(sc, intr_timer[0])) | 713 V_TIMERVALUE1(us_to_core_ticks(sc, intr_timer[1])); 714 t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1, v); 715 v = V_TIMERVALUE2(us_to_core_ticks(sc, intr_timer[2])) | 716 V_TIMERVALUE3(us_to_core_ticks(sc, intr_timer[3])); 717 t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3, v); 718 v = V_TIMERVALUE4(us_to_core_ticks(sc, intr_timer[4])) | 719 V_TIMERVALUE5(us_to_core_ticks(sc, intr_timer[5])); 720 t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5, v); 721 722 if (chip_id(sc) >= CHELSIO_T6) { 723 m = V_TSCALE(M_TSCALE); 724 if (tscale == 1) 725 v = 0; 726 else 727 v = V_TSCALE(tscale - 2); 728 t4_set_reg_field(sc, A_SGE_ITP_CONTROL, m, v); 729 730 if (sc->debug_flags & DF_DISABLE_TCB_CACHE) { 731 m = V_RDTHRESHOLD(M_RDTHRESHOLD) | F_WRTHRTHRESHEN | 732 V_WRTHRTHRESH(M_WRTHRTHRESH); 733 t4_tp_pio_read(sc, &v, 1, A_TP_CMM_CONFIG, 1); 734 v &= ~m; 735 v |= V_RDTHRESHOLD(1) | F_WRTHRTHRESHEN | 736 V_WRTHRTHRESH(16); 737 t4_tp_pio_write(sc, &v, 1, A_TP_CMM_CONFIG, 1); 738 } 739 } 740 741 /* 4K, 16K, 64K, 256K DDP "page sizes" for TDDP */ 742 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 743 t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, v); 744 745 /* 746 * 4K, 8K, 16K, 64K DDP "page sizes" for iSCSI DDP. These have been 747 * chosen with MAXPHYS = 128K in mind. The largest DDP buffer that we 748 * may have to deal with is MAXPHYS + 1 page. 749 */ 750 v = V_HPZ0(0) | V_HPZ1(1) | V_HPZ2(2) | V_HPZ3(4); 751 t4_write_reg(sc, A_ULP_RX_ISCSI_PSZ, v); 752 753 /* We use multiple DDP page sizes both in plain-TOE and ISCSI modes. */ 754 m = v = F_TDDPTAGTCB | F_ISCSITAGTCB; 755 t4_set_reg_field(sc, A_ULP_RX_CTL, m, v); 756 757 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 758 F_RESETDDPOFFSET; 759 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 760 t4_set_reg_field(sc, A_TP_PARA_REG5, m, v); 761 } 762 763 /* 764 * SGE wants the buffer to be at least 64B and then a multiple of 16. If 765 * padding is in use, the buffer's start and end need to be aligned to the pad 766 * boundary as well. We'll just make sure that the size is a multiple of the 767 * boundary here, it is up to the buffer allocation code to make sure the start 768 * of the buffer is aligned as well. 769 */ 770 static inline int 771 hwsz_ok(struct adapter *sc, int hwsz) 772 { 773 int mask = fl_pad ? sc->params.sge.pad_boundary - 1 : 16 - 1; 774 775 return (hwsz >= 64 && (hwsz & mask) == 0); 776 } 777 778 /* 779 * XXX: driver really should be able to deal with unexpected settings. 780 */ 781 int 782 t4_read_chip_settings(struct adapter *sc) 783 { 784 struct sge *s = &sc->sge; 785 struct sge_params *sp = &sc->params.sge; 786 int i, j, n, rc = 0; 787 uint32_t m, v, r; 788 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 789 static int sw_buf_sizes[] = { /* Sorted by size */ 790 MCLBYTES, 791 #if MJUMPAGESIZE != MCLBYTES 792 MJUMPAGESIZE, 793 #endif 794 MJUM9BYTES, 795 MJUM16BYTES 796 }; 797 struct sw_zone_info *swz, *safe_swz; 798 struct hw_buf_info *hwb; 799 800 m = F_RXPKTCPLMODE; 801 v = F_RXPKTCPLMODE; 802 r = sc->params.sge.sge_control; 803 if ((r & m) != v) { 804 device_printf(sc->dev, "invalid SGE_CONTROL(0x%x)\n", r); 805 rc = EINVAL; 806 } 807 808 /* 809 * If this changes then every single use of PAGE_SHIFT in the driver 810 * needs to be carefully reviewed for PAGE_SHIFT vs sp->page_shift. 811 */ 812 if (sp->page_shift != PAGE_SHIFT) { 813 device_printf(sc->dev, "invalid SGE_HOST_PAGE_SIZE(0x%x)\n", r); 814 rc = EINVAL; 815 } 816 817 /* Filter out unusable hw buffer sizes entirely (mark with -2). */ 818 hwb = &s->hw_buf_info[0]; 819 for (i = 0; i < nitems(s->hw_buf_info); i++, hwb++) { 820 r = sc->params.sge.sge_fl_buffer_size[i]; 821 hwb->size = r; 822 hwb->zidx = hwsz_ok(sc, r) ? -1 : -2; 823 hwb->next = -1; 824 } 825 826 /* 827 * Create a sorted list in decreasing order of hw buffer sizes (and so 828 * increasing order of spare area) for each software zone. 829 * 830 * If padding is enabled then the start and end of the buffer must align 831 * to the pad boundary; if packing is enabled then they must align with 832 * the pack boundary as well. Allocations from the cluster zones are 833 * aligned to min(size, 4K), so the buffer starts at that alignment and 834 * ends at hwb->size alignment. If mbuf inlining is allowed the 835 * starting alignment will be reduced to MSIZE and the driver will 836 * exercise appropriate caution when deciding on the best buffer layout 837 * to use. 838 */ 839 n = 0; /* no usable buffer size to begin with */ 840 swz = &s->sw_zone_info[0]; 841 safe_swz = NULL; 842 for (i = 0; i < SW_ZONE_SIZES; i++, swz++) { 843 int8_t head = -1, tail = -1; 844 845 swz->size = sw_buf_sizes[i]; 846 swz->zone = m_getzone(swz->size); 847 swz->type = m_gettype(swz->size); 848 849 if (swz->size < PAGE_SIZE) { 850 MPASS(powerof2(swz->size)); 851 if (fl_pad && (swz->size % sp->pad_boundary != 0)) 852 continue; 853 } 854 855 if (swz->size == safest_rx_cluster) 856 safe_swz = swz; 857 858 hwb = &s->hw_buf_info[0]; 859 for (j = 0; j < SGE_FLBUF_SIZES; j++, hwb++) { 860 if (hwb->zidx != -1 || hwb->size > swz->size) 861 continue; 862 #ifdef INVARIANTS 863 if (fl_pad) 864 MPASS(hwb->size % sp->pad_boundary == 0); 865 #endif 866 hwb->zidx = i; 867 if (head == -1) 868 head = tail = j; 869 else if (hwb->size < s->hw_buf_info[tail].size) { 870 s->hw_buf_info[tail].next = j; 871 tail = j; 872 } else { 873 int8_t *cur; 874 struct hw_buf_info *t; 875 876 for (cur = &head; *cur != -1; cur = &t->next) { 877 t = &s->hw_buf_info[*cur]; 878 if (hwb->size == t->size) { 879 hwb->zidx = -2; 880 break; 881 } 882 if (hwb->size > t->size) { 883 hwb->next = *cur; 884 *cur = j; 885 break; 886 } 887 } 888 } 889 } 890 swz->head_hwidx = head; 891 swz->tail_hwidx = tail; 892 893 if (tail != -1) { 894 n++; 895 if (swz->size - s->hw_buf_info[tail].size >= 896 CL_METADATA_SIZE) 897 sc->flags |= BUF_PACKING_OK; 898 } 899 } 900 if (n == 0) { 901 device_printf(sc->dev, "no usable SGE FL buffer size.\n"); 902 rc = EINVAL; 903 } 904 905 s->safe_hwidx1 = -1; 906 s->safe_hwidx2 = -1; 907 if (safe_swz != NULL) { 908 s->safe_hwidx1 = safe_swz->head_hwidx; 909 for (i = safe_swz->head_hwidx; i != -1; i = hwb->next) { 910 int spare; 911 912 hwb = &s->hw_buf_info[i]; 913 #ifdef INVARIANTS 914 if (fl_pad) 915 MPASS(hwb->size % sp->pad_boundary == 0); 916 #endif 917 spare = safe_swz->size - hwb->size; 918 if (spare >= CL_METADATA_SIZE) { 919 s->safe_hwidx2 = i; 920 break; 921 } 922 } 923 } 924 925 if (sc->flags & IS_VF) 926 return (0); 927 928 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 929 r = t4_read_reg(sc, A_ULP_RX_TDDP_PSZ); 930 if (r != v) { 931 device_printf(sc->dev, "invalid ULP_RX_TDDP_PSZ(0x%x)\n", r); 932 rc = EINVAL; 933 } 934 935 m = v = F_TDDPTAGTCB; 936 r = t4_read_reg(sc, A_ULP_RX_CTL); 937 if ((r & m) != v) { 938 device_printf(sc->dev, "invalid ULP_RX_CTL(0x%x)\n", r); 939 rc = EINVAL; 940 } 941 942 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 943 F_RESETDDPOFFSET; 944 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 945 r = t4_read_reg(sc, A_TP_PARA_REG5); 946 if ((r & m) != v) { 947 device_printf(sc->dev, "invalid TP_PARA_REG5(0x%x)\n", r); 948 rc = EINVAL; 949 } 950 951 t4_init_tp_params(sc, 1); 952 953 t4_read_mtu_tbl(sc, sc->params.mtus, NULL); 954 t4_load_mtus(sc, sc->params.mtus, sc->params.a_wnd, sc->params.b_wnd); 955 956 return (rc); 957 } 958 959 int 960 t4_create_dma_tag(struct adapter *sc) 961 { 962 int rc; 963 964 rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0, 965 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE, 966 BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL, 967 NULL, &sc->dmat); 968 if (rc != 0) { 969 device_printf(sc->dev, 970 "failed to create main DMA tag: %d\n", rc); 971 } 972 973 return (rc); 974 } 975 976 void 977 t4_sge_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx, 978 struct sysctl_oid_list *children) 979 { 980 struct sge_params *sp = &sc->params.sge; 981 982 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "buffer_sizes", 983 CTLTYPE_STRING | CTLFLAG_RD, &sc->sge, 0, sysctl_bufsizes, "A", 984 "freelist buffer sizes"); 985 986 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pktshift", CTLFLAG_RD, 987 NULL, sp->fl_pktshift, "payload DMA offset in rx buffer (bytes)"); 988 989 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pad", CTLFLAG_RD, 990 NULL, sp->pad_boundary, "payload pad boundary (bytes)"); 991 992 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "spg_len", CTLFLAG_RD, 993 NULL, sp->spg_len, "status page size (bytes)"); 994 995 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_drop", CTLFLAG_RD, 996 NULL, cong_drop, "congestion drop setting"); 997 998 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pack", CTLFLAG_RD, 999 NULL, sp->pack_boundary, "payload pack boundary (bytes)"); 1000 } 1001 1002 int 1003 t4_destroy_dma_tag(struct adapter *sc) 1004 { 1005 if (sc->dmat) 1006 bus_dma_tag_destroy(sc->dmat); 1007 1008 return (0); 1009 } 1010 1011 /* 1012 * Allocate and initialize the firmware event queue, control queues, and special 1013 * purpose rx queues owned by the adapter. 1014 * 1015 * Returns errno on failure. Resources allocated up to that point may still be 1016 * allocated. Caller is responsible for cleanup in case this function fails. 1017 */ 1018 int 1019 t4_setup_adapter_queues(struct adapter *sc) 1020 { 1021 struct sysctl_oid *oid; 1022 struct sysctl_oid_list *children; 1023 int rc, i; 1024 1025 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 1026 1027 sysctl_ctx_init(&sc->ctx); 1028 sc->flags |= ADAP_SYSCTL_CTX; 1029 1030 /* 1031 * Firmware event queue 1032 */ 1033 rc = alloc_fwq(sc); 1034 if (rc != 0) 1035 return (rc); 1036 1037 /* 1038 * That's all for the VF driver. 1039 */ 1040 if (sc->flags & IS_VF) 1041 return (rc); 1042 1043 oid = device_get_sysctl_tree(sc->dev); 1044 children = SYSCTL_CHILDREN(oid); 1045 1046 /* 1047 * XXX: General purpose rx queues, one per port. 1048 */ 1049 1050 /* 1051 * Control queues, one per port. 1052 */ 1053 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "ctrlq", 1054 CTLFLAG_RD, NULL, "control queues"); 1055 for_each_port(sc, i) { 1056 struct sge_wrq *ctrlq = &sc->sge.ctrlq[i]; 1057 1058 rc = alloc_ctrlq(sc, ctrlq, i, oid); 1059 if (rc != 0) 1060 return (rc); 1061 } 1062 1063 return (rc); 1064 } 1065 1066 /* 1067 * Idempotent 1068 */ 1069 int 1070 t4_teardown_adapter_queues(struct adapter *sc) 1071 { 1072 int i; 1073 1074 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 1075 1076 /* Do this before freeing the queue */ 1077 if (sc->flags & ADAP_SYSCTL_CTX) { 1078 sysctl_ctx_free(&sc->ctx); 1079 sc->flags &= ~ADAP_SYSCTL_CTX; 1080 } 1081 1082 if (!(sc->flags & IS_VF)) { 1083 for_each_port(sc, i) 1084 free_wrq(sc, &sc->sge.ctrlq[i]); 1085 } 1086 free_fwq(sc); 1087 1088 return (0); 1089 } 1090 1091 /* Maximum payload that can be delivered with a single iq descriptor */ 1092 static inline int 1093 mtu_to_max_payload(struct adapter *sc, int mtu, const int toe) 1094 { 1095 int payload; 1096 1097 #ifdef TCP_OFFLOAD 1098 if (toe) { 1099 int rxcs = G_RXCOALESCESIZE(t4_read_reg(sc, A_TP_PARA_REG2)); 1100 1101 /* Note that COP can set rx_coalesce on/off per connection. */ 1102 payload = max(mtu, rxcs); 1103 } else { 1104 #endif 1105 /* large enough even when hw VLAN extraction is disabled */ 1106 payload = sc->params.sge.fl_pktshift + ETHER_HDR_LEN + 1107 ETHER_VLAN_ENCAP_LEN + mtu; 1108 #ifdef TCP_OFFLOAD 1109 } 1110 #endif 1111 1112 return (payload); 1113 } 1114 1115 int 1116 t4_setup_vi_queues(struct vi_info *vi) 1117 { 1118 int rc = 0, i, intr_idx, iqidx; 1119 struct sge_rxq *rxq; 1120 struct sge_txq *txq; 1121 #ifdef TCP_OFFLOAD 1122 struct sge_ofld_rxq *ofld_rxq; 1123 #endif 1124 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1125 struct sge_wrq *ofld_txq; 1126 #endif 1127 #ifdef DEV_NETMAP 1128 int saved_idx; 1129 struct sge_nm_rxq *nm_rxq; 1130 struct sge_nm_txq *nm_txq; 1131 #endif 1132 char name[16]; 1133 struct port_info *pi = vi->pi; 1134 struct adapter *sc = pi->adapter; 1135 struct ifnet *ifp = vi->ifp; 1136 struct sysctl_oid *oid = device_get_sysctl_tree(vi->dev); 1137 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 1138 int maxp, mtu = ifp->if_mtu; 1139 1140 /* Interrupt vector to start from (when using multiple vectors) */ 1141 intr_idx = vi->first_intr; 1142 1143 #ifdef DEV_NETMAP 1144 saved_idx = intr_idx; 1145 if (ifp->if_capabilities & IFCAP_NETMAP) { 1146 1147 /* netmap is supported with direct interrupts only. */ 1148 MPASS(!forwarding_intr_to_fwq(sc)); 1149 1150 /* 1151 * We don't have buffers to back the netmap rx queues 1152 * right now so we create the queues in a way that 1153 * doesn't set off any congestion signal in the chip. 1154 */ 1155 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "nm_rxq", 1156 CTLFLAG_RD, NULL, "rx queues"); 1157 for_each_nm_rxq(vi, i, nm_rxq) { 1158 rc = alloc_nm_rxq(vi, nm_rxq, intr_idx, i, oid); 1159 if (rc != 0) 1160 goto done; 1161 intr_idx++; 1162 } 1163 1164 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "nm_txq", 1165 CTLFLAG_RD, NULL, "tx queues"); 1166 for_each_nm_txq(vi, i, nm_txq) { 1167 iqidx = vi->first_nm_rxq + (i % vi->nnmrxq); 1168 rc = alloc_nm_txq(vi, nm_txq, iqidx, i, oid); 1169 if (rc != 0) 1170 goto done; 1171 } 1172 } 1173 1174 /* Normal rx queues and netmap rx queues share the same interrupts. */ 1175 intr_idx = saved_idx; 1176 #endif 1177 1178 /* 1179 * Allocate rx queues first because a default iqid is required when 1180 * creating a tx queue. 1181 */ 1182 maxp = mtu_to_max_payload(sc, mtu, 0); 1183 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "rxq", 1184 CTLFLAG_RD, NULL, "rx queues"); 1185 for_each_rxq(vi, i, rxq) { 1186 1187 init_iq(&rxq->iq, sc, vi->tmr_idx, vi->pktc_idx, vi->qsize_rxq); 1188 1189 snprintf(name, sizeof(name), "%s rxq%d-fl", 1190 device_get_nameunit(vi->dev), i); 1191 init_fl(sc, &rxq->fl, vi->qsize_rxq / 8, maxp, name); 1192 1193 rc = alloc_rxq(vi, rxq, 1194 forwarding_intr_to_fwq(sc) ? -1 : intr_idx, i, oid); 1195 if (rc != 0) 1196 goto done; 1197 intr_idx++; 1198 } 1199 #ifdef DEV_NETMAP 1200 if (ifp->if_capabilities & IFCAP_NETMAP) 1201 intr_idx = saved_idx + max(vi->nrxq, vi->nnmrxq); 1202 #endif 1203 #ifdef TCP_OFFLOAD 1204 maxp = mtu_to_max_payload(sc, mtu, 1); 1205 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_rxq", 1206 CTLFLAG_RD, NULL, "rx queues for offloaded TCP connections"); 1207 for_each_ofld_rxq(vi, i, ofld_rxq) { 1208 1209 init_iq(&ofld_rxq->iq, sc, vi->ofld_tmr_idx, vi->ofld_pktc_idx, 1210 vi->qsize_rxq); 1211 1212 snprintf(name, sizeof(name), "%s ofld_rxq%d-fl", 1213 device_get_nameunit(vi->dev), i); 1214 init_fl(sc, &ofld_rxq->fl, vi->qsize_rxq / 8, maxp, name); 1215 1216 rc = alloc_ofld_rxq(vi, ofld_rxq, 1217 forwarding_intr_to_fwq(sc) ? -1 : intr_idx, i, oid); 1218 if (rc != 0) 1219 goto done; 1220 intr_idx++; 1221 } 1222 #endif 1223 1224 /* 1225 * Now the tx queues. 1226 */ 1227 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "txq", CTLFLAG_RD, 1228 NULL, "tx queues"); 1229 for_each_txq(vi, i, txq) { 1230 iqidx = vi->first_rxq + (i % vi->nrxq); 1231 snprintf(name, sizeof(name), "%s txq%d", 1232 device_get_nameunit(vi->dev), i); 1233 init_eq(sc, &txq->eq, EQ_ETH, vi->qsize_txq, pi->tx_chan, 1234 sc->sge.rxq[iqidx].iq.cntxt_id, name); 1235 1236 rc = alloc_txq(vi, txq, i, oid); 1237 if (rc != 0) 1238 goto done; 1239 } 1240 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1241 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_txq", 1242 CTLFLAG_RD, NULL, "tx queues for TOE/ETHOFLD"); 1243 for_each_ofld_txq(vi, i, ofld_txq) { 1244 struct sysctl_oid *oid2; 1245 1246 snprintf(name, sizeof(name), "%s ofld_txq%d", 1247 device_get_nameunit(vi->dev), i); 1248 if (vi->nofldrxq > 0) { 1249 iqidx = vi->first_ofld_rxq + (i % vi->nofldrxq); 1250 init_eq(sc, &ofld_txq->eq, EQ_OFLD, vi->qsize_txq, 1251 pi->tx_chan, sc->sge.ofld_rxq[iqidx].iq.cntxt_id, 1252 name); 1253 } else { 1254 iqidx = vi->first_rxq + (i % vi->nrxq); 1255 init_eq(sc, &ofld_txq->eq, EQ_OFLD, vi->qsize_txq, 1256 pi->tx_chan, sc->sge.rxq[iqidx].iq.cntxt_id, name); 1257 } 1258 1259 snprintf(name, sizeof(name), "%d", i); 1260 oid2 = SYSCTL_ADD_NODE(&vi->ctx, SYSCTL_CHILDREN(oid), OID_AUTO, 1261 name, CTLFLAG_RD, NULL, "offload tx queue"); 1262 1263 rc = alloc_wrq(sc, vi, ofld_txq, oid2); 1264 if (rc != 0) 1265 goto done; 1266 } 1267 #endif 1268 done: 1269 if (rc) 1270 t4_teardown_vi_queues(vi); 1271 1272 return (rc); 1273 } 1274 1275 /* 1276 * Idempotent 1277 */ 1278 int 1279 t4_teardown_vi_queues(struct vi_info *vi) 1280 { 1281 int i; 1282 struct sge_rxq *rxq; 1283 struct sge_txq *txq; 1284 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1285 struct port_info *pi = vi->pi; 1286 struct adapter *sc = pi->adapter; 1287 struct sge_wrq *ofld_txq; 1288 #endif 1289 #ifdef TCP_OFFLOAD 1290 struct sge_ofld_rxq *ofld_rxq; 1291 #endif 1292 #ifdef DEV_NETMAP 1293 struct sge_nm_rxq *nm_rxq; 1294 struct sge_nm_txq *nm_txq; 1295 #endif 1296 1297 /* Do this before freeing the queues */ 1298 if (vi->flags & VI_SYSCTL_CTX) { 1299 sysctl_ctx_free(&vi->ctx); 1300 vi->flags &= ~VI_SYSCTL_CTX; 1301 } 1302 1303 #ifdef DEV_NETMAP 1304 if (vi->ifp->if_capabilities & IFCAP_NETMAP) { 1305 for_each_nm_txq(vi, i, nm_txq) { 1306 free_nm_txq(vi, nm_txq); 1307 } 1308 1309 for_each_nm_rxq(vi, i, nm_rxq) { 1310 free_nm_rxq(vi, nm_rxq); 1311 } 1312 } 1313 #endif 1314 1315 /* 1316 * Take down all the tx queues first, as they reference the rx queues 1317 * (for egress updates, etc.). 1318 */ 1319 1320 for_each_txq(vi, i, txq) { 1321 free_txq(vi, txq); 1322 } 1323 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1324 for_each_ofld_txq(vi, i, ofld_txq) { 1325 free_wrq(sc, ofld_txq); 1326 } 1327 #endif 1328 1329 /* 1330 * Then take down the rx queues. 1331 */ 1332 1333 for_each_rxq(vi, i, rxq) { 1334 free_rxq(vi, rxq); 1335 } 1336 #ifdef TCP_OFFLOAD 1337 for_each_ofld_rxq(vi, i, ofld_rxq) { 1338 free_ofld_rxq(vi, ofld_rxq); 1339 } 1340 #endif 1341 1342 return (0); 1343 } 1344 1345 /* 1346 * Interrupt handler when the driver is using only 1 interrupt. This is a very 1347 * unusual scenario. 1348 * 1349 * a) Deals with errors, if any. 1350 * b) Services firmware event queue, which is taking interrupts for all other 1351 * queues. 1352 */ 1353 void 1354 t4_intr_all(void *arg) 1355 { 1356 struct adapter *sc = arg; 1357 struct sge_iq *fwq = &sc->sge.fwq; 1358 1359 MPASS(sc->intr_count == 1); 1360 1361 t4_intr_err(arg); 1362 t4_intr_evt(fwq); 1363 } 1364 1365 /* 1366 * Interrupt handler for errors (installed directly when multiple interrupts are 1367 * being used, or called by t4_intr_all). 1368 */ 1369 void 1370 t4_intr_err(void *arg) 1371 { 1372 struct adapter *sc = arg; 1373 1374 t4_write_reg(sc, MYPF_REG(A_PCIE_PF_CLI), 0); 1375 t4_slow_intr_handler(sc); 1376 } 1377 1378 /* 1379 * Interrupt handler for iq-only queues. The firmware event queue is the only 1380 * such queue right now. 1381 */ 1382 void 1383 t4_intr_evt(void *arg) 1384 { 1385 struct sge_iq *iq = arg; 1386 1387 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 1388 service_iq(iq, 0); 1389 (void) atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 1390 } 1391 } 1392 1393 /* 1394 * Interrupt handler for iq+fl queues. 1395 */ 1396 void 1397 t4_intr(void *arg) 1398 { 1399 struct sge_iq *iq = arg; 1400 1401 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 1402 service_iq_fl(iq, 0); 1403 (void) atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 1404 } 1405 } 1406 1407 #ifdef DEV_NETMAP 1408 /* 1409 * Interrupt handler for netmap rx queues. 1410 */ 1411 void 1412 t4_nm_intr(void *arg) 1413 { 1414 struct sge_nm_rxq *nm_rxq = arg; 1415 1416 if (atomic_cmpset_int(&nm_rxq->nm_state, NM_ON, NM_BUSY)) { 1417 service_nm_rxq(nm_rxq); 1418 (void) atomic_cmpset_int(&nm_rxq->nm_state, NM_BUSY, NM_ON); 1419 } 1420 } 1421 1422 /* 1423 * Interrupt handler for vectors shared between NIC and netmap rx queues. 1424 */ 1425 void 1426 t4_vi_intr(void *arg) 1427 { 1428 struct irq *irq = arg; 1429 1430 MPASS(irq->nm_rxq != NULL); 1431 t4_nm_intr(irq->nm_rxq); 1432 1433 MPASS(irq->rxq != NULL); 1434 t4_intr(irq->rxq); 1435 } 1436 #endif 1437 1438 /* 1439 * Deals with interrupts on an iq-only (no freelist) queue. 1440 */ 1441 static int 1442 service_iq(struct sge_iq *iq, int budget) 1443 { 1444 struct sge_iq *q; 1445 struct adapter *sc = iq->adapter; 1446 struct iq_desc *d = &iq->desc[iq->cidx]; 1447 int ndescs = 0, limit; 1448 int rsp_type; 1449 uint32_t lq; 1450 STAILQ_HEAD(, sge_iq) iql = STAILQ_HEAD_INITIALIZER(iql); 1451 1452 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq)); 1453 KASSERT((iq->flags & IQ_HAS_FL) == 0, 1454 ("%s: called for iq %p with fl (iq->flags 0x%x)", __func__, iq, 1455 iq->flags)); 1456 MPASS((iq->flags & IQ_ADJ_CREDIT) == 0); 1457 MPASS((iq->flags & IQ_LRO_ENABLED) == 0); 1458 1459 limit = budget ? budget : iq->qsize / 16; 1460 1461 /* 1462 * We always come back and check the descriptor ring for new indirect 1463 * interrupts and other responses after running a single handler. 1464 */ 1465 for (;;) { 1466 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) { 1467 1468 rmb(); 1469 1470 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen); 1471 lq = be32toh(d->rsp.pldbuflen_qid); 1472 1473 switch (rsp_type) { 1474 case X_RSPD_TYPE_FLBUF: 1475 panic("%s: data for an iq (%p) with no freelist", 1476 __func__, iq); 1477 1478 /* NOTREACHED */ 1479 1480 case X_RSPD_TYPE_CPL: 1481 KASSERT(d->rss.opcode < NUM_CPL_CMDS, 1482 ("%s: bad opcode %02x.", __func__, 1483 d->rss.opcode)); 1484 t4_cpl_handler[d->rss.opcode](iq, &d->rss, NULL); 1485 break; 1486 1487 case X_RSPD_TYPE_INTR: 1488 /* 1489 * There are 1K interrupt-capable queues (qids 0 1490 * through 1023). A response type indicating a 1491 * forwarded interrupt with a qid >= 1K is an 1492 * iWARP async notification. 1493 */ 1494 if (__predict_true(lq >= 1024)) { 1495 t4_an_handler(iq, &d->rsp); 1496 break; 1497 } 1498 1499 q = sc->sge.iqmap[lq - sc->sge.iq_start - 1500 sc->sge.iq_base]; 1501 if (atomic_cmpset_int(&q->state, IQS_IDLE, 1502 IQS_BUSY)) { 1503 if (service_iq_fl(q, q->qsize / 16) == 0) { 1504 (void) atomic_cmpset_int(&q->state, 1505 IQS_BUSY, IQS_IDLE); 1506 } else { 1507 STAILQ_INSERT_TAIL(&iql, q, 1508 link); 1509 } 1510 } 1511 break; 1512 1513 default: 1514 KASSERT(0, 1515 ("%s: illegal response type %d on iq %p", 1516 __func__, rsp_type, iq)); 1517 log(LOG_ERR, 1518 "%s: illegal response type %d on iq %p", 1519 device_get_nameunit(sc->dev), rsp_type, iq); 1520 break; 1521 } 1522 1523 d++; 1524 if (__predict_false(++iq->cidx == iq->sidx)) { 1525 iq->cidx = 0; 1526 iq->gen ^= F_RSPD_GEN; 1527 d = &iq->desc[0]; 1528 } 1529 if (__predict_false(++ndescs == limit)) { 1530 t4_write_reg(sc, sc->sge_gts_reg, 1531 V_CIDXINC(ndescs) | 1532 V_INGRESSQID(iq->cntxt_id) | 1533 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); 1534 ndescs = 0; 1535 1536 if (budget) { 1537 return (EINPROGRESS); 1538 } 1539 } 1540 } 1541 1542 if (STAILQ_EMPTY(&iql)) 1543 break; 1544 1545 /* 1546 * Process the head only, and send it to the back of the list if 1547 * it's still not done. 1548 */ 1549 q = STAILQ_FIRST(&iql); 1550 STAILQ_REMOVE_HEAD(&iql, link); 1551 if (service_iq_fl(q, q->qsize / 8) == 0) 1552 (void) atomic_cmpset_int(&q->state, IQS_BUSY, IQS_IDLE); 1553 else 1554 STAILQ_INSERT_TAIL(&iql, q, link); 1555 } 1556 1557 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) | 1558 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params)); 1559 1560 return (0); 1561 } 1562 1563 static inline int 1564 sort_before_lro(struct lro_ctrl *lro) 1565 { 1566 1567 return (lro->lro_mbuf_max != 0); 1568 } 1569 1570 static inline uint64_t 1571 last_flit_to_ns(struct adapter *sc, uint64_t lf) 1572 { 1573 uint64_t n = be64toh(lf) & 0xfffffffffffffff; /* 60b, not 64b. */ 1574 1575 if (n > UINT64_MAX / 1000000) 1576 return (n / sc->params.vpd.cclk * 1000000); 1577 else 1578 return (n * 1000000 / sc->params.vpd.cclk); 1579 } 1580 1581 /* 1582 * Deals with interrupts on an iq+fl queue. 1583 */ 1584 static int 1585 service_iq_fl(struct sge_iq *iq, int budget) 1586 { 1587 struct sge_rxq *rxq = iq_to_rxq(iq); 1588 struct sge_fl *fl; 1589 struct adapter *sc = iq->adapter; 1590 struct iq_desc *d = &iq->desc[iq->cidx]; 1591 int ndescs = 0, limit; 1592 int rsp_type, refill, starved; 1593 uint32_t lq; 1594 uint16_t fl_hw_cidx; 1595 struct mbuf *m0; 1596 #if defined(INET) || defined(INET6) 1597 const struct timeval lro_timeout = {0, sc->lro_timeout}; 1598 struct lro_ctrl *lro = &rxq->lro; 1599 #endif 1600 1601 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq)); 1602 MPASS(iq->flags & IQ_HAS_FL); 1603 1604 limit = budget ? budget : iq->qsize / 16; 1605 fl = &rxq->fl; 1606 fl_hw_cidx = fl->hw_cidx; /* stable snapshot */ 1607 1608 #if defined(INET) || defined(INET6) 1609 if (iq->flags & IQ_ADJ_CREDIT) { 1610 MPASS(sort_before_lro(lro)); 1611 iq->flags &= ~IQ_ADJ_CREDIT; 1612 if ((d->rsp.u.type_gen & F_RSPD_GEN) != iq->gen) { 1613 tcp_lro_flush_all(lro); 1614 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(1) | 1615 V_INGRESSQID((u32)iq->cntxt_id) | 1616 V_SEINTARM(iq->intr_params)); 1617 return (0); 1618 } 1619 ndescs = 1; 1620 } 1621 #else 1622 MPASS((iq->flags & IQ_ADJ_CREDIT) == 0); 1623 #endif 1624 1625 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) { 1626 1627 rmb(); 1628 1629 refill = 0; 1630 m0 = NULL; 1631 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen); 1632 lq = be32toh(d->rsp.pldbuflen_qid); 1633 1634 switch (rsp_type) { 1635 case X_RSPD_TYPE_FLBUF: 1636 1637 m0 = get_fl_payload(sc, fl, lq); 1638 if (__predict_false(m0 == NULL)) 1639 goto out; 1640 refill = IDXDIFF(fl->hw_cidx, fl_hw_cidx, fl->sidx) > 2; 1641 1642 if (iq->flags & IQ_RX_TIMESTAMP) { 1643 /* 1644 * Fill up rcv_tstmp but do not set M_TSTMP. 1645 * rcv_tstmp is not in the format that the 1646 * kernel expects and we don't want to mislead 1647 * it. For now this is only for custom code 1648 * that knows how to interpret cxgbe's stamp. 1649 */ 1650 m0->m_pkthdr.rcv_tstmp = 1651 last_flit_to_ns(sc, d->rsp.u.last_flit); 1652 #ifdef notyet 1653 m0->m_flags |= M_TSTMP; 1654 #endif 1655 } 1656 1657 /* fall through */ 1658 1659 case X_RSPD_TYPE_CPL: 1660 KASSERT(d->rss.opcode < NUM_CPL_CMDS, 1661 ("%s: bad opcode %02x.", __func__, d->rss.opcode)); 1662 t4_cpl_handler[d->rss.opcode](iq, &d->rss, m0); 1663 break; 1664 1665 case X_RSPD_TYPE_INTR: 1666 1667 /* 1668 * There are 1K interrupt-capable queues (qids 0 1669 * through 1023). A response type indicating a 1670 * forwarded interrupt with a qid >= 1K is an 1671 * iWARP async notification. That is the only 1672 * acceptable indirect interrupt on this queue. 1673 */ 1674 if (__predict_false(lq < 1024)) { 1675 panic("%s: indirect interrupt on iq_fl %p " 1676 "with qid %u", __func__, iq, lq); 1677 } 1678 1679 t4_an_handler(iq, &d->rsp); 1680 break; 1681 1682 default: 1683 KASSERT(0, ("%s: illegal response type %d on iq %p", 1684 __func__, rsp_type, iq)); 1685 log(LOG_ERR, "%s: illegal response type %d on iq %p", 1686 device_get_nameunit(sc->dev), rsp_type, iq); 1687 break; 1688 } 1689 1690 d++; 1691 if (__predict_false(++iq->cidx == iq->sidx)) { 1692 iq->cidx = 0; 1693 iq->gen ^= F_RSPD_GEN; 1694 d = &iq->desc[0]; 1695 } 1696 if (__predict_false(++ndescs == limit)) { 1697 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) | 1698 V_INGRESSQID(iq->cntxt_id) | 1699 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); 1700 ndescs = 0; 1701 1702 #if defined(INET) || defined(INET6) 1703 if (iq->flags & IQ_LRO_ENABLED && 1704 !sort_before_lro(lro) && 1705 sc->lro_timeout != 0) { 1706 tcp_lro_flush_inactive(lro, &lro_timeout); 1707 } 1708 #endif 1709 if (budget) { 1710 FL_LOCK(fl); 1711 refill_fl(sc, fl, 32); 1712 FL_UNLOCK(fl); 1713 1714 return (EINPROGRESS); 1715 } 1716 } 1717 if (refill) { 1718 FL_LOCK(fl); 1719 refill_fl(sc, fl, 32); 1720 FL_UNLOCK(fl); 1721 fl_hw_cidx = fl->hw_cidx; 1722 } 1723 } 1724 out: 1725 #if defined(INET) || defined(INET6) 1726 if (iq->flags & IQ_LRO_ENABLED) { 1727 if (ndescs > 0 && lro->lro_mbuf_count > 8) { 1728 MPASS(sort_before_lro(lro)); 1729 /* hold back one credit and don't flush LRO state */ 1730 iq->flags |= IQ_ADJ_CREDIT; 1731 ndescs--; 1732 } else { 1733 tcp_lro_flush_all(lro); 1734 } 1735 } 1736 #endif 1737 1738 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) | 1739 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params)); 1740 1741 FL_LOCK(fl); 1742 starved = refill_fl(sc, fl, 64); 1743 FL_UNLOCK(fl); 1744 if (__predict_false(starved != 0)) 1745 add_fl_to_sfl(sc, fl); 1746 1747 return (0); 1748 } 1749 1750 static inline int 1751 cl_has_metadata(struct sge_fl *fl, struct cluster_layout *cll) 1752 { 1753 int rc = fl->flags & FL_BUF_PACKING || cll->region1 > 0; 1754 1755 if (rc) 1756 MPASS(cll->region3 >= CL_METADATA_SIZE); 1757 1758 return (rc); 1759 } 1760 1761 static inline struct cluster_metadata * 1762 cl_metadata(struct adapter *sc, struct sge_fl *fl, struct cluster_layout *cll, 1763 caddr_t cl) 1764 { 1765 1766 if (cl_has_metadata(fl, cll)) { 1767 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx]; 1768 1769 return ((struct cluster_metadata *)(cl + swz->size) - 1); 1770 } 1771 return (NULL); 1772 } 1773 1774 static void 1775 rxb_free(struct mbuf *m) 1776 { 1777 uma_zone_t zone = m->m_ext.ext_arg1; 1778 void *cl = m->m_ext.ext_arg2; 1779 1780 uma_zfree(zone, cl); 1781 counter_u64_add(extfree_rels, 1); 1782 } 1783 1784 /* 1785 * The mbuf returned by this function could be allocated from zone_mbuf or 1786 * constructed in spare room in the cluster. 1787 * 1788 * The mbuf carries the payload in one of these ways 1789 * a) frame inside the mbuf (mbuf from zone_mbuf) 1790 * b) m_cljset (for clusters without metadata) zone_mbuf 1791 * c) m_extaddref (cluster with metadata) inline mbuf 1792 * d) m_extaddref (cluster with metadata) zone_mbuf 1793 */ 1794 static struct mbuf * 1795 get_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset, 1796 int remaining) 1797 { 1798 struct mbuf *m; 1799 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 1800 struct cluster_layout *cll = &sd->cll; 1801 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx]; 1802 struct hw_buf_info *hwb = &sc->sge.hw_buf_info[cll->hwidx]; 1803 struct cluster_metadata *clm = cl_metadata(sc, fl, cll, sd->cl); 1804 int len, blen; 1805 caddr_t payload; 1806 1807 blen = hwb->size - fl->rx_offset; /* max possible in this buf */ 1808 len = min(remaining, blen); 1809 payload = sd->cl + cll->region1 + fl->rx_offset; 1810 if (fl->flags & FL_BUF_PACKING) { 1811 const u_int l = fr_offset + len; 1812 const u_int pad = roundup2(l, fl->buf_boundary) - l; 1813 1814 if (fl->rx_offset + len + pad < hwb->size) 1815 blen = len + pad; 1816 MPASS(fl->rx_offset + blen <= hwb->size); 1817 } else { 1818 MPASS(fl->rx_offset == 0); /* not packing */ 1819 } 1820 1821 1822 if (sc->sc_do_rxcopy && len < RX_COPY_THRESHOLD) { 1823 1824 /* 1825 * Copy payload into a freshly allocated mbuf. 1826 */ 1827 1828 m = fr_offset == 0 ? 1829 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA); 1830 if (m == NULL) 1831 return (NULL); 1832 fl->mbuf_allocated++; 1833 1834 /* copy data to mbuf */ 1835 bcopy(payload, mtod(m, caddr_t), len); 1836 1837 } else if (sd->nmbuf * MSIZE < cll->region1) { 1838 1839 /* 1840 * There's spare room in the cluster for an mbuf. Create one 1841 * and associate it with the payload that's in the cluster. 1842 */ 1843 1844 MPASS(clm != NULL); 1845 m = (struct mbuf *)(sd->cl + sd->nmbuf * MSIZE); 1846 /* No bzero required */ 1847 if (m_init(m, M_NOWAIT, MT_DATA, 1848 fr_offset == 0 ? M_PKTHDR | M_NOFREE : M_NOFREE)) 1849 return (NULL); 1850 fl->mbuf_inlined++; 1851 m_extaddref(m, payload, blen, &clm->refcount, rxb_free, 1852 swz->zone, sd->cl); 1853 if (sd->nmbuf++ == 0) 1854 counter_u64_add(extfree_refs, 1); 1855 1856 } else { 1857 1858 /* 1859 * Grab an mbuf from zone_mbuf and associate it with the 1860 * payload in the cluster. 1861 */ 1862 1863 m = fr_offset == 0 ? 1864 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA); 1865 if (m == NULL) 1866 return (NULL); 1867 fl->mbuf_allocated++; 1868 if (clm != NULL) { 1869 m_extaddref(m, payload, blen, &clm->refcount, 1870 rxb_free, swz->zone, sd->cl); 1871 if (sd->nmbuf++ == 0) 1872 counter_u64_add(extfree_refs, 1); 1873 } else { 1874 m_cljset(m, sd->cl, swz->type); 1875 sd->cl = NULL; /* consumed, not a recycle candidate */ 1876 } 1877 } 1878 if (fr_offset == 0) 1879 m->m_pkthdr.len = remaining; 1880 m->m_len = len; 1881 1882 if (fl->flags & FL_BUF_PACKING) { 1883 fl->rx_offset += blen; 1884 MPASS(fl->rx_offset <= hwb->size); 1885 if (fl->rx_offset < hwb->size) 1886 return (m); /* without advancing the cidx */ 1887 } 1888 1889 if (__predict_false(++fl->cidx % 8 == 0)) { 1890 uint16_t cidx = fl->cidx / 8; 1891 1892 if (__predict_false(cidx == fl->sidx)) 1893 fl->cidx = cidx = 0; 1894 fl->hw_cidx = cidx; 1895 } 1896 fl->rx_offset = 0; 1897 1898 return (m); 1899 } 1900 1901 static struct mbuf * 1902 get_fl_payload(struct adapter *sc, struct sge_fl *fl, uint32_t len_newbuf) 1903 { 1904 struct mbuf *m0, *m, **pnext; 1905 u_int remaining; 1906 const u_int total = G_RSPD_LEN(len_newbuf); 1907 1908 if (__predict_false(fl->flags & FL_BUF_RESUME)) { 1909 M_ASSERTPKTHDR(fl->m0); 1910 MPASS(fl->m0->m_pkthdr.len == total); 1911 MPASS(fl->remaining < total); 1912 1913 m0 = fl->m0; 1914 pnext = fl->pnext; 1915 remaining = fl->remaining; 1916 fl->flags &= ~FL_BUF_RESUME; 1917 goto get_segment; 1918 } 1919 1920 if (fl->rx_offset > 0 && len_newbuf & F_RSPD_NEWBUF) { 1921 fl->rx_offset = 0; 1922 if (__predict_false(++fl->cidx % 8 == 0)) { 1923 uint16_t cidx = fl->cidx / 8; 1924 1925 if (__predict_false(cidx == fl->sidx)) 1926 fl->cidx = cidx = 0; 1927 fl->hw_cidx = cidx; 1928 } 1929 } 1930 1931 /* 1932 * Payload starts at rx_offset in the current hw buffer. Its length is 1933 * 'len' and it may span multiple hw buffers. 1934 */ 1935 1936 m0 = get_scatter_segment(sc, fl, 0, total); 1937 if (m0 == NULL) 1938 return (NULL); 1939 remaining = total - m0->m_len; 1940 pnext = &m0->m_next; 1941 while (remaining > 0) { 1942 get_segment: 1943 MPASS(fl->rx_offset == 0); 1944 m = get_scatter_segment(sc, fl, total - remaining, remaining); 1945 if (__predict_false(m == NULL)) { 1946 fl->m0 = m0; 1947 fl->pnext = pnext; 1948 fl->remaining = remaining; 1949 fl->flags |= FL_BUF_RESUME; 1950 return (NULL); 1951 } 1952 *pnext = m; 1953 pnext = &m->m_next; 1954 remaining -= m->m_len; 1955 } 1956 *pnext = NULL; 1957 1958 M_ASSERTPKTHDR(m0); 1959 return (m0); 1960 } 1961 1962 static int 1963 t4_eth_rx(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0) 1964 { 1965 struct sge_rxq *rxq = iq_to_rxq(iq); 1966 struct ifnet *ifp = rxq->ifp; 1967 struct adapter *sc = iq->adapter; 1968 const struct cpl_rx_pkt *cpl = (const void *)(rss + 1); 1969 #if defined(INET) || defined(INET6) 1970 struct lro_ctrl *lro = &rxq->lro; 1971 #endif 1972 static const int sw_hashtype[4][2] = { 1973 {M_HASHTYPE_NONE, M_HASHTYPE_NONE}, 1974 {M_HASHTYPE_RSS_IPV4, M_HASHTYPE_RSS_IPV6}, 1975 {M_HASHTYPE_RSS_TCP_IPV4, M_HASHTYPE_RSS_TCP_IPV6}, 1976 {M_HASHTYPE_RSS_UDP_IPV4, M_HASHTYPE_RSS_UDP_IPV6}, 1977 }; 1978 1979 KASSERT(m0 != NULL, ("%s: no payload with opcode %02x", __func__, 1980 rss->opcode)); 1981 1982 m0->m_pkthdr.len -= sc->params.sge.fl_pktshift; 1983 m0->m_len -= sc->params.sge.fl_pktshift; 1984 m0->m_data += sc->params.sge.fl_pktshift; 1985 1986 m0->m_pkthdr.rcvif = ifp; 1987 M_HASHTYPE_SET(m0, sw_hashtype[rss->hash_type][rss->ipv6]); 1988 m0->m_pkthdr.flowid = be32toh(rss->hash_val); 1989 1990 if (cpl->csum_calc && !(cpl->err_vec & sc->params.tp.err_vec_mask)) { 1991 if (ifp->if_capenable & IFCAP_RXCSUM && 1992 cpl->l2info & htobe32(F_RXF_IP)) { 1993 m0->m_pkthdr.csum_flags = (CSUM_IP_CHECKED | 1994 CSUM_IP_VALID | CSUM_DATA_VALID | CSUM_PSEUDO_HDR); 1995 rxq->rxcsum++; 1996 } else if (ifp->if_capenable & IFCAP_RXCSUM_IPV6 && 1997 cpl->l2info & htobe32(F_RXF_IP6)) { 1998 m0->m_pkthdr.csum_flags = (CSUM_DATA_VALID_IPV6 | 1999 CSUM_PSEUDO_HDR); 2000 rxq->rxcsum++; 2001 } 2002 2003 if (__predict_false(cpl->ip_frag)) 2004 m0->m_pkthdr.csum_data = be16toh(cpl->csum); 2005 else 2006 m0->m_pkthdr.csum_data = 0xffff; 2007 } 2008 2009 if (cpl->vlan_ex) { 2010 m0->m_pkthdr.ether_vtag = be16toh(cpl->vlan); 2011 m0->m_flags |= M_VLANTAG; 2012 rxq->vlan_extraction++; 2013 } 2014 2015 #if defined(INET) || defined(INET6) 2016 if (iq->flags & IQ_LRO_ENABLED) { 2017 if (sort_before_lro(lro)) { 2018 tcp_lro_queue_mbuf(lro, m0); 2019 return (0); /* queued for sort, then LRO */ 2020 } 2021 if (tcp_lro_rx(lro, m0, 0) == 0) 2022 return (0); /* queued for LRO */ 2023 } 2024 #endif 2025 ifp->if_input(ifp, m0); 2026 2027 return (0); 2028 } 2029 2030 /* 2031 * Must drain the wrq or make sure that someone else will. 2032 */ 2033 static void 2034 wrq_tx_drain(void *arg, int n) 2035 { 2036 struct sge_wrq *wrq = arg; 2037 struct sge_eq *eq = &wrq->eq; 2038 2039 EQ_LOCK(eq); 2040 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 2041 drain_wrq_wr_list(wrq->adapter, wrq); 2042 EQ_UNLOCK(eq); 2043 } 2044 2045 static void 2046 drain_wrq_wr_list(struct adapter *sc, struct sge_wrq *wrq) 2047 { 2048 struct sge_eq *eq = &wrq->eq; 2049 u_int available, dbdiff; /* # of hardware descriptors */ 2050 u_int n; 2051 struct wrqe *wr; 2052 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */ 2053 2054 EQ_LOCK_ASSERT_OWNED(eq); 2055 MPASS(TAILQ_EMPTY(&wrq->incomplete_wrs)); 2056 wr = STAILQ_FIRST(&wrq->wr_list); 2057 MPASS(wr != NULL); /* Must be called with something useful to do */ 2058 MPASS(eq->pidx == eq->dbidx); 2059 dbdiff = 0; 2060 2061 do { 2062 eq->cidx = read_hw_cidx(eq); 2063 if (eq->pidx == eq->cidx) 2064 available = eq->sidx - 1; 2065 else 2066 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2067 2068 MPASS(wr->wrq == wrq); 2069 n = howmany(wr->wr_len, EQ_ESIZE); 2070 if (available < n) 2071 break; 2072 2073 dst = (void *)&eq->desc[eq->pidx]; 2074 if (__predict_true(eq->sidx - eq->pidx > n)) { 2075 /* Won't wrap, won't end exactly at the status page. */ 2076 bcopy(&wr->wr[0], dst, wr->wr_len); 2077 eq->pidx += n; 2078 } else { 2079 int first_portion = (eq->sidx - eq->pidx) * EQ_ESIZE; 2080 2081 bcopy(&wr->wr[0], dst, first_portion); 2082 if (wr->wr_len > first_portion) { 2083 bcopy(&wr->wr[first_portion], &eq->desc[0], 2084 wr->wr_len - first_portion); 2085 } 2086 eq->pidx = n - (eq->sidx - eq->pidx); 2087 } 2088 wrq->tx_wrs_copied++; 2089 2090 if (available < eq->sidx / 4 && 2091 atomic_cmpset_int(&eq->equiq, 0, 1)) { 2092 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ | 2093 F_FW_WR_EQUEQ); 2094 eq->equeqidx = eq->pidx; 2095 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 32) { 2096 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ); 2097 eq->equeqidx = eq->pidx; 2098 } 2099 2100 dbdiff += n; 2101 if (dbdiff >= 16) { 2102 ring_eq_db(sc, eq, dbdiff); 2103 dbdiff = 0; 2104 } 2105 2106 STAILQ_REMOVE_HEAD(&wrq->wr_list, link); 2107 free_wrqe(wr); 2108 MPASS(wrq->nwr_pending > 0); 2109 wrq->nwr_pending--; 2110 MPASS(wrq->ndesc_needed >= n); 2111 wrq->ndesc_needed -= n; 2112 } while ((wr = STAILQ_FIRST(&wrq->wr_list)) != NULL); 2113 2114 if (dbdiff) 2115 ring_eq_db(sc, eq, dbdiff); 2116 } 2117 2118 /* 2119 * Doesn't fail. Holds on to work requests it can't send right away. 2120 */ 2121 void 2122 t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, struct wrqe *wr) 2123 { 2124 #ifdef INVARIANTS 2125 struct sge_eq *eq = &wrq->eq; 2126 #endif 2127 2128 EQ_LOCK_ASSERT_OWNED(eq); 2129 MPASS(wr != NULL); 2130 MPASS(wr->wr_len > 0 && wr->wr_len <= SGE_MAX_WR_LEN); 2131 MPASS((wr->wr_len & 0x7) == 0); 2132 2133 STAILQ_INSERT_TAIL(&wrq->wr_list, wr, link); 2134 wrq->nwr_pending++; 2135 wrq->ndesc_needed += howmany(wr->wr_len, EQ_ESIZE); 2136 2137 if (!TAILQ_EMPTY(&wrq->incomplete_wrs)) 2138 return; /* commit_wrq_wr will drain wr_list as well. */ 2139 2140 drain_wrq_wr_list(sc, wrq); 2141 2142 /* Doorbell must have caught up to the pidx. */ 2143 MPASS(eq->pidx == eq->dbidx); 2144 } 2145 2146 void 2147 t4_update_fl_bufsize(struct ifnet *ifp) 2148 { 2149 struct vi_info *vi = ifp->if_softc; 2150 struct adapter *sc = vi->pi->adapter; 2151 struct sge_rxq *rxq; 2152 #ifdef TCP_OFFLOAD 2153 struct sge_ofld_rxq *ofld_rxq; 2154 #endif 2155 struct sge_fl *fl; 2156 int i, maxp, mtu = ifp->if_mtu; 2157 2158 maxp = mtu_to_max_payload(sc, mtu, 0); 2159 for_each_rxq(vi, i, rxq) { 2160 fl = &rxq->fl; 2161 2162 FL_LOCK(fl); 2163 find_best_refill_source(sc, fl, maxp); 2164 FL_UNLOCK(fl); 2165 } 2166 #ifdef TCP_OFFLOAD 2167 maxp = mtu_to_max_payload(sc, mtu, 1); 2168 for_each_ofld_rxq(vi, i, ofld_rxq) { 2169 fl = &ofld_rxq->fl; 2170 2171 FL_LOCK(fl); 2172 find_best_refill_source(sc, fl, maxp); 2173 FL_UNLOCK(fl); 2174 } 2175 #endif 2176 } 2177 2178 static inline int 2179 mbuf_nsegs(struct mbuf *m) 2180 { 2181 2182 M_ASSERTPKTHDR(m); 2183 KASSERT(m->m_pkthdr.l5hlen > 0, 2184 ("%s: mbuf %p missing information on # of segments.", __func__, m)); 2185 2186 return (m->m_pkthdr.l5hlen); 2187 } 2188 2189 static inline void 2190 set_mbuf_nsegs(struct mbuf *m, uint8_t nsegs) 2191 { 2192 2193 M_ASSERTPKTHDR(m); 2194 m->m_pkthdr.l5hlen = nsegs; 2195 } 2196 2197 static inline int 2198 mbuf_len16(struct mbuf *m) 2199 { 2200 int n; 2201 2202 M_ASSERTPKTHDR(m); 2203 n = m->m_pkthdr.PH_loc.eight[0]; 2204 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16); 2205 2206 return (n); 2207 } 2208 2209 static inline void 2210 set_mbuf_len16(struct mbuf *m, uint8_t len16) 2211 { 2212 2213 M_ASSERTPKTHDR(m); 2214 m->m_pkthdr.PH_loc.eight[0] = len16; 2215 } 2216 2217 #ifdef RATELIMIT 2218 static inline int 2219 mbuf_eo_nsegs(struct mbuf *m) 2220 { 2221 2222 M_ASSERTPKTHDR(m); 2223 return (m->m_pkthdr.PH_loc.eight[1]); 2224 } 2225 2226 static inline void 2227 set_mbuf_eo_nsegs(struct mbuf *m, uint8_t nsegs) 2228 { 2229 2230 M_ASSERTPKTHDR(m); 2231 m->m_pkthdr.PH_loc.eight[1] = nsegs; 2232 } 2233 2234 static inline int 2235 mbuf_eo_len16(struct mbuf *m) 2236 { 2237 int n; 2238 2239 M_ASSERTPKTHDR(m); 2240 n = m->m_pkthdr.PH_loc.eight[2]; 2241 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16); 2242 2243 return (n); 2244 } 2245 2246 static inline void 2247 set_mbuf_eo_len16(struct mbuf *m, uint8_t len16) 2248 { 2249 2250 M_ASSERTPKTHDR(m); 2251 m->m_pkthdr.PH_loc.eight[2] = len16; 2252 } 2253 2254 static inline int 2255 mbuf_eo_tsclk_tsoff(struct mbuf *m) 2256 { 2257 2258 M_ASSERTPKTHDR(m); 2259 return (m->m_pkthdr.PH_loc.eight[3]); 2260 } 2261 2262 static inline void 2263 set_mbuf_eo_tsclk_tsoff(struct mbuf *m, uint8_t tsclk_tsoff) 2264 { 2265 2266 M_ASSERTPKTHDR(m); 2267 m->m_pkthdr.PH_loc.eight[3] = tsclk_tsoff; 2268 } 2269 2270 static inline int 2271 needs_eo(struct mbuf *m) 2272 { 2273 2274 return (m->m_pkthdr.snd_tag != NULL); 2275 } 2276 #endif 2277 2278 static inline int 2279 needs_tso(struct mbuf *m) 2280 { 2281 2282 M_ASSERTPKTHDR(m); 2283 2284 return (m->m_pkthdr.csum_flags & CSUM_TSO); 2285 } 2286 2287 static inline int 2288 needs_l3_csum(struct mbuf *m) 2289 { 2290 2291 M_ASSERTPKTHDR(m); 2292 2293 return (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TSO)); 2294 } 2295 2296 static inline int 2297 needs_l4_csum(struct mbuf *m) 2298 { 2299 2300 M_ASSERTPKTHDR(m); 2301 2302 return (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_UDP_IPV6 | 2303 CSUM_TCP_IPV6 | CSUM_TSO)); 2304 } 2305 2306 static inline int 2307 needs_tcp_csum(struct mbuf *m) 2308 { 2309 2310 M_ASSERTPKTHDR(m); 2311 return (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_TCP_IPV6 | CSUM_TSO)); 2312 } 2313 2314 #ifdef RATELIMIT 2315 static inline int 2316 needs_udp_csum(struct mbuf *m) 2317 { 2318 2319 M_ASSERTPKTHDR(m); 2320 return (m->m_pkthdr.csum_flags & (CSUM_UDP | CSUM_UDP_IPV6)); 2321 } 2322 #endif 2323 2324 static inline int 2325 needs_vlan_insertion(struct mbuf *m) 2326 { 2327 2328 M_ASSERTPKTHDR(m); 2329 2330 return (m->m_flags & M_VLANTAG); 2331 } 2332 2333 static void * 2334 m_advance(struct mbuf **pm, int *poffset, int len) 2335 { 2336 struct mbuf *m = *pm; 2337 int offset = *poffset; 2338 uintptr_t p = 0; 2339 2340 MPASS(len > 0); 2341 2342 for (;;) { 2343 if (offset + len < m->m_len) { 2344 offset += len; 2345 p = mtod(m, uintptr_t) + offset; 2346 break; 2347 } 2348 len -= m->m_len - offset; 2349 m = m->m_next; 2350 offset = 0; 2351 MPASS(m != NULL); 2352 } 2353 *poffset = offset; 2354 *pm = m; 2355 return ((void *)p); 2356 } 2357 2358 /* 2359 * Can deal with empty mbufs in the chain that have m_len = 0, but the chain 2360 * must have at least one mbuf that's not empty. It is possible for this 2361 * routine to return 0 if skip accounts for all the contents of the mbuf chain. 2362 */ 2363 static inline int 2364 count_mbuf_nsegs(struct mbuf *m, int skip) 2365 { 2366 vm_paddr_t lastb, next; 2367 vm_offset_t va; 2368 int len, nsegs; 2369 2370 M_ASSERTPKTHDR(m); 2371 MPASS(m->m_pkthdr.len > 0); 2372 MPASS(m->m_pkthdr.len >= skip); 2373 2374 nsegs = 0; 2375 lastb = 0; 2376 for (; m; m = m->m_next) { 2377 2378 len = m->m_len; 2379 if (__predict_false(len == 0)) 2380 continue; 2381 if (skip >= len) { 2382 skip -= len; 2383 continue; 2384 } 2385 va = mtod(m, vm_offset_t) + skip; 2386 len -= skip; 2387 skip = 0; 2388 next = pmap_kextract(va); 2389 nsegs += sglist_count((void *)(uintptr_t)va, len); 2390 if (lastb + 1 == next) 2391 nsegs--; 2392 lastb = pmap_kextract(va + len - 1); 2393 } 2394 2395 return (nsegs); 2396 } 2397 2398 /* 2399 * Analyze the mbuf to determine its tx needs. The mbuf passed in may change: 2400 * a) caller can assume it's been freed if this function returns with an error. 2401 * b) it may get defragged up if the gather list is too long for the hardware. 2402 */ 2403 int 2404 parse_pkt(struct adapter *sc, struct mbuf **mp) 2405 { 2406 struct mbuf *m0 = *mp, *m; 2407 int rc, nsegs, defragged = 0, offset; 2408 struct ether_header *eh; 2409 void *l3hdr; 2410 #if defined(INET) || defined(INET6) 2411 struct tcphdr *tcp; 2412 #endif 2413 uint16_t eh_type; 2414 2415 M_ASSERTPKTHDR(m0); 2416 if (__predict_false(m0->m_pkthdr.len < ETHER_HDR_LEN)) { 2417 rc = EINVAL; 2418 fail: 2419 m_freem(m0); 2420 *mp = NULL; 2421 return (rc); 2422 } 2423 restart: 2424 /* 2425 * First count the number of gather list segments in the payload. 2426 * Defrag the mbuf if nsegs exceeds the hardware limit. 2427 */ 2428 M_ASSERTPKTHDR(m0); 2429 MPASS(m0->m_pkthdr.len > 0); 2430 nsegs = count_mbuf_nsegs(m0, 0); 2431 if (nsegs > (needs_tso(m0) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS)) { 2432 if (defragged++ > 0 || (m = m_defrag(m0, M_NOWAIT)) == NULL) { 2433 rc = EFBIG; 2434 goto fail; 2435 } 2436 *mp = m0 = m; /* update caller's copy after defrag */ 2437 goto restart; 2438 } 2439 2440 if (__predict_false(nsegs > 2 && m0->m_pkthdr.len <= MHLEN)) { 2441 m0 = m_pullup(m0, m0->m_pkthdr.len); 2442 if (m0 == NULL) { 2443 /* Should have left well enough alone. */ 2444 rc = EFBIG; 2445 goto fail; 2446 } 2447 *mp = m0; /* update caller's copy after pullup */ 2448 goto restart; 2449 } 2450 set_mbuf_nsegs(m0, nsegs); 2451 if (sc->flags & IS_VF) 2452 set_mbuf_len16(m0, txpkt_vm_len16(nsegs, needs_tso(m0))); 2453 else 2454 set_mbuf_len16(m0, txpkt_len16(nsegs, needs_tso(m0))); 2455 2456 #ifdef RATELIMIT 2457 /* 2458 * Ethofld is limited to TCP and UDP for now, and only when L4 hw 2459 * checksumming is enabled. needs_l4_csum happens to check for all the 2460 * right things. 2461 */ 2462 if (__predict_false(needs_eo(m0) && !needs_l4_csum(m0))) 2463 m0->m_pkthdr.snd_tag = NULL; 2464 #endif 2465 2466 if (!needs_tso(m0) && 2467 #ifdef RATELIMIT 2468 !needs_eo(m0) && 2469 #endif 2470 !(sc->flags & IS_VF && (needs_l3_csum(m0) || needs_l4_csum(m0)))) 2471 return (0); 2472 2473 m = m0; 2474 eh = mtod(m, struct ether_header *); 2475 eh_type = ntohs(eh->ether_type); 2476 if (eh_type == ETHERTYPE_VLAN) { 2477 struct ether_vlan_header *evh = (void *)eh; 2478 2479 eh_type = ntohs(evh->evl_proto); 2480 m0->m_pkthdr.l2hlen = sizeof(*evh); 2481 } else 2482 m0->m_pkthdr.l2hlen = sizeof(*eh); 2483 2484 offset = 0; 2485 l3hdr = m_advance(&m, &offset, m0->m_pkthdr.l2hlen); 2486 2487 switch (eh_type) { 2488 #ifdef INET6 2489 case ETHERTYPE_IPV6: 2490 { 2491 struct ip6_hdr *ip6 = l3hdr; 2492 2493 MPASS(!needs_tso(m0) || ip6->ip6_nxt == IPPROTO_TCP); 2494 2495 m0->m_pkthdr.l3hlen = sizeof(*ip6); 2496 break; 2497 } 2498 #endif 2499 #ifdef INET 2500 case ETHERTYPE_IP: 2501 { 2502 struct ip *ip = l3hdr; 2503 2504 m0->m_pkthdr.l3hlen = ip->ip_hl * 4; 2505 break; 2506 } 2507 #endif 2508 default: 2509 panic("%s: ethertype 0x%04x unknown. if_cxgbe must be compiled" 2510 " with the same INET/INET6 options as the kernel.", 2511 __func__, eh_type); 2512 } 2513 2514 #if defined(INET) || defined(INET6) 2515 if (needs_tcp_csum(m0)) { 2516 tcp = m_advance(&m, &offset, m0->m_pkthdr.l3hlen); 2517 m0->m_pkthdr.l4hlen = tcp->th_off * 4; 2518 #ifdef RATELIMIT 2519 if (tsclk >= 0 && *(uint32_t *)(tcp + 1) == ntohl(0x0101080a)) { 2520 set_mbuf_eo_tsclk_tsoff(m0, 2521 V_FW_ETH_TX_EO_WR_TSCLK(tsclk) | 2522 V_FW_ETH_TX_EO_WR_TSOFF(sizeof(*tcp) / 2 + 1)); 2523 } else 2524 set_mbuf_eo_tsclk_tsoff(m0, 0); 2525 } else if (needs_udp_csum(m)) { 2526 m0->m_pkthdr.l4hlen = sizeof(struct udphdr); 2527 #endif 2528 } 2529 #ifdef RATELIMIT 2530 if (needs_eo(m0)) { 2531 u_int immhdrs; 2532 2533 /* EO WRs have the headers in the WR and not the GL. */ 2534 immhdrs = m0->m_pkthdr.l2hlen + m0->m_pkthdr.l3hlen + 2535 m0->m_pkthdr.l4hlen; 2536 nsegs = count_mbuf_nsegs(m0, immhdrs); 2537 set_mbuf_eo_nsegs(m0, nsegs); 2538 set_mbuf_eo_len16(m0, 2539 txpkt_eo_len16(nsegs, immhdrs, needs_tso(m0))); 2540 } 2541 #endif 2542 #endif 2543 MPASS(m0 == *mp); 2544 return (0); 2545 } 2546 2547 void * 2548 start_wrq_wr(struct sge_wrq *wrq, int len16, struct wrq_cookie *cookie) 2549 { 2550 struct sge_eq *eq = &wrq->eq; 2551 struct adapter *sc = wrq->adapter; 2552 int ndesc, available; 2553 struct wrqe *wr; 2554 void *w; 2555 2556 MPASS(len16 > 0); 2557 ndesc = howmany(len16, EQ_ESIZE / 16); 2558 MPASS(ndesc > 0 && ndesc <= SGE_MAX_WR_NDESC); 2559 2560 EQ_LOCK(eq); 2561 2562 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 2563 drain_wrq_wr_list(sc, wrq); 2564 2565 if (!STAILQ_EMPTY(&wrq->wr_list)) { 2566 slowpath: 2567 EQ_UNLOCK(eq); 2568 wr = alloc_wrqe(len16 * 16, wrq); 2569 if (__predict_false(wr == NULL)) 2570 return (NULL); 2571 cookie->pidx = -1; 2572 cookie->ndesc = ndesc; 2573 return (&wr->wr); 2574 } 2575 2576 eq->cidx = read_hw_cidx(eq); 2577 if (eq->pidx == eq->cidx) 2578 available = eq->sidx - 1; 2579 else 2580 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2581 if (available < ndesc) 2582 goto slowpath; 2583 2584 cookie->pidx = eq->pidx; 2585 cookie->ndesc = ndesc; 2586 TAILQ_INSERT_TAIL(&wrq->incomplete_wrs, cookie, link); 2587 2588 w = &eq->desc[eq->pidx]; 2589 IDXINCR(eq->pidx, ndesc, eq->sidx); 2590 if (__predict_false(cookie->pidx + ndesc > eq->sidx)) { 2591 w = &wrq->ss[0]; 2592 wrq->ss_pidx = cookie->pidx; 2593 wrq->ss_len = len16 * 16; 2594 } 2595 2596 EQ_UNLOCK(eq); 2597 2598 return (w); 2599 } 2600 2601 void 2602 commit_wrq_wr(struct sge_wrq *wrq, void *w, struct wrq_cookie *cookie) 2603 { 2604 struct sge_eq *eq = &wrq->eq; 2605 struct adapter *sc = wrq->adapter; 2606 int ndesc, pidx; 2607 struct wrq_cookie *prev, *next; 2608 2609 if (cookie->pidx == -1) { 2610 struct wrqe *wr = __containerof(w, struct wrqe, wr); 2611 2612 t4_wrq_tx(sc, wr); 2613 return; 2614 } 2615 2616 if (__predict_false(w == &wrq->ss[0])) { 2617 int n = (eq->sidx - wrq->ss_pidx) * EQ_ESIZE; 2618 2619 MPASS(wrq->ss_len > n); /* WR had better wrap around. */ 2620 bcopy(&wrq->ss[0], &eq->desc[wrq->ss_pidx], n); 2621 bcopy(&wrq->ss[n], &eq->desc[0], wrq->ss_len - n); 2622 wrq->tx_wrs_ss++; 2623 } else 2624 wrq->tx_wrs_direct++; 2625 2626 EQ_LOCK(eq); 2627 ndesc = cookie->ndesc; /* Can be more than SGE_MAX_WR_NDESC here. */ 2628 pidx = cookie->pidx; 2629 MPASS(pidx >= 0 && pidx < eq->sidx); 2630 prev = TAILQ_PREV(cookie, wrq_incomplete_wrs, link); 2631 next = TAILQ_NEXT(cookie, link); 2632 if (prev == NULL) { 2633 MPASS(pidx == eq->dbidx); 2634 if (next == NULL || ndesc >= 16) { 2635 int available; 2636 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */ 2637 2638 /* 2639 * Note that the WR via which we'll request tx updates 2640 * is at pidx and not eq->pidx, which has moved on 2641 * already. 2642 */ 2643 dst = (void *)&eq->desc[pidx]; 2644 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2645 if (available < eq->sidx / 4 && 2646 atomic_cmpset_int(&eq->equiq, 0, 1)) { 2647 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ | 2648 F_FW_WR_EQUEQ); 2649 eq->equeqidx = pidx; 2650 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 32) { 2651 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ); 2652 eq->equeqidx = pidx; 2653 } 2654 2655 ring_eq_db(wrq->adapter, eq, ndesc); 2656 } else { 2657 MPASS(IDXDIFF(next->pidx, pidx, eq->sidx) == ndesc); 2658 next->pidx = pidx; 2659 next->ndesc += ndesc; 2660 } 2661 } else { 2662 MPASS(IDXDIFF(pidx, prev->pidx, eq->sidx) == prev->ndesc); 2663 prev->ndesc += ndesc; 2664 } 2665 TAILQ_REMOVE(&wrq->incomplete_wrs, cookie, link); 2666 2667 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 2668 drain_wrq_wr_list(sc, wrq); 2669 2670 #ifdef INVARIANTS 2671 if (TAILQ_EMPTY(&wrq->incomplete_wrs)) { 2672 /* Doorbell must have caught up to the pidx. */ 2673 MPASS(wrq->eq.pidx == wrq->eq.dbidx); 2674 } 2675 #endif 2676 EQ_UNLOCK(eq); 2677 } 2678 2679 static u_int 2680 can_resume_eth_tx(struct mp_ring *r) 2681 { 2682 struct sge_eq *eq = r->cookie; 2683 2684 return (total_available_tx_desc(eq) > eq->sidx / 8); 2685 } 2686 2687 static inline int 2688 cannot_use_txpkts(struct mbuf *m) 2689 { 2690 /* maybe put a GL limit too, to avoid silliness? */ 2691 2692 return (needs_tso(m)); 2693 } 2694 2695 static inline int 2696 discard_tx(struct sge_eq *eq) 2697 { 2698 2699 return ((eq->flags & (EQ_ENABLED | EQ_QFLUSH)) != EQ_ENABLED); 2700 } 2701 2702 /* 2703 * r->items[cidx] to r->items[pidx], with a wraparound at r->size, are ready to 2704 * be consumed. Return the actual number consumed. 0 indicates a stall. 2705 */ 2706 static u_int 2707 eth_tx(struct mp_ring *r, u_int cidx, u_int pidx) 2708 { 2709 struct sge_txq *txq = r->cookie; 2710 struct sge_eq *eq = &txq->eq; 2711 struct ifnet *ifp = txq->ifp; 2712 struct vi_info *vi = ifp->if_softc; 2713 struct port_info *pi = vi->pi; 2714 struct adapter *sc = pi->adapter; 2715 u_int total, remaining; /* # of packets */ 2716 u_int available, dbdiff; /* # of hardware descriptors */ 2717 u_int n, next_cidx; 2718 struct mbuf *m0, *tail; 2719 struct txpkts txp; 2720 struct fw_eth_tx_pkts_wr *wr; /* any fw WR struct will do */ 2721 2722 remaining = IDXDIFF(pidx, cidx, r->size); 2723 MPASS(remaining > 0); /* Must not be called without work to do. */ 2724 total = 0; 2725 2726 TXQ_LOCK(txq); 2727 if (__predict_false(discard_tx(eq))) { 2728 while (cidx != pidx) { 2729 m0 = r->items[cidx]; 2730 m_freem(m0); 2731 if (++cidx == r->size) 2732 cidx = 0; 2733 } 2734 reclaim_tx_descs(txq, 2048); 2735 total = remaining; 2736 goto done; 2737 } 2738 2739 /* How many hardware descriptors do we have readily available. */ 2740 if (eq->pidx == eq->cidx) 2741 available = eq->sidx - 1; 2742 else 2743 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2744 dbdiff = IDXDIFF(eq->pidx, eq->dbidx, eq->sidx); 2745 2746 while (remaining > 0) { 2747 2748 m0 = r->items[cidx]; 2749 M_ASSERTPKTHDR(m0); 2750 MPASS(m0->m_nextpkt == NULL); 2751 2752 if (available < SGE_MAX_WR_NDESC) { 2753 available += reclaim_tx_descs(txq, 64); 2754 if (available < howmany(mbuf_len16(m0), EQ_ESIZE / 16)) 2755 break; /* out of descriptors */ 2756 } 2757 2758 next_cidx = cidx + 1; 2759 if (__predict_false(next_cidx == r->size)) 2760 next_cidx = 0; 2761 2762 wr = (void *)&eq->desc[eq->pidx]; 2763 if (sc->flags & IS_VF) { 2764 total++; 2765 remaining--; 2766 ETHER_BPF_MTAP(ifp, m0); 2767 n = write_txpkt_vm_wr(sc, txq, (void *)wr, m0, 2768 available); 2769 } else if (remaining > 1 && 2770 try_txpkts(m0, r->items[next_cidx], &txp, available) == 0) { 2771 2772 /* pkts at cidx, next_cidx should both be in txp. */ 2773 MPASS(txp.npkt == 2); 2774 tail = r->items[next_cidx]; 2775 MPASS(tail->m_nextpkt == NULL); 2776 ETHER_BPF_MTAP(ifp, m0); 2777 ETHER_BPF_MTAP(ifp, tail); 2778 m0->m_nextpkt = tail; 2779 2780 if (__predict_false(++next_cidx == r->size)) 2781 next_cidx = 0; 2782 2783 while (next_cidx != pidx) { 2784 if (add_to_txpkts(r->items[next_cidx], &txp, 2785 available) != 0) 2786 break; 2787 tail->m_nextpkt = r->items[next_cidx]; 2788 tail = tail->m_nextpkt; 2789 ETHER_BPF_MTAP(ifp, tail); 2790 if (__predict_false(++next_cidx == r->size)) 2791 next_cidx = 0; 2792 } 2793 2794 n = write_txpkts_wr(txq, wr, m0, &txp, available); 2795 total += txp.npkt; 2796 remaining -= txp.npkt; 2797 } else { 2798 total++; 2799 remaining--; 2800 ETHER_BPF_MTAP(ifp, m0); 2801 n = write_txpkt_wr(txq, (void *)wr, m0, available); 2802 } 2803 MPASS(n >= 1 && n <= available && n <= SGE_MAX_WR_NDESC); 2804 2805 available -= n; 2806 dbdiff += n; 2807 IDXINCR(eq->pidx, n, eq->sidx); 2808 2809 if (total_available_tx_desc(eq) < eq->sidx / 4 && 2810 atomic_cmpset_int(&eq->equiq, 0, 1)) { 2811 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ | 2812 F_FW_WR_EQUEQ); 2813 eq->equeqidx = eq->pidx; 2814 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 32) { 2815 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ); 2816 eq->equeqidx = eq->pidx; 2817 } 2818 2819 if (dbdiff >= 16 && remaining >= 4) { 2820 ring_eq_db(sc, eq, dbdiff); 2821 available += reclaim_tx_descs(txq, 4 * dbdiff); 2822 dbdiff = 0; 2823 } 2824 2825 cidx = next_cidx; 2826 } 2827 if (dbdiff != 0) { 2828 ring_eq_db(sc, eq, dbdiff); 2829 reclaim_tx_descs(txq, 32); 2830 } 2831 done: 2832 TXQ_UNLOCK(txq); 2833 2834 return (total); 2835 } 2836 2837 static inline void 2838 init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int pktc_idx, 2839 int qsize) 2840 { 2841 2842 KASSERT(tmr_idx >= 0 && tmr_idx < SGE_NTIMERS, 2843 ("%s: bad tmr_idx %d", __func__, tmr_idx)); 2844 KASSERT(pktc_idx < SGE_NCOUNTERS, /* -ve is ok, means don't use */ 2845 ("%s: bad pktc_idx %d", __func__, pktc_idx)); 2846 2847 iq->flags = 0; 2848 iq->adapter = sc; 2849 iq->intr_params = V_QINTR_TIMER_IDX(tmr_idx); 2850 iq->intr_pktc_idx = SGE_NCOUNTERS - 1; 2851 if (pktc_idx >= 0) { 2852 iq->intr_params |= F_QINTR_CNT_EN; 2853 iq->intr_pktc_idx = pktc_idx; 2854 } 2855 iq->qsize = roundup2(qsize, 16); /* See FW_IQ_CMD/iqsize */ 2856 iq->sidx = iq->qsize - sc->params.sge.spg_len / IQ_ESIZE; 2857 } 2858 2859 static inline void 2860 init_fl(struct adapter *sc, struct sge_fl *fl, int qsize, int maxp, char *name) 2861 { 2862 2863 fl->qsize = qsize; 2864 fl->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE; 2865 strlcpy(fl->lockname, name, sizeof(fl->lockname)); 2866 if (sc->flags & BUF_PACKING_OK && 2867 ((!is_t4(sc) && buffer_packing) || /* T5+: enabled unless 0 */ 2868 (is_t4(sc) && buffer_packing == 1)))/* T4: disabled unless 1 */ 2869 fl->flags |= FL_BUF_PACKING; 2870 find_best_refill_source(sc, fl, maxp); 2871 find_safe_refill_source(sc, fl); 2872 } 2873 2874 static inline void 2875 init_eq(struct adapter *sc, struct sge_eq *eq, int eqtype, int qsize, 2876 uint8_t tx_chan, uint16_t iqid, char *name) 2877 { 2878 KASSERT(eqtype <= EQ_TYPEMASK, ("%s: bad qtype %d", __func__, eqtype)); 2879 2880 eq->flags = eqtype & EQ_TYPEMASK; 2881 eq->tx_chan = tx_chan; 2882 eq->iqid = iqid; 2883 eq->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE; 2884 strlcpy(eq->lockname, name, sizeof(eq->lockname)); 2885 } 2886 2887 static int 2888 alloc_ring(struct adapter *sc, size_t len, bus_dma_tag_t *tag, 2889 bus_dmamap_t *map, bus_addr_t *pa, void **va) 2890 { 2891 int rc; 2892 2893 rc = bus_dma_tag_create(sc->dmat, 512, 0, BUS_SPACE_MAXADDR, 2894 BUS_SPACE_MAXADDR, NULL, NULL, len, 1, len, 0, NULL, NULL, tag); 2895 if (rc != 0) { 2896 device_printf(sc->dev, "cannot allocate DMA tag: %d\n", rc); 2897 goto done; 2898 } 2899 2900 rc = bus_dmamem_alloc(*tag, va, 2901 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, map); 2902 if (rc != 0) { 2903 device_printf(sc->dev, "cannot allocate DMA memory: %d\n", rc); 2904 goto done; 2905 } 2906 2907 rc = bus_dmamap_load(*tag, *map, *va, len, oneseg_dma_callback, pa, 0); 2908 if (rc != 0) { 2909 device_printf(sc->dev, "cannot load DMA map: %d\n", rc); 2910 goto done; 2911 } 2912 done: 2913 if (rc) 2914 free_ring(sc, *tag, *map, *pa, *va); 2915 2916 return (rc); 2917 } 2918 2919 static int 2920 free_ring(struct adapter *sc, bus_dma_tag_t tag, bus_dmamap_t map, 2921 bus_addr_t pa, void *va) 2922 { 2923 if (pa) 2924 bus_dmamap_unload(tag, map); 2925 if (va) 2926 bus_dmamem_free(tag, va, map); 2927 if (tag) 2928 bus_dma_tag_destroy(tag); 2929 2930 return (0); 2931 } 2932 2933 /* 2934 * Allocates the ring for an ingress queue and an optional freelist. If the 2935 * freelist is specified it will be allocated and then associated with the 2936 * ingress queue. 2937 * 2938 * Returns errno on failure. Resources allocated up to that point may still be 2939 * allocated. Caller is responsible for cleanup in case this function fails. 2940 * 2941 * If the ingress queue will take interrupts directly then the intr_idx 2942 * specifies the vector, starting from 0. -1 means the interrupts for this 2943 * queue should be forwarded to the fwq. 2944 */ 2945 static int 2946 alloc_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl, 2947 int intr_idx, int cong) 2948 { 2949 int rc, i, cntxt_id; 2950 size_t len; 2951 struct fw_iq_cmd c; 2952 struct port_info *pi = vi->pi; 2953 struct adapter *sc = iq->adapter; 2954 struct sge_params *sp = &sc->params.sge; 2955 __be32 v = 0; 2956 2957 len = iq->qsize * IQ_ESIZE; 2958 rc = alloc_ring(sc, len, &iq->desc_tag, &iq->desc_map, &iq->ba, 2959 (void **)&iq->desc); 2960 if (rc != 0) 2961 return (rc); 2962 2963 bzero(&c, sizeof(c)); 2964 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 2965 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) | 2966 V_FW_IQ_CMD_VFN(0)); 2967 2968 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART | 2969 FW_LEN16(c)); 2970 2971 /* Special handling for firmware event queue */ 2972 if (iq == &sc->sge.fwq) 2973 v |= F_FW_IQ_CMD_IQASYNCH; 2974 2975 if (intr_idx < 0) { 2976 /* Forwarded interrupts, all headed to fwq */ 2977 v |= F_FW_IQ_CMD_IQANDST; 2978 v |= V_FW_IQ_CMD_IQANDSTINDEX(sc->sge.fwq.cntxt_id); 2979 } else { 2980 KASSERT(intr_idx < sc->intr_count, 2981 ("%s: invalid direct intr_idx %d", __func__, intr_idx)); 2982 v |= V_FW_IQ_CMD_IQANDSTINDEX(intr_idx); 2983 } 2984 2985 c.type_to_iqandstindex = htobe32(v | 2986 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) | 2987 V_FW_IQ_CMD_VIID(vi->viid) | 2988 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT)); 2989 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->tx_chan) | 2990 F_FW_IQ_CMD_IQGTSMODE | 2991 V_FW_IQ_CMD_IQINTCNTTHRESH(iq->intr_pktc_idx) | 2992 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4)); 2993 c.iqsize = htobe16(iq->qsize); 2994 c.iqaddr = htobe64(iq->ba); 2995 if (cong >= 0) 2996 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN); 2997 2998 if (fl) { 2999 mtx_init(&fl->fl_lock, fl->lockname, NULL, MTX_DEF); 3000 3001 len = fl->qsize * EQ_ESIZE; 3002 rc = alloc_ring(sc, len, &fl->desc_tag, &fl->desc_map, 3003 &fl->ba, (void **)&fl->desc); 3004 if (rc) 3005 return (rc); 3006 3007 /* Allocate space for one software descriptor per buffer. */ 3008 rc = alloc_fl_sdesc(fl); 3009 if (rc != 0) { 3010 device_printf(sc->dev, 3011 "failed to setup fl software descriptors: %d\n", 3012 rc); 3013 return (rc); 3014 } 3015 3016 if (fl->flags & FL_BUF_PACKING) { 3017 fl->lowat = roundup2(sp->fl_starve_threshold2, 8); 3018 fl->buf_boundary = sp->pack_boundary; 3019 } else { 3020 fl->lowat = roundup2(sp->fl_starve_threshold, 8); 3021 fl->buf_boundary = 16; 3022 } 3023 if (fl_pad && fl->buf_boundary < sp->pad_boundary) 3024 fl->buf_boundary = sp->pad_boundary; 3025 3026 c.iqns_to_fl0congen |= 3027 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) | 3028 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO | 3029 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) | 3030 (fl->flags & FL_BUF_PACKING ? F_FW_IQ_CMD_FL0PACKEN : 3031 0)); 3032 if (cong >= 0) { 3033 c.iqns_to_fl0congen |= 3034 htobe32(V_FW_IQ_CMD_FL0CNGCHMAP(cong) | 3035 F_FW_IQ_CMD_FL0CONGCIF | 3036 F_FW_IQ_CMD_FL0CONGEN); 3037 } 3038 c.fl0dcaen_to_fl0cidxfthresh = 3039 htobe16(V_FW_IQ_CMD_FL0FBMIN(chip_id(sc) <= CHELSIO_T5 ? 3040 X_FETCHBURSTMIN_128B : X_FETCHBURSTMIN_64B) | 3041 V_FW_IQ_CMD_FL0FBMAX(chip_id(sc) <= CHELSIO_T5 ? 3042 X_FETCHBURSTMAX_512B : X_FETCHBURSTMAX_256B)); 3043 c.fl0size = htobe16(fl->qsize); 3044 c.fl0addr = htobe64(fl->ba); 3045 } 3046 3047 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3048 if (rc != 0) { 3049 device_printf(sc->dev, 3050 "failed to create ingress queue: %d\n", rc); 3051 return (rc); 3052 } 3053 3054 iq->cidx = 0; 3055 iq->gen = F_RSPD_GEN; 3056 iq->intr_next = iq->intr_params; 3057 iq->cntxt_id = be16toh(c.iqid); 3058 iq->abs_id = be16toh(c.physiqid); 3059 iq->flags |= IQ_ALLOCATED; 3060 3061 cntxt_id = iq->cntxt_id - sc->sge.iq_start; 3062 if (cntxt_id >= sc->sge.niq) { 3063 panic ("%s: iq->cntxt_id (%d) more than the max (%d)", __func__, 3064 cntxt_id, sc->sge.niq - 1); 3065 } 3066 sc->sge.iqmap[cntxt_id] = iq; 3067 3068 if (fl) { 3069 u_int qid; 3070 3071 iq->flags |= IQ_HAS_FL; 3072 fl->cntxt_id = be16toh(c.fl0id); 3073 fl->pidx = fl->cidx = 0; 3074 3075 cntxt_id = fl->cntxt_id - sc->sge.eq_start; 3076 if (cntxt_id >= sc->sge.neq) { 3077 panic("%s: fl->cntxt_id (%d) more than the max (%d)", 3078 __func__, cntxt_id, sc->sge.neq - 1); 3079 } 3080 sc->sge.eqmap[cntxt_id] = (void *)fl; 3081 3082 qid = fl->cntxt_id; 3083 if (isset(&sc->doorbells, DOORBELL_UDB)) { 3084 uint32_t s_qpp = sc->params.sge.eq_s_qpp; 3085 uint32_t mask = (1 << s_qpp) - 1; 3086 volatile uint8_t *udb; 3087 3088 udb = sc->udbs_base + UDBS_DB_OFFSET; 3089 udb += (qid >> s_qpp) << PAGE_SHIFT; 3090 qid &= mask; 3091 if (qid < PAGE_SIZE / UDBS_SEG_SIZE) { 3092 udb += qid << UDBS_SEG_SHIFT; 3093 qid = 0; 3094 } 3095 fl->udb = (volatile void *)udb; 3096 } 3097 fl->dbval = V_QID(qid) | sc->chip_params->sge_fl_db; 3098 3099 FL_LOCK(fl); 3100 /* Enough to make sure the SGE doesn't think it's starved */ 3101 refill_fl(sc, fl, fl->lowat); 3102 FL_UNLOCK(fl); 3103 } 3104 3105 if (chip_id(sc) >= CHELSIO_T5 && !(sc->flags & IS_VF) && cong >= 0) { 3106 uint32_t param, val; 3107 3108 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 3109 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) | 3110 V_FW_PARAMS_PARAM_YZ(iq->cntxt_id); 3111 if (cong == 0) 3112 val = 1 << 19; 3113 else { 3114 val = 2 << 19; 3115 for (i = 0; i < 4; i++) { 3116 if (cong & (1 << i)) 3117 val |= 1 << (i << 2); 3118 } 3119 } 3120 3121 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 3122 if (rc != 0) { 3123 /* report error but carry on */ 3124 device_printf(sc->dev, 3125 "failed to set congestion manager context for " 3126 "ingress queue %d: %d\n", iq->cntxt_id, rc); 3127 } 3128 } 3129 3130 /* Enable IQ interrupts */ 3131 atomic_store_rel_int(&iq->state, IQS_IDLE); 3132 t4_write_reg(sc, sc->sge_gts_reg, V_SEINTARM(iq->intr_params) | 3133 V_INGRESSQID(iq->cntxt_id)); 3134 3135 return (0); 3136 } 3137 3138 static int 3139 free_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl) 3140 { 3141 int rc; 3142 struct adapter *sc = iq->adapter; 3143 device_t dev; 3144 3145 if (sc == NULL) 3146 return (0); /* nothing to do */ 3147 3148 dev = vi ? vi->dev : sc->dev; 3149 3150 if (iq->flags & IQ_ALLOCATED) { 3151 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0, 3152 FW_IQ_TYPE_FL_INT_CAP, iq->cntxt_id, 3153 fl ? fl->cntxt_id : 0xffff, 0xffff); 3154 if (rc != 0) { 3155 device_printf(dev, 3156 "failed to free queue %p: %d\n", iq, rc); 3157 return (rc); 3158 } 3159 iq->flags &= ~IQ_ALLOCATED; 3160 } 3161 3162 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, iq->desc); 3163 3164 bzero(iq, sizeof(*iq)); 3165 3166 if (fl) { 3167 free_ring(sc, fl->desc_tag, fl->desc_map, fl->ba, 3168 fl->desc); 3169 3170 if (fl->sdesc) 3171 free_fl_sdesc(sc, fl); 3172 3173 if (mtx_initialized(&fl->fl_lock)) 3174 mtx_destroy(&fl->fl_lock); 3175 3176 bzero(fl, sizeof(*fl)); 3177 } 3178 3179 return (0); 3180 } 3181 3182 static void 3183 add_iq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid, 3184 struct sge_iq *iq) 3185 { 3186 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3187 3188 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, &iq->ba, 3189 "bus address of descriptor ring"); 3190 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3191 iq->qsize * IQ_ESIZE, "descriptor ring size in bytes"); 3192 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "abs_id", 3193 CTLTYPE_INT | CTLFLAG_RD, &iq->abs_id, 0, sysctl_uint16, "I", 3194 "absolute id of the queue"); 3195 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 3196 CTLTYPE_INT | CTLFLAG_RD, &iq->cntxt_id, 0, sysctl_uint16, "I", 3197 "SGE context id of the queue"); 3198 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx", 3199 CTLTYPE_INT | CTLFLAG_RD, &iq->cidx, 0, sysctl_uint16, "I", 3200 "consumer index"); 3201 } 3202 3203 static void 3204 add_fl_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx, 3205 struct sysctl_oid *oid, struct sge_fl *fl) 3206 { 3207 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3208 3209 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL, 3210 "freelist"); 3211 children = SYSCTL_CHILDREN(oid); 3212 3213 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, 3214 &fl->ba, "bus address of descriptor ring"); 3215 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3216 fl->sidx * EQ_ESIZE + sc->params.sge.spg_len, 3217 "desc ring size in bytes"); 3218 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 3219 CTLTYPE_INT | CTLFLAG_RD, &fl->cntxt_id, 0, sysctl_uint16, "I", 3220 "SGE context id of the freelist"); 3221 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "padding", CTLFLAG_RD, NULL, 3222 fl_pad ? 1 : 0, "padding enabled"); 3223 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "packing", CTLFLAG_RD, NULL, 3224 fl->flags & FL_BUF_PACKING ? 1 : 0, "packing enabled"); 3225 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &fl->cidx, 3226 0, "consumer index"); 3227 if (fl->flags & FL_BUF_PACKING) { 3228 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rx_offset", 3229 CTLFLAG_RD, &fl->rx_offset, 0, "packing rx offset"); 3230 } 3231 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &fl->pidx, 3232 0, "producer index"); 3233 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_allocated", 3234 CTLFLAG_RD, &fl->mbuf_allocated, "# of mbuf allocated"); 3235 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_inlined", 3236 CTLFLAG_RD, &fl->mbuf_inlined, "# of mbuf inlined in clusters"); 3237 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_allocated", 3238 CTLFLAG_RD, &fl->cl_allocated, "# of clusters allocated"); 3239 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_recycled", 3240 CTLFLAG_RD, &fl->cl_recycled, "# of clusters recycled"); 3241 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_fast_recycled", 3242 CTLFLAG_RD, &fl->cl_fast_recycled, "# of clusters recycled (fast)"); 3243 } 3244 3245 static int 3246 alloc_fwq(struct adapter *sc) 3247 { 3248 int rc, intr_idx; 3249 struct sge_iq *fwq = &sc->sge.fwq; 3250 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev); 3251 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3252 3253 init_iq(fwq, sc, 0, 0, FW_IQ_QSIZE); 3254 if (sc->flags & IS_VF) 3255 intr_idx = 0; 3256 else 3257 intr_idx = sc->intr_count > 1 ? 1 : 0; 3258 rc = alloc_iq_fl(&sc->port[0]->vi[0], fwq, NULL, intr_idx, -1); 3259 if (rc != 0) { 3260 device_printf(sc->dev, 3261 "failed to create firmware event queue: %d\n", rc); 3262 return (rc); 3263 } 3264 3265 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "fwq", CTLFLAG_RD, 3266 NULL, "firmware event queue"); 3267 add_iq_sysctls(&sc->ctx, oid, fwq); 3268 3269 return (0); 3270 } 3271 3272 static int 3273 free_fwq(struct adapter *sc) 3274 { 3275 return free_iq_fl(NULL, &sc->sge.fwq, NULL); 3276 } 3277 3278 static int 3279 alloc_ctrlq(struct adapter *sc, struct sge_wrq *ctrlq, int idx, 3280 struct sysctl_oid *oid) 3281 { 3282 int rc; 3283 char name[16]; 3284 struct sysctl_oid_list *children; 3285 3286 snprintf(name, sizeof(name), "%s ctrlq%d", device_get_nameunit(sc->dev), 3287 idx); 3288 init_eq(sc, &ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE, sc->port[idx]->tx_chan, 3289 sc->sge.fwq.cntxt_id, name); 3290 3291 children = SYSCTL_CHILDREN(oid); 3292 snprintf(name, sizeof(name), "%d", idx); 3293 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, name, CTLFLAG_RD, 3294 NULL, "ctrl queue"); 3295 rc = alloc_wrq(sc, NULL, ctrlq, oid); 3296 3297 return (rc); 3298 } 3299 3300 int 3301 tnl_cong(struct port_info *pi, int drop) 3302 { 3303 3304 if (drop == -1) 3305 return (-1); 3306 else if (drop == 1) 3307 return (0); 3308 else 3309 return (pi->rx_e_chan_map); 3310 } 3311 3312 static int 3313 alloc_rxq(struct vi_info *vi, struct sge_rxq *rxq, int intr_idx, int idx, 3314 struct sysctl_oid *oid) 3315 { 3316 int rc; 3317 struct adapter *sc = vi->pi->adapter; 3318 struct sysctl_oid_list *children; 3319 char name[16]; 3320 3321 rc = alloc_iq_fl(vi, &rxq->iq, &rxq->fl, intr_idx, 3322 tnl_cong(vi->pi, cong_drop)); 3323 if (rc != 0) 3324 return (rc); 3325 3326 if (idx == 0) 3327 sc->sge.iq_base = rxq->iq.abs_id - rxq->iq.cntxt_id; 3328 else 3329 KASSERT(rxq->iq.cntxt_id + sc->sge.iq_base == rxq->iq.abs_id, 3330 ("iq_base mismatch")); 3331 KASSERT(sc->sge.iq_base == 0 || sc->flags & IS_VF, 3332 ("PF with non-zero iq_base")); 3333 3334 /* 3335 * The freelist is just barely above the starvation threshold right now, 3336 * fill it up a bit more. 3337 */ 3338 FL_LOCK(&rxq->fl); 3339 refill_fl(sc, &rxq->fl, 128); 3340 FL_UNLOCK(&rxq->fl); 3341 3342 #if defined(INET) || defined(INET6) 3343 rc = tcp_lro_init_args(&rxq->lro, vi->ifp, lro_entries, lro_mbufs); 3344 if (rc != 0) 3345 return (rc); 3346 MPASS(rxq->lro.ifp == vi->ifp); /* also indicates LRO init'ed */ 3347 3348 if (vi->ifp->if_capenable & IFCAP_LRO) 3349 rxq->iq.flags |= IQ_LRO_ENABLED; 3350 #endif 3351 rxq->ifp = vi->ifp; 3352 3353 children = SYSCTL_CHILDREN(oid); 3354 3355 snprintf(name, sizeof(name), "%d", idx); 3356 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 3357 NULL, "rx queue"); 3358 children = SYSCTL_CHILDREN(oid); 3359 3360 add_iq_sysctls(&vi->ctx, oid, &rxq->iq); 3361 #if defined(INET) || defined(INET6) 3362 SYSCTL_ADD_U64(&vi->ctx, children, OID_AUTO, "lro_queued", CTLFLAG_RD, 3363 &rxq->lro.lro_queued, 0, NULL); 3364 SYSCTL_ADD_U64(&vi->ctx, children, OID_AUTO, "lro_flushed", CTLFLAG_RD, 3365 &rxq->lro.lro_flushed, 0, NULL); 3366 #endif 3367 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "rxcsum", CTLFLAG_RD, 3368 &rxq->rxcsum, "# of times hardware assisted with checksum"); 3369 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_extraction", 3370 CTLFLAG_RD, &rxq->vlan_extraction, 3371 "# of times hardware extracted 802.1Q tag"); 3372 3373 add_fl_sysctls(sc, &vi->ctx, oid, &rxq->fl); 3374 3375 return (rc); 3376 } 3377 3378 static int 3379 free_rxq(struct vi_info *vi, struct sge_rxq *rxq) 3380 { 3381 int rc; 3382 3383 #if defined(INET) || defined(INET6) 3384 if (rxq->lro.ifp) { 3385 tcp_lro_free(&rxq->lro); 3386 rxq->lro.ifp = NULL; 3387 } 3388 #endif 3389 3390 rc = free_iq_fl(vi, &rxq->iq, &rxq->fl); 3391 if (rc == 0) 3392 bzero(rxq, sizeof(*rxq)); 3393 3394 return (rc); 3395 } 3396 3397 #ifdef TCP_OFFLOAD 3398 static int 3399 alloc_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq, 3400 int intr_idx, int idx, struct sysctl_oid *oid) 3401 { 3402 struct port_info *pi = vi->pi; 3403 int rc; 3404 struct sysctl_oid_list *children; 3405 char name[16]; 3406 3407 rc = alloc_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl, intr_idx, 0); 3408 if (rc != 0) 3409 return (rc); 3410 3411 children = SYSCTL_CHILDREN(oid); 3412 3413 snprintf(name, sizeof(name), "%d", idx); 3414 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 3415 NULL, "rx queue"); 3416 add_iq_sysctls(&vi->ctx, oid, &ofld_rxq->iq); 3417 add_fl_sysctls(pi->adapter, &vi->ctx, oid, &ofld_rxq->fl); 3418 3419 return (rc); 3420 } 3421 3422 static int 3423 free_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq) 3424 { 3425 int rc; 3426 3427 rc = free_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl); 3428 if (rc == 0) 3429 bzero(ofld_rxq, sizeof(*ofld_rxq)); 3430 3431 return (rc); 3432 } 3433 #endif 3434 3435 #ifdef DEV_NETMAP 3436 static int 3437 alloc_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq, int intr_idx, 3438 int idx, struct sysctl_oid *oid) 3439 { 3440 int rc; 3441 struct sysctl_oid_list *children; 3442 struct sysctl_ctx_list *ctx; 3443 char name[16]; 3444 size_t len; 3445 struct adapter *sc = vi->pi->adapter; 3446 struct netmap_adapter *na = NA(vi->ifp); 3447 3448 MPASS(na != NULL); 3449 3450 len = vi->qsize_rxq * IQ_ESIZE; 3451 rc = alloc_ring(sc, len, &nm_rxq->iq_desc_tag, &nm_rxq->iq_desc_map, 3452 &nm_rxq->iq_ba, (void **)&nm_rxq->iq_desc); 3453 if (rc != 0) 3454 return (rc); 3455 3456 len = na->num_rx_desc * EQ_ESIZE + sc->params.sge.spg_len; 3457 rc = alloc_ring(sc, len, &nm_rxq->fl_desc_tag, &nm_rxq->fl_desc_map, 3458 &nm_rxq->fl_ba, (void **)&nm_rxq->fl_desc); 3459 if (rc != 0) 3460 return (rc); 3461 3462 nm_rxq->vi = vi; 3463 nm_rxq->nid = idx; 3464 nm_rxq->iq_cidx = 0; 3465 nm_rxq->iq_sidx = vi->qsize_rxq - sc->params.sge.spg_len / IQ_ESIZE; 3466 nm_rxq->iq_gen = F_RSPD_GEN; 3467 nm_rxq->fl_pidx = nm_rxq->fl_cidx = 0; 3468 nm_rxq->fl_sidx = na->num_rx_desc; 3469 nm_rxq->intr_idx = intr_idx; 3470 nm_rxq->iq_cntxt_id = INVALID_NM_RXQ_CNTXT_ID; 3471 3472 ctx = &vi->ctx; 3473 children = SYSCTL_CHILDREN(oid); 3474 3475 snprintf(name, sizeof(name), "%d", idx); 3476 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, name, CTLFLAG_RD, NULL, 3477 "rx queue"); 3478 children = SYSCTL_CHILDREN(oid); 3479 3480 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "abs_id", 3481 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_abs_id, 0, sysctl_uint16, 3482 "I", "absolute id of the queue"); 3483 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 3484 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cntxt_id, 0, sysctl_uint16, 3485 "I", "SGE context id of the queue"); 3486 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx", 3487 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cidx, 0, sysctl_uint16, "I", 3488 "consumer index"); 3489 3490 children = SYSCTL_CHILDREN(oid); 3491 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL, 3492 "freelist"); 3493 children = SYSCTL_CHILDREN(oid); 3494 3495 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 3496 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->fl_cntxt_id, 0, sysctl_uint16, 3497 "I", "SGE context id of the freelist"); 3498 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, 3499 &nm_rxq->fl_cidx, 0, "consumer index"); 3500 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, 3501 &nm_rxq->fl_pidx, 0, "producer index"); 3502 3503 return (rc); 3504 } 3505 3506 3507 static int 3508 free_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq) 3509 { 3510 struct adapter *sc = vi->pi->adapter; 3511 3512 if (vi->flags & VI_INIT_DONE) 3513 MPASS(nm_rxq->iq_cntxt_id == INVALID_NM_RXQ_CNTXT_ID); 3514 else 3515 MPASS(nm_rxq->iq_cntxt_id == 0); 3516 3517 free_ring(sc, nm_rxq->iq_desc_tag, nm_rxq->iq_desc_map, nm_rxq->iq_ba, 3518 nm_rxq->iq_desc); 3519 free_ring(sc, nm_rxq->fl_desc_tag, nm_rxq->fl_desc_map, nm_rxq->fl_ba, 3520 nm_rxq->fl_desc); 3521 3522 return (0); 3523 } 3524 3525 static int 3526 alloc_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq, int iqidx, int idx, 3527 struct sysctl_oid *oid) 3528 { 3529 int rc; 3530 size_t len; 3531 struct port_info *pi = vi->pi; 3532 struct adapter *sc = pi->adapter; 3533 struct netmap_adapter *na = NA(vi->ifp); 3534 char name[16]; 3535 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3536 3537 len = na->num_tx_desc * EQ_ESIZE + sc->params.sge.spg_len; 3538 rc = alloc_ring(sc, len, &nm_txq->desc_tag, &nm_txq->desc_map, 3539 &nm_txq->ba, (void **)&nm_txq->desc); 3540 if (rc) 3541 return (rc); 3542 3543 nm_txq->pidx = nm_txq->cidx = 0; 3544 nm_txq->sidx = na->num_tx_desc; 3545 nm_txq->nid = idx; 3546 nm_txq->iqidx = iqidx; 3547 nm_txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) | 3548 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(G_FW_VIID_PFN(vi->viid)) | 3549 V_TXPKT_VF(G_FW_VIID_VIN(vi->viid)) | 3550 V_TXPKT_VF_VLD(G_FW_VIID_VIVLD(vi->viid))); 3551 nm_txq->cntxt_id = INVALID_NM_TXQ_CNTXT_ID; 3552 3553 snprintf(name, sizeof(name), "%d", idx); 3554 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 3555 NULL, "netmap tx queue"); 3556 children = SYSCTL_CHILDREN(oid); 3557 3558 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 3559 &nm_txq->cntxt_id, 0, "SGE context id of the queue"); 3560 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx", 3561 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->cidx, 0, sysctl_uint16, "I", 3562 "consumer index"); 3563 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "pidx", 3564 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->pidx, 0, sysctl_uint16, "I", 3565 "producer index"); 3566 3567 return (rc); 3568 } 3569 3570 static int 3571 free_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq) 3572 { 3573 struct adapter *sc = vi->pi->adapter; 3574 3575 if (vi->flags & VI_INIT_DONE) 3576 MPASS(nm_txq->cntxt_id == INVALID_NM_TXQ_CNTXT_ID); 3577 else 3578 MPASS(nm_txq->cntxt_id == 0); 3579 3580 free_ring(sc, nm_txq->desc_tag, nm_txq->desc_map, nm_txq->ba, 3581 nm_txq->desc); 3582 3583 return (0); 3584 } 3585 #endif 3586 3587 static int 3588 ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq) 3589 { 3590 int rc, cntxt_id; 3591 struct fw_eq_ctrl_cmd c; 3592 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 3593 3594 bzero(&c, sizeof(c)); 3595 3596 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | F_FW_CMD_REQUEST | 3597 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_CTRL_CMD_PFN(sc->pf) | 3598 V_FW_EQ_CTRL_CMD_VFN(0)); 3599 c.alloc_to_len16 = htobe32(F_FW_EQ_CTRL_CMD_ALLOC | 3600 F_FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c)); 3601 c.cmpliqid_eqid = htonl(V_FW_EQ_CTRL_CMD_CMPLIQID(eq->iqid)); 3602 c.physeqid_pkd = htobe32(0); 3603 c.fetchszm_to_iqid = 3604 htobe32(V_FW_EQ_CTRL_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 3605 V_FW_EQ_CTRL_CMD_PCIECHN(eq->tx_chan) | 3606 F_FW_EQ_CTRL_CMD_FETCHRO | V_FW_EQ_CTRL_CMD_IQID(eq->iqid)); 3607 c.dcaen_to_eqsize = 3608 htobe32(V_FW_EQ_CTRL_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 3609 V_FW_EQ_CTRL_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 3610 V_FW_EQ_CTRL_CMD_CIDXFTHRESH(X_CIDXFLUSHTHRESH_32) | 3611 V_FW_EQ_CTRL_CMD_EQSIZE(qsize)); 3612 c.eqaddr = htobe64(eq->ba); 3613 3614 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3615 if (rc != 0) { 3616 device_printf(sc->dev, 3617 "failed to create control queue %d: %d\n", eq->tx_chan, rc); 3618 return (rc); 3619 } 3620 eq->flags |= EQ_ALLOCATED; 3621 3622 eq->cntxt_id = G_FW_EQ_CTRL_CMD_EQID(be32toh(c.cmpliqid_eqid)); 3623 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 3624 if (cntxt_id >= sc->sge.neq) 3625 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 3626 cntxt_id, sc->sge.neq - 1); 3627 sc->sge.eqmap[cntxt_id] = eq; 3628 3629 return (rc); 3630 } 3631 3632 static int 3633 eth_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 3634 { 3635 int rc, cntxt_id; 3636 struct fw_eq_eth_cmd c; 3637 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 3638 3639 bzero(&c, sizeof(c)); 3640 3641 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST | 3642 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) | 3643 V_FW_EQ_ETH_CMD_VFN(0)); 3644 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC | 3645 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c)); 3646 c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE | 3647 F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(vi->viid)); 3648 c.fetchszm_to_iqid = 3649 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) | 3650 V_FW_EQ_ETH_CMD_PCIECHN(eq->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO | 3651 V_FW_EQ_ETH_CMD_IQID(eq->iqid)); 3652 c.dcaen_to_eqsize = htobe32(V_FW_EQ_ETH_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 3653 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 3654 V_FW_EQ_ETH_CMD_EQSIZE(qsize)); 3655 c.eqaddr = htobe64(eq->ba); 3656 3657 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3658 if (rc != 0) { 3659 device_printf(vi->dev, 3660 "failed to create Ethernet egress queue: %d\n", rc); 3661 return (rc); 3662 } 3663 eq->flags |= EQ_ALLOCATED; 3664 3665 eq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd)); 3666 eq->abs_id = G_FW_EQ_ETH_CMD_PHYSEQID(be32toh(c.physeqid_pkd)); 3667 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 3668 if (cntxt_id >= sc->sge.neq) 3669 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 3670 cntxt_id, sc->sge.neq - 1); 3671 sc->sge.eqmap[cntxt_id] = eq; 3672 3673 return (rc); 3674 } 3675 3676 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 3677 static int 3678 ofld_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 3679 { 3680 int rc, cntxt_id; 3681 struct fw_eq_ofld_cmd c; 3682 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 3683 3684 bzero(&c, sizeof(c)); 3685 3686 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | F_FW_CMD_REQUEST | 3687 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_OFLD_CMD_PFN(sc->pf) | 3688 V_FW_EQ_OFLD_CMD_VFN(0)); 3689 c.alloc_to_len16 = htonl(F_FW_EQ_OFLD_CMD_ALLOC | 3690 F_FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c)); 3691 c.fetchszm_to_iqid = 3692 htonl(V_FW_EQ_OFLD_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) | 3693 V_FW_EQ_OFLD_CMD_PCIECHN(eq->tx_chan) | 3694 F_FW_EQ_OFLD_CMD_FETCHRO | V_FW_EQ_OFLD_CMD_IQID(eq->iqid)); 3695 c.dcaen_to_eqsize = 3696 htobe32(V_FW_EQ_OFLD_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 3697 V_FW_EQ_OFLD_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 3698 V_FW_EQ_OFLD_CMD_EQSIZE(qsize)); 3699 c.eqaddr = htobe64(eq->ba); 3700 3701 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3702 if (rc != 0) { 3703 device_printf(vi->dev, 3704 "failed to create egress queue for TCP offload: %d\n", rc); 3705 return (rc); 3706 } 3707 eq->flags |= EQ_ALLOCATED; 3708 3709 eq->cntxt_id = G_FW_EQ_OFLD_CMD_EQID(be32toh(c.eqid_pkd)); 3710 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 3711 if (cntxt_id >= sc->sge.neq) 3712 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 3713 cntxt_id, sc->sge.neq - 1); 3714 sc->sge.eqmap[cntxt_id] = eq; 3715 3716 return (rc); 3717 } 3718 #endif 3719 3720 static int 3721 alloc_eq(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 3722 { 3723 int rc, qsize; 3724 size_t len; 3725 3726 mtx_init(&eq->eq_lock, eq->lockname, NULL, MTX_DEF); 3727 3728 qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 3729 len = qsize * EQ_ESIZE; 3730 rc = alloc_ring(sc, len, &eq->desc_tag, &eq->desc_map, 3731 &eq->ba, (void **)&eq->desc); 3732 if (rc) 3733 return (rc); 3734 3735 eq->pidx = eq->cidx = 0; 3736 eq->equeqidx = eq->dbidx = 0; 3737 eq->doorbells = sc->doorbells; 3738 3739 switch (eq->flags & EQ_TYPEMASK) { 3740 case EQ_CTRL: 3741 rc = ctrl_eq_alloc(sc, eq); 3742 break; 3743 3744 case EQ_ETH: 3745 rc = eth_eq_alloc(sc, vi, eq); 3746 break; 3747 3748 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 3749 case EQ_OFLD: 3750 rc = ofld_eq_alloc(sc, vi, eq); 3751 break; 3752 #endif 3753 3754 default: 3755 panic("%s: invalid eq type %d.", __func__, 3756 eq->flags & EQ_TYPEMASK); 3757 } 3758 if (rc != 0) { 3759 device_printf(sc->dev, 3760 "failed to allocate egress queue(%d): %d\n", 3761 eq->flags & EQ_TYPEMASK, rc); 3762 } 3763 3764 if (isset(&eq->doorbells, DOORBELL_UDB) || 3765 isset(&eq->doorbells, DOORBELL_UDBWC) || 3766 isset(&eq->doorbells, DOORBELL_WCWR)) { 3767 uint32_t s_qpp = sc->params.sge.eq_s_qpp; 3768 uint32_t mask = (1 << s_qpp) - 1; 3769 volatile uint8_t *udb; 3770 3771 udb = sc->udbs_base + UDBS_DB_OFFSET; 3772 udb += (eq->cntxt_id >> s_qpp) << PAGE_SHIFT; /* pg offset */ 3773 eq->udb_qid = eq->cntxt_id & mask; /* id in page */ 3774 if (eq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE) 3775 clrbit(&eq->doorbells, DOORBELL_WCWR); 3776 else { 3777 udb += eq->udb_qid << UDBS_SEG_SHIFT; /* seg offset */ 3778 eq->udb_qid = 0; 3779 } 3780 eq->udb = (volatile void *)udb; 3781 } 3782 3783 return (rc); 3784 } 3785 3786 static int 3787 free_eq(struct adapter *sc, struct sge_eq *eq) 3788 { 3789 int rc; 3790 3791 if (eq->flags & EQ_ALLOCATED) { 3792 switch (eq->flags & EQ_TYPEMASK) { 3793 case EQ_CTRL: 3794 rc = -t4_ctrl_eq_free(sc, sc->mbox, sc->pf, 0, 3795 eq->cntxt_id); 3796 break; 3797 3798 case EQ_ETH: 3799 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0, 3800 eq->cntxt_id); 3801 break; 3802 3803 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 3804 case EQ_OFLD: 3805 rc = -t4_ofld_eq_free(sc, sc->mbox, sc->pf, 0, 3806 eq->cntxt_id); 3807 break; 3808 #endif 3809 3810 default: 3811 panic("%s: invalid eq type %d.", __func__, 3812 eq->flags & EQ_TYPEMASK); 3813 } 3814 if (rc != 0) { 3815 device_printf(sc->dev, 3816 "failed to free egress queue (%d): %d\n", 3817 eq->flags & EQ_TYPEMASK, rc); 3818 return (rc); 3819 } 3820 eq->flags &= ~EQ_ALLOCATED; 3821 } 3822 3823 free_ring(sc, eq->desc_tag, eq->desc_map, eq->ba, eq->desc); 3824 3825 if (mtx_initialized(&eq->eq_lock)) 3826 mtx_destroy(&eq->eq_lock); 3827 3828 bzero(eq, sizeof(*eq)); 3829 return (0); 3830 } 3831 3832 static int 3833 alloc_wrq(struct adapter *sc, struct vi_info *vi, struct sge_wrq *wrq, 3834 struct sysctl_oid *oid) 3835 { 3836 int rc; 3837 struct sysctl_ctx_list *ctx = vi ? &vi->ctx : &sc->ctx; 3838 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3839 3840 rc = alloc_eq(sc, vi, &wrq->eq); 3841 if (rc) 3842 return (rc); 3843 3844 wrq->adapter = sc; 3845 TASK_INIT(&wrq->wrq_tx_task, 0, wrq_tx_drain, wrq); 3846 TAILQ_INIT(&wrq->incomplete_wrs); 3847 STAILQ_INIT(&wrq->wr_list); 3848 wrq->nwr_pending = 0; 3849 wrq->ndesc_needed = 0; 3850 3851 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, 3852 &wrq->eq.ba, "bus address of descriptor ring"); 3853 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3854 wrq->eq.sidx * EQ_ESIZE + sc->params.sge.spg_len, 3855 "desc ring size in bytes"); 3856 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 3857 &wrq->eq.cntxt_id, 0, "SGE context id of the queue"); 3858 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx", 3859 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.cidx, 0, sysctl_uint16, "I", 3860 "consumer index"); 3861 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pidx", 3862 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.pidx, 0, sysctl_uint16, "I", 3863 "producer index"); 3864 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL, 3865 wrq->eq.sidx, "status page index"); 3866 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_direct", CTLFLAG_RD, 3867 &wrq->tx_wrs_direct, "# of work requests (direct)"); 3868 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_copied", CTLFLAG_RD, 3869 &wrq->tx_wrs_copied, "# of work requests (copied)"); 3870 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_sspace", CTLFLAG_RD, 3871 &wrq->tx_wrs_ss, "# of work requests (copied from scratch space)"); 3872 3873 return (rc); 3874 } 3875 3876 static int 3877 free_wrq(struct adapter *sc, struct sge_wrq *wrq) 3878 { 3879 int rc; 3880 3881 rc = free_eq(sc, &wrq->eq); 3882 if (rc) 3883 return (rc); 3884 3885 bzero(wrq, sizeof(*wrq)); 3886 return (0); 3887 } 3888 3889 static int 3890 alloc_txq(struct vi_info *vi, struct sge_txq *txq, int idx, 3891 struct sysctl_oid *oid) 3892 { 3893 int rc; 3894 struct port_info *pi = vi->pi; 3895 struct adapter *sc = pi->adapter; 3896 struct sge_eq *eq = &txq->eq; 3897 char name[16]; 3898 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3899 3900 rc = mp_ring_alloc(&txq->r, eq->sidx, txq, eth_tx, can_resume_eth_tx, 3901 M_CXGBE, M_WAITOK); 3902 if (rc != 0) { 3903 device_printf(sc->dev, "failed to allocate mp_ring: %d\n", rc); 3904 return (rc); 3905 } 3906 3907 rc = alloc_eq(sc, vi, eq); 3908 if (rc != 0) { 3909 mp_ring_free(txq->r); 3910 txq->r = NULL; 3911 return (rc); 3912 } 3913 3914 /* Can't fail after this point. */ 3915 3916 if (idx == 0) 3917 sc->sge.eq_base = eq->abs_id - eq->cntxt_id; 3918 else 3919 KASSERT(eq->cntxt_id + sc->sge.eq_base == eq->abs_id, 3920 ("eq_base mismatch")); 3921 KASSERT(sc->sge.eq_base == 0 || sc->flags & IS_VF, 3922 ("PF with non-zero eq_base")); 3923 3924 TASK_INIT(&txq->tx_reclaim_task, 0, tx_reclaim, eq); 3925 txq->ifp = vi->ifp; 3926 txq->gl = sglist_alloc(TX_SGL_SEGS, M_WAITOK); 3927 if (sc->flags & IS_VF) 3928 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) | 3929 V_TXPKT_INTF(pi->tx_chan)); 3930 else 3931 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) | 3932 V_TXPKT_INTF(pi->tx_chan) | 3933 V_TXPKT_PF(G_FW_VIID_PFN(vi->viid)) | 3934 V_TXPKT_VF(G_FW_VIID_VIN(vi->viid)) | 3935 V_TXPKT_VF_VLD(G_FW_VIID_VIVLD(vi->viid))); 3936 txq->tc_idx = -1; 3937 txq->sdesc = malloc(eq->sidx * sizeof(struct tx_sdesc), M_CXGBE, 3938 M_ZERO | M_WAITOK); 3939 3940 snprintf(name, sizeof(name), "%d", idx); 3941 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 3942 NULL, "tx queue"); 3943 children = SYSCTL_CHILDREN(oid); 3944 3945 SYSCTL_ADD_UAUTO(&vi->ctx, children, OID_AUTO, "ba", CTLFLAG_RD, 3946 &eq->ba, "bus address of descriptor ring"); 3947 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3948 eq->sidx * EQ_ESIZE + sc->params.sge.spg_len, 3949 "desc ring size in bytes"); 3950 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "abs_id", CTLFLAG_RD, 3951 &eq->abs_id, 0, "absolute id of the queue"); 3952 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 3953 &eq->cntxt_id, 0, "SGE context id of the queue"); 3954 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx", 3955 CTLTYPE_INT | CTLFLAG_RD, &eq->cidx, 0, sysctl_uint16, "I", 3956 "consumer index"); 3957 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "pidx", 3958 CTLTYPE_INT | CTLFLAG_RD, &eq->pidx, 0, sysctl_uint16, "I", 3959 "producer index"); 3960 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL, 3961 eq->sidx, "status page index"); 3962 3963 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "tc", 3964 CTLTYPE_INT | CTLFLAG_RW, vi, idx, sysctl_tc, "I", 3965 "traffic class (-1 means none)"); 3966 3967 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txcsum", CTLFLAG_RD, 3968 &txq->txcsum, "# of times hardware assisted with checksum"); 3969 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_insertion", 3970 CTLFLAG_RD, &txq->vlan_insertion, 3971 "# of times hardware inserted 802.1Q tag"); 3972 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "tso_wrs", CTLFLAG_RD, 3973 &txq->tso_wrs, "# of TSO work requests"); 3974 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "imm_wrs", CTLFLAG_RD, 3975 &txq->imm_wrs, "# of work requests with immediate data"); 3976 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "sgl_wrs", CTLFLAG_RD, 3977 &txq->sgl_wrs, "# of work requests with direct SGL"); 3978 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkt_wrs", CTLFLAG_RD, 3979 &txq->txpkt_wrs, "# of txpkt work requests (one pkt/WR)"); 3980 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_wrs", 3981 CTLFLAG_RD, &txq->txpkts0_wrs, 3982 "# of txpkts (type 0) work requests"); 3983 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_wrs", 3984 CTLFLAG_RD, &txq->txpkts1_wrs, 3985 "# of txpkts (type 1) work requests"); 3986 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_pkts", 3987 CTLFLAG_RD, &txq->txpkts0_pkts, 3988 "# of frames tx'd using type0 txpkts work requests"); 3989 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_pkts", 3990 CTLFLAG_RD, &txq->txpkts1_pkts, 3991 "# of frames tx'd using type1 txpkts work requests"); 3992 3993 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_enqueues", 3994 CTLFLAG_RD, &txq->r->enqueues, 3995 "# of enqueues to the mp_ring for this queue"); 3996 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_drops", 3997 CTLFLAG_RD, &txq->r->drops, 3998 "# of drops in the mp_ring for this queue"); 3999 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_starts", 4000 CTLFLAG_RD, &txq->r->starts, 4001 "# of normal consumer starts in the mp_ring for this queue"); 4002 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_stalls", 4003 CTLFLAG_RD, &txq->r->stalls, 4004 "# of consumer stalls in the mp_ring for this queue"); 4005 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_restarts", 4006 CTLFLAG_RD, &txq->r->restarts, 4007 "# of consumer restarts in the mp_ring for this queue"); 4008 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_abdications", 4009 CTLFLAG_RD, &txq->r->abdications, 4010 "# of consumer abdications in the mp_ring for this queue"); 4011 4012 return (0); 4013 } 4014 4015 static int 4016 free_txq(struct vi_info *vi, struct sge_txq *txq) 4017 { 4018 int rc; 4019 struct adapter *sc = vi->pi->adapter; 4020 struct sge_eq *eq = &txq->eq; 4021 4022 rc = free_eq(sc, eq); 4023 if (rc) 4024 return (rc); 4025 4026 sglist_free(txq->gl); 4027 free(txq->sdesc, M_CXGBE); 4028 mp_ring_free(txq->r); 4029 4030 bzero(txq, sizeof(*txq)); 4031 return (0); 4032 } 4033 4034 static void 4035 oneseg_dma_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error) 4036 { 4037 bus_addr_t *ba = arg; 4038 4039 KASSERT(nseg == 1, 4040 ("%s meant for single segment mappings only.", __func__)); 4041 4042 *ba = error ? 0 : segs->ds_addr; 4043 } 4044 4045 static inline void 4046 ring_fl_db(struct adapter *sc, struct sge_fl *fl) 4047 { 4048 uint32_t n, v; 4049 4050 n = IDXDIFF(fl->pidx / 8, fl->dbidx, fl->sidx); 4051 MPASS(n > 0); 4052 4053 wmb(); 4054 v = fl->dbval | V_PIDX(n); 4055 if (fl->udb) 4056 *fl->udb = htole32(v); 4057 else 4058 t4_write_reg(sc, sc->sge_kdoorbell_reg, v); 4059 IDXINCR(fl->dbidx, n, fl->sidx); 4060 } 4061 4062 /* 4063 * Fills up the freelist by allocating up to 'n' buffers. Buffers that are 4064 * recycled do not count towards this allocation budget. 4065 * 4066 * Returns non-zero to indicate that this freelist should be added to the list 4067 * of starving freelists. 4068 */ 4069 static int 4070 refill_fl(struct adapter *sc, struct sge_fl *fl, int n) 4071 { 4072 __be64 *d; 4073 struct fl_sdesc *sd; 4074 uintptr_t pa; 4075 caddr_t cl; 4076 struct cluster_layout *cll; 4077 struct sw_zone_info *swz; 4078 struct cluster_metadata *clm; 4079 uint16_t max_pidx; 4080 uint16_t hw_cidx = fl->hw_cidx; /* stable snapshot */ 4081 4082 FL_LOCK_ASSERT_OWNED(fl); 4083 4084 /* 4085 * We always stop at the beginning of the hardware descriptor that's just 4086 * before the one with the hw cidx. This is to avoid hw pidx = hw cidx, 4087 * which would mean an empty freelist to the chip. 4088 */ 4089 max_pidx = __predict_false(hw_cidx == 0) ? fl->sidx - 1 : hw_cidx - 1; 4090 if (fl->pidx == max_pidx * 8) 4091 return (0); 4092 4093 d = &fl->desc[fl->pidx]; 4094 sd = &fl->sdesc[fl->pidx]; 4095 cll = &fl->cll_def; /* default layout */ 4096 swz = &sc->sge.sw_zone_info[cll->zidx]; 4097 4098 while (n > 0) { 4099 4100 if (sd->cl != NULL) { 4101 4102 if (sd->nmbuf == 0) { 4103 /* 4104 * Fast recycle without involving any atomics on 4105 * the cluster's metadata (if the cluster has 4106 * metadata). This happens when all frames 4107 * received in the cluster were small enough to 4108 * fit within a single mbuf each. 4109 */ 4110 fl->cl_fast_recycled++; 4111 #ifdef INVARIANTS 4112 clm = cl_metadata(sc, fl, &sd->cll, sd->cl); 4113 if (clm != NULL) 4114 MPASS(clm->refcount == 1); 4115 #endif 4116 goto recycled_fast; 4117 } 4118 4119 /* 4120 * Cluster is guaranteed to have metadata. Clusters 4121 * without metadata always take the fast recycle path 4122 * when they're recycled. 4123 */ 4124 clm = cl_metadata(sc, fl, &sd->cll, sd->cl); 4125 MPASS(clm != NULL); 4126 4127 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) { 4128 fl->cl_recycled++; 4129 counter_u64_add(extfree_rels, 1); 4130 goto recycled; 4131 } 4132 sd->cl = NULL; /* gave up my reference */ 4133 } 4134 MPASS(sd->cl == NULL); 4135 alloc: 4136 cl = uma_zalloc(swz->zone, M_NOWAIT); 4137 if (__predict_false(cl == NULL)) { 4138 if (cll == &fl->cll_alt || fl->cll_alt.zidx == -1 || 4139 fl->cll_def.zidx == fl->cll_alt.zidx) 4140 break; 4141 4142 /* fall back to the safe zone */ 4143 cll = &fl->cll_alt; 4144 swz = &sc->sge.sw_zone_info[cll->zidx]; 4145 goto alloc; 4146 } 4147 fl->cl_allocated++; 4148 n--; 4149 4150 pa = pmap_kextract((vm_offset_t)cl); 4151 pa += cll->region1; 4152 sd->cl = cl; 4153 sd->cll = *cll; 4154 *d = htobe64(pa | cll->hwidx); 4155 clm = cl_metadata(sc, fl, cll, cl); 4156 if (clm != NULL) { 4157 recycled: 4158 #ifdef INVARIANTS 4159 clm->sd = sd; 4160 #endif 4161 clm->refcount = 1; 4162 } 4163 sd->nmbuf = 0; 4164 recycled_fast: 4165 d++; 4166 sd++; 4167 if (__predict_false(++fl->pidx % 8 == 0)) { 4168 uint16_t pidx = fl->pidx / 8; 4169 4170 if (__predict_false(pidx == fl->sidx)) { 4171 fl->pidx = 0; 4172 pidx = 0; 4173 sd = fl->sdesc; 4174 d = fl->desc; 4175 } 4176 if (pidx == max_pidx) 4177 break; 4178 4179 if (IDXDIFF(pidx, fl->dbidx, fl->sidx) >= 4) 4180 ring_fl_db(sc, fl); 4181 } 4182 } 4183 4184 if (fl->pidx / 8 != fl->dbidx) 4185 ring_fl_db(sc, fl); 4186 4187 return (FL_RUNNING_LOW(fl) && !(fl->flags & FL_STARVING)); 4188 } 4189 4190 /* 4191 * Attempt to refill all starving freelists. 4192 */ 4193 static void 4194 refill_sfl(void *arg) 4195 { 4196 struct adapter *sc = arg; 4197 struct sge_fl *fl, *fl_temp; 4198 4199 mtx_assert(&sc->sfl_lock, MA_OWNED); 4200 TAILQ_FOREACH_SAFE(fl, &sc->sfl, link, fl_temp) { 4201 FL_LOCK(fl); 4202 refill_fl(sc, fl, 64); 4203 if (FL_NOT_RUNNING_LOW(fl) || fl->flags & FL_DOOMED) { 4204 TAILQ_REMOVE(&sc->sfl, fl, link); 4205 fl->flags &= ~FL_STARVING; 4206 } 4207 FL_UNLOCK(fl); 4208 } 4209 4210 if (!TAILQ_EMPTY(&sc->sfl)) 4211 callout_schedule(&sc->sfl_callout, hz / 5); 4212 } 4213 4214 static int 4215 alloc_fl_sdesc(struct sge_fl *fl) 4216 { 4217 4218 fl->sdesc = malloc(fl->sidx * 8 * sizeof(struct fl_sdesc), M_CXGBE, 4219 M_ZERO | M_WAITOK); 4220 4221 return (0); 4222 } 4223 4224 static void 4225 free_fl_sdesc(struct adapter *sc, struct sge_fl *fl) 4226 { 4227 struct fl_sdesc *sd; 4228 struct cluster_metadata *clm; 4229 struct cluster_layout *cll; 4230 int i; 4231 4232 sd = fl->sdesc; 4233 for (i = 0; i < fl->sidx * 8; i++, sd++) { 4234 if (sd->cl == NULL) 4235 continue; 4236 4237 cll = &sd->cll; 4238 clm = cl_metadata(sc, fl, cll, sd->cl); 4239 if (sd->nmbuf == 0) 4240 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl); 4241 else if (clm && atomic_fetchadd_int(&clm->refcount, -1) == 1) { 4242 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl); 4243 counter_u64_add(extfree_rels, 1); 4244 } 4245 sd->cl = NULL; 4246 } 4247 4248 free(fl->sdesc, M_CXGBE); 4249 fl->sdesc = NULL; 4250 } 4251 4252 static inline void 4253 get_pkt_gl(struct mbuf *m, struct sglist *gl) 4254 { 4255 int rc; 4256 4257 M_ASSERTPKTHDR(m); 4258 4259 sglist_reset(gl); 4260 rc = sglist_append_mbuf(gl, m); 4261 if (__predict_false(rc != 0)) { 4262 panic("%s: mbuf %p (%d segs) was vetted earlier but now fails " 4263 "with %d.", __func__, m, mbuf_nsegs(m), rc); 4264 } 4265 4266 KASSERT(gl->sg_nseg == mbuf_nsegs(m), 4267 ("%s: nsegs changed for mbuf %p from %d to %d", __func__, m, 4268 mbuf_nsegs(m), gl->sg_nseg)); 4269 KASSERT(gl->sg_nseg > 0 && 4270 gl->sg_nseg <= (needs_tso(m) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS), 4271 ("%s: %d segments, should have been 1 <= nsegs <= %d", __func__, 4272 gl->sg_nseg, needs_tso(m) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS)); 4273 } 4274 4275 /* 4276 * len16 for a txpkt WR with a GL. Includes the firmware work request header. 4277 */ 4278 static inline u_int 4279 txpkt_len16(u_int nsegs, u_int tso) 4280 { 4281 u_int n; 4282 4283 MPASS(nsegs > 0); 4284 4285 nsegs--; /* first segment is part of ulptx_sgl */ 4286 n = sizeof(struct fw_eth_tx_pkt_wr) + sizeof(struct cpl_tx_pkt_core) + 4287 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 4288 if (tso) 4289 n += sizeof(struct cpl_tx_pkt_lso_core); 4290 4291 return (howmany(n, 16)); 4292 } 4293 4294 /* 4295 * len16 for a txpkt_vm WR with a GL. Includes the firmware work 4296 * request header. 4297 */ 4298 static inline u_int 4299 txpkt_vm_len16(u_int nsegs, u_int tso) 4300 { 4301 u_int n; 4302 4303 MPASS(nsegs > 0); 4304 4305 nsegs--; /* first segment is part of ulptx_sgl */ 4306 n = sizeof(struct fw_eth_tx_pkt_vm_wr) + 4307 sizeof(struct cpl_tx_pkt_core) + 4308 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 4309 if (tso) 4310 n += sizeof(struct cpl_tx_pkt_lso_core); 4311 4312 return (howmany(n, 16)); 4313 } 4314 4315 /* 4316 * len16 for a txpkts type 0 WR with a GL. Does not include the firmware work 4317 * request header. 4318 */ 4319 static inline u_int 4320 txpkts0_len16(u_int nsegs) 4321 { 4322 u_int n; 4323 4324 MPASS(nsegs > 0); 4325 4326 nsegs--; /* first segment is part of ulptx_sgl */ 4327 n = sizeof(struct ulp_txpkt) + sizeof(struct ulptx_idata) + 4328 sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl) + 4329 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 4330 4331 return (howmany(n, 16)); 4332 } 4333 4334 /* 4335 * len16 for a txpkts type 1 WR with a GL. Does not include the firmware work 4336 * request header. 4337 */ 4338 static inline u_int 4339 txpkts1_len16(void) 4340 { 4341 u_int n; 4342 4343 n = sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl); 4344 4345 return (howmany(n, 16)); 4346 } 4347 4348 static inline u_int 4349 imm_payload(u_int ndesc) 4350 { 4351 u_int n; 4352 4353 n = ndesc * EQ_ESIZE - sizeof(struct fw_eth_tx_pkt_wr) - 4354 sizeof(struct cpl_tx_pkt_core); 4355 4356 return (n); 4357 } 4358 4359 /* 4360 * Write a VM txpkt WR for this packet to the hardware descriptors, update the 4361 * software descriptor, and advance the pidx. It is guaranteed that enough 4362 * descriptors are available. 4363 * 4364 * The return value is the # of hardware descriptors used. 4365 */ 4366 static u_int 4367 write_txpkt_vm_wr(struct adapter *sc, struct sge_txq *txq, 4368 struct fw_eth_tx_pkt_vm_wr *wr, struct mbuf *m0, u_int available) 4369 { 4370 struct sge_eq *eq = &txq->eq; 4371 struct tx_sdesc *txsd; 4372 struct cpl_tx_pkt_core *cpl; 4373 uint32_t ctrl; /* used in many unrelated places */ 4374 uint64_t ctrl1; 4375 int csum_type, len16, ndesc, pktlen, nsegs; 4376 caddr_t dst; 4377 4378 TXQ_LOCK_ASSERT_OWNED(txq); 4379 M_ASSERTPKTHDR(m0); 4380 MPASS(available > 0 && available < eq->sidx); 4381 4382 len16 = mbuf_len16(m0); 4383 nsegs = mbuf_nsegs(m0); 4384 pktlen = m0->m_pkthdr.len; 4385 ctrl = sizeof(struct cpl_tx_pkt_core); 4386 if (needs_tso(m0)) 4387 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 4388 ndesc = howmany(len16, EQ_ESIZE / 16); 4389 MPASS(ndesc <= available); 4390 4391 /* Firmware work request header */ 4392 MPASS(wr == (void *)&eq->desc[eq->pidx]); 4393 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_VM_WR) | 4394 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl)); 4395 4396 ctrl = V_FW_WR_LEN16(len16); 4397 wr->equiq_to_len16 = htobe32(ctrl); 4398 wr->r3[0] = 0; 4399 wr->r3[1] = 0; 4400 4401 /* 4402 * Copy over ethmacdst, ethmacsrc, ethtype, and vlantci. 4403 * vlantci is ignored unless the ethtype is 0x8100, so it's 4404 * simpler to always copy it rather than making it 4405 * conditional. Also, it seems that we do not have to set 4406 * vlantci or fake the ethtype when doing VLAN tag insertion. 4407 */ 4408 m_copydata(m0, 0, sizeof(struct ether_header) + 2, wr->ethmacdst); 4409 4410 csum_type = -1; 4411 if (needs_tso(m0)) { 4412 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1); 4413 4414 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 4415 m0->m_pkthdr.l4hlen > 0, 4416 ("%s: mbuf %p needs TSO but missing header lengths", 4417 __func__, m0)); 4418 4419 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE | 4420 F_LSO_LAST_SLICE | V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) 4421 | V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2); 4422 if (m0->m_pkthdr.l2hlen == sizeof(struct ether_vlan_header)) 4423 ctrl |= V_LSO_ETHHDR_LEN(1); 4424 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 4425 ctrl |= F_LSO_IPV6; 4426 4427 lso->lso_ctrl = htobe32(ctrl); 4428 lso->ipid_ofst = htobe16(0); 4429 lso->mss = htobe16(m0->m_pkthdr.tso_segsz); 4430 lso->seqno_offset = htobe32(0); 4431 lso->len = htobe32(pktlen); 4432 4433 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 4434 csum_type = TX_CSUM_TCPIP6; 4435 else 4436 csum_type = TX_CSUM_TCPIP; 4437 4438 cpl = (void *)(lso + 1); 4439 4440 txq->tso_wrs++; 4441 } else { 4442 if (m0->m_pkthdr.csum_flags & CSUM_IP_TCP) 4443 csum_type = TX_CSUM_TCPIP; 4444 else if (m0->m_pkthdr.csum_flags & CSUM_IP_UDP) 4445 csum_type = TX_CSUM_UDPIP; 4446 else if (m0->m_pkthdr.csum_flags & CSUM_IP6_TCP) 4447 csum_type = TX_CSUM_TCPIP6; 4448 else if (m0->m_pkthdr.csum_flags & CSUM_IP6_UDP) 4449 csum_type = TX_CSUM_UDPIP6; 4450 #if defined(INET) 4451 else if (m0->m_pkthdr.csum_flags & CSUM_IP) { 4452 /* 4453 * XXX: The firmware appears to stomp on the 4454 * fragment/flags field of the IP header when 4455 * using TX_CSUM_IP. Fall back to doing 4456 * software checksums. 4457 */ 4458 u_short *sump; 4459 struct mbuf *m; 4460 int offset; 4461 4462 m = m0; 4463 offset = 0; 4464 sump = m_advance(&m, &offset, m0->m_pkthdr.l2hlen + 4465 offsetof(struct ip, ip_sum)); 4466 *sump = in_cksum_skip(m0, m0->m_pkthdr.l2hlen + 4467 m0->m_pkthdr.l3hlen, m0->m_pkthdr.l2hlen); 4468 m0->m_pkthdr.csum_flags &= ~CSUM_IP; 4469 } 4470 #endif 4471 4472 cpl = (void *)(wr + 1); 4473 } 4474 4475 /* Checksum offload */ 4476 ctrl1 = 0; 4477 if (needs_l3_csum(m0) == 0) 4478 ctrl1 |= F_TXPKT_IPCSUM_DIS; 4479 if (csum_type >= 0) { 4480 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0, 4481 ("%s: mbuf %p needs checksum offload but missing header lengths", 4482 __func__, m0)); 4483 4484 if (chip_id(sc) <= CHELSIO_T5) { 4485 ctrl1 |= V_TXPKT_ETHHDR_LEN(m0->m_pkthdr.l2hlen - 4486 ETHER_HDR_LEN); 4487 } else { 4488 ctrl1 |= V_T6_TXPKT_ETHHDR_LEN(m0->m_pkthdr.l2hlen - 4489 ETHER_HDR_LEN); 4490 } 4491 ctrl1 |= V_TXPKT_IPHDR_LEN(m0->m_pkthdr.l3hlen); 4492 ctrl1 |= V_TXPKT_CSUM_TYPE(csum_type); 4493 } else 4494 ctrl1 |= F_TXPKT_L4CSUM_DIS; 4495 if (m0->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | 4496 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO)) 4497 txq->txcsum++; /* some hardware assistance provided */ 4498 4499 /* VLAN tag insertion */ 4500 if (needs_vlan_insertion(m0)) { 4501 ctrl1 |= F_TXPKT_VLAN_VLD | 4502 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 4503 txq->vlan_insertion++; 4504 } 4505 4506 /* CPL header */ 4507 cpl->ctrl0 = txq->cpl_ctrl0; 4508 cpl->pack = 0; 4509 cpl->len = htobe16(pktlen); 4510 cpl->ctrl1 = htobe64(ctrl1); 4511 4512 /* SGL */ 4513 dst = (void *)(cpl + 1); 4514 4515 /* 4516 * A packet using TSO will use up an entire descriptor for the 4517 * firmware work request header, LSO CPL, and TX_PKT_XT CPL. 4518 * If this descriptor is the last descriptor in the ring, wrap 4519 * around to the front of the ring explicitly for the start of 4520 * the sgl. 4521 */ 4522 if (dst == (void *)&eq->desc[eq->sidx]) { 4523 dst = (void *)&eq->desc[0]; 4524 write_gl_to_txd(txq, m0, &dst, 0); 4525 } else 4526 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx); 4527 txq->sgl_wrs++; 4528 4529 txq->txpkt_wrs++; 4530 4531 txsd = &txq->sdesc[eq->pidx]; 4532 txsd->m = m0; 4533 txsd->desc_used = ndesc; 4534 4535 return (ndesc); 4536 } 4537 4538 /* 4539 * Write a txpkt WR for this packet to the hardware descriptors, update the 4540 * software descriptor, and advance the pidx. It is guaranteed that enough 4541 * descriptors are available. 4542 * 4543 * The return value is the # of hardware descriptors used. 4544 */ 4545 static u_int 4546 write_txpkt_wr(struct sge_txq *txq, struct fw_eth_tx_pkt_wr *wr, 4547 struct mbuf *m0, u_int available) 4548 { 4549 struct sge_eq *eq = &txq->eq; 4550 struct tx_sdesc *txsd; 4551 struct cpl_tx_pkt_core *cpl; 4552 uint32_t ctrl; /* used in many unrelated places */ 4553 uint64_t ctrl1; 4554 int len16, ndesc, pktlen, nsegs; 4555 caddr_t dst; 4556 4557 TXQ_LOCK_ASSERT_OWNED(txq); 4558 M_ASSERTPKTHDR(m0); 4559 MPASS(available > 0 && available < eq->sidx); 4560 4561 len16 = mbuf_len16(m0); 4562 nsegs = mbuf_nsegs(m0); 4563 pktlen = m0->m_pkthdr.len; 4564 ctrl = sizeof(struct cpl_tx_pkt_core); 4565 if (needs_tso(m0)) 4566 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 4567 else if (pktlen <= imm_payload(2) && available >= 2) { 4568 /* Immediate data. Recalculate len16 and set nsegs to 0. */ 4569 ctrl += pktlen; 4570 len16 = howmany(sizeof(struct fw_eth_tx_pkt_wr) + 4571 sizeof(struct cpl_tx_pkt_core) + pktlen, 16); 4572 nsegs = 0; 4573 } 4574 ndesc = howmany(len16, EQ_ESIZE / 16); 4575 MPASS(ndesc <= available); 4576 4577 /* Firmware work request header */ 4578 MPASS(wr == (void *)&eq->desc[eq->pidx]); 4579 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_WR) | 4580 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl)); 4581 4582 ctrl = V_FW_WR_LEN16(len16); 4583 wr->equiq_to_len16 = htobe32(ctrl); 4584 wr->r3 = 0; 4585 4586 if (needs_tso(m0)) { 4587 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1); 4588 4589 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 4590 m0->m_pkthdr.l4hlen > 0, 4591 ("%s: mbuf %p needs TSO but missing header lengths", 4592 __func__, m0)); 4593 4594 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE | 4595 F_LSO_LAST_SLICE | V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) 4596 | V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2); 4597 if (m0->m_pkthdr.l2hlen == sizeof(struct ether_vlan_header)) 4598 ctrl |= V_LSO_ETHHDR_LEN(1); 4599 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 4600 ctrl |= F_LSO_IPV6; 4601 4602 lso->lso_ctrl = htobe32(ctrl); 4603 lso->ipid_ofst = htobe16(0); 4604 lso->mss = htobe16(m0->m_pkthdr.tso_segsz); 4605 lso->seqno_offset = htobe32(0); 4606 lso->len = htobe32(pktlen); 4607 4608 cpl = (void *)(lso + 1); 4609 4610 txq->tso_wrs++; 4611 } else 4612 cpl = (void *)(wr + 1); 4613 4614 /* Checksum offload */ 4615 ctrl1 = 0; 4616 if (needs_l3_csum(m0) == 0) 4617 ctrl1 |= F_TXPKT_IPCSUM_DIS; 4618 if (needs_l4_csum(m0) == 0) 4619 ctrl1 |= F_TXPKT_L4CSUM_DIS; 4620 if (m0->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | 4621 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO)) 4622 txq->txcsum++; /* some hardware assistance provided */ 4623 4624 /* VLAN tag insertion */ 4625 if (needs_vlan_insertion(m0)) { 4626 ctrl1 |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 4627 txq->vlan_insertion++; 4628 } 4629 4630 /* CPL header */ 4631 cpl->ctrl0 = txq->cpl_ctrl0; 4632 cpl->pack = 0; 4633 cpl->len = htobe16(pktlen); 4634 cpl->ctrl1 = htobe64(ctrl1); 4635 4636 /* SGL */ 4637 dst = (void *)(cpl + 1); 4638 if (nsegs > 0) { 4639 4640 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx); 4641 txq->sgl_wrs++; 4642 } else { 4643 struct mbuf *m; 4644 4645 for (m = m0; m != NULL; m = m->m_next) { 4646 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len); 4647 #ifdef INVARIANTS 4648 pktlen -= m->m_len; 4649 #endif 4650 } 4651 #ifdef INVARIANTS 4652 KASSERT(pktlen == 0, ("%s: %d bytes left.", __func__, pktlen)); 4653 #endif 4654 txq->imm_wrs++; 4655 } 4656 4657 txq->txpkt_wrs++; 4658 4659 txsd = &txq->sdesc[eq->pidx]; 4660 txsd->m = m0; 4661 txsd->desc_used = ndesc; 4662 4663 return (ndesc); 4664 } 4665 4666 static int 4667 try_txpkts(struct mbuf *m, struct mbuf *n, struct txpkts *txp, u_int available) 4668 { 4669 u_int needed, nsegs1, nsegs2, l1, l2; 4670 4671 if (cannot_use_txpkts(m) || cannot_use_txpkts(n)) 4672 return (1); 4673 4674 nsegs1 = mbuf_nsegs(m); 4675 nsegs2 = mbuf_nsegs(n); 4676 if (nsegs1 + nsegs2 == 2) { 4677 txp->wr_type = 1; 4678 l1 = l2 = txpkts1_len16(); 4679 } else { 4680 txp->wr_type = 0; 4681 l1 = txpkts0_len16(nsegs1); 4682 l2 = txpkts0_len16(nsegs2); 4683 } 4684 txp->len16 = howmany(sizeof(struct fw_eth_tx_pkts_wr), 16) + l1 + l2; 4685 needed = howmany(txp->len16, EQ_ESIZE / 16); 4686 if (needed > SGE_MAX_WR_NDESC || needed > available) 4687 return (1); 4688 4689 txp->plen = m->m_pkthdr.len + n->m_pkthdr.len; 4690 if (txp->plen > 65535) 4691 return (1); 4692 4693 txp->npkt = 2; 4694 set_mbuf_len16(m, l1); 4695 set_mbuf_len16(n, l2); 4696 4697 return (0); 4698 } 4699 4700 static int 4701 add_to_txpkts(struct mbuf *m, struct txpkts *txp, u_int available) 4702 { 4703 u_int plen, len16, needed, nsegs; 4704 4705 MPASS(txp->wr_type == 0 || txp->wr_type == 1); 4706 4707 nsegs = mbuf_nsegs(m); 4708 if (needs_tso(m) || (txp->wr_type == 1 && nsegs != 1)) 4709 return (1); 4710 4711 plen = txp->plen + m->m_pkthdr.len; 4712 if (plen > 65535) 4713 return (1); 4714 4715 if (txp->wr_type == 0) 4716 len16 = txpkts0_len16(nsegs); 4717 else 4718 len16 = txpkts1_len16(); 4719 needed = howmany(txp->len16 + len16, EQ_ESIZE / 16); 4720 if (needed > SGE_MAX_WR_NDESC || needed > available) 4721 return (1); 4722 4723 txp->npkt++; 4724 txp->plen = plen; 4725 txp->len16 += len16; 4726 set_mbuf_len16(m, len16); 4727 4728 return (0); 4729 } 4730 4731 /* 4732 * Write a txpkts WR for the packets in txp to the hardware descriptors, update 4733 * the software descriptor, and advance the pidx. It is guaranteed that enough 4734 * descriptors are available. 4735 * 4736 * The return value is the # of hardware descriptors used. 4737 */ 4738 static u_int 4739 write_txpkts_wr(struct sge_txq *txq, struct fw_eth_tx_pkts_wr *wr, 4740 struct mbuf *m0, const struct txpkts *txp, u_int available) 4741 { 4742 struct sge_eq *eq = &txq->eq; 4743 struct tx_sdesc *txsd; 4744 struct cpl_tx_pkt_core *cpl; 4745 uint32_t ctrl; 4746 uint64_t ctrl1; 4747 int ndesc, checkwrap; 4748 struct mbuf *m; 4749 void *flitp; 4750 4751 TXQ_LOCK_ASSERT_OWNED(txq); 4752 MPASS(txp->npkt > 0); 4753 MPASS(txp->plen < 65536); 4754 MPASS(m0 != NULL); 4755 MPASS(m0->m_nextpkt != NULL); 4756 MPASS(txp->len16 <= howmany(SGE_MAX_WR_LEN, 16)); 4757 MPASS(available > 0 && available < eq->sidx); 4758 4759 ndesc = howmany(txp->len16, EQ_ESIZE / 16); 4760 MPASS(ndesc <= available); 4761 4762 MPASS(wr == (void *)&eq->desc[eq->pidx]); 4763 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR)); 4764 ctrl = V_FW_WR_LEN16(txp->len16); 4765 wr->equiq_to_len16 = htobe32(ctrl); 4766 wr->plen = htobe16(txp->plen); 4767 wr->npkt = txp->npkt; 4768 wr->r3 = 0; 4769 wr->type = txp->wr_type; 4770 flitp = wr + 1; 4771 4772 /* 4773 * At this point we are 16B into a hardware descriptor. If checkwrap is 4774 * set then we know the WR is going to wrap around somewhere. We'll 4775 * check for that at appropriate points. 4776 */ 4777 checkwrap = eq->sidx - ndesc < eq->pidx; 4778 for (m = m0; m != NULL; m = m->m_nextpkt) { 4779 if (txp->wr_type == 0) { 4780 struct ulp_txpkt *ulpmc; 4781 struct ulptx_idata *ulpsc; 4782 4783 /* ULP master command */ 4784 ulpmc = flitp; 4785 ulpmc->cmd_dest = htobe32(V_ULPTX_CMD(ULP_TX_PKT) | 4786 V_ULP_TXPKT_DEST(0) | V_ULP_TXPKT_FID(eq->iqid)); 4787 ulpmc->len = htobe32(mbuf_len16(m)); 4788 4789 /* ULP subcommand */ 4790 ulpsc = (void *)(ulpmc + 1); 4791 ulpsc->cmd_more = htobe32(V_ULPTX_CMD(ULP_TX_SC_IMM) | 4792 F_ULP_TX_SC_MORE); 4793 ulpsc->len = htobe32(sizeof(struct cpl_tx_pkt_core)); 4794 4795 cpl = (void *)(ulpsc + 1); 4796 if (checkwrap && 4797 (uintptr_t)cpl == (uintptr_t)&eq->desc[eq->sidx]) 4798 cpl = (void *)&eq->desc[0]; 4799 } else { 4800 cpl = flitp; 4801 } 4802 4803 /* Checksum offload */ 4804 ctrl1 = 0; 4805 if (needs_l3_csum(m) == 0) 4806 ctrl1 |= F_TXPKT_IPCSUM_DIS; 4807 if (needs_l4_csum(m) == 0) 4808 ctrl1 |= F_TXPKT_L4CSUM_DIS; 4809 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | 4810 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO)) 4811 txq->txcsum++; /* some hardware assistance provided */ 4812 4813 /* VLAN tag insertion */ 4814 if (needs_vlan_insertion(m)) { 4815 ctrl1 |= F_TXPKT_VLAN_VLD | 4816 V_TXPKT_VLAN(m->m_pkthdr.ether_vtag); 4817 txq->vlan_insertion++; 4818 } 4819 4820 /* CPL header */ 4821 cpl->ctrl0 = txq->cpl_ctrl0; 4822 cpl->pack = 0; 4823 cpl->len = htobe16(m->m_pkthdr.len); 4824 cpl->ctrl1 = htobe64(ctrl1); 4825 4826 flitp = cpl + 1; 4827 if (checkwrap && 4828 (uintptr_t)flitp == (uintptr_t)&eq->desc[eq->sidx]) 4829 flitp = (void *)&eq->desc[0]; 4830 4831 write_gl_to_txd(txq, m, (caddr_t *)(&flitp), checkwrap); 4832 4833 } 4834 4835 if (txp->wr_type == 0) { 4836 txq->txpkts0_pkts += txp->npkt; 4837 txq->txpkts0_wrs++; 4838 } else { 4839 txq->txpkts1_pkts += txp->npkt; 4840 txq->txpkts1_wrs++; 4841 } 4842 4843 txsd = &txq->sdesc[eq->pidx]; 4844 txsd->m = m0; 4845 txsd->desc_used = ndesc; 4846 4847 return (ndesc); 4848 } 4849 4850 /* 4851 * If the SGL ends on an address that is not 16 byte aligned, this function will 4852 * add a 0 filled flit at the end. 4853 */ 4854 static void 4855 write_gl_to_txd(struct sge_txq *txq, struct mbuf *m, caddr_t *to, int checkwrap) 4856 { 4857 struct sge_eq *eq = &txq->eq; 4858 struct sglist *gl = txq->gl; 4859 struct sglist_seg *seg; 4860 __be64 *flitp, *wrap; 4861 struct ulptx_sgl *usgl; 4862 int i, nflits, nsegs; 4863 4864 KASSERT(((uintptr_t)(*to) & 0xf) == 0, 4865 ("%s: SGL must start at a 16 byte boundary: %p", __func__, *to)); 4866 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]); 4867 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]); 4868 4869 get_pkt_gl(m, gl); 4870 nsegs = gl->sg_nseg; 4871 MPASS(nsegs > 0); 4872 4873 nflits = (3 * (nsegs - 1)) / 2 + ((nsegs - 1) & 1) + 2; 4874 flitp = (__be64 *)(*to); 4875 wrap = (__be64 *)(&eq->desc[eq->sidx]); 4876 seg = &gl->sg_segs[0]; 4877 usgl = (void *)flitp; 4878 4879 /* 4880 * We start at a 16 byte boundary somewhere inside the tx descriptor 4881 * ring, so we're at least 16 bytes away from the status page. There is 4882 * no chance of a wrap around in the middle of usgl (which is 16 bytes). 4883 */ 4884 4885 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 4886 V_ULPTX_NSGE(nsegs)); 4887 usgl->len0 = htobe32(seg->ss_len); 4888 usgl->addr0 = htobe64(seg->ss_paddr); 4889 seg++; 4890 4891 if (checkwrap == 0 || (uintptr_t)(flitp + nflits) <= (uintptr_t)wrap) { 4892 4893 /* Won't wrap around at all */ 4894 4895 for (i = 0; i < nsegs - 1; i++, seg++) { 4896 usgl->sge[i / 2].len[i & 1] = htobe32(seg->ss_len); 4897 usgl->sge[i / 2].addr[i & 1] = htobe64(seg->ss_paddr); 4898 } 4899 if (i & 1) 4900 usgl->sge[i / 2].len[1] = htobe32(0); 4901 flitp += nflits; 4902 } else { 4903 4904 /* Will wrap somewhere in the rest of the SGL */ 4905 4906 /* 2 flits already written, write the rest flit by flit */ 4907 flitp = (void *)(usgl + 1); 4908 for (i = 0; i < nflits - 2; i++) { 4909 if (flitp == wrap) 4910 flitp = (void *)eq->desc; 4911 *flitp++ = get_flit(seg, nsegs - 1, i); 4912 } 4913 } 4914 4915 if (nflits & 1) { 4916 MPASS(((uintptr_t)flitp) & 0xf); 4917 *flitp++ = 0; 4918 } 4919 4920 MPASS((((uintptr_t)flitp) & 0xf) == 0); 4921 if (__predict_false(flitp == wrap)) 4922 *to = (void *)eq->desc; 4923 else 4924 *to = (void *)flitp; 4925 } 4926 4927 static inline void 4928 copy_to_txd(struct sge_eq *eq, caddr_t from, caddr_t *to, int len) 4929 { 4930 4931 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]); 4932 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]); 4933 4934 if (__predict_true((uintptr_t)(*to) + len <= 4935 (uintptr_t)&eq->desc[eq->sidx])) { 4936 bcopy(from, *to, len); 4937 (*to) += len; 4938 } else { 4939 int portion = (uintptr_t)&eq->desc[eq->sidx] - (uintptr_t)(*to); 4940 4941 bcopy(from, *to, portion); 4942 from += portion; 4943 portion = len - portion; /* remaining */ 4944 bcopy(from, (void *)eq->desc, portion); 4945 (*to) = (caddr_t)eq->desc + portion; 4946 } 4947 } 4948 4949 static inline void 4950 ring_eq_db(struct adapter *sc, struct sge_eq *eq, u_int n) 4951 { 4952 u_int db; 4953 4954 MPASS(n > 0); 4955 4956 db = eq->doorbells; 4957 if (n > 1) 4958 clrbit(&db, DOORBELL_WCWR); 4959 wmb(); 4960 4961 switch (ffs(db) - 1) { 4962 case DOORBELL_UDB: 4963 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n)); 4964 break; 4965 4966 case DOORBELL_WCWR: { 4967 volatile uint64_t *dst, *src; 4968 int i; 4969 4970 /* 4971 * Queues whose 128B doorbell segment fits in the page do not 4972 * use relative qid (udb_qid is always 0). Only queues with 4973 * doorbell segments can do WCWR. 4974 */ 4975 KASSERT(eq->udb_qid == 0 && n == 1, 4976 ("%s: inappropriate doorbell (0x%x, %d, %d) for eq %p", 4977 __func__, eq->doorbells, n, eq->dbidx, eq)); 4978 4979 dst = (volatile void *)((uintptr_t)eq->udb + UDBS_WR_OFFSET - 4980 UDBS_DB_OFFSET); 4981 i = eq->dbidx; 4982 src = (void *)&eq->desc[i]; 4983 while (src != (void *)&eq->desc[i + 1]) 4984 *dst++ = *src++; 4985 wmb(); 4986 break; 4987 } 4988 4989 case DOORBELL_UDBWC: 4990 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n)); 4991 wmb(); 4992 break; 4993 4994 case DOORBELL_KDB: 4995 t4_write_reg(sc, sc->sge_kdoorbell_reg, 4996 V_QID(eq->cntxt_id) | V_PIDX(n)); 4997 break; 4998 } 4999 5000 IDXINCR(eq->dbidx, n, eq->sidx); 5001 } 5002 5003 static inline u_int 5004 reclaimable_tx_desc(struct sge_eq *eq) 5005 { 5006 uint16_t hw_cidx; 5007 5008 hw_cidx = read_hw_cidx(eq); 5009 return (IDXDIFF(hw_cidx, eq->cidx, eq->sidx)); 5010 } 5011 5012 static inline u_int 5013 total_available_tx_desc(struct sge_eq *eq) 5014 { 5015 uint16_t hw_cidx, pidx; 5016 5017 hw_cidx = read_hw_cidx(eq); 5018 pidx = eq->pidx; 5019 5020 if (pidx == hw_cidx) 5021 return (eq->sidx - 1); 5022 else 5023 return (IDXDIFF(hw_cidx, pidx, eq->sidx) - 1); 5024 } 5025 5026 static inline uint16_t 5027 read_hw_cidx(struct sge_eq *eq) 5028 { 5029 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx]; 5030 uint16_t cidx = spg->cidx; /* stable snapshot */ 5031 5032 return (be16toh(cidx)); 5033 } 5034 5035 /* 5036 * Reclaim 'n' descriptors approximately. 5037 */ 5038 static u_int 5039 reclaim_tx_descs(struct sge_txq *txq, u_int n) 5040 { 5041 struct tx_sdesc *txsd; 5042 struct sge_eq *eq = &txq->eq; 5043 u_int can_reclaim, reclaimed; 5044 5045 TXQ_LOCK_ASSERT_OWNED(txq); 5046 MPASS(n > 0); 5047 5048 reclaimed = 0; 5049 can_reclaim = reclaimable_tx_desc(eq); 5050 while (can_reclaim && reclaimed < n) { 5051 int ndesc; 5052 struct mbuf *m, *nextpkt; 5053 5054 txsd = &txq->sdesc[eq->cidx]; 5055 ndesc = txsd->desc_used; 5056 5057 /* Firmware doesn't return "partial" credits. */ 5058 KASSERT(can_reclaim >= ndesc, 5059 ("%s: unexpected number of credits: %d, %d", 5060 __func__, can_reclaim, ndesc)); 5061 5062 for (m = txsd->m; m != NULL; m = nextpkt) { 5063 nextpkt = m->m_nextpkt; 5064 m->m_nextpkt = NULL; 5065 m_freem(m); 5066 } 5067 reclaimed += ndesc; 5068 can_reclaim -= ndesc; 5069 IDXINCR(eq->cidx, ndesc, eq->sidx); 5070 } 5071 5072 return (reclaimed); 5073 } 5074 5075 static void 5076 tx_reclaim(void *arg, int n) 5077 { 5078 struct sge_txq *txq = arg; 5079 struct sge_eq *eq = &txq->eq; 5080 5081 do { 5082 if (TXQ_TRYLOCK(txq) == 0) 5083 break; 5084 n = reclaim_tx_descs(txq, 32); 5085 if (eq->cidx == eq->pidx) 5086 eq->equeqidx = eq->pidx; 5087 TXQ_UNLOCK(txq); 5088 } while (n > 0); 5089 } 5090 5091 static __be64 5092 get_flit(struct sglist_seg *segs, int nsegs, int idx) 5093 { 5094 int i = (idx / 3) * 2; 5095 5096 switch (idx % 3) { 5097 case 0: { 5098 uint64_t rc; 5099 5100 rc = (uint64_t)segs[i].ss_len << 32; 5101 if (i + 1 < nsegs) 5102 rc |= (uint64_t)(segs[i + 1].ss_len); 5103 5104 return (htobe64(rc)); 5105 } 5106 case 1: 5107 return (htobe64(segs[i].ss_paddr)); 5108 case 2: 5109 return (htobe64(segs[i + 1].ss_paddr)); 5110 } 5111 5112 return (0); 5113 } 5114 5115 static void 5116 find_best_refill_source(struct adapter *sc, struct sge_fl *fl, int maxp) 5117 { 5118 int8_t zidx, hwidx, idx; 5119 uint16_t region1, region3; 5120 int spare, spare_needed, n; 5121 struct sw_zone_info *swz; 5122 struct hw_buf_info *hwb, *hwb_list = &sc->sge.hw_buf_info[0]; 5123 5124 /* 5125 * Buffer Packing: Look for PAGE_SIZE or larger zone which has a bufsize 5126 * large enough for the max payload and cluster metadata. Otherwise 5127 * settle for the largest bufsize that leaves enough room in the cluster 5128 * for metadata. 5129 * 5130 * Without buffer packing: Look for the smallest zone which has a 5131 * bufsize large enough for the max payload. Settle for the largest 5132 * bufsize available if there's nothing big enough for max payload. 5133 */ 5134 spare_needed = fl->flags & FL_BUF_PACKING ? CL_METADATA_SIZE : 0; 5135 swz = &sc->sge.sw_zone_info[0]; 5136 hwidx = -1; 5137 for (zidx = 0; zidx < SW_ZONE_SIZES; zidx++, swz++) { 5138 if (swz->size > largest_rx_cluster) { 5139 if (__predict_true(hwidx != -1)) 5140 break; 5141 5142 /* 5143 * This is a misconfiguration. largest_rx_cluster is 5144 * preventing us from finding a refill source. See 5145 * dev.t5nex.<n>.buffer_sizes to figure out why. 5146 */ 5147 device_printf(sc->dev, "largest_rx_cluster=%u leaves no" 5148 " refill source for fl %p (dma %u). Ignored.\n", 5149 largest_rx_cluster, fl, maxp); 5150 } 5151 for (idx = swz->head_hwidx; idx != -1; idx = hwb->next) { 5152 hwb = &hwb_list[idx]; 5153 spare = swz->size - hwb->size; 5154 if (spare < spare_needed) 5155 continue; 5156 5157 hwidx = idx; /* best option so far */ 5158 if (hwb->size >= maxp) { 5159 5160 if ((fl->flags & FL_BUF_PACKING) == 0) 5161 goto done; /* stop looking (not packing) */ 5162 5163 if (swz->size >= safest_rx_cluster) 5164 goto done; /* stop looking (packing) */ 5165 } 5166 break; /* keep looking, next zone */ 5167 } 5168 } 5169 done: 5170 /* A usable hwidx has been located. */ 5171 MPASS(hwidx != -1); 5172 hwb = &hwb_list[hwidx]; 5173 zidx = hwb->zidx; 5174 swz = &sc->sge.sw_zone_info[zidx]; 5175 region1 = 0; 5176 region3 = swz->size - hwb->size; 5177 5178 /* 5179 * Stay within this zone and see if there is a better match when mbuf 5180 * inlining is allowed. Remember that the hwidx's are sorted in 5181 * decreasing order of size (so in increasing order of spare area). 5182 */ 5183 for (idx = hwidx; idx != -1; idx = hwb->next) { 5184 hwb = &hwb_list[idx]; 5185 spare = swz->size - hwb->size; 5186 5187 if (allow_mbufs_in_cluster == 0 || hwb->size < maxp) 5188 break; 5189 5190 /* 5191 * Do not inline mbufs if doing so would violate the pad/pack 5192 * boundary alignment requirement. 5193 */ 5194 if (fl_pad && (MSIZE % sc->params.sge.pad_boundary) != 0) 5195 continue; 5196 if (fl->flags & FL_BUF_PACKING && 5197 (MSIZE % sc->params.sge.pack_boundary) != 0) 5198 continue; 5199 5200 if (spare < CL_METADATA_SIZE + MSIZE) 5201 continue; 5202 n = (spare - CL_METADATA_SIZE) / MSIZE; 5203 if (n > howmany(hwb->size, maxp)) 5204 break; 5205 5206 hwidx = idx; 5207 if (fl->flags & FL_BUF_PACKING) { 5208 region1 = n * MSIZE; 5209 region3 = spare - region1; 5210 } else { 5211 region1 = MSIZE; 5212 region3 = spare - region1; 5213 break; 5214 } 5215 } 5216 5217 KASSERT(zidx >= 0 && zidx < SW_ZONE_SIZES, 5218 ("%s: bad zone %d for fl %p, maxp %d", __func__, zidx, fl, maxp)); 5219 KASSERT(hwidx >= 0 && hwidx <= SGE_FLBUF_SIZES, 5220 ("%s: bad hwidx %d for fl %p, maxp %d", __func__, hwidx, fl, maxp)); 5221 KASSERT(region1 + sc->sge.hw_buf_info[hwidx].size + region3 == 5222 sc->sge.sw_zone_info[zidx].size, 5223 ("%s: bad buffer layout for fl %p, maxp %d. " 5224 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp, 5225 sc->sge.sw_zone_info[zidx].size, region1, 5226 sc->sge.hw_buf_info[hwidx].size, region3)); 5227 if (fl->flags & FL_BUF_PACKING || region1 > 0) { 5228 KASSERT(region3 >= CL_METADATA_SIZE, 5229 ("%s: no room for metadata. fl %p, maxp %d; " 5230 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp, 5231 sc->sge.sw_zone_info[zidx].size, region1, 5232 sc->sge.hw_buf_info[hwidx].size, region3)); 5233 KASSERT(region1 % MSIZE == 0, 5234 ("%s: bad mbuf region for fl %p, maxp %d. " 5235 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp, 5236 sc->sge.sw_zone_info[zidx].size, region1, 5237 sc->sge.hw_buf_info[hwidx].size, region3)); 5238 } 5239 5240 fl->cll_def.zidx = zidx; 5241 fl->cll_def.hwidx = hwidx; 5242 fl->cll_def.region1 = region1; 5243 fl->cll_def.region3 = region3; 5244 } 5245 5246 static void 5247 find_safe_refill_source(struct adapter *sc, struct sge_fl *fl) 5248 { 5249 struct sge *s = &sc->sge; 5250 struct hw_buf_info *hwb; 5251 struct sw_zone_info *swz; 5252 int spare; 5253 int8_t hwidx; 5254 5255 if (fl->flags & FL_BUF_PACKING) 5256 hwidx = s->safe_hwidx2; /* with room for metadata */ 5257 else if (allow_mbufs_in_cluster && s->safe_hwidx2 != -1) { 5258 hwidx = s->safe_hwidx2; 5259 hwb = &s->hw_buf_info[hwidx]; 5260 swz = &s->sw_zone_info[hwb->zidx]; 5261 spare = swz->size - hwb->size; 5262 5263 /* no good if there isn't room for an mbuf as well */ 5264 if (spare < CL_METADATA_SIZE + MSIZE) 5265 hwidx = s->safe_hwidx1; 5266 } else 5267 hwidx = s->safe_hwidx1; 5268 5269 if (hwidx == -1) { 5270 /* No fallback source */ 5271 fl->cll_alt.hwidx = -1; 5272 fl->cll_alt.zidx = -1; 5273 5274 return; 5275 } 5276 5277 hwb = &s->hw_buf_info[hwidx]; 5278 swz = &s->sw_zone_info[hwb->zidx]; 5279 spare = swz->size - hwb->size; 5280 fl->cll_alt.hwidx = hwidx; 5281 fl->cll_alt.zidx = hwb->zidx; 5282 if (allow_mbufs_in_cluster && 5283 (fl_pad == 0 || (MSIZE % sc->params.sge.pad_boundary) == 0)) 5284 fl->cll_alt.region1 = ((spare - CL_METADATA_SIZE) / MSIZE) * MSIZE; 5285 else 5286 fl->cll_alt.region1 = 0; 5287 fl->cll_alt.region3 = spare - fl->cll_alt.region1; 5288 } 5289 5290 static void 5291 add_fl_to_sfl(struct adapter *sc, struct sge_fl *fl) 5292 { 5293 mtx_lock(&sc->sfl_lock); 5294 FL_LOCK(fl); 5295 if ((fl->flags & FL_DOOMED) == 0) { 5296 fl->flags |= FL_STARVING; 5297 TAILQ_INSERT_TAIL(&sc->sfl, fl, link); 5298 callout_reset(&sc->sfl_callout, hz / 5, refill_sfl, sc); 5299 } 5300 FL_UNLOCK(fl); 5301 mtx_unlock(&sc->sfl_lock); 5302 } 5303 5304 static void 5305 handle_wrq_egr_update(struct adapter *sc, struct sge_eq *eq) 5306 { 5307 struct sge_wrq *wrq = (void *)eq; 5308 5309 atomic_readandclear_int(&eq->equiq); 5310 taskqueue_enqueue(sc->tq[eq->tx_chan], &wrq->wrq_tx_task); 5311 } 5312 5313 static void 5314 handle_eth_egr_update(struct adapter *sc, struct sge_eq *eq) 5315 { 5316 struct sge_txq *txq = (void *)eq; 5317 5318 MPASS((eq->flags & EQ_TYPEMASK) == EQ_ETH); 5319 5320 atomic_readandclear_int(&eq->equiq); 5321 mp_ring_check_drainage(txq->r, 0); 5322 taskqueue_enqueue(sc->tq[eq->tx_chan], &txq->tx_reclaim_task); 5323 } 5324 5325 static int 5326 handle_sge_egr_update(struct sge_iq *iq, const struct rss_header *rss, 5327 struct mbuf *m) 5328 { 5329 const struct cpl_sge_egr_update *cpl = (const void *)(rss + 1); 5330 unsigned int qid = G_EGR_QID(ntohl(cpl->opcode_qid)); 5331 struct adapter *sc = iq->adapter; 5332 struct sge *s = &sc->sge; 5333 struct sge_eq *eq; 5334 static void (*h[])(struct adapter *, struct sge_eq *) = {NULL, 5335 &handle_wrq_egr_update, &handle_eth_egr_update, 5336 &handle_wrq_egr_update}; 5337 5338 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 5339 rss->opcode)); 5340 5341 eq = s->eqmap[qid - s->eq_start - s->eq_base]; 5342 (*h[eq->flags & EQ_TYPEMASK])(sc, eq); 5343 5344 return (0); 5345 } 5346 5347 /* handle_fw_msg works for both fw4_msg and fw6_msg because this is valid */ 5348 CTASSERT(offsetof(struct cpl_fw4_msg, data) == \ 5349 offsetof(struct cpl_fw6_msg, data)); 5350 5351 static int 5352 handle_fw_msg(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 5353 { 5354 struct adapter *sc = iq->adapter; 5355 const struct cpl_fw6_msg *cpl = (const void *)(rss + 1); 5356 5357 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 5358 rss->opcode)); 5359 5360 if (cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL) { 5361 const struct rss_header *rss2; 5362 5363 rss2 = (const struct rss_header *)&cpl->data[0]; 5364 return (t4_cpl_handler[rss2->opcode](iq, rss2, m)); 5365 } 5366 5367 return (t4_fw_msg_handler[cpl->type](sc, &cpl->data[0])); 5368 } 5369 5370 /** 5371 * t4_handle_wrerr_rpl - process a FW work request error message 5372 * @adap: the adapter 5373 * @rpl: start of the FW message 5374 */ 5375 static int 5376 t4_handle_wrerr_rpl(struct adapter *adap, const __be64 *rpl) 5377 { 5378 u8 opcode = *(const u8 *)rpl; 5379 const struct fw_error_cmd *e = (const void *)rpl; 5380 unsigned int i; 5381 5382 if (opcode != FW_ERROR_CMD) { 5383 log(LOG_ERR, 5384 "%s: Received WRERR_RPL message with opcode %#x\n", 5385 device_get_nameunit(adap->dev), opcode); 5386 return (EINVAL); 5387 } 5388 log(LOG_ERR, "%s: FW_ERROR (%s) ", device_get_nameunit(adap->dev), 5389 G_FW_ERROR_CMD_FATAL(be32toh(e->op_to_type)) ? "fatal" : 5390 "non-fatal"); 5391 switch (G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type))) { 5392 case FW_ERROR_TYPE_EXCEPTION: 5393 log(LOG_ERR, "exception info:\n"); 5394 for (i = 0; i < nitems(e->u.exception.info); i++) 5395 log(LOG_ERR, "%s%08x", i == 0 ? "\t" : " ", 5396 be32toh(e->u.exception.info[i])); 5397 log(LOG_ERR, "\n"); 5398 break; 5399 case FW_ERROR_TYPE_HWMODULE: 5400 log(LOG_ERR, "HW module regaddr %08x regval %08x\n", 5401 be32toh(e->u.hwmodule.regaddr), 5402 be32toh(e->u.hwmodule.regval)); 5403 break; 5404 case FW_ERROR_TYPE_WR: 5405 log(LOG_ERR, "WR cidx %d PF %d VF %d eqid %d hdr:\n", 5406 be16toh(e->u.wr.cidx), 5407 G_FW_ERROR_CMD_PFN(be16toh(e->u.wr.pfn_vfn)), 5408 G_FW_ERROR_CMD_VFN(be16toh(e->u.wr.pfn_vfn)), 5409 be32toh(e->u.wr.eqid)); 5410 for (i = 0; i < nitems(e->u.wr.wrhdr); i++) 5411 log(LOG_ERR, "%s%02x", i == 0 ? "\t" : " ", 5412 e->u.wr.wrhdr[i]); 5413 log(LOG_ERR, "\n"); 5414 break; 5415 case FW_ERROR_TYPE_ACL: 5416 log(LOG_ERR, "ACL cidx %d PF %d VF %d eqid %d %s", 5417 be16toh(e->u.acl.cidx), 5418 G_FW_ERROR_CMD_PFN(be16toh(e->u.acl.pfn_vfn)), 5419 G_FW_ERROR_CMD_VFN(be16toh(e->u.acl.pfn_vfn)), 5420 be32toh(e->u.acl.eqid), 5421 G_FW_ERROR_CMD_MV(be16toh(e->u.acl.mv_pkd)) ? "vlanid" : 5422 "MAC"); 5423 for (i = 0; i < nitems(e->u.acl.val); i++) 5424 log(LOG_ERR, " %02x", e->u.acl.val[i]); 5425 log(LOG_ERR, "\n"); 5426 break; 5427 default: 5428 log(LOG_ERR, "type %#x\n", 5429 G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type))); 5430 return (EINVAL); 5431 } 5432 return (0); 5433 } 5434 5435 static int 5436 sysctl_uint16(SYSCTL_HANDLER_ARGS) 5437 { 5438 uint16_t *id = arg1; 5439 int i = *id; 5440 5441 return sysctl_handle_int(oidp, &i, 0, req); 5442 } 5443 5444 static int 5445 sysctl_bufsizes(SYSCTL_HANDLER_ARGS) 5446 { 5447 struct sge *s = arg1; 5448 struct hw_buf_info *hwb = &s->hw_buf_info[0]; 5449 struct sw_zone_info *swz = &s->sw_zone_info[0]; 5450 int i, rc; 5451 struct sbuf sb; 5452 char c; 5453 5454 sbuf_new(&sb, NULL, 32, SBUF_AUTOEXTEND); 5455 for (i = 0; i < SGE_FLBUF_SIZES; i++, hwb++) { 5456 if (hwb->zidx >= 0 && swz[hwb->zidx].size <= largest_rx_cluster) 5457 c = '*'; 5458 else 5459 c = '\0'; 5460 5461 sbuf_printf(&sb, "%u%c ", hwb->size, c); 5462 } 5463 sbuf_trim(&sb); 5464 sbuf_finish(&sb); 5465 rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req); 5466 sbuf_delete(&sb); 5467 return (rc); 5468 } 5469 5470 #ifdef RATELIMIT 5471 /* 5472 * len16 for a txpkt WR with a GL. Includes the firmware work request header. 5473 */ 5474 static inline u_int 5475 txpkt_eo_len16(u_int nsegs, u_int immhdrs, u_int tso) 5476 { 5477 u_int n; 5478 5479 MPASS(immhdrs > 0); 5480 5481 n = roundup2(sizeof(struct fw_eth_tx_eo_wr) + 5482 sizeof(struct cpl_tx_pkt_core) + immhdrs, 16); 5483 if (__predict_false(nsegs == 0)) 5484 goto done; 5485 5486 nsegs--; /* first segment is part of ulptx_sgl */ 5487 n += sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 5488 if (tso) 5489 n += sizeof(struct cpl_tx_pkt_lso_core); 5490 5491 done: 5492 return (howmany(n, 16)); 5493 } 5494 5495 #define ETID_FLOWC_NPARAMS 6 5496 #define ETID_FLOWC_LEN (roundup2((sizeof(struct fw_flowc_wr) + \ 5497 ETID_FLOWC_NPARAMS * sizeof(struct fw_flowc_mnemval)), 16)) 5498 #define ETID_FLOWC_LEN16 (howmany(ETID_FLOWC_LEN, 16)) 5499 5500 static int 5501 send_etid_flowc_wr(struct cxgbe_snd_tag *cst, struct port_info *pi, 5502 struct vi_info *vi) 5503 { 5504 struct wrq_cookie cookie; 5505 u_int pfvf = G_FW_VIID_PFN(vi->viid) << S_FW_VIID_PFN; 5506 struct fw_flowc_wr *flowc; 5507 5508 mtx_assert(&cst->lock, MA_OWNED); 5509 MPASS((cst->flags & (EO_FLOWC_PENDING | EO_FLOWC_RPL_PENDING)) == 5510 EO_FLOWC_PENDING); 5511 5512 flowc = start_wrq_wr(cst->eo_txq, ETID_FLOWC_LEN16, &cookie); 5513 if (__predict_false(flowc == NULL)) 5514 return (ENOMEM); 5515 5516 bzero(flowc, ETID_FLOWC_LEN); 5517 flowc->op_to_nparams = htobe32(V_FW_WR_OP(FW_FLOWC_WR) | 5518 V_FW_FLOWC_WR_NPARAMS(ETID_FLOWC_NPARAMS) | V_FW_WR_COMPL(0)); 5519 flowc->flowid_len16 = htonl(V_FW_WR_LEN16(ETID_FLOWC_LEN16) | 5520 V_FW_WR_FLOWID(cst->etid)); 5521 flowc->mnemval[0].mnemonic = FW_FLOWC_MNEM_PFNVFN; 5522 flowc->mnemval[0].val = htobe32(pfvf); 5523 flowc->mnemval[1].mnemonic = FW_FLOWC_MNEM_CH; 5524 flowc->mnemval[1].val = htobe32(pi->tx_chan); 5525 flowc->mnemval[2].mnemonic = FW_FLOWC_MNEM_PORT; 5526 flowc->mnemval[2].val = htobe32(pi->tx_chan); 5527 flowc->mnemval[3].mnemonic = FW_FLOWC_MNEM_IQID; 5528 flowc->mnemval[3].val = htobe32(cst->iqid); 5529 flowc->mnemval[4].mnemonic = FW_FLOWC_MNEM_EOSTATE; 5530 flowc->mnemval[4].val = htobe32(FW_FLOWC_MNEM_EOSTATE_ESTABLISHED); 5531 flowc->mnemval[5].mnemonic = FW_FLOWC_MNEM_SCHEDCLASS; 5532 flowc->mnemval[5].val = htobe32(cst->schedcl); 5533 5534 commit_wrq_wr(cst->eo_txq, flowc, &cookie); 5535 5536 cst->flags &= ~EO_FLOWC_PENDING; 5537 cst->flags |= EO_FLOWC_RPL_PENDING; 5538 MPASS(cst->tx_credits >= ETID_FLOWC_LEN16); /* flowc is first WR. */ 5539 cst->tx_credits -= ETID_FLOWC_LEN16; 5540 5541 return (0); 5542 } 5543 5544 #define ETID_FLUSH_LEN16 (howmany(sizeof (struct fw_flowc_wr), 16)) 5545 5546 void 5547 send_etid_flush_wr(struct cxgbe_snd_tag *cst) 5548 { 5549 struct fw_flowc_wr *flowc; 5550 struct wrq_cookie cookie; 5551 5552 mtx_assert(&cst->lock, MA_OWNED); 5553 5554 flowc = start_wrq_wr(cst->eo_txq, ETID_FLUSH_LEN16, &cookie); 5555 if (__predict_false(flowc == NULL)) 5556 CXGBE_UNIMPLEMENTED(__func__); 5557 5558 bzero(flowc, ETID_FLUSH_LEN16 * 16); 5559 flowc->op_to_nparams = htobe32(V_FW_WR_OP(FW_FLOWC_WR) | 5560 V_FW_FLOWC_WR_NPARAMS(0) | F_FW_WR_COMPL); 5561 flowc->flowid_len16 = htobe32(V_FW_WR_LEN16(ETID_FLUSH_LEN16) | 5562 V_FW_WR_FLOWID(cst->etid)); 5563 5564 commit_wrq_wr(cst->eo_txq, flowc, &cookie); 5565 5566 cst->flags |= EO_FLUSH_RPL_PENDING; 5567 MPASS(cst->tx_credits >= ETID_FLUSH_LEN16); 5568 cst->tx_credits -= ETID_FLUSH_LEN16; 5569 cst->ncompl++; 5570 } 5571 5572 static void 5573 write_ethofld_wr(struct cxgbe_snd_tag *cst, struct fw_eth_tx_eo_wr *wr, 5574 struct mbuf *m0, int compl) 5575 { 5576 struct cpl_tx_pkt_core *cpl; 5577 uint64_t ctrl1; 5578 uint32_t ctrl; /* used in many unrelated places */ 5579 int len16, pktlen, nsegs, immhdrs; 5580 caddr_t dst; 5581 uintptr_t p; 5582 struct ulptx_sgl *usgl; 5583 struct sglist sg; 5584 struct sglist_seg segs[38]; /* XXX: find real limit. XXX: get off the stack */ 5585 5586 mtx_assert(&cst->lock, MA_OWNED); 5587 M_ASSERTPKTHDR(m0); 5588 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 5589 m0->m_pkthdr.l4hlen > 0, 5590 ("%s: ethofld mbuf %p is missing header lengths", __func__, m0)); 5591 5592 if (needs_udp_csum(m0)) { 5593 CXGBE_UNIMPLEMENTED("UDP ethofld"); 5594 } 5595 5596 len16 = mbuf_eo_len16(m0); 5597 nsegs = mbuf_eo_nsegs(m0); 5598 pktlen = m0->m_pkthdr.len; 5599 ctrl = sizeof(struct cpl_tx_pkt_core); 5600 if (needs_tso(m0)) 5601 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 5602 immhdrs = m0->m_pkthdr.l2hlen + m0->m_pkthdr.l3hlen + m0->m_pkthdr.l4hlen; 5603 ctrl += immhdrs; 5604 5605 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_EO_WR) | 5606 V_FW_ETH_TX_EO_WR_IMMDLEN(ctrl) | V_FW_WR_COMPL(!!compl)); 5607 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(len16) | 5608 V_FW_WR_FLOWID(cst->etid)); 5609 wr->r3 = 0; 5610 wr->u.tcpseg.type = FW_ETH_TX_EO_TYPE_TCPSEG; 5611 wr->u.tcpseg.ethlen = m0->m_pkthdr.l2hlen; 5612 wr->u.tcpseg.iplen = htobe16(m0->m_pkthdr.l3hlen); 5613 wr->u.tcpseg.tcplen = m0->m_pkthdr.l4hlen; 5614 wr->u.tcpseg.tsclk_tsoff = mbuf_eo_tsclk_tsoff(m0); 5615 wr->u.tcpseg.r4 = 0; 5616 wr->u.tcpseg.r5 = 0; 5617 wr->u.tcpseg.plen = htobe32(pktlen - immhdrs); 5618 5619 if (needs_tso(m0)) { 5620 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1); 5621 5622 wr->u.tcpseg.mss = htobe16(m0->m_pkthdr.tso_segsz); 5623 5624 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE | 5625 F_LSO_LAST_SLICE | V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) 5626 | V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2); 5627 if (m0->m_pkthdr.l2hlen == sizeof(struct ether_vlan_header)) 5628 ctrl |= V_LSO_ETHHDR_LEN(1); 5629 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 5630 ctrl |= F_LSO_IPV6; 5631 lso->lso_ctrl = htobe32(ctrl); 5632 lso->ipid_ofst = htobe16(0); 5633 lso->mss = htobe16(m0->m_pkthdr.tso_segsz); 5634 lso->seqno_offset = htobe32(0); 5635 lso->len = htobe32(pktlen); 5636 5637 cpl = (void *)(lso + 1); 5638 } else { 5639 wr->u.tcpseg.mss = htobe16(0xffff); 5640 cpl = (void *)(wr + 1); 5641 } 5642 5643 /* Checksum offload must be requested for ethofld. */ 5644 ctrl1 = 0; 5645 MPASS(needs_l4_csum(m0)); 5646 5647 /* VLAN tag insertion */ 5648 if (needs_vlan_insertion(m0)) { 5649 ctrl1 |= F_TXPKT_VLAN_VLD | 5650 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 5651 } 5652 5653 /* CPL header */ 5654 cpl->ctrl0 = cst->ctrl0; 5655 cpl->pack = 0; 5656 cpl->len = htobe16(pktlen); 5657 cpl->ctrl1 = htobe64(ctrl1); 5658 5659 /* Copy Ethernet, IP & TCP hdrs as immediate data */ 5660 p = (uintptr_t)(cpl + 1); 5661 m_copydata(m0, 0, immhdrs, (void *)p); 5662 5663 /* SGL */ 5664 dst = (void *)(cpl + 1); 5665 if (nsegs > 0) { 5666 int i, pad; 5667 5668 /* zero-pad upto next 16Byte boundary, if not 16Byte aligned */ 5669 p += immhdrs; 5670 pad = 16 - (immhdrs & 0xf); 5671 bzero((void *)p, pad); 5672 5673 usgl = (void *)(p + pad); 5674 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 5675 V_ULPTX_NSGE(nsegs)); 5676 5677 sglist_init(&sg, nitems(segs), segs); 5678 for (; m0 != NULL; m0 = m0->m_next) { 5679 if (__predict_false(m0->m_len == 0)) 5680 continue; 5681 if (immhdrs >= m0->m_len) { 5682 immhdrs -= m0->m_len; 5683 continue; 5684 } 5685 5686 sglist_append(&sg, mtod(m0, char *) + immhdrs, 5687 m0->m_len - immhdrs); 5688 immhdrs = 0; 5689 } 5690 MPASS(sg.sg_nseg == nsegs); 5691 5692 /* 5693 * Zero pad last 8B in case the WR doesn't end on a 16B 5694 * boundary. 5695 */ 5696 *(uint64_t *)((char *)wr + len16 * 16 - 8) = 0; 5697 5698 usgl->len0 = htobe32(segs[0].ss_len); 5699 usgl->addr0 = htobe64(segs[0].ss_paddr); 5700 for (i = 0; i < nsegs - 1; i++) { 5701 usgl->sge[i / 2].len[i & 1] = htobe32(segs[i + 1].ss_len); 5702 usgl->sge[i / 2].addr[i & 1] = htobe64(segs[i + 1].ss_paddr); 5703 } 5704 if (i & 1) 5705 usgl->sge[i / 2].len[1] = htobe32(0); 5706 } 5707 5708 } 5709 5710 static void 5711 ethofld_tx(struct cxgbe_snd_tag *cst) 5712 { 5713 struct mbuf *m; 5714 struct wrq_cookie cookie; 5715 int next_credits, compl; 5716 struct fw_eth_tx_eo_wr *wr; 5717 5718 mtx_assert(&cst->lock, MA_OWNED); 5719 5720 while ((m = mbufq_first(&cst->pending_tx)) != NULL) { 5721 M_ASSERTPKTHDR(m); 5722 5723 /* How many len16 credits do we need to send this mbuf. */ 5724 next_credits = mbuf_eo_len16(m); 5725 MPASS(next_credits > 0); 5726 if (next_credits > cst->tx_credits) { 5727 /* 5728 * Tx will make progress eventually because there is at 5729 * least one outstanding fw4_ack that will return 5730 * credits and kick the tx. 5731 */ 5732 MPASS(cst->ncompl > 0); 5733 return; 5734 } 5735 wr = start_wrq_wr(cst->eo_txq, next_credits, &cookie); 5736 if (__predict_false(wr == NULL)) { 5737 /* XXX: wishful thinking, not a real assertion. */ 5738 MPASS(cst->ncompl > 0); 5739 return; 5740 } 5741 cst->tx_credits -= next_credits; 5742 cst->tx_nocompl += next_credits; 5743 compl = cst->ncompl == 0 || cst->tx_nocompl >= cst->tx_total / 2; 5744 ETHER_BPF_MTAP(cst->com.ifp, m); 5745 write_ethofld_wr(cst, wr, m, compl); 5746 commit_wrq_wr(cst->eo_txq, wr, &cookie); 5747 if (compl) { 5748 cst->ncompl++; 5749 cst->tx_nocompl = 0; 5750 } 5751 (void) mbufq_dequeue(&cst->pending_tx); 5752 mbufq_enqueue(&cst->pending_fwack, m); 5753 } 5754 } 5755 5756 int 5757 ethofld_transmit(struct ifnet *ifp, struct mbuf *m0) 5758 { 5759 struct cxgbe_snd_tag *cst; 5760 int rc; 5761 5762 MPASS(m0->m_nextpkt == NULL); 5763 MPASS(m0->m_pkthdr.snd_tag != NULL); 5764 cst = mst_to_cst(m0->m_pkthdr.snd_tag); 5765 5766 mtx_lock(&cst->lock); 5767 MPASS(cst->flags & EO_SND_TAG_REF); 5768 5769 if (__predict_false(cst->flags & EO_FLOWC_PENDING)) { 5770 struct vi_info *vi = ifp->if_softc; 5771 struct port_info *pi = vi->pi; 5772 struct adapter *sc = pi->adapter; 5773 const uint32_t rss_mask = vi->rss_size - 1; 5774 uint32_t rss_hash; 5775 5776 cst->eo_txq = &sc->sge.ofld_txq[vi->first_ofld_txq]; 5777 if (M_HASHTYPE_ISHASH(m0)) 5778 rss_hash = m0->m_pkthdr.flowid; 5779 else 5780 rss_hash = arc4random(); 5781 /* We assume RSS hashing */ 5782 cst->iqid = vi->rss[rss_hash & rss_mask]; 5783 cst->eo_txq += rss_hash % vi->nofldtxq; 5784 rc = send_etid_flowc_wr(cst, pi, vi); 5785 if (rc != 0) 5786 goto done; 5787 } 5788 5789 if (__predict_false(cst->plen + m0->m_pkthdr.len > eo_max_backlog)) { 5790 rc = ENOBUFS; 5791 goto done; 5792 } 5793 5794 mbufq_enqueue(&cst->pending_tx, m0); 5795 cst->plen += m0->m_pkthdr.len; 5796 5797 ethofld_tx(cst); 5798 rc = 0; 5799 done: 5800 mtx_unlock(&cst->lock); 5801 if (__predict_false(rc != 0)) 5802 m_freem(m0); 5803 return (rc); 5804 } 5805 5806 static int 5807 ethofld_fw4_ack(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0) 5808 { 5809 struct adapter *sc = iq->adapter; 5810 const struct cpl_fw4_ack *cpl = (const void *)(rss + 1); 5811 struct mbuf *m; 5812 u_int etid = G_CPL_FW4_ACK_FLOWID(be32toh(OPCODE_TID(cpl))); 5813 struct cxgbe_snd_tag *cst; 5814 uint8_t credits = cpl->credits; 5815 5816 cst = lookup_etid(sc, etid); 5817 mtx_lock(&cst->lock); 5818 if (__predict_false(cst->flags & EO_FLOWC_RPL_PENDING)) { 5819 MPASS(credits >= ETID_FLOWC_LEN16); 5820 credits -= ETID_FLOWC_LEN16; 5821 cst->flags &= ~EO_FLOWC_RPL_PENDING; 5822 } 5823 5824 KASSERT(cst->ncompl > 0, 5825 ("%s: etid %u (%p) wasn't expecting completion.", 5826 __func__, etid, cst)); 5827 cst->ncompl--; 5828 5829 while (credits > 0) { 5830 m = mbufq_dequeue(&cst->pending_fwack); 5831 if (__predict_false(m == NULL)) { 5832 /* 5833 * The remaining credits are for the final flush that 5834 * was issued when the tag was freed by the kernel. 5835 */ 5836 MPASS((cst->flags & 5837 (EO_FLUSH_RPL_PENDING | EO_SND_TAG_REF)) == 5838 EO_FLUSH_RPL_PENDING); 5839 MPASS(credits == ETID_FLUSH_LEN16); 5840 MPASS(cst->tx_credits + cpl->credits == cst->tx_total); 5841 MPASS(cst->ncompl == 0); 5842 5843 cst->flags &= ~EO_FLUSH_RPL_PENDING; 5844 cst->tx_credits += cpl->credits; 5845 freetag: 5846 cxgbe_snd_tag_free_locked(cst); 5847 return (0); /* cst is gone. */ 5848 } 5849 KASSERT(m != NULL, 5850 ("%s: too many credits (%u, %u)", __func__, cpl->credits, 5851 credits)); 5852 KASSERT(credits >= mbuf_eo_len16(m), 5853 ("%s: too few credits (%u, %u, %u)", __func__, 5854 cpl->credits, credits, mbuf_eo_len16(m))); 5855 credits -= mbuf_eo_len16(m); 5856 cst->plen -= m->m_pkthdr.len; 5857 m_freem(m); 5858 } 5859 5860 cst->tx_credits += cpl->credits; 5861 MPASS(cst->tx_credits <= cst->tx_total); 5862 5863 m = mbufq_first(&cst->pending_tx); 5864 if (m != NULL && cst->tx_credits >= mbuf_eo_len16(m)) 5865 ethofld_tx(cst); 5866 5867 if (__predict_false((cst->flags & EO_SND_TAG_REF) == 0) && 5868 cst->ncompl == 0) { 5869 if (cst->tx_credits == cst->tx_total) 5870 goto freetag; 5871 else { 5872 MPASS((cst->flags & EO_FLUSH_RPL_PENDING) == 0); 5873 send_etid_flush_wr(cst); 5874 } 5875 } 5876 5877 mtx_unlock(&cst->lock); 5878 5879 return (0); 5880 } 5881 #endif 5882