1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 Chelsio Communications, Inc. 5 * All rights reserved. 6 * Written by: Navdeep Parhar <np@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include "opt_inet.h" 34 #include "opt_inet6.h" 35 #include "opt_kern_tls.h" 36 #include "opt_ratelimit.h" 37 38 #include <sys/types.h> 39 #include <sys/eventhandler.h> 40 #include <sys/mbuf.h> 41 #include <sys/socket.h> 42 #include <sys/kernel.h> 43 #include <sys/ktls.h> 44 #include <sys/malloc.h> 45 #include <sys/queue.h> 46 #include <sys/sbuf.h> 47 #include <sys/taskqueue.h> 48 #include <sys/time.h> 49 #include <sys/sglist.h> 50 #include <sys/sysctl.h> 51 #include <sys/smp.h> 52 #include <sys/socketvar.h> 53 #include <sys/counter.h> 54 #include <net/bpf.h> 55 #include <net/ethernet.h> 56 #include <net/if.h> 57 #include <net/if_vlan_var.h> 58 #include <net/if_vxlan.h> 59 #include <netinet/in.h> 60 #include <netinet/ip.h> 61 #include <netinet/ip6.h> 62 #include <netinet/tcp.h> 63 #include <netinet/udp.h> 64 #include <machine/in_cksum.h> 65 #include <machine/md_var.h> 66 #include <vm/vm.h> 67 #include <vm/pmap.h> 68 #ifdef DEV_NETMAP 69 #include <machine/bus.h> 70 #include <sys/selinfo.h> 71 #include <net/if_var.h> 72 #include <net/netmap.h> 73 #include <dev/netmap/netmap_kern.h> 74 #endif 75 76 #include "common/common.h" 77 #include "common/t4_regs.h" 78 #include "common/t4_regs_values.h" 79 #include "common/t4_msg.h" 80 #include "t4_l2t.h" 81 #include "t4_mp_ring.h" 82 83 #ifdef T4_PKT_TIMESTAMP 84 #define RX_COPY_THRESHOLD (MINCLSIZE - 8) 85 #else 86 #define RX_COPY_THRESHOLD MINCLSIZE 87 #endif 88 89 /* Internal mbuf flags stored in PH_loc.eight[1]. */ 90 #define MC_NOMAP 0x01 91 #define MC_RAW_WR 0x02 92 #define MC_TLS 0x04 93 94 /* 95 * Ethernet frames are DMA'd at this byte offset into the freelist buffer. 96 * 0-7 are valid values. 97 */ 98 static int fl_pktshift = 0; 99 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pktshift, CTLFLAG_RDTUN, &fl_pktshift, 0, 100 "payload DMA offset in rx buffer (bytes)"); 101 102 /* 103 * Pad ethernet payload up to this boundary. 104 * -1: driver should figure out a good value. 105 * 0: disable padding. 106 * Any power of 2 from 32 to 4096 (both inclusive) is also a valid value. 107 */ 108 int fl_pad = -1; 109 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pad, CTLFLAG_RDTUN, &fl_pad, 0, 110 "payload pad boundary (bytes)"); 111 112 /* 113 * Status page length. 114 * -1: driver should figure out a good value. 115 * 64 or 128 are the only other valid values. 116 */ 117 static int spg_len = -1; 118 SYSCTL_INT(_hw_cxgbe, OID_AUTO, spg_len, CTLFLAG_RDTUN, &spg_len, 0, 119 "status page size (bytes)"); 120 121 /* 122 * Congestion drops. 123 * -1: no congestion feedback (not recommended). 124 * 0: backpressure the channel instead of dropping packets right away. 125 * 1: no backpressure, drop packets for the congested queue immediately. 126 */ 127 static int cong_drop = 0; 128 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cong_drop, CTLFLAG_RDTUN, &cong_drop, 0, 129 "Congestion control for RX queues (0 = backpressure, 1 = drop"); 130 131 /* 132 * Deliver multiple frames in the same free list buffer if they fit. 133 * -1: let the driver decide whether to enable buffer packing or not. 134 * 0: disable buffer packing. 135 * 1: enable buffer packing. 136 */ 137 static int buffer_packing = -1; 138 SYSCTL_INT(_hw_cxgbe, OID_AUTO, buffer_packing, CTLFLAG_RDTUN, &buffer_packing, 139 0, "Enable buffer packing"); 140 141 /* 142 * Start next frame in a packed buffer at this boundary. 143 * -1: driver should figure out a good value. 144 * T4: driver will ignore this and use the same value as fl_pad above. 145 * T5: 16, or a power of 2 from 64 to 4096 (both inclusive) is a valid value. 146 */ 147 static int fl_pack = -1; 148 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pack, CTLFLAG_RDTUN, &fl_pack, 0, 149 "payload pack boundary (bytes)"); 150 151 /* 152 * Largest rx cluster size that the driver is allowed to allocate. 153 */ 154 static int largest_rx_cluster = MJUM16BYTES; 155 SYSCTL_INT(_hw_cxgbe, OID_AUTO, largest_rx_cluster, CTLFLAG_RDTUN, 156 &largest_rx_cluster, 0, "Largest rx cluster (bytes)"); 157 158 /* 159 * Size of cluster allocation that's most likely to succeed. The driver will 160 * fall back to this size if it fails to allocate clusters larger than this. 161 */ 162 static int safest_rx_cluster = PAGE_SIZE; 163 SYSCTL_INT(_hw_cxgbe, OID_AUTO, safest_rx_cluster, CTLFLAG_RDTUN, 164 &safest_rx_cluster, 0, "Safe rx cluster (bytes)"); 165 166 #ifdef RATELIMIT 167 /* 168 * Knob to control TCP timestamp rewriting, and the granularity of the tick used 169 * for rewriting. -1 and 0-3 are all valid values. 170 * -1: hardware should leave the TCP timestamps alone. 171 * 0: 1ms 172 * 1: 100us 173 * 2: 10us 174 * 3: 1us 175 */ 176 static int tsclk = -1; 177 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tsclk, CTLFLAG_RDTUN, &tsclk, 0, 178 "Control TCP timestamp rewriting when using pacing"); 179 180 static int eo_max_backlog = 1024 * 1024; 181 SYSCTL_INT(_hw_cxgbe, OID_AUTO, eo_max_backlog, CTLFLAG_RDTUN, &eo_max_backlog, 182 0, "Maximum backlog of ratelimited data per flow"); 183 #endif 184 185 /* 186 * The interrupt holdoff timers are multiplied by this value on T6+. 187 * 1 and 3-17 (both inclusive) are legal values. 188 */ 189 static int tscale = 1; 190 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tscale, CTLFLAG_RDTUN, &tscale, 0, 191 "Interrupt holdoff timer scale on T6+"); 192 193 /* 194 * Number of LRO entries in the lro_ctrl structure per rx queue. 195 */ 196 static int lro_entries = TCP_LRO_ENTRIES; 197 SYSCTL_INT(_hw_cxgbe, OID_AUTO, lro_entries, CTLFLAG_RDTUN, &lro_entries, 0, 198 "Number of LRO entries per RX queue"); 199 200 /* 201 * This enables presorting of frames before they're fed into tcp_lro_rx. 202 */ 203 static int lro_mbufs = 0; 204 SYSCTL_INT(_hw_cxgbe, OID_AUTO, lro_mbufs, CTLFLAG_RDTUN, &lro_mbufs, 0, 205 "Enable presorting of LRO frames"); 206 207 static counter_u64_t pullups; 208 SYSCTL_COUNTER_U64(_hw_cxgbe, OID_AUTO, pullups, CTLFLAG_RD, &pullups, 209 "Number of mbuf pullups performed"); 210 211 static counter_u64_t defrags; 212 SYSCTL_COUNTER_U64(_hw_cxgbe, OID_AUTO, defrags, CTLFLAG_RD, &defrags, 213 "Number of mbuf defrags performed"); 214 215 static int t4_tx_coalesce = 1; 216 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tx_coalesce, CTLFLAG_RWTUN, &t4_tx_coalesce, 0, 217 "tx coalescing allowed"); 218 219 /* 220 * The driver will make aggressive attempts at tx coalescing if it sees these 221 * many packets eligible for coalescing in quick succession, with no more than 222 * the specified gap in between the eth_tx calls that delivered the packets. 223 */ 224 static int t4_tx_coalesce_pkts = 32; 225 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tx_coalesce_pkts, CTLFLAG_RWTUN, 226 &t4_tx_coalesce_pkts, 0, 227 "# of consecutive packets (1 - 255) that will trigger tx coalescing"); 228 static int t4_tx_coalesce_gap = 5; 229 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tx_coalesce_gap, CTLFLAG_RWTUN, 230 &t4_tx_coalesce_gap, 0, "tx gap (in microseconds)"); 231 232 static int service_iq(struct sge_iq *, int); 233 static int service_iq_fl(struct sge_iq *, int); 234 static struct mbuf *get_fl_payload(struct adapter *, struct sge_fl *, uint32_t); 235 static int eth_rx(struct adapter *, struct sge_rxq *, const struct iq_desc *, 236 u_int); 237 static inline void init_iq(struct sge_iq *, struct adapter *, int, int, int); 238 static inline void init_fl(struct adapter *, struct sge_fl *, int, int, char *); 239 static inline void init_eq(struct adapter *, struct sge_eq *, int, int, uint8_t, 240 uint16_t, char *); 241 static int alloc_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *, 242 int, int); 243 static int free_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *); 244 static void add_iq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *, 245 struct sge_iq *); 246 static void add_fl_sysctls(struct adapter *, struct sysctl_ctx_list *, 247 struct sysctl_oid *, struct sge_fl *); 248 static int alloc_fwq(struct adapter *); 249 static int free_fwq(struct adapter *); 250 static int alloc_ctrlq(struct adapter *, struct sge_wrq *, int, 251 struct sysctl_oid *); 252 static int alloc_rxq(struct vi_info *, struct sge_rxq *, int, int, 253 struct sysctl_oid *); 254 static int free_rxq(struct vi_info *, struct sge_rxq *); 255 #ifdef TCP_OFFLOAD 256 static int alloc_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *, int, int, 257 struct sysctl_oid *); 258 static int free_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *); 259 #endif 260 static int ctrl_eq_alloc(struct adapter *, struct sge_eq *); 261 static int eth_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *); 262 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 263 static int ofld_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *); 264 #endif 265 static int alloc_eq(struct adapter *, struct vi_info *, struct sge_eq *); 266 static int free_eq(struct adapter *, struct sge_eq *); 267 static int alloc_wrq(struct adapter *, struct vi_info *, struct sge_wrq *, 268 struct sysctl_oid *); 269 static int free_wrq(struct adapter *, struct sge_wrq *); 270 static int alloc_txq(struct vi_info *, struct sge_txq *, int, 271 struct sysctl_oid *); 272 static int free_txq(struct vi_info *, struct sge_txq *); 273 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 274 static int alloc_ofld_txq(struct vi_info *, struct sge_ofld_txq *, int, 275 struct sysctl_oid *); 276 static int free_ofld_txq(struct vi_info *, struct sge_ofld_txq *); 277 #endif 278 static void oneseg_dma_callback(void *, bus_dma_segment_t *, int, int); 279 static inline void ring_fl_db(struct adapter *, struct sge_fl *); 280 static int refill_fl(struct adapter *, struct sge_fl *, int); 281 static void refill_sfl(void *); 282 static int alloc_fl_sdesc(struct sge_fl *); 283 static void free_fl_sdesc(struct adapter *, struct sge_fl *); 284 static int find_refill_source(struct adapter *, int, bool); 285 static void add_fl_to_sfl(struct adapter *, struct sge_fl *); 286 287 static inline void get_pkt_gl(struct mbuf *, struct sglist *); 288 static inline u_int txpkt_len16(u_int, const u_int); 289 static inline u_int txpkt_vm_len16(u_int, const u_int); 290 static inline void calculate_mbuf_len16(struct mbuf *, bool); 291 static inline u_int txpkts0_len16(u_int); 292 static inline u_int txpkts1_len16(void); 293 static u_int write_raw_wr(struct sge_txq *, void *, struct mbuf *, u_int); 294 static u_int write_txpkt_wr(struct adapter *, struct sge_txq *, struct mbuf *, 295 u_int); 296 static u_int write_txpkt_vm_wr(struct adapter *, struct sge_txq *, 297 struct mbuf *); 298 static int add_to_txpkts_vf(struct adapter *, struct sge_txq *, struct mbuf *, 299 int, bool *); 300 static int add_to_txpkts_pf(struct adapter *, struct sge_txq *, struct mbuf *, 301 int, bool *); 302 static u_int write_txpkts_wr(struct adapter *, struct sge_txq *); 303 static u_int write_txpkts_vm_wr(struct adapter *, struct sge_txq *); 304 static void write_gl_to_txd(struct sge_txq *, struct mbuf *, caddr_t *, int); 305 static inline void copy_to_txd(struct sge_eq *, caddr_t, caddr_t *, int); 306 static inline void ring_eq_db(struct adapter *, struct sge_eq *, u_int); 307 static inline uint16_t read_hw_cidx(struct sge_eq *); 308 static inline u_int reclaimable_tx_desc(struct sge_eq *); 309 static inline u_int total_available_tx_desc(struct sge_eq *); 310 static u_int reclaim_tx_descs(struct sge_txq *, u_int); 311 static void tx_reclaim(void *, int); 312 static __be64 get_flit(struct sglist_seg *, int, int); 313 static int handle_sge_egr_update(struct sge_iq *, const struct rss_header *, 314 struct mbuf *); 315 static int handle_fw_msg(struct sge_iq *, const struct rss_header *, 316 struct mbuf *); 317 static int t4_handle_wrerr_rpl(struct adapter *, const __be64 *); 318 static void wrq_tx_drain(void *, int); 319 static void drain_wrq_wr_list(struct adapter *, struct sge_wrq *); 320 321 static int sysctl_bufsizes(SYSCTL_HANDLER_ARGS); 322 #ifdef RATELIMIT 323 static inline u_int txpkt_eo_len16(u_int, u_int, u_int); 324 static int ethofld_fw4_ack(struct sge_iq *, const struct rss_header *, 325 struct mbuf *); 326 #endif 327 328 static counter_u64_t extfree_refs; 329 static counter_u64_t extfree_rels; 330 331 an_handler_t t4_an_handler; 332 fw_msg_handler_t t4_fw_msg_handler[NUM_FW6_TYPES]; 333 cpl_handler_t t4_cpl_handler[NUM_CPL_CMDS]; 334 cpl_handler_t set_tcb_rpl_handlers[NUM_CPL_COOKIES]; 335 cpl_handler_t l2t_write_rpl_handlers[NUM_CPL_COOKIES]; 336 cpl_handler_t act_open_rpl_handlers[NUM_CPL_COOKIES]; 337 cpl_handler_t abort_rpl_rss_handlers[NUM_CPL_COOKIES]; 338 cpl_handler_t fw4_ack_handlers[NUM_CPL_COOKIES]; 339 340 void 341 t4_register_an_handler(an_handler_t h) 342 { 343 uintptr_t *loc; 344 345 MPASS(h == NULL || t4_an_handler == NULL); 346 347 loc = (uintptr_t *)&t4_an_handler; 348 atomic_store_rel_ptr(loc, (uintptr_t)h); 349 } 350 351 void 352 t4_register_fw_msg_handler(int type, fw_msg_handler_t h) 353 { 354 uintptr_t *loc; 355 356 MPASS(type < nitems(t4_fw_msg_handler)); 357 MPASS(h == NULL || t4_fw_msg_handler[type] == NULL); 358 /* 359 * These are dispatched by the handler for FW{4|6}_CPL_MSG using the CPL 360 * handler dispatch table. Reject any attempt to install a handler for 361 * this subtype. 362 */ 363 MPASS(type != FW_TYPE_RSSCPL); 364 MPASS(type != FW6_TYPE_RSSCPL); 365 366 loc = (uintptr_t *)&t4_fw_msg_handler[type]; 367 atomic_store_rel_ptr(loc, (uintptr_t)h); 368 } 369 370 void 371 t4_register_cpl_handler(int opcode, cpl_handler_t h) 372 { 373 uintptr_t *loc; 374 375 MPASS(opcode < nitems(t4_cpl_handler)); 376 MPASS(h == NULL || t4_cpl_handler[opcode] == NULL); 377 378 loc = (uintptr_t *)&t4_cpl_handler[opcode]; 379 atomic_store_rel_ptr(loc, (uintptr_t)h); 380 } 381 382 static int 383 set_tcb_rpl_handler(struct sge_iq *iq, const struct rss_header *rss, 384 struct mbuf *m) 385 { 386 const struct cpl_set_tcb_rpl *cpl = (const void *)(rss + 1); 387 u_int tid; 388 int cookie; 389 390 MPASS(m == NULL); 391 392 tid = GET_TID(cpl); 393 if (is_hpftid(iq->adapter, tid) || is_ftid(iq->adapter, tid)) { 394 /* 395 * The return code for filter-write is put in the CPL cookie so 396 * we have to rely on the hardware tid (is_ftid) to determine 397 * that this is a response to a filter. 398 */ 399 cookie = CPL_COOKIE_FILTER; 400 } else { 401 cookie = G_COOKIE(cpl->cookie); 402 } 403 MPASS(cookie > CPL_COOKIE_RESERVED); 404 MPASS(cookie < nitems(set_tcb_rpl_handlers)); 405 406 return (set_tcb_rpl_handlers[cookie](iq, rss, m)); 407 } 408 409 static int 410 l2t_write_rpl_handler(struct sge_iq *iq, const struct rss_header *rss, 411 struct mbuf *m) 412 { 413 const struct cpl_l2t_write_rpl *rpl = (const void *)(rss + 1); 414 unsigned int cookie; 415 416 MPASS(m == NULL); 417 418 cookie = GET_TID(rpl) & F_SYNC_WR ? CPL_COOKIE_TOM : CPL_COOKIE_FILTER; 419 return (l2t_write_rpl_handlers[cookie](iq, rss, m)); 420 } 421 422 static int 423 act_open_rpl_handler(struct sge_iq *iq, const struct rss_header *rss, 424 struct mbuf *m) 425 { 426 const struct cpl_act_open_rpl *cpl = (const void *)(rss + 1); 427 u_int cookie = G_TID_COOKIE(G_AOPEN_ATID(be32toh(cpl->atid_status))); 428 429 MPASS(m == NULL); 430 MPASS(cookie != CPL_COOKIE_RESERVED); 431 432 return (act_open_rpl_handlers[cookie](iq, rss, m)); 433 } 434 435 static int 436 abort_rpl_rss_handler(struct sge_iq *iq, const struct rss_header *rss, 437 struct mbuf *m) 438 { 439 struct adapter *sc = iq->adapter; 440 u_int cookie; 441 442 MPASS(m == NULL); 443 if (is_hashfilter(sc)) 444 cookie = CPL_COOKIE_HASHFILTER; 445 else 446 cookie = CPL_COOKIE_TOM; 447 448 return (abort_rpl_rss_handlers[cookie](iq, rss, m)); 449 } 450 451 static int 452 fw4_ack_handler(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 453 { 454 struct adapter *sc = iq->adapter; 455 const struct cpl_fw4_ack *cpl = (const void *)(rss + 1); 456 unsigned int tid = G_CPL_FW4_ACK_FLOWID(be32toh(OPCODE_TID(cpl))); 457 u_int cookie; 458 459 MPASS(m == NULL); 460 if (is_etid(sc, tid)) 461 cookie = CPL_COOKIE_ETHOFLD; 462 else 463 cookie = CPL_COOKIE_TOM; 464 465 return (fw4_ack_handlers[cookie](iq, rss, m)); 466 } 467 468 static void 469 t4_init_shared_cpl_handlers(void) 470 { 471 472 t4_register_cpl_handler(CPL_SET_TCB_RPL, set_tcb_rpl_handler); 473 t4_register_cpl_handler(CPL_L2T_WRITE_RPL, l2t_write_rpl_handler); 474 t4_register_cpl_handler(CPL_ACT_OPEN_RPL, act_open_rpl_handler); 475 t4_register_cpl_handler(CPL_ABORT_RPL_RSS, abort_rpl_rss_handler); 476 t4_register_cpl_handler(CPL_FW4_ACK, fw4_ack_handler); 477 } 478 479 void 480 t4_register_shared_cpl_handler(int opcode, cpl_handler_t h, int cookie) 481 { 482 uintptr_t *loc; 483 484 MPASS(opcode < nitems(t4_cpl_handler)); 485 MPASS(cookie > CPL_COOKIE_RESERVED); 486 MPASS(cookie < NUM_CPL_COOKIES); 487 MPASS(t4_cpl_handler[opcode] != NULL); 488 489 switch (opcode) { 490 case CPL_SET_TCB_RPL: 491 loc = (uintptr_t *)&set_tcb_rpl_handlers[cookie]; 492 break; 493 case CPL_L2T_WRITE_RPL: 494 loc = (uintptr_t *)&l2t_write_rpl_handlers[cookie]; 495 break; 496 case CPL_ACT_OPEN_RPL: 497 loc = (uintptr_t *)&act_open_rpl_handlers[cookie]; 498 break; 499 case CPL_ABORT_RPL_RSS: 500 loc = (uintptr_t *)&abort_rpl_rss_handlers[cookie]; 501 break; 502 case CPL_FW4_ACK: 503 loc = (uintptr_t *)&fw4_ack_handlers[cookie]; 504 break; 505 default: 506 MPASS(0); 507 return; 508 } 509 MPASS(h == NULL || *loc == (uintptr_t)NULL); 510 atomic_store_rel_ptr(loc, (uintptr_t)h); 511 } 512 513 /* 514 * Called on MOD_LOAD. Validates and calculates the SGE tunables. 515 */ 516 void 517 t4_sge_modload(void) 518 { 519 520 if (fl_pktshift < 0 || fl_pktshift > 7) { 521 printf("Invalid hw.cxgbe.fl_pktshift value (%d)," 522 " using 0 instead.\n", fl_pktshift); 523 fl_pktshift = 0; 524 } 525 526 if (spg_len != 64 && spg_len != 128) { 527 int len; 528 529 #if defined(__i386__) || defined(__amd64__) 530 len = cpu_clflush_line_size > 64 ? 128 : 64; 531 #else 532 len = 64; 533 #endif 534 if (spg_len != -1) { 535 printf("Invalid hw.cxgbe.spg_len value (%d)," 536 " using %d instead.\n", spg_len, len); 537 } 538 spg_len = len; 539 } 540 541 if (cong_drop < -1 || cong_drop > 1) { 542 printf("Invalid hw.cxgbe.cong_drop value (%d)," 543 " using 0 instead.\n", cong_drop); 544 cong_drop = 0; 545 } 546 547 if (tscale != 1 && (tscale < 3 || tscale > 17)) { 548 printf("Invalid hw.cxgbe.tscale value (%d)," 549 " using 1 instead.\n", tscale); 550 tscale = 1; 551 } 552 553 if (largest_rx_cluster != MCLBYTES && 554 #if MJUMPAGESIZE != MCLBYTES 555 largest_rx_cluster != MJUMPAGESIZE && 556 #endif 557 largest_rx_cluster != MJUM9BYTES && 558 largest_rx_cluster != MJUM16BYTES) { 559 printf("Invalid hw.cxgbe.largest_rx_cluster value (%d)," 560 " using %d instead.\n", largest_rx_cluster, MJUM16BYTES); 561 largest_rx_cluster = MJUM16BYTES; 562 } 563 564 if (safest_rx_cluster != MCLBYTES && 565 #if MJUMPAGESIZE != MCLBYTES 566 safest_rx_cluster != MJUMPAGESIZE && 567 #endif 568 safest_rx_cluster != MJUM9BYTES && 569 safest_rx_cluster != MJUM16BYTES) { 570 printf("Invalid hw.cxgbe.safest_rx_cluster value (%d)," 571 " using %d instead.\n", safest_rx_cluster, MJUMPAGESIZE); 572 safest_rx_cluster = MJUMPAGESIZE; 573 } 574 575 extfree_refs = counter_u64_alloc(M_WAITOK); 576 extfree_rels = counter_u64_alloc(M_WAITOK); 577 pullups = counter_u64_alloc(M_WAITOK); 578 defrags = counter_u64_alloc(M_WAITOK); 579 counter_u64_zero(extfree_refs); 580 counter_u64_zero(extfree_rels); 581 counter_u64_zero(pullups); 582 counter_u64_zero(defrags); 583 584 t4_init_shared_cpl_handlers(); 585 t4_register_cpl_handler(CPL_FW4_MSG, handle_fw_msg); 586 t4_register_cpl_handler(CPL_FW6_MSG, handle_fw_msg); 587 t4_register_cpl_handler(CPL_SGE_EGR_UPDATE, handle_sge_egr_update); 588 #ifdef RATELIMIT 589 t4_register_shared_cpl_handler(CPL_FW4_ACK, ethofld_fw4_ack, 590 CPL_COOKIE_ETHOFLD); 591 #endif 592 t4_register_fw_msg_handler(FW6_TYPE_CMD_RPL, t4_handle_fw_rpl); 593 t4_register_fw_msg_handler(FW6_TYPE_WRERR_RPL, t4_handle_wrerr_rpl); 594 } 595 596 void 597 t4_sge_modunload(void) 598 { 599 600 counter_u64_free(extfree_refs); 601 counter_u64_free(extfree_rels); 602 counter_u64_free(pullups); 603 counter_u64_free(defrags); 604 } 605 606 uint64_t 607 t4_sge_extfree_refs(void) 608 { 609 uint64_t refs, rels; 610 611 rels = counter_u64_fetch(extfree_rels); 612 refs = counter_u64_fetch(extfree_refs); 613 614 return (refs - rels); 615 } 616 617 /* max 4096 */ 618 #define MAX_PACK_BOUNDARY 512 619 620 static inline void 621 setup_pad_and_pack_boundaries(struct adapter *sc) 622 { 623 uint32_t v, m; 624 int pad, pack, pad_shift; 625 626 pad_shift = chip_id(sc) > CHELSIO_T5 ? X_T6_INGPADBOUNDARY_SHIFT : 627 X_INGPADBOUNDARY_SHIFT; 628 pad = fl_pad; 629 if (fl_pad < (1 << pad_shift) || 630 fl_pad > (1 << (pad_shift + M_INGPADBOUNDARY)) || 631 !powerof2(fl_pad)) { 632 /* 633 * If there is any chance that we might use buffer packing and 634 * the chip is a T4, then pick 64 as the pad/pack boundary. Set 635 * it to the minimum allowed in all other cases. 636 */ 637 pad = is_t4(sc) && buffer_packing ? 64 : 1 << pad_shift; 638 639 /* 640 * For fl_pad = 0 we'll still write a reasonable value to the 641 * register but all the freelists will opt out of padding. 642 * We'll complain here only if the user tried to set it to a 643 * value greater than 0 that was invalid. 644 */ 645 if (fl_pad > 0) { 646 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pad value" 647 " (%d), using %d instead.\n", fl_pad, pad); 648 } 649 } 650 m = V_INGPADBOUNDARY(M_INGPADBOUNDARY); 651 v = V_INGPADBOUNDARY(ilog2(pad) - pad_shift); 652 t4_set_reg_field(sc, A_SGE_CONTROL, m, v); 653 654 if (is_t4(sc)) { 655 if (fl_pack != -1 && fl_pack != pad) { 656 /* Complain but carry on. */ 657 device_printf(sc->dev, "hw.cxgbe.fl_pack (%d) ignored," 658 " using %d instead.\n", fl_pack, pad); 659 } 660 return; 661 } 662 663 pack = fl_pack; 664 if (fl_pack < 16 || fl_pack == 32 || fl_pack > 4096 || 665 !powerof2(fl_pack)) { 666 if (sc->params.pci.mps > MAX_PACK_BOUNDARY) 667 pack = MAX_PACK_BOUNDARY; 668 else 669 pack = max(sc->params.pci.mps, CACHE_LINE_SIZE); 670 MPASS(powerof2(pack)); 671 if (pack < 16) 672 pack = 16; 673 if (pack == 32) 674 pack = 64; 675 if (pack > 4096) 676 pack = 4096; 677 if (fl_pack != -1) { 678 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pack value" 679 " (%d), using %d instead.\n", fl_pack, pack); 680 } 681 } 682 m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY); 683 if (pack == 16) 684 v = V_INGPACKBOUNDARY(0); 685 else 686 v = V_INGPACKBOUNDARY(ilog2(pack) - 5); 687 688 MPASS(!is_t4(sc)); /* T4 doesn't have SGE_CONTROL2 */ 689 t4_set_reg_field(sc, A_SGE_CONTROL2, m, v); 690 } 691 692 /* 693 * adap->params.vpd.cclk must be set up before this is called. 694 */ 695 void 696 t4_tweak_chip_settings(struct adapter *sc) 697 { 698 int i, reg; 699 uint32_t v, m; 700 int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200}; 701 int timer_max = M_TIMERVALUE0 * 1000 / sc->params.vpd.cclk; 702 int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */ 703 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 704 static int sw_buf_sizes[] = { 705 MCLBYTES, 706 #if MJUMPAGESIZE != MCLBYTES 707 MJUMPAGESIZE, 708 #endif 709 MJUM9BYTES, 710 MJUM16BYTES 711 }; 712 713 KASSERT(sc->flags & MASTER_PF, 714 ("%s: trying to change chip settings when not master.", __func__)); 715 716 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE; 717 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE | 718 V_EGRSTATUSPAGESIZE(spg_len == 128); 719 t4_set_reg_field(sc, A_SGE_CONTROL, m, v); 720 721 setup_pad_and_pack_boundaries(sc); 722 723 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) | 724 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) | 725 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) | 726 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) | 727 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) | 728 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) | 729 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) | 730 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10); 731 t4_write_reg(sc, A_SGE_HOST_PAGE_SIZE, v); 732 733 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0, 4096); 734 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE1, 65536); 735 reg = A_SGE_FL_BUFFER_SIZE2; 736 for (i = 0; i < nitems(sw_buf_sizes); i++) { 737 MPASS(reg <= A_SGE_FL_BUFFER_SIZE15); 738 t4_write_reg(sc, reg, sw_buf_sizes[i]); 739 reg += 4; 740 MPASS(reg <= A_SGE_FL_BUFFER_SIZE15); 741 t4_write_reg(sc, reg, sw_buf_sizes[i] - CL_METADATA_SIZE); 742 reg += 4; 743 } 744 745 v = V_THRESHOLD_0(intr_pktcount[0]) | V_THRESHOLD_1(intr_pktcount[1]) | 746 V_THRESHOLD_2(intr_pktcount[2]) | V_THRESHOLD_3(intr_pktcount[3]); 747 t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD, v); 748 749 KASSERT(intr_timer[0] <= timer_max, 750 ("%s: not a single usable timer (%d, %d)", __func__, intr_timer[0], 751 timer_max)); 752 for (i = 1; i < nitems(intr_timer); i++) { 753 KASSERT(intr_timer[i] >= intr_timer[i - 1], 754 ("%s: timers not listed in increasing order (%d)", 755 __func__, i)); 756 757 while (intr_timer[i] > timer_max) { 758 if (i == nitems(intr_timer) - 1) { 759 intr_timer[i] = timer_max; 760 break; 761 } 762 intr_timer[i] += intr_timer[i - 1]; 763 intr_timer[i] /= 2; 764 } 765 } 766 767 v = V_TIMERVALUE0(us_to_core_ticks(sc, intr_timer[0])) | 768 V_TIMERVALUE1(us_to_core_ticks(sc, intr_timer[1])); 769 t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1, v); 770 v = V_TIMERVALUE2(us_to_core_ticks(sc, intr_timer[2])) | 771 V_TIMERVALUE3(us_to_core_ticks(sc, intr_timer[3])); 772 t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3, v); 773 v = V_TIMERVALUE4(us_to_core_ticks(sc, intr_timer[4])) | 774 V_TIMERVALUE5(us_to_core_ticks(sc, intr_timer[5])); 775 t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5, v); 776 777 if (chip_id(sc) >= CHELSIO_T6) { 778 m = V_TSCALE(M_TSCALE); 779 if (tscale == 1) 780 v = 0; 781 else 782 v = V_TSCALE(tscale - 2); 783 t4_set_reg_field(sc, A_SGE_ITP_CONTROL, m, v); 784 785 if (sc->debug_flags & DF_DISABLE_TCB_CACHE) { 786 m = V_RDTHRESHOLD(M_RDTHRESHOLD) | F_WRTHRTHRESHEN | 787 V_WRTHRTHRESH(M_WRTHRTHRESH); 788 t4_tp_pio_read(sc, &v, 1, A_TP_CMM_CONFIG, 1); 789 v &= ~m; 790 v |= V_RDTHRESHOLD(1) | F_WRTHRTHRESHEN | 791 V_WRTHRTHRESH(16); 792 t4_tp_pio_write(sc, &v, 1, A_TP_CMM_CONFIG, 1); 793 } 794 } 795 796 /* 4K, 16K, 64K, 256K DDP "page sizes" for TDDP */ 797 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 798 t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, v); 799 800 /* 801 * 4K, 8K, 16K, 64K DDP "page sizes" for iSCSI DDP. These have been 802 * chosen with MAXPHYS = 128K in mind. The largest DDP buffer that we 803 * may have to deal with is MAXPHYS + 1 page. 804 */ 805 v = V_HPZ0(0) | V_HPZ1(1) | V_HPZ2(2) | V_HPZ3(4); 806 t4_write_reg(sc, A_ULP_RX_ISCSI_PSZ, v); 807 808 /* We use multiple DDP page sizes both in plain-TOE and ISCSI modes. */ 809 m = v = F_TDDPTAGTCB | F_ISCSITAGTCB; 810 t4_set_reg_field(sc, A_ULP_RX_CTL, m, v); 811 812 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 813 F_RESETDDPOFFSET; 814 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 815 t4_set_reg_field(sc, A_TP_PARA_REG5, m, v); 816 } 817 818 /* 819 * SGE wants the buffer to be at least 64B and then a multiple of 16. Its 820 * address mut be 16B aligned. If padding is in use the buffer's start and end 821 * need to be aligned to the pad boundary as well. We'll just make sure that 822 * the size is a multiple of the pad boundary here, it is up to the buffer 823 * allocation code to make sure the start of the buffer is aligned. 824 */ 825 static inline int 826 hwsz_ok(struct adapter *sc, int hwsz) 827 { 828 int mask = fl_pad ? sc->params.sge.pad_boundary - 1 : 16 - 1; 829 830 return (hwsz >= 64 && (hwsz & mask) == 0); 831 } 832 833 /* 834 * Initialize the rx buffer sizes and figure out which zones the buffers will 835 * be allocated from. 836 */ 837 void 838 t4_init_rx_buf_info(struct adapter *sc) 839 { 840 struct sge *s = &sc->sge; 841 struct sge_params *sp = &sc->params.sge; 842 int i, j, n; 843 static int sw_buf_sizes[] = { /* Sorted by size */ 844 MCLBYTES, 845 #if MJUMPAGESIZE != MCLBYTES 846 MJUMPAGESIZE, 847 #endif 848 MJUM9BYTES, 849 MJUM16BYTES 850 }; 851 struct rx_buf_info *rxb; 852 853 s->safe_zidx = -1; 854 rxb = &s->rx_buf_info[0]; 855 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) { 856 rxb->size1 = sw_buf_sizes[i]; 857 rxb->zone = m_getzone(rxb->size1); 858 rxb->type = m_gettype(rxb->size1); 859 rxb->size2 = 0; 860 rxb->hwidx1 = -1; 861 rxb->hwidx2 = -1; 862 for (j = 0; j < SGE_FLBUF_SIZES; j++) { 863 int hwsize = sp->sge_fl_buffer_size[j]; 864 865 if (!hwsz_ok(sc, hwsize)) 866 continue; 867 868 /* hwidx for size1 */ 869 if (rxb->hwidx1 == -1 && rxb->size1 == hwsize) 870 rxb->hwidx1 = j; 871 872 /* hwidx for size2 (buffer packing) */ 873 if (rxb->size1 - CL_METADATA_SIZE < hwsize) 874 continue; 875 n = rxb->size1 - hwsize - CL_METADATA_SIZE; 876 if (n == 0) { 877 rxb->hwidx2 = j; 878 rxb->size2 = hwsize; 879 break; /* stop looking */ 880 } 881 if (rxb->hwidx2 != -1) { 882 if (n < sp->sge_fl_buffer_size[rxb->hwidx2] - 883 hwsize - CL_METADATA_SIZE) { 884 rxb->hwidx2 = j; 885 rxb->size2 = hwsize; 886 } 887 } else if (n <= 2 * CL_METADATA_SIZE) { 888 rxb->hwidx2 = j; 889 rxb->size2 = hwsize; 890 } 891 } 892 if (rxb->hwidx2 != -1) 893 sc->flags |= BUF_PACKING_OK; 894 if (s->safe_zidx == -1 && rxb->size1 == safest_rx_cluster) 895 s->safe_zidx = i; 896 } 897 } 898 899 /* 900 * Verify some basic SGE settings for the PF and VF driver, and other 901 * miscellaneous settings for the PF driver. 902 */ 903 int 904 t4_verify_chip_settings(struct adapter *sc) 905 { 906 struct sge_params *sp = &sc->params.sge; 907 uint32_t m, v, r; 908 int rc = 0; 909 const uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 910 911 m = F_RXPKTCPLMODE; 912 v = F_RXPKTCPLMODE; 913 r = sp->sge_control; 914 if ((r & m) != v) { 915 device_printf(sc->dev, "invalid SGE_CONTROL(0x%x)\n", r); 916 rc = EINVAL; 917 } 918 919 /* 920 * If this changes then every single use of PAGE_SHIFT in the driver 921 * needs to be carefully reviewed for PAGE_SHIFT vs sp->page_shift. 922 */ 923 if (sp->page_shift != PAGE_SHIFT) { 924 device_printf(sc->dev, "invalid SGE_HOST_PAGE_SIZE(0x%x)\n", r); 925 rc = EINVAL; 926 } 927 928 if (sc->flags & IS_VF) 929 return (0); 930 931 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 932 r = t4_read_reg(sc, A_ULP_RX_TDDP_PSZ); 933 if (r != v) { 934 device_printf(sc->dev, "invalid ULP_RX_TDDP_PSZ(0x%x)\n", r); 935 if (sc->vres.ddp.size != 0) 936 rc = EINVAL; 937 } 938 939 m = v = F_TDDPTAGTCB; 940 r = t4_read_reg(sc, A_ULP_RX_CTL); 941 if ((r & m) != v) { 942 device_printf(sc->dev, "invalid ULP_RX_CTL(0x%x)\n", r); 943 if (sc->vres.ddp.size != 0) 944 rc = EINVAL; 945 } 946 947 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 948 F_RESETDDPOFFSET; 949 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 950 r = t4_read_reg(sc, A_TP_PARA_REG5); 951 if ((r & m) != v) { 952 device_printf(sc->dev, "invalid TP_PARA_REG5(0x%x)\n", r); 953 if (sc->vres.ddp.size != 0) 954 rc = EINVAL; 955 } 956 957 return (rc); 958 } 959 960 int 961 t4_create_dma_tag(struct adapter *sc) 962 { 963 int rc; 964 965 rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0, 966 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE, 967 BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL, 968 NULL, &sc->dmat); 969 if (rc != 0) { 970 device_printf(sc->dev, 971 "failed to create main DMA tag: %d\n", rc); 972 } 973 974 return (rc); 975 } 976 977 void 978 t4_sge_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx, 979 struct sysctl_oid_list *children) 980 { 981 struct sge_params *sp = &sc->params.sge; 982 983 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "buffer_sizes", 984 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 985 sysctl_bufsizes, "A", "freelist buffer sizes"); 986 987 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pktshift", CTLFLAG_RD, 988 NULL, sp->fl_pktshift, "payload DMA offset in rx buffer (bytes)"); 989 990 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pad", CTLFLAG_RD, 991 NULL, sp->pad_boundary, "payload pad boundary (bytes)"); 992 993 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "spg_len", CTLFLAG_RD, 994 NULL, sp->spg_len, "status page size (bytes)"); 995 996 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_drop", CTLFLAG_RD, 997 NULL, cong_drop, "congestion drop setting"); 998 999 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pack", CTLFLAG_RD, 1000 NULL, sp->pack_boundary, "payload pack boundary (bytes)"); 1001 } 1002 1003 int 1004 t4_destroy_dma_tag(struct adapter *sc) 1005 { 1006 if (sc->dmat) 1007 bus_dma_tag_destroy(sc->dmat); 1008 1009 return (0); 1010 } 1011 1012 /* 1013 * Allocate and initialize the firmware event queue, control queues, and special 1014 * purpose rx queues owned by the adapter. 1015 * 1016 * Returns errno on failure. Resources allocated up to that point may still be 1017 * allocated. Caller is responsible for cleanup in case this function fails. 1018 */ 1019 int 1020 t4_setup_adapter_queues(struct adapter *sc) 1021 { 1022 struct sysctl_oid *oid; 1023 struct sysctl_oid_list *children; 1024 int rc, i; 1025 1026 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 1027 1028 sysctl_ctx_init(&sc->ctx); 1029 sc->flags |= ADAP_SYSCTL_CTX; 1030 1031 /* 1032 * Firmware event queue 1033 */ 1034 rc = alloc_fwq(sc); 1035 if (rc != 0) 1036 return (rc); 1037 1038 /* 1039 * That's all for the VF driver. 1040 */ 1041 if (sc->flags & IS_VF) 1042 return (rc); 1043 1044 oid = device_get_sysctl_tree(sc->dev); 1045 children = SYSCTL_CHILDREN(oid); 1046 1047 /* 1048 * XXX: General purpose rx queues, one per port. 1049 */ 1050 1051 /* 1052 * Control queues, one per port. 1053 */ 1054 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "ctrlq", 1055 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "control queues"); 1056 for_each_port(sc, i) { 1057 struct sge_wrq *ctrlq = &sc->sge.ctrlq[i]; 1058 1059 rc = alloc_ctrlq(sc, ctrlq, i, oid); 1060 if (rc != 0) 1061 return (rc); 1062 } 1063 1064 return (rc); 1065 } 1066 1067 /* 1068 * Idempotent 1069 */ 1070 int 1071 t4_teardown_adapter_queues(struct adapter *sc) 1072 { 1073 int i; 1074 1075 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 1076 1077 /* Do this before freeing the queue */ 1078 if (sc->flags & ADAP_SYSCTL_CTX) { 1079 sysctl_ctx_free(&sc->ctx); 1080 sc->flags &= ~ADAP_SYSCTL_CTX; 1081 } 1082 1083 if (!(sc->flags & IS_VF)) { 1084 for_each_port(sc, i) 1085 free_wrq(sc, &sc->sge.ctrlq[i]); 1086 } 1087 free_fwq(sc); 1088 1089 return (0); 1090 } 1091 1092 /* Maximum payload that could arrive with a single iq descriptor. */ 1093 static inline int 1094 max_rx_payload(struct adapter *sc, struct ifnet *ifp, const bool ofld) 1095 { 1096 int maxp; 1097 1098 /* large enough even when hw VLAN extraction is disabled */ 1099 maxp = sc->params.sge.fl_pktshift + ETHER_HDR_LEN + 1100 ETHER_VLAN_ENCAP_LEN + ifp->if_mtu; 1101 if (ofld && sc->tt.tls && sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS && 1102 maxp < sc->params.tp.max_rx_pdu) 1103 maxp = sc->params.tp.max_rx_pdu; 1104 return (maxp); 1105 } 1106 1107 int 1108 t4_setup_vi_queues(struct vi_info *vi) 1109 { 1110 int rc = 0, i, intr_idx, iqidx; 1111 struct sge_rxq *rxq; 1112 struct sge_txq *txq; 1113 #ifdef TCP_OFFLOAD 1114 struct sge_ofld_rxq *ofld_rxq; 1115 #endif 1116 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1117 struct sge_ofld_txq *ofld_txq; 1118 #endif 1119 #ifdef DEV_NETMAP 1120 int saved_idx; 1121 struct sge_nm_rxq *nm_rxq; 1122 struct sge_nm_txq *nm_txq; 1123 #endif 1124 char name[16]; 1125 struct port_info *pi = vi->pi; 1126 struct adapter *sc = pi->adapter; 1127 struct ifnet *ifp = vi->ifp; 1128 struct sysctl_oid *oid = device_get_sysctl_tree(vi->dev); 1129 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 1130 int maxp; 1131 1132 /* Interrupt vector to start from (when using multiple vectors) */ 1133 intr_idx = vi->first_intr; 1134 1135 #ifdef DEV_NETMAP 1136 saved_idx = intr_idx; 1137 if (ifp->if_capabilities & IFCAP_NETMAP) { 1138 1139 /* netmap is supported with direct interrupts only. */ 1140 MPASS(!forwarding_intr_to_fwq(sc)); 1141 1142 /* 1143 * We don't have buffers to back the netmap rx queues 1144 * right now so we create the queues in a way that 1145 * doesn't set off any congestion signal in the chip. 1146 */ 1147 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "nm_rxq", 1148 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "rx queues"); 1149 for_each_nm_rxq(vi, i, nm_rxq) { 1150 rc = alloc_nm_rxq(vi, nm_rxq, intr_idx, i, oid); 1151 if (rc != 0) 1152 goto done; 1153 intr_idx++; 1154 } 1155 1156 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "nm_txq", 1157 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "tx queues"); 1158 for_each_nm_txq(vi, i, nm_txq) { 1159 iqidx = vi->first_nm_rxq + (i % vi->nnmrxq); 1160 rc = alloc_nm_txq(vi, nm_txq, iqidx, i, oid); 1161 if (rc != 0) 1162 goto done; 1163 } 1164 } 1165 1166 /* Normal rx queues and netmap rx queues share the same interrupts. */ 1167 intr_idx = saved_idx; 1168 #endif 1169 1170 /* 1171 * Allocate rx queues first because a default iqid is required when 1172 * creating a tx queue. 1173 */ 1174 maxp = max_rx_payload(sc, ifp, false); 1175 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "rxq", 1176 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "rx queues"); 1177 for_each_rxq(vi, i, rxq) { 1178 1179 init_iq(&rxq->iq, sc, vi->tmr_idx, vi->pktc_idx, vi->qsize_rxq); 1180 1181 snprintf(name, sizeof(name), "%s rxq%d-fl", 1182 device_get_nameunit(vi->dev), i); 1183 init_fl(sc, &rxq->fl, vi->qsize_rxq / 8, maxp, name); 1184 1185 rc = alloc_rxq(vi, rxq, 1186 forwarding_intr_to_fwq(sc) ? -1 : intr_idx, i, oid); 1187 if (rc != 0) 1188 goto done; 1189 intr_idx++; 1190 } 1191 #ifdef DEV_NETMAP 1192 if (ifp->if_capabilities & IFCAP_NETMAP) 1193 intr_idx = saved_idx + max(vi->nrxq, vi->nnmrxq); 1194 #endif 1195 #ifdef TCP_OFFLOAD 1196 maxp = max_rx_payload(sc, ifp, true); 1197 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_rxq", 1198 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "rx queues for offloaded TCP connections"); 1199 for_each_ofld_rxq(vi, i, ofld_rxq) { 1200 1201 init_iq(&ofld_rxq->iq, sc, vi->ofld_tmr_idx, vi->ofld_pktc_idx, 1202 vi->qsize_rxq); 1203 1204 snprintf(name, sizeof(name), "%s ofld_rxq%d-fl", 1205 device_get_nameunit(vi->dev), i); 1206 init_fl(sc, &ofld_rxq->fl, vi->qsize_rxq / 8, maxp, name); 1207 1208 rc = alloc_ofld_rxq(vi, ofld_rxq, 1209 forwarding_intr_to_fwq(sc) ? -1 : intr_idx, i, oid); 1210 if (rc != 0) 1211 goto done; 1212 intr_idx++; 1213 } 1214 #endif 1215 1216 /* 1217 * Now the tx queues. 1218 */ 1219 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "txq", 1220 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "tx queues"); 1221 for_each_txq(vi, i, txq) { 1222 iqidx = vi->first_rxq + (i % vi->nrxq); 1223 snprintf(name, sizeof(name), "%s txq%d", 1224 device_get_nameunit(vi->dev), i); 1225 init_eq(sc, &txq->eq, EQ_ETH, vi->qsize_txq, pi->tx_chan, 1226 sc->sge.rxq[iqidx].iq.cntxt_id, name); 1227 1228 rc = alloc_txq(vi, txq, i, oid); 1229 if (rc != 0) 1230 goto done; 1231 } 1232 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1233 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_txq", 1234 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "tx queues for TOE/ETHOFLD"); 1235 for_each_ofld_txq(vi, i, ofld_txq) { 1236 snprintf(name, sizeof(name), "%s ofld_txq%d", 1237 device_get_nameunit(vi->dev), i); 1238 if (vi->nofldrxq > 0) { 1239 iqidx = vi->first_ofld_rxq + (i % vi->nofldrxq); 1240 init_eq(sc, &ofld_txq->wrq.eq, EQ_OFLD, vi->qsize_txq, 1241 pi->tx_chan, sc->sge.ofld_rxq[iqidx].iq.cntxt_id, 1242 name); 1243 } else { 1244 iqidx = vi->first_rxq + (i % vi->nrxq); 1245 init_eq(sc, &ofld_txq->wrq.eq, EQ_OFLD, vi->qsize_txq, 1246 pi->tx_chan, sc->sge.rxq[iqidx].iq.cntxt_id, name); 1247 } 1248 1249 rc = alloc_ofld_txq(vi, ofld_txq, i, oid); 1250 if (rc != 0) 1251 goto done; 1252 } 1253 #endif 1254 done: 1255 if (rc) 1256 t4_teardown_vi_queues(vi); 1257 1258 return (rc); 1259 } 1260 1261 /* 1262 * Idempotent 1263 */ 1264 int 1265 t4_teardown_vi_queues(struct vi_info *vi) 1266 { 1267 int i; 1268 struct sge_rxq *rxq; 1269 struct sge_txq *txq; 1270 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1271 struct sge_ofld_txq *ofld_txq; 1272 #endif 1273 #ifdef TCP_OFFLOAD 1274 struct sge_ofld_rxq *ofld_rxq; 1275 #endif 1276 #ifdef DEV_NETMAP 1277 struct sge_nm_rxq *nm_rxq; 1278 struct sge_nm_txq *nm_txq; 1279 #endif 1280 1281 /* Do this before freeing the queues */ 1282 if (vi->flags & VI_SYSCTL_CTX) { 1283 sysctl_ctx_free(&vi->ctx); 1284 vi->flags &= ~VI_SYSCTL_CTX; 1285 } 1286 1287 #ifdef DEV_NETMAP 1288 if (vi->ifp->if_capabilities & IFCAP_NETMAP) { 1289 for_each_nm_txq(vi, i, nm_txq) { 1290 free_nm_txq(vi, nm_txq); 1291 } 1292 1293 for_each_nm_rxq(vi, i, nm_rxq) { 1294 free_nm_rxq(vi, nm_rxq); 1295 } 1296 } 1297 #endif 1298 1299 /* 1300 * Take down all the tx queues first, as they reference the rx queues 1301 * (for egress updates, etc.). 1302 */ 1303 1304 for_each_txq(vi, i, txq) { 1305 free_txq(vi, txq); 1306 } 1307 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1308 for_each_ofld_txq(vi, i, ofld_txq) { 1309 free_ofld_txq(vi, ofld_txq); 1310 } 1311 #endif 1312 1313 /* 1314 * Then take down the rx queues. 1315 */ 1316 1317 for_each_rxq(vi, i, rxq) { 1318 free_rxq(vi, rxq); 1319 } 1320 #ifdef TCP_OFFLOAD 1321 for_each_ofld_rxq(vi, i, ofld_rxq) { 1322 free_ofld_rxq(vi, ofld_rxq); 1323 } 1324 #endif 1325 1326 return (0); 1327 } 1328 1329 /* 1330 * Interrupt handler when the driver is using only 1 interrupt. This is a very 1331 * unusual scenario. 1332 * 1333 * a) Deals with errors, if any. 1334 * b) Services firmware event queue, which is taking interrupts for all other 1335 * queues. 1336 */ 1337 void 1338 t4_intr_all(void *arg) 1339 { 1340 struct adapter *sc = arg; 1341 struct sge_iq *fwq = &sc->sge.fwq; 1342 1343 MPASS(sc->intr_count == 1); 1344 1345 if (sc->intr_type == INTR_INTX) 1346 t4_write_reg(sc, MYPF_REG(A_PCIE_PF_CLI), 0); 1347 1348 t4_intr_err(arg); 1349 t4_intr_evt(fwq); 1350 } 1351 1352 /* 1353 * Interrupt handler for errors (installed directly when multiple interrupts are 1354 * being used, or called by t4_intr_all). 1355 */ 1356 void 1357 t4_intr_err(void *arg) 1358 { 1359 struct adapter *sc = arg; 1360 uint32_t v; 1361 const bool verbose = (sc->debug_flags & DF_VERBOSE_SLOWINTR) != 0; 1362 1363 if (sc->flags & ADAP_ERR) 1364 return; 1365 1366 v = t4_read_reg(sc, MYPF_REG(A_PL_PF_INT_CAUSE)); 1367 if (v & F_PFSW) { 1368 sc->swintr++; 1369 t4_write_reg(sc, MYPF_REG(A_PL_PF_INT_CAUSE), v); 1370 } 1371 1372 t4_slow_intr_handler(sc, verbose); 1373 } 1374 1375 /* 1376 * Interrupt handler for iq-only queues. The firmware event queue is the only 1377 * such queue right now. 1378 */ 1379 void 1380 t4_intr_evt(void *arg) 1381 { 1382 struct sge_iq *iq = arg; 1383 1384 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 1385 service_iq(iq, 0); 1386 (void) atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 1387 } 1388 } 1389 1390 /* 1391 * Interrupt handler for iq+fl queues. 1392 */ 1393 void 1394 t4_intr(void *arg) 1395 { 1396 struct sge_iq *iq = arg; 1397 1398 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 1399 service_iq_fl(iq, 0); 1400 (void) atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 1401 } 1402 } 1403 1404 #ifdef DEV_NETMAP 1405 /* 1406 * Interrupt handler for netmap rx queues. 1407 */ 1408 void 1409 t4_nm_intr(void *arg) 1410 { 1411 struct sge_nm_rxq *nm_rxq = arg; 1412 1413 if (atomic_cmpset_int(&nm_rxq->nm_state, NM_ON, NM_BUSY)) { 1414 service_nm_rxq(nm_rxq); 1415 (void) atomic_cmpset_int(&nm_rxq->nm_state, NM_BUSY, NM_ON); 1416 } 1417 } 1418 1419 /* 1420 * Interrupt handler for vectors shared between NIC and netmap rx queues. 1421 */ 1422 void 1423 t4_vi_intr(void *arg) 1424 { 1425 struct irq *irq = arg; 1426 1427 MPASS(irq->nm_rxq != NULL); 1428 t4_nm_intr(irq->nm_rxq); 1429 1430 MPASS(irq->rxq != NULL); 1431 t4_intr(irq->rxq); 1432 } 1433 #endif 1434 1435 /* 1436 * Deals with interrupts on an iq-only (no freelist) queue. 1437 */ 1438 static int 1439 service_iq(struct sge_iq *iq, int budget) 1440 { 1441 struct sge_iq *q; 1442 struct adapter *sc = iq->adapter; 1443 struct iq_desc *d = &iq->desc[iq->cidx]; 1444 int ndescs = 0, limit; 1445 int rsp_type; 1446 uint32_t lq; 1447 STAILQ_HEAD(, sge_iq) iql = STAILQ_HEAD_INITIALIZER(iql); 1448 1449 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq)); 1450 KASSERT((iq->flags & IQ_HAS_FL) == 0, 1451 ("%s: called for iq %p with fl (iq->flags 0x%x)", __func__, iq, 1452 iq->flags)); 1453 MPASS((iq->flags & IQ_ADJ_CREDIT) == 0); 1454 MPASS((iq->flags & IQ_LRO_ENABLED) == 0); 1455 1456 limit = budget ? budget : iq->qsize / 16; 1457 1458 /* 1459 * We always come back and check the descriptor ring for new indirect 1460 * interrupts and other responses after running a single handler. 1461 */ 1462 for (;;) { 1463 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) { 1464 1465 rmb(); 1466 1467 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen); 1468 lq = be32toh(d->rsp.pldbuflen_qid); 1469 1470 switch (rsp_type) { 1471 case X_RSPD_TYPE_FLBUF: 1472 panic("%s: data for an iq (%p) with no freelist", 1473 __func__, iq); 1474 1475 /* NOTREACHED */ 1476 1477 case X_RSPD_TYPE_CPL: 1478 KASSERT(d->rss.opcode < NUM_CPL_CMDS, 1479 ("%s: bad opcode %02x.", __func__, 1480 d->rss.opcode)); 1481 t4_cpl_handler[d->rss.opcode](iq, &d->rss, NULL); 1482 break; 1483 1484 case X_RSPD_TYPE_INTR: 1485 /* 1486 * There are 1K interrupt-capable queues (qids 0 1487 * through 1023). A response type indicating a 1488 * forwarded interrupt with a qid >= 1K is an 1489 * iWARP async notification. 1490 */ 1491 if (__predict_true(lq >= 1024)) { 1492 t4_an_handler(iq, &d->rsp); 1493 break; 1494 } 1495 1496 q = sc->sge.iqmap[lq - sc->sge.iq_start - 1497 sc->sge.iq_base]; 1498 if (atomic_cmpset_int(&q->state, IQS_IDLE, 1499 IQS_BUSY)) { 1500 if (service_iq_fl(q, q->qsize / 16) == 0) { 1501 (void) atomic_cmpset_int(&q->state, 1502 IQS_BUSY, IQS_IDLE); 1503 } else { 1504 STAILQ_INSERT_TAIL(&iql, q, 1505 link); 1506 } 1507 } 1508 break; 1509 1510 default: 1511 KASSERT(0, 1512 ("%s: illegal response type %d on iq %p", 1513 __func__, rsp_type, iq)); 1514 log(LOG_ERR, 1515 "%s: illegal response type %d on iq %p", 1516 device_get_nameunit(sc->dev), rsp_type, iq); 1517 break; 1518 } 1519 1520 d++; 1521 if (__predict_false(++iq->cidx == iq->sidx)) { 1522 iq->cidx = 0; 1523 iq->gen ^= F_RSPD_GEN; 1524 d = &iq->desc[0]; 1525 } 1526 if (__predict_false(++ndescs == limit)) { 1527 t4_write_reg(sc, sc->sge_gts_reg, 1528 V_CIDXINC(ndescs) | 1529 V_INGRESSQID(iq->cntxt_id) | 1530 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); 1531 ndescs = 0; 1532 1533 if (budget) { 1534 return (EINPROGRESS); 1535 } 1536 } 1537 } 1538 1539 if (STAILQ_EMPTY(&iql)) 1540 break; 1541 1542 /* 1543 * Process the head only, and send it to the back of the list if 1544 * it's still not done. 1545 */ 1546 q = STAILQ_FIRST(&iql); 1547 STAILQ_REMOVE_HEAD(&iql, link); 1548 if (service_iq_fl(q, q->qsize / 8) == 0) 1549 (void) atomic_cmpset_int(&q->state, IQS_BUSY, IQS_IDLE); 1550 else 1551 STAILQ_INSERT_TAIL(&iql, q, link); 1552 } 1553 1554 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) | 1555 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params)); 1556 1557 return (0); 1558 } 1559 1560 static inline int 1561 sort_before_lro(struct lro_ctrl *lro) 1562 { 1563 1564 return (lro->lro_mbuf_max != 0); 1565 } 1566 1567 static inline uint64_t 1568 last_flit_to_ns(struct adapter *sc, uint64_t lf) 1569 { 1570 uint64_t n = be64toh(lf) & 0xfffffffffffffff; /* 60b, not 64b. */ 1571 1572 if (n > UINT64_MAX / 1000000) 1573 return (n / sc->params.vpd.cclk * 1000000); 1574 else 1575 return (n * 1000000 / sc->params.vpd.cclk); 1576 } 1577 1578 static inline void 1579 move_to_next_rxbuf(struct sge_fl *fl) 1580 { 1581 1582 fl->rx_offset = 0; 1583 if (__predict_false((++fl->cidx & 7) == 0)) { 1584 uint16_t cidx = fl->cidx >> 3; 1585 1586 if (__predict_false(cidx == fl->sidx)) 1587 fl->cidx = cidx = 0; 1588 fl->hw_cidx = cidx; 1589 } 1590 } 1591 1592 /* 1593 * Deals with interrupts on an iq+fl queue. 1594 */ 1595 static int 1596 service_iq_fl(struct sge_iq *iq, int budget) 1597 { 1598 struct sge_rxq *rxq = iq_to_rxq(iq); 1599 struct sge_fl *fl; 1600 struct adapter *sc = iq->adapter; 1601 struct iq_desc *d = &iq->desc[iq->cidx]; 1602 int ndescs, limit; 1603 int rsp_type, starved; 1604 uint32_t lq; 1605 uint16_t fl_hw_cidx; 1606 struct mbuf *m0; 1607 #if defined(INET) || defined(INET6) 1608 const struct timeval lro_timeout = {0, sc->lro_timeout}; 1609 struct lro_ctrl *lro = &rxq->lro; 1610 #endif 1611 1612 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq)); 1613 MPASS(iq->flags & IQ_HAS_FL); 1614 1615 ndescs = 0; 1616 #if defined(INET) || defined(INET6) 1617 if (iq->flags & IQ_ADJ_CREDIT) { 1618 MPASS(sort_before_lro(lro)); 1619 iq->flags &= ~IQ_ADJ_CREDIT; 1620 if ((d->rsp.u.type_gen & F_RSPD_GEN) != iq->gen) { 1621 tcp_lro_flush_all(lro); 1622 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(1) | 1623 V_INGRESSQID((u32)iq->cntxt_id) | 1624 V_SEINTARM(iq->intr_params)); 1625 return (0); 1626 } 1627 ndescs = 1; 1628 } 1629 #else 1630 MPASS((iq->flags & IQ_ADJ_CREDIT) == 0); 1631 #endif 1632 1633 limit = budget ? budget : iq->qsize / 16; 1634 fl = &rxq->fl; 1635 fl_hw_cidx = fl->hw_cidx; /* stable snapshot */ 1636 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) { 1637 1638 rmb(); 1639 1640 m0 = NULL; 1641 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen); 1642 lq = be32toh(d->rsp.pldbuflen_qid); 1643 1644 switch (rsp_type) { 1645 case X_RSPD_TYPE_FLBUF: 1646 if (lq & F_RSPD_NEWBUF) { 1647 if (fl->rx_offset > 0) 1648 move_to_next_rxbuf(fl); 1649 lq = G_RSPD_LEN(lq); 1650 } 1651 if (IDXDIFF(fl->hw_cidx, fl_hw_cidx, fl->sidx) > 4) { 1652 FL_LOCK(fl); 1653 refill_fl(sc, fl, 64); 1654 FL_UNLOCK(fl); 1655 fl_hw_cidx = fl->hw_cidx; 1656 } 1657 1658 if (d->rss.opcode == CPL_RX_PKT) { 1659 if (__predict_true(eth_rx(sc, rxq, d, lq) == 0)) 1660 break; 1661 goto out; 1662 } 1663 m0 = get_fl_payload(sc, fl, lq); 1664 if (__predict_false(m0 == NULL)) 1665 goto out; 1666 1667 /* fall through */ 1668 1669 case X_RSPD_TYPE_CPL: 1670 KASSERT(d->rss.opcode < NUM_CPL_CMDS, 1671 ("%s: bad opcode %02x.", __func__, d->rss.opcode)); 1672 t4_cpl_handler[d->rss.opcode](iq, &d->rss, m0); 1673 break; 1674 1675 case X_RSPD_TYPE_INTR: 1676 1677 /* 1678 * There are 1K interrupt-capable queues (qids 0 1679 * through 1023). A response type indicating a 1680 * forwarded interrupt with a qid >= 1K is an 1681 * iWARP async notification. That is the only 1682 * acceptable indirect interrupt on this queue. 1683 */ 1684 if (__predict_false(lq < 1024)) { 1685 panic("%s: indirect interrupt on iq_fl %p " 1686 "with qid %u", __func__, iq, lq); 1687 } 1688 1689 t4_an_handler(iq, &d->rsp); 1690 break; 1691 1692 default: 1693 KASSERT(0, ("%s: illegal response type %d on iq %p", 1694 __func__, rsp_type, iq)); 1695 log(LOG_ERR, "%s: illegal response type %d on iq %p", 1696 device_get_nameunit(sc->dev), rsp_type, iq); 1697 break; 1698 } 1699 1700 d++; 1701 if (__predict_false(++iq->cidx == iq->sidx)) { 1702 iq->cidx = 0; 1703 iq->gen ^= F_RSPD_GEN; 1704 d = &iq->desc[0]; 1705 } 1706 if (__predict_false(++ndescs == limit)) { 1707 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) | 1708 V_INGRESSQID(iq->cntxt_id) | 1709 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); 1710 1711 #if defined(INET) || defined(INET6) 1712 if (iq->flags & IQ_LRO_ENABLED && 1713 !sort_before_lro(lro) && 1714 sc->lro_timeout != 0) { 1715 tcp_lro_flush_inactive(lro, &lro_timeout); 1716 } 1717 #endif 1718 if (budget) 1719 return (EINPROGRESS); 1720 ndescs = 0; 1721 } 1722 } 1723 out: 1724 #if defined(INET) || defined(INET6) 1725 if (iq->flags & IQ_LRO_ENABLED) { 1726 if (ndescs > 0 && lro->lro_mbuf_count > 8) { 1727 MPASS(sort_before_lro(lro)); 1728 /* hold back one credit and don't flush LRO state */ 1729 iq->flags |= IQ_ADJ_CREDIT; 1730 ndescs--; 1731 } else { 1732 tcp_lro_flush_all(lro); 1733 } 1734 } 1735 #endif 1736 1737 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) | 1738 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params)); 1739 1740 FL_LOCK(fl); 1741 starved = refill_fl(sc, fl, 64); 1742 FL_UNLOCK(fl); 1743 if (__predict_false(starved != 0)) 1744 add_fl_to_sfl(sc, fl); 1745 1746 return (0); 1747 } 1748 1749 static inline struct cluster_metadata * 1750 cl_metadata(struct fl_sdesc *sd) 1751 { 1752 1753 return ((void *)(sd->cl + sd->moff)); 1754 } 1755 1756 static void 1757 rxb_free(struct mbuf *m) 1758 { 1759 struct cluster_metadata *clm = m->m_ext.ext_arg1; 1760 1761 uma_zfree(clm->zone, clm->cl); 1762 counter_u64_add(extfree_rels, 1); 1763 } 1764 1765 /* 1766 * The mbuf returned comes from zone_muf and carries the payload in one of these 1767 * ways 1768 * a) complete frame inside the mbuf 1769 * b) m_cljset (for clusters without metadata) 1770 * d) m_extaddref (cluster with metadata) 1771 */ 1772 static struct mbuf * 1773 get_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset, 1774 int remaining) 1775 { 1776 struct mbuf *m; 1777 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 1778 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[sd->zidx]; 1779 struct cluster_metadata *clm; 1780 int len, blen; 1781 caddr_t payload; 1782 1783 if (fl->flags & FL_BUF_PACKING) { 1784 u_int l, pad; 1785 1786 blen = rxb->size2 - fl->rx_offset; /* max possible in this buf */ 1787 len = min(remaining, blen); 1788 payload = sd->cl + fl->rx_offset; 1789 1790 l = fr_offset + len; 1791 pad = roundup2(l, fl->buf_boundary) - l; 1792 if (fl->rx_offset + len + pad < rxb->size2) 1793 blen = len + pad; 1794 MPASS(fl->rx_offset + blen <= rxb->size2); 1795 } else { 1796 MPASS(fl->rx_offset == 0); /* not packing */ 1797 blen = rxb->size1; 1798 len = min(remaining, blen); 1799 payload = sd->cl; 1800 } 1801 1802 if (fr_offset == 0) { 1803 m = m_gethdr(M_NOWAIT, MT_DATA); 1804 if (__predict_false(m == NULL)) 1805 return (NULL); 1806 m->m_pkthdr.len = remaining; 1807 } else { 1808 m = m_get(M_NOWAIT, MT_DATA); 1809 if (__predict_false(m == NULL)) 1810 return (NULL); 1811 } 1812 m->m_len = len; 1813 1814 if (sc->sc_do_rxcopy && len < RX_COPY_THRESHOLD) { 1815 /* copy data to mbuf */ 1816 bcopy(payload, mtod(m, caddr_t), len); 1817 if (fl->flags & FL_BUF_PACKING) { 1818 fl->rx_offset += blen; 1819 MPASS(fl->rx_offset <= rxb->size2); 1820 if (fl->rx_offset < rxb->size2) 1821 return (m); /* without advancing the cidx */ 1822 } 1823 } else if (fl->flags & FL_BUF_PACKING) { 1824 clm = cl_metadata(sd); 1825 if (sd->nmbuf++ == 0) { 1826 clm->refcount = 1; 1827 clm->zone = rxb->zone; 1828 clm->cl = sd->cl; 1829 counter_u64_add(extfree_refs, 1); 1830 } 1831 m_extaddref(m, payload, blen, &clm->refcount, rxb_free, clm, 1832 NULL); 1833 1834 fl->rx_offset += blen; 1835 MPASS(fl->rx_offset <= rxb->size2); 1836 if (fl->rx_offset < rxb->size2) 1837 return (m); /* without advancing the cidx */ 1838 } else { 1839 m_cljset(m, sd->cl, rxb->type); 1840 sd->cl = NULL; /* consumed, not a recycle candidate */ 1841 } 1842 1843 move_to_next_rxbuf(fl); 1844 1845 return (m); 1846 } 1847 1848 static struct mbuf * 1849 get_fl_payload(struct adapter *sc, struct sge_fl *fl, const u_int plen) 1850 { 1851 struct mbuf *m0, *m, **pnext; 1852 u_int remaining; 1853 1854 if (__predict_false(fl->flags & FL_BUF_RESUME)) { 1855 M_ASSERTPKTHDR(fl->m0); 1856 MPASS(fl->m0->m_pkthdr.len == plen); 1857 MPASS(fl->remaining < plen); 1858 1859 m0 = fl->m0; 1860 pnext = fl->pnext; 1861 remaining = fl->remaining; 1862 fl->flags &= ~FL_BUF_RESUME; 1863 goto get_segment; 1864 } 1865 1866 /* 1867 * Payload starts at rx_offset in the current hw buffer. Its length is 1868 * 'len' and it may span multiple hw buffers. 1869 */ 1870 1871 m0 = get_scatter_segment(sc, fl, 0, plen); 1872 if (m0 == NULL) 1873 return (NULL); 1874 remaining = plen - m0->m_len; 1875 pnext = &m0->m_next; 1876 while (remaining > 0) { 1877 get_segment: 1878 MPASS(fl->rx_offset == 0); 1879 m = get_scatter_segment(sc, fl, plen - remaining, remaining); 1880 if (__predict_false(m == NULL)) { 1881 fl->m0 = m0; 1882 fl->pnext = pnext; 1883 fl->remaining = remaining; 1884 fl->flags |= FL_BUF_RESUME; 1885 return (NULL); 1886 } 1887 *pnext = m; 1888 pnext = &m->m_next; 1889 remaining -= m->m_len; 1890 } 1891 *pnext = NULL; 1892 1893 M_ASSERTPKTHDR(m0); 1894 return (m0); 1895 } 1896 1897 static int 1898 skip_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset, 1899 int remaining) 1900 { 1901 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 1902 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[sd->zidx]; 1903 int len, blen; 1904 1905 if (fl->flags & FL_BUF_PACKING) { 1906 u_int l, pad; 1907 1908 blen = rxb->size2 - fl->rx_offset; /* max possible in this buf */ 1909 len = min(remaining, blen); 1910 1911 l = fr_offset + len; 1912 pad = roundup2(l, fl->buf_boundary) - l; 1913 if (fl->rx_offset + len + pad < rxb->size2) 1914 blen = len + pad; 1915 fl->rx_offset += blen; 1916 MPASS(fl->rx_offset <= rxb->size2); 1917 if (fl->rx_offset < rxb->size2) 1918 return (len); /* without advancing the cidx */ 1919 } else { 1920 MPASS(fl->rx_offset == 0); /* not packing */ 1921 blen = rxb->size1; 1922 len = min(remaining, blen); 1923 } 1924 move_to_next_rxbuf(fl); 1925 return (len); 1926 } 1927 1928 static inline void 1929 skip_fl_payload(struct adapter *sc, struct sge_fl *fl, int plen) 1930 { 1931 int remaining, fr_offset, len; 1932 1933 fr_offset = 0; 1934 remaining = plen; 1935 while (remaining > 0) { 1936 len = skip_scatter_segment(sc, fl, fr_offset, remaining); 1937 fr_offset += len; 1938 remaining -= len; 1939 } 1940 } 1941 1942 static inline int 1943 get_segment_len(struct adapter *sc, struct sge_fl *fl, int plen) 1944 { 1945 int len; 1946 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 1947 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[sd->zidx]; 1948 1949 if (fl->flags & FL_BUF_PACKING) 1950 len = rxb->size2 - fl->rx_offset; 1951 else 1952 len = rxb->size1; 1953 1954 return (min(plen, len)); 1955 } 1956 1957 static int 1958 eth_rx(struct adapter *sc, struct sge_rxq *rxq, const struct iq_desc *d, 1959 u_int plen) 1960 { 1961 struct mbuf *m0; 1962 struct ifnet *ifp = rxq->ifp; 1963 struct sge_fl *fl = &rxq->fl; 1964 struct vi_info *vi = ifp->if_softc; 1965 const struct cpl_rx_pkt *cpl; 1966 #if defined(INET) || defined(INET6) 1967 struct lro_ctrl *lro = &rxq->lro; 1968 #endif 1969 uint16_t err_vec, tnl_type, tnlhdr_len; 1970 static const int sw_hashtype[4][2] = { 1971 {M_HASHTYPE_NONE, M_HASHTYPE_NONE}, 1972 {M_HASHTYPE_RSS_IPV4, M_HASHTYPE_RSS_IPV6}, 1973 {M_HASHTYPE_RSS_TCP_IPV4, M_HASHTYPE_RSS_TCP_IPV6}, 1974 {M_HASHTYPE_RSS_UDP_IPV4, M_HASHTYPE_RSS_UDP_IPV6}, 1975 }; 1976 static const int sw_csum_flags[2][2] = { 1977 { 1978 /* IP, inner IP */ 1979 CSUM_ENCAP_VXLAN | 1980 CSUM_L3_CALC | CSUM_L3_VALID | 1981 CSUM_L4_CALC | CSUM_L4_VALID | 1982 CSUM_INNER_L3_CALC | CSUM_INNER_L3_VALID | 1983 CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID, 1984 1985 /* IP, inner IP6 */ 1986 CSUM_ENCAP_VXLAN | 1987 CSUM_L3_CALC | CSUM_L3_VALID | 1988 CSUM_L4_CALC | CSUM_L4_VALID | 1989 CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID, 1990 }, 1991 { 1992 /* IP6, inner IP */ 1993 CSUM_ENCAP_VXLAN | 1994 CSUM_L4_CALC | CSUM_L4_VALID | 1995 CSUM_INNER_L3_CALC | CSUM_INNER_L3_VALID | 1996 CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID, 1997 1998 /* IP6, inner IP6 */ 1999 CSUM_ENCAP_VXLAN | 2000 CSUM_L4_CALC | CSUM_L4_VALID | 2001 CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID, 2002 }, 2003 }; 2004 2005 MPASS(plen > sc->params.sge.fl_pktshift); 2006 if (vi->pfil != NULL && PFIL_HOOKED_IN(vi->pfil) && 2007 __predict_true((fl->flags & FL_BUF_RESUME) == 0)) { 2008 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 2009 caddr_t frame; 2010 int rc, slen; 2011 2012 slen = get_segment_len(sc, fl, plen) - 2013 sc->params.sge.fl_pktshift; 2014 frame = sd->cl + fl->rx_offset + sc->params.sge.fl_pktshift; 2015 CURVNET_SET_QUIET(ifp->if_vnet); 2016 rc = pfil_run_hooks(vi->pfil, frame, ifp, 2017 slen | PFIL_MEMPTR | PFIL_IN, NULL); 2018 CURVNET_RESTORE(); 2019 if (rc == PFIL_DROPPED || rc == PFIL_CONSUMED) { 2020 skip_fl_payload(sc, fl, plen); 2021 return (0); 2022 } 2023 if (rc == PFIL_REALLOCED) { 2024 skip_fl_payload(sc, fl, plen); 2025 m0 = pfil_mem2mbuf(frame); 2026 goto have_mbuf; 2027 } 2028 } 2029 2030 m0 = get_fl_payload(sc, fl, plen); 2031 if (__predict_false(m0 == NULL)) 2032 return (ENOMEM); 2033 2034 m0->m_pkthdr.len -= sc->params.sge.fl_pktshift; 2035 m0->m_len -= sc->params.sge.fl_pktshift; 2036 m0->m_data += sc->params.sge.fl_pktshift; 2037 2038 have_mbuf: 2039 m0->m_pkthdr.rcvif = ifp; 2040 M_HASHTYPE_SET(m0, sw_hashtype[d->rss.hash_type][d->rss.ipv6]); 2041 m0->m_pkthdr.flowid = be32toh(d->rss.hash_val); 2042 2043 cpl = (const void *)(&d->rss + 1); 2044 if (sc->params.tp.rx_pkt_encap) { 2045 const uint16_t ev = be16toh(cpl->err_vec); 2046 2047 err_vec = G_T6_COMPR_RXERR_VEC(ev); 2048 tnl_type = G_T6_RX_TNL_TYPE(ev); 2049 tnlhdr_len = G_T6_RX_TNLHDR_LEN(ev); 2050 } else { 2051 err_vec = be16toh(cpl->err_vec); 2052 tnl_type = 0; 2053 tnlhdr_len = 0; 2054 } 2055 if (cpl->csum_calc && err_vec == 0) { 2056 int ipv6 = !!(cpl->l2info & htobe32(F_RXF_IP6)); 2057 2058 /* checksum(s) calculated and found to be correct. */ 2059 2060 MPASS((cpl->l2info & htobe32(F_RXF_IP)) ^ 2061 (cpl->l2info & htobe32(F_RXF_IP6))); 2062 m0->m_pkthdr.csum_data = be16toh(cpl->csum); 2063 if (tnl_type == 0) { 2064 if (!ipv6 && ifp->if_capenable & IFCAP_RXCSUM) { 2065 m0->m_pkthdr.csum_flags = CSUM_L3_CALC | 2066 CSUM_L3_VALID | CSUM_L4_CALC | 2067 CSUM_L4_VALID; 2068 } else if (ipv6 && ifp->if_capenable & IFCAP_RXCSUM_IPV6) { 2069 m0->m_pkthdr.csum_flags = CSUM_L4_CALC | 2070 CSUM_L4_VALID; 2071 } 2072 rxq->rxcsum++; 2073 } else { 2074 MPASS(tnl_type == RX_PKT_TNL_TYPE_VXLAN); 2075 2076 M_HASHTYPE_SETINNER(m0); 2077 if (__predict_false(cpl->ip_frag)) { 2078 /* 2079 * csum_data is for the inner frame (which is an 2080 * IP fragment) and is not 0xffff. There is no 2081 * way to pass the inner csum_data to the stack. 2082 * We don't want the stack to use the inner 2083 * csum_data to validate the outer frame or it 2084 * will get rejected. So we fix csum_data here 2085 * and let sw do the checksum of inner IP 2086 * fragments. 2087 * 2088 * XXX: Need 32b for csum_data2 in an rx mbuf. 2089 * Maybe stuff it into rcv_tstmp? 2090 */ 2091 m0->m_pkthdr.csum_data = 0xffff; 2092 if (ipv6) { 2093 m0->m_pkthdr.csum_flags = CSUM_L4_CALC | 2094 CSUM_L4_VALID; 2095 } else { 2096 m0->m_pkthdr.csum_flags = CSUM_L3_CALC | 2097 CSUM_L3_VALID | CSUM_L4_CALC | 2098 CSUM_L4_VALID; 2099 } 2100 } else { 2101 int outer_ipv6; 2102 2103 MPASS(m0->m_pkthdr.csum_data == 0xffff); 2104 2105 outer_ipv6 = tnlhdr_len >= 2106 sizeof(struct ether_header) + 2107 sizeof(struct ip6_hdr); 2108 m0->m_pkthdr.csum_flags = 2109 sw_csum_flags[outer_ipv6][ipv6]; 2110 } 2111 rxq->vxlan_rxcsum++; 2112 } 2113 } 2114 2115 if (cpl->vlan_ex) { 2116 m0->m_pkthdr.ether_vtag = be16toh(cpl->vlan); 2117 m0->m_flags |= M_VLANTAG; 2118 rxq->vlan_extraction++; 2119 } 2120 2121 if (rxq->iq.flags & IQ_RX_TIMESTAMP) { 2122 /* 2123 * Fill up rcv_tstmp but do not set M_TSTMP. 2124 * rcv_tstmp is not in the format that the 2125 * kernel expects and we don't want to mislead 2126 * it. For now this is only for custom code 2127 * that knows how to interpret cxgbe's stamp. 2128 */ 2129 m0->m_pkthdr.rcv_tstmp = 2130 last_flit_to_ns(sc, d->rsp.u.last_flit); 2131 #ifdef notyet 2132 m0->m_flags |= M_TSTMP; 2133 #endif 2134 } 2135 2136 #ifdef NUMA 2137 m0->m_pkthdr.numa_domain = ifp->if_numa_domain; 2138 #endif 2139 #if defined(INET) || defined(INET6) 2140 if (rxq->iq.flags & IQ_LRO_ENABLED && tnl_type == 0 && 2141 (M_HASHTYPE_GET(m0) == M_HASHTYPE_RSS_TCP_IPV4 || 2142 M_HASHTYPE_GET(m0) == M_HASHTYPE_RSS_TCP_IPV6)) { 2143 if (sort_before_lro(lro)) { 2144 tcp_lro_queue_mbuf(lro, m0); 2145 return (0); /* queued for sort, then LRO */ 2146 } 2147 if (tcp_lro_rx(lro, m0, 0) == 0) 2148 return (0); /* queued for LRO */ 2149 } 2150 #endif 2151 ifp->if_input(ifp, m0); 2152 2153 return (0); 2154 } 2155 2156 /* 2157 * Must drain the wrq or make sure that someone else will. 2158 */ 2159 static void 2160 wrq_tx_drain(void *arg, int n) 2161 { 2162 struct sge_wrq *wrq = arg; 2163 struct sge_eq *eq = &wrq->eq; 2164 2165 EQ_LOCK(eq); 2166 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 2167 drain_wrq_wr_list(wrq->adapter, wrq); 2168 EQ_UNLOCK(eq); 2169 } 2170 2171 static void 2172 drain_wrq_wr_list(struct adapter *sc, struct sge_wrq *wrq) 2173 { 2174 struct sge_eq *eq = &wrq->eq; 2175 u_int available, dbdiff; /* # of hardware descriptors */ 2176 u_int n; 2177 struct wrqe *wr; 2178 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */ 2179 2180 EQ_LOCK_ASSERT_OWNED(eq); 2181 MPASS(TAILQ_EMPTY(&wrq->incomplete_wrs)); 2182 wr = STAILQ_FIRST(&wrq->wr_list); 2183 MPASS(wr != NULL); /* Must be called with something useful to do */ 2184 MPASS(eq->pidx == eq->dbidx); 2185 dbdiff = 0; 2186 2187 do { 2188 eq->cidx = read_hw_cidx(eq); 2189 if (eq->pidx == eq->cidx) 2190 available = eq->sidx - 1; 2191 else 2192 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2193 2194 MPASS(wr->wrq == wrq); 2195 n = howmany(wr->wr_len, EQ_ESIZE); 2196 if (available < n) 2197 break; 2198 2199 dst = (void *)&eq->desc[eq->pidx]; 2200 if (__predict_true(eq->sidx - eq->pidx > n)) { 2201 /* Won't wrap, won't end exactly at the status page. */ 2202 bcopy(&wr->wr[0], dst, wr->wr_len); 2203 eq->pidx += n; 2204 } else { 2205 int first_portion = (eq->sidx - eq->pidx) * EQ_ESIZE; 2206 2207 bcopy(&wr->wr[0], dst, first_portion); 2208 if (wr->wr_len > first_portion) { 2209 bcopy(&wr->wr[first_portion], &eq->desc[0], 2210 wr->wr_len - first_portion); 2211 } 2212 eq->pidx = n - (eq->sidx - eq->pidx); 2213 } 2214 wrq->tx_wrs_copied++; 2215 2216 if (available < eq->sidx / 4 && 2217 atomic_cmpset_int(&eq->equiq, 0, 1)) { 2218 /* 2219 * XXX: This is not 100% reliable with some 2220 * types of WRs. But this is a very unusual 2221 * situation for an ofld/ctrl queue anyway. 2222 */ 2223 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ | 2224 F_FW_WR_EQUEQ); 2225 } 2226 2227 dbdiff += n; 2228 if (dbdiff >= 16) { 2229 ring_eq_db(sc, eq, dbdiff); 2230 dbdiff = 0; 2231 } 2232 2233 STAILQ_REMOVE_HEAD(&wrq->wr_list, link); 2234 free_wrqe(wr); 2235 MPASS(wrq->nwr_pending > 0); 2236 wrq->nwr_pending--; 2237 MPASS(wrq->ndesc_needed >= n); 2238 wrq->ndesc_needed -= n; 2239 } while ((wr = STAILQ_FIRST(&wrq->wr_list)) != NULL); 2240 2241 if (dbdiff) 2242 ring_eq_db(sc, eq, dbdiff); 2243 } 2244 2245 /* 2246 * Doesn't fail. Holds on to work requests it can't send right away. 2247 */ 2248 void 2249 t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, struct wrqe *wr) 2250 { 2251 #ifdef INVARIANTS 2252 struct sge_eq *eq = &wrq->eq; 2253 #endif 2254 2255 EQ_LOCK_ASSERT_OWNED(eq); 2256 MPASS(wr != NULL); 2257 MPASS(wr->wr_len > 0 && wr->wr_len <= SGE_MAX_WR_LEN); 2258 MPASS((wr->wr_len & 0x7) == 0); 2259 2260 STAILQ_INSERT_TAIL(&wrq->wr_list, wr, link); 2261 wrq->nwr_pending++; 2262 wrq->ndesc_needed += howmany(wr->wr_len, EQ_ESIZE); 2263 2264 if (!TAILQ_EMPTY(&wrq->incomplete_wrs)) 2265 return; /* commit_wrq_wr will drain wr_list as well. */ 2266 2267 drain_wrq_wr_list(sc, wrq); 2268 2269 /* Doorbell must have caught up to the pidx. */ 2270 MPASS(eq->pidx == eq->dbidx); 2271 } 2272 2273 void 2274 t4_update_fl_bufsize(struct ifnet *ifp) 2275 { 2276 struct vi_info *vi = ifp->if_softc; 2277 struct adapter *sc = vi->adapter; 2278 struct sge_rxq *rxq; 2279 #ifdef TCP_OFFLOAD 2280 struct sge_ofld_rxq *ofld_rxq; 2281 #endif 2282 struct sge_fl *fl; 2283 int i, maxp; 2284 2285 maxp = max_rx_payload(sc, ifp, false); 2286 for_each_rxq(vi, i, rxq) { 2287 fl = &rxq->fl; 2288 2289 FL_LOCK(fl); 2290 fl->zidx = find_refill_source(sc, maxp, 2291 fl->flags & FL_BUF_PACKING); 2292 FL_UNLOCK(fl); 2293 } 2294 #ifdef TCP_OFFLOAD 2295 maxp = max_rx_payload(sc, ifp, true); 2296 for_each_ofld_rxq(vi, i, ofld_rxq) { 2297 fl = &ofld_rxq->fl; 2298 2299 FL_LOCK(fl); 2300 fl->zidx = find_refill_source(sc, maxp, 2301 fl->flags & FL_BUF_PACKING); 2302 FL_UNLOCK(fl); 2303 } 2304 #endif 2305 } 2306 2307 static inline int 2308 mbuf_nsegs(struct mbuf *m) 2309 { 2310 2311 M_ASSERTPKTHDR(m); 2312 KASSERT(m->m_pkthdr.inner_l5hlen > 0, 2313 ("%s: mbuf %p missing information on # of segments.", __func__, m)); 2314 2315 return (m->m_pkthdr.inner_l5hlen); 2316 } 2317 2318 static inline void 2319 set_mbuf_nsegs(struct mbuf *m, uint8_t nsegs) 2320 { 2321 2322 M_ASSERTPKTHDR(m); 2323 m->m_pkthdr.inner_l5hlen = nsegs; 2324 } 2325 2326 static inline int 2327 mbuf_cflags(struct mbuf *m) 2328 { 2329 2330 M_ASSERTPKTHDR(m); 2331 return (m->m_pkthdr.PH_loc.eight[4]); 2332 } 2333 2334 static inline void 2335 set_mbuf_cflags(struct mbuf *m, uint8_t flags) 2336 { 2337 2338 M_ASSERTPKTHDR(m); 2339 m->m_pkthdr.PH_loc.eight[4] = flags; 2340 } 2341 2342 static inline int 2343 mbuf_len16(struct mbuf *m) 2344 { 2345 int n; 2346 2347 M_ASSERTPKTHDR(m); 2348 n = m->m_pkthdr.PH_loc.eight[0]; 2349 if (!(mbuf_cflags(m) & MC_TLS)) 2350 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16); 2351 2352 return (n); 2353 } 2354 2355 static inline void 2356 set_mbuf_len16(struct mbuf *m, uint8_t len16) 2357 { 2358 2359 M_ASSERTPKTHDR(m); 2360 if (!(mbuf_cflags(m) & MC_TLS)) 2361 MPASS(len16 > 0 && len16 <= SGE_MAX_WR_LEN / 16); 2362 m->m_pkthdr.PH_loc.eight[0] = len16; 2363 } 2364 2365 #ifdef RATELIMIT 2366 static inline int 2367 mbuf_eo_nsegs(struct mbuf *m) 2368 { 2369 2370 M_ASSERTPKTHDR(m); 2371 return (m->m_pkthdr.PH_loc.eight[1]); 2372 } 2373 2374 static inline void 2375 set_mbuf_eo_nsegs(struct mbuf *m, uint8_t nsegs) 2376 { 2377 2378 M_ASSERTPKTHDR(m); 2379 m->m_pkthdr.PH_loc.eight[1] = nsegs; 2380 } 2381 2382 static inline int 2383 mbuf_eo_len16(struct mbuf *m) 2384 { 2385 int n; 2386 2387 M_ASSERTPKTHDR(m); 2388 n = m->m_pkthdr.PH_loc.eight[2]; 2389 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16); 2390 2391 return (n); 2392 } 2393 2394 static inline void 2395 set_mbuf_eo_len16(struct mbuf *m, uint8_t len16) 2396 { 2397 2398 M_ASSERTPKTHDR(m); 2399 m->m_pkthdr.PH_loc.eight[2] = len16; 2400 } 2401 2402 static inline int 2403 mbuf_eo_tsclk_tsoff(struct mbuf *m) 2404 { 2405 2406 M_ASSERTPKTHDR(m); 2407 return (m->m_pkthdr.PH_loc.eight[3]); 2408 } 2409 2410 static inline void 2411 set_mbuf_eo_tsclk_tsoff(struct mbuf *m, uint8_t tsclk_tsoff) 2412 { 2413 2414 M_ASSERTPKTHDR(m); 2415 m->m_pkthdr.PH_loc.eight[3] = tsclk_tsoff; 2416 } 2417 2418 static inline int 2419 needs_eo(struct m_snd_tag *mst) 2420 { 2421 2422 return (mst != NULL && mst->type == IF_SND_TAG_TYPE_RATE_LIMIT); 2423 } 2424 #endif 2425 2426 /* 2427 * Try to allocate an mbuf to contain a raw work request. To make it 2428 * easy to construct the work request, don't allocate a chain but a 2429 * single mbuf. 2430 */ 2431 struct mbuf * 2432 alloc_wr_mbuf(int len, int how) 2433 { 2434 struct mbuf *m; 2435 2436 if (len <= MHLEN) 2437 m = m_gethdr(how, MT_DATA); 2438 else if (len <= MCLBYTES) 2439 m = m_getcl(how, MT_DATA, M_PKTHDR); 2440 else 2441 m = NULL; 2442 if (m == NULL) 2443 return (NULL); 2444 m->m_pkthdr.len = len; 2445 m->m_len = len; 2446 set_mbuf_cflags(m, MC_RAW_WR); 2447 set_mbuf_len16(m, howmany(len, 16)); 2448 return (m); 2449 } 2450 2451 static inline bool 2452 needs_hwcsum(struct mbuf *m) 2453 { 2454 const uint32_t csum_flags = CSUM_IP | CSUM_IP_UDP | CSUM_IP_TCP | 2455 CSUM_IP_TSO | CSUM_INNER_IP | CSUM_INNER_IP_UDP | 2456 CSUM_INNER_IP_TCP | CSUM_INNER_IP_TSO | CSUM_IP6_UDP | 2457 CSUM_IP6_TCP | CSUM_IP6_TSO | CSUM_INNER_IP6_UDP | 2458 CSUM_INNER_IP6_TCP | CSUM_INNER_IP6_TSO; 2459 2460 M_ASSERTPKTHDR(m); 2461 2462 return (m->m_pkthdr.csum_flags & csum_flags); 2463 } 2464 2465 static inline bool 2466 needs_tso(struct mbuf *m) 2467 { 2468 const uint32_t csum_flags = CSUM_IP_TSO | CSUM_IP6_TSO | 2469 CSUM_INNER_IP_TSO | CSUM_INNER_IP6_TSO; 2470 2471 M_ASSERTPKTHDR(m); 2472 2473 return (m->m_pkthdr.csum_flags & csum_flags); 2474 } 2475 2476 static inline bool 2477 needs_vxlan_csum(struct mbuf *m) 2478 { 2479 2480 M_ASSERTPKTHDR(m); 2481 2482 return (m->m_pkthdr.csum_flags & CSUM_ENCAP_VXLAN); 2483 } 2484 2485 static inline bool 2486 needs_vxlan_tso(struct mbuf *m) 2487 { 2488 const uint32_t csum_flags = CSUM_ENCAP_VXLAN | CSUM_INNER_IP_TSO | 2489 CSUM_INNER_IP6_TSO; 2490 2491 M_ASSERTPKTHDR(m); 2492 2493 return ((m->m_pkthdr.csum_flags & csum_flags) != 0 && 2494 (m->m_pkthdr.csum_flags & csum_flags) != CSUM_ENCAP_VXLAN); 2495 } 2496 2497 static inline bool 2498 needs_inner_tcp_csum(struct mbuf *m) 2499 { 2500 const uint32_t csum_flags = CSUM_INNER_IP_TSO | CSUM_INNER_IP6_TSO; 2501 2502 M_ASSERTPKTHDR(m); 2503 2504 return (m->m_pkthdr.csum_flags & csum_flags); 2505 } 2506 2507 static inline bool 2508 needs_l3_csum(struct mbuf *m) 2509 { 2510 const uint32_t csum_flags = CSUM_IP | CSUM_IP_TSO | CSUM_INNER_IP | 2511 CSUM_INNER_IP_TSO; 2512 2513 M_ASSERTPKTHDR(m); 2514 2515 return (m->m_pkthdr.csum_flags & csum_flags); 2516 } 2517 2518 static inline bool 2519 needs_outer_tcp_csum(struct mbuf *m) 2520 { 2521 const uint32_t csum_flags = CSUM_IP_TCP | CSUM_IP_TSO | CSUM_IP6_TCP | 2522 CSUM_IP6_TSO; 2523 2524 M_ASSERTPKTHDR(m); 2525 2526 return (m->m_pkthdr.csum_flags & csum_flags); 2527 } 2528 2529 #ifdef RATELIMIT 2530 static inline bool 2531 needs_outer_l4_csum(struct mbuf *m) 2532 { 2533 const uint32_t csum_flags = CSUM_IP_UDP | CSUM_IP_TCP | CSUM_IP_TSO | 2534 CSUM_IP6_UDP | CSUM_IP6_TCP | CSUM_IP6_TSO; 2535 2536 M_ASSERTPKTHDR(m); 2537 2538 return (m->m_pkthdr.csum_flags & csum_flags); 2539 } 2540 2541 static inline bool 2542 needs_outer_udp_csum(struct mbuf *m) 2543 { 2544 const uint32_t csum_flags = CSUM_IP_UDP | CSUM_IP6_UDP; 2545 2546 M_ASSERTPKTHDR(m); 2547 2548 return (m->m_pkthdr.csum_flags & csum_flags); 2549 } 2550 #endif 2551 2552 static inline bool 2553 needs_vlan_insertion(struct mbuf *m) 2554 { 2555 2556 M_ASSERTPKTHDR(m); 2557 2558 return (m->m_flags & M_VLANTAG); 2559 } 2560 2561 static void * 2562 m_advance(struct mbuf **pm, int *poffset, int len) 2563 { 2564 struct mbuf *m = *pm; 2565 int offset = *poffset; 2566 uintptr_t p = 0; 2567 2568 MPASS(len > 0); 2569 2570 for (;;) { 2571 if (offset + len < m->m_len) { 2572 offset += len; 2573 p = mtod(m, uintptr_t) + offset; 2574 break; 2575 } 2576 len -= m->m_len - offset; 2577 m = m->m_next; 2578 offset = 0; 2579 MPASS(m != NULL); 2580 } 2581 *poffset = offset; 2582 *pm = m; 2583 return ((void *)p); 2584 } 2585 2586 static inline int 2587 count_mbuf_ext_pgs(struct mbuf *m, int skip, vm_paddr_t *nextaddr) 2588 { 2589 vm_paddr_t paddr; 2590 int i, len, off, pglen, pgoff, seglen, segoff; 2591 int nsegs = 0; 2592 2593 M_ASSERTEXTPG(m); 2594 off = mtod(m, vm_offset_t); 2595 len = m->m_len; 2596 off += skip; 2597 len -= skip; 2598 2599 if (m->m_epg_hdrlen != 0) { 2600 if (off >= m->m_epg_hdrlen) { 2601 off -= m->m_epg_hdrlen; 2602 } else { 2603 seglen = m->m_epg_hdrlen - off; 2604 segoff = off; 2605 seglen = min(seglen, len); 2606 off = 0; 2607 len -= seglen; 2608 paddr = pmap_kextract( 2609 (vm_offset_t)&m->m_epg_hdr[segoff]); 2610 if (*nextaddr != paddr) 2611 nsegs++; 2612 *nextaddr = paddr + seglen; 2613 } 2614 } 2615 pgoff = m->m_epg_1st_off; 2616 for (i = 0; i < m->m_epg_npgs && len > 0; i++) { 2617 pglen = m_epg_pagelen(m, i, pgoff); 2618 if (off >= pglen) { 2619 off -= pglen; 2620 pgoff = 0; 2621 continue; 2622 } 2623 seglen = pglen - off; 2624 segoff = pgoff + off; 2625 off = 0; 2626 seglen = min(seglen, len); 2627 len -= seglen; 2628 paddr = m->m_epg_pa[i] + segoff; 2629 if (*nextaddr != paddr) 2630 nsegs++; 2631 *nextaddr = paddr + seglen; 2632 pgoff = 0; 2633 }; 2634 if (len != 0) { 2635 seglen = min(len, m->m_epg_trllen - off); 2636 len -= seglen; 2637 paddr = pmap_kextract((vm_offset_t)&m->m_epg_trail[off]); 2638 if (*nextaddr != paddr) 2639 nsegs++; 2640 *nextaddr = paddr + seglen; 2641 } 2642 2643 return (nsegs); 2644 } 2645 2646 2647 /* 2648 * Can deal with empty mbufs in the chain that have m_len = 0, but the chain 2649 * must have at least one mbuf that's not empty. It is possible for this 2650 * routine to return 0 if skip accounts for all the contents of the mbuf chain. 2651 */ 2652 static inline int 2653 count_mbuf_nsegs(struct mbuf *m, int skip, uint8_t *cflags) 2654 { 2655 vm_paddr_t nextaddr, paddr; 2656 vm_offset_t va; 2657 int len, nsegs; 2658 2659 M_ASSERTPKTHDR(m); 2660 MPASS(m->m_pkthdr.len > 0); 2661 MPASS(m->m_pkthdr.len >= skip); 2662 2663 nsegs = 0; 2664 nextaddr = 0; 2665 for (; m; m = m->m_next) { 2666 len = m->m_len; 2667 if (__predict_false(len == 0)) 2668 continue; 2669 if (skip >= len) { 2670 skip -= len; 2671 continue; 2672 } 2673 if ((m->m_flags & M_EXTPG) != 0) { 2674 *cflags |= MC_NOMAP; 2675 nsegs += count_mbuf_ext_pgs(m, skip, &nextaddr); 2676 skip = 0; 2677 continue; 2678 } 2679 va = mtod(m, vm_offset_t) + skip; 2680 len -= skip; 2681 skip = 0; 2682 paddr = pmap_kextract(va); 2683 nsegs += sglist_count((void *)(uintptr_t)va, len); 2684 if (paddr == nextaddr) 2685 nsegs--; 2686 nextaddr = pmap_kextract(va + len - 1) + 1; 2687 } 2688 2689 return (nsegs); 2690 } 2691 2692 /* 2693 * The maximum number of segments that can fit in a WR. 2694 */ 2695 static int 2696 max_nsegs_allowed(struct mbuf *m, bool vm_wr) 2697 { 2698 2699 if (vm_wr) { 2700 if (needs_tso(m)) 2701 return (TX_SGL_SEGS_VM_TSO); 2702 return (TX_SGL_SEGS_VM); 2703 } 2704 2705 if (needs_tso(m)) { 2706 if (needs_vxlan_tso(m)) 2707 return (TX_SGL_SEGS_VXLAN_TSO); 2708 else 2709 return (TX_SGL_SEGS_TSO); 2710 } 2711 2712 return (TX_SGL_SEGS); 2713 } 2714 2715 /* 2716 * Analyze the mbuf to determine its tx needs. The mbuf passed in may change: 2717 * a) caller can assume it's been freed if this function returns with an error. 2718 * b) it may get defragged up if the gather list is too long for the hardware. 2719 */ 2720 int 2721 parse_pkt(struct mbuf **mp, bool vm_wr) 2722 { 2723 struct mbuf *m0 = *mp, *m; 2724 int rc, nsegs, defragged = 0, offset; 2725 struct ether_header *eh; 2726 void *l3hdr; 2727 #if defined(INET) || defined(INET6) 2728 struct tcphdr *tcp; 2729 #endif 2730 #if defined(KERN_TLS) || defined(RATELIMIT) 2731 struct m_snd_tag *mst; 2732 #endif 2733 uint16_t eh_type; 2734 uint8_t cflags; 2735 2736 cflags = 0; 2737 M_ASSERTPKTHDR(m0); 2738 if (__predict_false(m0->m_pkthdr.len < ETHER_HDR_LEN)) { 2739 rc = EINVAL; 2740 fail: 2741 m_freem(m0); 2742 *mp = NULL; 2743 return (rc); 2744 } 2745 restart: 2746 /* 2747 * First count the number of gather list segments in the payload. 2748 * Defrag the mbuf if nsegs exceeds the hardware limit. 2749 */ 2750 M_ASSERTPKTHDR(m0); 2751 MPASS(m0->m_pkthdr.len > 0); 2752 nsegs = count_mbuf_nsegs(m0, 0, &cflags); 2753 #if defined(KERN_TLS) || defined(RATELIMIT) 2754 if (m0->m_pkthdr.csum_flags & CSUM_SND_TAG) 2755 mst = m0->m_pkthdr.snd_tag; 2756 else 2757 mst = NULL; 2758 #endif 2759 #ifdef KERN_TLS 2760 if (mst != NULL && mst->type == IF_SND_TAG_TYPE_TLS) { 2761 int len16; 2762 2763 cflags |= MC_TLS; 2764 set_mbuf_cflags(m0, cflags); 2765 rc = t6_ktls_parse_pkt(m0, &nsegs, &len16); 2766 if (rc != 0) 2767 goto fail; 2768 set_mbuf_nsegs(m0, nsegs); 2769 set_mbuf_len16(m0, len16); 2770 return (0); 2771 } 2772 #endif 2773 if (nsegs > max_nsegs_allowed(m0, vm_wr)) { 2774 if (defragged++ > 0) { 2775 rc = EFBIG; 2776 goto fail; 2777 } 2778 counter_u64_add(defrags, 1); 2779 if ((m = m_defrag(m0, M_NOWAIT)) == NULL) { 2780 rc = ENOMEM; 2781 goto fail; 2782 } 2783 *mp = m0 = m; /* update caller's copy after defrag */ 2784 goto restart; 2785 } 2786 2787 if (__predict_false(nsegs > 2 && m0->m_pkthdr.len <= MHLEN && 2788 !(cflags & MC_NOMAP))) { 2789 counter_u64_add(pullups, 1); 2790 m0 = m_pullup(m0, m0->m_pkthdr.len); 2791 if (m0 == NULL) { 2792 /* Should have left well enough alone. */ 2793 rc = EFBIG; 2794 goto fail; 2795 } 2796 *mp = m0; /* update caller's copy after pullup */ 2797 goto restart; 2798 } 2799 set_mbuf_nsegs(m0, nsegs); 2800 set_mbuf_cflags(m0, cflags); 2801 calculate_mbuf_len16(m0, vm_wr); 2802 2803 #ifdef RATELIMIT 2804 /* 2805 * Ethofld is limited to TCP and UDP for now, and only when L4 hw 2806 * checksumming is enabled. needs_outer_l4_csum happens to check for 2807 * all the right things. 2808 */ 2809 if (__predict_false(needs_eo(mst) && !needs_outer_l4_csum(m0))) { 2810 m_snd_tag_rele(m0->m_pkthdr.snd_tag); 2811 m0->m_pkthdr.snd_tag = NULL; 2812 m0->m_pkthdr.csum_flags &= ~CSUM_SND_TAG; 2813 mst = NULL; 2814 } 2815 #endif 2816 2817 if (!needs_hwcsum(m0) 2818 #ifdef RATELIMIT 2819 && !needs_eo(mst) 2820 #endif 2821 ) 2822 return (0); 2823 2824 m = m0; 2825 eh = mtod(m, struct ether_header *); 2826 eh_type = ntohs(eh->ether_type); 2827 if (eh_type == ETHERTYPE_VLAN) { 2828 struct ether_vlan_header *evh = (void *)eh; 2829 2830 eh_type = ntohs(evh->evl_proto); 2831 m0->m_pkthdr.l2hlen = sizeof(*evh); 2832 } else 2833 m0->m_pkthdr.l2hlen = sizeof(*eh); 2834 2835 offset = 0; 2836 l3hdr = m_advance(&m, &offset, m0->m_pkthdr.l2hlen); 2837 2838 switch (eh_type) { 2839 #ifdef INET6 2840 case ETHERTYPE_IPV6: 2841 m0->m_pkthdr.l3hlen = sizeof(struct ip6_hdr); 2842 break; 2843 #endif 2844 #ifdef INET 2845 case ETHERTYPE_IP: 2846 { 2847 struct ip *ip = l3hdr; 2848 2849 if (needs_vxlan_csum(m0)) { 2850 /* Driver will do the outer IP hdr checksum. */ 2851 ip->ip_sum = 0; 2852 if (needs_vxlan_tso(m0)) { 2853 const uint16_t ipl = ip->ip_len; 2854 2855 ip->ip_len = 0; 2856 ip->ip_sum = ~in_cksum_hdr(ip); 2857 ip->ip_len = ipl; 2858 } else 2859 ip->ip_sum = in_cksum_hdr(ip); 2860 } 2861 m0->m_pkthdr.l3hlen = ip->ip_hl << 2; 2862 break; 2863 } 2864 #endif 2865 default: 2866 panic("%s: ethertype 0x%04x unknown. if_cxgbe must be compiled" 2867 " with the same INET/INET6 options as the kernel.", 2868 __func__, eh_type); 2869 } 2870 2871 if (needs_vxlan_csum(m0)) { 2872 m0->m_pkthdr.l4hlen = sizeof(struct udphdr); 2873 m0->m_pkthdr.l5hlen = sizeof(struct vxlan_header); 2874 2875 /* Inner headers. */ 2876 eh = m_advance(&m, &offset, m0->m_pkthdr.l3hlen + 2877 sizeof(struct udphdr) + sizeof(struct vxlan_header)); 2878 eh_type = ntohs(eh->ether_type); 2879 if (eh_type == ETHERTYPE_VLAN) { 2880 struct ether_vlan_header *evh = (void *)eh; 2881 2882 eh_type = ntohs(evh->evl_proto); 2883 m0->m_pkthdr.inner_l2hlen = sizeof(*evh); 2884 } else 2885 m0->m_pkthdr.inner_l2hlen = sizeof(*eh); 2886 l3hdr = m_advance(&m, &offset, m0->m_pkthdr.inner_l2hlen); 2887 2888 switch (eh_type) { 2889 #ifdef INET6 2890 case ETHERTYPE_IPV6: 2891 m0->m_pkthdr.inner_l3hlen = sizeof(struct ip6_hdr); 2892 break; 2893 #endif 2894 #ifdef INET 2895 case ETHERTYPE_IP: 2896 { 2897 struct ip *ip = l3hdr; 2898 2899 m0->m_pkthdr.inner_l3hlen = ip->ip_hl << 2; 2900 break; 2901 } 2902 #endif 2903 default: 2904 panic("%s: VXLAN hw offload requested with unknown " 2905 "ethertype 0x%04x. if_cxgbe must be compiled" 2906 " with the same INET/INET6 options as the kernel.", 2907 __func__, eh_type); 2908 } 2909 #if defined(INET) || defined(INET6) 2910 if (needs_inner_tcp_csum(m0)) { 2911 tcp = m_advance(&m, &offset, m0->m_pkthdr.inner_l3hlen); 2912 m0->m_pkthdr.inner_l4hlen = tcp->th_off * 4; 2913 } 2914 #endif 2915 MPASS((m0->m_pkthdr.csum_flags & CSUM_SND_TAG) == 0); 2916 m0->m_pkthdr.csum_flags &= CSUM_INNER_IP6_UDP | 2917 CSUM_INNER_IP6_TCP | CSUM_INNER_IP6_TSO | CSUM_INNER_IP | 2918 CSUM_INNER_IP_UDP | CSUM_INNER_IP_TCP | CSUM_INNER_IP_TSO | 2919 CSUM_ENCAP_VXLAN; 2920 } 2921 2922 #if defined(INET) || defined(INET6) 2923 if (needs_outer_tcp_csum(m0)) { 2924 tcp = m_advance(&m, &offset, m0->m_pkthdr.l3hlen); 2925 m0->m_pkthdr.l4hlen = tcp->th_off * 4; 2926 #ifdef RATELIMIT 2927 if (tsclk >= 0 && *(uint32_t *)(tcp + 1) == ntohl(0x0101080a)) { 2928 set_mbuf_eo_tsclk_tsoff(m0, 2929 V_FW_ETH_TX_EO_WR_TSCLK(tsclk) | 2930 V_FW_ETH_TX_EO_WR_TSOFF(sizeof(*tcp) / 2 + 1)); 2931 } else 2932 set_mbuf_eo_tsclk_tsoff(m0, 0); 2933 } else if (needs_outer_udp_csum(m0)) { 2934 m0->m_pkthdr.l4hlen = sizeof(struct udphdr); 2935 #endif 2936 } 2937 #ifdef RATELIMIT 2938 if (needs_eo(mst)) { 2939 u_int immhdrs; 2940 2941 /* EO WRs have the headers in the WR and not the GL. */ 2942 immhdrs = m0->m_pkthdr.l2hlen + m0->m_pkthdr.l3hlen + 2943 m0->m_pkthdr.l4hlen; 2944 cflags = 0; 2945 nsegs = count_mbuf_nsegs(m0, immhdrs, &cflags); 2946 MPASS(cflags == mbuf_cflags(m0)); 2947 set_mbuf_eo_nsegs(m0, nsegs); 2948 set_mbuf_eo_len16(m0, 2949 txpkt_eo_len16(nsegs, immhdrs, needs_tso(m0))); 2950 } 2951 #endif 2952 #endif 2953 MPASS(m0 == *mp); 2954 return (0); 2955 } 2956 2957 void * 2958 start_wrq_wr(struct sge_wrq *wrq, int len16, struct wrq_cookie *cookie) 2959 { 2960 struct sge_eq *eq = &wrq->eq; 2961 struct adapter *sc = wrq->adapter; 2962 int ndesc, available; 2963 struct wrqe *wr; 2964 void *w; 2965 2966 MPASS(len16 > 0); 2967 ndesc = tx_len16_to_desc(len16); 2968 MPASS(ndesc > 0 && ndesc <= SGE_MAX_WR_NDESC); 2969 2970 EQ_LOCK(eq); 2971 2972 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 2973 drain_wrq_wr_list(sc, wrq); 2974 2975 if (!STAILQ_EMPTY(&wrq->wr_list)) { 2976 slowpath: 2977 EQ_UNLOCK(eq); 2978 wr = alloc_wrqe(len16 * 16, wrq); 2979 if (__predict_false(wr == NULL)) 2980 return (NULL); 2981 cookie->pidx = -1; 2982 cookie->ndesc = ndesc; 2983 return (&wr->wr); 2984 } 2985 2986 eq->cidx = read_hw_cidx(eq); 2987 if (eq->pidx == eq->cidx) 2988 available = eq->sidx - 1; 2989 else 2990 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2991 if (available < ndesc) 2992 goto slowpath; 2993 2994 cookie->pidx = eq->pidx; 2995 cookie->ndesc = ndesc; 2996 TAILQ_INSERT_TAIL(&wrq->incomplete_wrs, cookie, link); 2997 2998 w = &eq->desc[eq->pidx]; 2999 IDXINCR(eq->pidx, ndesc, eq->sidx); 3000 if (__predict_false(cookie->pidx + ndesc > eq->sidx)) { 3001 w = &wrq->ss[0]; 3002 wrq->ss_pidx = cookie->pidx; 3003 wrq->ss_len = len16 * 16; 3004 } 3005 3006 EQ_UNLOCK(eq); 3007 3008 return (w); 3009 } 3010 3011 void 3012 commit_wrq_wr(struct sge_wrq *wrq, void *w, struct wrq_cookie *cookie) 3013 { 3014 struct sge_eq *eq = &wrq->eq; 3015 struct adapter *sc = wrq->adapter; 3016 int ndesc, pidx; 3017 struct wrq_cookie *prev, *next; 3018 3019 if (cookie->pidx == -1) { 3020 struct wrqe *wr = __containerof(w, struct wrqe, wr); 3021 3022 t4_wrq_tx(sc, wr); 3023 return; 3024 } 3025 3026 if (__predict_false(w == &wrq->ss[0])) { 3027 int n = (eq->sidx - wrq->ss_pidx) * EQ_ESIZE; 3028 3029 MPASS(wrq->ss_len > n); /* WR had better wrap around. */ 3030 bcopy(&wrq->ss[0], &eq->desc[wrq->ss_pidx], n); 3031 bcopy(&wrq->ss[n], &eq->desc[0], wrq->ss_len - n); 3032 wrq->tx_wrs_ss++; 3033 } else 3034 wrq->tx_wrs_direct++; 3035 3036 EQ_LOCK(eq); 3037 ndesc = cookie->ndesc; /* Can be more than SGE_MAX_WR_NDESC here. */ 3038 pidx = cookie->pidx; 3039 MPASS(pidx >= 0 && pidx < eq->sidx); 3040 prev = TAILQ_PREV(cookie, wrq_incomplete_wrs, link); 3041 next = TAILQ_NEXT(cookie, link); 3042 if (prev == NULL) { 3043 MPASS(pidx == eq->dbidx); 3044 if (next == NULL || ndesc >= 16) { 3045 int available; 3046 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */ 3047 3048 /* 3049 * Note that the WR via which we'll request tx updates 3050 * is at pidx and not eq->pidx, which has moved on 3051 * already. 3052 */ 3053 dst = (void *)&eq->desc[pidx]; 3054 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 3055 if (available < eq->sidx / 4 && 3056 atomic_cmpset_int(&eq->equiq, 0, 1)) { 3057 /* 3058 * XXX: This is not 100% reliable with some 3059 * types of WRs. But this is a very unusual 3060 * situation for an ofld/ctrl queue anyway. 3061 */ 3062 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ | 3063 F_FW_WR_EQUEQ); 3064 } 3065 3066 ring_eq_db(wrq->adapter, eq, ndesc); 3067 } else { 3068 MPASS(IDXDIFF(next->pidx, pidx, eq->sidx) == ndesc); 3069 next->pidx = pidx; 3070 next->ndesc += ndesc; 3071 } 3072 } else { 3073 MPASS(IDXDIFF(pidx, prev->pidx, eq->sidx) == prev->ndesc); 3074 prev->ndesc += ndesc; 3075 } 3076 TAILQ_REMOVE(&wrq->incomplete_wrs, cookie, link); 3077 3078 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 3079 drain_wrq_wr_list(sc, wrq); 3080 3081 #ifdef INVARIANTS 3082 if (TAILQ_EMPTY(&wrq->incomplete_wrs)) { 3083 /* Doorbell must have caught up to the pidx. */ 3084 MPASS(wrq->eq.pidx == wrq->eq.dbidx); 3085 } 3086 #endif 3087 EQ_UNLOCK(eq); 3088 } 3089 3090 static u_int 3091 can_resume_eth_tx(struct mp_ring *r) 3092 { 3093 struct sge_eq *eq = r->cookie; 3094 3095 return (total_available_tx_desc(eq) > eq->sidx / 8); 3096 } 3097 3098 static inline bool 3099 cannot_use_txpkts(struct mbuf *m) 3100 { 3101 /* maybe put a GL limit too, to avoid silliness? */ 3102 3103 return (needs_tso(m) || (mbuf_cflags(m) & (MC_RAW_WR | MC_TLS)) != 0); 3104 } 3105 3106 static inline int 3107 discard_tx(struct sge_eq *eq) 3108 { 3109 3110 return ((eq->flags & (EQ_ENABLED | EQ_QFLUSH)) != EQ_ENABLED); 3111 } 3112 3113 static inline int 3114 wr_can_update_eq(void *p) 3115 { 3116 struct fw_eth_tx_pkts_wr *wr = p; 3117 3118 switch (G_FW_WR_OP(be32toh(wr->op_pkd))) { 3119 case FW_ULPTX_WR: 3120 case FW_ETH_TX_PKT_WR: 3121 case FW_ETH_TX_PKTS_WR: 3122 case FW_ETH_TX_PKTS2_WR: 3123 case FW_ETH_TX_PKT_VM_WR: 3124 case FW_ETH_TX_PKTS_VM_WR: 3125 return (1); 3126 default: 3127 return (0); 3128 } 3129 } 3130 3131 static inline void 3132 set_txupdate_flags(struct sge_txq *txq, u_int avail, 3133 struct fw_eth_tx_pkt_wr *wr) 3134 { 3135 struct sge_eq *eq = &txq->eq; 3136 struct txpkts *txp = &txq->txp; 3137 3138 if ((txp->npkt > 0 || avail < eq->sidx / 2) && 3139 atomic_cmpset_int(&eq->equiq, 0, 1)) { 3140 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ | F_FW_WR_EQUIQ); 3141 eq->equeqidx = eq->pidx; 3142 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 32) { 3143 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ); 3144 eq->equeqidx = eq->pidx; 3145 } 3146 } 3147 3148 #if defined(__i386__) || defined(__amd64__) 3149 extern uint64_t tsc_freq; 3150 #endif 3151 3152 static inline bool 3153 record_eth_tx_time(struct sge_txq *txq) 3154 { 3155 const uint64_t cycles = get_cyclecount(); 3156 const uint64_t last_tx = txq->last_tx; 3157 #if defined(__i386__) || defined(__amd64__) 3158 const uint64_t itg = tsc_freq * t4_tx_coalesce_gap / 1000000; 3159 #else 3160 const uint64_t itg = 0; 3161 #endif 3162 3163 MPASS(cycles >= last_tx); 3164 txq->last_tx = cycles; 3165 return (cycles - last_tx < itg); 3166 } 3167 3168 /* 3169 * r->items[cidx] to r->items[pidx], with a wraparound at r->size, are ready to 3170 * be consumed. Return the actual number consumed. 0 indicates a stall. 3171 */ 3172 static u_int 3173 eth_tx(struct mp_ring *r, u_int cidx, u_int pidx, bool *coalescing) 3174 { 3175 struct sge_txq *txq = r->cookie; 3176 struct ifnet *ifp = txq->ifp; 3177 struct sge_eq *eq = &txq->eq; 3178 struct txpkts *txp = &txq->txp; 3179 struct vi_info *vi = ifp->if_softc; 3180 struct adapter *sc = vi->adapter; 3181 u_int total, remaining; /* # of packets */ 3182 u_int n, avail, dbdiff; /* # of hardware descriptors */ 3183 int i, rc; 3184 struct mbuf *m0; 3185 bool snd, recent_tx; 3186 void *wr; /* start of the last WR written to the ring */ 3187 3188 TXQ_LOCK_ASSERT_OWNED(txq); 3189 recent_tx = record_eth_tx_time(txq); 3190 3191 remaining = IDXDIFF(pidx, cidx, r->size); 3192 if (__predict_false(discard_tx(eq))) { 3193 for (i = 0; i < txp->npkt; i++) 3194 m_freem(txp->mb[i]); 3195 txp->npkt = 0; 3196 while (cidx != pidx) { 3197 m0 = r->items[cidx]; 3198 m_freem(m0); 3199 if (++cidx == r->size) 3200 cidx = 0; 3201 } 3202 reclaim_tx_descs(txq, eq->sidx); 3203 *coalescing = false; 3204 return (remaining); /* emptied */ 3205 } 3206 3207 /* How many hardware descriptors do we have readily available. */ 3208 if (eq->pidx == eq->cidx) 3209 avail = eq->sidx - 1; 3210 else 3211 avail = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 3212 3213 total = 0; 3214 if (remaining == 0) { 3215 txp->score = 0; 3216 txq->txpkts_flush++; 3217 goto send_txpkts; 3218 } 3219 3220 dbdiff = 0; 3221 MPASS(remaining > 0); 3222 while (remaining > 0) { 3223 m0 = r->items[cidx]; 3224 M_ASSERTPKTHDR(m0); 3225 MPASS(m0->m_nextpkt == NULL); 3226 3227 if (avail < 2 * SGE_MAX_WR_NDESC) 3228 avail += reclaim_tx_descs(txq, 64); 3229 3230 if (t4_tx_coalesce == 0 && txp->npkt == 0) 3231 goto skip_coalescing; 3232 if (cannot_use_txpkts(m0)) 3233 txp->score = 0; 3234 else if (recent_tx) { 3235 if (++txp->score == 0) 3236 txp->score = UINT8_MAX; 3237 } else 3238 txp->score = 1; 3239 if (txp->npkt > 0 || remaining > 1 || 3240 txp->score >= t4_tx_coalesce_pkts || 3241 atomic_load_int(&txq->eq.equiq) != 0) { 3242 if (vi->flags & TX_USES_VM_WR) 3243 rc = add_to_txpkts_vf(sc, txq, m0, avail, &snd); 3244 else 3245 rc = add_to_txpkts_pf(sc, txq, m0, avail, &snd); 3246 } else { 3247 snd = false; 3248 rc = EINVAL; 3249 } 3250 if (snd) { 3251 MPASS(txp->npkt > 0); 3252 for (i = 0; i < txp->npkt; i++) 3253 ETHER_BPF_MTAP(ifp, txp->mb[i]); 3254 if (txp->npkt > 1) { 3255 MPASS(avail >= tx_len16_to_desc(txp->len16)); 3256 if (vi->flags & TX_USES_VM_WR) 3257 n = write_txpkts_vm_wr(sc, txq); 3258 else 3259 n = write_txpkts_wr(sc, txq); 3260 } else { 3261 MPASS(avail >= 3262 tx_len16_to_desc(mbuf_len16(txp->mb[0]))); 3263 if (vi->flags & TX_USES_VM_WR) 3264 n = write_txpkt_vm_wr(sc, txq, 3265 txp->mb[0]); 3266 else 3267 n = write_txpkt_wr(sc, txq, txp->mb[0], 3268 avail); 3269 } 3270 MPASS(n <= SGE_MAX_WR_NDESC); 3271 avail -= n; 3272 dbdiff += n; 3273 wr = &eq->desc[eq->pidx]; 3274 IDXINCR(eq->pidx, n, eq->sidx); 3275 txp->npkt = 0; /* emptied */ 3276 } 3277 if (rc == 0) { 3278 /* m0 was coalesced into txq->txpkts. */ 3279 goto next_mbuf; 3280 } 3281 if (rc == EAGAIN) { 3282 /* 3283 * m0 is suitable for tx coalescing but could not be 3284 * combined with the existing txq->txpkts, which has now 3285 * been transmitted. Start a new txpkts with m0. 3286 */ 3287 MPASS(snd); 3288 MPASS(txp->npkt == 0); 3289 continue; 3290 } 3291 3292 MPASS(rc != 0 && rc != EAGAIN); 3293 MPASS(txp->npkt == 0); 3294 skip_coalescing: 3295 n = tx_len16_to_desc(mbuf_len16(m0)); 3296 if (__predict_false(avail < n)) { 3297 avail += reclaim_tx_descs(txq, min(n, 32)); 3298 if (avail < n) 3299 break; /* out of descriptors */ 3300 } 3301 3302 wr = &eq->desc[eq->pidx]; 3303 if (mbuf_cflags(m0) & MC_RAW_WR) { 3304 n = write_raw_wr(txq, wr, m0, avail); 3305 #ifdef KERN_TLS 3306 } else if (mbuf_cflags(m0) & MC_TLS) { 3307 ETHER_BPF_MTAP(ifp, m0); 3308 n = t6_ktls_write_wr(txq, wr, m0, mbuf_nsegs(m0), 3309 avail); 3310 #endif 3311 } else { 3312 ETHER_BPF_MTAP(ifp, m0); 3313 if (vi->flags & TX_USES_VM_WR) 3314 n = write_txpkt_vm_wr(sc, txq, m0); 3315 else 3316 n = write_txpkt_wr(sc, txq, m0, avail); 3317 } 3318 MPASS(n >= 1 && n <= avail); 3319 if (!(mbuf_cflags(m0) & MC_TLS)) 3320 MPASS(n <= SGE_MAX_WR_NDESC); 3321 3322 avail -= n; 3323 dbdiff += n; 3324 IDXINCR(eq->pidx, n, eq->sidx); 3325 3326 if (dbdiff >= 512 / EQ_ESIZE) { /* X_FETCHBURSTMAX_512B */ 3327 if (wr_can_update_eq(wr)) 3328 set_txupdate_flags(txq, avail, wr); 3329 ring_eq_db(sc, eq, dbdiff); 3330 avail += reclaim_tx_descs(txq, 32); 3331 dbdiff = 0; 3332 } 3333 next_mbuf: 3334 total++; 3335 remaining--; 3336 if (__predict_false(++cidx == r->size)) 3337 cidx = 0; 3338 } 3339 if (dbdiff != 0) { 3340 if (wr_can_update_eq(wr)) 3341 set_txupdate_flags(txq, avail, wr); 3342 ring_eq_db(sc, eq, dbdiff); 3343 reclaim_tx_descs(txq, 32); 3344 } else if (eq->pidx == eq->cidx && txp->npkt > 0 && 3345 atomic_load_int(&txq->eq.equiq) == 0) { 3346 /* 3347 * If nothing was submitted to the chip for tx (it was coalesced 3348 * into txpkts instead) and there is no tx update outstanding 3349 * then we need to send txpkts now. 3350 */ 3351 send_txpkts: 3352 MPASS(txp->npkt > 0); 3353 for (i = 0; i < txp->npkt; i++) 3354 ETHER_BPF_MTAP(ifp, txp->mb[i]); 3355 if (txp->npkt > 1) { 3356 MPASS(avail >= tx_len16_to_desc(txp->len16)); 3357 if (vi->flags & TX_USES_VM_WR) 3358 n = write_txpkts_vm_wr(sc, txq); 3359 else 3360 n = write_txpkts_wr(sc, txq); 3361 } else { 3362 MPASS(avail >= 3363 tx_len16_to_desc(mbuf_len16(txp->mb[0]))); 3364 if (vi->flags & TX_USES_VM_WR) 3365 n = write_txpkt_vm_wr(sc, txq, txp->mb[0]); 3366 else 3367 n = write_txpkt_wr(sc, txq, txp->mb[0], avail); 3368 } 3369 MPASS(n <= SGE_MAX_WR_NDESC); 3370 wr = &eq->desc[eq->pidx]; 3371 IDXINCR(eq->pidx, n, eq->sidx); 3372 txp->npkt = 0; /* emptied */ 3373 3374 MPASS(wr_can_update_eq(wr)); 3375 set_txupdate_flags(txq, avail - n, wr); 3376 ring_eq_db(sc, eq, n); 3377 reclaim_tx_descs(txq, 32); 3378 } 3379 *coalescing = txp->npkt > 0; 3380 3381 return (total); 3382 } 3383 3384 static inline void 3385 init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int pktc_idx, 3386 int qsize) 3387 { 3388 3389 KASSERT(tmr_idx >= 0 && tmr_idx < SGE_NTIMERS, 3390 ("%s: bad tmr_idx %d", __func__, tmr_idx)); 3391 KASSERT(pktc_idx < SGE_NCOUNTERS, /* -ve is ok, means don't use */ 3392 ("%s: bad pktc_idx %d", __func__, pktc_idx)); 3393 3394 iq->flags = 0; 3395 iq->adapter = sc; 3396 iq->intr_params = V_QINTR_TIMER_IDX(tmr_idx); 3397 iq->intr_pktc_idx = SGE_NCOUNTERS - 1; 3398 if (pktc_idx >= 0) { 3399 iq->intr_params |= F_QINTR_CNT_EN; 3400 iq->intr_pktc_idx = pktc_idx; 3401 } 3402 iq->qsize = roundup2(qsize, 16); /* See FW_IQ_CMD/iqsize */ 3403 iq->sidx = iq->qsize - sc->params.sge.spg_len / IQ_ESIZE; 3404 } 3405 3406 static inline void 3407 init_fl(struct adapter *sc, struct sge_fl *fl, int qsize, int maxp, char *name) 3408 { 3409 3410 fl->qsize = qsize; 3411 fl->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE; 3412 strlcpy(fl->lockname, name, sizeof(fl->lockname)); 3413 if (sc->flags & BUF_PACKING_OK && 3414 ((!is_t4(sc) && buffer_packing) || /* T5+: enabled unless 0 */ 3415 (is_t4(sc) && buffer_packing == 1)))/* T4: disabled unless 1 */ 3416 fl->flags |= FL_BUF_PACKING; 3417 fl->zidx = find_refill_source(sc, maxp, fl->flags & FL_BUF_PACKING); 3418 fl->safe_zidx = sc->sge.safe_zidx; 3419 } 3420 3421 static inline void 3422 init_eq(struct adapter *sc, struct sge_eq *eq, int eqtype, int qsize, 3423 uint8_t tx_chan, uint16_t iqid, char *name) 3424 { 3425 KASSERT(eqtype <= EQ_TYPEMASK, ("%s: bad qtype %d", __func__, eqtype)); 3426 3427 eq->flags = eqtype & EQ_TYPEMASK; 3428 eq->tx_chan = tx_chan; 3429 eq->iqid = iqid; 3430 eq->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE; 3431 strlcpy(eq->lockname, name, sizeof(eq->lockname)); 3432 } 3433 3434 int 3435 alloc_ring(struct adapter *sc, size_t len, bus_dma_tag_t *tag, 3436 bus_dmamap_t *map, bus_addr_t *pa, void **va) 3437 { 3438 int rc; 3439 3440 rc = bus_dma_tag_create(sc->dmat, 512, 0, BUS_SPACE_MAXADDR, 3441 BUS_SPACE_MAXADDR, NULL, NULL, len, 1, len, 0, NULL, NULL, tag); 3442 if (rc != 0) { 3443 device_printf(sc->dev, "cannot allocate DMA tag: %d\n", rc); 3444 goto done; 3445 } 3446 3447 rc = bus_dmamem_alloc(*tag, va, 3448 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, map); 3449 if (rc != 0) { 3450 device_printf(sc->dev, "cannot allocate DMA memory: %d\n", rc); 3451 goto done; 3452 } 3453 3454 rc = bus_dmamap_load(*tag, *map, *va, len, oneseg_dma_callback, pa, 0); 3455 if (rc != 0) { 3456 device_printf(sc->dev, "cannot load DMA map: %d\n", rc); 3457 goto done; 3458 } 3459 done: 3460 if (rc) 3461 free_ring(sc, *tag, *map, *pa, *va); 3462 3463 return (rc); 3464 } 3465 3466 int 3467 free_ring(struct adapter *sc, bus_dma_tag_t tag, bus_dmamap_t map, 3468 bus_addr_t pa, void *va) 3469 { 3470 if (pa) 3471 bus_dmamap_unload(tag, map); 3472 if (va) 3473 bus_dmamem_free(tag, va, map); 3474 if (tag) 3475 bus_dma_tag_destroy(tag); 3476 3477 return (0); 3478 } 3479 3480 /* 3481 * Allocates the ring for an ingress queue and an optional freelist. If the 3482 * freelist is specified it will be allocated and then associated with the 3483 * ingress queue. 3484 * 3485 * Returns errno on failure. Resources allocated up to that point may still be 3486 * allocated. Caller is responsible for cleanup in case this function fails. 3487 * 3488 * If the ingress queue will take interrupts directly then the intr_idx 3489 * specifies the vector, starting from 0. -1 means the interrupts for this 3490 * queue should be forwarded to the fwq. 3491 */ 3492 static int 3493 alloc_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl, 3494 int intr_idx, int cong) 3495 { 3496 int rc, i, cntxt_id; 3497 size_t len; 3498 struct fw_iq_cmd c; 3499 struct port_info *pi = vi->pi; 3500 struct adapter *sc = iq->adapter; 3501 struct sge_params *sp = &sc->params.sge; 3502 __be32 v = 0; 3503 3504 len = iq->qsize * IQ_ESIZE; 3505 rc = alloc_ring(sc, len, &iq->desc_tag, &iq->desc_map, &iq->ba, 3506 (void **)&iq->desc); 3507 if (rc != 0) 3508 return (rc); 3509 3510 bzero(&c, sizeof(c)); 3511 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 3512 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) | 3513 V_FW_IQ_CMD_VFN(0)); 3514 3515 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART | 3516 FW_LEN16(c)); 3517 3518 /* Special handling for firmware event queue */ 3519 if (iq == &sc->sge.fwq) 3520 v |= F_FW_IQ_CMD_IQASYNCH; 3521 3522 if (intr_idx < 0) { 3523 /* Forwarded interrupts, all headed to fwq */ 3524 v |= F_FW_IQ_CMD_IQANDST; 3525 v |= V_FW_IQ_CMD_IQANDSTINDEX(sc->sge.fwq.cntxt_id); 3526 } else { 3527 KASSERT(intr_idx < sc->intr_count, 3528 ("%s: invalid direct intr_idx %d", __func__, intr_idx)); 3529 v |= V_FW_IQ_CMD_IQANDSTINDEX(intr_idx); 3530 } 3531 3532 c.type_to_iqandstindex = htobe32(v | 3533 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) | 3534 V_FW_IQ_CMD_VIID(vi->viid) | 3535 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT)); 3536 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->tx_chan) | 3537 F_FW_IQ_CMD_IQGTSMODE | 3538 V_FW_IQ_CMD_IQINTCNTTHRESH(iq->intr_pktc_idx) | 3539 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4)); 3540 c.iqsize = htobe16(iq->qsize); 3541 c.iqaddr = htobe64(iq->ba); 3542 if (cong >= 0) 3543 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN); 3544 3545 if (fl) { 3546 mtx_init(&fl->fl_lock, fl->lockname, NULL, MTX_DEF); 3547 3548 len = fl->qsize * EQ_ESIZE; 3549 rc = alloc_ring(sc, len, &fl->desc_tag, &fl->desc_map, 3550 &fl->ba, (void **)&fl->desc); 3551 if (rc) 3552 return (rc); 3553 3554 /* Allocate space for one software descriptor per buffer. */ 3555 rc = alloc_fl_sdesc(fl); 3556 if (rc != 0) { 3557 device_printf(sc->dev, 3558 "failed to setup fl software descriptors: %d\n", 3559 rc); 3560 return (rc); 3561 } 3562 3563 if (fl->flags & FL_BUF_PACKING) { 3564 fl->lowat = roundup2(sp->fl_starve_threshold2, 8); 3565 fl->buf_boundary = sp->pack_boundary; 3566 } else { 3567 fl->lowat = roundup2(sp->fl_starve_threshold, 8); 3568 fl->buf_boundary = 16; 3569 } 3570 if (fl_pad && fl->buf_boundary < sp->pad_boundary) 3571 fl->buf_boundary = sp->pad_boundary; 3572 3573 c.iqns_to_fl0congen |= 3574 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) | 3575 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO | 3576 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) | 3577 (fl->flags & FL_BUF_PACKING ? F_FW_IQ_CMD_FL0PACKEN : 3578 0)); 3579 if (cong >= 0) { 3580 c.iqns_to_fl0congen |= 3581 htobe32(V_FW_IQ_CMD_FL0CNGCHMAP(cong) | 3582 F_FW_IQ_CMD_FL0CONGCIF | 3583 F_FW_IQ_CMD_FL0CONGEN); 3584 } 3585 c.fl0dcaen_to_fl0cidxfthresh = 3586 htobe16(V_FW_IQ_CMD_FL0FBMIN(chip_id(sc) <= CHELSIO_T5 ? 3587 X_FETCHBURSTMIN_128B : X_FETCHBURSTMIN_64B_T6) | 3588 V_FW_IQ_CMD_FL0FBMAX(chip_id(sc) <= CHELSIO_T5 ? 3589 X_FETCHBURSTMAX_512B : X_FETCHBURSTMAX_256B)); 3590 c.fl0size = htobe16(fl->qsize); 3591 c.fl0addr = htobe64(fl->ba); 3592 } 3593 3594 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3595 if (rc != 0) { 3596 device_printf(sc->dev, 3597 "failed to create ingress queue: %d\n", rc); 3598 return (rc); 3599 } 3600 3601 iq->cidx = 0; 3602 iq->gen = F_RSPD_GEN; 3603 iq->intr_next = iq->intr_params; 3604 iq->cntxt_id = be16toh(c.iqid); 3605 iq->abs_id = be16toh(c.physiqid); 3606 iq->flags |= IQ_ALLOCATED; 3607 3608 cntxt_id = iq->cntxt_id - sc->sge.iq_start; 3609 if (cntxt_id >= sc->sge.iqmap_sz) { 3610 panic ("%s: iq->cntxt_id (%d) more than the max (%d)", __func__, 3611 cntxt_id, sc->sge.iqmap_sz - 1); 3612 } 3613 sc->sge.iqmap[cntxt_id] = iq; 3614 3615 if (fl) { 3616 u_int qid; 3617 3618 iq->flags |= IQ_HAS_FL; 3619 fl->cntxt_id = be16toh(c.fl0id); 3620 fl->pidx = fl->cidx = 0; 3621 3622 cntxt_id = fl->cntxt_id - sc->sge.eq_start; 3623 if (cntxt_id >= sc->sge.eqmap_sz) { 3624 panic("%s: fl->cntxt_id (%d) more than the max (%d)", 3625 __func__, cntxt_id, sc->sge.eqmap_sz - 1); 3626 } 3627 sc->sge.eqmap[cntxt_id] = (void *)fl; 3628 3629 qid = fl->cntxt_id; 3630 if (isset(&sc->doorbells, DOORBELL_UDB)) { 3631 uint32_t s_qpp = sc->params.sge.eq_s_qpp; 3632 uint32_t mask = (1 << s_qpp) - 1; 3633 volatile uint8_t *udb; 3634 3635 udb = sc->udbs_base + UDBS_DB_OFFSET; 3636 udb += (qid >> s_qpp) << PAGE_SHIFT; 3637 qid &= mask; 3638 if (qid < PAGE_SIZE / UDBS_SEG_SIZE) { 3639 udb += qid << UDBS_SEG_SHIFT; 3640 qid = 0; 3641 } 3642 fl->udb = (volatile void *)udb; 3643 } 3644 fl->dbval = V_QID(qid) | sc->chip_params->sge_fl_db; 3645 3646 FL_LOCK(fl); 3647 /* Enough to make sure the SGE doesn't think it's starved */ 3648 refill_fl(sc, fl, fl->lowat); 3649 FL_UNLOCK(fl); 3650 } 3651 3652 if (chip_id(sc) >= CHELSIO_T5 && !(sc->flags & IS_VF) && cong >= 0) { 3653 uint32_t param, val; 3654 3655 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 3656 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) | 3657 V_FW_PARAMS_PARAM_YZ(iq->cntxt_id); 3658 if (cong == 0) 3659 val = 1 << 19; 3660 else { 3661 val = 2 << 19; 3662 for (i = 0; i < 4; i++) { 3663 if (cong & (1 << i)) 3664 val |= 1 << (i << 2); 3665 } 3666 } 3667 3668 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 3669 if (rc != 0) { 3670 /* report error but carry on */ 3671 device_printf(sc->dev, 3672 "failed to set congestion manager context for " 3673 "ingress queue %d: %d\n", iq->cntxt_id, rc); 3674 } 3675 } 3676 3677 /* Enable IQ interrupts */ 3678 atomic_store_rel_int(&iq->state, IQS_IDLE); 3679 t4_write_reg(sc, sc->sge_gts_reg, V_SEINTARM(iq->intr_params) | 3680 V_INGRESSQID(iq->cntxt_id)); 3681 3682 return (0); 3683 } 3684 3685 static int 3686 free_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl) 3687 { 3688 int rc; 3689 struct adapter *sc = iq->adapter; 3690 device_t dev; 3691 3692 if (sc == NULL) 3693 return (0); /* nothing to do */ 3694 3695 dev = vi ? vi->dev : sc->dev; 3696 3697 if (iq->flags & IQ_ALLOCATED) { 3698 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0, 3699 FW_IQ_TYPE_FL_INT_CAP, iq->cntxt_id, 3700 fl ? fl->cntxt_id : 0xffff, 0xffff); 3701 if (rc != 0) { 3702 device_printf(dev, 3703 "failed to free queue %p: %d\n", iq, rc); 3704 return (rc); 3705 } 3706 iq->flags &= ~IQ_ALLOCATED; 3707 } 3708 3709 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, iq->desc); 3710 3711 bzero(iq, sizeof(*iq)); 3712 3713 if (fl) { 3714 free_ring(sc, fl->desc_tag, fl->desc_map, fl->ba, 3715 fl->desc); 3716 3717 if (fl->sdesc) 3718 free_fl_sdesc(sc, fl); 3719 3720 if (mtx_initialized(&fl->fl_lock)) 3721 mtx_destroy(&fl->fl_lock); 3722 3723 bzero(fl, sizeof(*fl)); 3724 } 3725 3726 return (0); 3727 } 3728 3729 static void 3730 add_iq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid, 3731 struct sge_iq *iq) 3732 { 3733 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3734 3735 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, &iq->ba, 3736 "bus address of descriptor ring"); 3737 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3738 iq->qsize * IQ_ESIZE, "descriptor ring size in bytes"); 3739 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "abs_id", CTLFLAG_RD, 3740 &iq->abs_id, 0, "absolute id of the queue"); 3741 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 3742 &iq->cntxt_id, 0, "SGE context id of the queue"); 3743 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &iq->cidx, 3744 0, "consumer index"); 3745 } 3746 3747 static void 3748 add_fl_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx, 3749 struct sysctl_oid *oid, struct sge_fl *fl) 3750 { 3751 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3752 3753 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", 3754 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "freelist"); 3755 children = SYSCTL_CHILDREN(oid); 3756 3757 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, 3758 &fl->ba, "bus address of descriptor ring"); 3759 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3760 fl->sidx * EQ_ESIZE + sc->params.sge.spg_len, 3761 "desc ring size in bytes"); 3762 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 3763 &fl->cntxt_id, 0, "SGE context id of the freelist"); 3764 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "padding", CTLFLAG_RD, NULL, 3765 fl_pad ? 1 : 0, "padding enabled"); 3766 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "packing", CTLFLAG_RD, NULL, 3767 fl->flags & FL_BUF_PACKING ? 1 : 0, "packing enabled"); 3768 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &fl->cidx, 3769 0, "consumer index"); 3770 if (fl->flags & FL_BUF_PACKING) { 3771 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rx_offset", 3772 CTLFLAG_RD, &fl->rx_offset, 0, "packing rx offset"); 3773 } 3774 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &fl->pidx, 3775 0, "producer index"); 3776 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_allocated", 3777 CTLFLAG_RD, &fl->cl_allocated, "# of clusters allocated"); 3778 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_recycled", 3779 CTLFLAG_RD, &fl->cl_recycled, "# of clusters recycled"); 3780 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_fast_recycled", 3781 CTLFLAG_RD, &fl->cl_fast_recycled, "# of clusters recycled (fast)"); 3782 } 3783 3784 static int 3785 alloc_fwq(struct adapter *sc) 3786 { 3787 int rc, intr_idx; 3788 struct sge_iq *fwq = &sc->sge.fwq; 3789 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev); 3790 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3791 3792 init_iq(fwq, sc, 0, 0, FW_IQ_QSIZE); 3793 if (sc->flags & IS_VF) 3794 intr_idx = 0; 3795 else 3796 intr_idx = sc->intr_count > 1 ? 1 : 0; 3797 rc = alloc_iq_fl(&sc->port[0]->vi[0], fwq, NULL, intr_idx, -1); 3798 if (rc != 0) { 3799 device_printf(sc->dev, 3800 "failed to create firmware event queue: %d\n", rc); 3801 return (rc); 3802 } 3803 3804 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "fwq", 3805 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "firmware event queue"); 3806 add_iq_sysctls(&sc->ctx, oid, fwq); 3807 3808 return (0); 3809 } 3810 3811 static int 3812 free_fwq(struct adapter *sc) 3813 { 3814 return free_iq_fl(NULL, &sc->sge.fwq, NULL); 3815 } 3816 3817 static int 3818 alloc_ctrlq(struct adapter *sc, struct sge_wrq *ctrlq, int idx, 3819 struct sysctl_oid *oid) 3820 { 3821 int rc; 3822 char name[16]; 3823 struct sysctl_oid_list *children; 3824 3825 snprintf(name, sizeof(name), "%s ctrlq%d", device_get_nameunit(sc->dev), 3826 idx); 3827 init_eq(sc, &ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE, sc->port[idx]->tx_chan, 3828 sc->sge.fwq.cntxt_id, name); 3829 3830 children = SYSCTL_CHILDREN(oid); 3831 snprintf(name, sizeof(name), "%d", idx); 3832 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, name, 3833 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "ctrl queue"); 3834 rc = alloc_wrq(sc, NULL, ctrlq, oid); 3835 3836 return (rc); 3837 } 3838 3839 int 3840 tnl_cong(struct port_info *pi, int drop) 3841 { 3842 3843 if (drop == -1) 3844 return (-1); 3845 else if (drop == 1) 3846 return (0); 3847 else 3848 return (pi->rx_e_chan_map); 3849 } 3850 3851 static int 3852 alloc_rxq(struct vi_info *vi, struct sge_rxq *rxq, int intr_idx, int idx, 3853 struct sysctl_oid *oid) 3854 { 3855 int rc; 3856 struct adapter *sc = vi->adapter; 3857 struct sysctl_oid_list *children; 3858 char name[16]; 3859 3860 rc = alloc_iq_fl(vi, &rxq->iq, &rxq->fl, intr_idx, 3861 tnl_cong(vi->pi, cong_drop)); 3862 if (rc != 0) 3863 return (rc); 3864 3865 if (idx == 0) 3866 sc->sge.iq_base = rxq->iq.abs_id - rxq->iq.cntxt_id; 3867 else 3868 KASSERT(rxq->iq.cntxt_id + sc->sge.iq_base == rxq->iq.abs_id, 3869 ("iq_base mismatch")); 3870 KASSERT(sc->sge.iq_base == 0 || sc->flags & IS_VF, 3871 ("PF with non-zero iq_base")); 3872 3873 /* 3874 * The freelist is just barely above the starvation threshold right now, 3875 * fill it up a bit more. 3876 */ 3877 FL_LOCK(&rxq->fl); 3878 refill_fl(sc, &rxq->fl, 128); 3879 FL_UNLOCK(&rxq->fl); 3880 3881 #if defined(INET) || defined(INET6) 3882 rc = tcp_lro_init_args(&rxq->lro, vi->ifp, lro_entries, lro_mbufs); 3883 if (rc != 0) 3884 return (rc); 3885 MPASS(rxq->lro.ifp == vi->ifp); /* also indicates LRO init'ed */ 3886 3887 if (vi->ifp->if_capenable & IFCAP_LRO) 3888 rxq->iq.flags |= IQ_LRO_ENABLED; 3889 #endif 3890 if (vi->ifp->if_capenable & IFCAP_HWRXTSTMP) 3891 rxq->iq.flags |= IQ_RX_TIMESTAMP; 3892 rxq->ifp = vi->ifp; 3893 3894 children = SYSCTL_CHILDREN(oid); 3895 3896 snprintf(name, sizeof(name), "%d", idx); 3897 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, 3898 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "rx queue"); 3899 children = SYSCTL_CHILDREN(oid); 3900 3901 add_iq_sysctls(&vi->ctx, oid, &rxq->iq); 3902 #if defined(INET) || defined(INET6) 3903 SYSCTL_ADD_U64(&vi->ctx, children, OID_AUTO, "lro_queued", CTLFLAG_RD, 3904 &rxq->lro.lro_queued, 0, NULL); 3905 SYSCTL_ADD_U64(&vi->ctx, children, OID_AUTO, "lro_flushed", CTLFLAG_RD, 3906 &rxq->lro.lro_flushed, 0, NULL); 3907 #endif 3908 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "rxcsum", CTLFLAG_RD, 3909 &rxq->rxcsum, "# of times hardware assisted with checksum"); 3910 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_extraction", 3911 CTLFLAG_RD, &rxq->vlan_extraction, 3912 "# of times hardware extracted 802.1Q tag"); 3913 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vxlan_rxcsum", 3914 CTLFLAG_RD, &rxq->vxlan_rxcsum, 3915 "# of times hardware assisted with inner checksum (VXLAN) "); 3916 3917 add_fl_sysctls(sc, &vi->ctx, oid, &rxq->fl); 3918 3919 return (rc); 3920 } 3921 3922 static int 3923 free_rxq(struct vi_info *vi, struct sge_rxq *rxq) 3924 { 3925 int rc; 3926 3927 #if defined(INET) || defined(INET6) 3928 if (rxq->lro.ifp) { 3929 tcp_lro_free(&rxq->lro); 3930 rxq->lro.ifp = NULL; 3931 } 3932 #endif 3933 3934 rc = free_iq_fl(vi, &rxq->iq, &rxq->fl); 3935 if (rc == 0) 3936 bzero(rxq, sizeof(*rxq)); 3937 3938 return (rc); 3939 } 3940 3941 #ifdef TCP_OFFLOAD 3942 static int 3943 alloc_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq, 3944 int intr_idx, int idx, struct sysctl_oid *oid) 3945 { 3946 struct port_info *pi = vi->pi; 3947 int rc; 3948 struct sysctl_oid_list *children; 3949 char name[16]; 3950 3951 rc = alloc_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl, intr_idx, 0); 3952 if (rc != 0) 3953 return (rc); 3954 3955 children = SYSCTL_CHILDREN(oid); 3956 3957 snprintf(name, sizeof(name), "%d", idx); 3958 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, 3959 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "rx queue"); 3960 add_iq_sysctls(&vi->ctx, oid, &ofld_rxq->iq); 3961 add_fl_sysctls(pi->adapter, &vi->ctx, oid, &ofld_rxq->fl); 3962 3963 SYSCTL_ADD_ULONG(&vi->ctx, SYSCTL_CHILDREN(oid), OID_AUTO, 3964 "rx_toe_tls_records", CTLFLAG_RD, &ofld_rxq->rx_toe_tls_records, 3965 "# of TOE TLS records received"); 3966 SYSCTL_ADD_ULONG(&vi->ctx, SYSCTL_CHILDREN(oid), OID_AUTO, 3967 "rx_toe_tls_octets", CTLFLAG_RD, &ofld_rxq->rx_toe_tls_octets, 3968 "# of payload octets in received TOE TLS records"); 3969 3970 return (rc); 3971 } 3972 3973 static int 3974 free_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq) 3975 { 3976 int rc; 3977 3978 rc = free_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl); 3979 if (rc == 0) 3980 bzero(ofld_rxq, sizeof(*ofld_rxq)); 3981 3982 return (rc); 3983 } 3984 #endif 3985 3986 /* 3987 * Returns a reasonable automatic cidx flush threshold for a given queue size. 3988 */ 3989 static u_int 3990 qsize_to_fthresh(int qsize) 3991 { 3992 u_int fthresh; 3993 3994 while (!powerof2(qsize)) 3995 qsize++; 3996 fthresh = ilog2(qsize); 3997 if (fthresh > X_CIDXFLUSHTHRESH_128) 3998 fthresh = X_CIDXFLUSHTHRESH_128; 3999 4000 return (fthresh); 4001 } 4002 4003 static int 4004 ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq) 4005 { 4006 int rc, cntxt_id; 4007 struct fw_eq_ctrl_cmd c; 4008 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 4009 4010 bzero(&c, sizeof(c)); 4011 4012 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | F_FW_CMD_REQUEST | 4013 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_CTRL_CMD_PFN(sc->pf) | 4014 V_FW_EQ_CTRL_CMD_VFN(0)); 4015 c.alloc_to_len16 = htobe32(F_FW_EQ_CTRL_CMD_ALLOC | 4016 F_FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c)); 4017 c.cmpliqid_eqid = htonl(V_FW_EQ_CTRL_CMD_CMPLIQID(eq->iqid)); 4018 c.physeqid_pkd = htobe32(0); 4019 c.fetchszm_to_iqid = 4020 htobe32(V_FW_EQ_CTRL_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 4021 V_FW_EQ_CTRL_CMD_PCIECHN(eq->tx_chan) | 4022 F_FW_EQ_CTRL_CMD_FETCHRO | V_FW_EQ_CTRL_CMD_IQID(eq->iqid)); 4023 c.dcaen_to_eqsize = 4024 htobe32(V_FW_EQ_CTRL_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ? 4025 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) | 4026 V_FW_EQ_CTRL_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 4027 V_FW_EQ_CTRL_CMD_CIDXFTHRESH(qsize_to_fthresh(qsize)) | 4028 V_FW_EQ_CTRL_CMD_EQSIZE(qsize)); 4029 c.eqaddr = htobe64(eq->ba); 4030 4031 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 4032 if (rc != 0) { 4033 device_printf(sc->dev, 4034 "failed to create control queue %d: %d\n", eq->tx_chan, rc); 4035 return (rc); 4036 } 4037 eq->flags |= EQ_ALLOCATED; 4038 4039 eq->cntxt_id = G_FW_EQ_CTRL_CMD_EQID(be32toh(c.cmpliqid_eqid)); 4040 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 4041 if (cntxt_id >= sc->sge.eqmap_sz) 4042 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 4043 cntxt_id, sc->sge.eqmap_sz - 1); 4044 sc->sge.eqmap[cntxt_id] = eq; 4045 4046 return (rc); 4047 } 4048 4049 static int 4050 eth_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 4051 { 4052 int rc, cntxt_id; 4053 struct fw_eq_eth_cmd c; 4054 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 4055 4056 bzero(&c, sizeof(c)); 4057 4058 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST | 4059 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) | 4060 V_FW_EQ_ETH_CMD_VFN(0)); 4061 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC | 4062 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c)); 4063 c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE | 4064 F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(vi->viid)); 4065 c.fetchszm_to_iqid = 4066 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) | 4067 V_FW_EQ_ETH_CMD_PCIECHN(eq->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO | 4068 V_FW_EQ_ETH_CMD_IQID(eq->iqid)); 4069 c.dcaen_to_eqsize = 4070 htobe32(V_FW_EQ_ETH_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ? 4071 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) | 4072 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 4073 V_FW_EQ_ETH_CMD_EQSIZE(qsize)); 4074 c.eqaddr = htobe64(eq->ba); 4075 4076 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 4077 if (rc != 0) { 4078 device_printf(vi->dev, 4079 "failed to create Ethernet egress queue: %d\n", rc); 4080 return (rc); 4081 } 4082 eq->flags |= EQ_ALLOCATED; 4083 4084 eq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd)); 4085 eq->abs_id = G_FW_EQ_ETH_CMD_PHYSEQID(be32toh(c.physeqid_pkd)); 4086 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 4087 if (cntxt_id >= sc->sge.eqmap_sz) 4088 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 4089 cntxt_id, sc->sge.eqmap_sz - 1); 4090 sc->sge.eqmap[cntxt_id] = eq; 4091 4092 return (rc); 4093 } 4094 4095 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 4096 static int 4097 ofld_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 4098 { 4099 int rc, cntxt_id; 4100 struct fw_eq_ofld_cmd c; 4101 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 4102 4103 bzero(&c, sizeof(c)); 4104 4105 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | F_FW_CMD_REQUEST | 4106 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_OFLD_CMD_PFN(sc->pf) | 4107 V_FW_EQ_OFLD_CMD_VFN(0)); 4108 c.alloc_to_len16 = htonl(F_FW_EQ_OFLD_CMD_ALLOC | 4109 F_FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c)); 4110 c.fetchszm_to_iqid = 4111 htonl(V_FW_EQ_OFLD_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 4112 V_FW_EQ_OFLD_CMD_PCIECHN(eq->tx_chan) | 4113 F_FW_EQ_OFLD_CMD_FETCHRO | V_FW_EQ_OFLD_CMD_IQID(eq->iqid)); 4114 c.dcaen_to_eqsize = 4115 htobe32(V_FW_EQ_OFLD_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ? 4116 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) | 4117 V_FW_EQ_OFLD_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 4118 V_FW_EQ_OFLD_CMD_CIDXFTHRESH(qsize_to_fthresh(qsize)) | 4119 V_FW_EQ_OFLD_CMD_EQSIZE(qsize)); 4120 c.eqaddr = htobe64(eq->ba); 4121 4122 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 4123 if (rc != 0) { 4124 device_printf(vi->dev, 4125 "failed to create egress queue for TCP offload: %d\n", rc); 4126 return (rc); 4127 } 4128 eq->flags |= EQ_ALLOCATED; 4129 4130 eq->cntxt_id = G_FW_EQ_OFLD_CMD_EQID(be32toh(c.eqid_pkd)); 4131 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 4132 if (cntxt_id >= sc->sge.eqmap_sz) 4133 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 4134 cntxt_id, sc->sge.eqmap_sz - 1); 4135 sc->sge.eqmap[cntxt_id] = eq; 4136 4137 return (rc); 4138 } 4139 #endif 4140 4141 static int 4142 alloc_eq(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 4143 { 4144 int rc, qsize; 4145 size_t len; 4146 4147 mtx_init(&eq->eq_lock, eq->lockname, NULL, MTX_DEF); 4148 4149 qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 4150 len = qsize * EQ_ESIZE; 4151 rc = alloc_ring(sc, len, &eq->desc_tag, &eq->desc_map, 4152 &eq->ba, (void **)&eq->desc); 4153 if (rc) 4154 return (rc); 4155 4156 eq->pidx = eq->cidx = eq->dbidx = 0; 4157 /* Note that equeqidx is not used with sge_wrq (OFLD/CTRL) queues. */ 4158 eq->equeqidx = 0; 4159 eq->doorbells = sc->doorbells; 4160 4161 switch (eq->flags & EQ_TYPEMASK) { 4162 case EQ_CTRL: 4163 rc = ctrl_eq_alloc(sc, eq); 4164 break; 4165 4166 case EQ_ETH: 4167 rc = eth_eq_alloc(sc, vi, eq); 4168 break; 4169 4170 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 4171 case EQ_OFLD: 4172 rc = ofld_eq_alloc(sc, vi, eq); 4173 break; 4174 #endif 4175 4176 default: 4177 panic("%s: invalid eq type %d.", __func__, 4178 eq->flags & EQ_TYPEMASK); 4179 } 4180 if (rc != 0) { 4181 device_printf(sc->dev, 4182 "failed to allocate egress queue(%d): %d\n", 4183 eq->flags & EQ_TYPEMASK, rc); 4184 } 4185 4186 if (isset(&eq->doorbells, DOORBELL_UDB) || 4187 isset(&eq->doorbells, DOORBELL_UDBWC) || 4188 isset(&eq->doorbells, DOORBELL_WCWR)) { 4189 uint32_t s_qpp = sc->params.sge.eq_s_qpp; 4190 uint32_t mask = (1 << s_qpp) - 1; 4191 volatile uint8_t *udb; 4192 4193 udb = sc->udbs_base + UDBS_DB_OFFSET; 4194 udb += (eq->cntxt_id >> s_qpp) << PAGE_SHIFT; /* pg offset */ 4195 eq->udb_qid = eq->cntxt_id & mask; /* id in page */ 4196 if (eq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE) 4197 clrbit(&eq->doorbells, DOORBELL_WCWR); 4198 else { 4199 udb += eq->udb_qid << UDBS_SEG_SHIFT; /* seg offset */ 4200 eq->udb_qid = 0; 4201 } 4202 eq->udb = (volatile void *)udb; 4203 } 4204 4205 return (rc); 4206 } 4207 4208 static int 4209 free_eq(struct adapter *sc, struct sge_eq *eq) 4210 { 4211 int rc; 4212 4213 if (eq->flags & EQ_ALLOCATED) { 4214 switch (eq->flags & EQ_TYPEMASK) { 4215 case EQ_CTRL: 4216 rc = -t4_ctrl_eq_free(sc, sc->mbox, sc->pf, 0, 4217 eq->cntxt_id); 4218 break; 4219 4220 case EQ_ETH: 4221 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0, 4222 eq->cntxt_id); 4223 break; 4224 4225 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 4226 case EQ_OFLD: 4227 rc = -t4_ofld_eq_free(sc, sc->mbox, sc->pf, 0, 4228 eq->cntxt_id); 4229 break; 4230 #endif 4231 4232 default: 4233 panic("%s: invalid eq type %d.", __func__, 4234 eq->flags & EQ_TYPEMASK); 4235 } 4236 if (rc != 0) { 4237 device_printf(sc->dev, 4238 "failed to free egress queue (%d): %d\n", 4239 eq->flags & EQ_TYPEMASK, rc); 4240 return (rc); 4241 } 4242 eq->flags &= ~EQ_ALLOCATED; 4243 } 4244 4245 free_ring(sc, eq->desc_tag, eq->desc_map, eq->ba, eq->desc); 4246 4247 if (mtx_initialized(&eq->eq_lock)) 4248 mtx_destroy(&eq->eq_lock); 4249 4250 bzero(eq, sizeof(*eq)); 4251 return (0); 4252 } 4253 4254 static int 4255 alloc_wrq(struct adapter *sc, struct vi_info *vi, struct sge_wrq *wrq, 4256 struct sysctl_oid *oid) 4257 { 4258 int rc; 4259 struct sysctl_ctx_list *ctx = vi ? &vi->ctx : &sc->ctx; 4260 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 4261 4262 rc = alloc_eq(sc, vi, &wrq->eq); 4263 if (rc) 4264 return (rc); 4265 4266 wrq->adapter = sc; 4267 TASK_INIT(&wrq->wrq_tx_task, 0, wrq_tx_drain, wrq); 4268 TAILQ_INIT(&wrq->incomplete_wrs); 4269 STAILQ_INIT(&wrq->wr_list); 4270 wrq->nwr_pending = 0; 4271 wrq->ndesc_needed = 0; 4272 4273 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, 4274 &wrq->eq.ba, "bus address of descriptor ring"); 4275 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 4276 wrq->eq.sidx * EQ_ESIZE + sc->params.sge.spg_len, 4277 "desc ring size in bytes"); 4278 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 4279 &wrq->eq.cntxt_id, 0, "SGE context id of the queue"); 4280 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, 4281 &wrq->eq.cidx, 0, "consumer index"); 4282 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, 4283 &wrq->eq.pidx, 0, "producer index"); 4284 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL, 4285 wrq->eq.sidx, "status page index"); 4286 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_direct", CTLFLAG_RD, 4287 &wrq->tx_wrs_direct, "# of work requests (direct)"); 4288 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_copied", CTLFLAG_RD, 4289 &wrq->tx_wrs_copied, "# of work requests (copied)"); 4290 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_sspace", CTLFLAG_RD, 4291 &wrq->tx_wrs_ss, "# of work requests (copied from scratch space)"); 4292 4293 return (rc); 4294 } 4295 4296 static int 4297 free_wrq(struct adapter *sc, struct sge_wrq *wrq) 4298 { 4299 int rc; 4300 4301 rc = free_eq(sc, &wrq->eq); 4302 if (rc) 4303 return (rc); 4304 4305 bzero(wrq, sizeof(*wrq)); 4306 return (0); 4307 } 4308 4309 static int 4310 alloc_txq(struct vi_info *vi, struct sge_txq *txq, int idx, 4311 struct sysctl_oid *oid) 4312 { 4313 int rc; 4314 struct port_info *pi = vi->pi; 4315 struct adapter *sc = pi->adapter; 4316 struct sge_eq *eq = &txq->eq; 4317 struct txpkts *txp; 4318 char name[16]; 4319 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 4320 4321 rc = mp_ring_alloc(&txq->r, eq->sidx, txq, eth_tx, can_resume_eth_tx, 4322 M_CXGBE, &eq->eq_lock, M_WAITOK); 4323 if (rc != 0) { 4324 device_printf(sc->dev, "failed to allocate mp_ring: %d\n", rc); 4325 return (rc); 4326 } 4327 4328 rc = alloc_eq(sc, vi, eq); 4329 if (rc != 0) { 4330 mp_ring_free(txq->r); 4331 txq->r = NULL; 4332 return (rc); 4333 } 4334 4335 /* Can't fail after this point. */ 4336 4337 if (idx == 0) 4338 sc->sge.eq_base = eq->abs_id - eq->cntxt_id; 4339 else 4340 KASSERT(eq->cntxt_id + sc->sge.eq_base == eq->abs_id, 4341 ("eq_base mismatch")); 4342 KASSERT(sc->sge.eq_base == 0 || sc->flags & IS_VF, 4343 ("PF with non-zero eq_base")); 4344 4345 TASK_INIT(&txq->tx_reclaim_task, 0, tx_reclaim, eq); 4346 txq->ifp = vi->ifp; 4347 txq->gl = sglist_alloc(TX_SGL_SEGS, M_WAITOK); 4348 if (vi->flags & TX_USES_VM_WR) 4349 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) | 4350 V_TXPKT_INTF(pi->tx_chan)); 4351 else 4352 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) | 4353 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(sc->pf) | 4354 V_TXPKT_VF(vi->vin) | V_TXPKT_VF_VLD(vi->vfvld)); 4355 txq->tc_idx = -1; 4356 txq->sdesc = malloc(eq->sidx * sizeof(struct tx_sdesc), M_CXGBE, 4357 M_ZERO | M_WAITOK); 4358 4359 txp = &txq->txp; 4360 MPASS(nitems(txp->mb) >= sc->params.max_pkts_per_eth_tx_pkts_wr); 4361 txq->txp.max_npkt = min(nitems(txp->mb), 4362 sc->params.max_pkts_per_eth_tx_pkts_wr); 4363 if (vi->flags & TX_USES_VM_WR && !(sc->flags & IS_VF)) 4364 txq->txp.max_npkt--; 4365 4366 snprintf(name, sizeof(name), "%d", idx); 4367 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, 4368 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "tx queue"); 4369 children = SYSCTL_CHILDREN(oid); 4370 4371 SYSCTL_ADD_UAUTO(&vi->ctx, children, OID_AUTO, "ba", CTLFLAG_RD, 4372 &eq->ba, "bus address of descriptor ring"); 4373 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 4374 eq->sidx * EQ_ESIZE + sc->params.sge.spg_len, 4375 "desc ring size in bytes"); 4376 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "abs_id", CTLFLAG_RD, 4377 &eq->abs_id, 0, "absolute id of the queue"); 4378 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 4379 &eq->cntxt_id, 0, "SGE context id of the queue"); 4380 SYSCTL_ADD_U16(&vi->ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, 4381 &eq->cidx, 0, "consumer index"); 4382 SYSCTL_ADD_U16(&vi->ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, 4383 &eq->pidx, 0, "producer index"); 4384 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL, 4385 eq->sidx, "status page index"); 4386 4387 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "tc", 4388 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, idx, sysctl_tc, 4389 "I", "traffic class (-1 means none)"); 4390 4391 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txcsum", CTLFLAG_RD, 4392 &txq->txcsum, "# of times hardware assisted with checksum"); 4393 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_insertion", 4394 CTLFLAG_RD, &txq->vlan_insertion, 4395 "# of times hardware inserted 802.1Q tag"); 4396 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "tso_wrs", CTLFLAG_RD, 4397 &txq->tso_wrs, "# of TSO work requests"); 4398 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "imm_wrs", CTLFLAG_RD, 4399 &txq->imm_wrs, "# of work requests with immediate data"); 4400 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "sgl_wrs", CTLFLAG_RD, 4401 &txq->sgl_wrs, "# of work requests with direct SGL"); 4402 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkt_wrs", CTLFLAG_RD, 4403 &txq->txpkt_wrs, "# of txpkt work requests (one pkt/WR)"); 4404 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_wrs", 4405 CTLFLAG_RD, &txq->txpkts0_wrs, 4406 "# of txpkts (type 0) work requests"); 4407 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_wrs", 4408 CTLFLAG_RD, &txq->txpkts1_wrs, 4409 "# of txpkts (type 1) work requests"); 4410 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_pkts", 4411 CTLFLAG_RD, &txq->txpkts0_pkts, 4412 "# of frames tx'd using type0 txpkts work requests"); 4413 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_pkts", 4414 CTLFLAG_RD, &txq->txpkts1_pkts, 4415 "# of frames tx'd using type1 txpkts work requests"); 4416 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts_flush", 4417 CTLFLAG_RD, &txq->txpkts_flush, 4418 "# of times txpkts had to be flushed out by an egress-update"); 4419 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "raw_wrs", CTLFLAG_RD, 4420 &txq->raw_wrs, "# of raw work requests (non-packets)"); 4421 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vxlan_tso_wrs", 4422 CTLFLAG_RD, &txq->vxlan_tso_wrs, "# of VXLAN TSO work requests"); 4423 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vxlan_txcsum", 4424 CTLFLAG_RD, &txq->vxlan_txcsum, 4425 "# of times hardware assisted with inner checksums (VXLAN)"); 4426 4427 #ifdef KERN_TLS 4428 if (is_ktls(sc)) { 4429 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, 4430 "kern_tls_records", CTLFLAG_RD, &txq->kern_tls_records, 4431 "# of NIC TLS records transmitted"); 4432 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, 4433 "kern_tls_short", CTLFLAG_RD, &txq->kern_tls_short, 4434 "# of short NIC TLS records transmitted"); 4435 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, 4436 "kern_tls_partial", CTLFLAG_RD, &txq->kern_tls_partial, 4437 "# of partial NIC TLS records transmitted"); 4438 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, 4439 "kern_tls_full", CTLFLAG_RD, &txq->kern_tls_full, 4440 "# of full NIC TLS records transmitted"); 4441 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, 4442 "kern_tls_octets", CTLFLAG_RD, &txq->kern_tls_octets, 4443 "# of payload octets in transmitted NIC TLS records"); 4444 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, 4445 "kern_tls_waste", CTLFLAG_RD, &txq->kern_tls_waste, 4446 "# of octets DMAd but not transmitted in NIC TLS records"); 4447 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, 4448 "kern_tls_options", CTLFLAG_RD, &txq->kern_tls_options, 4449 "# of NIC TLS options-only packets transmitted"); 4450 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, 4451 "kern_tls_header", CTLFLAG_RD, &txq->kern_tls_header, 4452 "# of NIC TLS header-only packets transmitted"); 4453 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, 4454 "kern_tls_fin", CTLFLAG_RD, &txq->kern_tls_fin, 4455 "# of NIC TLS FIN-only packets transmitted"); 4456 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, 4457 "kern_tls_fin_short", CTLFLAG_RD, &txq->kern_tls_fin_short, 4458 "# of NIC TLS padded FIN packets on short TLS records"); 4459 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, 4460 "kern_tls_cbc", CTLFLAG_RD, &txq->kern_tls_cbc, 4461 "# of NIC TLS sessions using AES-CBC"); 4462 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, 4463 "kern_tls_gcm", CTLFLAG_RD, &txq->kern_tls_gcm, 4464 "# of NIC TLS sessions using AES-GCM"); 4465 } 4466 #endif 4467 mp_ring_sysctls(txq->r, &vi->ctx, children); 4468 4469 return (0); 4470 } 4471 4472 static int 4473 free_txq(struct vi_info *vi, struct sge_txq *txq) 4474 { 4475 int rc; 4476 struct adapter *sc = vi->adapter; 4477 struct sge_eq *eq = &txq->eq; 4478 4479 rc = free_eq(sc, eq); 4480 if (rc) 4481 return (rc); 4482 4483 sglist_free(txq->gl); 4484 free(txq->sdesc, M_CXGBE); 4485 mp_ring_free(txq->r); 4486 4487 bzero(txq, sizeof(*txq)); 4488 return (0); 4489 } 4490 4491 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 4492 static int 4493 alloc_ofld_txq(struct vi_info *vi, struct sge_ofld_txq *ofld_txq, int idx, 4494 struct sysctl_oid *oid) 4495 { 4496 struct adapter *sc = vi->adapter; 4497 struct sysctl_oid_list *children; 4498 char name[16]; 4499 int rc; 4500 4501 children = SYSCTL_CHILDREN(oid); 4502 4503 snprintf(name, sizeof(name), "%d", idx); 4504 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, 4505 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "offload tx queue"); 4506 children = SYSCTL_CHILDREN(oid); 4507 4508 rc = alloc_wrq(sc, vi, &ofld_txq->wrq, oid); 4509 if (rc != 0) 4510 return (rc); 4511 4512 ofld_txq->tx_iscsi_pdus = counter_u64_alloc(M_WAITOK); 4513 ofld_txq->tx_iscsi_octets = counter_u64_alloc(M_WAITOK); 4514 ofld_txq->tx_toe_tls_records = counter_u64_alloc(M_WAITOK); 4515 ofld_txq->tx_toe_tls_octets = counter_u64_alloc(M_WAITOK); 4516 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, 4517 "tx_iscsi_pdus", CTLFLAG_RD, &ofld_txq->tx_iscsi_pdus, 4518 "# of iSCSI PDUs transmitted"); 4519 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, 4520 "tx_iscsi_octets", CTLFLAG_RD, &ofld_txq->tx_iscsi_octets, 4521 "# of payload octets in transmitted iSCSI PDUs"); 4522 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, 4523 "tx_toe_tls_records", CTLFLAG_RD, &ofld_txq->tx_toe_tls_records, 4524 "# of TOE TLS records transmitted"); 4525 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, 4526 "tx_toe_tls_octets", CTLFLAG_RD, &ofld_txq->tx_toe_tls_octets, 4527 "# of payload octets in transmitted TOE TLS records"); 4528 4529 return (rc); 4530 } 4531 4532 static int 4533 free_ofld_txq(struct vi_info *vi, struct sge_ofld_txq *ofld_txq) 4534 { 4535 struct adapter *sc = vi->adapter; 4536 int rc; 4537 4538 rc = free_wrq(sc, &ofld_txq->wrq); 4539 if (rc != 0) 4540 return (rc); 4541 4542 counter_u64_free(ofld_txq->tx_iscsi_pdus); 4543 counter_u64_free(ofld_txq->tx_iscsi_octets); 4544 counter_u64_free(ofld_txq->tx_toe_tls_records); 4545 counter_u64_free(ofld_txq->tx_toe_tls_octets); 4546 4547 bzero(ofld_txq, sizeof(*ofld_txq)); 4548 return (0); 4549 } 4550 #endif 4551 4552 static void 4553 oneseg_dma_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error) 4554 { 4555 bus_addr_t *ba = arg; 4556 4557 KASSERT(nseg == 1, 4558 ("%s meant for single segment mappings only.", __func__)); 4559 4560 *ba = error ? 0 : segs->ds_addr; 4561 } 4562 4563 static inline void 4564 ring_fl_db(struct adapter *sc, struct sge_fl *fl) 4565 { 4566 uint32_t n, v; 4567 4568 n = IDXDIFF(fl->pidx >> 3, fl->dbidx, fl->sidx); 4569 MPASS(n > 0); 4570 4571 wmb(); 4572 v = fl->dbval | V_PIDX(n); 4573 if (fl->udb) 4574 *fl->udb = htole32(v); 4575 else 4576 t4_write_reg(sc, sc->sge_kdoorbell_reg, v); 4577 IDXINCR(fl->dbidx, n, fl->sidx); 4578 } 4579 4580 /* 4581 * Fills up the freelist by allocating up to 'n' buffers. Buffers that are 4582 * recycled do not count towards this allocation budget. 4583 * 4584 * Returns non-zero to indicate that this freelist should be added to the list 4585 * of starving freelists. 4586 */ 4587 static int 4588 refill_fl(struct adapter *sc, struct sge_fl *fl, int n) 4589 { 4590 __be64 *d; 4591 struct fl_sdesc *sd; 4592 uintptr_t pa; 4593 caddr_t cl; 4594 struct rx_buf_info *rxb; 4595 struct cluster_metadata *clm; 4596 uint16_t max_pidx, zidx = fl->zidx; 4597 uint16_t hw_cidx = fl->hw_cidx; /* stable snapshot */ 4598 4599 FL_LOCK_ASSERT_OWNED(fl); 4600 4601 /* 4602 * We always stop at the beginning of the hardware descriptor that's just 4603 * before the one with the hw cidx. This is to avoid hw pidx = hw cidx, 4604 * which would mean an empty freelist to the chip. 4605 */ 4606 max_pidx = __predict_false(hw_cidx == 0) ? fl->sidx - 1 : hw_cidx - 1; 4607 if (fl->pidx == max_pidx * 8) 4608 return (0); 4609 4610 d = &fl->desc[fl->pidx]; 4611 sd = &fl->sdesc[fl->pidx]; 4612 rxb = &sc->sge.rx_buf_info[zidx]; 4613 4614 while (n > 0) { 4615 4616 if (sd->cl != NULL) { 4617 4618 if (sd->nmbuf == 0) { 4619 /* 4620 * Fast recycle without involving any atomics on 4621 * the cluster's metadata (if the cluster has 4622 * metadata). This happens when all frames 4623 * received in the cluster were small enough to 4624 * fit within a single mbuf each. 4625 */ 4626 fl->cl_fast_recycled++; 4627 goto recycled; 4628 } 4629 4630 /* 4631 * Cluster is guaranteed to have metadata. Clusters 4632 * without metadata always take the fast recycle path 4633 * when they're recycled. 4634 */ 4635 clm = cl_metadata(sd); 4636 MPASS(clm != NULL); 4637 4638 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) { 4639 fl->cl_recycled++; 4640 counter_u64_add(extfree_rels, 1); 4641 goto recycled; 4642 } 4643 sd->cl = NULL; /* gave up my reference */ 4644 } 4645 MPASS(sd->cl == NULL); 4646 cl = uma_zalloc(rxb->zone, M_NOWAIT); 4647 if (__predict_false(cl == NULL)) { 4648 if (zidx != fl->safe_zidx) { 4649 zidx = fl->safe_zidx; 4650 rxb = &sc->sge.rx_buf_info[zidx]; 4651 cl = uma_zalloc(rxb->zone, M_NOWAIT); 4652 } 4653 if (cl == NULL) 4654 break; 4655 } 4656 fl->cl_allocated++; 4657 n--; 4658 4659 pa = pmap_kextract((vm_offset_t)cl); 4660 sd->cl = cl; 4661 sd->zidx = zidx; 4662 4663 if (fl->flags & FL_BUF_PACKING) { 4664 *d = htobe64(pa | rxb->hwidx2); 4665 sd->moff = rxb->size2; 4666 } else { 4667 *d = htobe64(pa | rxb->hwidx1); 4668 sd->moff = 0; 4669 } 4670 recycled: 4671 sd->nmbuf = 0; 4672 d++; 4673 sd++; 4674 if (__predict_false((++fl->pidx & 7) == 0)) { 4675 uint16_t pidx = fl->pidx >> 3; 4676 4677 if (__predict_false(pidx == fl->sidx)) { 4678 fl->pidx = 0; 4679 pidx = 0; 4680 sd = fl->sdesc; 4681 d = fl->desc; 4682 } 4683 if (n < 8 || pidx == max_pidx) 4684 break; 4685 4686 if (IDXDIFF(pidx, fl->dbidx, fl->sidx) >= 4) 4687 ring_fl_db(sc, fl); 4688 } 4689 } 4690 4691 if ((fl->pidx >> 3) != fl->dbidx) 4692 ring_fl_db(sc, fl); 4693 4694 return (FL_RUNNING_LOW(fl) && !(fl->flags & FL_STARVING)); 4695 } 4696 4697 /* 4698 * Attempt to refill all starving freelists. 4699 */ 4700 static void 4701 refill_sfl(void *arg) 4702 { 4703 struct adapter *sc = arg; 4704 struct sge_fl *fl, *fl_temp; 4705 4706 mtx_assert(&sc->sfl_lock, MA_OWNED); 4707 TAILQ_FOREACH_SAFE(fl, &sc->sfl, link, fl_temp) { 4708 FL_LOCK(fl); 4709 refill_fl(sc, fl, 64); 4710 if (FL_NOT_RUNNING_LOW(fl) || fl->flags & FL_DOOMED) { 4711 TAILQ_REMOVE(&sc->sfl, fl, link); 4712 fl->flags &= ~FL_STARVING; 4713 } 4714 FL_UNLOCK(fl); 4715 } 4716 4717 if (!TAILQ_EMPTY(&sc->sfl)) 4718 callout_schedule(&sc->sfl_callout, hz / 5); 4719 } 4720 4721 static int 4722 alloc_fl_sdesc(struct sge_fl *fl) 4723 { 4724 4725 fl->sdesc = malloc(fl->sidx * 8 * sizeof(struct fl_sdesc), M_CXGBE, 4726 M_ZERO | M_WAITOK); 4727 4728 return (0); 4729 } 4730 4731 static void 4732 free_fl_sdesc(struct adapter *sc, struct sge_fl *fl) 4733 { 4734 struct fl_sdesc *sd; 4735 struct cluster_metadata *clm; 4736 int i; 4737 4738 sd = fl->sdesc; 4739 for (i = 0; i < fl->sidx * 8; i++, sd++) { 4740 if (sd->cl == NULL) 4741 continue; 4742 4743 if (sd->nmbuf == 0) 4744 uma_zfree(sc->sge.rx_buf_info[sd->zidx].zone, sd->cl); 4745 else if (fl->flags & FL_BUF_PACKING) { 4746 clm = cl_metadata(sd); 4747 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) { 4748 uma_zfree(sc->sge.rx_buf_info[sd->zidx].zone, 4749 sd->cl); 4750 counter_u64_add(extfree_rels, 1); 4751 } 4752 } 4753 sd->cl = NULL; 4754 } 4755 4756 free(fl->sdesc, M_CXGBE); 4757 fl->sdesc = NULL; 4758 } 4759 4760 static inline void 4761 get_pkt_gl(struct mbuf *m, struct sglist *gl) 4762 { 4763 int rc; 4764 4765 M_ASSERTPKTHDR(m); 4766 4767 sglist_reset(gl); 4768 rc = sglist_append_mbuf(gl, m); 4769 if (__predict_false(rc != 0)) { 4770 panic("%s: mbuf %p (%d segs) was vetted earlier but now fails " 4771 "with %d.", __func__, m, mbuf_nsegs(m), rc); 4772 } 4773 4774 KASSERT(gl->sg_nseg == mbuf_nsegs(m), 4775 ("%s: nsegs changed for mbuf %p from %d to %d", __func__, m, 4776 mbuf_nsegs(m), gl->sg_nseg)); 4777 #if 0 /* vm_wr not readily available here. */ 4778 KASSERT(gl->sg_nseg > 0 && gl->sg_nseg <= max_nsegs_allowed(m, vm_wr), 4779 ("%s: %d segments, should have been 1 <= nsegs <= %d", __func__, 4780 gl->sg_nseg, max_nsegs_allowed(m, vm_wr))); 4781 #endif 4782 } 4783 4784 /* 4785 * len16 for a txpkt WR with a GL. Includes the firmware work request header. 4786 */ 4787 static inline u_int 4788 txpkt_len16(u_int nsegs, const u_int extra) 4789 { 4790 u_int n; 4791 4792 MPASS(nsegs > 0); 4793 4794 nsegs--; /* first segment is part of ulptx_sgl */ 4795 n = extra + sizeof(struct fw_eth_tx_pkt_wr) + 4796 sizeof(struct cpl_tx_pkt_core) + 4797 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 4798 4799 return (howmany(n, 16)); 4800 } 4801 4802 /* 4803 * len16 for a txpkt_vm WR with a GL. Includes the firmware work 4804 * request header. 4805 */ 4806 static inline u_int 4807 txpkt_vm_len16(u_int nsegs, const u_int extra) 4808 { 4809 u_int n; 4810 4811 MPASS(nsegs > 0); 4812 4813 nsegs--; /* first segment is part of ulptx_sgl */ 4814 n = extra + sizeof(struct fw_eth_tx_pkt_vm_wr) + 4815 sizeof(struct cpl_tx_pkt_core) + 4816 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 4817 4818 return (howmany(n, 16)); 4819 } 4820 4821 static inline void 4822 calculate_mbuf_len16(struct mbuf *m, bool vm_wr) 4823 { 4824 const int lso = sizeof(struct cpl_tx_pkt_lso_core); 4825 const int tnl_lso = sizeof(struct cpl_tx_tnl_lso); 4826 4827 if (vm_wr) { 4828 if (needs_tso(m)) 4829 set_mbuf_len16(m, txpkt_vm_len16(mbuf_nsegs(m), lso)); 4830 else 4831 set_mbuf_len16(m, txpkt_vm_len16(mbuf_nsegs(m), 0)); 4832 return; 4833 } 4834 4835 if (needs_tso(m)) { 4836 if (needs_vxlan_tso(m)) 4837 set_mbuf_len16(m, txpkt_len16(mbuf_nsegs(m), tnl_lso)); 4838 else 4839 set_mbuf_len16(m, txpkt_len16(mbuf_nsegs(m), lso)); 4840 } else 4841 set_mbuf_len16(m, txpkt_len16(mbuf_nsegs(m), 0)); 4842 } 4843 4844 /* 4845 * len16 for a txpkts type 0 WR with a GL. Does not include the firmware work 4846 * request header. 4847 */ 4848 static inline u_int 4849 txpkts0_len16(u_int nsegs) 4850 { 4851 u_int n; 4852 4853 MPASS(nsegs > 0); 4854 4855 nsegs--; /* first segment is part of ulptx_sgl */ 4856 n = sizeof(struct ulp_txpkt) + sizeof(struct ulptx_idata) + 4857 sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl) + 4858 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 4859 4860 return (howmany(n, 16)); 4861 } 4862 4863 /* 4864 * len16 for a txpkts type 1 WR with a GL. Does not include the firmware work 4865 * request header. 4866 */ 4867 static inline u_int 4868 txpkts1_len16(void) 4869 { 4870 u_int n; 4871 4872 n = sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl); 4873 4874 return (howmany(n, 16)); 4875 } 4876 4877 static inline u_int 4878 imm_payload(u_int ndesc) 4879 { 4880 u_int n; 4881 4882 n = ndesc * EQ_ESIZE - sizeof(struct fw_eth_tx_pkt_wr) - 4883 sizeof(struct cpl_tx_pkt_core); 4884 4885 return (n); 4886 } 4887 4888 static inline uint64_t 4889 csum_to_ctrl(struct adapter *sc, struct mbuf *m) 4890 { 4891 uint64_t ctrl; 4892 int csum_type, l2hlen, l3hlen; 4893 int x, y; 4894 static const int csum_types[3][2] = { 4895 {TX_CSUM_TCPIP, TX_CSUM_TCPIP6}, 4896 {TX_CSUM_UDPIP, TX_CSUM_UDPIP6}, 4897 {TX_CSUM_IP, 0} 4898 }; 4899 4900 M_ASSERTPKTHDR(m); 4901 4902 if (!needs_hwcsum(m)) 4903 return (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS); 4904 4905 MPASS(m->m_pkthdr.l2hlen >= ETHER_HDR_LEN); 4906 MPASS(m->m_pkthdr.l3hlen >= sizeof(struct ip)); 4907 4908 if (needs_vxlan_csum(m)) { 4909 MPASS(m->m_pkthdr.l4hlen > 0); 4910 MPASS(m->m_pkthdr.l5hlen > 0); 4911 MPASS(m->m_pkthdr.inner_l2hlen >= ETHER_HDR_LEN); 4912 MPASS(m->m_pkthdr.inner_l3hlen >= sizeof(struct ip)); 4913 4914 l2hlen = m->m_pkthdr.l2hlen + m->m_pkthdr.l3hlen + 4915 m->m_pkthdr.l4hlen + m->m_pkthdr.l5hlen + 4916 m->m_pkthdr.inner_l2hlen - ETHER_HDR_LEN; 4917 l3hlen = m->m_pkthdr.inner_l3hlen; 4918 } else { 4919 l2hlen = m->m_pkthdr.l2hlen - ETHER_HDR_LEN; 4920 l3hlen = m->m_pkthdr.l3hlen; 4921 } 4922 4923 ctrl = 0; 4924 if (!needs_l3_csum(m)) 4925 ctrl |= F_TXPKT_IPCSUM_DIS; 4926 4927 if (m->m_pkthdr.csum_flags & (CSUM_IP_TCP | CSUM_INNER_IP_TCP | 4928 CSUM_IP6_TCP | CSUM_INNER_IP6_TCP)) 4929 x = 0; /* TCP */ 4930 else if (m->m_pkthdr.csum_flags & (CSUM_IP_UDP | CSUM_INNER_IP_UDP | 4931 CSUM_IP6_UDP | CSUM_INNER_IP6_UDP)) 4932 x = 1; /* UDP */ 4933 else 4934 x = 2; 4935 4936 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_IP_TCP | CSUM_IP_UDP | 4937 CSUM_INNER_IP | CSUM_INNER_IP_TCP | CSUM_INNER_IP_UDP)) 4938 y = 0; /* IPv4 */ 4939 else { 4940 MPASS(m->m_pkthdr.csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | 4941 CSUM_INNER_IP6_TCP | CSUM_INNER_IP6_UDP)); 4942 y = 1; /* IPv6 */ 4943 } 4944 /* 4945 * needs_hwcsum returned true earlier so there must be some kind of 4946 * checksum to calculate. 4947 */ 4948 csum_type = csum_types[x][y]; 4949 MPASS(csum_type != 0); 4950 if (csum_type == TX_CSUM_IP) 4951 ctrl |= F_TXPKT_L4CSUM_DIS; 4952 ctrl |= V_TXPKT_CSUM_TYPE(csum_type) | V_TXPKT_IPHDR_LEN(l3hlen); 4953 if (chip_id(sc) <= CHELSIO_T5) 4954 ctrl |= V_TXPKT_ETHHDR_LEN(l2hlen); 4955 else 4956 ctrl |= V_T6_TXPKT_ETHHDR_LEN(l2hlen); 4957 4958 return (ctrl); 4959 } 4960 4961 static inline void * 4962 write_lso_cpl(void *cpl, struct mbuf *m0) 4963 { 4964 struct cpl_tx_pkt_lso_core *lso; 4965 uint32_t ctrl; 4966 4967 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 4968 m0->m_pkthdr.l4hlen > 0, 4969 ("%s: mbuf %p needs TSO but missing header lengths", 4970 __func__, m0)); 4971 4972 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | 4973 F_LSO_FIRST_SLICE | F_LSO_LAST_SLICE | 4974 V_LSO_ETHHDR_LEN((m0->m_pkthdr.l2hlen - ETHER_HDR_LEN) >> 2) | 4975 V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) | 4976 V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2); 4977 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 4978 ctrl |= F_LSO_IPV6; 4979 4980 lso = cpl; 4981 lso->lso_ctrl = htobe32(ctrl); 4982 lso->ipid_ofst = htobe16(0); 4983 lso->mss = htobe16(m0->m_pkthdr.tso_segsz); 4984 lso->seqno_offset = htobe32(0); 4985 lso->len = htobe32(m0->m_pkthdr.len); 4986 4987 return (lso + 1); 4988 } 4989 4990 static void * 4991 write_tnl_lso_cpl(void *cpl, struct mbuf *m0) 4992 { 4993 struct cpl_tx_tnl_lso *tnl_lso = cpl; 4994 uint32_t ctrl; 4995 4996 KASSERT(m0->m_pkthdr.inner_l2hlen > 0 && 4997 m0->m_pkthdr.inner_l3hlen > 0 && m0->m_pkthdr.inner_l4hlen > 0 && 4998 m0->m_pkthdr.inner_l5hlen > 0, 4999 ("%s: mbuf %p needs VXLAN_TSO but missing inner header lengths", 5000 __func__, m0)); 5001 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 5002 m0->m_pkthdr.l4hlen > 0 && m0->m_pkthdr.l5hlen > 0, 5003 ("%s: mbuf %p needs VXLAN_TSO but missing outer header lengths", 5004 __func__, m0)); 5005 5006 /* Outer headers. */ 5007 ctrl = V_CPL_TX_TNL_LSO_OPCODE(CPL_TX_TNL_LSO) | 5008 F_CPL_TX_TNL_LSO_FIRST | F_CPL_TX_TNL_LSO_LAST | 5009 V_CPL_TX_TNL_LSO_ETHHDRLENOUT( 5010 (m0->m_pkthdr.l2hlen - ETHER_HDR_LEN) >> 2) | 5011 V_CPL_TX_TNL_LSO_IPHDRLENOUT(m0->m_pkthdr.l3hlen >> 2) | 5012 F_CPL_TX_TNL_LSO_IPLENSETOUT; 5013 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 5014 ctrl |= F_CPL_TX_TNL_LSO_IPV6OUT; 5015 else { 5016 ctrl |= F_CPL_TX_TNL_LSO_IPHDRCHKOUT | 5017 F_CPL_TX_TNL_LSO_IPIDINCOUT; 5018 } 5019 tnl_lso->op_to_IpIdSplitOut = htobe32(ctrl); 5020 tnl_lso->IpIdOffsetOut = 0; 5021 tnl_lso->UdpLenSetOut_to_TnlHdrLen = 5022 htobe16(F_CPL_TX_TNL_LSO_UDPCHKCLROUT | 5023 F_CPL_TX_TNL_LSO_UDPLENSETOUT | 5024 V_CPL_TX_TNL_LSO_TNLHDRLEN(m0->m_pkthdr.l2hlen + 5025 m0->m_pkthdr.l3hlen + m0->m_pkthdr.l4hlen + 5026 m0->m_pkthdr.l5hlen) | 5027 V_CPL_TX_TNL_LSO_TNLTYPE(TX_TNL_TYPE_VXLAN)); 5028 tnl_lso->r1 = 0; 5029 5030 /* Inner headers. */ 5031 ctrl = V_CPL_TX_TNL_LSO_ETHHDRLEN( 5032 (m0->m_pkthdr.inner_l2hlen - ETHER_HDR_LEN) >> 2) | 5033 V_CPL_TX_TNL_LSO_IPHDRLEN(m0->m_pkthdr.inner_l3hlen >> 2) | 5034 V_CPL_TX_TNL_LSO_TCPHDRLEN(m0->m_pkthdr.inner_l4hlen >> 2); 5035 if (m0->m_pkthdr.inner_l3hlen == sizeof(struct ip6_hdr)) 5036 ctrl |= F_CPL_TX_TNL_LSO_IPV6; 5037 tnl_lso->Flow_to_TcpHdrLen = htobe32(ctrl); 5038 tnl_lso->IpIdOffset = 0; 5039 tnl_lso->IpIdSplit_to_Mss = 5040 htobe16(V_CPL_TX_TNL_LSO_MSS(m0->m_pkthdr.tso_segsz)); 5041 tnl_lso->TCPSeqOffset = 0; 5042 tnl_lso->EthLenOffset_Size = 5043 htobe32(V_CPL_TX_TNL_LSO_SIZE(m0->m_pkthdr.len)); 5044 5045 return (tnl_lso + 1); 5046 } 5047 5048 #define VM_TX_L2HDR_LEN 16 /* ethmacdst to vlantci */ 5049 5050 /* 5051 * Write a VM txpkt WR for this packet to the hardware descriptors, update the 5052 * software descriptor, and advance the pidx. It is guaranteed that enough 5053 * descriptors are available. 5054 * 5055 * The return value is the # of hardware descriptors used. 5056 */ 5057 static u_int 5058 write_txpkt_vm_wr(struct adapter *sc, struct sge_txq *txq, struct mbuf *m0) 5059 { 5060 struct sge_eq *eq; 5061 struct fw_eth_tx_pkt_vm_wr *wr; 5062 struct tx_sdesc *txsd; 5063 struct cpl_tx_pkt_core *cpl; 5064 uint32_t ctrl; /* used in many unrelated places */ 5065 uint64_t ctrl1; 5066 int len16, ndesc, pktlen, nsegs; 5067 caddr_t dst; 5068 5069 TXQ_LOCK_ASSERT_OWNED(txq); 5070 M_ASSERTPKTHDR(m0); 5071 5072 len16 = mbuf_len16(m0); 5073 nsegs = mbuf_nsegs(m0); 5074 pktlen = m0->m_pkthdr.len; 5075 ctrl = sizeof(struct cpl_tx_pkt_core); 5076 if (needs_tso(m0)) 5077 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 5078 ndesc = tx_len16_to_desc(len16); 5079 5080 /* Firmware work request header */ 5081 eq = &txq->eq; 5082 wr = (void *)&eq->desc[eq->pidx]; 5083 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_VM_WR) | 5084 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl)); 5085 5086 ctrl = V_FW_WR_LEN16(len16); 5087 wr->equiq_to_len16 = htobe32(ctrl); 5088 wr->r3[0] = 0; 5089 wr->r3[1] = 0; 5090 5091 /* 5092 * Copy over ethmacdst, ethmacsrc, ethtype, and vlantci. 5093 * vlantci is ignored unless the ethtype is 0x8100, so it's 5094 * simpler to always copy it rather than making it 5095 * conditional. Also, it seems that we do not have to set 5096 * vlantci or fake the ethtype when doing VLAN tag insertion. 5097 */ 5098 m_copydata(m0, 0, VM_TX_L2HDR_LEN, wr->ethmacdst); 5099 5100 if (needs_tso(m0)) { 5101 cpl = write_lso_cpl(wr + 1, m0); 5102 txq->tso_wrs++; 5103 } else 5104 cpl = (void *)(wr + 1); 5105 5106 /* Checksum offload */ 5107 ctrl1 = csum_to_ctrl(sc, m0); 5108 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS)) 5109 txq->txcsum++; /* some hardware assistance provided */ 5110 5111 /* VLAN tag insertion */ 5112 if (needs_vlan_insertion(m0)) { 5113 ctrl1 |= F_TXPKT_VLAN_VLD | 5114 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 5115 txq->vlan_insertion++; 5116 } 5117 5118 /* CPL header */ 5119 cpl->ctrl0 = txq->cpl_ctrl0; 5120 cpl->pack = 0; 5121 cpl->len = htobe16(pktlen); 5122 cpl->ctrl1 = htobe64(ctrl1); 5123 5124 /* SGL */ 5125 dst = (void *)(cpl + 1); 5126 5127 /* 5128 * A packet using TSO will use up an entire descriptor for the 5129 * firmware work request header, LSO CPL, and TX_PKT_XT CPL. 5130 * If this descriptor is the last descriptor in the ring, wrap 5131 * around to the front of the ring explicitly for the start of 5132 * the sgl. 5133 */ 5134 if (dst == (void *)&eq->desc[eq->sidx]) { 5135 dst = (void *)&eq->desc[0]; 5136 write_gl_to_txd(txq, m0, &dst, 0); 5137 } else 5138 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx); 5139 txq->sgl_wrs++; 5140 txq->txpkt_wrs++; 5141 5142 txsd = &txq->sdesc[eq->pidx]; 5143 txsd->m = m0; 5144 txsd->desc_used = ndesc; 5145 5146 return (ndesc); 5147 } 5148 5149 /* 5150 * Write a raw WR to the hardware descriptors, update the software 5151 * descriptor, and advance the pidx. It is guaranteed that enough 5152 * descriptors are available. 5153 * 5154 * The return value is the # of hardware descriptors used. 5155 */ 5156 static u_int 5157 write_raw_wr(struct sge_txq *txq, void *wr, struct mbuf *m0, u_int available) 5158 { 5159 struct sge_eq *eq = &txq->eq; 5160 struct tx_sdesc *txsd; 5161 struct mbuf *m; 5162 caddr_t dst; 5163 int len16, ndesc; 5164 5165 len16 = mbuf_len16(m0); 5166 ndesc = tx_len16_to_desc(len16); 5167 MPASS(ndesc <= available); 5168 5169 dst = wr; 5170 for (m = m0; m != NULL; m = m->m_next) 5171 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len); 5172 5173 txq->raw_wrs++; 5174 5175 txsd = &txq->sdesc[eq->pidx]; 5176 txsd->m = m0; 5177 txsd->desc_used = ndesc; 5178 5179 return (ndesc); 5180 } 5181 5182 /* 5183 * Write a txpkt WR for this packet to the hardware descriptors, update the 5184 * software descriptor, and advance the pidx. It is guaranteed that enough 5185 * descriptors are available. 5186 * 5187 * The return value is the # of hardware descriptors used. 5188 */ 5189 static u_int 5190 write_txpkt_wr(struct adapter *sc, struct sge_txq *txq, struct mbuf *m0, 5191 u_int available) 5192 { 5193 struct sge_eq *eq; 5194 struct fw_eth_tx_pkt_wr *wr; 5195 struct tx_sdesc *txsd; 5196 struct cpl_tx_pkt_core *cpl; 5197 uint32_t ctrl; /* used in many unrelated places */ 5198 uint64_t ctrl1; 5199 int len16, ndesc, pktlen, nsegs; 5200 caddr_t dst; 5201 5202 TXQ_LOCK_ASSERT_OWNED(txq); 5203 M_ASSERTPKTHDR(m0); 5204 5205 len16 = mbuf_len16(m0); 5206 nsegs = mbuf_nsegs(m0); 5207 pktlen = m0->m_pkthdr.len; 5208 ctrl = sizeof(struct cpl_tx_pkt_core); 5209 if (needs_tso(m0)) { 5210 if (needs_vxlan_tso(m0)) 5211 ctrl += sizeof(struct cpl_tx_tnl_lso); 5212 else 5213 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 5214 } else if (!(mbuf_cflags(m0) & MC_NOMAP) && pktlen <= imm_payload(2) && 5215 available >= 2) { 5216 /* Immediate data. Recalculate len16 and set nsegs to 0. */ 5217 ctrl += pktlen; 5218 len16 = howmany(sizeof(struct fw_eth_tx_pkt_wr) + 5219 sizeof(struct cpl_tx_pkt_core) + pktlen, 16); 5220 nsegs = 0; 5221 } 5222 ndesc = tx_len16_to_desc(len16); 5223 MPASS(ndesc <= available); 5224 5225 /* Firmware work request header */ 5226 eq = &txq->eq; 5227 wr = (void *)&eq->desc[eq->pidx]; 5228 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_WR) | 5229 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl)); 5230 5231 ctrl = V_FW_WR_LEN16(len16); 5232 wr->equiq_to_len16 = htobe32(ctrl); 5233 wr->r3 = 0; 5234 5235 if (needs_tso(m0)) { 5236 if (needs_vxlan_tso(m0)) { 5237 cpl = write_tnl_lso_cpl(wr + 1, m0); 5238 txq->vxlan_tso_wrs++; 5239 } else { 5240 cpl = write_lso_cpl(wr + 1, m0); 5241 txq->tso_wrs++; 5242 } 5243 } else 5244 cpl = (void *)(wr + 1); 5245 5246 /* Checksum offload */ 5247 ctrl1 = csum_to_ctrl(sc, m0); 5248 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS)) { 5249 /* some hardware assistance provided */ 5250 if (needs_vxlan_csum(m0)) 5251 txq->vxlan_txcsum++; 5252 else 5253 txq->txcsum++; 5254 } 5255 5256 /* VLAN tag insertion */ 5257 if (needs_vlan_insertion(m0)) { 5258 ctrl1 |= F_TXPKT_VLAN_VLD | 5259 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 5260 txq->vlan_insertion++; 5261 } 5262 5263 /* CPL header */ 5264 cpl->ctrl0 = txq->cpl_ctrl0; 5265 cpl->pack = 0; 5266 cpl->len = htobe16(pktlen); 5267 cpl->ctrl1 = htobe64(ctrl1); 5268 5269 /* SGL */ 5270 dst = (void *)(cpl + 1); 5271 if (__predict_false((uintptr_t)dst == (uintptr_t)&eq->desc[eq->sidx])) 5272 dst = (caddr_t)&eq->desc[0]; 5273 if (nsegs > 0) { 5274 5275 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx); 5276 txq->sgl_wrs++; 5277 } else { 5278 struct mbuf *m; 5279 5280 for (m = m0; m != NULL; m = m->m_next) { 5281 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len); 5282 #ifdef INVARIANTS 5283 pktlen -= m->m_len; 5284 #endif 5285 } 5286 #ifdef INVARIANTS 5287 KASSERT(pktlen == 0, ("%s: %d bytes left.", __func__, pktlen)); 5288 #endif 5289 txq->imm_wrs++; 5290 } 5291 5292 txq->txpkt_wrs++; 5293 5294 txsd = &txq->sdesc[eq->pidx]; 5295 txsd->m = m0; 5296 txsd->desc_used = ndesc; 5297 5298 return (ndesc); 5299 } 5300 5301 static inline bool 5302 cmp_l2hdr(struct txpkts *txp, struct mbuf *m) 5303 { 5304 int len; 5305 5306 MPASS(txp->npkt > 0); 5307 MPASS(m->m_len >= VM_TX_L2HDR_LEN); 5308 5309 if (txp->ethtype == be16toh(ETHERTYPE_VLAN)) 5310 len = VM_TX_L2HDR_LEN; 5311 else 5312 len = sizeof(struct ether_header); 5313 5314 return (memcmp(m->m_data, &txp->ethmacdst[0], len) != 0); 5315 } 5316 5317 static inline void 5318 save_l2hdr(struct txpkts *txp, struct mbuf *m) 5319 { 5320 MPASS(m->m_len >= VM_TX_L2HDR_LEN); 5321 5322 memcpy(&txp->ethmacdst[0], mtod(m, const void *), VM_TX_L2HDR_LEN); 5323 } 5324 5325 static int 5326 add_to_txpkts_vf(struct adapter *sc, struct sge_txq *txq, struct mbuf *m, 5327 int avail, bool *send) 5328 { 5329 struct txpkts *txp = &txq->txp; 5330 5331 /* Cannot have TSO and coalesce at the same time. */ 5332 if (cannot_use_txpkts(m)) { 5333 cannot_coalesce: 5334 *send = txp->npkt > 0; 5335 return (EINVAL); 5336 } 5337 5338 /* VF allows coalescing of type 1 (1 GL) only */ 5339 if (mbuf_nsegs(m) > 1) 5340 goto cannot_coalesce; 5341 5342 *send = false; 5343 if (txp->npkt > 0) { 5344 MPASS(tx_len16_to_desc(txp->len16) <= avail); 5345 MPASS(txp->npkt < txp->max_npkt); 5346 MPASS(txp->wr_type == 1); /* VF supports type 1 only */ 5347 5348 if (tx_len16_to_desc(txp->len16 + txpkts1_len16()) > avail) { 5349 retry_after_send: 5350 *send = true; 5351 return (EAGAIN); 5352 } 5353 if (m->m_pkthdr.len + txp->plen > 65535) 5354 goto retry_after_send; 5355 if (cmp_l2hdr(txp, m)) 5356 goto retry_after_send; 5357 5358 txp->len16 += txpkts1_len16(); 5359 txp->plen += m->m_pkthdr.len; 5360 txp->mb[txp->npkt++] = m; 5361 if (txp->npkt == txp->max_npkt) 5362 *send = true; 5363 } else { 5364 txp->len16 = howmany(sizeof(struct fw_eth_tx_pkts_vm_wr), 16) + 5365 txpkts1_len16(); 5366 if (tx_len16_to_desc(txp->len16) > avail) 5367 goto cannot_coalesce; 5368 txp->npkt = 1; 5369 txp->wr_type = 1; 5370 txp->plen = m->m_pkthdr.len; 5371 txp->mb[0] = m; 5372 save_l2hdr(txp, m); 5373 } 5374 return (0); 5375 } 5376 5377 static int 5378 add_to_txpkts_pf(struct adapter *sc, struct sge_txq *txq, struct mbuf *m, 5379 int avail, bool *send) 5380 { 5381 struct txpkts *txp = &txq->txp; 5382 int nsegs; 5383 5384 MPASS(!(sc->flags & IS_VF)); 5385 5386 /* Cannot have TSO and coalesce at the same time. */ 5387 if (cannot_use_txpkts(m)) { 5388 cannot_coalesce: 5389 *send = txp->npkt > 0; 5390 return (EINVAL); 5391 } 5392 5393 *send = false; 5394 nsegs = mbuf_nsegs(m); 5395 if (txp->npkt == 0) { 5396 if (m->m_pkthdr.len > 65535) 5397 goto cannot_coalesce; 5398 if (nsegs > 1) { 5399 txp->wr_type = 0; 5400 txp->len16 = 5401 howmany(sizeof(struct fw_eth_tx_pkts_wr), 16) + 5402 txpkts0_len16(nsegs); 5403 } else { 5404 txp->wr_type = 1; 5405 txp->len16 = 5406 howmany(sizeof(struct fw_eth_tx_pkts_wr), 16) + 5407 txpkts1_len16(); 5408 } 5409 if (tx_len16_to_desc(txp->len16) > avail) 5410 goto cannot_coalesce; 5411 txp->npkt = 1; 5412 txp->plen = m->m_pkthdr.len; 5413 txp->mb[0] = m; 5414 } else { 5415 MPASS(tx_len16_to_desc(txp->len16) <= avail); 5416 MPASS(txp->npkt < txp->max_npkt); 5417 5418 if (m->m_pkthdr.len + txp->plen > 65535) { 5419 retry_after_send: 5420 *send = true; 5421 return (EAGAIN); 5422 } 5423 5424 MPASS(txp->wr_type == 0 || txp->wr_type == 1); 5425 if (txp->wr_type == 0) { 5426 if (tx_len16_to_desc(txp->len16 + 5427 txpkts0_len16(nsegs)) > min(avail, SGE_MAX_WR_NDESC)) 5428 goto retry_after_send; 5429 txp->len16 += txpkts0_len16(nsegs); 5430 } else { 5431 if (nsegs != 1) 5432 goto retry_after_send; 5433 if (tx_len16_to_desc(txp->len16 + txpkts1_len16()) > 5434 avail) 5435 goto retry_after_send; 5436 txp->len16 += txpkts1_len16(); 5437 } 5438 5439 txp->plen += m->m_pkthdr.len; 5440 txp->mb[txp->npkt++] = m; 5441 if (txp->npkt == txp->max_npkt) 5442 *send = true; 5443 } 5444 return (0); 5445 } 5446 5447 /* 5448 * Write a txpkts WR for the packets in txp to the hardware descriptors, update 5449 * the software descriptor, and advance the pidx. It is guaranteed that enough 5450 * descriptors are available. 5451 * 5452 * The return value is the # of hardware descriptors used. 5453 */ 5454 static u_int 5455 write_txpkts_wr(struct adapter *sc, struct sge_txq *txq) 5456 { 5457 const struct txpkts *txp = &txq->txp; 5458 struct sge_eq *eq = &txq->eq; 5459 struct fw_eth_tx_pkts_wr *wr; 5460 struct tx_sdesc *txsd; 5461 struct cpl_tx_pkt_core *cpl; 5462 uint64_t ctrl1; 5463 int ndesc, i, checkwrap; 5464 struct mbuf *m, *last; 5465 void *flitp; 5466 5467 TXQ_LOCK_ASSERT_OWNED(txq); 5468 MPASS(txp->npkt > 0); 5469 MPASS(txp->len16 <= howmany(SGE_MAX_WR_LEN, 16)); 5470 5471 wr = (void *)&eq->desc[eq->pidx]; 5472 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR)); 5473 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(txp->len16)); 5474 wr->plen = htobe16(txp->plen); 5475 wr->npkt = txp->npkt; 5476 wr->r3 = 0; 5477 wr->type = txp->wr_type; 5478 flitp = wr + 1; 5479 5480 /* 5481 * At this point we are 16B into a hardware descriptor. If checkwrap is 5482 * set then we know the WR is going to wrap around somewhere. We'll 5483 * check for that at appropriate points. 5484 */ 5485 ndesc = tx_len16_to_desc(txp->len16); 5486 last = NULL; 5487 checkwrap = eq->sidx - ndesc < eq->pidx; 5488 for (i = 0; i < txp->npkt; i++) { 5489 m = txp->mb[i]; 5490 if (txp->wr_type == 0) { 5491 struct ulp_txpkt *ulpmc; 5492 struct ulptx_idata *ulpsc; 5493 5494 /* ULP master command */ 5495 ulpmc = flitp; 5496 ulpmc->cmd_dest = htobe32(V_ULPTX_CMD(ULP_TX_PKT) | 5497 V_ULP_TXPKT_DEST(0) | V_ULP_TXPKT_FID(eq->iqid)); 5498 ulpmc->len = htobe32(txpkts0_len16(mbuf_nsegs(m))); 5499 5500 /* ULP subcommand */ 5501 ulpsc = (void *)(ulpmc + 1); 5502 ulpsc->cmd_more = htobe32(V_ULPTX_CMD(ULP_TX_SC_IMM) | 5503 F_ULP_TX_SC_MORE); 5504 ulpsc->len = htobe32(sizeof(struct cpl_tx_pkt_core)); 5505 5506 cpl = (void *)(ulpsc + 1); 5507 if (checkwrap && 5508 (uintptr_t)cpl == (uintptr_t)&eq->desc[eq->sidx]) 5509 cpl = (void *)&eq->desc[0]; 5510 } else { 5511 cpl = flitp; 5512 } 5513 5514 /* Checksum offload */ 5515 ctrl1 = csum_to_ctrl(sc, m); 5516 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS)) { 5517 /* some hardware assistance provided */ 5518 if (needs_vxlan_csum(m)) 5519 txq->vxlan_txcsum++; 5520 else 5521 txq->txcsum++; 5522 } 5523 5524 /* VLAN tag insertion */ 5525 if (needs_vlan_insertion(m)) { 5526 ctrl1 |= F_TXPKT_VLAN_VLD | 5527 V_TXPKT_VLAN(m->m_pkthdr.ether_vtag); 5528 txq->vlan_insertion++; 5529 } 5530 5531 /* CPL header */ 5532 cpl->ctrl0 = txq->cpl_ctrl0; 5533 cpl->pack = 0; 5534 cpl->len = htobe16(m->m_pkthdr.len); 5535 cpl->ctrl1 = htobe64(ctrl1); 5536 5537 flitp = cpl + 1; 5538 if (checkwrap && 5539 (uintptr_t)flitp == (uintptr_t)&eq->desc[eq->sidx]) 5540 flitp = (void *)&eq->desc[0]; 5541 5542 write_gl_to_txd(txq, m, (caddr_t *)(&flitp), checkwrap); 5543 5544 if (last != NULL) 5545 last->m_nextpkt = m; 5546 last = m; 5547 } 5548 5549 txq->sgl_wrs++; 5550 if (txp->wr_type == 0) { 5551 txq->txpkts0_pkts += txp->npkt; 5552 txq->txpkts0_wrs++; 5553 } else { 5554 txq->txpkts1_pkts += txp->npkt; 5555 txq->txpkts1_wrs++; 5556 } 5557 5558 txsd = &txq->sdesc[eq->pidx]; 5559 txsd->m = txp->mb[0]; 5560 txsd->desc_used = ndesc; 5561 5562 return (ndesc); 5563 } 5564 5565 static u_int 5566 write_txpkts_vm_wr(struct adapter *sc, struct sge_txq *txq) 5567 { 5568 const struct txpkts *txp = &txq->txp; 5569 struct sge_eq *eq = &txq->eq; 5570 struct fw_eth_tx_pkts_vm_wr *wr; 5571 struct tx_sdesc *txsd; 5572 struct cpl_tx_pkt_core *cpl; 5573 uint64_t ctrl1; 5574 int ndesc, i; 5575 struct mbuf *m, *last; 5576 void *flitp; 5577 5578 TXQ_LOCK_ASSERT_OWNED(txq); 5579 MPASS(txp->npkt > 0); 5580 MPASS(txp->wr_type == 1); /* VF supports type 1 only */ 5581 MPASS(txp->mb[0] != NULL); 5582 MPASS(txp->len16 <= howmany(SGE_MAX_WR_LEN, 16)); 5583 5584 wr = (void *)&eq->desc[eq->pidx]; 5585 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_VM_WR)); 5586 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(txp->len16)); 5587 wr->r3 = 0; 5588 wr->plen = htobe16(txp->plen); 5589 wr->npkt = txp->npkt; 5590 wr->r4 = 0; 5591 memcpy(&wr->ethmacdst[0], &txp->ethmacdst[0], 16); 5592 flitp = wr + 1; 5593 5594 /* 5595 * At this point we are 32B into a hardware descriptor. Each mbuf in 5596 * the WR will take 32B so we check for the end of the descriptor ring 5597 * before writing odd mbufs (mb[1], 3, 5, ..) 5598 */ 5599 ndesc = tx_len16_to_desc(txp->len16); 5600 last = NULL; 5601 for (i = 0; i < txp->npkt; i++) { 5602 m = txp->mb[i]; 5603 if (i & 1 && (uintptr_t)flitp == (uintptr_t)&eq->desc[eq->sidx]) 5604 flitp = &eq->desc[0]; 5605 cpl = flitp; 5606 5607 /* Checksum offload */ 5608 ctrl1 = csum_to_ctrl(sc, m); 5609 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS)) 5610 txq->txcsum++; /* some hardware assistance provided */ 5611 5612 /* VLAN tag insertion */ 5613 if (needs_vlan_insertion(m)) { 5614 ctrl1 |= F_TXPKT_VLAN_VLD | 5615 V_TXPKT_VLAN(m->m_pkthdr.ether_vtag); 5616 txq->vlan_insertion++; 5617 } 5618 5619 /* CPL header */ 5620 cpl->ctrl0 = txq->cpl_ctrl0; 5621 cpl->pack = 0; 5622 cpl->len = htobe16(m->m_pkthdr.len); 5623 cpl->ctrl1 = htobe64(ctrl1); 5624 5625 flitp = cpl + 1; 5626 MPASS(mbuf_nsegs(m) == 1); 5627 write_gl_to_txd(txq, m, (caddr_t *)(&flitp), 0); 5628 5629 if (last != NULL) 5630 last->m_nextpkt = m; 5631 last = m; 5632 } 5633 5634 txq->sgl_wrs++; 5635 txq->txpkts1_pkts += txp->npkt; 5636 txq->txpkts1_wrs++; 5637 5638 txsd = &txq->sdesc[eq->pidx]; 5639 txsd->m = txp->mb[0]; 5640 txsd->desc_used = ndesc; 5641 5642 return (ndesc); 5643 } 5644 5645 /* 5646 * If the SGL ends on an address that is not 16 byte aligned, this function will 5647 * add a 0 filled flit at the end. 5648 */ 5649 static void 5650 write_gl_to_txd(struct sge_txq *txq, struct mbuf *m, caddr_t *to, int checkwrap) 5651 { 5652 struct sge_eq *eq = &txq->eq; 5653 struct sglist *gl = txq->gl; 5654 struct sglist_seg *seg; 5655 __be64 *flitp, *wrap; 5656 struct ulptx_sgl *usgl; 5657 int i, nflits, nsegs; 5658 5659 KASSERT(((uintptr_t)(*to) & 0xf) == 0, 5660 ("%s: SGL must start at a 16 byte boundary: %p", __func__, *to)); 5661 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]); 5662 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]); 5663 5664 get_pkt_gl(m, gl); 5665 nsegs = gl->sg_nseg; 5666 MPASS(nsegs > 0); 5667 5668 nflits = (3 * (nsegs - 1)) / 2 + ((nsegs - 1) & 1) + 2; 5669 flitp = (__be64 *)(*to); 5670 wrap = (__be64 *)(&eq->desc[eq->sidx]); 5671 seg = &gl->sg_segs[0]; 5672 usgl = (void *)flitp; 5673 5674 /* 5675 * We start at a 16 byte boundary somewhere inside the tx descriptor 5676 * ring, so we're at least 16 bytes away from the status page. There is 5677 * no chance of a wrap around in the middle of usgl (which is 16 bytes). 5678 */ 5679 5680 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 5681 V_ULPTX_NSGE(nsegs)); 5682 usgl->len0 = htobe32(seg->ss_len); 5683 usgl->addr0 = htobe64(seg->ss_paddr); 5684 seg++; 5685 5686 if (checkwrap == 0 || (uintptr_t)(flitp + nflits) <= (uintptr_t)wrap) { 5687 5688 /* Won't wrap around at all */ 5689 5690 for (i = 0; i < nsegs - 1; i++, seg++) { 5691 usgl->sge[i / 2].len[i & 1] = htobe32(seg->ss_len); 5692 usgl->sge[i / 2].addr[i & 1] = htobe64(seg->ss_paddr); 5693 } 5694 if (i & 1) 5695 usgl->sge[i / 2].len[1] = htobe32(0); 5696 flitp += nflits; 5697 } else { 5698 5699 /* Will wrap somewhere in the rest of the SGL */ 5700 5701 /* 2 flits already written, write the rest flit by flit */ 5702 flitp = (void *)(usgl + 1); 5703 for (i = 0; i < nflits - 2; i++) { 5704 if (flitp == wrap) 5705 flitp = (void *)eq->desc; 5706 *flitp++ = get_flit(seg, nsegs - 1, i); 5707 } 5708 } 5709 5710 if (nflits & 1) { 5711 MPASS(((uintptr_t)flitp) & 0xf); 5712 *flitp++ = 0; 5713 } 5714 5715 MPASS((((uintptr_t)flitp) & 0xf) == 0); 5716 if (__predict_false(flitp == wrap)) 5717 *to = (void *)eq->desc; 5718 else 5719 *to = (void *)flitp; 5720 } 5721 5722 static inline void 5723 copy_to_txd(struct sge_eq *eq, caddr_t from, caddr_t *to, int len) 5724 { 5725 5726 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]); 5727 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]); 5728 5729 if (__predict_true((uintptr_t)(*to) + len <= 5730 (uintptr_t)&eq->desc[eq->sidx])) { 5731 bcopy(from, *to, len); 5732 (*to) += len; 5733 } else { 5734 int portion = (uintptr_t)&eq->desc[eq->sidx] - (uintptr_t)(*to); 5735 5736 bcopy(from, *to, portion); 5737 from += portion; 5738 portion = len - portion; /* remaining */ 5739 bcopy(from, (void *)eq->desc, portion); 5740 (*to) = (caddr_t)eq->desc + portion; 5741 } 5742 } 5743 5744 static inline void 5745 ring_eq_db(struct adapter *sc, struct sge_eq *eq, u_int n) 5746 { 5747 u_int db; 5748 5749 MPASS(n > 0); 5750 5751 db = eq->doorbells; 5752 if (n > 1) 5753 clrbit(&db, DOORBELL_WCWR); 5754 wmb(); 5755 5756 switch (ffs(db) - 1) { 5757 case DOORBELL_UDB: 5758 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n)); 5759 break; 5760 5761 case DOORBELL_WCWR: { 5762 volatile uint64_t *dst, *src; 5763 int i; 5764 5765 /* 5766 * Queues whose 128B doorbell segment fits in the page do not 5767 * use relative qid (udb_qid is always 0). Only queues with 5768 * doorbell segments can do WCWR. 5769 */ 5770 KASSERT(eq->udb_qid == 0 && n == 1, 5771 ("%s: inappropriate doorbell (0x%x, %d, %d) for eq %p", 5772 __func__, eq->doorbells, n, eq->dbidx, eq)); 5773 5774 dst = (volatile void *)((uintptr_t)eq->udb + UDBS_WR_OFFSET - 5775 UDBS_DB_OFFSET); 5776 i = eq->dbidx; 5777 src = (void *)&eq->desc[i]; 5778 while (src != (void *)&eq->desc[i + 1]) 5779 *dst++ = *src++; 5780 wmb(); 5781 break; 5782 } 5783 5784 case DOORBELL_UDBWC: 5785 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n)); 5786 wmb(); 5787 break; 5788 5789 case DOORBELL_KDB: 5790 t4_write_reg(sc, sc->sge_kdoorbell_reg, 5791 V_QID(eq->cntxt_id) | V_PIDX(n)); 5792 break; 5793 } 5794 5795 IDXINCR(eq->dbidx, n, eq->sidx); 5796 } 5797 5798 static inline u_int 5799 reclaimable_tx_desc(struct sge_eq *eq) 5800 { 5801 uint16_t hw_cidx; 5802 5803 hw_cidx = read_hw_cidx(eq); 5804 return (IDXDIFF(hw_cidx, eq->cidx, eq->sidx)); 5805 } 5806 5807 static inline u_int 5808 total_available_tx_desc(struct sge_eq *eq) 5809 { 5810 uint16_t hw_cidx, pidx; 5811 5812 hw_cidx = read_hw_cidx(eq); 5813 pidx = eq->pidx; 5814 5815 if (pidx == hw_cidx) 5816 return (eq->sidx - 1); 5817 else 5818 return (IDXDIFF(hw_cidx, pidx, eq->sidx) - 1); 5819 } 5820 5821 static inline uint16_t 5822 read_hw_cidx(struct sge_eq *eq) 5823 { 5824 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx]; 5825 uint16_t cidx = spg->cidx; /* stable snapshot */ 5826 5827 return (be16toh(cidx)); 5828 } 5829 5830 /* 5831 * Reclaim 'n' descriptors approximately. 5832 */ 5833 static u_int 5834 reclaim_tx_descs(struct sge_txq *txq, u_int n) 5835 { 5836 struct tx_sdesc *txsd; 5837 struct sge_eq *eq = &txq->eq; 5838 u_int can_reclaim, reclaimed; 5839 5840 TXQ_LOCK_ASSERT_OWNED(txq); 5841 MPASS(n > 0); 5842 5843 reclaimed = 0; 5844 can_reclaim = reclaimable_tx_desc(eq); 5845 while (can_reclaim && reclaimed < n) { 5846 int ndesc; 5847 struct mbuf *m, *nextpkt; 5848 5849 txsd = &txq->sdesc[eq->cidx]; 5850 ndesc = txsd->desc_used; 5851 5852 /* Firmware doesn't return "partial" credits. */ 5853 KASSERT(can_reclaim >= ndesc, 5854 ("%s: unexpected number of credits: %d, %d", 5855 __func__, can_reclaim, ndesc)); 5856 KASSERT(ndesc != 0, 5857 ("%s: descriptor with no credits: cidx %d", 5858 __func__, eq->cidx)); 5859 5860 for (m = txsd->m; m != NULL; m = nextpkt) { 5861 nextpkt = m->m_nextpkt; 5862 m->m_nextpkt = NULL; 5863 m_freem(m); 5864 } 5865 reclaimed += ndesc; 5866 can_reclaim -= ndesc; 5867 IDXINCR(eq->cidx, ndesc, eq->sidx); 5868 } 5869 5870 return (reclaimed); 5871 } 5872 5873 static void 5874 tx_reclaim(void *arg, int n) 5875 { 5876 struct sge_txq *txq = arg; 5877 struct sge_eq *eq = &txq->eq; 5878 5879 do { 5880 if (TXQ_TRYLOCK(txq) == 0) 5881 break; 5882 n = reclaim_tx_descs(txq, 32); 5883 if (eq->cidx == eq->pidx) 5884 eq->equeqidx = eq->pidx; 5885 TXQ_UNLOCK(txq); 5886 } while (n > 0); 5887 } 5888 5889 static __be64 5890 get_flit(struct sglist_seg *segs, int nsegs, int idx) 5891 { 5892 int i = (idx / 3) * 2; 5893 5894 switch (idx % 3) { 5895 case 0: { 5896 uint64_t rc; 5897 5898 rc = (uint64_t)segs[i].ss_len << 32; 5899 if (i + 1 < nsegs) 5900 rc |= (uint64_t)(segs[i + 1].ss_len); 5901 5902 return (htobe64(rc)); 5903 } 5904 case 1: 5905 return (htobe64(segs[i].ss_paddr)); 5906 case 2: 5907 return (htobe64(segs[i + 1].ss_paddr)); 5908 } 5909 5910 return (0); 5911 } 5912 5913 static int 5914 find_refill_source(struct adapter *sc, int maxp, bool packing) 5915 { 5916 int i, zidx = -1; 5917 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[0]; 5918 5919 if (packing) { 5920 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) { 5921 if (rxb->hwidx2 == -1) 5922 continue; 5923 if (rxb->size1 < PAGE_SIZE && 5924 rxb->size1 < largest_rx_cluster) 5925 continue; 5926 if (rxb->size1 > largest_rx_cluster) 5927 break; 5928 MPASS(rxb->size1 - rxb->size2 >= CL_METADATA_SIZE); 5929 if (rxb->size2 >= maxp) 5930 return (i); 5931 zidx = i; 5932 } 5933 } else { 5934 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) { 5935 if (rxb->hwidx1 == -1) 5936 continue; 5937 if (rxb->size1 > largest_rx_cluster) 5938 break; 5939 if (rxb->size1 >= maxp) 5940 return (i); 5941 zidx = i; 5942 } 5943 } 5944 5945 return (zidx); 5946 } 5947 5948 static void 5949 add_fl_to_sfl(struct adapter *sc, struct sge_fl *fl) 5950 { 5951 mtx_lock(&sc->sfl_lock); 5952 FL_LOCK(fl); 5953 if ((fl->flags & FL_DOOMED) == 0) { 5954 fl->flags |= FL_STARVING; 5955 TAILQ_INSERT_TAIL(&sc->sfl, fl, link); 5956 callout_reset(&sc->sfl_callout, hz / 5, refill_sfl, sc); 5957 } 5958 FL_UNLOCK(fl); 5959 mtx_unlock(&sc->sfl_lock); 5960 } 5961 5962 static void 5963 handle_wrq_egr_update(struct adapter *sc, struct sge_eq *eq) 5964 { 5965 struct sge_wrq *wrq = (void *)eq; 5966 5967 atomic_readandclear_int(&eq->equiq); 5968 taskqueue_enqueue(sc->tq[eq->tx_chan], &wrq->wrq_tx_task); 5969 } 5970 5971 static void 5972 handle_eth_egr_update(struct adapter *sc, struct sge_eq *eq) 5973 { 5974 struct sge_txq *txq = (void *)eq; 5975 5976 MPASS((eq->flags & EQ_TYPEMASK) == EQ_ETH); 5977 5978 atomic_readandclear_int(&eq->equiq); 5979 if (mp_ring_is_idle(txq->r)) 5980 taskqueue_enqueue(sc->tq[eq->tx_chan], &txq->tx_reclaim_task); 5981 else 5982 mp_ring_check_drainage(txq->r, 64); 5983 } 5984 5985 static int 5986 handle_sge_egr_update(struct sge_iq *iq, const struct rss_header *rss, 5987 struct mbuf *m) 5988 { 5989 const struct cpl_sge_egr_update *cpl = (const void *)(rss + 1); 5990 unsigned int qid = G_EGR_QID(ntohl(cpl->opcode_qid)); 5991 struct adapter *sc = iq->adapter; 5992 struct sge *s = &sc->sge; 5993 struct sge_eq *eq; 5994 static void (*h[])(struct adapter *, struct sge_eq *) = {NULL, 5995 &handle_wrq_egr_update, &handle_eth_egr_update, 5996 &handle_wrq_egr_update}; 5997 5998 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 5999 rss->opcode)); 6000 6001 eq = s->eqmap[qid - s->eq_start - s->eq_base]; 6002 (*h[eq->flags & EQ_TYPEMASK])(sc, eq); 6003 6004 return (0); 6005 } 6006 6007 /* handle_fw_msg works for both fw4_msg and fw6_msg because this is valid */ 6008 CTASSERT(offsetof(struct cpl_fw4_msg, data) == \ 6009 offsetof(struct cpl_fw6_msg, data)); 6010 6011 static int 6012 handle_fw_msg(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 6013 { 6014 struct adapter *sc = iq->adapter; 6015 const struct cpl_fw6_msg *cpl = (const void *)(rss + 1); 6016 6017 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 6018 rss->opcode)); 6019 6020 if (cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL) { 6021 const struct rss_header *rss2; 6022 6023 rss2 = (const struct rss_header *)&cpl->data[0]; 6024 return (t4_cpl_handler[rss2->opcode](iq, rss2, m)); 6025 } 6026 6027 return (t4_fw_msg_handler[cpl->type](sc, &cpl->data[0])); 6028 } 6029 6030 /** 6031 * t4_handle_wrerr_rpl - process a FW work request error message 6032 * @adap: the adapter 6033 * @rpl: start of the FW message 6034 */ 6035 static int 6036 t4_handle_wrerr_rpl(struct adapter *adap, const __be64 *rpl) 6037 { 6038 u8 opcode = *(const u8 *)rpl; 6039 const struct fw_error_cmd *e = (const void *)rpl; 6040 unsigned int i; 6041 6042 if (opcode != FW_ERROR_CMD) { 6043 log(LOG_ERR, 6044 "%s: Received WRERR_RPL message with opcode %#x\n", 6045 device_get_nameunit(adap->dev), opcode); 6046 return (EINVAL); 6047 } 6048 log(LOG_ERR, "%s: FW_ERROR (%s) ", device_get_nameunit(adap->dev), 6049 G_FW_ERROR_CMD_FATAL(be32toh(e->op_to_type)) ? "fatal" : 6050 "non-fatal"); 6051 switch (G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type))) { 6052 case FW_ERROR_TYPE_EXCEPTION: 6053 log(LOG_ERR, "exception info:\n"); 6054 for (i = 0; i < nitems(e->u.exception.info); i++) 6055 log(LOG_ERR, "%s%08x", i == 0 ? "\t" : " ", 6056 be32toh(e->u.exception.info[i])); 6057 log(LOG_ERR, "\n"); 6058 break; 6059 case FW_ERROR_TYPE_HWMODULE: 6060 log(LOG_ERR, "HW module regaddr %08x regval %08x\n", 6061 be32toh(e->u.hwmodule.regaddr), 6062 be32toh(e->u.hwmodule.regval)); 6063 break; 6064 case FW_ERROR_TYPE_WR: 6065 log(LOG_ERR, "WR cidx %d PF %d VF %d eqid %d hdr:\n", 6066 be16toh(e->u.wr.cidx), 6067 G_FW_ERROR_CMD_PFN(be16toh(e->u.wr.pfn_vfn)), 6068 G_FW_ERROR_CMD_VFN(be16toh(e->u.wr.pfn_vfn)), 6069 be32toh(e->u.wr.eqid)); 6070 for (i = 0; i < nitems(e->u.wr.wrhdr); i++) 6071 log(LOG_ERR, "%s%02x", i == 0 ? "\t" : " ", 6072 e->u.wr.wrhdr[i]); 6073 log(LOG_ERR, "\n"); 6074 break; 6075 case FW_ERROR_TYPE_ACL: 6076 log(LOG_ERR, "ACL cidx %d PF %d VF %d eqid %d %s", 6077 be16toh(e->u.acl.cidx), 6078 G_FW_ERROR_CMD_PFN(be16toh(e->u.acl.pfn_vfn)), 6079 G_FW_ERROR_CMD_VFN(be16toh(e->u.acl.pfn_vfn)), 6080 be32toh(e->u.acl.eqid), 6081 G_FW_ERROR_CMD_MV(be16toh(e->u.acl.mv_pkd)) ? "vlanid" : 6082 "MAC"); 6083 for (i = 0; i < nitems(e->u.acl.val); i++) 6084 log(LOG_ERR, " %02x", e->u.acl.val[i]); 6085 log(LOG_ERR, "\n"); 6086 break; 6087 default: 6088 log(LOG_ERR, "type %#x\n", 6089 G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type))); 6090 return (EINVAL); 6091 } 6092 return (0); 6093 } 6094 6095 static inline bool 6096 bufidx_used(struct adapter *sc, int idx) 6097 { 6098 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[0]; 6099 int i; 6100 6101 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) { 6102 if (rxb->size1 > largest_rx_cluster) 6103 continue; 6104 if (rxb->hwidx1 == idx || rxb->hwidx2 == idx) 6105 return (true); 6106 } 6107 6108 return (false); 6109 } 6110 6111 static int 6112 sysctl_bufsizes(SYSCTL_HANDLER_ARGS) 6113 { 6114 struct adapter *sc = arg1; 6115 struct sge_params *sp = &sc->params.sge; 6116 int i, rc; 6117 struct sbuf sb; 6118 char c; 6119 6120 sbuf_new(&sb, NULL, 128, SBUF_AUTOEXTEND); 6121 for (i = 0; i < SGE_FLBUF_SIZES; i++) { 6122 if (bufidx_used(sc, i)) 6123 c = '*'; 6124 else 6125 c = '\0'; 6126 6127 sbuf_printf(&sb, "%u%c ", sp->sge_fl_buffer_size[i], c); 6128 } 6129 sbuf_trim(&sb); 6130 sbuf_finish(&sb); 6131 rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req); 6132 sbuf_delete(&sb); 6133 return (rc); 6134 } 6135 6136 #ifdef RATELIMIT 6137 /* 6138 * len16 for a txpkt WR with a GL. Includes the firmware work request header. 6139 */ 6140 static inline u_int 6141 txpkt_eo_len16(u_int nsegs, u_int immhdrs, u_int tso) 6142 { 6143 u_int n; 6144 6145 MPASS(immhdrs > 0); 6146 6147 n = roundup2(sizeof(struct fw_eth_tx_eo_wr) + 6148 sizeof(struct cpl_tx_pkt_core) + immhdrs, 16); 6149 if (__predict_false(nsegs == 0)) 6150 goto done; 6151 6152 nsegs--; /* first segment is part of ulptx_sgl */ 6153 n += sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 6154 if (tso) 6155 n += sizeof(struct cpl_tx_pkt_lso_core); 6156 6157 done: 6158 return (howmany(n, 16)); 6159 } 6160 6161 #define ETID_FLOWC_NPARAMS 6 6162 #define ETID_FLOWC_LEN (roundup2((sizeof(struct fw_flowc_wr) + \ 6163 ETID_FLOWC_NPARAMS * sizeof(struct fw_flowc_mnemval)), 16)) 6164 #define ETID_FLOWC_LEN16 (howmany(ETID_FLOWC_LEN, 16)) 6165 6166 static int 6167 send_etid_flowc_wr(struct cxgbe_rate_tag *cst, struct port_info *pi, 6168 struct vi_info *vi) 6169 { 6170 struct wrq_cookie cookie; 6171 u_int pfvf = pi->adapter->pf << S_FW_VIID_PFN; 6172 struct fw_flowc_wr *flowc; 6173 6174 mtx_assert(&cst->lock, MA_OWNED); 6175 MPASS((cst->flags & (EO_FLOWC_PENDING | EO_FLOWC_RPL_PENDING)) == 6176 EO_FLOWC_PENDING); 6177 6178 flowc = start_wrq_wr(&cst->eo_txq->wrq, ETID_FLOWC_LEN16, &cookie); 6179 if (__predict_false(flowc == NULL)) 6180 return (ENOMEM); 6181 6182 bzero(flowc, ETID_FLOWC_LEN); 6183 flowc->op_to_nparams = htobe32(V_FW_WR_OP(FW_FLOWC_WR) | 6184 V_FW_FLOWC_WR_NPARAMS(ETID_FLOWC_NPARAMS) | V_FW_WR_COMPL(0)); 6185 flowc->flowid_len16 = htonl(V_FW_WR_LEN16(ETID_FLOWC_LEN16) | 6186 V_FW_WR_FLOWID(cst->etid)); 6187 flowc->mnemval[0].mnemonic = FW_FLOWC_MNEM_PFNVFN; 6188 flowc->mnemval[0].val = htobe32(pfvf); 6189 flowc->mnemval[1].mnemonic = FW_FLOWC_MNEM_CH; 6190 flowc->mnemval[1].val = htobe32(pi->tx_chan); 6191 flowc->mnemval[2].mnemonic = FW_FLOWC_MNEM_PORT; 6192 flowc->mnemval[2].val = htobe32(pi->tx_chan); 6193 flowc->mnemval[3].mnemonic = FW_FLOWC_MNEM_IQID; 6194 flowc->mnemval[3].val = htobe32(cst->iqid); 6195 flowc->mnemval[4].mnemonic = FW_FLOWC_MNEM_EOSTATE; 6196 flowc->mnemval[4].val = htobe32(FW_FLOWC_MNEM_EOSTATE_ESTABLISHED); 6197 flowc->mnemval[5].mnemonic = FW_FLOWC_MNEM_SCHEDCLASS; 6198 flowc->mnemval[5].val = htobe32(cst->schedcl); 6199 6200 commit_wrq_wr(&cst->eo_txq->wrq, flowc, &cookie); 6201 6202 cst->flags &= ~EO_FLOWC_PENDING; 6203 cst->flags |= EO_FLOWC_RPL_PENDING; 6204 MPASS(cst->tx_credits >= ETID_FLOWC_LEN16); /* flowc is first WR. */ 6205 cst->tx_credits -= ETID_FLOWC_LEN16; 6206 6207 return (0); 6208 } 6209 6210 #define ETID_FLUSH_LEN16 (howmany(sizeof (struct fw_flowc_wr), 16)) 6211 6212 void 6213 send_etid_flush_wr(struct cxgbe_rate_tag *cst) 6214 { 6215 struct fw_flowc_wr *flowc; 6216 struct wrq_cookie cookie; 6217 6218 mtx_assert(&cst->lock, MA_OWNED); 6219 6220 flowc = start_wrq_wr(&cst->eo_txq->wrq, ETID_FLUSH_LEN16, &cookie); 6221 if (__predict_false(flowc == NULL)) 6222 CXGBE_UNIMPLEMENTED(__func__); 6223 6224 bzero(flowc, ETID_FLUSH_LEN16 * 16); 6225 flowc->op_to_nparams = htobe32(V_FW_WR_OP(FW_FLOWC_WR) | 6226 V_FW_FLOWC_WR_NPARAMS(0) | F_FW_WR_COMPL); 6227 flowc->flowid_len16 = htobe32(V_FW_WR_LEN16(ETID_FLUSH_LEN16) | 6228 V_FW_WR_FLOWID(cst->etid)); 6229 6230 commit_wrq_wr(&cst->eo_txq->wrq, flowc, &cookie); 6231 6232 cst->flags |= EO_FLUSH_RPL_PENDING; 6233 MPASS(cst->tx_credits >= ETID_FLUSH_LEN16); 6234 cst->tx_credits -= ETID_FLUSH_LEN16; 6235 cst->ncompl++; 6236 } 6237 6238 static void 6239 write_ethofld_wr(struct cxgbe_rate_tag *cst, struct fw_eth_tx_eo_wr *wr, 6240 struct mbuf *m0, int compl) 6241 { 6242 struct cpl_tx_pkt_core *cpl; 6243 uint64_t ctrl1; 6244 uint32_t ctrl; /* used in many unrelated places */ 6245 int len16, pktlen, nsegs, immhdrs; 6246 caddr_t dst; 6247 uintptr_t p; 6248 struct ulptx_sgl *usgl; 6249 struct sglist sg; 6250 struct sglist_seg segs[38]; /* XXX: find real limit. XXX: get off the stack */ 6251 6252 mtx_assert(&cst->lock, MA_OWNED); 6253 M_ASSERTPKTHDR(m0); 6254 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 6255 m0->m_pkthdr.l4hlen > 0, 6256 ("%s: ethofld mbuf %p is missing header lengths", __func__, m0)); 6257 6258 len16 = mbuf_eo_len16(m0); 6259 nsegs = mbuf_eo_nsegs(m0); 6260 pktlen = m0->m_pkthdr.len; 6261 ctrl = sizeof(struct cpl_tx_pkt_core); 6262 if (needs_tso(m0)) 6263 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 6264 immhdrs = m0->m_pkthdr.l2hlen + m0->m_pkthdr.l3hlen + m0->m_pkthdr.l4hlen; 6265 ctrl += immhdrs; 6266 6267 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_EO_WR) | 6268 V_FW_ETH_TX_EO_WR_IMMDLEN(ctrl) | V_FW_WR_COMPL(!!compl)); 6269 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(len16) | 6270 V_FW_WR_FLOWID(cst->etid)); 6271 wr->r3 = 0; 6272 if (needs_outer_udp_csum(m0)) { 6273 wr->u.udpseg.type = FW_ETH_TX_EO_TYPE_UDPSEG; 6274 wr->u.udpseg.ethlen = m0->m_pkthdr.l2hlen; 6275 wr->u.udpseg.iplen = htobe16(m0->m_pkthdr.l3hlen); 6276 wr->u.udpseg.udplen = m0->m_pkthdr.l4hlen; 6277 wr->u.udpseg.rtplen = 0; 6278 wr->u.udpseg.r4 = 0; 6279 wr->u.udpseg.mss = htobe16(pktlen - immhdrs); 6280 wr->u.udpseg.schedpktsize = wr->u.udpseg.mss; 6281 wr->u.udpseg.plen = htobe32(pktlen - immhdrs); 6282 cpl = (void *)(wr + 1); 6283 } else { 6284 MPASS(needs_outer_tcp_csum(m0)); 6285 wr->u.tcpseg.type = FW_ETH_TX_EO_TYPE_TCPSEG; 6286 wr->u.tcpseg.ethlen = m0->m_pkthdr.l2hlen; 6287 wr->u.tcpseg.iplen = htobe16(m0->m_pkthdr.l3hlen); 6288 wr->u.tcpseg.tcplen = m0->m_pkthdr.l4hlen; 6289 wr->u.tcpseg.tsclk_tsoff = mbuf_eo_tsclk_tsoff(m0); 6290 wr->u.tcpseg.r4 = 0; 6291 wr->u.tcpseg.r5 = 0; 6292 wr->u.tcpseg.plen = htobe32(pktlen - immhdrs); 6293 6294 if (needs_tso(m0)) { 6295 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1); 6296 6297 wr->u.tcpseg.mss = htobe16(m0->m_pkthdr.tso_segsz); 6298 6299 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | 6300 F_LSO_FIRST_SLICE | F_LSO_LAST_SLICE | 6301 V_LSO_ETHHDR_LEN((m0->m_pkthdr.l2hlen - 6302 ETHER_HDR_LEN) >> 2) | 6303 V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) | 6304 V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2); 6305 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 6306 ctrl |= F_LSO_IPV6; 6307 lso->lso_ctrl = htobe32(ctrl); 6308 lso->ipid_ofst = htobe16(0); 6309 lso->mss = htobe16(m0->m_pkthdr.tso_segsz); 6310 lso->seqno_offset = htobe32(0); 6311 lso->len = htobe32(pktlen); 6312 6313 cpl = (void *)(lso + 1); 6314 } else { 6315 wr->u.tcpseg.mss = htobe16(0xffff); 6316 cpl = (void *)(wr + 1); 6317 } 6318 } 6319 6320 /* Checksum offload must be requested for ethofld. */ 6321 MPASS(needs_outer_l4_csum(m0)); 6322 ctrl1 = csum_to_ctrl(cst->adapter, m0); 6323 6324 /* VLAN tag insertion */ 6325 if (needs_vlan_insertion(m0)) { 6326 ctrl1 |= F_TXPKT_VLAN_VLD | 6327 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 6328 } 6329 6330 /* CPL header */ 6331 cpl->ctrl0 = cst->ctrl0; 6332 cpl->pack = 0; 6333 cpl->len = htobe16(pktlen); 6334 cpl->ctrl1 = htobe64(ctrl1); 6335 6336 /* Copy Ethernet, IP & TCP/UDP hdrs as immediate data */ 6337 p = (uintptr_t)(cpl + 1); 6338 m_copydata(m0, 0, immhdrs, (void *)p); 6339 6340 /* SGL */ 6341 dst = (void *)(cpl + 1); 6342 if (nsegs > 0) { 6343 int i, pad; 6344 6345 /* zero-pad upto next 16Byte boundary, if not 16Byte aligned */ 6346 p += immhdrs; 6347 pad = 16 - (immhdrs & 0xf); 6348 bzero((void *)p, pad); 6349 6350 usgl = (void *)(p + pad); 6351 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 6352 V_ULPTX_NSGE(nsegs)); 6353 6354 sglist_init(&sg, nitems(segs), segs); 6355 for (; m0 != NULL; m0 = m0->m_next) { 6356 if (__predict_false(m0->m_len == 0)) 6357 continue; 6358 if (immhdrs >= m0->m_len) { 6359 immhdrs -= m0->m_len; 6360 continue; 6361 } 6362 if (m0->m_flags & M_EXTPG) 6363 sglist_append_mbuf_epg(&sg, m0, 6364 mtod(m0, vm_offset_t), m0->m_len); 6365 else 6366 sglist_append(&sg, mtod(m0, char *) + immhdrs, 6367 m0->m_len - immhdrs); 6368 immhdrs = 0; 6369 } 6370 MPASS(sg.sg_nseg == nsegs); 6371 6372 /* 6373 * Zero pad last 8B in case the WR doesn't end on a 16B 6374 * boundary. 6375 */ 6376 *(uint64_t *)((char *)wr + len16 * 16 - 8) = 0; 6377 6378 usgl->len0 = htobe32(segs[0].ss_len); 6379 usgl->addr0 = htobe64(segs[0].ss_paddr); 6380 for (i = 0; i < nsegs - 1; i++) { 6381 usgl->sge[i / 2].len[i & 1] = htobe32(segs[i + 1].ss_len); 6382 usgl->sge[i / 2].addr[i & 1] = htobe64(segs[i + 1].ss_paddr); 6383 } 6384 if (i & 1) 6385 usgl->sge[i / 2].len[1] = htobe32(0); 6386 } 6387 6388 } 6389 6390 static void 6391 ethofld_tx(struct cxgbe_rate_tag *cst) 6392 { 6393 struct mbuf *m; 6394 struct wrq_cookie cookie; 6395 int next_credits, compl; 6396 struct fw_eth_tx_eo_wr *wr; 6397 6398 mtx_assert(&cst->lock, MA_OWNED); 6399 6400 while ((m = mbufq_first(&cst->pending_tx)) != NULL) { 6401 M_ASSERTPKTHDR(m); 6402 6403 /* How many len16 credits do we need to send this mbuf. */ 6404 next_credits = mbuf_eo_len16(m); 6405 MPASS(next_credits > 0); 6406 if (next_credits > cst->tx_credits) { 6407 /* 6408 * Tx will make progress eventually because there is at 6409 * least one outstanding fw4_ack that will return 6410 * credits and kick the tx. 6411 */ 6412 MPASS(cst->ncompl > 0); 6413 return; 6414 } 6415 wr = start_wrq_wr(&cst->eo_txq->wrq, next_credits, &cookie); 6416 if (__predict_false(wr == NULL)) { 6417 /* XXX: wishful thinking, not a real assertion. */ 6418 MPASS(cst->ncompl > 0); 6419 return; 6420 } 6421 cst->tx_credits -= next_credits; 6422 cst->tx_nocompl += next_credits; 6423 compl = cst->ncompl == 0 || cst->tx_nocompl >= cst->tx_total / 2; 6424 ETHER_BPF_MTAP(cst->com.ifp, m); 6425 write_ethofld_wr(cst, wr, m, compl); 6426 commit_wrq_wr(&cst->eo_txq->wrq, wr, &cookie); 6427 if (compl) { 6428 cst->ncompl++; 6429 cst->tx_nocompl = 0; 6430 } 6431 (void) mbufq_dequeue(&cst->pending_tx); 6432 6433 /* 6434 * Drop the mbuf's reference on the tag now rather 6435 * than waiting until m_freem(). This ensures that 6436 * cxgbe_rate_tag_free gets called when the inp drops 6437 * its reference on the tag and there are no more 6438 * mbufs in the pending_tx queue and can flush any 6439 * pending requests. Otherwise if the last mbuf 6440 * doesn't request a completion the etid will never be 6441 * released. 6442 */ 6443 m->m_pkthdr.snd_tag = NULL; 6444 m->m_pkthdr.csum_flags &= ~CSUM_SND_TAG; 6445 m_snd_tag_rele(&cst->com); 6446 6447 mbufq_enqueue(&cst->pending_fwack, m); 6448 } 6449 } 6450 6451 int 6452 ethofld_transmit(struct ifnet *ifp, struct mbuf *m0) 6453 { 6454 struct cxgbe_rate_tag *cst; 6455 int rc; 6456 6457 MPASS(m0->m_nextpkt == NULL); 6458 MPASS(m0->m_pkthdr.csum_flags & CSUM_SND_TAG); 6459 MPASS(m0->m_pkthdr.snd_tag != NULL); 6460 cst = mst_to_crt(m0->m_pkthdr.snd_tag); 6461 6462 mtx_lock(&cst->lock); 6463 MPASS(cst->flags & EO_SND_TAG_REF); 6464 6465 if (__predict_false(cst->flags & EO_FLOWC_PENDING)) { 6466 struct vi_info *vi = ifp->if_softc; 6467 struct port_info *pi = vi->pi; 6468 struct adapter *sc = pi->adapter; 6469 const uint32_t rss_mask = vi->rss_size - 1; 6470 uint32_t rss_hash; 6471 6472 cst->eo_txq = &sc->sge.ofld_txq[vi->first_ofld_txq]; 6473 if (M_HASHTYPE_ISHASH(m0)) 6474 rss_hash = m0->m_pkthdr.flowid; 6475 else 6476 rss_hash = arc4random(); 6477 /* We assume RSS hashing */ 6478 cst->iqid = vi->rss[rss_hash & rss_mask]; 6479 cst->eo_txq += rss_hash % vi->nofldtxq; 6480 rc = send_etid_flowc_wr(cst, pi, vi); 6481 if (rc != 0) 6482 goto done; 6483 } 6484 6485 if (__predict_false(cst->plen + m0->m_pkthdr.len > eo_max_backlog)) { 6486 rc = ENOBUFS; 6487 goto done; 6488 } 6489 6490 mbufq_enqueue(&cst->pending_tx, m0); 6491 cst->plen += m0->m_pkthdr.len; 6492 6493 /* 6494 * Hold an extra reference on the tag while generating work 6495 * requests to ensure that we don't try to free the tag during 6496 * ethofld_tx() in case we are sending the final mbuf after 6497 * the inp was freed. 6498 */ 6499 m_snd_tag_ref(&cst->com); 6500 ethofld_tx(cst); 6501 mtx_unlock(&cst->lock); 6502 m_snd_tag_rele(&cst->com); 6503 return (0); 6504 6505 done: 6506 mtx_unlock(&cst->lock); 6507 if (__predict_false(rc != 0)) 6508 m_freem(m0); 6509 return (rc); 6510 } 6511 6512 static int 6513 ethofld_fw4_ack(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0) 6514 { 6515 struct adapter *sc = iq->adapter; 6516 const struct cpl_fw4_ack *cpl = (const void *)(rss + 1); 6517 struct mbuf *m; 6518 u_int etid = G_CPL_FW4_ACK_FLOWID(be32toh(OPCODE_TID(cpl))); 6519 struct cxgbe_rate_tag *cst; 6520 uint8_t credits = cpl->credits; 6521 6522 cst = lookup_etid(sc, etid); 6523 mtx_lock(&cst->lock); 6524 if (__predict_false(cst->flags & EO_FLOWC_RPL_PENDING)) { 6525 MPASS(credits >= ETID_FLOWC_LEN16); 6526 credits -= ETID_FLOWC_LEN16; 6527 cst->flags &= ~EO_FLOWC_RPL_PENDING; 6528 } 6529 6530 KASSERT(cst->ncompl > 0, 6531 ("%s: etid %u (%p) wasn't expecting completion.", 6532 __func__, etid, cst)); 6533 cst->ncompl--; 6534 6535 while (credits > 0) { 6536 m = mbufq_dequeue(&cst->pending_fwack); 6537 if (__predict_false(m == NULL)) { 6538 /* 6539 * The remaining credits are for the final flush that 6540 * was issued when the tag was freed by the kernel. 6541 */ 6542 MPASS((cst->flags & 6543 (EO_FLUSH_RPL_PENDING | EO_SND_TAG_REF)) == 6544 EO_FLUSH_RPL_PENDING); 6545 MPASS(credits == ETID_FLUSH_LEN16); 6546 MPASS(cst->tx_credits + cpl->credits == cst->tx_total); 6547 MPASS(cst->ncompl == 0); 6548 6549 cst->flags &= ~EO_FLUSH_RPL_PENDING; 6550 cst->tx_credits += cpl->credits; 6551 cxgbe_rate_tag_free_locked(cst); 6552 return (0); /* cst is gone. */ 6553 } 6554 KASSERT(m != NULL, 6555 ("%s: too many credits (%u, %u)", __func__, cpl->credits, 6556 credits)); 6557 KASSERT(credits >= mbuf_eo_len16(m), 6558 ("%s: too few credits (%u, %u, %u)", __func__, 6559 cpl->credits, credits, mbuf_eo_len16(m))); 6560 credits -= mbuf_eo_len16(m); 6561 cst->plen -= m->m_pkthdr.len; 6562 m_freem(m); 6563 } 6564 6565 cst->tx_credits += cpl->credits; 6566 MPASS(cst->tx_credits <= cst->tx_total); 6567 6568 if (cst->flags & EO_SND_TAG_REF) { 6569 /* 6570 * As with ethofld_transmit(), hold an extra reference 6571 * so that the tag is stable across ethold_tx(). 6572 */ 6573 m_snd_tag_ref(&cst->com); 6574 m = mbufq_first(&cst->pending_tx); 6575 if (m != NULL && cst->tx_credits >= mbuf_eo_len16(m)) 6576 ethofld_tx(cst); 6577 mtx_unlock(&cst->lock); 6578 m_snd_tag_rele(&cst->com); 6579 } else { 6580 /* 6581 * There shouldn't be any pending packets if the tag 6582 * was freed by the kernel since any pending packet 6583 * should hold a reference to the tag. 6584 */ 6585 MPASS(mbufq_first(&cst->pending_tx) == NULL); 6586 mtx_unlock(&cst->lock); 6587 } 6588 6589 return (0); 6590 } 6591 #endif 6592