1 /*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 34 #include <sys/types.h> 35 #include <sys/eventhandler.h> 36 #include <sys/mbuf.h> 37 #include <sys/socket.h> 38 #include <sys/kernel.h> 39 #include <sys/kdb.h> 40 #include <sys/malloc.h> 41 #include <sys/queue.h> 42 #include <sys/taskqueue.h> 43 #include <sys/time.h> 44 #include <sys/sysctl.h> 45 #include <sys/smp.h> 46 #include <net/bpf.h> 47 #include <net/ethernet.h> 48 #include <net/if.h> 49 #include <net/if_vlan_var.h> 50 #include <netinet/in.h> 51 #include <netinet/ip.h> 52 #include <netinet/ip6.h> 53 #include <netinet/tcp.h> 54 #include <machine/md_var.h> 55 56 #include "common/common.h" 57 #include "common/t4_regs.h" 58 #include "common/t4_regs_values.h" 59 #include "common/t4_msg.h" 60 61 #ifdef T4_PKT_TIMESTAMP 62 #define RX_COPY_THRESHOLD (MINCLSIZE - 8) 63 #else 64 #define RX_COPY_THRESHOLD MINCLSIZE 65 #endif 66 67 /* 68 * Ethernet frames are DMA'd at this byte offset into the freelist buffer. 69 * 0-7 are valid values. 70 */ 71 static int fl_pktshift = 2; 72 TUNABLE_INT("hw.cxgbe.fl_pktshift", &fl_pktshift); 73 74 /* 75 * Pad ethernet payload up to this boundary. 76 * -1: driver should figure out a good value. 77 * 0: disable padding. 78 * Any power of 2 from 32 to 4096 (both inclusive) is also a valid value. 79 */ 80 static int fl_pad = -1; 81 TUNABLE_INT("hw.cxgbe.fl_pad", &fl_pad); 82 83 /* 84 * Status page length. 85 * -1: driver should figure out a good value. 86 * 64 or 128 are the only other valid values. 87 */ 88 static int spg_len = -1; 89 TUNABLE_INT("hw.cxgbe.spg_len", &spg_len); 90 91 /* 92 * Congestion drops. 93 * -1: no congestion feedback (not recommended). 94 * 0: backpressure the channel instead of dropping packets right away. 95 * 1: no backpressure, drop packets for the congested queue immediately. 96 */ 97 static int cong_drop = 0; 98 TUNABLE_INT("hw.cxgbe.cong_drop", &cong_drop); 99 100 /* 101 * Deliver multiple frames in the same free list buffer if they fit. 102 * -1: let the driver decide whether to enable buffer packing or not. 103 * 0: disable buffer packing. 104 * 1: enable buffer packing. 105 */ 106 static int buffer_packing = -1; 107 TUNABLE_INT("hw.cxgbe.buffer_packing", &buffer_packing); 108 109 /* 110 * Start next frame in a packed buffer at this boundary. 111 * -1: driver should figure out a good value. 112 * T4: 113 * --- 114 * if fl_pad != 0 115 * value specified here will be overridden by fl_pad. 116 * else 117 * power of 2 from 32 to 4096 (both inclusive) is a valid value here. 118 * T5: 119 * --- 120 * 16, or a power of 2 from 64 to 4096 (both inclusive) is a valid value. 121 */ 122 static int fl_pack = -1; 123 static int t4_fl_pack; 124 static int t5_fl_pack; 125 TUNABLE_INT("hw.cxgbe.fl_pack", &fl_pack); 126 127 /* Used to track coalesced tx work request */ 128 struct txpkts { 129 uint64_t *flitp; /* ptr to flit where next pkt should start */ 130 uint8_t npkt; /* # of packets in this work request */ 131 uint8_t nflits; /* # of flits used by this work request */ 132 uint16_t plen; /* total payload (sum of all packets) */ 133 }; 134 135 /* A packet's SGL. This + m_pkthdr has all info needed for tx */ 136 struct sgl { 137 int nsegs; /* # of segments in the SGL, 0 means imm. tx */ 138 int nflits; /* # of flits needed for the SGL */ 139 bus_dma_segment_t seg[TX_SGL_SEGS]; 140 }; 141 142 static int service_iq(struct sge_iq *, int); 143 static struct mbuf *get_fl_payload1(struct adapter *, struct sge_fl *, uint32_t, 144 int *); 145 static struct mbuf *get_fl_payload2(struct adapter *, struct sge_fl *, uint32_t, 146 int *); 147 static int t4_eth_rx(struct sge_iq *, const struct rss_header *, struct mbuf *); 148 static inline void init_iq(struct sge_iq *, struct adapter *, int, int, int, 149 int); 150 static inline void init_fl(struct adapter *, struct sge_fl *, int, int, int, 151 char *); 152 static inline void init_eq(struct sge_eq *, int, int, uint8_t, uint16_t, 153 char *); 154 static int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *, 155 bus_addr_t *, void **); 156 static int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 157 void *); 158 static int alloc_iq_fl(struct port_info *, struct sge_iq *, struct sge_fl *, 159 int, int); 160 static int free_iq_fl(struct port_info *, struct sge_iq *, struct sge_fl *); 161 static int alloc_fwq(struct adapter *); 162 static int free_fwq(struct adapter *); 163 static int alloc_mgmtq(struct adapter *); 164 static int free_mgmtq(struct adapter *); 165 static int alloc_rxq(struct port_info *, struct sge_rxq *, int, int, 166 struct sysctl_oid *); 167 static int free_rxq(struct port_info *, struct sge_rxq *); 168 #ifdef TCP_OFFLOAD 169 static int alloc_ofld_rxq(struct port_info *, struct sge_ofld_rxq *, int, int, 170 struct sysctl_oid *); 171 static int free_ofld_rxq(struct port_info *, struct sge_ofld_rxq *); 172 #endif 173 static int ctrl_eq_alloc(struct adapter *, struct sge_eq *); 174 static int eth_eq_alloc(struct adapter *, struct port_info *, struct sge_eq *); 175 #ifdef TCP_OFFLOAD 176 static int ofld_eq_alloc(struct adapter *, struct port_info *, struct sge_eq *); 177 #endif 178 static int alloc_eq(struct adapter *, struct port_info *, struct sge_eq *); 179 static int free_eq(struct adapter *, struct sge_eq *); 180 static int alloc_wrq(struct adapter *, struct port_info *, struct sge_wrq *, 181 struct sysctl_oid *); 182 static int free_wrq(struct adapter *, struct sge_wrq *); 183 static int alloc_txq(struct port_info *, struct sge_txq *, int, 184 struct sysctl_oid *); 185 static int free_txq(struct port_info *, struct sge_txq *); 186 static void oneseg_dma_callback(void *, bus_dma_segment_t *, int, int); 187 static inline bool is_new_response(const struct sge_iq *, struct rsp_ctrl **); 188 static inline void iq_next(struct sge_iq *); 189 static inline void ring_fl_db(struct adapter *, struct sge_fl *); 190 static int refill_fl(struct adapter *, struct sge_fl *, int); 191 static void refill_sfl(void *); 192 static int alloc_fl_sdesc(struct sge_fl *); 193 static void free_fl_sdesc(struct adapter *, struct sge_fl *); 194 static void set_fl_tag_idx(struct adapter *, struct sge_fl *, int); 195 static void add_fl_to_sfl(struct adapter *, struct sge_fl *); 196 197 static int get_pkt_sgl(struct sge_txq *, struct mbuf **, struct sgl *, int); 198 static int free_pkt_sgl(struct sge_txq *, struct sgl *); 199 static int write_txpkt_wr(struct port_info *, struct sge_txq *, struct mbuf *, 200 struct sgl *); 201 static int add_to_txpkts(struct port_info *, struct sge_txq *, struct txpkts *, 202 struct mbuf *, struct sgl *); 203 static void write_txpkts_wr(struct sge_txq *, struct txpkts *); 204 static inline void write_ulp_cpl_sgl(struct port_info *, struct sge_txq *, 205 struct txpkts *, struct mbuf *, struct sgl *); 206 static int write_sgl_to_txd(struct sge_eq *, struct sgl *, caddr_t *); 207 static inline void copy_to_txd(struct sge_eq *, caddr_t, caddr_t *, int); 208 static inline void ring_eq_db(struct adapter *, struct sge_eq *); 209 static inline int reclaimable(struct sge_eq *); 210 static int reclaim_tx_descs(struct sge_txq *, int, int); 211 static void write_eqflush_wr(struct sge_eq *); 212 static __be64 get_flit(bus_dma_segment_t *, int, int); 213 static int handle_sge_egr_update(struct sge_iq *, const struct rss_header *, 214 struct mbuf *); 215 static int handle_fw_msg(struct sge_iq *, const struct rss_header *, 216 struct mbuf *); 217 218 static int sysctl_uint16(SYSCTL_HANDLER_ARGS); 219 220 /* 221 * Called on MOD_LOAD. Validates and calculates the SGE tunables. 222 */ 223 void 224 t4_sge_modload(void) 225 { 226 int pad; 227 228 /* set pad to a reasonable powerof2 between 16 and 4096 (inclusive) */ 229 #if defined(__i386__) || defined(__amd64__) 230 pad = max(cpu_clflush_line_size, 16); 231 #else 232 pad = max(CACHE_LINE_SIZE, 16); 233 #endif 234 pad = min(pad, 4096); 235 236 if (fl_pktshift < 0 || fl_pktshift > 7) { 237 printf("Invalid hw.cxgbe.fl_pktshift value (%d)," 238 " using 2 instead.\n", fl_pktshift); 239 fl_pktshift = 2; 240 } 241 242 if (fl_pad != 0 && 243 (fl_pad < 32 || fl_pad > 4096 || !powerof2(fl_pad))) { 244 245 if (fl_pad != -1) { 246 printf("Invalid hw.cxgbe.fl_pad value (%d)," 247 " using %d instead.\n", fl_pad, max(pad, 32)); 248 } 249 fl_pad = max(pad, 32); 250 } 251 252 /* 253 * T4 has the same pad and pack boundary. If a pad boundary is set, 254 * pack boundary must be set to the same value. Otherwise take the 255 * specified value or auto-calculate something reasonable. 256 */ 257 if (fl_pad) 258 t4_fl_pack = fl_pad; 259 else if (fl_pack < 32 || fl_pack > 4096 || !powerof2(fl_pack)) 260 t4_fl_pack = max(pad, 32); 261 else 262 t4_fl_pack = fl_pack; 263 264 /* T5's pack boundary is independent of the pad boundary. */ 265 if (fl_pack < 16 || fl_pack == 32 || fl_pack > 4096 || 266 !powerof2(fl_pack)) 267 t5_fl_pack = max(pad, 64); 268 else 269 t5_fl_pack = fl_pack; 270 271 if (spg_len != 64 && spg_len != 128) { 272 int len; 273 274 #if defined(__i386__) || defined(__amd64__) 275 len = cpu_clflush_line_size > 64 ? 128 : 64; 276 #else 277 len = 64; 278 #endif 279 if (spg_len != -1) { 280 printf("Invalid hw.cxgbe.spg_len value (%d)," 281 " using %d instead.\n", spg_len, len); 282 } 283 spg_len = len; 284 } 285 286 if (cong_drop < -1 || cong_drop > 1) { 287 printf("Invalid hw.cxgbe.cong_drop value (%d)," 288 " using 0 instead.\n", cong_drop); 289 cong_drop = 0; 290 } 291 } 292 293 void 294 t4_init_sge_cpl_handlers(struct adapter *sc) 295 { 296 297 t4_register_cpl_handler(sc, CPL_FW4_MSG, handle_fw_msg); 298 t4_register_cpl_handler(sc, CPL_FW6_MSG, handle_fw_msg); 299 t4_register_cpl_handler(sc, CPL_SGE_EGR_UPDATE, handle_sge_egr_update); 300 t4_register_cpl_handler(sc, CPL_RX_PKT, t4_eth_rx); 301 t4_register_fw_msg_handler(sc, FW6_TYPE_CMD_RPL, t4_handle_fw_rpl); 302 } 303 304 /* 305 * adap->params.vpd.cclk must be set up before this is called. 306 */ 307 void 308 t4_tweak_chip_settings(struct adapter *sc) 309 { 310 int i; 311 uint32_t v, m; 312 int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200}; 313 int timer_max = M_TIMERVALUE0 * 1000 / sc->params.vpd.cclk; 314 int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */ 315 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 316 int sw_flbuf_sizes[] = { 317 MCLBYTES, 318 #if MJUMPAGESIZE != MCLBYTES 319 MJUMPAGESIZE, 320 #endif 321 MJUM9BYTES, 322 MJUM16BYTES, 323 MJUMPAGESIZE - MSIZE 324 }; 325 326 KASSERT(sc->flags & MASTER_PF, 327 ("%s: trying to change chip settings when not master.", __func__)); 328 329 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE; 330 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE | 331 V_EGRSTATUSPAGESIZE(spg_len == 128); 332 if (is_t4(sc) && (fl_pad || buffer_packing)) { 333 /* t4_fl_pack has the correct value even when fl_pad = 0 */ 334 m |= V_INGPADBOUNDARY(M_INGPADBOUNDARY); 335 v |= V_INGPADBOUNDARY(ilog2(t4_fl_pack) - 5); 336 } else if (is_t5(sc) && fl_pad) { 337 m |= V_INGPADBOUNDARY(M_INGPADBOUNDARY); 338 v |= V_INGPADBOUNDARY(ilog2(fl_pad) - 5); 339 } 340 t4_set_reg_field(sc, A_SGE_CONTROL, m, v); 341 342 if (is_t5(sc) && buffer_packing) { 343 m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY); 344 if (t5_fl_pack == 16) 345 v = V_INGPACKBOUNDARY(0); 346 else 347 v = V_INGPACKBOUNDARY(ilog2(t5_fl_pack) - 5); 348 t4_set_reg_field(sc, A_SGE_CONTROL2, m, v); 349 } 350 351 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) | 352 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) | 353 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) | 354 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) | 355 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) | 356 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) | 357 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) | 358 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10); 359 t4_write_reg(sc, A_SGE_HOST_PAGE_SIZE, v); 360 361 for (i = 0; i < min(nitems(sw_flbuf_sizes), 16); i++) { 362 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0 + (4 * i), 363 sw_flbuf_sizes[i]); 364 } 365 366 v = V_THRESHOLD_0(intr_pktcount[0]) | V_THRESHOLD_1(intr_pktcount[1]) | 367 V_THRESHOLD_2(intr_pktcount[2]) | V_THRESHOLD_3(intr_pktcount[3]); 368 t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD, v); 369 370 KASSERT(intr_timer[0] <= timer_max, 371 ("%s: not a single usable timer (%d, %d)", __func__, intr_timer[0], 372 timer_max)); 373 for (i = 1; i < nitems(intr_timer); i++) { 374 KASSERT(intr_timer[i] >= intr_timer[i - 1], 375 ("%s: timers not listed in increasing order (%d)", 376 __func__, i)); 377 378 while (intr_timer[i] > timer_max) { 379 if (i == nitems(intr_timer) - 1) { 380 intr_timer[i] = timer_max; 381 break; 382 } 383 intr_timer[i] += intr_timer[i - 1]; 384 intr_timer[i] /= 2; 385 } 386 } 387 388 v = V_TIMERVALUE0(us_to_core_ticks(sc, intr_timer[0])) | 389 V_TIMERVALUE1(us_to_core_ticks(sc, intr_timer[1])); 390 t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1, v); 391 v = V_TIMERVALUE2(us_to_core_ticks(sc, intr_timer[2])) | 392 V_TIMERVALUE3(us_to_core_ticks(sc, intr_timer[3])); 393 t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3, v); 394 v = V_TIMERVALUE4(us_to_core_ticks(sc, intr_timer[4])) | 395 V_TIMERVALUE5(us_to_core_ticks(sc, intr_timer[5])); 396 t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5, v); 397 398 if (cong_drop == 0) { 399 m = F_TUNNELCNGDROP0 | F_TUNNELCNGDROP1 | F_TUNNELCNGDROP2 | 400 F_TUNNELCNGDROP3; 401 t4_set_reg_field(sc, A_TP_PARA_REG3, m, 0); 402 } 403 404 /* 4K, 16K, 64K, 256K DDP "page sizes" */ 405 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 406 t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, v); 407 408 m = v = F_TDDPTAGTCB; 409 t4_set_reg_field(sc, A_ULP_RX_CTL, m, v); 410 411 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 412 F_RESETDDPOFFSET; 413 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 414 t4_set_reg_field(sc, A_TP_PARA_REG5, m, v); 415 } 416 417 /* 418 * XXX: driver really should be able to deal with unexpected settings. 419 */ 420 int 421 t4_read_chip_settings(struct adapter *sc) 422 { 423 struct sge *s = &sc->sge; 424 int i, j, n, rc = 0; 425 uint32_t m, v, r; 426 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 427 uint32_t sge_flbuf_sizes[16], sw_flbuf_sizes[] = { 428 MCLBYTES, 429 #if MJUMPAGESIZE != MCLBYTES 430 MJUMPAGESIZE, 431 #endif 432 MJUM9BYTES, 433 MJUM16BYTES 434 }; 435 436 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE; 437 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE | 438 V_EGRSTATUSPAGESIZE(spg_len == 128); 439 if (is_t4(sc) && (fl_pad || buffer_packing)) { 440 m |= V_INGPADBOUNDARY(M_INGPADBOUNDARY); 441 v |= V_INGPADBOUNDARY(ilog2(t4_fl_pack) - 5); 442 } else if (is_t5(sc) && fl_pad) { 443 m |= V_INGPADBOUNDARY(M_INGPADBOUNDARY); 444 v |= V_INGPADBOUNDARY(ilog2(fl_pad) - 5); 445 } 446 r = t4_read_reg(sc, A_SGE_CONTROL); 447 if ((r & m) != v) { 448 device_printf(sc->dev, "invalid SGE_CONTROL(0x%x)\n", r); 449 rc = EINVAL; 450 } 451 452 if (is_t5(sc) && buffer_packing) { 453 m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY); 454 if (t5_fl_pack == 16) 455 v = V_INGPACKBOUNDARY(0); 456 else 457 v = V_INGPACKBOUNDARY(ilog2(t5_fl_pack) - 5); 458 r = t4_read_reg(sc, A_SGE_CONTROL2); 459 if ((r & m) != v) { 460 device_printf(sc->dev, 461 "invalid SGE_CONTROL2(0x%x)\n", r); 462 rc = EINVAL; 463 } 464 } 465 466 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) | 467 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) | 468 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) | 469 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) | 470 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) | 471 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) | 472 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) | 473 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10); 474 r = t4_read_reg(sc, A_SGE_HOST_PAGE_SIZE); 475 if (r != v) { 476 device_printf(sc->dev, "invalid SGE_HOST_PAGE_SIZE(0x%x)\n", r); 477 rc = EINVAL; 478 } 479 480 /* 481 * Make a list of SGE FL buffer sizes programmed in the chip and tally 482 * it with the FL buffer sizes that we'd like to use. 483 */ 484 n = 0; 485 for (i = 0; i < nitems(sge_flbuf_sizes); i++) { 486 r = t4_read_reg(sc, A_SGE_FL_BUFFER_SIZE0 + (4 * i)); 487 sge_flbuf_sizes[i] = r; 488 if (r == MJUMPAGESIZE - MSIZE && 489 (sc->flags & BUF_PACKING_OK) == 0) { 490 sc->flags |= BUF_PACKING_OK; 491 FL_BUF_HWTAG(sc, n) = i; 492 FL_BUF_SIZE(sc, n) = MJUMPAGESIZE - MSIZE; 493 FL_BUF_TYPE(sc, n) = m_gettype(MJUMPAGESIZE); 494 FL_BUF_ZONE(sc, n) = m_getzone(MJUMPAGESIZE); 495 n++; 496 } 497 } 498 for (i = 0; i < nitems(sw_flbuf_sizes); i++) { 499 for (j = 0; j < nitems(sge_flbuf_sizes); j++) { 500 if (sw_flbuf_sizes[i] != sge_flbuf_sizes[j]) 501 continue; 502 FL_BUF_HWTAG(sc, n) = j; 503 FL_BUF_SIZE(sc, n) = sw_flbuf_sizes[i]; 504 FL_BUF_TYPE(sc, n) = m_gettype(sw_flbuf_sizes[i]); 505 FL_BUF_ZONE(sc, n) = m_getzone(sw_flbuf_sizes[i]); 506 n++; 507 break; 508 } 509 } 510 if (n == 0) { 511 device_printf(sc->dev, "no usable SGE FL buffer size.\n"); 512 rc = EINVAL; 513 } else if (n == 1 && (sc->flags & BUF_PACKING_OK)) { 514 device_printf(sc->dev, 515 "no usable SGE FL buffer size when not packing buffers.\n"); 516 rc = EINVAL; 517 } 518 FL_BUF_SIZES(sc) = n; 519 520 r = t4_read_reg(sc, A_SGE_INGRESS_RX_THRESHOLD); 521 s->counter_val[0] = G_THRESHOLD_0(r); 522 s->counter_val[1] = G_THRESHOLD_1(r); 523 s->counter_val[2] = G_THRESHOLD_2(r); 524 s->counter_val[3] = G_THRESHOLD_3(r); 525 526 r = t4_read_reg(sc, A_SGE_TIMER_VALUE_0_AND_1); 527 s->timer_val[0] = G_TIMERVALUE0(r) / core_ticks_per_usec(sc); 528 s->timer_val[1] = G_TIMERVALUE1(r) / core_ticks_per_usec(sc); 529 r = t4_read_reg(sc, A_SGE_TIMER_VALUE_2_AND_3); 530 s->timer_val[2] = G_TIMERVALUE2(r) / core_ticks_per_usec(sc); 531 s->timer_val[3] = G_TIMERVALUE3(r) / core_ticks_per_usec(sc); 532 r = t4_read_reg(sc, A_SGE_TIMER_VALUE_4_AND_5); 533 s->timer_val[4] = G_TIMERVALUE4(r) / core_ticks_per_usec(sc); 534 s->timer_val[5] = G_TIMERVALUE5(r) / core_ticks_per_usec(sc); 535 536 if (cong_drop == 0) { 537 m = F_TUNNELCNGDROP0 | F_TUNNELCNGDROP1 | F_TUNNELCNGDROP2 | 538 F_TUNNELCNGDROP3; 539 r = t4_read_reg(sc, A_TP_PARA_REG3); 540 if (r & m) { 541 device_printf(sc->dev, 542 "invalid TP_PARA_REG3(0x%x)\n", r); 543 rc = EINVAL; 544 } 545 } 546 547 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 548 r = t4_read_reg(sc, A_ULP_RX_TDDP_PSZ); 549 if (r != v) { 550 device_printf(sc->dev, "invalid ULP_RX_TDDP_PSZ(0x%x)\n", r); 551 rc = EINVAL; 552 } 553 554 m = v = F_TDDPTAGTCB; 555 r = t4_read_reg(sc, A_ULP_RX_CTL); 556 if ((r & m) != v) { 557 device_printf(sc->dev, "invalid ULP_RX_CTL(0x%x)\n", r); 558 rc = EINVAL; 559 } 560 561 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 562 F_RESETDDPOFFSET; 563 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 564 r = t4_read_reg(sc, A_TP_PARA_REG5); 565 if ((r & m) != v) { 566 device_printf(sc->dev, "invalid TP_PARA_REG5(0x%x)\n", r); 567 rc = EINVAL; 568 } 569 570 r = t4_read_reg(sc, A_SGE_CONM_CTRL); 571 s->fl_starve_threshold = G_EGRTHRESHOLD(r) * 2 + 1; 572 573 /* egress queues: log2 of # of doorbells per BAR2 page */ 574 r = t4_read_reg(sc, A_SGE_EGRESS_QUEUES_PER_PAGE_PF); 575 r >>= S_QUEUESPERPAGEPF0 + 576 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * sc->pf; 577 s->eq_s_qpp = r & M_QUEUESPERPAGEPF0; 578 579 /* ingress queues: log2 of # of doorbells per BAR2 page */ 580 r = t4_read_reg(sc, A_SGE_INGRESS_QUEUES_PER_PAGE_PF); 581 r >>= S_QUEUESPERPAGEPF0 + 582 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * sc->pf; 583 s->iq_s_qpp = r & M_QUEUESPERPAGEPF0; 584 585 t4_init_tp_params(sc); 586 587 t4_read_mtu_tbl(sc, sc->params.mtus, NULL); 588 t4_load_mtus(sc, sc->params.mtus, sc->params.a_wnd, sc->params.b_wnd); 589 590 return (rc); 591 } 592 593 int 594 t4_create_dma_tag(struct adapter *sc) 595 { 596 int rc; 597 598 rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0, 599 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE, 600 BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL, 601 NULL, &sc->dmat); 602 if (rc != 0) { 603 device_printf(sc->dev, 604 "failed to create main DMA tag: %d\n", rc); 605 } 606 607 return (rc); 608 } 609 610 static inline int 611 enable_buffer_packing(struct adapter *sc) 612 { 613 614 if (sc->flags & BUF_PACKING_OK && 615 ((is_t5(sc) && buffer_packing) || /* 1 or -1 both ok for T5 */ 616 (is_t4(sc) && buffer_packing == 1))) 617 return (1); 618 return (0); 619 } 620 621 void 622 t4_sge_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx, 623 struct sysctl_oid_list *children) 624 { 625 626 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pktshift", CTLFLAG_RD, 627 NULL, fl_pktshift, "payload DMA offset in rx buffer (bytes)"); 628 629 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pad", CTLFLAG_RD, 630 NULL, fl_pad, "payload pad boundary (bytes)"); 631 632 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "spg_len", CTLFLAG_RD, 633 NULL, spg_len, "status page size (bytes)"); 634 635 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_drop", CTLFLAG_RD, 636 NULL, cong_drop, "congestion drop setting"); 637 638 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "buffer_packing", CTLFLAG_RD, 639 NULL, enable_buffer_packing(sc), 640 "pack multiple frames in one fl buffer"); 641 642 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pack", CTLFLAG_RD, 643 NULL, is_t5(sc) ? t5_fl_pack : t4_fl_pack, 644 "payload pack boundary (bytes)"); 645 } 646 647 int 648 t4_destroy_dma_tag(struct adapter *sc) 649 { 650 if (sc->dmat) 651 bus_dma_tag_destroy(sc->dmat); 652 653 return (0); 654 } 655 656 /* 657 * Allocate and initialize the firmware event queue and the management queue. 658 * 659 * Returns errno on failure. Resources allocated up to that point may still be 660 * allocated. Caller is responsible for cleanup in case this function fails. 661 */ 662 int 663 t4_setup_adapter_queues(struct adapter *sc) 664 { 665 int rc; 666 667 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 668 669 sysctl_ctx_init(&sc->ctx); 670 sc->flags |= ADAP_SYSCTL_CTX; 671 672 /* 673 * Firmware event queue 674 */ 675 rc = alloc_fwq(sc); 676 if (rc != 0) 677 return (rc); 678 679 /* 680 * Management queue. This is just a control queue that uses the fwq as 681 * its associated iq. 682 */ 683 rc = alloc_mgmtq(sc); 684 685 return (rc); 686 } 687 688 /* 689 * Idempotent 690 */ 691 int 692 t4_teardown_adapter_queues(struct adapter *sc) 693 { 694 695 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 696 697 /* Do this before freeing the queue */ 698 if (sc->flags & ADAP_SYSCTL_CTX) { 699 sysctl_ctx_free(&sc->ctx); 700 sc->flags &= ~ADAP_SYSCTL_CTX; 701 } 702 703 free_mgmtq(sc); 704 free_fwq(sc); 705 706 return (0); 707 } 708 709 static inline int 710 first_vector(struct port_info *pi) 711 { 712 struct adapter *sc = pi->adapter; 713 int rc = T4_EXTRA_INTR, i; 714 715 if (sc->intr_count == 1) 716 return (0); 717 718 for_each_port(sc, i) { 719 struct port_info *p = sc->port[i]; 720 721 if (i == pi->port_id) 722 break; 723 724 #ifdef TCP_OFFLOAD 725 if (sc->flags & INTR_DIRECT) 726 rc += p->nrxq + p->nofldrxq; 727 else 728 rc += max(p->nrxq, p->nofldrxq); 729 #else 730 /* 731 * Not compiled with offload support and intr_count > 1. Only 732 * NIC queues exist and they'd better be taking direct 733 * interrupts. 734 */ 735 KASSERT(sc->flags & INTR_DIRECT, 736 ("%s: intr_count %d, !INTR_DIRECT", __func__, 737 sc->intr_count)); 738 739 rc += p->nrxq; 740 #endif 741 } 742 743 return (rc); 744 } 745 746 /* 747 * Given an arbitrary "index," come up with an iq that can be used by other 748 * queues (of this port) for interrupt forwarding, SGE egress updates, etc. 749 * The iq returned is guaranteed to be something that takes direct interrupts. 750 */ 751 static struct sge_iq * 752 port_intr_iq(struct port_info *pi, int idx) 753 { 754 struct adapter *sc = pi->adapter; 755 struct sge *s = &sc->sge; 756 struct sge_iq *iq = NULL; 757 758 if (sc->intr_count == 1) 759 return (&sc->sge.fwq); 760 761 #ifdef TCP_OFFLOAD 762 if (sc->flags & INTR_DIRECT) { 763 idx %= pi->nrxq + pi->nofldrxq; 764 765 if (idx >= pi->nrxq) { 766 idx -= pi->nrxq; 767 iq = &s->ofld_rxq[pi->first_ofld_rxq + idx].iq; 768 } else 769 iq = &s->rxq[pi->first_rxq + idx].iq; 770 771 } else { 772 idx %= max(pi->nrxq, pi->nofldrxq); 773 774 if (pi->nrxq >= pi->nofldrxq) 775 iq = &s->rxq[pi->first_rxq + idx].iq; 776 else 777 iq = &s->ofld_rxq[pi->first_ofld_rxq + idx].iq; 778 } 779 #else 780 /* 781 * Not compiled with offload support and intr_count > 1. Only NIC 782 * queues exist and they'd better be taking direct interrupts. 783 */ 784 KASSERT(sc->flags & INTR_DIRECT, 785 ("%s: intr_count %d, !INTR_DIRECT", __func__, sc->intr_count)); 786 787 idx %= pi->nrxq; 788 iq = &s->rxq[pi->first_rxq + idx].iq; 789 #endif 790 791 KASSERT(iq->flags & IQ_INTR, ("%s: EDOOFUS", __func__)); 792 return (iq); 793 } 794 795 static inline int 796 mtu_to_bufsize(int mtu) 797 { 798 int bufsize; 799 800 /* large enough for a frame even when VLAN extraction is disabled */ 801 bufsize = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + mtu; 802 bufsize = roundup2(bufsize + fl_pktshift, fl_pad); 803 804 return (bufsize); 805 } 806 807 #ifdef TCP_OFFLOAD 808 static inline int 809 mtu_to_bufsize_toe(struct adapter *sc, int mtu) 810 { 811 812 if (sc->tt.rx_coalesce) 813 return (G_RXCOALESCESIZE(t4_read_reg(sc, A_TP_PARA_REG2))); 814 815 return (mtu); 816 } 817 #endif 818 819 int 820 t4_setup_port_queues(struct port_info *pi) 821 { 822 int rc = 0, i, j, intr_idx, iqid; 823 struct sge_rxq *rxq; 824 struct sge_txq *txq; 825 struct sge_wrq *ctrlq; 826 #ifdef TCP_OFFLOAD 827 struct sge_ofld_rxq *ofld_rxq; 828 struct sge_wrq *ofld_txq; 829 struct sysctl_oid *oid2 = NULL; 830 #endif 831 char name[16]; 832 struct adapter *sc = pi->adapter; 833 struct ifnet *ifp = pi->ifp; 834 struct sysctl_oid *oid = device_get_sysctl_tree(pi->dev); 835 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 836 int bufsize, pack; 837 838 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "rxq", CTLFLAG_RD, 839 NULL, "rx queues"); 840 841 #ifdef TCP_OFFLOAD 842 if (is_offload(sc)) { 843 oid2 = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "ofld_rxq", 844 CTLFLAG_RD, NULL, 845 "rx queues for offloaded TCP connections"); 846 } 847 #endif 848 849 /* Interrupt vector to start from (when using multiple vectors) */ 850 intr_idx = first_vector(pi); 851 852 /* 853 * First pass over all rx queues (NIC and TOE): 854 * a) initialize iq and fl 855 * b) allocate queue iff it will take direct interrupts. 856 */ 857 bufsize = mtu_to_bufsize(ifp->if_mtu); 858 pack = enable_buffer_packing(sc); 859 for_each_rxq(pi, i, rxq) { 860 861 init_iq(&rxq->iq, sc, pi->tmr_idx, pi->pktc_idx, pi->qsize_rxq, 862 RX_IQ_ESIZE); 863 864 snprintf(name, sizeof(name), "%s rxq%d-fl", 865 device_get_nameunit(pi->dev), i); 866 init_fl(sc, &rxq->fl, pi->qsize_rxq / 8, bufsize, pack, name); 867 868 if (sc->flags & INTR_DIRECT 869 #ifdef TCP_OFFLOAD 870 || (sc->intr_count > 1 && pi->nrxq >= pi->nofldrxq) 871 #endif 872 ) { 873 rxq->iq.flags |= IQ_INTR; 874 rc = alloc_rxq(pi, rxq, intr_idx, i, oid); 875 if (rc != 0) 876 goto done; 877 intr_idx++; 878 } 879 } 880 881 #ifdef TCP_OFFLOAD 882 bufsize = mtu_to_bufsize_toe(sc, ifp->if_mtu); 883 pack = 0; /* XXX: think about this some more */ 884 for_each_ofld_rxq(pi, i, ofld_rxq) { 885 886 init_iq(&ofld_rxq->iq, sc, pi->tmr_idx, pi->pktc_idx, 887 pi->qsize_rxq, RX_IQ_ESIZE); 888 889 snprintf(name, sizeof(name), "%s ofld_rxq%d-fl", 890 device_get_nameunit(pi->dev), i); 891 init_fl(sc, &ofld_rxq->fl, pi->qsize_rxq / 8, bufsize, pack, 892 name); 893 894 if (sc->flags & INTR_DIRECT || 895 (sc->intr_count > 1 && pi->nofldrxq > pi->nrxq)) { 896 ofld_rxq->iq.flags |= IQ_INTR; 897 rc = alloc_ofld_rxq(pi, ofld_rxq, intr_idx, i, oid2); 898 if (rc != 0) 899 goto done; 900 intr_idx++; 901 } 902 } 903 #endif 904 905 /* 906 * Second pass over all rx queues (NIC and TOE). The queues forwarding 907 * their interrupts are allocated now. 908 */ 909 j = 0; 910 for_each_rxq(pi, i, rxq) { 911 if (rxq->iq.flags & IQ_INTR) 912 continue; 913 914 intr_idx = port_intr_iq(pi, j)->abs_id; 915 916 rc = alloc_rxq(pi, rxq, intr_idx, i, oid); 917 if (rc != 0) 918 goto done; 919 j++; 920 } 921 922 #ifdef TCP_OFFLOAD 923 for_each_ofld_rxq(pi, i, ofld_rxq) { 924 if (ofld_rxq->iq.flags & IQ_INTR) 925 continue; 926 927 intr_idx = port_intr_iq(pi, j)->abs_id; 928 929 rc = alloc_ofld_rxq(pi, ofld_rxq, intr_idx, i, oid2); 930 if (rc != 0) 931 goto done; 932 j++; 933 } 934 #endif 935 936 /* 937 * Now the tx queues. Only one pass needed. 938 */ 939 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "txq", CTLFLAG_RD, 940 NULL, "tx queues"); 941 j = 0; 942 for_each_txq(pi, i, txq) { 943 uint16_t iqid; 944 945 iqid = port_intr_iq(pi, j)->cntxt_id; 946 947 snprintf(name, sizeof(name), "%s txq%d", 948 device_get_nameunit(pi->dev), i); 949 init_eq(&txq->eq, EQ_ETH, pi->qsize_txq, pi->tx_chan, iqid, 950 name); 951 952 rc = alloc_txq(pi, txq, i, oid); 953 if (rc != 0) 954 goto done; 955 j++; 956 } 957 958 #ifdef TCP_OFFLOAD 959 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "ofld_txq", 960 CTLFLAG_RD, NULL, "tx queues for offloaded TCP connections"); 961 for_each_ofld_txq(pi, i, ofld_txq) { 962 uint16_t iqid; 963 964 iqid = port_intr_iq(pi, j)->cntxt_id; 965 966 snprintf(name, sizeof(name), "%s ofld_txq%d", 967 device_get_nameunit(pi->dev), i); 968 init_eq(&ofld_txq->eq, EQ_OFLD, pi->qsize_txq, pi->tx_chan, 969 iqid, name); 970 971 snprintf(name, sizeof(name), "%d", i); 972 oid2 = SYSCTL_ADD_NODE(&pi->ctx, SYSCTL_CHILDREN(oid), OID_AUTO, 973 name, CTLFLAG_RD, NULL, "offload tx queue"); 974 975 rc = alloc_wrq(sc, pi, ofld_txq, oid2); 976 if (rc != 0) 977 goto done; 978 j++; 979 } 980 #endif 981 982 /* 983 * Finally, the control queue. 984 */ 985 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "ctrlq", CTLFLAG_RD, 986 NULL, "ctrl queue"); 987 ctrlq = &sc->sge.ctrlq[pi->port_id]; 988 iqid = port_intr_iq(pi, 0)->cntxt_id; 989 snprintf(name, sizeof(name), "%s ctrlq", device_get_nameunit(pi->dev)); 990 init_eq(&ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE, pi->tx_chan, iqid, name); 991 rc = alloc_wrq(sc, pi, ctrlq, oid); 992 993 done: 994 if (rc) 995 t4_teardown_port_queues(pi); 996 997 return (rc); 998 } 999 1000 /* 1001 * Idempotent 1002 */ 1003 int 1004 t4_teardown_port_queues(struct port_info *pi) 1005 { 1006 int i; 1007 struct adapter *sc = pi->adapter; 1008 struct sge_rxq *rxq; 1009 struct sge_txq *txq; 1010 #ifdef TCP_OFFLOAD 1011 struct sge_ofld_rxq *ofld_rxq; 1012 struct sge_wrq *ofld_txq; 1013 #endif 1014 1015 /* Do this before freeing the queues */ 1016 if (pi->flags & PORT_SYSCTL_CTX) { 1017 sysctl_ctx_free(&pi->ctx); 1018 pi->flags &= ~PORT_SYSCTL_CTX; 1019 } 1020 1021 /* 1022 * Take down all the tx queues first, as they reference the rx queues 1023 * (for egress updates, etc.). 1024 */ 1025 1026 free_wrq(sc, &sc->sge.ctrlq[pi->port_id]); 1027 1028 for_each_txq(pi, i, txq) { 1029 free_txq(pi, txq); 1030 } 1031 1032 #ifdef TCP_OFFLOAD 1033 for_each_ofld_txq(pi, i, ofld_txq) { 1034 free_wrq(sc, ofld_txq); 1035 } 1036 #endif 1037 1038 /* 1039 * Then take down the rx queues that forward their interrupts, as they 1040 * reference other rx queues. 1041 */ 1042 1043 for_each_rxq(pi, i, rxq) { 1044 if ((rxq->iq.flags & IQ_INTR) == 0) 1045 free_rxq(pi, rxq); 1046 } 1047 1048 #ifdef TCP_OFFLOAD 1049 for_each_ofld_rxq(pi, i, ofld_rxq) { 1050 if ((ofld_rxq->iq.flags & IQ_INTR) == 0) 1051 free_ofld_rxq(pi, ofld_rxq); 1052 } 1053 #endif 1054 1055 /* 1056 * Then take down the rx queues that take direct interrupts. 1057 */ 1058 1059 for_each_rxq(pi, i, rxq) { 1060 if (rxq->iq.flags & IQ_INTR) 1061 free_rxq(pi, rxq); 1062 } 1063 1064 #ifdef TCP_OFFLOAD 1065 for_each_ofld_rxq(pi, i, ofld_rxq) { 1066 if (ofld_rxq->iq.flags & IQ_INTR) 1067 free_ofld_rxq(pi, ofld_rxq); 1068 } 1069 #endif 1070 1071 return (0); 1072 } 1073 1074 /* 1075 * Deals with errors and the firmware event queue. All data rx queues forward 1076 * their interrupt to the firmware event queue. 1077 */ 1078 void 1079 t4_intr_all(void *arg) 1080 { 1081 struct adapter *sc = arg; 1082 struct sge_iq *fwq = &sc->sge.fwq; 1083 1084 t4_intr_err(arg); 1085 if (atomic_cmpset_int(&fwq->state, IQS_IDLE, IQS_BUSY)) { 1086 service_iq(fwq, 0); 1087 atomic_cmpset_int(&fwq->state, IQS_BUSY, IQS_IDLE); 1088 } 1089 } 1090 1091 /* Deals with error interrupts */ 1092 void 1093 t4_intr_err(void *arg) 1094 { 1095 struct adapter *sc = arg; 1096 1097 t4_write_reg(sc, MYPF_REG(A_PCIE_PF_CLI), 0); 1098 t4_slow_intr_handler(sc); 1099 } 1100 1101 void 1102 t4_intr_evt(void *arg) 1103 { 1104 struct sge_iq *iq = arg; 1105 1106 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 1107 service_iq(iq, 0); 1108 atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 1109 } 1110 } 1111 1112 void 1113 t4_intr(void *arg) 1114 { 1115 struct sge_iq *iq = arg; 1116 1117 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 1118 service_iq(iq, 0); 1119 atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 1120 } 1121 } 1122 1123 /* 1124 * Deals with anything and everything on the given ingress queue. 1125 */ 1126 static int 1127 service_iq(struct sge_iq *iq, int budget) 1128 { 1129 struct sge_iq *q; 1130 struct sge_rxq *rxq = iq_to_rxq(iq); /* Use iff iq is part of rxq */ 1131 struct sge_fl *fl = &rxq->fl; /* Use iff IQ_HAS_FL */ 1132 struct adapter *sc = iq->adapter; 1133 struct rsp_ctrl *ctrl; 1134 const struct rss_header *rss; 1135 int ndescs = 0, limit, fl_bufs_used = 0; 1136 int rsp_type; 1137 uint32_t lq; 1138 struct mbuf *m0; 1139 STAILQ_HEAD(, sge_iq) iql = STAILQ_HEAD_INITIALIZER(iql); 1140 #if defined(INET) || defined(INET6) 1141 const struct timeval lro_timeout = {0, sc->lro_timeout}; 1142 #endif 1143 1144 limit = budget ? budget : iq->qsize / 8; 1145 1146 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq)); 1147 1148 /* 1149 * We always come back and check the descriptor ring for new indirect 1150 * interrupts and other responses after running a single handler. 1151 */ 1152 for (;;) { 1153 while (is_new_response(iq, &ctrl)) { 1154 1155 rmb(); 1156 1157 m0 = NULL; 1158 rsp_type = G_RSPD_TYPE(ctrl->u.type_gen); 1159 lq = be32toh(ctrl->pldbuflen_qid); 1160 rss = (const void *)iq->cdesc; 1161 1162 switch (rsp_type) { 1163 case X_RSPD_TYPE_FLBUF: 1164 1165 KASSERT(iq->flags & IQ_HAS_FL, 1166 ("%s: data for an iq (%p) with no freelist", 1167 __func__, iq)); 1168 1169 m0 = fl->flags & FL_BUF_PACKING ? 1170 get_fl_payload1(sc, fl, lq, &fl_bufs_used) : 1171 get_fl_payload2(sc, fl, lq, &fl_bufs_used); 1172 1173 if (__predict_false(m0 == NULL)) 1174 goto process_iql; 1175 #ifdef T4_PKT_TIMESTAMP 1176 /* 1177 * 60 bit timestamp for the payload is 1178 * *(uint64_t *)m0->m_pktdat. Note that it is 1179 * in the leading free-space in the mbuf. The 1180 * kernel can clobber it during a pullup, 1181 * m_copymdata, etc. You need to make sure that 1182 * the mbuf reaches you unmolested if you care 1183 * about the timestamp. 1184 */ 1185 *(uint64_t *)m0->m_pktdat = 1186 be64toh(ctrl->u.last_flit) & 1187 0xfffffffffffffff; 1188 #endif 1189 1190 /* fall through */ 1191 1192 case X_RSPD_TYPE_CPL: 1193 KASSERT(rss->opcode < NUM_CPL_CMDS, 1194 ("%s: bad opcode %02x.", __func__, 1195 rss->opcode)); 1196 sc->cpl_handler[rss->opcode](iq, rss, m0); 1197 break; 1198 1199 case X_RSPD_TYPE_INTR: 1200 1201 /* 1202 * Interrupts should be forwarded only to queues 1203 * that are not forwarding their interrupts. 1204 * This means service_iq can recurse but only 1 1205 * level deep. 1206 */ 1207 KASSERT(budget == 0, 1208 ("%s: budget %u, rsp_type %u", __func__, 1209 budget, rsp_type)); 1210 1211 /* 1212 * There are 1K interrupt-capable queues (qids 0 1213 * through 1023). A response type indicating a 1214 * forwarded interrupt with a qid >= 1K is an 1215 * iWARP async notification. 1216 */ 1217 if (lq >= 1024) { 1218 sc->an_handler(iq, ctrl); 1219 break; 1220 } 1221 1222 q = sc->sge.iqmap[lq - sc->sge.iq_start]; 1223 if (atomic_cmpset_int(&q->state, IQS_IDLE, 1224 IQS_BUSY)) { 1225 if (service_iq(q, q->qsize / 8) == 0) { 1226 atomic_cmpset_int(&q->state, 1227 IQS_BUSY, IQS_IDLE); 1228 } else { 1229 STAILQ_INSERT_TAIL(&iql, q, 1230 link); 1231 } 1232 } 1233 break; 1234 1235 default: 1236 KASSERT(0, 1237 ("%s: illegal response type %d on iq %p", 1238 __func__, rsp_type, iq)); 1239 log(LOG_ERR, 1240 "%s: illegal response type %d on iq %p", 1241 device_get_nameunit(sc->dev), rsp_type, iq); 1242 break; 1243 } 1244 1245 iq_next(iq); 1246 if (++ndescs == limit) { 1247 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), 1248 V_CIDXINC(ndescs) | 1249 V_INGRESSQID(iq->cntxt_id) | 1250 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); 1251 ndescs = 0; 1252 1253 #if defined(INET) || defined(INET6) 1254 if (iq->flags & IQ_LRO_ENABLED && 1255 sc->lro_timeout != 0) { 1256 tcp_lro_flush_inactive(&rxq->lro, 1257 &lro_timeout); 1258 } 1259 #endif 1260 1261 if (fl_bufs_used > 0) { 1262 FL_LOCK(fl); 1263 fl->needed += fl_bufs_used; 1264 refill_fl(sc, fl, fl->cap / 8); 1265 FL_UNLOCK(fl); 1266 fl_bufs_used = 0; 1267 } 1268 1269 if (budget) 1270 return (EINPROGRESS); 1271 } 1272 } 1273 1274 process_iql: 1275 if (STAILQ_EMPTY(&iql)) 1276 break; 1277 1278 /* 1279 * Process the head only, and send it to the back of the list if 1280 * it's still not done. 1281 */ 1282 q = STAILQ_FIRST(&iql); 1283 STAILQ_REMOVE_HEAD(&iql, link); 1284 if (service_iq(q, q->qsize / 8) == 0) 1285 atomic_cmpset_int(&q->state, IQS_BUSY, IQS_IDLE); 1286 else 1287 STAILQ_INSERT_TAIL(&iql, q, link); 1288 } 1289 1290 #if defined(INET) || defined(INET6) 1291 if (iq->flags & IQ_LRO_ENABLED) { 1292 struct lro_ctrl *lro = &rxq->lro; 1293 struct lro_entry *l; 1294 1295 while (!SLIST_EMPTY(&lro->lro_active)) { 1296 l = SLIST_FIRST(&lro->lro_active); 1297 SLIST_REMOVE_HEAD(&lro->lro_active, next); 1298 tcp_lro_flush(lro, l); 1299 } 1300 } 1301 #endif 1302 1303 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), V_CIDXINC(ndescs) | 1304 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params)); 1305 1306 if (iq->flags & IQ_HAS_FL) { 1307 int starved; 1308 1309 FL_LOCK(fl); 1310 fl->needed += fl_bufs_used; 1311 starved = refill_fl(sc, fl, fl->cap / 4); 1312 FL_UNLOCK(fl); 1313 if (__predict_false(starved != 0)) 1314 add_fl_to_sfl(sc, fl); 1315 } 1316 1317 return (0); 1318 } 1319 1320 static int 1321 fill_mbuf_stash(struct sge_fl *fl) 1322 { 1323 int i; 1324 1325 for (i = 0; i < nitems(fl->mstash); i++) { 1326 if (fl->mstash[i] == NULL) { 1327 struct mbuf *m; 1328 if ((m = m_get(M_NOWAIT, MT_NOINIT)) == NULL) 1329 return (ENOBUFS); 1330 fl->mstash[i] = m; 1331 } 1332 } 1333 return (0); 1334 } 1335 1336 static struct mbuf * 1337 get_mbuf_from_stash(struct sge_fl *fl) 1338 { 1339 int i; 1340 1341 for (i = 0; i < nitems(fl->mstash); i++) { 1342 if (fl->mstash[i] != NULL) { 1343 struct mbuf *m; 1344 1345 m = fl->mstash[i]; 1346 fl->mstash[i] = NULL; 1347 return (m); 1348 } else 1349 fl->mstash[i] = m_get(M_NOWAIT, MT_NOINIT); 1350 } 1351 1352 return (m_get(M_NOWAIT, MT_NOINIT)); 1353 } 1354 1355 static void 1356 return_mbuf_to_stash(struct sge_fl *fl, struct mbuf *m) 1357 { 1358 int i; 1359 1360 if (m == NULL) 1361 return; 1362 1363 for (i = 0; i < nitems(fl->mstash); i++) { 1364 if (fl->mstash[i] == NULL) { 1365 fl->mstash[i] = m; 1366 return; 1367 } 1368 } 1369 m_init(m, NULL, 0, M_NOWAIT, MT_DATA, 0); 1370 m_free(m); 1371 } 1372 1373 /* buf can be any address within the buffer */ 1374 static inline u_int * 1375 find_buf_refcnt(caddr_t buf) 1376 { 1377 uintptr_t ptr = (uintptr_t)buf; 1378 1379 return ((u_int *)((ptr & ~(MJUMPAGESIZE - 1)) + MSIZE - sizeof(u_int))); 1380 } 1381 1382 static inline struct mbuf * 1383 find_buf_mbuf(caddr_t buf) 1384 { 1385 uintptr_t ptr = (uintptr_t)buf; 1386 1387 return ((struct mbuf *)(ptr & ~(MJUMPAGESIZE - 1))); 1388 } 1389 1390 static int 1391 rxb_free(struct mbuf *m, void *arg1, void *arg2) 1392 { 1393 uma_zone_t zone = arg1; 1394 caddr_t cl = arg2; 1395 #ifdef INVARIANTS 1396 u_int refcount; 1397 1398 refcount = *find_buf_refcnt(cl); 1399 KASSERT(refcount == 0, ("%s: cl %p refcount is %u", __func__, 1400 cl - MSIZE, refcount)); 1401 #endif 1402 cl -= MSIZE; 1403 uma_zfree(zone, cl); 1404 1405 return (EXT_FREE_OK); 1406 } 1407 1408 static struct mbuf * 1409 get_fl_payload1(struct adapter *sc, struct sge_fl *fl, uint32_t len_newbuf, 1410 int *fl_bufs_used) 1411 { 1412 struct mbuf *m0, *m; 1413 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 1414 unsigned int nbuf, len; 1415 int pack_boundary = is_t4(sc) ? t4_fl_pack : t5_fl_pack; 1416 1417 /* 1418 * No assertion for the fl lock because we don't need it. This routine 1419 * is called only from the rx interrupt handler and it only updates 1420 * fl->cidx. (Contrast that with fl->pidx/fl->needed which could be 1421 * updated in the rx interrupt handler or the starvation helper routine. 1422 * That's why code that manipulates fl->pidx/fl->needed needs the fl 1423 * lock but this routine does not). 1424 */ 1425 1426 KASSERT(fl->flags & FL_BUF_PACKING, 1427 ("%s: buffer packing disabled for fl %p", __func__, fl)); 1428 1429 len = G_RSPD_LEN(len_newbuf); 1430 1431 if ((len_newbuf & F_RSPD_NEWBUF) == 0) { 1432 KASSERT(fl->rx_offset > 0, 1433 ("%s: packed frame but driver at offset=0", __func__)); 1434 1435 /* A packed frame is guaranteed to fit entirely in this buf. */ 1436 KASSERT(FL_BUF_SIZE(sc, sd->tag_idx) - fl->rx_offset >= len, 1437 ("%s: packing error. bufsz=%u, offset=%u, len=%u", 1438 __func__, FL_BUF_SIZE(sc, sd->tag_idx), fl->rx_offset, 1439 len)); 1440 1441 m0 = get_mbuf_from_stash(fl); 1442 if (m0 == NULL || 1443 m_init(m0, NULL, 0, M_NOWAIT, MT_DATA, M_PKTHDR) != 0) { 1444 return_mbuf_to_stash(fl, m0); 1445 return (NULL); 1446 } 1447 1448 bus_dmamap_sync(fl->tag[sd->tag_idx], sd->map, 1449 BUS_DMASYNC_POSTREAD); 1450 if (len < RX_COPY_THRESHOLD) { 1451 #ifdef T4_PKT_TIMESTAMP 1452 /* Leave room for a timestamp */ 1453 m0->m_data += 8; 1454 #endif 1455 bcopy(sd->cl + fl->rx_offset, mtod(m0, caddr_t), len); 1456 m0->m_pkthdr.len = len; 1457 m0->m_len = len; 1458 } else { 1459 m0->m_pkthdr.len = len; 1460 m0->m_len = len; 1461 m_extaddref(m0, sd->cl + fl->rx_offset, 1462 roundup2(m0->m_len, fl_pad), 1463 find_buf_refcnt(sd->cl), rxb_free, 1464 FL_BUF_ZONE(sc, sd->tag_idx), sd->cl); 1465 } 1466 fl->rx_offset += len; 1467 fl->rx_offset = roundup2(fl->rx_offset, fl_pad); 1468 fl->rx_offset = roundup2(fl->rx_offset, pack_boundary); 1469 if (fl->rx_offset >= FL_BUF_SIZE(sc, sd->tag_idx)) { 1470 fl->rx_offset = 0; 1471 (*fl_bufs_used) += 1; 1472 if (__predict_false(++fl->cidx == fl->cap)) 1473 fl->cidx = 0; 1474 } 1475 1476 return (m0); 1477 } 1478 1479 KASSERT(len_newbuf & F_RSPD_NEWBUF, 1480 ("%s: only new buffer handled here", __func__)); 1481 1482 nbuf = 0; 1483 1484 /* 1485 * Move to the start of the next buffer if we are still in the middle of 1486 * some buffer. This is the case where there was some room left in the 1487 * previous buffer but not enough to fit this frame in its entirety. 1488 */ 1489 if (fl->rx_offset > 0) { 1490 KASSERT(roundup2(len, fl_pad) > FL_BUF_SIZE(sc, sd->tag_idx) - 1491 fl->rx_offset, ("%s: frame (%u bytes) should have fit at " 1492 "cidx %u offset %u bufsize %u", __func__, len, fl->cidx, 1493 fl->rx_offset, FL_BUF_SIZE(sc, sd->tag_idx))); 1494 nbuf++; 1495 fl->rx_offset = 0; 1496 sd++; 1497 if (__predict_false(++fl->cidx == fl->cap)) { 1498 sd = fl->sdesc; 1499 fl->cidx = 0; 1500 } 1501 } 1502 1503 m0 = find_buf_mbuf(sd->cl); 1504 if (m_init(m0, NULL, 0, M_NOWAIT, MT_DATA, M_PKTHDR | M_NOFREE)) 1505 goto done; 1506 bus_dmamap_sync(fl->tag[sd->tag_idx], sd->map, BUS_DMASYNC_POSTREAD); 1507 m0->m_len = min(len, FL_BUF_SIZE(sc, sd->tag_idx)); 1508 m_extaddref(m0, sd->cl, roundup2(m0->m_len, fl_pad), 1509 find_buf_refcnt(sd->cl), rxb_free, FL_BUF_ZONE(sc, sd->tag_idx), 1510 sd->cl); 1511 m0->m_pkthdr.len = len; 1512 1513 fl->rx_offset = roundup2(m0->m_len, fl_pad); 1514 fl->rx_offset = roundup2(fl->rx_offset, pack_boundary); 1515 if (fl->rx_offset >= FL_BUF_SIZE(sc, sd->tag_idx)) { 1516 fl->rx_offset = 0; 1517 nbuf++; 1518 sd++; 1519 if (__predict_false(++fl->cidx == fl->cap)) { 1520 sd = fl->sdesc; 1521 fl->cidx = 0; 1522 } 1523 } 1524 1525 m = m0; 1526 len -= m->m_len; 1527 1528 while (len > 0) { 1529 m->m_next = find_buf_mbuf(sd->cl); 1530 m = m->m_next; 1531 1532 bus_dmamap_sync(fl->tag[sd->tag_idx], sd->map, 1533 BUS_DMASYNC_POSTREAD); 1534 1535 /* m_init for !M_PKTHDR can't fail so don't bother */ 1536 m_init(m, NULL, 0, M_NOWAIT, MT_DATA, M_NOFREE); 1537 m->m_len = min(len, FL_BUF_SIZE(sc, sd->tag_idx)); 1538 m_extaddref(m, sd->cl, roundup2(m->m_len, fl_pad), 1539 find_buf_refcnt(sd->cl), rxb_free, 1540 FL_BUF_ZONE(sc, sd->tag_idx), sd->cl); 1541 1542 fl->rx_offset = roundup2(m->m_len, fl_pad); 1543 fl->rx_offset = roundup2(fl->rx_offset, pack_boundary); 1544 if (fl->rx_offset >= FL_BUF_SIZE(sc, sd->tag_idx)) { 1545 fl->rx_offset = 0; 1546 nbuf++; 1547 sd++; 1548 if (__predict_false(++fl->cidx == fl->cap)) { 1549 sd = fl->sdesc; 1550 fl->cidx = 0; 1551 } 1552 } 1553 1554 len -= m->m_len; 1555 } 1556 done: 1557 (*fl_bufs_used) += nbuf; 1558 return (m0); 1559 } 1560 1561 static struct mbuf * 1562 get_fl_payload2(struct adapter *sc, struct sge_fl *fl, uint32_t len_newbuf, 1563 int *fl_bufs_used) 1564 { 1565 struct mbuf *m0, *m; 1566 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 1567 unsigned int nbuf, len; 1568 1569 /* 1570 * No assertion for the fl lock because we don't need it. This routine 1571 * is called only from the rx interrupt handler and it only updates 1572 * fl->cidx. (Contrast that with fl->pidx/fl->needed which could be 1573 * updated in the rx interrupt handler or the starvation helper routine. 1574 * That's why code that manipulates fl->pidx/fl->needed needs the fl 1575 * lock but this routine does not). 1576 */ 1577 1578 KASSERT((fl->flags & FL_BUF_PACKING) == 0, 1579 ("%s: buffer packing enabled for fl %p", __func__, fl)); 1580 if (__predict_false((len_newbuf & F_RSPD_NEWBUF) == 0)) 1581 panic("%s: cannot handle packed frames", __func__); 1582 len = G_RSPD_LEN(len_newbuf); 1583 1584 /* 1585 * We never want to run out of mbufs in between a frame when a frame 1586 * spans multiple fl buffers. If the fl's mbuf stash isn't full and 1587 * can't be filled up to the brim then fail early. 1588 */ 1589 if (len > FL_BUF_SIZE(sc, sd->tag_idx) && fill_mbuf_stash(fl) != 0) 1590 return (NULL); 1591 1592 m0 = get_mbuf_from_stash(fl); 1593 if (m0 == NULL || 1594 m_init(m0, NULL, 0, M_NOWAIT, MT_DATA, M_PKTHDR) != 0) { 1595 return_mbuf_to_stash(fl, m0); 1596 return (NULL); 1597 } 1598 1599 bus_dmamap_sync(fl->tag[sd->tag_idx], sd->map, BUS_DMASYNC_POSTREAD); 1600 1601 if (len < RX_COPY_THRESHOLD) { 1602 #ifdef T4_PKT_TIMESTAMP 1603 /* Leave room for a timestamp */ 1604 m0->m_data += 8; 1605 #endif 1606 /* copy data to mbuf, buffer will be recycled */ 1607 bcopy(sd->cl, mtod(m0, caddr_t), len); 1608 m0->m_len = len; 1609 } else { 1610 bus_dmamap_unload(fl->tag[sd->tag_idx], sd->map); 1611 m_cljset(m0, sd->cl, FL_BUF_TYPE(sc, sd->tag_idx)); 1612 sd->cl = NULL; /* consumed */ 1613 m0->m_len = min(len, FL_BUF_SIZE(sc, sd->tag_idx)); 1614 } 1615 m0->m_pkthdr.len = len; 1616 1617 sd++; 1618 if (__predict_false(++fl->cidx == fl->cap)) { 1619 sd = fl->sdesc; 1620 fl->cidx = 0; 1621 } 1622 1623 m = m0; 1624 len -= m->m_len; 1625 nbuf = 1; /* # of fl buffers used */ 1626 1627 while (len > 0) { 1628 /* Can't fail, we checked earlier that the stash was full. */ 1629 m->m_next = get_mbuf_from_stash(fl); 1630 m = m->m_next; 1631 1632 bus_dmamap_sync(fl->tag[sd->tag_idx], sd->map, 1633 BUS_DMASYNC_POSTREAD); 1634 1635 /* m_init for !M_PKTHDR can't fail so don't bother */ 1636 m_init(m, NULL, 0, M_NOWAIT, MT_DATA, 0); 1637 if (len <= MLEN) { 1638 bcopy(sd->cl, mtod(m, caddr_t), len); 1639 m->m_len = len; 1640 } else { 1641 bus_dmamap_unload(fl->tag[sd->tag_idx], sd->map); 1642 m_cljset(m, sd->cl, FL_BUF_TYPE(sc, sd->tag_idx)); 1643 sd->cl = NULL; /* consumed */ 1644 m->m_len = min(len, FL_BUF_SIZE(sc, sd->tag_idx)); 1645 } 1646 1647 sd++; 1648 if (__predict_false(++fl->cidx == fl->cap)) { 1649 sd = fl->sdesc; 1650 fl->cidx = 0; 1651 } 1652 1653 len -= m->m_len; 1654 nbuf++; 1655 } 1656 1657 (*fl_bufs_used) += nbuf; 1658 1659 return (m0); 1660 } 1661 1662 static int 1663 t4_eth_rx(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0) 1664 { 1665 struct sge_rxq *rxq = iq_to_rxq(iq); 1666 struct ifnet *ifp = rxq->ifp; 1667 const struct cpl_rx_pkt *cpl = (const void *)(rss + 1); 1668 #if defined(INET) || defined(INET6) 1669 struct lro_ctrl *lro = &rxq->lro; 1670 #endif 1671 1672 KASSERT(m0 != NULL, ("%s: no payload with opcode %02x", __func__, 1673 rss->opcode)); 1674 1675 m0->m_pkthdr.len -= fl_pktshift; 1676 m0->m_len -= fl_pktshift; 1677 m0->m_data += fl_pktshift; 1678 1679 m0->m_pkthdr.rcvif = ifp; 1680 m0->m_flags |= M_FLOWID; 1681 m0->m_pkthdr.flowid = rss->hash_val; 1682 1683 if (cpl->csum_calc && !cpl->err_vec) { 1684 if (ifp->if_capenable & IFCAP_RXCSUM && 1685 cpl->l2info & htobe32(F_RXF_IP)) { 1686 m0->m_pkthdr.csum_flags = (CSUM_IP_CHECKED | 1687 CSUM_IP_VALID | CSUM_DATA_VALID | CSUM_PSEUDO_HDR); 1688 rxq->rxcsum++; 1689 } else if (ifp->if_capenable & IFCAP_RXCSUM_IPV6 && 1690 cpl->l2info & htobe32(F_RXF_IP6)) { 1691 m0->m_pkthdr.csum_flags = (CSUM_DATA_VALID_IPV6 | 1692 CSUM_PSEUDO_HDR); 1693 rxq->rxcsum++; 1694 } 1695 1696 if (__predict_false(cpl->ip_frag)) 1697 m0->m_pkthdr.csum_data = be16toh(cpl->csum); 1698 else 1699 m0->m_pkthdr.csum_data = 0xffff; 1700 } 1701 1702 if (cpl->vlan_ex) { 1703 m0->m_pkthdr.ether_vtag = be16toh(cpl->vlan); 1704 m0->m_flags |= M_VLANTAG; 1705 rxq->vlan_extraction++; 1706 } 1707 1708 #if defined(INET) || defined(INET6) 1709 if (cpl->l2info & htobe32(F_RXF_LRO) && 1710 iq->flags & IQ_LRO_ENABLED && 1711 tcp_lro_rx(lro, m0, 0) == 0) { 1712 /* queued for LRO */ 1713 } else 1714 #endif 1715 ifp->if_input(ifp, m0); 1716 1717 return (0); 1718 } 1719 1720 /* 1721 * Doesn't fail. Holds on to work requests it can't send right away. 1722 */ 1723 void 1724 t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, struct wrqe *wr) 1725 { 1726 struct sge_eq *eq = &wrq->eq; 1727 int can_reclaim; 1728 caddr_t dst; 1729 1730 TXQ_LOCK_ASSERT_OWNED(wrq); 1731 #ifdef TCP_OFFLOAD 1732 KASSERT((eq->flags & EQ_TYPEMASK) == EQ_OFLD || 1733 (eq->flags & EQ_TYPEMASK) == EQ_CTRL, 1734 ("%s: eq type %d", __func__, eq->flags & EQ_TYPEMASK)); 1735 #else 1736 KASSERT((eq->flags & EQ_TYPEMASK) == EQ_CTRL, 1737 ("%s: eq type %d", __func__, eq->flags & EQ_TYPEMASK)); 1738 #endif 1739 1740 if (__predict_true(wr != NULL)) 1741 STAILQ_INSERT_TAIL(&wrq->wr_list, wr, link); 1742 1743 can_reclaim = reclaimable(eq); 1744 if (__predict_false(eq->flags & EQ_STALLED)) { 1745 if (can_reclaim < tx_resume_threshold(eq)) 1746 return; 1747 eq->flags &= ~EQ_STALLED; 1748 eq->unstalled++; 1749 } 1750 eq->cidx += can_reclaim; 1751 eq->avail += can_reclaim; 1752 if (__predict_false(eq->cidx >= eq->cap)) 1753 eq->cidx -= eq->cap; 1754 1755 while ((wr = STAILQ_FIRST(&wrq->wr_list)) != NULL) { 1756 int ndesc; 1757 1758 if (__predict_false(wr->wr_len < 0 || 1759 wr->wr_len > SGE_MAX_WR_LEN || (wr->wr_len & 0x7))) { 1760 1761 #ifdef INVARIANTS 1762 panic("%s: work request with length %d", __func__, 1763 wr->wr_len); 1764 #endif 1765 #ifdef KDB 1766 kdb_backtrace(); 1767 #endif 1768 log(LOG_ERR, "%s: %s work request with length %d", 1769 device_get_nameunit(sc->dev), __func__, wr->wr_len); 1770 STAILQ_REMOVE_HEAD(&wrq->wr_list, link); 1771 free_wrqe(wr); 1772 continue; 1773 } 1774 1775 ndesc = howmany(wr->wr_len, EQ_ESIZE); 1776 if (eq->avail < ndesc) { 1777 wrq->no_desc++; 1778 break; 1779 } 1780 1781 dst = (void *)&eq->desc[eq->pidx]; 1782 copy_to_txd(eq, wrtod(wr), &dst, wr->wr_len); 1783 1784 eq->pidx += ndesc; 1785 eq->avail -= ndesc; 1786 if (__predict_false(eq->pidx >= eq->cap)) 1787 eq->pidx -= eq->cap; 1788 1789 eq->pending += ndesc; 1790 if (eq->pending >= 8) 1791 ring_eq_db(sc, eq); 1792 1793 wrq->tx_wrs++; 1794 STAILQ_REMOVE_HEAD(&wrq->wr_list, link); 1795 free_wrqe(wr); 1796 1797 if (eq->avail < 8) { 1798 can_reclaim = reclaimable(eq); 1799 eq->cidx += can_reclaim; 1800 eq->avail += can_reclaim; 1801 if (__predict_false(eq->cidx >= eq->cap)) 1802 eq->cidx -= eq->cap; 1803 } 1804 } 1805 1806 if (eq->pending) 1807 ring_eq_db(sc, eq); 1808 1809 if (wr != NULL) { 1810 eq->flags |= EQ_STALLED; 1811 if (callout_pending(&eq->tx_callout) == 0) 1812 callout_reset(&eq->tx_callout, 1, t4_tx_callout, eq); 1813 } 1814 } 1815 1816 /* Per-packet header in a coalesced tx WR, before the SGL starts (in flits) */ 1817 #define TXPKTS_PKT_HDR ((\ 1818 sizeof(struct ulp_txpkt) + \ 1819 sizeof(struct ulptx_idata) + \ 1820 sizeof(struct cpl_tx_pkt_core) \ 1821 ) / 8) 1822 1823 /* Header of a coalesced tx WR, before SGL of first packet (in flits) */ 1824 #define TXPKTS_WR_HDR (\ 1825 sizeof(struct fw_eth_tx_pkts_wr) / 8 + \ 1826 TXPKTS_PKT_HDR) 1827 1828 /* Header of a tx WR, before SGL of first packet (in flits) */ 1829 #define TXPKT_WR_HDR ((\ 1830 sizeof(struct fw_eth_tx_pkt_wr) + \ 1831 sizeof(struct cpl_tx_pkt_core) \ 1832 ) / 8 ) 1833 1834 /* Header of a tx LSO WR, before SGL of first packet (in flits) */ 1835 #define TXPKT_LSO_WR_HDR ((\ 1836 sizeof(struct fw_eth_tx_pkt_wr) + \ 1837 sizeof(struct cpl_tx_pkt_lso_core) + \ 1838 sizeof(struct cpl_tx_pkt_core) \ 1839 ) / 8 ) 1840 1841 int 1842 t4_eth_tx(struct ifnet *ifp, struct sge_txq *txq, struct mbuf *m) 1843 { 1844 struct port_info *pi = (void *)ifp->if_softc; 1845 struct adapter *sc = pi->adapter; 1846 struct sge_eq *eq = &txq->eq; 1847 struct buf_ring *br = txq->br; 1848 struct mbuf *next; 1849 int rc, coalescing, can_reclaim; 1850 struct txpkts txpkts; 1851 struct sgl sgl; 1852 1853 TXQ_LOCK_ASSERT_OWNED(txq); 1854 KASSERT(m, ("%s: called with nothing to do.", __func__)); 1855 KASSERT((eq->flags & EQ_TYPEMASK) == EQ_ETH, 1856 ("%s: eq type %d", __func__, eq->flags & EQ_TYPEMASK)); 1857 1858 prefetch(&eq->desc[eq->pidx]); 1859 prefetch(&txq->sdesc[eq->pidx]); 1860 1861 txpkts.npkt = 0;/* indicates there's nothing in txpkts */ 1862 coalescing = 0; 1863 1864 can_reclaim = reclaimable(eq); 1865 if (__predict_false(eq->flags & EQ_STALLED)) { 1866 if (can_reclaim < tx_resume_threshold(eq)) { 1867 txq->m = m; 1868 return (0); 1869 } 1870 eq->flags &= ~EQ_STALLED; 1871 eq->unstalled++; 1872 } 1873 1874 if (__predict_false(eq->flags & EQ_DOOMED)) { 1875 m_freem(m); 1876 while ((m = buf_ring_dequeue_sc(txq->br)) != NULL) 1877 m_freem(m); 1878 return (ENETDOWN); 1879 } 1880 1881 if (eq->avail < 8 && can_reclaim) 1882 reclaim_tx_descs(txq, can_reclaim, 32); 1883 1884 for (; m; m = next ? next : drbr_dequeue(ifp, br)) { 1885 1886 if (eq->avail < 8) 1887 break; 1888 1889 next = m->m_nextpkt; 1890 m->m_nextpkt = NULL; 1891 1892 if (next || buf_ring_peek(br)) 1893 coalescing = 1; 1894 1895 rc = get_pkt_sgl(txq, &m, &sgl, coalescing); 1896 if (rc != 0) { 1897 if (rc == ENOMEM) { 1898 1899 /* Short of resources, suspend tx */ 1900 1901 m->m_nextpkt = next; 1902 break; 1903 } 1904 1905 /* 1906 * Unrecoverable error for this packet, throw it away 1907 * and move on to the next. get_pkt_sgl may already 1908 * have freed m (it will be NULL in that case and the 1909 * m_freem here is still safe). 1910 */ 1911 1912 m_freem(m); 1913 continue; 1914 } 1915 1916 if (coalescing && 1917 add_to_txpkts(pi, txq, &txpkts, m, &sgl) == 0) { 1918 1919 /* Successfully absorbed into txpkts */ 1920 1921 write_ulp_cpl_sgl(pi, txq, &txpkts, m, &sgl); 1922 goto doorbell; 1923 } 1924 1925 /* 1926 * We weren't coalescing to begin with, or current frame could 1927 * not be coalesced (add_to_txpkts flushes txpkts if a frame 1928 * given to it can't be coalesced). Either way there should be 1929 * nothing in txpkts. 1930 */ 1931 KASSERT(txpkts.npkt == 0, 1932 ("%s: txpkts not empty: %d", __func__, txpkts.npkt)); 1933 1934 /* We're sending out individual packets now */ 1935 coalescing = 0; 1936 1937 if (eq->avail < 8) 1938 reclaim_tx_descs(txq, 0, 8); 1939 rc = write_txpkt_wr(pi, txq, m, &sgl); 1940 if (rc != 0) { 1941 1942 /* Short of hardware descriptors, suspend tx */ 1943 1944 /* 1945 * This is an unlikely but expensive failure. We've 1946 * done all the hard work (DMA mappings etc.) and now we 1947 * can't send out the packet. What's worse, we have to 1948 * spend even more time freeing up everything in sgl. 1949 */ 1950 txq->no_desc++; 1951 free_pkt_sgl(txq, &sgl); 1952 1953 m->m_nextpkt = next; 1954 break; 1955 } 1956 1957 ETHER_BPF_MTAP(ifp, m); 1958 if (sgl.nsegs == 0) 1959 m_freem(m); 1960 doorbell: 1961 if (eq->pending >= 8) 1962 ring_eq_db(sc, eq); 1963 1964 can_reclaim = reclaimable(eq); 1965 if (can_reclaim >= 32) 1966 reclaim_tx_descs(txq, can_reclaim, 64); 1967 } 1968 1969 if (txpkts.npkt > 0) 1970 write_txpkts_wr(txq, &txpkts); 1971 1972 /* 1973 * m not NULL means there was an error but we haven't thrown it away. 1974 * This can happen when we're short of tx descriptors (no_desc) or maybe 1975 * even DMA maps (no_dmamap). Either way, a credit flush and reclaim 1976 * will get things going again. 1977 */ 1978 if (m && !(eq->flags & EQ_CRFLUSHED)) { 1979 struct tx_sdesc *txsd = &txq->sdesc[eq->pidx]; 1980 1981 /* 1982 * If EQ_CRFLUSHED is not set then we know we have at least one 1983 * available descriptor because any WR that reduces eq->avail to 1984 * 0 also sets EQ_CRFLUSHED. 1985 */ 1986 KASSERT(eq->avail > 0, ("%s: no space for eqflush.", __func__)); 1987 1988 txsd->desc_used = 1; 1989 txsd->credits = 0; 1990 write_eqflush_wr(eq); 1991 } 1992 txq->m = m; 1993 1994 if (eq->pending) 1995 ring_eq_db(sc, eq); 1996 1997 reclaim_tx_descs(txq, 0, 128); 1998 1999 if (eq->flags & EQ_STALLED && callout_pending(&eq->tx_callout) == 0) 2000 callout_reset(&eq->tx_callout, 1, t4_tx_callout, eq); 2001 2002 return (0); 2003 } 2004 2005 void 2006 t4_update_fl_bufsize(struct ifnet *ifp) 2007 { 2008 struct port_info *pi = ifp->if_softc; 2009 struct adapter *sc = pi->adapter; 2010 struct sge_rxq *rxq; 2011 #ifdef TCP_OFFLOAD 2012 struct sge_ofld_rxq *ofld_rxq; 2013 #endif 2014 struct sge_fl *fl; 2015 int i, bufsize; 2016 2017 bufsize = mtu_to_bufsize(ifp->if_mtu); 2018 for_each_rxq(pi, i, rxq) { 2019 fl = &rxq->fl; 2020 2021 FL_LOCK(fl); 2022 set_fl_tag_idx(sc, fl, bufsize); 2023 FL_UNLOCK(fl); 2024 } 2025 #ifdef TCP_OFFLOAD 2026 bufsize = mtu_to_bufsize_toe(pi->adapter, ifp->if_mtu); 2027 for_each_ofld_rxq(pi, i, ofld_rxq) { 2028 fl = &ofld_rxq->fl; 2029 2030 FL_LOCK(fl); 2031 set_fl_tag_idx(sc, fl, bufsize); 2032 FL_UNLOCK(fl); 2033 } 2034 #endif 2035 } 2036 2037 int 2038 can_resume_tx(struct sge_eq *eq) 2039 { 2040 return (reclaimable(eq) >= tx_resume_threshold(eq)); 2041 } 2042 2043 static inline void 2044 init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int pktc_idx, 2045 int qsize, int esize) 2046 { 2047 KASSERT(tmr_idx >= 0 && tmr_idx < SGE_NTIMERS, 2048 ("%s: bad tmr_idx %d", __func__, tmr_idx)); 2049 KASSERT(pktc_idx < SGE_NCOUNTERS, /* -ve is ok, means don't use */ 2050 ("%s: bad pktc_idx %d", __func__, pktc_idx)); 2051 2052 iq->flags = 0; 2053 iq->adapter = sc; 2054 iq->intr_params = V_QINTR_TIMER_IDX(tmr_idx); 2055 iq->intr_pktc_idx = SGE_NCOUNTERS - 1; 2056 if (pktc_idx >= 0) { 2057 iq->intr_params |= F_QINTR_CNT_EN; 2058 iq->intr_pktc_idx = pktc_idx; 2059 } 2060 iq->qsize = roundup2(qsize, 16); /* See FW_IQ_CMD/iqsize */ 2061 iq->esize = max(esize, 16); /* See FW_IQ_CMD/iqesize */ 2062 } 2063 2064 static inline void 2065 init_fl(struct adapter *sc, struct sge_fl *fl, int qsize, int bufsize, int pack, 2066 char *name) 2067 { 2068 2069 fl->qsize = qsize; 2070 strlcpy(fl->lockname, name, sizeof(fl->lockname)); 2071 if (pack) 2072 fl->flags |= FL_BUF_PACKING; 2073 set_fl_tag_idx(sc, fl, bufsize); 2074 } 2075 2076 static inline void 2077 init_eq(struct sge_eq *eq, int eqtype, int qsize, uint8_t tx_chan, 2078 uint16_t iqid, char *name) 2079 { 2080 KASSERT(tx_chan < NCHAN, ("%s: bad tx channel %d", __func__, tx_chan)); 2081 KASSERT(eqtype <= EQ_TYPEMASK, ("%s: bad qtype %d", __func__, eqtype)); 2082 2083 eq->flags = eqtype & EQ_TYPEMASK; 2084 eq->tx_chan = tx_chan; 2085 eq->iqid = iqid; 2086 eq->qsize = qsize; 2087 strlcpy(eq->lockname, name, sizeof(eq->lockname)); 2088 2089 TASK_INIT(&eq->tx_task, 0, t4_tx_task, eq); 2090 callout_init(&eq->tx_callout, CALLOUT_MPSAFE); 2091 } 2092 2093 static int 2094 alloc_ring(struct adapter *sc, size_t len, bus_dma_tag_t *tag, 2095 bus_dmamap_t *map, bus_addr_t *pa, void **va) 2096 { 2097 int rc; 2098 2099 rc = bus_dma_tag_create(sc->dmat, 512, 0, BUS_SPACE_MAXADDR, 2100 BUS_SPACE_MAXADDR, NULL, NULL, len, 1, len, 0, NULL, NULL, tag); 2101 if (rc != 0) { 2102 device_printf(sc->dev, "cannot allocate DMA tag: %d\n", rc); 2103 goto done; 2104 } 2105 2106 rc = bus_dmamem_alloc(*tag, va, 2107 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, map); 2108 if (rc != 0) { 2109 device_printf(sc->dev, "cannot allocate DMA memory: %d\n", rc); 2110 goto done; 2111 } 2112 2113 rc = bus_dmamap_load(*tag, *map, *va, len, oneseg_dma_callback, pa, 0); 2114 if (rc != 0) { 2115 device_printf(sc->dev, "cannot load DMA map: %d\n", rc); 2116 goto done; 2117 } 2118 done: 2119 if (rc) 2120 free_ring(sc, *tag, *map, *pa, *va); 2121 2122 return (rc); 2123 } 2124 2125 static int 2126 free_ring(struct adapter *sc, bus_dma_tag_t tag, bus_dmamap_t map, 2127 bus_addr_t pa, void *va) 2128 { 2129 if (pa) 2130 bus_dmamap_unload(tag, map); 2131 if (va) 2132 bus_dmamem_free(tag, va, map); 2133 if (tag) 2134 bus_dma_tag_destroy(tag); 2135 2136 return (0); 2137 } 2138 2139 /* 2140 * Allocates the ring for an ingress queue and an optional freelist. If the 2141 * freelist is specified it will be allocated and then associated with the 2142 * ingress queue. 2143 * 2144 * Returns errno on failure. Resources allocated up to that point may still be 2145 * allocated. Caller is responsible for cleanup in case this function fails. 2146 * 2147 * If the ingress queue will take interrupts directly (iq->flags & IQ_INTR) then 2148 * the intr_idx specifies the vector, starting from 0. Otherwise it specifies 2149 * the abs_id of the ingress queue to which its interrupts should be forwarded. 2150 */ 2151 static int 2152 alloc_iq_fl(struct port_info *pi, struct sge_iq *iq, struct sge_fl *fl, 2153 int intr_idx, int cong) 2154 { 2155 int rc, i, cntxt_id; 2156 size_t len; 2157 struct fw_iq_cmd c; 2158 struct adapter *sc = iq->adapter; 2159 __be32 v = 0; 2160 2161 len = iq->qsize * iq->esize; 2162 rc = alloc_ring(sc, len, &iq->desc_tag, &iq->desc_map, &iq->ba, 2163 (void **)&iq->desc); 2164 if (rc != 0) 2165 return (rc); 2166 2167 bzero(&c, sizeof(c)); 2168 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 2169 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) | 2170 V_FW_IQ_CMD_VFN(0)); 2171 2172 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART | 2173 FW_LEN16(c)); 2174 2175 /* Special handling for firmware event queue */ 2176 if (iq == &sc->sge.fwq) 2177 v |= F_FW_IQ_CMD_IQASYNCH; 2178 2179 if (iq->flags & IQ_INTR) { 2180 KASSERT(intr_idx < sc->intr_count, 2181 ("%s: invalid direct intr_idx %d", __func__, intr_idx)); 2182 } else 2183 v |= F_FW_IQ_CMD_IQANDST; 2184 v |= V_FW_IQ_CMD_IQANDSTINDEX(intr_idx); 2185 2186 c.type_to_iqandstindex = htobe32(v | 2187 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) | 2188 V_FW_IQ_CMD_VIID(pi->viid) | 2189 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT)); 2190 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->tx_chan) | 2191 F_FW_IQ_CMD_IQGTSMODE | 2192 V_FW_IQ_CMD_IQINTCNTTHRESH(iq->intr_pktc_idx) | 2193 V_FW_IQ_CMD_IQESIZE(ilog2(iq->esize) - 4)); 2194 c.iqsize = htobe16(iq->qsize); 2195 c.iqaddr = htobe64(iq->ba); 2196 if (cong >= 0) 2197 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN); 2198 2199 if (fl) { 2200 mtx_init(&fl->fl_lock, fl->lockname, NULL, MTX_DEF); 2201 2202 for (i = 0; i < FL_BUF_SIZES(sc); i++) { 2203 2204 /* 2205 * A freelist buffer must be 16 byte aligned as the SGE 2206 * uses the low 4 bits of the bus addr to figure out the 2207 * buffer size. 2208 */ 2209 rc = bus_dma_tag_create(sc->dmat, 16, 0, 2210 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 2211 FL_BUF_SIZE(sc, i), 1, FL_BUF_SIZE(sc, i), 2212 BUS_DMA_ALLOCNOW, NULL, NULL, &fl->tag[i]); 2213 if (rc != 0) { 2214 device_printf(sc->dev, 2215 "failed to create fl DMA tag[%d]: %d\n", 2216 i, rc); 2217 return (rc); 2218 } 2219 } 2220 len = fl->qsize * RX_FL_ESIZE; 2221 rc = alloc_ring(sc, len, &fl->desc_tag, &fl->desc_map, 2222 &fl->ba, (void **)&fl->desc); 2223 if (rc) 2224 return (rc); 2225 2226 /* Allocate space for one software descriptor per buffer. */ 2227 fl->cap = (fl->qsize - spg_len / RX_FL_ESIZE) * 8; 2228 rc = alloc_fl_sdesc(fl); 2229 if (rc != 0) { 2230 device_printf(sc->dev, 2231 "failed to setup fl software descriptors: %d\n", 2232 rc); 2233 return (rc); 2234 } 2235 fl->needed = fl->cap; 2236 fl->lowat = roundup2(sc->sge.fl_starve_threshold, 8); 2237 2238 c.iqns_to_fl0congen |= 2239 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) | 2240 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO | 2241 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) | 2242 (fl->flags & FL_BUF_PACKING ? F_FW_IQ_CMD_FL0PACKEN : 2243 0)); 2244 if (cong >= 0) { 2245 c.iqns_to_fl0congen |= 2246 htobe32(V_FW_IQ_CMD_FL0CNGCHMAP(cong) | 2247 F_FW_IQ_CMD_FL0CONGCIF | 2248 F_FW_IQ_CMD_FL0CONGEN); 2249 } 2250 c.fl0dcaen_to_fl0cidxfthresh = 2251 htobe16(V_FW_IQ_CMD_FL0FBMIN(X_FETCHBURSTMIN_64B) | 2252 V_FW_IQ_CMD_FL0FBMAX(X_FETCHBURSTMAX_512B)); 2253 c.fl0size = htobe16(fl->qsize); 2254 c.fl0addr = htobe64(fl->ba); 2255 } 2256 2257 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 2258 if (rc != 0) { 2259 device_printf(sc->dev, 2260 "failed to create ingress queue: %d\n", rc); 2261 return (rc); 2262 } 2263 2264 iq->cdesc = iq->desc; 2265 iq->cidx = 0; 2266 iq->gen = 1; 2267 iq->intr_next = iq->intr_params; 2268 iq->cntxt_id = be16toh(c.iqid); 2269 iq->abs_id = be16toh(c.physiqid); 2270 iq->flags |= IQ_ALLOCATED; 2271 2272 cntxt_id = iq->cntxt_id - sc->sge.iq_start; 2273 if (cntxt_id >= sc->sge.niq) { 2274 panic ("%s: iq->cntxt_id (%d) more than the max (%d)", __func__, 2275 cntxt_id, sc->sge.niq - 1); 2276 } 2277 sc->sge.iqmap[cntxt_id] = iq; 2278 2279 if (fl) { 2280 fl->cntxt_id = be16toh(c.fl0id); 2281 fl->pidx = fl->cidx = 0; 2282 2283 cntxt_id = fl->cntxt_id - sc->sge.eq_start; 2284 if (cntxt_id >= sc->sge.neq) { 2285 panic("%s: fl->cntxt_id (%d) more than the max (%d)", 2286 __func__, cntxt_id, sc->sge.neq - 1); 2287 } 2288 sc->sge.eqmap[cntxt_id] = (void *)fl; 2289 2290 FL_LOCK(fl); 2291 /* Enough to make sure the SGE doesn't think it's starved */ 2292 refill_fl(sc, fl, fl->lowat); 2293 FL_UNLOCK(fl); 2294 2295 iq->flags |= IQ_HAS_FL; 2296 } 2297 2298 if (is_t5(sc) && cong >= 0) { 2299 uint32_t param, val; 2300 2301 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 2302 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) | 2303 V_FW_PARAMS_PARAM_YZ(iq->cntxt_id); 2304 if (cong == 0) 2305 val = 1 << 19; 2306 else { 2307 val = 2 << 19; 2308 for (i = 0; i < 4; i++) { 2309 if (cong & (1 << i)) 2310 val |= 1 << (i << 2); 2311 } 2312 } 2313 2314 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 2315 if (rc != 0) { 2316 /* report error but carry on */ 2317 device_printf(sc->dev, 2318 "failed to set congestion manager context for " 2319 "ingress queue %d: %d\n", iq->cntxt_id, rc); 2320 } 2321 } 2322 2323 /* Enable IQ interrupts */ 2324 atomic_store_rel_int(&iq->state, IQS_IDLE); 2325 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), V_SEINTARM(iq->intr_params) | 2326 V_INGRESSQID(iq->cntxt_id)); 2327 2328 return (0); 2329 } 2330 2331 static int 2332 free_iq_fl(struct port_info *pi, struct sge_iq *iq, struct sge_fl *fl) 2333 { 2334 int i, rc; 2335 struct adapter *sc = iq->adapter; 2336 device_t dev; 2337 2338 if (sc == NULL) 2339 return (0); /* nothing to do */ 2340 2341 dev = pi ? pi->dev : sc->dev; 2342 2343 if (iq->flags & IQ_ALLOCATED) { 2344 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0, 2345 FW_IQ_TYPE_FL_INT_CAP, iq->cntxt_id, 2346 fl ? fl->cntxt_id : 0xffff, 0xffff); 2347 if (rc != 0) { 2348 device_printf(dev, 2349 "failed to free queue %p: %d\n", iq, rc); 2350 return (rc); 2351 } 2352 iq->flags &= ~IQ_ALLOCATED; 2353 } 2354 2355 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, iq->desc); 2356 2357 bzero(iq, sizeof(*iq)); 2358 2359 if (fl) { 2360 free_ring(sc, fl->desc_tag, fl->desc_map, fl->ba, 2361 fl->desc); 2362 2363 if (fl->sdesc) 2364 free_fl_sdesc(sc, fl); 2365 2366 for (i = 0; i < nitems(fl->mstash); i++) { 2367 struct mbuf *m = fl->mstash[i]; 2368 2369 if (m != NULL) { 2370 m_init(m, NULL, 0, M_NOWAIT, MT_DATA, 0); 2371 m_free(m); 2372 } 2373 } 2374 2375 if (mtx_initialized(&fl->fl_lock)) 2376 mtx_destroy(&fl->fl_lock); 2377 2378 for (i = 0; i < FL_BUF_SIZES(sc); i++) { 2379 if (fl->tag[i]) 2380 bus_dma_tag_destroy(fl->tag[i]); 2381 } 2382 2383 bzero(fl, sizeof(*fl)); 2384 } 2385 2386 return (0); 2387 } 2388 2389 static int 2390 alloc_fwq(struct adapter *sc) 2391 { 2392 int rc, intr_idx; 2393 struct sge_iq *fwq = &sc->sge.fwq; 2394 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev); 2395 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 2396 2397 init_iq(fwq, sc, 0, 0, FW_IQ_QSIZE, FW_IQ_ESIZE); 2398 fwq->flags |= IQ_INTR; /* always */ 2399 intr_idx = sc->intr_count > 1 ? 1 : 0; 2400 rc = alloc_iq_fl(sc->port[0], fwq, NULL, intr_idx, -1); 2401 if (rc != 0) { 2402 device_printf(sc->dev, 2403 "failed to create firmware event queue: %d\n", rc); 2404 return (rc); 2405 } 2406 2407 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "fwq", CTLFLAG_RD, 2408 NULL, "firmware event queue"); 2409 children = SYSCTL_CHILDREN(oid); 2410 2411 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "abs_id", 2412 CTLTYPE_INT | CTLFLAG_RD, &fwq->abs_id, 0, sysctl_uint16, "I", 2413 "absolute id of the queue"); 2414 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "cntxt_id", 2415 CTLTYPE_INT | CTLFLAG_RD, &fwq->cntxt_id, 0, sysctl_uint16, "I", 2416 "SGE context id of the queue"); 2417 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "cidx", 2418 CTLTYPE_INT | CTLFLAG_RD, &fwq->cidx, 0, sysctl_uint16, "I", 2419 "consumer index"); 2420 2421 return (0); 2422 } 2423 2424 static int 2425 free_fwq(struct adapter *sc) 2426 { 2427 return free_iq_fl(NULL, &sc->sge.fwq, NULL); 2428 } 2429 2430 static int 2431 alloc_mgmtq(struct adapter *sc) 2432 { 2433 int rc; 2434 struct sge_wrq *mgmtq = &sc->sge.mgmtq; 2435 char name[16]; 2436 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev); 2437 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 2438 2439 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "mgmtq", CTLFLAG_RD, 2440 NULL, "management queue"); 2441 2442 snprintf(name, sizeof(name), "%s mgmtq", device_get_nameunit(sc->dev)); 2443 init_eq(&mgmtq->eq, EQ_CTRL, CTRL_EQ_QSIZE, sc->port[0]->tx_chan, 2444 sc->sge.fwq.cntxt_id, name); 2445 rc = alloc_wrq(sc, NULL, mgmtq, oid); 2446 if (rc != 0) { 2447 device_printf(sc->dev, 2448 "failed to create management queue: %d\n", rc); 2449 return (rc); 2450 } 2451 2452 return (0); 2453 } 2454 2455 static int 2456 free_mgmtq(struct adapter *sc) 2457 { 2458 2459 return free_wrq(sc, &sc->sge.mgmtq); 2460 } 2461 2462 static inline int 2463 tnl_cong(struct port_info *pi) 2464 { 2465 2466 if (cong_drop == -1) 2467 return (-1); 2468 else if (cong_drop == 1) 2469 return (0); 2470 else 2471 return (1 << pi->tx_chan); 2472 } 2473 2474 static int 2475 alloc_rxq(struct port_info *pi, struct sge_rxq *rxq, int intr_idx, int idx, 2476 struct sysctl_oid *oid) 2477 { 2478 int rc; 2479 struct sysctl_oid_list *children; 2480 char name[16]; 2481 2482 rc = alloc_iq_fl(pi, &rxq->iq, &rxq->fl, intr_idx, tnl_cong(pi)); 2483 if (rc != 0) 2484 return (rc); 2485 2486 FL_LOCK(&rxq->fl); 2487 refill_fl(pi->adapter, &rxq->fl, rxq->fl.needed / 8); 2488 FL_UNLOCK(&rxq->fl); 2489 2490 #if defined(INET) || defined(INET6) 2491 rc = tcp_lro_init(&rxq->lro); 2492 if (rc != 0) 2493 return (rc); 2494 rxq->lro.ifp = pi->ifp; /* also indicates LRO init'ed */ 2495 2496 if (pi->ifp->if_capenable & IFCAP_LRO) 2497 rxq->iq.flags |= IQ_LRO_ENABLED; 2498 #endif 2499 rxq->ifp = pi->ifp; 2500 2501 children = SYSCTL_CHILDREN(oid); 2502 2503 snprintf(name, sizeof(name), "%d", idx); 2504 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 2505 NULL, "rx queue"); 2506 children = SYSCTL_CHILDREN(oid); 2507 2508 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "abs_id", 2509 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.abs_id, 0, sysctl_uint16, "I", 2510 "absolute id of the queue"); 2511 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cntxt_id", 2512 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.cntxt_id, 0, sysctl_uint16, "I", 2513 "SGE context id of the queue"); 2514 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cidx", 2515 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.cidx, 0, sysctl_uint16, "I", 2516 "consumer index"); 2517 #if defined(INET) || defined(INET6) 2518 SYSCTL_ADD_INT(&pi->ctx, children, OID_AUTO, "lro_queued", CTLFLAG_RD, 2519 &rxq->lro.lro_queued, 0, NULL); 2520 SYSCTL_ADD_INT(&pi->ctx, children, OID_AUTO, "lro_flushed", CTLFLAG_RD, 2521 &rxq->lro.lro_flushed, 0, NULL); 2522 #endif 2523 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "rxcsum", CTLFLAG_RD, 2524 &rxq->rxcsum, "# of times hardware assisted with checksum"); 2525 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "vlan_extraction", 2526 CTLFLAG_RD, &rxq->vlan_extraction, 2527 "# of times hardware extracted 802.1Q tag"); 2528 2529 children = SYSCTL_CHILDREN(oid); 2530 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "fl", CTLFLAG_RD, 2531 NULL, "freelist"); 2532 children = SYSCTL_CHILDREN(oid); 2533 2534 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cntxt_id", 2535 CTLTYPE_INT | CTLFLAG_RD, &rxq->fl.cntxt_id, 0, sysctl_uint16, "I", 2536 "SGE context id of the queue"); 2537 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, 2538 &rxq->fl.cidx, 0, "consumer index"); 2539 if (rxq->fl.flags & FL_BUF_PACKING) { 2540 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "rx_offset", 2541 CTLFLAG_RD, &rxq->fl.rx_offset, 0, "packing rx offset"); 2542 } 2543 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, 2544 &rxq->fl.pidx, 0, "producer index"); 2545 2546 return (rc); 2547 } 2548 2549 static int 2550 free_rxq(struct port_info *pi, struct sge_rxq *rxq) 2551 { 2552 int rc; 2553 2554 #if defined(INET) || defined(INET6) 2555 if (rxq->lro.ifp) { 2556 tcp_lro_free(&rxq->lro); 2557 rxq->lro.ifp = NULL; 2558 } 2559 #endif 2560 2561 rc = free_iq_fl(pi, &rxq->iq, &rxq->fl); 2562 if (rc == 0) 2563 bzero(rxq, sizeof(*rxq)); 2564 2565 return (rc); 2566 } 2567 2568 #ifdef TCP_OFFLOAD 2569 static int 2570 alloc_ofld_rxq(struct port_info *pi, struct sge_ofld_rxq *ofld_rxq, 2571 int intr_idx, int idx, struct sysctl_oid *oid) 2572 { 2573 int rc; 2574 struct sysctl_oid_list *children; 2575 char name[16]; 2576 2577 rc = alloc_iq_fl(pi, &ofld_rxq->iq, &ofld_rxq->fl, intr_idx, 2578 1 << pi->tx_chan); 2579 if (rc != 0) 2580 return (rc); 2581 2582 children = SYSCTL_CHILDREN(oid); 2583 2584 snprintf(name, sizeof(name), "%d", idx); 2585 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 2586 NULL, "rx queue"); 2587 children = SYSCTL_CHILDREN(oid); 2588 2589 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "abs_id", 2590 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.abs_id, 0, sysctl_uint16, 2591 "I", "absolute id of the queue"); 2592 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cntxt_id", 2593 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.cntxt_id, 0, sysctl_uint16, 2594 "I", "SGE context id of the queue"); 2595 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cidx", 2596 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.cidx, 0, sysctl_uint16, "I", 2597 "consumer index"); 2598 2599 children = SYSCTL_CHILDREN(oid); 2600 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "fl", CTLFLAG_RD, 2601 NULL, "freelist"); 2602 children = SYSCTL_CHILDREN(oid); 2603 2604 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cntxt_id", 2605 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->fl.cntxt_id, 0, sysctl_uint16, 2606 "I", "SGE context id of the queue"); 2607 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, 2608 &ofld_rxq->fl.cidx, 0, "consumer index"); 2609 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, 2610 &ofld_rxq->fl.pidx, 0, "producer index"); 2611 2612 return (rc); 2613 } 2614 2615 static int 2616 free_ofld_rxq(struct port_info *pi, struct sge_ofld_rxq *ofld_rxq) 2617 { 2618 int rc; 2619 2620 rc = free_iq_fl(pi, &ofld_rxq->iq, &ofld_rxq->fl); 2621 if (rc == 0) 2622 bzero(ofld_rxq, sizeof(*ofld_rxq)); 2623 2624 return (rc); 2625 } 2626 #endif 2627 2628 static int 2629 ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq) 2630 { 2631 int rc, cntxt_id; 2632 struct fw_eq_ctrl_cmd c; 2633 2634 bzero(&c, sizeof(c)); 2635 2636 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | F_FW_CMD_REQUEST | 2637 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_CTRL_CMD_PFN(sc->pf) | 2638 V_FW_EQ_CTRL_CMD_VFN(0)); 2639 c.alloc_to_len16 = htobe32(F_FW_EQ_CTRL_CMD_ALLOC | 2640 F_FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c)); 2641 c.cmpliqid_eqid = htonl(V_FW_EQ_CTRL_CMD_CMPLIQID(eq->iqid)); /* XXX */ 2642 c.physeqid_pkd = htobe32(0); 2643 c.fetchszm_to_iqid = 2644 htobe32(V_FW_EQ_CTRL_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 2645 V_FW_EQ_CTRL_CMD_PCIECHN(eq->tx_chan) | 2646 F_FW_EQ_CTRL_CMD_FETCHRO | V_FW_EQ_CTRL_CMD_IQID(eq->iqid)); 2647 c.dcaen_to_eqsize = 2648 htobe32(V_FW_EQ_CTRL_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 2649 V_FW_EQ_CTRL_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 2650 V_FW_EQ_CTRL_CMD_CIDXFTHRESH(X_CIDXFLUSHTHRESH_32) | 2651 V_FW_EQ_CTRL_CMD_EQSIZE(eq->qsize)); 2652 c.eqaddr = htobe64(eq->ba); 2653 2654 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 2655 if (rc != 0) { 2656 device_printf(sc->dev, 2657 "failed to create control queue %d: %d\n", eq->tx_chan, rc); 2658 return (rc); 2659 } 2660 eq->flags |= EQ_ALLOCATED; 2661 2662 eq->cntxt_id = G_FW_EQ_CTRL_CMD_EQID(be32toh(c.cmpliqid_eqid)); 2663 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 2664 if (cntxt_id >= sc->sge.neq) 2665 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 2666 cntxt_id, sc->sge.neq - 1); 2667 sc->sge.eqmap[cntxt_id] = eq; 2668 2669 return (rc); 2670 } 2671 2672 static int 2673 eth_eq_alloc(struct adapter *sc, struct port_info *pi, struct sge_eq *eq) 2674 { 2675 int rc, cntxt_id; 2676 struct fw_eq_eth_cmd c; 2677 2678 bzero(&c, sizeof(c)); 2679 2680 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST | 2681 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) | 2682 V_FW_EQ_ETH_CMD_VFN(0)); 2683 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC | 2684 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c)); 2685 c.viid_pkd = htobe32(V_FW_EQ_ETH_CMD_VIID(pi->viid)); 2686 c.fetchszm_to_iqid = 2687 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 2688 V_FW_EQ_ETH_CMD_PCIECHN(eq->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO | 2689 V_FW_EQ_ETH_CMD_IQID(eq->iqid)); 2690 c.dcaen_to_eqsize = htobe32(V_FW_EQ_ETH_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 2691 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 2692 V_FW_EQ_ETH_CMD_CIDXFTHRESH(X_CIDXFLUSHTHRESH_32) | 2693 V_FW_EQ_ETH_CMD_EQSIZE(eq->qsize)); 2694 c.eqaddr = htobe64(eq->ba); 2695 2696 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 2697 if (rc != 0) { 2698 device_printf(pi->dev, 2699 "failed to create Ethernet egress queue: %d\n", rc); 2700 return (rc); 2701 } 2702 eq->flags |= EQ_ALLOCATED; 2703 2704 eq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd)); 2705 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 2706 if (cntxt_id >= sc->sge.neq) 2707 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 2708 cntxt_id, sc->sge.neq - 1); 2709 sc->sge.eqmap[cntxt_id] = eq; 2710 2711 return (rc); 2712 } 2713 2714 #ifdef TCP_OFFLOAD 2715 static int 2716 ofld_eq_alloc(struct adapter *sc, struct port_info *pi, struct sge_eq *eq) 2717 { 2718 int rc, cntxt_id; 2719 struct fw_eq_ofld_cmd c; 2720 2721 bzero(&c, sizeof(c)); 2722 2723 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | F_FW_CMD_REQUEST | 2724 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_OFLD_CMD_PFN(sc->pf) | 2725 V_FW_EQ_OFLD_CMD_VFN(0)); 2726 c.alloc_to_len16 = htonl(F_FW_EQ_OFLD_CMD_ALLOC | 2727 F_FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c)); 2728 c.fetchszm_to_iqid = 2729 htonl(V_FW_EQ_OFLD_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 2730 V_FW_EQ_OFLD_CMD_PCIECHN(eq->tx_chan) | 2731 F_FW_EQ_OFLD_CMD_FETCHRO | V_FW_EQ_OFLD_CMD_IQID(eq->iqid)); 2732 c.dcaen_to_eqsize = 2733 htobe32(V_FW_EQ_OFLD_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 2734 V_FW_EQ_OFLD_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 2735 V_FW_EQ_OFLD_CMD_CIDXFTHRESH(X_CIDXFLUSHTHRESH_32) | 2736 V_FW_EQ_OFLD_CMD_EQSIZE(eq->qsize)); 2737 c.eqaddr = htobe64(eq->ba); 2738 2739 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 2740 if (rc != 0) { 2741 device_printf(pi->dev, 2742 "failed to create egress queue for TCP offload: %d\n", rc); 2743 return (rc); 2744 } 2745 eq->flags |= EQ_ALLOCATED; 2746 2747 eq->cntxt_id = G_FW_EQ_OFLD_CMD_EQID(be32toh(c.eqid_pkd)); 2748 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 2749 if (cntxt_id >= sc->sge.neq) 2750 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 2751 cntxt_id, sc->sge.neq - 1); 2752 sc->sge.eqmap[cntxt_id] = eq; 2753 2754 return (rc); 2755 } 2756 #endif 2757 2758 static int 2759 alloc_eq(struct adapter *sc, struct port_info *pi, struct sge_eq *eq) 2760 { 2761 int rc; 2762 size_t len; 2763 2764 mtx_init(&eq->eq_lock, eq->lockname, NULL, MTX_DEF); 2765 2766 len = eq->qsize * EQ_ESIZE; 2767 rc = alloc_ring(sc, len, &eq->desc_tag, &eq->desc_map, 2768 &eq->ba, (void **)&eq->desc); 2769 if (rc) 2770 return (rc); 2771 2772 eq->cap = eq->qsize - spg_len / EQ_ESIZE; 2773 eq->spg = (void *)&eq->desc[eq->cap]; 2774 eq->avail = eq->cap - 1; /* one less to avoid cidx = pidx */ 2775 eq->pidx = eq->cidx = 0; 2776 eq->doorbells = sc->doorbells; 2777 2778 switch (eq->flags & EQ_TYPEMASK) { 2779 case EQ_CTRL: 2780 rc = ctrl_eq_alloc(sc, eq); 2781 break; 2782 2783 case EQ_ETH: 2784 rc = eth_eq_alloc(sc, pi, eq); 2785 break; 2786 2787 #ifdef TCP_OFFLOAD 2788 case EQ_OFLD: 2789 rc = ofld_eq_alloc(sc, pi, eq); 2790 break; 2791 #endif 2792 2793 default: 2794 panic("%s: invalid eq type %d.", __func__, 2795 eq->flags & EQ_TYPEMASK); 2796 } 2797 if (rc != 0) { 2798 device_printf(sc->dev, 2799 "failed to allocate egress queue(%d): %d", 2800 eq->flags & EQ_TYPEMASK, rc); 2801 } 2802 2803 eq->tx_callout.c_cpu = eq->cntxt_id % mp_ncpus; 2804 2805 if (isset(&eq->doorbells, DOORBELL_UDB) || 2806 isset(&eq->doorbells, DOORBELL_UDBWC) || 2807 isset(&eq->doorbells, DOORBELL_WCWR)) { 2808 uint32_t s_qpp = sc->sge.eq_s_qpp; 2809 uint32_t mask = (1 << s_qpp) - 1; 2810 volatile uint8_t *udb; 2811 2812 udb = sc->udbs_base + UDBS_DB_OFFSET; 2813 udb += (eq->cntxt_id >> s_qpp) << PAGE_SHIFT; /* pg offset */ 2814 eq->udb_qid = eq->cntxt_id & mask; /* id in page */ 2815 if (eq->udb_qid > PAGE_SIZE / UDBS_SEG_SIZE) 2816 clrbit(&eq->doorbells, DOORBELL_WCWR); 2817 else { 2818 udb += eq->udb_qid << UDBS_SEG_SHIFT; /* seg offset */ 2819 eq->udb_qid = 0; 2820 } 2821 eq->udb = (volatile void *)udb; 2822 } 2823 2824 return (rc); 2825 } 2826 2827 static int 2828 free_eq(struct adapter *sc, struct sge_eq *eq) 2829 { 2830 int rc; 2831 2832 if (eq->flags & EQ_ALLOCATED) { 2833 switch (eq->flags & EQ_TYPEMASK) { 2834 case EQ_CTRL: 2835 rc = -t4_ctrl_eq_free(sc, sc->mbox, sc->pf, 0, 2836 eq->cntxt_id); 2837 break; 2838 2839 case EQ_ETH: 2840 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0, 2841 eq->cntxt_id); 2842 break; 2843 2844 #ifdef TCP_OFFLOAD 2845 case EQ_OFLD: 2846 rc = -t4_ofld_eq_free(sc, sc->mbox, sc->pf, 0, 2847 eq->cntxt_id); 2848 break; 2849 #endif 2850 2851 default: 2852 panic("%s: invalid eq type %d.", __func__, 2853 eq->flags & EQ_TYPEMASK); 2854 } 2855 if (rc != 0) { 2856 device_printf(sc->dev, 2857 "failed to free egress queue (%d): %d\n", 2858 eq->flags & EQ_TYPEMASK, rc); 2859 return (rc); 2860 } 2861 eq->flags &= ~EQ_ALLOCATED; 2862 } 2863 2864 free_ring(sc, eq->desc_tag, eq->desc_map, eq->ba, eq->desc); 2865 2866 if (mtx_initialized(&eq->eq_lock)) 2867 mtx_destroy(&eq->eq_lock); 2868 2869 bzero(eq, sizeof(*eq)); 2870 return (0); 2871 } 2872 2873 static int 2874 alloc_wrq(struct adapter *sc, struct port_info *pi, struct sge_wrq *wrq, 2875 struct sysctl_oid *oid) 2876 { 2877 int rc; 2878 struct sysctl_ctx_list *ctx = pi ? &pi->ctx : &sc->ctx; 2879 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 2880 2881 rc = alloc_eq(sc, pi, &wrq->eq); 2882 if (rc) 2883 return (rc); 2884 2885 wrq->adapter = sc; 2886 STAILQ_INIT(&wrq->wr_list); 2887 2888 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 2889 &wrq->eq.cntxt_id, 0, "SGE context id of the queue"); 2890 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx", 2891 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.cidx, 0, sysctl_uint16, "I", 2892 "consumer index"); 2893 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pidx", 2894 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.pidx, 0, sysctl_uint16, "I", 2895 "producer index"); 2896 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs", CTLFLAG_RD, 2897 &wrq->tx_wrs, "# of work requests"); 2898 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "no_desc", CTLFLAG_RD, 2899 &wrq->no_desc, 0, 2900 "# of times queue ran out of hardware descriptors"); 2901 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "unstalled", CTLFLAG_RD, 2902 &wrq->eq.unstalled, 0, "# of times queue recovered after stall"); 2903 2904 2905 return (rc); 2906 } 2907 2908 static int 2909 free_wrq(struct adapter *sc, struct sge_wrq *wrq) 2910 { 2911 int rc; 2912 2913 rc = free_eq(sc, &wrq->eq); 2914 if (rc) 2915 return (rc); 2916 2917 bzero(wrq, sizeof(*wrq)); 2918 return (0); 2919 } 2920 2921 static int 2922 alloc_txq(struct port_info *pi, struct sge_txq *txq, int idx, 2923 struct sysctl_oid *oid) 2924 { 2925 int rc; 2926 struct adapter *sc = pi->adapter; 2927 struct sge_eq *eq = &txq->eq; 2928 char name[16]; 2929 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 2930 2931 rc = alloc_eq(sc, pi, eq); 2932 if (rc) 2933 return (rc); 2934 2935 txq->ifp = pi->ifp; 2936 2937 txq->sdesc = malloc(eq->cap * sizeof(struct tx_sdesc), M_CXGBE, 2938 M_ZERO | M_WAITOK); 2939 txq->br = buf_ring_alloc(eq->qsize, M_CXGBE, M_WAITOK, &eq->eq_lock); 2940 2941 rc = bus_dma_tag_create(sc->dmat, 1, 0, BUS_SPACE_MAXADDR, 2942 BUS_SPACE_MAXADDR, NULL, NULL, 64 * 1024, TX_SGL_SEGS, 2943 BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL, NULL, &txq->tx_tag); 2944 if (rc != 0) { 2945 device_printf(sc->dev, 2946 "failed to create tx DMA tag: %d\n", rc); 2947 return (rc); 2948 } 2949 2950 /* 2951 * We can stuff ~10 frames in an 8-descriptor txpkts WR (8 is the SGE 2952 * limit for any WR). txq->no_dmamap events shouldn't occur if maps is 2953 * sized for the worst case. 2954 */ 2955 rc = t4_alloc_tx_maps(&txq->txmaps, txq->tx_tag, eq->qsize * 10 / 8, 2956 M_WAITOK); 2957 if (rc != 0) { 2958 device_printf(sc->dev, "failed to setup tx DMA maps: %d\n", rc); 2959 return (rc); 2960 } 2961 2962 snprintf(name, sizeof(name), "%d", idx); 2963 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 2964 NULL, "tx queue"); 2965 children = SYSCTL_CHILDREN(oid); 2966 2967 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 2968 &eq->cntxt_id, 0, "SGE context id of the queue"); 2969 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cidx", 2970 CTLTYPE_INT | CTLFLAG_RD, &eq->cidx, 0, sysctl_uint16, "I", 2971 "consumer index"); 2972 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "pidx", 2973 CTLTYPE_INT | CTLFLAG_RD, &eq->pidx, 0, sysctl_uint16, "I", 2974 "producer index"); 2975 2976 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "txcsum", CTLFLAG_RD, 2977 &txq->txcsum, "# of times hardware assisted with checksum"); 2978 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "vlan_insertion", 2979 CTLFLAG_RD, &txq->vlan_insertion, 2980 "# of times hardware inserted 802.1Q tag"); 2981 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "tso_wrs", CTLFLAG_RD, 2982 &txq->tso_wrs, "# of TSO work requests"); 2983 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "imm_wrs", CTLFLAG_RD, 2984 &txq->imm_wrs, "# of work requests with immediate data"); 2985 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "sgl_wrs", CTLFLAG_RD, 2986 &txq->sgl_wrs, "# of work requests with direct SGL"); 2987 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "txpkt_wrs", CTLFLAG_RD, 2988 &txq->txpkt_wrs, "# of txpkt work requests (one pkt/WR)"); 2989 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "txpkts_wrs", CTLFLAG_RD, 2990 &txq->txpkts_wrs, "# of txpkts work requests (multiple pkts/WR)"); 2991 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "txpkts_pkts", CTLFLAG_RD, 2992 &txq->txpkts_pkts, "# of frames tx'd using txpkts work requests"); 2993 2994 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "br_drops", CTLFLAG_RD, 2995 &txq->br->br_drops, "# of drops in the buf_ring for this queue"); 2996 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "no_dmamap", CTLFLAG_RD, 2997 &txq->no_dmamap, 0, "# of times txq ran out of DMA maps"); 2998 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "no_desc", CTLFLAG_RD, 2999 &txq->no_desc, 0, "# of times txq ran out of hardware descriptors"); 3000 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "egr_update", CTLFLAG_RD, 3001 &eq->egr_update, 0, "egress update notifications from the SGE"); 3002 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "unstalled", CTLFLAG_RD, 3003 &eq->unstalled, 0, "# of times txq recovered after stall"); 3004 3005 return (rc); 3006 } 3007 3008 static int 3009 free_txq(struct port_info *pi, struct sge_txq *txq) 3010 { 3011 int rc; 3012 struct adapter *sc = pi->adapter; 3013 struct sge_eq *eq = &txq->eq; 3014 3015 rc = free_eq(sc, eq); 3016 if (rc) 3017 return (rc); 3018 3019 free(txq->sdesc, M_CXGBE); 3020 3021 if (txq->txmaps.maps) 3022 t4_free_tx_maps(&txq->txmaps, txq->tx_tag); 3023 3024 buf_ring_free(txq->br, M_CXGBE); 3025 3026 if (txq->tx_tag) 3027 bus_dma_tag_destroy(txq->tx_tag); 3028 3029 bzero(txq, sizeof(*txq)); 3030 return (0); 3031 } 3032 3033 static void 3034 oneseg_dma_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3035 { 3036 bus_addr_t *ba = arg; 3037 3038 KASSERT(nseg == 1, 3039 ("%s meant for single segment mappings only.", __func__)); 3040 3041 *ba = error ? 0 : segs->ds_addr; 3042 } 3043 3044 static inline bool 3045 is_new_response(const struct sge_iq *iq, struct rsp_ctrl **ctrl) 3046 { 3047 *ctrl = (void *)((uintptr_t)iq->cdesc + 3048 (iq->esize - sizeof(struct rsp_ctrl))); 3049 3050 return (((*ctrl)->u.type_gen >> S_RSPD_GEN) == iq->gen); 3051 } 3052 3053 static inline void 3054 iq_next(struct sge_iq *iq) 3055 { 3056 iq->cdesc = (void *) ((uintptr_t)iq->cdesc + iq->esize); 3057 if (__predict_false(++iq->cidx == iq->qsize - 1)) { 3058 iq->cidx = 0; 3059 iq->gen ^= 1; 3060 iq->cdesc = iq->desc; 3061 } 3062 } 3063 3064 #define FL_HW_IDX(x) ((x) >> 3) 3065 static inline void 3066 ring_fl_db(struct adapter *sc, struct sge_fl *fl) 3067 { 3068 int ndesc = fl->pending / 8; 3069 uint32_t v; 3070 3071 if (FL_HW_IDX(fl->pidx) == FL_HW_IDX(fl->cidx)) 3072 ndesc--; /* hold back one credit */ 3073 3074 if (ndesc <= 0) 3075 return; /* nothing to do */ 3076 3077 v = F_DBPRIO | V_QID(fl->cntxt_id) | V_PIDX(ndesc); 3078 if (is_t5(sc)) 3079 v |= F_DBTYPE; 3080 3081 wmb(); 3082 3083 t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL), v); 3084 fl->pending -= ndesc * 8; 3085 } 3086 3087 /* 3088 * Fill up the freelist by upto nbufs and maybe ring its doorbell. 3089 * 3090 * Returns non-zero to indicate that it should be added to the list of starving 3091 * freelists. 3092 */ 3093 static int 3094 refill_fl(struct adapter *sc, struct sge_fl *fl, int nbufs) 3095 { 3096 __be64 *d = &fl->desc[fl->pidx]; 3097 struct fl_sdesc *sd = &fl->sdesc[fl->pidx]; 3098 bus_dma_tag_t tag; 3099 bus_addr_t pa; 3100 caddr_t cl; 3101 int rc; 3102 3103 FL_LOCK_ASSERT_OWNED(fl); 3104 #ifdef INVARIANTS 3105 if (fl->flags & FL_BUF_PACKING) 3106 KASSERT(sd->tag_idx == 0, 3107 ("%s: expected tag 0 but found tag %d at pidx %u instead", 3108 __func__, sd->tag_idx, fl->pidx)); 3109 #endif 3110 3111 if (nbufs > fl->needed) 3112 nbufs = fl->needed; 3113 3114 while (nbufs--) { 3115 3116 if (sd->cl != NULL) { 3117 3118 KASSERT(*d == sd->ba_hwtag, 3119 ("%s: recyling problem at pidx %d", 3120 __func__, fl->pidx)); 3121 3122 if (fl->flags & FL_BUF_PACKING) { 3123 u_int *refcount = find_buf_refcnt(sd->cl); 3124 3125 if (atomic_fetchadd_int(refcount, -1) == 1) { 3126 *refcount = 1; /* reinstate */ 3127 d++; 3128 goto recycled; 3129 } 3130 sd->cl = NULL; /* gave up my reference */ 3131 } else { 3132 /* 3133 * This happens when a frame small enough to fit 3134 * entirely in an mbuf was received in cl last 3135 * time. We'd held on to cl and can reuse it 3136 * now. Note that we reuse a cluster of the old 3137 * size if fl->tag_idx is no longer the same as 3138 * sd->tag_idx. 3139 */ 3140 d++; 3141 goto recycled; 3142 } 3143 } 3144 3145 if (__predict_false(fl->tag_idx != sd->tag_idx)) { 3146 bus_dmamap_t map; 3147 bus_dma_tag_t newtag = fl->tag[fl->tag_idx]; 3148 bus_dma_tag_t oldtag = fl->tag[sd->tag_idx]; 3149 3150 /* 3151 * An MTU change can get us here. Discard the old map 3152 * which was created with the old tag, but only if 3153 * we're able to get a new one. 3154 */ 3155 rc = bus_dmamap_create(newtag, 0, &map); 3156 if (rc == 0) { 3157 bus_dmamap_destroy(oldtag, sd->map); 3158 sd->map = map; 3159 sd->tag_idx = fl->tag_idx; 3160 } 3161 } 3162 3163 tag = fl->tag[sd->tag_idx]; 3164 3165 cl = uma_zalloc(FL_BUF_ZONE(sc, sd->tag_idx), M_NOWAIT); 3166 if (cl == NULL) 3167 break; 3168 if (fl->flags & FL_BUF_PACKING) { 3169 *find_buf_refcnt(cl) = 1; 3170 cl += MSIZE; 3171 } 3172 3173 rc = bus_dmamap_load(tag, sd->map, cl, 3174 FL_BUF_SIZE(sc, sd->tag_idx), oneseg_dma_callback, &pa, 0); 3175 if (rc != 0 || pa == 0) { 3176 fl->dmamap_failed++; 3177 if (fl->flags & FL_BUF_PACKING) 3178 cl -= MSIZE; 3179 uma_zfree(FL_BUF_ZONE(sc, sd->tag_idx), cl); 3180 break; 3181 } 3182 3183 sd->cl = cl; 3184 *d++ = htobe64(pa | FL_BUF_HWTAG(sc, sd->tag_idx)); 3185 3186 #ifdef INVARIANTS 3187 sd->ba_hwtag = htobe64(pa | FL_BUF_HWTAG(sc, sd->tag_idx)); 3188 #endif 3189 3190 recycled: 3191 fl->pending++; 3192 fl->needed--; 3193 sd++; 3194 if (++fl->pidx == fl->cap) { 3195 fl->pidx = 0; 3196 sd = fl->sdesc; 3197 d = fl->desc; 3198 } 3199 } 3200 3201 if (fl->pending >= 8) 3202 ring_fl_db(sc, fl); 3203 3204 return (FL_RUNNING_LOW(fl) && !(fl->flags & FL_STARVING)); 3205 } 3206 3207 /* 3208 * Attempt to refill all starving freelists. 3209 */ 3210 static void 3211 refill_sfl(void *arg) 3212 { 3213 struct adapter *sc = arg; 3214 struct sge_fl *fl, *fl_temp; 3215 3216 mtx_lock(&sc->sfl_lock); 3217 TAILQ_FOREACH_SAFE(fl, &sc->sfl, link, fl_temp) { 3218 FL_LOCK(fl); 3219 refill_fl(sc, fl, 64); 3220 if (FL_NOT_RUNNING_LOW(fl) || fl->flags & FL_DOOMED) { 3221 TAILQ_REMOVE(&sc->sfl, fl, link); 3222 fl->flags &= ~FL_STARVING; 3223 } 3224 FL_UNLOCK(fl); 3225 } 3226 3227 if (!TAILQ_EMPTY(&sc->sfl)) 3228 callout_schedule(&sc->sfl_callout, hz / 5); 3229 mtx_unlock(&sc->sfl_lock); 3230 } 3231 3232 static int 3233 alloc_fl_sdesc(struct sge_fl *fl) 3234 { 3235 struct fl_sdesc *sd; 3236 bus_dma_tag_t tag; 3237 int i, rc; 3238 3239 fl->sdesc = malloc(fl->cap * sizeof(struct fl_sdesc), M_CXGBE, 3240 M_ZERO | M_WAITOK); 3241 3242 tag = fl->tag[fl->tag_idx]; 3243 sd = fl->sdesc; 3244 for (i = 0; i < fl->cap; i++, sd++) { 3245 3246 sd->tag_idx = fl->tag_idx; 3247 rc = bus_dmamap_create(tag, 0, &sd->map); 3248 if (rc != 0) 3249 goto failed; 3250 } 3251 3252 return (0); 3253 failed: 3254 while (--i >= 0) { 3255 sd--; 3256 bus_dmamap_destroy(tag, sd->map); 3257 } 3258 KASSERT(sd == fl->sdesc, ("%s: EDOOFUS", __func__)); 3259 3260 free(fl->sdesc, M_CXGBE); 3261 fl->sdesc = NULL; 3262 3263 return (rc); 3264 } 3265 3266 static void 3267 free_fl_sdesc(struct adapter *sc, struct sge_fl *fl) 3268 { 3269 struct fl_sdesc *sd; 3270 int i; 3271 3272 sd = fl->sdesc; 3273 for (i = 0; i < fl->cap; i++, sd++) { 3274 3275 if (sd->cl) { 3276 bus_dmamap_unload(fl->tag[sd->tag_idx], sd->map); 3277 uma_zfree(FL_BUF_ZONE(sc, sd->tag_idx), sd->cl); 3278 sd->cl = NULL; 3279 } 3280 3281 bus_dmamap_destroy(fl->tag[sd->tag_idx], sd->map); 3282 } 3283 3284 free(fl->sdesc, M_CXGBE); 3285 fl->sdesc = NULL; 3286 } 3287 3288 int 3289 t4_alloc_tx_maps(struct tx_maps *txmaps, bus_dma_tag_t tx_tag, int count, 3290 int flags) 3291 { 3292 struct tx_map *txm; 3293 int i, rc; 3294 3295 txmaps->map_total = txmaps->map_avail = count; 3296 txmaps->map_cidx = txmaps->map_pidx = 0; 3297 3298 txmaps->maps = malloc(count * sizeof(struct tx_map), M_CXGBE, 3299 M_ZERO | flags); 3300 3301 txm = txmaps->maps; 3302 for (i = 0; i < count; i++, txm++) { 3303 rc = bus_dmamap_create(tx_tag, 0, &txm->map); 3304 if (rc != 0) 3305 goto failed; 3306 } 3307 3308 return (0); 3309 failed: 3310 while (--i >= 0) { 3311 txm--; 3312 bus_dmamap_destroy(tx_tag, txm->map); 3313 } 3314 KASSERT(txm == txmaps->maps, ("%s: EDOOFUS", __func__)); 3315 3316 free(txmaps->maps, M_CXGBE); 3317 txmaps->maps = NULL; 3318 3319 return (rc); 3320 } 3321 3322 void 3323 t4_free_tx_maps(struct tx_maps *txmaps, bus_dma_tag_t tx_tag) 3324 { 3325 struct tx_map *txm; 3326 int i; 3327 3328 txm = txmaps->maps; 3329 for (i = 0; i < txmaps->map_total; i++, txm++) { 3330 3331 if (txm->m) { 3332 bus_dmamap_unload(tx_tag, txm->map); 3333 m_freem(txm->m); 3334 txm->m = NULL; 3335 } 3336 3337 bus_dmamap_destroy(tx_tag, txm->map); 3338 } 3339 3340 free(txmaps->maps, M_CXGBE); 3341 txmaps->maps = NULL; 3342 } 3343 3344 /* 3345 * We'll do immediate data tx for non-TSO, but only when not coalescing. We're 3346 * willing to use upto 2 hardware descriptors which means a maximum of 96 bytes 3347 * of immediate data. 3348 */ 3349 #define IMM_LEN ( \ 3350 2 * EQ_ESIZE \ 3351 - sizeof(struct fw_eth_tx_pkt_wr) \ 3352 - sizeof(struct cpl_tx_pkt_core)) 3353 3354 /* 3355 * Returns non-zero on failure, no need to cleanup anything in that case. 3356 * 3357 * Note 1: We always try to defrag the mbuf if required and return EFBIG only 3358 * if the resulting chain still won't fit in a tx descriptor. 3359 * 3360 * Note 2: We'll pullup the mbuf chain if TSO is requested and the first mbuf 3361 * does not have the TCP header in it. 3362 */ 3363 static int 3364 get_pkt_sgl(struct sge_txq *txq, struct mbuf **fp, struct sgl *sgl, 3365 int sgl_only) 3366 { 3367 struct mbuf *m = *fp; 3368 struct tx_maps *txmaps; 3369 struct tx_map *txm; 3370 int rc, defragged = 0, n; 3371 3372 TXQ_LOCK_ASSERT_OWNED(txq); 3373 3374 if (m->m_pkthdr.tso_segsz) 3375 sgl_only = 1; /* Do not allow immediate data with LSO */ 3376 3377 start: sgl->nsegs = 0; 3378 3379 if (m->m_pkthdr.len <= IMM_LEN && !sgl_only) 3380 return (0); /* nsegs = 0 tells caller to use imm. tx */ 3381 3382 txmaps = &txq->txmaps; 3383 if (txmaps->map_avail == 0) { 3384 txq->no_dmamap++; 3385 return (ENOMEM); 3386 } 3387 txm = &txmaps->maps[txmaps->map_pidx]; 3388 3389 if (m->m_pkthdr.tso_segsz && m->m_len < 50) { 3390 *fp = m_pullup(m, 50); 3391 m = *fp; 3392 if (m == NULL) 3393 return (ENOBUFS); 3394 } 3395 3396 rc = bus_dmamap_load_mbuf_sg(txq->tx_tag, txm->map, m, sgl->seg, 3397 &sgl->nsegs, BUS_DMA_NOWAIT); 3398 if (rc == EFBIG && defragged == 0) { 3399 m = m_defrag(m, M_NOWAIT); 3400 if (m == NULL) 3401 return (EFBIG); 3402 3403 defragged = 1; 3404 *fp = m; 3405 goto start; 3406 } 3407 if (rc != 0) 3408 return (rc); 3409 3410 txm->m = m; 3411 txmaps->map_avail--; 3412 if (++txmaps->map_pidx == txmaps->map_total) 3413 txmaps->map_pidx = 0; 3414 3415 KASSERT(sgl->nsegs > 0 && sgl->nsegs <= TX_SGL_SEGS, 3416 ("%s: bad DMA mapping (%d segments)", __func__, sgl->nsegs)); 3417 3418 /* 3419 * Store the # of flits required to hold this frame's SGL in nflits. An 3420 * SGL has a (ULPTX header + len0, addr0) tuple optionally followed by 3421 * multiple (len0 + len1, addr0, addr1) tuples. If addr1 is not used 3422 * then len1 must be set to 0. 3423 */ 3424 n = sgl->nsegs - 1; 3425 sgl->nflits = (3 * n) / 2 + (n & 1) + 2; 3426 3427 return (0); 3428 } 3429 3430 3431 /* 3432 * Releases all the txq resources used up in the specified sgl. 3433 */ 3434 static int 3435 free_pkt_sgl(struct sge_txq *txq, struct sgl *sgl) 3436 { 3437 struct tx_maps *txmaps; 3438 struct tx_map *txm; 3439 3440 TXQ_LOCK_ASSERT_OWNED(txq); 3441 3442 if (sgl->nsegs == 0) 3443 return (0); /* didn't use any map */ 3444 3445 txmaps = &txq->txmaps; 3446 3447 /* 1 pkt uses exactly 1 map, back it out */ 3448 3449 txmaps->map_avail++; 3450 if (txmaps->map_pidx > 0) 3451 txmaps->map_pidx--; 3452 else 3453 txmaps->map_pidx = txmaps->map_total - 1; 3454 3455 txm = &txmaps->maps[txmaps->map_pidx]; 3456 bus_dmamap_unload(txq->tx_tag, txm->map); 3457 txm->m = NULL; 3458 3459 return (0); 3460 } 3461 3462 static int 3463 write_txpkt_wr(struct port_info *pi, struct sge_txq *txq, struct mbuf *m, 3464 struct sgl *sgl) 3465 { 3466 struct sge_eq *eq = &txq->eq; 3467 struct fw_eth_tx_pkt_wr *wr; 3468 struct cpl_tx_pkt_core *cpl; 3469 uint32_t ctrl; /* used in many unrelated places */ 3470 uint64_t ctrl1; 3471 int nflits, ndesc, pktlen; 3472 struct tx_sdesc *txsd; 3473 caddr_t dst; 3474 3475 TXQ_LOCK_ASSERT_OWNED(txq); 3476 3477 pktlen = m->m_pkthdr.len; 3478 3479 /* 3480 * Do we have enough flits to send this frame out? 3481 */ 3482 ctrl = sizeof(struct cpl_tx_pkt_core); 3483 if (m->m_pkthdr.tso_segsz) { 3484 nflits = TXPKT_LSO_WR_HDR; 3485 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 3486 } else 3487 nflits = TXPKT_WR_HDR; 3488 if (sgl->nsegs > 0) 3489 nflits += sgl->nflits; 3490 else { 3491 nflits += howmany(pktlen, 8); 3492 ctrl += pktlen; 3493 } 3494 ndesc = howmany(nflits, 8); 3495 if (ndesc > eq->avail) 3496 return (ENOMEM); 3497 3498 /* Firmware work request header */ 3499 wr = (void *)&eq->desc[eq->pidx]; 3500 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_WR) | 3501 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl)); 3502 ctrl = V_FW_WR_LEN16(howmany(nflits, 2)); 3503 if (eq->avail == ndesc) { 3504 if (!(eq->flags & EQ_CRFLUSHED)) { 3505 ctrl |= F_FW_WR_EQUEQ | F_FW_WR_EQUIQ; 3506 eq->flags |= EQ_CRFLUSHED; 3507 } 3508 eq->flags |= EQ_STALLED; 3509 } 3510 3511 wr->equiq_to_len16 = htobe32(ctrl); 3512 wr->r3 = 0; 3513 3514 if (m->m_pkthdr.tso_segsz) { 3515 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1); 3516 struct ether_header *eh; 3517 void *l3hdr; 3518 #if defined(INET) || defined(INET6) 3519 struct tcphdr *tcp; 3520 #endif 3521 uint16_t eh_type; 3522 3523 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE | 3524 F_LSO_LAST_SLICE; 3525 3526 eh = mtod(m, struct ether_header *); 3527 eh_type = ntohs(eh->ether_type); 3528 if (eh_type == ETHERTYPE_VLAN) { 3529 struct ether_vlan_header *evh = (void *)eh; 3530 3531 ctrl |= V_LSO_ETHHDR_LEN(1); 3532 l3hdr = evh + 1; 3533 eh_type = ntohs(evh->evl_proto); 3534 } else 3535 l3hdr = eh + 1; 3536 3537 switch (eh_type) { 3538 #ifdef INET6 3539 case ETHERTYPE_IPV6: 3540 { 3541 struct ip6_hdr *ip6 = l3hdr; 3542 3543 /* 3544 * XXX-BZ For now we do not pretend to support 3545 * IPv6 extension headers. 3546 */ 3547 KASSERT(ip6->ip6_nxt == IPPROTO_TCP, ("%s: CSUM_TSO " 3548 "with ip6_nxt != TCP: %u", __func__, ip6->ip6_nxt)); 3549 tcp = (struct tcphdr *)(ip6 + 1); 3550 ctrl |= F_LSO_IPV6; 3551 ctrl |= V_LSO_IPHDR_LEN(sizeof(*ip6) >> 2) | 3552 V_LSO_TCPHDR_LEN(tcp->th_off); 3553 break; 3554 } 3555 #endif 3556 #ifdef INET 3557 case ETHERTYPE_IP: 3558 { 3559 struct ip *ip = l3hdr; 3560 3561 tcp = (void *)((uintptr_t)ip + ip->ip_hl * 4); 3562 ctrl |= V_LSO_IPHDR_LEN(ip->ip_hl) | 3563 V_LSO_TCPHDR_LEN(tcp->th_off); 3564 break; 3565 } 3566 #endif 3567 default: 3568 panic("%s: CSUM_TSO but no supported IP version " 3569 "(0x%04x)", __func__, eh_type); 3570 } 3571 3572 lso->lso_ctrl = htobe32(ctrl); 3573 lso->ipid_ofst = htobe16(0); 3574 lso->mss = htobe16(m->m_pkthdr.tso_segsz); 3575 lso->seqno_offset = htobe32(0); 3576 lso->len = htobe32(pktlen); 3577 3578 cpl = (void *)(lso + 1); 3579 3580 txq->tso_wrs++; 3581 } else 3582 cpl = (void *)(wr + 1); 3583 3584 /* Checksum offload */ 3585 ctrl1 = 0; 3586 if (!(m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TSO))) 3587 ctrl1 |= F_TXPKT_IPCSUM_DIS; 3588 if (!(m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_UDP_IPV6 | 3589 CSUM_TCP_IPV6 | CSUM_TSO))) 3590 ctrl1 |= F_TXPKT_L4CSUM_DIS; 3591 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | 3592 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO)) 3593 txq->txcsum++; /* some hardware assistance provided */ 3594 3595 /* VLAN tag insertion */ 3596 if (m->m_flags & M_VLANTAG) { 3597 ctrl1 |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(m->m_pkthdr.ether_vtag); 3598 txq->vlan_insertion++; 3599 } 3600 3601 /* CPL header */ 3602 cpl->ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) | 3603 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(pi->adapter->pf)); 3604 cpl->pack = 0; 3605 cpl->len = htobe16(pktlen); 3606 cpl->ctrl1 = htobe64(ctrl1); 3607 3608 /* Software descriptor */ 3609 txsd = &txq->sdesc[eq->pidx]; 3610 txsd->desc_used = ndesc; 3611 3612 eq->pending += ndesc; 3613 eq->avail -= ndesc; 3614 eq->pidx += ndesc; 3615 if (eq->pidx >= eq->cap) 3616 eq->pidx -= eq->cap; 3617 3618 /* SGL */ 3619 dst = (void *)(cpl + 1); 3620 if (sgl->nsegs > 0) { 3621 txsd->credits = 1; 3622 txq->sgl_wrs++; 3623 write_sgl_to_txd(eq, sgl, &dst); 3624 } else { 3625 txsd->credits = 0; 3626 txq->imm_wrs++; 3627 for (; m; m = m->m_next) { 3628 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len); 3629 #ifdef INVARIANTS 3630 pktlen -= m->m_len; 3631 #endif 3632 } 3633 #ifdef INVARIANTS 3634 KASSERT(pktlen == 0, ("%s: %d bytes left.", __func__, pktlen)); 3635 #endif 3636 3637 } 3638 3639 txq->txpkt_wrs++; 3640 return (0); 3641 } 3642 3643 /* 3644 * Returns 0 to indicate that m has been accepted into a coalesced tx work 3645 * request. It has either been folded into txpkts or txpkts was flushed and m 3646 * has started a new coalesced work request (as the first frame in a fresh 3647 * txpkts). 3648 * 3649 * Returns non-zero to indicate a failure - caller is responsible for 3650 * transmitting m, if there was anything in txpkts it has been flushed. 3651 */ 3652 static int 3653 add_to_txpkts(struct port_info *pi, struct sge_txq *txq, struct txpkts *txpkts, 3654 struct mbuf *m, struct sgl *sgl) 3655 { 3656 struct sge_eq *eq = &txq->eq; 3657 int can_coalesce; 3658 struct tx_sdesc *txsd; 3659 int flits; 3660 3661 TXQ_LOCK_ASSERT_OWNED(txq); 3662 3663 KASSERT(sgl->nsegs, ("%s: can't coalesce imm data", __func__)); 3664 3665 if (txpkts->npkt > 0) { 3666 flits = TXPKTS_PKT_HDR + sgl->nflits; 3667 can_coalesce = m->m_pkthdr.tso_segsz == 0 && 3668 txpkts->nflits + flits <= TX_WR_FLITS && 3669 txpkts->nflits + flits <= eq->avail * 8 && 3670 txpkts->plen + m->m_pkthdr.len < 65536; 3671 3672 if (can_coalesce) { 3673 txpkts->npkt++; 3674 txpkts->nflits += flits; 3675 txpkts->plen += m->m_pkthdr.len; 3676 3677 txsd = &txq->sdesc[eq->pidx]; 3678 txsd->credits++; 3679 3680 return (0); 3681 } 3682 3683 /* 3684 * Couldn't coalesce m into txpkts. The first order of business 3685 * is to send txpkts on its way. Then we'll revisit m. 3686 */ 3687 write_txpkts_wr(txq, txpkts); 3688 } 3689 3690 /* 3691 * Check if we can start a new coalesced tx work request with m as 3692 * the first packet in it. 3693 */ 3694 3695 KASSERT(txpkts->npkt == 0, ("%s: txpkts not empty", __func__)); 3696 3697 flits = TXPKTS_WR_HDR + sgl->nflits; 3698 can_coalesce = m->m_pkthdr.tso_segsz == 0 && 3699 flits <= eq->avail * 8 && flits <= TX_WR_FLITS; 3700 3701 if (can_coalesce == 0) 3702 return (EINVAL); 3703 3704 /* 3705 * Start a fresh coalesced tx WR with m as the first frame in it. 3706 */ 3707 txpkts->npkt = 1; 3708 txpkts->nflits = flits; 3709 txpkts->flitp = &eq->desc[eq->pidx].flit[2]; 3710 txpkts->plen = m->m_pkthdr.len; 3711 3712 txsd = &txq->sdesc[eq->pidx]; 3713 txsd->credits = 1; 3714 3715 return (0); 3716 } 3717 3718 /* 3719 * Note that write_txpkts_wr can never run out of hardware descriptors (but 3720 * write_txpkt_wr can). add_to_txpkts ensures that a frame is accepted for 3721 * coalescing only if sufficient hardware descriptors are available. 3722 */ 3723 static void 3724 write_txpkts_wr(struct sge_txq *txq, struct txpkts *txpkts) 3725 { 3726 struct sge_eq *eq = &txq->eq; 3727 struct fw_eth_tx_pkts_wr *wr; 3728 struct tx_sdesc *txsd; 3729 uint32_t ctrl; 3730 int ndesc; 3731 3732 TXQ_LOCK_ASSERT_OWNED(txq); 3733 3734 ndesc = howmany(txpkts->nflits, 8); 3735 3736 wr = (void *)&eq->desc[eq->pidx]; 3737 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR)); 3738 ctrl = V_FW_WR_LEN16(howmany(txpkts->nflits, 2)); 3739 if (eq->avail == ndesc) { 3740 if (!(eq->flags & EQ_CRFLUSHED)) { 3741 ctrl |= F_FW_WR_EQUEQ | F_FW_WR_EQUIQ; 3742 eq->flags |= EQ_CRFLUSHED; 3743 } 3744 eq->flags |= EQ_STALLED; 3745 } 3746 wr->equiq_to_len16 = htobe32(ctrl); 3747 wr->plen = htobe16(txpkts->plen); 3748 wr->npkt = txpkts->npkt; 3749 wr->r3 = wr->type = 0; 3750 3751 /* Everything else already written */ 3752 3753 txsd = &txq->sdesc[eq->pidx]; 3754 txsd->desc_used = ndesc; 3755 3756 KASSERT(eq->avail >= ndesc, ("%s: out of descriptors", __func__)); 3757 3758 eq->pending += ndesc; 3759 eq->avail -= ndesc; 3760 eq->pidx += ndesc; 3761 if (eq->pidx >= eq->cap) 3762 eq->pidx -= eq->cap; 3763 3764 txq->txpkts_pkts += txpkts->npkt; 3765 txq->txpkts_wrs++; 3766 txpkts->npkt = 0; /* emptied */ 3767 } 3768 3769 static inline void 3770 write_ulp_cpl_sgl(struct port_info *pi, struct sge_txq *txq, 3771 struct txpkts *txpkts, struct mbuf *m, struct sgl *sgl) 3772 { 3773 struct ulp_txpkt *ulpmc; 3774 struct ulptx_idata *ulpsc; 3775 struct cpl_tx_pkt_core *cpl; 3776 struct sge_eq *eq = &txq->eq; 3777 uintptr_t flitp, start, end; 3778 uint64_t ctrl; 3779 caddr_t dst; 3780 3781 KASSERT(txpkts->npkt > 0, ("%s: txpkts is empty", __func__)); 3782 3783 start = (uintptr_t)eq->desc; 3784 end = (uintptr_t)eq->spg; 3785 3786 /* Checksum offload */ 3787 ctrl = 0; 3788 if (!(m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TSO))) 3789 ctrl |= F_TXPKT_IPCSUM_DIS; 3790 if (!(m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_UDP_IPV6 | 3791 CSUM_TCP_IPV6 | CSUM_TSO))) 3792 ctrl |= F_TXPKT_L4CSUM_DIS; 3793 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | 3794 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO)) 3795 txq->txcsum++; /* some hardware assistance provided */ 3796 3797 /* VLAN tag insertion */ 3798 if (m->m_flags & M_VLANTAG) { 3799 ctrl |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(m->m_pkthdr.ether_vtag); 3800 txq->vlan_insertion++; 3801 } 3802 3803 /* 3804 * The previous packet's SGL must have ended at a 16 byte boundary (this 3805 * is required by the firmware/hardware). It follows that flitp cannot 3806 * wrap around between the ULPTX master command and ULPTX subcommand (8 3807 * bytes each), and that it can not wrap around in the middle of the 3808 * cpl_tx_pkt_core either. 3809 */ 3810 flitp = (uintptr_t)txpkts->flitp; 3811 KASSERT((flitp & 0xf) == 0, 3812 ("%s: last SGL did not end at 16 byte boundary: %p", 3813 __func__, txpkts->flitp)); 3814 3815 /* ULP master command */ 3816 ulpmc = (void *)flitp; 3817 ulpmc->cmd_dest = htonl(V_ULPTX_CMD(ULP_TX_PKT) | V_ULP_TXPKT_DEST(0) | 3818 V_ULP_TXPKT_FID(eq->iqid)); 3819 ulpmc->len = htonl(howmany(sizeof(*ulpmc) + sizeof(*ulpsc) + 3820 sizeof(*cpl) + 8 * sgl->nflits, 16)); 3821 3822 /* ULP subcommand */ 3823 ulpsc = (void *)(ulpmc + 1); 3824 ulpsc->cmd_more = htobe32(V_ULPTX_CMD((u32)ULP_TX_SC_IMM) | 3825 F_ULP_TX_SC_MORE); 3826 ulpsc->len = htobe32(sizeof(struct cpl_tx_pkt_core)); 3827 3828 flitp += sizeof(*ulpmc) + sizeof(*ulpsc); 3829 if (flitp == end) 3830 flitp = start; 3831 3832 /* CPL_TX_PKT */ 3833 cpl = (void *)flitp; 3834 cpl->ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) | 3835 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(pi->adapter->pf)); 3836 cpl->pack = 0; 3837 cpl->len = htobe16(m->m_pkthdr.len); 3838 cpl->ctrl1 = htobe64(ctrl); 3839 3840 flitp += sizeof(*cpl); 3841 if (flitp == end) 3842 flitp = start; 3843 3844 /* SGL for this frame */ 3845 dst = (caddr_t)flitp; 3846 txpkts->nflits += write_sgl_to_txd(eq, sgl, &dst); 3847 txpkts->flitp = (void *)dst; 3848 3849 KASSERT(((uintptr_t)dst & 0xf) == 0, 3850 ("%s: SGL ends at %p (not a 16 byte boundary)", __func__, dst)); 3851 } 3852 3853 /* 3854 * If the SGL ends on an address that is not 16 byte aligned, this function will 3855 * add a 0 filled flit at the end. It returns 1 in that case. 3856 */ 3857 static int 3858 write_sgl_to_txd(struct sge_eq *eq, struct sgl *sgl, caddr_t *to) 3859 { 3860 __be64 *flitp, *end; 3861 struct ulptx_sgl *usgl; 3862 bus_dma_segment_t *seg; 3863 int i, padded; 3864 3865 KASSERT(sgl->nsegs > 0 && sgl->nflits > 0, 3866 ("%s: bad SGL - nsegs=%d, nflits=%d", 3867 __func__, sgl->nsegs, sgl->nflits)); 3868 3869 KASSERT(((uintptr_t)(*to) & 0xf) == 0, 3870 ("%s: SGL must start at a 16 byte boundary: %p", __func__, *to)); 3871 3872 flitp = (__be64 *)(*to); 3873 end = flitp + sgl->nflits; 3874 seg = &sgl->seg[0]; 3875 usgl = (void *)flitp; 3876 3877 /* 3878 * We start at a 16 byte boundary somewhere inside the tx descriptor 3879 * ring, so we're at least 16 bytes away from the status page. There is 3880 * no chance of a wrap around in the middle of usgl (which is 16 bytes). 3881 */ 3882 3883 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 3884 V_ULPTX_NSGE(sgl->nsegs)); 3885 usgl->len0 = htobe32(seg->ds_len); 3886 usgl->addr0 = htobe64(seg->ds_addr); 3887 seg++; 3888 3889 if ((uintptr_t)end <= (uintptr_t)eq->spg) { 3890 3891 /* Won't wrap around at all */ 3892 3893 for (i = 0; i < sgl->nsegs - 1; i++, seg++) { 3894 usgl->sge[i / 2].len[i & 1] = htobe32(seg->ds_len); 3895 usgl->sge[i / 2].addr[i & 1] = htobe64(seg->ds_addr); 3896 } 3897 if (i & 1) 3898 usgl->sge[i / 2].len[1] = htobe32(0); 3899 } else { 3900 3901 /* Will wrap somewhere in the rest of the SGL */ 3902 3903 /* 2 flits already written, write the rest flit by flit */ 3904 flitp = (void *)(usgl + 1); 3905 for (i = 0; i < sgl->nflits - 2; i++) { 3906 if ((uintptr_t)flitp == (uintptr_t)eq->spg) 3907 flitp = (void *)eq->desc; 3908 *flitp++ = get_flit(seg, sgl->nsegs - 1, i); 3909 } 3910 end = flitp; 3911 } 3912 3913 if ((uintptr_t)end & 0xf) { 3914 *(uint64_t *)end = 0; 3915 end++; 3916 padded = 1; 3917 } else 3918 padded = 0; 3919 3920 if ((uintptr_t)end == (uintptr_t)eq->spg) 3921 *to = (void *)eq->desc; 3922 else 3923 *to = (void *)end; 3924 3925 return (padded); 3926 } 3927 3928 static inline void 3929 copy_to_txd(struct sge_eq *eq, caddr_t from, caddr_t *to, int len) 3930 { 3931 if (__predict_true((uintptr_t)(*to) + len <= (uintptr_t)eq->spg)) { 3932 bcopy(from, *to, len); 3933 (*to) += len; 3934 } else { 3935 int portion = (uintptr_t)eq->spg - (uintptr_t)(*to); 3936 3937 bcopy(from, *to, portion); 3938 from += portion; 3939 portion = len - portion; /* remaining */ 3940 bcopy(from, (void *)eq->desc, portion); 3941 (*to) = (caddr_t)eq->desc + portion; 3942 } 3943 } 3944 3945 static inline void 3946 ring_eq_db(struct adapter *sc, struct sge_eq *eq) 3947 { 3948 u_int db, pending; 3949 3950 db = eq->doorbells; 3951 pending = eq->pending; 3952 if (pending > 1) 3953 clrbit(&db, DOORBELL_WCWR); 3954 eq->pending = 0; 3955 wmb(); 3956 3957 switch (ffs(db) - 1) { 3958 case DOORBELL_UDB: 3959 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(pending)); 3960 return; 3961 3962 case DOORBELL_WCWR: { 3963 volatile uint64_t *dst, *src; 3964 int i; 3965 3966 /* 3967 * Queues whose 128B doorbell segment fits in the page do not 3968 * use relative qid (udb_qid is always 0). Only queues with 3969 * doorbell segments can do WCWR. 3970 */ 3971 KASSERT(eq->udb_qid == 0 && pending == 1, 3972 ("%s: inappropriate doorbell (0x%x, %d, %d) for eq %p", 3973 __func__, eq->doorbells, pending, eq->pidx, eq)); 3974 3975 dst = (volatile void *)((uintptr_t)eq->udb + UDBS_WR_OFFSET - 3976 UDBS_DB_OFFSET); 3977 i = eq->pidx ? eq->pidx - 1 : eq->cap - 1; 3978 src = (void *)&eq->desc[i]; 3979 while (src != (void *)&eq->desc[i + 1]) 3980 *dst++ = *src++; 3981 wmb(); 3982 return; 3983 } 3984 3985 case DOORBELL_UDBWC: 3986 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(pending)); 3987 wmb(); 3988 return; 3989 3990 case DOORBELL_KDB: 3991 t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL), 3992 V_QID(eq->cntxt_id) | V_PIDX(pending)); 3993 return; 3994 } 3995 } 3996 3997 static inline int 3998 reclaimable(struct sge_eq *eq) 3999 { 4000 unsigned int cidx; 4001 4002 cidx = eq->spg->cidx; /* stable snapshot */ 4003 cidx = be16toh(cidx); 4004 4005 if (cidx >= eq->cidx) 4006 return (cidx - eq->cidx); 4007 else 4008 return (cidx + eq->cap - eq->cidx); 4009 } 4010 4011 /* 4012 * There are "can_reclaim" tx descriptors ready to be reclaimed. Reclaim as 4013 * many as possible but stop when there are around "n" mbufs to free. 4014 * 4015 * The actual number reclaimed is provided as the return value. 4016 */ 4017 static int 4018 reclaim_tx_descs(struct sge_txq *txq, int can_reclaim, int n) 4019 { 4020 struct tx_sdesc *txsd; 4021 struct tx_maps *txmaps; 4022 struct tx_map *txm; 4023 unsigned int reclaimed, maps; 4024 struct sge_eq *eq = &txq->eq; 4025 4026 TXQ_LOCK_ASSERT_OWNED(txq); 4027 4028 if (can_reclaim == 0) 4029 can_reclaim = reclaimable(eq); 4030 4031 maps = reclaimed = 0; 4032 while (can_reclaim && maps < n) { 4033 int ndesc; 4034 4035 txsd = &txq->sdesc[eq->cidx]; 4036 ndesc = txsd->desc_used; 4037 4038 /* Firmware doesn't return "partial" credits. */ 4039 KASSERT(can_reclaim >= ndesc, 4040 ("%s: unexpected number of credits: %d, %d", 4041 __func__, can_reclaim, ndesc)); 4042 4043 maps += txsd->credits; 4044 4045 reclaimed += ndesc; 4046 can_reclaim -= ndesc; 4047 4048 eq->cidx += ndesc; 4049 if (__predict_false(eq->cidx >= eq->cap)) 4050 eq->cidx -= eq->cap; 4051 } 4052 4053 txmaps = &txq->txmaps; 4054 txm = &txmaps->maps[txmaps->map_cidx]; 4055 if (maps) 4056 prefetch(txm->m); 4057 4058 eq->avail += reclaimed; 4059 KASSERT(eq->avail < eq->cap, /* avail tops out at (cap - 1) */ 4060 ("%s: too many descriptors available", __func__)); 4061 4062 txmaps->map_avail += maps; 4063 KASSERT(txmaps->map_avail <= txmaps->map_total, 4064 ("%s: too many maps available", __func__)); 4065 4066 while (maps--) { 4067 struct tx_map *next; 4068 4069 next = txm + 1; 4070 if (__predict_false(txmaps->map_cidx + 1 == txmaps->map_total)) 4071 next = txmaps->maps; 4072 prefetch(next->m); 4073 4074 bus_dmamap_unload(txq->tx_tag, txm->map); 4075 m_freem(txm->m); 4076 txm->m = NULL; 4077 4078 txm = next; 4079 if (__predict_false(++txmaps->map_cidx == txmaps->map_total)) 4080 txmaps->map_cidx = 0; 4081 } 4082 4083 return (reclaimed); 4084 } 4085 4086 static void 4087 write_eqflush_wr(struct sge_eq *eq) 4088 { 4089 struct fw_eq_flush_wr *wr; 4090 4091 EQ_LOCK_ASSERT_OWNED(eq); 4092 KASSERT(eq->avail > 0, ("%s: no descriptors left.", __func__)); 4093 KASSERT(!(eq->flags & EQ_CRFLUSHED), ("%s: flushed already", __func__)); 4094 4095 wr = (void *)&eq->desc[eq->pidx]; 4096 bzero(wr, sizeof(*wr)); 4097 wr->opcode = FW_EQ_FLUSH_WR; 4098 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(sizeof(*wr) / 16) | 4099 F_FW_WR_EQUEQ | F_FW_WR_EQUIQ); 4100 4101 eq->flags |= (EQ_CRFLUSHED | EQ_STALLED); 4102 eq->pending++; 4103 eq->avail--; 4104 if (++eq->pidx == eq->cap) 4105 eq->pidx = 0; 4106 } 4107 4108 static __be64 4109 get_flit(bus_dma_segment_t *sgl, int nsegs, int idx) 4110 { 4111 int i = (idx / 3) * 2; 4112 4113 switch (idx % 3) { 4114 case 0: { 4115 __be64 rc; 4116 4117 rc = htobe32(sgl[i].ds_len); 4118 if (i + 1 < nsegs) 4119 rc |= (uint64_t)htobe32(sgl[i + 1].ds_len) << 32; 4120 4121 return (rc); 4122 } 4123 case 1: 4124 return htobe64(sgl[i].ds_addr); 4125 case 2: 4126 return htobe64(sgl[i + 1].ds_addr); 4127 } 4128 4129 return (0); 4130 } 4131 4132 /* 4133 * Find an SGE FL buffer size to use for the given bufsize. Look for the the 4134 * smallest size that is large enough to hold bufsize or pick the largest size 4135 * if all sizes are less than bufsize. 4136 */ 4137 static void 4138 set_fl_tag_idx(struct adapter *sc, struct sge_fl *fl, int bufsize) 4139 { 4140 int i, largest, best, delta, start; 4141 4142 if (fl->flags & FL_BUF_PACKING) { 4143 fl->tag_idx = 0; /* first tag is the one for packing */ 4144 return; 4145 } 4146 4147 start = sc->flags & BUF_PACKING_OK ? 1 : 0; 4148 delta = FL_BUF_SIZE(sc, start) - bufsize; 4149 if (delta == 0) { 4150 fl->tag_idx = start; /* ideal fit, look no further */ 4151 return; 4152 } 4153 best = start; 4154 largest = start; 4155 4156 for (i = start + 1; i < FL_BUF_SIZES(sc); i++) { 4157 int d, fl_buf_size; 4158 4159 fl_buf_size = FL_BUF_SIZE(sc, i); 4160 d = fl_buf_size - bufsize; 4161 4162 if (d == 0) { 4163 fl->tag_idx = i; /* ideal fit, look no further */ 4164 return; 4165 } 4166 if (fl_buf_size > FL_BUF_SIZE(sc, largest)) 4167 largest = i; 4168 if (d > 0 && (delta < 0 || delta > d)) { 4169 delta = d; 4170 best = i; 4171 } 4172 } 4173 4174 if (delta > 0) 4175 fl->tag_idx = best; /* Found a buf bigger than bufsize */ 4176 else 4177 fl->tag_idx = largest; /* No buf large enough for bufsize */ 4178 } 4179 4180 static void 4181 add_fl_to_sfl(struct adapter *sc, struct sge_fl *fl) 4182 { 4183 mtx_lock(&sc->sfl_lock); 4184 FL_LOCK(fl); 4185 if ((fl->flags & FL_DOOMED) == 0) { 4186 fl->flags |= FL_STARVING; 4187 TAILQ_INSERT_TAIL(&sc->sfl, fl, link); 4188 callout_reset(&sc->sfl_callout, hz / 5, refill_sfl, sc); 4189 } 4190 FL_UNLOCK(fl); 4191 mtx_unlock(&sc->sfl_lock); 4192 } 4193 4194 static int 4195 handle_sge_egr_update(struct sge_iq *iq, const struct rss_header *rss, 4196 struct mbuf *m) 4197 { 4198 const struct cpl_sge_egr_update *cpl = (const void *)(rss + 1); 4199 unsigned int qid = G_EGR_QID(ntohl(cpl->opcode_qid)); 4200 struct adapter *sc = iq->adapter; 4201 struct sge *s = &sc->sge; 4202 struct sge_eq *eq; 4203 4204 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 4205 rss->opcode)); 4206 4207 eq = s->eqmap[qid - s->eq_start]; 4208 EQ_LOCK(eq); 4209 KASSERT(eq->flags & EQ_CRFLUSHED, 4210 ("%s: unsolicited egress update", __func__)); 4211 eq->flags &= ~EQ_CRFLUSHED; 4212 eq->egr_update++; 4213 4214 if (__predict_false(eq->flags & EQ_DOOMED)) 4215 wakeup_one(eq); 4216 else if (eq->flags & EQ_STALLED && can_resume_tx(eq)) 4217 taskqueue_enqueue(sc->tq[eq->tx_chan], &eq->tx_task); 4218 EQ_UNLOCK(eq); 4219 4220 return (0); 4221 } 4222 4223 /* handle_fw_msg works for both fw4_msg and fw6_msg because this is valid */ 4224 CTASSERT(offsetof(struct cpl_fw4_msg, data) == \ 4225 offsetof(struct cpl_fw6_msg, data)); 4226 4227 static int 4228 handle_fw_msg(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 4229 { 4230 struct adapter *sc = iq->adapter; 4231 const struct cpl_fw6_msg *cpl = (const void *)(rss + 1); 4232 4233 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 4234 rss->opcode)); 4235 4236 if (cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL) { 4237 const struct rss_header *rss2; 4238 4239 rss2 = (const struct rss_header *)&cpl->data[0]; 4240 return (sc->cpl_handler[rss2->opcode](iq, rss2, m)); 4241 } 4242 4243 return (sc->fw_msg_handler[cpl->type](sc, &cpl->data[0])); 4244 } 4245 4246 static int 4247 sysctl_uint16(SYSCTL_HANDLER_ARGS) 4248 { 4249 uint16_t *id = arg1; 4250 int i = *id; 4251 4252 return sysctl_handle_int(oidp, &i, 0, req); 4253 } 4254