xref: /freebsd/sys/dev/cxgbe/t4_sge.c (revision 998eb37aca6670b1ecbb7b5cad2b5b2d85d744b8)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3  *
4  * Copyright (c) 2011 Chelsio Communications, Inc.
5  * All rights reserved.
6  * Written by: Navdeep Parhar <np@FreeBSD.org>
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions and the following disclaimer.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27  * SUCH DAMAGE.
28  */
29 
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
32 
33 #include "opt_inet.h"
34 #include "opt_inet6.h"
35 #include "opt_kern_tls.h"
36 #include "opt_ratelimit.h"
37 
38 #include <sys/types.h>
39 #include <sys/eventhandler.h>
40 #include <sys/mbuf.h>
41 #include <sys/socket.h>
42 #include <sys/kernel.h>
43 #include <sys/ktls.h>
44 #include <sys/malloc.h>
45 #include <sys/msan.h>
46 #include <sys/queue.h>
47 #include <sys/sbuf.h>
48 #include <sys/taskqueue.h>
49 #include <sys/time.h>
50 #include <sys/sglist.h>
51 #include <sys/sysctl.h>
52 #include <sys/smp.h>
53 #include <sys/socketvar.h>
54 #include <sys/counter.h>
55 #include <net/bpf.h>
56 #include <net/ethernet.h>
57 #include <net/if.h>
58 #include <net/if_vlan_var.h>
59 #include <net/if_vxlan.h>
60 #include <netinet/in.h>
61 #include <netinet/ip.h>
62 #include <netinet/ip6.h>
63 #include <netinet/tcp.h>
64 #include <netinet/udp.h>
65 #include <machine/in_cksum.h>
66 #include <machine/md_var.h>
67 #include <vm/vm.h>
68 #include <vm/pmap.h>
69 #ifdef DEV_NETMAP
70 #include <machine/bus.h>
71 #include <sys/selinfo.h>
72 #include <net/if_var.h>
73 #include <net/netmap.h>
74 #include <dev/netmap/netmap_kern.h>
75 #endif
76 
77 #include "common/common.h"
78 #include "common/t4_regs.h"
79 #include "common/t4_regs_values.h"
80 #include "common/t4_msg.h"
81 #include "t4_l2t.h"
82 #include "t4_mp_ring.h"
83 
84 #ifdef T4_PKT_TIMESTAMP
85 #define RX_COPY_THRESHOLD (MINCLSIZE - 8)
86 #else
87 #define RX_COPY_THRESHOLD MINCLSIZE
88 #endif
89 
90 /* Internal mbuf flags stored in PH_loc.eight[1]. */
91 #define	MC_NOMAP		0x01
92 #define	MC_RAW_WR		0x02
93 #define	MC_TLS			0x04
94 
95 /*
96  * Ethernet frames are DMA'd at this byte offset into the freelist buffer.
97  * 0-7 are valid values.
98  */
99 static int fl_pktshift = 0;
100 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pktshift, CTLFLAG_RDTUN, &fl_pktshift, 0,
101     "payload DMA offset in rx buffer (bytes)");
102 
103 /*
104  * Pad ethernet payload up to this boundary.
105  * -1: driver should figure out a good value.
106  *  0: disable padding.
107  *  Any power of 2 from 32 to 4096 (both inclusive) is also a valid value.
108  */
109 int fl_pad = -1;
110 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pad, CTLFLAG_RDTUN, &fl_pad, 0,
111     "payload pad boundary (bytes)");
112 
113 /*
114  * Status page length.
115  * -1: driver should figure out a good value.
116  *  64 or 128 are the only other valid values.
117  */
118 static int spg_len = -1;
119 SYSCTL_INT(_hw_cxgbe, OID_AUTO, spg_len, CTLFLAG_RDTUN, &spg_len, 0,
120     "status page size (bytes)");
121 
122 /*
123  * Congestion drops.
124  * -1: no congestion feedback (not recommended).
125  *  0: backpressure the channel instead of dropping packets right away.
126  *  1: no backpressure, drop packets for the congested queue immediately.
127  *  2: both backpressure and drop.
128  */
129 static int cong_drop = 0;
130 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cong_drop, CTLFLAG_RDTUN, &cong_drop, 0,
131     "Congestion control for NIC RX queues (0 = backpressure, 1 = drop, 2 = both");
132 #ifdef TCP_OFFLOAD
133 static int ofld_cong_drop = 0;
134 SYSCTL_INT(_hw_cxgbe, OID_AUTO, ofld_cong_drop, CTLFLAG_RDTUN, &ofld_cong_drop, 0,
135     "Congestion control for TOE RX queues (0 = backpressure, 1 = drop, 2 = both");
136 #endif
137 
138 /*
139  * Deliver multiple frames in the same free list buffer if they fit.
140  * -1: let the driver decide whether to enable buffer packing or not.
141  *  0: disable buffer packing.
142  *  1: enable buffer packing.
143  */
144 static int buffer_packing = -1;
145 SYSCTL_INT(_hw_cxgbe, OID_AUTO, buffer_packing, CTLFLAG_RDTUN, &buffer_packing,
146     0, "Enable buffer packing");
147 
148 /*
149  * Start next frame in a packed buffer at this boundary.
150  * -1: driver should figure out a good value.
151  * T4: driver will ignore this and use the same value as fl_pad above.
152  * T5: 16, or a power of 2 from 64 to 4096 (both inclusive) is a valid value.
153  */
154 static int fl_pack = -1;
155 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pack, CTLFLAG_RDTUN, &fl_pack, 0,
156     "payload pack boundary (bytes)");
157 
158 /*
159  * Largest rx cluster size that the driver is allowed to allocate.
160  */
161 static int largest_rx_cluster = MJUM16BYTES;
162 SYSCTL_INT(_hw_cxgbe, OID_AUTO, largest_rx_cluster, CTLFLAG_RDTUN,
163     &largest_rx_cluster, 0, "Largest rx cluster (bytes)");
164 
165 /*
166  * Size of cluster allocation that's most likely to succeed.  The driver will
167  * fall back to this size if it fails to allocate clusters larger than this.
168  */
169 static int safest_rx_cluster = PAGE_SIZE;
170 SYSCTL_INT(_hw_cxgbe, OID_AUTO, safest_rx_cluster, CTLFLAG_RDTUN,
171     &safest_rx_cluster, 0, "Safe rx cluster (bytes)");
172 
173 #ifdef RATELIMIT
174 /*
175  * Knob to control TCP timestamp rewriting, and the granularity of the tick used
176  * for rewriting.  -1 and 0-3 are all valid values.
177  * -1: hardware should leave the TCP timestamps alone.
178  * 0: 1ms
179  * 1: 100us
180  * 2: 10us
181  * 3: 1us
182  */
183 static int tsclk = -1;
184 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tsclk, CTLFLAG_RDTUN, &tsclk, 0,
185     "Control TCP timestamp rewriting when using pacing");
186 
187 static int eo_max_backlog = 1024 * 1024;
188 SYSCTL_INT(_hw_cxgbe, OID_AUTO, eo_max_backlog, CTLFLAG_RDTUN, &eo_max_backlog,
189     0, "Maximum backlog of ratelimited data per flow");
190 #endif
191 
192 /*
193  * The interrupt holdoff timers are multiplied by this value on T6+.
194  * 1 and 3-17 (both inclusive) are legal values.
195  */
196 static int tscale = 1;
197 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tscale, CTLFLAG_RDTUN, &tscale, 0,
198     "Interrupt holdoff timer scale on T6+");
199 
200 /*
201  * Number of LRO entries in the lro_ctrl structure per rx queue.
202  */
203 static int lro_entries = TCP_LRO_ENTRIES;
204 SYSCTL_INT(_hw_cxgbe, OID_AUTO, lro_entries, CTLFLAG_RDTUN, &lro_entries, 0,
205     "Number of LRO entries per RX queue");
206 
207 /*
208  * This enables presorting of frames before they're fed into tcp_lro_rx.
209  */
210 static int lro_mbufs = 0;
211 SYSCTL_INT(_hw_cxgbe, OID_AUTO, lro_mbufs, CTLFLAG_RDTUN, &lro_mbufs, 0,
212     "Enable presorting of LRO frames");
213 
214 static counter_u64_t pullups;
215 SYSCTL_COUNTER_U64(_hw_cxgbe, OID_AUTO, pullups, CTLFLAG_RD, &pullups,
216     "Number of mbuf pullups performed");
217 
218 static counter_u64_t defrags;
219 SYSCTL_COUNTER_U64(_hw_cxgbe, OID_AUTO, defrags, CTLFLAG_RD, &defrags,
220     "Number of mbuf defrags performed");
221 
222 static int t4_tx_coalesce = 1;
223 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tx_coalesce, CTLFLAG_RWTUN, &t4_tx_coalesce, 0,
224     "tx coalescing allowed");
225 
226 /*
227  * The driver will make aggressive attempts at tx coalescing if it sees these
228  * many packets eligible for coalescing in quick succession, with no more than
229  * the specified gap in between the eth_tx calls that delivered the packets.
230  */
231 static int t4_tx_coalesce_pkts = 32;
232 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tx_coalesce_pkts, CTLFLAG_RWTUN,
233     &t4_tx_coalesce_pkts, 0,
234     "# of consecutive packets (1 - 255) that will trigger tx coalescing");
235 static int t4_tx_coalesce_gap = 5;
236 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tx_coalesce_gap, CTLFLAG_RWTUN,
237     &t4_tx_coalesce_gap, 0, "tx gap (in microseconds)");
238 
239 static int service_iq(struct sge_iq *, int);
240 static int service_iq_fl(struct sge_iq *, int);
241 static struct mbuf *get_fl_payload(struct adapter *, struct sge_fl *, uint32_t);
242 static int eth_rx(struct adapter *, struct sge_rxq *, const struct iq_desc *,
243     u_int);
244 static inline void init_iq(struct sge_iq *, struct adapter *, int, int, int,
245     int, int, int);
246 static inline void init_fl(struct adapter *, struct sge_fl *, int, int, char *);
247 static inline void init_eq(struct adapter *, struct sge_eq *, int, int, uint8_t,
248     struct sge_iq *, char *);
249 static int alloc_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *,
250     struct sysctl_ctx_list *, struct sysctl_oid *);
251 static void free_iq_fl(struct adapter *, struct sge_iq *, struct sge_fl *);
252 static void add_iq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *,
253     struct sge_iq *);
254 static void add_fl_sysctls(struct adapter *, struct sysctl_ctx_list *,
255     struct sysctl_oid *, struct sge_fl *);
256 static int alloc_iq_fl_hwq(struct vi_info *, struct sge_iq *, struct sge_fl *);
257 static int free_iq_fl_hwq(struct adapter *, struct sge_iq *, struct sge_fl *);
258 static int alloc_fwq(struct adapter *);
259 static void free_fwq(struct adapter *);
260 static int alloc_ctrlq(struct adapter *, int);
261 static void free_ctrlq(struct adapter *, int);
262 static int alloc_rxq(struct vi_info *, struct sge_rxq *, int, int, int);
263 static void free_rxq(struct vi_info *, struct sge_rxq *);
264 static void add_rxq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *,
265     struct sge_rxq *);
266 #ifdef TCP_OFFLOAD
267 static int alloc_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *, int, int,
268     int);
269 static void free_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *);
270 static void add_ofld_rxq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *,
271     struct sge_ofld_rxq *);
272 #endif
273 static int ctrl_eq_alloc(struct adapter *, struct sge_eq *);
274 static int eth_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *);
275 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
276 static int ofld_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *);
277 #endif
278 static int alloc_eq(struct adapter *, struct sge_eq *, struct sysctl_ctx_list *,
279     struct sysctl_oid *);
280 static void free_eq(struct adapter *, struct sge_eq *);
281 static void add_eq_sysctls(struct adapter *, struct sysctl_ctx_list *,
282     struct sysctl_oid *, struct sge_eq *);
283 static int alloc_eq_hwq(struct adapter *, struct vi_info *, struct sge_eq *);
284 static int free_eq_hwq(struct adapter *, struct vi_info *, struct sge_eq *);
285 static int alloc_wrq(struct adapter *, struct vi_info *, struct sge_wrq *,
286     struct sysctl_ctx_list *, struct sysctl_oid *);
287 static void free_wrq(struct adapter *, struct sge_wrq *);
288 static void add_wrq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *,
289     struct sge_wrq *);
290 static int alloc_txq(struct vi_info *, struct sge_txq *, int);
291 static void free_txq(struct vi_info *, struct sge_txq *);
292 static void add_txq_sysctls(struct vi_info *, struct sysctl_ctx_list *,
293     struct sysctl_oid *, struct sge_txq *);
294 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
295 static int alloc_ofld_txq(struct vi_info *, struct sge_ofld_txq *, int);
296 static void free_ofld_txq(struct vi_info *, struct sge_ofld_txq *);
297 static void add_ofld_txq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *,
298     struct sge_ofld_txq *);
299 #endif
300 static void oneseg_dma_callback(void *, bus_dma_segment_t *, int, int);
301 static inline void ring_fl_db(struct adapter *, struct sge_fl *);
302 static int refill_fl(struct adapter *, struct sge_fl *, int);
303 static void refill_sfl(void *);
304 static int find_refill_source(struct adapter *, int, bool);
305 static void add_fl_to_sfl(struct adapter *, struct sge_fl *);
306 
307 static inline void get_pkt_gl(struct mbuf *, struct sglist *);
308 static inline u_int txpkt_len16(u_int, const u_int);
309 static inline u_int txpkt_vm_len16(u_int, const u_int);
310 static inline void calculate_mbuf_len16(struct mbuf *, bool);
311 static inline u_int txpkts0_len16(u_int);
312 static inline u_int txpkts1_len16(void);
313 static u_int write_raw_wr(struct sge_txq *, void *, struct mbuf *, u_int);
314 static u_int write_txpkt_wr(struct adapter *, struct sge_txq *, struct mbuf *,
315     u_int);
316 static u_int write_txpkt_vm_wr(struct adapter *, struct sge_txq *,
317     struct mbuf *);
318 static int add_to_txpkts_vf(struct adapter *, struct sge_txq *, struct mbuf *,
319     int, bool *);
320 static int add_to_txpkts_pf(struct adapter *, struct sge_txq *, struct mbuf *,
321     int, bool *);
322 static u_int write_txpkts_wr(struct adapter *, struct sge_txq *);
323 static u_int write_txpkts_vm_wr(struct adapter *, struct sge_txq *);
324 static void write_gl_to_txd(struct sge_txq *, struct mbuf *, caddr_t *, int);
325 static inline void copy_to_txd(struct sge_eq *, caddr_t, caddr_t *, int);
326 static inline void ring_eq_db(struct adapter *, struct sge_eq *, u_int);
327 static inline uint16_t read_hw_cidx(struct sge_eq *);
328 static inline u_int reclaimable_tx_desc(struct sge_eq *);
329 static inline u_int total_available_tx_desc(struct sge_eq *);
330 static u_int reclaim_tx_descs(struct sge_txq *, u_int);
331 static void tx_reclaim(void *, int);
332 static __be64 get_flit(struct sglist_seg *, int, int);
333 static int handle_sge_egr_update(struct sge_iq *, const struct rss_header *,
334     struct mbuf *);
335 static int handle_fw_msg(struct sge_iq *, const struct rss_header *,
336     struct mbuf *);
337 static int t4_handle_wrerr_rpl(struct adapter *, const __be64 *);
338 static void wrq_tx_drain(void *, int);
339 static void drain_wrq_wr_list(struct adapter *, struct sge_wrq *);
340 
341 static int sysctl_bufsizes(SYSCTL_HANDLER_ARGS);
342 #ifdef RATELIMIT
343 #if defined(INET) || defined(INET6)
344 static inline u_int txpkt_eo_len16(u_int, u_int, u_int);
345 #endif
346 static int ethofld_fw4_ack(struct sge_iq *, const struct rss_header *,
347     struct mbuf *);
348 #endif
349 
350 static counter_u64_t extfree_refs;
351 static counter_u64_t extfree_rels;
352 
353 an_handler_t t4_an_handler;
354 fw_msg_handler_t t4_fw_msg_handler[NUM_FW6_TYPES];
355 cpl_handler_t t4_cpl_handler[NUM_CPL_CMDS];
356 cpl_handler_t set_tcb_rpl_handlers[NUM_CPL_COOKIES];
357 cpl_handler_t l2t_write_rpl_handlers[NUM_CPL_COOKIES];
358 cpl_handler_t act_open_rpl_handlers[NUM_CPL_COOKIES];
359 cpl_handler_t abort_rpl_rss_handlers[NUM_CPL_COOKIES];
360 cpl_handler_t fw4_ack_handlers[NUM_CPL_COOKIES];
361 
362 void
363 t4_register_an_handler(an_handler_t h)
364 {
365 	uintptr_t *loc;
366 
367 	MPASS(h == NULL || t4_an_handler == NULL);
368 
369 	loc = (uintptr_t *)&t4_an_handler;
370 	atomic_store_rel_ptr(loc, (uintptr_t)h);
371 }
372 
373 void
374 t4_register_fw_msg_handler(int type, fw_msg_handler_t h)
375 {
376 	uintptr_t *loc;
377 
378 	MPASS(type < nitems(t4_fw_msg_handler));
379 	MPASS(h == NULL || t4_fw_msg_handler[type] == NULL);
380 	/*
381 	 * These are dispatched by the handler for FW{4|6}_CPL_MSG using the CPL
382 	 * handler dispatch table.  Reject any attempt to install a handler for
383 	 * this subtype.
384 	 */
385 	MPASS(type != FW_TYPE_RSSCPL);
386 	MPASS(type != FW6_TYPE_RSSCPL);
387 
388 	loc = (uintptr_t *)&t4_fw_msg_handler[type];
389 	atomic_store_rel_ptr(loc, (uintptr_t)h);
390 }
391 
392 void
393 t4_register_cpl_handler(int opcode, cpl_handler_t h)
394 {
395 	uintptr_t *loc;
396 
397 	MPASS(opcode < nitems(t4_cpl_handler));
398 	MPASS(h == NULL || t4_cpl_handler[opcode] == NULL);
399 
400 	loc = (uintptr_t *)&t4_cpl_handler[opcode];
401 	atomic_store_rel_ptr(loc, (uintptr_t)h);
402 }
403 
404 static int
405 set_tcb_rpl_handler(struct sge_iq *iq, const struct rss_header *rss,
406     struct mbuf *m)
407 {
408 	const struct cpl_set_tcb_rpl *cpl = (const void *)(rss + 1);
409 	u_int tid;
410 	int cookie;
411 
412 	MPASS(m == NULL);
413 
414 	tid = GET_TID(cpl);
415 	if (is_hpftid(iq->adapter, tid) || is_ftid(iq->adapter, tid)) {
416 		/*
417 		 * The return code for filter-write is put in the CPL cookie so
418 		 * we have to rely on the hardware tid (is_ftid) to determine
419 		 * that this is a response to a filter.
420 		 */
421 		cookie = CPL_COOKIE_FILTER;
422 	} else {
423 		cookie = G_COOKIE(cpl->cookie);
424 	}
425 	MPASS(cookie > CPL_COOKIE_RESERVED);
426 	MPASS(cookie < nitems(set_tcb_rpl_handlers));
427 
428 	return (set_tcb_rpl_handlers[cookie](iq, rss, m));
429 }
430 
431 static int
432 l2t_write_rpl_handler(struct sge_iq *iq, const struct rss_header *rss,
433     struct mbuf *m)
434 {
435 	const struct cpl_l2t_write_rpl *rpl = (const void *)(rss + 1);
436 	unsigned int cookie;
437 
438 	MPASS(m == NULL);
439 
440 	cookie = GET_TID(rpl) & F_SYNC_WR ? CPL_COOKIE_TOM : CPL_COOKIE_FILTER;
441 	return (l2t_write_rpl_handlers[cookie](iq, rss, m));
442 }
443 
444 static int
445 act_open_rpl_handler(struct sge_iq *iq, const struct rss_header *rss,
446     struct mbuf *m)
447 {
448 	const struct cpl_act_open_rpl *cpl = (const void *)(rss + 1);
449 	u_int cookie = G_TID_COOKIE(G_AOPEN_ATID(be32toh(cpl->atid_status)));
450 
451 	MPASS(m == NULL);
452 	MPASS(cookie != CPL_COOKIE_RESERVED);
453 
454 	return (act_open_rpl_handlers[cookie](iq, rss, m));
455 }
456 
457 static int
458 abort_rpl_rss_handler(struct sge_iq *iq, const struct rss_header *rss,
459     struct mbuf *m)
460 {
461 	struct adapter *sc = iq->adapter;
462 	u_int cookie;
463 
464 	MPASS(m == NULL);
465 	if (is_hashfilter(sc))
466 		cookie = CPL_COOKIE_HASHFILTER;
467 	else
468 		cookie = CPL_COOKIE_TOM;
469 
470 	return (abort_rpl_rss_handlers[cookie](iq, rss, m));
471 }
472 
473 static int
474 fw4_ack_handler(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
475 {
476 	struct adapter *sc = iq->adapter;
477 	const struct cpl_fw4_ack *cpl = (const void *)(rss + 1);
478 	unsigned int tid = G_CPL_FW4_ACK_FLOWID(be32toh(OPCODE_TID(cpl)));
479 	u_int cookie;
480 
481 	MPASS(m == NULL);
482 	if (is_etid(sc, tid))
483 		cookie = CPL_COOKIE_ETHOFLD;
484 	else
485 		cookie = CPL_COOKIE_TOM;
486 
487 	return (fw4_ack_handlers[cookie](iq, rss, m));
488 }
489 
490 static void
491 t4_init_shared_cpl_handlers(void)
492 {
493 
494 	t4_register_cpl_handler(CPL_SET_TCB_RPL, set_tcb_rpl_handler);
495 	t4_register_cpl_handler(CPL_L2T_WRITE_RPL, l2t_write_rpl_handler);
496 	t4_register_cpl_handler(CPL_ACT_OPEN_RPL, act_open_rpl_handler);
497 	t4_register_cpl_handler(CPL_ABORT_RPL_RSS, abort_rpl_rss_handler);
498 	t4_register_cpl_handler(CPL_FW4_ACK, fw4_ack_handler);
499 }
500 
501 void
502 t4_register_shared_cpl_handler(int opcode, cpl_handler_t h, int cookie)
503 {
504 	uintptr_t *loc;
505 
506 	MPASS(opcode < nitems(t4_cpl_handler));
507 	MPASS(cookie > CPL_COOKIE_RESERVED);
508 	MPASS(cookie < NUM_CPL_COOKIES);
509 	MPASS(t4_cpl_handler[opcode] != NULL);
510 
511 	switch (opcode) {
512 	case CPL_SET_TCB_RPL:
513 		loc = (uintptr_t *)&set_tcb_rpl_handlers[cookie];
514 		break;
515 	case CPL_L2T_WRITE_RPL:
516 		loc = (uintptr_t *)&l2t_write_rpl_handlers[cookie];
517 		break;
518 	case CPL_ACT_OPEN_RPL:
519 		loc = (uintptr_t *)&act_open_rpl_handlers[cookie];
520 		break;
521 	case CPL_ABORT_RPL_RSS:
522 		loc = (uintptr_t *)&abort_rpl_rss_handlers[cookie];
523 		break;
524 	case CPL_FW4_ACK:
525 		loc = (uintptr_t *)&fw4_ack_handlers[cookie];
526 		break;
527 	default:
528 		MPASS(0);
529 		return;
530 	}
531 	MPASS(h == NULL || *loc == (uintptr_t)NULL);
532 	atomic_store_rel_ptr(loc, (uintptr_t)h);
533 }
534 
535 /*
536  * Called on MOD_LOAD.  Validates and calculates the SGE tunables.
537  */
538 void
539 t4_sge_modload(void)
540 {
541 
542 	if (fl_pktshift < 0 || fl_pktshift > 7) {
543 		printf("Invalid hw.cxgbe.fl_pktshift value (%d),"
544 		    " using 0 instead.\n", fl_pktshift);
545 		fl_pktshift = 0;
546 	}
547 
548 	if (spg_len != 64 && spg_len != 128) {
549 		int len;
550 
551 #if defined(__i386__) || defined(__amd64__)
552 		len = cpu_clflush_line_size > 64 ? 128 : 64;
553 #else
554 		len = 64;
555 #endif
556 		if (spg_len != -1) {
557 			printf("Invalid hw.cxgbe.spg_len value (%d),"
558 			    " using %d instead.\n", spg_len, len);
559 		}
560 		spg_len = len;
561 	}
562 
563 	if (cong_drop < -1 || cong_drop > 2) {
564 		printf("Invalid hw.cxgbe.cong_drop value (%d),"
565 		    " using 0 instead.\n", cong_drop);
566 		cong_drop = 0;
567 	}
568 #ifdef TCP_OFFLOAD
569 	if (ofld_cong_drop < -1 || ofld_cong_drop > 2) {
570 		printf("Invalid hw.cxgbe.ofld_cong_drop value (%d),"
571 		    " using 0 instead.\n", ofld_cong_drop);
572 		ofld_cong_drop = 0;
573 	}
574 #endif
575 
576 	if (tscale != 1 && (tscale < 3 || tscale > 17)) {
577 		printf("Invalid hw.cxgbe.tscale value (%d),"
578 		    " using 1 instead.\n", tscale);
579 		tscale = 1;
580 	}
581 
582 	if (largest_rx_cluster != MCLBYTES &&
583 	    largest_rx_cluster != MJUMPAGESIZE &&
584 	    largest_rx_cluster != MJUM9BYTES &&
585 	    largest_rx_cluster != MJUM16BYTES) {
586 		printf("Invalid hw.cxgbe.largest_rx_cluster value (%d),"
587 		    " using %d instead.\n", largest_rx_cluster, MJUM16BYTES);
588 		largest_rx_cluster = MJUM16BYTES;
589 	}
590 
591 	if (safest_rx_cluster != MCLBYTES &&
592 	    safest_rx_cluster != MJUMPAGESIZE &&
593 	    safest_rx_cluster != MJUM9BYTES &&
594 	    safest_rx_cluster != MJUM16BYTES) {
595 		printf("Invalid hw.cxgbe.safest_rx_cluster value (%d),"
596 		    " using %d instead.\n", safest_rx_cluster, MJUMPAGESIZE);
597 		safest_rx_cluster = MJUMPAGESIZE;
598 	}
599 
600 	extfree_refs = counter_u64_alloc(M_WAITOK);
601 	extfree_rels = counter_u64_alloc(M_WAITOK);
602 	pullups = counter_u64_alloc(M_WAITOK);
603 	defrags = counter_u64_alloc(M_WAITOK);
604 	counter_u64_zero(extfree_refs);
605 	counter_u64_zero(extfree_rels);
606 	counter_u64_zero(pullups);
607 	counter_u64_zero(defrags);
608 
609 	t4_init_shared_cpl_handlers();
610 	t4_register_cpl_handler(CPL_FW4_MSG, handle_fw_msg);
611 	t4_register_cpl_handler(CPL_FW6_MSG, handle_fw_msg);
612 	t4_register_cpl_handler(CPL_SGE_EGR_UPDATE, handle_sge_egr_update);
613 #ifdef RATELIMIT
614 	t4_register_shared_cpl_handler(CPL_FW4_ACK, ethofld_fw4_ack,
615 	    CPL_COOKIE_ETHOFLD);
616 #endif
617 	t4_register_fw_msg_handler(FW6_TYPE_CMD_RPL, t4_handle_fw_rpl);
618 	t4_register_fw_msg_handler(FW6_TYPE_WRERR_RPL, t4_handle_wrerr_rpl);
619 }
620 
621 void
622 t4_sge_modunload(void)
623 {
624 
625 	counter_u64_free(extfree_refs);
626 	counter_u64_free(extfree_rels);
627 	counter_u64_free(pullups);
628 	counter_u64_free(defrags);
629 }
630 
631 uint64_t
632 t4_sge_extfree_refs(void)
633 {
634 	uint64_t refs, rels;
635 
636 	rels = counter_u64_fetch(extfree_rels);
637 	refs = counter_u64_fetch(extfree_refs);
638 
639 	return (refs - rels);
640 }
641 
642 /* max 4096 */
643 #define MAX_PACK_BOUNDARY 512
644 
645 static inline void
646 setup_pad_and_pack_boundaries(struct adapter *sc)
647 {
648 	uint32_t v, m;
649 	int pad, pack, pad_shift;
650 
651 	pad_shift = chip_id(sc) > CHELSIO_T5 ? X_T6_INGPADBOUNDARY_SHIFT :
652 	    X_INGPADBOUNDARY_SHIFT;
653 	pad = fl_pad;
654 	if (fl_pad < (1 << pad_shift) ||
655 	    fl_pad > (1 << (pad_shift + M_INGPADBOUNDARY)) ||
656 	    !powerof2(fl_pad)) {
657 		/*
658 		 * If there is any chance that we might use buffer packing and
659 		 * the chip is a T4, then pick 64 as the pad/pack boundary.  Set
660 		 * it to the minimum allowed in all other cases.
661 		 */
662 		pad = is_t4(sc) && buffer_packing ? 64 : 1 << pad_shift;
663 
664 		/*
665 		 * For fl_pad = 0 we'll still write a reasonable value to the
666 		 * register but all the freelists will opt out of padding.
667 		 * We'll complain here only if the user tried to set it to a
668 		 * value greater than 0 that was invalid.
669 		 */
670 		if (fl_pad > 0) {
671 			device_printf(sc->dev, "Invalid hw.cxgbe.fl_pad value"
672 			    " (%d), using %d instead.\n", fl_pad, pad);
673 		}
674 	}
675 	m = V_INGPADBOUNDARY(M_INGPADBOUNDARY);
676 	v = V_INGPADBOUNDARY(ilog2(pad) - pad_shift);
677 	t4_set_reg_field(sc, A_SGE_CONTROL, m, v);
678 
679 	if (is_t4(sc)) {
680 		if (fl_pack != -1 && fl_pack != pad) {
681 			/* Complain but carry on. */
682 			device_printf(sc->dev, "hw.cxgbe.fl_pack (%d) ignored,"
683 			    " using %d instead.\n", fl_pack, pad);
684 		}
685 		return;
686 	}
687 
688 	pack = fl_pack;
689 	if (fl_pack < 16 || fl_pack == 32 || fl_pack > 4096 ||
690 	    !powerof2(fl_pack)) {
691 		if (sc->params.pci.mps > MAX_PACK_BOUNDARY)
692 			pack = MAX_PACK_BOUNDARY;
693 		else
694 			pack = max(sc->params.pci.mps, CACHE_LINE_SIZE);
695 		MPASS(powerof2(pack));
696 		if (pack < 16)
697 			pack = 16;
698 		if (pack == 32)
699 			pack = 64;
700 		if (pack > 4096)
701 			pack = 4096;
702 		if (fl_pack != -1) {
703 			device_printf(sc->dev, "Invalid hw.cxgbe.fl_pack value"
704 			    " (%d), using %d instead.\n", fl_pack, pack);
705 		}
706 	}
707 	m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY);
708 	if (pack == 16)
709 		v = V_INGPACKBOUNDARY(0);
710 	else
711 		v = V_INGPACKBOUNDARY(ilog2(pack) - 5);
712 
713 	MPASS(!is_t4(sc));	/* T4 doesn't have SGE_CONTROL2 */
714 	t4_set_reg_field(sc, A_SGE_CONTROL2, m, v);
715 }
716 
717 /*
718  * adap->params.vpd.cclk must be set up before this is called.
719  */
720 void
721 t4_tweak_chip_settings(struct adapter *sc)
722 {
723 	int i, reg;
724 	uint32_t v, m;
725 	int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200};
726 	int timer_max = M_TIMERVALUE0 * 1000 / sc->params.vpd.cclk;
727 	int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */
728 	uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE);
729 	static int sw_buf_sizes[] = {
730 		MCLBYTES,
731 		MJUMPAGESIZE,
732 		MJUM9BYTES,
733 		MJUM16BYTES
734 	};
735 
736 	KASSERT(sc->flags & MASTER_PF,
737 	    ("%s: trying to change chip settings when not master.", __func__));
738 
739 	m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE;
740 	v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE |
741 	    V_EGRSTATUSPAGESIZE(spg_len == 128);
742 	t4_set_reg_field(sc, A_SGE_CONTROL, m, v);
743 
744 	setup_pad_and_pack_boundaries(sc);
745 
746 	v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) |
747 	    V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) |
748 	    V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) |
749 	    V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) |
750 	    V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) |
751 	    V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) |
752 	    V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) |
753 	    V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10);
754 	t4_write_reg(sc, A_SGE_HOST_PAGE_SIZE, v);
755 
756 	t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0, 4096);
757 	t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE1, 65536);
758 	reg = A_SGE_FL_BUFFER_SIZE2;
759 	for (i = 0; i < nitems(sw_buf_sizes); i++) {
760 		MPASS(reg <= A_SGE_FL_BUFFER_SIZE15);
761 		t4_write_reg(sc, reg, sw_buf_sizes[i]);
762 		reg += 4;
763 		MPASS(reg <= A_SGE_FL_BUFFER_SIZE15);
764 		t4_write_reg(sc, reg, sw_buf_sizes[i] - CL_METADATA_SIZE);
765 		reg += 4;
766 	}
767 
768 	v = V_THRESHOLD_0(intr_pktcount[0]) | V_THRESHOLD_1(intr_pktcount[1]) |
769 	    V_THRESHOLD_2(intr_pktcount[2]) | V_THRESHOLD_3(intr_pktcount[3]);
770 	t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD, v);
771 
772 	KASSERT(intr_timer[0] <= timer_max,
773 	    ("%s: not a single usable timer (%d, %d)", __func__, intr_timer[0],
774 	    timer_max));
775 	for (i = 1; i < nitems(intr_timer); i++) {
776 		KASSERT(intr_timer[i] >= intr_timer[i - 1],
777 		    ("%s: timers not listed in increasing order (%d)",
778 		    __func__, i));
779 
780 		while (intr_timer[i] > timer_max) {
781 			if (i == nitems(intr_timer) - 1) {
782 				intr_timer[i] = timer_max;
783 				break;
784 			}
785 			intr_timer[i] += intr_timer[i - 1];
786 			intr_timer[i] /= 2;
787 		}
788 	}
789 
790 	v = V_TIMERVALUE0(us_to_core_ticks(sc, intr_timer[0])) |
791 	    V_TIMERVALUE1(us_to_core_ticks(sc, intr_timer[1]));
792 	t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1, v);
793 	v = V_TIMERVALUE2(us_to_core_ticks(sc, intr_timer[2])) |
794 	    V_TIMERVALUE3(us_to_core_ticks(sc, intr_timer[3]));
795 	t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3, v);
796 	v = V_TIMERVALUE4(us_to_core_ticks(sc, intr_timer[4])) |
797 	    V_TIMERVALUE5(us_to_core_ticks(sc, intr_timer[5]));
798 	t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5, v);
799 
800 	if (chip_id(sc) >= CHELSIO_T6) {
801 		m = V_TSCALE(M_TSCALE);
802 		if (tscale == 1)
803 			v = 0;
804 		else
805 			v = V_TSCALE(tscale - 2);
806 		t4_set_reg_field(sc, A_SGE_ITP_CONTROL, m, v);
807 
808 		if (sc->debug_flags & DF_DISABLE_TCB_CACHE) {
809 			m = V_RDTHRESHOLD(M_RDTHRESHOLD) | F_WRTHRTHRESHEN |
810 			    V_WRTHRTHRESH(M_WRTHRTHRESH);
811 			t4_tp_pio_read(sc, &v, 1, A_TP_CMM_CONFIG, 1);
812 			v &= ~m;
813 			v |= V_RDTHRESHOLD(1) | F_WRTHRTHRESHEN |
814 			    V_WRTHRTHRESH(16);
815 			t4_tp_pio_write(sc, &v, 1, A_TP_CMM_CONFIG, 1);
816 		}
817 	}
818 
819 	/* 4K, 16K, 64K, 256K DDP "page sizes" for TDDP */
820 	v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6);
821 	t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, v);
822 
823 	/*
824 	 * 4K, 8K, 16K, 64K DDP "page sizes" for iSCSI DDP.  These have been
825 	 * chosen with MAXPHYS = 128K in mind.  The largest DDP buffer that we
826 	 * may have to deal with is MAXPHYS + 1 page.
827 	 */
828 	v = V_HPZ0(0) | V_HPZ1(1) | V_HPZ2(2) | V_HPZ3(4);
829 	t4_write_reg(sc, A_ULP_RX_ISCSI_PSZ, v);
830 
831 	/* We use multiple DDP page sizes both in plain-TOE and ISCSI modes. */
832 	m = v = F_TDDPTAGTCB | F_ISCSITAGTCB;
833 	t4_set_reg_field(sc, A_ULP_RX_CTL, m, v);
834 
835 	m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET |
836 	    F_RESETDDPOFFSET;
837 	v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET;
838 	t4_set_reg_field(sc, A_TP_PARA_REG5, m, v);
839 }
840 
841 /*
842  * SGE wants the buffer to be at least 64B and then a multiple of 16.  Its
843  * address mut be 16B aligned.  If padding is in use the buffer's start and end
844  * need to be aligned to the pad boundary as well.  We'll just make sure that
845  * the size is a multiple of the pad boundary here, it is up to the buffer
846  * allocation code to make sure the start of the buffer is aligned.
847  */
848 static inline int
849 hwsz_ok(struct adapter *sc, int hwsz)
850 {
851 	int mask = fl_pad ? sc->params.sge.pad_boundary - 1 : 16 - 1;
852 
853 	return (hwsz >= 64 && (hwsz & mask) == 0);
854 }
855 
856 /*
857  * Initialize the rx buffer sizes and figure out which zones the buffers will
858  * be allocated from.
859  */
860 void
861 t4_init_rx_buf_info(struct adapter *sc)
862 {
863 	struct sge *s = &sc->sge;
864 	struct sge_params *sp = &sc->params.sge;
865 	int i, j, n;
866 	static int sw_buf_sizes[] = {	/* Sorted by size */
867 		MCLBYTES,
868 		MJUMPAGESIZE,
869 		MJUM9BYTES,
870 		MJUM16BYTES
871 	};
872 	struct rx_buf_info *rxb;
873 
874 	s->safe_zidx = -1;
875 	rxb = &s->rx_buf_info[0];
876 	for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) {
877 		rxb->size1 = sw_buf_sizes[i];
878 		rxb->zone = m_getzone(rxb->size1);
879 		rxb->type = m_gettype(rxb->size1);
880 		rxb->size2 = 0;
881 		rxb->hwidx1 = -1;
882 		rxb->hwidx2 = -1;
883 		for (j = 0; j < SGE_FLBUF_SIZES; j++) {
884 			int hwsize = sp->sge_fl_buffer_size[j];
885 
886 			if (!hwsz_ok(sc, hwsize))
887 				continue;
888 
889 			/* hwidx for size1 */
890 			if (rxb->hwidx1 == -1 && rxb->size1 == hwsize)
891 				rxb->hwidx1 = j;
892 
893 			/* hwidx for size2 (buffer packing) */
894 			if (rxb->size1 - CL_METADATA_SIZE < hwsize)
895 				continue;
896 			n = rxb->size1 - hwsize - CL_METADATA_SIZE;
897 			if (n == 0) {
898 				rxb->hwidx2 = j;
899 				rxb->size2 = hwsize;
900 				break;	/* stop looking */
901 			}
902 			if (rxb->hwidx2 != -1) {
903 				if (n < sp->sge_fl_buffer_size[rxb->hwidx2] -
904 				    hwsize - CL_METADATA_SIZE) {
905 					rxb->hwidx2 = j;
906 					rxb->size2 = hwsize;
907 				}
908 			} else if (n <= 2 * CL_METADATA_SIZE) {
909 				rxb->hwidx2 = j;
910 				rxb->size2 = hwsize;
911 			}
912 		}
913 		if (rxb->hwidx2 != -1)
914 			sc->flags |= BUF_PACKING_OK;
915 		if (s->safe_zidx == -1 && rxb->size1 == safest_rx_cluster)
916 			s->safe_zidx = i;
917 	}
918 }
919 
920 /*
921  * Verify some basic SGE settings for the PF and VF driver, and other
922  * miscellaneous settings for the PF driver.
923  */
924 int
925 t4_verify_chip_settings(struct adapter *sc)
926 {
927 	struct sge_params *sp = &sc->params.sge;
928 	uint32_t m, v, r;
929 	int rc = 0;
930 	const uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE);
931 
932 	m = F_RXPKTCPLMODE;
933 	v = F_RXPKTCPLMODE;
934 	r = sp->sge_control;
935 	if ((r & m) != v) {
936 		device_printf(sc->dev, "invalid SGE_CONTROL(0x%x)\n", r);
937 		rc = EINVAL;
938 	}
939 
940 	/*
941 	 * If this changes then every single use of PAGE_SHIFT in the driver
942 	 * needs to be carefully reviewed for PAGE_SHIFT vs sp->page_shift.
943 	 */
944 	if (sp->page_shift != PAGE_SHIFT) {
945 		device_printf(sc->dev, "invalid SGE_HOST_PAGE_SIZE(0x%x)\n", r);
946 		rc = EINVAL;
947 	}
948 
949 	if (sc->flags & IS_VF)
950 		return (0);
951 
952 	v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6);
953 	r = t4_read_reg(sc, A_ULP_RX_TDDP_PSZ);
954 	if (r != v) {
955 		device_printf(sc->dev, "invalid ULP_RX_TDDP_PSZ(0x%x)\n", r);
956 		if (sc->vres.ddp.size != 0)
957 			rc = EINVAL;
958 	}
959 
960 	m = v = F_TDDPTAGTCB;
961 	r = t4_read_reg(sc, A_ULP_RX_CTL);
962 	if ((r & m) != v) {
963 		device_printf(sc->dev, "invalid ULP_RX_CTL(0x%x)\n", r);
964 		if (sc->vres.ddp.size != 0)
965 			rc = EINVAL;
966 	}
967 
968 	m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET |
969 	    F_RESETDDPOFFSET;
970 	v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET;
971 	r = t4_read_reg(sc, A_TP_PARA_REG5);
972 	if ((r & m) != v) {
973 		device_printf(sc->dev, "invalid TP_PARA_REG5(0x%x)\n", r);
974 		if (sc->vres.ddp.size != 0)
975 			rc = EINVAL;
976 	}
977 
978 	return (rc);
979 }
980 
981 int
982 t4_create_dma_tag(struct adapter *sc)
983 {
984 	int rc;
985 
986 	rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0,
987 	    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE,
988 	    BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL,
989 	    NULL, &sc->dmat);
990 	if (rc != 0) {
991 		device_printf(sc->dev,
992 		    "failed to create main DMA tag: %d\n", rc);
993 	}
994 
995 	return (rc);
996 }
997 
998 void
999 t4_sge_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx,
1000     struct sysctl_oid_list *children)
1001 {
1002 	struct sge_params *sp = &sc->params.sge;
1003 
1004 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "buffer_sizes",
1005 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
1006 	    sysctl_bufsizes, "A", "freelist buffer sizes");
1007 
1008 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pktshift", CTLFLAG_RD,
1009 	    NULL, sp->fl_pktshift, "payload DMA offset in rx buffer (bytes)");
1010 
1011 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pad", CTLFLAG_RD,
1012 	    NULL, sp->pad_boundary, "payload pad boundary (bytes)");
1013 
1014 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "spg_len", CTLFLAG_RD,
1015 	    NULL, sp->spg_len, "status page size (bytes)");
1016 
1017 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_drop", CTLFLAG_RD,
1018 	    NULL, cong_drop, "congestion drop setting");
1019 #ifdef TCP_OFFLOAD
1020 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ofld_cong_drop", CTLFLAG_RD,
1021 	    NULL, ofld_cong_drop, "congestion drop setting");
1022 #endif
1023 
1024 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pack", CTLFLAG_RD,
1025 	    NULL, sp->pack_boundary, "payload pack boundary (bytes)");
1026 }
1027 
1028 int
1029 t4_destroy_dma_tag(struct adapter *sc)
1030 {
1031 	if (sc->dmat)
1032 		bus_dma_tag_destroy(sc->dmat);
1033 
1034 	return (0);
1035 }
1036 
1037 /*
1038  * Allocate and initialize the firmware event queue, control queues, and special
1039  * purpose rx queues owned by the adapter.
1040  *
1041  * Returns errno on failure.  Resources allocated up to that point may still be
1042  * allocated.  Caller is responsible for cleanup in case this function fails.
1043  */
1044 int
1045 t4_setup_adapter_queues(struct adapter *sc)
1046 {
1047 	int rc, i;
1048 
1049 	ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
1050 
1051 	/*
1052 	 * Firmware event queue
1053 	 */
1054 	rc = alloc_fwq(sc);
1055 	if (rc != 0)
1056 		return (rc);
1057 
1058 	/*
1059 	 * That's all for the VF driver.
1060 	 */
1061 	if (sc->flags & IS_VF)
1062 		return (rc);
1063 
1064 	/*
1065 	 * XXX: General purpose rx queues, one per port.
1066 	 */
1067 
1068 	/*
1069 	 * Control queues, one per port.
1070 	 */
1071 	for_each_port(sc, i) {
1072 		rc = alloc_ctrlq(sc, i);
1073 		if (rc != 0)
1074 			return (rc);
1075 	}
1076 
1077 	return (rc);
1078 }
1079 
1080 /*
1081  * Idempotent
1082  */
1083 int
1084 t4_teardown_adapter_queues(struct adapter *sc)
1085 {
1086 	int i;
1087 
1088 	ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
1089 
1090 	if (sc->sge.ctrlq != NULL) {
1091 		MPASS(!(sc->flags & IS_VF));	/* VFs don't allocate ctrlq. */
1092 		for_each_port(sc, i)
1093 			free_ctrlq(sc, i);
1094 	}
1095 	free_fwq(sc);
1096 
1097 	return (0);
1098 }
1099 
1100 /* Maximum payload that could arrive with a single iq descriptor. */
1101 static inline int
1102 max_rx_payload(struct adapter *sc, struct ifnet *ifp, const bool ofld)
1103 {
1104 	int maxp;
1105 
1106 	/* large enough even when hw VLAN extraction is disabled */
1107 	maxp = sc->params.sge.fl_pktshift + ETHER_HDR_LEN +
1108 	    ETHER_VLAN_ENCAP_LEN + ifp->if_mtu;
1109 	if (ofld && sc->tt.tls && sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS &&
1110 	    maxp < sc->params.tp.max_rx_pdu)
1111 		maxp = sc->params.tp.max_rx_pdu;
1112 	return (maxp);
1113 }
1114 
1115 int
1116 t4_setup_vi_queues(struct vi_info *vi)
1117 {
1118 	int rc = 0, i, intr_idx;
1119 	struct sge_rxq *rxq;
1120 	struct sge_txq *txq;
1121 #ifdef TCP_OFFLOAD
1122 	struct sge_ofld_rxq *ofld_rxq;
1123 #endif
1124 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1125 	struct sge_ofld_txq *ofld_txq;
1126 #endif
1127 #ifdef DEV_NETMAP
1128 	int saved_idx, iqidx;
1129 	struct sge_nm_rxq *nm_rxq;
1130 	struct sge_nm_txq *nm_txq;
1131 #endif
1132 	struct adapter *sc = vi->adapter;
1133 	struct ifnet *ifp = vi->ifp;
1134 	int maxp;
1135 
1136 	/* Interrupt vector to start from (when using multiple vectors) */
1137 	intr_idx = vi->first_intr;
1138 
1139 #ifdef DEV_NETMAP
1140 	saved_idx = intr_idx;
1141 	if (ifp->if_capabilities & IFCAP_NETMAP) {
1142 
1143 		/* netmap is supported with direct interrupts only. */
1144 		MPASS(!forwarding_intr_to_fwq(sc));
1145 		MPASS(vi->first_intr >= 0);
1146 
1147 		/*
1148 		 * We don't have buffers to back the netmap rx queues
1149 		 * right now so we create the queues in a way that
1150 		 * doesn't set off any congestion signal in the chip.
1151 		 */
1152 		for_each_nm_rxq(vi, i, nm_rxq) {
1153 			rc = alloc_nm_rxq(vi, nm_rxq, intr_idx, i);
1154 			if (rc != 0)
1155 				goto done;
1156 			intr_idx++;
1157 		}
1158 
1159 		for_each_nm_txq(vi, i, nm_txq) {
1160 			iqidx = vi->first_nm_rxq + (i % vi->nnmrxq);
1161 			rc = alloc_nm_txq(vi, nm_txq, iqidx, i);
1162 			if (rc != 0)
1163 				goto done;
1164 		}
1165 	}
1166 
1167 	/* Normal rx queues and netmap rx queues share the same interrupts. */
1168 	intr_idx = saved_idx;
1169 #endif
1170 
1171 	/*
1172 	 * Allocate rx queues first because a default iqid is required when
1173 	 * creating a tx queue.
1174 	 */
1175 	maxp = max_rx_payload(sc, ifp, false);
1176 	for_each_rxq(vi, i, rxq) {
1177 		rc = alloc_rxq(vi, rxq, i, intr_idx, maxp);
1178 		if (rc != 0)
1179 			goto done;
1180 		if (!forwarding_intr_to_fwq(sc))
1181 			intr_idx++;
1182 	}
1183 #ifdef DEV_NETMAP
1184 	if (ifp->if_capabilities & IFCAP_NETMAP)
1185 		intr_idx = saved_idx + max(vi->nrxq, vi->nnmrxq);
1186 #endif
1187 #ifdef TCP_OFFLOAD
1188 	maxp = max_rx_payload(sc, ifp, true);
1189 	for_each_ofld_rxq(vi, i, ofld_rxq) {
1190 		rc = alloc_ofld_rxq(vi, ofld_rxq, i, intr_idx, maxp);
1191 		if (rc != 0)
1192 			goto done;
1193 		if (!forwarding_intr_to_fwq(sc))
1194 			intr_idx++;
1195 	}
1196 #endif
1197 
1198 	/*
1199 	 * Now the tx queues.
1200 	 */
1201 	for_each_txq(vi, i, txq) {
1202 		rc = alloc_txq(vi, txq, i);
1203 		if (rc != 0)
1204 			goto done;
1205 	}
1206 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1207 	for_each_ofld_txq(vi, i, ofld_txq) {
1208 		rc = alloc_ofld_txq(vi, ofld_txq, i);
1209 		if (rc != 0)
1210 			goto done;
1211 	}
1212 #endif
1213 done:
1214 	if (rc)
1215 		t4_teardown_vi_queues(vi);
1216 
1217 	return (rc);
1218 }
1219 
1220 /*
1221  * Idempotent
1222  */
1223 int
1224 t4_teardown_vi_queues(struct vi_info *vi)
1225 {
1226 	int i;
1227 	struct sge_rxq *rxq;
1228 	struct sge_txq *txq;
1229 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1230 	struct sge_ofld_txq *ofld_txq;
1231 #endif
1232 #ifdef TCP_OFFLOAD
1233 	struct sge_ofld_rxq *ofld_rxq;
1234 #endif
1235 #ifdef DEV_NETMAP
1236 	struct sge_nm_rxq *nm_rxq;
1237 	struct sge_nm_txq *nm_txq;
1238 #endif
1239 
1240 #ifdef DEV_NETMAP
1241 	if (vi->ifp->if_capabilities & IFCAP_NETMAP) {
1242 		for_each_nm_txq(vi, i, nm_txq) {
1243 			free_nm_txq(vi, nm_txq);
1244 		}
1245 
1246 		for_each_nm_rxq(vi, i, nm_rxq) {
1247 			free_nm_rxq(vi, nm_rxq);
1248 		}
1249 	}
1250 #endif
1251 
1252 	/*
1253 	 * Take down all the tx queues first, as they reference the rx queues
1254 	 * (for egress updates, etc.).
1255 	 */
1256 
1257 	for_each_txq(vi, i, txq) {
1258 		free_txq(vi, txq);
1259 	}
1260 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1261 	for_each_ofld_txq(vi, i, ofld_txq) {
1262 		free_ofld_txq(vi, ofld_txq);
1263 	}
1264 #endif
1265 
1266 	/*
1267 	 * Then take down the rx queues.
1268 	 */
1269 
1270 	for_each_rxq(vi, i, rxq) {
1271 		free_rxq(vi, rxq);
1272 	}
1273 #ifdef TCP_OFFLOAD
1274 	for_each_ofld_rxq(vi, i, ofld_rxq) {
1275 		free_ofld_rxq(vi, ofld_rxq);
1276 	}
1277 #endif
1278 
1279 	return (0);
1280 }
1281 
1282 /*
1283  * Interrupt handler when the driver is using only 1 interrupt.  This is a very
1284  * unusual scenario.
1285  *
1286  * a) Deals with errors, if any.
1287  * b) Services firmware event queue, which is taking interrupts for all other
1288  *    queues.
1289  */
1290 void
1291 t4_intr_all(void *arg)
1292 {
1293 	struct adapter *sc = arg;
1294 	struct sge_iq *fwq = &sc->sge.fwq;
1295 
1296 	MPASS(sc->intr_count == 1);
1297 
1298 	if (sc->intr_type == INTR_INTX)
1299 		t4_write_reg(sc, MYPF_REG(A_PCIE_PF_CLI), 0);
1300 
1301 	t4_intr_err(arg);
1302 	t4_intr_evt(fwq);
1303 }
1304 
1305 /*
1306  * Interrupt handler for errors (installed directly when multiple interrupts are
1307  * being used, or called by t4_intr_all).
1308  */
1309 void
1310 t4_intr_err(void *arg)
1311 {
1312 	struct adapter *sc = arg;
1313 	uint32_t v;
1314 	const bool verbose = (sc->debug_flags & DF_VERBOSE_SLOWINTR) != 0;
1315 
1316 	if (atomic_load_int(&sc->error_flags) & ADAP_FATAL_ERR)
1317 		return;
1318 
1319 	v = t4_read_reg(sc, MYPF_REG(A_PL_PF_INT_CAUSE));
1320 	if (v & F_PFSW) {
1321 		sc->swintr++;
1322 		t4_write_reg(sc, MYPF_REG(A_PL_PF_INT_CAUSE), v);
1323 	}
1324 
1325 	if (t4_slow_intr_handler(sc, verbose))
1326 		t4_fatal_err(sc, false);
1327 }
1328 
1329 /*
1330  * Interrupt handler for iq-only queues.  The firmware event queue is the only
1331  * such queue right now.
1332  */
1333 void
1334 t4_intr_evt(void *arg)
1335 {
1336 	struct sge_iq *iq = arg;
1337 
1338 	if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) {
1339 		service_iq(iq, 0);
1340 		(void) atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE);
1341 	}
1342 }
1343 
1344 /*
1345  * Interrupt handler for iq+fl queues.
1346  */
1347 void
1348 t4_intr(void *arg)
1349 {
1350 	struct sge_iq *iq = arg;
1351 
1352 	if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) {
1353 		service_iq_fl(iq, 0);
1354 		(void) atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE);
1355 	}
1356 }
1357 
1358 #ifdef DEV_NETMAP
1359 /*
1360  * Interrupt handler for netmap rx queues.
1361  */
1362 void
1363 t4_nm_intr(void *arg)
1364 {
1365 	struct sge_nm_rxq *nm_rxq = arg;
1366 
1367 	if (atomic_cmpset_int(&nm_rxq->nm_state, NM_ON, NM_BUSY)) {
1368 		service_nm_rxq(nm_rxq);
1369 		(void) atomic_cmpset_int(&nm_rxq->nm_state, NM_BUSY, NM_ON);
1370 	}
1371 }
1372 
1373 /*
1374  * Interrupt handler for vectors shared between NIC and netmap rx queues.
1375  */
1376 void
1377 t4_vi_intr(void *arg)
1378 {
1379 	struct irq *irq = arg;
1380 
1381 	MPASS(irq->nm_rxq != NULL);
1382 	t4_nm_intr(irq->nm_rxq);
1383 
1384 	MPASS(irq->rxq != NULL);
1385 	t4_intr(irq->rxq);
1386 }
1387 #endif
1388 
1389 /*
1390  * Deals with interrupts on an iq-only (no freelist) queue.
1391  */
1392 static int
1393 service_iq(struct sge_iq *iq, int budget)
1394 {
1395 	struct sge_iq *q;
1396 	struct adapter *sc = iq->adapter;
1397 	struct iq_desc *d = &iq->desc[iq->cidx];
1398 	int ndescs = 0, limit;
1399 	int rsp_type;
1400 	uint32_t lq;
1401 	STAILQ_HEAD(, sge_iq) iql = STAILQ_HEAD_INITIALIZER(iql);
1402 
1403 	KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq));
1404 	KASSERT((iq->flags & IQ_HAS_FL) == 0,
1405 	    ("%s: called for iq %p with fl (iq->flags 0x%x)", __func__, iq,
1406 	    iq->flags));
1407 	MPASS((iq->flags & IQ_ADJ_CREDIT) == 0);
1408 	MPASS((iq->flags & IQ_LRO_ENABLED) == 0);
1409 
1410 	limit = budget ? budget : iq->qsize / 16;
1411 
1412 	/*
1413 	 * We always come back and check the descriptor ring for new indirect
1414 	 * interrupts and other responses after running a single handler.
1415 	 */
1416 	for (;;) {
1417 		while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) {
1418 
1419 			rmb();
1420 
1421 			rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen);
1422 			lq = be32toh(d->rsp.pldbuflen_qid);
1423 
1424 			switch (rsp_type) {
1425 			case X_RSPD_TYPE_FLBUF:
1426 				panic("%s: data for an iq (%p) with no freelist",
1427 				    __func__, iq);
1428 
1429 				/* NOTREACHED */
1430 
1431 			case X_RSPD_TYPE_CPL:
1432 				KASSERT(d->rss.opcode < NUM_CPL_CMDS,
1433 				    ("%s: bad opcode %02x.", __func__,
1434 				    d->rss.opcode));
1435 				t4_cpl_handler[d->rss.opcode](iq, &d->rss, NULL);
1436 				break;
1437 
1438 			case X_RSPD_TYPE_INTR:
1439 				/*
1440 				 * There are 1K interrupt-capable queues (qids 0
1441 				 * through 1023).  A response type indicating a
1442 				 * forwarded interrupt with a qid >= 1K is an
1443 				 * iWARP async notification.
1444 				 */
1445 				if (__predict_true(lq >= 1024)) {
1446 					t4_an_handler(iq, &d->rsp);
1447 					break;
1448 				}
1449 
1450 				q = sc->sge.iqmap[lq - sc->sge.iq_start -
1451 				    sc->sge.iq_base];
1452 				if (atomic_cmpset_int(&q->state, IQS_IDLE,
1453 				    IQS_BUSY)) {
1454 					if (service_iq_fl(q, q->qsize / 16) == 0) {
1455 						(void) atomic_cmpset_int(&q->state,
1456 						    IQS_BUSY, IQS_IDLE);
1457 					} else {
1458 						STAILQ_INSERT_TAIL(&iql, q,
1459 						    link);
1460 					}
1461 				}
1462 				break;
1463 
1464 			default:
1465 				KASSERT(0,
1466 				    ("%s: illegal response type %d on iq %p",
1467 				    __func__, rsp_type, iq));
1468 				log(LOG_ERR,
1469 				    "%s: illegal response type %d on iq %p",
1470 				    device_get_nameunit(sc->dev), rsp_type, iq);
1471 				break;
1472 			}
1473 
1474 			d++;
1475 			if (__predict_false(++iq->cidx == iq->sidx)) {
1476 				iq->cidx = 0;
1477 				iq->gen ^= F_RSPD_GEN;
1478 				d = &iq->desc[0];
1479 			}
1480 			if (__predict_false(++ndescs == limit)) {
1481 				t4_write_reg(sc, sc->sge_gts_reg,
1482 				    V_CIDXINC(ndescs) |
1483 				    V_INGRESSQID(iq->cntxt_id) |
1484 				    V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX)));
1485 				ndescs = 0;
1486 
1487 				if (budget) {
1488 					return (EINPROGRESS);
1489 				}
1490 			}
1491 		}
1492 
1493 		if (STAILQ_EMPTY(&iql))
1494 			break;
1495 
1496 		/*
1497 		 * Process the head only, and send it to the back of the list if
1498 		 * it's still not done.
1499 		 */
1500 		q = STAILQ_FIRST(&iql);
1501 		STAILQ_REMOVE_HEAD(&iql, link);
1502 		if (service_iq_fl(q, q->qsize / 8) == 0)
1503 			(void) atomic_cmpset_int(&q->state, IQS_BUSY, IQS_IDLE);
1504 		else
1505 			STAILQ_INSERT_TAIL(&iql, q, link);
1506 	}
1507 
1508 	t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) |
1509 	    V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params));
1510 
1511 	return (0);
1512 }
1513 
1514 #if defined(INET) || defined(INET6)
1515 static inline int
1516 sort_before_lro(struct lro_ctrl *lro)
1517 {
1518 
1519 	return (lro->lro_mbuf_max != 0);
1520 }
1521 #endif
1522 
1523 static inline uint64_t
1524 last_flit_to_ns(struct adapter *sc, uint64_t lf)
1525 {
1526 	uint64_t n = be64toh(lf) & 0xfffffffffffffff;	/* 60b, not 64b. */
1527 
1528 	if (n > UINT64_MAX / 1000000)
1529 		return (n / sc->params.vpd.cclk * 1000000);
1530 	else
1531 		return (n * 1000000 / sc->params.vpd.cclk);
1532 }
1533 
1534 static inline void
1535 move_to_next_rxbuf(struct sge_fl *fl)
1536 {
1537 
1538 	fl->rx_offset = 0;
1539 	if (__predict_false((++fl->cidx & 7) == 0)) {
1540 		uint16_t cidx = fl->cidx >> 3;
1541 
1542 		if (__predict_false(cidx == fl->sidx))
1543 			fl->cidx = cidx = 0;
1544 		fl->hw_cidx = cidx;
1545 	}
1546 }
1547 
1548 /*
1549  * Deals with interrupts on an iq+fl queue.
1550  */
1551 static int
1552 service_iq_fl(struct sge_iq *iq, int budget)
1553 {
1554 	struct sge_rxq *rxq = iq_to_rxq(iq);
1555 	struct sge_fl *fl;
1556 	struct adapter *sc = iq->adapter;
1557 	struct iq_desc *d = &iq->desc[iq->cidx];
1558 	int ndescs, limit;
1559 	int rsp_type, starved;
1560 	uint32_t lq;
1561 	uint16_t fl_hw_cidx;
1562 	struct mbuf *m0;
1563 #if defined(INET) || defined(INET6)
1564 	const struct timeval lro_timeout = {0, sc->lro_timeout};
1565 	struct lro_ctrl *lro = &rxq->lro;
1566 #endif
1567 
1568 	KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq));
1569 	MPASS(iq->flags & IQ_HAS_FL);
1570 
1571 	ndescs = 0;
1572 #if defined(INET) || defined(INET6)
1573 	if (iq->flags & IQ_ADJ_CREDIT) {
1574 		MPASS(sort_before_lro(lro));
1575 		iq->flags &= ~IQ_ADJ_CREDIT;
1576 		if ((d->rsp.u.type_gen & F_RSPD_GEN) != iq->gen) {
1577 			tcp_lro_flush_all(lro);
1578 			t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(1) |
1579 			    V_INGRESSQID((u32)iq->cntxt_id) |
1580 			    V_SEINTARM(iq->intr_params));
1581 			return (0);
1582 		}
1583 		ndescs = 1;
1584 	}
1585 #else
1586 	MPASS((iq->flags & IQ_ADJ_CREDIT) == 0);
1587 #endif
1588 
1589 	limit = budget ? budget : iq->qsize / 16;
1590 	fl = &rxq->fl;
1591 	fl_hw_cidx = fl->hw_cidx;	/* stable snapshot */
1592 	while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) {
1593 
1594 		rmb();
1595 
1596 		m0 = NULL;
1597 		rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen);
1598 		lq = be32toh(d->rsp.pldbuflen_qid);
1599 
1600 		switch (rsp_type) {
1601 		case X_RSPD_TYPE_FLBUF:
1602 			if (lq & F_RSPD_NEWBUF) {
1603 				if (fl->rx_offset > 0)
1604 					move_to_next_rxbuf(fl);
1605 				lq = G_RSPD_LEN(lq);
1606 			}
1607 			if (IDXDIFF(fl->hw_cidx, fl_hw_cidx, fl->sidx) > 4) {
1608 				FL_LOCK(fl);
1609 				refill_fl(sc, fl, 64);
1610 				FL_UNLOCK(fl);
1611 				fl_hw_cidx = fl->hw_cidx;
1612 			}
1613 
1614 			if (d->rss.opcode == CPL_RX_PKT) {
1615 				if (__predict_true(eth_rx(sc, rxq, d, lq) == 0))
1616 					break;
1617 				goto out;
1618 			}
1619 			m0 = get_fl_payload(sc, fl, lq);
1620 			if (__predict_false(m0 == NULL))
1621 				goto out;
1622 
1623 			/* fall through */
1624 
1625 		case X_RSPD_TYPE_CPL:
1626 			KASSERT(d->rss.opcode < NUM_CPL_CMDS,
1627 			    ("%s: bad opcode %02x.", __func__, d->rss.opcode));
1628 			t4_cpl_handler[d->rss.opcode](iq, &d->rss, m0);
1629 			break;
1630 
1631 		case X_RSPD_TYPE_INTR:
1632 
1633 			/*
1634 			 * There are 1K interrupt-capable queues (qids 0
1635 			 * through 1023).  A response type indicating a
1636 			 * forwarded interrupt with a qid >= 1K is an
1637 			 * iWARP async notification.  That is the only
1638 			 * acceptable indirect interrupt on this queue.
1639 			 */
1640 			if (__predict_false(lq < 1024)) {
1641 				panic("%s: indirect interrupt on iq_fl %p "
1642 				    "with qid %u", __func__, iq, lq);
1643 			}
1644 
1645 			t4_an_handler(iq, &d->rsp);
1646 			break;
1647 
1648 		default:
1649 			KASSERT(0, ("%s: illegal response type %d on iq %p",
1650 			    __func__, rsp_type, iq));
1651 			log(LOG_ERR, "%s: illegal response type %d on iq %p",
1652 			    device_get_nameunit(sc->dev), rsp_type, iq);
1653 			break;
1654 		}
1655 
1656 		d++;
1657 		if (__predict_false(++iq->cidx == iq->sidx)) {
1658 			iq->cidx = 0;
1659 			iq->gen ^= F_RSPD_GEN;
1660 			d = &iq->desc[0];
1661 		}
1662 		if (__predict_false(++ndescs == limit)) {
1663 			t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) |
1664 			    V_INGRESSQID(iq->cntxt_id) |
1665 			    V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX)));
1666 
1667 #if defined(INET) || defined(INET6)
1668 			if (iq->flags & IQ_LRO_ENABLED &&
1669 			    !sort_before_lro(lro) &&
1670 			    sc->lro_timeout != 0) {
1671 				tcp_lro_flush_inactive(lro, &lro_timeout);
1672 			}
1673 #endif
1674 			if (budget)
1675 				return (EINPROGRESS);
1676 			ndescs = 0;
1677 		}
1678 	}
1679 out:
1680 #if defined(INET) || defined(INET6)
1681 	if (iq->flags & IQ_LRO_ENABLED) {
1682 		if (ndescs > 0 && lro->lro_mbuf_count > 8) {
1683 			MPASS(sort_before_lro(lro));
1684 			/* hold back one credit and don't flush LRO state */
1685 			iq->flags |= IQ_ADJ_CREDIT;
1686 			ndescs--;
1687 		} else {
1688 			tcp_lro_flush_all(lro);
1689 		}
1690 	}
1691 #endif
1692 
1693 	t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) |
1694 	    V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params));
1695 
1696 	FL_LOCK(fl);
1697 	starved = refill_fl(sc, fl, 64);
1698 	FL_UNLOCK(fl);
1699 	if (__predict_false(starved != 0))
1700 		add_fl_to_sfl(sc, fl);
1701 
1702 	return (0);
1703 }
1704 
1705 static inline struct cluster_metadata *
1706 cl_metadata(struct fl_sdesc *sd)
1707 {
1708 
1709 	return ((void *)(sd->cl + sd->moff));
1710 }
1711 
1712 static void
1713 rxb_free(struct mbuf *m)
1714 {
1715 	struct cluster_metadata *clm = m->m_ext.ext_arg1;
1716 
1717 	uma_zfree(clm->zone, clm->cl);
1718 	counter_u64_add(extfree_rels, 1);
1719 }
1720 
1721 /*
1722  * The mbuf returned comes from zone_muf and carries the payload in one of these
1723  * ways
1724  * a) complete frame inside the mbuf
1725  * b) m_cljset (for clusters without metadata)
1726  * d) m_extaddref (cluster with metadata)
1727  */
1728 static struct mbuf *
1729 get_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset,
1730     int remaining)
1731 {
1732 	struct mbuf *m;
1733 	struct fl_sdesc *sd = &fl->sdesc[fl->cidx];
1734 	struct rx_buf_info *rxb = &sc->sge.rx_buf_info[sd->zidx];
1735 	struct cluster_metadata *clm;
1736 	int len, blen;
1737 	caddr_t payload;
1738 
1739 	if (fl->flags & FL_BUF_PACKING) {
1740 		u_int l, pad;
1741 
1742 		blen = rxb->size2 - fl->rx_offset;	/* max possible in this buf */
1743 		len = min(remaining, blen);
1744 		payload = sd->cl + fl->rx_offset;
1745 
1746 		l = fr_offset + len;
1747 		pad = roundup2(l, fl->buf_boundary) - l;
1748 		if (fl->rx_offset + len + pad < rxb->size2)
1749 			blen = len + pad;
1750 		MPASS(fl->rx_offset + blen <= rxb->size2);
1751 	} else {
1752 		MPASS(fl->rx_offset == 0);	/* not packing */
1753 		blen = rxb->size1;
1754 		len = min(remaining, blen);
1755 		payload = sd->cl;
1756 	}
1757 
1758 	if (fr_offset == 0) {
1759 		m = m_gethdr(M_NOWAIT, MT_DATA);
1760 		if (__predict_false(m == NULL))
1761 			return (NULL);
1762 		m->m_pkthdr.len = remaining;
1763 	} else {
1764 		m = m_get(M_NOWAIT, MT_DATA);
1765 		if (__predict_false(m == NULL))
1766 			return (NULL);
1767 	}
1768 	m->m_len = len;
1769 	kmsan_mark(payload, len, KMSAN_STATE_INITED);
1770 
1771 	if (sc->sc_do_rxcopy && len < RX_COPY_THRESHOLD) {
1772 		/* copy data to mbuf */
1773 		bcopy(payload, mtod(m, caddr_t), len);
1774 		if (fl->flags & FL_BUF_PACKING) {
1775 			fl->rx_offset += blen;
1776 			MPASS(fl->rx_offset <= rxb->size2);
1777 			if (fl->rx_offset < rxb->size2)
1778 				return (m);	/* without advancing the cidx */
1779 		}
1780 	} else if (fl->flags & FL_BUF_PACKING) {
1781 		clm = cl_metadata(sd);
1782 		if (sd->nmbuf++ == 0) {
1783 			clm->refcount = 1;
1784 			clm->zone = rxb->zone;
1785 			clm->cl = sd->cl;
1786 			counter_u64_add(extfree_refs, 1);
1787 		}
1788 		m_extaddref(m, payload, blen, &clm->refcount, rxb_free, clm,
1789 		    NULL);
1790 
1791 		fl->rx_offset += blen;
1792 		MPASS(fl->rx_offset <= rxb->size2);
1793 		if (fl->rx_offset < rxb->size2)
1794 			return (m);	/* without advancing the cidx */
1795 	} else {
1796 		m_cljset(m, sd->cl, rxb->type);
1797 		sd->cl = NULL;	/* consumed, not a recycle candidate */
1798 	}
1799 
1800 	move_to_next_rxbuf(fl);
1801 
1802 	return (m);
1803 }
1804 
1805 static struct mbuf *
1806 get_fl_payload(struct adapter *sc, struct sge_fl *fl, const u_int plen)
1807 {
1808 	struct mbuf *m0, *m, **pnext;
1809 	u_int remaining;
1810 
1811 	if (__predict_false(fl->flags & FL_BUF_RESUME)) {
1812 		M_ASSERTPKTHDR(fl->m0);
1813 		MPASS(fl->m0->m_pkthdr.len == plen);
1814 		MPASS(fl->remaining < plen);
1815 
1816 		m0 = fl->m0;
1817 		pnext = fl->pnext;
1818 		remaining = fl->remaining;
1819 		fl->flags &= ~FL_BUF_RESUME;
1820 		goto get_segment;
1821 	}
1822 
1823 	/*
1824 	 * Payload starts at rx_offset in the current hw buffer.  Its length is
1825 	 * 'len' and it may span multiple hw buffers.
1826 	 */
1827 
1828 	m0 = get_scatter_segment(sc, fl, 0, plen);
1829 	if (m0 == NULL)
1830 		return (NULL);
1831 	remaining = plen - m0->m_len;
1832 	pnext = &m0->m_next;
1833 	while (remaining > 0) {
1834 get_segment:
1835 		MPASS(fl->rx_offset == 0);
1836 		m = get_scatter_segment(sc, fl, plen - remaining, remaining);
1837 		if (__predict_false(m == NULL)) {
1838 			fl->m0 = m0;
1839 			fl->pnext = pnext;
1840 			fl->remaining = remaining;
1841 			fl->flags |= FL_BUF_RESUME;
1842 			return (NULL);
1843 		}
1844 		*pnext = m;
1845 		pnext = &m->m_next;
1846 		remaining -= m->m_len;
1847 	}
1848 	*pnext = NULL;
1849 
1850 	M_ASSERTPKTHDR(m0);
1851 	return (m0);
1852 }
1853 
1854 static int
1855 skip_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset,
1856     int remaining)
1857 {
1858 	struct fl_sdesc *sd = &fl->sdesc[fl->cidx];
1859 	struct rx_buf_info *rxb = &sc->sge.rx_buf_info[sd->zidx];
1860 	int len, blen;
1861 
1862 	if (fl->flags & FL_BUF_PACKING) {
1863 		u_int l, pad;
1864 
1865 		blen = rxb->size2 - fl->rx_offset;	/* max possible in this buf */
1866 		len = min(remaining, blen);
1867 
1868 		l = fr_offset + len;
1869 		pad = roundup2(l, fl->buf_boundary) - l;
1870 		if (fl->rx_offset + len + pad < rxb->size2)
1871 			blen = len + pad;
1872 		fl->rx_offset += blen;
1873 		MPASS(fl->rx_offset <= rxb->size2);
1874 		if (fl->rx_offset < rxb->size2)
1875 			return (len);	/* without advancing the cidx */
1876 	} else {
1877 		MPASS(fl->rx_offset == 0);	/* not packing */
1878 		blen = rxb->size1;
1879 		len = min(remaining, blen);
1880 	}
1881 	move_to_next_rxbuf(fl);
1882 	return (len);
1883 }
1884 
1885 static inline void
1886 skip_fl_payload(struct adapter *sc, struct sge_fl *fl, int plen)
1887 {
1888 	int remaining, fr_offset, len;
1889 
1890 	fr_offset = 0;
1891 	remaining = plen;
1892 	while (remaining > 0) {
1893 		len = skip_scatter_segment(sc, fl, fr_offset, remaining);
1894 		fr_offset += len;
1895 		remaining -= len;
1896 	}
1897 }
1898 
1899 static inline int
1900 get_segment_len(struct adapter *sc, struct sge_fl *fl, int plen)
1901 {
1902 	int len;
1903 	struct fl_sdesc *sd = &fl->sdesc[fl->cidx];
1904 	struct rx_buf_info *rxb = &sc->sge.rx_buf_info[sd->zidx];
1905 
1906 	if (fl->flags & FL_BUF_PACKING)
1907 		len = rxb->size2 - fl->rx_offset;
1908 	else
1909 		len = rxb->size1;
1910 
1911 	return (min(plen, len));
1912 }
1913 
1914 static int
1915 eth_rx(struct adapter *sc, struct sge_rxq *rxq, const struct iq_desc *d,
1916     u_int plen)
1917 {
1918 	struct mbuf *m0;
1919 	struct ifnet *ifp = rxq->ifp;
1920 	struct sge_fl *fl = &rxq->fl;
1921 	struct vi_info *vi = ifp->if_softc;
1922 	const struct cpl_rx_pkt *cpl;
1923 #if defined(INET) || defined(INET6)
1924 	struct lro_ctrl *lro = &rxq->lro;
1925 #endif
1926 	uint16_t err_vec, tnl_type, tnlhdr_len;
1927 	static const int sw_hashtype[4][2] = {
1928 		{M_HASHTYPE_NONE, M_HASHTYPE_NONE},
1929 		{M_HASHTYPE_RSS_IPV4, M_HASHTYPE_RSS_IPV6},
1930 		{M_HASHTYPE_RSS_TCP_IPV4, M_HASHTYPE_RSS_TCP_IPV6},
1931 		{M_HASHTYPE_RSS_UDP_IPV4, M_HASHTYPE_RSS_UDP_IPV6},
1932 	};
1933 	static const int sw_csum_flags[2][2] = {
1934 		{
1935 			/* IP, inner IP */
1936 			CSUM_ENCAP_VXLAN |
1937 			    CSUM_L3_CALC | CSUM_L3_VALID |
1938 			    CSUM_L4_CALC | CSUM_L4_VALID |
1939 			    CSUM_INNER_L3_CALC | CSUM_INNER_L3_VALID |
1940 			    CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID,
1941 
1942 			/* IP, inner IP6 */
1943 			CSUM_ENCAP_VXLAN |
1944 			    CSUM_L3_CALC | CSUM_L3_VALID |
1945 			    CSUM_L4_CALC | CSUM_L4_VALID |
1946 			    CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID,
1947 		},
1948 		{
1949 			/* IP6, inner IP */
1950 			CSUM_ENCAP_VXLAN |
1951 			    CSUM_L4_CALC | CSUM_L4_VALID |
1952 			    CSUM_INNER_L3_CALC | CSUM_INNER_L3_VALID |
1953 			    CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID,
1954 
1955 			/* IP6, inner IP6 */
1956 			CSUM_ENCAP_VXLAN |
1957 			    CSUM_L4_CALC | CSUM_L4_VALID |
1958 			    CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID,
1959 		},
1960 	};
1961 
1962 	MPASS(plen > sc->params.sge.fl_pktshift);
1963 	if (vi->pfil != NULL && PFIL_HOOKED_IN(vi->pfil) &&
1964 	    __predict_true((fl->flags & FL_BUF_RESUME) == 0)) {
1965 		struct fl_sdesc *sd = &fl->sdesc[fl->cidx];
1966 		caddr_t frame;
1967 		int rc, slen;
1968 
1969 		slen = get_segment_len(sc, fl, plen) -
1970 		    sc->params.sge.fl_pktshift;
1971 		frame = sd->cl + fl->rx_offset + sc->params.sge.fl_pktshift;
1972 		CURVNET_SET_QUIET(ifp->if_vnet);
1973 		rc = pfil_run_hooks(vi->pfil, frame, ifp,
1974 		    slen | PFIL_MEMPTR | PFIL_IN, NULL);
1975 		CURVNET_RESTORE();
1976 		if (rc == PFIL_DROPPED || rc == PFIL_CONSUMED) {
1977 			skip_fl_payload(sc, fl, plen);
1978 			return (0);
1979 		}
1980 		if (rc == PFIL_REALLOCED) {
1981 			skip_fl_payload(sc, fl, plen);
1982 			m0 = pfil_mem2mbuf(frame);
1983 			goto have_mbuf;
1984 		}
1985 	}
1986 
1987 	m0 = get_fl_payload(sc, fl, plen);
1988 	if (__predict_false(m0 == NULL))
1989 		return (ENOMEM);
1990 
1991 	m0->m_pkthdr.len -= sc->params.sge.fl_pktshift;
1992 	m0->m_len -= sc->params.sge.fl_pktshift;
1993 	m0->m_data += sc->params.sge.fl_pktshift;
1994 
1995 have_mbuf:
1996 	m0->m_pkthdr.rcvif = ifp;
1997 	M_HASHTYPE_SET(m0, sw_hashtype[d->rss.hash_type][d->rss.ipv6]);
1998 	m0->m_pkthdr.flowid = be32toh(d->rss.hash_val);
1999 
2000 	cpl = (const void *)(&d->rss + 1);
2001 	if (sc->params.tp.rx_pkt_encap) {
2002 		const uint16_t ev = be16toh(cpl->err_vec);
2003 
2004 		err_vec = G_T6_COMPR_RXERR_VEC(ev);
2005 		tnl_type = G_T6_RX_TNL_TYPE(ev);
2006 		tnlhdr_len = G_T6_RX_TNLHDR_LEN(ev);
2007 	} else {
2008 		err_vec = be16toh(cpl->err_vec);
2009 		tnl_type = 0;
2010 		tnlhdr_len = 0;
2011 	}
2012 	if (cpl->csum_calc && err_vec == 0) {
2013 		int ipv6 = !!(cpl->l2info & htobe32(F_RXF_IP6));
2014 
2015 		/* checksum(s) calculated and found to be correct. */
2016 
2017 		MPASS((cpl->l2info & htobe32(F_RXF_IP)) ^
2018 		    (cpl->l2info & htobe32(F_RXF_IP6)));
2019 		m0->m_pkthdr.csum_data = be16toh(cpl->csum);
2020 		if (tnl_type == 0) {
2021 	    		if (!ipv6 && ifp->if_capenable & IFCAP_RXCSUM) {
2022 				m0->m_pkthdr.csum_flags = CSUM_L3_CALC |
2023 				    CSUM_L3_VALID | CSUM_L4_CALC |
2024 				    CSUM_L4_VALID;
2025 			} else if (ipv6 && ifp->if_capenable & IFCAP_RXCSUM_IPV6) {
2026 				m0->m_pkthdr.csum_flags = CSUM_L4_CALC |
2027 				    CSUM_L4_VALID;
2028 			}
2029 			rxq->rxcsum++;
2030 		} else {
2031 			MPASS(tnl_type == RX_PKT_TNL_TYPE_VXLAN);
2032 
2033 			M_HASHTYPE_SETINNER(m0);
2034 			if (__predict_false(cpl->ip_frag)) {
2035 				/*
2036 				 * csum_data is for the inner frame (which is an
2037 				 * IP fragment) and is not 0xffff.  There is no
2038 				 * way to pass the inner csum_data to the stack.
2039 				 * We don't want the stack to use the inner
2040 				 * csum_data to validate the outer frame or it
2041 				 * will get rejected.  So we fix csum_data here
2042 				 * and let sw do the checksum of inner IP
2043 				 * fragments.
2044 				 *
2045 				 * XXX: Need 32b for csum_data2 in an rx mbuf.
2046 				 * Maybe stuff it into rcv_tstmp?
2047 				 */
2048 				m0->m_pkthdr.csum_data = 0xffff;
2049 				if (ipv6) {
2050 					m0->m_pkthdr.csum_flags = CSUM_L4_CALC |
2051 					    CSUM_L4_VALID;
2052 				} else {
2053 					m0->m_pkthdr.csum_flags = CSUM_L3_CALC |
2054 					    CSUM_L3_VALID | CSUM_L4_CALC |
2055 					    CSUM_L4_VALID;
2056 				}
2057 			} else {
2058 				int outer_ipv6;
2059 
2060 				MPASS(m0->m_pkthdr.csum_data == 0xffff);
2061 
2062 				outer_ipv6 = tnlhdr_len >=
2063 				    sizeof(struct ether_header) +
2064 				    sizeof(struct ip6_hdr);
2065 				m0->m_pkthdr.csum_flags =
2066 				    sw_csum_flags[outer_ipv6][ipv6];
2067 			}
2068 			rxq->vxlan_rxcsum++;
2069 		}
2070 	}
2071 
2072 	if (cpl->vlan_ex) {
2073 		m0->m_pkthdr.ether_vtag = be16toh(cpl->vlan);
2074 		m0->m_flags |= M_VLANTAG;
2075 		rxq->vlan_extraction++;
2076 	}
2077 
2078 	if (rxq->iq.flags & IQ_RX_TIMESTAMP) {
2079 		/*
2080 		 * Fill up rcv_tstmp but do not set M_TSTMP.
2081 		 * rcv_tstmp is not in the format that the
2082 		 * kernel expects and we don't want to mislead
2083 		 * it.  For now this is only for custom code
2084 		 * that knows how to interpret cxgbe's stamp.
2085 		 */
2086 		m0->m_pkthdr.rcv_tstmp =
2087 		    last_flit_to_ns(sc, d->rsp.u.last_flit);
2088 #ifdef notyet
2089 		m0->m_flags |= M_TSTMP;
2090 #endif
2091 	}
2092 
2093 #ifdef NUMA
2094 	m0->m_pkthdr.numa_domain = ifp->if_numa_domain;
2095 #endif
2096 #if defined(INET) || defined(INET6)
2097 	if (rxq->iq.flags & IQ_LRO_ENABLED && tnl_type == 0 &&
2098 	    (M_HASHTYPE_GET(m0) == M_HASHTYPE_RSS_TCP_IPV4 ||
2099 	    M_HASHTYPE_GET(m0) == M_HASHTYPE_RSS_TCP_IPV6)) {
2100 		if (sort_before_lro(lro)) {
2101 			tcp_lro_queue_mbuf(lro, m0);
2102 			return (0); /* queued for sort, then LRO */
2103 		}
2104 		if (tcp_lro_rx(lro, m0, 0) == 0)
2105 			return (0); /* queued for LRO */
2106 	}
2107 #endif
2108 	ifp->if_input(ifp, m0);
2109 
2110 	return (0);
2111 }
2112 
2113 /*
2114  * Must drain the wrq or make sure that someone else will.
2115  */
2116 static void
2117 wrq_tx_drain(void *arg, int n)
2118 {
2119 	struct sge_wrq *wrq = arg;
2120 	struct sge_eq *eq = &wrq->eq;
2121 
2122 	EQ_LOCK(eq);
2123 	if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list))
2124 		drain_wrq_wr_list(wrq->adapter, wrq);
2125 	EQ_UNLOCK(eq);
2126 }
2127 
2128 static void
2129 drain_wrq_wr_list(struct adapter *sc, struct sge_wrq *wrq)
2130 {
2131 	struct sge_eq *eq = &wrq->eq;
2132 	u_int available, dbdiff;	/* # of hardware descriptors */
2133 	u_int n;
2134 	struct wrqe *wr;
2135 	struct fw_eth_tx_pkt_wr *dst;	/* any fw WR struct will do */
2136 
2137 	EQ_LOCK_ASSERT_OWNED(eq);
2138 	MPASS(TAILQ_EMPTY(&wrq->incomplete_wrs));
2139 	wr = STAILQ_FIRST(&wrq->wr_list);
2140 	MPASS(wr != NULL);	/* Must be called with something useful to do */
2141 	MPASS(eq->pidx == eq->dbidx);
2142 	dbdiff = 0;
2143 
2144 	do {
2145 		eq->cidx = read_hw_cidx(eq);
2146 		if (eq->pidx == eq->cidx)
2147 			available = eq->sidx - 1;
2148 		else
2149 			available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
2150 
2151 		MPASS(wr->wrq == wrq);
2152 		n = howmany(wr->wr_len, EQ_ESIZE);
2153 		if (available < n)
2154 			break;
2155 
2156 		dst = (void *)&eq->desc[eq->pidx];
2157 		if (__predict_true(eq->sidx - eq->pidx > n)) {
2158 			/* Won't wrap, won't end exactly at the status page. */
2159 			bcopy(&wr->wr[0], dst, wr->wr_len);
2160 			eq->pidx += n;
2161 		} else {
2162 			int first_portion = (eq->sidx - eq->pidx) * EQ_ESIZE;
2163 
2164 			bcopy(&wr->wr[0], dst, first_portion);
2165 			if (wr->wr_len > first_portion) {
2166 				bcopy(&wr->wr[first_portion], &eq->desc[0],
2167 				    wr->wr_len - first_portion);
2168 			}
2169 			eq->pidx = n - (eq->sidx - eq->pidx);
2170 		}
2171 		wrq->tx_wrs_copied++;
2172 
2173 		if (available < eq->sidx / 4 &&
2174 		    atomic_cmpset_int(&eq->equiq, 0, 1)) {
2175 				/*
2176 				 * XXX: This is not 100% reliable with some
2177 				 * types of WRs.  But this is a very unusual
2178 				 * situation for an ofld/ctrl queue anyway.
2179 				 */
2180 			dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ |
2181 			    F_FW_WR_EQUEQ);
2182 		}
2183 
2184 		dbdiff += n;
2185 		if (dbdiff >= 16) {
2186 			ring_eq_db(sc, eq, dbdiff);
2187 			dbdiff = 0;
2188 		}
2189 
2190 		STAILQ_REMOVE_HEAD(&wrq->wr_list, link);
2191 		free_wrqe(wr);
2192 		MPASS(wrq->nwr_pending > 0);
2193 		wrq->nwr_pending--;
2194 		MPASS(wrq->ndesc_needed >= n);
2195 		wrq->ndesc_needed -= n;
2196 	} while ((wr = STAILQ_FIRST(&wrq->wr_list)) != NULL);
2197 
2198 	if (dbdiff)
2199 		ring_eq_db(sc, eq, dbdiff);
2200 }
2201 
2202 /*
2203  * Doesn't fail.  Holds on to work requests it can't send right away.
2204  */
2205 void
2206 t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, struct wrqe *wr)
2207 {
2208 #ifdef INVARIANTS
2209 	struct sge_eq *eq = &wrq->eq;
2210 #endif
2211 
2212 	EQ_LOCK_ASSERT_OWNED(eq);
2213 	MPASS(wr != NULL);
2214 	MPASS(wr->wr_len > 0 && wr->wr_len <= SGE_MAX_WR_LEN);
2215 	MPASS((wr->wr_len & 0x7) == 0);
2216 
2217 	STAILQ_INSERT_TAIL(&wrq->wr_list, wr, link);
2218 	wrq->nwr_pending++;
2219 	wrq->ndesc_needed += howmany(wr->wr_len, EQ_ESIZE);
2220 
2221 	if (!TAILQ_EMPTY(&wrq->incomplete_wrs))
2222 		return;	/* commit_wrq_wr will drain wr_list as well. */
2223 
2224 	drain_wrq_wr_list(sc, wrq);
2225 
2226 	/* Doorbell must have caught up to the pidx. */
2227 	MPASS(eq->pidx == eq->dbidx);
2228 }
2229 
2230 void
2231 t4_update_fl_bufsize(struct ifnet *ifp)
2232 {
2233 	struct vi_info *vi = ifp->if_softc;
2234 	struct adapter *sc = vi->adapter;
2235 	struct sge_rxq *rxq;
2236 #ifdef TCP_OFFLOAD
2237 	struct sge_ofld_rxq *ofld_rxq;
2238 #endif
2239 	struct sge_fl *fl;
2240 	int i, maxp;
2241 
2242 	maxp = max_rx_payload(sc, ifp, false);
2243 	for_each_rxq(vi, i, rxq) {
2244 		fl = &rxq->fl;
2245 
2246 		FL_LOCK(fl);
2247 		fl->zidx = find_refill_source(sc, maxp,
2248 		    fl->flags & FL_BUF_PACKING);
2249 		FL_UNLOCK(fl);
2250 	}
2251 #ifdef TCP_OFFLOAD
2252 	maxp = max_rx_payload(sc, ifp, true);
2253 	for_each_ofld_rxq(vi, i, ofld_rxq) {
2254 		fl = &ofld_rxq->fl;
2255 
2256 		FL_LOCK(fl);
2257 		fl->zidx = find_refill_source(sc, maxp,
2258 		    fl->flags & FL_BUF_PACKING);
2259 		FL_UNLOCK(fl);
2260 	}
2261 #endif
2262 }
2263 
2264 static inline int
2265 mbuf_nsegs(struct mbuf *m)
2266 {
2267 
2268 	M_ASSERTPKTHDR(m);
2269 	KASSERT(m->m_pkthdr.inner_l5hlen > 0,
2270 	    ("%s: mbuf %p missing information on # of segments.", __func__, m));
2271 
2272 	return (m->m_pkthdr.inner_l5hlen);
2273 }
2274 
2275 static inline void
2276 set_mbuf_nsegs(struct mbuf *m, uint8_t nsegs)
2277 {
2278 
2279 	M_ASSERTPKTHDR(m);
2280 	m->m_pkthdr.inner_l5hlen = nsegs;
2281 }
2282 
2283 static inline int
2284 mbuf_cflags(struct mbuf *m)
2285 {
2286 
2287 	M_ASSERTPKTHDR(m);
2288 	return (m->m_pkthdr.PH_loc.eight[4]);
2289 }
2290 
2291 static inline void
2292 set_mbuf_cflags(struct mbuf *m, uint8_t flags)
2293 {
2294 
2295 	M_ASSERTPKTHDR(m);
2296 	m->m_pkthdr.PH_loc.eight[4] = flags;
2297 }
2298 
2299 static inline int
2300 mbuf_len16(struct mbuf *m)
2301 {
2302 	int n;
2303 
2304 	M_ASSERTPKTHDR(m);
2305 	n = m->m_pkthdr.PH_loc.eight[0];
2306 	if (!(mbuf_cflags(m) & MC_TLS))
2307 		MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16);
2308 
2309 	return (n);
2310 }
2311 
2312 static inline void
2313 set_mbuf_len16(struct mbuf *m, uint8_t len16)
2314 {
2315 
2316 	M_ASSERTPKTHDR(m);
2317 	if (!(mbuf_cflags(m) & MC_TLS))
2318 		MPASS(len16 > 0 && len16 <= SGE_MAX_WR_LEN / 16);
2319 	m->m_pkthdr.PH_loc.eight[0] = len16;
2320 }
2321 
2322 #ifdef RATELIMIT
2323 static inline int
2324 mbuf_eo_nsegs(struct mbuf *m)
2325 {
2326 
2327 	M_ASSERTPKTHDR(m);
2328 	return (m->m_pkthdr.PH_loc.eight[1]);
2329 }
2330 
2331 #if defined(INET) || defined(INET6)
2332 static inline void
2333 set_mbuf_eo_nsegs(struct mbuf *m, uint8_t nsegs)
2334 {
2335 
2336 	M_ASSERTPKTHDR(m);
2337 	m->m_pkthdr.PH_loc.eight[1] = nsegs;
2338 }
2339 #endif
2340 
2341 static inline int
2342 mbuf_eo_len16(struct mbuf *m)
2343 {
2344 	int n;
2345 
2346 	M_ASSERTPKTHDR(m);
2347 	n = m->m_pkthdr.PH_loc.eight[2];
2348 	MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16);
2349 
2350 	return (n);
2351 }
2352 
2353 #if defined(INET) || defined(INET6)
2354 static inline void
2355 set_mbuf_eo_len16(struct mbuf *m, uint8_t len16)
2356 {
2357 
2358 	M_ASSERTPKTHDR(m);
2359 	m->m_pkthdr.PH_loc.eight[2] = len16;
2360 }
2361 #endif
2362 
2363 static inline int
2364 mbuf_eo_tsclk_tsoff(struct mbuf *m)
2365 {
2366 
2367 	M_ASSERTPKTHDR(m);
2368 	return (m->m_pkthdr.PH_loc.eight[3]);
2369 }
2370 
2371 #if defined(INET) || defined(INET6)
2372 static inline void
2373 set_mbuf_eo_tsclk_tsoff(struct mbuf *m, uint8_t tsclk_tsoff)
2374 {
2375 
2376 	M_ASSERTPKTHDR(m);
2377 	m->m_pkthdr.PH_loc.eight[3] = tsclk_tsoff;
2378 }
2379 #endif
2380 
2381 static inline int
2382 needs_eo(struct m_snd_tag *mst)
2383 {
2384 
2385 	return (mst != NULL && mst->sw->type == IF_SND_TAG_TYPE_RATE_LIMIT);
2386 }
2387 #endif
2388 
2389 /*
2390  * Try to allocate an mbuf to contain a raw work request.  To make it
2391  * easy to construct the work request, don't allocate a chain but a
2392  * single mbuf.
2393  */
2394 struct mbuf *
2395 alloc_wr_mbuf(int len, int how)
2396 {
2397 	struct mbuf *m;
2398 
2399 	if (len <= MHLEN)
2400 		m = m_gethdr(how, MT_DATA);
2401 	else if (len <= MCLBYTES)
2402 		m = m_getcl(how, MT_DATA, M_PKTHDR);
2403 	else
2404 		m = NULL;
2405 	if (m == NULL)
2406 		return (NULL);
2407 	m->m_pkthdr.len = len;
2408 	m->m_len = len;
2409 	set_mbuf_cflags(m, MC_RAW_WR);
2410 	set_mbuf_len16(m, howmany(len, 16));
2411 	return (m);
2412 }
2413 
2414 static inline bool
2415 needs_hwcsum(struct mbuf *m)
2416 {
2417 	const uint32_t csum_flags = CSUM_IP | CSUM_IP_UDP | CSUM_IP_TCP |
2418 	    CSUM_IP_TSO | CSUM_INNER_IP | CSUM_INNER_IP_UDP |
2419 	    CSUM_INNER_IP_TCP | CSUM_INNER_IP_TSO | CSUM_IP6_UDP |
2420 	    CSUM_IP6_TCP | CSUM_IP6_TSO | CSUM_INNER_IP6_UDP |
2421 	    CSUM_INNER_IP6_TCP | CSUM_INNER_IP6_TSO;
2422 
2423 	M_ASSERTPKTHDR(m);
2424 
2425 	return (m->m_pkthdr.csum_flags & csum_flags);
2426 }
2427 
2428 static inline bool
2429 needs_tso(struct mbuf *m)
2430 {
2431 	const uint32_t csum_flags = CSUM_IP_TSO | CSUM_IP6_TSO |
2432 	    CSUM_INNER_IP_TSO | CSUM_INNER_IP6_TSO;
2433 
2434 	M_ASSERTPKTHDR(m);
2435 
2436 	return (m->m_pkthdr.csum_flags & csum_flags);
2437 }
2438 
2439 static inline bool
2440 needs_vxlan_csum(struct mbuf *m)
2441 {
2442 
2443 	M_ASSERTPKTHDR(m);
2444 
2445 	return (m->m_pkthdr.csum_flags & CSUM_ENCAP_VXLAN);
2446 }
2447 
2448 static inline bool
2449 needs_vxlan_tso(struct mbuf *m)
2450 {
2451 	const uint32_t csum_flags = CSUM_ENCAP_VXLAN | CSUM_INNER_IP_TSO |
2452 	    CSUM_INNER_IP6_TSO;
2453 
2454 	M_ASSERTPKTHDR(m);
2455 
2456 	return ((m->m_pkthdr.csum_flags & csum_flags) != 0 &&
2457 	    (m->m_pkthdr.csum_flags & csum_flags) != CSUM_ENCAP_VXLAN);
2458 }
2459 
2460 #if defined(INET) || defined(INET6)
2461 static inline bool
2462 needs_inner_tcp_csum(struct mbuf *m)
2463 {
2464 	const uint32_t csum_flags = CSUM_INNER_IP_TSO | CSUM_INNER_IP6_TSO;
2465 
2466 	M_ASSERTPKTHDR(m);
2467 
2468 	return (m->m_pkthdr.csum_flags & csum_flags);
2469 }
2470 #endif
2471 
2472 static inline bool
2473 needs_l3_csum(struct mbuf *m)
2474 {
2475 	const uint32_t csum_flags = CSUM_IP | CSUM_IP_TSO | CSUM_INNER_IP |
2476 	    CSUM_INNER_IP_TSO;
2477 
2478 	M_ASSERTPKTHDR(m);
2479 
2480 	return (m->m_pkthdr.csum_flags & csum_flags);
2481 }
2482 
2483 static inline bool
2484 needs_outer_tcp_csum(struct mbuf *m)
2485 {
2486 	const uint32_t csum_flags = CSUM_IP_TCP | CSUM_IP_TSO | CSUM_IP6_TCP |
2487 	    CSUM_IP6_TSO;
2488 
2489 	M_ASSERTPKTHDR(m);
2490 
2491 	return (m->m_pkthdr.csum_flags & csum_flags);
2492 }
2493 
2494 #ifdef RATELIMIT
2495 static inline bool
2496 needs_outer_l4_csum(struct mbuf *m)
2497 {
2498 	const uint32_t csum_flags = CSUM_IP_UDP | CSUM_IP_TCP | CSUM_IP_TSO |
2499 	    CSUM_IP6_UDP | CSUM_IP6_TCP | CSUM_IP6_TSO;
2500 
2501 	M_ASSERTPKTHDR(m);
2502 
2503 	return (m->m_pkthdr.csum_flags & csum_flags);
2504 }
2505 
2506 static inline bool
2507 needs_outer_udp_csum(struct mbuf *m)
2508 {
2509 	const uint32_t csum_flags = CSUM_IP_UDP | CSUM_IP6_UDP;
2510 
2511 	M_ASSERTPKTHDR(m);
2512 
2513 	return (m->m_pkthdr.csum_flags & csum_flags);
2514 }
2515 #endif
2516 
2517 static inline bool
2518 needs_vlan_insertion(struct mbuf *m)
2519 {
2520 
2521 	M_ASSERTPKTHDR(m);
2522 
2523 	return (m->m_flags & M_VLANTAG);
2524 }
2525 
2526 #if defined(INET) || defined(INET6)
2527 static void *
2528 m_advance(struct mbuf **pm, int *poffset, int len)
2529 {
2530 	struct mbuf *m = *pm;
2531 	int offset = *poffset;
2532 	uintptr_t p = 0;
2533 
2534 	MPASS(len > 0);
2535 
2536 	for (;;) {
2537 		if (offset + len < m->m_len) {
2538 			offset += len;
2539 			p = mtod(m, uintptr_t) + offset;
2540 			break;
2541 		}
2542 		len -= m->m_len - offset;
2543 		m = m->m_next;
2544 		offset = 0;
2545 		MPASS(m != NULL);
2546 	}
2547 	*poffset = offset;
2548 	*pm = m;
2549 	return ((void *)p);
2550 }
2551 #endif
2552 
2553 static inline int
2554 count_mbuf_ext_pgs(struct mbuf *m, int skip, vm_paddr_t *nextaddr)
2555 {
2556 	vm_paddr_t paddr;
2557 	int i, len, off, pglen, pgoff, seglen, segoff;
2558 	int nsegs = 0;
2559 
2560 	M_ASSERTEXTPG(m);
2561 	off = mtod(m, vm_offset_t);
2562 	len = m->m_len;
2563 	off += skip;
2564 	len -= skip;
2565 
2566 	if (m->m_epg_hdrlen != 0) {
2567 		if (off >= m->m_epg_hdrlen) {
2568 			off -= m->m_epg_hdrlen;
2569 		} else {
2570 			seglen = m->m_epg_hdrlen - off;
2571 			segoff = off;
2572 			seglen = min(seglen, len);
2573 			off = 0;
2574 			len -= seglen;
2575 			paddr = pmap_kextract(
2576 			    (vm_offset_t)&m->m_epg_hdr[segoff]);
2577 			if (*nextaddr != paddr)
2578 				nsegs++;
2579 			*nextaddr = paddr + seglen;
2580 		}
2581 	}
2582 	pgoff = m->m_epg_1st_off;
2583 	for (i = 0; i < m->m_epg_npgs && len > 0; i++) {
2584 		pglen = m_epg_pagelen(m, i, pgoff);
2585 		if (off >= pglen) {
2586 			off -= pglen;
2587 			pgoff = 0;
2588 			continue;
2589 		}
2590 		seglen = pglen - off;
2591 		segoff = pgoff + off;
2592 		off = 0;
2593 		seglen = min(seglen, len);
2594 		len -= seglen;
2595 		paddr = m->m_epg_pa[i] + segoff;
2596 		if (*nextaddr != paddr)
2597 			nsegs++;
2598 		*nextaddr = paddr + seglen;
2599 		pgoff = 0;
2600 	};
2601 	if (len != 0) {
2602 		seglen = min(len, m->m_epg_trllen - off);
2603 		len -= seglen;
2604 		paddr = pmap_kextract((vm_offset_t)&m->m_epg_trail[off]);
2605 		if (*nextaddr != paddr)
2606 			nsegs++;
2607 		*nextaddr = paddr + seglen;
2608 	}
2609 
2610 	return (nsegs);
2611 }
2612 
2613 
2614 /*
2615  * Can deal with empty mbufs in the chain that have m_len = 0, but the chain
2616  * must have at least one mbuf that's not empty.  It is possible for this
2617  * routine to return 0 if skip accounts for all the contents of the mbuf chain.
2618  */
2619 static inline int
2620 count_mbuf_nsegs(struct mbuf *m, int skip, uint8_t *cflags)
2621 {
2622 	vm_paddr_t nextaddr, paddr;
2623 	vm_offset_t va;
2624 	int len, nsegs;
2625 
2626 	M_ASSERTPKTHDR(m);
2627 	MPASS(m->m_pkthdr.len > 0);
2628 	MPASS(m->m_pkthdr.len >= skip);
2629 
2630 	nsegs = 0;
2631 	nextaddr = 0;
2632 	for (; m; m = m->m_next) {
2633 		len = m->m_len;
2634 		if (__predict_false(len == 0))
2635 			continue;
2636 		if (skip >= len) {
2637 			skip -= len;
2638 			continue;
2639 		}
2640 		if ((m->m_flags & M_EXTPG) != 0) {
2641 			*cflags |= MC_NOMAP;
2642 			nsegs += count_mbuf_ext_pgs(m, skip, &nextaddr);
2643 			skip = 0;
2644 			continue;
2645 		}
2646 		va = mtod(m, vm_offset_t) + skip;
2647 		len -= skip;
2648 		skip = 0;
2649 		paddr = pmap_kextract(va);
2650 		nsegs += sglist_count((void *)(uintptr_t)va, len);
2651 		if (paddr == nextaddr)
2652 			nsegs--;
2653 		nextaddr = pmap_kextract(va + len - 1) + 1;
2654 	}
2655 
2656 	return (nsegs);
2657 }
2658 
2659 /*
2660  * The maximum number of segments that can fit in a WR.
2661  */
2662 static int
2663 max_nsegs_allowed(struct mbuf *m, bool vm_wr)
2664 {
2665 
2666 	if (vm_wr) {
2667 		if (needs_tso(m))
2668 			return (TX_SGL_SEGS_VM_TSO);
2669 		return (TX_SGL_SEGS_VM);
2670 	}
2671 
2672 	if (needs_tso(m)) {
2673 		if (needs_vxlan_tso(m))
2674 			return (TX_SGL_SEGS_VXLAN_TSO);
2675 		else
2676 			return (TX_SGL_SEGS_TSO);
2677 	}
2678 
2679 	return (TX_SGL_SEGS);
2680 }
2681 
2682 static struct timeval txerr_ratecheck = {0};
2683 static const struct timeval txerr_interval = {3, 0};
2684 
2685 /*
2686  * Analyze the mbuf to determine its tx needs.  The mbuf passed in may change:
2687  * a) caller can assume it's been freed if this function returns with an error.
2688  * b) it may get defragged up if the gather list is too long for the hardware.
2689  */
2690 int
2691 parse_pkt(struct mbuf **mp, bool vm_wr)
2692 {
2693 	struct mbuf *m0 = *mp, *m;
2694 	int rc, nsegs, defragged = 0;
2695 	struct ether_header *eh;
2696 #ifdef INET
2697 	void *l3hdr;
2698 #endif
2699 #if defined(INET) || defined(INET6)
2700 	int offset;
2701 	struct tcphdr *tcp;
2702 #endif
2703 #if defined(KERN_TLS) || defined(RATELIMIT)
2704 	struct m_snd_tag *mst;
2705 #endif
2706 	uint16_t eh_type;
2707 	uint8_t cflags;
2708 
2709 	cflags = 0;
2710 	M_ASSERTPKTHDR(m0);
2711 	if (__predict_false(m0->m_pkthdr.len < ETHER_HDR_LEN)) {
2712 		rc = EINVAL;
2713 fail:
2714 		m_freem(m0);
2715 		*mp = NULL;
2716 		return (rc);
2717 	}
2718 restart:
2719 	/*
2720 	 * First count the number of gather list segments in the payload.
2721 	 * Defrag the mbuf if nsegs exceeds the hardware limit.
2722 	 */
2723 	M_ASSERTPKTHDR(m0);
2724 	MPASS(m0->m_pkthdr.len > 0);
2725 	nsegs = count_mbuf_nsegs(m0, 0, &cflags);
2726 #if defined(KERN_TLS) || defined(RATELIMIT)
2727 	if (m0->m_pkthdr.csum_flags & CSUM_SND_TAG)
2728 		mst = m0->m_pkthdr.snd_tag;
2729 	else
2730 		mst = NULL;
2731 #endif
2732 #ifdef KERN_TLS
2733 	if (mst != NULL && mst->sw->type == IF_SND_TAG_TYPE_TLS) {
2734 		int len16;
2735 
2736 		cflags |= MC_TLS;
2737 		set_mbuf_cflags(m0, cflags);
2738 		rc = t6_ktls_parse_pkt(m0, &nsegs, &len16);
2739 		if (rc != 0)
2740 			goto fail;
2741 		set_mbuf_nsegs(m0, nsegs);
2742 		set_mbuf_len16(m0, len16);
2743 		return (0);
2744 	}
2745 #endif
2746 	if (nsegs > max_nsegs_allowed(m0, vm_wr)) {
2747 		if (defragged++ > 0) {
2748 			rc = EFBIG;
2749 			goto fail;
2750 		}
2751 		counter_u64_add(defrags, 1);
2752 		if ((m = m_defrag(m0, M_NOWAIT)) == NULL) {
2753 			rc = ENOMEM;
2754 			goto fail;
2755 		}
2756 		*mp = m0 = m;	/* update caller's copy after defrag */
2757 		goto restart;
2758 	}
2759 
2760 	if (__predict_false(nsegs > 2 && m0->m_pkthdr.len <= MHLEN &&
2761 	    !(cflags & MC_NOMAP))) {
2762 		counter_u64_add(pullups, 1);
2763 		m0 = m_pullup(m0, m0->m_pkthdr.len);
2764 		if (m0 == NULL) {
2765 			/* Should have left well enough alone. */
2766 			rc = EFBIG;
2767 			goto fail;
2768 		}
2769 		*mp = m0;	/* update caller's copy after pullup */
2770 		goto restart;
2771 	}
2772 	set_mbuf_nsegs(m0, nsegs);
2773 	set_mbuf_cflags(m0, cflags);
2774 	calculate_mbuf_len16(m0, vm_wr);
2775 
2776 #ifdef RATELIMIT
2777 	/*
2778 	 * Ethofld is limited to TCP and UDP for now, and only when L4 hw
2779 	 * checksumming is enabled.  needs_outer_l4_csum happens to check for
2780 	 * all the right things.
2781 	 */
2782 	if (__predict_false(needs_eo(mst) && !needs_outer_l4_csum(m0))) {
2783 		m_snd_tag_rele(m0->m_pkthdr.snd_tag);
2784 		m0->m_pkthdr.snd_tag = NULL;
2785 		m0->m_pkthdr.csum_flags &= ~CSUM_SND_TAG;
2786 		mst = NULL;
2787 	}
2788 #endif
2789 
2790 	if (!needs_hwcsum(m0)
2791 #ifdef RATELIMIT
2792    		 && !needs_eo(mst)
2793 #endif
2794 	)
2795 		return (0);
2796 
2797 	m = m0;
2798 	eh = mtod(m, struct ether_header *);
2799 	eh_type = ntohs(eh->ether_type);
2800 	if (eh_type == ETHERTYPE_VLAN) {
2801 		struct ether_vlan_header *evh = (void *)eh;
2802 
2803 		eh_type = ntohs(evh->evl_proto);
2804 		m0->m_pkthdr.l2hlen = sizeof(*evh);
2805 	} else
2806 		m0->m_pkthdr.l2hlen = sizeof(*eh);
2807 
2808 #if defined(INET) || defined(INET6)
2809 	offset = 0;
2810 #ifdef INET
2811 	l3hdr = m_advance(&m, &offset, m0->m_pkthdr.l2hlen);
2812 #else
2813 	m_advance(&m, &offset, m0->m_pkthdr.l2hlen);
2814 #endif
2815 #endif
2816 
2817 	switch (eh_type) {
2818 #ifdef INET6
2819 	case ETHERTYPE_IPV6:
2820 		m0->m_pkthdr.l3hlen = sizeof(struct ip6_hdr);
2821 		break;
2822 #endif
2823 #ifdef INET
2824 	case ETHERTYPE_IP:
2825 	{
2826 		struct ip *ip = l3hdr;
2827 
2828 		if (needs_vxlan_csum(m0)) {
2829 			/* Driver will do the outer IP hdr checksum. */
2830 			ip->ip_sum = 0;
2831 			if (needs_vxlan_tso(m0)) {
2832 				const uint16_t ipl = ip->ip_len;
2833 
2834 				ip->ip_len = 0;
2835 				ip->ip_sum = ~in_cksum_hdr(ip);
2836 				ip->ip_len = ipl;
2837 			} else
2838 				ip->ip_sum = in_cksum_hdr(ip);
2839 		}
2840 		m0->m_pkthdr.l3hlen = ip->ip_hl << 2;
2841 		break;
2842 	}
2843 #endif
2844 	default:
2845 		if (ratecheck(&txerr_ratecheck, &txerr_interval)) {
2846 			log(LOG_ERR, "%s: ethertype 0x%04x unknown.  "
2847 			    "if_cxgbe must be compiled with the same "
2848 			    "INET/INET6 options as the kernel.\n", __func__,
2849 			    eh_type);
2850 		}
2851 		rc = EINVAL;
2852 		goto fail;
2853 	}
2854 
2855 #if defined(INET) || defined(INET6)
2856 	if (needs_vxlan_csum(m0)) {
2857 		m0->m_pkthdr.l4hlen = sizeof(struct udphdr);
2858 		m0->m_pkthdr.l5hlen = sizeof(struct vxlan_header);
2859 
2860 		/* Inner headers. */
2861 		eh = m_advance(&m, &offset, m0->m_pkthdr.l3hlen +
2862 		    sizeof(struct udphdr) + sizeof(struct vxlan_header));
2863 		eh_type = ntohs(eh->ether_type);
2864 		if (eh_type == ETHERTYPE_VLAN) {
2865 			struct ether_vlan_header *evh = (void *)eh;
2866 
2867 			eh_type = ntohs(evh->evl_proto);
2868 			m0->m_pkthdr.inner_l2hlen = sizeof(*evh);
2869 		} else
2870 			m0->m_pkthdr.inner_l2hlen = sizeof(*eh);
2871 #ifdef INET
2872 		l3hdr = m_advance(&m, &offset, m0->m_pkthdr.inner_l2hlen);
2873 #else
2874 		m_advance(&m, &offset, m0->m_pkthdr.inner_l2hlen);
2875 #endif
2876 
2877 		switch (eh_type) {
2878 #ifdef INET6
2879 		case ETHERTYPE_IPV6:
2880 			m0->m_pkthdr.inner_l3hlen = sizeof(struct ip6_hdr);
2881 			break;
2882 #endif
2883 #ifdef INET
2884 		case ETHERTYPE_IP:
2885 		{
2886 			struct ip *ip = l3hdr;
2887 
2888 			m0->m_pkthdr.inner_l3hlen = ip->ip_hl << 2;
2889 			break;
2890 		}
2891 #endif
2892 		default:
2893 			if (ratecheck(&txerr_ratecheck, &txerr_interval)) {
2894 				log(LOG_ERR, "%s: VXLAN hw offload requested"
2895 				    "with unknown ethertype 0x%04x.  if_cxgbe "
2896 				    "must be compiled with the same INET/INET6 "
2897 				    "options as the kernel.\n", __func__,
2898 				    eh_type);
2899 			}
2900 			rc = EINVAL;
2901 			goto fail;
2902 		}
2903 		if (needs_inner_tcp_csum(m0)) {
2904 			tcp = m_advance(&m, &offset, m0->m_pkthdr.inner_l3hlen);
2905 			m0->m_pkthdr.inner_l4hlen = tcp->th_off * 4;
2906 		}
2907 		MPASS((m0->m_pkthdr.csum_flags & CSUM_SND_TAG) == 0);
2908 		m0->m_pkthdr.csum_flags &= CSUM_INNER_IP6_UDP |
2909 		    CSUM_INNER_IP6_TCP | CSUM_INNER_IP6_TSO | CSUM_INNER_IP |
2910 		    CSUM_INNER_IP_UDP | CSUM_INNER_IP_TCP | CSUM_INNER_IP_TSO |
2911 		    CSUM_ENCAP_VXLAN;
2912 	}
2913 
2914 	if (needs_outer_tcp_csum(m0)) {
2915 		tcp = m_advance(&m, &offset, m0->m_pkthdr.l3hlen);
2916 		m0->m_pkthdr.l4hlen = tcp->th_off * 4;
2917 #ifdef RATELIMIT
2918 		if (tsclk >= 0 && *(uint32_t *)(tcp + 1) == ntohl(0x0101080a)) {
2919 			set_mbuf_eo_tsclk_tsoff(m0,
2920 			    V_FW_ETH_TX_EO_WR_TSCLK(tsclk) |
2921 			    V_FW_ETH_TX_EO_WR_TSOFF(sizeof(*tcp) / 2 + 1));
2922 		} else
2923 			set_mbuf_eo_tsclk_tsoff(m0, 0);
2924 	} else if (needs_outer_udp_csum(m0)) {
2925 		m0->m_pkthdr.l4hlen = sizeof(struct udphdr);
2926 #endif
2927 	}
2928 #ifdef RATELIMIT
2929 	if (needs_eo(mst)) {
2930 		u_int immhdrs;
2931 
2932 		/* EO WRs have the headers in the WR and not the GL. */
2933 		immhdrs = m0->m_pkthdr.l2hlen + m0->m_pkthdr.l3hlen +
2934 		    m0->m_pkthdr.l4hlen;
2935 		cflags = 0;
2936 		nsegs = count_mbuf_nsegs(m0, immhdrs, &cflags);
2937 		MPASS(cflags == mbuf_cflags(m0));
2938 		set_mbuf_eo_nsegs(m0, nsegs);
2939 		set_mbuf_eo_len16(m0,
2940 		    txpkt_eo_len16(nsegs, immhdrs, needs_tso(m0)));
2941 	}
2942 #endif
2943 #endif
2944 	MPASS(m0 == *mp);
2945 	return (0);
2946 }
2947 
2948 void *
2949 start_wrq_wr(struct sge_wrq *wrq, int len16, struct wrq_cookie *cookie)
2950 {
2951 	struct sge_eq *eq = &wrq->eq;
2952 	struct adapter *sc = wrq->adapter;
2953 	int ndesc, available;
2954 	struct wrqe *wr;
2955 	void *w;
2956 
2957 	MPASS(len16 > 0);
2958 	ndesc = tx_len16_to_desc(len16);
2959 	MPASS(ndesc > 0 && ndesc <= SGE_MAX_WR_NDESC);
2960 
2961 	EQ_LOCK(eq);
2962 
2963 	if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list))
2964 		drain_wrq_wr_list(sc, wrq);
2965 
2966 	if (!STAILQ_EMPTY(&wrq->wr_list)) {
2967 slowpath:
2968 		EQ_UNLOCK(eq);
2969 		wr = alloc_wrqe(len16 * 16, wrq);
2970 		if (__predict_false(wr == NULL))
2971 			return (NULL);
2972 		cookie->pidx = -1;
2973 		cookie->ndesc = ndesc;
2974 		return (&wr->wr);
2975 	}
2976 
2977 	eq->cidx = read_hw_cidx(eq);
2978 	if (eq->pidx == eq->cidx)
2979 		available = eq->sidx - 1;
2980 	else
2981 		available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
2982 	if (available < ndesc)
2983 		goto slowpath;
2984 
2985 	cookie->pidx = eq->pidx;
2986 	cookie->ndesc = ndesc;
2987 	TAILQ_INSERT_TAIL(&wrq->incomplete_wrs, cookie, link);
2988 
2989 	w = &eq->desc[eq->pidx];
2990 	IDXINCR(eq->pidx, ndesc, eq->sidx);
2991 	if (__predict_false(cookie->pidx + ndesc > eq->sidx)) {
2992 		w = &wrq->ss[0];
2993 		wrq->ss_pidx = cookie->pidx;
2994 		wrq->ss_len = len16 * 16;
2995 	}
2996 
2997 	EQ_UNLOCK(eq);
2998 
2999 	return (w);
3000 }
3001 
3002 void
3003 commit_wrq_wr(struct sge_wrq *wrq, void *w, struct wrq_cookie *cookie)
3004 {
3005 	struct sge_eq *eq = &wrq->eq;
3006 	struct adapter *sc = wrq->adapter;
3007 	int ndesc, pidx;
3008 	struct wrq_cookie *prev, *next;
3009 
3010 	if (cookie->pidx == -1) {
3011 		struct wrqe *wr = __containerof(w, struct wrqe, wr);
3012 
3013 		t4_wrq_tx(sc, wr);
3014 		return;
3015 	}
3016 
3017 	if (__predict_false(w == &wrq->ss[0])) {
3018 		int n = (eq->sidx - wrq->ss_pidx) * EQ_ESIZE;
3019 
3020 		MPASS(wrq->ss_len > n);	/* WR had better wrap around. */
3021 		bcopy(&wrq->ss[0], &eq->desc[wrq->ss_pidx], n);
3022 		bcopy(&wrq->ss[n], &eq->desc[0], wrq->ss_len - n);
3023 		wrq->tx_wrs_ss++;
3024 	} else
3025 		wrq->tx_wrs_direct++;
3026 
3027 	EQ_LOCK(eq);
3028 	ndesc = cookie->ndesc;	/* Can be more than SGE_MAX_WR_NDESC here. */
3029 	pidx = cookie->pidx;
3030 	MPASS(pidx >= 0 && pidx < eq->sidx);
3031 	prev = TAILQ_PREV(cookie, wrq_incomplete_wrs, link);
3032 	next = TAILQ_NEXT(cookie, link);
3033 	if (prev == NULL) {
3034 		MPASS(pidx == eq->dbidx);
3035 		if (next == NULL || ndesc >= 16) {
3036 			int available;
3037 			struct fw_eth_tx_pkt_wr *dst;	/* any fw WR struct will do */
3038 
3039 			/*
3040 			 * Note that the WR via which we'll request tx updates
3041 			 * is at pidx and not eq->pidx, which has moved on
3042 			 * already.
3043 			 */
3044 			dst = (void *)&eq->desc[pidx];
3045 			available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
3046 			if (available < eq->sidx / 4 &&
3047 			    atomic_cmpset_int(&eq->equiq, 0, 1)) {
3048 				/*
3049 				 * XXX: This is not 100% reliable with some
3050 				 * types of WRs.  But this is a very unusual
3051 				 * situation for an ofld/ctrl queue anyway.
3052 				 */
3053 				dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ |
3054 				    F_FW_WR_EQUEQ);
3055 			}
3056 
3057 			ring_eq_db(wrq->adapter, eq, ndesc);
3058 		} else {
3059 			MPASS(IDXDIFF(next->pidx, pidx, eq->sidx) == ndesc);
3060 			next->pidx = pidx;
3061 			next->ndesc += ndesc;
3062 		}
3063 	} else {
3064 		MPASS(IDXDIFF(pidx, prev->pidx, eq->sidx) == prev->ndesc);
3065 		prev->ndesc += ndesc;
3066 	}
3067 	TAILQ_REMOVE(&wrq->incomplete_wrs, cookie, link);
3068 
3069 	if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list))
3070 		drain_wrq_wr_list(sc, wrq);
3071 
3072 #ifdef INVARIANTS
3073 	if (TAILQ_EMPTY(&wrq->incomplete_wrs)) {
3074 		/* Doorbell must have caught up to the pidx. */
3075 		MPASS(wrq->eq.pidx == wrq->eq.dbidx);
3076 	}
3077 #endif
3078 	EQ_UNLOCK(eq);
3079 }
3080 
3081 static u_int
3082 can_resume_eth_tx(struct mp_ring *r)
3083 {
3084 	struct sge_eq *eq = r->cookie;
3085 
3086 	return (total_available_tx_desc(eq) > eq->sidx / 8);
3087 }
3088 
3089 static inline bool
3090 cannot_use_txpkts(struct mbuf *m)
3091 {
3092 	/* maybe put a GL limit too, to avoid silliness? */
3093 
3094 	return (needs_tso(m) || (mbuf_cflags(m) & (MC_RAW_WR | MC_TLS)) != 0);
3095 }
3096 
3097 static inline int
3098 discard_tx(struct sge_eq *eq)
3099 {
3100 
3101 	return ((eq->flags & (EQ_ENABLED | EQ_QFLUSH)) != EQ_ENABLED);
3102 }
3103 
3104 static inline int
3105 wr_can_update_eq(void *p)
3106 {
3107 	struct fw_eth_tx_pkts_wr *wr = p;
3108 
3109 	switch (G_FW_WR_OP(be32toh(wr->op_pkd))) {
3110 	case FW_ULPTX_WR:
3111 	case FW_ETH_TX_PKT_WR:
3112 	case FW_ETH_TX_PKTS_WR:
3113 	case FW_ETH_TX_PKTS2_WR:
3114 	case FW_ETH_TX_PKT_VM_WR:
3115 	case FW_ETH_TX_PKTS_VM_WR:
3116 		return (1);
3117 	default:
3118 		return (0);
3119 	}
3120 }
3121 
3122 static inline void
3123 set_txupdate_flags(struct sge_txq *txq, u_int avail,
3124     struct fw_eth_tx_pkt_wr *wr)
3125 {
3126 	struct sge_eq *eq = &txq->eq;
3127 	struct txpkts *txp = &txq->txp;
3128 
3129 	if ((txp->npkt > 0 || avail < eq->sidx / 2) &&
3130 	    atomic_cmpset_int(&eq->equiq, 0, 1)) {
3131 		wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ | F_FW_WR_EQUIQ);
3132 		eq->equeqidx = eq->pidx;
3133 	} else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 32) {
3134 		wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ);
3135 		eq->equeqidx = eq->pidx;
3136 	}
3137 }
3138 
3139 #if defined(__i386__) || defined(__amd64__)
3140 extern uint64_t tsc_freq;
3141 #endif
3142 
3143 static inline bool
3144 record_eth_tx_time(struct sge_txq *txq)
3145 {
3146 	const uint64_t cycles = get_cyclecount();
3147 	const uint64_t last_tx = txq->last_tx;
3148 #if defined(__i386__) || defined(__amd64__)
3149 	const uint64_t itg = tsc_freq * t4_tx_coalesce_gap / 1000000;
3150 #else
3151 	const uint64_t itg = 0;
3152 #endif
3153 
3154 	MPASS(cycles >= last_tx);
3155 	txq->last_tx = cycles;
3156 	return (cycles - last_tx < itg);
3157 }
3158 
3159 /*
3160  * r->items[cidx] to r->items[pidx], with a wraparound at r->size, are ready to
3161  * be consumed.  Return the actual number consumed.  0 indicates a stall.
3162  */
3163 static u_int
3164 eth_tx(struct mp_ring *r, u_int cidx, u_int pidx, bool *coalescing)
3165 {
3166 	struct sge_txq *txq = r->cookie;
3167 	struct ifnet *ifp = txq->ifp;
3168 	struct sge_eq *eq = &txq->eq;
3169 	struct txpkts *txp = &txq->txp;
3170 	struct vi_info *vi = ifp->if_softc;
3171 	struct adapter *sc = vi->adapter;
3172 	u_int total, remaining;		/* # of packets */
3173 	u_int n, avail, dbdiff;		/* # of hardware descriptors */
3174 	int i, rc;
3175 	struct mbuf *m0;
3176 	bool snd, recent_tx;
3177 	void *wr;	/* start of the last WR written to the ring */
3178 
3179 	TXQ_LOCK_ASSERT_OWNED(txq);
3180 	recent_tx = record_eth_tx_time(txq);
3181 
3182 	remaining = IDXDIFF(pidx, cidx, r->size);
3183 	if (__predict_false(discard_tx(eq))) {
3184 		for (i = 0; i < txp->npkt; i++)
3185 			m_freem(txp->mb[i]);
3186 		txp->npkt = 0;
3187 		while (cidx != pidx) {
3188 			m0 = r->items[cidx];
3189 			m_freem(m0);
3190 			if (++cidx == r->size)
3191 				cidx = 0;
3192 		}
3193 		reclaim_tx_descs(txq, eq->sidx);
3194 		*coalescing = false;
3195 		return (remaining);	/* emptied */
3196 	}
3197 
3198 	/* How many hardware descriptors do we have readily available. */
3199 	if (eq->pidx == eq->cidx)
3200 		avail = eq->sidx - 1;
3201 	else
3202 		avail = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
3203 
3204 	total = 0;
3205 	if (remaining == 0) {
3206 		txp->score = 0;
3207 		txq->txpkts_flush++;
3208 		goto send_txpkts;
3209 	}
3210 
3211 	dbdiff = 0;
3212 	MPASS(remaining > 0);
3213 	while (remaining > 0) {
3214 		m0 = r->items[cidx];
3215 		M_ASSERTPKTHDR(m0);
3216 		MPASS(m0->m_nextpkt == NULL);
3217 
3218 		if (avail < 2 * SGE_MAX_WR_NDESC)
3219 			avail += reclaim_tx_descs(txq, 64);
3220 
3221 		if (t4_tx_coalesce == 0 && txp->npkt == 0)
3222 			goto skip_coalescing;
3223 		if (cannot_use_txpkts(m0))
3224 			txp->score = 0;
3225 		else if (recent_tx) {
3226 			if (++txp->score == 0)
3227 				txp->score = UINT8_MAX;
3228 		} else
3229 			txp->score = 1;
3230 		if (txp->npkt > 0 || remaining > 1 ||
3231 		    txp->score >= t4_tx_coalesce_pkts ||
3232 		    atomic_load_int(&txq->eq.equiq) != 0) {
3233 			if (vi->flags & TX_USES_VM_WR)
3234 				rc = add_to_txpkts_vf(sc, txq, m0, avail, &snd);
3235 			else
3236 				rc = add_to_txpkts_pf(sc, txq, m0, avail, &snd);
3237 		} else {
3238 			snd = false;
3239 			rc = EINVAL;
3240 		}
3241 		if (snd) {
3242 			MPASS(txp->npkt > 0);
3243 			for (i = 0; i < txp->npkt; i++)
3244 				ETHER_BPF_MTAP(ifp, txp->mb[i]);
3245 			if (txp->npkt > 1) {
3246 				MPASS(avail >= tx_len16_to_desc(txp->len16));
3247 				if (vi->flags & TX_USES_VM_WR)
3248 					n = write_txpkts_vm_wr(sc, txq);
3249 				else
3250 					n = write_txpkts_wr(sc, txq);
3251 			} else {
3252 				MPASS(avail >=
3253 				    tx_len16_to_desc(mbuf_len16(txp->mb[0])));
3254 				if (vi->flags & TX_USES_VM_WR)
3255 					n = write_txpkt_vm_wr(sc, txq,
3256 					    txp->mb[0]);
3257 				else
3258 					n = write_txpkt_wr(sc, txq, txp->mb[0],
3259 					    avail);
3260 			}
3261 			MPASS(n <= SGE_MAX_WR_NDESC);
3262 			avail -= n;
3263 			dbdiff += n;
3264 			wr = &eq->desc[eq->pidx];
3265 			IDXINCR(eq->pidx, n, eq->sidx);
3266 			txp->npkt = 0;	/* emptied */
3267 		}
3268 		if (rc == 0) {
3269 			/* m0 was coalesced into txq->txpkts. */
3270 			goto next_mbuf;
3271 		}
3272 		if (rc == EAGAIN) {
3273 			/*
3274 			 * m0 is suitable for tx coalescing but could not be
3275 			 * combined with the existing txq->txpkts, which has now
3276 			 * been transmitted.  Start a new txpkts with m0.
3277 			 */
3278 			MPASS(snd);
3279 			MPASS(txp->npkt == 0);
3280 			continue;
3281 		}
3282 
3283 		MPASS(rc != 0 && rc != EAGAIN);
3284 		MPASS(txp->npkt == 0);
3285 skip_coalescing:
3286 		n = tx_len16_to_desc(mbuf_len16(m0));
3287 		if (__predict_false(avail < n)) {
3288 			avail += reclaim_tx_descs(txq, min(n, 32));
3289 			if (avail < n)
3290 				break;	/* out of descriptors */
3291 		}
3292 
3293 		wr = &eq->desc[eq->pidx];
3294 		if (mbuf_cflags(m0) & MC_RAW_WR) {
3295 			n = write_raw_wr(txq, wr, m0, avail);
3296 #ifdef KERN_TLS
3297 		} else if (mbuf_cflags(m0) & MC_TLS) {
3298 			ETHER_BPF_MTAP(ifp, m0);
3299 			n = t6_ktls_write_wr(txq, wr, m0, mbuf_nsegs(m0),
3300 			    avail);
3301 #endif
3302 		} else {
3303 			ETHER_BPF_MTAP(ifp, m0);
3304 			if (vi->flags & TX_USES_VM_WR)
3305 				n = write_txpkt_vm_wr(sc, txq, m0);
3306 			else
3307 				n = write_txpkt_wr(sc, txq, m0, avail);
3308 		}
3309 		MPASS(n >= 1 && n <= avail);
3310 		if (!(mbuf_cflags(m0) & MC_TLS))
3311 			MPASS(n <= SGE_MAX_WR_NDESC);
3312 
3313 		avail -= n;
3314 		dbdiff += n;
3315 		IDXINCR(eq->pidx, n, eq->sidx);
3316 
3317 		if (dbdiff >= 512 / EQ_ESIZE) {	/* X_FETCHBURSTMAX_512B */
3318 			if (wr_can_update_eq(wr))
3319 				set_txupdate_flags(txq, avail, wr);
3320 			ring_eq_db(sc, eq, dbdiff);
3321 			avail += reclaim_tx_descs(txq, 32);
3322 			dbdiff = 0;
3323 		}
3324 next_mbuf:
3325 		total++;
3326 		remaining--;
3327 		if (__predict_false(++cidx == r->size))
3328 			cidx = 0;
3329 	}
3330 	if (dbdiff != 0) {
3331 		if (wr_can_update_eq(wr))
3332 			set_txupdate_flags(txq, avail, wr);
3333 		ring_eq_db(sc, eq, dbdiff);
3334 		reclaim_tx_descs(txq, 32);
3335 	} else if (eq->pidx == eq->cidx && txp->npkt > 0 &&
3336 	    atomic_load_int(&txq->eq.equiq) == 0) {
3337 		/*
3338 		 * If nothing was submitted to the chip for tx (it was coalesced
3339 		 * into txpkts instead) and there is no tx update outstanding
3340 		 * then we need to send txpkts now.
3341 		 */
3342 send_txpkts:
3343 		MPASS(txp->npkt > 0);
3344 		for (i = 0; i < txp->npkt; i++)
3345 			ETHER_BPF_MTAP(ifp, txp->mb[i]);
3346 		if (txp->npkt > 1) {
3347 			MPASS(avail >= tx_len16_to_desc(txp->len16));
3348 			if (vi->flags & TX_USES_VM_WR)
3349 				n = write_txpkts_vm_wr(sc, txq);
3350 			else
3351 				n = write_txpkts_wr(sc, txq);
3352 		} else {
3353 			MPASS(avail >=
3354 			    tx_len16_to_desc(mbuf_len16(txp->mb[0])));
3355 			if (vi->flags & TX_USES_VM_WR)
3356 				n = write_txpkt_vm_wr(sc, txq, txp->mb[0]);
3357 			else
3358 				n = write_txpkt_wr(sc, txq, txp->mb[0], avail);
3359 		}
3360 		MPASS(n <= SGE_MAX_WR_NDESC);
3361 		wr = &eq->desc[eq->pidx];
3362 		IDXINCR(eq->pidx, n, eq->sidx);
3363 		txp->npkt = 0;	/* emptied */
3364 
3365 		MPASS(wr_can_update_eq(wr));
3366 		set_txupdate_flags(txq, avail - n, wr);
3367 		ring_eq_db(sc, eq, n);
3368 		reclaim_tx_descs(txq, 32);
3369 	}
3370 	*coalescing = txp->npkt > 0;
3371 
3372 	return (total);
3373 }
3374 
3375 static inline void
3376 init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int pktc_idx,
3377     int qsize, int intr_idx, int cong, int qtype)
3378 {
3379 
3380 	KASSERT(tmr_idx >= 0 && tmr_idx < SGE_NTIMERS,
3381 	    ("%s: bad tmr_idx %d", __func__, tmr_idx));
3382 	KASSERT(pktc_idx < SGE_NCOUNTERS,	/* -ve is ok, means don't use */
3383 	    ("%s: bad pktc_idx %d", __func__, pktc_idx));
3384 	KASSERT(intr_idx >= -1 && intr_idx < sc->intr_count,
3385 	    ("%s: bad intr_idx %d", __func__, intr_idx));
3386 	KASSERT(qtype == FW_IQ_IQTYPE_OTHER || qtype == FW_IQ_IQTYPE_NIC ||
3387 	    qtype == FW_IQ_IQTYPE_OFLD, ("%s: bad qtype %d", __func__, qtype));
3388 
3389 	iq->flags = 0;
3390 	iq->state = IQS_DISABLED;
3391 	iq->adapter = sc;
3392 	iq->qtype = qtype;
3393 	iq->intr_params = V_QINTR_TIMER_IDX(tmr_idx);
3394 	iq->intr_pktc_idx = SGE_NCOUNTERS - 1;
3395 	if (pktc_idx >= 0) {
3396 		iq->intr_params |= F_QINTR_CNT_EN;
3397 		iq->intr_pktc_idx = pktc_idx;
3398 	}
3399 	iq->qsize = roundup2(qsize, 16);	/* See FW_IQ_CMD/iqsize */
3400 	iq->sidx = iq->qsize - sc->params.sge.spg_len / IQ_ESIZE;
3401 	iq->intr_idx = intr_idx;
3402 	iq->cong_drop = cong;
3403 }
3404 
3405 static inline void
3406 init_fl(struct adapter *sc, struct sge_fl *fl, int qsize, int maxp, char *name)
3407 {
3408 	struct sge_params *sp = &sc->params.sge;
3409 
3410 	fl->qsize = qsize;
3411 	fl->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE;
3412 	strlcpy(fl->lockname, name, sizeof(fl->lockname));
3413 	mtx_init(&fl->fl_lock, fl->lockname, NULL, MTX_DEF);
3414 	if (sc->flags & BUF_PACKING_OK &&
3415 	    ((!is_t4(sc) && buffer_packing) ||	/* T5+: enabled unless 0 */
3416 	    (is_t4(sc) && buffer_packing == 1)))/* T4: disabled unless 1 */
3417 		fl->flags |= FL_BUF_PACKING;
3418 	fl->zidx = find_refill_source(sc, maxp, fl->flags & FL_BUF_PACKING);
3419 	fl->safe_zidx = sc->sge.safe_zidx;
3420 	if (fl->flags & FL_BUF_PACKING) {
3421 		fl->lowat = roundup2(sp->fl_starve_threshold2, 8);
3422 		fl->buf_boundary = sp->pack_boundary;
3423 	} else {
3424 		fl->lowat = roundup2(sp->fl_starve_threshold, 8);
3425 		fl->buf_boundary = 16;
3426 	}
3427 	if (fl_pad && fl->buf_boundary < sp->pad_boundary)
3428 		fl->buf_boundary = sp->pad_boundary;
3429 }
3430 
3431 static inline void
3432 init_eq(struct adapter *sc, struct sge_eq *eq, int eqtype, int qsize,
3433     uint8_t tx_chan, struct sge_iq *iq, char *name)
3434 {
3435 	KASSERT(eqtype >= EQ_CTRL && eqtype <= EQ_OFLD,
3436 	    ("%s: bad qtype %d", __func__, eqtype));
3437 
3438 	eq->type = eqtype;
3439 	eq->tx_chan = tx_chan;
3440 	eq->iq = iq;
3441 	eq->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE;
3442 	strlcpy(eq->lockname, name, sizeof(eq->lockname));
3443 	mtx_init(&eq->eq_lock, eq->lockname, NULL, MTX_DEF);
3444 }
3445 
3446 int
3447 alloc_ring(struct adapter *sc, size_t len, bus_dma_tag_t *tag,
3448     bus_dmamap_t *map, bus_addr_t *pa, void **va)
3449 {
3450 	int rc;
3451 
3452 	rc = bus_dma_tag_create(sc->dmat, 512, 0, BUS_SPACE_MAXADDR,
3453 	    BUS_SPACE_MAXADDR, NULL, NULL, len, 1, len, 0, NULL, NULL, tag);
3454 	if (rc != 0) {
3455 		CH_ERR(sc, "cannot allocate DMA tag: %d\n", rc);
3456 		goto done;
3457 	}
3458 
3459 	rc = bus_dmamem_alloc(*tag, va,
3460 	    BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, map);
3461 	if (rc != 0) {
3462 		CH_ERR(sc, "cannot allocate DMA memory: %d\n", rc);
3463 		goto done;
3464 	}
3465 
3466 	rc = bus_dmamap_load(*tag, *map, *va, len, oneseg_dma_callback, pa, 0);
3467 	if (rc != 0) {
3468 		CH_ERR(sc, "cannot load DMA map: %d\n", rc);
3469 		goto done;
3470 	}
3471 done:
3472 	if (rc)
3473 		free_ring(sc, *tag, *map, *pa, *va);
3474 
3475 	return (rc);
3476 }
3477 
3478 int
3479 free_ring(struct adapter *sc, bus_dma_tag_t tag, bus_dmamap_t map,
3480     bus_addr_t pa, void *va)
3481 {
3482 	if (pa)
3483 		bus_dmamap_unload(tag, map);
3484 	if (va)
3485 		bus_dmamem_free(tag, va, map);
3486 	if (tag)
3487 		bus_dma_tag_destroy(tag);
3488 
3489 	return (0);
3490 }
3491 
3492 /*
3493  * Allocates the software resources (mainly memory and sysctl nodes) for an
3494  * ingress queue and an optional freelist.
3495  *
3496  * Sets IQ_SW_ALLOCATED and returns 0 on success.
3497  */
3498 static int
3499 alloc_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl,
3500     struct sysctl_ctx_list *ctx, struct sysctl_oid *oid)
3501 {
3502 	int rc;
3503 	size_t len;
3504 	struct adapter *sc = vi->adapter;
3505 
3506 	MPASS(!(iq->flags & IQ_SW_ALLOCATED));
3507 
3508 	len = iq->qsize * IQ_ESIZE;
3509 	rc = alloc_ring(sc, len, &iq->desc_tag, &iq->desc_map, &iq->ba,
3510 	    (void **)&iq->desc);
3511 	if (rc != 0)
3512 		return (rc);
3513 
3514 	if (fl) {
3515 		len = fl->qsize * EQ_ESIZE;
3516 		rc = alloc_ring(sc, len, &fl->desc_tag, &fl->desc_map,
3517 		    &fl->ba, (void **)&fl->desc);
3518 		if (rc) {
3519 			free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba,
3520 			    iq->desc);
3521 			return (rc);
3522 		}
3523 
3524 		/* Allocate space for one software descriptor per buffer. */
3525 		fl->sdesc = malloc(fl->sidx * 8 * sizeof(struct fl_sdesc),
3526 		    M_CXGBE, M_ZERO | M_WAITOK);
3527 
3528 		add_fl_sysctls(sc, ctx, oid, fl);
3529 		iq->flags |= IQ_HAS_FL;
3530 	}
3531 	add_iq_sysctls(ctx, oid, iq);
3532 	iq->flags |= IQ_SW_ALLOCATED;
3533 
3534 	return (0);
3535 }
3536 
3537 /*
3538  * Frees all software resources (memory and locks) associated with an ingress
3539  * queue and an optional freelist.
3540  */
3541 static void
3542 free_iq_fl(struct adapter *sc, struct sge_iq *iq, struct sge_fl *fl)
3543 {
3544 	MPASS(iq->flags & IQ_SW_ALLOCATED);
3545 
3546 	if (fl) {
3547 		MPASS(iq->flags & IQ_HAS_FL);
3548 		free_ring(sc, fl->desc_tag, fl->desc_map, fl->ba, fl->desc);
3549 		free_fl_buffers(sc, fl);
3550 		free(fl->sdesc, M_CXGBE);
3551 		mtx_destroy(&fl->fl_lock);
3552 		bzero(fl, sizeof(*fl));
3553 	}
3554 	free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, iq->desc);
3555 	bzero(iq, sizeof(*iq));
3556 }
3557 
3558 /*
3559  * Allocates a hardware ingress queue and an optional freelist that will be
3560  * associated with it.
3561  *
3562  * Returns errno on failure.  Resources allocated up to that point may still be
3563  * allocated.  Caller is responsible for cleanup in case this function fails.
3564  */
3565 static int
3566 alloc_iq_fl_hwq(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl)
3567 {
3568 	int rc, cntxt_id, cong_map;
3569 	struct fw_iq_cmd c;
3570 	struct adapter *sc = vi->adapter;
3571 	struct port_info *pi = vi->pi;
3572 	__be32 v = 0;
3573 
3574 	MPASS (!(iq->flags & IQ_HW_ALLOCATED));
3575 
3576 	bzero(&c, sizeof(c));
3577 	c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
3578 	    F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) |
3579 	    V_FW_IQ_CMD_VFN(0));
3580 
3581 	c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART |
3582 	    FW_LEN16(c));
3583 
3584 	/* Special handling for firmware event queue */
3585 	if (iq == &sc->sge.fwq)
3586 		v |= F_FW_IQ_CMD_IQASYNCH;
3587 
3588 	if (iq->intr_idx < 0) {
3589 		/* Forwarded interrupts, all headed to fwq */
3590 		v |= F_FW_IQ_CMD_IQANDST;
3591 		v |= V_FW_IQ_CMD_IQANDSTINDEX(sc->sge.fwq.cntxt_id);
3592 	} else {
3593 		KASSERT(iq->intr_idx < sc->intr_count,
3594 		    ("%s: invalid direct intr_idx %d", __func__, iq->intr_idx));
3595 		v |= V_FW_IQ_CMD_IQANDSTINDEX(iq->intr_idx);
3596 	}
3597 
3598 	bzero(iq->desc, iq->qsize * IQ_ESIZE);
3599 	c.type_to_iqandstindex = htobe32(v |
3600 	    V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) |
3601 	    V_FW_IQ_CMD_VIID(vi->viid) |
3602 	    V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT));
3603 	c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->tx_chan) |
3604 	    F_FW_IQ_CMD_IQGTSMODE |
3605 	    V_FW_IQ_CMD_IQINTCNTTHRESH(iq->intr_pktc_idx) |
3606 	    V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4));
3607 	c.iqsize = htobe16(iq->qsize);
3608 	c.iqaddr = htobe64(iq->ba);
3609 	c.iqns_to_fl0congen = htobe32(V_FW_IQ_CMD_IQTYPE(iq->qtype));
3610 	if (iq->cong_drop != -1) {
3611 		cong_map = iq->qtype == IQ_ETH ? pi->rx_e_chan_map : 0;
3612 		c.iqns_to_fl0congen |= htobe32(F_FW_IQ_CMD_IQFLINTCONGEN);
3613 	}
3614 
3615 	if (fl) {
3616 		bzero(fl->desc, fl->sidx * EQ_ESIZE + sc->params.sge.spg_len);
3617 		c.iqns_to_fl0congen |=
3618 		    htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) |
3619 			F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO |
3620 			(fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) |
3621 			(fl->flags & FL_BUF_PACKING ? F_FW_IQ_CMD_FL0PACKEN :
3622 			    0));
3623 		if (iq->cong_drop != -1) {
3624 			c.iqns_to_fl0congen |=
3625 				htobe32(V_FW_IQ_CMD_FL0CNGCHMAP(cong_map) |
3626 				    F_FW_IQ_CMD_FL0CONGCIF |
3627 				    F_FW_IQ_CMD_FL0CONGEN);
3628 		}
3629 		c.fl0dcaen_to_fl0cidxfthresh =
3630 		    htobe16(V_FW_IQ_CMD_FL0FBMIN(chip_id(sc) <= CHELSIO_T5 ?
3631 			X_FETCHBURSTMIN_128B : X_FETCHBURSTMIN_64B_T6) |
3632 			V_FW_IQ_CMD_FL0FBMAX(chip_id(sc) <= CHELSIO_T5 ?
3633 			X_FETCHBURSTMAX_512B : X_FETCHBURSTMAX_256B));
3634 		c.fl0size = htobe16(fl->qsize);
3635 		c.fl0addr = htobe64(fl->ba);
3636 	}
3637 
3638 	rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
3639 	if (rc != 0) {
3640 		CH_ERR(sc, "failed to create hw ingress queue: %d\n", rc);
3641 		return (rc);
3642 	}
3643 
3644 	iq->cidx = 0;
3645 	iq->gen = F_RSPD_GEN;
3646 	iq->cntxt_id = be16toh(c.iqid);
3647 	iq->abs_id = be16toh(c.physiqid);
3648 
3649 	cntxt_id = iq->cntxt_id - sc->sge.iq_start;
3650 	if (cntxt_id >= sc->sge.iqmap_sz) {
3651 		panic ("%s: iq->cntxt_id (%d) more than the max (%d)", __func__,
3652 		    cntxt_id, sc->sge.iqmap_sz - 1);
3653 	}
3654 	sc->sge.iqmap[cntxt_id] = iq;
3655 
3656 	if (fl) {
3657 		u_int qid;
3658 #ifdef INVARIANTS
3659 		int i;
3660 
3661 		MPASS(!(fl->flags & FL_BUF_RESUME));
3662 		for (i = 0; i < fl->sidx * 8; i++)
3663 			MPASS(fl->sdesc[i].cl == NULL);
3664 #endif
3665 		fl->cntxt_id = be16toh(c.fl0id);
3666 		fl->pidx = fl->cidx = fl->hw_cidx = fl->dbidx = 0;
3667 		fl->rx_offset = 0;
3668 		fl->flags &= ~(FL_STARVING | FL_DOOMED);
3669 
3670 		cntxt_id = fl->cntxt_id - sc->sge.eq_start;
3671 		if (cntxt_id >= sc->sge.eqmap_sz) {
3672 			panic("%s: fl->cntxt_id (%d) more than the max (%d)",
3673 			    __func__, cntxt_id, sc->sge.eqmap_sz - 1);
3674 		}
3675 		sc->sge.eqmap[cntxt_id] = (void *)fl;
3676 
3677 		qid = fl->cntxt_id;
3678 		if (isset(&sc->doorbells, DOORBELL_UDB)) {
3679 			uint32_t s_qpp = sc->params.sge.eq_s_qpp;
3680 			uint32_t mask = (1 << s_qpp) - 1;
3681 			volatile uint8_t *udb;
3682 
3683 			udb = sc->udbs_base + UDBS_DB_OFFSET;
3684 			udb += (qid >> s_qpp) << PAGE_SHIFT;
3685 			qid &= mask;
3686 			if (qid < PAGE_SIZE / UDBS_SEG_SIZE) {
3687 				udb += qid << UDBS_SEG_SHIFT;
3688 				qid = 0;
3689 			}
3690 			fl->udb = (volatile void *)udb;
3691 		}
3692 		fl->dbval = V_QID(qid) | sc->chip_params->sge_fl_db;
3693 
3694 		FL_LOCK(fl);
3695 		/* Enough to make sure the SGE doesn't think it's starved */
3696 		refill_fl(sc, fl, fl->lowat);
3697 		FL_UNLOCK(fl);
3698 	}
3699 
3700 	if (chip_id(sc) >= CHELSIO_T5 && !(sc->flags & IS_VF) &&
3701 	    iq->cong_drop != -1) {
3702 		t4_sge_set_conm_context(sc, iq->cntxt_id, iq->cong_drop,
3703 		    cong_map);
3704 	}
3705 
3706 	/* Enable IQ interrupts */
3707 	atomic_store_rel_int(&iq->state, IQS_IDLE);
3708 	t4_write_reg(sc, sc->sge_gts_reg, V_SEINTARM(iq->intr_params) |
3709 	    V_INGRESSQID(iq->cntxt_id));
3710 
3711 	iq->flags |= IQ_HW_ALLOCATED;
3712 
3713 	return (0);
3714 }
3715 
3716 static int
3717 free_iq_fl_hwq(struct adapter *sc, struct sge_iq *iq, struct sge_fl *fl)
3718 {
3719 	int rc;
3720 
3721 	MPASS(iq->flags & IQ_HW_ALLOCATED);
3722 	rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0, FW_IQ_TYPE_FL_INT_CAP,
3723 	    iq->cntxt_id, fl ? fl->cntxt_id : 0xffff, 0xffff);
3724 	if (rc != 0) {
3725 		CH_ERR(sc, "failed to free iq %p: %d\n", iq, rc);
3726 		return (rc);
3727 	}
3728 	iq->flags &= ~IQ_HW_ALLOCATED;
3729 
3730 	return (0);
3731 }
3732 
3733 static void
3734 add_iq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid,
3735     struct sge_iq *iq)
3736 {
3737 	struct sysctl_oid_list *children;
3738 
3739 	if (ctx == NULL || oid == NULL)
3740 		return;
3741 
3742 	children = SYSCTL_CHILDREN(oid);
3743 	SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, &iq->ba,
3744 	    "bus address of descriptor ring");
3745 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
3746 	    iq->qsize * IQ_ESIZE, "descriptor ring size in bytes");
3747 	SYSCTL_ADD_U16(ctx, children, OID_AUTO, "abs_id", CTLFLAG_RD,
3748 	    &iq->abs_id, 0, "absolute id of the queue");
3749 	SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
3750 	    &iq->cntxt_id, 0, "SGE context id of the queue");
3751 	SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &iq->cidx,
3752 	    0, "consumer index");
3753 }
3754 
3755 static void
3756 add_fl_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx,
3757     struct sysctl_oid *oid, struct sge_fl *fl)
3758 {
3759 	struct sysctl_oid_list *children;
3760 
3761 	if (ctx == NULL || oid == NULL)
3762 		return;
3763 
3764 	children = SYSCTL_CHILDREN(oid);
3765 	oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl",
3766 	    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "freelist");
3767 	children = SYSCTL_CHILDREN(oid);
3768 
3769 	SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD,
3770 	    &fl->ba, "bus address of descriptor ring");
3771 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
3772 	    fl->sidx * EQ_ESIZE + sc->params.sge.spg_len,
3773 	    "desc ring size in bytes");
3774 	SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
3775 	    &fl->cntxt_id, 0, "SGE context id of the freelist");
3776 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "padding", CTLFLAG_RD, NULL,
3777 	    fl_pad ? 1 : 0, "padding enabled");
3778 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "packing", CTLFLAG_RD, NULL,
3779 	    fl->flags & FL_BUF_PACKING ? 1 : 0, "packing enabled");
3780 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &fl->cidx,
3781 	    0, "consumer index");
3782 	if (fl->flags & FL_BUF_PACKING) {
3783 		SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rx_offset",
3784 		    CTLFLAG_RD, &fl->rx_offset, 0, "packing rx offset");
3785 	}
3786 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &fl->pidx,
3787 	    0, "producer index");
3788 	SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_allocated",
3789 	    CTLFLAG_RD, &fl->cl_allocated, "# of clusters allocated");
3790 	SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_recycled",
3791 	    CTLFLAG_RD, &fl->cl_recycled, "# of clusters recycled");
3792 	SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_fast_recycled",
3793 	    CTLFLAG_RD, &fl->cl_fast_recycled, "# of clusters recycled (fast)");
3794 }
3795 
3796 /*
3797  * Idempotent.
3798  */
3799 static int
3800 alloc_fwq(struct adapter *sc)
3801 {
3802 	int rc, intr_idx;
3803 	struct sge_iq *fwq = &sc->sge.fwq;
3804 	struct vi_info *vi = &sc->port[0]->vi[0];
3805 
3806 	if (!(fwq->flags & IQ_SW_ALLOCATED)) {
3807 		MPASS(!(fwq->flags & IQ_HW_ALLOCATED));
3808 
3809 		if (sc->flags & IS_VF)
3810 			intr_idx = 0;
3811 		else
3812 			intr_idx = sc->intr_count > 1 ? 1 : 0;
3813 		init_iq(fwq, sc, 0, 0, FW_IQ_QSIZE, intr_idx, -1, IQ_OTHER);
3814 		rc = alloc_iq_fl(vi, fwq, NULL, &sc->ctx, sc->fwq_oid);
3815 		if (rc != 0) {
3816 			CH_ERR(sc, "failed to allocate fwq: %d\n", rc);
3817 			return (rc);
3818 		}
3819 		MPASS(fwq->flags & IQ_SW_ALLOCATED);
3820 	}
3821 
3822 	if (!(fwq->flags & IQ_HW_ALLOCATED)) {
3823 		MPASS(fwq->flags & IQ_SW_ALLOCATED);
3824 
3825 		rc = alloc_iq_fl_hwq(vi, fwq, NULL);
3826 		if (rc != 0) {
3827 			CH_ERR(sc, "failed to create hw fwq: %d\n", rc);
3828 			return (rc);
3829 		}
3830 		MPASS(fwq->flags & IQ_HW_ALLOCATED);
3831 	}
3832 
3833 	return (0);
3834 }
3835 
3836 /*
3837  * Idempotent.
3838  */
3839 static void
3840 free_fwq(struct adapter *sc)
3841 {
3842 	struct sge_iq *fwq = &sc->sge.fwq;
3843 
3844 	if (fwq->flags & IQ_HW_ALLOCATED) {
3845 		MPASS(fwq->flags & IQ_SW_ALLOCATED);
3846 		free_iq_fl_hwq(sc, fwq, NULL);
3847 		MPASS(!(fwq->flags & IQ_HW_ALLOCATED));
3848 	}
3849 
3850 	if (fwq->flags & IQ_SW_ALLOCATED) {
3851 		MPASS(!(fwq->flags & IQ_HW_ALLOCATED));
3852 		free_iq_fl(sc, fwq, NULL);
3853 		MPASS(!(fwq->flags & IQ_SW_ALLOCATED));
3854 	}
3855 }
3856 
3857 /*
3858  * Idempotent.
3859  */
3860 static int
3861 alloc_ctrlq(struct adapter *sc, int idx)
3862 {
3863 	int rc;
3864 	char name[16];
3865 	struct sysctl_oid *oid;
3866 	struct sge_wrq *ctrlq = &sc->sge.ctrlq[idx];
3867 
3868 	MPASS(idx < sc->params.nports);
3869 
3870 	if (!(ctrlq->eq.flags & EQ_SW_ALLOCATED)) {
3871 		MPASS(!(ctrlq->eq.flags & EQ_HW_ALLOCATED));
3872 
3873 		snprintf(name, sizeof(name), "%d", idx);
3874 		oid = SYSCTL_ADD_NODE(&sc->ctx, SYSCTL_CHILDREN(sc->ctrlq_oid),
3875 		    OID_AUTO, name, CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
3876 		    "ctrl queue");
3877 
3878 		snprintf(name, sizeof(name), "%s ctrlq%d",
3879 		    device_get_nameunit(sc->dev), idx);
3880 		init_eq(sc, &ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE,
3881 		    sc->port[idx]->tx_chan, &sc->sge.fwq, name);
3882 		rc = alloc_wrq(sc, NULL, ctrlq, &sc->ctx, oid);
3883 		if (rc != 0) {
3884 			CH_ERR(sc, "failed to allocate ctrlq%d: %d\n", idx, rc);
3885 			sysctl_remove_oid(oid, 1, 1);
3886 			return (rc);
3887 		}
3888 		MPASS(ctrlq->eq.flags & EQ_SW_ALLOCATED);
3889 	}
3890 
3891 	if (!(ctrlq->eq.flags & EQ_HW_ALLOCATED)) {
3892 		MPASS(ctrlq->eq.flags & EQ_SW_ALLOCATED);
3893 
3894 		rc = alloc_eq_hwq(sc, NULL, &ctrlq->eq);
3895 		if (rc != 0) {
3896 			CH_ERR(sc, "failed to create hw ctrlq%d: %d\n", idx, rc);
3897 			return (rc);
3898 		}
3899 		MPASS(ctrlq->eq.flags & EQ_HW_ALLOCATED);
3900 	}
3901 
3902 	return (0);
3903 }
3904 
3905 /*
3906  * Idempotent.
3907  */
3908 static void
3909 free_ctrlq(struct adapter *sc, int idx)
3910 {
3911 	struct sge_wrq *ctrlq = &sc->sge.ctrlq[idx];
3912 
3913 	if (ctrlq->eq.flags & EQ_HW_ALLOCATED) {
3914 		MPASS(ctrlq->eq.flags & EQ_SW_ALLOCATED);
3915 		free_eq_hwq(sc, NULL, &ctrlq->eq);
3916 		MPASS(!(ctrlq->eq.flags & EQ_HW_ALLOCATED));
3917 	}
3918 
3919 	if (ctrlq->eq.flags & EQ_SW_ALLOCATED) {
3920 		MPASS(!(ctrlq->eq.flags & EQ_HW_ALLOCATED));
3921 		free_wrq(sc, ctrlq);
3922 		MPASS(!(ctrlq->eq.flags & EQ_SW_ALLOCATED));
3923 	}
3924 }
3925 
3926 int
3927 t4_sge_set_conm_context(struct adapter *sc, int cntxt_id, int cong_drop,
3928     int cong_map)
3929 {
3930 	const int cng_ch_bits_log = sc->chip_params->cng_ch_bits_log;
3931 	uint32_t param, val;
3932 	uint16_t ch_map;
3933 	int cong_mode, rc, i;
3934 
3935 	if (chip_id(sc) < CHELSIO_T5)
3936 		return (ENOTSUP);
3937 
3938 	/* Convert the driver knob to the mode understood by the firmware. */
3939 	switch (cong_drop) {
3940 	case -1:
3941 		cong_mode = X_CONMCTXT_CNGTPMODE_DISABLE;
3942 		break;
3943 	case 0:
3944 		cong_mode = X_CONMCTXT_CNGTPMODE_CHANNEL;
3945 		break;
3946 	case 1:
3947 		cong_mode = X_CONMCTXT_CNGTPMODE_QUEUE;
3948 		break;
3949 	case 2:
3950 		cong_mode = X_CONMCTXT_CNGTPMODE_BOTH;
3951 		break;
3952 	default:
3953 		MPASS(0);
3954 		CH_ERR(sc, "cong_drop = %d is invalid (ingress queue %d).\n",
3955 		    cong_drop, cntxt_id);
3956 		return (EINVAL);
3957 	}
3958 
3959 	param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
3960 	    V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) |
3961 	    V_FW_PARAMS_PARAM_YZ(cntxt_id);
3962 	val = V_CONMCTXT_CNGTPMODE(cong_mode);
3963 	if (cong_mode == X_CONMCTXT_CNGTPMODE_CHANNEL ||
3964 	    cong_mode == X_CONMCTXT_CNGTPMODE_BOTH) {
3965 		for (i = 0, ch_map = 0; i < 4; i++) {
3966 			if (cong_map & (1 << i))
3967 				ch_map |= 1 << (i << cng_ch_bits_log);
3968 		}
3969 		val |= V_CONMCTXT_CNGCHMAP(ch_map);
3970 	}
3971 	rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &param, &val);
3972 	if (rc != 0) {
3973 		CH_ERR(sc, "failed to set congestion manager context "
3974 		    "for ingress queue %d: %d\n", cntxt_id, rc);
3975 	}
3976 
3977 	return (rc);
3978 }
3979 
3980 /*
3981  * Idempotent.
3982  */
3983 static int
3984 alloc_rxq(struct vi_info *vi, struct sge_rxq *rxq, int idx, int intr_idx,
3985     int maxp)
3986 {
3987 	int rc;
3988 	struct adapter *sc = vi->adapter;
3989 	struct ifnet *ifp = vi->ifp;
3990 	struct sysctl_oid *oid;
3991 	char name[16];
3992 
3993 	if (!(rxq->iq.flags & IQ_SW_ALLOCATED)) {
3994 		MPASS(!(rxq->iq.flags & IQ_HW_ALLOCATED));
3995 #if defined(INET) || defined(INET6)
3996 		rc = tcp_lro_init_args(&rxq->lro, ifp, lro_entries, lro_mbufs);
3997 		if (rc != 0)
3998 			return (rc);
3999 		MPASS(rxq->lro.ifp == ifp);	/* also indicates LRO init'ed */
4000 #endif
4001 		rxq->ifp = ifp;
4002 
4003 		snprintf(name, sizeof(name), "%d", idx);
4004 		oid = SYSCTL_ADD_NODE(&vi->ctx, SYSCTL_CHILDREN(vi->rxq_oid),
4005 		    OID_AUTO, name, CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
4006 		    "rx queue");
4007 
4008 		init_iq(&rxq->iq, sc, vi->tmr_idx, vi->pktc_idx, vi->qsize_rxq,
4009 		    intr_idx, cong_drop, IQ_ETH);
4010 #if defined(INET) || defined(INET6)
4011 		if (ifp->if_capenable & IFCAP_LRO)
4012 			rxq->iq.flags |= IQ_LRO_ENABLED;
4013 #endif
4014 		if (ifp->if_capenable & IFCAP_HWRXTSTMP)
4015 			rxq->iq.flags |= IQ_RX_TIMESTAMP;
4016 		snprintf(name, sizeof(name), "%s rxq%d-fl",
4017 		    device_get_nameunit(vi->dev), idx);
4018 		init_fl(sc, &rxq->fl, vi->qsize_rxq / 8, maxp, name);
4019 		rc = alloc_iq_fl(vi, &rxq->iq, &rxq->fl, &vi->ctx, oid);
4020 		if (rc != 0) {
4021 			CH_ERR(vi, "failed to allocate rxq%d: %d\n", idx, rc);
4022 			sysctl_remove_oid(oid, 1, 1);
4023 #if defined(INET) || defined(INET6)
4024 			tcp_lro_free(&rxq->lro);
4025 			rxq->lro.ifp = NULL;
4026 #endif
4027 			return (rc);
4028 		}
4029 		MPASS(rxq->iq.flags & IQ_SW_ALLOCATED);
4030 		add_rxq_sysctls(&vi->ctx, oid, rxq);
4031 	}
4032 
4033 	if (!(rxq->iq.flags & IQ_HW_ALLOCATED)) {
4034 		MPASS(rxq->iq.flags & IQ_SW_ALLOCATED);
4035 		rc = alloc_iq_fl_hwq(vi, &rxq->iq, &rxq->fl);
4036 		if (rc != 0) {
4037 			CH_ERR(vi, "failed to create hw rxq%d: %d\n", idx, rc);
4038 			return (rc);
4039 		}
4040 		MPASS(rxq->iq.flags & IQ_HW_ALLOCATED);
4041 
4042 		if (idx == 0)
4043 			sc->sge.iq_base = rxq->iq.abs_id - rxq->iq.cntxt_id;
4044 		else
4045 			KASSERT(rxq->iq.cntxt_id + sc->sge.iq_base == rxq->iq.abs_id,
4046 			    ("iq_base mismatch"));
4047 		KASSERT(sc->sge.iq_base == 0 || sc->flags & IS_VF,
4048 		    ("PF with non-zero iq_base"));
4049 
4050 		/*
4051 		 * The freelist is just barely above the starvation threshold
4052 		 * right now, fill it up a bit more.
4053 		 */
4054 		FL_LOCK(&rxq->fl);
4055 		refill_fl(sc, &rxq->fl, 128);
4056 		FL_UNLOCK(&rxq->fl);
4057 	}
4058 
4059 	return (0);
4060 }
4061 
4062 /*
4063  * Idempotent.
4064  */
4065 static void
4066 free_rxq(struct vi_info *vi, struct sge_rxq *rxq)
4067 {
4068 	if (rxq->iq.flags & IQ_HW_ALLOCATED) {
4069 		MPASS(rxq->iq.flags & IQ_SW_ALLOCATED);
4070 		free_iq_fl_hwq(vi->adapter, &rxq->iq, &rxq->fl);
4071 		MPASS(!(rxq->iq.flags & IQ_HW_ALLOCATED));
4072 	}
4073 
4074 	if (rxq->iq.flags & IQ_SW_ALLOCATED) {
4075 		MPASS(!(rxq->iq.flags & IQ_HW_ALLOCATED));
4076 #if defined(INET) || defined(INET6)
4077 		tcp_lro_free(&rxq->lro);
4078 #endif
4079 		free_iq_fl(vi->adapter, &rxq->iq, &rxq->fl);
4080 		MPASS(!(rxq->iq.flags & IQ_SW_ALLOCATED));
4081 		bzero(rxq, sizeof(*rxq));
4082 	}
4083 }
4084 
4085 static void
4086 add_rxq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid,
4087     struct sge_rxq *rxq)
4088 {
4089 	struct sysctl_oid_list *children;
4090 
4091 	if (ctx == NULL || oid == NULL)
4092 		return;
4093 
4094 	children = SYSCTL_CHILDREN(oid);
4095 #if defined(INET) || defined(INET6)
4096 	SYSCTL_ADD_U64(ctx, children, OID_AUTO, "lro_queued", CTLFLAG_RD,
4097 	    &rxq->lro.lro_queued, 0, NULL);
4098 	SYSCTL_ADD_U64(ctx, children, OID_AUTO, "lro_flushed", CTLFLAG_RD,
4099 	    &rxq->lro.lro_flushed, 0, NULL);
4100 #endif
4101 	SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "rxcsum", CTLFLAG_RD,
4102 	    &rxq->rxcsum, "# of times hardware assisted with checksum");
4103 	SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "vlan_extraction", CTLFLAG_RD,
4104 	    &rxq->vlan_extraction, "# of times hardware extracted 802.1Q tag");
4105 	SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "vxlan_rxcsum", CTLFLAG_RD,
4106 	    &rxq->vxlan_rxcsum,
4107 	    "# of times hardware assisted with inner checksum (VXLAN)");
4108 }
4109 
4110 #ifdef TCP_OFFLOAD
4111 /*
4112  * Idempotent.
4113  */
4114 static int
4115 alloc_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq, int idx,
4116     int intr_idx, int maxp)
4117 {
4118 	int rc;
4119 	struct adapter *sc = vi->adapter;
4120 	struct sysctl_oid *oid;
4121 	char name[16];
4122 
4123 	if (!(ofld_rxq->iq.flags & IQ_SW_ALLOCATED)) {
4124 		MPASS(!(ofld_rxq->iq.flags & IQ_HW_ALLOCATED));
4125 
4126 		snprintf(name, sizeof(name), "%d", idx);
4127 		oid = SYSCTL_ADD_NODE(&vi->ctx,
4128 		    SYSCTL_CHILDREN(vi->ofld_rxq_oid), OID_AUTO, name,
4129 		    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "offload rx queue");
4130 
4131 		init_iq(&ofld_rxq->iq, sc, vi->ofld_tmr_idx, vi->ofld_pktc_idx,
4132 		    vi->qsize_rxq, intr_idx, ofld_cong_drop, IQ_OFLD);
4133 		snprintf(name, sizeof(name), "%s ofld_rxq%d-fl",
4134 		    device_get_nameunit(vi->dev), idx);
4135 		init_fl(sc, &ofld_rxq->fl, vi->qsize_rxq / 8, maxp, name);
4136 		rc = alloc_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl, &vi->ctx,
4137 		    oid);
4138 		if (rc != 0) {
4139 			CH_ERR(vi, "failed to allocate ofld_rxq%d: %d\n", idx,
4140 			    rc);
4141 			sysctl_remove_oid(oid, 1, 1);
4142 			return (rc);
4143 		}
4144 		MPASS(ofld_rxq->iq.flags & IQ_SW_ALLOCATED);
4145 		ofld_rxq->rx_iscsi_ddp_setup_ok = counter_u64_alloc(M_WAITOK);
4146 		ofld_rxq->rx_iscsi_ddp_setup_error =
4147 		    counter_u64_alloc(M_WAITOK);
4148 		add_ofld_rxq_sysctls(&vi->ctx, oid, ofld_rxq);
4149 	}
4150 
4151 	if (!(ofld_rxq->iq.flags & IQ_HW_ALLOCATED)) {
4152 		MPASS(ofld_rxq->iq.flags & IQ_SW_ALLOCATED);
4153 		rc = alloc_iq_fl_hwq(vi, &ofld_rxq->iq, &ofld_rxq->fl);
4154 		if (rc != 0) {
4155 			CH_ERR(vi, "failed to create hw ofld_rxq%d: %d\n", idx,
4156 			    rc);
4157 			return (rc);
4158 		}
4159 		MPASS(ofld_rxq->iq.flags & IQ_HW_ALLOCATED);
4160 	}
4161 	return (rc);
4162 }
4163 
4164 /*
4165  * Idempotent.
4166  */
4167 static void
4168 free_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq)
4169 {
4170 	if (ofld_rxq->iq.flags & IQ_HW_ALLOCATED) {
4171 		MPASS(ofld_rxq->iq.flags & IQ_SW_ALLOCATED);
4172 		free_iq_fl_hwq(vi->adapter, &ofld_rxq->iq, &ofld_rxq->fl);
4173 		MPASS(!(ofld_rxq->iq.flags & IQ_HW_ALLOCATED));
4174 	}
4175 
4176 	if (ofld_rxq->iq.flags & IQ_SW_ALLOCATED) {
4177 		MPASS(!(ofld_rxq->iq.flags & IQ_HW_ALLOCATED));
4178 		free_iq_fl(vi->adapter, &ofld_rxq->iq, &ofld_rxq->fl);
4179 		MPASS(!(ofld_rxq->iq.flags & IQ_SW_ALLOCATED));
4180 		counter_u64_free(ofld_rxq->rx_iscsi_ddp_setup_ok);
4181 		counter_u64_free(ofld_rxq->rx_iscsi_ddp_setup_error);
4182 		bzero(ofld_rxq, sizeof(*ofld_rxq));
4183 	}
4184 }
4185 
4186 static void
4187 add_ofld_rxq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid,
4188     struct sge_ofld_rxq *ofld_rxq)
4189 {
4190 	struct sysctl_oid_list *children;
4191 
4192 	if (ctx == NULL || oid == NULL)
4193 		return;
4194 
4195 	children = SYSCTL_CHILDREN(oid);
4196 	SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
4197 	    "rx_toe_tls_records", CTLFLAG_RD, &ofld_rxq->rx_toe_tls_records,
4198 	    "# of TOE TLS records received");
4199 	SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
4200 	    "rx_toe_tls_octets", CTLFLAG_RD, &ofld_rxq->rx_toe_tls_octets,
4201 	    "# of payload octets in received TOE TLS records");
4202 
4203 	oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "iscsi",
4204 	    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TOE iSCSI statistics");
4205 	children = SYSCTL_CHILDREN(oid);
4206 
4207 	SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "ddp_setup_ok",
4208 	    CTLFLAG_RD, &ofld_rxq->rx_iscsi_ddp_setup_ok,
4209 	    "# of times DDP buffer was setup successfully.");
4210 	SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "ddp_setup_error",
4211 	    CTLFLAG_RD, &ofld_rxq->rx_iscsi_ddp_setup_error,
4212 	    "# of times DDP buffer setup failed.");
4213 	SYSCTL_ADD_U64(ctx, children, OID_AUTO, "ddp_octets",
4214 	    CTLFLAG_RD, &ofld_rxq->rx_iscsi_ddp_octets, 0,
4215 	    "# of octets placed directly");
4216 	SYSCTL_ADD_U64(ctx, children, OID_AUTO, "ddp_pdus",
4217 	    CTLFLAG_RD, &ofld_rxq->rx_iscsi_ddp_pdus, 0,
4218 	    "# of PDUs with data placed directly.");
4219 	SYSCTL_ADD_U64(ctx, children, OID_AUTO, "fl_octets",
4220 	    CTLFLAG_RD, &ofld_rxq->rx_iscsi_fl_octets, 0,
4221 	    "# of data octets delivered in freelist");
4222 	SYSCTL_ADD_U64(ctx, children, OID_AUTO, "fl_pdus",
4223 	    CTLFLAG_RD, &ofld_rxq->rx_iscsi_fl_pdus, 0,
4224 	    "# of PDUs with data delivered in freelist");
4225 	SYSCTL_ADD_U64(ctx, children, OID_AUTO, "padding_errors",
4226 	    CTLFLAG_RD, &ofld_rxq->rx_iscsi_padding_errors, 0,
4227 	    "# of PDUs with invalid padding");
4228 	SYSCTL_ADD_U64(ctx, children, OID_AUTO, "header_digest_errors",
4229 	    CTLFLAG_RD, &ofld_rxq->rx_iscsi_header_digest_errors, 0,
4230 	    "# of PDUs with invalid header digests");
4231 	SYSCTL_ADD_U64(ctx, children, OID_AUTO, "data_digest_errors",
4232 	    CTLFLAG_RD, &ofld_rxq->rx_iscsi_data_digest_errors, 0,
4233 	    "# of PDUs with invalid data digests");
4234 }
4235 #endif
4236 
4237 /*
4238  * Returns a reasonable automatic cidx flush threshold for a given queue size.
4239  */
4240 static u_int
4241 qsize_to_fthresh(int qsize)
4242 {
4243 	u_int fthresh;
4244 
4245 	while (!powerof2(qsize))
4246 		qsize++;
4247 	fthresh = ilog2(qsize);
4248 	if (fthresh > X_CIDXFLUSHTHRESH_128)
4249 		fthresh = X_CIDXFLUSHTHRESH_128;
4250 
4251 	return (fthresh);
4252 }
4253 
4254 static int
4255 ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq)
4256 {
4257 	int rc, cntxt_id;
4258 	struct fw_eq_ctrl_cmd c;
4259 	int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
4260 
4261 	bzero(&c, sizeof(c));
4262 
4263 	c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | F_FW_CMD_REQUEST |
4264 	    F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_CTRL_CMD_PFN(sc->pf) |
4265 	    V_FW_EQ_CTRL_CMD_VFN(0));
4266 	c.alloc_to_len16 = htobe32(F_FW_EQ_CTRL_CMD_ALLOC |
4267 	    F_FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c));
4268 	c.cmpliqid_eqid = htonl(V_FW_EQ_CTRL_CMD_CMPLIQID(eq->iqid));
4269 	c.physeqid_pkd = htobe32(0);
4270 	c.fetchszm_to_iqid =
4271 	    htobe32(V_FW_EQ_CTRL_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) |
4272 		V_FW_EQ_CTRL_CMD_PCIECHN(eq->tx_chan) |
4273 		F_FW_EQ_CTRL_CMD_FETCHRO | V_FW_EQ_CTRL_CMD_IQID(eq->iqid));
4274 	c.dcaen_to_eqsize =
4275 	    htobe32(V_FW_EQ_CTRL_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ?
4276 		X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) |
4277 		V_FW_EQ_CTRL_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
4278 		V_FW_EQ_CTRL_CMD_CIDXFTHRESH(qsize_to_fthresh(qsize)) |
4279 		V_FW_EQ_CTRL_CMD_EQSIZE(qsize));
4280 	c.eqaddr = htobe64(eq->ba);
4281 
4282 	rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
4283 	if (rc != 0) {
4284 		CH_ERR(sc, "failed to create hw ctrlq for tx_chan %d: %d\n",
4285 		    eq->tx_chan, rc);
4286 		return (rc);
4287 	}
4288 
4289 	eq->cntxt_id = G_FW_EQ_CTRL_CMD_EQID(be32toh(c.cmpliqid_eqid));
4290 	eq->abs_id = G_FW_EQ_CTRL_CMD_PHYSEQID(be32toh(c.physeqid_pkd));
4291 	cntxt_id = eq->cntxt_id - sc->sge.eq_start;
4292 	if (cntxt_id >= sc->sge.eqmap_sz)
4293 	    panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
4294 		cntxt_id, sc->sge.eqmap_sz - 1);
4295 	sc->sge.eqmap[cntxt_id] = eq;
4296 
4297 	return (rc);
4298 }
4299 
4300 static int
4301 eth_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq)
4302 {
4303 	int rc, cntxt_id;
4304 	struct fw_eq_eth_cmd c;
4305 	int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
4306 
4307 	bzero(&c, sizeof(c));
4308 
4309 	c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST |
4310 	    F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) |
4311 	    V_FW_EQ_ETH_CMD_VFN(0));
4312 	c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC |
4313 	    F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c));
4314 	c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE |
4315 	    F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(vi->viid));
4316 	c.fetchszm_to_iqid =
4317 	    htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) |
4318 		V_FW_EQ_ETH_CMD_PCIECHN(eq->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO |
4319 		V_FW_EQ_ETH_CMD_IQID(eq->iqid));
4320 	c.dcaen_to_eqsize =
4321 	    htobe32(V_FW_EQ_ETH_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ?
4322 		X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) |
4323 		V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
4324 		V_FW_EQ_ETH_CMD_EQSIZE(qsize));
4325 	c.eqaddr = htobe64(eq->ba);
4326 
4327 	rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
4328 	if (rc != 0) {
4329 		device_printf(vi->dev,
4330 		    "failed to create Ethernet egress queue: %d\n", rc);
4331 		return (rc);
4332 	}
4333 
4334 	eq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd));
4335 	eq->abs_id = G_FW_EQ_ETH_CMD_PHYSEQID(be32toh(c.physeqid_pkd));
4336 	cntxt_id = eq->cntxt_id - sc->sge.eq_start;
4337 	if (cntxt_id >= sc->sge.eqmap_sz)
4338 	    panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
4339 		cntxt_id, sc->sge.eqmap_sz - 1);
4340 	sc->sge.eqmap[cntxt_id] = eq;
4341 
4342 	return (rc);
4343 }
4344 
4345 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
4346 static int
4347 ofld_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq)
4348 {
4349 	int rc, cntxt_id;
4350 	struct fw_eq_ofld_cmd c;
4351 	int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
4352 
4353 	bzero(&c, sizeof(c));
4354 
4355 	c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | F_FW_CMD_REQUEST |
4356 	    F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_OFLD_CMD_PFN(sc->pf) |
4357 	    V_FW_EQ_OFLD_CMD_VFN(0));
4358 	c.alloc_to_len16 = htonl(F_FW_EQ_OFLD_CMD_ALLOC |
4359 	    F_FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c));
4360 	c.fetchszm_to_iqid =
4361 		htonl(V_FW_EQ_OFLD_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) |
4362 		    V_FW_EQ_OFLD_CMD_PCIECHN(eq->tx_chan) |
4363 		    F_FW_EQ_OFLD_CMD_FETCHRO | V_FW_EQ_OFLD_CMD_IQID(eq->iqid));
4364 	c.dcaen_to_eqsize =
4365 	    htobe32(V_FW_EQ_OFLD_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ?
4366 		X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) |
4367 		V_FW_EQ_OFLD_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
4368 		V_FW_EQ_OFLD_CMD_CIDXFTHRESH(qsize_to_fthresh(qsize)) |
4369 		V_FW_EQ_OFLD_CMD_EQSIZE(qsize));
4370 	c.eqaddr = htobe64(eq->ba);
4371 
4372 	rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
4373 	if (rc != 0) {
4374 		device_printf(vi->dev,
4375 		    "failed to create egress queue for TCP offload: %d\n", rc);
4376 		return (rc);
4377 	}
4378 
4379 	eq->cntxt_id = G_FW_EQ_OFLD_CMD_EQID(be32toh(c.eqid_pkd));
4380 	eq->abs_id = G_FW_EQ_OFLD_CMD_PHYSEQID(be32toh(c.physeqid_pkd));
4381 	cntxt_id = eq->cntxt_id - sc->sge.eq_start;
4382 	if (cntxt_id >= sc->sge.eqmap_sz)
4383 	    panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
4384 		cntxt_id, sc->sge.eqmap_sz - 1);
4385 	sc->sge.eqmap[cntxt_id] = eq;
4386 
4387 	return (rc);
4388 }
4389 #endif
4390 
4391 /* SW only */
4392 static int
4393 alloc_eq(struct adapter *sc, struct sge_eq *eq, struct sysctl_ctx_list *ctx,
4394     struct sysctl_oid *oid)
4395 {
4396 	int rc, qsize;
4397 	size_t len;
4398 
4399 	MPASS(!(eq->flags & EQ_SW_ALLOCATED));
4400 
4401 	qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
4402 	len = qsize * EQ_ESIZE;
4403 	rc = alloc_ring(sc, len, &eq->desc_tag, &eq->desc_map, &eq->ba,
4404 	    (void **)&eq->desc);
4405 	if (rc)
4406 		return (rc);
4407 	if (ctx != NULL && oid != NULL)
4408 		add_eq_sysctls(sc, ctx, oid, eq);
4409 	eq->flags |= EQ_SW_ALLOCATED;
4410 
4411 	return (0);
4412 }
4413 
4414 /* SW only */
4415 static void
4416 free_eq(struct adapter *sc, struct sge_eq *eq)
4417 {
4418 	MPASS(eq->flags & EQ_SW_ALLOCATED);
4419 	if (eq->type == EQ_ETH)
4420 		MPASS(eq->pidx == eq->cidx);
4421 
4422 	free_ring(sc, eq->desc_tag, eq->desc_map, eq->ba, eq->desc);
4423 	mtx_destroy(&eq->eq_lock);
4424 	bzero(eq, sizeof(*eq));
4425 }
4426 
4427 static void
4428 add_eq_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx,
4429     struct sysctl_oid *oid, struct sge_eq *eq)
4430 {
4431 	struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
4432 
4433 	SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, &eq->ba,
4434 	    "bus address of descriptor ring");
4435 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
4436 	    eq->sidx * EQ_ESIZE + sc->params.sge.spg_len,
4437 	    "desc ring size in bytes");
4438 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "abs_id", CTLFLAG_RD,
4439 	    &eq->abs_id, 0, "absolute id of the queue");
4440 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
4441 	    &eq->cntxt_id, 0, "SGE context id of the queue");
4442 	SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &eq->cidx,
4443 	    0, "consumer index");
4444 	SYSCTL_ADD_U16(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &eq->pidx,
4445 	    0, "producer index");
4446 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL,
4447 	    eq->sidx, "status page index");
4448 }
4449 
4450 static int
4451 alloc_eq_hwq(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq)
4452 {
4453 	int rc;
4454 
4455 	MPASS(!(eq->flags & EQ_HW_ALLOCATED));
4456 
4457 	eq->iqid = eq->iq->cntxt_id;
4458 	eq->pidx = eq->cidx = eq->dbidx = 0;
4459 	/* Note that equeqidx is not used with sge_wrq (OFLD/CTRL) queues. */
4460 	eq->equeqidx = 0;
4461 	eq->doorbells = sc->doorbells;
4462 	bzero(eq->desc, eq->sidx * EQ_ESIZE + sc->params.sge.spg_len);
4463 
4464 	switch (eq->type) {
4465 	case EQ_CTRL:
4466 		rc = ctrl_eq_alloc(sc, eq);
4467 		break;
4468 
4469 	case EQ_ETH:
4470 		rc = eth_eq_alloc(sc, vi, eq);
4471 		break;
4472 
4473 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
4474 	case EQ_OFLD:
4475 		rc = ofld_eq_alloc(sc, vi, eq);
4476 		break;
4477 #endif
4478 
4479 	default:
4480 		panic("%s: invalid eq type %d.", __func__, eq->type);
4481 	}
4482 	if (rc != 0) {
4483 		CH_ERR(sc, "failed to allocate egress queue(%d): %d\n",
4484 		    eq->type, rc);
4485 		return (rc);
4486 	}
4487 
4488 	if (isset(&eq->doorbells, DOORBELL_UDB) ||
4489 	    isset(&eq->doorbells, DOORBELL_UDBWC) ||
4490 	    isset(&eq->doorbells, DOORBELL_WCWR)) {
4491 		uint32_t s_qpp = sc->params.sge.eq_s_qpp;
4492 		uint32_t mask = (1 << s_qpp) - 1;
4493 		volatile uint8_t *udb;
4494 
4495 		udb = sc->udbs_base + UDBS_DB_OFFSET;
4496 		udb += (eq->cntxt_id >> s_qpp) << PAGE_SHIFT;	/* pg offset */
4497 		eq->udb_qid = eq->cntxt_id & mask;		/* id in page */
4498 		if (eq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE)
4499 	    		clrbit(&eq->doorbells, DOORBELL_WCWR);
4500 		else {
4501 			udb += eq->udb_qid << UDBS_SEG_SHIFT;	/* seg offset */
4502 			eq->udb_qid = 0;
4503 		}
4504 		eq->udb = (volatile void *)udb;
4505 	}
4506 
4507 	eq->flags |= EQ_HW_ALLOCATED;
4508 	return (0);
4509 }
4510 
4511 static int
4512 free_eq_hwq(struct adapter *sc, struct vi_info *vi __unused, struct sge_eq *eq)
4513 {
4514 	int rc;
4515 
4516 	MPASS(eq->flags & EQ_HW_ALLOCATED);
4517 
4518 	switch (eq->type) {
4519 	case EQ_CTRL:
4520 		rc = -t4_ctrl_eq_free(sc, sc->mbox, sc->pf, 0, eq->cntxt_id);
4521 		break;
4522 	case EQ_ETH:
4523 		rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0, eq->cntxt_id);
4524 		break;
4525 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
4526 	case EQ_OFLD:
4527 		rc = -t4_ofld_eq_free(sc, sc->mbox, sc->pf, 0, eq->cntxt_id);
4528 		break;
4529 #endif
4530 	default:
4531 		panic("%s: invalid eq type %d.", __func__, eq->type);
4532 	}
4533 	if (rc != 0) {
4534 		CH_ERR(sc, "failed to free eq (type %d): %d\n", eq->type, rc);
4535 		return (rc);
4536 	}
4537 	eq->flags &= ~EQ_HW_ALLOCATED;
4538 
4539 	return (0);
4540 }
4541 
4542 static int
4543 alloc_wrq(struct adapter *sc, struct vi_info *vi, struct sge_wrq *wrq,
4544     struct sysctl_ctx_list *ctx, struct sysctl_oid *oid)
4545 {
4546 	struct sge_eq *eq = &wrq->eq;
4547 	int rc;
4548 
4549 	MPASS(!(eq->flags & EQ_SW_ALLOCATED));
4550 
4551 	rc = alloc_eq(sc, eq, ctx, oid);
4552 	if (rc)
4553 		return (rc);
4554 	MPASS(eq->flags & EQ_SW_ALLOCATED);
4555 	/* Can't fail after this. */
4556 
4557 	wrq->adapter = sc;
4558 	TASK_INIT(&wrq->wrq_tx_task, 0, wrq_tx_drain, wrq);
4559 	TAILQ_INIT(&wrq->incomplete_wrs);
4560 	STAILQ_INIT(&wrq->wr_list);
4561 	wrq->nwr_pending = 0;
4562 	wrq->ndesc_needed = 0;
4563 	add_wrq_sysctls(ctx, oid, wrq);
4564 
4565 	return (0);
4566 }
4567 
4568 static void
4569 free_wrq(struct adapter *sc, struct sge_wrq *wrq)
4570 {
4571 	free_eq(sc, &wrq->eq);
4572 	MPASS(wrq->nwr_pending == 0);
4573 	MPASS(TAILQ_EMPTY(&wrq->incomplete_wrs));
4574 	MPASS(STAILQ_EMPTY(&wrq->wr_list));
4575 	bzero(wrq, sizeof(*wrq));
4576 }
4577 
4578 static void
4579 add_wrq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid,
4580     struct sge_wrq *wrq)
4581 {
4582 	struct sysctl_oid_list *children;
4583 
4584 	if (ctx == NULL || oid == NULL)
4585 		return;
4586 
4587 	children = SYSCTL_CHILDREN(oid);
4588 	SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_direct", CTLFLAG_RD,
4589 	    &wrq->tx_wrs_direct, "# of work requests (direct)");
4590 	SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_copied", CTLFLAG_RD,
4591 	    &wrq->tx_wrs_copied, "# of work requests (copied)");
4592 	SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_sspace", CTLFLAG_RD,
4593 	    &wrq->tx_wrs_ss, "# of work requests (copied from scratch space)");
4594 }
4595 
4596 /*
4597  * Idempotent.
4598  */
4599 static int
4600 alloc_txq(struct vi_info *vi, struct sge_txq *txq, int idx)
4601 {
4602 	int rc, iqidx;
4603 	struct port_info *pi = vi->pi;
4604 	struct adapter *sc = vi->adapter;
4605 	struct sge_eq *eq = &txq->eq;
4606 	struct txpkts *txp;
4607 	char name[16];
4608 	struct sysctl_oid *oid;
4609 
4610 	if (!(eq->flags & EQ_SW_ALLOCATED)) {
4611 		MPASS(!(eq->flags & EQ_HW_ALLOCATED));
4612 
4613 		snprintf(name, sizeof(name), "%d", idx);
4614 		oid = SYSCTL_ADD_NODE(&vi->ctx, SYSCTL_CHILDREN(vi->txq_oid),
4615 		    OID_AUTO, name, CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
4616 		    "tx queue");
4617 
4618 		iqidx = vi->first_rxq + (idx % vi->nrxq);
4619 		snprintf(name, sizeof(name), "%s txq%d",
4620 		    device_get_nameunit(vi->dev), idx);
4621 		init_eq(sc, &txq->eq, EQ_ETH, vi->qsize_txq, pi->tx_chan,
4622 		    &sc->sge.rxq[iqidx].iq, name);
4623 
4624 		rc = mp_ring_alloc(&txq->r, eq->sidx, txq, eth_tx,
4625 		    can_resume_eth_tx, M_CXGBE, &eq->eq_lock, M_WAITOK);
4626 		if (rc != 0) {
4627 			CH_ERR(vi, "failed to allocate mp_ring for txq%d: %d\n",
4628 			    idx, rc);
4629 failed:
4630 			sysctl_remove_oid(oid, 1, 1);
4631 			return (rc);
4632 		}
4633 
4634 		rc = alloc_eq(sc, eq, &vi->ctx, oid);
4635 		if (rc) {
4636 			CH_ERR(vi, "failed to allocate txq%d: %d\n", idx, rc);
4637 			mp_ring_free(txq->r);
4638 			goto failed;
4639 		}
4640 		MPASS(eq->flags & EQ_SW_ALLOCATED);
4641 		/* Can't fail after this point. */
4642 
4643 		TASK_INIT(&txq->tx_reclaim_task, 0, tx_reclaim, eq);
4644 		txq->ifp = vi->ifp;
4645 		txq->gl = sglist_alloc(TX_SGL_SEGS, M_WAITOK);
4646 		txq->sdesc = malloc(eq->sidx * sizeof(struct tx_sdesc), M_CXGBE,
4647 		    M_ZERO | M_WAITOK);
4648 
4649 		add_txq_sysctls(vi, &vi->ctx, oid, txq);
4650 	}
4651 
4652 	if (!(eq->flags & EQ_HW_ALLOCATED)) {
4653 		MPASS(eq->flags & EQ_SW_ALLOCATED);
4654 		rc = alloc_eq_hwq(sc, vi, eq);
4655 		if (rc != 0) {
4656 			CH_ERR(vi, "failed to create hw txq%d: %d\n", idx, rc);
4657 			return (rc);
4658 		}
4659 		MPASS(eq->flags & EQ_HW_ALLOCATED);
4660 		/* Can't fail after this point. */
4661 
4662 		if (idx == 0)
4663 			sc->sge.eq_base = eq->abs_id - eq->cntxt_id;
4664 		else
4665 			KASSERT(eq->cntxt_id + sc->sge.eq_base == eq->abs_id,
4666 			    ("eq_base mismatch"));
4667 		KASSERT(sc->sge.eq_base == 0 || sc->flags & IS_VF,
4668 		    ("PF with non-zero eq_base"));
4669 
4670 		txp = &txq->txp;
4671 		MPASS(nitems(txp->mb) >= sc->params.max_pkts_per_eth_tx_pkts_wr);
4672 		txq->txp.max_npkt = min(nitems(txp->mb),
4673 		    sc->params.max_pkts_per_eth_tx_pkts_wr);
4674 		if (vi->flags & TX_USES_VM_WR && !(sc->flags & IS_VF))
4675 			txq->txp.max_npkt--;
4676 
4677 		if (vi->flags & TX_USES_VM_WR)
4678 			txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) |
4679 			    V_TXPKT_INTF(pi->tx_chan));
4680 		else
4681 			txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) |
4682 			    V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(sc->pf) |
4683 			    V_TXPKT_VF(vi->vin) | V_TXPKT_VF_VLD(vi->vfvld));
4684 
4685 		txq->tc_idx = -1;
4686 	}
4687 
4688 	return (0);
4689 }
4690 
4691 /*
4692  * Idempotent.
4693  */
4694 static void
4695 free_txq(struct vi_info *vi, struct sge_txq *txq)
4696 {
4697 	struct adapter *sc = vi->adapter;
4698 	struct sge_eq *eq = &txq->eq;
4699 
4700 	if (eq->flags & EQ_HW_ALLOCATED) {
4701 		MPASS(eq->flags & EQ_SW_ALLOCATED);
4702 		free_eq_hwq(sc, NULL, eq);
4703 		MPASS(!(eq->flags & EQ_HW_ALLOCATED));
4704 	}
4705 
4706 	if (eq->flags & EQ_SW_ALLOCATED) {
4707 		MPASS(!(eq->flags & EQ_HW_ALLOCATED));
4708 		sglist_free(txq->gl);
4709 		free(txq->sdesc, M_CXGBE);
4710 		mp_ring_free(txq->r);
4711 		free_eq(sc, eq);
4712 		MPASS(!(eq->flags & EQ_SW_ALLOCATED));
4713 		bzero(txq, sizeof(*txq));
4714 	}
4715 }
4716 
4717 static void
4718 add_txq_sysctls(struct vi_info *vi, struct sysctl_ctx_list *ctx,
4719     struct sysctl_oid *oid, struct sge_txq *txq)
4720 {
4721 	struct adapter *sc;
4722 	struct sysctl_oid_list *children;
4723 
4724 	if (ctx == NULL || oid == NULL)
4725 		return;
4726 
4727 	sc = vi->adapter;
4728 	children = SYSCTL_CHILDREN(oid);
4729 
4730 	mp_ring_sysctls(txq->r, ctx, children);
4731 
4732 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tc",
4733 	    CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, txq - sc->sge.txq,
4734 	    sysctl_tc, "I", "traffic class (-1 means none)");
4735 
4736 	SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txcsum", CTLFLAG_RD,
4737 	    &txq->txcsum, "# of times hardware assisted with checksum");
4738 	SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "vlan_insertion", CTLFLAG_RD,
4739 	    &txq->vlan_insertion, "# of times hardware inserted 802.1Q tag");
4740 	SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tso_wrs", CTLFLAG_RD,
4741 	    &txq->tso_wrs, "# of TSO work requests");
4742 	SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "imm_wrs", CTLFLAG_RD,
4743 	    &txq->imm_wrs, "# of work requests with immediate data");
4744 	SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "sgl_wrs", CTLFLAG_RD,
4745 	    &txq->sgl_wrs, "# of work requests with direct SGL");
4746 	SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkt_wrs", CTLFLAG_RD,
4747 	    &txq->txpkt_wrs, "# of txpkt work requests (one pkt/WR)");
4748 	SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkts0_wrs", CTLFLAG_RD,
4749 	    &txq->txpkts0_wrs, "# of txpkts (type 0) work requests");
4750 	SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkts1_wrs", CTLFLAG_RD,
4751 	    &txq->txpkts1_wrs, "# of txpkts (type 1) work requests");
4752 	SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkts0_pkts", CTLFLAG_RD,
4753 	    &txq->txpkts0_pkts,
4754 	    "# of frames tx'd using type0 txpkts work requests");
4755 	SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkts1_pkts", CTLFLAG_RD,
4756 	    &txq->txpkts1_pkts,
4757 	    "# of frames tx'd using type1 txpkts work requests");
4758 	SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkts_flush", CTLFLAG_RD,
4759 	    &txq->txpkts_flush,
4760 	    "# of times txpkts had to be flushed out by an egress-update");
4761 	SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "raw_wrs", CTLFLAG_RD,
4762 	    &txq->raw_wrs, "# of raw work requests (non-packets)");
4763 	SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "vxlan_tso_wrs", CTLFLAG_RD,
4764 	    &txq->vxlan_tso_wrs, "# of VXLAN TSO work requests");
4765 	SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "vxlan_txcsum", CTLFLAG_RD,
4766 	    &txq->vxlan_txcsum,
4767 	    "# of times hardware assisted with inner checksums (VXLAN)");
4768 
4769 #ifdef KERN_TLS
4770 	if (is_ktls(sc)) {
4771 		SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_records",
4772 		    CTLFLAG_RD, &txq->kern_tls_records,
4773 		    "# of NIC TLS records transmitted");
4774 		SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_short",
4775 		    CTLFLAG_RD, &txq->kern_tls_short,
4776 		    "# of short NIC TLS records transmitted");
4777 		SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_partial",
4778 		    CTLFLAG_RD, &txq->kern_tls_partial,
4779 		    "# of partial NIC TLS records transmitted");
4780 		SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_full",
4781 		    CTLFLAG_RD, &txq->kern_tls_full,
4782 		    "# of full NIC TLS records transmitted");
4783 		SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_octets",
4784 		    CTLFLAG_RD, &txq->kern_tls_octets,
4785 		    "# of payload octets in transmitted NIC TLS records");
4786 		SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_waste",
4787 		    CTLFLAG_RD, &txq->kern_tls_waste,
4788 		    "# of octets DMAd but not transmitted in NIC TLS records");
4789 		SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_options",
4790 		    CTLFLAG_RD, &txq->kern_tls_options,
4791 		    "# of NIC TLS options-only packets transmitted");
4792 		SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_header",
4793 		    CTLFLAG_RD, &txq->kern_tls_header,
4794 		    "# of NIC TLS header-only packets transmitted");
4795 		SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_fin",
4796 		    CTLFLAG_RD, &txq->kern_tls_fin,
4797 		    "# of NIC TLS FIN-only packets transmitted");
4798 		SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_fin_short",
4799 		    CTLFLAG_RD, &txq->kern_tls_fin_short,
4800 		    "# of NIC TLS padded FIN packets on short TLS records");
4801 		SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_cbc",
4802 		    CTLFLAG_RD, &txq->kern_tls_cbc,
4803 		    "# of NIC TLS sessions using AES-CBC");
4804 		SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_gcm",
4805 		    CTLFLAG_RD, &txq->kern_tls_gcm,
4806 		    "# of NIC TLS sessions using AES-GCM");
4807 	}
4808 #endif
4809 }
4810 
4811 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
4812 /*
4813  * Idempotent.
4814  */
4815 static int
4816 alloc_ofld_txq(struct vi_info *vi, struct sge_ofld_txq *ofld_txq, int idx)
4817 {
4818 	struct sysctl_oid *oid;
4819 	struct port_info *pi = vi->pi;
4820 	struct adapter *sc = vi->adapter;
4821 	struct sge_eq *eq = &ofld_txq->wrq.eq;
4822 	int rc, iqidx;
4823 	char name[16];
4824 
4825 	MPASS(idx >= 0);
4826 	MPASS(idx < vi->nofldtxq);
4827 
4828 	if (!(eq->flags & EQ_SW_ALLOCATED)) {
4829 		snprintf(name, sizeof(name), "%d", idx);
4830 		oid = SYSCTL_ADD_NODE(&vi->ctx,
4831 		    SYSCTL_CHILDREN(vi->ofld_txq_oid), OID_AUTO, name,
4832 		    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "offload tx queue");
4833 
4834 		snprintf(name, sizeof(name), "%s ofld_txq%d",
4835 		    device_get_nameunit(vi->dev), idx);
4836 		if (vi->nofldrxq > 0) {
4837 			iqidx = vi->first_ofld_rxq + (idx % vi->nofldrxq);
4838 			init_eq(sc, eq, EQ_OFLD, vi->qsize_txq, pi->tx_chan,
4839 			    &sc->sge.ofld_rxq[iqidx].iq, name);
4840 		} else {
4841 			iqidx = vi->first_rxq + (idx % vi->nrxq);
4842 			init_eq(sc, eq, EQ_OFLD, vi->qsize_txq, pi->tx_chan,
4843 			    &sc->sge.rxq[iqidx].iq, name);
4844 		}
4845 
4846 		rc = alloc_wrq(sc, vi, &ofld_txq->wrq, &vi->ctx, oid);
4847 		if (rc != 0) {
4848 			CH_ERR(vi, "failed to allocate ofld_txq%d: %d\n", idx,
4849 			    rc);
4850 			sysctl_remove_oid(oid, 1, 1);
4851 			return (rc);
4852 		}
4853 		MPASS(eq->flags & EQ_SW_ALLOCATED);
4854 		/* Can't fail after this point. */
4855 
4856 		ofld_txq->tx_iscsi_pdus = counter_u64_alloc(M_WAITOK);
4857 		ofld_txq->tx_iscsi_octets = counter_u64_alloc(M_WAITOK);
4858 		ofld_txq->tx_iscsi_iso_wrs = counter_u64_alloc(M_WAITOK);
4859 		ofld_txq->tx_toe_tls_records = counter_u64_alloc(M_WAITOK);
4860 		ofld_txq->tx_toe_tls_octets = counter_u64_alloc(M_WAITOK);
4861 		add_ofld_txq_sysctls(&vi->ctx, oid, ofld_txq);
4862 	}
4863 
4864 	if (!(eq->flags & EQ_HW_ALLOCATED)) {
4865 		rc = alloc_eq_hwq(sc, vi, eq);
4866 		if (rc != 0) {
4867 			CH_ERR(vi, "failed to create hw ofld_txq%d: %d\n", idx,
4868 			    rc);
4869 			return (rc);
4870 		}
4871 		MPASS(eq->flags & EQ_HW_ALLOCATED);
4872 	}
4873 
4874 	return (0);
4875 }
4876 
4877 /*
4878  * Idempotent.
4879  */
4880 static void
4881 free_ofld_txq(struct vi_info *vi, struct sge_ofld_txq *ofld_txq)
4882 {
4883 	struct adapter *sc = vi->adapter;
4884 	struct sge_eq *eq = &ofld_txq->wrq.eq;
4885 
4886 	if (eq->flags & EQ_HW_ALLOCATED) {
4887 		MPASS(eq->flags & EQ_SW_ALLOCATED);
4888 		free_eq_hwq(sc, NULL, eq);
4889 		MPASS(!(eq->flags & EQ_HW_ALLOCATED));
4890 	}
4891 
4892 	if (eq->flags & EQ_SW_ALLOCATED) {
4893 		MPASS(!(eq->flags & EQ_HW_ALLOCATED));
4894 		counter_u64_free(ofld_txq->tx_iscsi_pdus);
4895 		counter_u64_free(ofld_txq->tx_iscsi_octets);
4896 		counter_u64_free(ofld_txq->tx_iscsi_iso_wrs);
4897 		counter_u64_free(ofld_txq->tx_toe_tls_records);
4898 		counter_u64_free(ofld_txq->tx_toe_tls_octets);
4899 		free_wrq(sc, &ofld_txq->wrq);
4900 		MPASS(!(eq->flags & EQ_SW_ALLOCATED));
4901 		bzero(ofld_txq, sizeof(*ofld_txq));
4902 	}
4903 }
4904 
4905 static void
4906 add_ofld_txq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid,
4907     struct sge_ofld_txq *ofld_txq)
4908 {
4909 	struct sysctl_oid_list *children;
4910 
4911 	if (ctx == NULL || oid == NULL)
4912 		return;
4913 
4914 	children = SYSCTL_CHILDREN(oid);
4915 	SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_iscsi_pdus",
4916 	    CTLFLAG_RD, &ofld_txq->tx_iscsi_pdus,
4917 	    "# of iSCSI PDUs transmitted");
4918 	SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_iscsi_octets",
4919 	    CTLFLAG_RD, &ofld_txq->tx_iscsi_octets,
4920 	    "# of payload octets in transmitted iSCSI PDUs");
4921 	SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_iscsi_iso_wrs",
4922 	    CTLFLAG_RD, &ofld_txq->tx_iscsi_iso_wrs,
4923 	    "# of iSCSI segmentation offload work requests");
4924 	SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_toe_tls_records",
4925 	    CTLFLAG_RD, &ofld_txq->tx_toe_tls_records,
4926 	    "# of TOE TLS records transmitted");
4927 	SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_toe_tls_octets",
4928 	    CTLFLAG_RD, &ofld_txq->tx_toe_tls_octets,
4929 	    "# of payload octets in transmitted TOE TLS records");
4930 }
4931 #endif
4932 
4933 static void
4934 oneseg_dma_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error)
4935 {
4936 	bus_addr_t *ba = arg;
4937 
4938 	KASSERT(nseg == 1,
4939 	    ("%s meant for single segment mappings only.", __func__));
4940 
4941 	*ba = error ? 0 : segs->ds_addr;
4942 }
4943 
4944 static inline void
4945 ring_fl_db(struct adapter *sc, struct sge_fl *fl)
4946 {
4947 	uint32_t n, v;
4948 
4949 	n = IDXDIFF(fl->pidx >> 3, fl->dbidx, fl->sidx);
4950 	MPASS(n > 0);
4951 
4952 	wmb();
4953 	v = fl->dbval | V_PIDX(n);
4954 	if (fl->udb)
4955 		*fl->udb = htole32(v);
4956 	else
4957 		t4_write_reg(sc, sc->sge_kdoorbell_reg, v);
4958 	IDXINCR(fl->dbidx, n, fl->sidx);
4959 }
4960 
4961 /*
4962  * Fills up the freelist by allocating up to 'n' buffers.  Buffers that are
4963  * recycled do not count towards this allocation budget.
4964  *
4965  * Returns non-zero to indicate that this freelist should be added to the list
4966  * of starving freelists.
4967  */
4968 static int
4969 refill_fl(struct adapter *sc, struct sge_fl *fl, int n)
4970 {
4971 	__be64 *d;
4972 	struct fl_sdesc *sd;
4973 	uintptr_t pa;
4974 	caddr_t cl;
4975 	struct rx_buf_info *rxb;
4976 	struct cluster_metadata *clm;
4977 	uint16_t max_pidx, zidx = fl->zidx;
4978 	uint16_t hw_cidx = fl->hw_cidx;		/* stable snapshot */
4979 
4980 	FL_LOCK_ASSERT_OWNED(fl);
4981 
4982 	/*
4983 	 * We always stop at the beginning of the hardware descriptor that's just
4984 	 * before the one with the hw cidx.  This is to avoid hw pidx = hw cidx,
4985 	 * which would mean an empty freelist to the chip.
4986 	 */
4987 	max_pidx = __predict_false(hw_cidx == 0) ? fl->sidx - 1 : hw_cidx - 1;
4988 	if (fl->pidx == max_pidx * 8)
4989 		return (0);
4990 
4991 	d = &fl->desc[fl->pidx];
4992 	sd = &fl->sdesc[fl->pidx];
4993 	rxb = &sc->sge.rx_buf_info[zidx];
4994 
4995 	while (n > 0) {
4996 
4997 		if (sd->cl != NULL) {
4998 
4999 			if (sd->nmbuf == 0) {
5000 				/*
5001 				 * Fast recycle without involving any atomics on
5002 				 * the cluster's metadata (if the cluster has
5003 				 * metadata).  This happens when all frames
5004 				 * received in the cluster were small enough to
5005 				 * fit within a single mbuf each.
5006 				 */
5007 				fl->cl_fast_recycled++;
5008 				goto recycled;
5009 			}
5010 
5011 			/*
5012 			 * Cluster is guaranteed to have metadata.  Clusters
5013 			 * without metadata always take the fast recycle path
5014 			 * when they're recycled.
5015 			 */
5016 			clm = cl_metadata(sd);
5017 			MPASS(clm != NULL);
5018 
5019 			if (atomic_fetchadd_int(&clm->refcount, -1) == 1) {
5020 				fl->cl_recycled++;
5021 				counter_u64_add(extfree_rels, 1);
5022 				goto recycled;
5023 			}
5024 			sd->cl = NULL;	/* gave up my reference */
5025 		}
5026 		MPASS(sd->cl == NULL);
5027 		cl = uma_zalloc(rxb->zone, M_NOWAIT);
5028 		if (__predict_false(cl == NULL)) {
5029 			if (zidx != fl->safe_zidx) {
5030 				zidx = fl->safe_zidx;
5031 				rxb = &sc->sge.rx_buf_info[zidx];
5032 				cl = uma_zalloc(rxb->zone, M_NOWAIT);
5033 			}
5034 			if (cl == NULL)
5035 				break;
5036 		}
5037 		fl->cl_allocated++;
5038 		n--;
5039 
5040 		pa = pmap_kextract((vm_offset_t)cl);
5041 		sd->cl = cl;
5042 		sd->zidx = zidx;
5043 
5044 		if (fl->flags & FL_BUF_PACKING) {
5045 			*d = htobe64(pa | rxb->hwidx2);
5046 			sd->moff = rxb->size2;
5047 		} else {
5048 			*d = htobe64(pa | rxb->hwidx1);
5049 			sd->moff = 0;
5050 		}
5051 recycled:
5052 		sd->nmbuf = 0;
5053 		d++;
5054 		sd++;
5055 		if (__predict_false((++fl->pidx & 7) == 0)) {
5056 			uint16_t pidx = fl->pidx >> 3;
5057 
5058 			if (__predict_false(pidx == fl->sidx)) {
5059 				fl->pidx = 0;
5060 				pidx = 0;
5061 				sd = fl->sdesc;
5062 				d = fl->desc;
5063 			}
5064 			if (n < 8 || pidx == max_pidx)
5065 				break;
5066 
5067 			if (IDXDIFF(pidx, fl->dbidx, fl->sidx) >= 4)
5068 				ring_fl_db(sc, fl);
5069 		}
5070 	}
5071 
5072 	if ((fl->pidx >> 3) != fl->dbidx)
5073 		ring_fl_db(sc, fl);
5074 
5075 	return (FL_RUNNING_LOW(fl) && !(fl->flags & FL_STARVING));
5076 }
5077 
5078 /*
5079  * Attempt to refill all starving freelists.
5080  */
5081 static void
5082 refill_sfl(void *arg)
5083 {
5084 	struct adapter *sc = arg;
5085 	struct sge_fl *fl, *fl_temp;
5086 
5087 	mtx_assert(&sc->sfl_lock, MA_OWNED);
5088 	TAILQ_FOREACH_SAFE(fl, &sc->sfl, link, fl_temp) {
5089 		FL_LOCK(fl);
5090 		refill_fl(sc, fl, 64);
5091 		if (FL_NOT_RUNNING_LOW(fl) || fl->flags & FL_DOOMED) {
5092 			TAILQ_REMOVE(&sc->sfl, fl, link);
5093 			fl->flags &= ~FL_STARVING;
5094 		}
5095 		FL_UNLOCK(fl);
5096 	}
5097 
5098 	if (!TAILQ_EMPTY(&sc->sfl))
5099 		callout_schedule(&sc->sfl_callout, hz / 5);
5100 }
5101 
5102 /*
5103  * Release the driver's reference on all buffers in the given freelist.  Buffers
5104  * with kernel references cannot be freed and will prevent the driver from being
5105  * unloaded safely.
5106  */
5107 void
5108 free_fl_buffers(struct adapter *sc, struct sge_fl *fl)
5109 {
5110 	struct fl_sdesc *sd;
5111 	struct cluster_metadata *clm;
5112 	int i;
5113 
5114 	sd = fl->sdesc;
5115 	for (i = 0; i < fl->sidx * 8; i++, sd++) {
5116 		if (sd->cl == NULL)
5117 			continue;
5118 
5119 		if (sd->nmbuf == 0)
5120 			uma_zfree(sc->sge.rx_buf_info[sd->zidx].zone, sd->cl);
5121 		else if (fl->flags & FL_BUF_PACKING) {
5122 			clm = cl_metadata(sd);
5123 			if (atomic_fetchadd_int(&clm->refcount, -1) == 1) {
5124 				uma_zfree(sc->sge.rx_buf_info[sd->zidx].zone,
5125 				    sd->cl);
5126 				counter_u64_add(extfree_rels, 1);
5127 			}
5128 		}
5129 		sd->cl = NULL;
5130 	}
5131 
5132 	if (fl->flags & FL_BUF_RESUME) {
5133 		m_freem(fl->m0);
5134 		fl->flags &= ~FL_BUF_RESUME;
5135 	}
5136 }
5137 
5138 static inline void
5139 get_pkt_gl(struct mbuf *m, struct sglist *gl)
5140 {
5141 	int rc;
5142 
5143 	M_ASSERTPKTHDR(m);
5144 
5145 	sglist_reset(gl);
5146 	rc = sglist_append_mbuf(gl, m);
5147 	if (__predict_false(rc != 0)) {
5148 		panic("%s: mbuf %p (%d segs) was vetted earlier but now fails "
5149 		    "with %d.", __func__, m, mbuf_nsegs(m), rc);
5150 	}
5151 
5152 	KASSERT(gl->sg_nseg == mbuf_nsegs(m),
5153 	    ("%s: nsegs changed for mbuf %p from %d to %d", __func__, m,
5154 	    mbuf_nsegs(m), gl->sg_nseg));
5155 #if 0	/* vm_wr not readily available here. */
5156 	KASSERT(gl->sg_nseg > 0 && gl->sg_nseg <= max_nsegs_allowed(m, vm_wr),
5157 	    ("%s: %d segments, should have been 1 <= nsegs <= %d", __func__,
5158 		gl->sg_nseg, max_nsegs_allowed(m, vm_wr)));
5159 #endif
5160 }
5161 
5162 /*
5163  * len16 for a txpkt WR with a GL.  Includes the firmware work request header.
5164  */
5165 static inline u_int
5166 txpkt_len16(u_int nsegs, const u_int extra)
5167 {
5168 	u_int n;
5169 
5170 	MPASS(nsegs > 0);
5171 
5172 	nsegs--; /* first segment is part of ulptx_sgl */
5173 	n = extra + sizeof(struct fw_eth_tx_pkt_wr) +
5174 	    sizeof(struct cpl_tx_pkt_core) +
5175 	    sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1));
5176 
5177 	return (howmany(n, 16));
5178 }
5179 
5180 /*
5181  * len16 for a txpkt_vm WR with a GL.  Includes the firmware work
5182  * request header.
5183  */
5184 static inline u_int
5185 txpkt_vm_len16(u_int nsegs, const u_int extra)
5186 {
5187 	u_int n;
5188 
5189 	MPASS(nsegs > 0);
5190 
5191 	nsegs--; /* first segment is part of ulptx_sgl */
5192 	n = extra + sizeof(struct fw_eth_tx_pkt_vm_wr) +
5193 	    sizeof(struct cpl_tx_pkt_core) +
5194 	    sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1));
5195 
5196 	return (howmany(n, 16));
5197 }
5198 
5199 static inline void
5200 calculate_mbuf_len16(struct mbuf *m, bool vm_wr)
5201 {
5202 	const int lso = sizeof(struct cpl_tx_pkt_lso_core);
5203 	const int tnl_lso = sizeof(struct cpl_tx_tnl_lso);
5204 
5205 	if (vm_wr) {
5206 		if (needs_tso(m))
5207 			set_mbuf_len16(m, txpkt_vm_len16(mbuf_nsegs(m), lso));
5208 		else
5209 			set_mbuf_len16(m, txpkt_vm_len16(mbuf_nsegs(m), 0));
5210 		return;
5211 	}
5212 
5213 	if (needs_tso(m)) {
5214 		if (needs_vxlan_tso(m))
5215 			set_mbuf_len16(m, txpkt_len16(mbuf_nsegs(m), tnl_lso));
5216 		else
5217 			set_mbuf_len16(m, txpkt_len16(mbuf_nsegs(m), lso));
5218 	} else
5219 		set_mbuf_len16(m, txpkt_len16(mbuf_nsegs(m), 0));
5220 }
5221 
5222 /*
5223  * len16 for a txpkts type 0 WR with a GL.  Does not include the firmware work
5224  * request header.
5225  */
5226 static inline u_int
5227 txpkts0_len16(u_int nsegs)
5228 {
5229 	u_int n;
5230 
5231 	MPASS(nsegs > 0);
5232 
5233 	nsegs--; /* first segment is part of ulptx_sgl */
5234 	n = sizeof(struct ulp_txpkt) + sizeof(struct ulptx_idata) +
5235 	    sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl) +
5236 	    8 * ((3 * nsegs) / 2 + (nsegs & 1));
5237 
5238 	return (howmany(n, 16));
5239 }
5240 
5241 /*
5242  * len16 for a txpkts type 1 WR with a GL.  Does not include the firmware work
5243  * request header.
5244  */
5245 static inline u_int
5246 txpkts1_len16(void)
5247 {
5248 	u_int n;
5249 
5250 	n = sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl);
5251 
5252 	return (howmany(n, 16));
5253 }
5254 
5255 static inline u_int
5256 imm_payload(u_int ndesc)
5257 {
5258 	u_int n;
5259 
5260 	n = ndesc * EQ_ESIZE - sizeof(struct fw_eth_tx_pkt_wr) -
5261 	    sizeof(struct cpl_tx_pkt_core);
5262 
5263 	return (n);
5264 }
5265 
5266 static inline uint64_t
5267 csum_to_ctrl(struct adapter *sc, struct mbuf *m)
5268 {
5269 	uint64_t ctrl;
5270 	int csum_type, l2hlen, l3hlen;
5271 	int x, y;
5272 	static const int csum_types[3][2] = {
5273 		{TX_CSUM_TCPIP, TX_CSUM_TCPIP6},
5274 		{TX_CSUM_UDPIP, TX_CSUM_UDPIP6},
5275 		{TX_CSUM_IP, 0}
5276 	};
5277 
5278 	M_ASSERTPKTHDR(m);
5279 
5280 	if (!needs_hwcsum(m))
5281 		return (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS);
5282 
5283 	MPASS(m->m_pkthdr.l2hlen >= ETHER_HDR_LEN);
5284 	MPASS(m->m_pkthdr.l3hlen >= sizeof(struct ip));
5285 
5286 	if (needs_vxlan_csum(m)) {
5287 		MPASS(m->m_pkthdr.l4hlen > 0);
5288 		MPASS(m->m_pkthdr.l5hlen > 0);
5289 		MPASS(m->m_pkthdr.inner_l2hlen >= ETHER_HDR_LEN);
5290 		MPASS(m->m_pkthdr.inner_l3hlen >= sizeof(struct ip));
5291 
5292 		l2hlen = m->m_pkthdr.l2hlen + m->m_pkthdr.l3hlen +
5293 		    m->m_pkthdr.l4hlen + m->m_pkthdr.l5hlen +
5294 		    m->m_pkthdr.inner_l2hlen - ETHER_HDR_LEN;
5295 		l3hlen = m->m_pkthdr.inner_l3hlen;
5296 	} else {
5297 		l2hlen = m->m_pkthdr.l2hlen - ETHER_HDR_LEN;
5298 		l3hlen = m->m_pkthdr.l3hlen;
5299 	}
5300 
5301 	ctrl = 0;
5302 	if (!needs_l3_csum(m))
5303 		ctrl |= F_TXPKT_IPCSUM_DIS;
5304 
5305 	if (m->m_pkthdr.csum_flags & (CSUM_IP_TCP | CSUM_INNER_IP_TCP |
5306 	    CSUM_IP6_TCP | CSUM_INNER_IP6_TCP))
5307 		x = 0;	/* TCP */
5308 	else if (m->m_pkthdr.csum_flags & (CSUM_IP_UDP | CSUM_INNER_IP_UDP |
5309 	    CSUM_IP6_UDP | CSUM_INNER_IP6_UDP))
5310 		x = 1;	/* UDP */
5311 	else
5312 		x = 2;
5313 
5314 	if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_IP_TCP | CSUM_IP_UDP |
5315 	    CSUM_INNER_IP | CSUM_INNER_IP_TCP | CSUM_INNER_IP_UDP))
5316 		y = 0;	/* IPv4 */
5317 	else {
5318 		MPASS(m->m_pkthdr.csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP |
5319 		    CSUM_INNER_IP6_TCP | CSUM_INNER_IP6_UDP));
5320 		y = 1;	/* IPv6 */
5321 	}
5322 	/*
5323 	 * needs_hwcsum returned true earlier so there must be some kind of
5324 	 * checksum to calculate.
5325 	 */
5326 	csum_type = csum_types[x][y];
5327 	MPASS(csum_type != 0);
5328 	if (csum_type == TX_CSUM_IP)
5329 		ctrl |= F_TXPKT_L4CSUM_DIS;
5330 	ctrl |= V_TXPKT_CSUM_TYPE(csum_type) | V_TXPKT_IPHDR_LEN(l3hlen);
5331 	if (chip_id(sc) <= CHELSIO_T5)
5332 		ctrl |= V_TXPKT_ETHHDR_LEN(l2hlen);
5333 	else
5334 		ctrl |= V_T6_TXPKT_ETHHDR_LEN(l2hlen);
5335 
5336 	return (ctrl);
5337 }
5338 
5339 static inline void *
5340 write_lso_cpl(void *cpl, struct mbuf *m0)
5341 {
5342 	struct cpl_tx_pkt_lso_core *lso;
5343 	uint32_t ctrl;
5344 
5345 	KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 &&
5346 	    m0->m_pkthdr.l4hlen > 0,
5347 	    ("%s: mbuf %p needs TSO but missing header lengths",
5348 		__func__, m0));
5349 
5350 	ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) |
5351 	    F_LSO_FIRST_SLICE | F_LSO_LAST_SLICE |
5352 	    V_LSO_ETHHDR_LEN((m0->m_pkthdr.l2hlen - ETHER_HDR_LEN) >> 2) |
5353 	    V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) |
5354 	    V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2);
5355 	if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr))
5356 		ctrl |= F_LSO_IPV6;
5357 
5358 	lso = cpl;
5359 	lso->lso_ctrl = htobe32(ctrl);
5360 	lso->ipid_ofst = htobe16(0);
5361 	lso->mss = htobe16(m0->m_pkthdr.tso_segsz);
5362 	lso->seqno_offset = htobe32(0);
5363 	lso->len = htobe32(m0->m_pkthdr.len);
5364 
5365 	return (lso + 1);
5366 }
5367 
5368 static void *
5369 write_tnl_lso_cpl(void *cpl, struct mbuf *m0)
5370 {
5371 	struct cpl_tx_tnl_lso *tnl_lso = cpl;
5372 	uint32_t ctrl;
5373 
5374 	KASSERT(m0->m_pkthdr.inner_l2hlen > 0 &&
5375 	    m0->m_pkthdr.inner_l3hlen > 0 && m0->m_pkthdr.inner_l4hlen > 0 &&
5376 	    m0->m_pkthdr.inner_l5hlen > 0,
5377 	    ("%s: mbuf %p needs VXLAN_TSO but missing inner header lengths",
5378 		__func__, m0));
5379 	KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 &&
5380 	    m0->m_pkthdr.l4hlen > 0 && m0->m_pkthdr.l5hlen > 0,
5381 	    ("%s: mbuf %p needs VXLAN_TSO but missing outer header lengths",
5382 		__func__, m0));
5383 
5384 	/* Outer headers. */
5385 	ctrl = V_CPL_TX_TNL_LSO_OPCODE(CPL_TX_TNL_LSO) |
5386 	    F_CPL_TX_TNL_LSO_FIRST | F_CPL_TX_TNL_LSO_LAST |
5387 	    V_CPL_TX_TNL_LSO_ETHHDRLENOUT(
5388 		(m0->m_pkthdr.l2hlen - ETHER_HDR_LEN) >> 2) |
5389 	    V_CPL_TX_TNL_LSO_IPHDRLENOUT(m0->m_pkthdr.l3hlen >> 2) |
5390 	    F_CPL_TX_TNL_LSO_IPLENSETOUT;
5391 	if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr))
5392 		ctrl |= F_CPL_TX_TNL_LSO_IPV6OUT;
5393 	else {
5394 		ctrl |= F_CPL_TX_TNL_LSO_IPHDRCHKOUT |
5395 		    F_CPL_TX_TNL_LSO_IPIDINCOUT;
5396 	}
5397 	tnl_lso->op_to_IpIdSplitOut = htobe32(ctrl);
5398 	tnl_lso->IpIdOffsetOut = 0;
5399 	tnl_lso->UdpLenSetOut_to_TnlHdrLen =
5400 		htobe16(F_CPL_TX_TNL_LSO_UDPCHKCLROUT |
5401 		    F_CPL_TX_TNL_LSO_UDPLENSETOUT |
5402 		    V_CPL_TX_TNL_LSO_TNLHDRLEN(m0->m_pkthdr.l2hlen +
5403 			m0->m_pkthdr.l3hlen + m0->m_pkthdr.l4hlen +
5404 			m0->m_pkthdr.l5hlen) |
5405 		    V_CPL_TX_TNL_LSO_TNLTYPE(TX_TNL_TYPE_VXLAN));
5406 	tnl_lso->r1 = 0;
5407 
5408 	/* Inner headers. */
5409 	ctrl = V_CPL_TX_TNL_LSO_ETHHDRLEN(
5410 	    (m0->m_pkthdr.inner_l2hlen - ETHER_HDR_LEN) >> 2) |
5411 	    V_CPL_TX_TNL_LSO_IPHDRLEN(m0->m_pkthdr.inner_l3hlen >> 2) |
5412 	    V_CPL_TX_TNL_LSO_TCPHDRLEN(m0->m_pkthdr.inner_l4hlen >> 2);
5413 	if (m0->m_pkthdr.inner_l3hlen == sizeof(struct ip6_hdr))
5414 		ctrl |= F_CPL_TX_TNL_LSO_IPV6;
5415 	tnl_lso->Flow_to_TcpHdrLen = htobe32(ctrl);
5416 	tnl_lso->IpIdOffset = 0;
5417 	tnl_lso->IpIdSplit_to_Mss =
5418 	    htobe16(V_CPL_TX_TNL_LSO_MSS(m0->m_pkthdr.tso_segsz));
5419 	tnl_lso->TCPSeqOffset = 0;
5420 	tnl_lso->EthLenOffset_Size =
5421 	    htobe32(V_CPL_TX_TNL_LSO_SIZE(m0->m_pkthdr.len));
5422 
5423 	return (tnl_lso + 1);
5424 }
5425 
5426 #define VM_TX_L2HDR_LEN	16	/* ethmacdst to vlantci */
5427 
5428 /*
5429  * Write a VM txpkt WR for this packet to the hardware descriptors, update the
5430  * software descriptor, and advance the pidx.  It is guaranteed that enough
5431  * descriptors are available.
5432  *
5433  * The return value is the # of hardware descriptors used.
5434  */
5435 static u_int
5436 write_txpkt_vm_wr(struct adapter *sc, struct sge_txq *txq, struct mbuf *m0)
5437 {
5438 	struct sge_eq *eq;
5439 	struct fw_eth_tx_pkt_vm_wr *wr;
5440 	struct tx_sdesc *txsd;
5441 	struct cpl_tx_pkt_core *cpl;
5442 	uint32_t ctrl;	/* used in many unrelated places */
5443 	uint64_t ctrl1;
5444 	int len16, ndesc, pktlen;
5445 	caddr_t dst;
5446 
5447 	TXQ_LOCK_ASSERT_OWNED(txq);
5448 	M_ASSERTPKTHDR(m0);
5449 
5450 	len16 = mbuf_len16(m0);
5451 	pktlen = m0->m_pkthdr.len;
5452 	ctrl = sizeof(struct cpl_tx_pkt_core);
5453 	if (needs_tso(m0))
5454 		ctrl += sizeof(struct cpl_tx_pkt_lso_core);
5455 	ndesc = tx_len16_to_desc(len16);
5456 
5457 	/* Firmware work request header */
5458 	eq = &txq->eq;
5459 	wr = (void *)&eq->desc[eq->pidx];
5460 	wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_VM_WR) |
5461 	    V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl));
5462 
5463 	ctrl = V_FW_WR_LEN16(len16);
5464 	wr->equiq_to_len16 = htobe32(ctrl);
5465 	wr->r3[0] = 0;
5466 	wr->r3[1] = 0;
5467 
5468 	/*
5469 	 * Copy over ethmacdst, ethmacsrc, ethtype, and vlantci.
5470 	 * vlantci is ignored unless the ethtype is 0x8100, so it's
5471 	 * simpler to always copy it rather than making it
5472 	 * conditional.  Also, it seems that we do not have to set
5473 	 * vlantci or fake the ethtype when doing VLAN tag insertion.
5474 	 */
5475 	m_copydata(m0, 0, VM_TX_L2HDR_LEN, wr->ethmacdst);
5476 
5477 	if (needs_tso(m0)) {
5478 		cpl = write_lso_cpl(wr + 1, m0);
5479 		txq->tso_wrs++;
5480 	} else
5481 		cpl = (void *)(wr + 1);
5482 
5483 	/* Checksum offload */
5484 	ctrl1 = csum_to_ctrl(sc, m0);
5485 	if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS))
5486 		txq->txcsum++;	/* some hardware assistance provided */
5487 
5488 	/* VLAN tag insertion */
5489 	if (needs_vlan_insertion(m0)) {
5490 		ctrl1 |= F_TXPKT_VLAN_VLD |
5491 		    V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag);
5492 		txq->vlan_insertion++;
5493 	}
5494 
5495 	/* CPL header */
5496 	cpl->ctrl0 = txq->cpl_ctrl0;
5497 	cpl->pack = 0;
5498 	cpl->len = htobe16(pktlen);
5499 	cpl->ctrl1 = htobe64(ctrl1);
5500 
5501 	/* SGL */
5502 	dst = (void *)(cpl + 1);
5503 
5504 	/*
5505 	 * A packet using TSO will use up an entire descriptor for the
5506 	 * firmware work request header, LSO CPL, and TX_PKT_XT CPL.
5507 	 * If this descriptor is the last descriptor in the ring, wrap
5508 	 * around to the front of the ring explicitly for the start of
5509 	 * the sgl.
5510 	 */
5511 	if (dst == (void *)&eq->desc[eq->sidx]) {
5512 		dst = (void *)&eq->desc[0];
5513 		write_gl_to_txd(txq, m0, &dst, 0);
5514 	} else
5515 		write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx);
5516 	txq->sgl_wrs++;
5517 	txq->txpkt_wrs++;
5518 
5519 	txsd = &txq->sdesc[eq->pidx];
5520 	txsd->m = m0;
5521 	txsd->desc_used = ndesc;
5522 
5523 	return (ndesc);
5524 }
5525 
5526 /*
5527  * Write a raw WR to the hardware descriptors, update the software
5528  * descriptor, and advance the pidx.  It is guaranteed that enough
5529  * descriptors are available.
5530  *
5531  * The return value is the # of hardware descriptors used.
5532  */
5533 static u_int
5534 write_raw_wr(struct sge_txq *txq, void *wr, struct mbuf *m0, u_int available)
5535 {
5536 	struct sge_eq *eq = &txq->eq;
5537 	struct tx_sdesc *txsd;
5538 	struct mbuf *m;
5539 	caddr_t dst;
5540 	int len16, ndesc;
5541 
5542 	len16 = mbuf_len16(m0);
5543 	ndesc = tx_len16_to_desc(len16);
5544 	MPASS(ndesc <= available);
5545 
5546 	dst = wr;
5547 	for (m = m0; m != NULL; m = m->m_next)
5548 		copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len);
5549 
5550 	txq->raw_wrs++;
5551 
5552 	txsd = &txq->sdesc[eq->pidx];
5553 	txsd->m = m0;
5554 	txsd->desc_used = ndesc;
5555 
5556 	return (ndesc);
5557 }
5558 
5559 /*
5560  * Write a txpkt WR for this packet to the hardware descriptors, update the
5561  * software descriptor, and advance the pidx.  It is guaranteed that enough
5562  * descriptors are available.
5563  *
5564  * The return value is the # of hardware descriptors used.
5565  */
5566 static u_int
5567 write_txpkt_wr(struct adapter *sc, struct sge_txq *txq, struct mbuf *m0,
5568     u_int available)
5569 {
5570 	struct sge_eq *eq;
5571 	struct fw_eth_tx_pkt_wr *wr;
5572 	struct tx_sdesc *txsd;
5573 	struct cpl_tx_pkt_core *cpl;
5574 	uint32_t ctrl;	/* used in many unrelated places */
5575 	uint64_t ctrl1;
5576 	int len16, ndesc, pktlen, nsegs;
5577 	caddr_t dst;
5578 
5579 	TXQ_LOCK_ASSERT_OWNED(txq);
5580 	M_ASSERTPKTHDR(m0);
5581 
5582 	len16 = mbuf_len16(m0);
5583 	nsegs = mbuf_nsegs(m0);
5584 	pktlen = m0->m_pkthdr.len;
5585 	ctrl = sizeof(struct cpl_tx_pkt_core);
5586 	if (needs_tso(m0)) {
5587 		if (needs_vxlan_tso(m0))
5588 			ctrl += sizeof(struct cpl_tx_tnl_lso);
5589 		else
5590 			ctrl += sizeof(struct cpl_tx_pkt_lso_core);
5591 	} else if (!(mbuf_cflags(m0) & MC_NOMAP) && pktlen <= imm_payload(2) &&
5592 	    available >= 2) {
5593 		/* Immediate data.  Recalculate len16 and set nsegs to 0. */
5594 		ctrl += pktlen;
5595 		len16 = howmany(sizeof(struct fw_eth_tx_pkt_wr) +
5596 		    sizeof(struct cpl_tx_pkt_core) + pktlen, 16);
5597 		nsegs = 0;
5598 	}
5599 	ndesc = tx_len16_to_desc(len16);
5600 	MPASS(ndesc <= available);
5601 
5602 	/* Firmware work request header */
5603 	eq = &txq->eq;
5604 	wr = (void *)&eq->desc[eq->pidx];
5605 	wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_WR) |
5606 	    V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl));
5607 
5608 	ctrl = V_FW_WR_LEN16(len16);
5609 	wr->equiq_to_len16 = htobe32(ctrl);
5610 	wr->r3 = 0;
5611 
5612 	if (needs_tso(m0)) {
5613 		if (needs_vxlan_tso(m0)) {
5614 			cpl = write_tnl_lso_cpl(wr + 1, m0);
5615 			txq->vxlan_tso_wrs++;
5616 		} else {
5617 			cpl = write_lso_cpl(wr + 1, m0);
5618 			txq->tso_wrs++;
5619 		}
5620 	} else
5621 		cpl = (void *)(wr + 1);
5622 
5623 	/* Checksum offload */
5624 	ctrl1 = csum_to_ctrl(sc, m0);
5625 	if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS)) {
5626 		/* some hardware assistance provided */
5627 		if (needs_vxlan_csum(m0))
5628 			txq->vxlan_txcsum++;
5629 		else
5630 			txq->txcsum++;
5631 	}
5632 
5633 	/* VLAN tag insertion */
5634 	if (needs_vlan_insertion(m0)) {
5635 		ctrl1 |= F_TXPKT_VLAN_VLD |
5636 		    V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag);
5637 		txq->vlan_insertion++;
5638 	}
5639 
5640 	/* CPL header */
5641 	cpl->ctrl0 = txq->cpl_ctrl0;
5642 	cpl->pack = 0;
5643 	cpl->len = htobe16(pktlen);
5644 	cpl->ctrl1 = htobe64(ctrl1);
5645 
5646 	/* SGL */
5647 	dst = (void *)(cpl + 1);
5648 	if (__predict_false((uintptr_t)dst == (uintptr_t)&eq->desc[eq->sidx]))
5649 		dst = (caddr_t)&eq->desc[0];
5650 	if (nsegs > 0) {
5651 
5652 		write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx);
5653 		txq->sgl_wrs++;
5654 	} else {
5655 		struct mbuf *m;
5656 
5657 		for (m = m0; m != NULL; m = m->m_next) {
5658 			copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len);
5659 #ifdef INVARIANTS
5660 			pktlen -= m->m_len;
5661 #endif
5662 		}
5663 #ifdef INVARIANTS
5664 		KASSERT(pktlen == 0, ("%s: %d bytes left.", __func__, pktlen));
5665 #endif
5666 		txq->imm_wrs++;
5667 	}
5668 
5669 	txq->txpkt_wrs++;
5670 
5671 	txsd = &txq->sdesc[eq->pidx];
5672 	txsd->m = m0;
5673 	txsd->desc_used = ndesc;
5674 
5675 	return (ndesc);
5676 }
5677 
5678 static inline bool
5679 cmp_l2hdr(struct txpkts *txp, struct mbuf *m)
5680 {
5681 	int len;
5682 
5683 	MPASS(txp->npkt > 0);
5684 	MPASS(m->m_len >= VM_TX_L2HDR_LEN);
5685 
5686 	if (txp->ethtype == be16toh(ETHERTYPE_VLAN))
5687 		len = VM_TX_L2HDR_LEN;
5688 	else
5689 		len = sizeof(struct ether_header);
5690 
5691 	return (memcmp(m->m_data, &txp->ethmacdst[0], len) != 0);
5692 }
5693 
5694 static inline void
5695 save_l2hdr(struct txpkts *txp, struct mbuf *m)
5696 {
5697 	MPASS(m->m_len >= VM_TX_L2HDR_LEN);
5698 
5699 	memcpy(&txp->ethmacdst[0], mtod(m, const void *), VM_TX_L2HDR_LEN);
5700 }
5701 
5702 static int
5703 add_to_txpkts_vf(struct adapter *sc, struct sge_txq *txq, struct mbuf *m,
5704     int avail, bool *send)
5705 {
5706 	struct txpkts *txp = &txq->txp;
5707 
5708 	/* Cannot have TSO and coalesce at the same time. */
5709 	if (cannot_use_txpkts(m)) {
5710 cannot_coalesce:
5711 		*send = txp->npkt > 0;
5712 		return (EINVAL);
5713 	}
5714 
5715 	/* VF allows coalescing of type 1 (1 GL) only */
5716 	if (mbuf_nsegs(m) > 1)
5717 		goto cannot_coalesce;
5718 
5719 	*send = false;
5720 	if (txp->npkt > 0) {
5721 		MPASS(tx_len16_to_desc(txp->len16) <= avail);
5722 		MPASS(txp->npkt < txp->max_npkt);
5723 		MPASS(txp->wr_type == 1);	/* VF supports type 1 only */
5724 
5725 		if (tx_len16_to_desc(txp->len16 + txpkts1_len16()) > avail) {
5726 retry_after_send:
5727 			*send = true;
5728 			return (EAGAIN);
5729 		}
5730 		if (m->m_pkthdr.len + txp->plen > 65535)
5731 			goto retry_after_send;
5732 		if (cmp_l2hdr(txp, m))
5733 			goto retry_after_send;
5734 
5735 		txp->len16 += txpkts1_len16();
5736 		txp->plen += m->m_pkthdr.len;
5737 		txp->mb[txp->npkt++] = m;
5738 		if (txp->npkt == txp->max_npkt)
5739 			*send = true;
5740 	} else {
5741 		txp->len16 = howmany(sizeof(struct fw_eth_tx_pkts_vm_wr), 16) +
5742 		    txpkts1_len16();
5743 		if (tx_len16_to_desc(txp->len16) > avail)
5744 			goto cannot_coalesce;
5745 		txp->npkt = 1;
5746 		txp->wr_type = 1;
5747 		txp->plen = m->m_pkthdr.len;
5748 		txp->mb[0] = m;
5749 		save_l2hdr(txp, m);
5750 	}
5751 	return (0);
5752 }
5753 
5754 static int
5755 add_to_txpkts_pf(struct adapter *sc, struct sge_txq *txq, struct mbuf *m,
5756     int avail, bool *send)
5757 {
5758 	struct txpkts *txp = &txq->txp;
5759 	int nsegs;
5760 
5761 	MPASS(!(sc->flags & IS_VF));
5762 
5763 	/* Cannot have TSO and coalesce at the same time. */
5764 	if (cannot_use_txpkts(m)) {
5765 cannot_coalesce:
5766 		*send = txp->npkt > 0;
5767 		return (EINVAL);
5768 	}
5769 
5770 	*send = false;
5771 	nsegs = mbuf_nsegs(m);
5772 	if (txp->npkt == 0) {
5773 		if (m->m_pkthdr.len > 65535)
5774 			goto cannot_coalesce;
5775 		if (nsegs > 1) {
5776 			txp->wr_type = 0;
5777 			txp->len16 =
5778 			    howmany(sizeof(struct fw_eth_tx_pkts_wr), 16) +
5779 			    txpkts0_len16(nsegs);
5780 		} else {
5781 			txp->wr_type = 1;
5782 			txp->len16 =
5783 			    howmany(sizeof(struct fw_eth_tx_pkts_wr), 16) +
5784 			    txpkts1_len16();
5785 		}
5786 		if (tx_len16_to_desc(txp->len16) > avail)
5787 			goto cannot_coalesce;
5788 		txp->npkt = 1;
5789 		txp->plen = m->m_pkthdr.len;
5790 		txp->mb[0] = m;
5791 	} else {
5792 		MPASS(tx_len16_to_desc(txp->len16) <= avail);
5793 		MPASS(txp->npkt < txp->max_npkt);
5794 
5795 		if (m->m_pkthdr.len + txp->plen > 65535) {
5796 retry_after_send:
5797 			*send = true;
5798 			return (EAGAIN);
5799 		}
5800 
5801 		MPASS(txp->wr_type == 0 || txp->wr_type == 1);
5802 		if (txp->wr_type == 0) {
5803 			if (tx_len16_to_desc(txp->len16 +
5804 			    txpkts0_len16(nsegs)) > min(avail, SGE_MAX_WR_NDESC))
5805 				goto retry_after_send;
5806 			txp->len16 += txpkts0_len16(nsegs);
5807 		} else {
5808 			if (nsegs != 1)
5809 				goto retry_after_send;
5810 			if (tx_len16_to_desc(txp->len16 + txpkts1_len16()) >
5811 			    avail)
5812 				goto retry_after_send;
5813 			txp->len16 += txpkts1_len16();
5814 		}
5815 
5816 		txp->plen += m->m_pkthdr.len;
5817 		txp->mb[txp->npkt++] = m;
5818 		if (txp->npkt == txp->max_npkt)
5819 			*send = true;
5820 	}
5821 	return (0);
5822 }
5823 
5824 /*
5825  * Write a txpkts WR for the packets in txp to the hardware descriptors, update
5826  * the software descriptor, and advance the pidx.  It is guaranteed that enough
5827  * descriptors are available.
5828  *
5829  * The return value is the # of hardware descriptors used.
5830  */
5831 static u_int
5832 write_txpkts_wr(struct adapter *sc, struct sge_txq *txq)
5833 {
5834 	const struct txpkts *txp = &txq->txp;
5835 	struct sge_eq *eq = &txq->eq;
5836 	struct fw_eth_tx_pkts_wr *wr;
5837 	struct tx_sdesc *txsd;
5838 	struct cpl_tx_pkt_core *cpl;
5839 	uint64_t ctrl1;
5840 	int ndesc, i, checkwrap;
5841 	struct mbuf *m, *last;
5842 	void *flitp;
5843 
5844 	TXQ_LOCK_ASSERT_OWNED(txq);
5845 	MPASS(txp->npkt > 0);
5846 	MPASS(txp->len16 <= howmany(SGE_MAX_WR_LEN, 16));
5847 
5848 	wr = (void *)&eq->desc[eq->pidx];
5849 	wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR));
5850 	wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(txp->len16));
5851 	wr->plen = htobe16(txp->plen);
5852 	wr->npkt = txp->npkt;
5853 	wr->r3 = 0;
5854 	wr->type = txp->wr_type;
5855 	flitp = wr + 1;
5856 
5857 	/*
5858 	 * At this point we are 16B into a hardware descriptor.  If checkwrap is
5859 	 * set then we know the WR is going to wrap around somewhere.  We'll
5860 	 * check for that at appropriate points.
5861 	 */
5862 	ndesc = tx_len16_to_desc(txp->len16);
5863 	last = NULL;
5864 	checkwrap = eq->sidx - ndesc < eq->pidx;
5865 	for (i = 0; i < txp->npkt; i++) {
5866 		m = txp->mb[i];
5867 		if (txp->wr_type == 0) {
5868 			struct ulp_txpkt *ulpmc;
5869 			struct ulptx_idata *ulpsc;
5870 
5871 			/* ULP master command */
5872 			ulpmc = flitp;
5873 			ulpmc->cmd_dest = htobe32(V_ULPTX_CMD(ULP_TX_PKT) |
5874 			    V_ULP_TXPKT_DEST(0) | V_ULP_TXPKT_FID(eq->iqid));
5875 			ulpmc->len = htobe32(txpkts0_len16(mbuf_nsegs(m)));
5876 
5877 			/* ULP subcommand */
5878 			ulpsc = (void *)(ulpmc + 1);
5879 			ulpsc->cmd_more = htobe32(V_ULPTX_CMD(ULP_TX_SC_IMM) |
5880 			    F_ULP_TX_SC_MORE);
5881 			ulpsc->len = htobe32(sizeof(struct cpl_tx_pkt_core));
5882 
5883 			cpl = (void *)(ulpsc + 1);
5884 			if (checkwrap &&
5885 			    (uintptr_t)cpl == (uintptr_t)&eq->desc[eq->sidx])
5886 				cpl = (void *)&eq->desc[0];
5887 		} else {
5888 			cpl = flitp;
5889 		}
5890 
5891 		/* Checksum offload */
5892 		ctrl1 = csum_to_ctrl(sc, m);
5893 		if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS)) {
5894 			/* some hardware assistance provided */
5895 			if (needs_vxlan_csum(m))
5896 				txq->vxlan_txcsum++;
5897 			else
5898 				txq->txcsum++;
5899 		}
5900 
5901 		/* VLAN tag insertion */
5902 		if (needs_vlan_insertion(m)) {
5903 			ctrl1 |= F_TXPKT_VLAN_VLD |
5904 			    V_TXPKT_VLAN(m->m_pkthdr.ether_vtag);
5905 			txq->vlan_insertion++;
5906 		}
5907 
5908 		/* CPL header */
5909 		cpl->ctrl0 = txq->cpl_ctrl0;
5910 		cpl->pack = 0;
5911 		cpl->len = htobe16(m->m_pkthdr.len);
5912 		cpl->ctrl1 = htobe64(ctrl1);
5913 
5914 		flitp = cpl + 1;
5915 		if (checkwrap &&
5916 		    (uintptr_t)flitp == (uintptr_t)&eq->desc[eq->sidx])
5917 			flitp = (void *)&eq->desc[0];
5918 
5919 		write_gl_to_txd(txq, m, (caddr_t *)(&flitp), checkwrap);
5920 
5921 		if (last != NULL)
5922 			last->m_nextpkt = m;
5923 		last = m;
5924 	}
5925 
5926 	txq->sgl_wrs++;
5927 	if (txp->wr_type == 0) {
5928 		txq->txpkts0_pkts += txp->npkt;
5929 		txq->txpkts0_wrs++;
5930 	} else {
5931 		txq->txpkts1_pkts += txp->npkt;
5932 		txq->txpkts1_wrs++;
5933 	}
5934 
5935 	txsd = &txq->sdesc[eq->pidx];
5936 	txsd->m = txp->mb[0];
5937 	txsd->desc_used = ndesc;
5938 
5939 	return (ndesc);
5940 }
5941 
5942 static u_int
5943 write_txpkts_vm_wr(struct adapter *sc, struct sge_txq *txq)
5944 {
5945 	const struct txpkts *txp = &txq->txp;
5946 	struct sge_eq *eq = &txq->eq;
5947 	struct fw_eth_tx_pkts_vm_wr *wr;
5948 	struct tx_sdesc *txsd;
5949 	struct cpl_tx_pkt_core *cpl;
5950 	uint64_t ctrl1;
5951 	int ndesc, i;
5952 	struct mbuf *m, *last;
5953 	void *flitp;
5954 
5955 	TXQ_LOCK_ASSERT_OWNED(txq);
5956 	MPASS(txp->npkt > 0);
5957 	MPASS(txp->wr_type == 1);	/* VF supports type 1 only */
5958 	MPASS(txp->mb[0] != NULL);
5959 	MPASS(txp->len16 <= howmany(SGE_MAX_WR_LEN, 16));
5960 
5961 	wr = (void *)&eq->desc[eq->pidx];
5962 	wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_VM_WR));
5963 	wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(txp->len16));
5964 	wr->r3 = 0;
5965 	wr->plen = htobe16(txp->plen);
5966 	wr->npkt = txp->npkt;
5967 	wr->r4 = 0;
5968 	memcpy(&wr->ethmacdst[0], &txp->ethmacdst[0], 16);
5969 	flitp = wr + 1;
5970 
5971 	/*
5972 	 * At this point we are 32B into a hardware descriptor.  Each mbuf in
5973 	 * the WR will take 32B so we check for the end of the descriptor ring
5974 	 * before writing odd mbufs (mb[1], 3, 5, ..)
5975 	 */
5976 	ndesc = tx_len16_to_desc(txp->len16);
5977 	last = NULL;
5978 	for (i = 0; i < txp->npkt; i++) {
5979 		m = txp->mb[i];
5980 		if (i & 1 && (uintptr_t)flitp == (uintptr_t)&eq->desc[eq->sidx])
5981 			flitp = &eq->desc[0];
5982 		cpl = flitp;
5983 
5984 		/* Checksum offload */
5985 		ctrl1 = csum_to_ctrl(sc, m);
5986 		if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS))
5987 			txq->txcsum++;	/* some hardware assistance provided */
5988 
5989 		/* VLAN tag insertion */
5990 		if (needs_vlan_insertion(m)) {
5991 			ctrl1 |= F_TXPKT_VLAN_VLD |
5992 			    V_TXPKT_VLAN(m->m_pkthdr.ether_vtag);
5993 			txq->vlan_insertion++;
5994 		}
5995 
5996 		/* CPL header */
5997 		cpl->ctrl0 = txq->cpl_ctrl0;
5998 		cpl->pack = 0;
5999 		cpl->len = htobe16(m->m_pkthdr.len);
6000 		cpl->ctrl1 = htobe64(ctrl1);
6001 
6002 		flitp = cpl + 1;
6003 		MPASS(mbuf_nsegs(m) == 1);
6004 		write_gl_to_txd(txq, m, (caddr_t *)(&flitp), 0);
6005 
6006 		if (last != NULL)
6007 			last->m_nextpkt = m;
6008 		last = m;
6009 	}
6010 
6011 	txq->sgl_wrs++;
6012 	txq->txpkts1_pkts += txp->npkt;
6013 	txq->txpkts1_wrs++;
6014 
6015 	txsd = &txq->sdesc[eq->pidx];
6016 	txsd->m = txp->mb[0];
6017 	txsd->desc_used = ndesc;
6018 
6019 	return (ndesc);
6020 }
6021 
6022 /*
6023  * If the SGL ends on an address that is not 16 byte aligned, this function will
6024  * add a 0 filled flit at the end.
6025  */
6026 static void
6027 write_gl_to_txd(struct sge_txq *txq, struct mbuf *m, caddr_t *to, int checkwrap)
6028 {
6029 	struct sge_eq *eq = &txq->eq;
6030 	struct sglist *gl = txq->gl;
6031 	struct sglist_seg *seg;
6032 	__be64 *flitp, *wrap;
6033 	struct ulptx_sgl *usgl;
6034 	int i, nflits, nsegs;
6035 
6036 	KASSERT(((uintptr_t)(*to) & 0xf) == 0,
6037 	    ("%s: SGL must start at a 16 byte boundary: %p", __func__, *to));
6038 	MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]);
6039 	MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]);
6040 
6041 	get_pkt_gl(m, gl);
6042 	nsegs = gl->sg_nseg;
6043 	MPASS(nsegs > 0);
6044 
6045 	nflits = (3 * (nsegs - 1)) / 2 + ((nsegs - 1) & 1) + 2;
6046 	flitp = (__be64 *)(*to);
6047 	wrap = (__be64 *)(&eq->desc[eq->sidx]);
6048 	seg = &gl->sg_segs[0];
6049 	usgl = (void *)flitp;
6050 
6051 	/*
6052 	 * We start at a 16 byte boundary somewhere inside the tx descriptor
6053 	 * ring, so we're at least 16 bytes away from the status page.  There is
6054 	 * no chance of a wrap around in the middle of usgl (which is 16 bytes).
6055 	 */
6056 
6057 	usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) |
6058 	    V_ULPTX_NSGE(nsegs));
6059 	usgl->len0 = htobe32(seg->ss_len);
6060 	usgl->addr0 = htobe64(seg->ss_paddr);
6061 	seg++;
6062 
6063 	if (checkwrap == 0 || (uintptr_t)(flitp + nflits) <= (uintptr_t)wrap) {
6064 
6065 		/* Won't wrap around at all */
6066 
6067 		for (i = 0; i < nsegs - 1; i++, seg++) {
6068 			usgl->sge[i / 2].len[i & 1] = htobe32(seg->ss_len);
6069 			usgl->sge[i / 2].addr[i & 1] = htobe64(seg->ss_paddr);
6070 		}
6071 		if (i & 1)
6072 			usgl->sge[i / 2].len[1] = htobe32(0);
6073 		flitp += nflits;
6074 	} else {
6075 
6076 		/* Will wrap somewhere in the rest of the SGL */
6077 
6078 		/* 2 flits already written, write the rest flit by flit */
6079 		flitp = (void *)(usgl + 1);
6080 		for (i = 0; i < nflits - 2; i++) {
6081 			if (flitp == wrap)
6082 				flitp = (void *)eq->desc;
6083 			*flitp++ = get_flit(seg, nsegs - 1, i);
6084 		}
6085 	}
6086 
6087 	if (nflits & 1) {
6088 		MPASS(((uintptr_t)flitp) & 0xf);
6089 		*flitp++ = 0;
6090 	}
6091 
6092 	MPASS((((uintptr_t)flitp) & 0xf) == 0);
6093 	if (__predict_false(flitp == wrap))
6094 		*to = (void *)eq->desc;
6095 	else
6096 		*to = (void *)flitp;
6097 }
6098 
6099 static inline void
6100 copy_to_txd(struct sge_eq *eq, caddr_t from, caddr_t *to, int len)
6101 {
6102 
6103 	MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]);
6104 	MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]);
6105 
6106 	if (__predict_true((uintptr_t)(*to) + len <=
6107 	    (uintptr_t)&eq->desc[eq->sidx])) {
6108 		bcopy(from, *to, len);
6109 		(*to) += len;
6110 	} else {
6111 		int portion = (uintptr_t)&eq->desc[eq->sidx] - (uintptr_t)(*to);
6112 
6113 		bcopy(from, *to, portion);
6114 		from += portion;
6115 		portion = len - portion;	/* remaining */
6116 		bcopy(from, (void *)eq->desc, portion);
6117 		(*to) = (caddr_t)eq->desc + portion;
6118 	}
6119 }
6120 
6121 static inline void
6122 ring_eq_db(struct adapter *sc, struct sge_eq *eq, u_int n)
6123 {
6124 	u_int db;
6125 
6126 	MPASS(n > 0);
6127 
6128 	db = eq->doorbells;
6129 	if (n > 1)
6130 		clrbit(&db, DOORBELL_WCWR);
6131 	wmb();
6132 
6133 	switch (ffs(db) - 1) {
6134 	case DOORBELL_UDB:
6135 		*eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n));
6136 		break;
6137 
6138 	case DOORBELL_WCWR: {
6139 		volatile uint64_t *dst, *src;
6140 		int i;
6141 
6142 		/*
6143 		 * Queues whose 128B doorbell segment fits in the page do not
6144 		 * use relative qid (udb_qid is always 0).  Only queues with
6145 		 * doorbell segments can do WCWR.
6146 		 */
6147 		KASSERT(eq->udb_qid == 0 && n == 1,
6148 		    ("%s: inappropriate doorbell (0x%x, %d, %d) for eq %p",
6149 		    __func__, eq->doorbells, n, eq->dbidx, eq));
6150 
6151 		dst = (volatile void *)((uintptr_t)eq->udb + UDBS_WR_OFFSET -
6152 		    UDBS_DB_OFFSET);
6153 		i = eq->dbidx;
6154 		src = (void *)&eq->desc[i];
6155 		while (src != (void *)&eq->desc[i + 1])
6156 			*dst++ = *src++;
6157 		wmb();
6158 		break;
6159 	}
6160 
6161 	case DOORBELL_UDBWC:
6162 		*eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n));
6163 		wmb();
6164 		break;
6165 
6166 	case DOORBELL_KDB:
6167 		t4_write_reg(sc, sc->sge_kdoorbell_reg,
6168 		    V_QID(eq->cntxt_id) | V_PIDX(n));
6169 		break;
6170 	}
6171 
6172 	IDXINCR(eq->dbidx, n, eq->sidx);
6173 }
6174 
6175 static inline u_int
6176 reclaimable_tx_desc(struct sge_eq *eq)
6177 {
6178 	uint16_t hw_cidx;
6179 
6180 	hw_cidx = read_hw_cidx(eq);
6181 	return (IDXDIFF(hw_cidx, eq->cidx, eq->sidx));
6182 }
6183 
6184 static inline u_int
6185 total_available_tx_desc(struct sge_eq *eq)
6186 {
6187 	uint16_t hw_cidx, pidx;
6188 
6189 	hw_cidx = read_hw_cidx(eq);
6190 	pidx = eq->pidx;
6191 
6192 	if (pidx == hw_cidx)
6193 		return (eq->sidx - 1);
6194 	else
6195 		return (IDXDIFF(hw_cidx, pidx, eq->sidx) - 1);
6196 }
6197 
6198 static inline uint16_t
6199 read_hw_cidx(struct sge_eq *eq)
6200 {
6201 	struct sge_qstat *spg = (void *)&eq->desc[eq->sidx];
6202 	uint16_t cidx = spg->cidx;	/* stable snapshot */
6203 
6204 	return (be16toh(cidx));
6205 }
6206 
6207 /*
6208  * Reclaim 'n' descriptors approximately.
6209  */
6210 static u_int
6211 reclaim_tx_descs(struct sge_txq *txq, u_int n)
6212 {
6213 	struct tx_sdesc *txsd;
6214 	struct sge_eq *eq = &txq->eq;
6215 	u_int can_reclaim, reclaimed;
6216 
6217 	TXQ_LOCK_ASSERT_OWNED(txq);
6218 	MPASS(n > 0);
6219 
6220 	reclaimed = 0;
6221 	can_reclaim = reclaimable_tx_desc(eq);
6222 	while (can_reclaim && reclaimed < n) {
6223 		int ndesc;
6224 		struct mbuf *m, *nextpkt;
6225 
6226 		txsd = &txq->sdesc[eq->cidx];
6227 		ndesc = txsd->desc_used;
6228 
6229 		/* Firmware doesn't return "partial" credits. */
6230 		KASSERT(can_reclaim >= ndesc,
6231 		    ("%s: unexpected number of credits: %d, %d",
6232 		    __func__, can_reclaim, ndesc));
6233 		KASSERT(ndesc != 0,
6234 		    ("%s: descriptor with no credits: cidx %d",
6235 		    __func__, eq->cidx));
6236 
6237 		for (m = txsd->m; m != NULL; m = nextpkt) {
6238 			nextpkt = m->m_nextpkt;
6239 			m->m_nextpkt = NULL;
6240 			m_freem(m);
6241 		}
6242 		reclaimed += ndesc;
6243 		can_reclaim -= ndesc;
6244 		IDXINCR(eq->cidx, ndesc, eq->sidx);
6245 	}
6246 
6247 	return (reclaimed);
6248 }
6249 
6250 static void
6251 tx_reclaim(void *arg, int n)
6252 {
6253 	struct sge_txq *txq = arg;
6254 	struct sge_eq *eq = &txq->eq;
6255 
6256 	do {
6257 		if (TXQ_TRYLOCK(txq) == 0)
6258 			break;
6259 		n = reclaim_tx_descs(txq, 32);
6260 		if (eq->cidx == eq->pidx)
6261 			eq->equeqidx = eq->pidx;
6262 		TXQ_UNLOCK(txq);
6263 	} while (n > 0);
6264 }
6265 
6266 static __be64
6267 get_flit(struct sglist_seg *segs, int nsegs, int idx)
6268 {
6269 	int i = (idx / 3) * 2;
6270 
6271 	switch (idx % 3) {
6272 	case 0: {
6273 		uint64_t rc;
6274 
6275 		rc = (uint64_t)segs[i].ss_len << 32;
6276 		if (i + 1 < nsegs)
6277 			rc |= (uint64_t)(segs[i + 1].ss_len);
6278 
6279 		return (htobe64(rc));
6280 	}
6281 	case 1:
6282 		return (htobe64(segs[i].ss_paddr));
6283 	case 2:
6284 		return (htobe64(segs[i + 1].ss_paddr));
6285 	}
6286 
6287 	return (0);
6288 }
6289 
6290 static int
6291 find_refill_source(struct adapter *sc, int maxp, bool packing)
6292 {
6293 	int i, zidx = -1;
6294 	struct rx_buf_info *rxb = &sc->sge.rx_buf_info[0];
6295 
6296 	if (packing) {
6297 		for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) {
6298 			if (rxb->hwidx2 == -1)
6299 				continue;
6300 			if (rxb->size1 < PAGE_SIZE &&
6301 			    rxb->size1 < largest_rx_cluster)
6302 				continue;
6303 			if (rxb->size1 > largest_rx_cluster)
6304 				break;
6305 			MPASS(rxb->size1 - rxb->size2 >= CL_METADATA_SIZE);
6306 			if (rxb->size2 >= maxp)
6307 				return (i);
6308 			zidx = i;
6309 		}
6310 	} else {
6311 		for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) {
6312 			if (rxb->hwidx1 == -1)
6313 				continue;
6314 			if (rxb->size1 > largest_rx_cluster)
6315 				break;
6316 			if (rxb->size1 >= maxp)
6317 				return (i);
6318 			zidx = i;
6319 		}
6320 	}
6321 
6322 	return (zidx);
6323 }
6324 
6325 static void
6326 add_fl_to_sfl(struct adapter *sc, struct sge_fl *fl)
6327 {
6328 	mtx_lock(&sc->sfl_lock);
6329 	FL_LOCK(fl);
6330 	if ((fl->flags & FL_DOOMED) == 0) {
6331 		fl->flags |= FL_STARVING;
6332 		TAILQ_INSERT_TAIL(&sc->sfl, fl, link);
6333 		callout_reset(&sc->sfl_callout, hz / 5, refill_sfl, sc);
6334 	}
6335 	FL_UNLOCK(fl);
6336 	mtx_unlock(&sc->sfl_lock);
6337 }
6338 
6339 static void
6340 handle_wrq_egr_update(struct adapter *sc, struct sge_eq *eq)
6341 {
6342 	struct sge_wrq *wrq = (void *)eq;
6343 
6344 	atomic_readandclear_int(&eq->equiq);
6345 	taskqueue_enqueue(sc->tq[eq->tx_chan], &wrq->wrq_tx_task);
6346 }
6347 
6348 static void
6349 handle_eth_egr_update(struct adapter *sc, struct sge_eq *eq)
6350 {
6351 	struct sge_txq *txq = (void *)eq;
6352 
6353 	MPASS(eq->type == EQ_ETH);
6354 
6355 	atomic_readandclear_int(&eq->equiq);
6356 	if (mp_ring_is_idle(txq->r))
6357 		taskqueue_enqueue(sc->tq[eq->tx_chan], &txq->tx_reclaim_task);
6358 	else
6359 		mp_ring_check_drainage(txq->r, 64);
6360 }
6361 
6362 static int
6363 handle_sge_egr_update(struct sge_iq *iq, const struct rss_header *rss,
6364     struct mbuf *m)
6365 {
6366 	const struct cpl_sge_egr_update *cpl = (const void *)(rss + 1);
6367 	unsigned int qid = G_EGR_QID(ntohl(cpl->opcode_qid));
6368 	struct adapter *sc = iq->adapter;
6369 	struct sge *s = &sc->sge;
6370 	struct sge_eq *eq;
6371 	static void (*h[])(struct adapter *, struct sge_eq *) = {NULL,
6372 		&handle_wrq_egr_update, &handle_eth_egr_update,
6373 		&handle_wrq_egr_update};
6374 
6375 	KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
6376 	    rss->opcode));
6377 
6378 	eq = s->eqmap[qid - s->eq_start - s->eq_base];
6379 	(*h[eq->type])(sc, eq);
6380 
6381 	return (0);
6382 }
6383 
6384 /* handle_fw_msg works for both fw4_msg and fw6_msg because this is valid */
6385 CTASSERT(offsetof(struct cpl_fw4_msg, data) == \
6386     offsetof(struct cpl_fw6_msg, data));
6387 
6388 static int
6389 handle_fw_msg(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
6390 {
6391 	struct adapter *sc = iq->adapter;
6392 	const struct cpl_fw6_msg *cpl = (const void *)(rss + 1);
6393 
6394 	KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
6395 	    rss->opcode));
6396 
6397 	if (cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL) {
6398 		const struct rss_header *rss2;
6399 
6400 		rss2 = (const struct rss_header *)&cpl->data[0];
6401 		return (t4_cpl_handler[rss2->opcode](iq, rss2, m));
6402 	}
6403 
6404 	return (t4_fw_msg_handler[cpl->type](sc, &cpl->data[0]));
6405 }
6406 
6407 /**
6408  *	t4_handle_wrerr_rpl - process a FW work request error message
6409  *	@adap: the adapter
6410  *	@rpl: start of the FW message
6411  */
6412 static int
6413 t4_handle_wrerr_rpl(struct adapter *adap, const __be64 *rpl)
6414 {
6415 	u8 opcode = *(const u8 *)rpl;
6416 	const struct fw_error_cmd *e = (const void *)rpl;
6417 	unsigned int i;
6418 
6419 	if (opcode != FW_ERROR_CMD) {
6420 		log(LOG_ERR,
6421 		    "%s: Received WRERR_RPL message with opcode %#x\n",
6422 		    device_get_nameunit(adap->dev), opcode);
6423 		return (EINVAL);
6424 	}
6425 	log(LOG_ERR, "%s: FW_ERROR (%s) ", device_get_nameunit(adap->dev),
6426 	    G_FW_ERROR_CMD_FATAL(be32toh(e->op_to_type)) ? "fatal" :
6427 	    "non-fatal");
6428 	switch (G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type))) {
6429 	case FW_ERROR_TYPE_EXCEPTION:
6430 		log(LOG_ERR, "exception info:\n");
6431 		for (i = 0; i < nitems(e->u.exception.info); i++)
6432 			log(LOG_ERR, "%s%08x", i == 0 ? "\t" : " ",
6433 			    be32toh(e->u.exception.info[i]));
6434 		log(LOG_ERR, "\n");
6435 		break;
6436 	case FW_ERROR_TYPE_HWMODULE:
6437 		log(LOG_ERR, "HW module regaddr %08x regval %08x\n",
6438 		    be32toh(e->u.hwmodule.regaddr),
6439 		    be32toh(e->u.hwmodule.regval));
6440 		break;
6441 	case FW_ERROR_TYPE_WR:
6442 		log(LOG_ERR, "WR cidx %d PF %d VF %d eqid %d hdr:\n",
6443 		    be16toh(e->u.wr.cidx),
6444 		    G_FW_ERROR_CMD_PFN(be16toh(e->u.wr.pfn_vfn)),
6445 		    G_FW_ERROR_CMD_VFN(be16toh(e->u.wr.pfn_vfn)),
6446 		    be32toh(e->u.wr.eqid));
6447 		for (i = 0; i < nitems(e->u.wr.wrhdr); i++)
6448 			log(LOG_ERR, "%s%02x", i == 0 ? "\t" : " ",
6449 			    e->u.wr.wrhdr[i]);
6450 		log(LOG_ERR, "\n");
6451 		break;
6452 	case FW_ERROR_TYPE_ACL:
6453 		log(LOG_ERR, "ACL cidx %d PF %d VF %d eqid %d %s",
6454 		    be16toh(e->u.acl.cidx),
6455 		    G_FW_ERROR_CMD_PFN(be16toh(e->u.acl.pfn_vfn)),
6456 		    G_FW_ERROR_CMD_VFN(be16toh(e->u.acl.pfn_vfn)),
6457 		    be32toh(e->u.acl.eqid),
6458 		    G_FW_ERROR_CMD_MV(be16toh(e->u.acl.mv_pkd)) ? "vlanid" :
6459 		    "MAC");
6460 		for (i = 0; i < nitems(e->u.acl.val); i++)
6461 			log(LOG_ERR, " %02x", e->u.acl.val[i]);
6462 		log(LOG_ERR, "\n");
6463 		break;
6464 	default:
6465 		log(LOG_ERR, "type %#x\n",
6466 		    G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type)));
6467 		return (EINVAL);
6468 	}
6469 	return (0);
6470 }
6471 
6472 static inline bool
6473 bufidx_used(struct adapter *sc, int idx)
6474 {
6475 	struct rx_buf_info *rxb = &sc->sge.rx_buf_info[0];
6476 	int i;
6477 
6478 	for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) {
6479 		if (rxb->size1 > largest_rx_cluster)
6480 			continue;
6481 		if (rxb->hwidx1 == idx || rxb->hwidx2 == idx)
6482 			return (true);
6483 	}
6484 
6485 	return (false);
6486 }
6487 
6488 static int
6489 sysctl_bufsizes(SYSCTL_HANDLER_ARGS)
6490 {
6491 	struct adapter *sc = arg1;
6492 	struct sge_params *sp = &sc->params.sge;
6493 	int i, rc;
6494 	struct sbuf sb;
6495 	char c;
6496 
6497 	sbuf_new(&sb, NULL, 128, SBUF_AUTOEXTEND);
6498 	for (i = 0; i < SGE_FLBUF_SIZES; i++) {
6499 		if (bufidx_used(sc, i))
6500 			c = '*';
6501 		else
6502 			c = '\0';
6503 
6504 		sbuf_printf(&sb, "%u%c ", sp->sge_fl_buffer_size[i], c);
6505 	}
6506 	sbuf_trim(&sb);
6507 	sbuf_finish(&sb);
6508 	rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req);
6509 	sbuf_delete(&sb);
6510 	return (rc);
6511 }
6512 
6513 #ifdef RATELIMIT
6514 #if defined(INET) || defined(INET6)
6515 /*
6516  * len16 for a txpkt WR with a GL.  Includes the firmware work request header.
6517  */
6518 static inline u_int
6519 txpkt_eo_len16(u_int nsegs, u_int immhdrs, u_int tso)
6520 {
6521 	u_int n;
6522 
6523 	MPASS(immhdrs > 0);
6524 
6525 	n = roundup2(sizeof(struct fw_eth_tx_eo_wr) +
6526 	    sizeof(struct cpl_tx_pkt_core) + immhdrs, 16);
6527 	if (__predict_false(nsegs == 0))
6528 		goto done;
6529 
6530 	nsegs--; /* first segment is part of ulptx_sgl */
6531 	n += sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1));
6532 	if (tso)
6533 		n += sizeof(struct cpl_tx_pkt_lso_core);
6534 
6535 done:
6536 	return (howmany(n, 16));
6537 }
6538 #endif
6539 
6540 #define ETID_FLOWC_NPARAMS 6
6541 #define ETID_FLOWC_LEN (roundup2((sizeof(struct fw_flowc_wr) + \
6542     ETID_FLOWC_NPARAMS * sizeof(struct fw_flowc_mnemval)), 16))
6543 #define ETID_FLOWC_LEN16 (howmany(ETID_FLOWC_LEN, 16))
6544 
6545 static int
6546 send_etid_flowc_wr(struct cxgbe_rate_tag *cst, struct port_info *pi,
6547     struct vi_info *vi)
6548 {
6549 	struct wrq_cookie cookie;
6550 	u_int pfvf = pi->adapter->pf << S_FW_VIID_PFN;
6551 	struct fw_flowc_wr *flowc;
6552 
6553 	mtx_assert(&cst->lock, MA_OWNED);
6554 	MPASS((cst->flags & (EO_FLOWC_PENDING | EO_FLOWC_RPL_PENDING)) ==
6555 	    EO_FLOWC_PENDING);
6556 
6557 	flowc = start_wrq_wr(&cst->eo_txq->wrq, ETID_FLOWC_LEN16, &cookie);
6558 	if (__predict_false(flowc == NULL))
6559 		return (ENOMEM);
6560 
6561 	bzero(flowc, ETID_FLOWC_LEN);
6562 	flowc->op_to_nparams = htobe32(V_FW_WR_OP(FW_FLOWC_WR) |
6563 	    V_FW_FLOWC_WR_NPARAMS(ETID_FLOWC_NPARAMS) | V_FW_WR_COMPL(0));
6564 	flowc->flowid_len16 = htonl(V_FW_WR_LEN16(ETID_FLOWC_LEN16) |
6565 	    V_FW_WR_FLOWID(cst->etid));
6566 	flowc->mnemval[0].mnemonic = FW_FLOWC_MNEM_PFNVFN;
6567 	flowc->mnemval[0].val = htobe32(pfvf);
6568 	flowc->mnemval[1].mnemonic = FW_FLOWC_MNEM_CH;
6569 	flowc->mnemval[1].val = htobe32(pi->tx_chan);
6570 	flowc->mnemval[2].mnemonic = FW_FLOWC_MNEM_PORT;
6571 	flowc->mnemval[2].val = htobe32(pi->tx_chan);
6572 	flowc->mnemval[3].mnemonic = FW_FLOWC_MNEM_IQID;
6573 	flowc->mnemval[3].val = htobe32(cst->iqid);
6574 	flowc->mnemval[4].mnemonic = FW_FLOWC_MNEM_EOSTATE;
6575 	flowc->mnemval[4].val = htobe32(FW_FLOWC_MNEM_EOSTATE_ESTABLISHED);
6576 	flowc->mnemval[5].mnemonic = FW_FLOWC_MNEM_SCHEDCLASS;
6577 	flowc->mnemval[5].val = htobe32(cst->schedcl);
6578 
6579 	commit_wrq_wr(&cst->eo_txq->wrq, flowc, &cookie);
6580 
6581 	cst->flags &= ~EO_FLOWC_PENDING;
6582 	cst->flags |= EO_FLOWC_RPL_PENDING;
6583 	MPASS(cst->tx_credits >= ETID_FLOWC_LEN16);	/* flowc is first WR. */
6584 	cst->tx_credits -= ETID_FLOWC_LEN16;
6585 
6586 	return (0);
6587 }
6588 
6589 #define ETID_FLUSH_LEN16 (howmany(sizeof (struct fw_flowc_wr), 16))
6590 
6591 void
6592 send_etid_flush_wr(struct cxgbe_rate_tag *cst)
6593 {
6594 	struct fw_flowc_wr *flowc;
6595 	struct wrq_cookie cookie;
6596 
6597 	mtx_assert(&cst->lock, MA_OWNED);
6598 
6599 	flowc = start_wrq_wr(&cst->eo_txq->wrq, ETID_FLUSH_LEN16, &cookie);
6600 	if (__predict_false(flowc == NULL))
6601 		CXGBE_UNIMPLEMENTED(__func__);
6602 
6603 	bzero(flowc, ETID_FLUSH_LEN16 * 16);
6604 	flowc->op_to_nparams = htobe32(V_FW_WR_OP(FW_FLOWC_WR) |
6605 	    V_FW_FLOWC_WR_NPARAMS(0) | F_FW_WR_COMPL);
6606 	flowc->flowid_len16 = htobe32(V_FW_WR_LEN16(ETID_FLUSH_LEN16) |
6607 	    V_FW_WR_FLOWID(cst->etid));
6608 
6609 	commit_wrq_wr(&cst->eo_txq->wrq, flowc, &cookie);
6610 
6611 	cst->flags |= EO_FLUSH_RPL_PENDING;
6612 	MPASS(cst->tx_credits >= ETID_FLUSH_LEN16);
6613 	cst->tx_credits -= ETID_FLUSH_LEN16;
6614 	cst->ncompl++;
6615 }
6616 
6617 static void
6618 write_ethofld_wr(struct cxgbe_rate_tag *cst, struct fw_eth_tx_eo_wr *wr,
6619     struct mbuf *m0, int compl)
6620 {
6621 	struct cpl_tx_pkt_core *cpl;
6622 	uint64_t ctrl1;
6623 	uint32_t ctrl;	/* used in many unrelated places */
6624 	int len16, pktlen, nsegs, immhdrs;
6625 	uintptr_t p;
6626 	struct ulptx_sgl *usgl;
6627 	struct sglist sg;
6628 	struct sglist_seg segs[38];	/* XXX: find real limit.  XXX: get off the stack */
6629 
6630 	mtx_assert(&cst->lock, MA_OWNED);
6631 	M_ASSERTPKTHDR(m0);
6632 	KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 &&
6633 	    m0->m_pkthdr.l4hlen > 0,
6634 	    ("%s: ethofld mbuf %p is missing header lengths", __func__, m0));
6635 
6636 	len16 = mbuf_eo_len16(m0);
6637 	nsegs = mbuf_eo_nsegs(m0);
6638 	pktlen = m0->m_pkthdr.len;
6639 	ctrl = sizeof(struct cpl_tx_pkt_core);
6640 	if (needs_tso(m0))
6641 		ctrl += sizeof(struct cpl_tx_pkt_lso_core);
6642 	immhdrs = m0->m_pkthdr.l2hlen + m0->m_pkthdr.l3hlen + m0->m_pkthdr.l4hlen;
6643 	ctrl += immhdrs;
6644 
6645 	wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_EO_WR) |
6646 	    V_FW_ETH_TX_EO_WR_IMMDLEN(ctrl) | V_FW_WR_COMPL(!!compl));
6647 	wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(len16) |
6648 	    V_FW_WR_FLOWID(cst->etid));
6649 	wr->r3 = 0;
6650 	if (needs_outer_udp_csum(m0)) {
6651 		wr->u.udpseg.type = FW_ETH_TX_EO_TYPE_UDPSEG;
6652 		wr->u.udpseg.ethlen = m0->m_pkthdr.l2hlen;
6653 		wr->u.udpseg.iplen = htobe16(m0->m_pkthdr.l3hlen);
6654 		wr->u.udpseg.udplen = m0->m_pkthdr.l4hlen;
6655 		wr->u.udpseg.rtplen = 0;
6656 		wr->u.udpseg.r4 = 0;
6657 		wr->u.udpseg.mss = htobe16(pktlen - immhdrs);
6658 		wr->u.udpseg.schedpktsize = wr->u.udpseg.mss;
6659 		wr->u.udpseg.plen = htobe32(pktlen - immhdrs);
6660 		cpl = (void *)(wr + 1);
6661 	} else {
6662 		MPASS(needs_outer_tcp_csum(m0));
6663 		wr->u.tcpseg.type = FW_ETH_TX_EO_TYPE_TCPSEG;
6664 		wr->u.tcpseg.ethlen = m0->m_pkthdr.l2hlen;
6665 		wr->u.tcpseg.iplen = htobe16(m0->m_pkthdr.l3hlen);
6666 		wr->u.tcpseg.tcplen = m0->m_pkthdr.l4hlen;
6667 		wr->u.tcpseg.tsclk_tsoff = mbuf_eo_tsclk_tsoff(m0);
6668 		wr->u.tcpseg.r4 = 0;
6669 		wr->u.tcpseg.r5 = 0;
6670 		wr->u.tcpseg.plen = htobe32(pktlen - immhdrs);
6671 
6672 		if (needs_tso(m0)) {
6673 			struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1);
6674 
6675 			wr->u.tcpseg.mss = htobe16(m0->m_pkthdr.tso_segsz);
6676 
6677 			ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) |
6678 			    F_LSO_FIRST_SLICE | F_LSO_LAST_SLICE |
6679 			    V_LSO_ETHHDR_LEN((m0->m_pkthdr.l2hlen -
6680 				ETHER_HDR_LEN) >> 2) |
6681 			    V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) |
6682 			    V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2);
6683 			if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr))
6684 				ctrl |= F_LSO_IPV6;
6685 			lso->lso_ctrl = htobe32(ctrl);
6686 			lso->ipid_ofst = htobe16(0);
6687 			lso->mss = htobe16(m0->m_pkthdr.tso_segsz);
6688 			lso->seqno_offset = htobe32(0);
6689 			lso->len = htobe32(pktlen);
6690 
6691 			cpl = (void *)(lso + 1);
6692 		} else {
6693 			wr->u.tcpseg.mss = htobe16(0xffff);
6694 			cpl = (void *)(wr + 1);
6695 		}
6696 	}
6697 
6698 	/* Checksum offload must be requested for ethofld. */
6699 	MPASS(needs_outer_l4_csum(m0));
6700 	ctrl1 = csum_to_ctrl(cst->adapter, m0);
6701 
6702 	/* VLAN tag insertion */
6703 	if (needs_vlan_insertion(m0)) {
6704 		ctrl1 |= F_TXPKT_VLAN_VLD |
6705 		    V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag);
6706 	}
6707 
6708 	/* CPL header */
6709 	cpl->ctrl0 = cst->ctrl0;
6710 	cpl->pack = 0;
6711 	cpl->len = htobe16(pktlen);
6712 	cpl->ctrl1 = htobe64(ctrl1);
6713 
6714 	/* Copy Ethernet, IP & TCP/UDP hdrs as immediate data */
6715 	p = (uintptr_t)(cpl + 1);
6716 	m_copydata(m0, 0, immhdrs, (void *)p);
6717 
6718 	/* SGL */
6719 	if (nsegs > 0) {
6720 		int i, pad;
6721 
6722 		/* zero-pad upto next 16Byte boundary, if not 16Byte aligned */
6723 		p += immhdrs;
6724 		pad = 16 - (immhdrs & 0xf);
6725 		bzero((void *)p, pad);
6726 
6727 		usgl = (void *)(p + pad);
6728 		usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) |
6729 		    V_ULPTX_NSGE(nsegs));
6730 
6731 		sglist_init(&sg, nitems(segs), segs);
6732 		for (; m0 != NULL; m0 = m0->m_next) {
6733 			if (__predict_false(m0->m_len == 0))
6734 				continue;
6735 			if (immhdrs >= m0->m_len) {
6736 				immhdrs -= m0->m_len;
6737 				continue;
6738 			}
6739 			if (m0->m_flags & M_EXTPG)
6740 				sglist_append_mbuf_epg(&sg, m0,
6741 				    mtod(m0, vm_offset_t), m0->m_len);
6742                         else
6743 				sglist_append(&sg, mtod(m0, char *) + immhdrs,
6744 				    m0->m_len - immhdrs);
6745 			immhdrs = 0;
6746 		}
6747 		MPASS(sg.sg_nseg == nsegs);
6748 
6749 		/*
6750 		 * Zero pad last 8B in case the WR doesn't end on a 16B
6751 		 * boundary.
6752 		 */
6753 		*(uint64_t *)((char *)wr + len16 * 16 - 8) = 0;
6754 
6755 		usgl->len0 = htobe32(segs[0].ss_len);
6756 		usgl->addr0 = htobe64(segs[0].ss_paddr);
6757 		for (i = 0; i < nsegs - 1; i++) {
6758 			usgl->sge[i / 2].len[i & 1] = htobe32(segs[i + 1].ss_len);
6759 			usgl->sge[i / 2].addr[i & 1] = htobe64(segs[i + 1].ss_paddr);
6760 		}
6761 		if (i & 1)
6762 			usgl->sge[i / 2].len[1] = htobe32(0);
6763 	}
6764 
6765 }
6766 
6767 static void
6768 ethofld_tx(struct cxgbe_rate_tag *cst)
6769 {
6770 	struct mbuf *m;
6771 	struct wrq_cookie cookie;
6772 	int next_credits, compl;
6773 	struct fw_eth_tx_eo_wr *wr;
6774 
6775 	mtx_assert(&cst->lock, MA_OWNED);
6776 
6777 	while ((m = mbufq_first(&cst->pending_tx)) != NULL) {
6778 		M_ASSERTPKTHDR(m);
6779 
6780 		/* How many len16 credits do we need to send this mbuf. */
6781 		next_credits = mbuf_eo_len16(m);
6782 		MPASS(next_credits > 0);
6783 		if (next_credits > cst->tx_credits) {
6784 			/*
6785 			 * Tx will make progress eventually because there is at
6786 			 * least one outstanding fw4_ack that will return
6787 			 * credits and kick the tx.
6788 			 */
6789 			MPASS(cst->ncompl > 0);
6790 			return;
6791 		}
6792 		wr = start_wrq_wr(&cst->eo_txq->wrq, next_credits, &cookie);
6793 		if (__predict_false(wr == NULL)) {
6794 			/* XXX: wishful thinking, not a real assertion. */
6795 			MPASS(cst->ncompl > 0);
6796 			return;
6797 		}
6798 		cst->tx_credits -= next_credits;
6799 		cst->tx_nocompl += next_credits;
6800 		compl = cst->ncompl == 0 || cst->tx_nocompl >= cst->tx_total / 2;
6801 		ETHER_BPF_MTAP(cst->com.ifp, m);
6802 		write_ethofld_wr(cst, wr, m, compl);
6803 		commit_wrq_wr(&cst->eo_txq->wrq, wr, &cookie);
6804 		if (compl) {
6805 			cst->ncompl++;
6806 			cst->tx_nocompl	= 0;
6807 		}
6808 		(void) mbufq_dequeue(&cst->pending_tx);
6809 
6810 		/*
6811 		 * Drop the mbuf's reference on the tag now rather
6812 		 * than waiting until m_freem().  This ensures that
6813 		 * cxgbe_rate_tag_free gets called when the inp drops
6814 		 * its reference on the tag and there are no more
6815 		 * mbufs in the pending_tx queue and can flush any
6816 		 * pending requests.  Otherwise if the last mbuf
6817 		 * doesn't request a completion the etid will never be
6818 		 * released.
6819 		 */
6820 		m->m_pkthdr.snd_tag = NULL;
6821 		m->m_pkthdr.csum_flags &= ~CSUM_SND_TAG;
6822 		m_snd_tag_rele(&cst->com);
6823 
6824 		mbufq_enqueue(&cst->pending_fwack, m);
6825 	}
6826 }
6827 
6828 int
6829 ethofld_transmit(struct ifnet *ifp, struct mbuf *m0)
6830 {
6831 	struct cxgbe_rate_tag *cst;
6832 	int rc;
6833 
6834 	MPASS(m0->m_nextpkt == NULL);
6835 	MPASS(m0->m_pkthdr.csum_flags & CSUM_SND_TAG);
6836 	MPASS(m0->m_pkthdr.snd_tag != NULL);
6837 	cst = mst_to_crt(m0->m_pkthdr.snd_tag);
6838 
6839 	mtx_lock(&cst->lock);
6840 	MPASS(cst->flags & EO_SND_TAG_REF);
6841 
6842 	if (__predict_false(cst->flags & EO_FLOWC_PENDING)) {
6843 		struct vi_info *vi = ifp->if_softc;
6844 		struct port_info *pi = vi->pi;
6845 		struct adapter *sc = pi->adapter;
6846 		const uint32_t rss_mask = vi->rss_size - 1;
6847 		uint32_t rss_hash;
6848 
6849 		cst->eo_txq = &sc->sge.ofld_txq[vi->first_ofld_txq];
6850 		if (M_HASHTYPE_ISHASH(m0))
6851 			rss_hash = m0->m_pkthdr.flowid;
6852 		else
6853 			rss_hash = arc4random();
6854 		/* We assume RSS hashing */
6855 		cst->iqid = vi->rss[rss_hash & rss_mask];
6856 		cst->eo_txq += rss_hash % vi->nofldtxq;
6857 		rc = send_etid_flowc_wr(cst, pi, vi);
6858 		if (rc != 0)
6859 			goto done;
6860 	}
6861 
6862 	if (__predict_false(cst->plen + m0->m_pkthdr.len > eo_max_backlog)) {
6863 		rc = ENOBUFS;
6864 		goto done;
6865 	}
6866 
6867 	mbufq_enqueue(&cst->pending_tx, m0);
6868 	cst->plen += m0->m_pkthdr.len;
6869 
6870 	/*
6871 	 * Hold an extra reference on the tag while generating work
6872 	 * requests to ensure that we don't try to free the tag during
6873 	 * ethofld_tx() in case we are sending the final mbuf after
6874 	 * the inp was freed.
6875 	 */
6876 	m_snd_tag_ref(&cst->com);
6877 	ethofld_tx(cst);
6878 	mtx_unlock(&cst->lock);
6879 	m_snd_tag_rele(&cst->com);
6880 	return (0);
6881 
6882 done:
6883 	mtx_unlock(&cst->lock);
6884 	if (__predict_false(rc != 0))
6885 		m_freem(m0);
6886 	return (rc);
6887 }
6888 
6889 static int
6890 ethofld_fw4_ack(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0)
6891 {
6892 	struct adapter *sc = iq->adapter;
6893 	const struct cpl_fw4_ack *cpl = (const void *)(rss + 1);
6894 	struct mbuf *m;
6895 	u_int etid = G_CPL_FW4_ACK_FLOWID(be32toh(OPCODE_TID(cpl)));
6896 	struct cxgbe_rate_tag *cst;
6897 	uint8_t credits = cpl->credits;
6898 
6899 	cst = lookup_etid(sc, etid);
6900 	mtx_lock(&cst->lock);
6901 	if (__predict_false(cst->flags & EO_FLOWC_RPL_PENDING)) {
6902 		MPASS(credits >= ETID_FLOWC_LEN16);
6903 		credits -= ETID_FLOWC_LEN16;
6904 		cst->flags &= ~EO_FLOWC_RPL_PENDING;
6905 	}
6906 
6907 	KASSERT(cst->ncompl > 0,
6908 	    ("%s: etid %u (%p) wasn't expecting completion.",
6909 	    __func__, etid, cst));
6910 	cst->ncompl--;
6911 
6912 	while (credits > 0) {
6913 		m = mbufq_dequeue(&cst->pending_fwack);
6914 		if (__predict_false(m == NULL)) {
6915 			/*
6916 			 * The remaining credits are for the final flush that
6917 			 * was issued when the tag was freed by the kernel.
6918 			 */
6919 			MPASS((cst->flags &
6920 			    (EO_FLUSH_RPL_PENDING | EO_SND_TAG_REF)) ==
6921 			    EO_FLUSH_RPL_PENDING);
6922 			MPASS(credits == ETID_FLUSH_LEN16);
6923 			MPASS(cst->tx_credits + cpl->credits == cst->tx_total);
6924 			MPASS(cst->ncompl == 0);
6925 
6926 			cst->flags &= ~EO_FLUSH_RPL_PENDING;
6927 			cst->tx_credits += cpl->credits;
6928 			cxgbe_rate_tag_free_locked(cst);
6929 			return (0);	/* cst is gone. */
6930 		}
6931 		KASSERT(m != NULL,
6932 		    ("%s: too many credits (%u, %u)", __func__, cpl->credits,
6933 		    credits));
6934 		KASSERT(credits >= mbuf_eo_len16(m),
6935 		    ("%s: too few credits (%u, %u, %u)", __func__,
6936 		    cpl->credits, credits, mbuf_eo_len16(m)));
6937 		credits -= mbuf_eo_len16(m);
6938 		cst->plen -= m->m_pkthdr.len;
6939 		m_freem(m);
6940 	}
6941 
6942 	cst->tx_credits += cpl->credits;
6943 	MPASS(cst->tx_credits <= cst->tx_total);
6944 
6945 	if (cst->flags & EO_SND_TAG_REF) {
6946 		/*
6947 		 * As with ethofld_transmit(), hold an extra reference
6948 		 * so that the tag is stable across ethold_tx().
6949 		 */
6950 		m_snd_tag_ref(&cst->com);
6951 		m = mbufq_first(&cst->pending_tx);
6952 		if (m != NULL && cst->tx_credits >= mbuf_eo_len16(m))
6953 			ethofld_tx(cst);
6954 		mtx_unlock(&cst->lock);
6955 		m_snd_tag_rele(&cst->com);
6956 	} else {
6957 		/*
6958 		 * There shouldn't be any pending packets if the tag
6959 		 * was freed by the kernel since any pending packet
6960 		 * should hold a reference to the tag.
6961 		 */
6962 		MPASS(mbufq_first(&cst->pending_tx) == NULL);
6963 		mtx_unlock(&cst->lock);
6964 	}
6965 
6966 	return (0);
6967 }
6968 #endif
6969