1 /*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 34 #include <sys/types.h> 35 #include <sys/eventhandler.h> 36 #include <sys/mbuf.h> 37 #include <sys/socket.h> 38 #include <sys/kernel.h> 39 #include <sys/malloc.h> 40 #include <sys/queue.h> 41 #include <sys/sbuf.h> 42 #include <sys/taskqueue.h> 43 #include <sys/time.h> 44 #include <sys/sglist.h> 45 #include <sys/sysctl.h> 46 #include <sys/smp.h> 47 #include <sys/counter.h> 48 #include <net/bpf.h> 49 #include <net/ethernet.h> 50 #include <net/if.h> 51 #include <net/if_vlan_var.h> 52 #include <netinet/in.h> 53 #include <netinet/ip.h> 54 #include <netinet/ip6.h> 55 #include <netinet/tcp.h> 56 #include <machine/in_cksum.h> 57 #include <machine/md_var.h> 58 #include <vm/vm.h> 59 #include <vm/pmap.h> 60 #ifdef DEV_NETMAP 61 #include <machine/bus.h> 62 #include <sys/selinfo.h> 63 #include <net/if_var.h> 64 #include <net/netmap.h> 65 #include <dev/netmap/netmap_kern.h> 66 #endif 67 68 #include "common/common.h" 69 #include "common/t4_regs.h" 70 #include "common/t4_regs_values.h" 71 #include "common/t4_msg.h" 72 #include "t4_l2t.h" 73 #include "t4_mp_ring.h" 74 75 #ifdef T4_PKT_TIMESTAMP 76 #define RX_COPY_THRESHOLD (MINCLSIZE - 8) 77 #else 78 #define RX_COPY_THRESHOLD MINCLSIZE 79 #endif 80 81 /* 82 * Ethernet frames are DMA'd at this byte offset into the freelist buffer. 83 * 0-7 are valid values. 84 */ 85 static int fl_pktshift = 2; 86 TUNABLE_INT("hw.cxgbe.fl_pktshift", &fl_pktshift); 87 88 /* 89 * Pad ethernet payload up to this boundary. 90 * -1: driver should figure out a good value. 91 * 0: disable padding. 92 * Any power of 2 from 32 to 4096 (both inclusive) is also a valid value. 93 */ 94 int fl_pad = -1; 95 TUNABLE_INT("hw.cxgbe.fl_pad", &fl_pad); 96 97 /* 98 * Status page length. 99 * -1: driver should figure out a good value. 100 * 64 or 128 are the only other valid values. 101 */ 102 static int spg_len = -1; 103 TUNABLE_INT("hw.cxgbe.spg_len", &spg_len); 104 105 /* 106 * Congestion drops. 107 * -1: no congestion feedback (not recommended). 108 * 0: backpressure the channel instead of dropping packets right away. 109 * 1: no backpressure, drop packets for the congested queue immediately. 110 */ 111 static int cong_drop = 0; 112 TUNABLE_INT("hw.cxgbe.cong_drop", &cong_drop); 113 114 /* 115 * Deliver multiple frames in the same free list buffer if they fit. 116 * -1: let the driver decide whether to enable buffer packing or not. 117 * 0: disable buffer packing. 118 * 1: enable buffer packing. 119 */ 120 static int buffer_packing = -1; 121 TUNABLE_INT("hw.cxgbe.buffer_packing", &buffer_packing); 122 123 /* 124 * Start next frame in a packed buffer at this boundary. 125 * -1: driver should figure out a good value. 126 * T4: driver will ignore this and use the same value as fl_pad above. 127 * T5: 16, or a power of 2 from 64 to 4096 (both inclusive) is a valid value. 128 */ 129 static int fl_pack = -1; 130 TUNABLE_INT("hw.cxgbe.fl_pack", &fl_pack); 131 132 /* 133 * Allow the driver to create mbuf(s) in a cluster allocated for rx. 134 * 0: never; always allocate mbufs from the zone_mbuf UMA zone. 135 * 1: ok to create mbuf(s) within a cluster if there is room. 136 */ 137 static int allow_mbufs_in_cluster = 1; 138 TUNABLE_INT("hw.cxgbe.allow_mbufs_in_cluster", &allow_mbufs_in_cluster); 139 140 /* 141 * Largest rx cluster size that the driver is allowed to allocate. 142 */ 143 static int largest_rx_cluster = MJUM16BYTES; 144 TUNABLE_INT("hw.cxgbe.largest_rx_cluster", &largest_rx_cluster); 145 146 /* 147 * Size of cluster allocation that's most likely to succeed. The driver will 148 * fall back to this size if it fails to allocate clusters larger than this. 149 */ 150 static int safest_rx_cluster = PAGE_SIZE; 151 TUNABLE_INT("hw.cxgbe.safest_rx_cluster", &safest_rx_cluster); 152 153 /* 154 * The interrupt holdoff timers are multiplied by this value on T6+. 155 * 1 and 3-17 (both inclusive) are legal values. 156 */ 157 static int tscale = 1; 158 TUNABLE_INT("hw.cxgbe.tscale", &tscale); 159 160 /* 161 * Number of LRO entries in the lro_ctrl structure per rx queue. 162 */ 163 static int lro_entries = TCP_LRO_ENTRIES; 164 TUNABLE_INT("hw.cxgbe.lro_entries", &lro_entries); 165 166 /* 167 * This enables presorting of frames before they're fed into tcp_lro_rx. 168 */ 169 static int lro_mbufs = 0; 170 TUNABLE_INT("hw.cxgbe.lro_mbufs", &lro_mbufs); 171 172 struct txpkts { 173 u_int wr_type; /* type 0 or type 1 */ 174 u_int npkt; /* # of packets in this work request */ 175 u_int plen; /* total payload (sum of all packets) */ 176 u_int len16; /* # of 16B pieces used by this work request */ 177 }; 178 179 /* A packet's SGL. This + m_pkthdr has all info needed for tx */ 180 struct sgl { 181 struct sglist sg; 182 struct sglist_seg seg[TX_SGL_SEGS]; 183 }; 184 185 static int service_iq(struct sge_iq *, int); 186 static struct mbuf *get_fl_payload(struct adapter *, struct sge_fl *, uint32_t); 187 static int t4_eth_rx(struct sge_iq *, const struct rss_header *, struct mbuf *); 188 static inline void init_iq(struct sge_iq *, struct adapter *, int, int, int); 189 static inline void init_fl(struct adapter *, struct sge_fl *, int, int, char *); 190 static inline void init_eq(struct adapter *, struct sge_eq *, int, int, uint8_t, 191 uint16_t, char *); 192 static int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *, 193 bus_addr_t *, void **); 194 static int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 195 void *); 196 static int alloc_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *, 197 int, int); 198 static int free_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *); 199 static void add_fl_sysctls(struct adapter *, struct sysctl_ctx_list *, 200 struct sysctl_oid *, struct sge_fl *); 201 static int alloc_fwq(struct adapter *); 202 static int free_fwq(struct adapter *); 203 static int alloc_mgmtq(struct adapter *); 204 static int free_mgmtq(struct adapter *); 205 static int alloc_rxq(struct vi_info *, struct sge_rxq *, int, int, 206 struct sysctl_oid *); 207 static int free_rxq(struct vi_info *, struct sge_rxq *); 208 #ifdef TCP_OFFLOAD 209 static int alloc_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *, int, int, 210 struct sysctl_oid *); 211 static int free_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *); 212 #endif 213 #ifdef DEV_NETMAP 214 static int alloc_nm_rxq(struct vi_info *, struct sge_nm_rxq *, int, int, 215 struct sysctl_oid *); 216 static int free_nm_rxq(struct vi_info *, struct sge_nm_rxq *); 217 static int alloc_nm_txq(struct vi_info *, struct sge_nm_txq *, int, int, 218 struct sysctl_oid *); 219 static int free_nm_txq(struct vi_info *, struct sge_nm_txq *); 220 #endif 221 static int ctrl_eq_alloc(struct adapter *, struct sge_eq *); 222 static int eth_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *); 223 #ifdef TCP_OFFLOAD 224 static int ofld_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *); 225 #endif 226 static int alloc_eq(struct adapter *, struct vi_info *, struct sge_eq *); 227 static int free_eq(struct adapter *, struct sge_eq *); 228 static int alloc_wrq(struct adapter *, struct vi_info *, struct sge_wrq *, 229 struct sysctl_oid *); 230 static int free_wrq(struct adapter *, struct sge_wrq *); 231 static int alloc_txq(struct vi_info *, struct sge_txq *, int, 232 struct sysctl_oid *); 233 static int free_txq(struct vi_info *, struct sge_txq *); 234 static void oneseg_dma_callback(void *, bus_dma_segment_t *, int, int); 235 static inline void ring_fl_db(struct adapter *, struct sge_fl *); 236 static int refill_fl(struct adapter *, struct sge_fl *, int); 237 static void refill_sfl(void *); 238 static int alloc_fl_sdesc(struct sge_fl *); 239 static void free_fl_sdesc(struct adapter *, struct sge_fl *); 240 static void find_best_refill_source(struct adapter *, struct sge_fl *, int); 241 static void find_safe_refill_source(struct adapter *, struct sge_fl *); 242 static void add_fl_to_sfl(struct adapter *, struct sge_fl *); 243 244 static inline void get_pkt_gl(struct mbuf *, struct sglist *); 245 static inline u_int txpkt_len16(u_int, u_int); 246 static inline u_int txpkt_vm_len16(u_int, u_int); 247 static inline u_int txpkts0_len16(u_int); 248 static inline u_int txpkts1_len16(void); 249 static u_int write_txpkt_wr(struct sge_txq *, struct fw_eth_tx_pkt_wr *, 250 struct mbuf *, u_int); 251 static u_int write_txpkt_vm_wr(struct adapter *, struct sge_txq *, 252 struct fw_eth_tx_pkt_vm_wr *, struct mbuf *, u_int); 253 static int try_txpkts(struct mbuf *, struct mbuf *, struct txpkts *, u_int); 254 static int add_to_txpkts(struct mbuf *, struct txpkts *, u_int); 255 static u_int write_txpkts_wr(struct sge_txq *, struct fw_eth_tx_pkts_wr *, 256 struct mbuf *, const struct txpkts *, u_int); 257 static void write_gl_to_txd(struct sge_txq *, struct mbuf *, caddr_t *, int); 258 static inline void copy_to_txd(struct sge_eq *, caddr_t, caddr_t *, int); 259 static inline void ring_eq_db(struct adapter *, struct sge_eq *, u_int); 260 static inline uint16_t read_hw_cidx(struct sge_eq *); 261 static inline u_int reclaimable_tx_desc(struct sge_eq *); 262 static inline u_int total_available_tx_desc(struct sge_eq *); 263 static u_int reclaim_tx_descs(struct sge_txq *, u_int); 264 static void tx_reclaim(void *, int); 265 static __be64 get_flit(struct sglist_seg *, int, int); 266 static int handle_sge_egr_update(struct sge_iq *, const struct rss_header *, 267 struct mbuf *); 268 static int handle_fw_msg(struct sge_iq *, const struct rss_header *, 269 struct mbuf *); 270 static int t4_handle_wrerr_rpl(struct adapter *, const __be64 *); 271 static void wrq_tx_drain(void *, int); 272 static void drain_wrq_wr_list(struct adapter *, struct sge_wrq *); 273 274 static int sysctl_uint16(SYSCTL_HANDLER_ARGS); 275 static int sysctl_bufsizes(SYSCTL_HANDLER_ARGS); 276 static int sysctl_tc(SYSCTL_HANDLER_ARGS); 277 278 static counter_u64_t extfree_refs; 279 static counter_u64_t extfree_rels; 280 281 an_handler_t t4_an_handler; 282 fw_msg_handler_t t4_fw_msg_handler[NUM_FW6_TYPES]; 283 cpl_handler_t t4_cpl_handler[NUM_CPL_CMDS]; 284 285 286 static int 287 an_not_handled(struct sge_iq *iq, const struct rsp_ctrl *ctrl) 288 { 289 290 #ifdef INVARIANTS 291 panic("%s: async notification on iq %p (ctrl %p)", __func__, iq, ctrl); 292 #else 293 log(LOG_ERR, "%s: async notification on iq %p (ctrl %p)\n", 294 __func__, iq, ctrl); 295 #endif 296 return (EDOOFUS); 297 } 298 299 int 300 t4_register_an_handler(an_handler_t h) 301 { 302 uintptr_t *loc, new; 303 304 new = h ? (uintptr_t)h : (uintptr_t)an_not_handled; 305 loc = (uintptr_t *) &t4_an_handler; 306 atomic_store_rel_ptr(loc, new); 307 308 return (0); 309 } 310 311 static int 312 fw_msg_not_handled(struct adapter *sc, const __be64 *rpl) 313 { 314 const struct cpl_fw6_msg *cpl = 315 __containerof(rpl, struct cpl_fw6_msg, data[0]); 316 317 #ifdef INVARIANTS 318 panic("%s: fw_msg type %d", __func__, cpl->type); 319 #else 320 log(LOG_ERR, "%s: fw_msg type %d\n", __func__, cpl->type); 321 #endif 322 return (EDOOFUS); 323 } 324 325 int 326 t4_register_fw_msg_handler(int type, fw_msg_handler_t h) 327 { 328 uintptr_t *loc, new; 329 330 if (type >= nitems(t4_fw_msg_handler)) 331 return (EINVAL); 332 333 /* 334 * These are dispatched by the handler for FW{4|6}_CPL_MSG using the CPL 335 * handler dispatch table. Reject any attempt to install a handler for 336 * this subtype. 337 */ 338 if (type == FW_TYPE_RSSCPL || type == FW6_TYPE_RSSCPL) 339 return (EINVAL); 340 341 new = h ? (uintptr_t)h : (uintptr_t)fw_msg_not_handled; 342 loc = (uintptr_t *) &t4_fw_msg_handler[type]; 343 atomic_store_rel_ptr(loc, new); 344 345 return (0); 346 } 347 348 static int 349 cpl_not_handled(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 350 { 351 352 #ifdef INVARIANTS 353 panic("%s: opcode 0x%02x on iq %p with payload %p", 354 __func__, rss->opcode, iq, m); 355 #else 356 log(LOG_ERR, "%s: opcode 0x%02x on iq %p with payload %p\n", 357 __func__, rss->opcode, iq, m); 358 m_freem(m); 359 #endif 360 return (EDOOFUS); 361 } 362 363 int 364 t4_register_cpl_handler(int opcode, cpl_handler_t h) 365 { 366 uintptr_t *loc, new; 367 368 if (opcode >= nitems(t4_cpl_handler)) 369 return (EINVAL); 370 371 new = h ? (uintptr_t)h : (uintptr_t)cpl_not_handled; 372 loc = (uintptr_t *) &t4_cpl_handler[opcode]; 373 atomic_store_rel_ptr(loc, new); 374 375 return (0); 376 } 377 378 /* 379 * Called on MOD_LOAD. Validates and calculates the SGE tunables. 380 */ 381 void 382 t4_sge_modload(void) 383 { 384 int i; 385 386 if (fl_pktshift < 0 || fl_pktshift > 7) { 387 printf("Invalid hw.cxgbe.fl_pktshift value (%d)," 388 " using 2 instead.\n", fl_pktshift); 389 fl_pktshift = 2; 390 } 391 392 if (spg_len != 64 && spg_len != 128) { 393 int len; 394 395 #if defined(__i386__) || defined(__amd64__) 396 len = cpu_clflush_line_size > 64 ? 128 : 64; 397 #else 398 len = 64; 399 #endif 400 if (spg_len != -1) { 401 printf("Invalid hw.cxgbe.spg_len value (%d)," 402 " using %d instead.\n", spg_len, len); 403 } 404 spg_len = len; 405 } 406 407 if (cong_drop < -1 || cong_drop > 1) { 408 printf("Invalid hw.cxgbe.cong_drop value (%d)," 409 " using 0 instead.\n", cong_drop); 410 cong_drop = 0; 411 } 412 413 if (tscale != 1 && (tscale < 3 || tscale > 17)) { 414 printf("Invalid hw.cxgbe.tscale value (%d)," 415 " using 1 instead.\n", tscale); 416 tscale = 1; 417 } 418 419 extfree_refs = counter_u64_alloc(M_WAITOK); 420 extfree_rels = counter_u64_alloc(M_WAITOK); 421 counter_u64_zero(extfree_refs); 422 counter_u64_zero(extfree_rels); 423 424 t4_an_handler = an_not_handled; 425 for (i = 0; i < nitems(t4_fw_msg_handler); i++) 426 t4_fw_msg_handler[i] = fw_msg_not_handled; 427 for (i = 0; i < nitems(t4_cpl_handler); i++) 428 t4_cpl_handler[i] = cpl_not_handled; 429 430 t4_register_cpl_handler(CPL_FW4_MSG, handle_fw_msg); 431 t4_register_cpl_handler(CPL_FW6_MSG, handle_fw_msg); 432 t4_register_cpl_handler(CPL_SGE_EGR_UPDATE, handle_sge_egr_update); 433 t4_register_cpl_handler(CPL_RX_PKT, t4_eth_rx); 434 t4_register_fw_msg_handler(FW6_TYPE_CMD_RPL, t4_handle_fw_rpl); 435 t4_register_fw_msg_handler(FW6_TYPE_WRERR_RPL, t4_handle_wrerr_rpl); 436 } 437 438 void 439 t4_sge_modunload(void) 440 { 441 442 counter_u64_free(extfree_refs); 443 counter_u64_free(extfree_rels); 444 } 445 446 uint64_t 447 t4_sge_extfree_refs(void) 448 { 449 uint64_t refs, rels; 450 451 rels = counter_u64_fetch(extfree_rels); 452 refs = counter_u64_fetch(extfree_refs); 453 454 return (refs - rels); 455 } 456 457 static inline void 458 setup_pad_and_pack_boundaries(struct adapter *sc) 459 { 460 uint32_t v, m; 461 int pad, pack, pad_shift; 462 463 pad_shift = chip_id(sc) > CHELSIO_T5 ? X_T6_INGPADBOUNDARY_SHIFT : 464 X_INGPADBOUNDARY_SHIFT; 465 pad = fl_pad; 466 if (fl_pad < (1 << pad_shift) || 467 fl_pad > (1 << (pad_shift + M_INGPADBOUNDARY)) || 468 !powerof2(fl_pad)) { 469 /* 470 * If there is any chance that we might use buffer packing and 471 * the chip is a T4, then pick 64 as the pad/pack boundary. Set 472 * it to the minimum allowed in all other cases. 473 */ 474 pad = is_t4(sc) && buffer_packing ? 64 : 1 << pad_shift; 475 476 /* 477 * For fl_pad = 0 we'll still write a reasonable value to the 478 * register but all the freelists will opt out of padding. 479 * We'll complain here only if the user tried to set it to a 480 * value greater than 0 that was invalid. 481 */ 482 if (fl_pad > 0) { 483 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pad value" 484 " (%d), using %d instead.\n", fl_pad, pad); 485 } 486 } 487 m = V_INGPADBOUNDARY(M_INGPADBOUNDARY); 488 v = V_INGPADBOUNDARY(ilog2(pad) - pad_shift); 489 t4_set_reg_field(sc, A_SGE_CONTROL, m, v); 490 491 if (is_t4(sc)) { 492 if (fl_pack != -1 && fl_pack != pad) { 493 /* Complain but carry on. */ 494 device_printf(sc->dev, "hw.cxgbe.fl_pack (%d) ignored," 495 " using %d instead.\n", fl_pack, pad); 496 } 497 return; 498 } 499 500 pack = fl_pack; 501 if (fl_pack < 16 || fl_pack == 32 || fl_pack > 4096 || 502 !powerof2(fl_pack)) { 503 pack = max(sc->params.pci.mps, CACHE_LINE_SIZE); 504 MPASS(powerof2(pack)); 505 if (pack < 16) 506 pack = 16; 507 if (pack == 32) 508 pack = 64; 509 if (pack > 4096) 510 pack = 4096; 511 if (fl_pack != -1) { 512 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pack value" 513 " (%d), using %d instead.\n", fl_pack, pack); 514 } 515 } 516 m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY); 517 if (pack == 16) 518 v = V_INGPACKBOUNDARY(0); 519 else 520 v = V_INGPACKBOUNDARY(ilog2(pack) - 5); 521 522 MPASS(!is_t4(sc)); /* T4 doesn't have SGE_CONTROL2 */ 523 t4_set_reg_field(sc, A_SGE_CONTROL2, m, v); 524 } 525 526 /* 527 * adap->params.vpd.cclk must be set up before this is called. 528 */ 529 void 530 t4_tweak_chip_settings(struct adapter *sc) 531 { 532 int i; 533 uint32_t v, m; 534 int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200}; 535 int timer_max = M_TIMERVALUE0 * 1000 / sc->params.vpd.cclk; 536 int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */ 537 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 538 static int sge_flbuf_sizes[] = { 539 MCLBYTES, 540 #if MJUMPAGESIZE != MCLBYTES 541 MJUMPAGESIZE, 542 MJUMPAGESIZE - CL_METADATA_SIZE, 543 MJUMPAGESIZE - 2 * MSIZE - CL_METADATA_SIZE, 544 #endif 545 MJUM9BYTES, 546 MJUM16BYTES, 547 MCLBYTES - MSIZE - CL_METADATA_SIZE, 548 MJUM9BYTES - CL_METADATA_SIZE, 549 MJUM16BYTES - CL_METADATA_SIZE, 550 }; 551 552 KASSERT(sc->flags & MASTER_PF, 553 ("%s: trying to change chip settings when not master.", __func__)); 554 555 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE; 556 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE | 557 V_EGRSTATUSPAGESIZE(spg_len == 128); 558 t4_set_reg_field(sc, A_SGE_CONTROL, m, v); 559 560 setup_pad_and_pack_boundaries(sc); 561 562 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) | 563 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) | 564 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) | 565 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) | 566 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) | 567 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) | 568 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) | 569 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10); 570 t4_write_reg(sc, A_SGE_HOST_PAGE_SIZE, v); 571 572 KASSERT(nitems(sge_flbuf_sizes) <= SGE_FLBUF_SIZES, 573 ("%s: hw buffer size table too big", __func__)); 574 for (i = 0; i < min(nitems(sge_flbuf_sizes), SGE_FLBUF_SIZES); i++) { 575 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0 + (4 * i), 576 sge_flbuf_sizes[i]); 577 } 578 579 v = V_THRESHOLD_0(intr_pktcount[0]) | V_THRESHOLD_1(intr_pktcount[1]) | 580 V_THRESHOLD_2(intr_pktcount[2]) | V_THRESHOLD_3(intr_pktcount[3]); 581 t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD, v); 582 583 KASSERT(intr_timer[0] <= timer_max, 584 ("%s: not a single usable timer (%d, %d)", __func__, intr_timer[0], 585 timer_max)); 586 for (i = 1; i < nitems(intr_timer); i++) { 587 KASSERT(intr_timer[i] >= intr_timer[i - 1], 588 ("%s: timers not listed in increasing order (%d)", 589 __func__, i)); 590 591 while (intr_timer[i] > timer_max) { 592 if (i == nitems(intr_timer) - 1) { 593 intr_timer[i] = timer_max; 594 break; 595 } 596 intr_timer[i] += intr_timer[i - 1]; 597 intr_timer[i] /= 2; 598 } 599 } 600 601 v = V_TIMERVALUE0(us_to_core_ticks(sc, intr_timer[0])) | 602 V_TIMERVALUE1(us_to_core_ticks(sc, intr_timer[1])); 603 t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1, v); 604 v = V_TIMERVALUE2(us_to_core_ticks(sc, intr_timer[2])) | 605 V_TIMERVALUE3(us_to_core_ticks(sc, intr_timer[3])); 606 t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3, v); 607 v = V_TIMERVALUE4(us_to_core_ticks(sc, intr_timer[4])) | 608 V_TIMERVALUE5(us_to_core_ticks(sc, intr_timer[5])); 609 t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5, v); 610 611 if (chip_id(sc) >= CHELSIO_T6) { 612 m = V_TSCALE(M_TSCALE); 613 if (tscale == 1) 614 v = 0; 615 else 616 v = V_TSCALE(tscale - 2); 617 t4_set_reg_field(sc, A_SGE_ITP_CONTROL, m, v); 618 } 619 620 /* 4K, 16K, 64K, 256K DDP "page sizes" for TDDP */ 621 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 622 t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, v); 623 624 /* 625 * 4K, 8K, 16K, 64K DDP "page sizes" for iSCSI DDP. These have been 626 * chosen with MAXPHYS = 128K in mind. The largest DDP buffer that we 627 * may have to deal with is MAXPHYS + 1 page. 628 */ 629 v = V_HPZ0(0) | V_HPZ1(1) | V_HPZ2(2) | V_HPZ3(4); 630 t4_write_reg(sc, A_ULP_RX_ISCSI_PSZ, v); 631 632 /* We use multiple DDP page sizes both in plain-TOE and ISCSI modes. */ 633 m = v = F_TDDPTAGTCB | F_ISCSITAGTCB; 634 t4_set_reg_field(sc, A_ULP_RX_CTL, m, v); 635 636 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 637 F_RESETDDPOFFSET; 638 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 639 t4_set_reg_field(sc, A_TP_PARA_REG5, m, v); 640 } 641 642 /* 643 * SGE wants the buffer to be at least 64B and then a multiple of 16. If 644 * padding is in use, the buffer's start and end need to be aligned to the pad 645 * boundary as well. We'll just make sure that the size is a multiple of the 646 * boundary here, it is up to the buffer allocation code to make sure the start 647 * of the buffer is aligned as well. 648 */ 649 static inline int 650 hwsz_ok(struct adapter *sc, int hwsz) 651 { 652 int mask = fl_pad ? sc->params.sge.pad_boundary - 1 : 16 - 1; 653 654 return (hwsz >= 64 && (hwsz & mask) == 0); 655 } 656 657 /* 658 * XXX: driver really should be able to deal with unexpected settings. 659 */ 660 int 661 t4_read_chip_settings(struct adapter *sc) 662 { 663 struct sge *s = &sc->sge; 664 struct sge_params *sp = &sc->params.sge; 665 int i, j, n, rc = 0; 666 uint32_t m, v, r; 667 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 668 static int sw_buf_sizes[] = { /* Sorted by size */ 669 MCLBYTES, 670 #if MJUMPAGESIZE != MCLBYTES 671 MJUMPAGESIZE, 672 #endif 673 MJUM9BYTES, 674 MJUM16BYTES 675 }; 676 struct sw_zone_info *swz, *safe_swz; 677 struct hw_buf_info *hwb; 678 679 m = F_RXPKTCPLMODE; 680 v = F_RXPKTCPLMODE; 681 r = sc->params.sge.sge_control; 682 if ((r & m) != v) { 683 device_printf(sc->dev, "invalid SGE_CONTROL(0x%x)\n", r); 684 rc = EINVAL; 685 } 686 687 /* 688 * If this changes then every single use of PAGE_SHIFT in the driver 689 * needs to be carefully reviewed for PAGE_SHIFT vs sp->page_shift. 690 */ 691 if (sp->page_shift != PAGE_SHIFT) { 692 device_printf(sc->dev, "invalid SGE_HOST_PAGE_SIZE(0x%x)\n", r); 693 rc = EINVAL; 694 } 695 696 /* Filter out unusable hw buffer sizes entirely (mark with -2). */ 697 hwb = &s->hw_buf_info[0]; 698 for (i = 0; i < nitems(s->hw_buf_info); i++, hwb++) { 699 r = sc->params.sge.sge_fl_buffer_size[i]; 700 hwb->size = r; 701 hwb->zidx = hwsz_ok(sc, r) ? -1 : -2; 702 hwb->next = -1; 703 } 704 705 /* 706 * Create a sorted list in decreasing order of hw buffer sizes (and so 707 * increasing order of spare area) for each software zone. 708 * 709 * If padding is enabled then the start and end of the buffer must align 710 * to the pad boundary; if packing is enabled then they must align with 711 * the pack boundary as well. Allocations from the cluster zones are 712 * aligned to min(size, 4K), so the buffer starts at that alignment and 713 * ends at hwb->size alignment. If mbuf inlining is allowed the 714 * starting alignment will be reduced to MSIZE and the driver will 715 * exercise appropriate caution when deciding on the best buffer layout 716 * to use. 717 */ 718 n = 0; /* no usable buffer size to begin with */ 719 swz = &s->sw_zone_info[0]; 720 safe_swz = NULL; 721 for (i = 0; i < SW_ZONE_SIZES; i++, swz++) { 722 int8_t head = -1, tail = -1; 723 724 swz->size = sw_buf_sizes[i]; 725 swz->zone = m_getzone(swz->size); 726 swz->type = m_gettype(swz->size); 727 728 if (swz->size < PAGE_SIZE) { 729 MPASS(powerof2(swz->size)); 730 if (fl_pad && (swz->size % sp->pad_boundary != 0)) 731 continue; 732 } 733 734 if (swz->size == safest_rx_cluster) 735 safe_swz = swz; 736 737 hwb = &s->hw_buf_info[0]; 738 for (j = 0; j < SGE_FLBUF_SIZES; j++, hwb++) { 739 if (hwb->zidx != -1 || hwb->size > swz->size) 740 continue; 741 #ifdef INVARIANTS 742 if (fl_pad) 743 MPASS(hwb->size % sp->pad_boundary == 0); 744 #endif 745 hwb->zidx = i; 746 if (head == -1) 747 head = tail = j; 748 else if (hwb->size < s->hw_buf_info[tail].size) { 749 s->hw_buf_info[tail].next = j; 750 tail = j; 751 } else { 752 int8_t *cur; 753 struct hw_buf_info *t; 754 755 for (cur = &head; *cur != -1; cur = &t->next) { 756 t = &s->hw_buf_info[*cur]; 757 if (hwb->size == t->size) { 758 hwb->zidx = -2; 759 break; 760 } 761 if (hwb->size > t->size) { 762 hwb->next = *cur; 763 *cur = j; 764 break; 765 } 766 } 767 } 768 } 769 swz->head_hwidx = head; 770 swz->tail_hwidx = tail; 771 772 if (tail != -1) { 773 n++; 774 if (swz->size - s->hw_buf_info[tail].size >= 775 CL_METADATA_SIZE) 776 sc->flags |= BUF_PACKING_OK; 777 } 778 } 779 if (n == 0) { 780 device_printf(sc->dev, "no usable SGE FL buffer size.\n"); 781 rc = EINVAL; 782 } 783 784 s->safe_hwidx1 = -1; 785 s->safe_hwidx2 = -1; 786 if (safe_swz != NULL) { 787 s->safe_hwidx1 = safe_swz->head_hwidx; 788 for (i = safe_swz->head_hwidx; i != -1; i = hwb->next) { 789 int spare; 790 791 hwb = &s->hw_buf_info[i]; 792 #ifdef INVARIANTS 793 if (fl_pad) 794 MPASS(hwb->size % sp->pad_boundary == 0); 795 #endif 796 spare = safe_swz->size - hwb->size; 797 if (spare >= CL_METADATA_SIZE) { 798 s->safe_hwidx2 = i; 799 break; 800 } 801 } 802 } 803 804 if (sc->flags & IS_VF) 805 return (0); 806 807 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 808 r = t4_read_reg(sc, A_ULP_RX_TDDP_PSZ); 809 if (r != v) { 810 device_printf(sc->dev, "invalid ULP_RX_TDDP_PSZ(0x%x)\n", r); 811 rc = EINVAL; 812 } 813 814 m = v = F_TDDPTAGTCB; 815 r = t4_read_reg(sc, A_ULP_RX_CTL); 816 if ((r & m) != v) { 817 device_printf(sc->dev, "invalid ULP_RX_CTL(0x%x)\n", r); 818 rc = EINVAL; 819 } 820 821 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 822 F_RESETDDPOFFSET; 823 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 824 r = t4_read_reg(sc, A_TP_PARA_REG5); 825 if ((r & m) != v) { 826 device_printf(sc->dev, "invalid TP_PARA_REG5(0x%x)\n", r); 827 rc = EINVAL; 828 } 829 830 t4_init_tp_params(sc); 831 832 t4_read_mtu_tbl(sc, sc->params.mtus, NULL); 833 t4_load_mtus(sc, sc->params.mtus, sc->params.a_wnd, sc->params.b_wnd); 834 835 return (rc); 836 } 837 838 int 839 t4_create_dma_tag(struct adapter *sc) 840 { 841 int rc; 842 843 rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0, 844 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE, 845 BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL, 846 NULL, &sc->dmat); 847 if (rc != 0) { 848 device_printf(sc->dev, 849 "failed to create main DMA tag: %d\n", rc); 850 } 851 852 return (rc); 853 } 854 855 void 856 t4_sge_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx, 857 struct sysctl_oid_list *children) 858 { 859 struct sge_params *sp = &sc->params.sge; 860 861 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "buffer_sizes", 862 CTLTYPE_STRING | CTLFLAG_RD, &sc->sge, 0, sysctl_bufsizes, "A", 863 "freelist buffer sizes"); 864 865 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pktshift", CTLFLAG_RD, 866 NULL, sp->fl_pktshift, "payload DMA offset in rx buffer (bytes)"); 867 868 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pad", CTLFLAG_RD, 869 NULL, sp->pad_boundary, "payload pad boundary (bytes)"); 870 871 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "spg_len", CTLFLAG_RD, 872 NULL, sp->spg_len, "status page size (bytes)"); 873 874 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_drop", CTLFLAG_RD, 875 NULL, cong_drop, "congestion drop setting"); 876 877 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pack", CTLFLAG_RD, 878 NULL, sp->pack_boundary, "payload pack boundary (bytes)"); 879 } 880 881 int 882 t4_destroy_dma_tag(struct adapter *sc) 883 { 884 if (sc->dmat) 885 bus_dma_tag_destroy(sc->dmat); 886 887 return (0); 888 } 889 890 /* 891 * Allocate and initialize the firmware event queue and the management queue. 892 * 893 * Returns errno on failure. Resources allocated up to that point may still be 894 * allocated. Caller is responsible for cleanup in case this function fails. 895 */ 896 int 897 t4_setup_adapter_queues(struct adapter *sc) 898 { 899 int rc; 900 901 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 902 903 sysctl_ctx_init(&sc->ctx); 904 sc->flags |= ADAP_SYSCTL_CTX; 905 906 /* 907 * Firmware event queue 908 */ 909 rc = alloc_fwq(sc); 910 if (rc != 0) 911 return (rc); 912 913 /* 914 * Management queue. This is just a control queue that uses the fwq as 915 * its associated iq. 916 */ 917 if (!(sc->flags & IS_VF)) 918 rc = alloc_mgmtq(sc); 919 920 return (rc); 921 } 922 923 /* 924 * Idempotent 925 */ 926 int 927 t4_teardown_adapter_queues(struct adapter *sc) 928 { 929 930 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 931 932 /* Do this before freeing the queue */ 933 if (sc->flags & ADAP_SYSCTL_CTX) { 934 sysctl_ctx_free(&sc->ctx); 935 sc->flags &= ~ADAP_SYSCTL_CTX; 936 } 937 938 free_mgmtq(sc); 939 free_fwq(sc); 940 941 return (0); 942 } 943 944 static inline int 945 first_vector(struct vi_info *vi) 946 { 947 struct adapter *sc = vi->pi->adapter; 948 949 if (sc->intr_count == 1) 950 return (0); 951 952 return (vi->first_intr); 953 } 954 955 /* 956 * Given an arbitrary "index," come up with an iq that can be used by other 957 * queues (of this VI) for interrupt forwarding, SGE egress updates, etc. 958 * The iq returned is guaranteed to be something that takes direct interrupts. 959 */ 960 static struct sge_iq * 961 vi_intr_iq(struct vi_info *vi, int idx) 962 { 963 struct adapter *sc = vi->pi->adapter; 964 struct sge *s = &sc->sge; 965 struct sge_iq *iq = NULL; 966 int nintr, i; 967 968 if (sc->intr_count == 1) 969 return (&sc->sge.fwq); 970 971 nintr = vi->nintr; 972 #ifdef DEV_NETMAP 973 /* Do not consider any netmap-only interrupts */ 974 if (vi->flags & INTR_RXQ && vi->nnmrxq > vi->nrxq) 975 nintr -= vi->nnmrxq - vi->nrxq; 976 #endif 977 KASSERT(nintr != 0, 978 ("%s: vi %p has no exclusive interrupts, total interrupts = %d", 979 __func__, vi, sc->intr_count)); 980 i = idx % nintr; 981 982 if (vi->flags & INTR_RXQ) { 983 if (i < vi->nrxq) { 984 iq = &s->rxq[vi->first_rxq + i].iq; 985 goto done; 986 } 987 i -= vi->nrxq; 988 } 989 #ifdef TCP_OFFLOAD 990 if (vi->flags & INTR_OFLD_RXQ) { 991 if (i < vi->nofldrxq) { 992 iq = &s->ofld_rxq[vi->first_ofld_rxq + i].iq; 993 goto done; 994 } 995 i -= vi->nofldrxq; 996 } 997 #endif 998 panic("%s: vi %p, intr_flags 0x%lx, idx %d, total intr %d\n", __func__, 999 vi, vi->flags & INTR_ALL, idx, nintr); 1000 done: 1001 MPASS(iq != NULL); 1002 KASSERT(iq->flags & IQ_INTR, 1003 ("%s: iq %p (vi %p, intr_flags 0x%lx, idx %d)", __func__, iq, vi, 1004 vi->flags & INTR_ALL, idx)); 1005 return (iq); 1006 } 1007 1008 /* Maximum payload that can be delivered with a single iq descriptor */ 1009 static inline int 1010 mtu_to_max_payload(struct adapter *sc, int mtu, const int toe) 1011 { 1012 int payload; 1013 1014 #ifdef TCP_OFFLOAD 1015 if (toe) { 1016 payload = sc->tt.rx_coalesce ? 1017 G_RXCOALESCESIZE(t4_read_reg(sc, A_TP_PARA_REG2)) : mtu; 1018 } else { 1019 #endif 1020 /* large enough even when hw VLAN extraction is disabled */ 1021 payload = sc->params.sge.fl_pktshift + ETHER_HDR_LEN + 1022 ETHER_VLAN_ENCAP_LEN + mtu; 1023 #ifdef TCP_OFFLOAD 1024 } 1025 #endif 1026 1027 return (payload); 1028 } 1029 1030 int 1031 t4_setup_vi_queues(struct vi_info *vi) 1032 { 1033 int rc = 0, i, j, intr_idx, iqid; 1034 struct sge_rxq *rxq; 1035 struct sge_txq *txq; 1036 struct sge_wrq *ctrlq; 1037 #ifdef TCP_OFFLOAD 1038 struct sge_ofld_rxq *ofld_rxq; 1039 struct sge_wrq *ofld_txq; 1040 #endif 1041 #ifdef DEV_NETMAP 1042 int saved_idx; 1043 struct sge_nm_rxq *nm_rxq; 1044 struct sge_nm_txq *nm_txq; 1045 #endif 1046 char name[16]; 1047 struct port_info *pi = vi->pi; 1048 struct adapter *sc = pi->adapter; 1049 struct ifnet *ifp = vi->ifp; 1050 struct sysctl_oid *oid = device_get_sysctl_tree(vi->dev); 1051 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 1052 int maxp, mtu = ifp->if_mtu; 1053 1054 /* Interrupt vector to start from (when using multiple vectors) */ 1055 intr_idx = first_vector(vi); 1056 1057 #ifdef DEV_NETMAP 1058 saved_idx = intr_idx; 1059 if (ifp->if_capabilities & IFCAP_NETMAP) { 1060 1061 /* netmap is supported with direct interrupts only. */ 1062 MPASS(vi->flags & INTR_RXQ); 1063 1064 /* 1065 * We don't have buffers to back the netmap rx queues 1066 * right now so we create the queues in a way that 1067 * doesn't set off any congestion signal in the chip. 1068 */ 1069 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "nm_rxq", 1070 CTLFLAG_RD, NULL, "rx queues"); 1071 for_each_nm_rxq(vi, i, nm_rxq) { 1072 rc = alloc_nm_rxq(vi, nm_rxq, intr_idx, i, oid); 1073 if (rc != 0) 1074 goto done; 1075 intr_idx++; 1076 } 1077 1078 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "nm_txq", 1079 CTLFLAG_RD, NULL, "tx queues"); 1080 for_each_nm_txq(vi, i, nm_txq) { 1081 iqid = vi->first_nm_rxq + (i % vi->nnmrxq); 1082 rc = alloc_nm_txq(vi, nm_txq, iqid, i, oid); 1083 if (rc != 0) 1084 goto done; 1085 } 1086 } 1087 1088 /* Normal rx queues and netmap rx queues share the same interrupts. */ 1089 intr_idx = saved_idx; 1090 #endif 1091 1092 /* 1093 * First pass over all NIC and TOE rx queues: 1094 * a) initialize iq and fl 1095 * b) allocate queue iff it will take direct interrupts. 1096 */ 1097 maxp = mtu_to_max_payload(sc, mtu, 0); 1098 if (vi->flags & INTR_RXQ) { 1099 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "rxq", 1100 CTLFLAG_RD, NULL, "rx queues"); 1101 } 1102 for_each_rxq(vi, i, rxq) { 1103 1104 init_iq(&rxq->iq, sc, vi->tmr_idx, vi->pktc_idx, vi->qsize_rxq); 1105 1106 snprintf(name, sizeof(name), "%s rxq%d-fl", 1107 device_get_nameunit(vi->dev), i); 1108 init_fl(sc, &rxq->fl, vi->qsize_rxq / 8, maxp, name); 1109 1110 if (vi->flags & INTR_RXQ) { 1111 rxq->iq.flags |= IQ_INTR; 1112 rc = alloc_rxq(vi, rxq, intr_idx, i, oid); 1113 if (rc != 0) 1114 goto done; 1115 intr_idx++; 1116 } 1117 } 1118 #ifdef DEV_NETMAP 1119 if (ifp->if_capabilities & IFCAP_NETMAP) 1120 intr_idx = saved_idx + max(vi->nrxq, vi->nnmrxq); 1121 #endif 1122 #ifdef TCP_OFFLOAD 1123 maxp = mtu_to_max_payload(sc, mtu, 1); 1124 if (vi->flags & INTR_OFLD_RXQ) { 1125 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_rxq", 1126 CTLFLAG_RD, NULL, 1127 "rx queues for offloaded TCP connections"); 1128 } 1129 for_each_ofld_rxq(vi, i, ofld_rxq) { 1130 1131 init_iq(&ofld_rxq->iq, sc, vi->tmr_idx, vi->pktc_idx, 1132 vi->qsize_rxq); 1133 1134 snprintf(name, sizeof(name), "%s ofld_rxq%d-fl", 1135 device_get_nameunit(vi->dev), i); 1136 init_fl(sc, &ofld_rxq->fl, vi->qsize_rxq / 8, maxp, name); 1137 1138 if (vi->flags & INTR_OFLD_RXQ) { 1139 ofld_rxq->iq.flags |= IQ_INTR; 1140 rc = alloc_ofld_rxq(vi, ofld_rxq, intr_idx, i, oid); 1141 if (rc != 0) 1142 goto done; 1143 intr_idx++; 1144 } 1145 } 1146 #endif 1147 1148 /* 1149 * Second pass over all NIC and TOE rx queues. The queues forwarding 1150 * their interrupts are allocated now. 1151 */ 1152 j = 0; 1153 if (!(vi->flags & INTR_RXQ)) { 1154 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "rxq", 1155 CTLFLAG_RD, NULL, "rx queues"); 1156 for_each_rxq(vi, i, rxq) { 1157 MPASS(!(rxq->iq.flags & IQ_INTR)); 1158 1159 intr_idx = vi_intr_iq(vi, j)->abs_id; 1160 1161 rc = alloc_rxq(vi, rxq, intr_idx, i, oid); 1162 if (rc != 0) 1163 goto done; 1164 j++; 1165 } 1166 } 1167 #ifdef TCP_OFFLOAD 1168 if (vi->nofldrxq != 0 && !(vi->flags & INTR_OFLD_RXQ)) { 1169 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_rxq", 1170 CTLFLAG_RD, NULL, 1171 "rx queues for offloaded TCP connections"); 1172 for_each_ofld_rxq(vi, i, ofld_rxq) { 1173 MPASS(!(ofld_rxq->iq.flags & IQ_INTR)); 1174 1175 intr_idx = vi_intr_iq(vi, j)->abs_id; 1176 1177 rc = alloc_ofld_rxq(vi, ofld_rxq, intr_idx, i, oid); 1178 if (rc != 0) 1179 goto done; 1180 j++; 1181 } 1182 } 1183 #endif 1184 1185 /* 1186 * Now the tx queues. Only one pass needed. 1187 */ 1188 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "txq", CTLFLAG_RD, 1189 NULL, "tx queues"); 1190 j = 0; 1191 for_each_txq(vi, i, txq) { 1192 iqid = vi_intr_iq(vi, j)->cntxt_id; 1193 snprintf(name, sizeof(name), "%s txq%d", 1194 device_get_nameunit(vi->dev), i); 1195 init_eq(sc, &txq->eq, EQ_ETH, vi->qsize_txq, pi->tx_chan, iqid, 1196 name); 1197 1198 rc = alloc_txq(vi, txq, i, oid); 1199 if (rc != 0) 1200 goto done; 1201 j++; 1202 } 1203 #ifdef TCP_OFFLOAD 1204 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_txq", 1205 CTLFLAG_RD, NULL, "tx queues for offloaded TCP connections"); 1206 for_each_ofld_txq(vi, i, ofld_txq) { 1207 struct sysctl_oid *oid2; 1208 1209 iqid = vi_intr_iq(vi, j)->cntxt_id; 1210 snprintf(name, sizeof(name), "%s ofld_txq%d", 1211 device_get_nameunit(vi->dev), i); 1212 init_eq(sc, &ofld_txq->eq, EQ_OFLD, vi->qsize_txq, pi->tx_chan, 1213 iqid, name); 1214 1215 snprintf(name, sizeof(name), "%d", i); 1216 oid2 = SYSCTL_ADD_NODE(&vi->ctx, SYSCTL_CHILDREN(oid), OID_AUTO, 1217 name, CTLFLAG_RD, NULL, "offload tx queue"); 1218 1219 rc = alloc_wrq(sc, vi, ofld_txq, oid2); 1220 if (rc != 0) 1221 goto done; 1222 j++; 1223 } 1224 #endif 1225 1226 /* 1227 * Finally, the control queue. 1228 */ 1229 if (!IS_MAIN_VI(vi) || sc->flags & IS_VF) 1230 goto done; 1231 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ctrlq", CTLFLAG_RD, 1232 NULL, "ctrl queue"); 1233 ctrlq = &sc->sge.ctrlq[pi->port_id]; 1234 iqid = vi_intr_iq(vi, 0)->cntxt_id; 1235 snprintf(name, sizeof(name), "%s ctrlq", device_get_nameunit(vi->dev)); 1236 init_eq(sc, &ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE, pi->tx_chan, iqid, 1237 name); 1238 rc = alloc_wrq(sc, vi, ctrlq, oid); 1239 1240 done: 1241 if (rc) 1242 t4_teardown_vi_queues(vi); 1243 1244 return (rc); 1245 } 1246 1247 /* 1248 * Idempotent 1249 */ 1250 int 1251 t4_teardown_vi_queues(struct vi_info *vi) 1252 { 1253 int i; 1254 struct port_info *pi = vi->pi; 1255 struct adapter *sc = pi->adapter; 1256 struct sge_rxq *rxq; 1257 struct sge_txq *txq; 1258 #ifdef TCP_OFFLOAD 1259 struct sge_ofld_rxq *ofld_rxq; 1260 struct sge_wrq *ofld_txq; 1261 #endif 1262 #ifdef DEV_NETMAP 1263 struct sge_nm_rxq *nm_rxq; 1264 struct sge_nm_txq *nm_txq; 1265 #endif 1266 1267 /* Do this before freeing the queues */ 1268 if (vi->flags & VI_SYSCTL_CTX) { 1269 sysctl_ctx_free(&vi->ctx); 1270 vi->flags &= ~VI_SYSCTL_CTX; 1271 } 1272 1273 #ifdef DEV_NETMAP 1274 if (vi->ifp->if_capabilities & IFCAP_NETMAP) { 1275 for_each_nm_txq(vi, i, nm_txq) { 1276 free_nm_txq(vi, nm_txq); 1277 } 1278 1279 for_each_nm_rxq(vi, i, nm_rxq) { 1280 free_nm_rxq(vi, nm_rxq); 1281 } 1282 } 1283 #endif 1284 1285 /* 1286 * Take down all the tx queues first, as they reference the rx queues 1287 * (for egress updates, etc.). 1288 */ 1289 1290 if (IS_MAIN_VI(vi) && !(sc->flags & IS_VF)) 1291 free_wrq(sc, &sc->sge.ctrlq[pi->port_id]); 1292 1293 for_each_txq(vi, i, txq) { 1294 free_txq(vi, txq); 1295 } 1296 #ifdef TCP_OFFLOAD 1297 for_each_ofld_txq(vi, i, ofld_txq) { 1298 free_wrq(sc, ofld_txq); 1299 } 1300 #endif 1301 1302 /* 1303 * Then take down the rx queues that forward their interrupts, as they 1304 * reference other rx queues. 1305 */ 1306 1307 for_each_rxq(vi, i, rxq) { 1308 if ((rxq->iq.flags & IQ_INTR) == 0) 1309 free_rxq(vi, rxq); 1310 } 1311 #ifdef TCP_OFFLOAD 1312 for_each_ofld_rxq(vi, i, ofld_rxq) { 1313 if ((ofld_rxq->iq.flags & IQ_INTR) == 0) 1314 free_ofld_rxq(vi, ofld_rxq); 1315 } 1316 #endif 1317 1318 /* 1319 * Then take down the rx queues that take direct interrupts. 1320 */ 1321 1322 for_each_rxq(vi, i, rxq) { 1323 if (rxq->iq.flags & IQ_INTR) 1324 free_rxq(vi, rxq); 1325 } 1326 #ifdef TCP_OFFLOAD 1327 for_each_ofld_rxq(vi, i, ofld_rxq) { 1328 if (ofld_rxq->iq.flags & IQ_INTR) 1329 free_ofld_rxq(vi, ofld_rxq); 1330 } 1331 #endif 1332 1333 return (0); 1334 } 1335 1336 /* 1337 * Deals with errors and the firmware event queue. All data rx queues forward 1338 * their interrupt to the firmware event queue. 1339 */ 1340 void 1341 t4_intr_all(void *arg) 1342 { 1343 struct adapter *sc = arg; 1344 struct sge_iq *fwq = &sc->sge.fwq; 1345 1346 t4_intr_err(arg); 1347 if (atomic_cmpset_int(&fwq->state, IQS_IDLE, IQS_BUSY)) { 1348 service_iq(fwq, 0); 1349 atomic_cmpset_int(&fwq->state, IQS_BUSY, IQS_IDLE); 1350 } 1351 } 1352 1353 /* Deals with error interrupts */ 1354 void 1355 t4_intr_err(void *arg) 1356 { 1357 struct adapter *sc = arg; 1358 1359 t4_write_reg(sc, MYPF_REG(A_PCIE_PF_CLI), 0); 1360 t4_slow_intr_handler(sc); 1361 } 1362 1363 void 1364 t4_intr_evt(void *arg) 1365 { 1366 struct sge_iq *iq = arg; 1367 1368 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 1369 service_iq(iq, 0); 1370 atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 1371 } 1372 } 1373 1374 void 1375 t4_intr(void *arg) 1376 { 1377 struct sge_iq *iq = arg; 1378 1379 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 1380 service_iq(iq, 0); 1381 atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 1382 } 1383 } 1384 1385 void 1386 t4_vi_intr(void *arg) 1387 { 1388 struct irq *irq = arg; 1389 1390 #ifdef DEV_NETMAP 1391 if (atomic_cmpset_int(&irq->nm_state, NM_ON, NM_BUSY)) { 1392 t4_nm_intr(irq->nm_rxq); 1393 atomic_cmpset_int(&irq->nm_state, NM_BUSY, NM_ON); 1394 } 1395 #endif 1396 if (irq->rxq != NULL) 1397 t4_intr(irq->rxq); 1398 } 1399 1400 static inline int 1401 sort_before_lro(struct lro_ctrl *lro) 1402 { 1403 1404 return (lro->lro_mbuf_max != 0); 1405 } 1406 1407 /* 1408 * Deals with anything and everything on the given ingress queue. 1409 */ 1410 static int 1411 service_iq(struct sge_iq *iq, int budget) 1412 { 1413 struct sge_iq *q; 1414 struct sge_rxq *rxq = iq_to_rxq(iq); /* Use iff iq is part of rxq */ 1415 struct sge_fl *fl; /* Use iff IQ_HAS_FL */ 1416 struct adapter *sc = iq->adapter; 1417 struct iq_desc *d = &iq->desc[iq->cidx]; 1418 int ndescs = 0, limit; 1419 int rsp_type, refill; 1420 uint32_t lq; 1421 uint16_t fl_hw_cidx; 1422 struct mbuf *m0; 1423 STAILQ_HEAD(, sge_iq) iql = STAILQ_HEAD_INITIALIZER(iql); 1424 #if defined(INET) || defined(INET6) 1425 const struct timeval lro_timeout = {0, sc->lro_timeout}; 1426 struct lro_ctrl *lro = &rxq->lro; 1427 #endif 1428 1429 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq)); 1430 1431 limit = budget ? budget : iq->qsize / 16; 1432 1433 if (iq->flags & IQ_HAS_FL) { 1434 fl = &rxq->fl; 1435 fl_hw_cidx = fl->hw_cidx; /* stable snapshot */ 1436 } else { 1437 fl = NULL; 1438 fl_hw_cidx = 0; /* to silence gcc warning */ 1439 } 1440 1441 #if defined(INET) || defined(INET6) 1442 if (iq->flags & IQ_ADJ_CREDIT) { 1443 MPASS(sort_before_lro(lro)); 1444 iq->flags &= ~IQ_ADJ_CREDIT; 1445 if ((d->rsp.u.type_gen & F_RSPD_GEN) != iq->gen) { 1446 tcp_lro_flush_all(lro); 1447 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(1) | 1448 V_INGRESSQID((u32)iq->cntxt_id) | 1449 V_SEINTARM(iq->intr_params)); 1450 return (0); 1451 } 1452 ndescs = 1; 1453 } 1454 #else 1455 MPASS((iq->flags & IQ_ADJ_CREDIT) == 0); 1456 #endif 1457 1458 /* 1459 * We always come back and check the descriptor ring for new indirect 1460 * interrupts and other responses after running a single handler. 1461 */ 1462 for (;;) { 1463 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) { 1464 1465 rmb(); 1466 1467 refill = 0; 1468 m0 = NULL; 1469 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen); 1470 lq = be32toh(d->rsp.pldbuflen_qid); 1471 1472 switch (rsp_type) { 1473 case X_RSPD_TYPE_FLBUF: 1474 1475 KASSERT(iq->flags & IQ_HAS_FL, 1476 ("%s: data for an iq (%p) with no freelist", 1477 __func__, iq)); 1478 1479 m0 = get_fl_payload(sc, fl, lq); 1480 if (__predict_false(m0 == NULL)) 1481 goto process_iql; 1482 refill = IDXDIFF(fl->hw_cidx, fl_hw_cidx, fl->sidx) > 2; 1483 #ifdef T4_PKT_TIMESTAMP 1484 /* 1485 * 60 bit timestamp for the payload is 1486 * *(uint64_t *)m0->m_pktdat. Note that it is 1487 * in the leading free-space in the mbuf. The 1488 * kernel can clobber it during a pullup, 1489 * m_copymdata, etc. You need to make sure that 1490 * the mbuf reaches you unmolested if you care 1491 * about the timestamp. 1492 */ 1493 *(uint64_t *)m0->m_pktdat = 1494 be64toh(ctrl->u.last_flit) & 1495 0xfffffffffffffff; 1496 #endif 1497 1498 /* fall through */ 1499 1500 case X_RSPD_TYPE_CPL: 1501 KASSERT(d->rss.opcode < NUM_CPL_CMDS, 1502 ("%s: bad opcode %02x.", __func__, 1503 d->rss.opcode)); 1504 t4_cpl_handler[d->rss.opcode](iq, &d->rss, m0); 1505 break; 1506 1507 case X_RSPD_TYPE_INTR: 1508 1509 /* 1510 * Interrupts should be forwarded only to queues 1511 * that are not forwarding their interrupts. 1512 * This means service_iq can recurse but only 1 1513 * level deep. 1514 */ 1515 KASSERT(budget == 0, 1516 ("%s: budget %u, rsp_type %u", __func__, 1517 budget, rsp_type)); 1518 1519 /* 1520 * There are 1K interrupt-capable queues (qids 0 1521 * through 1023). A response type indicating a 1522 * forwarded interrupt with a qid >= 1K is an 1523 * iWARP async notification. 1524 */ 1525 if (lq >= 1024) { 1526 t4_an_handler(iq, &d->rsp); 1527 break; 1528 } 1529 1530 q = sc->sge.iqmap[lq - sc->sge.iq_start - 1531 sc->sge.iq_base]; 1532 if (atomic_cmpset_int(&q->state, IQS_IDLE, 1533 IQS_BUSY)) { 1534 if (service_iq(q, q->qsize / 16) == 0) { 1535 atomic_cmpset_int(&q->state, 1536 IQS_BUSY, IQS_IDLE); 1537 } else { 1538 STAILQ_INSERT_TAIL(&iql, q, 1539 link); 1540 } 1541 } 1542 break; 1543 1544 default: 1545 KASSERT(0, 1546 ("%s: illegal response type %d on iq %p", 1547 __func__, rsp_type, iq)); 1548 log(LOG_ERR, 1549 "%s: illegal response type %d on iq %p", 1550 device_get_nameunit(sc->dev), rsp_type, iq); 1551 break; 1552 } 1553 1554 d++; 1555 if (__predict_false(++iq->cidx == iq->sidx)) { 1556 iq->cidx = 0; 1557 iq->gen ^= F_RSPD_GEN; 1558 d = &iq->desc[0]; 1559 } 1560 if (__predict_false(++ndescs == limit)) { 1561 t4_write_reg(sc, sc->sge_gts_reg, 1562 V_CIDXINC(ndescs) | 1563 V_INGRESSQID(iq->cntxt_id) | 1564 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); 1565 ndescs = 0; 1566 1567 #if defined(INET) || defined(INET6) 1568 if (iq->flags & IQ_LRO_ENABLED && 1569 !sort_before_lro(lro) && 1570 sc->lro_timeout != 0) { 1571 tcp_lro_flush_inactive(lro, 1572 &lro_timeout); 1573 } 1574 #endif 1575 1576 if (budget) { 1577 if (iq->flags & IQ_HAS_FL) { 1578 FL_LOCK(fl); 1579 refill_fl(sc, fl, 32); 1580 FL_UNLOCK(fl); 1581 } 1582 return (EINPROGRESS); 1583 } 1584 } 1585 if (refill) { 1586 FL_LOCK(fl); 1587 refill_fl(sc, fl, 32); 1588 FL_UNLOCK(fl); 1589 fl_hw_cidx = fl->hw_cidx; 1590 } 1591 } 1592 1593 process_iql: 1594 if (STAILQ_EMPTY(&iql)) 1595 break; 1596 1597 /* 1598 * Process the head only, and send it to the back of the list if 1599 * it's still not done. 1600 */ 1601 q = STAILQ_FIRST(&iql); 1602 STAILQ_REMOVE_HEAD(&iql, link); 1603 if (service_iq(q, q->qsize / 8) == 0) 1604 atomic_cmpset_int(&q->state, IQS_BUSY, IQS_IDLE); 1605 else 1606 STAILQ_INSERT_TAIL(&iql, q, link); 1607 } 1608 1609 #if defined(INET) || defined(INET6) 1610 if (iq->flags & IQ_LRO_ENABLED) { 1611 if (ndescs > 0 && lro->lro_mbuf_count > 8) { 1612 MPASS(sort_before_lro(lro)); 1613 /* hold back one credit and don't flush LRO state */ 1614 iq->flags |= IQ_ADJ_CREDIT; 1615 ndescs--; 1616 } else { 1617 tcp_lro_flush_all(lro); 1618 } 1619 } 1620 #endif 1621 1622 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) | 1623 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params)); 1624 1625 if (iq->flags & IQ_HAS_FL) { 1626 int starved; 1627 1628 FL_LOCK(fl); 1629 starved = refill_fl(sc, fl, 64); 1630 FL_UNLOCK(fl); 1631 if (__predict_false(starved != 0)) 1632 add_fl_to_sfl(sc, fl); 1633 } 1634 1635 return (0); 1636 } 1637 1638 static inline int 1639 cl_has_metadata(struct sge_fl *fl, struct cluster_layout *cll) 1640 { 1641 int rc = fl->flags & FL_BUF_PACKING || cll->region1 > 0; 1642 1643 if (rc) 1644 MPASS(cll->region3 >= CL_METADATA_SIZE); 1645 1646 return (rc); 1647 } 1648 1649 static inline struct cluster_metadata * 1650 cl_metadata(struct adapter *sc, struct sge_fl *fl, struct cluster_layout *cll, 1651 caddr_t cl) 1652 { 1653 1654 if (cl_has_metadata(fl, cll)) { 1655 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx]; 1656 1657 return ((struct cluster_metadata *)(cl + swz->size) - 1); 1658 } 1659 return (NULL); 1660 } 1661 1662 static void 1663 rxb_free(struct mbuf *m, void *arg1, void *arg2) 1664 { 1665 uma_zone_t zone = arg1; 1666 caddr_t cl = arg2; 1667 1668 uma_zfree(zone, cl); 1669 counter_u64_add(extfree_rels, 1); 1670 } 1671 1672 /* 1673 * The mbuf returned by this function could be allocated from zone_mbuf or 1674 * constructed in spare room in the cluster. 1675 * 1676 * The mbuf carries the payload in one of these ways 1677 * a) frame inside the mbuf (mbuf from zone_mbuf) 1678 * b) m_cljset (for clusters without metadata) zone_mbuf 1679 * c) m_extaddref (cluster with metadata) inline mbuf 1680 * d) m_extaddref (cluster with metadata) zone_mbuf 1681 */ 1682 static struct mbuf * 1683 get_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset, 1684 int remaining) 1685 { 1686 struct mbuf *m; 1687 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 1688 struct cluster_layout *cll = &sd->cll; 1689 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx]; 1690 struct hw_buf_info *hwb = &sc->sge.hw_buf_info[cll->hwidx]; 1691 struct cluster_metadata *clm = cl_metadata(sc, fl, cll, sd->cl); 1692 int len, blen; 1693 caddr_t payload; 1694 1695 blen = hwb->size - fl->rx_offset; /* max possible in this buf */ 1696 len = min(remaining, blen); 1697 payload = sd->cl + cll->region1 + fl->rx_offset; 1698 if (fl->flags & FL_BUF_PACKING) { 1699 const u_int l = fr_offset + len; 1700 const u_int pad = roundup2(l, fl->buf_boundary) - l; 1701 1702 if (fl->rx_offset + len + pad < hwb->size) 1703 blen = len + pad; 1704 MPASS(fl->rx_offset + blen <= hwb->size); 1705 } else { 1706 MPASS(fl->rx_offset == 0); /* not packing */ 1707 } 1708 1709 1710 if (sc->sc_do_rxcopy && len < RX_COPY_THRESHOLD) { 1711 1712 /* 1713 * Copy payload into a freshly allocated mbuf. 1714 */ 1715 1716 m = fr_offset == 0 ? 1717 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA); 1718 if (m == NULL) 1719 return (NULL); 1720 fl->mbuf_allocated++; 1721 #ifdef T4_PKT_TIMESTAMP 1722 /* Leave room for a timestamp */ 1723 m->m_data += 8; 1724 #endif 1725 /* copy data to mbuf */ 1726 bcopy(payload, mtod(m, caddr_t), len); 1727 1728 } else if (sd->nmbuf * MSIZE < cll->region1) { 1729 1730 /* 1731 * There's spare room in the cluster for an mbuf. Create one 1732 * and associate it with the payload that's in the cluster. 1733 */ 1734 1735 MPASS(clm != NULL); 1736 m = (struct mbuf *)(sd->cl + sd->nmbuf * MSIZE); 1737 /* No bzero required */ 1738 if (m_init(m, M_NOWAIT, MT_DATA, 1739 fr_offset == 0 ? M_PKTHDR | M_NOFREE : M_NOFREE)) 1740 return (NULL); 1741 fl->mbuf_inlined++; 1742 m_extaddref(m, payload, blen, &clm->refcount, rxb_free, 1743 swz->zone, sd->cl); 1744 if (sd->nmbuf++ == 0) 1745 counter_u64_add(extfree_refs, 1); 1746 1747 } else { 1748 1749 /* 1750 * Grab an mbuf from zone_mbuf and associate it with the 1751 * payload in the cluster. 1752 */ 1753 1754 m = fr_offset == 0 ? 1755 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA); 1756 if (m == NULL) 1757 return (NULL); 1758 fl->mbuf_allocated++; 1759 if (clm != NULL) { 1760 m_extaddref(m, payload, blen, &clm->refcount, 1761 rxb_free, swz->zone, sd->cl); 1762 if (sd->nmbuf++ == 0) 1763 counter_u64_add(extfree_refs, 1); 1764 } else { 1765 m_cljset(m, sd->cl, swz->type); 1766 sd->cl = NULL; /* consumed, not a recycle candidate */ 1767 } 1768 } 1769 if (fr_offset == 0) 1770 m->m_pkthdr.len = remaining; 1771 m->m_len = len; 1772 1773 if (fl->flags & FL_BUF_PACKING) { 1774 fl->rx_offset += blen; 1775 MPASS(fl->rx_offset <= hwb->size); 1776 if (fl->rx_offset < hwb->size) 1777 return (m); /* without advancing the cidx */ 1778 } 1779 1780 if (__predict_false(++fl->cidx % 8 == 0)) { 1781 uint16_t cidx = fl->cidx / 8; 1782 1783 if (__predict_false(cidx == fl->sidx)) 1784 fl->cidx = cidx = 0; 1785 fl->hw_cidx = cidx; 1786 } 1787 fl->rx_offset = 0; 1788 1789 return (m); 1790 } 1791 1792 static struct mbuf * 1793 get_fl_payload(struct adapter *sc, struct sge_fl *fl, uint32_t len_newbuf) 1794 { 1795 struct mbuf *m0, *m, **pnext; 1796 u_int remaining; 1797 const u_int total = G_RSPD_LEN(len_newbuf); 1798 1799 if (__predict_false(fl->flags & FL_BUF_RESUME)) { 1800 M_ASSERTPKTHDR(fl->m0); 1801 MPASS(fl->m0->m_pkthdr.len == total); 1802 MPASS(fl->remaining < total); 1803 1804 m0 = fl->m0; 1805 pnext = fl->pnext; 1806 remaining = fl->remaining; 1807 fl->flags &= ~FL_BUF_RESUME; 1808 goto get_segment; 1809 } 1810 1811 if (fl->rx_offset > 0 && len_newbuf & F_RSPD_NEWBUF) { 1812 fl->rx_offset = 0; 1813 if (__predict_false(++fl->cidx % 8 == 0)) { 1814 uint16_t cidx = fl->cidx / 8; 1815 1816 if (__predict_false(cidx == fl->sidx)) 1817 fl->cidx = cidx = 0; 1818 fl->hw_cidx = cidx; 1819 } 1820 } 1821 1822 /* 1823 * Payload starts at rx_offset in the current hw buffer. Its length is 1824 * 'len' and it may span multiple hw buffers. 1825 */ 1826 1827 m0 = get_scatter_segment(sc, fl, 0, total); 1828 if (m0 == NULL) 1829 return (NULL); 1830 remaining = total - m0->m_len; 1831 pnext = &m0->m_next; 1832 while (remaining > 0) { 1833 get_segment: 1834 MPASS(fl->rx_offset == 0); 1835 m = get_scatter_segment(sc, fl, total - remaining, remaining); 1836 if (__predict_false(m == NULL)) { 1837 fl->m0 = m0; 1838 fl->pnext = pnext; 1839 fl->remaining = remaining; 1840 fl->flags |= FL_BUF_RESUME; 1841 return (NULL); 1842 } 1843 *pnext = m; 1844 pnext = &m->m_next; 1845 remaining -= m->m_len; 1846 } 1847 *pnext = NULL; 1848 1849 M_ASSERTPKTHDR(m0); 1850 return (m0); 1851 } 1852 1853 static int 1854 t4_eth_rx(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0) 1855 { 1856 struct sge_rxq *rxq = iq_to_rxq(iq); 1857 struct ifnet *ifp = rxq->ifp; 1858 struct adapter *sc = iq->adapter; 1859 const struct cpl_rx_pkt *cpl = (const void *)(rss + 1); 1860 #if defined(INET) || defined(INET6) 1861 struct lro_ctrl *lro = &rxq->lro; 1862 #endif 1863 static const int sw_hashtype[4][2] = { 1864 {M_HASHTYPE_NONE, M_HASHTYPE_NONE}, 1865 {M_HASHTYPE_RSS_IPV4, M_HASHTYPE_RSS_IPV6}, 1866 {M_HASHTYPE_RSS_TCP_IPV4, M_HASHTYPE_RSS_TCP_IPV6}, 1867 {M_HASHTYPE_RSS_UDP_IPV4, M_HASHTYPE_RSS_UDP_IPV6}, 1868 }; 1869 1870 KASSERT(m0 != NULL, ("%s: no payload with opcode %02x", __func__, 1871 rss->opcode)); 1872 1873 m0->m_pkthdr.len -= sc->params.sge.fl_pktshift; 1874 m0->m_len -= sc->params.sge.fl_pktshift; 1875 m0->m_data += sc->params.sge.fl_pktshift; 1876 1877 m0->m_pkthdr.rcvif = ifp; 1878 M_HASHTYPE_SET(m0, sw_hashtype[rss->hash_type][rss->ipv6]); 1879 m0->m_pkthdr.flowid = be32toh(rss->hash_val); 1880 1881 if (cpl->csum_calc && !(cpl->err_vec & sc->params.tp.err_vec_mask)) { 1882 if (ifp->if_capenable & IFCAP_RXCSUM && 1883 cpl->l2info & htobe32(F_RXF_IP)) { 1884 m0->m_pkthdr.csum_flags = (CSUM_IP_CHECKED | 1885 CSUM_IP_VALID | CSUM_DATA_VALID | CSUM_PSEUDO_HDR); 1886 rxq->rxcsum++; 1887 } else if (ifp->if_capenable & IFCAP_RXCSUM_IPV6 && 1888 cpl->l2info & htobe32(F_RXF_IP6)) { 1889 m0->m_pkthdr.csum_flags = (CSUM_DATA_VALID_IPV6 | 1890 CSUM_PSEUDO_HDR); 1891 rxq->rxcsum++; 1892 } 1893 1894 if (__predict_false(cpl->ip_frag)) 1895 m0->m_pkthdr.csum_data = be16toh(cpl->csum); 1896 else 1897 m0->m_pkthdr.csum_data = 0xffff; 1898 } 1899 1900 if (cpl->vlan_ex) { 1901 m0->m_pkthdr.ether_vtag = be16toh(cpl->vlan); 1902 m0->m_flags |= M_VLANTAG; 1903 rxq->vlan_extraction++; 1904 } 1905 1906 #if defined(INET) || defined(INET6) 1907 if (iq->flags & IQ_LRO_ENABLED) { 1908 if (sort_before_lro(lro)) { 1909 tcp_lro_queue_mbuf(lro, m0); 1910 return (0); /* queued for sort, then LRO */ 1911 } 1912 if (tcp_lro_rx(lro, m0, 0) == 0) 1913 return (0); /* queued for LRO */ 1914 } 1915 #endif 1916 ifp->if_input(ifp, m0); 1917 1918 return (0); 1919 } 1920 1921 /* 1922 * Must drain the wrq or make sure that someone else will. 1923 */ 1924 static void 1925 wrq_tx_drain(void *arg, int n) 1926 { 1927 struct sge_wrq *wrq = arg; 1928 struct sge_eq *eq = &wrq->eq; 1929 1930 EQ_LOCK(eq); 1931 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 1932 drain_wrq_wr_list(wrq->adapter, wrq); 1933 EQ_UNLOCK(eq); 1934 } 1935 1936 static void 1937 drain_wrq_wr_list(struct adapter *sc, struct sge_wrq *wrq) 1938 { 1939 struct sge_eq *eq = &wrq->eq; 1940 u_int available, dbdiff; /* # of hardware descriptors */ 1941 u_int n; 1942 struct wrqe *wr; 1943 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */ 1944 1945 EQ_LOCK_ASSERT_OWNED(eq); 1946 MPASS(TAILQ_EMPTY(&wrq->incomplete_wrs)); 1947 wr = STAILQ_FIRST(&wrq->wr_list); 1948 MPASS(wr != NULL); /* Must be called with something useful to do */ 1949 MPASS(eq->pidx == eq->dbidx); 1950 dbdiff = 0; 1951 1952 do { 1953 eq->cidx = read_hw_cidx(eq); 1954 if (eq->pidx == eq->cidx) 1955 available = eq->sidx - 1; 1956 else 1957 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 1958 1959 MPASS(wr->wrq == wrq); 1960 n = howmany(wr->wr_len, EQ_ESIZE); 1961 if (available < n) 1962 break; 1963 1964 dst = (void *)&eq->desc[eq->pidx]; 1965 if (__predict_true(eq->sidx - eq->pidx > n)) { 1966 /* Won't wrap, won't end exactly at the status page. */ 1967 bcopy(&wr->wr[0], dst, wr->wr_len); 1968 eq->pidx += n; 1969 } else { 1970 int first_portion = (eq->sidx - eq->pidx) * EQ_ESIZE; 1971 1972 bcopy(&wr->wr[0], dst, first_portion); 1973 if (wr->wr_len > first_portion) { 1974 bcopy(&wr->wr[first_portion], &eq->desc[0], 1975 wr->wr_len - first_portion); 1976 } 1977 eq->pidx = n - (eq->sidx - eq->pidx); 1978 } 1979 wrq->tx_wrs_copied++; 1980 1981 if (available < eq->sidx / 4 && 1982 atomic_cmpset_int(&eq->equiq, 0, 1)) { 1983 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ | 1984 F_FW_WR_EQUEQ); 1985 eq->equeqidx = eq->pidx; 1986 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 32) { 1987 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ); 1988 eq->equeqidx = eq->pidx; 1989 } 1990 1991 dbdiff += n; 1992 if (dbdiff >= 16) { 1993 ring_eq_db(sc, eq, dbdiff); 1994 dbdiff = 0; 1995 } 1996 1997 STAILQ_REMOVE_HEAD(&wrq->wr_list, link); 1998 free_wrqe(wr); 1999 MPASS(wrq->nwr_pending > 0); 2000 wrq->nwr_pending--; 2001 MPASS(wrq->ndesc_needed >= n); 2002 wrq->ndesc_needed -= n; 2003 } while ((wr = STAILQ_FIRST(&wrq->wr_list)) != NULL); 2004 2005 if (dbdiff) 2006 ring_eq_db(sc, eq, dbdiff); 2007 } 2008 2009 /* 2010 * Doesn't fail. Holds on to work requests it can't send right away. 2011 */ 2012 void 2013 t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, struct wrqe *wr) 2014 { 2015 #ifdef INVARIANTS 2016 struct sge_eq *eq = &wrq->eq; 2017 #endif 2018 2019 EQ_LOCK_ASSERT_OWNED(eq); 2020 MPASS(wr != NULL); 2021 MPASS(wr->wr_len > 0 && wr->wr_len <= SGE_MAX_WR_LEN); 2022 MPASS((wr->wr_len & 0x7) == 0); 2023 2024 STAILQ_INSERT_TAIL(&wrq->wr_list, wr, link); 2025 wrq->nwr_pending++; 2026 wrq->ndesc_needed += howmany(wr->wr_len, EQ_ESIZE); 2027 2028 if (!TAILQ_EMPTY(&wrq->incomplete_wrs)) 2029 return; /* commit_wrq_wr will drain wr_list as well. */ 2030 2031 drain_wrq_wr_list(sc, wrq); 2032 2033 /* Doorbell must have caught up to the pidx. */ 2034 MPASS(eq->pidx == eq->dbidx); 2035 } 2036 2037 void 2038 t4_update_fl_bufsize(struct ifnet *ifp) 2039 { 2040 struct vi_info *vi = ifp->if_softc; 2041 struct adapter *sc = vi->pi->adapter; 2042 struct sge_rxq *rxq; 2043 #ifdef TCP_OFFLOAD 2044 struct sge_ofld_rxq *ofld_rxq; 2045 #endif 2046 struct sge_fl *fl; 2047 int i, maxp, mtu = ifp->if_mtu; 2048 2049 maxp = mtu_to_max_payload(sc, mtu, 0); 2050 for_each_rxq(vi, i, rxq) { 2051 fl = &rxq->fl; 2052 2053 FL_LOCK(fl); 2054 find_best_refill_source(sc, fl, maxp); 2055 FL_UNLOCK(fl); 2056 } 2057 #ifdef TCP_OFFLOAD 2058 maxp = mtu_to_max_payload(sc, mtu, 1); 2059 for_each_ofld_rxq(vi, i, ofld_rxq) { 2060 fl = &ofld_rxq->fl; 2061 2062 FL_LOCK(fl); 2063 find_best_refill_source(sc, fl, maxp); 2064 FL_UNLOCK(fl); 2065 } 2066 #endif 2067 } 2068 2069 static inline int 2070 mbuf_nsegs(struct mbuf *m) 2071 { 2072 2073 M_ASSERTPKTHDR(m); 2074 KASSERT(m->m_pkthdr.l5hlen > 0, 2075 ("%s: mbuf %p missing information on # of segments.", __func__, m)); 2076 2077 return (m->m_pkthdr.l5hlen); 2078 } 2079 2080 static inline void 2081 set_mbuf_nsegs(struct mbuf *m, uint8_t nsegs) 2082 { 2083 2084 M_ASSERTPKTHDR(m); 2085 m->m_pkthdr.l5hlen = nsegs; 2086 } 2087 2088 static inline int 2089 mbuf_len16(struct mbuf *m) 2090 { 2091 int n; 2092 2093 M_ASSERTPKTHDR(m); 2094 n = m->m_pkthdr.PH_loc.eight[0]; 2095 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16); 2096 2097 return (n); 2098 } 2099 2100 static inline void 2101 set_mbuf_len16(struct mbuf *m, uint8_t len16) 2102 { 2103 2104 M_ASSERTPKTHDR(m); 2105 m->m_pkthdr.PH_loc.eight[0] = len16; 2106 } 2107 2108 static inline int 2109 needs_tso(struct mbuf *m) 2110 { 2111 2112 M_ASSERTPKTHDR(m); 2113 2114 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 2115 KASSERT(m->m_pkthdr.tso_segsz > 0, 2116 ("%s: TSO requested in mbuf %p but MSS not provided", 2117 __func__, m)); 2118 return (1); 2119 } 2120 2121 return (0); 2122 } 2123 2124 static inline int 2125 needs_l3_csum(struct mbuf *m) 2126 { 2127 2128 M_ASSERTPKTHDR(m); 2129 2130 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TSO)) 2131 return (1); 2132 return (0); 2133 } 2134 2135 static inline int 2136 needs_l4_csum(struct mbuf *m) 2137 { 2138 2139 M_ASSERTPKTHDR(m); 2140 2141 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_UDP_IPV6 | 2142 CSUM_TCP_IPV6 | CSUM_TSO)) 2143 return (1); 2144 return (0); 2145 } 2146 2147 static inline int 2148 needs_vlan_insertion(struct mbuf *m) 2149 { 2150 2151 M_ASSERTPKTHDR(m); 2152 2153 if (m->m_flags & M_VLANTAG) { 2154 KASSERT(m->m_pkthdr.ether_vtag != 0, 2155 ("%s: HWVLAN requested in mbuf %p but tag not provided", 2156 __func__, m)); 2157 return (1); 2158 } 2159 return (0); 2160 } 2161 2162 static void * 2163 m_advance(struct mbuf **pm, int *poffset, int len) 2164 { 2165 struct mbuf *m = *pm; 2166 int offset = *poffset; 2167 uintptr_t p = 0; 2168 2169 MPASS(len > 0); 2170 2171 for (;;) { 2172 if (offset + len < m->m_len) { 2173 offset += len; 2174 p = mtod(m, uintptr_t) + offset; 2175 break; 2176 } 2177 len -= m->m_len - offset; 2178 m = m->m_next; 2179 offset = 0; 2180 MPASS(m != NULL); 2181 } 2182 *poffset = offset; 2183 *pm = m; 2184 return ((void *)p); 2185 } 2186 2187 /* 2188 * Can deal with empty mbufs in the chain that have m_len = 0, but the chain 2189 * must have at least one mbuf that's not empty. 2190 */ 2191 static inline int 2192 count_mbuf_nsegs(struct mbuf *m) 2193 { 2194 vm_paddr_t lastb, next; 2195 vm_offset_t va; 2196 int len, nsegs; 2197 2198 MPASS(m != NULL); 2199 2200 nsegs = 0; 2201 lastb = 0; 2202 for (; m; m = m->m_next) { 2203 2204 len = m->m_len; 2205 if (__predict_false(len == 0)) 2206 continue; 2207 va = mtod(m, vm_offset_t); 2208 next = pmap_kextract(va); 2209 nsegs += sglist_count(m->m_data, len); 2210 if (lastb + 1 == next) 2211 nsegs--; 2212 lastb = pmap_kextract(va + len - 1); 2213 } 2214 2215 MPASS(nsegs > 0); 2216 return (nsegs); 2217 } 2218 2219 /* 2220 * Analyze the mbuf to determine its tx needs. The mbuf passed in may change: 2221 * a) caller can assume it's been freed if this function returns with an error. 2222 * b) it may get defragged up if the gather list is too long for the hardware. 2223 */ 2224 int 2225 parse_pkt(struct adapter *sc, struct mbuf **mp) 2226 { 2227 struct mbuf *m0 = *mp, *m; 2228 int rc, nsegs, defragged = 0, offset; 2229 struct ether_header *eh; 2230 void *l3hdr; 2231 #if defined(INET) || defined(INET6) 2232 struct tcphdr *tcp; 2233 #endif 2234 uint16_t eh_type; 2235 2236 M_ASSERTPKTHDR(m0); 2237 if (__predict_false(m0->m_pkthdr.len < ETHER_HDR_LEN)) { 2238 rc = EINVAL; 2239 fail: 2240 m_freem(m0); 2241 *mp = NULL; 2242 return (rc); 2243 } 2244 restart: 2245 /* 2246 * First count the number of gather list segments in the payload. 2247 * Defrag the mbuf if nsegs exceeds the hardware limit. 2248 */ 2249 M_ASSERTPKTHDR(m0); 2250 MPASS(m0->m_pkthdr.len > 0); 2251 nsegs = count_mbuf_nsegs(m0); 2252 if (nsegs > (needs_tso(m0) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS)) { 2253 if (defragged++ > 0 || (m = m_defrag(m0, M_NOWAIT)) == NULL) { 2254 rc = EFBIG; 2255 goto fail; 2256 } 2257 *mp = m0 = m; /* update caller's copy after defrag */ 2258 goto restart; 2259 } 2260 2261 if (__predict_false(nsegs > 2 && m0->m_pkthdr.len <= MHLEN)) { 2262 m0 = m_pullup(m0, m0->m_pkthdr.len); 2263 if (m0 == NULL) { 2264 /* Should have left well enough alone. */ 2265 rc = EFBIG; 2266 goto fail; 2267 } 2268 *mp = m0; /* update caller's copy after pullup */ 2269 goto restart; 2270 } 2271 set_mbuf_nsegs(m0, nsegs); 2272 if (sc->flags & IS_VF) 2273 set_mbuf_len16(m0, txpkt_vm_len16(nsegs, needs_tso(m0))); 2274 else 2275 set_mbuf_len16(m0, txpkt_len16(nsegs, needs_tso(m0))); 2276 2277 if (!needs_tso(m0) && 2278 !(sc->flags & IS_VF && (needs_l3_csum(m0) || needs_l4_csum(m0)))) 2279 return (0); 2280 2281 m = m0; 2282 eh = mtod(m, struct ether_header *); 2283 eh_type = ntohs(eh->ether_type); 2284 if (eh_type == ETHERTYPE_VLAN) { 2285 struct ether_vlan_header *evh = (void *)eh; 2286 2287 eh_type = ntohs(evh->evl_proto); 2288 m0->m_pkthdr.l2hlen = sizeof(*evh); 2289 } else 2290 m0->m_pkthdr.l2hlen = sizeof(*eh); 2291 2292 offset = 0; 2293 l3hdr = m_advance(&m, &offset, m0->m_pkthdr.l2hlen); 2294 2295 switch (eh_type) { 2296 #ifdef INET6 2297 case ETHERTYPE_IPV6: 2298 { 2299 struct ip6_hdr *ip6 = l3hdr; 2300 2301 MPASS(!needs_tso(m0) || ip6->ip6_nxt == IPPROTO_TCP); 2302 2303 m0->m_pkthdr.l3hlen = sizeof(*ip6); 2304 break; 2305 } 2306 #endif 2307 #ifdef INET 2308 case ETHERTYPE_IP: 2309 { 2310 struct ip *ip = l3hdr; 2311 2312 m0->m_pkthdr.l3hlen = ip->ip_hl * 4; 2313 break; 2314 } 2315 #endif 2316 default: 2317 panic("%s: ethertype 0x%04x unknown. if_cxgbe must be compiled" 2318 " with the same INET/INET6 options as the kernel.", 2319 __func__, eh_type); 2320 } 2321 2322 #if defined(INET) || defined(INET6) 2323 if (needs_tso(m0)) { 2324 tcp = m_advance(&m, &offset, m0->m_pkthdr.l3hlen); 2325 m0->m_pkthdr.l4hlen = tcp->th_off * 4; 2326 } 2327 #endif 2328 MPASS(m0 == *mp); 2329 return (0); 2330 } 2331 2332 void * 2333 start_wrq_wr(struct sge_wrq *wrq, int len16, struct wrq_cookie *cookie) 2334 { 2335 struct sge_eq *eq = &wrq->eq; 2336 struct adapter *sc = wrq->adapter; 2337 int ndesc, available; 2338 struct wrqe *wr; 2339 void *w; 2340 2341 MPASS(len16 > 0); 2342 ndesc = howmany(len16, EQ_ESIZE / 16); 2343 MPASS(ndesc > 0 && ndesc <= SGE_MAX_WR_NDESC); 2344 2345 EQ_LOCK(eq); 2346 2347 if (!STAILQ_EMPTY(&wrq->wr_list)) 2348 drain_wrq_wr_list(sc, wrq); 2349 2350 if (!STAILQ_EMPTY(&wrq->wr_list)) { 2351 slowpath: 2352 EQ_UNLOCK(eq); 2353 wr = alloc_wrqe(len16 * 16, wrq); 2354 if (__predict_false(wr == NULL)) 2355 return (NULL); 2356 cookie->pidx = -1; 2357 cookie->ndesc = ndesc; 2358 return (&wr->wr); 2359 } 2360 2361 eq->cidx = read_hw_cidx(eq); 2362 if (eq->pidx == eq->cidx) 2363 available = eq->sidx - 1; 2364 else 2365 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2366 if (available < ndesc) 2367 goto slowpath; 2368 2369 cookie->pidx = eq->pidx; 2370 cookie->ndesc = ndesc; 2371 TAILQ_INSERT_TAIL(&wrq->incomplete_wrs, cookie, link); 2372 2373 w = &eq->desc[eq->pidx]; 2374 IDXINCR(eq->pidx, ndesc, eq->sidx); 2375 if (__predict_false(cookie->pidx + ndesc > eq->sidx)) { 2376 w = &wrq->ss[0]; 2377 wrq->ss_pidx = cookie->pidx; 2378 wrq->ss_len = len16 * 16; 2379 } 2380 2381 EQ_UNLOCK(eq); 2382 2383 return (w); 2384 } 2385 2386 void 2387 commit_wrq_wr(struct sge_wrq *wrq, void *w, struct wrq_cookie *cookie) 2388 { 2389 struct sge_eq *eq = &wrq->eq; 2390 struct adapter *sc = wrq->adapter; 2391 int ndesc, pidx; 2392 struct wrq_cookie *prev, *next; 2393 2394 if (cookie->pidx == -1) { 2395 struct wrqe *wr = __containerof(w, struct wrqe, wr); 2396 2397 t4_wrq_tx(sc, wr); 2398 return; 2399 } 2400 2401 ndesc = cookie->ndesc; /* Can be more than SGE_MAX_WR_NDESC here. */ 2402 pidx = cookie->pidx; 2403 MPASS(pidx >= 0 && pidx < eq->sidx); 2404 if (__predict_false(w == &wrq->ss[0])) { 2405 int n = (eq->sidx - wrq->ss_pidx) * EQ_ESIZE; 2406 2407 MPASS(wrq->ss_len > n); /* WR had better wrap around. */ 2408 bcopy(&wrq->ss[0], &eq->desc[wrq->ss_pidx], n); 2409 bcopy(&wrq->ss[n], &eq->desc[0], wrq->ss_len - n); 2410 wrq->tx_wrs_ss++; 2411 } else 2412 wrq->tx_wrs_direct++; 2413 2414 EQ_LOCK(eq); 2415 prev = TAILQ_PREV(cookie, wrq_incomplete_wrs, link); 2416 next = TAILQ_NEXT(cookie, link); 2417 if (prev == NULL) { 2418 MPASS(pidx == eq->dbidx); 2419 if (next == NULL || ndesc >= 16) 2420 ring_eq_db(wrq->adapter, eq, ndesc); 2421 else { 2422 MPASS(IDXDIFF(next->pidx, pidx, eq->sidx) == ndesc); 2423 next->pidx = pidx; 2424 next->ndesc += ndesc; 2425 } 2426 } else { 2427 MPASS(IDXDIFF(pidx, prev->pidx, eq->sidx) == prev->ndesc); 2428 prev->ndesc += ndesc; 2429 } 2430 TAILQ_REMOVE(&wrq->incomplete_wrs, cookie, link); 2431 2432 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 2433 drain_wrq_wr_list(sc, wrq); 2434 2435 #ifdef INVARIANTS 2436 if (TAILQ_EMPTY(&wrq->incomplete_wrs)) { 2437 /* Doorbell must have caught up to the pidx. */ 2438 MPASS(wrq->eq.pidx == wrq->eq.dbidx); 2439 } 2440 #endif 2441 EQ_UNLOCK(eq); 2442 } 2443 2444 static u_int 2445 can_resume_eth_tx(struct mp_ring *r) 2446 { 2447 struct sge_eq *eq = r->cookie; 2448 2449 return (total_available_tx_desc(eq) > eq->sidx / 8); 2450 } 2451 2452 static inline int 2453 cannot_use_txpkts(struct mbuf *m) 2454 { 2455 /* maybe put a GL limit too, to avoid silliness? */ 2456 2457 return (needs_tso(m)); 2458 } 2459 2460 static inline int 2461 discard_tx(struct sge_eq *eq) 2462 { 2463 2464 return ((eq->flags & (EQ_ENABLED | EQ_QFLUSH)) != EQ_ENABLED); 2465 } 2466 2467 /* 2468 * r->items[cidx] to r->items[pidx], with a wraparound at r->size, are ready to 2469 * be consumed. Return the actual number consumed. 0 indicates a stall. 2470 */ 2471 static u_int 2472 eth_tx(struct mp_ring *r, u_int cidx, u_int pidx) 2473 { 2474 struct sge_txq *txq = r->cookie; 2475 struct sge_eq *eq = &txq->eq; 2476 struct ifnet *ifp = txq->ifp; 2477 struct vi_info *vi = ifp->if_softc; 2478 struct port_info *pi = vi->pi; 2479 struct adapter *sc = pi->adapter; 2480 u_int total, remaining; /* # of packets */ 2481 u_int available, dbdiff; /* # of hardware descriptors */ 2482 u_int n, next_cidx; 2483 struct mbuf *m0, *tail; 2484 struct txpkts txp; 2485 struct fw_eth_tx_pkts_wr *wr; /* any fw WR struct will do */ 2486 2487 remaining = IDXDIFF(pidx, cidx, r->size); 2488 MPASS(remaining > 0); /* Must not be called without work to do. */ 2489 total = 0; 2490 2491 TXQ_LOCK(txq); 2492 if (__predict_false(discard_tx(eq))) { 2493 while (cidx != pidx) { 2494 m0 = r->items[cidx]; 2495 m_freem(m0); 2496 if (++cidx == r->size) 2497 cidx = 0; 2498 } 2499 reclaim_tx_descs(txq, 2048); 2500 total = remaining; 2501 goto done; 2502 } 2503 2504 /* How many hardware descriptors do we have readily available. */ 2505 if (eq->pidx == eq->cidx) 2506 available = eq->sidx - 1; 2507 else 2508 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2509 dbdiff = IDXDIFF(eq->pidx, eq->dbidx, eq->sidx); 2510 2511 while (remaining > 0) { 2512 2513 m0 = r->items[cidx]; 2514 M_ASSERTPKTHDR(m0); 2515 MPASS(m0->m_nextpkt == NULL); 2516 2517 if (available < SGE_MAX_WR_NDESC) { 2518 available += reclaim_tx_descs(txq, 64); 2519 if (available < howmany(mbuf_len16(m0), EQ_ESIZE / 16)) 2520 break; /* out of descriptors */ 2521 } 2522 2523 next_cidx = cidx + 1; 2524 if (__predict_false(next_cidx == r->size)) 2525 next_cidx = 0; 2526 2527 wr = (void *)&eq->desc[eq->pidx]; 2528 if (sc->flags & IS_VF) { 2529 total++; 2530 remaining--; 2531 ETHER_BPF_MTAP(ifp, m0); 2532 n = write_txpkt_vm_wr(sc, txq, (void *)wr, m0, 2533 available); 2534 } else if (remaining > 1 && 2535 try_txpkts(m0, r->items[next_cidx], &txp, available) == 0) { 2536 2537 /* pkts at cidx, next_cidx should both be in txp. */ 2538 MPASS(txp.npkt == 2); 2539 tail = r->items[next_cidx]; 2540 MPASS(tail->m_nextpkt == NULL); 2541 ETHER_BPF_MTAP(ifp, m0); 2542 ETHER_BPF_MTAP(ifp, tail); 2543 m0->m_nextpkt = tail; 2544 2545 if (__predict_false(++next_cidx == r->size)) 2546 next_cidx = 0; 2547 2548 while (next_cidx != pidx) { 2549 if (add_to_txpkts(r->items[next_cidx], &txp, 2550 available) != 0) 2551 break; 2552 tail->m_nextpkt = r->items[next_cidx]; 2553 tail = tail->m_nextpkt; 2554 ETHER_BPF_MTAP(ifp, tail); 2555 if (__predict_false(++next_cidx == r->size)) 2556 next_cidx = 0; 2557 } 2558 2559 n = write_txpkts_wr(txq, wr, m0, &txp, available); 2560 total += txp.npkt; 2561 remaining -= txp.npkt; 2562 } else { 2563 total++; 2564 remaining--; 2565 ETHER_BPF_MTAP(ifp, m0); 2566 n = write_txpkt_wr(txq, (void *)wr, m0, available); 2567 } 2568 MPASS(n >= 1 && n <= available && n <= SGE_MAX_WR_NDESC); 2569 2570 available -= n; 2571 dbdiff += n; 2572 IDXINCR(eq->pidx, n, eq->sidx); 2573 2574 if (total_available_tx_desc(eq) < eq->sidx / 4 && 2575 atomic_cmpset_int(&eq->equiq, 0, 1)) { 2576 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ | 2577 F_FW_WR_EQUEQ); 2578 eq->equeqidx = eq->pidx; 2579 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 32) { 2580 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ); 2581 eq->equeqidx = eq->pidx; 2582 } 2583 2584 if (dbdiff >= 16 && remaining >= 4) { 2585 ring_eq_db(sc, eq, dbdiff); 2586 available += reclaim_tx_descs(txq, 4 * dbdiff); 2587 dbdiff = 0; 2588 } 2589 2590 cidx = next_cidx; 2591 } 2592 if (dbdiff != 0) { 2593 ring_eq_db(sc, eq, dbdiff); 2594 reclaim_tx_descs(txq, 32); 2595 } 2596 done: 2597 TXQ_UNLOCK(txq); 2598 2599 return (total); 2600 } 2601 2602 static inline void 2603 init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int pktc_idx, 2604 int qsize) 2605 { 2606 2607 KASSERT(tmr_idx >= 0 && tmr_idx < SGE_NTIMERS, 2608 ("%s: bad tmr_idx %d", __func__, tmr_idx)); 2609 KASSERT(pktc_idx < SGE_NCOUNTERS, /* -ve is ok, means don't use */ 2610 ("%s: bad pktc_idx %d", __func__, pktc_idx)); 2611 2612 iq->flags = 0; 2613 iq->adapter = sc; 2614 iq->intr_params = V_QINTR_TIMER_IDX(tmr_idx); 2615 iq->intr_pktc_idx = SGE_NCOUNTERS - 1; 2616 if (pktc_idx >= 0) { 2617 iq->intr_params |= F_QINTR_CNT_EN; 2618 iq->intr_pktc_idx = pktc_idx; 2619 } 2620 iq->qsize = roundup2(qsize, 16); /* See FW_IQ_CMD/iqsize */ 2621 iq->sidx = iq->qsize - sc->params.sge.spg_len / IQ_ESIZE; 2622 } 2623 2624 static inline void 2625 init_fl(struct adapter *sc, struct sge_fl *fl, int qsize, int maxp, char *name) 2626 { 2627 2628 fl->qsize = qsize; 2629 fl->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE; 2630 strlcpy(fl->lockname, name, sizeof(fl->lockname)); 2631 if (sc->flags & BUF_PACKING_OK && 2632 ((!is_t4(sc) && buffer_packing) || /* T5+: enabled unless 0 */ 2633 (is_t4(sc) && buffer_packing == 1)))/* T4: disabled unless 1 */ 2634 fl->flags |= FL_BUF_PACKING; 2635 find_best_refill_source(sc, fl, maxp); 2636 find_safe_refill_source(sc, fl); 2637 } 2638 2639 static inline void 2640 init_eq(struct adapter *sc, struct sge_eq *eq, int eqtype, int qsize, 2641 uint8_t tx_chan, uint16_t iqid, char *name) 2642 { 2643 KASSERT(eqtype <= EQ_TYPEMASK, ("%s: bad qtype %d", __func__, eqtype)); 2644 2645 eq->flags = eqtype & EQ_TYPEMASK; 2646 eq->tx_chan = tx_chan; 2647 eq->iqid = iqid; 2648 eq->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE; 2649 strlcpy(eq->lockname, name, sizeof(eq->lockname)); 2650 } 2651 2652 static int 2653 alloc_ring(struct adapter *sc, size_t len, bus_dma_tag_t *tag, 2654 bus_dmamap_t *map, bus_addr_t *pa, void **va) 2655 { 2656 int rc; 2657 2658 rc = bus_dma_tag_create(sc->dmat, 512, 0, BUS_SPACE_MAXADDR, 2659 BUS_SPACE_MAXADDR, NULL, NULL, len, 1, len, 0, NULL, NULL, tag); 2660 if (rc != 0) { 2661 device_printf(sc->dev, "cannot allocate DMA tag: %d\n", rc); 2662 goto done; 2663 } 2664 2665 rc = bus_dmamem_alloc(*tag, va, 2666 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, map); 2667 if (rc != 0) { 2668 device_printf(sc->dev, "cannot allocate DMA memory: %d\n", rc); 2669 goto done; 2670 } 2671 2672 rc = bus_dmamap_load(*tag, *map, *va, len, oneseg_dma_callback, pa, 0); 2673 if (rc != 0) { 2674 device_printf(sc->dev, "cannot load DMA map: %d\n", rc); 2675 goto done; 2676 } 2677 done: 2678 if (rc) 2679 free_ring(sc, *tag, *map, *pa, *va); 2680 2681 return (rc); 2682 } 2683 2684 static int 2685 free_ring(struct adapter *sc, bus_dma_tag_t tag, bus_dmamap_t map, 2686 bus_addr_t pa, void *va) 2687 { 2688 if (pa) 2689 bus_dmamap_unload(tag, map); 2690 if (va) 2691 bus_dmamem_free(tag, va, map); 2692 if (tag) 2693 bus_dma_tag_destroy(tag); 2694 2695 return (0); 2696 } 2697 2698 /* 2699 * Allocates the ring for an ingress queue and an optional freelist. If the 2700 * freelist is specified it will be allocated and then associated with the 2701 * ingress queue. 2702 * 2703 * Returns errno on failure. Resources allocated up to that point may still be 2704 * allocated. Caller is responsible for cleanup in case this function fails. 2705 * 2706 * If the ingress queue will take interrupts directly (iq->flags & IQ_INTR) then 2707 * the intr_idx specifies the vector, starting from 0. Otherwise it specifies 2708 * the abs_id of the ingress queue to which its interrupts should be forwarded. 2709 */ 2710 static int 2711 alloc_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl, 2712 int intr_idx, int cong) 2713 { 2714 int rc, i, cntxt_id; 2715 size_t len; 2716 struct fw_iq_cmd c; 2717 struct port_info *pi = vi->pi; 2718 struct adapter *sc = iq->adapter; 2719 struct sge_params *sp = &sc->params.sge; 2720 __be32 v = 0; 2721 2722 len = iq->qsize * IQ_ESIZE; 2723 rc = alloc_ring(sc, len, &iq->desc_tag, &iq->desc_map, &iq->ba, 2724 (void **)&iq->desc); 2725 if (rc != 0) 2726 return (rc); 2727 2728 bzero(&c, sizeof(c)); 2729 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 2730 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) | 2731 V_FW_IQ_CMD_VFN(0)); 2732 2733 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART | 2734 FW_LEN16(c)); 2735 2736 /* Special handling for firmware event queue */ 2737 if (iq == &sc->sge.fwq) 2738 v |= F_FW_IQ_CMD_IQASYNCH; 2739 2740 if (iq->flags & IQ_INTR) { 2741 KASSERT(intr_idx < sc->intr_count, 2742 ("%s: invalid direct intr_idx %d", __func__, intr_idx)); 2743 } else 2744 v |= F_FW_IQ_CMD_IQANDST; 2745 v |= V_FW_IQ_CMD_IQANDSTINDEX(intr_idx); 2746 2747 c.type_to_iqandstindex = htobe32(v | 2748 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) | 2749 V_FW_IQ_CMD_VIID(vi->viid) | 2750 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT)); 2751 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->tx_chan) | 2752 F_FW_IQ_CMD_IQGTSMODE | 2753 V_FW_IQ_CMD_IQINTCNTTHRESH(iq->intr_pktc_idx) | 2754 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4)); 2755 c.iqsize = htobe16(iq->qsize); 2756 c.iqaddr = htobe64(iq->ba); 2757 if (cong >= 0) 2758 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN); 2759 2760 if (fl) { 2761 mtx_init(&fl->fl_lock, fl->lockname, NULL, MTX_DEF); 2762 2763 len = fl->qsize * EQ_ESIZE; 2764 rc = alloc_ring(sc, len, &fl->desc_tag, &fl->desc_map, 2765 &fl->ba, (void **)&fl->desc); 2766 if (rc) 2767 return (rc); 2768 2769 /* Allocate space for one software descriptor per buffer. */ 2770 rc = alloc_fl_sdesc(fl); 2771 if (rc != 0) { 2772 device_printf(sc->dev, 2773 "failed to setup fl software descriptors: %d\n", 2774 rc); 2775 return (rc); 2776 } 2777 2778 if (fl->flags & FL_BUF_PACKING) { 2779 fl->lowat = roundup2(sp->fl_starve_threshold2, 8); 2780 fl->buf_boundary = sp->pack_boundary; 2781 } else { 2782 fl->lowat = roundup2(sp->fl_starve_threshold, 8); 2783 fl->buf_boundary = 16; 2784 } 2785 if (fl_pad && fl->buf_boundary < sp->pad_boundary) 2786 fl->buf_boundary = sp->pad_boundary; 2787 2788 c.iqns_to_fl0congen |= 2789 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) | 2790 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO | 2791 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) | 2792 (fl->flags & FL_BUF_PACKING ? F_FW_IQ_CMD_FL0PACKEN : 2793 0)); 2794 if (cong >= 0) { 2795 c.iqns_to_fl0congen |= 2796 htobe32(V_FW_IQ_CMD_FL0CNGCHMAP(cong) | 2797 F_FW_IQ_CMD_FL0CONGCIF | 2798 F_FW_IQ_CMD_FL0CONGEN); 2799 } 2800 c.fl0dcaen_to_fl0cidxfthresh = 2801 htobe16(V_FW_IQ_CMD_FL0FBMIN(chip_id(sc) <= CHELSIO_T5 ? 2802 X_FETCHBURSTMIN_128B : X_FETCHBURSTMIN_64B) | 2803 V_FW_IQ_CMD_FL0FBMAX(chip_id(sc) <= CHELSIO_T5 ? 2804 X_FETCHBURSTMAX_512B : X_FETCHBURSTMAX_256B)); 2805 c.fl0size = htobe16(fl->qsize); 2806 c.fl0addr = htobe64(fl->ba); 2807 } 2808 2809 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 2810 if (rc != 0) { 2811 device_printf(sc->dev, 2812 "failed to create ingress queue: %d\n", rc); 2813 return (rc); 2814 } 2815 2816 iq->cidx = 0; 2817 iq->gen = F_RSPD_GEN; 2818 iq->intr_next = iq->intr_params; 2819 iq->cntxt_id = be16toh(c.iqid); 2820 iq->abs_id = be16toh(c.physiqid); 2821 iq->flags |= IQ_ALLOCATED; 2822 2823 cntxt_id = iq->cntxt_id - sc->sge.iq_start; 2824 if (cntxt_id >= sc->sge.niq) { 2825 panic ("%s: iq->cntxt_id (%d) more than the max (%d)", __func__, 2826 cntxt_id, sc->sge.niq - 1); 2827 } 2828 sc->sge.iqmap[cntxt_id] = iq; 2829 2830 if (fl) { 2831 u_int qid; 2832 2833 iq->flags |= IQ_HAS_FL; 2834 fl->cntxt_id = be16toh(c.fl0id); 2835 fl->pidx = fl->cidx = 0; 2836 2837 cntxt_id = fl->cntxt_id - sc->sge.eq_start; 2838 if (cntxt_id >= sc->sge.neq) { 2839 panic("%s: fl->cntxt_id (%d) more than the max (%d)", 2840 __func__, cntxt_id, sc->sge.neq - 1); 2841 } 2842 sc->sge.eqmap[cntxt_id] = (void *)fl; 2843 2844 qid = fl->cntxt_id; 2845 if (isset(&sc->doorbells, DOORBELL_UDB)) { 2846 uint32_t s_qpp = sc->params.sge.eq_s_qpp; 2847 uint32_t mask = (1 << s_qpp) - 1; 2848 volatile uint8_t *udb; 2849 2850 udb = sc->udbs_base + UDBS_DB_OFFSET; 2851 udb += (qid >> s_qpp) << PAGE_SHIFT; 2852 qid &= mask; 2853 if (qid < PAGE_SIZE / UDBS_SEG_SIZE) { 2854 udb += qid << UDBS_SEG_SHIFT; 2855 qid = 0; 2856 } 2857 fl->udb = (volatile void *)udb; 2858 } 2859 fl->dbval = V_QID(qid) | sc->chip_params->sge_fl_db; 2860 2861 FL_LOCK(fl); 2862 /* Enough to make sure the SGE doesn't think it's starved */ 2863 refill_fl(sc, fl, fl->lowat); 2864 FL_UNLOCK(fl); 2865 } 2866 2867 if (chip_id(sc) >= CHELSIO_T5 && !(sc->flags & IS_VF) && cong >= 0) { 2868 uint32_t param, val; 2869 2870 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 2871 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) | 2872 V_FW_PARAMS_PARAM_YZ(iq->cntxt_id); 2873 if (cong == 0) 2874 val = 1 << 19; 2875 else { 2876 val = 2 << 19; 2877 for (i = 0; i < 4; i++) { 2878 if (cong & (1 << i)) 2879 val |= 1 << (i << 2); 2880 } 2881 } 2882 2883 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 2884 if (rc != 0) { 2885 /* report error but carry on */ 2886 device_printf(sc->dev, 2887 "failed to set congestion manager context for " 2888 "ingress queue %d: %d\n", iq->cntxt_id, rc); 2889 } 2890 } 2891 2892 /* Enable IQ interrupts */ 2893 atomic_store_rel_int(&iq->state, IQS_IDLE); 2894 t4_write_reg(sc, sc->sge_gts_reg, V_SEINTARM(iq->intr_params) | 2895 V_INGRESSQID(iq->cntxt_id)); 2896 2897 return (0); 2898 } 2899 2900 static int 2901 free_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl) 2902 { 2903 int rc; 2904 struct adapter *sc = iq->adapter; 2905 device_t dev; 2906 2907 if (sc == NULL) 2908 return (0); /* nothing to do */ 2909 2910 dev = vi ? vi->dev : sc->dev; 2911 2912 if (iq->flags & IQ_ALLOCATED) { 2913 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0, 2914 FW_IQ_TYPE_FL_INT_CAP, iq->cntxt_id, 2915 fl ? fl->cntxt_id : 0xffff, 0xffff); 2916 if (rc != 0) { 2917 device_printf(dev, 2918 "failed to free queue %p: %d\n", iq, rc); 2919 return (rc); 2920 } 2921 iq->flags &= ~IQ_ALLOCATED; 2922 } 2923 2924 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, iq->desc); 2925 2926 bzero(iq, sizeof(*iq)); 2927 2928 if (fl) { 2929 free_ring(sc, fl->desc_tag, fl->desc_map, fl->ba, 2930 fl->desc); 2931 2932 if (fl->sdesc) 2933 free_fl_sdesc(sc, fl); 2934 2935 if (mtx_initialized(&fl->fl_lock)) 2936 mtx_destroy(&fl->fl_lock); 2937 2938 bzero(fl, sizeof(*fl)); 2939 } 2940 2941 return (0); 2942 } 2943 2944 static void 2945 add_fl_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx, 2946 struct sysctl_oid *oid, struct sge_fl *fl) 2947 { 2948 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 2949 2950 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL, 2951 "freelist"); 2952 children = SYSCTL_CHILDREN(oid); 2953 2954 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, 2955 &fl->ba, "bus address of descriptor ring"); 2956 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 2957 fl->sidx * EQ_ESIZE + sc->params.sge.spg_len, 2958 "desc ring size in bytes"); 2959 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 2960 CTLTYPE_INT | CTLFLAG_RD, &fl->cntxt_id, 0, sysctl_uint16, "I", 2961 "SGE context id of the freelist"); 2962 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "padding", CTLFLAG_RD, NULL, 2963 fl_pad ? 1 : 0, "padding enabled"); 2964 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "packing", CTLFLAG_RD, NULL, 2965 fl->flags & FL_BUF_PACKING ? 1 : 0, "packing enabled"); 2966 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &fl->cidx, 2967 0, "consumer index"); 2968 if (fl->flags & FL_BUF_PACKING) { 2969 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rx_offset", 2970 CTLFLAG_RD, &fl->rx_offset, 0, "packing rx offset"); 2971 } 2972 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &fl->pidx, 2973 0, "producer index"); 2974 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_allocated", 2975 CTLFLAG_RD, &fl->mbuf_allocated, "# of mbuf allocated"); 2976 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_inlined", 2977 CTLFLAG_RD, &fl->mbuf_inlined, "# of mbuf inlined in clusters"); 2978 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_allocated", 2979 CTLFLAG_RD, &fl->cl_allocated, "# of clusters allocated"); 2980 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_recycled", 2981 CTLFLAG_RD, &fl->cl_recycled, "# of clusters recycled"); 2982 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_fast_recycled", 2983 CTLFLAG_RD, &fl->cl_fast_recycled, "# of clusters recycled (fast)"); 2984 } 2985 2986 static int 2987 alloc_fwq(struct adapter *sc) 2988 { 2989 int rc, intr_idx; 2990 struct sge_iq *fwq = &sc->sge.fwq; 2991 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev); 2992 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 2993 2994 init_iq(fwq, sc, 0, 0, FW_IQ_QSIZE); 2995 fwq->flags |= IQ_INTR; /* always */ 2996 if (sc->flags & IS_VF) 2997 intr_idx = 0; 2998 else { 2999 intr_idx = sc->intr_count > 1 ? 1 : 0; 3000 fwq->set_tcb_rpl = t4_filter_rpl; 3001 fwq->l2t_write_rpl = do_l2t_write_rpl; 3002 } 3003 rc = alloc_iq_fl(&sc->port[0]->vi[0], fwq, NULL, intr_idx, -1); 3004 if (rc != 0) { 3005 device_printf(sc->dev, 3006 "failed to create firmware event queue: %d\n", rc); 3007 return (rc); 3008 } 3009 3010 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "fwq", CTLFLAG_RD, 3011 NULL, "firmware event queue"); 3012 children = SYSCTL_CHILDREN(oid); 3013 3014 SYSCTL_ADD_UAUTO(&sc->ctx, children, OID_AUTO, "ba", CTLFLAG_RD, 3015 &fwq->ba, "bus address of descriptor ring"); 3016 SYSCTL_ADD_INT(&sc->ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3017 fwq->qsize * IQ_ESIZE, "descriptor ring size in bytes"); 3018 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "abs_id", 3019 CTLTYPE_INT | CTLFLAG_RD, &fwq->abs_id, 0, sysctl_uint16, "I", 3020 "absolute id of the queue"); 3021 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "cntxt_id", 3022 CTLTYPE_INT | CTLFLAG_RD, &fwq->cntxt_id, 0, sysctl_uint16, "I", 3023 "SGE context id of the queue"); 3024 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "cidx", 3025 CTLTYPE_INT | CTLFLAG_RD, &fwq->cidx, 0, sysctl_uint16, "I", 3026 "consumer index"); 3027 3028 return (0); 3029 } 3030 3031 static int 3032 free_fwq(struct adapter *sc) 3033 { 3034 return free_iq_fl(NULL, &sc->sge.fwq, NULL); 3035 } 3036 3037 static int 3038 alloc_mgmtq(struct adapter *sc) 3039 { 3040 int rc; 3041 struct sge_wrq *mgmtq = &sc->sge.mgmtq; 3042 char name[16]; 3043 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev); 3044 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3045 3046 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "mgmtq", CTLFLAG_RD, 3047 NULL, "management queue"); 3048 3049 snprintf(name, sizeof(name), "%s mgmtq", device_get_nameunit(sc->dev)); 3050 init_eq(sc, &mgmtq->eq, EQ_CTRL, CTRL_EQ_QSIZE, sc->port[0]->tx_chan, 3051 sc->sge.fwq.cntxt_id, name); 3052 rc = alloc_wrq(sc, NULL, mgmtq, oid); 3053 if (rc != 0) { 3054 device_printf(sc->dev, 3055 "failed to create management queue: %d\n", rc); 3056 return (rc); 3057 } 3058 3059 return (0); 3060 } 3061 3062 static int 3063 free_mgmtq(struct adapter *sc) 3064 { 3065 3066 return free_wrq(sc, &sc->sge.mgmtq); 3067 } 3068 3069 int 3070 tnl_cong(struct port_info *pi, int drop) 3071 { 3072 3073 if (drop == -1) 3074 return (-1); 3075 else if (drop == 1) 3076 return (0); 3077 else 3078 return (pi->rx_chan_map); 3079 } 3080 3081 static int 3082 alloc_rxq(struct vi_info *vi, struct sge_rxq *rxq, int intr_idx, int idx, 3083 struct sysctl_oid *oid) 3084 { 3085 int rc; 3086 struct adapter *sc = vi->pi->adapter; 3087 struct sysctl_oid_list *children; 3088 char name[16]; 3089 3090 rc = alloc_iq_fl(vi, &rxq->iq, &rxq->fl, intr_idx, 3091 tnl_cong(vi->pi, cong_drop)); 3092 if (rc != 0) 3093 return (rc); 3094 3095 if (idx == 0) 3096 sc->sge.iq_base = rxq->iq.abs_id - rxq->iq.cntxt_id; 3097 else 3098 KASSERT(rxq->iq.cntxt_id + sc->sge.iq_base == rxq->iq.abs_id, 3099 ("iq_base mismatch")); 3100 KASSERT(sc->sge.iq_base == 0 || sc->flags & IS_VF, 3101 ("PF with non-zero iq_base")); 3102 3103 /* 3104 * The freelist is just barely above the starvation threshold right now, 3105 * fill it up a bit more. 3106 */ 3107 FL_LOCK(&rxq->fl); 3108 refill_fl(sc, &rxq->fl, 128); 3109 FL_UNLOCK(&rxq->fl); 3110 3111 #if defined(INET) || defined(INET6) 3112 rc = tcp_lro_init_args(&rxq->lro, vi->ifp, lro_entries, lro_mbufs); 3113 if (rc != 0) 3114 return (rc); 3115 MPASS(rxq->lro.ifp == vi->ifp); /* also indicates LRO init'ed */ 3116 3117 if (vi->ifp->if_capenable & IFCAP_LRO) 3118 rxq->iq.flags |= IQ_LRO_ENABLED; 3119 #endif 3120 rxq->ifp = vi->ifp; 3121 3122 children = SYSCTL_CHILDREN(oid); 3123 3124 snprintf(name, sizeof(name), "%d", idx); 3125 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 3126 NULL, "rx queue"); 3127 children = SYSCTL_CHILDREN(oid); 3128 3129 SYSCTL_ADD_UAUTO(&vi->ctx, children, OID_AUTO, "ba", CTLFLAG_RD, 3130 &rxq->iq.ba, "bus address of descriptor ring"); 3131 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3132 rxq->iq.qsize * IQ_ESIZE, "descriptor ring size in bytes"); 3133 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "abs_id", 3134 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.abs_id, 0, sysctl_uint16, "I", 3135 "absolute id of the queue"); 3136 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cntxt_id", 3137 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.cntxt_id, 0, sysctl_uint16, "I", 3138 "SGE context id of the queue"); 3139 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx", 3140 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.cidx, 0, sysctl_uint16, "I", 3141 "consumer index"); 3142 #if defined(INET) || defined(INET6) 3143 SYSCTL_ADD_U64(&vi->ctx, children, OID_AUTO, "lro_queued", CTLFLAG_RD, 3144 &rxq->lro.lro_queued, 0, NULL); 3145 SYSCTL_ADD_U64(&vi->ctx, children, OID_AUTO, "lro_flushed", CTLFLAG_RD, 3146 &rxq->lro.lro_flushed, 0, NULL); 3147 #endif 3148 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "rxcsum", CTLFLAG_RD, 3149 &rxq->rxcsum, "# of times hardware assisted with checksum"); 3150 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_extraction", 3151 CTLFLAG_RD, &rxq->vlan_extraction, 3152 "# of times hardware extracted 802.1Q tag"); 3153 3154 add_fl_sysctls(sc, &vi->ctx, oid, &rxq->fl); 3155 3156 return (rc); 3157 } 3158 3159 static int 3160 free_rxq(struct vi_info *vi, struct sge_rxq *rxq) 3161 { 3162 int rc; 3163 3164 #if defined(INET) || defined(INET6) 3165 if (rxq->lro.ifp) { 3166 tcp_lro_free(&rxq->lro); 3167 rxq->lro.ifp = NULL; 3168 } 3169 #endif 3170 3171 rc = free_iq_fl(vi, &rxq->iq, &rxq->fl); 3172 if (rc == 0) 3173 bzero(rxq, sizeof(*rxq)); 3174 3175 return (rc); 3176 } 3177 3178 #ifdef TCP_OFFLOAD 3179 static int 3180 alloc_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq, 3181 int intr_idx, int idx, struct sysctl_oid *oid) 3182 { 3183 struct port_info *pi = vi->pi; 3184 int rc; 3185 struct sysctl_oid_list *children; 3186 char name[16]; 3187 3188 rc = alloc_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl, intr_idx, 3189 pi->rx_chan_map); 3190 if (rc != 0) 3191 return (rc); 3192 3193 children = SYSCTL_CHILDREN(oid); 3194 3195 snprintf(name, sizeof(name), "%d", idx); 3196 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 3197 NULL, "rx queue"); 3198 children = SYSCTL_CHILDREN(oid); 3199 3200 SYSCTL_ADD_UAUTO(&vi->ctx, children, OID_AUTO, "ba", CTLFLAG_RD, 3201 &ofld_rxq->iq.ba, "bus address of descriptor ring"); 3202 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3203 ofld_rxq->iq.qsize * IQ_ESIZE, "descriptor ring size in bytes"); 3204 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "abs_id", 3205 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.abs_id, 0, sysctl_uint16, 3206 "I", "absolute id of the queue"); 3207 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cntxt_id", 3208 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.cntxt_id, 0, sysctl_uint16, 3209 "I", "SGE context id of the queue"); 3210 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx", 3211 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.cidx, 0, sysctl_uint16, "I", 3212 "consumer index"); 3213 3214 add_fl_sysctls(pi->adapter, &vi->ctx, oid, &ofld_rxq->fl); 3215 3216 return (rc); 3217 } 3218 3219 static int 3220 free_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq) 3221 { 3222 int rc; 3223 3224 rc = free_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl); 3225 if (rc == 0) 3226 bzero(ofld_rxq, sizeof(*ofld_rxq)); 3227 3228 return (rc); 3229 } 3230 #endif 3231 3232 #ifdef DEV_NETMAP 3233 static int 3234 alloc_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq, int intr_idx, 3235 int idx, struct sysctl_oid *oid) 3236 { 3237 int rc; 3238 struct sysctl_oid_list *children; 3239 struct sysctl_ctx_list *ctx; 3240 char name[16]; 3241 size_t len; 3242 struct adapter *sc = vi->pi->adapter; 3243 struct netmap_adapter *na = NA(vi->ifp); 3244 3245 MPASS(na != NULL); 3246 3247 len = vi->qsize_rxq * IQ_ESIZE; 3248 rc = alloc_ring(sc, len, &nm_rxq->iq_desc_tag, &nm_rxq->iq_desc_map, 3249 &nm_rxq->iq_ba, (void **)&nm_rxq->iq_desc); 3250 if (rc != 0) 3251 return (rc); 3252 3253 len = na->num_rx_desc * EQ_ESIZE + sc->params.sge.spg_len; 3254 rc = alloc_ring(sc, len, &nm_rxq->fl_desc_tag, &nm_rxq->fl_desc_map, 3255 &nm_rxq->fl_ba, (void **)&nm_rxq->fl_desc); 3256 if (rc != 0) 3257 return (rc); 3258 3259 nm_rxq->vi = vi; 3260 nm_rxq->nid = idx; 3261 nm_rxq->iq_cidx = 0; 3262 nm_rxq->iq_sidx = vi->qsize_rxq - sc->params.sge.spg_len / IQ_ESIZE; 3263 nm_rxq->iq_gen = F_RSPD_GEN; 3264 nm_rxq->fl_pidx = nm_rxq->fl_cidx = 0; 3265 nm_rxq->fl_sidx = na->num_rx_desc; 3266 nm_rxq->intr_idx = intr_idx; 3267 3268 ctx = &vi->ctx; 3269 children = SYSCTL_CHILDREN(oid); 3270 3271 snprintf(name, sizeof(name), "%d", idx); 3272 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, name, CTLFLAG_RD, NULL, 3273 "rx queue"); 3274 children = SYSCTL_CHILDREN(oid); 3275 3276 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "abs_id", 3277 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_abs_id, 0, sysctl_uint16, 3278 "I", "absolute id of the queue"); 3279 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 3280 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cntxt_id, 0, sysctl_uint16, 3281 "I", "SGE context id of the queue"); 3282 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx", 3283 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cidx, 0, sysctl_uint16, "I", 3284 "consumer index"); 3285 3286 children = SYSCTL_CHILDREN(oid); 3287 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL, 3288 "freelist"); 3289 children = SYSCTL_CHILDREN(oid); 3290 3291 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 3292 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->fl_cntxt_id, 0, sysctl_uint16, 3293 "I", "SGE context id of the freelist"); 3294 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, 3295 &nm_rxq->fl_cidx, 0, "consumer index"); 3296 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, 3297 &nm_rxq->fl_pidx, 0, "producer index"); 3298 3299 return (rc); 3300 } 3301 3302 3303 static int 3304 free_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq) 3305 { 3306 struct adapter *sc = vi->pi->adapter; 3307 3308 free_ring(sc, nm_rxq->iq_desc_tag, nm_rxq->iq_desc_map, nm_rxq->iq_ba, 3309 nm_rxq->iq_desc); 3310 free_ring(sc, nm_rxq->fl_desc_tag, nm_rxq->fl_desc_map, nm_rxq->fl_ba, 3311 nm_rxq->fl_desc); 3312 3313 return (0); 3314 } 3315 3316 static int 3317 alloc_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq, int iqidx, int idx, 3318 struct sysctl_oid *oid) 3319 { 3320 int rc; 3321 size_t len; 3322 struct port_info *pi = vi->pi; 3323 struct adapter *sc = pi->adapter; 3324 struct netmap_adapter *na = NA(vi->ifp); 3325 char name[16]; 3326 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3327 3328 len = na->num_tx_desc * EQ_ESIZE + sc->params.sge.spg_len; 3329 rc = alloc_ring(sc, len, &nm_txq->desc_tag, &nm_txq->desc_map, 3330 &nm_txq->ba, (void **)&nm_txq->desc); 3331 if (rc) 3332 return (rc); 3333 3334 nm_txq->pidx = nm_txq->cidx = 0; 3335 nm_txq->sidx = na->num_tx_desc; 3336 nm_txq->nid = idx; 3337 nm_txq->iqidx = iqidx; 3338 nm_txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) | 3339 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(G_FW_VIID_PFN(vi->viid)) | 3340 V_TXPKT_VF(G_FW_VIID_VIN(vi->viid)) | 3341 V_TXPKT_VF_VLD(G_FW_VIID_VIVLD(vi->viid))); 3342 3343 snprintf(name, sizeof(name), "%d", idx); 3344 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 3345 NULL, "netmap tx queue"); 3346 children = SYSCTL_CHILDREN(oid); 3347 3348 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 3349 &nm_txq->cntxt_id, 0, "SGE context id of the queue"); 3350 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx", 3351 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->cidx, 0, sysctl_uint16, "I", 3352 "consumer index"); 3353 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "pidx", 3354 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->pidx, 0, sysctl_uint16, "I", 3355 "producer index"); 3356 3357 return (rc); 3358 } 3359 3360 static int 3361 free_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq) 3362 { 3363 struct adapter *sc = vi->pi->adapter; 3364 3365 free_ring(sc, nm_txq->desc_tag, nm_txq->desc_map, nm_txq->ba, 3366 nm_txq->desc); 3367 3368 return (0); 3369 } 3370 #endif 3371 3372 static int 3373 ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq) 3374 { 3375 int rc, cntxt_id; 3376 struct fw_eq_ctrl_cmd c; 3377 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 3378 3379 bzero(&c, sizeof(c)); 3380 3381 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | F_FW_CMD_REQUEST | 3382 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_CTRL_CMD_PFN(sc->pf) | 3383 V_FW_EQ_CTRL_CMD_VFN(0)); 3384 c.alloc_to_len16 = htobe32(F_FW_EQ_CTRL_CMD_ALLOC | 3385 F_FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c)); 3386 c.cmpliqid_eqid = htonl(V_FW_EQ_CTRL_CMD_CMPLIQID(eq->iqid)); 3387 c.physeqid_pkd = htobe32(0); 3388 c.fetchszm_to_iqid = 3389 htobe32(V_FW_EQ_CTRL_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 3390 V_FW_EQ_CTRL_CMD_PCIECHN(eq->tx_chan) | 3391 F_FW_EQ_CTRL_CMD_FETCHRO | V_FW_EQ_CTRL_CMD_IQID(eq->iqid)); 3392 c.dcaen_to_eqsize = 3393 htobe32(V_FW_EQ_CTRL_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 3394 V_FW_EQ_CTRL_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 3395 V_FW_EQ_CTRL_CMD_CIDXFTHRESH(X_CIDXFLUSHTHRESH_32) | 3396 V_FW_EQ_CTRL_CMD_EQSIZE(qsize)); 3397 c.eqaddr = htobe64(eq->ba); 3398 3399 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3400 if (rc != 0) { 3401 device_printf(sc->dev, 3402 "failed to create control queue %d: %d\n", eq->tx_chan, rc); 3403 return (rc); 3404 } 3405 eq->flags |= EQ_ALLOCATED; 3406 3407 eq->cntxt_id = G_FW_EQ_CTRL_CMD_EQID(be32toh(c.cmpliqid_eqid)); 3408 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 3409 if (cntxt_id >= sc->sge.neq) 3410 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 3411 cntxt_id, sc->sge.neq - 1); 3412 sc->sge.eqmap[cntxt_id] = eq; 3413 3414 return (rc); 3415 } 3416 3417 static int 3418 eth_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 3419 { 3420 int rc, cntxt_id; 3421 struct fw_eq_eth_cmd c; 3422 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 3423 3424 bzero(&c, sizeof(c)); 3425 3426 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST | 3427 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) | 3428 V_FW_EQ_ETH_CMD_VFN(0)); 3429 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC | 3430 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c)); 3431 c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE | 3432 F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(vi->viid)); 3433 c.fetchszm_to_iqid = 3434 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) | 3435 V_FW_EQ_ETH_CMD_PCIECHN(eq->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO | 3436 V_FW_EQ_ETH_CMD_IQID(eq->iqid)); 3437 c.dcaen_to_eqsize = htobe32(V_FW_EQ_ETH_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 3438 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 3439 V_FW_EQ_ETH_CMD_EQSIZE(qsize)); 3440 c.eqaddr = htobe64(eq->ba); 3441 3442 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3443 if (rc != 0) { 3444 device_printf(vi->dev, 3445 "failed to create Ethernet egress queue: %d\n", rc); 3446 return (rc); 3447 } 3448 eq->flags |= EQ_ALLOCATED; 3449 3450 eq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd)); 3451 eq->abs_id = G_FW_EQ_ETH_CMD_PHYSEQID(be32toh(c.physeqid_pkd)); 3452 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 3453 if (cntxt_id >= sc->sge.neq) 3454 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 3455 cntxt_id, sc->sge.neq - 1); 3456 sc->sge.eqmap[cntxt_id] = eq; 3457 3458 return (rc); 3459 } 3460 3461 #ifdef TCP_OFFLOAD 3462 static int 3463 ofld_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 3464 { 3465 int rc, cntxt_id; 3466 struct fw_eq_ofld_cmd c; 3467 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 3468 3469 bzero(&c, sizeof(c)); 3470 3471 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | F_FW_CMD_REQUEST | 3472 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_OFLD_CMD_PFN(sc->pf) | 3473 V_FW_EQ_OFLD_CMD_VFN(0)); 3474 c.alloc_to_len16 = htonl(F_FW_EQ_OFLD_CMD_ALLOC | 3475 F_FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c)); 3476 c.fetchszm_to_iqid = 3477 htonl(V_FW_EQ_OFLD_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) | 3478 V_FW_EQ_OFLD_CMD_PCIECHN(eq->tx_chan) | 3479 F_FW_EQ_OFLD_CMD_FETCHRO | V_FW_EQ_OFLD_CMD_IQID(eq->iqid)); 3480 c.dcaen_to_eqsize = 3481 htobe32(V_FW_EQ_OFLD_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 3482 V_FW_EQ_OFLD_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 3483 V_FW_EQ_OFLD_CMD_EQSIZE(qsize)); 3484 c.eqaddr = htobe64(eq->ba); 3485 3486 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3487 if (rc != 0) { 3488 device_printf(vi->dev, 3489 "failed to create egress queue for TCP offload: %d\n", rc); 3490 return (rc); 3491 } 3492 eq->flags |= EQ_ALLOCATED; 3493 3494 eq->cntxt_id = G_FW_EQ_OFLD_CMD_EQID(be32toh(c.eqid_pkd)); 3495 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 3496 if (cntxt_id >= sc->sge.neq) 3497 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 3498 cntxt_id, sc->sge.neq - 1); 3499 sc->sge.eqmap[cntxt_id] = eq; 3500 3501 return (rc); 3502 } 3503 #endif 3504 3505 static int 3506 alloc_eq(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 3507 { 3508 int rc, qsize; 3509 size_t len; 3510 3511 mtx_init(&eq->eq_lock, eq->lockname, NULL, MTX_DEF); 3512 3513 qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 3514 len = qsize * EQ_ESIZE; 3515 rc = alloc_ring(sc, len, &eq->desc_tag, &eq->desc_map, 3516 &eq->ba, (void **)&eq->desc); 3517 if (rc) 3518 return (rc); 3519 3520 eq->pidx = eq->cidx = 0; 3521 eq->equeqidx = eq->dbidx = 0; 3522 eq->doorbells = sc->doorbells; 3523 3524 switch (eq->flags & EQ_TYPEMASK) { 3525 case EQ_CTRL: 3526 rc = ctrl_eq_alloc(sc, eq); 3527 break; 3528 3529 case EQ_ETH: 3530 rc = eth_eq_alloc(sc, vi, eq); 3531 break; 3532 3533 #ifdef TCP_OFFLOAD 3534 case EQ_OFLD: 3535 rc = ofld_eq_alloc(sc, vi, eq); 3536 break; 3537 #endif 3538 3539 default: 3540 panic("%s: invalid eq type %d.", __func__, 3541 eq->flags & EQ_TYPEMASK); 3542 } 3543 if (rc != 0) { 3544 device_printf(sc->dev, 3545 "failed to allocate egress queue(%d): %d\n", 3546 eq->flags & EQ_TYPEMASK, rc); 3547 } 3548 3549 if (isset(&eq->doorbells, DOORBELL_UDB) || 3550 isset(&eq->doorbells, DOORBELL_UDBWC) || 3551 isset(&eq->doorbells, DOORBELL_WCWR)) { 3552 uint32_t s_qpp = sc->params.sge.eq_s_qpp; 3553 uint32_t mask = (1 << s_qpp) - 1; 3554 volatile uint8_t *udb; 3555 3556 udb = sc->udbs_base + UDBS_DB_OFFSET; 3557 udb += (eq->cntxt_id >> s_qpp) << PAGE_SHIFT; /* pg offset */ 3558 eq->udb_qid = eq->cntxt_id & mask; /* id in page */ 3559 if (eq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE) 3560 clrbit(&eq->doorbells, DOORBELL_WCWR); 3561 else { 3562 udb += eq->udb_qid << UDBS_SEG_SHIFT; /* seg offset */ 3563 eq->udb_qid = 0; 3564 } 3565 eq->udb = (volatile void *)udb; 3566 } 3567 3568 return (rc); 3569 } 3570 3571 static int 3572 free_eq(struct adapter *sc, struct sge_eq *eq) 3573 { 3574 int rc; 3575 3576 if (eq->flags & EQ_ALLOCATED) { 3577 switch (eq->flags & EQ_TYPEMASK) { 3578 case EQ_CTRL: 3579 rc = -t4_ctrl_eq_free(sc, sc->mbox, sc->pf, 0, 3580 eq->cntxt_id); 3581 break; 3582 3583 case EQ_ETH: 3584 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0, 3585 eq->cntxt_id); 3586 break; 3587 3588 #ifdef TCP_OFFLOAD 3589 case EQ_OFLD: 3590 rc = -t4_ofld_eq_free(sc, sc->mbox, sc->pf, 0, 3591 eq->cntxt_id); 3592 break; 3593 #endif 3594 3595 default: 3596 panic("%s: invalid eq type %d.", __func__, 3597 eq->flags & EQ_TYPEMASK); 3598 } 3599 if (rc != 0) { 3600 device_printf(sc->dev, 3601 "failed to free egress queue (%d): %d\n", 3602 eq->flags & EQ_TYPEMASK, rc); 3603 return (rc); 3604 } 3605 eq->flags &= ~EQ_ALLOCATED; 3606 } 3607 3608 free_ring(sc, eq->desc_tag, eq->desc_map, eq->ba, eq->desc); 3609 3610 if (mtx_initialized(&eq->eq_lock)) 3611 mtx_destroy(&eq->eq_lock); 3612 3613 bzero(eq, sizeof(*eq)); 3614 return (0); 3615 } 3616 3617 static int 3618 alloc_wrq(struct adapter *sc, struct vi_info *vi, struct sge_wrq *wrq, 3619 struct sysctl_oid *oid) 3620 { 3621 int rc; 3622 struct sysctl_ctx_list *ctx = vi ? &vi->ctx : &sc->ctx; 3623 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3624 3625 rc = alloc_eq(sc, vi, &wrq->eq); 3626 if (rc) 3627 return (rc); 3628 3629 wrq->adapter = sc; 3630 TASK_INIT(&wrq->wrq_tx_task, 0, wrq_tx_drain, wrq); 3631 TAILQ_INIT(&wrq->incomplete_wrs); 3632 STAILQ_INIT(&wrq->wr_list); 3633 wrq->nwr_pending = 0; 3634 wrq->ndesc_needed = 0; 3635 3636 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, 3637 &wrq->eq.ba, "bus address of descriptor ring"); 3638 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3639 wrq->eq.sidx * EQ_ESIZE + sc->params.sge.spg_len, 3640 "desc ring size in bytes"); 3641 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 3642 &wrq->eq.cntxt_id, 0, "SGE context id of the queue"); 3643 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx", 3644 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.cidx, 0, sysctl_uint16, "I", 3645 "consumer index"); 3646 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pidx", 3647 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.pidx, 0, sysctl_uint16, "I", 3648 "producer index"); 3649 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL, 3650 wrq->eq.sidx, "status page index"); 3651 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_direct", CTLFLAG_RD, 3652 &wrq->tx_wrs_direct, "# of work requests (direct)"); 3653 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_copied", CTLFLAG_RD, 3654 &wrq->tx_wrs_copied, "# of work requests (copied)"); 3655 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_sspace", CTLFLAG_RD, 3656 &wrq->tx_wrs_ss, "# of work requests (copied from scratch space)"); 3657 3658 return (rc); 3659 } 3660 3661 static int 3662 free_wrq(struct adapter *sc, struct sge_wrq *wrq) 3663 { 3664 int rc; 3665 3666 rc = free_eq(sc, &wrq->eq); 3667 if (rc) 3668 return (rc); 3669 3670 bzero(wrq, sizeof(*wrq)); 3671 return (0); 3672 } 3673 3674 static int 3675 alloc_txq(struct vi_info *vi, struct sge_txq *txq, int idx, 3676 struct sysctl_oid *oid) 3677 { 3678 int rc; 3679 struct port_info *pi = vi->pi; 3680 struct adapter *sc = pi->adapter; 3681 struct sge_eq *eq = &txq->eq; 3682 char name[16]; 3683 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3684 3685 rc = mp_ring_alloc(&txq->r, eq->sidx, txq, eth_tx, can_resume_eth_tx, 3686 M_CXGBE, M_WAITOK); 3687 if (rc != 0) { 3688 device_printf(sc->dev, "failed to allocate mp_ring: %d\n", rc); 3689 return (rc); 3690 } 3691 3692 rc = alloc_eq(sc, vi, eq); 3693 if (rc != 0) { 3694 mp_ring_free(txq->r); 3695 txq->r = NULL; 3696 return (rc); 3697 } 3698 3699 /* Can't fail after this point. */ 3700 3701 if (idx == 0) 3702 sc->sge.eq_base = eq->abs_id - eq->cntxt_id; 3703 else 3704 KASSERT(eq->cntxt_id + sc->sge.eq_base == eq->abs_id, 3705 ("eq_base mismatch")); 3706 KASSERT(sc->sge.eq_base == 0 || sc->flags & IS_VF, 3707 ("PF with non-zero eq_base")); 3708 3709 TASK_INIT(&txq->tx_reclaim_task, 0, tx_reclaim, eq); 3710 txq->ifp = vi->ifp; 3711 txq->gl = sglist_alloc(TX_SGL_SEGS, M_WAITOK); 3712 if (sc->flags & IS_VF) 3713 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) | 3714 V_TXPKT_INTF(pi->tx_chan)); 3715 else 3716 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) | 3717 V_TXPKT_INTF(pi->tx_chan) | 3718 V_TXPKT_PF(G_FW_VIID_PFN(vi->viid)) | 3719 V_TXPKT_VF(G_FW_VIID_VIN(vi->viid)) | 3720 V_TXPKT_VF_VLD(G_FW_VIID_VIVLD(vi->viid))); 3721 txq->tc_idx = -1; 3722 txq->sdesc = malloc(eq->sidx * sizeof(struct tx_sdesc), M_CXGBE, 3723 M_ZERO | M_WAITOK); 3724 3725 snprintf(name, sizeof(name), "%d", idx); 3726 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 3727 NULL, "tx queue"); 3728 children = SYSCTL_CHILDREN(oid); 3729 3730 SYSCTL_ADD_UAUTO(&vi->ctx, children, OID_AUTO, "ba", CTLFLAG_RD, 3731 &eq->ba, "bus address of descriptor ring"); 3732 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3733 eq->sidx * EQ_ESIZE + sc->params.sge.spg_len, 3734 "desc ring size in bytes"); 3735 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "abs_id", CTLFLAG_RD, 3736 &eq->abs_id, 0, "absolute id of the queue"); 3737 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 3738 &eq->cntxt_id, 0, "SGE context id of the queue"); 3739 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx", 3740 CTLTYPE_INT | CTLFLAG_RD, &eq->cidx, 0, sysctl_uint16, "I", 3741 "consumer index"); 3742 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "pidx", 3743 CTLTYPE_INT | CTLFLAG_RD, &eq->pidx, 0, sysctl_uint16, "I", 3744 "producer index"); 3745 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL, 3746 eq->sidx, "status page index"); 3747 3748 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "tc", 3749 CTLTYPE_INT | CTLFLAG_RW, vi, idx, sysctl_tc, "I", 3750 "traffic class (-1 means none)"); 3751 3752 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txcsum", CTLFLAG_RD, 3753 &txq->txcsum, "# of times hardware assisted with checksum"); 3754 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_insertion", 3755 CTLFLAG_RD, &txq->vlan_insertion, 3756 "# of times hardware inserted 802.1Q tag"); 3757 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "tso_wrs", CTLFLAG_RD, 3758 &txq->tso_wrs, "# of TSO work requests"); 3759 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "imm_wrs", CTLFLAG_RD, 3760 &txq->imm_wrs, "# of work requests with immediate data"); 3761 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "sgl_wrs", CTLFLAG_RD, 3762 &txq->sgl_wrs, "# of work requests with direct SGL"); 3763 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkt_wrs", CTLFLAG_RD, 3764 &txq->txpkt_wrs, "# of txpkt work requests (one pkt/WR)"); 3765 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_wrs", 3766 CTLFLAG_RD, &txq->txpkts0_wrs, 3767 "# of txpkts (type 0) work requests"); 3768 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_wrs", 3769 CTLFLAG_RD, &txq->txpkts1_wrs, 3770 "# of txpkts (type 1) work requests"); 3771 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_pkts", 3772 CTLFLAG_RD, &txq->txpkts0_pkts, 3773 "# of frames tx'd using type0 txpkts work requests"); 3774 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_pkts", 3775 CTLFLAG_RD, &txq->txpkts1_pkts, 3776 "# of frames tx'd using type1 txpkts work requests"); 3777 3778 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_enqueues", 3779 CTLFLAG_RD, &txq->r->enqueues, 3780 "# of enqueues to the mp_ring for this queue"); 3781 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_drops", 3782 CTLFLAG_RD, &txq->r->drops, 3783 "# of drops in the mp_ring for this queue"); 3784 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_starts", 3785 CTLFLAG_RD, &txq->r->starts, 3786 "# of normal consumer starts in the mp_ring for this queue"); 3787 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_stalls", 3788 CTLFLAG_RD, &txq->r->stalls, 3789 "# of consumer stalls in the mp_ring for this queue"); 3790 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_restarts", 3791 CTLFLAG_RD, &txq->r->restarts, 3792 "# of consumer restarts in the mp_ring for this queue"); 3793 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_abdications", 3794 CTLFLAG_RD, &txq->r->abdications, 3795 "# of consumer abdications in the mp_ring for this queue"); 3796 3797 return (0); 3798 } 3799 3800 static int 3801 free_txq(struct vi_info *vi, struct sge_txq *txq) 3802 { 3803 int rc; 3804 struct adapter *sc = vi->pi->adapter; 3805 struct sge_eq *eq = &txq->eq; 3806 3807 rc = free_eq(sc, eq); 3808 if (rc) 3809 return (rc); 3810 3811 sglist_free(txq->gl); 3812 free(txq->sdesc, M_CXGBE); 3813 mp_ring_free(txq->r); 3814 3815 bzero(txq, sizeof(*txq)); 3816 return (0); 3817 } 3818 3819 static void 3820 oneseg_dma_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3821 { 3822 bus_addr_t *ba = arg; 3823 3824 KASSERT(nseg == 1, 3825 ("%s meant for single segment mappings only.", __func__)); 3826 3827 *ba = error ? 0 : segs->ds_addr; 3828 } 3829 3830 static inline void 3831 ring_fl_db(struct adapter *sc, struct sge_fl *fl) 3832 { 3833 uint32_t n, v; 3834 3835 n = IDXDIFF(fl->pidx / 8, fl->dbidx, fl->sidx); 3836 MPASS(n > 0); 3837 3838 wmb(); 3839 v = fl->dbval | V_PIDX(n); 3840 if (fl->udb) 3841 *fl->udb = htole32(v); 3842 else 3843 t4_write_reg(sc, sc->sge_kdoorbell_reg, v); 3844 IDXINCR(fl->dbidx, n, fl->sidx); 3845 } 3846 3847 /* 3848 * Fills up the freelist by allocating up to 'n' buffers. Buffers that are 3849 * recycled do not count towards this allocation budget. 3850 * 3851 * Returns non-zero to indicate that this freelist should be added to the list 3852 * of starving freelists. 3853 */ 3854 static int 3855 refill_fl(struct adapter *sc, struct sge_fl *fl, int n) 3856 { 3857 __be64 *d; 3858 struct fl_sdesc *sd; 3859 uintptr_t pa; 3860 caddr_t cl; 3861 struct cluster_layout *cll; 3862 struct sw_zone_info *swz; 3863 struct cluster_metadata *clm; 3864 uint16_t max_pidx; 3865 uint16_t hw_cidx = fl->hw_cidx; /* stable snapshot */ 3866 3867 FL_LOCK_ASSERT_OWNED(fl); 3868 3869 /* 3870 * We always stop at the beginning of the hardware descriptor that's just 3871 * before the one with the hw cidx. This is to avoid hw pidx = hw cidx, 3872 * which would mean an empty freelist to the chip. 3873 */ 3874 max_pidx = __predict_false(hw_cidx == 0) ? fl->sidx - 1 : hw_cidx - 1; 3875 if (fl->pidx == max_pidx * 8) 3876 return (0); 3877 3878 d = &fl->desc[fl->pidx]; 3879 sd = &fl->sdesc[fl->pidx]; 3880 cll = &fl->cll_def; /* default layout */ 3881 swz = &sc->sge.sw_zone_info[cll->zidx]; 3882 3883 while (n > 0) { 3884 3885 if (sd->cl != NULL) { 3886 3887 if (sd->nmbuf == 0) { 3888 /* 3889 * Fast recycle without involving any atomics on 3890 * the cluster's metadata (if the cluster has 3891 * metadata). This happens when all frames 3892 * received in the cluster were small enough to 3893 * fit within a single mbuf each. 3894 */ 3895 fl->cl_fast_recycled++; 3896 #ifdef INVARIANTS 3897 clm = cl_metadata(sc, fl, &sd->cll, sd->cl); 3898 if (clm != NULL) 3899 MPASS(clm->refcount == 1); 3900 #endif 3901 goto recycled_fast; 3902 } 3903 3904 /* 3905 * Cluster is guaranteed to have metadata. Clusters 3906 * without metadata always take the fast recycle path 3907 * when they're recycled. 3908 */ 3909 clm = cl_metadata(sc, fl, &sd->cll, sd->cl); 3910 MPASS(clm != NULL); 3911 3912 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) { 3913 fl->cl_recycled++; 3914 counter_u64_add(extfree_rels, 1); 3915 goto recycled; 3916 } 3917 sd->cl = NULL; /* gave up my reference */ 3918 } 3919 MPASS(sd->cl == NULL); 3920 alloc: 3921 cl = uma_zalloc(swz->zone, M_NOWAIT); 3922 if (__predict_false(cl == NULL)) { 3923 if (cll == &fl->cll_alt || fl->cll_alt.zidx == -1 || 3924 fl->cll_def.zidx == fl->cll_alt.zidx) 3925 break; 3926 3927 /* fall back to the safe zone */ 3928 cll = &fl->cll_alt; 3929 swz = &sc->sge.sw_zone_info[cll->zidx]; 3930 goto alloc; 3931 } 3932 fl->cl_allocated++; 3933 n--; 3934 3935 pa = pmap_kextract((vm_offset_t)cl); 3936 pa += cll->region1; 3937 sd->cl = cl; 3938 sd->cll = *cll; 3939 *d = htobe64(pa | cll->hwidx); 3940 clm = cl_metadata(sc, fl, cll, cl); 3941 if (clm != NULL) { 3942 recycled: 3943 #ifdef INVARIANTS 3944 clm->sd = sd; 3945 #endif 3946 clm->refcount = 1; 3947 } 3948 sd->nmbuf = 0; 3949 recycled_fast: 3950 d++; 3951 sd++; 3952 if (__predict_false(++fl->pidx % 8 == 0)) { 3953 uint16_t pidx = fl->pidx / 8; 3954 3955 if (__predict_false(pidx == fl->sidx)) { 3956 fl->pidx = 0; 3957 pidx = 0; 3958 sd = fl->sdesc; 3959 d = fl->desc; 3960 } 3961 if (pidx == max_pidx) 3962 break; 3963 3964 if (IDXDIFF(pidx, fl->dbidx, fl->sidx) >= 4) 3965 ring_fl_db(sc, fl); 3966 } 3967 } 3968 3969 if (fl->pidx / 8 != fl->dbidx) 3970 ring_fl_db(sc, fl); 3971 3972 return (FL_RUNNING_LOW(fl) && !(fl->flags & FL_STARVING)); 3973 } 3974 3975 /* 3976 * Attempt to refill all starving freelists. 3977 */ 3978 static void 3979 refill_sfl(void *arg) 3980 { 3981 struct adapter *sc = arg; 3982 struct sge_fl *fl, *fl_temp; 3983 3984 mtx_assert(&sc->sfl_lock, MA_OWNED); 3985 TAILQ_FOREACH_SAFE(fl, &sc->sfl, link, fl_temp) { 3986 FL_LOCK(fl); 3987 refill_fl(sc, fl, 64); 3988 if (FL_NOT_RUNNING_LOW(fl) || fl->flags & FL_DOOMED) { 3989 TAILQ_REMOVE(&sc->sfl, fl, link); 3990 fl->flags &= ~FL_STARVING; 3991 } 3992 FL_UNLOCK(fl); 3993 } 3994 3995 if (!TAILQ_EMPTY(&sc->sfl)) 3996 callout_schedule(&sc->sfl_callout, hz / 5); 3997 } 3998 3999 static int 4000 alloc_fl_sdesc(struct sge_fl *fl) 4001 { 4002 4003 fl->sdesc = malloc(fl->sidx * 8 * sizeof(struct fl_sdesc), M_CXGBE, 4004 M_ZERO | M_WAITOK); 4005 4006 return (0); 4007 } 4008 4009 static void 4010 free_fl_sdesc(struct adapter *sc, struct sge_fl *fl) 4011 { 4012 struct fl_sdesc *sd; 4013 struct cluster_metadata *clm; 4014 struct cluster_layout *cll; 4015 int i; 4016 4017 sd = fl->sdesc; 4018 for (i = 0; i < fl->sidx * 8; i++, sd++) { 4019 if (sd->cl == NULL) 4020 continue; 4021 4022 cll = &sd->cll; 4023 clm = cl_metadata(sc, fl, cll, sd->cl); 4024 if (sd->nmbuf == 0) 4025 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl); 4026 else if (clm && atomic_fetchadd_int(&clm->refcount, -1) == 1) { 4027 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl); 4028 counter_u64_add(extfree_rels, 1); 4029 } 4030 sd->cl = NULL; 4031 } 4032 4033 free(fl->sdesc, M_CXGBE); 4034 fl->sdesc = NULL; 4035 } 4036 4037 static inline void 4038 get_pkt_gl(struct mbuf *m, struct sglist *gl) 4039 { 4040 int rc; 4041 4042 M_ASSERTPKTHDR(m); 4043 4044 sglist_reset(gl); 4045 rc = sglist_append_mbuf(gl, m); 4046 if (__predict_false(rc != 0)) { 4047 panic("%s: mbuf %p (%d segs) was vetted earlier but now fails " 4048 "with %d.", __func__, m, mbuf_nsegs(m), rc); 4049 } 4050 4051 KASSERT(gl->sg_nseg == mbuf_nsegs(m), 4052 ("%s: nsegs changed for mbuf %p from %d to %d", __func__, m, 4053 mbuf_nsegs(m), gl->sg_nseg)); 4054 KASSERT(gl->sg_nseg > 0 && 4055 gl->sg_nseg <= (needs_tso(m) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS), 4056 ("%s: %d segments, should have been 1 <= nsegs <= %d", __func__, 4057 gl->sg_nseg, needs_tso(m) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS)); 4058 } 4059 4060 /* 4061 * len16 for a txpkt WR with a GL. Includes the firmware work request header. 4062 */ 4063 static inline u_int 4064 txpkt_len16(u_int nsegs, u_int tso) 4065 { 4066 u_int n; 4067 4068 MPASS(nsegs > 0); 4069 4070 nsegs--; /* first segment is part of ulptx_sgl */ 4071 n = sizeof(struct fw_eth_tx_pkt_wr) + sizeof(struct cpl_tx_pkt_core) + 4072 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 4073 if (tso) 4074 n += sizeof(struct cpl_tx_pkt_lso_core); 4075 4076 return (howmany(n, 16)); 4077 } 4078 4079 /* 4080 * len16 for a txpkt_vm WR with a GL. Includes the firmware work 4081 * request header. 4082 */ 4083 static inline u_int 4084 txpkt_vm_len16(u_int nsegs, u_int tso) 4085 { 4086 u_int n; 4087 4088 MPASS(nsegs > 0); 4089 4090 nsegs--; /* first segment is part of ulptx_sgl */ 4091 n = sizeof(struct fw_eth_tx_pkt_vm_wr) + 4092 sizeof(struct cpl_tx_pkt_core) + 4093 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 4094 if (tso) 4095 n += sizeof(struct cpl_tx_pkt_lso_core); 4096 4097 return (howmany(n, 16)); 4098 } 4099 4100 /* 4101 * len16 for a txpkts type 0 WR with a GL. Does not include the firmware work 4102 * request header. 4103 */ 4104 static inline u_int 4105 txpkts0_len16(u_int nsegs) 4106 { 4107 u_int n; 4108 4109 MPASS(nsegs > 0); 4110 4111 nsegs--; /* first segment is part of ulptx_sgl */ 4112 n = sizeof(struct ulp_txpkt) + sizeof(struct ulptx_idata) + 4113 sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl) + 4114 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 4115 4116 return (howmany(n, 16)); 4117 } 4118 4119 /* 4120 * len16 for a txpkts type 1 WR with a GL. Does not include the firmware work 4121 * request header. 4122 */ 4123 static inline u_int 4124 txpkts1_len16(void) 4125 { 4126 u_int n; 4127 4128 n = sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl); 4129 4130 return (howmany(n, 16)); 4131 } 4132 4133 static inline u_int 4134 imm_payload(u_int ndesc) 4135 { 4136 u_int n; 4137 4138 n = ndesc * EQ_ESIZE - sizeof(struct fw_eth_tx_pkt_wr) - 4139 sizeof(struct cpl_tx_pkt_core); 4140 4141 return (n); 4142 } 4143 4144 /* 4145 * Write a VM txpkt WR for this packet to the hardware descriptors, update the 4146 * software descriptor, and advance the pidx. It is guaranteed that enough 4147 * descriptors are available. 4148 * 4149 * The return value is the # of hardware descriptors used. 4150 */ 4151 static u_int 4152 write_txpkt_vm_wr(struct adapter *sc, struct sge_txq *txq, 4153 struct fw_eth_tx_pkt_vm_wr *wr, struct mbuf *m0, u_int available) 4154 { 4155 struct sge_eq *eq = &txq->eq; 4156 struct tx_sdesc *txsd; 4157 struct cpl_tx_pkt_core *cpl; 4158 uint32_t ctrl; /* used in many unrelated places */ 4159 uint64_t ctrl1; 4160 int csum_type, len16, ndesc, pktlen, nsegs; 4161 caddr_t dst; 4162 4163 TXQ_LOCK_ASSERT_OWNED(txq); 4164 M_ASSERTPKTHDR(m0); 4165 MPASS(available > 0 && available < eq->sidx); 4166 4167 len16 = mbuf_len16(m0); 4168 nsegs = mbuf_nsegs(m0); 4169 pktlen = m0->m_pkthdr.len; 4170 ctrl = sizeof(struct cpl_tx_pkt_core); 4171 if (needs_tso(m0)) 4172 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 4173 ndesc = howmany(len16, EQ_ESIZE / 16); 4174 MPASS(ndesc <= available); 4175 4176 /* Firmware work request header */ 4177 MPASS(wr == (void *)&eq->desc[eq->pidx]); 4178 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_VM_WR) | 4179 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl)); 4180 4181 ctrl = V_FW_WR_LEN16(len16); 4182 wr->equiq_to_len16 = htobe32(ctrl); 4183 wr->r3[0] = 0; 4184 wr->r3[1] = 0; 4185 4186 /* 4187 * Copy over ethmacdst, ethmacsrc, ethtype, and vlantci. 4188 * vlantci is ignored unless the ethtype is 0x8100, so it's 4189 * simpler to always copy it rather than making it 4190 * conditional. Also, it seems that we do not have to set 4191 * vlantci or fake the ethtype when doing VLAN tag insertion. 4192 */ 4193 m_copydata(m0, 0, sizeof(struct ether_header) + 2, wr->ethmacdst); 4194 4195 csum_type = -1; 4196 if (needs_tso(m0)) { 4197 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1); 4198 4199 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 4200 m0->m_pkthdr.l4hlen > 0, 4201 ("%s: mbuf %p needs TSO but missing header lengths", 4202 __func__, m0)); 4203 4204 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE | 4205 F_LSO_LAST_SLICE | V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) 4206 | V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2); 4207 if (m0->m_pkthdr.l2hlen == sizeof(struct ether_vlan_header)) 4208 ctrl |= V_LSO_ETHHDR_LEN(1); 4209 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 4210 ctrl |= F_LSO_IPV6; 4211 4212 lso->lso_ctrl = htobe32(ctrl); 4213 lso->ipid_ofst = htobe16(0); 4214 lso->mss = htobe16(m0->m_pkthdr.tso_segsz); 4215 lso->seqno_offset = htobe32(0); 4216 lso->len = htobe32(pktlen); 4217 4218 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 4219 csum_type = TX_CSUM_TCPIP6; 4220 else 4221 csum_type = TX_CSUM_TCPIP; 4222 4223 cpl = (void *)(lso + 1); 4224 4225 txq->tso_wrs++; 4226 } else { 4227 if (m0->m_pkthdr.csum_flags & CSUM_IP_TCP) 4228 csum_type = TX_CSUM_TCPIP; 4229 else if (m0->m_pkthdr.csum_flags & CSUM_IP_UDP) 4230 csum_type = TX_CSUM_UDPIP; 4231 else if (m0->m_pkthdr.csum_flags & CSUM_IP6_TCP) 4232 csum_type = TX_CSUM_TCPIP6; 4233 else if (m0->m_pkthdr.csum_flags & CSUM_IP6_UDP) 4234 csum_type = TX_CSUM_UDPIP6; 4235 #if defined(INET) 4236 else if (m0->m_pkthdr.csum_flags & CSUM_IP) { 4237 /* 4238 * XXX: The firmware appears to stomp on the 4239 * fragment/flags field of the IP header when 4240 * using TX_CSUM_IP. Fall back to doing 4241 * software checksums. 4242 */ 4243 u_short *sump; 4244 struct mbuf *m; 4245 int offset; 4246 4247 m = m0; 4248 offset = 0; 4249 sump = m_advance(&m, &offset, m0->m_pkthdr.l2hlen + 4250 offsetof(struct ip, ip_sum)); 4251 *sump = in_cksum_skip(m0, m0->m_pkthdr.l2hlen + 4252 m0->m_pkthdr.l3hlen, m0->m_pkthdr.l2hlen); 4253 m0->m_pkthdr.csum_flags &= ~CSUM_IP; 4254 } 4255 #endif 4256 4257 cpl = (void *)(wr + 1); 4258 } 4259 4260 /* Checksum offload */ 4261 ctrl1 = 0; 4262 if (needs_l3_csum(m0) == 0) 4263 ctrl1 |= F_TXPKT_IPCSUM_DIS; 4264 if (csum_type >= 0) { 4265 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0, 4266 ("%s: mbuf %p needs checksum offload but missing header lengths", 4267 __func__, m0)); 4268 4269 if (chip_id(sc) <= CHELSIO_T5) { 4270 ctrl1 |= V_TXPKT_ETHHDR_LEN(m0->m_pkthdr.l2hlen - 4271 ETHER_HDR_LEN); 4272 } else { 4273 ctrl1 |= V_T6_TXPKT_ETHHDR_LEN(m0->m_pkthdr.l2hlen - 4274 ETHER_HDR_LEN); 4275 } 4276 ctrl1 |= V_TXPKT_IPHDR_LEN(m0->m_pkthdr.l3hlen); 4277 ctrl1 |= V_TXPKT_CSUM_TYPE(csum_type); 4278 } else 4279 ctrl1 |= F_TXPKT_L4CSUM_DIS; 4280 if (m0->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | 4281 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO)) 4282 txq->txcsum++; /* some hardware assistance provided */ 4283 4284 /* VLAN tag insertion */ 4285 if (needs_vlan_insertion(m0)) { 4286 ctrl1 |= F_TXPKT_VLAN_VLD | 4287 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 4288 txq->vlan_insertion++; 4289 } 4290 4291 /* CPL header */ 4292 cpl->ctrl0 = txq->cpl_ctrl0; 4293 cpl->pack = 0; 4294 cpl->len = htobe16(pktlen); 4295 cpl->ctrl1 = htobe64(ctrl1); 4296 4297 /* SGL */ 4298 dst = (void *)(cpl + 1); 4299 4300 /* 4301 * A packet using TSO will use up an entire descriptor for the 4302 * firmware work request header, LSO CPL, and TX_PKT_XT CPL. 4303 * If this descriptor is the last descriptor in the ring, wrap 4304 * around to the front of the ring explicitly for the start of 4305 * the sgl. 4306 */ 4307 if (dst == (void *)&eq->desc[eq->sidx]) { 4308 dst = (void *)&eq->desc[0]; 4309 write_gl_to_txd(txq, m0, &dst, 0); 4310 } else 4311 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx); 4312 txq->sgl_wrs++; 4313 4314 txq->txpkt_wrs++; 4315 4316 txsd = &txq->sdesc[eq->pidx]; 4317 txsd->m = m0; 4318 txsd->desc_used = ndesc; 4319 4320 return (ndesc); 4321 } 4322 4323 /* 4324 * Write a txpkt WR for this packet to the hardware descriptors, update the 4325 * software descriptor, and advance the pidx. It is guaranteed that enough 4326 * descriptors are available. 4327 * 4328 * The return value is the # of hardware descriptors used. 4329 */ 4330 static u_int 4331 write_txpkt_wr(struct sge_txq *txq, struct fw_eth_tx_pkt_wr *wr, 4332 struct mbuf *m0, u_int available) 4333 { 4334 struct sge_eq *eq = &txq->eq; 4335 struct tx_sdesc *txsd; 4336 struct cpl_tx_pkt_core *cpl; 4337 uint32_t ctrl; /* used in many unrelated places */ 4338 uint64_t ctrl1; 4339 int len16, ndesc, pktlen, nsegs; 4340 caddr_t dst; 4341 4342 TXQ_LOCK_ASSERT_OWNED(txq); 4343 M_ASSERTPKTHDR(m0); 4344 MPASS(available > 0 && available < eq->sidx); 4345 4346 len16 = mbuf_len16(m0); 4347 nsegs = mbuf_nsegs(m0); 4348 pktlen = m0->m_pkthdr.len; 4349 ctrl = sizeof(struct cpl_tx_pkt_core); 4350 if (needs_tso(m0)) 4351 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 4352 else if (pktlen <= imm_payload(2) && available >= 2) { 4353 /* Immediate data. Recalculate len16 and set nsegs to 0. */ 4354 ctrl += pktlen; 4355 len16 = howmany(sizeof(struct fw_eth_tx_pkt_wr) + 4356 sizeof(struct cpl_tx_pkt_core) + pktlen, 16); 4357 nsegs = 0; 4358 } 4359 ndesc = howmany(len16, EQ_ESIZE / 16); 4360 MPASS(ndesc <= available); 4361 4362 /* Firmware work request header */ 4363 MPASS(wr == (void *)&eq->desc[eq->pidx]); 4364 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_WR) | 4365 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl)); 4366 4367 ctrl = V_FW_WR_LEN16(len16); 4368 wr->equiq_to_len16 = htobe32(ctrl); 4369 wr->r3 = 0; 4370 4371 if (needs_tso(m0)) { 4372 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1); 4373 4374 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 4375 m0->m_pkthdr.l4hlen > 0, 4376 ("%s: mbuf %p needs TSO but missing header lengths", 4377 __func__, m0)); 4378 4379 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE | 4380 F_LSO_LAST_SLICE | V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) 4381 | V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2); 4382 if (m0->m_pkthdr.l2hlen == sizeof(struct ether_vlan_header)) 4383 ctrl |= V_LSO_ETHHDR_LEN(1); 4384 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 4385 ctrl |= F_LSO_IPV6; 4386 4387 lso->lso_ctrl = htobe32(ctrl); 4388 lso->ipid_ofst = htobe16(0); 4389 lso->mss = htobe16(m0->m_pkthdr.tso_segsz); 4390 lso->seqno_offset = htobe32(0); 4391 lso->len = htobe32(pktlen); 4392 4393 cpl = (void *)(lso + 1); 4394 4395 txq->tso_wrs++; 4396 } else 4397 cpl = (void *)(wr + 1); 4398 4399 /* Checksum offload */ 4400 ctrl1 = 0; 4401 if (needs_l3_csum(m0) == 0) 4402 ctrl1 |= F_TXPKT_IPCSUM_DIS; 4403 if (needs_l4_csum(m0) == 0) 4404 ctrl1 |= F_TXPKT_L4CSUM_DIS; 4405 if (m0->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | 4406 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO)) 4407 txq->txcsum++; /* some hardware assistance provided */ 4408 4409 /* VLAN tag insertion */ 4410 if (needs_vlan_insertion(m0)) { 4411 ctrl1 |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 4412 txq->vlan_insertion++; 4413 } 4414 4415 /* CPL header */ 4416 cpl->ctrl0 = txq->cpl_ctrl0; 4417 cpl->pack = 0; 4418 cpl->len = htobe16(pktlen); 4419 cpl->ctrl1 = htobe64(ctrl1); 4420 4421 /* SGL */ 4422 dst = (void *)(cpl + 1); 4423 if (nsegs > 0) { 4424 4425 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx); 4426 txq->sgl_wrs++; 4427 } else { 4428 struct mbuf *m; 4429 4430 for (m = m0; m != NULL; m = m->m_next) { 4431 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len); 4432 #ifdef INVARIANTS 4433 pktlen -= m->m_len; 4434 #endif 4435 } 4436 #ifdef INVARIANTS 4437 KASSERT(pktlen == 0, ("%s: %d bytes left.", __func__, pktlen)); 4438 #endif 4439 txq->imm_wrs++; 4440 } 4441 4442 txq->txpkt_wrs++; 4443 4444 txsd = &txq->sdesc[eq->pidx]; 4445 txsd->m = m0; 4446 txsd->desc_used = ndesc; 4447 4448 return (ndesc); 4449 } 4450 4451 static int 4452 try_txpkts(struct mbuf *m, struct mbuf *n, struct txpkts *txp, u_int available) 4453 { 4454 u_int needed, nsegs1, nsegs2, l1, l2; 4455 4456 if (cannot_use_txpkts(m) || cannot_use_txpkts(n)) 4457 return (1); 4458 4459 nsegs1 = mbuf_nsegs(m); 4460 nsegs2 = mbuf_nsegs(n); 4461 if (nsegs1 + nsegs2 == 2) { 4462 txp->wr_type = 1; 4463 l1 = l2 = txpkts1_len16(); 4464 } else { 4465 txp->wr_type = 0; 4466 l1 = txpkts0_len16(nsegs1); 4467 l2 = txpkts0_len16(nsegs2); 4468 } 4469 txp->len16 = howmany(sizeof(struct fw_eth_tx_pkts_wr), 16) + l1 + l2; 4470 needed = howmany(txp->len16, EQ_ESIZE / 16); 4471 if (needed > SGE_MAX_WR_NDESC || needed > available) 4472 return (1); 4473 4474 txp->plen = m->m_pkthdr.len + n->m_pkthdr.len; 4475 if (txp->plen > 65535) 4476 return (1); 4477 4478 txp->npkt = 2; 4479 set_mbuf_len16(m, l1); 4480 set_mbuf_len16(n, l2); 4481 4482 return (0); 4483 } 4484 4485 static int 4486 add_to_txpkts(struct mbuf *m, struct txpkts *txp, u_int available) 4487 { 4488 u_int plen, len16, needed, nsegs; 4489 4490 MPASS(txp->wr_type == 0 || txp->wr_type == 1); 4491 4492 nsegs = mbuf_nsegs(m); 4493 if (needs_tso(m) || (txp->wr_type == 1 && nsegs != 1)) 4494 return (1); 4495 4496 plen = txp->plen + m->m_pkthdr.len; 4497 if (plen > 65535) 4498 return (1); 4499 4500 if (txp->wr_type == 0) 4501 len16 = txpkts0_len16(nsegs); 4502 else 4503 len16 = txpkts1_len16(); 4504 needed = howmany(txp->len16 + len16, EQ_ESIZE / 16); 4505 if (needed > SGE_MAX_WR_NDESC || needed > available) 4506 return (1); 4507 4508 txp->npkt++; 4509 txp->plen = plen; 4510 txp->len16 += len16; 4511 set_mbuf_len16(m, len16); 4512 4513 return (0); 4514 } 4515 4516 /* 4517 * Write a txpkts WR for the packets in txp to the hardware descriptors, update 4518 * the software descriptor, and advance the pidx. It is guaranteed that enough 4519 * descriptors are available. 4520 * 4521 * The return value is the # of hardware descriptors used. 4522 */ 4523 static u_int 4524 write_txpkts_wr(struct sge_txq *txq, struct fw_eth_tx_pkts_wr *wr, 4525 struct mbuf *m0, const struct txpkts *txp, u_int available) 4526 { 4527 struct sge_eq *eq = &txq->eq; 4528 struct tx_sdesc *txsd; 4529 struct cpl_tx_pkt_core *cpl; 4530 uint32_t ctrl; 4531 uint64_t ctrl1; 4532 int ndesc, checkwrap; 4533 struct mbuf *m; 4534 void *flitp; 4535 4536 TXQ_LOCK_ASSERT_OWNED(txq); 4537 MPASS(txp->npkt > 0); 4538 MPASS(txp->plen < 65536); 4539 MPASS(m0 != NULL); 4540 MPASS(m0->m_nextpkt != NULL); 4541 MPASS(txp->len16 <= howmany(SGE_MAX_WR_LEN, 16)); 4542 MPASS(available > 0 && available < eq->sidx); 4543 4544 ndesc = howmany(txp->len16, EQ_ESIZE / 16); 4545 MPASS(ndesc <= available); 4546 4547 MPASS(wr == (void *)&eq->desc[eq->pidx]); 4548 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR)); 4549 ctrl = V_FW_WR_LEN16(txp->len16); 4550 wr->equiq_to_len16 = htobe32(ctrl); 4551 wr->plen = htobe16(txp->plen); 4552 wr->npkt = txp->npkt; 4553 wr->r3 = 0; 4554 wr->type = txp->wr_type; 4555 flitp = wr + 1; 4556 4557 /* 4558 * At this point we are 16B into a hardware descriptor. If checkwrap is 4559 * set then we know the WR is going to wrap around somewhere. We'll 4560 * check for that at appropriate points. 4561 */ 4562 checkwrap = eq->sidx - ndesc < eq->pidx; 4563 for (m = m0; m != NULL; m = m->m_nextpkt) { 4564 if (txp->wr_type == 0) { 4565 struct ulp_txpkt *ulpmc; 4566 struct ulptx_idata *ulpsc; 4567 4568 /* ULP master command */ 4569 ulpmc = flitp; 4570 ulpmc->cmd_dest = htobe32(V_ULPTX_CMD(ULP_TX_PKT) | 4571 V_ULP_TXPKT_DEST(0) | V_ULP_TXPKT_FID(eq->iqid)); 4572 ulpmc->len = htobe32(mbuf_len16(m)); 4573 4574 /* ULP subcommand */ 4575 ulpsc = (void *)(ulpmc + 1); 4576 ulpsc->cmd_more = htobe32(V_ULPTX_CMD(ULP_TX_SC_IMM) | 4577 F_ULP_TX_SC_MORE); 4578 ulpsc->len = htobe32(sizeof(struct cpl_tx_pkt_core)); 4579 4580 cpl = (void *)(ulpsc + 1); 4581 if (checkwrap && 4582 (uintptr_t)cpl == (uintptr_t)&eq->desc[eq->sidx]) 4583 cpl = (void *)&eq->desc[0]; 4584 txq->txpkts0_pkts += txp->npkt; 4585 txq->txpkts0_wrs++; 4586 } else { 4587 cpl = flitp; 4588 txq->txpkts1_pkts += txp->npkt; 4589 txq->txpkts1_wrs++; 4590 } 4591 4592 /* Checksum offload */ 4593 ctrl1 = 0; 4594 if (needs_l3_csum(m) == 0) 4595 ctrl1 |= F_TXPKT_IPCSUM_DIS; 4596 if (needs_l4_csum(m) == 0) 4597 ctrl1 |= F_TXPKT_L4CSUM_DIS; 4598 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | 4599 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO)) 4600 txq->txcsum++; /* some hardware assistance provided */ 4601 4602 /* VLAN tag insertion */ 4603 if (needs_vlan_insertion(m)) { 4604 ctrl1 |= F_TXPKT_VLAN_VLD | 4605 V_TXPKT_VLAN(m->m_pkthdr.ether_vtag); 4606 txq->vlan_insertion++; 4607 } 4608 4609 /* CPL header */ 4610 cpl->ctrl0 = txq->cpl_ctrl0; 4611 cpl->pack = 0; 4612 cpl->len = htobe16(m->m_pkthdr.len); 4613 cpl->ctrl1 = htobe64(ctrl1); 4614 4615 flitp = cpl + 1; 4616 if (checkwrap && 4617 (uintptr_t)flitp == (uintptr_t)&eq->desc[eq->sidx]) 4618 flitp = (void *)&eq->desc[0]; 4619 4620 write_gl_to_txd(txq, m, (caddr_t *)(&flitp), checkwrap); 4621 4622 } 4623 4624 txsd = &txq->sdesc[eq->pidx]; 4625 txsd->m = m0; 4626 txsd->desc_used = ndesc; 4627 4628 return (ndesc); 4629 } 4630 4631 /* 4632 * If the SGL ends on an address that is not 16 byte aligned, this function will 4633 * add a 0 filled flit at the end. 4634 */ 4635 static void 4636 write_gl_to_txd(struct sge_txq *txq, struct mbuf *m, caddr_t *to, int checkwrap) 4637 { 4638 struct sge_eq *eq = &txq->eq; 4639 struct sglist *gl = txq->gl; 4640 struct sglist_seg *seg; 4641 __be64 *flitp, *wrap; 4642 struct ulptx_sgl *usgl; 4643 int i, nflits, nsegs; 4644 4645 KASSERT(((uintptr_t)(*to) & 0xf) == 0, 4646 ("%s: SGL must start at a 16 byte boundary: %p", __func__, *to)); 4647 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]); 4648 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]); 4649 4650 get_pkt_gl(m, gl); 4651 nsegs = gl->sg_nseg; 4652 MPASS(nsegs > 0); 4653 4654 nflits = (3 * (nsegs - 1)) / 2 + ((nsegs - 1) & 1) + 2; 4655 flitp = (__be64 *)(*to); 4656 wrap = (__be64 *)(&eq->desc[eq->sidx]); 4657 seg = &gl->sg_segs[0]; 4658 usgl = (void *)flitp; 4659 4660 /* 4661 * We start at a 16 byte boundary somewhere inside the tx descriptor 4662 * ring, so we're at least 16 bytes away from the status page. There is 4663 * no chance of a wrap around in the middle of usgl (which is 16 bytes). 4664 */ 4665 4666 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 4667 V_ULPTX_NSGE(nsegs)); 4668 usgl->len0 = htobe32(seg->ss_len); 4669 usgl->addr0 = htobe64(seg->ss_paddr); 4670 seg++; 4671 4672 if (checkwrap == 0 || (uintptr_t)(flitp + nflits) <= (uintptr_t)wrap) { 4673 4674 /* Won't wrap around at all */ 4675 4676 for (i = 0; i < nsegs - 1; i++, seg++) { 4677 usgl->sge[i / 2].len[i & 1] = htobe32(seg->ss_len); 4678 usgl->sge[i / 2].addr[i & 1] = htobe64(seg->ss_paddr); 4679 } 4680 if (i & 1) 4681 usgl->sge[i / 2].len[1] = htobe32(0); 4682 flitp += nflits; 4683 } else { 4684 4685 /* Will wrap somewhere in the rest of the SGL */ 4686 4687 /* 2 flits already written, write the rest flit by flit */ 4688 flitp = (void *)(usgl + 1); 4689 for (i = 0; i < nflits - 2; i++) { 4690 if (flitp == wrap) 4691 flitp = (void *)eq->desc; 4692 *flitp++ = get_flit(seg, nsegs - 1, i); 4693 } 4694 } 4695 4696 if (nflits & 1) { 4697 MPASS(((uintptr_t)flitp) & 0xf); 4698 *flitp++ = 0; 4699 } 4700 4701 MPASS((((uintptr_t)flitp) & 0xf) == 0); 4702 if (__predict_false(flitp == wrap)) 4703 *to = (void *)eq->desc; 4704 else 4705 *to = (void *)flitp; 4706 } 4707 4708 static inline void 4709 copy_to_txd(struct sge_eq *eq, caddr_t from, caddr_t *to, int len) 4710 { 4711 4712 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]); 4713 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]); 4714 4715 if (__predict_true((uintptr_t)(*to) + len <= 4716 (uintptr_t)&eq->desc[eq->sidx])) { 4717 bcopy(from, *to, len); 4718 (*to) += len; 4719 } else { 4720 int portion = (uintptr_t)&eq->desc[eq->sidx] - (uintptr_t)(*to); 4721 4722 bcopy(from, *to, portion); 4723 from += portion; 4724 portion = len - portion; /* remaining */ 4725 bcopy(from, (void *)eq->desc, portion); 4726 (*to) = (caddr_t)eq->desc + portion; 4727 } 4728 } 4729 4730 static inline void 4731 ring_eq_db(struct adapter *sc, struct sge_eq *eq, u_int n) 4732 { 4733 u_int db; 4734 4735 MPASS(n > 0); 4736 4737 db = eq->doorbells; 4738 if (n > 1) 4739 clrbit(&db, DOORBELL_WCWR); 4740 wmb(); 4741 4742 switch (ffs(db) - 1) { 4743 case DOORBELL_UDB: 4744 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n)); 4745 break; 4746 4747 case DOORBELL_WCWR: { 4748 volatile uint64_t *dst, *src; 4749 int i; 4750 4751 /* 4752 * Queues whose 128B doorbell segment fits in the page do not 4753 * use relative qid (udb_qid is always 0). Only queues with 4754 * doorbell segments can do WCWR. 4755 */ 4756 KASSERT(eq->udb_qid == 0 && n == 1, 4757 ("%s: inappropriate doorbell (0x%x, %d, %d) for eq %p", 4758 __func__, eq->doorbells, n, eq->dbidx, eq)); 4759 4760 dst = (volatile void *)((uintptr_t)eq->udb + UDBS_WR_OFFSET - 4761 UDBS_DB_OFFSET); 4762 i = eq->dbidx; 4763 src = (void *)&eq->desc[i]; 4764 while (src != (void *)&eq->desc[i + 1]) 4765 *dst++ = *src++; 4766 wmb(); 4767 break; 4768 } 4769 4770 case DOORBELL_UDBWC: 4771 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n)); 4772 wmb(); 4773 break; 4774 4775 case DOORBELL_KDB: 4776 t4_write_reg(sc, sc->sge_kdoorbell_reg, 4777 V_QID(eq->cntxt_id) | V_PIDX(n)); 4778 break; 4779 } 4780 4781 IDXINCR(eq->dbidx, n, eq->sidx); 4782 } 4783 4784 static inline u_int 4785 reclaimable_tx_desc(struct sge_eq *eq) 4786 { 4787 uint16_t hw_cidx; 4788 4789 hw_cidx = read_hw_cidx(eq); 4790 return (IDXDIFF(hw_cidx, eq->cidx, eq->sidx)); 4791 } 4792 4793 static inline u_int 4794 total_available_tx_desc(struct sge_eq *eq) 4795 { 4796 uint16_t hw_cidx, pidx; 4797 4798 hw_cidx = read_hw_cidx(eq); 4799 pidx = eq->pidx; 4800 4801 if (pidx == hw_cidx) 4802 return (eq->sidx - 1); 4803 else 4804 return (IDXDIFF(hw_cidx, pidx, eq->sidx) - 1); 4805 } 4806 4807 static inline uint16_t 4808 read_hw_cidx(struct sge_eq *eq) 4809 { 4810 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx]; 4811 uint16_t cidx = spg->cidx; /* stable snapshot */ 4812 4813 return (be16toh(cidx)); 4814 } 4815 4816 /* 4817 * Reclaim 'n' descriptors approximately. 4818 */ 4819 static u_int 4820 reclaim_tx_descs(struct sge_txq *txq, u_int n) 4821 { 4822 struct tx_sdesc *txsd; 4823 struct sge_eq *eq = &txq->eq; 4824 u_int can_reclaim, reclaimed; 4825 4826 TXQ_LOCK_ASSERT_OWNED(txq); 4827 MPASS(n > 0); 4828 4829 reclaimed = 0; 4830 can_reclaim = reclaimable_tx_desc(eq); 4831 while (can_reclaim && reclaimed < n) { 4832 int ndesc; 4833 struct mbuf *m, *nextpkt; 4834 4835 txsd = &txq->sdesc[eq->cidx]; 4836 ndesc = txsd->desc_used; 4837 4838 /* Firmware doesn't return "partial" credits. */ 4839 KASSERT(can_reclaim >= ndesc, 4840 ("%s: unexpected number of credits: %d, %d", 4841 __func__, can_reclaim, ndesc)); 4842 4843 for (m = txsd->m; m != NULL; m = nextpkt) { 4844 nextpkt = m->m_nextpkt; 4845 m->m_nextpkt = NULL; 4846 m_freem(m); 4847 } 4848 reclaimed += ndesc; 4849 can_reclaim -= ndesc; 4850 IDXINCR(eq->cidx, ndesc, eq->sidx); 4851 } 4852 4853 return (reclaimed); 4854 } 4855 4856 static void 4857 tx_reclaim(void *arg, int n) 4858 { 4859 struct sge_txq *txq = arg; 4860 struct sge_eq *eq = &txq->eq; 4861 4862 do { 4863 if (TXQ_TRYLOCK(txq) == 0) 4864 break; 4865 n = reclaim_tx_descs(txq, 32); 4866 if (eq->cidx == eq->pidx) 4867 eq->equeqidx = eq->pidx; 4868 TXQ_UNLOCK(txq); 4869 } while (n > 0); 4870 } 4871 4872 static __be64 4873 get_flit(struct sglist_seg *segs, int nsegs, int idx) 4874 { 4875 int i = (idx / 3) * 2; 4876 4877 switch (idx % 3) { 4878 case 0: { 4879 __be64 rc; 4880 4881 rc = htobe32(segs[i].ss_len); 4882 if (i + 1 < nsegs) 4883 rc |= (uint64_t)htobe32(segs[i + 1].ss_len) << 32; 4884 4885 return (rc); 4886 } 4887 case 1: 4888 return (htobe64(segs[i].ss_paddr)); 4889 case 2: 4890 return (htobe64(segs[i + 1].ss_paddr)); 4891 } 4892 4893 return (0); 4894 } 4895 4896 static void 4897 find_best_refill_source(struct adapter *sc, struct sge_fl *fl, int maxp) 4898 { 4899 int8_t zidx, hwidx, idx; 4900 uint16_t region1, region3; 4901 int spare, spare_needed, n; 4902 struct sw_zone_info *swz; 4903 struct hw_buf_info *hwb, *hwb_list = &sc->sge.hw_buf_info[0]; 4904 4905 /* 4906 * Buffer Packing: Look for PAGE_SIZE or larger zone which has a bufsize 4907 * large enough for the max payload and cluster metadata. Otherwise 4908 * settle for the largest bufsize that leaves enough room in the cluster 4909 * for metadata. 4910 * 4911 * Without buffer packing: Look for the smallest zone which has a 4912 * bufsize large enough for the max payload. Settle for the largest 4913 * bufsize available if there's nothing big enough for max payload. 4914 */ 4915 spare_needed = fl->flags & FL_BUF_PACKING ? CL_METADATA_SIZE : 0; 4916 swz = &sc->sge.sw_zone_info[0]; 4917 hwidx = -1; 4918 for (zidx = 0; zidx < SW_ZONE_SIZES; zidx++, swz++) { 4919 if (swz->size > largest_rx_cluster) { 4920 if (__predict_true(hwidx != -1)) 4921 break; 4922 4923 /* 4924 * This is a misconfiguration. largest_rx_cluster is 4925 * preventing us from finding a refill source. See 4926 * dev.t5nex.<n>.buffer_sizes to figure out why. 4927 */ 4928 device_printf(sc->dev, "largest_rx_cluster=%u leaves no" 4929 " refill source for fl %p (dma %u). Ignored.\n", 4930 largest_rx_cluster, fl, maxp); 4931 } 4932 for (idx = swz->head_hwidx; idx != -1; idx = hwb->next) { 4933 hwb = &hwb_list[idx]; 4934 spare = swz->size - hwb->size; 4935 if (spare < spare_needed) 4936 continue; 4937 4938 hwidx = idx; /* best option so far */ 4939 if (hwb->size >= maxp) { 4940 4941 if ((fl->flags & FL_BUF_PACKING) == 0) 4942 goto done; /* stop looking (not packing) */ 4943 4944 if (swz->size >= safest_rx_cluster) 4945 goto done; /* stop looking (packing) */ 4946 } 4947 break; /* keep looking, next zone */ 4948 } 4949 } 4950 done: 4951 /* A usable hwidx has been located. */ 4952 MPASS(hwidx != -1); 4953 hwb = &hwb_list[hwidx]; 4954 zidx = hwb->zidx; 4955 swz = &sc->sge.sw_zone_info[zidx]; 4956 region1 = 0; 4957 region3 = swz->size - hwb->size; 4958 4959 /* 4960 * Stay within this zone and see if there is a better match when mbuf 4961 * inlining is allowed. Remember that the hwidx's are sorted in 4962 * decreasing order of size (so in increasing order of spare area). 4963 */ 4964 for (idx = hwidx; idx != -1; idx = hwb->next) { 4965 hwb = &hwb_list[idx]; 4966 spare = swz->size - hwb->size; 4967 4968 if (allow_mbufs_in_cluster == 0 || hwb->size < maxp) 4969 break; 4970 4971 /* 4972 * Do not inline mbufs if doing so would violate the pad/pack 4973 * boundary alignment requirement. 4974 */ 4975 if (fl_pad && (MSIZE % sc->params.sge.pad_boundary) != 0) 4976 continue; 4977 if (fl->flags & FL_BUF_PACKING && 4978 (MSIZE % sc->params.sge.pack_boundary) != 0) 4979 continue; 4980 4981 if (spare < CL_METADATA_SIZE + MSIZE) 4982 continue; 4983 n = (spare - CL_METADATA_SIZE) / MSIZE; 4984 if (n > howmany(hwb->size, maxp)) 4985 break; 4986 4987 hwidx = idx; 4988 if (fl->flags & FL_BUF_PACKING) { 4989 region1 = n * MSIZE; 4990 region3 = spare - region1; 4991 } else { 4992 region1 = MSIZE; 4993 region3 = spare - region1; 4994 break; 4995 } 4996 } 4997 4998 KASSERT(zidx >= 0 && zidx < SW_ZONE_SIZES, 4999 ("%s: bad zone %d for fl %p, maxp %d", __func__, zidx, fl, maxp)); 5000 KASSERT(hwidx >= 0 && hwidx <= SGE_FLBUF_SIZES, 5001 ("%s: bad hwidx %d for fl %p, maxp %d", __func__, hwidx, fl, maxp)); 5002 KASSERT(region1 + sc->sge.hw_buf_info[hwidx].size + region3 == 5003 sc->sge.sw_zone_info[zidx].size, 5004 ("%s: bad buffer layout for fl %p, maxp %d. " 5005 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp, 5006 sc->sge.sw_zone_info[zidx].size, region1, 5007 sc->sge.hw_buf_info[hwidx].size, region3)); 5008 if (fl->flags & FL_BUF_PACKING || region1 > 0) { 5009 KASSERT(region3 >= CL_METADATA_SIZE, 5010 ("%s: no room for metadata. fl %p, maxp %d; " 5011 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp, 5012 sc->sge.sw_zone_info[zidx].size, region1, 5013 sc->sge.hw_buf_info[hwidx].size, region3)); 5014 KASSERT(region1 % MSIZE == 0, 5015 ("%s: bad mbuf region for fl %p, maxp %d. " 5016 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp, 5017 sc->sge.sw_zone_info[zidx].size, region1, 5018 sc->sge.hw_buf_info[hwidx].size, region3)); 5019 } 5020 5021 fl->cll_def.zidx = zidx; 5022 fl->cll_def.hwidx = hwidx; 5023 fl->cll_def.region1 = region1; 5024 fl->cll_def.region3 = region3; 5025 } 5026 5027 static void 5028 find_safe_refill_source(struct adapter *sc, struct sge_fl *fl) 5029 { 5030 struct sge *s = &sc->sge; 5031 struct hw_buf_info *hwb; 5032 struct sw_zone_info *swz; 5033 int spare; 5034 int8_t hwidx; 5035 5036 if (fl->flags & FL_BUF_PACKING) 5037 hwidx = s->safe_hwidx2; /* with room for metadata */ 5038 else if (allow_mbufs_in_cluster && s->safe_hwidx2 != -1) { 5039 hwidx = s->safe_hwidx2; 5040 hwb = &s->hw_buf_info[hwidx]; 5041 swz = &s->sw_zone_info[hwb->zidx]; 5042 spare = swz->size - hwb->size; 5043 5044 /* no good if there isn't room for an mbuf as well */ 5045 if (spare < CL_METADATA_SIZE + MSIZE) 5046 hwidx = s->safe_hwidx1; 5047 } else 5048 hwidx = s->safe_hwidx1; 5049 5050 if (hwidx == -1) { 5051 /* No fallback source */ 5052 fl->cll_alt.hwidx = -1; 5053 fl->cll_alt.zidx = -1; 5054 5055 return; 5056 } 5057 5058 hwb = &s->hw_buf_info[hwidx]; 5059 swz = &s->sw_zone_info[hwb->zidx]; 5060 spare = swz->size - hwb->size; 5061 fl->cll_alt.hwidx = hwidx; 5062 fl->cll_alt.zidx = hwb->zidx; 5063 if (allow_mbufs_in_cluster && 5064 (fl_pad == 0 || (MSIZE % sc->params.sge.pad_boundary) == 0)) 5065 fl->cll_alt.region1 = ((spare - CL_METADATA_SIZE) / MSIZE) * MSIZE; 5066 else 5067 fl->cll_alt.region1 = 0; 5068 fl->cll_alt.region3 = spare - fl->cll_alt.region1; 5069 } 5070 5071 static void 5072 add_fl_to_sfl(struct adapter *sc, struct sge_fl *fl) 5073 { 5074 mtx_lock(&sc->sfl_lock); 5075 FL_LOCK(fl); 5076 if ((fl->flags & FL_DOOMED) == 0) { 5077 fl->flags |= FL_STARVING; 5078 TAILQ_INSERT_TAIL(&sc->sfl, fl, link); 5079 callout_reset(&sc->sfl_callout, hz / 5, refill_sfl, sc); 5080 } 5081 FL_UNLOCK(fl); 5082 mtx_unlock(&sc->sfl_lock); 5083 } 5084 5085 static void 5086 handle_wrq_egr_update(struct adapter *sc, struct sge_eq *eq) 5087 { 5088 struct sge_wrq *wrq = (void *)eq; 5089 5090 atomic_readandclear_int(&eq->equiq); 5091 taskqueue_enqueue(sc->tq[eq->tx_chan], &wrq->wrq_tx_task); 5092 } 5093 5094 static void 5095 handle_eth_egr_update(struct adapter *sc, struct sge_eq *eq) 5096 { 5097 struct sge_txq *txq = (void *)eq; 5098 5099 MPASS((eq->flags & EQ_TYPEMASK) == EQ_ETH); 5100 5101 atomic_readandclear_int(&eq->equiq); 5102 mp_ring_check_drainage(txq->r, 0); 5103 taskqueue_enqueue(sc->tq[eq->tx_chan], &txq->tx_reclaim_task); 5104 } 5105 5106 static int 5107 handle_sge_egr_update(struct sge_iq *iq, const struct rss_header *rss, 5108 struct mbuf *m) 5109 { 5110 const struct cpl_sge_egr_update *cpl = (const void *)(rss + 1); 5111 unsigned int qid = G_EGR_QID(ntohl(cpl->opcode_qid)); 5112 struct adapter *sc = iq->adapter; 5113 struct sge *s = &sc->sge; 5114 struct sge_eq *eq; 5115 static void (*h[])(struct adapter *, struct sge_eq *) = {NULL, 5116 &handle_wrq_egr_update, &handle_eth_egr_update, 5117 &handle_wrq_egr_update}; 5118 5119 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 5120 rss->opcode)); 5121 5122 eq = s->eqmap[qid - s->eq_start - s->eq_base]; 5123 (*h[eq->flags & EQ_TYPEMASK])(sc, eq); 5124 5125 return (0); 5126 } 5127 5128 /* handle_fw_msg works for both fw4_msg and fw6_msg because this is valid */ 5129 CTASSERT(offsetof(struct cpl_fw4_msg, data) == \ 5130 offsetof(struct cpl_fw6_msg, data)); 5131 5132 static int 5133 handle_fw_msg(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 5134 { 5135 struct adapter *sc = iq->adapter; 5136 const struct cpl_fw6_msg *cpl = (const void *)(rss + 1); 5137 5138 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 5139 rss->opcode)); 5140 5141 if (cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL) { 5142 const struct rss_header *rss2; 5143 5144 rss2 = (const struct rss_header *)&cpl->data[0]; 5145 return (t4_cpl_handler[rss2->opcode](iq, rss2, m)); 5146 } 5147 5148 return (t4_fw_msg_handler[cpl->type](sc, &cpl->data[0])); 5149 } 5150 5151 /** 5152 * t4_handle_wrerr_rpl - process a FW work request error message 5153 * @adap: the adapter 5154 * @rpl: start of the FW message 5155 */ 5156 static int 5157 t4_handle_wrerr_rpl(struct adapter *adap, const __be64 *rpl) 5158 { 5159 u8 opcode = *(const u8 *)rpl; 5160 const struct fw_error_cmd *e = (const void *)rpl; 5161 unsigned int i; 5162 5163 if (opcode != FW_ERROR_CMD) { 5164 log(LOG_ERR, 5165 "%s: Received WRERR_RPL message with opcode %#x\n", 5166 device_get_nameunit(adap->dev), opcode); 5167 return (EINVAL); 5168 } 5169 log(LOG_ERR, "%s: FW_ERROR (%s) ", device_get_nameunit(adap->dev), 5170 G_FW_ERROR_CMD_FATAL(be32toh(e->op_to_type)) ? "fatal" : 5171 "non-fatal"); 5172 switch (G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type))) { 5173 case FW_ERROR_TYPE_EXCEPTION: 5174 log(LOG_ERR, "exception info:\n"); 5175 for (i = 0; i < nitems(e->u.exception.info); i++) 5176 log(LOG_ERR, "%s%08x", i == 0 ? "\t" : " ", 5177 be32toh(e->u.exception.info[i])); 5178 log(LOG_ERR, "\n"); 5179 break; 5180 case FW_ERROR_TYPE_HWMODULE: 5181 log(LOG_ERR, "HW module regaddr %08x regval %08x\n", 5182 be32toh(e->u.hwmodule.regaddr), 5183 be32toh(e->u.hwmodule.regval)); 5184 break; 5185 case FW_ERROR_TYPE_WR: 5186 log(LOG_ERR, "WR cidx %d PF %d VF %d eqid %d hdr:\n", 5187 be16toh(e->u.wr.cidx), 5188 G_FW_ERROR_CMD_PFN(be16toh(e->u.wr.pfn_vfn)), 5189 G_FW_ERROR_CMD_VFN(be16toh(e->u.wr.pfn_vfn)), 5190 be32toh(e->u.wr.eqid)); 5191 for (i = 0; i < nitems(e->u.wr.wrhdr); i++) 5192 log(LOG_ERR, "%s%02x", i == 0 ? "\t" : " ", 5193 e->u.wr.wrhdr[i]); 5194 log(LOG_ERR, "\n"); 5195 break; 5196 case FW_ERROR_TYPE_ACL: 5197 log(LOG_ERR, "ACL cidx %d PF %d VF %d eqid %d %s", 5198 be16toh(e->u.acl.cidx), 5199 G_FW_ERROR_CMD_PFN(be16toh(e->u.acl.pfn_vfn)), 5200 G_FW_ERROR_CMD_VFN(be16toh(e->u.acl.pfn_vfn)), 5201 be32toh(e->u.acl.eqid), 5202 G_FW_ERROR_CMD_MV(be16toh(e->u.acl.mv_pkd)) ? "vlanid" : 5203 "MAC"); 5204 for (i = 0; i < nitems(e->u.acl.val); i++) 5205 log(LOG_ERR, " %02x", e->u.acl.val[i]); 5206 log(LOG_ERR, "\n"); 5207 break; 5208 default: 5209 log(LOG_ERR, "type %#x\n", 5210 G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type))); 5211 return (EINVAL); 5212 } 5213 return (0); 5214 } 5215 5216 static int 5217 sysctl_uint16(SYSCTL_HANDLER_ARGS) 5218 { 5219 uint16_t *id = arg1; 5220 int i = *id; 5221 5222 return sysctl_handle_int(oidp, &i, 0, req); 5223 } 5224 5225 static int 5226 sysctl_bufsizes(SYSCTL_HANDLER_ARGS) 5227 { 5228 struct sge *s = arg1; 5229 struct hw_buf_info *hwb = &s->hw_buf_info[0]; 5230 struct sw_zone_info *swz = &s->sw_zone_info[0]; 5231 int i, rc; 5232 struct sbuf sb; 5233 char c; 5234 5235 sbuf_new(&sb, NULL, 32, SBUF_AUTOEXTEND); 5236 for (i = 0; i < SGE_FLBUF_SIZES; i++, hwb++) { 5237 if (hwb->zidx >= 0 && swz[hwb->zidx].size <= largest_rx_cluster) 5238 c = '*'; 5239 else 5240 c = '\0'; 5241 5242 sbuf_printf(&sb, "%u%c ", hwb->size, c); 5243 } 5244 sbuf_trim(&sb); 5245 sbuf_finish(&sb); 5246 rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req); 5247 sbuf_delete(&sb); 5248 return (rc); 5249 } 5250 5251 static int 5252 sysctl_tc(SYSCTL_HANDLER_ARGS) 5253 { 5254 struct vi_info *vi = arg1; 5255 struct port_info *pi; 5256 struct adapter *sc; 5257 struct sge_txq *txq; 5258 struct tx_cl_rl_params *tc; 5259 int qidx = arg2, rc, tc_idx; 5260 uint32_t fw_queue, fw_class; 5261 5262 MPASS(qidx >= 0 && qidx < vi->ntxq); 5263 pi = vi->pi; 5264 sc = pi->adapter; 5265 txq = &sc->sge.txq[vi->first_txq + qidx]; 5266 5267 tc_idx = txq->tc_idx; 5268 rc = sysctl_handle_int(oidp, &tc_idx, 0, req); 5269 if (rc != 0 || req->newptr == NULL) 5270 return (rc); 5271 5272 if (sc->flags & IS_VF) 5273 return (EPERM); 5274 5275 /* Note that -1 is legitimate input (it means unbind). */ 5276 if (tc_idx < -1 || tc_idx >= sc->chip_params->nsched_cls) 5277 return (EINVAL); 5278 5279 mtx_lock(&sc->tc_lock); 5280 if (tc_idx == txq->tc_idx) { 5281 rc = 0; /* No change, nothing to do. */ 5282 goto done; 5283 } 5284 5285 fw_queue = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 5286 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH) | 5287 V_FW_PARAMS_PARAM_YZ(txq->eq.cntxt_id); 5288 5289 if (tc_idx == -1) 5290 fw_class = 0xffffffff; /* Unbind. */ 5291 else { 5292 /* 5293 * Bind to a different class. 5294 */ 5295 tc = &pi->sched_params->cl_rl[tc_idx]; 5296 if (tc->flags & TX_CLRL_ERROR) { 5297 /* Previous attempt to set the cl-rl params failed. */ 5298 rc = EIO; 5299 goto done; 5300 } else { 5301 /* 5302 * Ok to proceed. Place a reference on the new class 5303 * while still holding on to the reference on the 5304 * previous class, if any. 5305 */ 5306 fw_class = tc_idx; 5307 tc->refcount++; 5308 } 5309 } 5310 mtx_unlock(&sc->tc_lock); 5311 5312 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4stc"); 5313 if (rc) 5314 return (rc); 5315 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &fw_queue, &fw_class); 5316 end_synchronized_op(sc, 0); 5317 5318 mtx_lock(&sc->tc_lock); 5319 if (rc == 0) { 5320 if (txq->tc_idx != -1) { 5321 tc = &pi->sched_params->cl_rl[txq->tc_idx]; 5322 MPASS(tc->refcount > 0); 5323 tc->refcount--; 5324 } 5325 txq->tc_idx = tc_idx; 5326 } else if (tc_idx != -1) { 5327 tc = &pi->sched_params->cl_rl[tc_idx]; 5328 MPASS(tc->refcount > 0); 5329 tc->refcount--; 5330 } 5331 done: 5332 mtx_unlock(&sc->tc_lock); 5333 return (rc); 5334 } 5335