1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2011, 2025 Chelsio Communications. 5 * Written by: Navdeep Parhar <np@FreeBSD.org> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 #include "opt_inet.h" 31 #include "opt_inet6.h" 32 #include "opt_kern_tls.h" 33 #include "opt_ratelimit.h" 34 35 #include <sys/types.h> 36 #include <sys/eventhandler.h> 37 #include <sys/mbuf.h> 38 #include <sys/socket.h> 39 #include <sys/kernel.h> 40 #include <sys/ktls.h> 41 #include <sys/malloc.h> 42 #include <sys/msan.h> 43 #include <sys/queue.h> 44 #include <sys/sbuf.h> 45 #include <sys/taskqueue.h> 46 #include <sys/time.h> 47 #include <sys/sglist.h> 48 #include <sys/sysctl.h> 49 #include <sys/smp.h> 50 #include <sys/socketvar.h> 51 #include <sys/counter.h> 52 #include <net/bpf.h> 53 #include <net/ethernet.h> 54 #include <net/if.h> 55 #include <net/if_vlan_var.h> 56 #include <net/if_vxlan.h> 57 #include <netinet/in.h> 58 #include <netinet/ip.h> 59 #include <netinet/ip6.h> 60 #include <netinet/tcp.h> 61 #include <netinet/udp.h> 62 #include <machine/in_cksum.h> 63 #include <machine/md_var.h> 64 #include <vm/vm.h> 65 #include <vm/pmap.h> 66 #ifdef DEV_NETMAP 67 #include <machine/bus.h> 68 #include <sys/selinfo.h> 69 #include <net/if_var.h> 70 #include <net/netmap.h> 71 #include <dev/netmap/netmap_kern.h> 72 #endif 73 74 #include "common/common.h" 75 #include "common/t4_regs.h" 76 #include "common/t4_regs_values.h" 77 #include "common/t4_msg.h" 78 #include "t4_l2t.h" 79 #include "t4_mp_ring.h" 80 81 #define RX_COPY_THRESHOLD MINCLSIZE 82 83 /* 84 * Ethernet frames are DMA'd at this byte offset into the freelist buffer. 85 * 0-7 are valid values. 86 */ 87 static int fl_pktshift = 0; 88 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pktshift, CTLFLAG_RDTUN, &fl_pktshift, 0, 89 "payload DMA offset in rx buffer (bytes)"); 90 91 /* 92 * Pad ethernet payload up to this boundary. 93 * -1: driver should figure out a good value. 94 * 0: disable padding. 95 * Any power of 2 from 32 to 4096 (both inclusive) is also a valid value. 96 */ 97 int fl_pad = -1; 98 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pad, CTLFLAG_RDTUN, &fl_pad, 0, 99 "payload pad boundary (bytes)"); 100 101 /* 102 * Status page length. 103 * -1: driver should figure out a good value. 104 * 64 or 128 are the only other valid values. 105 */ 106 static int spg_len = -1; 107 SYSCTL_INT(_hw_cxgbe, OID_AUTO, spg_len, CTLFLAG_RDTUN, &spg_len, 0, 108 "status page size (bytes)"); 109 110 /* 111 * Congestion drops. 112 * -1: no congestion feedback (not recommended). 113 * 0: backpressure the channel instead of dropping packets right away. 114 * 1: no backpressure, drop packets for the congested queue immediately. 115 * 2: both backpressure and drop. 116 */ 117 static int cong_drop = 0; 118 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cong_drop, CTLFLAG_RDTUN, &cong_drop, 0, 119 "Congestion control for NIC RX queues (0 = backpressure, 1 = drop, 2 = both"); 120 #ifdef TCP_OFFLOAD 121 static int ofld_cong_drop = 0; 122 SYSCTL_INT(_hw_cxgbe, OID_AUTO, ofld_cong_drop, CTLFLAG_RDTUN, &ofld_cong_drop, 0, 123 "Congestion control for TOE RX queues (0 = backpressure, 1 = drop, 2 = both"); 124 #endif 125 126 /* 127 * Deliver multiple frames in the same free list buffer if they fit. 128 * -1: let the driver decide whether to enable buffer packing or not. 129 * 0: disable buffer packing. 130 * 1: enable buffer packing. 131 */ 132 static int buffer_packing = -1; 133 SYSCTL_INT(_hw_cxgbe, OID_AUTO, buffer_packing, CTLFLAG_RDTUN, &buffer_packing, 134 0, "Enable buffer packing"); 135 136 /* 137 * Start next frame in a packed buffer at this boundary. 138 * -1: driver should figure out a good value. 139 * T4: driver will ignore this and use the same value as fl_pad above. 140 * T5: 16, or a power of 2 from 64 to 4096 (both inclusive) is a valid value. 141 */ 142 static int fl_pack = -1; 143 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pack, CTLFLAG_RDTUN, &fl_pack, 0, 144 "payload pack boundary (bytes)"); 145 146 /* 147 * Largest rx cluster size that the driver is allowed to allocate. 148 */ 149 static int largest_rx_cluster = MJUM16BYTES; 150 SYSCTL_INT(_hw_cxgbe, OID_AUTO, largest_rx_cluster, CTLFLAG_RDTUN, 151 &largest_rx_cluster, 0, "Largest rx cluster (bytes)"); 152 153 /* 154 * Size of cluster allocation that's most likely to succeed. The driver will 155 * fall back to this size if it fails to allocate clusters larger than this. 156 */ 157 static int safest_rx_cluster = PAGE_SIZE; 158 SYSCTL_INT(_hw_cxgbe, OID_AUTO, safest_rx_cluster, CTLFLAG_RDTUN, 159 &safest_rx_cluster, 0, "Safe rx cluster (bytes)"); 160 161 #ifdef RATELIMIT 162 /* 163 * Knob to control TCP timestamp rewriting, and the granularity of the tick used 164 * for rewriting. -1 and 0-3 are all valid values. 165 * -1: hardware should leave the TCP timestamps alone. 166 * 0: 1ms 167 * 1: 100us 168 * 2: 10us 169 * 3: 1us 170 */ 171 static int tsclk = -1; 172 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tsclk, CTLFLAG_RDTUN, &tsclk, 0, 173 "Control TCP timestamp rewriting when using pacing"); 174 175 static int eo_max_backlog = 1024 * 1024; 176 SYSCTL_INT(_hw_cxgbe, OID_AUTO, eo_max_backlog, CTLFLAG_RDTUN, &eo_max_backlog, 177 0, "Maximum backlog of ratelimited data per flow"); 178 #endif 179 180 /* 181 * The interrupt holdoff timers are multiplied by this value on T6+. 182 * 1 and 3-17 (both inclusive) are legal values. 183 */ 184 static int tscale = 1; 185 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tscale, CTLFLAG_RDTUN, &tscale, 0, 186 "Interrupt holdoff timer scale on T6+"); 187 188 /* 189 * Number of LRO entries in the lro_ctrl structure per rx queue. 190 */ 191 static int lro_entries = TCP_LRO_ENTRIES; 192 SYSCTL_INT(_hw_cxgbe, OID_AUTO, lro_entries, CTLFLAG_RDTUN, &lro_entries, 0, 193 "Number of LRO entries per RX queue"); 194 195 /* 196 * This enables presorting of frames before they're fed into tcp_lro_rx. 197 */ 198 static int lro_mbufs = 0; 199 SYSCTL_INT(_hw_cxgbe, OID_AUTO, lro_mbufs, CTLFLAG_RDTUN, &lro_mbufs, 0, 200 "Enable presorting of LRO frames"); 201 202 static counter_u64_t pullups; 203 SYSCTL_COUNTER_U64(_hw_cxgbe, OID_AUTO, pullups, CTLFLAG_RD, &pullups, 204 "Number of mbuf pullups performed"); 205 206 static counter_u64_t defrags; 207 SYSCTL_COUNTER_U64(_hw_cxgbe, OID_AUTO, defrags, CTLFLAG_RD, &defrags, 208 "Number of mbuf defrags performed"); 209 210 static int t4_tx_coalesce = 1; 211 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tx_coalesce, CTLFLAG_RWTUN, &t4_tx_coalesce, 0, 212 "tx coalescing allowed"); 213 214 /* 215 * The driver will make aggressive attempts at tx coalescing if it sees these 216 * many packets eligible for coalescing in quick succession, with no more than 217 * the specified gap in between the eth_tx calls that delivered the packets. 218 */ 219 static int t4_tx_coalesce_pkts = 32; 220 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tx_coalesce_pkts, CTLFLAG_RWTUN, 221 &t4_tx_coalesce_pkts, 0, 222 "# of consecutive packets (1 - 255) that will trigger tx coalescing"); 223 static int t4_tx_coalesce_gap = 5; 224 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tx_coalesce_gap, CTLFLAG_RWTUN, 225 &t4_tx_coalesce_gap, 0, "tx gap (in microseconds)"); 226 227 static int service_iq(struct sge_iq *, int); 228 static int service_iq_fl(struct sge_iq *, int); 229 static struct mbuf *get_fl_payload(struct adapter *, struct sge_fl *, uint32_t); 230 static int eth_rx(struct adapter *, struct sge_rxq *, const struct iq_desc *, 231 u_int); 232 static inline void init_iq(struct sge_iq *, struct adapter *, int, int, int, 233 int, int, int); 234 static inline void init_fl(struct adapter *, struct sge_fl *, int, int, char *); 235 static inline void init_eq(struct adapter *, struct sge_eq *, int, int, uint8_t, 236 struct sge_iq *, char *); 237 static int alloc_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *, 238 struct sysctl_ctx_list *, struct sysctl_oid *); 239 static void free_iq_fl(struct adapter *, struct sge_iq *, struct sge_fl *); 240 static void add_iq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *, 241 struct sge_iq *); 242 static void add_fl_sysctls(struct adapter *, struct sysctl_ctx_list *, 243 struct sysctl_oid *, struct sge_fl *); 244 static int alloc_iq_fl_hwq(struct vi_info *, struct sge_iq *, struct sge_fl *); 245 static int free_iq_fl_hwq(struct adapter *, struct sge_iq *, struct sge_fl *); 246 static int alloc_fwq(struct adapter *); 247 static void free_fwq(struct adapter *); 248 static int alloc_ctrlq(struct adapter *, int); 249 static void free_ctrlq(struct adapter *, int); 250 static int alloc_rxq(struct vi_info *, struct sge_rxq *, int, int, int); 251 static void free_rxq(struct vi_info *, struct sge_rxq *); 252 static void add_rxq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *, 253 struct sge_rxq *); 254 #ifdef TCP_OFFLOAD 255 static int alloc_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *, int, int, 256 int); 257 static void free_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *); 258 static void add_ofld_rxq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *, 259 struct sge_ofld_rxq *); 260 #endif 261 static int ctrl_eq_alloc(struct adapter *, struct sge_eq *, int); 262 static int eth_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *, 263 int); 264 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 265 static int ofld_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *, 266 int); 267 #endif 268 static int alloc_eq(struct adapter *, struct sge_eq *, struct sysctl_ctx_list *, 269 struct sysctl_oid *); 270 static void free_eq(struct adapter *, struct sge_eq *); 271 static void add_eq_sysctls(struct adapter *, struct sysctl_ctx_list *, 272 struct sysctl_oid *, struct sge_eq *); 273 static int alloc_eq_hwq(struct adapter *, struct vi_info *, struct sge_eq *, 274 int); 275 static int free_eq_hwq(struct adapter *, struct vi_info *, struct sge_eq *); 276 static int alloc_wrq(struct adapter *, struct vi_info *, struct sge_wrq *, 277 struct sysctl_ctx_list *, struct sysctl_oid *); 278 static void free_wrq(struct adapter *, struct sge_wrq *); 279 static void add_wrq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *, 280 struct sge_wrq *); 281 static int alloc_txq(struct vi_info *, struct sge_txq *, int); 282 static void free_txq(struct vi_info *, struct sge_txq *); 283 static void add_txq_sysctls(struct vi_info *, struct sysctl_ctx_list *, 284 struct sysctl_oid *, struct sge_txq *); 285 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 286 static int alloc_ofld_txq(struct vi_info *, struct sge_ofld_txq *, int); 287 static void free_ofld_txq(struct vi_info *, struct sge_ofld_txq *); 288 static void add_ofld_txq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *, 289 struct sge_ofld_txq *); 290 #endif 291 static void oneseg_dma_callback(void *, bus_dma_segment_t *, int, int); 292 static inline void ring_fl_db(struct adapter *, struct sge_fl *); 293 static int refill_fl(struct adapter *, struct sge_fl *, int); 294 static void refill_sfl(void *); 295 static int find_refill_source(struct adapter *, int, bool); 296 static void add_fl_to_sfl(struct adapter *, struct sge_fl *); 297 298 static inline void get_pkt_gl(struct mbuf *, struct sglist *); 299 static inline u_int txpkt_len16(u_int, const u_int); 300 static inline u_int txpkt_vm_len16(u_int, const u_int); 301 static inline void calculate_mbuf_len16(struct mbuf *, bool); 302 static inline u_int txpkts0_len16(u_int); 303 static inline u_int txpkts1_len16(void); 304 static u_int write_raw_wr(struct sge_txq *, void *, struct mbuf *, u_int); 305 static u_int write_txpkt_wr(struct adapter *, struct sge_txq *, struct mbuf *, 306 u_int); 307 static u_int write_txpkt_vm_wr(struct adapter *, struct sge_txq *, 308 struct mbuf *); 309 static int add_to_txpkts_vf(struct adapter *, struct sge_txq *, struct mbuf *, 310 int, bool *); 311 static int add_to_txpkts_pf(struct adapter *, struct sge_txq *, struct mbuf *, 312 int, bool *); 313 static u_int write_txpkts_wr(struct adapter *, struct sge_txq *); 314 static u_int write_txpkts_vm_wr(struct adapter *, struct sge_txq *); 315 static void write_gl_to_txd(struct sge_txq *, struct mbuf *, caddr_t *, int); 316 static inline void copy_to_txd(struct sge_eq *, caddr_t, caddr_t *, int); 317 static inline void ring_eq_db(struct adapter *, struct sge_eq *, u_int); 318 static inline uint16_t read_hw_cidx(struct sge_eq *); 319 static inline u_int reclaimable_tx_desc(struct sge_eq *); 320 static inline u_int total_available_tx_desc(struct sge_eq *); 321 static u_int reclaim_tx_descs(struct sge_txq *, u_int); 322 static void tx_reclaim(void *, int); 323 static __be64 get_flit(struct sglist_seg *, int, int); 324 static int handle_sge_egr_update(struct sge_iq *, const struct rss_header *, 325 struct mbuf *); 326 static int handle_fw_msg(struct sge_iq *, const struct rss_header *, 327 struct mbuf *); 328 static int t4_handle_wrerr_rpl(struct adapter *, const __be64 *); 329 static void wrq_tx_drain(void *, int); 330 static void drain_wrq_wr_list(struct adapter *, struct sge_wrq *); 331 332 static int sysctl_bufsizes(SYSCTL_HANDLER_ARGS); 333 #ifdef RATELIMIT 334 static int ethofld_fw4_ack(struct sge_iq *, const struct rss_header *, 335 struct mbuf *); 336 #if defined(INET) || defined(INET6) 337 static inline u_int txpkt_eo_len16(u_int, u_int, u_int); 338 static int ethofld_transmit(if_t, struct mbuf *); 339 #endif 340 #endif 341 342 static counter_u64_t extfree_refs; 343 static counter_u64_t extfree_rels; 344 345 an_handler_t t4_an_handler; 346 fw_msg_handler_t t4_fw_msg_handler[NUM_FW6_TYPES]; 347 cpl_handler_t t4_cpl_handler[NUM_CPL_CMDS]; 348 cpl_handler_t set_tcb_rpl_handlers[NUM_CPL_COOKIES]; 349 cpl_handler_t l2t_write_rpl_handlers[NUM_CPL_COOKIES]; 350 cpl_handler_t act_open_rpl_handlers[NUM_CPL_COOKIES]; 351 cpl_handler_t abort_rpl_rss_handlers[NUM_CPL_COOKIES]; 352 cpl_handler_t fw4_ack_handlers[NUM_CPL_COOKIES]; 353 cpl_handler_t fw6_pld_handlers[NUM_CPL_FW6_COOKIES]; 354 355 void 356 t4_register_an_handler(an_handler_t h) 357 { 358 uintptr_t *loc; 359 360 MPASS(h == NULL || t4_an_handler == NULL); 361 362 loc = (uintptr_t *)&t4_an_handler; 363 atomic_store_rel_ptr(loc, (uintptr_t)h); 364 } 365 366 void 367 t4_register_fw_msg_handler(int type, fw_msg_handler_t h) 368 { 369 uintptr_t *loc; 370 371 MPASS(type < nitems(t4_fw_msg_handler)); 372 MPASS(h == NULL || t4_fw_msg_handler[type] == NULL); 373 /* 374 * These are dispatched by the handler for FW{4|6}_CPL_MSG using the CPL 375 * handler dispatch table. Reject any attempt to install a handler for 376 * this subtype. 377 */ 378 MPASS(type != FW_TYPE_RSSCPL); 379 MPASS(type != FW6_TYPE_RSSCPL); 380 381 loc = (uintptr_t *)&t4_fw_msg_handler[type]; 382 atomic_store_rel_ptr(loc, (uintptr_t)h); 383 } 384 385 void 386 t4_register_cpl_handler(int opcode, cpl_handler_t h) 387 { 388 uintptr_t *loc; 389 390 MPASS(opcode < nitems(t4_cpl_handler)); 391 MPASS(h == NULL || t4_cpl_handler[opcode] == NULL); 392 393 loc = (uintptr_t *)&t4_cpl_handler[opcode]; 394 atomic_store_rel_ptr(loc, (uintptr_t)h); 395 } 396 397 static int 398 set_tcb_rpl_handler(struct sge_iq *iq, const struct rss_header *rss, 399 struct mbuf *m) 400 { 401 const struct cpl_set_tcb_rpl *cpl = (const void *)(rss + 1); 402 u_int tid; 403 int cookie; 404 405 MPASS(m == NULL); 406 407 tid = GET_TID(cpl); 408 if (is_hpftid(iq->adapter, tid) || is_ftid(iq->adapter, tid)) { 409 /* 410 * The return code for filter-write is put in the CPL cookie so 411 * we have to rely on the hardware tid (is_ftid) to determine 412 * that this is a response to a filter. 413 */ 414 cookie = CPL_COOKIE_FILTER; 415 } else { 416 cookie = G_COOKIE(cpl->cookie); 417 } 418 MPASS(cookie > CPL_COOKIE_RESERVED); 419 MPASS(cookie < nitems(set_tcb_rpl_handlers)); 420 421 return (set_tcb_rpl_handlers[cookie](iq, rss, m)); 422 } 423 424 static int 425 l2t_write_rpl_handler(struct sge_iq *iq, const struct rss_header *rss, 426 struct mbuf *m) 427 { 428 const struct cpl_l2t_write_rpl *rpl = (const void *)(rss + 1); 429 unsigned int cookie; 430 431 MPASS(m == NULL); 432 433 cookie = GET_TID(rpl) & F_SYNC_WR ? CPL_COOKIE_TOM : CPL_COOKIE_FILTER; 434 return (l2t_write_rpl_handlers[cookie](iq, rss, m)); 435 } 436 437 static int 438 act_open_rpl_handler(struct sge_iq *iq, const struct rss_header *rss, 439 struct mbuf *m) 440 { 441 const struct cpl_act_open_rpl *cpl = (const void *)(rss + 1); 442 u_int cookie = G_TID_COOKIE(G_AOPEN_ATID(be32toh(cpl->atid_status))); 443 444 MPASS(m == NULL); 445 MPASS(cookie != CPL_COOKIE_RESERVED); 446 447 return (act_open_rpl_handlers[cookie](iq, rss, m)); 448 } 449 450 static int 451 abort_rpl_rss_handler(struct sge_iq *iq, const struct rss_header *rss, 452 struct mbuf *m) 453 { 454 struct adapter *sc = iq->adapter; 455 u_int cookie; 456 457 MPASS(m == NULL); 458 if (is_hashfilter(sc)) 459 cookie = CPL_COOKIE_HASHFILTER; 460 else 461 cookie = CPL_COOKIE_TOM; 462 463 return (abort_rpl_rss_handlers[cookie](iq, rss, m)); 464 } 465 466 static int 467 fw4_ack_handler(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 468 { 469 struct adapter *sc = iq->adapter; 470 const struct cpl_fw4_ack *cpl = (const void *)(rss + 1); 471 unsigned int tid = G_CPL_FW4_ACK_FLOWID(be32toh(OPCODE_TID(cpl))); 472 u_int cookie; 473 474 MPASS(m == NULL); 475 if (is_etid(sc, tid)) 476 cookie = CPL_COOKIE_ETHOFLD; 477 else 478 cookie = CPL_COOKIE_TOM; 479 480 return (fw4_ack_handlers[cookie](iq, rss, m)); 481 } 482 483 static int 484 fw6_pld_handler(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 485 { 486 const struct cpl_fw6_pld *cpl; 487 uint64_t cookie; 488 489 if (m != NULL) 490 cpl = mtod(m, const void *); 491 else 492 cpl = (const void *)(rss + 1); 493 cookie = be64toh(cpl->data[1]) & CPL_FW6_COOKIE_MASK; 494 495 return (fw6_pld_handlers[cookie](iq, rss, m)); 496 } 497 498 static void 499 t4_init_shared_cpl_handlers(void) 500 { 501 502 t4_register_cpl_handler(CPL_SET_TCB_RPL, set_tcb_rpl_handler); 503 t4_register_cpl_handler(CPL_L2T_WRITE_RPL, l2t_write_rpl_handler); 504 t4_register_cpl_handler(CPL_ACT_OPEN_RPL, act_open_rpl_handler); 505 t4_register_cpl_handler(CPL_ABORT_RPL_RSS, abort_rpl_rss_handler); 506 t4_register_cpl_handler(CPL_FW4_ACK, fw4_ack_handler); 507 t4_register_cpl_handler(CPL_FW6_PLD, fw6_pld_handler); 508 } 509 510 void 511 t4_register_shared_cpl_handler(int opcode, cpl_handler_t h, int cookie) 512 { 513 uintptr_t *loc; 514 515 MPASS(opcode < nitems(t4_cpl_handler)); 516 if (opcode == CPL_FW6_PLD) { 517 MPASS(cookie < NUM_CPL_FW6_COOKIES); 518 } else { 519 MPASS(cookie > CPL_COOKIE_RESERVED); 520 MPASS(cookie < NUM_CPL_COOKIES); 521 } 522 MPASS(t4_cpl_handler[opcode] != NULL); 523 524 switch (opcode) { 525 case CPL_SET_TCB_RPL: 526 loc = (uintptr_t *)&set_tcb_rpl_handlers[cookie]; 527 break; 528 case CPL_L2T_WRITE_RPL: 529 loc = (uintptr_t *)&l2t_write_rpl_handlers[cookie]; 530 break; 531 case CPL_ACT_OPEN_RPL: 532 loc = (uintptr_t *)&act_open_rpl_handlers[cookie]; 533 break; 534 case CPL_ABORT_RPL_RSS: 535 loc = (uintptr_t *)&abort_rpl_rss_handlers[cookie]; 536 break; 537 case CPL_FW4_ACK: 538 loc = (uintptr_t *)&fw4_ack_handlers[cookie]; 539 break; 540 case CPL_FW6_PLD: 541 loc = (uintptr_t *)&fw6_pld_handlers[cookie]; 542 break; 543 default: 544 MPASS(0); 545 return; 546 } 547 MPASS(h == NULL || *loc == (uintptr_t)NULL); 548 atomic_store_rel_ptr(loc, (uintptr_t)h); 549 } 550 551 /* 552 * Called on MOD_LOAD. Validates and calculates the SGE tunables. 553 */ 554 void 555 t4_sge_modload(void) 556 { 557 558 if (fl_pktshift < 0 || fl_pktshift > 7) { 559 printf("Invalid hw.cxgbe.fl_pktshift value (%d)," 560 " using 0 instead.\n", fl_pktshift); 561 fl_pktshift = 0; 562 } 563 564 if (spg_len != 64 && spg_len != 128) { 565 int len; 566 567 #if defined(__i386__) || defined(__amd64__) 568 len = cpu_clflush_line_size > 64 ? 128 : 64; 569 #else 570 len = 64; 571 #endif 572 if (spg_len != -1) { 573 printf("Invalid hw.cxgbe.spg_len value (%d)," 574 " using %d instead.\n", spg_len, len); 575 } 576 spg_len = len; 577 } 578 579 if (cong_drop < -1 || cong_drop > 2) { 580 printf("Invalid hw.cxgbe.cong_drop value (%d)," 581 " using 0 instead.\n", cong_drop); 582 cong_drop = 0; 583 } 584 #ifdef TCP_OFFLOAD 585 if (ofld_cong_drop < -1 || ofld_cong_drop > 2) { 586 printf("Invalid hw.cxgbe.ofld_cong_drop value (%d)," 587 " using 0 instead.\n", ofld_cong_drop); 588 ofld_cong_drop = 0; 589 } 590 #endif 591 592 if (tscale != 1 && (tscale < 3 || tscale > 17)) { 593 printf("Invalid hw.cxgbe.tscale value (%d)," 594 " using 1 instead.\n", tscale); 595 tscale = 1; 596 } 597 598 if (largest_rx_cluster != MCLBYTES && 599 #if MJUMPAGESIZE != MCLBYTES 600 largest_rx_cluster != MJUMPAGESIZE && 601 #endif 602 largest_rx_cluster != MJUM9BYTES && 603 largest_rx_cluster != MJUM16BYTES) { 604 printf("Invalid hw.cxgbe.largest_rx_cluster value (%d)," 605 " using %d instead.\n", largest_rx_cluster, MJUM16BYTES); 606 largest_rx_cluster = MJUM16BYTES; 607 } 608 609 if (safest_rx_cluster != MCLBYTES && 610 #if MJUMPAGESIZE != MCLBYTES 611 safest_rx_cluster != MJUMPAGESIZE && 612 #endif 613 safest_rx_cluster != MJUM9BYTES && 614 safest_rx_cluster != MJUM16BYTES) { 615 printf("Invalid hw.cxgbe.safest_rx_cluster value (%d)," 616 " using %d instead.\n", safest_rx_cluster, MJUMPAGESIZE); 617 safest_rx_cluster = MJUMPAGESIZE; 618 } 619 620 extfree_refs = counter_u64_alloc(M_WAITOK); 621 extfree_rels = counter_u64_alloc(M_WAITOK); 622 pullups = counter_u64_alloc(M_WAITOK); 623 defrags = counter_u64_alloc(M_WAITOK); 624 counter_u64_zero(extfree_refs); 625 counter_u64_zero(extfree_rels); 626 counter_u64_zero(pullups); 627 counter_u64_zero(defrags); 628 629 t4_init_shared_cpl_handlers(); 630 t4_register_cpl_handler(CPL_FW4_MSG, handle_fw_msg); 631 t4_register_cpl_handler(CPL_FW6_MSG, handle_fw_msg); 632 t4_register_cpl_handler(CPL_SGE_EGR_UPDATE, handle_sge_egr_update); 633 #ifdef RATELIMIT 634 t4_register_shared_cpl_handler(CPL_FW4_ACK, ethofld_fw4_ack, 635 CPL_COOKIE_ETHOFLD); 636 #endif 637 t4_register_fw_msg_handler(FW6_TYPE_CMD_RPL, t4_handle_fw_rpl); 638 t4_register_fw_msg_handler(FW6_TYPE_WRERR_RPL, t4_handle_wrerr_rpl); 639 } 640 641 void 642 t4_sge_modunload(void) 643 { 644 645 counter_u64_free(extfree_refs); 646 counter_u64_free(extfree_rels); 647 counter_u64_free(pullups); 648 counter_u64_free(defrags); 649 } 650 651 uint64_t 652 t4_sge_extfree_refs(void) 653 { 654 uint64_t refs, rels; 655 656 rels = counter_u64_fetch(extfree_rels); 657 refs = counter_u64_fetch(extfree_refs); 658 659 return (refs - rels); 660 } 661 662 /* max 4096 */ 663 #define MAX_PACK_BOUNDARY 512 664 665 static inline void 666 setup_pad_and_pack_boundaries(struct adapter *sc) 667 { 668 uint32_t v, m; 669 int pad, pack, pad_shift; 670 671 pad_shift = chip_id(sc) > CHELSIO_T5 ? X_T6_INGPADBOUNDARY_SHIFT : 672 X_INGPADBOUNDARY_SHIFT; 673 pad = fl_pad; 674 if (fl_pad < (1 << pad_shift) || 675 fl_pad > (1 << (pad_shift + M_INGPADBOUNDARY)) || 676 !powerof2(fl_pad)) { 677 /* 678 * If there is any chance that we might use buffer packing and 679 * the chip is a T4, then pick 64 as the pad/pack boundary. Set 680 * it to the minimum allowed in all other cases. 681 */ 682 pad = is_t4(sc) && buffer_packing ? 64 : 1 << pad_shift; 683 684 /* 685 * For fl_pad = 0 we'll still write a reasonable value to the 686 * register but all the freelists will opt out of padding. 687 * We'll complain here only if the user tried to set it to a 688 * value greater than 0 that was invalid. 689 */ 690 if (fl_pad > 0) { 691 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pad value" 692 " (%d), using %d instead.\n", fl_pad, pad); 693 } 694 } 695 m = V_INGPADBOUNDARY(M_INGPADBOUNDARY); 696 v = V_INGPADBOUNDARY(ilog2(pad) - pad_shift); 697 t4_set_reg_field(sc, A_SGE_CONTROL, m, v); 698 699 if (is_t4(sc)) { 700 if (fl_pack != -1 && fl_pack != pad) { 701 /* Complain but carry on. */ 702 device_printf(sc->dev, "hw.cxgbe.fl_pack (%d) ignored," 703 " using %d instead.\n", fl_pack, pad); 704 } 705 return; 706 } 707 708 pack = fl_pack; 709 if (fl_pack < 16 || fl_pack == 32 || fl_pack > 4096 || 710 !powerof2(fl_pack)) { 711 if (sc->params.pci.mps > MAX_PACK_BOUNDARY) 712 pack = MAX_PACK_BOUNDARY; 713 else 714 pack = max(sc->params.pci.mps, CACHE_LINE_SIZE); 715 MPASS(powerof2(pack)); 716 if (pack < 16) 717 pack = 16; 718 if (pack == 32) 719 pack = 64; 720 if (pack > 4096) 721 pack = 4096; 722 if (fl_pack != -1) { 723 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pack value" 724 " (%d), using %d instead.\n", fl_pack, pack); 725 } 726 } 727 m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY); 728 if (pack == 16) 729 v = V_INGPACKBOUNDARY(0); 730 else 731 v = V_INGPACKBOUNDARY(ilog2(pack) - 5); 732 733 MPASS(!is_t4(sc)); /* T4 doesn't have SGE_CONTROL2 */ 734 t4_set_reg_field(sc, A_SGE_CONTROL2, m, v); 735 } 736 737 /* 738 * adap->params.vpd.cclk must be set up before this is called. 739 */ 740 void 741 t4_tweak_chip_settings(struct adapter *sc) 742 { 743 int i, reg; 744 uint32_t v, m; 745 int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200}; 746 int timer_max = M_TIMERVALUE0 * 1000 / sc->params.vpd.cclk; 747 int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */ 748 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 749 static int sw_buf_sizes[] = { 750 MCLBYTES, 751 #if MJUMPAGESIZE != MCLBYTES 752 MJUMPAGESIZE, 753 #endif 754 MJUM9BYTES, 755 MJUM16BYTES 756 }; 757 758 KASSERT(sc->flags & MASTER_PF, 759 ("%s: trying to change chip settings when not master.", __func__)); 760 761 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE; 762 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE | 763 V_EGRSTATUSPAGESIZE(spg_len == 128); 764 t4_set_reg_field(sc, A_SGE_CONTROL, m, v); 765 766 setup_pad_and_pack_boundaries(sc); 767 768 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) | 769 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) | 770 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) | 771 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) | 772 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) | 773 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) | 774 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) | 775 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10); 776 t4_write_reg(sc, A_SGE_HOST_PAGE_SIZE, v); 777 778 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0, 4096); 779 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE1, 65536); 780 reg = A_SGE_FL_BUFFER_SIZE2; 781 for (i = 0; i < nitems(sw_buf_sizes); i++) { 782 MPASS(reg <= A_SGE_FL_BUFFER_SIZE15); 783 t4_write_reg(sc, reg, sw_buf_sizes[i]); 784 reg += 4; 785 MPASS(reg <= A_SGE_FL_BUFFER_SIZE15); 786 t4_write_reg(sc, reg, sw_buf_sizes[i] - CL_METADATA_SIZE); 787 reg += 4; 788 } 789 790 v = V_THRESHOLD_0(intr_pktcount[0]) | V_THRESHOLD_1(intr_pktcount[1]) | 791 V_THRESHOLD_2(intr_pktcount[2]) | V_THRESHOLD_3(intr_pktcount[3]); 792 t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD, v); 793 794 KASSERT(intr_timer[0] <= timer_max, 795 ("%s: not a single usable timer (%d, %d)", __func__, intr_timer[0], 796 timer_max)); 797 for (i = 1; i < nitems(intr_timer); i++) { 798 KASSERT(intr_timer[i] >= intr_timer[i - 1], 799 ("%s: timers not listed in increasing order (%d)", 800 __func__, i)); 801 802 while (intr_timer[i] > timer_max) { 803 if (i == nitems(intr_timer) - 1) { 804 intr_timer[i] = timer_max; 805 break; 806 } 807 intr_timer[i] += intr_timer[i - 1]; 808 intr_timer[i] /= 2; 809 } 810 } 811 812 v = V_TIMERVALUE0(us_to_core_ticks(sc, intr_timer[0])) | 813 V_TIMERVALUE1(us_to_core_ticks(sc, intr_timer[1])); 814 t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1, v); 815 v = V_TIMERVALUE2(us_to_core_ticks(sc, intr_timer[2])) | 816 V_TIMERVALUE3(us_to_core_ticks(sc, intr_timer[3])); 817 t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3, v); 818 v = V_TIMERVALUE4(us_to_core_ticks(sc, intr_timer[4])) | 819 V_TIMERVALUE5(us_to_core_ticks(sc, intr_timer[5])); 820 t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5, v); 821 822 if (chip_id(sc) >= CHELSIO_T6) { 823 m = V_TSCALE(M_TSCALE); 824 if (tscale == 1) 825 v = 0; 826 else 827 v = V_TSCALE(tscale - 2); 828 t4_set_reg_field(sc, A_SGE_ITP_CONTROL, m, v); 829 830 if (sc->debug_flags & DF_DISABLE_TCB_CACHE) { 831 m = V_RDTHRESHOLD(M_RDTHRESHOLD) | F_WRTHRTHRESHEN | 832 V_WRTHRTHRESH(M_WRTHRTHRESH); 833 t4_tp_pio_read(sc, &v, 1, A_TP_CMM_CONFIG, 1); 834 v &= ~m; 835 v |= V_RDTHRESHOLD(1) | F_WRTHRTHRESHEN | 836 V_WRTHRTHRESH(16); 837 t4_tp_pio_write(sc, &v, 1, A_TP_CMM_CONFIG, 1); 838 } 839 } 840 841 /* 4K, 16K, 64K, 256K DDP "page sizes" for TDDP */ 842 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 843 t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, v); 844 845 /* 846 * 4K, 8K, 16K, 64K DDP "page sizes" for iSCSI DDP. These have been 847 * chosen with MAXPHYS = 128K in mind. The largest DDP buffer that we 848 * may have to deal with is MAXPHYS + 1 page. 849 */ 850 v = V_HPZ0(0) | V_HPZ1(1) | V_HPZ2(2) | V_HPZ3(4); 851 t4_write_reg(sc, A_ULP_RX_ISCSI_PSZ, v); 852 853 /* We use multiple DDP page sizes both in plain-TOE and ISCSI modes. */ 854 m = v = F_TDDPTAGTCB | F_ISCSITAGTCB; 855 if (sc->nvmecaps != 0) { 856 /* Request DDP status bit for NVMe PDU completions. */ 857 m |= F_NVME_TCP_DDP_VAL_EN; 858 v |= F_NVME_TCP_DDP_VAL_EN; 859 } 860 t4_set_reg_field(sc, A_ULP_RX_CTL, m, v); 861 862 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 863 F_RESETDDPOFFSET; 864 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 865 t4_set_reg_field(sc, A_TP_PARA_REG5, m, v); 866 } 867 868 /* 869 * SGE wants the buffer to be at least 64B and then a multiple of 16. Its 870 * address mut be 16B aligned. If padding is in use the buffer's start and end 871 * need to be aligned to the pad boundary as well. We'll just make sure that 872 * the size is a multiple of the pad boundary here, it is up to the buffer 873 * allocation code to make sure the start of the buffer is aligned. 874 */ 875 static inline int 876 hwsz_ok(struct adapter *sc, int hwsz) 877 { 878 int mask = fl_pad ? sc->params.sge.pad_boundary - 1 : 16 - 1; 879 880 return (hwsz >= 64 && (hwsz & mask) == 0); 881 } 882 883 /* 884 * Initialize the rx buffer sizes and figure out which zones the buffers will 885 * be allocated from. 886 */ 887 void 888 t4_init_rx_buf_info(struct adapter *sc) 889 { 890 struct sge *s = &sc->sge; 891 struct sge_params *sp = &sc->params.sge; 892 int i, j, n; 893 static int sw_buf_sizes[] = { /* Sorted by size */ 894 MCLBYTES, 895 #if MJUMPAGESIZE != MCLBYTES 896 MJUMPAGESIZE, 897 #endif 898 MJUM9BYTES, 899 MJUM16BYTES 900 }; 901 struct rx_buf_info *rxb; 902 903 s->safe_zidx = -1; 904 rxb = &s->rx_buf_info[0]; 905 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) { 906 rxb->size1 = sw_buf_sizes[i]; 907 rxb->zone = m_getzone(rxb->size1); 908 rxb->type = m_gettype(rxb->size1); 909 rxb->size2 = 0; 910 rxb->hwidx1 = -1; 911 rxb->hwidx2 = -1; 912 for (j = 0; j < SGE_FLBUF_SIZES; j++) { 913 int hwsize = sp->sge_fl_buffer_size[j]; 914 915 if (!hwsz_ok(sc, hwsize)) 916 continue; 917 918 /* hwidx for size1 */ 919 if (rxb->hwidx1 == -1 && rxb->size1 == hwsize) 920 rxb->hwidx1 = j; 921 922 /* hwidx for size2 (buffer packing) */ 923 if (rxb->size1 - CL_METADATA_SIZE < hwsize) 924 continue; 925 n = rxb->size1 - hwsize - CL_METADATA_SIZE; 926 if (n == 0) { 927 rxb->hwidx2 = j; 928 rxb->size2 = hwsize; 929 break; /* stop looking */ 930 } 931 if (rxb->hwidx2 != -1) { 932 if (n < sp->sge_fl_buffer_size[rxb->hwidx2] - 933 hwsize - CL_METADATA_SIZE) { 934 rxb->hwidx2 = j; 935 rxb->size2 = hwsize; 936 } 937 } else if (n <= 2 * CL_METADATA_SIZE) { 938 rxb->hwidx2 = j; 939 rxb->size2 = hwsize; 940 } 941 } 942 if (rxb->hwidx2 != -1) 943 sc->flags |= BUF_PACKING_OK; 944 if (s->safe_zidx == -1 && rxb->size1 == safest_rx_cluster) 945 s->safe_zidx = i; 946 } 947 } 948 949 /* 950 * Verify some basic SGE settings for the PF and VF driver, and other 951 * miscellaneous settings for the PF driver. 952 */ 953 int 954 t4_verify_chip_settings(struct adapter *sc) 955 { 956 struct sge_params *sp = &sc->params.sge; 957 uint32_t m, v, r; 958 int rc = 0; 959 const uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 960 961 m = F_RXPKTCPLMODE; 962 v = F_RXPKTCPLMODE; 963 r = sp->sge_control; 964 if ((r & m) != v) { 965 device_printf(sc->dev, "invalid SGE_CONTROL(0x%x)\n", r); 966 rc = EINVAL; 967 } 968 969 /* 970 * If this changes then every single use of PAGE_SHIFT in the driver 971 * needs to be carefully reviewed for PAGE_SHIFT vs sp->page_shift. 972 */ 973 if (sp->page_shift != PAGE_SHIFT) { 974 device_printf(sc->dev, "invalid SGE_HOST_PAGE_SIZE(0x%x)\n", r); 975 rc = EINVAL; 976 } 977 978 if (sc->flags & IS_VF) 979 return (0); 980 981 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 982 r = t4_read_reg(sc, A_ULP_RX_TDDP_PSZ); 983 if (r != v) { 984 device_printf(sc->dev, "invalid ULP_RX_TDDP_PSZ(0x%x)\n", r); 985 if (sc->vres.ddp.size != 0) 986 rc = EINVAL; 987 } 988 989 m = v = F_TDDPTAGTCB; 990 r = t4_read_reg(sc, A_ULP_RX_CTL); 991 if ((r & m) != v) { 992 device_printf(sc->dev, "invalid ULP_RX_CTL(0x%x)\n", r); 993 if (sc->vres.ddp.size != 0) 994 rc = EINVAL; 995 } 996 997 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 998 F_RESETDDPOFFSET; 999 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 1000 r = t4_read_reg(sc, A_TP_PARA_REG5); 1001 if ((r & m) != v) { 1002 device_printf(sc->dev, "invalid TP_PARA_REG5(0x%x)\n", r); 1003 if (sc->vres.ddp.size != 0) 1004 rc = EINVAL; 1005 } 1006 1007 return (rc); 1008 } 1009 1010 int 1011 t4_create_dma_tag(struct adapter *sc) 1012 { 1013 int rc; 1014 1015 rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0, 1016 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE, 1017 BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL, 1018 NULL, &sc->dmat); 1019 if (rc != 0) { 1020 device_printf(sc->dev, 1021 "failed to create main DMA tag: %d\n", rc); 1022 } 1023 1024 return (rc); 1025 } 1026 1027 void 1028 t4_sge_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx, 1029 struct sysctl_oid_list *children) 1030 { 1031 struct sge_params *sp = &sc->params.sge; 1032 1033 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "buffer_sizes", 1034 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 1035 sysctl_bufsizes, "A", "freelist buffer sizes"); 1036 1037 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pktshift", CTLFLAG_RD, 1038 NULL, sp->fl_pktshift, "payload DMA offset in rx buffer (bytes)"); 1039 1040 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pad", CTLFLAG_RD, 1041 NULL, sp->pad_boundary, "payload pad boundary (bytes)"); 1042 1043 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "spg_len", CTLFLAG_RD, 1044 NULL, sp->spg_len, "status page size (bytes)"); 1045 1046 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_drop", CTLFLAG_RD, 1047 NULL, cong_drop, "congestion drop setting"); 1048 #ifdef TCP_OFFLOAD 1049 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ofld_cong_drop", CTLFLAG_RD, 1050 NULL, ofld_cong_drop, "congestion drop setting"); 1051 #endif 1052 1053 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pack", CTLFLAG_RD, 1054 NULL, sp->pack_boundary, "payload pack boundary (bytes)"); 1055 } 1056 1057 int 1058 t4_destroy_dma_tag(struct adapter *sc) 1059 { 1060 if (sc->dmat) 1061 bus_dma_tag_destroy(sc->dmat); 1062 1063 return (0); 1064 } 1065 1066 /* 1067 * Allocate and initialize the firmware event queue, control queues, and special 1068 * purpose rx queues owned by the adapter. 1069 * 1070 * Returns errno on failure. Resources allocated up to that point may still be 1071 * allocated. Caller is responsible for cleanup in case this function fails. 1072 */ 1073 int 1074 t4_setup_adapter_queues(struct adapter *sc) 1075 { 1076 int rc, i; 1077 1078 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 1079 1080 /* 1081 * Firmware event queue 1082 */ 1083 rc = alloc_fwq(sc); 1084 if (rc != 0) 1085 return (rc); 1086 1087 /* 1088 * That's all for the VF driver. 1089 */ 1090 if (sc->flags & IS_VF) 1091 return (rc); 1092 1093 /* 1094 * XXX: General purpose rx queues, one per port. 1095 */ 1096 1097 /* 1098 * Control queues. At least one per port and per internal core. 1099 */ 1100 for (i = 0; i < sc->sge.nctrlq; i++) { 1101 rc = alloc_ctrlq(sc, i); 1102 if (rc != 0) 1103 return (rc); 1104 } 1105 1106 return (rc); 1107 } 1108 1109 /* 1110 * Idempotent 1111 */ 1112 int 1113 t4_teardown_adapter_queues(struct adapter *sc) 1114 { 1115 int i; 1116 1117 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 1118 1119 if (sc->sge.ctrlq != NULL) { 1120 MPASS(!(sc->flags & IS_VF)); /* VFs don't allocate ctrlq. */ 1121 for (i = 0; i < sc->sge.nctrlq; i++) 1122 free_ctrlq(sc, i); 1123 } 1124 free_fwq(sc); 1125 1126 return (0); 1127 } 1128 1129 /* Maximum payload that could arrive with a single iq descriptor. */ 1130 static inline int 1131 max_rx_payload(struct adapter *sc, if_t ifp, const bool ofld) 1132 { 1133 int maxp; 1134 1135 /* large enough even when hw VLAN extraction is disabled */ 1136 maxp = sc->params.sge.fl_pktshift + ETHER_HDR_LEN + 1137 ETHER_VLAN_ENCAP_LEN + if_getmtu(ifp); 1138 if (ofld && sc->tt.tls && sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS && 1139 maxp < sc->params.tp.max_rx_pdu) 1140 maxp = sc->params.tp.max_rx_pdu; 1141 return (maxp); 1142 } 1143 1144 int 1145 t4_setup_vi_queues(struct vi_info *vi) 1146 { 1147 int rc = 0, i, intr_idx; 1148 struct sge_rxq *rxq; 1149 struct sge_txq *txq; 1150 #ifdef TCP_OFFLOAD 1151 struct sge_ofld_rxq *ofld_rxq; 1152 #endif 1153 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1154 struct sge_ofld_txq *ofld_txq; 1155 #endif 1156 #ifdef DEV_NETMAP 1157 int saved_idx, iqidx; 1158 struct sge_nm_rxq *nm_rxq; 1159 struct sge_nm_txq *nm_txq; 1160 #endif 1161 struct adapter *sc = vi->adapter; 1162 if_t ifp = vi->ifp; 1163 int maxp; 1164 1165 /* Interrupt vector to start from (when using multiple vectors) */ 1166 intr_idx = vi->first_intr; 1167 1168 #ifdef DEV_NETMAP 1169 saved_idx = intr_idx; 1170 if (if_getcapabilities(ifp) & IFCAP_NETMAP) { 1171 1172 /* netmap is supported with direct interrupts only. */ 1173 MPASS(!forwarding_intr_to_fwq(sc)); 1174 MPASS(vi->first_intr >= 0); 1175 1176 /* 1177 * We don't have buffers to back the netmap rx queues 1178 * right now so we create the queues in a way that 1179 * doesn't set off any congestion signal in the chip. 1180 */ 1181 for_each_nm_rxq(vi, i, nm_rxq) { 1182 rc = alloc_nm_rxq(vi, nm_rxq, intr_idx, i); 1183 if (rc != 0) 1184 goto done; 1185 intr_idx++; 1186 } 1187 1188 for_each_nm_txq(vi, i, nm_txq) { 1189 iqidx = vi->first_nm_rxq + (i % vi->nnmrxq); 1190 rc = alloc_nm_txq(vi, nm_txq, iqidx, i); 1191 if (rc != 0) 1192 goto done; 1193 } 1194 } 1195 1196 /* Normal rx queues and netmap rx queues share the same interrupts. */ 1197 intr_idx = saved_idx; 1198 #endif 1199 1200 /* 1201 * Allocate rx queues first because a default iqid is required when 1202 * creating a tx queue. 1203 */ 1204 maxp = max_rx_payload(sc, ifp, false); 1205 for_each_rxq(vi, i, rxq) { 1206 rc = alloc_rxq(vi, rxq, i, intr_idx, maxp); 1207 if (rc != 0) 1208 goto done; 1209 if (!forwarding_intr_to_fwq(sc)) 1210 intr_idx++; 1211 } 1212 #ifdef DEV_NETMAP 1213 if (if_getcapabilities(ifp) & IFCAP_NETMAP) 1214 intr_idx = saved_idx + max(vi->nrxq, vi->nnmrxq); 1215 #endif 1216 #ifdef TCP_OFFLOAD 1217 maxp = max_rx_payload(sc, ifp, true); 1218 for_each_ofld_rxq(vi, i, ofld_rxq) { 1219 rc = alloc_ofld_rxq(vi, ofld_rxq, i, intr_idx, maxp); 1220 if (rc != 0) 1221 goto done; 1222 if (!forwarding_intr_to_fwq(sc)) 1223 intr_idx++; 1224 } 1225 #endif 1226 1227 /* 1228 * Now the tx queues. 1229 */ 1230 for_each_txq(vi, i, txq) { 1231 rc = alloc_txq(vi, txq, i); 1232 if (rc != 0) 1233 goto done; 1234 } 1235 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1236 for_each_ofld_txq(vi, i, ofld_txq) { 1237 rc = alloc_ofld_txq(vi, ofld_txq, i); 1238 if (rc != 0) 1239 goto done; 1240 } 1241 #endif 1242 done: 1243 if (rc) 1244 t4_teardown_vi_queues(vi); 1245 1246 return (rc); 1247 } 1248 1249 /* 1250 * Idempotent 1251 */ 1252 int 1253 t4_teardown_vi_queues(struct vi_info *vi) 1254 { 1255 int i; 1256 struct sge_rxq *rxq; 1257 struct sge_txq *txq; 1258 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1259 struct sge_ofld_txq *ofld_txq; 1260 #endif 1261 #ifdef TCP_OFFLOAD 1262 struct sge_ofld_rxq *ofld_rxq; 1263 #endif 1264 #ifdef DEV_NETMAP 1265 struct sge_nm_rxq *nm_rxq; 1266 struct sge_nm_txq *nm_txq; 1267 #endif 1268 1269 #ifdef DEV_NETMAP 1270 if (if_getcapabilities(vi->ifp) & IFCAP_NETMAP) { 1271 for_each_nm_txq(vi, i, nm_txq) { 1272 free_nm_txq(vi, nm_txq); 1273 } 1274 1275 for_each_nm_rxq(vi, i, nm_rxq) { 1276 free_nm_rxq(vi, nm_rxq); 1277 } 1278 } 1279 #endif 1280 1281 /* 1282 * Take down all the tx queues first, as they reference the rx queues 1283 * (for egress updates, etc.). 1284 */ 1285 1286 for_each_txq(vi, i, txq) { 1287 free_txq(vi, txq); 1288 } 1289 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1290 for_each_ofld_txq(vi, i, ofld_txq) { 1291 free_ofld_txq(vi, ofld_txq); 1292 } 1293 #endif 1294 1295 /* 1296 * Then take down the rx queues. 1297 */ 1298 1299 for_each_rxq(vi, i, rxq) { 1300 free_rxq(vi, rxq); 1301 } 1302 #ifdef TCP_OFFLOAD 1303 for_each_ofld_rxq(vi, i, ofld_rxq) { 1304 free_ofld_rxq(vi, ofld_rxq); 1305 } 1306 #endif 1307 1308 return (0); 1309 } 1310 1311 /* 1312 * Interrupt handler when the driver is using only 1 interrupt. This is a very 1313 * unusual scenario. 1314 * 1315 * a) Deals with errors, if any. 1316 * b) Services firmware event queue, which is taking interrupts for all other 1317 * queues. 1318 */ 1319 void 1320 t4_intr_all(void *arg) 1321 { 1322 struct adapter *sc = arg; 1323 struct sge_iq *fwq = &sc->sge.fwq; 1324 1325 MPASS(sc->intr_count == 1); 1326 1327 if (sc->intr_type == INTR_INTX) 1328 t4_write_reg(sc, MYPF_REG(A_PCIE_PF_CLI), 0); 1329 1330 t4_intr_err(arg); 1331 t4_intr_evt(fwq); 1332 } 1333 1334 /* 1335 * Interrupt handler for errors (installed directly when multiple interrupts are 1336 * being used, or called by t4_intr_all). 1337 */ 1338 void 1339 t4_intr_err(void *arg) 1340 { 1341 struct adapter *sc = arg; 1342 uint32_t v; 1343 1344 if (atomic_load_int(&sc->error_flags) & ADAP_FATAL_ERR) 1345 return; 1346 1347 v = t4_read_reg(sc, MYPF_REG(A_PL_PF_INT_CAUSE)); 1348 if (v & F_PFSW) { 1349 sc->swintr++; 1350 t4_write_reg(sc, MYPF_REG(A_PL_PF_INT_CAUSE), v); 1351 } 1352 1353 if (t4_slow_intr_handler(sc, sc->intr_flags)) 1354 t4_fatal_err(sc, false); 1355 } 1356 1357 /* 1358 * Interrupt handler for iq-only queues. The firmware event queue is the only 1359 * such queue right now. 1360 */ 1361 void 1362 t4_intr_evt(void *arg) 1363 { 1364 struct sge_iq *iq = arg; 1365 1366 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 1367 service_iq(iq, 0); 1368 (void) atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 1369 } 1370 } 1371 1372 /* 1373 * Interrupt handler for iq+fl queues. 1374 */ 1375 void 1376 t4_intr(void *arg) 1377 { 1378 struct sge_iq *iq = arg; 1379 1380 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 1381 service_iq_fl(iq, 0); 1382 (void) atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 1383 } 1384 } 1385 1386 #ifdef DEV_NETMAP 1387 /* 1388 * Interrupt handler for netmap rx queues. 1389 */ 1390 void 1391 t4_nm_intr(void *arg) 1392 { 1393 struct sge_nm_rxq *nm_rxq = arg; 1394 1395 if (atomic_cmpset_int(&nm_rxq->nm_state, NM_ON, NM_BUSY)) { 1396 service_nm_rxq(nm_rxq); 1397 (void) atomic_cmpset_int(&nm_rxq->nm_state, NM_BUSY, NM_ON); 1398 } 1399 } 1400 1401 /* 1402 * Interrupt handler for vectors shared between NIC and netmap rx queues. 1403 */ 1404 void 1405 t4_vi_intr(void *arg) 1406 { 1407 struct irq *irq = arg; 1408 1409 MPASS(irq->nm_rxq != NULL); 1410 t4_nm_intr(irq->nm_rxq); 1411 1412 MPASS(irq->rxq != NULL); 1413 t4_intr(irq->rxq); 1414 } 1415 #endif 1416 1417 /* 1418 * Deals with interrupts on an iq-only (no freelist) queue. 1419 */ 1420 static int 1421 service_iq(struct sge_iq *iq, int budget) 1422 { 1423 struct sge_iq *q; 1424 struct adapter *sc = iq->adapter; 1425 struct iq_desc *d = &iq->desc[iq->cidx]; 1426 int ndescs = 0, limit; 1427 int rsp_type; 1428 uint32_t lq; 1429 STAILQ_HEAD(, sge_iq) iql = STAILQ_HEAD_INITIALIZER(iql); 1430 1431 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq)); 1432 KASSERT((iq->flags & IQ_HAS_FL) == 0, 1433 ("%s: called for iq %p with fl (iq->flags 0x%x)", __func__, iq, 1434 iq->flags)); 1435 MPASS((iq->flags & IQ_ADJ_CREDIT) == 0); 1436 MPASS((iq->flags & IQ_LRO_ENABLED) == 0); 1437 1438 limit = budget ? budget : iq->qsize / 16; 1439 1440 /* 1441 * We always come back and check the descriptor ring for new indirect 1442 * interrupts and other responses after running a single handler. 1443 */ 1444 for (;;) { 1445 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) { 1446 1447 rmb(); 1448 1449 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen); 1450 lq = be32toh(d->rsp.pldbuflen_qid); 1451 1452 switch (rsp_type) { 1453 case X_RSPD_TYPE_FLBUF: 1454 panic("%s: data for an iq (%p) with no freelist", 1455 __func__, iq); 1456 1457 /* NOTREACHED */ 1458 1459 case X_RSPD_TYPE_CPL: 1460 KASSERT(d->rss.opcode < NUM_CPL_CMDS, 1461 ("%s: bad opcode %02x.", __func__, 1462 d->rss.opcode)); 1463 t4_cpl_handler[d->rss.opcode](iq, &d->rss, NULL); 1464 break; 1465 1466 case X_RSPD_TYPE_INTR: 1467 /* 1468 * There are 1K interrupt-capable queues (qids 0 1469 * through 1023). A response type indicating a 1470 * forwarded interrupt with a qid >= 1K is an 1471 * iWARP async notification. 1472 */ 1473 if (__predict_true(lq >= 1024)) { 1474 t4_an_handler(iq, &d->rsp); 1475 break; 1476 } 1477 1478 q = sc->sge.iqmap[lq - sc->sge.iq_start - 1479 sc->sge.iq_base]; 1480 if (atomic_cmpset_int(&q->state, IQS_IDLE, 1481 IQS_BUSY)) { 1482 if (service_iq_fl(q, q->qsize / 16) == 0) { 1483 (void) atomic_cmpset_int(&q->state, 1484 IQS_BUSY, IQS_IDLE); 1485 } else { 1486 STAILQ_INSERT_TAIL(&iql, q, 1487 link); 1488 } 1489 } 1490 break; 1491 1492 default: 1493 KASSERT(0, 1494 ("%s: illegal response type %d on iq %p", 1495 __func__, rsp_type, iq)); 1496 log(LOG_ERR, 1497 "%s: illegal response type %d on iq %p", 1498 device_get_nameunit(sc->dev), rsp_type, iq); 1499 break; 1500 } 1501 1502 d++; 1503 if (__predict_false(++iq->cidx == iq->sidx)) { 1504 iq->cidx = 0; 1505 iq->gen ^= F_RSPD_GEN; 1506 d = &iq->desc[0]; 1507 } 1508 if (__predict_false(++ndescs == limit)) { 1509 t4_write_reg(sc, sc->sge_gts_reg, 1510 V_CIDXINC(ndescs) | 1511 V_INGRESSQID(iq->cntxt_id) | 1512 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); 1513 ndescs = 0; 1514 1515 if (budget) { 1516 return (EINPROGRESS); 1517 } 1518 } 1519 } 1520 1521 if (STAILQ_EMPTY(&iql)) 1522 break; 1523 1524 /* 1525 * Process the head only, and send it to the back of the list if 1526 * it's still not done. 1527 */ 1528 q = STAILQ_FIRST(&iql); 1529 STAILQ_REMOVE_HEAD(&iql, link); 1530 if (service_iq_fl(q, q->qsize / 8) == 0) 1531 (void) atomic_cmpset_int(&q->state, IQS_BUSY, IQS_IDLE); 1532 else 1533 STAILQ_INSERT_TAIL(&iql, q, link); 1534 } 1535 1536 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) | 1537 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params)); 1538 1539 return (0); 1540 } 1541 1542 #if defined(INET) || defined(INET6) 1543 static inline int 1544 sort_before_lro(struct lro_ctrl *lro) 1545 { 1546 1547 return (lro->lro_mbuf_max != 0); 1548 } 1549 #endif 1550 1551 #define CGBE_SHIFT_SCALE 10 1552 1553 static inline uint64_t 1554 t4_tstmp_to_ns(struct adapter *sc, uint64_t lf) 1555 { 1556 struct clock_sync *cur, dcur; 1557 uint64_t hw_clocks; 1558 uint64_t hw_clk_div; 1559 sbintime_t sbt_cur_to_prev, sbt; 1560 uint64_t hw_tstmp = lf & 0xfffffffffffffffULL; /* 60b, not 64b. */ 1561 seqc_t gen; 1562 1563 for (;;) { 1564 cur = &sc->cal_info[sc->cal_current]; 1565 gen = seqc_read(&cur->gen); 1566 if (gen == 0) 1567 return (0); 1568 dcur = *cur; 1569 if (seqc_consistent(&cur->gen, gen)) 1570 break; 1571 } 1572 1573 /* 1574 * Our goal here is to have a result that is: 1575 * 1576 * ( (cur_time - prev_time) ) 1577 * ((hw_tstmp - hw_prev) * ----------------------------- ) + prev_time 1578 * ( (hw_cur - hw_prev) ) 1579 * 1580 * With the constraints that we cannot use float and we 1581 * don't want to overflow the uint64_t numbers we are using. 1582 */ 1583 hw_clocks = hw_tstmp - dcur.hw_prev; 1584 sbt_cur_to_prev = (dcur.sbt_cur - dcur.sbt_prev); 1585 hw_clk_div = dcur.hw_cur - dcur.hw_prev; 1586 sbt = hw_clocks * sbt_cur_to_prev / hw_clk_div + dcur.sbt_prev; 1587 return (sbttons(sbt)); 1588 } 1589 1590 static inline void 1591 move_to_next_rxbuf(struct sge_fl *fl) 1592 { 1593 1594 fl->rx_offset = 0; 1595 if (__predict_false((++fl->cidx & 7) == 0)) { 1596 uint16_t cidx = fl->cidx >> 3; 1597 1598 if (__predict_false(cidx == fl->sidx)) 1599 fl->cidx = cidx = 0; 1600 fl->hw_cidx = cidx; 1601 } 1602 } 1603 1604 /* 1605 * Deals with interrupts on an iq+fl queue. 1606 */ 1607 static int 1608 service_iq_fl(struct sge_iq *iq, int budget) 1609 { 1610 struct sge_rxq *rxq = iq_to_rxq(iq); 1611 struct sge_fl *fl; 1612 struct adapter *sc = iq->adapter; 1613 struct iq_desc *d = &iq->desc[iq->cidx]; 1614 int ndescs, limit; 1615 int rsp_type, starved; 1616 uint32_t lq; 1617 uint16_t fl_hw_cidx; 1618 struct mbuf *m0; 1619 #if defined(INET) || defined(INET6) 1620 const struct timeval lro_timeout = {0, sc->lro_timeout}; 1621 struct lro_ctrl *lro = &rxq->lro; 1622 #endif 1623 1624 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq)); 1625 MPASS(iq->flags & IQ_HAS_FL); 1626 1627 ndescs = 0; 1628 #if defined(INET) || defined(INET6) 1629 if (iq->flags & IQ_ADJ_CREDIT) { 1630 MPASS(sort_before_lro(lro)); 1631 iq->flags &= ~IQ_ADJ_CREDIT; 1632 if ((d->rsp.u.type_gen & F_RSPD_GEN) != iq->gen) { 1633 tcp_lro_flush_all(lro); 1634 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(1) | 1635 V_INGRESSQID((u32)iq->cntxt_id) | 1636 V_SEINTARM(iq->intr_params)); 1637 return (0); 1638 } 1639 ndescs = 1; 1640 } 1641 #else 1642 MPASS((iq->flags & IQ_ADJ_CREDIT) == 0); 1643 #endif 1644 1645 limit = budget ? budget : iq->qsize / 16; 1646 fl = &rxq->fl; 1647 fl_hw_cidx = fl->hw_cidx; /* stable snapshot */ 1648 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) { 1649 1650 rmb(); 1651 1652 m0 = NULL; 1653 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen); 1654 lq = be32toh(d->rsp.pldbuflen_qid); 1655 1656 switch (rsp_type) { 1657 case X_RSPD_TYPE_FLBUF: 1658 if (lq & F_RSPD_NEWBUF) { 1659 if (fl->rx_offset > 0) 1660 move_to_next_rxbuf(fl); 1661 lq = G_RSPD_LEN(lq); 1662 } 1663 if (IDXDIFF(fl->hw_cidx, fl_hw_cidx, fl->sidx) > 4) { 1664 FL_LOCK(fl); 1665 refill_fl(sc, fl, 64); 1666 FL_UNLOCK(fl); 1667 fl_hw_cidx = fl->hw_cidx; 1668 } 1669 1670 if (d->rss.opcode == CPL_RX_PKT) { 1671 if (__predict_true(eth_rx(sc, rxq, d, lq) == 0)) 1672 break; 1673 goto out; 1674 } 1675 m0 = get_fl_payload(sc, fl, lq); 1676 if (__predict_false(m0 == NULL)) 1677 goto out; 1678 1679 /* fall through */ 1680 1681 case X_RSPD_TYPE_CPL: 1682 KASSERT(d->rss.opcode < NUM_CPL_CMDS, 1683 ("%s: bad opcode %02x.", __func__, d->rss.opcode)); 1684 t4_cpl_handler[d->rss.opcode](iq, &d->rss, m0); 1685 break; 1686 1687 case X_RSPD_TYPE_INTR: 1688 1689 /* 1690 * There are 1K interrupt-capable queues (qids 0 1691 * through 1023). A response type indicating a 1692 * forwarded interrupt with a qid >= 1K is an 1693 * iWARP async notification. That is the only 1694 * acceptable indirect interrupt on this queue. 1695 */ 1696 if (__predict_false(lq < 1024)) { 1697 panic("%s: indirect interrupt on iq_fl %p " 1698 "with qid %u", __func__, iq, lq); 1699 } 1700 1701 t4_an_handler(iq, &d->rsp); 1702 break; 1703 1704 default: 1705 KASSERT(0, ("%s: illegal response type %d on iq %p", 1706 __func__, rsp_type, iq)); 1707 log(LOG_ERR, "%s: illegal response type %d on iq %p", 1708 device_get_nameunit(sc->dev), rsp_type, iq); 1709 break; 1710 } 1711 1712 d++; 1713 if (__predict_false(++iq->cidx == iq->sidx)) { 1714 iq->cidx = 0; 1715 iq->gen ^= F_RSPD_GEN; 1716 d = &iq->desc[0]; 1717 } 1718 if (__predict_false(++ndescs == limit)) { 1719 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) | 1720 V_INGRESSQID(iq->cntxt_id) | 1721 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); 1722 1723 #if defined(INET) || defined(INET6) 1724 if (iq->flags & IQ_LRO_ENABLED && 1725 !sort_before_lro(lro) && 1726 sc->lro_timeout != 0) { 1727 tcp_lro_flush_inactive(lro, &lro_timeout); 1728 } 1729 #endif 1730 if (budget) 1731 return (EINPROGRESS); 1732 ndescs = 0; 1733 } 1734 } 1735 out: 1736 #if defined(INET) || defined(INET6) 1737 if (iq->flags & IQ_LRO_ENABLED) { 1738 if (ndescs > 0 && lro->lro_mbuf_count > 8) { 1739 MPASS(sort_before_lro(lro)); 1740 /* hold back one credit and don't flush LRO state */ 1741 iq->flags |= IQ_ADJ_CREDIT; 1742 ndescs--; 1743 } else { 1744 tcp_lro_flush_all(lro); 1745 } 1746 } 1747 #endif 1748 1749 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) | 1750 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params)); 1751 1752 FL_LOCK(fl); 1753 starved = refill_fl(sc, fl, 64); 1754 FL_UNLOCK(fl); 1755 if (__predict_false(starved != 0)) 1756 add_fl_to_sfl(sc, fl); 1757 1758 return (0); 1759 } 1760 1761 static inline struct cluster_metadata * 1762 cl_metadata(struct fl_sdesc *sd) 1763 { 1764 1765 return ((void *)(sd->cl + sd->moff)); 1766 } 1767 1768 static void 1769 rxb_free(struct mbuf *m) 1770 { 1771 struct cluster_metadata *clm = m->m_ext.ext_arg1; 1772 1773 uma_zfree(clm->zone, clm->cl); 1774 counter_u64_add(extfree_rels, 1); 1775 } 1776 1777 /* 1778 * The mbuf returned comes from zone_muf and carries the payload in one of these 1779 * ways 1780 * a) complete frame inside the mbuf 1781 * b) m_cljset (for clusters without metadata) 1782 * d) m_extaddref (cluster with metadata) 1783 */ 1784 static struct mbuf * 1785 get_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset, 1786 int remaining) 1787 { 1788 struct mbuf *m; 1789 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 1790 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[sd->zidx]; 1791 struct cluster_metadata *clm; 1792 int len, blen; 1793 caddr_t payload; 1794 1795 if (fl->flags & FL_BUF_PACKING) { 1796 u_int l, pad; 1797 1798 blen = rxb->size2 - fl->rx_offset; /* max possible in this buf */ 1799 len = min(remaining, blen); 1800 payload = sd->cl + fl->rx_offset; 1801 1802 l = fr_offset + len; 1803 pad = roundup2(l, fl->buf_boundary) - l; 1804 if (fl->rx_offset + len + pad < rxb->size2) 1805 blen = len + pad; 1806 MPASS(fl->rx_offset + blen <= rxb->size2); 1807 } else { 1808 MPASS(fl->rx_offset == 0); /* not packing */ 1809 blen = rxb->size1; 1810 len = min(remaining, blen); 1811 payload = sd->cl; 1812 } 1813 1814 if (fr_offset == 0) { 1815 m = m_gethdr(M_NOWAIT, MT_DATA); 1816 if (__predict_false(m == NULL)) 1817 return (NULL); 1818 m->m_pkthdr.len = remaining; 1819 } else { 1820 m = m_get(M_NOWAIT, MT_DATA); 1821 if (__predict_false(m == NULL)) 1822 return (NULL); 1823 } 1824 m->m_len = len; 1825 kmsan_mark(payload, len, KMSAN_STATE_INITED); 1826 1827 if (sc->sc_do_rxcopy && len < RX_COPY_THRESHOLD) { 1828 /* copy data to mbuf */ 1829 bcopy(payload, mtod(m, caddr_t), len); 1830 if (fl->flags & FL_BUF_PACKING) { 1831 fl->rx_offset += blen; 1832 MPASS(fl->rx_offset <= rxb->size2); 1833 if (fl->rx_offset < rxb->size2) 1834 return (m); /* without advancing the cidx */ 1835 } 1836 } else if (fl->flags & FL_BUF_PACKING) { 1837 clm = cl_metadata(sd); 1838 if (sd->nmbuf++ == 0) { 1839 clm->refcount = 1; 1840 clm->zone = rxb->zone; 1841 clm->cl = sd->cl; 1842 counter_u64_add(extfree_refs, 1); 1843 } 1844 m_extaddref(m, payload, blen, &clm->refcount, rxb_free, clm, 1845 NULL); 1846 1847 fl->rx_offset += blen; 1848 MPASS(fl->rx_offset <= rxb->size2); 1849 if (fl->rx_offset < rxb->size2) 1850 return (m); /* without advancing the cidx */ 1851 } else { 1852 m_cljset(m, sd->cl, rxb->type); 1853 sd->cl = NULL; /* consumed, not a recycle candidate */ 1854 } 1855 1856 move_to_next_rxbuf(fl); 1857 1858 return (m); 1859 } 1860 1861 static struct mbuf * 1862 get_fl_payload(struct adapter *sc, struct sge_fl *fl, const u_int plen) 1863 { 1864 struct mbuf *m0, *m, **pnext; 1865 u_int remaining; 1866 1867 if (__predict_false(fl->flags & FL_BUF_RESUME)) { 1868 M_ASSERTPKTHDR(fl->m0); 1869 MPASS(fl->m0->m_pkthdr.len == plen); 1870 MPASS(fl->remaining < plen); 1871 1872 m0 = fl->m0; 1873 pnext = fl->pnext; 1874 remaining = fl->remaining; 1875 fl->flags &= ~FL_BUF_RESUME; 1876 goto get_segment; 1877 } 1878 1879 /* 1880 * Payload starts at rx_offset in the current hw buffer. Its length is 1881 * 'len' and it may span multiple hw buffers. 1882 */ 1883 1884 m0 = get_scatter_segment(sc, fl, 0, plen); 1885 if (m0 == NULL) 1886 return (NULL); 1887 remaining = plen - m0->m_len; 1888 pnext = &m0->m_next; 1889 while (remaining > 0) { 1890 get_segment: 1891 MPASS(fl->rx_offset == 0); 1892 m = get_scatter_segment(sc, fl, plen - remaining, remaining); 1893 if (__predict_false(m == NULL)) { 1894 fl->m0 = m0; 1895 fl->pnext = pnext; 1896 fl->remaining = remaining; 1897 fl->flags |= FL_BUF_RESUME; 1898 return (NULL); 1899 } 1900 *pnext = m; 1901 pnext = &m->m_next; 1902 remaining -= m->m_len; 1903 } 1904 *pnext = NULL; 1905 1906 M_ASSERTPKTHDR(m0); 1907 return (m0); 1908 } 1909 1910 static int 1911 skip_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset, 1912 int remaining) 1913 { 1914 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 1915 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[sd->zidx]; 1916 int len, blen; 1917 1918 if (fl->flags & FL_BUF_PACKING) { 1919 u_int l, pad; 1920 1921 blen = rxb->size2 - fl->rx_offset; /* max possible in this buf */ 1922 len = min(remaining, blen); 1923 1924 l = fr_offset + len; 1925 pad = roundup2(l, fl->buf_boundary) - l; 1926 if (fl->rx_offset + len + pad < rxb->size2) 1927 blen = len + pad; 1928 fl->rx_offset += blen; 1929 MPASS(fl->rx_offset <= rxb->size2); 1930 if (fl->rx_offset < rxb->size2) 1931 return (len); /* without advancing the cidx */ 1932 } else { 1933 MPASS(fl->rx_offset == 0); /* not packing */ 1934 blen = rxb->size1; 1935 len = min(remaining, blen); 1936 } 1937 move_to_next_rxbuf(fl); 1938 return (len); 1939 } 1940 1941 static inline void 1942 skip_fl_payload(struct adapter *sc, struct sge_fl *fl, int plen) 1943 { 1944 int remaining, fr_offset, len; 1945 1946 fr_offset = 0; 1947 remaining = plen; 1948 while (remaining > 0) { 1949 len = skip_scatter_segment(sc, fl, fr_offset, remaining); 1950 fr_offset += len; 1951 remaining -= len; 1952 } 1953 } 1954 1955 static inline int 1956 get_segment_len(struct adapter *sc, struct sge_fl *fl, int plen) 1957 { 1958 int len; 1959 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 1960 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[sd->zidx]; 1961 1962 if (fl->flags & FL_BUF_PACKING) 1963 len = rxb->size2 - fl->rx_offset; 1964 else 1965 len = rxb->size1; 1966 1967 return (min(plen, len)); 1968 } 1969 1970 static int 1971 eth_rx(struct adapter *sc, struct sge_rxq *rxq, const struct iq_desc *d, 1972 u_int plen) 1973 { 1974 struct mbuf *m0; 1975 if_t ifp = rxq->ifp; 1976 struct sge_fl *fl = &rxq->fl; 1977 struct vi_info *vi = if_getsoftc(ifp); 1978 const struct cpl_rx_pkt *cpl; 1979 #if defined(INET) || defined(INET6) 1980 struct lro_ctrl *lro = &rxq->lro; 1981 #endif 1982 uint16_t err_vec, tnl_type, tnlhdr_len; 1983 static const int sw_hashtype[4][2] = { 1984 {M_HASHTYPE_NONE, M_HASHTYPE_NONE}, 1985 {M_HASHTYPE_RSS_IPV4, M_HASHTYPE_RSS_IPV6}, 1986 {M_HASHTYPE_RSS_TCP_IPV4, M_HASHTYPE_RSS_TCP_IPV6}, 1987 {M_HASHTYPE_RSS_UDP_IPV4, M_HASHTYPE_RSS_UDP_IPV6}, 1988 }; 1989 static const int sw_csum_flags[2][2] = { 1990 { 1991 /* IP, inner IP */ 1992 CSUM_ENCAP_VXLAN | 1993 CSUM_L3_CALC | CSUM_L3_VALID | 1994 CSUM_L4_CALC | CSUM_L4_VALID | 1995 CSUM_INNER_L3_CALC | CSUM_INNER_L3_VALID | 1996 CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID, 1997 1998 /* IP, inner IP6 */ 1999 CSUM_ENCAP_VXLAN | 2000 CSUM_L3_CALC | CSUM_L3_VALID | 2001 CSUM_L4_CALC | CSUM_L4_VALID | 2002 CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID, 2003 }, 2004 { 2005 /* IP6, inner IP */ 2006 CSUM_ENCAP_VXLAN | 2007 CSUM_L4_CALC | CSUM_L4_VALID | 2008 CSUM_INNER_L3_CALC | CSUM_INNER_L3_VALID | 2009 CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID, 2010 2011 /* IP6, inner IP6 */ 2012 CSUM_ENCAP_VXLAN | 2013 CSUM_L4_CALC | CSUM_L4_VALID | 2014 CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID, 2015 }, 2016 }; 2017 2018 MPASS(plen > sc->params.sge.fl_pktshift); 2019 if (vi->pfil != NULL && PFIL_HOOKED_IN(vi->pfil) && 2020 __predict_true((fl->flags & FL_BUF_RESUME) == 0)) { 2021 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 2022 caddr_t frame; 2023 int rc, slen; 2024 2025 slen = get_segment_len(sc, fl, plen) - 2026 sc->params.sge.fl_pktshift; 2027 frame = sd->cl + fl->rx_offset + sc->params.sge.fl_pktshift; 2028 CURVNET_SET_QUIET(if_getvnet(ifp)); 2029 rc = pfil_mem_in(vi->pfil, frame, slen, ifp, &m0); 2030 CURVNET_RESTORE(); 2031 if (rc == PFIL_DROPPED || rc == PFIL_CONSUMED) { 2032 skip_fl_payload(sc, fl, plen); 2033 return (0); 2034 } 2035 if (rc == PFIL_REALLOCED) { 2036 skip_fl_payload(sc, fl, plen); 2037 goto have_mbuf; 2038 } 2039 } 2040 2041 m0 = get_fl_payload(sc, fl, plen); 2042 if (__predict_false(m0 == NULL)) 2043 return (ENOMEM); 2044 2045 m0->m_pkthdr.len -= sc->params.sge.fl_pktshift; 2046 m0->m_len -= sc->params.sge.fl_pktshift; 2047 m0->m_data += sc->params.sge.fl_pktshift; 2048 2049 have_mbuf: 2050 m0->m_pkthdr.rcvif = ifp; 2051 M_HASHTYPE_SET(m0, sw_hashtype[d->rss.hash_type][d->rss.ipv6]); 2052 m0->m_pkthdr.flowid = be32toh(d->rss.hash_val); 2053 2054 cpl = (const void *)(&d->rss + 1); 2055 if (sc->params.tp.rx_pkt_encap) { 2056 const uint16_t ev = be16toh(cpl->err_vec); 2057 2058 err_vec = G_T6_COMPR_RXERR_VEC(ev); 2059 tnl_type = G_T6_RX_TNL_TYPE(ev); 2060 tnlhdr_len = G_T6_RX_TNLHDR_LEN(ev); 2061 } else { 2062 err_vec = be16toh(cpl->err_vec); 2063 tnl_type = 0; 2064 tnlhdr_len = 0; 2065 } 2066 if (cpl->csum_calc && err_vec == 0) { 2067 int ipv6 = !!(cpl->l2info & htobe32(F_RXF_IP6)); 2068 2069 /* checksum(s) calculated and found to be correct. */ 2070 2071 MPASS((cpl->l2info & htobe32(F_RXF_IP)) ^ 2072 (cpl->l2info & htobe32(F_RXF_IP6))); 2073 m0->m_pkthdr.csum_data = be16toh(cpl->csum); 2074 if (tnl_type == 0) { 2075 if (!ipv6 && if_getcapenable(ifp) & IFCAP_RXCSUM) { 2076 m0->m_pkthdr.csum_flags = CSUM_L3_CALC | 2077 CSUM_L3_VALID | CSUM_L4_CALC | 2078 CSUM_L4_VALID; 2079 } else if (ipv6 && if_getcapenable(ifp) & IFCAP_RXCSUM_IPV6) { 2080 m0->m_pkthdr.csum_flags = CSUM_L4_CALC | 2081 CSUM_L4_VALID; 2082 } 2083 rxq->rxcsum++; 2084 } else { 2085 MPASS(tnl_type == RX_PKT_TNL_TYPE_VXLAN); 2086 2087 M_HASHTYPE_SETINNER(m0); 2088 if (__predict_false(cpl->ip_frag)) { 2089 /* 2090 * csum_data is for the inner frame (which is an 2091 * IP fragment) and is not 0xffff. There is no 2092 * way to pass the inner csum_data to the stack. 2093 * We don't want the stack to use the inner 2094 * csum_data to validate the outer frame or it 2095 * will get rejected. So we fix csum_data here 2096 * and let sw do the checksum of inner IP 2097 * fragments. 2098 * 2099 * XXX: Need 32b for csum_data2 in an rx mbuf. 2100 * Maybe stuff it into rcv_tstmp? 2101 */ 2102 m0->m_pkthdr.csum_data = 0xffff; 2103 if (ipv6) { 2104 m0->m_pkthdr.csum_flags = CSUM_L4_CALC | 2105 CSUM_L4_VALID; 2106 } else { 2107 m0->m_pkthdr.csum_flags = CSUM_L3_CALC | 2108 CSUM_L3_VALID | CSUM_L4_CALC | 2109 CSUM_L4_VALID; 2110 } 2111 } else { 2112 int outer_ipv6; 2113 2114 MPASS(m0->m_pkthdr.csum_data == 0xffff); 2115 2116 outer_ipv6 = tnlhdr_len >= 2117 sizeof(struct ether_header) + 2118 sizeof(struct ip6_hdr); 2119 m0->m_pkthdr.csum_flags = 2120 sw_csum_flags[outer_ipv6][ipv6]; 2121 } 2122 rxq->vxlan_rxcsum++; 2123 } 2124 } 2125 2126 if (cpl->vlan_ex) { 2127 if (sc->flags & IS_VF && sc->vlan_id) { 2128 /* 2129 * HW is not setup correctly if extracted vlan_id does 2130 * not match the VF's setting. 2131 */ 2132 MPASS(be16toh(cpl->vlan) == sc->vlan_id); 2133 } else { 2134 m0->m_pkthdr.ether_vtag = be16toh(cpl->vlan); 2135 m0->m_flags |= M_VLANTAG; 2136 rxq->vlan_extraction++; 2137 } 2138 } 2139 2140 if (rxq->iq.flags & IQ_RX_TIMESTAMP) { 2141 /* 2142 * Fill up rcv_tstmp but do not set M_TSTMP as 2143 * long as we get a non-zero back from t4_tstmp_to_ns(). 2144 */ 2145 m0->m_pkthdr.rcv_tstmp = t4_tstmp_to_ns(sc, 2146 be64toh(d->rsp.u.last_flit)); 2147 if (m0->m_pkthdr.rcv_tstmp != 0) 2148 m0->m_flags |= M_TSTMP; 2149 } 2150 2151 #ifdef NUMA 2152 m0->m_pkthdr.numa_domain = if_getnumadomain(ifp); 2153 #endif 2154 #if defined(INET) || defined(INET6) 2155 if (rxq->iq.flags & IQ_LRO_ENABLED && tnl_type == 0 && 2156 (M_HASHTYPE_GET(m0) == M_HASHTYPE_RSS_TCP_IPV4 || 2157 M_HASHTYPE_GET(m0) == M_HASHTYPE_RSS_TCP_IPV6)) { 2158 if (sort_before_lro(lro)) { 2159 tcp_lro_queue_mbuf(lro, m0); 2160 return (0); /* queued for sort, then LRO */ 2161 } 2162 if (tcp_lro_rx(lro, m0, 0) == 0) 2163 return (0); /* queued for LRO */ 2164 } 2165 #endif 2166 if_input(ifp, m0); 2167 2168 return (0); 2169 } 2170 2171 /* 2172 * Must drain the wrq or make sure that someone else will. 2173 */ 2174 static void 2175 wrq_tx_drain(void *arg, int n) 2176 { 2177 struct sge_wrq *wrq = arg; 2178 struct sge_eq *eq = &wrq->eq; 2179 2180 EQ_LOCK(eq); 2181 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 2182 drain_wrq_wr_list(wrq->adapter, wrq); 2183 EQ_UNLOCK(eq); 2184 } 2185 2186 static void 2187 drain_wrq_wr_list(struct adapter *sc, struct sge_wrq *wrq) 2188 { 2189 struct sge_eq *eq = &wrq->eq; 2190 u_int available, dbdiff; /* # of hardware descriptors */ 2191 u_int n; 2192 struct wrqe *wr; 2193 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */ 2194 2195 EQ_LOCK_ASSERT_OWNED(eq); 2196 MPASS(TAILQ_EMPTY(&wrq->incomplete_wrs)); 2197 wr = STAILQ_FIRST(&wrq->wr_list); 2198 MPASS(wr != NULL); /* Must be called with something useful to do */ 2199 MPASS(eq->pidx == eq->dbidx); 2200 dbdiff = 0; 2201 2202 do { 2203 eq->cidx = read_hw_cidx(eq); 2204 if (eq->pidx == eq->cidx) 2205 available = eq->sidx - 1; 2206 else 2207 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2208 2209 MPASS(wr->wrq == wrq); 2210 n = howmany(wr->wr_len, EQ_ESIZE); 2211 if (available < n) 2212 break; 2213 2214 dst = (void *)&eq->desc[eq->pidx]; 2215 if (__predict_true(eq->sidx - eq->pidx > n)) { 2216 /* Won't wrap, won't end exactly at the status page. */ 2217 bcopy(&wr->wr[0], dst, wr->wr_len); 2218 eq->pidx += n; 2219 } else { 2220 int first_portion = (eq->sidx - eq->pidx) * EQ_ESIZE; 2221 2222 bcopy(&wr->wr[0], dst, first_portion); 2223 if (wr->wr_len > first_portion) { 2224 bcopy(&wr->wr[first_portion], &eq->desc[0], 2225 wr->wr_len - first_portion); 2226 } 2227 eq->pidx = n - (eq->sidx - eq->pidx); 2228 } 2229 wrq->tx_wrs_copied++; 2230 2231 if (available < eq->sidx / 4 && 2232 atomic_cmpset_int(&eq->equiq, 0, 1)) { 2233 /* 2234 * XXX: This is not 100% reliable with some 2235 * types of WRs. But this is a very unusual 2236 * situation for an ofld/ctrl queue anyway. 2237 */ 2238 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ | 2239 F_FW_WR_EQUEQ); 2240 } 2241 2242 dbdiff += n; 2243 if (dbdiff >= 16) { 2244 ring_eq_db(sc, eq, dbdiff); 2245 dbdiff = 0; 2246 } 2247 2248 STAILQ_REMOVE_HEAD(&wrq->wr_list, link); 2249 free_wrqe(wr); 2250 MPASS(wrq->nwr_pending > 0); 2251 wrq->nwr_pending--; 2252 MPASS(wrq->ndesc_needed >= n); 2253 wrq->ndesc_needed -= n; 2254 } while ((wr = STAILQ_FIRST(&wrq->wr_list)) != NULL); 2255 2256 if (dbdiff) 2257 ring_eq_db(sc, eq, dbdiff); 2258 } 2259 2260 /* 2261 * Doesn't fail. Holds on to work requests it can't send right away. 2262 */ 2263 void 2264 t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, struct wrqe *wr) 2265 { 2266 #ifdef INVARIANTS 2267 struct sge_eq *eq = &wrq->eq; 2268 #endif 2269 2270 EQ_LOCK_ASSERT_OWNED(eq); 2271 MPASS(wr != NULL); 2272 MPASS(wr->wr_len > 0 && wr->wr_len <= SGE_MAX_WR_LEN); 2273 MPASS((wr->wr_len & 0x7) == 0); 2274 2275 STAILQ_INSERT_TAIL(&wrq->wr_list, wr, link); 2276 wrq->nwr_pending++; 2277 wrq->ndesc_needed += howmany(wr->wr_len, EQ_ESIZE); 2278 2279 if (!TAILQ_EMPTY(&wrq->incomplete_wrs)) 2280 return; /* commit_wrq_wr will drain wr_list as well. */ 2281 2282 drain_wrq_wr_list(sc, wrq); 2283 2284 /* Doorbell must have caught up to the pidx. */ 2285 MPASS(eq->pidx == eq->dbidx); 2286 } 2287 2288 void 2289 t4_update_fl_bufsize(if_t ifp) 2290 { 2291 struct vi_info *vi = if_getsoftc(ifp); 2292 struct adapter *sc = vi->adapter; 2293 struct sge_rxq *rxq; 2294 #ifdef TCP_OFFLOAD 2295 struct sge_ofld_rxq *ofld_rxq; 2296 #endif 2297 struct sge_fl *fl; 2298 int i, maxp; 2299 2300 maxp = max_rx_payload(sc, ifp, false); 2301 for_each_rxq(vi, i, rxq) { 2302 fl = &rxq->fl; 2303 2304 FL_LOCK(fl); 2305 fl->zidx = find_refill_source(sc, maxp, 2306 fl->flags & FL_BUF_PACKING); 2307 FL_UNLOCK(fl); 2308 } 2309 #ifdef TCP_OFFLOAD 2310 maxp = max_rx_payload(sc, ifp, true); 2311 for_each_ofld_rxq(vi, i, ofld_rxq) { 2312 fl = &ofld_rxq->fl; 2313 2314 FL_LOCK(fl); 2315 fl->zidx = find_refill_source(sc, maxp, 2316 fl->flags & FL_BUF_PACKING); 2317 FL_UNLOCK(fl); 2318 } 2319 #endif 2320 } 2321 2322 #ifdef RATELIMIT 2323 static inline int 2324 mbuf_eo_nsegs(struct mbuf *m) 2325 { 2326 2327 M_ASSERTPKTHDR(m); 2328 return (m->m_pkthdr.PH_loc.eight[1]); 2329 } 2330 2331 #if defined(INET) || defined(INET6) 2332 static inline void 2333 set_mbuf_eo_nsegs(struct mbuf *m, uint8_t nsegs) 2334 { 2335 2336 M_ASSERTPKTHDR(m); 2337 m->m_pkthdr.PH_loc.eight[1] = nsegs; 2338 } 2339 #endif 2340 2341 static inline int 2342 mbuf_eo_len16(struct mbuf *m) 2343 { 2344 int n; 2345 2346 M_ASSERTPKTHDR(m); 2347 n = m->m_pkthdr.PH_loc.eight[2]; 2348 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16); 2349 2350 return (n); 2351 } 2352 2353 #if defined(INET) || defined(INET6) 2354 static inline void 2355 set_mbuf_eo_len16(struct mbuf *m, uint8_t len16) 2356 { 2357 2358 M_ASSERTPKTHDR(m); 2359 m->m_pkthdr.PH_loc.eight[2] = len16; 2360 } 2361 #endif 2362 2363 static inline int 2364 mbuf_eo_tsclk_tsoff(struct mbuf *m) 2365 { 2366 2367 M_ASSERTPKTHDR(m); 2368 return (m->m_pkthdr.PH_loc.eight[3]); 2369 } 2370 2371 #if defined(INET) || defined(INET6) 2372 static inline void 2373 set_mbuf_eo_tsclk_tsoff(struct mbuf *m, uint8_t tsclk_tsoff) 2374 { 2375 2376 M_ASSERTPKTHDR(m); 2377 m->m_pkthdr.PH_loc.eight[3] = tsclk_tsoff; 2378 } 2379 #endif 2380 2381 static inline int 2382 needs_eo(struct m_snd_tag *mst) 2383 { 2384 2385 return (mst != NULL && mst->sw->type == IF_SND_TAG_TYPE_RATE_LIMIT); 2386 } 2387 #endif 2388 2389 /* 2390 * Try to allocate an mbuf to contain a raw work request. To make it 2391 * easy to construct the work request, don't allocate a chain but a 2392 * single mbuf. 2393 */ 2394 struct mbuf * 2395 alloc_wr_mbuf(int len, int how) 2396 { 2397 struct mbuf *m; 2398 2399 if (len <= MHLEN) 2400 m = m_gethdr(how, MT_DATA); 2401 else if (len <= MCLBYTES) 2402 m = m_getcl(how, MT_DATA, M_PKTHDR); 2403 else 2404 m = NULL; 2405 if (m == NULL) 2406 return (NULL); 2407 m->m_pkthdr.len = len; 2408 m->m_len = len; 2409 set_mbuf_cflags(m, MC_RAW_WR); 2410 set_mbuf_len16(m, howmany(len, 16)); 2411 return (m); 2412 } 2413 2414 static inline bool 2415 needs_hwcsum(struct mbuf *m) 2416 { 2417 const uint32_t csum_flags = CSUM_IP | CSUM_IP_UDP | CSUM_IP_TCP | 2418 CSUM_IP_TSO | CSUM_INNER_IP | CSUM_INNER_IP_UDP | 2419 CSUM_INNER_IP_TCP | CSUM_INNER_IP_TSO | CSUM_IP6_UDP | 2420 CSUM_IP6_TCP | CSUM_IP6_TSO | CSUM_INNER_IP6_UDP | 2421 CSUM_INNER_IP6_TCP | CSUM_INNER_IP6_TSO; 2422 2423 M_ASSERTPKTHDR(m); 2424 2425 return (m->m_pkthdr.csum_flags & csum_flags); 2426 } 2427 2428 static inline bool 2429 needs_tso(struct mbuf *m) 2430 { 2431 const uint32_t csum_flags = CSUM_IP_TSO | CSUM_IP6_TSO | 2432 CSUM_INNER_IP_TSO | CSUM_INNER_IP6_TSO; 2433 2434 M_ASSERTPKTHDR(m); 2435 2436 return (m->m_pkthdr.csum_flags & csum_flags); 2437 } 2438 2439 static inline bool 2440 needs_vxlan_csum(struct mbuf *m) 2441 { 2442 2443 M_ASSERTPKTHDR(m); 2444 2445 return (m->m_pkthdr.csum_flags & CSUM_ENCAP_VXLAN); 2446 } 2447 2448 static inline bool 2449 needs_vxlan_tso(struct mbuf *m) 2450 { 2451 const uint32_t csum_flags = CSUM_ENCAP_VXLAN | CSUM_INNER_IP_TSO | 2452 CSUM_INNER_IP6_TSO; 2453 2454 M_ASSERTPKTHDR(m); 2455 2456 return ((m->m_pkthdr.csum_flags & csum_flags) != 0 && 2457 (m->m_pkthdr.csum_flags & csum_flags) != CSUM_ENCAP_VXLAN); 2458 } 2459 2460 #if defined(INET) || defined(INET6) 2461 static inline bool 2462 needs_inner_tcp_csum(struct mbuf *m) 2463 { 2464 const uint32_t csum_flags = CSUM_INNER_IP_TSO | CSUM_INNER_IP6_TSO; 2465 2466 M_ASSERTPKTHDR(m); 2467 2468 return (m->m_pkthdr.csum_flags & csum_flags); 2469 } 2470 #endif 2471 2472 static inline bool 2473 needs_l3_csum(struct mbuf *m) 2474 { 2475 const uint32_t csum_flags = CSUM_IP | CSUM_IP_TSO | CSUM_INNER_IP | 2476 CSUM_INNER_IP_TSO; 2477 2478 M_ASSERTPKTHDR(m); 2479 2480 return (m->m_pkthdr.csum_flags & csum_flags); 2481 } 2482 2483 static inline bool 2484 needs_outer_tcp_csum(struct mbuf *m) 2485 { 2486 const uint32_t csum_flags = CSUM_IP_TCP | CSUM_IP_TSO | CSUM_IP6_TCP | 2487 CSUM_IP6_TSO; 2488 2489 M_ASSERTPKTHDR(m); 2490 2491 return (m->m_pkthdr.csum_flags & csum_flags); 2492 } 2493 2494 #ifdef RATELIMIT 2495 static inline bool 2496 needs_outer_l4_csum(struct mbuf *m) 2497 { 2498 const uint32_t csum_flags = CSUM_IP_UDP | CSUM_IP_TCP | CSUM_IP_TSO | 2499 CSUM_IP6_UDP | CSUM_IP6_TCP | CSUM_IP6_TSO; 2500 2501 M_ASSERTPKTHDR(m); 2502 2503 return (m->m_pkthdr.csum_flags & csum_flags); 2504 } 2505 2506 static inline bool 2507 needs_outer_udp_csum(struct mbuf *m) 2508 { 2509 const uint32_t csum_flags = CSUM_IP_UDP | CSUM_IP6_UDP; 2510 2511 M_ASSERTPKTHDR(m); 2512 2513 return (m->m_pkthdr.csum_flags & csum_flags); 2514 } 2515 #endif 2516 2517 static inline bool 2518 needs_vlan_insertion(struct mbuf *m) 2519 { 2520 2521 M_ASSERTPKTHDR(m); 2522 2523 return (m->m_flags & M_VLANTAG); 2524 } 2525 2526 #if defined(INET) || defined(INET6) 2527 static void * 2528 m_advance(struct mbuf **pm, int *poffset, int len) 2529 { 2530 struct mbuf *m = *pm; 2531 int offset = *poffset; 2532 uintptr_t p = 0; 2533 2534 MPASS(len > 0); 2535 2536 for (;;) { 2537 if (offset + len < m->m_len) { 2538 offset += len; 2539 p = mtod(m, uintptr_t) + offset; 2540 break; 2541 } 2542 len -= m->m_len - offset; 2543 m = m->m_next; 2544 offset = 0; 2545 MPASS(m != NULL); 2546 } 2547 *poffset = offset; 2548 *pm = m; 2549 return ((void *)p); 2550 } 2551 #endif 2552 2553 static inline int 2554 count_mbuf_ext_pgs(struct mbuf *m, int skip, vm_paddr_t *nextaddr) 2555 { 2556 vm_paddr_t paddr; 2557 int i, len, off, pglen, pgoff, seglen, segoff; 2558 int nsegs = 0; 2559 2560 M_ASSERTEXTPG(m); 2561 off = mtod(m, vm_offset_t); 2562 len = m->m_len; 2563 off += skip; 2564 len -= skip; 2565 2566 if (m->m_epg_hdrlen != 0) { 2567 if (off >= m->m_epg_hdrlen) { 2568 off -= m->m_epg_hdrlen; 2569 } else { 2570 seglen = m->m_epg_hdrlen - off; 2571 segoff = off; 2572 seglen = min(seglen, len); 2573 off = 0; 2574 len -= seglen; 2575 paddr = pmap_kextract( 2576 (vm_offset_t)&m->m_epg_hdr[segoff]); 2577 if (*nextaddr != paddr) 2578 nsegs++; 2579 *nextaddr = paddr + seglen; 2580 } 2581 } 2582 pgoff = m->m_epg_1st_off; 2583 for (i = 0; i < m->m_epg_npgs && len > 0; i++) { 2584 pglen = m_epg_pagelen(m, i, pgoff); 2585 if (off >= pglen) { 2586 off -= pglen; 2587 pgoff = 0; 2588 continue; 2589 } 2590 seglen = pglen - off; 2591 segoff = pgoff + off; 2592 off = 0; 2593 seglen = min(seglen, len); 2594 len -= seglen; 2595 paddr = m->m_epg_pa[i] + segoff; 2596 if (*nextaddr != paddr) 2597 nsegs++; 2598 *nextaddr = paddr + seglen; 2599 pgoff = 0; 2600 }; 2601 if (len != 0) { 2602 seglen = min(len, m->m_epg_trllen - off); 2603 len -= seglen; 2604 paddr = pmap_kextract((vm_offset_t)&m->m_epg_trail[off]); 2605 if (*nextaddr != paddr) 2606 nsegs++; 2607 *nextaddr = paddr + seglen; 2608 } 2609 2610 return (nsegs); 2611 } 2612 2613 2614 /* 2615 * Can deal with empty mbufs in the chain that have m_len = 0, but the chain 2616 * must have at least one mbuf that's not empty. It is possible for this 2617 * routine to return 0 if skip accounts for all the contents of the mbuf chain. 2618 */ 2619 static inline int 2620 count_mbuf_nsegs(struct mbuf *m, int skip, uint8_t *cflags) 2621 { 2622 vm_paddr_t nextaddr, paddr; 2623 vm_offset_t va; 2624 int len, nsegs; 2625 2626 M_ASSERTPKTHDR(m); 2627 MPASS(m->m_pkthdr.len > 0); 2628 MPASS(m->m_pkthdr.len >= skip); 2629 2630 nsegs = 0; 2631 nextaddr = 0; 2632 for (; m; m = m->m_next) { 2633 len = m->m_len; 2634 if (__predict_false(len == 0)) 2635 continue; 2636 if (skip >= len) { 2637 skip -= len; 2638 continue; 2639 } 2640 if ((m->m_flags & M_EXTPG) != 0) { 2641 *cflags |= MC_NOMAP; 2642 nsegs += count_mbuf_ext_pgs(m, skip, &nextaddr); 2643 skip = 0; 2644 continue; 2645 } 2646 va = mtod(m, vm_offset_t) + skip; 2647 len -= skip; 2648 skip = 0; 2649 paddr = pmap_kextract(va); 2650 nsegs += sglist_count((void *)(uintptr_t)va, len); 2651 if (paddr == nextaddr) 2652 nsegs--; 2653 nextaddr = pmap_kextract(va + len - 1) + 1; 2654 } 2655 2656 return (nsegs); 2657 } 2658 2659 /* 2660 * The maximum number of segments that can fit in a WR. 2661 */ 2662 static int 2663 max_nsegs_allowed(struct mbuf *m, bool vm_wr) 2664 { 2665 2666 if (vm_wr) { 2667 if (needs_tso(m)) 2668 return (TX_SGL_SEGS_VM_TSO); 2669 return (TX_SGL_SEGS_VM); 2670 } 2671 2672 if (needs_tso(m)) { 2673 if (needs_vxlan_tso(m)) 2674 return (TX_SGL_SEGS_VXLAN_TSO); 2675 else 2676 return (TX_SGL_SEGS_TSO); 2677 } 2678 2679 return (TX_SGL_SEGS); 2680 } 2681 2682 static struct timeval txerr_ratecheck = {0}; 2683 static const struct timeval txerr_interval = {3, 0}; 2684 2685 /* 2686 * Analyze the mbuf to determine its tx needs. The mbuf passed in may change: 2687 * a) caller can assume it's been freed if this function returns with an error. 2688 * b) it may get defragged up if the gather list is too long for the hardware. 2689 */ 2690 int 2691 parse_pkt(struct mbuf **mp, bool vm_wr) 2692 { 2693 struct mbuf *m0 = *mp, *m; 2694 int rc, nsegs, defragged = 0; 2695 struct ether_header *eh; 2696 #ifdef INET 2697 void *l3hdr; 2698 #endif 2699 #if defined(INET) || defined(INET6) 2700 int offset; 2701 struct tcphdr *tcp; 2702 #endif 2703 #if defined(KERN_TLS) || defined(RATELIMIT) 2704 struct m_snd_tag *mst; 2705 #endif 2706 uint16_t eh_type; 2707 uint8_t cflags; 2708 2709 cflags = 0; 2710 M_ASSERTPKTHDR(m0); 2711 if (__predict_false(m0->m_pkthdr.len < ETHER_HDR_LEN)) { 2712 rc = EINVAL; 2713 fail: 2714 m_freem(m0); 2715 *mp = NULL; 2716 return (rc); 2717 } 2718 restart: 2719 /* 2720 * First count the number of gather list segments in the payload. 2721 * Defrag the mbuf if nsegs exceeds the hardware limit. 2722 */ 2723 M_ASSERTPKTHDR(m0); 2724 MPASS(m0->m_pkthdr.len > 0); 2725 nsegs = count_mbuf_nsegs(m0, 0, &cflags); 2726 #if defined(KERN_TLS) || defined(RATELIMIT) 2727 if (m0->m_pkthdr.csum_flags & CSUM_SND_TAG) 2728 mst = m0->m_pkthdr.snd_tag; 2729 else 2730 mst = NULL; 2731 #endif 2732 #ifdef KERN_TLS 2733 if (mst != NULL && mst->sw->type == IF_SND_TAG_TYPE_TLS) { 2734 struct vi_info *vi = if_getsoftc(mst->ifp); 2735 2736 cflags |= MC_TLS; 2737 set_mbuf_cflags(m0, cflags); 2738 if (is_t6(vi->pi->adapter)) 2739 rc = t6_ktls_parse_pkt(m0); 2740 else 2741 rc = t7_ktls_parse_pkt(m0); 2742 if (rc != 0) 2743 goto fail; 2744 return (EINPROGRESS); 2745 } 2746 #endif 2747 if (nsegs > max_nsegs_allowed(m0, vm_wr)) { 2748 if (defragged++ > 0) { 2749 rc = EFBIG; 2750 goto fail; 2751 } 2752 counter_u64_add(defrags, 1); 2753 if ((m = m_defrag(m0, M_NOWAIT)) == NULL) { 2754 rc = ENOMEM; 2755 goto fail; 2756 } 2757 *mp = m0 = m; /* update caller's copy after defrag */ 2758 goto restart; 2759 } 2760 2761 if (__predict_false(nsegs > 2 && m0->m_pkthdr.len <= MHLEN && 2762 !(cflags & MC_NOMAP))) { 2763 counter_u64_add(pullups, 1); 2764 m0 = m_pullup(m0, m0->m_pkthdr.len); 2765 if (m0 == NULL) { 2766 /* Should have left well enough alone. */ 2767 rc = EFBIG; 2768 goto fail; 2769 } 2770 *mp = m0; /* update caller's copy after pullup */ 2771 goto restart; 2772 } 2773 set_mbuf_nsegs(m0, nsegs); 2774 set_mbuf_cflags(m0, cflags); 2775 calculate_mbuf_len16(m0, vm_wr); 2776 2777 #ifdef RATELIMIT 2778 /* 2779 * Ethofld is limited to TCP and UDP for now, and only when L4 hw 2780 * checksumming is enabled. needs_outer_l4_csum happens to check for 2781 * all the right things. 2782 */ 2783 if (__predict_false(needs_eo(mst) && !needs_outer_l4_csum(m0))) { 2784 m_snd_tag_rele(m0->m_pkthdr.snd_tag); 2785 m0->m_pkthdr.snd_tag = NULL; 2786 m0->m_pkthdr.csum_flags &= ~CSUM_SND_TAG; 2787 mst = NULL; 2788 } 2789 #endif 2790 2791 if (!needs_hwcsum(m0) 2792 #ifdef RATELIMIT 2793 && !needs_eo(mst) 2794 #endif 2795 ) 2796 return (0); 2797 2798 m = m0; 2799 eh = mtod(m, struct ether_header *); 2800 eh_type = ntohs(eh->ether_type); 2801 if (eh_type == ETHERTYPE_VLAN) { 2802 struct ether_vlan_header *evh = (void *)eh; 2803 2804 eh_type = ntohs(evh->evl_proto); 2805 m0->m_pkthdr.l2hlen = sizeof(*evh); 2806 } else 2807 m0->m_pkthdr.l2hlen = sizeof(*eh); 2808 2809 #if defined(INET) || defined(INET6) 2810 offset = 0; 2811 #ifdef INET 2812 l3hdr = m_advance(&m, &offset, m0->m_pkthdr.l2hlen); 2813 #else 2814 m_advance(&m, &offset, m0->m_pkthdr.l2hlen); 2815 #endif 2816 #endif 2817 2818 switch (eh_type) { 2819 #ifdef INET6 2820 case ETHERTYPE_IPV6: 2821 m0->m_pkthdr.l3hlen = sizeof(struct ip6_hdr); 2822 break; 2823 #endif 2824 #ifdef INET 2825 case ETHERTYPE_IP: 2826 { 2827 struct ip *ip = l3hdr; 2828 2829 if (needs_vxlan_csum(m0)) { 2830 /* Driver will do the outer IP hdr checksum. */ 2831 ip->ip_sum = 0; 2832 if (needs_vxlan_tso(m0)) { 2833 const uint16_t ipl = ip->ip_len; 2834 2835 ip->ip_len = 0; 2836 ip->ip_sum = ~in_cksum_hdr(ip); 2837 ip->ip_len = ipl; 2838 } else 2839 ip->ip_sum = in_cksum_hdr(ip); 2840 } 2841 m0->m_pkthdr.l3hlen = ip->ip_hl << 2; 2842 break; 2843 } 2844 #endif 2845 default: 2846 if (ratecheck(&txerr_ratecheck, &txerr_interval)) { 2847 log(LOG_ERR, "%s: ethertype 0x%04x unknown. " 2848 "if_cxgbe must be compiled with the same " 2849 "INET/INET6 options as the kernel.\n", __func__, 2850 eh_type); 2851 } 2852 rc = EINVAL; 2853 goto fail; 2854 } 2855 2856 #if defined(INET) || defined(INET6) 2857 if (needs_vxlan_csum(m0)) { 2858 m0->m_pkthdr.l4hlen = sizeof(struct udphdr); 2859 m0->m_pkthdr.l5hlen = sizeof(struct vxlan_header); 2860 2861 /* Inner headers. */ 2862 eh = m_advance(&m, &offset, m0->m_pkthdr.l3hlen + 2863 sizeof(struct udphdr) + sizeof(struct vxlan_header)); 2864 eh_type = ntohs(eh->ether_type); 2865 if (eh_type == ETHERTYPE_VLAN) { 2866 struct ether_vlan_header *evh = (void *)eh; 2867 2868 eh_type = ntohs(evh->evl_proto); 2869 m0->m_pkthdr.inner_l2hlen = sizeof(*evh); 2870 } else 2871 m0->m_pkthdr.inner_l2hlen = sizeof(*eh); 2872 #ifdef INET 2873 l3hdr = m_advance(&m, &offset, m0->m_pkthdr.inner_l2hlen); 2874 #else 2875 m_advance(&m, &offset, m0->m_pkthdr.inner_l2hlen); 2876 #endif 2877 2878 switch (eh_type) { 2879 #ifdef INET6 2880 case ETHERTYPE_IPV6: 2881 m0->m_pkthdr.inner_l3hlen = sizeof(struct ip6_hdr); 2882 break; 2883 #endif 2884 #ifdef INET 2885 case ETHERTYPE_IP: 2886 { 2887 struct ip *ip = l3hdr; 2888 2889 m0->m_pkthdr.inner_l3hlen = ip->ip_hl << 2; 2890 break; 2891 } 2892 #endif 2893 default: 2894 if (ratecheck(&txerr_ratecheck, &txerr_interval)) { 2895 log(LOG_ERR, "%s: VXLAN hw offload requested" 2896 "with unknown ethertype 0x%04x. if_cxgbe " 2897 "must be compiled with the same INET/INET6 " 2898 "options as the kernel.\n", __func__, 2899 eh_type); 2900 } 2901 rc = EINVAL; 2902 goto fail; 2903 } 2904 if (needs_inner_tcp_csum(m0)) { 2905 tcp = m_advance(&m, &offset, m0->m_pkthdr.inner_l3hlen); 2906 m0->m_pkthdr.inner_l4hlen = tcp->th_off * 4; 2907 } 2908 MPASS((m0->m_pkthdr.csum_flags & CSUM_SND_TAG) == 0); 2909 m0->m_pkthdr.csum_flags &= CSUM_INNER_IP6_UDP | 2910 CSUM_INNER_IP6_TCP | CSUM_INNER_IP6_TSO | CSUM_INNER_IP | 2911 CSUM_INNER_IP_UDP | CSUM_INNER_IP_TCP | CSUM_INNER_IP_TSO | 2912 CSUM_ENCAP_VXLAN; 2913 } 2914 2915 if (needs_outer_tcp_csum(m0)) { 2916 tcp = m_advance(&m, &offset, m0->m_pkthdr.l3hlen); 2917 m0->m_pkthdr.l4hlen = tcp->th_off * 4; 2918 #ifdef RATELIMIT 2919 if (tsclk >= 0 && *(uint32_t *)(tcp + 1) == ntohl(0x0101080a)) { 2920 set_mbuf_eo_tsclk_tsoff(m0, 2921 V_FW_ETH_TX_EO_WR_TSCLK(tsclk) | 2922 V_FW_ETH_TX_EO_WR_TSOFF(sizeof(*tcp) / 2 + 1)); 2923 } else 2924 set_mbuf_eo_tsclk_tsoff(m0, 0); 2925 } else if (needs_outer_udp_csum(m0)) { 2926 m0->m_pkthdr.l4hlen = sizeof(struct udphdr); 2927 #endif 2928 } 2929 #ifdef RATELIMIT 2930 if (needs_eo(mst)) { 2931 u_int immhdrs; 2932 2933 /* EO WRs have the headers in the WR and not the GL. */ 2934 immhdrs = m0->m_pkthdr.l2hlen + m0->m_pkthdr.l3hlen + 2935 m0->m_pkthdr.l4hlen; 2936 cflags = 0; 2937 nsegs = count_mbuf_nsegs(m0, immhdrs, &cflags); 2938 MPASS(cflags == mbuf_cflags(m0)); 2939 set_mbuf_eo_nsegs(m0, nsegs); 2940 set_mbuf_eo_len16(m0, 2941 txpkt_eo_len16(nsegs, immhdrs, needs_tso(m0))); 2942 rc = ethofld_transmit(mst->ifp, m0); 2943 if (rc != 0) 2944 goto fail; 2945 return (EINPROGRESS); 2946 } 2947 #endif 2948 #endif 2949 MPASS(m0 == *mp); 2950 return (0); 2951 } 2952 2953 void * 2954 start_wrq_wr(struct sge_wrq *wrq, int len16, struct wrq_cookie *cookie) 2955 { 2956 struct sge_eq *eq = &wrq->eq; 2957 struct adapter *sc = wrq->adapter; 2958 int ndesc, available; 2959 struct wrqe *wr; 2960 void *w; 2961 2962 MPASS(len16 > 0); 2963 ndesc = tx_len16_to_desc(len16); 2964 MPASS(ndesc > 0 && ndesc <= SGE_MAX_WR_NDESC); 2965 2966 EQ_LOCK(eq); 2967 if (__predict_false((eq->flags & EQ_HW_ALLOCATED) == 0)) { 2968 EQ_UNLOCK(eq); 2969 return (NULL); 2970 } 2971 2972 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 2973 drain_wrq_wr_list(sc, wrq); 2974 2975 if (!STAILQ_EMPTY(&wrq->wr_list)) { 2976 slowpath: 2977 EQ_UNLOCK(eq); 2978 wr = alloc_wrqe(len16 * 16, wrq); 2979 if (__predict_false(wr == NULL)) 2980 return (NULL); 2981 cookie->pidx = -1; 2982 cookie->ndesc = ndesc; 2983 return (&wr->wr); 2984 } 2985 2986 eq->cidx = read_hw_cidx(eq); 2987 if (eq->pidx == eq->cidx) 2988 available = eq->sidx - 1; 2989 else 2990 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2991 if (available < ndesc) 2992 goto slowpath; 2993 2994 cookie->pidx = eq->pidx; 2995 cookie->ndesc = ndesc; 2996 TAILQ_INSERT_TAIL(&wrq->incomplete_wrs, cookie, link); 2997 2998 w = &eq->desc[eq->pidx]; 2999 IDXINCR(eq->pidx, ndesc, eq->sidx); 3000 if (__predict_false(cookie->pidx + ndesc > eq->sidx)) { 3001 w = &wrq->ss[0]; 3002 wrq->ss_pidx = cookie->pidx; 3003 wrq->ss_len = len16 * 16; 3004 } 3005 3006 EQ_UNLOCK(eq); 3007 3008 return (w); 3009 } 3010 3011 void 3012 commit_wrq_wr(struct sge_wrq *wrq, void *w, struct wrq_cookie *cookie) 3013 { 3014 struct sge_eq *eq = &wrq->eq; 3015 struct adapter *sc = wrq->adapter; 3016 int ndesc, pidx; 3017 struct wrq_cookie *prev, *next; 3018 3019 if (cookie->pidx == -1) { 3020 struct wrqe *wr = __containerof(w, struct wrqe, wr); 3021 3022 t4_wrq_tx(sc, wr); 3023 return; 3024 } 3025 3026 if (__predict_false(w == &wrq->ss[0])) { 3027 int n = (eq->sidx - wrq->ss_pidx) * EQ_ESIZE; 3028 3029 MPASS(wrq->ss_len > n); /* WR had better wrap around. */ 3030 bcopy(&wrq->ss[0], &eq->desc[wrq->ss_pidx], n); 3031 bcopy(&wrq->ss[n], &eq->desc[0], wrq->ss_len - n); 3032 wrq->tx_wrs_ss++; 3033 } else 3034 wrq->tx_wrs_direct++; 3035 3036 EQ_LOCK(eq); 3037 ndesc = cookie->ndesc; /* Can be more than SGE_MAX_WR_NDESC here. */ 3038 pidx = cookie->pidx; 3039 MPASS(pidx >= 0 && pidx < eq->sidx); 3040 prev = TAILQ_PREV(cookie, wrq_incomplete_wrs, link); 3041 next = TAILQ_NEXT(cookie, link); 3042 if (prev == NULL) { 3043 MPASS(pidx == eq->dbidx); 3044 if (next == NULL || ndesc >= 16) { 3045 int available; 3046 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */ 3047 3048 /* 3049 * Note that the WR via which we'll request tx updates 3050 * is at pidx and not eq->pidx, which has moved on 3051 * already. 3052 */ 3053 dst = (void *)&eq->desc[pidx]; 3054 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 3055 if (available < eq->sidx / 4 && 3056 atomic_cmpset_int(&eq->equiq, 0, 1)) { 3057 /* 3058 * XXX: This is not 100% reliable with some 3059 * types of WRs. But this is a very unusual 3060 * situation for an ofld/ctrl queue anyway. 3061 */ 3062 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ | 3063 F_FW_WR_EQUEQ); 3064 } 3065 3066 if (__predict_true(eq->flags & EQ_HW_ALLOCATED)) 3067 ring_eq_db(wrq->adapter, eq, ndesc); 3068 else 3069 IDXINCR(eq->dbidx, ndesc, eq->sidx); 3070 } else { 3071 MPASS(IDXDIFF(next->pidx, pidx, eq->sidx) == ndesc); 3072 next->pidx = pidx; 3073 next->ndesc += ndesc; 3074 } 3075 } else { 3076 MPASS(IDXDIFF(pidx, prev->pidx, eq->sidx) == prev->ndesc); 3077 prev->ndesc += ndesc; 3078 } 3079 TAILQ_REMOVE(&wrq->incomplete_wrs, cookie, link); 3080 3081 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 3082 drain_wrq_wr_list(sc, wrq); 3083 3084 #ifdef INVARIANTS 3085 if (TAILQ_EMPTY(&wrq->incomplete_wrs)) { 3086 /* Doorbell must have caught up to the pidx. */ 3087 MPASS(wrq->eq.pidx == wrq->eq.dbidx); 3088 } 3089 #endif 3090 EQ_UNLOCK(eq); 3091 } 3092 3093 static u_int 3094 can_resume_eth_tx(struct mp_ring *r) 3095 { 3096 struct sge_eq *eq = r->cookie; 3097 3098 return (total_available_tx_desc(eq) > eq->sidx / 8); 3099 } 3100 3101 static inline bool 3102 cannot_use_txpkts(struct mbuf *m) 3103 { 3104 /* maybe put a GL limit too, to avoid silliness? */ 3105 3106 return (needs_tso(m) || (mbuf_cflags(m) & (MC_RAW_WR | MC_TLS)) != 0); 3107 } 3108 3109 static inline int 3110 discard_tx(struct sge_eq *eq) 3111 { 3112 3113 return ((eq->flags & (EQ_ENABLED | EQ_QFLUSH)) != EQ_ENABLED); 3114 } 3115 3116 static inline int 3117 wr_can_update_eq(void *p) 3118 { 3119 struct fw_eth_tx_pkts_wr *wr = p; 3120 3121 switch (G_FW_WR_OP(be32toh(wr->op_pkd))) { 3122 case FW_ULPTX_WR: 3123 case FW_ETH_TX_PKT_WR: 3124 case FW_ETH_TX_PKTS_WR: 3125 case FW_ETH_TX_PKTS2_WR: 3126 case FW_ETH_TX_PKT_VM_WR: 3127 case FW_ETH_TX_PKTS_VM_WR: 3128 return (1); 3129 default: 3130 return (0); 3131 } 3132 } 3133 3134 static inline void 3135 set_txupdate_flags(struct sge_txq *txq, u_int avail, 3136 struct fw_eth_tx_pkt_wr *wr) 3137 { 3138 struct sge_eq *eq = &txq->eq; 3139 struct txpkts *txp = &txq->txp; 3140 3141 if ((txp->npkt > 0 || avail < eq->sidx / 2) && 3142 atomic_cmpset_int(&eq->equiq, 0, 1)) { 3143 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ | F_FW_WR_EQUIQ); 3144 eq->equeqidx = eq->pidx; 3145 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 32) { 3146 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ); 3147 eq->equeqidx = eq->pidx; 3148 } 3149 } 3150 3151 #if defined(__i386__) || defined(__amd64__) 3152 extern uint64_t tsc_freq; 3153 #endif 3154 3155 static inline bool 3156 record_eth_tx_time(struct sge_txq *txq) 3157 { 3158 const uint64_t cycles = get_cyclecount(); 3159 const uint64_t last_tx = txq->last_tx; 3160 #if defined(__i386__) || defined(__amd64__) 3161 const uint64_t itg = tsc_freq * t4_tx_coalesce_gap / 1000000; 3162 #else 3163 const uint64_t itg = 0; 3164 #endif 3165 3166 MPASS(cycles >= last_tx); 3167 txq->last_tx = cycles; 3168 return (cycles - last_tx < itg); 3169 } 3170 3171 /* 3172 * r->items[cidx] to r->items[pidx], with a wraparound at r->size, are ready to 3173 * be consumed. Return the actual number consumed. 0 indicates a stall. 3174 */ 3175 static u_int 3176 eth_tx(struct mp_ring *r, u_int cidx, u_int pidx, bool *coalescing) 3177 { 3178 struct sge_txq *txq = r->cookie; 3179 if_t ifp = txq->ifp; 3180 struct sge_eq *eq = &txq->eq; 3181 struct txpkts *txp = &txq->txp; 3182 struct vi_info *vi = if_getsoftc(ifp); 3183 struct adapter *sc = vi->adapter; 3184 u_int total, remaining; /* # of packets */ 3185 u_int n, avail, dbdiff; /* # of hardware descriptors */ 3186 int i, rc; 3187 struct mbuf *m0; 3188 bool snd, recent_tx; 3189 void *wr; /* start of the last WR written to the ring */ 3190 3191 TXQ_LOCK_ASSERT_OWNED(txq); 3192 recent_tx = record_eth_tx_time(txq); 3193 3194 remaining = IDXDIFF(pidx, cidx, r->size); 3195 if (__predict_false(discard_tx(eq))) { 3196 for (i = 0; i < txp->npkt; i++) 3197 m_freem(txp->mb[i]); 3198 txp->npkt = 0; 3199 while (cidx != pidx) { 3200 m0 = r->items[cidx]; 3201 m_freem(m0); 3202 if (++cidx == r->size) 3203 cidx = 0; 3204 } 3205 reclaim_tx_descs(txq, eq->sidx); 3206 *coalescing = false; 3207 return (remaining); /* emptied */ 3208 } 3209 3210 /* How many hardware descriptors do we have readily available. */ 3211 if (eq->pidx == eq->cidx) 3212 avail = eq->sidx - 1; 3213 else 3214 avail = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 3215 3216 total = 0; 3217 if (remaining == 0) { 3218 txp->score = 0; 3219 txq->txpkts_flush++; 3220 goto send_txpkts; 3221 } 3222 3223 dbdiff = 0; 3224 MPASS(remaining > 0); 3225 while (remaining > 0) { 3226 m0 = r->items[cidx]; 3227 M_ASSERTPKTHDR(m0); 3228 MPASS(m0->m_nextpkt == NULL); 3229 3230 if (avail < 2 * SGE_MAX_WR_NDESC) 3231 avail += reclaim_tx_descs(txq, 64); 3232 3233 if (t4_tx_coalesce == 0 && txp->npkt == 0) 3234 goto skip_coalescing; 3235 if (cannot_use_txpkts(m0)) 3236 txp->score = 0; 3237 else if (recent_tx) { 3238 if (++txp->score == 0) 3239 txp->score = UINT8_MAX; 3240 } else 3241 txp->score = 1; 3242 if (txp->npkt > 0 || remaining > 1 || 3243 txp->score >= t4_tx_coalesce_pkts || 3244 atomic_load_int(&txq->eq.equiq) != 0) { 3245 if (vi->flags & TX_USES_VM_WR) 3246 rc = add_to_txpkts_vf(sc, txq, m0, avail, &snd); 3247 else 3248 rc = add_to_txpkts_pf(sc, txq, m0, avail, &snd); 3249 } else { 3250 snd = false; 3251 rc = EINVAL; 3252 } 3253 if (snd) { 3254 MPASS(txp->npkt > 0); 3255 for (i = 0; i < txp->npkt; i++) 3256 ETHER_BPF_MTAP(ifp, txp->mb[i]); 3257 if (txp->npkt > 1) { 3258 MPASS(avail >= tx_len16_to_desc(txp->len16)); 3259 if (vi->flags & TX_USES_VM_WR) 3260 n = write_txpkts_vm_wr(sc, txq); 3261 else 3262 n = write_txpkts_wr(sc, txq); 3263 } else { 3264 MPASS(avail >= 3265 tx_len16_to_desc(mbuf_len16(txp->mb[0]))); 3266 if (vi->flags & TX_USES_VM_WR) 3267 n = write_txpkt_vm_wr(sc, txq, 3268 txp->mb[0]); 3269 else 3270 n = write_txpkt_wr(sc, txq, txp->mb[0], 3271 avail); 3272 } 3273 MPASS(n <= SGE_MAX_WR_NDESC); 3274 avail -= n; 3275 dbdiff += n; 3276 wr = &eq->desc[eq->pidx]; 3277 IDXINCR(eq->pidx, n, eq->sidx); 3278 txp->npkt = 0; /* emptied */ 3279 } 3280 if (rc == 0) { 3281 /* m0 was coalesced into txq->txpkts. */ 3282 goto next_mbuf; 3283 } 3284 if (rc == EAGAIN) { 3285 /* 3286 * m0 is suitable for tx coalescing but could not be 3287 * combined with the existing txq->txpkts, which has now 3288 * been transmitted. Start a new txpkts with m0. 3289 */ 3290 MPASS(snd); 3291 MPASS(txp->npkt == 0); 3292 continue; 3293 } 3294 3295 MPASS(rc != 0 && rc != EAGAIN); 3296 MPASS(txp->npkt == 0); 3297 skip_coalescing: 3298 n = tx_len16_to_desc(mbuf_len16(m0)); 3299 if (__predict_false(avail < n)) { 3300 avail += reclaim_tx_descs(txq, min(n, 32)); 3301 if (avail < n) 3302 break; /* out of descriptors */ 3303 } 3304 3305 wr = &eq->desc[eq->pidx]; 3306 if (mbuf_cflags(m0) & MC_RAW_WR) { 3307 n = write_raw_wr(txq, wr, m0, avail); 3308 #ifdef KERN_TLS 3309 } else if (mbuf_cflags(m0) & MC_TLS) { 3310 ETHER_BPF_MTAP(ifp, m0); 3311 if (is_t6(sc)) 3312 n = t6_ktls_write_wr(txq, wr, m0, avail); 3313 else 3314 n = t7_ktls_write_wr(txq, wr, m0, avail); 3315 #endif 3316 } else { 3317 ETHER_BPF_MTAP(ifp, m0); 3318 if (vi->flags & TX_USES_VM_WR) 3319 n = write_txpkt_vm_wr(sc, txq, m0); 3320 else 3321 n = write_txpkt_wr(sc, txq, m0, avail); 3322 } 3323 MPASS(n >= 1 && n <= avail); 3324 if (!(mbuf_cflags(m0) & MC_TLS)) 3325 MPASS(n <= SGE_MAX_WR_NDESC); 3326 3327 avail -= n; 3328 dbdiff += n; 3329 IDXINCR(eq->pidx, n, eq->sidx); 3330 3331 if (dbdiff >= 512 / EQ_ESIZE) { /* X_FETCHBURSTMAX_512B */ 3332 if (wr_can_update_eq(wr)) 3333 set_txupdate_flags(txq, avail, wr); 3334 ring_eq_db(sc, eq, dbdiff); 3335 avail += reclaim_tx_descs(txq, 32); 3336 dbdiff = 0; 3337 } 3338 next_mbuf: 3339 total++; 3340 remaining--; 3341 if (__predict_false(++cidx == r->size)) 3342 cidx = 0; 3343 } 3344 if (dbdiff != 0) { 3345 if (wr_can_update_eq(wr)) 3346 set_txupdate_flags(txq, avail, wr); 3347 ring_eq_db(sc, eq, dbdiff); 3348 reclaim_tx_descs(txq, 32); 3349 } else if (eq->pidx == eq->cidx && txp->npkt > 0 && 3350 atomic_load_int(&txq->eq.equiq) == 0) { 3351 /* 3352 * If nothing was submitted to the chip for tx (it was coalesced 3353 * into txpkts instead) and there is no tx update outstanding 3354 * then we need to send txpkts now. 3355 */ 3356 send_txpkts: 3357 MPASS(txp->npkt > 0); 3358 for (i = 0; i < txp->npkt; i++) 3359 ETHER_BPF_MTAP(ifp, txp->mb[i]); 3360 if (txp->npkt > 1) { 3361 MPASS(avail >= tx_len16_to_desc(txp->len16)); 3362 if (vi->flags & TX_USES_VM_WR) 3363 n = write_txpkts_vm_wr(sc, txq); 3364 else 3365 n = write_txpkts_wr(sc, txq); 3366 } else { 3367 MPASS(avail >= 3368 tx_len16_to_desc(mbuf_len16(txp->mb[0]))); 3369 if (vi->flags & TX_USES_VM_WR) 3370 n = write_txpkt_vm_wr(sc, txq, txp->mb[0]); 3371 else 3372 n = write_txpkt_wr(sc, txq, txp->mb[0], avail); 3373 } 3374 MPASS(n <= SGE_MAX_WR_NDESC); 3375 wr = &eq->desc[eq->pidx]; 3376 IDXINCR(eq->pidx, n, eq->sidx); 3377 txp->npkt = 0; /* emptied */ 3378 3379 MPASS(wr_can_update_eq(wr)); 3380 set_txupdate_flags(txq, avail - n, wr); 3381 ring_eq_db(sc, eq, n); 3382 reclaim_tx_descs(txq, 32); 3383 } 3384 *coalescing = txp->npkt > 0; 3385 3386 return (total); 3387 } 3388 3389 static inline void 3390 init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int pktc_idx, 3391 int qsize, int intr_idx, int cong, int qtype) 3392 { 3393 3394 KASSERT(tmr_idx >= 0 && tmr_idx < SGE_NTIMERS, 3395 ("%s: bad tmr_idx %d", __func__, tmr_idx)); 3396 KASSERT(pktc_idx < SGE_NCOUNTERS, /* -ve is ok, means don't use */ 3397 ("%s: bad pktc_idx %d", __func__, pktc_idx)); 3398 KASSERT(intr_idx >= -1 && intr_idx < sc->intr_count, 3399 ("%s: bad intr_idx %d", __func__, intr_idx)); 3400 KASSERT(qtype == FW_IQ_IQTYPE_OTHER || qtype == FW_IQ_IQTYPE_NIC || 3401 qtype == FW_IQ_IQTYPE_OFLD, ("%s: bad qtype %d", __func__, qtype)); 3402 3403 iq->flags = 0; 3404 iq->state = IQS_DISABLED; 3405 iq->adapter = sc; 3406 iq->qtype = qtype; 3407 iq->intr_params = V_QINTR_TIMER_IDX(tmr_idx); 3408 iq->intr_pktc_idx = SGE_NCOUNTERS - 1; 3409 if (pktc_idx >= 0) { 3410 iq->intr_params |= F_QINTR_CNT_EN; 3411 iq->intr_pktc_idx = pktc_idx; 3412 } 3413 iq->qsize = roundup2(qsize, 16); /* See FW_IQ_CMD/iqsize */ 3414 iq->sidx = iq->qsize - sc->params.sge.spg_len / IQ_ESIZE; 3415 iq->intr_idx = intr_idx; 3416 iq->cong_drop = cong; 3417 } 3418 3419 static inline void 3420 init_fl(struct adapter *sc, struct sge_fl *fl, int qsize, int maxp, char *name) 3421 { 3422 struct sge_params *sp = &sc->params.sge; 3423 3424 fl->qsize = qsize; 3425 fl->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE; 3426 strlcpy(fl->lockname, name, sizeof(fl->lockname)); 3427 mtx_init(&fl->fl_lock, fl->lockname, NULL, MTX_DEF); 3428 if (sc->flags & BUF_PACKING_OK && 3429 ((!is_t4(sc) && buffer_packing) || /* T5+: enabled unless 0 */ 3430 (is_t4(sc) && buffer_packing == 1)))/* T4: disabled unless 1 */ 3431 fl->flags |= FL_BUF_PACKING; 3432 fl->zidx = find_refill_source(sc, maxp, fl->flags & FL_BUF_PACKING); 3433 fl->safe_zidx = sc->sge.safe_zidx; 3434 if (fl->flags & FL_BUF_PACKING) { 3435 fl->lowat = roundup2(sp->fl_starve_threshold2, 8); 3436 fl->buf_boundary = sp->pack_boundary; 3437 } else { 3438 fl->lowat = roundup2(sp->fl_starve_threshold, 8); 3439 fl->buf_boundary = 16; 3440 } 3441 if (fl_pad && fl->buf_boundary < sp->pad_boundary) 3442 fl->buf_boundary = sp->pad_boundary; 3443 } 3444 3445 static inline void 3446 init_eq(struct adapter *sc, struct sge_eq *eq, int eqtype, int qsize, 3447 uint8_t port_id, struct sge_iq *iq, char *name) 3448 { 3449 KASSERT(eqtype >= EQ_CTRL && eqtype <= EQ_OFLD, 3450 ("%s: bad qtype %d", __func__, eqtype)); 3451 3452 eq->type = eqtype; 3453 eq->port_id = port_id; 3454 eq->tx_chan = sc->port[port_id]->tx_chan; 3455 eq->hw_port = sc->port[port_id]->hw_port; 3456 eq->iq = iq; 3457 eq->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE; 3458 strlcpy(eq->lockname, name, sizeof(eq->lockname)); 3459 mtx_init(&eq->eq_lock, eq->lockname, NULL, MTX_DEF); 3460 } 3461 3462 int 3463 alloc_ring(struct adapter *sc, size_t len, bus_dma_tag_t *tag, 3464 bus_dmamap_t *map, bus_addr_t *pa, void **va) 3465 { 3466 int rc; 3467 3468 rc = bus_dma_tag_create(sc->dmat, 512, 0, BUS_SPACE_MAXADDR, 3469 BUS_SPACE_MAXADDR, NULL, NULL, len, 1, len, 0, NULL, NULL, tag); 3470 if (rc != 0) { 3471 CH_ERR(sc, "cannot allocate DMA tag: %d\n", rc); 3472 goto done; 3473 } 3474 3475 rc = bus_dmamem_alloc(*tag, va, 3476 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, map); 3477 if (rc != 0) { 3478 CH_ERR(sc, "cannot allocate DMA memory: %d\n", rc); 3479 goto done; 3480 } 3481 3482 rc = bus_dmamap_load(*tag, *map, *va, len, oneseg_dma_callback, pa, 0); 3483 if (rc != 0) { 3484 CH_ERR(sc, "cannot load DMA map: %d\n", rc); 3485 goto done; 3486 } 3487 done: 3488 if (rc) 3489 free_ring(sc, *tag, *map, *pa, *va); 3490 3491 return (rc); 3492 } 3493 3494 int 3495 free_ring(struct adapter *sc, bus_dma_tag_t tag, bus_dmamap_t map, 3496 bus_addr_t pa, void *va) 3497 { 3498 if (pa) 3499 bus_dmamap_unload(tag, map); 3500 if (va) 3501 bus_dmamem_free(tag, va, map); 3502 if (tag) 3503 bus_dma_tag_destroy(tag); 3504 3505 return (0); 3506 } 3507 3508 /* 3509 * Allocates the software resources (mainly memory and sysctl nodes) for an 3510 * ingress queue and an optional freelist. 3511 * 3512 * Sets IQ_SW_ALLOCATED and returns 0 on success. 3513 */ 3514 static int 3515 alloc_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl, 3516 struct sysctl_ctx_list *ctx, struct sysctl_oid *oid) 3517 { 3518 int rc; 3519 size_t len; 3520 struct adapter *sc = vi->adapter; 3521 3522 MPASS(!(iq->flags & IQ_SW_ALLOCATED)); 3523 3524 len = iq->qsize * IQ_ESIZE; 3525 rc = alloc_ring(sc, len, &iq->desc_tag, &iq->desc_map, &iq->ba, 3526 (void **)&iq->desc); 3527 if (rc != 0) 3528 return (rc); 3529 3530 if (fl) { 3531 len = fl->qsize * EQ_ESIZE; 3532 rc = alloc_ring(sc, len, &fl->desc_tag, &fl->desc_map, 3533 &fl->ba, (void **)&fl->desc); 3534 if (rc) { 3535 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, 3536 iq->desc); 3537 return (rc); 3538 } 3539 3540 /* Allocate space for one software descriptor per buffer. */ 3541 fl->sdesc = malloc(fl->sidx * 8 * sizeof(struct fl_sdesc), 3542 M_CXGBE, M_ZERO | M_WAITOK); 3543 3544 add_fl_sysctls(sc, ctx, oid, fl); 3545 iq->flags |= IQ_HAS_FL; 3546 } 3547 add_iq_sysctls(ctx, oid, iq); 3548 iq->flags |= IQ_SW_ALLOCATED; 3549 3550 return (0); 3551 } 3552 3553 /* 3554 * Frees all software resources (memory and locks) associated with an ingress 3555 * queue and an optional freelist. 3556 */ 3557 static void 3558 free_iq_fl(struct adapter *sc, struct sge_iq *iq, struct sge_fl *fl) 3559 { 3560 MPASS(iq->flags & IQ_SW_ALLOCATED); 3561 3562 if (fl) { 3563 MPASS(iq->flags & IQ_HAS_FL); 3564 free_ring(sc, fl->desc_tag, fl->desc_map, fl->ba, fl->desc); 3565 free_fl_buffers(sc, fl); 3566 free(fl->sdesc, M_CXGBE); 3567 mtx_destroy(&fl->fl_lock); 3568 bzero(fl, sizeof(*fl)); 3569 } 3570 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, iq->desc); 3571 bzero(iq, sizeof(*iq)); 3572 } 3573 3574 /* 3575 * Allocates a hardware ingress queue and an optional freelist that will be 3576 * associated with it. 3577 * 3578 * Returns errno on failure. Resources allocated up to that point may still be 3579 * allocated. Caller is responsible for cleanup in case this function fails. 3580 */ 3581 static int 3582 alloc_iq_fl_hwq(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl) 3583 { 3584 int rc, cntxt_id, cong_map; 3585 struct fw_iq_cmd c; 3586 struct adapter *sc = vi->adapter; 3587 struct port_info *pi = vi->pi; 3588 __be32 v = 0; 3589 3590 MPASS (!(iq->flags & IQ_HW_ALLOCATED)); 3591 3592 bzero(&c, sizeof(c)); 3593 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 3594 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) | 3595 V_FW_IQ_CMD_VFN(0)); 3596 3597 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART | 3598 FW_LEN16(c)); 3599 3600 /* Special handling for firmware event queue */ 3601 if (iq == &sc->sge.fwq) 3602 v |= F_FW_IQ_CMD_IQASYNCH; 3603 3604 if (iq->intr_idx < 0) { 3605 /* Forwarded interrupts, all headed to fwq */ 3606 v |= F_FW_IQ_CMD_IQANDST; 3607 v |= V_FW_IQ_CMD_IQANDSTINDEX(sc->sge.fwq.cntxt_id); 3608 } else { 3609 KASSERT(iq->intr_idx < sc->intr_count, 3610 ("%s: invalid direct intr_idx %d", __func__, iq->intr_idx)); 3611 v |= V_FW_IQ_CMD_IQANDSTINDEX(iq->intr_idx); 3612 } 3613 3614 bzero(iq->desc, iq->qsize * IQ_ESIZE); 3615 c.type_to_iqandstindex = htobe32(v | 3616 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) | 3617 V_FW_IQ_CMD_VIID(vi->viid) | 3618 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT)); 3619 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->hw_port) | 3620 F_FW_IQ_CMD_IQGTSMODE | 3621 V_FW_IQ_CMD_IQINTCNTTHRESH(iq->intr_pktc_idx) | 3622 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4)); 3623 c.iqsize = htobe16(iq->qsize); 3624 c.iqaddr = htobe64(iq->ba); 3625 c.iqns_to_fl0congen = htobe32(V_FW_IQ_CMD_IQTYPE(iq->qtype)); 3626 if (iq->cong_drop != -1) { 3627 if (iq->qtype == IQ_ETH) { 3628 if (chip_id(sc) >= CHELSIO_T7) 3629 cong_map = 1 << pi->hw_port; 3630 else 3631 cong_map = pi->rx_e_chan_map; 3632 } else 3633 cong_map = 0; 3634 c.iqns_to_fl0congen |= htobe32(F_FW_IQ_CMD_IQFLINTCONGEN); 3635 } 3636 3637 if (fl) { 3638 bzero(fl->desc, fl->sidx * EQ_ESIZE + sc->params.sge.spg_len); 3639 c.iqns_to_fl0congen |= 3640 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) | 3641 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO | 3642 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) | 3643 (fl->flags & FL_BUF_PACKING ? F_FW_IQ_CMD_FL0PACKEN : 3644 0)); 3645 if (iq->cong_drop != -1) { 3646 c.iqns_to_fl0congen |= 3647 htobe32(V_FW_IQ_CMD_FL0CNGCHMAP(cong_map) | 3648 F_FW_IQ_CMD_FL0CONGCIF | 3649 F_FW_IQ_CMD_FL0CONGEN); 3650 } 3651 c.fl0dcaen_to_fl0cidxfthresh = 3652 htobe16(V_FW_IQ_CMD_FL0FBMIN(chip_id(sc) <= CHELSIO_T5 ? 3653 X_FETCHBURSTMIN_128B : X_FETCHBURSTMIN_64B_T6) | 3654 V_FW_IQ_CMD_FL0FBMAX(chip_id(sc) <= CHELSIO_T5 ? 3655 X_FETCHBURSTMAX_512B : X_FETCHBURSTMAX_256B)); 3656 c.fl0size = htobe16(fl->qsize); 3657 c.fl0addr = htobe64(fl->ba); 3658 } 3659 3660 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3661 if (rc != 0) { 3662 CH_ERR(sc, "failed to create hw ingress queue: %d\n", rc); 3663 return (rc); 3664 } 3665 3666 iq->cidx = 0; 3667 iq->gen = F_RSPD_GEN; 3668 iq->cntxt_id = be16toh(c.iqid); 3669 iq->abs_id = be16toh(c.physiqid); 3670 3671 cntxt_id = iq->cntxt_id - sc->sge.iq_start; 3672 if (cntxt_id >= sc->sge.iqmap_sz) { 3673 panic ("%s: iq->cntxt_id (%d) more than the max (%d)", __func__, 3674 cntxt_id, sc->sge.iqmap_sz - 1); 3675 } 3676 sc->sge.iqmap[cntxt_id] = iq; 3677 3678 if (fl) { 3679 u_int qid; 3680 #ifdef INVARIANTS 3681 int i; 3682 3683 MPASS(!(fl->flags & FL_BUF_RESUME)); 3684 for (i = 0; i < fl->sidx * 8; i++) 3685 MPASS(fl->sdesc[i].cl == NULL); 3686 #endif 3687 fl->cntxt_id = be16toh(c.fl0id); 3688 fl->pidx = fl->cidx = fl->hw_cidx = fl->dbidx = 0; 3689 fl->rx_offset = 0; 3690 fl->flags &= ~(FL_STARVING | FL_DOOMED); 3691 3692 cntxt_id = fl->cntxt_id - sc->sge.eq_start; 3693 if (cntxt_id >= sc->sge.eqmap_sz) { 3694 panic("%s: fl->cntxt_id (%d) more than the max (%d)", 3695 __func__, cntxt_id, sc->sge.eqmap_sz - 1); 3696 } 3697 sc->sge.eqmap[cntxt_id] = (void *)fl; 3698 3699 qid = fl->cntxt_id; 3700 if (isset(&sc->doorbells, DOORBELL_UDB)) { 3701 uint32_t s_qpp = sc->params.sge.eq_s_qpp; 3702 uint32_t mask = (1 << s_qpp) - 1; 3703 volatile uint8_t *udb; 3704 3705 udb = sc->udbs_base + UDBS_DB_OFFSET; 3706 udb += (qid >> s_qpp) << PAGE_SHIFT; 3707 qid &= mask; 3708 if (qid < PAGE_SIZE / UDBS_SEG_SIZE) { 3709 udb += qid << UDBS_SEG_SHIFT; 3710 qid = 0; 3711 } 3712 fl->udb = (volatile void *)udb; 3713 } 3714 fl->dbval = V_QID(qid) | sc->chip_params->sge_fl_db; 3715 3716 FL_LOCK(fl); 3717 /* Enough to make sure the SGE doesn't think it's starved */ 3718 refill_fl(sc, fl, fl->lowat); 3719 FL_UNLOCK(fl); 3720 } 3721 3722 if (chip_id(sc) >= CHELSIO_T5 && !(sc->flags & IS_VF) && 3723 iq->cong_drop != -1) { 3724 t4_sge_set_conm_context(sc, iq->cntxt_id, iq->cong_drop, 3725 cong_map); 3726 } 3727 3728 /* Enable IQ interrupts */ 3729 atomic_store_rel_int(&iq->state, IQS_IDLE); 3730 t4_write_reg(sc, sc->sge_gts_reg, V_SEINTARM(iq->intr_params) | 3731 V_INGRESSQID(iq->cntxt_id)); 3732 3733 iq->flags |= IQ_HW_ALLOCATED; 3734 3735 return (0); 3736 } 3737 3738 static int 3739 free_iq_fl_hwq(struct adapter *sc, struct sge_iq *iq, struct sge_fl *fl) 3740 { 3741 int rc; 3742 3743 MPASS(iq->flags & IQ_HW_ALLOCATED); 3744 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0, FW_IQ_TYPE_FL_INT_CAP, 3745 iq->cntxt_id, fl ? fl->cntxt_id : 0xffff, 0xffff); 3746 if (rc != 0) { 3747 CH_ERR(sc, "failed to free iq %p: %d\n", iq, rc); 3748 return (rc); 3749 } 3750 iq->flags &= ~IQ_HW_ALLOCATED; 3751 3752 return (0); 3753 } 3754 3755 static void 3756 add_iq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid, 3757 struct sge_iq *iq) 3758 { 3759 struct sysctl_oid_list *children; 3760 3761 if (ctx == NULL || oid == NULL) 3762 return; 3763 3764 children = SYSCTL_CHILDREN(oid); 3765 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, &iq->ba, 3766 "bus address of descriptor ring"); 3767 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3768 iq->qsize * IQ_ESIZE, "descriptor ring size in bytes"); 3769 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "abs_id", CTLFLAG_RD, 3770 &iq->abs_id, 0, "absolute id of the queue"); 3771 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 3772 &iq->cntxt_id, 0, "SGE context id of the queue"); 3773 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &iq->cidx, 3774 0, "consumer index"); 3775 } 3776 3777 static void 3778 add_fl_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx, 3779 struct sysctl_oid *oid, struct sge_fl *fl) 3780 { 3781 struct sysctl_oid_list *children; 3782 3783 if (ctx == NULL || oid == NULL) 3784 return; 3785 3786 children = SYSCTL_CHILDREN(oid); 3787 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", 3788 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "freelist"); 3789 children = SYSCTL_CHILDREN(oid); 3790 3791 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, 3792 &fl->ba, "bus address of descriptor ring"); 3793 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3794 fl->sidx * EQ_ESIZE + sc->params.sge.spg_len, 3795 "desc ring size in bytes"); 3796 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 3797 &fl->cntxt_id, 0, "SGE context id of the freelist"); 3798 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "padding", CTLFLAG_RD, NULL, 3799 fl_pad ? 1 : 0, "padding enabled"); 3800 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "packing", CTLFLAG_RD, NULL, 3801 fl->flags & FL_BUF_PACKING ? 1 : 0, "packing enabled"); 3802 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &fl->cidx, 3803 0, "consumer index"); 3804 if (fl->flags & FL_BUF_PACKING) { 3805 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rx_offset", 3806 CTLFLAG_RD, &fl->rx_offset, 0, "packing rx offset"); 3807 } 3808 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &fl->pidx, 3809 0, "producer index"); 3810 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_allocated", 3811 CTLFLAG_RD, &fl->cl_allocated, "# of clusters allocated"); 3812 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_recycled", 3813 CTLFLAG_RD, &fl->cl_recycled, "# of clusters recycled"); 3814 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_fast_recycled", 3815 CTLFLAG_RD, &fl->cl_fast_recycled, "# of clusters recycled (fast)"); 3816 } 3817 3818 /* 3819 * Idempotent. 3820 */ 3821 static int 3822 alloc_fwq(struct adapter *sc) 3823 { 3824 int rc, intr_idx; 3825 struct sge_iq *fwq = &sc->sge.fwq; 3826 struct vi_info *vi = &sc->port[0]->vi[0]; 3827 3828 if (!(fwq->flags & IQ_SW_ALLOCATED)) { 3829 MPASS(!(fwq->flags & IQ_HW_ALLOCATED)); 3830 3831 if (sc->flags & IS_VF) 3832 intr_idx = 0; 3833 else 3834 intr_idx = sc->intr_count > 1 ? 1 : 0; 3835 init_iq(fwq, sc, 0, 0, FW_IQ_QSIZE, intr_idx, -1, IQ_OTHER); 3836 rc = alloc_iq_fl(vi, fwq, NULL, &sc->ctx, sc->fwq_oid); 3837 if (rc != 0) { 3838 CH_ERR(sc, "failed to allocate fwq: %d\n", rc); 3839 return (rc); 3840 } 3841 MPASS(fwq->flags & IQ_SW_ALLOCATED); 3842 } 3843 3844 if (!(fwq->flags & IQ_HW_ALLOCATED)) { 3845 MPASS(fwq->flags & IQ_SW_ALLOCATED); 3846 3847 rc = alloc_iq_fl_hwq(vi, fwq, NULL); 3848 if (rc != 0) { 3849 CH_ERR(sc, "failed to create hw fwq: %d\n", rc); 3850 return (rc); 3851 } 3852 MPASS(fwq->flags & IQ_HW_ALLOCATED); 3853 } 3854 3855 return (0); 3856 } 3857 3858 /* 3859 * Idempotent. 3860 */ 3861 static void 3862 free_fwq(struct adapter *sc) 3863 { 3864 struct sge_iq *fwq = &sc->sge.fwq; 3865 3866 if (fwq->flags & IQ_HW_ALLOCATED) { 3867 MPASS(fwq->flags & IQ_SW_ALLOCATED); 3868 free_iq_fl_hwq(sc, fwq, NULL); 3869 MPASS(!(fwq->flags & IQ_HW_ALLOCATED)); 3870 } 3871 3872 if (fwq->flags & IQ_SW_ALLOCATED) { 3873 MPASS(!(fwq->flags & IQ_HW_ALLOCATED)); 3874 free_iq_fl(sc, fwq, NULL); 3875 MPASS(!(fwq->flags & IQ_SW_ALLOCATED)); 3876 } 3877 } 3878 3879 /* 3880 * Idempotent. 3881 */ 3882 static int 3883 alloc_ctrlq(struct adapter *sc, int idx) 3884 { 3885 int rc; 3886 char name[16]; 3887 struct sysctl_oid *oid; 3888 struct sge_wrq *ctrlq = &sc->sge.ctrlq[idx]; 3889 3890 MPASS(idx < sc->sge.nctrlq); 3891 3892 if (!(ctrlq->eq.flags & EQ_SW_ALLOCATED)) { 3893 MPASS(!(ctrlq->eq.flags & EQ_HW_ALLOCATED)); 3894 3895 snprintf(name, sizeof(name), "%d", idx); 3896 oid = SYSCTL_ADD_NODE(&sc->ctx, SYSCTL_CHILDREN(sc->ctrlq_oid), 3897 OID_AUTO, name, CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 3898 "ctrl queue"); 3899 3900 snprintf(name, sizeof(name), "%s ctrlq%d", 3901 device_get_nameunit(sc->dev), idx); 3902 init_eq(sc, &ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE, 3903 idx % sc->params.nports, &sc->sge.fwq, name); 3904 rc = alloc_wrq(sc, NULL, ctrlq, &sc->ctx, oid); 3905 if (rc != 0) { 3906 CH_ERR(sc, "failed to allocate ctrlq%d: %d\n", idx, rc); 3907 sysctl_remove_oid(oid, 1, 1); 3908 return (rc); 3909 } 3910 MPASS(ctrlq->eq.flags & EQ_SW_ALLOCATED); 3911 } 3912 3913 if (!(ctrlq->eq.flags & EQ_HW_ALLOCATED)) { 3914 MPASS(ctrlq->eq.flags & EQ_SW_ALLOCATED); 3915 MPASS(ctrlq->nwr_pending == 0); 3916 MPASS(ctrlq->ndesc_needed == 0); 3917 3918 rc = alloc_eq_hwq(sc, NULL, &ctrlq->eq, idx); 3919 if (rc != 0) { 3920 CH_ERR(sc, "failed to create hw ctrlq%d: %d\n", idx, rc); 3921 return (rc); 3922 } 3923 MPASS(ctrlq->eq.flags & EQ_HW_ALLOCATED); 3924 } 3925 3926 return (0); 3927 } 3928 3929 /* 3930 * Idempotent. 3931 */ 3932 static void 3933 free_ctrlq(struct adapter *sc, int idx) 3934 { 3935 struct sge_wrq *ctrlq = &sc->sge.ctrlq[idx]; 3936 3937 if (ctrlq->eq.flags & EQ_HW_ALLOCATED) { 3938 MPASS(ctrlq->eq.flags & EQ_SW_ALLOCATED); 3939 free_eq_hwq(sc, NULL, &ctrlq->eq); 3940 MPASS(!(ctrlq->eq.flags & EQ_HW_ALLOCATED)); 3941 } 3942 3943 if (ctrlq->eq.flags & EQ_SW_ALLOCATED) { 3944 MPASS(!(ctrlq->eq.flags & EQ_HW_ALLOCATED)); 3945 free_wrq(sc, ctrlq); 3946 MPASS(!(ctrlq->eq.flags & EQ_SW_ALLOCATED)); 3947 } 3948 } 3949 3950 int 3951 t4_sge_set_conm_context(struct adapter *sc, int cntxt_id, int cong_drop, 3952 int cong_map) 3953 { 3954 const int cng_ch_bits_log = sc->chip_params->cng_ch_bits_log; 3955 uint32_t param, val; 3956 uint16_t ch_map; 3957 int cong_mode, rc, i; 3958 3959 if (chip_id(sc) < CHELSIO_T5) 3960 return (ENOTSUP); 3961 3962 /* Convert the driver knob to the mode understood by the firmware. */ 3963 switch (cong_drop) { 3964 case -1: 3965 cong_mode = X_CONMCTXT_CNGTPMODE_DISABLE; 3966 break; 3967 case 0: 3968 cong_mode = X_CONMCTXT_CNGTPMODE_CHANNEL; 3969 break; 3970 case 1: 3971 cong_mode = X_CONMCTXT_CNGTPMODE_QUEUE; 3972 break; 3973 case 2: 3974 cong_mode = X_CONMCTXT_CNGTPMODE_BOTH; 3975 break; 3976 default: 3977 MPASS(0); 3978 CH_ERR(sc, "cong_drop = %d is invalid (ingress queue %d).\n", 3979 cong_drop, cntxt_id); 3980 return (EINVAL); 3981 } 3982 3983 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 3984 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) | 3985 V_FW_PARAMS_PARAM_YZ(cntxt_id); 3986 if (chip_id(sc) >= CHELSIO_T7) { 3987 val = V_T7_DMAQ_CONM_CTXT_CNGTPMODE(cong_mode) | 3988 V_T7_DMAQ_CONM_CTXT_CH_VEC(cong_map); 3989 } else { 3990 val = V_CONMCTXT_CNGTPMODE(cong_mode); 3991 if (cong_mode == X_CONMCTXT_CNGTPMODE_CHANNEL || 3992 cong_mode == X_CONMCTXT_CNGTPMODE_BOTH) { 3993 for (i = 0, ch_map = 0; i < 4; i++) { 3994 if (cong_map & (1 << i)) 3995 ch_map |= 1 << (i << cng_ch_bits_log); 3996 } 3997 val |= V_CONMCTXT_CNGCHMAP(ch_map); 3998 } 3999 } 4000 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 4001 if (rc != 0) { 4002 CH_ERR(sc, "failed to set congestion manager context " 4003 "for ingress queue %d: %d\n", cntxt_id, rc); 4004 } 4005 4006 return (rc); 4007 } 4008 4009 /* 4010 * Idempotent. 4011 */ 4012 static int 4013 alloc_rxq(struct vi_info *vi, struct sge_rxq *rxq, int idx, int intr_idx, 4014 int maxp) 4015 { 4016 int rc; 4017 struct adapter *sc = vi->adapter; 4018 if_t ifp = vi->ifp; 4019 struct sysctl_oid *oid; 4020 char name[16]; 4021 4022 if (!(rxq->iq.flags & IQ_SW_ALLOCATED)) { 4023 MPASS(!(rxq->iq.flags & IQ_HW_ALLOCATED)); 4024 #if defined(INET) || defined(INET6) 4025 rc = tcp_lro_init_args(&rxq->lro, ifp, lro_entries, lro_mbufs); 4026 if (rc != 0) 4027 return (rc); 4028 MPASS(rxq->lro.ifp == ifp); /* also indicates LRO init'ed */ 4029 #endif 4030 rxq->ifp = ifp; 4031 4032 snprintf(name, sizeof(name), "%d", idx); 4033 oid = SYSCTL_ADD_NODE(&vi->ctx, SYSCTL_CHILDREN(vi->rxq_oid), 4034 OID_AUTO, name, CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 4035 "rx queue"); 4036 4037 init_iq(&rxq->iq, sc, vi->tmr_idx, vi->pktc_idx, vi->qsize_rxq, 4038 intr_idx, cong_drop, IQ_ETH); 4039 #if defined(INET) || defined(INET6) 4040 if (if_getcapenable(ifp) & IFCAP_LRO) 4041 rxq->iq.flags |= IQ_LRO_ENABLED; 4042 #endif 4043 if (if_getcapenable(ifp) & IFCAP_HWRXTSTMP) 4044 rxq->iq.flags |= IQ_RX_TIMESTAMP; 4045 snprintf(name, sizeof(name), "%s rxq%d-fl", 4046 device_get_nameunit(vi->dev), idx); 4047 init_fl(sc, &rxq->fl, vi->qsize_rxq / 8, maxp, name); 4048 rc = alloc_iq_fl(vi, &rxq->iq, &rxq->fl, &vi->ctx, oid); 4049 if (rc != 0) { 4050 CH_ERR(vi, "failed to allocate rxq%d: %d\n", idx, rc); 4051 sysctl_remove_oid(oid, 1, 1); 4052 #if defined(INET) || defined(INET6) 4053 tcp_lro_free(&rxq->lro); 4054 rxq->lro.ifp = NULL; 4055 #endif 4056 return (rc); 4057 } 4058 MPASS(rxq->iq.flags & IQ_SW_ALLOCATED); 4059 add_rxq_sysctls(&vi->ctx, oid, rxq); 4060 } 4061 4062 if (!(rxq->iq.flags & IQ_HW_ALLOCATED)) { 4063 MPASS(rxq->iq.flags & IQ_SW_ALLOCATED); 4064 rc = alloc_iq_fl_hwq(vi, &rxq->iq, &rxq->fl); 4065 if (rc != 0) { 4066 CH_ERR(vi, "failed to create hw rxq%d: %d\n", idx, rc); 4067 return (rc); 4068 } 4069 MPASS(rxq->iq.flags & IQ_HW_ALLOCATED); 4070 4071 if (idx == 0) 4072 sc->sge.iq_base = rxq->iq.abs_id - rxq->iq.cntxt_id; 4073 else 4074 KASSERT(rxq->iq.cntxt_id + sc->sge.iq_base == rxq->iq.abs_id, 4075 ("iq_base mismatch")); 4076 KASSERT(sc->sge.iq_base == 0 || sc->flags & IS_VF, 4077 ("PF with non-zero iq_base")); 4078 4079 /* 4080 * The freelist is just barely above the starvation threshold 4081 * right now, fill it up a bit more. 4082 */ 4083 FL_LOCK(&rxq->fl); 4084 refill_fl(sc, &rxq->fl, 128); 4085 FL_UNLOCK(&rxq->fl); 4086 } 4087 4088 return (0); 4089 } 4090 4091 /* 4092 * Idempotent. 4093 */ 4094 static void 4095 free_rxq(struct vi_info *vi, struct sge_rxq *rxq) 4096 { 4097 if (rxq->iq.flags & IQ_HW_ALLOCATED) { 4098 MPASS(rxq->iq.flags & IQ_SW_ALLOCATED); 4099 free_iq_fl_hwq(vi->adapter, &rxq->iq, &rxq->fl); 4100 MPASS(!(rxq->iq.flags & IQ_HW_ALLOCATED)); 4101 } 4102 4103 if (rxq->iq.flags & IQ_SW_ALLOCATED) { 4104 MPASS(!(rxq->iq.flags & IQ_HW_ALLOCATED)); 4105 #if defined(INET) || defined(INET6) 4106 tcp_lro_free(&rxq->lro); 4107 #endif 4108 free_iq_fl(vi->adapter, &rxq->iq, &rxq->fl); 4109 MPASS(!(rxq->iq.flags & IQ_SW_ALLOCATED)); 4110 bzero(rxq, sizeof(*rxq)); 4111 } 4112 } 4113 4114 static void 4115 add_rxq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid, 4116 struct sge_rxq *rxq) 4117 { 4118 struct sysctl_oid_list *children; 4119 4120 if (ctx == NULL || oid == NULL) 4121 return; 4122 4123 children = SYSCTL_CHILDREN(oid); 4124 #if defined(INET) || defined(INET6) 4125 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "lro_queued", CTLFLAG_RD, 4126 &rxq->lro.lro_queued, 0, NULL); 4127 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "lro_flushed", CTLFLAG_RD, 4128 &rxq->lro.lro_flushed, 0, NULL); 4129 #endif 4130 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "rxcsum", CTLFLAG_RD, 4131 &rxq->rxcsum, "# of times hardware assisted with checksum"); 4132 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "vlan_extraction", CTLFLAG_RD, 4133 &rxq->vlan_extraction, "# of times hardware extracted 802.1Q tag"); 4134 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "vxlan_rxcsum", CTLFLAG_RD, 4135 &rxq->vxlan_rxcsum, 4136 "# of times hardware assisted with inner checksum (VXLAN)"); 4137 } 4138 4139 #ifdef TCP_OFFLOAD 4140 /* 4141 * Idempotent. 4142 */ 4143 static int 4144 alloc_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq, int idx, 4145 int intr_idx, int maxp) 4146 { 4147 int rc; 4148 struct adapter *sc = vi->adapter; 4149 struct sysctl_oid *oid; 4150 char name[16]; 4151 4152 if (!(ofld_rxq->iq.flags & IQ_SW_ALLOCATED)) { 4153 MPASS(!(ofld_rxq->iq.flags & IQ_HW_ALLOCATED)); 4154 4155 snprintf(name, sizeof(name), "%d", idx); 4156 oid = SYSCTL_ADD_NODE(&vi->ctx, 4157 SYSCTL_CHILDREN(vi->ofld_rxq_oid), OID_AUTO, name, 4158 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "offload rx queue"); 4159 4160 init_iq(&ofld_rxq->iq, sc, vi->ofld_tmr_idx, vi->ofld_pktc_idx, 4161 vi->qsize_rxq, intr_idx, ofld_cong_drop, IQ_OFLD); 4162 snprintf(name, sizeof(name), "%s ofld_rxq%d-fl", 4163 device_get_nameunit(vi->dev), idx); 4164 init_fl(sc, &ofld_rxq->fl, vi->qsize_rxq / 8, maxp, name); 4165 rc = alloc_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl, &vi->ctx, 4166 oid); 4167 if (rc != 0) { 4168 CH_ERR(vi, "failed to allocate ofld_rxq%d: %d\n", idx, 4169 rc); 4170 sysctl_remove_oid(oid, 1, 1); 4171 return (rc); 4172 } 4173 MPASS(ofld_rxq->iq.flags & IQ_SW_ALLOCATED); 4174 ofld_rxq->rx_iscsi_ddp_setup_ok = counter_u64_alloc(M_WAITOK); 4175 ofld_rxq->rx_iscsi_ddp_setup_error = 4176 counter_u64_alloc(M_WAITOK); 4177 ofld_rxq->rx_nvme_ddp_setup_ok = counter_u64_alloc(M_WAITOK); 4178 ofld_rxq->rx_nvme_ddp_setup_no_stag = 4179 counter_u64_alloc(M_WAITOK); 4180 ofld_rxq->rx_nvme_ddp_setup_error = 4181 counter_u64_alloc(M_WAITOK); 4182 ofld_rxq->rx_nvme_ddp_octets = counter_u64_alloc(M_WAITOK); 4183 ofld_rxq->rx_nvme_ddp_pdus = counter_u64_alloc(M_WAITOK); 4184 ofld_rxq->rx_nvme_fl_octets = counter_u64_alloc(M_WAITOK); 4185 ofld_rxq->rx_nvme_fl_pdus = counter_u64_alloc(M_WAITOK); 4186 ofld_rxq->rx_nvme_invalid_headers = counter_u64_alloc(M_WAITOK); 4187 ofld_rxq->rx_nvme_header_digest_errors = 4188 counter_u64_alloc(M_WAITOK); 4189 ofld_rxq->rx_nvme_data_digest_errors = 4190 counter_u64_alloc(M_WAITOK); 4191 ofld_rxq->ddp_buffer_alloc = counter_u64_alloc(M_WAITOK); 4192 ofld_rxq->ddp_buffer_reuse = counter_u64_alloc(M_WAITOK); 4193 ofld_rxq->ddp_buffer_free = counter_u64_alloc(M_WAITOK); 4194 add_ofld_rxq_sysctls(&vi->ctx, oid, ofld_rxq); 4195 } 4196 4197 if (!(ofld_rxq->iq.flags & IQ_HW_ALLOCATED)) { 4198 MPASS(ofld_rxq->iq.flags & IQ_SW_ALLOCATED); 4199 rc = alloc_iq_fl_hwq(vi, &ofld_rxq->iq, &ofld_rxq->fl); 4200 if (rc != 0) { 4201 CH_ERR(vi, "failed to create hw ofld_rxq%d: %d\n", idx, 4202 rc); 4203 return (rc); 4204 } 4205 MPASS(ofld_rxq->iq.flags & IQ_HW_ALLOCATED); 4206 } 4207 return (rc); 4208 } 4209 4210 /* 4211 * Idempotent. 4212 */ 4213 static void 4214 free_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq) 4215 { 4216 if (ofld_rxq->iq.flags & IQ_HW_ALLOCATED) { 4217 MPASS(ofld_rxq->iq.flags & IQ_SW_ALLOCATED); 4218 free_iq_fl_hwq(vi->adapter, &ofld_rxq->iq, &ofld_rxq->fl); 4219 MPASS(!(ofld_rxq->iq.flags & IQ_HW_ALLOCATED)); 4220 } 4221 4222 if (ofld_rxq->iq.flags & IQ_SW_ALLOCATED) { 4223 MPASS(!(ofld_rxq->iq.flags & IQ_HW_ALLOCATED)); 4224 free_iq_fl(vi->adapter, &ofld_rxq->iq, &ofld_rxq->fl); 4225 MPASS(!(ofld_rxq->iq.flags & IQ_SW_ALLOCATED)); 4226 counter_u64_free(ofld_rxq->rx_iscsi_ddp_setup_ok); 4227 counter_u64_free(ofld_rxq->rx_iscsi_ddp_setup_error); 4228 counter_u64_free(ofld_rxq->rx_nvme_ddp_setup_ok); 4229 counter_u64_free(ofld_rxq->rx_nvme_ddp_setup_no_stag); 4230 counter_u64_free(ofld_rxq->rx_nvme_ddp_setup_error); 4231 counter_u64_free(ofld_rxq->rx_nvme_ddp_octets); 4232 counter_u64_free(ofld_rxq->rx_nvme_ddp_pdus); 4233 counter_u64_free(ofld_rxq->rx_nvme_fl_octets); 4234 counter_u64_free(ofld_rxq->rx_nvme_fl_pdus); 4235 counter_u64_free(ofld_rxq->rx_nvme_invalid_headers); 4236 counter_u64_free(ofld_rxq->rx_nvme_header_digest_errors); 4237 counter_u64_free(ofld_rxq->rx_nvme_data_digest_errors); 4238 counter_u64_free(ofld_rxq->ddp_buffer_alloc); 4239 counter_u64_free(ofld_rxq->ddp_buffer_reuse); 4240 counter_u64_free(ofld_rxq->ddp_buffer_free); 4241 bzero(ofld_rxq, sizeof(*ofld_rxq)); 4242 } 4243 } 4244 4245 static void 4246 add_ofld_rxq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid, 4247 struct sge_ofld_rxq *ofld_rxq) 4248 { 4249 struct sysctl_oid_list *children, *top; 4250 4251 if (ctx == NULL || oid == NULL) 4252 return; 4253 4254 top = children = SYSCTL_CHILDREN(oid); 4255 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "rx_aio_ddp_jobs", 4256 CTLFLAG_RD, &ofld_rxq->rx_aio_ddp_jobs, 0, 4257 "# of aio_read(2) jobs completed via DDP"); 4258 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "rx_aio_ddp_octets", 4259 CTLFLAG_RD, &ofld_rxq->rx_aio_ddp_octets, 0, 4260 "# of octets placed directly for aio_read(2) jobs"); 4261 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 4262 "rx_toe_tls_records", CTLFLAG_RD, &ofld_rxq->rx_toe_tls_records, 4263 "# of TOE TLS records received"); 4264 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 4265 "rx_toe_tls_octets", CTLFLAG_RD, &ofld_rxq->rx_toe_tls_octets, 4266 "# of payload octets in received TOE TLS records"); 4267 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 4268 "rx_toe_ddp_octets", CTLFLAG_RD, &ofld_rxq->rx_toe_ddp_octets, 4269 "# of payload octets received via TCP DDP"); 4270 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, 4271 "ddp_buffer_alloc", CTLFLAG_RD, &ofld_rxq->ddp_buffer_alloc, 4272 "# of DDP RCV buffers allocated"); 4273 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, 4274 "ddp_buffer_reuse", CTLFLAG_RD, &ofld_rxq->ddp_buffer_reuse, 4275 "# of DDP RCV buffers reused"); 4276 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, 4277 "ddp_buffer_free", CTLFLAG_RD, &ofld_rxq->ddp_buffer_free, 4278 "# of DDP RCV buffers freed"); 4279 4280 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "iscsi", 4281 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TOE iSCSI statistics"); 4282 children = SYSCTL_CHILDREN(oid); 4283 4284 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "ddp_setup_ok", 4285 CTLFLAG_RD, &ofld_rxq->rx_iscsi_ddp_setup_ok, 4286 "# of times DDP buffer was setup successfully."); 4287 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "ddp_setup_error", 4288 CTLFLAG_RD, &ofld_rxq->rx_iscsi_ddp_setup_error, 4289 "# of times DDP buffer setup failed."); 4290 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "ddp_octets", 4291 CTLFLAG_RD, &ofld_rxq->rx_iscsi_ddp_octets, 0, 4292 "# of octets placed directly"); 4293 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "ddp_pdus", 4294 CTLFLAG_RD, &ofld_rxq->rx_iscsi_ddp_pdus, 0, 4295 "# of PDUs with data placed directly."); 4296 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "fl_octets", 4297 CTLFLAG_RD, &ofld_rxq->rx_iscsi_fl_octets, 0, 4298 "# of data octets delivered in freelist"); 4299 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "fl_pdus", 4300 CTLFLAG_RD, &ofld_rxq->rx_iscsi_fl_pdus, 0, 4301 "# of PDUs with data delivered in freelist"); 4302 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "padding_errors", 4303 CTLFLAG_RD, &ofld_rxq->rx_iscsi_padding_errors, 0, 4304 "# of PDUs with invalid padding"); 4305 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "header_digest_errors", 4306 CTLFLAG_RD, &ofld_rxq->rx_iscsi_header_digest_errors, 0, 4307 "# of PDUs with invalid header digests"); 4308 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "data_digest_errors", 4309 CTLFLAG_RD, &ofld_rxq->rx_iscsi_data_digest_errors, 0, 4310 "# of PDUs with invalid data digests"); 4311 4312 oid = SYSCTL_ADD_NODE(ctx, top, OID_AUTO, "nvme", 4313 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TOE NVMe statistics"); 4314 children = SYSCTL_CHILDREN(oid); 4315 4316 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "ddp_setup_ok", 4317 CTLFLAG_RD, &ofld_rxq->rx_nvme_ddp_setup_ok, 4318 "# of times DDP buffer was setup successfully"); 4319 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "ddp_setup_no_stag", 4320 CTLFLAG_RD, &ofld_rxq->rx_nvme_ddp_setup_no_stag, 4321 "# of times STAG was not available for DDP buffer setup"); 4322 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "ddp_setup_error", 4323 CTLFLAG_RD, &ofld_rxq->rx_nvme_ddp_setup_error, 4324 "# of times DDP buffer setup failed"); 4325 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "ddp_octets", 4326 CTLFLAG_RD, &ofld_rxq->rx_nvme_ddp_octets, 4327 "# of octets placed directly"); 4328 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "ddp_pdus", 4329 CTLFLAG_RD, &ofld_rxq->rx_nvme_ddp_pdus, 4330 "# of PDUs with data placed directly"); 4331 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "fl_octets", 4332 CTLFLAG_RD, &ofld_rxq->rx_nvme_fl_octets, 4333 "# of data octets delivered in freelist"); 4334 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "fl_pdus", 4335 CTLFLAG_RD, &ofld_rxq->rx_nvme_fl_pdus, 4336 "# of PDUs with data delivered in freelist"); 4337 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "invalid_headers", 4338 CTLFLAG_RD, &ofld_rxq->rx_nvme_invalid_headers, 4339 "# of PDUs with invalid header field"); 4340 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "header_digest_errors", 4341 CTLFLAG_RD, &ofld_rxq->rx_nvme_header_digest_errors, 4342 "# of PDUs with invalid header digests"); 4343 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "data_digest_errors", 4344 CTLFLAG_RD, &ofld_rxq->rx_nvme_data_digest_errors, 4345 "# of PDUs with invalid data digests"); 4346 } 4347 #endif 4348 4349 /* 4350 * Returns a reasonable automatic cidx flush threshold for a given queue size. 4351 */ 4352 static u_int 4353 qsize_to_fthresh(int qsize) 4354 { 4355 u_int fthresh; 4356 4357 fthresh = qsize == 0 ? 0 : order_base_2(qsize); 4358 if (fthresh > X_CIDXFLUSHTHRESH_128) 4359 fthresh = X_CIDXFLUSHTHRESH_128; 4360 4361 return (fthresh); 4362 } 4363 4364 static int 4365 ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq, int idx) 4366 { 4367 int rc, cntxt_id, core; 4368 struct fw_eq_ctrl_cmd c; 4369 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 4370 4371 core = sc->params.tid_qid_sel_mask != 0 ? idx % sc->params.ncores : 0; 4372 bzero(&c, sizeof(c)); 4373 4374 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | F_FW_CMD_REQUEST | 4375 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_CTRL_CMD_PFN(sc->pf) | 4376 V_FW_EQ_CTRL_CMD_VFN(0)); 4377 c.alloc_to_len16 = htobe32(F_FW_EQ_CTRL_CMD_ALLOC | 4378 V_FW_EQ_CTRL_CMD_COREGROUP(core) | 4379 F_FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c)); 4380 c.cmpliqid_eqid = htonl(V_FW_EQ_CTRL_CMD_CMPLIQID(eq->iqid)); 4381 c.physeqid_pkd = htobe32(0); 4382 c.fetchszm_to_iqid = 4383 htobe32(V_FW_EQ_CTRL_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 4384 V_FW_EQ_CTRL_CMD_PCIECHN(eq->hw_port) | 4385 F_FW_EQ_CTRL_CMD_FETCHRO | V_FW_EQ_CTRL_CMD_IQID(eq->iqid)); 4386 c.dcaen_to_eqsize = 4387 htobe32(V_FW_EQ_CTRL_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ? 4388 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) | 4389 V_FW_EQ_CTRL_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 4390 V_FW_EQ_CTRL_CMD_CIDXFTHRESH(qsize_to_fthresh(qsize)) | 4391 V_FW_EQ_CTRL_CMD_EQSIZE(qsize)); 4392 c.eqaddr = htobe64(eq->ba); 4393 4394 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 4395 if (rc != 0) { 4396 CH_ERR(sc, "failed to create hw ctrlq for port %d: %d\n", 4397 eq->port_id, rc); 4398 return (rc); 4399 } 4400 4401 eq->cntxt_id = G_FW_EQ_CTRL_CMD_EQID(be32toh(c.cmpliqid_eqid)); 4402 eq->abs_id = G_FW_EQ_CTRL_CMD_PHYSEQID(be32toh(c.physeqid_pkd)); 4403 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 4404 if (cntxt_id >= sc->sge.eqmap_sz) 4405 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 4406 cntxt_id, sc->sge.eqmap_sz - 1); 4407 sc->sge.eqmap[cntxt_id] = eq; 4408 4409 return (rc); 4410 } 4411 4412 static int 4413 eth_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq, int idx) 4414 { 4415 int rc, cntxt_id, core; 4416 struct fw_eq_eth_cmd c; 4417 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 4418 4419 core = sc->params.ncores > 1 ? idx % sc->params.ncores : 0; 4420 bzero(&c, sizeof(c)); 4421 4422 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST | 4423 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) | 4424 V_FW_EQ_ETH_CMD_VFN(0)); 4425 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC | 4426 V_FW_EQ_ETH_CMD_COREGROUP(core) | 4427 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c)); 4428 c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE | 4429 F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(vi->viid)); 4430 c.fetchszm_to_iqid = 4431 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) | 4432 V_FW_EQ_ETH_CMD_PCIECHN(eq->hw_port) | F_FW_EQ_ETH_CMD_FETCHRO | 4433 V_FW_EQ_ETH_CMD_IQID(eq->iqid)); 4434 c.dcaen_to_eqsize = 4435 htobe32(V_FW_EQ_ETH_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ? 4436 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) | 4437 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 4438 V_FW_EQ_ETH_CMD_EQSIZE(qsize)); 4439 c.eqaddr = htobe64(eq->ba); 4440 4441 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 4442 if (rc != 0) { 4443 device_printf(vi->dev, 4444 "failed to create Ethernet egress queue: %d\n", rc); 4445 return (rc); 4446 } 4447 4448 eq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd)); 4449 eq->abs_id = G_FW_EQ_ETH_CMD_PHYSEQID(be32toh(c.physeqid_pkd)); 4450 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 4451 if (cntxt_id >= sc->sge.eqmap_sz) 4452 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 4453 cntxt_id, sc->sge.eqmap_sz - 1); 4454 sc->sge.eqmap[cntxt_id] = eq; 4455 4456 return (rc); 4457 } 4458 4459 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 4460 /* 4461 * ncores number of uP cores. 4462 * nq number of queues for this VI 4463 * idx queue index 4464 */ 4465 static inline int 4466 qidx_to_core(int ncores, int nq, int idx) 4467 { 4468 MPASS(nq % ncores == 0); 4469 MPASS(idx >= 0 && idx < nq); 4470 4471 return (idx * ncores / nq); 4472 } 4473 4474 static int 4475 ofld_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq, 4476 int idx) 4477 { 4478 int rc, cntxt_id, core; 4479 struct fw_eq_ofld_cmd c; 4480 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 4481 4482 if (sc->params.tid_qid_sel_mask != 0) 4483 core = qidx_to_core(sc->params.ncores, vi->nofldtxq, idx); 4484 else 4485 core = 0; 4486 4487 bzero(&c, sizeof(c)); 4488 4489 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | F_FW_CMD_REQUEST | 4490 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_OFLD_CMD_PFN(sc->pf) | 4491 V_FW_EQ_OFLD_CMD_VFN(0)); 4492 c.alloc_to_len16 = htonl(F_FW_EQ_OFLD_CMD_ALLOC | 4493 V_FW_EQ_OFLD_CMD_COREGROUP(core) | 4494 F_FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c)); 4495 c.fetchszm_to_iqid = 4496 htonl(V_FW_EQ_OFLD_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 4497 V_FW_EQ_OFLD_CMD_PCIECHN(eq->hw_port) | 4498 F_FW_EQ_OFLD_CMD_FETCHRO | V_FW_EQ_OFLD_CMD_IQID(eq->iqid)); 4499 c.dcaen_to_eqsize = 4500 htobe32(V_FW_EQ_OFLD_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ? 4501 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) | 4502 V_FW_EQ_OFLD_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 4503 V_FW_EQ_OFLD_CMD_CIDXFTHRESH(qsize_to_fthresh(qsize)) | 4504 V_FW_EQ_OFLD_CMD_EQSIZE(qsize)); 4505 c.eqaddr = htobe64(eq->ba); 4506 4507 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 4508 if (rc != 0) { 4509 device_printf(vi->dev, 4510 "failed to create egress queue for TCP offload: %d\n", rc); 4511 return (rc); 4512 } 4513 4514 eq->cntxt_id = G_FW_EQ_OFLD_CMD_EQID(be32toh(c.eqid_pkd)); 4515 eq->abs_id = G_FW_EQ_OFLD_CMD_PHYSEQID(be32toh(c.physeqid_pkd)); 4516 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 4517 if (cntxt_id >= sc->sge.eqmap_sz) 4518 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 4519 cntxt_id, sc->sge.eqmap_sz - 1); 4520 sc->sge.eqmap[cntxt_id] = eq; 4521 4522 return (rc); 4523 } 4524 #endif 4525 4526 /* SW only */ 4527 static int 4528 alloc_eq(struct adapter *sc, struct sge_eq *eq, struct sysctl_ctx_list *ctx, 4529 struct sysctl_oid *oid) 4530 { 4531 int rc, qsize; 4532 size_t len; 4533 4534 MPASS(!(eq->flags & EQ_SW_ALLOCATED)); 4535 4536 qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 4537 len = qsize * EQ_ESIZE; 4538 rc = alloc_ring(sc, len, &eq->desc_tag, &eq->desc_map, &eq->ba, 4539 (void **)&eq->desc); 4540 if (rc) 4541 return (rc); 4542 if (ctx != NULL && oid != NULL) 4543 add_eq_sysctls(sc, ctx, oid, eq); 4544 eq->flags |= EQ_SW_ALLOCATED; 4545 4546 return (0); 4547 } 4548 4549 /* SW only */ 4550 static void 4551 free_eq(struct adapter *sc, struct sge_eq *eq) 4552 { 4553 MPASS(eq->flags & EQ_SW_ALLOCATED); 4554 if (eq->type == EQ_ETH) 4555 MPASS(eq->pidx == eq->cidx); 4556 4557 free_ring(sc, eq->desc_tag, eq->desc_map, eq->ba, eq->desc); 4558 mtx_destroy(&eq->eq_lock); 4559 bzero(eq, sizeof(*eq)); 4560 } 4561 4562 static void 4563 add_eq_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx, 4564 struct sysctl_oid *oid, struct sge_eq *eq) 4565 { 4566 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 4567 4568 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, &eq->ba, 4569 "bus address of descriptor ring"); 4570 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 4571 eq->sidx * EQ_ESIZE + sc->params.sge.spg_len, 4572 "desc ring size in bytes"); 4573 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "abs_id", CTLFLAG_RD, 4574 &eq->abs_id, 0, "absolute id of the queue"); 4575 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 4576 &eq->cntxt_id, 0, "SGE context id of the queue"); 4577 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &eq->cidx, 4578 0, "consumer index"); 4579 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &eq->pidx, 4580 0, "producer index"); 4581 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL, 4582 eq->sidx, "status page index"); 4583 } 4584 4585 static int 4586 alloc_eq_hwq(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq, int idx) 4587 { 4588 int rc; 4589 4590 MPASS(!(eq->flags & EQ_HW_ALLOCATED)); 4591 4592 eq->iqid = eq->iq->cntxt_id; 4593 eq->pidx = eq->cidx = eq->dbidx = 0; 4594 /* Note that equeqidx is not used with sge_wrq (OFLD/CTRL) queues. */ 4595 eq->equeqidx = 0; 4596 eq->doorbells = sc->doorbells; 4597 bzero(eq->desc, eq->sidx * EQ_ESIZE + sc->params.sge.spg_len); 4598 4599 switch (eq->type) { 4600 case EQ_CTRL: 4601 rc = ctrl_eq_alloc(sc, eq, idx); 4602 break; 4603 4604 case EQ_ETH: 4605 rc = eth_eq_alloc(sc, vi, eq, idx); 4606 break; 4607 4608 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 4609 case EQ_OFLD: 4610 rc = ofld_eq_alloc(sc, vi, eq, idx); 4611 break; 4612 #endif 4613 4614 default: 4615 panic("%s: invalid eq type %d.", __func__, eq->type); 4616 } 4617 if (rc != 0) { 4618 CH_ERR(sc, "failed to allocate egress queue(%d): %d\n", 4619 eq->type, rc); 4620 return (rc); 4621 } 4622 4623 if (isset(&eq->doorbells, DOORBELL_UDB) || 4624 isset(&eq->doorbells, DOORBELL_UDBWC) || 4625 isset(&eq->doorbells, DOORBELL_WCWR)) { 4626 uint32_t s_qpp = sc->params.sge.eq_s_qpp; 4627 uint32_t mask = (1 << s_qpp) - 1; 4628 volatile uint8_t *udb; 4629 4630 udb = sc->udbs_base + UDBS_DB_OFFSET; 4631 udb += (eq->cntxt_id >> s_qpp) << PAGE_SHIFT; /* pg offset */ 4632 eq->udb_qid = eq->cntxt_id & mask; /* id in page */ 4633 if (eq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE) 4634 clrbit(&eq->doorbells, DOORBELL_WCWR); 4635 else { 4636 udb += eq->udb_qid << UDBS_SEG_SHIFT; /* seg offset */ 4637 eq->udb_qid = 0; 4638 } 4639 eq->udb = (volatile void *)udb; 4640 } 4641 4642 eq->flags |= EQ_HW_ALLOCATED; 4643 return (0); 4644 } 4645 4646 static int 4647 free_eq_hwq(struct adapter *sc, struct vi_info *vi __unused, struct sge_eq *eq) 4648 { 4649 int rc; 4650 4651 MPASS(eq->flags & EQ_HW_ALLOCATED); 4652 4653 switch (eq->type) { 4654 case EQ_CTRL: 4655 rc = -t4_ctrl_eq_free(sc, sc->mbox, sc->pf, 0, eq->cntxt_id); 4656 break; 4657 case EQ_ETH: 4658 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0, eq->cntxt_id); 4659 break; 4660 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 4661 case EQ_OFLD: 4662 rc = -t4_ofld_eq_free(sc, sc->mbox, sc->pf, 0, eq->cntxt_id); 4663 break; 4664 #endif 4665 default: 4666 panic("%s: invalid eq type %d.", __func__, eq->type); 4667 } 4668 if (rc != 0) { 4669 CH_ERR(sc, "failed to free eq (type %d): %d\n", eq->type, rc); 4670 return (rc); 4671 } 4672 eq->flags &= ~EQ_HW_ALLOCATED; 4673 4674 return (0); 4675 } 4676 4677 static int 4678 alloc_wrq(struct adapter *sc, struct vi_info *vi, struct sge_wrq *wrq, 4679 struct sysctl_ctx_list *ctx, struct sysctl_oid *oid) 4680 { 4681 struct sge_eq *eq = &wrq->eq; 4682 int rc; 4683 4684 MPASS(!(eq->flags & EQ_SW_ALLOCATED)); 4685 4686 rc = alloc_eq(sc, eq, ctx, oid); 4687 if (rc) 4688 return (rc); 4689 MPASS(eq->flags & EQ_SW_ALLOCATED); 4690 /* Can't fail after this. */ 4691 4692 wrq->adapter = sc; 4693 TASK_INIT(&wrq->wrq_tx_task, 0, wrq_tx_drain, wrq); 4694 TAILQ_INIT(&wrq->incomplete_wrs); 4695 STAILQ_INIT(&wrq->wr_list); 4696 wrq->nwr_pending = 0; 4697 wrq->ndesc_needed = 0; 4698 add_wrq_sysctls(ctx, oid, wrq); 4699 4700 return (0); 4701 } 4702 4703 static void 4704 free_wrq(struct adapter *sc, struct sge_wrq *wrq) 4705 { 4706 free_eq(sc, &wrq->eq); 4707 MPASS(wrq->nwr_pending == 0); 4708 MPASS(wrq->ndesc_needed == 0); 4709 MPASS(TAILQ_EMPTY(&wrq->incomplete_wrs)); 4710 MPASS(STAILQ_EMPTY(&wrq->wr_list)); 4711 bzero(wrq, sizeof(*wrq)); 4712 } 4713 4714 static void 4715 add_wrq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid, 4716 struct sge_wrq *wrq) 4717 { 4718 struct sysctl_oid_list *children; 4719 4720 if (ctx == NULL || oid == NULL) 4721 return; 4722 4723 children = SYSCTL_CHILDREN(oid); 4724 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_direct", CTLFLAG_RD, 4725 &wrq->tx_wrs_direct, "# of work requests (direct)"); 4726 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_copied", CTLFLAG_RD, 4727 &wrq->tx_wrs_copied, "# of work requests (copied)"); 4728 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_sspace", CTLFLAG_RD, 4729 &wrq->tx_wrs_ss, "# of work requests (copied from scratch space)"); 4730 } 4731 4732 /* 4733 * Idempotent. 4734 */ 4735 static int 4736 alloc_txq(struct vi_info *vi, struct sge_txq *txq, int idx) 4737 { 4738 int rc, iqidx; 4739 struct port_info *pi = vi->pi; 4740 struct adapter *sc = vi->adapter; 4741 struct sge_eq *eq = &txq->eq; 4742 struct txpkts *txp; 4743 char name[16]; 4744 struct sysctl_oid *oid; 4745 4746 if (!(eq->flags & EQ_SW_ALLOCATED)) { 4747 MPASS(!(eq->flags & EQ_HW_ALLOCATED)); 4748 4749 snprintf(name, sizeof(name), "%d", idx); 4750 oid = SYSCTL_ADD_NODE(&vi->ctx, SYSCTL_CHILDREN(vi->txq_oid), 4751 OID_AUTO, name, CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 4752 "tx queue"); 4753 4754 iqidx = vi->first_rxq + (idx % vi->nrxq); 4755 snprintf(name, sizeof(name), "%s txq%d", 4756 device_get_nameunit(vi->dev), idx); 4757 init_eq(sc, &txq->eq, EQ_ETH, vi->qsize_txq, pi->port_id, 4758 &sc->sge.rxq[iqidx].iq, name); 4759 4760 rc = mp_ring_alloc(&txq->r, eq->sidx, txq, eth_tx, 4761 can_resume_eth_tx, M_CXGBE, &eq->eq_lock, M_WAITOK); 4762 if (rc != 0) { 4763 CH_ERR(vi, "failed to allocate mp_ring for txq%d: %d\n", 4764 idx, rc); 4765 failed: 4766 sysctl_remove_oid(oid, 1, 1); 4767 return (rc); 4768 } 4769 4770 rc = alloc_eq(sc, eq, &vi->ctx, oid); 4771 if (rc) { 4772 CH_ERR(vi, "failed to allocate txq%d: %d\n", idx, rc); 4773 mp_ring_free(txq->r); 4774 goto failed; 4775 } 4776 MPASS(eq->flags & EQ_SW_ALLOCATED); 4777 /* Can't fail after this point. */ 4778 4779 TASK_INIT(&txq->tx_reclaim_task, 0, tx_reclaim, eq); 4780 txq->ifp = vi->ifp; 4781 txq->gl = sglist_alloc(TX_SGL_SEGS, M_WAITOK); 4782 txq->sdesc = malloc(eq->sidx * sizeof(struct tx_sdesc), M_CXGBE, 4783 M_ZERO | M_WAITOK); 4784 4785 add_txq_sysctls(vi, &vi->ctx, oid, txq); 4786 } 4787 4788 if (!(eq->flags & EQ_HW_ALLOCATED)) { 4789 MPASS(eq->flags & EQ_SW_ALLOCATED); 4790 rc = alloc_eq_hwq(sc, vi, eq, idx); 4791 if (rc != 0) { 4792 CH_ERR(vi, "failed to create hw txq%d: %d\n", idx, rc); 4793 return (rc); 4794 } 4795 MPASS(eq->flags & EQ_HW_ALLOCATED); 4796 /* Can't fail after this point. */ 4797 4798 if (idx == 0) 4799 sc->sge.eq_base = eq->abs_id - eq->cntxt_id; 4800 else 4801 KASSERT(eq->cntxt_id + sc->sge.eq_base == eq->abs_id, 4802 ("eq_base mismatch")); 4803 KASSERT(sc->sge.eq_base == 0 || sc->flags & IS_VF, 4804 ("PF with non-zero eq_base")); 4805 4806 txp = &txq->txp; 4807 MPASS(nitems(txp->mb) >= sc->params.max_pkts_per_eth_tx_pkts_wr); 4808 txq->txp.max_npkt = min(nitems(txp->mb), 4809 sc->params.max_pkts_per_eth_tx_pkts_wr); 4810 if (vi->flags & TX_USES_VM_WR && !(sc->flags & IS_VF)) 4811 txq->txp.max_npkt--; 4812 4813 if (vi->flags & TX_USES_VM_WR) 4814 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) | 4815 V_TXPKT_INTF(pi->hw_port)); 4816 else 4817 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) | 4818 V_TXPKT_INTF(pi->hw_port) | V_TXPKT_PF(sc->pf) | 4819 V_TXPKT_VF(vi->vin) | V_TXPKT_VF_VLD(vi->vfvld)); 4820 4821 txq->tc_idx = -1; 4822 } 4823 4824 return (0); 4825 } 4826 4827 /* 4828 * Idempotent. 4829 */ 4830 static void 4831 free_txq(struct vi_info *vi, struct sge_txq *txq) 4832 { 4833 struct adapter *sc = vi->adapter; 4834 struct sge_eq *eq = &txq->eq; 4835 4836 if (eq->flags & EQ_HW_ALLOCATED) { 4837 MPASS(eq->flags & EQ_SW_ALLOCATED); 4838 free_eq_hwq(sc, NULL, eq); 4839 MPASS(!(eq->flags & EQ_HW_ALLOCATED)); 4840 } 4841 4842 if (eq->flags & EQ_SW_ALLOCATED) { 4843 MPASS(!(eq->flags & EQ_HW_ALLOCATED)); 4844 sglist_free(txq->gl); 4845 free(txq->sdesc, M_CXGBE); 4846 mp_ring_free(txq->r); 4847 free_eq(sc, eq); 4848 MPASS(!(eq->flags & EQ_SW_ALLOCATED)); 4849 bzero(txq, sizeof(*txq)); 4850 } 4851 } 4852 4853 static void 4854 add_txq_sysctls(struct vi_info *vi, struct sysctl_ctx_list *ctx, 4855 struct sysctl_oid *oid, struct sge_txq *txq) 4856 { 4857 struct adapter *sc; 4858 struct sysctl_oid_list *children; 4859 4860 if (ctx == NULL || oid == NULL) 4861 return; 4862 4863 sc = vi->adapter; 4864 children = SYSCTL_CHILDREN(oid); 4865 4866 mp_ring_sysctls(txq->r, ctx, children); 4867 4868 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tc", 4869 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, txq - sc->sge.txq, 4870 sysctl_tc, "I", "traffic class (-1 means none)"); 4871 4872 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txcsum", CTLFLAG_RD, 4873 &txq->txcsum, "# of times hardware assisted with checksum"); 4874 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "vlan_insertion", CTLFLAG_RD, 4875 &txq->vlan_insertion, "# of times hardware inserted 802.1Q tag"); 4876 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tso_wrs", CTLFLAG_RD, 4877 &txq->tso_wrs, "# of TSO work requests"); 4878 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "imm_wrs", CTLFLAG_RD, 4879 &txq->imm_wrs, "# of work requests with immediate data"); 4880 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "sgl_wrs", CTLFLAG_RD, 4881 &txq->sgl_wrs, "# of work requests with direct SGL"); 4882 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkt_wrs", CTLFLAG_RD, 4883 &txq->txpkt_wrs, "# of txpkt work requests (one pkt/WR)"); 4884 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkts0_wrs", CTLFLAG_RD, 4885 &txq->txpkts0_wrs, "# of txpkts (type 0) work requests"); 4886 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkts1_wrs", CTLFLAG_RD, 4887 &txq->txpkts1_wrs, "# of txpkts (type 1) work requests"); 4888 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkts0_pkts", CTLFLAG_RD, 4889 &txq->txpkts0_pkts, 4890 "# of frames tx'd using type0 txpkts work requests"); 4891 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkts1_pkts", CTLFLAG_RD, 4892 &txq->txpkts1_pkts, 4893 "# of frames tx'd using type1 txpkts work requests"); 4894 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkts_flush", CTLFLAG_RD, 4895 &txq->txpkts_flush, 4896 "# of times txpkts had to be flushed out by an egress-update"); 4897 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "raw_wrs", CTLFLAG_RD, 4898 &txq->raw_wrs, "# of raw work requests (non-packets)"); 4899 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "vxlan_tso_wrs", CTLFLAG_RD, 4900 &txq->vxlan_tso_wrs, "# of VXLAN TSO work requests"); 4901 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "vxlan_txcsum", CTLFLAG_RD, 4902 &txq->vxlan_txcsum, 4903 "# of times hardware assisted with inner checksums (VXLAN)"); 4904 4905 #ifdef KERN_TLS 4906 if (is_ktls(sc)) { 4907 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_records", 4908 CTLFLAG_RD, &txq->kern_tls_records, 4909 "# of NIC TLS records transmitted"); 4910 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_short", 4911 CTLFLAG_RD, &txq->kern_tls_short, 4912 "# of short NIC TLS records transmitted"); 4913 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_partial", 4914 CTLFLAG_RD, &txq->kern_tls_partial, 4915 "# of partial NIC TLS records transmitted"); 4916 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_full", 4917 CTLFLAG_RD, &txq->kern_tls_full, 4918 "# of full NIC TLS records transmitted"); 4919 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_octets", 4920 CTLFLAG_RD, &txq->kern_tls_octets, 4921 "# of payload octets in transmitted NIC TLS records"); 4922 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_waste", 4923 CTLFLAG_RD, &txq->kern_tls_waste, 4924 "# of octets DMAd but not transmitted in NIC TLS records"); 4925 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_header", 4926 CTLFLAG_RD, &txq->kern_tls_header, 4927 "# of NIC TLS header-only packets transmitted"); 4928 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_fin_short", 4929 CTLFLAG_RD, &txq->kern_tls_fin_short, 4930 "# of NIC TLS padded FIN packets on short TLS records"); 4931 if (is_t6(sc)) { 4932 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, 4933 "kern_tls_options", CTLFLAG_RD, 4934 &txq->kern_tls_options, 4935 "# of NIC TLS options-only packets transmitted"); 4936 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, 4937 "kern_tls_fin", CTLFLAG_RD, &txq->kern_tls_fin, 4938 "# of NIC TLS FIN-only packets transmitted"); 4939 } else { 4940 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, 4941 "kern_tls_ghash_received", CTLFLAG_RD, 4942 &txq->kern_tls_ghash_received, 4943 "# of NIC TLS GHASHes received"); 4944 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, 4945 "kern_tls_ghash_requested", CTLFLAG_RD, 4946 &txq->kern_tls_ghash_requested, 4947 "# of NIC TLS GHASHes requested"); 4948 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, 4949 "kern_tls_lso", CTLFLAG_RD, 4950 &txq->kern_tls_lso, 4951 "# of NIC TLS records transmitted using LSO"); 4952 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, 4953 "kern_tls_partial_ghash", CTLFLAG_RD, 4954 &txq->kern_tls_partial_ghash, 4955 "# of NIC TLS records encrypted using a partial GHASH"); 4956 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, 4957 "kern_tls_splitmode", CTLFLAG_RD, 4958 &txq->kern_tls_splitmode, 4959 "# of NIC TLS records using SplitMode"); 4960 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, 4961 "kern_tls_trailer", CTLFLAG_RD, 4962 &txq->kern_tls_trailer, 4963 "# of NIC TLS trailer-only packets transmitted"); 4964 } 4965 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_cbc", 4966 CTLFLAG_RD, &txq->kern_tls_cbc, 4967 "# of NIC TLS sessions using AES-CBC"); 4968 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_gcm", 4969 CTLFLAG_RD, &txq->kern_tls_gcm, 4970 "# of NIC TLS sessions using AES-GCM"); 4971 } 4972 #endif 4973 } 4974 4975 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 4976 /* 4977 * Idempotent. 4978 */ 4979 static int 4980 alloc_ofld_txq(struct vi_info *vi, struct sge_ofld_txq *ofld_txq, int idx) 4981 { 4982 struct sysctl_oid *oid; 4983 struct port_info *pi = vi->pi; 4984 struct adapter *sc = vi->adapter; 4985 struct sge_eq *eq = &ofld_txq->wrq.eq; 4986 int rc, iqidx; 4987 char name[16]; 4988 4989 MPASS(idx >= 0); 4990 MPASS(idx < vi->nofldtxq); 4991 4992 if (!(eq->flags & EQ_SW_ALLOCATED)) { 4993 snprintf(name, sizeof(name), "%d", idx); 4994 oid = SYSCTL_ADD_NODE(&vi->ctx, 4995 SYSCTL_CHILDREN(vi->ofld_txq_oid), OID_AUTO, name, 4996 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "offload tx queue"); 4997 4998 snprintf(name, sizeof(name), "%s ofld_txq%d", 4999 device_get_nameunit(vi->dev), idx); 5000 if (vi->nofldrxq > 0) { 5001 iqidx = vi->first_ofld_rxq + (idx % vi->nofldrxq); 5002 init_eq(sc, eq, EQ_OFLD, vi->qsize_txq, pi->port_id, 5003 &sc->sge.ofld_rxq[iqidx].iq, name); 5004 } else { 5005 iqidx = vi->first_rxq + (idx % vi->nrxq); 5006 init_eq(sc, eq, EQ_OFLD, vi->qsize_txq, pi->port_id, 5007 &sc->sge.rxq[iqidx].iq, name); 5008 } 5009 5010 rc = alloc_wrq(sc, vi, &ofld_txq->wrq, &vi->ctx, oid); 5011 if (rc != 0) { 5012 CH_ERR(vi, "failed to allocate ofld_txq%d: %d\n", idx, 5013 rc); 5014 sysctl_remove_oid(oid, 1, 1); 5015 return (rc); 5016 } 5017 MPASS(eq->flags & EQ_SW_ALLOCATED); 5018 /* Can't fail after this point. */ 5019 5020 ofld_txq->tx_iscsi_pdus = counter_u64_alloc(M_WAITOK); 5021 ofld_txq->tx_iscsi_octets = counter_u64_alloc(M_WAITOK); 5022 ofld_txq->tx_iscsi_iso_wrs = counter_u64_alloc(M_WAITOK); 5023 ofld_txq->tx_nvme_pdus = counter_u64_alloc(M_WAITOK); 5024 ofld_txq->tx_nvme_octets = counter_u64_alloc(M_WAITOK); 5025 ofld_txq->tx_nvme_iso_wrs = counter_u64_alloc(M_WAITOK); 5026 ofld_txq->tx_aio_jobs = counter_u64_alloc(M_WAITOK); 5027 ofld_txq->tx_aio_octets = counter_u64_alloc(M_WAITOK); 5028 ofld_txq->tx_toe_tls_records = counter_u64_alloc(M_WAITOK); 5029 ofld_txq->tx_toe_tls_octets = counter_u64_alloc(M_WAITOK); 5030 add_ofld_txq_sysctls(&vi->ctx, oid, ofld_txq); 5031 } 5032 5033 if (!(eq->flags & EQ_HW_ALLOCATED)) { 5034 MPASS(eq->flags & EQ_SW_ALLOCATED); 5035 MPASS(ofld_txq->wrq.nwr_pending == 0); 5036 MPASS(ofld_txq->wrq.ndesc_needed == 0); 5037 rc = alloc_eq_hwq(sc, vi, eq, idx); 5038 if (rc != 0) { 5039 CH_ERR(vi, "failed to create hw ofld_txq%d: %d\n", idx, 5040 rc); 5041 return (rc); 5042 } 5043 MPASS(eq->flags & EQ_HW_ALLOCATED); 5044 } 5045 5046 return (0); 5047 } 5048 5049 /* 5050 * Idempotent. 5051 */ 5052 static void 5053 free_ofld_txq(struct vi_info *vi, struct sge_ofld_txq *ofld_txq) 5054 { 5055 struct adapter *sc = vi->adapter; 5056 struct sge_eq *eq = &ofld_txq->wrq.eq; 5057 5058 if (eq->flags & EQ_HW_ALLOCATED) { 5059 MPASS(eq->flags & EQ_SW_ALLOCATED); 5060 free_eq_hwq(sc, NULL, eq); 5061 MPASS(!(eq->flags & EQ_HW_ALLOCATED)); 5062 } 5063 5064 if (eq->flags & EQ_SW_ALLOCATED) { 5065 MPASS(!(eq->flags & EQ_HW_ALLOCATED)); 5066 counter_u64_free(ofld_txq->tx_iscsi_pdus); 5067 counter_u64_free(ofld_txq->tx_iscsi_octets); 5068 counter_u64_free(ofld_txq->tx_iscsi_iso_wrs); 5069 counter_u64_free(ofld_txq->tx_nvme_pdus); 5070 counter_u64_free(ofld_txq->tx_nvme_octets); 5071 counter_u64_free(ofld_txq->tx_nvme_iso_wrs); 5072 counter_u64_free(ofld_txq->tx_aio_jobs); 5073 counter_u64_free(ofld_txq->tx_aio_octets); 5074 counter_u64_free(ofld_txq->tx_toe_tls_records); 5075 counter_u64_free(ofld_txq->tx_toe_tls_octets); 5076 free_wrq(sc, &ofld_txq->wrq); 5077 MPASS(!(eq->flags & EQ_SW_ALLOCATED)); 5078 bzero(ofld_txq, sizeof(*ofld_txq)); 5079 } 5080 } 5081 5082 static void 5083 add_ofld_txq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid, 5084 struct sge_ofld_txq *ofld_txq) 5085 { 5086 struct sysctl_oid_list *children; 5087 5088 if (ctx == NULL || oid == NULL) 5089 return; 5090 5091 children = SYSCTL_CHILDREN(oid); 5092 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_iscsi_pdus", 5093 CTLFLAG_RD, &ofld_txq->tx_iscsi_pdus, 5094 "# of iSCSI PDUs transmitted"); 5095 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_iscsi_octets", 5096 CTLFLAG_RD, &ofld_txq->tx_iscsi_octets, 5097 "# of payload octets in transmitted iSCSI PDUs"); 5098 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_iscsi_iso_wrs", 5099 CTLFLAG_RD, &ofld_txq->tx_iscsi_iso_wrs, 5100 "# of iSCSI segmentation offload work requests"); 5101 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_nvme_pdus", 5102 CTLFLAG_RD, &ofld_txq->tx_nvme_pdus, 5103 "# of NVMe PDUs transmitted"); 5104 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_nvme_octets", 5105 CTLFLAG_RD, &ofld_txq->tx_nvme_octets, 5106 "# of payload octets in transmitted NVMe PDUs"); 5107 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_nvme_iso_wrs", 5108 CTLFLAG_RD, &ofld_txq->tx_nvme_iso_wrs, 5109 "# of NVMe segmentation offload work requests"); 5110 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_aio_jobs", 5111 CTLFLAG_RD, &ofld_txq->tx_aio_jobs, 5112 "# of zero-copy aio_write(2) jobs transmitted"); 5113 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_aio_octets", 5114 CTLFLAG_RD, &ofld_txq->tx_aio_octets, 5115 "# of payload octets in transmitted zero-copy aio_write(2) jobs"); 5116 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_toe_tls_records", 5117 CTLFLAG_RD, &ofld_txq->tx_toe_tls_records, 5118 "# of TOE TLS records transmitted"); 5119 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_toe_tls_octets", 5120 CTLFLAG_RD, &ofld_txq->tx_toe_tls_octets, 5121 "# of payload octets in transmitted TOE TLS records"); 5122 } 5123 #endif 5124 5125 static void 5126 oneseg_dma_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error) 5127 { 5128 bus_addr_t *ba = arg; 5129 5130 KASSERT(nseg == 1, 5131 ("%s meant for single segment mappings only.", __func__)); 5132 5133 *ba = error ? 0 : segs->ds_addr; 5134 } 5135 5136 static inline void 5137 ring_fl_db(struct adapter *sc, struct sge_fl *fl) 5138 { 5139 uint32_t n, v; 5140 5141 n = IDXDIFF(fl->pidx >> 3, fl->dbidx, fl->sidx); 5142 MPASS(n > 0); 5143 5144 wmb(); 5145 v = fl->dbval | V_PIDX(n); 5146 if (fl->udb) 5147 *fl->udb = htole32(v); 5148 else 5149 t4_write_reg(sc, sc->sge_kdoorbell_reg, v); 5150 IDXINCR(fl->dbidx, n, fl->sidx); 5151 } 5152 5153 /* 5154 * Fills up the freelist by allocating up to 'n' buffers. Buffers that are 5155 * recycled do not count towards this allocation budget. 5156 * 5157 * Returns non-zero to indicate that this freelist should be added to the list 5158 * of starving freelists. 5159 */ 5160 static int 5161 refill_fl(struct adapter *sc, struct sge_fl *fl, int n) 5162 { 5163 __be64 *d; 5164 struct fl_sdesc *sd; 5165 uintptr_t pa; 5166 caddr_t cl; 5167 struct rx_buf_info *rxb; 5168 struct cluster_metadata *clm; 5169 uint16_t max_pidx, zidx = fl->zidx; 5170 uint16_t hw_cidx = fl->hw_cidx; /* stable snapshot */ 5171 5172 FL_LOCK_ASSERT_OWNED(fl); 5173 5174 /* 5175 * We always stop at the beginning of the hardware descriptor that's just 5176 * before the one with the hw cidx. This is to avoid hw pidx = hw cidx, 5177 * which would mean an empty freelist to the chip. 5178 */ 5179 max_pidx = __predict_false(hw_cidx == 0) ? fl->sidx - 1 : hw_cidx - 1; 5180 if (fl->pidx == max_pidx * 8) 5181 return (0); 5182 5183 d = &fl->desc[fl->pidx]; 5184 sd = &fl->sdesc[fl->pidx]; 5185 rxb = &sc->sge.rx_buf_info[zidx]; 5186 5187 while (n > 0) { 5188 5189 if (sd->cl != NULL) { 5190 5191 if (sd->nmbuf == 0) { 5192 /* 5193 * Fast recycle without involving any atomics on 5194 * the cluster's metadata (if the cluster has 5195 * metadata). This happens when all frames 5196 * received in the cluster were small enough to 5197 * fit within a single mbuf each. 5198 */ 5199 fl->cl_fast_recycled++; 5200 goto recycled; 5201 } 5202 5203 /* 5204 * Cluster is guaranteed to have metadata. Clusters 5205 * without metadata always take the fast recycle path 5206 * when they're recycled. 5207 */ 5208 clm = cl_metadata(sd); 5209 MPASS(clm != NULL); 5210 5211 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) { 5212 fl->cl_recycled++; 5213 counter_u64_add(extfree_rels, 1); 5214 goto recycled; 5215 } 5216 sd->cl = NULL; /* gave up my reference */ 5217 } 5218 MPASS(sd->cl == NULL); 5219 cl = uma_zalloc(rxb->zone, M_NOWAIT); 5220 if (__predict_false(cl == NULL)) { 5221 if (zidx != fl->safe_zidx) { 5222 zidx = fl->safe_zidx; 5223 rxb = &sc->sge.rx_buf_info[zidx]; 5224 cl = uma_zalloc(rxb->zone, M_NOWAIT); 5225 } 5226 if (cl == NULL) 5227 break; 5228 } 5229 fl->cl_allocated++; 5230 n--; 5231 5232 pa = pmap_kextract((vm_offset_t)cl); 5233 sd->cl = cl; 5234 sd->zidx = zidx; 5235 5236 if (fl->flags & FL_BUF_PACKING) { 5237 *d = htobe64(pa | rxb->hwidx2); 5238 sd->moff = rxb->size2; 5239 } else { 5240 *d = htobe64(pa | rxb->hwidx1); 5241 sd->moff = 0; 5242 } 5243 recycled: 5244 sd->nmbuf = 0; 5245 d++; 5246 sd++; 5247 if (__predict_false((++fl->pidx & 7) == 0)) { 5248 uint16_t pidx = fl->pidx >> 3; 5249 5250 if (__predict_false(pidx == fl->sidx)) { 5251 fl->pidx = 0; 5252 pidx = 0; 5253 sd = fl->sdesc; 5254 d = fl->desc; 5255 } 5256 if (n < 8 || pidx == max_pidx) 5257 break; 5258 5259 if (IDXDIFF(pidx, fl->dbidx, fl->sidx) >= 4) 5260 ring_fl_db(sc, fl); 5261 } 5262 } 5263 5264 if ((fl->pidx >> 3) != fl->dbidx) 5265 ring_fl_db(sc, fl); 5266 5267 return (FL_RUNNING_LOW(fl) && !(fl->flags & FL_STARVING)); 5268 } 5269 5270 /* 5271 * Attempt to refill all starving freelists. 5272 */ 5273 static void 5274 refill_sfl(void *arg) 5275 { 5276 struct adapter *sc = arg; 5277 struct sge_fl *fl, *fl_temp; 5278 5279 mtx_assert(&sc->sfl_lock, MA_OWNED); 5280 TAILQ_FOREACH_SAFE(fl, &sc->sfl, link, fl_temp) { 5281 FL_LOCK(fl); 5282 refill_fl(sc, fl, 64); 5283 if (FL_NOT_RUNNING_LOW(fl) || fl->flags & FL_DOOMED) { 5284 TAILQ_REMOVE(&sc->sfl, fl, link); 5285 fl->flags &= ~FL_STARVING; 5286 } 5287 FL_UNLOCK(fl); 5288 } 5289 5290 if (!TAILQ_EMPTY(&sc->sfl)) 5291 callout_schedule(&sc->sfl_callout, hz / 5); 5292 } 5293 5294 /* 5295 * Release the driver's reference on all buffers in the given freelist. Buffers 5296 * with kernel references cannot be freed and will prevent the driver from being 5297 * unloaded safely. 5298 */ 5299 void 5300 free_fl_buffers(struct adapter *sc, struct sge_fl *fl) 5301 { 5302 struct fl_sdesc *sd; 5303 struct cluster_metadata *clm; 5304 int i; 5305 5306 sd = fl->sdesc; 5307 for (i = 0; i < fl->sidx * 8; i++, sd++) { 5308 if (sd->cl == NULL) 5309 continue; 5310 5311 if (sd->nmbuf == 0) 5312 uma_zfree(sc->sge.rx_buf_info[sd->zidx].zone, sd->cl); 5313 else if (fl->flags & FL_BUF_PACKING) { 5314 clm = cl_metadata(sd); 5315 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) { 5316 uma_zfree(sc->sge.rx_buf_info[sd->zidx].zone, 5317 sd->cl); 5318 counter_u64_add(extfree_rels, 1); 5319 } 5320 } 5321 sd->cl = NULL; 5322 } 5323 5324 if (fl->flags & FL_BUF_RESUME) { 5325 m_freem(fl->m0); 5326 fl->flags &= ~FL_BUF_RESUME; 5327 } 5328 } 5329 5330 static inline void 5331 get_pkt_gl(struct mbuf *m, struct sglist *gl) 5332 { 5333 int rc; 5334 5335 M_ASSERTPKTHDR(m); 5336 5337 sglist_reset(gl); 5338 rc = sglist_append_mbuf(gl, m); 5339 if (__predict_false(rc != 0)) { 5340 panic("%s: mbuf %p (%d segs) was vetted earlier but now fails " 5341 "with %d.", __func__, m, mbuf_nsegs(m), rc); 5342 } 5343 5344 KASSERT(gl->sg_nseg == mbuf_nsegs(m), 5345 ("%s: nsegs changed for mbuf %p from %d to %d", __func__, m, 5346 mbuf_nsegs(m), gl->sg_nseg)); 5347 #if 0 /* vm_wr not readily available here. */ 5348 KASSERT(gl->sg_nseg > 0 && gl->sg_nseg <= max_nsegs_allowed(m, vm_wr), 5349 ("%s: %d segments, should have been 1 <= nsegs <= %d", __func__, 5350 gl->sg_nseg, max_nsegs_allowed(m, vm_wr))); 5351 #endif 5352 } 5353 5354 /* 5355 * len16 for a txpkt WR with a GL. Includes the firmware work request header. 5356 */ 5357 static inline u_int 5358 txpkt_len16(u_int nsegs, const u_int extra) 5359 { 5360 u_int n; 5361 5362 MPASS(nsegs > 0); 5363 5364 nsegs--; /* first segment is part of ulptx_sgl */ 5365 n = extra + sizeof(struct fw_eth_tx_pkt_wr) + 5366 sizeof(struct cpl_tx_pkt_core) + 5367 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 5368 5369 return (howmany(n, 16)); 5370 } 5371 5372 /* 5373 * len16 for a txpkt_vm WR with a GL. Includes the firmware work 5374 * request header. 5375 */ 5376 static inline u_int 5377 txpkt_vm_len16(u_int nsegs, const u_int extra) 5378 { 5379 u_int n; 5380 5381 MPASS(nsegs > 0); 5382 5383 nsegs--; /* first segment is part of ulptx_sgl */ 5384 n = extra + sizeof(struct fw_eth_tx_pkt_vm_wr) + 5385 sizeof(struct cpl_tx_pkt_core) + 5386 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 5387 5388 return (howmany(n, 16)); 5389 } 5390 5391 static inline void 5392 calculate_mbuf_len16(struct mbuf *m, bool vm_wr) 5393 { 5394 const int lso = sizeof(struct cpl_tx_pkt_lso_core); 5395 const int tnl_lso = sizeof(struct cpl_tx_tnl_lso); 5396 5397 if (vm_wr) { 5398 if (needs_tso(m)) 5399 set_mbuf_len16(m, txpkt_vm_len16(mbuf_nsegs(m), lso)); 5400 else 5401 set_mbuf_len16(m, txpkt_vm_len16(mbuf_nsegs(m), 0)); 5402 return; 5403 } 5404 5405 if (needs_tso(m)) { 5406 if (needs_vxlan_tso(m)) 5407 set_mbuf_len16(m, txpkt_len16(mbuf_nsegs(m), tnl_lso)); 5408 else 5409 set_mbuf_len16(m, txpkt_len16(mbuf_nsegs(m), lso)); 5410 } else 5411 set_mbuf_len16(m, txpkt_len16(mbuf_nsegs(m), 0)); 5412 } 5413 5414 /* 5415 * len16 for a txpkts type 0 WR with a GL. Does not include the firmware work 5416 * request header. 5417 */ 5418 static inline u_int 5419 txpkts0_len16(u_int nsegs) 5420 { 5421 u_int n; 5422 5423 MPASS(nsegs > 0); 5424 5425 nsegs--; /* first segment is part of ulptx_sgl */ 5426 n = sizeof(struct ulp_txpkt) + sizeof(struct ulptx_idata) + 5427 sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl) + 5428 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 5429 5430 return (howmany(n, 16)); 5431 } 5432 5433 /* 5434 * len16 for a txpkts type 1 WR with a GL. Does not include the firmware work 5435 * request header. 5436 */ 5437 static inline u_int 5438 txpkts1_len16(void) 5439 { 5440 u_int n; 5441 5442 n = sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl); 5443 5444 return (howmany(n, 16)); 5445 } 5446 5447 static inline u_int 5448 imm_payload(u_int ndesc) 5449 { 5450 u_int n; 5451 5452 n = ndesc * EQ_ESIZE - sizeof(struct fw_eth_tx_pkt_wr) - 5453 sizeof(struct cpl_tx_pkt_core); 5454 5455 return (n); 5456 } 5457 5458 static inline uint64_t 5459 csum_to_ctrl(struct adapter *sc, struct mbuf *m) 5460 { 5461 uint64_t ctrl; 5462 int csum_type, l2hlen, l3hlen; 5463 int x, y; 5464 static const int csum_types[3][2] = { 5465 {TX_CSUM_TCPIP, TX_CSUM_TCPIP6}, 5466 {TX_CSUM_UDPIP, TX_CSUM_UDPIP6}, 5467 {TX_CSUM_IP, 0} 5468 }; 5469 5470 M_ASSERTPKTHDR(m); 5471 5472 if (!needs_hwcsum(m)) 5473 return (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS); 5474 5475 MPASS(m->m_pkthdr.l2hlen >= ETHER_HDR_LEN); 5476 MPASS(m->m_pkthdr.l3hlen >= sizeof(struct ip)); 5477 5478 if (needs_vxlan_csum(m)) { 5479 MPASS(m->m_pkthdr.l4hlen > 0); 5480 MPASS(m->m_pkthdr.l5hlen > 0); 5481 MPASS(m->m_pkthdr.inner_l2hlen >= ETHER_HDR_LEN); 5482 MPASS(m->m_pkthdr.inner_l3hlen >= sizeof(struct ip)); 5483 5484 l2hlen = m->m_pkthdr.l2hlen + m->m_pkthdr.l3hlen + 5485 m->m_pkthdr.l4hlen + m->m_pkthdr.l5hlen + 5486 m->m_pkthdr.inner_l2hlen - ETHER_HDR_LEN; 5487 l3hlen = m->m_pkthdr.inner_l3hlen; 5488 } else { 5489 l2hlen = m->m_pkthdr.l2hlen - ETHER_HDR_LEN; 5490 l3hlen = m->m_pkthdr.l3hlen; 5491 } 5492 5493 ctrl = 0; 5494 if (!needs_l3_csum(m)) 5495 ctrl |= F_TXPKT_IPCSUM_DIS; 5496 5497 if (m->m_pkthdr.csum_flags & (CSUM_IP_TCP | CSUM_INNER_IP_TCP | 5498 CSUM_IP6_TCP | CSUM_INNER_IP6_TCP)) 5499 x = 0; /* TCP */ 5500 else if (m->m_pkthdr.csum_flags & (CSUM_IP_UDP | CSUM_INNER_IP_UDP | 5501 CSUM_IP6_UDP | CSUM_INNER_IP6_UDP)) 5502 x = 1; /* UDP */ 5503 else 5504 x = 2; 5505 5506 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_IP_TCP | CSUM_IP_UDP | 5507 CSUM_INNER_IP | CSUM_INNER_IP_TCP | CSUM_INNER_IP_UDP)) 5508 y = 0; /* IPv4 */ 5509 else { 5510 MPASS(m->m_pkthdr.csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | 5511 CSUM_INNER_IP6_TCP | CSUM_INNER_IP6_UDP)); 5512 y = 1; /* IPv6 */ 5513 } 5514 /* 5515 * needs_hwcsum returned true earlier so there must be some kind of 5516 * checksum to calculate. 5517 */ 5518 csum_type = csum_types[x][y]; 5519 MPASS(csum_type != 0); 5520 if (csum_type == TX_CSUM_IP) 5521 ctrl |= F_TXPKT_L4CSUM_DIS; 5522 ctrl |= V_TXPKT_CSUM_TYPE(csum_type) | V_TXPKT_IPHDR_LEN(l3hlen); 5523 if (chip_id(sc) <= CHELSIO_T5) 5524 ctrl |= V_TXPKT_ETHHDR_LEN(l2hlen); 5525 else 5526 ctrl |= V_T6_TXPKT_ETHHDR_LEN(l2hlen); 5527 5528 return (ctrl); 5529 } 5530 5531 static inline void * 5532 write_lso_cpl(void *cpl, struct mbuf *m0) 5533 { 5534 struct cpl_tx_pkt_lso_core *lso; 5535 uint32_t ctrl; 5536 5537 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 5538 m0->m_pkthdr.l4hlen > 0, 5539 ("%s: mbuf %p needs TSO but missing header lengths", 5540 __func__, m0)); 5541 5542 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | 5543 F_LSO_FIRST_SLICE | F_LSO_LAST_SLICE | 5544 V_LSO_ETHHDR_LEN((m0->m_pkthdr.l2hlen - ETHER_HDR_LEN) >> 2) | 5545 V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) | 5546 V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2); 5547 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 5548 ctrl |= F_LSO_IPV6; 5549 5550 lso = cpl; 5551 lso->lso_ctrl = htobe32(ctrl); 5552 lso->ipid_ofst = htobe16(0); 5553 lso->mss = htobe16(m0->m_pkthdr.tso_segsz); 5554 lso->seqno_offset = htobe32(0); 5555 lso->len = htobe32(m0->m_pkthdr.len); 5556 5557 return (lso + 1); 5558 } 5559 5560 static void * 5561 write_tnl_lso_cpl(void *cpl, struct mbuf *m0) 5562 { 5563 struct cpl_tx_tnl_lso *tnl_lso = cpl; 5564 uint32_t ctrl; 5565 5566 KASSERT(m0->m_pkthdr.inner_l2hlen > 0 && 5567 m0->m_pkthdr.inner_l3hlen > 0 && m0->m_pkthdr.inner_l4hlen > 0 && 5568 m0->m_pkthdr.inner_l5hlen > 0, 5569 ("%s: mbuf %p needs VXLAN_TSO but missing inner header lengths", 5570 __func__, m0)); 5571 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 5572 m0->m_pkthdr.l4hlen > 0 && m0->m_pkthdr.l5hlen > 0, 5573 ("%s: mbuf %p needs VXLAN_TSO but missing outer header lengths", 5574 __func__, m0)); 5575 5576 /* Outer headers. */ 5577 ctrl = V_CPL_TX_TNL_LSO_OPCODE(CPL_TX_TNL_LSO) | 5578 F_CPL_TX_TNL_LSO_FIRST | F_CPL_TX_TNL_LSO_LAST | 5579 V_CPL_TX_TNL_LSO_ETHHDRLENOUT( 5580 (m0->m_pkthdr.l2hlen - ETHER_HDR_LEN) >> 2) | 5581 V_CPL_TX_TNL_LSO_IPHDRLENOUT(m0->m_pkthdr.l3hlen >> 2) | 5582 F_CPL_TX_TNL_LSO_IPLENSETOUT; 5583 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 5584 ctrl |= F_CPL_TX_TNL_LSO_IPV6OUT; 5585 else { 5586 ctrl |= F_CPL_TX_TNL_LSO_IPHDRCHKOUT | 5587 F_CPL_TX_TNL_LSO_IPIDINCOUT; 5588 } 5589 tnl_lso->op_to_IpIdSplitOut = htobe32(ctrl); 5590 tnl_lso->IpIdOffsetOut = 0; 5591 tnl_lso->UdpLenSetOut_to_TnlHdrLen = 5592 htobe16(F_CPL_TX_TNL_LSO_UDPCHKCLROUT | 5593 F_CPL_TX_TNL_LSO_UDPLENSETOUT | 5594 V_CPL_TX_TNL_LSO_TNLHDRLEN(m0->m_pkthdr.l2hlen + 5595 m0->m_pkthdr.l3hlen + m0->m_pkthdr.l4hlen + 5596 m0->m_pkthdr.l5hlen) | 5597 V_CPL_TX_TNL_LSO_TNLTYPE(TX_TNL_TYPE_VXLAN)); 5598 tnl_lso->ipsecen_to_rocev2 = 0; 5599 tnl_lso->roce_eth = 0; 5600 5601 /* Inner headers. */ 5602 ctrl = V_CPL_TX_TNL_LSO_ETHHDRLEN( 5603 (m0->m_pkthdr.inner_l2hlen - ETHER_HDR_LEN) >> 2) | 5604 V_CPL_TX_TNL_LSO_IPHDRLEN(m0->m_pkthdr.inner_l3hlen >> 2) | 5605 V_CPL_TX_TNL_LSO_TCPHDRLEN(m0->m_pkthdr.inner_l4hlen >> 2); 5606 if (m0->m_pkthdr.inner_l3hlen == sizeof(struct ip6_hdr)) 5607 ctrl |= F_CPL_TX_TNL_LSO_IPV6; 5608 tnl_lso->Flow_to_TcpHdrLen = htobe32(ctrl); 5609 tnl_lso->IpIdOffset = 0; 5610 tnl_lso->IpIdSplit_to_Mss = 5611 htobe16(V_CPL_TX_TNL_LSO_MSS(m0->m_pkthdr.tso_segsz)); 5612 tnl_lso->TCPSeqOffset = 0; 5613 tnl_lso->EthLenOffset_Size = 5614 htobe32(V_CPL_TX_TNL_LSO_SIZE(m0->m_pkthdr.len)); 5615 5616 return (tnl_lso + 1); 5617 } 5618 5619 #define VM_TX_L2HDR_LEN 16 /* ethmacdst to vlantci */ 5620 5621 /* 5622 * Write a VM txpkt WR for this packet to the hardware descriptors, update the 5623 * software descriptor, and advance the pidx. It is guaranteed that enough 5624 * descriptors are available. 5625 * 5626 * The return value is the # of hardware descriptors used. 5627 */ 5628 static u_int 5629 write_txpkt_vm_wr(struct adapter *sc, struct sge_txq *txq, struct mbuf *m0) 5630 { 5631 struct sge_eq *eq; 5632 struct fw_eth_tx_pkt_vm_wr *wr; 5633 struct tx_sdesc *txsd; 5634 struct cpl_tx_pkt_core *cpl; 5635 uint32_t ctrl; /* used in many unrelated places */ 5636 uint64_t ctrl1; 5637 int len16, ndesc, pktlen; 5638 caddr_t dst; 5639 5640 TXQ_LOCK_ASSERT_OWNED(txq); 5641 M_ASSERTPKTHDR(m0); 5642 5643 len16 = mbuf_len16(m0); 5644 pktlen = m0->m_pkthdr.len; 5645 ctrl = sizeof(struct cpl_tx_pkt_core); 5646 if (needs_tso(m0)) 5647 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 5648 ndesc = tx_len16_to_desc(len16); 5649 5650 /* Firmware work request header */ 5651 eq = &txq->eq; 5652 wr = (void *)&eq->desc[eq->pidx]; 5653 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_VM_WR) | 5654 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl)); 5655 5656 ctrl = V_FW_WR_LEN16(len16); 5657 wr->equiq_to_len16 = htobe32(ctrl); 5658 wr->r3[0] = 0; 5659 wr->r3[1] = 0; 5660 5661 /* 5662 * Copy over ethmacdst, ethmacsrc, ethtype, and vlantci. 5663 * vlantci is ignored unless the ethtype is 0x8100, so it's 5664 * simpler to always copy it rather than making it 5665 * conditional. Also, it seems that we do not have to set 5666 * vlantci or fake the ethtype when doing VLAN tag insertion. 5667 */ 5668 m_copydata(m0, 0, VM_TX_L2HDR_LEN, wr->ethmacdst); 5669 5670 if (needs_tso(m0)) { 5671 cpl = write_lso_cpl(wr + 1, m0); 5672 txq->tso_wrs++; 5673 } else 5674 cpl = (void *)(wr + 1); 5675 5676 /* Checksum offload */ 5677 ctrl1 = csum_to_ctrl(sc, m0); 5678 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS)) 5679 txq->txcsum++; /* some hardware assistance provided */ 5680 5681 /* VLAN tag insertion */ 5682 if (needs_vlan_insertion(m0)) { 5683 ctrl1 |= F_TXPKT_VLAN_VLD | 5684 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 5685 txq->vlan_insertion++; 5686 } else if (sc->vlan_id) 5687 ctrl1 |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(sc->vlan_id); 5688 5689 /* CPL header */ 5690 cpl->ctrl0 = txq->cpl_ctrl0; 5691 cpl->pack = 0; 5692 cpl->len = htobe16(pktlen); 5693 cpl->ctrl1 = htobe64(ctrl1); 5694 5695 /* SGL */ 5696 dst = (void *)(cpl + 1); 5697 5698 /* 5699 * A packet using TSO will use up an entire descriptor for the 5700 * firmware work request header, LSO CPL, and TX_PKT_XT CPL. 5701 * If this descriptor is the last descriptor in the ring, wrap 5702 * around to the front of the ring explicitly for the start of 5703 * the sgl. 5704 */ 5705 if (dst == (void *)&eq->desc[eq->sidx]) { 5706 dst = (void *)&eq->desc[0]; 5707 write_gl_to_txd(txq, m0, &dst, 0); 5708 } else 5709 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx); 5710 txq->sgl_wrs++; 5711 txq->txpkt_wrs++; 5712 5713 txsd = &txq->sdesc[eq->pidx]; 5714 txsd->m = m0; 5715 txsd->desc_used = ndesc; 5716 5717 return (ndesc); 5718 } 5719 5720 /* 5721 * Write a raw WR to the hardware descriptors, update the software 5722 * descriptor, and advance the pidx. It is guaranteed that enough 5723 * descriptors are available. 5724 * 5725 * The return value is the # of hardware descriptors used. 5726 */ 5727 static u_int 5728 write_raw_wr(struct sge_txq *txq, void *wr, struct mbuf *m0, u_int available) 5729 { 5730 struct sge_eq *eq = &txq->eq; 5731 struct tx_sdesc *txsd; 5732 struct mbuf *m; 5733 caddr_t dst; 5734 int len16, ndesc; 5735 5736 len16 = mbuf_len16(m0); 5737 ndesc = tx_len16_to_desc(len16); 5738 MPASS(ndesc <= available); 5739 5740 dst = wr; 5741 for (m = m0; m != NULL; m = m->m_next) 5742 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len); 5743 5744 txq->raw_wrs++; 5745 5746 txsd = &txq->sdesc[eq->pidx]; 5747 txsd->m = m0; 5748 txsd->desc_used = ndesc; 5749 5750 return (ndesc); 5751 } 5752 5753 /* 5754 * Write a txpkt WR for this packet to the hardware descriptors, update the 5755 * software descriptor, and advance the pidx. It is guaranteed that enough 5756 * descriptors are available. 5757 * 5758 * The return value is the # of hardware descriptors used. 5759 */ 5760 static u_int 5761 write_txpkt_wr(struct adapter *sc, struct sge_txq *txq, struct mbuf *m0, 5762 u_int available) 5763 { 5764 struct sge_eq *eq; 5765 struct fw_eth_tx_pkt_wr *wr; 5766 struct tx_sdesc *txsd; 5767 struct cpl_tx_pkt_core *cpl; 5768 uint32_t ctrl; /* used in many unrelated places */ 5769 uint64_t ctrl1; 5770 int len16, ndesc, pktlen, nsegs; 5771 caddr_t dst; 5772 5773 TXQ_LOCK_ASSERT_OWNED(txq); 5774 M_ASSERTPKTHDR(m0); 5775 5776 len16 = mbuf_len16(m0); 5777 nsegs = mbuf_nsegs(m0); 5778 pktlen = m0->m_pkthdr.len; 5779 ctrl = sizeof(struct cpl_tx_pkt_core); 5780 if (needs_tso(m0)) { 5781 if (needs_vxlan_tso(m0)) 5782 ctrl += sizeof(struct cpl_tx_tnl_lso); 5783 else 5784 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 5785 } else if (!(mbuf_cflags(m0) & MC_NOMAP) && pktlen <= imm_payload(2) && 5786 available >= 2) { 5787 /* Immediate data. Recalculate len16 and set nsegs to 0. */ 5788 ctrl += pktlen; 5789 len16 = howmany(sizeof(struct fw_eth_tx_pkt_wr) + 5790 sizeof(struct cpl_tx_pkt_core) + pktlen, 16); 5791 nsegs = 0; 5792 } 5793 ndesc = tx_len16_to_desc(len16); 5794 MPASS(ndesc <= available); 5795 5796 /* Firmware work request header */ 5797 eq = &txq->eq; 5798 wr = (void *)&eq->desc[eq->pidx]; 5799 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_WR) | 5800 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl)); 5801 5802 ctrl = V_FW_WR_LEN16(len16); 5803 wr->equiq_to_len16 = htobe32(ctrl); 5804 wr->r3 = 0; 5805 5806 if (needs_tso(m0)) { 5807 if (needs_vxlan_tso(m0)) { 5808 cpl = write_tnl_lso_cpl(wr + 1, m0); 5809 txq->vxlan_tso_wrs++; 5810 } else { 5811 cpl = write_lso_cpl(wr + 1, m0); 5812 txq->tso_wrs++; 5813 } 5814 } else 5815 cpl = (void *)(wr + 1); 5816 5817 /* Checksum offload */ 5818 ctrl1 = csum_to_ctrl(sc, m0); 5819 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS)) { 5820 /* some hardware assistance provided */ 5821 if (needs_vxlan_csum(m0)) 5822 txq->vxlan_txcsum++; 5823 else 5824 txq->txcsum++; 5825 } 5826 5827 /* VLAN tag insertion */ 5828 if (needs_vlan_insertion(m0)) { 5829 ctrl1 |= F_TXPKT_VLAN_VLD | 5830 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 5831 txq->vlan_insertion++; 5832 } 5833 5834 /* CPL header */ 5835 cpl->ctrl0 = txq->cpl_ctrl0; 5836 cpl->pack = 0; 5837 cpl->len = htobe16(pktlen); 5838 cpl->ctrl1 = htobe64(ctrl1); 5839 5840 /* SGL */ 5841 dst = (void *)(cpl + 1); 5842 if (__predict_false((uintptr_t)dst == (uintptr_t)&eq->desc[eq->sidx])) 5843 dst = (caddr_t)&eq->desc[0]; 5844 if (nsegs > 0) { 5845 5846 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx); 5847 txq->sgl_wrs++; 5848 } else { 5849 struct mbuf *m; 5850 5851 for (m = m0; m != NULL; m = m->m_next) { 5852 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len); 5853 #ifdef INVARIANTS 5854 pktlen -= m->m_len; 5855 #endif 5856 } 5857 #ifdef INVARIANTS 5858 KASSERT(pktlen == 0, ("%s: %d bytes left.", __func__, pktlen)); 5859 #endif 5860 txq->imm_wrs++; 5861 } 5862 5863 txq->txpkt_wrs++; 5864 5865 txsd = &txq->sdesc[eq->pidx]; 5866 txsd->m = m0; 5867 txsd->desc_used = ndesc; 5868 5869 return (ndesc); 5870 } 5871 5872 static inline bool 5873 cmp_l2hdr(struct txpkts *txp, struct mbuf *m) 5874 { 5875 int len; 5876 5877 MPASS(txp->npkt > 0); 5878 MPASS(m->m_len >= VM_TX_L2HDR_LEN); 5879 5880 if (txp->ethtype == be16toh(ETHERTYPE_VLAN)) 5881 len = VM_TX_L2HDR_LEN; 5882 else 5883 len = sizeof(struct ether_header); 5884 5885 return (memcmp(m->m_data, &txp->ethmacdst[0], len) != 0); 5886 } 5887 5888 static inline void 5889 save_l2hdr(struct txpkts *txp, struct mbuf *m) 5890 { 5891 MPASS(m->m_len >= VM_TX_L2HDR_LEN); 5892 5893 memcpy(&txp->ethmacdst[0], mtod(m, const void *), VM_TX_L2HDR_LEN); 5894 } 5895 5896 static int 5897 add_to_txpkts_vf(struct adapter *sc, struct sge_txq *txq, struct mbuf *m, 5898 int avail, bool *send) 5899 { 5900 struct txpkts *txp = &txq->txp; 5901 5902 /* Cannot have TSO and coalesce at the same time. */ 5903 if (cannot_use_txpkts(m)) { 5904 cannot_coalesce: 5905 *send = txp->npkt > 0; 5906 return (EINVAL); 5907 } 5908 5909 /* VF allows coalescing of type 1 (1 GL) only */ 5910 if (mbuf_nsegs(m) > 1) 5911 goto cannot_coalesce; 5912 5913 *send = false; 5914 if (txp->npkt > 0) { 5915 MPASS(tx_len16_to_desc(txp->len16) <= avail); 5916 MPASS(txp->npkt < txp->max_npkt); 5917 MPASS(txp->wr_type == 1); /* VF supports type 1 only */ 5918 5919 if (tx_len16_to_desc(txp->len16 + txpkts1_len16()) > avail) { 5920 retry_after_send: 5921 *send = true; 5922 return (EAGAIN); 5923 } 5924 if (m->m_pkthdr.len + txp->plen > 65535) 5925 goto retry_after_send; 5926 if (cmp_l2hdr(txp, m)) 5927 goto retry_after_send; 5928 5929 txp->len16 += txpkts1_len16(); 5930 txp->plen += m->m_pkthdr.len; 5931 txp->mb[txp->npkt++] = m; 5932 if (txp->npkt == txp->max_npkt) 5933 *send = true; 5934 } else { 5935 txp->len16 = howmany(sizeof(struct fw_eth_tx_pkts_vm_wr), 16) + 5936 txpkts1_len16(); 5937 if (tx_len16_to_desc(txp->len16) > avail) 5938 goto cannot_coalesce; 5939 txp->npkt = 1; 5940 txp->wr_type = 1; 5941 txp->plen = m->m_pkthdr.len; 5942 txp->mb[0] = m; 5943 save_l2hdr(txp, m); 5944 } 5945 return (0); 5946 } 5947 5948 static int 5949 add_to_txpkts_pf(struct adapter *sc, struct sge_txq *txq, struct mbuf *m, 5950 int avail, bool *send) 5951 { 5952 struct txpkts *txp = &txq->txp; 5953 int nsegs; 5954 5955 MPASS(!(sc->flags & IS_VF)); 5956 5957 /* Cannot have TSO and coalesce at the same time. */ 5958 if (cannot_use_txpkts(m)) { 5959 cannot_coalesce: 5960 *send = txp->npkt > 0; 5961 return (EINVAL); 5962 } 5963 5964 *send = false; 5965 nsegs = mbuf_nsegs(m); 5966 if (txp->npkt == 0) { 5967 if (m->m_pkthdr.len > 65535) 5968 goto cannot_coalesce; 5969 if (nsegs > 1) { 5970 txp->wr_type = 0; 5971 txp->len16 = 5972 howmany(sizeof(struct fw_eth_tx_pkts_wr), 16) + 5973 txpkts0_len16(nsegs); 5974 } else { 5975 txp->wr_type = 1; 5976 txp->len16 = 5977 howmany(sizeof(struct fw_eth_tx_pkts_wr), 16) + 5978 txpkts1_len16(); 5979 } 5980 if (tx_len16_to_desc(txp->len16) > avail) 5981 goto cannot_coalesce; 5982 txp->npkt = 1; 5983 txp->plen = m->m_pkthdr.len; 5984 txp->mb[0] = m; 5985 } else { 5986 MPASS(tx_len16_to_desc(txp->len16) <= avail); 5987 MPASS(txp->npkt < txp->max_npkt); 5988 5989 if (m->m_pkthdr.len + txp->plen > 65535) { 5990 retry_after_send: 5991 *send = true; 5992 return (EAGAIN); 5993 } 5994 5995 MPASS(txp->wr_type == 0 || txp->wr_type == 1); 5996 if (txp->wr_type == 0) { 5997 if (tx_len16_to_desc(txp->len16 + 5998 txpkts0_len16(nsegs)) > min(avail, SGE_MAX_WR_NDESC)) 5999 goto retry_after_send; 6000 txp->len16 += txpkts0_len16(nsegs); 6001 } else { 6002 if (nsegs != 1) 6003 goto retry_after_send; 6004 if (tx_len16_to_desc(txp->len16 + txpkts1_len16()) > 6005 avail) 6006 goto retry_after_send; 6007 txp->len16 += txpkts1_len16(); 6008 } 6009 6010 txp->plen += m->m_pkthdr.len; 6011 txp->mb[txp->npkt++] = m; 6012 if (txp->npkt == txp->max_npkt) 6013 *send = true; 6014 } 6015 return (0); 6016 } 6017 6018 /* 6019 * Write a txpkts WR for the packets in txp to the hardware descriptors, update 6020 * the software descriptor, and advance the pidx. It is guaranteed that enough 6021 * descriptors are available. 6022 * 6023 * The return value is the # of hardware descriptors used. 6024 */ 6025 static u_int 6026 write_txpkts_wr(struct adapter *sc, struct sge_txq *txq) 6027 { 6028 const struct txpkts *txp = &txq->txp; 6029 struct sge_eq *eq = &txq->eq; 6030 struct fw_eth_tx_pkts_wr *wr; 6031 struct tx_sdesc *txsd; 6032 struct cpl_tx_pkt_core *cpl; 6033 uint64_t ctrl1; 6034 int ndesc, i, checkwrap; 6035 struct mbuf *m, *last; 6036 void *flitp; 6037 6038 TXQ_LOCK_ASSERT_OWNED(txq); 6039 MPASS(txp->npkt > 0); 6040 MPASS(txp->len16 <= howmany(SGE_MAX_WR_LEN, 16)); 6041 6042 wr = (void *)&eq->desc[eq->pidx]; 6043 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR)); 6044 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(txp->len16)); 6045 wr->plen = htobe16(txp->plen); 6046 wr->npkt = txp->npkt; 6047 wr->r3 = 0; 6048 wr->type = txp->wr_type; 6049 flitp = wr + 1; 6050 6051 /* 6052 * At this point we are 16B into a hardware descriptor. If checkwrap is 6053 * set then we know the WR is going to wrap around somewhere. We'll 6054 * check for that at appropriate points. 6055 */ 6056 ndesc = tx_len16_to_desc(txp->len16); 6057 last = NULL; 6058 checkwrap = eq->sidx - ndesc < eq->pidx; 6059 for (i = 0; i < txp->npkt; i++) { 6060 m = txp->mb[i]; 6061 if (txp->wr_type == 0) { 6062 struct ulp_txpkt *ulpmc; 6063 struct ulptx_idata *ulpsc; 6064 6065 /* ULP master command */ 6066 ulpmc = flitp; 6067 ulpmc->cmd_dest = htobe32(V_ULPTX_CMD(ULP_TX_PKT) | 6068 V_ULP_TXPKT_DEST(0) | V_ULP_TXPKT_FID(eq->iqid)); 6069 ulpmc->len = htobe32(txpkts0_len16(mbuf_nsegs(m))); 6070 6071 /* ULP subcommand */ 6072 ulpsc = (void *)(ulpmc + 1); 6073 ulpsc->cmd_more = htobe32(V_ULPTX_CMD(ULP_TX_SC_IMM) | 6074 F_ULP_TX_SC_MORE); 6075 ulpsc->len = htobe32(sizeof(struct cpl_tx_pkt_core)); 6076 6077 cpl = (void *)(ulpsc + 1); 6078 if (checkwrap && 6079 (uintptr_t)cpl == (uintptr_t)&eq->desc[eq->sidx]) 6080 cpl = (void *)&eq->desc[0]; 6081 } else { 6082 cpl = flitp; 6083 } 6084 6085 /* Checksum offload */ 6086 ctrl1 = csum_to_ctrl(sc, m); 6087 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS)) { 6088 /* some hardware assistance provided */ 6089 if (needs_vxlan_csum(m)) 6090 txq->vxlan_txcsum++; 6091 else 6092 txq->txcsum++; 6093 } 6094 6095 /* VLAN tag insertion */ 6096 if (needs_vlan_insertion(m)) { 6097 ctrl1 |= F_TXPKT_VLAN_VLD | 6098 V_TXPKT_VLAN(m->m_pkthdr.ether_vtag); 6099 txq->vlan_insertion++; 6100 } 6101 6102 /* CPL header */ 6103 cpl->ctrl0 = txq->cpl_ctrl0; 6104 cpl->pack = 0; 6105 cpl->len = htobe16(m->m_pkthdr.len); 6106 cpl->ctrl1 = htobe64(ctrl1); 6107 6108 flitp = cpl + 1; 6109 if (checkwrap && 6110 (uintptr_t)flitp == (uintptr_t)&eq->desc[eq->sidx]) 6111 flitp = (void *)&eq->desc[0]; 6112 6113 write_gl_to_txd(txq, m, (caddr_t *)(&flitp), checkwrap); 6114 6115 if (last != NULL) 6116 last->m_nextpkt = m; 6117 last = m; 6118 } 6119 6120 txq->sgl_wrs++; 6121 if (txp->wr_type == 0) { 6122 txq->txpkts0_pkts += txp->npkt; 6123 txq->txpkts0_wrs++; 6124 } else { 6125 txq->txpkts1_pkts += txp->npkt; 6126 txq->txpkts1_wrs++; 6127 } 6128 6129 txsd = &txq->sdesc[eq->pidx]; 6130 txsd->m = txp->mb[0]; 6131 txsd->desc_used = ndesc; 6132 6133 return (ndesc); 6134 } 6135 6136 static u_int 6137 write_txpkts_vm_wr(struct adapter *sc, struct sge_txq *txq) 6138 { 6139 const struct txpkts *txp = &txq->txp; 6140 struct sge_eq *eq = &txq->eq; 6141 struct fw_eth_tx_pkts_vm_wr *wr; 6142 struct tx_sdesc *txsd; 6143 struct cpl_tx_pkt_core *cpl; 6144 uint64_t ctrl1; 6145 int ndesc, i; 6146 struct mbuf *m, *last; 6147 void *flitp; 6148 6149 TXQ_LOCK_ASSERT_OWNED(txq); 6150 MPASS(txp->npkt > 0); 6151 MPASS(txp->wr_type == 1); /* VF supports type 1 only */ 6152 MPASS(txp->mb[0] != NULL); 6153 MPASS(txp->len16 <= howmany(SGE_MAX_WR_LEN, 16)); 6154 6155 wr = (void *)&eq->desc[eq->pidx]; 6156 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_VM_WR)); 6157 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(txp->len16)); 6158 wr->r3 = 0; 6159 wr->plen = htobe16(txp->plen); 6160 wr->npkt = txp->npkt; 6161 wr->r4 = 0; 6162 memcpy(&wr->ethmacdst[0], &txp->ethmacdst[0], 16); 6163 flitp = wr + 1; 6164 6165 /* 6166 * At this point we are 32B into a hardware descriptor. Each mbuf in 6167 * the WR will take 32B so we check for the end of the descriptor ring 6168 * before writing odd mbufs (mb[1], 3, 5, ..) 6169 */ 6170 ndesc = tx_len16_to_desc(txp->len16); 6171 last = NULL; 6172 for (i = 0; i < txp->npkt; i++) { 6173 m = txp->mb[i]; 6174 if (i & 1 && (uintptr_t)flitp == (uintptr_t)&eq->desc[eq->sidx]) 6175 flitp = &eq->desc[0]; 6176 cpl = flitp; 6177 6178 /* Checksum offload */ 6179 ctrl1 = csum_to_ctrl(sc, m); 6180 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS)) 6181 txq->txcsum++; /* some hardware assistance provided */ 6182 6183 /* VLAN tag insertion */ 6184 if (needs_vlan_insertion(m)) { 6185 ctrl1 |= F_TXPKT_VLAN_VLD | 6186 V_TXPKT_VLAN(m->m_pkthdr.ether_vtag); 6187 txq->vlan_insertion++; 6188 } else if (sc->vlan_id) 6189 ctrl1 |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(sc->vlan_id); 6190 6191 /* CPL header */ 6192 cpl->ctrl0 = txq->cpl_ctrl0; 6193 cpl->pack = 0; 6194 cpl->len = htobe16(m->m_pkthdr.len); 6195 cpl->ctrl1 = htobe64(ctrl1); 6196 6197 flitp = cpl + 1; 6198 MPASS(mbuf_nsegs(m) == 1); 6199 write_gl_to_txd(txq, m, (caddr_t *)(&flitp), 0); 6200 6201 if (last != NULL) 6202 last->m_nextpkt = m; 6203 last = m; 6204 } 6205 6206 txq->sgl_wrs++; 6207 txq->txpkts1_pkts += txp->npkt; 6208 txq->txpkts1_wrs++; 6209 6210 txsd = &txq->sdesc[eq->pidx]; 6211 txsd->m = txp->mb[0]; 6212 txsd->desc_used = ndesc; 6213 6214 return (ndesc); 6215 } 6216 6217 /* 6218 * If the SGL ends on an address that is not 16 byte aligned, this function will 6219 * add a 0 filled flit at the end. 6220 */ 6221 static void 6222 write_gl_to_txd(struct sge_txq *txq, struct mbuf *m, caddr_t *to, int checkwrap) 6223 { 6224 struct sge_eq *eq = &txq->eq; 6225 struct sglist *gl = txq->gl; 6226 struct sglist_seg *seg; 6227 __be64 *flitp, *wrap; 6228 struct ulptx_sgl *usgl; 6229 int i, nflits, nsegs; 6230 6231 KASSERT(((uintptr_t)(*to) & 0xf) == 0, 6232 ("%s: SGL must start at a 16 byte boundary: %p", __func__, *to)); 6233 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]); 6234 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]); 6235 6236 get_pkt_gl(m, gl); 6237 nsegs = gl->sg_nseg; 6238 MPASS(nsegs > 0); 6239 6240 nflits = (3 * (nsegs - 1)) / 2 + ((nsegs - 1) & 1) + 2; 6241 flitp = (__be64 *)(*to); 6242 wrap = (__be64 *)(&eq->desc[eq->sidx]); 6243 seg = &gl->sg_segs[0]; 6244 usgl = (void *)flitp; 6245 6246 /* 6247 * We start at a 16 byte boundary somewhere inside the tx descriptor 6248 * ring, so we're at least 16 bytes away from the status page. There is 6249 * no chance of a wrap around in the middle of usgl (which is 16 bytes). 6250 */ 6251 6252 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 6253 V_ULPTX_NSGE(nsegs)); 6254 usgl->len0 = htobe32(seg->ss_len); 6255 usgl->addr0 = htobe64(seg->ss_paddr); 6256 seg++; 6257 6258 if (checkwrap == 0 || (uintptr_t)(flitp + nflits) <= (uintptr_t)wrap) { 6259 6260 /* Won't wrap around at all */ 6261 6262 for (i = 0; i < nsegs - 1; i++, seg++) { 6263 usgl->sge[i / 2].len[i & 1] = htobe32(seg->ss_len); 6264 usgl->sge[i / 2].addr[i & 1] = htobe64(seg->ss_paddr); 6265 } 6266 if (i & 1) 6267 usgl->sge[i / 2].len[1] = htobe32(0); 6268 flitp += nflits; 6269 } else { 6270 6271 /* Will wrap somewhere in the rest of the SGL */ 6272 6273 /* 2 flits already written, write the rest flit by flit */ 6274 flitp = (void *)(usgl + 1); 6275 for (i = 0; i < nflits - 2; i++) { 6276 if (flitp == wrap) 6277 flitp = (void *)eq->desc; 6278 *flitp++ = get_flit(seg, nsegs - 1, i); 6279 } 6280 } 6281 6282 if (nflits & 1) { 6283 MPASS(((uintptr_t)flitp) & 0xf); 6284 *flitp++ = 0; 6285 } 6286 6287 MPASS((((uintptr_t)flitp) & 0xf) == 0); 6288 if (__predict_false(flitp == wrap)) 6289 *to = (void *)eq->desc; 6290 else 6291 *to = (void *)flitp; 6292 } 6293 6294 static inline void 6295 copy_to_txd(struct sge_eq *eq, caddr_t from, caddr_t *to, int len) 6296 { 6297 6298 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]); 6299 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]); 6300 6301 if (__predict_true((uintptr_t)(*to) + len <= 6302 (uintptr_t)&eq->desc[eq->sidx])) { 6303 bcopy(from, *to, len); 6304 (*to) += len; 6305 } else { 6306 int portion = (uintptr_t)&eq->desc[eq->sidx] - (uintptr_t)(*to); 6307 6308 bcopy(from, *to, portion); 6309 from += portion; 6310 portion = len - portion; /* remaining */ 6311 bcopy(from, (void *)eq->desc, portion); 6312 (*to) = (caddr_t)eq->desc + portion; 6313 } 6314 } 6315 6316 static inline void 6317 ring_eq_db(struct adapter *sc, struct sge_eq *eq, u_int n) 6318 { 6319 u_int db; 6320 6321 MPASS(n > 0); 6322 6323 db = eq->doorbells; 6324 if (n > 1) 6325 clrbit(&db, DOORBELL_WCWR); 6326 wmb(); 6327 6328 switch (ffs(db) - 1) { 6329 case DOORBELL_UDB: 6330 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n)); 6331 break; 6332 6333 case DOORBELL_WCWR: { 6334 volatile uint64_t *dst, *src; 6335 int i; 6336 6337 /* 6338 * Queues whose 128B doorbell segment fits in the page do not 6339 * use relative qid (udb_qid is always 0). Only queues with 6340 * doorbell segments can do WCWR. 6341 */ 6342 KASSERT(eq->udb_qid == 0 && n == 1, 6343 ("%s: inappropriate doorbell (0x%x, %d, %d) for eq %p", 6344 __func__, eq->doorbells, n, eq->dbidx, eq)); 6345 6346 dst = (volatile void *)((uintptr_t)eq->udb + UDBS_WR_OFFSET - 6347 UDBS_DB_OFFSET); 6348 i = eq->dbidx; 6349 src = (void *)&eq->desc[i]; 6350 while (src != (void *)&eq->desc[i + 1]) 6351 *dst++ = *src++; 6352 wmb(); 6353 break; 6354 } 6355 6356 case DOORBELL_UDBWC: 6357 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n)); 6358 wmb(); 6359 break; 6360 6361 case DOORBELL_KDB: 6362 t4_write_reg(sc, sc->sge_kdoorbell_reg, 6363 V_QID(eq->cntxt_id) | V_PIDX(n)); 6364 break; 6365 } 6366 6367 IDXINCR(eq->dbidx, n, eq->sidx); 6368 } 6369 6370 static inline u_int 6371 reclaimable_tx_desc(struct sge_eq *eq) 6372 { 6373 uint16_t hw_cidx; 6374 6375 hw_cidx = read_hw_cidx(eq); 6376 return (IDXDIFF(hw_cidx, eq->cidx, eq->sidx)); 6377 } 6378 6379 static inline u_int 6380 total_available_tx_desc(struct sge_eq *eq) 6381 { 6382 uint16_t hw_cidx, pidx; 6383 6384 hw_cidx = read_hw_cidx(eq); 6385 pidx = eq->pidx; 6386 6387 if (pidx == hw_cidx) 6388 return (eq->sidx - 1); 6389 else 6390 return (IDXDIFF(hw_cidx, pidx, eq->sidx) - 1); 6391 } 6392 6393 static inline uint16_t 6394 read_hw_cidx(struct sge_eq *eq) 6395 { 6396 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx]; 6397 uint16_t cidx = spg->cidx; /* stable snapshot */ 6398 6399 return (be16toh(cidx)); 6400 } 6401 6402 /* 6403 * Reclaim 'n' descriptors approximately. 6404 */ 6405 static u_int 6406 reclaim_tx_descs(struct sge_txq *txq, u_int n) 6407 { 6408 struct tx_sdesc *txsd; 6409 struct sge_eq *eq = &txq->eq; 6410 u_int can_reclaim, reclaimed; 6411 6412 TXQ_LOCK_ASSERT_OWNED(txq); 6413 MPASS(n > 0); 6414 6415 reclaimed = 0; 6416 can_reclaim = reclaimable_tx_desc(eq); 6417 while (can_reclaim && reclaimed < n) { 6418 int ndesc; 6419 struct mbuf *m, *nextpkt; 6420 6421 txsd = &txq->sdesc[eq->cidx]; 6422 ndesc = txsd->desc_used; 6423 6424 /* Firmware doesn't return "partial" credits. */ 6425 KASSERT(can_reclaim >= ndesc, 6426 ("%s: unexpected number of credits: %d, %d", 6427 __func__, can_reclaim, ndesc)); 6428 KASSERT(ndesc != 0, 6429 ("%s: descriptor with no credits: cidx %d", 6430 __func__, eq->cidx)); 6431 6432 for (m = txsd->m; m != NULL; m = nextpkt) { 6433 nextpkt = m->m_nextpkt; 6434 m->m_nextpkt = NULL; 6435 m_freem(m); 6436 } 6437 reclaimed += ndesc; 6438 can_reclaim -= ndesc; 6439 IDXINCR(eq->cidx, ndesc, eq->sidx); 6440 } 6441 6442 return (reclaimed); 6443 } 6444 6445 static void 6446 tx_reclaim(void *arg, int n) 6447 { 6448 struct sge_txq *txq = arg; 6449 struct sge_eq *eq = &txq->eq; 6450 6451 do { 6452 if (TXQ_TRYLOCK(txq) == 0) 6453 break; 6454 n = reclaim_tx_descs(txq, 32); 6455 if (eq->cidx == eq->pidx) 6456 eq->equeqidx = eq->pidx; 6457 TXQ_UNLOCK(txq); 6458 } while (n > 0); 6459 } 6460 6461 static __be64 6462 get_flit(struct sglist_seg *segs, int nsegs, int idx) 6463 { 6464 int i = (idx / 3) * 2; 6465 6466 switch (idx % 3) { 6467 case 0: { 6468 uint64_t rc; 6469 6470 rc = (uint64_t)segs[i].ss_len << 32; 6471 if (i + 1 < nsegs) 6472 rc |= (uint64_t)(segs[i + 1].ss_len); 6473 6474 return (htobe64(rc)); 6475 } 6476 case 1: 6477 return (htobe64(segs[i].ss_paddr)); 6478 case 2: 6479 return (htobe64(segs[i + 1].ss_paddr)); 6480 } 6481 6482 return (0); 6483 } 6484 6485 static int 6486 find_refill_source(struct adapter *sc, int maxp, bool packing) 6487 { 6488 int i, zidx = -1; 6489 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[0]; 6490 6491 if (packing) { 6492 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) { 6493 if (rxb->hwidx2 == -1) 6494 continue; 6495 if (rxb->size1 < PAGE_SIZE && 6496 rxb->size1 < largest_rx_cluster) 6497 continue; 6498 if (rxb->size1 > largest_rx_cluster) 6499 break; 6500 MPASS(rxb->size1 - rxb->size2 >= CL_METADATA_SIZE); 6501 if (rxb->size2 >= maxp) 6502 return (i); 6503 zidx = i; 6504 } 6505 } else { 6506 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) { 6507 if (rxb->hwidx1 == -1) 6508 continue; 6509 if (rxb->size1 > largest_rx_cluster) 6510 break; 6511 if (rxb->size1 >= maxp) 6512 return (i); 6513 zidx = i; 6514 } 6515 } 6516 6517 return (zidx); 6518 } 6519 6520 static void 6521 add_fl_to_sfl(struct adapter *sc, struct sge_fl *fl) 6522 { 6523 mtx_lock(&sc->sfl_lock); 6524 FL_LOCK(fl); 6525 if ((fl->flags & FL_DOOMED) == 0) { 6526 fl->flags |= FL_STARVING; 6527 TAILQ_INSERT_TAIL(&sc->sfl, fl, link); 6528 callout_reset(&sc->sfl_callout, hz / 5, refill_sfl, sc); 6529 } 6530 FL_UNLOCK(fl); 6531 mtx_unlock(&sc->sfl_lock); 6532 } 6533 6534 static void 6535 handle_wrq_egr_update(struct adapter *sc, struct sge_eq *eq) 6536 { 6537 struct sge_wrq *wrq = (void *)eq; 6538 6539 atomic_readandclear_int(&eq->equiq); 6540 taskqueue_enqueue(sc->tq[eq->port_id], &wrq->wrq_tx_task); 6541 } 6542 6543 static void 6544 handle_eth_egr_update(struct adapter *sc, struct sge_eq *eq) 6545 { 6546 struct sge_txq *txq = (void *)eq; 6547 6548 MPASS(eq->type == EQ_ETH); 6549 6550 atomic_readandclear_int(&eq->equiq); 6551 if (mp_ring_is_idle(txq->r)) 6552 taskqueue_enqueue(sc->tq[eq->port_id], &txq->tx_reclaim_task); 6553 else 6554 mp_ring_check_drainage(txq->r, 64); 6555 } 6556 6557 static int 6558 handle_sge_egr_update(struct sge_iq *iq, const struct rss_header *rss, 6559 struct mbuf *m) 6560 { 6561 const struct cpl_sge_egr_update *cpl = (const void *)(rss + 1); 6562 unsigned int qid = G_EGR_QID(ntohl(cpl->opcode_qid)); 6563 struct adapter *sc = iq->adapter; 6564 struct sge *s = &sc->sge; 6565 struct sge_eq *eq; 6566 static void (*h[])(struct adapter *, struct sge_eq *) = {NULL, 6567 &handle_wrq_egr_update, &handle_eth_egr_update, 6568 &handle_wrq_egr_update}; 6569 6570 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 6571 rss->opcode)); 6572 6573 eq = s->eqmap[qid - s->eq_start - s->eq_base]; 6574 (*h[eq->type])(sc, eq); 6575 6576 return (0); 6577 } 6578 6579 /* handle_fw_msg works for both fw4_msg and fw6_msg because this is valid */ 6580 CTASSERT(offsetof(struct cpl_fw4_msg, data) == \ 6581 offsetof(struct cpl_fw6_msg, data)); 6582 6583 static int 6584 handle_fw_msg(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 6585 { 6586 struct adapter *sc = iq->adapter; 6587 const struct cpl_fw6_msg *cpl = (const void *)(rss + 1); 6588 6589 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 6590 rss->opcode)); 6591 6592 if (cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL) { 6593 const struct rss_header *rss2; 6594 6595 rss2 = (const struct rss_header *)&cpl->data[0]; 6596 return (t4_cpl_handler[rss2->opcode](iq, rss2, m)); 6597 } 6598 6599 return (t4_fw_msg_handler[cpl->type](sc, &cpl->data[0])); 6600 } 6601 6602 /** 6603 * t4_handle_wrerr_rpl - process a FW work request error message 6604 * @adap: the adapter 6605 * @rpl: start of the FW message 6606 */ 6607 static int 6608 t4_handle_wrerr_rpl(struct adapter *adap, const __be64 *rpl) 6609 { 6610 u8 opcode = *(const u8 *)rpl; 6611 const struct fw_error_cmd *e = (const void *)rpl; 6612 unsigned int i; 6613 6614 if (opcode != FW_ERROR_CMD) { 6615 log(LOG_ERR, 6616 "%s: Received WRERR_RPL message with opcode %#x\n", 6617 device_get_nameunit(adap->dev), opcode); 6618 return (EINVAL); 6619 } 6620 log(LOG_ERR, "%s: FW_ERROR (%s) ", device_get_nameunit(adap->dev), 6621 G_FW_ERROR_CMD_FATAL(be32toh(e->op_to_type)) ? "fatal" : 6622 "non-fatal"); 6623 switch (G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type))) { 6624 case FW_ERROR_TYPE_EXCEPTION: 6625 log(LOG_ERR, "exception info:\n"); 6626 for (i = 0; i < nitems(e->u.exception.info); i++) 6627 log(LOG_ERR, "%s%08x", i == 0 ? "\t" : " ", 6628 be32toh(e->u.exception.info[i])); 6629 log(LOG_ERR, "\n"); 6630 break; 6631 case FW_ERROR_TYPE_HWMODULE: 6632 log(LOG_ERR, "HW module regaddr %08x regval %08x\n", 6633 be32toh(e->u.hwmodule.regaddr), 6634 be32toh(e->u.hwmodule.regval)); 6635 break; 6636 case FW_ERROR_TYPE_WR: 6637 log(LOG_ERR, "WR cidx %d PF %d VF %d eqid %d hdr:\n", 6638 be16toh(e->u.wr.cidx), 6639 G_FW_ERROR_CMD_PFN(be16toh(e->u.wr.pfn_vfn)), 6640 G_FW_ERROR_CMD_VFN(be16toh(e->u.wr.pfn_vfn)), 6641 be32toh(e->u.wr.eqid)); 6642 for (i = 0; i < nitems(e->u.wr.wrhdr); i++) 6643 log(LOG_ERR, "%s%02x", i == 0 ? "\t" : " ", 6644 e->u.wr.wrhdr[i]); 6645 log(LOG_ERR, "\n"); 6646 break; 6647 case FW_ERROR_TYPE_ACL: 6648 log(LOG_ERR, "ACL cidx %d PF %d VF %d eqid %d %s", 6649 be16toh(e->u.acl.cidx), 6650 G_FW_ERROR_CMD_PFN(be16toh(e->u.acl.pfn_vfn)), 6651 G_FW_ERROR_CMD_VFN(be16toh(e->u.acl.pfn_vfn)), 6652 be32toh(e->u.acl.eqid), 6653 G_FW_ERROR_CMD_MV(be16toh(e->u.acl.mv_pkd)) ? "vlanid" : 6654 "MAC"); 6655 for (i = 0; i < nitems(e->u.acl.val); i++) 6656 log(LOG_ERR, " %02x", e->u.acl.val[i]); 6657 log(LOG_ERR, "\n"); 6658 break; 6659 default: 6660 log(LOG_ERR, "type %#x\n", 6661 G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type))); 6662 return (EINVAL); 6663 } 6664 return (0); 6665 } 6666 6667 static inline bool 6668 bufidx_used(struct adapter *sc, int idx) 6669 { 6670 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[0]; 6671 int i; 6672 6673 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) { 6674 if (rxb->size1 > largest_rx_cluster) 6675 continue; 6676 if (rxb->hwidx1 == idx || rxb->hwidx2 == idx) 6677 return (true); 6678 } 6679 6680 return (false); 6681 } 6682 6683 static int 6684 sysctl_bufsizes(SYSCTL_HANDLER_ARGS) 6685 { 6686 struct adapter *sc = arg1; 6687 struct sge_params *sp = &sc->params.sge; 6688 int i, rc; 6689 struct sbuf sb; 6690 char c; 6691 6692 sbuf_new(&sb, NULL, 128, SBUF_AUTOEXTEND); 6693 for (i = 0; i < SGE_FLBUF_SIZES; i++) { 6694 if (bufidx_used(sc, i)) 6695 c = '*'; 6696 else 6697 c = '\0'; 6698 6699 sbuf_printf(&sb, "%u%c ", sp->sge_fl_buffer_size[i], c); 6700 } 6701 sbuf_trim(&sb); 6702 sbuf_finish(&sb); 6703 rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req); 6704 sbuf_delete(&sb); 6705 return (rc); 6706 } 6707 6708 #ifdef RATELIMIT 6709 #if defined(INET) || defined(INET6) 6710 /* 6711 * len16 for a txpkt WR with a GL. Includes the firmware work request header. 6712 */ 6713 static inline u_int 6714 txpkt_eo_len16(u_int nsegs, u_int immhdrs, u_int tso) 6715 { 6716 u_int n; 6717 6718 MPASS(immhdrs > 0); 6719 6720 n = roundup2(sizeof(struct fw_eth_tx_eo_wr) + 6721 sizeof(struct cpl_tx_pkt_core) + immhdrs, 16); 6722 if (__predict_false(nsegs == 0)) 6723 goto done; 6724 6725 nsegs--; /* first segment is part of ulptx_sgl */ 6726 n += sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 6727 if (tso) 6728 n += sizeof(struct cpl_tx_pkt_lso_core); 6729 6730 done: 6731 return (howmany(n, 16)); 6732 } 6733 #endif 6734 6735 #define ETID_FLOWC_NPARAMS 6 6736 #define ETID_FLOWC_LEN (roundup2((sizeof(struct fw_flowc_wr) + \ 6737 ETID_FLOWC_NPARAMS * sizeof(struct fw_flowc_mnemval)), 16)) 6738 #define ETID_FLOWC_LEN16 (howmany(ETID_FLOWC_LEN, 16)) 6739 6740 #if defined(INET) || defined(INET6) 6741 static int 6742 send_etid_flowc_wr(struct cxgbe_rate_tag *cst, struct port_info *pi, 6743 struct vi_info *vi) 6744 { 6745 struct wrq_cookie cookie; 6746 u_int pfvf = pi->adapter->pf << S_FW_VIID_PFN; 6747 struct fw_flowc_wr *flowc; 6748 6749 mtx_assert(&cst->lock, MA_OWNED); 6750 MPASS((cst->flags & (EO_FLOWC_PENDING | EO_FLOWC_RPL_PENDING)) == 6751 EO_FLOWC_PENDING); 6752 6753 flowc = start_wrq_wr(&cst->eo_txq->wrq, ETID_FLOWC_LEN16, &cookie); 6754 if (__predict_false(flowc == NULL)) 6755 return (ENOMEM); 6756 6757 bzero(flowc, ETID_FLOWC_LEN); 6758 flowc->op_to_nparams = htobe32(V_FW_WR_OP(FW_FLOWC_WR) | 6759 V_FW_FLOWC_WR_NPARAMS(ETID_FLOWC_NPARAMS) | V_FW_WR_COMPL(0)); 6760 flowc->flowid_len16 = htonl(V_FW_WR_LEN16(ETID_FLOWC_LEN16) | 6761 V_FW_WR_FLOWID(cst->etid)); 6762 flowc->mnemval[0].mnemonic = FW_FLOWC_MNEM_PFNVFN; 6763 flowc->mnemval[0].val = htobe32(pfvf); 6764 /* Firmware expects hw port and will translate to channel itself. */ 6765 flowc->mnemval[1].mnemonic = FW_FLOWC_MNEM_CH; 6766 flowc->mnemval[1].val = htobe32(pi->hw_port); 6767 flowc->mnemval[2].mnemonic = FW_FLOWC_MNEM_PORT; 6768 flowc->mnemval[2].val = htobe32(pi->hw_port); 6769 flowc->mnemval[3].mnemonic = FW_FLOWC_MNEM_IQID; 6770 flowc->mnemval[3].val = htobe32(cst->iqid); 6771 flowc->mnemval[4].mnemonic = FW_FLOWC_MNEM_EOSTATE; 6772 flowc->mnemval[4].val = htobe32(FW_FLOWC_MNEM_EOSTATE_ESTABLISHED); 6773 flowc->mnemval[5].mnemonic = FW_FLOWC_MNEM_SCHEDCLASS; 6774 flowc->mnemval[5].val = htobe32(cst->schedcl); 6775 6776 commit_wrq_wr(&cst->eo_txq->wrq, flowc, &cookie); 6777 6778 cst->flags &= ~EO_FLOWC_PENDING; 6779 cst->flags |= EO_FLOWC_RPL_PENDING; 6780 MPASS(cst->tx_credits >= ETID_FLOWC_LEN16); /* flowc is first WR. */ 6781 cst->tx_credits -= ETID_FLOWC_LEN16; 6782 6783 return (0); 6784 } 6785 #endif 6786 6787 #define ETID_FLUSH_LEN16 (howmany(sizeof (struct fw_flowc_wr), 16)) 6788 6789 void 6790 send_etid_flush_wr(struct cxgbe_rate_tag *cst) 6791 { 6792 struct fw_flowc_wr *flowc; 6793 struct wrq_cookie cookie; 6794 6795 mtx_assert(&cst->lock, MA_OWNED); 6796 6797 flowc = start_wrq_wr(&cst->eo_txq->wrq, ETID_FLUSH_LEN16, &cookie); 6798 if (__predict_false(flowc == NULL)) 6799 CXGBE_UNIMPLEMENTED(__func__); 6800 6801 bzero(flowc, ETID_FLUSH_LEN16 * 16); 6802 flowc->op_to_nparams = htobe32(V_FW_WR_OP(FW_FLOWC_WR) | 6803 V_FW_FLOWC_WR_NPARAMS(0) | F_FW_WR_COMPL); 6804 flowc->flowid_len16 = htobe32(V_FW_WR_LEN16(ETID_FLUSH_LEN16) | 6805 V_FW_WR_FLOWID(cst->etid)); 6806 6807 commit_wrq_wr(&cst->eo_txq->wrq, flowc, &cookie); 6808 6809 cst->flags |= EO_FLUSH_RPL_PENDING; 6810 MPASS(cst->tx_credits >= ETID_FLUSH_LEN16); 6811 cst->tx_credits -= ETID_FLUSH_LEN16; 6812 cst->ncompl++; 6813 } 6814 6815 static void 6816 write_ethofld_wr(struct cxgbe_rate_tag *cst, struct fw_eth_tx_eo_wr *wr, 6817 struct mbuf *m0, int compl) 6818 { 6819 struct cpl_tx_pkt_core *cpl; 6820 uint64_t ctrl1; 6821 uint32_t ctrl; /* used in many unrelated places */ 6822 int len16, pktlen, nsegs, immhdrs; 6823 uintptr_t p; 6824 struct ulptx_sgl *usgl; 6825 struct sglist sg; 6826 struct sglist_seg segs[38]; /* XXX: find real limit. XXX: get off the stack */ 6827 6828 mtx_assert(&cst->lock, MA_OWNED); 6829 M_ASSERTPKTHDR(m0); 6830 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 6831 m0->m_pkthdr.l4hlen > 0, 6832 ("%s: ethofld mbuf %p is missing header lengths", __func__, m0)); 6833 6834 len16 = mbuf_eo_len16(m0); 6835 nsegs = mbuf_eo_nsegs(m0); 6836 pktlen = m0->m_pkthdr.len; 6837 ctrl = sizeof(struct cpl_tx_pkt_core); 6838 if (needs_tso(m0)) 6839 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 6840 immhdrs = m0->m_pkthdr.l2hlen + m0->m_pkthdr.l3hlen + m0->m_pkthdr.l4hlen; 6841 ctrl += immhdrs; 6842 6843 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_EO_WR) | 6844 V_FW_ETH_TX_EO_WR_IMMDLEN(ctrl) | V_FW_WR_COMPL(!!compl)); 6845 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(len16) | 6846 V_FW_WR_FLOWID(cst->etid)); 6847 wr->r3 = 0; 6848 if (needs_outer_udp_csum(m0)) { 6849 wr->u.udpseg.type = FW_ETH_TX_EO_TYPE_UDPSEG; 6850 wr->u.udpseg.ethlen = m0->m_pkthdr.l2hlen; 6851 wr->u.udpseg.iplen = htobe16(m0->m_pkthdr.l3hlen); 6852 wr->u.udpseg.udplen = m0->m_pkthdr.l4hlen; 6853 wr->u.udpseg.rtplen = 0; 6854 wr->u.udpseg.r4 = 0; 6855 wr->u.udpseg.mss = htobe16(pktlen - immhdrs); 6856 wr->u.udpseg.schedpktsize = wr->u.udpseg.mss; 6857 wr->u.udpseg.plen = htobe32(pktlen - immhdrs); 6858 cpl = (void *)(wr + 1); 6859 } else { 6860 MPASS(needs_outer_tcp_csum(m0)); 6861 wr->u.tcpseg.type = FW_ETH_TX_EO_TYPE_TCPSEG; 6862 wr->u.tcpseg.ethlen = m0->m_pkthdr.l2hlen; 6863 wr->u.tcpseg.iplen = htobe16(m0->m_pkthdr.l3hlen); 6864 wr->u.tcpseg.tcplen = m0->m_pkthdr.l4hlen; 6865 wr->u.tcpseg.tsclk_tsoff = mbuf_eo_tsclk_tsoff(m0); 6866 wr->u.tcpseg.r4 = 0; 6867 wr->u.tcpseg.r5 = 0; 6868 wr->u.tcpseg.plen = htobe32(pktlen - immhdrs); 6869 6870 if (needs_tso(m0)) { 6871 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1); 6872 6873 wr->u.tcpseg.mss = htobe16(m0->m_pkthdr.tso_segsz); 6874 6875 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | 6876 F_LSO_FIRST_SLICE | F_LSO_LAST_SLICE | 6877 V_LSO_ETHHDR_LEN((m0->m_pkthdr.l2hlen - 6878 ETHER_HDR_LEN) >> 2) | 6879 V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) | 6880 V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2); 6881 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 6882 ctrl |= F_LSO_IPV6; 6883 lso->lso_ctrl = htobe32(ctrl); 6884 lso->ipid_ofst = htobe16(0); 6885 lso->mss = htobe16(m0->m_pkthdr.tso_segsz); 6886 lso->seqno_offset = htobe32(0); 6887 lso->len = htobe32(pktlen); 6888 6889 cpl = (void *)(lso + 1); 6890 } else { 6891 wr->u.tcpseg.mss = htobe16(0xffff); 6892 cpl = (void *)(wr + 1); 6893 } 6894 } 6895 6896 /* Checksum offload must be requested for ethofld. */ 6897 MPASS(needs_outer_l4_csum(m0)); 6898 ctrl1 = csum_to_ctrl(cst->adapter, m0); 6899 6900 /* VLAN tag insertion */ 6901 if (needs_vlan_insertion(m0)) { 6902 ctrl1 |= F_TXPKT_VLAN_VLD | 6903 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 6904 } 6905 6906 /* CPL header */ 6907 cpl->ctrl0 = cst->ctrl0; 6908 cpl->pack = 0; 6909 cpl->len = htobe16(pktlen); 6910 cpl->ctrl1 = htobe64(ctrl1); 6911 6912 /* Copy Ethernet, IP & TCP/UDP hdrs as immediate data */ 6913 p = (uintptr_t)(cpl + 1); 6914 m_copydata(m0, 0, immhdrs, (void *)p); 6915 6916 /* SGL */ 6917 if (nsegs > 0) { 6918 int i, pad; 6919 6920 /* zero-pad upto next 16Byte boundary, if not 16Byte aligned */ 6921 p += immhdrs; 6922 pad = 16 - (immhdrs & 0xf); 6923 bzero((void *)p, pad); 6924 6925 usgl = (void *)(p + pad); 6926 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 6927 V_ULPTX_NSGE(nsegs)); 6928 6929 sglist_init(&sg, nitems(segs), segs); 6930 for (; m0 != NULL; m0 = m0->m_next) { 6931 if (__predict_false(m0->m_len == 0)) 6932 continue; 6933 if (immhdrs >= m0->m_len) { 6934 immhdrs -= m0->m_len; 6935 continue; 6936 } 6937 if (m0->m_flags & M_EXTPG) 6938 sglist_append_mbuf_epg(&sg, m0, 6939 mtod(m0, vm_offset_t), m0->m_len); 6940 else 6941 sglist_append(&sg, mtod(m0, char *) + immhdrs, 6942 m0->m_len - immhdrs); 6943 immhdrs = 0; 6944 } 6945 MPASS(sg.sg_nseg == nsegs); 6946 6947 /* 6948 * Zero pad last 8B in case the WR doesn't end on a 16B 6949 * boundary. 6950 */ 6951 *(uint64_t *)((char *)wr + len16 * 16 - 8) = 0; 6952 6953 usgl->len0 = htobe32(segs[0].ss_len); 6954 usgl->addr0 = htobe64(segs[0].ss_paddr); 6955 for (i = 0; i < nsegs - 1; i++) { 6956 usgl->sge[i / 2].len[i & 1] = htobe32(segs[i + 1].ss_len); 6957 usgl->sge[i / 2].addr[i & 1] = htobe64(segs[i + 1].ss_paddr); 6958 } 6959 if (i & 1) 6960 usgl->sge[i / 2].len[1] = htobe32(0); 6961 } 6962 6963 } 6964 6965 static void 6966 ethofld_tx(struct cxgbe_rate_tag *cst) 6967 { 6968 struct mbuf *m; 6969 struct wrq_cookie cookie; 6970 int next_credits, compl; 6971 struct fw_eth_tx_eo_wr *wr; 6972 6973 mtx_assert(&cst->lock, MA_OWNED); 6974 6975 while ((m = mbufq_first(&cst->pending_tx)) != NULL) { 6976 M_ASSERTPKTHDR(m); 6977 6978 /* How many len16 credits do we need to send this mbuf. */ 6979 next_credits = mbuf_eo_len16(m); 6980 MPASS(next_credits > 0); 6981 if (next_credits > cst->tx_credits) { 6982 /* 6983 * Tx will make progress eventually because there is at 6984 * least one outstanding fw4_ack that will return 6985 * credits and kick the tx. 6986 */ 6987 MPASS(cst->ncompl > 0); 6988 return; 6989 } 6990 wr = start_wrq_wr(&cst->eo_txq->wrq, next_credits, &cookie); 6991 if (__predict_false(wr == NULL)) { 6992 /* XXX: wishful thinking, not a real assertion. */ 6993 MPASS(cst->ncompl > 0); 6994 return; 6995 } 6996 cst->tx_credits -= next_credits; 6997 cst->tx_nocompl += next_credits; 6998 compl = cst->ncompl == 0 || cst->tx_nocompl >= cst->tx_total / 2; 6999 ETHER_BPF_MTAP(cst->com.ifp, m); 7000 write_ethofld_wr(cst, wr, m, compl); 7001 commit_wrq_wr(&cst->eo_txq->wrq, wr, &cookie); 7002 if (compl) { 7003 cst->ncompl++; 7004 cst->tx_nocompl = 0; 7005 } 7006 (void) mbufq_dequeue(&cst->pending_tx); 7007 7008 /* 7009 * Drop the mbuf's reference on the tag now rather 7010 * than waiting until m_freem(). This ensures that 7011 * cxgbe_rate_tag_free gets called when the inp drops 7012 * its reference on the tag and there are no more 7013 * mbufs in the pending_tx queue and can flush any 7014 * pending requests. Otherwise if the last mbuf 7015 * doesn't request a completion the etid will never be 7016 * released. 7017 */ 7018 m->m_pkthdr.snd_tag = NULL; 7019 m->m_pkthdr.csum_flags &= ~CSUM_SND_TAG; 7020 m_snd_tag_rele(&cst->com); 7021 7022 mbufq_enqueue(&cst->pending_fwack, m); 7023 } 7024 } 7025 7026 #if defined(INET) || defined(INET6) 7027 static int 7028 ethofld_transmit(if_t ifp, struct mbuf *m0) 7029 { 7030 struct cxgbe_rate_tag *cst; 7031 int rc; 7032 7033 MPASS(m0->m_nextpkt == NULL); 7034 MPASS(m0->m_pkthdr.csum_flags & CSUM_SND_TAG); 7035 MPASS(m0->m_pkthdr.snd_tag != NULL); 7036 cst = mst_to_crt(m0->m_pkthdr.snd_tag); 7037 7038 mtx_lock(&cst->lock); 7039 MPASS(cst->flags & EO_SND_TAG_REF); 7040 7041 if (__predict_false(cst->flags & EO_FLOWC_PENDING)) { 7042 struct vi_info *vi = if_getsoftc(ifp); 7043 struct port_info *pi = vi->pi; 7044 struct adapter *sc = pi->adapter; 7045 const uint32_t rss_mask = vi->rss_size - 1; 7046 uint32_t rss_hash; 7047 7048 cst->eo_txq = &sc->sge.ofld_txq[vi->first_ofld_txq]; 7049 if (M_HASHTYPE_ISHASH(m0)) 7050 rss_hash = m0->m_pkthdr.flowid; 7051 else 7052 rss_hash = arc4random(); 7053 /* We assume RSS hashing */ 7054 cst->iqid = vi->rss[rss_hash & rss_mask]; 7055 cst->eo_txq += rss_hash % vi->nofldtxq; 7056 rc = send_etid_flowc_wr(cst, pi, vi); 7057 if (rc != 0) 7058 goto done; 7059 } 7060 7061 if (__predict_false(cst->plen + m0->m_pkthdr.len > eo_max_backlog)) { 7062 rc = ENOBUFS; 7063 goto done; 7064 } 7065 7066 mbufq_enqueue(&cst->pending_tx, m0); 7067 cst->plen += m0->m_pkthdr.len; 7068 7069 /* 7070 * Hold an extra reference on the tag while generating work 7071 * requests to ensure that we don't try to free the tag during 7072 * ethofld_tx() in case we are sending the final mbuf after 7073 * the inp was freed. 7074 */ 7075 m_snd_tag_ref(&cst->com); 7076 ethofld_tx(cst); 7077 mtx_unlock(&cst->lock); 7078 m_snd_tag_rele(&cst->com); 7079 return (0); 7080 7081 done: 7082 mtx_unlock(&cst->lock); 7083 return (rc); 7084 } 7085 #endif 7086 7087 static int 7088 ethofld_fw4_ack(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0) 7089 { 7090 struct adapter *sc = iq->adapter; 7091 const struct cpl_fw4_ack *cpl = (const void *)(rss + 1); 7092 struct mbuf *m; 7093 u_int etid = G_CPL_FW4_ACK_FLOWID(be32toh(OPCODE_TID(cpl))); 7094 struct cxgbe_rate_tag *cst; 7095 uint8_t credits = cpl->credits; 7096 7097 cst = lookup_etid(sc, etid); 7098 mtx_lock(&cst->lock); 7099 if (__predict_false(cst->flags & EO_FLOWC_RPL_PENDING)) { 7100 MPASS(credits >= ETID_FLOWC_LEN16); 7101 credits -= ETID_FLOWC_LEN16; 7102 cst->flags &= ~EO_FLOWC_RPL_PENDING; 7103 } 7104 7105 KASSERT(cst->ncompl > 0, 7106 ("%s: etid %u (%p) wasn't expecting completion.", 7107 __func__, etid, cst)); 7108 cst->ncompl--; 7109 7110 while (credits > 0) { 7111 m = mbufq_dequeue(&cst->pending_fwack); 7112 if (__predict_false(m == NULL)) { 7113 /* 7114 * The remaining credits are for the final flush that 7115 * was issued when the tag was freed by the kernel. 7116 */ 7117 MPASS((cst->flags & 7118 (EO_FLUSH_RPL_PENDING | EO_SND_TAG_REF)) == 7119 EO_FLUSH_RPL_PENDING); 7120 MPASS(credits == ETID_FLUSH_LEN16); 7121 MPASS(cst->tx_credits + cpl->credits == cst->tx_total); 7122 MPASS(cst->ncompl == 0); 7123 7124 cst->flags &= ~EO_FLUSH_RPL_PENDING; 7125 cst->tx_credits += cpl->credits; 7126 cxgbe_rate_tag_free_locked(cst); 7127 return (0); /* cst is gone. */ 7128 } 7129 KASSERT(m != NULL, 7130 ("%s: too many credits (%u, %u)", __func__, cpl->credits, 7131 credits)); 7132 KASSERT(credits >= mbuf_eo_len16(m), 7133 ("%s: too few credits (%u, %u, %u)", __func__, 7134 cpl->credits, credits, mbuf_eo_len16(m))); 7135 credits -= mbuf_eo_len16(m); 7136 cst->plen -= m->m_pkthdr.len; 7137 m_freem(m); 7138 } 7139 7140 cst->tx_credits += cpl->credits; 7141 MPASS(cst->tx_credits <= cst->tx_total); 7142 7143 if (cst->flags & EO_SND_TAG_REF) { 7144 /* 7145 * As with ethofld_transmit(), hold an extra reference 7146 * so that the tag is stable across ethold_tx(). 7147 */ 7148 m_snd_tag_ref(&cst->com); 7149 m = mbufq_first(&cst->pending_tx); 7150 if (m != NULL && cst->tx_credits >= mbuf_eo_len16(m)) 7151 ethofld_tx(cst); 7152 mtx_unlock(&cst->lock); 7153 m_snd_tag_rele(&cst->com); 7154 } else { 7155 /* 7156 * There shouldn't be any pending packets if the tag 7157 * was freed by the kernel since any pending packet 7158 * should hold a reference to the tag. 7159 */ 7160 MPASS(mbufq_first(&cst->pending_tx) == NULL); 7161 mtx_unlock(&cst->lock); 7162 } 7163 7164 return (0); 7165 } 7166 #endif 7167