1 /*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 34 #include <sys/types.h> 35 #include <sys/eventhandler.h> 36 #include <sys/mbuf.h> 37 #include <sys/socket.h> 38 #include <sys/kernel.h> 39 #include <sys/kdb.h> 40 #include <sys/malloc.h> 41 #include <sys/queue.h> 42 #include <sys/sbuf.h> 43 #include <sys/taskqueue.h> 44 #include <sys/time.h> 45 #include <sys/sysctl.h> 46 #include <sys/smp.h> 47 #include <net/bpf.h> 48 #include <net/ethernet.h> 49 #include <net/if.h> 50 #include <net/if_vlan_var.h> 51 #include <netinet/in.h> 52 #include <netinet/ip.h> 53 #include <netinet/ip6.h> 54 #include <netinet/tcp.h> 55 #include <machine/md_var.h> 56 #include <vm/vm.h> 57 #include <vm/pmap.h> 58 #ifdef DEV_NETMAP 59 #include <machine/bus.h> 60 #include <sys/selinfo.h> 61 #include <net/if_var.h> 62 #include <net/netmap.h> 63 #include <dev/netmap/netmap_kern.h> 64 #endif 65 66 #include "common/common.h" 67 #include "common/t4_regs.h" 68 #include "common/t4_regs_values.h" 69 #include "common/t4_msg.h" 70 71 #ifdef T4_PKT_TIMESTAMP 72 #define RX_COPY_THRESHOLD (MINCLSIZE - 8) 73 #else 74 #define RX_COPY_THRESHOLD MINCLSIZE 75 #endif 76 77 /* 78 * Ethernet frames are DMA'd at this byte offset into the freelist buffer. 79 * 0-7 are valid values. 80 */ 81 int fl_pktshift = 2; 82 TUNABLE_INT("hw.cxgbe.fl_pktshift", &fl_pktshift); 83 84 /* 85 * Pad ethernet payload up to this boundary. 86 * -1: driver should figure out a good value. 87 * 0: disable padding. 88 * Any power of 2 from 32 to 4096 (both inclusive) is also a valid value. 89 */ 90 int fl_pad = -1; 91 TUNABLE_INT("hw.cxgbe.fl_pad", &fl_pad); 92 93 /* 94 * Status page length. 95 * -1: driver should figure out a good value. 96 * 64 or 128 are the only other valid values. 97 */ 98 int spg_len = -1; 99 TUNABLE_INT("hw.cxgbe.spg_len", &spg_len); 100 101 /* 102 * Congestion drops. 103 * -1: no congestion feedback (not recommended). 104 * 0: backpressure the channel instead of dropping packets right away. 105 * 1: no backpressure, drop packets for the congested queue immediately. 106 */ 107 static int cong_drop = 0; 108 TUNABLE_INT("hw.cxgbe.cong_drop", &cong_drop); 109 110 /* 111 * Deliver multiple frames in the same free list buffer if they fit. 112 * -1: let the driver decide whether to enable buffer packing or not. 113 * 0: disable buffer packing. 114 * 1: enable buffer packing. 115 */ 116 static int buffer_packing = -1; 117 TUNABLE_INT("hw.cxgbe.buffer_packing", &buffer_packing); 118 119 /* 120 * Start next frame in a packed buffer at this boundary. 121 * -1: driver should figure out a good value. 122 * T4: 123 * --- 124 * if fl_pad != 0 125 * value specified here will be overridden by fl_pad. 126 * else 127 * power of 2 from 32 to 4096 (both inclusive) is a valid value here. 128 * T5: 129 * --- 130 * 16, or a power of 2 from 64 to 4096 (both inclusive) is a valid value. 131 */ 132 static int fl_pack = -1; 133 static int t4_fl_pack; 134 static int t5_fl_pack; 135 TUNABLE_INT("hw.cxgbe.fl_pack", &fl_pack); 136 137 /* 138 * Allow the driver to create mbuf(s) in a cluster allocated for rx. 139 * 0: never; always allocate mbufs from the zone_mbuf UMA zone. 140 * 1: ok to create mbuf(s) within a cluster if there is room. 141 */ 142 static int allow_mbufs_in_cluster = 1; 143 TUNABLE_INT("hw.cxgbe.allow_mbufs_in_cluster", &allow_mbufs_in_cluster); 144 145 /* 146 * Largest rx cluster size that the driver is allowed to allocate. 147 */ 148 static int largest_rx_cluster = MJUM16BYTES; 149 TUNABLE_INT("hw.cxgbe.largest_rx_cluster", &largest_rx_cluster); 150 151 /* 152 * Size of cluster allocation that's most likely to succeed. The driver will 153 * fall back to this size if it fails to allocate clusters larger than this. 154 */ 155 static int safest_rx_cluster = PAGE_SIZE; 156 TUNABLE_INT("hw.cxgbe.safest_rx_cluster", &safest_rx_cluster); 157 158 /* Used to track coalesced tx work request */ 159 struct txpkts { 160 uint64_t *flitp; /* ptr to flit where next pkt should start */ 161 uint8_t npkt; /* # of packets in this work request */ 162 uint8_t nflits; /* # of flits used by this work request */ 163 uint16_t plen; /* total payload (sum of all packets) */ 164 }; 165 166 /* A packet's SGL. This + m_pkthdr has all info needed for tx */ 167 struct sgl { 168 int nsegs; /* # of segments in the SGL, 0 means imm. tx */ 169 int nflits; /* # of flits needed for the SGL */ 170 bus_dma_segment_t seg[TX_SGL_SEGS]; 171 }; 172 173 static int service_iq(struct sge_iq *, int); 174 static struct mbuf *get_fl_payload(struct adapter *, struct sge_fl *, uint32_t, 175 int *); 176 static int t4_eth_rx(struct sge_iq *, const struct rss_header *, struct mbuf *); 177 static inline void init_iq(struct sge_iq *, struct adapter *, int, int, int, 178 int); 179 static inline void init_fl(struct adapter *, struct sge_fl *, int, int, int, 180 char *); 181 static inline void init_eq(struct sge_eq *, int, int, uint8_t, uint16_t, 182 char *); 183 static int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *, 184 bus_addr_t *, void **); 185 static int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 186 void *); 187 static int alloc_iq_fl(struct port_info *, struct sge_iq *, struct sge_fl *, 188 int, int); 189 static int free_iq_fl(struct port_info *, struct sge_iq *, struct sge_fl *); 190 static void add_fl_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *, 191 struct sge_fl *); 192 static int alloc_fwq(struct adapter *); 193 static int free_fwq(struct adapter *); 194 static int alloc_mgmtq(struct adapter *); 195 static int free_mgmtq(struct adapter *); 196 static int alloc_rxq(struct port_info *, struct sge_rxq *, int, int, 197 struct sysctl_oid *); 198 static int free_rxq(struct port_info *, struct sge_rxq *); 199 #ifdef TCP_OFFLOAD 200 static int alloc_ofld_rxq(struct port_info *, struct sge_ofld_rxq *, int, int, 201 struct sysctl_oid *); 202 static int free_ofld_rxq(struct port_info *, struct sge_ofld_rxq *); 203 #endif 204 #ifdef DEV_NETMAP 205 static int alloc_nm_rxq(struct port_info *, struct sge_nm_rxq *, int, int, 206 struct sysctl_oid *); 207 static int free_nm_rxq(struct port_info *, struct sge_nm_rxq *); 208 static int alloc_nm_txq(struct port_info *, struct sge_nm_txq *, int, int, 209 struct sysctl_oid *); 210 static int free_nm_txq(struct port_info *, struct sge_nm_txq *); 211 #endif 212 static int ctrl_eq_alloc(struct adapter *, struct sge_eq *); 213 static int eth_eq_alloc(struct adapter *, struct port_info *, struct sge_eq *); 214 #ifdef TCP_OFFLOAD 215 static int ofld_eq_alloc(struct adapter *, struct port_info *, struct sge_eq *); 216 #endif 217 static int alloc_eq(struct adapter *, struct port_info *, struct sge_eq *); 218 static int free_eq(struct adapter *, struct sge_eq *); 219 static int alloc_wrq(struct adapter *, struct port_info *, struct sge_wrq *, 220 struct sysctl_oid *); 221 static int free_wrq(struct adapter *, struct sge_wrq *); 222 static int alloc_txq(struct port_info *, struct sge_txq *, int, 223 struct sysctl_oid *); 224 static int free_txq(struct port_info *, struct sge_txq *); 225 static void oneseg_dma_callback(void *, bus_dma_segment_t *, int, int); 226 static inline bool is_new_response(const struct sge_iq *, struct rsp_ctrl **); 227 static inline void iq_next(struct sge_iq *); 228 static inline void ring_fl_db(struct adapter *, struct sge_fl *); 229 static int refill_fl(struct adapter *, struct sge_fl *, int); 230 static void refill_sfl(void *); 231 static int alloc_fl_sdesc(struct sge_fl *); 232 static void free_fl_sdesc(struct adapter *, struct sge_fl *); 233 static void find_best_refill_source(struct adapter *, struct sge_fl *, int); 234 static void find_safe_refill_source(struct adapter *, struct sge_fl *); 235 static void add_fl_to_sfl(struct adapter *, struct sge_fl *); 236 237 static int get_pkt_sgl(struct sge_txq *, struct mbuf **, struct sgl *, int); 238 static int free_pkt_sgl(struct sge_txq *, struct sgl *); 239 static int write_txpkt_wr(struct port_info *, struct sge_txq *, struct mbuf *, 240 struct sgl *); 241 static int add_to_txpkts(struct port_info *, struct sge_txq *, struct txpkts *, 242 struct mbuf *, struct sgl *); 243 static void write_txpkts_wr(struct sge_txq *, struct txpkts *); 244 static inline void write_ulp_cpl_sgl(struct port_info *, struct sge_txq *, 245 struct txpkts *, struct mbuf *, struct sgl *); 246 static int write_sgl_to_txd(struct sge_eq *, struct sgl *, caddr_t *); 247 static inline void copy_to_txd(struct sge_eq *, caddr_t, caddr_t *, int); 248 static inline void ring_eq_db(struct adapter *, struct sge_eq *); 249 static inline int reclaimable(struct sge_eq *); 250 static int reclaim_tx_descs(struct sge_txq *, int, int); 251 static void write_eqflush_wr(struct sge_eq *); 252 static __be64 get_flit(bus_dma_segment_t *, int, int); 253 static int handle_sge_egr_update(struct sge_iq *, const struct rss_header *, 254 struct mbuf *); 255 static int handle_fw_msg(struct sge_iq *, const struct rss_header *, 256 struct mbuf *); 257 258 static int sysctl_uint16(SYSCTL_HANDLER_ARGS); 259 static int sysctl_bufsizes(SYSCTL_HANDLER_ARGS); 260 261 /* 262 * Called on MOD_LOAD. Validates and calculates the SGE tunables. 263 */ 264 void 265 t4_sge_modload(void) 266 { 267 int pad; 268 269 /* set pad to a reasonable powerof2 between 16 and 4096 (inclusive) */ 270 #if defined(__i386__) || defined(__amd64__) 271 pad = max(cpu_clflush_line_size, 16); 272 #else 273 pad = max(CACHE_LINE_SIZE, 16); 274 #endif 275 pad = min(pad, 4096); 276 277 if (fl_pktshift < 0 || fl_pktshift > 7) { 278 printf("Invalid hw.cxgbe.fl_pktshift value (%d)," 279 " using 2 instead.\n", fl_pktshift); 280 fl_pktshift = 2; 281 } 282 283 if (fl_pad != 0 && 284 (fl_pad < 32 || fl_pad > 4096 || !powerof2(fl_pad))) { 285 286 if (fl_pad != -1) { 287 printf("Invalid hw.cxgbe.fl_pad value (%d)," 288 " using %d instead.\n", fl_pad, max(pad, 32)); 289 } 290 fl_pad = max(pad, 32); 291 } 292 293 /* 294 * T4 has the same pad and pack boundary. If a pad boundary is set, 295 * pack boundary must be set to the same value. Otherwise take the 296 * specified value or auto-calculate something reasonable. 297 */ 298 if (fl_pad) 299 t4_fl_pack = fl_pad; 300 else if (fl_pack < 32 || fl_pack > 4096 || !powerof2(fl_pack)) 301 t4_fl_pack = max(pad, 32); 302 else 303 t4_fl_pack = fl_pack; 304 305 /* T5's pack boundary is independent of the pad boundary. */ 306 if (fl_pack < 16 || fl_pack == 32 || fl_pack > 4096 || 307 !powerof2(fl_pack)) 308 t5_fl_pack = max(pad, CACHE_LINE_SIZE); 309 else 310 t5_fl_pack = fl_pack; 311 312 if (spg_len != 64 && spg_len != 128) { 313 int len; 314 315 #if defined(__i386__) || defined(__amd64__) 316 len = cpu_clflush_line_size > 64 ? 128 : 64; 317 #else 318 len = 64; 319 #endif 320 if (spg_len != -1) { 321 printf("Invalid hw.cxgbe.spg_len value (%d)," 322 " using %d instead.\n", spg_len, len); 323 } 324 spg_len = len; 325 } 326 327 if (cong_drop < -1 || cong_drop > 1) { 328 printf("Invalid hw.cxgbe.cong_drop value (%d)," 329 " using 0 instead.\n", cong_drop); 330 cong_drop = 0; 331 } 332 } 333 334 void 335 t4_init_sge_cpl_handlers(struct adapter *sc) 336 { 337 338 t4_register_cpl_handler(sc, CPL_FW4_MSG, handle_fw_msg); 339 t4_register_cpl_handler(sc, CPL_FW6_MSG, handle_fw_msg); 340 t4_register_cpl_handler(sc, CPL_SGE_EGR_UPDATE, handle_sge_egr_update); 341 t4_register_cpl_handler(sc, CPL_RX_PKT, t4_eth_rx); 342 t4_register_fw_msg_handler(sc, FW6_TYPE_CMD_RPL, t4_handle_fw_rpl); 343 } 344 345 /* 346 * adap->params.vpd.cclk must be set up before this is called. 347 */ 348 void 349 t4_tweak_chip_settings(struct adapter *sc) 350 { 351 int i; 352 uint32_t v, m; 353 int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200}; 354 int timer_max = M_TIMERVALUE0 * 1000 / sc->params.vpd.cclk; 355 int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */ 356 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 357 static int sge_flbuf_sizes[] = { 358 MCLBYTES, 359 #if MJUMPAGESIZE != MCLBYTES 360 MJUMPAGESIZE, 361 MJUMPAGESIZE - CL_METADATA_SIZE, 362 MJUMPAGESIZE - 2 * MSIZE - CL_METADATA_SIZE, 363 #endif 364 MJUM9BYTES, 365 MJUM16BYTES, 366 MCLBYTES - MSIZE - CL_METADATA_SIZE, 367 MJUM9BYTES - CL_METADATA_SIZE, 368 MJUM16BYTES - CL_METADATA_SIZE, 369 }; 370 371 KASSERT(sc->flags & MASTER_PF, 372 ("%s: trying to change chip settings when not master.", __func__)); 373 374 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE; 375 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE | 376 V_EGRSTATUSPAGESIZE(spg_len == 128); 377 if (is_t4(sc) && (fl_pad || buffer_packing)) { 378 /* t4_fl_pack has the correct value even when fl_pad = 0 */ 379 m |= V_INGPADBOUNDARY(M_INGPADBOUNDARY); 380 v |= V_INGPADBOUNDARY(ilog2(t4_fl_pack) - 5); 381 } else if (is_t5(sc) && fl_pad) { 382 m |= V_INGPADBOUNDARY(M_INGPADBOUNDARY); 383 v |= V_INGPADBOUNDARY(ilog2(fl_pad) - 5); 384 } 385 t4_set_reg_field(sc, A_SGE_CONTROL, m, v); 386 387 if (is_t5(sc) && buffer_packing) { 388 m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY); 389 if (t5_fl_pack == 16) 390 v = V_INGPACKBOUNDARY(0); 391 else 392 v = V_INGPACKBOUNDARY(ilog2(t5_fl_pack) - 5); 393 t4_set_reg_field(sc, A_SGE_CONTROL2, m, v); 394 } 395 396 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) | 397 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) | 398 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) | 399 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) | 400 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) | 401 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) | 402 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) | 403 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10); 404 t4_write_reg(sc, A_SGE_HOST_PAGE_SIZE, v); 405 406 KASSERT(nitems(sge_flbuf_sizes) <= SGE_FLBUF_SIZES, 407 ("%s: hw buffer size table too big", __func__)); 408 for (i = 0; i < min(nitems(sge_flbuf_sizes), SGE_FLBUF_SIZES); i++) { 409 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0 + (4 * i), 410 sge_flbuf_sizes[i]); 411 } 412 413 v = V_THRESHOLD_0(intr_pktcount[0]) | V_THRESHOLD_1(intr_pktcount[1]) | 414 V_THRESHOLD_2(intr_pktcount[2]) | V_THRESHOLD_3(intr_pktcount[3]); 415 t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD, v); 416 417 KASSERT(intr_timer[0] <= timer_max, 418 ("%s: not a single usable timer (%d, %d)", __func__, intr_timer[0], 419 timer_max)); 420 for (i = 1; i < nitems(intr_timer); i++) { 421 KASSERT(intr_timer[i] >= intr_timer[i - 1], 422 ("%s: timers not listed in increasing order (%d)", 423 __func__, i)); 424 425 while (intr_timer[i] > timer_max) { 426 if (i == nitems(intr_timer) - 1) { 427 intr_timer[i] = timer_max; 428 break; 429 } 430 intr_timer[i] += intr_timer[i - 1]; 431 intr_timer[i] /= 2; 432 } 433 } 434 435 v = V_TIMERVALUE0(us_to_core_ticks(sc, intr_timer[0])) | 436 V_TIMERVALUE1(us_to_core_ticks(sc, intr_timer[1])); 437 t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1, v); 438 v = V_TIMERVALUE2(us_to_core_ticks(sc, intr_timer[2])) | 439 V_TIMERVALUE3(us_to_core_ticks(sc, intr_timer[3])); 440 t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3, v); 441 v = V_TIMERVALUE4(us_to_core_ticks(sc, intr_timer[4])) | 442 V_TIMERVALUE5(us_to_core_ticks(sc, intr_timer[5])); 443 t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5, v); 444 445 if (cong_drop == 0) { 446 m = F_TUNNELCNGDROP0 | F_TUNNELCNGDROP1 | F_TUNNELCNGDROP2 | 447 F_TUNNELCNGDROP3; 448 t4_set_reg_field(sc, A_TP_PARA_REG3, m, 0); 449 } 450 451 /* 4K, 16K, 64K, 256K DDP "page sizes" */ 452 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 453 t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, v); 454 455 m = v = F_TDDPTAGTCB; 456 t4_set_reg_field(sc, A_ULP_RX_CTL, m, v); 457 458 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 459 F_RESETDDPOFFSET; 460 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 461 t4_set_reg_field(sc, A_TP_PARA_REG5, m, v); 462 } 463 464 /* 465 * SGE wants the buffer to be at least 64B and then a multiple of the pad 466 * boundary or 16, whichever is greater. 467 */ 468 static inline int 469 hwsz_ok(int hwsz) 470 { 471 int mask = max(fl_pad, 16) - 1; 472 473 return (hwsz >= 64 && (hwsz & mask) == 0); 474 } 475 476 /* 477 * XXX: driver really should be able to deal with unexpected settings. 478 */ 479 int 480 t4_read_chip_settings(struct adapter *sc) 481 { 482 struct sge *s = &sc->sge; 483 int i, j, n, rc = 0; 484 uint32_t m, v, r; 485 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 486 static int sw_buf_sizes[] = { /* Sorted by size */ 487 MCLBYTES, 488 #if MJUMPAGESIZE != MCLBYTES 489 MJUMPAGESIZE, 490 #endif 491 MJUM9BYTES, 492 MJUM16BYTES 493 }; 494 struct sw_zone_info *swz, *safe_swz; 495 struct hw_buf_info *hwb; 496 497 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE; 498 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE | 499 V_EGRSTATUSPAGESIZE(spg_len == 128); 500 if (is_t4(sc) && (fl_pad || buffer_packing)) { 501 m |= V_INGPADBOUNDARY(M_INGPADBOUNDARY); 502 v |= V_INGPADBOUNDARY(ilog2(t4_fl_pack) - 5); 503 } else if (is_t5(sc) && fl_pad) { 504 m |= V_INGPADBOUNDARY(M_INGPADBOUNDARY); 505 v |= V_INGPADBOUNDARY(ilog2(fl_pad) - 5); 506 } 507 r = t4_read_reg(sc, A_SGE_CONTROL); 508 if ((r & m) != v) { 509 device_printf(sc->dev, "invalid SGE_CONTROL(0x%x)\n", r); 510 rc = EINVAL; 511 } 512 513 if (is_t5(sc) && buffer_packing) { 514 m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY); 515 if (t5_fl_pack == 16) 516 v = V_INGPACKBOUNDARY(0); 517 else 518 v = V_INGPACKBOUNDARY(ilog2(t5_fl_pack) - 5); 519 r = t4_read_reg(sc, A_SGE_CONTROL2); 520 if ((r & m) != v) { 521 device_printf(sc->dev, 522 "invalid SGE_CONTROL2(0x%x)\n", r); 523 rc = EINVAL; 524 } 525 } 526 s->pack_boundary = is_t4(sc) ? t4_fl_pack : t5_fl_pack; 527 528 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) | 529 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) | 530 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) | 531 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) | 532 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) | 533 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) | 534 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) | 535 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10); 536 r = t4_read_reg(sc, A_SGE_HOST_PAGE_SIZE); 537 if (r != v) { 538 device_printf(sc->dev, "invalid SGE_HOST_PAGE_SIZE(0x%x)\n", r); 539 rc = EINVAL; 540 } 541 542 /* Filter out unusable hw buffer sizes entirely (mark with -2). */ 543 hwb = &s->hw_buf_info[0]; 544 for (i = 0; i < nitems(s->hw_buf_info); i++, hwb++) { 545 r = t4_read_reg(sc, A_SGE_FL_BUFFER_SIZE0 + (4 * i)); 546 hwb->size = r; 547 hwb->zidx = hwsz_ok(r) ? -1 : -2; 548 hwb->next = -1; 549 } 550 551 /* 552 * Create a sorted list in decreasing order of hw buffer sizes (and so 553 * increasing order of spare area) for each software zone. 554 */ 555 n = 0; /* no usable buffer size to begin with */ 556 swz = &s->sw_zone_info[0]; 557 safe_swz = NULL; 558 for (i = 0; i < SW_ZONE_SIZES; i++, swz++) { 559 int8_t head = -1, tail = -1; 560 561 swz->size = sw_buf_sizes[i]; 562 swz->zone = m_getzone(swz->size); 563 swz->type = m_gettype(swz->size); 564 565 if (swz->size == safest_rx_cluster) 566 safe_swz = swz; 567 568 hwb = &s->hw_buf_info[0]; 569 for (j = 0; j < SGE_FLBUF_SIZES; j++, hwb++) { 570 if (hwb->zidx != -1 || hwb->size > swz->size) 571 continue; 572 hwb->zidx = i; 573 if (head == -1) 574 head = tail = j; 575 else if (hwb->size < s->hw_buf_info[tail].size) { 576 s->hw_buf_info[tail].next = j; 577 tail = j; 578 } else { 579 int8_t *cur; 580 struct hw_buf_info *t; 581 582 for (cur = &head; *cur != -1; cur = &t->next) { 583 t = &s->hw_buf_info[*cur]; 584 if (hwb->size == t->size) { 585 hwb->zidx = -2; 586 break; 587 } 588 if (hwb->size > t->size) { 589 hwb->next = *cur; 590 *cur = j; 591 break; 592 } 593 } 594 } 595 } 596 swz->head_hwidx = head; 597 swz->tail_hwidx = tail; 598 599 if (tail != -1) { 600 n++; 601 if (swz->size - s->hw_buf_info[tail].size >= 602 CL_METADATA_SIZE) 603 sc->flags |= BUF_PACKING_OK; 604 } 605 } 606 if (n == 0) { 607 device_printf(sc->dev, "no usable SGE FL buffer size.\n"); 608 rc = EINVAL; 609 } 610 611 s->safe_hwidx1 = -1; 612 s->safe_hwidx2 = -1; 613 if (safe_swz != NULL) { 614 s->safe_hwidx1 = safe_swz->head_hwidx; 615 for (i = safe_swz->head_hwidx; i != -1; i = hwb->next) { 616 int spare; 617 618 hwb = &s->hw_buf_info[i]; 619 spare = safe_swz->size - hwb->size; 620 if (spare < CL_METADATA_SIZE) 621 continue; 622 if (s->safe_hwidx2 == -1 || 623 spare == CL_METADATA_SIZE + MSIZE) 624 s->safe_hwidx2 = i; 625 if (spare >= CL_METADATA_SIZE + MSIZE) 626 break; 627 } 628 } 629 630 r = t4_read_reg(sc, A_SGE_INGRESS_RX_THRESHOLD); 631 s->counter_val[0] = G_THRESHOLD_0(r); 632 s->counter_val[1] = G_THRESHOLD_1(r); 633 s->counter_val[2] = G_THRESHOLD_2(r); 634 s->counter_val[3] = G_THRESHOLD_3(r); 635 636 r = t4_read_reg(sc, A_SGE_TIMER_VALUE_0_AND_1); 637 s->timer_val[0] = G_TIMERVALUE0(r) / core_ticks_per_usec(sc); 638 s->timer_val[1] = G_TIMERVALUE1(r) / core_ticks_per_usec(sc); 639 r = t4_read_reg(sc, A_SGE_TIMER_VALUE_2_AND_3); 640 s->timer_val[2] = G_TIMERVALUE2(r) / core_ticks_per_usec(sc); 641 s->timer_val[3] = G_TIMERVALUE3(r) / core_ticks_per_usec(sc); 642 r = t4_read_reg(sc, A_SGE_TIMER_VALUE_4_AND_5); 643 s->timer_val[4] = G_TIMERVALUE4(r) / core_ticks_per_usec(sc); 644 s->timer_val[5] = G_TIMERVALUE5(r) / core_ticks_per_usec(sc); 645 646 if (cong_drop == 0) { 647 m = F_TUNNELCNGDROP0 | F_TUNNELCNGDROP1 | F_TUNNELCNGDROP2 | 648 F_TUNNELCNGDROP3; 649 r = t4_read_reg(sc, A_TP_PARA_REG3); 650 if (r & m) { 651 device_printf(sc->dev, 652 "invalid TP_PARA_REG3(0x%x)\n", r); 653 rc = EINVAL; 654 } 655 } 656 657 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 658 r = t4_read_reg(sc, A_ULP_RX_TDDP_PSZ); 659 if (r != v) { 660 device_printf(sc->dev, "invalid ULP_RX_TDDP_PSZ(0x%x)\n", r); 661 rc = EINVAL; 662 } 663 664 m = v = F_TDDPTAGTCB; 665 r = t4_read_reg(sc, A_ULP_RX_CTL); 666 if ((r & m) != v) { 667 device_printf(sc->dev, "invalid ULP_RX_CTL(0x%x)\n", r); 668 rc = EINVAL; 669 } 670 671 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 672 F_RESETDDPOFFSET; 673 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 674 r = t4_read_reg(sc, A_TP_PARA_REG5); 675 if ((r & m) != v) { 676 device_printf(sc->dev, "invalid TP_PARA_REG5(0x%x)\n", r); 677 rc = EINVAL; 678 } 679 680 r = t4_read_reg(sc, A_SGE_CONM_CTRL); 681 s->fl_starve_threshold = G_EGRTHRESHOLD(r) * 2 + 1; 682 if (is_t4(sc)) 683 s->fl_starve_threshold2 = s->fl_starve_threshold; 684 else 685 s->fl_starve_threshold2 = G_EGRTHRESHOLDPACKING(r) * 2 + 1; 686 687 /* egress queues: log2 of # of doorbells per BAR2 page */ 688 r = t4_read_reg(sc, A_SGE_EGRESS_QUEUES_PER_PAGE_PF); 689 r >>= S_QUEUESPERPAGEPF0 + 690 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * sc->pf; 691 s->eq_s_qpp = r & M_QUEUESPERPAGEPF0; 692 693 /* ingress queues: log2 of # of doorbells per BAR2 page */ 694 r = t4_read_reg(sc, A_SGE_INGRESS_QUEUES_PER_PAGE_PF); 695 r >>= S_QUEUESPERPAGEPF0 + 696 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * sc->pf; 697 s->iq_s_qpp = r & M_QUEUESPERPAGEPF0; 698 699 t4_init_tp_params(sc); 700 701 t4_read_mtu_tbl(sc, sc->params.mtus, NULL); 702 t4_load_mtus(sc, sc->params.mtus, sc->params.a_wnd, sc->params.b_wnd); 703 704 return (rc); 705 } 706 707 int 708 t4_create_dma_tag(struct adapter *sc) 709 { 710 int rc; 711 712 rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0, 713 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE, 714 BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL, 715 NULL, &sc->dmat); 716 if (rc != 0) { 717 device_printf(sc->dev, 718 "failed to create main DMA tag: %d\n", rc); 719 } 720 721 return (rc); 722 } 723 724 static inline int 725 enable_buffer_packing(struct adapter *sc) 726 { 727 728 if (sc->flags & BUF_PACKING_OK && 729 ((is_t5(sc) && buffer_packing) || /* 1 or -1 both ok for T5 */ 730 (is_t4(sc) && buffer_packing == 1))) 731 return (1); 732 return (0); 733 } 734 735 void 736 t4_sge_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx, 737 struct sysctl_oid_list *children) 738 { 739 740 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "buffer_sizes", 741 CTLTYPE_STRING | CTLFLAG_RD, &sc->sge, 0, sysctl_bufsizes, "A", 742 "freelist buffer sizes"); 743 744 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pktshift", CTLFLAG_RD, 745 NULL, fl_pktshift, "payload DMA offset in rx buffer (bytes)"); 746 747 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pad", CTLFLAG_RD, 748 NULL, fl_pad, "payload pad boundary (bytes)"); 749 750 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "spg_len", CTLFLAG_RD, 751 NULL, spg_len, "status page size (bytes)"); 752 753 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_drop", CTLFLAG_RD, 754 NULL, cong_drop, "congestion drop setting"); 755 756 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "buffer_packing", CTLFLAG_RD, 757 NULL, enable_buffer_packing(sc), 758 "pack multiple frames in one fl buffer"); 759 760 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pack", CTLFLAG_RD, 761 NULL, sc->sge.pack_boundary, "payload pack boundary (bytes)"); 762 } 763 764 int 765 t4_destroy_dma_tag(struct adapter *sc) 766 { 767 if (sc->dmat) 768 bus_dma_tag_destroy(sc->dmat); 769 770 return (0); 771 } 772 773 /* 774 * Allocate and initialize the firmware event queue and the management queue. 775 * 776 * Returns errno on failure. Resources allocated up to that point may still be 777 * allocated. Caller is responsible for cleanup in case this function fails. 778 */ 779 int 780 t4_setup_adapter_queues(struct adapter *sc) 781 { 782 int rc; 783 784 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 785 786 sysctl_ctx_init(&sc->ctx); 787 sc->flags |= ADAP_SYSCTL_CTX; 788 789 /* 790 * Firmware event queue 791 */ 792 rc = alloc_fwq(sc); 793 if (rc != 0) 794 return (rc); 795 796 /* 797 * Management queue. This is just a control queue that uses the fwq as 798 * its associated iq. 799 */ 800 rc = alloc_mgmtq(sc); 801 802 return (rc); 803 } 804 805 /* 806 * Idempotent 807 */ 808 int 809 t4_teardown_adapter_queues(struct adapter *sc) 810 { 811 812 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 813 814 /* Do this before freeing the queue */ 815 if (sc->flags & ADAP_SYSCTL_CTX) { 816 sysctl_ctx_free(&sc->ctx); 817 sc->flags &= ~ADAP_SYSCTL_CTX; 818 } 819 820 free_mgmtq(sc); 821 free_fwq(sc); 822 823 return (0); 824 } 825 826 static inline int 827 port_intr_count(struct port_info *pi) 828 { 829 int rc = 0; 830 831 if (pi->flags & INTR_RXQ) 832 rc += pi->nrxq; 833 #ifdef TCP_OFFLOAD 834 if (pi->flags & INTR_OFLD_RXQ) 835 rc += pi->nofldrxq; 836 #endif 837 #ifdef DEV_NETMAP 838 if (pi->flags & INTR_NM_RXQ) 839 rc += pi->nnmrxq; 840 #endif 841 return (rc); 842 } 843 844 static inline int 845 first_vector(struct port_info *pi) 846 { 847 struct adapter *sc = pi->adapter; 848 int rc = T4_EXTRA_INTR, i; 849 850 if (sc->intr_count == 1) 851 return (0); 852 853 for_each_port(sc, i) { 854 if (i == pi->port_id) 855 break; 856 857 rc += port_intr_count(sc->port[i]); 858 } 859 860 return (rc); 861 } 862 863 /* 864 * Given an arbitrary "index," come up with an iq that can be used by other 865 * queues (of this port) for interrupt forwarding, SGE egress updates, etc. 866 * The iq returned is guaranteed to be something that takes direct interrupts. 867 */ 868 static struct sge_iq * 869 port_intr_iq(struct port_info *pi, int idx) 870 { 871 struct adapter *sc = pi->adapter; 872 struct sge *s = &sc->sge; 873 struct sge_iq *iq = NULL; 874 int nintr, i; 875 876 if (sc->intr_count == 1) 877 return (&sc->sge.fwq); 878 879 nintr = port_intr_count(pi); 880 KASSERT(nintr != 0, 881 ("%s: pi %p has no exclusive interrupts, total interrupts = %d", 882 __func__, pi, sc->intr_count)); 883 #ifdef DEV_NETMAP 884 /* Exclude netmap queues as they can't take anyone else's interrupts */ 885 if (pi->flags & INTR_NM_RXQ) 886 nintr -= pi->nnmrxq; 887 KASSERT(nintr > 0, 888 ("%s: pi %p has nintr %d after netmap adjustment of %d", __func__, 889 pi, nintr, pi->nnmrxq)); 890 #endif 891 i = idx % nintr; 892 893 if (pi->flags & INTR_RXQ) { 894 if (i < pi->nrxq) { 895 iq = &s->rxq[pi->first_rxq + i].iq; 896 goto done; 897 } 898 i -= pi->nrxq; 899 } 900 #ifdef TCP_OFFLOAD 901 if (pi->flags & INTR_OFLD_RXQ) { 902 if (i < pi->nofldrxq) { 903 iq = &s->ofld_rxq[pi->first_ofld_rxq + i].iq; 904 goto done; 905 } 906 i -= pi->nofldrxq; 907 } 908 #endif 909 panic("%s: pi %p, intr_flags 0x%lx, idx %d, total intr %d\n", __func__, 910 pi, pi->flags & INTR_ALL, idx, nintr); 911 done: 912 MPASS(iq != NULL); 913 KASSERT(iq->flags & IQ_INTR, 914 ("%s: iq %p (port %p, intr_flags 0x%lx, idx %d)", __func__, iq, pi, 915 pi->flags & INTR_ALL, idx)); 916 return (iq); 917 } 918 919 /* Maximum payload that can be delivered with a single iq descriptor */ 920 static inline int 921 mtu_to_max_payload(struct adapter *sc, int mtu, const int toe) 922 { 923 int payload; 924 925 #ifdef TCP_OFFLOAD 926 if (toe) { 927 payload = sc->tt.rx_coalesce ? 928 G_RXCOALESCESIZE(t4_read_reg(sc, A_TP_PARA_REG2)) : mtu; 929 } else { 930 #endif 931 /* large enough even when hw VLAN extraction is disabled */ 932 payload = fl_pktshift + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 933 mtu; 934 #ifdef TCP_OFFLOAD 935 } 936 #endif 937 payload = roundup2(payload, fl_pad); 938 939 return (payload); 940 } 941 942 int 943 t4_setup_port_queues(struct port_info *pi) 944 { 945 int rc = 0, i, j, intr_idx, iqid; 946 struct sge_rxq *rxq; 947 struct sge_txq *txq; 948 struct sge_wrq *ctrlq; 949 #ifdef TCP_OFFLOAD 950 struct sge_ofld_rxq *ofld_rxq; 951 struct sge_wrq *ofld_txq; 952 #endif 953 #ifdef DEV_NETMAP 954 struct sge_nm_rxq *nm_rxq; 955 struct sge_nm_txq *nm_txq; 956 #endif 957 char name[16]; 958 struct adapter *sc = pi->adapter; 959 struct ifnet *ifp = pi->ifp; 960 struct sysctl_oid *oid = device_get_sysctl_tree(pi->dev); 961 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 962 int maxp, pack, mtu = ifp->if_mtu; 963 964 /* Interrupt vector to start from (when using multiple vectors) */ 965 intr_idx = first_vector(pi); 966 967 /* 968 * First pass over all NIC and TOE rx queues: 969 * a) initialize iq and fl 970 * b) allocate queue iff it will take direct interrupts. 971 */ 972 maxp = mtu_to_max_payload(sc, mtu, 0); 973 pack = enable_buffer_packing(sc); 974 if (pi->flags & INTR_RXQ) { 975 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "rxq", 976 CTLFLAG_RD, NULL, "rx queues"); 977 } 978 for_each_rxq(pi, i, rxq) { 979 980 init_iq(&rxq->iq, sc, pi->tmr_idx, pi->pktc_idx, pi->qsize_rxq, 981 RX_IQ_ESIZE); 982 983 snprintf(name, sizeof(name), "%s rxq%d-fl", 984 device_get_nameunit(pi->dev), i); 985 init_fl(sc, &rxq->fl, pi->qsize_rxq / 8, maxp, pack, name); 986 987 if (pi->flags & INTR_RXQ) { 988 rxq->iq.flags |= IQ_INTR; 989 rc = alloc_rxq(pi, rxq, intr_idx, i, oid); 990 if (rc != 0) 991 goto done; 992 intr_idx++; 993 } 994 } 995 #ifdef TCP_OFFLOAD 996 maxp = mtu_to_max_payload(sc, mtu, 1); 997 if (is_offload(sc) && pi->flags & INTR_OFLD_RXQ) { 998 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "ofld_rxq", 999 CTLFLAG_RD, NULL, 1000 "rx queues for offloaded TCP connections"); 1001 } 1002 for_each_ofld_rxq(pi, i, ofld_rxq) { 1003 1004 init_iq(&ofld_rxq->iq, sc, pi->tmr_idx, pi->pktc_idx, 1005 pi->qsize_rxq, RX_IQ_ESIZE); 1006 1007 snprintf(name, sizeof(name), "%s ofld_rxq%d-fl", 1008 device_get_nameunit(pi->dev), i); 1009 init_fl(sc, &ofld_rxq->fl, pi->qsize_rxq / 8, maxp, pack, name); 1010 1011 if (pi->flags & INTR_OFLD_RXQ) { 1012 ofld_rxq->iq.flags |= IQ_INTR; 1013 rc = alloc_ofld_rxq(pi, ofld_rxq, intr_idx, i, oid); 1014 if (rc != 0) 1015 goto done; 1016 intr_idx++; 1017 } 1018 } 1019 #endif 1020 #ifdef DEV_NETMAP 1021 /* 1022 * We don't have buffers to back the netmap rx queues right now so we 1023 * create the queues in a way that doesn't set off any congestion signal 1024 * in the chip. 1025 */ 1026 if (pi->flags & INTR_NM_RXQ) { 1027 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "nm_rxq", 1028 CTLFLAG_RD, NULL, "rx queues for netmap"); 1029 for_each_nm_rxq(pi, i, nm_rxq) { 1030 rc = alloc_nm_rxq(pi, nm_rxq, intr_idx, i, oid); 1031 if (rc != 0) 1032 goto done; 1033 intr_idx++; 1034 } 1035 } 1036 #endif 1037 1038 /* 1039 * Second pass over all NIC and TOE rx queues. The queues forwarding 1040 * their interrupts are allocated now. 1041 */ 1042 j = 0; 1043 if (!(pi->flags & INTR_RXQ)) { 1044 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "rxq", 1045 CTLFLAG_RD, NULL, "rx queues"); 1046 for_each_rxq(pi, i, rxq) { 1047 MPASS(!(rxq->iq.flags & IQ_INTR)); 1048 1049 intr_idx = port_intr_iq(pi, j)->abs_id; 1050 1051 rc = alloc_rxq(pi, rxq, intr_idx, i, oid); 1052 if (rc != 0) 1053 goto done; 1054 j++; 1055 } 1056 } 1057 #ifdef TCP_OFFLOAD 1058 if (is_offload(sc) && !(pi->flags & INTR_OFLD_RXQ)) { 1059 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "ofld_rxq", 1060 CTLFLAG_RD, NULL, 1061 "rx queues for offloaded TCP connections"); 1062 for_each_ofld_rxq(pi, i, ofld_rxq) { 1063 MPASS(!(ofld_rxq->iq.flags & IQ_INTR)); 1064 1065 intr_idx = port_intr_iq(pi, j)->abs_id; 1066 1067 rc = alloc_ofld_rxq(pi, ofld_rxq, intr_idx, i, oid); 1068 if (rc != 0) 1069 goto done; 1070 j++; 1071 } 1072 } 1073 #endif 1074 #ifdef DEV_NETMAP 1075 if (!(pi->flags & INTR_NM_RXQ)) 1076 CXGBE_UNIMPLEMENTED(__func__); 1077 #endif 1078 1079 /* 1080 * Now the tx queues. Only one pass needed. 1081 */ 1082 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "txq", CTLFLAG_RD, 1083 NULL, "tx queues"); 1084 j = 0; 1085 for_each_txq(pi, i, txq) { 1086 iqid = port_intr_iq(pi, j)->cntxt_id; 1087 snprintf(name, sizeof(name), "%s txq%d", 1088 device_get_nameunit(pi->dev), i); 1089 init_eq(&txq->eq, EQ_ETH, pi->qsize_txq, pi->tx_chan, iqid, 1090 name); 1091 1092 rc = alloc_txq(pi, txq, i, oid); 1093 if (rc != 0) 1094 goto done; 1095 j++; 1096 } 1097 #ifdef TCP_OFFLOAD 1098 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "ofld_txq", 1099 CTLFLAG_RD, NULL, "tx queues for offloaded TCP connections"); 1100 for_each_ofld_txq(pi, i, ofld_txq) { 1101 struct sysctl_oid *oid2; 1102 1103 iqid = port_intr_iq(pi, j)->cntxt_id; 1104 snprintf(name, sizeof(name), "%s ofld_txq%d", 1105 device_get_nameunit(pi->dev), i); 1106 init_eq(&ofld_txq->eq, EQ_OFLD, pi->qsize_txq, pi->tx_chan, 1107 iqid, name); 1108 1109 snprintf(name, sizeof(name), "%d", i); 1110 oid2 = SYSCTL_ADD_NODE(&pi->ctx, SYSCTL_CHILDREN(oid), OID_AUTO, 1111 name, CTLFLAG_RD, NULL, "offload tx queue"); 1112 1113 rc = alloc_wrq(sc, pi, ofld_txq, oid2); 1114 if (rc != 0) 1115 goto done; 1116 j++; 1117 } 1118 #endif 1119 #ifdef DEV_NETMAP 1120 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "nm_txq", 1121 CTLFLAG_RD, NULL, "tx queues for netmap use"); 1122 for_each_nm_txq(pi, i, nm_txq) { 1123 iqid = pi->first_nm_rxq + (j % pi->nnmrxq); 1124 rc = alloc_nm_txq(pi, nm_txq, iqid, i, oid); 1125 if (rc != 0) 1126 goto done; 1127 j++; 1128 } 1129 #endif 1130 1131 /* 1132 * Finally, the control queue. 1133 */ 1134 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "ctrlq", CTLFLAG_RD, 1135 NULL, "ctrl queue"); 1136 ctrlq = &sc->sge.ctrlq[pi->port_id]; 1137 iqid = port_intr_iq(pi, 0)->cntxt_id; 1138 snprintf(name, sizeof(name), "%s ctrlq", device_get_nameunit(pi->dev)); 1139 init_eq(&ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE, pi->tx_chan, iqid, name); 1140 rc = alloc_wrq(sc, pi, ctrlq, oid); 1141 1142 done: 1143 if (rc) 1144 t4_teardown_port_queues(pi); 1145 1146 return (rc); 1147 } 1148 1149 /* 1150 * Idempotent 1151 */ 1152 int 1153 t4_teardown_port_queues(struct port_info *pi) 1154 { 1155 int i; 1156 struct adapter *sc = pi->adapter; 1157 struct sge_rxq *rxq; 1158 struct sge_txq *txq; 1159 #ifdef TCP_OFFLOAD 1160 struct sge_ofld_rxq *ofld_rxq; 1161 struct sge_wrq *ofld_txq; 1162 #endif 1163 #ifdef DEV_NETMAP 1164 struct sge_nm_rxq *nm_rxq; 1165 struct sge_nm_txq *nm_txq; 1166 #endif 1167 1168 /* Do this before freeing the queues */ 1169 if (pi->flags & PORT_SYSCTL_CTX) { 1170 sysctl_ctx_free(&pi->ctx); 1171 pi->flags &= ~PORT_SYSCTL_CTX; 1172 } 1173 1174 /* 1175 * Take down all the tx queues first, as they reference the rx queues 1176 * (for egress updates, etc.). 1177 */ 1178 1179 free_wrq(sc, &sc->sge.ctrlq[pi->port_id]); 1180 1181 for_each_txq(pi, i, txq) { 1182 free_txq(pi, txq); 1183 } 1184 #ifdef TCP_OFFLOAD 1185 for_each_ofld_txq(pi, i, ofld_txq) { 1186 free_wrq(sc, ofld_txq); 1187 } 1188 #endif 1189 #ifdef DEV_NETMAP 1190 for_each_nm_txq(pi, i, nm_txq) 1191 free_nm_txq(pi, nm_txq); 1192 #endif 1193 1194 /* 1195 * Then take down the rx queues that forward their interrupts, as they 1196 * reference other rx queues. 1197 */ 1198 1199 for_each_rxq(pi, i, rxq) { 1200 if ((rxq->iq.flags & IQ_INTR) == 0) 1201 free_rxq(pi, rxq); 1202 } 1203 #ifdef TCP_OFFLOAD 1204 for_each_ofld_rxq(pi, i, ofld_rxq) { 1205 if ((ofld_rxq->iq.flags & IQ_INTR) == 0) 1206 free_ofld_rxq(pi, ofld_rxq); 1207 } 1208 #endif 1209 #ifdef DEV_NETMAP 1210 for_each_nm_rxq(pi, i, nm_rxq) 1211 free_nm_rxq(pi, nm_rxq); 1212 #endif 1213 1214 /* 1215 * Then take down the rx queues that take direct interrupts. 1216 */ 1217 1218 for_each_rxq(pi, i, rxq) { 1219 if (rxq->iq.flags & IQ_INTR) 1220 free_rxq(pi, rxq); 1221 } 1222 #ifdef TCP_OFFLOAD 1223 for_each_ofld_rxq(pi, i, ofld_rxq) { 1224 if (ofld_rxq->iq.flags & IQ_INTR) 1225 free_ofld_rxq(pi, ofld_rxq); 1226 } 1227 #endif 1228 #ifdef DEV_NETMAP 1229 CXGBE_UNIMPLEMENTED(__func__); 1230 #endif 1231 1232 return (0); 1233 } 1234 1235 /* 1236 * Deals with errors and the firmware event queue. All data rx queues forward 1237 * their interrupt to the firmware event queue. 1238 */ 1239 void 1240 t4_intr_all(void *arg) 1241 { 1242 struct adapter *sc = arg; 1243 struct sge_iq *fwq = &sc->sge.fwq; 1244 1245 t4_intr_err(arg); 1246 if (atomic_cmpset_int(&fwq->state, IQS_IDLE, IQS_BUSY)) { 1247 service_iq(fwq, 0); 1248 atomic_cmpset_int(&fwq->state, IQS_BUSY, IQS_IDLE); 1249 } 1250 } 1251 1252 /* Deals with error interrupts */ 1253 void 1254 t4_intr_err(void *arg) 1255 { 1256 struct adapter *sc = arg; 1257 1258 t4_write_reg(sc, MYPF_REG(A_PCIE_PF_CLI), 0); 1259 t4_slow_intr_handler(sc); 1260 } 1261 1262 void 1263 t4_intr_evt(void *arg) 1264 { 1265 struct sge_iq *iq = arg; 1266 1267 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 1268 service_iq(iq, 0); 1269 atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 1270 } 1271 } 1272 1273 void 1274 t4_intr(void *arg) 1275 { 1276 struct sge_iq *iq = arg; 1277 1278 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 1279 service_iq(iq, 0); 1280 atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 1281 } 1282 } 1283 1284 /* 1285 * Deals with anything and everything on the given ingress queue. 1286 */ 1287 static int 1288 service_iq(struct sge_iq *iq, int budget) 1289 { 1290 struct sge_iq *q; 1291 struct sge_rxq *rxq = iq_to_rxq(iq); /* Use iff iq is part of rxq */ 1292 struct sge_fl *fl = &rxq->fl; /* Use iff IQ_HAS_FL */ 1293 struct adapter *sc = iq->adapter; 1294 struct rsp_ctrl *ctrl; 1295 const struct rss_header *rss; 1296 int ndescs = 0, limit, fl_bufs_used = 0; 1297 int rsp_type; 1298 uint32_t lq; 1299 struct mbuf *m0; 1300 STAILQ_HEAD(, sge_iq) iql = STAILQ_HEAD_INITIALIZER(iql); 1301 #if defined(INET) || defined(INET6) 1302 const struct timeval lro_timeout = {0, sc->lro_timeout}; 1303 #endif 1304 1305 limit = budget ? budget : iq->qsize / 8; 1306 1307 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq)); 1308 1309 /* 1310 * We always come back and check the descriptor ring for new indirect 1311 * interrupts and other responses after running a single handler. 1312 */ 1313 for (;;) { 1314 while (is_new_response(iq, &ctrl)) { 1315 1316 rmb(); 1317 1318 m0 = NULL; 1319 rsp_type = G_RSPD_TYPE(ctrl->u.type_gen); 1320 lq = be32toh(ctrl->pldbuflen_qid); 1321 rss = (const void *)iq->cdesc; 1322 1323 switch (rsp_type) { 1324 case X_RSPD_TYPE_FLBUF: 1325 1326 KASSERT(iq->flags & IQ_HAS_FL, 1327 ("%s: data for an iq (%p) with no freelist", 1328 __func__, iq)); 1329 1330 m0 = get_fl_payload(sc, fl, lq, &fl_bufs_used); 1331 if (__predict_false(m0 == NULL)) 1332 goto process_iql; 1333 #ifdef T4_PKT_TIMESTAMP 1334 /* 1335 * 60 bit timestamp for the payload is 1336 * *(uint64_t *)m0->m_pktdat. Note that it is 1337 * in the leading free-space in the mbuf. The 1338 * kernel can clobber it during a pullup, 1339 * m_copymdata, etc. You need to make sure that 1340 * the mbuf reaches you unmolested if you care 1341 * about the timestamp. 1342 */ 1343 *(uint64_t *)m0->m_pktdat = 1344 be64toh(ctrl->u.last_flit) & 1345 0xfffffffffffffff; 1346 #endif 1347 1348 /* fall through */ 1349 1350 case X_RSPD_TYPE_CPL: 1351 KASSERT(rss->opcode < NUM_CPL_CMDS, 1352 ("%s: bad opcode %02x.", __func__, 1353 rss->opcode)); 1354 sc->cpl_handler[rss->opcode](iq, rss, m0); 1355 break; 1356 1357 case X_RSPD_TYPE_INTR: 1358 1359 /* 1360 * Interrupts should be forwarded only to queues 1361 * that are not forwarding their interrupts. 1362 * This means service_iq can recurse but only 1 1363 * level deep. 1364 */ 1365 KASSERT(budget == 0, 1366 ("%s: budget %u, rsp_type %u", __func__, 1367 budget, rsp_type)); 1368 1369 /* 1370 * There are 1K interrupt-capable queues (qids 0 1371 * through 1023). A response type indicating a 1372 * forwarded interrupt with a qid >= 1K is an 1373 * iWARP async notification. 1374 */ 1375 if (lq >= 1024) { 1376 sc->an_handler(iq, ctrl); 1377 break; 1378 } 1379 1380 q = sc->sge.iqmap[lq - sc->sge.iq_start]; 1381 if (atomic_cmpset_int(&q->state, IQS_IDLE, 1382 IQS_BUSY)) { 1383 if (service_iq(q, q->qsize / 8) == 0) { 1384 atomic_cmpset_int(&q->state, 1385 IQS_BUSY, IQS_IDLE); 1386 } else { 1387 STAILQ_INSERT_TAIL(&iql, q, 1388 link); 1389 } 1390 } 1391 break; 1392 1393 default: 1394 KASSERT(0, 1395 ("%s: illegal response type %d on iq %p", 1396 __func__, rsp_type, iq)); 1397 log(LOG_ERR, 1398 "%s: illegal response type %d on iq %p", 1399 device_get_nameunit(sc->dev), rsp_type, iq); 1400 break; 1401 } 1402 1403 if (fl_bufs_used >= 16) { 1404 FL_LOCK(fl); 1405 fl->needed += fl_bufs_used; 1406 refill_fl(sc, fl, 32); 1407 FL_UNLOCK(fl); 1408 fl_bufs_used = 0; 1409 } 1410 1411 iq_next(iq); 1412 if (++ndescs == limit) { 1413 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), 1414 V_CIDXINC(ndescs) | 1415 V_INGRESSQID(iq->cntxt_id) | 1416 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); 1417 ndescs = 0; 1418 1419 #if defined(INET) || defined(INET6) 1420 if (iq->flags & IQ_LRO_ENABLED && 1421 sc->lro_timeout != 0) { 1422 tcp_lro_flush_inactive(&rxq->lro, 1423 &lro_timeout); 1424 } 1425 #endif 1426 1427 if (budget) { 1428 if (fl_bufs_used) { 1429 FL_LOCK(fl); 1430 fl->needed += fl_bufs_used; 1431 refill_fl(sc, fl, 32); 1432 FL_UNLOCK(fl); 1433 } 1434 return (EINPROGRESS); 1435 } 1436 } 1437 } 1438 1439 process_iql: 1440 if (STAILQ_EMPTY(&iql)) 1441 break; 1442 1443 /* 1444 * Process the head only, and send it to the back of the list if 1445 * it's still not done. 1446 */ 1447 q = STAILQ_FIRST(&iql); 1448 STAILQ_REMOVE_HEAD(&iql, link); 1449 if (service_iq(q, q->qsize / 8) == 0) 1450 atomic_cmpset_int(&q->state, IQS_BUSY, IQS_IDLE); 1451 else 1452 STAILQ_INSERT_TAIL(&iql, q, link); 1453 } 1454 1455 #if defined(INET) || defined(INET6) 1456 if (iq->flags & IQ_LRO_ENABLED) { 1457 struct lro_ctrl *lro = &rxq->lro; 1458 struct lro_entry *l; 1459 1460 while (!SLIST_EMPTY(&lro->lro_active)) { 1461 l = SLIST_FIRST(&lro->lro_active); 1462 SLIST_REMOVE_HEAD(&lro->lro_active, next); 1463 tcp_lro_flush(lro, l); 1464 } 1465 } 1466 #endif 1467 1468 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), V_CIDXINC(ndescs) | 1469 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params)); 1470 1471 if (iq->flags & IQ_HAS_FL) { 1472 int starved; 1473 1474 FL_LOCK(fl); 1475 fl->needed += fl_bufs_used; 1476 starved = refill_fl(sc, fl, 64); 1477 FL_UNLOCK(fl); 1478 if (__predict_false(starved != 0)) 1479 add_fl_to_sfl(sc, fl); 1480 } 1481 1482 return (0); 1483 } 1484 1485 static inline int 1486 cl_has_metadata(struct sge_fl *fl, struct cluster_layout *cll) 1487 { 1488 int rc = fl->flags & FL_BUF_PACKING || cll->region1 > 0; 1489 1490 if (rc) 1491 MPASS(cll->region3 >= CL_METADATA_SIZE); 1492 1493 return (rc); 1494 } 1495 1496 static inline struct cluster_metadata * 1497 cl_metadata(struct adapter *sc, struct sge_fl *fl, struct cluster_layout *cll, 1498 caddr_t cl) 1499 { 1500 1501 if (cl_has_metadata(fl, cll)) { 1502 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx]; 1503 1504 return ((struct cluster_metadata *)(cl + swz->size) - 1); 1505 } 1506 return (NULL); 1507 } 1508 1509 static int 1510 rxb_free(struct mbuf *m, void *arg1, void *arg2) 1511 { 1512 uma_zone_t zone = arg1; 1513 caddr_t cl = arg2; 1514 1515 uma_zfree(zone, cl); 1516 1517 return (EXT_FREE_OK); 1518 } 1519 1520 /* 1521 * The mbuf returned by this function could be allocated from zone_mbuf or 1522 * constructed in spare room in the cluster. 1523 * 1524 * The mbuf carries the payload in one of these ways 1525 * a) frame inside the mbuf (mbuf from zone_mbuf) 1526 * b) m_cljset (for clusters without metadata) zone_mbuf 1527 * c) m_extaddref (cluster with metadata) inline mbuf 1528 * d) m_extaddref (cluster with metadata) zone_mbuf 1529 */ 1530 static struct mbuf * 1531 get_scatter_segment(struct adapter *sc, struct sge_fl *fl, int total, int flags) 1532 { 1533 struct mbuf *m; 1534 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 1535 struct cluster_layout *cll = &sd->cll; 1536 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx]; 1537 struct hw_buf_info *hwb = &sc->sge.hw_buf_info[cll->hwidx]; 1538 struct cluster_metadata *clm = cl_metadata(sc, fl, cll, sd->cl); 1539 int len, padded_len; 1540 caddr_t payload; 1541 1542 len = min(total, hwb->size - fl->rx_offset); 1543 padded_len = roundup2(len, fl_pad); 1544 payload = sd->cl + cll->region1 + fl->rx_offset; 1545 1546 if (sc->sc_do_rxcopy && len < RX_COPY_THRESHOLD) { 1547 1548 /* 1549 * Copy payload into a freshly allocated mbuf. 1550 */ 1551 1552 m = flags & M_PKTHDR ? 1553 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA); 1554 if (m == NULL) 1555 return (NULL); 1556 fl->mbuf_allocated++; 1557 #ifdef T4_PKT_TIMESTAMP 1558 /* Leave room for a timestamp */ 1559 m->m_data += 8; 1560 #endif 1561 /* copy data to mbuf */ 1562 bcopy(payload, mtod(m, caddr_t), len); 1563 1564 } else if (sd->nmbuf * MSIZE < cll->region1) { 1565 1566 /* 1567 * There's spare room in the cluster for an mbuf. Create one 1568 * and associate it with the payload that's in the cluster too. 1569 */ 1570 1571 MPASS(clm != NULL); 1572 m = (struct mbuf *)(sd->cl + sd->nmbuf * MSIZE); 1573 /* No bzero required */ 1574 if (m_init(m, NULL, 0, M_NOWAIT, MT_DATA, flags | M_NOFREE)) 1575 return (NULL); 1576 fl->mbuf_inlined++; 1577 m_extaddref(m, payload, padded_len, &clm->refcount, rxb_free, 1578 swz->zone, sd->cl); 1579 sd->nmbuf++; 1580 1581 } else { 1582 1583 /* 1584 * Grab an mbuf from zone_mbuf and associate it with the 1585 * payload in the cluster. 1586 */ 1587 1588 m = flags & M_PKTHDR ? 1589 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA); 1590 if (m == NULL) 1591 return (NULL); 1592 fl->mbuf_allocated++; 1593 if (clm != NULL) 1594 m_extaddref(m, payload, padded_len, &clm->refcount, 1595 rxb_free, swz->zone, sd->cl); 1596 else { 1597 m_cljset(m, sd->cl, swz->type); 1598 sd->cl = NULL; /* consumed, not a recycle candidate */ 1599 } 1600 } 1601 if (flags & M_PKTHDR) 1602 m->m_pkthdr.len = total; 1603 m->m_len = len; 1604 1605 if (fl->flags & FL_BUF_PACKING) { 1606 fl->rx_offset += roundup2(padded_len, sc->sge.pack_boundary); 1607 MPASS(fl->rx_offset <= hwb->size); 1608 if (fl->rx_offset < hwb->size) 1609 return (m); /* without advancing the cidx */ 1610 } 1611 1612 if (__predict_false(++fl->cidx == fl->cap)) 1613 fl->cidx = 0; 1614 fl->rx_offset = 0; 1615 1616 return (m); 1617 } 1618 1619 static struct mbuf * 1620 get_fl_payload(struct adapter *sc, struct sge_fl *fl, uint32_t len_newbuf, 1621 int *fl_bufs_used) 1622 { 1623 struct mbuf *m0, *m, **pnext; 1624 u_int nbuf, len; 1625 1626 /* 1627 * No assertion for the fl lock because we don't need it. This routine 1628 * is called only from the rx interrupt handler and it only updates 1629 * fl->cidx. (Contrast that with fl->pidx/fl->needed which could be 1630 * updated in the rx interrupt handler or the starvation helper routine. 1631 * That's why code that manipulates fl->pidx/fl->needed needs the fl 1632 * lock but this routine does not). 1633 */ 1634 1635 nbuf = 0; 1636 len = G_RSPD_LEN(len_newbuf); 1637 if (__predict_false(fl->m0 != NULL)) { 1638 M_ASSERTPKTHDR(fl->m0); 1639 MPASS(len == fl->m0->m_pkthdr.len); 1640 MPASS(fl->remaining < len); 1641 1642 m0 = fl->m0; 1643 pnext = fl->pnext; 1644 len = fl->remaining; 1645 fl->m0 = NULL; 1646 goto get_segment; 1647 } 1648 1649 if (fl->rx_offset > 0 && len_newbuf & F_RSPD_NEWBUF) { 1650 nbuf++; 1651 fl->rx_offset = 0; 1652 if (__predict_false(++fl->cidx == fl->cap)) 1653 fl->cidx = 0; 1654 } 1655 1656 /* 1657 * Payload starts at rx_offset in the current hw buffer. Its length is 1658 * 'len' and it may span multiple hw buffers. 1659 */ 1660 1661 m0 = get_scatter_segment(sc, fl, len, M_PKTHDR); 1662 if (m0 == NULL) 1663 goto done; 1664 len -= m0->m_len; 1665 pnext = &m0->m_next; 1666 while (len > 0) { 1667 nbuf++; 1668 get_segment: 1669 MPASS(fl->rx_offset == 0); 1670 m = get_scatter_segment(sc, fl, len, 0); 1671 if (m == NULL) { 1672 fl->m0 = m0; 1673 fl->pnext = pnext; 1674 fl->remaining = len; 1675 m0 = NULL; 1676 goto done; 1677 } 1678 *pnext = m; 1679 pnext = &m->m_next; 1680 len -= m->m_len; 1681 } 1682 *pnext = NULL; 1683 if (fl->rx_offset == 0) 1684 nbuf++; 1685 done: 1686 (*fl_bufs_used) += nbuf; 1687 return (m0); 1688 } 1689 1690 static int 1691 t4_eth_rx(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0) 1692 { 1693 struct sge_rxq *rxq = iq_to_rxq(iq); 1694 struct ifnet *ifp = rxq->ifp; 1695 const struct cpl_rx_pkt *cpl = (const void *)(rss + 1); 1696 #if defined(INET) || defined(INET6) 1697 struct lro_ctrl *lro = &rxq->lro; 1698 #endif 1699 1700 KASSERT(m0 != NULL, ("%s: no payload with opcode %02x", __func__, 1701 rss->opcode)); 1702 1703 m0->m_pkthdr.len -= fl_pktshift; 1704 m0->m_len -= fl_pktshift; 1705 m0->m_data += fl_pktshift; 1706 1707 m0->m_pkthdr.rcvif = ifp; 1708 m0->m_flags |= M_FLOWID; 1709 m0->m_pkthdr.flowid = be32toh(rss->hash_val); 1710 1711 if (cpl->csum_calc && !cpl->err_vec) { 1712 if (ifp->if_capenable & IFCAP_RXCSUM && 1713 cpl->l2info & htobe32(F_RXF_IP)) { 1714 m0->m_pkthdr.csum_flags = (CSUM_IP_CHECKED | 1715 CSUM_IP_VALID | CSUM_DATA_VALID | CSUM_PSEUDO_HDR); 1716 rxq->rxcsum++; 1717 } else if (ifp->if_capenable & IFCAP_RXCSUM_IPV6 && 1718 cpl->l2info & htobe32(F_RXF_IP6)) { 1719 m0->m_pkthdr.csum_flags = (CSUM_DATA_VALID_IPV6 | 1720 CSUM_PSEUDO_HDR); 1721 rxq->rxcsum++; 1722 } 1723 1724 if (__predict_false(cpl->ip_frag)) 1725 m0->m_pkthdr.csum_data = be16toh(cpl->csum); 1726 else 1727 m0->m_pkthdr.csum_data = 0xffff; 1728 } 1729 1730 if (cpl->vlan_ex) { 1731 m0->m_pkthdr.ether_vtag = be16toh(cpl->vlan); 1732 m0->m_flags |= M_VLANTAG; 1733 rxq->vlan_extraction++; 1734 } 1735 1736 #if defined(INET) || defined(INET6) 1737 if (cpl->l2info & htobe32(F_RXF_LRO) && 1738 iq->flags & IQ_LRO_ENABLED && 1739 tcp_lro_rx(lro, m0, 0) == 0) { 1740 /* queued for LRO */ 1741 } else 1742 #endif 1743 ifp->if_input(ifp, m0); 1744 1745 return (0); 1746 } 1747 1748 /* 1749 * Doesn't fail. Holds on to work requests it can't send right away. 1750 */ 1751 void 1752 t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, struct wrqe *wr) 1753 { 1754 struct sge_eq *eq = &wrq->eq; 1755 int can_reclaim; 1756 caddr_t dst; 1757 1758 TXQ_LOCK_ASSERT_OWNED(wrq); 1759 #ifdef TCP_OFFLOAD 1760 KASSERT((eq->flags & EQ_TYPEMASK) == EQ_OFLD || 1761 (eq->flags & EQ_TYPEMASK) == EQ_CTRL, 1762 ("%s: eq type %d", __func__, eq->flags & EQ_TYPEMASK)); 1763 #else 1764 KASSERT((eq->flags & EQ_TYPEMASK) == EQ_CTRL, 1765 ("%s: eq type %d", __func__, eq->flags & EQ_TYPEMASK)); 1766 #endif 1767 1768 if (__predict_true(wr != NULL)) 1769 STAILQ_INSERT_TAIL(&wrq->wr_list, wr, link); 1770 1771 can_reclaim = reclaimable(eq); 1772 if (__predict_false(eq->flags & EQ_STALLED)) { 1773 if (can_reclaim < tx_resume_threshold(eq)) 1774 return; 1775 eq->flags &= ~EQ_STALLED; 1776 eq->unstalled++; 1777 } 1778 eq->cidx += can_reclaim; 1779 eq->avail += can_reclaim; 1780 if (__predict_false(eq->cidx >= eq->cap)) 1781 eq->cidx -= eq->cap; 1782 1783 while ((wr = STAILQ_FIRST(&wrq->wr_list)) != NULL) { 1784 int ndesc; 1785 1786 if (__predict_false(wr->wr_len < 0 || 1787 wr->wr_len > SGE_MAX_WR_LEN || (wr->wr_len & 0x7))) { 1788 1789 #ifdef INVARIANTS 1790 panic("%s: work request with length %d", __func__, 1791 wr->wr_len); 1792 #endif 1793 #ifdef KDB 1794 kdb_backtrace(); 1795 #endif 1796 log(LOG_ERR, "%s: %s work request with length %d", 1797 device_get_nameunit(sc->dev), __func__, wr->wr_len); 1798 STAILQ_REMOVE_HEAD(&wrq->wr_list, link); 1799 free_wrqe(wr); 1800 continue; 1801 } 1802 1803 ndesc = howmany(wr->wr_len, EQ_ESIZE); 1804 if (eq->avail < ndesc) { 1805 wrq->no_desc++; 1806 break; 1807 } 1808 1809 dst = (void *)&eq->desc[eq->pidx]; 1810 copy_to_txd(eq, wrtod(wr), &dst, wr->wr_len); 1811 1812 eq->pidx += ndesc; 1813 eq->avail -= ndesc; 1814 if (__predict_false(eq->pidx >= eq->cap)) 1815 eq->pidx -= eq->cap; 1816 1817 eq->pending += ndesc; 1818 if (eq->pending >= 8) 1819 ring_eq_db(sc, eq); 1820 1821 wrq->tx_wrs++; 1822 STAILQ_REMOVE_HEAD(&wrq->wr_list, link); 1823 free_wrqe(wr); 1824 1825 if (eq->avail < 8) { 1826 can_reclaim = reclaimable(eq); 1827 eq->cidx += can_reclaim; 1828 eq->avail += can_reclaim; 1829 if (__predict_false(eq->cidx >= eq->cap)) 1830 eq->cidx -= eq->cap; 1831 } 1832 } 1833 1834 if (eq->pending) 1835 ring_eq_db(sc, eq); 1836 1837 if (wr != NULL) { 1838 eq->flags |= EQ_STALLED; 1839 if (callout_pending(&eq->tx_callout) == 0) 1840 callout_reset(&eq->tx_callout, 1, t4_tx_callout, eq); 1841 } 1842 } 1843 1844 /* Per-packet header in a coalesced tx WR, before the SGL starts (in flits) */ 1845 #define TXPKTS_PKT_HDR ((\ 1846 sizeof(struct ulp_txpkt) + \ 1847 sizeof(struct ulptx_idata) + \ 1848 sizeof(struct cpl_tx_pkt_core) \ 1849 ) / 8) 1850 1851 /* Header of a coalesced tx WR, before SGL of first packet (in flits) */ 1852 #define TXPKTS_WR_HDR (\ 1853 sizeof(struct fw_eth_tx_pkts_wr) / 8 + \ 1854 TXPKTS_PKT_HDR) 1855 1856 /* Header of a tx WR, before SGL of first packet (in flits) */ 1857 #define TXPKT_WR_HDR ((\ 1858 sizeof(struct fw_eth_tx_pkt_wr) + \ 1859 sizeof(struct cpl_tx_pkt_core) \ 1860 ) / 8 ) 1861 1862 /* Header of a tx LSO WR, before SGL of first packet (in flits) */ 1863 #define TXPKT_LSO_WR_HDR ((\ 1864 sizeof(struct fw_eth_tx_pkt_wr) + \ 1865 sizeof(struct cpl_tx_pkt_lso_core) + \ 1866 sizeof(struct cpl_tx_pkt_core) \ 1867 ) / 8 ) 1868 1869 int 1870 t4_eth_tx(struct ifnet *ifp, struct sge_txq *txq, struct mbuf *m) 1871 { 1872 struct port_info *pi = (void *)ifp->if_softc; 1873 struct adapter *sc = pi->adapter; 1874 struct sge_eq *eq = &txq->eq; 1875 struct buf_ring *br = txq->br; 1876 struct mbuf *next; 1877 int rc, coalescing, can_reclaim; 1878 struct txpkts txpkts; 1879 struct sgl sgl; 1880 1881 TXQ_LOCK_ASSERT_OWNED(txq); 1882 KASSERT(m, ("%s: called with nothing to do.", __func__)); 1883 KASSERT((eq->flags & EQ_TYPEMASK) == EQ_ETH, 1884 ("%s: eq type %d", __func__, eq->flags & EQ_TYPEMASK)); 1885 1886 prefetch(&eq->desc[eq->pidx]); 1887 prefetch(&txq->sdesc[eq->pidx]); 1888 1889 txpkts.npkt = 0;/* indicates there's nothing in txpkts */ 1890 coalescing = 0; 1891 1892 can_reclaim = reclaimable(eq); 1893 if (__predict_false(eq->flags & EQ_STALLED)) { 1894 if (can_reclaim < tx_resume_threshold(eq)) { 1895 txq->m = m; 1896 return (0); 1897 } 1898 eq->flags &= ~EQ_STALLED; 1899 eq->unstalled++; 1900 } 1901 1902 if (__predict_false(eq->flags & EQ_DOOMED)) { 1903 m_freem(m); 1904 while ((m = buf_ring_dequeue_sc(txq->br)) != NULL) 1905 m_freem(m); 1906 return (ENETDOWN); 1907 } 1908 1909 if (eq->avail < 8 && can_reclaim) 1910 reclaim_tx_descs(txq, can_reclaim, 32); 1911 1912 for (; m; m = next ? next : drbr_dequeue(ifp, br)) { 1913 1914 if (eq->avail < 8) 1915 break; 1916 1917 next = m->m_nextpkt; 1918 m->m_nextpkt = NULL; 1919 1920 if (next || buf_ring_peek(br)) 1921 coalescing = 1; 1922 1923 rc = get_pkt_sgl(txq, &m, &sgl, coalescing); 1924 if (rc != 0) { 1925 if (rc == ENOMEM) { 1926 1927 /* Short of resources, suspend tx */ 1928 1929 m->m_nextpkt = next; 1930 break; 1931 } 1932 1933 /* 1934 * Unrecoverable error for this packet, throw it away 1935 * and move on to the next. get_pkt_sgl may already 1936 * have freed m (it will be NULL in that case and the 1937 * m_freem here is still safe). 1938 */ 1939 1940 m_freem(m); 1941 continue; 1942 } 1943 1944 if (coalescing && 1945 add_to_txpkts(pi, txq, &txpkts, m, &sgl) == 0) { 1946 1947 /* Successfully absorbed into txpkts */ 1948 1949 write_ulp_cpl_sgl(pi, txq, &txpkts, m, &sgl); 1950 goto doorbell; 1951 } 1952 1953 /* 1954 * We weren't coalescing to begin with, or current frame could 1955 * not be coalesced (add_to_txpkts flushes txpkts if a frame 1956 * given to it can't be coalesced). Either way there should be 1957 * nothing in txpkts. 1958 */ 1959 KASSERT(txpkts.npkt == 0, 1960 ("%s: txpkts not empty: %d", __func__, txpkts.npkt)); 1961 1962 /* We're sending out individual packets now */ 1963 coalescing = 0; 1964 1965 if (eq->avail < 8) 1966 reclaim_tx_descs(txq, 0, 8); 1967 rc = write_txpkt_wr(pi, txq, m, &sgl); 1968 if (rc != 0) { 1969 1970 /* Short of hardware descriptors, suspend tx */ 1971 1972 /* 1973 * This is an unlikely but expensive failure. We've 1974 * done all the hard work (DMA mappings etc.) and now we 1975 * can't send out the packet. What's worse, we have to 1976 * spend even more time freeing up everything in sgl. 1977 */ 1978 txq->no_desc++; 1979 free_pkt_sgl(txq, &sgl); 1980 1981 m->m_nextpkt = next; 1982 break; 1983 } 1984 1985 ETHER_BPF_MTAP(ifp, m); 1986 if (sgl.nsegs == 0) 1987 m_freem(m); 1988 doorbell: 1989 if (eq->pending >= 8) 1990 ring_eq_db(sc, eq); 1991 1992 can_reclaim = reclaimable(eq); 1993 if (can_reclaim >= 32) 1994 reclaim_tx_descs(txq, can_reclaim, 64); 1995 } 1996 1997 if (txpkts.npkt > 0) 1998 write_txpkts_wr(txq, &txpkts); 1999 2000 /* 2001 * m not NULL means there was an error but we haven't thrown it away. 2002 * This can happen when we're short of tx descriptors (no_desc) or maybe 2003 * even DMA maps (no_dmamap). Either way, a credit flush and reclaim 2004 * will get things going again. 2005 */ 2006 if (m && !(eq->flags & EQ_CRFLUSHED)) { 2007 struct tx_sdesc *txsd = &txq->sdesc[eq->pidx]; 2008 2009 /* 2010 * If EQ_CRFLUSHED is not set then we know we have at least one 2011 * available descriptor because any WR that reduces eq->avail to 2012 * 0 also sets EQ_CRFLUSHED. 2013 */ 2014 KASSERT(eq->avail > 0, ("%s: no space for eqflush.", __func__)); 2015 2016 txsd->desc_used = 1; 2017 txsd->credits = 0; 2018 write_eqflush_wr(eq); 2019 } 2020 txq->m = m; 2021 2022 if (eq->pending) 2023 ring_eq_db(sc, eq); 2024 2025 reclaim_tx_descs(txq, 0, 128); 2026 2027 if (eq->flags & EQ_STALLED && callout_pending(&eq->tx_callout) == 0) 2028 callout_reset(&eq->tx_callout, 1, t4_tx_callout, eq); 2029 2030 return (0); 2031 } 2032 2033 void 2034 t4_update_fl_bufsize(struct ifnet *ifp) 2035 { 2036 struct port_info *pi = ifp->if_softc; 2037 struct adapter *sc = pi->adapter; 2038 struct sge_rxq *rxq; 2039 #ifdef TCP_OFFLOAD 2040 struct sge_ofld_rxq *ofld_rxq; 2041 #endif 2042 struct sge_fl *fl; 2043 int i, maxp, mtu = ifp->if_mtu; 2044 2045 maxp = mtu_to_max_payload(sc, mtu, 0); 2046 for_each_rxq(pi, i, rxq) { 2047 fl = &rxq->fl; 2048 2049 FL_LOCK(fl); 2050 find_best_refill_source(sc, fl, maxp); 2051 FL_UNLOCK(fl); 2052 } 2053 #ifdef TCP_OFFLOAD 2054 maxp = mtu_to_max_payload(sc, mtu, 1); 2055 for_each_ofld_rxq(pi, i, ofld_rxq) { 2056 fl = &ofld_rxq->fl; 2057 2058 FL_LOCK(fl); 2059 find_best_refill_source(sc, fl, maxp); 2060 FL_UNLOCK(fl); 2061 } 2062 #endif 2063 } 2064 2065 int 2066 can_resume_tx(struct sge_eq *eq) 2067 { 2068 return (reclaimable(eq) >= tx_resume_threshold(eq)); 2069 } 2070 2071 static inline void 2072 init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int pktc_idx, 2073 int qsize, int esize) 2074 { 2075 KASSERT(tmr_idx >= 0 && tmr_idx < SGE_NTIMERS, 2076 ("%s: bad tmr_idx %d", __func__, tmr_idx)); 2077 KASSERT(pktc_idx < SGE_NCOUNTERS, /* -ve is ok, means don't use */ 2078 ("%s: bad pktc_idx %d", __func__, pktc_idx)); 2079 2080 iq->flags = 0; 2081 iq->adapter = sc; 2082 iq->intr_params = V_QINTR_TIMER_IDX(tmr_idx); 2083 iq->intr_pktc_idx = SGE_NCOUNTERS - 1; 2084 if (pktc_idx >= 0) { 2085 iq->intr_params |= F_QINTR_CNT_EN; 2086 iq->intr_pktc_idx = pktc_idx; 2087 } 2088 iq->qsize = roundup2(qsize, 16); /* See FW_IQ_CMD/iqsize */ 2089 iq->esize = max(esize, 16); /* See FW_IQ_CMD/iqesize */ 2090 } 2091 2092 static inline void 2093 init_fl(struct adapter *sc, struct sge_fl *fl, int qsize, int maxp, int pack, 2094 char *name) 2095 { 2096 2097 fl->qsize = qsize; 2098 strlcpy(fl->lockname, name, sizeof(fl->lockname)); 2099 if (pack) 2100 fl->flags |= FL_BUF_PACKING; 2101 find_best_refill_source(sc, fl, maxp); 2102 find_safe_refill_source(sc, fl); 2103 } 2104 2105 static inline void 2106 init_eq(struct sge_eq *eq, int eqtype, int qsize, uint8_t tx_chan, 2107 uint16_t iqid, char *name) 2108 { 2109 KASSERT(tx_chan < NCHAN, ("%s: bad tx channel %d", __func__, tx_chan)); 2110 KASSERT(eqtype <= EQ_TYPEMASK, ("%s: bad qtype %d", __func__, eqtype)); 2111 2112 eq->flags = eqtype & EQ_TYPEMASK; 2113 eq->tx_chan = tx_chan; 2114 eq->iqid = iqid; 2115 eq->qsize = qsize; 2116 strlcpy(eq->lockname, name, sizeof(eq->lockname)); 2117 2118 TASK_INIT(&eq->tx_task, 0, t4_tx_task, eq); 2119 callout_init(&eq->tx_callout, CALLOUT_MPSAFE); 2120 } 2121 2122 static int 2123 alloc_ring(struct adapter *sc, size_t len, bus_dma_tag_t *tag, 2124 bus_dmamap_t *map, bus_addr_t *pa, void **va) 2125 { 2126 int rc; 2127 2128 rc = bus_dma_tag_create(sc->dmat, 512, 0, BUS_SPACE_MAXADDR, 2129 BUS_SPACE_MAXADDR, NULL, NULL, len, 1, len, 0, NULL, NULL, tag); 2130 if (rc != 0) { 2131 device_printf(sc->dev, "cannot allocate DMA tag: %d\n", rc); 2132 goto done; 2133 } 2134 2135 rc = bus_dmamem_alloc(*tag, va, 2136 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, map); 2137 if (rc != 0) { 2138 device_printf(sc->dev, "cannot allocate DMA memory: %d\n", rc); 2139 goto done; 2140 } 2141 2142 rc = bus_dmamap_load(*tag, *map, *va, len, oneseg_dma_callback, pa, 0); 2143 if (rc != 0) { 2144 device_printf(sc->dev, "cannot load DMA map: %d\n", rc); 2145 goto done; 2146 } 2147 done: 2148 if (rc) 2149 free_ring(sc, *tag, *map, *pa, *va); 2150 2151 return (rc); 2152 } 2153 2154 static int 2155 free_ring(struct adapter *sc, bus_dma_tag_t tag, bus_dmamap_t map, 2156 bus_addr_t pa, void *va) 2157 { 2158 if (pa) 2159 bus_dmamap_unload(tag, map); 2160 if (va) 2161 bus_dmamem_free(tag, va, map); 2162 if (tag) 2163 bus_dma_tag_destroy(tag); 2164 2165 return (0); 2166 } 2167 2168 /* 2169 * Allocates the ring for an ingress queue and an optional freelist. If the 2170 * freelist is specified it will be allocated and then associated with the 2171 * ingress queue. 2172 * 2173 * Returns errno on failure. Resources allocated up to that point may still be 2174 * allocated. Caller is responsible for cleanup in case this function fails. 2175 * 2176 * If the ingress queue will take interrupts directly (iq->flags & IQ_INTR) then 2177 * the intr_idx specifies the vector, starting from 0. Otherwise it specifies 2178 * the abs_id of the ingress queue to which its interrupts should be forwarded. 2179 */ 2180 static int 2181 alloc_iq_fl(struct port_info *pi, struct sge_iq *iq, struct sge_fl *fl, 2182 int intr_idx, int cong) 2183 { 2184 int rc, i, cntxt_id; 2185 size_t len; 2186 struct fw_iq_cmd c; 2187 struct adapter *sc = iq->adapter; 2188 __be32 v = 0; 2189 2190 len = iq->qsize * iq->esize; 2191 rc = alloc_ring(sc, len, &iq->desc_tag, &iq->desc_map, &iq->ba, 2192 (void **)&iq->desc); 2193 if (rc != 0) 2194 return (rc); 2195 2196 bzero(&c, sizeof(c)); 2197 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 2198 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) | 2199 V_FW_IQ_CMD_VFN(0)); 2200 2201 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART | 2202 FW_LEN16(c)); 2203 2204 /* Special handling for firmware event queue */ 2205 if (iq == &sc->sge.fwq) 2206 v |= F_FW_IQ_CMD_IQASYNCH; 2207 2208 if (iq->flags & IQ_INTR) { 2209 KASSERT(intr_idx < sc->intr_count, 2210 ("%s: invalid direct intr_idx %d", __func__, intr_idx)); 2211 } else 2212 v |= F_FW_IQ_CMD_IQANDST; 2213 v |= V_FW_IQ_CMD_IQANDSTINDEX(intr_idx); 2214 2215 c.type_to_iqandstindex = htobe32(v | 2216 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) | 2217 V_FW_IQ_CMD_VIID(pi->viid) | 2218 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT)); 2219 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->tx_chan) | 2220 F_FW_IQ_CMD_IQGTSMODE | 2221 V_FW_IQ_CMD_IQINTCNTTHRESH(iq->intr_pktc_idx) | 2222 V_FW_IQ_CMD_IQESIZE(ilog2(iq->esize) - 4)); 2223 c.iqsize = htobe16(iq->qsize); 2224 c.iqaddr = htobe64(iq->ba); 2225 if (cong >= 0) 2226 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN); 2227 2228 if (fl) { 2229 mtx_init(&fl->fl_lock, fl->lockname, NULL, MTX_DEF); 2230 2231 len = fl->qsize * RX_FL_ESIZE; 2232 rc = alloc_ring(sc, len, &fl->desc_tag, &fl->desc_map, 2233 &fl->ba, (void **)&fl->desc); 2234 if (rc) 2235 return (rc); 2236 2237 /* Allocate space for one software descriptor per buffer. */ 2238 fl->cap = (fl->qsize - spg_len / RX_FL_ESIZE) * 8; 2239 rc = alloc_fl_sdesc(fl); 2240 if (rc != 0) { 2241 device_printf(sc->dev, 2242 "failed to setup fl software descriptors: %d\n", 2243 rc); 2244 return (rc); 2245 } 2246 fl->needed = fl->cap; 2247 fl->lowat = fl->flags & FL_BUF_PACKING ? 2248 roundup2(sc->sge.fl_starve_threshold2, 8) : 2249 roundup2(sc->sge.fl_starve_threshold, 8); 2250 2251 c.iqns_to_fl0congen |= 2252 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) | 2253 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO | 2254 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) | 2255 (fl->flags & FL_BUF_PACKING ? F_FW_IQ_CMD_FL0PACKEN : 2256 0)); 2257 if (cong >= 0) { 2258 c.iqns_to_fl0congen |= 2259 htobe32(V_FW_IQ_CMD_FL0CNGCHMAP(cong) | 2260 F_FW_IQ_CMD_FL0CONGCIF | 2261 F_FW_IQ_CMD_FL0CONGEN); 2262 } 2263 c.fl0dcaen_to_fl0cidxfthresh = 2264 htobe16(V_FW_IQ_CMD_FL0FBMIN(X_FETCHBURSTMIN_64B) | 2265 V_FW_IQ_CMD_FL0FBMAX(X_FETCHBURSTMAX_512B)); 2266 c.fl0size = htobe16(fl->qsize); 2267 c.fl0addr = htobe64(fl->ba); 2268 } 2269 2270 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 2271 if (rc != 0) { 2272 device_printf(sc->dev, 2273 "failed to create ingress queue: %d\n", rc); 2274 return (rc); 2275 } 2276 2277 iq->cdesc = iq->desc; 2278 iq->cidx = 0; 2279 iq->gen = 1; 2280 iq->intr_next = iq->intr_params; 2281 iq->cntxt_id = be16toh(c.iqid); 2282 iq->abs_id = be16toh(c.physiqid); 2283 iq->flags |= IQ_ALLOCATED; 2284 2285 cntxt_id = iq->cntxt_id - sc->sge.iq_start; 2286 if (cntxt_id >= sc->sge.niq) { 2287 panic ("%s: iq->cntxt_id (%d) more than the max (%d)", __func__, 2288 cntxt_id, sc->sge.niq - 1); 2289 } 2290 sc->sge.iqmap[cntxt_id] = iq; 2291 2292 if (fl) { 2293 fl->cntxt_id = be16toh(c.fl0id); 2294 fl->pidx = fl->cidx = 0; 2295 2296 cntxt_id = fl->cntxt_id - sc->sge.eq_start; 2297 if (cntxt_id >= sc->sge.neq) { 2298 panic("%s: fl->cntxt_id (%d) more than the max (%d)", 2299 __func__, cntxt_id, sc->sge.neq - 1); 2300 } 2301 sc->sge.eqmap[cntxt_id] = (void *)fl; 2302 2303 FL_LOCK(fl); 2304 /* Enough to make sure the SGE doesn't think it's starved */ 2305 refill_fl(sc, fl, fl->lowat); 2306 FL_UNLOCK(fl); 2307 2308 iq->flags |= IQ_HAS_FL; 2309 } 2310 2311 if (is_t5(sc) && cong >= 0) { 2312 uint32_t param, val; 2313 2314 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 2315 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) | 2316 V_FW_PARAMS_PARAM_YZ(iq->cntxt_id); 2317 if (cong == 0) 2318 val = 1 << 19; 2319 else { 2320 val = 2 << 19; 2321 for (i = 0; i < 4; i++) { 2322 if (cong & (1 << i)) 2323 val |= 1 << (i << 2); 2324 } 2325 } 2326 2327 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 2328 if (rc != 0) { 2329 /* report error but carry on */ 2330 device_printf(sc->dev, 2331 "failed to set congestion manager context for " 2332 "ingress queue %d: %d\n", iq->cntxt_id, rc); 2333 } 2334 } 2335 2336 /* Enable IQ interrupts */ 2337 atomic_store_rel_int(&iq->state, IQS_IDLE); 2338 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), V_SEINTARM(iq->intr_params) | 2339 V_INGRESSQID(iq->cntxt_id)); 2340 2341 return (0); 2342 } 2343 2344 static int 2345 free_iq_fl(struct port_info *pi, struct sge_iq *iq, struct sge_fl *fl) 2346 { 2347 int rc; 2348 struct adapter *sc = iq->adapter; 2349 device_t dev; 2350 2351 if (sc == NULL) 2352 return (0); /* nothing to do */ 2353 2354 dev = pi ? pi->dev : sc->dev; 2355 2356 if (iq->flags & IQ_ALLOCATED) { 2357 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0, 2358 FW_IQ_TYPE_FL_INT_CAP, iq->cntxt_id, 2359 fl ? fl->cntxt_id : 0xffff, 0xffff); 2360 if (rc != 0) { 2361 device_printf(dev, 2362 "failed to free queue %p: %d\n", iq, rc); 2363 return (rc); 2364 } 2365 iq->flags &= ~IQ_ALLOCATED; 2366 } 2367 2368 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, iq->desc); 2369 2370 bzero(iq, sizeof(*iq)); 2371 2372 if (fl) { 2373 free_ring(sc, fl->desc_tag, fl->desc_map, fl->ba, 2374 fl->desc); 2375 2376 if (fl->sdesc) 2377 free_fl_sdesc(sc, fl); 2378 2379 if (mtx_initialized(&fl->fl_lock)) 2380 mtx_destroy(&fl->fl_lock); 2381 2382 bzero(fl, sizeof(*fl)); 2383 } 2384 2385 return (0); 2386 } 2387 2388 static void 2389 add_fl_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid, 2390 struct sge_fl *fl) 2391 { 2392 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 2393 2394 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL, 2395 "freelist"); 2396 children = SYSCTL_CHILDREN(oid); 2397 2398 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 2399 CTLTYPE_INT | CTLFLAG_RD, &fl->cntxt_id, 0, sysctl_uint16, "I", 2400 "SGE context id of the freelist"); 2401 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &fl->cidx, 2402 0, "consumer index"); 2403 if (fl->flags & FL_BUF_PACKING) { 2404 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rx_offset", 2405 CTLFLAG_RD, &fl->rx_offset, 0, "packing rx offset"); 2406 } 2407 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &fl->pidx, 2408 0, "producer index"); 2409 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_allocated", 2410 CTLFLAG_RD, &fl->mbuf_allocated, "# of mbuf allocated"); 2411 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_inlined", 2412 CTLFLAG_RD, &fl->mbuf_inlined, "# of mbuf inlined in clusters"); 2413 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_allocated", 2414 CTLFLAG_RD, &fl->cl_allocated, "# of clusters allocated"); 2415 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_recycled", 2416 CTLFLAG_RD, &fl->cl_recycled, "# of clusters recycled"); 2417 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_fast_recycled", 2418 CTLFLAG_RD, &fl->cl_fast_recycled, "# of clusters recycled (fast)"); 2419 } 2420 2421 static int 2422 alloc_fwq(struct adapter *sc) 2423 { 2424 int rc, intr_idx; 2425 struct sge_iq *fwq = &sc->sge.fwq; 2426 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev); 2427 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 2428 2429 init_iq(fwq, sc, 0, 0, FW_IQ_QSIZE, FW_IQ_ESIZE); 2430 fwq->flags |= IQ_INTR; /* always */ 2431 intr_idx = sc->intr_count > 1 ? 1 : 0; 2432 rc = alloc_iq_fl(sc->port[0], fwq, NULL, intr_idx, -1); 2433 if (rc != 0) { 2434 device_printf(sc->dev, 2435 "failed to create firmware event queue: %d\n", rc); 2436 return (rc); 2437 } 2438 2439 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "fwq", CTLFLAG_RD, 2440 NULL, "firmware event queue"); 2441 children = SYSCTL_CHILDREN(oid); 2442 2443 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "abs_id", 2444 CTLTYPE_INT | CTLFLAG_RD, &fwq->abs_id, 0, sysctl_uint16, "I", 2445 "absolute id of the queue"); 2446 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "cntxt_id", 2447 CTLTYPE_INT | CTLFLAG_RD, &fwq->cntxt_id, 0, sysctl_uint16, "I", 2448 "SGE context id of the queue"); 2449 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "cidx", 2450 CTLTYPE_INT | CTLFLAG_RD, &fwq->cidx, 0, sysctl_uint16, "I", 2451 "consumer index"); 2452 2453 return (0); 2454 } 2455 2456 static int 2457 free_fwq(struct adapter *sc) 2458 { 2459 return free_iq_fl(NULL, &sc->sge.fwq, NULL); 2460 } 2461 2462 static int 2463 alloc_mgmtq(struct adapter *sc) 2464 { 2465 int rc; 2466 struct sge_wrq *mgmtq = &sc->sge.mgmtq; 2467 char name[16]; 2468 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev); 2469 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 2470 2471 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "mgmtq", CTLFLAG_RD, 2472 NULL, "management queue"); 2473 2474 snprintf(name, sizeof(name), "%s mgmtq", device_get_nameunit(sc->dev)); 2475 init_eq(&mgmtq->eq, EQ_CTRL, CTRL_EQ_QSIZE, sc->port[0]->tx_chan, 2476 sc->sge.fwq.cntxt_id, name); 2477 rc = alloc_wrq(sc, NULL, mgmtq, oid); 2478 if (rc != 0) { 2479 device_printf(sc->dev, 2480 "failed to create management queue: %d\n", rc); 2481 return (rc); 2482 } 2483 2484 return (0); 2485 } 2486 2487 static int 2488 free_mgmtq(struct adapter *sc) 2489 { 2490 2491 return free_wrq(sc, &sc->sge.mgmtq); 2492 } 2493 2494 static inline int 2495 tnl_cong(struct port_info *pi) 2496 { 2497 2498 if (cong_drop == -1) 2499 return (-1); 2500 else if (cong_drop == 1) 2501 return (0); 2502 else 2503 return (pi->rx_chan_map); 2504 } 2505 2506 static int 2507 alloc_rxq(struct port_info *pi, struct sge_rxq *rxq, int intr_idx, int idx, 2508 struct sysctl_oid *oid) 2509 { 2510 int rc; 2511 struct sysctl_oid_list *children; 2512 char name[16]; 2513 2514 rc = alloc_iq_fl(pi, &rxq->iq, &rxq->fl, intr_idx, tnl_cong(pi)); 2515 if (rc != 0) 2516 return (rc); 2517 2518 FL_LOCK(&rxq->fl); 2519 refill_fl(pi->adapter, &rxq->fl, rxq->fl.needed / 8); 2520 FL_UNLOCK(&rxq->fl); 2521 2522 #if defined(INET) || defined(INET6) 2523 rc = tcp_lro_init(&rxq->lro); 2524 if (rc != 0) 2525 return (rc); 2526 rxq->lro.ifp = pi->ifp; /* also indicates LRO init'ed */ 2527 2528 if (pi->ifp->if_capenable & IFCAP_LRO) 2529 rxq->iq.flags |= IQ_LRO_ENABLED; 2530 #endif 2531 rxq->ifp = pi->ifp; 2532 2533 children = SYSCTL_CHILDREN(oid); 2534 2535 snprintf(name, sizeof(name), "%d", idx); 2536 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 2537 NULL, "rx queue"); 2538 children = SYSCTL_CHILDREN(oid); 2539 2540 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "abs_id", 2541 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.abs_id, 0, sysctl_uint16, "I", 2542 "absolute id of the queue"); 2543 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cntxt_id", 2544 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.cntxt_id, 0, sysctl_uint16, "I", 2545 "SGE context id of the queue"); 2546 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cidx", 2547 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.cidx, 0, sysctl_uint16, "I", 2548 "consumer index"); 2549 #if defined(INET) || defined(INET6) 2550 SYSCTL_ADD_INT(&pi->ctx, children, OID_AUTO, "lro_queued", CTLFLAG_RD, 2551 &rxq->lro.lro_queued, 0, NULL); 2552 SYSCTL_ADD_INT(&pi->ctx, children, OID_AUTO, "lro_flushed", CTLFLAG_RD, 2553 &rxq->lro.lro_flushed, 0, NULL); 2554 #endif 2555 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "rxcsum", CTLFLAG_RD, 2556 &rxq->rxcsum, "# of times hardware assisted with checksum"); 2557 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "vlan_extraction", 2558 CTLFLAG_RD, &rxq->vlan_extraction, 2559 "# of times hardware extracted 802.1Q tag"); 2560 2561 add_fl_sysctls(&pi->ctx, oid, &rxq->fl); 2562 2563 return (rc); 2564 } 2565 2566 static int 2567 free_rxq(struct port_info *pi, struct sge_rxq *rxq) 2568 { 2569 int rc; 2570 2571 #if defined(INET) || defined(INET6) 2572 if (rxq->lro.ifp) { 2573 tcp_lro_free(&rxq->lro); 2574 rxq->lro.ifp = NULL; 2575 } 2576 #endif 2577 2578 rc = free_iq_fl(pi, &rxq->iq, &rxq->fl); 2579 if (rc == 0) 2580 bzero(rxq, sizeof(*rxq)); 2581 2582 return (rc); 2583 } 2584 2585 #ifdef TCP_OFFLOAD 2586 static int 2587 alloc_ofld_rxq(struct port_info *pi, struct sge_ofld_rxq *ofld_rxq, 2588 int intr_idx, int idx, struct sysctl_oid *oid) 2589 { 2590 int rc; 2591 struct sysctl_oid_list *children; 2592 char name[16]; 2593 2594 rc = alloc_iq_fl(pi, &ofld_rxq->iq, &ofld_rxq->fl, intr_idx, 2595 pi->rx_chan_map); 2596 if (rc != 0) 2597 return (rc); 2598 2599 children = SYSCTL_CHILDREN(oid); 2600 2601 snprintf(name, sizeof(name), "%d", idx); 2602 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 2603 NULL, "rx queue"); 2604 children = SYSCTL_CHILDREN(oid); 2605 2606 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "abs_id", 2607 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.abs_id, 0, sysctl_uint16, 2608 "I", "absolute id of the queue"); 2609 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cntxt_id", 2610 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.cntxt_id, 0, sysctl_uint16, 2611 "I", "SGE context id of the queue"); 2612 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cidx", 2613 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.cidx, 0, sysctl_uint16, "I", 2614 "consumer index"); 2615 2616 add_fl_sysctls(&pi->ctx, oid, &ofld_rxq->fl); 2617 2618 return (rc); 2619 } 2620 2621 static int 2622 free_ofld_rxq(struct port_info *pi, struct sge_ofld_rxq *ofld_rxq) 2623 { 2624 int rc; 2625 2626 rc = free_iq_fl(pi, &ofld_rxq->iq, &ofld_rxq->fl); 2627 if (rc == 0) 2628 bzero(ofld_rxq, sizeof(*ofld_rxq)); 2629 2630 return (rc); 2631 } 2632 #endif 2633 2634 #ifdef DEV_NETMAP 2635 static int 2636 alloc_nm_rxq(struct port_info *pi, struct sge_nm_rxq *nm_rxq, int intr_idx, 2637 int idx, struct sysctl_oid *oid) 2638 { 2639 int rc; 2640 struct sysctl_oid_list *children; 2641 struct sysctl_ctx_list *ctx; 2642 char name[16]; 2643 size_t len; 2644 struct adapter *sc = pi->adapter; 2645 struct netmap_adapter *na = NA(pi->nm_ifp); 2646 2647 MPASS(na != NULL); 2648 2649 len = pi->qsize_rxq * RX_IQ_ESIZE; 2650 rc = alloc_ring(sc, len, &nm_rxq->iq_desc_tag, &nm_rxq->iq_desc_map, 2651 &nm_rxq->iq_ba, (void **)&nm_rxq->iq_desc); 2652 if (rc != 0) 2653 return (rc); 2654 2655 len = na->num_rx_desc * RX_FL_ESIZE + spg_len; 2656 rc = alloc_ring(sc, len, &nm_rxq->fl_desc_tag, &nm_rxq->fl_desc_map, 2657 &nm_rxq->fl_ba, (void **)&nm_rxq->fl_desc); 2658 if (rc != 0) 2659 return (rc); 2660 2661 nm_rxq->pi = pi; 2662 nm_rxq->nid = idx; 2663 nm_rxq->iq_cidx = 0; 2664 nm_rxq->iq_sidx = pi->qsize_rxq - spg_len / RX_IQ_ESIZE; 2665 nm_rxq->iq_gen = F_RSPD_GEN; 2666 nm_rxq->fl_pidx = nm_rxq->fl_cidx = 0; 2667 nm_rxq->fl_sidx = na->num_rx_desc; 2668 nm_rxq->intr_idx = intr_idx; 2669 2670 ctx = &pi->ctx; 2671 children = SYSCTL_CHILDREN(oid); 2672 2673 snprintf(name, sizeof(name), "%d", idx); 2674 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, name, CTLFLAG_RD, NULL, 2675 "rx queue"); 2676 children = SYSCTL_CHILDREN(oid); 2677 2678 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "abs_id", 2679 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_abs_id, 0, sysctl_uint16, 2680 "I", "absolute id of the queue"); 2681 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 2682 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cntxt_id, 0, sysctl_uint16, 2683 "I", "SGE context id of the queue"); 2684 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx", 2685 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cidx, 0, sysctl_uint16, "I", 2686 "consumer index"); 2687 2688 children = SYSCTL_CHILDREN(oid); 2689 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL, 2690 "freelist"); 2691 children = SYSCTL_CHILDREN(oid); 2692 2693 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 2694 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->fl_cntxt_id, 0, sysctl_uint16, 2695 "I", "SGE context id of the freelist"); 2696 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, 2697 &nm_rxq->fl_cidx, 0, "consumer index"); 2698 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, 2699 &nm_rxq->fl_pidx, 0, "producer index"); 2700 2701 return (rc); 2702 } 2703 2704 2705 static int 2706 free_nm_rxq(struct port_info *pi, struct sge_nm_rxq *nm_rxq) 2707 { 2708 struct adapter *sc = pi->adapter; 2709 2710 free_ring(sc, nm_rxq->iq_desc_tag, nm_rxq->iq_desc_map, nm_rxq->iq_ba, 2711 nm_rxq->iq_desc); 2712 free_ring(sc, nm_rxq->fl_desc_tag, nm_rxq->fl_desc_map, nm_rxq->fl_ba, 2713 nm_rxq->fl_desc); 2714 2715 return (0); 2716 } 2717 2718 static int 2719 alloc_nm_txq(struct port_info *pi, struct sge_nm_txq *nm_txq, int iqidx, int idx, 2720 struct sysctl_oid *oid) 2721 { 2722 int rc; 2723 size_t len; 2724 struct adapter *sc = pi->adapter; 2725 struct netmap_adapter *na = NA(pi->nm_ifp); 2726 char name[16]; 2727 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 2728 2729 len = na->num_tx_desc * EQ_ESIZE + spg_len; 2730 rc = alloc_ring(sc, len, &nm_txq->desc_tag, &nm_txq->desc_map, 2731 &nm_txq->ba, (void **)&nm_txq->desc); 2732 if (rc) 2733 return (rc); 2734 2735 nm_txq->pidx = nm_txq->cidx = 0; 2736 nm_txq->sidx = na->num_tx_desc; 2737 nm_txq->nid = idx; 2738 nm_txq->iqidx = iqidx; 2739 nm_txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) | 2740 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(sc->pf)); 2741 2742 snprintf(name, sizeof(name), "%d", idx); 2743 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 2744 NULL, "netmap tx queue"); 2745 children = SYSCTL_CHILDREN(oid); 2746 2747 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 2748 &nm_txq->cntxt_id, 0, "SGE context id of the queue"); 2749 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cidx", 2750 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->cidx, 0, sysctl_uint16, "I", 2751 "consumer index"); 2752 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "pidx", 2753 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->pidx, 0, sysctl_uint16, "I", 2754 "producer index"); 2755 2756 return (rc); 2757 } 2758 2759 static int 2760 free_nm_txq(struct port_info *pi, struct sge_nm_txq *nm_txq) 2761 { 2762 struct adapter *sc = pi->adapter; 2763 2764 free_ring(sc, nm_txq->desc_tag, nm_txq->desc_map, nm_txq->ba, 2765 nm_txq->desc); 2766 2767 return (0); 2768 } 2769 #endif 2770 2771 static int 2772 ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq) 2773 { 2774 int rc, cntxt_id; 2775 struct fw_eq_ctrl_cmd c; 2776 2777 bzero(&c, sizeof(c)); 2778 2779 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | F_FW_CMD_REQUEST | 2780 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_CTRL_CMD_PFN(sc->pf) | 2781 V_FW_EQ_CTRL_CMD_VFN(0)); 2782 c.alloc_to_len16 = htobe32(F_FW_EQ_CTRL_CMD_ALLOC | 2783 F_FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c)); 2784 c.cmpliqid_eqid = htonl(V_FW_EQ_CTRL_CMD_CMPLIQID(eq->iqid)); /* XXX */ 2785 c.physeqid_pkd = htobe32(0); 2786 c.fetchszm_to_iqid = 2787 htobe32(V_FW_EQ_CTRL_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 2788 V_FW_EQ_CTRL_CMD_PCIECHN(eq->tx_chan) | 2789 F_FW_EQ_CTRL_CMD_FETCHRO | V_FW_EQ_CTRL_CMD_IQID(eq->iqid)); 2790 c.dcaen_to_eqsize = 2791 htobe32(V_FW_EQ_CTRL_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 2792 V_FW_EQ_CTRL_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 2793 V_FW_EQ_CTRL_CMD_CIDXFTHRESH(X_CIDXFLUSHTHRESH_32) | 2794 V_FW_EQ_CTRL_CMD_EQSIZE(eq->qsize)); 2795 c.eqaddr = htobe64(eq->ba); 2796 2797 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 2798 if (rc != 0) { 2799 device_printf(sc->dev, 2800 "failed to create control queue %d: %d\n", eq->tx_chan, rc); 2801 return (rc); 2802 } 2803 eq->flags |= EQ_ALLOCATED; 2804 2805 eq->cntxt_id = G_FW_EQ_CTRL_CMD_EQID(be32toh(c.cmpliqid_eqid)); 2806 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 2807 if (cntxt_id >= sc->sge.neq) 2808 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 2809 cntxt_id, sc->sge.neq - 1); 2810 sc->sge.eqmap[cntxt_id] = eq; 2811 2812 return (rc); 2813 } 2814 2815 static int 2816 eth_eq_alloc(struct adapter *sc, struct port_info *pi, struct sge_eq *eq) 2817 { 2818 int rc, cntxt_id; 2819 struct fw_eq_eth_cmd c; 2820 2821 bzero(&c, sizeof(c)); 2822 2823 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST | 2824 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) | 2825 V_FW_EQ_ETH_CMD_VFN(0)); 2826 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC | 2827 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c)); 2828 c.viid_pkd = htobe32(V_FW_EQ_ETH_CMD_VIID(pi->viid)); 2829 c.fetchszm_to_iqid = 2830 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 2831 V_FW_EQ_ETH_CMD_PCIECHN(eq->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO | 2832 V_FW_EQ_ETH_CMD_IQID(eq->iqid)); 2833 c.dcaen_to_eqsize = htobe32(V_FW_EQ_ETH_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 2834 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 2835 V_FW_EQ_ETH_CMD_CIDXFTHRESH(X_CIDXFLUSHTHRESH_32) | 2836 V_FW_EQ_ETH_CMD_EQSIZE(eq->qsize)); 2837 c.eqaddr = htobe64(eq->ba); 2838 2839 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 2840 if (rc != 0) { 2841 device_printf(pi->dev, 2842 "failed to create Ethernet egress queue: %d\n", rc); 2843 return (rc); 2844 } 2845 eq->flags |= EQ_ALLOCATED; 2846 2847 eq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd)); 2848 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 2849 if (cntxt_id >= sc->sge.neq) 2850 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 2851 cntxt_id, sc->sge.neq - 1); 2852 sc->sge.eqmap[cntxt_id] = eq; 2853 2854 return (rc); 2855 } 2856 2857 #ifdef TCP_OFFLOAD 2858 static int 2859 ofld_eq_alloc(struct adapter *sc, struct port_info *pi, struct sge_eq *eq) 2860 { 2861 int rc, cntxt_id; 2862 struct fw_eq_ofld_cmd c; 2863 2864 bzero(&c, sizeof(c)); 2865 2866 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | F_FW_CMD_REQUEST | 2867 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_OFLD_CMD_PFN(sc->pf) | 2868 V_FW_EQ_OFLD_CMD_VFN(0)); 2869 c.alloc_to_len16 = htonl(F_FW_EQ_OFLD_CMD_ALLOC | 2870 F_FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c)); 2871 c.fetchszm_to_iqid = 2872 htonl(V_FW_EQ_OFLD_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 2873 V_FW_EQ_OFLD_CMD_PCIECHN(eq->tx_chan) | 2874 F_FW_EQ_OFLD_CMD_FETCHRO | V_FW_EQ_OFLD_CMD_IQID(eq->iqid)); 2875 c.dcaen_to_eqsize = 2876 htobe32(V_FW_EQ_OFLD_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 2877 V_FW_EQ_OFLD_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 2878 V_FW_EQ_OFLD_CMD_CIDXFTHRESH(X_CIDXFLUSHTHRESH_32) | 2879 V_FW_EQ_OFLD_CMD_EQSIZE(eq->qsize)); 2880 c.eqaddr = htobe64(eq->ba); 2881 2882 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 2883 if (rc != 0) { 2884 device_printf(pi->dev, 2885 "failed to create egress queue for TCP offload: %d\n", rc); 2886 return (rc); 2887 } 2888 eq->flags |= EQ_ALLOCATED; 2889 2890 eq->cntxt_id = G_FW_EQ_OFLD_CMD_EQID(be32toh(c.eqid_pkd)); 2891 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 2892 if (cntxt_id >= sc->sge.neq) 2893 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 2894 cntxt_id, sc->sge.neq - 1); 2895 sc->sge.eqmap[cntxt_id] = eq; 2896 2897 return (rc); 2898 } 2899 #endif 2900 2901 static int 2902 alloc_eq(struct adapter *sc, struct port_info *pi, struct sge_eq *eq) 2903 { 2904 int rc; 2905 size_t len; 2906 2907 mtx_init(&eq->eq_lock, eq->lockname, NULL, MTX_DEF); 2908 2909 len = eq->qsize * EQ_ESIZE; 2910 rc = alloc_ring(sc, len, &eq->desc_tag, &eq->desc_map, 2911 &eq->ba, (void **)&eq->desc); 2912 if (rc) 2913 return (rc); 2914 2915 eq->cap = eq->qsize - spg_len / EQ_ESIZE; 2916 eq->spg = (void *)&eq->desc[eq->cap]; 2917 eq->avail = eq->cap - 1; /* one less to avoid cidx = pidx */ 2918 eq->pidx = eq->cidx = 0; 2919 eq->doorbells = sc->doorbells; 2920 2921 switch (eq->flags & EQ_TYPEMASK) { 2922 case EQ_CTRL: 2923 rc = ctrl_eq_alloc(sc, eq); 2924 break; 2925 2926 case EQ_ETH: 2927 rc = eth_eq_alloc(sc, pi, eq); 2928 break; 2929 2930 #ifdef TCP_OFFLOAD 2931 case EQ_OFLD: 2932 rc = ofld_eq_alloc(sc, pi, eq); 2933 break; 2934 #endif 2935 2936 default: 2937 panic("%s: invalid eq type %d.", __func__, 2938 eq->flags & EQ_TYPEMASK); 2939 } 2940 if (rc != 0) { 2941 device_printf(sc->dev, 2942 "failed to allocate egress queue(%d): %d", 2943 eq->flags & EQ_TYPEMASK, rc); 2944 } 2945 2946 eq->tx_callout.c_cpu = eq->cntxt_id % mp_ncpus; 2947 2948 if (isset(&eq->doorbells, DOORBELL_UDB) || 2949 isset(&eq->doorbells, DOORBELL_UDBWC) || 2950 isset(&eq->doorbells, DOORBELL_WCWR)) { 2951 uint32_t s_qpp = sc->sge.eq_s_qpp; 2952 uint32_t mask = (1 << s_qpp) - 1; 2953 volatile uint8_t *udb; 2954 2955 udb = sc->udbs_base + UDBS_DB_OFFSET; 2956 udb += (eq->cntxt_id >> s_qpp) << PAGE_SHIFT; /* pg offset */ 2957 eq->udb_qid = eq->cntxt_id & mask; /* id in page */ 2958 if (eq->udb_qid > PAGE_SIZE / UDBS_SEG_SIZE) 2959 clrbit(&eq->doorbells, DOORBELL_WCWR); 2960 else { 2961 udb += eq->udb_qid << UDBS_SEG_SHIFT; /* seg offset */ 2962 eq->udb_qid = 0; 2963 } 2964 eq->udb = (volatile void *)udb; 2965 } 2966 2967 return (rc); 2968 } 2969 2970 static int 2971 free_eq(struct adapter *sc, struct sge_eq *eq) 2972 { 2973 int rc; 2974 2975 if (eq->flags & EQ_ALLOCATED) { 2976 switch (eq->flags & EQ_TYPEMASK) { 2977 case EQ_CTRL: 2978 rc = -t4_ctrl_eq_free(sc, sc->mbox, sc->pf, 0, 2979 eq->cntxt_id); 2980 break; 2981 2982 case EQ_ETH: 2983 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0, 2984 eq->cntxt_id); 2985 break; 2986 2987 #ifdef TCP_OFFLOAD 2988 case EQ_OFLD: 2989 rc = -t4_ofld_eq_free(sc, sc->mbox, sc->pf, 0, 2990 eq->cntxt_id); 2991 break; 2992 #endif 2993 2994 default: 2995 panic("%s: invalid eq type %d.", __func__, 2996 eq->flags & EQ_TYPEMASK); 2997 } 2998 if (rc != 0) { 2999 device_printf(sc->dev, 3000 "failed to free egress queue (%d): %d\n", 3001 eq->flags & EQ_TYPEMASK, rc); 3002 return (rc); 3003 } 3004 eq->flags &= ~EQ_ALLOCATED; 3005 } 3006 3007 free_ring(sc, eq->desc_tag, eq->desc_map, eq->ba, eq->desc); 3008 3009 if (mtx_initialized(&eq->eq_lock)) 3010 mtx_destroy(&eq->eq_lock); 3011 3012 bzero(eq, sizeof(*eq)); 3013 return (0); 3014 } 3015 3016 static int 3017 alloc_wrq(struct adapter *sc, struct port_info *pi, struct sge_wrq *wrq, 3018 struct sysctl_oid *oid) 3019 { 3020 int rc; 3021 struct sysctl_ctx_list *ctx = pi ? &pi->ctx : &sc->ctx; 3022 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3023 3024 rc = alloc_eq(sc, pi, &wrq->eq); 3025 if (rc) 3026 return (rc); 3027 3028 wrq->adapter = sc; 3029 STAILQ_INIT(&wrq->wr_list); 3030 3031 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 3032 &wrq->eq.cntxt_id, 0, "SGE context id of the queue"); 3033 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx", 3034 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.cidx, 0, sysctl_uint16, "I", 3035 "consumer index"); 3036 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pidx", 3037 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.pidx, 0, sysctl_uint16, "I", 3038 "producer index"); 3039 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs", CTLFLAG_RD, 3040 &wrq->tx_wrs, "# of work requests"); 3041 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "no_desc", CTLFLAG_RD, 3042 &wrq->no_desc, 0, 3043 "# of times queue ran out of hardware descriptors"); 3044 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "unstalled", CTLFLAG_RD, 3045 &wrq->eq.unstalled, 0, "# of times queue recovered after stall"); 3046 3047 return (rc); 3048 } 3049 3050 static int 3051 free_wrq(struct adapter *sc, struct sge_wrq *wrq) 3052 { 3053 int rc; 3054 3055 rc = free_eq(sc, &wrq->eq); 3056 if (rc) 3057 return (rc); 3058 3059 bzero(wrq, sizeof(*wrq)); 3060 return (0); 3061 } 3062 3063 static int 3064 alloc_txq(struct port_info *pi, struct sge_txq *txq, int idx, 3065 struct sysctl_oid *oid) 3066 { 3067 int rc; 3068 struct adapter *sc = pi->adapter; 3069 struct sge_eq *eq = &txq->eq; 3070 char name[16]; 3071 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3072 3073 rc = alloc_eq(sc, pi, eq); 3074 if (rc) 3075 return (rc); 3076 3077 txq->ifp = pi->ifp; 3078 3079 txq->sdesc = malloc(eq->cap * sizeof(struct tx_sdesc), M_CXGBE, 3080 M_ZERO | M_WAITOK); 3081 txq->br = buf_ring_alloc(eq->qsize, M_CXGBE, M_WAITOK, &eq->eq_lock); 3082 3083 rc = bus_dma_tag_create(sc->dmat, 1, 0, BUS_SPACE_MAXADDR, 3084 BUS_SPACE_MAXADDR, NULL, NULL, 64 * 1024, TX_SGL_SEGS, 3085 BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL, NULL, &txq->tx_tag); 3086 if (rc != 0) { 3087 device_printf(sc->dev, 3088 "failed to create tx DMA tag: %d\n", rc); 3089 return (rc); 3090 } 3091 3092 /* 3093 * We can stuff ~10 frames in an 8-descriptor txpkts WR (8 is the SGE 3094 * limit for any WR). txq->no_dmamap events shouldn't occur if maps is 3095 * sized for the worst case. 3096 */ 3097 rc = t4_alloc_tx_maps(&txq->txmaps, txq->tx_tag, eq->qsize * 10 / 8, 3098 M_WAITOK); 3099 if (rc != 0) { 3100 device_printf(sc->dev, "failed to setup tx DMA maps: %d\n", rc); 3101 return (rc); 3102 } 3103 3104 snprintf(name, sizeof(name), "%d", idx); 3105 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 3106 NULL, "tx queue"); 3107 children = SYSCTL_CHILDREN(oid); 3108 3109 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 3110 &eq->cntxt_id, 0, "SGE context id of the queue"); 3111 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cidx", 3112 CTLTYPE_INT | CTLFLAG_RD, &eq->cidx, 0, sysctl_uint16, "I", 3113 "consumer index"); 3114 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "pidx", 3115 CTLTYPE_INT | CTLFLAG_RD, &eq->pidx, 0, sysctl_uint16, "I", 3116 "producer index"); 3117 3118 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "txcsum", CTLFLAG_RD, 3119 &txq->txcsum, "# of times hardware assisted with checksum"); 3120 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "vlan_insertion", 3121 CTLFLAG_RD, &txq->vlan_insertion, 3122 "# of times hardware inserted 802.1Q tag"); 3123 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "tso_wrs", CTLFLAG_RD, 3124 &txq->tso_wrs, "# of TSO work requests"); 3125 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "imm_wrs", CTLFLAG_RD, 3126 &txq->imm_wrs, "# of work requests with immediate data"); 3127 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "sgl_wrs", CTLFLAG_RD, 3128 &txq->sgl_wrs, "# of work requests with direct SGL"); 3129 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "txpkt_wrs", CTLFLAG_RD, 3130 &txq->txpkt_wrs, "# of txpkt work requests (one pkt/WR)"); 3131 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "txpkts_wrs", CTLFLAG_RD, 3132 &txq->txpkts_wrs, "# of txpkts work requests (multiple pkts/WR)"); 3133 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "txpkts_pkts", CTLFLAG_RD, 3134 &txq->txpkts_pkts, "# of frames tx'd using txpkts work requests"); 3135 3136 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "br_drops", CTLFLAG_RD, 3137 &txq->br->br_drops, "# of drops in the buf_ring for this queue"); 3138 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "no_dmamap", CTLFLAG_RD, 3139 &txq->no_dmamap, 0, "# of times txq ran out of DMA maps"); 3140 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "no_desc", CTLFLAG_RD, 3141 &txq->no_desc, 0, "# of times txq ran out of hardware descriptors"); 3142 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "egr_update", CTLFLAG_RD, 3143 &eq->egr_update, 0, "egress update notifications from the SGE"); 3144 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "unstalled", CTLFLAG_RD, 3145 &eq->unstalled, 0, "# of times txq recovered after stall"); 3146 3147 return (rc); 3148 } 3149 3150 static int 3151 free_txq(struct port_info *pi, struct sge_txq *txq) 3152 { 3153 int rc; 3154 struct adapter *sc = pi->adapter; 3155 struct sge_eq *eq = &txq->eq; 3156 3157 rc = free_eq(sc, eq); 3158 if (rc) 3159 return (rc); 3160 3161 free(txq->sdesc, M_CXGBE); 3162 3163 if (txq->txmaps.maps) 3164 t4_free_tx_maps(&txq->txmaps, txq->tx_tag); 3165 3166 buf_ring_free(txq->br, M_CXGBE); 3167 3168 if (txq->tx_tag) 3169 bus_dma_tag_destroy(txq->tx_tag); 3170 3171 bzero(txq, sizeof(*txq)); 3172 return (0); 3173 } 3174 3175 static void 3176 oneseg_dma_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3177 { 3178 bus_addr_t *ba = arg; 3179 3180 KASSERT(nseg == 1, 3181 ("%s meant for single segment mappings only.", __func__)); 3182 3183 *ba = error ? 0 : segs->ds_addr; 3184 } 3185 3186 static inline bool 3187 is_new_response(const struct sge_iq *iq, struct rsp_ctrl **ctrl) 3188 { 3189 *ctrl = (void *)((uintptr_t)iq->cdesc + 3190 (iq->esize - sizeof(struct rsp_ctrl))); 3191 3192 return (((*ctrl)->u.type_gen >> S_RSPD_GEN) == iq->gen); 3193 } 3194 3195 static inline void 3196 iq_next(struct sge_iq *iq) 3197 { 3198 iq->cdesc = (void *) ((uintptr_t)iq->cdesc + iq->esize); 3199 if (__predict_false(++iq->cidx == iq->qsize - spg_len / iq->esize)) { 3200 iq->cidx = 0; 3201 iq->gen ^= 1; 3202 iq->cdesc = iq->desc; 3203 } 3204 } 3205 3206 #define FL_HW_IDX(x) ((x) >> 3) 3207 static inline void 3208 ring_fl_db(struct adapter *sc, struct sge_fl *fl) 3209 { 3210 int ndesc = fl->pending / 8; 3211 uint32_t v; 3212 3213 if (FL_HW_IDX(fl->pidx) == FL_HW_IDX(fl->cidx)) 3214 ndesc--; /* hold back one credit */ 3215 3216 if (ndesc <= 0) 3217 return; /* nothing to do */ 3218 3219 v = F_DBPRIO | V_QID(fl->cntxt_id) | V_PIDX(ndesc); 3220 if (is_t5(sc)) 3221 v |= F_DBTYPE; 3222 3223 wmb(); 3224 3225 t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL), v); 3226 fl->pending -= ndesc * 8; 3227 } 3228 3229 /* 3230 * Fill up the freelist by upto nbufs and maybe ring its doorbell. 3231 * 3232 * Returns non-zero to indicate that it should be added to the list of starving 3233 * freelists. 3234 */ 3235 static int 3236 refill_fl(struct adapter *sc, struct sge_fl *fl, int nbufs) 3237 { 3238 __be64 *d = &fl->desc[fl->pidx]; 3239 struct fl_sdesc *sd = &fl->sdesc[fl->pidx]; 3240 uintptr_t pa; 3241 caddr_t cl; 3242 struct cluster_layout *cll = &fl->cll_def; /* default layout */ 3243 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx]; 3244 struct cluster_metadata *clm; 3245 3246 FL_LOCK_ASSERT_OWNED(fl); 3247 3248 if (nbufs > fl->needed) 3249 nbufs = fl->needed; 3250 nbufs -= (fl->pidx + nbufs) % 8; 3251 3252 while (nbufs--) { 3253 3254 if (sd->cl != NULL) { 3255 3256 if (sd->nmbuf == 0) { 3257 /* 3258 * Fast recycle without involving any atomics on 3259 * the cluster's metadata (if the cluster has 3260 * metadata). This happens when all frames 3261 * received in the cluster were small enough to 3262 * fit within a single mbuf each. 3263 */ 3264 fl->cl_fast_recycled++; 3265 goto recycled_fast; 3266 } 3267 3268 /* 3269 * Cluster is guaranteed to have metadata. Clusters 3270 * without metadata always take the fast recycle path 3271 * when they're recycled. 3272 */ 3273 clm = cl_metadata(sc, fl, &sd->cll, sd->cl); 3274 MPASS(clm != NULL); 3275 3276 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) { 3277 fl->cl_recycled++; 3278 goto recycled; 3279 } 3280 sd->cl = NULL; /* gave up my reference */ 3281 } 3282 MPASS(sd->cl == NULL); 3283 alloc: 3284 cl = uma_zalloc(swz->zone, M_NOWAIT); 3285 if (__predict_false(cl == NULL)) { 3286 if (cll == &fl->cll_alt || fl->cll_alt.zidx == -1 || 3287 fl->cll_def.zidx == fl->cll_alt.zidx) 3288 break; 3289 3290 /* fall back to the safe zone */ 3291 cll = &fl->cll_alt; 3292 swz = &sc->sge.sw_zone_info[cll->zidx]; 3293 goto alloc; 3294 } 3295 fl->cl_allocated++; 3296 3297 pa = pmap_kextract((vm_offset_t)cl); 3298 pa += cll->region1; 3299 sd->cl = cl; 3300 sd->cll = *cll; 3301 *d = htobe64(pa | cll->hwidx); 3302 clm = cl_metadata(sc, fl, cll, cl); 3303 if (clm != NULL) { 3304 recycled: 3305 #ifdef INVARIANTS 3306 clm->sd = sd; 3307 #endif 3308 clm->refcount = 1; 3309 } 3310 sd->nmbuf = 0; 3311 recycled_fast: 3312 fl->pending++; 3313 fl->needed--; 3314 d++; 3315 sd++; 3316 if (__predict_false(++fl->pidx == fl->cap)) { 3317 fl->pidx = 0; 3318 sd = fl->sdesc; 3319 d = fl->desc; 3320 } 3321 } 3322 3323 if (fl->pending >= 8) 3324 ring_fl_db(sc, fl); 3325 3326 return (FL_RUNNING_LOW(fl) && !(fl->flags & FL_STARVING)); 3327 } 3328 3329 /* 3330 * Attempt to refill all starving freelists. 3331 */ 3332 static void 3333 refill_sfl(void *arg) 3334 { 3335 struct adapter *sc = arg; 3336 struct sge_fl *fl, *fl_temp; 3337 3338 mtx_lock(&sc->sfl_lock); 3339 TAILQ_FOREACH_SAFE(fl, &sc->sfl, link, fl_temp) { 3340 FL_LOCK(fl); 3341 refill_fl(sc, fl, 64); 3342 if (FL_NOT_RUNNING_LOW(fl) || fl->flags & FL_DOOMED) { 3343 TAILQ_REMOVE(&sc->sfl, fl, link); 3344 fl->flags &= ~FL_STARVING; 3345 } 3346 FL_UNLOCK(fl); 3347 } 3348 3349 if (!TAILQ_EMPTY(&sc->sfl)) 3350 callout_schedule(&sc->sfl_callout, hz / 5); 3351 mtx_unlock(&sc->sfl_lock); 3352 } 3353 3354 static int 3355 alloc_fl_sdesc(struct sge_fl *fl) 3356 { 3357 3358 fl->sdesc = malloc(fl->cap * sizeof(struct fl_sdesc), M_CXGBE, 3359 M_ZERO | M_WAITOK); 3360 3361 return (0); 3362 } 3363 3364 static void 3365 free_fl_sdesc(struct adapter *sc, struct sge_fl *fl) 3366 { 3367 struct fl_sdesc *sd; 3368 struct cluster_metadata *clm; 3369 struct cluster_layout *cll; 3370 int i; 3371 3372 sd = fl->sdesc; 3373 for (i = 0; i < fl->cap; i++, sd++) { 3374 if (sd->cl == NULL) 3375 continue; 3376 3377 cll = &sd->cll; 3378 clm = cl_metadata(sc, fl, cll, sd->cl); 3379 if (sd->nmbuf == 0 || 3380 (clm && atomic_fetchadd_int(&clm->refcount, -1) == 1)) { 3381 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl); 3382 } 3383 sd->cl = NULL; 3384 } 3385 3386 free(fl->sdesc, M_CXGBE); 3387 fl->sdesc = NULL; 3388 } 3389 3390 int 3391 t4_alloc_tx_maps(struct tx_maps *txmaps, bus_dma_tag_t tx_tag, int count, 3392 int flags) 3393 { 3394 struct tx_map *txm; 3395 int i, rc; 3396 3397 txmaps->map_total = txmaps->map_avail = count; 3398 txmaps->map_cidx = txmaps->map_pidx = 0; 3399 3400 txmaps->maps = malloc(count * sizeof(struct tx_map), M_CXGBE, 3401 M_ZERO | flags); 3402 3403 txm = txmaps->maps; 3404 for (i = 0; i < count; i++, txm++) { 3405 rc = bus_dmamap_create(tx_tag, 0, &txm->map); 3406 if (rc != 0) 3407 goto failed; 3408 } 3409 3410 return (0); 3411 failed: 3412 while (--i >= 0) { 3413 txm--; 3414 bus_dmamap_destroy(tx_tag, txm->map); 3415 } 3416 KASSERT(txm == txmaps->maps, ("%s: EDOOFUS", __func__)); 3417 3418 free(txmaps->maps, M_CXGBE); 3419 txmaps->maps = NULL; 3420 3421 return (rc); 3422 } 3423 3424 void 3425 t4_free_tx_maps(struct tx_maps *txmaps, bus_dma_tag_t tx_tag) 3426 { 3427 struct tx_map *txm; 3428 int i; 3429 3430 txm = txmaps->maps; 3431 for (i = 0; i < txmaps->map_total; i++, txm++) { 3432 3433 if (txm->m) { 3434 bus_dmamap_unload(tx_tag, txm->map); 3435 m_freem(txm->m); 3436 txm->m = NULL; 3437 } 3438 3439 bus_dmamap_destroy(tx_tag, txm->map); 3440 } 3441 3442 free(txmaps->maps, M_CXGBE); 3443 txmaps->maps = NULL; 3444 } 3445 3446 /* 3447 * We'll do immediate data tx for non-TSO, but only when not coalescing. We're 3448 * willing to use upto 2 hardware descriptors which means a maximum of 96 bytes 3449 * of immediate data. 3450 */ 3451 #define IMM_LEN ( \ 3452 2 * EQ_ESIZE \ 3453 - sizeof(struct fw_eth_tx_pkt_wr) \ 3454 - sizeof(struct cpl_tx_pkt_core)) 3455 3456 /* 3457 * Returns non-zero on failure, no need to cleanup anything in that case. 3458 * 3459 * Note 1: We always try to defrag the mbuf if required and return EFBIG only 3460 * if the resulting chain still won't fit in a tx descriptor. 3461 * 3462 * Note 2: We'll pullup the mbuf chain if TSO is requested and the first mbuf 3463 * does not have the TCP header in it. 3464 */ 3465 static int 3466 get_pkt_sgl(struct sge_txq *txq, struct mbuf **fp, struct sgl *sgl, 3467 int sgl_only) 3468 { 3469 struct mbuf *m = *fp; 3470 struct tx_maps *txmaps; 3471 struct tx_map *txm; 3472 int rc, defragged = 0, n; 3473 3474 TXQ_LOCK_ASSERT_OWNED(txq); 3475 3476 if (m->m_pkthdr.tso_segsz) 3477 sgl_only = 1; /* Do not allow immediate data with LSO */ 3478 3479 start: sgl->nsegs = 0; 3480 3481 if (m->m_pkthdr.len <= IMM_LEN && !sgl_only) 3482 return (0); /* nsegs = 0 tells caller to use imm. tx */ 3483 3484 txmaps = &txq->txmaps; 3485 if (txmaps->map_avail == 0) { 3486 txq->no_dmamap++; 3487 return (ENOMEM); 3488 } 3489 txm = &txmaps->maps[txmaps->map_pidx]; 3490 3491 if (m->m_pkthdr.tso_segsz && m->m_len < 50) { 3492 *fp = m_pullup(m, 50); 3493 m = *fp; 3494 if (m == NULL) 3495 return (ENOBUFS); 3496 } 3497 3498 rc = bus_dmamap_load_mbuf_sg(txq->tx_tag, txm->map, m, sgl->seg, 3499 &sgl->nsegs, BUS_DMA_NOWAIT); 3500 if (rc == EFBIG && defragged == 0) { 3501 m = m_defrag(m, M_NOWAIT); 3502 if (m == NULL) 3503 return (EFBIG); 3504 3505 defragged = 1; 3506 *fp = m; 3507 goto start; 3508 } 3509 if (rc != 0) 3510 return (rc); 3511 3512 txm->m = m; 3513 txmaps->map_avail--; 3514 if (++txmaps->map_pidx == txmaps->map_total) 3515 txmaps->map_pidx = 0; 3516 3517 KASSERT(sgl->nsegs > 0 && sgl->nsegs <= TX_SGL_SEGS, 3518 ("%s: bad DMA mapping (%d segments)", __func__, sgl->nsegs)); 3519 3520 /* 3521 * Store the # of flits required to hold this frame's SGL in nflits. An 3522 * SGL has a (ULPTX header + len0, addr0) tuple optionally followed by 3523 * multiple (len0 + len1, addr0, addr1) tuples. If addr1 is not used 3524 * then len1 must be set to 0. 3525 */ 3526 n = sgl->nsegs - 1; 3527 sgl->nflits = (3 * n) / 2 + (n & 1) + 2; 3528 3529 return (0); 3530 } 3531 3532 3533 /* 3534 * Releases all the txq resources used up in the specified sgl. 3535 */ 3536 static int 3537 free_pkt_sgl(struct sge_txq *txq, struct sgl *sgl) 3538 { 3539 struct tx_maps *txmaps; 3540 struct tx_map *txm; 3541 3542 TXQ_LOCK_ASSERT_OWNED(txq); 3543 3544 if (sgl->nsegs == 0) 3545 return (0); /* didn't use any map */ 3546 3547 txmaps = &txq->txmaps; 3548 3549 /* 1 pkt uses exactly 1 map, back it out */ 3550 3551 txmaps->map_avail++; 3552 if (txmaps->map_pidx > 0) 3553 txmaps->map_pidx--; 3554 else 3555 txmaps->map_pidx = txmaps->map_total - 1; 3556 3557 txm = &txmaps->maps[txmaps->map_pidx]; 3558 bus_dmamap_unload(txq->tx_tag, txm->map); 3559 txm->m = NULL; 3560 3561 return (0); 3562 } 3563 3564 static int 3565 write_txpkt_wr(struct port_info *pi, struct sge_txq *txq, struct mbuf *m, 3566 struct sgl *sgl) 3567 { 3568 struct sge_eq *eq = &txq->eq; 3569 struct fw_eth_tx_pkt_wr *wr; 3570 struct cpl_tx_pkt_core *cpl; 3571 uint32_t ctrl; /* used in many unrelated places */ 3572 uint64_t ctrl1; 3573 int nflits, ndesc, pktlen; 3574 struct tx_sdesc *txsd; 3575 caddr_t dst; 3576 3577 TXQ_LOCK_ASSERT_OWNED(txq); 3578 3579 pktlen = m->m_pkthdr.len; 3580 3581 /* 3582 * Do we have enough flits to send this frame out? 3583 */ 3584 ctrl = sizeof(struct cpl_tx_pkt_core); 3585 if (m->m_pkthdr.tso_segsz) { 3586 nflits = TXPKT_LSO_WR_HDR; 3587 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 3588 } else 3589 nflits = TXPKT_WR_HDR; 3590 if (sgl->nsegs > 0) 3591 nflits += sgl->nflits; 3592 else { 3593 nflits += howmany(pktlen, 8); 3594 ctrl += pktlen; 3595 } 3596 ndesc = howmany(nflits, 8); 3597 if (ndesc > eq->avail) 3598 return (ENOMEM); 3599 3600 /* Firmware work request header */ 3601 wr = (void *)&eq->desc[eq->pidx]; 3602 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_WR) | 3603 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl)); 3604 ctrl = V_FW_WR_LEN16(howmany(nflits, 2)); 3605 if (eq->avail == ndesc) { 3606 if (!(eq->flags & EQ_CRFLUSHED)) { 3607 ctrl |= F_FW_WR_EQUEQ | F_FW_WR_EQUIQ; 3608 eq->flags |= EQ_CRFLUSHED; 3609 } 3610 eq->flags |= EQ_STALLED; 3611 } 3612 3613 wr->equiq_to_len16 = htobe32(ctrl); 3614 wr->r3 = 0; 3615 3616 if (m->m_pkthdr.tso_segsz) { 3617 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1); 3618 struct ether_header *eh; 3619 void *l3hdr; 3620 #if defined(INET) || defined(INET6) 3621 struct tcphdr *tcp; 3622 #endif 3623 uint16_t eh_type; 3624 3625 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE | 3626 F_LSO_LAST_SLICE; 3627 3628 eh = mtod(m, struct ether_header *); 3629 eh_type = ntohs(eh->ether_type); 3630 if (eh_type == ETHERTYPE_VLAN) { 3631 struct ether_vlan_header *evh = (void *)eh; 3632 3633 ctrl |= V_LSO_ETHHDR_LEN(1); 3634 l3hdr = evh + 1; 3635 eh_type = ntohs(evh->evl_proto); 3636 } else 3637 l3hdr = eh + 1; 3638 3639 switch (eh_type) { 3640 #ifdef INET6 3641 case ETHERTYPE_IPV6: 3642 { 3643 struct ip6_hdr *ip6 = l3hdr; 3644 3645 /* 3646 * XXX-BZ For now we do not pretend to support 3647 * IPv6 extension headers. 3648 */ 3649 KASSERT(ip6->ip6_nxt == IPPROTO_TCP, ("%s: CSUM_TSO " 3650 "with ip6_nxt != TCP: %u", __func__, ip6->ip6_nxt)); 3651 tcp = (struct tcphdr *)(ip6 + 1); 3652 ctrl |= F_LSO_IPV6; 3653 ctrl |= V_LSO_IPHDR_LEN(sizeof(*ip6) >> 2) | 3654 V_LSO_TCPHDR_LEN(tcp->th_off); 3655 break; 3656 } 3657 #endif 3658 #ifdef INET 3659 case ETHERTYPE_IP: 3660 { 3661 struct ip *ip = l3hdr; 3662 3663 tcp = (void *)((uintptr_t)ip + ip->ip_hl * 4); 3664 ctrl |= V_LSO_IPHDR_LEN(ip->ip_hl) | 3665 V_LSO_TCPHDR_LEN(tcp->th_off); 3666 break; 3667 } 3668 #endif 3669 default: 3670 panic("%s: CSUM_TSO but no supported IP version " 3671 "(0x%04x)", __func__, eh_type); 3672 } 3673 3674 lso->lso_ctrl = htobe32(ctrl); 3675 lso->ipid_ofst = htobe16(0); 3676 lso->mss = htobe16(m->m_pkthdr.tso_segsz); 3677 lso->seqno_offset = htobe32(0); 3678 lso->len = htobe32(pktlen); 3679 3680 cpl = (void *)(lso + 1); 3681 3682 txq->tso_wrs++; 3683 } else 3684 cpl = (void *)(wr + 1); 3685 3686 /* Checksum offload */ 3687 ctrl1 = 0; 3688 if (!(m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TSO))) 3689 ctrl1 |= F_TXPKT_IPCSUM_DIS; 3690 if (!(m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_UDP_IPV6 | 3691 CSUM_TCP_IPV6 | CSUM_TSO))) 3692 ctrl1 |= F_TXPKT_L4CSUM_DIS; 3693 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | 3694 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO)) 3695 txq->txcsum++; /* some hardware assistance provided */ 3696 3697 /* VLAN tag insertion */ 3698 if (m->m_flags & M_VLANTAG) { 3699 ctrl1 |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(m->m_pkthdr.ether_vtag); 3700 txq->vlan_insertion++; 3701 } 3702 3703 /* CPL header */ 3704 cpl->ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) | 3705 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(pi->adapter->pf)); 3706 cpl->pack = 0; 3707 cpl->len = htobe16(pktlen); 3708 cpl->ctrl1 = htobe64(ctrl1); 3709 3710 /* Software descriptor */ 3711 txsd = &txq->sdesc[eq->pidx]; 3712 txsd->desc_used = ndesc; 3713 3714 eq->pending += ndesc; 3715 eq->avail -= ndesc; 3716 eq->pidx += ndesc; 3717 if (eq->pidx >= eq->cap) 3718 eq->pidx -= eq->cap; 3719 3720 /* SGL */ 3721 dst = (void *)(cpl + 1); 3722 if (sgl->nsegs > 0) { 3723 txsd->credits = 1; 3724 txq->sgl_wrs++; 3725 write_sgl_to_txd(eq, sgl, &dst); 3726 } else { 3727 txsd->credits = 0; 3728 txq->imm_wrs++; 3729 for (; m; m = m->m_next) { 3730 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len); 3731 #ifdef INVARIANTS 3732 pktlen -= m->m_len; 3733 #endif 3734 } 3735 #ifdef INVARIANTS 3736 KASSERT(pktlen == 0, ("%s: %d bytes left.", __func__, pktlen)); 3737 #endif 3738 3739 } 3740 3741 txq->txpkt_wrs++; 3742 return (0); 3743 } 3744 3745 /* 3746 * Returns 0 to indicate that m has been accepted into a coalesced tx work 3747 * request. It has either been folded into txpkts or txpkts was flushed and m 3748 * has started a new coalesced work request (as the first frame in a fresh 3749 * txpkts). 3750 * 3751 * Returns non-zero to indicate a failure - caller is responsible for 3752 * transmitting m, if there was anything in txpkts it has been flushed. 3753 */ 3754 static int 3755 add_to_txpkts(struct port_info *pi, struct sge_txq *txq, struct txpkts *txpkts, 3756 struct mbuf *m, struct sgl *sgl) 3757 { 3758 struct sge_eq *eq = &txq->eq; 3759 int can_coalesce; 3760 struct tx_sdesc *txsd; 3761 int flits; 3762 3763 TXQ_LOCK_ASSERT_OWNED(txq); 3764 3765 KASSERT(sgl->nsegs, ("%s: can't coalesce imm data", __func__)); 3766 3767 if (txpkts->npkt > 0) { 3768 flits = TXPKTS_PKT_HDR + sgl->nflits; 3769 can_coalesce = m->m_pkthdr.tso_segsz == 0 && 3770 txpkts->nflits + flits <= TX_WR_FLITS && 3771 txpkts->nflits + flits <= eq->avail * 8 && 3772 txpkts->plen + m->m_pkthdr.len < 65536; 3773 3774 if (can_coalesce) { 3775 txpkts->npkt++; 3776 txpkts->nflits += flits; 3777 txpkts->plen += m->m_pkthdr.len; 3778 3779 txsd = &txq->sdesc[eq->pidx]; 3780 txsd->credits++; 3781 3782 return (0); 3783 } 3784 3785 /* 3786 * Couldn't coalesce m into txpkts. The first order of business 3787 * is to send txpkts on its way. Then we'll revisit m. 3788 */ 3789 write_txpkts_wr(txq, txpkts); 3790 } 3791 3792 /* 3793 * Check if we can start a new coalesced tx work request with m as 3794 * the first packet in it. 3795 */ 3796 3797 KASSERT(txpkts->npkt == 0, ("%s: txpkts not empty", __func__)); 3798 3799 flits = TXPKTS_WR_HDR + sgl->nflits; 3800 can_coalesce = m->m_pkthdr.tso_segsz == 0 && 3801 flits <= eq->avail * 8 && flits <= TX_WR_FLITS; 3802 3803 if (can_coalesce == 0) 3804 return (EINVAL); 3805 3806 /* 3807 * Start a fresh coalesced tx WR with m as the first frame in it. 3808 */ 3809 txpkts->npkt = 1; 3810 txpkts->nflits = flits; 3811 txpkts->flitp = &eq->desc[eq->pidx].flit[2]; 3812 txpkts->plen = m->m_pkthdr.len; 3813 3814 txsd = &txq->sdesc[eq->pidx]; 3815 txsd->credits = 1; 3816 3817 return (0); 3818 } 3819 3820 /* 3821 * Note that write_txpkts_wr can never run out of hardware descriptors (but 3822 * write_txpkt_wr can). add_to_txpkts ensures that a frame is accepted for 3823 * coalescing only if sufficient hardware descriptors are available. 3824 */ 3825 static void 3826 write_txpkts_wr(struct sge_txq *txq, struct txpkts *txpkts) 3827 { 3828 struct sge_eq *eq = &txq->eq; 3829 struct fw_eth_tx_pkts_wr *wr; 3830 struct tx_sdesc *txsd; 3831 uint32_t ctrl; 3832 int ndesc; 3833 3834 TXQ_LOCK_ASSERT_OWNED(txq); 3835 3836 ndesc = howmany(txpkts->nflits, 8); 3837 3838 wr = (void *)&eq->desc[eq->pidx]; 3839 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR)); 3840 ctrl = V_FW_WR_LEN16(howmany(txpkts->nflits, 2)); 3841 if (eq->avail == ndesc) { 3842 if (!(eq->flags & EQ_CRFLUSHED)) { 3843 ctrl |= F_FW_WR_EQUEQ | F_FW_WR_EQUIQ; 3844 eq->flags |= EQ_CRFLUSHED; 3845 } 3846 eq->flags |= EQ_STALLED; 3847 } 3848 wr->equiq_to_len16 = htobe32(ctrl); 3849 wr->plen = htobe16(txpkts->plen); 3850 wr->npkt = txpkts->npkt; 3851 wr->r3 = wr->type = 0; 3852 3853 /* Everything else already written */ 3854 3855 txsd = &txq->sdesc[eq->pidx]; 3856 txsd->desc_used = ndesc; 3857 3858 KASSERT(eq->avail >= ndesc, ("%s: out of descriptors", __func__)); 3859 3860 eq->pending += ndesc; 3861 eq->avail -= ndesc; 3862 eq->pidx += ndesc; 3863 if (eq->pidx >= eq->cap) 3864 eq->pidx -= eq->cap; 3865 3866 txq->txpkts_pkts += txpkts->npkt; 3867 txq->txpkts_wrs++; 3868 txpkts->npkt = 0; /* emptied */ 3869 } 3870 3871 static inline void 3872 write_ulp_cpl_sgl(struct port_info *pi, struct sge_txq *txq, 3873 struct txpkts *txpkts, struct mbuf *m, struct sgl *sgl) 3874 { 3875 struct ulp_txpkt *ulpmc; 3876 struct ulptx_idata *ulpsc; 3877 struct cpl_tx_pkt_core *cpl; 3878 struct sge_eq *eq = &txq->eq; 3879 uintptr_t flitp, start, end; 3880 uint64_t ctrl; 3881 caddr_t dst; 3882 3883 KASSERT(txpkts->npkt > 0, ("%s: txpkts is empty", __func__)); 3884 3885 start = (uintptr_t)eq->desc; 3886 end = (uintptr_t)eq->spg; 3887 3888 /* Checksum offload */ 3889 ctrl = 0; 3890 if (!(m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TSO))) 3891 ctrl |= F_TXPKT_IPCSUM_DIS; 3892 if (!(m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_UDP_IPV6 | 3893 CSUM_TCP_IPV6 | CSUM_TSO))) 3894 ctrl |= F_TXPKT_L4CSUM_DIS; 3895 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | 3896 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO)) 3897 txq->txcsum++; /* some hardware assistance provided */ 3898 3899 /* VLAN tag insertion */ 3900 if (m->m_flags & M_VLANTAG) { 3901 ctrl |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(m->m_pkthdr.ether_vtag); 3902 txq->vlan_insertion++; 3903 } 3904 3905 /* 3906 * The previous packet's SGL must have ended at a 16 byte boundary (this 3907 * is required by the firmware/hardware). It follows that flitp cannot 3908 * wrap around between the ULPTX master command and ULPTX subcommand (8 3909 * bytes each), and that it can not wrap around in the middle of the 3910 * cpl_tx_pkt_core either. 3911 */ 3912 flitp = (uintptr_t)txpkts->flitp; 3913 KASSERT((flitp & 0xf) == 0, 3914 ("%s: last SGL did not end at 16 byte boundary: %p", 3915 __func__, txpkts->flitp)); 3916 3917 /* ULP master command */ 3918 ulpmc = (void *)flitp; 3919 ulpmc->cmd_dest = htonl(V_ULPTX_CMD(ULP_TX_PKT) | V_ULP_TXPKT_DEST(0) | 3920 V_ULP_TXPKT_FID(eq->iqid)); 3921 ulpmc->len = htonl(howmany(sizeof(*ulpmc) + sizeof(*ulpsc) + 3922 sizeof(*cpl) + 8 * sgl->nflits, 16)); 3923 3924 /* ULP subcommand */ 3925 ulpsc = (void *)(ulpmc + 1); 3926 ulpsc->cmd_more = htobe32(V_ULPTX_CMD((u32)ULP_TX_SC_IMM) | 3927 F_ULP_TX_SC_MORE); 3928 ulpsc->len = htobe32(sizeof(struct cpl_tx_pkt_core)); 3929 3930 flitp += sizeof(*ulpmc) + sizeof(*ulpsc); 3931 if (flitp == end) 3932 flitp = start; 3933 3934 /* CPL_TX_PKT */ 3935 cpl = (void *)flitp; 3936 cpl->ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) | 3937 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(pi->adapter->pf)); 3938 cpl->pack = 0; 3939 cpl->len = htobe16(m->m_pkthdr.len); 3940 cpl->ctrl1 = htobe64(ctrl); 3941 3942 flitp += sizeof(*cpl); 3943 if (flitp == end) 3944 flitp = start; 3945 3946 /* SGL for this frame */ 3947 dst = (caddr_t)flitp; 3948 txpkts->nflits += write_sgl_to_txd(eq, sgl, &dst); 3949 txpkts->flitp = (void *)dst; 3950 3951 KASSERT(((uintptr_t)dst & 0xf) == 0, 3952 ("%s: SGL ends at %p (not a 16 byte boundary)", __func__, dst)); 3953 } 3954 3955 /* 3956 * If the SGL ends on an address that is not 16 byte aligned, this function will 3957 * add a 0 filled flit at the end. It returns 1 in that case. 3958 */ 3959 static int 3960 write_sgl_to_txd(struct sge_eq *eq, struct sgl *sgl, caddr_t *to) 3961 { 3962 __be64 *flitp, *end; 3963 struct ulptx_sgl *usgl; 3964 bus_dma_segment_t *seg; 3965 int i, padded; 3966 3967 KASSERT(sgl->nsegs > 0 && sgl->nflits > 0, 3968 ("%s: bad SGL - nsegs=%d, nflits=%d", 3969 __func__, sgl->nsegs, sgl->nflits)); 3970 3971 KASSERT(((uintptr_t)(*to) & 0xf) == 0, 3972 ("%s: SGL must start at a 16 byte boundary: %p", __func__, *to)); 3973 3974 flitp = (__be64 *)(*to); 3975 end = flitp + sgl->nflits; 3976 seg = &sgl->seg[0]; 3977 usgl = (void *)flitp; 3978 3979 /* 3980 * We start at a 16 byte boundary somewhere inside the tx descriptor 3981 * ring, so we're at least 16 bytes away from the status page. There is 3982 * no chance of a wrap around in the middle of usgl (which is 16 bytes). 3983 */ 3984 3985 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 3986 V_ULPTX_NSGE(sgl->nsegs)); 3987 usgl->len0 = htobe32(seg->ds_len); 3988 usgl->addr0 = htobe64(seg->ds_addr); 3989 seg++; 3990 3991 if ((uintptr_t)end <= (uintptr_t)eq->spg) { 3992 3993 /* Won't wrap around at all */ 3994 3995 for (i = 0; i < sgl->nsegs - 1; i++, seg++) { 3996 usgl->sge[i / 2].len[i & 1] = htobe32(seg->ds_len); 3997 usgl->sge[i / 2].addr[i & 1] = htobe64(seg->ds_addr); 3998 } 3999 if (i & 1) 4000 usgl->sge[i / 2].len[1] = htobe32(0); 4001 } else { 4002 4003 /* Will wrap somewhere in the rest of the SGL */ 4004 4005 /* 2 flits already written, write the rest flit by flit */ 4006 flitp = (void *)(usgl + 1); 4007 for (i = 0; i < sgl->nflits - 2; i++) { 4008 if ((uintptr_t)flitp == (uintptr_t)eq->spg) 4009 flitp = (void *)eq->desc; 4010 *flitp++ = get_flit(seg, sgl->nsegs - 1, i); 4011 } 4012 end = flitp; 4013 } 4014 4015 if ((uintptr_t)end & 0xf) { 4016 *(uint64_t *)end = 0; 4017 end++; 4018 padded = 1; 4019 } else 4020 padded = 0; 4021 4022 if ((uintptr_t)end == (uintptr_t)eq->spg) 4023 *to = (void *)eq->desc; 4024 else 4025 *to = (void *)end; 4026 4027 return (padded); 4028 } 4029 4030 static inline void 4031 copy_to_txd(struct sge_eq *eq, caddr_t from, caddr_t *to, int len) 4032 { 4033 if (__predict_true((uintptr_t)(*to) + len <= (uintptr_t)eq->spg)) { 4034 bcopy(from, *to, len); 4035 (*to) += len; 4036 } else { 4037 int portion = (uintptr_t)eq->spg - (uintptr_t)(*to); 4038 4039 bcopy(from, *to, portion); 4040 from += portion; 4041 portion = len - portion; /* remaining */ 4042 bcopy(from, (void *)eq->desc, portion); 4043 (*to) = (caddr_t)eq->desc + portion; 4044 } 4045 } 4046 4047 static inline void 4048 ring_eq_db(struct adapter *sc, struct sge_eq *eq) 4049 { 4050 u_int db, pending; 4051 4052 db = eq->doorbells; 4053 pending = eq->pending; 4054 if (pending > 1) 4055 clrbit(&db, DOORBELL_WCWR); 4056 eq->pending = 0; 4057 wmb(); 4058 4059 switch (ffs(db) - 1) { 4060 case DOORBELL_UDB: 4061 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(pending)); 4062 return; 4063 4064 case DOORBELL_WCWR: { 4065 volatile uint64_t *dst, *src; 4066 int i; 4067 4068 /* 4069 * Queues whose 128B doorbell segment fits in the page do not 4070 * use relative qid (udb_qid is always 0). Only queues with 4071 * doorbell segments can do WCWR. 4072 */ 4073 KASSERT(eq->udb_qid == 0 && pending == 1, 4074 ("%s: inappropriate doorbell (0x%x, %d, %d) for eq %p", 4075 __func__, eq->doorbells, pending, eq->pidx, eq)); 4076 4077 dst = (volatile void *)((uintptr_t)eq->udb + UDBS_WR_OFFSET - 4078 UDBS_DB_OFFSET); 4079 i = eq->pidx ? eq->pidx - 1 : eq->cap - 1; 4080 src = (void *)&eq->desc[i]; 4081 while (src != (void *)&eq->desc[i + 1]) 4082 *dst++ = *src++; 4083 wmb(); 4084 return; 4085 } 4086 4087 case DOORBELL_UDBWC: 4088 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(pending)); 4089 wmb(); 4090 return; 4091 4092 case DOORBELL_KDB: 4093 t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL), 4094 V_QID(eq->cntxt_id) | V_PIDX(pending)); 4095 return; 4096 } 4097 } 4098 4099 static inline int 4100 reclaimable(struct sge_eq *eq) 4101 { 4102 unsigned int cidx; 4103 4104 cidx = eq->spg->cidx; /* stable snapshot */ 4105 cidx = be16toh(cidx); 4106 4107 if (cidx >= eq->cidx) 4108 return (cidx - eq->cidx); 4109 else 4110 return (cidx + eq->cap - eq->cidx); 4111 } 4112 4113 /* 4114 * There are "can_reclaim" tx descriptors ready to be reclaimed. Reclaim as 4115 * many as possible but stop when there are around "n" mbufs to free. 4116 * 4117 * The actual number reclaimed is provided as the return value. 4118 */ 4119 static int 4120 reclaim_tx_descs(struct sge_txq *txq, int can_reclaim, int n) 4121 { 4122 struct tx_sdesc *txsd; 4123 struct tx_maps *txmaps; 4124 struct tx_map *txm; 4125 unsigned int reclaimed, maps; 4126 struct sge_eq *eq = &txq->eq; 4127 4128 TXQ_LOCK_ASSERT_OWNED(txq); 4129 4130 if (can_reclaim == 0) 4131 can_reclaim = reclaimable(eq); 4132 4133 maps = reclaimed = 0; 4134 while (can_reclaim && maps < n) { 4135 int ndesc; 4136 4137 txsd = &txq->sdesc[eq->cidx]; 4138 ndesc = txsd->desc_used; 4139 4140 /* Firmware doesn't return "partial" credits. */ 4141 KASSERT(can_reclaim >= ndesc, 4142 ("%s: unexpected number of credits: %d, %d", 4143 __func__, can_reclaim, ndesc)); 4144 4145 maps += txsd->credits; 4146 4147 reclaimed += ndesc; 4148 can_reclaim -= ndesc; 4149 4150 eq->cidx += ndesc; 4151 if (__predict_false(eq->cidx >= eq->cap)) 4152 eq->cidx -= eq->cap; 4153 } 4154 4155 txmaps = &txq->txmaps; 4156 txm = &txmaps->maps[txmaps->map_cidx]; 4157 if (maps) 4158 prefetch(txm->m); 4159 4160 eq->avail += reclaimed; 4161 KASSERT(eq->avail < eq->cap, /* avail tops out at (cap - 1) */ 4162 ("%s: too many descriptors available", __func__)); 4163 4164 txmaps->map_avail += maps; 4165 KASSERT(txmaps->map_avail <= txmaps->map_total, 4166 ("%s: too many maps available", __func__)); 4167 4168 while (maps--) { 4169 struct tx_map *next; 4170 4171 next = txm + 1; 4172 if (__predict_false(txmaps->map_cidx + 1 == txmaps->map_total)) 4173 next = txmaps->maps; 4174 prefetch(next->m); 4175 4176 bus_dmamap_unload(txq->tx_tag, txm->map); 4177 m_freem(txm->m); 4178 txm->m = NULL; 4179 4180 txm = next; 4181 if (__predict_false(++txmaps->map_cidx == txmaps->map_total)) 4182 txmaps->map_cidx = 0; 4183 } 4184 4185 return (reclaimed); 4186 } 4187 4188 static void 4189 write_eqflush_wr(struct sge_eq *eq) 4190 { 4191 struct fw_eq_flush_wr *wr; 4192 4193 EQ_LOCK_ASSERT_OWNED(eq); 4194 KASSERT(eq->avail > 0, ("%s: no descriptors left.", __func__)); 4195 KASSERT(!(eq->flags & EQ_CRFLUSHED), ("%s: flushed already", __func__)); 4196 4197 wr = (void *)&eq->desc[eq->pidx]; 4198 bzero(wr, sizeof(*wr)); 4199 wr->opcode = FW_EQ_FLUSH_WR; 4200 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(sizeof(*wr) / 16) | 4201 F_FW_WR_EQUEQ | F_FW_WR_EQUIQ); 4202 4203 eq->flags |= (EQ_CRFLUSHED | EQ_STALLED); 4204 eq->pending++; 4205 eq->avail--; 4206 if (++eq->pidx == eq->cap) 4207 eq->pidx = 0; 4208 } 4209 4210 static __be64 4211 get_flit(bus_dma_segment_t *sgl, int nsegs, int idx) 4212 { 4213 int i = (idx / 3) * 2; 4214 4215 switch (idx % 3) { 4216 case 0: { 4217 __be64 rc; 4218 4219 rc = htobe32(sgl[i].ds_len); 4220 if (i + 1 < nsegs) 4221 rc |= (uint64_t)htobe32(sgl[i + 1].ds_len) << 32; 4222 4223 return (rc); 4224 } 4225 case 1: 4226 return htobe64(sgl[i].ds_addr); 4227 case 2: 4228 return htobe64(sgl[i + 1].ds_addr); 4229 } 4230 4231 return (0); 4232 } 4233 4234 static void 4235 find_best_refill_source(struct adapter *sc, struct sge_fl *fl, int maxp) 4236 { 4237 int8_t zidx, hwidx, idx; 4238 uint16_t region1, region3; 4239 int spare, spare_needed, n; 4240 struct sw_zone_info *swz; 4241 struct hw_buf_info *hwb, *hwb_list = &sc->sge.hw_buf_info[0]; 4242 4243 /* 4244 * Buffer Packing: Look for PAGE_SIZE or larger zone which has a bufsize 4245 * large enough for the max payload and cluster metadata. Otherwise 4246 * settle for the largest bufsize that leaves enough room in the cluster 4247 * for metadata. 4248 * 4249 * Without buffer packing: Look for the smallest zone which has a 4250 * bufsize large enough for the max payload. Settle for the largest 4251 * bufsize available if there's nothing big enough for max payload. 4252 */ 4253 spare_needed = fl->flags & FL_BUF_PACKING ? CL_METADATA_SIZE : 0; 4254 swz = &sc->sge.sw_zone_info[0]; 4255 hwidx = -1; 4256 for (zidx = 0; zidx < SW_ZONE_SIZES; zidx++, swz++) { 4257 if (swz->size > largest_rx_cluster) { 4258 if (__predict_true(hwidx != -1)) 4259 break; 4260 4261 /* 4262 * This is a misconfiguration. largest_rx_cluster is 4263 * preventing us from finding a refill source. See 4264 * dev.t5nex.<n>.buffer_sizes to figure out why. 4265 */ 4266 device_printf(sc->dev, "largest_rx_cluster=%u leaves no" 4267 " refill source for fl %p (dma %u). Ignored.\n", 4268 largest_rx_cluster, fl, maxp); 4269 } 4270 for (idx = swz->head_hwidx; idx != -1; idx = hwb->next) { 4271 hwb = &hwb_list[idx]; 4272 spare = swz->size - hwb->size; 4273 if (spare < spare_needed) 4274 continue; 4275 4276 hwidx = idx; /* best option so far */ 4277 if (hwb->size >= maxp) { 4278 4279 if ((fl->flags & FL_BUF_PACKING) == 0) 4280 goto done; /* stop looking (not packing) */ 4281 4282 if (swz->size >= safest_rx_cluster) 4283 goto done; /* stop looking (packing) */ 4284 } 4285 break; /* keep looking, next zone */ 4286 } 4287 } 4288 done: 4289 /* A usable hwidx has been located. */ 4290 MPASS(hwidx != -1); 4291 hwb = &hwb_list[hwidx]; 4292 zidx = hwb->zidx; 4293 swz = &sc->sge.sw_zone_info[zidx]; 4294 region1 = 0; 4295 region3 = swz->size - hwb->size; 4296 4297 /* 4298 * Stay within this zone and see if there is a better match when mbuf 4299 * inlining is allowed. Remember that the hwidx's are sorted in 4300 * decreasing order of size (so in increasing order of spare area). 4301 */ 4302 for (idx = hwidx; idx != -1; idx = hwb->next) { 4303 hwb = &hwb_list[idx]; 4304 spare = swz->size - hwb->size; 4305 4306 if (allow_mbufs_in_cluster == 0 || hwb->size < maxp) 4307 break; 4308 if (spare < CL_METADATA_SIZE + MSIZE) 4309 continue; 4310 n = (spare - CL_METADATA_SIZE) / MSIZE; 4311 if (n > howmany(hwb->size, maxp)) 4312 break; 4313 4314 hwidx = idx; 4315 if (fl->flags & FL_BUF_PACKING) { 4316 region1 = n * MSIZE; 4317 region3 = spare - region1; 4318 } else { 4319 region1 = MSIZE; 4320 region3 = spare - region1; 4321 break; 4322 } 4323 } 4324 4325 KASSERT(zidx >= 0 && zidx < SW_ZONE_SIZES, 4326 ("%s: bad zone %d for fl %p, maxp %d", __func__, zidx, fl, maxp)); 4327 KASSERT(hwidx >= 0 && hwidx <= SGE_FLBUF_SIZES, 4328 ("%s: bad hwidx %d for fl %p, maxp %d", __func__, hwidx, fl, maxp)); 4329 KASSERT(region1 + sc->sge.hw_buf_info[hwidx].size + region3 == 4330 sc->sge.sw_zone_info[zidx].size, 4331 ("%s: bad buffer layout for fl %p, maxp %d. " 4332 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp, 4333 sc->sge.sw_zone_info[zidx].size, region1, 4334 sc->sge.hw_buf_info[hwidx].size, region3)); 4335 if (fl->flags & FL_BUF_PACKING || region1 > 0) { 4336 KASSERT(region3 >= CL_METADATA_SIZE, 4337 ("%s: no room for metadata. fl %p, maxp %d; " 4338 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp, 4339 sc->sge.sw_zone_info[zidx].size, region1, 4340 sc->sge.hw_buf_info[hwidx].size, region3)); 4341 KASSERT(region1 % MSIZE == 0, 4342 ("%s: bad mbuf region for fl %p, maxp %d. " 4343 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp, 4344 sc->sge.sw_zone_info[zidx].size, region1, 4345 sc->sge.hw_buf_info[hwidx].size, region3)); 4346 } 4347 4348 fl->cll_def.zidx = zidx; 4349 fl->cll_def.hwidx = hwidx; 4350 fl->cll_def.region1 = region1; 4351 fl->cll_def.region3 = region3; 4352 } 4353 4354 static void 4355 find_safe_refill_source(struct adapter *sc, struct sge_fl *fl) 4356 { 4357 struct sge *s = &sc->sge; 4358 struct hw_buf_info *hwb; 4359 struct sw_zone_info *swz; 4360 int spare; 4361 int8_t hwidx; 4362 4363 if (fl->flags & FL_BUF_PACKING) 4364 hwidx = s->safe_hwidx2; /* with room for metadata */ 4365 else if (allow_mbufs_in_cluster && s->safe_hwidx2 != -1) { 4366 hwidx = s->safe_hwidx2; 4367 hwb = &s->hw_buf_info[hwidx]; 4368 swz = &s->sw_zone_info[hwb->zidx]; 4369 spare = swz->size - hwb->size; 4370 4371 /* no good if there isn't room for an mbuf as well */ 4372 if (spare < CL_METADATA_SIZE + MSIZE) 4373 hwidx = s->safe_hwidx1; 4374 } else 4375 hwidx = s->safe_hwidx1; 4376 4377 if (hwidx == -1) { 4378 /* No fallback source */ 4379 fl->cll_alt.hwidx = -1; 4380 fl->cll_alt.zidx = -1; 4381 4382 return; 4383 } 4384 4385 hwb = &s->hw_buf_info[hwidx]; 4386 swz = &s->sw_zone_info[hwb->zidx]; 4387 spare = swz->size - hwb->size; 4388 fl->cll_alt.hwidx = hwidx; 4389 fl->cll_alt.zidx = hwb->zidx; 4390 if (allow_mbufs_in_cluster) 4391 fl->cll_alt.region1 = ((spare - CL_METADATA_SIZE) / MSIZE) * MSIZE; 4392 else 4393 fl->cll_alt.region1 = 0; 4394 fl->cll_alt.region3 = spare - fl->cll_alt.region1; 4395 } 4396 4397 static void 4398 add_fl_to_sfl(struct adapter *sc, struct sge_fl *fl) 4399 { 4400 mtx_lock(&sc->sfl_lock); 4401 FL_LOCK(fl); 4402 if ((fl->flags & FL_DOOMED) == 0) { 4403 fl->flags |= FL_STARVING; 4404 TAILQ_INSERT_TAIL(&sc->sfl, fl, link); 4405 callout_reset(&sc->sfl_callout, hz / 5, refill_sfl, sc); 4406 } 4407 FL_UNLOCK(fl); 4408 mtx_unlock(&sc->sfl_lock); 4409 } 4410 4411 static int 4412 handle_sge_egr_update(struct sge_iq *iq, const struct rss_header *rss, 4413 struct mbuf *m) 4414 { 4415 const struct cpl_sge_egr_update *cpl = (const void *)(rss + 1); 4416 unsigned int qid = G_EGR_QID(ntohl(cpl->opcode_qid)); 4417 struct adapter *sc = iq->adapter; 4418 struct sge *s = &sc->sge; 4419 struct sge_eq *eq; 4420 4421 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 4422 rss->opcode)); 4423 4424 eq = s->eqmap[qid - s->eq_start]; 4425 EQ_LOCK(eq); 4426 KASSERT(eq->flags & EQ_CRFLUSHED, 4427 ("%s: unsolicited egress update", __func__)); 4428 eq->flags &= ~EQ_CRFLUSHED; 4429 eq->egr_update++; 4430 4431 if (__predict_false(eq->flags & EQ_DOOMED)) 4432 wakeup_one(eq); 4433 else if (eq->flags & EQ_STALLED && can_resume_tx(eq)) 4434 taskqueue_enqueue(sc->tq[eq->tx_chan], &eq->tx_task); 4435 EQ_UNLOCK(eq); 4436 4437 return (0); 4438 } 4439 4440 /* handle_fw_msg works for both fw4_msg and fw6_msg because this is valid */ 4441 CTASSERT(offsetof(struct cpl_fw4_msg, data) == \ 4442 offsetof(struct cpl_fw6_msg, data)); 4443 4444 static int 4445 handle_fw_msg(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 4446 { 4447 struct adapter *sc = iq->adapter; 4448 const struct cpl_fw6_msg *cpl = (const void *)(rss + 1); 4449 4450 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 4451 rss->opcode)); 4452 4453 if (cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL) { 4454 const struct rss_header *rss2; 4455 4456 rss2 = (const struct rss_header *)&cpl->data[0]; 4457 return (sc->cpl_handler[rss2->opcode](iq, rss2, m)); 4458 } 4459 4460 return (sc->fw_msg_handler[cpl->type](sc, &cpl->data[0])); 4461 } 4462 4463 static int 4464 sysctl_uint16(SYSCTL_HANDLER_ARGS) 4465 { 4466 uint16_t *id = arg1; 4467 int i = *id; 4468 4469 return sysctl_handle_int(oidp, &i, 0, req); 4470 } 4471 4472 static int 4473 sysctl_bufsizes(SYSCTL_HANDLER_ARGS) 4474 { 4475 struct sge *s = arg1; 4476 struct hw_buf_info *hwb = &s->hw_buf_info[0]; 4477 struct sw_zone_info *swz = &s->sw_zone_info[0]; 4478 int i, rc; 4479 struct sbuf sb; 4480 char c; 4481 4482 sbuf_new(&sb, NULL, 32, SBUF_AUTOEXTEND); 4483 for (i = 0; i < SGE_FLBUF_SIZES; i++, hwb++) { 4484 if (hwb->zidx >= 0 && swz[hwb->zidx].size <= largest_rx_cluster) 4485 c = '*'; 4486 else 4487 c = '\0'; 4488 4489 sbuf_printf(&sb, "%u%c ", hwb->size, c); 4490 } 4491 sbuf_trim(&sb); 4492 sbuf_finish(&sb); 4493 rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req); 4494 sbuf_delete(&sb); 4495 return (rc); 4496 } 4497