1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 Chelsio Communications, Inc. 5 * All rights reserved. 6 * Written by: Navdeep Parhar <np@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include "opt_inet.h" 34 #include "opt_inet6.h" 35 #include "opt_kern_tls.h" 36 #include "opt_ratelimit.h" 37 38 #include <sys/types.h> 39 #include <sys/eventhandler.h> 40 #include <sys/mbuf.h> 41 #include <sys/socket.h> 42 #include <sys/kernel.h> 43 #include <sys/ktls.h> 44 #include <sys/malloc.h> 45 #include <sys/queue.h> 46 #include <sys/sbuf.h> 47 #include <sys/taskqueue.h> 48 #include <sys/time.h> 49 #include <sys/sglist.h> 50 #include <sys/sysctl.h> 51 #include <sys/smp.h> 52 #include <sys/socketvar.h> 53 #include <sys/counter.h> 54 #include <net/bpf.h> 55 #include <net/ethernet.h> 56 #include <net/if.h> 57 #include <net/if_vlan_var.h> 58 #include <netinet/in.h> 59 #include <netinet/ip.h> 60 #include <netinet/ip6.h> 61 #include <netinet/tcp.h> 62 #include <netinet/udp.h> 63 #include <machine/in_cksum.h> 64 #include <machine/md_var.h> 65 #include <vm/vm.h> 66 #include <vm/pmap.h> 67 #ifdef DEV_NETMAP 68 #include <machine/bus.h> 69 #include <sys/selinfo.h> 70 #include <net/if_var.h> 71 #include <net/netmap.h> 72 #include <dev/netmap/netmap_kern.h> 73 #endif 74 75 #include "common/common.h" 76 #include "common/t4_regs.h" 77 #include "common/t4_regs_values.h" 78 #include "common/t4_msg.h" 79 #include "t4_l2t.h" 80 #include "t4_mp_ring.h" 81 82 #ifdef T4_PKT_TIMESTAMP 83 #define RX_COPY_THRESHOLD (MINCLSIZE - 8) 84 #else 85 #define RX_COPY_THRESHOLD MINCLSIZE 86 #endif 87 88 /* Internal mbuf flags stored in PH_loc.eight[1]. */ 89 #define MC_NOMAP 0x01 90 #define MC_RAW_WR 0x02 91 #define MC_TLS 0x04 92 93 /* 94 * Ethernet frames are DMA'd at this byte offset into the freelist buffer. 95 * 0-7 are valid values. 96 */ 97 static int fl_pktshift = 0; 98 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pktshift, CTLFLAG_RDTUN, &fl_pktshift, 0, 99 "payload DMA offset in rx buffer (bytes)"); 100 101 /* 102 * Pad ethernet payload up to this boundary. 103 * -1: driver should figure out a good value. 104 * 0: disable padding. 105 * Any power of 2 from 32 to 4096 (both inclusive) is also a valid value. 106 */ 107 int fl_pad = -1; 108 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pad, CTLFLAG_RDTUN, &fl_pad, 0, 109 "payload pad boundary (bytes)"); 110 111 /* 112 * Status page length. 113 * -1: driver should figure out a good value. 114 * 64 or 128 are the only other valid values. 115 */ 116 static int spg_len = -1; 117 SYSCTL_INT(_hw_cxgbe, OID_AUTO, spg_len, CTLFLAG_RDTUN, &spg_len, 0, 118 "status page size (bytes)"); 119 120 /* 121 * Congestion drops. 122 * -1: no congestion feedback (not recommended). 123 * 0: backpressure the channel instead of dropping packets right away. 124 * 1: no backpressure, drop packets for the congested queue immediately. 125 */ 126 static int cong_drop = 0; 127 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cong_drop, CTLFLAG_RDTUN, &cong_drop, 0, 128 "Congestion control for RX queues (0 = backpressure, 1 = drop"); 129 130 /* 131 * Deliver multiple frames in the same free list buffer if they fit. 132 * -1: let the driver decide whether to enable buffer packing or not. 133 * 0: disable buffer packing. 134 * 1: enable buffer packing. 135 */ 136 static int buffer_packing = -1; 137 SYSCTL_INT(_hw_cxgbe, OID_AUTO, buffer_packing, CTLFLAG_RDTUN, &buffer_packing, 138 0, "Enable buffer packing"); 139 140 /* 141 * Start next frame in a packed buffer at this boundary. 142 * -1: driver should figure out a good value. 143 * T4: driver will ignore this and use the same value as fl_pad above. 144 * T5: 16, or a power of 2 from 64 to 4096 (both inclusive) is a valid value. 145 */ 146 static int fl_pack = -1; 147 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pack, CTLFLAG_RDTUN, &fl_pack, 0, 148 "payload pack boundary (bytes)"); 149 150 /* 151 * Largest rx cluster size that the driver is allowed to allocate. 152 */ 153 static int largest_rx_cluster = MJUM16BYTES; 154 SYSCTL_INT(_hw_cxgbe, OID_AUTO, largest_rx_cluster, CTLFLAG_RDTUN, 155 &largest_rx_cluster, 0, "Largest rx cluster (bytes)"); 156 157 /* 158 * Size of cluster allocation that's most likely to succeed. The driver will 159 * fall back to this size if it fails to allocate clusters larger than this. 160 */ 161 static int safest_rx_cluster = PAGE_SIZE; 162 SYSCTL_INT(_hw_cxgbe, OID_AUTO, safest_rx_cluster, CTLFLAG_RDTUN, 163 &safest_rx_cluster, 0, "Safe rx cluster (bytes)"); 164 165 #ifdef RATELIMIT 166 /* 167 * Knob to control TCP timestamp rewriting, and the granularity of the tick used 168 * for rewriting. -1 and 0-3 are all valid values. 169 * -1: hardware should leave the TCP timestamps alone. 170 * 0: 1ms 171 * 1: 100us 172 * 2: 10us 173 * 3: 1us 174 */ 175 static int tsclk = -1; 176 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tsclk, CTLFLAG_RDTUN, &tsclk, 0, 177 "Control TCP timestamp rewriting when using pacing"); 178 179 static int eo_max_backlog = 1024 * 1024; 180 SYSCTL_INT(_hw_cxgbe, OID_AUTO, eo_max_backlog, CTLFLAG_RDTUN, &eo_max_backlog, 181 0, "Maximum backlog of ratelimited data per flow"); 182 #endif 183 184 /* 185 * The interrupt holdoff timers are multiplied by this value on T6+. 186 * 1 and 3-17 (both inclusive) are legal values. 187 */ 188 static int tscale = 1; 189 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tscale, CTLFLAG_RDTUN, &tscale, 0, 190 "Interrupt holdoff timer scale on T6+"); 191 192 /* 193 * Number of LRO entries in the lro_ctrl structure per rx queue. 194 */ 195 static int lro_entries = TCP_LRO_ENTRIES; 196 SYSCTL_INT(_hw_cxgbe, OID_AUTO, lro_entries, CTLFLAG_RDTUN, &lro_entries, 0, 197 "Number of LRO entries per RX queue"); 198 199 /* 200 * This enables presorting of frames before they're fed into tcp_lro_rx. 201 */ 202 static int lro_mbufs = 0; 203 SYSCTL_INT(_hw_cxgbe, OID_AUTO, lro_mbufs, CTLFLAG_RDTUN, &lro_mbufs, 0, 204 "Enable presorting of LRO frames"); 205 206 static int service_iq(struct sge_iq *, int); 207 static int service_iq_fl(struct sge_iq *, int); 208 static struct mbuf *get_fl_payload(struct adapter *, struct sge_fl *, uint32_t); 209 static int eth_rx(struct adapter *, struct sge_rxq *, const struct iq_desc *, 210 u_int); 211 static inline void init_iq(struct sge_iq *, struct adapter *, int, int, int); 212 static inline void init_fl(struct adapter *, struct sge_fl *, int, int, char *); 213 static inline void init_eq(struct adapter *, struct sge_eq *, int, int, uint8_t, 214 uint16_t, char *); 215 static int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *, 216 bus_addr_t *, void **); 217 static int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 218 void *); 219 static int alloc_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *, 220 int, int); 221 static int free_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *); 222 static void add_iq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *, 223 struct sge_iq *); 224 static void add_fl_sysctls(struct adapter *, struct sysctl_ctx_list *, 225 struct sysctl_oid *, struct sge_fl *); 226 static int alloc_fwq(struct adapter *); 227 static int free_fwq(struct adapter *); 228 static int alloc_ctrlq(struct adapter *, struct sge_wrq *, int, 229 struct sysctl_oid *); 230 static int alloc_rxq(struct vi_info *, struct sge_rxq *, int, int, 231 struct sysctl_oid *); 232 static int free_rxq(struct vi_info *, struct sge_rxq *); 233 #ifdef TCP_OFFLOAD 234 static int alloc_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *, int, int, 235 struct sysctl_oid *); 236 static int free_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *); 237 #endif 238 #ifdef DEV_NETMAP 239 static int alloc_nm_rxq(struct vi_info *, struct sge_nm_rxq *, int, int, 240 struct sysctl_oid *); 241 static int free_nm_rxq(struct vi_info *, struct sge_nm_rxq *); 242 static int alloc_nm_txq(struct vi_info *, struct sge_nm_txq *, int, int, 243 struct sysctl_oid *); 244 static int free_nm_txq(struct vi_info *, struct sge_nm_txq *); 245 #endif 246 static int ctrl_eq_alloc(struct adapter *, struct sge_eq *); 247 static int eth_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *); 248 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 249 static int ofld_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *); 250 #endif 251 static int alloc_eq(struct adapter *, struct vi_info *, struct sge_eq *); 252 static int free_eq(struct adapter *, struct sge_eq *); 253 static int alloc_wrq(struct adapter *, struct vi_info *, struct sge_wrq *, 254 struct sysctl_oid *); 255 static int free_wrq(struct adapter *, struct sge_wrq *); 256 static int alloc_txq(struct vi_info *, struct sge_txq *, int, 257 struct sysctl_oid *); 258 static int free_txq(struct vi_info *, struct sge_txq *); 259 static void oneseg_dma_callback(void *, bus_dma_segment_t *, int, int); 260 static inline void ring_fl_db(struct adapter *, struct sge_fl *); 261 static int refill_fl(struct adapter *, struct sge_fl *, int); 262 static void refill_sfl(void *); 263 static int alloc_fl_sdesc(struct sge_fl *); 264 static void free_fl_sdesc(struct adapter *, struct sge_fl *); 265 static int find_refill_source(struct adapter *, int, bool); 266 static void add_fl_to_sfl(struct adapter *, struct sge_fl *); 267 268 static inline void get_pkt_gl(struct mbuf *, struct sglist *); 269 static inline u_int txpkt_len16(u_int, u_int); 270 static inline u_int txpkt_vm_len16(u_int, u_int); 271 static inline u_int txpkts0_len16(u_int); 272 static inline u_int txpkts1_len16(void); 273 static u_int write_raw_wr(struct sge_txq *, void *, struct mbuf *, u_int); 274 static u_int write_txpkt_wr(struct adapter *, struct sge_txq *, struct mbuf *, 275 u_int); 276 static u_int write_txpkt_vm_wr(struct adapter *, struct sge_txq *, 277 struct mbuf *); 278 static int add_to_txpkts_vf(struct adapter *, struct sge_txq *, struct mbuf *, 279 int, bool *); 280 static int add_to_txpkts_pf(struct adapter *, struct sge_txq *, struct mbuf *, 281 int, bool *); 282 static u_int write_txpkts_wr(struct adapter *, struct sge_txq *); 283 static u_int write_txpkts_vm_wr(struct adapter *, struct sge_txq *); 284 static void write_gl_to_txd(struct sge_txq *, struct mbuf *, caddr_t *, int); 285 static inline void copy_to_txd(struct sge_eq *, caddr_t, caddr_t *, int); 286 static inline void ring_eq_db(struct adapter *, struct sge_eq *, u_int); 287 static inline uint16_t read_hw_cidx(struct sge_eq *); 288 static inline u_int reclaimable_tx_desc(struct sge_eq *); 289 static inline u_int total_available_tx_desc(struct sge_eq *); 290 static u_int reclaim_tx_descs(struct sge_txq *, u_int); 291 static void tx_reclaim(void *, int); 292 static __be64 get_flit(struct sglist_seg *, int, int); 293 static int handle_sge_egr_update(struct sge_iq *, const struct rss_header *, 294 struct mbuf *); 295 static int handle_fw_msg(struct sge_iq *, const struct rss_header *, 296 struct mbuf *); 297 static int t4_handle_wrerr_rpl(struct adapter *, const __be64 *); 298 static void wrq_tx_drain(void *, int); 299 static void drain_wrq_wr_list(struct adapter *, struct sge_wrq *); 300 301 static int sysctl_uint16(SYSCTL_HANDLER_ARGS); 302 static int sysctl_bufsizes(SYSCTL_HANDLER_ARGS); 303 #ifdef RATELIMIT 304 static inline u_int txpkt_eo_len16(u_int, u_int, u_int); 305 static int ethofld_fw4_ack(struct sge_iq *, const struct rss_header *, 306 struct mbuf *); 307 #endif 308 309 static counter_u64_t extfree_refs; 310 static counter_u64_t extfree_rels; 311 312 an_handler_t t4_an_handler; 313 fw_msg_handler_t t4_fw_msg_handler[NUM_FW6_TYPES]; 314 cpl_handler_t t4_cpl_handler[NUM_CPL_CMDS]; 315 cpl_handler_t set_tcb_rpl_handlers[NUM_CPL_COOKIES]; 316 cpl_handler_t l2t_write_rpl_handlers[NUM_CPL_COOKIES]; 317 cpl_handler_t act_open_rpl_handlers[NUM_CPL_COOKIES]; 318 cpl_handler_t abort_rpl_rss_handlers[NUM_CPL_COOKIES]; 319 cpl_handler_t fw4_ack_handlers[NUM_CPL_COOKIES]; 320 321 void 322 t4_register_an_handler(an_handler_t h) 323 { 324 uintptr_t *loc; 325 326 MPASS(h == NULL || t4_an_handler == NULL); 327 328 loc = (uintptr_t *)&t4_an_handler; 329 atomic_store_rel_ptr(loc, (uintptr_t)h); 330 } 331 332 void 333 t4_register_fw_msg_handler(int type, fw_msg_handler_t h) 334 { 335 uintptr_t *loc; 336 337 MPASS(type < nitems(t4_fw_msg_handler)); 338 MPASS(h == NULL || t4_fw_msg_handler[type] == NULL); 339 /* 340 * These are dispatched by the handler for FW{4|6}_CPL_MSG using the CPL 341 * handler dispatch table. Reject any attempt to install a handler for 342 * this subtype. 343 */ 344 MPASS(type != FW_TYPE_RSSCPL); 345 MPASS(type != FW6_TYPE_RSSCPL); 346 347 loc = (uintptr_t *)&t4_fw_msg_handler[type]; 348 atomic_store_rel_ptr(loc, (uintptr_t)h); 349 } 350 351 void 352 t4_register_cpl_handler(int opcode, cpl_handler_t h) 353 { 354 uintptr_t *loc; 355 356 MPASS(opcode < nitems(t4_cpl_handler)); 357 MPASS(h == NULL || t4_cpl_handler[opcode] == NULL); 358 359 loc = (uintptr_t *)&t4_cpl_handler[opcode]; 360 atomic_store_rel_ptr(loc, (uintptr_t)h); 361 } 362 363 static int 364 set_tcb_rpl_handler(struct sge_iq *iq, const struct rss_header *rss, 365 struct mbuf *m) 366 { 367 const struct cpl_set_tcb_rpl *cpl = (const void *)(rss + 1); 368 u_int tid; 369 int cookie; 370 371 MPASS(m == NULL); 372 373 tid = GET_TID(cpl); 374 if (is_hpftid(iq->adapter, tid) || is_ftid(iq->adapter, tid)) { 375 /* 376 * The return code for filter-write is put in the CPL cookie so 377 * we have to rely on the hardware tid (is_ftid) to determine 378 * that this is a response to a filter. 379 */ 380 cookie = CPL_COOKIE_FILTER; 381 } else { 382 cookie = G_COOKIE(cpl->cookie); 383 } 384 MPASS(cookie > CPL_COOKIE_RESERVED); 385 MPASS(cookie < nitems(set_tcb_rpl_handlers)); 386 387 return (set_tcb_rpl_handlers[cookie](iq, rss, m)); 388 } 389 390 static int 391 l2t_write_rpl_handler(struct sge_iq *iq, const struct rss_header *rss, 392 struct mbuf *m) 393 { 394 const struct cpl_l2t_write_rpl *rpl = (const void *)(rss + 1); 395 unsigned int cookie; 396 397 MPASS(m == NULL); 398 399 cookie = GET_TID(rpl) & F_SYNC_WR ? CPL_COOKIE_TOM : CPL_COOKIE_FILTER; 400 return (l2t_write_rpl_handlers[cookie](iq, rss, m)); 401 } 402 403 static int 404 act_open_rpl_handler(struct sge_iq *iq, const struct rss_header *rss, 405 struct mbuf *m) 406 { 407 const struct cpl_act_open_rpl *cpl = (const void *)(rss + 1); 408 u_int cookie = G_TID_COOKIE(G_AOPEN_ATID(be32toh(cpl->atid_status))); 409 410 MPASS(m == NULL); 411 MPASS(cookie != CPL_COOKIE_RESERVED); 412 413 return (act_open_rpl_handlers[cookie](iq, rss, m)); 414 } 415 416 static int 417 abort_rpl_rss_handler(struct sge_iq *iq, const struct rss_header *rss, 418 struct mbuf *m) 419 { 420 struct adapter *sc = iq->adapter; 421 u_int cookie; 422 423 MPASS(m == NULL); 424 if (is_hashfilter(sc)) 425 cookie = CPL_COOKIE_HASHFILTER; 426 else 427 cookie = CPL_COOKIE_TOM; 428 429 return (abort_rpl_rss_handlers[cookie](iq, rss, m)); 430 } 431 432 static int 433 fw4_ack_handler(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 434 { 435 struct adapter *sc = iq->adapter; 436 const struct cpl_fw4_ack *cpl = (const void *)(rss + 1); 437 unsigned int tid = G_CPL_FW4_ACK_FLOWID(be32toh(OPCODE_TID(cpl))); 438 u_int cookie; 439 440 MPASS(m == NULL); 441 if (is_etid(sc, tid)) 442 cookie = CPL_COOKIE_ETHOFLD; 443 else 444 cookie = CPL_COOKIE_TOM; 445 446 return (fw4_ack_handlers[cookie](iq, rss, m)); 447 } 448 449 static void 450 t4_init_shared_cpl_handlers(void) 451 { 452 453 t4_register_cpl_handler(CPL_SET_TCB_RPL, set_tcb_rpl_handler); 454 t4_register_cpl_handler(CPL_L2T_WRITE_RPL, l2t_write_rpl_handler); 455 t4_register_cpl_handler(CPL_ACT_OPEN_RPL, act_open_rpl_handler); 456 t4_register_cpl_handler(CPL_ABORT_RPL_RSS, abort_rpl_rss_handler); 457 t4_register_cpl_handler(CPL_FW4_ACK, fw4_ack_handler); 458 } 459 460 void 461 t4_register_shared_cpl_handler(int opcode, cpl_handler_t h, int cookie) 462 { 463 uintptr_t *loc; 464 465 MPASS(opcode < nitems(t4_cpl_handler)); 466 MPASS(cookie > CPL_COOKIE_RESERVED); 467 MPASS(cookie < NUM_CPL_COOKIES); 468 MPASS(t4_cpl_handler[opcode] != NULL); 469 470 switch (opcode) { 471 case CPL_SET_TCB_RPL: 472 loc = (uintptr_t *)&set_tcb_rpl_handlers[cookie]; 473 break; 474 case CPL_L2T_WRITE_RPL: 475 loc = (uintptr_t *)&l2t_write_rpl_handlers[cookie]; 476 break; 477 case CPL_ACT_OPEN_RPL: 478 loc = (uintptr_t *)&act_open_rpl_handlers[cookie]; 479 break; 480 case CPL_ABORT_RPL_RSS: 481 loc = (uintptr_t *)&abort_rpl_rss_handlers[cookie]; 482 break; 483 case CPL_FW4_ACK: 484 loc = (uintptr_t *)&fw4_ack_handlers[cookie]; 485 break; 486 default: 487 MPASS(0); 488 return; 489 } 490 MPASS(h == NULL || *loc == (uintptr_t)NULL); 491 atomic_store_rel_ptr(loc, (uintptr_t)h); 492 } 493 494 /* 495 * Called on MOD_LOAD. Validates and calculates the SGE tunables. 496 */ 497 void 498 t4_sge_modload(void) 499 { 500 501 if (fl_pktshift < 0 || fl_pktshift > 7) { 502 printf("Invalid hw.cxgbe.fl_pktshift value (%d)," 503 " using 0 instead.\n", fl_pktshift); 504 fl_pktshift = 0; 505 } 506 507 if (spg_len != 64 && spg_len != 128) { 508 int len; 509 510 #if defined(__i386__) || defined(__amd64__) 511 len = cpu_clflush_line_size > 64 ? 128 : 64; 512 #else 513 len = 64; 514 #endif 515 if (spg_len != -1) { 516 printf("Invalid hw.cxgbe.spg_len value (%d)," 517 " using %d instead.\n", spg_len, len); 518 } 519 spg_len = len; 520 } 521 522 if (cong_drop < -1 || cong_drop > 1) { 523 printf("Invalid hw.cxgbe.cong_drop value (%d)," 524 " using 0 instead.\n", cong_drop); 525 cong_drop = 0; 526 } 527 528 if (tscale != 1 && (tscale < 3 || tscale > 17)) { 529 printf("Invalid hw.cxgbe.tscale value (%d)," 530 " using 1 instead.\n", tscale); 531 tscale = 1; 532 } 533 534 extfree_refs = counter_u64_alloc(M_WAITOK); 535 extfree_rels = counter_u64_alloc(M_WAITOK); 536 counter_u64_zero(extfree_refs); 537 counter_u64_zero(extfree_rels); 538 539 t4_init_shared_cpl_handlers(); 540 t4_register_cpl_handler(CPL_FW4_MSG, handle_fw_msg); 541 t4_register_cpl_handler(CPL_FW6_MSG, handle_fw_msg); 542 t4_register_cpl_handler(CPL_SGE_EGR_UPDATE, handle_sge_egr_update); 543 #ifdef RATELIMIT 544 t4_register_shared_cpl_handler(CPL_FW4_ACK, ethofld_fw4_ack, 545 CPL_COOKIE_ETHOFLD); 546 #endif 547 t4_register_fw_msg_handler(FW6_TYPE_CMD_RPL, t4_handle_fw_rpl); 548 t4_register_fw_msg_handler(FW6_TYPE_WRERR_RPL, t4_handle_wrerr_rpl); 549 } 550 551 void 552 t4_sge_modunload(void) 553 { 554 555 counter_u64_free(extfree_refs); 556 counter_u64_free(extfree_rels); 557 } 558 559 uint64_t 560 t4_sge_extfree_refs(void) 561 { 562 uint64_t refs, rels; 563 564 rels = counter_u64_fetch(extfree_rels); 565 refs = counter_u64_fetch(extfree_refs); 566 567 return (refs - rels); 568 } 569 570 /* max 4096 */ 571 #define MAX_PACK_BOUNDARY 512 572 573 static inline void 574 setup_pad_and_pack_boundaries(struct adapter *sc) 575 { 576 uint32_t v, m; 577 int pad, pack, pad_shift; 578 579 pad_shift = chip_id(sc) > CHELSIO_T5 ? X_T6_INGPADBOUNDARY_SHIFT : 580 X_INGPADBOUNDARY_SHIFT; 581 pad = fl_pad; 582 if (fl_pad < (1 << pad_shift) || 583 fl_pad > (1 << (pad_shift + M_INGPADBOUNDARY)) || 584 !powerof2(fl_pad)) { 585 /* 586 * If there is any chance that we might use buffer packing and 587 * the chip is a T4, then pick 64 as the pad/pack boundary. Set 588 * it to the minimum allowed in all other cases. 589 */ 590 pad = is_t4(sc) && buffer_packing ? 64 : 1 << pad_shift; 591 592 /* 593 * For fl_pad = 0 we'll still write a reasonable value to the 594 * register but all the freelists will opt out of padding. 595 * We'll complain here only if the user tried to set it to a 596 * value greater than 0 that was invalid. 597 */ 598 if (fl_pad > 0) { 599 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pad value" 600 " (%d), using %d instead.\n", fl_pad, pad); 601 } 602 } 603 m = V_INGPADBOUNDARY(M_INGPADBOUNDARY); 604 v = V_INGPADBOUNDARY(ilog2(pad) - pad_shift); 605 t4_set_reg_field(sc, A_SGE_CONTROL, m, v); 606 607 if (is_t4(sc)) { 608 if (fl_pack != -1 && fl_pack != pad) { 609 /* Complain but carry on. */ 610 device_printf(sc->dev, "hw.cxgbe.fl_pack (%d) ignored," 611 " using %d instead.\n", fl_pack, pad); 612 } 613 return; 614 } 615 616 pack = fl_pack; 617 if (fl_pack < 16 || fl_pack == 32 || fl_pack > 4096 || 618 !powerof2(fl_pack)) { 619 if (sc->params.pci.mps > MAX_PACK_BOUNDARY) 620 pack = MAX_PACK_BOUNDARY; 621 else 622 pack = max(sc->params.pci.mps, CACHE_LINE_SIZE); 623 MPASS(powerof2(pack)); 624 if (pack < 16) 625 pack = 16; 626 if (pack == 32) 627 pack = 64; 628 if (pack > 4096) 629 pack = 4096; 630 if (fl_pack != -1) { 631 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pack value" 632 " (%d), using %d instead.\n", fl_pack, pack); 633 } 634 } 635 m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY); 636 if (pack == 16) 637 v = V_INGPACKBOUNDARY(0); 638 else 639 v = V_INGPACKBOUNDARY(ilog2(pack) - 5); 640 641 MPASS(!is_t4(sc)); /* T4 doesn't have SGE_CONTROL2 */ 642 t4_set_reg_field(sc, A_SGE_CONTROL2, m, v); 643 } 644 645 /* 646 * adap->params.vpd.cclk must be set up before this is called. 647 */ 648 void 649 t4_tweak_chip_settings(struct adapter *sc) 650 { 651 int i, reg; 652 uint32_t v, m; 653 int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200}; 654 int timer_max = M_TIMERVALUE0 * 1000 / sc->params.vpd.cclk; 655 int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */ 656 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 657 static int sw_buf_sizes[] = { 658 MCLBYTES, 659 #if MJUMPAGESIZE != MCLBYTES 660 MJUMPAGESIZE, 661 #endif 662 MJUM9BYTES, 663 MJUM16BYTES 664 }; 665 666 KASSERT(sc->flags & MASTER_PF, 667 ("%s: trying to change chip settings when not master.", __func__)); 668 669 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE; 670 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE | 671 V_EGRSTATUSPAGESIZE(spg_len == 128); 672 t4_set_reg_field(sc, A_SGE_CONTROL, m, v); 673 674 setup_pad_and_pack_boundaries(sc); 675 676 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) | 677 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) | 678 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) | 679 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) | 680 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) | 681 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) | 682 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) | 683 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10); 684 t4_write_reg(sc, A_SGE_HOST_PAGE_SIZE, v); 685 686 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0, 4096); 687 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE1, 65536); 688 reg = A_SGE_FL_BUFFER_SIZE2; 689 for (i = 0; i < nitems(sw_buf_sizes); i++) { 690 MPASS(reg <= A_SGE_FL_BUFFER_SIZE15); 691 t4_write_reg(sc, reg, sw_buf_sizes[i]); 692 reg += 4; 693 MPASS(reg <= A_SGE_FL_BUFFER_SIZE15); 694 t4_write_reg(sc, reg, sw_buf_sizes[i] - CL_METADATA_SIZE); 695 reg += 4; 696 } 697 698 v = V_THRESHOLD_0(intr_pktcount[0]) | V_THRESHOLD_1(intr_pktcount[1]) | 699 V_THRESHOLD_2(intr_pktcount[2]) | V_THRESHOLD_3(intr_pktcount[3]); 700 t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD, v); 701 702 KASSERT(intr_timer[0] <= timer_max, 703 ("%s: not a single usable timer (%d, %d)", __func__, intr_timer[0], 704 timer_max)); 705 for (i = 1; i < nitems(intr_timer); i++) { 706 KASSERT(intr_timer[i] >= intr_timer[i - 1], 707 ("%s: timers not listed in increasing order (%d)", 708 __func__, i)); 709 710 while (intr_timer[i] > timer_max) { 711 if (i == nitems(intr_timer) - 1) { 712 intr_timer[i] = timer_max; 713 break; 714 } 715 intr_timer[i] += intr_timer[i - 1]; 716 intr_timer[i] /= 2; 717 } 718 } 719 720 v = V_TIMERVALUE0(us_to_core_ticks(sc, intr_timer[0])) | 721 V_TIMERVALUE1(us_to_core_ticks(sc, intr_timer[1])); 722 t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1, v); 723 v = V_TIMERVALUE2(us_to_core_ticks(sc, intr_timer[2])) | 724 V_TIMERVALUE3(us_to_core_ticks(sc, intr_timer[3])); 725 t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3, v); 726 v = V_TIMERVALUE4(us_to_core_ticks(sc, intr_timer[4])) | 727 V_TIMERVALUE5(us_to_core_ticks(sc, intr_timer[5])); 728 t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5, v); 729 730 if (chip_id(sc) >= CHELSIO_T6) { 731 m = V_TSCALE(M_TSCALE); 732 if (tscale == 1) 733 v = 0; 734 else 735 v = V_TSCALE(tscale - 2); 736 t4_set_reg_field(sc, A_SGE_ITP_CONTROL, m, v); 737 738 if (sc->debug_flags & DF_DISABLE_TCB_CACHE) { 739 m = V_RDTHRESHOLD(M_RDTHRESHOLD) | F_WRTHRTHRESHEN | 740 V_WRTHRTHRESH(M_WRTHRTHRESH); 741 t4_tp_pio_read(sc, &v, 1, A_TP_CMM_CONFIG, 1); 742 v &= ~m; 743 v |= V_RDTHRESHOLD(1) | F_WRTHRTHRESHEN | 744 V_WRTHRTHRESH(16); 745 t4_tp_pio_write(sc, &v, 1, A_TP_CMM_CONFIG, 1); 746 } 747 } 748 749 /* 4K, 16K, 64K, 256K DDP "page sizes" for TDDP */ 750 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 751 t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, v); 752 753 /* 754 * 4K, 8K, 16K, 64K DDP "page sizes" for iSCSI DDP. These have been 755 * chosen with MAXPHYS = 128K in mind. The largest DDP buffer that we 756 * may have to deal with is MAXPHYS + 1 page. 757 */ 758 v = V_HPZ0(0) | V_HPZ1(1) | V_HPZ2(2) | V_HPZ3(4); 759 t4_write_reg(sc, A_ULP_RX_ISCSI_PSZ, v); 760 761 /* We use multiple DDP page sizes both in plain-TOE and ISCSI modes. */ 762 m = v = F_TDDPTAGTCB | F_ISCSITAGTCB; 763 t4_set_reg_field(sc, A_ULP_RX_CTL, m, v); 764 765 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 766 F_RESETDDPOFFSET; 767 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 768 t4_set_reg_field(sc, A_TP_PARA_REG5, m, v); 769 } 770 771 /* 772 * SGE wants the buffer to be at least 64B and then a multiple of 16. Its 773 * address mut be 16B aligned. If padding is in use the buffer's start and end 774 * need to be aligned to the pad boundary as well. We'll just make sure that 775 * the size is a multiple of the pad boundary here, it is up to the buffer 776 * allocation code to make sure the start of the buffer is aligned. 777 */ 778 static inline int 779 hwsz_ok(struct adapter *sc, int hwsz) 780 { 781 int mask = fl_pad ? sc->params.sge.pad_boundary - 1 : 16 - 1; 782 783 return (hwsz >= 64 && (hwsz & mask) == 0); 784 } 785 786 /* 787 * XXX: driver really should be able to deal with unexpected settings. 788 */ 789 int 790 t4_read_chip_settings(struct adapter *sc) 791 { 792 struct sge *s = &sc->sge; 793 struct sge_params *sp = &sc->params.sge; 794 int i, j, n, rc = 0; 795 uint32_t m, v, r; 796 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 797 static int sw_buf_sizes[] = { /* Sorted by size */ 798 MCLBYTES, 799 #if MJUMPAGESIZE != MCLBYTES 800 MJUMPAGESIZE, 801 #endif 802 MJUM9BYTES, 803 MJUM16BYTES 804 }; 805 struct rx_buf_info *rxb; 806 807 m = F_RXPKTCPLMODE; 808 v = F_RXPKTCPLMODE; 809 r = sc->params.sge.sge_control; 810 if ((r & m) != v) { 811 device_printf(sc->dev, "invalid SGE_CONTROL(0x%x)\n", r); 812 rc = EINVAL; 813 } 814 815 /* 816 * If this changes then every single use of PAGE_SHIFT in the driver 817 * needs to be carefully reviewed for PAGE_SHIFT vs sp->page_shift. 818 */ 819 if (sp->page_shift != PAGE_SHIFT) { 820 device_printf(sc->dev, "invalid SGE_HOST_PAGE_SIZE(0x%x)\n", r); 821 rc = EINVAL; 822 } 823 824 s->safe_zidx = -1; 825 rxb = &s->rx_buf_info[0]; 826 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) { 827 rxb->size1 = sw_buf_sizes[i]; 828 rxb->zone = m_getzone(rxb->size1); 829 rxb->type = m_gettype(rxb->size1); 830 rxb->size2 = 0; 831 rxb->hwidx1 = -1; 832 rxb->hwidx2 = -1; 833 for (j = 0; j < SGE_FLBUF_SIZES; j++) { 834 int hwsize = sp->sge_fl_buffer_size[j]; 835 836 if (!hwsz_ok(sc, hwsize)) 837 continue; 838 839 /* hwidx for size1 */ 840 if (rxb->hwidx1 == -1 && rxb->size1 == hwsize) 841 rxb->hwidx1 = j; 842 843 /* hwidx for size2 (buffer packing) */ 844 if (rxb->size1 - CL_METADATA_SIZE < hwsize) 845 continue; 846 n = rxb->size1 - hwsize - CL_METADATA_SIZE; 847 if (n == 0) { 848 rxb->hwidx2 = j; 849 rxb->size2 = hwsize; 850 break; /* stop looking */ 851 } 852 if (rxb->hwidx2 != -1) { 853 if (n < sp->sge_fl_buffer_size[rxb->hwidx2] - 854 hwsize - CL_METADATA_SIZE) { 855 rxb->hwidx2 = j; 856 rxb->size2 = hwsize; 857 } 858 } else if (n <= 2 * CL_METADATA_SIZE) { 859 rxb->hwidx2 = j; 860 rxb->size2 = hwsize; 861 } 862 } 863 if (rxb->hwidx2 != -1) 864 sc->flags |= BUF_PACKING_OK; 865 if (s->safe_zidx == -1 && rxb->size1 == safest_rx_cluster) 866 s->safe_zidx = i; 867 } 868 869 if (sc->flags & IS_VF) 870 return (0); 871 872 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 873 r = t4_read_reg(sc, A_ULP_RX_TDDP_PSZ); 874 if (r != v) { 875 device_printf(sc->dev, "invalid ULP_RX_TDDP_PSZ(0x%x)\n", r); 876 rc = EINVAL; 877 } 878 879 m = v = F_TDDPTAGTCB; 880 r = t4_read_reg(sc, A_ULP_RX_CTL); 881 if ((r & m) != v) { 882 device_printf(sc->dev, "invalid ULP_RX_CTL(0x%x)\n", r); 883 rc = EINVAL; 884 } 885 886 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 887 F_RESETDDPOFFSET; 888 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 889 r = t4_read_reg(sc, A_TP_PARA_REG5); 890 if ((r & m) != v) { 891 device_printf(sc->dev, "invalid TP_PARA_REG5(0x%x)\n", r); 892 rc = EINVAL; 893 } 894 895 t4_init_tp_params(sc, 1); 896 897 t4_read_mtu_tbl(sc, sc->params.mtus, NULL); 898 t4_load_mtus(sc, sc->params.mtus, sc->params.a_wnd, sc->params.b_wnd); 899 900 return (rc); 901 } 902 903 int 904 t4_create_dma_tag(struct adapter *sc) 905 { 906 int rc; 907 908 rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0, 909 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE, 910 BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL, 911 NULL, &sc->dmat); 912 if (rc != 0) { 913 device_printf(sc->dev, 914 "failed to create main DMA tag: %d\n", rc); 915 } 916 917 return (rc); 918 } 919 920 void 921 t4_sge_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx, 922 struct sysctl_oid_list *children) 923 { 924 struct sge_params *sp = &sc->params.sge; 925 926 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "buffer_sizes", 927 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 928 sysctl_bufsizes, "A", "freelist buffer sizes"); 929 930 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pktshift", CTLFLAG_RD, 931 NULL, sp->fl_pktshift, "payload DMA offset in rx buffer (bytes)"); 932 933 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pad", CTLFLAG_RD, 934 NULL, sp->pad_boundary, "payload pad boundary (bytes)"); 935 936 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "spg_len", CTLFLAG_RD, 937 NULL, sp->spg_len, "status page size (bytes)"); 938 939 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_drop", CTLFLAG_RD, 940 NULL, cong_drop, "congestion drop setting"); 941 942 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pack", CTLFLAG_RD, 943 NULL, sp->pack_boundary, "payload pack boundary (bytes)"); 944 } 945 946 int 947 t4_destroy_dma_tag(struct adapter *sc) 948 { 949 if (sc->dmat) 950 bus_dma_tag_destroy(sc->dmat); 951 952 return (0); 953 } 954 955 /* 956 * Allocate and initialize the firmware event queue, control queues, and special 957 * purpose rx queues owned by the adapter. 958 * 959 * Returns errno on failure. Resources allocated up to that point may still be 960 * allocated. Caller is responsible for cleanup in case this function fails. 961 */ 962 int 963 t4_setup_adapter_queues(struct adapter *sc) 964 { 965 struct sysctl_oid *oid; 966 struct sysctl_oid_list *children; 967 int rc, i; 968 969 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 970 971 sysctl_ctx_init(&sc->ctx); 972 sc->flags |= ADAP_SYSCTL_CTX; 973 974 /* 975 * Firmware event queue 976 */ 977 rc = alloc_fwq(sc); 978 if (rc != 0) 979 return (rc); 980 981 /* 982 * That's all for the VF driver. 983 */ 984 if (sc->flags & IS_VF) 985 return (rc); 986 987 oid = device_get_sysctl_tree(sc->dev); 988 children = SYSCTL_CHILDREN(oid); 989 990 /* 991 * XXX: General purpose rx queues, one per port. 992 */ 993 994 /* 995 * Control queues, one per port. 996 */ 997 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "ctrlq", 998 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "control queues"); 999 for_each_port(sc, i) { 1000 struct sge_wrq *ctrlq = &sc->sge.ctrlq[i]; 1001 1002 rc = alloc_ctrlq(sc, ctrlq, i, oid); 1003 if (rc != 0) 1004 return (rc); 1005 } 1006 1007 return (rc); 1008 } 1009 1010 /* 1011 * Idempotent 1012 */ 1013 int 1014 t4_teardown_adapter_queues(struct adapter *sc) 1015 { 1016 int i; 1017 1018 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 1019 1020 /* Do this before freeing the queue */ 1021 if (sc->flags & ADAP_SYSCTL_CTX) { 1022 sysctl_ctx_free(&sc->ctx); 1023 sc->flags &= ~ADAP_SYSCTL_CTX; 1024 } 1025 1026 if (!(sc->flags & IS_VF)) { 1027 for_each_port(sc, i) 1028 free_wrq(sc, &sc->sge.ctrlq[i]); 1029 } 1030 free_fwq(sc); 1031 1032 return (0); 1033 } 1034 1035 /* Maximum payload that could arrive with a single iq descriptor. */ 1036 static inline int 1037 max_rx_payload(struct adapter *sc, struct ifnet *ifp, const bool ofld) 1038 { 1039 int maxp; 1040 1041 /* large enough even when hw VLAN extraction is disabled */ 1042 maxp = sc->params.sge.fl_pktshift + ETHER_HDR_LEN + 1043 ETHER_VLAN_ENCAP_LEN + ifp->if_mtu; 1044 if (ofld && sc->tt.tls && sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS && 1045 maxp < sc->params.tp.max_rx_pdu) 1046 maxp = sc->params.tp.max_rx_pdu; 1047 return (maxp); 1048 } 1049 1050 int 1051 t4_setup_vi_queues(struct vi_info *vi) 1052 { 1053 int rc = 0, i, intr_idx, iqidx; 1054 struct sge_rxq *rxq; 1055 struct sge_txq *txq; 1056 #ifdef TCP_OFFLOAD 1057 struct sge_ofld_rxq *ofld_rxq; 1058 #endif 1059 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1060 struct sge_wrq *ofld_txq; 1061 #endif 1062 #ifdef DEV_NETMAP 1063 int saved_idx; 1064 struct sge_nm_rxq *nm_rxq; 1065 struct sge_nm_txq *nm_txq; 1066 #endif 1067 char name[16]; 1068 struct port_info *pi = vi->pi; 1069 struct adapter *sc = pi->adapter; 1070 struct ifnet *ifp = vi->ifp; 1071 struct sysctl_oid *oid = device_get_sysctl_tree(vi->dev); 1072 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 1073 int maxp; 1074 1075 /* Interrupt vector to start from (when using multiple vectors) */ 1076 intr_idx = vi->first_intr; 1077 1078 #ifdef DEV_NETMAP 1079 saved_idx = intr_idx; 1080 if (ifp->if_capabilities & IFCAP_NETMAP) { 1081 1082 /* netmap is supported with direct interrupts only. */ 1083 MPASS(!forwarding_intr_to_fwq(sc)); 1084 1085 /* 1086 * We don't have buffers to back the netmap rx queues 1087 * right now so we create the queues in a way that 1088 * doesn't set off any congestion signal in the chip. 1089 */ 1090 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "nm_rxq", 1091 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "rx queues"); 1092 for_each_nm_rxq(vi, i, nm_rxq) { 1093 rc = alloc_nm_rxq(vi, nm_rxq, intr_idx, i, oid); 1094 if (rc != 0) 1095 goto done; 1096 intr_idx++; 1097 } 1098 1099 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "nm_txq", 1100 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "tx queues"); 1101 for_each_nm_txq(vi, i, nm_txq) { 1102 iqidx = vi->first_nm_rxq + (i % vi->nnmrxq); 1103 rc = alloc_nm_txq(vi, nm_txq, iqidx, i, oid); 1104 if (rc != 0) 1105 goto done; 1106 } 1107 } 1108 1109 /* Normal rx queues and netmap rx queues share the same interrupts. */ 1110 intr_idx = saved_idx; 1111 #endif 1112 1113 /* 1114 * Allocate rx queues first because a default iqid is required when 1115 * creating a tx queue. 1116 */ 1117 maxp = max_rx_payload(sc, ifp, false); 1118 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "rxq", 1119 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "rx queues"); 1120 for_each_rxq(vi, i, rxq) { 1121 1122 init_iq(&rxq->iq, sc, vi->tmr_idx, vi->pktc_idx, vi->qsize_rxq); 1123 1124 snprintf(name, sizeof(name), "%s rxq%d-fl", 1125 device_get_nameunit(vi->dev), i); 1126 init_fl(sc, &rxq->fl, vi->qsize_rxq / 8, maxp, name); 1127 1128 rc = alloc_rxq(vi, rxq, 1129 forwarding_intr_to_fwq(sc) ? -1 : intr_idx, i, oid); 1130 if (rc != 0) 1131 goto done; 1132 intr_idx++; 1133 } 1134 #ifdef DEV_NETMAP 1135 if (ifp->if_capabilities & IFCAP_NETMAP) 1136 intr_idx = saved_idx + max(vi->nrxq, vi->nnmrxq); 1137 #endif 1138 #ifdef TCP_OFFLOAD 1139 maxp = max_rx_payload(sc, ifp, true); 1140 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_rxq", 1141 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "rx queues for offloaded TCP connections"); 1142 for_each_ofld_rxq(vi, i, ofld_rxq) { 1143 1144 init_iq(&ofld_rxq->iq, sc, vi->ofld_tmr_idx, vi->ofld_pktc_idx, 1145 vi->qsize_rxq); 1146 1147 snprintf(name, sizeof(name), "%s ofld_rxq%d-fl", 1148 device_get_nameunit(vi->dev), i); 1149 init_fl(sc, &ofld_rxq->fl, vi->qsize_rxq / 8, maxp, name); 1150 1151 rc = alloc_ofld_rxq(vi, ofld_rxq, 1152 forwarding_intr_to_fwq(sc) ? -1 : intr_idx, i, oid); 1153 if (rc != 0) 1154 goto done; 1155 intr_idx++; 1156 } 1157 #endif 1158 1159 /* 1160 * Now the tx queues. 1161 */ 1162 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "txq", 1163 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "tx queues"); 1164 for_each_txq(vi, i, txq) { 1165 iqidx = vi->first_rxq + (i % vi->nrxq); 1166 snprintf(name, sizeof(name), "%s txq%d", 1167 device_get_nameunit(vi->dev), i); 1168 init_eq(sc, &txq->eq, EQ_ETH, vi->qsize_txq, pi->tx_chan, 1169 sc->sge.rxq[iqidx].iq.cntxt_id, name); 1170 1171 rc = alloc_txq(vi, txq, i, oid); 1172 if (rc != 0) 1173 goto done; 1174 } 1175 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1176 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_txq", 1177 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "tx queues for TOE/ETHOFLD"); 1178 for_each_ofld_txq(vi, i, ofld_txq) { 1179 struct sysctl_oid *oid2; 1180 1181 snprintf(name, sizeof(name), "%s ofld_txq%d", 1182 device_get_nameunit(vi->dev), i); 1183 if (vi->nofldrxq > 0) { 1184 iqidx = vi->first_ofld_rxq + (i % vi->nofldrxq); 1185 init_eq(sc, &ofld_txq->eq, EQ_OFLD, vi->qsize_txq, 1186 pi->tx_chan, sc->sge.ofld_rxq[iqidx].iq.cntxt_id, 1187 name); 1188 } else { 1189 iqidx = vi->first_rxq + (i % vi->nrxq); 1190 init_eq(sc, &ofld_txq->eq, EQ_OFLD, vi->qsize_txq, 1191 pi->tx_chan, sc->sge.rxq[iqidx].iq.cntxt_id, name); 1192 } 1193 1194 snprintf(name, sizeof(name), "%d", i); 1195 oid2 = SYSCTL_ADD_NODE(&vi->ctx, SYSCTL_CHILDREN(oid), OID_AUTO, 1196 name, CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "offload tx queue"); 1197 1198 rc = alloc_wrq(sc, vi, ofld_txq, oid2); 1199 if (rc != 0) 1200 goto done; 1201 } 1202 #endif 1203 done: 1204 if (rc) 1205 t4_teardown_vi_queues(vi); 1206 1207 return (rc); 1208 } 1209 1210 /* 1211 * Idempotent 1212 */ 1213 int 1214 t4_teardown_vi_queues(struct vi_info *vi) 1215 { 1216 int i; 1217 struct sge_rxq *rxq; 1218 struct sge_txq *txq; 1219 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1220 struct port_info *pi = vi->pi; 1221 struct adapter *sc = pi->adapter; 1222 struct sge_wrq *ofld_txq; 1223 #endif 1224 #ifdef TCP_OFFLOAD 1225 struct sge_ofld_rxq *ofld_rxq; 1226 #endif 1227 #ifdef DEV_NETMAP 1228 struct sge_nm_rxq *nm_rxq; 1229 struct sge_nm_txq *nm_txq; 1230 #endif 1231 1232 /* Do this before freeing the queues */ 1233 if (vi->flags & VI_SYSCTL_CTX) { 1234 sysctl_ctx_free(&vi->ctx); 1235 vi->flags &= ~VI_SYSCTL_CTX; 1236 } 1237 1238 #ifdef DEV_NETMAP 1239 if (vi->ifp->if_capabilities & IFCAP_NETMAP) { 1240 for_each_nm_txq(vi, i, nm_txq) { 1241 free_nm_txq(vi, nm_txq); 1242 } 1243 1244 for_each_nm_rxq(vi, i, nm_rxq) { 1245 free_nm_rxq(vi, nm_rxq); 1246 } 1247 } 1248 #endif 1249 1250 /* 1251 * Take down all the tx queues first, as they reference the rx queues 1252 * (for egress updates, etc.). 1253 */ 1254 1255 for_each_txq(vi, i, txq) { 1256 free_txq(vi, txq); 1257 } 1258 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1259 for_each_ofld_txq(vi, i, ofld_txq) { 1260 free_wrq(sc, ofld_txq); 1261 } 1262 #endif 1263 1264 /* 1265 * Then take down the rx queues. 1266 */ 1267 1268 for_each_rxq(vi, i, rxq) { 1269 free_rxq(vi, rxq); 1270 } 1271 #ifdef TCP_OFFLOAD 1272 for_each_ofld_rxq(vi, i, ofld_rxq) { 1273 free_ofld_rxq(vi, ofld_rxq); 1274 } 1275 #endif 1276 1277 return (0); 1278 } 1279 1280 /* 1281 * Interrupt handler when the driver is using only 1 interrupt. This is a very 1282 * unusual scenario. 1283 * 1284 * a) Deals with errors, if any. 1285 * b) Services firmware event queue, which is taking interrupts for all other 1286 * queues. 1287 */ 1288 void 1289 t4_intr_all(void *arg) 1290 { 1291 struct adapter *sc = arg; 1292 struct sge_iq *fwq = &sc->sge.fwq; 1293 1294 MPASS(sc->intr_count == 1); 1295 1296 if (sc->intr_type == INTR_INTX) 1297 t4_write_reg(sc, MYPF_REG(A_PCIE_PF_CLI), 0); 1298 1299 t4_intr_err(arg); 1300 t4_intr_evt(fwq); 1301 } 1302 1303 /* 1304 * Interrupt handler for errors (installed directly when multiple interrupts are 1305 * being used, or called by t4_intr_all). 1306 */ 1307 void 1308 t4_intr_err(void *arg) 1309 { 1310 struct adapter *sc = arg; 1311 uint32_t v; 1312 const bool verbose = (sc->debug_flags & DF_VERBOSE_SLOWINTR) != 0; 1313 1314 if (sc->flags & ADAP_ERR) 1315 return; 1316 1317 v = t4_read_reg(sc, MYPF_REG(A_PL_PF_INT_CAUSE)); 1318 if (v & F_PFSW) { 1319 sc->swintr++; 1320 t4_write_reg(sc, MYPF_REG(A_PL_PF_INT_CAUSE), v); 1321 } 1322 1323 t4_slow_intr_handler(sc, verbose); 1324 } 1325 1326 /* 1327 * Interrupt handler for iq-only queues. The firmware event queue is the only 1328 * such queue right now. 1329 */ 1330 void 1331 t4_intr_evt(void *arg) 1332 { 1333 struct sge_iq *iq = arg; 1334 1335 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 1336 service_iq(iq, 0); 1337 (void) atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 1338 } 1339 } 1340 1341 /* 1342 * Interrupt handler for iq+fl queues. 1343 */ 1344 void 1345 t4_intr(void *arg) 1346 { 1347 struct sge_iq *iq = arg; 1348 1349 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 1350 service_iq_fl(iq, 0); 1351 (void) atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 1352 } 1353 } 1354 1355 #ifdef DEV_NETMAP 1356 /* 1357 * Interrupt handler for netmap rx queues. 1358 */ 1359 void 1360 t4_nm_intr(void *arg) 1361 { 1362 struct sge_nm_rxq *nm_rxq = arg; 1363 1364 if (atomic_cmpset_int(&nm_rxq->nm_state, NM_ON, NM_BUSY)) { 1365 service_nm_rxq(nm_rxq); 1366 (void) atomic_cmpset_int(&nm_rxq->nm_state, NM_BUSY, NM_ON); 1367 } 1368 } 1369 1370 /* 1371 * Interrupt handler for vectors shared between NIC and netmap rx queues. 1372 */ 1373 void 1374 t4_vi_intr(void *arg) 1375 { 1376 struct irq *irq = arg; 1377 1378 MPASS(irq->nm_rxq != NULL); 1379 t4_nm_intr(irq->nm_rxq); 1380 1381 MPASS(irq->rxq != NULL); 1382 t4_intr(irq->rxq); 1383 } 1384 #endif 1385 1386 /* 1387 * Deals with interrupts on an iq-only (no freelist) queue. 1388 */ 1389 static int 1390 service_iq(struct sge_iq *iq, int budget) 1391 { 1392 struct sge_iq *q; 1393 struct adapter *sc = iq->adapter; 1394 struct iq_desc *d = &iq->desc[iq->cidx]; 1395 int ndescs = 0, limit; 1396 int rsp_type; 1397 uint32_t lq; 1398 STAILQ_HEAD(, sge_iq) iql = STAILQ_HEAD_INITIALIZER(iql); 1399 1400 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq)); 1401 KASSERT((iq->flags & IQ_HAS_FL) == 0, 1402 ("%s: called for iq %p with fl (iq->flags 0x%x)", __func__, iq, 1403 iq->flags)); 1404 MPASS((iq->flags & IQ_ADJ_CREDIT) == 0); 1405 MPASS((iq->flags & IQ_LRO_ENABLED) == 0); 1406 1407 limit = budget ? budget : iq->qsize / 16; 1408 1409 /* 1410 * We always come back and check the descriptor ring for new indirect 1411 * interrupts and other responses after running a single handler. 1412 */ 1413 for (;;) { 1414 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) { 1415 1416 rmb(); 1417 1418 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen); 1419 lq = be32toh(d->rsp.pldbuflen_qid); 1420 1421 switch (rsp_type) { 1422 case X_RSPD_TYPE_FLBUF: 1423 panic("%s: data for an iq (%p) with no freelist", 1424 __func__, iq); 1425 1426 /* NOTREACHED */ 1427 1428 case X_RSPD_TYPE_CPL: 1429 KASSERT(d->rss.opcode < NUM_CPL_CMDS, 1430 ("%s: bad opcode %02x.", __func__, 1431 d->rss.opcode)); 1432 t4_cpl_handler[d->rss.opcode](iq, &d->rss, NULL); 1433 break; 1434 1435 case X_RSPD_TYPE_INTR: 1436 /* 1437 * There are 1K interrupt-capable queues (qids 0 1438 * through 1023). A response type indicating a 1439 * forwarded interrupt with a qid >= 1K is an 1440 * iWARP async notification. 1441 */ 1442 if (__predict_true(lq >= 1024)) { 1443 t4_an_handler(iq, &d->rsp); 1444 break; 1445 } 1446 1447 q = sc->sge.iqmap[lq - sc->sge.iq_start - 1448 sc->sge.iq_base]; 1449 if (atomic_cmpset_int(&q->state, IQS_IDLE, 1450 IQS_BUSY)) { 1451 if (service_iq_fl(q, q->qsize / 16) == 0) { 1452 (void) atomic_cmpset_int(&q->state, 1453 IQS_BUSY, IQS_IDLE); 1454 } else { 1455 STAILQ_INSERT_TAIL(&iql, q, 1456 link); 1457 } 1458 } 1459 break; 1460 1461 default: 1462 KASSERT(0, 1463 ("%s: illegal response type %d on iq %p", 1464 __func__, rsp_type, iq)); 1465 log(LOG_ERR, 1466 "%s: illegal response type %d on iq %p", 1467 device_get_nameunit(sc->dev), rsp_type, iq); 1468 break; 1469 } 1470 1471 d++; 1472 if (__predict_false(++iq->cidx == iq->sidx)) { 1473 iq->cidx = 0; 1474 iq->gen ^= F_RSPD_GEN; 1475 d = &iq->desc[0]; 1476 } 1477 if (__predict_false(++ndescs == limit)) { 1478 t4_write_reg(sc, sc->sge_gts_reg, 1479 V_CIDXINC(ndescs) | 1480 V_INGRESSQID(iq->cntxt_id) | 1481 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); 1482 ndescs = 0; 1483 1484 if (budget) { 1485 return (EINPROGRESS); 1486 } 1487 } 1488 } 1489 1490 if (STAILQ_EMPTY(&iql)) 1491 break; 1492 1493 /* 1494 * Process the head only, and send it to the back of the list if 1495 * it's still not done. 1496 */ 1497 q = STAILQ_FIRST(&iql); 1498 STAILQ_REMOVE_HEAD(&iql, link); 1499 if (service_iq_fl(q, q->qsize / 8) == 0) 1500 (void) atomic_cmpset_int(&q->state, IQS_BUSY, IQS_IDLE); 1501 else 1502 STAILQ_INSERT_TAIL(&iql, q, link); 1503 } 1504 1505 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) | 1506 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params)); 1507 1508 return (0); 1509 } 1510 1511 static inline int 1512 sort_before_lro(struct lro_ctrl *lro) 1513 { 1514 1515 return (lro->lro_mbuf_max != 0); 1516 } 1517 1518 static inline uint64_t 1519 last_flit_to_ns(struct adapter *sc, uint64_t lf) 1520 { 1521 uint64_t n = be64toh(lf) & 0xfffffffffffffff; /* 60b, not 64b. */ 1522 1523 if (n > UINT64_MAX / 1000000) 1524 return (n / sc->params.vpd.cclk * 1000000); 1525 else 1526 return (n * 1000000 / sc->params.vpd.cclk); 1527 } 1528 1529 static inline void 1530 move_to_next_rxbuf(struct sge_fl *fl) 1531 { 1532 1533 fl->rx_offset = 0; 1534 if (__predict_false((++fl->cidx & 7) == 0)) { 1535 uint16_t cidx = fl->cidx >> 3; 1536 1537 if (__predict_false(cidx == fl->sidx)) 1538 fl->cidx = cidx = 0; 1539 fl->hw_cidx = cidx; 1540 } 1541 } 1542 1543 /* 1544 * Deals with interrupts on an iq+fl queue. 1545 */ 1546 static int 1547 service_iq_fl(struct sge_iq *iq, int budget) 1548 { 1549 struct sge_rxq *rxq = iq_to_rxq(iq); 1550 struct sge_fl *fl; 1551 struct adapter *sc = iq->adapter; 1552 struct iq_desc *d = &iq->desc[iq->cidx]; 1553 int ndescs, limit; 1554 int rsp_type, starved; 1555 uint32_t lq; 1556 uint16_t fl_hw_cidx; 1557 struct mbuf *m0; 1558 #if defined(INET) || defined(INET6) 1559 const struct timeval lro_timeout = {0, sc->lro_timeout}; 1560 struct lro_ctrl *lro = &rxq->lro; 1561 #endif 1562 1563 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq)); 1564 MPASS(iq->flags & IQ_HAS_FL); 1565 1566 ndescs = 0; 1567 #if defined(INET) || defined(INET6) 1568 if (iq->flags & IQ_ADJ_CREDIT) { 1569 MPASS(sort_before_lro(lro)); 1570 iq->flags &= ~IQ_ADJ_CREDIT; 1571 if ((d->rsp.u.type_gen & F_RSPD_GEN) != iq->gen) { 1572 tcp_lro_flush_all(lro); 1573 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(1) | 1574 V_INGRESSQID((u32)iq->cntxt_id) | 1575 V_SEINTARM(iq->intr_params)); 1576 return (0); 1577 } 1578 ndescs = 1; 1579 } 1580 #else 1581 MPASS((iq->flags & IQ_ADJ_CREDIT) == 0); 1582 #endif 1583 1584 limit = budget ? budget : iq->qsize / 16; 1585 fl = &rxq->fl; 1586 fl_hw_cidx = fl->hw_cidx; /* stable snapshot */ 1587 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) { 1588 1589 rmb(); 1590 1591 m0 = NULL; 1592 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen); 1593 lq = be32toh(d->rsp.pldbuflen_qid); 1594 1595 switch (rsp_type) { 1596 case X_RSPD_TYPE_FLBUF: 1597 if (lq & F_RSPD_NEWBUF) { 1598 if (fl->rx_offset > 0) 1599 move_to_next_rxbuf(fl); 1600 lq = G_RSPD_LEN(lq); 1601 } 1602 if (IDXDIFF(fl->hw_cidx, fl_hw_cidx, fl->sidx) > 4) { 1603 FL_LOCK(fl); 1604 refill_fl(sc, fl, 64); 1605 FL_UNLOCK(fl); 1606 fl_hw_cidx = fl->hw_cidx; 1607 } 1608 1609 if (d->rss.opcode == CPL_RX_PKT) { 1610 if (__predict_true(eth_rx(sc, rxq, d, lq) == 0)) 1611 break; 1612 goto out; 1613 } 1614 m0 = get_fl_payload(sc, fl, lq); 1615 if (__predict_false(m0 == NULL)) 1616 goto out; 1617 1618 /* fall through */ 1619 1620 case X_RSPD_TYPE_CPL: 1621 KASSERT(d->rss.opcode < NUM_CPL_CMDS, 1622 ("%s: bad opcode %02x.", __func__, d->rss.opcode)); 1623 t4_cpl_handler[d->rss.opcode](iq, &d->rss, m0); 1624 break; 1625 1626 case X_RSPD_TYPE_INTR: 1627 1628 /* 1629 * There are 1K interrupt-capable queues (qids 0 1630 * through 1023). A response type indicating a 1631 * forwarded interrupt with a qid >= 1K is an 1632 * iWARP async notification. That is the only 1633 * acceptable indirect interrupt on this queue. 1634 */ 1635 if (__predict_false(lq < 1024)) { 1636 panic("%s: indirect interrupt on iq_fl %p " 1637 "with qid %u", __func__, iq, lq); 1638 } 1639 1640 t4_an_handler(iq, &d->rsp); 1641 break; 1642 1643 default: 1644 KASSERT(0, ("%s: illegal response type %d on iq %p", 1645 __func__, rsp_type, iq)); 1646 log(LOG_ERR, "%s: illegal response type %d on iq %p", 1647 device_get_nameunit(sc->dev), rsp_type, iq); 1648 break; 1649 } 1650 1651 d++; 1652 if (__predict_false(++iq->cidx == iq->sidx)) { 1653 iq->cidx = 0; 1654 iq->gen ^= F_RSPD_GEN; 1655 d = &iq->desc[0]; 1656 } 1657 if (__predict_false(++ndescs == limit)) { 1658 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) | 1659 V_INGRESSQID(iq->cntxt_id) | 1660 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); 1661 1662 #if defined(INET) || defined(INET6) 1663 if (iq->flags & IQ_LRO_ENABLED && 1664 !sort_before_lro(lro) && 1665 sc->lro_timeout != 0) { 1666 tcp_lro_flush_inactive(lro, &lro_timeout); 1667 } 1668 #endif 1669 if (budget) 1670 return (EINPROGRESS); 1671 ndescs = 0; 1672 } 1673 } 1674 out: 1675 #if defined(INET) || defined(INET6) 1676 if (iq->flags & IQ_LRO_ENABLED) { 1677 if (ndescs > 0 && lro->lro_mbuf_count > 8) { 1678 MPASS(sort_before_lro(lro)); 1679 /* hold back one credit and don't flush LRO state */ 1680 iq->flags |= IQ_ADJ_CREDIT; 1681 ndescs--; 1682 } else { 1683 tcp_lro_flush_all(lro); 1684 } 1685 } 1686 #endif 1687 1688 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) | 1689 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params)); 1690 1691 FL_LOCK(fl); 1692 starved = refill_fl(sc, fl, 64); 1693 FL_UNLOCK(fl); 1694 if (__predict_false(starved != 0)) 1695 add_fl_to_sfl(sc, fl); 1696 1697 return (0); 1698 } 1699 1700 static inline struct cluster_metadata * 1701 cl_metadata(struct fl_sdesc *sd) 1702 { 1703 1704 return ((void *)(sd->cl + sd->moff)); 1705 } 1706 1707 static void 1708 rxb_free(struct mbuf *m) 1709 { 1710 struct cluster_metadata *clm = m->m_ext.ext_arg1; 1711 1712 uma_zfree(clm->zone, clm->cl); 1713 counter_u64_add(extfree_rels, 1); 1714 } 1715 1716 /* 1717 * The mbuf returned comes from zone_muf and carries the payload in one of these 1718 * ways 1719 * a) complete frame inside the mbuf 1720 * b) m_cljset (for clusters without metadata) 1721 * d) m_extaddref (cluster with metadata) 1722 */ 1723 static struct mbuf * 1724 get_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset, 1725 int remaining) 1726 { 1727 struct mbuf *m; 1728 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 1729 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[sd->zidx]; 1730 struct cluster_metadata *clm; 1731 int len, blen; 1732 caddr_t payload; 1733 1734 if (fl->flags & FL_BUF_PACKING) { 1735 u_int l, pad; 1736 1737 blen = rxb->size2 - fl->rx_offset; /* max possible in this buf */ 1738 len = min(remaining, blen); 1739 payload = sd->cl + fl->rx_offset; 1740 1741 l = fr_offset + len; 1742 pad = roundup2(l, fl->buf_boundary) - l; 1743 if (fl->rx_offset + len + pad < rxb->size2) 1744 blen = len + pad; 1745 MPASS(fl->rx_offset + blen <= rxb->size2); 1746 } else { 1747 MPASS(fl->rx_offset == 0); /* not packing */ 1748 blen = rxb->size1; 1749 len = min(remaining, blen); 1750 payload = sd->cl; 1751 } 1752 1753 if (fr_offset == 0) { 1754 m = m_gethdr(M_NOWAIT, MT_DATA); 1755 if (__predict_false(m == NULL)) 1756 return (NULL); 1757 m->m_pkthdr.len = remaining; 1758 } else { 1759 m = m_get(M_NOWAIT, MT_DATA); 1760 if (__predict_false(m == NULL)) 1761 return (NULL); 1762 } 1763 m->m_len = len; 1764 1765 if (sc->sc_do_rxcopy && len < RX_COPY_THRESHOLD) { 1766 /* copy data to mbuf */ 1767 bcopy(payload, mtod(m, caddr_t), len); 1768 if (fl->flags & FL_BUF_PACKING) { 1769 fl->rx_offset += blen; 1770 MPASS(fl->rx_offset <= rxb->size2); 1771 if (fl->rx_offset < rxb->size2) 1772 return (m); /* without advancing the cidx */ 1773 } 1774 } else if (fl->flags & FL_BUF_PACKING) { 1775 clm = cl_metadata(sd); 1776 if (sd->nmbuf++ == 0) { 1777 clm->refcount = 1; 1778 clm->zone = rxb->zone; 1779 clm->cl = sd->cl; 1780 counter_u64_add(extfree_refs, 1); 1781 } 1782 m_extaddref(m, payload, blen, &clm->refcount, rxb_free, clm, 1783 NULL); 1784 1785 fl->rx_offset += blen; 1786 MPASS(fl->rx_offset <= rxb->size2); 1787 if (fl->rx_offset < rxb->size2) 1788 return (m); /* without advancing the cidx */ 1789 } else { 1790 m_cljset(m, sd->cl, rxb->type); 1791 sd->cl = NULL; /* consumed, not a recycle candidate */ 1792 } 1793 1794 move_to_next_rxbuf(fl); 1795 1796 return (m); 1797 } 1798 1799 static struct mbuf * 1800 get_fl_payload(struct adapter *sc, struct sge_fl *fl, const u_int plen) 1801 { 1802 struct mbuf *m0, *m, **pnext; 1803 u_int remaining; 1804 1805 if (__predict_false(fl->flags & FL_BUF_RESUME)) { 1806 M_ASSERTPKTHDR(fl->m0); 1807 MPASS(fl->m0->m_pkthdr.len == plen); 1808 MPASS(fl->remaining < plen); 1809 1810 m0 = fl->m0; 1811 pnext = fl->pnext; 1812 remaining = fl->remaining; 1813 fl->flags &= ~FL_BUF_RESUME; 1814 goto get_segment; 1815 } 1816 1817 /* 1818 * Payload starts at rx_offset in the current hw buffer. Its length is 1819 * 'len' and it may span multiple hw buffers. 1820 */ 1821 1822 m0 = get_scatter_segment(sc, fl, 0, plen); 1823 if (m0 == NULL) 1824 return (NULL); 1825 remaining = plen - m0->m_len; 1826 pnext = &m0->m_next; 1827 while (remaining > 0) { 1828 get_segment: 1829 MPASS(fl->rx_offset == 0); 1830 m = get_scatter_segment(sc, fl, plen - remaining, remaining); 1831 if (__predict_false(m == NULL)) { 1832 fl->m0 = m0; 1833 fl->pnext = pnext; 1834 fl->remaining = remaining; 1835 fl->flags |= FL_BUF_RESUME; 1836 return (NULL); 1837 } 1838 *pnext = m; 1839 pnext = &m->m_next; 1840 remaining -= m->m_len; 1841 } 1842 *pnext = NULL; 1843 1844 M_ASSERTPKTHDR(m0); 1845 return (m0); 1846 } 1847 1848 static int 1849 skip_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset, 1850 int remaining) 1851 { 1852 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 1853 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[sd->zidx]; 1854 int len, blen; 1855 1856 if (fl->flags & FL_BUF_PACKING) { 1857 u_int l, pad; 1858 1859 blen = rxb->size2 - fl->rx_offset; /* max possible in this buf */ 1860 len = min(remaining, blen); 1861 1862 l = fr_offset + len; 1863 pad = roundup2(l, fl->buf_boundary) - l; 1864 if (fl->rx_offset + len + pad < rxb->size2) 1865 blen = len + pad; 1866 fl->rx_offset += blen; 1867 MPASS(fl->rx_offset <= rxb->size2); 1868 if (fl->rx_offset < rxb->size2) 1869 return (len); /* without advancing the cidx */ 1870 } else { 1871 MPASS(fl->rx_offset == 0); /* not packing */ 1872 blen = rxb->size1; 1873 len = min(remaining, blen); 1874 } 1875 move_to_next_rxbuf(fl); 1876 return (len); 1877 } 1878 1879 static inline void 1880 skip_fl_payload(struct adapter *sc, struct sge_fl *fl, int plen) 1881 { 1882 int remaining, fr_offset, len; 1883 1884 fr_offset = 0; 1885 remaining = plen; 1886 while (remaining > 0) { 1887 len = skip_scatter_segment(sc, fl, fr_offset, remaining); 1888 fr_offset += len; 1889 remaining -= len; 1890 } 1891 } 1892 1893 static inline int 1894 get_segment_len(struct adapter *sc, struct sge_fl *fl, int plen) 1895 { 1896 int len; 1897 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 1898 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[sd->zidx]; 1899 1900 if (fl->flags & FL_BUF_PACKING) 1901 len = rxb->size2 - fl->rx_offset; 1902 else 1903 len = rxb->size1; 1904 1905 return (min(plen, len)); 1906 } 1907 1908 static int 1909 eth_rx(struct adapter *sc, struct sge_rxq *rxq, const struct iq_desc *d, 1910 u_int plen) 1911 { 1912 struct mbuf *m0; 1913 struct ifnet *ifp = rxq->ifp; 1914 struct sge_fl *fl = &rxq->fl; 1915 struct vi_info *vi = ifp->if_softc; 1916 const struct cpl_rx_pkt *cpl; 1917 #if defined(INET) || defined(INET6) 1918 struct lro_ctrl *lro = &rxq->lro; 1919 #endif 1920 static const int sw_hashtype[4][2] = { 1921 {M_HASHTYPE_NONE, M_HASHTYPE_NONE}, 1922 {M_HASHTYPE_RSS_IPV4, M_HASHTYPE_RSS_IPV6}, 1923 {M_HASHTYPE_RSS_TCP_IPV4, M_HASHTYPE_RSS_TCP_IPV6}, 1924 {M_HASHTYPE_RSS_UDP_IPV4, M_HASHTYPE_RSS_UDP_IPV6}, 1925 }; 1926 1927 MPASS(plen > sc->params.sge.fl_pktshift); 1928 if (vi->pfil != NULL && PFIL_HOOKED_IN(vi->pfil) && 1929 __predict_true((fl->flags & FL_BUF_RESUME) == 0)) { 1930 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 1931 caddr_t frame; 1932 int rc, slen; 1933 1934 slen = get_segment_len(sc, fl, plen) - 1935 sc->params.sge.fl_pktshift; 1936 frame = sd->cl + fl->rx_offset + sc->params.sge.fl_pktshift; 1937 CURVNET_SET_QUIET(ifp->if_vnet); 1938 rc = pfil_run_hooks(vi->pfil, frame, ifp, 1939 slen | PFIL_MEMPTR | PFIL_IN, NULL); 1940 CURVNET_RESTORE(); 1941 if (rc == PFIL_DROPPED || rc == PFIL_CONSUMED) { 1942 skip_fl_payload(sc, fl, plen); 1943 return (0); 1944 } 1945 if (rc == PFIL_REALLOCED) { 1946 skip_fl_payload(sc, fl, plen); 1947 m0 = pfil_mem2mbuf(frame); 1948 goto have_mbuf; 1949 } 1950 } 1951 1952 m0 = get_fl_payload(sc, fl, plen); 1953 if (__predict_false(m0 == NULL)) 1954 return (ENOMEM); 1955 1956 m0->m_pkthdr.len -= sc->params.sge.fl_pktshift; 1957 m0->m_len -= sc->params.sge.fl_pktshift; 1958 m0->m_data += sc->params.sge.fl_pktshift; 1959 1960 have_mbuf: 1961 m0->m_pkthdr.rcvif = ifp; 1962 M_HASHTYPE_SET(m0, sw_hashtype[d->rss.hash_type][d->rss.ipv6]); 1963 m0->m_pkthdr.flowid = be32toh(d->rss.hash_val); 1964 1965 cpl = (const void *)(&d->rss + 1); 1966 if (cpl->csum_calc && !(cpl->err_vec & sc->params.tp.err_vec_mask)) { 1967 if (ifp->if_capenable & IFCAP_RXCSUM && 1968 cpl->l2info & htobe32(F_RXF_IP)) { 1969 m0->m_pkthdr.csum_flags = (CSUM_IP_CHECKED | 1970 CSUM_IP_VALID | CSUM_DATA_VALID | CSUM_PSEUDO_HDR); 1971 rxq->rxcsum++; 1972 } else if (ifp->if_capenable & IFCAP_RXCSUM_IPV6 && 1973 cpl->l2info & htobe32(F_RXF_IP6)) { 1974 m0->m_pkthdr.csum_flags = (CSUM_DATA_VALID_IPV6 | 1975 CSUM_PSEUDO_HDR); 1976 rxq->rxcsum++; 1977 } 1978 1979 if (__predict_false(cpl->ip_frag)) 1980 m0->m_pkthdr.csum_data = be16toh(cpl->csum); 1981 else 1982 m0->m_pkthdr.csum_data = 0xffff; 1983 } 1984 1985 if (cpl->vlan_ex) { 1986 m0->m_pkthdr.ether_vtag = be16toh(cpl->vlan); 1987 m0->m_flags |= M_VLANTAG; 1988 rxq->vlan_extraction++; 1989 } 1990 1991 if (rxq->iq.flags & IQ_RX_TIMESTAMP) { 1992 /* 1993 * Fill up rcv_tstmp but do not set M_TSTMP. 1994 * rcv_tstmp is not in the format that the 1995 * kernel expects and we don't want to mislead 1996 * it. For now this is only for custom code 1997 * that knows how to interpret cxgbe's stamp. 1998 */ 1999 m0->m_pkthdr.rcv_tstmp = 2000 last_flit_to_ns(sc, d->rsp.u.last_flit); 2001 #ifdef notyet 2002 m0->m_flags |= M_TSTMP; 2003 #endif 2004 } 2005 2006 #ifdef NUMA 2007 m0->m_pkthdr.numa_domain = ifp->if_numa_domain; 2008 #endif 2009 #if defined(INET) || defined(INET6) 2010 if (rxq->iq.flags & IQ_LRO_ENABLED && 2011 (M_HASHTYPE_GET(m0) == M_HASHTYPE_RSS_TCP_IPV4 || 2012 M_HASHTYPE_GET(m0) == M_HASHTYPE_RSS_TCP_IPV6)) { 2013 if (sort_before_lro(lro)) { 2014 tcp_lro_queue_mbuf(lro, m0); 2015 return (0); /* queued for sort, then LRO */ 2016 } 2017 if (tcp_lro_rx(lro, m0, 0) == 0) 2018 return (0); /* queued for LRO */ 2019 } 2020 #endif 2021 ifp->if_input(ifp, m0); 2022 2023 return (0); 2024 } 2025 2026 /* 2027 * Must drain the wrq or make sure that someone else will. 2028 */ 2029 static void 2030 wrq_tx_drain(void *arg, int n) 2031 { 2032 struct sge_wrq *wrq = arg; 2033 struct sge_eq *eq = &wrq->eq; 2034 2035 EQ_LOCK(eq); 2036 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 2037 drain_wrq_wr_list(wrq->adapter, wrq); 2038 EQ_UNLOCK(eq); 2039 } 2040 2041 static void 2042 drain_wrq_wr_list(struct adapter *sc, struct sge_wrq *wrq) 2043 { 2044 struct sge_eq *eq = &wrq->eq; 2045 u_int available, dbdiff; /* # of hardware descriptors */ 2046 u_int n; 2047 struct wrqe *wr; 2048 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */ 2049 2050 EQ_LOCK_ASSERT_OWNED(eq); 2051 MPASS(TAILQ_EMPTY(&wrq->incomplete_wrs)); 2052 wr = STAILQ_FIRST(&wrq->wr_list); 2053 MPASS(wr != NULL); /* Must be called with something useful to do */ 2054 MPASS(eq->pidx == eq->dbidx); 2055 dbdiff = 0; 2056 2057 do { 2058 eq->cidx = read_hw_cidx(eq); 2059 if (eq->pidx == eq->cidx) 2060 available = eq->sidx - 1; 2061 else 2062 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2063 2064 MPASS(wr->wrq == wrq); 2065 n = howmany(wr->wr_len, EQ_ESIZE); 2066 if (available < n) 2067 break; 2068 2069 dst = (void *)&eq->desc[eq->pidx]; 2070 if (__predict_true(eq->sidx - eq->pidx > n)) { 2071 /* Won't wrap, won't end exactly at the status page. */ 2072 bcopy(&wr->wr[0], dst, wr->wr_len); 2073 eq->pidx += n; 2074 } else { 2075 int first_portion = (eq->sidx - eq->pidx) * EQ_ESIZE; 2076 2077 bcopy(&wr->wr[0], dst, first_portion); 2078 if (wr->wr_len > first_portion) { 2079 bcopy(&wr->wr[first_portion], &eq->desc[0], 2080 wr->wr_len - first_portion); 2081 } 2082 eq->pidx = n - (eq->sidx - eq->pidx); 2083 } 2084 wrq->tx_wrs_copied++; 2085 2086 if (available < eq->sidx / 4 && 2087 atomic_cmpset_int(&eq->equiq, 0, 1)) { 2088 /* 2089 * XXX: This is not 100% reliable with some 2090 * types of WRs. But this is a very unusual 2091 * situation for an ofld/ctrl queue anyway. 2092 */ 2093 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ | 2094 F_FW_WR_EQUEQ); 2095 } 2096 2097 dbdiff += n; 2098 if (dbdiff >= 16) { 2099 ring_eq_db(sc, eq, dbdiff); 2100 dbdiff = 0; 2101 } 2102 2103 STAILQ_REMOVE_HEAD(&wrq->wr_list, link); 2104 free_wrqe(wr); 2105 MPASS(wrq->nwr_pending > 0); 2106 wrq->nwr_pending--; 2107 MPASS(wrq->ndesc_needed >= n); 2108 wrq->ndesc_needed -= n; 2109 } while ((wr = STAILQ_FIRST(&wrq->wr_list)) != NULL); 2110 2111 if (dbdiff) 2112 ring_eq_db(sc, eq, dbdiff); 2113 } 2114 2115 /* 2116 * Doesn't fail. Holds on to work requests it can't send right away. 2117 */ 2118 void 2119 t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, struct wrqe *wr) 2120 { 2121 #ifdef INVARIANTS 2122 struct sge_eq *eq = &wrq->eq; 2123 #endif 2124 2125 EQ_LOCK_ASSERT_OWNED(eq); 2126 MPASS(wr != NULL); 2127 MPASS(wr->wr_len > 0 && wr->wr_len <= SGE_MAX_WR_LEN); 2128 MPASS((wr->wr_len & 0x7) == 0); 2129 2130 STAILQ_INSERT_TAIL(&wrq->wr_list, wr, link); 2131 wrq->nwr_pending++; 2132 wrq->ndesc_needed += howmany(wr->wr_len, EQ_ESIZE); 2133 2134 if (!TAILQ_EMPTY(&wrq->incomplete_wrs)) 2135 return; /* commit_wrq_wr will drain wr_list as well. */ 2136 2137 drain_wrq_wr_list(sc, wrq); 2138 2139 /* Doorbell must have caught up to the pidx. */ 2140 MPASS(eq->pidx == eq->dbidx); 2141 } 2142 2143 void 2144 t4_update_fl_bufsize(struct ifnet *ifp) 2145 { 2146 struct vi_info *vi = ifp->if_softc; 2147 struct adapter *sc = vi->adapter; 2148 struct sge_rxq *rxq; 2149 #ifdef TCP_OFFLOAD 2150 struct sge_ofld_rxq *ofld_rxq; 2151 #endif 2152 struct sge_fl *fl; 2153 int i, maxp; 2154 2155 maxp = max_rx_payload(sc, ifp, false); 2156 for_each_rxq(vi, i, rxq) { 2157 fl = &rxq->fl; 2158 2159 FL_LOCK(fl); 2160 fl->zidx = find_refill_source(sc, maxp, 2161 fl->flags & FL_BUF_PACKING); 2162 FL_UNLOCK(fl); 2163 } 2164 #ifdef TCP_OFFLOAD 2165 maxp = max_rx_payload(sc, ifp, true); 2166 for_each_ofld_rxq(vi, i, ofld_rxq) { 2167 fl = &ofld_rxq->fl; 2168 2169 FL_LOCK(fl); 2170 fl->zidx = find_refill_source(sc, maxp, 2171 fl->flags & FL_BUF_PACKING); 2172 FL_UNLOCK(fl); 2173 } 2174 #endif 2175 } 2176 2177 static inline int 2178 mbuf_nsegs(struct mbuf *m) 2179 { 2180 2181 M_ASSERTPKTHDR(m); 2182 KASSERT(m->m_pkthdr.l5hlen > 0, 2183 ("%s: mbuf %p missing information on # of segments.", __func__, m)); 2184 2185 return (m->m_pkthdr.l5hlen); 2186 } 2187 2188 static inline void 2189 set_mbuf_nsegs(struct mbuf *m, uint8_t nsegs) 2190 { 2191 2192 M_ASSERTPKTHDR(m); 2193 m->m_pkthdr.l5hlen = nsegs; 2194 } 2195 2196 static inline int 2197 mbuf_cflags(struct mbuf *m) 2198 { 2199 2200 M_ASSERTPKTHDR(m); 2201 return (m->m_pkthdr.PH_loc.eight[4]); 2202 } 2203 2204 static inline void 2205 set_mbuf_cflags(struct mbuf *m, uint8_t flags) 2206 { 2207 2208 M_ASSERTPKTHDR(m); 2209 m->m_pkthdr.PH_loc.eight[4] = flags; 2210 } 2211 2212 static inline int 2213 mbuf_len16(struct mbuf *m) 2214 { 2215 int n; 2216 2217 M_ASSERTPKTHDR(m); 2218 n = m->m_pkthdr.PH_loc.eight[0]; 2219 if (!(mbuf_cflags(m) & MC_TLS)) 2220 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16); 2221 2222 return (n); 2223 } 2224 2225 static inline void 2226 set_mbuf_len16(struct mbuf *m, uint8_t len16) 2227 { 2228 2229 M_ASSERTPKTHDR(m); 2230 m->m_pkthdr.PH_loc.eight[0] = len16; 2231 } 2232 2233 #ifdef RATELIMIT 2234 static inline int 2235 mbuf_eo_nsegs(struct mbuf *m) 2236 { 2237 2238 M_ASSERTPKTHDR(m); 2239 return (m->m_pkthdr.PH_loc.eight[1]); 2240 } 2241 2242 static inline void 2243 set_mbuf_eo_nsegs(struct mbuf *m, uint8_t nsegs) 2244 { 2245 2246 M_ASSERTPKTHDR(m); 2247 m->m_pkthdr.PH_loc.eight[1] = nsegs; 2248 } 2249 2250 static inline int 2251 mbuf_eo_len16(struct mbuf *m) 2252 { 2253 int n; 2254 2255 M_ASSERTPKTHDR(m); 2256 n = m->m_pkthdr.PH_loc.eight[2]; 2257 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16); 2258 2259 return (n); 2260 } 2261 2262 static inline void 2263 set_mbuf_eo_len16(struct mbuf *m, uint8_t len16) 2264 { 2265 2266 M_ASSERTPKTHDR(m); 2267 m->m_pkthdr.PH_loc.eight[2] = len16; 2268 } 2269 2270 static inline int 2271 mbuf_eo_tsclk_tsoff(struct mbuf *m) 2272 { 2273 2274 M_ASSERTPKTHDR(m); 2275 return (m->m_pkthdr.PH_loc.eight[3]); 2276 } 2277 2278 static inline void 2279 set_mbuf_eo_tsclk_tsoff(struct mbuf *m, uint8_t tsclk_tsoff) 2280 { 2281 2282 M_ASSERTPKTHDR(m); 2283 m->m_pkthdr.PH_loc.eight[3] = tsclk_tsoff; 2284 } 2285 2286 static inline int 2287 needs_eo(struct cxgbe_snd_tag *cst) 2288 { 2289 2290 return (cst != NULL && cst->type == IF_SND_TAG_TYPE_RATE_LIMIT); 2291 } 2292 #endif 2293 2294 /* 2295 * Try to allocate an mbuf to contain a raw work request. To make it 2296 * easy to construct the work request, don't allocate a chain but a 2297 * single mbuf. 2298 */ 2299 struct mbuf * 2300 alloc_wr_mbuf(int len, int how) 2301 { 2302 struct mbuf *m; 2303 2304 if (len <= MHLEN) 2305 m = m_gethdr(how, MT_DATA); 2306 else if (len <= MCLBYTES) 2307 m = m_getcl(how, MT_DATA, M_PKTHDR); 2308 else 2309 m = NULL; 2310 if (m == NULL) 2311 return (NULL); 2312 m->m_pkthdr.len = len; 2313 m->m_len = len; 2314 set_mbuf_cflags(m, MC_RAW_WR); 2315 set_mbuf_len16(m, howmany(len, 16)); 2316 return (m); 2317 } 2318 2319 static inline int 2320 needs_hwcsum(struct mbuf *m) 2321 { 2322 2323 M_ASSERTPKTHDR(m); 2324 2325 return (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_IP | 2326 CSUM_TSO | CSUM_UDP_IPV6 | CSUM_TCP_IPV6)); 2327 } 2328 2329 static inline int 2330 needs_tso(struct mbuf *m) 2331 { 2332 2333 M_ASSERTPKTHDR(m); 2334 2335 return (m->m_pkthdr.csum_flags & CSUM_TSO); 2336 } 2337 2338 static inline int 2339 needs_l3_csum(struct mbuf *m) 2340 { 2341 2342 M_ASSERTPKTHDR(m); 2343 2344 return (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TSO)); 2345 } 2346 2347 static inline int 2348 needs_tcp_csum(struct mbuf *m) 2349 { 2350 2351 M_ASSERTPKTHDR(m); 2352 return (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_TCP_IPV6 | CSUM_TSO)); 2353 } 2354 2355 #ifdef RATELIMIT 2356 static inline int 2357 needs_l4_csum(struct mbuf *m) 2358 { 2359 2360 M_ASSERTPKTHDR(m); 2361 2362 return (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_UDP_IPV6 | 2363 CSUM_TCP_IPV6 | CSUM_TSO)); 2364 } 2365 2366 static inline int 2367 needs_udp_csum(struct mbuf *m) 2368 { 2369 2370 M_ASSERTPKTHDR(m); 2371 return (m->m_pkthdr.csum_flags & (CSUM_UDP | CSUM_UDP_IPV6)); 2372 } 2373 #endif 2374 2375 static inline int 2376 needs_vlan_insertion(struct mbuf *m) 2377 { 2378 2379 M_ASSERTPKTHDR(m); 2380 2381 return (m->m_flags & M_VLANTAG); 2382 } 2383 2384 static void * 2385 m_advance(struct mbuf **pm, int *poffset, int len) 2386 { 2387 struct mbuf *m = *pm; 2388 int offset = *poffset; 2389 uintptr_t p = 0; 2390 2391 MPASS(len > 0); 2392 2393 for (;;) { 2394 if (offset + len < m->m_len) { 2395 offset += len; 2396 p = mtod(m, uintptr_t) + offset; 2397 break; 2398 } 2399 len -= m->m_len - offset; 2400 m = m->m_next; 2401 offset = 0; 2402 MPASS(m != NULL); 2403 } 2404 *poffset = offset; 2405 *pm = m; 2406 return ((void *)p); 2407 } 2408 2409 static inline int 2410 count_mbuf_ext_pgs(struct mbuf *m, int skip, vm_paddr_t *nextaddr) 2411 { 2412 vm_paddr_t paddr; 2413 int i, len, off, pglen, pgoff, seglen, segoff; 2414 int nsegs = 0; 2415 2416 M_ASSERTEXTPG(m); 2417 off = mtod(m, vm_offset_t); 2418 len = m->m_len; 2419 off += skip; 2420 len -= skip; 2421 2422 if (m->m_epg_hdrlen != 0) { 2423 if (off >= m->m_epg_hdrlen) { 2424 off -= m->m_epg_hdrlen; 2425 } else { 2426 seglen = m->m_epg_hdrlen - off; 2427 segoff = off; 2428 seglen = min(seglen, len); 2429 off = 0; 2430 len -= seglen; 2431 paddr = pmap_kextract( 2432 (vm_offset_t)&m->m_epg_hdr[segoff]); 2433 if (*nextaddr != paddr) 2434 nsegs++; 2435 *nextaddr = paddr + seglen; 2436 } 2437 } 2438 pgoff = m->m_epg_1st_off; 2439 for (i = 0; i < m->m_epg_npgs && len > 0; i++) { 2440 pglen = m_epg_pagelen(m, i, pgoff); 2441 if (off >= pglen) { 2442 off -= pglen; 2443 pgoff = 0; 2444 continue; 2445 } 2446 seglen = pglen - off; 2447 segoff = pgoff + off; 2448 off = 0; 2449 seglen = min(seglen, len); 2450 len -= seglen; 2451 paddr = m->m_epg_pa[i] + segoff; 2452 if (*nextaddr != paddr) 2453 nsegs++; 2454 *nextaddr = paddr + seglen; 2455 pgoff = 0; 2456 }; 2457 if (len != 0) { 2458 seglen = min(len, m->m_epg_trllen - off); 2459 len -= seglen; 2460 paddr = pmap_kextract((vm_offset_t)&m->m_epg_trail[off]); 2461 if (*nextaddr != paddr) 2462 nsegs++; 2463 *nextaddr = paddr + seglen; 2464 } 2465 2466 return (nsegs); 2467 } 2468 2469 2470 /* 2471 * Can deal with empty mbufs in the chain that have m_len = 0, but the chain 2472 * must have at least one mbuf that's not empty. It is possible for this 2473 * routine to return 0 if skip accounts for all the contents of the mbuf chain. 2474 */ 2475 static inline int 2476 count_mbuf_nsegs(struct mbuf *m, int skip, uint8_t *cflags) 2477 { 2478 vm_paddr_t nextaddr, paddr; 2479 vm_offset_t va; 2480 int len, nsegs; 2481 2482 M_ASSERTPKTHDR(m); 2483 MPASS(m->m_pkthdr.len > 0); 2484 MPASS(m->m_pkthdr.len >= skip); 2485 2486 nsegs = 0; 2487 nextaddr = 0; 2488 for (; m; m = m->m_next) { 2489 len = m->m_len; 2490 if (__predict_false(len == 0)) 2491 continue; 2492 if (skip >= len) { 2493 skip -= len; 2494 continue; 2495 } 2496 if ((m->m_flags & M_EXTPG) != 0) { 2497 *cflags |= MC_NOMAP; 2498 nsegs += count_mbuf_ext_pgs(m, skip, &nextaddr); 2499 skip = 0; 2500 continue; 2501 } 2502 va = mtod(m, vm_offset_t) + skip; 2503 len -= skip; 2504 skip = 0; 2505 paddr = pmap_kextract(va); 2506 nsegs += sglist_count((void *)(uintptr_t)va, len); 2507 if (paddr == nextaddr) 2508 nsegs--; 2509 nextaddr = pmap_kextract(va + len - 1) + 1; 2510 } 2511 2512 return (nsegs); 2513 } 2514 2515 /* 2516 * Analyze the mbuf to determine its tx needs. The mbuf passed in may change: 2517 * a) caller can assume it's been freed if this function returns with an error. 2518 * b) it may get defragged up if the gather list is too long for the hardware. 2519 */ 2520 int 2521 parse_pkt(struct adapter *sc, struct mbuf **mp) 2522 { 2523 struct mbuf *m0 = *mp, *m; 2524 int rc, nsegs, defragged = 0, offset; 2525 struct ether_header *eh; 2526 void *l3hdr; 2527 #if defined(INET) || defined(INET6) 2528 struct tcphdr *tcp; 2529 #endif 2530 #if defined(KERN_TLS) || defined(RATELIMIT) 2531 struct cxgbe_snd_tag *cst; 2532 #endif 2533 uint16_t eh_type; 2534 uint8_t cflags; 2535 2536 cflags = 0; 2537 M_ASSERTPKTHDR(m0); 2538 if (__predict_false(m0->m_pkthdr.len < ETHER_HDR_LEN)) { 2539 rc = EINVAL; 2540 fail: 2541 m_freem(m0); 2542 *mp = NULL; 2543 return (rc); 2544 } 2545 restart: 2546 /* 2547 * First count the number of gather list segments in the payload. 2548 * Defrag the mbuf if nsegs exceeds the hardware limit. 2549 */ 2550 M_ASSERTPKTHDR(m0); 2551 MPASS(m0->m_pkthdr.len > 0); 2552 nsegs = count_mbuf_nsegs(m0, 0, &cflags); 2553 #if defined(KERN_TLS) || defined(RATELIMIT) 2554 if (m0->m_pkthdr.csum_flags & CSUM_SND_TAG) 2555 cst = mst_to_cst(m0->m_pkthdr.snd_tag); 2556 else 2557 cst = NULL; 2558 #endif 2559 #ifdef KERN_TLS 2560 if (cst != NULL && cst->type == IF_SND_TAG_TYPE_TLS) { 2561 int len16; 2562 2563 cflags |= MC_TLS; 2564 set_mbuf_cflags(m0, cflags); 2565 rc = t6_ktls_parse_pkt(m0, &nsegs, &len16); 2566 if (rc != 0) 2567 goto fail; 2568 set_mbuf_nsegs(m0, nsegs); 2569 set_mbuf_len16(m0, len16); 2570 return (0); 2571 } 2572 #endif 2573 if (nsegs > (needs_tso(m0) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS)) { 2574 if (defragged++ > 0 || (m = m_defrag(m0, M_NOWAIT)) == NULL) { 2575 rc = EFBIG; 2576 goto fail; 2577 } 2578 *mp = m0 = m; /* update caller's copy after defrag */ 2579 goto restart; 2580 } 2581 2582 if (__predict_false(nsegs > 2 && m0->m_pkthdr.len <= MHLEN && 2583 !(cflags & MC_NOMAP))) { 2584 m0 = m_pullup(m0, m0->m_pkthdr.len); 2585 if (m0 == NULL) { 2586 /* Should have left well enough alone. */ 2587 rc = EFBIG; 2588 goto fail; 2589 } 2590 *mp = m0; /* update caller's copy after pullup */ 2591 goto restart; 2592 } 2593 set_mbuf_nsegs(m0, nsegs); 2594 set_mbuf_cflags(m0, cflags); 2595 if (sc->flags & IS_VF) 2596 set_mbuf_len16(m0, txpkt_vm_len16(nsegs, needs_tso(m0))); 2597 else 2598 set_mbuf_len16(m0, txpkt_len16(nsegs, needs_tso(m0))); 2599 2600 #ifdef RATELIMIT 2601 /* 2602 * Ethofld is limited to TCP and UDP for now, and only when L4 hw 2603 * checksumming is enabled. needs_l4_csum happens to check for all the 2604 * right things. 2605 */ 2606 if (__predict_false(needs_eo(cst) && !needs_l4_csum(m0))) { 2607 m_snd_tag_rele(m0->m_pkthdr.snd_tag); 2608 m0->m_pkthdr.snd_tag = NULL; 2609 m0->m_pkthdr.csum_flags &= ~CSUM_SND_TAG; 2610 cst = NULL; 2611 } 2612 #endif 2613 2614 if (!needs_hwcsum(m0) 2615 #ifdef RATELIMIT 2616 && !needs_eo(cst) 2617 #endif 2618 ) 2619 return (0); 2620 2621 m = m0; 2622 eh = mtod(m, struct ether_header *); 2623 eh_type = ntohs(eh->ether_type); 2624 if (eh_type == ETHERTYPE_VLAN) { 2625 struct ether_vlan_header *evh = (void *)eh; 2626 2627 eh_type = ntohs(evh->evl_proto); 2628 m0->m_pkthdr.l2hlen = sizeof(*evh); 2629 } else 2630 m0->m_pkthdr.l2hlen = sizeof(*eh); 2631 2632 offset = 0; 2633 l3hdr = m_advance(&m, &offset, m0->m_pkthdr.l2hlen); 2634 2635 switch (eh_type) { 2636 #ifdef INET6 2637 case ETHERTYPE_IPV6: 2638 { 2639 struct ip6_hdr *ip6 = l3hdr; 2640 2641 MPASS(!needs_tso(m0) || ip6->ip6_nxt == IPPROTO_TCP); 2642 2643 m0->m_pkthdr.l3hlen = sizeof(*ip6); 2644 break; 2645 } 2646 #endif 2647 #ifdef INET 2648 case ETHERTYPE_IP: 2649 { 2650 struct ip *ip = l3hdr; 2651 2652 m0->m_pkthdr.l3hlen = ip->ip_hl * 4; 2653 break; 2654 } 2655 #endif 2656 default: 2657 panic("%s: ethertype 0x%04x unknown. if_cxgbe must be compiled" 2658 " with the same INET/INET6 options as the kernel.", 2659 __func__, eh_type); 2660 } 2661 2662 #if defined(INET) || defined(INET6) 2663 if (needs_tcp_csum(m0)) { 2664 tcp = m_advance(&m, &offset, m0->m_pkthdr.l3hlen); 2665 m0->m_pkthdr.l4hlen = tcp->th_off * 4; 2666 #ifdef RATELIMIT 2667 if (tsclk >= 0 && *(uint32_t *)(tcp + 1) == ntohl(0x0101080a)) { 2668 set_mbuf_eo_tsclk_tsoff(m0, 2669 V_FW_ETH_TX_EO_WR_TSCLK(tsclk) | 2670 V_FW_ETH_TX_EO_WR_TSOFF(sizeof(*tcp) / 2 + 1)); 2671 } else 2672 set_mbuf_eo_tsclk_tsoff(m0, 0); 2673 } else if (needs_udp_csum(m0)) { 2674 m0->m_pkthdr.l4hlen = sizeof(struct udphdr); 2675 #endif 2676 } 2677 #ifdef RATELIMIT 2678 if (needs_eo(cst)) { 2679 u_int immhdrs; 2680 2681 /* EO WRs have the headers in the WR and not the GL. */ 2682 immhdrs = m0->m_pkthdr.l2hlen + m0->m_pkthdr.l3hlen + 2683 m0->m_pkthdr.l4hlen; 2684 cflags = 0; 2685 nsegs = count_mbuf_nsegs(m0, immhdrs, &cflags); 2686 MPASS(cflags == mbuf_cflags(m0)); 2687 set_mbuf_eo_nsegs(m0, nsegs); 2688 set_mbuf_eo_len16(m0, 2689 txpkt_eo_len16(nsegs, immhdrs, needs_tso(m0))); 2690 } 2691 #endif 2692 #endif 2693 MPASS(m0 == *mp); 2694 return (0); 2695 } 2696 2697 void * 2698 start_wrq_wr(struct sge_wrq *wrq, int len16, struct wrq_cookie *cookie) 2699 { 2700 struct sge_eq *eq = &wrq->eq; 2701 struct adapter *sc = wrq->adapter; 2702 int ndesc, available; 2703 struct wrqe *wr; 2704 void *w; 2705 2706 MPASS(len16 > 0); 2707 ndesc = tx_len16_to_desc(len16); 2708 MPASS(ndesc > 0 && ndesc <= SGE_MAX_WR_NDESC); 2709 2710 EQ_LOCK(eq); 2711 2712 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 2713 drain_wrq_wr_list(sc, wrq); 2714 2715 if (!STAILQ_EMPTY(&wrq->wr_list)) { 2716 slowpath: 2717 EQ_UNLOCK(eq); 2718 wr = alloc_wrqe(len16 * 16, wrq); 2719 if (__predict_false(wr == NULL)) 2720 return (NULL); 2721 cookie->pidx = -1; 2722 cookie->ndesc = ndesc; 2723 return (&wr->wr); 2724 } 2725 2726 eq->cidx = read_hw_cidx(eq); 2727 if (eq->pidx == eq->cidx) 2728 available = eq->sidx - 1; 2729 else 2730 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2731 if (available < ndesc) 2732 goto slowpath; 2733 2734 cookie->pidx = eq->pidx; 2735 cookie->ndesc = ndesc; 2736 TAILQ_INSERT_TAIL(&wrq->incomplete_wrs, cookie, link); 2737 2738 w = &eq->desc[eq->pidx]; 2739 IDXINCR(eq->pidx, ndesc, eq->sidx); 2740 if (__predict_false(cookie->pidx + ndesc > eq->sidx)) { 2741 w = &wrq->ss[0]; 2742 wrq->ss_pidx = cookie->pidx; 2743 wrq->ss_len = len16 * 16; 2744 } 2745 2746 EQ_UNLOCK(eq); 2747 2748 return (w); 2749 } 2750 2751 void 2752 commit_wrq_wr(struct sge_wrq *wrq, void *w, struct wrq_cookie *cookie) 2753 { 2754 struct sge_eq *eq = &wrq->eq; 2755 struct adapter *sc = wrq->adapter; 2756 int ndesc, pidx; 2757 struct wrq_cookie *prev, *next; 2758 2759 if (cookie->pidx == -1) { 2760 struct wrqe *wr = __containerof(w, struct wrqe, wr); 2761 2762 t4_wrq_tx(sc, wr); 2763 return; 2764 } 2765 2766 if (__predict_false(w == &wrq->ss[0])) { 2767 int n = (eq->sidx - wrq->ss_pidx) * EQ_ESIZE; 2768 2769 MPASS(wrq->ss_len > n); /* WR had better wrap around. */ 2770 bcopy(&wrq->ss[0], &eq->desc[wrq->ss_pidx], n); 2771 bcopy(&wrq->ss[n], &eq->desc[0], wrq->ss_len - n); 2772 wrq->tx_wrs_ss++; 2773 } else 2774 wrq->tx_wrs_direct++; 2775 2776 EQ_LOCK(eq); 2777 ndesc = cookie->ndesc; /* Can be more than SGE_MAX_WR_NDESC here. */ 2778 pidx = cookie->pidx; 2779 MPASS(pidx >= 0 && pidx < eq->sidx); 2780 prev = TAILQ_PREV(cookie, wrq_incomplete_wrs, link); 2781 next = TAILQ_NEXT(cookie, link); 2782 if (prev == NULL) { 2783 MPASS(pidx == eq->dbidx); 2784 if (next == NULL || ndesc >= 16) { 2785 int available; 2786 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */ 2787 2788 /* 2789 * Note that the WR via which we'll request tx updates 2790 * is at pidx and not eq->pidx, which has moved on 2791 * already. 2792 */ 2793 dst = (void *)&eq->desc[pidx]; 2794 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2795 if (available < eq->sidx / 4 && 2796 atomic_cmpset_int(&eq->equiq, 0, 1)) { 2797 /* 2798 * XXX: This is not 100% reliable with some 2799 * types of WRs. But this is a very unusual 2800 * situation for an ofld/ctrl queue anyway. 2801 */ 2802 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ | 2803 F_FW_WR_EQUEQ); 2804 } 2805 2806 ring_eq_db(wrq->adapter, eq, ndesc); 2807 } else { 2808 MPASS(IDXDIFF(next->pidx, pidx, eq->sidx) == ndesc); 2809 next->pidx = pidx; 2810 next->ndesc += ndesc; 2811 } 2812 } else { 2813 MPASS(IDXDIFF(pidx, prev->pidx, eq->sidx) == prev->ndesc); 2814 prev->ndesc += ndesc; 2815 } 2816 TAILQ_REMOVE(&wrq->incomplete_wrs, cookie, link); 2817 2818 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 2819 drain_wrq_wr_list(sc, wrq); 2820 2821 #ifdef INVARIANTS 2822 if (TAILQ_EMPTY(&wrq->incomplete_wrs)) { 2823 /* Doorbell must have caught up to the pidx. */ 2824 MPASS(wrq->eq.pidx == wrq->eq.dbidx); 2825 } 2826 #endif 2827 EQ_UNLOCK(eq); 2828 } 2829 2830 static u_int 2831 can_resume_eth_tx(struct mp_ring *r) 2832 { 2833 struct sge_eq *eq = r->cookie; 2834 2835 return (total_available_tx_desc(eq) > eq->sidx / 8); 2836 } 2837 2838 static inline bool 2839 cannot_use_txpkts(struct mbuf *m) 2840 { 2841 /* maybe put a GL limit too, to avoid silliness? */ 2842 2843 return (needs_tso(m) || (mbuf_cflags(m) & (MC_RAW_WR | MC_TLS)) != 0); 2844 } 2845 2846 static inline int 2847 discard_tx(struct sge_eq *eq) 2848 { 2849 2850 return ((eq->flags & (EQ_ENABLED | EQ_QFLUSH)) != EQ_ENABLED); 2851 } 2852 2853 static inline int 2854 wr_can_update_eq(void *p) 2855 { 2856 struct fw_eth_tx_pkts_wr *wr = p; 2857 2858 switch (G_FW_WR_OP(be32toh(wr->op_pkd))) { 2859 case FW_ULPTX_WR: 2860 case FW_ETH_TX_PKT_WR: 2861 case FW_ETH_TX_PKTS_WR: 2862 case FW_ETH_TX_PKTS2_WR: 2863 case FW_ETH_TX_PKT_VM_WR: 2864 case FW_ETH_TX_PKTS_VM_WR: 2865 return (1); 2866 default: 2867 return (0); 2868 } 2869 } 2870 2871 static inline void 2872 set_txupdate_flags(struct sge_txq *txq, u_int avail, 2873 struct fw_eth_tx_pkt_wr *wr) 2874 { 2875 struct sge_eq *eq = &txq->eq; 2876 struct txpkts *txp = &txq->txp; 2877 2878 if ((txp->npkt > 0 || avail < eq->sidx / 2) && 2879 atomic_cmpset_int(&eq->equiq, 0, 1)) { 2880 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ | F_FW_WR_EQUIQ); 2881 eq->equeqidx = eq->pidx; 2882 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 32) { 2883 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ); 2884 eq->equeqidx = eq->pidx; 2885 } 2886 } 2887 2888 /* 2889 * r->items[cidx] to r->items[pidx], with a wraparound at r->size, are ready to 2890 * be consumed. Return the actual number consumed. 0 indicates a stall. 2891 */ 2892 static u_int 2893 eth_tx(struct mp_ring *r, u_int cidx, u_int pidx, bool *coalescing) 2894 { 2895 struct sge_txq *txq = r->cookie; 2896 struct ifnet *ifp = txq->ifp; 2897 struct sge_eq *eq = &txq->eq; 2898 struct txpkts *txp = &txq->txp; 2899 struct vi_info *vi = ifp->if_softc; 2900 struct adapter *sc = vi->adapter; 2901 u_int total, remaining; /* # of packets */ 2902 u_int n, avail, dbdiff; /* # of hardware descriptors */ 2903 int i, rc; 2904 struct mbuf *m0; 2905 bool snd; 2906 void *wr; /* start of the last WR written to the ring */ 2907 2908 TXQ_LOCK_ASSERT_OWNED(txq); 2909 2910 remaining = IDXDIFF(pidx, cidx, r->size); 2911 if (__predict_false(discard_tx(eq))) { 2912 for (i = 0; i < txp->npkt; i++) 2913 m_freem(txp->mb[i]); 2914 txp->npkt = 0; 2915 while (cidx != pidx) { 2916 m0 = r->items[cidx]; 2917 m_freem(m0); 2918 if (++cidx == r->size) 2919 cidx = 0; 2920 } 2921 reclaim_tx_descs(txq, eq->sidx); 2922 *coalescing = false; 2923 return (remaining); /* emptied */ 2924 } 2925 2926 /* How many hardware descriptors do we have readily available. */ 2927 if (eq->pidx == eq->cidx) { 2928 avail = eq->sidx - 1; 2929 if (txp->score++ >= 5) 2930 txp->score = 5; /* tx is completely idle, reset. */ 2931 } else 2932 avail = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2933 2934 total = 0; 2935 if (remaining == 0) { 2936 if (txp->score-- == 1) /* egr_update had to drain txpkts */ 2937 txp->score = 1; 2938 goto send_txpkts; 2939 } 2940 2941 dbdiff = 0; 2942 MPASS(remaining > 0); 2943 while (remaining > 0) { 2944 m0 = r->items[cidx]; 2945 M_ASSERTPKTHDR(m0); 2946 MPASS(m0->m_nextpkt == NULL); 2947 2948 if (avail < 2 * SGE_MAX_WR_NDESC) 2949 avail += reclaim_tx_descs(txq, 64); 2950 2951 if (txp->npkt > 0 || remaining > 1 || txp->score > 3 || 2952 atomic_load_int(&txq->eq.equiq) != 0) { 2953 if (sc->flags & IS_VF) 2954 rc = add_to_txpkts_vf(sc, txq, m0, avail, &snd); 2955 else 2956 rc = add_to_txpkts_pf(sc, txq, m0, avail, &snd); 2957 } else { 2958 snd = false; 2959 rc = EINVAL; 2960 } 2961 if (snd) { 2962 MPASS(txp->npkt > 0); 2963 for (i = 0; i < txp->npkt; i++) 2964 ETHER_BPF_MTAP(ifp, txp->mb[i]); 2965 if (txp->npkt > 1) { 2966 if (txp->score++ >= 10) 2967 txp->score = 10; 2968 MPASS(avail >= tx_len16_to_desc(txp->len16)); 2969 if (sc->flags & IS_VF) 2970 n = write_txpkts_vm_wr(sc, txq); 2971 else 2972 n = write_txpkts_wr(sc, txq); 2973 } else { 2974 MPASS(avail >= 2975 tx_len16_to_desc(mbuf_len16(txp->mb[0]))); 2976 if (sc->flags & IS_VF) 2977 n = write_txpkt_vm_wr(sc, txq, 2978 txp->mb[0]); 2979 else 2980 n = write_txpkt_wr(sc, txq, txp->mb[0], 2981 avail); 2982 } 2983 MPASS(n <= SGE_MAX_WR_NDESC); 2984 avail -= n; 2985 dbdiff += n; 2986 wr = &eq->desc[eq->pidx]; 2987 IDXINCR(eq->pidx, n, eq->sidx); 2988 txp->npkt = 0; /* emptied */ 2989 } 2990 if (rc == 0) { 2991 /* m0 was coalesced into txq->txpkts. */ 2992 goto next_mbuf; 2993 } 2994 if (rc == EAGAIN) { 2995 /* 2996 * m0 is suitable for tx coalescing but could not be 2997 * combined with the existing txq->txpkts, which has now 2998 * been transmitted. Start a new txpkts with m0. 2999 */ 3000 MPASS(snd); 3001 MPASS(txp->npkt == 0); 3002 continue; 3003 } 3004 3005 MPASS(rc != 0 && rc != EAGAIN); 3006 MPASS(txp->npkt == 0); 3007 3008 n = tx_len16_to_desc(mbuf_len16(m0)); 3009 if (__predict_false(avail < n)) { 3010 avail += reclaim_tx_descs(txq, min(n, 32)); 3011 if (avail < n) 3012 break; /* out of descriptors */ 3013 } 3014 3015 wr = &eq->desc[eq->pidx]; 3016 if (mbuf_cflags(m0) & MC_RAW_WR) { 3017 n = write_raw_wr(txq, wr, m0, avail); 3018 #ifdef KERN_TLS 3019 } else if (mbuf_cflags(m0) & MC_TLS) { 3020 ETHER_BPF_MTAP(ifp, m0); 3021 n = t6_ktls_write_wr(txq, wr, m0, mbuf_nsegs(m0), 3022 avail); 3023 #endif 3024 } else { 3025 ETHER_BPF_MTAP(ifp, m0); 3026 if (sc->flags & IS_VF) 3027 n = write_txpkt_vm_wr(sc, txq, m0); 3028 else 3029 n = write_txpkt_wr(sc, txq, m0, avail); 3030 } 3031 MPASS(n >= 1 && n <= avail); 3032 if (!(mbuf_cflags(m0) & MC_TLS)) 3033 MPASS(n <= SGE_MAX_WR_NDESC); 3034 3035 avail -= n; 3036 dbdiff += n; 3037 IDXINCR(eq->pidx, n, eq->sidx); 3038 3039 if (dbdiff >= 512 / EQ_ESIZE) { /* X_FETCHBURSTMAX_512B */ 3040 if (wr_can_update_eq(wr)) 3041 set_txupdate_flags(txq, avail, wr); 3042 ring_eq_db(sc, eq, dbdiff); 3043 avail += reclaim_tx_descs(txq, 32); 3044 dbdiff = 0; 3045 } 3046 next_mbuf: 3047 total++; 3048 remaining--; 3049 if (__predict_false(++cidx == r->size)) 3050 cidx = 0; 3051 } 3052 if (dbdiff != 0) { 3053 if (wr_can_update_eq(wr)) 3054 set_txupdate_flags(txq, avail, wr); 3055 ring_eq_db(sc, eq, dbdiff); 3056 reclaim_tx_descs(txq, 32); 3057 } else if (eq->pidx == eq->cidx && txp->npkt > 0 && 3058 atomic_load_int(&txq->eq.equiq) == 0) { 3059 /* 3060 * If nothing was submitted to the chip for tx (it was coalesced 3061 * into txpkts instead) and there is no tx update outstanding 3062 * then we need to send txpkts now. 3063 */ 3064 send_txpkts: 3065 MPASS(txp->npkt > 0); 3066 for (i = 0; i < txp->npkt; i++) 3067 ETHER_BPF_MTAP(ifp, txp->mb[i]); 3068 if (txp->npkt > 1) { 3069 MPASS(avail >= tx_len16_to_desc(txp->len16)); 3070 if (sc->flags & IS_VF) 3071 n = write_txpkts_vm_wr(sc, txq); 3072 else 3073 n = write_txpkts_wr(sc, txq); 3074 } else { 3075 MPASS(avail >= 3076 tx_len16_to_desc(mbuf_len16(txp->mb[0]))); 3077 if (sc->flags & IS_VF) 3078 n = write_txpkt_vm_wr(sc, txq, txp->mb[0]); 3079 else 3080 n = write_txpkt_wr(sc, txq, txp->mb[0], avail); 3081 } 3082 MPASS(n <= SGE_MAX_WR_NDESC); 3083 wr = &eq->desc[eq->pidx]; 3084 IDXINCR(eq->pidx, n, eq->sidx); 3085 txp->npkt = 0; /* emptied */ 3086 3087 MPASS(wr_can_update_eq(wr)); 3088 set_txupdate_flags(txq, avail - n, wr); 3089 ring_eq_db(sc, eq, n); 3090 reclaim_tx_descs(txq, 32); 3091 } 3092 *coalescing = txp->npkt > 0; 3093 3094 return (total); 3095 } 3096 3097 static inline void 3098 init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int pktc_idx, 3099 int qsize) 3100 { 3101 3102 KASSERT(tmr_idx >= 0 && tmr_idx < SGE_NTIMERS, 3103 ("%s: bad tmr_idx %d", __func__, tmr_idx)); 3104 KASSERT(pktc_idx < SGE_NCOUNTERS, /* -ve is ok, means don't use */ 3105 ("%s: bad pktc_idx %d", __func__, pktc_idx)); 3106 3107 iq->flags = 0; 3108 iq->adapter = sc; 3109 iq->intr_params = V_QINTR_TIMER_IDX(tmr_idx); 3110 iq->intr_pktc_idx = SGE_NCOUNTERS - 1; 3111 if (pktc_idx >= 0) { 3112 iq->intr_params |= F_QINTR_CNT_EN; 3113 iq->intr_pktc_idx = pktc_idx; 3114 } 3115 iq->qsize = roundup2(qsize, 16); /* See FW_IQ_CMD/iqsize */ 3116 iq->sidx = iq->qsize - sc->params.sge.spg_len / IQ_ESIZE; 3117 } 3118 3119 static inline void 3120 init_fl(struct adapter *sc, struct sge_fl *fl, int qsize, int maxp, char *name) 3121 { 3122 3123 fl->qsize = qsize; 3124 fl->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE; 3125 strlcpy(fl->lockname, name, sizeof(fl->lockname)); 3126 if (sc->flags & BUF_PACKING_OK && 3127 ((!is_t4(sc) && buffer_packing) || /* T5+: enabled unless 0 */ 3128 (is_t4(sc) && buffer_packing == 1)))/* T4: disabled unless 1 */ 3129 fl->flags |= FL_BUF_PACKING; 3130 fl->zidx = find_refill_source(sc, maxp, fl->flags & FL_BUF_PACKING); 3131 fl->safe_zidx = sc->sge.safe_zidx; 3132 } 3133 3134 static inline void 3135 init_eq(struct adapter *sc, struct sge_eq *eq, int eqtype, int qsize, 3136 uint8_t tx_chan, uint16_t iqid, char *name) 3137 { 3138 KASSERT(eqtype <= EQ_TYPEMASK, ("%s: bad qtype %d", __func__, eqtype)); 3139 3140 eq->flags = eqtype & EQ_TYPEMASK; 3141 eq->tx_chan = tx_chan; 3142 eq->iqid = iqid; 3143 eq->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE; 3144 strlcpy(eq->lockname, name, sizeof(eq->lockname)); 3145 } 3146 3147 static int 3148 alloc_ring(struct adapter *sc, size_t len, bus_dma_tag_t *tag, 3149 bus_dmamap_t *map, bus_addr_t *pa, void **va) 3150 { 3151 int rc; 3152 3153 rc = bus_dma_tag_create(sc->dmat, 512, 0, BUS_SPACE_MAXADDR, 3154 BUS_SPACE_MAXADDR, NULL, NULL, len, 1, len, 0, NULL, NULL, tag); 3155 if (rc != 0) { 3156 device_printf(sc->dev, "cannot allocate DMA tag: %d\n", rc); 3157 goto done; 3158 } 3159 3160 rc = bus_dmamem_alloc(*tag, va, 3161 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, map); 3162 if (rc != 0) { 3163 device_printf(sc->dev, "cannot allocate DMA memory: %d\n", rc); 3164 goto done; 3165 } 3166 3167 rc = bus_dmamap_load(*tag, *map, *va, len, oneseg_dma_callback, pa, 0); 3168 if (rc != 0) { 3169 device_printf(sc->dev, "cannot load DMA map: %d\n", rc); 3170 goto done; 3171 } 3172 done: 3173 if (rc) 3174 free_ring(sc, *tag, *map, *pa, *va); 3175 3176 return (rc); 3177 } 3178 3179 static int 3180 free_ring(struct adapter *sc, bus_dma_tag_t tag, bus_dmamap_t map, 3181 bus_addr_t pa, void *va) 3182 { 3183 if (pa) 3184 bus_dmamap_unload(tag, map); 3185 if (va) 3186 bus_dmamem_free(tag, va, map); 3187 if (tag) 3188 bus_dma_tag_destroy(tag); 3189 3190 return (0); 3191 } 3192 3193 /* 3194 * Allocates the ring for an ingress queue and an optional freelist. If the 3195 * freelist is specified it will be allocated and then associated with the 3196 * ingress queue. 3197 * 3198 * Returns errno on failure. Resources allocated up to that point may still be 3199 * allocated. Caller is responsible for cleanup in case this function fails. 3200 * 3201 * If the ingress queue will take interrupts directly then the intr_idx 3202 * specifies the vector, starting from 0. -1 means the interrupts for this 3203 * queue should be forwarded to the fwq. 3204 */ 3205 static int 3206 alloc_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl, 3207 int intr_idx, int cong) 3208 { 3209 int rc, i, cntxt_id; 3210 size_t len; 3211 struct fw_iq_cmd c; 3212 struct port_info *pi = vi->pi; 3213 struct adapter *sc = iq->adapter; 3214 struct sge_params *sp = &sc->params.sge; 3215 __be32 v = 0; 3216 3217 len = iq->qsize * IQ_ESIZE; 3218 rc = alloc_ring(sc, len, &iq->desc_tag, &iq->desc_map, &iq->ba, 3219 (void **)&iq->desc); 3220 if (rc != 0) 3221 return (rc); 3222 3223 bzero(&c, sizeof(c)); 3224 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 3225 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) | 3226 V_FW_IQ_CMD_VFN(0)); 3227 3228 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART | 3229 FW_LEN16(c)); 3230 3231 /* Special handling for firmware event queue */ 3232 if (iq == &sc->sge.fwq) 3233 v |= F_FW_IQ_CMD_IQASYNCH; 3234 3235 if (intr_idx < 0) { 3236 /* Forwarded interrupts, all headed to fwq */ 3237 v |= F_FW_IQ_CMD_IQANDST; 3238 v |= V_FW_IQ_CMD_IQANDSTINDEX(sc->sge.fwq.cntxt_id); 3239 } else { 3240 KASSERT(intr_idx < sc->intr_count, 3241 ("%s: invalid direct intr_idx %d", __func__, intr_idx)); 3242 v |= V_FW_IQ_CMD_IQANDSTINDEX(intr_idx); 3243 } 3244 3245 c.type_to_iqandstindex = htobe32(v | 3246 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) | 3247 V_FW_IQ_CMD_VIID(vi->viid) | 3248 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT)); 3249 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->tx_chan) | 3250 F_FW_IQ_CMD_IQGTSMODE | 3251 V_FW_IQ_CMD_IQINTCNTTHRESH(iq->intr_pktc_idx) | 3252 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4)); 3253 c.iqsize = htobe16(iq->qsize); 3254 c.iqaddr = htobe64(iq->ba); 3255 if (cong >= 0) 3256 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN); 3257 3258 if (fl) { 3259 mtx_init(&fl->fl_lock, fl->lockname, NULL, MTX_DEF); 3260 3261 len = fl->qsize * EQ_ESIZE; 3262 rc = alloc_ring(sc, len, &fl->desc_tag, &fl->desc_map, 3263 &fl->ba, (void **)&fl->desc); 3264 if (rc) 3265 return (rc); 3266 3267 /* Allocate space for one software descriptor per buffer. */ 3268 rc = alloc_fl_sdesc(fl); 3269 if (rc != 0) { 3270 device_printf(sc->dev, 3271 "failed to setup fl software descriptors: %d\n", 3272 rc); 3273 return (rc); 3274 } 3275 3276 if (fl->flags & FL_BUF_PACKING) { 3277 fl->lowat = roundup2(sp->fl_starve_threshold2, 8); 3278 fl->buf_boundary = sp->pack_boundary; 3279 } else { 3280 fl->lowat = roundup2(sp->fl_starve_threshold, 8); 3281 fl->buf_boundary = 16; 3282 } 3283 if (fl_pad && fl->buf_boundary < sp->pad_boundary) 3284 fl->buf_boundary = sp->pad_boundary; 3285 3286 c.iqns_to_fl0congen |= 3287 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) | 3288 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO | 3289 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) | 3290 (fl->flags & FL_BUF_PACKING ? F_FW_IQ_CMD_FL0PACKEN : 3291 0)); 3292 if (cong >= 0) { 3293 c.iqns_to_fl0congen |= 3294 htobe32(V_FW_IQ_CMD_FL0CNGCHMAP(cong) | 3295 F_FW_IQ_CMD_FL0CONGCIF | 3296 F_FW_IQ_CMD_FL0CONGEN); 3297 } 3298 c.fl0dcaen_to_fl0cidxfthresh = 3299 htobe16(V_FW_IQ_CMD_FL0FBMIN(chip_id(sc) <= CHELSIO_T5 ? 3300 X_FETCHBURSTMIN_128B : X_FETCHBURSTMIN_64B_T6) | 3301 V_FW_IQ_CMD_FL0FBMAX(chip_id(sc) <= CHELSIO_T5 ? 3302 X_FETCHBURSTMAX_512B : X_FETCHBURSTMAX_256B)); 3303 c.fl0size = htobe16(fl->qsize); 3304 c.fl0addr = htobe64(fl->ba); 3305 } 3306 3307 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3308 if (rc != 0) { 3309 device_printf(sc->dev, 3310 "failed to create ingress queue: %d\n", rc); 3311 return (rc); 3312 } 3313 3314 iq->cidx = 0; 3315 iq->gen = F_RSPD_GEN; 3316 iq->intr_next = iq->intr_params; 3317 iq->cntxt_id = be16toh(c.iqid); 3318 iq->abs_id = be16toh(c.physiqid); 3319 iq->flags |= IQ_ALLOCATED; 3320 3321 cntxt_id = iq->cntxt_id - sc->sge.iq_start; 3322 if (cntxt_id >= sc->sge.niq) { 3323 panic ("%s: iq->cntxt_id (%d) more than the max (%d)", __func__, 3324 cntxt_id, sc->sge.niq - 1); 3325 } 3326 sc->sge.iqmap[cntxt_id] = iq; 3327 3328 if (fl) { 3329 u_int qid; 3330 3331 iq->flags |= IQ_HAS_FL; 3332 fl->cntxt_id = be16toh(c.fl0id); 3333 fl->pidx = fl->cidx = 0; 3334 3335 cntxt_id = fl->cntxt_id - sc->sge.eq_start; 3336 if (cntxt_id >= sc->sge.neq) { 3337 panic("%s: fl->cntxt_id (%d) more than the max (%d)", 3338 __func__, cntxt_id, sc->sge.neq - 1); 3339 } 3340 sc->sge.eqmap[cntxt_id] = (void *)fl; 3341 3342 qid = fl->cntxt_id; 3343 if (isset(&sc->doorbells, DOORBELL_UDB)) { 3344 uint32_t s_qpp = sc->params.sge.eq_s_qpp; 3345 uint32_t mask = (1 << s_qpp) - 1; 3346 volatile uint8_t *udb; 3347 3348 udb = sc->udbs_base + UDBS_DB_OFFSET; 3349 udb += (qid >> s_qpp) << PAGE_SHIFT; 3350 qid &= mask; 3351 if (qid < PAGE_SIZE / UDBS_SEG_SIZE) { 3352 udb += qid << UDBS_SEG_SHIFT; 3353 qid = 0; 3354 } 3355 fl->udb = (volatile void *)udb; 3356 } 3357 fl->dbval = V_QID(qid) | sc->chip_params->sge_fl_db; 3358 3359 FL_LOCK(fl); 3360 /* Enough to make sure the SGE doesn't think it's starved */ 3361 refill_fl(sc, fl, fl->lowat); 3362 FL_UNLOCK(fl); 3363 } 3364 3365 if (chip_id(sc) >= CHELSIO_T5 && !(sc->flags & IS_VF) && cong >= 0) { 3366 uint32_t param, val; 3367 3368 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 3369 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) | 3370 V_FW_PARAMS_PARAM_YZ(iq->cntxt_id); 3371 if (cong == 0) 3372 val = 1 << 19; 3373 else { 3374 val = 2 << 19; 3375 for (i = 0; i < 4; i++) { 3376 if (cong & (1 << i)) 3377 val |= 1 << (i << 2); 3378 } 3379 } 3380 3381 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 3382 if (rc != 0) { 3383 /* report error but carry on */ 3384 device_printf(sc->dev, 3385 "failed to set congestion manager context for " 3386 "ingress queue %d: %d\n", iq->cntxt_id, rc); 3387 } 3388 } 3389 3390 /* Enable IQ interrupts */ 3391 atomic_store_rel_int(&iq->state, IQS_IDLE); 3392 t4_write_reg(sc, sc->sge_gts_reg, V_SEINTARM(iq->intr_params) | 3393 V_INGRESSQID(iq->cntxt_id)); 3394 3395 return (0); 3396 } 3397 3398 static int 3399 free_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl) 3400 { 3401 int rc; 3402 struct adapter *sc = iq->adapter; 3403 device_t dev; 3404 3405 if (sc == NULL) 3406 return (0); /* nothing to do */ 3407 3408 dev = vi ? vi->dev : sc->dev; 3409 3410 if (iq->flags & IQ_ALLOCATED) { 3411 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0, 3412 FW_IQ_TYPE_FL_INT_CAP, iq->cntxt_id, 3413 fl ? fl->cntxt_id : 0xffff, 0xffff); 3414 if (rc != 0) { 3415 device_printf(dev, 3416 "failed to free queue %p: %d\n", iq, rc); 3417 return (rc); 3418 } 3419 iq->flags &= ~IQ_ALLOCATED; 3420 } 3421 3422 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, iq->desc); 3423 3424 bzero(iq, sizeof(*iq)); 3425 3426 if (fl) { 3427 free_ring(sc, fl->desc_tag, fl->desc_map, fl->ba, 3428 fl->desc); 3429 3430 if (fl->sdesc) 3431 free_fl_sdesc(sc, fl); 3432 3433 if (mtx_initialized(&fl->fl_lock)) 3434 mtx_destroy(&fl->fl_lock); 3435 3436 bzero(fl, sizeof(*fl)); 3437 } 3438 3439 return (0); 3440 } 3441 3442 static void 3443 add_iq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid, 3444 struct sge_iq *iq) 3445 { 3446 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3447 3448 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, &iq->ba, 3449 "bus address of descriptor ring"); 3450 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3451 iq->qsize * IQ_ESIZE, "descriptor ring size in bytes"); 3452 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "abs_id", 3453 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, &iq->abs_id, 0, 3454 sysctl_uint16, "I", "absolute id of the queue"); 3455 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 3456 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, &iq->cntxt_id, 0, 3457 sysctl_uint16, "I", "SGE context id of the queue"); 3458 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx", 3459 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, &iq->cidx, 0, 3460 sysctl_uint16, "I", "consumer index"); 3461 } 3462 3463 static void 3464 add_fl_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx, 3465 struct sysctl_oid *oid, struct sge_fl *fl) 3466 { 3467 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3468 3469 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", 3470 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "freelist"); 3471 children = SYSCTL_CHILDREN(oid); 3472 3473 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, 3474 &fl->ba, "bus address of descriptor ring"); 3475 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3476 fl->sidx * EQ_ESIZE + sc->params.sge.spg_len, 3477 "desc ring size in bytes"); 3478 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 3479 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, &fl->cntxt_id, 0, 3480 sysctl_uint16, "I", "SGE context id of the freelist"); 3481 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "padding", CTLFLAG_RD, NULL, 3482 fl_pad ? 1 : 0, "padding enabled"); 3483 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "packing", CTLFLAG_RD, NULL, 3484 fl->flags & FL_BUF_PACKING ? 1 : 0, "packing enabled"); 3485 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &fl->cidx, 3486 0, "consumer index"); 3487 if (fl->flags & FL_BUF_PACKING) { 3488 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rx_offset", 3489 CTLFLAG_RD, &fl->rx_offset, 0, "packing rx offset"); 3490 } 3491 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &fl->pidx, 3492 0, "producer index"); 3493 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_allocated", 3494 CTLFLAG_RD, &fl->cl_allocated, "# of clusters allocated"); 3495 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_recycled", 3496 CTLFLAG_RD, &fl->cl_recycled, "# of clusters recycled"); 3497 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_fast_recycled", 3498 CTLFLAG_RD, &fl->cl_fast_recycled, "# of clusters recycled (fast)"); 3499 } 3500 3501 static int 3502 alloc_fwq(struct adapter *sc) 3503 { 3504 int rc, intr_idx; 3505 struct sge_iq *fwq = &sc->sge.fwq; 3506 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev); 3507 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3508 3509 init_iq(fwq, sc, 0, 0, FW_IQ_QSIZE); 3510 if (sc->flags & IS_VF) 3511 intr_idx = 0; 3512 else 3513 intr_idx = sc->intr_count > 1 ? 1 : 0; 3514 rc = alloc_iq_fl(&sc->port[0]->vi[0], fwq, NULL, intr_idx, -1); 3515 if (rc != 0) { 3516 device_printf(sc->dev, 3517 "failed to create firmware event queue: %d\n", rc); 3518 return (rc); 3519 } 3520 3521 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "fwq", 3522 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "firmware event queue"); 3523 add_iq_sysctls(&sc->ctx, oid, fwq); 3524 3525 return (0); 3526 } 3527 3528 static int 3529 free_fwq(struct adapter *sc) 3530 { 3531 return free_iq_fl(NULL, &sc->sge.fwq, NULL); 3532 } 3533 3534 static int 3535 alloc_ctrlq(struct adapter *sc, struct sge_wrq *ctrlq, int idx, 3536 struct sysctl_oid *oid) 3537 { 3538 int rc; 3539 char name[16]; 3540 struct sysctl_oid_list *children; 3541 3542 snprintf(name, sizeof(name), "%s ctrlq%d", device_get_nameunit(sc->dev), 3543 idx); 3544 init_eq(sc, &ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE, sc->port[idx]->tx_chan, 3545 sc->sge.fwq.cntxt_id, name); 3546 3547 children = SYSCTL_CHILDREN(oid); 3548 snprintf(name, sizeof(name), "%d", idx); 3549 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, name, 3550 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "ctrl queue"); 3551 rc = alloc_wrq(sc, NULL, ctrlq, oid); 3552 3553 return (rc); 3554 } 3555 3556 int 3557 tnl_cong(struct port_info *pi, int drop) 3558 { 3559 3560 if (drop == -1) 3561 return (-1); 3562 else if (drop == 1) 3563 return (0); 3564 else 3565 return (pi->rx_e_chan_map); 3566 } 3567 3568 static int 3569 alloc_rxq(struct vi_info *vi, struct sge_rxq *rxq, int intr_idx, int idx, 3570 struct sysctl_oid *oid) 3571 { 3572 int rc; 3573 struct adapter *sc = vi->adapter; 3574 struct sysctl_oid_list *children; 3575 char name[16]; 3576 3577 rc = alloc_iq_fl(vi, &rxq->iq, &rxq->fl, intr_idx, 3578 tnl_cong(vi->pi, cong_drop)); 3579 if (rc != 0) 3580 return (rc); 3581 3582 if (idx == 0) 3583 sc->sge.iq_base = rxq->iq.abs_id - rxq->iq.cntxt_id; 3584 else 3585 KASSERT(rxq->iq.cntxt_id + sc->sge.iq_base == rxq->iq.abs_id, 3586 ("iq_base mismatch")); 3587 KASSERT(sc->sge.iq_base == 0 || sc->flags & IS_VF, 3588 ("PF with non-zero iq_base")); 3589 3590 /* 3591 * The freelist is just barely above the starvation threshold right now, 3592 * fill it up a bit more. 3593 */ 3594 FL_LOCK(&rxq->fl); 3595 refill_fl(sc, &rxq->fl, 128); 3596 FL_UNLOCK(&rxq->fl); 3597 3598 #if defined(INET) || defined(INET6) 3599 rc = tcp_lro_init_args(&rxq->lro, vi->ifp, lro_entries, lro_mbufs); 3600 if (rc != 0) 3601 return (rc); 3602 MPASS(rxq->lro.ifp == vi->ifp); /* also indicates LRO init'ed */ 3603 3604 if (vi->ifp->if_capenable & IFCAP_LRO) 3605 rxq->iq.flags |= IQ_LRO_ENABLED; 3606 #endif 3607 if (vi->ifp->if_capenable & IFCAP_HWRXTSTMP) 3608 rxq->iq.flags |= IQ_RX_TIMESTAMP; 3609 rxq->ifp = vi->ifp; 3610 3611 children = SYSCTL_CHILDREN(oid); 3612 3613 snprintf(name, sizeof(name), "%d", idx); 3614 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, 3615 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "rx queue"); 3616 children = SYSCTL_CHILDREN(oid); 3617 3618 add_iq_sysctls(&vi->ctx, oid, &rxq->iq); 3619 #if defined(INET) || defined(INET6) 3620 SYSCTL_ADD_U64(&vi->ctx, children, OID_AUTO, "lro_queued", CTLFLAG_RD, 3621 &rxq->lro.lro_queued, 0, NULL); 3622 SYSCTL_ADD_U64(&vi->ctx, children, OID_AUTO, "lro_flushed", CTLFLAG_RD, 3623 &rxq->lro.lro_flushed, 0, NULL); 3624 #endif 3625 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "rxcsum", CTLFLAG_RD, 3626 &rxq->rxcsum, "# of times hardware assisted with checksum"); 3627 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_extraction", 3628 CTLFLAG_RD, &rxq->vlan_extraction, 3629 "# of times hardware extracted 802.1Q tag"); 3630 3631 add_fl_sysctls(sc, &vi->ctx, oid, &rxq->fl); 3632 3633 return (rc); 3634 } 3635 3636 static int 3637 free_rxq(struct vi_info *vi, struct sge_rxq *rxq) 3638 { 3639 int rc; 3640 3641 #if defined(INET) || defined(INET6) 3642 if (rxq->lro.ifp) { 3643 tcp_lro_free(&rxq->lro); 3644 rxq->lro.ifp = NULL; 3645 } 3646 #endif 3647 3648 rc = free_iq_fl(vi, &rxq->iq, &rxq->fl); 3649 if (rc == 0) 3650 bzero(rxq, sizeof(*rxq)); 3651 3652 return (rc); 3653 } 3654 3655 #ifdef TCP_OFFLOAD 3656 static int 3657 alloc_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq, 3658 int intr_idx, int idx, struct sysctl_oid *oid) 3659 { 3660 struct port_info *pi = vi->pi; 3661 int rc; 3662 struct sysctl_oid_list *children; 3663 char name[16]; 3664 3665 rc = alloc_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl, intr_idx, 0); 3666 if (rc != 0) 3667 return (rc); 3668 3669 children = SYSCTL_CHILDREN(oid); 3670 3671 snprintf(name, sizeof(name), "%d", idx); 3672 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, 3673 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "rx queue"); 3674 add_iq_sysctls(&vi->ctx, oid, &ofld_rxq->iq); 3675 add_fl_sysctls(pi->adapter, &vi->ctx, oid, &ofld_rxq->fl); 3676 3677 return (rc); 3678 } 3679 3680 static int 3681 free_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq) 3682 { 3683 int rc; 3684 3685 rc = free_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl); 3686 if (rc == 0) 3687 bzero(ofld_rxq, sizeof(*ofld_rxq)); 3688 3689 return (rc); 3690 } 3691 #endif 3692 3693 #ifdef DEV_NETMAP 3694 static int 3695 alloc_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq, int intr_idx, 3696 int idx, struct sysctl_oid *oid) 3697 { 3698 int rc; 3699 struct sysctl_oid_list *children; 3700 struct sysctl_ctx_list *ctx; 3701 char name[16]; 3702 size_t len; 3703 struct adapter *sc = vi->adapter; 3704 struct netmap_adapter *na = NA(vi->ifp); 3705 3706 MPASS(na != NULL); 3707 3708 len = vi->qsize_rxq * IQ_ESIZE; 3709 rc = alloc_ring(sc, len, &nm_rxq->iq_desc_tag, &nm_rxq->iq_desc_map, 3710 &nm_rxq->iq_ba, (void **)&nm_rxq->iq_desc); 3711 if (rc != 0) 3712 return (rc); 3713 3714 len = na->num_rx_desc * EQ_ESIZE + sc->params.sge.spg_len; 3715 rc = alloc_ring(sc, len, &nm_rxq->fl_desc_tag, &nm_rxq->fl_desc_map, 3716 &nm_rxq->fl_ba, (void **)&nm_rxq->fl_desc); 3717 if (rc != 0) 3718 return (rc); 3719 3720 nm_rxq->vi = vi; 3721 nm_rxq->nid = idx; 3722 nm_rxq->iq_cidx = 0; 3723 nm_rxq->iq_sidx = vi->qsize_rxq - sc->params.sge.spg_len / IQ_ESIZE; 3724 nm_rxq->iq_gen = F_RSPD_GEN; 3725 nm_rxq->fl_pidx = nm_rxq->fl_cidx = 0; 3726 nm_rxq->fl_sidx = na->num_rx_desc; 3727 nm_rxq->fl_sidx2 = nm_rxq->fl_sidx; /* copy for rxsync cacheline */ 3728 nm_rxq->intr_idx = intr_idx; 3729 nm_rxq->iq_cntxt_id = INVALID_NM_RXQ_CNTXT_ID; 3730 3731 ctx = &vi->ctx; 3732 children = SYSCTL_CHILDREN(oid); 3733 3734 snprintf(name, sizeof(name), "%d", idx); 3735 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, name, 3736 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "rx queue"); 3737 children = SYSCTL_CHILDREN(oid); 3738 3739 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "abs_id", 3740 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, &nm_rxq->iq_abs_id, 3741 0, sysctl_uint16, "I", "absolute id of the queue"); 3742 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 3743 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, &nm_rxq->iq_cntxt_id, 3744 0, sysctl_uint16, "I", "SGE context id of the queue"); 3745 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx", 3746 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, &nm_rxq->iq_cidx, 0, 3747 sysctl_uint16, "I", "consumer index"); 3748 3749 children = SYSCTL_CHILDREN(oid); 3750 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", 3751 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "freelist"); 3752 children = SYSCTL_CHILDREN(oid); 3753 3754 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 3755 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, &nm_rxq->fl_cntxt_id, 3756 0, sysctl_uint16, "I", "SGE context id of the freelist"); 3757 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, 3758 &nm_rxq->fl_cidx, 0, "consumer index"); 3759 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, 3760 &nm_rxq->fl_pidx, 0, "producer index"); 3761 3762 return (rc); 3763 } 3764 3765 3766 static int 3767 free_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq) 3768 { 3769 struct adapter *sc = vi->adapter; 3770 3771 if (vi->flags & VI_INIT_DONE) 3772 MPASS(nm_rxq->iq_cntxt_id == INVALID_NM_RXQ_CNTXT_ID); 3773 else 3774 MPASS(nm_rxq->iq_cntxt_id == 0); 3775 3776 free_ring(sc, nm_rxq->iq_desc_tag, nm_rxq->iq_desc_map, nm_rxq->iq_ba, 3777 nm_rxq->iq_desc); 3778 free_ring(sc, nm_rxq->fl_desc_tag, nm_rxq->fl_desc_map, nm_rxq->fl_ba, 3779 nm_rxq->fl_desc); 3780 3781 return (0); 3782 } 3783 3784 static int 3785 alloc_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq, int iqidx, int idx, 3786 struct sysctl_oid *oid) 3787 { 3788 int rc; 3789 size_t len; 3790 struct port_info *pi = vi->pi; 3791 struct adapter *sc = pi->adapter; 3792 struct netmap_adapter *na = NA(vi->ifp); 3793 char name[16]; 3794 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3795 3796 len = na->num_tx_desc * EQ_ESIZE + sc->params.sge.spg_len; 3797 rc = alloc_ring(sc, len, &nm_txq->desc_tag, &nm_txq->desc_map, 3798 &nm_txq->ba, (void **)&nm_txq->desc); 3799 if (rc) 3800 return (rc); 3801 3802 nm_txq->pidx = nm_txq->cidx = 0; 3803 nm_txq->sidx = na->num_tx_desc; 3804 nm_txq->nid = idx; 3805 nm_txq->iqidx = iqidx; 3806 nm_txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) | 3807 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(sc->pf) | 3808 V_TXPKT_VF(vi->vin) | V_TXPKT_VF_VLD(vi->vfvld)); 3809 if (sc->params.fw_vers >= FW_VERSION32(1, 24, 11, 0)) 3810 nm_txq->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS2_WR)); 3811 else 3812 nm_txq->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR)); 3813 nm_txq->cntxt_id = INVALID_NM_TXQ_CNTXT_ID; 3814 3815 snprintf(name, sizeof(name), "%d", idx); 3816 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, 3817 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "netmap tx queue"); 3818 children = SYSCTL_CHILDREN(oid); 3819 3820 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 3821 &nm_txq->cntxt_id, 0, "SGE context id of the queue"); 3822 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx", 3823 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, &nm_txq->cidx, 0, 3824 sysctl_uint16, "I", "consumer index"); 3825 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "pidx", 3826 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, &nm_txq->pidx, 0, 3827 sysctl_uint16, "I", "producer index"); 3828 3829 return (rc); 3830 } 3831 3832 static int 3833 free_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq) 3834 { 3835 struct adapter *sc = vi->adapter; 3836 3837 if (vi->flags & VI_INIT_DONE) 3838 MPASS(nm_txq->cntxt_id == INVALID_NM_TXQ_CNTXT_ID); 3839 else 3840 MPASS(nm_txq->cntxt_id == 0); 3841 3842 free_ring(sc, nm_txq->desc_tag, nm_txq->desc_map, nm_txq->ba, 3843 nm_txq->desc); 3844 3845 return (0); 3846 } 3847 #endif 3848 3849 /* 3850 * Returns a reasonable automatic cidx flush threshold for a given queue size. 3851 */ 3852 static u_int 3853 qsize_to_fthresh(int qsize) 3854 { 3855 u_int fthresh; 3856 3857 while (!powerof2(qsize)) 3858 qsize++; 3859 fthresh = ilog2(qsize); 3860 if (fthresh > X_CIDXFLUSHTHRESH_128) 3861 fthresh = X_CIDXFLUSHTHRESH_128; 3862 3863 return (fthresh); 3864 } 3865 3866 static int 3867 ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq) 3868 { 3869 int rc, cntxt_id; 3870 struct fw_eq_ctrl_cmd c; 3871 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 3872 3873 bzero(&c, sizeof(c)); 3874 3875 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | F_FW_CMD_REQUEST | 3876 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_CTRL_CMD_PFN(sc->pf) | 3877 V_FW_EQ_CTRL_CMD_VFN(0)); 3878 c.alloc_to_len16 = htobe32(F_FW_EQ_CTRL_CMD_ALLOC | 3879 F_FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c)); 3880 c.cmpliqid_eqid = htonl(V_FW_EQ_CTRL_CMD_CMPLIQID(eq->iqid)); 3881 c.physeqid_pkd = htobe32(0); 3882 c.fetchszm_to_iqid = 3883 htobe32(V_FW_EQ_CTRL_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 3884 V_FW_EQ_CTRL_CMD_PCIECHN(eq->tx_chan) | 3885 F_FW_EQ_CTRL_CMD_FETCHRO | V_FW_EQ_CTRL_CMD_IQID(eq->iqid)); 3886 c.dcaen_to_eqsize = 3887 htobe32(V_FW_EQ_CTRL_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ? 3888 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) | 3889 V_FW_EQ_CTRL_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 3890 V_FW_EQ_CTRL_CMD_CIDXFTHRESH(qsize_to_fthresh(qsize)) | 3891 V_FW_EQ_CTRL_CMD_EQSIZE(qsize)); 3892 c.eqaddr = htobe64(eq->ba); 3893 3894 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3895 if (rc != 0) { 3896 device_printf(sc->dev, 3897 "failed to create control queue %d: %d\n", eq->tx_chan, rc); 3898 return (rc); 3899 } 3900 eq->flags |= EQ_ALLOCATED; 3901 3902 eq->cntxt_id = G_FW_EQ_CTRL_CMD_EQID(be32toh(c.cmpliqid_eqid)); 3903 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 3904 if (cntxt_id >= sc->sge.neq) 3905 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 3906 cntxt_id, sc->sge.neq - 1); 3907 sc->sge.eqmap[cntxt_id] = eq; 3908 3909 return (rc); 3910 } 3911 3912 static int 3913 eth_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 3914 { 3915 int rc, cntxt_id; 3916 struct fw_eq_eth_cmd c; 3917 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 3918 3919 bzero(&c, sizeof(c)); 3920 3921 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST | 3922 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) | 3923 V_FW_EQ_ETH_CMD_VFN(0)); 3924 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC | 3925 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c)); 3926 c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE | 3927 F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(vi->viid)); 3928 c.fetchszm_to_iqid = 3929 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) | 3930 V_FW_EQ_ETH_CMD_PCIECHN(eq->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO | 3931 V_FW_EQ_ETH_CMD_IQID(eq->iqid)); 3932 c.dcaen_to_eqsize = 3933 htobe32(V_FW_EQ_ETH_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ? 3934 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) | 3935 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 3936 V_FW_EQ_ETH_CMD_EQSIZE(qsize)); 3937 c.eqaddr = htobe64(eq->ba); 3938 3939 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3940 if (rc != 0) { 3941 device_printf(vi->dev, 3942 "failed to create Ethernet egress queue: %d\n", rc); 3943 return (rc); 3944 } 3945 eq->flags |= EQ_ALLOCATED; 3946 3947 eq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd)); 3948 eq->abs_id = G_FW_EQ_ETH_CMD_PHYSEQID(be32toh(c.physeqid_pkd)); 3949 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 3950 if (cntxt_id >= sc->sge.neq) 3951 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 3952 cntxt_id, sc->sge.neq - 1); 3953 sc->sge.eqmap[cntxt_id] = eq; 3954 3955 return (rc); 3956 } 3957 3958 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 3959 static int 3960 ofld_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 3961 { 3962 int rc, cntxt_id; 3963 struct fw_eq_ofld_cmd c; 3964 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 3965 3966 bzero(&c, sizeof(c)); 3967 3968 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | F_FW_CMD_REQUEST | 3969 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_OFLD_CMD_PFN(sc->pf) | 3970 V_FW_EQ_OFLD_CMD_VFN(0)); 3971 c.alloc_to_len16 = htonl(F_FW_EQ_OFLD_CMD_ALLOC | 3972 F_FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c)); 3973 c.fetchszm_to_iqid = 3974 htonl(V_FW_EQ_OFLD_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 3975 V_FW_EQ_OFLD_CMD_PCIECHN(eq->tx_chan) | 3976 F_FW_EQ_OFLD_CMD_FETCHRO | V_FW_EQ_OFLD_CMD_IQID(eq->iqid)); 3977 c.dcaen_to_eqsize = 3978 htobe32(V_FW_EQ_OFLD_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ? 3979 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) | 3980 V_FW_EQ_OFLD_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 3981 V_FW_EQ_OFLD_CMD_CIDXFTHRESH(qsize_to_fthresh(qsize)) | 3982 V_FW_EQ_OFLD_CMD_EQSIZE(qsize)); 3983 c.eqaddr = htobe64(eq->ba); 3984 3985 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3986 if (rc != 0) { 3987 device_printf(vi->dev, 3988 "failed to create egress queue for TCP offload: %d\n", rc); 3989 return (rc); 3990 } 3991 eq->flags |= EQ_ALLOCATED; 3992 3993 eq->cntxt_id = G_FW_EQ_OFLD_CMD_EQID(be32toh(c.eqid_pkd)); 3994 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 3995 if (cntxt_id >= sc->sge.neq) 3996 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 3997 cntxt_id, sc->sge.neq - 1); 3998 sc->sge.eqmap[cntxt_id] = eq; 3999 4000 return (rc); 4001 } 4002 #endif 4003 4004 static int 4005 alloc_eq(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 4006 { 4007 int rc, qsize; 4008 size_t len; 4009 4010 mtx_init(&eq->eq_lock, eq->lockname, NULL, MTX_DEF); 4011 4012 qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 4013 len = qsize * EQ_ESIZE; 4014 rc = alloc_ring(sc, len, &eq->desc_tag, &eq->desc_map, 4015 &eq->ba, (void **)&eq->desc); 4016 if (rc) 4017 return (rc); 4018 4019 eq->pidx = eq->cidx = eq->dbidx = 0; 4020 /* Note that equeqidx is not used with sge_wrq (OFLD/CTRL) queues. */ 4021 eq->equeqidx = 0; 4022 eq->doorbells = sc->doorbells; 4023 4024 switch (eq->flags & EQ_TYPEMASK) { 4025 case EQ_CTRL: 4026 rc = ctrl_eq_alloc(sc, eq); 4027 break; 4028 4029 case EQ_ETH: 4030 rc = eth_eq_alloc(sc, vi, eq); 4031 break; 4032 4033 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 4034 case EQ_OFLD: 4035 rc = ofld_eq_alloc(sc, vi, eq); 4036 break; 4037 #endif 4038 4039 default: 4040 panic("%s: invalid eq type %d.", __func__, 4041 eq->flags & EQ_TYPEMASK); 4042 } 4043 if (rc != 0) { 4044 device_printf(sc->dev, 4045 "failed to allocate egress queue(%d): %d\n", 4046 eq->flags & EQ_TYPEMASK, rc); 4047 } 4048 4049 if (isset(&eq->doorbells, DOORBELL_UDB) || 4050 isset(&eq->doorbells, DOORBELL_UDBWC) || 4051 isset(&eq->doorbells, DOORBELL_WCWR)) { 4052 uint32_t s_qpp = sc->params.sge.eq_s_qpp; 4053 uint32_t mask = (1 << s_qpp) - 1; 4054 volatile uint8_t *udb; 4055 4056 udb = sc->udbs_base + UDBS_DB_OFFSET; 4057 udb += (eq->cntxt_id >> s_qpp) << PAGE_SHIFT; /* pg offset */ 4058 eq->udb_qid = eq->cntxt_id & mask; /* id in page */ 4059 if (eq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE) 4060 clrbit(&eq->doorbells, DOORBELL_WCWR); 4061 else { 4062 udb += eq->udb_qid << UDBS_SEG_SHIFT; /* seg offset */ 4063 eq->udb_qid = 0; 4064 } 4065 eq->udb = (volatile void *)udb; 4066 } 4067 4068 return (rc); 4069 } 4070 4071 static int 4072 free_eq(struct adapter *sc, struct sge_eq *eq) 4073 { 4074 int rc; 4075 4076 if (eq->flags & EQ_ALLOCATED) { 4077 switch (eq->flags & EQ_TYPEMASK) { 4078 case EQ_CTRL: 4079 rc = -t4_ctrl_eq_free(sc, sc->mbox, sc->pf, 0, 4080 eq->cntxt_id); 4081 break; 4082 4083 case EQ_ETH: 4084 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0, 4085 eq->cntxt_id); 4086 break; 4087 4088 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 4089 case EQ_OFLD: 4090 rc = -t4_ofld_eq_free(sc, sc->mbox, sc->pf, 0, 4091 eq->cntxt_id); 4092 break; 4093 #endif 4094 4095 default: 4096 panic("%s: invalid eq type %d.", __func__, 4097 eq->flags & EQ_TYPEMASK); 4098 } 4099 if (rc != 0) { 4100 device_printf(sc->dev, 4101 "failed to free egress queue (%d): %d\n", 4102 eq->flags & EQ_TYPEMASK, rc); 4103 return (rc); 4104 } 4105 eq->flags &= ~EQ_ALLOCATED; 4106 } 4107 4108 free_ring(sc, eq->desc_tag, eq->desc_map, eq->ba, eq->desc); 4109 4110 if (mtx_initialized(&eq->eq_lock)) 4111 mtx_destroy(&eq->eq_lock); 4112 4113 bzero(eq, sizeof(*eq)); 4114 return (0); 4115 } 4116 4117 static int 4118 alloc_wrq(struct adapter *sc, struct vi_info *vi, struct sge_wrq *wrq, 4119 struct sysctl_oid *oid) 4120 { 4121 int rc; 4122 struct sysctl_ctx_list *ctx = vi ? &vi->ctx : &sc->ctx; 4123 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 4124 4125 rc = alloc_eq(sc, vi, &wrq->eq); 4126 if (rc) 4127 return (rc); 4128 4129 wrq->adapter = sc; 4130 TASK_INIT(&wrq->wrq_tx_task, 0, wrq_tx_drain, wrq); 4131 TAILQ_INIT(&wrq->incomplete_wrs); 4132 STAILQ_INIT(&wrq->wr_list); 4133 wrq->nwr_pending = 0; 4134 wrq->ndesc_needed = 0; 4135 4136 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, 4137 &wrq->eq.ba, "bus address of descriptor ring"); 4138 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 4139 wrq->eq.sidx * EQ_ESIZE + sc->params.sge.spg_len, 4140 "desc ring size in bytes"); 4141 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 4142 &wrq->eq.cntxt_id, 0, "SGE context id of the queue"); 4143 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx", 4144 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, &wrq->eq.cidx, 0, 4145 sysctl_uint16, "I", "consumer index"); 4146 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pidx", 4147 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, &wrq->eq.pidx, 0, 4148 sysctl_uint16, "I", "producer index"); 4149 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL, 4150 wrq->eq.sidx, "status page index"); 4151 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_direct", CTLFLAG_RD, 4152 &wrq->tx_wrs_direct, "# of work requests (direct)"); 4153 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_copied", CTLFLAG_RD, 4154 &wrq->tx_wrs_copied, "# of work requests (copied)"); 4155 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_sspace", CTLFLAG_RD, 4156 &wrq->tx_wrs_ss, "# of work requests (copied from scratch space)"); 4157 4158 return (rc); 4159 } 4160 4161 static int 4162 free_wrq(struct adapter *sc, struct sge_wrq *wrq) 4163 { 4164 int rc; 4165 4166 rc = free_eq(sc, &wrq->eq); 4167 if (rc) 4168 return (rc); 4169 4170 bzero(wrq, sizeof(*wrq)); 4171 return (0); 4172 } 4173 4174 static int 4175 alloc_txq(struct vi_info *vi, struct sge_txq *txq, int idx, 4176 struct sysctl_oid *oid) 4177 { 4178 int rc; 4179 struct port_info *pi = vi->pi; 4180 struct adapter *sc = pi->adapter; 4181 struct sge_eq *eq = &txq->eq; 4182 struct txpkts *txp; 4183 char name[16]; 4184 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 4185 4186 rc = mp_ring_alloc(&txq->r, eq->sidx, txq, eth_tx, can_resume_eth_tx, 4187 M_CXGBE, &eq->eq_lock, M_WAITOK); 4188 if (rc != 0) { 4189 device_printf(sc->dev, "failed to allocate mp_ring: %d\n", rc); 4190 return (rc); 4191 } 4192 4193 rc = alloc_eq(sc, vi, eq); 4194 if (rc != 0) { 4195 mp_ring_free(txq->r); 4196 txq->r = NULL; 4197 return (rc); 4198 } 4199 4200 /* Can't fail after this point. */ 4201 4202 if (idx == 0) 4203 sc->sge.eq_base = eq->abs_id - eq->cntxt_id; 4204 else 4205 KASSERT(eq->cntxt_id + sc->sge.eq_base == eq->abs_id, 4206 ("eq_base mismatch")); 4207 KASSERT(sc->sge.eq_base == 0 || sc->flags & IS_VF, 4208 ("PF with non-zero eq_base")); 4209 4210 TASK_INIT(&txq->tx_reclaim_task, 0, tx_reclaim, eq); 4211 txq->ifp = vi->ifp; 4212 txq->gl = sglist_alloc(TX_SGL_SEGS, M_WAITOK); 4213 if (sc->flags & IS_VF) 4214 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) | 4215 V_TXPKT_INTF(pi->tx_chan)); 4216 else 4217 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) | 4218 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(sc->pf) | 4219 V_TXPKT_VF(vi->vin) | V_TXPKT_VF_VLD(vi->vfvld)); 4220 txq->tc_idx = -1; 4221 txq->sdesc = malloc(eq->sidx * sizeof(struct tx_sdesc), M_CXGBE, 4222 M_ZERO | M_WAITOK); 4223 4224 txp = &txq->txp; 4225 txp->score = 5; 4226 MPASS(nitems(txp->mb) >= sc->params.max_pkts_per_eth_tx_pkts_wr); 4227 txq->txp.max_npkt = min(nitems(txp->mb), 4228 sc->params.max_pkts_per_eth_tx_pkts_wr); 4229 4230 snprintf(name, sizeof(name), "%d", idx); 4231 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, 4232 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "tx queue"); 4233 children = SYSCTL_CHILDREN(oid); 4234 4235 SYSCTL_ADD_UAUTO(&vi->ctx, children, OID_AUTO, "ba", CTLFLAG_RD, 4236 &eq->ba, "bus address of descriptor ring"); 4237 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 4238 eq->sidx * EQ_ESIZE + sc->params.sge.spg_len, 4239 "desc ring size in bytes"); 4240 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "abs_id", CTLFLAG_RD, 4241 &eq->abs_id, 0, "absolute id of the queue"); 4242 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 4243 &eq->cntxt_id, 0, "SGE context id of the queue"); 4244 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx", 4245 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, &eq->cidx, 0, 4246 sysctl_uint16, "I", "consumer index"); 4247 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "pidx", 4248 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, &eq->pidx, 0, 4249 sysctl_uint16, "I", "producer index"); 4250 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL, 4251 eq->sidx, "status page index"); 4252 4253 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "tc", 4254 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, vi, idx, sysctl_tc, 4255 "I", "traffic class (-1 means none)"); 4256 4257 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txcsum", CTLFLAG_RD, 4258 &txq->txcsum, "# of times hardware assisted with checksum"); 4259 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_insertion", 4260 CTLFLAG_RD, &txq->vlan_insertion, 4261 "# of times hardware inserted 802.1Q tag"); 4262 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "tso_wrs", CTLFLAG_RD, 4263 &txq->tso_wrs, "# of TSO work requests"); 4264 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "imm_wrs", CTLFLAG_RD, 4265 &txq->imm_wrs, "# of work requests with immediate data"); 4266 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "sgl_wrs", CTLFLAG_RD, 4267 &txq->sgl_wrs, "# of work requests with direct SGL"); 4268 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkt_wrs", CTLFLAG_RD, 4269 &txq->txpkt_wrs, "# of txpkt work requests (one pkt/WR)"); 4270 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_wrs", 4271 CTLFLAG_RD, &txq->txpkts0_wrs, 4272 "# of txpkts (type 0) work requests"); 4273 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_wrs", 4274 CTLFLAG_RD, &txq->txpkts1_wrs, 4275 "# of txpkts (type 1) work requests"); 4276 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_pkts", 4277 CTLFLAG_RD, &txq->txpkts0_pkts, 4278 "# of frames tx'd using type0 txpkts work requests"); 4279 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_pkts", 4280 CTLFLAG_RD, &txq->txpkts1_pkts, 4281 "# of frames tx'd using type1 txpkts work requests"); 4282 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "raw_wrs", CTLFLAG_RD, 4283 &txq->raw_wrs, "# of raw work requests (non-packets)"); 4284 4285 #ifdef KERN_TLS 4286 if (sc->flags & KERN_TLS_OK) { 4287 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, 4288 "kern_tls_records", CTLFLAG_RD, &txq->kern_tls_records, 4289 "# of NIC TLS records transmitted"); 4290 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, 4291 "kern_tls_short", CTLFLAG_RD, &txq->kern_tls_short, 4292 "# of short NIC TLS records transmitted"); 4293 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, 4294 "kern_tls_partial", CTLFLAG_RD, &txq->kern_tls_partial, 4295 "# of partial NIC TLS records transmitted"); 4296 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, 4297 "kern_tls_full", CTLFLAG_RD, &txq->kern_tls_full, 4298 "# of full NIC TLS records transmitted"); 4299 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, 4300 "kern_tls_octets", CTLFLAG_RD, &txq->kern_tls_octets, 4301 "# of payload octets in transmitted NIC TLS records"); 4302 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, 4303 "kern_tls_waste", CTLFLAG_RD, &txq->kern_tls_waste, 4304 "# of octets DMAd but not transmitted in NIC TLS records"); 4305 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, 4306 "kern_tls_options", CTLFLAG_RD, &txq->kern_tls_options, 4307 "# of NIC TLS options-only packets transmitted"); 4308 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, 4309 "kern_tls_header", CTLFLAG_RD, &txq->kern_tls_header, 4310 "# of NIC TLS header-only packets transmitted"); 4311 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, 4312 "kern_tls_fin", CTLFLAG_RD, &txq->kern_tls_fin, 4313 "# of NIC TLS FIN-only packets transmitted"); 4314 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, 4315 "kern_tls_fin_short", CTLFLAG_RD, &txq->kern_tls_fin_short, 4316 "# of NIC TLS padded FIN packets on short TLS records"); 4317 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, 4318 "kern_tls_cbc", CTLFLAG_RD, &txq->kern_tls_cbc, 4319 "# of NIC TLS sessions using AES-CBC"); 4320 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, 4321 "kern_tls_gcm", CTLFLAG_RD, &txq->kern_tls_gcm, 4322 "# of NIC TLS sessions using AES-GCM"); 4323 } 4324 #endif 4325 mp_ring_sysctls(txq->r, &vi->ctx, children); 4326 4327 return (0); 4328 } 4329 4330 static int 4331 free_txq(struct vi_info *vi, struct sge_txq *txq) 4332 { 4333 int rc; 4334 struct adapter *sc = vi->adapter; 4335 struct sge_eq *eq = &txq->eq; 4336 4337 rc = free_eq(sc, eq); 4338 if (rc) 4339 return (rc); 4340 4341 sglist_free(txq->gl); 4342 free(txq->sdesc, M_CXGBE); 4343 mp_ring_free(txq->r); 4344 4345 bzero(txq, sizeof(*txq)); 4346 return (0); 4347 } 4348 4349 static void 4350 oneseg_dma_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error) 4351 { 4352 bus_addr_t *ba = arg; 4353 4354 KASSERT(nseg == 1, 4355 ("%s meant for single segment mappings only.", __func__)); 4356 4357 *ba = error ? 0 : segs->ds_addr; 4358 } 4359 4360 static inline void 4361 ring_fl_db(struct adapter *sc, struct sge_fl *fl) 4362 { 4363 uint32_t n, v; 4364 4365 n = IDXDIFF(fl->pidx >> 3, fl->dbidx, fl->sidx); 4366 MPASS(n > 0); 4367 4368 wmb(); 4369 v = fl->dbval | V_PIDX(n); 4370 if (fl->udb) 4371 *fl->udb = htole32(v); 4372 else 4373 t4_write_reg(sc, sc->sge_kdoorbell_reg, v); 4374 IDXINCR(fl->dbidx, n, fl->sidx); 4375 } 4376 4377 /* 4378 * Fills up the freelist by allocating up to 'n' buffers. Buffers that are 4379 * recycled do not count towards this allocation budget. 4380 * 4381 * Returns non-zero to indicate that this freelist should be added to the list 4382 * of starving freelists. 4383 */ 4384 static int 4385 refill_fl(struct adapter *sc, struct sge_fl *fl, int n) 4386 { 4387 __be64 *d; 4388 struct fl_sdesc *sd; 4389 uintptr_t pa; 4390 caddr_t cl; 4391 struct rx_buf_info *rxb; 4392 struct cluster_metadata *clm; 4393 uint16_t max_pidx; 4394 uint16_t hw_cidx = fl->hw_cidx; /* stable snapshot */ 4395 4396 FL_LOCK_ASSERT_OWNED(fl); 4397 4398 /* 4399 * We always stop at the beginning of the hardware descriptor that's just 4400 * before the one with the hw cidx. This is to avoid hw pidx = hw cidx, 4401 * which would mean an empty freelist to the chip. 4402 */ 4403 max_pidx = __predict_false(hw_cidx == 0) ? fl->sidx - 1 : hw_cidx - 1; 4404 if (fl->pidx == max_pidx * 8) 4405 return (0); 4406 4407 d = &fl->desc[fl->pidx]; 4408 sd = &fl->sdesc[fl->pidx]; 4409 4410 while (n > 0) { 4411 4412 if (sd->cl != NULL) { 4413 4414 if (sd->nmbuf == 0) { 4415 /* 4416 * Fast recycle without involving any atomics on 4417 * the cluster's metadata (if the cluster has 4418 * metadata). This happens when all frames 4419 * received in the cluster were small enough to 4420 * fit within a single mbuf each. 4421 */ 4422 fl->cl_fast_recycled++; 4423 goto recycled; 4424 } 4425 4426 /* 4427 * Cluster is guaranteed to have metadata. Clusters 4428 * without metadata always take the fast recycle path 4429 * when they're recycled. 4430 */ 4431 clm = cl_metadata(sd); 4432 MPASS(clm != NULL); 4433 4434 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) { 4435 fl->cl_recycled++; 4436 counter_u64_add(extfree_rels, 1); 4437 goto recycled; 4438 } 4439 sd->cl = NULL; /* gave up my reference */ 4440 } 4441 MPASS(sd->cl == NULL); 4442 rxb = &sc->sge.rx_buf_info[fl->zidx]; 4443 cl = uma_zalloc(rxb->zone, M_NOWAIT); 4444 if (__predict_false(cl == NULL)) { 4445 if (fl->zidx != fl->safe_zidx) { 4446 rxb = &sc->sge.rx_buf_info[fl->safe_zidx]; 4447 cl = uma_zalloc(rxb->zone, M_NOWAIT); 4448 } 4449 if (cl == NULL) 4450 break; 4451 } 4452 fl->cl_allocated++; 4453 n--; 4454 4455 pa = pmap_kextract((vm_offset_t)cl); 4456 sd->cl = cl; 4457 sd->zidx = fl->zidx; 4458 4459 if (fl->flags & FL_BUF_PACKING) { 4460 *d = htobe64(pa | rxb->hwidx2); 4461 sd->moff = rxb->size2; 4462 } else { 4463 *d = htobe64(pa | rxb->hwidx1); 4464 sd->moff = 0; 4465 } 4466 recycled: 4467 sd->nmbuf = 0; 4468 d++; 4469 sd++; 4470 if (__predict_false((++fl->pidx & 7) == 0)) { 4471 uint16_t pidx = fl->pidx >> 3; 4472 4473 if (__predict_false(pidx == fl->sidx)) { 4474 fl->pidx = 0; 4475 pidx = 0; 4476 sd = fl->sdesc; 4477 d = fl->desc; 4478 } 4479 if (n < 8 || pidx == max_pidx) 4480 break; 4481 4482 if (IDXDIFF(pidx, fl->dbidx, fl->sidx) >= 4) 4483 ring_fl_db(sc, fl); 4484 } 4485 } 4486 4487 if ((fl->pidx >> 3) != fl->dbidx) 4488 ring_fl_db(sc, fl); 4489 4490 return (FL_RUNNING_LOW(fl) && !(fl->flags & FL_STARVING)); 4491 } 4492 4493 /* 4494 * Attempt to refill all starving freelists. 4495 */ 4496 static void 4497 refill_sfl(void *arg) 4498 { 4499 struct adapter *sc = arg; 4500 struct sge_fl *fl, *fl_temp; 4501 4502 mtx_assert(&sc->sfl_lock, MA_OWNED); 4503 TAILQ_FOREACH_SAFE(fl, &sc->sfl, link, fl_temp) { 4504 FL_LOCK(fl); 4505 refill_fl(sc, fl, 64); 4506 if (FL_NOT_RUNNING_LOW(fl) || fl->flags & FL_DOOMED) { 4507 TAILQ_REMOVE(&sc->sfl, fl, link); 4508 fl->flags &= ~FL_STARVING; 4509 } 4510 FL_UNLOCK(fl); 4511 } 4512 4513 if (!TAILQ_EMPTY(&sc->sfl)) 4514 callout_schedule(&sc->sfl_callout, hz / 5); 4515 } 4516 4517 static int 4518 alloc_fl_sdesc(struct sge_fl *fl) 4519 { 4520 4521 fl->sdesc = malloc(fl->sidx * 8 * sizeof(struct fl_sdesc), M_CXGBE, 4522 M_ZERO | M_WAITOK); 4523 4524 return (0); 4525 } 4526 4527 static void 4528 free_fl_sdesc(struct adapter *sc, struct sge_fl *fl) 4529 { 4530 struct fl_sdesc *sd; 4531 struct cluster_metadata *clm; 4532 int i; 4533 4534 sd = fl->sdesc; 4535 for (i = 0; i < fl->sidx * 8; i++, sd++) { 4536 if (sd->cl == NULL) 4537 continue; 4538 4539 if (sd->nmbuf == 0) 4540 uma_zfree(sc->sge.rx_buf_info[sd->zidx].zone, sd->cl); 4541 else if (fl->flags & FL_BUF_PACKING) { 4542 clm = cl_metadata(sd); 4543 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) { 4544 uma_zfree(sc->sge.rx_buf_info[sd->zidx].zone, 4545 sd->cl); 4546 counter_u64_add(extfree_rels, 1); 4547 } 4548 } 4549 sd->cl = NULL; 4550 } 4551 4552 free(fl->sdesc, M_CXGBE); 4553 fl->sdesc = NULL; 4554 } 4555 4556 static inline void 4557 get_pkt_gl(struct mbuf *m, struct sglist *gl) 4558 { 4559 int rc; 4560 4561 M_ASSERTPKTHDR(m); 4562 4563 sglist_reset(gl); 4564 rc = sglist_append_mbuf(gl, m); 4565 if (__predict_false(rc != 0)) { 4566 panic("%s: mbuf %p (%d segs) was vetted earlier but now fails " 4567 "with %d.", __func__, m, mbuf_nsegs(m), rc); 4568 } 4569 4570 KASSERT(gl->sg_nseg == mbuf_nsegs(m), 4571 ("%s: nsegs changed for mbuf %p from %d to %d", __func__, m, 4572 mbuf_nsegs(m), gl->sg_nseg)); 4573 KASSERT(gl->sg_nseg > 0 && 4574 gl->sg_nseg <= (needs_tso(m) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS), 4575 ("%s: %d segments, should have been 1 <= nsegs <= %d", __func__, 4576 gl->sg_nseg, needs_tso(m) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS)); 4577 } 4578 4579 /* 4580 * len16 for a txpkt WR with a GL. Includes the firmware work request header. 4581 */ 4582 static inline u_int 4583 txpkt_len16(u_int nsegs, u_int tso) 4584 { 4585 u_int n; 4586 4587 MPASS(nsegs > 0); 4588 4589 nsegs--; /* first segment is part of ulptx_sgl */ 4590 n = sizeof(struct fw_eth_tx_pkt_wr) + sizeof(struct cpl_tx_pkt_core) + 4591 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 4592 if (tso) 4593 n += sizeof(struct cpl_tx_pkt_lso_core); 4594 4595 return (howmany(n, 16)); 4596 } 4597 4598 /* 4599 * len16 for a txpkt_vm WR with a GL. Includes the firmware work 4600 * request header. 4601 */ 4602 static inline u_int 4603 txpkt_vm_len16(u_int nsegs, u_int tso) 4604 { 4605 u_int n; 4606 4607 MPASS(nsegs > 0); 4608 4609 nsegs--; /* first segment is part of ulptx_sgl */ 4610 n = sizeof(struct fw_eth_tx_pkt_vm_wr) + 4611 sizeof(struct cpl_tx_pkt_core) + 4612 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 4613 if (tso) 4614 n += sizeof(struct cpl_tx_pkt_lso_core); 4615 4616 return (howmany(n, 16)); 4617 } 4618 4619 /* 4620 * len16 for a txpkts type 0 WR with a GL. Does not include the firmware work 4621 * request header. 4622 */ 4623 static inline u_int 4624 txpkts0_len16(u_int nsegs) 4625 { 4626 u_int n; 4627 4628 MPASS(nsegs > 0); 4629 4630 nsegs--; /* first segment is part of ulptx_sgl */ 4631 n = sizeof(struct ulp_txpkt) + sizeof(struct ulptx_idata) + 4632 sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl) + 4633 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 4634 4635 return (howmany(n, 16)); 4636 } 4637 4638 /* 4639 * len16 for a txpkts type 1 WR with a GL. Does not include the firmware work 4640 * request header. 4641 */ 4642 static inline u_int 4643 txpkts1_len16(void) 4644 { 4645 u_int n; 4646 4647 n = sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl); 4648 4649 return (howmany(n, 16)); 4650 } 4651 4652 static inline u_int 4653 imm_payload(u_int ndesc) 4654 { 4655 u_int n; 4656 4657 n = ndesc * EQ_ESIZE - sizeof(struct fw_eth_tx_pkt_wr) - 4658 sizeof(struct cpl_tx_pkt_core); 4659 4660 return (n); 4661 } 4662 4663 static inline uint64_t 4664 csum_to_ctrl(struct adapter *sc, struct mbuf *m) 4665 { 4666 uint64_t ctrl; 4667 int csum_type; 4668 4669 M_ASSERTPKTHDR(m); 4670 4671 if (needs_hwcsum(m) == 0) 4672 return (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS); 4673 4674 ctrl = 0; 4675 if (needs_l3_csum(m) == 0) 4676 ctrl |= F_TXPKT_IPCSUM_DIS; 4677 switch (m->m_pkthdr.csum_flags & 4678 (CSUM_IP_TCP | CSUM_IP_UDP | CSUM_IP6_TCP | CSUM_IP6_UDP)) { 4679 case CSUM_IP_TCP: 4680 csum_type = TX_CSUM_TCPIP; 4681 break; 4682 case CSUM_IP_UDP: 4683 csum_type = TX_CSUM_UDPIP; 4684 break; 4685 case CSUM_IP6_TCP: 4686 csum_type = TX_CSUM_TCPIP6; 4687 break; 4688 case CSUM_IP6_UDP: 4689 csum_type = TX_CSUM_UDPIP6; 4690 break; 4691 default: 4692 /* needs_hwcsum told us that at least some hwcsum is needed. */ 4693 MPASS(ctrl == 0); 4694 MPASS(m->m_pkthdr.csum_flags & CSUM_IP); 4695 ctrl |= F_TXPKT_L4CSUM_DIS; 4696 csum_type = TX_CSUM_IP; 4697 break; 4698 } 4699 4700 MPASS(m->m_pkthdr.l2hlen > 0); 4701 MPASS(m->m_pkthdr.l3hlen > 0); 4702 ctrl |= V_TXPKT_CSUM_TYPE(csum_type) | 4703 V_TXPKT_IPHDR_LEN(m->m_pkthdr.l3hlen); 4704 if (chip_id(sc) <= CHELSIO_T5) 4705 ctrl |= V_TXPKT_ETHHDR_LEN(m->m_pkthdr.l2hlen - ETHER_HDR_LEN); 4706 else 4707 ctrl |= V_T6_TXPKT_ETHHDR_LEN(m->m_pkthdr.l2hlen - ETHER_HDR_LEN); 4708 4709 return (ctrl); 4710 } 4711 4712 #define VM_TX_L2HDR_LEN 16 /* ethmacdst to vlantci */ 4713 4714 /* 4715 * Write a VM txpkt WR for this packet to the hardware descriptors, update the 4716 * software descriptor, and advance the pidx. It is guaranteed that enough 4717 * descriptors are available. 4718 * 4719 * The return value is the # of hardware descriptors used. 4720 */ 4721 static u_int 4722 write_txpkt_vm_wr(struct adapter *sc, struct sge_txq *txq, struct mbuf *m0) 4723 { 4724 struct sge_eq *eq; 4725 struct fw_eth_tx_pkt_vm_wr *wr; 4726 struct tx_sdesc *txsd; 4727 struct cpl_tx_pkt_core *cpl; 4728 uint32_t ctrl; /* used in many unrelated places */ 4729 uint64_t ctrl1; 4730 int len16, ndesc, pktlen, nsegs; 4731 caddr_t dst; 4732 4733 TXQ_LOCK_ASSERT_OWNED(txq); 4734 M_ASSERTPKTHDR(m0); 4735 4736 len16 = mbuf_len16(m0); 4737 nsegs = mbuf_nsegs(m0); 4738 pktlen = m0->m_pkthdr.len; 4739 ctrl = sizeof(struct cpl_tx_pkt_core); 4740 if (needs_tso(m0)) 4741 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 4742 ndesc = tx_len16_to_desc(len16); 4743 4744 /* Firmware work request header */ 4745 eq = &txq->eq; 4746 wr = (void *)&eq->desc[eq->pidx]; 4747 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_VM_WR) | 4748 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl)); 4749 4750 ctrl = V_FW_WR_LEN16(len16); 4751 wr->equiq_to_len16 = htobe32(ctrl); 4752 wr->r3[0] = 0; 4753 wr->r3[1] = 0; 4754 4755 /* 4756 * Copy over ethmacdst, ethmacsrc, ethtype, and vlantci. 4757 * vlantci is ignored unless the ethtype is 0x8100, so it's 4758 * simpler to always copy it rather than making it 4759 * conditional. Also, it seems that we do not have to set 4760 * vlantci or fake the ethtype when doing VLAN tag insertion. 4761 */ 4762 m_copydata(m0, 0, VM_TX_L2HDR_LEN, wr->ethmacdst); 4763 4764 if (needs_tso(m0)) { 4765 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1); 4766 4767 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 4768 m0->m_pkthdr.l4hlen > 0, 4769 ("%s: mbuf %p needs TSO but missing header lengths", 4770 __func__, m0)); 4771 4772 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE | 4773 F_LSO_LAST_SLICE | V_LSO_ETHHDR_LEN((m0->m_pkthdr.l2hlen - 4774 ETHER_HDR_LEN) >> 2) | 4775 V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) | 4776 V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2); 4777 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 4778 ctrl |= F_LSO_IPV6; 4779 4780 lso->lso_ctrl = htobe32(ctrl); 4781 lso->ipid_ofst = htobe16(0); 4782 lso->mss = htobe16(m0->m_pkthdr.tso_segsz); 4783 lso->seqno_offset = htobe32(0); 4784 lso->len = htobe32(pktlen); 4785 4786 cpl = (void *)(lso + 1); 4787 4788 txq->tso_wrs++; 4789 } else 4790 cpl = (void *)(wr + 1); 4791 4792 /* Checksum offload */ 4793 ctrl1 = csum_to_ctrl(sc, m0); 4794 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS)) 4795 txq->txcsum++; /* some hardware assistance provided */ 4796 4797 /* VLAN tag insertion */ 4798 if (needs_vlan_insertion(m0)) { 4799 ctrl1 |= F_TXPKT_VLAN_VLD | 4800 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 4801 txq->vlan_insertion++; 4802 } 4803 4804 /* CPL header */ 4805 cpl->ctrl0 = txq->cpl_ctrl0; 4806 cpl->pack = 0; 4807 cpl->len = htobe16(pktlen); 4808 cpl->ctrl1 = htobe64(ctrl1); 4809 4810 /* SGL */ 4811 dst = (void *)(cpl + 1); 4812 4813 /* 4814 * A packet using TSO will use up an entire descriptor for the 4815 * firmware work request header, LSO CPL, and TX_PKT_XT CPL. 4816 * If this descriptor is the last descriptor in the ring, wrap 4817 * around to the front of the ring explicitly for the start of 4818 * the sgl. 4819 */ 4820 if (dst == (void *)&eq->desc[eq->sidx]) { 4821 dst = (void *)&eq->desc[0]; 4822 write_gl_to_txd(txq, m0, &dst, 0); 4823 } else 4824 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx); 4825 txq->sgl_wrs++; 4826 txq->txpkt_wrs++; 4827 4828 txsd = &txq->sdesc[eq->pidx]; 4829 txsd->m = m0; 4830 txsd->desc_used = ndesc; 4831 4832 return (ndesc); 4833 } 4834 4835 /* 4836 * Write a raw WR to the hardware descriptors, update the software 4837 * descriptor, and advance the pidx. It is guaranteed that enough 4838 * descriptors are available. 4839 * 4840 * The return value is the # of hardware descriptors used. 4841 */ 4842 static u_int 4843 write_raw_wr(struct sge_txq *txq, void *wr, struct mbuf *m0, u_int available) 4844 { 4845 struct sge_eq *eq = &txq->eq; 4846 struct tx_sdesc *txsd; 4847 struct mbuf *m; 4848 caddr_t dst; 4849 int len16, ndesc; 4850 4851 len16 = mbuf_len16(m0); 4852 ndesc = tx_len16_to_desc(len16); 4853 MPASS(ndesc <= available); 4854 4855 dst = wr; 4856 for (m = m0; m != NULL; m = m->m_next) 4857 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len); 4858 4859 txq->raw_wrs++; 4860 4861 txsd = &txq->sdesc[eq->pidx]; 4862 txsd->m = m0; 4863 txsd->desc_used = ndesc; 4864 4865 return (ndesc); 4866 } 4867 4868 /* 4869 * Write a txpkt WR for this packet to the hardware descriptors, update the 4870 * software descriptor, and advance the pidx. It is guaranteed that enough 4871 * descriptors are available. 4872 * 4873 * The return value is the # of hardware descriptors used. 4874 */ 4875 static u_int 4876 write_txpkt_wr(struct adapter *sc, struct sge_txq *txq, struct mbuf *m0, 4877 u_int available) 4878 { 4879 struct sge_eq *eq; 4880 struct fw_eth_tx_pkt_wr *wr; 4881 struct tx_sdesc *txsd; 4882 struct cpl_tx_pkt_core *cpl; 4883 uint32_t ctrl; /* used in many unrelated places */ 4884 uint64_t ctrl1; 4885 int len16, ndesc, pktlen, nsegs; 4886 caddr_t dst; 4887 4888 TXQ_LOCK_ASSERT_OWNED(txq); 4889 M_ASSERTPKTHDR(m0); 4890 4891 len16 = mbuf_len16(m0); 4892 nsegs = mbuf_nsegs(m0); 4893 pktlen = m0->m_pkthdr.len; 4894 ctrl = sizeof(struct cpl_tx_pkt_core); 4895 if (needs_tso(m0)) 4896 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 4897 else if (!(mbuf_cflags(m0) & MC_NOMAP) && pktlen <= imm_payload(2) && 4898 available >= 2) { 4899 /* Immediate data. Recalculate len16 and set nsegs to 0. */ 4900 ctrl += pktlen; 4901 len16 = howmany(sizeof(struct fw_eth_tx_pkt_wr) + 4902 sizeof(struct cpl_tx_pkt_core) + pktlen, 16); 4903 nsegs = 0; 4904 } 4905 ndesc = tx_len16_to_desc(len16); 4906 MPASS(ndesc <= available); 4907 4908 /* Firmware work request header */ 4909 eq = &txq->eq; 4910 wr = (void *)&eq->desc[eq->pidx]; 4911 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_WR) | 4912 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl)); 4913 4914 ctrl = V_FW_WR_LEN16(len16); 4915 wr->equiq_to_len16 = htobe32(ctrl); 4916 wr->r3 = 0; 4917 4918 if (needs_tso(m0)) { 4919 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1); 4920 4921 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 4922 m0->m_pkthdr.l4hlen > 0, 4923 ("%s: mbuf %p needs TSO but missing header lengths", 4924 __func__, m0)); 4925 4926 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE | 4927 F_LSO_LAST_SLICE | V_LSO_ETHHDR_LEN((m0->m_pkthdr.l2hlen - 4928 ETHER_HDR_LEN) >> 2) | 4929 V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) | 4930 V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2); 4931 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 4932 ctrl |= F_LSO_IPV6; 4933 4934 lso->lso_ctrl = htobe32(ctrl); 4935 lso->ipid_ofst = htobe16(0); 4936 lso->mss = htobe16(m0->m_pkthdr.tso_segsz); 4937 lso->seqno_offset = htobe32(0); 4938 lso->len = htobe32(pktlen); 4939 4940 cpl = (void *)(lso + 1); 4941 4942 txq->tso_wrs++; 4943 } else 4944 cpl = (void *)(wr + 1); 4945 4946 /* Checksum offload */ 4947 ctrl1 = csum_to_ctrl(sc, m0); 4948 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS)) 4949 txq->txcsum++; /* some hardware assistance provided */ 4950 4951 /* VLAN tag insertion */ 4952 if (needs_vlan_insertion(m0)) { 4953 ctrl1 |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 4954 txq->vlan_insertion++; 4955 } 4956 4957 /* CPL header */ 4958 cpl->ctrl0 = txq->cpl_ctrl0; 4959 cpl->pack = 0; 4960 cpl->len = htobe16(pktlen); 4961 cpl->ctrl1 = htobe64(ctrl1); 4962 4963 /* SGL */ 4964 dst = (void *)(cpl + 1); 4965 if (nsegs > 0) { 4966 4967 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx); 4968 txq->sgl_wrs++; 4969 } else { 4970 struct mbuf *m; 4971 4972 for (m = m0; m != NULL; m = m->m_next) { 4973 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len); 4974 #ifdef INVARIANTS 4975 pktlen -= m->m_len; 4976 #endif 4977 } 4978 #ifdef INVARIANTS 4979 KASSERT(pktlen == 0, ("%s: %d bytes left.", __func__, pktlen)); 4980 #endif 4981 txq->imm_wrs++; 4982 } 4983 4984 txq->txpkt_wrs++; 4985 4986 txsd = &txq->sdesc[eq->pidx]; 4987 txsd->m = m0; 4988 txsd->desc_used = ndesc; 4989 4990 return (ndesc); 4991 } 4992 4993 static inline bool 4994 cmp_l2hdr(struct txpkts *txp, struct mbuf *m) 4995 { 4996 int len; 4997 4998 MPASS(txp->npkt > 0); 4999 MPASS(m->m_len >= VM_TX_L2HDR_LEN); 5000 5001 if (txp->ethtype == be16toh(ETHERTYPE_VLAN)) 5002 len = VM_TX_L2HDR_LEN; 5003 else 5004 len = sizeof(struct ether_header); 5005 5006 return (memcmp(m->m_data, &txp->ethmacdst[0], len) != 0); 5007 } 5008 5009 static inline void 5010 save_l2hdr(struct txpkts *txp, struct mbuf *m) 5011 { 5012 MPASS(m->m_len >= VM_TX_L2HDR_LEN); 5013 5014 memcpy(&txp->ethmacdst[0], mtod(m, const void *), VM_TX_L2HDR_LEN); 5015 } 5016 5017 static int 5018 add_to_txpkts_vf(struct adapter *sc, struct sge_txq *txq, struct mbuf *m, 5019 int avail, bool *send) 5020 { 5021 struct txpkts *txp = &txq->txp; 5022 5023 MPASS(sc->flags & IS_VF); 5024 5025 /* Cannot have TSO and coalesce at the same time. */ 5026 if (cannot_use_txpkts(m)) { 5027 cannot_coalesce: 5028 *send = txp->npkt > 0; 5029 return (EINVAL); 5030 } 5031 5032 /* VF allows coalescing of type 1 (1 GL) only */ 5033 if (mbuf_nsegs(m) > 1) 5034 goto cannot_coalesce; 5035 5036 *send = false; 5037 if (txp->npkt > 0) { 5038 MPASS(tx_len16_to_desc(txp->len16) <= avail); 5039 MPASS(txp->npkt < txp->max_npkt); 5040 MPASS(txp->wr_type == 1); /* VF supports type 1 only */ 5041 5042 if (tx_len16_to_desc(txp->len16 + txpkts1_len16()) > avail) { 5043 retry_after_send: 5044 *send = true; 5045 return (EAGAIN); 5046 } 5047 if (m->m_pkthdr.len + txp->plen > 65535) 5048 goto retry_after_send; 5049 if (cmp_l2hdr(txp, m)) 5050 goto retry_after_send; 5051 5052 txp->len16 += txpkts1_len16(); 5053 txp->plen += m->m_pkthdr.len; 5054 txp->mb[txp->npkt++] = m; 5055 if (txp->npkt == txp->max_npkt) 5056 *send = true; 5057 } else { 5058 txp->len16 = howmany(sizeof(struct fw_eth_tx_pkts_vm_wr), 16) + 5059 txpkts1_len16(); 5060 if (tx_len16_to_desc(txp->len16) > avail) 5061 goto cannot_coalesce; 5062 txp->npkt = 1; 5063 txp->wr_type = 1; 5064 txp->plen = m->m_pkthdr.len; 5065 txp->mb[0] = m; 5066 save_l2hdr(txp, m); 5067 } 5068 return (0); 5069 } 5070 5071 static int 5072 add_to_txpkts_pf(struct adapter *sc, struct sge_txq *txq, struct mbuf *m, 5073 int avail, bool *send) 5074 { 5075 struct txpkts *txp = &txq->txp; 5076 int nsegs; 5077 5078 MPASS(!(sc->flags & IS_VF)); 5079 5080 /* Cannot have TSO and coalesce at the same time. */ 5081 if (cannot_use_txpkts(m)) { 5082 cannot_coalesce: 5083 *send = txp->npkt > 0; 5084 return (EINVAL); 5085 } 5086 5087 *send = false; 5088 nsegs = mbuf_nsegs(m); 5089 if (txp->npkt == 0) { 5090 if (m->m_pkthdr.len > 65535) 5091 goto cannot_coalesce; 5092 if (nsegs > 1) { 5093 txp->wr_type = 0; 5094 txp->len16 = 5095 howmany(sizeof(struct fw_eth_tx_pkts_wr), 16) + 5096 txpkts0_len16(nsegs); 5097 } else { 5098 txp->wr_type = 1; 5099 txp->len16 = 5100 howmany(sizeof(struct fw_eth_tx_pkts_wr), 16) + 5101 txpkts1_len16(); 5102 } 5103 if (tx_len16_to_desc(txp->len16) > avail) 5104 goto cannot_coalesce; 5105 txp->npkt = 1; 5106 txp->plen = m->m_pkthdr.len; 5107 txp->mb[0] = m; 5108 } else { 5109 MPASS(tx_len16_to_desc(txp->len16) <= avail); 5110 MPASS(txp->npkt < txp->max_npkt); 5111 5112 if (m->m_pkthdr.len + txp->plen > 65535) { 5113 retry_after_send: 5114 *send = true; 5115 return (EAGAIN); 5116 } 5117 5118 MPASS(txp->wr_type == 0 || txp->wr_type == 1); 5119 if (txp->wr_type == 0) { 5120 if (tx_len16_to_desc(txp->len16 + 5121 txpkts0_len16(nsegs)) > min(avail, SGE_MAX_WR_NDESC)) 5122 goto retry_after_send; 5123 txp->len16 += txpkts0_len16(nsegs); 5124 } else { 5125 if (nsegs != 1) 5126 goto retry_after_send; 5127 if (tx_len16_to_desc(txp->len16 + txpkts1_len16()) > 5128 avail) 5129 goto retry_after_send; 5130 txp->len16 += txpkts1_len16(); 5131 } 5132 5133 txp->plen += m->m_pkthdr.len; 5134 txp->mb[txp->npkt++] = m; 5135 if (txp->npkt == txp->max_npkt) 5136 *send = true; 5137 } 5138 return (0); 5139 } 5140 5141 /* 5142 * Write a txpkts WR for the packets in txp to the hardware descriptors, update 5143 * the software descriptor, and advance the pidx. It is guaranteed that enough 5144 * descriptors are available. 5145 * 5146 * The return value is the # of hardware descriptors used. 5147 */ 5148 static u_int 5149 write_txpkts_wr(struct adapter *sc, struct sge_txq *txq) 5150 { 5151 const struct txpkts *txp = &txq->txp; 5152 struct sge_eq *eq = &txq->eq; 5153 struct fw_eth_tx_pkts_wr *wr; 5154 struct tx_sdesc *txsd; 5155 struct cpl_tx_pkt_core *cpl; 5156 uint64_t ctrl1; 5157 int ndesc, i, checkwrap; 5158 struct mbuf *m, *last; 5159 void *flitp; 5160 5161 TXQ_LOCK_ASSERT_OWNED(txq); 5162 MPASS(txp->npkt > 0); 5163 MPASS(txp->len16 <= howmany(SGE_MAX_WR_LEN, 16)); 5164 5165 wr = (void *)&eq->desc[eq->pidx]; 5166 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR)); 5167 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(txp->len16)); 5168 wr->plen = htobe16(txp->plen); 5169 wr->npkt = txp->npkt; 5170 wr->r3 = 0; 5171 wr->type = txp->wr_type; 5172 flitp = wr + 1; 5173 5174 /* 5175 * At this point we are 16B into a hardware descriptor. If checkwrap is 5176 * set then we know the WR is going to wrap around somewhere. We'll 5177 * check for that at appropriate points. 5178 */ 5179 ndesc = tx_len16_to_desc(txp->len16); 5180 last = NULL; 5181 checkwrap = eq->sidx - ndesc < eq->pidx; 5182 for (i = 0; i < txp->npkt; i++) { 5183 m = txp->mb[i]; 5184 if (txp->wr_type == 0) { 5185 struct ulp_txpkt *ulpmc; 5186 struct ulptx_idata *ulpsc; 5187 5188 /* ULP master command */ 5189 ulpmc = flitp; 5190 ulpmc->cmd_dest = htobe32(V_ULPTX_CMD(ULP_TX_PKT) | 5191 V_ULP_TXPKT_DEST(0) | V_ULP_TXPKT_FID(eq->iqid)); 5192 ulpmc->len = htobe32(txpkts0_len16(mbuf_nsegs(m))); 5193 5194 /* ULP subcommand */ 5195 ulpsc = (void *)(ulpmc + 1); 5196 ulpsc->cmd_more = htobe32(V_ULPTX_CMD(ULP_TX_SC_IMM) | 5197 F_ULP_TX_SC_MORE); 5198 ulpsc->len = htobe32(sizeof(struct cpl_tx_pkt_core)); 5199 5200 cpl = (void *)(ulpsc + 1); 5201 if (checkwrap && 5202 (uintptr_t)cpl == (uintptr_t)&eq->desc[eq->sidx]) 5203 cpl = (void *)&eq->desc[0]; 5204 } else { 5205 cpl = flitp; 5206 } 5207 5208 /* Checksum offload */ 5209 ctrl1 = csum_to_ctrl(sc, m); 5210 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS)) 5211 txq->txcsum++; /* some hardware assistance provided */ 5212 5213 /* VLAN tag insertion */ 5214 if (needs_vlan_insertion(m)) { 5215 ctrl1 |= F_TXPKT_VLAN_VLD | 5216 V_TXPKT_VLAN(m->m_pkthdr.ether_vtag); 5217 txq->vlan_insertion++; 5218 } 5219 5220 /* CPL header */ 5221 cpl->ctrl0 = txq->cpl_ctrl0; 5222 cpl->pack = 0; 5223 cpl->len = htobe16(m->m_pkthdr.len); 5224 cpl->ctrl1 = htobe64(ctrl1); 5225 5226 flitp = cpl + 1; 5227 if (checkwrap && 5228 (uintptr_t)flitp == (uintptr_t)&eq->desc[eq->sidx]) 5229 flitp = (void *)&eq->desc[0]; 5230 5231 write_gl_to_txd(txq, m, (caddr_t *)(&flitp), checkwrap); 5232 5233 if (last != NULL) 5234 last->m_nextpkt = m; 5235 last = m; 5236 } 5237 5238 txq->sgl_wrs++; 5239 if (txp->wr_type == 0) { 5240 txq->txpkts0_pkts += txp->npkt; 5241 txq->txpkts0_wrs++; 5242 } else { 5243 txq->txpkts1_pkts += txp->npkt; 5244 txq->txpkts1_wrs++; 5245 } 5246 5247 txsd = &txq->sdesc[eq->pidx]; 5248 txsd->m = txp->mb[0]; 5249 txsd->desc_used = ndesc; 5250 5251 return (ndesc); 5252 } 5253 5254 static u_int 5255 write_txpkts_vm_wr(struct adapter *sc, struct sge_txq *txq) 5256 { 5257 const struct txpkts *txp = &txq->txp; 5258 struct sge_eq *eq = &txq->eq; 5259 struct fw_eth_tx_pkts_vm_wr *wr; 5260 struct tx_sdesc *txsd; 5261 struct cpl_tx_pkt_core *cpl; 5262 uint64_t ctrl1; 5263 int ndesc, i; 5264 struct mbuf *m, *last; 5265 void *flitp; 5266 5267 TXQ_LOCK_ASSERT_OWNED(txq); 5268 MPASS(txp->npkt > 0); 5269 MPASS(txp->wr_type == 1); /* VF supports type 1 only */ 5270 MPASS(txp->mb[0] != NULL); 5271 MPASS(txp->len16 <= howmany(SGE_MAX_WR_LEN, 16)); 5272 5273 wr = (void *)&eq->desc[eq->pidx]; 5274 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_VM_WR)); 5275 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(txp->len16)); 5276 wr->r3 = 0; 5277 wr->plen = htobe16(txp->plen); 5278 wr->npkt = txp->npkt; 5279 wr->r4 = 0; 5280 memcpy(&wr->ethmacdst[0], &txp->ethmacdst[0], 16); 5281 flitp = wr + 1; 5282 5283 /* 5284 * At this point we are 32B into a hardware descriptor. Each mbuf in 5285 * the WR will take 32B so we check for the end of the descriptor ring 5286 * before writing odd mbufs (mb[1], 3, 5, ..) 5287 */ 5288 ndesc = tx_len16_to_desc(txp->len16); 5289 last = NULL; 5290 for (i = 0; i < txp->npkt; i++) { 5291 m = txp->mb[i]; 5292 if (i & 1 && (uintptr_t)flitp == (uintptr_t)&eq->desc[eq->sidx]) 5293 flitp = &eq->desc[0]; 5294 cpl = flitp; 5295 5296 /* Checksum offload */ 5297 ctrl1 = csum_to_ctrl(sc, m); 5298 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS)) 5299 txq->txcsum++; /* some hardware assistance provided */ 5300 5301 /* VLAN tag insertion */ 5302 if (needs_vlan_insertion(m)) { 5303 ctrl1 |= F_TXPKT_VLAN_VLD | 5304 V_TXPKT_VLAN(m->m_pkthdr.ether_vtag); 5305 txq->vlan_insertion++; 5306 } 5307 5308 /* CPL header */ 5309 cpl->ctrl0 = txq->cpl_ctrl0; 5310 cpl->pack = 0; 5311 cpl->len = htobe16(m->m_pkthdr.len); 5312 cpl->ctrl1 = htobe64(ctrl1); 5313 5314 flitp = cpl + 1; 5315 MPASS(mbuf_nsegs(m) == 1); 5316 write_gl_to_txd(txq, m, (caddr_t *)(&flitp), 0); 5317 5318 if (last != NULL) 5319 last->m_nextpkt = m; 5320 last = m; 5321 } 5322 5323 txq->sgl_wrs++; 5324 txq->txpkts1_pkts += txp->npkt; 5325 txq->txpkts1_wrs++; 5326 5327 txsd = &txq->sdesc[eq->pidx]; 5328 txsd->m = txp->mb[0]; 5329 txsd->desc_used = ndesc; 5330 5331 return (ndesc); 5332 } 5333 5334 /* 5335 * If the SGL ends on an address that is not 16 byte aligned, this function will 5336 * add a 0 filled flit at the end. 5337 */ 5338 static void 5339 write_gl_to_txd(struct sge_txq *txq, struct mbuf *m, caddr_t *to, int checkwrap) 5340 { 5341 struct sge_eq *eq = &txq->eq; 5342 struct sglist *gl = txq->gl; 5343 struct sglist_seg *seg; 5344 __be64 *flitp, *wrap; 5345 struct ulptx_sgl *usgl; 5346 int i, nflits, nsegs; 5347 5348 KASSERT(((uintptr_t)(*to) & 0xf) == 0, 5349 ("%s: SGL must start at a 16 byte boundary: %p", __func__, *to)); 5350 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]); 5351 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]); 5352 5353 get_pkt_gl(m, gl); 5354 nsegs = gl->sg_nseg; 5355 MPASS(nsegs > 0); 5356 5357 nflits = (3 * (nsegs - 1)) / 2 + ((nsegs - 1) & 1) + 2; 5358 flitp = (__be64 *)(*to); 5359 wrap = (__be64 *)(&eq->desc[eq->sidx]); 5360 seg = &gl->sg_segs[0]; 5361 usgl = (void *)flitp; 5362 5363 /* 5364 * We start at a 16 byte boundary somewhere inside the tx descriptor 5365 * ring, so we're at least 16 bytes away from the status page. There is 5366 * no chance of a wrap around in the middle of usgl (which is 16 bytes). 5367 */ 5368 5369 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 5370 V_ULPTX_NSGE(nsegs)); 5371 usgl->len0 = htobe32(seg->ss_len); 5372 usgl->addr0 = htobe64(seg->ss_paddr); 5373 seg++; 5374 5375 if (checkwrap == 0 || (uintptr_t)(flitp + nflits) <= (uintptr_t)wrap) { 5376 5377 /* Won't wrap around at all */ 5378 5379 for (i = 0; i < nsegs - 1; i++, seg++) { 5380 usgl->sge[i / 2].len[i & 1] = htobe32(seg->ss_len); 5381 usgl->sge[i / 2].addr[i & 1] = htobe64(seg->ss_paddr); 5382 } 5383 if (i & 1) 5384 usgl->sge[i / 2].len[1] = htobe32(0); 5385 flitp += nflits; 5386 } else { 5387 5388 /* Will wrap somewhere in the rest of the SGL */ 5389 5390 /* 2 flits already written, write the rest flit by flit */ 5391 flitp = (void *)(usgl + 1); 5392 for (i = 0; i < nflits - 2; i++) { 5393 if (flitp == wrap) 5394 flitp = (void *)eq->desc; 5395 *flitp++ = get_flit(seg, nsegs - 1, i); 5396 } 5397 } 5398 5399 if (nflits & 1) { 5400 MPASS(((uintptr_t)flitp) & 0xf); 5401 *flitp++ = 0; 5402 } 5403 5404 MPASS((((uintptr_t)flitp) & 0xf) == 0); 5405 if (__predict_false(flitp == wrap)) 5406 *to = (void *)eq->desc; 5407 else 5408 *to = (void *)flitp; 5409 } 5410 5411 static inline void 5412 copy_to_txd(struct sge_eq *eq, caddr_t from, caddr_t *to, int len) 5413 { 5414 5415 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]); 5416 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]); 5417 5418 if (__predict_true((uintptr_t)(*to) + len <= 5419 (uintptr_t)&eq->desc[eq->sidx])) { 5420 bcopy(from, *to, len); 5421 (*to) += len; 5422 } else { 5423 int portion = (uintptr_t)&eq->desc[eq->sidx] - (uintptr_t)(*to); 5424 5425 bcopy(from, *to, portion); 5426 from += portion; 5427 portion = len - portion; /* remaining */ 5428 bcopy(from, (void *)eq->desc, portion); 5429 (*to) = (caddr_t)eq->desc + portion; 5430 } 5431 } 5432 5433 static inline void 5434 ring_eq_db(struct adapter *sc, struct sge_eq *eq, u_int n) 5435 { 5436 u_int db; 5437 5438 MPASS(n > 0); 5439 5440 db = eq->doorbells; 5441 if (n > 1) 5442 clrbit(&db, DOORBELL_WCWR); 5443 wmb(); 5444 5445 switch (ffs(db) - 1) { 5446 case DOORBELL_UDB: 5447 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n)); 5448 break; 5449 5450 case DOORBELL_WCWR: { 5451 volatile uint64_t *dst, *src; 5452 int i; 5453 5454 /* 5455 * Queues whose 128B doorbell segment fits in the page do not 5456 * use relative qid (udb_qid is always 0). Only queues with 5457 * doorbell segments can do WCWR. 5458 */ 5459 KASSERT(eq->udb_qid == 0 && n == 1, 5460 ("%s: inappropriate doorbell (0x%x, %d, %d) for eq %p", 5461 __func__, eq->doorbells, n, eq->dbidx, eq)); 5462 5463 dst = (volatile void *)((uintptr_t)eq->udb + UDBS_WR_OFFSET - 5464 UDBS_DB_OFFSET); 5465 i = eq->dbidx; 5466 src = (void *)&eq->desc[i]; 5467 while (src != (void *)&eq->desc[i + 1]) 5468 *dst++ = *src++; 5469 wmb(); 5470 break; 5471 } 5472 5473 case DOORBELL_UDBWC: 5474 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n)); 5475 wmb(); 5476 break; 5477 5478 case DOORBELL_KDB: 5479 t4_write_reg(sc, sc->sge_kdoorbell_reg, 5480 V_QID(eq->cntxt_id) | V_PIDX(n)); 5481 break; 5482 } 5483 5484 IDXINCR(eq->dbidx, n, eq->sidx); 5485 } 5486 5487 static inline u_int 5488 reclaimable_tx_desc(struct sge_eq *eq) 5489 { 5490 uint16_t hw_cidx; 5491 5492 hw_cidx = read_hw_cidx(eq); 5493 return (IDXDIFF(hw_cidx, eq->cidx, eq->sidx)); 5494 } 5495 5496 static inline u_int 5497 total_available_tx_desc(struct sge_eq *eq) 5498 { 5499 uint16_t hw_cidx, pidx; 5500 5501 hw_cidx = read_hw_cidx(eq); 5502 pidx = eq->pidx; 5503 5504 if (pidx == hw_cidx) 5505 return (eq->sidx - 1); 5506 else 5507 return (IDXDIFF(hw_cidx, pidx, eq->sidx) - 1); 5508 } 5509 5510 static inline uint16_t 5511 read_hw_cidx(struct sge_eq *eq) 5512 { 5513 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx]; 5514 uint16_t cidx = spg->cidx; /* stable snapshot */ 5515 5516 return (be16toh(cidx)); 5517 } 5518 5519 /* 5520 * Reclaim 'n' descriptors approximately. 5521 */ 5522 static u_int 5523 reclaim_tx_descs(struct sge_txq *txq, u_int n) 5524 { 5525 struct tx_sdesc *txsd; 5526 struct sge_eq *eq = &txq->eq; 5527 u_int can_reclaim, reclaimed; 5528 5529 TXQ_LOCK_ASSERT_OWNED(txq); 5530 MPASS(n > 0); 5531 5532 reclaimed = 0; 5533 can_reclaim = reclaimable_tx_desc(eq); 5534 while (can_reclaim && reclaimed < n) { 5535 int ndesc; 5536 struct mbuf *m, *nextpkt; 5537 5538 txsd = &txq->sdesc[eq->cidx]; 5539 ndesc = txsd->desc_used; 5540 5541 /* Firmware doesn't return "partial" credits. */ 5542 KASSERT(can_reclaim >= ndesc, 5543 ("%s: unexpected number of credits: %d, %d", 5544 __func__, can_reclaim, ndesc)); 5545 KASSERT(ndesc != 0, 5546 ("%s: descriptor with no credits: cidx %d", 5547 __func__, eq->cidx)); 5548 5549 for (m = txsd->m; m != NULL; m = nextpkt) { 5550 nextpkt = m->m_nextpkt; 5551 m->m_nextpkt = NULL; 5552 m_freem(m); 5553 } 5554 reclaimed += ndesc; 5555 can_reclaim -= ndesc; 5556 IDXINCR(eq->cidx, ndesc, eq->sidx); 5557 } 5558 5559 return (reclaimed); 5560 } 5561 5562 static void 5563 tx_reclaim(void *arg, int n) 5564 { 5565 struct sge_txq *txq = arg; 5566 struct sge_eq *eq = &txq->eq; 5567 5568 do { 5569 if (TXQ_TRYLOCK(txq) == 0) 5570 break; 5571 n = reclaim_tx_descs(txq, 32); 5572 if (eq->cidx == eq->pidx) 5573 eq->equeqidx = eq->pidx; 5574 TXQ_UNLOCK(txq); 5575 } while (n > 0); 5576 } 5577 5578 static __be64 5579 get_flit(struct sglist_seg *segs, int nsegs, int idx) 5580 { 5581 int i = (idx / 3) * 2; 5582 5583 switch (idx % 3) { 5584 case 0: { 5585 uint64_t rc; 5586 5587 rc = (uint64_t)segs[i].ss_len << 32; 5588 if (i + 1 < nsegs) 5589 rc |= (uint64_t)(segs[i + 1].ss_len); 5590 5591 return (htobe64(rc)); 5592 } 5593 case 1: 5594 return (htobe64(segs[i].ss_paddr)); 5595 case 2: 5596 return (htobe64(segs[i + 1].ss_paddr)); 5597 } 5598 5599 return (0); 5600 } 5601 5602 static int 5603 find_refill_source(struct adapter *sc, int maxp, bool packing) 5604 { 5605 int i, zidx = -1; 5606 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[0]; 5607 5608 if (packing) { 5609 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) { 5610 if (rxb->hwidx2 == -1) 5611 continue; 5612 if (rxb->size1 < PAGE_SIZE && 5613 rxb->size1 < largest_rx_cluster) 5614 continue; 5615 if (rxb->size1 > largest_rx_cluster) 5616 break; 5617 MPASS(rxb->size1 - rxb->size2 >= CL_METADATA_SIZE); 5618 if (rxb->size2 >= maxp) 5619 return (i); 5620 zidx = i; 5621 } 5622 } else { 5623 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) { 5624 if (rxb->hwidx1 == -1) 5625 continue; 5626 if (rxb->size1 > largest_rx_cluster) 5627 break; 5628 if (rxb->size1 >= maxp) 5629 return (i); 5630 zidx = i; 5631 } 5632 } 5633 5634 return (zidx); 5635 } 5636 5637 static void 5638 add_fl_to_sfl(struct adapter *sc, struct sge_fl *fl) 5639 { 5640 mtx_lock(&sc->sfl_lock); 5641 FL_LOCK(fl); 5642 if ((fl->flags & FL_DOOMED) == 0) { 5643 fl->flags |= FL_STARVING; 5644 TAILQ_INSERT_TAIL(&sc->sfl, fl, link); 5645 callout_reset(&sc->sfl_callout, hz / 5, refill_sfl, sc); 5646 } 5647 FL_UNLOCK(fl); 5648 mtx_unlock(&sc->sfl_lock); 5649 } 5650 5651 static void 5652 handle_wrq_egr_update(struct adapter *sc, struct sge_eq *eq) 5653 { 5654 struct sge_wrq *wrq = (void *)eq; 5655 5656 atomic_readandclear_int(&eq->equiq); 5657 taskqueue_enqueue(sc->tq[eq->tx_chan], &wrq->wrq_tx_task); 5658 } 5659 5660 static void 5661 handle_eth_egr_update(struct adapter *sc, struct sge_eq *eq) 5662 { 5663 struct sge_txq *txq = (void *)eq; 5664 5665 MPASS((eq->flags & EQ_TYPEMASK) == EQ_ETH); 5666 5667 atomic_readandclear_int(&eq->equiq); 5668 if (mp_ring_is_idle(txq->r)) 5669 taskqueue_enqueue(sc->tq[eq->tx_chan], &txq->tx_reclaim_task); 5670 else 5671 mp_ring_check_drainage(txq->r, 64); 5672 } 5673 5674 static int 5675 handle_sge_egr_update(struct sge_iq *iq, const struct rss_header *rss, 5676 struct mbuf *m) 5677 { 5678 const struct cpl_sge_egr_update *cpl = (const void *)(rss + 1); 5679 unsigned int qid = G_EGR_QID(ntohl(cpl->opcode_qid)); 5680 struct adapter *sc = iq->adapter; 5681 struct sge *s = &sc->sge; 5682 struct sge_eq *eq; 5683 static void (*h[])(struct adapter *, struct sge_eq *) = {NULL, 5684 &handle_wrq_egr_update, &handle_eth_egr_update, 5685 &handle_wrq_egr_update}; 5686 5687 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 5688 rss->opcode)); 5689 5690 eq = s->eqmap[qid - s->eq_start - s->eq_base]; 5691 (*h[eq->flags & EQ_TYPEMASK])(sc, eq); 5692 5693 return (0); 5694 } 5695 5696 /* handle_fw_msg works for both fw4_msg and fw6_msg because this is valid */ 5697 CTASSERT(offsetof(struct cpl_fw4_msg, data) == \ 5698 offsetof(struct cpl_fw6_msg, data)); 5699 5700 static int 5701 handle_fw_msg(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 5702 { 5703 struct adapter *sc = iq->adapter; 5704 const struct cpl_fw6_msg *cpl = (const void *)(rss + 1); 5705 5706 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 5707 rss->opcode)); 5708 5709 if (cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL) { 5710 const struct rss_header *rss2; 5711 5712 rss2 = (const struct rss_header *)&cpl->data[0]; 5713 return (t4_cpl_handler[rss2->opcode](iq, rss2, m)); 5714 } 5715 5716 return (t4_fw_msg_handler[cpl->type](sc, &cpl->data[0])); 5717 } 5718 5719 /** 5720 * t4_handle_wrerr_rpl - process a FW work request error message 5721 * @adap: the adapter 5722 * @rpl: start of the FW message 5723 */ 5724 static int 5725 t4_handle_wrerr_rpl(struct adapter *adap, const __be64 *rpl) 5726 { 5727 u8 opcode = *(const u8 *)rpl; 5728 const struct fw_error_cmd *e = (const void *)rpl; 5729 unsigned int i; 5730 5731 if (opcode != FW_ERROR_CMD) { 5732 log(LOG_ERR, 5733 "%s: Received WRERR_RPL message with opcode %#x\n", 5734 device_get_nameunit(adap->dev), opcode); 5735 return (EINVAL); 5736 } 5737 log(LOG_ERR, "%s: FW_ERROR (%s) ", device_get_nameunit(adap->dev), 5738 G_FW_ERROR_CMD_FATAL(be32toh(e->op_to_type)) ? "fatal" : 5739 "non-fatal"); 5740 switch (G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type))) { 5741 case FW_ERROR_TYPE_EXCEPTION: 5742 log(LOG_ERR, "exception info:\n"); 5743 for (i = 0; i < nitems(e->u.exception.info); i++) 5744 log(LOG_ERR, "%s%08x", i == 0 ? "\t" : " ", 5745 be32toh(e->u.exception.info[i])); 5746 log(LOG_ERR, "\n"); 5747 break; 5748 case FW_ERROR_TYPE_HWMODULE: 5749 log(LOG_ERR, "HW module regaddr %08x regval %08x\n", 5750 be32toh(e->u.hwmodule.regaddr), 5751 be32toh(e->u.hwmodule.regval)); 5752 break; 5753 case FW_ERROR_TYPE_WR: 5754 log(LOG_ERR, "WR cidx %d PF %d VF %d eqid %d hdr:\n", 5755 be16toh(e->u.wr.cidx), 5756 G_FW_ERROR_CMD_PFN(be16toh(e->u.wr.pfn_vfn)), 5757 G_FW_ERROR_CMD_VFN(be16toh(e->u.wr.pfn_vfn)), 5758 be32toh(e->u.wr.eqid)); 5759 for (i = 0; i < nitems(e->u.wr.wrhdr); i++) 5760 log(LOG_ERR, "%s%02x", i == 0 ? "\t" : " ", 5761 e->u.wr.wrhdr[i]); 5762 log(LOG_ERR, "\n"); 5763 break; 5764 case FW_ERROR_TYPE_ACL: 5765 log(LOG_ERR, "ACL cidx %d PF %d VF %d eqid %d %s", 5766 be16toh(e->u.acl.cidx), 5767 G_FW_ERROR_CMD_PFN(be16toh(e->u.acl.pfn_vfn)), 5768 G_FW_ERROR_CMD_VFN(be16toh(e->u.acl.pfn_vfn)), 5769 be32toh(e->u.acl.eqid), 5770 G_FW_ERROR_CMD_MV(be16toh(e->u.acl.mv_pkd)) ? "vlanid" : 5771 "MAC"); 5772 for (i = 0; i < nitems(e->u.acl.val); i++) 5773 log(LOG_ERR, " %02x", e->u.acl.val[i]); 5774 log(LOG_ERR, "\n"); 5775 break; 5776 default: 5777 log(LOG_ERR, "type %#x\n", 5778 G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type))); 5779 return (EINVAL); 5780 } 5781 return (0); 5782 } 5783 5784 static int 5785 sysctl_uint16(SYSCTL_HANDLER_ARGS) 5786 { 5787 uint16_t *id = arg1; 5788 int i = *id; 5789 5790 return sysctl_handle_int(oidp, &i, 0, req); 5791 } 5792 5793 static inline bool 5794 bufidx_used(struct adapter *sc, int idx) 5795 { 5796 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[0]; 5797 int i; 5798 5799 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) { 5800 if (rxb->size1 > largest_rx_cluster) 5801 continue; 5802 if (rxb->hwidx1 == idx || rxb->hwidx2 == idx) 5803 return (true); 5804 } 5805 5806 return (false); 5807 } 5808 5809 static int 5810 sysctl_bufsizes(SYSCTL_HANDLER_ARGS) 5811 { 5812 struct adapter *sc = arg1; 5813 struct sge_params *sp = &sc->params.sge; 5814 int i, rc; 5815 struct sbuf sb; 5816 char c; 5817 5818 sbuf_new(&sb, NULL, 128, SBUF_AUTOEXTEND); 5819 for (i = 0; i < SGE_FLBUF_SIZES; i++) { 5820 if (bufidx_used(sc, i)) 5821 c = '*'; 5822 else 5823 c = '\0'; 5824 5825 sbuf_printf(&sb, "%u%c ", sp->sge_fl_buffer_size[i], c); 5826 } 5827 sbuf_trim(&sb); 5828 sbuf_finish(&sb); 5829 rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req); 5830 sbuf_delete(&sb); 5831 return (rc); 5832 } 5833 5834 #ifdef RATELIMIT 5835 /* 5836 * len16 for a txpkt WR with a GL. Includes the firmware work request header. 5837 */ 5838 static inline u_int 5839 txpkt_eo_len16(u_int nsegs, u_int immhdrs, u_int tso) 5840 { 5841 u_int n; 5842 5843 MPASS(immhdrs > 0); 5844 5845 n = roundup2(sizeof(struct fw_eth_tx_eo_wr) + 5846 sizeof(struct cpl_tx_pkt_core) + immhdrs, 16); 5847 if (__predict_false(nsegs == 0)) 5848 goto done; 5849 5850 nsegs--; /* first segment is part of ulptx_sgl */ 5851 n += sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 5852 if (tso) 5853 n += sizeof(struct cpl_tx_pkt_lso_core); 5854 5855 done: 5856 return (howmany(n, 16)); 5857 } 5858 5859 #define ETID_FLOWC_NPARAMS 6 5860 #define ETID_FLOWC_LEN (roundup2((sizeof(struct fw_flowc_wr) + \ 5861 ETID_FLOWC_NPARAMS * sizeof(struct fw_flowc_mnemval)), 16)) 5862 #define ETID_FLOWC_LEN16 (howmany(ETID_FLOWC_LEN, 16)) 5863 5864 static int 5865 send_etid_flowc_wr(struct cxgbe_rate_tag *cst, struct port_info *pi, 5866 struct vi_info *vi) 5867 { 5868 struct wrq_cookie cookie; 5869 u_int pfvf = pi->adapter->pf << S_FW_VIID_PFN; 5870 struct fw_flowc_wr *flowc; 5871 5872 mtx_assert(&cst->lock, MA_OWNED); 5873 MPASS((cst->flags & (EO_FLOWC_PENDING | EO_FLOWC_RPL_PENDING)) == 5874 EO_FLOWC_PENDING); 5875 5876 flowc = start_wrq_wr(cst->eo_txq, ETID_FLOWC_LEN16, &cookie); 5877 if (__predict_false(flowc == NULL)) 5878 return (ENOMEM); 5879 5880 bzero(flowc, ETID_FLOWC_LEN); 5881 flowc->op_to_nparams = htobe32(V_FW_WR_OP(FW_FLOWC_WR) | 5882 V_FW_FLOWC_WR_NPARAMS(ETID_FLOWC_NPARAMS) | V_FW_WR_COMPL(0)); 5883 flowc->flowid_len16 = htonl(V_FW_WR_LEN16(ETID_FLOWC_LEN16) | 5884 V_FW_WR_FLOWID(cst->etid)); 5885 flowc->mnemval[0].mnemonic = FW_FLOWC_MNEM_PFNVFN; 5886 flowc->mnemval[0].val = htobe32(pfvf); 5887 flowc->mnemval[1].mnemonic = FW_FLOWC_MNEM_CH; 5888 flowc->mnemval[1].val = htobe32(pi->tx_chan); 5889 flowc->mnemval[2].mnemonic = FW_FLOWC_MNEM_PORT; 5890 flowc->mnemval[2].val = htobe32(pi->tx_chan); 5891 flowc->mnemval[3].mnemonic = FW_FLOWC_MNEM_IQID; 5892 flowc->mnemval[3].val = htobe32(cst->iqid); 5893 flowc->mnemval[4].mnemonic = FW_FLOWC_MNEM_EOSTATE; 5894 flowc->mnemval[4].val = htobe32(FW_FLOWC_MNEM_EOSTATE_ESTABLISHED); 5895 flowc->mnemval[5].mnemonic = FW_FLOWC_MNEM_SCHEDCLASS; 5896 flowc->mnemval[5].val = htobe32(cst->schedcl); 5897 5898 commit_wrq_wr(cst->eo_txq, flowc, &cookie); 5899 5900 cst->flags &= ~EO_FLOWC_PENDING; 5901 cst->flags |= EO_FLOWC_RPL_PENDING; 5902 MPASS(cst->tx_credits >= ETID_FLOWC_LEN16); /* flowc is first WR. */ 5903 cst->tx_credits -= ETID_FLOWC_LEN16; 5904 5905 return (0); 5906 } 5907 5908 #define ETID_FLUSH_LEN16 (howmany(sizeof (struct fw_flowc_wr), 16)) 5909 5910 void 5911 send_etid_flush_wr(struct cxgbe_rate_tag *cst) 5912 { 5913 struct fw_flowc_wr *flowc; 5914 struct wrq_cookie cookie; 5915 5916 mtx_assert(&cst->lock, MA_OWNED); 5917 5918 flowc = start_wrq_wr(cst->eo_txq, ETID_FLUSH_LEN16, &cookie); 5919 if (__predict_false(flowc == NULL)) 5920 CXGBE_UNIMPLEMENTED(__func__); 5921 5922 bzero(flowc, ETID_FLUSH_LEN16 * 16); 5923 flowc->op_to_nparams = htobe32(V_FW_WR_OP(FW_FLOWC_WR) | 5924 V_FW_FLOWC_WR_NPARAMS(0) | F_FW_WR_COMPL); 5925 flowc->flowid_len16 = htobe32(V_FW_WR_LEN16(ETID_FLUSH_LEN16) | 5926 V_FW_WR_FLOWID(cst->etid)); 5927 5928 commit_wrq_wr(cst->eo_txq, flowc, &cookie); 5929 5930 cst->flags |= EO_FLUSH_RPL_PENDING; 5931 MPASS(cst->tx_credits >= ETID_FLUSH_LEN16); 5932 cst->tx_credits -= ETID_FLUSH_LEN16; 5933 cst->ncompl++; 5934 } 5935 5936 static void 5937 write_ethofld_wr(struct cxgbe_rate_tag *cst, struct fw_eth_tx_eo_wr *wr, 5938 struct mbuf *m0, int compl) 5939 { 5940 struct cpl_tx_pkt_core *cpl; 5941 uint64_t ctrl1; 5942 uint32_t ctrl; /* used in many unrelated places */ 5943 int len16, pktlen, nsegs, immhdrs; 5944 caddr_t dst; 5945 uintptr_t p; 5946 struct ulptx_sgl *usgl; 5947 struct sglist sg; 5948 struct sglist_seg segs[38]; /* XXX: find real limit. XXX: get off the stack */ 5949 5950 mtx_assert(&cst->lock, MA_OWNED); 5951 M_ASSERTPKTHDR(m0); 5952 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 5953 m0->m_pkthdr.l4hlen > 0, 5954 ("%s: ethofld mbuf %p is missing header lengths", __func__, m0)); 5955 5956 len16 = mbuf_eo_len16(m0); 5957 nsegs = mbuf_eo_nsegs(m0); 5958 pktlen = m0->m_pkthdr.len; 5959 ctrl = sizeof(struct cpl_tx_pkt_core); 5960 if (needs_tso(m0)) 5961 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 5962 immhdrs = m0->m_pkthdr.l2hlen + m0->m_pkthdr.l3hlen + m0->m_pkthdr.l4hlen; 5963 ctrl += immhdrs; 5964 5965 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_EO_WR) | 5966 V_FW_ETH_TX_EO_WR_IMMDLEN(ctrl) | V_FW_WR_COMPL(!!compl)); 5967 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(len16) | 5968 V_FW_WR_FLOWID(cst->etid)); 5969 wr->r3 = 0; 5970 if (needs_udp_csum(m0)) { 5971 wr->u.udpseg.type = FW_ETH_TX_EO_TYPE_UDPSEG; 5972 wr->u.udpseg.ethlen = m0->m_pkthdr.l2hlen; 5973 wr->u.udpseg.iplen = htobe16(m0->m_pkthdr.l3hlen); 5974 wr->u.udpseg.udplen = m0->m_pkthdr.l4hlen; 5975 wr->u.udpseg.rtplen = 0; 5976 wr->u.udpseg.r4 = 0; 5977 wr->u.udpseg.mss = htobe16(pktlen - immhdrs); 5978 wr->u.udpseg.schedpktsize = wr->u.udpseg.mss; 5979 wr->u.udpseg.plen = htobe32(pktlen - immhdrs); 5980 cpl = (void *)(wr + 1); 5981 } else { 5982 MPASS(needs_tcp_csum(m0)); 5983 wr->u.tcpseg.type = FW_ETH_TX_EO_TYPE_TCPSEG; 5984 wr->u.tcpseg.ethlen = m0->m_pkthdr.l2hlen; 5985 wr->u.tcpseg.iplen = htobe16(m0->m_pkthdr.l3hlen); 5986 wr->u.tcpseg.tcplen = m0->m_pkthdr.l4hlen; 5987 wr->u.tcpseg.tsclk_tsoff = mbuf_eo_tsclk_tsoff(m0); 5988 wr->u.tcpseg.r4 = 0; 5989 wr->u.tcpseg.r5 = 0; 5990 wr->u.tcpseg.plen = htobe32(pktlen - immhdrs); 5991 5992 if (needs_tso(m0)) { 5993 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1); 5994 5995 wr->u.tcpseg.mss = htobe16(m0->m_pkthdr.tso_segsz); 5996 5997 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | 5998 F_LSO_FIRST_SLICE | F_LSO_LAST_SLICE | 5999 V_LSO_ETHHDR_LEN((m0->m_pkthdr.l2hlen - 6000 ETHER_HDR_LEN) >> 2) | 6001 V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) | 6002 V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2); 6003 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 6004 ctrl |= F_LSO_IPV6; 6005 lso->lso_ctrl = htobe32(ctrl); 6006 lso->ipid_ofst = htobe16(0); 6007 lso->mss = htobe16(m0->m_pkthdr.tso_segsz); 6008 lso->seqno_offset = htobe32(0); 6009 lso->len = htobe32(pktlen); 6010 6011 cpl = (void *)(lso + 1); 6012 } else { 6013 wr->u.tcpseg.mss = htobe16(0xffff); 6014 cpl = (void *)(wr + 1); 6015 } 6016 } 6017 6018 /* Checksum offload must be requested for ethofld. */ 6019 MPASS(needs_l4_csum(m0)); 6020 ctrl1 = csum_to_ctrl(cst->adapter, m0); 6021 6022 /* VLAN tag insertion */ 6023 if (needs_vlan_insertion(m0)) { 6024 ctrl1 |= F_TXPKT_VLAN_VLD | 6025 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 6026 } 6027 6028 /* CPL header */ 6029 cpl->ctrl0 = cst->ctrl0; 6030 cpl->pack = 0; 6031 cpl->len = htobe16(pktlen); 6032 cpl->ctrl1 = htobe64(ctrl1); 6033 6034 /* Copy Ethernet, IP & TCP/UDP hdrs as immediate data */ 6035 p = (uintptr_t)(cpl + 1); 6036 m_copydata(m0, 0, immhdrs, (void *)p); 6037 6038 /* SGL */ 6039 dst = (void *)(cpl + 1); 6040 if (nsegs > 0) { 6041 int i, pad; 6042 6043 /* zero-pad upto next 16Byte boundary, if not 16Byte aligned */ 6044 p += immhdrs; 6045 pad = 16 - (immhdrs & 0xf); 6046 bzero((void *)p, pad); 6047 6048 usgl = (void *)(p + pad); 6049 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 6050 V_ULPTX_NSGE(nsegs)); 6051 6052 sglist_init(&sg, nitems(segs), segs); 6053 for (; m0 != NULL; m0 = m0->m_next) { 6054 if (__predict_false(m0->m_len == 0)) 6055 continue; 6056 if (immhdrs >= m0->m_len) { 6057 immhdrs -= m0->m_len; 6058 continue; 6059 } 6060 if (m0->m_flags & M_EXTPG) 6061 sglist_append_mbuf_epg(&sg, m0, 6062 mtod(m0, vm_offset_t), m0->m_len); 6063 else 6064 sglist_append(&sg, mtod(m0, char *) + immhdrs, 6065 m0->m_len - immhdrs); 6066 immhdrs = 0; 6067 } 6068 MPASS(sg.sg_nseg == nsegs); 6069 6070 /* 6071 * Zero pad last 8B in case the WR doesn't end on a 16B 6072 * boundary. 6073 */ 6074 *(uint64_t *)((char *)wr + len16 * 16 - 8) = 0; 6075 6076 usgl->len0 = htobe32(segs[0].ss_len); 6077 usgl->addr0 = htobe64(segs[0].ss_paddr); 6078 for (i = 0; i < nsegs - 1; i++) { 6079 usgl->sge[i / 2].len[i & 1] = htobe32(segs[i + 1].ss_len); 6080 usgl->sge[i / 2].addr[i & 1] = htobe64(segs[i + 1].ss_paddr); 6081 } 6082 if (i & 1) 6083 usgl->sge[i / 2].len[1] = htobe32(0); 6084 } 6085 6086 } 6087 6088 static void 6089 ethofld_tx(struct cxgbe_rate_tag *cst) 6090 { 6091 struct mbuf *m; 6092 struct wrq_cookie cookie; 6093 int next_credits, compl; 6094 struct fw_eth_tx_eo_wr *wr; 6095 6096 mtx_assert(&cst->lock, MA_OWNED); 6097 6098 while ((m = mbufq_first(&cst->pending_tx)) != NULL) { 6099 M_ASSERTPKTHDR(m); 6100 6101 /* How many len16 credits do we need to send this mbuf. */ 6102 next_credits = mbuf_eo_len16(m); 6103 MPASS(next_credits > 0); 6104 if (next_credits > cst->tx_credits) { 6105 /* 6106 * Tx will make progress eventually because there is at 6107 * least one outstanding fw4_ack that will return 6108 * credits and kick the tx. 6109 */ 6110 MPASS(cst->ncompl > 0); 6111 return; 6112 } 6113 wr = start_wrq_wr(cst->eo_txq, next_credits, &cookie); 6114 if (__predict_false(wr == NULL)) { 6115 /* XXX: wishful thinking, not a real assertion. */ 6116 MPASS(cst->ncompl > 0); 6117 return; 6118 } 6119 cst->tx_credits -= next_credits; 6120 cst->tx_nocompl += next_credits; 6121 compl = cst->ncompl == 0 || cst->tx_nocompl >= cst->tx_total / 2; 6122 ETHER_BPF_MTAP(cst->com.com.ifp, m); 6123 write_ethofld_wr(cst, wr, m, compl); 6124 commit_wrq_wr(cst->eo_txq, wr, &cookie); 6125 if (compl) { 6126 cst->ncompl++; 6127 cst->tx_nocompl = 0; 6128 } 6129 (void) mbufq_dequeue(&cst->pending_tx); 6130 6131 /* 6132 * Drop the mbuf's reference on the tag now rather 6133 * than waiting until m_freem(). This ensures that 6134 * cxgbe_rate_tag_free gets called when the inp drops 6135 * its reference on the tag and there are no more 6136 * mbufs in the pending_tx queue and can flush any 6137 * pending requests. Otherwise if the last mbuf 6138 * doesn't request a completion the etid will never be 6139 * released. 6140 */ 6141 m->m_pkthdr.snd_tag = NULL; 6142 m->m_pkthdr.csum_flags &= ~CSUM_SND_TAG; 6143 m_snd_tag_rele(&cst->com.com); 6144 6145 mbufq_enqueue(&cst->pending_fwack, m); 6146 } 6147 } 6148 6149 int 6150 ethofld_transmit(struct ifnet *ifp, struct mbuf *m0) 6151 { 6152 struct cxgbe_rate_tag *cst; 6153 int rc; 6154 6155 MPASS(m0->m_nextpkt == NULL); 6156 MPASS(m0->m_pkthdr.csum_flags & CSUM_SND_TAG); 6157 MPASS(m0->m_pkthdr.snd_tag != NULL); 6158 cst = mst_to_crt(m0->m_pkthdr.snd_tag); 6159 6160 mtx_lock(&cst->lock); 6161 MPASS(cst->flags & EO_SND_TAG_REF); 6162 6163 if (__predict_false(cst->flags & EO_FLOWC_PENDING)) { 6164 struct vi_info *vi = ifp->if_softc; 6165 struct port_info *pi = vi->pi; 6166 struct adapter *sc = pi->adapter; 6167 const uint32_t rss_mask = vi->rss_size - 1; 6168 uint32_t rss_hash; 6169 6170 cst->eo_txq = &sc->sge.ofld_txq[vi->first_ofld_txq]; 6171 if (M_HASHTYPE_ISHASH(m0)) 6172 rss_hash = m0->m_pkthdr.flowid; 6173 else 6174 rss_hash = arc4random(); 6175 /* We assume RSS hashing */ 6176 cst->iqid = vi->rss[rss_hash & rss_mask]; 6177 cst->eo_txq += rss_hash % vi->nofldtxq; 6178 rc = send_etid_flowc_wr(cst, pi, vi); 6179 if (rc != 0) 6180 goto done; 6181 } 6182 6183 if (__predict_false(cst->plen + m0->m_pkthdr.len > eo_max_backlog)) { 6184 rc = ENOBUFS; 6185 goto done; 6186 } 6187 6188 mbufq_enqueue(&cst->pending_tx, m0); 6189 cst->plen += m0->m_pkthdr.len; 6190 6191 /* 6192 * Hold an extra reference on the tag while generating work 6193 * requests to ensure that we don't try to free the tag during 6194 * ethofld_tx() in case we are sending the final mbuf after 6195 * the inp was freed. 6196 */ 6197 m_snd_tag_ref(&cst->com.com); 6198 ethofld_tx(cst); 6199 mtx_unlock(&cst->lock); 6200 m_snd_tag_rele(&cst->com.com); 6201 return (0); 6202 6203 done: 6204 mtx_unlock(&cst->lock); 6205 if (__predict_false(rc != 0)) 6206 m_freem(m0); 6207 return (rc); 6208 } 6209 6210 static int 6211 ethofld_fw4_ack(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0) 6212 { 6213 struct adapter *sc = iq->adapter; 6214 const struct cpl_fw4_ack *cpl = (const void *)(rss + 1); 6215 struct mbuf *m; 6216 u_int etid = G_CPL_FW4_ACK_FLOWID(be32toh(OPCODE_TID(cpl))); 6217 struct cxgbe_rate_tag *cst; 6218 uint8_t credits = cpl->credits; 6219 6220 cst = lookup_etid(sc, etid); 6221 mtx_lock(&cst->lock); 6222 if (__predict_false(cst->flags & EO_FLOWC_RPL_PENDING)) { 6223 MPASS(credits >= ETID_FLOWC_LEN16); 6224 credits -= ETID_FLOWC_LEN16; 6225 cst->flags &= ~EO_FLOWC_RPL_PENDING; 6226 } 6227 6228 KASSERT(cst->ncompl > 0, 6229 ("%s: etid %u (%p) wasn't expecting completion.", 6230 __func__, etid, cst)); 6231 cst->ncompl--; 6232 6233 while (credits > 0) { 6234 m = mbufq_dequeue(&cst->pending_fwack); 6235 if (__predict_false(m == NULL)) { 6236 /* 6237 * The remaining credits are for the final flush that 6238 * was issued when the tag was freed by the kernel. 6239 */ 6240 MPASS((cst->flags & 6241 (EO_FLUSH_RPL_PENDING | EO_SND_TAG_REF)) == 6242 EO_FLUSH_RPL_PENDING); 6243 MPASS(credits == ETID_FLUSH_LEN16); 6244 MPASS(cst->tx_credits + cpl->credits == cst->tx_total); 6245 MPASS(cst->ncompl == 0); 6246 6247 cst->flags &= ~EO_FLUSH_RPL_PENDING; 6248 cst->tx_credits += cpl->credits; 6249 cxgbe_rate_tag_free_locked(cst); 6250 return (0); /* cst is gone. */ 6251 } 6252 KASSERT(m != NULL, 6253 ("%s: too many credits (%u, %u)", __func__, cpl->credits, 6254 credits)); 6255 KASSERT(credits >= mbuf_eo_len16(m), 6256 ("%s: too few credits (%u, %u, %u)", __func__, 6257 cpl->credits, credits, mbuf_eo_len16(m))); 6258 credits -= mbuf_eo_len16(m); 6259 cst->plen -= m->m_pkthdr.len; 6260 m_freem(m); 6261 } 6262 6263 cst->tx_credits += cpl->credits; 6264 MPASS(cst->tx_credits <= cst->tx_total); 6265 6266 if (cst->flags & EO_SND_TAG_REF) { 6267 /* 6268 * As with ethofld_transmit(), hold an extra reference 6269 * so that the tag is stable across ethold_tx(). 6270 */ 6271 m_snd_tag_ref(&cst->com.com); 6272 m = mbufq_first(&cst->pending_tx); 6273 if (m != NULL && cst->tx_credits >= mbuf_eo_len16(m)) 6274 ethofld_tx(cst); 6275 mtx_unlock(&cst->lock); 6276 m_snd_tag_rele(&cst->com.com); 6277 } else { 6278 /* 6279 * There shouldn't be any pending packets if the tag 6280 * was freed by the kernel since any pending packet 6281 * should hold a reference to the tag. 6282 */ 6283 MPASS(mbufq_first(&cst->pending_tx) == NULL); 6284 mtx_unlock(&cst->lock); 6285 } 6286 6287 return (0); 6288 } 6289 #endif 6290