1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 Chelsio Communications, Inc. 5 * All rights reserved. 6 * Written by: Navdeep Parhar <np@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include "opt_inet.h" 34 #include "opt_inet6.h" 35 #include "opt_ratelimit.h" 36 37 #include <sys/types.h> 38 #include <sys/eventhandler.h> 39 #include <sys/mbuf.h> 40 #include <sys/socket.h> 41 #include <sys/kernel.h> 42 #include <sys/malloc.h> 43 #include <sys/queue.h> 44 #include <sys/sbuf.h> 45 #include <sys/taskqueue.h> 46 #include <sys/time.h> 47 #include <sys/sglist.h> 48 #include <sys/sysctl.h> 49 #include <sys/smp.h> 50 #include <sys/counter.h> 51 #include <net/bpf.h> 52 #include <net/ethernet.h> 53 #include <net/if.h> 54 #include <net/if_vlan_var.h> 55 #include <netinet/in.h> 56 #include <netinet/ip.h> 57 #include <netinet/ip6.h> 58 #include <netinet/tcp.h> 59 #include <netinet/udp.h> 60 #include <machine/in_cksum.h> 61 #include <machine/md_var.h> 62 #include <vm/vm.h> 63 #include <vm/pmap.h> 64 #ifdef DEV_NETMAP 65 #include <machine/bus.h> 66 #include <sys/selinfo.h> 67 #include <net/if_var.h> 68 #include <net/netmap.h> 69 #include <dev/netmap/netmap_kern.h> 70 #endif 71 72 #include "common/common.h" 73 #include "common/t4_regs.h" 74 #include "common/t4_regs_values.h" 75 #include "common/t4_msg.h" 76 #include "t4_l2t.h" 77 #include "t4_mp_ring.h" 78 79 #ifdef T4_PKT_TIMESTAMP 80 #define RX_COPY_THRESHOLD (MINCLSIZE - 8) 81 #else 82 #define RX_COPY_THRESHOLD MINCLSIZE 83 #endif 84 85 /* Internal mbuf flags stored in PH_loc.eight[1]. */ 86 #define MC_RAW_WR 0x02 87 88 /* 89 * Ethernet frames are DMA'd at this byte offset into the freelist buffer. 90 * 0-7 are valid values. 91 */ 92 static int fl_pktshift = 0; 93 TUNABLE_INT("hw.cxgbe.fl_pktshift", &fl_pktshift); 94 95 /* 96 * Pad ethernet payload up to this boundary. 97 * -1: driver should figure out a good value. 98 * 0: disable padding. 99 * Any power of 2 from 32 to 4096 (both inclusive) is also a valid value. 100 */ 101 int fl_pad = -1; 102 TUNABLE_INT("hw.cxgbe.fl_pad", &fl_pad); 103 104 /* 105 * Status page length. 106 * -1: driver should figure out a good value. 107 * 64 or 128 are the only other valid values. 108 */ 109 static int spg_len = -1; 110 TUNABLE_INT("hw.cxgbe.spg_len", &spg_len); 111 112 /* 113 * Congestion drops. 114 * -1: no congestion feedback (not recommended). 115 * 0: backpressure the channel instead of dropping packets right away. 116 * 1: no backpressure, drop packets for the congested queue immediately. 117 */ 118 static int cong_drop = 0; 119 TUNABLE_INT("hw.cxgbe.cong_drop", &cong_drop); 120 121 /* 122 * Deliver multiple frames in the same free list buffer if they fit. 123 * -1: let the driver decide whether to enable buffer packing or not. 124 * 0: disable buffer packing. 125 * 1: enable buffer packing. 126 */ 127 static int buffer_packing = -1; 128 TUNABLE_INT("hw.cxgbe.buffer_packing", &buffer_packing); 129 130 /* 131 * Start next frame in a packed buffer at this boundary. 132 * -1: driver should figure out a good value. 133 * T4: driver will ignore this and use the same value as fl_pad above. 134 * T5: 16, or a power of 2 from 64 to 4096 (both inclusive) is a valid value. 135 */ 136 static int fl_pack = -1; 137 TUNABLE_INT("hw.cxgbe.fl_pack", &fl_pack); 138 139 /* 140 * Allow the driver to create mbuf(s) in a cluster allocated for rx. 141 * 0: never; always allocate mbufs from the zone_mbuf UMA zone. 142 * 1: ok to create mbuf(s) within a cluster if there is room. 143 */ 144 static int allow_mbufs_in_cluster = 1; 145 TUNABLE_INT("hw.cxgbe.allow_mbufs_in_cluster", &allow_mbufs_in_cluster); 146 147 /* 148 * Largest rx cluster size that the driver is allowed to allocate. 149 */ 150 static int largest_rx_cluster = MJUM16BYTES; 151 TUNABLE_INT("hw.cxgbe.largest_rx_cluster", &largest_rx_cluster); 152 153 /* 154 * Size of cluster allocation that's most likely to succeed. The driver will 155 * fall back to this size if it fails to allocate clusters larger than this. 156 */ 157 static int safest_rx_cluster = PAGE_SIZE; 158 TUNABLE_INT("hw.cxgbe.safest_rx_cluster", &safest_rx_cluster); 159 160 #ifdef RATELIMIT 161 /* 162 * Knob to control TCP timestamp rewriting, and the granularity of the tick used 163 * for rewriting. -1 and 0-3 are all valid values. 164 * -1: hardware should leave the TCP timestamps alone. 165 * 0: 1ms 166 * 1: 100us 167 * 2: 10us 168 * 3: 1us 169 */ 170 static int tsclk = -1; 171 TUNABLE_INT("hw.cxgbe.tsclk", &tsclk); 172 173 static int eo_max_backlog = 1024 * 1024; 174 TUNABLE_INT("hw.cxgbe.eo_max_backlog", &eo_max_backlog); 175 #endif 176 177 /* 178 * The interrupt holdoff timers are multiplied by this value on T6+. 179 * 1 and 3-17 (both inclusive) are legal values. 180 */ 181 static int tscale = 1; 182 TUNABLE_INT("hw.cxgbe.tscale", &tscale); 183 184 /* 185 * Number of LRO entries in the lro_ctrl structure per rx queue. 186 */ 187 static int lro_entries = TCP_LRO_ENTRIES; 188 TUNABLE_INT("hw.cxgbe.lro_entries", &lro_entries); 189 190 /* 191 * This enables presorting of frames before they're fed into tcp_lro_rx. 192 */ 193 static int lro_mbufs = 0; 194 TUNABLE_INT("hw.cxgbe.lro_mbufs", &lro_mbufs); 195 196 struct txpkts { 197 u_int wr_type; /* type 0 or type 1 */ 198 u_int npkt; /* # of packets in this work request */ 199 u_int plen; /* total payload (sum of all packets) */ 200 u_int len16; /* # of 16B pieces used by this work request */ 201 }; 202 203 /* A packet's SGL. This + m_pkthdr has all info needed for tx */ 204 struct sgl { 205 struct sglist sg; 206 struct sglist_seg seg[TX_SGL_SEGS]; 207 }; 208 209 static int service_iq(struct sge_iq *, int); 210 static int service_iq_fl(struct sge_iq *, int); 211 static struct mbuf *get_fl_payload(struct adapter *, struct sge_fl *, uint32_t); 212 static int t4_eth_rx(struct sge_iq *, const struct rss_header *, struct mbuf *); 213 static inline void init_iq(struct sge_iq *, struct adapter *, int, int, int); 214 static inline void init_fl(struct adapter *, struct sge_fl *, int, int, char *); 215 static inline void init_eq(struct adapter *, struct sge_eq *, int, int, uint8_t, 216 uint16_t, char *); 217 static int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *, 218 bus_addr_t *, void **); 219 static int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 220 void *); 221 static int alloc_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *, 222 int, int); 223 static int free_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *); 224 static void add_iq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *, 225 struct sge_iq *); 226 static void add_fl_sysctls(struct adapter *, struct sysctl_ctx_list *, 227 struct sysctl_oid *, struct sge_fl *); 228 static int alloc_fwq(struct adapter *); 229 static int free_fwq(struct adapter *); 230 static int alloc_ctrlq(struct adapter *, struct sge_wrq *, int, 231 struct sysctl_oid *); 232 static int alloc_rxq(struct vi_info *, struct sge_rxq *, int, int, 233 struct sysctl_oid *); 234 static int free_rxq(struct vi_info *, struct sge_rxq *); 235 #ifdef TCP_OFFLOAD 236 static int alloc_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *, int, int, 237 struct sysctl_oid *); 238 static int free_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *); 239 #endif 240 #ifdef DEV_NETMAP 241 static int alloc_nm_rxq(struct vi_info *, struct sge_nm_rxq *, int, int, 242 struct sysctl_oid *); 243 static int free_nm_rxq(struct vi_info *, struct sge_nm_rxq *); 244 static int alloc_nm_txq(struct vi_info *, struct sge_nm_txq *, int, int, 245 struct sysctl_oid *); 246 static int free_nm_txq(struct vi_info *, struct sge_nm_txq *); 247 #endif 248 static int ctrl_eq_alloc(struct adapter *, struct sge_eq *); 249 static int eth_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *); 250 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 251 static int ofld_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *); 252 #endif 253 static int alloc_eq(struct adapter *, struct vi_info *, struct sge_eq *); 254 static int free_eq(struct adapter *, struct sge_eq *); 255 static int alloc_wrq(struct adapter *, struct vi_info *, struct sge_wrq *, 256 struct sysctl_oid *); 257 static int free_wrq(struct adapter *, struct sge_wrq *); 258 static int alloc_txq(struct vi_info *, struct sge_txq *, int, 259 struct sysctl_oid *); 260 static int free_txq(struct vi_info *, struct sge_txq *); 261 static void oneseg_dma_callback(void *, bus_dma_segment_t *, int, int); 262 static inline void ring_fl_db(struct adapter *, struct sge_fl *); 263 static int refill_fl(struct adapter *, struct sge_fl *, int); 264 static void refill_sfl(void *); 265 static int alloc_fl_sdesc(struct sge_fl *); 266 static void free_fl_sdesc(struct adapter *, struct sge_fl *); 267 static void find_best_refill_source(struct adapter *, struct sge_fl *, int); 268 static void find_safe_refill_source(struct adapter *, struct sge_fl *); 269 static void add_fl_to_sfl(struct adapter *, struct sge_fl *); 270 271 static inline void get_pkt_gl(struct mbuf *, struct sglist *); 272 static inline u_int txpkt_len16(u_int, u_int); 273 static inline u_int txpkt_vm_len16(u_int, u_int); 274 static inline u_int txpkts0_len16(u_int); 275 static inline u_int txpkts1_len16(void); 276 static u_int write_raw_wr(struct sge_txq *, void *, struct mbuf *, u_int); 277 static u_int write_txpkt_wr(struct sge_txq *, struct fw_eth_tx_pkt_wr *, 278 struct mbuf *, u_int); 279 static u_int write_txpkt_vm_wr(struct adapter *, struct sge_txq *, 280 struct fw_eth_tx_pkt_vm_wr *, struct mbuf *, u_int); 281 static int try_txpkts(struct mbuf *, struct mbuf *, struct txpkts *, u_int); 282 static int add_to_txpkts(struct mbuf *, struct txpkts *, u_int); 283 static u_int write_txpkts_wr(struct sge_txq *, struct fw_eth_tx_pkts_wr *, 284 struct mbuf *, const struct txpkts *, u_int); 285 static void write_gl_to_txd(struct sge_txq *, struct mbuf *, caddr_t *, int); 286 static inline void copy_to_txd(struct sge_eq *, caddr_t, caddr_t *, int); 287 static inline void ring_eq_db(struct adapter *, struct sge_eq *, u_int); 288 static inline uint16_t read_hw_cidx(struct sge_eq *); 289 static inline u_int reclaimable_tx_desc(struct sge_eq *); 290 static inline u_int total_available_tx_desc(struct sge_eq *); 291 static u_int reclaim_tx_descs(struct sge_txq *, u_int); 292 static void tx_reclaim(void *, int); 293 static __be64 get_flit(struct sglist_seg *, int, int); 294 static int handle_sge_egr_update(struct sge_iq *, const struct rss_header *, 295 struct mbuf *); 296 static int handle_fw_msg(struct sge_iq *, const struct rss_header *, 297 struct mbuf *); 298 static int t4_handle_wrerr_rpl(struct adapter *, const __be64 *); 299 static void wrq_tx_drain(void *, int); 300 static void drain_wrq_wr_list(struct adapter *, struct sge_wrq *); 301 302 static int sysctl_uint16(SYSCTL_HANDLER_ARGS); 303 static int sysctl_bufsizes(SYSCTL_HANDLER_ARGS); 304 #ifdef RATELIMIT 305 static inline u_int txpkt_eo_len16(u_int, u_int, u_int); 306 static int ethofld_fw4_ack(struct sge_iq *, const struct rss_header *, 307 struct mbuf *); 308 #endif 309 310 static counter_u64_t extfree_refs; 311 static counter_u64_t extfree_rels; 312 313 an_handler_t t4_an_handler; 314 fw_msg_handler_t t4_fw_msg_handler[NUM_FW6_TYPES]; 315 cpl_handler_t t4_cpl_handler[NUM_CPL_CMDS]; 316 cpl_handler_t set_tcb_rpl_handlers[NUM_CPL_COOKIES]; 317 cpl_handler_t l2t_write_rpl_handlers[NUM_CPL_COOKIES]; 318 cpl_handler_t act_open_rpl_handlers[NUM_CPL_COOKIES]; 319 cpl_handler_t abort_rpl_rss_handlers[NUM_CPL_COOKIES]; 320 cpl_handler_t fw4_ack_handlers[NUM_CPL_COOKIES]; 321 322 void 323 t4_register_an_handler(an_handler_t h) 324 { 325 uintptr_t *loc; 326 327 MPASS(h == NULL || t4_an_handler == NULL); 328 329 loc = (uintptr_t *)&t4_an_handler; 330 atomic_store_rel_ptr(loc, (uintptr_t)h); 331 } 332 333 void 334 t4_register_fw_msg_handler(int type, fw_msg_handler_t h) 335 { 336 uintptr_t *loc; 337 338 MPASS(type < nitems(t4_fw_msg_handler)); 339 MPASS(h == NULL || t4_fw_msg_handler[type] == NULL); 340 /* 341 * These are dispatched by the handler for FW{4|6}_CPL_MSG using the CPL 342 * handler dispatch table. Reject any attempt to install a handler for 343 * this subtype. 344 */ 345 MPASS(type != FW_TYPE_RSSCPL); 346 MPASS(type != FW6_TYPE_RSSCPL); 347 348 loc = (uintptr_t *)&t4_fw_msg_handler[type]; 349 atomic_store_rel_ptr(loc, (uintptr_t)h); 350 } 351 352 void 353 t4_register_cpl_handler(int opcode, cpl_handler_t h) 354 { 355 uintptr_t *loc; 356 357 MPASS(opcode < nitems(t4_cpl_handler)); 358 MPASS(h == NULL || t4_cpl_handler[opcode] == NULL); 359 360 loc = (uintptr_t *)&t4_cpl_handler[opcode]; 361 atomic_store_rel_ptr(loc, (uintptr_t)h); 362 } 363 364 static int 365 set_tcb_rpl_handler(struct sge_iq *iq, const struct rss_header *rss, 366 struct mbuf *m) 367 { 368 const struct cpl_set_tcb_rpl *cpl = (const void *)(rss + 1); 369 u_int tid; 370 int cookie; 371 372 MPASS(m == NULL); 373 374 tid = GET_TID(cpl); 375 if (is_hpftid(iq->adapter, tid) || is_ftid(iq->adapter, tid)) { 376 /* 377 * The return code for filter-write is put in the CPL cookie so 378 * we have to rely on the hardware tid (is_ftid) to determine 379 * that this is a response to a filter. 380 */ 381 cookie = CPL_COOKIE_FILTER; 382 } else { 383 cookie = G_COOKIE(cpl->cookie); 384 } 385 MPASS(cookie > CPL_COOKIE_RESERVED); 386 MPASS(cookie < nitems(set_tcb_rpl_handlers)); 387 388 return (set_tcb_rpl_handlers[cookie](iq, rss, m)); 389 } 390 391 static int 392 l2t_write_rpl_handler(struct sge_iq *iq, const struct rss_header *rss, 393 struct mbuf *m) 394 { 395 const struct cpl_l2t_write_rpl *rpl = (const void *)(rss + 1); 396 unsigned int cookie; 397 398 MPASS(m == NULL); 399 400 cookie = GET_TID(rpl) & F_SYNC_WR ? CPL_COOKIE_TOM : CPL_COOKIE_FILTER; 401 return (l2t_write_rpl_handlers[cookie](iq, rss, m)); 402 } 403 404 static int 405 act_open_rpl_handler(struct sge_iq *iq, const struct rss_header *rss, 406 struct mbuf *m) 407 { 408 const struct cpl_act_open_rpl *cpl = (const void *)(rss + 1); 409 u_int cookie = G_TID_COOKIE(G_AOPEN_ATID(be32toh(cpl->atid_status))); 410 411 MPASS(m == NULL); 412 MPASS(cookie != CPL_COOKIE_RESERVED); 413 414 return (act_open_rpl_handlers[cookie](iq, rss, m)); 415 } 416 417 static int 418 abort_rpl_rss_handler(struct sge_iq *iq, const struct rss_header *rss, 419 struct mbuf *m) 420 { 421 struct adapter *sc = iq->adapter; 422 u_int cookie; 423 424 MPASS(m == NULL); 425 if (is_hashfilter(sc)) 426 cookie = CPL_COOKIE_HASHFILTER; 427 else 428 cookie = CPL_COOKIE_TOM; 429 430 return (abort_rpl_rss_handlers[cookie](iq, rss, m)); 431 } 432 433 static int 434 fw4_ack_handler(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 435 { 436 struct adapter *sc = iq->adapter; 437 const struct cpl_fw4_ack *cpl = (const void *)(rss + 1); 438 unsigned int tid = G_CPL_FW4_ACK_FLOWID(be32toh(OPCODE_TID(cpl))); 439 u_int cookie; 440 441 MPASS(m == NULL); 442 if (is_etid(sc, tid)) 443 cookie = CPL_COOKIE_ETHOFLD; 444 else 445 cookie = CPL_COOKIE_TOM; 446 447 return (fw4_ack_handlers[cookie](iq, rss, m)); 448 } 449 450 static void 451 t4_init_shared_cpl_handlers(void) 452 { 453 454 t4_register_cpl_handler(CPL_SET_TCB_RPL, set_tcb_rpl_handler); 455 t4_register_cpl_handler(CPL_L2T_WRITE_RPL, l2t_write_rpl_handler); 456 t4_register_cpl_handler(CPL_ACT_OPEN_RPL, act_open_rpl_handler); 457 t4_register_cpl_handler(CPL_ABORT_RPL_RSS, abort_rpl_rss_handler); 458 t4_register_cpl_handler(CPL_FW4_ACK, fw4_ack_handler); 459 } 460 461 void 462 t4_register_shared_cpl_handler(int opcode, cpl_handler_t h, int cookie) 463 { 464 uintptr_t *loc; 465 466 MPASS(opcode < nitems(t4_cpl_handler)); 467 MPASS(cookie > CPL_COOKIE_RESERVED); 468 MPASS(cookie < NUM_CPL_COOKIES); 469 MPASS(t4_cpl_handler[opcode] != NULL); 470 471 switch (opcode) { 472 case CPL_SET_TCB_RPL: 473 loc = (uintptr_t *)&set_tcb_rpl_handlers[cookie]; 474 break; 475 case CPL_L2T_WRITE_RPL: 476 loc = (uintptr_t *)&l2t_write_rpl_handlers[cookie]; 477 break; 478 case CPL_ACT_OPEN_RPL: 479 loc = (uintptr_t *)&act_open_rpl_handlers[cookie]; 480 break; 481 case CPL_ABORT_RPL_RSS: 482 loc = (uintptr_t *)&abort_rpl_rss_handlers[cookie]; 483 break; 484 case CPL_FW4_ACK: 485 loc = (uintptr_t *)&fw4_ack_handlers[cookie]; 486 break; 487 default: 488 MPASS(0); 489 return; 490 } 491 MPASS(h == NULL || *loc == (uintptr_t)NULL); 492 atomic_store_rel_ptr(loc, (uintptr_t)h); 493 } 494 495 /* 496 * Called on MOD_LOAD. Validates and calculates the SGE tunables. 497 */ 498 void 499 t4_sge_modload(void) 500 { 501 502 if (fl_pktshift < 0 || fl_pktshift > 7) { 503 printf("Invalid hw.cxgbe.fl_pktshift value (%d)," 504 " using 0 instead.\n", fl_pktshift); 505 fl_pktshift = 0; 506 } 507 508 if (spg_len != 64 && spg_len != 128) { 509 int len; 510 511 #if defined(__i386__) || defined(__amd64__) 512 len = cpu_clflush_line_size > 64 ? 128 : 64; 513 #else 514 len = 64; 515 #endif 516 if (spg_len != -1) { 517 printf("Invalid hw.cxgbe.spg_len value (%d)," 518 " using %d instead.\n", spg_len, len); 519 } 520 spg_len = len; 521 } 522 523 if (cong_drop < -1 || cong_drop > 1) { 524 printf("Invalid hw.cxgbe.cong_drop value (%d)," 525 " using 0 instead.\n", cong_drop); 526 cong_drop = 0; 527 } 528 529 if (tscale != 1 && (tscale < 3 || tscale > 17)) { 530 printf("Invalid hw.cxgbe.tscale value (%d)," 531 " using 1 instead.\n", tscale); 532 tscale = 1; 533 } 534 535 extfree_refs = counter_u64_alloc(M_WAITOK); 536 extfree_rels = counter_u64_alloc(M_WAITOK); 537 counter_u64_zero(extfree_refs); 538 counter_u64_zero(extfree_rels); 539 540 t4_init_shared_cpl_handlers(); 541 t4_register_cpl_handler(CPL_FW4_MSG, handle_fw_msg); 542 t4_register_cpl_handler(CPL_FW6_MSG, handle_fw_msg); 543 t4_register_cpl_handler(CPL_SGE_EGR_UPDATE, handle_sge_egr_update); 544 t4_register_cpl_handler(CPL_RX_PKT, t4_eth_rx); 545 #ifdef RATELIMIT 546 t4_register_shared_cpl_handler(CPL_FW4_ACK, ethofld_fw4_ack, 547 CPL_COOKIE_ETHOFLD); 548 #endif 549 t4_register_fw_msg_handler(FW6_TYPE_CMD_RPL, t4_handle_fw_rpl); 550 t4_register_fw_msg_handler(FW6_TYPE_WRERR_RPL, t4_handle_wrerr_rpl); 551 } 552 553 void 554 t4_sge_modunload(void) 555 { 556 557 counter_u64_free(extfree_refs); 558 counter_u64_free(extfree_rels); 559 } 560 561 uint64_t 562 t4_sge_extfree_refs(void) 563 { 564 uint64_t refs, rels; 565 566 rels = counter_u64_fetch(extfree_rels); 567 refs = counter_u64_fetch(extfree_refs); 568 569 return (refs - rels); 570 } 571 572 static inline void 573 setup_pad_and_pack_boundaries(struct adapter *sc) 574 { 575 uint32_t v, m; 576 int pad, pack, pad_shift; 577 578 pad_shift = chip_id(sc) > CHELSIO_T5 ? X_T6_INGPADBOUNDARY_SHIFT : 579 X_INGPADBOUNDARY_SHIFT; 580 pad = fl_pad; 581 if (fl_pad < (1 << pad_shift) || 582 fl_pad > (1 << (pad_shift + M_INGPADBOUNDARY)) || 583 !powerof2(fl_pad)) { 584 /* 585 * If there is any chance that we might use buffer packing and 586 * the chip is a T4, then pick 64 as the pad/pack boundary. Set 587 * it to the minimum allowed in all other cases. 588 */ 589 pad = is_t4(sc) && buffer_packing ? 64 : 1 << pad_shift; 590 591 /* 592 * For fl_pad = 0 we'll still write a reasonable value to the 593 * register but all the freelists will opt out of padding. 594 * We'll complain here only if the user tried to set it to a 595 * value greater than 0 that was invalid. 596 */ 597 if (fl_pad > 0) { 598 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pad value" 599 " (%d), using %d instead.\n", fl_pad, pad); 600 } 601 } 602 m = V_INGPADBOUNDARY(M_INGPADBOUNDARY); 603 v = V_INGPADBOUNDARY(ilog2(pad) - pad_shift); 604 t4_set_reg_field(sc, A_SGE_CONTROL, m, v); 605 606 if (is_t4(sc)) { 607 if (fl_pack != -1 && fl_pack != pad) { 608 /* Complain but carry on. */ 609 device_printf(sc->dev, "hw.cxgbe.fl_pack (%d) ignored," 610 " using %d instead.\n", fl_pack, pad); 611 } 612 return; 613 } 614 615 pack = fl_pack; 616 if (fl_pack < 16 || fl_pack == 32 || fl_pack > 4096 || 617 !powerof2(fl_pack)) { 618 pack = max(sc->params.pci.mps, CACHE_LINE_SIZE); 619 MPASS(powerof2(pack)); 620 if (pack < 16) 621 pack = 16; 622 if (pack == 32) 623 pack = 64; 624 if (pack > 4096) 625 pack = 4096; 626 if (fl_pack != -1) { 627 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pack value" 628 " (%d), using %d instead.\n", fl_pack, pack); 629 } 630 } 631 m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY); 632 if (pack == 16) 633 v = V_INGPACKBOUNDARY(0); 634 else 635 v = V_INGPACKBOUNDARY(ilog2(pack) - 5); 636 637 MPASS(!is_t4(sc)); /* T4 doesn't have SGE_CONTROL2 */ 638 t4_set_reg_field(sc, A_SGE_CONTROL2, m, v); 639 } 640 641 /* 642 * adap->params.vpd.cclk must be set up before this is called. 643 */ 644 void 645 t4_tweak_chip_settings(struct adapter *sc) 646 { 647 int i; 648 uint32_t v, m; 649 int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200}; 650 int timer_max = M_TIMERVALUE0 * 1000 / sc->params.vpd.cclk; 651 int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */ 652 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 653 static int sge_flbuf_sizes[] = { 654 MCLBYTES, 655 #if MJUMPAGESIZE != MCLBYTES 656 MJUMPAGESIZE, 657 MJUMPAGESIZE - CL_METADATA_SIZE, 658 MJUMPAGESIZE - 2 * MSIZE - CL_METADATA_SIZE, 659 #endif 660 MJUM9BYTES, 661 MJUM16BYTES, 662 MCLBYTES - MSIZE - CL_METADATA_SIZE, 663 MJUM9BYTES - CL_METADATA_SIZE, 664 MJUM16BYTES - CL_METADATA_SIZE, 665 }; 666 667 KASSERT(sc->flags & MASTER_PF, 668 ("%s: trying to change chip settings when not master.", __func__)); 669 670 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE; 671 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE | 672 V_EGRSTATUSPAGESIZE(spg_len == 128); 673 t4_set_reg_field(sc, A_SGE_CONTROL, m, v); 674 675 setup_pad_and_pack_boundaries(sc); 676 677 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) | 678 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) | 679 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) | 680 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) | 681 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) | 682 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) | 683 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) | 684 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10); 685 t4_write_reg(sc, A_SGE_HOST_PAGE_SIZE, v); 686 687 KASSERT(nitems(sge_flbuf_sizes) <= SGE_FLBUF_SIZES, 688 ("%s: hw buffer size table too big", __func__)); 689 for (i = 0; i < min(nitems(sge_flbuf_sizes), SGE_FLBUF_SIZES); i++) { 690 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0 + (4 * i), 691 sge_flbuf_sizes[i]); 692 } 693 694 v = V_THRESHOLD_0(intr_pktcount[0]) | V_THRESHOLD_1(intr_pktcount[1]) | 695 V_THRESHOLD_2(intr_pktcount[2]) | V_THRESHOLD_3(intr_pktcount[3]); 696 t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD, v); 697 698 KASSERT(intr_timer[0] <= timer_max, 699 ("%s: not a single usable timer (%d, %d)", __func__, intr_timer[0], 700 timer_max)); 701 for (i = 1; i < nitems(intr_timer); i++) { 702 KASSERT(intr_timer[i] >= intr_timer[i - 1], 703 ("%s: timers not listed in increasing order (%d)", 704 __func__, i)); 705 706 while (intr_timer[i] > timer_max) { 707 if (i == nitems(intr_timer) - 1) { 708 intr_timer[i] = timer_max; 709 break; 710 } 711 intr_timer[i] += intr_timer[i - 1]; 712 intr_timer[i] /= 2; 713 } 714 } 715 716 v = V_TIMERVALUE0(us_to_core_ticks(sc, intr_timer[0])) | 717 V_TIMERVALUE1(us_to_core_ticks(sc, intr_timer[1])); 718 t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1, v); 719 v = V_TIMERVALUE2(us_to_core_ticks(sc, intr_timer[2])) | 720 V_TIMERVALUE3(us_to_core_ticks(sc, intr_timer[3])); 721 t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3, v); 722 v = V_TIMERVALUE4(us_to_core_ticks(sc, intr_timer[4])) | 723 V_TIMERVALUE5(us_to_core_ticks(sc, intr_timer[5])); 724 t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5, v); 725 726 if (chip_id(sc) >= CHELSIO_T6) { 727 m = V_TSCALE(M_TSCALE); 728 if (tscale == 1) 729 v = 0; 730 else 731 v = V_TSCALE(tscale - 2); 732 t4_set_reg_field(sc, A_SGE_ITP_CONTROL, m, v); 733 734 if (sc->debug_flags & DF_DISABLE_TCB_CACHE) { 735 m = V_RDTHRESHOLD(M_RDTHRESHOLD) | F_WRTHRTHRESHEN | 736 V_WRTHRTHRESH(M_WRTHRTHRESH); 737 t4_tp_pio_read(sc, &v, 1, A_TP_CMM_CONFIG, 1); 738 v &= ~m; 739 v |= V_RDTHRESHOLD(1) | F_WRTHRTHRESHEN | 740 V_WRTHRTHRESH(16); 741 t4_tp_pio_write(sc, &v, 1, A_TP_CMM_CONFIG, 1); 742 } 743 } 744 745 /* 4K, 16K, 64K, 256K DDP "page sizes" for TDDP */ 746 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 747 t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, v); 748 749 /* 750 * 4K, 8K, 16K, 64K DDP "page sizes" for iSCSI DDP. These have been 751 * chosen with MAXPHYS = 128K in mind. The largest DDP buffer that we 752 * may have to deal with is MAXPHYS + 1 page. 753 */ 754 v = V_HPZ0(0) | V_HPZ1(1) | V_HPZ2(2) | V_HPZ3(4); 755 t4_write_reg(sc, A_ULP_RX_ISCSI_PSZ, v); 756 757 /* We use multiple DDP page sizes both in plain-TOE and ISCSI modes. */ 758 m = v = F_TDDPTAGTCB | F_ISCSITAGTCB; 759 t4_set_reg_field(sc, A_ULP_RX_CTL, m, v); 760 761 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 762 F_RESETDDPOFFSET; 763 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 764 t4_set_reg_field(sc, A_TP_PARA_REG5, m, v); 765 } 766 767 /* 768 * SGE wants the buffer to be at least 64B and then a multiple of 16. If 769 * padding is in use, the buffer's start and end need to be aligned to the pad 770 * boundary as well. We'll just make sure that the size is a multiple of the 771 * boundary here, it is up to the buffer allocation code to make sure the start 772 * of the buffer is aligned as well. 773 */ 774 static inline int 775 hwsz_ok(struct adapter *sc, int hwsz) 776 { 777 int mask = fl_pad ? sc->params.sge.pad_boundary - 1 : 16 - 1; 778 779 return (hwsz >= 64 && (hwsz & mask) == 0); 780 } 781 782 /* 783 * XXX: driver really should be able to deal with unexpected settings. 784 */ 785 int 786 t4_read_chip_settings(struct adapter *sc) 787 { 788 struct sge *s = &sc->sge; 789 struct sge_params *sp = &sc->params.sge; 790 int i, j, n, rc = 0; 791 uint32_t m, v, r; 792 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 793 static int sw_buf_sizes[] = { /* Sorted by size */ 794 MCLBYTES, 795 #if MJUMPAGESIZE != MCLBYTES 796 MJUMPAGESIZE, 797 #endif 798 MJUM9BYTES, 799 MJUM16BYTES 800 }; 801 struct sw_zone_info *swz, *safe_swz; 802 struct hw_buf_info *hwb; 803 804 m = F_RXPKTCPLMODE; 805 v = F_RXPKTCPLMODE; 806 r = sc->params.sge.sge_control; 807 if ((r & m) != v) { 808 device_printf(sc->dev, "invalid SGE_CONTROL(0x%x)\n", r); 809 rc = EINVAL; 810 } 811 812 /* 813 * If this changes then every single use of PAGE_SHIFT in the driver 814 * needs to be carefully reviewed for PAGE_SHIFT vs sp->page_shift. 815 */ 816 if (sp->page_shift != PAGE_SHIFT) { 817 device_printf(sc->dev, "invalid SGE_HOST_PAGE_SIZE(0x%x)\n", r); 818 rc = EINVAL; 819 } 820 821 /* Filter out unusable hw buffer sizes entirely (mark with -2). */ 822 hwb = &s->hw_buf_info[0]; 823 for (i = 0; i < nitems(s->hw_buf_info); i++, hwb++) { 824 r = sc->params.sge.sge_fl_buffer_size[i]; 825 hwb->size = r; 826 hwb->zidx = hwsz_ok(sc, r) ? -1 : -2; 827 hwb->next = -1; 828 } 829 830 /* 831 * Create a sorted list in decreasing order of hw buffer sizes (and so 832 * increasing order of spare area) for each software zone. 833 * 834 * If padding is enabled then the start and end of the buffer must align 835 * to the pad boundary; if packing is enabled then they must align with 836 * the pack boundary as well. Allocations from the cluster zones are 837 * aligned to min(size, 4K), so the buffer starts at that alignment and 838 * ends at hwb->size alignment. If mbuf inlining is allowed the 839 * starting alignment will be reduced to MSIZE and the driver will 840 * exercise appropriate caution when deciding on the best buffer layout 841 * to use. 842 */ 843 n = 0; /* no usable buffer size to begin with */ 844 swz = &s->sw_zone_info[0]; 845 safe_swz = NULL; 846 for (i = 0; i < SW_ZONE_SIZES; i++, swz++) { 847 int8_t head = -1, tail = -1; 848 849 swz->size = sw_buf_sizes[i]; 850 swz->zone = m_getzone(swz->size); 851 swz->type = m_gettype(swz->size); 852 853 if (swz->size < PAGE_SIZE) { 854 MPASS(powerof2(swz->size)); 855 if (fl_pad && (swz->size % sp->pad_boundary != 0)) 856 continue; 857 } 858 859 if (swz->size == safest_rx_cluster) 860 safe_swz = swz; 861 862 hwb = &s->hw_buf_info[0]; 863 for (j = 0; j < SGE_FLBUF_SIZES; j++, hwb++) { 864 if (hwb->zidx != -1 || hwb->size > swz->size) 865 continue; 866 #ifdef INVARIANTS 867 if (fl_pad) 868 MPASS(hwb->size % sp->pad_boundary == 0); 869 #endif 870 hwb->zidx = i; 871 if (head == -1) 872 head = tail = j; 873 else if (hwb->size < s->hw_buf_info[tail].size) { 874 s->hw_buf_info[tail].next = j; 875 tail = j; 876 } else { 877 int8_t *cur; 878 struct hw_buf_info *t; 879 880 for (cur = &head; *cur != -1; cur = &t->next) { 881 t = &s->hw_buf_info[*cur]; 882 if (hwb->size == t->size) { 883 hwb->zidx = -2; 884 break; 885 } 886 if (hwb->size > t->size) { 887 hwb->next = *cur; 888 *cur = j; 889 break; 890 } 891 } 892 } 893 } 894 swz->head_hwidx = head; 895 swz->tail_hwidx = tail; 896 897 if (tail != -1) { 898 n++; 899 if (swz->size - s->hw_buf_info[tail].size >= 900 CL_METADATA_SIZE) 901 sc->flags |= BUF_PACKING_OK; 902 } 903 } 904 if (n == 0) { 905 device_printf(sc->dev, "no usable SGE FL buffer size.\n"); 906 rc = EINVAL; 907 } 908 909 s->safe_hwidx1 = -1; 910 s->safe_hwidx2 = -1; 911 if (safe_swz != NULL) { 912 s->safe_hwidx1 = safe_swz->head_hwidx; 913 for (i = safe_swz->head_hwidx; i != -1; i = hwb->next) { 914 int spare; 915 916 hwb = &s->hw_buf_info[i]; 917 #ifdef INVARIANTS 918 if (fl_pad) 919 MPASS(hwb->size % sp->pad_boundary == 0); 920 #endif 921 spare = safe_swz->size - hwb->size; 922 if (spare >= CL_METADATA_SIZE) { 923 s->safe_hwidx2 = i; 924 break; 925 } 926 } 927 } 928 929 if (sc->flags & IS_VF) 930 return (0); 931 932 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 933 r = t4_read_reg(sc, A_ULP_RX_TDDP_PSZ); 934 if (r != v) { 935 device_printf(sc->dev, "invalid ULP_RX_TDDP_PSZ(0x%x)\n", r); 936 rc = EINVAL; 937 } 938 939 m = v = F_TDDPTAGTCB; 940 r = t4_read_reg(sc, A_ULP_RX_CTL); 941 if ((r & m) != v) { 942 device_printf(sc->dev, "invalid ULP_RX_CTL(0x%x)\n", r); 943 rc = EINVAL; 944 } 945 946 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 947 F_RESETDDPOFFSET; 948 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 949 r = t4_read_reg(sc, A_TP_PARA_REG5); 950 if ((r & m) != v) { 951 device_printf(sc->dev, "invalid TP_PARA_REG5(0x%x)\n", r); 952 rc = EINVAL; 953 } 954 955 t4_init_tp_params(sc, 1); 956 957 t4_read_mtu_tbl(sc, sc->params.mtus, NULL); 958 t4_load_mtus(sc, sc->params.mtus, sc->params.a_wnd, sc->params.b_wnd); 959 960 return (rc); 961 } 962 963 int 964 t4_create_dma_tag(struct adapter *sc) 965 { 966 int rc; 967 968 rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0, 969 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE, 970 BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL, 971 NULL, &sc->dmat); 972 if (rc != 0) { 973 device_printf(sc->dev, 974 "failed to create main DMA tag: %d\n", rc); 975 } 976 977 return (rc); 978 } 979 980 void 981 t4_sge_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx, 982 struct sysctl_oid_list *children) 983 { 984 struct sge_params *sp = &sc->params.sge; 985 986 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "buffer_sizes", 987 CTLTYPE_STRING | CTLFLAG_RD, &sc->sge, 0, sysctl_bufsizes, "A", 988 "freelist buffer sizes"); 989 990 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pktshift", CTLFLAG_RD, 991 NULL, sp->fl_pktshift, "payload DMA offset in rx buffer (bytes)"); 992 993 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pad", CTLFLAG_RD, 994 NULL, sp->pad_boundary, "payload pad boundary (bytes)"); 995 996 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "spg_len", CTLFLAG_RD, 997 NULL, sp->spg_len, "status page size (bytes)"); 998 999 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_drop", CTLFLAG_RD, 1000 NULL, cong_drop, "congestion drop setting"); 1001 1002 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pack", CTLFLAG_RD, 1003 NULL, sp->pack_boundary, "payload pack boundary (bytes)"); 1004 } 1005 1006 int 1007 t4_destroy_dma_tag(struct adapter *sc) 1008 { 1009 if (sc->dmat) 1010 bus_dma_tag_destroy(sc->dmat); 1011 1012 return (0); 1013 } 1014 1015 /* 1016 * Allocate and initialize the firmware event queue, control queues, and special 1017 * purpose rx queues owned by the adapter. 1018 * 1019 * Returns errno on failure. Resources allocated up to that point may still be 1020 * allocated. Caller is responsible for cleanup in case this function fails. 1021 */ 1022 int 1023 t4_setup_adapter_queues(struct adapter *sc) 1024 { 1025 struct sysctl_oid *oid; 1026 struct sysctl_oid_list *children; 1027 int rc, i; 1028 1029 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 1030 1031 sysctl_ctx_init(&sc->ctx); 1032 sc->flags |= ADAP_SYSCTL_CTX; 1033 1034 /* 1035 * Firmware event queue 1036 */ 1037 rc = alloc_fwq(sc); 1038 if (rc != 0) 1039 return (rc); 1040 1041 /* 1042 * That's all for the VF driver. 1043 */ 1044 if (sc->flags & IS_VF) 1045 return (rc); 1046 1047 oid = device_get_sysctl_tree(sc->dev); 1048 children = SYSCTL_CHILDREN(oid); 1049 1050 /* 1051 * XXX: General purpose rx queues, one per port. 1052 */ 1053 1054 /* 1055 * Control queues, one per port. 1056 */ 1057 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "ctrlq", 1058 CTLFLAG_RD, NULL, "control queues"); 1059 for_each_port(sc, i) { 1060 struct sge_wrq *ctrlq = &sc->sge.ctrlq[i]; 1061 1062 rc = alloc_ctrlq(sc, ctrlq, i, oid); 1063 if (rc != 0) 1064 return (rc); 1065 } 1066 1067 return (rc); 1068 } 1069 1070 /* 1071 * Idempotent 1072 */ 1073 int 1074 t4_teardown_adapter_queues(struct adapter *sc) 1075 { 1076 int i; 1077 1078 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 1079 1080 /* Do this before freeing the queue */ 1081 if (sc->flags & ADAP_SYSCTL_CTX) { 1082 sysctl_ctx_free(&sc->ctx); 1083 sc->flags &= ~ADAP_SYSCTL_CTX; 1084 } 1085 1086 if (!(sc->flags & IS_VF)) { 1087 for_each_port(sc, i) 1088 free_wrq(sc, &sc->sge.ctrlq[i]); 1089 } 1090 free_fwq(sc); 1091 1092 return (0); 1093 } 1094 1095 /* Maximum payload that can be delivered with a single iq descriptor */ 1096 static inline int 1097 mtu_to_max_payload(struct adapter *sc, int mtu, const int toe) 1098 { 1099 int payload; 1100 1101 #ifdef TCP_OFFLOAD 1102 if (toe) { 1103 int rxcs = G_RXCOALESCESIZE(t4_read_reg(sc, A_TP_PARA_REG2)); 1104 1105 /* Note that COP can set rx_coalesce on/off per connection. */ 1106 payload = max(mtu, rxcs); 1107 } else { 1108 #endif 1109 /* large enough even when hw VLAN extraction is disabled */ 1110 payload = sc->params.sge.fl_pktshift + ETHER_HDR_LEN + 1111 ETHER_VLAN_ENCAP_LEN + mtu; 1112 #ifdef TCP_OFFLOAD 1113 } 1114 #endif 1115 1116 return (payload); 1117 } 1118 1119 int 1120 t4_setup_vi_queues(struct vi_info *vi) 1121 { 1122 int rc = 0, i, intr_idx, iqidx; 1123 struct sge_rxq *rxq; 1124 struct sge_txq *txq; 1125 #ifdef TCP_OFFLOAD 1126 struct sge_ofld_rxq *ofld_rxq; 1127 #endif 1128 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1129 struct sge_wrq *ofld_txq; 1130 #endif 1131 #ifdef DEV_NETMAP 1132 int saved_idx; 1133 struct sge_nm_rxq *nm_rxq; 1134 struct sge_nm_txq *nm_txq; 1135 #endif 1136 char name[16]; 1137 struct port_info *pi = vi->pi; 1138 struct adapter *sc = pi->adapter; 1139 struct ifnet *ifp = vi->ifp; 1140 struct sysctl_oid *oid = device_get_sysctl_tree(vi->dev); 1141 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 1142 int maxp, mtu = ifp->if_mtu; 1143 1144 /* Interrupt vector to start from (when using multiple vectors) */ 1145 intr_idx = vi->first_intr; 1146 1147 #ifdef DEV_NETMAP 1148 saved_idx = intr_idx; 1149 if (ifp->if_capabilities & IFCAP_NETMAP) { 1150 1151 /* netmap is supported with direct interrupts only. */ 1152 MPASS(!forwarding_intr_to_fwq(sc)); 1153 1154 /* 1155 * We don't have buffers to back the netmap rx queues 1156 * right now so we create the queues in a way that 1157 * doesn't set off any congestion signal in the chip. 1158 */ 1159 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "nm_rxq", 1160 CTLFLAG_RD, NULL, "rx queues"); 1161 for_each_nm_rxq(vi, i, nm_rxq) { 1162 rc = alloc_nm_rxq(vi, nm_rxq, intr_idx, i, oid); 1163 if (rc != 0) 1164 goto done; 1165 intr_idx++; 1166 } 1167 1168 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "nm_txq", 1169 CTLFLAG_RD, NULL, "tx queues"); 1170 for_each_nm_txq(vi, i, nm_txq) { 1171 iqidx = vi->first_nm_rxq + (i % vi->nnmrxq); 1172 rc = alloc_nm_txq(vi, nm_txq, iqidx, i, oid); 1173 if (rc != 0) 1174 goto done; 1175 } 1176 } 1177 1178 /* Normal rx queues and netmap rx queues share the same interrupts. */ 1179 intr_idx = saved_idx; 1180 #endif 1181 1182 /* 1183 * Allocate rx queues first because a default iqid is required when 1184 * creating a tx queue. 1185 */ 1186 maxp = mtu_to_max_payload(sc, mtu, 0); 1187 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "rxq", 1188 CTLFLAG_RD, NULL, "rx queues"); 1189 for_each_rxq(vi, i, rxq) { 1190 1191 init_iq(&rxq->iq, sc, vi->tmr_idx, vi->pktc_idx, vi->qsize_rxq); 1192 1193 snprintf(name, sizeof(name), "%s rxq%d-fl", 1194 device_get_nameunit(vi->dev), i); 1195 init_fl(sc, &rxq->fl, vi->qsize_rxq / 8, maxp, name); 1196 1197 rc = alloc_rxq(vi, rxq, 1198 forwarding_intr_to_fwq(sc) ? -1 : intr_idx, i, oid); 1199 if (rc != 0) 1200 goto done; 1201 intr_idx++; 1202 } 1203 #ifdef DEV_NETMAP 1204 if (ifp->if_capabilities & IFCAP_NETMAP) 1205 intr_idx = saved_idx + max(vi->nrxq, vi->nnmrxq); 1206 #endif 1207 #ifdef TCP_OFFLOAD 1208 maxp = mtu_to_max_payload(sc, mtu, 1); 1209 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_rxq", 1210 CTLFLAG_RD, NULL, "rx queues for offloaded TCP connections"); 1211 for_each_ofld_rxq(vi, i, ofld_rxq) { 1212 1213 init_iq(&ofld_rxq->iq, sc, vi->ofld_tmr_idx, vi->ofld_pktc_idx, 1214 vi->qsize_rxq); 1215 1216 snprintf(name, sizeof(name), "%s ofld_rxq%d-fl", 1217 device_get_nameunit(vi->dev), i); 1218 init_fl(sc, &ofld_rxq->fl, vi->qsize_rxq / 8, maxp, name); 1219 1220 rc = alloc_ofld_rxq(vi, ofld_rxq, 1221 forwarding_intr_to_fwq(sc) ? -1 : intr_idx, i, oid); 1222 if (rc != 0) 1223 goto done; 1224 intr_idx++; 1225 } 1226 #endif 1227 1228 /* 1229 * Now the tx queues. 1230 */ 1231 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "txq", CTLFLAG_RD, 1232 NULL, "tx queues"); 1233 for_each_txq(vi, i, txq) { 1234 iqidx = vi->first_rxq + (i % vi->nrxq); 1235 snprintf(name, sizeof(name), "%s txq%d", 1236 device_get_nameunit(vi->dev), i); 1237 init_eq(sc, &txq->eq, EQ_ETH, vi->qsize_txq, pi->tx_chan, 1238 sc->sge.rxq[iqidx].iq.cntxt_id, name); 1239 1240 rc = alloc_txq(vi, txq, i, oid); 1241 if (rc != 0) 1242 goto done; 1243 } 1244 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1245 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_txq", 1246 CTLFLAG_RD, NULL, "tx queues for TOE/ETHOFLD"); 1247 for_each_ofld_txq(vi, i, ofld_txq) { 1248 struct sysctl_oid *oid2; 1249 1250 snprintf(name, sizeof(name), "%s ofld_txq%d", 1251 device_get_nameunit(vi->dev), i); 1252 if (vi->nofldrxq > 0) { 1253 iqidx = vi->first_ofld_rxq + (i % vi->nofldrxq); 1254 init_eq(sc, &ofld_txq->eq, EQ_OFLD, vi->qsize_txq, 1255 pi->tx_chan, sc->sge.ofld_rxq[iqidx].iq.cntxt_id, 1256 name); 1257 } else { 1258 iqidx = vi->first_rxq + (i % vi->nrxq); 1259 init_eq(sc, &ofld_txq->eq, EQ_OFLD, vi->qsize_txq, 1260 pi->tx_chan, sc->sge.rxq[iqidx].iq.cntxt_id, name); 1261 } 1262 1263 snprintf(name, sizeof(name), "%d", i); 1264 oid2 = SYSCTL_ADD_NODE(&vi->ctx, SYSCTL_CHILDREN(oid), OID_AUTO, 1265 name, CTLFLAG_RD, NULL, "offload tx queue"); 1266 1267 rc = alloc_wrq(sc, vi, ofld_txq, oid2); 1268 if (rc != 0) 1269 goto done; 1270 } 1271 #endif 1272 done: 1273 if (rc) 1274 t4_teardown_vi_queues(vi); 1275 1276 return (rc); 1277 } 1278 1279 /* 1280 * Idempotent 1281 */ 1282 int 1283 t4_teardown_vi_queues(struct vi_info *vi) 1284 { 1285 int i; 1286 struct sge_rxq *rxq; 1287 struct sge_txq *txq; 1288 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1289 struct port_info *pi = vi->pi; 1290 struct adapter *sc = pi->adapter; 1291 struct sge_wrq *ofld_txq; 1292 #endif 1293 #ifdef TCP_OFFLOAD 1294 struct sge_ofld_rxq *ofld_rxq; 1295 #endif 1296 #ifdef DEV_NETMAP 1297 struct sge_nm_rxq *nm_rxq; 1298 struct sge_nm_txq *nm_txq; 1299 #endif 1300 1301 /* Do this before freeing the queues */ 1302 if (vi->flags & VI_SYSCTL_CTX) { 1303 sysctl_ctx_free(&vi->ctx); 1304 vi->flags &= ~VI_SYSCTL_CTX; 1305 } 1306 1307 #ifdef DEV_NETMAP 1308 if (vi->ifp->if_capabilities & IFCAP_NETMAP) { 1309 for_each_nm_txq(vi, i, nm_txq) { 1310 free_nm_txq(vi, nm_txq); 1311 } 1312 1313 for_each_nm_rxq(vi, i, nm_rxq) { 1314 free_nm_rxq(vi, nm_rxq); 1315 } 1316 } 1317 #endif 1318 1319 /* 1320 * Take down all the tx queues first, as they reference the rx queues 1321 * (for egress updates, etc.). 1322 */ 1323 1324 for_each_txq(vi, i, txq) { 1325 free_txq(vi, txq); 1326 } 1327 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1328 for_each_ofld_txq(vi, i, ofld_txq) { 1329 free_wrq(sc, ofld_txq); 1330 } 1331 #endif 1332 1333 /* 1334 * Then take down the rx queues. 1335 */ 1336 1337 for_each_rxq(vi, i, rxq) { 1338 free_rxq(vi, rxq); 1339 } 1340 #ifdef TCP_OFFLOAD 1341 for_each_ofld_rxq(vi, i, ofld_rxq) { 1342 free_ofld_rxq(vi, ofld_rxq); 1343 } 1344 #endif 1345 1346 return (0); 1347 } 1348 1349 /* 1350 * Interrupt handler when the driver is using only 1 interrupt. This is a very 1351 * unusual scenario. 1352 * 1353 * a) Deals with errors, if any. 1354 * b) Services firmware event queue, which is taking interrupts for all other 1355 * queues. 1356 */ 1357 void 1358 t4_intr_all(void *arg) 1359 { 1360 struct adapter *sc = arg; 1361 struct sge_iq *fwq = &sc->sge.fwq; 1362 1363 MPASS(sc->intr_count == 1); 1364 1365 t4_intr_err(arg); 1366 t4_intr_evt(fwq); 1367 } 1368 1369 /* 1370 * Interrupt handler for errors (installed directly when multiple interrupts are 1371 * being used, or called by t4_intr_all). 1372 */ 1373 void 1374 t4_intr_err(void *arg) 1375 { 1376 struct adapter *sc = arg; 1377 1378 t4_write_reg(sc, MYPF_REG(A_PCIE_PF_CLI), 0); 1379 t4_slow_intr_handler(sc); 1380 } 1381 1382 /* 1383 * Interrupt handler for iq-only queues. The firmware event queue is the only 1384 * such queue right now. 1385 */ 1386 void 1387 t4_intr_evt(void *arg) 1388 { 1389 struct sge_iq *iq = arg; 1390 1391 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 1392 service_iq(iq, 0); 1393 (void) atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 1394 } 1395 } 1396 1397 /* 1398 * Interrupt handler for iq+fl queues. 1399 */ 1400 void 1401 t4_intr(void *arg) 1402 { 1403 struct sge_iq *iq = arg; 1404 1405 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 1406 service_iq_fl(iq, 0); 1407 (void) atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 1408 } 1409 } 1410 1411 #ifdef DEV_NETMAP 1412 /* 1413 * Interrupt handler for netmap rx queues. 1414 */ 1415 void 1416 t4_nm_intr(void *arg) 1417 { 1418 struct sge_nm_rxq *nm_rxq = arg; 1419 1420 if (atomic_cmpset_int(&nm_rxq->nm_state, NM_ON, NM_BUSY)) { 1421 service_nm_rxq(nm_rxq); 1422 (void) atomic_cmpset_int(&nm_rxq->nm_state, NM_BUSY, NM_ON); 1423 } 1424 } 1425 1426 /* 1427 * Interrupt handler for vectors shared between NIC and netmap rx queues. 1428 */ 1429 void 1430 t4_vi_intr(void *arg) 1431 { 1432 struct irq *irq = arg; 1433 1434 MPASS(irq->nm_rxq != NULL); 1435 t4_nm_intr(irq->nm_rxq); 1436 1437 MPASS(irq->rxq != NULL); 1438 t4_intr(irq->rxq); 1439 } 1440 #endif 1441 1442 /* 1443 * Deals with interrupts on an iq-only (no freelist) queue. 1444 */ 1445 static int 1446 service_iq(struct sge_iq *iq, int budget) 1447 { 1448 struct sge_iq *q; 1449 struct adapter *sc = iq->adapter; 1450 struct iq_desc *d = &iq->desc[iq->cidx]; 1451 int ndescs = 0, limit; 1452 int rsp_type; 1453 uint32_t lq; 1454 STAILQ_HEAD(, sge_iq) iql = STAILQ_HEAD_INITIALIZER(iql); 1455 1456 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq)); 1457 KASSERT((iq->flags & IQ_HAS_FL) == 0, 1458 ("%s: called for iq %p with fl (iq->flags 0x%x)", __func__, iq, 1459 iq->flags)); 1460 MPASS((iq->flags & IQ_ADJ_CREDIT) == 0); 1461 MPASS((iq->flags & IQ_LRO_ENABLED) == 0); 1462 1463 limit = budget ? budget : iq->qsize / 16; 1464 1465 /* 1466 * We always come back and check the descriptor ring for new indirect 1467 * interrupts and other responses after running a single handler. 1468 */ 1469 for (;;) { 1470 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) { 1471 1472 rmb(); 1473 1474 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen); 1475 lq = be32toh(d->rsp.pldbuflen_qid); 1476 1477 switch (rsp_type) { 1478 case X_RSPD_TYPE_FLBUF: 1479 panic("%s: data for an iq (%p) with no freelist", 1480 __func__, iq); 1481 1482 /* NOTREACHED */ 1483 1484 case X_RSPD_TYPE_CPL: 1485 KASSERT(d->rss.opcode < NUM_CPL_CMDS, 1486 ("%s: bad opcode %02x.", __func__, 1487 d->rss.opcode)); 1488 t4_cpl_handler[d->rss.opcode](iq, &d->rss, NULL); 1489 break; 1490 1491 case X_RSPD_TYPE_INTR: 1492 /* 1493 * There are 1K interrupt-capable queues (qids 0 1494 * through 1023). A response type indicating a 1495 * forwarded interrupt with a qid >= 1K is an 1496 * iWARP async notification. 1497 */ 1498 if (__predict_true(lq >= 1024)) { 1499 t4_an_handler(iq, &d->rsp); 1500 break; 1501 } 1502 1503 q = sc->sge.iqmap[lq - sc->sge.iq_start - 1504 sc->sge.iq_base]; 1505 if (atomic_cmpset_int(&q->state, IQS_IDLE, 1506 IQS_BUSY)) { 1507 if (service_iq_fl(q, q->qsize / 16) == 0) { 1508 (void) atomic_cmpset_int(&q->state, 1509 IQS_BUSY, IQS_IDLE); 1510 } else { 1511 STAILQ_INSERT_TAIL(&iql, q, 1512 link); 1513 } 1514 } 1515 break; 1516 1517 default: 1518 KASSERT(0, 1519 ("%s: illegal response type %d on iq %p", 1520 __func__, rsp_type, iq)); 1521 log(LOG_ERR, 1522 "%s: illegal response type %d on iq %p", 1523 device_get_nameunit(sc->dev), rsp_type, iq); 1524 break; 1525 } 1526 1527 d++; 1528 if (__predict_false(++iq->cidx == iq->sidx)) { 1529 iq->cidx = 0; 1530 iq->gen ^= F_RSPD_GEN; 1531 d = &iq->desc[0]; 1532 } 1533 if (__predict_false(++ndescs == limit)) { 1534 t4_write_reg(sc, sc->sge_gts_reg, 1535 V_CIDXINC(ndescs) | 1536 V_INGRESSQID(iq->cntxt_id) | 1537 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); 1538 ndescs = 0; 1539 1540 if (budget) { 1541 return (EINPROGRESS); 1542 } 1543 } 1544 } 1545 1546 if (STAILQ_EMPTY(&iql)) 1547 break; 1548 1549 /* 1550 * Process the head only, and send it to the back of the list if 1551 * it's still not done. 1552 */ 1553 q = STAILQ_FIRST(&iql); 1554 STAILQ_REMOVE_HEAD(&iql, link); 1555 if (service_iq_fl(q, q->qsize / 8) == 0) 1556 (void) atomic_cmpset_int(&q->state, IQS_BUSY, IQS_IDLE); 1557 else 1558 STAILQ_INSERT_TAIL(&iql, q, link); 1559 } 1560 1561 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) | 1562 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params)); 1563 1564 return (0); 1565 } 1566 1567 static inline int 1568 sort_before_lro(struct lro_ctrl *lro) 1569 { 1570 1571 return (lro->lro_mbuf_max != 0); 1572 } 1573 1574 static inline uint64_t 1575 last_flit_to_ns(struct adapter *sc, uint64_t lf) 1576 { 1577 uint64_t n = be64toh(lf) & 0xfffffffffffffff; /* 60b, not 64b. */ 1578 1579 if (n > UINT64_MAX / 1000000) 1580 return (n / sc->params.vpd.cclk * 1000000); 1581 else 1582 return (n * 1000000 / sc->params.vpd.cclk); 1583 } 1584 1585 /* 1586 * Deals with interrupts on an iq+fl queue. 1587 */ 1588 static int 1589 service_iq_fl(struct sge_iq *iq, int budget) 1590 { 1591 struct sge_rxq *rxq = iq_to_rxq(iq); 1592 struct sge_fl *fl; 1593 struct adapter *sc = iq->adapter; 1594 struct iq_desc *d = &iq->desc[iq->cidx]; 1595 int ndescs = 0, limit; 1596 int rsp_type, refill, starved; 1597 uint32_t lq; 1598 uint16_t fl_hw_cidx; 1599 struct mbuf *m0; 1600 #if defined(INET) || defined(INET6) 1601 const struct timeval lro_timeout = {0, sc->lro_timeout}; 1602 struct lro_ctrl *lro = &rxq->lro; 1603 #endif 1604 1605 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq)); 1606 MPASS(iq->flags & IQ_HAS_FL); 1607 1608 limit = budget ? budget : iq->qsize / 16; 1609 fl = &rxq->fl; 1610 fl_hw_cidx = fl->hw_cidx; /* stable snapshot */ 1611 1612 #if defined(INET) || defined(INET6) 1613 if (iq->flags & IQ_ADJ_CREDIT) { 1614 MPASS(sort_before_lro(lro)); 1615 iq->flags &= ~IQ_ADJ_CREDIT; 1616 if ((d->rsp.u.type_gen & F_RSPD_GEN) != iq->gen) { 1617 tcp_lro_flush_all(lro); 1618 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(1) | 1619 V_INGRESSQID((u32)iq->cntxt_id) | 1620 V_SEINTARM(iq->intr_params)); 1621 return (0); 1622 } 1623 ndescs = 1; 1624 } 1625 #else 1626 MPASS((iq->flags & IQ_ADJ_CREDIT) == 0); 1627 #endif 1628 1629 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) { 1630 1631 rmb(); 1632 1633 refill = 0; 1634 m0 = NULL; 1635 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen); 1636 lq = be32toh(d->rsp.pldbuflen_qid); 1637 1638 switch (rsp_type) { 1639 case X_RSPD_TYPE_FLBUF: 1640 1641 m0 = get_fl_payload(sc, fl, lq); 1642 if (__predict_false(m0 == NULL)) 1643 goto out; 1644 refill = IDXDIFF(fl->hw_cidx, fl_hw_cidx, fl->sidx) > 2; 1645 1646 if (iq->flags & IQ_RX_TIMESTAMP) { 1647 /* 1648 * Fill up rcv_tstmp but do not set M_TSTMP. 1649 * rcv_tstmp is not in the format that the 1650 * kernel expects and we don't want to mislead 1651 * it. For now this is only for custom code 1652 * that knows how to interpret cxgbe's stamp. 1653 */ 1654 m0->m_pkthdr.rcv_tstmp = 1655 last_flit_to_ns(sc, d->rsp.u.last_flit); 1656 #ifdef notyet 1657 m0->m_flags |= M_TSTMP; 1658 #endif 1659 } 1660 1661 /* fall through */ 1662 1663 case X_RSPD_TYPE_CPL: 1664 KASSERT(d->rss.opcode < NUM_CPL_CMDS, 1665 ("%s: bad opcode %02x.", __func__, d->rss.opcode)); 1666 t4_cpl_handler[d->rss.opcode](iq, &d->rss, m0); 1667 break; 1668 1669 case X_RSPD_TYPE_INTR: 1670 1671 /* 1672 * There are 1K interrupt-capable queues (qids 0 1673 * through 1023). A response type indicating a 1674 * forwarded interrupt with a qid >= 1K is an 1675 * iWARP async notification. That is the only 1676 * acceptable indirect interrupt on this queue. 1677 */ 1678 if (__predict_false(lq < 1024)) { 1679 panic("%s: indirect interrupt on iq_fl %p " 1680 "with qid %u", __func__, iq, lq); 1681 } 1682 1683 t4_an_handler(iq, &d->rsp); 1684 break; 1685 1686 default: 1687 KASSERT(0, ("%s: illegal response type %d on iq %p", 1688 __func__, rsp_type, iq)); 1689 log(LOG_ERR, "%s: illegal response type %d on iq %p", 1690 device_get_nameunit(sc->dev), rsp_type, iq); 1691 break; 1692 } 1693 1694 d++; 1695 if (__predict_false(++iq->cidx == iq->sidx)) { 1696 iq->cidx = 0; 1697 iq->gen ^= F_RSPD_GEN; 1698 d = &iq->desc[0]; 1699 } 1700 if (__predict_false(++ndescs == limit)) { 1701 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) | 1702 V_INGRESSQID(iq->cntxt_id) | 1703 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); 1704 ndescs = 0; 1705 1706 #if defined(INET) || defined(INET6) 1707 if (iq->flags & IQ_LRO_ENABLED && 1708 !sort_before_lro(lro) && 1709 sc->lro_timeout != 0) { 1710 tcp_lro_flush_inactive(lro, &lro_timeout); 1711 } 1712 #endif 1713 if (budget) { 1714 FL_LOCK(fl); 1715 refill_fl(sc, fl, 32); 1716 FL_UNLOCK(fl); 1717 1718 return (EINPROGRESS); 1719 } 1720 } 1721 if (refill) { 1722 FL_LOCK(fl); 1723 refill_fl(sc, fl, 32); 1724 FL_UNLOCK(fl); 1725 fl_hw_cidx = fl->hw_cidx; 1726 } 1727 } 1728 out: 1729 #if defined(INET) || defined(INET6) 1730 if (iq->flags & IQ_LRO_ENABLED) { 1731 if (ndescs > 0 && lro->lro_mbuf_count > 8) { 1732 MPASS(sort_before_lro(lro)); 1733 /* hold back one credit and don't flush LRO state */ 1734 iq->flags |= IQ_ADJ_CREDIT; 1735 ndescs--; 1736 } else { 1737 tcp_lro_flush_all(lro); 1738 } 1739 } 1740 #endif 1741 1742 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) | 1743 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params)); 1744 1745 FL_LOCK(fl); 1746 starved = refill_fl(sc, fl, 64); 1747 FL_UNLOCK(fl); 1748 if (__predict_false(starved != 0)) 1749 add_fl_to_sfl(sc, fl); 1750 1751 return (0); 1752 } 1753 1754 static inline int 1755 cl_has_metadata(struct sge_fl *fl, struct cluster_layout *cll) 1756 { 1757 int rc = fl->flags & FL_BUF_PACKING || cll->region1 > 0; 1758 1759 if (rc) 1760 MPASS(cll->region3 >= CL_METADATA_SIZE); 1761 1762 return (rc); 1763 } 1764 1765 static inline struct cluster_metadata * 1766 cl_metadata(struct adapter *sc, struct sge_fl *fl, struct cluster_layout *cll, 1767 caddr_t cl) 1768 { 1769 1770 if (cl_has_metadata(fl, cll)) { 1771 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx]; 1772 1773 return ((struct cluster_metadata *)(cl + swz->size) - 1); 1774 } 1775 return (NULL); 1776 } 1777 1778 static void 1779 rxb_free(struct mbuf *m) 1780 { 1781 uma_zone_t zone = m->m_ext.ext_arg1; 1782 void *cl = m->m_ext.ext_arg2; 1783 1784 uma_zfree(zone, cl); 1785 counter_u64_add(extfree_rels, 1); 1786 } 1787 1788 /* 1789 * The mbuf returned by this function could be allocated from zone_mbuf or 1790 * constructed in spare room in the cluster. 1791 * 1792 * The mbuf carries the payload in one of these ways 1793 * a) frame inside the mbuf (mbuf from zone_mbuf) 1794 * b) m_cljset (for clusters without metadata) zone_mbuf 1795 * c) m_extaddref (cluster with metadata) inline mbuf 1796 * d) m_extaddref (cluster with metadata) zone_mbuf 1797 */ 1798 static struct mbuf * 1799 get_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset, 1800 int remaining) 1801 { 1802 struct mbuf *m; 1803 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 1804 struct cluster_layout *cll = &sd->cll; 1805 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx]; 1806 struct hw_buf_info *hwb = &sc->sge.hw_buf_info[cll->hwidx]; 1807 struct cluster_metadata *clm = cl_metadata(sc, fl, cll, sd->cl); 1808 int len, blen; 1809 caddr_t payload; 1810 1811 blen = hwb->size - fl->rx_offset; /* max possible in this buf */ 1812 len = min(remaining, blen); 1813 payload = sd->cl + cll->region1 + fl->rx_offset; 1814 if (fl->flags & FL_BUF_PACKING) { 1815 const u_int l = fr_offset + len; 1816 const u_int pad = roundup2(l, fl->buf_boundary) - l; 1817 1818 if (fl->rx_offset + len + pad < hwb->size) 1819 blen = len + pad; 1820 MPASS(fl->rx_offset + blen <= hwb->size); 1821 } else { 1822 MPASS(fl->rx_offset == 0); /* not packing */ 1823 } 1824 1825 1826 if (sc->sc_do_rxcopy && len < RX_COPY_THRESHOLD) { 1827 1828 /* 1829 * Copy payload into a freshly allocated mbuf. 1830 */ 1831 1832 m = fr_offset == 0 ? 1833 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA); 1834 if (m == NULL) 1835 return (NULL); 1836 fl->mbuf_allocated++; 1837 1838 /* copy data to mbuf */ 1839 bcopy(payload, mtod(m, caddr_t), len); 1840 1841 } else if (sd->nmbuf * MSIZE < cll->region1) { 1842 1843 /* 1844 * There's spare room in the cluster for an mbuf. Create one 1845 * and associate it with the payload that's in the cluster. 1846 */ 1847 1848 MPASS(clm != NULL); 1849 m = (struct mbuf *)(sd->cl + sd->nmbuf * MSIZE); 1850 /* No bzero required */ 1851 if (m_init(m, M_NOWAIT, MT_DATA, 1852 fr_offset == 0 ? M_PKTHDR | M_NOFREE : M_NOFREE)) 1853 return (NULL); 1854 fl->mbuf_inlined++; 1855 m_extaddref(m, payload, blen, &clm->refcount, rxb_free, 1856 swz->zone, sd->cl); 1857 if (sd->nmbuf++ == 0) 1858 counter_u64_add(extfree_refs, 1); 1859 1860 } else { 1861 1862 /* 1863 * Grab an mbuf from zone_mbuf and associate it with the 1864 * payload in the cluster. 1865 */ 1866 1867 m = fr_offset == 0 ? 1868 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA); 1869 if (m == NULL) 1870 return (NULL); 1871 fl->mbuf_allocated++; 1872 if (clm != NULL) { 1873 m_extaddref(m, payload, blen, &clm->refcount, 1874 rxb_free, swz->zone, sd->cl); 1875 if (sd->nmbuf++ == 0) 1876 counter_u64_add(extfree_refs, 1); 1877 } else { 1878 m_cljset(m, sd->cl, swz->type); 1879 sd->cl = NULL; /* consumed, not a recycle candidate */ 1880 } 1881 } 1882 if (fr_offset == 0) 1883 m->m_pkthdr.len = remaining; 1884 m->m_len = len; 1885 1886 if (fl->flags & FL_BUF_PACKING) { 1887 fl->rx_offset += blen; 1888 MPASS(fl->rx_offset <= hwb->size); 1889 if (fl->rx_offset < hwb->size) 1890 return (m); /* without advancing the cidx */ 1891 } 1892 1893 if (__predict_false(++fl->cidx % 8 == 0)) { 1894 uint16_t cidx = fl->cidx / 8; 1895 1896 if (__predict_false(cidx == fl->sidx)) 1897 fl->cidx = cidx = 0; 1898 fl->hw_cidx = cidx; 1899 } 1900 fl->rx_offset = 0; 1901 1902 return (m); 1903 } 1904 1905 static struct mbuf * 1906 get_fl_payload(struct adapter *sc, struct sge_fl *fl, uint32_t len_newbuf) 1907 { 1908 struct mbuf *m0, *m, **pnext; 1909 u_int remaining; 1910 const u_int total = G_RSPD_LEN(len_newbuf); 1911 1912 if (__predict_false(fl->flags & FL_BUF_RESUME)) { 1913 M_ASSERTPKTHDR(fl->m0); 1914 MPASS(fl->m0->m_pkthdr.len == total); 1915 MPASS(fl->remaining < total); 1916 1917 m0 = fl->m0; 1918 pnext = fl->pnext; 1919 remaining = fl->remaining; 1920 fl->flags &= ~FL_BUF_RESUME; 1921 goto get_segment; 1922 } 1923 1924 if (fl->rx_offset > 0 && len_newbuf & F_RSPD_NEWBUF) { 1925 fl->rx_offset = 0; 1926 if (__predict_false(++fl->cidx % 8 == 0)) { 1927 uint16_t cidx = fl->cidx / 8; 1928 1929 if (__predict_false(cidx == fl->sidx)) 1930 fl->cidx = cidx = 0; 1931 fl->hw_cidx = cidx; 1932 } 1933 } 1934 1935 /* 1936 * Payload starts at rx_offset in the current hw buffer. Its length is 1937 * 'len' and it may span multiple hw buffers. 1938 */ 1939 1940 m0 = get_scatter_segment(sc, fl, 0, total); 1941 if (m0 == NULL) 1942 return (NULL); 1943 remaining = total - m0->m_len; 1944 pnext = &m0->m_next; 1945 while (remaining > 0) { 1946 get_segment: 1947 MPASS(fl->rx_offset == 0); 1948 m = get_scatter_segment(sc, fl, total - remaining, remaining); 1949 if (__predict_false(m == NULL)) { 1950 fl->m0 = m0; 1951 fl->pnext = pnext; 1952 fl->remaining = remaining; 1953 fl->flags |= FL_BUF_RESUME; 1954 return (NULL); 1955 } 1956 *pnext = m; 1957 pnext = &m->m_next; 1958 remaining -= m->m_len; 1959 } 1960 *pnext = NULL; 1961 1962 M_ASSERTPKTHDR(m0); 1963 return (m0); 1964 } 1965 1966 static int 1967 t4_eth_rx(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0) 1968 { 1969 struct sge_rxq *rxq = iq_to_rxq(iq); 1970 struct ifnet *ifp = rxq->ifp; 1971 struct adapter *sc = iq->adapter; 1972 const struct cpl_rx_pkt *cpl = (const void *)(rss + 1); 1973 #if defined(INET) || defined(INET6) 1974 struct lro_ctrl *lro = &rxq->lro; 1975 #endif 1976 static const int sw_hashtype[4][2] = { 1977 {M_HASHTYPE_NONE, M_HASHTYPE_NONE}, 1978 {M_HASHTYPE_RSS_IPV4, M_HASHTYPE_RSS_IPV6}, 1979 {M_HASHTYPE_RSS_TCP_IPV4, M_HASHTYPE_RSS_TCP_IPV6}, 1980 {M_HASHTYPE_RSS_UDP_IPV4, M_HASHTYPE_RSS_UDP_IPV6}, 1981 }; 1982 1983 KASSERT(m0 != NULL, ("%s: no payload with opcode %02x", __func__, 1984 rss->opcode)); 1985 1986 m0->m_pkthdr.len -= sc->params.sge.fl_pktshift; 1987 m0->m_len -= sc->params.sge.fl_pktshift; 1988 m0->m_data += sc->params.sge.fl_pktshift; 1989 1990 m0->m_pkthdr.rcvif = ifp; 1991 M_HASHTYPE_SET(m0, sw_hashtype[rss->hash_type][rss->ipv6]); 1992 m0->m_pkthdr.flowid = be32toh(rss->hash_val); 1993 1994 if (cpl->csum_calc && !(cpl->err_vec & sc->params.tp.err_vec_mask)) { 1995 if (ifp->if_capenable & IFCAP_RXCSUM && 1996 cpl->l2info & htobe32(F_RXF_IP)) { 1997 m0->m_pkthdr.csum_flags = (CSUM_IP_CHECKED | 1998 CSUM_IP_VALID | CSUM_DATA_VALID | CSUM_PSEUDO_HDR); 1999 rxq->rxcsum++; 2000 } else if (ifp->if_capenable & IFCAP_RXCSUM_IPV6 && 2001 cpl->l2info & htobe32(F_RXF_IP6)) { 2002 m0->m_pkthdr.csum_flags = (CSUM_DATA_VALID_IPV6 | 2003 CSUM_PSEUDO_HDR); 2004 rxq->rxcsum++; 2005 } 2006 2007 if (__predict_false(cpl->ip_frag)) 2008 m0->m_pkthdr.csum_data = be16toh(cpl->csum); 2009 else 2010 m0->m_pkthdr.csum_data = 0xffff; 2011 } 2012 2013 if (cpl->vlan_ex) { 2014 m0->m_pkthdr.ether_vtag = be16toh(cpl->vlan); 2015 m0->m_flags |= M_VLANTAG; 2016 rxq->vlan_extraction++; 2017 } 2018 2019 #if defined(INET) || defined(INET6) 2020 if (iq->flags & IQ_LRO_ENABLED) { 2021 if (sort_before_lro(lro)) { 2022 tcp_lro_queue_mbuf(lro, m0); 2023 return (0); /* queued for sort, then LRO */ 2024 } 2025 if (tcp_lro_rx(lro, m0, 0) == 0) 2026 return (0); /* queued for LRO */ 2027 } 2028 #endif 2029 ifp->if_input(ifp, m0); 2030 2031 return (0); 2032 } 2033 2034 /* 2035 * Must drain the wrq or make sure that someone else will. 2036 */ 2037 static void 2038 wrq_tx_drain(void *arg, int n) 2039 { 2040 struct sge_wrq *wrq = arg; 2041 struct sge_eq *eq = &wrq->eq; 2042 2043 EQ_LOCK(eq); 2044 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 2045 drain_wrq_wr_list(wrq->adapter, wrq); 2046 EQ_UNLOCK(eq); 2047 } 2048 2049 static void 2050 drain_wrq_wr_list(struct adapter *sc, struct sge_wrq *wrq) 2051 { 2052 struct sge_eq *eq = &wrq->eq; 2053 u_int available, dbdiff; /* # of hardware descriptors */ 2054 u_int n; 2055 struct wrqe *wr; 2056 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */ 2057 2058 EQ_LOCK_ASSERT_OWNED(eq); 2059 MPASS(TAILQ_EMPTY(&wrq->incomplete_wrs)); 2060 wr = STAILQ_FIRST(&wrq->wr_list); 2061 MPASS(wr != NULL); /* Must be called with something useful to do */ 2062 MPASS(eq->pidx == eq->dbidx); 2063 dbdiff = 0; 2064 2065 do { 2066 eq->cidx = read_hw_cidx(eq); 2067 if (eq->pidx == eq->cidx) 2068 available = eq->sidx - 1; 2069 else 2070 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2071 2072 MPASS(wr->wrq == wrq); 2073 n = howmany(wr->wr_len, EQ_ESIZE); 2074 if (available < n) 2075 break; 2076 2077 dst = (void *)&eq->desc[eq->pidx]; 2078 if (__predict_true(eq->sidx - eq->pidx > n)) { 2079 /* Won't wrap, won't end exactly at the status page. */ 2080 bcopy(&wr->wr[0], dst, wr->wr_len); 2081 eq->pidx += n; 2082 } else { 2083 int first_portion = (eq->sidx - eq->pidx) * EQ_ESIZE; 2084 2085 bcopy(&wr->wr[0], dst, first_portion); 2086 if (wr->wr_len > first_portion) { 2087 bcopy(&wr->wr[first_portion], &eq->desc[0], 2088 wr->wr_len - first_portion); 2089 } 2090 eq->pidx = n - (eq->sidx - eq->pidx); 2091 } 2092 wrq->tx_wrs_copied++; 2093 2094 if (available < eq->sidx / 4 && 2095 atomic_cmpset_int(&eq->equiq, 0, 1)) { 2096 /* 2097 * XXX: This is not 100% reliable with some 2098 * types of WRs. But this is a very unusual 2099 * situation for an ofld/ctrl queue anyway. 2100 */ 2101 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ | 2102 F_FW_WR_EQUEQ); 2103 } 2104 2105 dbdiff += n; 2106 if (dbdiff >= 16) { 2107 ring_eq_db(sc, eq, dbdiff); 2108 dbdiff = 0; 2109 } 2110 2111 STAILQ_REMOVE_HEAD(&wrq->wr_list, link); 2112 free_wrqe(wr); 2113 MPASS(wrq->nwr_pending > 0); 2114 wrq->nwr_pending--; 2115 MPASS(wrq->ndesc_needed >= n); 2116 wrq->ndesc_needed -= n; 2117 } while ((wr = STAILQ_FIRST(&wrq->wr_list)) != NULL); 2118 2119 if (dbdiff) 2120 ring_eq_db(sc, eq, dbdiff); 2121 } 2122 2123 /* 2124 * Doesn't fail. Holds on to work requests it can't send right away. 2125 */ 2126 void 2127 t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, struct wrqe *wr) 2128 { 2129 #ifdef INVARIANTS 2130 struct sge_eq *eq = &wrq->eq; 2131 #endif 2132 2133 EQ_LOCK_ASSERT_OWNED(eq); 2134 MPASS(wr != NULL); 2135 MPASS(wr->wr_len > 0 && wr->wr_len <= SGE_MAX_WR_LEN); 2136 MPASS((wr->wr_len & 0x7) == 0); 2137 2138 STAILQ_INSERT_TAIL(&wrq->wr_list, wr, link); 2139 wrq->nwr_pending++; 2140 wrq->ndesc_needed += howmany(wr->wr_len, EQ_ESIZE); 2141 2142 if (!TAILQ_EMPTY(&wrq->incomplete_wrs)) 2143 return; /* commit_wrq_wr will drain wr_list as well. */ 2144 2145 drain_wrq_wr_list(sc, wrq); 2146 2147 /* Doorbell must have caught up to the pidx. */ 2148 MPASS(eq->pidx == eq->dbidx); 2149 } 2150 2151 void 2152 t4_update_fl_bufsize(struct ifnet *ifp) 2153 { 2154 struct vi_info *vi = ifp->if_softc; 2155 struct adapter *sc = vi->pi->adapter; 2156 struct sge_rxq *rxq; 2157 #ifdef TCP_OFFLOAD 2158 struct sge_ofld_rxq *ofld_rxq; 2159 #endif 2160 struct sge_fl *fl; 2161 int i, maxp, mtu = ifp->if_mtu; 2162 2163 maxp = mtu_to_max_payload(sc, mtu, 0); 2164 for_each_rxq(vi, i, rxq) { 2165 fl = &rxq->fl; 2166 2167 FL_LOCK(fl); 2168 find_best_refill_source(sc, fl, maxp); 2169 FL_UNLOCK(fl); 2170 } 2171 #ifdef TCP_OFFLOAD 2172 maxp = mtu_to_max_payload(sc, mtu, 1); 2173 for_each_ofld_rxq(vi, i, ofld_rxq) { 2174 fl = &ofld_rxq->fl; 2175 2176 FL_LOCK(fl); 2177 find_best_refill_source(sc, fl, maxp); 2178 FL_UNLOCK(fl); 2179 } 2180 #endif 2181 } 2182 2183 static inline int 2184 mbuf_nsegs(struct mbuf *m) 2185 { 2186 2187 M_ASSERTPKTHDR(m); 2188 KASSERT(m->m_pkthdr.l5hlen > 0, 2189 ("%s: mbuf %p missing information on # of segments.", __func__, m)); 2190 2191 return (m->m_pkthdr.l5hlen); 2192 } 2193 2194 static inline void 2195 set_mbuf_nsegs(struct mbuf *m, uint8_t nsegs) 2196 { 2197 2198 M_ASSERTPKTHDR(m); 2199 m->m_pkthdr.l5hlen = nsegs; 2200 } 2201 2202 static inline int 2203 mbuf_cflags(struct mbuf *m) 2204 { 2205 2206 M_ASSERTPKTHDR(m); 2207 return (m->m_pkthdr.PH_loc.eight[4]); 2208 } 2209 2210 static inline void 2211 set_mbuf_cflags(struct mbuf *m, uint8_t flags) 2212 { 2213 2214 M_ASSERTPKTHDR(m); 2215 m->m_pkthdr.PH_loc.eight[4] = flags; 2216 } 2217 2218 static inline int 2219 mbuf_len16(struct mbuf *m) 2220 { 2221 int n; 2222 2223 M_ASSERTPKTHDR(m); 2224 n = m->m_pkthdr.PH_loc.eight[0]; 2225 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16); 2226 2227 return (n); 2228 } 2229 2230 static inline void 2231 set_mbuf_len16(struct mbuf *m, uint8_t len16) 2232 { 2233 2234 M_ASSERTPKTHDR(m); 2235 m->m_pkthdr.PH_loc.eight[0] = len16; 2236 } 2237 2238 #ifdef RATELIMIT 2239 static inline int 2240 mbuf_eo_nsegs(struct mbuf *m) 2241 { 2242 2243 M_ASSERTPKTHDR(m); 2244 return (m->m_pkthdr.PH_loc.eight[1]); 2245 } 2246 2247 static inline void 2248 set_mbuf_eo_nsegs(struct mbuf *m, uint8_t nsegs) 2249 { 2250 2251 M_ASSERTPKTHDR(m); 2252 m->m_pkthdr.PH_loc.eight[1] = nsegs; 2253 } 2254 2255 static inline int 2256 mbuf_eo_len16(struct mbuf *m) 2257 { 2258 int n; 2259 2260 M_ASSERTPKTHDR(m); 2261 n = m->m_pkthdr.PH_loc.eight[2]; 2262 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16); 2263 2264 return (n); 2265 } 2266 2267 static inline void 2268 set_mbuf_eo_len16(struct mbuf *m, uint8_t len16) 2269 { 2270 2271 M_ASSERTPKTHDR(m); 2272 m->m_pkthdr.PH_loc.eight[2] = len16; 2273 } 2274 2275 static inline int 2276 mbuf_eo_tsclk_tsoff(struct mbuf *m) 2277 { 2278 2279 M_ASSERTPKTHDR(m); 2280 return (m->m_pkthdr.PH_loc.eight[3]); 2281 } 2282 2283 static inline void 2284 set_mbuf_eo_tsclk_tsoff(struct mbuf *m, uint8_t tsclk_tsoff) 2285 { 2286 2287 M_ASSERTPKTHDR(m); 2288 m->m_pkthdr.PH_loc.eight[3] = tsclk_tsoff; 2289 } 2290 2291 static inline int 2292 needs_eo(struct mbuf *m) 2293 { 2294 2295 return (m->m_pkthdr.snd_tag != NULL); 2296 } 2297 #endif 2298 2299 /* 2300 * Try to allocate an mbuf to contain a raw work request. To make it 2301 * easy to construct the work request, don't allocate a chain but a 2302 * single mbuf. 2303 */ 2304 struct mbuf * 2305 alloc_wr_mbuf(int len, int how) 2306 { 2307 struct mbuf *m; 2308 2309 if (len <= MHLEN) 2310 m = m_gethdr(how, MT_DATA); 2311 else if (len <= MCLBYTES) 2312 m = m_getcl(how, MT_DATA, M_PKTHDR); 2313 else 2314 m = NULL; 2315 if (m == NULL) 2316 return (NULL); 2317 m->m_pkthdr.len = len; 2318 m->m_len = len; 2319 set_mbuf_cflags(m, MC_RAW_WR); 2320 set_mbuf_len16(m, howmany(len, 16)); 2321 return (m); 2322 } 2323 2324 static inline int 2325 needs_tso(struct mbuf *m) 2326 { 2327 2328 M_ASSERTPKTHDR(m); 2329 2330 return (m->m_pkthdr.csum_flags & CSUM_TSO); 2331 } 2332 2333 static inline int 2334 needs_l3_csum(struct mbuf *m) 2335 { 2336 2337 M_ASSERTPKTHDR(m); 2338 2339 return (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TSO)); 2340 } 2341 2342 static inline int 2343 needs_l4_csum(struct mbuf *m) 2344 { 2345 2346 M_ASSERTPKTHDR(m); 2347 2348 return (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_UDP_IPV6 | 2349 CSUM_TCP_IPV6 | CSUM_TSO)); 2350 } 2351 2352 static inline int 2353 needs_tcp_csum(struct mbuf *m) 2354 { 2355 2356 M_ASSERTPKTHDR(m); 2357 return (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_TCP_IPV6 | CSUM_TSO)); 2358 } 2359 2360 #ifdef RATELIMIT 2361 static inline int 2362 needs_udp_csum(struct mbuf *m) 2363 { 2364 2365 M_ASSERTPKTHDR(m); 2366 return (m->m_pkthdr.csum_flags & (CSUM_UDP | CSUM_UDP_IPV6)); 2367 } 2368 #endif 2369 2370 static inline int 2371 needs_vlan_insertion(struct mbuf *m) 2372 { 2373 2374 M_ASSERTPKTHDR(m); 2375 2376 return (m->m_flags & M_VLANTAG); 2377 } 2378 2379 static void * 2380 m_advance(struct mbuf **pm, int *poffset, int len) 2381 { 2382 struct mbuf *m = *pm; 2383 int offset = *poffset; 2384 uintptr_t p = 0; 2385 2386 MPASS(len > 0); 2387 2388 for (;;) { 2389 if (offset + len < m->m_len) { 2390 offset += len; 2391 p = mtod(m, uintptr_t) + offset; 2392 break; 2393 } 2394 len -= m->m_len - offset; 2395 m = m->m_next; 2396 offset = 0; 2397 MPASS(m != NULL); 2398 } 2399 *poffset = offset; 2400 *pm = m; 2401 return ((void *)p); 2402 } 2403 2404 /* 2405 * Can deal with empty mbufs in the chain that have m_len = 0, but the chain 2406 * must have at least one mbuf that's not empty. It is possible for this 2407 * routine to return 0 if skip accounts for all the contents of the mbuf chain. 2408 */ 2409 static inline int 2410 count_mbuf_nsegs(struct mbuf *m, int skip) 2411 { 2412 vm_paddr_t lastb, next; 2413 vm_offset_t va; 2414 int len, nsegs; 2415 2416 M_ASSERTPKTHDR(m); 2417 MPASS(m->m_pkthdr.len > 0); 2418 MPASS(m->m_pkthdr.len >= skip); 2419 2420 nsegs = 0; 2421 lastb = 0; 2422 for (; m; m = m->m_next) { 2423 2424 len = m->m_len; 2425 if (__predict_false(len == 0)) 2426 continue; 2427 if (skip >= len) { 2428 skip -= len; 2429 continue; 2430 } 2431 va = mtod(m, vm_offset_t) + skip; 2432 len -= skip; 2433 skip = 0; 2434 next = pmap_kextract(va); 2435 nsegs += sglist_count((void *)(uintptr_t)va, len); 2436 if (lastb + 1 == next) 2437 nsegs--; 2438 lastb = pmap_kextract(va + len - 1); 2439 } 2440 2441 return (nsegs); 2442 } 2443 2444 /* 2445 * Analyze the mbuf to determine its tx needs. The mbuf passed in may change: 2446 * a) caller can assume it's been freed if this function returns with an error. 2447 * b) it may get defragged up if the gather list is too long for the hardware. 2448 */ 2449 int 2450 parse_pkt(struct adapter *sc, struct mbuf **mp) 2451 { 2452 struct mbuf *m0 = *mp, *m; 2453 int rc, nsegs, defragged = 0, offset; 2454 struct ether_header *eh; 2455 void *l3hdr; 2456 #if defined(INET) || defined(INET6) 2457 struct tcphdr *tcp; 2458 #endif 2459 uint16_t eh_type; 2460 2461 M_ASSERTPKTHDR(m0); 2462 if (__predict_false(m0->m_pkthdr.len < ETHER_HDR_LEN)) { 2463 rc = EINVAL; 2464 fail: 2465 m_freem(m0); 2466 *mp = NULL; 2467 return (rc); 2468 } 2469 restart: 2470 /* 2471 * First count the number of gather list segments in the payload. 2472 * Defrag the mbuf if nsegs exceeds the hardware limit. 2473 */ 2474 M_ASSERTPKTHDR(m0); 2475 MPASS(m0->m_pkthdr.len > 0); 2476 nsegs = count_mbuf_nsegs(m0, 0); 2477 if (nsegs > (needs_tso(m0) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS)) { 2478 if (defragged++ > 0 || (m = m_defrag(m0, M_NOWAIT)) == NULL) { 2479 rc = EFBIG; 2480 goto fail; 2481 } 2482 *mp = m0 = m; /* update caller's copy after defrag */ 2483 goto restart; 2484 } 2485 2486 if (__predict_false(nsegs > 2 && m0->m_pkthdr.len <= MHLEN)) { 2487 m0 = m_pullup(m0, m0->m_pkthdr.len); 2488 if (m0 == NULL) { 2489 /* Should have left well enough alone. */ 2490 rc = EFBIG; 2491 goto fail; 2492 } 2493 *mp = m0; /* update caller's copy after pullup */ 2494 goto restart; 2495 } 2496 set_mbuf_nsegs(m0, nsegs); 2497 set_mbuf_cflags(m0, 0); 2498 if (sc->flags & IS_VF) 2499 set_mbuf_len16(m0, txpkt_vm_len16(nsegs, needs_tso(m0))); 2500 else 2501 set_mbuf_len16(m0, txpkt_len16(nsegs, needs_tso(m0))); 2502 2503 #ifdef RATELIMIT 2504 /* 2505 * Ethofld is limited to TCP and UDP for now, and only when L4 hw 2506 * checksumming is enabled. needs_l4_csum happens to check for all the 2507 * right things. 2508 */ 2509 if (__predict_false(needs_eo(m0) && !needs_l4_csum(m0))) 2510 m0->m_pkthdr.snd_tag = NULL; 2511 #endif 2512 2513 if (!needs_tso(m0) && 2514 #ifdef RATELIMIT 2515 !needs_eo(m0) && 2516 #endif 2517 !(sc->flags & IS_VF && (needs_l3_csum(m0) || needs_l4_csum(m0)))) 2518 return (0); 2519 2520 m = m0; 2521 eh = mtod(m, struct ether_header *); 2522 eh_type = ntohs(eh->ether_type); 2523 if (eh_type == ETHERTYPE_VLAN) { 2524 struct ether_vlan_header *evh = (void *)eh; 2525 2526 eh_type = ntohs(evh->evl_proto); 2527 m0->m_pkthdr.l2hlen = sizeof(*evh); 2528 } else 2529 m0->m_pkthdr.l2hlen = sizeof(*eh); 2530 2531 offset = 0; 2532 l3hdr = m_advance(&m, &offset, m0->m_pkthdr.l2hlen); 2533 2534 switch (eh_type) { 2535 #ifdef INET6 2536 case ETHERTYPE_IPV6: 2537 { 2538 struct ip6_hdr *ip6 = l3hdr; 2539 2540 MPASS(!needs_tso(m0) || ip6->ip6_nxt == IPPROTO_TCP); 2541 2542 m0->m_pkthdr.l3hlen = sizeof(*ip6); 2543 break; 2544 } 2545 #endif 2546 #ifdef INET 2547 case ETHERTYPE_IP: 2548 { 2549 struct ip *ip = l3hdr; 2550 2551 m0->m_pkthdr.l3hlen = ip->ip_hl * 4; 2552 break; 2553 } 2554 #endif 2555 default: 2556 panic("%s: ethertype 0x%04x unknown. if_cxgbe must be compiled" 2557 " with the same INET/INET6 options as the kernel.", 2558 __func__, eh_type); 2559 } 2560 2561 #if defined(INET) || defined(INET6) 2562 if (needs_tcp_csum(m0)) { 2563 tcp = m_advance(&m, &offset, m0->m_pkthdr.l3hlen); 2564 m0->m_pkthdr.l4hlen = tcp->th_off * 4; 2565 #ifdef RATELIMIT 2566 if (tsclk >= 0 && *(uint32_t *)(tcp + 1) == ntohl(0x0101080a)) { 2567 set_mbuf_eo_tsclk_tsoff(m0, 2568 V_FW_ETH_TX_EO_WR_TSCLK(tsclk) | 2569 V_FW_ETH_TX_EO_WR_TSOFF(sizeof(*tcp) / 2 + 1)); 2570 } else 2571 set_mbuf_eo_tsclk_tsoff(m0, 0); 2572 } else if (needs_udp_csum(m)) { 2573 m0->m_pkthdr.l4hlen = sizeof(struct udphdr); 2574 #endif 2575 } 2576 #ifdef RATELIMIT 2577 if (needs_eo(m0)) { 2578 u_int immhdrs; 2579 2580 /* EO WRs have the headers in the WR and not the GL. */ 2581 immhdrs = m0->m_pkthdr.l2hlen + m0->m_pkthdr.l3hlen + 2582 m0->m_pkthdr.l4hlen; 2583 nsegs = count_mbuf_nsegs(m0, immhdrs); 2584 set_mbuf_eo_nsegs(m0, nsegs); 2585 set_mbuf_eo_len16(m0, 2586 txpkt_eo_len16(nsegs, immhdrs, needs_tso(m0))); 2587 } 2588 #endif 2589 #endif 2590 MPASS(m0 == *mp); 2591 return (0); 2592 } 2593 2594 void * 2595 start_wrq_wr(struct sge_wrq *wrq, int len16, struct wrq_cookie *cookie) 2596 { 2597 struct sge_eq *eq = &wrq->eq; 2598 struct adapter *sc = wrq->adapter; 2599 int ndesc, available; 2600 struct wrqe *wr; 2601 void *w; 2602 2603 MPASS(len16 > 0); 2604 ndesc = howmany(len16, EQ_ESIZE / 16); 2605 MPASS(ndesc > 0 && ndesc <= SGE_MAX_WR_NDESC); 2606 2607 EQ_LOCK(eq); 2608 2609 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 2610 drain_wrq_wr_list(sc, wrq); 2611 2612 if (!STAILQ_EMPTY(&wrq->wr_list)) { 2613 slowpath: 2614 EQ_UNLOCK(eq); 2615 wr = alloc_wrqe(len16 * 16, wrq); 2616 if (__predict_false(wr == NULL)) 2617 return (NULL); 2618 cookie->pidx = -1; 2619 cookie->ndesc = ndesc; 2620 return (&wr->wr); 2621 } 2622 2623 eq->cidx = read_hw_cidx(eq); 2624 if (eq->pidx == eq->cidx) 2625 available = eq->sidx - 1; 2626 else 2627 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2628 if (available < ndesc) 2629 goto slowpath; 2630 2631 cookie->pidx = eq->pidx; 2632 cookie->ndesc = ndesc; 2633 TAILQ_INSERT_TAIL(&wrq->incomplete_wrs, cookie, link); 2634 2635 w = &eq->desc[eq->pidx]; 2636 IDXINCR(eq->pidx, ndesc, eq->sidx); 2637 if (__predict_false(cookie->pidx + ndesc > eq->sidx)) { 2638 w = &wrq->ss[0]; 2639 wrq->ss_pidx = cookie->pidx; 2640 wrq->ss_len = len16 * 16; 2641 } 2642 2643 EQ_UNLOCK(eq); 2644 2645 return (w); 2646 } 2647 2648 void 2649 commit_wrq_wr(struct sge_wrq *wrq, void *w, struct wrq_cookie *cookie) 2650 { 2651 struct sge_eq *eq = &wrq->eq; 2652 struct adapter *sc = wrq->adapter; 2653 int ndesc, pidx; 2654 struct wrq_cookie *prev, *next; 2655 2656 if (cookie->pidx == -1) { 2657 struct wrqe *wr = __containerof(w, struct wrqe, wr); 2658 2659 t4_wrq_tx(sc, wr); 2660 return; 2661 } 2662 2663 if (__predict_false(w == &wrq->ss[0])) { 2664 int n = (eq->sidx - wrq->ss_pidx) * EQ_ESIZE; 2665 2666 MPASS(wrq->ss_len > n); /* WR had better wrap around. */ 2667 bcopy(&wrq->ss[0], &eq->desc[wrq->ss_pidx], n); 2668 bcopy(&wrq->ss[n], &eq->desc[0], wrq->ss_len - n); 2669 wrq->tx_wrs_ss++; 2670 } else 2671 wrq->tx_wrs_direct++; 2672 2673 EQ_LOCK(eq); 2674 ndesc = cookie->ndesc; /* Can be more than SGE_MAX_WR_NDESC here. */ 2675 pidx = cookie->pidx; 2676 MPASS(pidx >= 0 && pidx < eq->sidx); 2677 prev = TAILQ_PREV(cookie, wrq_incomplete_wrs, link); 2678 next = TAILQ_NEXT(cookie, link); 2679 if (prev == NULL) { 2680 MPASS(pidx == eq->dbidx); 2681 if (next == NULL || ndesc >= 16) { 2682 int available; 2683 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */ 2684 2685 /* 2686 * Note that the WR via which we'll request tx updates 2687 * is at pidx and not eq->pidx, which has moved on 2688 * already. 2689 */ 2690 dst = (void *)&eq->desc[pidx]; 2691 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2692 if (available < eq->sidx / 4 && 2693 atomic_cmpset_int(&eq->equiq, 0, 1)) { 2694 /* 2695 * XXX: This is not 100% reliable with some 2696 * types of WRs. But this is a very unusual 2697 * situation for an ofld/ctrl queue anyway. 2698 */ 2699 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ | 2700 F_FW_WR_EQUEQ); 2701 } 2702 2703 ring_eq_db(wrq->adapter, eq, ndesc); 2704 } else { 2705 MPASS(IDXDIFF(next->pidx, pidx, eq->sidx) == ndesc); 2706 next->pidx = pidx; 2707 next->ndesc += ndesc; 2708 } 2709 } else { 2710 MPASS(IDXDIFF(pidx, prev->pidx, eq->sidx) == prev->ndesc); 2711 prev->ndesc += ndesc; 2712 } 2713 TAILQ_REMOVE(&wrq->incomplete_wrs, cookie, link); 2714 2715 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 2716 drain_wrq_wr_list(sc, wrq); 2717 2718 #ifdef INVARIANTS 2719 if (TAILQ_EMPTY(&wrq->incomplete_wrs)) { 2720 /* Doorbell must have caught up to the pidx. */ 2721 MPASS(wrq->eq.pidx == wrq->eq.dbidx); 2722 } 2723 #endif 2724 EQ_UNLOCK(eq); 2725 } 2726 2727 static u_int 2728 can_resume_eth_tx(struct mp_ring *r) 2729 { 2730 struct sge_eq *eq = r->cookie; 2731 2732 return (total_available_tx_desc(eq) > eq->sidx / 8); 2733 } 2734 2735 static inline int 2736 cannot_use_txpkts(struct mbuf *m) 2737 { 2738 /* maybe put a GL limit too, to avoid silliness? */ 2739 2740 return (needs_tso(m) || (mbuf_cflags(m) & MC_RAW_WR) != 0); 2741 } 2742 2743 static inline int 2744 discard_tx(struct sge_eq *eq) 2745 { 2746 2747 return ((eq->flags & (EQ_ENABLED | EQ_QFLUSH)) != EQ_ENABLED); 2748 } 2749 2750 static inline int 2751 wr_can_update_eq(struct fw_eth_tx_pkts_wr *wr) 2752 { 2753 2754 switch (G_FW_WR_OP(be32toh(wr->op_pkd))) { 2755 case FW_ULPTX_WR: 2756 case FW_ETH_TX_PKT_WR: 2757 case FW_ETH_TX_PKTS_WR: 2758 case FW_ETH_TX_PKT_VM_WR: 2759 return (1); 2760 default: 2761 return (0); 2762 } 2763 } 2764 2765 /* 2766 * r->items[cidx] to r->items[pidx], with a wraparound at r->size, are ready to 2767 * be consumed. Return the actual number consumed. 0 indicates a stall. 2768 */ 2769 static u_int 2770 eth_tx(struct mp_ring *r, u_int cidx, u_int pidx) 2771 { 2772 struct sge_txq *txq = r->cookie; 2773 struct sge_eq *eq = &txq->eq; 2774 struct ifnet *ifp = txq->ifp; 2775 struct vi_info *vi = ifp->if_softc; 2776 struct port_info *pi = vi->pi; 2777 struct adapter *sc = pi->adapter; 2778 u_int total, remaining; /* # of packets */ 2779 u_int available, dbdiff; /* # of hardware descriptors */ 2780 u_int n, next_cidx; 2781 struct mbuf *m0, *tail; 2782 struct txpkts txp; 2783 struct fw_eth_tx_pkts_wr *wr; /* any fw WR struct will do */ 2784 2785 remaining = IDXDIFF(pidx, cidx, r->size); 2786 MPASS(remaining > 0); /* Must not be called without work to do. */ 2787 total = 0; 2788 2789 TXQ_LOCK(txq); 2790 if (__predict_false(discard_tx(eq))) { 2791 while (cidx != pidx) { 2792 m0 = r->items[cidx]; 2793 m_freem(m0); 2794 if (++cidx == r->size) 2795 cidx = 0; 2796 } 2797 reclaim_tx_descs(txq, 2048); 2798 total = remaining; 2799 goto done; 2800 } 2801 2802 /* How many hardware descriptors do we have readily available. */ 2803 if (eq->pidx == eq->cidx) 2804 available = eq->sidx - 1; 2805 else 2806 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2807 dbdiff = IDXDIFF(eq->pidx, eq->dbidx, eq->sidx); 2808 2809 while (remaining > 0) { 2810 2811 m0 = r->items[cidx]; 2812 M_ASSERTPKTHDR(m0); 2813 MPASS(m0->m_nextpkt == NULL); 2814 2815 if (available < SGE_MAX_WR_NDESC) { 2816 available += reclaim_tx_descs(txq, 64); 2817 if (available < howmany(mbuf_len16(m0), EQ_ESIZE / 16)) 2818 break; /* out of descriptors */ 2819 } 2820 2821 next_cidx = cidx + 1; 2822 if (__predict_false(next_cidx == r->size)) 2823 next_cidx = 0; 2824 2825 wr = (void *)&eq->desc[eq->pidx]; 2826 if (sc->flags & IS_VF) { 2827 total++; 2828 remaining--; 2829 ETHER_BPF_MTAP(ifp, m0); 2830 n = write_txpkt_vm_wr(sc, txq, (void *)wr, m0, 2831 available); 2832 } else if (remaining > 1 && 2833 try_txpkts(m0, r->items[next_cidx], &txp, available) == 0) { 2834 2835 /* pkts at cidx, next_cidx should both be in txp. */ 2836 MPASS(txp.npkt == 2); 2837 tail = r->items[next_cidx]; 2838 MPASS(tail->m_nextpkt == NULL); 2839 ETHER_BPF_MTAP(ifp, m0); 2840 ETHER_BPF_MTAP(ifp, tail); 2841 m0->m_nextpkt = tail; 2842 2843 if (__predict_false(++next_cidx == r->size)) 2844 next_cidx = 0; 2845 2846 while (next_cidx != pidx) { 2847 if (add_to_txpkts(r->items[next_cidx], &txp, 2848 available) != 0) 2849 break; 2850 tail->m_nextpkt = r->items[next_cidx]; 2851 tail = tail->m_nextpkt; 2852 ETHER_BPF_MTAP(ifp, tail); 2853 if (__predict_false(++next_cidx == r->size)) 2854 next_cidx = 0; 2855 } 2856 2857 n = write_txpkts_wr(txq, wr, m0, &txp, available); 2858 total += txp.npkt; 2859 remaining -= txp.npkt; 2860 } else if (mbuf_cflags(m0) & MC_RAW_WR) { 2861 total++; 2862 remaining--; 2863 n = write_raw_wr(txq, (void *)wr, m0, available); 2864 } else { 2865 total++; 2866 remaining--; 2867 ETHER_BPF_MTAP(ifp, m0); 2868 n = write_txpkt_wr(txq, (void *)wr, m0, available); 2869 } 2870 MPASS(n >= 1 && n <= available && n <= SGE_MAX_WR_NDESC); 2871 2872 available -= n; 2873 dbdiff += n; 2874 IDXINCR(eq->pidx, n, eq->sidx); 2875 2876 if (wr_can_update_eq(wr)) { 2877 if (total_available_tx_desc(eq) < eq->sidx / 4 && 2878 atomic_cmpset_int(&eq->equiq, 0, 1)) { 2879 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ | 2880 F_FW_WR_EQUEQ); 2881 eq->equeqidx = eq->pidx; 2882 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 2883 32) { 2884 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ); 2885 eq->equeqidx = eq->pidx; 2886 } 2887 } 2888 2889 if (dbdiff >= 16 && remaining >= 4) { 2890 ring_eq_db(sc, eq, dbdiff); 2891 available += reclaim_tx_descs(txq, 4 * dbdiff); 2892 dbdiff = 0; 2893 } 2894 2895 cidx = next_cidx; 2896 } 2897 if (dbdiff != 0) { 2898 ring_eq_db(sc, eq, dbdiff); 2899 reclaim_tx_descs(txq, 32); 2900 } 2901 done: 2902 TXQ_UNLOCK(txq); 2903 2904 return (total); 2905 } 2906 2907 static inline void 2908 init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int pktc_idx, 2909 int qsize) 2910 { 2911 2912 KASSERT(tmr_idx >= 0 && tmr_idx < SGE_NTIMERS, 2913 ("%s: bad tmr_idx %d", __func__, tmr_idx)); 2914 KASSERT(pktc_idx < SGE_NCOUNTERS, /* -ve is ok, means don't use */ 2915 ("%s: bad pktc_idx %d", __func__, pktc_idx)); 2916 2917 iq->flags = 0; 2918 iq->adapter = sc; 2919 iq->intr_params = V_QINTR_TIMER_IDX(tmr_idx); 2920 iq->intr_pktc_idx = SGE_NCOUNTERS - 1; 2921 if (pktc_idx >= 0) { 2922 iq->intr_params |= F_QINTR_CNT_EN; 2923 iq->intr_pktc_idx = pktc_idx; 2924 } 2925 iq->qsize = roundup2(qsize, 16); /* See FW_IQ_CMD/iqsize */ 2926 iq->sidx = iq->qsize - sc->params.sge.spg_len / IQ_ESIZE; 2927 } 2928 2929 static inline void 2930 init_fl(struct adapter *sc, struct sge_fl *fl, int qsize, int maxp, char *name) 2931 { 2932 2933 fl->qsize = qsize; 2934 fl->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE; 2935 strlcpy(fl->lockname, name, sizeof(fl->lockname)); 2936 if (sc->flags & BUF_PACKING_OK && 2937 ((!is_t4(sc) && buffer_packing) || /* T5+: enabled unless 0 */ 2938 (is_t4(sc) && buffer_packing == 1)))/* T4: disabled unless 1 */ 2939 fl->flags |= FL_BUF_PACKING; 2940 find_best_refill_source(sc, fl, maxp); 2941 find_safe_refill_source(sc, fl); 2942 } 2943 2944 static inline void 2945 init_eq(struct adapter *sc, struct sge_eq *eq, int eqtype, int qsize, 2946 uint8_t tx_chan, uint16_t iqid, char *name) 2947 { 2948 KASSERT(eqtype <= EQ_TYPEMASK, ("%s: bad qtype %d", __func__, eqtype)); 2949 2950 eq->flags = eqtype & EQ_TYPEMASK; 2951 eq->tx_chan = tx_chan; 2952 eq->iqid = iqid; 2953 eq->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE; 2954 strlcpy(eq->lockname, name, sizeof(eq->lockname)); 2955 } 2956 2957 static int 2958 alloc_ring(struct adapter *sc, size_t len, bus_dma_tag_t *tag, 2959 bus_dmamap_t *map, bus_addr_t *pa, void **va) 2960 { 2961 int rc; 2962 2963 rc = bus_dma_tag_create(sc->dmat, 512, 0, BUS_SPACE_MAXADDR, 2964 BUS_SPACE_MAXADDR, NULL, NULL, len, 1, len, 0, NULL, NULL, tag); 2965 if (rc != 0) { 2966 device_printf(sc->dev, "cannot allocate DMA tag: %d\n", rc); 2967 goto done; 2968 } 2969 2970 rc = bus_dmamem_alloc(*tag, va, 2971 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, map); 2972 if (rc != 0) { 2973 device_printf(sc->dev, "cannot allocate DMA memory: %d\n", rc); 2974 goto done; 2975 } 2976 2977 rc = bus_dmamap_load(*tag, *map, *va, len, oneseg_dma_callback, pa, 0); 2978 if (rc != 0) { 2979 device_printf(sc->dev, "cannot load DMA map: %d\n", rc); 2980 goto done; 2981 } 2982 done: 2983 if (rc) 2984 free_ring(sc, *tag, *map, *pa, *va); 2985 2986 return (rc); 2987 } 2988 2989 static int 2990 free_ring(struct adapter *sc, bus_dma_tag_t tag, bus_dmamap_t map, 2991 bus_addr_t pa, void *va) 2992 { 2993 if (pa) 2994 bus_dmamap_unload(tag, map); 2995 if (va) 2996 bus_dmamem_free(tag, va, map); 2997 if (tag) 2998 bus_dma_tag_destroy(tag); 2999 3000 return (0); 3001 } 3002 3003 /* 3004 * Allocates the ring for an ingress queue and an optional freelist. If the 3005 * freelist is specified it will be allocated and then associated with the 3006 * ingress queue. 3007 * 3008 * Returns errno on failure. Resources allocated up to that point may still be 3009 * allocated. Caller is responsible for cleanup in case this function fails. 3010 * 3011 * If the ingress queue will take interrupts directly then the intr_idx 3012 * specifies the vector, starting from 0. -1 means the interrupts for this 3013 * queue should be forwarded to the fwq. 3014 */ 3015 static int 3016 alloc_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl, 3017 int intr_idx, int cong) 3018 { 3019 int rc, i, cntxt_id; 3020 size_t len; 3021 struct fw_iq_cmd c; 3022 struct port_info *pi = vi->pi; 3023 struct adapter *sc = iq->adapter; 3024 struct sge_params *sp = &sc->params.sge; 3025 __be32 v = 0; 3026 3027 len = iq->qsize * IQ_ESIZE; 3028 rc = alloc_ring(sc, len, &iq->desc_tag, &iq->desc_map, &iq->ba, 3029 (void **)&iq->desc); 3030 if (rc != 0) 3031 return (rc); 3032 3033 bzero(&c, sizeof(c)); 3034 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 3035 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) | 3036 V_FW_IQ_CMD_VFN(0)); 3037 3038 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART | 3039 FW_LEN16(c)); 3040 3041 /* Special handling for firmware event queue */ 3042 if (iq == &sc->sge.fwq) 3043 v |= F_FW_IQ_CMD_IQASYNCH; 3044 3045 if (intr_idx < 0) { 3046 /* Forwarded interrupts, all headed to fwq */ 3047 v |= F_FW_IQ_CMD_IQANDST; 3048 v |= V_FW_IQ_CMD_IQANDSTINDEX(sc->sge.fwq.cntxt_id); 3049 } else { 3050 KASSERT(intr_idx < sc->intr_count, 3051 ("%s: invalid direct intr_idx %d", __func__, intr_idx)); 3052 v |= V_FW_IQ_CMD_IQANDSTINDEX(intr_idx); 3053 } 3054 3055 c.type_to_iqandstindex = htobe32(v | 3056 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) | 3057 V_FW_IQ_CMD_VIID(vi->viid) | 3058 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT)); 3059 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->tx_chan) | 3060 F_FW_IQ_CMD_IQGTSMODE | 3061 V_FW_IQ_CMD_IQINTCNTTHRESH(iq->intr_pktc_idx) | 3062 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4)); 3063 c.iqsize = htobe16(iq->qsize); 3064 c.iqaddr = htobe64(iq->ba); 3065 if (cong >= 0) 3066 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN); 3067 3068 if (fl) { 3069 mtx_init(&fl->fl_lock, fl->lockname, NULL, MTX_DEF); 3070 3071 len = fl->qsize * EQ_ESIZE; 3072 rc = alloc_ring(sc, len, &fl->desc_tag, &fl->desc_map, 3073 &fl->ba, (void **)&fl->desc); 3074 if (rc) 3075 return (rc); 3076 3077 /* Allocate space for one software descriptor per buffer. */ 3078 rc = alloc_fl_sdesc(fl); 3079 if (rc != 0) { 3080 device_printf(sc->dev, 3081 "failed to setup fl software descriptors: %d\n", 3082 rc); 3083 return (rc); 3084 } 3085 3086 if (fl->flags & FL_BUF_PACKING) { 3087 fl->lowat = roundup2(sp->fl_starve_threshold2, 8); 3088 fl->buf_boundary = sp->pack_boundary; 3089 } else { 3090 fl->lowat = roundup2(sp->fl_starve_threshold, 8); 3091 fl->buf_boundary = 16; 3092 } 3093 if (fl_pad && fl->buf_boundary < sp->pad_boundary) 3094 fl->buf_boundary = sp->pad_boundary; 3095 3096 c.iqns_to_fl0congen |= 3097 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) | 3098 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO | 3099 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) | 3100 (fl->flags & FL_BUF_PACKING ? F_FW_IQ_CMD_FL0PACKEN : 3101 0)); 3102 if (cong >= 0) { 3103 c.iqns_to_fl0congen |= 3104 htobe32(V_FW_IQ_CMD_FL0CNGCHMAP(cong) | 3105 F_FW_IQ_CMD_FL0CONGCIF | 3106 F_FW_IQ_CMD_FL0CONGEN); 3107 } 3108 c.fl0dcaen_to_fl0cidxfthresh = 3109 htobe16(V_FW_IQ_CMD_FL0FBMIN(chip_id(sc) <= CHELSIO_T5 ? 3110 X_FETCHBURSTMIN_128B : X_FETCHBURSTMIN_64B) | 3111 V_FW_IQ_CMD_FL0FBMAX(chip_id(sc) <= CHELSIO_T5 ? 3112 X_FETCHBURSTMAX_512B : X_FETCHBURSTMAX_256B)); 3113 c.fl0size = htobe16(fl->qsize); 3114 c.fl0addr = htobe64(fl->ba); 3115 } 3116 3117 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3118 if (rc != 0) { 3119 device_printf(sc->dev, 3120 "failed to create ingress queue: %d\n", rc); 3121 return (rc); 3122 } 3123 3124 iq->cidx = 0; 3125 iq->gen = F_RSPD_GEN; 3126 iq->intr_next = iq->intr_params; 3127 iq->cntxt_id = be16toh(c.iqid); 3128 iq->abs_id = be16toh(c.physiqid); 3129 iq->flags |= IQ_ALLOCATED; 3130 3131 cntxt_id = iq->cntxt_id - sc->sge.iq_start; 3132 if (cntxt_id >= sc->sge.niq) { 3133 panic ("%s: iq->cntxt_id (%d) more than the max (%d)", __func__, 3134 cntxt_id, sc->sge.niq - 1); 3135 } 3136 sc->sge.iqmap[cntxt_id] = iq; 3137 3138 if (fl) { 3139 u_int qid; 3140 3141 iq->flags |= IQ_HAS_FL; 3142 fl->cntxt_id = be16toh(c.fl0id); 3143 fl->pidx = fl->cidx = 0; 3144 3145 cntxt_id = fl->cntxt_id - sc->sge.eq_start; 3146 if (cntxt_id >= sc->sge.neq) { 3147 panic("%s: fl->cntxt_id (%d) more than the max (%d)", 3148 __func__, cntxt_id, sc->sge.neq - 1); 3149 } 3150 sc->sge.eqmap[cntxt_id] = (void *)fl; 3151 3152 qid = fl->cntxt_id; 3153 if (isset(&sc->doorbells, DOORBELL_UDB)) { 3154 uint32_t s_qpp = sc->params.sge.eq_s_qpp; 3155 uint32_t mask = (1 << s_qpp) - 1; 3156 volatile uint8_t *udb; 3157 3158 udb = sc->udbs_base + UDBS_DB_OFFSET; 3159 udb += (qid >> s_qpp) << PAGE_SHIFT; 3160 qid &= mask; 3161 if (qid < PAGE_SIZE / UDBS_SEG_SIZE) { 3162 udb += qid << UDBS_SEG_SHIFT; 3163 qid = 0; 3164 } 3165 fl->udb = (volatile void *)udb; 3166 } 3167 fl->dbval = V_QID(qid) | sc->chip_params->sge_fl_db; 3168 3169 FL_LOCK(fl); 3170 /* Enough to make sure the SGE doesn't think it's starved */ 3171 refill_fl(sc, fl, fl->lowat); 3172 FL_UNLOCK(fl); 3173 } 3174 3175 if (chip_id(sc) >= CHELSIO_T5 && !(sc->flags & IS_VF) && cong >= 0) { 3176 uint32_t param, val; 3177 3178 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 3179 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) | 3180 V_FW_PARAMS_PARAM_YZ(iq->cntxt_id); 3181 if (cong == 0) 3182 val = 1 << 19; 3183 else { 3184 val = 2 << 19; 3185 for (i = 0; i < 4; i++) { 3186 if (cong & (1 << i)) 3187 val |= 1 << (i << 2); 3188 } 3189 } 3190 3191 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 3192 if (rc != 0) { 3193 /* report error but carry on */ 3194 device_printf(sc->dev, 3195 "failed to set congestion manager context for " 3196 "ingress queue %d: %d\n", iq->cntxt_id, rc); 3197 } 3198 } 3199 3200 /* Enable IQ interrupts */ 3201 atomic_store_rel_int(&iq->state, IQS_IDLE); 3202 t4_write_reg(sc, sc->sge_gts_reg, V_SEINTARM(iq->intr_params) | 3203 V_INGRESSQID(iq->cntxt_id)); 3204 3205 return (0); 3206 } 3207 3208 static int 3209 free_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl) 3210 { 3211 int rc; 3212 struct adapter *sc = iq->adapter; 3213 device_t dev; 3214 3215 if (sc == NULL) 3216 return (0); /* nothing to do */ 3217 3218 dev = vi ? vi->dev : sc->dev; 3219 3220 if (iq->flags & IQ_ALLOCATED) { 3221 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0, 3222 FW_IQ_TYPE_FL_INT_CAP, iq->cntxt_id, 3223 fl ? fl->cntxt_id : 0xffff, 0xffff); 3224 if (rc != 0) { 3225 device_printf(dev, 3226 "failed to free queue %p: %d\n", iq, rc); 3227 return (rc); 3228 } 3229 iq->flags &= ~IQ_ALLOCATED; 3230 } 3231 3232 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, iq->desc); 3233 3234 bzero(iq, sizeof(*iq)); 3235 3236 if (fl) { 3237 free_ring(sc, fl->desc_tag, fl->desc_map, fl->ba, 3238 fl->desc); 3239 3240 if (fl->sdesc) 3241 free_fl_sdesc(sc, fl); 3242 3243 if (mtx_initialized(&fl->fl_lock)) 3244 mtx_destroy(&fl->fl_lock); 3245 3246 bzero(fl, sizeof(*fl)); 3247 } 3248 3249 return (0); 3250 } 3251 3252 static void 3253 add_iq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid, 3254 struct sge_iq *iq) 3255 { 3256 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3257 3258 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, &iq->ba, 3259 "bus address of descriptor ring"); 3260 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3261 iq->qsize * IQ_ESIZE, "descriptor ring size in bytes"); 3262 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "abs_id", 3263 CTLTYPE_INT | CTLFLAG_RD, &iq->abs_id, 0, sysctl_uint16, "I", 3264 "absolute id of the queue"); 3265 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 3266 CTLTYPE_INT | CTLFLAG_RD, &iq->cntxt_id, 0, sysctl_uint16, "I", 3267 "SGE context id of the queue"); 3268 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx", 3269 CTLTYPE_INT | CTLFLAG_RD, &iq->cidx, 0, sysctl_uint16, "I", 3270 "consumer index"); 3271 } 3272 3273 static void 3274 add_fl_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx, 3275 struct sysctl_oid *oid, struct sge_fl *fl) 3276 { 3277 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3278 3279 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL, 3280 "freelist"); 3281 children = SYSCTL_CHILDREN(oid); 3282 3283 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, 3284 &fl->ba, "bus address of descriptor ring"); 3285 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3286 fl->sidx * EQ_ESIZE + sc->params.sge.spg_len, 3287 "desc ring size in bytes"); 3288 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 3289 CTLTYPE_INT | CTLFLAG_RD, &fl->cntxt_id, 0, sysctl_uint16, "I", 3290 "SGE context id of the freelist"); 3291 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "padding", CTLFLAG_RD, NULL, 3292 fl_pad ? 1 : 0, "padding enabled"); 3293 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "packing", CTLFLAG_RD, NULL, 3294 fl->flags & FL_BUF_PACKING ? 1 : 0, "packing enabled"); 3295 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &fl->cidx, 3296 0, "consumer index"); 3297 if (fl->flags & FL_BUF_PACKING) { 3298 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rx_offset", 3299 CTLFLAG_RD, &fl->rx_offset, 0, "packing rx offset"); 3300 } 3301 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &fl->pidx, 3302 0, "producer index"); 3303 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_allocated", 3304 CTLFLAG_RD, &fl->mbuf_allocated, "# of mbuf allocated"); 3305 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_inlined", 3306 CTLFLAG_RD, &fl->mbuf_inlined, "# of mbuf inlined in clusters"); 3307 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_allocated", 3308 CTLFLAG_RD, &fl->cl_allocated, "# of clusters allocated"); 3309 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_recycled", 3310 CTLFLAG_RD, &fl->cl_recycled, "# of clusters recycled"); 3311 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_fast_recycled", 3312 CTLFLAG_RD, &fl->cl_fast_recycled, "# of clusters recycled (fast)"); 3313 } 3314 3315 static int 3316 alloc_fwq(struct adapter *sc) 3317 { 3318 int rc, intr_idx; 3319 struct sge_iq *fwq = &sc->sge.fwq; 3320 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev); 3321 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3322 3323 init_iq(fwq, sc, 0, 0, FW_IQ_QSIZE); 3324 if (sc->flags & IS_VF) 3325 intr_idx = 0; 3326 else 3327 intr_idx = sc->intr_count > 1 ? 1 : 0; 3328 rc = alloc_iq_fl(&sc->port[0]->vi[0], fwq, NULL, intr_idx, -1); 3329 if (rc != 0) { 3330 device_printf(sc->dev, 3331 "failed to create firmware event queue: %d\n", rc); 3332 return (rc); 3333 } 3334 3335 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "fwq", CTLFLAG_RD, 3336 NULL, "firmware event queue"); 3337 add_iq_sysctls(&sc->ctx, oid, fwq); 3338 3339 return (0); 3340 } 3341 3342 static int 3343 free_fwq(struct adapter *sc) 3344 { 3345 return free_iq_fl(NULL, &sc->sge.fwq, NULL); 3346 } 3347 3348 static int 3349 alloc_ctrlq(struct adapter *sc, struct sge_wrq *ctrlq, int idx, 3350 struct sysctl_oid *oid) 3351 { 3352 int rc; 3353 char name[16]; 3354 struct sysctl_oid_list *children; 3355 3356 snprintf(name, sizeof(name), "%s ctrlq%d", device_get_nameunit(sc->dev), 3357 idx); 3358 init_eq(sc, &ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE, sc->port[idx]->tx_chan, 3359 sc->sge.fwq.cntxt_id, name); 3360 3361 children = SYSCTL_CHILDREN(oid); 3362 snprintf(name, sizeof(name), "%d", idx); 3363 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, name, CTLFLAG_RD, 3364 NULL, "ctrl queue"); 3365 rc = alloc_wrq(sc, NULL, ctrlq, oid); 3366 3367 return (rc); 3368 } 3369 3370 int 3371 tnl_cong(struct port_info *pi, int drop) 3372 { 3373 3374 if (drop == -1) 3375 return (-1); 3376 else if (drop == 1) 3377 return (0); 3378 else 3379 return (pi->rx_e_chan_map); 3380 } 3381 3382 static int 3383 alloc_rxq(struct vi_info *vi, struct sge_rxq *rxq, int intr_idx, int idx, 3384 struct sysctl_oid *oid) 3385 { 3386 int rc; 3387 struct adapter *sc = vi->pi->adapter; 3388 struct sysctl_oid_list *children; 3389 char name[16]; 3390 3391 rc = alloc_iq_fl(vi, &rxq->iq, &rxq->fl, intr_idx, 3392 tnl_cong(vi->pi, cong_drop)); 3393 if (rc != 0) 3394 return (rc); 3395 3396 if (idx == 0) 3397 sc->sge.iq_base = rxq->iq.abs_id - rxq->iq.cntxt_id; 3398 else 3399 KASSERT(rxq->iq.cntxt_id + sc->sge.iq_base == rxq->iq.abs_id, 3400 ("iq_base mismatch")); 3401 KASSERT(sc->sge.iq_base == 0 || sc->flags & IS_VF, 3402 ("PF with non-zero iq_base")); 3403 3404 /* 3405 * The freelist is just barely above the starvation threshold right now, 3406 * fill it up a bit more. 3407 */ 3408 FL_LOCK(&rxq->fl); 3409 refill_fl(sc, &rxq->fl, 128); 3410 FL_UNLOCK(&rxq->fl); 3411 3412 #if defined(INET) || defined(INET6) 3413 rc = tcp_lro_init_args(&rxq->lro, vi->ifp, lro_entries, lro_mbufs); 3414 if (rc != 0) 3415 return (rc); 3416 MPASS(rxq->lro.ifp == vi->ifp); /* also indicates LRO init'ed */ 3417 3418 if (vi->ifp->if_capenable & IFCAP_LRO) 3419 rxq->iq.flags |= IQ_LRO_ENABLED; 3420 #endif 3421 rxq->ifp = vi->ifp; 3422 3423 children = SYSCTL_CHILDREN(oid); 3424 3425 snprintf(name, sizeof(name), "%d", idx); 3426 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 3427 NULL, "rx queue"); 3428 children = SYSCTL_CHILDREN(oid); 3429 3430 add_iq_sysctls(&vi->ctx, oid, &rxq->iq); 3431 #if defined(INET) || defined(INET6) 3432 SYSCTL_ADD_U64(&vi->ctx, children, OID_AUTO, "lro_queued", CTLFLAG_RD, 3433 &rxq->lro.lro_queued, 0, NULL); 3434 SYSCTL_ADD_U64(&vi->ctx, children, OID_AUTO, "lro_flushed", CTLFLAG_RD, 3435 &rxq->lro.lro_flushed, 0, NULL); 3436 #endif 3437 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "rxcsum", CTLFLAG_RD, 3438 &rxq->rxcsum, "# of times hardware assisted with checksum"); 3439 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_extraction", 3440 CTLFLAG_RD, &rxq->vlan_extraction, 3441 "# of times hardware extracted 802.1Q tag"); 3442 3443 add_fl_sysctls(sc, &vi->ctx, oid, &rxq->fl); 3444 3445 return (rc); 3446 } 3447 3448 static int 3449 free_rxq(struct vi_info *vi, struct sge_rxq *rxq) 3450 { 3451 int rc; 3452 3453 #if defined(INET) || defined(INET6) 3454 if (rxq->lro.ifp) { 3455 tcp_lro_free(&rxq->lro); 3456 rxq->lro.ifp = NULL; 3457 } 3458 #endif 3459 3460 rc = free_iq_fl(vi, &rxq->iq, &rxq->fl); 3461 if (rc == 0) 3462 bzero(rxq, sizeof(*rxq)); 3463 3464 return (rc); 3465 } 3466 3467 #ifdef TCP_OFFLOAD 3468 static int 3469 alloc_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq, 3470 int intr_idx, int idx, struct sysctl_oid *oid) 3471 { 3472 struct port_info *pi = vi->pi; 3473 int rc; 3474 struct sysctl_oid_list *children; 3475 char name[16]; 3476 3477 rc = alloc_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl, intr_idx, 0); 3478 if (rc != 0) 3479 return (rc); 3480 3481 children = SYSCTL_CHILDREN(oid); 3482 3483 snprintf(name, sizeof(name), "%d", idx); 3484 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 3485 NULL, "rx queue"); 3486 add_iq_sysctls(&vi->ctx, oid, &ofld_rxq->iq); 3487 add_fl_sysctls(pi->adapter, &vi->ctx, oid, &ofld_rxq->fl); 3488 3489 return (rc); 3490 } 3491 3492 static int 3493 free_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq) 3494 { 3495 int rc; 3496 3497 rc = free_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl); 3498 if (rc == 0) 3499 bzero(ofld_rxq, sizeof(*ofld_rxq)); 3500 3501 return (rc); 3502 } 3503 #endif 3504 3505 #ifdef DEV_NETMAP 3506 static int 3507 alloc_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq, int intr_idx, 3508 int idx, struct sysctl_oid *oid) 3509 { 3510 int rc; 3511 struct sysctl_oid_list *children; 3512 struct sysctl_ctx_list *ctx; 3513 char name[16]; 3514 size_t len; 3515 struct adapter *sc = vi->pi->adapter; 3516 struct netmap_adapter *na = NA(vi->ifp); 3517 3518 MPASS(na != NULL); 3519 3520 len = vi->qsize_rxq * IQ_ESIZE; 3521 rc = alloc_ring(sc, len, &nm_rxq->iq_desc_tag, &nm_rxq->iq_desc_map, 3522 &nm_rxq->iq_ba, (void **)&nm_rxq->iq_desc); 3523 if (rc != 0) 3524 return (rc); 3525 3526 len = na->num_rx_desc * EQ_ESIZE + sc->params.sge.spg_len; 3527 rc = alloc_ring(sc, len, &nm_rxq->fl_desc_tag, &nm_rxq->fl_desc_map, 3528 &nm_rxq->fl_ba, (void **)&nm_rxq->fl_desc); 3529 if (rc != 0) 3530 return (rc); 3531 3532 nm_rxq->vi = vi; 3533 nm_rxq->nid = idx; 3534 nm_rxq->iq_cidx = 0; 3535 nm_rxq->iq_sidx = vi->qsize_rxq - sc->params.sge.spg_len / IQ_ESIZE; 3536 nm_rxq->iq_gen = F_RSPD_GEN; 3537 nm_rxq->fl_pidx = nm_rxq->fl_cidx = 0; 3538 nm_rxq->fl_sidx = na->num_rx_desc; 3539 nm_rxq->intr_idx = intr_idx; 3540 nm_rxq->iq_cntxt_id = INVALID_NM_RXQ_CNTXT_ID; 3541 3542 ctx = &vi->ctx; 3543 children = SYSCTL_CHILDREN(oid); 3544 3545 snprintf(name, sizeof(name), "%d", idx); 3546 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, name, CTLFLAG_RD, NULL, 3547 "rx queue"); 3548 children = SYSCTL_CHILDREN(oid); 3549 3550 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "abs_id", 3551 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_abs_id, 0, sysctl_uint16, 3552 "I", "absolute id of the queue"); 3553 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 3554 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cntxt_id, 0, sysctl_uint16, 3555 "I", "SGE context id of the queue"); 3556 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx", 3557 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cidx, 0, sysctl_uint16, "I", 3558 "consumer index"); 3559 3560 children = SYSCTL_CHILDREN(oid); 3561 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL, 3562 "freelist"); 3563 children = SYSCTL_CHILDREN(oid); 3564 3565 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 3566 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->fl_cntxt_id, 0, sysctl_uint16, 3567 "I", "SGE context id of the freelist"); 3568 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, 3569 &nm_rxq->fl_cidx, 0, "consumer index"); 3570 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, 3571 &nm_rxq->fl_pidx, 0, "producer index"); 3572 3573 return (rc); 3574 } 3575 3576 3577 static int 3578 free_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq) 3579 { 3580 struct adapter *sc = vi->pi->adapter; 3581 3582 if (vi->flags & VI_INIT_DONE) 3583 MPASS(nm_rxq->iq_cntxt_id == INVALID_NM_RXQ_CNTXT_ID); 3584 else 3585 MPASS(nm_rxq->iq_cntxt_id == 0); 3586 3587 free_ring(sc, nm_rxq->iq_desc_tag, nm_rxq->iq_desc_map, nm_rxq->iq_ba, 3588 nm_rxq->iq_desc); 3589 free_ring(sc, nm_rxq->fl_desc_tag, nm_rxq->fl_desc_map, nm_rxq->fl_ba, 3590 nm_rxq->fl_desc); 3591 3592 return (0); 3593 } 3594 3595 static int 3596 alloc_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq, int iqidx, int idx, 3597 struct sysctl_oid *oid) 3598 { 3599 int rc; 3600 size_t len; 3601 struct port_info *pi = vi->pi; 3602 struct adapter *sc = pi->adapter; 3603 struct netmap_adapter *na = NA(vi->ifp); 3604 char name[16]; 3605 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3606 3607 len = na->num_tx_desc * EQ_ESIZE + sc->params.sge.spg_len; 3608 rc = alloc_ring(sc, len, &nm_txq->desc_tag, &nm_txq->desc_map, 3609 &nm_txq->ba, (void **)&nm_txq->desc); 3610 if (rc) 3611 return (rc); 3612 3613 nm_txq->pidx = nm_txq->cidx = 0; 3614 nm_txq->sidx = na->num_tx_desc; 3615 nm_txq->nid = idx; 3616 nm_txq->iqidx = iqidx; 3617 nm_txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) | 3618 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(G_FW_VIID_PFN(vi->viid)) | 3619 V_TXPKT_VF(G_FW_VIID_VIN(vi->viid)) | 3620 V_TXPKT_VF_VLD(G_FW_VIID_VIVLD(vi->viid))); 3621 nm_txq->cntxt_id = INVALID_NM_TXQ_CNTXT_ID; 3622 3623 snprintf(name, sizeof(name), "%d", idx); 3624 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 3625 NULL, "netmap tx queue"); 3626 children = SYSCTL_CHILDREN(oid); 3627 3628 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 3629 &nm_txq->cntxt_id, 0, "SGE context id of the queue"); 3630 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx", 3631 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->cidx, 0, sysctl_uint16, "I", 3632 "consumer index"); 3633 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "pidx", 3634 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->pidx, 0, sysctl_uint16, "I", 3635 "producer index"); 3636 3637 return (rc); 3638 } 3639 3640 static int 3641 free_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq) 3642 { 3643 struct adapter *sc = vi->pi->adapter; 3644 3645 if (vi->flags & VI_INIT_DONE) 3646 MPASS(nm_txq->cntxt_id == INVALID_NM_TXQ_CNTXT_ID); 3647 else 3648 MPASS(nm_txq->cntxt_id == 0); 3649 3650 free_ring(sc, nm_txq->desc_tag, nm_txq->desc_map, nm_txq->ba, 3651 nm_txq->desc); 3652 3653 return (0); 3654 } 3655 #endif 3656 3657 /* 3658 * Returns a reasonable automatic cidx flush threshold for a given queue size. 3659 */ 3660 static u_int 3661 qsize_to_fthresh(int qsize) 3662 { 3663 u_int fthresh; 3664 3665 while (!powerof2(qsize)) 3666 qsize++; 3667 fthresh = ilog2(qsize); 3668 if (fthresh > X_CIDXFLUSHTHRESH_128) 3669 fthresh = X_CIDXFLUSHTHRESH_128; 3670 3671 return (fthresh); 3672 } 3673 3674 static int 3675 ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq) 3676 { 3677 int rc, cntxt_id; 3678 struct fw_eq_ctrl_cmd c; 3679 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 3680 3681 bzero(&c, sizeof(c)); 3682 3683 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | F_FW_CMD_REQUEST | 3684 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_CTRL_CMD_PFN(sc->pf) | 3685 V_FW_EQ_CTRL_CMD_VFN(0)); 3686 c.alloc_to_len16 = htobe32(F_FW_EQ_CTRL_CMD_ALLOC | 3687 F_FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c)); 3688 c.cmpliqid_eqid = htonl(V_FW_EQ_CTRL_CMD_CMPLIQID(eq->iqid)); 3689 c.physeqid_pkd = htobe32(0); 3690 c.fetchszm_to_iqid = 3691 htobe32(V_FW_EQ_CTRL_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 3692 V_FW_EQ_CTRL_CMD_PCIECHN(eq->tx_chan) | 3693 F_FW_EQ_CTRL_CMD_FETCHRO | V_FW_EQ_CTRL_CMD_IQID(eq->iqid)); 3694 c.dcaen_to_eqsize = 3695 htobe32(V_FW_EQ_CTRL_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 3696 V_FW_EQ_CTRL_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 3697 V_FW_EQ_CTRL_CMD_CIDXFTHRESH(qsize_to_fthresh(qsize)) | 3698 V_FW_EQ_CTRL_CMD_EQSIZE(qsize)); 3699 c.eqaddr = htobe64(eq->ba); 3700 3701 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3702 if (rc != 0) { 3703 device_printf(sc->dev, 3704 "failed to create control queue %d: %d\n", eq->tx_chan, rc); 3705 return (rc); 3706 } 3707 eq->flags |= EQ_ALLOCATED; 3708 3709 eq->cntxt_id = G_FW_EQ_CTRL_CMD_EQID(be32toh(c.cmpliqid_eqid)); 3710 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 3711 if (cntxt_id >= sc->sge.neq) 3712 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 3713 cntxt_id, sc->sge.neq - 1); 3714 sc->sge.eqmap[cntxt_id] = eq; 3715 3716 return (rc); 3717 } 3718 3719 static int 3720 eth_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 3721 { 3722 int rc, cntxt_id; 3723 struct fw_eq_eth_cmd c; 3724 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 3725 3726 bzero(&c, sizeof(c)); 3727 3728 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST | 3729 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) | 3730 V_FW_EQ_ETH_CMD_VFN(0)); 3731 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC | 3732 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c)); 3733 c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE | 3734 F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(vi->viid)); 3735 c.fetchszm_to_iqid = 3736 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) | 3737 V_FW_EQ_ETH_CMD_PCIECHN(eq->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO | 3738 V_FW_EQ_ETH_CMD_IQID(eq->iqid)); 3739 c.dcaen_to_eqsize = htobe32(V_FW_EQ_ETH_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 3740 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 3741 V_FW_EQ_ETH_CMD_EQSIZE(qsize)); 3742 c.eqaddr = htobe64(eq->ba); 3743 3744 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3745 if (rc != 0) { 3746 device_printf(vi->dev, 3747 "failed to create Ethernet egress queue: %d\n", rc); 3748 return (rc); 3749 } 3750 eq->flags |= EQ_ALLOCATED; 3751 3752 eq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd)); 3753 eq->abs_id = G_FW_EQ_ETH_CMD_PHYSEQID(be32toh(c.physeqid_pkd)); 3754 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 3755 if (cntxt_id >= sc->sge.neq) 3756 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 3757 cntxt_id, sc->sge.neq - 1); 3758 sc->sge.eqmap[cntxt_id] = eq; 3759 3760 return (rc); 3761 } 3762 3763 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 3764 static int 3765 ofld_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 3766 { 3767 int rc, cntxt_id; 3768 struct fw_eq_ofld_cmd c; 3769 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 3770 3771 bzero(&c, sizeof(c)); 3772 3773 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | F_FW_CMD_REQUEST | 3774 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_OFLD_CMD_PFN(sc->pf) | 3775 V_FW_EQ_OFLD_CMD_VFN(0)); 3776 c.alloc_to_len16 = htonl(F_FW_EQ_OFLD_CMD_ALLOC | 3777 F_FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c)); 3778 c.fetchszm_to_iqid = 3779 htonl(V_FW_EQ_OFLD_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 3780 V_FW_EQ_OFLD_CMD_PCIECHN(eq->tx_chan) | 3781 F_FW_EQ_OFLD_CMD_FETCHRO | V_FW_EQ_OFLD_CMD_IQID(eq->iqid)); 3782 c.dcaen_to_eqsize = 3783 htobe32(V_FW_EQ_OFLD_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 3784 V_FW_EQ_OFLD_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 3785 V_FW_EQ_OFLD_CMD_CIDXFTHRESH(qsize_to_fthresh(qsize)) | 3786 V_FW_EQ_OFLD_CMD_EQSIZE(qsize)); 3787 c.eqaddr = htobe64(eq->ba); 3788 3789 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3790 if (rc != 0) { 3791 device_printf(vi->dev, 3792 "failed to create egress queue for TCP offload: %d\n", rc); 3793 return (rc); 3794 } 3795 eq->flags |= EQ_ALLOCATED; 3796 3797 eq->cntxt_id = G_FW_EQ_OFLD_CMD_EQID(be32toh(c.eqid_pkd)); 3798 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 3799 if (cntxt_id >= sc->sge.neq) 3800 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 3801 cntxt_id, sc->sge.neq - 1); 3802 sc->sge.eqmap[cntxt_id] = eq; 3803 3804 return (rc); 3805 } 3806 #endif 3807 3808 static int 3809 alloc_eq(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 3810 { 3811 int rc, qsize; 3812 size_t len; 3813 3814 mtx_init(&eq->eq_lock, eq->lockname, NULL, MTX_DEF); 3815 3816 qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 3817 len = qsize * EQ_ESIZE; 3818 rc = alloc_ring(sc, len, &eq->desc_tag, &eq->desc_map, 3819 &eq->ba, (void **)&eq->desc); 3820 if (rc) 3821 return (rc); 3822 3823 eq->pidx = eq->cidx = eq->dbidx = 0; 3824 /* Note that equeqidx is not used with sge_wrq (OFLD/CTRL) queues. */ 3825 eq->equeqidx = 0; 3826 eq->doorbells = sc->doorbells; 3827 3828 switch (eq->flags & EQ_TYPEMASK) { 3829 case EQ_CTRL: 3830 rc = ctrl_eq_alloc(sc, eq); 3831 break; 3832 3833 case EQ_ETH: 3834 rc = eth_eq_alloc(sc, vi, eq); 3835 break; 3836 3837 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 3838 case EQ_OFLD: 3839 rc = ofld_eq_alloc(sc, vi, eq); 3840 break; 3841 #endif 3842 3843 default: 3844 panic("%s: invalid eq type %d.", __func__, 3845 eq->flags & EQ_TYPEMASK); 3846 } 3847 if (rc != 0) { 3848 device_printf(sc->dev, 3849 "failed to allocate egress queue(%d): %d\n", 3850 eq->flags & EQ_TYPEMASK, rc); 3851 } 3852 3853 if (isset(&eq->doorbells, DOORBELL_UDB) || 3854 isset(&eq->doorbells, DOORBELL_UDBWC) || 3855 isset(&eq->doorbells, DOORBELL_WCWR)) { 3856 uint32_t s_qpp = sc->params.sge.eq_s_qpp; 3857 uint32_t mask = (1 << s_qpp) - 1; 3858 volatile uint8_t *udb; 3859 3860 udb = sc->udbs_base + UDBS_DB_OFFSET; 3861 udb += (eq->cntxt_id >> s_qpp) << PAGE_SHIFT; /* pg offset */ 3862 eq->udb_qid = eq->cntxt_id & mask; /* id in page */ 3863 if (eq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE) 3864 clrbit(&eq->doorbells, DOORBELL_WCWR); 3865 else { 3866 udb += eq->udb_qid << UDBS_SEG_SHIFT; /* seg offset */ 3867 eq->udb_qid = 0; 3868 } 3869 eq->udb = (volatile void *)udb; 3870 } 3871 3872 return (rc); 3873 } 3874 3875 static int 3876 free_eq(struct adapter *sc, struct sge_eq *eq) 3877 { 3878 int rc; 3879 3880 if (eq->flags & EQ_ALLOCATED) { 3881 switch (eq->flags & EQ_TYPEMASK) { 3882 case EQ_CTRL: 3883 rc = -t4_ctrl_eq_free(sc, sc->mbox, sc->pf, 0, 3884 eq->cntxt_id); 3885 break; 3886 3887 case EQ_ETH: 3888 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0, 3889 eq->cntxt_id); 3890 break; 3891 3892 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 3893 case EQ_OFLD: 3894 rc = -t4_ofld_eq_free(sc, sc->mbox, sc->pf, 0, 3895 eq->cntxt_id); 3896 break; 3897 #endif 3898 3899 default: 3900 panic("%s: invalid eq type %d.", __func__, 3901 eq->flags & EQ_TYPEMASK); 3902 } 3903 if (rc != 0) { 3904 device_printf(sc->dev, 3905 "failed to free egress queue (%d): %d\n", 3906 eq->flags & EQ_TYPEMASK, rc); 3907 return (rc); 3908 } 3909 eq->flags &= ~EQ_ALLOCATED; 3910 } 3911 3912 free_ring(sc, eq->desc_tag, eq->desc_map, eq->ba, eq->desc); 3913 3914 if (mtx_initialized(&eq->eq_lock)) 3915 mtx_destroy(&eq->eq_lock); 3916 3917 bzero(eq, sizeof(*eq)); 3918 return (0); 3919 } 3920 3921 static int 3922 alloc_wrq(struct adapter *sc, struct vi_info *vi, struct sge_wrq *wrq, 3923 struct sysctl_oid *oid) 3924 { 3925 int rc; 3926 struct sysctl_ctx_list *ctx = vi ? &vi->ctx : &sc->ctx; 3927 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3928 3929 rc = alloc_eq(sc, vi, &wrq->eq); 3930 if (rc) 3931 return (rc); 3932 3933 wrq->adapter = sc; 3934 TASK_INIT(&wrq->wrq_tx_task, 0, wrq_tx_drain, wrq); 3935 TAILQ_INIT(&wrq->incomplete_wrs); 3936 STAILQ_INIT(&wrq->wr_list); 3937 wrq->nwr_pending = 0; 3938 wrq->ndesc_needed = 0; 3939 3940 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, 3941 &wrq->eq.ba, "bus address of descriptor ring"); 3942 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3943 wrq->eq.sidx * EQ_ESIZE + sc->params.sge.spg_len, 3944 "desc ring size in bytes"); 3945 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 3946 &wrq->eq.cntxt_id, 0, "SGE context id of the queue"); 3947 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx", 3948 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.cidx, 0, sysctl_uint16, "I", 3949 "consumer index"); 3950 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pidx", 3951 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.pidx, 0, sysctl_uint16, "I", 3952 "producer index"); 3953 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL, 3954 wrq->eq.sidx, "status page index"); 3955 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_direct", CTLFLAG_RD, 3956 &wrq->tx_wrs_direct, "# of work requests (direct)"); 3957 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_copied", CTLFLAG_RD, 3958 &wrq->tx_wrs_copied, "# of work requests (copied)"); 3959 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_sspace", CTLFLAG_RD, 3960 &wrq->tx_wrs_ss, "# of work requests (copied from scratch space)"); 3961 3962 return (rc); 3963 } 3964 3965 static int 3966 free_wrq(struct adapter *sc, struct sge_wrq *wrq) 3967 { 3968 int rc; 3969 3970 rc = free_eq(sc, &wrq->eq); 3971 if (rc) 3972 return (rc); 3973 3974 bzero(wrq, sizeof(*wrq)); 3975 return (0); 3976 } 3977 3978 static int 3979 alloc_txq(struct vi_info *vi, struct sge_txq *txq, int idx, 3980 struct sysctl_oid *oid) 3981 { 3982 int rc; 3983 struct port_info *pi = vi->pi; 3984 struct adapter *sc = pi->adapter; 3985 struct sge_eq *eq = &txq->eq; 3986 char name[16]; 3987 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3988 3989 rc = mp_ring_alloc(&txq->r, eq->sidx, txq, eth_tx, can_resume_eth_tx, 3990 M_CXGBE, M_WAITOK); 3991 if (rc != 0) { 3992 device_printf(sc->dev, "failed to allocate mp_ring: %d\n", rc); 3993 return (rc); 3994 } 3995 3996 rc = alloc_eq(sc, vi, eq); 3997 if (rc != 0) { 3998 mp_ring_free(txq->r); 3999 txq->r = NULL; 4000 return (rc); 4001 } 4002 4003 /* Can't fail after this point. */ 4004 4005 if (idx == 0) 4006 sc->sge.eq_base = eq->abs_id - eq->cntxt_id; 4007 else 4008 KASSERT(eq->cntxt_id + sc->sge.eq_base == eq->abs_id, 4009 ("eq_base mismatch")); 4010 KASSERT(sc->sge.eq_base == 0 || sc->flags & IS_VF, 4011 ("PF with non-zero eq_base")); 4012 4013 TASK_INIT(&txq->tx_reclaim_task, 0, tx_reclaim, eq); 4014 txq->ifp = vi->ifp; 4015 txq->gl = sglist_alloc(TX_SGL_SEGS, M_WAITOK); 4016 if (sc->flags & IS_VF) 4017 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) | 4018 V_TXPKT_INTF(pi->tx_chan)); 4019 else 4020 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) | 4021 V_TXPKT_INTF(pi->tx_chan) | 4022 V_TXPKT_PF(G_FW_VIID_PFN(vi->viid)) | 4023 V_TXPKT_VF(G_FW_VIID_VIN(vi->viid)) | 4024 V_TXPKT_VF_VLD(G_FW_VIID_VIVLD(vi->viid))); 4025 txq->tc_idx = -1; 4026 txq->sdesc = malloc(eq->sidx * sizeof(struct tx_sdesc), M_CXGBE, 4027 M_ZERO | M_WAITOK); 4028 4029 snprintf(name, sizeof(name), "%d", idx); 4030 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 4031 NULL, "tx queue"); 4032 children = SYSCTL_CHILDREN(oid); 4033 4034 SYSCTL_ADD_UAUTO(&vi->ctx, children, OID_AUTO, "ba", CTLFLAG_RD, 4035 &eq->ba, "bus address of descriptor ring"); 4036 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 4037 eq->sidx * EQ_ESIZE + sc->params.sge.spg_len, 4038 "desc ring size in bytes"); 4039 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "abs_id", CTLFLAG_RD, 4040 &eq->abs_id, 0, "absolute id of the queue"); 4041 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 4042 &eq->cntxt_id, 0, "SGE context id of the queue"); 4043 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx", 4044 CTLTYPE_INT | CTLFLAG_RD, &eq->cidx, 0, sysctl_uint16, "I", 4045 "consumer index"); 4046 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "pidx", 4047 CTLTYPE_INT | CTLFLAG_RD, &eq->pidx, 0, sysctl_uint16, "I", 4048 "producer index"); 4049 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL, 4050 eq->sidx, "status page index"); 4051 4052 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "tc", 4053 CTLTYPE_INT | CTLFLAG_RW, vi, idx, sysctl_tc, "I", 4054 "traffic class (-1 means none)"); 4055 4056 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txcsum", CTLFLAG_RD, 4057 &txq->txcsum, "# of times hardware assisted with checksum"); 4058 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_insertion", 4059 CTLFLAG_RD, &txq->vlan_insertion, 4060 "# of times hardware inserted 802.1Q tag"); 4061 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "tso_wrs", CTLFLAG_RD, 4062 &txq->tso_wrs, "# of TSO work requests"); 4063 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "imm_wrs", CTLFLAG_RD, 4064 &txq->imm_wrs, "# of work requests with immediate data"); 4065 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "sgl_wrs", CTLFLAG_RD, 4066 &txq->sgl_wrs, "# of work requests with direct SGL"); 4067 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkt_wrs", CTLFLAG_RD, 4068 &txq->txpkt_wrs, "# of txpkt work requests (one pkt/WR)"); 4069 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_wrs", 4070 CTLFLAG_RD, &txq->txpkts0_wrs, 4071 "# of txpkts (type 0) work requests"); 4072 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_wrs", 4073 CTLFLAG_RD, &txq->txpkts1_wrs, 4074 "# of txpkts (type 1) work requests"); 4075 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_pkts", 4076 CTLFLAG_RD, &txq->txpkts0_pkts, 4077 "# of frames tx'd using type0 txpkts work requests"); 4078 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_pkts", 4079 CTLFLAG_RD, &txq->txpkts1_pkts, 4080 "# of frames tx'd using type1 txpkts work requests"); 4081 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "raw_wrs", CTLFLAG_RD, 4082 &txq->raw_wrs, "# of raw work requests (non-packets)"); 4083 4084 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_enqueues", 4085 CTLFLAG_RD, &txq->r->enqueues, 4086 "# of enqueues to the mp_ring for this queue"); 4087 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_drops", 4088 CTLFLAG_RD, &txq->r->drops, 4089 "# of drops in the mp_ring for this queue"); 4090 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_starts", 4091 CTLFLAG_RD, &txq->r->starts, 4092 "# of normal consumer starts in the mp_ring for this queue"); 4093 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_stalls", 4094 CTLFLAG_RD, &txq->r->stalls, 4095 "# of consumer stalls in the mp_ring for this queue"); 4096 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_restarts", 4097 CTLFLAG_RD, &txq->r->restarts, 4098 "# of consumer restarts in the mp_ring for this queue"); 4099 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_abdications", 4100 CTLFLAG_RD, &txq->r->abdications, 4101 "# of consumer abdications in the mp_ring for this queue"); 4102 4103 return (0); 4104 } 4105 4106 static int 4107 free_txq(struct vi_info *vi, struct sge_txq *txq) 4108 { 4109 int rc; 4110 struct adapter *sc = vi->pi->adapter; 4111 struct sge_eq *eq = &txq->eq; 4112 4113 rc = free_eq(sc, eq); 4114 if (rc) 4115 return (rc); 4116 4117 sglist_free(txq->gl); 4118 free(txq->sdesc, M_CXGBE); 4119 mp_ring_free(txq->r); 4120 4121 bzero(txq, sizeof(*txq)); 4122 return (0); 4123 } 4124 4125 static void 4126 oneseg_dma_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error) 4127 { 4128 bus_addr_t *ba = arg; 4129 4130 KASSERT(nseg == 1, 4131 ("%s meant for single segment mappings only.", __func__)); 4132 4133 *ba = error ? 0 : segs->ds_addr; 4134 } 4135 4136 static inline void 4137 ring_fl_db(struct adapter *sc, struct sge_fl *fl) 4138 { 4139 uint32_t n, v; 4140 4141 n = IDXDIFF(fl->pidx / 8, fl->dbidx, fl->sidx); 4142 MPASS(n > 0); 4143 4144 wmb(); 4145 v = fl->dbval | V_PIDX(n); 4146 if (fl->udb) 4147 *fl->udb = htole32(v); 4148 else 4149 t4_write_reg(sc, sc->sge_kdoorbell_reg, v); 4150 IDXINCR(fl->dbidx, n, fl->sidx); 4151 } 4152 4153 /* 4154 * Fills up the freelist by allocating up to 'n' buffers. Buffers that are 4155 * recycled do not count towards this allocation budget. 4156 * 4157 * Returns non-zero to indicate that this freelist should be added to the list 4158 * of starving freelists. 4159 */ 4160 static int 4161 refill_fl(struct adapter *sc, struct sge_fl *fl, int n) 4162 { 4163 __be64 *d; 4164 struct fl_sdesc *sd; 4165 uintptr_t pa; 4166 caddr_t cl; 4167 struct cluster_layout *cll; 4168 struct sw_zone_info *swz; 4169 struct cluster_metadata *clm; 4170 uint16_t max_pidx; 4171 uint16_t hw_cidx = fl->hw_cidx; /* stable snapshot */ 4172 4173 FL_LOCK_ASSERT_OWNED(fl); 4174 4175 /* 4176 * We always stop at the beginning of the hardware descriptor that's just 4177 * before the one with the hw cidx. This is to avoid hw pidx = hw cidx, 4178 * which would mean an empty freelist to the chip. 4179 */ 4180 max_pidx = __predict_false(hw_cidx == 0) ? fl->sidx - 1 : hw_cidx - 1; 4181 if (fl->pidx == max_pidx * 8) 4182 return (0); 4183 4184 d = &fl->desc[fl->pidx]; 4185 sd = &fl->sdesc[fl->pidx]; 4186 cll = &fl->cll_def; /* default layout */ 4187 swz = &sc->sge.sw_zone_info[cll->zidx]; 4188 4189 while (n > 0) { 4190 4191 if (sd->cl != NULL) { 4192 4193 if (sd->nmbuf == 0) { 4194 /* 4195 * Fast recycle without involving any atomics on 4196 * the cluster's metadata (if the cluster has 4197 * metadata). This happens when all frames 4198 * received in the cluster were small enough to 4199 * fit within a single mbuf each. 4200 */ 4201 fl->cl_fast_recycled++; 4202 #ifdef INVARIANTS 4203 clm = cl_metadata(sc, fl, &sd->cll, sd->cl); 4204 if (clm != NULL) 4205 MPASS(clm->refcount == 1); 4206 #endif 4207 goto recycled_fast; 4208 } 4209 4210 /* 4211 * Cluster is guaranteed to have metadata. Clusters 4212 * without metadata always take the fast recycle path 4213 * when they're recycled. 4214 */ 4215 clm = cl_metadata(sc, fl, &sd->cll, sd->cl); 4216 MPASS(clm != NULL); 4217 4218 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) { 4219 fl->cl_recycled++; 4220 counter_u64_add(extfree_rels, 1); 4221 goto recycled; 4222 } 4223 sd->cl = NULL; /* gave up my reference */ 4224 } 4225 MPASS(sd->cl == NULL); 4226 alloc: 4227 cl = uma_zalloc(swz->zone, M_NOWAIT); 4228 if (__predict_false(cl == NULL)) { 4229 if (cll == &fl->cll_alt || fl->cll_alt.zidx == -1 || 4230 fl->cll_def.zidx == fl->cll_alt.zidx) 4231 break; 4232 4233 /* fall back to the safe zone */ 4234 cll = &fl->cll_alt; 4235 swz = &sc->sge.sw_zone_info[cll->zidx]; 4236 goto alloc; 4237 } 4238 fl->cl_allocated++; 4239 n--; 4240 4241 pa = pmap_kextract((vm_offset_t)cl); 4242 pa += cll->region1; 4243 sd->cl = cl; 4244 sd->cll = *cll; 4245 *d = htobe64(pa | cll->hwidx); 4246 clm = cl_metadata(sc, fl, cll, cl); 4247 if (clm != NULL) { 4248 recycled: 4249 #ifdef INVARIANTS 4250 clm->sd = sd; 4251 #endif 4252 clm->refcount = 1; 4253 } 4254 sd->nmbuf = 0; 4255 recycled_fast: 4256 d++; 4257 sd++; 4258 if (__predict_false(++fl->pidx % 8 == 0)) { 4259 uint16_t pidx = fl->pidx / 8; 4260 4261 if (__predict_false(pidx == fl->sidx)) { 4262 fl->pidx = 0; 4263 pidx = 0; 4264 sd = fl->sdesc; 4265 d = fl->desc; 4266 } 4267 if (pidx == max_pidx) 4268 break; 4269 4270 if (IDXDIFF(pidx, fl->dbidx, fl->sidx) >= 4) 4271 ring_fl_db(sc, fl); 4272 } 4273 } 4274 4275 if (fl->pidx / 8 != fl->dbidx) 4276 ring_fl_db(sc, fl); 4277 4278 return (FL_RUNNING_LOW(fl) && !(fl->flags & FL_STARVING)); 4279 } 4280 4281 /* 4282 * Attempt to refill all starving freelists. 4283 */ 4284 static void 4285 refill_sfl(void *arg) 4286 { 4287 struct adapter *sc = arg; 4288 struct sge_fl *fl, *fl_temp; 4289 4290 mtx_assert(&sc->sfl_lock, MA_OWNED); 4291 TAILQ_FOREACH_SAFE(fl, &sc->sfl, link, fl_temp) { 4292 FL_LOCK(fl); 4293 refill_fl(sc, fl, 64); 4294 if (FL_NOT_RUNNING_LOW(fl) || fl->flags & FL_DOOMED) { 4295 TAILQ_REMOVE(&sc->sfl, fl, link); 4296 fl->flags &= ~FL_STARVING; 4297 } 4298 FL_UNLOCK(fl); 4299 } 4300 4301 if (!TAILQ_EMPTY(&sc->sfl)) 4302 callout_schedule(&sc->sfl_callout, hz / 5); 4303 } 4304 4305 static int 4306 alloc_fl_sdesc(struct sge_fl *fl) 4307 { 4308 4309 fl->sdesc = malloc(fl->sidx * 8 * sizeof(struct fl_sdesc), M_CXGBE, 4310 M_ZERO | M_WAITOK); 4311 4312 return (0); 4313 } 4314 4315 static void 4316 free_fl_sdesc(struct adapter *sc, struct sge_fl *fl) 4317 { 4318 struct fl_sdesc *sd; 4319 struct cluster_metadata *clm; 4320 struct cluster_layout *cll; 4321 int i; 4322 4323 sd = fl->sdesc; 4324 for (i = 0; i < fl->sidx * 8; i++, sd++) { 4325 if (sd->cl == NULL) 4326 continue; 4327 4328 cll = &sd->cll; 4329 clm = cl_metadata(sc, fl, cll, sd->cl); 4330 if (sd->nmbuf == 0) 4331 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl); 4332 else if (clm && atomic_fetchadd_int(&clm->refcount, -1) == 1) { 4333 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl); 4334 counter_u64_add(extfree_rels, 1); 4335 } 4336 sd->cl = NULL; 4337 } 4338 4339 free(fl->sdesc, M_CXGBE); 4340 fl->sdesc = NULL; 4341 } 4342 4343 static inline void 4344 get_pkt_gl(struct mbuf *m, struct sglist *gl) 4345 { 4346 int rc; 4347 4348 M_ASSERTPKTHDR(m); 4349 4350 sglist_reset(gl); 4351 rc = sglist_append_mbuf(gl, m); 4352 if (__predict_false(rc != 0)) { 4353 panic("%s: mbuf %p (%d segs) was vetted earlier but now fails " 4354 "with %d.", __func__, m, mbuf_nsegs(m), rc); 4355 } 4356 4357 KASSERT(gl->sg_nseg == mbuf_nsegs(m), 4358 ("%s: nsegs changed for mbuf %p from %d to %d", __func__, m, 4359 mbuf_nsegs(m), gl->sg_nseg)); 4360 KASSERT(gl->sg_nseg > 0 && 4361 gl->sg_nseg <= (needs_tso(m) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS), 4362 ("%s: %d segments, should have been 1 <= nsegs <= %d", __func__, 4363 gl->sg_nseg, needs_tso(m) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS)); 4364 } 4365 4366 /* 4367 * len16 for a txpkt WR with a GL. Includes the firmware work request header. 4368 */ 4369 static inline u_int 4370 txpkt_len16(u_int nsegs, u_int tso) 4371 { 4372 u_int n; 4373 4374 MPASS(nsegs > 0); 4375 4376 nsegs--; /* first segment is part of ulptx_sgl */ 4377 n = sizeof(struct fw_eth_tx_pkt_wr) + sizeof(struct cpl_tx_pkt_core) + 4378 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 4379 if (tso) 4380 n += sizeof(struct cpl_tx_pkt_lso_core); 4381 4382 return (howmany(n, 16)); 4383 } 4384 4385 /* 4386 * len16 for a txpkt_vm WR with a GL. Includes the firmware work 4387 * request header. 4388 */ 4389 static inline u_int 4390 txpkt_vm_len16(u_int nsegs, u_int tso) 4391 { 4392 u_int n; 4393 4394 MPASS(nsegs > 0); 4395 4396 nsegs--; /* first segment is part of ulptx_sgl */ 4397 n = sizeof(struct fw_eth_tx_pkt_vm_wr) + 4398 sizeof(struct cpl_tx_pkt_core) + 4399 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 4400 if (tso) 4401 n += sizeof(struct cpl_tx_pkt_lso_core); 4402 4403 return (howmany(n, 16)); 4404 } 4405 4406 /* 4407 * len16 for a txpkts type 0 WR with a GL. Does not include the firmware work 4408 * request header. 4409 */ 4410 static inline u_int 4411 txpkts0_len16(u_int nsegs) 4412 { 4413 u_int n; 4414 4415 MPASS(nsegs > 0); 4416 4417 nsegs--; /* first segment is part of ulptx_sgl */ 4418 n = sizeof(struct ulp_txpkt) + sizeof(struct ulptx_idata) + 4419 sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl) + 4420 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 4421 4422 return (howmany(n, 16)); 4423 } 4424 4425 /* 4426 * len16 for a txpkts type 1 WR with a GL. Does not include the firmware work 4427 * request header. 4428 */ 4429 static inline u_int 4430 txpkts1_len16(void) 4431 { 4432 u_int n; 4433 4434 n = sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl); 4435 4436 return (howmany(n, 16)); 4437 } 4438 4439 static inline u_int 4440 imm_payload(u_int ndesc) 4441 { 4442 u_int n; 4443 4444 n = ndesc * EQ_ESIZE - sizeof(struct fw_eth_tx_pkt_wr) - 4445 sizeof(struct cpl_tx_pkt_core); 4446 4447 return (n); 4448 } 4449 4450 /* 4451 * Write a VM txpkt WR for this packet to the hardware descriptors, update the 4452 * software descriptor, and advance the pidx. It is guaranteed that enough 4453 * descriptors are available. 4454 * 4455 * The return value is the # of hardware descriptors used. 4456 */ 4457 static u_int 4458 write_txpkt_vm_wr(struct adapter *sc, struct sge_txq *txq, 4459 struct fw_eth_tx_pkt_vm_wr *wr, struct mbuf *m0, u_int available) 4460 { 4461 struct sge_eq *eq = &txq->eq; 4462 struct tx_sdesc *txsd; 4463 struct cpl_tx_pkt_core *cpl; 4464 uint32_t ctrl; /* used in many unrelated places */ 4465 uint64_t ctrl1; 4466 int csum_type, len16, ndesc, pktlen, nsegs; 4467 caddr_t dst; 4468 4469 TXQ_LOCK_ASSERT_OWNED(txq); 4470 M_ASSERTPKTHDR(m0); 4471 MPASS(available > 0 && available < eq->sidx); 4472 4473 len16 = mbuf_len16(m0); 4474 nsegs = mbuf_nsegs(m0); 4475 pktlen = m0->m_pkthdr.len; 4476 ctrl = sizeof(struct cpl_tx_pkt_core); 4477 if (needs_tso(m0)) 4478 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 4479 ndesc = howmany(len16, EQ_ESIZE / 16); 4480 MPASS(ndesc <= available); 4481 4482 /* Firmware work request header */ 4483 MPASS(wr == (void *)&eq->desc[eq->pidx]); 4484 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_VM_WR) | 4485 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl)); 4486 4487 ctrl = V_FW_WR_LEN16(len16); 4488 wr->equiq_to_len16 = htobe32(ctrl); 4489 wr->r3[0] = 0; 4490 wr->r3[1] = 0; 4491 4492 /* 4493 * Copy over ethmacdst, ethmacsrc, ethtype, and vlantci. 4494 * vlantci is ignored unless the ethtype is 0x8100, so it's 4495 * simpler to always copy it rather than making it 4496 * conditional. Also, it seems that we do not have to set 4497 * vlantci or fake the ethtype when doing VLAN tag insertion. 4498 */ 4499 m_copydata(m0, 0, sizeof(struct ether_header) + 2, wr->ethmacdst); 4500 4501 csum_type = -1; 4502 if (needs_tso(m0)) { 4503 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1); 4504 4505 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 4506 m0->m_pkthdr.l4hlen > 0, 4507 ("%s: mbuf %p needs TSO but missing header lengths", 4508 __func__, m0)); 4509 4510 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE | 4511 F_LSO_LAST_SLICE | V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) 4512 | V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2); 4513 if (m0->m_pkthdr.l2hlen == sizeof(struct ether_vlan_header)) 4514 ctrl |= V_LSO_ETHHDR_LEN(1); 4515 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 4516 ctrl |= F_LSO_IPV6; 4517 4518 lso->lso_ctrl = htobe32(ctrl); 4519 lso->ipid_ofst = htobe16(0); 4520 lso->mss = htobe16(m0->m_pkthdr.tso_segsz); 4521 lso->seqno_offset = htobe32(0); 4522 lso->len = htobe32(pktlen); 4523 4524 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 4525 csum_type = TX_CSUM_TCPIP6; 4526 else 4527 csum_type = TX_CSUM_TCPIP; 4528 4529 cpl = (void *)(lso + 1); 4530 4531 txq->tso_wrs++; 4532 } else { 4533 if (m0->m_pkthdr.csum_flags & CSUM_IP_TCP) 4534 csum_type = TX_CSUM_TCPIP; 4535 else if (m0->m_pkthdr.csum_flags & CSUM_IP_UDP) 4536 csum_type = TX_CSUM_UDPIP; 4537 else if (m0->m_pkthdr.csum_flags & CSUM_IP6_TCP) 4538 csum_type = TX_CSUM_TCPIP6; 4539 else if (m0->m_pkthdr.csum_flags & CSUM_IP6_UDP) 4540 csum_type = TX_CSUM_UDPIP6; 4541 #if defined(INET) 4542 else if (m0->m_pkthdr.csum_flags & CSUM_IP) { 4543 /* 4544 * XXX: The firmware appears to stomp on the 4545 * fragment/flags field of the IP header when 4546 * using TX_CSUM_IP. Fall back to doing 4547 * software checksums. 4548 */ 4549 u_short *sump; 4550 struct mbuf *m; 4551 int offset; 4552 4553 m = m0; 4554 offset = 0; 4555 sump = m_advance(&m, &offset, m0->m_pkthdr.l2hlen + 4556 offsetof(struct ip, ip_sum)); 4557 *sump = in_cksum_skip(m0, m0->m_pkthdr.l2hlen + 4558 m0->m_pkthdr.l3hlen, m0->m_pkthdr.l2hlen); 4559 m0->m_pkthdr.csum_flags &= ~CSUM_IP; 4560 } 4561 #endif 4562 4563 cpl = (void *)(wr + 1); 4564 } 4565 4566 /* Checksum offload */ 4567 ctrl1 = 0; 4568 if (needs_l3_csum(m0) == 0) 4569 ctrl1 |= F_TXPKT_IPCSUM_DIS; 4570 if (csum_type >= 0) { 4571 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0, 4572 ("%s: mbuf %p needs checksum offload but missing header lengths", 4573 __func__, m0)); 4574 4575 if (chip_id(sc) <= CHELSIO_T5) { 4576 ctrl1 |= V_TXPKT_ETHHDR_LEN(m0->m_pkthdr.l2hlen - 4577 ETHER_HDR_LEN); 4578 } else { 4579 ctrl1 |= V_T6_TXPKT_ETHHDR_LEN(m0->m_pkthdr.l2hlen - 4580 ETHER_HDR_LEN); 4581 } 4582 ctrl1 |= V_TXPKT_IPHDR_LEN(m0->m_pkthdr.l3hlen); 4583 ctrl1 |= V_TXPKT_CSUM_TYPE(csum_type); 4584 } else 4585 ctrl1 |= F_TXPKT_L4CSUM_DIS; 4586 if (m0->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | 4587 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO)) 4588 txq->txcsum++; /* some hardware assistance provided */ 4589 4590 /* VLAN tag insertion */ 4591 if (needs_vlan_insertion(m0)) { 4592 ctrl1 |= F_TXPKT_VLAN_VLD | 4593 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 4594 txq->vlan_insertion++; 4595 } 4596 4597 /* CPL header */ 4598 cpl->ctrl0 = txq->cpl_ctrl0; 4599 cpl->pack = 0; 4600 cpl->len = htobe16(pktlen); 4601 cpl->ctrl1 = htobe64(ctrl1); 4602 4603 /* SGL */ 4604 dst = (void *)(cpl + 1); 4605 4606 /* 4607 * A packet using TSO will use up an entire descriptor for the 4608 * firmware work request header, LSO CPL, and TX_PKT_XT CPL. 4609 * If this descriptor is the last descriptor in the ring, wrap 4610 * around to the front of the ring explicitly for the start of 4611 * the sgl. 4612 */ 4613 if (dst == (void *)&eq->desc[eq->sidx]) { 4614 dst = (void *)&eq->desc[0]; 4615 write_gl_to_txd(txq, m0, &dst, 0); 4616 } else 4617 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx); 4618 txq->sgl_wrs++; 4619 4620 txq->txpkt_wrs++; 4621 4622 txsd = &txq->sdesc[eq->pidx]; 4623 txsd->m = m0; 4624 txsd->desc_used = ndesc; 4625 4626 return (ndesc); 4627 } 4628 4629 /* 4630 * Write a raw WR to the hardware descriptors, update the software 4631 * descriptor, and advance the pidx. It is guaranteed that enough 4632 * descriptors are available. 4633 * 4634 * The return value is the # of hardware descriptors used. 4635 */ 4636 static u_int 4637 write_raw_wr(struct sge_txq *txq, void *wr, struct mbuf *m0, u_int available) 4638 { 4639 struct sge_eq *eq = &txq->eq; 4640 struct tx_sdesc *txsd; 4641 struct mbuf *m; 4642 caddr_t dst; 4643 int len16, ndesc; 4644 4645 len16 = mbuf_len16(m0); 4646 ndesc = howmany(len16, EQ_ESIZE / 16); 4647 MPASS(ndesc <= available); 4648 4649 dst = wr; 4650 for (m = m0; m != NULL; m = m->m_next) 4651 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len); 4652 4653 txq->raw_wrs++; 4654 4655 txsd = &txq->sdesc[eq->pidx]; 4656 txsd->m = m0; 4657 txsd->desc_used = ndesc; 4658 4659 return (ndesc); 4660 } 4661 4662 /* 4663 * Write a txpkt WR for this packet to the hardware descriptors, update the 4664 * software descriptor, and advance the pidx. It is guaranteed that enough 4665 * descriptors are available. 4666 * 4667 * The return value is the # of hardware descriptors used. 4668 */ 4669 static u_int 4670 write_txpkt_wr(struct sge_txq *txq, struct fw_eth_tx_pkt_wr *wr, 4671 struct mbuf *m0, u_int available) 4672 { 4673 struct sge_eq *eq = &txq->eq; 4674 struct tx_sdesc *txsd; 4675 struct cpl_tx_pkt_core *cpl; 4676 uint32_t ctrl; /* used in many unrelated places */ 4677 uint64_t ctrl1; 4678 int len16, ndesc, pktlen, nsegs; 4679 caddr_t dst; 4680 4681 TXQ_LOCK_ASSERT_OWNED(txq); 4682 M_ASSERTPKTHDR(m0); 4683 MPASS(available > 0 && available < eq->sidx); 4684 4685 len16 = mbuf_len16(m0); 4686 nsegs = mbuf_nsegs(m0); 4687 pktlen = m0->m_pkthdr.len; 4688 ctrl = sizeof(struct cpl_tx_pkt_core); 4689 if (needs_tso(m0)) 4690 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 4691 else if (pktlen <= imm_payload(2) && available >= 2) { 4692 /* Immediate data. Recalculate len16 and set nsegs to 0. */ 4693 ctrl += pktlen; 4694 len16 = howmany(sizeof(struct fw_eth_tx_pkt_wr) + 4695 sizeof(struct cpl_tx_pkt_core) + pktlen, 16); 4696 nsegs = 0; 4697 } 4698 ndesc = howmany(len16, EQ_ESIZE / 16); 4699 MPASS(ndesc <= available); 4700 4701 /* Firmware work request header */ 4702 MPASS(wr == (void *)&eq->desc[eq->pidx]); 4703 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_WR) | 4704 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl)); 4705 4706 ctrl = V_FW_WR_LEN16(len16); 4707 wr->equiq_to_len16 = htobe32(ctrl); 4708 wr->r3 = 0; 4709 4710 if (needs_tso(m0)) { 4711 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1); 4712 4713 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 4714 m0->m_pkthdr.l4hlen > 0, 4715 ("%s: mbuf %p needs TSO but missing header lengths", 4716 __func__, m0)); 4717 4718 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE | 4719 F_LSO_LAST_SLICE | V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) 4720 | V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2); 4721 if (m0->m_pkthdr.l2hlen == sizeof(struct ether_vlan_header)) 4722 ctrl |= V_LSO_ETHHDR_LEN(1); 4723 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 4724 ctrl |= F_LSO_IPV6; 4725 4726 lso->lso_ctrl = htobe32(ctrl); 4727 lso->ipid_ofst = htobe16(0); 4728 lso->mss = htobe16(m0->m_pkthdr.tso_segsz); 4729 lso->seqno_offset = htobe32(0); 4730 lso->len = htobe32(pktlen); 4731 4732 cpl = (void *)(lso + 1); 4733 4734 txq->tso_wrs++; 4735 } else 4736 cpl = (void *)(wr + 1); 4737 4738 /* Checksum offload */ 4739 ctrl1 = 0; 4740 if (needs_l3_csum(m0) == 0) 4741 ctrl1 |= F_TXPKT_IPCSUM_DIS; 4742 if (needs_l4_csum(m0) == 0) 4743 ctrl1 |= F_TXPKT_L4CSUM_DIS; 4744 if (m0->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | 4745 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO)) 4746 txq->txcsum++; /* some hardware assistance provided */ 4747 4748 /* VLAN tag insertion */ 4749 if (needs_vlan_insertion(m0)) { 4750 ctrl1 |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 4751 txq->vlan_insertion++; 4752 } 4753 4754 /* CPL header */ 4755 cpl->ctrl0 = txq->cpl_ctrl0; 4756 cpl->pack = 0; 4757 cpl->len = htobe16(pktlen); 4758 cpl->ctrl1 = htobe64(ctrl1); 4759 4760 /* SGL */ 4761 dst = (void *)(cpl + 1); 4762 if (nsegs > 0) { 4763 4764 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx); 4765 txq->sgl_wrs++; 4766 } else { 4767 struct mbuf *m; 4768 4769 for (m = m0; m != NULL; m = m->m_next) { 4770 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len); 4771 #ifdef INVARIANTS 4772 pktlen -= m->m_len; 4773 #endif 4774 } 4775 #ifdef INVARIANTS 4776 KASSERT(pktlen == 0, ("%s: %d bytes left.", __func__, pktlen)); 4777 #endif 4778 txq->imm_wrs++; 4779 } 4780 4781 txq->txpkt_wrs++; 4782 4783 txsd = &txq->sdesc[eq->pidx]; 4784 txsd->m = m0; 4785 txsd->desc_used = ndesc; 4786 4787 return (ndesc); 4788 } 4789 4790 static int 4791 try_txpkts(struct mbuf *m, struct mbuf *n, struct txpkts *txp, u_int available) 4792 { 4793 u_int needed, nsegs1, nsegs2, l1, l2; 4794 4795 if (cannot_use_txpkts(m) || cannot_use_txpkts(n)) 4796 return (1); 4797 4798 nsegs1 = mbuf_nsegs(m); 4799 nsegs2 = mbuf_nsegs(n); 4800 if (nsegs1 + nsegs2 == 2) { 4801 txp->wr_type = 1; 4802 l1 = l2 = txpkts1_len16(); 4803 } else { 4804 txp->wr_type = 0; 4805 l1 = txpkts0_len16(nsegs1); 4806 l2 = txpkts0_len16(nsegs2); 4807 } 4808 txp->len16 = howmany(sizeof(struct fw_eth_tx_pkts_wr), 16) + l1 + l2; 4809 needed = howmany(txp->len16, EQ_ESIZE / 16); 4810 if (needed > SGE_MAX_WR_NDESC || needed > available) 4811 return (1); 4812 4813 txp->plen = m->m_pkthdr.len + n->m_pkthdr.len; 4814 if (txp->plen > 65535) 4815 return (1); 4816 4817 txp->npkt = 2; 4818 set_mbuf_len16(m, l1); 4819 set_mbuf_len16(n, l2); 4820 4821 return (0); 4822 } 4823 4824 static int 4825 add_to_txpkts(struct mbuf *m, struct txpkts *txp, u_int available) 4826 { 4827 u_int plen, len16, needed, nsegs; 4828 4829 MPASS(txp->wr_type == 0 || txp->wr_type == 1); 4830 4831 if (cannot_use_txpkts(m)) 4832 return (1); 4833 4834 nsegs = mbuf_nsegs(m); 4835 if (txp->wr_type == 1 && nsegs != 1) 4836 return (1); 4837 4838 plen = txp->plen + m->m_pkthdr.len; 4839 if (plen > 65535) 4840 return (1); 4841 4842 if (txp->wr_type == 0) 4843 len16 = txpkts0_len16(nsegs); 4844 else 4845 len16 = txpkts1_len16(); 4846 needed = howmany(txp->len16 + len16, EQ_ESIZE / 16); 4847 if (needed > SGE_MAX_WR_NDESC || needed > available) 4848 return (1); 4849 4850 txp->npkt++; 4851 txp->plen = plen; 4852 txp->len16 += len16; 4853 set_mbuf_len16(m, len16); 4854 4855 return (0); 4856 } 4857 4858 /* 4859 * Write a txpkts WR for the packets in txp to the hardware descriptors, update 4860 * the software descriptor, and advance the pidx. It is guaranteed that enough 4861 * descriptors are available. 4862 * 4863 * The return value is the # of hardware descriptors used. 4864 */ 4865 static u_int 4866 write_txpkts_wr(struct sge_txq *txq, struct fw_eth_tx_pkts_wr *wr, 4867 struct mbuf *m0, const struct txpkts *txp, u_int available) 4868 { 4869 struct sge_eq *eq = &txq->eq; 4870 struct tx_sdesc *txsd; 4871 struct cpl_tx_pkt_core *cpl; 4872 uint32_t ctrl; 4873 uint64_t ctrl1; 4874 int ndesc, checkwrap; 4875 struct mbuf *m; 4876 void *flitp; 4877 4878 TXQ_LOCK_ASSERT_OWNED(txq); 4879 MPASS(txp->npkt > 0); 4880 MPASS(txp->plen < 65536); 4881 MPASS(m0 != NULL); 4882 MPASS(m0->m_nextpkt != NULL); 4883 MPASS(txp->len16 <= howmany(SGE_MAX_WR_LEN, 16)); 4884 MPASS(available > 0 && available < eq->sidx); 4885 4886 ndesc = howmany(txp->len16, EQ_ESIZE / 16); 4887 MPASS(ndesc <= available); 4888 4889 MPASS(wr == (void *)&eq->desc[eq->pidx]); 4890 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR)); 4891 ctrl = V_FW_WR_LEN16(txp->len16); 4892 wr->equiq_to_len16 = htobe32(ctrl); 4893 wr->plen = htobe16(txp->plen); 4894 wr->npkt = txp->npkt; 4895 wr->r3 = 0; 4896 wr->type = txp->wr_type; 4897 flitp = wr + 1; 4898 4899 /* 4900 * At this point we are 16B into a hardware descriptor. If checkwrap is 4901 * set then we know the WR is going to wrap around somewhere. We'll 4902 * check for that at appropriate points. 4903 */ 4904 checkwrap = eq->sidx - ndesc < eq->pidx; 4905 for (m = m0; m != NULL; m = m->m_nextpkt) { 4906 if (txp->wr_type == 0) { 4907 struct ulp_txpkt *ulpmc; 4908 struct ulptx_idata *ulpsc; 4909 4910 /* ULP master command */ 4911 ulpmc = flitp; 4912 ulpmc->cmd_dest = htobe32(V_ULPTX_CMD(ULP_TX_PKT) | 4913 V_ULP_TXPKT_DEST(0) | V_ULP_TXPKT_FID(eq->iqid)); 4914 ulpmc->len = htobe32(mbuf_len16(m)); 4915 4916 /* ULP subcommand */ 4917 ulpsc = (void *)(ulpmc + 1); 4918 ulpsc->cmd_more = htobe32(V_ULPTX_CMD(ULP_TX_SC_IMM) | 4919 F_ULP_TX_SC_MORE); 4920 ulpsc->len = htobe32(sizeof(struct cpl_tx_pkt_core)); 4921 4922 cpl = (void *)(ulpsc + 1); 4923 if (checkwrap && 4924 (uintptr_t)cpl == (uintptr_t)&eq->desc[eq->sidx]) 4925 cpl = (void *)&eq->desc[0]; 4926 } else { 4927 cpl = flitp; 4928 } 4929 4930 /* Checksum offload */ 4931 ctrl1 = 0; 4932 if (needs_l3_csum(m) == 0) 4933 ctrl1 |= F_TXPKT_IPCSUM_DIS; 4934 if (needs_l4_csum(m) == 0) 4935 ctrl1 |= F_TXPKT_L4CSUM_DIS; 4936 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | 4937 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO)) 4938 txq->txcsum++; /* some hardware assistance provided */ 4939 4940 /* VLAN tag insertion */ 4941 if (needs_vlan_insertion(m)) { 4942 ctrl1 |= F_TXPKT_VLAN_VLD | 4943 V_TXPKT_VLAN(m->m_pkthdr.ether_vtag); 4944 txq->vlan_insertion++; 4945 } 4946 4947 /* CPL header */ 4948 cpl->ctrl0 = txq->cpl_ctrl0; 4949 cpl->pack = 0; 4950 cpl->len = htobe16(m->m_pkthdr.len); 4951 cpl->ctrl1 = htobe64(ctrl1); 4952 4953 flitp = cpl + 1; 4954 if (checkwrap && 4955 (uintptr_t)flitp == (uintptr_t)&eq->desc[eq->sidx]) 4956 flitp = (void *)&eq->desc[0]; 4957 4958 write_gl_to_txd(txq, m, (caddr_t *)(&flitp), checkwrap); 4959 4960 } 4961 4962 if (txp->wr_type == 0) { 4963 txq->txpkts0_pkts += txp->npkt; 4964 txq->txpkts0_wrs++; 4965 } else { 4966 txq->txpkts1_pkts += txp->npkt; 4967 txq->txpkts1_wrs++; 4968 } 4969 4970 txsd = &txq->sdesc[eq->pidx]; 4971 txsd->m = m0; 4972 txsd->desc_used = ndesc; 4973 4974 return (ndesc); 4975 } 4976 4977 /* 4978 * If the SGL ends on an address that is not 16 byte aligned, this function will 4979 * add a 0 filled flit at the end. 4980 */ 4981 static void 4982 write_gl_to_txd(struct sge_txq *txq, struct mbuf *m, caddr_t *to, int checkwrap) 4983 { 4984 struct sge_eq *eq = &txq->eq; 4985 struct sglist *gl = txq->gl; 4986 struct sglist_seg *seg; 4987 __be64 *flitp, *wrap; 4988 struct ulptx_sgl *usgl; 4989 int i, nflits, nsegs; 4990 4991 KASSERT(((uintptr_t)(*to) & 0xf) == 0, 4992 ("%s: SGL must start at a 16 byte boundary: %p", __func__, *to)); 4993 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]); 4994 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]); 4995 4996 get_pkt_gl(m, gl); 4997 nsegs = gl->sg_nseg; 4998 MPASS(nsegs > 0); 4999 5000 nflits = (3 * (nsegs - 1)) / 2 + ((nsegs - 1) & 1) + 2; 5001 flitp = (__be64 *)(*to); 5002 wrap = (__be64 *)(&eq->desc[eq->sidx]); 5003 seg = &gl->sg_segs[0]; 5004 usgl = (void *)flitp; 5005 5006 /* 5007 * We start at a 16 byte boundary somewhere inside the tx descriptor 5008 * ring, so we're at least 16 bytes away from the status page. There is 5009 * no chance of a wrap around in the middle of usgl (which is 16 bytes). 5010 */ 5011 5012 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 5013 V_ULPTX_NSGE(nsegs)); 5014 usgl->len0 = htobe32(seg->ss_len); 5015 usgl->addr0 = htobe64(seg->ss_paddr); 5016 seg++; 5017 5018 if (checkwrap == 0 || (uintptr_t)(flitp + nflits) <= (uintptr_t)wrap) { 5019 5020 /* Won't wrap around at all */ 5021 5022 for (i = 0; i < nsegs - 1; i++, seg++) { 5023 usgl->sge[i / 2].len[i & 1] = htobe32(seg->ss_len); 5024 usgl->sge[i / 2].addr[i & 1] = htobe64(seg->ss_paddr); 5025 } 5026 if (i & 1) 5027 usgl->sge[i / 2].len[1] = htobe32(0); 5028 flitp += nflits; 5029 } else { 5030 5031 /* Will wrap somewhere in the rest of the SGL */ 5032 5033 /* 2 flits already written, write the rest flit by flit */ 5034 flitp = (void *)(usgl + 1); 5035 for (i = 0; i < nflits - 2; i++) { 5036 if (flitp == wrap) 5037 flitp = (void *)eq->desc; 5038 *flitp++ = get_flit(seg, nsegs - 1, i); 5039 } 5040 } 5041 5042 if (nflits & 1) { 5043 MPASS(((uintptr_t)flitp) & 0xf); 5044 *flitp++ = 0; 5045 } 5046 5047 MPASS((((uintptr_t)flitp) & 0xf) == 0); 5048 if (__predict_false(flitp == wrap)) 5049 *to = (void *)eq->desc; 5050 else 5051 *to = (void *)flitp; 5052 } 5053 5054 static inline void 5055 copy_to_txd(struct sge_eq *eq, caddr_t from, caddr_t *to, int len) 5056 { 5057 5058 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]); 5059 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]); 5060 5061 if (__predict_true((uintptr_t)(*to) + len <= 5062 (uintptr_t)&eq->desc[eq->sidx])) { 5063 bcopy(from, *to, len); 5064 (*to) += len; 5065 } else { 5066 int portion = (uintptr_t)&eq->desc[eq->sidx] - (uintptr_t)(*to); 5067 5068 bcopy(from, *to, portion); 5069 from += portion; 5070 portion = len - portion; /* remaining */ 5071 bcopy(from, (void *)eq->desc, portion); 5072 (*to) = (caddr_t)eq->desc + portion; 5073 } 5074 } 5075 5076 static inline void 5077 ring_eq_db(struct adapter *sc, struct sge_eq *eq, u_int n) 5078 { 5079 u_int db; 5080 5081 MPASS(n > 0); 5082 5083 db = eq->doorbells; 5084 if (n > 1) 5085 clrbit(&db, DOORBELL_WCWR); 5086 wmb(); 5087 5088 switch (ffs(db) - 1) { 5089 case DOORBELL_UDB: 5090 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n)); 5091 break; 5092 5093 case DOORBELL_WCWR: { 5094 volatile uint64_t *dst, *src; 5095 int i; 5096 5097 /* 5098 * Queues whose 128B doorbell segment fits in the page do not 5099 * use relative qid (udb_qid is always 0). Only queues with 5100 * doorbell segments can do WCWR. 5101 */ 5102 KASSERT(eq->udb_qid == 0 && n == 1, 5103 ("%s: inappropriate doorbell (0x%x, %d, %d) for eq %p", 5104 __func__, eq->doorbells, n, eq->dbidx, eq)); 5105 5106 dst = (volatile void *)((uintptr_t)eq->udb + UDBS_WR_OFFSET - 5107 UDBS_DB_OFFSET); 5108 i = eq->dbidx; 5109 src = (void *)&eq->desc[i]; 5110 while (src != (void *)&eq->desc[i + 1]) 5111 *dst++ = *src++; 5112 wmb(); 5113 break; 5114 } 5115 5116 case DOORBELL_UDBWC: 5117 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n)); 5118 wmb(); 5119 break; 5120 5121 case DOORBELL_KDB: 5122 t4_write_reg(sc, sc->sge_kdoorbell_reg, 5123 V_QID(eq->cntxt_id) | V_PIDX(n)); 5124 break; 5125 } 5126 5127 IDXINCR(eq->dbidx, n, eq->sidx); 5128 } 5129 5130 static inline u_int 5131 reclaimable_tx_desc(struct sge_eq *eq) 5132 { 5133 uint16_t hw_cidx; 5134 5135 hw_cidx = read_hw_cidx(eq); 5136 return (IDXDIFF(hw_cidx, eq->cidx, eq->sidx)); 5137 } 5138 5139 static inline u_int 5140 total_available_tx_desc(struct sge_eq *eq) 5141 { 5142 uint16_t hw_cidx, pidx; 5143 5144 hw_cidx = read_hw_cidx(eq); 5145 pidx = eq->pidx; 5146 5147 if (pidx == hw_cidx) 5148 return (eq->sidx - 1); 5149 else 5150 return (IDXDIFF(hw_cidx, pidx, eq->sidx) - 1); 5151 } 5152 5153 static inline uint16_t 5154 read_hw_cidx(struct sge_eq *eq) 5155 { 5156 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx]; 5157 uint16_t cidx = spg->cidx; /* stable snapshot */ 5158 5159 return (be16toh(cidx)); 5160 } 5161 5162 /* 5163 * Reclaim 'n' descriptors approximately. 5164 */ 5165 static u_int 5166 reclaim_tx_descs(struct sge_txq *txq, u_int n) 5167 { 5168 struct tx_sdesc *txsd; 5169 struct sge_eq *eq = &txq->eq; 5170 u_int can_reclaim, reclaimed; 5171 5172 TXQ_LOCK_ASSERT_OWNED(txq); 5173 MPASS(n > 0); 5174 5175 reclaimed = 0; 5176 can_reclaim = reclaimable_tx_desc(eq); 5177 while (can_reclaim && reclaimed < n) { 5178 int ndesc; 5179 struct mbuf *m, *nextpkt; 5180 5181 txsd = &txq->sdesc[eq->cidx]; 5182 ndesc = txsd->desc_used; 5183 5184 /* Firmware doesn't return "partial" credits. */ 5185 KASSERT(can_reclaim >= ndesc, 5186 ("%s: unexpected number of credits: %d, %d", 5187 __func__, can_reclaim, ndesc)); 5188 KASSERT(ndesc != 0, 5189 ("%s: descriptor with no credits: cidx %d", 5190 __func__, eq->cidx)); 5191 5192 for (m = txsd->m; m != NULL; m = nextpkt) { 5193 nextpkt = m->m_nextpkt; 5194 m->m_nextpkt = NULL; 5195 m_freem(m); 5196 } 5197 reclaimed += ndesc; 5198 can_reclaim -= ndesc; 5199 IDXINCR(eq->cidx, ndesc, eq->sidx); 5200 } 5201 5202 return (reclaimed); 5203 } 5204 5205 static void 5206 tx_reclaim(void *arg, int n) 5207 { 5208 struct sge_txq *txq = arg; 5209 struct sge_eq *eq = &txq->eq; 5210 5211 do { 5212 if (TXQ_TRYLOCK(txq) == 0) 5213 break; 5214 n = reclaim_tx_descs(txq, 32); 5215 if (eq->cidx == eq->pidx) 5216 eq->equeqidx = eq->pidx; 5217 TXQ_UNLOCK(txq); 5218 } while (n > 0); 5219 } 5220 5221 static __be64 5222 get_flit(struct sglist_seg *segs, int nsegs, int idx) 5223 { 5224 int i = (idx / 3) * 2; 5225 5226 switch (idx % 3) { 5227 case 0: { 5228 uint64_t rc; 5229 5230 rc = (uint64_t)segs[i].ss_len << 32; 5231 if (i + 1 < nsegs) 5232 rc |= (uint64_t)(segs[i + 1].ss_len); 5233 5234 return (htobe64(rc)); 5235 } 5236 case 1: 5237 return (htobe64(segs[i].ss_paddr)); 5238 case 2: 5239 return (htobe64(segs[i + 1].ss_paddr)); 5240 } 5241 5242 return (0); 5243 } 5244 5245 static void 5246 find_best_refill_source(struct adapter *sc, struct sge_fl *fl, int maxp) 5247 { 5248 int8_t zidx, hwidx, idx; 5249 uint16_t region1, region3; 5250 int spare, spare_needed, n; 5251 struct sw_zone_info *swz; 5252 struct hw_buf_info *hwb, *hwb_list = &sc->sge.hw_buf_info[0]; 5253 5254 /* 5255 * Buffer Packing: Look for PAGE_SIZE or larger zone which has a bufsize 5256 * large enough for the max payload and cluster metadata. Otherwise 5257 * settle for the largest bufsize that leaves enough room in the cluster 5258 * for metadata. 5259 * 5260 * Without buffer packing: Look for the smallest zone which has a 5261 * bufsize large enough for the max payload. Settle for the largest 5262 * bufsize available if there's nothing big enough for max payload. 5263 */ 5264 spare_needed = fl->flags & FL_BUF_PACKING ? CL_METADATA_SIZE : 0; 5265 swz = &sc->sge.sw_zone_info[0]; 5266 hwidx = -1; 5267 for (zidx = 0; zidx < SW_ZONE_SIZES; zidx++, swz++) { 5268 if (swz->size > largest_rx_cluster) { 5269 if (__predict_true(hwidx != -1)) 5270 break; 5271 5272 /* 5273 * This is a misconfiguration. largest_rx_cluster is 5274 * preventing us from finding a refill source. See 5275 * dev.t5nex.<n>.buffer_sizes to figure out why. 5276 */ 5277 device_printf(sc->dev, "largest_rx_cluster=%u leaves no" 5278 " refill source for fl %p (dma %u). Ignored.\n", 5279 largest_rx_cluster, fl, maxp); 5280 } 5281 for (idx = swz->head_hwidx; idx != -1; idx = hwb->next) { 5282 hwb = &hwb_list[idx]; 5283 spare = swz->size - hwb->size; 5284 if (spare < spare_needed) 5285 continue; 5286 5287 hwidx = idx; /* best option so far */ 5288 if (hwb->size >= maxp) { 5289 5290 if ((fl->flags & FL_BUF_PACKING) == 0) 5291 goto done; /* stop looking (not packing) */ 5292 5293 if (swz->size >= safest_rx_cluster) 5294 goto done; /* stop looking (packing) */ 5295 } 5296 break; /* keep looking, next zone */ 5297 } 5298 } 5299 done: 5300 /* A usable hwidx has been located. */ 5301 MPASS(hwidx != -1); 5302 hwb = &hwb_list[hwidx]; 5303 zidx = hwb->zidx; 5304 swz = &sc->sge.sw_zone_info[zidx]; 5305 region1 = 0; 5306 region3 = swz->size - hwb->size; 5307 5308 /* 5309 * Stay within this zone and see if there is a better match when mbuf 5310 * inlining is allowed. Remember that the hwidx's are sorted in 5311 * decreasing order of size (so in increasing order of spare area). 5312 */ 5313 for (idx = hwidx; idx != -1; idx = hwb->next) { 5314 hwb = &hwb_list[idx]; 5315 spare = swz->size - hwb->size; 5316 5317 if (allow_mbufs_in_cluster == 0 || hwb->size < maxp) 5318 break; 5319 5320 /* 5321 * Do not inline mbufs if doing so would violate the pad/pack 5322 * boundary alignment requirement. 5323 */ 5324 if (fl_pad && (MSIZE % sc->params.sge.pad_boundary) != 0) 5325 continue; 5326 if (fl->flags & FL_BUF_PACKING && 5327 (MSIZE % sc->params.sge.pack_boundary) != 0) 5328 continue; 5329 5330 if (spare < CL_METADATA_SIZE + MSIZE) 5331 continue; 5332 n = (spare - CL_METADATA_SIZE) / MSIZE; 5333 if (n > howmany(hwb->size, maxp)) 5334 break; 5335 5336 hwidx = idx; 5337 if (fl->flags & FL_BUF_PACKING) { 5338 region1 = n * MSIZE; 5339 region3 = spare - region1; 5340 } else { 5341 region1 = MSIZE; 5342 region3 = spare - region1; 5343 break; 5344 } 5345 } 5346 5347 KASSERT(zidx >= 0 && zidx < SW_ZONE_SIZES, 5348 ("%s: bad zone %d for fl %p, maxp %d", __func__, zidx, fl, maxp)); 5349 KASSERT(hwidx >= 0 && hwidx <= SGE_FLBUF_SIZES, 5350 ("%s: bad hwidx %d for fl %p, maxp %d", __func__, hwidx, fl, maxp)); 5351 KASSERT(region1 + sc->sge.hw_buf_info[hwidx].size + region3 == 5352 sc->sge.sw_zone_info[zidx].size, 5353 ("%s: bad buffer layout for fl %p, maxp %d. " 5354 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp, 5355 sc->sge.sw_zone_info[zidx].size, region1, 5356 sc->sge.hw_buf_info[hwidx].size, region3)); 5357 if (fl->flags & FL_BUF_PACKING || region1 > 0) { 5358 KASSERT(region3 >= CL_METADATA_SIZE, 5359 ("%s: no room for metadata. fl %p, maxp %d; " 5360 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp, 5361 sc->sge.sw_zone_info[zidx].size, region1, 5362 sc->sge.hw_buf_info[hwidx].size, region3)); 5363 KASSERT(region1 % MSIZE == 0, 5364 ("%s: bad mbuf region for fl %p, maxp %d. " 5365 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp, 5366 sc->sge.sw_zone_info[zidx].size, region1, 5367 sc->sge.hw_buf_info[hwidx].size, region3)); 5368 } 5369 5370 fl->cll_def.zidx = zidx; 5371 fl->cll_def.hwidx = hwidx; 5372 fl->cll_def.region1 = region1; 5373 fl->cll_def.region3 = region3; 5374 } 5375 5376 static void 5377 find_safe_refill_source(struct adapter *sc, struct sge_fl *fl) 5378 { 5379 struct sge *s = &sc->sge; 5380 struct hw_buf_info *hwb; 5381 struct sw_zone_info *swz; 5382 int spare; 5383 int8_t hwidx; 5384 5385 if (fl->flags & FL_BUF_PACKING) 5386 hwidx = s->safe_hwidx2; /* with room for metadata */ 5387 else if (allow_mbufs_in_cluster && s->safe_hwidx2 != -1) { 5388 hwidx = s->safe_hwidx2; 5389 hwb = &s->hw_buf_info[hwidx]; 5390 swz = &s->sw_zone_info[hwb->zidx]; 5391 spare = swz->size - hwb->size; 5392 5393 /* no good if there isn't room for an mbuf as well */ 5394 if (spare < CL_METADATA_SIZE + MSIZE) 5395 hwidx = s->safe_hwidx1; 5396 } else 5397 hwidx = s->safe_hwidx1; 5398 5399 if (hwidx == -1) { 5400 /* No fallback source */ 5401 fl->cll_alt.hwidx = -1; 5402 fl->cll_alt.zidx = -1; 5403 5404 return; 5405 } 5406 5407 hwb = &s->hw_buf_info[hwidx]; 5408 swz = &s->sw_zone_info[hwb->zidx]; 5409 spare = swz->size - hwb->size; 5410 fl->cll_alt.hwidx = hwidx; 5411 fl->cll_alt.zidx = hwb->zidx; 5412 if (allow_mbufs_in_cluster && 5413 (fl_pad == 0 || (MSIZE % sc->params.sge.pad_boundary) == 0)) 5414 fl->cll_alt.region1 = ((spare - CL_METADATA_SIZE) / MSIZE) * MSIZE; 5415 else 5416 fl->cll_alt.region1 = 0; 5417 fl->cll_alt.region3 = spare - fl->cll_alt.region1; 5418 } 5419 5420 static void 5421 add_fl_to_sfl(struct adapter *sc, struct sge_fl *fl) 5422 { 5423 mtx_lock(&sc->sfl_lock); 5424 FL_LOCK(fl); 5425 if ((fl->flags & FL_DOOMED) == 0) { 5426 fl->flags |= FL_STARVING; 5427 TAILQ_INSERT_TAIL(&sc->sfl, fl, link); 5428 callout_reset(&sc->sfl_callout, hz / 5, refill_sfl, sc); 5429 } 5430 FL_UNLOCK(fl); 5431 mtx_unlock(&sc->sfl_lock); 5432 } 5433 5434 static void 5435 handle_wrq_egr_update(struct adapter *sc, struct sge_eq *eq) 5436 { 5437 struct sge_wrq *wrq = (void *)eq; 5438 5439 atomic_readandclear_int(&eq->equiq); 5440 taskqueue_enqueue(sc->tq[eq->tx_chan], &wrq->wrq_tx_task); 5441 } 5442 5443 static void 5444 handle_eth_egr_update(struct adapter *sc, struct sge_eq *eq) 5445 { 5446 struct sge_txq *txq = (void *)eq; 5447 5448 MPASS((eq->flags & EQ_TYPEMASK) == EQ_ETH); 5449 5450 atomic_readandclear_int(&eq->equiq); 5451 mp_ring_check_drainage(txq->r, 0); 5452 taskqueue_enqueue(sc->tq[eq->tx_chan], &txq->tx_reclaim_task); 5453 } 5454 5455 static int 5456 handle_sge_egr_update(struct sge_iq *iq, const struct rss_header *rss, 5457 struct mbuf *m) 5458 { 5459 const struct cpl_sge_egr_update *cpl = (const void *)(rss + 1); 5460 unsigned int qid = G_EGR_QID(ntohl(cpl->opcode_qid)); 5461 struct adapter *sc = iq->adapter; 5462 struct sge *s = &sc->sge; 5463 struct sge_eq *eq; 5464 static void (*h[])(struct adapter *, struct sge_eq *) = {NULL, 5465 &handle_wrq_egr_update, &handle_eth_egr_update, 5466 &handle_wrq_egr_update}; 5467 5468 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 5469 rss->opcode)); 5470 5471 eq = s->eqmap[qid - s->eq_start - s->eq_base]; 5472 (*h[eq->flags & EQ_TYPEMASK])(sc, eq); 5473 5474 return (0); 5475 } 5476 5477 /* handle_fw_msg works for both fw4_msg and fw6_msg because this is valid */ 5478 CTASSERT(offsetof(struct cpl_fw4_msg, data) == \ 5479 offsetof(struct cpl_fw6_msg, data)); 5480 5481 static int 5482 handle_fw_msg(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 5483 { 5484 struct adapter *sc = iq->adapter; 5485 const struct cpl_fw6_msg *cpl = (const void *)(rss + 1); 5486 5487 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 5488 rss->opcode)); 5489 5490 if (cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL) { 5491 const struct rss_header *rss2; 5492 5493 rss2 = (const struct rss_header *)&cpl->data[0]; 5494 return (t4_cpl_handler[rss2->opcode](iq, rss2, m)); 5495 } 5496 5497 return (t4_fw_msg_handler[cpl->type](sc, &cpl->data[0])); 5498 } 5499 5500 /** 5501 * t4_handle_wrerr_rpl - process a FW work request error message 5502 * @adap: the adapter 5503 * @rpl: start of the FW message 5504 */ 5505 static int 5506 t4_handle_wrerr_rpl(struct adapter *adap, const __be64 *rpl) 5507 { 5508 u8 opcode = *(const u8 *)rpl; 5509 const struct fw_error_cmd *e = (const void *)rpl; 5510 unsigned int i; 5511 5512 if (opcode != FW_ERROR_CMD) { 5513 log(LOG_ERR, 5514 "%s: Received WRERR_RPL message with opcode %#x\n", 5515 device_get_nameunit(adap->dev), opcode); 5516 return (EINVAL); 5517 } 5518 log(LOG_ERR, "%s: FW_ERROR (%s) ", device_get_nameunit(adap->dev), 5519 G_FW_ERROR_CMD_FATAL(be32toh(e->op_to_type)) ? "fatal" : 5520 "non-fatal"); 5521 switch (G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type))) { 5522 case FW_ERROR_TYPE_EXCEPTION: 5523 log(LOG_ERR, "exception info:\n"); 5524 for (i = 0; i < nitems(e->u.exception.info); i++) 5525 log(LOG_ERR, "%s%08x", i == 0 ? "\t" : " ", 5526 be32toh(e->u.exception.info[i])); 5527 log(LOG_ERR, "\n"); 5528 break; 5529 case FW_ERROR_TYPE_HWMODULE: 5530 log(LOG_ERR, "HW module regaddr %08x regval %08x\n", 5531 be32toh(e->u.hwmodule.regaddr), 5532 be32toh(e->u.hwmodule.regval)); 5533 break; 5534 case FW_ERROR_TYPE_WR: 5535 log(LOG_ERR, "WR cidx %d PF %d VF %d eqid %d hdr:\n", 5536 be16toh(e->u.wr.cidx), 5537 G_FW_ERROR_CMD_PFN(be16toh(e->u.wr.pfn_vfn)), 5538 G_FW_ERROR_CMD_VFN(be16toh(e->u.wr.pfn_vfn)), 5539 be32toh(e->u.wr.eqid)); 5540 for (i = 0; i < nitems(e->u.wr.wrhdr); i++) 5541 log(LOG_ERR, "%s%02x", i == 0 ? "\t" : " ", 5542 e->u.wr.wrhdr[i]); 5543 log(LOG_ERR, "\n"); 5544 break; 5545 case FW_ERROR_TYPE_ACL: 5546 log(LOG_ERR, "ACL cidx %d PF %d VF %d eqid %d %s", 5547 be16toh(e->u.acl.cidx), 5548 G_FW_ERROR_CMD_PFN(be16toh(e->u.acl.pfn_vfn)), 5549 G_FW_ERROR_CMD_VFN(be16toh(e->u.acl.pfn_vfn)), 5550 be32toh(e->u.acl.eqid), 5551 G_FW_ERROR_CMD_MV(be16toh(e->u.acl.mv_pkd)) ? "vlanid" : 5552 "MAC"); 5553 for (i = 0; i < nitems(e->u.acl.val); i++) 5554 log(LOG_ERR, " %02x", e->u.acl.val[i]); 5555 log(LOG_ERR, "\n"); 5556 break; 5557 default: 5558 log(LOG_ERR, "type %#x\n", 5559 G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type))); 5560 return (EINVAL); 5561 } 5562 return (0); 5563 } 5564 5565 static int 5566 sysctl_uint16(SYSCTL_HANDLER_ARGS) 5567 { 5568 uint16_t *id = arg1; 5569 int i = *id; 5570 5571 return sysctl_handle_int(oidp, &i, 0, req); 5572 } 5573 5574 static int 5575 sysctl_bufsizes(SYSCTL_HANDLER_ARGS) 5576 { 5577 struct sge *s = arg1; 5578 struct hw_buf_info *hwb = &s->hw_buf_info[0]; 5579 struct sw_zone_info *swz = &s->sw_zone_info[0]; 5580 int i, rc; 5581 struct sbuf sb; 5582 char c; 5583 5584 sbuf_new(&sb, NULL, 32, SBUF_AUTOEXTEND); 5585 for (i = 0; i < SGE_FLBUF_SIZES; i++, hwb++) { 5586 if (hwb->zidx >= 0 && swz[hwb->zidx].size <= largest_rx_cluster) 5587 c = '*'; 5588 else 5589 c = '\0'; 5590 5591 sbuf_printf(&sb, "%u%c ", hwb->size, c); 5592 } 5593 sbuf_trim(&sb); 5594 sbuf_finish(&sb); 5595 rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req); 5596 sbuf_delete(&sb); 5597 return (rc); 5598 } 5599 5600 #ifdef RATELIMIT 5601 /* 5602 * len16 for a txpkt WR with a GL. Includes the firmware work request header. 5603 */ 5604 static inline u_int 5605 txpkt_eo_len16(u_int nsegs, u_int immhdrs, u_int tso) 5606 { 5607 u_int n; 5608 5609 MPASS(immhdrs > 0); 5610 5611 n = roundup2(sizeof(struct fw_eth_tx_eo_wr) + 5612 sizeof(struct cpl_tx_pkt_core) + immhdrs, 16); 5613 if (__predict_false(nsegs == 0)) 5614 goto done; 5615 5616 nsegs--; /* first segment is part of ulptx_sgl */ 5617 n += sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 5618 if (tso) 5619 n += sizeof(struct cpl_tx_pkt_lso_core); 5620 5621 done: 5622 return (howmany(n, 16)); 5623 } 5624 5625 #define ETID_FLOWC_NPARAMS 6 5626 #define ETID_FLOWC_LEN (roundup2((sizeof(struct fw_flowc_wr) + \ 5627 ETID_FLOWC_NPARAMS * sizeof(struct fw_flowc_mnemval)), 16)) 5628 #define ETID_FLOWC_LEN16 (howmany(ETID_FLOWC_LEN, 16)) 5629 5630 static int 5631 send_etid_flowc_wr(struct cxgbe_snd_tag *cst, struct port_info *pi, 5632 struct vi_info *vi) 5633 { 5634 struct wrq_cookie cookie; 5635 u_int pfvf = G_FW_VIID_PFN(vi->viid) << S_FW_VIID_PFN; 5636 struct fw_flowc_wr *flowc; 5637 5638 mtx_assert(&cst->lock, MA_OWNED); 5639 MPASS((cst->flags & (EO_FLOWC_PENDING | EO_FLOWC_RPL_PENDING)) == 5640 EO_FLOWC_PENDING); 5641 5642 flowc = start_wrq_wr(cst->eo_txq, ETID_FLOWC_LEN16, &cookie); 5643 if (__predict_false(flowc == NULL)) 5644 return (ENOMEM); 5645 5646 bzero(flowc, ETID_FLOWC_LEN); 5647 flowc->op_to_nparams = htobe32(V_FW_WR_OP(FW_FLOWC_WR) | 5648 V_FW_FLOWC_WR_NPARAMS(ETID_FLOWC_NPARAMS) | V_FW_WR_COMPL(0)); 5649 flowc->flowid_len16 = htonl(V_FW_WR_LEN16(ETID_FLOWC_LEN16) | 5650 V_FW_WR_FLOWID(cst->etid)); 5651 flowc->mnemval[0].mnemonic = FW_FLOWC_MNEM_PFNVFN; 5652 flowc->mnemval[0].val = htobe32(pfvf); 5653 flowc->mnemval[1].mnemonic = FW_FLOWC_MNEM_CH; 5654 flowc->mnemval[1].val = htobe32(pi->tx_chan); 5655 flowc->mnemval[2].mnemonic = FW_FLOWC_MNEM_PORT; 5656 flowc->mnemval[2].val = htobe32(pi->tx_chan); 5657 flowc->mnemval[3].mnemonic = FW_FLOWC_MNEM_IQID; 5658 flowc->mnemval[3].val = htobe32(cst->iqid); 5659 flowc->mnemval[4].mnemonic = FW_FLOWC_MNEM_EOSTATE; 5660 flowc->mnemval[4].val = htobe32(FW_FLOWC_MNEM_EOSTATE_ESTABLISHED); 5661 flowc->mnemval[5].mnemonic = FW_FLOWC_MNEM_SCHEDCLASS; 5662 flowc->mnemval[5].val = htobe32(cst->schedcl); 5663 5664 commit_wrq_wr(cst->eo_txq, flowc, &cookie); 5665 5666 cst->flags &= ~EO_FLOWC_PENDING; 5667 cst->flags |= EO_FLOWC_RPL_PENDING; 5668 MPASS(cst->tx_credits >= ETID_FLOWC_LEN16); /* flowc is first WR. */ 5669 cst->tx_credits -= ETID_FLOWC_LEN16; 5670 5671 return (0); 5672 } 5673 5674 #define ETID_FLUSH_LEN16 (howmany(sizeof (struct fw_flowc_wr), 16)) 5675 5676 void 5677 send_etid_flush_wr(struct cxgbe_snd_tag *cst) 5678 { 5679 struct fw_flowc_wr *flowc; 5680 struct wrq_cookie cookie; 5681 5682 mtx_assert(&cst->lock, MA_OWNED); 5683 5684 flowc = start_wrq_wr(cst->eo_txq, ETID_FLUSH_LEN16, &cookie); 5685 if (__predict_false(flowc == NULL)) 5686 CXGBE_UNIMPLEMENTED(__func__); 5687 5688 bzero(flowc, ETID_FLUSH_LEN16 * 16); 5689 flowc->op_to_nparams = htobe32(V_FW_WR_OP(FW_FLOWC_WR) | 5690 V_FW_FLOWC_WR_NPARAMS(0) | F_FW_WR_COMPL); 5691 flowc->flowid_len16 = htobe32(V_FW_WR_LEN16(ETID_FLUSH_LEN16) | 5692 V_FW_WR_FLOWID(cst->etid)); 5693 5694 commit_wrq_wr(cst->eo_txq, flowc, &cookie); 5695 5696 cst->flags |= EO_FLUSH_RPL_PENDING; 5697 MPASS(cst->tx_credits >= ETID_FLUSH_LEN16); 5698 cst->tx_credits -= ETID_FLUSH_LEN16; 5699 cst->ncompl++; 5700 } 5701 5702 static void 5703 write_ethofld_wr(struct cxgbe_snd_tag *cst, struct fw_eth_tx_eo_wr *wr, 5704 struct mbuf *m0, int compl) 5705 { 5706 struct cpl_tx_pkt_core *cpl; 5707 uint64_t ctrl1; 5708 uint32_t ctrl; /* used in many unrelated places */ 5709 int len16, pktlen, nsegs, immhdrs; 5710 caddr_t dst; 5711 uintptr_t p; 5712 struct ulptx_sgl *usgl; 5713 struct sglist sg; 5714 struct sglist_seg segs[38]; /* XXX: find real limit. XXX: get off the stack */ 5715 5716 mtx_assert(&cst->lock, MA_OWNED); 5717 M_ASSERTPKTHDR(m0); 5718 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 5719 m0->m_pkthdr.l4hlen > 0, 5720 ("%s: ethofld mbuf %p is missing header lengths", __func__, m0)); 5721 5722 len16 = mbuf_eo_len16(m0); 5723 nsegs = mbuf_eo_nsegs(m0); 5724 pktlen = m0->m_pkthdr.len; 5725 ctrl = sizeof(struct cpl_tx_pkt_core); 5726 if (needs_tso(m0)) 5727 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 5728 immhdrs = m0->m_pkthdr.l2hlen + m0->m_pkthdr.l3hlen + m0->m_pkthdr.l4hlen; 5729 ctrl += immhdrs; 5730 5731 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_EO_WR) | 5732 V_FW_ETH_TX_EO_WR_IMMDLEN(ctrl) | V_FW_WR_COMPL(!!compl)); 5733 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(len16) | 5734 V_FW_WR_FLOWID(cst->etid)); 5735 wr->r3 = 0; 5736 if (needs_udp_csum(m0)) { 5737 wr->u.udpseg.type = FW_ETH_TX_EO_TYPE_UDPSEG; 5738 wr->u.udpseg.ethlen = m0->m_pkthdr.l2hlen; 5739 wr->u.udpseg.iplen = htobe16(m0->m_pkthdr.l3hlen); 5740 wr->u.udpseg.udplen = m0->m_pkthdr.l4hlen; 5741 wr->u.udpseg.rtplen = 0; 5742 wr->u.udpseg.r4 = 0; 5743 wr->u.udpseg.mss = htobe16(pktlen - immhdrs); 5744 wr->u.udpseg.schedpktsize = wr->u.udpseg.mss; 5745 wr->u.udpseg.plen = htobe32(pktlen - immhdrs); 5746 cpl = (void *)(wr + 1); 5747 } else { 5748 MPASS(needs_tcp_csum(m0)); 5749 wr->u.tcpseg.type = FW_ETH_TX_EO_TYPE_TCPSEG; 5750 wr->u.tcpseg.ethlen = m0->m_pkthdr.l2hlen; 5751 wr->u.tcpseg.iplen = htobe16(m0->m_pkthdr.l3hlen); 5752 wr->u.tcpseg.tcplen = m0->m_pkthdr.l4hlen; 5753 wr->u.tcpseg.tsclk_tsoff = mbuf_eo_tsclk_tsoff(m0); 5754 wr->u.tcpseg.r4 = 0; 5755 wr->u.tcpseg.r5 = 0; 5756 wr->u.tcpseg.plen = htobe32(pktlen - immhdrs); 5757 5758 if (needs_tso(m0)) { 5759 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1); 5760 5761 wr->u.tcpseg.mss = htobe16(m0->m_pkthdr.tso_segsz); 5762 5763 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | 5764 F_LSO_FIRST_SLICE | F_LSO_LAST_SLICE | 5765 V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) | 5766 V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2); 5767 if (m0->m_pkthdr.l2hlen == sizeof(struct ether_vlan_header)) 5768 ctrl |= V_LSO_ETHHDR_LEN(1); 5769 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 5770 ctrl |= F_LSO_IPV6; 5771 lso->lso_ctrl = htobe32(ctrl); 5772 lso->ipid_ofst = htobe16(0); 5773 lso->mss = htobe16(m0->m_pkthdr.tso_segsz); 5774 lso->seqno_offset = htobe32(0); 5775 lso->len = htobe32(pktlen); 5776 5777 cpl = (void *)(lso + 1); 5778 } else { 5779 wr->u.tcpseg.mss = htobe16(0xffff); 5780 cpl = (void *)(wr + 1); 5781 } 5782 } 5783 5784 /* Checksum offload must be requested for ethofld. */ 5785 ctrl1 = 0; 5786 MPASS(needs_l4_csum(m0)); 5787 5788 /* VLAN tag insertion */ 5789 if (needs_vlan_insertion(m0)) { 5790 ctrl1 |= F_TXPKT_VLAN_VLD | 5791 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 5792 } 5793 5794 /* CPL header */ 5795 cpl->ctrl0 = cst->ctrl0; 5796 cpl->pack = 0; 5797 cpl->len = htobe16(pktlen); 5798 cpl->ctrl1 = htobe64(ctrl1); 5799 5800 /* Copy Ethernet, IP & TCP/UDP hdrs as immediate data */ 5801 p = (uintptr_t)(cpl + 1); 5802 m_copydata(m0, 0, immhdrs, (void *)p); 5803 5804 /* SGL */ 5805 dst = (void *)(cpl + 1); 5806 if (nsegs > 0) { 5807 int i, pad; 5808 5809 /* zero-pad upto next 16Byte boundary, if not 16Byte aligned */ 5810 p += immhdrs; 5811 pad = 16 - (immhdrs & 0xf); 5812 bzero((void *)p, pad); 5813 5814 usgl = (void *)(p + pad); 5815 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 5816 V_ULPTX_NSGE(nsegs)); 5817 5818 sglist_init(&sg, nitems(segs), segs); 5819 for (; m0 != NULL; m0 = m0->m_next) { 5820 if (__predict_false(m0->m_len == 0)) 5821 continue; 5822 if (immhdrs >= m0->m_len) { 5823 immhdrs -= m0->m_len; 5824 continue; 5825 } 5826 5827 sglist_append(&sg, mtod(m0, char *) + immhdrs, 5828 m0->m_len - immhdrs); 5829 immhdrs = 0; 5830 } 5831 MPASS(sg.sg_nseg == nsegs); 5832 5833 /* 5834 * Zero pad last 8B in case the WR doesn't end on a 16B 5835 * boundary. 5836 */ 5837 *(uint64_t *)((char *)wr + len16 * 16 - 8) = 0; 5838 5839 usgl->len0 = htobe32(segs[0].ss_len); 5840 usgl->addr0 = htobe64(segs[0].ss_paddr); 5841 for (i = 0; i < nsegs - 1; i++) { 5842 usgl->sge[i / 2].len[i & 1] = htobe32(segs[i + 1].ss_len); 5843 usgl->sge[i / 2].addr[i & 1] = htobe64(segs[i + 1].ss_paddr); 5844 } 5845 if (i & 1) 5846 usgl->sge[i / 2].len[1] = htobe32(0); 5847 } 5848 5849 } 5850 5851 static void 5852 ethofld_tx(struct cxgbe_snd_tag *cst) 5853 { 5854 struct mbuf *m; 5855 struct wrq_cookie cookie; 5856 int next_credits, compl; 5857 struct fw_eth_tx_eo_wr *wr; 5858 5859 mtx_assert(&cst->lock, MA_OWNED); 5860 5861 while ((m = mbufq_first(&cst->pending_tx)) != NULL) { 5862 M_ASSERTPKTHDR(m); 5863 5864 /* How many len16 credits do we need to send this mbuf. */ 5865 next_credits = mbuf_eo_len16(m); 5866 MPASS(next_credits > 0); 5867 if (next_credits > cst->tx_credits) { 5868 /* 5869 * Tx will make progress eventually because there is at 5870 * least one outstanding fw4_ack that will return 5871 * credits and kick the tx. 5872 */ 5873 MPASS(cst->ncompl > 0); 5874 return; 5875 } 5876 wr = start_wrq_wr(cst->eo_txq, next_credits, &cookie); 5877 if (__predict_false(wr == NULL)) { 5878 /* XXX: wishful thinking, not a real assertion. */ 5879 MPASS(cst->ncompl > 0); 5880 return; 5881 } 5882 cst->tx_credits -= next_credits; 5883 cst->tx_nocompl += next_credits; 5884 compl = cst->ncompl == 0 || cst->tx_nocompl >= cst->tx_total / 2; 5885 ETHER_BPF_MTAP(cst->com.ifp, m); 5886 write_ethofld_wr(cst, wr, m, compl); 5887 commit_wrq_wr(cst->eo_txq, wr, &cookie); 5888 if (compl) { 5889 cst->ncompl++; 5890 cst->tx_nocompl = 0; 5891 } 5892 (void) mbufq_dequeue(&cst->pending_tx); 5893 mbufq_enqueue(&cst->pending_fwack, m); 5894 } 5895 } 5896 5897 int 5898 ethofld_transmit(struct ifnet *ifp, struct mbuf *m0) 5899 { 5900 struct cxgbe_snd_tag *cst; 5901 int rc; 5902 5903 MPASS(m0->m_nextpkt == NULL); 5904 MPASS(m0->m_pkthdr.snd_tag != NULL); 5905 cst = mst_to_cst(m0->m_pkthdr.snd_tag); 5906 5907 mtx_lock(&cst->lock); 5908 MPASS(cst->flags & EO_SND_TAG_REF); 5909 5910 if (__predict_false(cst->flags & EO_FLOWC_PENDING)) { 5911 struct vi_info *vi = ifp->if_softc; 5912 struct port_info *pi = vi->pi; 5913 struct adapter *sc = pi->adapter; 5914 const uint32_t rss_mask = vi->rss_size - 1; 5915 uint32_t rss_hash; 5916 5917 cst->eo_txq = &sc->sge.ofld_txq[vi->first_ofld_txq]; 5918 if (M_HASHTYPE_ISHASH(m0)) 5919 rss_hash = m0->m_pkthdr.flowid; 5920 else 5921 rss_hash = arc4random(); 5922 /* We assume RSS hashing */ 5923 cst->iqid = vi->rss[rss_hash & rss_mask]; 5924 cst->eo_txq += rss_hash % vi->nofldtxq; 5925 rc = send_etid_flowc_wr(cst, pi, vi); 5926 if (rc != 0) 5927 goto done; 5928 } 5929 5930 if (__predict_false(cst->plen + m0->m_pkthdr.len > eo_max_backlog)) { 5931 rc = ENOBUFS; 5932 goto done; 5933 } 5934 5935 mbufq_enqueue(&cst->pending_tx, m0); 5936 cst->plen += m0->m_pkthdr.len; 5937 5938 ethofld_tx(cst); 5939 rc = 0; 5940 done: 5941 mtx_unlock(&cst->lock); 5942 if (__predict_false(rc != 0)) 5943 m_freem(m0); 5944 return (rc); 5945 } 5946 5947 static int 5948 ethofld_fw4_ack(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0) 5949 { 5950 struct adapter *sc = iq->adapter; 5951 const struct cpl_fw4_ack *cpl = (const void *)(rss + 1); 5952 struct mbuf *m; 5953 u_int etid = G_CPL_FW4_ACK_FLOWID(be32toh(OPCODE_TID(cpl))); 5954 struct cxgbe_snd_tag *cst; 5955 uint8_t credits = cpl->credits; 5956 5957 cst = lookup_etid(sc, etid); 5958 mtx_lock(&cst->lock); 5959 if (__predict_false(cst->flags & EO_FLOWC_RPL_PENDING)) { 5960 MPASS(credits >= ETID_FLOWC_LEN16); 5961 credits -= ETID_FLOWC_LEN16; 5962 cst->flags &= ~EO_FLOWC_RPL_PENDING; 5963 } 5964 5965 KASSERT(cst->ncompl > 0, 5966 ("%s: etid %u (%p) wasn't expecting completion.", 5967 __func__, etid, cst)); 5968 cst->ncompl--; 5969 5970 while (credits > 0) { 5971 m = mbufq_dequeue(&cst->pending_fwack); 5972 if (__predict_false(m == NULL)) { 5973 /* 5974 * The remaining credits are for the final flush that 5975 * was issued when the tag was freed by the kernel. 5976 */ 5977 MPASS((cst->flags & 5978 (EO_FLUSH_RPL_PENDING | EO_SND_TAG_REF)) == 5979 EO_FLUSH_RPL_PENDING); 5980 MPASS(credits == ETID_FLUSH_LEN16); 5981 MPASS(cst->tx_credits + cpl->credits == cst->tx_total); 5982 MPASS(cst->ncompl == 0); 5983 5984 cst->flags &= ~EO_FLUSH_RPL_PENDING; 5985 cst->tx_credits += cpl->credits; 5986 freetag: 5987 cxgbe_snd_tag_free_locked(cst); 5988 return (0); /* cst is gone. */ 5989 } 5990 KASSERT(m != NULL, 5991 ("%s: too many credits (%u, %u)", __func__, cpl->credits, 5992 credits)); 5993 KASSERT(credits >= mbuf_eo_len16(m), 5994 ("%s: too few credits (%u, %u, %u)", __func__, 5995 cpl->credits, credits, mbuf_eo_len16(m))); 5996 credits -= mbuf_eo_len16(m); 5997 cst->plen -= m->m_pkthdr.len; 5998 m_freem(m); 5999 } 6000 6001 cst->tx_credits += cpl->credits; 6002 MPASS(cst->tx_credits <= cst->tx_total); 6003 6004 m = mbufq_first(&cst->pending_tx); 6005 if (m != NULL && cst->tx_credits >= mbuf_eo_len16(m)) 6006 ethofld_tx(cst); 6007 6008 if (__predict_false((cst->flags & EO_SND_TAG_REF) == 0) && 6009 cst->ncompl == 0) { 6010 if (cst->tx_credits == cst->tx_total) 6011 goto freetag; 6012 else { 6013 MPASS((cst->flags & EO_FLUSH_RPL_PENDING) == 0); 6014 send_etid_flush_wr(cst); 6015 } 6016 } 6017 6018 mtx_unlock(&cst->lock); 6019 6020 return (0); 6021 } 6022 #endif 6023