1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2011 Chelsio Communications, Inc. 5 * All rights reserved. 6 * Written by: Navdeep Parhar <np@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 #include "opt_kern_tls.h" 34 #include "opt_ratelimit.h" 35 36 #include <sys/types.h> 37 #include <sys/eventhandler.h> 38 #include <sys/mbuf.h> 39 #include <sys/socket.h> 40 #include <sys/kernel.h> 41 #include <sys/ktls.h> 42 #include <sys/malloc.h> 43 #include <sys/msan.h> 44 #include <sys/queue.h> 45 #include <sys/sbuf.h> 46 #include <sys/taskqueue.h> 47 #include <sys/time.h> 48 #include <sys/sglist.h> 49 #include <sys/sysctl.h> 50 #include <sys/smp.h> 51 #include <sys/socketvar.h> 52 #include <sys/counter.h> 53 #include <net/bpf.h> 54 #include <net/ethernet.h> 55 #include <net/if.h> 56 #include <net/if_vlan_var.h> 57 #include <net/if_vxlan.h> 58 #include <netinet/in.h> 59 #include <netinet/ip.h> 60 #include <netinet/ip6.h> 61 #include <netinet/tcp.h> 62 #include <netinet/udp.h> 63 #include <machine/in_cksum.h> 64 #include <machine/md_var.h> 65 #include <vm/vm.h> 66 #include <vm/pmap.h> 67 #ifdef DEV_NETMAP 68 #include <machine/bus.h> 69 #include <sys/selinfo.h> 70 #include <net/if_var.h> 71 #include <net/netmap.h> 72 #include <dev/netmap/netmap_kern.h> 73 #endif 74 75 #include "common/common.h" 76 #include "common/t4_regs.h" 77 #include "common/t4_regs_values.h" 78 #include "common/t4_msg.h" 79 #include "t4_l2t.h" 80 #include "t4_mp_ring.h" 81 82 #define RX_COPY_THRESHOLD MINCLSIZE 83 84 /* 85 * Ethernet frames are DMA'd at this byte offset into the freelist buffer. 86 * 0-7 are valid values. 87 */ 88 static int fl_pktshift = 0; 89 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pktshift, CTLFLAG_RDTUN, &fl_pktshift, 0, 90 "payload DMA offset in rx buffer (bytes)"); 91 92 /* 93 * Pad ethernet payload up to this boundary. 94 * -1: driver should figure out a good value. 95 * 0: disable padding. 96 * Any power of 2 from 32 to 4096 (both inclusive) is also a valid value. 97 */ 98 int fl_pad = -1; 99 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pad, CTLFLAG_RDTUN, &fl_pad, 0, 100 "payload pad boundary (bytes)"); 101 102 /* 103 * Status page length. 104 * -1: driver should figure out a good value. 105 * 64 or 128 are the only other valid values. 106 */ 107 static int spg_len = -1; 108 SYSCTL_INT(_hw_cxgbe, OID_AUTO, spg_len, CTLFLAG_RDTUN, &spg_len, 0, 109 "status page size (bytes)"); 110 111 /* 112 * Congestion drops. 113 * -1: no congestion feedback (not recommended). 114 * 0: backpressure the channel instead of dropping packets right away. 115 * 1: no backpressure, drop packets for the congested queue immediately. 116 * 2: both backpressure and drop. 117 */ 118 static int cong_drop = 0; 119 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cong_drop, CTLFLAG_RDTUN, &cong_drop, 0, 120 "Congestion control for NIC RX queues (0 = backpressure, 1 = drop, 2 = both"); 121 #ifdef TCP_OFFLOAD 122 static int ofld_cong_drop = 0; 123 SYSCTL_INT(_hw_cxgbe, OID_AUTO, ofld_cong_drop, CTLFLAG_RDTUN, &ofld_cong_drop, 0, 124 "Congestion control for TOE RX queues (0 = backpressure, 1 = drop, 2 = both"); 125 #endif 126 127 /* 128 * Deliver multiple frames in the same free list buffer if they fit. 129 * -1: let the driver decide whether to enable buffer packing or not. 130 * 0: disable buffer packing. 131 * 1: enable buffer packing. 132 */ 133 static int buffer_packing = -1; 134 SYSCTL_INT(_hw_cxgbe, OID_AUTO, buffer_packing, CTLFLAG_RDTUN, &buffer_packing, 135 0, "Enable buffer packing"); 136 137 /* 138 * Start next frame in a packed buffer at this boundary. 139 * -1: driver should figure out a good value. 140 * T4: driver will ignore this and use the same value as fl_pad above. 141 * T5: 16, or a power of 2 from 64 to 4096 (both inclusive) is a valid value. 142 */ 143 static int fl_pack = -1; 144 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pack, CTLFLAG_RDTUN, &fl_pack, 0, 145 "payload pack boundary (bytes)"); 146 147 /* 148 * Largest rx cluster size that the driver is allowed to allocate. 149 */ 150 static int largest_rx_cluster = MJUM16BYTES; 151 SYSCTL_INT(_hw_cxgbe, OID_AUTO, largest_rx_cluster, CTLFLAG_RDTUN, 152 &largest_rx_cluster, 0, "Largest rx cluster (bytes)"); 153 154 /* 155 * Size of cluster allocation that's most likely to succeed. The driver will 156 * fall back to this size if it fails to allocate clusters larger than this. 157 */ 158 static int safest_rx_cluster = PAGE_SIZE; 159 SYSCTL_INT(_hw_cxgbe, OID_AUTO, safest_rx_cluster, CTLFLAG_RDTUN, 160 &safest_rx_cluster, 0, "Safe rx cluster (bytes)"); 161 162 #ifdef RATELIMIT 163 /* 164 * Knob to control TCP timestamp rewriting, and the granularity of the tick used 165 * for rewriting. -1 and 0-3 are all valid values. 166 * -1: hardware should leave the TCP timestamps alone. 167 * 0: 1ms 168 * 1: 100us 169 * 2: 10us 170 * 3: 1us 171 */ 172 static int tsclk = -1; 173 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tsclk, CTLFLAG_RDTUN, &tsclk, 0, 174 "Control TCP timestamp rewriting when using pacing"); 175 176 static int eo_max_backlog = 1024 * 1024; 177 SYSCTL_INT(_hw_cxgbe, OID_AUTO, eo_max_backlog, CTLFLAG_RDTUN, &eo_max_backlog, 178 0, "Maximum backlog of ratelimited data per flow"); 179 #endif 180 181 /* 182 * The interrupt holdoff timers are multiplied by this value on T6+. 183 * 1 and 3-17 (both inclusive) are legal values. 184 */ 185 static int tscale = 1; 186 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tscale, CTLFLAG_RDTUN, &tscale, 0, 187 "Interrupt holdoff timer scale on T6+"); 188 189 /* 190 * Number of LRO entries in the lro_ctrl structure per rx queue. 191 */ 192 static int lro_entries = TCP_LRO_ENTRIES; 193 SYSCTL_INT(_hw_cxgbe, OID_AUTO, lro_entries, CTLFLAG_RDTUN, &lro_entries, 0, 194 "Number of LRO entries per RX queue"); 195 196 /* 197 * This enables presorting of frames before they're fed into tcp_lro_rx. 198 */ 199 static int lro_mbufs = 0; 200 SYSCTL_INT(_hw_cxgbe, OID_AUTO, lro_mbufs, CTLFLAG_RDTUN, &lro_mbufs, 0, 201 "Enable presorting of LRO frames"); 202 203 static counter_u64_t pullups; 204 SYSCTL_COUNTER_U64(_hw_cxgbe, OID_AUTO, pullups, CTLFLAG_RD, &pullups, 205 "Number of mbuf pullups performed"); 206 207 static counter_u64_t defrags; 208 SYSCTL_COUNTER_U64(_hw_cxgbe, OID_AUTO, defrags, CTLFLAG_RD, &defrags, 209 "Number of mbuf defrags performed"); 210 211 static int t4_tx_coalesce = 1; 212 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tx_coalesce, CTLFLAG_RWTUN, &t4_tx_coalesce, 0, 213 "tx coalescing allowed"); 214 215 /* 216 * The driver will make aggressive attempts at tx coalescing if it sees these 217 * many packets eligible for coalescing in quick succession, with no more than 218 * the specified gap in between the eth_tx calls that delivered the packets. 219 */ 220 static int t4_tx_coalesce_pkts = 32; 221 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tx_coalesce_pkts, CTLFLAG_RWTUN, 222 &t4_tx_coalesce_pkts, 0, 223 "# of consecutive packets (1 - 255) that will trigger tx coalescing"); 224 static int t4_tx_coalesce_gap = 5; 225 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tx_coalesce_gap, CTLFLAG_RWTUN, 226 &t4_tx_coalesce_gap, 0, "tx gap (in microseconds)"); 227 228 static int service_iq(struct sge_iq *, int); 229 static int service_iq_fl(struct sge_iq *, int); 230 static struct mbuf *get_fl_payload(struct adapter *, struct sge_fl *, uint32_t); 231 static int eth_rx(struct adapter *, struct sge_rxq *, const struct iq_desc *, 232 u_int); 233 static inline void init_iq(struct sge_iq *, struct adapter *, int, int, int, 234 int, int, int); 235 static inline void init_fl(struct adapter *, struct sge_fl *, int, int, char *); 236 static inline void init_eq(struct adapter *, struct sge_eq *, int, int, uint8_t, 237 struct sge_iq *, char *); 238 static int alloc_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *, 239 struct sysctl_ctx_list *, struct sysctl_oid *); 240 static void free_iq_fl(struct adapter *, struct sge_iq *, struct sge_fl *); 241 static void add_iq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *, 242 struct sge_iq *); 243 static void add_fl_sysctls(struct adapter *, struct sysctl_ctx_list *, 244 struct sysctl_oid *, struct sge_fl *); 245 static int alloc_iq_fl_hwq(struct vi_info *, struct sge_iq *, struct sge_fl *); 246 static int free_iq_fl_hwq(struct adapter *, struct sge_iq *, struct sge_fl *); 247 static int alloc_fwq(struct adapter *); 248 static void free_fwq(struct adapter *); 249 static int alloc_ctrlq(struct adapter *, int); 250 static void free_ctrlq(struct adapter *, int); 251 static int alloc_rxq(struct vi_info *, struct sge_rxq *, int, int, int); 252 static void free_rxq(struct vi_info *, struct sge_rxq *); 253 static void add_rxq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *, 254 struct sge_rxq *); 255 #ifdef TCP_OFFLOAD 256 static int alloc_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *, int, int, 257 int); 258 static void free_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *); 259 static void add_ofld_rxq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *, 260 struct sge_ofld_rxq *); 261 #endif 262 static int ctrl_eq_alloc(struct adapter *, struct sge_eq *); 263 static int eth_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *); 264 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 265 static int ofld_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *); 266 #endif 267 static int alloc_eq(struct adapter *, struct sge_eq *, struct sysctl_ctx_list *, 268 struct sysctl_oid *); 269 static void free_eq(struct adapter *, struct sge_eq *); 270 static void add_eq_sysctls(struct adapter *, struct sysctl_ctx_list *, 271 struct sysctl_oid *, struct sge_eq *); 272 static int alloc_eq_hwq(struct adapter *, struct vi_info *, struct sge_eq *); 273 static int free_eq_hwq(struct adapter *, struct vi_info *, struct sge_eq *); 274 static int alloc_wrq(struct adapter *, struct vi_info *, struct sge_wrq *, 275 struct sysctl_ctx_list *, struct sysctl_oid *); 276 static void free_wrq(struct adapter *, struct sge_wrq *); 277 static void add_wrq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *, 278 struct sge_wrq *); 279 static int alloc_txq(struct vi_info *, struct sge_txq *, int); 280 static void free_txq(struct vi_info *, struct sge_txq *); 281 static void add_txq_sysctls(struct vi_info *, struct sysctl_ctx_list *, 282 struct sysctl_oid *, struct sge_txq *); 283 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 284 static int alloc_ofld_txq(struct vi_info *, struct sge_ofld_txq *, int); 285 static void free_ofld_txq(struct vi_info *, struct sge_ofld_txq *); 286 static void add_ofld_txq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *, 287 struct sge_ofld_txq *); 288 #endif 289 static void oneseg_dma_callback(void *, bus_dma_segment_t *, int, int); 290 static inline void ring_fl_db(struct adapter *, struct sge_fl *); 291 static int refill_fl(struct adapter *, struct sge_fl *, int); 292 static void refill_sfl(void *); 293 static int find_refill_source(struct adapter *, int, bool); 294 static void add_fl_to_sfl(struct adapter *, struct sge_fl *); 295 296 static inline void get_pkt_gl(struct mbuf *, struct sglist *); 297 static inline u_int txpkt_len16(u_int, const u_int); 298 static inline u_int txpkt_vm_len16(u_int, const u_int); 299 static inline void calculate_mbuf_len16(struct mbuf *, bool); 300 static inline u_int txpkts0_len16(u_int); 301 static inline u_int txpkts1_len16(void); 302 static u_int write_raw_wr(struct sge_txq *, void *, struct mbuf *, u_int); 303 static u_int write_txpkt_wr(struct adapter *, struct sge_txq *, struct mbuf *, 304 u_int); 305 static u_int write_txpkt_vm_wr(struct adapter *, struct sge_txq *, 306 struct mbuf *); 307 static int add_to_txpkts_vf(struct adapter *, struct sge_txq *, struct mbuf *, 308 int, bool *); 309 static int add_to_txpkts_pf(struct adapter *, struct sge_txq *, struct mbuf *, 310 int, bool *); 311 static u_int write_txpkts_wr(struct adapter *, struct sge_txq *); 312 static u_int write_txpkts_vm_wr(struct adapter *, struct sge_txq *); 313 static void write_gl_to_txd(struct sge_txq *, struct mbuf *, caddr_t *, int); 314 static inline void copy_to_txd(struct sge_eq *, caddr_t, caddr_t *, int); 315 static inline void ring_eq_db(struct adapter *, struct sge_eq *, u_int); 316 static inline uint16_t read_hw_cidx(struct sge_eq *); 317 static inline u_int reclaimable_tx_desc(struct sge_eq *); 318 static inline u_int total_available_tx_desc(struct sge_eq *); 319 static u_int reclaim_tx_descs(struct sge_txq *, u_int); 320 static void tx_reclaim(void *, int); 321 static __be64 get_flit(struct sglist_seg *, int, int); 322 static int handle_sge_egr_update(struct sge_iq *, const struct rss_header *, 323 struct mbuf *); 324 static int handle_fw_msg(struct sge_iq *, const struct rss_header *, 325 struct mbuf *); 326 static int t4_handle_wrerr_rpl(struct adapter *, const __be64 *); 327 static void wrq_tx_drain(void *, int); 328 static void drain_wrq_wr_list(struct adapter *, struct sge_wrq *); 329 330 static int sysctl_bufsizes(SYSCTL_HANDLER_ARGS); 331 #ifdef RATELIMIT 332 static int ethofld_fw4_ack(struct sge_iq *, const struct rss_header *, 333 struct mbuf *); 334 #if defined(INET) || defined(INET6) 335 static inline u_int txpkt_eo_len16(u_int, u_int, u_int); 336 static int ethofld_transmit(if_t, struct mbuf *); 337 #endif 338 #endif 339 340 static counter_u64_t extfree_refs; 341 static counter_u64_t extfree_rels; 342 343 an_handler_t t4_an_handler; 344 fw_msg_handler_t t4_fw_msg_handler[NUM_FW6_TYPES]; 345 cpl_handler_t t4_cpl_handler[NUM_CPL_CMDS]; 346 cpl_handler_t set_tcb_rpl_handlers[NUM_CPL_COOKIES]; 347 cpl_handler_t l2t_write_rpl_handlers[NUM_CPL_COOKIES]; 348 cpl_handler_t act_open_rpl_handlers[NUM_CPL_COOKIES]; 349 cpl_handler_t abort_rpl_rss_handlers[NUM_CPL_COOKIES]; 350 cpl_handler_t fw4_ack_handlers[NUM_CPL_COOKIES]; 351 352 void 353 t4_register_an_handler(an_handler_t h) 354 { 355 uintptr_t *loc; 356 357 MPASS(h == NULL || t4_an_handler == NULL); 358 359 loc = (uintptr_t *)&t4_an_handler; 360 atomic_store_rel_ptr(loc, (uintptr_t)h); 361 } 362 363 void 364 t4_register_fw_msg_handler(int type, fw_msg_handler_t h) 365 { 366 uintptr_t *loc; 367 368 MPASS(type < nitems(t4_fw_msg_handler)); 369 MPASS(h == NULL || t4_fw_msg_handler[type] == NULL); 370 /* 371 * These are dispatched by the handler for FW{4|6}_CPL_MSG using the CPL 372 * handler dispatch table. Reject any attempt to install a handler for 373 * this subtype. 374 */ 375 MPASS(type != FW_TYPE_RSSCPL); 376 MPASS(type != FW6_TYPE_RSSCPL); 377 378 loc = (uintptr_t *)&t4_fw_msg_handler[type]; 379 atomic_store_rel_ptr(loc, (uintptr_t)h); 380 } 381 382 void 383 t4_register_cpl_handler(int opcode, cpl_handler_t h) 384 { 385 uintptr_t *loc; 386 387 MPASS(opcode < nitems(t4_cpl_handler)); 388 MPASS(h == NULL || t4_cpl_handler[opcode] == NULL); 389 390 loc = (uintptr_t *)&t4_cpl_handler[opcode]; 391 atomic_store_rel_ptr(loc, (uintptr_t)h); 392 } 393 394 static int 395 set_tcb_rpl_handler(struct sge_iq *iq, const struct rss_header *rss, 396 struct mbuf *m) 397 { 398 const struct cpl_set_tcb_rpl *cpl = (const void *)(rss + 1); 399 u_int tid; 400 int cookie; 401 402 MPASS(m == NULL); 403 404 tid = GET_TID(cpl); 405 if (is_hpftid(iq->adapter, tid) || is_ftid(iq->adapter, tid)) { 406 /* 407 * The return code for filter-write is put in the CPL cookie so 408 * we have to rely on the hardware tid (is_ftid) to determine 409 * that this is a response to a filter. 410 */ 411 cookie = CPL_COOKIE_FILTER; 412 } else { 413 cookie = G_COOKIE(cpl->cookie); 414 } 415 MPASS(cookie > CPL_COOKIE_RESERVED); 416 MPASS(cookie < nitems(set_tcb_rpl_handlers)); 417 418 return (set_tcb_rpl_handlers[cookie](iq, rss, m)); 419 } 420 421 static int 422 l2t_write_rpl_handler(struct sge_iq *iq, const struct rss_header *rss, 423 struct mbuf *m) 424 { 425 const struct cpl_l2t_write_rpl *rpl = (const void *)(rss + 1); 426 unsigned int cookie; 427 428 MPASS(m == NULL); 429 430 cookie = GET_TID(rpl) & F_SYNC_WR ? CPL_COOKIE_TOM : CPL_COOKIE_FILTER; 431 return (l2t_write_rpl_handlers[cookie](iq, rss, m)); 432 } 433 434 static int 435 act_open_rpl_handler(struct sge_iq *iq, const struct rss_header *rss, 436 struct mbuf *m) 437 { 438 const struct cpl_act_open_rpl *cpl = (const void *)(rss + 1); 439 u_int cookie = G_TID_COOKIE(G_AOPEN_ATID(be32toh(cpl->atid_status))); 440 441 MPASS(m == NULL); 442 MPASS(cookie != CPL_COOKIE_RESERVED); 443 444 return (act_open_rpl_handlers[cookie](iq, rss, m)); 445 } 446 447 static int 448 abort_rpl_rss_handler(struct sge_iq *iq, const struct rss_header *rss, 449 struct mbuf *m) 450 { 451 struct adapter *sc = iq->adapter; 452 u_int cookie; 453 454 MPASS(m == NULL); 455 if (is_hashfilter(sc)) 456 cookie = CPL_COOKIE_HASHFILTER; 457 else 458 cookie = CPL_COOKIE_TOM; 459 460 return (abort_rpl_rss_handlers[cookie](iq, rss, m)); 461 } 462 463 static int 464 fw4_ack_handler(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 465 { 466 struct adapter *sc = iq->adapter; 467 const struct cpl_fw4_ack *cpl = (const void *)(rss + 1); 468 unsigned int tid = G_CPL_FW4_ACK_FLOWID(be32toh(OPCODE_TID(cpl))); 469 u_int cookie; 470 471 MPASS(m == NULL); 472 if (is_etid(sc, tid)) 473 cookie = CPL_COOKIE_ETHOFLD; 474 else 475 cookie = CPL_COOKIE_TOM; 476 477 return (fw4_ack_handlers[cookie](iq, rss, m)); 478 } 479 480 static void 481 t4_init_shared_cpl_handlers(void) 482 { 483 484 t4_register_cpl_handler(CPL_SET_TCB_RPL, set_tcb_rpl_handler); 485 t4_register_cpl_handler(CPL_L2T_WRITE_RPL, l2t_write_rpl_handler); 486 t4_register_cpl_handler(CPL_ACT_OPEN_RPL, act_open_rpl_handler); 487 t4_register_cpl_handler(CPL_ABORT_RPL_RSS, abort_rpl_rss_handler); 488 t4_register_cpl_handler(CPL_FW4_ACK, fw4_ack_handler); 489 } 490 491 void 492 t4_register_shared_cpl_handler(int opcode, cpl_handler_t h, int cookie) 493 { 494 uintptr_t *loc; 495 496 MPASS(opcode < nitems(t4_cpl_handler)); 497 MPASS(cookie > CPL_COOKIE_RESERVED); 498 MPASS(cookie < NUM_CPL_COOKIES); 499 MPASS(t4_cpl_handler[opcode] != NULL); 500 501 switch (opcode) { 502 case CPL_SET_TCB_RPL: 503 loc = (uintptr_t *)&set_tcb_rpl_handlers[cookie]; 504 break; 505 case CPL_L2T_WRITE_RPL: 506 loc = (uintptr_t *)&l2t_write_rpl_handlers[cookie]; 507 break; 508 case CPL_ACT_OPEN_RPL: 509 loc = (uintptr_t *)&act_open_rpl_handlers[cookie]; 510 break; 511 case CPL_ABORT_RPL_RSS: 512 loc = (uintptr_t *)&abort_rpl_rss_handlers[cookie]; 513 break; 514 case CPL_FW4_ACK: 515 loc = (uintptr_t *)&fw4_ack_handlers[cookie]; 516 break; 517 default: 518 MPASS(0); 519 return; 520 } 521 MPASS(h == NULL || *loc == (uintptr_t)NULL); 522 atomic_store_rel_ptr(loc, (uintptr_t)h); 523 } 524 525 /* 526 * Called on MOD_LOAD. Validates and calculates the SGE tunables. 527 */ 528 void 529 t4_sge_modload(void) 530 { 531 532 if (fl_pktshift < 0 || fl_pktshift > 7) { 533 printf("Invalid hw.cxgbe.fl_pktshift value (%d)," 534 " using 0 instead.\n", fl_pktshift); 535 fl_pktshift = 0; 536 } 537 538 if (spg_len != 64 && spg_len != 128) { 539 int len; 540 541 #if defined(__i386__) || defined(__amd64__) 542 len = cpu_clflush_line_size > 64 ? 128 : 64; 543 #else 544 len = 64; 545 #endif 546 if (spg_len != -1) { 547 printf("Invalid hw.cxgbe.spg_len value (%d)," 548 " using %d instead.\n", spg_len, len); 549 } 550 spg_len = len; 551 } 552 553 if (cong_drop < -1 || cong_drop > 2) { 554 printf("Invalid hw.cxgbe.cong_drop value (%d)," 555 " using 0 instead.\n", cong_drop); 556 cong_drop = 0; 557 } 558 #ifdef TCP_OFFLOAD 559 if (ofld_cong_drop < -1 || ofld_cong_drop > 2) { 560 printf("Invalid hw.cxgbe.ofld_cong_drop value (%d)," 561 " using 0 instead.\n", ofld_cong_drop); 562 ofld_cong_drop = 0; 563 } 564 #endif 565 566 if (tscale != 1 && (tscale < 3 || tscale > 17)) { 567 printf("Invalid hw.cxgbe.tscale value (%d)," 568 " using 1 instead.\n", tscale); 569 tscale = 1; 570 } 571 572 if (largest_rx_cluster != MCLBYTES && 573 largest_rx_cluster != MJUMPAGESIZE && 574 largest_rx_cluster != MJUM9BYTES && 575 largest_rx_cluster != MJUM16BYTES) { 576 printf("Invalid hw.cxgbe.largest_rx_cluster value (%d)," 577 " using %d instead.\n", largest_rx_cluster, MJUM16BYTES); 578 largest_rx_cluster = MJUM16BYTES; 579 } 580 581 if (safest_rx_cluster != MCLBYTES && 582 safest_rx_cluster != MJUMPAGESIZE && 583 safest_rx_cluster != MJUM9BYTES && 584 safest_rx_cluster != MJUM16BYTES) { 585 printf("Invalid hw.cxgbe.safest_rx_cluster value (%d)," 586 " using %d instead.\n", safest_rx_cluster, MJUMPAGESIZE); 587 safest_rx_cluster = MJUMPAGESIZE; 588 } 589 590 extfree_refs = counter_u64_alloc(M_WAITOK); 591 extfree_rels = counter_u64_alloc(M_WAITOK); 592 pullups = counter_u64_alloc(M_WAITOK); 593 defrags = counter_u64_alloc(M_WAITOK); 594 counter_u64_zero(extfree_refs); 595 counter_u64_zero(extfree_rels); 596 counter_u64_zero(pullups); 597 counter_u64_zero(defrags); 598 599 t4_init_shared_cpl_handlers(); 600 t4_register_cpl_handler(CPL_FW4_MSG, handle_fw_msg); 601 t4_register_cpl_handler(CPL_FW6_MSG, handle_fw_msg); 602 t4_register_cpl_handler(CPL_SGE_EGR_UPDATE, handle_sge_egr_update); 603 #ifdef RATELIMIT 604 t4_register_shared_cpl_handler(CPL_FW4_ACK, ethofld_fw4_ack, 605 CPL_COOKIE_ETHOFLD); 606 #endif 607 t4_register_fw_msg_handler(FW6_TYPE_CMD_RPL, t4_handle_fw_rpl); 608 t4_register_fw_msg_handler(FW6_TYPE_WRERR_RPL, t4_handle_wrerr_rpl); 609 } 610 611 void 612 t4_sge_modunload(void) 613 { 614 615 counter_u64_free(extfree_refs); 616 counter_u64_free(extfree_rels); 617 counter_u64_free(pullups); 618 counter_u64_free(defrags); 619 } 620 621 uint64_t 622 t4_sge_extfree_refs(void) 623 { 624 uint64_t refs, rels; 625 626 rels = counter_u64_fetch(extfree_rels); 627 refs = counter_u64_fetch(extfree_refs); 628 629 return (refs - rels); 630 } 631 632 /* max 4096 */ 633 #define MAX_PACK_BOUNDARY 512 634 635 static inline void 636 setup_pad_and_pack_boundaries(struct adapter *sc) 637 { 638 uint32_t v, m; 639 int pad, pack, pad_shift; 640 641 pad_shift = chip_id(sc) > CHELSIO_T5 ? X_T6_INGPADBOUNDARY_SHIFT : 642 X_INGPADBOUNDARY_SHIFT; 643 pad = fl_pad; 644 if (fl_pad < (1 << pad_shift) || 645 fl_pad > (1 << (pad_shift + M_INGPADBOUNDARY)) || 646 !powerof2(fl_pad)) { 647 /* 648 * If there is any chance that we might use buffer packing and 649 * the chip is a T4, then pick 64 as the pad/pack boundary. Set 650 * it to the minimum allowed in all other cases. 651 */ 652 pad = is_t4(sc) && buffer_packing ? 64 : 1 << pad_shift; 653 654 /* 655 * For fl_pad = 0 we'll still write a reasonable value to the 656 * register but all the freelists will opt out of padding. 657 * We'll complain here only if the user tried to set it to a 658 * value greater than 0 that was invalid. 659 */ 660 if (fl_pad > 0) { 661 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pad value" 662 " (%d), using %d instead.\n", fl_pad, pad); 663 } 664 } 665 m = V_INGPADBOUNDARY(M_INGPADBOUNDARY); 666 v = V_INGPADBOUNDARY(ilog2(pad) - pad_shift); 667 t4_set_reg_field(sc, A_SGE_CONTROL, m, v); 668 669 if (is_t4(sc)) { 670 if (fl_pack != -1 && fl_pack != pad) { 671 /* Complain but carry on. */ 672 device_printf(sc->dev, "hw.cxgbe.fl_pack (%d) ignored," 673 " using %d instead.\n", fl_pack, pad); 674 } 675 return; 676 } 677 678 pack = fl_pack; 679 if (fl_pack < 16 || fl_pack == 32 || fl_pack > 4096 || 680 !powerof2(fl_pack)) { 681 if (sc->params.pci.mps > MAX_PACK_BOUNDARY) 682 pack = MAX_PACK_BOUNDARY; 683 else 684 pack = max(sc->params.pci.mps, CACHE_LINE_SIZE); 685 MPASS(powerof2(pack)); 686 if (pack < 16) 687 pack = 16; 688 if (pack == 32) 689 pack = 64; 690 if (pack > 4096) 691 pack = 4096; 692 if (fl_pack != -1) { 693 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pack value" 694 " (%d), using %d instead.\n", fl_pack, pack); 695 } 696 } 697 m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY); 698 if (pack == 16) 699 v = V_INGPACKBOUNDARY(0); 700 else 701 v = V_INGPACKBOUNDARY(ilog2(pack) - 5); 702 703 MPASS(!is_t4(sc)); /* T4 doesn't have SGE_CONTROL2 */ 704 t4_set_reg_field(sc, A_SGE_CONTROL2, m, v); 705 } 706 707 /* 708 * adap->params.vpd.cclk must be set up before this is called. 709 */ 710 void 711 t4_tweak_chip_settings(struct adapter *sc) 712 { 713 int i, reg; 714 uint32_t v, m; 715 int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200}; 716 int timer_max = M_TIMERVALUE0 * 1000 / sc->params.vpd.cclk; 717 int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */ 718 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 719 static int sw_buf_sizes[] = { 720 MCLBYTES, 721 MJUMPAGESIZE, 722 MJUM9BYTES, 723 MJUM16BYTES 724 }; 725 726 KASSERT(sc->flags & MASTER_PF, 727 ("%s: trying to change chip settings when not master.", __func__)); 728 729 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE; 730 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE | 731 V_EGRSTATUSPAGESIZE(spg_len == 128); 732 t4_set_reg_field(sc, A_SGE_CONTROL, m, v); 733 734 setup_pad_and_pack_boundaries(sc); 735 736 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) | 737 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) | 738 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) | 739 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) | 740 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) | 741 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) | 742 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) | 743 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10); 744 t4_write_reg(sc, A_SGE_HOST_PAGE_SIZE, v); 745 746 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0, 4096); 747 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE1, 65536); 748 reg = A_SGE_FL_BUFFER_SIZE2; 749 for (i = 0; i < nitems(sw_buf_sizes); i++) { 750 MPASS(reg <= A_SGE_FL_BUFFER_SIZE15); 751 t4_write_reg(sc, reg, sw_buf_sizes[i]); 752 reg += 4; 753 MPASS(reg <= A_SGE_FL_BUFFER_SIZE15); 754 t4_write_reg(sc, reg, sw_buf_sizes[i] - CL_METADATA_SIZE); 755 reg += 4; 756 } 757 758 v = V_THRESHOLD_0(intr_pktcount[0]) | V_THRESHOLD_1(intr_pktcount[1]) | 759 V_THRESHOLD_2(intr_pktcount[2]) | V_THRESHOLD_3(intr_pktcount[3]); 760 t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD, v); 761 762 KASSERT(intr_timer[0] <= timer_max, 763 ("%s: not a single usable timer (%d, %d)", __func__, intr_timer[0], 764 timer_max)); 765 for (i = 1; i < nitems(intr_timer); i++) { 766 KASSERT(intr_timer[i] >= intr_timer[i - 1], 767 ("%s: timers not listed in increasing order (%d)", 768 __func__, i)); 769 770 while (intr_timer[i] > timer_max) { 771 if (i == nitems(intr_timer) - 1) { 772 intr_timer[i] = timer_max; 773 break; 774 } 775 intr_timer[i] += intr_timer[i - 1]; 776 intr_timer[i] /= 2; 777 } 778 } 779 780 v = V_TIMERVALUE0(us_to_core_ticks(sc, intr_timer[0])) | 781 V_TIMERVALUE1(us_to_core_ticks(sc, intr_timer[1])); 782 t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1, v); 783 v = V_TIMERVALUE2(us_to_core_ticks(sc, intr_timer[2])) | 784 V_TIMERVALUE3(us_to_core_ticks(sc, intr_timer[3])); 785 t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3, v); 786 v = V_TIMERVALUE4(us_to_core_ticks(sc, intr_timer[4])) | 787 V_TIMERVALUE5(us_to_core_ticks(sc, intr_timer[5])); 788 t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5, v); 789 790 if (chip_id(sc) >= CHELSIO_T6) { 791 m = V_TSCALE(M_TSCALE); 792 if (tscale == 1) 793 v = 0; 794 else 795 v = V_TSCALE(tscale - 2); 796 t4_set_reg_field(sc, A_SGE_ITP_CONTROL, m, v); 797 798 if (sc->debug_flags & DF_DISABLE_TCB_CACHE) { 799 m = V_RDTHRESHOLD(M_RDTHRESHOLD) | F_WRTHRTHRESHEN | 800 V_WRTHRTHRESH(M_WRTHRTHRESH); 801 t4_tp_pio_read(sc, &v, 1, A_TP_CMM_CONFIG, 1); 802 v &= ~m; 803 v |= V_RDTHRESHOLD(1) | F_WRTHRTHRESHEN | 804 V_WRTHRTHRESH(16); 805 t4_tp_pio_write(sc, &v, 1, A_TP_CMM_CONFIG, 1); 806 } 807 } 808 809 /* 4K, 16K, 64K, 256K DDP "page sizes" for TDDP */ 810 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 811 t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, v); 812 813 /* 814 * 4K, 8K, 16K, 64K DDP "page sizes" for iSCSI DDP. These have been 815 * chosen with MAXPHYS = 128K in mind. The largest DDP buffer that we 816 * may have to deal with is MAXPHYS + 1 page. 817 */ 818 v = V_HPZ0(0) | V_HPZ1(1) | V_HPZ2(2) | V_HPZ3(4); 819 t4_write_reg(sc, A_ULP_RX_ISCSI_PSZ, v); 820 821 /* We use multiple DDP page sizes both in plain-TOE and ISCSI modes. */ 822 m = v = F_TDDPTAGTCB | F_ISCSITAGTCB; 823 t4_set_reg_field(sc, A_ULP_RX_CTL, m, v); 824 825 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 826 F_RESETDDPOFFSET; 827 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 828 t4_set_reg_field(sc, A_TP_PARA_REG5, m, v); 829 } 830 831 /* 832 * SGE wants the buffer to be at least 64B and then a multiple of 16. Its 833 * address mut be 16B aligned. If padding is in use the buffer's start and end 834 * need to be aligned to the pad boundary as well. We'll just make sure that 835 * the size is a multiple of the pad boundary here, it is up to the buffer 836 * allocation code to make sure the start of the buffer is aligned. 837 */ 838 static inline int 839 hwsz_ok(struct adapter *sc, int hwsz) 840 { 841 int mask = fl_pad ? sc->params.sge.pad_boundary - 1 : 16 - 1; 842 843 return (hwsz >= 64 && (hwsz & mask) == 0); 844 } 845 846 /* 847 * Initialize the rx buffer sizes and figure out which zones the buffers will 848 * be allocated from. 849 */ 850 void 851 t4_init_rx_buf_info(struct adapter *sc) 852 { 853 struct sge *s = &sc->sge; 854 struct sge_params *sp = &sc->params.sge; 855 int i, j, n; 856 static int sw_buf_sizes[] = { /* Sorted by size */ 857 MCLBYTES, 858 MJUMPAGESIZE, 859 MJUM9BYTES, 860 MJUM16BYTES 861 }; 862 struct rx_buf_info *rxb; 863 864 s->safe_zidx = -1; 865 rxb = &s->rx_buf_info[0]; 866 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) { 867 rxb->size1 = sw_buf_sizes[i]; 868 rxb->zone = m_getzone(rxb->size1); 869 rxb->type = m_gettype(rxb->size1); 870 rxb->size2 = 0; 871 rxb->hwidx1 = -1; 872 rxb->hwidx2 = -1; 873 for (j = 0; j < SGE_FLBUF_SIZES; j++) { 874 int hwsize = sp->sge_fl_buffer_size[j]; 875 876 if (!hwsz_ok(sc, hwsize)) 877 continue; 878 879 /* hwidx for size1 */ 880 if (rxb->hwidx1 == -1 && rxb->size1 == hwsize) 881 rxb->hwidx1 = j; 882 883 /* hwidx for size2 (buffer packing) */ 884 if (rxb->size1 - CL_METADATA_SIZE < hwsize) 885 continue; 886 n = rxb->size1 - hwsize - CL_METADATA_SIZE; 887 if (n == 0) { 888 rxb->hwidx2 = j; 889 rxb->size2 = hwsize; 890 break; /* stop looking */ 891 } 892 if (rxb->hwidx2 != -1) { 893 if (n < sp->sge_fl_buffer_size[rxb->hwidx2] - 894 hwsize - CL_METADATA_SIZE) { 895 rxb->hwidx2 = j; 896 rxb->size2 = hwsize; 897 } 898 } else if (n <= 2 * CL_METADATA_SIZE) { 899 rxb->hwidx2 = j; 900 rxb->size2 = hwsize; 901 } 902 } 903 if (rxb->hwidx2 != -1) 904 sc->flags |= BUF_PACKING_OK; 905 if (s->safe_zidx == -1 && rxb->size1 == safest_rx_cluster) 906 s->safe_zidx = i; 907 } 908 } 909 910 /* 911 * Verify some basic SGE settings for the PF and VF driver, and other 912 * miscellaneous settings for the PF driver. 913 */ 914 int 915 t4_verify_chip_settings(struct adapter *sc) 916 { 917 struct sge_params *sp = &sc->params.sge; 918 uint32_t m, v, r; 919 int rc = 0; 920 const uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 921 922 m = F_RXPKTCPLMODE; 923 v = F_RXPKTCPLMODE; 924 r = sp->sge_control; 925 if ((r & m) != v) { 926 device_printf(sc->dev, "invalid SGE_CONTROL(0x%x)\n", r); 927 rc = EINVAL; 928 } 929 930 /* 931 * If this changes then every single use of PAGE_SHIFT in the driver 932 * needs to be carefully reviewed for PAGE_SHIFT vs sp->page_shift. 933 */ 934 if (sp->page_shift != PAGE_SHIFT) { 935 device_printf(sc->dev, "invalid SGE_HOST_PAGE_SIZE(0x%x)\n", r); 936 rc = EINVAL; 937 } 938 939 if (sc->flags & IS_VF) 940 return (0); 941 942 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 943 r = t4_read_reg(sc, A_ULP_RX_TDDP_PSZ); 944 if (r != v) { 945 device_printf(sc->dev, "invalid ULP_RX_TDDP_PSZ(0x%x)\n", r); 946 if (sc->vres.ddp.size != 0) 947 rc = EINVAL; 948 } 949 950 m = v = F_TDDPTAGTCB; 951 r = t4_read_reg(sc, A_ULP_RX_CTL); 952 if ((r & m) != v) { 953 device_printf(sc->dev, "invalid ULP_RX_CTL(0x%x)\n", r); 954 if (sc->vres.ddp.size != 0) 955 rc = EINVAL; 956 } 957 958 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 959 F_RESETDDPOFFSET; 960 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 961 r = t4_read_reg(sc, A_TP_PARA_REG5); 962 if ((r & m) != v) { 963 device_printf(sc->dev, "invalid TP_PARA_REG5(0x%x)\n", r); 964 if (sc->vres.ddp.size != 0) 965 rc = EINVAL; 966 } 967 968 return (rc); 969 } 970 971 int 972 t4_create_dma_tag(struct adapter *sc) 973 { 974 int rc; 975 976 rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0, 977 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE, 978 BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL, 979 NULL, &sc->dmat); 980 if (rc != 0) { 981 device_printf(sc->dev, 982 "failed to create main DMA tag: %d\n", rc); 983 } 984 985 return (rc); 986 } 987 988 void 989 t4_sge_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx, 990 struct sysctl_oid_list *children) 991 { 992 struct sge_params *sp = &sc->params.sge; 993 994 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "buffer_sizes", 995 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 996 sysctl_bufsizes, "A", "freelist buffer sizes"); 997 998 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pktshift", CTLFLAG_RD, 999 NULL, sp->fl_pktshift, "payload DMA offset in rx buffer (bytes)"); 1000 1001 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pad", CTLFLAG_RD, 1002 NULL, sp->pad_boundary, "payload pad boundary (bytes)"); 1003 1004 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "spg_len", CTLFLAG_RD, 1005 NULL, sp->spg_len, "status page size (bytes)"); 1006 1007 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_drop", CTLFLAG_RD, 1008 NULL, cong_drop, "congestion drop setting"); 1009 #ifdef TCP_OFFLOAD 1010 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ofld_cong_drop", CTLFLAG_RD, 1011 NULL, ofld_cong_drop, "congestion drop setting"); 1012 #endif 1013 1014 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pack", CTLFLAG_RD, 1015 NULL, sp->pack_boundary, "payload pack boundary (bytes)"); 1016 } 1017 1018 int 1019 t4_destroy_dma_tag(struct adapter *sc) 1020 { 1021 if (sc->dmat) 1022 bus_dma_tag_destroy(sc->dmat); 1023 1024 return (0); 1025 } 1026 1027 /* 1028 * Allocate and initialize the firmware event queue, control queues, and special 1029 * purpose rx queues owned by the adapter. 1030 * 1031 * Returns errno on failure. Resources allocated up to that point may still be 1032 * allocated. Caller is responsible for cleanup in case this function fails. 1033 */ 1034 int 1035 t4_setup_adapter_queues(struct adapter *sc) 1036 { 1037 int rc, i; 1038 1039 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 1040 1041 /* 1042 * Firmware event queue 1043 */ 1044 rc = alloc_fwq(sc); 1045 if (rc != 0) 1046 return (rc); 1047 1048 /* 1049 * That's all for the VF driver. 1050 */ 1051 if (sc->flags & IS_VF) 1052 return (rc); 1053 1054 /* 1055 * XXX: General purpose rx queues, one per port. 1056 */ 1057 1058 /* 1059 * Control queues, one per port. 1060 */ 1061 for_each_port(sc, i) { 1062 rc = alloc_ctrlq(sc, i); 1063 if (rc != 0) 1064 return (rc); 1065 } 1066 1067 return (rc); 1068 } 1069 1070 /* 1071 * Idempotent 1072 */ 1073 int 1074 t4_teardown_adapter_queues(struct adapter *sc) 1075 { 1076 int i; 1077 1078 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 1079 1080 if (sc->sge.ctrlq != NULL) { 1081 MPASS(!(sc->flags & IS_VF)); /* VFs don't allocate ctrlq. */ 1082 for_each_port(sc, i) 1083 free_ctrlq(sc, i); 1084 } 1085 free_fwq(sc); 1086 1087 return (0); 1088 } 1089 1090 /* Maximum payload that could arrive with a single iq descriptor. */ 1091 static inline int 1092 max_rx_payload(struct adapter *sc, if_t ifp, const bool ofld) 1093 { 1094 int maxp; 1095 1096 /* large enough even when hw VLAN extraction is disabled */ 1097 maxp = sc->params.sge.fl_pktshift + ETHER_HDR_LEN + 1098 ETHER_VLAN_ENCAP_LEN + if_getmtu(ifp); 1099 if (ofld && sc->tt.tls && sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS && 1100 maxp < sc->params.tp.max_rx_pdu) 1101 maxp = sc->params.tp.max_rx_pdu; 1102 return (maxp); 1103 } 1104 1105 int 1106 t4_setup_vi_queues(struct vi_info *vi) 1107 { 1108 int rc = 0, i, intr_idx; 1109 struct sge_rxq *rxq; 1110 struct sge_txq *txq; 1111 #ifdef TCP_OFFLOAD 1112 struct sge_ofld_rxq *ofld_rxq; 1113 #endif 1114 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1115 struct sge_ofld_txq *ofld_txq; 1116 #endif 1117 #ifdef DEV_NETMAP 1118 int saved_idx, iqidx; 1119 struct sge_nm_rxq *nm_rxq; 1120 struct sge_nm_txq *nm_txq; 1121 #endif 1122 struct adapter *sc = vi->adapter; 1123 if_t ifp = vi->ifp; 1124 int maxp; 1125 1126 /* Interrupt vector to start from (when using multiple vectors) */ 1127 intr_idx = vi->first_intr; 1128 1129 #ifdef DEV_NETMAP 1130 saved_idx = intr_idx; 1131 if (if_getcapabilities(ifp) & IFCAP_NETMAP) { 1132 1133 /* netmap is supported with direct interrupts only. */ 1134 MPASS(!forwarding_intr_to_fwq(sc)); 1135 MPASS(vi->first_intr >= 0); 1136 1137 /* 1138 * We don't have buffers to back the netmap rx queues 1139 * right now so we create the queues in a way that 1140 * doesn't set off any congestion signal in the chip. 1141 */ 1142 for_each_nm_rxq(vi, i, nm_rxq) { 1143 rc = alloc_nm_rxq(vi, nm_rxq, intr_idx, i); 1144 if (rc != 0) 1145 goto done; 1146 intr_idx++; 1147 } 1148 1149 for_each_nm_txq(vi, i, nm_txq) { 1150 iqidx = vi->first_nm_rxq + (i % vi->nnmrxq); 1151 rc = alloc_nm_txq(vi, nm_txq, iqidx, i); 1152 if (rc != 0) 1153 goto done; 1154 } 1155 } 1156 1157 /* Normal rx queues and netmap rx queues share the same interrupts. */ 1158 intr_idx = saved_idx; 1159 #endif 1160 1161 /* 1162 * Allocate rx queues first because a default iqid is required when 1163 * creating a tx queue. 1164 */ 1165 maxp = max_rx_payload(sc, ifp, false); 1166 for_each_rxq(vi, i, rxq) { 1167 rc = alloc_rxq(vi, rxq, i, intr_idx, maxp); 1168 if (rc != 0) 1169 goto done; 1170 if (!forwarding_intr_to_fwq(sc)) 1171 intr_idx++; 1172 } 1173 #ifdef DEV_NETMAP 1174 if (if_getcapabilities(ifp) & IFCAP_NETMAP) 1175 intr_idx = saved_idx + max(vi->nrxq, vi->nnmrxq); 1176 #endif 1177 #ifdef TCP_OFFLOAD 1178 maxp = max_rx_payload(sc, ifp, true); 1179 for_each_ofld_rxq(vi, i, ofld_rxq) { 1180 rc = alloc_ofld_rxq(vi, ofld_rxq, i, intr_idx, maxp); 1181 if (rc != 0) 1182 goto done; 1183 if (!forwarding_intr_to_fwq(sc)) 1184 intr_idx++; 1185 } 1186 #endif 1187 1188 /* 1189 * Now the tx queues. 1190 */ 1191 for_each_txq(vi, i, txq) { 1192 rc = alloc_txq(vi, txq, i); 1193 if (rc != 0) 1194 goto done; 1195 } 1196 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1197 for_each_ofld_txq(vi, i, ofld_txq) { 1198 rc = alloc_ofld_txq(vi, ofld_txq, i); 1199 if (rc != 0) 1200 goto done; 1201 } 1202 #endif 1203 done: 1204 if (rc) 1205 t4_teardown_vi_queues(vi); 1206 1207 return (rc); 1208 } 1209 1210 /* 1211 * Idempotent 1212 */ 1213 int 1214 t4_teardown_vi_queues(struct vi_info *vi) 1215 { 1216 int i; 1217 struct sge_rxq *rxq; 1218 struct sge_txq *txq; 1219 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1220 struct sge_ofld_txq *ofld_txq; 1221 #endif 1222 #ifdef TCP_OFFLOAD 1223 struct sge_ofld_rxq *ofld_rxq; 1224 #endif 1225 #ifdef DEV_NETMAP 1226 struct sge_nm_rxq *nm_rxq; 1227 struct sge_nm_txq *nm_txq; 1228 #endif 1229 1230 #ifdef DEV_NETMAP 1231 if (if_getcapabilities(vi->ifp) & IFCAP_NETMAP) { 1232 for_each_nm_txq(vi, i, nm_txq) { 1233 free_nm_txq(vi, nm_txq); 1234 } 1235 1236 for_each_nm_rxq(vi, i, nm_rxq) { 1237 free_nm_rxq(vi, nm_rxq); 1238 } 1239 } 1240 #endif 1241 1242 /* 1243 * Take down all the tx queues first, as they reference the rx queues 1244 * (for egress updates, etc.). 1245 */ 1246 1247 for_each_txq(vi, i, txq) { 1248 free_txq(vi, txq); 1249 } 1250 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1251 for_each_ofld_txq(vi, i, ofld_txq) { 1252 free_ofld_txq(vi, ofld_txq); 1253 } 1254 #endif 1255 1256 /* 1257 * Then take down the rx queues. 1258 */ 1259 1260 for_each_rxq(vi, i, rxq) { 1261 free_rxq(vi, rxq); 1262 } 1263 #ifdef TCP_OFFLOAD 1264 for_each_ofld_rxq(vi, i, ofld_rxq) { 1265 free_ofld_rxq(vi, ofld_rxq); 1266 } 1267 #endif 1268 1269 return (0); 1270 } 1271 1272 /* 1273 * Interrupt handler when the driver is using only 1 interrupt. This is a very 1274 * unusual scenario. 1275 * 1276 * a) Deals with errors, if any. 1277 * b) Services firmware event queue, which is taking interrupts for all other 1278 * queues. 1279 */ 1280 void 1281 t4_intr_all(void *arg) 1282 { 1283 struct adapter *sc = arg; 1284 struct sge_iq *fwq = &sc->sge.fwq; 1285 1286 MPASS(sc->intr_count == 1); 1287 1288 if (sc->intr_type == INTR_INTX) 1289 t4_write_reg(sc, MYPF_REG(A_PCIE_PF_CLI), 0); 1290 1291 t4_intr_err(arg); 1292 t4_intr_evt(fwq); 1293 } 1294 1295 /* 1296 * Interrupt handler for errors (installed directly when multiple interrupts are 1297 * being used, or called by t4_intr_all). 1298 */ 1299 void 1300 t4_intr_err(void *arg) 1301 { 1302 struct adapter *sc = arg; 1303 uint32_t v; 1304 const bool verbose = (sc->debug_flags & DF_VERBOSE_SLOWINTR) != 0; 1305 1306 if (atomic_load_int(&sc->error_flags) & ADAP_FATAL_ERR) 1307 return; 1308 1309 v = t4_read_reg(sc, MYPF_REG(A_PL_PF_INT_CAUSE)); 1310 if (v & F_PFSW) { 1311 sc->swintr++; 1312 t4_write_reg(sc, MYPF_REG(A_PL_PF_INT_CAUSE), v); 1313 } 1314 1315 if (t4_slow_intr_handler(sc, verbose)) 1316 t4_fatal_err(sc, false); 1317 } 1318 1319 /* 1320 * Interrupt handler for iq-only queues. The firmware event queue is the only 1321 * such queue right now. 1322 */ 1323 void 1324 t4_intr_evt(void *arg) 1325 { 1326 struct sge_iq *iq = arg; 1327 1328 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 1329 service_iq(iq, 0); 1330 (void) atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 1331 } 1332 } 1333 1334 /* 1335 * Interrupt handler for iq+fl queues. 1336 */ 1337 void 1338 t4_intr(void *arg) 1339 { 1340 struct sge_iq *iq = arg; 1341 1342 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 1343 service_iq_fl(iq, 0); 1344 (void) atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 1345 } 1346 } 1347 1348 #ifdef DEV_NETMAP 1349 /* 1350 * Interrupt handler for netmap rx queues. 1351 */ 1352 void 1353 t4_nm_intr(void *arg) 1354 { 1355 struct sge_nm_rxq *nm_rxq = arg; 1356 1357 if (atomic_cmpset_int(&nm_rxq->nm_state, NM_ON, NM_BUSY)) { 1358 service_nm_rxq(nm_rxq); 1359 (void) atomic_cmpset_int(&nm_rxq->nm_state, NM_BUSY, NM_ON); 1360 } 1361 } 1362 1363 /* 1364 * Interrupt handler for vectors shared between NIC and netmap rx queues. 1365 */ 1366 void 1367 t4_vi_intr(void *arg) 1368 { 1369 struct irq *irq = arg; 1370 1371 MPASS(irq->nm_rxq != NULL); 1372 t4_nm_intr(irq->nm_rxq); 1373 1374 MPASS(irq->rxq != NULL); 1375 t4_intr(irq->rxq); 1376 } 1377 #endif 1378 1379 /* 1380 * Deals with interrupts on an iq-only (no freelist) queue. 1381 */ 1382 static int 1383 service_iq(struct sge_iq *iq, int budget) 1384 { 1385 struct sge_iq *q; 1386 struct adapter *sc = iq->adapter; 1387 struct iq_desc *d = &iq->desc[iq->cidx]; 1388 int ndescs = 0, limit; 1389 int rsp_type; 1390 uint32_t lq; 1391 STAILQ_HEAD(, sge_iq) iql = STAILQ_HEAD_INITIALIZER(iql); 1392 1393 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq)); 1394 KASSERT((iq->flags & IQ_HAS_FL) == 0, 1395 ("%s: called for iq %p with fl (iq->flags 0x%x)", __func__, iq, 1396 iq->flags)); 1397 MPASS((iq->flags & IQ_ADJ_CREDIT) == 0); 1398 MPASS((iq->flags & IQ_LRO_ENABLED) == 0); 1399 1400 limit = budget ? budget : iq->qsize / 16; 1401 1402 /* 1403 * We always come back and check the descriptor ring for new indirect 1404 * interrupts and other responses after running a single handler. 1405 */ 1406 for (;;) { 1407 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) { 1408 1409 rmb(); 1410 1411 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen); 1412 lq = be32toh(d->rsp.pldbuflen_qid); 1413 1414 switch (rsp_type) { 1415 case X_RSPD_TYPE_FLBUF: 1416 panic("%s: data for an iq (%p) with no freelist", 1417 __func__, iq); 1418 1419 /* NOTREACHED */ 1420 1421 case X_RSPD_TYPE_CPL: 1422 KASSERT(d->rss.opcode < NUM_CPL_CMDS, 1423 ("%s: bad opcode %02x.", __func__, 1424 d->rss.opcode)); 1425 t4_cpl_handler[d->rss.opcode](iq, &d->rss, NULL); 1426 break; 1427 1428 case X_RSPD_TYPE_INTR: 1429 /* 1430 * There are 1K interrupt-capable queues (qids 0 1431 * through 1023). A response type indicating a 1432 * forwarded interrupt with a qid >= 1K is an 1433 * iWARP async notification. 1434 */ 1435 if (__predict_true(lq >= 1024)) { 1436 t4_an_handler(iq, &d->rsp); 1437 break; 1438 } 1439 1440 q = sc->sge.iqmap[lq - sc->sge.iq_start - 1441 sc->sge.iq_base]; 1442 if (atomic_cmpset_int(&q->state, IQS_IDLE, 1443 IQS_BUSY)) { 1444 if (service_iq_fl(q, q->qsize / 16) == 0) { 1445 (void) atomic_cmpset_int(&q->state, 1446 IQS_BUSY, IQS_IDLE); 1447 } else { 1448 STAILQ_INSERT_TAIL(&iql, q, 1449 link); 1450 } 1451 } 1452 break; 1453 1454 default: 1455 KASSERT(0, 1456 ("%s: illegal response type %d on iq %p", 1457 __func__, rsp_type, iq)); 1458 log(LOG_ERR, 1459 "%s: illegal response type %d on iq %p", 1460 device_get_nameunit(sc->dev), rsp_type, iq); 1461 break; 1462 } 1463 1464 d++; 1465 if (__predict_false(++iq->cidx == iq->sidx)) { 1466 iq->cidx = 0; 1467 iq->gen ^= F_RSPD_GEN; 1468 d = &iq->desc[0]; 1469 } 1470 if (__predict_false(++ndescs == limit)) { 1471 t4_write_reg(sc, sc->sge_gts_reg, 1472 V_CIDXINC(ndescs) | 1473 V_INGRESSQID(iq->cntxt_id) | 1474 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); 1475 ndescs = 0; 1476 1477 if (budget) { 1478 return (EINPROGRESS); 1479 } 1480 } 1481 } 1482 1483 if (STAILQ_EMPTY(&iql)) 1484 break; 1485 1486 /* 1487 * Process the head only, and send it to the back of the list if 1488 * it's still not done. 1489 */ 1490 q = STAILQ_FIRST(&iql); 1491 STAILQ_REMOVE_HEAD(&iql, link); 1492 if (service_iq_fl(q, q->qsize / 8) == 0) 1493 (void) atomic_cmpset_int(&q->state, IQS_BUSY, IQS_IDLE); 1494 else 1495 STAILQ_INSERT_TAIL(&iql, q, link); 1496 } 1497 1498 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) | 1499 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params)); 1500 1501 return (0); 1502 } 1503 1504 #if defined(INET) || defined(INET6) 1505 static inline int 1506 sort_before_lro(struct lro_ctrl *lro) 1507 { 1508 1509 return (lro->lro_mbuf_max != 0); 1510 } 1511 #endif 1512 1513 #define CGBE_SHIFT_SCALE 10 1514 1515 static inline uint64_t 1516 t4_tstmp_to_ns(struct adapter *sc, uint64_t lf) 1517 { 1518 struct clock_sync *cur, dcur; 1519 uint64_t hw_clocks; 1520 uint64_t hw_clk_div; 1521 sbintime_t sbt_cur_to_prev, sbt; 1522 uint64_t hw_tstmp = lf & 0xfffffffffffffffULL; /* 60b, not 64b. */ 1523 seqc_t gen; 1524 1525 for (;;) { 1526 cur = &sc->cal_info[sc->cal_current]; 1527 gen = seqc_read(&cur->gen); 1528 if (gen == 0) 1529 return (0); 1530 dcur = *cur; 1531 if (seqc_consistent(&cur->gen, gen)) 1532 break; 1533 } 1534 1535 /* 1536 * Our goal here is to have a result that is: 1537 * 1538 * ( (cur_time - prev_time) ) 1539 * ((hw_tstmp - hw_prev) * ----------------------------- ) + prev_time 1540 * ( (hw_cur - hw_prev) ) 1541 * 1542 * With the constraints that we cannot use float and we 1543 * don't want to overflow the uint64_t numbers we are using. 1544 */ 1545 hw_clocks = hw_tstmp - dcur.hw_prev; 1546 sbt_cur_to_prev = (dcur.sbt_cur - dcur.sbt_prev); 1547 hw_clk_div = dcur.hw_cur - dcur.hw_prev; 1548 sbt = hw_clocks * sbt_cur_to_prev / hw_clk_div + dcur.sbt_prev; 1549 return (sbttons(sbt)); 1550 } 1551 1552 static inline void 1553 move_to_next_rxbuf(struct sge_fl *fl) 1554 { 1555 1556 fl->rx_offset = 0; 1557 if (__predict_false((++fl->cidx & 7) == 0)) { 1558 uint16_t cidx = fl->cidx >> 3; 1559 1560 if (__predict_false(cidx == fl->sidx)) 1561 fl->cidx = cidx = 0; 1562 fl->hw_cidx = cidx; 1563 } 1564 } 1565 1566 /* 1567 * Deals with interrupts on an iq+fl queue. 1568 */ 1569 static int 1570 service_iq_fl(struct sge_iq *iq, int budget) 1571 { 1572 struct sge_rxq *rxq = iq_to_rxq(iq); 1573 struct sge_fl *fl; 1574 struct adapter *sc = iq->adapter; 1575 struct iq_desc *d = &iq->desc[iq->cidx]; 1576 int ndescs, limit; 1577 int rsp_type, starved; 1578 uint32_t lq; 1579 uint16_t fl_hw_cidx; 1580 struct mbuf *m0; 1581 #if defined(INET) || defined(INET6) 1582 const struct timeval lro_timeout = {0, sc->lro_timeout}; 1583 struct lro_ctrl *lro = &rxq->lro; 1584 #endif 1585 1586 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq)); 1587 MPASS(iq->flags & IQ_HAS_FL); 1588 1589 ndescs = 0; 1590 #if defined(INET) || defined(INET6) 1591 if (iq->flags & IQ_ADJ_CREDIT) { 1592 MPASS(sort_before_lro(lro)); 1593 iq->flags &= ~IQ_ADJ_CREDIT; 1594 if ((d->rsp.u.type_gen & F_RSPD_GEN) != iq->gen) { 1595 tcp_lro_flush_all(lro); 1596 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(1) | 1597 V_INGRESSQID((u32)iq->cntxt_id) | 1598 V_SEINTARM(iq->intr_params)); 1599 return (0); 1600 } 1601 ndescs = 1; 1602 } 1603 #else 1604 MPASS((iq->flags & IQ_ADJ_CREDIT) == 0); 1605 #endif 1606 1607 limit = budget ? budget : iq->qsize / 16; 1608 fl = &rxq->fl; 1609 fl_hw_cidx = fl->hw_cidx; /* stable snapshot */ 1610 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) { 1611 1612 rmb(); 1613 1614 m0 = NULL; 1615 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen); 1616 lq = be32toh(d->rsp.pldbuflen_qid); 1617 1618 switch (rsp_type) { 1619 case X_RSPD_TYPE_FLBUF: 1620 if (lq & F_RSPD_NEWBUF) { 1621 if (fl->rx_offset > 0) 1622 move_to_next_rxbuf(fl); 1623 lq = G_RSPD_LEN(lq); 1624 } 1625 if (IDXDIFF(fl->hw_cidx, fl_hw_cidx, fl->sidx) > 4) { 1626 FL_LOCK(fl); 1627 refill_fl(sc, fl, 64); 1628 FL_UNLOCK(fl); 1629 fl_hw_cidx = fl->hw_cidx; 1630 } 1631 1632 if (d->rss.opcode == CPL_RX_PKT) { 1633 if (__predict_true(eth_rx(sc, rxq, d, lq) == 0)) 1634 break; 1635 goto out; 1636 } 1637 m0 = get_fl_payload(sc, fl, lq); 1638 if (__predict_false(m0 == NULL)) 1639 goto out; 1640 1641 /* fall through */ 1642 1643 case X_RSPD_TYPE_CPL: 1644 KASSERT(d->rss.opcode < NUM_CPL_CMDS, 1645 ("%s: bad opcode %02x.", __func__, d->rss.opcode)); 1646 t4_cpl_handler[d->rss.opcode](iq, &d->rss, m0); 1647 break; 1648 1649 case X_RSPD_TYPE_INTR: 1650 1651 /* 1652 * There are 1K interrupt-capable queues (qids 0 1653 * through 1023). A response type indicating a 1654 * forwarded interrupt with a qid >= 1K is an 1655 * iWARP async notification. That is the only 1656 * acceptable indirect interrupt on this queue. 1657 */ 1658 if (__predict_false(lq < 1024)) { 1659 panic("%s: indirect interrupt on iq_fl %p " 1660 "with qid %u", __func__, iq, lq); 1661 } 1662 1663 t4_an_handler(iq, &d->rsp); 1664 break; 1665 1666 default: 1667 KASSERT(0, ("%s: illegal response type %d on iq %p", 1668 __func__, rsp_type, iq)); 1669 log(LOG_ERR, "%s: illegal response type %d on iq %p", 1670 device_get_nameunit(sc->dev), rsp_type, iq); 1671 break; 1672 } 1673 1674 d++; 1675 if (__predict_false(++iq->cidx == iq->sidx)) { 1676 iq->cidx = 0; 1677 iq->gen ^= F_RSPD_GEN; 1678 d = &iq->desc[0]; 1679 } 1680 if (__predict_false(++ndescs == limit)) { 1681 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) | 1682 V_INGRESSQID(iq->cntxt_id) | 1683 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); 1684 1685 #if defined(INET) || defined(INET6) 1686 if (iq->flags & IQ_LRO_ENABLED && 1687 !sort_before_lro(lro) && 1688 sc->lro_timeout != 0) { 1689 tcp_lro_flush_inactive(lro, &lro_timeout); 1690 } 1691 #endif 1692 if (budget) 1693 return (EINPROGRESS); 1694 ndescs = 0; 1695 } 1696 } 1697 out: 1698 #if defined(INET) || defined(INET6) 1699 if (iq->flags & IQ_LRO_ENABLED) { 1700 if (ndescs > 0 && lro->lro_mbuf_count > 8) { 1701 MPASS(sort_before_lro(lro)); 1702 /* hold back one credit and don't flush LRO state */ 1703 iq->flags |= IQ_ADJ_CREDIT; 1704 ndescs--; 1705 } else { 1706 tcp_lro_flush_all(lro); 1707 } 1708 } 1709 #endif 1710 1711 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) | 1712 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params)); 1713 1714 FL_LOCK(fl); 1715 starved = refill_fl(sc, fl, 64); 1716 FL_UNLOCK(fl); 1717 if (__predict_false(starved != 0)) 1718 add_fl_to_sfl(sc, fl); 1719 1720 return (0); 1721 } 1722 1723 static inline struct cluster_metadata * 1724 cl_metadata(struct fl_sdesc *sd) 1725 { 1726 1727 return ((void *)(sd->cl + sd->moff)); 1728 } 1729 1730 static void 1731 rxb_free(struct mbuf *m) 1732 { 1733 struct cluster_metadata *clm = m->m_ext.ext_arg1; 1734 1735 uma_zfree(clm->zone, clm->cl); 1736 counter_u64_add(extfree_rels, 1); 1737 } 1738 1739 /* 1740 * The mbuf returned comes from zone_muf and carries the payload in one of these 1741 * ways 1742 * a) complete frame inside the mbuf 1743 * b) m_cljset (for clusters without metadata) 1744 * d) m_extaddref (cluster with metadata) 1745 */ 1746 static struct mbuf * 1747 get_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset, 1748 int remaining) 1749 { 1750 struct mbuf *m; 1751 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 1752 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[sd->zidx]; 1753 struct cluster_metadata *clm; 1754 int len, blen; 1755 caddr_t payload; 1756 1757 if (fl->flags & FL_BUF_PACKING) { 1758 u_int l, pad; 1759 1760 blen = rxb->size2 - fl->rx_offset; /* max possible in this buf */ 1761 len = min(remaining, blen); 1762 payload = sd->cl + fl->rx_offset; 1763 1764 l = fr_offset + len; 1765 pad = roundup2(l, fl->buf_boundary) - l; 1766 if (fl->rx_offset + len + pad < rxb->size2) 1767 blen = len + pad; 1768 MPASS(fl->rx_offset + blen <= rxb->size2); 1769 } else { 1770 MPASS(fl->rx_offset == 0); /* not packing */ 1771 blen = rxb->size1; 1772 len = min(remaining, blen); 1773 payload = sd->cl; 1774 } 1775 1776 if (fr_offset == 0) { 1777 m = m_gethdr(M_NOWAIT, MT_DATA); 1778 if (__predict_false(m == NULL)) 1779 return (NULL); 1780 m->m_pkthdr.len = remaining; 1781 } else { 1782 m = m_get(M_NOWAIT, MT_DATA); 1783 if (__predict_false(m == NULL)) 1784 return (NULL); 1785 } 1786 m->m_len = len; 1787 kmsan_mark(payload, len, KMSAN_STATE_INITED); 1788 1789 if (sc->sc_do_rxcopy && len < RX_COPY_THRESHOLD) { 1790 /* copy data to mbuf */ 1791 bcopy(payload, mtod(m, caddr_t), len); 1792 if (fl->flags & FL_BUF_PACKING) { 1793 fl->rx_offset += blen; 1794 MPASS(fl->rx_offset <= rxb->size2); 1795 if (fl->rx_offset < rxb->size2) 1796 return (m); /* without advancing the cidx */ 1797 } 1798 } else if (fl->flags & FL_BUF_PACKING) { 1799 clm = cl_metadata(sd); 1800 if (sd->nmbuf++ == 0) { 1801 clm->refcount = 1; 1802 clm->zone = rxb->zone; 1803 clm->cl = sd->cl; 1804 counter_u64_add(extfree_refs, 1); 1805 } 1806 m_extaddref(m, payload, blen, &clm->refcount, rxb_free, clm, 1807 NULL); 1808 1809 fl->rx_offset += blen; 1810 MPASS(fl->rx_offset <= rxb->size2); 1811 if (fl->rx_offset < rxb->size2) 1812 return (m); /* without advancing the cidx */ 1813 } else { 1814 m_cljset(m, sd->cl, rxb->type); 1815 sd->cl = NULL; /* consumed, not a recycle candidate */ 1816 } 1817 1818 move_to_next_rxbuf(fl); 1819 1820 return (m); 1821 } 1822 1823 static struct mbuf * 1824 get_fl_payload(struct adapter *sc, struct sge_fl *fl, const u_int plen) 1825 { 1826 struct mbuf *m0, *m, **pnext; 1827 u_int remaining; 1828 1829 if (__predict_false(fl->flags & FL_BUF_RESUME)) { 1830 M_ASSERTPKTHDR(fl->m0); 1831 MPASS(fl->m0->m_pkthdr.len == plen); 1832 MPASS(fl->remaining < plen); 1833 1834 m0 = fl->m0; 1835 pnext = fl->pnext; 1836 remaining = fl->remaining; 1837 fl->flags &= ~FL_BUF_RESUME; 1838 goto get_segment; 1839 } 1840 1841 /* 1842 * Payload starts at rx_offset in the current hw buffer. Its length is 1843 * 'len' and it may span multiple hw buffers. 1844 */ 1845 1846 m0 = get_scatter_segment(sc, fl, 0, plen); 1847 if (m0 == NULL) 1848 return (NULL); 1849 remaining = plen - m0->m_len; 1850 pnext = &m0->m_next; 1851 while (remaining > 0) { 1852 get_segment: 1853 MPASS(fl->rx_offset == 0); 1854 m = get_scatter_segment(sc, fl, plen - remaining, remaining); 1855 if (__predict_false(m == NULL)) { 1856 fl->m0 = m0; 1857 fl->pnext = pnext; 1858 fl->remaining = remaining; 1859 fl->flags |= FL_BUF_RESUME; 1860 return (NULL); 1861 } 1862 *pnext = m; 1863 pnext = &m->m_next; 1864 remaining -= m->m_len; 1865 } 1866 *pnext = NULL; 1867 1868 M_ASSERTPKTHDR(m0); 1869 return (m0); 1870 } 1871 1872 static int 1873 skip_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset, 1874 int remaining) 1875 { 1876 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 1877 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[sd->zidx]; 1878 int len, blen; 1879 1880 if (fl->flags & FL_BUF_PACKING) { 1881 u_int l, pad; 1882 1883 blen = rxb->size2 - fl->rx_offset; /* max possible in this buf */ 1884 len = min(remaining, blen); 1885 1886 l = fr_offset + len; 1887 pad = roundup2(l, fl->buf_boundary) - l; 1888 if (fl->rx_offset + len + pad < rxb->size2) 1889 blen = len + pad; 1890 fl->rx_offset += blen; 1891 MPASS(fl->rx_offset <= rxb->size2); 1892 if (fl->rx_offset < rxb->size2) 1893 return (len); /* without advancing the cidx */ 1894 } else { 1895 MPASS(fl->rx_offset == 0); /* not packing */ 1896 blen = rxb->size1; 1897 len = min(remaining, blen); 1898 } 1899 move_to_next_rxbuf(fl); 1900 return (len); 1901 } 1902 1903 static inline void 1904 skip_fl_payload(struct adapter *sc, struct sge_fl *fl, int plen) 1905 { 1906 int remaining, fr_offset, len; 1907 1908 fr_offset = 0; 1909 remaining = plen; 1910 while (remaining > 0) { 1911 len = skip_scatter_segment(sc, fl, fr_offset, remaining); 1912 fr_offset += len; 1913 remaining -= len; 1914 } 1915 } 1916 1917 static inline int 1918 get_segment_len(struct adapter *sc, struct sge_fl *fl, int plen) 1919 { 1920 int len; 1921 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 1922 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[sd->zidx]; 1923 1924 if (fl->flags & FL_BUF_PACKING) 1925 len = rxb->size2 - fl->rx_offset; 1926 else 1927 len = rxb->size1; 1928 1929 return (min(plen, len)); 1930 } 1931 1932 static int 1933 eth_rx(struct adapter *sc, struct sge_rxq *rxq, const struct iq_desc *d, 1934 u_int plen) 1935 { 1936 struct mbuf *m0; 1937 if_t ifp = rxq->ifp; 1938 struct sge_fl *fl = &rxq->fl; 1939 struct vi_info *vi = if_getsoftc(ifp); 1940 const struct cpl_rx_pkt *cpl; 1941 #if defined(INET) || defined(INET6) 1942 struct lro_ctrl *lro = &rxq->lro; 1943 #endif 1944 uint16_t err_vec, tnl_type, tnlhdr_len; 1945 static const int sw_hashtype[4][2] = { 1946 {M_HASHTYPE_NONE, M_HASHTYPE_NONE}, 1947 {M_HASHTYPE_RSS_IPV4, M_HASHTYPE_RSS_IPV6}, 1948 {M_HASHTYPE_RSS_TCP_IPV4, M_HASHTYPE_RSS_TCP_IPV6}, 1949 {M_HASHTYPE_RSS_UDP_IPV4, M_HASHTYPE_RSS_UDP_IPV6}, 1950 }; 1951 static const int sw_csum_flags[2][2] = { 1952 { 1953 /* IP, inner IP */ 1954 CSUM_ENCAP_VXLAN | 1955 CSUM_L3_CALC | CSUM_L3_VALID | 1956 CSUM_L4_CALC | CSUM_L4_VALID | 1957 CSUM_INNER_L3_CALC | CSUM_INNER_L3_VALID | 1958 CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID, 1959 1960 /* IP, inner IP6 */ 1961 CSUM_ENCAP_VXLAN | 1962 CSUM_L3_CALC | CSUM_L3_VALID | 1963 CSUM_L4_CALC | CSUM_L4_VALID | 1964 CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID, 1965 }, 1966 { 1967 /* IP6, inner IP */ 1968 CSUM_ENCAP_VXLAN | 1969 CSUM_L4_CALC | CSUM_L4_VALID | 1970 CSUM_INNER_L3_CALC | CSUM_INNER_L3_VALID | 1971 CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID, 1972 1973 /* IP6, inner IP6 */ 1974 CSUM_ENCAP_VXLAN | 1975 CSUM_L4_CALC | CSUM_L4_VALID | 1976 CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID, 1977 }, 1978 }; 1979 1980 MPASS(plen > sc->params.sge.fl_pktshift); 1981 if (vi->pfil != NULL && PFIL_HOOKED_IN(vi->pfil) && 1982 __predict_true((fl->flags & FL_BUF_RESUME) == 0)) { 1983 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 1984 caddr_t frame; 1985 int rc, slen; 1986 1987 slen = get_segment_len(sc, fl, plen) - 1988 sc->params.sge.fl_pktshift; 1989 frame = sd->cl + fl->rx_offset + sc->params.sge.fl_pktshift; 1990 CURVNET_SET_QUIET(if_getvnet(ifp)); 1991 rc = pfil_mem_in(vi->pfil, frame, slen, ifp, &m0); 1992 CURVNET_RESTORE(); 1993 if (rc == PFIL_DROPPED || rc == PFIL_CONSUMED) { 1994 skip_fl_payload(sc, fl, plen); 1995 return (0); 1996 } 1997 if (rc == PFIL_REALLOCED) { 1998 skip_fl_payload(sc, fl, plen); 1999 goto have_mbuf; 2000 } 2001 } 2002 2003 m0 = get_fl_payload(sc, fl, plen); 2004 if (__predict_false(m0 == NULL)) 2005 return (ENOMEM); 2006 2007 m0->m_pkthdr.len -= sc->params.sge.fl_pktshift; 2008 m0->m_len -= sc->params.sge.fl_pktshift; 2009 m0->m_data += sc->params.sge.fl_pktshift; 2010 2011 have_mbuf: 2012 m0->m_pkthdr.rcvif = ifp; 2013 M_HASHTYPE_SET(m0, sw_hashtype[d->rss.hash_type][d->rss.ipv6]); 2014 m0->m_pkthdr.flowid = be32toh(d->rss.hash_val); 2015 2016 cpl = (const void *)(&d->rss + 1); 2017 if (sc->params.tp.rx_pkt_encap) { 2018 const uint16_t ev = be16toh(cpl->err_vec); 2019 2020 err_vec = G_T6_COMPR_RXERR_VEC(ev); 2021 tnl_type = G_T6_RX_TNL_TYPE(ev); 2022 tnlhdr_len = G_T6_RX_TNLHDR_LEN(ev); 2023 } else { 2024 err_vec = be16toh(cpl->err_vec); 2025 tnl_type = 0; 2026 tnlhdr_len = 0; 2027 } 2028 if (cpl->csum_calc && err_vec == 0) { 2029 int ipv6 = !!(cpl->l2info & htobe32(F_RXF_IP6)); 2030 2031 /* checksum(s) calculated and found to be correct. */ 2032 2033 MPASS((cpl->l2info & htobe32(F_RXF_IP)) ^ 2034 (cpl->l2info & htobe32(F_RXF_IP6))); 2035 m0->m_pkthdr.csum_data = be16toh(cpl->csum); 2036 if (tnl_type == 0) { 2037 if (!ipv6 && if_getcapenable(ifp) & IFCAP_RXCSUM) { 2038 m0->m_pkthdr.csum_flags = CSUM_L3_CALC | 2039 CSUM_L3_VALID | CSUM_L4_CALC | 2040 CSUM_L4_VALID; 2041 } else if (ipv6 && if_getcapenable(ifp) & IFCAP_RXCSUM_IPV6) { 2042 m0->m_pkthdr.csum_flags = CSUM_L4_CALC | 2043 CSUM_L4_VALID; 2044 } 2045 rxq->rxcsum++; 2046 } else { 2047 MPASS(tnl_type == RX_PKT_TNL_TYPE_VXLAN); 2048 2049 M_HASHTYPE_SETINNER(m0); 2050 if (__predict_false(cpl->ip_frag)) { 2051 /* 2052 * csum_data is for the inner frame (which is an 2053 * IP fragment) and is not 0xffff. There is no 2054 * way to pass the inner csum_data to the stack. 2055 * We don't want the stack to use the inner 2056 * csum_data to validate the outer frame or it 2057 * will get rejected. So we fix csum_data here 2058 * and let sw do the checksum of inner IP 2059 * fragments. 2060 * 2061 * XXX: Need 32b for csum_data2 in an rx mbuf. 2062 * Maybe stuff it into rcv_tstmp? 2063 */ 2064 m0->m_pkthdr.csum_data = 0xffff; 2065 if (ipv6) { 2066 m0->m_pkthdr.csum_flags = CSUM_L4_CALC | 2067 CSUM_L4_VALID; 2068 } else { 2069 m0->m_pkthdr.csum_flags = CSUM_L3_CALC | 2070 CSUM_L3_VALID | CSUM_L4_CALC | 2071 CSUM_L4_VALID; 2072 } 2073 } else { 2074 int outer_ipv6; 2075 2076 MPASS(m0->m_pkthdr.csum_data == 0xffff); 2077 2078 outer_ipv6 = tnlhdr_len >= 2079 sizeof(struct ether_header) + 2080 sizeof(struct ip6_hdr); 2081 m0->m_pkthdr.csum_flags = 2082 sw_csum_flags[outer_ipv6][ipv6]; 2083 } 2084 rxq->vxlan_rxcsum++; 2085 } 2086 } 2087 2088 if (cpl->vlan_ex) { 2089 if (sc->flags & IS_VF && sc->vlan_id) { 2090 /* 2091 * HW is not setup correctly if extracted vlan_id does 2092 * not match the VF's setting. 2093 */ 2094 MPASS(be16toh(cpl->vlan) == sc->vlan_id); 2095 } else { 2096 m0->m_pkthdr.ether_vtag = be16toh(cpl->vlan); 2097 m0->m_flags |= M_VLANTAG; 2098 rxq->vlan_extraction++; 2099 } 2100 } 2101 2102 if (rxq->iq.flags & IQ_RX_TIMESTAMP) { 2103 /* 2104 * Fill up rcv_tstmp but do not set M_TSTMP as 2105 * long as we get a non-zero back from t4_tstmp_to_ns(). 2106 */ 2107 m0->m_pkthdr.rcv_tstmp = t4_tstmp_to_ns(sc, 2108 be64toh(d->rsp.u.last_flit)); 2109 if (m0->m_pkthdr.rcv_tstmp != 0) 2110 m0->m_flags |= M_TSTMP; 2111 } 2112 2113 #ifdef NUMA 2114 m0->m_pkthdr.numa_domain = if_getnumadomain(ifp); 2115 #endif 2116 #if defined(INET) || defined(INET6) 2117 if (rxq->iq.flags & IQ_LRO_ENABLED && tnl_type == 0 && 2118 (M_HASHTYPE_GET(m0) == M_HASHTYPE_RSS_TCP_IPV4 || 2119 M_HASHTYPE_GET(m0) == M_HASHTYPE_RSS_TCP_IPV6)) { 2120 if (sort_before_lro(lro)) { 2121 tcp_lro_queue_mbuf(lro, m0); 2122 return (0); /* queued for sort, then LRO */ 2123 } 2124 if (tcp_lro_rx(lro, m0, 0) == 0) 2125 return (0); /* queued for LRO */ 2126 } 2127 #endif 2128 if_input(ifp, m0); 2129 2130 return (0); 2131 } 2132 2133 /* 2134 * Must drain the wrq or make sure that someone else will. 2135 */ 2136 static void 2137 wrq_tx_drain(void *arg, int n) 2138 { 2139 struct sge_wrq *wrq = arg; 2140 struct sge_eq *eq = &wrq->eq; 2141 2142 EQ_LOCK(eq); 2143 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 2144 drain_wrq_wr_list(wrq->adapter, wrq); 2145 EQ_UNLOCK(eq); 2146 } 2147 2148 static void 2149 drain_wrq_wr_list(struct adapter *sc, struct sge_wrq *wrq) 2150 { 2151 struct sge_eq *eq = &wrq->eq; 2152 u_int available, dbdiff; /* # of hardware descriptors */ 2153 u_int n; 2154 struct wrqe *wr; 2155 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */ 2156 2157 EQ_LOCK_ASSERT_OWNED(eq); 2158 MPASS(TAILQ_EMPTY(&wrq->incomplete_wrs)); 2159 wr = STAILQ_FIRST(&wrq->wr_list); 2160 MPASS(wr != NULL); /* Must be called with something useful to do */ 2161 MPASS(eq->pidx == eq->dbidx); 2162 dbdiff = 0; 2163 2164 do { 2165 eq->cidx = read_hw_cidx(eq); 2166 if (eq->pidx == eq->cidx) 2167 available = eq->sidx - 1; 2168 else 2169 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2170 2171 MPASS(wr->wrq == wrq); 2172 n = howmany(wr->wr_len, EQ_ESIZE); 2173 if (available < n) 2174 break; 2175 2176 dst = (void *)&eq->desc[eq->pidx]; 2177 if (__predict_true(eq->sidx - eq->pidx > n)) { 2178 /* Won't wrap, won't end exactly at the status page. */ 2179 bcopy(&wr->wr[0], dst, wr->wr_len); 2180 eq->pidx += n; 2181 } else { 2182 int first_portion = (eq->sidx - eq->pidx) * EQ_ESIZE; 2183 2184 bcopy(&wr->wr[0], dst, first_portion); 2185 if (wr->wr_len > first_portion) { 2186 bcopy(&wr->wr[first_portion], &eq->desc[0], 2187 wr->wr_len - first_portion); 2188 } 2189 eq->pidx = n - (eq->sidx - eq->pidx); 2190 } 2191 wrq->tx_wrs_copied++; 2192 2193 if (available < eq->sidx / 4 && 2194 atomic_cmpset_int(&eq->equiq, 0, 1)) { 2195 /* 2196 * XXX: This is not 100% reliable with some 2197 * types of WRs. But this is a very unusual 2198 * situation for an ofld/ctrl queue anyway. 2199 */ 2200 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ | 2201 F_FW_WR_EQUEQ); 2202 } 2203 2204 dbdiff += n; 2205 if (dbdiff >= 16) { 2206 ring_eq_db(sc, eq, dbdiff); 2207 dbdiff = 0; 2208 } 2209 2210 STAILQ_REMOVE_HEAD(&wrq->wr_list, link); 2211 free_wrqe(wr); 2212 MPASS(wrq->nwr_pending > 0); 2213 wrq->nwr_pending--; 2214 MPASS(wrq->ndesc_needed >= n); 2215 wrq->ndesc_needed -= n; 2216 } while ((wr = STAILQ_FIRST(&wrq->wr_list)) != NULL); 2217 2218 if (dbdiff) 2219 ring_eq_db(sc, eq, dbdiff); 2220 } 2221 2222 /* 2223 * Doesn't fail. Holds on to work requests it can't send right away. 2224 */ 2225 void 2226 t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, struct wrqe *wr) 2227 { 2228 #ifdef INVARIANTS 2229 struct sge_eq *eq = &wrq->eq; 2230 #endif 2231 2232 EQ_LOCK_ASSERT_OWNED(eq); 2233 MPASS(wr != NULL); 2234 MPASS(wr->wr_len > 0 && wr->wr_len <= SGE_MAX_WR_LEN); 2235 MPASS((wr->wr_len & 0x7) == 0); 2236 2237 STAILQ_INSERT_TAIL(&wrq->wr_list, wr, link); 2238 wrq->nwr_pending++; 2239 wrq->ndesc_needed += howmany(wr->wr_len, EQ_ESIZE); 2240 2241 if (!TAILQ_EMPTY(&wrq->incomplete_wrs)) 2242 return; /* commit_wrq_wr will drain wr_list as well. */ 2243 2244 drain_wrq_wr_list(sc, wrq); 2245 2246 /* Doorbell must have caught up to the pidx. */ 2247 MPASS(eq->pidx == eq->dbidx); 2248 } 2249 2250 void 2251 t4_update_fl_bufsize(if_t ifp) 2252 { 2253 struct vi_info *vi = if_getsoftc(ifp); 2254 struct adapter *sc = vi->adapter; 2255 struct sge_rxq *rxq; 2256 #ifdef TCP_OFFLOAD 2257 struct sge_ofld_rxq *ofld_rxq; 2258 #endif 2259 struct sge_fl *fl; 2260 int i, maxp; 2261 2262 maxp = max_rx_payload(sc, ifp, false); 2263 for_each_rxq(vi, i, rxq) { 2264 fl = &rxq->fl; 2265 2266 FL_LOCK(fl); 2267 fl->zidx = find_refill_source(sc, maxp, 2268 fl->flags & FL_BUF_PACKING); 2269 FL_UNLOCK(fl); 2270 } 2271 #ifdef TCP_OFFLOAD 2272 maxp = max_rx_payload(sc, ifp, true); 2273 for_each_ofld_rxq(vi, i, ofld_rxq) { 2274 fl = &ofld_rxq->fl; 2275 2276 FL_LOCK(fl); 2277 fl->zidx = find_refill_source(sc, maxp, 2278 fl->flags & FL_BUF_PACKING); 2279 FL_UNLOCK(fl); 2280 } 2281 #endif 2282 } 2283 2284 #ifdef RATELIMIT 2285 static inline int 2286 mbuf_eo_nsegs(struct mbuf *m) 2287 { 2288 2289 M_ASSERTPKTHDR(m); 2290 return (m->m_pkthdr.PH_loc.eight[1]); 2291 } 2292 2293 #if defined(INET) || defined(INET6) 2294 static inline void 2295 set_mbuf_eo_nsegs(struct mbuf *m, uint8_t nsegs) 2296 { 2297 2298 M_ASSERTPKTHDR(m); 2299 m->m_pkthdr.PH_loc.eight[1] = nsegs; 2300 } 2301 #endif 2302 2303 static inline int 2304 mbuf_eo_len16(struct mbuf *m) 2305 { 2306 int n; 2307 2308 M_ASSERTPKTHDR(m); 2309 n = m->m_pkthdr.PH_loc.eight[2]; 2310 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16); 2311 2312 return (n); 2313 } 2314 2315 #if defined(INET) || defined(INET6) 2316 static inline void 2317 set_mbuf_eo_len16(struct mbuf *m, uint8_t len16) 2318 { 2319 2320 M_ASSERTPKTHDR(m); 2321 m->m_pkthdr.PH_loc.eight[2] = len16; 2322 } 2323 #endif 2324 2325 static inline int 2326 mbuf_eo_tsclk_tsoff(struct mbuf *m) 2327 { 2328 2329 M_ASSERTPKTHDR(m); 2330 return (m->m_pkthdr.PH_loc.eight[3]); 2331 } 2332 2333 #if defined(INET) || defined(INET6) 2334 static inline void 2335 set_mbuf_eo_tsclk_tsoff(struct mbuf *m, uint8_t tsclk_tsoff) 2336 { 2337 2338 M_ASSERTPKTHDR(m); 2339 m->m_pkthdr.PH_loc.eight[3] = tsclk_tsoff; 2340 } 2341 #endif 2342 2343 static inline int 2344 needs_eo(struct m_snd_tag *mst) 2345 { 2346 2347 return (mst != NULL && mst->sw->type == IF_SND_TAG_TYPE_RATE_LIMIT); 2348 } 2349 #endif 2350 2351 /* 2352 * Try to allocate an mbuf to contain a raw work request. To make it 2353 * easy to construct the work request, don't allocate a chain but a 2354 * single mbuf. 2355 */ 2356 struct mbuf * 2357 alloc_wr_mbuf(int len, int how) 2358 { 2359 struct mbuf *m; 2360 2361 if (len <= MHLEN) 2362 m = m_gethdr(how, MT_DATA); 2363 else if (len <= MCLBYTES) 2364 m = m_getcl(how, MT_DATA, M_PKTHDR); 2365 else 2366 m = NULL; 2367 if (m == NULL) 2368 return (NULL); 2369 m->m_pkthdr.len = len; 2370 m->m_len = len; 2371 set_mbuf_cflags(m, MC_RAW_WR); 2372 set_mbuf_len16(m, howmany(len, 16)); 2373 return (m); 2374 } 2375 2376 static inline bool 2377 needs_hwcsum(struct mbuf *m) 2378 { 2379 const uint32_t csum_flags = CSUM_IP | CSUM_IP_UDP | CSUM_IP_TCP | 2380 CSUM_IP_TSO | CSUM_INNER_IP | CSUM_INNER_IP_UDP | 2381 CSUM_INNER_IP_TCP | CSUM_INNER_IP_TSO | CSUM_IP6_UDP | 2382 CSUM_IP6_TCP | CSUM_IP6_TSO | CSUM_INNER_IP6_UDP | 2383 CSUM_INNER_IP6_TCP | CSUM_INNER_IP6_TSO; 2384 2385 M_ASSERTPKTHDR(m); 2386 2387 return (m->m_pkthdr.csum_flags & csum_flags); 2388 } 2389 2390 static inline bool 2391 needs_tso(struct mbuf *m) 2392 { 2393 const uint32_t csum_flags = CSUM_IP_TSO | CSUM_IP6_TSO | 2394 CSUM_INNER_IP_TSO | CSUM_INNER_IP6_TSO; 2395 2396 M_ASSERTPKTHDR(m); 2397 2398 return (m->m_pkthdr.csum_flags & csum_flags); 2399 } 2400 2401 static inline bool 2402 needs_vxlan_csum(struct mbuf *m) 2403 { 2404 2405 M_ASSERTPKTHDR(m); 2406 2407 return (m->m_pkthdr.csum_flags & CSUM_ENCAP_VXLAN); 2408 } 2409 2410 static inline bool 2411 needs_vxlan_tso(struct mbuf *m) 2412 { 2413 const uint32_t csum_flags = CSUM_ENCAP_VXLAN | CSUM_INNER_IP_TSO | 2414 CSUM_INNER_IP6_TSO; 2415 2416 M_ASSERTPKTHDR(m); 2417 2418 return ((m->m_pkthdr.csum_flags & csum_flags) != 0 && 2419 (m->m_pkthdr.csum_flags & csum_flags) != CSUM_ENCAP_VXLAN); 2420 } 2421 2422 #if defined(INET) || defined(INET6) 2423 static inline bool 2424 needs_inner_tcp_csum(struct mbuf *m) 2425 { 2426 const uint32_t csum_flags = CSUM_INNER_IP_TSO | CSUM_INNER_IP6_TSO; 2427 2428 M_ASSERTPKTHDR(m); 2429 2430 return (m->m_pkthdr.csum_flags & csum_flags); 2431 } 2432 #endif 2433 2434 static inline bool 2435 needs_l3_csum(struct mbuf *m) 2436 { 2437 const uint32_t csum_flags = CSUM_IP | CSUM_IP_TSO | CSUM_INNER_IP | 2438 CSUM_INNER_IP_TSO; 2439 2440 M_ASSERTPKTHDR(m); 2441 2442 return (m->m_pkthdr.csum_flags & csum_flags); 2443 } 2444 2445 static inline bool 2446 needs_outer_tcp_csum(struct mbuf *m) 2447 { 2448 const uint32_t csum_flags = CSUM_IP_TCP | CSUM_IP_TSO | CSUM_IP6_TCP | 2449 CSUM_IP6_TSO; 2450 2451 M_ASSERTPKTHDR(m); 2452 2453 return (m->m_pkthdr.csum_flags & csum_flags); 2454 } 2455 2456 #ifdef RATELIMIT 2457 static inline bool 2458 needs_outer_l4_csum(struct mbuf *m) 2459 { 2460 const uint32_t csum_flags = CSUM_IP_UDP | CSUM_IP_TCP | CSUM_IP_TSO | 2461 CSUM_IP6_UDP | CSUM_IP6_TCP | CSUM_IP6_TSO; 2462 2463 M_ASSERTPKTHDR(m); 2464 2465 return (m->m_pkthdr.csum_flags & csum_flags); 2466 } 2467 2468 static inline bool 2469 needs_outer_udp_csum(struct mbuf *m) 2470 { 2471 const uint32_t csum_flags = CSUM_IP_UDP | CSUM_IP6_UDP; 2472 2473 M_ASSERTPKTHDR(m); 2474 2475 return (m->m_pkthdr.csum_flags & csum_flags); 2476 } 2477 #endif 2478 2479 static inline bool 2480 needs_vlan_insertion(struct mbuf *m) 2481 { 2482 2483 M_ASSERTPKTHDR(m); 2484 2485 return (m->m_flags & M_VLANTAG); 2486 } 2487 2488 #if defined(INET) || defined(INET6) 2489 static void * 2490 m_advance(struct mbuf **pm, int *poffset, int len) 2491 { 2492 struct mbuf *m = *pm; 2493 int offset = *poffset; 2494 uintptr_t p = 0; 2495 2496 MPASS(len > 0); 2497 2498 for (;;) { 2499 if (offset + len < m->m_len) { 2500 offset += len; 2501 p = mtod(m, uintptr_t) + offset; 2502 break; 2503 } 2504 len -= m->m_len - offset; 2505 m = m->m_next; 2506 offset = 0; 2507 MPASS(m != NULL); 2508 } 2509 *poffset = offset; 2510 *pm = m; 2511 return ((void *)p); 2512 } 2513 #endif 2514 2515 static inline int 2516 count_mbuf_ext_pgs(struct mbuf *m, int skip, vm_paddr_t *nextaddr) 2517 { 2518 vm_paddr_t paddr; 2519 int i, len, off, pglen, pgoff, seglen, segoff; 2520 int nsegs = 0; 2521 2522 M_ASSERTEXTPG(m); 2523 off = mtod(m, vm_offset_t); 2524 len = m->m_len; 2525 off += skip; 2526 len -= skip; 2527 2528 if (m->m_epg_hdrlen != 0) { 2529 if (off >= m->m_epg_hdrlen) { 2530 off -= m->m_epg_hdrlen; 2531 } else { 2532 seglen = m->m_epg_hdrlen - off; 2533 segoff = off; 2534 seglen = min(seglen, len); 2535 off = 0; 2536 len -= seglen; 2537 paddr = pmap_kextract( 2538 (vm_offset_t)&m->m_epg_hdr[segoff]); 2539 if (*nextaddr != paddr) 2540 nsegs++; 2541 *nextaddr = paddr + seglen; 2542 } 2543 } 2544 pgoff = m->m_epg_1st_off; 2545 for (i = 0; i < m->m_epg_npgs && len > 0; i++) { 2546 pglen = m_epg_pagelen(m, i, pgoff); 2547 if (off >= pglen) { 2548 off -= pglen; 2549 pgoff = 0; 2550 continue; 2551 } 2552 seglen = pglen - off; 2553 segoff = pgoff + off; 2554 off = 0; 2555 seglen = min(seglen, len); 2556 len -= seglen; 2557 paddr = m->m_epg_pa[i] + segoff; 2558 if (*nextaddr != paddr) 2559 nsegs++; 2560 *nextaddr = paddr + seglen; 2561 pgoff = 0; 2562 }; 2563 if (len != 0) { 2564 seglen = min(len, m->m_epg_trllen - off); 2565 len -= seglen; 2566 paddr = pmap_kextract((vm_offset_t)&m->m_epg_trail[off]); 2567 if (*nextaddr != paddr) 2568 nsegs++; 2569 *nextaddr = paddr + seglen; 2570 } 2571 2572 return (nsegs); 2573 } 2574 2575 2576 /* 2577 * Can deal with empty mbufs in the chain that have m_len = 0, but the chain 2578 * must have at least one mbuf that's not empty. It is possible for this 2579 * routine to return 0 if skip accounts for all the contents of the mbuf chain. 2580 */ 2581 static inline int 2582 count_mbuf_nsegs(struct mbuf *m, int skip, uint8_t *cflags) 2583 { 2584 vm_paddr_t nextaddr, paddr; 2585 vm_offset_t va; 2586 int len, nsegs; 2587 2588 M_ASSERTPKTHDR(m); 2589 MPASS(m->m_pkthdr.len > 0); 2590 MPASS(m->m_pkthdr.len >= skip); 2591 2592 nsegs = 0; 2593 nextaddr = 0; 2594 for (; m; m = m->m_next) { 2595 len = m->m_len; 2596 if (__predict_false(len == 0)) 2597 continue; 2598 if (skip >= len) { 2599 skip -= len; 2600 continue; 2601 } 2602 if ((m->m_flags & M_EXTPG) != 0) { 2603 *cflags |= MC_NOMAP; 2604 nsegs += count_mbuf_ext_pgs(m, skip, &nextaddr); 2605 skip = 0; 2606 continue; 2607 } 2608 va = mtod(m, vm_offset_t) + skip; 2609 len -= skip; 2610 skip = 0; 2611 paddr = pmap_kextract(va); 2612 nsegs += sglist_count((void *)(uintptr_t)va, len); 2613 if (paddr == nextaddr) 2614 nsegs--; 2615 nextaddr = pmap_kextract(va + len - 1) + 1; 2616 } 2617 2618 return (nsegs); 2619 } 2620 2621 /* 2622 * The maximum number of segments that can fit in a WR. 2623 */ 2624 static int 2625 max_nsegs_allowed(struct mbuf *m, bool vm_wr) 2626 { 2627 2628 if (vm_wr) { 2629 if (needs_tso(m)) 2630 return (TX_SGL_SEGS_VM_TSO); 2631 return (TX_SGL_SEGS_VM); 2632 } 2633 2634 if (needs_tso(m)) { 2635 if (needs_vxlan_tso(m)) 2636 return (TX_SGL_SEGS_VXLAN_TSO); 2637 else 2638 return (TX_SGL_SEGS_TSO); 2639 } 2640 2641 return (TX_SGL_SEGS); 2642 } 2643 2644 static struct timeval txerr_ratecheck = {0}; 2645 static const struct timeval txerr_interval = {3, 0}; 2646 2647 /* 2648 * Analyze the mbuf to determine its tx needs. The mbuf passed in may change: 2649 * a) caller can assume it's been freed if this function returns with an error. 2650 * b) it may get defragged up if the gather list is too long for the hardware. 2651 */ 2652 int 2653 parse_pkt(struct mbuf **mp, bool vm_wr) 2654 { 2655 struct mbuf *m0 = *mp, *m; 2656 int rc, nsegs, defragged = 0; 2657 struct ether_header *eh; 2658 #ifdef INET 2659 void *l3hdr; 2660 #endif 2661 #if defined(INET) || defined(INET6) 2662 int offset; 2663 struct tcphdr *tcp; 2664 #endif 2665 #if defined(KERN_TLS) || defined(RATELIMIT) 2666 struct m_snd_tag *mst; 2667 #endif 2668 uint16_t eh_type; 2669 uint8_t cflags; 2670 2671 cflags = 0; 2672 M_ASSERTPKTHDR(m0); 2673 if (__predict_false(m0->m_pkthdr.len < ETHER_HDR_LEN)) { 2674 rc = EINVAL; 2675 fail: 2676 m_freem(m0); 2677 *mp = NULL; 2678 return (rc); 2679 } 2680 restart: 2681 /* 2682 * First count the number of gather list segments in the payload. 2683 * Defrag the mbuf if nsegs exceeds the hardware limit. 2684 */ 2685 M_ASSERTPKTHDR(m0); 2686 MPASS(m0->m_pkthdr.len > 0); 2687 nsegs = count_mbuf_nsegs(m0, 0, &cflags); 2688 #if defined(KERN_TLS) || defined(RATELIMIT) 2689 if (m0->m_pkthdr.csum_flags & CSUM_SND_TAG) 2690 mst = m0->m_pkthdr.snd_tag; 2691 else 2692 mst = NULL; 2693 #endif 2694 #ifdef KERN_TLS 2695 if (mst != NULL && mst->sw->type == IF_SND_TAG_TYPE_TLS) { 2696 cflags |= MC_TLS; 2697 set_mbuf_cflags(m0, cflags); 2698 rc = t6_ktls_parse_pkt(m0); 2699 if (rc != 0) 2700 goto fail; 2701 return (EINPROGRESS); 2702 } 2703 #endif 2704 if (nsegs > max_nsegs_allowed(m0, vm_wr)) { 2705 if (defragged++ > 0) { 2706 rc = EFBIG; 2707 goto fail; 2708 } 2709 counter_u64_add(defrags, 1); 2710 if ((m = m_defrag(m0, M_NOWAIT)) == NULL) { 2711 rc = ENOMEM; 2712 goto fail; 2713 } 2714 *mp = m0 = m; /* update caller's copy after defrag */ 2715 goto restart; 2716 } 2717 2718 if (__predict_false(nsegs > 2 && m0->m_pkthdr.len <= MHLEN && 2719 !(cflags & MC_NOMAP))) { 2720 counter_u64_add(pullups, 1); 2721 m0 = m_pullup(m0, m0->m_pkthdr.len); 2722 if (m0 == NULL) { 2723 /* Should have left well enough alone. */ 2724 rc = EFBIG; 2725 goto fail; 2726 } 2727 *mp = m0; /* update caller's copy after pullup */ 2728 goto restart; 2729 } 2730 set_mbuf_nsegs(m0, nsegs); 2731 set_mbuf_cflags(m0, cflags); 2732 calculate_mbuf_len16(m0, vm_wr); 2733 2734 #ifdef RATELIMIT 2735 /* 2736 * Ethofld is limited to TCP and UDP for now, and only when L4 hw 2737 * checksumming is enabled. needs_outer_l4_csum happens to check for 2738 * all the right things. 2739 */ 2740 if (__predict_false(needs_eo(mst) && !needs_outer_l4_csum(m0))) { 2741 m_snd_tag_rele(m0->m_pkthdr.snd_tag); 2742 m0->m_pkthdr.snd_tag = NULL; 2743 m0->m_pkthdr.csum_flags &= ~CSUM_SND_TAG; 2744 mst = NULL; 2745 } 2746 #endif 2747 2748 if (!needs_hwcsum(m0) 2749 #ifdef RATELIMIT 2750 && !needs_eo(mst) 2751 #endif 2752 ) 2753 return (0); 2754 2755 m = m0; 2756 eh = mtod(m, struct ether_header *); 2757 eh_type = ntohs(eh->ether_type); 2758 if (eh_type == ETHERTYPE_VLAN) { 2759 struct ether_vlan_header *evh = (void *)eh; 2760 2761 eh_type = ntohs(evh->evl_proto); 2762 m0->m_pkthdr.l2hlen = sizeof(*evh); 2763 } else 2764 m0->m_pkthdr.l2hlen = sizeof(*eh); 2765 2766 #if defined(INET) || defined(INET6) 2767 offset = 0; 2768 #ifdef INET 2769 l3hdr = m_advance(&m, &offset, m0->m_pkthdr.l2hlen); 2770 #else 2771 m_advance(&m, &offset, m0->m_pkthdr.l2hlen); 2772 #endif 2773 #endif 2774 2775 switch (eh_type) { 2776 #ifdef INET6 2777 case ETHERTYPE_IPV6: 2778 m0->m_pkthdr.l3hlen = sizeof(struct ip6_hdr); 2779 break; 2780 #endif 2781 #ifdef INET 2782 case ETHERTYPE_IP: 2783 { 2784 struct ip *ip = l3hdr; 2785 2786 if (needs_vxlan_csum(m0)) { 2787 /* Driver will do the outer IP hdr checksum. */ 2788 ip->ip_sum = 0; 2789 if (needs_vxlan_tso(m0)) { 2790 const uint16_t ipl = ip->ip_len; 2791 2792 ip->ip_len = 0; 2793 ip->ip_sum = ~in_cksum_hdr(ip); 2794 ip->ip_len = ipl; 2795 } else 2796 ip->ip_sum = in_cksum_hdr(ip); 2797 } 2798 m0->m_pkthdr.l3hlen = ip->ip_hl << 2; 2799 break; 2800 } 2801 #endif 2802 default: 2803 if (ratecheck(&txerr_ratecheck, &txerr_interval)) { 2804 log(LOG_ERR, "%s: ethertype 0x%04x unknown. " 2805 "if_cxgbe must be compiled with the same " 2806 "INET/INET6 options as the kernel.\n", __func__, 2807 eh_type); 2808 } 2809 rc = EINVAL; 2810 goto fail; 2811 } 2812 2813 #if defined(INET) || defined(INET6) 2814 if (needs_vxlan_csum(m0)) { 2815 m0->m_pkthdr.l4hlen = sizeof(struct udphdr); 2816 m0->m_pkthdr.l5hlen = sizeof(struct vxlan_header); 2817 2818 /* Inner headers. */ 2819 eh = m_advance(&m, &offset, m0->m_pkthdr.l3hlen + 2820 sizeof(struct udphdr) + sizeof(struct vxlan_header)); 2821 eh_type = ntohs(eh->ether_type); 2822 if (eh_type == ETHERTYPE_VLAN) { 2823 struct ether_vlan_header *evh = (void *)eh; 2824 2825 eh_type = ntohs(evh->evl_proto); 2826 m0->m_pkthdr.inner_l2hlen = sizeof(*evh); 2827 } else 2828 m0->m_pkthdr.inner_l2hlen = sizeof(*eh); 2829 #ifdef INET 2830 l3hdr = m_advance(&m, &offset, m0->m_pkthdr.inner_l2hlen); 2831 #else 2832 m_advance(&m, &offset, m0->m_pkthdr.inner_l2hlen); 2833 #endif 2834 2835 switch (eh_type) { 2836 #ifdef INET6 2837 case ETHERTYPE_IPV6: 2838 m0->m_pkthdr.inner_l3hlen = sizeof(struct ip6_hdr); 2839 break; 2840 #endif 2841 #ifdef INET 2842 case ETHERTYPE_IP: 2843 { 2844 struct ip *ip = l3hdr; 2845 2846 m0->m_pkthdr.inner_l3hlen = ip->ip_hl << 2; 2847 break; 2848 } 2849 #endif 2850 default: 2851 if (ratecheck(&txerr_ratecheck, &txerr_interval)) { 2852 log(LOG_ERR, "%s: VXLAN hw offload requested" 2853 "with unknown ethertype 0x%04x. if_cxgbe " 2854 "must be compiled with the same INET/INET6 " 2855 "options as the kernel.\n", __func__, 2856 eh_type); 2857 } 2858 rc = EINVAL; 2859 goto fail; 2860 } 2861 if (needs_inner_tcp_csum(m0)) { 2862 tcp = m_advance(&m, &offset, m0->m_pkthdr.inner_l3hlen); 2863 m0->m_pkthdr.inner_l4hlen = tcp->th_off * 4; 2864 } 2865 MPASS((m0->m_pkthdr.csum_flags & CSUM_SND_TAG) == 0); 2866 m0->m_pkthdr.csum_flags &= CSUM_INNER_IP6_UDP | 2867 CSUM_INNER_IP6_TCP | CSUM_INNER_IP6_TSO | CSUM_INNER_IP | 2868 CSUM_INNER_IP_UDP | CSUM_INNER_IP_TCP | CSUM_INNER_IP_TSO | 2869 CSUM_ENCAP_VXLAN; 2870 } 2871 2872 if (needs_outer_tcp_csum(m0)) { 2873 tcp = m_advance(&m, &offset, m0->m_pkthdr.l3hlen); 2874 m0->m_pkthdr.l4hlen = tcp->th_off * 4; 2875 #ifdef RATELIMIT 2876 if (tsclk >= 0 && *(uint32_t *)(tcp + 1) == ntohl(0x0101080a)) { 2877 set_mbuf_eo_tsclk_tsoff(m0, 2878 V_FW_ETH_TX_EO_WR_TSCLK(tsclk) | 2879 V_FW_ETH_TX_EO_WR_TSOFF(sizeof(*tcp) / 2 + 1)); 2880 } else 2881 set_mbuf_eo_tsclk_tsoff(m0, 0); 2882 } else if (needs_outer_udp_csum(m0)) { 2883 m0->m_pkthdr.l4hlen = sizeof(struct udphdr); 2884 #endif 2885 } 2886 #ifdef RATELIMIT 2887 if (needs_eo(mst)) { 2888 u_int immhdrs; 2889 2890 /* EO WRs have the headers in the WR and not the GL. */ 2891 immhdrs = m0->m_pkthdr.l2hlen + m0->m_pkthdr.l3hlen + 2892 m0->m_pkthdr.l4hlen; 2893 cflags = 0; 2894 nsegs = count_mbuf_nsegs(m0, immhdrs, &cflags); 2895 MPASS(cflags == mbuf_cflags(m0)); 2896 set_mbuf_eo_nsegs(m0, nsegs); 2897 set_mbuf_eo_len16(m0, 2898 txpkt_eo_len16(nsegs, immhdrs, needs_tso(m0))); 2899 rc = ethofld_transmit(mst->ifp, m0); 2900 if (rc != 0) 2901 goto fail; 2902 return (EINPROGRESS); 2903 } 2904 #endif 2905 #endif 2906 MPASS(m0 == *mp); 2907 return (0); 2908 } 2909 2910 void * 2911 start_wrq_wr(struct sge_wrq *wrq, int len16, struct wrq_cookie *cookie) 2912 { 2913 struct sge_eq *eq = &wrq->eq; 2914 struct adapter *sc = wrq->adapter; 2915 int ndesc, available; 2916 struct wrqe *wr; 2917 void *w; 2918 2919 MPASS(len16 > 0); 2920 ndesc = tx_len16_to_desc(len16); 2921 MPASS(ndesc > 0 && ndesc <= SGE_MAX_WR_NDESC); 2922 2923 EQ_LOCK(eq); 2924 if (__predict_false((eq->flags & EQ_HW_ALLOCATED) == 0)) { 2925 EQ_UNLOCK(eq); 2926 return (NULL); 2927 } 2928 2929 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 2930 drain_wrq_wr_list(sc, wrq); 2931 2932 if (!STAILQ_EMPTY(&wrq->wr_list)) { 2933 slowpath: 2934 EQ_UNLOCK(eq); 2935 wr = alloc_wrqe(len16 * 16, wrq); 2936 if (__predict_false(wr == NULL)) 2937 return (NULL); 2938 cookie->pidx = -1; 2939 cookie->ndesc = ndesc; 2940 return (&wr->wr); 2941 } 2942 2943 eq->cidx = read_hw_cidx(eq); 2944 if (eq->pidx == eq->cidx) 2945 available = eq->sidx - 1; 2946 else 2947 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2948 if (available < ndesc) 2949 goto slowpath; 2950 2951 cookie->pidx = eq->pidx; 2952 cookie->ndesc = ndesc; 2953 TAILQ_INSERT_TAIL(&wrq->incomplete_wrs, cookie, link); 2954 2955 w = &eq->desc[eq->pidx]; 2956 IDXINCR(eq->pidx, ndesc, eq->sidx); 2957 if (__predict_false(cookie->pidx + ndesc > eq->sidx)) { 2958 w = &wrq->ss[0]; 2959 wrq->ss_pidx = cookie->pidx; 2960 wrq->ss_len = len16 * 16; 2961 } 2962 2963 EQ_UNLOCK(eq); 2964 2965 return (w); 2966 } 2967 2968 void 2969 commit_wrq_wr(struct sge_wrq *wrq, void *w, struct wrq_cookie *cookie) 2970 { 2971 struct sge_eq *eq = &wrq->eq; 2972 struct adapter *sc = wrq->adapter; 2973 int ndesc, pidx; 2974 struct wrq_cookie *prev, *next; 2975 2976 if (cookie->pidx == -1) { 2977 struct wrqe *wr = __containerof(w, struct wrqe, wr); 2978 2979 t4_wrq_tx(sc, wr); 2980 return; 2981 } 2982 2983 if (__predict_false(w == &wrq->ss[0])) { 2984 int n = (eq->sidx - wrq->ss_pidx) * EQ_ESIZE; 2985 2986 MPASS(wrq->ss_len > n); /* WR had better wrap around. */ 2987 bcopy(&wrq->ss[0], &eq->desc[wrq->ss_pidx], n); 2988 bcopy(&wrq->ss[n], &eq->desc[0], wrq->ss_len - n); 2989 wrq->tx_wrs_ss++; 2990 } else 2991 wrq->tx_wrs_direct++; 2992 2993 EQ_LOCK(eq); 2994 ndesc = cookie->ndesc; /* Can be more than SGE_MAX_WR_NDESC here. */ 2995 pidx = cookie->pidx; 2996 MPASS(pidx >= 0 && pidx < eq->sidx); 2997 prev = TAILQ_PREV(cookie, wrq_incomplete_wrs, link); 2998 next = TAILQ_NEXT(cookie, link); 2999 if (prev == NULL) { 3000 MPASS(pidx == eq->dbidx); 3001 if (next == NULL || ndesc >= 16) { 3002 int available; 3003 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */ 3004 3005 /* 3006 * Note that the WR via which we'll request tx updates 3007 * is at pidx and not eq->pidx, which has moved on 3008 * already. 3009 */ 3010 dst = (void *)&eq->desc[pidx]; 3011 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 3012 if (available < eq->sidx / 4 && 3013 atomic_cmpset_int(&eq->equiq, 0, 1)) { 3014 /* 3015 * XXX: This is not 100% reliable with some 3016 * types of WRs. But this is a very unusual 3017 * situation for an ofld/ctrl queue anyway. 3018 */ 3019 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ | 3020 F_FW_WR_EQUEQ); 3021 } 3022 3023 if (__predict_true(eq->flags & EQ_HW_ALLOCATED)) 3024 ring_eq_db(wrq->adapter, eq, ndesc); 3025 else 3026 IDXINCR(eq->dbidx, ndesc, eq->sidx); 3027 } else { 3028 MPASS(IDXDIFF(next->pidx, pidx, eq->sidx) == ndesc); 3029 next->pidx = pidx; 3030 next->ndesc += ndesc; 3031 } 3032 } else { 3033 MPASS(IDXDIFF(pidx, prev->pidx, eq->sidx) == prev->ndesc); 3034 prev->ndesc += ndesc; 3035 } 3036 TAILQ_REMOVE(&wrq->incomplete_wrs, cookie, link); 3037 3038 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 3039 drain_wrq_wr_list(sc, wrq); 3040 3041 #ifdef INVARIANTS 3042 if (TAILQ_EMPTY(&wrq->incomplete_wrs)) { 3043 /* Doorbell must have caught up to the pidx. */ 3044 MPASS(wrq->eq.pidx == wrq->eq.dbidx); 3045 } 3046 #endif 3047 EQ_UNLOCK(eq); 3048 } 3049 3050 static u_int 3051 can_resume_eth_tx(struct mp_ring *r) 3052 { 3053 struct sge_eq *eq = r->cookie; 3054 3055 return (total_available_tx_desc(eq) > eq->sidx / 8); 3056 } 3057 3058 static inline bool 3059 cannot_use_txpkts(struct mbuf *m) 3060 { 3061 /* maybe put a GL limit too, to avoid silliness? */ 3062 3063 return (needs_tso(m) || (mbuf_cflags(m) & (MC_RAW_WR | MC_TLS)) != 0); 3064 } 3065 3066 static inline int 3067 discard_tx(struct sge_eq *eq) 3068 { 3069 3070 return ((eq->flags & (EQ_ENABLED | EQ_QFLUSH)) != EQ_ENABLED); 3071 } 3072 3073 static inline int 3074 wr_can_update_eq(void *p) 3075 { 3076 struct fw_eth_tx_pkts_wr *wr = p; 3077 3078 switch (G_FW_WR_OP(be32toh(wr->op_pkd))) { 3079 case FW_ULPTX_WR: 3080 case FW_ETH_TX_PKT_WR: 3081 case FW_ETH_TX_PKTS_WR: 3082 case FW_ETH_TX_PKTS2_WR: 3083 case FW_ETH_TX_PKT_VM_WR: 3084 case FW_ETH_TX_PKTS_VM_WR: 3085 return (1); 3086 default: 3087 return (0); 3088 } 3089 } 3090 3091 static inline void 3092 set_txupdate_flags(struct sge_txq *txq, u_int avail, 3093 struct fw_eth_tx_pkt_wr *wr) 3094 { 3095 struct sge_eq *eq = &txq->eq; 3096 struct txpkts *txp = &txq->txp; 3097 3098 if ((txp->npkt > 0 || avail < eq->sidx / 2) && 3099 atomic_cmpset_int(&eq->equiq, 0, 1)) { 3100 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ | F_FW_WR_EQUIQ); 3101 eq->equeqidx = eq->pidx; 3102 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 32) { 3103 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ); 3104 eq->equeqidx = eq->pidx; 3105 } 3106 } 3107 3108 #if defined(__i386__) || defined(__amd64__) 3109 extern uint64_t tsc_freq; 3110 #endif 3111 3112 static inline bool 3113 record_eth_tx_time(struct sge_txq *txq) 3114 { 3115 const uint64_t cycles = get_cyclecount(); 3116 const uint64_t last_tx = txq->last_tx; 3117 #if defined(__i386__) || defined(__amd64__) 3118 const uint64_t itg = tsc_freq * t4_tx_coalesce_gap / 1000000; 3119 #else 3120 const uint64_t itg = 0; 3121 #endif 3122 3123 MPASS(cycles >= last_tx); 3124 txq->last_tx = cycles; 3125 return (cycles - last_tx < itg); 3126 } 3127 3128 /* 3129 * r->items[cidx] to r->items[pidx], with a wraparound at r->size, are ready to 3130 * be consumed. Return the actual number consumed. 0 indicates a stall. 3131 */ 3132 static u_int 3133 eth_tx(struct mp_ring *r, u_int cidx, u_int pidx, bool *coalescing) 3134 { 3135 struct sge_txq *txq = r->cookie; 3136 if_t ifp = txq->ifp; 3137 struct sge_eq *eq = &txq->eq; 3138 struct txpkts *txp = &txq->txp; 3139 struct vi_info *vi = if_getsoftc(ifp); 3140 struct adapter *sc = vi->adapter; 3141 u_int total, remaining; /* # of packets */ 3142 u_int n, avail, dbdiff; /* # of hardware descriptors */ 3143 int i, rc; 3144 struct mbuf *m0; 3145 bool snd, recent_tx; 3146 void *wr; /* start of the last WR written to the ring */ 3147 3148 TXQ_LOCK_ASSERT_OWNED(txq); 3149 recent_tx = record_eth_tx_time(txq); 3150 3151 remaining = IDXDIFF(pidx, cidx, r->size); 3152 if (__predict_false(discard_tx(eq))) { 3153 for (i = 0; i < txp->npkt; i++) 3154 m_freem(txp->mb[i]); 3155 txp->npkt = 0; 3156 while (cidx != pidx) { 3157 m0 = r->items[cidx]; 3158 m_freem(m0); 3159 if (++cidx == r->size) 3160 cidx = 0; 3161 } 3162 reclaim_tx_descs(txq, eq->sidx); 3163 *coalescing = false; 3164 return (remaining); /* emptied */ 3165 } 3166 3167 /* How many hardware descriptors do we have readily available. */ 3168 if (eq->pidx == eq->cidx) 3169 avail = eq->sidx - 1; 3170 else 3171 avail = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 3172 3173 total = 0; 3174 if (remaining == 0) { 3175 txp->score = 0; 3176 txq->txpkts_flush++; 3177 goto send_txpkts; 3178 } 3179 3180 dbdiff = 0; 3181 MPASS(remaining > 0); 3182 while (remaining > 0) { 3183 m0 = r->items[cidx]; 3184 M_ASSERTPKTHDR(m0); 3185 MPASS(m0->m_nextpkt == NULL); 3186 3187 if (avail < 2 * SGE_MAX_WR_NDESC) 3188 avail += reclaim_tx_descs(txq, 64); 3189 3190 if (t4_tx_coalesce == 0 && txp->npkt == 0) 3191 goto skip_coalescing; 3192 if (cannot_use_txpkts(m0)) 3193 txp->score = 0; 3194 else if (recent_tx) { 3195 if (++txp->score == 0) 3196 txp->score = UINT8_MAX; 3197 } else 3198 txp->score = 1; 3199 if (txp->npkt > 0 || remaining > 1 || 3200 txp->score >= t4_tx_coalesce_pkts || 3201 atomic_load_int(&txq->eq.equiq) != 0) { 3202 if (vi->flags & TX_USES_VM_WR) 3203 rc = add_to_txpkts_vf(sc, txq, m0, avail, &snd); 3204 else 3205 rc = add_to_txpkts_pf(sc, txq, m0, avail, &snd); 3206 } else { 3207 snd = false; 3208 rc = EINVAL; 3209 } 3210 if (snd) { 3211 MPASS(txp->npkt > 0); 3212 for (i = 0; i < txp->npkt; i++) 3213 ETHER_BPF_MTAP(ifp, txp->mb[i]); 3214 if (txp->npkt > 1) { 3215 MPASS(avail >= tx_len16_to_desc(txp->len16)); 3216 if (vi->flags & TX_USES_VM_WR) 3217 n = write_txpkts_vm_wr(sc, txq); 3218 else 3219 n = write_txpkts_wr(sc, txq); 3220 } else { 3221 MPASS(avail >= 3222 tx_len16_to_desc(mbuf_len16(txp->mb[0]))); 3223 if (vi->flags & TX_USES_VM_WR) 3224 n = write_txpkt_vm_wr(sc, txq, 3225 txp->mb[0]); 3226 else 3227 n = write_txpkt_wr(sc, txq, txp->mb[0], 3228 avail); 3229 } 3230 MPASS(n <= SGE_MAX_WR_NDESC); 3231 avail -= n; 3232 dbdiff += n; 3233 wr = &eq->desc[eq->pidx]; 3234 IDXINCR(eq->pidx, n, eq->sidx); 3235 txp->npkt = 0; /* emptied */ 3236 } 3237 if (rc == 0) { 3238 /* m0 was coalesced into txq->txpkts. */ 3239 goto next_mbuf; 3240 } 3241 if (rc == EAGAIN) { 3242 /* 3243 * m0 is suitable for tx coalescing but could not be 3244 * combined with the existing txq->txpkts, which has now 3245 * been transmitted. Start a new txpkts with m0. 3246 */ 3247 MPASS(snd); 3248 MPASS(txp->npkt == 0); 3249 continue; 3250 } 3251 3252 MPASS(rc != 0 && rc != EAGAIN); 3253 MPASS(txp->npkt == 0); 3254 skip_coalescing: 3255 n = tx_len16_to_desc(mbuf_len16(m0)); 3256 if (__predict_false(avail < n)) { 3257 avail += reclaim_tx_descs(txq, min(n, 32)); 3258 if (avail < n) 3259 break; /* out of descriptors */ 3260 } 3261 3262 wr = &eq->desc[eq->pidx]; 3263 if (mbuf_cflags(m0) & MC_RAW_WR) { 3264 n = write_raw_wr(txq, wr, m0, avail); 3265 #ifdef KERN_TLS 3266 } else if (mbuf_cflags(m0) & MC_TLS) { 3267 ETHER_BPF_MTAP(ifp, m0); 3268 n = t6_ktls_write_wr(txq, wr, m0, avail); 3269 #endif 3270 } else { 3271 ETHER_BPF_MTAP(ifp, m0); 3272 if (vi->flags & TX_USES_VM_WR) 3273 n = write_txpkt_vm_wr(sc, txq, m0); 3274 else 3275 n = write_txpkt_wr(sc, txq, m0, avail); 3276 } 3277 MPASS(n >= 1 && n <= avail); 3278 if (!(mbuf_cflags(m0) & MC_TLS)) 3279 MPASS(n <= SGE_MAX_WR_NDESC); 3280 3281 avail -= n; 3282 dbdiff += n; 3283 IDXINCR(eq->pidx, n, eq->sidx); 3284 3285 if (dbdiff >= 512 / EQ_ESIZE) { /* X_FETCHBURSTMAX_512B */ 3286 if (wr_can_update_eq(wr)) 3287 set_txupdate_flags(txq, avail, wr); 3288 ring_eq_db(sc, eq, dbdiff); 3289 avail += reclaim_tx_descs(txq, 32); 3290 dbdiff = 0; 3291 } 3292 next_mbuf: 3293 total++; 3294 remaining--; 3295 if (__predict_false(++cidx == r->size)) 3296 cidx = 0; 3297 } 3298 if (dbdiff != 0) { 3299 if (wr_can_update_eq(wr)) 3300 set_txupdate_flags(txq, avail, wr); 3301 ring_eq_db(sc, eq, dbdiff); 3302 reclaim_tx_descs(txq, 32); 3303 } else if (eq->pidx == eq->cidx && txp->npkt > 0 && 3304 atomic_load_int(&txq->eq.equiq) == 0) { 3305 /* 3306 * If nothing was submitted to the chip for tx (it was coalesced 3307 * into txpkts instead) and there is no tx update outstanding 3308 * then we need to send txpkts now. 3309 */ 3310 send_txpkts: 3311 MPASS(txp->npkt > 0); 3312 for (i = 0; i < txp->npkt; i++) 3313 ETHER_BPF_MTAP(ifp, txp->mb[i]); 3314 if (txp->npkt > 1) { 3315 MPASS(avail >= tx_len16_to_desc(txp->len16)); 3316 if (vi->flags & TX_USES_VM_WR) 3317 n = write_txpkts_vm_wr(sc, txq); 3318 else 3319 n = write_txpkts_wr(sc, txq); 3320 } else { 3321 MPASS(avail >= 3322 tx_len16_to_desc(mbuf_len16(txp->mb[0]))); 3323 if (vi->flags & TX_USES_VM_WR) 3324 n = write_txpkt_vm_wr(sc, txq, txp->mb[0]); 3325 else 3326 n = write_txpkt_wr(sc, txq, txp->mb[0], avail); 3327 } 3328 MPASS(n <= SGE_MAX_WR_NDESC); 3329 wr = &eq->desc[eq->pidx]; 3330 IDXINCR(eq->pidx, n, eq->sidx); 3331 txp->npkt = 0; /* emptied */ 3332 3333 MPASS(wr_can_update_eq(wr)); 3334 set_txupdate_flags(txq, avail - n, wr); 3335 ring_eq_db(sc, eq, n); 3336 reclaim_tx_descs(txq, 32); 3337 } 3338 *coalescing = txp->npkt > 0; 3339 3340 return (total); 3341 } 3342 3343 static inline void 3344 init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int pktc_idx, 3345 int qsize, int intr_idx, int cong, int qtype) 3346 { 3347 3348 KASSERT(tmr_idx >= 0 && tmr_idx < SGE_NTIMERS, 3349 ("%s: bad tmr_idx %d", __func__, tmr_idx)); 3350 KASSERT(pktc_idx < SGE_NCOUNTERS, /* -ve is ok, means don't use */ 3351 ("%s: bad pktc_idx %d", __func__, pktc_idx)); 3352 KASSERT(intr_idx >= -1 && intr_idx < sc->intr_count, 3353 ("%s: bad intr_idx %d", __func__, intr_idx)); 3354 KASSERT(qtype == FW_IQ_IQTYPE_OTHER || qtype == FW_IQ_IQTYPE_NIC || 3355 qtype == FW_IQ_IQTYPE_OFLD, ("%s: bad qtype %d", __func__, qtype)); 3356 3357 iq->flags = 0; 3358 iq->state = IQS_DISABLED; 3359 iq->adapter = sc; 3360 iq->qtype = qtype; 3361 iq->intr_params = V_QINTR_TIMER_IDX(tmr_idx); 3362 iq->intr_pktc_idx = SGE_NCOUNTERS - 1; 3363 if (pktc_idx >= 0) { 3364 iq->intr_params |= F_QINTR_CNT_EN; 3365 iq->intr_pktc_idx = pktc_idx; 3366 } 3367 iq->qsize = roundup2(qsize, 16); /* See FW_IQ_CMD/iqsize */ 3368 iq->sidx = iq->qsize - sc->params.sge.spg_len / IQ_ESIZE; 3369 iq->intr_idx = intr_idx; 3370 iq->cong_drop = cong; 3371 } 3372 3373 static inline void 3374 init_fl(struct adapter *sc, struct sge_fl *fl, int qsize, int maxp, char *name) 3375 { 3376 struct sge_params *sp = &sc->params.sge; 3377 3378 fl->qsize = qsize; 3379 fl->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE; 3380 strlcpy(fl->lockname, name, sizeof(fl->lockname)); 3381 mtx_init(&fl->fl_lock, fl->lockname, NULL, MTX_DEF); 3382 if (sc->flags & BUF_PACKING_OK && 3383 ((!is_t4(sc) && buffer_packing) || /* T5+: enabled unless 0 */ 3384 (is_t4(sc) && buffer_packing == 1)))/* T4: disabled unless 1 */ 3385 fl->flags |= FL_BUF_PACKING; 3386 fl->zidx = find_refill_source(sc, maxp, fl->flags & FL_BUF_PACKING); 3387 fl->safe_zidx = sc->sge.safe_zidx; 3388 if (fl->flags & FL_BUF_PACKING) { 3389 fl->lowat = roundup2(sp->fl_starve_threshold2, 8); 3390 fl->buf_boundary = sp->pack_boundary; 3391 } else { 3392 fl->lowat = roundup2(sp->fl_starve_threshold, 8); 3393 fl->buf_boundary = 16; 3394 } 3395 if (fl_pad && fl->buf_boundary < sp->pad_boundary) 3396 fl->buf_boundary = sp->pad_boundary; 3397 } 3398 3399 static inline void 3400 init_eq(struct adapter *sc, struct sge_eq *eq, int eqtype, int qsize, 3401 uint8_t port_id, struct sge_iq *iq, char *name) 3402 { 3403 KASSERT(eqtype >= EQ_CTRL && eqtype <= EQ_OFLD, 3404 ("%s: bad qtype %d", __func__, eqtype)); 3405 3406 eq->type = eqtype; 3407 eq->port_id = port_id; 3408 eq->tx_chan = sc->port[port_id]->tx_chan; 3409 eq->iq = iq; 3410 eq->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE; 3411 strlcpy(eq->lockname, name, sizeof(eq->lockname)); 3412 mtx_init(&eq->eq_lock, eq->lockname, NULL, MTX_DEF); 3413 } 3414 3415 int 3416 alloc_ring(struct adapter *sc, size_t len, bus_dma_tag_t *tag, 3417 bus_dmamap_t *map, bus_addr_t *pa, void **va) 3418 { 3419 int rc; 3420 3421 rc = bus_dma_tag_create(sc->dmat, 512, 0, BUS_SPACE_MAXADDR, 3422 BUS_SPACE_MAXADDR, NULL, NULL, len, 1, len, 0, NULL, NULL, tag); 3423 if (rc != 0) { 3424 CH_ERR(sc, "cannot allocate DMA tag: %d\n", rc); 3425 goto done; 3426 } 3427 3428 rc = bus_dmamem_alloc(*tag, va, 3429 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, map); 3430 if (rc != 0) { 3431 CH_ERR(sc, "cannot allocate DMA memory: %d\n", rc); 3432 goto done; 3433 } 3434 3435 rc = bus_dmamap_load(*tag, *map, *va, len, oneseg_dma_callback, pa, 0); 3436 if (rc != 0) { 3437 CH_ERR(sc, "cannot load DMA map: %d\n", rc); 3438 goto done; 3439 } 3440 done: 3441 if (rc) 3442 free_ring(sc, *tag, *map, *pa, *va); 3443 3444 return (rc); 3445 } 3446 3447 int 3448 free_ring(struct adapter *sc, bus_dma_tag_t tag, bus_dmamap_t map, 3449 bus_addr_t pa, void *va) 3450 { 3451 if (pa) 3452 bus_dmamap_unload(tag, map); 3453 if (va) 3454 bus_dmamem_free(tag, va, map); 3455 if (tag) 3456 bus_dma_tag_destroy(tag); 3457 3458 return (0); 3459 } 3460 3461 /* 3462 * Allocates the software resources (mainly memory and sysctl nodes) for an 3463 * ingress queue and an optional freelist. 3464 * 3465 * Sets IQ_SW_ALLOCATED and returns 0 on success. 3466 */ 3467 static int 3468 alloc_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl, 3469 struct sysctl_ctx_list *ctx, struct sysctl_oid *oid) 3470 { 3471 int rc; 3472 size_t len; 3473 struct adapter *sc = vi->adapter; 3474 3475 MPASS(!(iq->flags & IQ_SW_ALLOCATED)); 3476 3477 len = iq->qsize * IQ_ESIZE; 3478 rc = alloc_ring(sc, len, &iq->desc_tag, &iq->desc_map, &iq->ba, 3479 (void **)&iq->desc); 3480 if (rc != 0) 3481 return (rc); 3482 3483 if (fl) { 3484 len = fl->qsize * EQ_ESIZE; 3485 rc = alloc_ring(sc, len, &fl->desc_tag, &fl->desc_map, 3486 &fl->ba, (void **)&fl->desc); 3487 if (rc) { 3488 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, 3489 iq->desc); 3490 return (rc); 3491 } 3492 3493 /* Allocate space for one software descriptor per buffer. */ 3494 fl->sdesc = malloc(fl->sidx * 8 * sizeof(struct fl_sdesc), 3495 M_CXGBE, M_ZERO | M_WAITOK); 3496 3497 add_fl_sysctls(sc, ctx, oid, fl); 3498 iq->flags |= IQ_HAS_FL; 3499 } 3500 add_iq_sysctls(ctx, oid, iq); 3501 iq->flags |= IQ_SW_ALLOCATED; 3502 3503 return (0); 3504 } 3505 3506 /* 3507 * Frees all software resources (memory and locks) associated with an ingress 3508 * queue and an optional freelist. 3509 */ 3510 static void 3511 free_iq_fl(struct adapter *sc, struct sge_iq *iq, struct sge_fl *fl) 3512 { 3513 MPASS(iq->flags & IQ_SW_ALLOCATED); 3514 3515 if (fl) { 3516 MPASS(iq->flags & IQ_HAS_FL); 3517 free_ring(sc, fl->desc_tag, fl->desc_map, fl->ba, fl->desc); 3518 free_fl_buffers(sc, fl); 3519 free(fl->sdesc, M_CXGBE); 3520 mtx_destroy(&fl->fl_lock); 3521 bzero(fl, sizeof(*fl)); 3522 } 3523 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, iq->desc); 3524 bzero(iq, sizeof(*iq)); 3525 } 3526 3527 /* 3528 * Allocates a hardware ingress queue and an optional freelist that will be 3529 * associated with it. 3530 * 3531 * Returns errno on failure. Resources allocated up to that point may still be 3532 * allocated. Caller is responsible for cleanup in case this function fails. 3533 */ 3534 static int 3535 alloc_iq_fl_hwq(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl) 3536 { 3537 int rc, cntxt_id, cong_map; 3538 struct fw_iq_cmd c; 3539 struct adapter *sc = vi->adapter; 3540 struct port_info *pi = vi->pi; 3541 __be32 v = 0; 3542 3543 MPASS (!(iq->flags & IQ_HW_ALLOCATED)); 3544 3545 bzero(&c, sizeof(c)); 3546 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 3547 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) | 3548 V_FW_IQ_CMD_VFN(0)); 3549 3550 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART | 3551 FW_LEN16(c)); 3552 3553 /* Special handling for firmware event queue */ 3554 if (iq == &sc->sge.fwq) 3555 v |= F_FW_IQ_CMD_IQASYNCH; 3556 3557 if (iq->intr_idx < 0) { 3558 /* Forwarded interrupts, all headed to fwq */ 3559 v |= F_FW_IQ_CMD_IQANDST; 3560 v |= V_FW_IQ_CMD_IQANDSTINDEX(sc->sge.fwq.cntxt_id); 3561 } else { 3562 KASSERT(iq->intr_idx < sc->intr_count, 3563 ("%s: invalid direct intr_idx %d", __func__, iq->intr_idx)); 3564 v |= V_FW_IQ_CMD_IQANDSTINDEX(iq->intr_idx); 3565 } 3566 3567 bzero(iq->desc, iq->qsize * IQ_ESIZE); 3568 c.type_to_iqandstindex = htobe32(v | 3569 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) | 3570 V_FW_IQ_CMD_VIID(vi->viid) | 3571 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT)); 3572 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->tx_chan) | 3573 F_FW_IQ_CMD_IQGTSMODE | 3574 V_FW_IQ_CMD_IQINTCNTTHRESH(iq->intr_pktc_idx) | 3575 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4)); 3576 c.iqsize = htobe16(iq->qsize); 3577 c.iqaddr = htobe64(iq->ba); 3578 c.iqns_to_fl0congen = htobe32(V_FW_IQ_CMD_IQTYPE(iq->qtype)); 3579 if (iq->cong_drop != -1) { 3580 cong_map = iq->qtype == IQ_ETH ? pi->rx_e_chan_map : 0; 3581 c.iqns_to_fl0congen |= htobe32(F_FW_IQ_CMD_IQFLINTCONGEN); 3582 } 3583 3584 if (fl) { 3585 bzero(fl->desc, fl->sidx * EQ_ESIZE + sc->params.sge.spg_len); 3586 c.iqns_to_fl0congen |= 3587 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) | 3588 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO | 3589 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) | 3590 (fl->flags & FL_BUF_PACKING ? F_FW_IQ_CMD_FL0PACKEN : 3591 0)); 3592 if (iq->cong_drop != -1) { 3593 c.iqns_to_fl0congen |= 3594 htobe32(V_FW_IQ_CMD_FL0CNGCHMAP(cong_map) | 3595 F_FW_IQ_CMD_FL0CONGCIF | 3596 F_FW_IQ_CMD_FL0CONGEN); 3597 } 3598 c.fl0dcaen_to_fl0cidxfthresh = 3599 htobe16(V_FW_IQ_CMD_FL0FBMIN(chip_id(sc) <= CHELSIO_T5 ? 3600 X_FETCHBURSTMIN_128B : X_FETCHBURSTMIN_64B_T6) | 3601 V_FW_IQ_CMD_FL0FBMAX(chip_id(sc) <= CHELSIO_T5 ? 3602 X_FETCHBURSTMAX_512B : X_FETCHBURSTMAX_256B)); 3603 c.fl0size = htobe16(fl->qsize); 3604 c.fl0addr = htobe64(fl->ba); 3605 } 3606 3607 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3608 if (rc != 0) { 3609 CH_ERR(sc, "failed to create hw ingress queue: %d\n", rc); 3610 return (rc); 3611 } 3612 3613 iq->cidx = 0; 3614 iq->gen = F_RSPD_GEN; 3615 iq->cntxt_id = be16toh(c.iqid); 3616 iq->abs_id = be16toh(c.physiqid); 3617 3618 cntxt_id = iq->cntxt_id - sc->sge.iq_start; 3619 if (cntxt_id >= sc->sge.iqmap_sz) { 3620 panic ("%s: iq->cntxt_id (%d) more than the max (%d)", __func__, 3621 cntxt_id, sc->sge.iqmap_sz - 1); 3622 } 3623 sc->sge.iqmap[cntxt_id] = iq; 3624 3625 if (fl) { 3626 u_int qid; 3627 #ifdef INVARIANTS 3628 int i; 3629 3630 MPASS(!(fl->flags & FL_BUF_RESUME)); 3631 for (i = 0; i < fl->sidx * 8; i++) 3632 MPASS(fl->sdesc[i].cl == NULL); 3633 #endif 3634 fl->cntxt_id = be16toh(c.fl0id); 3635 fl->pidx = fl->cidx = fl->hw_cidx = fl->dbidx = 0; 3636 fl->rx_offset = 0; 3637 fl->flags &= ~(FL_STARVING | FL_DOOMED); 3638 3639 cntxt_id = fl->cntxt_id - sc->sge.eq_start; 3640 if (cntxt_id >= sc->sge.eqmap_sz) { 3641 panic("%s: fl->cntxt_id (%d) more than the max (%d)", 3642 __func__, cntxt_id, sc->sge.eqmap_sz - 1); 3643 } 3644 sc->sge.eqmap[cntxt_id] = (void *)fl; 3645 3646 qid = fl->cntxt_id; 3647 if (isset(&sc->doorbells, DOORBELL_UDB)) { 3648 uint32_t s_qpp = sc->params.sge.eq_s_qpp; 3649 uint32_t mask = (1 << s_qpp) - 1; 3650 volatile uint8_t *udb; 3651 3652 udb = sc->udbs_base + UDBS_DB_OFFSET; 3653 udb += (qid >> s_qpp) << PAGE_SHIFT; 3654 qid &= mask; 3655 if (qid < PAGE_SIZE / UDBS_SEG_SIZE) { 3656 udb += qid << UDBS_SEG_SHIFT; 3657 qid = 0; 3658 } 3659 fl->udb = (volatile void *)udb; 3660 } 3661 fl->dbval = V_QID(qid) | sc->chip_params->sge_fl_db; 3662 3663 FL_LOCK(fl); 3664 /* Enough to make sure the SGE doesn't think it's starved */ 3665 refill_fl(sc, fl, fl->lowat); 3666 FL_UNLOCK(fl); 3667 } 3668 3669 if (chip_id(sc) >= CHELSIO_T5 && !(sc->flags & IS_VF) && 3670 iq->cong_drop != -1) { 3671 t4_sge_set_conm_context(sc, iq->cntxt_id, iq->cong_drop, 3672 cong_map); 3673 } 3674 3675 /* Enable IQ interrupts */ 3676 atomic_store_rel_int(&iq->state, IQS_IDLE); 3677 t4_write_reg(sc, sc->sge_gts_reg, V_SEINTARM(iq->intr_params) | 3678 V_INGRESSQID(iq->cntxt_id)); 3679 3680 iq->flags |= IQ_HW_ALLOCATED; 3681 3682 return (0); 3683 } 3684 3685 static int 3686 free_iq_fl_hwq(struct adapter *sc, struct sge_iq *iq, struct sge_fl *fl) 3687 { 3688 int rc; 3689 3690 MPASS(iq->flags & IQ_HW_ALLOCATED); 3691 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0, FW_IQ_TYPE_FL_INT_CAP, 3692 iq->cntxt_id, fl ? fl->cntxt_id : 0xffff, 0xffff); 3693 if (rc != 0) { 3694 CH_ERR(sc, "failed to free iq %p: %d\n", iq, rc); 3695 return (rc); 3696 } 3697 iq->flags &= ~IQ_HW_ALLOCATED; 3698 3699 return (0); 3700 } 3701 3702 static void 3703 add_iq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid, 3704 struct sge_iq *iq) 3705 { 3706 struct sysctl_oid_list *children; 3707 3708 if (ctx == NULL || oid == NULL) 3709 return; 3710 3711 children = SYSCTL_CHILDREN(oid); 3712 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, &iq->ba, 3713 "bus address of descriptor ring"); 3714 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3715 iq->qsize * IQ_ESIZE, "descriptor ring size in bytes"); 3716 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "abs_id", CTLFLAG_RD, 3717 &iq->abs_id, 0, "absolute id of the queue"); 3718 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 3719 &iq->cntxt_id, 0, "SGE context id of the queue"); 3720 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &iq->cidx, 3721 0, "consumer index"); 3722 } 3723 3724 static void 3725 add_fl_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx, 3726 struct sysctl_oid *oid, struct sge_fl *fl) 3727 { 3728 struct sysctl_oid_list *children; 3729 3730 if (ctx == NULL || oid == NULL) 3731 return; 3732 3733 children = SYSCTL_CHILDREN(oid); 3734 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", 3735 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "freelist"); 3736 children = SYSCTL_CHILDREN(oid); 3737 3738 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, 3739 &fl->ba, "bus address of descriptor ring"); 3740 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3741 fl->sidx * EQ_ESIZE + sc->params.sge.spg_len, 3742 "desc ring size in bytes"); 3743 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 3744 &fl->cntxt_id, 0, "SGE context id of the freelist"); 3745 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "padding", CTLFLAG_RD, NULL, 3746 fl_pad ? 1 : 0, "padding enabled"); 3747 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "packing", CTLFLAG_RD, NULL, 3748 fl->flags & FL_BUF_PACKING ? 1 : 0, "packing enabled"); 3749 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &fl->cidx, 3750 0, "consumer index"); 3751 if (fl->flags & FL_BUF_PACKING) { 3752 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rx_offset", 3753 CTLFLAG_RD, &fl->rx_offset, 0, "packing rx offset"); 3754 } 3755 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &fl->pidx, 3756 0, "producer index"); 3757 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_allocated", 3758 CTLFLAG_RD, &fl->cl_allocated, "# of clusters allocated"); 3759 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_recycled", 3760 CTLFLAG_RD, &fl->cl_recycled, "# of clusters recycled"); 3761 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_fast_recycled", 3762 CTLFLAG_RD, &fl->cl_fast_recycled, "# of clusters recycled (fast)"); 3763 } 3764 3765 /* 3766 * Idempotent. 3767 */ 3768 static int 3769 alloc_fwq(struct adapter *sc) 3770 { 3771 int rc, intr_idx; 3772 struct sge_iq *fwq = &sc->sge.fwq; 3773 struct vi_info *vi = &sc->port[0]->vi[0]; 3774 3775 if (!(fwq->flags & IQ_SW_ALLOCATED)) { 3776 MPASS(!(fwq->flags & IQ_HW_ALLOCATED)); 3777 3778 if (sc->flags & IS_VF) 3779 intr_idx = 0; 3780 else 3781 intr_idx = sc->intr_count > 1 ? 1 : 0; 3782 init_iq(fwq, sc, 0, 0, FW_IQ_QSIZE, intr_idx, -1, IQ_OTHER); 3783 rc = alloc_iq_fl(vi, fwq, NULL, &sc->ctx, sc->fwq_oid); 3784 if (rc != 0) { 3785 CH_ERR(sc, "failed to allocate fwq: %d\n", rc); 3786 return (rc); 3787 } 3788 MPASS(fwq->flags & IQ_SW_ALLOCATED); 3789 } 3790 3791 if (!(fwq->flags & IQ_HW_ALLOCATED)) { 3792 MPASS(fwq->flags & IQ_SW_ALLOCATED); 3793 3794 rc = alloc_iq_fl_hwq(vi, fwq, NULL); 3795 if (rc != 0) { 3796 CH_ERR(sc, "failed to create hw fwq: %d\n", rc); 3797 return (rc); 3798 } 3799 MPASS(fwq->flags & IQ_HW_ALLOCATED); 3800 } 3801 3802 return (0); 3803 } 3804 3805 /* 3806 * Idempotent. 3807 */ 3808 static void 3809 free_fwq(struct adapter *sc) 3810 { 3811 struct sge_iq *fwq = &sc->sge.fwq; 3812 3813 if (fwq->flags & IQ_HW_ALLOCATED) { 3814 MPASS(fwq->flags & IQ_SW_ALLOCATED); 3815 free_iq_fl_hwq(sc, fwq, NULL); 3816 MPASS(!(fwq->flags & IQ_HW_ALLOCATED)); 3817 } 3818 3819 if (fwq->flags & IQ_SW_ALLOCATED) { 3820 MPASS(!(fwq->flags & IQ_HW_ALLOCATED)); 3821 free_iq_fl(sc, fwq, NULL); 3822 MPASS(!(fwq->flags & IQ_SW_ALLOCATED)); 3823 } 3824 } 3825 3826 /* 3827 * Idempotent. 3828 */ 3829 static int 3830 alloc_ctrlq(struct adapter *sc, int idx) 3831 { 3832 int rc; 3833 char name[16]; 3834 struct sysctl_oid *oid; 3835 struct sge_wrq *ctrlq = &sc->sge.ctrlq[idx]; 3836 3837 MPASS(idx < sc->params.nports); 3838 3839 if (!(ctrlq->eq.flags & EQ_SW_ALLOCATED)) { 3840 MPASS(!(ctrlq->eq.flags & EQ_HW_ALLOCATED)); 3841 3842 snprintf(name, sizeof(name), "%d", idx); 3843 oid = SYSCTL_ADD_NODE(&sc->ctx, SYSCTL_CHILDREN(sc->ctrlq_oid), 3844 OID_AUTO, name, CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 3845 "ctrl queue"); 3846 3847 snprintf(name, sizeof(name), "%s ctrlq%d", 3848 device_get_nameunit(sc->dev), idx); 3849 init_eq(sc, &ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE, idx, 3850 &sc->sge.fwq, name); 3851 rc = alloc_wrq(sc, NULL, ctrlq, &sc->ctx, oid); 3852 if (rc != 0) { 3853 CH_ERR(sc, "failed to allocate ctrlq%d: %d\n", idx, rc); 3854 sysctl_remove_oid(oid, 1, 1); 3855 return (rc); 3856 } 3857 MPASS(ctrlq->eq.flags & EQ_SW_ALLOCATED); 3858 } 3859 3860 if (!(ctrlq->eq.flags & EQ_HW_ALLOCATED)) { 3861 MPASS(ctrlq->eq.flags & EQ_SW_ALLOCATED); 3862 MPASS(ctrlq->nwr_pending == 0); 3863 MPASS(ctrlq->ndesc_needed == 0); 3864 3865 rc = alloc_eq_hwq(sc, NULL, &ctrlq->eq); 3866 if (rc != 0) { 3867 CH_ERR(sc, "failed to create hw ctrlq%d: %d\n", idx, rc); 3868 return (rc); 3869 } 3870 MPASS(ctrlq->eq.flags & EQ_HW_ALLOCATED); 3871 } 3872 3873 return (0); 3874 } 3875 3876 /* 3877 * Idempotent. 3878 */ 3879 static void 3880 free_ctrlq(struct adapter *sc, int idx) 3881 { 3882 struct sge_wrq *ctrlq = &sc->sge.ctrlq[idx]; 3883 3884 if (ctrlq->eq.flags & EQ_HW_ALLOCATED) { 3885 MPASS(ctrlq->eq.flags & EQ_SW_ALLOCATED); 3886 free_eq_hwq(sc, NULL, &ctrlq->eq); 3887 MPASS(!(ctrlq->eq.flags & EQ_HW_ALLOCATED)); 3888 } 3889 3890 if (ctrlq->eq.flags & EQ_SW_ALLOCATED) { 3891 MPASS(!(ctrlq->eq.flags & EQ_HW_ALLOCATED)); 3892 free_wrq(sc, ctrlq); 3893 MPASS(!(ctrlq->eq.flags & EQ_SW_ALLOCATED)); 3894 } 3895 } 3896 3897 int 3898 t4_sge_set_conm_context(struct adapter *sc, int cntxt_id, int cong_drop, 3899 int cong_map) 3900 { 3901 const int cng_ch_bits_log = sc->chip_params->cng_ch_bits_log; 3902 uint32_t param, val; 3903 uint16_t ch_map; 3904 int cong_mode, rc, i; 3905 3906 if (chip_id(sc) < CHELSIO_T5) 3907 return (ENOTSUP); 3908 3909 /* Convert the driver knob to the mode understood by the firmware. */ 3910 switch (cong_drop) { 3911 case -1: 3912 cong_mode = X_CONMCTXT_CNGTPMODE_DISABLE; 3913 break; 3914 case 0: 3915 cong_mode = X_CONMCTXT_CNGTPMODE_CHANNEL; 3916 break; 3917 case 1: 3918 cong_mode = X_CONMCTXT_CNGTPMODE_QUEUE; 3919 break; 3920 case 2: 3921 cong_mode = X_CONMCTXT_CNGTPMODE_BOTH; 3922 break; 3923 default: 3924 MPASS(0); 3925 CH_ERR(sc, "cong_drop = %d is invalid (ingress queue %d).\n", 3926 cong_drop, cntxt_id); 3927 return (EINVAL); 3928 } 3929 3930 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 3931 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) | 3932 V_FW_PARAMS_PARAM_YZ(cntxt_id); 3933 val = V_CONMCTXT_CNGTPMODE(cong_mode); 3934 if (cong_mode == X_CONMCTXT_CNGTPMODE_CHANNEL || 3935 cong_mode == X_CONMCTXT_CNGTPMODE_BOTH) { 3936 for (i = 0, ch_map = 0; i < 4; i++) { 3937 if (cong_map & (1 << i)) 3938 ch_map |= 1 << (i << cng_ch_bits_log); 3939 } 3940 val |= V_CONMCTXT_CNGCHMAP(ch_map); 3941 } 3942 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 3943 if (rc != 0) { 3944 CH_ERR(sc, "failed to set congestion manager context " 3945 "for ingress queue %d: %d\n", cntxt_id, rc); 3946 } 3947 3948 return (rc); 3949 } 3950 3951 /* 3952 * Idempotent. 3953 */ 3954 static int 3955 alloc_rxq(struct vi_info *vi, struct sge_rxq *rxq, int idx, int intr_idx, 3956 int maxp) 3957 { 3958 int rc; 3959 struct adapter *sc = vi->adapter; 3960 if_t ifp = vi->ifp; 3961 struct sysctl_oid *oid; 3962 char name[16]; 3963 3964 if (!(rxq->iq.flags & IQ_SW_ALLOCATED)) { 3965 MPASS(!(rxq->iq.flags & IQ_HW_ALLOCATED)); 3966 #if defined(INET) || defined(INET6) 3967 rc = tcp_lro_init_args(&rxq->lro, ifp, lro_entries, lro_mbufs); 3968 if (rc != 0) 3969 return (rc); 3970 MPASS(rxq->lro.ifp == ifp); /* also indicates LRO init'ed */ 3971 #endif 3972 rxq->ifp = ifp; 3973 3974 snprintf(name, sizeof(name), "%d", idx); 3975 oid = SYSCTL_ADD_NODE(&vi->ctx, SYSCTL_CHILDREN(vi->rxq_oid), 3976 OID_AUTO, name, CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 3977 "rx queue"); 3978 3979 init_iq(&rxq->iq, sc, vi->tmr_idx, vi->pktc_idx, vi->qsize_rxq, 3980 intr_idx, cong_drop, IQ_ETH); 3981 #if defined(INET) || defined(INET6) 3982 if (if_getcapenable(ifp) & IFCAP_LRO) 3983 rxq->iq.flags |= IQ_LRO_ENABLED; 3984 #endif 3985 if (if_getcapenable(ifp) & IFCAP_HWRXTSTMP) 3986 rxq->iq.flags |= IQ_RX_TIMESTAMP; 3987 snprintf(name, sizeof(name), "%s rxq%d-fl", 3988 device_get_nameunit(vi->dev), idx); 3989 init_fl(sc, &rxq->fl, vi->qsize_rxq / 8, maxp, name); 3990 rc = alloc_iq_fl(vi, &rxq->iq, &rxq->fl, &vi->ctx, oid); 3991 if (rc != 0) { 3992 CH_ERR(vi, "failed to allocate rxq%d: %d\n", idx, rc); 3993 sysctl_remove_oid(oid, 1, 1); 3994 #if defined(INET) || defined(INET6) 3995 tcp_lro_free(&rxq->lro); 3996 rxq->lro.ifp = NULL; 3997 #endif 3998 return (rc); 3999 } 4000 MPASS(rxq->iq.flags & IQ_SW_ALLOCATED); 4001 add_rxq_sysctls(&vi->ctx, oid, rxq); 4002 } 4003 4004 if (!(rxq->iq.flags & IQ_HW_ALLOCATED)) { 4005 MPASS(rxq->iq.flags & IQ_SW_ALLOCATED); 4006 rc = alloc_iq_fl_hwq(vi, &rxq->iq, &rxq->fl); 4007 if (rc != 0) { 4008 CH_ERR(vi, "failed to create hw rxq%d: %d\n", idx, rc); 4009 return (rc); 4010 } 4011 MPASS(rxq->iq.flags & IQ_HW_ALLOCATED); 4012 4013 if (idx == 0) 4014 sc->sge.iq_base = rxq->iq.abs_id - rxq->iq.cntxt_id; 4015 else 4016 KASSERT(rxq->iq.cntxt_id + sc->sge.iq_base == rxq->iq.abs_id, 4017 ("iq_base mismatch")); 4018 KASSERT(sc->sge.iq_base == 0 || sc->flags & IS_VF, 4019 ("PF with non-zero iq_base")); 4020 4021 /* 4022 * The freelist is just barely above the starvation threshold 4023 * right now, fill it up a bit more. 4024 */ 4025 FL_LOCK(&rxq->fl); 4026 refill_fl(sc, &rxq->fl, 128); 4027 FL_UNLOCK(&rxq->fl); 4028 } 4029 4030 return (0); 4031 } 4032 4033 /* 4034 * Idempotent. 4035 */ 4036 static void 4037 free_rxq(struct vi_info *vi, struct sge_rxq *rxq) 4038 { 4039 if (rxq->iq.flags & IQ_HW_ALLOCATED) { 4040 MPASS(rxq->iq.flags & IQ_SW_ALLOCATED); 4041 free_iq_fl_hwq(vi->adapter, &rxq->iq, &rxq->fl); 4042 MPASS(!(rxq->iq.flags & IQ_HW_ALLOCATED)); 4043 } 4044 4045 if (rxq->iq.flags & IQ_SW_ALLOCATED) { 4046 MPASS(!(rxq->iq.flags & IQ_HW_ALLOCATED)); 4047 #if defined(INET) || defined(INET6) 4048 tcp_lro_free(&rxq->lro); 4049 #endif 4050 free_iq_fl(vi->adapter, &rxq->iq, &rxq->fl); 4051 MPASS(!(rxq->iq.flags & IQ_SW_ALLOCATED)); 4052 bzero(rxq, sizeof(*rxq)); 4053 } 4054 } 4055 4056 static void 4057 add_rxq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid, 4058 struct sge_rxq *rxq) 4059 { 4060 struct sysctl_oid_list *children; 4061 4062 if (ctx == NULL || oid == NULL) 4063 return; 4064 4065 children = SYSCTL_CHILDREN(oid); 4066 #if defined(INET) || defined(INET6) 4067 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "lro_queued", CTLFLAG_RD, 4068 &rxq->lro.lro_queued, 0, NULL); 4069 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "lro_flushed", CTLFLAG_RD, 4070 &rxq->lro.lro_flushed, 0, NULL); 4071 #endif 4072 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "rxcsum", CTLFLAG_RD, 4073 &rxq->rxcsum, "# of times hardware assisted with checksum"); 4074 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "vlan_extraction", CTLFLAG_RD, 4075 &rxq->vlan_extraction, "# of times hardware extracted 802.1Q tag"); 4076 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "vxlan_rxcsum", CTLFLAG_RD, 4077 &rxq->vxlan_rxcsum, 4078 "# of times hardware assisted with inner checksum (VXLAN)"); 4079 } 4080 4081 #ifdef TCP_OFFLOAD 4082 /* 4083 * Idempotent. 4084 */ 4085 static int 4086 alloc_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq, int idx, 4087 int intr_idx, int maxp) 4088 { 4089 int rc; 4090 struct adapter *sc = vi->adapter; 4091 struct sysctl_oid *oid; 4092 char name[16]; 4093 4094 if (!(ofld_rxq->iq.flags & IQ_SW_ALLOCATED)) { 4095 MPASS(!(ofld_rxq->iq.flags & IQ_HW_ALLOCATED)); 4096 4097 snprintf(name, sizeof(name), "%d", idx); 4098 oid = SYSCTL_ADD_NODE(&vi->ctx, 4099 SYSCTL_CHILDREN(vi->ofld_rxq_oid), OID_AUTO, name, 4100 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "offload rx queue"); 4101 4102 init_iq(&ofld_rxq->iq, sc, vi->ofld_tmr_idx, vi->ofld_pktc_idx, 4103 vi->qsize_rxq, intr_idx, ofld_cong_drop, IQ_OFLD); 4104 snprintf(name, sizeof(name), "%s ofld_rxq%d-fl", 4105 device_get_nameunit(vi->dev), idx); 4106 init_fl(sc, &ofld_rxq->fl, vi->qsize_rxq / 8, maxp, name); 4107 rc = alloc_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl, &vi->ctx, 4108 oid); 4109 if (rc != 0) { 4110 CH_ERR(vi, "failed to allocate ofld_rxq%d: %d\n", idx, 4111 rc); 4112 sysctl_remove_oid(oid, 1, 1); 4113 return (rc); 4114 } 4115 MPASS(ofld_rxq->iq.flags & IQ_SW_ALLOCATED); 4116 ofld_rxq->rx_iscsi_ddp_setup_ok = counter_u64_alloc(M_WAITOK); 4117 ofld_rxq->rx_iscsi_ddp_setup_error = 4118 counter_u64_alloc(M_WAITOK); 4119 ofld_rxq->ddp_buffer_alloc = counter_u64_alloc(M_WAITOK); 4120 ofld_rxq->ddp_buffer_reuse = counter_u64_alloc(M_WAITOK); 4121 ofld_rxq->ddp_buffer_free = counter_u64_alloc(M_WAITOK); 4122 add_ofld_rxq_sysctls(&vi->ctx, oid, ofld_rxq); 4123 } 4124 4125 if (!(ofld_rxq->iq.flags & IQ_HW_ALLOCATED)) { 4126 MPASS(ofld_rxq->iq.flags & IQ_SW_ALLOCATED); 4127 rc = alloc_iq_fl_hwq(vi, &ofld_rxq->iq, &ofld_rxq->fl); 4128 if (rc != 0) { 4129 CH_ERR(vi, "failed to create hw ofld_rxq%d: %d\n", idx, 4130 rc); 4131 return (rc); 4132 } 4133 MPASS(ofld_rxq->iq.flags & IQ_HW_ALLOCATED); 4134 } 4135 return (rc); 4136 } 4137 4138 /* 4139 * Idempotent. 4140 */ 4141 static void 4142 free_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq) 4143 { 4144 if (ofld_rxq->iq.flags & IQ_HW_ALLOCATED) { 4145 MPASS(ofld_rxq->iq.flags & IQ_SW_ALLOCATED); 4146 free_iq_fl_hwq(vi->adapter, &ofld_rxq->iq, &ofld_rxq->fl); 4147 MPASS(!(ofld_rxq->iq.flags & IQ_HW_ALLOCATED)); 4148 } 4149 4150 if (ofld_rxq->iq.flags & IQ_SW_ALLOCATED) { 4151 MPASS(!(ofld_rxq->iq.flags & IQ_HW_ALLOCATED)); 4152 free_iq_fl(vi->adapter, &ofld_rxq->iq, &ofld_rxq->fl); 4153 MPASS(!(ofld_rxq->iq.flags & IQ_SW_ALLOCATED)); 4154 counter_u64_free(ofld_rxq->rx_iscsi_ddp_setup_ok); 4155 counter_u64_free(ofld_rxq->rx_iscsi_ddp_setup_error); 4156 counter_u64_free(ofld_rxq->ddp_buffer_alloc); 4157 counter_u64_free(ofld_rxq->ddp_buffer_reuse); 4158 counter_u64_free(ofld_rxq->ddp_buffer_free); 4159 bzero(ofld_rxq, sizeof(*ofld_rxq)); 4160 } 4161 } 4162 4163 static void 4164 add_ofld_rxq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid, 4165 struct sge_ofld_rxq *ofld_rxq) 4166 { 4167 struct sysctl_oid_list *children; 4168 4169 if (ctx == NULL || oid == NULL) 4170 return; 4171 4172 children = SYSCTL_CHILDREN(oid); 4173 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "rx_aio_ddp_jobs", 4174 CTLFLAG_RD, &ofld_rxq->rx_aio_ddp_jobs, 0, 4175 "# of aio_read(2) jobs completed via DDP"); 4176 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "rx_aio_ddp_octets", 4177 CTLFLAG_RD, &ofld_rxq->rx_aio_ddp_octets, 0, 4178 "# of octets placed directly for aio_read(2) jobs"); 4179 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 4180 "rx_toe_tls_records", CTLFLAG_RD, &ofld_rxq->rx_toe_tls_records, 4181 "# of TOE TLS records received"); 4182 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 4183 "rx_toe_tls_octets", CTLFLAG_RD, &ofld_rxq->rx_toe_tls_octets, 4184 "# of payload octets in received TOE TLS records"); 4185 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 4186 "rx_toe_ddp_octets", CTLFLAG_RD, &ofld_rxq->rx_toe_ddp_octets, 4187 "# of payload octets received via TCP DDP"); 4188 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, 4189 "ddp_buffer_alloc", CTLFLAG_RD, &ofld_rxq->ddp_buffer_alloc, 4190 "# of DDP RCV buffers allocated"); 4191 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, 4192 "ddp_buffer_reuse", CTLFLAG_RD, &ofld_rxq->ddp_buffer_reuse, 4193 "# of DDP RCV buffers reused"); 4194 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, 4195 "ddp_buffer_free", CTLFLAG_RD, &ofld_rxq->ddp_buffer_free, 4196 "# of DDP RCV buffers freed"); 4197 4198 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "iscsi", 4199 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TOE iSCSI statistics"); 4200 children = SYSCTL_CHILDREN(oid); 4201 4202 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "ddp_setup_ok", 4203 CTLFLAG_RD, &ofld_rxq->rx_iscsi_ddp_setup_ok, 4204 "# of times DDP buffer was setup successfully."); 4205 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "ddp_setup_error", 4206 CTLFLAG_RD, &ofld_rxq->rx_iscsi_ddp_setup_error, 4207 "# of times DDP buffer setup failed."); 4208 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "ddp_octets", 4209 CTLFLAG_RD, &ofld_rxq->rx_iscsi_ddp_octets, 0, 4210 "# of octets placed directly"); 4211 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "ddp_pdus", 4212 CTLFLAG_RD, &ofld_rxq->rx_iscsi_ddp_pdus, 0, 4213 "# of PDUs with data placed directly."); 4214 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "fl_octets", 4215 CTLFLAG_RD, &ofld_rxq->rx_iscsi_fl_octets, 0, 4216 "# of data octets delivered in freelist"); 4217 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "fl_pdus", 4218 CTLFLAG_RD, &ofld_rxq->rx_iscsi_fl_pdus, 0, 4219 "# of PDUs with data delivered in freelist"); 4220 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "padding_errors", 4221 CTLFLAG_RD, &ofld_rxq->rx_iscsi_padding_errors, 0, 4222 "# of PDUs with invalid padding"); 4223 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "header_digest_errors", 4224 CTLFLAG_RD, &ofld_rxq->rx_iscsi_header_digest_errors, 0, 4225 "# of PDUs with invalid header digests"); 4226 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "data_digest_errors", 4227 CTLFLAG_RD, &ofld_rxq->rx_iscsi_data_digest_errors, 0, 4228 "# of PDUs with invalid data digests"); 4229 } 4230 #endif 4231 4232 /* 4233 * Returns a reasonable automatic cidx flush threshold for a given queue size. 4234 */ 4235 static u_int 4236 qsize_to_fthresh(int qsize) 4237 { 4238 u_int fthresh; 4239 4240 fthresh = qsize == 0 ? 0 : order_base_2(qsize); 4241 if (fthresh > X_CIDXFLUSHTHRESH_128) 4242 fthresh = X_CIDXFLUSHTHRESH_128; 4243 4244 return (fthresh); 4245 } 4246 4247 static int 4248 ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq) 4249 { 4250 int rc, cntxt_id; 4251 struct fw_eq_ctrl_cmd c; 4252 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 4253 4254 bzero(&c, sizeof(c)); 4255 4256 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | F_FW_CMD_REQUEST | 4257 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_CTRL_CMD_PFN(sc->pf) | 4258 V_FW_EQ_CTRL_CMD_VFN(0)); 4259 c.alloc_to_len16 = htobe32(F_FW_EQ_CTRL_CMD_ALLOC | 4260 F_FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c)); 4261 c.cmpliqid_eqid = htonl(V_FW_EQ_CTRL_CMD_CMPLIQID(eq->iqid)); 4262 c.physeqid_pkd = htobe32(0); 4263 c.fetchszm_to_iqid = 4264 htobe32(V_FW_EQ_CTRL_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 4265 V_FW_EQ_CTRL_CMD_PCIECHN(eq->tx_chan) | 4266 F_FW_EQ_CTRL_CMD_FETCHRO | V_FW_EQ_CTRL_CMD_IQID(eq->iqid)); 4267 c.dcaen_to_eqsize = 4268 htobe32(V_FW_EQ_CTRL_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ? 4269 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) | 4270 V_FW_EQ_CTRL_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 4271 V_FW_EQ_CTRL_CMD_CIDXFTHRESH(qsize_to_fthresh(qsize)) | 4272 V_FW_EQ_CTRL_CMD_EQSIZE(qsize)); 4273 c.eqaddr = htobe64(eq->ba); 4274 4275 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 4276 if (rc != 0) { 4277 CH_ERR(sc, "failed to create hw ctrlq for tx_chan %d: %d\n", 4278 eq->tx_chan, rc); 4279 return (rc); 4280 } 4281 4282 eq->cntxt_id = G_FW_EQ_CTRL_CMD_EQID(be32toh(c.cmpliqid_eqid)); 4283 eq->abs_id = G_FW_EQ_CTRL_CMD_PHYSEQID(be32toh(c.physeqid_pkd)); 4284 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 4285 if (cntxt_id >= sc->sge.eqmap_sz) 4286 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 4287 cntxt_id, sc->sge.eqmap_sz - 1); 4288 sc->sge.eqmap[cntxt_id] = eq; 4289 4290 return (rc); 4291 } 4292 4293 static int 4294 eth_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 4295 { 4296 int rc, cntxt_id; 4297 struct fw_eq_eth_cmd c; 4298 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 4299 4300 bzero(&c, sizeof(c)); 4301 4302 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST | 4303 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) | 4304 V_FW_EQ_ETH_CMD_VFN(0)); 4305 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC | 4306 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c)); 4307 c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE | 4308 F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(vi->viid)); 4309 c.fetchszm_to_iqid = 4310 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) | 4311 V_FW_EQ_ETH_CMD_PCIECHN(eq->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO | 4312 V_FW_EQ_ETH_CMD_IQID(eq->iqid)); 4313 c.dcaen_to_eqsize = 4314 htobe32(V_FW_EQ_ETH_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ? 4315 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) | 4316 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 4317 V_FW_EQ_ETH_CMD_EQSIZE(qsize)); 4318 c.eqaddr = htobe64(eq->ba); 4319 4320 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 4321 if (rc != 0) { 4322 device_printf(vi->dev, 4323 "failed to create Ethernet egress queue: %d\n", rc); 4324 return (rc); 4325 } 4326 4327 eq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd)); 4328 eq->abs_id = G_FW_EQ_ETH_CMD_PHYSEQID(be32toh(c.physeqid_pkd)); 4329 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 4330 if (cntxt_id >= sc->sge.eqmap_sz) 4331 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 4332 cntxt_id, sc->sge.eqmap_sz - 1); 4333 sc->sge.eqmap[cntxt_id] = eq; 4334 4335 return (rc); 4336 } 4337 4338 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 4339 static int 4340 ofld_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 4341 { 4342 int rc, cntxt_id; 4343 struct fw_eq_ofld_cmd c; 4344 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 4345 4346 bzero(&c, sizeof(c)); 4347 4348 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | F_FW_CMD_REQUEST | 4349 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_OFLD_CMD_PFN(sc->pf) | 4350 V_FW_EQ_OFLD_CMD_VFN(0)); 4351 c.alloc_to_len16 = htonl(F_FW_EQ_OFLD_CMD_ALLOC | 4352 F_FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c)); 4353 c.fetchszm_to_iqid = 4354 htonl(V_FW_EQ_OFLD_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 4355 V_FW_EQ_OFLD_CMD_PCIECHN(eq->tx_chan) | 4356 F_FW_EQ_OFLD_CMD_FETCHRO | V_FW_EQ_OFLD_CMD_IQID(eq->iqid)); 4357 c.dcaen_to_eqsize = 4358 htobe32(V_FW_EQ_OFLD_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ? 4359 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) | 4360 V_FW_EQ_OFLD_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 4361 V_FW_EQ_OFLD_CMD_CIDXFTHRESH(qsize_to_fthresh(qsize)) | 4362 V_FW_EQ_OFLD_CMD_EQSIZE(qsize)); 4363 c.eqaddr = htobe64(eq->ba); 4364 4365 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 4366 if (rc != 0) { 4367 device_printf(vi->dev, 4368 "failed to create egress queue for TCP offload: %d\n", rc); 4369 return (rc); 4370 } 4371 4372 eq->cntxt_id = G_FW_EQ_OFLD_CMD_EQID(be32toh(c.eqid_pkd)); 4373 eq->abs_id = G_FW_EQ_OFLD_CMD_PHYSEQID(be32toh(c.physeqid_pkd)); 4374 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 4375 if (cntxt_id >= sc->sge.eqmap_sz) 4376 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 4377 cntxt_id, sc->sge.eqmap_sz - 1); 4378 sc->sge.eqmap[cntxt_id] = eq; 4379 4380 return (rc); 4381 } 4382 #endif 4383 4384 /* SW only */ 4385 static int 4386 alloc_eq(struct adapter *sc, struct sge_eq *eq, struct sysctl_ctx_list *ctx, 4387 struct sysctl_oid *oid) 4388 { 4389 int rc, qsize; 4390 size_t len; 4391 4392 MPASS(!(eq->flags & EQ_SW_ALLOCATED)); 4393 4394 qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 4395 len = qsize * EQ_ESIZE; 4396 rc = alloc_ring(sc, len, &eq->desc_tag, &eq->desc_map, &eq->ba, 4397 (void **)&eq->desc); 4398 if (rc) 4399 return (rc); 4400 if (ctx != NULL && oid != NULL) 4401 add_eq_sysctls(sc, ctx, oid, eq); 4402 eq->flags |= EQ_SW_ALLOCATED; 4403 4404 return (0); 4405 } 4406 4407 /* SW only */ 4408 static void 4409 free_eq(struct adapter *sc, struct sge_eq *eq) 4410 { 4411 MPASS(eq->flags & EQ_SW_ALLOCATED); 4412 if (eq->type == EQ_ETH) 4413 MPASS(eq->pidx == eq->cidx); 4414 4415 free_ring(sc, eq->desc_tag, eq->desc_map, eq->ba, eq->desc); 4416 mtx_destroy(&eq->eq_lock); 4417 bzero(eq, sizeof(*eq)); 4418 } 4419 4420 static void 4421 add_eq_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx, 4422 struct sysctl_oid *oid, struct sge_eq *eq) 4423 { 4424 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 4425 4426 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, &eq->ba, 4427 "bus address of descriptor ring"); 4428 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 4429 eq->sidx * EQ_ESIZE + sc->params.sge.spg_len, 4430 "desc ring size in bytes"); 4431 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "abs_id", CTLFLAG_RD, 4432 &eq->abs_id, 0, "absolute id of the queue"); 4433 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 4434 &eq->cntxt_id, 0, "SGE context id of the queue"); 4435 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &eq->cidx, 4436 0, "consumer index"); 4437 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &eq->pidx, 4438 0, "producer index"); 4439 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL, 4440 eq->sidx, "status page index"); 4441 } 4442 4443 static int 4444 alloc_eq_hwq(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 4445 { 4446 int rc; 4447 4448 MPASS(!(eq->flags & EQ_HW_ALLOCATED)); 4449 4450 eq->iqid = eq->iq->cntxt_id; 4451 eq->pidx = eq->cidx = eq->dbidx = 0; 4452 /* Note that equeqidx is not used with sge_wrq (OFLD/CTRL) queues. */ 4453 eq->equeqidx = 0; 4454 eq->doorbells = sc->doorbells; 4455 bzero(eq->desc, eq->sidx * EQ_ESIZE + sc->params.sge.spg_len); 4456 4457 switch (eq->type) { 4458 case EQ_CTRL: 4459 rc = ctrl_eq_alloc(sc, eq); 4460 break; 4461 4462 case EQ_ETH: 4463 rc = eth_eq_alloc(sc, vi, eq); 4464 break; 4465 4466 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 4467 case EQ_OFLD: 4468 rc = ofld_eq_alloc(sc, vi, eq); 4469 break; 4470 #endif 4471 4472 default: 4473 panic("%s: invalid eq type %d.", __func__, eq->type); 4474 } 4475 if (rc != 0) { 4476 CH_ERR(sc, "failed to allocate egress queue(%d): %d\n", 4477 eq->type, rc); 4478 return (rc); 4479 } 4480 4481 if (isset(&eq->doorbells, DOORBELL_UDB) || 4482 isset(&eq->doorbells, DOORBELL_UDBWC) || 4483 isset(&eq->doorbells, DOORBELL_WCWR)) { 4484 uint32_t s_qpp = sc->params.sge.eq_s_qpp; 4485 uint32_t mask = (1 << s_qpp) - 1; 4486 volatile uint8_t *udb; 4487 4488 udb = sc->udbs_base + UDBS_DB_OFFSET; 4489 udb += (eq->cntxt_id >> s_qpp) << PAGE_SHIFT; /* pg offset */ 4490 eq->udb_qid = eq->cntxt_id & mask; /* id in page */ 4491 if (eq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE) 4492 clrbit(&eq->doorbells, DOORBELL_WCWR); 4493 else { 4494 udb += eq->udb_qid << UDBS_SEG_SHIFT; /* seg offset */ 4495 eq->udb_qid = 0; 4496 } 4497 eq->udb = (volatile void *)udb; 4498 } 4499 4500 eq->flags |= EQ_HW_ALLOCATED; 4501 return (0); 4502 } 4503 4504 static int 4505 free_eq_hwq(struct adapter *sc, struct vi_info *vi __unused, struct sge_eq *eq) 4506 { 4507 int rc; 4508 4509 MPASS(eq->flags & EQ_HW_ALLOCATED); 4510 4511 switch (eq->type) { 4512 case EQ_CTRL: 4513 rc = -t4_ctrl_eq_free(sc, sc->mbox, sc->pf, 0, eq->cntxt_id); 4514 break; 4515 case EQ_ETH: 4516 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0, eq->cntxt_id); 4517 break; 4518 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 4519 case EQ_OFLD: 4520 rc = -t4_ofld_eq_free(sc, sc->mbox, sc->pf, 0, eq->cntxt_id); 4521 break; 4522 #endif 4523 default: 4524 panic("%s: invalid eq type %d.", __func__, eq->type); 4525 } 4526 if (rc != 0) { 4527 CH_ERR(sc, "failed to free eq (type %d): %d\n", eq->type, rc); 4528 return (rc); 4529 } 4530 eq->flags &= ~EQ_HW_ALLOCATED; 4531 4532 return (0); 4533 } 4534 4535 static int 4536 alloc_wrq(struct adapter *sc, struct vi_info *vi, struct sge_wrq *wrq, 4537 struct sysctl_ctx_list *ctx, struct sysctl_oid *oid) 4538 { 4539 struct sge_eq *eq = &wrq->eq; 4540 int rc; 4541 4542 MPASS(!(eq->flags & EQ_SW_ALLOCATED)); 4543 4544 rc = alloc_eq(sc, eq, ctx, oid); 4545 if (rc) 4546 return (rc); 4547 MPASS(eq->flags & EQ_SW_ALLOCATED); 4548 /* Can't fail after this. */ 4549 4550 wrq->adapter = sc; 4551 TASK_INIT(&wrq->wrq_tx_task, 0, wrq_tx_drain, wrq); 4552 TAILQ_INIT(&wrq->incomplete_wrs); 4553 STAILQ_INIT(&wrq->wr_list); 4554 wrq->nwr_pending = 0; 4555 wrq->ndesc_needed = 0; 4556 add_wrq_sysctls(ctx, oid, wrq); 4557 4558 return (0); 4559 } 4560 4561 static void 4562 free_wrq(struct adapter *sc, struct sge_wrq *wrq) 4563 { 4564 free_eq(sc, &wrq->eq); 4565 MPASS(wrq->nwr_pending == 0); 4566 MPASS(wrq->ndesc_needed == 0); 4567 MPASS(TAILQ_EMPTY(&wrq->incomplete_wrs)); 4568 MPASS(STAILQ_EMPTY(&wrq->wr_list)); 4569 bzero(wrq, sizeof(*wrq)); 4570 } 4571 4572 static void 4573 add_wrq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid, 4574 struct sge_wrq *wrq) 4575 { 4576 struct sysctl_oid_list *children; 4577 4578 if (ctx == NULL || oid == NULL) 4579 return; 4580 4581 children = SYSCTL_CHILDREN(oid); 4582 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_direct", CTLFLAG_RD, 4583 &wrq->tx_wrs_direct, "# of work requests (direct)"); 4584 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_copied", CTLFLAG_RD, 4585 &wrq->tx_wrs_copied, "# of work requests (copied)"); 4586 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_sspace", CTLFLAG_RD, 4587 &wrq->tx_wrs_ss, "# of work requests (copied from scratch space)"); 4588 } 4589 4590 /* 4591 * Idempotent. 4592 */ 4593 static int 4594 alloc_txq(struct vi_info *vi, struct sge_txq *txq, int idx) 4595 { 4596 int rc, iqidx; 4597 struct port_info *pi = vi->pi; 4598 struct adapter *sc = vi->adapter; 4599 struct sge_eq *eq = &txq->eq; 4600 struct txpkts *txp; 4601 char name[16]; 4602 struct sysctl_oid *oid; 4603 4604 if (!(eq->flags & EQ_SW_ALLOCATED)) { 4605 MPASS(!(eq->flags & EQ_HW_ALLOCATED)); 4606 4607 snprintf(name, sizeof(name), "%d", idx); 4608 oid = SYSCTL_ADD_NODE(&vi->ctx, SYSCTL_CHILDREN(vi->txq_oid), 4609 OID_AUTO, name, CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 4610 "tx queue"); 4611 4612 iqidx = vi->first_rxq + (idx % vi->nrxq); 4613 snprintf(name, sizeof(name), "%s txq%d", 4614 device_get_nameunit(vi->dev), idx); 4615 init_eq(sc, &txq->eq, EQ_ETH, vi->qsize_txq, pi->port_id, 4616 &sc->sge.rxq[iqidx].iq, name); 4617 4618 rc = mp_ring_alloc(&txq->r, eq->sidx, txq, eth_tx, 4619 can_resume_eth_tx, M_CXGBE, &eq->eq_lock, M_WAITOK); 4620 if (rc != 0) { 4621 CH_ERR(vi, "failed to allocate mp_ring for txq%d: %d\n", 4622 idx, rc); 4623 failed: 4624 sysctl_remove_oid(oid, 1, 1); 4625 return (rc); 4626 } 4627 4628 rc = alloc_eq(sc, eq, &vi->ctx, oid); 4629 if (rc) { 4630 CH_ERR(vi, "failed to allocate txq%d: %d\n", idx, rc); 4631 mp_ring_free(txq->r); 4632 goto failed; 4633 } 4634 MPASS(eq->flags & EQ_SW_ALLOCATED); 4635 /* Can't fail after this point. */ 4636 4637 TASK_INIT(&txq->tx_reclaim_task, 0, tx_reclaim, eq); 4638 txq->ifp = vi->ifp; 4639 txq->gl = sglist_alloc(TX_SGL_SEGS, M_WAITOK); 4640 txq->sdesc = malloc(eq->sidx * sizeof(struct tx_sdesc), M_CXGBE, 4641 M_ZERO | M_WAITOK); 4642 4643 add_txq_sysctls(vi, &vi->ctx, oid, txq); 4644 } 4645 4646 if (!(eq->flags & EQ_HW_ALLOCATED)) { 4647 MPASS(eq->flags & EQ_SW_ALLOCATED); 4648 rc = alloc_eq_hwq(sc, vi, eq); 4649 if (rc != 0) { 4650 CH_ERR(vi, "failed to create hw txq%d: %d\n", idx, rc); 4651 return (rc); 4652 } 4653 MPASS(eq->flags & EQ_HW_ALLOCATED); 4654 /* Can't fail after this point. */ 4655 4656 if (idx == 0) 4657 sc->sge.eq_base = eq->abs_id - eq->cntxt_id; 4658 else 4659 KASSERT(eq->cntxt_id + sc->sge.eq_base == eq->abs_id, 4660 ("eq_base mismatch")); 4661 KASSERT(sc->sge.eq_base == 0 || sc->flags & IS_VF, 4662 ("PF with non-zero eq_base")); 4663 4664 txp = &txq->txp; 4665 MPASS(nitems(txp->mb) >= sc->params.max_pkts_per_eth_tx_pkts_wr); 4666 txq->txp.max_npkt = min(nitems(txp->mb), 4667 sc->params.max_pkts_per_eth_tx_pkts_wr); 4668 if (vi->flags & TX_USES_VM_WR && !(sc->flags & IS_VF)) 4669 txq->txp.max_npkt--; 4670 4671 if (vi->flags & TX_USES_VM_WR) 4672 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) | 4673 V_TXPKT_INTF(pi->tx_chan)); 4674 else 4675 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) | 4676 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(sc->pf) | 4677 V_TXPKT_VF(vi->vin) | V_TXPKT_VF_VLD(vi->vfvld)); 4678 4679 txq->tc_idx = -1; 4680 } 4681 4682 return (0); 4683 } 4684 4685 /* 4686 * Idempotent. 4687 */ 4688 static void 4689 free_txq(struct vi_info *vi, struct sge_txq *txq) 4690 { 4691 struct adapter *sc = vi->adapter; 4692 struct sge_eq *eq = &txq->eq; 4693 4694 if (eq->flags & EQ_HW_ALLOCATED) { 4695 MPASS(eq->flags & EQ_SW_ALLOCATED); 4696 free_eq_hwq(sc, NULL, eq); 4697 MPASS(!(eq->flags & EQ_HW_ALLOCATED)); 4698 } 4699 4700 if (eq->flags & EQ_SW_ALLOCATED) { 4701 MPASS(!(eq->flags & EQ_HW_ALLOCATED)); 4702 sglist_free(txq->gl); 4703 free(txq->sdesc, M_CXGBE); 4704 mp_ring_free(txq->r); 4705 free_eq(sc, eq); 4706 MPASS(!(eq->flags & EQ_SW_ALLOCATED)); 4707 bzero(txq, sizeof(*txq)); 4708 } 4709 } 4710 4711 static void 4712 add_txq_sysctls(struct vi_info *vi, struct sysctl_ctx_list *ctx, 4713 struct sysctl_oid *oid, struct sge_txq *txq) 4714 { 4715 struct adapter *sc; 4716 struct sysctl_oid_list *children; 4717 4718 if (ctx == NULL || oid == NULL) 4719 return; 4720 4721 sc = vi->adapter; 4722 children = SYSCTL_CHILDREN(oid); 4723 4724 mp_ring_sysctls(txq->r, ctx, children); 4725 4726 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tc", 4727 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, txq - sc->sge.txq, 4728 sysctl_tc, "I", "traffic class (-1 means none)"); 4729 4730 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txcsum", CTLFLAG_RD, 4731 &txq->txcsum, "# of times hardware assisted with checksum"); 4732 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "vlan_insertion", CTLFLAG_RD, 4733 &txq->vlan_insertion, "# of times hardware inserted 802.1Q tag"); 4734 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tso_wrs", CTLFLAG_RD, 4735 &txq->tso_wrs, "# of TSO work requests"); 4736 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "imm_wrs", CTLFLAG_RD, 4737 &txq->imm_wrs, "# of work requests with immediate data"); 4738 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "sgl_wrs", CTLFLAG_RD, 4739 &txq->sgl_wrs, "# of work requests with direct SGL"); 4740 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkt_wrs", CTLFLAG_RD, 4741 &txq->txpkt_wrs, "# of txpkt work requests (one pkt/WR)"); 4742 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkts0_wrs", CTLFLAG_RD, 4743 &txq->txpkts0_wrs, "# of txpkts (type 0) work requests"); 4744 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkts1_wrs", CTLFLAG_RD, 4745 &txq->txpkts1_wrs, "# of txpkts (type 1) work requests"); 4746 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkts0_pkts", CTLFLAG_RD, 4747 &txq->txpkts0_pkts, 4748 "# of frames tx'd using type0 txpkts work requests"); 4749 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkts1_pkts", CTLFLAG_RD, 4750 &txq->txpkts1_pkts, 4751 "# of frames tx'd using type1 txpkts work requests"); 4752 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkts_flush", CTLFLAG_RD, 4753 &txq->txpkts_flush, 4754 "# of times txpkts had to be flushed out by an egress-update"); 4755 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "raw_wrs", CTLFLAG_RD, 4756 &txq->raw_wrs, "# of raw work requests (non-packets)"); 4757 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "vxlan_tso_wrs", CTLFLAG_RD, 4758 &txq->vxlan_tso_wrs, "# of VXLAN TSO work requests"); 4759 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "vxlan_txcsum", CTLFLAG_RD, 4760 &txq->vxlan_txcsum, 4761 "# of times hardware assisted with inner checksums (VXLAN)"); 4762 4763 #ifdef KERN_TLS 4764 if (is_ktls(sc)) { 4765 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_records", 4766 CTLFLAG_RD, &txq->kern_tls_records, 4767 "# of NIC TLS records transmitted"); 4768 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_short", 4769 CTLFLAG_RD, &txq->kern_tls_short, 4770 "# of short NIC TLS records transmitted"); 4771 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_partial", 4772 CTLFLAG_RD, &txq->kern_tls_partial, 4773 "# of partial NIC TLS records transmitted"); 4774 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_full", 4775 CTLFLAG_RD, &txq->kern_tls_full, 4776 "# of full NIC TLS records transmitted"); 4777 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_octets", 4778 CTLFLAG_RD, &txq->kern_tls_octets, 4779 "# of payload octets in transmitted NIC TLS records"); 4780 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_waste", 4781 CTLFLAG_RD, &txq->kern_tls_waste, 4782 "# of octets DMAd but not transmitted in NIC TLS records"); 4783 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_options", 4784 CTLFLAG_RD, &txq->kern_tls_options, 4785 "# of NIC TLS options-only packets transmitted"); 4786 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_header", 4787 CTLFLAG_RD, &txq->kern_tls_header, 4788 "# of NIC TLS header-only packets transmitted"); 4789 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_fin", 4790 CTLFLAG_RD, &txq->kern_tls_fin, 4791 "# of NIC TLS FIN-only packets transmitted"); 4792 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_fin_short", 4793 CTLFLAG_RD, &txq->kern_tls_fin_short, 4794 "# of NIC TLS padded FIN packets on short TLS records"); 4795 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_cbc", 4796 CTLFLAG_RD, &txq->kern_tls_cbc, 4797 "# of NIC TLS sessions using AES-CBC"); 4798 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_gcm", 4799 CTLFLAG_RD, &txq->kern_tls_gcm, 4800 "# of NIC TLS sessions using AES-GCM"); 4801 } 4802 #endif 4803 } 4804 4805 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 4806 /* 4807 * Idempotent. 4808 */ 4809 static int 4810 alloc_ofld_txq(struct vi_info *vi, struct sge_ofld_txq *ofld_txq, int idx) 4811 { 4812 struct sysctl_oid *oid; 4813 struct port_info *pi = vi->pi; 4814 struct adapter *sc = vi->adapter; 4815 struct sge_eq *eq = &ofld_txq->wrq.eq; 4816 int rc, iqidx; 4817 char name[16]; 4818 4819 MPASS(idx >= 0); 4820 MPASS(idx < vi->nofldtxq); 4821 4822 if (!(eq->flags & EQ_SW_ALLOCATED)) { 4823 snprintf(name, sizeof(name), "%d", idx); 4824 oid = SYSCTL_ADD_NODE(&vi->ctx, 4825 SYSCTL_CHILDREN(vi->ofld_txq_oid), OID_AUTO, name, 4826 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "offload tx queue"); 4827 4828 snprintf(name, sizeof(name), "%s ofld_txq%d", 4829 device_get_nameunit(vi->dev), idx); 4830 if (vi->nofldrxq > 0) { 4831 iqidx = vi->first_ofld_rxq + (idx % vi->nofldrxq); 4832 init_eq(sc, eq, EQ_OFLD, vi->qsize_txq, pi->port_id, 4833 &sc->sge.ofld_rxq[iqidx].iq, name); 4834 } else { 4835 iqidx = vi->first_rxq + (idx % vi->nrxq); 4836 init_eq(sc, eq, EQ_OFLD, vi->qsize_txq, pi->port_id, 4837 &sc->sge.rxq[iqidx].iq, name); 4838 } 4839 4840 rc = alloc_wrq(sc, vi, &ofld_txq->wrq, &vi->ctx, oid); 4841 if (rc != 0) { 4842 CH_ERR(vi, "failed to allocate ofld_txq%d: %d\n", idx, 4843 rc); 4844 sysctl_remove_oid(oid, 1, 1); 4845 return (rc); 4846 } 4847 MPASS(eq->flags & EQ_SW_ALLOCATED); 4848 /* Can't fail after this point. */ 4849 4850 ofld_txq->tx_iscsi_pdus = counter_u64_alloc(M_WAITOK); 4851 ofld_txq->tx_iscsi_octets = counter_u64_alloc(M_WAITOK); 4852 ofld_txq->tx_iscsi_iso_wrs = counter_u64_alloc(M_WAITOK); 4853 ofld_txq->tx_aio_jobs = counter_u64_alloc(M_WAITOK); 4854 ofld_txq->tx_aio_octets = counter_u64_alloc(M_WAITOK); 4855 ofld_txq->tx_toe_tls_records = counter_u64_alloc(M_WAITOK); 4856 ofld_txq->tx_toe_tls_octets = counter_u64_alloc(M_WAITOK); 4857 add_ofld_txq_sysctls(&vi->ctx, oid, ofld_txq); 4858 } 4859 4860 if (!(eq->flags & EQ_HW_ALLOCATED)) { 4861 MPASS(eq->flags & EQ_SW_ALLOCATED); 4862 MPASS(ofld_txq->wrq.nwr_pending == 0); 4863 MPASS(ofld_txq->wrq.ndesc_needed == 0); 4864 rc = alloc_eq_hwq(sc, vi, eq); 4865 if (rc != 0) { 4866 CH_ERR(vi, "failed to create hw ofld_txq%d: %d\n", idx, 4867 rc); 4868 return (rc); 4869 } 4870 MPASS(eq->flags & EQ_HW_ALLOCATED); 4871 } 4872 4873 return (0); 4874 } 4875 4876 /* 4877 * Idempotent. 4878 */ 4879 static void 4880 free_ofld_txq(struct vi_info *vi, struct sge_ofld_txq *ofld_txq) 4881 { 4882 struct adapter *sc = vi->adapter; 4883 struct sge_eq *eq = &ofld_txq->wrq.eq; 4884 4885 if (eq->flags & EQ_HW_ALLOCATED) { 4886 MPASS(eq->flags & EQ_SW_ALLOCATED); 4887 free_eq_hwq(sc, NULL, eq); 4888 MPASS(!(eq->flags & EQ_HW_ALLOCATED)); 4889 } 4890 4891 if (eq->flags & EQ_SW_ALLOCATED) { 4892 MPASS(!(eq->flags & EQ_HW_ALLOCATED)); 4893 counter_u64_free(ofld_txq->tx_iscsi_pdus); 4894 counter_u64_free(ofld_txq->tx_iscsi_octets); 4895 counter_u64_free(ofld_txq->tx_iscsi_iso_wrs); 4896 counter_u64_free(ofld_txq->tx_aio_jobs); 4897 counter_u64_free(ofld_txq->tx_aio_octets); 4898 counter_u64_free(ofld_txq->tx_toe_tls_records); 4899 counter_u64_free(ofld_txq->tx_toe_tls_octets); 4900 free_wrq(sc, &ofld_txq->wrq); 4901 MPASS(!(eq->flags & EQ_SW_ALLOCATED)); 4902 bzero(ofld_txq, sizeof(*ofld_txq)); 4903 } 4904 } 4905 4906 static void 4907 add_ofld_txq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid, 4908 struct sge_ofld_txq *ofld_txq) 4909 { 4910 struct sysctl_oid_list *children; 4911 4912 if (ctx == NULL || oid == NULL) 4913 return; 4914 4915 children = SYSCTL_CHILDREN(oid); 4916 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_iscsi_pdus", 4917 CTLFLAG_RD, &ofld_txq->tx_iscsi_pdus, 4918 "# of iSCSI PDUs transmitted"); 4919 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_iscsi_octets", 4920 CTLFLAG_RD, &ofld_txq->tx_iscsi_octets, 4921 "# of payload octets in transmitted iSCSI PDUs"); 4922 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_iscsi_iso_wrs", 4923 CTLFLAG_RD, &ofld_txq->tx_iscsi_iso_wrs, 4924 "# of iSCSI segmentation offload work requests"); 4925 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_aio_jobs", 4926 CTLFLAG_RD, &ofld_txq->tx_aio_jobs, 4927 "# of zero-copy aio_write(2) jobs transmitted"); 4928 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_aio_octets", 4929 CTLFLAG_RD, &ofld_txq->tx_aio_octets, 4930 "# of payload octets in transmitted zero-copy aio_write(2) jobs"); 4931 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_toe_tls_records", 4932 CTLFLAG_RD, &ofld_txq->tx_toe_tls_records, 4933 "# of TOE TLS records transmitted"); 4934 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_toe_tls_octets", 4935 CTLFLAG_RD, &ofld_txq->tx_toe_tls_octets, 4936 "# of payload octets in transmitted TOE TLS records"); 4937 } 4938 #endif 4939 4940 static void 4941 oneseg_dma_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error) 4942 { 4943 bus_addr_t *ba = arg; 4944 4945 KASSERT(nseg == 1, 4946 ("%s meant for single segment mappings only.", __func__)); 4947 4948 *ba = error ? 0 : segs->ds_addr; 4949 } 4950 4951 static inline void 4952 ring_fl_db(struct adapter *sc, struct sge_fl *fl) 4953 { 4954 uint32_t n, v; 4955 4956 n = IDXDIFF(fl->pidx >> 3, fl->dbidx, fl->sidx); 4957 MPASS(n > 0); 4958 4959 wmb(); 4960 v = fl->dbval | V_PIDX(n); 4961 if (fl->udb) 4962 *fl->udb = htole32(v); 4963 else 4964 t4_write_reg(sc, sc->sge_kdoorbell_reg, v); 4965 IDXINCR(fl->dbidx, n, fl->sidx); 4966 } 4967 4968 /* 4969 * Fills up the freelist by allocating up to 'n' buffers. Buffers that are 4970 * recycled do not count towards this allocation budget. 4971 * 4972 * Returns non-zero to indicate that this freelist should be added to the list 4973 * of starving freelists. 4974 */ 4975 static int 4976 refill_fl(struct adapter *sc, struct sge_fl *fl, int n) 4977 { 4978 __be64 *d; 4979 struct fl_sdesc *sd; 4980 uintptr_t pa; 4981 caddr_t cl; 4982 struct rx_buf_info *rxb; 4983 struct cluster_metadata *clm; 4984 uint16_t max_pidx, zidx = fl->zidx; 4985 uint16_t hw_cidx = fl->hw_cidx; /* stable snapshot */ 4986 4987 FL_LOCK_ASSERT_OWNED(fl); 4988 4989 /* 4990 * We always stop at the beginning of the hardware descriptor that's just 4991 * before the one with the hw cidx. This is to avoid hw pidx = hw cidx, 4992 * which would mean an empty freelist to the chip. 4993 */ 4994 max_pidx = __predict_false(hw_cidx == 0) ? fl->sidx - 1 : hw_cidx - 1; 4995 if (fl->pidx == max_pidx * 8) 4996 return (0); 4997 4998 d = &fl->desc[fl->pidx]; 4999 sd = &fl->sdesc[fl->pidx]; 5000 rxb = &sc->sge.rx_buf_info[zidx]; 5001 5002 while (n > 0) { 5003 5004 if (sd->cl != NULL) { 5005 5006 if (sd->nmbuf == 0) { 5007 /* 5008 * Fast recycle without involving any atomics on 5009 * the cluster's metadata (if the cluster has 5010 * metadata). This happens when all frames 5011 * received in the cluster were small enough to 5012 * fit within a single mbuf each. 5013 */ 5014 fl->cl_fast_recycled++; 5015 goto recycled; 5016 } 5017 5018 /* 5019 * Cluster is guaranteed to have metadata. Clusters 5020 * without metadata always take the fast recycle path 5021 * when they're recycled. 5022 */ 5023 clm = cl_metadata(sd); 5024 MPASS(clm != NULL); 5025 5026 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) { 5027 fl->cl_recycled++; 5028 counter_u64_add(extfree_rels, 1); 5029 goto recycled; 5030 } 5031 sd->cl = NULL; /* gave up my reference */ 5032 } 5033 MPASS(sd->cl == NULL); 5034 cl = uma_zalloc(rxb->zone, M_NOWAIT); 5035 if (__predict_false(cl == NULL)) { 5036 if (zidx != fl->safe_zidx) { 5037 zidx = fl->safe_zidx; 5038 rxb = &sc->sge.rx_buf_info[zidx]; 5039 cl = uma_zalloc(rxb->zone, M_NOWAIT); 5040 } 5041 if (cl == NULL) 5042 break; 5043 } 5044 fl->cl_allocated++; 5045 n--; 5046 5047 pa = pmap_kextract((vm_offset_t)cl); 5048 sd->cl = cl; 5049 sd->zidx = zidx; 5050 5051 if (fl->flags & FL_BUF_PACKING) { 5052 *d = htobe64(pa | rxb->hwidx2); 5053 sd->moff = rxb->size2; 5054 } else { 5055 *d = htobe64(pa | rxb->hwidx1); 5056 sd->moff = 0; 5057 } 5058 recycled: 5059 sd->nmbuf = 0; 5060 d++; 5061 sd++; 5062 if (__predict_false((++fl->pidx & 7) == 0)) { 5063 uint16_t pidx = fl->pidx >> 3; 5064 5065 if (__predict_false(pidx == fl->sidx)) { 5066 fl->pidx = 0; 5067 pidx = 0; 5068 sd = fl->sdesc; 5069 d = fl->desc; 5070 } 5071 if (n < 8 || pidx == max_pidx) 5072 break; 5073 5074 if (IDXDIFF(pidx, fl->dbidx, fl->sidx) >= 4) 5075 ring_fl_db(sc, fl); 5076 } 5077 } 5078 5079 if ((fl->pidx >> 3) != fl->dbidx) 5080 ring_fl_db(sc, fl); 5081 5082 return (FL_RUNNING_LOW(fl) && !(fl->flags & FL_STARVING)); 5083 } 5084 5085 /* 5086 * Attempt to refill all starving freelists. 5087 */ 5088 static void 5089 refill_sfl(void *arg) 5090 { 5091 struct adapter *sc = arg; 5092 struct sge_fl *fl, *fl_temp; 5093 5094 mtx_assert(&sc->sfl_lock, MA_OWNED); 5095 TAILQ_FOREACH_SAFE(fl, &sc->sfl, link, fl_temp) { 5096 FL_LOCK(fl); 5097 refill_fl(sc, fl, 64); 5098 if (FL_NOT_RUNNING_LOW(fl) || fl->flags & FL_DOOMED) { 5099 TAILQ_REMOVE(&sc->sfl, fl, link); 5100 fl->flags &= ~FL_STARVING; 5101 } 5102 FL_UNLOCK(fl); 5103 } 5104 5105 if (!TAILQ_EMPTY(&sc->sfl)) 5106 callout_schedule(&sc->sfl_callout, hz / 5); 5107 } 5108 5109 /* 5110 * Release the driver's reference on all buffers in the given freelist. Buffers 5111 * with kernel references cannot be freed and will prevent the driver from being 5112 * unloaded safely. 5113 */ 5114 void 5115 free_fl_buffers(struct adapter *sc, struct sge_fl *fl) 5116 { 5117 struct fl_sdesc *sd; 5118 struct cluster_metadata *clm; 5119 int i; 5120 5121 sd = fl->sdesc; 5122 for (i = 0; i < fl->sidx * 8; i++, sd++) { 5123 if (sd->cl == NULL) 5124 continue; 5125 5126 if (sd->nmbuf == 0) 5127 uma_zfree(sc->sge.rx_buf_info[sd->zidx].zone, sd->cl); 5128 else if (fl->flags & FL_BUF_PACKING) { 5129 clm = cl_metadata(sd); 5130 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) { 5131 uma_zfree(sc->sge.rx_buf_info[sd->zidx].zone, 5132 sd->cl); 5133 counter_u64_add(extfree_rels, 1); 5134 } 5135 } 5136 sd->cl = NULL; 5137 } 5138 5139 if (fl->flags & FL_BUF_RESUME) { 5140 m_freem(fl->m0); 5141 fl->flags &= ~FL_BUF_RESUME; 5142 } 5143 } 5144 5145 static inline void 5146 get_pkt_gl(struct mbuf *m, struct sglist *gl) 5147 { 5148 int rc; 5149 5150 M_ASSERTPKTHDR(m); 5151 5152 sglist_reset(gl); 5153 rc = sglist_append_mbuf(gl, m); 5154 if (__predict_false(rc != 0)) { 5155 panic("%s: mbuf %p (%d segs) was vetted earlier but now fails " 5156 "with %d.", __func__, m, mbuf_nsegs(m), rc); 5157 } 5158 5159 KASSERT(gl->sg_nseg == mbuf_nsegs(m), 5160 ("%s: nsegs changed for mbuf %p from %d to %d", __func__, m, 5161 mbuf_nsegs(m), gl->sg_nseg)); 5162 #if 0 /* vm_wr not readily available here. */ 5163 KASSERT(gl->sg_nseg > 0 && gl->sg_nseg <= max_nsegs_allowed(m, vm_wr), 5164 ("%s: %d segments, should have been 1 <= nsegs <= %d", __func__, 5165 gl->sg_nseg, max_nsegs_allowed(m, vm_wr))); 5166 #endif 5167 } 5168 5169 /* 5170 * len16 for a txpkt WR with a GL. Includes the firmware work request header. 5171 */ 5172 static inline u_int 5173 txpkt_len16(u_int nsegs, const u_int extra) 5174 { 5175 u_int n; 5176 5177 MPASS(nsegs > 0); 5178 5179 nsegs--; /* first segment is part of ulptx_sgl */ 5180 n = extra + sizeof(struct fw_eth_tx_pkt_wr) + 5181 sizeof(struct cpl_tx_pkt_core) + 5182 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 5183 5184 return (howmany(n, 16)); 5185 } 5186 5187 /* 5188 * len16 for a txpkt_vm WR with a GL. Includes the firmware work 5189 * request header. 5190 */ 5191 static inline u_int 5192 txpkt_vm_len16(u_int nsegs, const u_int extra) 5193 { 5194 u_int n; 5195 5196 MPASS(nsegs > 0); 5197 5198 nsegs--; /* first segment is part of ulptx_sgl */ 5199 n = extra + sizeof(struct fw_eth_tx_pkt_vm_wr) + 5200 sizeof(struct cpl_tx_pkt_core) + 5201 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 5202 5203 return (howmany(n, 16)); 5204 } 5205 5206 static inline void 5207 calculate_mbuf_len16(struct mbuf *m, bool vm_wr) 5208 { 5209 const int lso = sizeof(struct cpl_tx_pkt_lso_core); 5210 const int tnl_lso = sizeof(struct cpl_tx_tnl_lso); 5211 5212 if (vm_wr) { 5213 if (needs_tso(m)) 5214 set_mbuf_len16(m, txpkt_vm_len16(mbuf_nsegs(m), lso)); 5215 else 5216 set_mbuf_len16(m, txpkt_vm_len16(mbuf_nsegs(m), 0)); 5217 return; 5218 } 5219 5220 if (needs_tso(m)) { 5221 if (needs_vxlan_tso(m)) 5222 set_mbuf_len16(m, txpkt_len16(mbuf_nsegs(m), tnl_lso)); 5223 else 5224 set_mbuf_len16(m, txpkt_len16(mbuf_nsegs(m), lso)); 5225 } else 5226 set_mbuf_len16(m, txpkt_len16(mbuf_nsegs(m), 0)); 5227 } 5228 5229 /* 5230 * len16 for a txpkts type 0 WR with a GL. Does not include the firmware work 5231 * request header. 5232 */ 5233 static inline u_int 5234 txpkts0_len16(u_int nsegs) 5235 { 5236 u_int n; 5237 5238 MPASS(nsegs > 0); 5239 5240 nsegs--; /* first segment is part of ulptx_sgl */ 5241 n = sizeof(struct ulp_txpkt) + sizeof(struct ulptx_idata) + 5242 sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl) + 5243 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 5244 5245 return (howmany(n, 16)); 5246 } 5247 5248 /* 5249 * len16 for a txpkts type 1 WR with a GL. Does not include the firmware work 5250 * request header. 5251 */ 5252 static inline u_int 5253 txpkts1_len16(void) 5254 { 5255 u_int n; 5256 5257 n = sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl); 5258 5259 return (howmany(n, 16)); 5260 } 5261 5262 static inline u_int 5263 imm_payload(u_int ndesc) 5264 { 5265 u_int n; 5266 5267 n = ndesc * EQ_ESIZE - sizeof(struct fw_eth_tx_pkt_wr) - 5268 sizeof(struct cpl_tx_pkt_core); 5269 5270 return (n); 5271 } 5272 5273 static inline uint64_t 5274 csum_to_ctrl(struct adapter *sc, struct mbuf *m) 5275 { 5276 uint64_t ctrl; 5277 int csum_type, l2hlen, l3hlen; 5278 int x, y; 5279 static const int csum_types[3][2] = { 5280 {TX_CSUM_TCPIP, TX_CSUM_TCPIP6}, 5281 {TX_CSUM_UDPIP, TX_CSUM_UDPIP6}, 5282 {TX_CSUM_IP, 0} 5283 }; 5284 5285 M_ASSERTPKTHDR(m); 5286 5287 if (!needs_hwcsum(m)) 5288 return (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS); 5289 5290 MPASS(m->m_pkthdr.l2hlen >= ETHER_HDR_LEN); 5291 MPASS(m->m_pkthdr.l3hlen >= sizeof(struct ip)); 5292 5293 if (needs_vxlan_csum(m)) { 5294 MPASS(m->m_pkthdr.l4hlen > 0); 5295 MPASS(m->m_pkthdr.l5hlen > 0); 5296 MPASS(m->m_pkthdr.inner_l2hlen >= ETHER_HDR_LEN); 5297 MPASS(m->m_pkthdr.inner_l3hlen >= sizeof(struct ip)); 5298 5299 l2hlen = m->m_pkthdr.l2hlen + m->m_pkthdr.l3hlen + 5300 m->m_pkthdr.l4hlen + m->m_pkthdr.l5hlen + 5301 m->m_pkthdr.inner_l2hlen - ETHER_HDR_LEN; 5302 l3hlen = m->m_pkthdr.inner_l3hlen; 5303 } else { 5304 l2hlen = m->m_pkthdr.l2hlen - ETHER_HDR_LEN; 5305 l3hlen = m->m_pkthdr.l3hlen; 5306 } 5307 5308 ctrl = 0; 5309 if (!needs_l3_csum(m)) 5310 ctrl |= F_TXPKT_IPCSUM_DIS; 5311 5312 if (m->m_pkthdr.csum_flags & (CSUM_IP_TCP | CSUM_INNER_IP_TCP | 5313 CSUM_IP6_TCP | CSUM_INNER_IP6_TCP)) 5314 x = 0; /* TCP */ 5315 else if (m->m_pkthdr.csum_flags & (CSUM_IP_UDP | CSUM_INNER_IP_UDP | 5316 CSUM_IP6_UDP | CSUM_INNER_IP6_UDP)) 5317 x = 1; /* UDP */ 5318 else 5319 x = 2; 5320 5321 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_IP_TCP | CSUM_IP_UDP | 5322 CSUM_INNER_IP | CSUM_INNER_IP_TCP | CSUM_INNER_IP_UDP)) 5323 y = 0; /* IPv4 */ 5324 else { 5325 MPASS(m->m_pkthdr.csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | 5326 CSUM_INNER_IP6_TCP | CSUM_INNER_IP6_UDP)); 5327 y = 1; /* IPv6 */ 5328 } 5329 /* 5330 * needs_hwcsum returned true earlier so there must be some kind of 5331 * checksum to calculate. 5332 */ 5333 csum_type = csum_types[x][y]; 5334 MPASS(csum_type != 0); 5335 if (csum_type == TX_CSUM_IP) 5336 ctrl |= F_TXPKT_L4CSUM_DIS; 5337 ctrl |= V_TXPKT_CSUM_TYPE(csum_type) | V_TXPKT_IPHDR_LEN(l3hlen); 5338 if (chip_id(sc) <= CHELSIO_T5) 5339 ctrl |= V_TXPKT_ETHHDR_LEN(l2hlen); 5340 else 5341 ctrl |= V_T6_TXPKT_ETHHDR_LEN(l2hlen); 5342 5343 return (ctrl); 5344 } 5345 5346 static inline void * 5347 write_lso_cpl(void *cpl, struct mbuf *m0) 5348 { 5349 struct cpl_tx_pkt_lso_core *lso; 5350 uint32_t ctrl; 5351 5352 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 5353 m0->m_pkthdr.l4hlen > 0, 5354 ("%s: mbuf %p needs TSO but missing header lengths", 5355 __func__, m0)); 5356 5357 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | 5358 F_LSO_FIRST_SLICE | F_LSO_LAST_SLICE | 5359 V_LSO_ETHHDR_LEN((m0->m_pkthdr.l2hlen - ETHER_HDR_LEN) >> 2) | 5360 V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) | 5361 V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2); 5362 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 5363 ctrl |= F_LSO_IPV6; 5364 5365 lso = cpl; 5366 lso->lso_ctrl = htobe32(ctrl); 5367 lso->ipid_ofst = htobe16(0); 5368 lso->mss = htobe16(m0->m_pkthdr.tso_segsz); 5369 lso->seqno_offset = htobe32(0); 5370 lso->len = htobe32(m0->m_pkthdr.len); 5371 5372 return (lso + 1); 5373 } 5374 5375 static void * 5376 write_tnl_lso_cpl(void *cpl, struct mbuf *m0) 5377 { 5378 struct cpl_tx_tnl_lso *tnl_lso = cpl; 5379 uint32_t ctrl; 5380 5381 KASSERT(m0->m_pkthdr.inner_l2hlen > 0 && 5382 m0->m_pkthdr.inner_l3hlen > 0 && m0->m_pkthdr.inner_l4hlen > 0 && 5383 m0->m_pkthdr.inner_l5hlen > 0, 5384 ("%s: mbuf %p needs VXLAN_TSO but missing inner header lengths", 5385 __func__, m0)); 5386 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 5387 m0->m_pkthdr.l4hlen > 0 && m0->m_pkthdr.l5hlen > 0, 5388 ("%s: mbuf %p needs VXLAN_TSO but missing outer header lengths", 5389 __func__, m0)); 5390 5391 /* Outer headers. */ 5392 ctrl = V_CPL_TX_TNL_LSO_OPCODE(CPL_TX_TNL_LSO) | 5393 F_CPL_TX_TNL_LSO_FIRST | F_CPL_TX_TNL_LSO_LAST | 5394 V_CPL_TX_TNL_LSO_ETHHDRLENOUT( 5395 (m0->m_pkthdr.l2hlen - ETHER_HDR_LEN) >> 2) | 5396 V_CPL_TX_TNL_LSO_IPHDRLENOUT(m0->m_pkthdr.l3hlen >> 2) | 5397 F_CPL_TX_TNL_LSO_IPLENSETOUT; 5398 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 5399 ctrl |= F_CPL_TX_TNL_LSO_IPV6OUT; 5400 else { 5401 ctrl |= F_CPL_TX_TNL_LSO_IPHDRCHKOUT | 5402 F_CPL_TX_TNL_LSO_IPIDINCOUT; 5403 } 5404 tnl_lso->op_to_IpIdSplitOut = htobe32(ctrl); 5405 tnl_lso->IpIdOffsetOut = 0; 5406 tnl_lso->UdpLenSetOut_to_TnlHdrLen = 5407 htobe16(F_CPL_TX_TNL_LSO_UDPCHKCLROUT | 5408 F_CPL_TX_TNL_LSO_UDPLENSETOUT | 5409 V_CPL_TX_TNL_LSO_TNLHDRLEN(m0->m_pkthdr.l2hlen + 5410 m0->m_pkthdr.l3hlen + m0->m_pkthdr.l4hlen + 5411 m0->m_pkthdr.l5hlen) | 5412 V_CPL_TX_TNL_LSO_TNLTYPE(TX_TNL_TYPE_VXLAN)); 5413 tnl_lso->r1 = 0; 5414 5415 /* Inner headers. */ 5416 ctrl = V_CPL_TX_TNL_LSO_ETHHDRLEN( 5417 (m0->m_pkthdr.inner_l2hlen - ETHER_HDR_LEN) >> 2) | 5418 V_CPL_TX_TNL_LSO_IPHDRLEN(m0->m_pkthdr.inner_l3hlen >> 2) | 5419 V_CPL_TX_TNL_LSO_TCPHDRLEN(m0->m_pkthdr.inner_l4hlen >> 2); 5420 if (m0->m_pkthdr.inner_l3hlen == sizeof(struct ip6_hdr)) 5421 ctrl |= F_CPL_TX_TNL_LSO_IPV6; 5422 tnl_lso->Flow_to_TcpHdrLen = htobe32(ctrl); 5423 tnl_lso->IpIdOffset = 0; 5424 tnl_lso->IpIdSplit_to_Mss = 5425 htobe16(V_CPL_TX_TNL_LSO_MSS(m0->m_pkthdr.tso_segsz)); 5426 tnl_lso->TCPSeqOffset = 0; 5427 tnl_lso->EthLenOffset_Size = 5428 htobe32(V_CPL_TX_TNL_LSO_SIZE(m0->m_pkthdr.len)); 5429 5430 return (tnl_lso + 1); 5431 } 5432 5433 #define VM_TX_L2HDR_LEN 16 /* ethmacdst to vlantci */ 5434 5435 /* 5436 * Write a VM txpkt WR for this packet to the hardware descriptors, update the 5437 * software descriptor, and advance the pidx. It is guaranteed that enough 5438 * descriptors are available. 5439 * 5440 * The return value is the # of hardware descriptors used. 5441 */ 5442 static u_int 5443 write_txpkt_vm_wr(struct adapter *sc, struct sge_txq *txq, struct mbuf *m0) 5444 { 5445 struct sge_eq *eq; 5446 struct fw_eth_tx_pkt_vm_wr *wr; 5447 struct tx_sdesc *txsd; 5448 struct cpl_tx_pkt_core *cpl; 5449 uint32_t ctrl; /* used in many unrelated places */ 5450 uint64_t ctrl1; 5451 int len16, ndesc, pktlen; 5452 caddr_t dst; 5453 5454 TXQ_LOCK_ASSERT_OWNED(txq); 5455 M_ASSERTPKTHDR(m0); 5456 5457 len16 = mbuf_len16(m0); 5458 pktlen = m0->m_pkthdr.len; 5459 ctrl = sizeof(struct cpl_tx_pkt_core); 5460 if (needs_tso(m0)) 5461 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 5462 ndesc = tx_len16_to_desc(len16); 5463 5464 /* Firmware work request header */ 5465 eq = &txq->eq; 5466 wr = (void *)&eq->desc[eq->pidx]; 5467 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_VM_WR) | 5468 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl)); 5469 5470 ctrl = V_FW_WR_LEN16(len16); 5471 wr->equiq_to_len16 = htobe32(ctrl); 5472 wr->r3[0] = 0; 5473 wr->r3[1] = 0; 5474 5475 /* 5476 * Copy over ethmacdst, ethmacsrc, ethtype, and vlantci. 5477 * vlantci is ignored unless the ethtype is 0x8100, so it's 5478 * simpler to always copy it rather than making it 5479 * conditional. Also, it seems that we do not have to set 5480 * vlantci or fake the ethtype when doing VLAN tag insertion. 5481 */ 5482 m_copydata(m0, 0, VM_TX_L2HDR_LEN, wr->ethmacdst); 5483 5484 if (needs_tso(m0)) { 5485 cpl = write_lso_cpl(wr + 1, m0); 5486 txq->tso_wrs++; 5487 } else 5488 cpl = (void *)(wr + 1); 5489 5490 /* Checksum offload */ 5491 ctrl1 = csum_to_ctrl(sc, m0); 5492 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS)) 5493 txq->txcsum++; /* some hardware assistance provided */ 5494 5495 /* VLAN tag insertion */ 5496 if (needs_vlan_insertion(m0)) { 5497 ctrl1 |= F_TXPKT_VLAN_VLD | 5498 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 5499 txq->vlan_insertion++; 5500 } else if (sc->vlan_id) 5501 ctrl1 |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(sc->vlan_id); 5502 5503 /* CPL header */ 5504 cpl->ctrl0 = txq->cpl_ctrl0; 5505 cpl->pack = 0; 5506 cpl->len = htobe16(pktlen); 5507 cpl->ctrl1 = htobe64(ctrl1); 5508 5509 /* SGL */ 5510 dst = (void *)(cpl + 1); 5511 5512 /* 5513 * A packet using TSO will use up an entire descriptor for the 5514 * firmware work request header, LSO CPL, and TX_PKT_XT CPL. 5515 * If this descriptor is the last descriptor in the ring, wrap 5516 * around to the front of the ring explicitly for the start of 5517 * the sgl. 5518 */ 5519 if (dst == (void *)&eq->desc[eq->sidx]) { 5520 dst = (void *)&eq->desc[0]; 5521 write_gl_to_txd(txq, m0, &dst, 0); 5522 } else 5523 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx); 5524 txq->sgl_wrs++; 5525 txq->txpkt_wrs++; 5526 5527 txsd = &txq->sdesc[eq->pidx]; 5528 txsd->m = m0; 5529 txsd->desc_used = ndesc; 5530 5531 return (ndesc); 5532 } 5533 5534 /* 5535 * Write a raw WR to the hardware descriptors, update the software 5536 * descriptor, and advance the pidx. It is guaranteed that enough 5537 * descriptors are available. 5538 * 5539 * The return value is the # of hardware descriptors used. 5540 */ 5541 static u_int 5542 write_raw_wr(struct sge_txq *txq, void *wr, struct mbuf *m0, u_int available) 5543 { 5544 struct sge_eq *eq = &txq->eq; 5545 struct tx_sdesc *txsd; 5546 struct mbuf *m; 5547 caddr_t dst; 5548 int len16, ndesc; 5549 5550 len16 = mbuf_len16(m0); 5551 ndesc = tx_len16_to_desc(len16); 5552 MPASS(ndesc <= available); 5553 5554 dst = wr; 5555 for (m = m0; m != NULL; m = m->m_next) 5556 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len); 5557 5558 txq->raw_wrs++; 5559 5560 txsd = &txq->sdesc[eq->pidx]; 5561 txsd->m = m0; 5562 txsd->desc_used = ndesc; 5563 5564 return (ndesc); 5565 } 5566 5567 /* 5568 * Write a txpkt WR for this packet to the hardware descriptors, update the 5569 * software descriptor, and advance the pidx. It is guaranteed that enough 5570 * descriptors are available. 5571 * 5572 * The return value is the # of hardware descriptors used. 5573 */ 5574 static u_int 5575 write_txpkt_wr(struct adapter *sc, struct sge_txq *txq, struct mbuf *m0, 5576 u_int available) 5577 { 5578 struct sge_eq *eq; 5579 struct fw_eth_tx_pkt_wr *wr; 5580 struct tx_sdesc *txsd; 5581 struct cpl_tx_pkt_core *cpl; 5582 uint32_t ctrl; /* used in many unrelated places */ 5583 uint64_t ctrl1; 5584 int len16, ndesc, pktlen, nsegs; 5585 caddr_t dst; 5586 5587 TXQ_LOCK_ASSERT_OWNED(txq); 5588 M_ASSERTPKTHDR(m0); 5589 5590 len16 = mbuf_len16(m0); 5591 nsegs = mbuf_nsegs(m0); 5592 pktlen = m0->m_pkthdr.len; 5593 ctrl = sizeof(struct cpl_tx_pkt_core); 5594 if (needs_tso(m0)) { 5595 if (needs_vxlan_tso(m0)) 5596 ctrl += sizeof(struct cpl_tx_tnl_lso); 5597 else 5598 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 5599 } else if (!(mbuf_cflags(m0) & MC_NOMAP) && pktlen <= imm_payload(2) && 5600 available >= 2) { 5601 /* Immediate data. Recalculate len16 and set nsegs to 0. */ 5602 ctrl += pktlen; 5603 len16 = howmany(sizeof(struct fw_eth_tx_pkt_wr) + 5604 sizeof(struct cpl_tx_pkt_core) + pktlen, 16); 5605 nsegs = 0; 5606 } 5607 ndesc = tx_len16_to_desc(len16); 5608 MPASS(ndesc <= available); 5609 5610 /* Firmware work request header */ 5611 eq = &txq->eq; 5612 wr = (void *)&eq->desc[eq->pidx]; 5613 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_WR) | 5614 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl)); 5615 5616 ctrl = V_FW_WR_LEN16(len16); 5617 wr->equiq_to_len16 = htobe32(ctrl); 5618 wr->r3 = 0; 5619 5620 if (needs_tso(m0)) { 5621 if (needs_vxlan_tso(m0)) { 5622 cpl = write_tnl_lso_cpl(wr + 1, m0); 5623 txq->vxlan_tso_wrs++; 5624 } else { 5625 cpl = write_lso_cpl(wr + 1, m0); 5626 txq->tso_wrs++; 5627 } 5628 } else 5629 cpl = (void *)(wr + 1); 5630 5631 /* Checksum offload */ 5632 ctrl1 = csum_to_ctrl(sc, m0); 5633 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS)) { 5634 /* some hardware assistance provided */ 5635 if (needs_vxlan_csum(m0)) 5636 txq->vxlan_txcsum++; 5637 else 5638 txq->txcsum++; 5639 } 5640 5641 /* VLAN tag insertion */ 5642 if (needs_vlan_insertion(m0)) { 5643 ctrl1 |= F_TXPKT_VLAN_VLD | 5644 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 5645 txq->vlan_insertion++; 5646 } 5647 5648 /* CPL header */ 5649 cpl->ctrl0 = txq->cpl_ctrl0; 5650 cpl->pack = 0; 5651 cpl->len = htobe16(pktlen); 5652 cpl->ctrl1 = htobe64(ctrl1); 5653 5654 /* SGL */ 5655 dst = (void *)(cpl + 1); 5656 if (__predict_false((uintptr_t)dst == (uintptr_t)&eq->desc[eq->sidx])) 5657 dst = (caddr_t)&eq->desc[0]; 5658 if (nsegs > 0) { 5659 5660 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx); 5661 txq->sgl_wrs++; 5662 } else { 5663 struct mbuf *m; 5664 5665 for (m = m0; m != NULL; m = m->m_next) { 5666 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len); 5667 #ifdef INVARIANTS 5668 pktlen -= m->m_len; 5669 #endif 5670 } 5671 #ifdef INVARIANTS 5672 KASSERT(pktlen == 0, ("%s: %d bytes left.", __func__, pktlen)); 5673 #endif 5674 txq->imm_wrs++; 5675 } 5676 5677 txq->txpkt_wrs++; 5678 5679 txsd = &txq->sdesc[eq->pidx]; 5680 txsd->m = m0; 5681 txsd->desc_used = ndesc; 5682 5683 return (ndesc); 5684 } 5685 5686 static inline bool 5687 cmp_l2hdr(struct txpkts *txp, struct mbuf *m) 5688 { 5689 int len; 5690 5691 MPASS(txp->npkt > 0); 5692 MPASS(m->m_len >= VM_TX_L2HDR_LEN); 5693 5694 if (txp->ethtype == be16toh(ETHERTYPE_VLAN)) 5695 len = VM_TX_L2HDR_LEN; 5696 else 5697 len = sizeof(struct ether_header); 5698 5699 return (memcmp(m->m_data, &txp->ethmacdst[0], len) != 0); 5700 } 5701 5702 static inline void 5703 save_l2hdr(struct txpkts *txp, struct mbuf *m) 5704 { 5705 MPASS(m->m_len >= VM_TX_L2HDR_LEN); 5706 5707 memcpy(&txp->ethmacdst[0], mtod(m, const void *), VM_TX_L2HDR_LEN); 5708 } 5709 5710 static int 5711 add_to_txpkts_vf(struct adapter *sc, struct sge_txq *txq, struct mbuf *m, 5712 int avail, bool *send) 5713 { 5714 struct txpkts *txp = &txq->txp; 5715 5716 /* Cannot have TSO and coalesce at the same time. */ 5717 if (cannot_use_txpkts(m)) { 5718 cannot_coalesce: 5719 *send = txp->npkt > 0; 5720 return (EINVAL); 5721 } 5722 5723 /* VF allows coalescing of type 1 (1 GL) only */ 5724 if (mbuf_nsegs(m) > 1) 5725 goto cannot_coalesce; 5726 5727 *send = false; 5728 if (txp->npkt > 0) { 5729 MPASS(tx_len16_to_desc(txp->len16) <= avail); 5730 MPASS(txp->npkt < txp->max_npkt); 5731 MPASS(txp->wr_type == 1); /* VF supports type 1 only */ 5732 5733 if (tx_len16_to_desc(txp->len16 + txpkts1_len16()) > avail) { 5734 retry_after_send: 5735 *send = true; 5736 return (EAGAIN); 5737 } 5738 if (m->m_pkthdr.len + txp->plen > 65535) 5739 goto retry_after_send; 5740 if (cmp_l2hdr(txp, m)) 5741 goto retry_after_send; 5742 5743 txp->len16 += txpkts1_len16(); 5744 txp->plen += m->m_pkthdr.len; 5745 txp->mb[txp->npkt++] = m; 5746 if (txp->npkt == txp->max_npkt) 5747 *send = true; 5748 } else { 5749 txp->len16 = howmany(sizeof(struct fw_eth_tx_pkts_vm_wr), 16) + 5750 txpkts1_len16(); 5751 if (tx_len16_to_desc(txp->len16) > avail) 5752 goto cannot_coalesce; 5753 txp->npkt = 1; 5754 txp->wr_type = 1; 5755 txp->plen = m->m_pkthdr.len; 5756 txp->mb[0] = m; 5757 save_l2hdr(txp, m); 5758 } 5759 return (0); 5760 } 5761 5762 static int 5763 add_to_txpkts_pf(struct adapter *sc, struct sge_txq *txq, struct mbuf *m, 5764 int avail, bool *send) 5765 { 5766 struct txpkts *txp = &txq->txp; 5767 int nsegs; 5768 5769 MPASS(!(sc->flags & IS_VF)); 5770 5771 /* Cannot have TSO and coalesce at the same time. */ 5772 if (cannot_use_txpkts(m)) { 5773 cannot_coalesce: 5774 *send = txp->npkt > 0; 5775 return (EINVAL); 5776 } 5777 5778 *send = false; 5779 nsegs = mbuf_nsegs(m); 5780 if (txp->npkt == 0) { 5781 if (m->m_pkthdr.len > 65535) 5782 goto cannot_coalesce; 5783 if (nsegs > 1) { 5784 txp->wr_type = 0; 5785 txp->len16 = 5786 howmany(sizeof(struct fw_eth_tx_pkts_wr), 16) + 5787 txpkts0_len16(nsegs); 5788 } else { 5789 txp->wr_type = 1; 5790 txp->len16 = 5791 howmany(sizeof(struct fw_eth_tx_pkts_wr), 16) + 5792 txpkts1_len16(); 5793 } 5794 if (tx_len16_to_desc(txp->len16) > avail) 5795 goto cannot_coalesce; 5796 txp->npkt = 1; 5797 txp->plen = m->m_pkthdr.len; 5798 txp->mb[0] = m; 5799 } else { 5800 MPASS(tx_len16_to_desc(txp->len16) <= avail); 5801 MPASS(txp->npkt < txp->max_npkt); 5802 5803 if (m->m_pkthdr.len + txp->plen > 65535) { 5804 retry_after_send: 5805 *send = true; 5806 return (EAGAIN); 5807 } 5808 5809 MPASS(txp->wr_type == 0 || txp->wr_type == 1); 5810 if (txp->wr_type == 0) { 5811 if (tx_len16_to_desc(txp->len16 + 5812 txpkts0_len16(nsegs)) > min(avail, SGE_MAX_WR_NDESC)) 5813 goto retry_after_send; 5814 txp->len16 += txpkts0_len16(nsegs); 5815 } else { 5816 if (nsegs != 1) 5817 goto retry_after_send; 5818 if (tx_len16_to_desc(txp->len16 + txpkts1_len16()) > 5819 avail) 5820 goto retry_after_send; 5821 txp->len16 += txpkts1_len16(); 5822 } 5823 5824 txp->plen += m->m_pkthdr.len; 5825 txp->mb[txp->npkt++] = m; 5826 if (txp->npkt == txp->max_npkt) 5827 *send = true; 5828 } 5829 return (0); 5830 } 5831 5832 /* 5833 * Write a txpkts WR for the packets in txp to the hardware descriptors, update 5834 * the software descriptor, and advance the pidx. It is guaranteed that enough 5835 * descriptors are available. 5836 * 5837 * The return value is the # of hardware descriptors used. 5838 */ 5839 static u_int 5840 write_txpkts_wr(struct adapter *sc, struct sge_txq *txq) 5841 { 5842 const struct txpkts *txp = &txq->txp; 5843 struct sge_eq *eq = &txq->eq; 5844 struct fw_eth_tx_pkts_wr *wr; 5845 struct tx_sdesc *txsd; 5846 struct cpl_tx_pkt_core *cpl; 5847 uint64_t ctrl1; 5848 int ndesc, i, checkwrap; 5849 struct mbuf *m, *last; 5850 void *flitp; 5851 5852 TXQ_LOCK_ASSERT_OWNED(txq); 5853 MPASS(txp->npkt > 0); 5854 MPASS(txp->len16 <= howmany(SGE_MAX_WR_LEN, 16)); 5855 5856 wr = (void *)&eq->desc[eq->pidx]; 5857 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR)); 5858 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(txp->len16)); 5859 wr->plen = htobe16(txp->plen); 5860 wr->npkt = txp->npkt; 5861 wr->r3 = 0; 5862 wr->type = txp->wr_type; 5863 flitp = wr + 1; 5864 5865 /* 5866 * At this point we are 16B into a hardware descriptor. If checkwrap is 5867 * set then we know the WR is going to wrap around somewhere. We'll 5868 * check for that at appropriate points. 5869 */ 5870 ndesc = tx_len16_to_desc(txp->len16); 5871 last = NULL; 5872 checkwrap = eq->sidx - ndesc < eq->pidx; 5873 for (i = 0; i < txp->npkt; i++) { 5874 m = txp->mb[i]; 5875 if (txp->wr_type == 0) { 5876 struct ulp_txpkt *ulpmc; 5877 struct ulptx_idata *ulpsc; 5878 5879 /* ULP master command */ 5880 ulpmc = flitp; 5881 ulpmc->cmd_dest = htobe32(V_ULPTX_CMD(ULP_TX_PKT) | 5882 V_ULP_TXPKT_DEST(0) | V_ULP_TXPKT_FID(eq->iqid)); 5883 ulpmc->len = htobe32(txpkts0_len16(mbuf_nsegs(m))); 5884 5885 /* ULP subcommand */ 5886 ulpsc = (void *)(ulpmc + 1); 5887 ulpsc->cmd_more = htobe32(V_ULPTX_CMD(ULP_TX_SC_IMM) | 5888 F_ULP_TX_SC_MORE); 5889 ulpsc->len = htobe32(sizeof(struct cpl_tx_pkt_core)); 5890 5891 cpl = (void *)(ulpsc + 1); 5892 if (checkwrap && 5893 (uintptr_t)cpl == (uintptr_t)&eq->desc[eq->sidx]) 5894 cpl = (void *)&eq->desc[0]; 5895 } else { 5896 cpl = flitp; 5897 } 5898 5899 /* Checksum offload */ 5900 ctrl1 = csum_to_ctrl(sc, m); 5901 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS)) { 5902 /* some hardware assistance provided */ 5903 if (needs_vxlan_csum(m)) 5904 txq->vxlan_txcsum++; 5905 else 5906 txq->txcsum++; 5907 } 5908 5909 /* VLAN tag insertion */ 5910 if (needs_vlan_insertion(m)) { 5911 ctrl1 |= F_TXPKT_VLAN_VLD | 5912 V_TXPKT_VLAN(m->m_pkthdr.ether_vtag); 5913 txq->vlan_insertion++; 5914 } 5915 5916 /* CPL header */ 5917 cpl->ctrl0 = txq->cpl_ctrl0; 5918 cpl->pack = 0; 5919 cpl->len = htobe16(m->m_pkthdr.len); 5920 cpl->ctrl1 = htobe64(ctrl1); 5921 5922 flitp = cpl + 1; 5923 if (checkwrap && 5924 (uintptr_t)flitp == (uintptr_t)&eq->desc[eq->sidx]) 5925 flitp = (void *)&eq->desc[0]; 5926 5927 write_gl_to_txd(txq, m, (caddr_t *)(&flitp), checkwrap); 5928 5929 if (last != NULL) 5930 last->m_nextpkt = m; 5931 last = m; 5932 } 5933 5934 txq->sgl_wrs++; 5935 if (txp->wr_type == 0) { 5936 txq->txpkts0_pkts += txp->npkt; 5937 txq->txpkts0_wrs++; 5938 } else { 5939 txq->txpkts1_pkts += txp->npkt; 5940 txq->txpkts1_wrs++; 5941 } 5942 5943 txsd = &txq->sdesc[eq->pidx]; 5944 txsd->m = txp->mb[0]; 5945 txsd->desc_used = ndesc; 5946 5947 return (ndesc); 5948 } 5949 5950 static u_int 5951 write_txpkts_vm_wr(struct adapter *sc, struct sge_txq *txq) 5952 { 5953 const struct txpkts *txp = &txq->txp; 5954 struct sge_eq *eq = &txq->eq; 5955 struct fw_eth_tx_pkts_vm_wr *wr; 5956 struct tx_sdesc *txsd; 5957 struct cpl_tx_pkt_core *cpl; 5958 uint64_t ctrl1; 5959 int ndesc, i; 5960 struct mbuf *m, *last; 5961 void *flitp; 5962 5963 TXQ_LOCK_ASSERT_OWNED(txq); 5964 MPASS(txp->npkt > 0); 5965 MPASS(txp->wr_type == 1); /* VF supports type 1 only */ 5966 MPASS(txp->mb[0] != NULL); 5967 MPASS(txp->len16 <= howmany(SGE_MAX_WR_LEN, 16)); 5968 5969 wr = (void *)&eq->desc[eq->pidx]; 5970 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_VM_WR)); 5971 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(txp->len16)); 5972 wr->r3 = 0; 5973 wr->plen = htobe16(txp->plen); 5974 wr->npkt = txp->npkt; 5975 wr->r4 = 0; 5976 memcpy(&wr->ethmacdst[0], &txp->ethmacdst[0], 16); 5977 flitp = wr + 1; 5978 5979 /* 5980 * At this point we are 32B into a hardware descriptor. Each mbuf in 5981 * the WR will take 32B so we check for the end of the descriptor ring 5982 * before writing odd mbufs (mb[1], 3, 5, ..) 5983 */ 5984 ndesc = tx_len16_to_desc(txp->len16); 5985 last = NULL; 5986 for (i = 0; i < txp->npkt; i++) { 5987 m = txp->mb[i]; 5988 if (i & 1 && (uintptr_t)flitp == (uintptr_t)&eq->desc[eq->sidx]) 5989 flitp = &eq->desc[0]; 5990 cpl = flitp; 5991 5992 /* Checksum offload */ 5993 ctrl1 = csum_to_ctrl(sc, m); 5994 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS)) 5995 txq->txcsum++; /* some hardware assistance provided */ 5996 5997 /* VLAN tag insertion */ 5998 if (needs_vlan_insertion(m)) { 5999 ctrl1 |= F_TXPKT_VLAN_VLD | 6000 V_TXPKT_VLAN(m->m_pkthdr.ether_vtag); 6001 txq->vlan_insertion++; 6002 } else if (sc->vlan_id) 6003 ctrl1 |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(sc->vlan_id); 6004 6005 /* CPL header */ 6006 cpl->ctrl0 = txq->cpl_ctrl0; 6007 cpl->pack = 0; 6008 cpl->len = htobe16(m->m_pkthdr.len); 6009 cpl->ctrl1 = htobe64(ctrl1); 6010 6011 flitp = cpl + 1; 6012 MPASS(mbuf_nsegs(m) == 1); 6013 write_gl_to_txd(txq, m, (caddr_t *)(&flitp), 0); 6014 6015 if (last != NULL) 6016 last->m_nextpkt = m; 6017 last = m; 6018 } 6019 6020 txq->sgl_wrs++; 6021 txq->txpkts1_pkts += txp->npkt; 6022 txq->txpkts1_wrs++; 6023 6024 txsd = &txq->sdesc[eq->pidx]; 6025 txsd->m = txp->mb[0]; 6026 txsd->desc_used = ndesc; 6027 6028 return (ndesc); 6029 } 6030 6031 /* 6032 * If the SGL ends on an address that is not 16 byte aligned, this function will 6033 * add a 0 filled flit at the end. 6034 */ 6035 static void 6036 write_gl_to_txd(struct sge_txq *txq, struct mbuf *m, caddr_t *to, int checkwrap) 6037 { 6038 struct sge_eq *eq = &txq->eq; 6039 struct sglist *gl = txq->gl; 6040 struct sglist_seg *seg; 6041 __be64 *flitp, *wrap; 6042 struct ulptx_sgl *usgl; 6043 int i, nflits, nsegs; 6044 6045 KASSERT(((uintptr_t)(*to) & 0xf) == 0, 6046 ("%s: SGL must start at a 16 byte boundary: %p", __func__, *to)); 6047 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]); 6048 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]); 6049 6050 get_pkt_gl(m, gl); 6051 nsegs = gl->sg_nseg; 6052 MPASS(nsegs > 0); 6053 6054 nflits = (3 * (nsegs - 1)) / 2 + ((nsegs - 1) & 1) + 2; 6055 flitp = (__be64 *)(*to); 6056 wrap = (__be64 *)(&eq->desc[eq->sidx]); 6057 seg = &gl->sg_segs[0]; 6058 usgl = (void *)flitp; 6059 6060 /* 6061 * We start at a 16 byte boundary somewhere inside the tx descriptor 6062 * ring, so we're at least 16 bytes away from the status page. There is 6063 * no chance of a wrap around in the middle of usgl (which is 16 bytes). 6064 */ 6065 6066 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 6067 V_ULPTX_NSGE(nsegs)); 6068 usgl->len0 = htobe32(seg->ss_len); 6069 usgl->addr0 = htobe64(seg->ss_paddr); 6070 seg++; 6071 6072 if (checkwrap == 0 || (uintptr_t)(flitp + nflits) <= (uintptr_t)wrap) { 6073 6074 /* Won't wrap around at all */ 6075 6076 for (i = 0; i < nsegs - 1; i++, seg++) { 6077 usgl->sge[i / 2].len[i & 1] = htobe32(seg->ss_len); 6078 usgl->sge[i / 2].addr[i & 1] = htobe64(seg->ss_paddr); 6079 } 6080 if (i & 1) 6081 usgl->sge[i / 2].len[1] = htobe32(0); 6082 flitp += nflits; 6083 } else { 6084 6085 /* Will wrap somewhere in the rest of the SGL */ 6086 6087 /* 2 flits already written, write the rest flit by flit */ 6088 flitp = (void *)(usgl + 1); 6089 for (i = 0; i < nflits - 2; i++) { 6090 if (flitp == wrap) 6091 flitp = (void *)eq->desc; 6092 *flitp++ = get_flit(seg, nsegs - 1, i); 6093 } 6094 } 6095 6096 if (nflits & 1) { 6097 MPASS(((uintptr_t)flitp) & 0xf); 6098 *flitp++ = 0; 6099 } 6100 6101 MPASS((((uintptr_t)flitp) & 0xf) == 0); 6102 if (__predict_false(flitp == wrap)) 6103 *to = (void *)eq->desc; 6104 else 6105 *to = (void *)flitp; 6106 } 6107 6108 static inline void 6109 copy_to_txd(struct sge_eq *eq, caddr_t from, caddr_t *to, int len) 6110 { 6111 6112 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]); 6113 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]); 6114 6115 if (__predict_true((uintptr_t)(*to) + len <= 6116 (uintptr_t)&eq->desc[eq->sidx])) { 6117 bcopy(from, *to, len); 6118 (*to) += len; 6119 } else { 6120 int portion = (uintptr_t)&eq->desc[eq->sidx] - (uintptr_t)(*to); 6121 6122 bcopy(from, *to, portion); 6123 from += portion; 6124 portion = len - portion; /* remaining */ 6125 bcopy(from, (void *)eq->desc, portion); 6126 (*to) = (caddr_t)eq->desc + portion; 6127 } 6128 } 6129 6130 static inline void 6131 ring_eq_db(struct adapter *sc, struct sge_eq *eq, u_int n) 6132 { 6133 u_int db; 6134 6135 MPASS(n > 0); 6136 6137 db = eq->doorbells; 6138 if (n > 1) 6139 clrbit(&db, DOORBELL_WCWR); 6140 wmb(); 6141 6142 switch (ffs(db) - 1) { 6143 case DOORBELL_UDB: 6144 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n)); 6145 break; 6146 6147 case DOORBELL_WCWR: { 6148 volatile uint64_t *dst, *src; 6149 int i; 6150 6151 /* 6152 * Queues whose 128B doorbell segment fits in the page do not 6153 * use relative qid (udb_qid is always 0). Only queues with 6154 * doorbell segments can do WCWR. 6155 */ 6156 KASSERT(eq->udb_qid == 0 && n == 1, 6157 ("%s: inappropriate doorbell (0x%x, %d, %d) for eq %p", 6158 __func__, eq->doorbells, n, eq->dbidx, eq)); 6159 6160 dst = (volatile void *)((uintptr_t)eq->udb + UDBS_WR_OFFSET - 6161 UDBS_DB_OFFSET); 6162 i = eq->dbidx; 6163 src = (void *)&eq->desc[i]; 6164 while (src != (void *)&eq->desc[i + 1]) 6165 *dst++ = *src++; 6166 wmb(); 6167 break; 6168 } 6169 6170 case DOORBELL_UDBWC: 6171 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n)); 6172 wmb(); 6173 break; 6174 6175 case DOORBELL_KDB: 6176 t4_write_reg(sc, sc->sge_kdoorbell_reg, 6177 V_QID(eq->cntxt_id) | V_PIDX(n)); 6178 break; 6179 } 6180 6181 IDXINCR(eq->dbidx, n, eq->sidx); 6182 } 6183 6184 static inline u_int 6185 reclaimable_tx_desc(struct sge_eq *eq) 6186 { 6187 uint16_t hw_cidx; 6188 6189 hw_cidx = read_hw_cidx(eq); 6190 return (IDXDIFF(hw_cidx, eq->cidx, eq->sidx)); 6191 } 6192 6193 static inline u_int 6194 total_available_tx_desc(struct sge_eq *eq) 6195 { 6196 uint16_t hw_cidx, pidx; 6197 6198 hw_cidx = read_hw_cidx(eq); 6199 pidx = eq->pidx; 6200 6201 if (pidx == hw_cidx) 6202 return (eq->sidx - 1); 6203 else 6204 return (IDXDIFF(hw_cidx, pidx, eq->sidx) - 1); 6205 } 6206 6207 static inline uint16_t 6208 read_hw_cidx(struct sge_eq *eq) 6209 { 6210 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx]; 6211 uint16_t cidx = spg->cidx; /* stable snapshot */ 6212 6213 return (be16toh(cidx)); 6214 } 6215 6216 /* 6217 * Reclaim 'n' descriptors approximately. 6218 */ 6219 static u_int 6220 reclaim_tx_descs(struct sge_txq *txq, u_int n) 6221 { 6222 struct tx_sdesc *txsd; 6223 struct sge_eq *eq = &txq->eq; 6224 u_int can_reclaim, reclaimed; 6225 6226 TXQ_LOCK_ASSERT_OWNED(txq); 6227 MPASS(n > 0); 6228 6229 reclaimed = 0; 6230 can_reclaim = reclaimable_tx_desc(eq); 6231 while (can_reclaim && reclaimed < n) { 6232 int ndesc; 6233 struct mbuf *m, *nextpkt; 6234 6235 txsd = &txq->sdesc[eq->cidx]; 6236 ndesc = txsd->desc_used; 6237 6238 /* Firmware doesn't return "partial" credits. */ 6239 KASSERT(can_reclaim >= ndesc, 6240 ("%s: unexpected number of credits: %d, %d", 6241 __func__, can_reclaim, ndesc)); 6242 KASSERT(ndesc != 0, 6243 ("%s: descriptor with no credits: cidx %d", 6244 __func__, eq->cidx)); 6245 6246 for (m = txsd->m; m != NULL; m = nextpkt) { 6247 nextpkt = m->m_nextpkt; 6248 m->m_nextpkt = NULL; 6249 m_freem(m); 6250 } 6251 reclaimed += ndesc; 6252 can_reclaim -= ndesc; 6253 IDXINCR(eq->cidx, ndesc, eq->sidx); 6254 } 6255 6256 return (reclaimed); 6257 } 6258 6259 static void 6260 tx_reclaim(void *arg, int n) 6261 { 6262 struct sge_txq *txq = arg; 6263 struct sge_eq *eq = &txq->eq; 6264 6265 do { 6266 if (TXQ_TRYLOCK(txq) == 0) 6267 break; 6268 n = reclaim_tx_descs(txq, 32); 6269 if (eq->cidx == eq->pidx) 6270 eq->equeqidx = eq->pidx; 6271 TXQ_UNLOCK(txq); 6272 } while (n > 0); 6273 } 6274 6275 static __be64 6276 get_flit(struct sglist_seg *segs, int nsegs, int idx) 6277 { 6278 int i = (idx / 3) * 2; 6279 6280 switch (idx % 3) { 6281 case 0: { 6282 uint64_t rc; 6283 6284 rc = (uint64_t)segs[i].ss_len << 32; 6285 if (i + 1 < nsegs) 6286 rc |= (uint64_t)(segs[i + 1].ss_len); 6287 6288 return (htobe64(rc)); 6289 } 6290 case 1: 6291 return (htobe64(segs[i].ss_paddr)); 6292 case 2: 6293 return (htobe64(segs[i + 1].ss_paddr)); 6294 } 6295 6296 return (0); 6297 } 6298 6299 static int 6300 find_refill_source(struct adapter *sc, int maxp, bool packing) 6301 { 6302 int i, zidx = -1; 6303 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[0]; 6304 6305 if (packing) { 6306 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) { 6307 if (rxb->hwidx2 == -1) 6308 continue; 6309 if (rxb->size1 < PAGE_SIZE && 6310 rxb->size1 < largest_rx_cluster) 6311 continue; 6312 if (rxb->size1 > largest_rx_cluster) 6313 break; 6314 MPASS(rxb->size1 - rxb->size2 >= CL_METADATA_SIZE); 6315 if (rxb->size2 >= maxp) 6316 return (i); 6317 zidx = i; 6318 } 6319 } else { 6320 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) { 6321 if (rxb->hwidx1 == -1) 6322 continue; 6323 if (rxb->size1 > largest_rx_cluster) 6324 break; 6325 if (rxb->size1 >= maxp) 6326 return (i); 6327 zidx = i; 6328 } 6329 } 6330 6331 return (zidx); 6332 } 6333 6334 static void 6335 add_fl_to_sfl(struct adapter *sc, struct sge_fl *fl) 6336 { 6337 mtx_lock(&sc->sfl_lock); 6338 FL_LOCK(fl); 6339 if ((fl->flags & FL_DOOMED) == 0) { 6340 fl->flags |= FL_STARVING; 6341 TAILQ_INSERT_TAIL(&sc->sfl, fl, link); 6342 callout_reset(&sc->sfl_callout, hz / 5, refill_sfl, sc); 6343 } 6344 FL_UNLOCK(fl); 6345 mtx_unlock(&sc->sfl_lock); 6346 } 6347 6348 static void 6349 handle_wrq_egr_update(struct adapter *sc, struct sge_eq *eq) 6350 { 6351 struct sge_wrq *wrq = (void *)eq; 6352 6353 atomic_readandclear_int(&eq->equiq); 6354 taskqueue_enqueue(sc->tq[eq->port_id], &wrq->wrq_tx_task); 6355 } 6356 6357 static void 6358 handle_eth_egr_update(struct adapter *sc, struct sge_eq *eq) 6359 { 6360 struct sge_txq *txq = (void *)eq; 6361 6362 MPASS(eq->type == EQ_ETH); 6363 6364 atomic_readandclear_int(&eq->equiq); 6365 if (mp_ring_is_idle(txq->r)) 6366 taskqueue_enqueue(sc->tq[eq->port_id], &txq->tx_reclaim_task); 6367 else 6368 mp_ring_check_drainage(txq->r, 64); 6369 } 6370 6371 static int 6372 handle_sge_egr_update(struct sge_iq *iq, const struct rss_header *rss, 6373 struct mbuf *m) 6374 { 6375 const struct cpl_sge_egr_update *cpl = (const void *)(rss + 1); 6376 unsigned int qid = G_EGR_QID(ntohl(cpl->opcode_qid)); 6377 struct adapter *sc = iq->adapter; 6378 struct sge *s = &sc->sge; 6379 struct sge_eq *eq; 6380 static void (*h[])(struct adapter *, struct sge_eq *) = {NULL, 6381 &handle_wrq_egr_update, &handle_eth_egr_update, 6382 &handle_wrq_egr_update}; 6383 6384 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 6385 rss->opcode)); 6386 6387 eq = s->eqmap[qid - s->eq_start - s->eq_base]; 6388 (*h[eq->type])(sc, eq); 6389 6390 return (0); 6391 } 6392 6393 /* handle_fw_msg works for both fw4_msg and fw6_msg because this is valid */ 6394 CTASSERT(offsetof(struct cpl_fw4_msg, data) == \ 6395 offsetof(struct cpl_fw6_msg, data)); 6396 6397 static int 6398 handle_fw_msg(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 6399 { 6400 struct adapter *sc = iq->adapter; 6401 const struct cpl_fw6_msg *cpl = (const void *)(rss + 1); 6402 6403 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 6404 rss->opcode)); 6405 6406 if (cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL) { 6407 const struct rss_header *rss2; 6408 6409 rss2 = (const struct rss_header *)&cpl->data[0]; 6410 return (t4_cpl_handler[rss2->opcode](iq, rss2, m)); 6411 } 6412 6413 return (t4_fw_msg_handler[cpl->type](sc, &cpl->data[0])); 6414 } 6415 6416 /** 6417 * t4_handle_wrerr_rpl - process a FW work request error message 6418 * @adap: the adapter 6419 * @rpl: start of the FW message 6420 */ 6421 static int 6422 t4_handle_wrerr_rpl(struct adapter *adap, const __be64 *rpl) 6423 { 6424 u8 opcode = *(const u8 *)rpl; 6425 const struct fw_error_cmd *e = (const void *)rpl; 6426 unsigned int i; 6427 6428 if (opcode != FW_ERROR_CMD) { 6429 log(LOG_ERR, 6430 "%s: Received WRERR_RPL message with opcode %#x\n", 6431 device_get_nameunit(adap->dev), opcode); 6432 return (EINVAL); 6433 } 6434 log(LOG_ERR, "%s: FW_ERROR (%s) ", device_get_nameunit(adap->dev), 6435 G_FW_ERROR_CMD_FATAL(be32toh(e->op_to_type)) ? "fatal" : 6436 "non-fatal"); 6437 switch (G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type))) { 6438 case FW_ERROR_TYPE_EXCEPTION: 6439 log(LOG_ERR, "exception info:\n"); 6440 for (i = 0; i < nitems(e->u.exception.info); i++) 6441 log(LOG_ERR, "%s%08x", i == 0 ? "\t" : " ", 6442 be32toh(e->u.exception.info[i])); 6443 log(LOG_ERR, "\n"); 6444 break; 6445 case FW_ERROR_TYPE_HWMODULE: 6446 log(LOG_ERR, "HW module regaddr %08x regval %08x\n", 6447 be32toh(e->u.hwmodule.regaddr), 6448 be32toh(e->u.hwmodule.regval)); 6449 break; 6450 case FW_ERROR_TYPE_WR: 6451 log(LOG_ERR, "WR cidx %d PF %d VF %d eqid %d hdr:\n", 6452 be16toh(e->u.wr.cidx), 6453 G_FW_ERROR_CMD_PFN(be16toh(e->u.wr.pfn_vfn)), 6454 G_FW_ERROR_CMD_VFN(be16toh(e->u.wr.pfn_vfn)), 6455 be32toh(e->u.wr.eqid)); 6456 for (i = 0; i < nitems(e->u.wr.wrhdr); i++) 6457 log(LOG_ERR, "%s%02x", i == 0 ? "\t" : " ", 6458 e->u.wr.wrhdr[i]); 6459 log(LOG_ERR, "\n"); 6460 break; 6461 case FW_ERROR_TYPE_ACL: 6462 log(LOG_ERR, "ACL cidx %d PF %d VF %d eqid %d %s", 6463 be16toh(e->u.acl.cidx), 6464 G_FW_ERROR_CMD_PFN(be16toh(e->u.acl.pfn_vfn)), 6465 G_FW_ERROR_CMD_VFN(be16toh(e->u.acl.pfn_vfn)), 6466 be32toh(e->u.acl.eqid), 6467 G_FW_ERROR_CMD_MV(be16toh(e->u.acl.mv_pkd)) ? "vlanid" : 6468 "MAC"); 6469 for (i = 0; i < nitems(e->u.acl.val); i++) 6470 log(LOG_ERR, " %02x", e->u.acl.val[i]); 6471 log(LOG_ERR, "\n"); 6472 break; 6473 default: 6474 log(LOG_ERR, "type %#x\n", 6475 G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type))); 6476 return (EINVAL); 6477 } 6478 return (0); 6479 } 6480 6481 static inline bool 6482 bufidx_used(struct adapter *sc, int idx) 6483 { 6484 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[0]; 6485 int i; 6486 6487 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) { 6488 if (rxb->size1 > largest_rx_cluster) 6489 continue; 6490 if (rxb->hwidx1 == idx || rxb->hwidx2 == idx) 6491 return (true); 6492 } 6493 6494 return (false); 6495 } 6496 6497 static int 6498 sysctl_bufsizes(SYSCTL_HANDLER_ARGS) 6499 { 6500 struct adapter *sc = arg1; 6501 struct sge_params *sp = &sc->params.sge; 6502 int i, rc; 6503 struct sbuf sb; 6504 char c; 6505 6506 sbuf_new(&sb, NULL, 128, SBUF_AUTOEXTEND); 6507 for (i = 0; i < SGE_FLBUF_SIZES; i++) { 6508 if (bufidx_used(sc, i)) 6509 c = '*'; 6510 else 6511 c = '\0'; 6512 6513 sbuf_printf(&sb, "%u%c ", sp->sge_fl_buffer_size[i], c); 6514 } 6515 sbuf_trim(&sb); 6516 sbuf_finish(&sb); 6517 rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req); 6518 sbuf_delete(&sb); 6519 return (rc); 6520 } 6521 6522 #ifdef RATELIMIT 6523 #if defined(INET) || defined(INET6) 6524 /* 6525 * len16 for a txpkt WR with a GL. Includes the firmware work request header. 6526 */ 6527 static inline u_int 6528 txpkt_eo_len16(u_int nsegs, u_int immhdrs, u_int tso) 6529 { 6530 u_int n; 6531 6532 MPASS(immhdrs > 0); 6533 6534 n = roundup2(sizeof(struct fw_eth_tx_eo_wr) + 6535 sizeof(struct cpl_tx_pkt_core) + immhdrs, 16); 6536 if (__predict_false(nsegs == 0)) 6537 goto done; 6538 6539 nsegs--; /* first segment is part of ulptx_sgl */ 6540 n += sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 6541 if (tso) 6542 n += sizeof(struct cpl_tx_pkt_lso_core); 6543 6544 done: 6545 return (howmany(n, 16)); 6546 } 6547 #endif 6548 6549 #define ETID_FLOWC_NPARAMS 6 6550 #define ETID_FLOWC_LEN (roundup2((sizeof(struct fw_flowc_wr) + \ 6551 ETID_FLOWC_NPARAMS * sizeof(struct fw_flowc_mnemval)), 16)) 6552 #define ETID_FLOWC_LEN16 (howmany(ETID_FLOWC_LEN, 16)) 6553 6554 #if defined(INET) || defined(INET6) 6555 static int 6556 send_etid_flowc_wr(struct cxgbe_rate_tag *cst, struct port_info *pi, 6557 struct vi_info *vi) 6558 { 6559 struct wrq_cookie cookie; 6560 u_int pfvf = pi->adapter->pf << S_FW_VIID_PFN; 6561 struct fw_flowc_wr *flowc; 6562 6563 mtx_assert(&cst->lock, MA_OWNED); 6564 MPASS((cst->flags & (EO_FLOWC_PENDING | EO_FLOWC_RPL_PENDING)) == 6565 EO_FLOWC_PENDING); 6566 6567 flowc = start_wrq_wr(&cst->eo_txq->wrq, ETID_FLOWC_LEN16, &cookie); 6568 if (__predict_false(flowc == NULL)) 6569 return (ENOMEM); 6570 6571 bzero(flowc, ETID_FLOWC_LEN); 6572 flowc->op_to_nparams = htobe32(V_FW_WR_OP(FW_FLOWC_WR) | 6573 V_FW_FLOWC_WR_NPARAMS(ETID_FLOWC_NPARAMS) | V_FW_WR_COMPL(0)); 6574 flowc->flowid_len16 = htonl(V_FW_WR_LEN16(ETID_FLOWC_LEN16) | 6575 V_FW_WR_FLOWID(cst->etid)); 6576 flowc->mnemval[0].mnemonic = FW_FLOWC_MNEM_PFNVFN; 6577 flowc->mnemval[0].val = htobe32(pfvf); 6578 flowc->mnemval[1].mnemonic = FW_FLOWC_MNEM_CH; 6579 flowc->mnemval[1].val = htobe32(pi->tx_chan); 6580 flowc->mnemval[2].mnemonic = FW_FLOWC_MNEM_PORT; 6581 flowc->mnemval[2].val = htobe32(pi->tx_chan); 6582 flowc->mnemval[3].mnemonic = FW_FLOWC_MNEM_IQID; 6583 flowc->mnemval[3].val = htobe32(cst->iqid); 6584 flowc->mnemval[4].mnemonic = FW_FLOWC_MNEM_EOSTATE; 6585 flowc->mnemval[4].val = htobe32(FW_FLOWC_MNEM_EOSTATE_ESTABLISHED); 6586 flowc->mnemval[5].mnemonic = FW_FLOWC_MNEM_SCHEDCLASS; 6587 flowc->mnemval[5].val = htobe32(cst->schedcl); 6588 6589 commit_wrq_wr(&cst->eo_txq->wrq, flowc, &cookie); 6590 6591 cst->flags &= ~EO_FLOWC_PENDING; 6592 cst->flags |= EO_FLOWC_RPL_PENDING; 6593 MPASS(cst->tx_credits >= ETID_FLOWC_LEN16); /* flowc is first WR. */ 6594 cst->tx_credits -= ETID_FLOWC_LEN16; 6595 6596 return (0); 6597 } 6598 #endif 6599 6600 #define ETID_FLUSH_LEN16 (howmany(sizeof (struct fw_flowc_wr), 16)) 6601 6602 void 6603 send_etid_flush_wr(struct cxgbe_rate_tag *cst) 6604 { 6605 struct fw_flowc_wr *flowc; 6606 struct wrq_cookie cookie; 6607 6608 mtx_assert(&cst->lock, MA_OWNED); 6609 6610 flowc = start_wrq_wr(&cst->eo_txq->wrq, ETID_FLUSH_LEN16, &cookie); 6611 if (__predict_false(flowc == NULL)) 6612 CXGBE_UNIMPLEMENTED(__func__); 6613 6614 bzero(flowc, ETID_FLUSH_LEN16 * 16); 6615 flowc->op_to_nparams = htobe32(V_FW_WR_OP(FW_FLOWC_WR) | 6616 V_FW_FLOWC_WR_NPARAMS(0) | F_FW_WR_COMPL); 6617 flowc->flowid_len16 = htobe32(V_FW_WR_LEN16(ETID_FLUSH_LEN16) | 6618 V_FW_WR_FLOWID(cst->etid)); 6619 6620 commit_wrq_wr(&cst->eo_txq->wrq, flowc, &cookie); 6621 6622 cst->flags |= EO_FLUSH_RPL_PENDING; 6623 MPASS(cst->tx_credits >= ETID_FLUSH_LEN16); 6624 cst->tx_credits -= ETID_FLUSH_LEN16; 6625 cst->ncompl++; 6626 } 6627 6628 static void 6629 write_ethofld_wr(struct cxgbe_rate_tag *cst, struct fw_eth_tx_eo_wr *wr, 6630 struct mbuf *m0, int compl) 6631 { 6632 struct cpl_tx_pkt_core *cpl; 6633 uint64_t ctrl1; 6634 uint32_t ctrl; /* used in many unrelated places */ 6635 int len16, pktlen, nsegs, immhdrs; 6636 uintptr_t p; 6637 struct ulptx_sgl *usgl; 6638 struct sglist sg; 6639 struct sglist_seg segs[38]; /* XXX: find real limit. XXX: get off the stack */ 6640 6641 mtx_assert(&cst->lock, MA_OWNED); 6642 M_ASSERTPKTHDR(m0); 6643 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 6644 m0->m_pkthdr.l4hlen > 0, 6645 ("%s: ethofld mbuf %p is missing header lengths", __func__, m0)); 6646 6647 len16 = mbuf_eo_len16(m0); 6648 nsegs = mbuf_eo_nsegs(m0); 6649 pktlen = m0->m_pkthdr.len; 6650 ctrl = sizeof(struct cpl_tx_pkt_core); 6651 if (needs_tso(m0)) 6652 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 6653 immhdrs = m0->m_pkthdr.l2hlen + m0->m_pkthdr.l3hlen + m0->m_pkthdr.l4hlen; 6654 ctrl += immhdrs; 6655 6656 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_EO_WR) | 6657 V_FW_ETH_TX_EO_WR_IMMDLEN(ctrl) | V_FW_WR_COMPL(!!compl)); 6658 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(len16) | 6659 V_FW_WR_FLOWID(cst->etid)); 6660 wr->r3 = 0; 6661 if (needs_outer_udp_csum(m0)) { 6662 wr->u.udpseg.type = FW_ETH_TX_EO_TYPE_UDPSEG; 6663 wr->u.udpseg.ethlen = m0->m_pkthdr.l2hlen; 6664 wr->u.udpseg.iplen = htobe16(m0->m_pkthdr.l3hlen); 6665 wr->u.udpseg.udplen = m0->m_pkthdr.l4hlen; 6666 wr->u.udpseg.rtplen = 0; 6667 wr->u.udpseg.r4 = 0; 6668 wr->u.udpseg.mss = htobe16(pktlen - immhdrs); 6669 wr->u.udpseg.schedpktsize = wr->u.udpseg.mss; 6670 wr->u.udpseg.plen = htobe32(pktlen - immhdrs); 6671 cpl = (void *)(wr + 1); 6672 } else { 6673 MPASS(needs_outer_tcp_csum(m0)); 6674 wr->u.tcpseg.type = FW_ETH_TX_EO_TYPE_TCPSEG; 6675 wr->u.tcpseg.ethlen = m0->m_pkthdr.l2hlen; 6676 wr->u.tcpseg.iplen = htobe16(m0->m_pkthdr.l3hlen); 6677 wr->u.tcpseg.tcplen = m0->m_pkthdr.l4hlen; 6678 wr->u.tcpseg.tsclk_tsoff = mbuf_eo_tsclk_tsoff(m0); 6679 wr->u.tcpseg.r4 = 0; 6680 wr->u.tcpseg.r5 = 0; 6681 wr->u.tcpseg.plen = htobe32(pktlen - immhdrs); 6682 6683 if (needs_tso(m0)) { 6684 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1); 6685 6686 wr->u.tcpseg.mss = htobe16(m0->m_pkthdr.tso_segsz); 6687 6688 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | 6689 F_LSO_FIRST_SLICE | F_LSO_LAST_SLICE | 6690 V_LSO_ETHHDR_LEN((m0->m_pkthdr.l2hlen - 6691 ETHER_HDR_LEN) >> 2) | 6692 V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) | 6693 V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2); 6694 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 6695 ctrl |= F_LSO_IPV6; 6696 lso->lso_ctrl = htobe32(ctrl); 6697 lso->ipid_ofst = htobe16(0); 6698 lso->mss = htobe16(m0->m_pkthdr.tso_segsz); 6699 lso->seqno_offset = htobe32(0); 6700 lso->len = htobe32(pktlen); 6701 6702 cpl = (void *)(lso + 1); 6703 } else { 6704 wr->u.tcpseg.mss = htobe16(0xffff); 6705 cpl = (void *)(wr + 1); 6706 } 6707 } 6708 6709 /* Checksum offload must be requested for ethofld. */ 6710 MPASS(needs_outer_l4_csum(m0)); 6711 ctrl1 = csum_to_ctrl(cst->adapter, m0); 6712 6713 /* VLAN tag insertion */ 6714 if (needs_vlan_insertion(m0)) { 6715 ctrl1 |= F_TXPKT_VLAN_VLD | 6716 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 6717 } 6718 6719 /* CPL header */ 6720 cpl->ctrl0 = cst->ctrl0; 6721 cpl->pack = 0; 6722 cpl->len = htobe16(pktlen); 6723 cpl->ctrl1 = htobe64(ctrl1); 6724 6725 /* Copy Ethernet, IP & TCP/UDP hdrs as immediate data */ 6726 p = (uintptr_t)(cpl + 1); 6727 m_copydata(m0, 0, immhdrs, (void *)p); 6728 6729 /* SGL */ 6730 if (nsegs > 0) { 6731 int i, pad; 6732 6733 /* zero-pad upto next 16Byte boundary, if not 16Byte aligned */ 6734 p += immhdrs; 6735 pad = 16 - (immhdrs & 0xf); 6736 bzero((void *)p, pad); 6737 6738 usgl = (void *)(p + pad); 6739 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 6740 V_ULPTX_NSGE(nsegs)); 6741 6742 sglist_init(&sg, nitems(segs), segs); 6743 for (; m0 != NULL; m0 = m0->m_next) { 6744 if (__predict_false(m0->m_len == 0)) 6745 continue; 6746 if (immhdrs >= m0->m_len) { 6747 immhdrs -= m0->m_len; 6748 continue; 6749 } 6750 if (m0->m_flags & M_EXTPG) 6751 sglist_append_mbuf_epg(&sg, m0, 6752 mtod(m0, vm_offset_t), m0->m_len); 6753 else 6754 sglist_append(&sg, mtod(m0, char *) + immhdrs, 6755 m0->m_len - immhdrs); 6756 immhdrs = 0; 6757 } 6758 MPASS(sg.sg_nseg == nsegs); 6759 6760 /* 6761 * Zero pad last 8B in case the WR doesn't end on a 16B 6762 * boundary. 6763 */ 6764 *(uint64_t *)((char *)wr + len16 * 16 - 8) = 0; 6765 6766 usgl->len0 = htobe32(segs[0].ss_len); 6767 usgl->addr0 = htobe64(segs[0].ss_paddr); 6768 for (i = 0; i < nsegs - 1; i++) { 6769 usgl->sge[i / 2].len[i & 1] = htobe32(segs[i + 1].ss_len); 6770 usgl->sge[i / 2].addr[i & 1] = htobe64(segs[i + 1].ss_paddr); 6771 } 6772 if (i & 1) 6773 usgl->sge[i / 2].len[1] = htobe32(0); 6774 } 6775 6776 } 6777 6778 static void 6779 ethofld_tx(struct cxgbe_rate_tag *cst) 6780 { 6781 struct mbuf *m; 6782 struct wrq_cookie cookie; 6783 int next_credits, compl; 6784 struct fw_eth_tx_eo_wr *wr; 6785 6786 mtx_assert(&cst->lock, MA_OWNED); 6787 6788 while ((m = mbufq_first(&cst->pending_tx)) != NULL) { 6789 M_ASSERTPKTHDR(m); 6790 6791 /* How many len16 credits do we need to send this mbuf. */ 6792 next_credits = mbuf_eo_len16(m); 6793 MPASS(next_credits > 0); 6794 if (next_credits > cst->tx_credits) { 6795 /* 6796 * Tx will make progress eventually because there is at 6797 * least one outstanding fw4_ack that will return 6798 * credits and kick the tx. 6799 */ 6800 MPASS(cst->ncompl > 0); 6801 return; 6802 } 6803 wr = start_wrq_wr(&cst->eo_txq->wrq, next_credits, &cookie); 6804 if (__predict_false(wr == NULL)) { 6805 /* XXX: wishful thinking, not a real assertion. */ 6806 MPASS(cst->ncompl > 0); 6807 return; 6808 } 6809 cst->tx_credits -= next_credits; 6810 cst->tx_nocompl += next_credits; 6811 compl = cst->ncompl == 0 || cst->tx_nocompl >= cst->tx_total / 2; 6812 ETHER_BPF_MTAP(cst->com.ifp, m); 6813 write_ethofld_wr(cst, wr, m, compl); 6814 commit_wrq_wr(&cst->eo_txq->wrq, wr, &cookie); 6815 if (compl) { 6816 cst->ncompl++; 6817 cst->tx_nocompl = 0; 6818 } 6819 (void) mbufq_dequeue(&cst->pending_tx); 6820 6821 /* 6822 * Drop the mbuf's reference on the tag now rather 6823 * than waiting until m_freem(). This ensures that 6824 * cxgbe_rate_tag_free gets called when the inp drops 6825 * its reference on the tag and there are no more 6826 * mbufs in the pending_tx queue and can flush any 6827 * pending requests. Otherwise if the last mbuf 6828 * doesn't request a completion the etid will never be 6829 * released. 6830 */ 6831 m->m_pkthdr.snd_tag = NULL; 6832 m->m_pkthdr.csum_flags &= ~CSUM_SND_TAG; 6833 m_snd_tag_rele(&cst->com); 6834 6835 mbufq_enqueue(&cst->pending_fwack, m); 6836 } 6837 } 6838 6839 #if defined(INET) || defined(INET6) 6840 static int 6841 ethofld_transmit(if_t ifp, struct mbuf *m0) 6842 { 6843 struct cxgbe_rate_tag *cst; 6844 int rc; 6845 6846 MPASS(m0->m_nextpkt == NULL); 6847 MPASS(m0->m_pkthdr.csum_flags & CSUM_SND_TAG); 6848 MPASS(m0->m_pkthdr.snd_tag != NULL); 6849 cst = mst_to_crt(m0->m_pkthdr.snd_tag); 6850 6851 mtx_lock(&cst->lock); 6852 MPASS(cst->flags & EO_SND_TAG_REF); 6853 6854 if (__predict_false(cst->flags & EO_FLOWC_PENDING)) { 6855 struct vi_info *vi = if_getsoftc(ifp); 6856 struct port_info *pi = vi->pi; 6857 struct adapter *sc = pi->adapter; 6858 const uint32_t rss_mask = vi->rss_size - 1; 6859 uint32_t rss_hash; 6860 6861 cst->eo_txq = &sc->sge.ofld_txq[vi->first_ofld_txq]; 6862 if (M_HASHTYPE_ISHASH(m0)) 6863 rss_hash = m0->m_pkthdr.flowid; 6864 else 6865 rss_hash = arc4random(); 6866 /* We assume RSS hashing */ 6867 cst->iqid = vi->rss[rss_hash & rss_mask]; 6868 cst->eo_txq += rss_hash % vi->nofldtxq; 6869 rc = send_etid_flowc_wr(cst, pi, vi); 6870 if (rc != 0) 6871 goto done; 6872 } 6873 6874 if (__predict_false(cst->plen + m0->m_pkthdr.len > eo_max_backlog)) { 6875 rc = ENOBUFS; 6876 goto done; 6877 } 6878 6879 mbufq_enqueue(&cst->pending_tx, m0); 6880 cst->plen += m0->m_pkthdr.len; 6881 6882 /* 6883 * Hold an extra reference on the tag while generating work 6884 * requests to ensure that we don't try to free the tag during 6885 * ethofld_tx() in case we are sending the final mbuf after 6886 * the inp was freed. 6887 */ 6888 m_snd_tag_ref(&cst->com); 6889 ethofld_tx(cst); 6890 mtx_unlock(&cst->lock); 6891 m_snd_tag_rele(&cst->com); 6892 return (0); 6893 6894 done: 6895 mtx_unlock(&cst->lock); 6896 return (rc); 6897 } 6898 #endif 6899 6900 static int 6901 ethofld_fw4_ack(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0) 6902 { 6903 struct adapter *sc = iq->adapter; 6904 const struct cpl_fw4_ack *cpl = (const void *)(rss + 1); 6905 struct mbuf *m; 6906 u_int etid = G_CPL_FW4_ACK_FLOWID(be32toh(OPCODE_TID(cpl))); 6907 struct cxgbe_rate_tag *cst; 6908 uint8_t credits = cpl->credits; 6909 6910 cst = lookup_etid(sc, etid); 6911 mtx_lock(&cst->lock); 6912 if (__predict_false(cst->flags & EO_FLOWC_RPL_PENDING)) { 6913 MPASS(credits >= ETID_FLOWC_LEN16); 6914 credits -= ETID_FLOWC_LEN16; 6915 cst->flags &= ~EO_FLOWC_RPL_PENDING; 6916 } 6917 6918 KASSERT(cst->ncompl > 0, 6919 ("%s: etid %u (%p) wasn't expecting completion.", 6920 __func__, etid, cst)); 6921 cst->ncompl--; 6922 6923 while (credits > 0) { 6924 m = mbufq_dequeue(&cst->pending_fwack); 6925 if (__predict_false(m == NULL)) { 6926 /* 6927 * The remaining credits are for the final flush that 6928 * was issued when the tag was freed by the kernel. 6929 */ 6930 MPASS((cst->flags & 6931 (EO_FLUSH_RPL_PENDING | EO_SND_TAG_REF)) == 6932 EO_FLUSH_RPL_PENDING); 6933 MPASS(credits == ETID_FLUSH_LEN16); 6934 MPASS(cst->tx_credits + cpl->credits == cst->tx_total); 6935 MPASS(cst->ncompl == 0); 6936 6937 cst->flags &= ~EO_FLUSH_RPL_PENDING; 6938 cst->tx_credits += cpl->credits; 6939 cxgbe_rate_tag_free_locked(cst); 6940 return (0); /* cst is gone. */ 6941 } 6942 KASSERT(m != NULL, 6943 ("%s: too many credits (%u, %u)", __func__, cpl->credits, 6944 credits)); 6945 KASSERT(credits >= mbuf_eo_len16(m), 6946 ("%s: too few credits (%u, %u, %u)", __func__, 6947 cpl->credits, credits, mbuf_eo_len16(m))); 6948 credits -= mbuf_eo_len16(m); 6949 cst->plen -= m->m_pkthdr.len; 6950 m_freem(m); 6951 } 6952 6953 cst->tx_credits += cpl->credits; 6954 MPASS(cst->tx_credits <= cst->tx_total); 6955 6956 if (cst->flags & EO_SND_TAG_REF) { 6957 /* 6958 * As with ethofld_transmit(), hold an extra reference 6959 * so that the tag is stable across ethold_tx(). 6960 */ 6961 m_snd_tag_ref(&cst->com); 6962 m = mbufq_first(&cst->pending_tx); 6963 if (m != NULL && cst->tx_credits >= mbuf_eo_len16(m)) 6964 ethofld_tx(cst); 6965 mtx_unlock(&cst->lock); 6966 m_snd_tag_rele(&cst->com); 6967 } else { 6968 /* 6969 * There shouldn't be any pending packets if the tag 6970 * was freed by the kernel since any pending packet 6971 * should hold a reference to the tag. 6972 */ 6973 MPASS(mbufq_first(&cst->pending_tx) == NULL); 6974 mtx_unlock(&cst->lock); 6975 } 6976 6977 return (0); 6978 } 6979 #endif 6980