1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 Chelsio Communications, Inc. 5 * All rights reserved. 6 * Written by: Navdeep Parhar <np@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include "opt_inet.h" 34 #include "opt_inet6.h" 35 #include "opt_ratelimit.h" 36 37 #include <sys/types.h> 38 #include <sys/eventhandler.h> 39 #include <sys/mbuf.h> 40 #include <sys/socket.h> 41 #include <sys/kernel.h> 42 #include <sys/malloc.h> 43 #include <sys/queue.h> 44 #include <sys/sbuf.h> 45 #include <sys/taskqueue.h> 46 #include <sys/time.h> 47 #include <sys/sglist.h> 48 #include <sys/sysctl.h> 49 #include <sys/smp.h> 50 #include <sys/counter.h> 51 #include <net/bpf.h> 52 #include <net/ethernet.h> 53 #include <net/if.h> 54 #include <net/if_vlan_var.h> 55 #include <netinet/in.h> 56 #include <netinet/ip.h> 57 #include <netinet/ip6.h> 58 #include <netinet/tcp.h> 59 #include <netinet/udp.h> 60 #include <machine/in_cksum.h> 61 #include <machine/md_var.h> 62 #include <vm/vm.h> 63 #include <vm/pmap.h> 64 #ifdef DEV_NETMAP 65 #include <machine/bus.h> 66 #include <sys/selinfo.h> 67 #include <net/if_var.h> 68 #include <net/netmap.h> 69 #include <dev/netmap/netmap_kern.h> 70 #endif 71 72 #include "common/common.h" 73 #include "common/t4_regs.h" 74 #include "common/t4_regs_values.h" 75 #include "common/t4_msg.h" 76 #include "t4_l2t.h" 77 #include "t4_mp_ring.h" 78 79 #ifdef T4_PKT_TIMESTAMP 80 #define RX_COPY_THRESHOLD (MINCLSIZE - 8) 81 #else 82 #define RX_COPY_THRESHOLD MINCLSIZE 83 #endif 84 85 /* 86 * Ethernet frames are DMA'd at this byte offset into the freelist buffer. 87 * 0-7 are valid values. 88 */ 89 static int fl_pktshift = 0; 90 TUNABLE_INT("hw.cxgbe.fl_pktshift", &fl_pktshift); 91 92 /* 93 * Pad ethernet payload up to this boundary. 94 * -1: driver should figure out a good value. 95 * 0: disable padding. 96 * Any power of 2 from 32 to 4096 (both inclusive) is also a valid value. 97 */ 98 int fl_pad = -1; 99 TUNABLE_INT("hw.cxgbe.fl_pad", &fl_pad); 100 101 /* 102 * Status page length. 103 * -1: driver should figure out a good value. 104 * 64 or 128 are the only other valid values. 105 */ 106 static int spg_len = -1; 107 TUNABLE_INT("hw.cxgbe.spg_len", &spg_len); 108 109 /* 110 * Congestion drops. 111 * -1: no congestion feedback (not recommended). 112 * 0: backpressure the channel instead of dropping packets right away. 113 * 1: no backpressure, drop packets for the congested queue immediately. 114 */ 115 static int cong_drop = 0; 116 TUNABLE_INT("hw.cxgbe.cong_drop", &cong_drop); 117 118 /* 119 * Deliver multiple frames in the same free list buffer if they fit. 120 * -1: let the driver decide whether to enable buffer packing or not. 121 * 0: disable buffer packing. 122 * 1: enable buffer packing. 123 */ 124 static int buffer_packing = -1; 125 TUNABLE_INT("hw.cxgbe.buffer_packing", &buffer_packing); 126 127 /* 128 * Start next frame in a packed buffer at this boundary. 129 * -1: driver should figure out a good value. 130 * T4: driver will ignore this and use the same value as fl_pad above. 131 * T5: 16, or a power of 2 from 64 to 4096 (both inclusive) is a valid value. 132 */ 133 static int fl_pack = -1; 134 TUNABLE_INT("hw.cxgbe.fl_pack", &fl_pack); 135 136 /* 137 * Allow the driver to create mbuf(s) in a cluster allocated for rx. 138 * 0: never; always allocate mbufs from the zone_mbuf UMA zone. 139 * 1: ok to create mbuf(s) within a cluster if there is room. 140 */ 141 static int allow_mbufs_in_cluster = 1; 142 TUNABLE_INT("hw.cxgbe.allow_mbufs_in_cluster", &allow_mbufs_in_cluster); 143 144 /* 145 * Largest rx cluster size that the driver is allowed to allocate. 146 */ 147 static int largest_rx_cluster = MJUM16BYTES; 148 TUNABLE_INT("hw.cxgbe.largest_rx_cluster", &largest_rx_cluster); 149 150 /* 151 * Size of cluster allocation that's most likely to succeed. The driver will 152 * fall back to this size if it fails to allocate clusters larger than this. 153 */ 154 static int safest_rx_cluster = PAGE_SIZE; 155 TUNABLE_INT("hw.cxgbe.safest_rx_cluster", &safest_rx_cluster); 156 157 #ifdef RATELIMIT 158 /* 159 * Knob to control TCP timestamp rewriting, and the granularity of the tick used 160 * for rewriting. -1 and 0-3 are all valid values. 161 * -1: hardware should leave the TCP timestamps alone. 162 * 0: 1ms 163 * 1: 100us 164 * 2: 10us 165 * 3: 1us 166 */ 167 static int tsclk = -1; 168 TUNABLE_INT("hw.cxgbe.tsclk", &tsclk); 169 170 static int eo_max_backlog = 1024 * 1024; 171 TUNABLE_INT("hw.cxgbe.eo_max_backlog", &eo_max_backlog); 172 #endif 173 174 /* 175 * The interrupt holdoff timers are multiplied by this value on T6+. 176 * 1 and 3-17 (both inclusive) are legal values. 177 */ 178 static int tscale = 1; 179 TUNABLE_INT("hw.cxgbe.tscale", &tscale); 180 181 /* 182 * Number of LRO entries in the lro_ctrl structure per rx queue. 183 */ 184 static int lro_entries = TCP_LRO_ENTRIES; 185 TUNABLE_INT("hw.cxgbe.lro_entries", &lro_entries); 186 187 /* 188 * This enables presorting of frames before they're fed into tcp_lro_rx. 189 */ 190 static int lro_mbufs = 0; 191 TUNABLE_INT("hw.cxgbe.lro_mbufs", &lro_mbufs); 192 193 struct txpkts { 194 u_int wr_type; /* type 0 or type 1 */ 195 u_int npkt; /* # of packets in this work request */ 196 u_int plen; /* total payload (sum of all packets) */ 197 u_int len16; /* # of 16B pieces used by this work request */ 198 }; 199 200 /* A packet's SGL. This + m_pkthdr has all info needed for tx */ 201 struct sgl { 202 struct sglist sg; 203 struct sglist_seg seg[TX_SGL_SEGS]; 204 }; 205 206 static int service_iq(struct sge_iq *, int); 207 static int service_iq_fl(struct sge_iq *, int); 208 static struct mbuf *get_fl_payload(struct adapter *, struct sge_fl *, uint32_t); 209 static int t4_eth_rx(struct sge_iq *, const struct rss_header *, struct mbuf *); 210 static inline void init_iq(struct sge_iq *, struct adapter *, int, int, int); 211 static inline void init_fl(struct adapter *, struct sge_fl *, int, int, char *); 212 static inline void init_eq(struct adapter *, struct sge_eq *, int, int, uint8_t, 213 uint16_t, char *); 214 static int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *, 215 bus_addr_t *, void **); 216 static int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 217 void *); 218 static int alloc_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *, 219 int, int); 220 static int free_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *); 221 static void add_iq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *, 222 struct sge_iq *); 223 static void add_fl_sysctls(struct adapter *, struct sysctl_ctx_list *, 224 struct sysctl_oid *, struct sge_fl *); 225 static int alloc_fwq(struct adapter *); 226 static int free_fwq(struct adapter *); 227 static int alloc_ctrlq(struct adapter *, struct sge_wrq *, int, 228 struct sysctl_oid *); 229 static int alloc_rxq(struct vi_info *, struct sge_rxq *, int, int, 230 struct sysctl_oid *); 231 static int free_rxq(struct vi_info *, struct sge_rxq *); 232 #ifdef TCP_OFFLOAD 233 static int alloc_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *, int, int, 234 struct sysctl_oid *); 235 static int free_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *); 236 #endif 237 #ifdef DEV_NETMAP 238 static int alloc_nm_rxq(struct vi_info *, struct sge_nm_rxq *, int, int, 239 struct sysctl_oid *); 240 static int free_nm_rxq(struct vi_info *, struct sge_nm_rxq *); 241 static int alloc_nm_txq(struct vi_info *, struct sge_nm_txq *, int, int, 242 struct sysctl_oid *); 243 static int free_nm_txq(struct vi_info *, struct sge_nm_txq *); 244 #endif 245 static int ctrl_eq_alloc(struct adapter *, struct sge_eq *); 246 static int eth_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *); 247 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 248 static int ofld_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *); 249 #endif 250 static int alloc_eq(struct adapter *, struct vi_info *, struct sge_eq *); 251 static int free_eq(struct adapter *, struct sge_eq *); 252 static int alloc_wrq(struct adapter *, struct vi_info *, struct sge_wrq *, 253 struct sysctl_oid *); 254 static int free_wrq(struct adapter *, struct sge_wrq *); 255 static int alloc_txq(struct vi_info *, struct sge_txq *, int, 256 struct sysctl_oid *); 257 static int free_txq(struct vi_info *, struct sge_txq *); 258 static void oneseg_dma_callback(void *, bus_dma_segment_t *, int, int); 259 static inline void ring_fl_db(struct adapter *, struct sge_fl *); 260 static int refill_fl(struct adapter *, struct sge_fl *, int); 261 static void refill_sfl(void *); 262 static int alloc_fl_sdesc(struct sge_fl *); 263 static void free_fl_sdesc(struct adapter *, struct sge_fl *); 264 static void find_best_refill_source(struct adapter *, struct sge_fl *, int); 265 static void find_safe_refill_source(struct adapter *, struct sge_fl *); 266 static void add_fl_to_sfl(struct adapter *, struct sge_fl *); 267 268 static inline void get_pkt_gl(struct mbuf *, struct sglist *); 269 static inline u_int txpkt_len16(u_int, u_int); 270 static inline u_int txpkt_vm_len16(u_int, u_int); 271 static inline u_int txpkts0_len16(u_int); 272 static inline u_int txpkts1_len16(void); 273 static u_int write_txpkt_wr(struct sge_txq *, struct fw_eth_tx_pkt_wr *, 274 struct mbuf *, u_int); 275 static u_int write_txpkt_vm_wr(struct adapter *, struct sge_txq *, 276 struct fw_eth_tx_pkt_vm_wr *, struct mbuf *, u_int); 277 static int try_txpkts(struct mbuf *, struct mbuf *, struct txpkts *, u_int); 278 static int add_to_txpkts(struct mbuf *, struct txpkts *, u_int); 279 static u_int write_txpkts_wr(struct sge_txq *, struct fw_eth_tx_pkts_wr *, 280 struct mbuf *, const struct txpkts *, u_int); 281 static void write_gl_to_txd(struct sge_txq *, struct mbuf *, caddr_t *, int); 282 static inline void copy_to_txd(struct sge_eq *, caddr_t, caddr_t *, int); 283 static inline void ring_eq_db(struct adapter *, struct sge_eq *, u_int); 284 static inline uint16_t read_hw_cidx(struct sge_eq *); 285 static inline u_int reclaimable_tx_desc(struct sge_eq *); 286 static inline u_int total_available_tx_desc(struct sge_eq *); 287 static u_int reclaim_tx_descs(struct sge_txq *, u_int); 288 static void tx_reclaim(void *, int); 289 static __be64 get_flit(struct sglist_seg *, int, int); 290 static int handle_sge_egr_update(struct sge_iq *, const struct rss_header *, 291 struct mbuf *); 292 static int handle_fw_msg(struct sge_iq *, const struct rss_header *, 293 struct mbuf *); 294 static int t4_handle_wrerr_rpl(struct adapter *, const __be64 *); 295 static void wrq_tx_drain(void *, int); 296 static void drain_wrq_wr_list(struct adapter *, struct sge_wrq *); 297 298 static int sysctl_uint16(SYSCTL_HANDLER_ARGS); 299 static int sysctl_bufsizes(SYSCTL_HANDLER_ARGS); 300 #ifdef RATELIMIT 301 static inline u_int txpkt_eo_len16(u_int, u_int, u_int); 302 static int ethofld_fw4_ack(struct sge_iq *, const struct rss_header *, 303 struct mbuf *); 304 #endif 305 306 static counter_u64_t extfree_refs; 307 static counter_u64_t extfree_rels; 308 309 an_handler_t t4_an_handler; 310 fw_msg_handler_t t4_fw_msg_handler[NUM_FW6_TYPES]; 311 cpl_handler_t t4_cpl_handler[NUM_CPL_CMDS]; 312 cpl_handler_t set_tcb_rpl_handlers[NUM_CPL_COOKIES]; 313 cpl_handler_t l2t_write_rpl_handlers[NUM_CPL_COOKIES]; 314 cpl_handler_t act_open_rpl_handlers[NUM_CPL_COOKIES]; 315 cpl_handler_t abort_rpl_rss_handlers[NUM_CPL_COOKIES]; 316 cpl_handler_t fw4_ack_handlers[NUM_CPL_COOKIES]; 317 318 void 319 t4_register_an_handler(an_handler_t h) 320 { 321 uintptr_t *loc; 322 323 MPASS(h == NULL || t4_an_handler == NULL); 324 325 loc = (uintptr_t *)&t4_an_handler; 326 atomic_store_rel_ptr(loc, (uintptr_t)h); 327 } 328 329 void 330 t4_register_fw_msg_handler(int type, fw_msg_handler_t h) 331 { 332 uintptr_t *loc; 333 334 MPASS(type < nitems(t4_fw_msg_handler)); 335 MPASS(h == NULL || t4_fw_msg_handler[type] == NULL); 336 /* 337 * These are dispatched by the handler for FW{4|6}_CPL_MSG using the CPL 338 * handler dispatch table. Reject any attempt to install a handler for 339 * this subtype. 340 */ 341 MPASS(type != FW_TYPE_RSSCPL); 342 MPASS(type != FW6_TYPE_RSSCPL); 343 344 loc = (uintptr_t *)&t4_fw_msg_handler[type]; 345 atomic_store_rel_ptr(loc, (uintptr_t)h); 346 } 347 348 void 349 t4_register_cpl_handler(int opcode, cpl_handler_t h) 350 { 351 uintptr_t *loc; 352 353 MPASS(opcode < nitems(t4_cpl_handler)); 354 MPASS(h == NULL || t4_cpl_handler[opcode] == NULL); 355 356 loc = (uintptr_t *)&t4_cpl_handler[opcode]; 357 atomic_store_rel_ptr(loc, (uintptr_t)h); 358 } 359 360 static int 361 set_tcb_rpl_handler(struct sge_iq *iq, const struct rss_header *rss, 362 struct mbuf *m) 363 { 364 const struct cpl_set_tcb_rpl *cpl = (const void *)(rss + 1); 365 u_int tid; 366 int cookie; 367 368 MPASS(m == NULL); 369 370 tid = GET_TID(cpl); 371 if (is_hpftid(iq->adapter, tid) || is_ftid(iq->adapter, tid)) { 372 /* 373 * The return code for filter-write is put in the CPL cookie so 374 * we have to rely on the hardware tid (is_ftid) to determine 375 * that this is a response to a filter. 376 */ 377 cookie = CPL_COOKIE_FILTER; 378 } else { 379 cookie = G_COOKIE(cpl->cookie); 380 } 381 MPASS(cookie > CPL_COOKIE_RESERVED); 382 MPASS(cookie < nitems(set_tcb_rpl_handlers)); 383 384 return (set_tcb_rpl_handlers[cookie](iq, rss, m)); 385 } 386 387 static int 388 l2t_write_rpl_handler(struct sge_iq *iq, const struct rss_header *rss, 389 struct mbuf *m) 390 { 391 const struct cpl_l2t_write_rpl *rpl = (const void *)(rss + 1); 392 unsigned int cookie; 393 394 MPASS(m == NULL); 395 396 cookie = GET_TID(rpl) & F_SYNC_WR ? CPL_COOKIE_TOM : CPL_COOKIE_FILTER; 397 return (l2t_write_rpl_handlers[cookie](iq, rss, m)); 398 } 399 400 static int 401 act_open_rpl_handler(struct sge_iq *iq, const struct rss_header *rss, 402 struct mbuf *m) 403 { 404 const struct cpl_act_open_rpl *cpl = (const void *)(rss + 1); 405 u_int cookie = G_TID_COOKIE(G_AOPEN_ATID(be32toh(cpl->atid_status))); 406 407 MPASS(m == NULL); 408 MPASS(cookie != CPL_COOKIE_RESERVED); 409 410 return (act_open_rpl_handlers[cookie](iq, rss, m)); 411 } 412 413 static int 414 abort_rpl_rss_handler(struct sge_iq *iq, const struct rss_header *rss, 415 struct mbuf *m) 416 { 417 struct adapter *sc = iq->adapter; 418 u_int cookie; 419 420 MPASS(m == NULL); 421 if (is_hashfilter(sc)) 422 cookie = CPL_COOKIE_HASHFILTER; 423 else 424 cookie = CPL_COOKIE_TOM; 425 426 return (abort_rpl_rss_handlers[cookie](iq, rss, m)); 427 } 428 429 static int 430 fw4_ack_handler(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 431 { 432 struct adapter *sc = iq->adapter; 433 const struct cpl_fw4_ack *cpl = (const void *)(rss + 1); 434 unsigned int tid = G_CPL_FW4_ACK_FLOWID(be32toh(OPCODE_TID(cpl))); 435 u_int cookie; 436 437 MPASS(m == NULL); 438 if (is_etid(sc, tid)) 439 cookie = CPL_COOKIE_ETHOFLD; 440 else 441 cookie = CPL_COOKIE_TOM; 442 443 return (fw4_ack_handlers[cookie](iq, rss, m)); 444 } 445 446 static void 447 t4_init_shared_cpl_handlers(void) 448 { 449 450 t4_register_cpl_handler(CPL_SET_TCB_RPL, set_tcb_rpl_handler); 451 t4_register_cpl_handler(CPL_L2T_WRITE_RPL, l2t_write_rpl_handler); 452 t4_register_cpl_handler(CPL_ACT_OPEN_RPL, act_open_rpl_handler); 453 t4_register_cpl_handler(CPL_ABORT_RPL_RSS, abort_rpl_rss_handler); 454 t4_register_cpl_handler(CPL_FW4_ACK, fw4_ack_handler); 455 } 456 457 void 458 t4_register_shared_cpl_handler(int opcode, cpl_handler_t h, int cookie) 459 { 460 uintptr_t *loc; 461 462 MPASS(opcode < nitems(t4_cpl_handler)); 463 MPASS(cookie > CPL_COOKIE_RESERVED); 464 MPASS(cookie < NUM_CPL_COOKIES); 465 MPASS(t4_cpl_handler[opcode] != NULL); 466 467 switch (opcode) { 468 case CPL_SET_TCB_RPL: 469 loc = (uintptr_t *)&set_tcb_rpl_handlers[cookie]; 470 break; 471 case CPL_L2T_WRITE_RPL: 472 loc = (uintptr_t *)&l2t_write_rpl_handlers[cookie]; 473 break; 474 case CPL_ACT_OPEN_RPL: 475 loc = (uintptr_t *)&act_open_rpl_handlers[cookie]; 476 break; 477 case CPL_ABORT_RPL_RSS: 478 loc = (uintptr_t *)&abort_rpl_rss_handlers[cookie]; 479 break; 480 case CPL_FW4_ACK: 481 loc = (uintptr_t *)&fw4_ack_handlers[cookie]; 482 break; 483 default: 484 MPASS(0); 485 return; 486 } 487 MPASS(h == NULL || *loc == (uintptr_t)NULL); 488 atomic_store_rel_ptr(loc, (uintptr_t)h); 489 } 490 491 /* 492 * Called on MOD_LOAD. Validates and calculates the SGE tunables. 493 */ 494 void 495 t4_sge_modload(void) 496 { 497 498 if (fl_pktshift < 0 || fl_pktshift > 7) { 499 printf("Invalid hw.cxgbe.fl_pktshift value (%d)," 500 " using 0 instead.\n", fl_pktshift); 501 fl_pktshift = 0; 502 } 503 504 if (spg_len != 64 && spg_len != 128) { 505 int len; 506 507 #if defined(__i386__) || defined(__amd64__) 508 len = cpu_clflush_line_size > 64 ? 128 : 64; 509 #else 510 len = 64; 511 #endif 512 if (spg_len != -1) { 513 printf("Invalid hw.cxgbe.spg_len value (%d)," 514 " using %d instead.\n", spg_len, len); 515 } 516 spg_len = len; 517 } 518 519 if (cong_drop < -1 || cong_drop > 1) { 520 printf("Invalid hw.cxgbe.cong_drop value (%d)," 521 " using 0 instead.\n", cong_drop); 522 cong_drop = 0; 523 } 524 525 if (tscale != 1 && (tscale < 3 || tscale > 17)) { 526 printf("Invalid hw.cxgbe.tscale value (%d)," 527 " using 1 instead.\n", tscale); 528 tscale = 1; 529 } 530 531 extfree_refs = counter_u64_alloc(M_WAITOK); 532 extfree_rels = counter_u64_alloc(M_WAITOK); 533 counter_u64_zero(extfree_refs); 534 counter_u64_zero(extfree_rels); 535 536 t4_init_shared_cpl_handlers(); 537 t4_register_cpl_handler(CPL_FW4_MSG, handle_fw_msg); 538 t4_register_cpl_handler(CPL_FW6_MSG, handle_fw_msg); 539 t4_register_cpl_handler(CPL_SGE_EGR_UPDATE, handle_sge_egr_update); 540 t4_register_cpl_handler(CPL_RX_PKT, t4_eth_rx); 541 #ifdef RATELIMIT 542 t4_register_shared_cpl_handler(CPL_FW4_ACK, ethofld_fw4_ack, 543 CPL_COOKIE_ETHOFLD); 544 #endif 545 t4_register_fw_msg_handler(FW6_TYPE_CMD_RPL, t4_handle_fw_rpl); 546 t4_register_fw_msg_handler(FW6_TYPE_WRERR_RPL, t4_handle_wrerr_rpl); 547 } 548 549 void 550 t4_sge_modunload(void) 551 { 552 553 counter_u64_free(extfree_refs); 554 counter_u64_free(extfree_rels); 555 } 556 557 uint64_t 558 t4_sge_extfree_refs(void) 559 { 560 uint64_t refs, rels; 561 562 rels = counter_u64_fetch(extfree_rels); 563 refs = counter_u64_fetch(extfree_refs); 564 565 return (refs - rels); 566 } 567 568 static inline void 569 setup_pad_and_pack_boundaries(struct adapter *sc) 570 { 571 uint32_t v, m; 572 int pad, pack, pad_shift; 573 574 pad_shift = chip_id(sc) > CHELSIO_T5 ? X_T6_INGPADBOUNDARY_SHIFT : 575 X_INGPADBOUNDARY_SHIFT; 576 pad = fl_pad; 577 if (fl_pad < (1 << pad_shift) || 578 fl_pad > (1 << (pad_shift + M_INGPADBOUNDARY)) || 579 !powerof2(fl_pad)) { 580 /* 581 * If there is any chance that we might use buffer packing and 582 * the chip is a T4, then pick 64 as the pad/pack boundary. Set 583 * it to the minimum allowed in all other cases. 584 */ 585 pad = is_t4(sc) && buffer_packing ? 64 : 1 << pad_shift; 586 587 /* 588 * For fl_pad = 0 we'll still write a reasonable value to the 589 * register but all the freelists will opt out of padding. 590 * We'll complain here only if the user tried to set it to a 591 * value greater than 0 that was invalid. 592 */ 593 if (fl_pad > 0) { 594 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pad value" 595 " (%d), using %d instead.\n", fl_pad, pad); 596 } 597 } 598 m = V_INGPADBOUNDARY(M_INGPADBOUNDARY); 599 v = V_INGPADBOUNDARY(ilog2(pad) - pad_shift); 600 t4_set_reg_field(sc, A_SGE_CONTROL, m, v); 601 602 if (is_t4(sc)) { 603 if (fl_pack != -1 && fl_pack != pad) { 604 /* Complain but carry on. */ 605 device_printf(sc->dev, "hw.cxgbe.fl_pack (%d) ignored," 606 " using %d instead.\n", fl_pack, pad); 607 } 608 return; 609 } 610 611 pack = fl_pack; 612 if (fl_pack < 16 || fl_pack == 32 || fl_pack > 4096 || 613 !powerof2(fl_pack)) { 614 pack = max(sc->params.pci.mps, CACHE_LINE_SIZE); 615 MPASS(powerof2(pack)); 616 if (pack < 16) 617 pack = 16; 618 if (pack == 32) 619 pack = 64; 620 if (pack > 4096) 621 pack = 4096; 622 if (fl_pack != -1) { 623 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pack value" 624 " (%d), using %d instead.\n", fl_pack, pack); 625 } 626 } 627 m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY); 628 if (pack == 16) 629 v = V_INGPACKBOUNDARY(0); 630 else 631 v = V_INGPACKBOUNDARY(ilog2(pack) - 5); 632 633 MPASS(!is_t4(sc)); /* T4 doesn't have SGE_CONTROL2 */ 634 t4_set_reg_field(sc, A_SGE_CONTROL2, m, v); 635 } 636 637 /* 638 * adap->params.vpd.cclk must be set up before this is called. 639 */ 640 void 641 t4_tweak_chip_settings(struct adapter *sc) 642 { 643 int i; 644 uint32_t v, m; 645 int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200}; 646 int timer_max = M_TIMERVALUE0 * 1000 / sc->params.vpd.cclk; 647 int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */ 648 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 649 static int sge_flbuf_sizes[] = { 650 MCLBYTES, 651 #if MJUMPAGESIZE != MCLBYTES 652 MJUMPAGESIZE, 653 MJUMPAGESIZE - CL_METADATA_SIZE, 654 MJUMPAGESIZE - 2 * MSIZE - CL_METADATA_SIZE, 655 #endif 656 MJUM9BYTES, 657 MJUM16BYTES, 658 MCLBYTES - MSIZE - CL_METADATA_SIZE, 659 MJUM9BYTES - CL_METADATA_SIZE, 660 MJUM16BYTES - CL_METADATA_SIZE, 661 }; 662 663 KASSERT(sc->flags & MASTER_PF, 664 ("%s: trying to change chip settings when not master.", __func__)); 665 666 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE; 667 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE | 668 V_EGRSTATUSPAGESIZE(spg_len == 128); 669 t4_set_reg_field(sc, A_SGE_CONTROL, m, v); 670 671 setup_pad_and_pack_boundaries(sc); 672 673 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) | 674 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) | 675 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) | 676 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) | 677 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) | 678 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) | 679 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) | 680 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10); 681 t4_write_reg(sc, A_SGE_HOST_PAGE_SIZE, v); 682 683 KASSERT(nitems(sge_flbuf_sizes) <= SGE_FLBUF_SIZES, 684 ("%s: hw buffer size table too big", __func__)); 685 for (i = 0; i < min(nitems(sge_flbuf_sizes), SGE_FLBUF_SIZES); i++) { 686 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0 + (4 * i), 687 sge_flbuf_sizes[i]); 688 } 689 690 v = V_THRESHOLD_0(intr_pktcount[0]) | V_THRESHOLD_1(intr_pktcount[1]) | 691 V_THRESHOLD_2(intr_pktcount[2]) | V_THRESHOLD_3(intr_pktcount[3]); 692 t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD, v); 693 694 KASSERT(intr_timer[0] <= timer_max, 695 ("%s: not a single usable timer (%d, %d)", __func__, intr_timer[0], 696 timer_max)); 697 for (i = 1; i < nitems(intr_timer); i++) { 698 KASSERT(intr_timer[i] >= intr_timer[i - 1], 699 ("%s: timers not listed in increasing order (%d)", 700 __func__, i)); 701 702 while (intr_timer[i] > timer_max) { 703 if (i == nitems(intr_timer) - 1) { 704 intr_timer[i] = timer_max; 705 break; 706 } 707 intr_timer[i] += intr_timer[i - 1]; 708 intr_timer[i] /= 2; 709 } 710 } 711 712 v = V_TIMERVALUE0(us_to_core_ticks(sc, intr_timer[0])) | 713 V_TIMERVALUE1(us_to_core_ticks(sc, intr_timer[1])); 714 t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1, v); 715 v = V_TIMERVALUE2(us_to_core_ticks(sc, intr_timer[2])) | 716 V_TIMERVALUE3(us_to_core_ticks(sc, intr_timer[3])); 717 t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3, v); 718 v = V_TIMERVALUE4(us_to_core_ticks(sc, intr_timer[4])) | 719 V_TIMERVALUE5(us_to_core_ticks(sc, intr_timer[5])); 720 t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5, v); 721 722 if (chip_id(sc) >= CHELSIO_T6) { 723 m = V_TSCALE(M_TSCALE); 724 if (tscale == 1) 725 v = 0; 726 else 727 v = V_TSCALE(tscale - 2); 728 t4_set_reg_field(sc, A_SGE_ITP_CONTROL, m, v); 729 730 if (sc->debug_flags & DF_DISABLE_TCB_CACHE) { 731 m = V_RDTHRESHOLD(M_RDTHRESHOLD) | F_WRTHRTHRESHEN | 732 V_WRTHRTHRESH(M_WRTHRTHRESH); 733 t4_tp_pio_read(sc, &v, 1, A_TP_CMM_CONFIG, 1); 734 v &= ~m; 735 v |= V_RDTHRESHOLD(1) | F_WRTHRTHRESHEN | 736 V_WRTHRTHRESH(16); 737 t4_tp_pio_write(sc, &v, 1, A_TP_CMM_CONFIG, 1); 738 } 739 } 740 741 /* 4K, 16K, 64K, 256K DDP "page sizes" for TDDP */ 742 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 743 t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, v); 744 745 /* 746 * 4K, 8K, 16K, 64K DDP "page sizes" for iSCSI DDP. These have been 747 * chosen with MAXPHYS = 128K in mind. The largest DDP buffer that we 748 * may have to deal with is MAXPHYS + 1 page. 749 */ 750 v = V_HPZ0(0) | V_HPZ1(1) | V_HPZ2(2) | V_HPZ3(4); 751 t4_write_reg(sc, A_ULP_RX_ISCSI_PSZ, v); 752 753 /* We use multiple DDP page sizes both in plain-TOE and ISCSI modes. */ 754 m = v = F_TDDPTAGTCB | F_ISCSITAGTCB; 755 t4_set_reg_field(sc, A_ULP_RX_CTL, m, v); 756 757 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 758 F_RESETDDPOFFSET; 759 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 760 t4_set_reg_field(sc, A_TP_PARA_REG5, m, v); 761 } 762 763 /* 764 * SGE wants the buffer to be at least 64B and then a multiple of 16. If 765 * padding is in use, the buffer's start and end need to be aligned to the pad 766 * boundary as well. We'll just make sure that the size is a multiple of the 767 * boundary here, it is up to the buffer allocation code to make sure the start 768 * of the buffer is aligned as well. 769 */ 770 static inline int 771 hwsz_ok(struct adapter *sc, int hwsz) 772 { 773 int mask = fl_pad ? sc->params.sge.pad_boundary - 1 : 16 - 1; 774 775 return (hwsz >= 64 && (hwsz & mask) == 0); 776 } 777 778 /* 779 * XXX: driver really should be able to deal with unexpected settings. 780 */ 781 int 782 t4_read_chip_settings(struct adapter *sc) 783 { 784 struct sge *s = &sc->sge; 785 struct sge_params *sp = &sc->params.sge; 786 int i, j, n, rc = 0; 787 uint32_t m, v, r; 788 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 789 static int sw_buf_sizes[] = { /* Sorted by size */ 790 MCLBYTES, 791 #if MJUMPAGESIZE != MCLBYTES 792 MJUMPAGESIZE, 793 #endif 794 MJUM9BYTES, 795 MJUM16BYTES 796 }; 797 struct sw_zone_info *swz, *safe_swz; 798 struct hw_buf_info *hwb; 799 800 m = F_RXPKTCPLMODE; 801 v = F_RXPKTCPLMODE; 802 r = sc->params.sge.sge_control; 803 if ((r & m) != v) { 804 device_printf(sc->dev, "invalid SGE_CONTROL(0x%x)\n", r); 805 rc = EINVAL; 806 } 807 808 /* 809 * If this changes then every single use of PAGE_SHIFT in the driver 810 * needs to be carefully reviewed for PAGE_SHIFT vs sp->page_shift. 811 */ 812 if (sp->page_shift != PAGE_SHIFT) { 813 device_printf(sc->dev, "invalid SGE_HOST_PAGE_SIZE(0x%x)\n", r); 814 rc = EINVAL; 815 } 816 817 /* Filter out unusable hw buffer sizes entirely (mark with -2). */ 818 hwb = &s->hw_buf_info[0]; 819 for (i = 0; i < nitems(s->hw_buf_info); i++, hwb++) { 820 r = sc->params.sge.sge_fl_buffer_size[i]; 821 hwb->size = r; 822 hwb->zidx = hwsz_ok(sc, r) ? -1 : -2; 823 hwb->next = -1; 824 } 825 826 /* 827 * Create a sorted list in decreasing order of hw buffer sizes (and so 828 * increasing order of spare area) for each software zone. 829 * 830 * If padding is enabled then the start and end of the buffer must align 831 * to the pad boundary; if packing is enabled then they must align with 832 * the pack boundary as well. Allocations from the cluster zones are 833 * aligned to min(size, 4K), so the buffer starts at that alignment and 834 * ends at hwb->size alignment. If mbuf inlining is allowed the 835 * starting alignment will be reduced to MSIZE and the driver will 836 * exercise appropriate caution when deciding on the best buffer layout 837 * to use. 838 */ 839 n = 0; /* no usable buffer size to begin with */ 840 swz = &s->sw_zone_info[0]; 841 safe_swz = NULL; 842 for (i = 0; i < SW_ZONE_SIZES; i++, swz++) { 843 int8_t head = -1, tail = -1; 844 845 swz->size = sw_buf_sizes[i]; 846 swz->zone = m_getzone(swz->size); 847 swz->type = m_gettype(swz->size); 848 849 if (swz->size < PAGE_SIZE) { 850 MPASS(powerof2(swz->size)); 851 if (fl_pad && (swz->size % sp->pad_boundary != 0)) 852 continue; 853 } 854 855 if (swz->size == safest_rx_cluster) 856 safe_swz = swz; 857 858 hwb = &s->hw_buf_info[0]; 859 for (j = 0; j < SGE_FLBUF_SIZES; j++, hwb++) { 860 if (hwb->zidx != -1 || hwb->size > swz->size) 861 continue; 862 #ifdef INVARIANTS 863 if (fl_pad) 864 MPASS(hwb->size % sp->pad_boundary == 0); 865 #endif 866 hwb->zidx = i; 867 if (head == -1) 868 head = tail = j; 869 else if (hwb->size < s->hw_buf_info[tail].size) { 870 s->hw_buf_info[tail].next = j; 871 tail = j; 872 } else { 873 int8_t *cur; 874 struct hw_buf_info *t; 875 876 for (cur = &head; *cur != -1; cur = &t->next) { 877 t = &s->hw_buf_info[*cur]; 878 if (hwb->size == t->size) { 879 hwb->zidx = -2; 880 break; 881 } 882 if (hwb->size > t->size) { 883 hwb->next = *cur; 884 *cur = j; 885 break; 886 } 887 } 888 } 889 } 890 swz->head_hwidx = head; 891 swz->tail_hwidx = tail; 892 893 if (tail != -1) { 894 n++; 895 if (swz->size - s->hw_buf_info[tail].size >= 896 CL_METADATA_SIZE) 897 sc->flags |= BUF_PACKING_OK; 898 } 899 } 900 if (n == 0) { 901 device_printf(sc->dev, "no usable SGE FL buffer size.\n"); 902 rc = EINVAL; 903 } 904 905 s->safe_hwidx1 = -1; 906 s->safe_hwidx2 = -1; 907 if (safe_swz != NULL) { 908 s->safe_hwidx1 = safe_swz->head_hwidx; 909 for (i = safe_swz->head_hwidx; i != -1; i = hwb->next) { 910 int spare; 911 912 hwb = &s->hw_buf_info[i]; 913 #ifdef INVARIANTS 914 if (fl_pad) 915 MPASS(hwb->size % sp->pad_boundary == 0); 916 #endif 917 spare = safe_swz->size - hwb->size; 918 if (spare >= CL_METADATA_SIZE) { 919 s->safe_hwidx2 = i; 920 break; 921 } 922 } 923 } 924 925 if (sc->flags & IS_VF) 926 return (0); 927 928 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 929 r = t4_read_reg(sc, A_ULP_RX_TDDP_PSZ); 930 if (r != v) { 931 device_printf(sc->dev, "invalid ULP_RX_TDDP_PSZ(0x%x)\n", r); 932 rc = EINVAL; 933 } 934 935 m = v = F_TDDPTAGTCB; 936 r = t4_read_reg(sc, A_ULP_RX_CTL); 937 if ((r & m) != v) { 938 device_printf(sc->dev, "invalid ULP_RX_CTL(0x%x)\n", r); 939 rc = EINVAL; 940 } 941 942 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 943 F_RESETDDPOFFSET; 944 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 945 r = t4_read_reg(sc, A_TP_PARA_REG5); 946 if ((r & m) != v) { 947 device_printf(sc->dev, "invalid TP_PARA_REG5(0x%x)\n", r); 948 rc = EINVAL; 949 } 950 951 t4_init_tp_params(sc, 1); 952 953 t4_read_mtu_tbl(sc, sc->params.mtus, NULL); 954 t4_load_mtus(sc, sc->params.mtus, sc->params.a_wnd, sc->params.b_wnd); 955 956 return (rc); 957 } 958 959 int 960 t4_create_dma_tag(struct adapter *sc) 961 { 962 int rc; 963 964 rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0, 965 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE, 966 BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL, 967 NULL, &sc->dmat); 968 if (rc != 0) { 969 device_printf(sc->dev, 970 "failed to create main DMA tag: %d\n", rc); 971 } 972 973 return (rc); 974 } 975 976 void 977 t4_sge_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx, 978 struct sysctl_oid_list *children) 979 { 980 struct sge_params *sp = &sc->params.sge; 981 982 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "buffer_sizes", 983 CTLTYPE_STRING | CTLFLAG_RD, &sc->sge, 0, sysctl_bufsizes, "A", 984 "freelist buffer sizes"); 985 986 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pktshift", CTLFLAG_RD, 987 NULL, sp->fl_pktshift, "payload DMA offset in rx buffer (bytes)"); 988 989 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pad", CTLFLAG_RD, 990 NULL, sp->pad_boundary, "payload pad boundary (bytes)"); 991 992 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "spg_len", CTLFLAG_RD, 993 NULL, sp->spg_len, "status page size (bytes)"); 994 995 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_drop", CTLFLAG_RD, 996 NULL, cong_drop, "congestion drop setting"); 997 998 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pack", CTLFLAG_RD, 999 NULL, sp->pack_boundary, "payload pack boundary (bytes)"); 1000 } 1001 1002 int 1003 t4_destroy_dma_tag(struct adapter *sc) 1004 { 1005 if (sc->dmat) 1006 bus_dma_tag_destroy(sc->dmat); 1007 1008 return (0); 1009 } 1010 1011 /* 1012 * Allocate and initialize the firmware event queue, control queues, and special 1013 * purpose rx queues owned by the adapter. 1014 * 1015 * Returns errno on failure. Resources allocated up to that point may still be 1016 * allocated. Caller is responsible for cleanup in case this function fails. 1017 */ 1018 int 1019 t4_setup_adapter_queues(struct adapter *sc) 1020 { 1021 struct sysctl_oid *oid; 1022 struct sysctl_oid_list *children; 1023 int rc, i; 1024 1025 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 1026 1027 sysctl_ctx_init(&sc->ctx); 1028 sc->flags |= ADAP_SYSCTL_CTX; 1029 1030 /* 1031 * Firmware event queue 1032 */ 1033 rc = alloc_fwq(sc); 1034 if (rc != 0) 1035 return (rc); 1036 1037 /* 1038 * That's all for the VF driver. 1039 */ 1040 if (sc->flags & IS_VF) 1041 return (rc); 1042 1043 oid = device_get_sysctl_tree(sc->dev); 1044 children = SYSCTL_CHILDREN(oid); 1045 1046 /* 1047 * XXX: General purpose rx queues, one per port. 1048 */ 1049 1050 /* 1051 * Control queues, one per port. 1052 */ 1053 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "ctrlq", 1054 CTLFLAG_RD, NULL, "control queues"); 1055 for_each_port(sc, i) { 1056 struct sge_wrq *ctrlq = &sc->sge.ctrlq[i]; 1057 1058 rc = alloc_ctrlq(sc, ctrlq, i, oid); 1059 if (rc != 0) 1060 return (rc); 1061 } 1062 1063 return (rc); 1064 } 1065 1066 /* 1067 * Idempotent 1068 */ 1069 int 1070 t4_teardown_adapter_queues(struct adapter *sc) 1071 { 1072 int i; 1073 1074 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 1075 1076 /* Do this before freeing the queue */ 1077 if (sc->flags & ADAP_SYSCTL_CTX) { 1078 sysctl_ctx_free(&sc->ctx); 1079 sc->flags &= ~ADAP_SYSCTL_CTX; 1080 } 1081 1082 if (!(sc->flags & IS_VF)) { 1083 for_each_port(sc, i) 1084 free_wrq(sc, &sc->sge.ctrlq[i]); 1085 } 1086 free_fwq(sc); 1087 1088 return (0); 1089 } 1090 1091 /* Maximum payload that can be delivered with a single iq descriptor */ 1092 static inline int 1093 mtu_to_max_payload(struct adapter *sc, int mtu, const int toe) 1094 { 1095 int payload; 1096 1097 #ifdef TCP_OFFLOAD 1098 if (toe) { 1099 int rxcs = G_RXCOALESCESIZE(t4_read_reg(sc, A_TP_PARA_REG2)); 1100 1101 /* Note that COP can set rx_coalesce on/off per connection. */ 1102 payload = max(mtu, rxcs); 1103 } else { 1104 #endif 1105 /* large enough even when hw VLAN extraction is disabled */ 1106 payload = sc->params.sge.fl_pktshift + ETHER_HDR_LEN + 1107 ETHER_VLAN_ENCAP_LEN + mtu; 1108 #ifdef TCP_OFFLOAD 1109 } 1110 #endif 1111 1112 return (payload); 1113 } 1114 1115 int 1116 t4_setup_vi_queues(struct vi_info *vi) 1117 { 1118 int rc = 0, i, intr_idx, iqidx; 1119 struct sge_rxq *rxq; 1120 struct sge_txq *txq; 1121 #ifdef TCP_OFFLOAD 1122 struct sge_ofld_rxq *ofld_rxq; 1123 #endif 1124 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1125 struct sge_wrq *ofld_txq; 1126 #endif 1127 #ifdef DEV_NETMAP 1128 int saved_idx; 1129 struct sge_nm_rxq *nm_rxq; 1130 struct sge_nm_txq *nm_txq; 1131 #endif 1132 char name[16]; 1133 struct port_info *pi = vi->pi; 1134 struct adapter *sc = pi->adapter; 1135 struct ifnet *ifp = vi->ifp; 1136 struct sysctl_oid *oid = device_get_sysctl_tree(vi->dev); 1137 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 1138 int maxp, mtu = ifp->if_mtu; 1139 1140 /* Interrupt vector to start from (when using multiple vectors) */ 1141 intr_idx = vi->first_intr; 1142 1143 #ifdef DEV_NETMAP 1144 saved_idx = intr_idx; 1145 if (ifp->if_capabilities & IFCAP_NETMAP) { 1146 1147 /* netmap is supported with direct interrupts only. */ 1148 MPASS(!forwarding_intr_to_fwq(sc)); 1149 1150 /* 1151 * We don't have buffers to back the netmap rx queues 1152 * right now so we create the queues in a way that 1153 * doesn't set off any congestion signal in the chip. 1154 */ 1155 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "nm_rxq", 1156 CTLFLAG_RD, NULL, "rx queues"); 1157 for_each_nm_rxq(vi, i, nm_rxq) { 1158 rc = alloc_nm_rxq(vi, nm_rxq, intr_idx, i, oid); 1159 if (rc != 0) 1160 goto done; 1161 intr_idx++; 1162 } 1163 1164 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "nm_txq", 1165 CTLFLAG_RD, NULL, "tx queues"); 1166 for_each_nm_txq(vi, i, nm_txq) { 1167 iqidx = vi->first_nm_rxq + (i % vi->nnmrxq); 1168 rc = alloc_nm_txq(vi, nm_txq, iqidx, i, oid); 1169 if (rc != 0) 1170 goto done; 1171 } 1172 } 1173 1174 /* Normal rx queues and netmap rx queues share the same interrupts. */ 1175 intr_idx = saved_idx; 1176 #endif 1177 1178 /* 1179 * Allocate rx queues first because a default iqid is required when 1180 * creating a tx queue. 1181 */ 1182 maxp = mtu_to_max_payload(sc, mtu, 0); 1183 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "rxq", 1184 CTLFLAG_RD, NULL, "rx queues"); 1185 for_each_rxq(vi, i, rxq) { 1186 1187 init_iq(&rxq->iq, sc, vi->tmr_idx, vi->pktc_idx, vi->qsize_rxq); 1188 1189 snprintf(name, sizeof(name), "%s rxq%d-fl", 1190 device_get_nameunit(vi->dev), i); 1191 init_fl(sc, &rxq->fl, vi->qsize_rxq / 8, maxp, name); 1192 1193 rc = alloc_rxq(vi, rxq, 1194 forwarding_intr_to_fwq(sc) ? -1 : intr_idx, i, oid); 1195 if (rc != 0) 1196 goto done; 1197 intr_idx++; 1198 } 1199 #ifdef DEV_NETMAP 1200 if (ifp->if_capabilities & IFCAP_NETMAP) 1201 intr_idx = saved_idx + max(vi->nrxq, vi->nnmrxq); 1202 #endif 1203 #ifdef TCP_OFFLOAD 1204 maxp = mtu_to_max_payload(sc, mtu, 1); 1205 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_rxq", 1206 CTLFLAG_RD, NULL, "rx queues for offloaded TCP connections"); 1207 for_each_ofld_rxq(vi, i, ofld_rxq) { 1208 1209 init_iq(&ofld_rxq->iq, sc, vi->ofld_tmr_idx, vi->ofld_pktc_idx, 1210 vi->qsize_rxq); 1211 1212 snprintf(name, sizeof(name), "%s ofld_rxq%d-fl", 1213 device_get_nameunit(vi->dev), i); 1214 init_fl(sc, &ofld_rxq->fl, vi->qsize_rxq / 8, maxp, name); 1215 1216 rc = alloc_ofld_rxq(vi, ofld_rxq, 1217 forwarding_intr_to_fwq(sc) ? -1 : intr_idx, i, oid); 1218 if (rc != 0) 1219 goto done; 1220 intr_idx++; 1221 } 1222 #endif 1223 1224 /* 1225 * Now the tx queues. 1226 */ 1227 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "txq", CTLFLAG_RD, 1228 NULL, "tx queues"); 1229 for_each_txq(vi, i, txq) { 1230 iqidx = vi->first_rxq + (i % vi->nrxq); 1231 snprintf(name, sizeof(name), "%s txq%d", 1232 device_get_nameunit(vi->dev), i); 1233 init_eq(sc, &txq->eq, EQ_ETH, vi->qsize_txq, pi->tx_chan, 1234 sc->sge.rxq[iqidx].iq.cntxt_id, name); 1235 1236 rc = alloc_txq(vi, txq, i, oid); 1237 if (rc != 0) 1238 goto done; 1239 } 1240 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1241 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_txq", 1242 CTLFLAG_RD, NULL, "tx queues for TOE/ETHOFLD"); 1243 for_each_ofld_txq(vi, i, ofld_txq) { 1244 struct sysctl_oid *oid2; 1245 1246 snprintf(name, sizeof(name), "%s ofld_txq%d", 1247 device_get_nameunit(vi->dev), i); 1248 #ifdef TCP_OFFLOAD 1249 iqidx = vi->first_ofld_rxq + (i % vi->nofldrxq); 1250 init_eq(sc, &ofld_txq->eq, EQ_OFLD, vi->qsize_txq, pi->tx_chan, 1251 sc->sge.ofld_rxq[iqidx].iq.cntxt_id, name); 1252 #else 1253 iqidx = vi->first_rxq + (i % vi->nrxq); 1254 init_eq(sc, &ofld_txq->eq, EQ_OFLD, vi->qsize_txq, pi->tx_chan, 1255 sc->sge.rxq[iqidx].iq.cntxt_id, name); 1256 #endif 1257 1258 snprintf(name, sizeof(name), "%d", i); 1259 oid2 = SYSCTL_ADD_NODE(&vi->ctx, SYSCTL_CHILDREN(oid), OID_AUTO, 1260 name, CTLFLAG_RD, NULL, "offload tx queue"); 1261 1262 rc = alloc_wrq(sc, vi, ofld_txq, oid2); 1263 if (rc != 0) 1264 goto done; 1265 } 1266 #endif 1267 done: 1268 if (rc) 1269 t4_teardown_vi_queues(vi); 1270 1271 return (rc); 1272 } 1273 1274 /* 1275 * Idempotent 1276 */ 1277 int 1278 t4_teardown_vi_queues(struct vi_info *vi) 1279 { 1280 int i; 1281 struct sge_rxq *rxq; 1282 struct sge_txq *txq; 1283 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1284 struct port_info *pi = vi->pi; 1285 struct adapter *sc = pi->adapter; 1286 struct sge_wrq *ofld_txq; 1287 #endif 1288 #ifdef TCP_OFFLOAD 1289 struct sge_ofld_rxq *ofld_rxq; 1290 #endif 1291 #ifdef DEV_NETMAP 1292 struct sge_nm_rxq *nm_rxq; 1293 struct sge_nm_txq *nm_txq; 1294 #endif 1295 1296 /* Do this before freeing the queues */ 1297 if (vi->flags & VI_SYSCTL_CTX) { 1298 sysctl_ctx_free(&vi->ctx); 1299 vi->flags &= ~VI_SYSCTL_CTX; 1300 } 1301 1302 #ifdef DEV_NETMAP 1303 if (vi->ifp->if_capabilities & IFCAP_NETMAP) { 1304 for_each_nm_txq(vi, i, nm_txq) { 1305 free_nm_txq(vi, nm_txq); 1306 } 1307 1308 for_each_nm_rxq(vi, i, nm_rxq) { 1309 free_nm_rxq(vi, nm_rxq); 1310 } 1311 } 1312 #endif 1313 1314 /* 1315 * Take down all the tx queues first, as they reference the rx queues 1316 * (for egress updates, etc.). 1317 */ 1318 1319 for_each_txq(vi, i, txq) { 1320 free_txq(vi, txq); 1321 } 1322 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1323 for_each_ofld_txq(vi, i, ofld_txq) { 1324 free_wrq(sc, ofld_txq); 1325 } 1326 #endif 1327 1328 /* 1329 * Then take down the rx queues. 1330 */ 1331 1332 for_each_rxq(vi, i, rxq) { 1333 free_rxq(vi, rxq); 1334 } 1335 #ifdef TCP_OFFLOAD 1336 for_each_ofld_rxq(vi, i, ofld_rxq) { 1337 free_ofld_rxq(vi, ofld_rxq); 1338 } 1339 #endif 1340 1341 return (0); 1342 } 1343 1344 /* 1345 * Interrupt handler when the driver is using only 1 interrupt. This is a very 1346 * unusual scenario. 1347 * 1348 * a) Deals with errors, if any. 1349 * b) Services firmware event queue, which is taking interrupts for all other 1350 * queues. 1351 */ 1352 void 1353 t4_intr_all(void *arg) 1354 { 1355 struct adapter *sc = arg; 1356 struct sge_iq *fwq = &sc->sge.fwq; 1357 1358 MPASS(sc->intr_count == 1); 1359 1360 t4_intr_err(arg); 1361 t4_intr_evt(fwq); 1362 } 1363 1364 /* 1365 * Interrupt handler for errors (installed directly when multiple interrupts are 1366 * being used, or called by t4_intr_all). 1367 */ 1368 void 1369 t4_intr_err(void *arg) 1370 { 1371 struct adapter *sc = arg; 1372 1373 t4_write_reg(sc, MYPF_REG(A_PCIE_PF_CLI), 0); 1374 t4_slow_intr_handler(sc); 1375 } 1376 1377 /* 1378 * Interrupt handler for iq-only queues. The firmware event queue is the only 1379 * such queue right now. 1380 */ 1381 void 1382 t4_intr_evt(void *arg) 1383 { 1384 struct sge_iq *iq = arg; 1385 1386 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 1387 service_iq(iq, 0); 1388 (void) atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 1389 } 1390 } 1391 1392 /* 1393 * Interrupt handler for iq+fl queues. 1394 */ 1395 void 1396 t4_intr(void *arg) 1397 { 1398 struct sge_iq *iq = arg; 1399 1400 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 1401 service_iq_fl(iq, 0); 1402 (void) atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 1403 } 1404 } 1405 1406 #ifdef DEV_NETMAP 1407 /* 1408 * Interrupt handler for netmap rx queues. 1409 */ 1410 void 1411 t4_nm_intr(void *arg) 1412 { 1413 struct sge_nm_rxq *nm_rxq = arg; 1414 1415 if (atomic_cmpset_int(&nm_rxq->nm_state, NM_ON, NM_BUSY)) { 1416 service_nm_rxq(nm_rxq); 1417 (void) atomic_cmpset_int(&nm_rxq->nm_state, NM_BUSY, NM_ON); 1418 } 1419 } 1420 1421 /* 1422 * Interrupt handler for vectors shared between NIC and netmap rx queues. 1423 */ 1424 void 1425 t4_vi_intr(void *arg) 1426 { 1427 struct irq *irq = arg; 1428 1429 MPASS(irq->nm_rxq != NULL); 1430 t4_nm_intr(irq->nm_rxq); 1431 1432 MPASS(irq->rxq != NULL); 1433 t4_intr(irq->rxq); 1434 } 1435 #endif 1436 1437 /* 1438 * Deals with interrupts on an iq-only (no freelist) queue. 1439 */ 1440 static int 1441 service_iq(struct sge_iq *iq, int budget) 1442 { 1443 struct sge_iq *q; 1444 struct adapter *sc = iq->adapter; 1445 struct iq_desc *d = &iq->desc[iq->cidx]; 1446 int ndescs = 0, limit; 1447 int rsp_type; 1448 uint32_t lq; 1449 STAILQ_HEAD(, sge_iq) iql = STAILQ_HEAD_INITIALIZER(iql); 1450 1451 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq)); 1452 KASSERT((iq->flags & IQ_HAS_FL) == 0, 1453 ("%s: called for iq %p with fl (iq->flags 0x%x)", __func__, iq, 1454 iq->flags)); 1455 MPASS((iq->flags & IQ_ADJ_CREDIT) == 0); 1456 MPASS((iq->flags & IQ_LRO_ENABLED) == 0); 1457 1458 limit = budget ? budget : iq->qsize / 16; 1459 1460 /* 1461 * We always come back and check the descriptor ring for new indirect 1462 * interrupts and other responses after running a single handler. 1463 */ 1464 for (;;) { 1465 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) { 1466 1467 rmb(); 1468 1469 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen); 1470 lq = be32toh(d->rsp.pldbuflen_qid); 1471 1472 switch (rsp_type) { 1473 case X_RSPD_TYPE_FLBUF: 1474 panic("%s: data for an iq (%p) with no freelist", 1475 __func__, iq); 1476 1477 /* NOTREACHED */ 1478 1479 case X_RSPD_TYPE_CPL: 1480 KASSERT(d->rss.opcode < NUM_CPL_CMDS, 1481 ("%s: bad opcode %02x.", __func__, 1482 d->rss.opcode)); 1483 t4_cpl_handler[d->rss.opcode](iq, &d->rss, NULL); 1484 break; 1485 1486 case X_RSPD_TYPE_INTR: 1487 /* 1488 * There are 1K interrupt-capable queues (qids 0 1489 * through 1023). A response type indicating a 1490 * forwarded interrupt with a qid >= 1K is an 1491 * iWARP async notification. 1492 */ 1493 if (__predict_true(lq >= 1024)) { 1494 t4_an_handler(iq, &d->rsp); 1495 break; 1496 } 1497 1498 q = sc->sge.iqmap[lq - sc->sge.iq_start - 1499 sc->sge.iq_base]; 1500 if (atomic_cmpset_int(&q->state, IQS_IDLE, 1501 IQS_BUSY)) { 1502 if (service_iq_fl(q, q->qsize / 16) == 0) { 1503 (void) atomic_cmpset_int(&q->state, 1504 IQS_BUSY, IQS_IDLE); 1505 } else { 1506 STAILQ_INSERT_TAIL(&iql, q, 1507 link); 1508 } 1509 } 1510 break; 1511 1512 default: 1513 KASSERT(0, 1514 ("%s: illegal response type %d on iq %p", 1515 __func__, rsp_type, iq)); 1516 log(LOG_ERR, 1517 "%s: illegal response type %d on iq %p", 1518 device_get_nameunit(sc->dev), rsp_type, iq); 1519 break; 1520 } 1521 1522 d++; 1523 if (__predict_false(++iq->cidx == iq->sidx)) { 1524 iq->cidx = 0; 1525 iq->gen ^= F_RSPD_GEN; 1526 d = &iq->desc[0]; 1527 } 1528 if (__predict_false(++ndescs == limit)) { 1529 t4_write_reg(sc, sc->sge_gts_reg, 1530 V_CIDXINC(ndescs) | 1531 V_INGRESSQID(iq->cntxt_id) | 1532 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); 1533 ndescs = 0; 1534 1535 if (budget) { 1536 return (EINPROGRESS); 1537 } 1538 } 1539 } 1540 1541 if (STAILQ_EMPTY(&iql)) 1542 break; 1543 1544 /* 1545 * Process the head only, and send it to the back of the list if 1546 * it's still not done. 1547 */ 1548 q = STAILQ_FIRST(&iql); 1549 STAILQ_REMOVE_HEAD(&iql, link); 1550 if (service_iq_fl(q, q->qsize / 8) == 0) 1551 (void) atomic_cmpset_int(&q->state, IQS_BUSY, IQS_IDLE); 1552 else 1553 STAILQ_INSERT_TAIL(&iql, q, link); 1554 } 1555 1556 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) | 1557 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params)); 1558 1559 return (0); 1560 } 1561 1562 static inline int 1563 sort_before_lro(struct lro_ctrl *lro) 1564 { 1565 1566 return (lro->lro_mbuf_max != 0); 1567 } 1568 1569 static inline uint64_t 1570 last_flit_to_ns(struct adapter *sc, uint64_t lf) 1571 { 1572 uint64_t n = be64toh(lf) & 0xfffffffffffffff; /* 60b, not 64b. */ 1573 1574 if (n > UINT64_MAX / 1000000) 1575 return (n / sc->params.vpd.cclk * 1000000); 1576 else 1577 return (n * 1000000 / sc->params.vpd.cclk); 1578 } 1579 1580 /* 1581 * Deals with interrupts on an iq+fl queue. 1582 */ 1583 static int 1584 service_iq_fl(struct sge_iq *iq, int budget) 1585 { 1586 struct sge_rxq *rxq = iq_to_rxq(iq); 1587 struct sge_fl *fl; 1588 struct adapter *sc = iq->adapter; 1589 struct iq_desc *d = &iq->desc[iq->cidx]; 1590 int ndescs = 0, limit; 1591 int rsp_type, refill, starved; 1592 uint32_t lq; 1593 uint16_t fl_hw_cidx; 1594 struct mbuf *m0; 1595 #if defined(INET) || defined(INET6) 1596 const struct timeval lro_timeout = {0, sc->lro_timeout}; 1597 struct lro_ctrl *lro = &rxq->lro; 1598 #endif 1599 1600 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq)); 1601 MPASS(iq->flags & IQ_HAS_FL); 1602 1603 limit = budget ? budget : iq->qsize / 16; 1604 fl = &rxq->fl; 1605 fl_hw_cidx = fl->hw_cidx; /* stable snapshot */ 1606 1607 #if defined(INET) || defined(INET6) 1608 if (iq->flags & IQ_ADJ_CREDIT) { 1609 MPASS(sort_before_lro(lro)); 1610 iq->flags &= ~IQ_ADJ_CREDIT; 1611 if ((d->rsp.u.type_gen & F_RSPD_GEN) != iq->gen) { 1612 tcp_lro_flush_all(lro); 1613 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(1) | 1614 V_INGRESSQID((u32)iq->cntxt_id) | 1615 V_SEINTARM(iq->intr_params)); 1616 return (0); 1617 } 1618 ndescs = 1; 1619 } 1620 #else 1621 MPASS((iq->flags & IQ_ADJ_CREDIT) == 0); 1622 #endif 1623 1624 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) { 1625 1626 rmb(); 1627 1628 refill = 0; 1629 m0 = NULL; 1630 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen); 1631 lq = be32toh(d->rsp.pldbuflen_qid); 1632 1633 switch (rsp_type) { 1634 case X_RSPD_TYPE_FLBUF: 1635 1636 m0 = get_fl_payload(sc, fl, lq); 1637 if (__predict_false(m0 == NULL)) 1638 goto out; 1639 refill = IDXDIFF(fl->hw_cidx, fl_hw_cidx, fl->sidx) > 2; 1640 1641 if (iq->flags & IQ_RX_TIMESTAMP) { 1642 /* 1643 * Fill up rcv_tstmp but do not set M_TSTMP. 1644 * rcv_tstmp is not in the format that the 1645 * kernel expects and we don't want to mislead 1646 * it. For now this is only for custom code 1647 * that knows how to interpret cxgbe's stamp. 1648 */ 1649 m0->m_pkthdr.rcv_tstmp = 1650 last_flit_to_ns(sc, d->rsp.u.last_flit); 1651 #ifdef notyet 1652 m0->m_flags |= M_TSTMP; 1653 #endif 1654 } 1655 1656 /* fall through */ 1657 1658 case X_RSPD_TYPE_CPL: 1659 KASSERT(d->rss.opcode < NUM_CPL_CMDS, 1660 ("%s: bad opcode %02x.", __func__, d->rss.opcode)); 1661 t4_cpl_handler[d->rss.opcode](iq, &d->rss, m0); 1662 break; 1663 1664 case X_RSPD_TYPE_INTR: 1665 1666 /* 1667 * There are 1K interrupt-capable queues (qids 0 1668 * through 1023). A response type indicating a 1669 * forwarded interrupt with a qid >= 1K is an 1670 * iWARP async notification. That is the only 1671 * acceptable indirect interrupt on this queue. 1672 */ 1673 if (__predict_false(lq < 1024)) { 1674 panic("%s: indirect interrupt on iq_fl %p " 1675 "with qid %u", __func__, iq, lq); 1676 } 1677 1678 t4_an_handler(iq, &d->rsp); 1679 break; 1680 1681 default: 1682 KASSERT(0, ("%s: illegal response type %d on iq %p", 1683 __func__, rsp_type, iq)); 1684 log(LOG_ERR, "%s: illegal response type %d on iq %p", 1685 device_get_nameunit(sc->dev), rsp_type, iq); 1686 break; 1687 } 1688 1689 d++; 1690 if (__predict_false(++iq->cidx == iq->sidx)) { 1691 iq->cidx = 0; 1692 iq->gen ^= F_RSPD_GEN; 1693 d = &iq->desc[0]; 1694 } 1695 if (__predict_false(++ndescs == limit)) { 1696 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) | 1697 V_INGRESSQID(iq->cntxt_id) | 1698 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); 1699 ndescs = 0; 1700 1701 #if defined(INET) || defined(INET6) 1702 if (iq->flags & IQ_LRO_ENABLED && 1703 !sort_before_lro(lro) && 1704 sc->lro_timeout != 0) { 1705 tcp_lro_flush_inactive(lro, &lro_timeout); 1706 } 1707 #endif 1708 if (budget) { 1709 FL_LOCK(fl); 1710 refill_fl(sc, fl, 32); 1711 FL_UNLOCK(fl); 1712 1713 return (EINPROGRESS); 1714 } 1715 } 1716 if (refill) { 1717 FL_LOCK(fl); 1718 refill_fl(sc, fl, 32); 1719 FL_UNLOCK(fl); 1720 fl_hw_cidx = fl->hw_cidx; 1721 } 1722 } 1723 out: 1724 #if defined(INET) || defined(INET6) 1725 if (iq->flags & IQ_LRO_ENABLED) { 1726 if (ndescs > 0 && lro->lro_mbuf_count > 8) { 1727 MPASS(sort_before_lro(lro)); 1728 /* hold back one credit and don't flush LRO state */ 1729 iq->flags |= IQ_ADJ_CREDIT; 1730 ndescs--; 1731 } else { 1732 tcp_lro_flush_all(lro); 1733 } 1734 } 1735 #endif 1736 1737 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) | 1738 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params)); 1739 1740 FL_LOCK(fl); 1741 starved = refill_fl(sc, fl, 64); 1742 FL_UNLOCK(fl); 1743 if (__predict_false(starved != 0)) 1744 add_fl_to_sfl(sc, fl); 1745 1746 return (0); 1747 } 1748 1749 static inline int 1750 cl_has_metadata(struct sge_fl *fl, struct cluster_layout *cll) 1751 { 1752 int rc = fl->flags & FL_BUF_PACKING || cll->region1 > 0; 1753 1754 if (rc) 1755 MPASS(cll->region3 >= CL_METADATA_SIZE); 1756 1757 return (rc); 1758 } 1759 1760 static inline struct cluster_metadata * 1761 cl_metadata(struct adapter *sc, struct sge_fl *fl, struct cluster_layout *cll, 1762 caddr_t cl) 1763 { 1764 1765 if (cl_has_metadata(fl, cll)) { 1766 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx]; 1767 1768 return ((struct cluster_metadata *)(cl + swz->size) - 1); 1769 } 1770 return (NULL); 1771 } 1772 1773 static void 1774 rxb_free(struct mbuf *m) 1775 { 1776 uma_zone_t zone = m->m_ext.ext_arg1; 1777 void *cl = m->m_ext.ext_arg2; 1778 1779 uma_zfree(zone, cl); 1780 counter_u64_add(extfree_rels, 1); 1781 } 1782 1783 /* 1784 * The mbuf returned by this function could be allocated from zone_mbuf or 1785 * constructed in spare room in the cluster. 1786 * 1787 * The mbuf carries the payload in one of these ways 1788 * a) frame inside the mbuf (mbuf from zone_mbuf) 1789 * b) m_cljset (for clusters without metadata) zone_mbuf 1790 * c) m_extaddref (cluster with metadata) inline mbuf 1791 * d) m_extaddref (cluster with metadata) zone_mbuf 1792 */ 1793 static struct mbuf * 1794 get_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset, 1795 int remaining) 1796 { 1797 struct mbuf *m; 1798 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 1799 struct cluster_layout *cll = &sd->cll; 1800 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx]; 1801 struct hw_buf_info *hwb = &sc->sge.hw_buf_info[cll->hwidx]; 1802 struct cluster_metadata *clm = cl_metadata(sc, fl, cll, sd->cl); 1803 int len, blen; 1804 caddr_t payload; 1805 1806 blen = hwb->size - fl->rx_offset; /* max possible in this buf */ 1807 len = min(remaining, blen); 1808 payload = sd->cl + cll->region1 + fl->rx_offset; 1809 if (fl->flags & FL_BUF_PACKING) { 1810 const u_int l = fr_offset + len; 1811 const u_int pad = roundup2(l, fl->buf_boundary) - l; 1812 1813 if (fl->rx_offset + len + pad < hwb->size) 1814 blen = len + pad; 1815 MPASS(fl->rx_offset + blen <= hwb->size); 1816 } else { 1817 MPASS(fl->rx_offset == 0); /* not packing */ 1818 } 1819 1820 1821 if (sc->sc_do_rxcopy && len < RX_COPY_THRESHOLD) { 1822 1823 /* 1824 * Copy payload into a freshly allocated mbuf. 1825 */ 1826 1827 m = fr_offset == 0 ? 1828 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA); 1829 if (m == NULL) 1830 return (NULL); 1831 fl->mbuf_allocated++; 1832 1833 /* copy data to mbuf */ 1834 bcopy(payload, mtod(m, caddr_t), len); 1835 1836 } else if (sd->nmbuf * MSIZE < cll->region1) { 1837 1838 /* 1839 * There's spare room in the cluster for an mbuf. Create one 1840 * and associate it with the payload that's in the cluster. 1841 */ 1842 1843 MPASS(clm != NULL); 1844 m = (struct mbuf *)(sd->cl + sd->nmbuf * MSIZE); 1845 /* No bzero required */ 1846 if (m_init(m, M_NOWAIT, MT_DATA, 1847 fr_offset == 0 ? M_PKTHDR | M_NOFREE : M_NOFREE)) 1848 return (NULL); 1849 fl->mbuf_inlined++; 1850 m_extaddref(m, payload, blen, &clm->refcount, rxb_free, 1851 swz->zone, sd->cl); 1852 if (sd->nmbuf++ == 0) 1853 counter_u64_add(extfree_refs, 1); 1854 1855 } else { 1856 1857 /* 1858 * Grab an mbuf from zone_mbuf and associate it with the 1859 * payload in the cluster. 1860 */ 1861 1862 m = fr_offset == 0 ? 1863 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA); 1864 if (m == NULL) 1865 return (NULL); 1866 fl->mbuf_allocated++; 1867 if (clm != NULL) { 1868 m_extaddref(m, payload, blen, &clm->refcount, 1869 rxb_free, swz->zone, sd->cl); 1870 if (sd->nmbuf++ == 0) 1871 counter_u64_add(extfree_refs, 1); 1872 } else { 1873 m_cljset(m, sd->cl, swz->type); 1874 sd->cl = NULL; /* consumed, not a recycle candidate */ 1875 } 1876 } 1877 if (fr_offset == 0) 1878 m->m_pkthdr.len = remaining; 1879 m->m_len = len; 1880 1881 if (fl->flags & FL_BUF_PACKING) { 1882 fl->rx_offset += blen; 1883 MPASS(fl->rx_offset <= hwb->size); 1884 if (fl->rx_offset < hwb->size) 1885 return (m); /* without advancing the cidx */ 1886 } 1887 1888 if (__predict_false(++fl->cidx % 8 == 0)) { 1889 uint16_t cidx = fl->cidx / 8; 1890 1891 if (__predict_false(cidx == fl->sidx)) 1892 fl->cidx = cidx = 0; 1893 fl->hw_cidx = cidx; 1894 } 1895 fl->rx_offset = 0; 1896 1897 return (m); 1898 } 1899 1900 static struct mbuf * 1901 get_fl_payload(struct adapter *sc, struct sge_fl *fl, uint32_t len_newbuf) 1902 { 1903 struct mbuf *m0, *m, **pnext; 1904 u_int remaining; 1905 const u_int total = G_RSPD_LEN(len_newbuf); 1906 1907 if (__predict_false(fl->flags & FL_BUF_RESUME)) { 1908 M_ASSERTPKTHDR(fl->m0); 1909 MPASS(fl->m0->m_pkthdr.len == total); 1910 MPASS(fl->remaining < total); 1911 1912 m0 = fl->m0; 1913 pnext = fl->pnext; 1914 remaining = fl->remaining; 1915 fl->flags &= ~FL_BUF_RESUME; 1916 goto get_segment; 1917 } 1918 1919 if (fl->rx_offset > 0 && len_newbuf & F_RSPD_NEWBUF) { 1920 fl->rx_offset = 0; 1921 if (__predict_false(++fl->cidx % 8 == 0)) { 1922 uint16_t cidx = fl->cidx / 8; 1923 1924 if (__predict_false(cidx == fl->sidx)) 1925 fl->cidx = cidx = 0; 1926 fl->hw_cidx = cidx; 1927 } 1928 } 1929 1930 /* 1931 * Payload starts at rx_offset in the current hw buffer. Its length is 1932 * 'len' and it may span multiple hw buffers. 1933 */ 1934 1935 m0 = get_scatter_segment(sc, fl, 0, total); 1936 if (m0 == NULL) 1937 return (NULL); 1938 remaining = total - m0->m_len; 1939 pnext = &m0->m_next; 1940 while (remaining > 0) { 1941 get_segment: 1942 MPASS(fl->rx_offset == 0); 1943 m = get_scatter_segment(sc, fl, total - remaining, remaining); 1944 if (__predict_false(m == NULL)) { 1945 fl->m0 = m0; 1946 fl->pnext = pnext; 1947 fl->remaining = remaining; 1948 fl->flags |= FL_BUF_RESUME; 1949 return (NULL); 1950 } 1951 *pnext = m; 1952 pnext = &m->m_next; 1953 remaining -= m->m_len; 1954 } 1955 *pnext = NULL; 1956 1957 M_ASSERTPKTHDR(m0); 1958 return (m0); 1959 } 1960 1961 static int 1962 t4_eth_rx(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0) 1963 { 1964 struct sge_rxq *rxq = iq_to_rxq(iq); 1965 struct ifnet *ifp = rxq->ifp; 1966 struct adapter *sc = iq->adapter; 1967 const struct cpl_rx_pkt *cpl = (const void *)(rss + 1); 1968 #if defined(INET) || defined(INET6) 1969 struct lro_ctrl *lro = &rxq->lro; 1970 #endif 1971 static const int sw_hashtype[4][2] = { 1972 {M_HASHTYPE_NONE, M_HASHTYPE_NONE}, 1973 {M_HASHTYPE_RSS_IPV4, M_HASHTYPE_RSS_IPV6}, 1974 {M_HASHTYPE_RSS_TCP_IPV4, M_HASHTYPE_RSS_TCP_IPV6}, 1975 {M_HASHTYPE_RSS_UDP_IPV4, M_HASHTYPE_RSS_UDP_IPV6}, 1976 }; 1977 1978 KASSERT(m0 != NULL, ("%s: no payload with opcode %02x", __func__, 1979 rss->opcode)); 1980 1981 m0->m_pkthdr.len -= sc->params.sge.fl_pktshift; 1982 m0->m_len -= sc->params.sge.fl_pktshift; 1983 m0->m_data += sc->params.sge.fl_pktshift; 1984 1985 m0->m_pkthdr.rcvif = ifp; 1986 M_HASHTYPE_SET(m0, sw_hashtype[rss->hash_type][rss->ipv6]); 1987 m0->m_pkthdr.flowid = be32toh(rss->hash_val); 1988 1989 if (cpl->csum_calc && !(cpl->err_vec & sc->params.tp.err_vec_mask)) { 1990 if (ifp->if_capenable & IFCAP_RXCSUM && 1991 cpl->l2info & htobe32(F_RXF_IP)) { 1992 m0->m_pkthdr.csum_flags = (CSUM_IP_CHECKED | 1993 CSUM_IP_VALID | CSUM_DATA_VALID | CSUM_PSEUDO_HDR); 1994 rxq->rxcsum++; 1995 } else if (ifp->if_capenable & IFCAP_RXCSUM_IPV6 && 1996 cpl->l2info & htobe32(F_RXF_IP6)) { 1997 m0->m_pkthdr.csum_flags = (CSUM_DATA_VALID_IPV6 | 1998 CSUM_PSEUDO_HDR); 1999 rxq->rxcsum++; 2000 } 2001 2002 if (__predict_false(cpl->ip_frag)) 2003 m0->m_pkthdr.csum_data = be16toh(cpl->csum); 2004 else 2005 m0->m_pkthdr.csum_data = 0xffff; 2006 } 2007 2008 if (cpl->vlan_ex) { 2009 m0->m_pkthdr.ether_vtag = be16toh(cpl->vlan); 2010 m0->m_flags |= M_VLANTAG; 2011 rxq->vlan_extraction++; 2012 } 2013 2014 #if defined(INET) || defined(INET6) 2015 if (iq->flags & IQ_LRO_ENABLED) { 2016 if (sort_before_lro(lro)) { 2017 tcp_lro_queue_mbuf(lro, m0); 2018 return (0); /* queued for sort, then LRO */ 2019 } 2020 if (tcp_lro_rx(lro, m0, 0) == 0) 2021 return (0); /* queued for LRO */ 2022 } 2023 #endif 2024 ifp->if_input(ifp, m0); 2025 2026 return (0); 2027 } 2028 2029 /* 2030 * Must drain the wrq or make sure that someone else will. 2031 */ 2032 static void 2033 wrq_tx_drain(void *arg, int n) 2034 { 2035 struct sge_wrq *wrq = arg; 2036 struct sge_eq *eq = &wrq->eq; 2037 2038 EQ_LOCK(eq); 2039 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 2040 drain_wrq_wr_list(wrq->adapter, wrq); 2041 EQ_UNLOCK(eq); 2042 } 2043 2044 static void 2045 drain_wrq_wr_list(struct adapter *sc, struct sge_wrq *wrq) 2046 { 2047 struct sge_eq *eq = &wrq->eq; 2048 u_int available, dbdiff; /* # of hardware descriptors */ 2049 u_int n; 2050 struct wrqe *wr; 2051 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */ 2052 2053 EQ_LOCK_ASSERT_OWNED(eq); 2054 MPASS(TAILQ_EMPTY(&wrq->incomplete_wrs)); 2055 wr = STAILQ_FIRST(&wrq->wr_list); 2056 MPASS(wr != NULL); /* Must be called with something useful to do */ 2057 MPASS(eq->pidx == eq->dbidx); 2058 dbdiff = 0; 2059 2060 do { 2061 eq->cidx = read_hw_cidx(eq); 2062 if (eq->pidx == eq->cidx) 2063 available = eq->sidx - 1; 2064 else 2065 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2066 2067 MPASS(wr->wrq == wrq); 2068 n = howmany(wr->wr_len, EQ_ESIZE); 2069 if (available < n) 2070 break; 2071 2072 dst = (void *)&eq->desc[eq->pidx]; 2073 if (__predict_true(eq->sidx - eq->pidx > n)) { 2074 /* Won't wrap, won't end exactly at the status page. */ 2075 bcopy(&wr->wr[0], dst, wr->wr_len); 2076 eq->pidx += n; 2077 } else { 2078 int first_portion = (eq->sidx - eq->pidx) * EQ_ESIZE; 2079 2080 bcopy(&wr->wr[0], dst, first_portion); 2081 if (wr->wr_len > first_portion) { 2082 bcopy(&wr->wr[first_portion], &eq->desc[0], 2083 wr->wr_len - first_portion); 2084 } 2085 eq->pidx = n - (eq->sidx - eq->pidx); 2086 } 2087 wrq->tx_wrs_copied++; 2088 2089 if (available < eq->sidx / 4 && 2090 atomic_cmpset_int(&eq->equiq, 0, 1)) { 2091 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ | 2092 F_FW_WR_EQUEQ); 2093 eq->equeqidx = eq->pidx; 2094 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 32) { 2095 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ); 2096 eq->equeqidx = eq->pidx; 2097 } 2098 2099 dbdiff += n; 2100 if (dbdiff >= 16) { 2101 ring_eq_db(sc, eq, dbdiff); 2102 dbdiff = 0; 2103 } 2104 2105 STAILQ_REMOVE_HEAD(&wrq->wr_list, link); 2106 free_wrqe(wr); 2107 MPASS(wrq->nwr_pending > 0); 2108 wrq->nwr_pending--; 2109 MPASS(wrq->ndesc_needed >= n); 2110 wrq->ndesc_needed -= n; 2111 } while ((wr = STAILQ_FIRST(&wrq->wr_list)) != NULL); 2112 2113 if (dbdiff) 2114 ring_eq_db(sc, eq, dbdiff); 2115 } 2116 2117 /* 2118 * Doesn't fail. Holds on to work requests it can't send right away. 2119 */ 2120 void 2121 t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, struct wrqe *wr) 2122 { 2123 #ifdef INVARIANTS 2124 struct sge_eq *eq = &wrq->eq; 2125 #endif 2126 2127 EQ_LOCK_ASSERT_OWNED(eq); 2128 MPASS(wr != NULL); 2129 MPASS(wr->wr_len > 0 && wr->wr_len <= SGE_MAX_WR_LEN); 2130 MPASS((wr->wr_len & 0x7) == 0); 2131 2132 STAILQ_INSERT_TAIL(&wrq->wr_list, wr, link); 2133 wrq->nwr_pending++; 2134 wrq->ndesc_needed += howmany(wr->wr_len, EQ_ESIZE); 2135 2136 if (!TAILQ_EMPTY(&wrq->incomplete_wrs)) 2137 return; /* commit_wrq_wr will drain wr_list as well. */ 2138 2139 drain_wrq_wr_list(sc, wrq); 2140 2141 /* Doorbell must have caught up to the pidx. */ 2142 MPASS(eq->pidx == eq->dbidx); 2143 } 2144 2145 void 2146 t4_update_fl_bufsize(struct ifnet *ifp) 2147 { 2148 struct vi_info *vi = ifp->if_softc; 2149 struct adapter *sc = vi->pi->adapter; 2150 struct sge_rxq *rxq; 2151 #ifdef TCP_OFFLOAD 2152 struct sge_ofld_rxq *ofld_rxq; 2153 #endif 2154 struct sge_fl *fl; 2155 int i, maxp, mtu = ifp->if_mtu; 2156 2157 maxp = mtu_to_max_payload(sc, mtu, 0); 2158 for_each_rxq(vi, i, rxq) { 2159 fl = &rxq->fl; 2160 2161 FL_LOCK(fl); 2162 find_best_refill_source(sc, fl, maxp); 2163 FL_UNLOCK(fl); 2164 } 2165 #ifdef TCP_OFFLOAD 2166 maxp = mtu_to_max_payload(sc, mtu, 1); 2167 for_each_ofld_rxq(vi, i, ofld_rxq) { 2168 fl = &ofld_rxq->fl; 2169 2170 FL_LOCK(fl); 2171 find_best_refill_source(sc, fl, maxp); 2172 FL_UNLOCK(fl); 2173 } 2174 #endif 2175 } 2176 2177 static inline int 2178 mbuf_nsegs(struct mbuf *m) 2179 { 2180 2181 M_ASSERTPKTHDR(m); 2182 KASSERT(m->m_pkthdr.l5hlen > 0, 2183 ("%s: mbuf %p missing information on # of segments.", __func__, m)); 2184 2185 return (m->m_pkthdr.l5hlen); 2186 } 2187 2188 static inline void 2189 set_mbuf_nsegs(struct mbuf *m, uint8_t nsegs) 2190 { 2191 2192 M_ASSERTPKTHDR(m); 2193 m->m_pkthdr.l5hlen = nsegs; 2194 } 2195 2196 static inline int 2197 mbuf_len16(struct mbuf *m) 2198 { 2199 int n; 2200 2201 M_ASSERTPKTHDR(m); 2202 n = m->m_pkthdr.PH_loc.eight[0]; 2203 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16); 2204 2205 return (n); 2206 } 2207 2208 static inline void 2209 set_mbuf_len16(struct mbuf *m, uint8_t len16) 2210 { 2211 2212 M_ASSERTPKTHDR(m); 2213 m->m_pkthdr.PH_loc.eight[0] = len16; 2214 } 2215 2216 #ifdef RATELIMIT 2217 static inline int 2218 mbuf_eo_nsegs(struct mbuf *m) 2219 { 2220 2221 M_ASSERTPKTHDR(m); 2222 return (m->m_pkthdr.PH_loc.eight[1]); 2223 } 2224 2225 static inline void 2226 set_mbuf_eo_nsegs(struct mbuf *m, uint8_t nsegs) 2227 { 2228 2229 M_ASSERTPKTHDR(m); 2230 m->m_pkthdr.PH_loc.eight[1] = nsegs; 2231 } 2232 2233 static inline int 2234 mbuf_eo_len16(struct mbuf *m) 2235 { 2236 int n; 2237 2238 M_ASSERTPKTHDR(m); 2239 n = m->m_pkthdr.PH_loc.eight[2]; 2240 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16); 2241 2242 return (n); 2243 } 2244 2245 static inline void 2246 set_mbuf_eo_len16(struct mbuf *m, uint8_t len16) 2247 { 2248 2249 M_ASSERTPKTHDR(m); 2250 m->m_pkthdr.PH_loc.eight[2] = len16; 2251 } 2252 2253 static inline int 2254 mbuf_eo_tsclk_tsoff(struct mbuf *m) 2255 { 2256 2257 M_ASSERTPKTHDR(m); 2258 return (m->m_pkthdr.PH_loc.eight[3]); 2259 } 2260 2261 static inline void 2262 set_mbuf_eo_tsclk_tsoff(struct mbuf *m, uint8_t tsclk_tsoff) 2263 { 2264 2265 M_ASSERTPKTHDR(m); 2266 m->m_pkthdr.PH_loc.eight[3] = tsclk_tsoff; 2267 } 2268 2269 static inline int 2270 needs_eo(struct mbuf *m) 2271 { 2272 2273 return (m->m_pkthdr.snd_tag != NULL); 2274 } 2275 #endif 2276 2277 static inline int 2278 needs_tso(struct mbuf *m) 2279 { 2280 2281 M_ASSERTPKTHDR(m); 2282 2283 return (m->m_pkthdr.csum_flags & CSUM_TSO); 2284 } 2285 2286 static inline int 2287 needs_l3_csum(struct mbuf *m) 2288 { 2289 2290 M_ASSERTPKTHDR(m); 2291 2292 return (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TSO)); 2293 } 2294 2295 static inline int 2296 needs_l4_csum(struct mbuf *m) 2297 { 2298 2299 M_ASSERTPKTHDR(m); 2300 2301 return (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_UDP_IPV6 | 2302 CSUM_TCP_IPV6 | CSUM_TSO)); 2303 } 2304 2305 static inline int 2306 needs_tcp_csum(struct mbuf *m) 2307 { 2308 2309 M_ASSERTPKTHDR(m); 2310 return (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_TCP_IPV6 | CSUM_TSO)); 2311 } 2312 2313 #ifdef RATELIMIT 2314 static inline int 2315 needs_udp_csum(struct mbuf *m) 2316 { 2317 2318 M_ASSERTPKTHDR(m); 2319 return (m->m_pkthdr.csum_flags & (CSUM_UDP | CSUM_UDP_IPV6)); 2320 } 2321 #endif 2322 2323 static inline int 2324 needs_vlan_insertion(struct mbuf *m) 2325 { 2326 2327 M_ASSERTPKTHDR(m); 2328 2329 return (m->m_flags & M_VLANTAG); 2330 } 2331 2332 static void * 2333 m_advance(struct mbuf **pm, int *poffset, int len) 2334 { 2335 struct mbuf *m = *pm; 2336 int offset = *poffset; 2337 uintptr_t p = 0; 2338 2339 MPASS(len > 0); 2340 2341 for (;;) { 2342 if (offset + len < m->m_len) { 2343 offset += len; 2344 p = mtod(m, uintptr_t) + offset; 2345 break; 2346 } 2347 len -= m->m_len - offset; 2348 m = m->m_next; 2349 offset = 0; 2350 MPASS(m != NULL); 2351 } 2352 *poffset = offset; 2353 *pm = m; 2354 return ((void *)p); 2355 } 2356 2357 /* 2358 * Can deal with empty mbufs in the chain that have m_len = 0, but the chain 2359 * must have at least one mbuf that's not empty. It is possible for this 2360 * routine to return 0 if skip accounts for all the contents of the mbuf chain. 2361 */ 2362 static inline int 2363 count_mbuf_nsegs(struct mbuf *m, int skip) 2364 { 2365 vm_paddr_t lastb, next; 2366 vm_offset_t va; 2367 int len, nsegs; 2368 2369 M_ASSERTPKTHDR(m); 2370 MPASS(m->m_pkthdr.len > 0); 2371 MPASS(m->m_pkthdr.len >= skip); 2372 2373 nsegs = 0; 2374 lastb = 0; 2375 for (; m; m = m->m_next) { 2376 2377 len = m->m_len; 2378 if (__predict_false(len == 0)) 2379 continue; 2380 if (skip >= len) { 2381 skip -= len; 2382 continue; 2383 } 2384 va = mtod(m, vm_offset_t) + skip; 2385 len -= skip; 2386 skip = 0; 2387 next = pmap_kextract(va); 2388 nsegs += sglist_count((void *)(uintptr_t)va, len); 2389 if (lastb + 1 == next) 2390 nsegs--; 2391 lastb = pmap_kextract(va + len - 1); 2392 } 2393 2394 return (nsegs); 2395 } 2396 2397 /* 2398 * Analyze the mbuf to determine its tx needs. The mbuf passed in may change: 2399 * a) caller can assume it's been freed if this function returns with an error. 2400 * b) it may get defragged up if the gather list is too long for the hardware. 2401 */ 2402 int 2403 parse_pkt(struct adapter *sc, struct mbuf **mp) 2404 { 2405 struct mbuf *m0 = *mp, *m; 2406 int rc, nsegs, defragged = 0, offset; 2407 struct ether_header *eh; 2408 void *l3hdr; 2409 #if defined(INET) || defined(INET6) 2410 struct tcphdr *tcp; 2411 #endif 2412 uint16_t eh_type; 2413 2414 M_ASSERTPKTHDR(m0); 2415 if (__predict_false(m0->m_pkthdr.len < ETHER_HDR_LEN)) { 2416 rc = EINVAL; 2417 fail: 2418 m_freem(m0); 2419 *mp = NULL; 2420 return (rc); 2421 } 2422 restart: 2423 /* 2424 * First count the number of gather list segments in the payload. 2425 * Defrag the mbuf if nsegs exceeds the hardware limit. 2426 */ 2427 M_ASSERTPKTHDR(m0); 2428 MPASS(m0->m_pkthdr.len > 0); 2429 nsegs = count_mbuf_nsegs(m0, 0); 2430 if (nsegs > (needs_tso(m0) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS)) { 2431 if (defragged++ > 0 || (m = m_defrag(m0, M_NOWAIT)) == NULL) { 2432 rc = EFBIG; 2433 goto fail; 2434 } 2435 *mp = m0 = m; /* update caller's copy after defrag */ 2436 goto restart; 2437 } 2438 2439 if (__predict_false(nsegs > 2 && m0->m_pkthdr.len <= MHLEN)) { 2440 m0 = m_pullup(m0, m0->m_pkthdr.len); 2441 if (m0 == NULL) { 2442 /* Should have left well enough alone. */ 2443 rc = EFBIG; 2444 goto fail; 2445 } 2446 *mp = m0; /* update caller's copy after pullup */ 2447 goto restart; 2448 } 2449 set_mbuf_nsegs(m0, nsegs); 2450 if (sc->flags & IS_VF) 2451 set_mbuf_len16(m0, txpkt_vm_len16(nsegs, needs_tso(m0))); 2452 else 2453 set_mbuf_len16(m0, txpkt_len16(nsegs, needs_tso(m0))); 2454 2455 #ifdef RATELIMIT 2456 /* 2457 * Ethofld is limited to TCP and UDP for now, and only when L4 hw 2458 * checksumming is enabled. needs_l4_csum happens to check for all the 2459 * right things. 2460 */ 2461 if (__predict_false(needs_eo(m0) && !needs_l4_csum(m0))) 2462 m0->m_pkthdr.snd_tag = NULL; 2463 #endif 2464 2465 if (!needs_tso(m0) && 2466 #ifdef RATELIMIT 2467 !needs_eo(m0) && 2468 #endif 2469 !(sc->flags & IS_VF && (needs_l3_csum(m0) || needs_l4_csum(m0)))) 2470 return (0); 2471 2472 m = m0; 2473 eh = mtod(m, struct ether_header *); 2474 eh_type = ntohs(eh->ether_type); 2475 if (eh_type == ETHERTYPE_VLAN) { 2476 struct ether_vlan_header *evh = (void *)eh; 2477 2478 eh_type = ntohs(evh->evl_proto); 2479 m0->m_pkthdr.l2hlen = sizeof(*evh); 2480 } else 2481 m0->m_pkthdr.l2hlen = sizeof(*eh); 2482 2483 offset = 0; 2484 l3hdr = m_advance(&m, &offset, m0->m_pkthdr.l2hlen); 2485 2486 switch (eh_type) { 2487 #ifdef INET6 2488 case ETHERTYPE_IPV6: 2489 { 2490 struct ip6_hdr *ip6 = l3hdr; 2491 2492 MPASS(!needs_tso(m0) || ip6->ip6_nxt == IPPROTO_TCP); 2493 2494 m0->m_pkthdr.l3hlen = sizeof(*ip6); 2495 break; 2496 } 2497 #endif 2498 #ifdef INET 2499 case ETHERTYPE_IP: 2500 { 2501 struct ip *ip = l3hdr; 2502 2503 m0->m_pkthdr.l3hlen = ip->ip_hl * 4; 2504 break; 2505 } 2506 #endif 2507 default: 2508 panic("%s: ethertype 0x%04x unknown. if_cxgbe must be compiled" 2509 " with the same INET/INET6 options as the kernel.", 2510 __func__, eh_type); 2511 } 2512 2513 #if defined(INET) || defined(INET6) 2514 if (needs_tcp_csum(m0)) { 2515 tcp = m_advance(&m, &offset, m0->m_pkthdr.l3hlen); 2516 m0->m_pkthdr.l4hlen = tcp->th_off * 4; 2517 #ifdef RATELIMIT 2518 if (tsclk >= 0 && *(uint32_t *)(tcp + 1) == ntohl(0x0101080a)) { 2519 set_mbuf_eo_tsclk_tsoff(m0, 2520 V_FW_ETH_TX_EO_WR_TSCLK(tsclk) | 2521 V_FW_ETH_TX_EO_WR_TSOFF(sizeof(*tcp) / 2 + 1)); 2522 } else 2523 set_mbuf_eo_tsclk_tsoff(m0, 0); 2524 } else if (needs_udp_csum(m)) { 2525 m0->m_pkthdr.l4hlen = sizeof(struct udphdr); 2526 #endif 2527 } 2528 #ifdef RATELIMIT 2529 if (needs_eo(m0)) { 2530 u_int immhdrs; 2531 2532 /* EO WRs have the headers in the WR and not the GL. */ 2533 immhdrs = m0->m_pkthdr.l2hlen + m0->m_pkthdr.l3hlen + 2534 m0->m_pkthdr.l4hlen; 2535 nsegs = count_mbuf_nsegs(m0, immhdrs); 2536 set_mbuf_eo_nsegs(m0, nsegs); 2537 set_mbuf_eo_len16(m0, 2538 txpkt_eo_len16(nsegs, immhdrs, needs_tso(m0))); 2539 } 2540 #endif 2541 #endif 2542 MPASS(m0 == *mp); 2543 return (0); 2544 } 2545 2546 void * 2547 start_wrq_wr(struct sge_wrq *wrq, int len16, struct wrq_cookie *cookie) 2548 { 2549 struct sge_eq *eq = &wrq->eq; 2550 struct adapter *sc = wrq->adapter; 2551 int ndesc, available; 2552 struct wrqe *wr; 2553 void *w; 2554 2555 MPASS(len16 > 0); 2556 ndesc = howmany(len16, EQ_ESIZE / 16); 2557 MPASS(ndesc > 0 && ndesc <= SGE_MAX_WR_NDESC); 2558 2559 EQ_LOCK(eq); 2560 2561 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 2562 drain_wrq_wr_list(sc, wrq); 2563 2564 if (!STAILQ_EMPTY(&wrq->wr_list)) { 2565 slowpath: 2566 EQ_UNLOCK(eq); 2567 wr = alloc_wrqe(len16 * 16, wrq); 2568 if (__predict_false(wr == NULL)) 2569 return (NULL); 2570 cookie->pidx = -1; 2571 cookie->ndesc = ndesc; 2572 return (&wr->wr); 2573 } 2574 2575 eq->cidx = read_hw_cidx(eq); 2576 if (eq->pidx == eq->cidx) 2577 available = eq->sidx - 1; 2578 else 2579 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2580 if (available < ndesc) 2581 goto slowpath; 2582 2583 cookie->pidx = eq->pidx; 2584 cookie->ndesc = ndesc; 2585 TAILQ_INSERT_TAIL(&wrq->incomplete_wrs, cookie, link); 2586 2587 w = &eq->desc[eq->pidx]; 2588 IDXINCR(eq->pidx, ndesc, eq->sidx); 2589 if (__predict_false(cookie->pidx + ndesc > eq->sidx)) { 2590 w = &wrq->ss[0]; 2591 wrq->ss_pidx = cookie->pidx; 2592 wrq->ss_len = len16 * 16; 2593 } 2594 2595 EQ_UNLOCK(eq); 2596 2597 return (w); 2598 } 2599 2600 void 2601 commit_wrq_wr(struct sge_wrq *wrq, void *w, struct wrq_cookie *cookie) 2602 { 2603 struct sge_eq *eq = &wrq->eq; 2604 struct adapter *sc = wrq->adapter; 2605 int ndesc, pidx; 2606 struct wrq_cookie *prev, *next; 2607 2608 if (cookie->pidx == -1) { 2609 struct wrqe *wr = __containerof(w, struct wrqe, wr); 2610 2611 t4_wrq_tx(sc, wr); 2612 return; 2613 } 2614 2615 if (__predict_false(w == &wrq->ss[0])) { 2616 int n = (eq->sidx - wrq->ss_pidx) * EQ_ESIZE; 2617 2618 MPASS(wrq->ss_len > n); /* WR had better wrap around. */ 2619 bcopy(&wrq->ss[0], &eq->desc[wrq->ss_pidx], n); 2620 bcopy(&wrq->ss[n], &eq->desc[0], wrq->ss_len - n); 2621 wrq->tx_wrs_ss++; 2622 } else 2623 wrq->tx_wrs_direct++; 2624 2625 EQ_LOCK(eq); 2626 ndesc = cookie->ndesc; /* Can be more than SGE_MAX_WR_NDESC here. */ 2627 pidx = cookie->pidx; 2628 MPASS(pidx >= 0 && pidx < eq->sidx); 2629 prev = TAILQ_PREV(cookie, wrq_incomplete_wrs, link); 2630 next = TAILQ_NEXT(cookie, link); 2631 if (prev == NULL) { 2632 MPASS(pidx == eq->dbidx); 2633 if (next == NULL || ndesc >= 16) { 2634 int available; 2635 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */ 2636 2637 /* 2638 * Note that the WR via which we'll request tx updates 2639 * is at pidx and not eq->pidx, which has moved on 2640 * already. 2641 */ 2642 dst = (void *)&eq->desc[pidx]; 2643 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2644 if (available < eq->sidx / 4 && 2645 atomic_cmpset_int(&eq->equiq, 0, 1)) { 2646 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ | 2647 F_FW_WR_EQUEQ); 2648 eq->equeqidx = pidx; 2649 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 32) { 2650 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ); 2651 eq->equeqidx = pidx; 2652 } 2653 2654 ring_eq_db(wrq->adapter, eq, ndesc); 2655 } else { 2656 MPASS(IDXDIFF(next->pidx, pidx, eq->sidx) == ndesc); 2657 next->pidx = pidx; 2658 next->ndesc += ndesc; 2659 } 2660 } else { 2661 MPASS(IDXDIFF(pidx, prev->pidx, eq->sidx) == prev->ndesc); 2662 prev->ndesc += ndesc; 2663 } 2664 TAILQ_REMOVE(&wrq->incomplete_wrs, cookie, link); 2665 2666 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 2667 drain_wrq_wr_list(sc, wrq); 2668 2669 #ifdef INVARIANTS 2670 if (TAILQ_EMPTY(&wrq->incomplete_wrs)) { 2671 /* Doorbell must have caught up to the pidx. */ 2672 MPASS(wrq->eq.pidx == wrq->eq.dbidx); 2673 } 2674 #endif 2675 EQ_UNLOCK(eq); 2676 } 2677 2678 static u_int 2679 can_resume_eth_tx(struct mp_ring *r) 2680 { 2681 struct sge_eq *eq = r->cookie; 2682 2683 return (total_available_tx_desc(eq) > eq->sidx / 8); 2684 } 2685 2686 static inline int 2687 cannot_use_txpkts(struct mbuf *m) 2688 { 2689 /* maybe put a GL limit too, to avoid silliness? */ 2690 2691 return (needs_tso(m)); 2692 } 2693 2694 static inline int 2695 discard_tx(struct sge_eq *eq) 2696 { 2697 2698 return ((eq->flags & (EQ_ENABLED | EQ_QFLUSH)) != EQ_ENABLED); 2699 } 2700 2701 /* 2702 * r->items[cidx] to r->items[pidx], with a wraparound at r->size, are ready to 2703 * be consumed. Return the actual number consumed. 0 indicates a stall. 2704 */ 2705 static u_int 2706 eth_tx(struct mp_ring *r, u_int cidx, u_int pidx) 2707 { 2708 struct sge_txq *txq = r->cookie; 2709 struct sge_eq *eq = &txq->eq; 2710 struct ifnet *ifp = txq->ifp; 2711 struct vi_info *vi = ifp->if_softc; 2712 struct port_info *pi = vi->pi; 2713 struct adapter *sc = pi->adapter; 2714 u_int total, remaining; /* # of packets */ 2715 u_int available, dbdiff; /* # of hardware descriptors */ 2716 u_int n, next_cidx; 2717 struct mbuf *m0, *tail; 2718 struct txpkts txp; 2719 struct fw_eth_tx_pkts_wr *wr; /* any fw WR struct will do */ 2720 2721 remaining = IDXDIFF(pidx, cidx, r->size); 2722 MPASS(remaining > 0); /* Must not be called without work to do. */ 2723 total = 0; 2724 2725 TXQ_LOCK(txq); 2726 if (__predict_false(discard_tx(eq))) { 2727 while (cidx != pidx) { 2728 m0 = r->items[cidx]; 2729 m_freem(m0); 2730 if (++cidx == r->size) 2731 cidx = 0; 2732 } 2733 reclaim_tx_descs(txq, 2048); 2734 total = remaining; 2735 goto done; 2736 } 2737 2738 /* How many hardware descriptors do we have readily available. */ 2739 if (eq->pidx == eq->cidx) 2740 available = eq->sidx - 1; 2741 else 2742 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2743 dbdiff = IDXDIFF(eq->pidx, eq->dbidx, eq->sidx); 2744 2745 while (remaining > 0) { 2746 2747 m0 = r->items[cidx]; 2748 M_ASSERTPKTHDR(m0); 2749 MPASS(m0->m_nextpkt == NULL); 2750 2751 if (available < SGE_MAX_WR_NDESC) { 2752 available += reclaim_tx_descs(txq, 64); 2753 if (available < howmany(mbuf_len16(m0), EQ_ESIZE / 16)) 2754 break; /* out of descriptors */ 2755 } 2756 2757 next_cidx = cidx + 1; 2758 if (__predict_false(next_cidx == r->size)) 2759 next_cidx = 0; 2760 2761 wr = (void *)&eq->desc[eq->pidx]; 2762 if (sc->flags & IS_VF) { 2763 total++; 2764 remaining--; 2765 ETHER_BPF_MTAP(ifp, m0); 2766 n = write_txpkt_vm_wr(sc, txq, (void *)wr, m0, 2767 available); 2768 } else if (remaining > 1 && 2769 try_txpkts(m0, r->items[next_cidx], &txp, available) == 0) { 2770 2771 /* pkts at cidx, next_cidx should both be in txp. */ 2772 MPASS(txp.npkt == 2); 2773 tail = r->items[next_cidx]; 2774 MPASS(tail->m_nextpkt == NULL); 2775 ETHER_BPF_MTAP(ifp, m0); 2776 ETHER_BPF_MTAP(ifp, tail); 2777 m0->m_nextpkt = tail; 2778 2779 if (__predict_false(++next_cidx == r->size)) 2780 next_cidx = 0; 2781 2782 while (next_cidx != pidx) { 2783 if (add_to_txpkts(r->items[next_cidx], &txp, 2784 available) != 0) 2785 break; 2786 tail->m_nextpkt = r->items[next_cidx]; 2787 tail = tail->m_nextpkt; 2788 ETHER_BPF_MTAP(ifp, tail); 2789 if (__predict_false(++next_cidx == r->size)) 2790 next_cidx = 0; 2791 } 2792 2793 n = write_txpkts_wr(txq, wr, m0, &txp, available); 2794 total += txp.npkt; 2795 remaining -= txp.npkt; 2796 } else { 2797 total++; 2798 remaining--; 2799 ETHER_BPF_MTAP(ifp, m0); 2800 n = write_txpkt_wr(txq, (void *)wr, m0, available); 2801 } 2802 MPASS(n >= 1 && n <= available && n <= SGE_MAX_WR_NDESC); 2803 2804 available -= n; 2805 dbdiff += n; 2806 IDXINCR(eq->pidx, n, eq->sidx); 2807 2808 if (total_available_tx_desc(eq) < eq->sidx / 4 && 2809 atomic_cmpset_int(&eq->equiq, 0, 1)) { 2810 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ | 2811 F_FW_WR_EQUEQ); 2812 eq->equeqidx = eq->pidx; 2813 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 32) { 2814 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ); 2815 eq->equeqidx = eq->pidx; 2816 } 2817 2818 if (dbdiff >= 16 && remaining >= 4) { 2819 ring_eq_db(sc, eq, dbdiff); 2820 available += reclaim_tx_descs(txq, 4 * dbdiff); 2821 dbdiff = 0; 2822 } 2823 2824 cidx = next_cidx; 2825 } 2826 if (dbdiff != 0) { 2827 ring_eq_db(sc, eq, dbdiff); 2828 reclaim_tx_descs(txq, 32); 2829 } 2830 done: 2831 TXQ_UNLOCK(txq); 2832 2833 return (total); 2834 } 2835 2836 static inline void 2837 init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int pktc_idx, 2838 int qsize) 2839 { 2840 2841 KASSERT(tmr_idx >= 0 && tmr_idx < SGE_NTIMERS, 2842 ("%s: bad tmr_idx %d", __func__, tmr_idx)); 2843 KASSERT(pktc_idx < SGE_NCOUNTERS, /* -ve is ok, means don't use */ 2844 ("%s: bad pktc_idx %d", __func__, pktc_idx)); 2845 2846 iq->flags = 0; 2847 iq->adapter = sc; 2848 iq->intr_params = V_QINTR_TIMER_IDX(tmr_idx); 2849 iq->intr_pktc_idx = SGE_NCOUNTERS - 1; 2850 if (pktc_idx >= 0) { 2851 iq->intr_params |= F_QINTR_CNT_EN; 2852 iq->intr_pktc_idx = pktc_idx; 2853 } 2854 iq->qsize = roundup2(qsize, 16); /* See FW_IQ_CMD/iqsize */ 2855 iq->sidx = iq->qsize - sc->params.sge.spg_len / IQ_ESIZE; 2856 } 2857 2858 static inline void 2859 init_fl(struct adapter *sc, struct sge_fl *fl, int qsize, int maxp, char *name) 2860 { 2861 2862 fl->qsize = qsize; 2863 fl->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE; 2864 strlcpy(fl->lockname, name, sizeof(fl->lockname)); 2865 if (sc->flags & BUF_PACKING_OK && 2866 ((!is_t4(sc) && buffer_packing) || /* T5+: enabled unless 0 */ 2867 (is_t4(sc) && buffer_packing == 1)))/* T4: disabled unless 1 */ 2868 fl->flags |= FL_BUF_PACKING; 2869 find_best_refill_source(sc, fl, maxp); 2870 find_safe_refill_source(sc, fl); 2871 } 2872 2873 static inline void 2874 init_eq(struct adapter *sc, struct sge_eq *eq, int eqtype, int qsize, 2875 uint8_t tx_chan, uint16_t iqid, char *name) 2876 { 2877 KASSERT(eqtype <= EQ_TYPEMASK, ("%s: bad qtype %d", __func__, eqtype)); 2878 2879 eq->flags = eqtype & EQ_TYPEMASK; 2880 eq->tx_chan = tx_chan; 2881 eq->iqid = iqid; 2882 eq->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE; 2883 strlcpy(eq->lockname, name, sizeof(eq->lockname)); 2884 } 2885 2886 static int 2887 alloc_ring(struct adapter *sc, size_t len, bus_dma_tag_t *tag, 2888 bus_dmamap_t *map, bus_addr_t *pa, void **va) 2889 { 2890 int rc; 2891 2892 rc = bus_dma_tag_create(sc->dmat, 512, 0, BUS_SPACE_MAXADDR, 2893 BUS_SPACE_MAXADDR, NULL, NULL, len, 1, len, 0, NULL, NULL, tag); 2894 if (rc != 0) { 2895 device_printf(sc->dev, "cannot allocate DMA tag: %d\n", rc); 2896 goto done; 2897 } 2898 2899 rc = bus_dmamem_alloc(*tag, va, 2900 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, map); 2901 if (rc != 0) { 2902 device_printf(sc->dev, "cannot allocate DMA memory: %d\n", rc); 2903 goto done; 2904 } 2905 2906 rc = bus_dmamap_load(*tag, *map, *va, len, oneseg_dma_callback, pa, 0); 2907 if (rc != 0) { 2908 device_printf(sc->dev, "cannot load DMA map: %d\n", rc); 2909 goto done; 2910 } 2911 done: 2912 if (rc) 2913 free_ring(sc, *tag, *map, *pa, *va); 2914 2915 return (rc); 2916 } 2917 2918 static int 2919 free_ring(struct adapter *sc, bus_dma_tag_t tag, bus_dmamap_t map, 2920 bus_addr_t pa, void *va) 2921 { 2922 if (pa) 2923 bus_dmamap_unload(tag, map); 2924 if (va) 2925 bus_dmamem_free(tag, va, map); 2926 if (tag) 2927 bus_dma_tag_destroy(tag); 2928 2929 return (0); 2930 } 2931 2932 /* 2933 * Allocates the ring for an ingress queue and an optional freelist. If the 2934 * freelist is specified it will be allocated and then associated with the 2935 * ingress queue. 2936 * 2937 * Returns errno on failure. Resources allocated up to that point may still be 2938 * allocated. Caller is responsible for cleanup in case this function fails. 2939 * 2940 * If the ingress queue will take interrupts directly then the intr_idx 2941 * specifies the vector, starting from 0. -1 means the interrupts for this 2942 * queue should be forwarded to the fwq. 2943 */ 2944 static int 2945 alloc_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl, 2946 int intr_idx, int cong) 2947 { 2948 int rc, i, cntxt_id; 2949 size_t len; 2950 struct fw_iq_cmd c; 2951 struct port_info *pi = vi->pi; 2952 struct adapter *sc = iq->adapter; 2953 struct sge_params *sp = &sc->params.sge; 2954 __be32 v = 0; 2955 2956 len = iq->qsize * IQ_ESIZE; 2957 rc = alloc_ring(sc, len, &iq->desc_tag, &iq->desc_map, &iq->ba, 2958 (void **)&iq->desc); 2959 if (rc != 0) 2960 return (rc); 2961 2962 bzero(&c, sizeof(c)); 2963 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 2964 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) | 2965 V_FW_IQ_CMD_VFN(0)); 2966 2967 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART | 2968 FW_LEN16(c)); 2969 2970 /* Special handling for firmware event queue */ 2971 if (iq == &sc->sge.fwq) 2972 v |= F_FW_IQ_CMD_IQASYNCH; 2973 2974 if (intr_idx < 0) { 2975 /* Forwarded interrupts, all headed to fwq */ 2976 v |= F_FW_IQ_CMD_IQANDST; 2977 v |= V_FW_IQ_CMD_IQANDSTINDEX(sc->sge.fwq.cntxt_id); 2978 } else { 2979 KASSERT(intr_idx < sc->intr_count, 2980 ("%s: invalid direct intr_idx %d", __func__, intr_idx)); 2981 v |= V_FW_IQ_CMD_IQANDSTINDEX(intr_idx); 2982 } 2983 2984 c.type_to_iqandstindex = htobe32(v | 2985 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) | 2986 V_FW_IQ_CMD_VIID(vi->viid) | 2987 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT)); 2988 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->tx_chan) | 2989 F_FW_IQ_CMD_IQGTSMODE | 2990 V_FW_IQ_CMD_IQINTCNTTHRESH(iq->intr_pktc_idx) | 2991 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4)); 2992 c.iqsize = htobe16(iq->qsize); 2993 c.iqaddr = htobe64(iq->ba); 2994 if (cong >= 0) 2995 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN); 2996 2997 if (fl) { 2998 mtx_init(&fl->fl_lock, fl->lockname, NULL, MTX_DEF); 2999 3000 len = fl->qsize * EQ_ESIZE; 3001 rc = alloc_ring(sc, len, &fl->desc_tag, &fl->desc_map, 3002 &fl->ba, (void **)&fl->desc); 3003 if (rc) 3004 return (rc); 3005 3006 /* Allocate space for one software descriptor per buffer. */ 3007 rc = alloc_fl_sdesc(fl); 3008 if (rc != 0) { 3009 device_printf(sc->dev, 3010 "failed to setup fl software descriptors: %d\n", 3011 rc); 3012 return (rc); 3013 } 3014 3015 if (fl->flags & FL_BUF_PACKING) { 3016 fl->lowat = roundup2(sp->fl_starve_threshold2, 8); 3017 fl->buf_boundary = sp->pack_boundary; 3018 } else { 3019 fl->lowat = roundup2(sp->fl_starve_threshold, 8); 3020 fl->buf_boundary = 16; 3021 } 3022 if (fl_pad && fl->buf_boundary < sp->pad_boundary) 3023 fl->buf_boundary = sp->pad_boundary; 3024 3025 c.iqns_to_fl0congen |= 3026 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) | 3027 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO | 3028 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) | 3029 (fl->flags & FL_BUF_PACKING ? F_FW_IQ_CMD_FL0PACKEN : 3030 0)); 3031 if (cong >= 0) { 3032 c.iqns_to_fl0congen |= 3033 htobe32(V_FW_IQ_CMD_FL0CNGCHMAP(cong) | 3034 F_FW_IQ_CMD_FL0CONGCIF | 3035 F_FW_IQ_CMD_FL0CONGEN); 3036 } 3037 c.fl0dcaen_to_fl0cidxfthresh = 3038 htobe16(V_FW_IQ_CMD_FL0FBMIN(chip_id(sc) <= CHELSIO_T5 ? 3039 X_FETCHBURSTMIN_128B : X_FETCHBURSTMIN_64B) | 3040 V_FW_IQ_CMD_FL0FBMAX(chip_id(sc) <= CHELSIO_T5 ? 3041 X_FETCHBURSTMAX_512B : X_FETCHBURSTMAX_256B)); 3042 c.fl0size = htobe16(fl->qsize); 3043 c.fl0addr = htobe64(fl->ba); 3044 } 3045 3046 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3047 if (rc != 0) { 3048 device_printf(sc->dev, 3049 "failed to create ingress queue: %d\n", rc); 3050 return (rc); 3051 } 3052 3053 iq->cidx = 0; 3054 iq->gen = F_RSPD_GEN; 3055 iq->intr_next = iq->intr_params; 3056 iq->cntxt_id = be16toh(c.iqid); 3057 iq->abs_id = be16toh(c.physiqid); 3058 iq->flags |= IQ_ALLOCATED; 3059 3060 cntxt_id = iq->cntxt_id - sc->sge.iq_start; 3061 if (cntxt_id >= sc->sge.niq) { 3062 panic ("%s: iq->cntxt_id (%d) more than the max (%d)", __func__, 3063 cntxt_id, sc->sge.niq - 1); 3064 } 3065 sc->sge.iqmap[cntxt_id] = iq; 3066 3067 if (fl) { 3068 u_int qid; 3069 3070 iq->flags |= IQ_HAS_FL; 3071 fl->cntxt_id = be16toh(c.fl0id); 3072 fl->pidx = fl->cidx = 0; 3073 3074 cntxt_id = fl->cntxt_id - sc->sge.eq_start; 3075 if (cntxt_id >= sc->sge.neq) { 3076 panic("%s: fl->cntxt_id (%d) more than the max (%d)", 3077 __func__, cntxt_id, sc->sge.neq - 1); 3078 } 3079 sc->sge.eqmap[cntxt_id] = (void *)fl; 3080 3081 qid = fl->cntxt_id; 3082 if (isset(&sc->doorbells, DOORBELL_UDB)) { 3083 uint32_t s_qpp = sc->params.sge.eq_s_qpp; 3084 uint32_t mask = (1 << s_qpp) - 1; 3085 volatile uint8_t *udb; 3086 3087 udb = sc->udbs_base + UDBS_DB_OFFSET; 3088 udb += (qid >> s_qpp) << PAGE_SHIFT; 3089 qid &= mask; 3090 if (qid < PAGE_SIZE / UDBS_SEG_SIZE) { 3091 udb += qid << UDBS_SEG_SHIFT; 3092 qid = 0; 3093 } 3094 fl->udb = (volatile void *)udb; 3095 } 3096 fl->dbval = V_QID(qid) | sc->chip_params->sge_fl_db; 3097 3098 FL_LOCK(fl); 3099 /* Enough to make sure the SGE doesn't think it's starved */ 3100 refill_fl(sc, fl, fl->lowat); 3101 FL_UNLOCK(fl); 3102 } 3103 3104 if (chip_id(sc) >= CHELSIO_T5 && !(sc->flags & IS_VF) && cong >= 0) { 3105 uint32_t param, val; 3106 3107 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 3108 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) | 3109 V_FW_PARAMS_PARAM_YZ(iq->cntxt_id); 3110 if (cong == 0) 3111 val = 1 << 19; 3112 else { 3113 val = 2 << 19; 3114 for (i = 0; i < 4; i++) { 3115 if (cong & (1 << i)) 3116 val |= 1 << (i << 2); 3117 } 3118 } 3119 3120 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 3121 if (rc != 0) { 3122 /* report error but carry on */ 3123 device_printf(sc->dev, 3124 "failed to set congestion manager context for " 3125 "ingress queue %d: %d\n", iq->cntxt_id, rc); 3126 } 3127 } 3128 3129 /* Enable IQ interrupts */ 3130 atomic_store_rel_int(&iq->state, IQS_IDLE); 3131 t4_write_reg(sc, sc->sge_gts_reg, V_SEINTARM(iq->intr_params) | 3132 V_INGRESSQID(iq->cntxt_id)); 3133 3134 return (0); 3135 } 3136 3137 static int 3138 free_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl) 3139 { 3140 int rc; 3141 struct adapter *sc = iq->adapter; 3142 device_t dev; 3143 3144 if (sc == NULL) 3145 return (0); /* nothing to do */ 3146 3147 dev = vi ? vi->dev : sc->dev; 3148 3149 if (iq->flags & IQ_ALLOCATED) { 3150 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0, 3151 FW_IQ_TYPE_FL_INT_CAP, iq->cntxt_id, 3152 fl ? fl->cntxt_id : 0xffff, 0xffff); 3153 if (rc != 0) { 3154 device_printf(dev, 3155 "failed to free queue %p: %d\n", iq, rc); 3156 return (rc); 3157 } 3158 iq->flags &= ~IQ_ALLOCATED; 3159 } 3160 3161 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, iq->desc); 3162 3163 bzero(iq, sizeof(*iq)); 3164 3165 if (fl) { 3166 free_ring(sc, fl->desc_tag, fl->desc_map, fl->ba, 3167 fl->desc); 3168 3169 if (fl->sdesc) 3170 free_fl_sdesc(sc, fl); 3171 3172 if (mtx_initialized(&fl->fl_lock)) 3173 mtx_destroy(&fl->fl_lock); 3174 3175 bzero(fl, sizeof(*fl)); 3176 } 3177 3178 return (0); 3179 } 3180 3181 static void 3182 add_iq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid, 3183 struct sge_iq *iq) 3184 { 3185 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3186 3187 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, &iq->ba, 3188 "bus address of descriptor ring"); 3189 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3190 iq->qsize * IQ_ESIZE, "descriptor ring size in bytes"); 3191 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "abs_id", 3192 CTLTYPE_INT | CTLFLAG_RD, &iq->abs_id, 0, sysctl_uint16, "I", 3193 "absolute id of the queue"); 3194 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 3195 CTLTYPE_INT | CTLFLAG_RD, &iq->cntxt_id, 0, sysctl_uint16, "I", 3196 "SGE context id of the queue"); 3197 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx", 3198 CTLTYPE_INT | CTLFLAG_RD, &iq->cidx, 0, sysctl_uint16, "I", 3199 "consumer index"); 3200 } 3201 3202 static void 3203 add_fl_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx, 3204 struct sysctl_oid *oid, struct sge_fl *fl) 3205 { 3206 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3207 3208 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL, 3209 "freelist"); 3210 children = SYSCTL_CHILDREN(oid); 3211 3212 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, 3213 &fl->ba, "bus address of descriptor ring"); 3214 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3215 fl->sidx * EQ_ESIZE + sc->params.sge.spg_len, 3216 "desc ring size in bytes"); 3217 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 3218 CTLTYPE_INT | CTLFLAG_RD, &fl->cntxt_id, 0, sysctl_uint16, "I", 3219 "SGE context id of the freelist"); 3220 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "padding", CTLFLAG_RD, NULL, 3221 fl_pad ? 1 : 0, "padding enabled"); 3222 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "packing", CTLFLAG_RD, NULL, 3223 fl->flags & FL_BUF_PACKING ? 1 : 0, "packing enabled"); 3224 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &fl->cidx, 3225 0, "consumer index"); 3226 if (fl->flags & FL_BUF_PACKING) { 3227 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rx_offset", 3228 CTLFLAG_RD, &fl->rx_offset, 0, "packing rx offset"); 3229 } 3230 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &fl->pidx, 3231 0, "producer index"); 3232 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_allocated", 3233 CTLFLAG_RD, &fl->mbuf_allocated, "# of mbuf allocated"); 3234 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_inlined", 3235 CTLFLAG_RD, &fl->mbuf_inlined, "# of mbuf inlined in clusters"); 3236 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_allocated", 3237 CTLFLAG_RD, &fl->cl_allocated, "# of clusters allocated"); 3238 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_recycled", 3239 CTLFLAG_RD, &fl->cl_recycled, "# of clusters recycled"); 3240 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_fast_recycled", 3241 CTLFLAG_RD, &fl->cl_fast_recycled, "# of clusters recycled (fast)"); 3242 } 3243 3244 static int 3245 alloc_fwq(struct adapter *sc) 3246 { 3247 int rc, intr_idx; 3248 struct sge_iq *fwq = &sc->sge.fwq; 3249 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev); 3250 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3251 3252 init_iq(fwq, sc, 0, 0, FW_IQ_QSIZE); 3253 if (sc->flags & IS_VF) 3254 intr_idx = 0; 3255 else 3256 intr_idx = sc->intr_count > 1 ? 1 : 0; 3257 rc = alloc_iq_fl(&sc->port[0]->vi[0], fwq, NULL, intr_idx, -1); 3258 if (rc != 0) { 3259 device_printf(sc->dev, 3260 "failed to create firmware event queue: %d\n", rc); 3261 return (rc); 3262 } 3263 3264 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "fwq", CTLFLAG_RD, 3265 NULL, "firmware event queue"); 3266 add_iq_sysctls(&sc->ctx, oid, fwq); 3267 3268 return (0); 3269 } 3270 3271 static int 3272 free_fwq(struct adapter *sc) 3273 { 3274 return free_iq_fl(NULL, &sc->sge.fwq, NULL); 3275 } 3276 3277 static int 3278 alloc_ctrlq(struct adapter *sc, struct sge_wrq *ctrlq, int idx, 3279 struct sysctl_oid *oid) 3280 { 3281 int rc; 3282 char name[16]; 3283 struct sysctl_oid_list *children; 3284 3285 snprintf(name, sizeof(name), "%s ctrlq%d", device_get_nameunit(sc->dev), 3286 idx); 3287 init_eq(sc, &ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE, sc->port[idx]->tx_chan, 3288 sc->sge.fwq.cntxt_id, name); 3289 3290 children = SYSCTL_CHILDREN(oid); 3291 snprintf(name, sizeof(name), "%d", idx); 3292 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, name, CTLFLAG_RD, 3293 NULL, "ctrl queue"); 3294 rc = alloc_wrq(sc, NULL, ctrlq, oid); 3295 3296 return (rc); 3297 } 3298 3299 int 3300 tnl_cong(struct port_info *pi, int drop) 3301 { 3302 3303 if (drop == -1) 3304 return (-1); 3305 else if (drop == 1) 3306 return (0); 3307 else 3308 return (pi->rx_e_chan_map); 3309 } 3310 3311 static int 3312 alloc_rxq(struct vi_info *vi, struct sge_rxq *rxq, int intr_idx, int idx, 3313 struct sysctl_oid *oid) 3314 { 3315 int rc; 3316 struct adapter *sc = vi->pi->adapter; 3317 struct sysctl_oid_list *children; 3318 char name[16]; 3319 3320 rc = alloc_iq_fl(vi, &rxq->iq, &rxq->fl, intr_idx, 3321 tnl_cong(vi->pi, cong_drop)); 3322 if (rc != 0) 3323 return (rc); 3324 3325 if (idx == 0) 3326 sc->sge.iq_base = rxq->iq.abs_id - rxq->iq.cntxt_id; 3327 else 3328 KASSERT(rxq->iq.cntxt_id + sc->sge.iq_base == rxq->iq.abs_id, 3329 ("iq_base mismatch")); 3330 KASSERT(sc->sge.iq_base == 0 || sc->flags & IS_VF, 3331 ("PF with non-zero iq_base")); 3332 3333 /* 3334 * The freelist is just barely above the starvation threshold right now, 3335 * fill it up a bit more. 3336 */ 3337 FL_LOCK(&rxq->fl); 3338 refill_fl(sc, &rxq->fl, 128); 3339 FL_UNLOCK(&rxq->fl); 3340 3341 #if defined(INET) || defined(INET6) 3342 rc = tcp_lro_init_args(&rxq->lro, vi->ifp, lro_entries, lro_mbufs); 3343 if (rc != 0) 3344 return (rc); 3345 MPASS(rxq->lro.ifp == vi->ifp); /* also indicates LRO init'ed */ 3346 3347 if (vi->ifp->if_capenable & IFCAP_LRO) 3348 rxq->iq.flags |= IQ_LRO_ENABLED; 3349 #endif 3350 rxq->ifp = vi->ifp; 3351 3352 children = SYSCTL_CHILDREN(oid); 3353 3354 snprintf(name, sizeof(name), "%d", idx); 3355 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 3356 NULL, "rx queue"); 3357 children = SYSCTL_CHILDREN(oid); 3358 3359 add_iq_sysctls(&vi->ctx, oid, &rxq->iq); 3360 #if defined(INET) || defined(INET6) 3361 SYSCTL_ADD_U64(&vi->ctx, children, OID_AUTO, "lro_queued", CTLFLAG_RD, 3362 &rxq->lro.lro_queued, 0, NULL); 3363 SYSCTL_ADD_U64(&vi->ctx, children, OID_AUTO, "lro_flushed", CTLFLAG_RD, 3364 &rxq->lro.lro_flushed, 0, NULL); 3365 #endif 3366 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "rxcsum", CTLFLAG_RD, 3367 &rxq->rxcsum, "# of times hardware assisted with checksum"); 3368 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_extraction", 3369 CTLFLAG_RD, &rxq->vlan_extraction, 3370 "# of times hardware extracted 802.1Q tag"); 3371 3372 add_fl_sysctls(sc, &vi->ctx, oid, &rxq->fl); 3373 3374 return (rc); 3375 } 3376 3377 static int 3378 free_rxq(struct vi_info *vi, struct sge_rxq *rxq) 3379 { 3380 int rc; 3381 3382 #if defined(INET) || defined(INET6) 3383 if (rxq->lro.ifp) { 3384 tcp_lro_free(&rxq->lro); 3385 rxq->lro.ifp = NULL; 3386 } 3387 #endif 3388 3389 rc = free_iq_fl(vi, &rxq->iq, &rxq->fl); 3390 if (rc == 0) 3391 bzero(rxq, sizeof(*rxq)); 3392 3393 return (rc); 3394 } 3395 3396 #ifdef TCP_OFFLOAD 3397 static int 3398 alloc_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq, 3399 int intr_idx, int idx, struct sysctl_oid *oid) 3400 { 3401 struct port_info *pi = vi->pi; 3402 int rc; 3403 struct sysctl_oid_list *children; 3404 char name[16]; 3405 3406 rc = alloc_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl, intr_idx, 0); 3407 if (rc != 0) 3408 return (rc); 3409 3410 children = SYSCTL_CHILDREN(oid); 3411 3412 snprintf(name, sizeof(name), "%d", idx); 3413 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 3414 NULL, "rx queue"); 3415 add_iq_sysctls(&vi->ctx, oid, &ofld_rxq->iq); 3416 add_fl_sysctls(pi->adapter, &vi->ctx, oid, &ofld_rxq->fl); 3417 3418 return (rc); 3419 } 3420 3421 static int 3422 free_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq) 3423 { 3424 int rc; 3425 3426 rc = free_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl); 3427 if (rc == 0) 3428 bzero(ofld_rxq, sizeof(*ofld_rxq)); 3429 3430 return (rc); 3431 } 3432 #endif 3433 3434 #ifdef DEV_NETMAP 3435 static int 3436 alloc_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq, int intr_idx, 3437 int idx, struct sysctl_oid *oid) 3438 { 3439 int rc; 3440 struct sysctl_oid_list *children; 3441 struct sysctl_ctx_list *ctx; 3442 char name[16]; 3443 size_t len; 3444 struct adapter *sc = vi->pi->adapter; 3445 struct netmap_adapter *na = NA(vi->ifp); 3446 3447 MPASS(na != NULL); 3448 3449 len = vi->qsize_rxq * IQ_ESIZE; 3450 rc = alloc_ring(sc, len, &nm_rxq->iq_desc_tag, &nm_rxq->iq_desc_map, 3451 &nm_rxq->iq_ba, (void **)&nm_rxq->iq_desc); 3452 if (rc != 0) 3453 return (rc); 3454 3455 len = na->num_rx_desc * EQ_ESIZE + sc->params.sge.spg_len; 3456 rc = alloc_ring(sc, len, &nm_rxq->fl_desc_tag, &nm_rxq->fl_desc_map, 3457 &nm_rxq->fl_ba, (void **)&nm_rxq->fl_desc); 3458 if (rc != 0) 3459 return (rc); 3460 3461 nm_rxq->vi = vi; 3462 nm_rxq->nid = idx; 3463 nm_rxq->iq_cidx = 0; 3464 nm_rxq->iq_sidx = vi->qsize_rxq - sc->params.sge.spg_len / IQ_ESIZE; 3465 nm_rxq->iq_gen = F_RSPD_GEN; 3466 nm_rxq->fl_pidx = nm_rxq->fl_cidx = 0; 3467 nm_rxq->fl_sidx = na->num_rx_desc; 3468 nm_rxq->intr_idx = intr_idx; 3469 nm_rxq->iq_cntxt_id = INVALID_NM_RXQ_CNTXT_ID; 3470 3471 ctx = &vi->ctx; 3472 children = SYSCTL_CHILDREN(oid); 3473 3474 snprintf(name, sizeof(name), "%d", idx); 3475 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, name, CTLFLAG_RD, NULL, 3476 "rx queue"); 3477 children = SYSCTL_CHILDREN(oid); 3478 3479 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "abs_id", 3480 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_abs_id, 0, sysctl_uint16, 3481 "I", "absolute id of the queue"); 3482 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 3483 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cntxt_id, 0, sysctl_uint16, 3484 "I", "SGE context id of the queue"); 3485 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx", 3486 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cidx, 0, sysctl_uint16, "I", 3487 "consumer index"); 3488 3489 children = SYSCTL_CHILDREN(oid); 3490 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL, 3491 "freelist"); 3492 children = SYSCTL_CHILDREN(oid); 3493 3494 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 3495 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->fl_cntxt_id, 0, sysctl_uint16, 3496 "I", "SGE context id of the freelist"); 3497 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, 3498 &nm_rxq->fl_cidx, 0, "consumer index"); 3499 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, 3500 &nm_rxq->fl_pidx, 0, "producer index"); 3501 3502 return (rc); 3503 } 3504 3505 3506 static int 3507 free_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq) 3508 { 3509 struct adapter *sc = vi->pi->adapter; 3510 3511 if (vi->flags & VI_INIT_DONE) 3512 MPASS(nm_rxq->iq_cntxt_id == INVALID_NM_RXQ_CNTXT_ID); 3513 else 3514 MPASS(nm_rxq->iq_cntxt_id == 0); 3515 3516 free_ring(sc, nm_rxq->iq_desc_tag, nm_rxq->iq_desc_map, nm_rxq->iq_ba, 3517 nm_rxq->iq_desc); 3518 free_ring(sc, nm_rxq->fl_desc_tag, nm_rxq->fl_desc_map, nm_rxq->fl_ba, 3519 nm_rxq->fl_desc); 3520 3521 return (0); 3522 } 3523 3524 static int 3525 alloc_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq, int iqidx, int idx, 3526 struct sysctl_oid *oid) 3527 { 3528 int rc; 3529 size_t len; 3530 struct port_info *pi = vi->pi; 3531 struct adapter *sc = pi->adapter; 3532 struct netmap_adapter *na = NA(vi->ifp); 3533 char name[16]; 3534 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3535 3536 len = na->num_tx_desc * EQ_ESIZE + sc->params.sge.spg_len; 3537 rc = alloc_ring(sc, len, &nm_txq->desc_tag, &nm_txq->desc_map, 3538 &nm_txq->ba, (void **)&nm_txq->desc); 3539 if (rc) 3540 return (rc); 3541 3542 nm_txq->pidx = nm_txq->cidx = 0; 3543 nm_txq->sidx = na->num_tx_desc; 3544 nm_txq->nid = idx; 3545 nm_txq->iqidx = iqidx; 3546 nm_txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) | 3547 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(G_FW_VIID_PFN(vi->viid)) | 3548 V_TXPKT_VF(G_FW_VIID_VIN(vi->viid)) | 3549 V_TXPKT_VF_VLD(G_FW_VIID_VIVLD(vi->viid))); 3550 nm_txq->cntxt_id = INVALID_NM_TXQ_CNTXT_ID; 3551 3552 snprintf(name, sizeof(name), "%d", idx); 3553 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 3554 NULL, "netmap tx queue"); 3555 children = SYSCTL_CHILDREN(oid); 3556 3557 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 3558 &nm_txq->cntxt_id, 0, "SGE context id of the queue"); 3559 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx", 3560 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->cidx, 0, sysctl_uint16, "I", 3561 "consumer index"); 3562 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "pidx", 3563 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->pidx, 0, sysctl_uint16, "I", 3564 "producer index"); 3565 3566 return (rc); 3567 } 3568 3569 static int 3570 free_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq) 3571 { 3572 struct adapter *sc = vi->pi->adapter; 3573 3574 if (vi->flags & VI_INIT_DONE) 3575 MPASS(nm_txq->cntxt_id == INVALID_NM_TXQ_CNTXT_ID); 3576 else 3577 MPASS(nm_txq->cntxt_id == 0); 3578 3579 free_ring(sc, nm_txq->desc_tag, nm_txq->desc_map, nm_txq->ba, 3580 nm_txq->desc); 3581 3582 return (0); 3583 } 3584 #endif 3585 3586 static int 3587 ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq) 3588 { 3589 int rc, cntxt_id; 3590 struct fw_eq_ctrl_cmd c; 3591 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 3592 3593 bzero(&c, sizeof(c)); 3594 3595 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | F_FW_CMD_REQUEST | 3596 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_CTRL_CMD_PFN(sc->pf) | 3597 V_FW_EQ_CTRL_CMD_VFN(0)); 3598 c.alloc_to_len16 = htobe32(F_FW_EQ_CTRL_CMD_ALLOC | 3599 F_FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c)); 3600 c.cmpliqid_eqid = htonl(V_FW_EQ_CTRL_CMD_CMPLIQID(eq->iqid)); 3601 c.physeqid_pkd = htobe32(0); 3602 c.fetchszm_to_iqid = 3603 htobe32(V_FW_EQ_CTRL_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 3604 V_FW_EQ_CTRL_CMD_PCIECHN(eq->tx_chan) | 3605 F_FW_EQ_CTRL_CMD_FETCHRO | V_FW_EQ_CTRL_CMD_IQID(eq->iqid)); 3606 c.dcaen_to_eqsize = 3607 htobe32(V_FW_EQ_CTRL_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 3608 V_FW_EQ_CTRL_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 3609 V_FW_EQ_CTRL_CMD_CIDXFTHRESH(X_CIDXFLUSHTHRESH_32) | 3610 V_FW_EQ_CTRL_CMD_EQSIZE(qsize)); 3611 c.eqaddr = htobe64(eq->ba); 3612 3613 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3614 if (rc != 0) { 3615 device_printf(sc->dev, 3616 "failed to create control queue %d: %d\n", eq->tx_chan, rc); 3617 return (rc); 3618 } 3619 eq->flags |= EQ_ALLOCATED; 3620 3621 eq->cntxt_id = G_FW_EQ_CTRL_CMD_EQID(be32toh(c.cmpliqid_eqid)); 3622 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 3623 if (cntxt_id >= sc->sge.neq) 3624 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 3625 cntxt_id, sc->sge.neq - 1); 3626 sc->sge.eqmap[cntxt_id] = eq; 3627 3628 return (rc); 3629 } 3630 3631 static int 3632 eth_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 3633 { 3634 int rc, cntxt_id; 3635 struct fw_eq_eth_cmd c; 3636 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 3637 3638 bzero(&c, sizeof(c)); 3639 3640 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST | 3641 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) | 3642 V_FW_EQ_ETH_CMD_VFN(0)); 3643 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC | 3644 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c)); 3645 c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE | 3646 F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(vi->viid)); 3647 c.fetchszm_to_iqid = 3648 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) | 3649 V_FW_EQ_ETH_CMD_PCIECHN(eq->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO | 3650 V_FW_EQ_ETH_CMD_IQID(eq->iqid)); 3651 c.dcaen_to_eqsize = htobe32(V_FW_EQ_ETH_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 3652 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 3653 V_FW_EQ_ETH_CMD_EQSIZE(qsize)); 3654 c.eqaddr = htobe64(eq->ba); 3655 3656 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3657 if (rc != 0) { 3658 device_printf(vi->dev, 3659 "failed to create Ethernet egress queue: %d\n", rc); 3660 return (rc); 3661 } 3662 eq->flags |= EQ_ALLOCATED; 3663 3664 eq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd)); 3665 eq->abs_id = G_FW_EQ_ETH_CMD_PHYSEQID(be32toh(c.physeqid_pkd)); 3666 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 3667 if (cntxt_id >= sc->sge.neq) 3668 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 3669 cntxt_id, sc->sge.neq - 1); 3670 sc->sge.eqmap[cntxt_id] = eq; 3671 3672 return (rc); 3673 } 3674 3675 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 3676 static int 3677 ofld_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 3678 { 3679 int rc, cntxt_id; 3680 struct fw_eq_ofld_cmd c; 3681 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 3682 3683 bzero(&c, sizeof(c)); 3684 3685 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | F_FW_CMD_REQUEST | 3686 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_OFLD_CMD_PFN(sc->pf) | 3687 V_FW_EQ_OFLD_CMD_VFN(0)); 3688 c.alloc_to_len16 = htonl(F_FW_EQ_OFLD_CMD_ALLOC | 3689 F_FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c)); 3690 c.fetchszm_to_iqid = 3691 htonl(V_FW_EQ_OFLD_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) | 3692 V_FW_EQ_OFLD_CMD_PCIECHN(eq->tx_chan) | 3693 F_FW_EQ_OFLD_CMD_FETCHRO | V_FW_EQ_OFLD_CMD_IQID(eq->iqid)); 3694 c.dcaen_to_eqsize = 3695 htobe32(V_FW_EQ_OFLD_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 3696 V_FW_EQ_OFLD_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 3697 V_FW_EQ_OFLD_CMD_EQSIZE(qsize)); 3698 c.eqaddr = htobe64(eq->ba); 3699 3700 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3701 if (rc != 0) { 3702 device_printf(vi->dev, 3703 "failed to create egress queue for TCP offload: %d\n", rc); 3704 return (rc); 3705 } 3706 eq->flags |= EQ_ALLOCATED; 3707 3708 eq->cntxt_id = G_FW_EQ_OFLD_CMD_EQID(be32toh(c.eqid_pkd)); 3709 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 3710 if (cntxt_id >= sc->sge.neq) 3711 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 3712 cntxt_id, sc->sge.neq - 1); 3713 sc->sge.eqmap[cntxt_id] = eq; 3714 3715 return (rc); 3716 } 3717 #endif 3718 3719 static int 3720 alloc_eq(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 3721 { 3722 int rc, qsize; 3723 size_t len; 3724 3725 mtx_init(&eq->eq_lock, eq->lockname, NULL, MTX_DEF); 3726 3727 qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 3728 len = qsize * EQ_ESIZE; 3729 rc = alloc_ring(sc, len, &eq->desc_tag, &eq->desc_map, 3730 &eq->ba, (void **)&eq->desc); 3731 if (rc) 3732 return (rc); 3733 3734 eq->pidx = eq->cidx = 0; 3735 eq->equeqidx = eq->dbidx = 0; 3736 eq->doorbells = sc->doorbells; 3737 3738 switch (eq->flags & EQ_TYPEMASK) { 3739 case EQ_CTRL: 3740 rc = ctrl_eq_alloc(sc, eq); 3741 break; 3742 3743 case EQ_ETH: 3744 rc = eth_eq_alloc(sc, vi, eq); 3745 break; 3746 3747 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 3748 case EQ_OFLD: 3749 rc = ofld_eq_alloc(sc, vi, eq); 3750 break; 3751 #endif 3752 3753 default: 3754 panic("%s: invalid eq type %d.", __func__, 3755 eq->flags & EQ_TYPEMASK); 3756 } 3757 if (rc != 0) { 3758 device_printf(sc->dev, 3759 "failed to allocate egress queue(%d): %d\n", 3760 eq->flags & EQ_TYPEMASK, rc); 3761 } 3762 3763 if (isset(&eq->doorbells, DOORBELL_UDB) || 3764 isset(&eq->doorbells, DOORBELL_UDBWC) || 3765 isset(&eq->doorbells, DOORBELL_WCWR)) { 3766 uint32_t s_qpp = sc->params.sge.eq_s_qpp; 3767 uint32_t mask = (1 << s_qpp) - 1; 3768 volatile uint8_t *udb; 3769 3770 udb = sc->udbs_base + UDBS_DB_OFFSET; 3771 udb += (eq->cntxt_id >> s_qpp) << PAGE_SHIFT; /* pg offset */ 3772 eq->udb_qid = eq->cntxt_id & mask; /* id in page */ 3773 if (eq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE) 3774 clrbit(&eq->doorbells, DOORBELL_WCWR); 3775 else { 3776 udb += eq->udb_qid << UDBS_SEG_SHIFT; /* seg offset */ 3777 eq->udb_qid = 0; 3778 } 3779 eq->udb = (volatile void *)udb; 3780 } 3781 3782 return (rc); 3783 } 3784 3785 static int 3786 free_eq(struct adapter *sc, struct sge_eq *eq) 3787 { 3788 int rc; 3789 3790 if (eq->flags & EQ_ALLOCATED) { 3791 switch (eq->flags & EQ_TYPEMASK) { 3792 case EQ_CTRL: 3793 rc = -t4_ctrl_eq_free(sc, sc->mbox, sc->pf, 0, 3794 eq->cntxt_id); 3795 break; 3796 3797 case EQ_ETH: 3798 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0, 3799 eq->cntxt_id); 3800 break; 3801 3802 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 3803 case EQ_OFLD: 3804 rc = -t4_ofld_eq_free(sc, sc->mbox, sc->pf, 0, 3805 eq->cntxt_id); 3806 break; 3807 #endif 3808 3809 default: 3810 panic("%s: invalid eq type %d.", __func__, 3811 eq->flags & EQ_TYPEMASK); 3812 } 3813 if (rc != 0) { 3814 device_printf(sc->dev, 3815 "failed to free egress queue (%d): %d\n", 3816 eq->flags & EQ_TYPEMASK, rc); 3817 return (rc); 3818 } 3819 eq->flags &= ~EQ_ALLOCATED; 3820 } 3821 3822 free_ring(sc, eq->desc_tag, eq->desc_map, eq->ba, eq->desc); 3823 3824 if (mtx_initialized(&eq->eq_lock)) 3825 mtx_destroy(&eq->eq_lock); 3826 3827 bzero(eq, sizeof(*eq)); 3828 return (0); 3829 } 3830 3831 static int 3832 alloc_wrq(struct adapter *sc, struct vi_info *vi, struct sge_wrq *wrq, 3833 struct sysctl_oid *oid) 3834 { 3835 int rc; 3836 struct sysctl_ctx_list *ctx = vi ? &vi->ctx : &sc->ctx; 3837 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3838 3839 rc = alloc_eq(sc, vi, &wrq->eq); 3840 if (rc) 3841 return (rc); 3842 3843 wrq->adapter = sc; 3844 TASK_INIT(&wrq->wrq_tx_task, 0, wrq_tx_drain, wrq); 3845 TAILQ_INIT(&wrq->incomplete_wrs); 3846 STAILQ_INIT(&wrq->wr_list); 3847 wrq->nwr_pending = 0; 3848 wrq->ndesc_needed = 0; 3849 3850 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, 3851 &wrq->eq.ba, "bus address of descriptor ring"); 3852 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3853 wrq->eq.sidx * EQ_ESIZE + sc->params.sge.spg_len, 3854 "desc ring size in bytes"); 3855 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 3856 &wrq->eq.cntxt_id, 0, "SGE context id of the queue"); 3857 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx", 3858 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.cidx, 0, sysctl_uint16, "I", 3859 "consumer index"); 3860 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pidx", 3861 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.pidx, 0, sysctl_uint16, "I", 3862 "producer index"); 3863 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL, 3864 wrq->eq.sidx, "status page index"); 3865 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_direct", CTLFLAG_RD, 3866 &wrq->tx_wrs_direct, "# of work requests (direct)"); 3867 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_copied", CTLFLAG_RD, 3868 &wrq->tx_wrs_copied, "# of work requests (copied)"); 3869 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_sspace", CTLFLAG_RD, 3870 &wrq->tx_wrs_ss, "# of work requests (copied from scratch space)"); 3871 3872 return (rc); 3873 } 3874 3875 static int 3876 free_wrq(struct adapter *sc, struct sge_wrq *wrq) 3877 { 3878 int rc; 3879 3880 rc = free_eq(sc, &wrq->eq); 3881 if (rc) 3882 return (rc); 3883 3884 bzero(wrq, sizeof(*wrq)); 3885 return (0); 3886 } 3887 3888 static int 3889 alloc_txq(struct vi_info *vi, struct sge_txq *txq, int idx, 3890 struct sysctl_oid *oid) 3891 { 3892 int rc; 3893 struct port_info *pi = vi->pi; 3894 struct adapter *sc = pi->adapter; 3895 struct sge_eq *eq = &txq->eq; 3896 char name[16]; 3897 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3898 3899 rc = mp_ring_alloc(&txq->r, eq->sidx, txq, eth_tx, can_resume_eth_tx, 3900 M_CXGBE, M_WAITOK); 3901 if (rc != 0) { 3902 device_printf(sc->dev, "failed to allocate mp_ring: %d\n", rc); 3903 return (rc); 3904 } 3905 3906 rc = alloc_eq(sc, vi, eq); 3907 if (rc != 0) { 3908 mp_ring_free(txq->r); 3909 txq->r = NULL; 3910 return (rc); 3911 } 3912 3913 /* Can't fail after this point. */ 3914 3915 if (idx == 0) 3916 sc->sge.eq_base = eq->abs_id - eq->cntxt_id; 3917 else 3918 KASSERT(eq->cntxt_id + sc->sge.eq_base == eq->abs_id, 3919 ("eq_base mismatch")); 3920 KASSERT(sc->sge.eq_base == 0 || sc->flags & IS_VF, 3921 ("PF with non-zero eq_base")); 3922 3923 TASK_INIT(&txq->tx_reclaim_task, 0, tx_reclaim, eq); 3924 txq->ifp = vi->ifp; 3925 txq->gl = sglist_alloc(TX_SGL_SEGS, M_WAITOK); 3926 if (sc->flags & IS_VF) 3927 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) | 3928 V_TXPKT_INTF(pi->tx_chan)); 3929 else 3930 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) | 3931 V_TXPKT_INTF(pi->tx_chan) | 3932 V_TXPKT_PF(G_FW_VIID_PFN(vi->viid)) | 3933 V_TXPKT_VF(G_FW_VIID_VIN(vi->viid)) | 3934 V_TXPKT_VF_VLD(G_FW_VIID_VIVLD(vi->viid))); 3935 txq->tc_idx = -1; 3936 txq->sdesc = malloc(eq->sidx * sizeof(struct tx_sdesc), M_CXGBE, 3937 M_ZERO | M_WAITOK); 3938 3939 snprintf(name, sizeof(name), "%d", idx); 3940 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 3941 NULL, "tx queue"); 3942 children = SYSCTL_CHILDREN(oid); 3943 3944 SYSCTL_ADD_UAUTO(&vi->ctx, children, OID_AUTO, "ba", CTLFLAG_RD, 3945 &eq->ba, "bus address of descriptor ring"); 3946 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3947 eq->sidx * EQ_ESIZE + sc->params.sge.spg_len, 3948 "desc ring size in bytes"); 3949 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "abs_id", CTLFLAG_RD, 3950 &eq->abs_id, 0, "absolute id of the queue"); 3951 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 3952 &eq->cntxt_id, 0, "SGE context id of the queue"); 3953 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx", 3954 CTLTYPE_INT | CTLFLAG_RD, &eq->cidx, 0, sysctl_uint16, "I", 3955 "consumer index"); 3956 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "pidx", 3957 CTLTYPE_INT | CTLFLAG_RD, &eq->pidx, 0, sysctl_uint16, "I", 3958 "producer index"); 3959 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL, 3960 eq->sidx, "status page index"); 3961 3962 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "tc", 3963 CTLTYPE_INT | CTLFLAG_RW, vi, idx, sysctl_tc, "I", 3964 "traffic class (-1 means none)"); 3965 3966 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txcsum", CTLFLAG_RD, 3967 &txq->txcsum, "# of times hardware assisted with checksum"); 3968 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_insertion", 3969 CTLFLAG_RD, &txq->vlan_insertion, 3970 "# of times hardware inserted 802.1Q tag"); 3971 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "tso_wrs", CTLFLAG_RD, 3972 &txq->tso_wrs, "# of TSO work requests"); 3973 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "imm_wrs", CTLFLAG_RD, 3974 &txq->imm_wrs, "# of work requests with immediate data"); 3975 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "sgl_wrs", CTLFLAG_RD, 3976 &txq->sgl_wrs, "# of work requests with direct SGL"); 3977 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkt_wrs", CTLFLAG_RD, 3978 &txq->txpkt_wrs, "# of txpkt work requests (one pkt/WR)"); 3979 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_wrs", 3980 CTLFLAG_RD, &txq->txpkts0_wrs, 3981 "# of txpkts (type 0) work requests"); 3982 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_wrs", 3983 CTLFLAG_RD, &txq->txpkts1_wrs, 3984 "# of txpkts (type 1) work requests"); 3985 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_pkts", 3986 CTLFLAG_RD, &txq->txpkts0_pkts, 3987 "# of frames tx'd using type0 txpkts work requests"); 3988 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_pkts", 3989 CTLFLAG_RD, &txq->txpkts1_pkts, 3990 "# of frames tx'd using type1 txpkts work requests"); 3991 3992 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_enqueues", 3993 CTLFLAG_RD, &txq->r->enqueues, 3994 "# of enqueues to the mp_ring for this queue"); 3995 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_drops", 3996 CTLFLAG_RD, &txq->r->drops, 3997 "# of drops in the mp_ring for this queue"); 3998 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_starts", 3999 CTLFLAG_RD, &txq->r->starts, 4000 "# of normal consumer starts in the mp_ring for this queue"); 4001 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_stalls", 4002 CTLFLAG_RD, &txq->r->stalls, 4003 "# of consumer stalls in the mp_ring for this queue"); 4004 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_restarts", 4005 CTLFLAG_RD, &txq->r->restarts, 4006 "# of consumer restarts in the mp_ring for this queue"); 4007 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_abdications", 4008 CTLFLAG_RD, &txq->r->abdications, 4009 "# of consumer abdications in the mp_ring for this queue"); 4010 4011 return (0); 4012 } 4013 4014 static int 4015 free_txq(struct vi_info *vi, struct sge_txq *txq) 4016 { 4017 int rc; 4018 struct adapter *sc = vi->pi->adapter; 4019 struct sge_eq *eq = &txq->eq; 4020 4021 rc = free_eq(sc, eq); 4022 if (rc) 4023 return (rc); 4024 4025 sglist_free(txq->gl); 4026 free(txq->sdesc, M_CXGBE); 4027 mp_ring_free(txq->r); 4028 4029 bzero(txq, sizeof(*txq)); 4030 return (0); 4031 } 4032 4033 static void 4034 oneseg_dma_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error) 4035 { 4036 bus_addr_t *ba = arg; 4037 4038 KASSERT(nseg == 1, 4039 ("%s meant for single segment mappings only.", __func__)); 4040 4041 *ba = error ? 0 : segs->ds_addr; 4042 } 4043 4044 static inline void 4045 ring_fl_db(struct adapter *sc, struct sge_fl *fl) 4046 { 4047 uint32_t n, v; 4048 4049 n = IDXDIFF(fl->pidx / 8, fl->dbidx, fl->sidx); 4050 MPASS(n > 0); 4051 4052 wmb(); 4053 v = fl->dbval | V_PIDX(n); 4054 if (fl->udb) 4055 *fl->udb = htole32(v); 4056 else 4057 t4_write_reg(sc, sc->sge_kdoorbell_reg, v); 4058 IDXINCR(fl->dbidx, n, fl->sidx); 4059 } 4060 4061 /* 4062 * Fills up the freelist by allocating up to 'n' buffers. Buffers that are 4063 * recycled do not count towards this allocation budget. 4064 * 4065 * Returns non-zero to indicate that this freelist should be added to the list 4066 * of starving freelists. 4067 */ 4068 static int 4069 refill_fl(struct adapter *sc, struct sge_fl *fl, int n) 4070 { 4071 __be64 *d; 4072 struct fl_sdesc *sd; 4073 uintptr_t pa; 4074 caddr_t cl; 4075 struct cluster_layout *cll; 4076 struct sw_zone_info *swz; 4077 struct cluster_metadata *clm; 4078 uint16_t max_pidx; 4079 uint16_t hw_cidx = fl->hw_cidx; /* stable snapshot */ 4080 4081 FL_LOCK_ASSERT_OWNED(fl); 4082 4083 /* 4084 * We always stop at the beginning of the hardware descriptor that's just 4085 * before the one with the hw cidx. This is to avoid hw pidx = hw cidx, 4086 * which would mean an empty freelist to the chip. 4087 */ 4088 max_pidx = __predict_false(hw_cidx == 0) ? fl->sidx - 1 : hw_cidx - 1; 4089 if (fl->pidx == max_pidx * 8) 4090 return (0); 4091 4092 d = &fl->desc[fl->pidx]; 4093 sd = &fl->sdesc[fl->pidx]; 4094 cll = &fl->cll_def; /* default layout */ 4095 swz = &sc->sge.sw_zone_info[cll->zidx]; 4096 4097 while (n > 0) { 4098 4099 if (sd->cl != NULL) { 4100 4101 if (sd->nmbuf == 0) { 4102 /* 4103 * Fast recycle without involving any atomics on 4104 * the cluster's metadata (if the cluster has 4105 * metadata). This happens when all frames 4106 * received in the cluster were small enough to 4107 * fit within a single mbuf each. 4108 */ 4109 fl->cl_fast_recycled++; 4110 #ifdef INVARIANTS 4111 clm = cl_metadata(sc, fl, &sd->cll, sd->cl); 4112 if (clm != NULL) 4113 MPASS(clm->refcount == 1); 4114 #endif 4115 goto recycled_fast; 4116 } 4117 4118 /* 4119 * Cluster is guaranteed to have metadata. Clusters 4120 * without metadata always take the fast recycle path 4121 * when they're recycled. 4122 */ 4123 clm = cl_metadata(sc, fl, &sd->cll, sd->cl); 4124 MPASS(clm != NULL); 4125 4126 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) { 4127 fl->cl_recycled++; 4128 counter_u64_add(extfree_rels, 1); 4129 goto recycled; 4130 } 4131 sd->cl = NULL; /* gave up my reference */ 4132 } 4133 MPASS(sd->cl == NULL); 4134 alloc: 4135 cl = uma_zalloc(swz->zone, M_NOWAIT); 4136 if (__predict_false(cl == NULL)) { 4137 if (cll == &fl->cll_alt || fl->cll_alt.zidx == -1 || 4138 fl->cll_def.zidx == fl->cll_alt.zidx) 4139 break; 4140 4141 /* fall back to the safe zone */ 4142 cll = &fl->cll_alt; 4143 swz = &sc->sge.sw_zone_info[cll->zidx]; 4144 goto alloc; 4145 } 4146 fl->cl_allocated++; 4147 n--; 4148 4149 pa = pmap_kextract((vm_offset_t)cl); 4150 pa += cll->region1; 4151 sd->cl = cl; 4152 sd->cll = *cll; 4153 *d = htobe64(pa | cll->hwidx); 4154 clm = cl_metadata(sc, fl, cll, cl); 4155 if (clm != NULL) { 4156 recycled: 4157 #ifdef INVARIANTS 4158 clm->sd = sd; 4159 #endif 4160 clm->refcount = 1; 4161 } 4162 sd->nmbuf = 0; 4163 recycled_fast: 4164 d++; 4165 sd++; 4166 if (__predict_false(++fl->pidx % 8 == 0)) { 4167 uint16_t pidx = fl->pidx / 8; 4168 4169 if (__predict_false(pidx == fl->sidx)) { 4170 fl->pidx = 0; 4171 pidx = 0; 4172 sd = fl->sdesc; 4173 d = fl->desc; 4174 } 4175 if (pidx == max_pidx) 4176 break; 4177 4178 if (IDXDIFF(pidx, fl->dbidx, fl->sidx) >= 4) 4179 ring_fl_db(sc, fl); 4180 } 4181 } 4182 4183 if (fl->pidx / 8 != fl->dbidx) 4184 ring_fl_db(sc, fl); 4185 4186 return (FL_RUNNING_LOW(fl) && !(fl->flags & FL_STARVING)); 4187 } 4188 4189 /* 4190 * Attempt to refill all starving freelists. 4191 */ 4192 static void 4193 refill_sfl(void *arg) 4194 { 4195 struct adapter *sc = arg; 4196 struct sge_fl *fl, *fl_temp; 4197 4198 mtx_assert(&sc->sfl_lock, MA_OWNED); 4199 TAILQ_FOREACH_SAFE(fl, &sc->sfl, link, fl_temp) { 4200 FL_LOCK(fl); 4201 refill_fl(sc, fl, 64); 4202 if (FL_NOT_RUNNING_LOW(fl) || fl->flags & FL_DOOMED) { 4203 TAILQ_REMOVE(&sc->sfl, fl, link); 4204 fl->flags &= ~FL_STARVING; 4205 } 4206 FL_UNLOCK(fl); 4207 } 4208 4209 if (!TAILQ_EMPTY(&sc->sfl)) 4210 callout_schedule(&sc->sfl_callout, hz / 5); 4211 } 4212 4213 static int 4214 alloc_fl_sdesc(struct sge_fl *fl) 4215 { 4216 4217 fl->sdesc = malloc(fl->sidx * 8 * sizeof(struct fl_sdesc), M_CXGBE, 4218 M_ZERO | M_WAITOK); 4219 4220 return (0); 4221 } 4222 4223 static void 4224 free_fl_sdesc(struct adapter *sc, struct sge_fl *fl) 4225 { 4226 struct fl_sdesc *sd; 4227 struct cluster_metadata *clm; 4228 struct cluster_layout *cll; 4229 int i; 4230 4231 sd = fl->sdesc; 4232 for (i = 0; i < fl->sidx * 8; i++, sd++) { 4233 if (sd->cl == NULL) 4234 continue; 4235 4236 cll = &sd->cll; 4237 clm = cl_metadata(sc, fl, cll, sd->cl); 4238 if (sd->nmbuf == 0) 4239 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl); 4240 else if (clm && atomic_fetchadd_int(&clm->refcount, -1) == 1) { 4241 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl); 4242 counter_u64_add(extfree_rels, 1); 4243 } 4244 sd->cl = NULL; 4245 } 4246 4247 free(fl->sdesc, M_CXGBE); 4248 fl->sdesc = NULL; 4249 } 4250 4251 static inline void 4252 get_pkt_gl(struct mbuf *m, struct sglist *gl) 4253 { 4254 int rc; 4255 4256 M_ASSERTPKTHDR(m); 4257 4258 sglist_reset(gl); 4259 rc = sglist_append_mbuf(gl, m); 4260 if (__predict_false(rc != 0)) { 4261 panic("%s: mbuf %p (%d segs) was vetted earlier but now fails " 4262 "with %d.", __func__, m, mbuf_nsegs(m), rc); 4263 } 4264 4265 KASSERT(gl->sg_nseg == mbuf_nsegs(m), 4266 ("%s: nsegs changed for mbuf %p from %d to %d", __func__, m, 4267 mbuf_nsegs(m), gl->sg_nseg)); 4268 KASSERT(gl->sg_nseg > 0 && 4269 gl->sg_nseg <= (needs_tso(m) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS), 4270 ("%s: %d segments, should have been 1 <= nsegs <= %d", __func__, 4271 gl->sg_nseg, needs_tso(m) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS)); 4272 } 4273 4274 /* 4275 * len16 for a txpkt WR with a GL. Includes the firmware work request header. 4276 */ 4277 static inline u_int 4278 txpkt_len16(u_int nsegs, u_int tso) 4279 { 4280 u_int n; 4281 4282 MPASS(nsegs > 0); 4283 4284 nsegs--; /* first segment is part of ulptx_sgl */ 4285 n = sizeof(struct fw_eth_tx_pkt_wr) + sizeof(struct cpl_tx_pkt_core) + 4286 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 4287 if (tso) 4288 n += sizeof(struct cpl_tx_pkt_lso_core); 4289 4290 return (howmany(n, 16)); 4291 } 4292 4293 /* 4294 * len16 for a txpkt_vm WR with a GL. Includes the firmware work 4295 * request header. 4296 */ 4297 static inline u_int 4298 txpkt_vm_len16(u_int nsegs, u_int tso) 4299 { 4300 u_int n; 4301 4302 MPASS(nsegs > 0); 4303 4304 nsegs--; /* first segment is part of ulptx_sgl */ 4305 n = sizeof(struct fw_eth_tx_pkt_vm_wr) + 4306 sizeof(struct cpl_tx_pkt_core) + 4307 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 4308 if (tso) 4309 n += sizeof(struct cpl_tx_pkt_lso_core); 4310 4311 return (howmany(n, 16)); 4312 } 4313 4314 /* 4315 * len16 for a txpkts type 0 WR with a GL. Does not include the firmware work 4316 * request header. 4317 */ 4318 static inline u_int 4319 txpkts0_len16(u_int nsegs) 4320 { 4321 u_int n; 4322 4323 MPASS(nsegs > 0); 4324 4325 nsegs--; /* first segment is part of ulptx_sgl */ 4326 n = sizeof(struct ulp_txpkt) + sizeof(struct ulptx_idata) + 4327 sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl) + 4328 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 4329 4330 return (howmany(n, 16)); 4331 } 4332 4333 /* 4334 * len16 for a txpkts type 1 WR with a GL. Does not include the firmware work 4335 * request header. 4336 */ 4337 static inline u_int 4338 txpkts1_len16(void) 4339 { 4340 u_int n; 4341 4342 n = sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl); 4343 4344 return (howmany(n, 16)); 4345 } 4346 4347 static inline u_int 4348 imm_payload(u_int ndesc) 4349 { 4350 u_int n; 4351 4352 n = ndesc * EQ_ESIZE - sizeof(struct fw_eth_tx_pkt_wr) - 4353 sizeof(struct cpl_tx_pkt_core); 4354 4355 return (n); 4356 } 4357 4358 /* 4359 * Write a VM txpkt WR for this packet to the hardware descriptors, update the 4360 * software descriptor, and advance the pidx. It is guaranteed that enough 4361 * descriptors are available. 4362 * 4363 * The return value is the # of hardware descriptors used. 4364 */ 4365 static u_int 4366 write_txpkt_vm_wr(struct adapter *sc, struct sge_txq *txq, 4367 struct fw_eth_tx_pkt_vm_wr *wr, struct mbuf *m0, u_int available) 4368 { 4369 struct sge_eq *eq = &txq->eq; 4370 struct tx_sdesc *txsd; 4371 struct cpl_tx_pkt_core *cpl; 4372 uint32_t ctrl; /* used in many unrelated places */ 4373 uint64_t ctrl1; 4374 int csum_type, len16, ndesc, pktlen, nsegs; 4375 caddr_t dst; 4376 4377 TXQ_LOCK_ASSERT_OWNED(txq); 4378 M_ASSERTPKTHDR(m0); 4379 MPASS(available > 0 && available < eq->sidx); 4380 4381 len16 = mbuf_len16(m0); 4382 nsegs = mbuf_nsegs(m0); 4383 pktlen = m0->m_pkthdr.len; 4384 ctrl = sizeof(struct cpl_tx_pkt_core); 4385 if (needs_tso(m0)) 4386 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 4387 ndesc = howmany(len16, EQ_ESIZE / 16); 4388 MPASS(ndesc <= available); 4389 4390 /* Firmware work request header */ 4391 MPASS(wr == (void *)&eq->desc[eq->pidx]); 4392 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_VM_WR) | 4393 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl)); 4394 4395 ctrl = V_FW_WR_LEN16(len16); 4396 wr->equiq_to_len16 = htobe32(ctrl); 4397 wr->r3[0] = 0; 4398 wr->r3[1] = 0; 4399 4400 /* 4401 * Copy over ethmacdst, ethmacsrc, ethtype, and vlantci. 4402 * vlantci is ignored unless the ethtype is 0x8100, so it's 4403 * simpler to always copy it rather than making it 4404 * conditional. Also, it seems that we do not have to set 4405 * vlantci or fake the ethtype when doing VLAN tag insertion. 4406 */ 4407 m_copydata(m0, 0, sizeof(struct ether_header) + 2, wr->ethmacdst); 4408 4409 csum_type = -1; 4410 if (needs_tso(m0)) { 4411 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1); 4412 4413 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 4414 m0->m_pkthdr.l4hlen > 0, 4415 ("%s: mbuf %p needs TSO but missing header lengths", 4416 __func__, m0)); 4417 4418 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE | 4419 F_LSO_LAST_SLICE | V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) 4420 | V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2); 4421 if (m0->m_pkthdr.l2hlen == sizeof(struct ether_vlan_header)) 4422 ctrl |= V_LSO_ETHHDR_LEN(1); 4423 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 4424 ctrl |= F_LSO_IPV6; 4425 4426 lso->lso_ctrl = htobe32(ctrl); 4427 lso->ipid_ofst = htobe16(0); 4428 lso->mss = htobe16(m0->m_pkthdr.tso_segsz); 4429 lso->seqno_offset = htobe32(0); 4430 lso->len = htobe32(pktlen); 4431 4432 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 4433 csum_type = TX_CSUM_TCPIP6; 4434 else 4435 csum_type = TX_CSUM_TCPIP; 4436 4437 cpl = (void *)(lso + 1); 4438 4439 txq->tso_wrs++; 4440 } else { 4441 if (m0->m_pkthdr.csum_flags & CSUM_IP_TCP) 4442 csum_type = TX_CSUM_TCPIP; 4443 else if (m0->m_pkthdr.csum_flags & CSUM_IP_UDP) 4444 csum_type = TX_CSUM_UDPIP; 4445 else if (m0->m_pkthdr.csum_flags & CSUM_IP6_TCP) 4446 csum_type = TX_CSUM_TCPIP6; 4447 else if (m0->m_pkthdr.csum_flags & CSUM_IP6_UDP) 4448 csum_type = TX_CSUM_UDPIP6; 4449 #if defined(INET) 4450 else if (m0->m_pkthdr.csum_flags & CSUM_IP) { 4451 /* 4452 * XXX: The firmware appears to stomp on the 4453 * fragment/flags field of the IP header when 4454 * using TX_CSUM_IP. Fall back to doing 4455 * software checksums. 4456 */ 4457 u_short *sump; 4458 struct mbuf *m; 4459 int offset; 4460 4461 m = m0; 4462 offset = 0; 4463 sump = m_advance(&m, &offset, m0->m_pkthdr.l2hlen + 4464 offsetof(struct ip, ip_sum)); 4465 *sump = in_cksum_skip(m0, m0->m_pkthdr.l2hlen + 4466 m0->m_pkthdr.l3hlen, m0->m_pkthdr.l2hlen); 4467 m0->m_pkthdr.csum_flags &= ~CSUM_IP; 4468 } 4469 #endif 4470 4471 cpl = (void *)(wr + 1); 4472 } 4473 4474 /* Checksum offload */ 4475 ctrl1 = 0; 4476 if (needs_l3_csum(m0) == 0) 4477 ctrl1 |= F_TXPKT_IPCSUM_DIS; 4478 if (csum_type >= 0) { 4479 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0, 4480 ("%s: mbuf %p needs checksum offload but missing header lengths", 4481 __func__, m0)); 4482 4483 if (chip_id(sc) <= CHELSIO_T5) { 4484 ctrl1 |= V_TXPKT_ETHHDR_LEN(m0->m_pkthdr.l2hlen - 4485 ETHER_HDR_LEN); 4486 } else { 4487 ctrl1 |= V_T6_TXPKT_ETHHDR_LEN(m0->m_pkthdr.l2hlen - 4488 ETHER_HDR_LEN); 4489 } 4490 ctrl1 |= V_TXPKT_IPHDR_LEN(m0->m_pkthdr.l3hlen); 4491 ctrl1 |= V_TXPKT_CSUM_TYPE(csum_type); 4492 } else 4493 ctrl1 |= F_TXPKT_L4CSUM_DIS; 4494 if (m0->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | 4495 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO)) 4496 txq->txcsum++; /* some hardware assistance provided */ 4497 4498 /* VLAN tag insertion */ 4499 if (needs_vlan_insertion(m0)) { 4500 ctrl1 |= F_TXPKT_VLAN_VLD | 4501 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 4502 txq->vlan_insertion++; 4503 } 4504 4505 /* CPL header */ 4506 cpl->ctrl0 = txq->cpl_ctrl0; 4507 cpl->pack = 0; 4508 cpl->len = htobe16(pktlen); 4509 cpl->ctrl1 = htobe64(ctrl1); 4510 4511 /* SGL */ 4512 dst = (void *)(cpl + 1); 4513 4514 /* 4515 * A packet using TSO will use up an entire descriptor for the 4516 * firmware work request header, LSO CPL, and TX_PKT_XT CPL. 4517 * If this descriptor is the last descriptor in the ring, wrap 4518 * around to the front of the ring explicitly for the start of 4519 * the sgl. 4520 */ 4521 if (dst == (void *)&eq->desc[eq->sidx]) { 4522 dst = (void *)&eq->desc[0]; 4523 write_gl_to_txd(txq, m0, &dst, 0); 4524 } else 4525 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx); 4526 txq->sgl_wrs++; 4527 4528 txq->txpkt_wrs++; 4529 4530 txsd = &txq->sdesc[eq->pidx]; 4531 txsd->m = m0; 4532 txsd->desc_used = ndesc; 4533 4534 return (ndesc); 4535 } 4536 4537 /* 4538 * Write a txpkt WR for this packet to the hardware descriptors, update the 4539 * software descriptor, and advance the pidx. It is guaranteed that enough 4540 * descriptors are available. 4541 * 4542 * The return value is the # of hardware descriptors used. 4543 */ 4544 static u_int 4545 write_txpkt_wr(struct sge_txq *txq, struct fw_eth_tx_pkt_wr *wr, 4546 struct mbuf *m0, u_int available) 4547 { 4548 struct sge_eq *eq = &txq->eq; 4549 struct tx_sdesc *txsd; 4550 struct cpl_tx_pkt_core *cpl; 4551 uint32_t ctrl; /* used in many unrelated places */ 4552 uint64_t ctrl1; 4553 int len16, ndesc, pktlen, nsegs; 4554 caddr_t dst; 4555 4556 TXQ_LOCK_ASSERT_OWNED(txq); 4557 M_ASSERTPKTHDR(m0); 4558 MPASS(available > 0 && available < eq->sidx); 4559 4560 len16 = mbuf_len16(m0); 4561 nsegs = mbuf_nsegs(m0); 4562 pktlen = m0->m_pkthdr.len; 4563 ctrl = sizeof(struct cpl_tx_pkt_core); 4564 if (needs_tso(m0)) 4565 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 4566 else if (pktlen <= imm_payload(2) && available >= 2) { 4567 /* Immediate data. Recalculate len16 and set nsegs to 0. */ 4568 ctrl += pktlen; 4569 len16 = howmany(sizeof(struct fw_eth_tx_pkt_wr) + 4570 sizeof(struct cpl_tx_pkt_core) + pktlen, 16); 4571 nsegs = 0; 4572 } 4573 ndesc = howmany(len16, EQ_ESIZE / 16); 4574 MPASS(ndesc <= available); 4575 4576 /* Firmware work request header */ 4577 MPASS(wr == (void *)&eq->desc[eq->pidx]); 4578 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_WR) | 4579 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl)); 4580 4581 ctrl = V_FW_WR_LEN16(len16); 4582 wr->equiq_to_len16 = htobe32(ctrl); 4583 wr->r3 = 0; 4584 4585 if (needs_tso(m0)) { 4586 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1); 4587 4588 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 4589 m0->m_pkthdr.l4hlen > 0, 4590 ("%s: mbuf %p needs TSO but missing header lengths", 4591 __func__, m0)); 4592 4593 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE | 4594 F_LSO_LAST_SLICE | V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) 4595 | V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2); 4596 if (m0->m_pkthdr.l2hlen == sizeof(struct ether_vlan_header)) 4597 ctrl |= V_LSO_ETHHDR_LEN(1); 4598 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 4599 ctrl |= F_LSO_IPV6; 4600 4601 lso->lso_ctrl = htobe32(ctrl); 4602 lso->ipid_ofst = htobe16(0); 4603 lso->mss = htobe16(m0->m_pkthdr.tso_segsz); 4604 lso->seqno_offset = htobe32(0); 4605 lso->len = htobe32(pktlen); 4606 4607 cpl = (void *)(lso + 1); 4608 4609 txq->tso_wrs++; 4610 } else 4611 cpl = (void *)(wr + 1); 4612 4613 /* Checksum offload */ 4614 ctrl1 = 0; 4615 if (needs_l3_csum(m0) == 0) 4616 ctrl1 |= F_TXPKT_IPCSUM_DIS; 4617 if (needs_l4_csum(m0) == 0) 4618 ctrl1 |= F_TXPKT_L4CSUM_DIS; 4619 if (m0->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | 4620 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO)) 4621 txq->txcsum++; /* some hardware assistance provided */ 4622 4623 /* VLAN tag insertion */ 4624 if (needs_vlan_insertion(m0)) { 4625 ctrl1 |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 4626 txq->vlan_insertion++; 4627 } 4628 4629 /* CPL header */ 4630 cpl->ctrl0 = txq->cpl_ctrl0; 4631 cpl->pack = 0; 4632 cpl->len = htobe16(pktlen); 4633 cpl->ctrl1 = htobe64(ctrl1); 4634 4635 /* SGL */ 4636 dst = (void *)(cpl + 1); 4637 if (nsegs > 0) { 4638 4639 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx); 4640 txq->sgl_wrs++; 4641 } else { 4642 struct mbuf *m; 4643 4644 for (m = m0; m != NULL; m = m->m_next) { 4645 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len); 4646 #ifdef INVARIANTS 4647 pktlen -= m->m_len; 4648 #endif 4649 } 4650 #ifdef INVARIANTS 4651 KASSERT(pktlen == 0, ("%s: %d bytes left.", __func__, pktlen)); 4652 #endif 4653 txq->imm_wrs++; 4654 } 4655 4656 txq->txpkt_wrs++; 4657 4658 txsd = &txq->sdesc[eq->pidx]; 4659 txsd->m = m0; 4660 txsd->desc_used = ndesc; 4661 4662 return (ndesc); 4663 } 4664 4665 static int 4666 try_txpkts(struct mbuf *m, struct mbuf *n, struct txpkts *txp, u_int available) 4667 { 4668 u_int needed, nsegs1, nsegs2, l1, l2; 4669 4670 if (cannot_use_txpkts(m) || cannot_use_txpkts(n)) 4671 return (1); 4672 4673 nsegs1 = mbuf_nsegs(m); 4674 nsegs2 = mbuf_nsegs(n); 4675 if (nsegs1 + nsegs2 == 2) { 4676 txp->wr_type = 1; 4677 l1 = l2 = txpkts1_len16(); 4678 } else { 4679 txp->wr_type = 0; 4680 l1 = txpkts0_len16(nsegs1); 4681 l2 = txpkts0_len16(nsegs2); 4682 } 4683 txp->len16 = howmany(sizeof(struct fw_eth_tx_pkts_wr), 16) + l1 + l2; 4684 needed = howmany(txp->len16, EQ_ESIZE / 16); 4685 if (needed > SGE_MAX_WR_NDESC || needed > available) 4686 return (1); 4687 4688 txp->plen = m->m_pkthdr.len + n->m_pkthdr.len; 4689 if (txp->plen > 65535) 4690 return (1); 4691 4692 txp->npkt = 2; 4693 set_mbuf_len16(m, l1); 4694 set_mbuf_len16(n, l2); 4695 4696 return (0); 4697 } 4698 4699 static int 4700 add_to_txpkts(struct mbuf *m, struct txpkts *txp, u_int available) 4701 { 4702 u_int plen, len16, needed, nsegs; 4703 4704 MPASS(txp->wr_type == 0 || txp->wr_type == 1); 4705 4706 nsegs = mbuf_nsegs(m); 4707 if (needs_tso(m) || (txp->wr_type == 1 && nsegs != 1)) 4708 return (1); 4709 4710 plen = txp->plen + m->m_pkthdr.len; 4711 if (plen > 65535) 4712 return (1); 4713 4714 if (txp->wr_type == 0) 4715 len16 = txpkts0_len16(nsegs); 4716 else 4717 len16 = txpkts1_len16(); 4718 needed = howmany(txp->len16 + len16, EQ_ESIZE / 16); 4719 if (needed > SGE_MAX_WR_NDESC || needed > available) 4720 return (1); 4721 4722 txp->npkt++; 4723 txp->plen = plen; 4724 txp->len16 += len16; 4725 set_mbuf_len16(m, len16); 4726 4727 return (0); 4728 } 4729 4730 /* 4731 * Write a txpkts WR for the packets in txp to the hardware descriptors, update 4732 * the software descriptor, and advance the pidx. It is guaranteed that enough 4733 * descriptors are available. 4734 * 4735 * The return value is the # of hardware descriptors used. 4736 */ 4737 static u_int 4738 write_txpkts_wr(struct sge_txq *txq, struct fw_eth_tx_pkts_wr *wr, 4739 struct mbuf *m0, const struct txpkts *txp, u_int available) 4740 { 4741 struct sge_eq *eq = &txq->eq; 4742 struct tx_sdesc *txsd; 4743 struct cpl_tx_pkt_core *cpl; 4744 uint32_t ctrl; 4745 uint64_t ctrl1; 4746 int ndesc, checkwrap; 4747 struct mbuf *m; 4748 void *flitp; 4749 4750 TXQ_LOCK_ASSERT_OWNED(txq); 4751 MPASS(txp->npkt > 0); 4752 MPASS(txp->plen < 65536); 4753 MPASS(m0 != NULL); 4754 MPASS(m0->m_nextpkt != NULL); 4755 MPASS(txp->len16 <= howmany(SGE_MAX_WR_LEN, 16)); 4756 MPASS(available > 0 && available < eq->sidx); 4757 4758 ndesc = howmany(txp->len16, EQ_ESIZE / 16); 4759 MPASS(ndesc <= available); 4760 4761 MPASS(wr == (void *)&eq->desc[eq->pidx]); 4762 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR)); 4763 ctrl = V_FW_WR_LEN16(txp->len16); 4764 wr->equiq_to_len16 = htobe32(ctrl); 4765 wr->plen = htobe16(txp->plen); 4766 wr->npkt = txp->npkt; 4767 wr->r3 = 0; 4768 wr->type = txp->wr_type; 4769 flitp = wr + 1; 4770 4771 /* 4772 * At this point we are 16B into a hardware descriptor. If checkwrap is 4773 * set then we know the WR is going to wrap around somewhere. We'll 4774 * check for that at appropriate points. 4775 */ 4776 checkwrap = eq->sidx - ndesc < eq->pidx; 4777 for (m = m0; m != NULL; m = m->m_nextpkt) { 4778 if (txp->wr_type == 0) { 4779 struct ulp_txpkt *ulpmc; 4780 struct ulptx_idata *ulpsc; 4781 4782 /* ULP master command */ 4783 ulpmc = flitp; 4784 ulpmc->cmd_dest = htobe32(V_ULPTX_CMD(ULP_TX_PKT) | 4785 V_ULP_TXPKT_DEST(0) | V_ULP_TXPKT_FID(eq->iqid)); 4786 ulpmc->len = htobe32(mbuf_len16(m)); 4787 4788 /* ULP subcommand */ 4789 ulpsc = (void *)(ulpmc + 1); 4790 ulpsc->cmd_more = htobe32(V_ULPTX_CMD(ULP_TX_SC_IMM) | 4791 F_ULP_TX_SC_MORE); 4792 ulpsc->len = htobe32(sizeof(struct cpl_tx_pkt_core)); 4793 4794 cpl = (void *)(ulpsc + 1); 4795 if (checkwrap && 4796 (uintptr_t)cpl == (uintptr_t)&eq->desc[eq->sidx]) 4797 cpl = (void *)&eq->desc[0]; 4798 } else { 4799 cpl = flitp; 4800 } 4801 4802 /* Checksum offload */ 4803 ctrl1 = 0; 4804 if (needs_l3_csum(m) == 0) 4805 ctrl1 |= F_TXPKT_IPCSUM_DIS; 4806 if (needs_l4_csum(m) == 0) 4807 ctrl1 |= F_TXPKT_L4CSUM_DIS; 4808 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | 4809 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO)) 4810 txq->txcsum++; /* some hardware assistance provided */ 4811 4812 /* VLAN tag insertion */ 4813 if (needs_vlan_insertion(m)) { 4814 ctrl1 |= F_TXPKT_VLAN_VLD | 4815 V_TXPKT_VLAN(m->m_pkthdr.ether_vtag); 4816 txq->vlan_insertion++; 4817 } 4818 4819 /* CPL header */ 4820 cpl->ctrl0 = txq->cpl_ctrl0; 4821 cpl->pack = 0; 4822 cpl->len = htobe16(m->m_pkthdr.len); 4823 cpl->ctrl1 = htobe64(ctrl1); 4824 4825 flitp = cpl + 1; 4826 if (checkwrap && 4827 (uintptr_t)flitp == (uintptr_t)&eq->desc[eq->sidx]) 4828 flitp = (void *)&eq->desc[0]; 4829 4830 write_gl_to_txd(txq, m, (caddr_t *)(&flitp), checkwrap); 4831 4832 } 4833 4834 if (txp->wr_type == 0) { 4835 txq->txpkts0_pkts += txp->npkt; 4836 txq->txpkts0_wrs++; 4837 } else { 4838 txq->txpkts1_pkts += txp->npkt; 4839 txq->txpkts1_wrs++; 4840 } 4841 4842 txsd = &txq->sdesc[eq->pidx]; 4843 txsd->m = m0; 4844 txsd->desc_used = ndesc; 4845 4846 return (ndesc); 4847 } 4848 4849 /* 4850 * If the SGL ends on an address that is not 16 byte aligned, this function will 4851 * add a 0 filled flit at the end. 4852 */ 4853 static void 4854 write_gl_to_txd(struct sge_txq *txq, struct mbuf *m, caddr_t *to, int checkwrap) 4855 { 4856 struct sge_eq *eq = &txq->eq; 4857 struct sglist *gl = txq->gl; 4858 struct sglist_seg *seg; 4859 __be64 *flitp, *wrap; 4860 struct ulptx_sgl *usgl; 4861 int i, nflits, nsegs; 4862 4863 KASSERT(((uintptr_t)(*to) & 0xf) == 0, 4864 ("%s: SGL must start at a 16 byte boundary: %p", __func__, *to)); 4865 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]); 4866 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]); 4867 4868 get_pkt_gl(m, gl); 4869 nsegs = gl->sg_nseg; 4870 MPASS(nsegs > 0); 4871 4872 nflits = (3 * (nsegs - 1)) / 2 + ((nsegs - 1) & 1) + 2; 4873 flitp = (__be64 *)(*to); 4874 wrap = (__be64 *)(&eq->desc[eq->sidx]); 4875 seg = &gl->sg_segs[0]; 4876 usgl = (void *)flitp; 4877 4878 /* 4879 * We start at a 16 byte boundary somewhere inside the tx descriptor 4880 * ring, so we're at least 16 bytes away from the status page. There is 4881 * no chance of a wrap around in the middle of usgl (which is 16 bytes). 4882 */ 4883 4884 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 4885 V_ULPTX_NSGE(nsegs)); 4886 usgl->len0 = htobe32(seg->ss_len); 4887 usgl->addr0 = htobe64(seg->ss_paddr); 4888 seg++; 4889 4890 if (checkwrap == 0 || (uintptr_t)(flitp + nflits) <= (uintptr_t)wrap) { 4891 4892 /* Won't wrap around at all */ 4893 4894 for (i = 0; i < nsegs - 1; i++, seg++) { 4895 usgl->sge[i / 2].len[i & 1] = htobe32(seg->ss_len); 4896 usgl->sge[i / 2].addr[i & 1] = htobe64(seg->ss_paddr); 4897 } 4898 if (i & 1) 4899 usgl->sge[i / 2].len[1] = htobe32(0); 4900 flitp += nflits; 4901 } else { 4902 4903 /* Will wrap somewhere in the rest of the SGL */ 4904 4905 /* 2 flits already written, write the rest flit by flit */ 4906 flitp = (void *)(usgl + 1); 4907 for (i = 0; i < nflits - 2; i++) { 4908 if (flitp == wrap) 4909 flitp = (void *)eq->desc; 4910 *flitp++ = get_flit(seg, nsegs - 1, i); 4911 } 4912 } 4913 4914 if (nflits & 1) { 4915 MPASS(((uintptr_t)flitp) & 0xf); 4916 *flitp++ = 0; 4917 } 4918 4919 MPASS((((uintptr_t)flitp) & 0xf) == 0); 4920 if (__predict_false(flitp == wrap)) 4921 *to = (void *)eq->desc; 4922 else 4923 *to = (void *)flitp; 4924 } 4925 4926 static inline void 4927 copy_to_txd(struct sge_eq *eq, caddr_t from, caddr_t *to, int len) 4928 { 4929 4930 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]); 4931 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]); 4932 4933 if (__predict_true((uintptr_t)(*to) + len <= 4934 (uintptr_t)&eq->desc[eq->sidx])) { 4935 bcopy(from, *to, len); 4936 (*to) += len; 4937 } else { 4938 int portion = (uintptr_t)&eq->desc[eq->sidx] - (uintptr_t)(*to); 4939 4940 bcopy(from, *to, portion); 4941 from += portion; 4942 portion = len - portion; /* remaining */ 4943 bcopy(from, (void *)eq->desc, portion); 4944 (*to) = (caddr_t)eq->desc + portion; 4945 } 4946 } 4947 4948 static inline void 4949 ring_eq_db(struct adapter *sc, struct sge_eq *eq, u_int n) 4950 { 4951 u_int db; 4952 4953 MPASS(n > 0); 4954 4955 db = eq->doorbells; 4956 if (n > 1) 4957 clrbit(&db, DOORBELL_WCWR); 4958 wmb(); 4959 4960 switch (ffs(db) - 1) { 4961 case DOORBELL_UDB: 4962 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n)); 4963 break; 4964 4965 case DOORBELL_WCWR: { 4966 volatile uint64_t *dst, *src; 4967 int i; 4968 4969 /* 4970 * Queues whose 128B doorbell segment fits in the page do not 4971 * use relative qid (udb_qid is always 0). Only queues with 4972 * doorbell segments can do WCWR. 4973 */ 4974 KASSERT(eq->udb_qid == 0 && n == 1, 4975 ("%s: inappropriate doorbell (0x%x, %d, %d) for eq %p", 4976 __func__, eq->doorbells, n, eq->dbidx, eq)); 4977 4978 dst = (volatile void *)((uintptr_t)eq->udb + UDBS_WR_OFFSET - 4979 UDBS_DB_OFFSET); 4980 i = eq->dbidx; 4981 src = (void *)&eq->desc[i]; 4982 while (src != (void *)&eq->desc[i + 1]) 4983 *dst++ = *src++; 4984 wmb(); 4985 break; 4986 } 4987 4988 case DOORBELL_UDBWC: 4989 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n)); 4990 wmb(); 4991 break; 4992 4993 case DOORBELL_KDB: 4994 t4_write_reg(sc, sc->sge_kdoorbell_reg, 4995 V_QID(eq->cntxt_id) | V_PIDX(n)); 4996 break; 4997 } 4998 4999 IDXINCR(eq->dbidx, n, eq->sidx); 5000 } 5001 5002 static inline u_int 5003 reclaimable_tx_desc(struct sge_eq *eq) 5004 { 5005 uint16_t hw_cidx; 5006 5007 hw_cidx = read_hw_cidx(eq); 5008 return (IDXDIFF(hw_cidx, eq->cidx, eq->sidx)); 5009 } 5010 5011 static inline u_int 5012 total_available_tx_desc(struct sge_eq *eq) 5013 { 5014 uint16_t hw_cidx, pidx; 5015 5016 hw_cidx = read_hw_cidx(eq); 5017 pidx = eq->pidx; 5018 5019 if (pidx == hw_cidx) 5020 return (eq->sidx - 1); 5021 else 5022 return (IDXDIFF(hw_cidx, pidx, eq->sidx) - 1); 5023 } 5024 5025 static inline uint16_t 5026 read_hw_cidx(struct sge_eq *eq) 5027 { 5028 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx]; 5029 uint16_t cidx = spg->cidx; /* stable snapshot */ 5030 5031 return (be16toh(cidx)); 5032 } 5033 5034 /* 5035 * Reclaim 'n' descriptors approximately. 5036 */ 5037 static u_int 5038 reclaim_tx_descs(struct sge_txq *txq, u_int n) 5039 { 5040 struct tx_sdesc *txsd; 5041 struct sge_eq *eq = &txq->eq; 5042 u_int can_reclaim, reclaimed; 5043 5044 TXQ_LOCK_ASSERT_OWNED(txq); 5045 MPASS(n > 0); 5046 5047 reclaimed = 0; 5048 can_reclaim = reclaimable_tx_desc(eq); 5049 while (can_reclaim && reclaimed < n) { 5050 int ndesc; 5051 struct mbuf *m, *nextpkt; 5052 5053 txsd = &txq->sdesc[eq->cidx]; 5054 ndesc = txsd->desc_used; 5055 5056 /* Firmware doesn't return "partial" credits. */ 5057 KASSERT(can_reclaim >= ndesc, 5058 ("%s: unexpected number of credits: %d, %d", 5059 __func__, can_reclaim, ndesc)); 5060 5061 for (m = txsd->m; m != NULL; m = nextpkt) { 5062 nextpkt = m->m_nextpkt; 5063 m->m_nextpkt = NULL; 5064 m_freem(m); 5065 } 5066 reclaimed += ndesc; 5067 can_reclaim -= ndesc; 5068 IDXINCR(eq->cidx, ndesc, eq->sidx); 5069 } 5070 5071 return (reclaimed); 5072 } 5073 5074 static void 5075 tx_reclaim(void *arg, int n) 5076 { 5077 struct sge_txq *txq = arg; 5078 struct sge_eq *eq = &txq->eq; 5079 5080 do { 5081 if (TXQ_TRYLOCK(txq) == 0) 5082 break; 5083 n = reclaim_tx_descs(txq, 32); 5084 if (eq->cidx == eq->pidx) 5085 eq->equeqidx = eq->pidx; 5086 TXQ_UNLOCK(txq); 5087 } while (n > 0); 5088 } 5089 5090 static __be64 5091 get_flit(struct sglist_seg *segs, int nsegs, int idx) 5092 { 5093 int i = (idx / 3) * 2; 5094 5095 switch (idx % 3) { 5096 case 0: { 5097 uint64_t rc; 5098 5099 rc = (uint64_t)segs[i].ss_len << 32; 5100 if (i + 1 < nsegs) 5101 rc |= (uint64_t)(segs[i + 1].ss_len); 5102 5103 return (htobe64(rc)); 5104 } 5105 case 1: 5106 return (htobe64(segs[i].ss_paddr)); 5107 case 2: 5108 return (htobe64(segs[i + 1].ss_paddr)); 5109 } 5110 5111 return (0); 5112 } 5113 5114 static void 5115 find_best_refill_source(struct adapter *sc, struct sge_fl *fl, int maxp) 5116 { 5117 int8_t zidx, hwidx, idx; 5118 uint16_t region1, region3; 5119 int spare, spare_needed, n; 5120 struct sw_zone_info *swz; 5121 struct hw_buf_info *hwb, *hwb_list = &sc->sge.hw_buf_info[0]; 5122 5123 /* 5124 * Buffer Packing: Look for PAGE_SIZE or larger zone which has a bufsize 5125 * large enough for the max payload and cluster metadata. Otherwise 5126 * settle for the largest bufsize that leaves enough room in the cluster 5127 * for metadata. 5128 * 5129 * Without buffer packing: Look for the smallest zone which has a 5130 * bufsize large enough for the max payload. Settle for the largest 5131 * bufsize available if there's nothing big enough for max payload. 5132 */ 5133 spare_needed = fl->flags & FL_BUF_PACKING ? CL_METADATA_SIZE : 0; 5134 swz = &sc->sge.sw_zone_info[0]; 5135 hwidx = -1; 5136 for (zidx = 0; zidx < SW_ZONE_SIZES; zidx++, swz++) { 5137 if (swz->size > largest_rx_cluster) { 5138 if (__predict_true(hwidx != -1)) 5139 break; 5140 5141 /* 5142 * This is a misconfiguration. largest_rx_cluster is 5143 * preventing us from finding a refill source. See 5144 * dev.t5nex.<n>.buffer_sizes to figure out why. 5145 */ 5146 device_printf(sc->dev, "largest_rx_cluster=%u leaves no" 5147 " refill source for fl %p (dma %u). Ignored.\n", 5148 largest_rx_cluster, fl, maxp); 5149 } 5150 for (idx = swz->head_hwidx; idx != -1; idx = hwb->next) { 5151 hwb = &hwb_list[idx]; 5152 spare = swz->size - hwb->size; 5153 if (spare < spare_needed) 5154 continue; 5155 5156 hwidx = idx; /* best option so far */ 5157 if (hwb->size >= maxp) { 5158 5159 if ((fl->flags & FL_BUF_PACKING) == 0) 5160 goto done; /* stop looking (not packing) */ 5161 5162 if (swz->size >= safest_rx_cluster) 5163 goto done; /* stop looking (packing) */ 5164 } 5165 break; /* keep looking, next zone */ 5166 } 5167 } 5168 done: 5169 /* A usable hwidx has been located. */ 5170 MPASS(hwidx != -1); 5171 hwb = &hwb_list[hwidx]; 5172 zidx = hwb->zidx; 5173 swz = &sc->sge.sw_zone_info[zidx]; 5174 region1 = 0; 5175 region3 = swz->size - hwb->size; 5176 5177 /* 5178 * Stay within this zone and see if there is a better match when mbuf 5179 * inlining is allowed. Remember that the hwidx's are sorted in 5180 * decreasing order of size (so in increasing order of spare area). 5181 */ 5182 for (idx = hwidx; idx != -1; idx = hwb->next) { 5183 hwb = &hwb_list[idx]; 5184 spare = swz->size - hwb->size; 5185 5186 if (allow_mbufs_in_cluster == 0 || hwb->size < maxp) 5187 break; 5188 5189 /* 5190 * Do not inline mbufs if doing so would violate the pad/pack 5191 * boundary alignment requirement. 5192 */ 5193 if (fl_pad && (MSIZE % sc->params.sge.pad_boundary) != 0) 5194 continue; 5195 if (fl->flags & FL_BUF_PACKING && 5196 (MSIZE % sc->params.sge.pack_boundary) != 0) 5197 continue; 5198 5199 if (spare < CL_METADATA_SIZE + MSIZE) 5200 continue; 5201 n = (spare - CL_METADATA_SIZE) / MSIZE; 5202 if (n > howmany(hwb->size, maxp)) 5203 break; 5204 5205 hwidx = idx; 5206 if (fl->flags & FL_BUF_PACKING) { 5207 region1 = n * MSIZE; 5208 region3 = spare - region1; 5209 } else { 5210 region1 = MSIZE; 5211 region3 = spare - region1; 5212 break; 5213 } 5214 } 5215 5216 KASSERT(zidx >= 0 && zidx < SW_ZONE_SIZES, 5217 ("%s: bad zone %d for fl %p, maxp %d", __func__, zidx, fl, maxp)); 5218 KASSERT(hwidx >= 0 && hwidx <= SGE_FLBUF_SIZES, 5219 ("%s: bad hwidx %d for fl %p, maxp %d", __func__, hwidx, fl, maxp)); 5220 KASSERT(region1 + sc->sge.hw_buf_info[hwidx].size + region3 == 5221 sc->sge.sw_zone_info[zidx].size, 5222 ("%s: bad buffer layout for fl %p, maxp %d. " 5223 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp, 5224 sc->sge.sw_zone_info[zidx].size, region1, 5225 sc->sge.hw_buf_info[hwidx].size, region3)); 5226 if (fl->flags & FL_BUF_PACKING || region1 > 0) { 5227 KASSERT(region3 >= CL_METADATA_SIZE, 5228 ("%s: no room for metadata. fl %p, maxp %d; " 5229 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp, 5230 sc->sge.sw_zone_info[zidx].size, region1, 5231 sc->sge.hw_buf_info[hwidx].size, region3)); 5232 KASSERT(region1 % MSIZE == 0, 5233 ("%s: bad mbuf region for fl %p, maxp %d. " 5234 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp, 5235 sc->sge.sw_zone_info[zidx].size, region1, 5236 sc->sge.hw_buf_info[hwidx].size, region3)); 5237 } 5238 5239 fl->cll_def.zidx = zidx; 5240 fl->cll_def.hwidx = hwidx; 5241 fl->cll_def.region1 = region1; 5242 fl->cll_def.region3 = region3; 5243 } 5244 5245 static void 5246 find_safe_refill_source(struct adapter *sc, struct sge_fl *fl) 5247 { 5248 struct sge *s = &sc->sge; 5249 struct hw_buf_info *hwb; 5250 struct sw_zone_info *swz; 5251 int spare; 5252 int8_t hwidx; 5253 5254 if (fl->flags & FL_BUF_PACKING) 5255 hwidx = s->safe_hwidx2; /* with room for metadata */ 5256 else if (allow_mbufs_in_cluster && s->safe_hwidx2 != -1) { 5257 hwidx = s->safe_hwidx2; 5258 hwb = &s->hw_buf_info[hwidx]; 5259 swz = &s->sw_zone_info[hwb->zidx]; 5260 spare = swz->size - hwb->size; 5261 5262 /* no good if there isn't room for an mbuf as well */ 5263 if (spare < CL_METADATA_SIZE + MSIZE) 5264 hwidx = s->safe_hwidx1; 5265 } else 5266 hwidx = s->safe_hwidx1; 5267 5268 if (hwidx == -1) { 5269 /* No fallback source */ 5270 fl->cll_alt.hwidx = -1; 5271 fl->cll_alt.zidx = -1; 5272 5273 return; 5274 } 5275 5276 hwb = &s->hw_buf_info[hwidx]; 5277 swz = &s->sw_zone_info[hwb->zidx]; 5278 spare = swz->size - hwb->size; 5279 fl->cll_alt.hwidx = hwidx; 5280 fl->cll_alt.zidx = hwb->zidx; 5281 if (allow_mbufs_in_cluster && 5282 (fl_pad == 0 || (MSIZE % sc->params.sge.pad_boundary) == 0)) 5283 fl->cll_alt.region1 = ((spare - CL_METADATA_SIZE) / MSIZE) * MSIZE; 5284 else 5285 fl->cll_alt.region1 = 0; 5286 fl->cll_alt.region3 = spare - fl->cll_alt.region1; 5287 } 5288 5289 static void 5290 add_fl_to_sfl(struct adapter *sc, struct sge_fl *fl) 5291 { 5292 mtx_lock(&sc->sfl_lock); 5293 FL_LOCK(fl); 5294 if ((fl->flags & FL_DOOMED) == 0) { 5295 fl->flags |= FL_STARVING; 5296 TAILQ_INSERT_TAIL(&sc->sfl, fl, link); 5297 callout_reset(&sc->sfl_callout, hz / 5, refill_sfl, sc); 5298 } 5299 FL_UNLOCK(fl); 5300 mtx_unlock(&sc->sfl_lock); 5301 } 5302 5303 static void 5304 handle_wrq_egr_update(struct adapter *sc, struct sge_eq *eq) 5305 { 5306 struct sge_wrq *wrq = (void *)eq; 5307 5308 atomic_readandclear_int(&eq->equiq); 5309 taskqueue_enqueue(sc->tq[eq->tx_chan], &wrq->wrq_tx_task); 5310 } 5311 5312 static void 5313 handle_eth_egr_update(struct adapter *sc, struct sge_eq *eq) 5314 { 5315 struct sge_txq *txq = (void *)eq; 5316 5317 MPASS((eq->flags & EQ_TYPEMASK) == EQ_ETH); 5318 5319 atomic_readandclear_int(&eq->equiq); 5320 mp_ring_check_drainage(txq->r, 0); 5321 taskqueue_enqueue(sc->tq[eq->tx_chan], &txq->tx_reclaim_task); 5322 } 5323 5324 static int 5325 handle_sge_egr_update(struct sge_iq *iq, const struct rss_header *rss, 5326 struct mbuf *m) 5327 { 5328 const struct cpl_sge_egr_update *cpl = (const void *)(rss + 1); 5329 unsigned int qid = G_EGR_QID(ntohl(cpl->opcode_qid)); 5330 struct adapter *sc = iq->adapter; 5331 struct sge *s = &sc->sge; 5332 struct sge_eq *eq; 5333 static void (*h[])(struct adapter *, struct sge_eq *) = {NULL, 5334 &handle_wrq_egr_update, &handle_eth_egr_update, 5335 &handle_wrq_egr_update}; 5336 5337 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 5338 rss->opcode)); 5339 5340 eq = s->eqmap[qid - s->eq_start - s->eq_base]; 5341 (*h[eq->flags & EQ_TYPEMASK])(sc, eq); 5342 5343 return (0); 5344 } 5345 5346 /* handle_fw_msg works for both fw4_msg and fw6_msg because this is valid */ 5347 CTASSERT(offsetof(struct cpl_fw4_msg, data) == \ 5348 offsetof(struct cpl_fw6_msg, data)); 5349 5350 static int 5351 handle_fw_msg(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 5352 { 5353 struct adapter *sc = iq->adapter; 5354 const struct cpl_fw6_msg *cpl = (const void *)(rss + 1); 5355 5356 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 5357 rss->opcode)); 5358 5359 if (cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL) { 5360 const struct rss_header *rss2; 5361 5362 rss2 = (const struct rss_header *)&cpl->data[0]; 5363 return (t4_cpl_handler[rss2->opcode](iq, rss2, m)); 5364 } 5365 5366 return (t4_fw_msg_handler[cpl->type](sc, &cpl->data[0])); 5367 } 5368 5369 /** 5370 * t4_handle_wrerr_rpl - process a FW work request error message 5371 * @adap: the adapter 5372 * @rpl: start of the FW message 5373 */ 5374 static int 5375 t4_handle_wrerr_rpl(struct adapter *adap, const __be64 *rpl) 5376 { 5377 u8 opcode = *(const u8 *)rpl; 5378 const struct fw_error_cmd *e = (const void *)rpl; 5379 unsigned int i; 5380 5381 if (opcode != FW_ERROR_CMD) { 5382 log(LOG_ERR, 5383 "%s: Received WRERR_RPL message with opcode %#x\n", 5384 device_get_nameunit(adap->dev), opcode); 5385 return (EINVAL); 5386 } 5387 log(LOG_ERR, "%s: FW_ERROR (%s) ", device_get_nameunit(adap->dev), 5388 G_FW_ERROR_CMD_FATAL(be32toh(e->op_to_type)) ? "fatal" : 5389 "non-fatal"); 5390 switch (G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type))) { 5391 case FW_ERROR_TYPE_EXCEPTION: 5392 log(LOG_ERR, "exception info:\n"); 5393 for (i = 0; i < nitems(e->u.exception.info); i++) 5394 log(LOG_ERR, "%s%08x", i == 0 ? "\t" : " ", 5395 be32toh(e->u.exception.info[i])); 5396 log(LOG_ERR, "\n"); 5397 break; 5398 case FW_ERROR_TYPE_HWMODULE: 5399 log(LOG_ERR, "HW module regaddr %08x regval %08x\n", 5400 be32toh(e->u.hwmodule.regaddr), 5401 be32toh(e->u.hwmodule.regval)); 5402 break; 5403 case FW_ERROR_TYPE_WR: 5404 log(LOG_ERR, "WR cidx %d PF %d VF %d eqid %d hdr:\n", 5405 be16toh(e->u.wr.cidx), 5406 G_FW_ERROR_CMD_PFN(be16toh(e->u.wr.pfn_vfn)), 5407 G_FW_ERROR_CMD_VFN(be16toh(e->u.wr.pfn_vfn)), 5408 be32toh(e->u.wr.eqid)); 5409 for (i = 0; i < nitems(e->u.wr.wrhdr); i++) 5410 log(LOG_ERR, "%s%02x", i == 0 ? "\t" : " ", 5411 e->u.wr.wrhdr[i]); 5412 log(LOG_ERR, "\n"); 5413 break; 5414 case FW_ERROR_TYPE_ACL: 5415 log(LOG_ERR, "ACL cidx %d PF %d VF %d eqid %d %s", 5416 be16toh(e->u.acl.cidx), 5417 G_FW_ERROR_CMD_PFN(be16toh(e->u.acl.pfn_vfn)), 5418 G_FW_ERROR_CMD_VFN(be16toh(e->u.acl.pfn_vfn)), 5419 be32toh(e->u.acl.eqid), 5420 G_FW_ERROR_CMD_MV(be16toh(e->u.acl.mv_pkd)) ? "vlanid" : 5421 "MAC"); 5422 for (i = 0; i < nitems(e->u.acl.val); i++) 5423 log(LOG_ERR, " %02x", e->u.acl.val[i]); 5424 log(LOG_ERR, "\n"); 5425 break; 5426 default: 5427 log(LOG_ERR, "type %#x\n", 5428 G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type))); 5429 return (EINVAL); 5430 } 5431 return (0); 5432 } 5433 5434 static int 5435 sysctl_uint16(SYSCTL_HANDLER_ARGS) 5436 { 5437 uint16_t *id = arg1; 5438 int i = *id; 5439 5440 return sysctl_handle_int(oidp, &i, 0, req); 5441 } 5442 5443 static int 5444 sysctl_bufsizes(SYSCTL_HANDLER_ARGS) 5445 { 5446 struct sge *s = arg1; 5447 struct hw_buf_info *hwb = &s->hw_buf_info[0]; 5448 struct sw_zone_info *swz = &s->sw_zone_info[0]; 5449 int i, rc; 5450 struct sbuf sb; 5451 char c; 5452 5453 sbuf_new(&sb, NULL, 32, SBUF_AUTOEXTEND); 5454 for (i = 0; i < SGE_FLBUF_SIZES; i++, hwb++) { 5455 if (hwb->zidx >= 0 && swz[hwb->zidx].size <= largest_rx_cluster) 5456 c = '*'; 5457 else 5458 c = '\0'; 5459 5460 sbuf_printf(&sb, "%u%c ", hwb->size, c); 5461 } 5462 sbuf_trim(&sb); 5463 sbuf_finish(&sb); 5464 rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req); 5465 sbuf_delete(&sb); 5466 return (rc); 5467 } 5468 5469 #ifdef RATELIMIT 5470 /* 5471 * len16 for a txpkt WR with a GL. Includes the firmware work request header. 5472 */ 5473 static inline u_int 5474 txpkt_eo_len16(u_int nsegs, u_int immhdrs, u_int tso) 5475 { 5476 u_int n; 5477 5478 MPASS(immhdrs > 0); 5479 5480 n = roundup2(sizeof(struct fw_eth_tx_eo_wr) + 5481 sizeof(struct cpl_tx_pkt_core) + immhdrs, 16); 5482 if (__predict_false(nsegs == 0)) 5483 goto done; 5484 5485 nsegs--; /* first segment is part of ulptx_sgl */ 5486 n += sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 5487 if (tso) 5488 n += sizeof(struct cpl_tx_pkt_lso_core); 5489 5490 done: 5491 return (howmany(n, 16)); 5492 } 5493 5494 #define ETID_FLOWC_NPARAMS 6 5495 #define ETID_FLOWC_LEN (roundup2((sizeof(struct fw_flowc_wr) + \ 5496 ETID_FLOWC_NPARAMS * sizeof(struct fw_flowc_mnemval)), 16)) 5497 #define ETID_FLOWC_LEN16 (howmany(ETID_FLOWC_LEN, 16)) 5498 5499 static int 5500 send_etid_flowc_wr(struct cxgbe_snd_tag *cst, struct port_info *pi, 5501 struct vi_info *vi) 5502 { 5503 struct wrq_cookie cookie; 5504 u_int pfvf = G_FW_VIID_PFN(vi->viid) << S_FW_VIID_PFN; 5505 struct fw_flowc_wr *flowc; 5506 5507 mtx_assert(&cst->lock, MA_OWNED); 5508 MPASS((cst->flags & (EO_FLOWC_PENDING | EO_FLOWC_RPL_PENDING)) == 5509 EO_FLOWC_PENDING); 5510 5511 flowc = start_wrq_wr(cst->eo_txq, ETID_FLOWC_LEN16, &cookie); 5512 if (__predict_false(flowc == NULL)) 5513 return (ENOMEM); 5514 5515 bzero(flowc, ETID_FLOWC_LEN); 5516 flowc->op_to_nparams = htobe32(V_FW_WR_OP(FW_FLOWC_WR) | 5517 V_FW_FLOWC_WR_NPARAMS(ETID_FLOWC_NPARAMS) | V_FW_WR_COMPL(0)); 5518 flowc->flowid_len16 = htonl(V_FW_WR_LEN16(ETID_FLOWC_LEN16) | 5519 V_FW_WR_FLOWID(cst->etid)); 5520 flowc->mnemval[0].mnemonic = FW_FLOWC_MNEM_PFNVFN; 5521 flowc->mnemval[0].val = htobe32(pfvf); 5522 flowc->mnemval[1].mnemonic = FW_FLOWC_MNEM_CH; 5523 flowc->mnemval[1].val = htobe32(pi->tx_chan); 5524 flowc->mnemval[2].mnemonic = FW_FLOWC_MNEM_PORT; 5525 flowc->mnemval[2].val = htobe32(pi->tx_chan); 5526 flowc->mnemval[3].mnemonic = FW_FLOWC_MNEM_IQID; 5527 flowc->mnemval[3].val = htobe32(cst->iqid); 5528 flowc->mnemval[4].mnemonic = FW_FLOWC_MNEM_EOSTATE; 5529 flowc->mnemval[4].val = htobe32(FW_FLOWC_MNEM_EOSTATE_ESTABLISHED); 5530 flowc->mnemval[5].mnemonic = FW_FLOWC_MNEM_SCHEDCLASS; 5531 flowc->mnemval[5].val = htobe32(cst->schedcl); 5532 5533 commit_wrq_wr(cst->eo_txq, flowc, &cookie); 5534 5535 cst->flags &= ~EO_FLOWC_PENDING; 5536 cst->flags |= EO_FLOWC_RPL_PENDING; 5537 MPASS(cst->tx_credits >= ETID_FLOWC_LEN16); /* flowc is first WR. */ 5538 cst->tx_credits -= ETID_FLOWC_LEN16; 5539 5540 return (0); 5541 } 5542 5543 #define ETID_FLUSH_LEN16 (howmany(sizeof (struct fw_flowc_wr), 16)) 5544 5545 void 5546 send_etid_flush_wr(struct cxgbe_snd_tag *cst) 5547 { 5548 struct fw_flowc_wr *flowc; 5549 struct wrq_cookie cookie; 5550 5551 mtx_assert(&cst->lock, MA_OWNED); 5552 5553 flowc = start_wrq_wr(cst->eo_txq, ETID_FLUSH_LEN16, &cookie); 5554 if (__predict_false(flowc == NULL)) 5555 CXGBE_UNIMPLEMENTED(__func__); 5556 5557 bzero(flowc, ETID_FLUSH_LEN16 * 16); 5558 flowc->op_to_nparams = htobe32(V_FW_WR_OP(FW_FLOWC_WR) | 5559 V_FW_FLOWC_WR_NPARAMS(0) | F_FW_WR_COMPL); 5560 flowc->flowid_len16 = htobe32(V_FW_WR_LEN16(ETID_FLUSH_LEN16) | 5561 V_FW_WR_FLOWID(cst->etid)); 5562 5563 commit_wrq_wr(cst->eo_txq, flowc, &cookie); 5564 5565 cst->flags |= EO_FLUSH_RPL_PENDING; 5566 MPASS(cst->tx_credits >= ETID_FLUSH_LEN16); 5567 cst->tx_credits -= ETID_FLUSH_LEN16; 5568 cst->ncompl++; 5569 } 5570 5571 static void 5572 write_ethofld_wr(struct cxgbe_snd_tag *cst, struct fw_eth_tx_eo_wr *wr, 5573 struct mbuf *m0, int compl) 5574 { 5575 struct cpl_tx_pkt_core *cpl; 5576 uint64_t ctrl1; 5577 uint32_t ctrl; /* used in many unrelated places */ 5578 int len16, pktlen, nsegs, immhdrs; 5579 caddr_t dst; 5580 uintptr_t p; 5581 struct ulptx_sgl *usgl; 5582 struct sglist sg; 5583 struct sglist_seg segs[38]; /* XXX: find real limit. XXX: get off the stack */ 5584 5585 mtx_assert(&cst->lock, MA_OWNED); 5586 M_ASSERTPKTHDR(m0); 5587 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 5588 m0->m_pkthdr.l4hlen > 0, 5589 ("%s: ethofld mbuf %p is missing header lengths", __func__, m0)); 5590 5591 if (needs_udp_csum(m0)) { 5592 CXGBE_UNIMPLEMENTED("UDP ethofld"); 5593 } 5594 5595 len16 = mbuf_eo_len16(m0); 5596 nsegs = mbuf_eo_nsegs(m0); 5597 pktlen = m0->m_pkthdr.len; 5598 ctrl = sizeof(struct cpl_tx_pkt_core); 5599 if (needs_tso(m0)) 5600 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 5601 immhdrs = m0->m_pkthdr.l2hlen + m0->m_pkthdr.l3hlen + m0->m_pkthdr.l4hlen; 5602 ctrl += immhdrs; 5603 5604 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_EO_WR) | 5605 V_FW_ETH_TX_EO_WR_IMMDLEN(ctrl) | V_FW_WR_COMPL(!!compl)); 5606 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(len16) | 5607 V_FW_WR_FLOWID(cst->etid)); 5608 wr->r3 = 0; 5609 wr->u.tcpseg.type = FW_ETH_TX_EO_TYPE_TCPSEG; 5610 wr->u.tcpseg.ethlen = m0->m_pkthdr.l2hlen; 5611 wr->u.tcpseg.iplen = htobe16(m0->m_pkthdr.l3hlen); 5612 wr->u.tcpseg.tcplen = m0->m_pkthdr.l4hlen; 5613 wr->u.tcpseg.tsclk_tsoff = mbuf_eo_tsclk_tsoff(m0); 5614 wr->u.tcpseg.r4 = 0; 5615 wr->u.tcpseg.r5 = 0; 5616 wr->u.tcpseg.plen = htobe32(pktlen - immhdrs); 5617 5618 if (needs_tso(m0)) { 5619 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1); 5620 5621 wr->u.tcpseg.mss = htobe16(m0->m_pkthdr.tso_segsz); 5622 5623 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE | 5624 F_LSO_LAST_SLICE | V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) 5625 | V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2); 5626 if (m0->m_pkthdr.l2hlen == sizeof(struct ether_vlan_header)) 5627 ctrl |= V_LSO_ETHHDR_LEN(1); 5628 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 5629 ctrl |= F_LSO_IPV6; 5630 lso->lso_ctrl = htobe32(ctrl); 5631 lso->ipid_ofst = htobe16(0); 5632 lso->mss = htobe16(m0->m_pkthdr.tso_segsz); 5633 lso->seqno_offset = htobe32(0); 5634 lso->len = htobe32(pktlen); 5635 5636 cpl = (void *)(lso + 1); 5637 } else { 5638 wr->u.tcpseg.mss = htobe16(0xffff); 5639 cpl = (void *)(wr + 1); 5640 } 5641 5642 /* Checksum offload must be requested for ethofld. */ 5643 ctrl1 = 0; 5644 MPASS(needs_l4_csum(m0)); 5645 5646 /* VLAN tag insertion */ 5647 if (needs_vlan_insertion(m0)) { 5648 ctrl1 |= F_TXPKT_VLAN_VLD | 5649 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 5650 } 5651 5652 /* CPL header */ 5653 cpl->ctrl0 = cst->ctrl0; 5654 cpl->pack = 0; 5655 cpl->len = htobe16(pktlen); 5656 cpl->ctrl1 = htobe64(ctrl1); 5657 5658 /* Copy Ethernet, IP & TCP hdrs as immediate data */ 5659 p = (uintptr_t)(cpl + 1); 5660 m_copydata(m0, 0, immhdrs, (void *)p); 5661 5662 /* SGL */ 5663 dst = (void *)(cpl + 1); 5664 if (nsegs > 0) { 5665 int i, pad; 5666 5667 /* zero-pad upto next 16Byte boundary, if not 16Byte aligned */ 5668 p += immhdrs; 5669 pad = 16 - (immhdrs & 0xf); 5670 bzero((void *)p, pad); 5671 5672 usgl = (void *)(p + pad); 5673 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 5674 V_ULPTX_NSGE(nsegs)); 5675 5676 sglist_init(&sg, nitems(segs), segs); 5677 for (; m0 != NULL; m0 = m0->m_next) { 5678 if (__predict_false(m0->m_len == 0)) 5679 continue; 5680 if (immhdrs >= m0->m_len) { 5681 immhdrs -= m0->m_len; 5682 continue; 5683 } 5684 5685 sglist_append(&sg, mtod(m0, char *) + immhdrs, 5686 m0->m_len - immhdrs); 5687 immhdrs = 0; 5688 } 5689 MPASS(sg.sg_nseg == nsegs); 5690 5691 /* 5692 * Zero pad last 8B in case the WR doesn't end on a 16B 5693 * boundary. 5694 */ 5695 *(uint64_t *)((char *)wr + len16 * 16 - 8) = 0; 5696 5697 usgl->len0 = htobe32(segs[0].ss_len); 5698 usgl->addr0 = htobe64(segs[0].ss_paddr); 5699 for (i = 0; i < nsegs - 1; i++) { 5700 usgl->sge[i / 2].len[i & 1] = htobe32(segs[i + 1].ss_len); 5701 usgl->sge[i / 2].addr[i & 1] = htobe64(segs[i + 1].ss_paddr); 5702 } 5703 if (i & 1) 5704 usgl->sge[i / 2].len[1] = htobe32(0); 5705 } 5706 5707 } 5708 5709 static void 5710 ethofld_tx(struct cxgbe_snd_tag *cst) 5711 { 5712 struct mbuf *m; 5713 struct wrq_cookie cookie; 5714 int next_credits, compl; 5715 struct fw_eth_tx_eo_wr *wr; 5716 5717 mtx_assert(&cst->lock, MA_OWNED); 5718 5719 while ((m = mbufq_first(&cst->pending_tx)) != NULL) { 5720 M_ASSERTPKTHDR(m); 5721 5722 /* How many len16 credits do we need to send this mbuf. */ 5723 next_credits = mbuf_eo_len16(m); 5724 MPASS(next_credits > 0); 5725 if (next_credits > cst->tx_credits) { 5726 /* 5727 * Tx will make progress eventually because there is at 5728 * least one outstanding fw4_ack that will return 5729 * credits and kick the tx. 5730 */ 5731 MPASS(cst->ncompl > 0); 5732 return; 5733 } 5734 wr = start_wrq_wr(cst->eo_txq, next_credits, &cookie); 5735 if (__predict_false(wr == NULL)) { 5736 /* XXX: wishful thinking, not a real assertion. */ 5737 MPASS(cst->ncompl > 0); 5738 return; 5739 } 5740 cst->tx_credits -= next_credits; 5741 cst->tx_nocompl += next_credits; 5742 compl = cst->ncompl == 0 || cst->tx_nocompl >= cst->tx_total / 2; 5743 ETHER_BPF_MTAP(cst->com.ifp, m); 5744 write_ethofld_wr(cst, wr, m, compl); 5745 commit_wrq_wr(cst->eo_txq, wr, &cookie); 5746 if (compl) { 5747 cst->ncompl++; 5748 cst->tx_nocompl = 0; 5749 } 5750 (void) mbufq_dequeue(&cst->pending_tx); 5751 mbufq_enqueue(&cst->pending_fwack, m); 5752 } 5753 } 5754 5755 int 5756 ethofld_transmit(struct ifnet *ifp, struct mbuf *m0) 5757 { 5758 struct cxgbe_snd_tag *cst; 5759 int rc; 5760 5761 MPASS(m0->m_nextpkt == NULL); 5762 MPASS(m0->m_pkthdr.snd_tag != NULL); 5763 cst = mst_to_cst(m0->m_pkthdr.snd_tag); 5764 5765 mtx_lock(&cst->lock); 5766 MPASS(cst->flags & EO_SND_TAG_REF); 5767 5768 if (__predict_false(cst->flags & EO_FLOWC_PENDING)) { 5769 struct vi_info *vi = ifp->if_softc; 5770 struct port_info *pi = vi->pi; 5771 struct adapter *sc = pi->adapter; 5772 const uint32_t rss_mask = vi->rss_size - 1; 5773 uint32_t rss_hash; 5774 5775 cst->eo_txq = &sc->sge.ofld_txq[vi->first_ofld_txq]; 5776 if (M_HASHTYPE_ISHASH(m0)) 5777 rss_hash = m0->m_pkthdr.flowid; 5778 else 5779 rss_hash = arc4random(); 5780 /* We assume RSS hashing */ 5781 cst->iqid = vi->rss[rss_hash & rss_mask]; 5782 cst->eo_txq += rss_hash % vi->nofldtxq; 5783 rc = send_etid_flowc_wr(cst, pi, vi); 5784 if (rc != 0) 5785 goto done; 5786 } 5787 5788 if (__predict_false(cst->plen + m0->m_pkthdr.len > eo_max_backlog)) { 5789 rc = ENOBUFS; 5790 goto done; 5791 } 5792 5793 mbufq_enqueue(&cst->pending_tx, m0); 5794 cst->plen += m0->m_pkthdr.len; 5795 5796 ethofld_tx(cst); 5797 rc = 0; 5798 done: 5799 mtx_unlock(&cst->lock); 5800 if (__predict_false(rc != 0)) 5801 m_freem(m0); 5802 return (rc); 5803 } 5804 5805 static int 5806 ethofld_fw4_ack(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0) 5807 { 5808 struct adapter *sc = iq->adapter; 5809 const struct cpl_fw4_ack *cpl = (const void *)(rss + 1); 5810 struct mbuf *m; 5811 u_int etid = G_CPL_FW4_ACK_FLOWID(be32toh(OPCODE_TID(cpl))); 5812 struct cxgbe_snd_tag *cst; 5813 uint8_t credits = cpl->credits; 5814 5815 cst = lookup_etid(sc, etid); 5816 mtx_lock(&cst->lock); 5817 if (__predict_false(cst->flags & EO_FLOWC_RPL_PENDING)) { 5818 MPASS(credits >= ETID_FLOWC_LEN16); 5819 credits -= ETID_FLOWC_LEN16; 5820 cst->flags &= ~EO_FLOWC_RPL_PENDING; 5821 } 5822 5823 KASSERT(cst->ncompl > 0, 5824 ("%s: etid %u (%p) wasn't expecting completion.", 5825 __func__, etid, cst)); 5826 cst->ncompl--; 5827 5828 while (credits > 0) { 5829 m = mbufq_dequeue(&cst->pending_fwack); 5830 if (__predict_false(m == NULL)) { 5831 /* 5832 * The remaining credits are for the final flush that 5833 * was issued when the tag was freed by the kernel. 5834 */ 5835 MPASS((cst->flags & 5836 (EO_FLUSH_RPL_PENDING | EO_SND_TAG_REF)) == 5837 EO_FLUSH_RPL_PENDING); 5838 MPASS(credits == ETID_FLUSH_LEN16); 5839 MPASS(cst->tx_credits + cpl->credits == cst->tx_total); 5840 MPASS(cst->ncompl == 0); 5841 5842 cst->flags &= ~EO_FLUSH_RPL_PENDING; 5843 cst->tx_credits += cpl->credits; 5844 freetag: 5845 cxgbe_snd_tag_free_locked(cst); 5846 return (0); /* cst is gone. */ 5847 } 5848 KASSERT(m != NULL, 5849 ("%s: too many credits (%u, %u)", __func__, cpl->credits, 5850 credits)); 5851 KASSERT(credits >= mbuf_eo_len16(m), 5852 ("%s: too few credits (%u, %u, %u)", __func__, 5853 cpl->credits, credits, mbuf_eo_len16(m))); 5854 credits -= mbuf_eo_len16(m); 5855 cst->plen -= m->m_pkthdr.len; 5856 m_freem(m); 5857 } 5858 5859 cst->tx_credits += cpl->credits; 5860 MPASS(cst->tx_credits <= cst->tx_total); 5861 5862 m = mbufq_first(&cst->pending_tx); 5863 if (m != NULL && cst->tx_credits >= mbuf_eo_len16(m)) 5864 ethofld_tx(cst); 5865 5866 if (__predict_false((cst->flags & EO_SND_TAG_REF) == 0) && 5867 cst->ncompl == 0) { 5868 if (cst->tx_credits == cst->tx_total) 5869 goto freetag; 5870 else { 5871 MPASS((cst->flags & EO_FLUSH_RPL_PENDING) == 0); 5872 send_etid_flush_wr(cst); 5873 } 5874 } 5875 5876 mtx_unlock(&cst->lock); 5877 5878 return (0); 5879 } 5880 #endif 5881