1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 Chelsio Communications, Inc. 5 * All rights reserved. 6 * Written by: Navdeep Parhar <np@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include "opt_inet.h" 34 #include "opt_inet6.h" 35 #include "opt_ratelimit.h" 36 37 #include <sys/types.h> 38 #include <sys/eventhandler.h> 39 #include <sys/mbuf.h> 40 #include <sys/socket.h> 41 #include <sys/kernel.h> 42 #include <sys/malloc.h> 43 #include <sys/queue.h> 44 #include <sys/sbuf.h> 45 #include <sys/taskqueue.h> 46 #include <sys/time.h> 47 #include <sys/sglist.h> 48 #include <sys/sysctl.h> 49 #include <sys/smp.h> 50 #include <sys/counter.h> 51 #include <net/bpf.h> 52 #include <net/ethernet.h> 53 #include <net/if.h> 54 #include <net/if_vlan_var.h> 55 #include <netinet/in.h> 56 #include <netinet/ip.h> 57 #include <netinet/ip6.h> 58 #include <netinet/tcp.h> 59 #include <netinet/udp.h> 60 #include <machine/in_cksum.h> 61 #include <machine/md_var.h> 62 #include <vm/vm.h> 63 #include <vm/pmap.h> 64 #ifdef DEV_NETMAP 65 #include <machine/bus.h> 66 #include <sys/selinfo.h> 67 #include <net/if_var.h> 68 #include <net/netmap.h> 69 #include <dev/netmap/netmap_kern.h> 70 #endif 71 72 #include "common/common.h" 73 #include "common/t4_regs.h" 74 #include "common/t4_regs_values.h" 75 #include "common/t4_msg.h" 76 #include "t4_l2t.h" 77 #include "t4_mp_ring.h" 78 79 #ifdef T4_PKT_TIMESTAMP 80 #define RX_COPY_THRESHOLD (MINCLSIZE - 8) 81 #else 82 #define RX_COPY_THRESHOLD MINCLSIZE 83 #endif 84 85 /* Internal mbuf flags stored in PH_loc.eight[1]. */ 86 #define MC_RAW_WR 0x02 87 88 /* 89 * Ethernet frames are DMA'd at this byte offset into the freelist buffer. 90 * 0-7 are valid values. 91 */ 92 static int fl_pktshift = 0; 93 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pktshift, CTLFLAG_RDTUN, &fl_pktshift, 0, 94 "payload DMA offset in rx buffer (bytes)"); 95 96 /* 97 * Pad ethernet payload up to this boundary. 98 * -1: driver should figure out a good value. 99 * 0: disable padding. 100 * Any power of 2 from 32 to 4096 (both inclusive) is also a valid value. 101 */ 102 int fl_pad = -1; 103 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pad, CTLFLAG_RDTUN, &fl_pad, 0, 104 "payload pad boundary (bytes)"); 105 106 /* 107 * Status page length. 108 * -1: driver should figure out a good value. 109 * 64 or 128 are the only other valid values. 110 */ 111 static int spg_len = -1; 112 SYSCTL_INT(_hw_cxgbe, OID_AUTO, spg_len, CTLFLAG_RDTUN, &spg_len, 0, 113 "status page size (bytes)"); 114 115 /* 116 * Congestion drops. 117 * -1: no congestion feedback (not recommended). 118 * 0: backpressure the channel instead of dropping packets right away. 119 * 1: no backpressure, drop packets for the congested queue immediately. 120 */ 121 static int cong_drop = 0; 122 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cong_drop, CTLFLAG_RDTUN, &cong_drop, 0, 123 "Congestion control for RX queues (0 = backpressure, 1 = drop"); 124 125 /* 126 * Deliver multiple frames in the same free list buffer if they fit. 127 * -1: let the driver decide whether to enable buffer packing or not. 128 * 0: disable buffer packing. 129 * 1: enable buffer packing. 130 */ 131 static int buffer_packing = -1; 132 SYSCTL_INT(_hw_cxgbe, OID_AUTO, buffer_packing, CTLFLAG_RDTUN, &buffer_packing, 133 0, "Enable buffer packing"); 134 135 /* 136 * Start next frame in a packed buffer at this boundary. 137 * -1: driver should figure out a good value. 138 * T4: driver will ignore this and use the same value as fl_pad above. 139 * T5: 16, or a power of 2 from 64 to 4096 (both inclusive) is a valid value. 140 */ 141 static int fl_pack = -1; 142 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pack, CTLFLAG_RDTUN, &fl_pack, 0, 143 "payload pack boundary (bytes)"); 144 145 /* 146 * Allow the driver to create mbuf(s) in a cluster allocated for rx. 147 * 0: never; always allocate mbufs from the zone_mbuf UMA zone. 148 * 1: ok to create mbuf(s) within a cluster if there is room. 149 */ 150 static int allow_mbufs_in_cluster = 1; 151 SYSCTL_INT(_hw_cxgbe, OID_AUTO, allow_mbufs_in_cluster, CTLFLAG_RDTUN, 152 &allow_mbufs_in_cluster, 0, 153 "Allow driver to create mbufs within a rx cluster"); 154 155 /* 156 * Largest rx cluster size that the driver is allowed to allocate. 157 */ 158 static int largest_rx_cluster = MJUM16BYTES; 159 SYSCTL_INT(_hw_cxgbe, OID_AUTO, largest_rx_cluster, CTLFLAG_RDTUN, 160 &largest_rx_cluster, 0, "Largest rx cluster (bytes)"); 161 162 /* 163 * Size of cluster allocation that's most likely to succeed. The driver will 164 * fall back to this size if it fails to allocate clusters larger than this. 165 */ 166 static int safest_rx_cluster = PAGE_SIZE; 167 SYSCTL_INT(_hw_cxgbe, OID_AUTO, safest_rx_cluster, CTLFLAG_RDTUN, 168 &safest_rx_cluster, 0, "Safe rx cluster (bytes)"); 169 170 #ifdef RATELIMIT 171 /* 172 * Knob to control TCP timestamp rewriting, and the granularity of the tick used 173 * for rewriting. -1 and 0-3 are all valid values. 174 * -1: hardware should leave the TCP timestamps alone. 175 * 0: 1ms 176 * 1: 100us 177 * 2: 10us 178 * 3: 1us 179 */ 180 static int tsclk = -1; 181 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tsclk, CTLFLAG_RDTUN, &tsclk, 0, 182 "Control TCP timestamp rewriting when using pacing"); 183 184 static int eo_max_backlog = 1024 * 1024; 185 SYSCTL_INT(_hw_cxgbe, OID_AUTO, eo_max_backlog, CTLFLAG_RDTUN, &eo_max_backlog, 186 0, "Maximum backlog of ratelimited data per flow"); 187 #endif 188 189 /* 190 * The interrupt holdoff timers are multiplied by this value on T6+. 191 * 1 and 3-17 (both inclusive) are legal values. 192 */ 193 static int tscale = 1; 194 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tscale, CTLFLAG_RDTUN, &tscale, 0, 195 "Interrupt holdoff timer scale on T6+"); 196 197 /* 198 * Number of LRO entries in the lro_ctrl structure per rx queue. 199 */ 200 static int lro_entries = TCP_LRO_ENTRIES; 201 SYSCTL_INT(_hw_cxgbe, OID_AUTO, lro_entries, CTLFLAG_RDTUN, &lro_entries, 0, 202 "Number of LRO entries per RX queue"); 203 204 /* 205 * This enables presorting of frames before they're fed into tcp_lro_rx. 206 */ 207 static int lro_mbufs = 0; 208 SYSCTL_INT(_hw_cxgbe, OID_AUTO, lro_mbufs, CTLFLAG_RDTUN, &lro_mbufs, 0, 209 "Enable presorting of LRO frames"); 210 211 struct txpkts { 212 u_int wr_type; /* type 0 or type 1 */ 213 u_int npkt; /* # of packets in this work request */ 214 u_int plen; /* total payload (sum of all packets) */ 215 u_int len16; /* # of 16B pieces used by this work request */ 216 }; 217 218 /* A packet's SGL. This + m_pkthdr has all info needed for tx */ 219 struct sgl { 220 struct sglist sg; 221 struct sglist_seg seg[TX_SGL_SEGS]; 222 }; 223 224 static int service_iq(struct sge_iq *, int); 225 static int service_iq_fl(struct sge_iq *, int); 226 static struct mbuf *get_fl_payload(struct adapter *, struct sge_fl *, uint32_t); 227 static int t4_eth_rx(struct sge_iq *, const struct rss_header *, struct mbuf *); 228 static inline void init_iq(struct sge_iq *, struct adapter *, int, int, int); 229 static inline void init_fl(struct adapter *, struct sge_fl *, int, int, char *); 230 static inline void init_eq(struct adapter *, struct sge_eq *, int, int, uint8_t, 231 uint16_t, char *); 232 static int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *, 233 bus_addr_t *, void **); 234 static int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 235 void *); 236 static int alloc_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *, 237 int, int); 238 static int free_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *); 239 static void add_iq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *, 240 struct sge_iq *); 241 static void add_fl_sysctls(struct adapter *, struct sysctl_ctx_list *, 242 struct sysctl_oid *, struct sge_fl *); 243 static int alloc_fwq(struct adapter *); 244 static int free_fwq(struct adapter *); 245 static int alloc_ctrlq(struct adapter *, struct sge_wrq *, int, 246 struct sysctl_oid *); 247 static int alloc_rxq(struct vi_info *, struct sge_rxq *, int, int, 248 struct sysctl_oid *); 249 static int free_rxq(struct vi_info *, struct sge_rxq *); 250 #ifdef TCP_OFFLOAD 251 static int alloc_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *, int, int, 252 struct sysctl_oid *); 253 static int free_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *); 254 #endif 255 #ifdef DEV_NETMAP 256 static int alloc_nm_rxq(struct vi_info *, struct sge_nm_rxq *, int, int, 257 struct sysctl_oid *); 258 static int free_nm_rxq(struct vi_info *, struct sge_nm_rxq *); 259 static int alloc_nm_txq(struct vi_info *, struct sge_nm_txq *, int, int, 260 struct sysctl_oid *); 261 static int free_nm_txq(struct vi_info *, struct sge_nm_txq *); 262 #endif 263 static int ctrl_eq_alloc(struct adapter *, struct sge_eq *); 264 static int eth_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *); 265 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 266 static int ofld_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *); 267 #endif 268 static int alloc_eq(struct adapter *, struct vi_info *, struct sge_eq *); 269 static int free_eq(struct adapter *, struct sge_eq *); 270 static int alloc_wrq(struct adapter *, struct vi_info *, struct sge_wrq *, 271 struct sysctl_oid *); 272 static int free_wrq(struct adapter *, struct sge_wrq *); 273 static int alloc_txq(struct vi_info *, struct sge_txq *, int, 274 struct sysctl_oid *); 275 static int free_txq(struct vi_info *, struct sge_txq *); 276 static void oneseg_dma_callback(void *, bus_dma_segment_t *, int, int); 277 static inline void ring_fl_db(struct adapter *, struct sge_fl *); 278 static int refill_fl(struct adapter *, struct sge_fl *, int); 279 static void refill_sfl(void *); 280 static int alloc_fl_sdesc(struct sge_fl *); 281 static void free_fl_sdesc(struct adapter *, struct sge_fl *); 282 static void find_best_refill_source(struct adapter *, struct sge_fl *, int); 283 static void find_safe_refill_source(struct adapter *, struct sge_fl *); 284 static void add_fl_to_sfl(struct adapter *, struct sge_fl *); 285 286 static inline void get_pkt_gl(struct mbuf *, struct sglist *); 287 static inline u_int txpkt_len16(u_int, u_int); 288 static inline u_int txpkt_vm_len16(u_int, u_int); 289 static inline u_int txpkts0_len16(u_int); 290 static inline u_int txpkts1_len16(void); 291 static u_int write_raw_wr(struct sge_txq *, void *, struct mbuf *, u_int); 292 static u_int write_txpkt_wr(struct sge_txq *, struct fw_eth_tx_pkt_wr *, 293 struct mbuf *, u_int); 294 static u_int write_txpkt_vm_wr(struct adapter *, struct sge_txq *, 295 struct fw_eth_tx_pkt_vm_wr *, struct mbuf *, u_int); 296 static int try_txpkts(struct mbuf *, struct mbuf *, struct txpkts *, u_int); 297 static int add_to_txpkts(struct mbuf *, struct txpkts *, u_int); 298 static u_int write_txpkts_wr(struct sge_txq *, struct fw_eth_tx_pkts_wr *, 299 struct mbuf *, const struct txpkts *, u_int); 300 static void write_gl_to_txd(struct sge_txq *, struct mbuf *, caddr_t *, int); 301 static inline void copy_to_txd(struct sge_eq *, caddr_t, caddr_t *, int); 302 static inline void ring_eq_db(struct adapter *, struct sge_eq *, u_int); 303 static inline uint16_t read_hw_cidx(struct sge_eq *); 304 static inline u_int reclaimable_tx_desc(struct sge_eq *); 305 static inline u_int total_available_tx_desc(struct sge_eq *); 306 static u_int reclaim_tx_descs(struct sge_txq *, u_int); 307 static void tx_reclaim(void *, int); 308 static __be64 get_flit(struct sglist_seg *, int, int); 309 static int handle_sge_egr_update(struct sge_iq *, const struct rss_header *, 310 struct mbuf *); 311 static int handle_fw_msg(struct sge_iq *, const struct rss_header *, 312 struct mbuf *); 313 static int t4_handle_wrerr_rpl(struct adapter *, const __be64 *); 314 static void wrq_tx_drain(void *, int); 315 static void drain_wrq_wr_list(struct adapter *, struct sge_wrq *); 316 317 static int sysctl_uint16(SYSCTL_HANDLER_ARGS); 318 static int sysctl_bufsizes(SYSCTL_HANDLER_ARGS); 319 #ifdef RATELIMIT 320 static inline u_int txpkt_eo_len16(u_int, u_int, u_int); 321 static int ethofld_fw4_ack(struct sge_iq *, const struct rss_header *, 322 struct mbuf *); 323 #endif 324 325 static counter_u64_t extfree_refs; 326 static counter_u64_t extfree_rels; 327 328 an_handler_t t4_an_handler; 329 fw_msg_handler_t t4_fw_msg_handler[NUM_FW6_TYPES]; 330 cpl_handler_t t4_cpl_handler[NUM_CPL_CMDS]; 331 cpl_handler_t set_tcb_rpl_handlers[NUM_CPL_COOKIES]; 332 cpl_handler_t l2t_write_rpl_handlers[NUM_CPL_COOKIES]; 333 cpl_handler_t act_open_rpl_handlers[NUM_CPL_COOKIES]; 334 cpl_handler_t abort_rpl_rss_handlers[NUM_CPL_COOKIES]; 335 cpl_handler_t fw4_ack_handlers[NUM_CPL_COOKIES]; 336 337 void 338 t4_register_an_handler(an_handler_t h) 339 { 340 uintptr_t *loc; 341 342 MPASS(h == NULL || t4_an_handler == NULL); 343 344 loc = (uintptr_t *)&t4_an_handler; 345 atomic_store_rel_ptr(loc, (uintptr_t)h); 346 } 347 348 void 349 t4_register_fw_msg_handler(int type, fw_msg_handler_t h) 350 { 351 uintptr_t *loc; 352 353 MPASS(type < nitems(t4_fw_msg_handler)); 354 MPASS(h == NULL || t4_fw_msg_handler[type] == NULL); 355 /* 356 * These are dispatched by the handler for FW{4|6}_CPL_MSG using the CPL 357 * handler dispatch table. Reject any attempt to install a handler for 358 * this subtype. 359 */ 360 MPASS(type != FW_TYPE_RSSCPL); 361 MPASS(type != FW6_TYPE_RSSCPL); 362 363 loc = (uintptr_t *)&t4_fw_msg_handler[type]; 364 atomic_store_rel_ptr(loc, (uintptr_t)h); 365 } 366 367 void 368 t4_register_cpl_handler(int opcode, cpl_handler_t h) 369 { 370 uintptr_t *loc; 371 372 MPASS(opcode < nitems(t4_cpl_handler)); 373 MPASS(h == NULL || t4_cpl_handler[opcode] == NULL); 374 375 loc = (uintptr_t *)&t4_cpl_handler[opcode]; 376 atomic_store_rel_ptr(loc, (uintptr_t)h); 377 } 378 379 static int 380 set_tcb_rpl_handler(struct sge_iq *iq, const struct rss_header *rss, 381 struct mbuf *m) 382 { 383 const struct cpl_set_tcb_rpl *cpl = (const void *)(rss + 1); 384 u_int tid; 385 int cookie; 386 387 MPASS(m == NULL); 388 389 tid = GET_TID(cpl); 390 if (is_hpftid(iq->adapter, tid) || is_ftid(iq->adapter, tid)) { 391 /* 392 * The return code for filter-write is put in the CPL cookie so 393 * we have to rely on the hardware tid (is_ftid) to determine 394 * that this is a response to a filter. 395 */ 396 cookie = CPL_COOKIE_FILTER; 397 } else { 398 cookie = G_COOKIE(cpl->cookie); 399 } 400 MPASS(cookie > CPL_COOKIE_RESERVED); 401 MPASS(cookie < nitems(set_tcb_rpl_handlers)); 402 403 return (set_tcb_rpl_handlers[cookie](iq, rss, m)); 404 } 405 406 static int 407 l2t_write_rpl_handler(struct sge_iq *iq, const struct rss_header *rss, 408 struct mbuf *m) 409 { 410 const struct cpl_l2t_write_rpl *rpl = (const void *)(rss + 1); 411 unsigned int cookie; 412 413 MPASS(m == NULL); 414 415 cookie = GET_TID(rpl) & F_SYNC_WR ? CPL_COOKIE_TOM : CPL_COOKIE_FILTER; 416 return (l2t_write_rpl_handlers[cookie](iq, rss, m)); 417 } 418 419 static int 420 act_open_rpl_handler(struct sge_iq *iq, const struct rss_header *rss, 421 struct mbuf *m) 422 { 423 const struct cpl_act_open_rpl *cpl = (const void *)(rss + 1); 424 u_int cookie = G_TID_COOKIE(G_AOPEN_ATID(be32toh(cpl->atid_status))); 425 426 MPASS(m == NULL); 427 MPASS(cookie != CPL_COOKIE_RESERVED); 428 429 return (act_open_rpl_handlers[cookie](iq, rss, m)); 430 } 431 432 static int 433 abort_rpl_rss_handler(struct sge_iq *iq, const struct rss_header *rss, 434 struct mbuf *m) 435 { 436 struct adapter *sc = iq->adapter; 437 u_int cookie; 438 439 MPASS(m == NULL); 440 if (is_hashfilter(sc)) 441 cookie = CPL_COOKIE_HASHFILTER; 442 else 443 cookie = CPL_COOKIE_TOM; 444 445 return (abort_rpl_rss_handlers[cookie](iq, rss, m)); 446 } 447 448 static int 449 fw4_ack_handler(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 450 { 451 struct adapter *sc = iq->adapter; 452 const struct cpl_fw4_ack *cpl = (const void *)(rss + 1); 453 unsigned int tid = G_CPL_FW4_ACK_FLOWID(be32toh(OPCODE_TID(cpl))); 454 u_int cookie; 455 456 MPASS(m == NULL); 457 if (is_etid(sc, tid)) 458 cookie = CPL_COOKIE_ETHOFLD; 459 else 460 cookie = CPL_COOKIE_TOM; 461 462 return (fw4_ack_handlers[cookie](iq, rss, m)); 463 } 464 465 static void 466 t4_init_shared_cpl_handlers(void) 467 { 468 469 t4_register_cpl_handler(CPL_SET_TCB_RPL, set_tcb_rpl_handler); 470 t4_register_cpl_handler(CPL_L2T_WRITE_RPL, l2t_write_rpl_handler); 471 t4_register_cpl_handler(CPL_ACT_OPEN_RPL, act_open_rpl_handler); 472 t4_register_cpl_handler(CPL_ABORT_RPL_RSS, abort_rpl_rss_handler); 473 t4_register_cpl_handler(CPL_FW4_ACK, fw4_ack_handler); 474 } 475 476 void 477 t4_register_shared_cpl_handler(int opcode, cpl_handler_t h, int cookie) 478 { 479 uintptr_t *loc; 480 481 MPASS(opcode < nitems(t4_cpl_handler)); 482 MPASS(cookie > CPL_COOKIE_RESERVED); 483 MPASS(cookie < NUM_CPL_COOKIES); 484 MPASS(t4_cpl_handler[opcode] != NULL); 485 486 switch (opcode) { 487 case CPL_SET_TCB_RPL: 488 loc = (uintptr_t *)&set_tcb_rpl_handlers[cookie]; 489 break; 490 case CPL_L2T_WRITE_RPL: 491 loc = (uintptr_t *)&l2t_write_rpl_handlers[cookie]; 492 break; 493 case CPL_ACT_OPEN_RPL: 494 loc = (uintptr_t *)&act_open_rpl_handlers[cookie]; 495 break; 496 case CPL_ABORT_RPL_RSS: 497 loc = (uintptr_t *)&abort_rpl_rss_handlers[cookie]; 498 break; 499 case CPL_FW4_ACK: 500 loc = (uintptr_t *)&fw4_ack_handlers[cookie]; 501 break; 502 default: 503 MPASS(0); 504 return; 505 } 506 MPASS(h == NULL || *loc == (uintptr_t)NULL); 507 atomic_store_rel_ptr(loc, (uintptr_t)h); 508 } 509 510 /* 511 * Called on MOD_LOAD. Validates and calculates the SGE tunables. 512 */ 513 void 514 t4_sge_modload(void) 515 { 516 517 if (fl_pktshift < 0 || fl_pktshift > 7) { 518 printf("Invalid hw.cxgbe.fl_pktshift value (%d)," 519 " using 0 instead.\n", fl_pktshift); 520 fl_pktshift = 0; 521 } 522 523 if (spg_len != 64 && spg_len != 128) { 524 int len; 525 526 #if defined(__i386__) || defined(__amd64__) 527 len = cpu_clflush_line_size > 64 ? 128 : 64; 528 #else 529 len = 64; 530 #endif 531 if (spg_len != -1) { 532 printf("Invalid hw.cxgbe.spg_len value (%d)," 533 " using %d instead.\n", spg_len, len); 534 } 535 spg_len = len; 536 } 537 538 if (cong_drop < -1 || cong_drop > 1) { 539 printf("Invalid hw.cxgbe.cong_drop value (%d)," 540 " using 0 instead.\n", cong_drop); 541 cong_drop = 0; 542 } 543 544 if (tscale != 1 && (tscale < 3 || tscale > 17)) { 545 printf("Invalid hw.cxgbe.tscale value (%d)," 546 " using 1 instead.\n", tscale); 547 tscale = 1; 548 } 549 550 extfree_refs = counter_u64_alloc(M_WAITOK); 551 extfree_rels = counter_u64_alloc(M_WAITOK); 552 counter_u64_zero(extfree_refs); 553 counter_u64_zero(extfree_rels); 554 555 t4_init_shared_cpl_handlers(); 556 t4_register_cpl_handler(CPL_FW4_MSG, handle_fw_msg); 557 t4_register_cpl_handler(CPL_FW6_MSG, handle_fw_msg); 558 t4_register_cpl_handler(CPL_SGE_EGR_UPDATE, handle_sge_egr_update); 559 t4_register_cpl_handler(CPL_RX_PKT, t4_eth_rx); 560 #ifdef RATELIMIT 561 t4_register_shared_cpl_handler(CPL_FW4_ACK, ethofld_fw4_ack, 562 CPL_COOKIE_ETHOFLD); 563 #endif 564 t4_register_fw_msg_handler(FW6_TYPE_CMD_RPL, t4_handle_fw_rpl); 565 t4_register_fw_msg_handler(FW6_TYPE_WRERR_RPL, t4_handle_wrerr_rpl); 566 } 567 568 void 569 t4_sge_modunload(void) 570 { 571 572 counter_u64_free(extfree_refs); 573 counter_u64_free(extfree_rels); 574 } 575 576 uint64_t 577 t4_sge_extfree_refs(void) 578 { 579 uint64_t refs, rels; 580 581 rels = counter_u64_fetch(extfree_rels); 582 refs = counter_u64_fetch(extfree_refs); 583 584 return (refs - rels); 585 } 586 587 static inline void 588 setup_pad_and_pack_boundaries(struct adapter *sc) 589 { 590 uint32_t v, m; 591 int pad, pack, pad_shift; 592 593 pad_shift = chip_id(sc) > CHELSIO_T5 ? X_T6_INGPADBOUNDARY_SHIFT : 594 X_INGPADBOUNDARY_SHIFT; 595 pad = fl_pad; 596 if (fl_pad < (1 << pad_shift) || 597 fl_pad > (1 << (pad_shift + M_INGPADBOUNDARY)) || 598 !powerof2(fl_pad)) { 599 /* 600 * If there is any chance that we might use buffer packing and 601 * the chip is a T4, then pick 64 as the pad/pack boundary. Set 602 * it to the minimum allowed in all other cases. 603 */ 604 pad = is_t4(sc) && buffer_packing ? 64 : 1 << pad_shift; 605 606 /* 607 * For fl_pad = 0 we'll still write a reasonable value to the 608 * register but all the freelists will opt out of padding. 609 * We'll complain here only if the user tried to set it to a 610 * value greater than 0 that was invalid. 611 */ 612 if (fl_pad > 0) { 613 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pad value" 614 " (%d), using %d instead.\n", fl_pad, pad); 615 } 616 } 617 m = V_INGPADBOUNDARY(M_INGPADBOUNDARY); 618 v = V_INGPADBOUNDARY(ilog2(pad) - pad_shift); 619 t4_set_reg_field(sc, A_SGE_CONTROL, m, v); 620 621 if (is_t4(sc)) { 622 if (fl_pack != -1 && fl_pack != pad) { 623 /* Complain but carry on. */ 624 device_printf(sc->dev, "hw.cxgbe.fl_pack (%d) ignored," 625 " using %d instead.\n", fl_pack, pad); 626 } 627 return; 628 } 629 630 pack = fl_pack; 631 if (fl_pack < 16 || fl_pack == 32 || fl_pack > 4096 || 632 !powerof2(fl_pack)) { 633 pack = max(sc->params.pci.mps, CACHE_LINE_SIZE); 634 MPASS(powerof2(pack)); 635 if (pack < 16) 636 pack = 16; 637 if (pack == 32) 638 pack = 64; 639 if (pack > 4096) 640 pack = 4096; 641 if (fl_pack != -1) { 642 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pack value" 643 " (%d), using %d instead.\n", fl_pack, pack); 644 } 645 } 646 m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY); 647 if (pack == 16) 648 v = V_INGPACKBOUNDARY(0); 649 else 650 v = V_INGPACKBOUNDARY(ilog2(pack) - 5); 651 652 MPASS(!is_t4(sc)); /* T4 doesn't have SGE_CONTROL2 */ 653 t4_set_reg_field(sc, A_SGE_CONTROL2, m, v); 654 } 655 656 /* 657 * adap->params.vpd.cclk must be set up before this is called. 658 */ 659 void 660 t4_tweak_chip_settings(struct adapter *sc) 661 { 662 int i; 663 uint32_t v, m; 664 int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200}; 665 int timer_max = M_TIMERVALUE0 * 1000 / sc->params.vpd.cclk; 666 int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */ 667 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 668 static int sge_flbuf_sizes[] = { 669 MCLBYTES, 670 #if MJUMPAGESIZE != MCLBYTES 671 MJUMPAGESIZE, 672 MJUMPAGESIZE - CL_METADATA_SIZE, 673 MJUMPAGESIZE - 2 * MSIZE - CL_METADATA_SIZE, 674 #endif 675 MJUM9BYTES, 676 MJUM16BYTES, 677 MCLBYTES - MSIZE - CL_METADATA_SIZE, 678 MJUM9BYTES - CL_METADATA_SIZE, 679 MJUM16BYTES - CL_METADATA_SIZE, 680 }; 681 682 KASSERT(sc->flags & MASTER_PF, 683 ("%s: trying to change chip settings when not master.", __func__)); 684 685 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE; 686 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE | 687 V_EGRSTATUSPAGESIZE(spg_len == 128); 688 t4_set_reg_field(sc, A_SGE_CONTROL, m, v); 689 690 setup_pad_and_pack_boundaries(sc); 691 692 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) | 693 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) | 694 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) | 695 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) | 696 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) | 697 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) | 698 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) | 699 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10); 700 t4_write_reg(sc, A_SGE_HOST_PAGE_SIZE, v); 701 702 KASSERT(nitems(sge_flbuf_sizes) <= SGE_FLBUF_SIZES, 703 ("%s: hw buffer size table too big", __func__)); 704 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0, 4096); 705 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE1, 65536); 706 for (i = 0; i < min(nitems(sge_flbuf_sizes), SGE_FLBUF_SIZES); i++) { 707 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE15 - (4 * i), 708 sge_flbuf_sizes[i]); 709 } 710 711 v = V_THRESHOLD_0(intr_pktcount[0]) | V_THRESHOLD_1(intr_pktcount[1]) | 712 V_THRESHOLD_2(intr_pktcount[2]) | V_THRESHOLD_3(intr_pktcount[3]); 713 t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD, v); 714 715 KASSERT(intr_timer[0] <= timer_max, 716 ("%s: not a single usable timer (%d, %d)", __func__, intr_timer[0], 717 timer_max)); 718 for (i = 1; i < nitems(intr_timer); i++) { 719 KASSERT(intr_timer[i] >= intr_timer[i - 1], 720 ("%s: timers not listed in increasing order (%d)", 721 __func__, i)); 722 723 while (intr_timer[i] > timer_max) { 724 if (i == nitems(intr_timer) - 1) { 725 intr_timer[i] = timer_max; 726 break; 727 } 728 intr_timer[i] += intr_timer[i - 1]; 729 intr_timer[i] /= 2; 730 } 731 } 732 733 v = V_TIMERVALUE0(us_to_core_ticks(sc, intr_timer[0])) | 734 V_TIMERVALUE1(us_to_core_ticks(sc, intr_timer[1])); 735 t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1, v); 736 v = V_TIMERVALUE2(us_to_core_ticks(sc, intr_timer[2])) | 737 V_TIMERVALUE3(us_to_core_ticks(sc, intr_timer[3])); 738 t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3, v); 739 v = V_TIMERVALUE4(us_to_core_ticks(sc, intr_timer[4])) | 740 V_TIMERVALUE5(us_to_core_ticks(sc, intr_timer[5])); 741 t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5, v); 742 743 if (chip_id(sc) >= CHELSIO_T6) { 744 m = V_TSCALE(M_TSCALE); 745 if (tscale == 1) 746 v = 0; 747 else 748 v = V_TSCALE(tscale - 2); 749 t4_set_reg_field(sc, A_SGE_ITP_CONTROL, m, v); 750 751 if (sc->debug_flags & DF_DISABLE_TCB_CACHE) { 752 m = V_RDTHRESHOLD(M_RDTHRESHOLD) | F_WRTHRTHRESHEN | 753 V_WRTHRTHRESH(M_WRTHRTHRESH); 754 t4_tp_pio_read(sc, &v, 1, A_TP_CMM_CONFIG, 1); 755 v &= ~m; 756 v |= V_RDTHRESHOLD(1) | F_WRTHRTHRESHEN | 757 V_WRTHRTHRESH(16); 758 t4_tp_pio_write(sc, &v, 1, A_TP_CMM_CONFIG, 1); 759 } 760 } 761 762 /* 4K, 16K, 64K, 256K DDP "page sizes" for TDDP */ 763 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 764 t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, v); 765 766 /* 767 * 4K, 8K, 16K, 64K DDP "page sizes" for iSCSI DDP. These have been 768 * chosen with MAXPHYS = 128K in mind. The largest DDP buffer that we 769 * may have to deal with is MAXPHYS + 1 page. 770 */ 771 v = V_HPZ0(0) | V_HPZ1(1) | V_HPZ2(2) | V_HPZ3(4); 772 t4_write_reg(sc, A_ULP_RX_ISCSI_PSZ, v); 773 774 /* We use multiple DDP page sizes both in plain-TOE and ISCSI modes. */ 775 m = v = F_TDDPTAGTCB | F_ISCSITAGTCB; 776 t4_set_reg_field(sc, A_ULP_RX_CTL, m, v); 777 778 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 779 F_RESETDDPOFFSET; 780 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 781 t4_set_reg_field(sc, A_TP_PARA_REG5, m, v); 782 } 783 784 /* 785 * SGE wants the buffer to be at least 64B and then a multiple of 16. If 786 * padding is in use, the buffer's start and end need to be aligned to the pad 787 * boundary as well. We'll just make sure that the size is a multiple of the 788 * boundary here, it is up to the buffer allocation code to make sure the start 789 * of the buffer is aligned as well. 790 */ 791 static inline int 792 hwsz_ok(struct adapter *sc, int hwsz) 793 { 794 int mask = fl_pad ? sc->params.sge.pad_boundary - 1 : 16 - 1; 795 796 return (hwsz >= 64 && (hwsz & mask) == 0); 797 } 798 799 /* 800 * XXX: driver really should be able to deal with unexpected settings. 801 */ 802 int 803 t4_read_chip_settings(struct adapter *sc) 804 { 805 struct sge *s = &sc->sge; 806 struct sge_params *sp = &sc->params.sge; 807 int i, j, n, rc = 0; 808 uint32_t m, v, r; 809 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 810 static int sw_buf_sizes[] = { /* Sorted by size */ 811 MCLBYTES, 812 #if MJUMPAGESIZE != MCLBYTES 813 MJUMPAGESIZE, 814 #endif 815 MJUM9BYTES, 816 MJUM16BYTES 817 }; 818 struct sw_zone_info *swz, *safe_swz; 819 struct hw_buf_info *hwb; 820 821 m = F_RXPKTCPLMODE; 822 v = F_RXPKTCPLMODE; 823 r = sc->params.sge.sge_control; 824 if ((r & m) != v) { 825 device_printf(sc->dev, "invalid SGE_CONTROL(0x%x)\n", r); 826 rc = EINVAL; 827 } 828 829 /* 830 * If this changes then every single use of PAGE_SHIFT in the driver 831 * needs to be carefully reviewed for PAGE_SHIFT vs sp->page_shift. 832 */ 833 if (sp->page_shift != PAGE_SHIFT) { 834 device_printf(sc->dev, "invalid SGE_HOST_PAGE_SIZE(0x%x)\n", r); 835 rc = EINVAL; 836 } 837 838 /* Filter out unusable hw buffer sizes entirely (mark with -2). */ 839 hwb = &s->hw_buf_info[0]; 840 for (i = 0; i < nitems(s->hw_buf_info); i++, hwb++) { 841 r = sc->params.sge.sge_fl_buffer_size[i]; 842 hwb->size = r; 843 hwb->zidx = hwsz_ok(sc, r) ? -1 : -2; 844 hwb->next = -1; 845 } 846 847 /* 848 * Create a sorted list in decreasing order of hw buffer sizes (and so 849 * increasing order of spare area) for each software zone. 850 * 851 * If padding is enabled then the start and end of the buffer must align 852 * to the pad boundary; if packing is enabled then they must align with 853 * the pack boundary as well. Allocations from the cluster zones are 854 * aligned to min(size, 4K), so the buffer starts at that alignment and 855 * ends at hwb->size alignment. If mbuf inlining is allowed the 856 * starting alignment will be reduced to MSIZE and the driver will 857 * exercise appropriate caution when deciding on the best buffer layout 858 * to use. 859 */ 860 n = 0; /* no usable buffer size to begin with */ 861 swz = &s->sw_zone_info[0]; 862 safe_swz = NULL; 863 for (i = 0; i < SW_ZONE_SIZES; i++, swz++) { 864 int8_t head = -1, tail = -1; 865 866 swz->size = sw_buf_sizes[i]; 867 swz->zone = m_getzone(swz->size); 868 swz->type = m_gettype(swz->size); 869 870 if (swz->size < PAGE_SIZE) { 871 MPASS(powerof2(swz->size)); 872 if (fl_pad && (swz->size % sp->pad_boundary != 0)) 873 continue; 874 } 875 876 if (swz->size == safest_rx_cluster) 877 safe_swz = swz; 878 879 hwb = &s->hw_buf_info[0]; 880 for (j = 0; j < SGE_FLBUF_SIZES; j++, hwb++) { 881 if (hwb->zidx != -1 || hwb->size > swz->size) 882 continue; 883 #ifdef INVARIANTS 884 if (fl_pad) 885 MPASS(hwb->size % sp->pad_boundary == 0); 886 #endif 887 hwb->zidx = i; 888 if (head == -1) 889 head = tail = j; 890 else if (hwb->size < s->hw_buf_info[tail].size) { 891 s->hw_buf_info[tail].next = j; 892 tail = j; 893 } else { 894 int8_t *cur; 895 struct hw_buf_info *t; 896 897 for (cur = &head; *cur != -1; cur = &t->next) { 898 t = &s->hw_buf_info[*cur]; 899 if (hwb->size == t->size) { 900 hwb->zidx = -2; 901 break; 902 } 903 if (hwb->size > t->size) { 904 hwb->next = *cur; 905 *cur = j; 906 break; 907 } 908 } 909 } 910 } 911 swz->head_hwidx = head; 912 swz->tail_hwidx = tail; 913 914 if (tail != -1) { 915 n++; 916 if (swz->size - s->hw_buf_info[tail].size >= 917 CL_METADATA_SIZE) 918 sc->flags |= BUF_PACKING_OK; 919 } 920 } 921 if (n == 0) { 922 device_printf(sc->dev, "no usable SGE FL buffer size.\n"); 923 rc = EINVAL; 924 } 925 926 s->safe_hwidx1 = -1; 927 s->safe_hwidx2 = -1; 928 if (safe_swz != NULL) { 929 s->safe_hwidx1 = safe_swz->head_hwidx; 930 for (i = safe_swz->head_hwidx; i != -1; i = hwb->next) { 931 int spare; 932 933 hwb = &s->hw_buf_info[i]; 934 #ifdef INVARIANTS 935 if (fl_pad) 936 MPASS(hwb->size % sp->pad_boundary == 0); 937 #endif 938 spare = safe_swz->size - hwb->size; 939 if (spare >= CL_METADATA_SIZE) { 940 s->safe_hwidx2 = i; 941 break; 942 } 943 } 944 } 945 946 if (sc->flags & IS_VF) 947 return (0); 948 949 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 950 r = t4_read_reg(sc, A_ULP_RX_TDDP_PSZ); 951 if (r != v) { 952 device_printf(sc->dev, "invalid ULP_RX_TDDP_PSZ(0x%x)\n", r); 953 rc = EINVAL; 954 } 955 956 m = v = F_TDDPTAGTCB; 957 r = t4_read_reg(sc, A_ULP_RX_CTL); 958 if ((r & m) != v) { 959 device_printf(sc->dev, "invalid ULP_RX_CTL(0x%x)\n", r); 960 rc = EINVAL; 961 } 962 963 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 964 F_RESETDDPOFFSET; 965 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 966 r = t4_read_reg(sc, A_TP_PARA_REG5); 967 if ((r & m) != v) { 968 device_printf(sc->dev, "invalid TP_PARA_REG5(0x%x)\n", r); 969 rc = EINVAL; 970 } 971 972 t4_init_tp_params(sc, 1); 973 974 t4_read_mtu_tbl(sc, sc->params.mtus, NULL); 975 t4_load_mtus(sc, sc->params.mtus, sc->params.a_wnd, sc->params.b_wnd); 976 977 return (rc); 978 } 979 980 int 981 t4_create_dma_tag(struct adapter *sc) 982 { 983 int rc; 984 985 rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0, 986 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE, 987 BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL, 988 NULL, &sc->dmat); 989 if (rc != 0) { 990 device_printf(sc->dev, 991 "failed to create main DMA tag: %d\n", rc); 992 } 993 994 return (rc); 995 } 996 997 void 998 t4_sge_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx, 999 struct sysctl_oid_list *children) 1000 { 1001 struct sge_params *sp = &sc->params.sge; 1002 1003 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "buffer_sizes", 1004 CTLTYPE_STRING | CTLFLAG_RD, &sc->sge, 0, sysctl_bufsizes, "A", 1005 "freelist buffer sizes"); 1006 1007 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pktshift", CTLFLAG_RD, 1008 NULL, sp->fl_pktshift, "payload DMA offset in rx buffer (bytes)"); 1009 1010 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pad", CTLFLAG_RD, 1011 NULL, sp->pad_boundary, "payload pad boundary (bytes)"); 1012 1013 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "spg_len", CTLFLAG_RD, 1014 NULL, sp->spg_len, "status page size (bytes)"); 1015 1016 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_drop", CTLFLAG_RD, 1017 NULL, cong_drop, "congestion drop setting"); 1018 1019 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pack", CTLFLAG_RD, 1020 NULL, sp->pack_boundary, "payload pack boundary (bytes)"); 1021 } 1022 1023 int 1024 t4_destroy_dma_tag(struct adapter *sc) 1025 { 1026 if (sc->dmat) 1027 bus_dma_tag_destroy(sc->dmat); 1028 1029 return (0); 1030 } 1031 1032 /* 1033 * Allocate and initialize the firmware event queue, control queues, and special 1034 * purpose rx queues owned by the adapter. 1035 * 1036 * Returns errno on failure. Resources allocated up to that point may still be 1037 * allocated. Caller is responsible for cleanup in case this function fails. 1038 */ 1039 int 1040 t4_setup_adapter_queues(struct adapter *sc) 1041 { 1042 struct sysctl_oid *oid; 1043 struct sysctl_oid_list *children; 1044 int rc, i; 1045 1046 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 1047 1048 sysctl_ctx_init(&sc->ctx); 1049 sc->flags |= ADAP_SYSCTL_CTX; 1050 1051 /* 1052 * Firmware event queue 1053 */ 1054 rc = alloc_fwq(sc); 1055 if (rc != 0) 1056 return (rc); 1057 1058 /* 1059 * That's all for the VF driver. 1060 */ 1061 if (sc->flags & IS_VF) 1062 return (rc); 1063 1064 oid = device_get_sysctl_tree(sc->dev); 1065 children = SYSCTL_CHILDREN(oid); 1066 1067 /* 1068 * XXX: General purpose rx queues, one per port. 1069 */ 1070 1071 /* 1072 * Control queues, one per port. 1073 */ 1074 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "ctrlq", 1075 CTLFLAG_RD, NULL, "control queues"); 1076 for_each_port(sc, i) { 1077 struct sge_wrq *ctrlq = &sc->sge.ctrlq[i]; 1078 1079 rc = alloc_ctrlq(sc, ctrlq, i, oid); 1080 if (rc != 0) 1081 return (rc); 1082 } 1083 1084 return (rc); 1085 } 1086 1087 /* 1088 * Idempotent 1089 */ 1090 int 1091 t4_teardown_adapter_queues(struct adapter *sc) 1092 { 1093 int i; 1094 1095 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 1096 1097 /* Do this before freeing the queue */ 1098 if (sc->flags & ADAP_SYSCTL_CTX) { 1099 sysctl_ctx_free(&sc->ctx); 1100 sc->flags &= ~ADAP_SYSCTL_CTX; 1101 } 1102 1103 if (!(sc->flags & IS_VF)) { 1104 for_each_port(sc, i) 1105 free_wrq(sc, &sc->sge.ctrlq[i]); 1106 } 1107 free_fwq(sc); 1108 1109 return (0); 1110 } 1111 1112 /* Maximum payload that can be delivered with a single iq descriptor */ 1113 static inline int 1114 mtu_to_max_payload(struct adapter *sc, int mtu, const int toe) 1115 { 1116 int payload; 1117 1118 #ifdef TCP_OFFLOAD 1119 if (toe) { 1120 int rxcs = G_RXCOALESCESIZE(t4_read_reg(sc, A_TP_PARA_REG2)); 1121 1122 /* Note that COP can set rx_coalesce on/off per connection. */ 1123 payload = max(mtu, rxcs); 1124 } else { 1125 #endif 1126 /* large enough even when hw VLAN extraction is disabled */ 1127 payload = sc->params.sge.fl_pktshift + ETHER_HDR_LEN + 1128 ETHER_VLAN_ENCAP_LEN + mtu; 1129 #ifdef TCP_OFFLOAD 1130 } 1131 #endif 1132 1133 return (payload); 1134 } 1135 1136 int 1137 t4_setup_vi_queues(struct vi_info *vi) 1138 { 1139 int rc = 0, i, intr_idx, iqidx; 1140 struct sge_rxq *rxq; 1141 struct sge_txq *txq; 1142 #ifdef TCP_OFFLOAD 1143 struct sge_ofld_rxq *ofld_rxq; 1144 #endif 1145 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1146 struct sge_wrq *ofld_txq; 1147 #endif 1148 #ifdef DEV_NETMAP 1149 int saved_idx; 1150 struct sge_nm_rxq *nm_rxq; 1151 struct sge_nm_txq *nm_txq; 1152 #endif 1153 char name[16]; 1154 struct port_info *pi = vi->pi; 1155 struct adapter *sc = pi->adapter; 1156 struct ifnet *ifp = vi->ifp; 1157 struct sysctl_oid *oid = device_get_sysctl_tree(vi->dev); 1158 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 1159 int maxp, mtu = ifp->if_mtu; 1160 1161 /* Interrupt vector to start from (when using multiple vectors) */ 1162 intr_idx = vi->first_intr; 1163 1164 #ifdef DEV_NETMAP 1165 saved_idx = intr_idx; 1166 if (ifp->if_capabilities & IFCAP_NETMAP) { 1167 1168 /* netmap is supported with direct interrupts only. */ 1169 MPASS(!forwarding_intr_to_fwq(sc)); 1170 1171 /* 1172 * We don't have buffers to back the netmap rx queues 1173 * right now so we create the queues in a way that 1174 * doesn't set off any congestion signal in the chip. 1175 */ 1176 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "nm_rxq", 1177 CTLFLAG_RD, NULL, "rx queues"); 1178 for_each_nm_rxq(vi, i, nm_rxq) { 1179 rc = alloc_nm_rxq(vi, nm_rxq, intr_idx, i, oid); 1180 if (rc != 0) 1181 goto done; 1182 intr_idx++; 1183 } 1184 1185 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "nm_txq", 1186 CTLFLAG_RD, NULL, "tx queues"); 1187 for_each_nm_txq(vi, i, nm_txq) { 1188 iqidx = vi->first_nm_rxq + (i % vi->nnmrxq); 1189 rc = alloc_nm_txq(vi, nm_txq, iqidx, i, oid); 1190 if (rc != 0) 1191 goto done; 1192 } 1193 } 1194 1195 /* Normal rx queues and netmap rx queues share the same interrupts. */ 1196 intr_idx = saved_idx; 1197 #endif 1198 1199 /* 1200 * Allocate rx queues first because a default iqid is required when 1201 * creating a tx queue. 1202 */ 1203 maxp = mtu_to_max_payload(sc, mtu, 0); 1204 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "rxq", 1205 CTLFLAG_RD, NULL, "rx queues"); 1206 for_each_rxq(vi, i, rxq) { 1207 1208 init_iq(&rxq->iq, sc, vi->tmr_idx, vi->pktc_idx, vi->qsize_rxq); 1209 1210 snprintf(name, sizeof(name), "%s rxq%d-fl", 1211 device_get_nameunit(vi->dev), i); 1212 init_fl(sc, &rxq->fl, vi->qsize_rxq / 8, maxp, name); 1213 1214 rc = alloc_rxq(vi, rxq, 1215 forwarding_intr_to_fwq(sc) ? -1 : intr_idx, i, oid); 1216 if (rc != 0) 1217 goto done; 1218 intr_idx++; 1219 } 1220 #ifdef DEV_NETMAP 1221 if (ifp->if_capabilities & IFCAP_NETMAP) 1222 intr_idx = saved_idx + max(vi->nrxq, vi->nnmrxq); 1223 #endif 1224 #ifdef TCP_OFFLOAD 1225 maxp = mtu_to_max_payload(sc, mtu, 1); 1226 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_rxq", 1227 CTLFLAG_RD, NULL, "rx queues for offloaded TCP connections"); 1228 for_each_ofld_rxq(vi, i, ofld_rxq) { 1229 1230 init_iq(&ofld_rxq->iq, sc, vi->ofld_tmr_idx, vi->ofld_pktc_idx, 1231 vi->qsize_rxq); 1232 1233 snprintf(name, sizeof(name), "%s ofld_rxq%d-fl", 1234 device_get_nameunit(vi->dev), i); 1235 init_fl(sc, &ofld_rxq->fl, vi->qsize_rxq / 8, maxp, name); 1236 1237 rc = alloc_ofld_rxq(vi, ofld_rxq, 1238 forwarding_intr_to_fwq(sc) ? -1 : intr_idx, i, oid); 1239 if (rc != 0) 1240 goto done; 1241 intr_idx++; 1242 } 1243 #endif 1244 1245 /* 1246 * Now the tx queues. 1247 */ 1248 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "txq", CTLFLAG_RD, 1249 NULL, "tx queues"); 1250 for_each_txq(vi, i, txq) { 1251 iqidx = vi->first_rxq + (i % vi->nrxq); 1252 snprintf(name, sizeof(name), "%s txq%d", 1253 device_get_nameunit(vi->dev), i); 1254 init_eq(sc, &txq->eq, EQ_ETH, vi->qsize_txq, pi->tx_chan, 1255 sc->sge.rxq[iqidx].iq.cntxt_id, name); 1256 1257 rc = alloc_txq(vi, txq, i, oid); 1258 if (rc != 0) 1259 goto done; 1260 } 1261 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1262 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_txq", 1263 CTLFLAG_RD, NULL, "tx queues for TOE/ETHOFLD"); 1264 for_each_ofld_txq(vi, i, ofld_txq) { 1265 struct sysctl_oid *oid2; 1266 1267 snprintf(name, sizeof(name), "%s ofld_txq%d", 1268 device_get_nameunit(vi->dev), i); 1269 if (vi->nofldrxq > 0) { 1270 iqidx = vi->first_ofld_rxq + (i % vi->nofldrxq); 1271 init_eq(sc, &ofld_txq->eq, EQ_OFLD, vi->qsize_txq, 1272 pi->tx_chan, sc->sge.ofld_rxq[iqidx].iq.cntxt_id, 1273 name); 1274 } else { 1275 iqidx = vi->first_rxq + (i % vi->nrxq); 1276 init_eq(sc, &ofld_txq->eq, EQ_OFLD, vi->qsize_txq, 1277 pi->tx_chan, sc->sge.rxq[iqidx].iq.cntxt_id, name); 1278 } 1279 1280 snprintf(name, sizeof(name), "%d", i); 1281 oid2 = SYSCTL_ADD_NODE(&vi->ctx, SYSCTL_CHILDREN(oid), OID_AUTO, 1282 name, CTLFLAG_RD, NULL, "offload tx queue"); 1283 1284 rc = alloc_wrq(sc, vi, ofld_txq, oid2); 1285 if (rc != 0) 1286 goto done; 1287 } 1288 #endif 1289 done: 1290 if (rc) 1291 t4_teardown_vi_queues(vi); 1292 1293 return (rc); 1294 } 1295 1296 /* 1297 * Idempotent 1298 */ 1299 int 1300 t4_teardown_vi_queues(struct vi_info *vi) 1301 { 1302 int i; 1303 struct sge_rxq *rxq; 1304 struct sge_txq *txq; 1305 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1306 struct port_info *pi = vi->pi; 1307 struct adapter *sc = pi->adapter; 1308 struct sge_wrq *ofld_txq; 1309 #endif 1310 #ifdef TCP_OFFLOAD 1311 struct sge_ofld_rxq *ofld_rxq; 1312 #endif 1313 #ifdef DEV_NETMAP 1314 struct sge_nm_rxq *nm_rxq; 1315 struct sge_nm_txq *nm_txq; 1316 #endif 1317 1318 /* Do this before freeing the queues */ 1319 if (vi->flags & VI_SYSCTL_CTX) { 1320 sysctl_ctx_free(&vi->ctx); 1321 vi->flags &= ~VI_SYSCTL_CTX; 1322 } 1323 1324 #ifdef DEV_NETMAP 1325 if (vi->ifp->if_capabilities & IFCAP_NETMAP) { 1326 for_each_nm_txq(vi, i, nm_txq) { 1327 free_nm_txq(vi, nm_txq); 1328 } 1329 1330 for_each_nm_rxq(vi, i, nm_rxq) { 1331 free_nm_rxq(vi, nm_rxq); 1332 } 1333 } 1334 #endif 1335 1336 /* 1337 * Take down all the tx queues first, as they reference the rx queues 1338 * (for egress updates, etc.). 1339 */ 1340 1341 for_each_txq(vi, i, txq) { 1342 free_txq(vi, txq); 1343 } 1344 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1345 for_each_ofld_txq(vi, i, ofld_txq) { 1346 free_wrq(sc, ofld_txq); 1347 } 1348 #endif 1349 1350 /* 1351 * Then take down the rx queues. 1352 */ 1353 1354 for_each_rxq(vi, i, rxq) { 1355 free_rxq(vi, rxq); 1356 } 1357 #ifdef TCP_OFFLOAD 1358 for_each_ofld_rxq(vi, i, ofld_rxq) { 1359 free_ofld_rxq(vi, ofld_rxq); 1360 } 1361 #endif 1362 1363 return (0); 1364 } 1365 1366 /* 1367 * Interrupt handler when the driver is using only 1 interrupt. This is a very 1368 * unusual scenario. 1369 * 1370 * a) Deals with errors, if any. 1371 * b) Services firmware event queue, which is taking interrupts for all other 1372 * queues. 1373 */ 1374 void 1375 t4_intr_all(void *arg) 1376 { 1377 struct adapter *sc = arg; 1378 struct sge_iq *fwq = &sc->sge.fwq; 1379 1380 MPASS(sc->intr_count == 1); 1381 1382 t4_intr_err(arg); 1383 t4_intr_evt(fwq); 1384 } 1385 1386 /* 1387 * Interrupt handler for errors (installed directly when multiple interrupts are 1388 * being used, or called by t4_intr_all). 1389 */ 1390 void 1391 t4_intr_err(void *arg) 1392 { 1393 struct adapter *sc = arg; 1394 1395 t4_write_reg(sc, MYPF_REG(A_PCIE_PF_CLI), 0); 1396 t4_slow_intr_handler(sc); 1397 } 1398 1399 /* 1400 * Interrupt handler for iq-only queues. The firmware event queue is the only 1401 * such queue right now. 1402 */ 1403 void 1404 t4_intr_evt(void *arg) 1405 { 1406 struct sge_iq *iq = arg; 1407 1408 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 1409 service_iq(iq, 0); 1410 (void) atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 1411 } 1412 } 1413 1414 /* 1415 * Interrupt handler for iq+fl queues. 1416 */ 1417 void 1418 t4_intr(void *arg) 1419 { 1420 struct sge_iq *iq = arg; 1421 1422 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 1423 service_iq_fl(iq, 0); 1424 (void) atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 1425 } 1426 } 1427 1428 #ifdef DEV_NETMAP 1429 /* 1430 * Interrupt handler for netmap rx queues. 1431 */ 1432 void 1433 t4_nm_intr(void *arg) 1434 { 1435 struct sge_nm_rxq *nm_rxq = arg; 1436 1437 if (atomic_cmpset_int(&nm_rxq->nm_state, NM_ON, NM_BUSY)) { 1438 service_nm_rxq(nm_rxq); 1439 (void) atomic_cmpset_int(&nm_rxq->nm_state, NM_BUSY, NM_ON); 1440 } 1441 } 1442 1443 /* 1444 * Interrupt handler for vectors shared between NIC and netmap rx queues. 1445 */ 1446 void 1447 t4_vi_intr(void *arg) 1448 { 1449 struct irq *irq = arg; 1450 1451 MPASS(irq->nm_rxq != NULL); 1452 t4_nm_intr(irq->nm_rxq); 1453 1454 MPASS(irq->rxq != NULL); 1455 t4_intr(irq->rxq); 1456 } 1457 #endif 1458 1459 /* 1460 * Deals with interrupts on an iq-only (no freelist) queue. 1461 */ 1462 static int 1463 service_iq(struct sge_iq *iq, int budget) 1464 { 1465 struct sge_iq *q; 1466 struct adapter *sc = iq->adapter; 1467 struct iq_desc *d = &iq->desc[iq->cidx]; 1468 int ndescs = 0, limit; 1469 int rsp_type; 1470 uint32_t lq; 1471 STAILQ_HEAD(, sge_iq) iql = STAILQ_HEAD_INITIALIZER(iql); 1472 1473 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq)); 1474 KASSERT((iq->flags & IQ_HAS_FL) == 0, 1475 ("%s: called for iq %p with fl (iq->flags 0x%x)", __func__, iq, 1476 iq->flags)); 1477 MPASS((iq->flags & IQ_ADJ_CREDIT) == 0); 1478 MPASS((iq->flags & IQ_LRO_ENABLED) == 0); 1479 1480 limit = budget ? budget : iq->qsize / 16; 1481 1482 /* 1483 * We always come back and check the descriptor ring for new indirect 1484 * interrupts and other responses after running a single handler. 1485 */ 1486 for (;;) { 1487 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) { 1488 1489 rmb(); 1490 1491 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen); 1492 lq = be32toh(d->rsp.pldbuflen_qid); 1493 1494 switch (rsp_type) { 1495 case X_RSPD_TYPE_FLBUF: 1496 panic("%s: data for an iq (%p) with no freelist", 1497 __func__, iq); 1498 1499 /* NOTREACHED */ 1500 1501 case X_RSPD_TYPE_CPL: 1502 KASSERT(d->rss.opcode < NUM_CPL_CMDS, 1503 ("%s: bad opcode %02x.", __func__, 1504 d->rss.opcode)); 1505 t4_cpl_handler[d->rss.opcode](iq, &d->rss, NULL); 1506 break; 1507 1508 case X_RSPD_TYPE_INTR: 1509 /* 1510 * There are 1K interrupt-capable queues (qids 0 1511 * through 1023). A response type indicating a 1512 * forwarded interrupt with a qid >= 1K is an 1513 * iWARP async notification. 1514 */ 1515 if (__predict_true(lq >= 1024)) { 1516 t4_an_handler(iq, &d->rsp); 1517 break; 1518 } 1519 1520 q = sc->sge.iqmap[lq - sc->sge.iq_start - 1521 sc->sge.iq_base]; 1522 if (atomic_cmpset_int(&q->state, IQS_IDLE, 1523 IQS_BUSY)) { 1524 if (service_iq_fl(q, q->qsize / 16) == 0) { 1525 (void) atomic_cmpset_int(&q->state, 1526 IQS_BUSY, IQS_IDLE); 1527 } else { 1528 STAILQ_INSERT_TAIL(&iql, q, 1529 link); 1530 } 1531 } 1532 break; 1533 1534 default: 1535 KASSERT(0, 1536 ("%s: illegal response type %d on iq %p", 1537 __func__, rsp_type, iq)); 1538 log(LOG_ERR, 1539 "%s: illegal response type %d on iq %p", 1540 device_get_nameunit(sc->dev), rsp_type, iq); 1541 break; 1542 } 1543 1544 d++; 1545 if (__predict_false(++iq->cidx == iq->sidx)) { 1546 iq->cidx = 0; 1547 iq->gen ^= F_RSPD_GEN; 1548 d = &iq->desc[0]; 1549 } 1550 if (__predict_false(++ndescs == limit)) { 1551 t4_write_reg(sc, sc->sge_gts_reg, 1552 V_CIDXINC(ndescs) | 1553 V_INGRESSQID(iq->cntxt_id) | 1554 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); 1555 ndescs = 0; 1556 1557 if (budget) { 1558 return (EINPROGRESS); 1559 } 1560 } 1561 } 1562 1563 if (STAILQ_EMPTY(&iql)) 1564 break; 1565 1566 /* 1567 * Process the head only, and send it to the back of the list if 1568 * it's still not done. 1569 */ 1570 q = STAILQ_FIRST(&iql); 1571 STAILQ_REMOVE_HEAD(&iql, link); 1572 if (service_iq_fl(q, q->qsize / 8) == 0) 1573 (void) atomic_cmpset_int(&q->state, IQS_BUSY, IQS_IDLE); 1574 else 1575 STAILQ_INSERT_TAIL(&iql, q, link); 1576 } 1577 1578 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) | 1579 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params)); 1580 1581 return (0); 1582 } 1583 1584 static inline int 1585 sort_before_lro(struct lro_ctrl *lro) 1586 { 1587 1588 return (lro->lro_mbuf_max != 0); 1589 } 1590 1591 static inline uint64_t 1592 last_flit_to_ns(struct adapter *sc, uint64_t lf) 1593 { 1594 uint64_t n = be64toh(lf) & 0xfffffffffffffff; /* 60b, not 64b. */ 1595 1596 if (n > UINT64_MAX / 1000000) 1597 return (n / sc->params.vpd.cclk * 1000000); 1598 else 1599 return (n * 1000000 / sc->params.vpd.cclk); 1600 } 1601 1602 /* 1603 * Deals with interrupts on an iq+fl queue. 1604 */ 1605 static int 1606 service_iq_fl(struct sge_iq *iq, int budget) 1607 { 1608 struct sge_rxq *rxq = iq_to_rxq(iq); 1609 struct sge_fl *fl; 1610 struct adapter *sc = iq->adapter; 1611 struct iq_desc *d = &iq->desc[iq->cidx]; 1612 int ndescs = 0, limit; 1613 int rsp_type, refill, starved; 1614 uint32_t lq; 1615 uint16_t fl_hw_cidx; 1616 struct mbuf *m0; 1617 #if defined(INET) || defined(INET6) 1618 const struct timeval lro_timeout = {0, sc->lro_timeout}; 1619 struct lro_ctrl *lro = &rxq->lro; 1620 #endif 1621 1622 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq)); 1623 MPASS(iq->flags & IQ_HAS_FL); 1624 1625 limit = budget ? budget : iq->qsize / 16; 1626 fl = &rxq->fl; 1627 fl_hw_cidx = fl->hw_cidx; /* stable snapshot */ 1628 1629 #if defined(INET) || defined(INET6) 1630 if (iq->flags & IQ_ADJ_CREDIT) { 1631 MPASS(sort_before_lro(lro)); 1632 iq->flags &= ~IQ_ADJ_CREDIT; 1633 if ((d->rsp.u.type_gen & F_RSPD_GEN) != iq->gen) { 1634 tcp_lro_flush_all(lro); 1635 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(1) | 1636 V_INGRESSQID((u32)iq->cntxt_id) | 1637 V_SEINTARM(iq->intr_params)); 1638 return (0); 1639 } 1640 ndescs = 1; 1641 } 1642 #else 1643 MPASS((iq->flags & IQ_ADJ_CREDIT) == 0); 1644 #endif 1645 1646 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) { 1647 1648 rmb(); 1649 1650 refill = 0; 1651 m0 = NULL; 1652 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen); 1653 lq = be32toh(d->rsp.pldbuflen_qid); 1654 1655 switch (rsp_type) { 1656 case X_RSPD_TYPE_FLBUF: 1657 1658 m0 = get_fl_payload(sc, fl, lq); 1659 if (__predict_false(m0 == NULL)) 1660 goto out; 1661 refill = IDXDIFF(fl->hw_cidx, fl_hw_cidx, fl->sidx) > 2; 1662 1663 if (iq->flags & IQ_RX_TIMESTAMP) { 1664 /* 1665 * Fill up rcv_tstmp but do not set M_TSTMP. 1666 * rcv_tstmp is not in the format that the 1667 * kernel expects and we don't want to mislead 1668 * it. For now this is only for custom code 1669 * that knows how to interpret cxgbe's stamp. 1670 */ 1671 m0->m_pkthdr.rcv_tstmp = 1672 last_flit_to_ns(sc, d->rsp.u.last_flit); 1673 #ifdef notyet 1674 m0->m_flags |= M_TSTMP; 1675 #endif 1676 } 1677 1678 /* fall through */ 1679 1680 case X_RSPD_TYPE_CPL: 1681 KASSERT(d->rss.opcode < NUM_CPL_CMDS, 1682 ("%s: bad opcode %02x.", __func__, d->rss.opcode)); 1683 t4_cpl_handler[d->rss.opcode](iq, &d->rss, m0); 1684 break; 1685 1686 case X_RSPD_TYPE_INTR: 1687 1688 /* 1689 * There are 1K interrupt-capable queues (qids 0 1690 * through 1023). A response type indicating a 1691 * forwarded interrupt with a qid >= 1K is an 1692 * iWARP async notification. That is the only 1693 * acceptable indirect interrupt on this queue. 1694 */ 1695 if (__predict_false(lq < 1024)) { 1696 panic("%s: indirect interrupt on iq_fl %p " 1697 "with qid %u", __func__, iq, lq); 1698 } 1699 1700 t4_an_handler(iq, &d->rsp); 1701 break; 1702 1703 default: 1704 KASSERT(0, ("%s: illegal response type %d on iq %p", 1705 __func__, rsp_type, iq)); 1706 log(LOG_ERR, "%s: illegal response type %d on iq %p", 1707 device_get_nameunit(sc->dev), rsp_type, iq); 1708 break; 1709 } 1710 1711 d++; 1712 if (__predict_false(++iq->cidx == iq->sidx)) { 1713 iq->cidx = 0; 1714 iq->gen ^= F_RSPD_GEN; 1715 d = &iq->desc[0]; 1716 } 1717 if (__predict_false(++ndescs == limit)) { 1718 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) | 1719 V_INGRESSQID(iq->cntxt_id) | 1720 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); 1721 ndescs = 0; 1722 1723 #if defined(INET) || defined(INET6) 1724 if (iq->flags & IQ_LRO_ENABLED && 1725 !sort_before_lro(lro) && 1726 sc->lro_timeout != 0) { 1727 tcp_lro_flush_inactive(lro, &lro_timeout); 1728 } 1729 #endif 1730 if (budget) { 1731 FL_LOCK(fl); 1732 refill_fl(sc, fl, 32); 1733 FL_UNLOCK(fl); 1734 1735 return (EINPROGRESS); 1736 } 1737 } 1738 if (refill) { 1739 FL_LOCK(fl); 1740 refill_fl(sc, fl, 32); 1741 FL_UNLOCK(fl); 1742 fl_hw_cidx = fl->hw_cidx; 1743 } 1744 } 1745 out: 1746 #if defined(INET) || defined(INET6) 1747 if (iq->flags & IQ_LRO_ENABLED) { 1748 if (ndescs > 0 && lro->lro_mbuf_count > 8) { 1749 MPASS(sort_before_lro(lro)); 1750 /* hold back one credit and don't flush LRO state */ 1751 iq->flags |= IQ_ADJ_CREDIT; 1752 ndescs--; 1753 } else { 1754 tcp_lro_flush_all(lro); 1755 } 1756 } 1757 #endif 1758 1759 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) | 1760 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params)); 1761 1762 FL_LOCK(fl); 1763 starved = refill_fl(sc, fl, 64); 1764 FL_UNLOCK(fl); 1765 if (__predict_false(starved != 0)) 1766 add_fl_to_sfl(sc, fl); 1767 1768 return (0); 1769 } 1770 1771 static inline int 1772 cl_has_metadata(struct sge_fl *fl, struct cluster_layout *cll) 1773 { 1774 int rc = fl->flags & FL_BUF_PACKING || cll->region1 > 0; 1775 1776 if (rc) 1777 MPASS(cll->region3 >= CL_METADATA_SIZE); 1778 1779 return (rc); 1780 } 1781 1782 static inline struct cluster_metadata * 1783 cl_metadata(struct adapter *sc, struct sge_fl *fl, struct cluster_layout *cll, 1784 caddr_t cl) 1785 { 1786 1787 if (cl_has_metadata(fl, cll)) { 1788 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx]; 1789 1790 return ((struct cluster_metadata *)(cl + swz->size) - 1); 1791 } 1792 return (NULL); 1793 } 1794 1795 static void 1796 rxb_free(struct mbuf *m) 1797 { 1798 uma_zone_t zone = m->m_ext.ext_arg1; 1799 void *cl = m->m_ext.ext_arg2; 1800 1801 uma_zfree(zone, cl); 1802 counter_u64_add(extfree_rels, 1); 1803 } 1804 1805 /* 1806 * The mbuf returned by this function could be allocated from zone_mbuf or 1807 * constructed in spare room in the cluster. 1808 * 1809 * The mbuf carries the payload in one of these ways 1810 * a) frame inside the mbuf (mbuf from zone_mbuf) 1811 * b) m_cljset (for clusters without metadata) zone_mbuf 1812 * c) m_extaddref (cluster with metadata) inline mbuf 1813 * d) m_extaddref (cluster with metadata) zone_mbuf 1814 */ 1815 static struct mbuf * 1816 get_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset, 1817 int remaining) 1818 { 1819 struct mbuf *m; 1820 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 1821 struct cluster_layout *cll = &sd->cll; 1822 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx]; 1823 struct hw_buf_info *hwb = &sc->sge.hw_buf_info[cll->hwidx]; 1824 struct cluster_metadata *clm = cl_metadata(sc, fl, cll, sd->cl); 1825 int len, blen; 1826 caddr_t payload; 1827 1828 blen = hwb->size - fl->rx_offset; /* max possible in this buf */ 1829 len = min(remaining, blen); 1830 payload = sd->cl + cll->region1 + fl->rx_offset; 1831 if (fl->flags & FL_BUF_PACKING) { 1832 const u_int l = fr_offset + len; 1833 const u_int pad = roundup2(l, fl->buf_boundary) - l; 1834 1835 if (fl->rx_offset + len + pad < hwb->size) 1836 blen = len + pad; 1837 MPASS(fl->rx_offset + blen <= hwb->size); 1838 } else { 1839 MPASS(fl->rx_offset == 0); /* not packing */ 1840 } 1841 1842 1843 if (sc->sc_do_rxcopy && len < RX_COPY_THRESHOLD) { 1844 1845 /* 1846 * Copy payload into a freshly allocated mbuf. 1847 */ 1848 1849 m = fr_offset == 0 ? 1850 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA); 1851 if (m == NULL) 1852 return (NULL); 1853 fl->mbuf_allocated++; 1854 1855 /* copy data to mbuf */ 1856 bcopy(payload, mtod(m, caddr_t), len); 1857 1858 } else if (sd->nmbuf * MSIZE < cll->region1) { 1859 1860 /* 1861 * There's spare room in the cluster for an mbuf. Create one 1862 * and associate it with the payload that's in the cluster. 1863 */ 1864 1865 MPASS(clm != NULL); 1866 m = (struct mbuf *)(sd->cl + sd->nmbuf * MSIZE); 1867 /* No bzero required */ 1868 if (m_init(m, M_NOWAIT, MT_DATA, 1869 fr_offset == 0 ? M_PKTHDR | M_NOFREE : M_NOFREE)) 1870 return (NULL); 1871 fl->mbuf_inlined++; 1872 m_extaddref(m, payload, blen, &clm->refcount, rxb_free, 1873 swz->zone, sd->cl); 1874 if (sd->nmbuf++ == 0) 1875 counter_u64_add(extfree_refs, 1); 1876 1877 } else { 1878 1879 /* 1880 * Grab an mbuf from zone_mbuf and associate it with the 1881 * payload in the cluster. 1882 */ 1883 1884 m = fr_offset == 0 ? 1885 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA); 1886 if (m == NULL) 1887 return (NULL); 1888 fl->mbuf_allocated++; 1889 if (clm != NULL) { 1890 m_extaddref(m, payload, blen, &clm->refcount, 1891 rxb_free, swz->zone, sd->cl); 1892 if (sd->nmbuf++ == 0) 1893 counter_u64_add(extfree_refs, 1); 1894 } else { 1895 m_cljset(m, sd->cl, swz->type); 1896 sd->cl = NULL; /* consumed, not a recycle candidate */ 1897 } 1898 } 1899 if (fr_offset == 0) 1900 m->m_pkthdr.len = remaining; 1901 m->m_len = len; 1902 1903 if (fl->flags & FL_BUF_PACKING) { 1904 fl->rx_offset += blen; 1905 MPASS(fl->rx_offset <= hwb->size); 1906 if (fl->rx_offset < hwb->size) 1907 return (m); /* without advancing the cidx */ 1908 } 1909 1910 if (__predict_false(++fl->cidx % 8 == 0)) { 1911 uint16_t cidx = fl->cidx / 8; 1912 1913 if (__predict_false(cidx == fl->sidx)) 1914 fl->cidx = cidx = 0; 1915 fl->hw_cidx = cidx; 1916 } 1917 fl->rx_offset = 0; 1918 1919 return (m); 1920 } 1921 1922 static struct mbuf * 1923 get_fl_payload(struct adapter *sc, struct sge_fl *fl, uint32_t len_newbuf) 1924 { 1925 struct mbuf *m0, *m, **pnext; 1926 u_int remaining; 1927 const u_int total = G_RSPD_LEN(len_newbuf); 1928 1929 if (__predict_false(fl->flags & FL_BUF_RESUME)) { 1930 M_ASSERTPKTHDR(fl->m0); 1931 MPASS(fl->m0->m_pkthdr.len == total); 1932 MPASS(fl->remaining < total); 1933 1934 m0 = fl->m0; 1935 pnext = fl->pnext; 1936 remaining = fl->remaining; 1937 fl->flags &= ~FL_BUF_RESUME; 1938 goto get_segment; 1939 } 1940 1941 if (fl->rx_offset > 0 && len_newbuf & F_RSPD_NEWBUF) { 1942 fl->rx_offset = 0; 1943 if (__predict_false(++fl->cidx % 8 == 0)) { 1944 uint16_t cidx = fl->cidx / 8; 1945 1946 if (__predict_false(cidx == fl->sidx)) 1947 fl->cidx = cidx = 0; 1948 fl->hw_cidx = cidx; 1949 } 1950 } 1951 1952 /* 1953 * Payload starts at rx_offset in the current hw buffer. Its length is 1954 * 'len' and it may span multiple hw buffers. 1955 */ 1956 1957 m0 = get_scatter_segment(sc, fl, 0, total); 1958 if (m0 == NULL) 1959 return (NULL); 1960 remaining = total - m0->m_len; 1961 pnext = &m0->m_next; 1962 while (remaining > 0) { 1963 get_segment: 1964 MPASS(fl->rx_offset == 0); 1965 m = get_scatter_segment(sc, fl, total - remaining, remaining); 1966 if (__predict_false(m == NULL)) { 1967 fl->m0 = m0; 1968 fl->pnext = pnext; 1969 fl->remaining = remaining; 1970 fl->flags |= FL_BUF_RESUME; 1971 return (NULL); 1972 } 1973 *pnext = m; 1974 pnext = &m->m_next; 1975 remaining -= m->m_len; 1976 } 1977 *pnext = NULL; 1978 1979 M_ASSERTPKTHDR(m0); 1980 return (m0); 1981 } 1982 1983 static int 1984 t4_eth_rx(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0) 1985 { 1986 struct sge_rxq *rxq = iq_to_rxq(iq); 1987 struct ifnet *ifp = rxq->ifp; 1988 struct adapter *sc = iq->adapter; 1989 const struct cpl_rx_pkt *cpl = (const void *)(rss + 1); 1990 #if defined(INET) || defined(INET6) 1991 struct lro_ctrl *lro = &rxq->lro; 1992 #endif 1993 static const int sw_hashtype[4][2] = { 1994 {M_HASHTYPE_NONE, M_HASHTYPE_NONE}, 1995 {M_HASHTYPE_RSS_IPV4, M_HASHTYPE_RSS_IPV6}, 1996 {M_HASHTYPE_RSS_TCP_IPV4, M_HASHTYPE_RSS_TCP_IPV6}, 1997 {M_HASHTYPE_RSS_UDP_IPV4, M_HASHTYPE_RSS_UDP_IPV6}, 1998 }; 1999 2000 KASSERT(m0 != NULL, ("%s: no payload with opcode %02x", __func__, 2001 rss->opcode)); 2002 2003 m0->m_pkthdr.len -= sc->params.sge.fl_pktshift; 2004 m0->m_len -= sc->params.sge.fl_pktshift; 2005 m0->m_data += sc->params.sge.fl_pktshift; 2006 2007 m0->m_pkthdr.rcvif = ifp; 2008 M_HASHTYPE_SET(m0, sw_hashtype[rss->hash_type][rss->ipv6]); 2009 m0->m_pkthdr.flowid = be32toh(rss->hash_val); 2010 2011 if (cpl->csum_calc && !(cpl->err_vec & sc->params.tp.err_vec_mask)) { 2012 if (ifp->if_capenable & IFCAP_RXCSUM && 2013 cpl->l2info & htobe32(F_RXF_IP)) { 2014 m0->m_pkthdr.csum_flags = (CSUM_IP_CHECKED | 2015 CSUM_IP_VALID | CSUM_DATA_VALID | CSUM_PSEUDO_HDR); 2016 rxq->rxcsum++; 2017 } else if (ifp->if_capenable & IFCAP_RXCSUM_IPV6 && 2018 cpl->l2info & htobe32(F_RXF_IP6)) { 2019 m0->m_pkthdr.csum_flags = (CSUM_DATA_VALID_IPV6 | 2020 CSUM_PSEUDO_HDR); 2021 rxq->rxcsum++; 2022 } 2023 2024 if (__predict_false(cpl->ip_frag)) 2025 m0->m_pkthdr.csum_data = be16toh(cpl->csum); 2026 else 2027 m0->m_pkthdr.csum_data = 0xffff; 2028 } 2029 2030 if (cpl->vlan_ex) { 2031 m0->m_pkthdr.ether_vtag = be16toh(cpl->vlan); 2032 m0->m_flags |= M_VLANTAG; 2033 rxq->vlan_extraction++; 2034 } 2035 2036 #if defined(INET) || defined(INET6) 2037 if (iq->flags & IQ_LRO_ENABLED) { 2038 if (sort_before_lro(lro)) { 2039 tcp_lro_queue_mbuf(lro, m0); 2040 return (0); /* queued for sort, then LRO */ 2041 } 2042 if (tcp_lro_rx(lro, m0, 0) == 0) 2043 return (0); /* queued for LRO */ 2044 } 2045 #endif 2046 ifp->if_input(ifp, m0); 2047 2048 return (0); 2049 } 2050 2051 /* 2052 * Must drain the wrq or make sure that someone else will. 2053 */ 2054 static void 2055 wrq_tx_drain(void *arg, int n) 2056 { 2057 struct sge_wrq *wrq = arg; 2058 struct sge_eq *eq = &wrq->eq; 2059 2060 EQ_LOCK(eq); 2061 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 2062 drain_wrq_wr_list(wrq->adapter, wrq); 2063 EQ_UNLOCK(eq); 2064 } 2065 2066 static void 2067 drain_wrq_wr_list(struct adapter *sc, struct sge_wrq *wrq) 2068 { 2069 struct sge_eq *eq = &wrq->eq; 2070 u_int available, dbdiff; /* # of hardware descriptors */ 2071 u_int n; 2072 struct wrqe *wr; 2073 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */ 2074 2075 EQ_LOCK_ASSERT_OWNED(eq); 2076 MPASS(TAILQ_EMPTY(&wrq->incomplete_wrs)); 2077 wr = STAILQ_FIRST(&wrq->wr_list); 2078 MPASS(wr != NULL); /* Must be called with something useful to do */ 2079 MPASS(eq->pidx == eq->dbidx); 2080 dbdiff = 0; 2081 2082 do { 2083 eq->cidx = read_hw_cidx(eq); 2084 if (eq->pidx == eq->cidx) 2085 available = eq->sidx - 1; 2086 else 2087 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2088 2089 MPASS(wr->wrq == wrq); 2090 n = howmany(wr->wr_len, EQ_ESIZE); 2091 if (available < n) 2092 break; 2093 2094 dst = (void *)&eq->desc[eq->pidx]; 2095 if (__predict_true(eq->sidx - eq->pidx > n)) { 2096 /* Won't wrap, won't end exactly at the status page. */ 2097 bcopy(&wr->wr[0], dst, wr->wr_len); 2098 eq->pidx += n; 2099 } else { 2100 int first_portion = (eq->sidx - eq->pidx) * EQ_ESIZE; 2101 2102 bcopy(&wr->wr[0], dst, first_portion); 2103 if (wr->wr_len > first_portion) { 2104 bcopy(&wr->wr[first_portion], &eq->desc[0], 2105 wr->wr_len - first_portion); 2106 } 2107 eq->pidx = n - (eq->sidx - eq->pidx); 2108 } 2109 wrq->tx_wrs_copied++; 2110 2111 if (available < eq->sidx / 4 && 2112 atomic_cmpset_int(&eq->equiq, 0, 1)) { 2113 /* 2114 * XXX: This is not 100% reliable with some 2115 * types of WRs. But this is a very unusual 2116 * situation for an ofld/ctrl queue anyway. 2117 */ 2118 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ | 2119 F_FW_WR_EQUEQ); 2120 } 2121 2122 dbdiff += n; 2123 if (dbdiff >= 16) { 2124 ring_eq_db(sc, eq, dbdiff); 2125 dbdiff = 0; 2126 } 2127 2128 STAILQ_REMOVE_HEAD(&wrq->wr_list, link); 2129 free_wrqe(wr); 2130 MPASS(wrq->nwr_pending > 0); 2131 wrq->nwr_pending--; 2132 MPASS(wrq->ndesc_needed >= n); 2133 wrq->ndesc_needed -= n; 2134 } while ((wr = STAILQ_FIRST(&wrq->wr_list)) != NULL); 2135 2136 if (dbdiff) 2137 ring_eq_db(sc, eq, dbdiff); 2138 } 2139 2140 /* 2141 * Doesn't fail. Holds on to work requests it can't send right away. 2142 */ 2143 void 2144 t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, struct wrqe *wr) 2145 { 2146 #ifdef INVARIANTS 2147 struct sge_eq *eq = &wrq->eq; 2148 #endif 2149 2150 EQ_LOCK_ASSERT_OWNED(eq); 2151 MPASS(wr != NULL); 2152 MPASS(wr->wr_len > 0 && wr->wr_len <= SGE_MAX_WR_LEN); 2153 MPASS((wr->wr_len & 0x7) == 0); 2154 2155 STAILQ_INSERT_TAIL(&wrq->wr_list, wr, link); 2156 wrq->nwr_pending++; 2157 wrq->ndesc_needed += howmany(wr->wr_len, EQ_ESIZE); 2158 2159 if (!TAILQ_EMPTY(&wrq->incomplete_wrs)) 2160 return; /* commit_wrq_wr will drain wr_list as well. */ 2161 2162 drain_wrq_wr_list(sc, wrq); 2163 2164 /* Doorbell must have caught up to the pidx. */ 2165 MPASS(eq->pidx == eq->dbidx); 2166 } 2167 2168 void 2169 t4_update_fl_bufsize(struct ifnet *ifp) 2170 { 2171 struct vi_info *vi = ifp->if_softc; 2172 struct adapter *sc = vi->pi->adapter; 2173 struct sge_rxq *rxq; 2174 #ifdef TCP_OFFLOAD 2175 struct sge_ofld_rxq *ofld_rxq; 2176 #endif 2177 struct sge_fl *fl; 2178 int i, maxp, mtu = ifp->if_mtu; 2179 2180 maxp = mtu_to_max_payload(sc, mtu, 0); 2181 for_each_rxq(vi, i, rxq) { 2182 fl = &rxq->fl; 2183 2184 FL_LOCK(fl); 2185 find_best_refill_source(sc, fl, maxp); 2186 FL_UNLOCK(fl); 2187 } 2188 #ifdef TCP_OFFLOAD 2189 maxp = mtu_to_max_payload(sc, mtu, 1); 2190 for_each_ofld_rxq(vi, i, ofld_rxq) { 2191 fl = &ofld_rxq->fl; 2192 2193 FL_LOCK(fl); 2194 find_best_refill_source(sc, fl, maxp); 2195 FL_UNLOCK(fl); 2196 } 2197 #endif 2198 } 2199 2200 static inline int 2201 mbuf_nsegs(struct mbuf *m) 2202 { 2203 2204 M_ASSERTPKTHDR(m); 2205 KASSERT(m->m_pkthdr.l5hlen > 0, 2206 ("%s: mbuf %p missing information on # of segments.", __func__, m)); 2207 2208 return (m->m_pkthdr.l5hlen); 2209 } 2210 2211 static inline void 2212 set_mbuf_nsegs(struct mbuf *m, uint8_t nsegs) 2213 { 2214 2215 M_ASSERTPKTHDR(m); 2216 m->m_pkthdr.l5hlen = nsegs; 2217 } 2218 2219 static inline int 2220 mbuf_cflags(struct mbuf *m) 2221 { 2222 2223 M_ASSERTPKTHDR(m); 2224 return (m->m_pkthdr.PH_loc.eight[4]); 2225 } 2226 2227 static inline void 2228 set_mbuf_cflags(struct mbuf *m, uint8_t flags) 2229 { 2230 2231 M_ASSERTPKTHDR(m); 2232 m->m_pkthdr.PH_loc.eight[4] = flags; 2233 } 2234 2235 static inline int 2236 mbuf_len16(struct mbuf *m) 2237 { 2238 int n; 2239 2240 M_ASSERTPKTHDR(m); 2241 n = m->m_pkthdr.PH_loc.eight[0]; 2242 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16); 2243 2244 return (n); 2245 } 2246 2247 static inline void 2248 set_mbuf_len16(struct mbuf *m, uint8_t len16) 2249 { 2250 2251 M_ASSERTPKTHDR(m); 2252 m->m_pkthdr.PH_loc.eight[0] = len16; 2253 } 2254 2255 #ifdef RATELIMIT 2256 static inline int 2257 mbuf_eo_nsegs(struct mbuf *m) 2258 { 2259 2260 M_ASSERTPKTHDR(m); 2261 return (m->m_pkthdr.PH_loc.eight[1]); 2262 } 2263 2264 static inline void 2265 set_mbuf_eo_nsegs(struct mbuf *m, uint8_t nsegs) 2266 { 2267 2268 M_ASSERTPKTHDR(m); 2269 m->m_pkthdr.PH_loc.eight[1] = nsegs; 2270 } 2271 2272 static inline int 2273 mbuf_eo_len16(struct mbuf *m) 2274 { 2275 int n; 2276 2277 M_ASSERTPKTHDR(m); 2278 n = m->m_pkthdr.PH_loc.eight[2]; 2279 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16); 2280 2281 return (n); 2282 } 2283 2284 static inline void 2285 set_mbuf_eo_len16(struct mbuf *m, uint8_t len16) 2286 { 2287 2288 M_ASSERTPKTHDR(m); 2289 m->m_pkthdr.PH_loc.eight[2] = len16; 2290 } 2291 2292 static inline int 2293 mbuf_eo_tsclk_tsoff(struct mbuf *m) 2294 { 2295 2296 M_ASSERTPKTHDR(m); 2297 return (m->m_pkthdr.PH_loc.eight[3]); 2298 } 2299 2300 static inline void 2301 set_mbuf_eo_tsclk_tsoff(struct mbuf *m, uint8_t tsclk_tsoff) 2302 { 2303 2304 M_ASSERTPKTHDR(m); 2305 m->m_pkthdr.PH_loc.eight[3] = tsclk_tsoff; 2306 } 2307 2308 static inline int 2309 needs_eo(struct mbuf *m) 2310 { 2311 2312 return (m->m_pkthdr.snd_tag != NULL); 2313 } 2314 #endif 2315 2316 /* 2317 * Try to allocate an mbuf to contain a raw work request. To make it 2318 * easy to construct the work request, don't allocate a chain but a 2319 * single mbuf. 2320 */ 2321 struct mbuf * 2322 alloc_wr_mbuf(int len, int how) 2323 { 2324 struct mbuf *m; 2325 2326 if (len <= MHLEN) 2327 m = m_gethdr(how, MT_DATA); 2328 else if (len <= MCLBYTES) 2329 m = m_getcl(how, MT_DATA, M_PKTHDR); 2330 else 2331 m = NULL; 2332 if (m == NULL) 2333 return (NULL); 2334 m->m_pkthdr.len = len; 2335 m->m_len = len; 2336 set_mbuf_cflags(m, MC_RAW_WR); 2337 set_mbuf_len16(m, howmany(len, 16)); 2338 return (m); 2339 } 2340 2341 static inline int 2342 needs_tso(struct mbuf *m) 2343 { 2344 2345 M_ASSERTPKTHDR(m); 2346 2347 return (m->m_pkthdr.csum_flags & CSUM_TSO); 2348 } 2349 2350 static inline int 2351 needs_l3_csum(struct mbuf *m) 2352 { 2353 2354 M_ASSERTPKTHDR(m); 2355 2356 return (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TSO)); 2357 } 2358 2359 static inline int 2360 needs_l4_csum(struct mbuf *m) 2361 { 2362 2363 M_ASSERTPKTHDR(m); 2364 2365 return (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_UDP_IPV6 | 2366 CSUM_TCP_IPV6 | CSUM_TSO)); 2367 } 2368 2369 static inline int 2370 needs_tcp_csum(struct mbuf *m) 2371 { 2372 2373 M_ASSERTPKTHDR(m); 2374 return (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_TCP_IPV6 | CSUM_TSO)); 2375 } 2376 2377 #ifdef RATELIMIT 2378 static inline int 2379 needs_udp_csum(struct mbuf *m) 2380 { 2381 2382 M_ASSERTPKTHDR(m); 2383 return (m->m_pkthdr.csum_flags & (CSUM_UDP | CSUM_UDP_IPV6)); 2384 } 2385 #endif 2386 2387 static inline int 2388 needs_vlan_insertion(struct mbuf *m) 2389 { 2390 2391 M_ASSERTPKTHDR(m); 2392 2393 return (m->m_flags & M_VLANTAG); 2394 } 2395 2396 static void * 2397 m_advance(struct mbuf **pm, int *poffset, int len) 2398 { 2399 struct mbuf *m = *pm; 2400 int offset = *poffset; 2401 uintptr_t p = 0; 2402 2403 MPASS(len > 0); 2404 2405 for (;;) { 2406 if (offset + len < m->m_len) { 2407 offset += len; 2408 p = mtod(m, uintptr_t) + offset; 2409 break; 2410 } 2411 len -= m->m_len - offset; 2412 m = m->m_next; 2413 offset = 0; 2414 MPASS(m != NULL); 2415 } 2416 *poffset = offset; 2417 *pm = m; 2418 return ((void *)p); 2419 } 2420 2421 /* 2422 * Can deal with empty mbufs in the chain that have m_len = 0, but the chain 2423 * must have at least one mbuf that's not empty. It is possible for this 2424 * routine to return 0 if skip accounts for all the contents of the mbuf chain. 2425 */ 2426 static inline int 2427 count_mbuf_nsegs(struct mbuf *m, int skip) 2428 { 2429 vm_paddr_t lastb, next; 2430 vm_offset_t va; 2431 int len, nsegs; 2432 2433 M_ASSERTPKTHDR(m); 2434 MPASS(m->m_pkthdr.len > 0); 2435 MPASS(m->m_pkthdr.len >= skip); 2436 2437 nsegs = 0; 2438 lastb = 0; 2439 for (; m; m = m->m_next) { 2440 2441 len = m->m_len; 2442 if (__predict_false(len == 0)) 2443 continue; 2444 if (skip >= len) { 2445 skip -= len; 2446 continue; 2447 } 2448 va = mtod(m, vm_offset_t) + skip; 2449 len -= skip; 2450 skip = 0; 2451 next = pmap_kextract(va); 2452 nsegs += sglist_count((void *)(uintptr_t)va, len); 2453 if (lastb + 1 == next) 2454 nsegs--; 2455 lastb = pmap_kextract(va + len - 1); 2456 } 2457 2458 return (nsegs); 2459 } 2460 2461 /* 2462 * Analyze the mbuf to determine its tx needs. The mbuf passed in may change: 2463 * a) caller can assume it's been freed if this function returns with an error. 2464 * b) it may get defragged up if the gather list is too long for the hardware. 2465 */ 2466 int 2467 parse_pkt(struct adapter *sc, struct mbuf **mp) 2468 { 2469 struct mbuf *m0 = *mp, *m; 2470 int rc, nsegs, defragged = 0, offset; 2471 struct ether_header *eh; 2472 void *l3hdr; 2473 #if defined(INET) || defined(INET6) 2474 struct tcphdr *tcp; 2475 #endif 2476 uint16_t eh_type; 2477 2478 M_ASSERTPKTHDR(m0); 2479 if (__predict_false(m0->m_pkthdr.len < ETHER_HDR_LEN)) { 2480 rc = EINVAL; 2481 fail: 2482 m_freem(m0); 2483 *mp = NULL; 2484 return (rc); 2485 } 2486 restart: 2487 /* 2488 * First count the number of gather list segments in the payload. 2489 * Defrag the mbuf if nsegs exceeds the hardware limit. 2490 */ 2491 M_ASSERTPKTHDR(m0); 2492 MPASS(m0->m_pkthdr.len > 0); 2493 nsegs = count_mbuf_nsegs(m0, 0); 2494 if (nsegs > (needs_tso(m0) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS)) { 2495 if (defragged++ > 0 || (m = m_defrag(m0, M_NOWAIT)) == NULL) { 2496 rc = EFBIG; 2497 goto fail; 2498 } 2499 *mp = m0 = m; /* update caller's copy after defrag */ 2500 goto restart; 2501 } 2502 2503 if (__predict_false(nsegs > 2 && m0->m_pkthdr.len <= MHLEN)) { 2504 m0 = m_pullup(m0, m0->m_pkthdr.len); 2505 if (m0 == NULL) { 2506 /* Should have left well enough alone. */ 2507 rc = EFBIG; 2508 goto fail; 2509 } 2510 *mp = m0; /* update caller's copy after pullup */ 2511 goto restart; 2512 } 2513 set_mbuf_nsegs(m0, nsegs); 2514 set_mbuf_cflags(m0, 0); 2515 if (sc->flags & IS_VF) 2516 set_mbuf_len16(m0, txpkt_vm_len16(nsegs, needs_tso(m0))); 2517 else 2518 set_mbuf_len16(m0, txpkt_len16(nsegs, needs_tso(m0))); 2519 2520 #ifdef RATELIMIT 2521 /* 2522 * Ethofld is limited to TCP and UDP for now, and only when L4 hw 2523 * checksumming is enabled. needs_l4_csum happens to check for all the 2524 * right things. 2525 */ 2526 if (__predict_false(needs_eo(m0) && !needs_l4_csum(m0))) 2527 m0->m_pkthdr.snd_tag = NULL; 2528 #endif 2529 2530 if (!needs_tso(m0) && 2531 #ifdef RATELIMIT 2532 !needs_eo(m0) && 2533 #endif 2534 !(sc->flags & IS_VF && (needs_l3_csum(m0) || needs_l4_csum(m0)))) 2535 return (0); 2536 2537 m = m0; 2538 eh = mtod(m, struct ether_header *); 2539 eh_type = ntohs(eh->ether_type); 2540 if (eh_type == ETHERTYPE_VLAN) { 2541 struct ether_vlan_header *evh = (void *)eh; 2542 2543 eh_type = ntohs(evh->evl_proto); 2544 m0->m_pkthdr.l2hlen = sizeof(*evh); 2545 } else 2546 m0->m_pkthdr.l2hlen = sizeof(*eh); 2547 2548 offset = 0; 2549 l3hdr = m_advance(&m, &offset, m0->m_pkthdr.l2hlen); 2550 2551 switch (eh_type) { 2552 #ifdef INET6 2553 case ETHERTYPE_IPV6: 2554 { 2555 struct ip6_hdr *ip6 = l3hdr; 2556 2557 MPASS(!needs_tso(m0) || ip6->ip6_nxt == IPPROTO_TCP); 2558 2559 m0->m_pkthdr.l3hlen = sizeof(*ip6); 2560 break; 2561 } 2562 #endif 2563 #ifdef INET 2564 case ETHERTYPE_IP: 2565 { 2566 struct ip *ip = l3hdr; 2567 2568 m0->m_pkthdr.l3hlen = ip->ip_hl * 4; 2569 break; 2570 } 2571 #endif 2572 default: 2573 panic("%s: ethertype 0x%04x unknown. if_cxgbe must be compiled" 2574 " with the same INET/INET6 options as the kernel.", 2575 __func__, eh_type); 2576 } 2577 2578 #if defined(INET) || defined(INET6) 2579 if (needs_tcp_csum(m0)) { 2580 tcp = m_advance(&m, &offset, m0->m_pkthdr.l3hlen); 2581 m0->m_pkthdr.l4hlen = tcp->th_off * 4; 2582 #ifdef RATELIMIT 2583 if (tsclk >= 0 && *(uint32_t *)(tcp + 1) == ntohl(0x0101080a)) { 2584 set_mbuf_eo_tsclk_tsoff(m0, 2585 V_FW_ETH_TX_EO_WR_TSCLK(tsclk) | 2586 V_FW_ETH_TX_EO_WR_TSOFF(sizeof(*tcp) / 2 + 1)); 2587 } else 2588 set_mbuf_eo_tsclk_tsoff(m0, 0); 2589 } else if (needs_udp_csum(m)) { 2590 m0->m_pkthdr.l4hlen = sizeof(struct udphdr); 2591 #endif 2592 } 2593 #ifdef RATELIMIT 2594 if (needs_eo(m0)) { 2595 u_int immhdrs; 2596 2597 /* EO WRs have the headers in the WR and not the GL. */ 2598 immhdrs = m0->m_pkthdr.l2hlen + m0->m_pkthdr.l3hlen + 2599 m0->m_pkthdr.l4hlen; 2600 nsegs = count_mbuf_nsegs(m0, immhdrs); 2601 set_mbuf_eo_nsegs(m0, nsegs); 2602 set_mbuf_eo_len16(m0, 2603 txpkt_eo_len16(nsegs, immhdrs, needs_tso(m0))); 2604 } 2605 #endif 2606 #endif 2607 MPASS(m0 == *mp); 2608 return (0); 2609 } 2610 2611 void * 2612 start_wrq_wr(struct sge_wrq *wrq, int len16, struct wrq_cookie *cookie) 2613 { 2614 struct sge_eq *eq = &wrq->eq; 2615 struct adapter *sc = wrq->adapter; 2616 int ndesc, available; 2617 struct wrqe *wr; 2618 void *w; 2619 2620 MPASS(len16 > 0); 2621 ndesc = howmany(len16, EQ_ESIZE / 16); 2622 MPASS(ndesc > 0 && ndesc <= SGE_MAX_WR_NDESC); 2623 2624 EQ_LOCK(eq); 2625 2626 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 2627 drain_wrq_wr_list(sc, wrq); 2628 2629 if (!STAILQ_EMPTY(&wrq->wr_list)) { 2630 slowpath: 2631 EQ_UNLOCK(eq); 2632 wr = alloc_wrqe(len16 * 16, wrq); 2633 if (__predict_false(wr == NULL)) 2634 return (NULL); 2635 cookie->pidx = -1; 2636 cookie->ndesc = ndesc; 2637 return (&wr->wr); 2638 } 2639 2640 eq->cidx = read_hw_cidx(eq); 2641 if (eq->pidx == eq->cidx) 2642 available = eq->sidx - 1; 2643 else 2644 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2645 if (available < ndesc) 2646 goto slowpath; 2647 2648 cookie->pidx = eq->pidx; 2649 cookie->ndesc = ndesc; 2650 TAILQ_INSERT_TAIL(&wrq->incomplete_wrs, cookie, link); 2651 2652 w = &eq->desc[eq->pidx]; 2653 IDXINCR(eq->pidx, ndesc, eq->sidx); 2654 if (__predict_false(cookie->pidx + ndesc > eq->sidx)) { 2655 w = &wrq->ss[0]; 2656 wrq->ss_pidx = cookie->pidx; 2657 wrq->ss_len = len16 * 16; 2658 } 2659 2660 EQ_UNLOCK(eq); 2661 2662 return (w); 2663 } 2664 2665 void 2666 commit_wrq_wr(struct sge_wrq *wrq, void *w, struct wrq_cookie *cookie) 2667 { 2668 struct sge_eq *eq = &wrq->eq; 2669 struct adapter *sc = wrq->adapter; 2670 int ndesc, pidx; 2671 struct wrq_cookie *prev, *next; 2672 2673 if (cookie->pidx == -1) { 2674 struct wrqe *wr = __containerof(w, struct wrqe, wr); 2675 2676 t4_wrq_tx(sc, wr); 2677 return; 2678 } 2679 2680 if (__predict_false(w == &wrq->ss[0])) { 2681 int n = (eq->sidx - wrq->ss_pidx) * EQ_ESIZE; 2682 2683 MPASS(wrq->ss_len > n); /* WR had better wrap around. */ 2684 bcopy(&wrq->ss[0], &eq->desc[wrq->ss_pidx], n); 2685 bcopy(&wrq->ss[n], &eq->desc[0], wrq->ss_len - n); 2686 wrq->tx_wrs_ss++; 2687 } else 2688 wrq->tx_wrs_direct++; 2689 2690 EQ_LOCK(eq); 2691 ndesc = cookie->ndesc; /* Can be more than SGE_MAX_WR_NDESC here. */ 2692 pidx = cookie->pidx; 2693 MPASS(pidx >= 0 && pidx < eq->sidx); 2694 prev = TAILQ_PREV(cookie, wrq_incomplete_wrs, link); 2695 next = TAILQ_NEXT(cookie, link); 2696 if (prev == NULL) { 2697 MPASS(pidx == eq->dbidx); 2698 if (next == NULL || ndesc >= 16) { 2699 int available; 2700 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */ 2701 2702 /* 2703 * Note that the WR via which we'll request tx updates 2704 * is at pidx and not eq->pidx, which has moved on 2705 * already. 2706 */ 2707 dst = (void *)&eq->desc[pidx]; 2708 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2709 if (available < eq->sidx / 4 && 2710 atomic_cmpset_int(&eq->equiq, 0, 1)) { 2711 /* 2712 * XXX: This is not 100% reliable with some 2713 * types of WRs. But this is a very unusual 2714 * situation for an ofld/ctrl queue anyway. 2715 */ 2716 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ | 2717 F_FW_WR_EQUEQ); 2718 } 2719 2720 ring_eq_db(wrq->adapter, eq, ndesc); 2721 } else { 2722 MPASS(IDXDIFF(next->pidx, pidx, eq->sidx) == ndesc); 2723 next->pidx = pidx; 2724 next->ndesc += ndesc; 2725 } 2726 } else { 2727 MPASS(IDXDIFF(pidx, prev->pidx, eq->sidx) == prev->ndesc); 2728 prev->ndesc += ndesc; 2729 } 2730 TAILQ_REMOVE(&wrq->incomplete_wrs, cookie, link); 2731 2732 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 2733 drain_wrq_wr_list(sc, wrq); 2734 2735 #ifdef INVARIANTS 2736 if (TAILQ_EMPTY(&wrq->incomplete_wrs)) { 2737 /* Doorbell must have caught up to the pidx. */ 2738 MPASS(wrq->eq.pidx == wrq->eq.dbidx); 2739 } 2740 #endif 2741 EQ_UNLOCK(eq); 2742 } 2743 2744 static u_int 2745 can_resume_eth_tx(struct mp_ring *r) 2746 { 2747 struct sge_eq *eq = r->cookie; 2748 2749 return (total_available_tx_desc(eq) > eq->sidx / 8); 2750 } 2751 2752 static inline int 2753 cannot_use_txpkts(struct mbuf *m) 2754 { 2755 /* maybe put a GL limit too, to avoid silliness? */ 2756 2757 return (needs_tso(m) || (mbuf_cflags(m) & MC_RAW_WR) != 0); 2758 } 2759 2760 static inline int 2761 discard_tx(struct sge_eq *eq) 2762 { 2763 2764 return ((eq->flags & (EQ_ENABLED | EQ_QFLUSH)) != EQ_ENABLED); 2765 } 2766 2767 static inline int 2768 wr_can_update_eq(struct fw_eth_tx_pkts_wr *wr) 2769 { 2770 2771 switch (G_FW_WR_OP(be32toh(wr->op_pkd))) { 2772 case FW_ULPTX_WR: 2773 case FW_ETH_TX_PKT_WR: 2774 case FW_ETH_TX_PKTS_WR: 2775 case FW_ETH_TX_PKT_VM_WR: 2776 return (1); 2777 default: 2778 return (0); 2779 } 2780 } 2781 2782 /* 2783 * r->items[cidx] to r->items[pidx], with a wraparound at r->size, are ready to 2784 * be consumed. Return the actual number consumed. 0 indicates a stall. 2785 */ 2786 static u_int 2787 eth_tx(struct mp_ring *r, u_int cidx, u_int pidx) 2788 { 2789 struct sge_txq *txq = r->cookie; 2790 struct sge_eq *eq = &txq->eq; 2791 struct ifnet *ifp = txq->ifp; 2792 struct vi_info *vi = ifp->if_softc; 2793 struct port_info *pi = vi->pi; 2794 struct adapter *sc = pi->adapter; 2795 u_int total, remaining; /* # of packets */ 2796 u_int available, dbdiff; /* # of hardware descriptors */ 2797 u_int n, next_cidx; 2798 struct mbuf *m0, *tail; 2799 struct txpkts txp; 2800 struct fw_eth_tx_pkts_wr *wr; /* any fw WR struct will do */ 2801 2802 remaining = IDXDIFF(pidx, cidx, r->size); 2803 MPASS(remaining > 0); /* Must not be called without work to do. */ 2804 total = 0; 2805 2806 TXQ_LOCK(txq); 2807 if (__predict_false(discard_tx(eq))) { 2808 while (cidx != pidx) { 2809 m0 = r->items[cidx]; 2810 m_freem(m0); 2811 if (++cidx == r->size) 2812 cidx = 0; 2813 } 2814 reclaim_tx_descs(txq, 2048); 2815 total = remaining; 2816 goto done; 2817 } 2818 2819 /* How many hardware descriptors do we have readily available. */ 2820 if (eq->pidx == eq->cidx) 2821 available = eq->sidx - 1; 2822 else 2823 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2824 dbdiff = IDXDIFF(eq->pidx, eq->dbidx, eq->sidx); 2825 2826 while (remaining > 0) { 2827 2828 m0 = r->items[cidx]; 2829 M_ASSERTPKTHDR(m0); 2830 MPASS(m0->m_nextpkt == NULL); 2831 2832 if (available < SGE_MAX_WR_NDESC) { 2833 available += reclaim_tx_descs(txq, 64); 2834 if (available < howmany(mbuf_len16(m0), EQ_ESIZE / 16)) 2835 break; /* out of descriptors */ 2836 } 2837 2838 next_cidx = cidx + 1; 2839 if (__predict_false(next_cidx == r->size)) 2840 next_cidx = 0; 2841 2842 wr = (void *)&eq->desc[eq->pidx]; 2843 if (sc->flags & IS_VF) { 2844 total++; 2845 remaining--; 2846 ETHER_BPF_MTAP(ifp, m0); 2847 n = write_txpkt_vm_wr(sc, txq, (void *)wr, m0, 2848 available); 2849 } else if (remaining > 1 && 2850 try_txpkts(m0, r->items[next_cidx], &txp, available) == 0) { 2851 2852 /* pkts at cidx, next_cidx should both be in txp. */ 2853 MPASS(txp.npkt == 2); 2854 tail = r->items[next_cidx]; 2855 MPASS(tail->m_nextpkt == NULL); 2856 ETHER_BPF_MTAP(ifp, m0); 2857 ETHER_BPF_MTAP(ifp, tail); 2858 m0->m_nextpkt = tail; 2859 2860 if (__predict_false(++next_cidx == r->size)) 2861 next_cidx = 0; 2862 2863 while (next_cidx != pidx) { 2864 if (add_to_txpkts(r->items[next_cidx], &txp, 2865 available) != 0) 2866 break; 2867 tail->m_nextpkt = r->items[next_cidx]; 2868 tail = tail->m_nextpkt; 2869 ETHER_BPF_MTAP(ifp, tail); 2870 if (__predict_false(++next_cidx == r->size)) 2871 next_cidx = 0; 2872 } 2873 2874 n = write_txpkts_wr(txq, wr, m0, &txp, available); 2875 total += txp.npkt; 2876 remaining -= txp.npkt; 2877 } else if (mbuf_cflags(m0) & MC_RAW_WR) { 2878 total++; 2879 remaining--; 2880 n = write_raw_wr(txq, (void *)wr, m0, available); 2881 } else { 2882 total++; 2883 remaining--; 2884 ETHER_BPF_MTAP(ifp, m0); 2885 n = write_txpkt_wr(txq, (void *)wr, m0, available); 2886 } 2887 MPASS(n >= 1 && n <= available && n <= SGE_MAX_WR_NDESC); 2888 2889 available -= n; 2890 dbdiff += n; 2891 IDXINCR(eq->pidx, n, eq->sidx); 2892 2893 if (wr_can_update_eq(wr)) { 2894 if (total_available_tx_desc(eq) < eq->sidx / 4 && 2895 atomic_cmpset_int(&eq->equiq, 0, 1)) { 2896 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ | 2897 F_FW_WR_EQUEQ); 2898 eq->equeqidx = eq->pidx; 2899 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 2900 32) { 2901 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ); 2902 eq->equeqidx = eq->pidx; 2903 } 2904 } 2905 2906 if (dbdiff >= 16 && remaining >= 4) { 2907 ring_eq_db(sc, eq, dbdiff); 2908 available += reclaim_tx_descs(txq, 4 * dbdiff); 2909 dbdiff = 0; 2910 } 2911 2912 cidx = next_cidx; 2913 } 2914 if (dbdiff != 0) { 2915 ring_eq_db(sc, eq, dbdiff); 2916 reclaim_tx_descs(txq, 32); 2917 } 2918 done: 2919 TXQ_UNLOCK(txq); 2920 2921 return (total); 2922 } 2923 2924 static inline void 2925 init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int pktc_idx, 2926 int qsize) 2927 { 2928 2929 KASSERT(tmr_idx >= 0 && tmr_idx < SGE_NTIMERS, 2930 ("%s: bad tmr_idx %d", __func__, tmr_idx)); 2931 KASSERT(pktc_idx < SGE_NCOUNTERS, /* -ve is ok, means don't use */ 2932 ("%s: bad pktc_idx %d", __func__, pktc_idx)); 2933 2934 iq->flags = 0; 2935 iq->adapter = sc; 2936 iq->intr_params = V_QINTR_TIMER_IDX(tmr_idx); 2937 iq->intr_pktc_idx = SGE_NCOUNTERS - 1; 2938 if (pktc_idx >= 0) { 2939 iq->intr_params |= F_QINTR_CNT_EN; 2940 iq->intr_pktc_idx = pktc_idx; 2941 } 2942 iq->qsize = roundup2(qsize, 16); /* See FW_IQ_CMD/iqsize */ 2943 iq->sidx = iq->qsize - sc->params.sge.spg_len / IQ_ESIZE; 2944 } 2945 2946 static inline void 2947 init_fl(struct adapter *sc, struct sge_fl *fl, int qsize, int maxp, char *name) 2948 { 2949 2950 fl->qsize = qsize; 2951 fl->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE; 2952 strlcpy(fl->lockname, name, sizeof(fl->lockname)); 2953 if (sc->flags & BUF_PACKING_OK && 2954 ((!is_t4(sc) && buffer_packing) || /* T5+: enabled unless 0 */ 2955 (is_t4(sc) && buffer_packing == 1)))/* T4: disabled unless 1 */ 2956 fl->flags |= FL_BUF_PACKING; 2957 find_best_refill_source(sc, fl, maxp); 2958 find_safe_refill_source(sc, fl); 2959 } 2960 2961 static inline void 2962 init_eq(struct adapter *sc, struct sge_eq *eq, int eqtype, int qsize, 2963 uint8_t tx_chan, uint16_t iqid, char *name) 2964 { 2965 KASSERT(eqtype <= EQ_TYPEMASK, ("%s: bad qtype %d", __func__, eqtype)); 2966 2967 eq->flags = eqtype & EQ_TYPEMASK; 2968 eq->tx_chan = tx_chan; 2969 eq->iqid = iqid; 2970 eq->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE; 2971 strlcpy(eq->lockname, name, sizeof(eq->lockname)); 2972 } 2973 2974 static int 2975 alloc_ring(struct adapter *sc, size_t len, bus_dma_tag_t *tag, 2976 bus_dmamap_t *map, bus_addr_t *pa, void **va) 2977 { 2978 int rc; 2979 2980 rc = bus_dma_tag_create(sc->dmat, 512, 0, BUS_SPACE_MAXADDR, 2981 BUS_SPACE_MAXADDR, NULL, NULL, len, 1, len, 0, NULL, NULL, tag); 2982 if (rc != 0) { 2983 device_printf(sc->dev, "cannot allocate DMA tag: %d\n", rc); 2984 goto done; 2985 } 2986 2987 rc = bus_dmamem_alloc(*tag, va, 2988 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, map); 2989 if (rc != 0) { 2990 device_printf(sc->dev, "cannot allocate DMA memory: %d\n", rc); 2991 goto done; 2992 } 2993 2994 rc = bus_dmamap_load(*tag, *map, *va, len, oneseg_dma_callback, pa, 0); 2995 if (rc != 0) { 2996 device_printf(sc->dev, "cannot load DMA map: %d\n", rc); 2997 goto done; 2998 } 2999 done: 3000 if (rc) 3001 free_ring(sc, *tag, *map, *pa, *va); 3002 3003 return (rc); 3004 } 3005 3006 static int 3007 free_ring(struct adapter *sc, bus_dma_tag_t tag, bus_dmamap_t map, 3008 bus_addr_t pa, void *va) 3009 { 3010 if (pa) 3011 bus_dmamap_unload(tag, map); 3012 if (va) 3013 bus_dmamem_free(tag, va, map); 3014 if (tag) 3015 bus_dma_tag_destroy(tag); 3016 3017 return (0); 3018 } 3019 3020 /* 3021 * Allocates the ring for an ingress queue and an optional freelist. If the 3022 * freelist is specified it will be allocated and then associated with the 3023 * ingress queue. 3024 * 3025 * Returns errno on failure. Resources allocated up to that point may still be 3026 * allocated. Caller is responsible for cleanup in case this function fails. 3027 * 3028 * If the ingress queue will take interrupts directly then the intr_idx 3029 * specifies the vector, starting from 0. -1 means the interrupts for this 3030 * queue should be forwarded to the fwq. 3031 */ 3032 static int 3033 alloc_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl, 3034 int intr_idx, int cong) 3035 { 3036 int rc, i, cntxt_id; 3037 size_t len; 3038 struct fw_iq_cmd c; 3039 struct port_info *pi = vi->pi; 3040 struct adapter *sc = iq->adapter; 3041 struct sge_params *sp = &sc->params.sge; 3042 __be32 v = 0; 3043 3044 len = iq->qsize * IQ_ESIZE; 3045 rc = alloc_ring(sc, len, &iq->desc_tag, &iq->desc_map, &iq->ba, 3046 (void **)&iq->desc); 3047 if (rc != 0) 3048 return (rc); 3049 3050 bzero(&c, sizeof(c)); 3051 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 3052 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) | 3053 V_FW_IQ_CMD_VFN(0)); 3054 3055 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART | 3056 FW_LEN16(c)); 3057 3058 /* Special handling for firmware event queue */ 3059 if (iq == &sc->sge.fwq) 3060 v |= F_FW_IQ_CMD_IQASYNCH; 3061 3062 if (intr_idx < 0) { 3063 /* Forwarded interrupts, all headed to fwq */ 3064 v |= F_FW_IQ_CMD_IQANDST; 3065 v |= V_FW_IQ_CMD_IQANDSTINDEX(sc->sge.fwq.cntxt_id); 3066 } else { 3067 KASSERT(intr_idx < sc->intr_count, 3068 ("%s: invalid direct intr_idx %d", __func__, intr_idx)); 3069 v |= V_FW_IQ_CMD_IQANDSTINDEX(intr_idx); 3070 } 3071 3072 c.type_to_iqandstindex = htobe32(v | 3073 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) | 3074 V_FW_IQ_CMD_VIID(vi->viid) | 3075 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT)); 3076 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->tx_chan) | 3077 F_FW_IQ_CMD_IQGTSMODE | 3078 V_FW_IQ_CMD_IQINTCNTTHRESH(iq->intr_pktc_idx) | 3079 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4)); 3080 c.iqsize = htobe16(iq->qsize); 3081 c.iqaddr = htobe64(iq->ba); 3082 if (cong >= 0) 3083 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN); 3084 3085 if (fl) { 3086 mtx_init(&fl->fl_lock, fl->lockname, NULL, MTX_DEF); 3087 3088 len = fl->qsize * EQ_ESIZE; 3089 rc = alloc_ring(sc, len, &fl->desc_tag, &fl->desc_map, 3090 &fl->ba, (void **)&fl->desc); 3091 if (rc) 3092 return (rc); 3093 3094 /* Allocate space for one software descriptor per buffer. */ 3095 rc = alloc_fl_sdesc(fl); 3096 if (rc != 0) { 3097 device_printf(sc->dev, 3098 "failed to setup fl software descriptors: %d\n", 3099 rc); 3100 return (rc); 3101 } 3102 3103 if (fl->flags & FL_BUF_PACKING) { 3104 fl->lowat = roundup2(sp->fl_starve_threshold2, 8); 3105 fl->buf_boundary = sp->pack_boundary; 3106 } else { 3107 fl->lowat = roundup2(sp->fl_starve_threshold, 8); 3108 fl->buf_boundary = 16; 3109 } 3110 if (fl_pad && fl->buf_boundary < sp->pad_boundary) 3111 fl->buf_boundary = sp->pad_boundary; 3112 3113 c.iqns_to_fl0congen |= 3114 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) | 3115 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO | 3116 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) | 3117 (fl->flags & FL_BUF_PACKING ? F_FW_IQ_CMD_FL0PACKEN : 3118 0)); 3119 if (cong >= 0) { 3120 c.iqns_to_fl0congen |= 3121 htobe32(V_FW_IQ_CMD_FL0CNGCHMAP(cong) | 3122 F_FW_IQ_CMD_FL0CONGCIF | 3123 F_FW_IQ_CMD_FL0CONGEN); 3124 } 3125 c.fl0dcaen_to_fl0cidxfthresh = 3126 htobe16(V_FW_IQ_CMD_FL0FBMIN(chip_id(sc) <= CHELSIO_T5 ? 3127 X_FETCHBURSTMIN_128B : X_FETCHBURSTMIN_64B) | 3128 V_FW_IQ_CMD_FL0FBMAX(chip_id(sc) <= CHELSIO_T5 ? 3129 X_FETCHBURSTMAX_512B : X_FETCHBURSTMAX_256B)); 3130 c.fl0size = htobe16(fl->qsize); 3131 c.fl0addr = htobe64(fl->ba); 3132 } 3133 3134 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3135 if (rc != 0) { 3136 device_printf(sc->dev, 3137 "failed to create ingress queue: %d\n", rc); 3138 return (rc); 3139 } 3140 3141 iq->cidx = 0; 3142 iq->gen = F_RSPD_GEN; 3143 iq->intr_next = iq->intr_params; 3144 iq->cntxt_id = be16toh(c.iqid); 3145 iq->abs_id = be16toh(c.physiqid); 3146 iq->flags |= IQ_ALLOCATED; 3147 3148 cntxt_id = iq->cntxt_id - sc->sge.iq_start; 3149 if (cntxt_id >= sc->sge.niq) { 3150 panic ("%s: iq->cntxt_id (%d) more than the max (%d)", __func__, 3151 cntxt_id, sc->sge.niq - 1); 3152 } 3153 sc->sge.iqmap[cntxt_id] = iq; 3154 3155 if (fl) { 3156 u_int qid; 3157 3158 iq->flags |= IQ_HAS_FL; 3159 fl->cntxt_id = be16toh(c.fl0id); 3160 fl->pidx = fl->cidx = 0; 3161 3162 cntxt_id = fl->cntxt_id - sc->sge.eq_start; 3163 if (cntxt_id >= sc->sge.neq) { 3164 panic("%s: fl->cntxt_id (%d) more than the max (%d)", 3165 __func__, cntxt_id, sc->sge.neq - 1); 3166 } 3167 sc->sge.eqmap[cntxt_id] = (void *)fl; 3168 3169 qid = fl->cntxt_id; 3170 if (isset(&sc->doorbells, DOORBELL_UDB)) { 3171 uint32_t s_qpp = sc->params.sge.eq_s_qpp; 3172 uint32_t mask = (1 << s_qpp) - 1; 3173 volatile uint8_t *udb; 3174 3175 udb = sc->udbs_base + UDBS_DB_OFFSET; 3176 udb += (qid >> s_qpp) << PAGE_SHIFT; 3177 qid &= mask; 3178 if (qid < PAGE_SIZE / UDBS_SEG_SIZE) { 3179 udb += qid << UDBS_SEG_SHIFT; 3180 qid = 0; 3181 } 3182 fl->udb = (volatile void *)udb; 3183 } 3184 fl->dbval = V_QID(qid) | sc->chip_params->sge_fl_db; 3185 3186 FL_LOCK(fl); 3187 /* Enough to make sure the SGE doesn't think it's starved */ 3188 refill_fl(sc, fl, fl->lowat); 3189 FL_UNLOCK(fl); 3190 } 3191 3192 if (chip_id(sc) >= CHELSIO_T5 && !(sc->flags & IS_VF) && cong >= 0) { 3193 uint32_t param, val; 3194 3195 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 3196 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) | 3197 V_FW_PARAMS_PARAM_YZ(iq->cntxt_id); 3198 if (cong == 0) 3199 val = 1 << 19; 3200 else { 3201 val = 2 << 19; 3202 for (i = 0; i < 4; i++) { 3203 if (cong & (1 << i)) 3204 val |= 1 << (i << 2); 3205 } 3206 } 3207 3208 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 3209 if (rc != 0) { 3210 /* report error but carry on */ 3211 device_printf(sc->dev, 3212 "failed to set congestion manager context for " 3213 "ingress queue %d: %d\n", iq->cntxt_id, rc); 3214 } 3215 } 3216 3217 /* Enable IQ interrupts */ 3218 atomic_store_rel_int(&iq->state, IQS_IDLE); 3219 t4_write_reg(sc, sc->sge_gts_reg, V_SEINTARM(iq->intr_params) | 3220 V_INGRESSQID(iq->cntxt_id)); 3221 3222 return (0); 3223 } 3224 3225 static int 3226 free_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl) 3227 { 3228 int rc; 3229 struct adapter *sc = iq->adapter; 3230 device_t dev; 3231 3232 if (sc == NULL) 3233 return (0); /* nothing to do */ 3234 3235 dev = vi ? vi->dev : sc->dev; 3236 3237 if (iq->flags & IQ_ALLOCATED) { 3238 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0, 3239 FW_IQ_TYPE_FL_INT_CAP, iq->cntxt_id, 3240 fl ? fl->cntxt_id : 0xffff, 0xffff); 3241 if (rc != 0) { 3242 device_printf(dev, 3243 "failed to free queue %p: %d\n", iq, rc); 3244 return (rc); 3245 } 3246 iq->flags &= ~IQ_ALLOCATED; 3247 } 3248 3249 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, iq->desc); 3250 3251 bzero(iq, sizeof(*iq)); 3252 3253 if (fl) { 3254 free_ring(sc, fl->desc_tag, fl->desc_map, fl->ba, 3255 fl->desc); 3256 3257 if (fl->sdesc) 3258 free_fl_sdesc(sc, fl); 3259 3260 if (mtx_initialized(&fl->fl_lock)) 3261 mtx_destroy(&fl->fl_lock); 3262 3263 bzero(fl, sizeof(*fl)); 3264 } 3265 3266 return (0); 3267 } 3268 3269 static void 3270 add_iq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid, 3271 struct sge_iq *iq) 3272 { 3273 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3274 3275 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, &iq->ba, 3276 "bus address of descriptor ring"); 3277 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3278 iq->qsize * IQ_ESIZE, "descriptor ring size in bytes"); 3279 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "abs_id", 3280 CTLTYPE_INT | CTLFLAG_RD, &iq->abs_id, 0, sysctl_uint16, "I", 3281 "absolute id of the queue"); 3282 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 3283 CTLTYPE_INT | CTLFLAG_RD, &iq->cntxt_id, 0, sysctl_uint16, "I", 3284 "SGE context id of the queue"); 3285 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx", 3286 CTLTYPE_INT | CTLFLAG_RD, &iq->cidx, 0, sysctl_uint16, "I", 3287 "consumer index"); 3288 } 3289 3290 static void 3291 add_fl_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx, 3292 struct sysctl_oid *oid, struct sge_fl *fl) 3293 { 3294 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3295 3296 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL, 3297 "freelist"); 3298 children = SYSCTL_CHILDREN(oid); 3299 3300 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, 3301 &fl->ba, "bus address of descriptor ring"); 3302 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3303 fl->sidx * EQ_ESIZE + sc->params.sge.spg_len, 3304 "desc ring size in bytes"); 3305 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 3306 CTLTYPE_INT | CTLFLAG_RD, &fl->cntxt_id, 0, sysctl_uint16, "I", 3307 "SGE context id of the freelist"); 3308 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "padding", CTLFLAG_RD, NULL, 3309 fl_pad ? 1 : 0, "padding enabled"); 3310 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "packing", CTLFLAG_RD, NULL, 3311 fl->flags & FL_BUF_PACKING ? 1 : 0, "packing enabled"); 3312 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &fl->cidx, 3313 0, "consumer index"); 3314 if (fl->flags & FL_BUF_PACKING) { 3315 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rx_offset", 3316 CTLFLAG_RD, &fl->rx_offset, 0, "packing rx offset"); 3317 } 3318 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &fl->pidx, 3319 0, "producer index"); 3320 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_allocated", 3321 CTLFLAG_RD, &fl->mbuf_allocated, "# of mbuf allocated"); 3322 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_inlined", 3323 CTLFLAG_RD, &fl->mbuf_inlined, "# of mbuf inlined in clusters"); 3324 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_allocated", 3325 CTLFLAG_RD, &fl->cl_allocated, "# of clusters allocated"); 3326 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_recycled", 3327 CTLFLAG_RD, &fl->cl_recycled, "# of clusters recycled"); 3328 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_fast_recycled", 3329 CTLFLAG_RD, &fl->cl_fast_recycled, "# of clusters recycled (fast)"); 3330 } 3331 3332 static int 3333 alloc_fwq(struct adapter *sc) 3334 { 3335 int rc, intr_idx; 3336 struct sge_iq *fwq = &sc->sge.fwq; 3337 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev); 3338 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3339 3340 init_iq(fwq, sc, 0, 0, FW_IQ_QSIZE); 3341 if (sc->flags & IS_VF) 3342 intr_idx = 0; 3343 else 3344 intr_idx = sc->intr_count > 1 ? 1 : 0; 3345 rc = alloc_iq_fl(&sc->port[0]->vi[0], fwq, NULL, intr_idx, -1); 3346 if (rc != 0) { 3347 device_printf(sc->dev, 3348 "failed to create firmware event queue: %d\n", rc); 3349 return (rc); 3350 } 3351 3352 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "fwq", CTLFLAG_RD, 3353 NULL, "firmware event queue"); 3354 add_iq_sysctls(&sc->ctx, oid, fwq); 3355 3356 return (0); 3357 } 3358 3359 static int 3360 free_fwq(struct adapter *sc) 3361 { 3362 return free_iq_fl(NULL, &sc->sge.fwq, NULL); 3363 } 3364 3365 static int 3366 alloc_ctrlq(struct adapter *sc, struct sge_wrq *ctrlq, int idx, 3367 struct sysctl_oid *oid) 3368 { 3369 int rc; 3370 char name[16]; 3371 struct sysctl_oid_list *children; 3372 3373 snprintf(name, sizeof(name), "%s ctrlq%d", device_get_nameunit(sc->dev), 3374 idx); 3375 init_eq(sc, &ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE, sc->port[idx]->tx_chan, 3376 sc->sge.fwq.cntxt_id, name); 3377 3378 children = SYSCTL_CHILDREN(oid); 3379 snprintf(name, sizeof(name), "%d", idx); 3380 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, name, CTLFLAG_RD, 3381 NULL, "ctrl queue"); 3382 rc = alloc_wrq(sc, NULL, ctrlq, oid); 3383 3384 return (rc); 3385 } 3386 3387 int 3388 tnl_cong(struct port_info *pi, int drop) 3389 { 3390 3391 if (drop == -1) 3392 return (-1); 3393 else if (drop == 1) 3394 return (0); 3395 else 3396 return (pi->rx_e_chan_map); 3397 } 3398 3399 static int 3400 alloc_rxq(struct vi_info *vi, struct sge_rxq *rxq, int intr_idx, int idx, 3401 struct sysctl_oid *oid) 3402 { 3403 int rc; 3404 struct adapter *sc = vi->pi->adapter; 3405 struct sysctl_oid_list *children; 3406 char name[16]; 3407 3408 rc = alloc_iq_fl(vi, &rxq->iq, &rxq->fl, intr_idx, 3409 tnl_cong(vi->pi, cong_drop)); 3410 if (rc != 0) 3411 return (rc); 3412 3413 if (idx == 0) 3414 sc->sge.iq_base = rxq->iq.abs_id - rxq->iq.cntxt_id; 3415 else 3416 KASSERT(rxq->iq.cntxt_id + sc->sge.iq_base == rxq->iq.abs_id, 3417 ("iq_base mismatch")); 3418 KASSERT(sc->sge.iq_base == 0 || sc->flags & IS_VF, 3419 ("PF with non-zero iq_base")); 3420 3421 /* 3422 * The freelist is just barely above the starvation threshold right now, 3423 * fill it up a bit more. 3424 */ 3425 FL_LOCK(&rxq->fl); 3426 refill_fl(sc, &rxq->fl, 128); 3427 FL_UNLOCK(&rxq->fl); 3428 3429 #if defined(INET) || defined(INET6) 3430 rc = tcp_lro_init_args(&rxq->lro, vi->ifp, lro_entries, lro_mbufs); 3431 if (rc != 0) 3432 return (rc); 3433 MPASS(rxq->lro.ifp == vi->ifp); /* also indicates LRO init'ed */ 3434 3435 if (vi->ifp->if_capenable & IFCAP_LRO) 3436 rxq->iq.flags |= IQ_LRO_ENABLED; 3437 #endif 3438 if (vi->ifp->if_capenable & IFCAP_HWRXTSTMP) 3439 rxq->iq.flags |= IQ_RX_TIMESTAMP; 3440 rxq->ifp = vi->ifp; 3441 3442 children = SYSCTL_CHILDREN(oid); 3443 3444 snprintf(name, sizeof(name), "%d", idx); 3445 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 3446 NULL, "rx queue"); 3447 children = SYSCTL_CHILDREN(oid); 3448 3449 add_iq_sysctls(&vi->ctx, oid, &rxq->iq); 3450 #if defined(INET) || defined(INET6) 3451 SYSCTL_ADD_U64(&vi->ctx, children, OID_AUTO, "lro_queued", CTLFLAG_RD, 3452 &rxq->lro.lro_queued, 0, NULL); 3453 SYSCTL_ADD_U64(&vi->ctx, children, OID_AUTO, "lro_flushed", CTLFLAG_RD, 3454 &rxq->lro.lro_flushed, 0, NULL); 3455 #endif 3456 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "rxcsum", CTLFLAG_RD, 3457 &rxq->rxcsum, "# of times hardware assisted with checksum"); 3458 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_extraction", 3459 CTLFLAG_RD, &rxq->vlan_extraction, 3460 "# of times hardware extracted 802.1Q tag"); 3461 3462 add_fl_sysctls(sc, &vi->ctx, oid, &rxq->fl); 3463 3464 return (rc); 3465 } 3466 3467 static int 3468 free_rxq(struct vi_info *vi, struct sge_rxq *rxq) 3469 { 3470 int rc; 3471 3472 #if defined(INET) || defined(INET6) 3473 if (rxq->lro.ifp) { 3474 tcp_lro_free(&rxq->lro); 3475 rxq->lro.ifp = NULL; 3476 } 3477 #endif 3478 3479 rc = free_iq_fl(vi, &rxq->iq, &rxq->fl); 3480 if (rc == 0) 3481 bzero(rxq, sizeof(*rxq)); 3482 3483 return (rc); 3484 } 3485 3486 #ifdef TCP_OFFLOAD 3487 static int 3488 alloc_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq, 3489 int intr_idx, int idx, struct sysctl_oid *oid) 3490 { 3491 struct port_info *pi = vi->pi; 3492 int rc; 3493 struct sysctl_oid_list *children; 3494 char name[16]; 3495 3496 rc = alloc_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl, intr_idx, 0); 3497 if (rc != 0) 3498 return (rc); 3499 3500 children = SYSCTL_CHILDREN(oid); 3501 3502 snprintf(name, sizeof(name), "%d", idx); 3503 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 3504 NULL, "rx queue"); 3505 add_iq_sysctls(&vi->ctx, oid, &ofld_rxq->iq); 3506 add_fl_sysctls(pi->adapter, &vi->ctx, oid, &ofld_rxq->fl); 3507 3508 return (rc); 3509 } 3510 3511 static int 3512 free_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq) 3513 { 3514 int rc; 3515 3516 rc = free_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl); 3517 if (rc == 0) 3518 bzero(ofld_rxq, sizeof(*ofld_rxq)); 3519 3520 return (rc); 3521 } 3522 #endif 3523 3524 #ifdef DEV_NETMAP 3525 static int 3526 alloc_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq, int intr_idx, 3527 int idx, struct sysctl_oid *oid) 3528 { 3529 int rc; 3530 struct sysctl_oid_list *children; 3531 struct sysctl_ctx_list *ctx; 3532 char name[16]; 3533 size_t len; 3534 struct adapter *sc = vi->pi->adapter; 3535 struct netmap_adapter *na = NA(vi->ifp); 3536 3537 MPASS(na != NULL); 3538 3539 len = vi->qsize_rxq * IQ_ESIZE; 3540 rc = alloc_ring(sc, len, &nm_rxq->iq_desc_tag, &nm_rxq->iq_desc_map, 3541 &nm_rxq->iq_ba, (void **)&nm_rxq->iq_desc); 3542 if (rc != 0) 3543 return (rc); 3544 3545 len = na->num_rx_desc * EQ_ESIZE + sc->params.sge.spg_len; 3546 rc = alloc_ring(sc, len, &nm_rxq->fl_desc_tag, &nm_rxq->fl_desc_map, 3547 &nm_rxq->fl_ba, (void **)&nm_rxq->fl_desc); 3548 if (rc != 0) 3549 return (rc); 3550 3551 nm_rxq->vi = vi; 3552 nm_rxq->nid = idx; 3553 nm_rxq->iq_cidx = 0; 3554 nm_rxq->iq_sidx = vi->qsize_rxq - sc->params.sge.spg_len / IQ_ESIZE; 3555 nm_rxq->iq_gen = F_RSPD_GEN; 3556 nm_rxq->fl_pidx = nm_rxq->fl_cidx = 0; 3557 nm_rxq->fl_sidx = na->num_rx_desc; 3558 nm_rxq->intr_idx = intr_idx; 3559 nm_rxq->iq_cntxt_id = INVALID_NM_RXQ_CNTXT_ID; 3560 3561 ctx = &vi->ctx; 3562 children = SYSCTL_CHILDREN(oid); 3563 3564 snprintf(name, sizeof(name), "%d", idx); 3565 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, name, CTLFLAG_RD, NULL, 3566 "rx queue"); 3567 children = SYSCTL_CHILDREN(oid); 3568 3569 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "abs_id", 3570 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_abs_id, 0, sysctl_uint16, 3571 "I", "absolute id of the queue"); 3572 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 3573 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cntxt_id, 0, sysctl_uint16, 3574 "I", "SGE context id of the queue"); 3575 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx", 3576 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cidx, 0, sysctl_uint16, "I", 3577 "consumer index"); 3578 3579 children = SYSCTL_CHILDREN(oid); 3580 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL, 3581 "freelist"); 3582 children = SYSCTL_CHILDREN(oid); 3583 3584 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 3585 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->fl_cntxt_id, 0, sysctl_uint16, 3586 "I", "SGE context id of the freelist"); 3587 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, 3588 &nm_rxq->fl_cidx, 0, "consumer index"); 3589 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, 3590 &nm_rxq->fl_pidx, 0, "producer index"); 3591 3592 return (rc); 3593 } 3594 3595 3596 static int 3597 free_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq) 3598 { 3599 struct adapter *sc = vi->pi->adapter; 3600 3601 if (vi->flags & VI_INIT_DONE) 3602 MPASS(nm_rxq->iq_cntxt_id == INVALID_NM_RXQ_CNTXT_ID); 3603 else 3604 MPASS(nm_rxq->iq_cntxt_id == 0); 3605 3606 free_ring(sc, nm_rxq->iq_desc_tag, nm_rxq->iq_desc_map, nm_rxq->iq_ba, 3607 nm_rxq->iq_desc); 3608 free_ring(sc, nm_rxq->fl_desc_tag, nm_rxq->fl_desc_map, nm_rxq->fl_ba, 3609 nm_rxq->fl_desc); 3610 3611 return (0); 3612 } 3613 3614 static int 3615 alloc_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq, int iqidx, int idx, 3616 struct sysctl_oid *oid) 3617 { 3618 int rc; 3619 size_t len; 3620 struct port_info *pi = vi->pi; 3621 struct adapter *sc = pi->adapter; 3622 struct netmap_adapter *na = NA(vi->ifp); 3623 char name[16]; 3624 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3625 3626 len = na->num_tx_desc * EQ_ESIZE + sc->params.sge.spg_len; 3627 rc = alloc_ring(sc, len, &nm_txq->desc_tag, &nm_txq->desc_map, 3628 &nm_txq->ba, (void **)&nm_txq->desc); 3629 if (rc) 3630 return (rc); 3631 3632 nm_txq->pidx = nm_txq->cidx = 0; 3633 nm_txq->sidx = na->num_tx_desc; 3634 nm_txq->nid = idx; 3635 nm_txq->iqidx = iqidx; 3636 nm_txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) | 3637 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(G_FW_VIID_PFN(vi->viid)) | 3638 V_TXPKT_VF(G_FW_VIID_VIN(vi->viid)) | 3639 V_TXPKT_VF_VLD(G_FW_VIID_VIVLD(vi->viid))); 3640 nm_txq->cntxt_id = INVALID_NM_TXQ_CNTXT_ID; 3641 3642 snprintf(name, sizeof(name), "%d", idx); 3643 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 3644 NULL, "netmap tx queue"); 3645 children = SYSCTL_CHILDREN(oid); 3646 3647 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 3648 &nm_txq->cntxt_id, 0, "SGE context id of the queue"); 3649 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx", 3650 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->cidx, 0, sysctl_uint16, "I", 3651 "consumer index"); 3652 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "pidx", 3653 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->pidx, 0, sysctl_uint16, "I", 3654 "producer index"); 3655 3656 return (rc); 3657 } 3658 3659 static int 3660 free_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq) 3661 { 3662 struct adapter *sc = vi->pi->adapter; 3663 3664 if (vi->flags & VI_INIT_DONE) 3665 MPASS(nm_txq->cntxt_id == INVALID_NM_TXQ_CNTXT_ID); 3666 else 3667 MPASS(nm_txq->cntxt_id == 0); 3668 3669 free_ring(sc, nm_txq->desc_tag, nm_txq->desc_map, nm_txq->ba, 3670 nm_txq->desc); 3671 3672 return (0); 3673 } 3674 #endif 3675 3676 /* 3677 * Returns a reasonable automatic cidx flush threshold for a given queue size. 3678 */ 3679 static u_int 3680 qsize_to_fthresh(int qsize) 3681 { 3682 u_int fthresh; 3683 3684 while (!powerof2(qsize)) 3685 qsize++; 3686 fthresh = ilog2(qsize); 3687 if (fthresh > X_CIDXFLUSHTHRESH_128) 3688 fthresh = X_CIDXFLUSHTHRESH_128; 3689 3690 return (fthresh); 3691 } 3692 3693 static int 3694 ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq) 3695 { 3696 int rc, cntxt_id; 3697 struct fw_eq_ctrl_cmd c; 3698 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 3699 3700 bzero(&c, sizeof(c)); 3701 3702 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | F_FW_CMD_REQUEST | 3703 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_CTRL_CMD_PFN(sc->pf) | 3704 V_FW_EQ_CTRL_CMD_VFN(0)); 3705 c.alloc_to_len16 = htobe32(F_FW_EQ_CTRL_CMD_ALLOC | 3706 F_FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c)); 3707 c.cmpliqid_eqid = htonl(V_FW_EQ_CTRL_CMD_CMPLIQID(eq->iqid)); 3708 c.physeqid_pkd = htobe32(0); 3709 c.fetchszm_to_iqid = 3710 htobe32(V_FW_EQ_CTRL_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 3711 V_FW_EQ_CTRL_CMD_PCIECHN(eq->tx_chan) | 3712 F_FW_EQ_CTRL_CMD_FETCHRO | V_FW_EQ_CTRL_CMD_IQID(eq->iqid)); 3713 c.dcaen_to_eqsize = 3714 htobe32(V_FW_EQ_CTRL_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 3715 V_FW_EQ_CTRL_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 3716 V_FW_EQ_CTRL_CMD_CIDXFTHRESH(qsize_to_fthresh(qsize)) | 3717 V_FW_EQ_CTRL_CMD_EQSIZE(qsize)); 3718 c.eqaddr = htobe64(eq->ba); 3719 3720 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3721 if (rc != 0) { 3722 device_printf(sc->dev, 3723 "failed to create control queue %d: %d\n", eq->tx_chan, rc); 3724 return (rc); 3725 } 3726 eq->flags |= EQ_ALLOCATED; 3727 3728 eq->cntxt_id = G_FW_EQ_CTRL_CMD_EQID(be32toh(c.cmpliqid_eqid)); 3729 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 3730 if (cntxt_id >= sc->sge.neq) 3731 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 3732 cntxt_id, sc->sge.neq - 1); 3733 sc->sge.eqmap[cntxt_id] = eq; 3734 3735 return (rc); 3736 } 3737 3738 static int 3739 eth_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 3740 { 3741 int rc, cntxt_id; 3742 struct fw_eq_eth_cmd c; 3743 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 3744 3745 bzero(&c, sizeof(c)); 3746 3747 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST | 3748 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) | 3749 V_FW_EQ_ETH_CMD_VFN(0)); 3750 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC | 3751 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c)); 3752 c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE | 3753 F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(vi->viid)); 3754 c.fetchszm_to_iqid = 3755 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) | 3756 V_FW_EQ_ETH_CMD_PCIECHN(eq->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO | 3757 V_FW_EQ_ETH_CMD_IQID(eq->iqid)); 3758 c.dcaen_to_eqsize = htobe32(V_FW_EQ_ETH_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 3759 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 3760 V_FW_EQ_ETH_CMD_EQSIZE(qsize)); 3761 c.eqaddr = htobe64(eq->ba); 3762 3763 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3764 if (rc != 0) { 3765 device_printf(vi->dev, 3766 "failed to create Ethernet egress queue: %d\n", rc); 3767 return (rc); 3768 } 3769 eq->flags |= EQ_ALLOCATED; 3770 3771 eq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd)); 3772 eq->abs_id = G_FW_EQ_ETH_CMD_PHYSEQID(be32toh(c.physeqid_pkd)); 3773 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 3774 if (cntxt_id >= sc->sge.neq) 3775 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 3776 cntxt_id, sc->sge.neq - 1); 3777 sc->sge.eqmap[cntxt_id] = eq; 3778 3779 return (rc); 3780 } 3781 3782 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 3783 static int 3784 ofld_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 3785 { 3786 int rc, cntxt_id; 3787 struct fw_eq_ofld_cmd c; 3788 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 3789 3790 bzero(&c, sizeof(c)); 3791 3792 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | F_FW_CMD_REQUEST | 3793 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_OFLD_CMD_PFN(sc->pf) | 3794 V_FW_EQ_OFLD_CMD_VFN(0)); 3795 c.alloc_to_len16 = htonl(F_FW_EQ_OFLD_CMD_ALLOC | 3796 F_FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c)); 3797 c.fetchszm_to_iqid = 3798 htonl(V_FW_EQ_OFLD_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 3799 V_FW_EQ_OFLD_CMD_PCIECHN(eq->tx_chan) | 3800 F_FW_EQ_OFLD_CMD_FETCHRO | V_FW_EQ_OFLD_CMD_IQID(eq->iqid)); 3801 c.dcaen_to_eqsize = 3802 htobe32(V_FW_EQ_OFLD_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 3803 V_FW_EQ_OFLD_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 3804 V_FW_EQ_OFLD_CMD_CIDXFTHRESH(qsize_to_fthresh(qsize)) | 3805 V_FW_EQ_OFLD_CMD_EQSIZE(qsize)); 3806 c.eqaddr = htobe64(eq->ba); 3807 3808 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3809 if (rc != 0) { 3810 device_printf(vi->dev, 3811 "failed to create egress queue for TCP offload: %d\n", rc); 3812 return (rc); 3813 } 3814 eq->flags |= EQ_ALLOCATED; 3815 3816 eq->cntxt_id = G_FW_EQ_OFLD_CMD_EQID(be32toh(c.eqid_pkd)); 3817 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 3818 if (cntxt_id >= sc->sge.neq) 3819 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 3820 cntxt_id, sc->sge.neq - 1); 3821 sc->sge.eqmap[cntxt_id] = eq; 3822 3823 return (rc); 3824 } 3825 #endif 3826 3827 static int 3828 alloc_eq(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 3829 { 3830 int rc, qsize; 3831 size_t len; 3832 3833 mtx_init(&eq->eq_lock, eq->lockname, NULL, MTX_DEF); 3834 3835 qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 3836 len = qsize * EQ_ESIZE; 3837 rc = alloc_ring(sc, len, &eq->desc_tag, &eq->desc_map, 3838 &eq->ba, (void **)&eq->desc); 3839 if (rc) 3840 return (rc); 3841 3842 eq->pidx = eq->cidx = eq->dbidx = 0; 3843 /* Note that equeqidx is not used with sge_wrq (OFLD/CTRL) queues. */ 3844 eq->equeqidx = 0; 3845 eq->doorbells = sc->doorbells; 3846 3847 switch (eq->flags & EQ_TYPEMASK) { 3848 case EQ_CTRL: 3849 rc = ctrl_eq_alloc(sc, eq); 3850 break; 3851 3852 case EQ_ETH: 3853 rc = eth_eq_alloc(sc, vi, eq); 3854 break; 3855 3856 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 3857 case EQ_OFLD: 3858 rc = ofld_eq_alloc(sc, vi, eq); 3859 break; 3860 #endif 3861 3862 default: 3863 panic("%s: invalid eq type %d.", __func__, 3864 eq->flags & EQ_TYPEMASK); 3865 } 3866 if (rc != 0) { 3867 device_printf(sc->dev, 3868 "failed to allocate egress queue(%d): %d\n", 3869 eq->flags & EQ_TYPEMASK, rc); 3870 } 3871 3872 if (isset(&eq->doorbells, DOORBELL_UDB) || 3873 isset(&eq->doorbells, DOORBELL_UDBWC) || 3874 isset(&eq->doorbells, DOORBELL_WCWR)) { 3875 uint32_t s_qpp = sc->params.sge.eq_s_qpp; 3876 uint32_t mask = (1 << s_qpp) - 1; 3877 volatile uint8_t *udb; 3878 3879 udb = sc->udbs_base + UDBS_DB_OFFSET; 3880 udb += (eq->cntxt_id >> s_qpp) << PAGE_SHIFT; /* pg offset */ 3881 eq->udb_qid = eq->cntxt_id & mask; /* id in page */ 3882 if (eq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE) 3883 clrbit(&eq->doorbells, DOORBELL_WCWR); 3884 else { 3885 udb += eq->udb_qid << UDBS_SEG_SHIFT; /* seg offset */ 3886 eq->udb_qid = 0; 3887 } 3888 eq->udb = (volatile void *)udb; 3889 } 3890 3891 return (rc); 3892 } 3893 3894 static int 3895 free_eq(struct adapter *sc, struct sge_eq *eq) 3896 { 3897 int rc; 3898 3899 if (eq->flags & EQ_ALLOCATED) { 3900 switch (eq->flags & EQ_TYPEMASK) { 3901 case EQ_CTRL: 3902 rc = -t4_ctrl_eq_free(sc, sc->mbox, sc->pf, 0, 3903 eq->cntxt_id); 3904 break; 3905 3906 case EQ_ETH: 3907 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0, 3908 eq->cntxt_id); 3909 break; 3910 3911 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 3912 case EQ_OFLD: 3913 rc = -t4_ofld_eq_free(sc, sc->mbox, sc->pf, 0, 3914 eq->cntxt_id); 3915 break; 3916 #endif 3917 3918 default: 3919 panic("%s: invalid eq type %d.", __func__, 3920 eq->flags & EQ_TYPEMASK); 3921 } 3922 if (rc != 0) { 3923 device_printf(sc->dev, 3924 "failed to free egress queue (%d): %d\n", 3925 eq->flags & EQ_TYPEMASK, rc); 3926 return (rc); 3927 } 3928 eq->flags &= ~EQ_ALLOCATED; 3929 } 3930 3931 free_ring(sc, eq->desc_tag, eq->desc_map, eq->ba, eq->desc); 3932 3933 if (mtx_initialized(&eq->eq_lock)) 3934 mtx_destroy(&eq->eq_lock); 3935 3936 bzero(eq, sizeof(*eq)); 3937 return (0); 3938 } 3939 3940 static int 3941 alloc_wrq(struct adapter *sc, struct vi_info *vi, struct sge_wrq *wrq, 3942 struct sysctl_oid *oid) 3943 { 3944 int rc; 3945 struct sysctl_ctx_list *ctx = vi ? &vi->ctx : &sc->ctx; 3946 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3947 3948 rc = alloc_eq(sc, vi, &wrq->eq); 3949 if (rc) 3950 return (rc); 3951 3952 wrq->adapter = sc; 3953 TASK_INIT(&wrq->wrq_tx_task, 0, wrq_tx_drain, wrq); 3954 TAILQ_INIT(&wrq->incomplete_wrs); 3955 STAILQ_INIT(&wrq->wr_list); 3956 wrq->nwr_pending = 0; 3957 wrq->ndesc_needed = 0; 3958 3959 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, 3960 &wrq->eq.ba, "bus address of descriptor ring"); 3961 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3962 wrq->eq.sidx * EQ_ESIZE + sc->params.sge.spg_len, 3963 "desc ring size in bytes"); 3964 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 3965 &wrq->eq.cntxt_id, 0, "SGE context id of the queue"); 3966 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx", 3967 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.cidx, 0, sysctl_uint16, "I", 3968 "consumer index"); 3969 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pidx", 3970 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.pidx, 0, sysctl_uint16, "I", 3971 "producer index"); 3972 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL, 3973 wrq->eq.sidx, "status page index"); 3974 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_direct", CTLFLAG_RD, 3975 &wrq->tx_wrs_direct, "# of work requests (direct)"); 3976 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_copied", CTLFLAG_RD, 3977 &wrq->tx_wrs_copied, "# of work requests (copied)"); 3978 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_sspace", CTLFLAG_RD, 3979 &wrq->tx_wrs_ss, "# of work requests (copied from scratch space)"); 3980 3981 return (rc); 3982 } 3983 3984 static int 3985 free_wrq(struct adapter *sc, struct sge_wrq *wrq) 3986 { 3987 int rc; 3988 3989 rc = free_eq(sc, &wrq->eq); 3990 if (rc) 3991 return (rc); 3992 3993 bzero(wrq, sizeof(*wrq)); 3994 return (0); 3995 } 3996 3997 static int 3998 alloc_txq(struct vi_info *vi, struct sge_txq *txq, int idx, 3999 struct sysctl_oid *oid) 4000 { 4001 int rc; 4002 struct port_info *pi = vi->pi; 4003 struct adapter *sc = pi->adapter; 4004 struct sge_eq *eq = &txq->eq; 4005 char name[16]; 4006 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 4007 4008 rc = mp_ring_alloc(&txq->r, eq->sidx, txq, eth_tx, can_resume_eth_tx, 4009 M_CXGBE, M_WAITOK); 4010 if (rc != 0) { 4011 device_printf(sc->dev, "failed to allocate mp_ring: %d\n", rc); 4012 return (rc); 4013 } 4014 4015 rc = alloc_eq(sc, vi, eq); 4016 if (rc != 0) { 4017 mp_ring_free(txq->r); 4018 txq->r = NULL; 4019 return (rc); 4020 } 4021 4022 /* Can't fail after this point. */ 4023 4024 if (idx == 0) 4025 sc->sge.eq_base = eq->abs_id - eq->cntxt_id; 4026 else 4027 KASSERT(eq->cntxt_id + sc->sge.eq_base == eq->abs_id, 4028 ("eq_base mismatch")); 4029 KASSERT(sc->sge.eq_base == 0 || sc->flags & IS_VF, 4030 ("PF with non-zero eq_base")); 4031 4032 TASK_INIT(&txq->tx_reclaim_task, 0, tx_reclaim, eq); 4033 txq->ifp = vi->ifp; 4034 txq->gl = sglist_alloc(TX_SGL_SEGS, M_WAITOK); 4035 if (sc->flags & IS_VF) 4036 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) | 4037 V_TXPKT_INTF(pi->tx_chan)); 4038 else 4039 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) | 4040 V_TXPKT_INTF(pi->tx_chan) | 4041 V_TXPKT_PF(G_FW_VIID_PFN(vi->viid)) | 4042 V_TXPKT_VF(G_FW_VIID_VIN(vi->viid)) | 4043 V_TXPKT_VF_VLD(G_FW_VIID_VIVLD(vi->viid))); 4044 txq->tc_idx = -1; 4045 txq->sdesc = malloc(eq->sidx * sizeof(struct tx_sdesc), M_CXGBE, 4046 M_ZERO | M_WAITOK); 4047 4048 snprintf(name, sizeof(name), "%d", idx); 4049 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 4050 NULL, "tx queue"); 4051 children = SYSCTL_CHILDREN(oid); 4052 4053 SYSCTL_ADD_UAUTO(&vi->ctx, children, OID_AUTO, "ba", CTLFLAG_RD, 4054 &eq->ba, "bus address of descriptor ring"); 4055 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 4056 eq->sidx * EQ_ESIZE + sc->params.sge.spg_len, 4057 "desc ring size in bytes"); 4058 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "abs_id", CTLFLAG_RD, 4059 &eq->abs_id, 0, "absolute id of the queue"); 4060 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 4061 &eq->cntxt_id, 0, "SGE context id of the queue"); 4062 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx", 4063 CTLTYPE_INT | CTLFLAG_RD, &eq->cidx, 0, sysctl_uint16, "I", 4064 "consumer index"); 4065 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "pidx", 4066 CTLTYPE_INT | CTLFLAG_RD, &eq->pidx, 0, sysctl_uint16, "I", 4067 "producer index"); 4068 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL, 4069 eq->sidx, "status page index"); 4070 4071 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "tc", 4072 CTLTYPE_INT | CTLFLAG_RW, vi, idx, sysctl_tc, "I", 4073 "traffic class (-1 means none)"); 4074 4075 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txcsum", CTLFLAG_RD, 4076 &txq->txcsum, "# of times hardware assisted with checksum"); 4077 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_insertion", 4078 CTLFLAG_RD, &txq->vlan_insertion, 4079 "# of times hardware inserted 802.1Q tag"); 4080 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "tso_wrs", CTLFLAG_RD, 4081 &txq->tso_wrs, "# of TSO work requests"); 4082 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "imm_wrs", CTLFLAG_RD, 4083 &txq->imm_wrs, "# of work requests with immediate data"); 4084 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "sgl_wrs", CTLFLAG_RD, 4085 &txq->sgl_wrs, "# of work requests with direct SGL"); 4086 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkt_wrs", CTLFLAG_RD, 4087 &txq->txpkt_wrs, "# of txpkt work requests (one pkt/WR)"); 4088 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_wrs", 4089 CTLFLAG_RD, &txq->txpkts0_wrs, 4090 "# of txpkts (type 0) work requests"); 4091 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_wrs", 4092 CTLFLAG_RD, &txq->txpkts1_wrs, 4093 "# of txpkts (type 1) work requests"); 4094 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_pkts", 4095 CTLFLAG_RD, &txq->txpkts0_pkts, 4096 "# of frames tx'd using type0 txpkts work requests"); 4097 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_pkts", 4098 CTLFLAG_RD, &txq->txpkts1_pkts, 4099 "# of frames tx'd using type1 txpkts work requests"); 4100 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "raw_wrs", CTLFLAG_RD, 4101 &txq->raw_wrs, "# of raw work requests (non-packets)"); 4102 4103 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_enqueues", 4104 CTLFLAG_RD, &txq->r->enqueues, 4105 "# of enqueues to the mp_ring for this queue"); 4106 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_drops", 4107 CTLFLAG_RD, &txq->r->drops, 4108 "# of drops in the mp_ring for this queue"); 4109 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_starts", 4110 CTLFLAG_RD, &txq->r->starts, 4111 "# of normal consumer starts in the mp_ring for this queue"); 4112 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_stalls", 4113 CTLFLAG_RD, &txq->r->stalls, 4114 "# of consumer stalls in the mp_ring for this queue"); 4115 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_restarts", 4116 CTLFLAG_RD, &txq->r->restarts, 4117 "# of consumer restarts in the mp_ring for this queue"); 4118 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_abdications", 4119 CTLFLAG_RD, &txq->r->abdications, 4120 "# of consumer abdications in the mp_ring for this queue"); 4121 4122 return (0); 4123 } 4124 4125 static int 4126 free_txq(struct vi_info *vi, struct sge_txq *txq) 4127 { 4128 int rc; 4129 struct adapter *sc = vi->pi->adapter; 4130 struct sge_eq *eq = &txq->eq; 4131 4132 rc = free_eq(sc, eq); 4133 if (rc) 4134 return (rc); 4135 4136 sglist_free(txq->gl); 4137 free(txq->sdesc, M_CXGBE); 4138 mp_ring_free(txq->r); 4139 4140 bzero(txq, sizeof(*txq)); 4141 return (0); 4142 } 4143 4144 static void 4145 oneseg_dma_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error) 4146 { 4147 bus_addr_t *ba = arg; 4148 4149 KASSERT(nseg == 1, 4150 ("%s meant for single segment mappings only.", __func__)); 4151 4152 *ba = error ? 0 : segs->ds_addr; 4153 } 4154 4155 static inline void 4156 ring_fl_db(struct adapter *sc, struct sge_fl *fl) 4157 { 4158 uint32_t n, v; 4159 4160 n = IDXDIFF(fl->pidx / 8, fl->dbidx, fl->sidx); 4161 MPASS(n > 0); 4162 4163 wmb(); 4164 v = fl->dbval | V_PIDX(n); 4165 if (fl->udb) 4166 *fl->udb = htole32(v); 4167 else 4168 t4_write_reg(sc, sc->sge_kdoorbell_reg, v); 4169 IDXINCR(fl->dbidx, n, fl->sidx); 4170 } 4171 4172 /* 4173 * Fills up the freelist by allocating up to 'n' buffers. Buffers that are 4174 * recycled do not count towards this allocation budget. 4175 * 4176 * Returns non-zero to indicate that this freelist should be added to the list 4177 * of starving freelists. 4178 */ 4179 static int 4180 refill_fl(struct adapter *sc, struct sge_fl *fl, int n) 4181 { 4182 __be64 *d; 4183 struct fl_sdesc *sd; 4184 uintptr_t pa; 4185 caddr_t cl; 4186 struct cluster_layout *cll; 4187 struct sw_zone_info *swz; 4188 struct cluster_metadata *clm; 4189 uint16_t max_pidx; 4190 uint16_t hw_cidx = fl->hw_cidx; /* stable snapshot */ 4191 4192 FL_LOCK_ASSERT_OWNED(fl); 4193 4194 /* 4195 * We always stop at the beginning of the hardware descriptor that's just 4196 * before the one with the hw cidx. This is to avoid hw pidx = hw cidx, 4197 * which would mean an empty freelist to the chip. 4198 */ 4199 max_pidx = __predict_false(hw_cidx == 0) ? fl->sidx - 1 : hw_cidx - 1; 4200 if (fl->pidx == max_pidx * 8) 4201 return (0); 4202 4203 d = &fl->desc[fl->pidx]; 4204 sd = &fl->sdesc[fl->pidx]; 4205 cll = &fl->cll_def; /* default layout */ 4206 swz = &sc->sge.sw_zone_info[cll->zidx]; 4207 4208 while (n > 0) { 4209 4210 if (sd->cl != NULL) { 4211 4212 if (sd->nmbuf == 0) { 4213 /* 4214 * Fast recycle without involving any atomics on 4215 * the cluster's metadata (if the cluster has 4216 * metadata). This happens when all frames 4217 * received in the cluster were small enough to 4218 * fit within a single mbuf each. 4219 */ 4220 fl->cl_fast_recycled++; 4221 #ifdef INVARIANTS 4222 clm = cl_metadata(sc, fl, &sd->cll, sd->cl); 4223 if (clm != NULL) 4224 MPASS(clm->refcount == 1); 4225 #endif 4226 goto recycled_fast; 4227 } 4228 4229 /* 4230 * Cluster is guaranteed to have metadata. Clusters 4231 * without metadata always take the fast recycle path 4232 * when they're recycled. 4233 */ 4234 clm = cl_metadata(sc, fl, &sd->cll, sd->cl); 4235 MPASS(clm != NULL); 4236 4237 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) { 4238 fl->cl_recycled++; 4239 counter_u64_add(extfree_rels, 1); 4240 goto recycled; 4241 } 4242 sd->cl = NULL; /* gave up my reference */ 4243 } 4244 MPASS(sd->cl == NULL); 4245 alloc: 4246 cl = uma_zalloc(swz->zone, M_NOWAIT); 4247 if (__predict_false(cl == NULL)) { 4248 if (cll == &fl->cll_alt || fl->cll_alt.zidx == -1 || 4249 fl->cll_def.zidx == fl->cll_alt.zidx) 4250 break; 4251 4252 /* fall back to the safe zone */ 4253 cll = &fl->cll_alt; 4254 swz = &sc->sge.sw_zone_info[cll->zidx]; 4255 goto alloc; 4256 } 4257 fl->cl_allocated++; 4258 n--; 4259 4260 pa = pmap_kextract((vm_offset_t)cl); 4261 pa += cll->region1; 4262 sd->cl = cl; 4263 sd->cll = *cll; 4264 *d = htobe64(pa | cll->hwidx); 4265 clm = cl_metadata(sc, fl, cll, cl); 4266 if (clm != NULL) { 4267 recycled: 4268 #ifdef INVARIANTS 4269 clm->sd = sd; 4270 #endif 4271 clm->refcount = 1; 4272 } 4273 sd->nmbuf = 0; 4274 recycled_fast: 4275 d++; 4276 sd++; 4277 if (__predict_false(++fl->pidx % 8 == 0)) { 4278 uint16_t pidx = fl->pidx / 8; 4279 4280 if (__predict_false(pidx == fl->sidx)) { 4281 fl->pidx = 0; 4282 pidx = 0; 4283 sd = fl->sdesc; 4284 d = fl->desc; 4285 } 4286 if (pidx == max_pidx) 4287 break; 4288 4289 if (IDXDIFF(pidx, fl->dbidx, fl->sidx) >= 4) 4290 ring_fl_db(sc, fl); 4291 } 4292 } 4293 4294 if (fl->pidx / 8 != fl->dbidx) 4295 ring_fl_db(sc, fl); 4296 4297 return (FL_RUNNING_LOW(fl) && !(fl->flags & FL_STARVING)); 4298 } 4299 4300 /* 4301 * Attempt to refill all starving freelists. 4302 */ 4303 static void 4304 refill_sfl(void *arg) 4305 { 4306 struct adapter *sc = arg; 4307 struct sge_fl *fl, *fl_temp; 4308 4309 mtx_assert(&sc->sfl_lock, MA_OWNED); 4310 TAILQ_FOREACH_SAFE(fl, &sc->sfl, link, fl_temp) { 4311 FL_LOCK(fl); 4312 refill_fl(sc, fl, 64); 4313 if (FL_NOT_RUNNING_LOW(fl) || fl->flags & FL_DOOMED) { 4314 TAILQ_REMOVE(&sc->sfl, fl, link); 4315 fl->flags &= ~FL_STARVING; 4316 } 4317 FL_UNLOCK(fl); 4318 } 4319 4320 if (!TAILQ_EMPTY(&sc->sfl)) 4321 callout_schedule(&sc->sfl_callout, hz / 5); 4322 } 4323 4324 static int 4325 alloc_fl_sdesc(struct sge_fl *fl) 4326 { 4327 4328 fl->sdesc = malloc(fl->sidx * 8 * sizeof(struct fl_sdesc), M_CXGBE, 4329 M_ZERO | M_WAITOK); 4330 4331 return (0); 4332 } 4333 4334 static void 4335 free_fl_sdesc(struct adapter *sc, struct sge_fl *fl) 4336 { 4337 struct fl_sdesc *sd; 4338 struct cluster_metadata *clm; 4339 struct cluster_layout *cll; 4340 int i; 4341 4342 sd = fl->sdesc; 4343 for (i = 0; i < fl->sidx * 8; i++, sd++) { 4344 if (sd->cl == NULL) 4345 continue; 4346 4347 cll = &sd->cll; 4348 clm = cl_metadata(sc, fl, cll, sd->cl); 4349 if (sd->nmbuf == 0) 4350 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl); 4351 else if (clm && atomic_fetchadd_int(&clm->refcount, -1) == 1) { 4352 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl); 4353 counter_u64_add(extfree_rels, 1); 4354 } 4355 sd->cl = NULL; 4356 } 4357 4358 free(fl->sdesc, M_CXGBE); 4359 fl->sdesc = NULL; 4360 } 4361 4362 static inline void 4363 get_pkt_gl(struct mbuf *m, struct sglist *gl) 4364 { 4365 int rc; 4366 4367 M_ASSERTPKTHDR(m); 4368 4369 sglist_reset(gl); 4370 rc = sglist_append_mbuf(gl, m); 4371 if (__predict_false(rc != 0)) { 4372 panic("%s: mbuf %p (%d segs) was vetted earlier but now fails " 4373 "with %d.", __func__, m, mbuf_nsegs(m), rc); 4374 } 4375 4376 KASSERT(gl->sg_nseg == mbuf_nsegs(m), 4377 ("%s: nsegs changed for mbuf %p from %d to %d", __func__, m, 4378 mbuf_nsegs(m), gl->sg_nseg)); 4379 KASSERT(gl->sg_nseg > 0 && 4380 gl->sg_nseg <= (needs_tso(m) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS), 4381 ("%s: %d segments, should have been 1 <= nsegs <= %d", __func__, 4382 gl->sg_nseg, needs_tso(m) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS)); 4383 } 4384 4385 /* 4386 * len16 for a txpkt WR with a GL. Includes the firmware work request header. 4387 */ 4388 static inline u_int 4389 txpkt_len16(u_int nsegs, u_int tso) 4390 { 4391 u_int n; 4392 4393 MPASS(nsegs > 0); 4394 4395 nsegs--; /* first segment is part of ulptx_sgl */ 4396 n = sizeof(struct fw_eth_tx_pkt_wr) + sizeof(struct cpl_tx_pkt_core) + 4397 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 4398 if (tso) 4399 n += sizeof(struct cpl_tx_pkt_lso_core); 4400 4401 return (howmany(n, 16)); 4402 } 4403 4404 /* 4405 * len16 for a txpkt_vm WR with a GL. Includes the firmware work 4406 * request header. 4407 */ 4408 static inline u_int 4409 txpkt_vm_len16(u_int nsegs, u_int tso) 4410 { 4411 u_int n; 4412 4413 MPASS(nsegs > 0); 4414 4415 nsegs--; /* first segment is part of ulptx_sgl */ 4416 n = sizeof(struct fw_eth_tx_pkt_vm_wr) + 4417 sizeof(struct cpl_tx_pkt_core) + 4418 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 4419 if (tso) 4420 n += sizeof(struct cpl_tx_pkt_lso_core); 4421 4422 return (howmany(n, 16)); 4423 } 4424 4425 /* 4426 * len16 for a txpkts type 0 WR with a GL. Does not include the firmware work 4427 * request header. 4428 */ 4429 static inline u_int 4430 txpkts0_len16(u_int nsegs) 4431 { 4432 u_int n; 4433 4434 MPASS(nsegs > 0); 4435 4436 nsegs--; /* first segment is part of ulptx_sgl */ 4437 n = sizeof(struct ulp_txpkt) + sizeof(struct ulptx_idata) + 4438 sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl) + 4439 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 4440 4441 return (howmany(n, 16)); 4442 } 4443 4444 /* 4445 * len16 for a txpkts type 1 WR with a GL. Does not include the firmware work 4446 * request header. 4447 */ 4448 static inline u_int 4449 txpkts1_len16(void) 4450 { 4451 u_int n; 4452 4453 n = sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl); 4454 4455 return (howmany(n, 16)); 4456 } 4457 4458 static inline u_int 4459 imm_payload(u_int ndesc) 4460 { 4461 u_int n; 4462 4463 n = ndesc * EQ_ESIZE - sizeof(struct fw_eth_tx_pkt_wr) - 4464 sizeof(struct cpl_tx_pkt_core); 4465 4466 return (n); 4467 } 4468 4469 /* 4470 * Write a VM txpkt WR for this packet to the hardware descriptors, update the 4471 * software descriptor, and advance the pidx. It is guaranteed that enough 4472 * descriptors are available. 4473 * 4474 * The return value is the # of hardware descriptors used. 4475 */ 4476 static u_int 4477 write_txpkt_vm_wr(struct adapter *sc, struct sge_txq *txq, 4478 struct fw_eth_tx_pkt_vm_wr *wr, struct mbuf *m0, u_int available) 4479 { 4480 struct sge_eq *eq = &txq->eq; 4481 struct tx_sdesc *txsd; 4482 struct cpl_tx_pkt_core *cpl; 4483 uint32_t ctrl; /* used in many unrelated places */ 4484 uint64_t ctrl1; 4485 int csum_type, len16, ndesc, pktlen, nsegs; 4486 caddr_t dst; 4487 4488 TXQ_LOCK_ASSERT_OWNED(txq); 4489 M_ASSERTPKTHDR(m0); 4490 MPASS(available > 0 && available < eq->sidx); 4491 4492 len16 = mbuf_len16(m0); 4493 nsegs = mbuf_nsegs(m0); 4494 pktlen = m0->m_pkthdr.len; 4495 ctrl = sizeof(struct cpl_tx_pkt_core); 4496 if (needs_tso(m0)) 4497 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 4498 ndesc = howmany(len16, EQ_ESIZE / 16); 4499 MPASS(ndesc <= available); 4500 4501 /* Firmware work request header */ 4502 MPASS(wr == (void *)&eq->desc[eq->pidx]); 4503 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_VM_WR) | 4504 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl)); 4505 4506 ctrl = V_FW_WR_LEN16(len16); 4507 wr->equiq_to_len16 = htobe32(ctrl); 4508 wr->r3[0] = 0; 4509 wr->r3[1] = 0; 4510 4511 /* 4512 * Copy over ethmacdst, ethmacsrc, ethtype, and vlantci. 4513 * vlantci is ignored unless the ethtype is 0x8100, so it's 4514 * simpler to always copy it rather than making it 4515 * conditional. Also, it seems that we do not have to set 4516 * vlantci or fake the ethtype when doing VLAN tag insertion. 4517 */ 4518 m_copydata(m0, 0, sizeof(struct ether_header) + 2, wr->ethmacdst); 4519 4520 csum_type = -1; 4521 if (needs_tso(m0)) { 4522 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1); 4523 4524 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 4525 m0->m_pkthdr.l4hlen > 0, 4526 ("%s: mbuf %p needs TSO but missing header lengths", 4527 __func__, m0)); 4528 4529 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE | 4530 F_LSO_LAST_SLICE | V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) 4531 | V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2); 4532 if (m0->m_pkthdr.l2hlen == sizeof(struct ether_vlan_header)) 4533 ctrl |= V_LSO_ETHHDR_LEN(1); 4534 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 4535 ctrl |= F_LSO_IPV6; 4536 4537 lso->lso_ctrl = htobe32(ctrl); 4538 lso->ipid_ofst = htobe16(0); 4539 lso->mss = htobe16(m0->m_pkthdr.tso_segsz); 4540 lso->seqno_offset = htobe32(0); 4541 lso->len = htobe32(pktlen); 4542 4543 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 4544 csum_type = TX_CSUM_TCPIP6; 4545 else 4546 csum_type = TX_CSUM_TCPIP; 4547 4548 cpl = (void *)(lso + 1); 4549 4550 txq->tso_wrs++; 4551 } else { 4552 if (m0->m_pkthdr.csum_flags & CSUM_IP_TCP) 4553 csum_type = TX_CSUM_TCPIP; 4554 else if (m0->m_pkthdr.csum_flags & CSUM_IP_UDP) 4555 csum_type = TX_CSUM_UDPIP; 4556 else if (m0->m_pkthdr.csum_flags & CSUM_IP6_TCP) 4557 csum_type = TX_CSUM_TCPIP6; 4558 else if (m0->m_pkthdr.csum_flags & CSUM_IP6_UDP) 4559 csum_type = TX_CSUM_UDPIP6; 4560 #if defined(INET) 4561 else if (m0->m_pkthdr.csum_flags & CSUM_IP) { 4562 /* 4563 * XXX: The firmware appears to stomp on the 4564 * fragment/flags field of the IP header when 4565 * using TX_CSUM_IP. Fall back to doing 4566 * software checksums. 4567 */ 4568 u_short *sump; 4569 struct mbuf *m; 4570 int offset; 4571 4572 m = m0; 4573 offset = 0; 4574 sump = m_advance(&m, &offset, m0->m_pkthdr.l2hlen + 4575 offsetof(struct ip, ip_sum)); 4576 *sump = in_cksum_skip(m0, m0->m_pkthdr.l2hlen + 4577 m0->m_pkthdr.l3hlen, m0->m_pkthdr.l2hlen); 4578 m0->m_pkthdr.csum_flags &= ~CSUM_IP; 4579 } 4580 #endif 4581 4582 cpl = (void *)(wr + 1); 4583 } 4584 4585 /* Checksum offload */ 4586 ctrl1 = 0; 4587 if (needs_l3_csum(m0) == 0) 4588 ctrl1 |= F_TXPKT_IPCSUM_DIS; 4589 if (csum_type >= 0) { 4590 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0, 4591 ("%s: mbuf %p needs checksum offload but missing header lengths", 4592 __func__, m0)); 4593 4594 if (chip_id(sc) <= CHELSIO_T5) { 4595 ctrl1 |= V_TXPKT_ETHHDR_LEN(m0->m_pkthdr.l2hlen - 4596 ETHER_HDR_LEN); 4597 } else { 4598 ctrl1 |= V_T6_TXPKT_ETHHDR_LEN(m0->m_pkthdr.l2hlen - 4599 ETHER_HDR_LEN); 4600 } 4601 ctrl1 |= V_TXPKT_IPHDR_LEN(m0->m_pkthdr.l3hlen); 4602 ctrl1 |= V_TXPKT_CSUM_TYPE(csum_type); 4603 } else 4604 ctrl1 |= F_TXPKT_L4CSUM_DIS; 4605 if (m0->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | 4606 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO)) 4607 txq->txcsum++; /* some hardware assistance provided */ 4608 4609 /* VLAN tag insertion */ 4610 if (needs_vlan_insertion(m0)) { 4611 ctrl1 |= F_TXPKT_VLAN_VLD | 4612 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 4613 txq->vlan_insertion++; 4614 } 4615 4616 /* CPL header */ 4617 cpl->ctrl0 = txq->cpl_ctrl0; 4618 cpl->pack = 0; 4619 cpl->len = htobe16(pktlen); 4620 cpl->ctrl1 = htobe64(ctrl1); 4621 4622 /* SGL */ 4623 dst = (void *)(cpl + 1); 4624 4625 /* 4626 * A packet using TSO will use up an entire descriptor for the 4627 * firmware work request header, LSO CPL, and TX_PKT_XT CPL. 4628 * If this descriptor is the last descriptor in the ring, wrap 4629 * around to the front of the ring explicitly for the start of 4630 * the sgl. 4631 */ 4632 if (dst == (void *)&eq->desc[eq->sidx]) { 4633 dst = (void *)&eq->desc[0]; 4634 write_gl_to_txd(txq, m0, &dst, 0); 4635 } else 4636 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx); 4637 txq->sgl_wrs++; 4638 4639 txq->txpkt_wrs++; 4640 4641 txsd = &txq->sdesc[eq->pidx]; 4642 txsd->m = m0; 4643 txsd->desc_used = ndesc; 4644 4645 return (ndesc); 4646 } 4647 4648 /* 4649 * Write a raw WR to the hardware descriptors, update the software 4650 * descriptor, and advance the pidx. It is guaranteed that enough 4651 * descriptors are available. 4652 * 4653 * The return value is the # of hardware descriptors used. 4654 */ 4655 static u_int 4656 write_raw_wr(struct sge_txq *txq, void *wr, struct mbuf *m0, u_int available) 4657 { 4658 struct sge_eq *eq = &txq->eq; 4659 struct tx_sdesc *txsd; 4660 struct mbuf *m; 4661 caddr_t dst; 4662 int len16, ndesc; 4663 4664 len16 = mbuf_len16(m0); 4665 ndesc = howmany(len16, EQ_ESIZE / 16); 4666 MPASS(ndesc <= available); 4667 4668 dst = wr; 4669 for (m = m0; m != NULL; m = m->m_next) 4670 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len); 4671 4672 txq->raw_wrs++; 4673 4674 txsd = &txq->sdesc[eq->pidx]; 4675 txsd->m = m0; 4676 txsd->desc_used = ndesc; 4677 4678 return (ndesc); 4679 } 4680 4681 /* 4682 * Write a txpkt WR for this packet to the hardware descriptors, update the 4683 * software descriptor, and advance the pidx. It is guaranteed that enough 4684 * descriptors are available. 4685 * 4686 * The return value is the # of hardware descriptors used. 4687 */ 4688 static u_int 4689 write_txpkt_wr(struct sge_txq *txq, struct fw_eth_tx_pkt_wr *wr, 4690 struct mbuf *m0, u_int available) 4691 { 4692 struct sge_eq *eq = &txq->eq; 4693 struct tx_sdesc *txsd; 4694 struct cpl_tx_pkt_core *cpl; 4695 uint32_t ctrl; /* used in many unrelated places */ 4696 uint64_t ctrl1; 4697 int len16, ndesc, pktlen, nsegs; 4698 caddr_t dst; 4699 4700 TXQ_LOCK_ASSERT_OWNED(txq); 4701 M_ASSERTPKTHDR(m0); 4702 MPASS(available > 0 && available < eq->sidx); 4703 4704 len16 = mbuf_len16(m0); 4705 nsegs = mbuf_nsegs(m0); 4706 pktlen = m0->m_pkthdr.len; 4707 ctrl = sizeof(struct cpl_tx_pkt_core); 4708 if (needs_tso(m0)) 4709 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 4710 else if (pktlen <= imm_payload(2) && available >= 2) { 4711 /* Immediate data. Recalculate len16 and set nsegs to 0. */ 4712 ctrl += pktlen; 4713 len16 = howmany(sizeof(struct fw_eth_tx_pkt_wr) + 4714 sizeof(struct cpl_tx_pkt_core) + pktlen, 16); 4715 nsegs = 0; 4716 } 4717 ndesc = howmany(len16, EQ_ESIZE / 16); 4718 MPASS(ndesc <= available); 4719 4720 /* Firmware work request header */ 4721 MPASS(wr == (void *)&eq->desc[eq->pidx]); 4722 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_WR) | 4723 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl)); 4724 4725 ctrl = V_FW_WR_LEN16(len16); 4726 wr->equiq_to_len16 = htobe32(ctrl); 4727 wr->r3 = 0; 4728 4729 if (needs_tso(m0)) { 4730 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1); 4731 4732 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 4733 m0->m_pkthdr.l4hlen > 0, 4734 ("%s: mbuf %p needs TSO but missing header lengths", 4735 __func__, m0)); 4736 4737 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE | 4738 F_LSO_LAST_SLICE | V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) 4739 | V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2); 4740 if (m0->m_pkthdr.l2hlen == sizeof(struct ether_vlan_header)) 4741 ctrl |= V_LSO_ETHHDR_LEN(1); 4742 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 4743 ctrl |= F_LSO_IPV6; 4744 4745 lso->lso_ctrl = htobe32(ctrl); 4746 lso->ipid_ofst = htobe16(0); 4747 lso->mss = htobe16(m0->m_pkthdr.tso_segsz); 4748 lso->seqno_offset = htobe32(0); 4749 lso->len = htobe32(pktlen); 4750 4751 cpl = (void *)(lso + 1); 4752 4753 txq->tso_wrs++; 4754 } else 4755 cpl = (void *)(wr + 1); 4756 4757 /* Checksum offload */ 4758 ctrl1 = 0; 4759 if (needs_l3_csum(m0) == 0) 4760 ctrl1 |= F_TXPKT_IPCSUM_DIS; 4761 if (needs_l4_csum(m0) == 0) 4762 ctrl1 |= F_TXPKT_L4CSUM_DIS; 4763 if (m0->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | 4764 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO)) 4765 txq->txcsum++; /* some hardware assistance provided */ 4766 4767 /* VLAN tag insertion */ 4768 if (needs_vlan_insertion(m0)) { 4769 ctrl1 |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 4770 txq->vlan_insertion++; 4771 } 4772 4773 /* CPL header */ 4774 cpl->ctrl0 = txq->cpl_ctrl0; 4775 cpl->pack = 0; 4776 cpl->len = htobe16(pktlen); 4777 cpl->ctrl1 = htobe64(ctrl1); 4778 4779 /* SGL */ 4780 dst = (void *)(cpl + 1); 4781 if (nsegs > 0) { 4782 4783 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx); 4784 txq->sgl_wrs++; 4785 } else { 4786 struct mbuf *m; 4787 4788 for (m = m0; m != NULL; m = m->m_next) { 4789 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len); 4790 #ifdef INVARIANTS 4791 pktlen -= m->m_len; 4792 #endif 4793 } 4794 #ifdef INVARIANTS 4795 KASSERT(pktlen == 0, ("%s: %d bytes left.", __func__, pktlen)); 4796 #endif 4797 txq->imm_wrs++; 4798 } 4799 4800 txq->txpkt_wrs++; 4801 4802 txsd = &txq->sdesc[eq->pidx]; 4803 txsd->m = m0; 4804 txsd->desc_used = ndesc; 4805 4806 return (ndesc); 4807 } 4808 4809 static int 4810 try_txpkts(struct mbuf *m, struct mbuf *n, struct txpkts *txp, u_int available) 4811 { 4812 u_int needed, nsegs1, nsegs2, l1, l2; 4813 4814 if (cannot_use_txpkts(m) || cannot_use_txpkts(n)) 4815 return (1); 4816 4817 nsegs1 = mbuf_nsegs(m); 4818 nsegs2 = mbuf_nsegs(n); 4819 if (nsegs1 + nsegs2 == 2) { 4820 txp->wr_type = 1; 4821 l1 = l2 = txpkts1_len16(); 4822 } else { 4823 txp->wr_type = 0; 4824 l1 = txpkts0_len16(nsegs1); 4825 l2 = txpkts0_len16(nsegs2); 4826 } 4827 txp->len16 = howmany(sizeof(struct fw_eth_tx_pkts_wr), 16) + l1 + l2; 4828 needed = howmany(txp->len16, EQ_ESIZE / 16); 4829 if (needed > SGE_MAX_WR_NDESC || needed > available) 4830 return (1); 4831 4832 txp->plen = m->m_pkthdr.len + n->m_pkthdr.len; 4833 if (txp->plen > 65535) 4834 return (1); 4835 4836 txp->npkt = 2; 4837 set_mbuf_len16(m, l1); 4838 set_mbuf_len16(n, l2); 4839 4840 return (0); 4841 } 4842 4843 static int 4844 add_to_txpkts(struct mbuf *m, struct txpkts *txp, u_int available) 4845 { 4846 u_int plen, len16, needed, nsegs; 4847 4848 MPASS(txp->wr_type == 0 || txp->wr_type == 1); 4849 4850 if (cannot_use_txpkts(m)) 4851 return (1); 4852 4853 nsegs = mbuf_nsegs(m); 4854 if (txp->wr_type == 1 && nsegs != 1) 4855 return (1); 4856 4857 plen = txp->plen + m->m_pkthdr.len; 4858 if (plen > 65535) 4859 return (1); 4860 4861 if (txp->wr_type == 0) 4862 len16 = txpkts0_len16(nsegs); 4863 else 4864 len16 = txpkts1_len16(); 4865 needed = howmany(txp->len16 + len16, EQ_ESIZE / 16); 4866 if (needed > SGE_MAX_WR_NDESC || needed > available) 4867 return (1); 4868 4869 txp->npkt++; 4870 txp->plen = plen; 4871 txp->len16 += len16; 4872 set_mbuf_len16(m, len16); 4873 4874 return (0); 4875 } 4876 4877 /* 4878 * Write a txpkts WR for the packets in txp to the hardware descriptors, update 4879 * the software descriptor, and advance the pidx. It is guaranteed that enough 4880 * descriptors are available. 4881 * 4882 * The return value is the # of hardware descriptors used. 4883 */ 4884 static u_int 4885 write_txpkts_wr(struct sge_txq *txq, struct fw_eth_tx_pkts_wr *wr, 4886 struct mbuf *m0, const struct txpkts *txp, u_int available) 4887 { 4888 struct sge_eq *eq = &txq->eq; 4889 struct tx_sdesc *txsd; 4890 struct cpl_tx_pkt_core *cpl; 4891 uint32_t ctrl; 4892 uint64_t ctrl1; 4893 int ndesc, checkwrap; 4894 struct mbuf *m; 4895 void *flitp; 4896 4897 TXQ_LOCK_ASSERT_OWNED(txq); 4898 MPASS(txp->npkt > 0); 4899 MPASS(txp->plen < 65536); 4900 MPASS(m0 != NULL); 4901 MPASS(m0->m_nextpkt != NULL); 4902 MPASS(txp->len16 <= howmany(SGE_MAX_WR_LEN, 16)); 4903 MPASS(available > 0 && available < eq->sidx); 4904 4905 ndesc = howmany(txp->len16, EQ_ESIZE / 16); 4906 MPASS(ndesc <= available); 4907 4908 MPASS(wr == (void *)&eq->desc[eq->pidx]); 4909 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR)); 4910 ctrl = V_FW_WR_LEN16(txp->len16); 4911 wr->equiq_to_len16 = htobe32(ctrl); 4912 wr->plen = htobe16(txp->plen); 4913 wr->npkt = txp->npkt; 4914 wr->r3 = 0; 4915 wr->type = txp->wr_type; 4916 flitp = wr + 1; 4917 4918 /* 4919 * At this point we are 16B into a hardware descriptor. If checkwrap is 4920 * set then we know the WR is going to wrap around somewhere. We'll 4921 * check for that at appropriate points. 4922 */ 4923 checkwrap = eq->sidx - ndesc < eq->pidx; 4924 for (m = m0; m != NULL; m = m->m_nextpkt) { 4925 if (txp->wr_type == 0) { 4926 struct ulp_txpkt *ulpmc; 4927 struct ulptx_idata *ulpsc; 4928 4929 /* ULP master command */ 4930 ulpmc = flitp; 4931 ulpmc->cmd_dest = htobe32(V_ULPTX_CMD(ULP_TX_PKT) | 4932 V_ULP_TXPKT_DEST(0) | V_ULP_TXPKT_FID(eq->iqid)); 4933 ulpmc->len = htobe32(mbuf_len16(m)); 4934 4935 /* ULP subcommand */ 4936 ulpsc = (void *)(ulpmc + 1); 4937 ulpsc->cmd_more = htobe32(V_ULPTX_CMD(ULP_TX_SC_IMM) | 4938 F_ULP_TX_SC_MORE); 4939 ulpsc->len = htobe32(sizeof(struct cpl_tx_pkt_core)); 4940 4941 cpl = (void *)(ulpsc + 1); 4942 if (checkwrap && 4943 (uintptr_t)cpl == (uintptr_t)&eq->desc[eq->sidx]) 4944 cpl = (void *)&eq->desc[0]; 4945 } else { 4946 cpl = flitp; 4947 } 4948 4949 /* Checksum offload */ 4950 ctrl1 = 0; 4951 if (needs_l3_csum(m) == 0) 4952 ctrl1 |= F_TXPKT_IPCSUM_DIS; 4953 if (needs_l4_csum(m) == 0) 4954 ctrl1 |= F_TXPKT_L4CSUM_DIS; 4955 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | 4956 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO)) 4957 txq->txcsum++; /* some hardware assistance provided */ 4958 4959 /* VLAN tag insertion */ 4960 if (needs_vlan_insertion(m)) { 4961 ctrl1 |= F_TXPKT_VLAN_VLD | 4962 V_TXPKT_VLAN(m->m_pkthdr.ether_vtag); 4963 txq->vlan_insertion++; 4964 } 4965 4966 /* CPL header */ 4967 cpl->ctrl0 = txq->cpl_ctrl0; 4968 cpl->pack = 0; 4969 cpl->len = htobe16(m->m_pkthdr.len); 4970 cpl->ctrl1 = htobe64(ctrl1); 4971 4972 flitp = cpl + 1; 4973 if (checkwrap && 4974 (uintptr_t)flitp == (uintptr_t)&eq->desc[eq->sidx]) 4975 flitp = (void *)&eq->desc[0]; 4976 4977 write_gl_to_txd(txq, m, (caddr_t *)(&flitp), checkwrap); 4978 4979 } 4980 4981 if (txp->wr_type == 0) { 4982 txq->txpkts0_pkts += txp->npkt; 4983 txq->txpkts0_wrs++; 4984 } else { 4985 txq->txpkts1_pkts += txp->npkt; 4986 txq->txpkts1_wrs++; 4987 } 4988 4989 txsd = &txq->sdesc[eq->pidx]; 4990 txsd->m = m0; 4991 txsd->desc_used = ndesc; 4992 4993 return (ndesc); 4994 } 4995 4996 /* 4997 * If the SGL ends on an address that is not 16 byte aligned, this function will 4998 * add a 0 filled flit at the end. 4999 */ 5000 static void 5001 write_gl_to_txd(struct sge_txq *txq, struct mbuf *m, caddr_t *to, int checkwrap) 5002 { 5003 struct sge_eq *eq = &txq->eq; 5004 struct sglist *gl = txq->gl; 5005 struct sglist_seg *seg; 5006 __be64 *flitp, *wrap; 5007 struct ulptx_sgl *usgl; 5008 int i, nflits, nsegs; 5009 5010 KASSERT(((uintptr_t)(*to) & 0xf) == 0, 5011 ("%s: SGL must start at a 16 byte boundary: %p", __func__, *to)); 5012 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]); 5013 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]); 5014 5015 get_pkt_gl(m, gl); 5016 nsegs = gl->sg_nseg; 5017 MPASS(nsegs > 0); 5018 5019 nflits = (3 * (nsegs - 1)) / 2 + ((nsegs - 1) & 1) + 2; 5020 flitp = (__be64 *)(*to); 5021 wrap = (__be64 *)(&eq->desc[eq->sidx]); 5022 seg = &gl->sg_segs[0]; 5023 usgl = (void *)flitp; 5024 5025 /* 5026 * We start at a 16 byte boundary somewhere inside the tx descriptor 5027 * ring, so we're at least 16 bytes away from the status page. There is 5028 * no chance of a wrap around in the middle of usgl (which is 16 bytes). 5029 */ 5030 5031 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 5032 V_ULPTX_NSGE(nsegs)); 5033 usgl->len0 = htobe32(seg->ss_len); 5034 usgl->addr0 = htobe64(seg->ss_paddr); 5035 seg++; 5036 5037 if (checkwrap == 0 || (uintptr_t)(flitp + nflits) <= (uintptr_t)wrap) { 5038 5039 /* Won't wrap around at all */ 5040 5041 for (i = 0; i < nsegs - 1; i++, seg++) { 5042 usgl->sge[i / 2].len[i & 1] = htobe32(seg->ss_len); 5043 usgl->sge[i / 2].addr[i & 1] = htobe64(seg->ss_paddr); 5044 } 5045 if (i & 1) 5046 usgl->sge[i / 2].len[1] = htobe32(0); 5047 flitp += nflits; 5048 } else { 5049 5050 /* Will wrap somewhere in the rest of the SGL */ 5051 5052 /* 2 flits already written, write the rest flit by flit */ 5053 flitp = (void *)(usgl + 1); 5054 for (i = 0; i < nflits - 2; i++) { 5055 if (flitp == wrap) 5056 flitp = (void *)eq->desc; 5057 *flitp++ = get_flit(seg, nsegs - 1, i); 5058 } 5059 } 5060 5061 if (nflits & 1) { 5062 MPASS(((uintptr_t)flitp) & 0xf); 5063 *flitp++ = 0; 5064 } 5065 5066 MPASS((((uintptr_t)flitp) & 0xf) == 0); 5067 if (__predict_false(flitp == wrap)) 5068 *to = (void *)eq->desc; 5069 else 5070 *to = (void *)flitp; 5071 } 5072 5073 static inline void 5074 copy_to_txd(struct sge_eq *eq, caddr_t from, caddr_t *to, int len) 5075 { 5076 5077 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]); 5078 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]); 5079 5080 if (__predict_true((uintptr_t)(*to) + len <= 5081 (uintptr_t)&eq->desc[eq->sidx])) { 5082 bcopy(from, *to, len); 5083 (*to) += len; 5084 } else { 5085 int portion = (uintptr_t)&eq->desc[eq->sidx] - (uintptr_t)(*to); 5086 5087 bcopy(from, *to, portion); 5088 from += portion; 5089 portion = len - portion; /* remaining */ 5090 bcopy(from, (void *)eq->desc, portion); 5091 (*to) = (caddr_t)eq->desc + portion; 5092 } 5093 } 5094 5095 static inline void 5096 ring_eq_db(struct adapter *sc, struct sge_eq *eq, u_int n) 5097 { 5098 u_int db; 5099 5100 MPASS(n > 0); 5101 5102 db = eq->doorbells; 5103 if (n > 1) 5104 clrbit(&db, DOORBELL_WCWR); 5105 wmb(); 5106 5107 switch (ffs(db) - 1) { 5108 case DOORBELL_UDB: 5109 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n)); 5110 break; 5111 5112 case DOORBELL_WCWR: { 5113 volatile uint64_t *dst, *src; 5114 int i; 5115 5116 /* 5117 * Queues whose 128B doorbell segment fits in the page do not 5118 * use relative qid (udb_qid is always 0). Only queues with 5119 * doorbell segments can do WCWR. 5120 */ 5121 KASSERT(eq->udb_qid == 0 && n == 1, 5122 ("%s: inappropriate doorbell (0x%x, %d, %d) for eq %p", 5123 __func__, eq->doorbells, n, eq->dbidx, eq)); 5124 5125 dst = (volatile void *)((uintptr_t)eq->udb + UDBS_WR_OFFSET - 5126 UDBS_DB_OFFSET); 5127 i = eq->dbidx; 5128 src = (void *)&eq->desc[i]; 5129 while (src != (void *)&eq->desc[i + 1]) 5130 *dst++ = *src++; 5131 wmb(); 5132 break; 5133 } 5134 5135 case DOORBELL_UDBWC: 5136 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n)); 5137 wmb(); 5138 break; 5139 5140 case DOORBELL_KDB: 5141 t4_write_reg(sc, sc->sge_kdoorbell_reg, 5142 V_QID(eq->cntxt_id) | V_PIDX(n)); 5143 break; 5144 } 5145 5146 IDXINCR(eq->dbidx, n, eq->sidx); 5147 } 5148 5149 static inline u_int 5150 reclaimable_tx_desc(struct sge_eq *eq) 5151 { 5152 uint16_t hw_cidx; 5153 5154 hw_cidx = read_hw_cidx(eq); 5155 return (IDXDIFF(hw_cidx, eq->cidx, eq->sidx)); 5156 } 5157 5158 static inline u_int 5159 total_available_tx_desc(struct sge_eq *eq) 5160 { 5161 uint16_t hw_cidx, pidx; 5162 5163 hw_cidx = read_hw_cidx(eq); 5164 pidx = eq->pidx; 5165 5166 if (pidx == hw_cidx) 5167 return (eq->sidx - 1); 5168 else 5169 return (IDXDIFF(hw_cidx, pidx, eq->sidx) - 1); 5170 } 5171 5172 static inline uint16_t 5173 read_hw_cidx(struct sge_eq *eq) 5174 { 5175 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx]; 5176 uint16_t cidx = spg->cidx; /* stable snapshot */ 5177 5178 return (be16toh(cidx)); 5179 } 5180 5181 /* 5182 * Reclaim 'n' descriptors approximately. 5183 */ 5184 static u_int 5185 reclaim_tx_descs(struct sge_txq *txq, u_int n) 5186 { 5187 struct tx_sdesc *txsd; 5188 struct sge_eq *eq = &txq->eq; 5189 u_int can_reclaim, reclaimed; 5190 5191 TXQ_LOCK_ASSERT_OWNED(txq); 5192 MPASS(n > 0); 5193 5194 reclaimed = 0; 5195 can_reclaim = reclaimable_tx_desc(eq); 5196 while (can_reclaim && reclaimed < n) { 5197 int ndesc; 5198 struct mbuf *m, *nextpkt; 5199 5200 txsd = &txq->sdesc[eq->cidx]; 5201 ndesc = txsd->desc_used; 5202 5203 /* Firmware doesn't return "partial" credits. */ 5204 KASSERT(can_reclaim >= ndesc, 5205 ("%s: unexpected number of credits: %d, %d", 5206 __func__, can_reclaim, ndesc)); 5207 KASSERT(ndesc != 0, 5208 ("%s: descriptor with no credits: cidx %d", 5209 __func__, eq->cidx)); 5210 5211 for (m = txsd->m; m != NULL; m = nextpkt) { 5212 nextpkt = m->m_nextpkt; 5213 m->m_nextpkt = NULL; 5214 m_freem(m); 5215 } 5216 reclaimed += ndesc; 5217 can_reclaim -= ndesc; 5218 IDXINCR(eq->cidx, ndesc, eq->sidx); 5219 } 5220 5221 return (reclaimed); 5222 } 5223 5224 static void 5225 tx_reclaim(void *arg, int n) 5226 { 5227 struct sge_txq *txq = arg; 5228 struct sge_eq *eq = &txq->eq; 5229 5230 do { 5231 if (TXQ_TRYLOCK(txq) == 0) 5232 break; 5233 n = reclaim_tx_descs(txq, 32); 5234 if (eq->cidx == eq->pidx) 5235 eq->equeqidx = eq->pidx; 5236 TXQ_UNLOCK(txq); 5237 } while (n > 0); 5238 } 5239 5240 static __be64 5241 get_flit(struct sglist_seg *segs, int nsegs, int idx) 5242 { 5243 int i = (idx / 3) * 2; 5244 5245 switch (idx % 3) { 5246 case 0: { 5247 uint64_t rc; 5248 5249 rc = (uint64_t)segs[i].ss_len << 32; 5250 if (i + 1 < nsegs) 5251 rc |= (uint64_t)(segs[i + 1].ss_len); 5252 5253 return (htobe64(rc)); 5254 } 5255 case 1: 5256 return (htobe64(segs[i].ss_paddr)); 5257 case 2: 5258 return (htobe64(segs[i + 1].ss_paddr)); 5259 } 5260 5261 return (0); 5262 } 5263 5264 static void 5265 find_best_refill_source(struct adapter *sc, struct sge_fl *fl, int maxp) 5266 { 5267 int8_t zidx, hwidx, idx; 5268 uint16_t region1, region3; 5269 int spare, spare_needed, n; 5270 struct sw_zone_info *swz; 5271 struct hw_buf_info *hwb, *hwb_list = &sc->sge.hw_buf_info[0]; 5272 5273 /* 5274 * Buffer Packing: Look for PAGE_SIZE or larger zone which has a bufsize 5275 * large enough for the max payload and cluster metadata. Otherwise 5276 * settle for the largest bufsize that leaves enough room in the cluster 5277 * for metadata. 5278 * 5279 * Without buffer packing: Look for the smallest zone which has a 5280 * bufsize large enough for the max payload. Settle for the largest 5281 * bufsize available if there's nothing big enough for max payload. 5282 */ 5283 spare_needed = fl->flags & FL_BUF_PACKING ? CL_METADATA_SIZE : 0; 5284 swz = &sc->sge.sw_zone_info[0]; 5285 hwidx = -1; 5286 for (zidx = 0; zidx < SW_ZONE_SIZES; zidx++, swz++) { 5287 if (swz->size > largest_rx_cluster) { 5288 if (__predict_true(hwidx != -1)) 5289 break; 5290 5291 /* 5292 * This is a misconfiguration. largest_rx_cluster is 5293 * preventing us from finding a refill source. See 5294 * dev.t5nex.<n>.buffer_sizes to figure out why. 5295 */ 5296 device_printf(sc->dev, "largest_rx_cluster=%u leaves no" 5297 " refill source for fl %p (dma %u). Ignored.\n", 5298 largest_rx_cluster, fl, maxp); 5299 } 5300 for (idx = swz->head_hwidx; idx != -1; idx = hwb->next) { 5301 hwb = &hwb_list[idx]; 5302 spare = swz->size - hwb->size; 5303 if (spare < spare_needed) 5304 continue; 5305 5306 hwidx = idx; /* best option so far */ 5307 if (hwb->size >= maxp) { 5308 5309 if ((fl->flags & FL_BUF_PACKING) == 0) 5310 goto done; /* stop looking (not packing) */ 5311 5312 if (swz->size >= safest_rx_cluster) 5313 goto done; /* stop looking (packing) */ 5314 } 5315 break; /* keep looking, next zone */ 5316 } 5317 } 5318 done: 5319 /* A usable hwidx has been located. */ 5320 MPASS(hwidx != -1); 5321 hwb = &hwb_list[hwidx]; 5322 zidx = hwb->zidx; 5323 swz = &sc->sge.sw_zone_info[zidx]; 5324 region1 = 0; 5325 region3 = swz->size - hwb->size; 5326 5327 /* 5328 * Stay within this zone and see if there is a better match when mbuf 5329 * inlining is allowed. Remember that the hwidx's are sorted in 5330 * decreasing order of size (so in increasing order of spare area). 5331 */ 5332 for (idx = hwidx; idx != -1; idx = hwb->next) { 5333 hwb = &hwb_list[idx]; 5334 spare = swz->size - hwb->size; 5335 5336 if (allow_mbufs_in_cluster == 0 || hwb->size < maxp) 5337 break; 5338 5339 /* 5340 * Do not inline mbufs if doing so would violate the pad/pack 5341 * boundary alignment requirement. 5342 */ 5343 if (fl_pad && (MSIZE % sc->params.sge.pad_boundary) != 0) 5344 continue; 5345 if (fl->flags & FL_BUF_PACKING && 5346 (MSIZE % sc->params.sge.pack_boundary) != 0) 5347 continue; 5348 5349 if (spare < CL_METADATA_SIZE + MSIZE) 5350 continue; 5351 n = (spare - CL_METADATA_SIZE) / MSIZE; 5352 if (n > howmany(hwb->size, maxp)) 5353 break; 5354 5355 hwidx = idx; 5356 if (fl->flags & FL_BUF_PACKING) { 5357 region1 = n * MSIZE; 5358 region3 = spare - region1; 5359 } else { 5360 region1 = MSIZE; 5361 region3 = spare - region1; 5362 break; 5363 } 5364 } 5365 5366 KASSERT(zidx >= 0 && zidx < SW_ZONE_SIZES, 5367 ("%s: bad zone %d for fl %p, maxp %d", __func__, zidx, fl, maxp)); 5368 KASSERT(hwidx >= 0 && hwidx <= SGE_FLBUF_SIZES, 5369 ("%s: bad hwidx %d for fl %p, maxp %d", __func__, hwidx, fl, maxp)); 5370 KASSERT(region1 + sc->sge.hw_buf_info[hwidx].size + region3 == 5371 sc->sge.sw_zone_info[zidx].size, 5372 ("%s: bad buffer layout for fl %p, maxp %d. " 5373 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp, 5374 sc->sge.sw_zone_info[zidx].size, region1, 5375 sc->sge.hw_buf_info[hwidx].size, region3)); 5376 if (fl->flags & FL_BUF_PACKING || region1 > 0) { 5377 KASSERT(region3 >= CL_METADATA_SIZE, 5378 ("%s: no room for metadata. fl %p, maxp %d; " 5379 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp, 5380 sc->sge.sw_zone_info[zidx].size, region1, 5381 sc->sge.hw_buf_info[hwidx].size, region3)); 5382 KASSERT(region1 % MSIZE == 0, 5383 ("%s: bad mbuf region for fl %p, maxp %d. " 5384 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp, 5385 sc->sge.sw_zone_info[zidx].size, region1, 5386 sc->sge.hw_buf_info[hwidx].size, region3)); 5387 } 5388 5389 fl->cll_def.zidx = zidx; 5390 fl->cll_def.hwidx = hwidx; 5391 fl->cll_def.region1 = region1; 5392 fl->cll_def.region3 = region3; 5393 } 5394 5395 static void 5396 find_safe_refill_source(struct adapter *sc, struct sge_fl *fl) 5397 { 5398 struct sge *s = &sc->sge; 5399 struct hw_buf_info *hwb; 5400 struct sw_zone_info *swz; 5401 int spare; 5402 int8_t hwidx; 5403 5404 if (fl->flags & FL_BUF_PACKING) 5405 hwidx = s->safe_hwidx2; /* with room for metadata */ 5406 else if (allow_mbufs_in_cluster && s->safe_hwidx2 != -1) { 5407 hwidx = s->safe_hwidx2; 5408 hwb = &s->hw_buf_info[hwidx]; 5409 swz = &s->sw_zone_info[hwb->zidx]; 5410 spare = swz->size - hwb->size; 5411 5412 /* no good if there isn't room for an mbuf as well */ 5413 if (spare < CL_METADATA_SIZE + MSIZE) 5414 hwidx = s->safe_hwidx1; 5415 } else 5416 hwidx = s->safe_hwidx1; 5417 5418 if (hwidx == -1) { 5419 /* No fallback source */ 5420 fl->cll_alt.hwidx = -1; 5421 fl->cll_alt.zidx = -1; 5422 5423 return; 5424 } 5425 5426 hwb = &s->hw_buf_info[hwidx]; 5427 swz = &s->sw_zone_info[hwb->zidx]; 5428 spare = swz->size - hwb->size; 5429 fl->cll_alt.hwidx = hwidx; 5430 fl->cll_alt.zidx = hwb->zidx; 5431 if (allow_mbufs_in_cluster && 5432 (fl_pad == 0 || (MSIZE % sc->params.sge.pad_boundary) == 0)) 5433 fl->cll_alt.region1 = ((spare - CL_METADATA_SIZE) / MSIZE) * MSIZE; 5434 else 5435 fl->cll_alt.region1 = 0; 5436 fl->cll_alt.region3 = spare - fl->cll_alt.region1; 5437 } 5438 5439 static void 5440 add_fl_to_sfl(struct adapter *sc, struct sge_fl *fl) 5441 { 5442 mtx_lock(&sc->sfl_lock); 5443 FL_LOCK(fl); 5444 if ((fl->flags & FL_DOOMED) == 0) { 5445 fl->flags |= FL_STARVING; 5446 TAILQ_INSERT_TAIL(&sc->sfl, fl, link); 5447 callout_reset(&sc->sfl_callout, hz / 5, refill_sfl, sc); 5448 } 5449 FL_UNLOCK(fl); 5450 mtx_unlock(&sc->sfl_lock); 5451 } 5452 5453 static void 5454 handle_wrq_egr_update(struct adapter *sc, struct sge_eq *eq) 5455 { 5456 struct sge_wrq *wrq = (void *)eq; 5457 5458 atomic_readandclear_int(&eq->equiq); 5459 taskqueue_enqueue(sc->tq[eq->tx_chan], &wrq->wrq_tx_task); 5460 } 5461 5462 static void 5463 handle_eth_egr_update(struct adapter *sc, struct sge_eq *eq) 5464 { 5465 struct sge_txq *txq = (void *)eq; 5466 5467 MPASS((eq->flags & EQ_TYPEMASK) == EQ_ETH); 5468 5469 atomic_readandclear_int(&eq->equiq); 5470 mp_ring_check_drainage(txq->r, 0); 5471 taskqueue_enqueue(sc->tq[eq->tx_chan], &txq->tx_reclaim_task); 5472 } 5473 5474 static int 5475 handle_sge_egr_update(struct sge_iq *iq, const struct rss_header *rss, 5476 struct mbuf *m) 5477 { 5478 const struct cpl_sge_egr_update *cpl = (const void *)(rss + 1); 5479 unsigned int qid = G_EGR_QID(ntohl(cpl->opcode_qid)); 5480 struct adapter *sc = iq->adapter; 5481 struct sge *s = &sc->sge; 5482 struct sge_eq *eq; 5483 static void (*h[])(struct adapter *, struct sge_eq *) = {NULL, 5484 &handle_wrq_egr_update, &handle_eth_egr_update, 5485 &handle_wrq_egr_update}; 5486 5487 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 5488 rss->opcode)); 5489 5490 eq = s->eqmap[qid - s->eq_start - s->eq_base]; 5491 (*h[eq->flags & EQ_TYPEMASK])(sc, eq); 5492 5493 return (0); 5494 } 5495 5496 /* handle_fw_msg works for both fw4_msg and fw6_msg because this is valid */ 5497 CTASSERT(offsetof(struct cpl_fw4_msg, data) == \ 5498 offsetof(struct cpl_fw6_msg, data)); 5499 5500 static int 5501 handle_fw_msg(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 5502 { 5503 struct adapter *sc = iq->adapter; 5504 const struct cpl_fw6_msg *cpl = (const void *)(rss + 1); 5505 5506 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 5507 rss->opcode)); 5508 5509 if (cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL) { 5510 const struct rss_header *rss2; 5511 5512 rss2 = (const struct rss_header *)&cpl->data[0]; 5513 return (t4_cpl_handler[rss2->opcode](iq, rss2, m)); 5514 } 5515 5516 return (t4_fw_msg_handler[cpl->type](sc, &cpl->data[0])); 5517 } 5518 5519 /** 5520 * t4_handle_wrerr_rpl - process a FW work request error message 5521 * @adap: the adapter 5522 * @rpl: start of the FW message 5523 */ 5524 static int 5525 t4_handle_wrerr_rpl(struct adapter *adap, const __be64 *rpl) 5526 { 5527 u8 opcode = *(const u8 *)rpl; 5528 const struct fw_error_cmd *e = (const void *)rpl; 5529 unsigned int i; 5530 5531 if (opcode != FW_ERROR_CMD) { 5532 log(LOG_ERR, 5533 "%s: Received WRERR_RPL message with opcode %#x\n", 5534 device_get_nameunit(adap->dev), opcode); 5535 return (EINVAL); 5536 } 5537 log(LOG_ERR, "%s: FW_ERROR (%s) ", device_get_nameunit(adap->dev), 5538 G_FW_ERROR_CMD_FATAL(be32toh(e->op_to_type)) ? "fatal" : 5539 "non-fatal"); 5540 switch (G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type))) { 5541 case FW_ERROR_TYPE_EXCEPTION: 5542 log(LOG_ERR, "exception info:\n"); 5543 for (i = 0; i < nitems(e->u.exception.info); i++) 5544 log(LOG_ERR, "%s%08x", i == 0 ? "\t" : " ", 5545 be32toh(e->u.exception.info[i])); 5546 log(LOG_ERR, "\n"); 5547 break; 5548 case FW_ERROR_TYPE_HWMODULE: 5549 log(LOG_ERR, "HW module regaddr %08x regval %08x\n", 5550 be32toh(e->u.hwmodule.regaddr), 5551 be32toh(e->u.hwmodule.regval)); 5552 break; 5553 case FW_ERROR_TYPE_WR: 5554 log(LOG_ERR, "WR cidx %d PF %d VF %d eqid %d hdr:\n", 5555 be16toh(e->u.wr.cidx), 5556 G_FW_ERROR_CMD_PFN(be16toh(e->u.wr.pfn_vfn)), 5557 G_FW_ERROR_CMD_VFN(be16toh(e->u.wr.pfn_vfn)), 5558 be32toh(e->u.wr.eqid)); 5559 for (i = 0; i < nitems(e->u.wr.wrhdr); i++) 5560 log(LOG_ERR, "%s%02x", i == 0 ? "\t" : " ", 5561 e->u.wr.wrhdr[i]); 5562 log(LOG_ERR, "\n"); 5563 break; 5564 case FW_ERROR_TYPE_ACL: 5565 log(LOG_ERR, "ACL cidx %d PF %d VF %d eqid %d %s", 5566 be16toh(e->u.acl.cidx), 5567 G_FW_ERROR_CMD_PFN(be16toh(e->u.acl.pfn_vfn)), 5568 G_FW_ERROR_CMD_VFN(be16toh(e->u.acl.pfn_vfn)), 5569 be32toh(e->u.acl.eqid), 5570 G_FW_ERROR_CMD_MV(be16toh(e->u.acl.mv_pkd)) ? "vlanid" : 5571 "MAC"); 5572 for (i = 0; i < nitems(e->u.acl.val); i++) 5573 log(LOG_ERR, " %02x", e->u.acl.val[i]); 5574 log(LOG_ERR, "\n"); 5575 break; 5576 default: 5577 log(LOG_ERR, "type %#x\n", 5578 G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type))); 5579 return (EINVAL); 5580 } 5581 return (0); 5582 } 5583 5584 static int 5585 sysctl_uint16(SYSCTL_HANDLER_ARGS) 5586 { 5587 uint16_t *id = arg1; 5588 int i = *id; 5589 5590 return sysctl_handle_int(oidp, &i, 0, req); 5591 } 5592 5593 static int 5594 sysctl_bufsizes(SYSCTL_HANDLER_ARGS) 5595 { 5596 struct sge *s = arg1; 5597 struct hw_buf_info *hwb = &s->hw_buf_info[0]; 5598 struct sw_zone_info *swz = &s->sw_zone_info[0]; 5599 int i, rc; 5600 struct sbuf sb; 5601 char c; 5602 5603 sbuf_new(&sb, NULL, 32, SBUF_AUTOEXTEND); 5604 for (i = 0; i < SGE_FLBUF_SIZES; i++, hwb++) { 5605 if (hwb->zidx >= 0 && swz[hwb->zidx].size <= largest_rx_cluster) 5606 c = '*'; 5607 else 5608 c = '\0'; 5609 5610 sbuf_printf(&sb, "%u%c ", hwb->size, c); 5611 } 5612 sbuf_trim(&sb); 5613 sbuf_finish(&sb); 5614 rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req); 5615 sbuf_delete(&sb); 5616 return (rc); 5617 } 5618 5619 #ifdef RATELIMIT 5620 /* 5621 * len16 for a txpkt WR with a GL. Includes the firmware work request header. 5622 */ 5623 static inline u_int 5624 txpkt_eo_len16(u_int nsegs, u_int immhdrs, u_int tso) 5625 { 5626 u_int n; 5627 5628 MPASS(immhdrs > 0); 5629 5630 n = roundup2(sizeof(struct fw_eth_tx_eo_wr) + 5631 sizeof(struct cpl_tx_pkt_core) + immhdrs, 16); 5632 if (__predict_false(nsegs == 0)) 5633 goto done; 5634 5635 nsegs--; /* first segment is part of ulptx_sgl */ 5636 n += sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 5637 if (tso) 5638 n += sizeof(struct cpl_tx_pkt_lso_core); 5639 5640 done: 5641 return (howmany(n, 16)); 5642 } 5643 5644 #define ETID_FLOWC_NPARAMS 6 5645 #define ETID_FLOWC_LEN (roundup2((sizeof(struct fw_flowc_wr) + \ 5646 ETID_FLOWC_NPARAMS * sizeof(struct fw_flowc_mnemval)), 16)) 5647 #define ETID_FLOWC_LEN16 (howmany(ETID_FLOWC_LEN, 16)) 5648 5649 static int 5650 send_etid_flowc_wr(struct cxgbe_snd_tag *cst, struct port_info *pi, 5651 struct vi_info *vi) 5652 { 5653 struct wrq_cookie cookie; 5654 u_int pfvf = G_FW_VIID_PFN(vi->viid) << S_FW_VIID_PFN; 5655 struct fw_flowc_wr *flowc; 5656 5657 mtx_assert(&cst->lock, MA_OWNED); 5658 MPASS((cst->flags & (EO_FLOWC_PENDING | EO_FLOWC_RPL_PENDING)) == 5659 EO_FLOWC_PENDING); 5660 5661 flowc = start_wrq_wr(cst->eo_txq, ETID_FLOWC_LEN16, &cookie); 5662 if (__predict_false(flowc == NULL)) 5663 return (ENOMEM); 5664 5665 bzero(flowc, ETID_FLOWC_LEN); 5666 flowc->op_to_nparams = htobe32(V_FW_WR_OP(FW_FLOWC_WR) | 5667 V_FW_FLOWC_WR_NPARAMS(ETID_FLOWC_NPARAMS) | V_FW_WR_COMPL(0)); 5668 flowc->flowid_len16 = htonl(V_FW_WR_LEN16(ETID_FLOWC_LEN16) | 5669 V_FW_WR_FLOWID(cst->etid)); 5670 flowc->mnemval[0].mnemonic = FW_FLOWC_MNEM_PFNVFN; 5671 flowc->mnemval[0].val = htobe32(pfvf); 5672 flowc->mnemval[1].mnemonic = FW_FLOWC_MNEM_CH; 5673 flowc->mnemval[1].val = htobe32(pi->tx_chan); 5674 flowc->mnemval[2].mnemonic = FW_FLOWC_MNEM_PORT; 5675 flowc->mnemval[2].val = htobe32(pi->tx_chan); 5676 flowc->mnemval[3].mnemonic = FW_FLOWC_MNEM_IQID; 5677 flowc->mnemval[3].val = htobe32(cst->iqid); 5678 flowc->mnemval[4].mnemonic = FW_FLOWC_MNEM_EOSTATE; 5679 flowc->mnemval[4].val = htobe32(FW_FLOWC_MNEM_EOSTATE_ESTABLISHED); 5680 flowc->mnemval[5].mnemonic = FW_FLOWC_MNEM_SCHEDCLASS; 5681 flowc->mnemval[5].val = htobe32(cst->schedcl); 5682 5683 commit_wrq_wr(cst->eo_txq, flowc, &cookie); 5684 5685 cst->flags &= ~EO_FLOWC_PENDING; 5686 cst->flags |= EO_FLOWC_RPL_PENDING; 5687 MPASS(cst->tx_credits >= ETID_FLOWC_LEN16); /* flowc is first WR. */ 5688 cst->tx_credits -= ETID_FLOWC_LEN16; 5689 5690 return (0); 5691 } 5692 5693 #define ETID_FLUSH_LEN16 (howmany(sizeof (struct fw_flowc_wr), 16)) 5694 5695 void 5696 send_etid_flush_wr(struct cxgbe_snd_tag *cst) 5697 { 5698 struct fw_flowc_wr *flowc; 5699 struct wrq_cookie cookie; 5700 5701 mtx_assert(&cst->lock, MA_OWNED); 5702 5703 flowc = start_wrq_wr(cst->eo_txq, ETID_FLUSH_LEN16, &cookie); 5704 if (__predict_false(flowc == NULL)) 5705 CXGBE_UNIMPLEMENTED(__func__); 5706 5707 bzero(flowc, ETID_FLUSH_LEN16 * 16); 5708 flowc->op_to_nparams = htobe32(V_FW_WR_OP(FW_FLOWC_WR) | 5709 V_FW_FLOWC_WR_NPARAMS(0) | F_FW_WR_COMPL); 5710 flowc->flowid_len16 = htobe32(V_FW_WR_LEN16(ETID_FLUSH_LEN16) | 5711 V_FW_WR_FLOWID(cst->etid)); 5712 5713 commit_wrq_wr(cst->eo_txq, flowc, &cookie); 5714 5715 cst->flags |= EO_FLUSH_RPL_PENDING; 5716 MPASS(cst->tx_credits >= ETID_FLUSH_LEN16); 5717 cst->tx_credits -= ETID_FLUSH_LEN16; 5718 cst->ncompl++; 5719 } 5720 5721 static void 5722 write_ethofld_wr(struct cxgbe_snd_tag *cst, struct fw_eth_tx_eo_wr *wr, 5723 struct mbuf *m0, int compl) 5724 { 5725 struct cpl_tx_pkt_core *cpl; 5726 uint64_t ctrl1; 5727 uint32_t ctrl; /* used in many unrelated places */ 5728 int len16, pktlen, nsegs, immhdrs; 5729 caddr_t dst; 5730 uintptr_t p; 5731 struct ulptx_sgl *usgl; 5732 struct sglist sg; 5733 struct sglist_seg segs[38]; /* XXX: find real limit. XXX: get off the stack */ 5734 5735 mtx_assert(&cst->lock, MA_OWNED); 5736 M_ASSERTPKTHDR(m0); 5737 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 5738 m0->m_pkthdr.l4hlen > 0, 5739 ("%s: ethofld mbuf %p is missing header lengths", __func__, m0)); 5740 5741 len16 = mbuf_eo_len16(m0); 5742 nsegs = mbuf_eo_nsegs(m0); 5743 pktlen = m0->m_pkthdr.len; 5744 ctrl = sizeof(struct cpl_tx_pkt_core); 5745 if (needs_tso(m0)) 5746 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 5747 immhdrs = m0->m_pkthdr.l2hlen + m0->m_pkthdr.l3hlen + m0->m_pkthdr.l4hlen; 5748 ctrl += immhdrs; 5749 5750 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_EO_WR) | 5751 V_FW_ETH_TX_EO_WR_IMMDLEN(ctrl) | V_FW_WR_COMPL(!!compl)); 5752 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(len16) | 5753 V_FW_WR_FLOWID(cst->etid)); 5754 wr->r3 = 0; 5755 if (needs_udp_csum(m0)) { 5756 wr->u.udpseg.type = FW_ETH_TX_EO_TYPE_UDPSEG; 5757 wr->u.udpseg.ethlen = m0->m_pkthdr.l2hlen; 5758 wr->u.udpseg.iplen = htobe16(m0->m_pkthdr.l3hlen); 5759 wr->u.udpseg.udplen = m0->m_pkthdr.l4hlen; 5760 wr->u.udpseg.rtplen = 0; 5761 wr->u.udpseg.r4 = 0; 5762 wr->u.udpseg.mss = htobe16(pktlen - immhdrs); 5763 wr->u.udpseg.schedpktsize = wr->u.udpseg.mss; 5764 wr->u.udpseg.plen = htobe32(pktlen - immhdrs); 5765 cpl = (void *)(wr + 1); 5766 } else { 5767 MPASS(needs_tcp_csum(m0)); 5768 wr->u.tcpseg.type = FW_ETH_TX_EO_TYPE_TCPSEG; 5769 wr->u.tcpseg.ethlen = m0->m_pkthdr.l2hlen; 5770 wr->u.tcpseg.iplen = htobe16(m0->m_pkthdr.l3hlen); 5771 wr->u.tcpseg.tcplen = m0->m_pkthdr.l4hlen; 5772 wr->u.tcpseg.tsclk_tsoff = mbuf_eo_tsclk_tsoff(m0); 5773 wr->u.tcpseg.r4 = 0; 5774 wr->u.tcpseg.r5 = 0; 5775 wr->u.tcpseg.plen = htobe32(pktlen - immhdrs); 5776 5777 if (needs_tso(m0)) { 5778 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1); 5779 5780 wr->u.tcpseg.mss = htobe16(m0->m_pkthdr.tso_segsz); 5781 5782 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | 5783 F_LSO_FIRST_SLICE | F_LSO_LAST_SLICE | 5784 V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) | 5785 V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2); 5786 if (m0->m_pkthdr.l2hlen == sizeof(struct ether_vlan_header)) 5787 ctrl |= V_LSO_ETHHDR_LEN(1); 5788 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 5789 ctrl |= F_LSO_IPV6; 5790 lso->lso_ctrl = htobe32(ctrl); 5791 lso->ipid_ofst = htobe16(0); 5792 lso->mss = htobe16(m0->m_pkthdr.tso_segsz); 5793 lso->seqno_offset = htobe32(0); 5794 lso->len = htobe32(pktlen); 5795 5796 cpl = (void *)(lso + 1); 5797 } else { 5798 wr->u.tcpseg.mss = htobe16(0xffff); 5799 cpl = (void *)(wr + 1); 5800 } 5801 } 5802 5803 /* Checksum offload must be requested for ethofld. */ 5804 ctrl1 = 0; 5805 MPASS(needs_l4_csum(m0)); 5806 5807 /* VLAN tag insertion */ 5808 if (needs_vlan_insertion(m0)) { 5809 ctrl1 |= F_TXPKT_VLAN_VLD | 5810 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 5811 } 5812 5813 /* CPL header */ 5814 cpl->ctrl0 = cst->ctrl0; 5815 cpl->pack = 0; 5816 cpl->len = htobe16(pktlen); 5817 cpl->ctrl1 = htobe64(ctrl1); 5818 5819 /* Copy Ethernet, IP & TCP/UDP hdrs as immediate data */ 5820 p = (uintptr_t)(cpl + 1); 5821 m_copydata(m0, 0, immhdrs, (void *)p); 5822 5823 /* SGL */ 5824 dst = (void *)(cpl + 1); 5825 if (nsegs > 0) { 5826 int i, pad; 5827 5828 /* zero-pad upto next 16Byte boundary, if not 16Byte aligned */ 5829 p += immhdrs; 5830 pad = 16 - (immhdrs & 0xf); 5831 bzero((void *)p, pad); 5832 5833 usgl = (void *)(p + pad); 5834 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 5835 V_ULPTX_NSGE(nsegs)); 5836 5837 sglist_init(&sg, nitems(segs), segs); 5838 for (; m0 != NULL; m0 = m0->m_next) { 5839 if (__predict_false(m0->m_len == 0)) 5840 continue; 5841 if (immhdrs >= m0->m_len) { 5842 immhdrs -= m0->m_len; 5843 continue; 5844 } 5845 5846 sglist_append(&sg, mtod(m0, char *) + immhdrs, 5847 m0->m_len - immhdrs); 5848 immhdrs = 0; 5849 } 5850 MPASS(sg.sg_nseg == nsegs); 5851 5852 /* 5853 * Zero pad last 8B in case the WR doesn't end on a 16B 5854 * boundary. 5855 */ 5856 *(uint64_t *)((char *)wr + len16 * 16 - 8) = 0; 5857 5858 usgl->len0 = htobe32(segs[0].ss_len); 5859 usgl->addr0 = htobe64(segs[0].ss_paddr); 5860 for (i = 0; i < nsegs - 1; i++) { 5861 usgl->sge[i / 2].len[i & 1] = htobe32(segs[i + 1].ss_len); 5862 usgl->sge[i / 2].addr[i & 1] = htobe64(segs[i + 1].ss_paddr); 5863 } 5864 if (i & 1) 5865 usgl->sge[i / 2].len[1] = htobe32(0); 5866 } 5867 5868 } 5869 5870 static void 5871 ethofld_tx(struct cxgbe_snd_tag *cst) 5872 { 5873 struct mbuf *m; 5874 struct wrq_cookie cookie; 5875 int next_credits, compl; 5876 struct fw_eth_tx_eo_wr *wr; 5877 5878 mtx_assert(&cst->lock, MA_OWNED); 5879 5880 while ((m = mbufq_first(&cst->pending_tx)) != NULL) { 5881 M_ASSERTPKTHDR(m); 5882 5883 /* How many len16 credits do we need to send this mbuf. */ 5884 next_credits = mbuf_eo_len16(m); 5885 MPASS(next_credits > 0); 5886 if (next_credits > cst->tx_credits) { 5887 /* 5888 * Tx will make progress eventually because there is at 5889 * least one outstanding fw4_ack that will return 5890 * credits and kick the tx. 5891 */ 5892 MPASS(cst->ncompl > 0); 5893 return; 5894 } 5895 wr = start_wrq_wr(cst->eo_txq, next_credits, &cookie); 5896 if (__predict_false(wr == NULL)) { 5897 /* XXX: wishful thinking, not a real assertion. */ 5898 MPASS(cst->ncompl > 0); 5899 return; 5900 } 5901 cst->tx_credits -= next_credits; 5902 cst->tx_nocompl += next_credits; 5903 compl = cst->ncompl == 0 || cst->tx_nocompl >= cst->tx_total / 2; 5904 ETHER_BPF_MTAP(cst->com.ifp, m); 5905 write_ethofld_wr(cst, wr, m, compl); 5906 commit_wrq_wr(cst->eo_txq, wr, &cookie); 5907 if (compl) { 5908 cst->ncompl++; 5909 cst->tx_nocompl = 0; 5910 } 5911 (void) mbufq_dequeue(&cst->pending_tx); 5912 mbufq_enqueue(&cst->pending_fwack, m); 5913 } 5914 } 5915 5916 int 5917 ethofld_transmit(struct ifnet *ifp, struct mbuf *m0) 5918 { 5919 struct cxgbe_snd_tag *cst; 5920 int rc; 5921 5922 MPASS(m0->m_nextpkt == NULL); 5923 MPASS(m0->m_pkthdr.snd_tag != NULL); 5924 cst = mst_to_cst(m0->m_pkthdr.snd_tag); 5925 5926 mtx_lock(&cst->lock); 5927 MPASS(cst->flags & EO_SND_TAG_REF); 5928 5929 if (__predict_false(cst->flags & EO_FLOWC_PENDING)) { 5930 struct vi_info *vi = ifp->if_softc; 5931 struct port_info *pi = vi->pi; 5932 struct adapter *sc = pi->adapter; 5933 const uint32_t rss_mask = vi->rss_size - 1; 5934 uint32_t rss_hash; 5935 5936 cst->eo_txq = &sc->sge.ofld_txq[vi->first_ofld_txq]; 5937 if (M_HASHTYPE_ISHASH(m0)) 5938 rss_hash = m0->m_pkthdr.flowid; 5939 else 5940 rss_hash = arc4random(); 5941 /* We assume RSS hashing */ 5942 cst->iqid = vi->rss[rss_hash & rss_mask]; 5943 cst->eo_txq += rss_hash % vi->nofldtxq; 5944 rc = send_etid_flowc_wr(cst, pi, vi); 5945 if (rc != 0) 5946 goto done; 5947 } 5948 5949 if (__predict_false(cst->plen + m0->m_pkthdr.len > eo_max_backlog)) { 5950 rc = ENOBUFS; 5951 goto done; 5952 } 5953 5954 mbufq_enqueue(&cst->pending_tx, m0); 5955 cst->plen += m0->m_pkthdr.len; 5956 5957 ethofld_tx(cst); 5958 rc = 0; 5959 done: 5960 mtx_unlock(&cst->lock); 5961 if (__predict_false(rc != 0)) 5962 m_freem(m0); 5963 return (rc); 5964 } 5965 5966 static int 5967 ethofld_fw4_ack(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0) 5968 { 5969 struct adapter *sc = iq->adapter; 5970 const struct cpl_fw4_ack *cpl = (const void *)(rss + 1); 5971 struct mbuf *m; 5972 u_int etid = G_CPL_FW4_ACK_FLOWID(be32toh(OPCODE_TID(cpl))); 5973 struct cxgbe_snd_tag *cst; 5974 uint8_t credits = cpl->credits; 5975 5976 cst = lookup_etid(sc, etid); 5977 mtx_lock(&cst->lock); 5978 if (__predict_false(cst->flags & EO_FLOWC_RPL_PENDING)) { 5979 MPASS(credits >= ETID_FLOWC_LEN16); 5980 credits -= ETID_FLOWC_LEN16; 5981 cst->flags &= ~EO_FLOWC_RPL_PENDING; 5982 } 5983 5984 KASSERT(cst->ncompl > 0, 5985 ("%s: etid %u (%p) wasn't expecting completion.", 5986 __func__, etid, cst)); 5987 cst->ncompl--; 5988 5989 while (credits > 0) { 5990 m = mbufq_dequeue(&cst->pending_fwack); 5991 if (__predict_false(m == NULL)) { 5992 /* 5993 * The remaining credits are for the final flush that 5994 * was issued when the tag was freed by the kernel. 5995 */ 5996 MPASS((cst->flags & 5997 (EO_FLUSH_RPL_PENDING | EO_SND_TAG_REF)) == 5998 EO_FLUSH_RPL_PENDING); 5999 MPASS(credits == ETID_FLUSH_LEN16); 6000 MPASS(cst->tx_credits + cpl->credits == cst->tx_total); 6001 MPASS(cst->ncompl == 0); 6002 6003 cst->flags &= ~EO_FLUSH_RPL_PENDING; 6004 cst->tx_credits += cpl->credits; 6005 freetag: 6006 cxgbe_snd_tag_free_locked(cst); 6007 return (0); /* cst is gone. */ 6008 } 6009 KASSERT(m != NULL, 6010 ("%s: too many credits (%u, %u)", __func__, cpl->credits, 6011 credits)); 6012 KASSERT(credits >= mbuf_eo_len16(m), 6013 ("%s: too few credits (%u, %u, %u)", __func__, 6014 cpl->credits, credits, mbuf_eo_len16(m))); 6015 credits -= mbuf_eo_len16(m); 6016 cst->plen -= m->m_pkthdr.len; 6017 m_freem(m); 6018 } 6019 6020 cst->tx_credits += cpl->credits; 6021 MPASS(cst->tx_credits <= cst->tx_total); 6022 6023 m = mbufq_first(&cst->pending_tx); 6024 if (m != NULL && cst->tx_credits >= mbuf_eo_len16(m)) 6025 ethofld_tx(cst); 6026 6027 if (__predict_false((cst->flags & EO_SND_TAG_REF) == 0) && 6028 cst->ncompl == 0) { 6029 if (cst->tx_credits == cst->tx_total) 6030 goto freetag; 6031 else { 6032 MPASS((cst->flags & EO_FLUSH_RPL_PENDING) == 0); 6033 send_etid_flush_wr(cst); 6034 } 6035 } 6036 6037 mtx_unlock(&cst->lock); 6038 6039 return (0); 6040 } 6041 #endif 6042