1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 Chelsio Communications, Inc. 5 * All rights reserved. 6 * Written by: Navdeep Parhar <np@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include "opt_inet.h" 34 #include "opt_inet6.h" 35 #include "opt_kern_tls.h" 36 #include "opt_ratelimit.h" 37 38 #include <sys/types.h> 39 #include <sys/eventhandler.h> 40 #include <sys/mbuf.h> 41 #include <sys/socket.h> 42 #include <sys/kernel.h> 43 #include <sys/ktls.h> 44 #include <sys/malloc.h> 45 #include <sys/queue.h> 46 #include <sys/sbuf.h> 47 #include <sys/taskqueue.h> 48 #include <sys/time.h> 49 #include <sys/sglist.h> 50 #include <sys/sysctl.h> 51 #include <sys/smp.h> 52 #include <sys/socketvar.h> 53 #include <sys/counter.h> 54 #include <net/bpf.h> 55 #include <net/ethernet.h> 56 #include <net/if.h> 57 #include <net/if_vlan_var.h> 58 #include <net/if_vxlan.h> 59 #include <netinet/in.h> 60 #include <netinet/ip.h> 61 #include <netinet/ip6.h> 62 #include <netinet/tcp.h> 63 #include <netinet/udp.h> 64 #include <machine/in_cksum.h> 65 #include <machine/md_var.h> 66 #include <vm/vm.h> 67 #include <vm/pmap.h> 68 #ifdef DEV_NETMAP 69 #include <machine/bus.h> 70 #include <sys/selinfo.h> 71 #include <net/if_var.h> 72 #include <net/netmap.h> 73 #include <dev/netmap/netmap_kern.h> 74 #endif 75 76 #include "common/common.h" 77 #include "common/t4_regs.h" 78 #include "common/t4_regs_values.h" 79 #include "common/t4_msg.h" 80 #include "t4_l2t.h" 81 #include "t4_mp_ring.h" 82 83 #ifdef T4_PKT_TIMESTAMP 84 #define RX_COPY_THRESHOLD (MINCLSIZE - 8) 85 #else 86 #define RX_COPY_THRESHOLD MINCLSIZE 87 #endif 88 89 /* Internal mbuf flags stored in PH_loc.eight[1]. */ 90 #define MC_NOMAP 0x01 91 #define MC_RAW_WR 0x02 92 #define MC_TLS 0x04 93 94 /* 95 * Ethernet frames are DMA'd at this byte offset into the freelist buffer. 96 * 0-7 are valid values. 97 */ 98 static int fl_pktshift = 0; 99 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pktshift, CTLFLAG_RDTUN, &fl_pktshift, 0, 100 "payload DMA offset in rx buffer (bytes)"); 101 102 /* 103 * Pad ethernet payload up to this boundary. 104 * -1: driver should figure out a good value. 105 * 0: disable padding. 106 * Any power of 2 from 32 to 4096 (both inclusive) is also a valid value. 107 */ 108 int fl_pad = -1; 109 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pad, CTLFLAG_RDTUN, &fl_pad, 0, 110 "payload pad boundary (bytes)"); 111 112 /* 113 * Status page length. 114 * -1: driver should figure out a good value. 115 * 64 or 128 are the only other valid values. 116 */ 117 static int spg_len = -1; 118 SYSCTL_INT(_hw_cxgbe, OID_AUTO, spg_len, CTLFLAG_RDTUN, &spg_len, 0, 119 "status page size (bytes)"); 120 121 /* 122 * Congestion drops. 123 * -1: no congestion feedback (not recommended). 124 * 0: backpressure the channel instead of dropping packets right away. 125 * 1: no backpressure, drop packets for the congested queue immediately. 126 */ 127 static int cong_drop = 0; 128 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cong_drop, CTLFLAG_RDTUN, &cong_drop, 0, 129 "Congestion control for RX queues (0 = backpressure, 1 = drop"); 130 131 /* 132 * Deliver multiple frames in the same free list buffer if they fit. 133 * -1: let the driver decide whether to enable buffer packing or not. 134 * 0: disable buffer packing. 135 * 1: enable buffer packing. 136 */ 137 static int buffer_packing = -1; 138 SYSCTL_INT(_hw_cxgbe, OID_AUTO, buffer_packing, CTLFLAG_RDTUN, &buffer_packing, 139 0, "Enable buffer packing"); 140 141 /* 142 * Start next frame in a packed buffer at this boundary. 143 * -1: driver should figure out a good value. 144 * T4: driver will ignore this and use the same value as fl_pad above. 145 * T5: 16, or a power of 2 from 64 to 4096 (both inclusive) is a valid value. 146 */ 147 static int fl_pack = -1; 148 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pack, CTLFLAG_RDTUN, &fl_pack, 0, 149 "payload pack boundary (bytes)"); 150 151 /* 152 * Largest rx cluster size that the driver is allowed to allocate. 153 */ 154 static int largest_rx_cluster = MJUM16BYTES; 155 SYSCTL_INT(_hw_cxgbe, OID_AUTO, largest_rx_cluster, CTLFLAG_RDTUN, 156 &largest_rx_cluster, 0, "Largest rx cluster (bytes)"); 157 158 /* 159 * Size of cluster allocation that's most likely to succeed. The driver will 160 * fall back to this size if it fails to allocate clusters larger than this. 161 */ 162 static int safest_rx_cluster = PAGE_SIZE; 163 SYSCTL_INT(_hw_cxgbe, OID_AUTO, safest_rx_cluster, CTLFLAG_RDTUN, 164 &safest_rx_cluster, 0, "Safe rx cluster (bytes)"); 165 166 #ifdef RATELIMIT 167 /* 168 * Knob to control TCP timestamp rewriting, and the granularity of the tick used 169 * for rewriting. -1 and 0-3 are all valid values. 170 * -1: hardware should leave the TCP timestamps alone. 171 * 0: 1ms 172 * 1: 100us 173 * 2: 10us 174 * 3: 1us 175 */ 176 static int tsclk = -1; 177 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tsclk, CTLFLAG_RDTUN, &tsclk, 0, 178 "Control TCP timestamp rewriting when using pacing"); 179 180 static int eo_max_backlog = 1024 * 1024; 181 SYSCTL_INT(_hw_cxgbe, OID_AUTO, eo_max_backlog, CTLFLAG_RDTUN, &eo_max_backlog, 182 0, "Maximum backlog of ratelimited data per flow"); 183 #endif 184 185 /* 186 * The interrupt holdoff timers are multiplied by this value on T6+. 187 * 1 and 3-17 (both inclusive) are legal values. 188 */ 189 static int tscale = 1; 190 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tscale, CTLFLAG_RDTUN, &tscale, 0, 191 "Interrupt holdoff timer scale on T6+"); 192 193 /* 194 * Number of LRO entries in the lro_ctrl structure per rx queue. 195 */ 196 static int lro_entries = TCP_LRO_ENTRIES; 197 SYSCTL_INT(_hw_cxgbe, OID_AUTO, lro_entries, CTLFLAG_RDTUN, &lro_entries, 0, 198 "Number of LRO entries per RX queue"); 199 200 /* 201 * This enables presorting of frames before they're fed into tcp_lro_rx. 202 */ 203 static int lro_mbufs = 0; 204 SYSCTL_INT(_hw_cxgbe, OID_AUTO, lro_mbufs, CTLFLAG_RDTUN, &lro_mbufs, 0, 205 "Enable presorting of LRO frames"); 206 207 static counter_u64_t pullups; 208 SYSCTL_COUNTER_U64(_hw_cxgbe, OID_AUTO, pullups, CTLFLAG_RD, &pullups, 209 "Number of mbuf pullups performed"); 210 211 static counter_u64_t defrags; 212 SYSCTL_COUNTER_U64(_hw_cxgbe, OID_AUTO, defrags, CTLFLAG_RD, &defrags, 213 "Number of mbuf defrags performed"); 214 215 static int t4_tx_coalesce = 1; 216 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tx_coalesce, CTLFLAG_RWTUN, &t4_tx_coalesce, 0, 217 "tx coalescing allowed"); 218 219 /* 220 * The driver will make aggressive attempts at tx coalescing if it sees these 221 * many packets eligible for coalescing in quick succession, with no more than 222 * the specified gap in between the eth_tx calls that delivered the packets. 223 */ 224 static int t4_tx_coalesce_pkts = 32; 225 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tx_coalesce_pkts, CTLFLAG_RWTUN, 226 &t4_tx_coalesce_pkts, 0, 227 "# of consecutive packets (1 - 255) that will trigger tx coalescing"); 228 static int t4_tx_coalesce_gap = 5; 229 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tx_coalesce_gap, CTLFLAG_RWTUN, 230 &t4_tx_coalesce_gap, 0, "tx gap (in microseconds)"); 231 232 static int service_iq(struct sge_iq *, int); 233 static int service_iq_fl(struct sge_iq *, int); 234 static struct mbuf *get_fl_payload(struct adapter *, struct sge_fl *, uint32_t); 235 static int eth_rx(struct adapter *, struct sge_rxq *, const struct iq_desc *, 236 u_int); 237 static inline void init_iq(struct sge_iq *, struct adapter *, int, int, int, 238 int, int); 239 static inline void init_fl(struct adapter *, struct sge_fl *, int, int, char *); 240 static inline void init_eq(struct adapter *, struct sge_eq *, int, int, uint8_t, 241 struct sge_iq *, char *); 242 static int alloc_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *, 243 struct sysctl_ctx_list *, struct sysctl_oid *); 244 static void free_iq_fl(struct adapter *, struct sge_iq *, struct sge_fl *); 245 static void add_iq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *, 246 struct sge_iq *); 247 static void add_fl_sysctls(struct adapter *, struct sysctl_ctx_list *, 248 struct sysctl_oid *, struct sge_fl *); 249 static int alloc_iq_fl_hwq(struct vi_info *, struct sge_iq *, struct sge_fl *); 250 static int free_iq_fl_hwq(struct adapter *, struct sge_iq *, struct sge_fl *); 251 static int alloc_fwq(struct adapter *); 252 static void free_fwq(struct adapter *); 253 static int alloc_ctrlq(struct adapter *, int); 254 static void free_ctrlq(struct adapter *, int); 255 static int alloc_rxq(struct vi_info *, struct sge_rxq *, int, int, int); 256 static void free_rxq(struct vi_info *, struct sge_rxq *); 257 static void add_rxq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *, 258 struct sge_rxq *); 259 #ifdef TCP_OFFLOAD 260 static int alloc_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *, int, int, 261 int); 262 static void free_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *); 263 static void add_ofld_rxq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *, 264 struct sge_ofld_rxq *); 265 #endif 266 static int ctrl_eq_alloc(struct adapter *, struct sge_eq *); 267 static int eth_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *); 268 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 269 static int ofld_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *); 270 #endif 271 static int alloc_eq(struct adapter *, struct sge_eq *, struct sysctl_ctx_list *, 272 struct sysctl_oid *); 273 static void free_eq(struct adapter *, struct sge_eq *); 274 static void add_eq_sysctls(struct adapter *, struct sysctl_ctx_list *, 275 struct sysctl_oid *, struct sge_eq *); 276 static int alloc_eq_hwq(struct adapter *, struct vi_info *, struct sge_eq *); 277 static int free_eq_hwq(struct adapter *, struct vi_info *, struct sge_eq *); 278 static int alloc_wrq(struct adapter *, struct vi_info *, struct sge_wrq *, 279 struct sysctl_ctx_list *, struct sysctl_oid *); 280 static void free_wrq(struct adapter *, struct sge_wrq *); 281 static void add_wrq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *, 282 struct sge_wrq *); 283 static int alloc_txq(struct vi_info *, struct sge_txq *, int); 284 static void free_txq(struct vi_info *, struct sge_txq *); 285 static void add_txq_sysctls(struct vi_info *, struct sysctl_ctx_list *, 286 struct sysctl_oid *, struct sge_txq *); 287 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 288 static int alloc_ofld_txq(struct vi_info *, struct sge_ofld_txq *, int); 289 static void free_ofld_txq(struct vi_info *, struct sge_ofld_txq *); 290 static void add_ofld_txq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *, 291 struct sge_ofld_txq *); 292 #endif 293 static void oneseg_dma_callback(void *, bus_dma_segment_t *, int, int); 294 static inline void ring_fl_db(struct adapter *, struct sge_fl *); 295 static int refill_fl(struct adapter *, struct sge_fl *, int); 296 static void refill_sfl(void *); 297 static int find_refill_source(struct adapter *, int, bool); 298 static void add_fl_to_sfl(struct adapter *, struct sge_fl *); 299 300 static inline void get_pkt_gl(struct mbuf *, struct sglist *); 301 static inline u_int txpkt_len16(u_int, const u_int); 302 static inline u_int txpkt_vm_len16(u_int, const u_int); 303 static inline void calculate_mbuf_len16(struct mbuf *, bool); 304 static inline u_int txpkts0_len16(u_int); 305 static inline u_int txpkts1_len16(void); 306 static u_int write_raw_wr(struct sge_txq *, void *, struct mbuf *, u_int); 307 static u_int write_txpkt_wr(struct adapter *, struct sge_txq *, struct mbuf *, 308 u_int); 309 static u_int write_txpkt_vm_wr(struct adapter *, struct sge_txq *, 310 struct mbuf *); 311 static int add_to_txpkts_vf(struct adapter *, struct sge_txq *, struct mbuf *, 312 int, bool *); 313 static int add_to_txpkts_pf(struct adapter *, struct sge_txq *, struct mbuf *, 314 int, bool *); 315 static u_int write_txpkts_wr(struct adapter *, struct sge_txq *); 316 static u_int write_txpkts_vm_wr(struct adapter *, struct sge_txq *); 317 static void write_gl_to_txd(struct sge_txq *, struct mbuf *, caddr_t *, int); 318 static inline void copy_to_txd(struct sge_eq *, caddr_t, caddr_t *, int); 319 static inline void ring_eq_db(struct adapter *, struct sge_eq *, u_int); 320 static inline uint16_t read_hw_cidx(struct sge_eq *); 321 static inline u_int reclaimable_tx_desc(struct sge_eq *); 322 static inline u_int total_available_tx_desc(struct sge_eq *); 323 static u_int reclaim_tx_descs(struct sge_txq *, u_int); 324 static void tx_reclaim(void *, int); 325 static __be64 get_flit(struct sglist_seg *, int, int); 326 static int handle_sge_egr_update(struct sge_iq *, const struct rss_header *, 327 struct mbuf *); 328 static int handle_fw_msg(struct sge_iq *, const struct rss_header *, 329 struct mbuf *); 330 static int t4_handle_wrerr_rpl(struct adapter *, const __be64 *); 331 static void wrq_tx_drain(void *, int); 332 static void drain_wrq_wr_list(struct adapter *, struct sge_wrq *); 333 334 static int sysctl_bufsizes(SYSCTL_HANDLER_ARGS); 335 #ifdef RATELIMIT 336 static inline u_int txpkt_eo_len16(u_int, u_int, u_int); 337 static int ethofld_fw4_ack(struct sge_iq *, const struct rss_header *, 338 struct mbuf *); 339 #endif 340 341 static counter_u64_t extfree_refs; 342 static counter_u64_t extfree_rels; 343 344 an_handler_t t4_an_handler; 345 fw_msg_handler_t t4_fw_msg_handler[NUM_FW6_TYPES]; 346 cpl_handler_t t4_cpl_handler[NUM_CPL_CMDS]; 347 cpl_handler_t set_tcb_rpl_handlers[NUM_CPL_COOKIES]; 348 cpl_handler_t l2t_write_rpl_handlers[NUM_CPL_COOKIES]; 349 cpl_handler_t act_open_rpl_handlers[NUM_CPL_COOKIES]; 350 cpl_handler_t abort_rpl_rss_handlers[NUM_CPL_COOKIES]; 351 cpl_handler_t fw4_ack_handlers[NUM_CPL_COOKIES]; 352 353 void 354 t4_register_an_handler(an_handler_t h) 355 { 356 uintptr_t *loc; 357 358 MPASS(h == NULL || t4_an_handler == NULL); 359 360 loc = (uintptr_t *)&t4_an_handler; 361 atomic_store_rel_ptr(loc, (uintptr_t)h); 362 } 363 364 void 365 t4_register_fw_msg_handler(int type, fw_msg_handler_t h) 366 { 367 uintptr_t *loc; 368 369 MPASS(type < nitems(t4_fw_msg_handler)); 370 MPASS(h == NULL || t4_fw_msg_handler[type] == NULL); 371 /* 372 * These are dispatched by the handler for FW{4|6}_CPL_MSG using the CPL 373 * handler dispatch table. Reject any attempt to install a handler for 374 * this subtype. 375 */ 376 MPASS(type != FW_TYPE_RSSCPL); 377 MPASS(type != FW6_TYPE_RSSCPL); 378 379 loc = (uintptr_t *)&t4_fw_msg_handler[type]; 380 atomic_store_rel_ptr(loc, (uintptr_t)h); 381 } 382 383 void 384 t4_register_cpl_handler(int opcode, cpl_handler_t h) 385 { 386 uintptr_t *loc; 387 388 MPASS(opcode < nitems(t4_cpl_handler)); 389 MPASS(h == NULL || t4_cpl_handler[opcode] == NULL); 390 391 loc = (uintptr_t *)&t4_cpl_handler[opcode]; 392 atomic_store_rel_ptr(loc, (uintptr_t)h); 393 } 394 395 static int 396 set_tcb_rpl_handler(struct sge_iq *iq, const struct rss_header *rss, 397 struct mbuf *m) 398 { 399 const struct cpl_set_tcb_rpl *cpl = (const void *)(rss + 1); 400 u_int tid; 401 int cookie; 402 403 MPASS(m == NULL); 404 405 tid = GET_TID(cpl); 406 if (is_hpftid(iq->adapter, tid) || is_ftid(iq->adapter, tid)) { 407 /* 408 * The return code for filter-write is put in the CPL cookie so 409 * we have to rely on the hardware tid (is_ftid) to determine 410 * that this is a response to a filter. 411 */ 412 cookie = CPL_COOKIE_FILTER; 413 } else { 414 cookie = G_COOKIE(cpl->cookie); 415 } 416 MPASS(cookie > CPL_COOKIE_RESERVED); 417 MPASS(cookie < nitems(set_tcb_rpl_handlers)); 418 419 return (set_tcb_rpl_handlers[cookie](iq, rss, m)); 420 } 421 422 static int 423 l2t_write_rpl_handler(struct sge_iq *iq, const struct rss_header *rss, 424 struct mbuf *m) 425 { 426 const struct cpl_l2t_write_rpl *rpl = (const void *)(rss + 1); 427 unsigned int cookie; 428 429 MPASS(m == NULL); 430 431 cookie = GET_TID(rpl) & F_SYNC_WR ? CPL_COOKIE_TOM : CPL_COOKIE_FILTER; 432 return (l2t_write_rpl_handlers[cookie](iq, rss, m)); 433 } 434 435 static int 436 act_open_rpl_handler(struct sge_iq *iq, const struct rss_header *rss, 437 struct mbuf *m) 438 { 439 const struct cpl_act_open_rpl *cpl = (const void *)(rss + 1); 440 u_int cookie = G_TID_COOKIE(G_AOPEN_ATID(be32toh(cpl->atid_status))); 441 442 MPASS(m == NULL); 443 MPASS(cookie != CPL_COOKIE_RESERVED); 444 445 return (act_open_rpl_handlers[cookie](iq, rss, m)); 446 } 447 448 static int 449 abort_rpl_rss_handler(struct sge_iq *iq, const struct rss_header *rss, 450 struct mbuf *m) 451 { 452 struct adapter *sc = iq->adapter; 453 u_int cookie; 454 455 MPASS(m == NULL); 456 if (is_hashfilter(sc)) 457 cookie = CPL_COOKIE_HASHFILTER; 458 else 459 cookie = CPL_COOKIE_TOM; 460 461 return (abort_rpl_rss_handlers[cookie](iq, rss, m)); 462 } 463 464 static int 465 fw4_ack_handler(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 466 { 467 struct adapter *sc = iq->adapter; 468 const struct cpl_fw4_ack *cpl = (const void *)(rss + 1); 469 unsigned int tid = G_CPL_FW4_ACK_FLOWID(be32toh(OPCODE_TID(cpl))); 470 u_int cookie; 471 472 MPASS(m == NULL); 473 if (is_etid(sc, tid)) 474 cookie = CPL_COOKIE_ETHOFLD; 475 else 476 cookie = CPL_COOKIE_TOM; 477 478 return (fw4_ack_handlers[cookie](iq, rss, m)); 479 } 480 481 static void 482 t4_init_shared_cpl_handlers(void) 483 { 484 485 t4_register_cpl_handler(CPL_SET_TCB_RPL, set_tcb_rpl_handler); 486 t4_register_cpl_handler(CPL_L2T_WRITE_RPL, l2t_write_rpl_handler); 487 t4_register_cpl_handler(CPL_ACT_OPEN_RPL, act_open_rpl_handler); 488 t4_register_cpl_handler(CPL_ABORT_RPL_RSS, abort_rpl_rss_handler); 489 t4_register_cpl_handler(CPL_FW4_ACK, fw4_ack_handler); 490 } 491 492 void 493 t4_register_shared_cpl_handler(int opcode, cpl_handler_t h, int cookie) 494 { 495 uintptr_t *loc; 496 497 MPASS(opcode < nitems(t4_cpl_handler)); 498 MPASS(cookie > CPL_COOKIE_RESERVED); 499 MPASS(cookie < NUM_CPL_COOKIES); 500 MPASS(t4_cpl_handler[opcode] != NULL); 501 502 switch (opcode) { 503 case CPL_SET_TCB_RPL: 504 loc = (uintptr_t *)&set_tcb_rpl_handlers[cookie]; 505 break; 506 case CPL_L2T_WRITE_RPL: 507 loc = (uintptr_t *)&l2t_write_rpl_handlers[cookie]; 508 break; 509 case CPL_ACT_OPEN_RPL: 510 loc = (uintptr_t *)&act_open_rpl_handlers[cookie]; 511 break; 512 case CPL_ABORT_RPL_RSS: 513 loc = (uintptr_t *)&abort_rpl_rss_handlers[cookie]; 514 break; 515 case CPL_FW4_ACK: 516 loc = (uintptr_t *)&fw4_ack_handlers[cookie]; 517 break; 518 default: 519 MPASS(0); 520 return; 521 } 522 MPASS(h == NULL || *loc == (uintptr_t)NULL); 523 atomic_store_rel_ptr(loc, (uintptr_t)h); 524 } 525 526 /* 527 * Called on MOD_LOAD. Validates and calculates the SGE tunables. 528 */ 529 void 530 t4_sge_modload(void) 531 { 532 533 if (fl_pktshift < 0 || fl_pktshift > 7) { 534 printf("Invalid hw.cxgbe.fl_pktshift value (%d)," 535 " using 0 instead.\n", fl_pktshift); 536 fl_pktshift = 0; 537 } 538 539 if (spg_len != 64 && spg_len != 128) { 540 int len; 541 542 #if defined(__i386__) || defined(__amd64__) 543 len = cpu_clflush_line_size > 64 ? 128 : 64; 544 #else 545 len = 64; 546 #endif 547 if (spg_len != -1) { 548 printf("Invalid hw.cxgbe.spg_len value (%d)," 549 " using %d instead.\n", spg_len, len); 550 } 551 spg_len = len; 552 } 553 554 if (cong_drop < -1 || cong_drop > 1) { 555 printf("Invalid hw.cxgbe.cong_drop value (%d)," 556 " using 0 instead.\n", cong_drop); 557 cong_drop = 0; 558 } 559 560 if (tscale != 1 && (tscale < 3 || tscale > 17)) { 561 printf("Invalid hw.cxgbe.tscale value (%d)," 562 " using 1 instead.\n", tscale); 563 tscale = 1; 564 } 565 566 if (largest_rx_cluster != MCLBYTES && 567 #if MJUMPAGESIZE != MCLBYTES 568 largest_rx_cluster != MJUMPAGESIZE && 569 #endif 570 largest_rx_cluster != MJUM9BYTES && 571 largest_rx_cluster != MJUM16BYTES) { 572 printf("Invalid hw.cxgbe.largest_rx_cluster value (%d)," 573 " using %d instead.\n", largest_rx_cluster, MJUM16BYTES); 574 largest_rx_cluster = MJUM16BYTES; 575 } 576 577 if (safest_rx_cluster != MCLBYTES && 578 #if MJUMPAGESIZE != MCLBYTES 579 safest_rx_cluster != MJUMPAGESIZE && 580 #endif 581 safest_rx_cluster != MJUM9BYTES && 582 safest_rx_cluster != MJUM16BYTES) { 583 printf("Invalid hw.cxgbe.safest_rx_cluster value (%d)," 584 " using %d instead.\n", safest_rx_cluster, MJUMPAGESIZE); 585 safest_rx_cluster = MJUMPAGESIZE; 586 } 587 588 extfree_refs = counter_u64_alloc(M_WAITOK); 589 extfree_rels = counter_u64_alloc(M_WAITOK); 590 pullups = counter_u64_alloc(M_WAITOK); 591 defrags = counter_u64_alloc(M_WAITOK); 592 counter_u64_zero(extfree_refs); 593 counter_u64_zero(extfree_rels); 594 counter_u64_zero(pullups); 595 counter_u64_zero(defrags); 596 597 t4_init_shared_cpl_handlers(); 598 t4_register_cpl_handler(CPL_FW4_MSG, handle_fw_msg); 599 t4_register_cpl_handler(CPL_FW6_MSG, handle_fw_msg); 600 t4_register_cpl_handler(CPL_SGE_EGR_UPDATE, handle_sge_egr_update); 601 #ifdef RATELIMIT 602 t4_register_shared_cpl_handler(CPL_FW4_ACK, ethofld_fw4_ack, 603 CPL_COOKIE_ETHOFLD); 604 #endif 605 t4_register_fw_msg_handler(FW6_TYPE_CMD_RPL, t4_handle_fw_rpl); 606 t4_register_fw_msg_handler(FW6_TYPE_WRERR_RPL, t4_handle_wrerr_rpl); 607 } 608 609 void 610 t4_sge_modunload(void) 611 { 612 613 counter_u64_free(extfree_refs); 614 counter_u64_free(extfree_rels); 615 counter_u64_free(pullups); 616 counter_u64_free(defrags); 617 } 618 619 uint64_t 620 t4_sge_extfree_refs(void) 621 { 622 uint64_t refs, rels; 623 624 rels = counter_u64_fetch(extfree_rels); 625 refs = counter_u64_fetch(extfree_refs); 626 627 return (refs - rels); 628 } 629 630 /* max 4096 */ 631 #define MAX_PACK_BOUNDARY 512 632 633 static inline void 634 setup_pad_and_pack_boundaries(struct adapter *sc) 635 { 636 uint32_t v, m; 637 int pad, pack, pad_shift; 638 639 pad_shift = chip_id(sc) > CHELSIO_T5 ? X_T6_INGPADBOUNDARY_SHIFT : 640 X_INGPADBOUNDARY_SHIFT; 641 pad = fl_pad; 642 if (fl_pad < (1 << pad_shift) || 643 fl_pad > (1 << (pad_shift + M_INGPADBOUNDARY)) || 644 !powerof2(fl_pad)) { 645 /* 646 * If there is any chance that we might use buffer packing and 647 * the chip is a T4, then pick 64 as the pad/pack boundary. Set 648 * it to the minimum allowed in all other cases. 649 */ 650 pad = is_t4(sc) && buffer_packing ? 64 : 1 << pad_shift; 651 652 /* 653 * For fl_pad = 0 we'll still write a reasonable value to the 654 * register but all the freelists will opt out of padding. 655 * We'll complain here only if the user tried to set it to a 656 * value greater than 0 that was invalid. 657 */ 658 if (fl_pad > 0) { 659 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pad value" 660 " (%d), using %d instead.\n", fl_pad, pad); 661 } 662 } 663 m = V_INGPADBOUNDARY(M_INGPADBOUNDARY); 664 v = V_INGPADBOUNDARY(ilog2(pad) - pad_shift); 665 t4_set_reg_field(sc, A_SGE_CONTROL, m, v); 666 667 if (is_t4(sc)) { 668 if (fl_pack != -1 && fl_pack != pad) { 669 /* Complain but carry on. */ 670 device_printf(sc->dev, "hw.cxgbe.fl_pack (%d) ignored," 671 " using %d instead.\n", fl_pack, pad); 672 } 673 return; 674 } 675 676 pack = fl_pack; 677 if (fl_pack < 16 || fl_pack == 32 || fl_pack > 4096 || 678 !powerof2(fl_pack)) { 679 if (sc->params.pci.mps > MAX_PACK_BOUNDARY) 680 pack = MAX_PACK_BOUNDARY; 681 else 682 pack = max(sc->params.pci.mps, CACHE_LINE_SIZE); 683 MPASS(powerof2(pack)); 684 if (pack < 16) 685 pack = 16; 686 if (pack == 32) 687 pack = 64; 688 if (pack > 4096) 689 pack = 4096; 690 if (fl_pack != -1) { 691 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pack value" 692 " (%d), using %d instead.\n", fl_pack, pack); 693 } 694 } 695 m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY); 696 if (pack == 16) 697 v = V_INGPACKBOUNDARY(0); 698 else 699 v = V_INGPACKBOUNDARY(ilog2(pack) - 5); 700 701 MPASS(!is_t4(sc)); /* T4 doesn't have SGE_CONTROL2 */ 702 t4_set_reg_field(sc, A_SGE_CONTROL2, m, v); 703 } 704 705 /* 706 * adap->params.vpd.cclk must be set up before this is called. 707 */ 708 void 709 t4_tweak_chip_settings(struct adapter *sc) 710 { 711 int i, reg; 712 uint32_t v, m; 713 int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200}; 714 int timer_max = M_TIMERVALUE0 * 1000 / sc->params.vpd.cclk; 715 int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */ 716 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 717 static int sw_buf_sizes[] = { 718 MCLBYTES, 719 #if MJUMPAGESIZE != MCLBYTES 720 MJUMPAGESIZE, 721 #endif 722 MJUM9BYTES, 723 MJUM16BYTES 724 }; 725 726 KASSERT(sc->flags & MASTER_PF, 727 ("%s: trying to change chip settings when not master.", __func__)); 728 729 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE; 730 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE | 731 V_EGRSTATUSPAGESIZE(spg_len == 128); 732 t4_set_reg_field(sc, A_SGE_CONTROL, m, v); 733 734 setup_pad_and_pack_boundaries(sc); 735 736 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) | 737 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) | 738 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) | 739 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) | 740 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) | 741 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) | 742 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) | 743 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10); 744 t4_write_reg(sc, A_SGE_HOST_PAGE_SIZE, v); 745 746 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0, 4096); 747 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE1, 65536); 748 reg = A_SGE_FL_BUFFER_SIZE2; 749 for (i = 0; i < nitems(sw_buf_sizes); i++) { 750 MPASS(reg <= A_SGE_FL_BUFFER_SIZE15); 751 t4_write_reg(sc, reg, sw_buf_sizes[i]); 752 reg += 4; 753 MPASS(reg <= A_SGE_FL_BUFFER_SIZE15); 754 t4_write_reg(sc, reg, sw_buf_sizes[i] - CL_METADATA_SIZE); 755 reg += 4; 756 } 757 758 v = V_THRESHOLD_0(intr_pktcount[0]) | V_THRESHOLD_1(intr_pktcount[1]) | 759 V_THRESHOLD_2(intr_pktcount[2]) | V_THRESHOLD_3(intr_pktcount[3]); 760 t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD, v); 761 762 KASSERT(intr_timer[0] <= timer_max, 763 ("%s: not a single usable timer (%d, %d)", __func__, intr_timer[0], 764 timer_max)); 765 for (i = 1; i < nitems(intr_timer); i++) { 766 KASSERT(intr_timer[i] >= intr_timer[i - 1], 767 ("%s: timers not listed in increasing order (%d)", 768 __func__, i)); 769 770 while (intr_timer[i] > timer_max) { 771 if (i == nitems(intr_timer) - 1) { 772 intr_timer[i] = timer_max; 773 break; 774 } 775 intr_timer[i] += intr_timer[i - 1]; 776 intr_timer[i] /= 2; 777 } 778 } 779 780 v = V_TIMERVALUE0(us_to_core_ticks(sc, intr_timer[0])) | 781 V_TIMERVALUE1(us_to_core_ticks(sc, intr_timer[1])); 782 t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1, v); 783 v = V_TIMERVALUE2(us_to_core_ticks(sc, intr_timer[2])) | 784 V_TIMERVALUE3(us_to_core_ticks(sc, intr_timer[3])); 785 t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3, v); 786 v = V_TIMERVALUE4(us_to_core_ticks(sc, intr_timer[4])) | 787 V_TIMERVALUE5(us_to_core_ticks(sc, intr_timer[5])); 788 t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5, v); 789 790 if (chip_id(sc) >= CHELSIO_T6) { 791 m = V_TSCALE(M_TSCALE); 792 if (tscale == 1) 793 v = 0; 794 else 795 v = V_TSCALE(tscale - 2); 796 t4_set_reg_field(sc, A_SGE_ITP_CONTROL, m, v); 797 798 if (sc->debug_flags & DF_DISABLE_TCB_CACHE) { 799 m = V_RDTHRESHOLD(M_RDTHRESHOLD) | F_WRTHRTHRESHEN | 800 V_WRTHRTHRESH(M_WRTHRTHRESH); 801 t4_tp_pio_read(sc, &v, 1, A_TP_CMM_CONFIG, 1); 802 v &= ~m; 803 v |= V_RDTHRESHOLD(1) | F_WRTHRTHRESHEN | 804 V_WRTHRTHRESH(16); 805 t4_tp_pio_write(sc, &v, 1, A_TP_CMM_CONFIG, 1); 806 } 807 } 808 809 /* 4K, 16K, 64K, 256K DDP "page sizes" for TDDP */ 810 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 811 t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, v); 812 813 /* 814 * 4K, 8K, 16K, 64K DDP "page sizes" for iSCSI DDP. These have been 815 * chosen with MAXPHYS = 128K in mind. The largest DDP buffer that we 816 * may have to deal with is MAXPHYS + 1 page. 817 */ 818 v = V_HPZ0(0) | V_HPZ1(1) | V_HPZ2(2) | V_HPZ3(4); 819 t4_write_reg(sc, A_ULP_RX_ISCSI_PSZ, v); 820 821 /* We use multiple DDP page sizes both in plain-TOE and ISCSI modes. */ 822 m = v = F_TDDPTAGTCB | F_ISCSITAGTCB; 823 t4_set_reg_field(sc, A_ULP_RX_CTL, m, v); 824 825 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 826 F_RESETDDPOFFSET; 827 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 828 t4_set_reg_field(sc, A_TP_PARA_REG5, m, v); 829 } 830 831 /* 832 * SGE wants the buffer to be at least 64B and then a multiple of 16. Its 833 * address mut be 16B aligned. If padding is in use the buffer's start and end 834 * need to be aligned to the pad boundary as well. We'll just make sure that 835 * the size is a multiple of the pad boundary here, it is up to the buffer 836 * allocation code to make sure the start of the buffer is aligned. 837 */ 838 static inline int 839 hwsz_ok(struct adapter *sc, int hwsz) 840 { 841 int mask = fl_pad ? sc->params.sge.pad_boundary - 1 : 16 - 1; 842 843 return (hwsz >= 64 && (hwsz & mask) == 0); 844 } 845 846 /* 847 * Initialize the rx buffer sizes and figure out which zones the buffers will 848 * be allocated from. 849 */ 850 void 851 t4_init_rx_buf_info(struct adapter *sc) 852 { 853 struct sge *s = &sc->sge; 854 struct sge_params *sp = &sc->params.sge; 855 int i, j, n; 856 static int sw_buf_sizes[] = { /* Sorted by size */ 857 MCLBYTES, 858 #if MJUMPAGESIZE != MCLBYTES 859 MJUMPAGESIZE, 860 #endif 861 MJUM9BYTES, 862 MJUM16BYTES 863 }; 864 struct rx_buf_info *rxb; 865 866 s->safe_zidx = -1; 867 rxb = &s->rx_buf_info[0]; 868 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) { 869 rxb->size1 = sw_buf_sizes[i]; 870 rxb->zone = m_getzone(rxb->size1); 871 rxb->type = m_gettype(rxb->size1); 872 rxb->size2 = 0; 873 rxb->hwidx1 = -1; 874 rxb->hwidx2 = -1; 875 for (j = 0; j < SGE_FLBUF_SIZES; j++) { 876 int hwsize = sp->sge_fl_buffer_size[j]; 877 878 if (!hwsz_ok(sc, hwsize)) 879 continue; 880 881 /* hwidx for size1 */ 882 if (rxb->hwidx1 == -1 && rxb->size1 == hwsize) 883 rxb->hwidx1 = j; 884 885 /* hwidx for size2 (buffer packing) */ 886 if (rxb->size1 - CL_METADATA_SIZE < hwsize) 887 continue; 888 n = rxb->size1 - hwsize - CL_METADATA_SIZE; 889 if (n == 0) { 890 rxb->hwidx2 = j; 891 rxb->size2 = hwsize; 892 break; /* stop looking */ 893 } 894 if (rxb->hwidx2 != -1) { 895 if (n < sp->sge_fl_buffer_size[rxb->hwidx2] - 896 hwsize - CL_METADATA_SIZE) { 897 rxb->hwidx2 = j; 898 rxb->size2 = hwsize; 899 } 900 } else if (n <= 2 * CL_METADATA_SIZE) { 901 rxb->hwidx2 = j; 902 rxb->size2 = hwsize; 903 } 904 } 905 if (rxb->hwidx2 != -1) 906 sc->flags |= BUF_PACKING_OK; 907 if (s->safe_zidx == -1 && rxb->size1 == safest_rx_cluster) 908 s->safe_zidx = i; 909 } 910 } 911 912 /* 913 * Verify some basic SGE settings for the PF and VF driver, and other 914 * miscellaneous settings for the PF driver. 915 */ 916 int 917 t4_verify_chip_settings(struct adapter *sc) 918 { 919 struct sge_params *sp = &sc->params.sge; 920 uint32_t m, v, r; 921 int rc = 0; 922 const uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 923 924 m = F_RXPKTCPLMODE; 925 v = F_RXPKTCPLMODE; 926 r = sp->sge_control; 927 if ((r & m) != v) { 928 device_printf(sc->dev, "invalid SGE_CONTROL(0x%x)\n", r); 929 rc = EINVAL; 930 } 931 932 /* 933 * If this changes then every single use of PAGE_SHIFT in the driver 934 * needs to be carefully reviewed for PAGE_SHIFT vs sp->page_shift. 935 */ 936 if (sp->page_shift != PAGE_SHIFT) { 937 device_printf(sc->dev, "invalid SGE_HOST_PAGE_SIZE(0x%x)\n", r); 938 rc = EINVAL; 939 } 940 941 if (sc->flags & IS_VF) 942 return (0); 943 944 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 945 r = t4_read_reg(sc, A_ULP_RX_TDDP_PSZ); 946 if (r != v) { 947 device_printf(sc->dev, "invalid ULP_RX_TDDP_PSZ(0x%x)\n", r); 948 if (sc->vres.ddp.size != 0) 949 rc = EINVAL; 950 } 951 952 m = v = F_TDDPTAGTCB; 953 r = t4_read_reg(sc, A_ULP_RX_CTL); 954 if ((r & m) != v) { 955 device_printf(sc->dev, "invalid ULP_RX_CTL(0x%x)\n", r); 956 if (sc->vres.ddp.size != 0) 957 rc = EINVAL; 958 } 959 960 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 961 F_RESETDDPOFFSET; 962 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 963 r = t4_read_reg(sc, A_TP_PARA_REG5); 964 if ((r & m) != v) { 965 device_printf(sc->dev, "invalid TP_PARA_REG5(0x%x)\n", r); 966 if (sc->vres.ddp.size != 0) 967 rc = EINVAL; 968 } 969 970 return (rc); 971 } 972 973 int 974 t4_create_dma_tag(struct adapter *sc) 975 { 976 int rc; 977 978 rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0, 979 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE, 980 BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL, 981 NULL, &sc->dmat); 982 if (rc != 0) { 983 device_printf(sc->dev, 984 "failed to create main DMA tag: %d\n", rc); 985 } 986 987 return (rc); 988 } 989 990 void 991 t4_sge_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx, 992 struct sysctl_oid_list *children) 993 { 994 struct sge_params *sp = &sc->params.sge; 995 996 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "buffer_sizes", 997 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 998 sysctl_bufsizes, "A", "freelist buffer sizes"); 999 1000 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pktshift", CTLFLAG_RD, 1001 NULL, sp->fl_pktshift, "payload DMA offset in rx buffer (bytes)"); 1002 1003 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pad", CTLFLAG_RD, 1004 NULL, sp->pad_boundary, "payload pad boundary (bytes)"); 1005 1006 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "spg_len", CTLFLAG_RD, 1007 NULL, sp->spg_len, "status page size (bytes)"); 1008 1009 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_drop", CTLFLAG_RD, 1010 NULL, cong_drop, "congestion drop setting"); 1011 1012 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pack", CTLFLAG_RD, 1013 NULL, sp->pack_boundary, "payload pack boundary (bytes)"); 1014 } 1015 1016 int 1017 t4_destroy_dma_tag(struct adapter *sc) 1018 { 1019 if (sc->dmat) 1020 bus_dma_tag_destroy(sc->dmat); 1021 1022 return (0); 1023 } 1024 1025 /* 1026 * Allocate and initialize the firmware event queue, control queues, and special 1027 * purpose rx queues owned by the adapter. 1028 * 1029 * Returns errno on failure. Resources allocated up to that point may still be 1030 * allocated. Caller is responsible for cleanup in case this function fails. 1031 */ 1032 int 1033 t4_setup_adapter_queues(struct adapter *sc) 1034 { 1035 int rc, i; 1036 1037 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 1038 1039 /* 1040 * Firmware event queue 1041 */ 1042 rc = alloc_fwq(sc); 1043 if (rc != 0) 1044 return (rc); 1045 1046 /* 1047 * That's all for the VF driver. 1048 */ 1049 if (sc->flags & IS_VF) 1050 return (rc); 1051 1052 /* 1053 * XXX: General purpose rx queues, one per port. 1054 */ 1055 1056 /* 1057 * Control queues, one per port. 1058 */ 1059 for_each_port(sc, i) { 1060 rc = alloc_ctrlq(sc, i); 1061 if (rc != 0) 1062 return (rc); 1063 } 1064 1065 return (rc); 1066 } 1067 1068 /* 1069 * Idempotent 1070 */ 1071 int 1072 t4_teardown_adapter_queues(struct adapter *sc) 1073 { 1074 int i; 1075 1076 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 1077 1078 if (!(sc->flags & IS_VF)) { 1079 for_each_port(sc, i) 1080 free_ctrlq(sc, i); 1081 } 1082 free_fwq(sc); 1083 1084 return (0); 1085 } 1086 1087 /* Maximum payload that could arrive with a single iq descriptor. */ 1088 static inline int 1089 max_rx_payload(struct adapter *sc, struct ifnet *ifp, const bool ofld) 1090 { 1091 int maxp; 1092 1093 /* large enough even when hw VLAN extraction is disabled */ 1094 maxp = sc->params.sge.fl_pktshift + ETHER_HDR_LEN + 1095 ETHER_VLAN_ENCAP_LEN + ifp->if_mtu; 1096 if (ofld && sc->tt.tls && sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS && 1097 maxp < sc->params.tp.max_rx_pdu) 1098 maxp = sc->params.tp.max_rx_pdu; 1099 return (maxp); 1100 } 1101 1102 int 1103 t4_setup_vi_queues(struct vi_info *vi) 1104 { 1105 int rc = 0, i, intr_idx; 1106 struct sge_rxq *rxq; 1107 struct sge_txq *txq; 1108 #ifdef TCP_OFFLOAD 1109 struct sge_ofld_rxq *ofld_rxq; 1110 #endif 1111 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1112 struct sge_ofld_txq *ofld_txq; 1113 #endif 1114 #ifdef DEV_NETMAP 1115 int saved_idx, iqidx; 1116 struct sge_nm_rxq *nm_rxq; 1117 struct sge_nm_txq *nm_txq; 1118 #endif 1119 struct adapter *sc = vi->adapter; 1120 struct ifnet *ifp = vi->ifp; 1121 int maxp; 1122 1123 /* Interrupt vector to start from (when using multiple vectors) */ 1124 intr_idx = vi->first_intr; 1125 1126 #ifdef DEV_NETMAP 1127 saved_idx = intr_idx; 1128 if (ifp->if_capabilities & IFCAP_NETMAP) { 1129 1130 /* netmap is supported with direct interrupts only. */ 1131 MPASS(!forwarding_intr_to_fwq(sc)); 1132 MPASS(vi->first_intr >= 0); 1133 1134 /* 1135 * We don't have buffers to back the netmap rx queues 1136 * right now so we create the queues in a way that 1137 * doesn't set off any congestion signal in the chip. 1138 */ 1139 for_each_nm_rxq(vi, i, nm_rxq) { 1140 rc = alloc_nm_rxq(vi, nm_rxq, intr_idx, i); 1141 if (rc != 0) 1142 goto done; 1143 intr_idx++; 1144 } 1145 1146 for_each_nm_txq(vi, i, nm_txq) { 1147 iqidx = vi->first_nm_rxq + (i % vi->nnmrxq); 1148 rc = alloc_nm_txq(vi, nm_txq, iqidx, i); 1149 if (rc != 0) 1150 goto done; 1151 } 1152 } 1153 1154 /* Normal rx queues and netmap rx queues share the same interrupts. */ 1155 intr_idx = saved_idx; 1156 #endif 1157 1158 /* 1159 * Allocate rx queues first because a default iqid is required when 1160 * creating a tx queue. 1161 */ 1162 maxp = max_rx_payload(sc, ifp, false); 1163 for_each_rxq(vi, i, rxq) { 1164 rc = alloc_rxq(vi, rxq, i, intr_idx, maxp); 1165 if (rc != 0) 1166 goto done; 1167 if (!forwarding_intr_to_fwq(sc)) 1168 intr_idx++; 1169 } 1170 #ifdef DEV_NETMAP 1171 if (ifp->if_capabilities & IFCAP_NETMAP) 1172 intr_idx = saved_idx + max(vi->nrxq, vi->nnmrxq); 1173 #endif 1174 #ifdef TCP_OFFLOAD 1175 maxp = max_rx_payload(sc, ifp, true); 1176 for_each_ofld_rxq(vi, i, ofld_rxq) { 1177 rc = alloc_ofld_rxq(vi, ofld_rxq, i, intr_idx, maxp); 1178 if (rc != 0) 1179 goto done; 1180 if (!forwarding_intr_to_fwq(sc)) 1181 intr_idx++; 1182 } 1183 #endif 1184 1185 /* 1186 * Now the tx queues. 1187 */ 1188 for_each_txq(vi, i, txq) { 1189 rc = alloc_txq(vi, txq, i); 1190 if (rc != 0) 1191 goto done; 1192 } 1193 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1194 for_each_ofld_txq(vi, i, ofld_txq) { 1195 rc = alloc_ofld_txq(vi, ofld_txq, i); 1196 if (rc != 0) 1197 goto done; 1198 } 1199 #endif 1200 done: 1201 if (rc) 1202 t4_teardown_vi_queues(vi); 1203 1204 return (rc); 1205 } 1206 1207 /* 1208 * Idempotent 1209 */ 1210 int 1211 t4_teardown_vi_queues(struct vi_info *vi) 1212 { 1213 int i; 1214 struct sge_rxq *rxq; 1215 struct sge_txq *txq; 1216 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1217 struct sge_ofld_txq *ofld_txq; 1218 #endif 1219 #ifdef TCP_OFFLOAD 1220 struct sge_ofld_rxq *ofld_rxq; 1221 #endif 1222 #ifdef DEV_NETMAP 1223 struct sge_nm_rxq *nm_rxq; 1224 struct sge_nm_txq *nm_txq; 1225 #endif 1226 1227 #ifdef DEV_NETMAP 1228 if (vi->ifp->if_capabilities & IFCAP_NETMAP) { 1229 for_each_nm_txq(vi, i, nm_txq) { 1230 free_nm_txq(vi, nm_txq); 1231 } 1232 1233 for_each_nm_rxq(vi, i, nm_rxq) { 1234 free_nm_rxq(vi, nm_rxq); 1235 } 1236 } 1237 #endif 1238 1239 /* 1240 * Take down all the tx queues first, as they reference the rx queues 1241 * (for egress updates, etc.). 1242 */ 1243 1244 for_each_txq(vi, i, txq) { 1245 free_txq(vi, txq); 1246 } 1247 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1248 for_each_ofld_txq(vi, i, ofld_txq) { 1249 free_ofld_txq(vi, ofld_txq); 1250 } 1251 #endif 1252 1253 /* 1254 * Then take down the rx queues. 1255 */ 1256 1257 for_each_rxq(vi, i, rxq) { 1258 free_rxq(vi, rxq); 1259 } 1260 #ifdef TCP_OFFLOAD 1261 for_each_ofld_rxq(vi, i, ofld_rxq) { 1262 free_ofld_rxq(vi, ofld_rxq); 1263 } 1264 #endif 1265 1266 return (0); 1267 } 1268 1269 /* 1270 * Interrupt handler when the driver is using only 1 interrupt. This is a very 1271 * unusual scenario. 1272 * 1273 * a) Deals with errors, if any. 1274 * b) Services firmware event queue, which is taking interrupts for all other 1275 * queues. 1276 */ 1277 void 1278 t4_intr_all(void *arg) 1279 { 1280 struct adapter *sc = arg; 1281 struct sge_iq *fwq = &sc->sge.fwq; 1282 1283 MPASS(sc->intr_count == 1); 1284 1285 if (sc->intr_type == INTR_INTX) 1286 t4_write_reg(sc, MYPF_REG(A_PCIE_PF_CLI), 0); 1287 1288 t4_intr_err(arg); 1289 t4_intr_evt(fwq); 1290 } 1291 1292 /* 1293 * Interrupt handler for errors (installed directly when multiple interrupts are 1294 * being used, or called by t4_intr_all). 1295 */ 1296 void 1297 t4_intr_err(void *arg) 1298 { 1299 struct adapter *sc = arg; 1300 uint32_t v; 1301 const bool verbose = (sc->debug_flags & DF_VERBOSE_SLOWINTR) != 0; 1302 1303 if (sc->flags & ADAP_ERR) 1304 return; 1305 1306 v = t4_read_reg(sc, MYPF_REG(A_PL_PF_INT_CAUSE)); 1307 if (v & F_PFSW) { 1308 sc->swintr++; 1309 t4_write_reg(sc, MYPF_REG(A_PL_PF_INT_CAUSE), v); 1310 } 1311 1312 t4_slow_intr_handler(sc, verbose); 1313 } 1314 1315 /* 1316 * Interrupt handler for iq-only queues. The firmware event queue is the only 1317 * such queue right now. 1318 */ 1319 void 1320 t4_intr_evt(void *arg) 1321 { 1322 struct sge_iq *iq = arg; 1323 1324 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 1325 service_iq(iq, 0); 1326 (void) atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 1327 } 1328 } 1329 1330 /* 1331 * Interrupt handler for iq+fl queues. 1332 */ 1333 void 1334 t4_intr(void *arg) 1335 { 1336 struct sge_iq *iq = arg; 1337 1338 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 1339 service_iq_fl(iq, 0); 1340 (void) atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 1341 } 1342 } 1343 1344 #ifdef DEV_NETMAP 1345 /* 1346 * Interrupt handler for netmap rx queues. 1347 */ 1348 void 1349 t4_nm_intr(void *arg) 1350 { 1351 struct sge_nm_rxq *nm_rxq = arg; 1352 1353 if (atomic_cmpset_int(&nm_rxq->nm_state, NM_ON, NM_BUSY)) { 1354 service_nm_rxq(nm_rxq); 1355 (void) atomic_cmpset_int(&nm_rxq->nm_state, NM_BUSY, NM_ON); 1356 } 1357 } 1358 1359 /* 1360 * Interrupt handler for vectors shared between NIC and netmap rx queues. 1361 */ 1362 void 1363 t4_vi_intr(void *arg) 1364 { 1365 struct irq *irq = arg; 1366 1367 MPASS(irq->nm_rxq != NULL); 1368 t4_nm_intr(irq->nm_rxq); 1369 1370 MPASS(irq->rxq != NULL); 1371 t4_intr(irq->rxq); 1372 } 1373 #endif 1374 1375 /* 1376 * Deals with interrupts on an iq-only (no freelist) queue. 1377 */ 1378 static int 1379 service_iq(struct sge_iq *iq, int budget) 1380 { 1381 struct sge_iq *q; 1382 struct adapter *sc = iq->adapter; 1383 struct iq_desc *d = &iq->desc[iq->cidx]; 1384 int ndescs = 0, limit; 1385 int rsp_type; 1386 uint32_t lq; 1387 STAILQ_HEAD(, sge_iq) iql = STAILQ_HEAD_INITIALIZER(iql); 1388 1389 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq)); 1390 KASSERT((iq->flags & IQ_HAS_FL) == 0, 1391 ("%s: called for iq %p with fl (iq->flags 0x%x)", __func__, iq, 1392 iq->flags)); 1393 MPASS((iq->flags & IQ_ADJ_CREDIT) == 0); 1394 MPASS((iq->flags & IQ_LRO_ENABLED) == 0); 1395 1396 limit = budget ? budget : iq->qsize / 16; 1397 1398 /* 1399 * We always come back and check the descriptor ring for new indirect 1400 * interrupts and other responses after running a single handler. 1401 */ 1402 for (;;) { 1403 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) { 1404 1405 rmb(); 1406 1407 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen); 1408 lq = be32toh(d->rsp.pldbuflen_qid); 1409 1410 switch (rsp_type) { 1411 case X_RSPD_TYPE_FLBUF: 1412 panic("%s: data for an iq (%p) with no freelist", 1413 __func__, iq); 1414 1415 /* NOTREACHED */ 1416 1417 case X_RSPD_TYPE_CPL: 1418 KASSERT(d->rss.opcode < NUM_CPL_CMDS, 1419 ("%s: bad opcode %02x.", __func__, 1420 d->rss.opcode)); 1421 t4_cpl_handler[d->rss.opcode](iq, &d->rss, NULL); 1422 break; 1423 1424 case X_RSPD_TYPE_INTR: 1425 /* 1426 * There are 1K interrupt-capable queues (qids 0 1427 * through 1023). A response type indicating a 1428 * forwarded interrupt with a qid >= 1K is an 1429 * iWARP async notification. 1430 */ 1431 if (__predict_true(lq >= 1024)) { 1432 t4_an_handler(iq, &d->rsp); 1433 break; 1434 } 1435 1436 q = sc->sge.iqmap[lq - sc->sge.iq_start - 1437 sc->sge.iq_base]; 1438 if (atomic_cmpset_int(&q->state, IQS_IDLE, 1439 IQS_BUSY)) { 1440 if (service_iq_fl(q, q->qsize / 16) == 0) { 1441 (void) atomic_cmpset_int(&q->state, 1442 IQS_BUSY, IQS_IDLE); 1443 } else { 1444 STAILQ_INSERT_TAIL(&iql, q, 1445 link); 1446 } 1447 } 1448 break; 1449 1450 default: 1451 KASSERT(0, 1452 ("%s: illegal response type %d on iq %p", 1453 __func__, rsp_type, iq)); 1454 log(LOG_ERR, 1455 "%s: illegal response type %d on iq %p", 1456 device_get_nameunit(sc->dev), rsp_type, iq); 1457 break; 1458 } 1459 1460 d++; 1461 if (__predict_false(++iq->cidx == iq->sidx)) { 1462 iq->cidx = 0; 1463 iq->gen ^= F_RSPD_GEN; 1464 d = &iq->desc[0]; 1465 } 1466 if (__predict_false(++ndescs == limit)) { 1467 t4_write_reg(sc, sc->sge_gts_reg, 1468 V_CIDXINC(ndescs) | 1469 V_INGRESSQID(iq->cntxt_id) | 1470 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); 1471 ndescs = 0; 1472 1473 if (budget) { 1474 return (EINPROGRESS); 1475 } 1476 } 1477 } 1478 1479 if (STAILQ_EMPTY(&iql)) 1480 break; 1481 1482 /* 1483 * Process the head only, and send it to the back of the list if 1484 * it's still not done. 1485 */ 1486 q = STAILQ_FIRST(&iql); 1487 STAILQ_REMOVE_HEAD(&iql, link); 1488 if (service_iq_fl(q, q->qsize / 8) == 0) 1489 (void) atomic_cmpset_int(&q->state, IQS_BUSY, IQS_IDLE); 1490 else 1491 STAILQ_INSERT_TAIL(&iql, q, link); 1492 } 1493 1494 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) | 1495 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params)); 1496 1497 return (0); 1498 } 1499 1500 static inline int 1501 sort_before_lro(struct lro_ctrl *lro) 1502 { 1503 1504 return (lro->lro_mbuf_max != 0); 1505 } 1506 1507 static inline uint64_t 1508 last_flit_to_ns(struct adapter *sc, uint64_t lf) 1509 { 1510 uint64_t n = be64toh(lf) & 0xfffffffffffffff; /* 60b, not 64b. */ 1511 1512 if (n > UINT64_MAX / 1000000) 1513 return (n / sc->params.vpd.cclk * 1000000); 1514 else 1515 return (n * 1000000 / sc->params.vpd.cclk); 1516 } 1517 1518 static inline void 1519 move_to_next_rxbuf(struct sge_fl *fl) 1520 { 1521 1522 fl->rx_offset = 0; 1523 if (__predict_false((++fl->cidx & 7) == 0)) { 1524 uint16_t cidx = fl->cidx >> 3; 1525 1526 if (__predict_false(cidx == fl->sidx)) 1527 fl->cidx = cidx = 0; 1528 fl->hw_cidx = cidx; 1529 } 1530 } 1531 1532 /* 1533 * Deals with interrupts on an iq+fl queue. 1534 */ 1535 static int 1536 service_iq_fl(struct sge_iq *iq, int budget) 1537 { 1538 struct sge_rxq *rxq = iq_to_rxq(iq); 1539 struct sge_fl *fl; 1540 struct adapter *sc = iq->adapter; 1541 struct iq_desc *d = &iq->desc[iq->cidx]; 1542 int ndescs, limit; 1543 int rsp_type, starved; 1544 uint32_t lq; 1545 uint16_t fl_hw_cidx; 1546 struct mbuf *m0; 1547 #if defined(INET) || defined(INET6) 1548 const struct timeval lro_timeout = {0, sc->lro_timeout}; 1549 struct lro_ctrl *lro = &rxq->lro; 1550 #endif 1551 1552 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq)); 1553 MPASS(iq->flags & IQ_HAS_FL); 1554 1555 ndescs = 0; 1556 #if defined(INET) || defined(INET6) 1557 if (iq->flags & IQ_ADJ_CREDIT) { 1558 MPASS(sort_before_lro(lro)); 1559 iq->flags &= ~IQ_ADJ_CREDIT; 1560 if ((d->rsp.u.type_gen & F_RSPD_GEN) != iq->gen) { 1561 tcp_lro_flush_all(lro); 1562 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(1) | 1563 V_INGRESSQID((u32)iq->cntxt_id) | 1564 V_SEINTARM(iq->intr_params)); 1565 return (0); 1566 } 1567 ndescs = 1; 1568 } 1569 #else 1570 MPASS((iq->flags & IQ_ADJ_CREDIT) == 0); 1571 #endif 1572 1573 limit = budget ? budget : iq->qsize / 16; 1574 fl = &rxq->fl; 1575 fl_hw_cidx = fl->hw_cidx; /* stable snapshot */ 1576 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) { 1577 1578 rmb(); 1579 1580 m0 = NULL; 1581 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen); 1582 lq = be32toh(d->rsp.pldbuflen_qid); 1583 1584 switch (rsp_type) { 1585 case X_RSPD_TYPE_FLBUF: 1586 if (lq & F_RSPD_NEWBUF) { 1587 if (fl->rx_offset > 0) 1588 move_to_next_rxbuf(fl); 1589 lq = G_RSPD_LEN(lq); 1590 } 1591 if (IDXDIFF(fl->hw_cidx, fl_hw_cidx, fl->sidx) > 4) { 1592 FL_LOCK(fl); 1593 refill_fl(sc, fl, 64); 1594 FL_UNLOCK(fl); 1595 fl_hw_cidx = fl->hw_cidx; 1596 } 1597 1598 if (d->rss.opcode == CPL_RX_PKT) { 1599 if (__predict_true(eth_rx(sc, rxq, d, lq) == 0)) 1600 break; 1601 goto out; 1602 } 1603 m0 = get_fl_payload(sc, fl, lq); 1604 if (__predict_false(m0 == NULL)) 1605 goto out; 1606 1607 /* fall through */ 1608 1609 case X_RSPD_TYPE_CPL: 1610 KASSERT(d->rss.opcode < NUM_CPL_CMDS, 1611 ("%s: bad opcode %02x.", __func__, d->rss.opcode)); 1612 t4_cpl_handler[d->rss.opcode](iq, &d->rss, m0); 1613 break; 1614 1615 case X_RSPD_TYPE_INTR: 1616 1617 /* 1618 * There are 1K interrupt-capable queues (qids 0 1619 * through 1023). A response type indicating a 1620 * forwarded interrupt with a qid >= 1K is an 1621 * iWARP async notification. That is the only 1622 * acceptable indirect interrupt on this queue. 1623 */ 1624 if (__predict_false(lq < 1024)) { 1625 panic("%s: indirect interrupt on iq_fl %p " 1626 "with qid %u", __func__, iq, lq); 1627 } 1628 1629 t4_an_handler(iq, &d->rsp); 1630 break; 1631 1632 default: 1633 KASSERT(0, ("%s: illegal response type %d on iq %p", 1634 __func__, rsp_type, iq)); 1635 log(LOG_ERR, "%s: illegal response type %d on iq %p", 1636 device_get_nameunit(sc->dev), rsp_type, iq); 1637 break; 1638 } 1639 1640 d++; 1641 if (__predict_false(++iq->cidx == iq->sidx)) { 1642 iq->cidx = 0; 1643 iq->gen ^= F_RSPD_GEN; 1644 d = &iq->desc[0]; 1645 } 1646 if (__predict_false(++ndescs == limit)) { 1647 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) | 1648 V_INGRESSQID(iq->cntxt_id) | 1649 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); 1650 1651 #if defined(INET) || defined(INET6) 1652 if (iq->flags & IQ_LRO_ENABLED && 1653 !sort_before_lro(lro) && 1654 sc->lro_timeout != 0) { 1655 tcp_lro_flush_inactive(lro, &lro_timeout); 1656 } 1657 #endif 1658 if (budget) 1659 return (EINPROGRESS); 1660 ndescs = 0; 1661 } 1662 } 1663 out: 1664 #if defined(INET) || defined(INET6) 1665 if (iq->flags & IQ_LRO_ENABLED) { 1666 if (ndescs > 0 && lro->lro_mbuf_count > 8) { 1667 MPASS(sort_before_lro(lro)); 1668 /* hold back one credit and don't flush LRO state */ 1669 iq->flags |= IQ_ADJ_CREDIT; 1670 ndescs--; 1671 } else { 1672 tcp_lro_flush_all(lro); 1673 } 1674 } 1675 #endif 1676 1677 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) | 1678 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params)); 1679 1680 FL_LOCK(fl); 1681 starved = refill_fl(sc, fl, 64); 1682 FL_UNLOCK(fl); 1683 if (__predict_false(starved != 0)) 1684 add_fl_to_sfl(sc, fl); 1685 1686 return (0); 1687 } 1688 1689 static inline struct cluster_metadata * 1690 cl_metadata(struct fl_sdesc *sd) 1691 { 1692 1693 return ((void *)(sd->cl + sd->moff)); 1694 } 1695 1696 static void 1697 rxb_free(struct mbuf *m) 1698 { 1699 struct cluster_metadata *clm = m->m_ext.ext_arg1; 1700 1701 uma_zfree(clm->zone, clm->cl); 1702 counter_u64_add(extfree_rels, 1); 1703 } 1704 1705 /* 1706 * The mbuf returned comes from zone_muf and carries the payload in one of these 1707 * ways 1708 * a) complete frame inside the mbuf 1709 * b) m_cljset (for clusters without metadata) 1710 * d) m_extaddref (cluster with metadata) 1711 */ 1712 static struct mbuf * 1713 get_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset, 1714 int remaining) 1715 { 1716 struct mbuf *m; 1717 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 1718 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[sd->zidx]; 1719 struct cluster_metadata *clm; 1720 int len, blen; 1721 caddr_t payload; 1722 1723 if (fl->flags & FL_BUF_PACKING) { 1724 u_int l, pad; 1725 1726 blen = rxb->size2 - fl->rx_offset; /* max possible in this buf */ 1727 len = min(remaining, blen); 1728 payload = sd->cl + fl->rx_offset; 1729 1730 l = fr_offset + len; 1731 pad = roundup2(l, fl->buf_boundary) - l; 1732 if (fl->rx_offset + len + pad < rxb->size2) 1733 blen = len + pad; 1734 MPASS(fl->rx_offset + blen <= rxb->size2); 1735 } else { 1736 MPASS(fl->rx_offset == 0); /* not packing */ 1737 blen = rxb->size1; 1738 len = min(remaining, blen); 1739 payload = sd->cl; 1740 } 1741 1742 if (fr_offset == 0) { 1743 m = m_gethdr(M_NOWAIT, MT_DATA); 1744 if (__predict_false(m == NULL)) 1745 return (NULL); 1746 m->m_pkthdr.len = remaining; 1747 } else { 1748 m = m_get(M_NOWAIT, MT_DATA); 1749 if (__predict_false(m == NULL)) 1750 return (NULL); 1751 } 1752 m->m_len = len; 1753 1754 if (sc->sc_do_rxcopy && len < RX_COPY_THRESHOLD) { 1755 /* copy data to mbuf */ 1756 bcopy(payload, mtod(m, caddr_t), len); 1757 if (fl->flags & FL_BUF_PACKING) { 1758 fl->rx_offset += blen; 1759 MPASS(fl->rx_offset <= rxb->size2); 1760 if (fl->rx_offset < rxb->size2) 1761 return (m); /* without advancing the cidx */ 1762 } 1763 } else if (fl->flags & FL_BUF_PACKING) { 1764 clm = cl_metadata(sd); 1765 if (sd->nmbuf++ == 0) { 1766 clm->refcount = 1; 1767 clm->zone = rxb->zone; 1768 clm->cl = sd->cl; 1769 counter_u64_add(extfree_refs, 1); 1770 } 1771 m_extaddref(m, payload, blen, &clm->refcount, rxb_free, clm, 1772 NULL); 1773 1774 fl->rx_offset += blen; 1775 MPASS(fl->rx_offset <= rxb->size2); 1776 if (fl->rx_offset < rxb->size2) 1777 return (m); /* without advancing the cidx */ 1778 } else { 1779 m_cljset(m, sd->cl, rxb->type); 1780 sd->cl = NULL; /* consumed, not a recycle candidate */ 1781 } 1782 1783 move_to_next_rxbuf(fl); 1784 1785 return (m); 1786 } 1787 1788 static struct mbuf * 1789 get_fl_payload(struct adapter *sc, struct sge_fl *fl, const u_int plen) 1790 { 1791 struct mbuf *m0, *m, **pnext; 1792 u_int remaining; 1793 1794 if (__predict_false(fl->flags & FL_BUF_RESUME)) { 1795 M_ASSERTPKTHDR(fl->m0); 1796 MPASS(fl->m0->m_pkthdr.len == plen); 1797 MPASS(fl->remaining < plen); 1798 1799 m0 = fl->m0; 1800 pnext = fl->pnext; 1801 remaining = fl->remaining; 1802 fl->flags &= ~FL_BUF_RESUME; 1803 goto get_segment; 1804 } 1805 1806 /* 1807 * Payload starts at rx_offset in the current hw buffer. Its length is 1808 * 'len' and it may span multiple hw buffers. 1809 */ 1810 1811 m0 = get_scatter_segment(sc, fl, 0, plen); 1812 if (m0 == NULL) 1813 return (NULL); 1814 remaining = plen - m0->m_len; 1815 pnext = &m0->m_next; 1816 while (remaining > 0) { 1817 get_segment: 1818 MPASS(fl->rx_offset == 0); 1819 m = get_scatter_segment(sc, fl, plen - remaining, remaining); 1820 if (__predict_false(m == NULL)) { 1821 fl->m0 = m0; 1822 fl->pnext = pnext; 1823 fl->remaining = remaining; 1824 fl->flags |= FL_BUF_RESUME; 1825 return (NULL); 1826 } 1827 *pnext = m; 1828 pnext = &m->m_next; 1829 remaining -= m->m_len; 1830 } 1831 *pnext = NULL; 1832 1833 M_ASSERTPKTHDR(m0); 1834 return (m0); 1835 } 1836 1837 static int 1838 skip_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset, 1839 int remaining) 1840 { 1841 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 1842 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[sd->zidx]; 1843 int len, blen; 1844 1845 if (fl->flags & FL_BUF_PACKING) { 1846 u_int l, pad; 1847 1848 blen = rxb->size2 - fl->rx_offset; /* max possible in this buf */ 1849 len = min(remaining, blen); 1850 1851 l = fr_offset + len; 1852 pad = roundup2(l, fl->buf_boundary) - l; 1853 if (fl->rx_offset + len + pad < rxb->size2) 1854 blen = len + pad; 1855 fl->rx_offset += blen; 1856 MPASS(fl->rx_offset <= rxb->size2); 1857 if (fl->rx_offset < rxb->size2) 1858 return (len); /* without advancing the cidx */ 1859 } else { 1860 MPASS(fl->rx_offset == 0); /* not packing */ 1861 blen = rxb->size1; 1862 len = min(remaining, blen); 1863 } 1864 move_to_next_rxbuf(fl); 1865 return (len); 1866 } 1867 1868 static inline void 1869 skip_fl_payload(struct adapter *sc, struct sge_fl *fl, int plen) 1870 { 1871 int remaining, fr_offset, len; 1872 1873 fr_offset = 0; 1874 remaining = plen; 1875 while (remaining > 0) { 1876 len = skip_scatter_segment(sc, fl, fr_offset, remaining); 1877 fr_offset += len; 1878 remaining -= len; 1879 } 1880 } 1881 1882 static inline int 1883 get_segment_len(struct adapter *sc, struct sge_fl *fl, int plen) 1884 { 1885 int len; 1886 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 1887 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[sd->zidx]; 1888 1889 if (fl->flags & FL_BUF_PACKING) 1890 len = rxb->size2 - fl->rx_offset; 1891 else 1892 len = rxb->size1; 1893 1894 return (min(plen, len)); 1895 } 1896 1897 static int 1898 eth_rx(struct adapter *sc, struct sge_rxq *rxq, const struct iq_desc *d, 1899 u_int plen) 1900 { 1901 struct mbuf *m0; 1902 struct ifnet *ifp = rxq->ifp; 1903 struct sge_fl *fl = &rxq->fl; 1904 struct vi_info *vi = ifp->if_softc; 1905 const struct cpl_rx_pkt *cpl; 1906 #if defined(INET) || defined(INET6) 1907 struct lro_ctrl *lro = &rxq->lro; 1908 #endif 1909 uint16_t err_vec, tnl_type, tnlhdr_len; 1910 static const int sw_hashtype[4][2] = { 1911 {M_HASHTYPE_NONE, M_HASHTYPE_NONE}, 1912 {M_HASHTYPE_RSS_IPV4, M_HASHTYPE_RSS_IPV6}, 1913 {M_HASHTYPE_RSS_TCP_IPV4, M_HASHTYPE_RSS_TCP_IPV6}, 1914 {M_HASHTYPE_RSS_UDP_IPV4, M_HASHTYPE_RSS_UDP_IPV6}, 1915 }; 1916 static const int sw_csum_flags[2][2] = { 1917 { 1918 /* IP, inner IP */ 1919 CSUM_ENCAP_VXLAN | 1920 CSUM_L3_CALC | CSUM_L3_VALID | 1921 CSUM_L4_CALC | CSUM_L4_VALID | 1922 CSUM_INNER_L3_CALC | CSUM_INNER_L3_VALID | 1923 CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID, 1924 1925 /* IP, inner IP6 */ 1926 CSUM_ENCAP_VXLAN | 1927 CSUM_L3_CALC | CSUM_L3_VALID | 1928 CSUM_L4_CALC | CSUM_L4_VALID | 1929 CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID, 1930 }, 1931 { 1932 /* IP6, inner IP */ 1933 CSUM_ENCAP_VXLAN | 1934 CSUM_L4_CALC | CSUM_L4_VALID | 1935 CSUM_INNER_L3_CALC | CSUM_INNER_L3_VALID | 1936 CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID, 1937 1938 /* IP6, inner IP6 */ 1939 CSUM_ENCAP_VXLAN | 1940 CSUM_L4_CALC | CSUM_L4_VALID | 1941 CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID, 1942 }, 1943 }; 1944 1945 MPASS(plen > sc->params.sge.fl_pktshift); 1946 if (vi->pfil != NULL && PFIL_HOOKED_IN(vi->pfil) && 1947 __predict_true((fl->flags & FL_BUF_RESUME) == 0)) { 1948 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 1949 caddr_t frame; 1950 int rc, slen; 1951 1952 slen = get_segment_len(sc, fl, plen) - 1953 sc->params.sge.fl_pktshift; 1954 frame = sd->cl + fl->rx_offset + sc->params.sge.fl_pktshift; 1955 CURVNET_SET_QUIET(ifp->if_vnet); 1956 rc = pfil_run_hooks(vi->pfil, frame, ifp, 1957 slen | PFIL_MEMPTR | PFIL_IN, NULL); 1958 CURVNET_RESTORE(); 1959 if (rc == PFIL_DROPPED || rc == PFIL_CONSUMED) { 1960 skip_fl_payload(sc, fl, plen); 1961 return (0); 1962 } 1963 if (rc == PFIL_REALLOCED) { 1964 skip_fl_payload(sc, fl, plen); 1965 m0 = pfil_mem2mbuf(frame); 1966 goto have_mbuf; 1967 } 1968 } 1969 1970 m0 = get_fl_payload(sc, fl, plen); 1971 if (__predict_false(m0 == NULL)) 1972 return (ENOMEM); 1973 1974 m0->m_pkthdr.len -= sc->params.sge.fl_pktshift; 1975 m0->m_len -= sc->params.sge.fl_pktshift; 1976 m0->m_data += sc->params.sge.fl_pktshift; 1977 1978 have_mbuf: 1979 m0->m_pkthdr.rcvif = ifp; 1980 M_HASHTYPE_SET(m0, sw_hashtype[d->rss.hash_type][d->rss.ipv6]); 1981 m0->m_pkthdr.flowid = be32toh(d->rss.hash_val); 1982 1983 cpl = (const void *)(&d->rss + 1); 1984 if (sc->params.tp.rx_pkt_encap) { 1985 const uint16_t ev = be16toh(cpl->err_vec); 1986 1987 err_vec = G_T6_COMPR_RXERR_VEC(ev); 1988 tnl_type = G_T6_RX_TNL_TYPE(ev); 1989 tnlhdr_len = G_T6_RX_TNLHDR_LEN(ev); 1990 } else { 1991 err_vec = be16toh(cpl->err_vec); 1992 tnl_type = 0; 1993 tnlhdr_len = 0; 1994 } 1995 if (cpl->csum_calc && err_vec == 0) { 1996 int ipv6 = !!(cpl->l2info & htobe32(F_RXF_IP6)); 1997 1998 /* checksum(s) calculated and found to be correct. */ 1999 2000 MPASS((cpl->l2info & htobe32(F_RXF_IP)) ^ 2001 (cpl->l2info & htobe32(F_RXF_IP6))); 2002 m0->m_pkthdr.csum_data = be16toh(cpl->csum); 2003 if (tnl_type == 0) { 2004 if (!ipv6 && ifp->if_capenable & IFCAP_RXCSUM) { 2005 m0->m_pkthdr.csum_flags = CSUM_L3_CALC | 2006 CSUM_L3_VALID | CSUM_L4_CALC | 2007 CSUM_L4_VALID; 2008 } else if (ipv6 && ifp->if_capenable & IFCAP_RXCSUM_IPV6) { 2009 m0->m_pkthdr.csum_flags = CSUM_L4_CALC | 2010 CSUM_L4_VALID; 2011 } 2012 rxq->rxcsum++; 2013 } else { 2014 MPASS(tnl_type == RX_PKT_TNL_TYPE_VXLAN); 2015 2016 M_HASHTYPE_SETINNER(m0); 2017 if (__predict_false(cpl->ip_frag)) { 2018 /* 2019 * csum_data is for the inner frame (which is an 2020 * IP fragment) and is not 0xffff. There is no 2021 * way to pass the inner csum_data to the stack. 2022 * We don't want the stack to use the inner 2023 * csum_data to validate the outer frame or it 2024 * will get rejected. So we fix csum_data here 2025 * and let sw do the checksum of inner IP 2026 * fragments. 2027 * 2028 * XXX: Need 32b for csum_data2 in an rx mbuf. 2029 * Maybe stuff it into rcv_tstmp? 2030 */ 2031 m0->m_pkthdr.csum_data = 0xffff; 2032 if (ipv6) { 2033 m0->m_pkthdr.csum_flags = CSUM_L4_CALC | 2034 CSUM_L4_VALID; 2035 } else { 2036 m0->m_pkthdr.csum_flags = CSUM_L3_CALC | 2037 CSUM_L3_VALID | CSUM_L4_CALC | 2038 CSUM_L4_VALID; 2039 } 2040 } else { 2041 int outer_ipv6; 2042 2043 MPASS(m0->m_pkthdr.csum_data == 0xffff); 2044 2045 outer_ipv6 = tnlhdr_len >= 2046 sizeof(struct ether_header) + 2047 sizeof(struct ip6_hdr); 2048 m0->m_pkthdr.csum_flags = 2049 sw_csum_flags[outer_ipv6][ipv6]; 2050 } 2051 rxq->vxlan_rxcsum++; 2052 } 2053 } 2054 2055 if (cpl->vlan_ex) { 2056 m0->m_pkthdr.ether_vtag = be16toh(cpl->vlan); 2057 m0->m_flags |= M_VLANTAG; 2058 rxq->vlan_extraction++; 2059 } 2060 2061 if (rxq->iq.flags & IQ_RX_TIMESTAMP) { 2062 /* 2063 * Fill up rcv_tstmp but do not set M_TSTMP. 2064 * rcv_tstmp is not in the format that the 2065 * kernel expects and we don't want to mislead 2066 * it. For now this is only for custom code 2067 * that knows how to interpret cxgbe's stamp. 2068 */ 2069 m0->m_pkthdr.rcv_tstmp = 2070 last_flit_to_ns(sc, d->rsp.u.last_flit); 2071 #ifdef notyet 2072 m0->m_flags |= M_TSTMP; 2073 #endif 2074 } 2075 2076 #ifdef NUMA 2077 m0->m_pkthdr.numa_domain = ifp->if_numa_domain; 2078 #endif 2079 #if defined(INET) || defined(INET6) 2080 if (rxq->iq.flags & IQ_LRO_ENABLED && tnl_type == 0 && 2081 (M_HASHTYPE_GET(m0) == M_HASHTYPE_RSS_TCP_IPV4 || 2082 M_HASHTYPE_GET(m0) == M_HASHTYPE_RSS_TCP_IPV6)) { 2083 if (sort_before_lro(lro)) { 2084 tcp_lro_queue_mbuf(lro, m0); 2085 return (0); /* queued for sort, then LRO */ 2086 } 2087 if (tcp_lro_rx(lro, m0, 0) == 0) 2088 return (0); /* queued for LRO */ 2089 } 2090 #endif 2091 ifp->if_input(ifp, m0); 2092 2093 return (0); 2094 } 2095 2096 /* 2097 * Must drain the wrq or make sure that someone else will. 2098 */ 2099 static void 2100 wrq_tx_drain(void *arg, int n) 2101 { 2102 struct sge_wrq *wrq = arg; 2103 struct sge_eq *eq = &wrq->eq; 2104 2105 EQ_LOCK(eq); 2106 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 2107 drain_wrq_wr_list(wrq->adapter, wrq); 2108 EQ_UNLOCK(eq); 2109 } 2110 2111 static void 2112 drain_wrq_wr_list(struct adapter *sc, struct sge_wrq *wrq) 2113 { 2114 struct sge_eq *eq = &wrq->eq; 2115 u_int available, dbdiff; /* # of hardware descriptors */ 2116 u_int n; 2117 struct wrqe *wr; 2118 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */ 2119 2120 EQ_LOCK_ASSERT_OWNED(eq); 2121 MPASS(TAILQ_EMPTY(&wrq->incomplete_wrs)); 2122 wr = STAILQ_FIRST(&wrq->wr_list); 2123 MPASS(wr != NULL); /* Must be called with something useful to do */ 2124 MPASS(eq->pidx == eq->dbidx); 2125 dbdiff = 0; 2126 2127 do { 2128 eq->cidx = read_hw_cidx(eq); 2129 if (eq->pidx == eq->cidx) 2130 available = eq->sidx - 1; 2131 else 2132 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2133 2134 MPASS(wr->wrq == wrq); 2135 n = howmany(wr->wr_len, EQ_ESIZE); 2136 if (available < n) 2137 break; 2138 2139 dst = (void *)&eq->desc[eq->pidx]; 2140 if (__predict_true(eq->sidx - eq->pidx > n)) { 2141 /* Won't wrap, won't end exactly at the status page. */ 2142 bcopy(&wr->wr[0], dst, wr->wr_len); 2143 eq->pidx += n; 2144 } else { 2145 int first_portion = (eq->sidx - eq->pidx) * EQ_ESIZE; 2146 2147 bcopy(&wr->wr[0], dst, first_portion); 2148 if (wr->wr_len > first_portion) { 2149 bcopy(&wr->wr[first_portion], &eq->desc[0], 2150 wr->wr_len - first_portion); 2151 } 2152 eq->pidx = n - (eq->sidx - eq->pidx); 2153 } 2154 wrq->tx_wrs_copied++; 2155 2156 if (available < eq->sidx / 4 && 2157 atomic_cmpset_int(&eq->equiq, 0, 1)) { 2158 /* 2159 * XXX: This is not 100% reliable with some 2160 * types of WRs. But this is a very unusual 2161 * situation for an ofld/ctrl queue anyway. 2162 */ 2163 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ | 2164 F_FW_WR_EQUEQ); 2165 } 2166 2167 dbdiff += n; 2168 if (dbdiff >= 16) { 2169 ring_eq_db(sc, eq, dbdiff); 2170 dbdiff = 0; 2171 } 2172 2173 STAILQ_REMOVE_HEAD(&wrq->wr_list, link); 2174 free_wrqe(wr); 2175 MPASS(wrq->nwr_pending > 0); 2176 wrq->nwr_pending--; 2177 MPASS(wrq->ndesc_needed >= n); 2178 wrq->ndesc_needed -= n; 2179 } while ((wr = STAILQ_FIRST(&wrq->wr_list)) != NULL); 2180 2181 if (dbdiff) 2182 ring_eq_db(sc, eq, dbdiff); 2183 } 2184 2185 /* 2186 * Doesn't fail. Holds on to work requests it can't send right away. 2187 */ 2188 void 2189 t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, struct wrqe *wr) 2190 { 2191 #ifdef INVARIANTS 2192 struct sge_eq *eq = &wrq->eq; 2193 #endif 2194 2195 EQ_LOCK_ASSERT_OWNED(eq); 2196 MPASS(wr != NULL); 2197 MPASS(wr->wr_len > 0 && wr->wr_len <= SGE_MAX_WR_LEN); 2198 MPASS((wr->wr_len & 0x7) == 0); 2199 2200 STAILQ_INSERT_TAIL(&wrq->wr_list, wr, link); 2201 wrq->nwr_pending++; 2202 wrq->ndesc_needed += howmany(wr->wr_len, EQ_ESIZE); 2203 2204 if (!TAILQ_EMPTY(&wrq->incomplete_wrs)) 2205 return; /* commit_wrq_wr will drain wr_list as well. */ 2206 2207 drain_wrq_wr_list(sc, wrq); 2208 2209 /* Doorbell must have caught up to the pidx. */ 2210 MPASS(eq->pidx == eq->dbidx); 2211 } 2212 2213 void 2214 t4_update_fl_bufsize(struct ifnet *ifp) 2215 { 2216 struct vi_info *vi = ifp->if_softc; 2217 struct adapter *sc = vi->adapter; 2218 struct sge_rxq *rxq; 2219 #ifdef TCP_OFFLOAD 2220 struct sge_ofld_rxq *ofld_rxq; 2221 #endif 2222 struct sge_fl *fl; 2223 int i, maxp; 2224 2225 maxp = max_rx_payload(sc, ifp, false); 2226 for_each_rxq(vi, i, rxq) { 2227 fl = &rxq->fl; 2228 2229 FL_LOCK(fl); 2230 fl->zidx = find_refill_source(sc, maxp, 2231 fl->flags & FL_BUF_PACKING); 2232 FL_UNLOCK(fl); 2233 } 2234 #ifdef TCP_OFFLOAD 2235 maxp = max_rx_payload(sc, ifp, true); 2236 for_each_ofld_rxq(vi, i, ofld_rxq) { 2237 fl = &ofld_rxq->fl; 2238 2239 FL_LOCK(fl); 2240 fl->zidx = find_refill_source(sc, maxp, 2241 fl->flags & FL_BUF_PACKING); 2242 FL_UNLOCK(fl); 2243 } 2244 #endif 2245 } 2246 2247 static inline int 2248 mbuf_nsegs(struct mbuf *m) 2249 { 2250 2251 M_ASSERTPKTHDR(m); 2252 KASSERT(m->m_pkthdr.inner_l5hlen > 0, 2253 ("%s: mbuf %p missing information on # of segments.", __func__, m)); 2254 2255 return (m->m_pkthdr.inner_l5hlen); 2256 } 2257 2258 static inline void 2259 set_mbuf_nsegs(struct mbuf *m, uint8_t nsegs) 2260 { 2261 2262 M_ASSERTPKTHDR(m); 2263 m->m_pkthdr.inner_l5hlen = nsegs; 2264 } 2265 2266 static inline int 2267 mbuf_cflags(struct mbuf *m) 2268 { 2269 2270 M_ASSERTPKTHDR(m); 2271 return (m->m_pkthdr.PH_loc.eight[4]); 2272 } 2273 2274 static inline void 2275 set_mbuf_cflags(struct mbuf *m, uint8_t flags) 2276 { 2277 2278 M_ASSERTPKTHDR(m); 2279 m->m_pkthdr.PH_loc.eight[4] = flags; 2280 } 2281 2282 static inline int 2283 mbuf_len16(struct mbuf *m) 2284 { 2285 int n; 2286 2287 M_ASSERTPKTHDR(m); 2288 n = m->m_pkthdr.PH_loc.eight[0]; 2289 if (!(mbuf_cflags(m) & MC_TLS)) 2290 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16); 2291 2292 return (n); 2293 } 2294 2295 static inline void 2296 set_mbuf_len16(struct mbuf *m, uint8_t len16) 2297 { 2298 2299 M_ASSERTPKTHDR(m); 2300 if (!(mbuf_cflags(m) & MC_TLS)) 2301 MPASS(len16 > 0 && len16 <= SGE_MAX_WR_LEN / 16); 2302 m->m_pkthdr.PH_loc.eight[0] = len16; 2303 } 2304 2305 #ifdef RATELIMIT 2306 static inline int 2307 mbuf_eo_nsegs(struct mbuf *m) 2308 { 2309 2310 M_ASSERTPKTHDR(m); 2311 return (m->m_pkthdr.PH_loc.eight[1]); 2312 } 2313 2314 static inline void 2315 set_mbuf_eo_nsegs(struct mbuf *m, uint8_t nsegs) 2316 { 2317 2318 M_ASSERTPKTHDR(m); 2319 m->m_pkthdr.PH_loc.eight[1] = nsegs; 2320 } 2321 2322 static inline int 2323 mbuf_eo_len16(struct mbuf *m) 2324 { 2325 int n; 2326 2327 M_ASSERTPKTHDR(m); 2328 n = m->m_pkthdr.PH_loc.eight[2]; 2329 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16); 2330 2331 return (n); 2332 } 2333 2334 static inline void 2335 set_mbuf_eo_len16(struct mbuf *m, uint8_t len16) 2336 { 2337 2338 M_ASSERTPKTHDR(m); 2339 m->m_pkthdr.PH_loc.eight[2] = len16; 2340 } 2341 2342 static inline int 2343 mbuf_eo_tsclk_tsoff(struct mbuf *m) 2344 { 2345 2346 M_ASSERTPKTHDR(m); 2347 return (m->m_pkthdr.PH_loc.eight[3]); 2348 } 2349 2350 static inline void 2351 set_mbuf_eo_tsclk_tsoff(struct mbuf *m, uint8_t tsclk_tsoff) 2352 { 2353 2354 M_ASSERTPKTHDR(m); 2355 m->m_pkthdr.PH_loc.eight[3] = tsclk_tsoff; 2356 } 2357 2358 static inline int 2359 needs_eo(struct m_snd_tag *mst) 2360 { 2361 2362 return (mst != NULL && mst->type == IF_SND_TAG_TYPE_RATE_LIMIT); 2363 } 2364 #endif 2365 2366 /* 2367 * Try to allocate an mbuf to contain a raw work request. To make it 2368 * easy to construct the work request, don't allocate a chain but a 2369 * single mbuf. 2370 */ 2371 struct mbuf * 2372 alloc_wr_mbuf(int len, int how) 2373 { 2374 struct mbuf *m; 2375 2376 if (len <= MHLEN) 2377 m = m_gethdr(how, MT_DATA); 2378 else if (len <= MCLBYTES) 2379 m = m_getcl(how, MT_DATA, M_PKTHDR); 2380 else 2381 m = NULL; 2382 if (m == NULL) 2383 return (NULL); 2384 m->m_pkthdr.len = len; 2385 m->m_len = len; 2386 set_mbuf_cflags(m, MC_RAW_WR); 2387 set_mbuf_len16(m, howmany(len, 16)); 2388 return (m); 2389 } 2390 2391 static inline bool 2392 needs_hwcsum(struct mbuf *m) 2393 { 2394 const uint32_t csum_flags = CSUM_IP | CSUM_IP_UDP | CSUM_IP_TCP | 2395 CSUM_IP_TSO | CSUM_INNER_IP | CSUM_INNER_IP_UDP | 2396 CSUM_INNER_IP_TCP | CSUM_INNER_IP_TSO | CSUM_IP6_UDP | 2397 CSUM_IP6_TCP | CSUM_IP6_TSO | CSUM_INNER_IP6_UDP | 2398 CSUM_INNER_IP6_TCP | CSUM_INNER_IP6_TSO; 2399 2400 M_ASSERTPKTHDR(m); 2401 2402 return (m->m_pkthdr.csum_flags & csum_flags); 2403 } 2404 2405 static inline bool 2406 needs_tso(struct mbuf *m) 2407 { 2408 const uint32_t csum_flags = CSUM_IP_TSO | CSUM_IP6_TSO | 2409 CSUM_INNER_IP_TSO | CSUM_INNER_IP6_TSO; 2410 2411 M_ASSERTPKTHDR(m); 2412 2413 return (m->m_pkthdr.csum_flags & csum_flags); 2414 } 2415 2416 static inline bool 2417 needs_vxlan_csum(struct mbuf *m) 2418 { 2419 2420 M_ASSERTPKTHDR(m); 2421 2422 return (m->m_pkthdr.csum_flags & CSUM_ENCAP_VXLAN); 2423 } 2424 2425 static inline bool 2426 needs_vxlan_tso(struct mbuf *m) 2427 { 2428 const uint32_t csum_flags = CSUM_ENCAP_VXLAN | CSUM_INNER_IP_TSO | 2429 CSUM_INNER_IP6_TSO; 2430 2431 M_ASSERTPKTHDR(m); 2432 2433 return ((m->m_pkthdr.csum_flags & csum_flags) != 0 && 2434 (m->m_pkthdr.csum_flags & csum_flags) != CSUM_ENCAP_VXLAN); 2435 } 2436 2437 static inline bool 2438 needs_inner_tcp_csum(struct mbuf *m) 2439 { 2440 const uint32_t csum_flags = CSUM_INNER_IP_TSO | CSUM_INNER_IP6_TSO; 2441 2442 M_ASSERTPKTHDR(m); 2443 2444 return (m->m_pkthdr.csum_flags & csum_flags); 2445 } 2446 2447 static inline bool 2448 needs_l3_csum(struct mbuf *m) 2449 { 2450 const uint32_t csum_flags = CSUM_IP | CSUM_IP_TSO | CSUM_INNER_IP | 2451 CSUM_INNER_IP_TSO; 2452 2453 M_ASSERTPKTHDR(m); 2454 2455 return (m->m_pkthdr.csum_flags & csum_flags); 2456 } 2457 2458 static inline bool 2459 needs_outer_tcp_csum(struct mbuf *m) 2460 { 2461 const uint32_t csum_flags = CSUM_IP_TCP | CSUM_IP_TSO | CSUM_IP6_TCP | 2462 CSUM_IP6_TSO; 2463 2464 M_ASSERTPKTHDR(m); 2465 2466 return (m->m_pkthdr.csum_flags & csum_flags); 2467 } 2468 2469 #ifdef RATELIMIT 2470 static inline bool 2471 needs_outer_l4_csum(struct mbuf *m) 2472 { 2473 const uint32_t csum_flags = CSUM_IP_UDP | CSUM_IP_TCP | CSUM_IP_TSO | 2474 CSUM_IP6_UDP | CSUM_IP6_TCP | CSUM_IP6_TSO; 2475 2476 M_ASSERTPKTHDR(m); 2477 2478 return (m->m_pkthdr.csum_flags & csum_flags); 2479 } 2480 2481 static inline bool 2482 needs_outer_udp_csum(struct mbuf *m) 2483 { 2484 const uint32_t csum_flags = CSUM_IP_UDP | CSUM_IP6_UDP; 2485 2486 M_ASSERTPKTHDR(m); 2487 2488 return (m->m_pkthdr.csum_flags & csum_flags); 2489 } 2490 #endif 2491 2492 static inline bool 2493 needs_vlan_insertion(struct mbuf *m) 2494 { 2495 2496 M_ASSERTPKTHDR(m); 2497 2498 return (m->m_flags & M_VLANTAG); 2499 } 2500 2501 static void * 2502 m_advance(struct mbuf **pm, int *poffset, int len) 2503 { 2504 struct mbuf *m = *pm; 2505 int offset = *poffset; 2506 uintptr_t p = 0; 2507 2508 MPASS(len > 0); 2509 2510 for (;;) { 2511 if (offset + len < m->m_len) { 2512 offset += len; 2513 p = mtod(m, uintptr_t) + offset; 2514 break; 2515 } 2516 len -= m->m_len - offset; 2517 m = m->m_next; 2518 offset = 0; 2519 MPASS(m != NULL); 2520 } 2521 *poffset = offset; 2522 *pm = m; 2523 return ((void *)p); 2524 } 2525 2526 static inline int 2527 count_mbuf_ext_pgs(struct mbuf *m, int skip, vm_paddr_t *nextaddr) 2528 { 2529 vm_paddr_t paddr; 2530 int i, len, off, pglen, pgoff, seglen, segoff; 2531 int nsegs = 0; 2532 2533 M_ASSERTEXTPG(m); 2534 off = mtod(m, vm_offset_t); 2535 len = m->m_len; 2536 off += skip; 2537 len -= skip; 2538 2539 if (m->m_epg_hdrlen != 0) { 2540 if (off >= m->m_epg_hdrlen) { 2541 off -= m->m_epg_hdrlen; 2542 } else { 2543 seglen = m->m_epg_hdrlen - off; 2544 segoff = off; 2545 seglen = min(seglen, len); 2546 off = 0; 2547 len -= seglen; 2548 paddr = pmap_kextract( 2549 (vm_offset_t)&m->m_epg_hdr[segoff]); 2550 if (*nextaddr != paddr) 2551 nsegs++; 2552 *nextaddr = paddr + seglen; 2553 } 2554 } 2555 pgoff = m->m_epg_1st_off; 2556 for (i = 0; i < m->m_epg_npgs && len > 0; i++) { 2557 pglen = m_epg_pagelen(m, i, pgoff); 2558 if (off >= pglen) { 2559 off -= pglen; 2560 pgoff = 0; 2561 continue; 2562 } 2563 seglen = pglen - off; 2564 segoff = pgoff + off; 2565 off = 0; 2566 seglen = min(seglen, len); 2567 len -= seglen; 2568 paddr = m->m_epg_pa[i] + segoff; 2569 if (*nextaddr != paddr) 2570 nsegs++; 2571 *nextaddr = paddr + seglen; 2572 pgoff = 0; 2573 }; 2574 if (len != 0) { 2575 seglen = min(len, m->m_epg_trllen - off); 2576 len -= seglen; 2577 paddr = pmap_kextract((vm_offset_t)&m->m_epg_trail[off]); 2578 if (*nextaddr != paddr) 2579 nsegs++; 2580 *nextaddr = paddr + seglen; 2581 } 2582 2583 return (nsegs); 2584 } 2585 2586 2587 /* 2588 * Can deal with empty mbufs in the chain that have m_len = 0, but the chain 2589 * must have at least one mbuf that's not empty. It is possible for this 2590 * routine to return 0 if skip accounts for all the contents of the mbuf chain. 2591 */ 2592 static inline int 2593 count_mbuf_nsegs(struct mbuf *m, int skip, uint8_t *cflags) 2594 { 2595 vm_paddr_t nextaddr, paddr; 2596 vm_offset_t va; 2597 int len, nsegs; 2598 2599 M_ASSERTPKTHDR(m); 2600 MPASS(m->m_pkthdr.len > 0); 2601 MPASS(m->m_pkthdr.len >= skip); 2602 2603 nsegs = 0; 2604 nextaddr = 0; 2605 for (; m; m = m->m_next) { 2606 len = m->m_len; 2607 if (__predict_false(len == 0)) 2608 continue; 2609 if (skip >= len) { 2610 skip -= len; 2611 continue; 2612 } 2613 if ((m->m_flags & M_EXTPG) != 0) { 2614 *cflags |= MC_NOMAP; 2615 nsegs += count_mbuf_ext_pgs(m, skip, &nextaddr); 2616 skip = 0; 2617 continue; 2618 } 2619 va = mtod(m, vm_offset_t) + skip; 2620 len -= skip; 2621 skip = 0; 2622 paddr = pmap_kextract(va); 2623 nsegs += sglist_count((void *)(uintptr_t)va, len); 2624 if (paddr == nextaddr) 2625 nsegs--; 2626 nextaddr = pmap_kextract(va + len - 1) + 1; 2627 } 2628 2629 return (nsegs); 2630 } 2631 2632 /* 2633 * The maximum number of segments that can fit in a WR. 2634 */ 2635 static int 2636 max_nsegs_allowed(struct mbuf *m, bool vm_wr) 2637 { 2638 2639 if (vm_wr) { 2640 if (needs_tso(m)) 2641 return (TX_SGL_SEGS_VM_TSO); 2642 return (TX_SGL_SEGS_VM); 2643 } 2644 2645 if (needs_tso(m)) { 2646 if (needs_vxlan_tso(m)) 2647 return (TX_SGL_SEGS_VXLAN_TSO); 2648 else 2649 return (TX_SGL_SEGS_TSO); 2650 } 2651 2652 return (TX_SGL_SEGS); 2653 } 2654 2655 static struct timeval txerr_ratecheck = {0}; 2656 static const struct timeval txerr_interval = {3, 0}; 2657 2658 /* 2659 * Analyze the mbuf to determine its tx needs. The mbuf passed in may change: 2660 * a) caller can assume it's been freed if this function returns with an error. 2661 * b) it may get defragged up if the gather list is too long for the hardware. 2662 */ 2663 int 2664 parse_pkt(struct mbuf **mp, bool vm_wr) 2665 { 2666 struct mbuf *m0 = *mp, *m; 2667 int rc, nsegs, defragged = 0, offset; 2668 struct ether_header *eh; 2669 void *l3hdr; 2670 #if defined(INET) || defined(INET6) 2671 struct tcphdr *tcp; 2672 #endif 2673 #if defined(KERN_TLS) || defined(RATELIMIT) 2674 struct m_snd_tag *mst; 2675 #endif 2676 uint16_t eh_type; 2677 uint8_t cflags; 2678 2679 cflags = 0; 2680 M_ASSERTPKTHDR(m0); 2681 if (__predict_false(m0->m_pkthdr.len < ETHER_HDR_LEN)) { 2682 rc = EINVAL; 2683 fail: 2684 m_freem(m0); 2685 *mp = NULL; 2686 return (rc); 2687 } 2688 restart: 2689 /* 2690 * First count the number of gather list segments in the payload. 2691 * Defrag the mbuf if nsegs exceeds the hardware limit. 2692 */ 2693 M_ASSERTPKTHDR(m0); 2694 MPASS(m0->m_pkthdr.len > 0); 2695 nsegs = count_mbuf_nsegs(m0, 0, &cflags); 2696 #if defined(KERN_TLS) || defined(RATELIMIT) 2697 if (m0->m_pkthdr.csum_flags & CSUM_SND_TAG) 2698 mst = m0->m_pkthdr.snd_tag; 2699 else 2700 mst = NULL; 2701 #endif 2702 #ifdef KERN_TLS 2703 if (mst != NULL && mst->type == IF_SND_TAG_TYPE_TLS) { 2704 int len16; 2705 2706 cflags |= MC_TLS; 2707 set_mbuf_cflags(m0, cflags); 2708 rc = t6_ktls_parse_pkt(m0, &nsegs, &len16); 2709 if (rc != 0) 2710 goto fail; 2711 set_mbuf_nsegs(m0, nsegs); 2712 set_mbuf_len16(m0, len16); 2713 return (0); 2714 } 2715 #endif 2716 if (nsegs > max_nsegs_allowed(m0, vm_wr)) { 2717 if (defragged++ > 0) { 2718 rc = EFBIG; 2719 goto fail; 2720 } 2721 counter_u64_add(defrags, 1); 2722 if ((m = m_defrag(m0, M_NOWAIT)) == NULL) { 2723 rc = ENOMEM; 2724 goto fail; 2725 } 2726 *mp = m0 = m; /* update caller's copy after defrag */ 2727 goto restart; 2728 } 2729 2730 if (__predict_false(nsegs > 2 && m0->m_pkthdr.len <= MHLEN && 2731 !(cflags & MC_NOMAP))) { 2732 counter_u64_add(pullups, 1); 2733 m0 = m_pullup(m0, m0->m_pkthdr.len); 2734 if (m0 == NULL) { 2735 /* Should have left well enough alone. */ 2736 rc = EFBIG; 2737 goto fail; 2738 } 2739 *mp = m0; /* update caller's copy after pullup */ 2740 goto restart; 2741 } 2742 set_mbuf_nsegs(m0, nsegs); 2743 set_mbuf_cflags(m0, cflags); 2744 calculate_mbuf_len16(m0, vm_wr); 2745 2746 #ifdef RATELIMIT 2747 /* 2748 * Ethofld is limited to TCP and UDP for now, and only when L4 hw 2749 * checksumming is enabled. needs_outer_l4_csum happens to check for 2750 * all the right things. 2751 */ 2752 if (__predict_false(needs_eo(mst) && !needs_outer_l4_csum(m0))) { 2753 m_snd_tag_rele(m0->m_pkthdr.snd_tag); 2754 m0->m_pkthdr.snd_tag = NULL; 2755 m0->m_pkthdr.csum_flags &= ~CSUM_SND_TAG; 2756 mst = NULL; 2757 } 2758 #endif 2759 2760 if (!needs_hwcsum(m0) 2761 #ifdef RATELIMIT 2762 && !needs_eo(mst) 2763 #endif 2764 ) 2765 return (0); 2766 2767 m = m0; 2768 eh = mtod(m, struct ether_header *); 2769 eh_type = ntohs(eh->ether_type); 2770 if (eh_type == ETHERTYPE_VLAN) { 2771 struct ether_vlan_header *evh = (void *)eh; 2772 2773 eh_type = ntohs(evh->evl_proto); 2774 m0->m_pkthdr.l2hlen = sizeof(*evh); 2775 } else 2776 m0->m_pkthdr.l2hlen = sizeof(*eh); 2777 2778 offset = 0; 2779 l3hdr = m_advance(&m, &offset, m0->m_pkthdr.l2hlen); 2780 2781 switch (eh_type) { 2782 #ifdef INET6 2783 case ETHERTYPE_IPV6: 2784 m0->m_pkthdr.l3hlen = sizeof(struct ip6_hdr); 2785 break; 2786 #endif 2787 #ifdef INET 2788 case ETHERTYPE_IP: 2789 { 2790 struct ip *ip = l3hdr; 2791 2792 if (needs_vxlan_csum(m0)) { 2793 /* Driver will do the outer IP hdr checksum. */ 2794 ip->ip_sum = 0; 2795 if (needs_vxlan_tso(m0)) { 2796 const uint16_t ipl = ip->ip_len; 2797 2798 ip->ip_len = 0; 2799 ip->ip_sum = ~in_cksum_hdr(ip); 2800 ip->ip_len = ipl; 2801 } else 2802 ip->ip_sum = in_cksum_hdr(ip); 2803 } 2804 m0->m_pkthdr.l3hlen = ip->ip_hl << 2; 2805 break; 2806 } 2807 #endif 2808 default: 2809 if (ratecheck(&txerr_ratecheck, &txerr_interval)) { 2810 log(LOG_ERR, "%s: ethertype 0x%04x unknown. " 2811 "if_cxgbe must be compiled with the same " 2812 "INET/INET6 options as the kernel.\n", __func__, 2813 eh_type); 2814 } 2815 rc = EINVAL; 2816 goto fail; 2817 } 2818 2819 if (needs_vxlan_csum(m0)) { 2820 m0->m_pkthdr.l4hlen = sizeof(struct udphdr); 2821 m0->m_pkthdr.l5hlen = sizeof(struct vxlan_header); 2822 2823 /* Inner headers. */ 2824 eh = m_advance(&m, &offset, m0->m_pkthdr.l3hlen + 2825 sizeof(struct udphdr) + sizeof(struct vxlan_header)); 2826 eh_type = ntohs(eh->ether_type); 2827 if (eh_type == ETHERTYPE_VLAN) { 2828 struct ether_vlan_header *evh = (void *)eh; 2829 2830 eh_type = ntohs(evh->evl_proto); 2831 m0->m_pkthdr.inner_l2hlen = sizeof(*evh); 2832 } else 2833 m0->m_pkthdr.inner_l2hlen = sizeof(*eh); 2834 l3hdr = m_advance(&m, &offset, m0->m_pkthdr.inner_l2hlen); 2835 2836 switch (eh_type) { 2837 #ifdef INET6 2838 case ETHERTYPE_IPV6: 2839 m0->m_pkthdr.inner_l3hlen = sizeof(struct ip6_hdr); 2840 break; 2841 #endif 2842 #ifdef INET 2843 case ETHERTYPE_IP: 2844 { 2845 struct ip *ip = l3hdr; 2846 2847 m0->m_pkthdr.inner_l3hlen = ip->ip_hl << 2; 2848 break; 2849 } 2850 #endif 2851 default: 2852 if (ratecheck(&txerr_ratecheck, &txerr_interval)) { 2853 log(LOG_ERR, "%s: VXLAN hw offload requested" 2854 "with unknown ethertype 0x%04x. if_cxgbe " 2855 "must be compiled with the same INET/INET6 " 2856 "options as the kernel.\n", __func__, 2857 eh_type); 2858 } 2859 rc = EINVAL; 2860 goto fail; 2861 } 2862 #if defined(INET) || defined(INET6) 2863 if (needs_inner_tcp_csum(m0)) { 2864 tcp = m_advance(&m, &offset, m0->m_pkthdr.inner_l3hlen); 2865 m0->m_pkthdr.inner_l4hlen = tcp->th_off * 4; 2866 } 2867 #endif 2868 MPASS((m0->m_pkthdr.csum_flags & CSUM_SND_TAG) == 0); 2869 m0->m_pkthdr.csum_flags &= CSUM_INNER_IP6_UDP | 2870 CSUM_INNER_IP6_TCP | CSUM_INNER_IP6_TSO | CSUM_INNER_IP | 2871 CSUM_INNER_IP_UDP | CSUM_INNER_IP_TCP | CSUM_INNER_IP_TSO | 2872 CSUM_ENCAP_VXLAN; 2873 } 2874 2875 #if defined(INET) || defined(INET6) 2876 if (needs_outer_tcp_csum(m0)) { 2877 tcp = m_advance(&m, &offset, m0->m_pkthdr.l3hlen); 2878 m0->m_pkthdr.l4hlen = tcp->th_off * 4; 2879 #ifdef RATELIMIT 2880 if (tsclk >= 0 && *(uint32_t *)(tcp + 1) == ntohl(0x0101080a)) { 2881 set_mbuf_eo_tsclk_tsoff(m0, 2882 V_FW_ETH_TX_EO_WR_TSCLK(tsclk) | 2883 V_FW_ETH_TX_EO_WR_TSOFF(sizeof(*tcp) / 2 + 1)); 2884 } else 2885 set_mbuf_eo_tsclk_tsoff(m0, 0); 2886 } else if (needs_outer_udp_csum(m0)) { 2887 m0->m_pkthdr.l4hlen = sizeof(struct udphdr); 2888 #endif 2889 } 2890 #ifdef RATELIMIT 2891 if (needs_eo(mst)) { 2892 u_int immhdrs; 2893 2894 /* EO WRs have the headers in the WR and not the GL. */ 2895 immhdrs = m0->m_pkthdr.l2hlen + m0->m_pkthdr.l3hlen + 2896 m0->m_pkthdr.l4hlen; 2897 cflags = 0; 2898 nsegs = count_mbuf_nsegs(m0, immhdrs, &cflags); 2899 MPASS(cflags == mbuf_cflags(m0)); 2900 set_mbuf_eo_nsegs(m0, nsegs); 2901 set_mbuf_eo_len16(m0, 2902 txpkt_eo_len16(nsegs, immhdrs, needs_tso(m0))); 2903 } 2904 #endif 2905 #endif 2906 MPASS(m0 == *mp); 2907 return (0); 2908 } 2909 2910 void * 2911 start_wrq_wr(struct sge_wrq *wrq, int len16, struct wrq_cookie *cookie) 2912 { 2913 struct sge_eq *eq = &wrq->eq; 2914 struct adapter *sc = wrq->adapter; 2915 int ndesc, available; 2916 struct wrqe *wr; 2917 void *w; 2918 2919 MPASS(len16 > 0); 2920 ndesc = tx_len16_to_desc(len16); 2921 MPASS(ndesc > 0 && ndesc <= SGE_MAX_WR_NDESC); 2922 2923 EQ_LOCK(eq); 2924 2925 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 2926 drain_wrq_wr_list(sc, wrq); 2927 2928 if (!STAILQ_EMPTY(&wrq->wr_list)) { 2929 slowpath: 2930 EQ_UNLOCK(eq); 2931 wr = alloc_wrqe(len16 * 16, wrq); 2932 if (__predict_false(wr == NULL)) 2933 return (NULL); 2934 cookie->pidx = -1; 2935 cookie->ndesc = ndesc; 2936 return (&wr->wr); 2937 } 2938 2939 eq->cidx = read_hw_cidx(eq); 2940 if (eq->pidx == eq->cidx) 2941 available = eq->sidx - 1; 2942 else 2943 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2944 if (available < ndesc) 2945 goto slowpath; 2946 2947 cookie->pidx = eq->pidx; 2948 cookie->ndesc = ndesc; 2949 TAILQ_INSERT_TAIL(&wrq->incomplete_wrs, cookie, link); 2950 2951 w = &eq->desc[eq->pidx]; 2952 IDXINCR(eq->pidx, ndesc, eq->sidx); 2953 if (__predict_false(cookie->pidx + ndesc > eq->sidx)) { 2954 w = &wrq->ss[0]; 2955 wrq->ss_pidx = cookie->pidx; 2956 wrq->ss_len = len16 * 16; 2957 } 2958 2959 EQ_UNLOCK(eq); 2960 2961 return (w); 2962 } 2963 2964 void 2965 commit_wrq_wr(struct sge_wrq *wrq, void *w, struct wrq_cookie *cookie) 2966 { 2967 struct sge_eq *eq = &wrq->eq; 2968 struct adapter *sc = wrq->adapter; 2969 int ndesc, pidx; 2970 struct wrq_cookie *prev, *next; 2971 2972 if (cookie->pidx == -1) { 2973 struct wrqe *wr = __containerof(w, struct wrqe, wr); 2974 2975 t4_wrq_tx(sc, wr); 2976 return; 2977 } 2978 2979 if (__predict_false(w == &wrq->ss[0])) { 2980 int n = (eq->sidx - wrq->ss_pidx) * EQ_ESIZE; 2981 2982 MPASS(wrq->ss_len > n); /* WR had better wrap around. */ 2983 bcopy(&wrq->ss[0], &eq->desc[wrq->ss_pidx], n); 2984 bcopy(&wrq->ss[n], &eq->desc[0], wrq->ss_len - n); 2985 wrq->tx_wrs_ss++; 2986 } else 2987 wrq->tx_wrs_direct++; 2988 2989 EQ_LOCK(eq); 2990 ndesc = cookie->ndesc; /* Can be more than SGE_MAX_WR_NDESC here. */ 2991 pidx = cookie->pidx; 2992 MPASS(pidx >= 0 && pidx < eq->sidx); 2993 prev = TAILQ_PREV(cookie, wrq_incomplete_wrs, link); 2994 next = TAILQ_NEXT(cookie, link); 2995 if (prev == NULL) { 2996 MPASS(pidx == eq->dbidx); 2997 if (next == NULL || ndesc >= 16) { 2998 int available; 2999 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */ 3000 3001 /* 3002 * Note that the WR via which we'll request tx updates 3003 * is at pidx and not eq->pidx, which has moved on 3004 * already. 3005 */ 3006 dst = (void *)&eq->desc[pidx]; 3007 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 3008 if (available < eq->sidx / 4 && 3009 atomic_cmpset_int(&eq->equiq, 0, 1)) { 3010 /* 3011 * XXX: This is not 100% reliable with some 3012 * types of WRs. But this is a very unusual 3013 * situation for an ofld/ctrl queue anyway. 3014 */ 3015 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ | 3016 F_FW_WR_EQUEQ); 3017 } 3018 3019 ring_eq_db(wrq->adapter, eq, ndesc); 3020 } else { 3021 MPASS(IDXDIFF(next->pidx, pidx, eq->sidx) == ndesc); 3022 next->pidx = pidx; 3023 next->ndesc += ndesc; 3024 } 3025 } else { 3026 MPASS(IDXDIFF(pidx, prev->pidx, eq->sidx) == prev->ndesc); 3027 prev->ndesc += ndesc; 3028 } 3029 TAILQ_REMOVE(&wrq->incomplete_wrs, cookie, link); 3030 3031 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 3032 drain_wrq_wr_list(sc, wrq); 3033 3034 #ifdef INVARIANTS 3035 if (TAILQ_EMPTY(&wrq->incomplete_wrs)) { 3036 /* Doorbell must have caught up to the pidx. */ 3037 MPASS(wrq->eq.pidx == wrq->eq.dbidx); 3038 } 3039 #endif 3040 EQ_UNLOCK(eq); 3041 } 3042 3043 static u_int 3044 can_resume_eth_tx(struct mp_ring *r) 3045 { 3046 struct sge_eq *eq = r->cookie; 3047 3048 return (total_available_tx_desc(eq) > eq->sidx / 8); 3049 } 3050 3051 static inline bool 3052 cannot_use_txpkts(struct mbuf *m) 3053 { 3054 /* maybe put a GL limit too, to avoid silliness? */ 3055 3056 return (needs_tso(m) || (mbuf_cflags(m) & (MC_RAW_WR | MC_TLS)) != 0); 3057 } 3058 3059 static inline int 3060 discard_tx(struct sge_eq *eq) 3061 { 3062 3063 return ((eq->flags & (EQ_ENABLED | EQ_QFLUSH)) != EQ_ENABLED); 3064 } 3065 3066 static inline int 3067 wr_can_update_eq(void *p) 3068 { 3069 struct fw_eth_tx_pkts_wr *wr = p; 3070 3071 switch (G_FW_WR_OP(be32toh(wr->op_pkd))) { 3072 case FW_ULPTX_WR: 3073 case FW_ETH_TX_PKT_WR: 3074 case FW_ETH_TX_PKTS_WR: 3075 case FW_ETH_TX_PKTS2_WR: 3076 case FW_ETH_TX_PKT_VM_WR: 3077 case FW_ETH_TX_PKTS_VM_WR: 3078 return (1); 3079 default: 3080 return (0); 3081 } 3082 } 3083 3084 static inline void 3085 set_txupdate_flags(struct sge_txq *txq, u_int avail, 3086 struct fw_eth_tx_pkt_wr *wr) 3087 { 3088 struct sge_eq *eq = &txq->eq; 3089 struct txpkts *txp = &txq->txp; 3090 3091 if ((txp->npkt > 0 || avail < eq->sidx / 2) && 3092 atomic_cmpset_int(&eq->equiq, 0, 1)) { 3093 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ | F_FW_WR_EQUIQ); 3094 eq->equeqidx = eq->pidx; 3095 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 32) { 3096 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ); 3097 eq->equeqidx = eq->pidx; 3098 } 3099 } 3100 3101 #if defined(__i386__) || defined(__amd64__) 3102 extern uint64_t tsc_freq; 3103 #endif 3104 3105 static inline bool 3106 record_eth_tx_time(struct sge_txq *txq) 3107 { 3108 const uint64_t cycles = get_cyclecount(); 3109 const uint64_t last_tx = txq->last_tx; 3110 #if defined(__i386__) || defined(__amd64__) 3111 const uint64_t itg = tsc_freq * t4_tx_coalesce_gap / 1000000; 3112 #else 3113 const uint64_t itg = 0; 3114 #endif 3115 3116 MPASS(cycles >= last_tx); 3117 txq->last_tx = cycles; 3118 return (cycles - last_tx < itg); 3119 } 3120 3121 /* 3122 * r->items[cidx] to r->items[pidx], with a wraparound at r->size, are ready to 3123 * be consumed. Return the actual number consumed. 0 indicates a stall. 3124 */ 3125 static u_int 3126 eth_tx(struct mp_ring *r, u_int cidx, u_int pidx, bool *coalescing) 3127 { 3128 struct sge_txq *txq = r->cookie; 3129 struct ifnet *ifp = txq->ifp; 3130 struct sge_eq *eq = &txq->eq; 3131 struct txpkts *txp = &txq->txp; 3132 struct vi_info *vi = ifp->if_softc; 3133 struct adapter *sc = vi->adapter; 3134 u_int total, remaining; /* # of packets */ 3135 u_int n, avail, dbdiff; /* # of hardware descriptors */ 3136 int i, rc; 3137 struct mbuf *m0; 3138 bool snd, recent_tx; 3139 void *wr; /* start of the last WR written to the ring */ 3140 3141 TXQ_LOCK_ASSERT_OWNED(txq); 3142 recent_tx = record_eth_tx_time(txq); 3143 3144 remaining = IDXDIFF(pidx, cidx, r->size); 3145 if (__predict_false(discard_tx(eq))) { 3146 for (i = 0; i < txp->npkt; i++) 3147 m_freem(txp->mb[i]); 3148 txp->npkt = 0; 3149 while (cidx != pidx) { 3150 m0 = r->items[cidx]; 3151 m_freem(m0); 3152 if (++cidx == r->size) 3153 cidx = 0; 3154 } 3155 reclaim_tx_descs(txq, eq->sidx); 3156 *coalescing = false; 3157 return (remaining); /* emptied */ 3158 } 3159 3160 /* How many hardware descriptors do we have readily available. */ 3161 if (eq->pidx == eq->cidx) 3162 avail = eq->sidx - 1; 3163 else 3164 avail = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 3165 3166 total = 0; 3167 if (remaining == 0) { 3168 txp->score = 0; 3169 txq->txpkts_flush++; 3170 goto send_txpkts; 3171 } 3172 3173 dbdiff = 0; 3174 MPASS(remaining > 0); 3175 while (remaining > 0) { 3176 m0 = r->items[cidx]; 3177 M_ASSERTPKTHDR(m0); 3178 MPASS(m0->m_nextpkt == NULL); 3179 3180 if (avail < 2 * SGE_MAX_WR_NDESC) 3181 avail += reclaim_tx_descs(txq, 64); 3182 3183 if (t4_tx_coalesce == 0 && txp->npkt == 0) 3184 goto skip_coalescing; 3185 if (cannot_use_txpkts(m0)) 3186 txp->score = 0; 3187 else if (recent_tx) { 3188 if (++txp->score == 0) 3189 txp->score = UINT8_MAX; 3190 } else 3191 txp->score = 1; 3192 if (txp->npkt > 0 || remaining > 1 || 3193 txp->score >= t4_tx_coalesce_pkts || 3194 atomic_load_int(&txq->eq.equiq) != 0) { 3195 if (vi->flags & TX_USES_VM_WR) 3196 rc = add_to_txpkts_vf(sc, txq, m0, avail, &snd); 3197 else 3198 rc = add_to_txpkts_pf(sc, txq, m0, avail, &snd); 3199 } else { 3200 snd = false; 3201 rc = EINVAL; 3202 } 3203 if (snd) { 3204 MPASS(txp->npkt > 0); 3205 for (i = 0; i < txp->npkt; i++) 3206 ETHER_BPF_MTAP(ifp, txp->mb[i]); 3207 if (txp->npkt > 1) { 3208 MPASS(avail >= tx_len16_to_desc(txp->len16)); 3209 if (vi->flags & TX_USES_VM_WR) 3210 n = write_txpkts_vm_wr(sc, txq); 3211 else 3212 n = write_txpkts_wr(sc, txq); 3213 } else { 3214 MPASS(avail >= 3215 tx_len16_to_desc(mbuf_len16(txp->mb[0]))); 3216 if (vi->flags & TX_USES_VM_WR) 3217 n = write_txpkt_vm_wr(sc, txq, 3218 txp->mb[0]); 3219 else 3220 n = write_txpkt_wr(sc, txq, txp->mb[0], 3221 avail); 3222 } 3223 MPASS(n <= SGE_MAX_WR_NDESC); 3224 avail -= n; 3225 dbdiff += n; 3226 wr = &eq->desc[eq->pidx]; 3227 IDXINCR(eq->pidx, n, eq->sidx); 3228 txp->npkt = 0; /* emptied */ 3229 } 3230 if (rc == 0) { 3231 /* m0 was coalesced into txq->txpkts. */ 3232 goto next_mbuf; 3233 } 3234 if (rc == EAGAIN) { 3235 /* 3236 * m0 is suitable for tx coalescing but could not be 3237 * combined with the existing txq->txpkts, which has now 3238 * been transmitted. Start a new txpkts with m0. 3239 */ 3240 MPASS(snd); 3241 MPASS(txp->npkt == 0); 3242 continue; 3243 } 3244 3245 MPASS(rc != 0 && rc != EAGAIN); 3246 MPASS(txp->npkt == 0); 3247 skip_coalescing: 3248 n = tx_len16_to_desc(mbuf_len16(m0)); 3249 if (__predict_false(avail < n)) { 3250 avail += reclaim_tx_descs(txq, min(n, 32)); 3251 if (avail < n) 3252 break; /* out of descriptors */ 3253 } 3254 3255 wr = &eq->desc[eq->pidx]; 3256 if (mbuf_cflags(m0) & MC_RAW_WR) { 3257 n = write_raw_wr(txq, wr, m0, avail); 3258 #ifdef KERN_TLS 3259 } else if (mbuf_cflags(m0) & MC_TLS) { 3260 ETHER_BPF_MTAP(ifp, m0); 3261 n = t6_ktls_write_wr(txq, wr, m0, mbuf_nsegs(m0), 3262 avail); 3263 #endif 3264 } else { 3265 ETHER_BPF_MTAP(ifp, m0); 3266 if (vi->flags & TX_USES_VM_WR) 3267 n = write_txpkt_vm_wr(sc, txq, m0); 3268 else 3269 n = write_txpkt_wr(sc, txq, m0, avail); 3270 } 3271 MPASS(n >= 1 && n <= avail); 3272 if (!(mbuf_cflags(m0) & MC_TLS)) 3273 MPASS(n <= SGE_MAX_WR_NDESC); 3274 3275 avail -= n; 3276 dbdiff += n; 3277 IDXINCR(eq->pidx, n, eq->sidx); 3278 3279 if (dbdiff >= 512 / EQ_ESIZE) { /* X_FETCHBURSTMAX_512B */ 3280 if (wr_can_update_eq(wr)) 3281 set_txupdate_flags(txq, avail, wr); 3282 ring_eq_db(sc, eq, dbdiff); 3283 avail += reclaim_tx_descs(txq, 32); 3284 dbdiff = 0; 3285 } 3286 next_mbuf: 3287 total++; 3288 remaining--; 3289 if (__predict_false(++cidx == r->size)) 3290 cidx = 0; 3291 } 3292 if (dbdiff != 0) { 3293 if (wr_can_update_eq(wr)) 3294 set_txupdate_flags(txq, avail, wr); 3295 ring_eq_db(sc, eq, dbdiff); 3296 reclaim_tx_descs(txq, 32); 3297 } else if (eq->pidx == eq->cidx && txp->npkt > 0 && 3298 atomic_load_int(&txq->eq.equiq) == 0) { 3299 /* 3300 * If nothing was submitted to the chip for tx (it was coalesced 3301 * into txpkts instead) and there is no tx update outstanding 3302 * then we need to send txpkts now. 3303 */ 3304 send_txpkts: 3305 MPASS(txp->npkt > 0); 3306 for (i = 0; i < txp->npkt; i++) 3307 ETHER_BPF_MTAP(ifp, txp->mb[i]); 3308 if (txp->npkt > 1) { 3309 MPASS(avail >= tx_len16_to_desc(txp->len16)); 3310 if (vi->flags & TX_USES_VM_WR) 3311 n = write_txpkts_vm_wr(sc, txq); 3312 else 3313 n = write_txpkts_wr(sc, txq); 3314 } else { 3315 MPASS(avail >= 3316 tx_len16_to_desc(mbuf_len16(txp->mb[0]))); 3317 if (vi->flags & TX_USES_VM_WR) 3318 n = write_txpkt_vm_wr(sc, txq, txp->mb[0]); 3319 else 3320 n = write_txpkt_wr(sc, txq, txp->mb[0], avail); 3321 } 3322 MPASS(n <= SGE_MAX_WR_NDESC); 3323 wr = &eq->desc[eq->pidx]; 3324 IDXINCR(eq->pidx, n, eq->sidx); 3325 txp->npkt = 0; /* emptied */ 3326 3327 MPASS(wr_can_update_eq(wr)); 3328 set_txupdate_flags(txq, avail - n, wr); 3329 ring_eq_db(sc, eq, n); 3330 reclaim_tx_descs(txq, 32); 3331 } 3332 *coalescing = txp->npkt > 0; 3333 3334 return (total); 3335 } 3336 3337 static inline void 3338 init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int pktc_idx, 3339 int qsize, int intr_idx, int cong) 3340 { 3341 3342 KASSERT(tmr_idx >= 0 && tmr_idx < SGE_NTIMERS, 3343 ("%s: bad tmr_idx %d", __func__, tmr_idx)); 3344 KASSERT(pktc_idx < SGE_NCOUNTERS, /* -ve is ok, means don't use */ 3345 ("%s: bad pktc_idx %d", __func__, pktc_idx)); 3346 KASSERT(intr_idx >= -1 && intr_idx < sc->intr_count, 3347 ("%s: bad intr_idx %d", __func__, intr_idx)); 3348 3349 iq->flags = 0; 3350 iq->state = IQS_DISABLED; 3351 iq->adapter = sc; 3352 iq->intr_params = V_QINTR_TIMER_IDX(tmr_idx); 3353 iq->intr_pktc_idx = SGE_NCOUNTERS - 1; 3354 if (pktc_idx >= 0) { 3355 iq->intr_params |= F_QINTR_CNT_EN; 3356 iq->intr_pktc_idx = pktc_idx; 3357 } 3358 iq->qsize = roundup2(qsize, 16); /* See FW_IQ_CMD/iqsize */ 3359 iq->sidx = iq->qsize - sc->params.sge.spg_len / IQ_ESIZE; 3360 iq->intr_idx = intr_idx; 3361 iq->cong = cong; 3362 } 3363 3364 static inline void 3365 init_fl(struct adapter *sc, struct sge_fl *fl, int qsize, int maxp, char *name) 3366 { 3367 struct sge_params *sp = &sc->params.sge; 3368 3369 fl->qsize = qsize; 3370 fl->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE; 3371 strlcpy(fl->lockname, name, sizeof(fl->lockname)); 3372 mtx_init(&fl->fl_lock, fl->lockname, NULL, MTX_DEF); 3373 if (sc->flags & BUF_PACKING_OK && 3374 ((!is_t4(sc) && buffer_packing) || /* T5+: enabled unless 0 */ 3375 (is_t4(sc) && buffer_packing == 1)))/* T4: disabled unless 1 */ 3376 fl->flags |= FL_BUF_PACKING; 3377 fl->zidx = find_refill_source(sc, maxp, fl->flags & FL_BUF_PACKING); 3378 fl->safe_zidx = sc->sge.safe_zidx; 3379 if (fl->flags & FL_BUF_PACKING) { 3380 fl->lowat = roundup2(sp->fl_starve_threshold2, 8); 3381 fl->buf_boundary = sp->pack_boundary; 3382 } else { 3383 fl->lowat = roundup2(sp->fl_starve_threshold, 8); 3384 fl->buf_boundary = 16; 3385 } 3386 if (fl_pad && fl->buf_boundary < sp->pad_boundary) 3387 fl->buf_boundary = sp->pad_boundary; 3388 } 3389 3390 static inline void 3391 init_eq(struct adapter *sc, struct sge_eq *eq, int eqtype, int qsize, 3392 uint8_t tx_chan, struct sge_iq *iq, char *name) 3393 { 3394 KASSERT(eqtype >= EQ_CTRL && eqtype <= EQ_OFLD, 3395 ("%s: bad qtype %d", __func__, eqtype)); 3396 3397 eq->type = eqtype; 3398 eq->tx_chan = tx_chan; 3399 eq->iq = iq; 3400 eq->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE; 3401 strlcpy(eq->lockname, name, sizeof(eq->lockname)); 3402 mtx_init(&eq->eq_lock, eq->lockname, NULL, MTX_DEF); 3403 } 3404 3405 int 3406 alloc_ring(struct adapter *sc, size_t len, bus_dma_tag_t *tag, 3407 bus_dmamap_t *map, bus_addr_t *pa, void **va) 3408 { 3409 int rc; 3410 3411 rc = bus_dma_tag_create(sc->dmat, 512, 0, BUS_SPACE_MAXADDR, 3412 BUS_SPACE_MAXADDR, NULL, NULL, len, 1, len, 0, NULL, NULL, tag); 3413 if (rc != 0) { 3414 CH_ERR(sc, "cannot allocate DMA tag: %d\n", rc); 3415 goto done; 3416 } 3417 3418 rc = bus_dmamem_alloc(*tag, va, 3419 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, map); 3420 if (rc != 0) { 3421 CH_ERR(sc, "cannot allocate DMA memory: %d\n", rc); 3422 goto done; 3423 } 3424 3425 rc = bus_dmamap_load(*tag, *map, *va, len, oneseg_dma_callback, pa, 0); 3426 if (rc != 0) { 3427 CH_ERR(sc, "cannot load DMA map: %d\n", rc); 3428 goto done; 3429 } 3430 done: 3431 if (rc) 3432 free_ring(sc, *tag, *map, *pa, *va); 3433 3434 return (rc); 3435 } 3436 3437 int 3438 free_ring(struct adapter *sc, bus_dma_tag_t tag, bus_dmamap_t map, 3439 bus_addr_t pa, void *va) 3440 { 3441 if (pa) 3442 bus_dmamap_unload(tag, map); 3443 if (va) 3444 bus_dmamem_free(tag, va, map); 3445 if (tag) 3446 bus_dma_tag_destroy(tag); 3447 3448 return (0); 3449 } 3450 3451 /* 3452 * Allocates the software resources (mainly memory and sysctl nodes) for an 3453 * ingress queue and an optional freelist. 3454 * 3455 * Sets IQ_SW_ALLOCATED and returns 0 on success. 3456 */ 3457 static int 3458 alloc_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl, 3459 struct sysctl_ctx_list *ctx, struct sysctl_oid *oid) 3460 { 3461 int rc; 3462 size_t len; 3463 struct adapter *sc = vi->adapter; 3464 3465 MPASS(!(iq->flags & IQ_SW_ALLOCATED)); 3466 3467 len = iq->qsize * IQ_ESIZE; 3468 rc = alloc_ring(sc, len, &iq->desc_tag, &iq->desc_map, &iq->ba, 3469 (void **)&iq->desc); 3470 if (rc != 0) 3471 return (rc); 3472 3473 if (fl) { 3474 len = fl->qsize * EQ_ESIZE; 3475 rc = alloc_ring(sc, len, &fl->desc_tag, &fl->desc_map, 3476 &fl->ba, (void **)&fl->desc); 3477 if (rc) { 3478 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, 3479 iq->desc); 3480 return (rc); 3481 } 3482 3483 /* Allocate space for one software descriptor per buffer. */ 3484 fl->sdesc = malloc(fl->sidx * 8 * sizeof(struct fl_sdesc), 3485 M_CXGBE, M_ZERO | M_WAITOK); 3486 3487 add_fl_sysctls(sc, ctx, oid, fl); 3488 iq->flags |= IQ_HAS_FL; 3489 } 3490 add_iq_sysctls(ctx, oid, iq); 3491 iq->flags |= IQ_SW_ALLOCATED; 3492 3493 return (0); 3494 } 3495 3496 /* 3497 * Frees all software resources (memory and locks) associated with an ingress 3498 * queue and an optional freelist. 3499 */ 3500 static void 3501 free_iq_fl(struct adapter *sc, struct sge_iq *iq, struct sge_fl *fl) 3502 { 3503 MPASS(iq->flags & IQ_SW_ALLOCATED); 3504 3505 if (fl) { 3506 MPASS(iq->flags & IQ_HAS_FL); 3507 free_ring(sc, fl->desc_tag, fl->desc_map, fl->ba, fl->desc); 3508 free_fl_buffers(sc, fl); 3509 free(fl->sdesc, M_CXGBE); 3510 mtx_destroy(&fl->fl_lock); 3511 bzero(fl, sizeof(*fl)); 3512 } 3513 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, iq->desc); 3514 bzero(iq, sizeof(*iq)); 3515 } 3516 3517 /* 3518 * Allocates a hardware ingress queue and an optional freelist that will be 3519 * associated with it. 3520 * 3521 * Returns errno on failure. Resources allocated up to that point may still be 3522 * allocated. Caller is responsible for cleanup in case this function fails. 3523 */ 3524 static int 3525 alloc_iq_fl_hwq(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl) 3526 { 3527 int rc, i, cntxt_id; 3528 struct fw_iq_cmd c; 3529 struct adapter *sc = vi->adapter; 3530 __be32 v = 0; 3531 3532 MPASS (!(iq->flags & IQ_HW_ALLOCATED)); 3533 3534 bzero(&c, sizeof(c)); 3535 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 3536 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) | 3537 V_FW_IQ_CMD_VFN(0)); 3538 3539 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART | 3540 FW_LEN16(c)); 3541 3542 /* Special handling for firmware event queue */ 3543 if (iq == &sc->sge.fwq) 3544 v |= F_FW_IQ_CMD_IQASYNCH; 3545 3546 if (iq->intr_idx < 0) { 3547 /* Forwarded interrupts, all headed to fwq */ 3548 v |= F_FW_IQ_CMD_IQANDST; 3549 v |= V_FW_IQ_CMD_IQANDSTINDEX(sc->sge.fwq.cntxt_id); 3550 } else { 3551 KASSERT(iq->intr_idx < sc->intr_count, 3552 ("%s: invalid direct intr_idx %d", __func__, iq->intr_idx)); 3553 v |= V_FW_IQ_CMD_IQANDSTINDEX(iq->intr_idx); 3554 } 3555 3556 bzero(iq->desc, iq->qsize * IQ_ESIZE); 3557 c.type_to_iqandstindex = htobe32(v | 3558 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) | 3559 V_FW_IQ_CMD_VIID(vi->viid) | 3560 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT)); 3561 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(vi->pi->tx_chan) | 3562 F_FW_IQ_CMD_IQGTSMODE | 3563 V_FW_IQ_CMD_IQINTCNTTHRESH(iq->intr_pktc_idx) | 3564 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4)); 3565 c.iqsize = htobe16(iq->qsize); 3566 c.iqaddr = htobe64(iq->ba); 3567 if (iq->cong >= 0) 3568 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN); 3569 3570 if (fl) { 3571 bzero(fl->desc, fl->sidx * EQ_ESIZE + sc->params.sge.spg_len); 3572 c.iqns_to_fl0congen |= 3573 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) | 3574 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO | 3575 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) | 3576 (fl->flags & FL_BUF_PACKING ? F_FW_IQ_CMD_FL0PACKEN : 3577 0)); 3578 if (iq->cong >= 0) { 3579 c.iqns_to_fl0congen |= 3580 htobe32(V_FW_IQ_CMD_FL0CNGCHMAP(iq->cong) | 3581 F_FW_IQ_CMD_FL0CONGCIF | 3582 F_FW_IQ_CMD_FL0CONGEN); 3583 } 3584 c.fl0dcaen_to_fl0cidxfthresh = 3585 htobe16(V_FW_IQ_CMD_FL0FBMIN(chip_id(sc) <= CHELSIO_T5 ? 3586 X_FETCHBURSTMIN_128B : X_FETCHBURSTMIN_64B_T6) | 3587 V_FW_IQ_CMD_FL0FBMAX(chip_id(sc) <= CHELSIO_T5 ? 3588 X_FETCHBURSTMAX_512B : X_FETCHBURSTMAX_256B)); 3589 c.fl0size = htobe16(fl->qsize); 3590 c.fl0addr = htobe64(fl->ba); 3591 } 3592 3593 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3594 if (rc != 0) { 3595 CH_ERR(sc, "failed to create hw ingress queue: %d\n", rc); 3596 return (rc); 3597 } 3598 3599 iq->cidx = 0; 3600 iq->gen = F_RSPD_GEN; 3601 iq->cntxt_id = be16toh(c.iqid); 3602 iq->abs_id = be16toh(c.physiqid); 3603 3604 cntxt_id = iq->cntxt_id - sc->sge.iq_start; 3605 if (cntxt_id >= sc->sge.iqmap_sz) { 3606 panic ("%s: iq->cntxt_id (%d) more than the max (%d)", __func__, 3607 cntxt_id, sc->sge.iqmap_sz - 1); 3608 } 3609 sc->sge.iqmap[cntxt_id] = iq; 3610 3611 if (fl) { 3612 u_int qid; 3613 #ifdef INVARIANTS 3614 MPASS(!(fl->flags & FL_BUF_RESUME)); 3615 for (i = 0; i < fl->sidx * 8; i++) 3616 MPASS(fl->sdesc[i].cl == NULL); 3617 #endif 3618 fl->cntxt_id = be16toh(c.fl0id); 3619 fl->pidx = fl->cidx = fl->hw_cidx = fl->dbidx = 0; 3620 fl->rx_offset = 0; 3621 fl->flags &= ~(FL_STARVING | FL_DOOMED); 3622 3623 cntxt_id = fl->cntxt_id - sc->sge.eq_start; 3624 if (cntxt_id >= sc->sge.eqmap_sz) { 3625 panic("%s: fl->cntxt_id (%d) more than the max (%d)", 3626 __func__, cntxt_id, sc->sge.eqmap_sz - 1); 3627 } 3628 sc->sge.eqmap[cntxt_id] = (void *)fl; 3629 3630 qid = fl->cntxt_id; 3631 if (isset(&sc->doorbells, DOORBELL_UDB)) { 3632 uint32_t s_qpp = sc->params.sge.eq_s_qpp; 3633 uint32_t mask = (1 << s_qpp) - 1; 3634 volatile uint8_t *udb; 3635 3636 udb = sc->udbs_base + UDBS_DB_OFFSET; 3637 udb += (qid >> s_qpp) << PAGE_SHIFT; 3638 qid &= mask; 3639 if (qid < PAGE_SIZE / UDBS_SEG_SIZE) { 3640 udb += qid << UDBS_SEG_SHIFT; 3641 qid = 0; 3642 } 3643 fl->udb = (volatile void *)udb; 3644 } 3645 fl->dbval = V_QID(qid) | sc->chip_params->sge_fl_db; 3646 3647 FL_LOCK(fl); 3648 /* Enough to make sure the SGE doesn't think it's starved */ 3649 refill_fl(sc, fl, fl->lowat); 3650 FL_UNLOCK(fl); 3651 } 3652 3653 if (chip_id(sc) >= CHELSIO_T5 && !(sc->flags & IS_VF) && iq->cong >= 0) { 3654 uint32_t param, val; 3655 3656 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 3657 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) | 3658 V_FW_PARAMS_PARAM_YZ(iq->cntxt_id); 3659 if (iq->cong == 0) 3660 val = 1 << 19; 3661 else { 3662 val = 2 << 19; 3663 for (i = 0; i < 4; i++) { 3664 if (iq->cong & (1 << i)) 3665 val |= 1 << (i << 2); 3666 } 3667 } 3668 3669 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 3670 if (rc != 0) { 3671 /* report error but carry on */ 3672 CH_ERR(sc, "failed to set congestion manager context " 3673 "for ingress queue %d: %d\n", iq->cntxt_id, rc); 3674 } 3675 } 3676 3677 /* Enable IQ interrupts */ 3678 atomic_store_rel_int(&iq->state, IQS_IDLE); 3679 t4_write_reg(sc, sc->sge_gts_reg, V_SEINTARM(iq->intr_params) | 3680 V_INGRESSQID(iq->cntxt_id)); 3681 3682 iq->flags |= IQ_HW_ALLOCATED; 3683 3684 return (0); 3685 } 3686 3687 static int 3688 free_iq_fl_hwq(struct adapter *sc, struct sge_iq *iq, struct sge_fl *fl) 3689 { 3690 int rc; 3691 3692 MPASS(iq->flags & IQ_HW_ALLOCATED); 3693 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0, FW_IQ_TYPE_FL_INT_CAP, 3694 iq->cntxt_id, fl ? fl->cntxt_id : 0xffff, 0xffff); 3695 if (rc != 0) { 3696 CH_ERR(sc, "failed to free iq %p: %d\n", iq, rc); 3697 return (rc); 3698 } 3699 iq->flags &= ~IQ_HW_ALLOCATED; 3700 3701 return (0); 3702 } 3703 3704 static void 3705 add_iq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid, 3706 struct sge_iq *iq) 3707 { 3708 struct sysctl_oid_list *children; 3709 3710 if (ctx == NULL || oid == NULL) 3711 return; 3712 3713 children = SYSCTL_CHILDREN(oid); 3714 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, &iq->ba, 3715 "bus address of descriptor ring"); 3716 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3717 iq->qsize * IQ_ESIZE, "descriptor ring size in bytes"); 3718 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "abs_id", CTLFLAG_RD, 3719 &iq->abs_id, 0, "absolute id of the queue"); 3720 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 3721 &iq->cntxt_id, 0, "SGE context id of the queue"); 3722 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &iq->cidx, 3723 0, "consumer index"); 3724 } 3725 3726 static void 3727 add_fl_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx, 3728 struct sysctl_oid *oid, struct sge_fl *fl) 3729 { 3730 struct sysctl_oid_list *children; 3731 3732 if (ctx == NULL || oid == NULL) 3733 return; 3734 3735 children = SYSCTL_CHILDREN(oid); 3736 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", 3737 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "freelist"); 3738 children = SYSCTL_CHILDREN(oid); 3739 3740 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, 3741 &fl->ba, "bus address of descriptor ring"); 3742 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3743 fl->sidx * EQ_ESIZE + sc->params.sge.spg_len, 3744 "desc ring size in bytes"); 3745 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 3746 &fl->cntxt_id, 0, "SGE context id of the freelist"); 3747 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "padding", CTLFLAG_RD, NULL, 3748 fl_pad ? 1 : 0, "padding enabled"); 3749 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "packing", CTLFLAG_RD, NULL, 3750 fl->flags & FL_BUF_PACKING ? 1 : 0, "packing enabled"); 3751 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &fl->cidx, 3752 0, "consumer index"); 3753 if (fl->flags & FL_BUF_PACKING) { 3754 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rx_offset", 3755 CTLFLAG_RD, &fl->rx_offset, 0, "packing rx offset"); 3756 } 3757 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &fl->pidx, 3758 0, "producer index"); 3759 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_allocated", 3760 CTLFLAG_RD, &fl->cl_allocated, "# of clusters allocated"); 3761 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_recycled", 3762 CTLFLAG_RD, &fl->cl_recycled, "# of clusters recycled"); 3763 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_fast_recycled", 3764 CTLFLAG_RD, &fl->cl_fast_recycled, "# of clusters recycled (fast)"); 3765 } 3766 3767 /* 3768 * Idempotent. 3769 */ 3770 static int 3771 alloc_fwq(struct adapter *sc) 3772 { 3773 int rc, intr_idx; 3774 struct sge_iq *fwq = &sc->sge.fwq; 3775 struct vi_info *vi = &sc->port[0]->vi[0]; 3776 3777 if (!(fwq->flags & IQ_SW_ALLOCATED)) { 3778 MPASS(!(fwq->flags & IQ_HW_ALLOCATED)); 3779 3780 if (sc->flags & IS_VF) 3781 intr_idx = 0; 3782 else 3783 intr_idx = sc->intr_count > 1 ? 1 : 0; 3784 init_iq(fwq, sc, 0, 0, FW_IQ_QSIZE, intr_idx, -1); 3785 rc = alloc_iq_fl(vi, fwq, NULL, &sc->ctx, sc->fwq_oid); 3786 if (rc != 0) { 3787 CH_ERR(sc, "failed to allocate fwq: %d\n", rc); 3788 return (rc); 3789 } 3790 MPASS(fwq->flags & IQ_SW_ALLOCATED); 3791 } 3792 3793 if (!(fwq->flags & IQ_HW_ALLOCATED)) { 3794 MPASS(fwq->flags & IQ_SW_ALLOCATED); 3795 3796 rc = alloc_iq_fl_hwq(vi, fwq, NULL); 3797 if (rc != 0) { 3798 CH_ERR(sc, "failed to create hw fwq: %d\n", rc); 3799 return (rc); 3800 } 3801 MPASS(fwq->flags & IQ_HW_ALLOCATED); 3802 } 3803 3804 return (0); 3805 } 3806 3807 /* 3808 * Idempotent. 3809 */ 3810 static void 3811 free_fwq(struct adapter *sc) 3812 { 3813 struct sge_iq *fwq = &sc->sge.fwq; 3814 3815 if (fwq->flags & IQ_HW_ALLOCATED) { 3816 MPASS(fwq->flags & IQ_SW_ALLOCATED); 3817 free_iq_fl_hwq(sc, fwq, NULL); 3818 MPASS(!(fwq->flags & IQ_HW_ALLOCATED)); 3819 } 3820 3821 if (fwq->flags & IQ_SW_ALLOCATED) { 3822 MPASS(!(fwq->flags & IQ_HW_ALLOCATED)); 3823 free_iq_fl(sc, fwq, NULL); 3824 MPASS(!(fwq->flags & IQ_SW_ALLOCATED)); 3825 } 3826 } 3827 3828 /* 3829 * Idempotent. 3830 */ 3831 static int 3832 alloc_ctrlq(struct adapter *sc, int idx) 3833 { 3834 int rc; 3835 char name[16]; 3836 struct sysctl_oid *oid; 3837 struct sge_wrq *ctrlq = &sc->sge.ctrlq[idx]; 3838 3839 MPASS(idx < sc->params.nports); 3840 3841 if (!(ctrlq->eq.flags & EQ_SW_ALLOCATED)) { 3842 MPASS(!(ctrlq->eq.flags & EQ_HW_ALLOCATED)); 3843 3844 snprintf(name, sizeof(name), "%d", idx); 3845 oid = SYSCTL_ADD_NODE(&sc->ctx, SYSCTL_CHILDREN(sc->ctrlq_oid), 3846 OID_AUTO, name, CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 3847 "ctrl queue"); 3848 3849 snprintf(name, sizeof(name), "%s ctrlq%d", 3850 device_get_nameunit(sc->dev), idx); 3851 init_eq(sc, &ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE, 3852 sc->port[idx]->tx_chan, &sc->sge.fwq, name); 3853 rc = alloc_wrq(sc, NULL, ctrlq, &sc->ctx, oid); 3854 if (rc != 0) { 3855 CH_ERR(sc, "failed to allocate ctrlq%d: %d\n", idx, rc); 3856 sysctl_remove_oid(oid, 1, 1); 3857 return (rc); 3858 } 3859 MPASS(ctrlq->eq.flags & EQ_SW_ALLOCATED); 3860 } 3861 3862 if (!(ctrlq->eq.flags & EQ_HW_ALLOCATED)) { 3863 MPASS(ctrlq->eq.flags & EQ_SW_ALLOCATED); 3864 3865 rc = alloc_eq_hwq(sc, NULL, &ctrlq->eq); 3866 if (rc != 0) { 3867 CH_ERR(sc, "failed to create hw ctrlq%d: %d\n", idx, rc); 3868 return (rc); 3869 } 3870 MPASS(ctrlq->eq.flags & EQ_HW_ALLOCATED); 3871 } 3872 3873 return (0); 3874 } 3875 3876 /* 3877 * Idempotent. 3878 */ 3879 static void 3880 free_ctrlq(struct adapter *sc, int idx) 3881 { 3882 struct sge_wrq *ctrlq = &sc->sge.ctrlq[idx]; 3883 3884 if (ctrlq->eq.flags & EQ_HW_ALLOCATED) { 3885 MPASS(ctrlq->eq.flags & EQ_SW_ALLOCATED); 3886 free_eq_hwq(sc, NULL, &ctrlq->eq); 3887 MPASS(!(ctrlq->eq.flags & EQ_HW_ALLOCATED)); 3888 } 3889 3890 if (ctrlq->eq.flags & EQ_SW_ALLOCATED) { 3891 MPASS(!(ctrlq->eq.flags & EQ_HW_ALLOCATED)); 3892 free_wrq(sc, ctrlq); 3893 MPASS(!(ctrlq->eq.flags & EQ_SW_ALLOCATED)); 3894 } 3895 } 3896 3897 int 3898 tnl_cong(struct port_info *pi, int drop) 3899 { 3900 3901 if (drop == -1) 3902 return (-1); 3903 else if (drop == 1) 3904 return (0); 3905 else 3906 return (pi->rx_e_chan_map); 3907 } 3908 3909 /* 3910 * Idempotent. 3911 */ 3912 static int 3913 alloc_rxq(struct vi_info *vi, struct sge_rxq *rxq, int idx, int intr_idx, 3914 int maxp) 3915 { 3916 int rc; 3917 struct adapter *sc = vi->adapter; 3918 struct ifnet *ifp = vi->ifp; 3919 struct sysctl_oid *oid; 3920 char name[16]; 3921 3922 if (!(rxq->iq.flags & IQ_SW_ALLOCATED)) { 3923 MPASS(!(rxq->iq.flags & IQ_HW_ALLOCATED)); 3924 #if defined(INET) || defined(INET6) 3925 rc = tcp_lro_init_args(&rxq->lro, ifp, lro_entries, lro_mbufs); 3926 if (rc != 0) 3927 return (rc); 3928 MPASS(rxq->lro.ifp == ifp); /* also indicates LRO init'ed */ 3929 3930 if (ifp->if_capenable & IFCAP_LRO) 3931 rxq->iq.flags |= IQ_LRO_ENABLED; 3932 #endif 3933 if (ifp->if_capenable & IFCAP_HWRXTSTMP) 3934 rxq->iq.flags |= IQ_RX_TIMESTAMP; 3935 rxq->ifp = ifp; 3936 3937 snprintf(name, sizeof(name), "%d", idx); 3938 oid = SYSCTL_ADD_NODE(&vi->ctx, SYSCTL_CHILDREN(vi->rxq_oid), 3939 OID_AUTO, name, CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 3940 "rx queue"); 3941 3942 init_iq(&rxq->iq, sc, vi->tmr_idx, vi->pktc_idx, vi->qsize_rxq, 3943 intr_idx, tnl_cong(vi->pi, cong_drop)); 3944 snprintf(name, sizeof(name), "%s rxq%d-fl", 3945 device_get_nameunit(vi->dev), idx); 3946 init_fl(sc, &rxq->fl, vi->qsize_rxq / 8, maxp, name); 3947 rc = alloc_iq_fl(vi, &rxq->iq, &rxq->fl, &vi->ctx, oid); 3948 if (rc != 0) { 3949 CH_ERR(vi, "failed to allocate rxq%d: %d\n", idx, rc); 3950 sysctl_remove_oid(oid, 1, 1); 3951 #if defined(INET) || defined(INET6) 3952 tcp_lro_free(&rxq->lro); 3953 rxq->lro.ifp = NULL; 3954 #endif 3955 return (rc); 3956 } 3957 MPASS(rxq->iq.flags & IQ_SW_ALLOCATED); 3958 add_rxq_sysctls(&vi->ctx, oid, rxq); 3959 } 3960 3961 if (!(rxq->iq.flags & IQ_HW_ALLOCATED)) { 3962 MPASS(rxq->iq.flags & IQ_SW_ALLOCATED); 3963 rc = alloc_iq_fl_hwq(vi, &rxq->iq, &rxq->fl); 3964 if (rc != 0) { 3965 CH_ERR(vi, "failed to create hw rxq%d: %d\n", idx, rc); 3966 return (rc); 3967 } 3968 MPASS(rxq->iq.flags & IQ_HW_ALLOCATED); 3969 3970 if (idx == 0) 3971 sc->sge.iq_base = rxq->iq.abs_id - rxq->iq.cntxt_id; 3972 else 3973 KASSERT(rxq->iq.cntxt_id + sc->sge.iq_base == rxq->iq.abs_id, 3974 ("iq_base mismatch")); 3975 KASSERT(sc->sge.iq_base == 0 || sc->flags & IS_VF, 3976 ("PF with non-zero iq_base")); 3977 3978 /* 3979 * The freelist is just barely above the starvation threshold 3980 * right now, fill it up a bit more. 3981 */ 3982 FL_LOCK(&rxq->fl); 3983 refill_fl(sc, &rxq->fl, 128); 3984 FL_UNLOCK(&rxq->fl); 3985 } 3986 3987 return (0); 3988 } 3989 3990 /* 3991 * Idempotent. 3992 */ 3993 static void 3994 free_rxq(struct vi_info *vi, struct sge_rxq *rxq) 3995 { 3996 if (rxq->iq.flags & IQ_HW_ALLOCATED) { 3997 MPASS(rxq->iq.flags & IQ_SW_ALLOCATED); 3998 free_iq_fl_hwq(vi->adapter, &rxq->iq, &rxq->fl); 3999 MPASS(!(rxq->iq.flags & IQ_HW_ALLOCATED)); 4000 } 4001 4002 if (rxq->iq.flags & IQ_SW_ALLOCATED) { 4003 MPASS(!(rxq->iq.flags & IQ_HW_ALLOCATED)); 4004 #if defined(INET) || defined(INET6) 4005 tcp_lro_free(&rxq->lro); 4006 #endif 4007 free_iq_fl(vi->adapter, &rxq->iq, &rxq->fl); 4008 MPASS(!(rxq->iq.flags & IQ_SW_ALLOCATED)); 4009 bzero(rxq, sizeof(*rxq)); 4010 } 4011 } 4012 4013 static void 4014 add_rxq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid, 4015 struct sge_rxq *rxq) 4016 { 4017 struct sysctl_oid_list *children; 4018 4019 if (ctx == NULL || oid == NULL) 4020 return; 4021 4022 children = SYSCTL_CHILDREN(oid); 4023 #if defined(INET) || defined(INET6) 4024 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "lro_queued", CTLFLAG_RD, 4025 &rxq->lro.lro_queued, 0, NULL); 4026 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "lro_flushed", CTLFLAG_RD, 4027 &rxq->lro.lro_flushed, 0, NULL); 4028 #endif 4029 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "rxcsum", CTLFLAG_RD, 4030 &rxq->rxcsum, "# of times hardware assisted with checksum"); 4031 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "vlan_extraction", CTLFLAG_RD, 4032 &rxq->vlan_extraction, "# of times hardware extracted 802.1Q tag"); 4033 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "vxlan_rxcsum", CTLFLAG_RD, 4034 &rxq->vxlan_rxcsum, 4035 "# of times hardware assisted with inner checksum (VXLAN)"); 4036 } 4037 4038 #ifdef TCP_OFFLOAD 4039 /* 4040 * Idempotent. 4041 */ 4042 static int 4043 alloc_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq, int idx, 4044 int intr_idx, int maxp) 4045 { 4046 int rc; 4047 struct adapter *sc = vi->adapter; 4048 struct sysctl_oid *oid; 4049 char name[16]; 4050 4051 if (!(ofld_rxq->iq.flags & IQ_SW_ALLOCATED)) { 4052 MPASS(!(ofld_rxq->iq.flags & IQ_HW_ALLOCATED)); 4053 4054 snprintf(name, sizeof(name), "%d", idx); 4055 oid = SYSCTL_ADD_NODE(&vi->ctx, 4056 SYSCTL_CHILDREN(vi->ofld_rxq_oid), OID_AUTO, name, 4057 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "offload rx queue"); 4058 4059 init_iq(&ofld_rxq->iq, sc, vi->ofld_tmr_idx, vi->ofld_pktc_idx, 4060 vi->qsize_rxq, intr_idx, 0); 4061 snprintf(name, sizeof(name), "%s ofld_rxq%d-fl", 4062 device_get_nameunit(vi->dev), idx); 4063 init_fl(sc, &ofld_rxq->fl, vi->qsize_rxq / 8, maxp, name); 4064 rc = alloc_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl, &vi->ctx, 4065 oid); 4066 if (rc != 0) { 4067 CH_ERR(vi, "failed to allocate ofld_rxq%d: %d\n", idx, 4068 rc); 4069 sysctl_remove_oid(oid, 1, 1); 4070 return (rc); 4071 } 4072 MPASS(ofld_rxq->iq.flags & IQ_SW_ALLOCATED); 4073 ofld_rxq->rx_iscsi_ddp_setup_ok = counter_u64_alloc(M_WAITOK); 4074 ofld_rxq->rx_iscsi_ddp_setup_error = 4075 counter_u64_alloc(M_WAITOK); 4076 add_ofld_rxq_sysctls(&vi->ctx, oid, ofld_rxq); 4077 } 4078 4079 if (!(ofld_rxq->iq.flags & IQ_HW_ALLOCATED)) { 4080 MPASS(ofld_rxq->iq.flags & IQ_SW_ALLOCATED); 4081 rc = alloc_iq_fl_hwq(vi, &ofld_rxq->iq, &ofld_rxq->fl); 4082 if (rc != 0) { 4083 CH_ERR(vi, "failed to create hw ofld_rxq%d: %d\n", idx, 4084 rc); 4085 return (rc); 4086 } 4087 MPASS(ofld_rxq->iq.flags & IQ_HW_ALLOCATED); 4088 } 4089 return (rc); 4090 } 4091 4092 /* 4093 * Idempotent. 4094 */ 4095 static void 4096 free_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq) 4097 { 4098 if (ofld_rxq->iq.flags & IQ_HW_ALLOCATED) { 4099 MPASS(ofld_rxq->iq.flags & IQ_SW_ALLOCATED); 4100 free_iq_fl_hwq(vi->adapter, &ofld_rxq->iq, &ofld_rxq->fl); 4101 MPASS(!(ofld_rxq->iq.flags & IQ_HW_ALLOCATED)); 4102 } 4103 4104 if (ofld_rxq->iq.flags & IQ_SW_ALLOCATED) { 4105 MPASS(!(ofld_rxq->iq.flags & IQ_HW_ALLOCATED)); 4106 free_iq_fl(vi->adapter, &ofld_rxq->iq, &ofld_rxq->fl); 4107 MPASS(!(ofld_rxq->iq.flags & IQ_SW_ALLOCATED)); 4108 counter_u64_free(ofld_rxq->rx_iscsi_ddp_setup_ok); 4109 counter_u64_free(ofld_rxq->rx_iscsi_ddp_setup_error); 4110 bzero(ofld_rxq, sizeof(*ofld_rxq)); 4111 } 4112 } 4113 4114 static void 4115 add_ofld_rxq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid, 4116 struct sge_ofld_rxq *ofld_rxq) 4117 { 4118 struct sysctl_oid_list *children; 4119 4120 if (ctx == NULL || oid == NULL) 4121 return; 4122 4123 children = SYSCTL_CHILDREN(oid); 4124 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 4125 "rx_toe_tls_records", CTLFLAG_RD, &ofld_rxq->rx_toe_tls_records, 4126 "# of TOE TLS records received"); 4127 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 4128 "rx_toe_tls_octets", CTLFLAG_RD, &ofld_rxq->rx_toe_tls_octets, 4129 "# of payload octets in received TOE TLS records"); 4130 4131 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "iscsi", 4132 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TOE iSCSI statistics"); 4133 children = SYSCTL_CHILDREN(oid); 4134 4135 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "ddp_setup_ok", 4136 CTLFLAG_RD, &ofld_rxq->rx_iscsi_ddp_setup_ok, 4137 "# of times DDP buffer was setup successfully."); 4138 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "ddp_setup_error", 4139 CTLFLAG_RD, &ofld_rxq->rx_iscsi_ddp_setup_error, 4140 "# of times DDP buffer setup failed."); 4141 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "ddp_octets", 4142 CTLFLAG_RD, &ofld_rxq->rx_iscsi_ddp_octets, 0, 4143 "# of octets placed directly"); 4144 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "ddp_pdus", 4145 CTLFLAG_RD, &ofld_rxq->rx_iscsi_ddp_pdus, 0, 4146 "# of PDUs with data placed directly."); 4147 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "fl_octets", 4148 CTLFLAG_RD, &ofld_rxq->rx_iscsi_fl_octets, 0, 4149 "# of data octets delivered in freelist"); 4150 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "fl_pdus", 4151 CTLFLAG_RD, &ofld_rxq->rx_iscsi_fl_pdus, 0, 4152 "# of PDUs with data delivered in freelist"); 4153 } 4154 #endif 4155 4156 /* 4157 * Returns a reasonable automatic cidx flush threshold for a given queue size. 4158 */ 4159 static u_int 4160 qsize_to_fthresh(int qsize) 4161 { 4162 u_int fthresh; 4163 4164 while (!powerof2(qsize)) 4165 qsize++; 4166 fthresh = ilog2(qsize); 4167 if (fthresh > X_CIDXFLUSHTHRESH_128) 4168 fthresh = X_CIDXFLUSHTHRESH_128; 4169 4170 return (fthresh); 4171 } 4172 4173 static int 4174 ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq) 4175 { 4176 int rc, cntxt_id; 4177 struct fw_eq_ctrl_cmd c; 4178 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 4179 4180 bzero(&c, sizeof(c)); 4181 4182 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | F_FW_CMD_REQUEST | 4183 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_CTRL_CMD_PFN(sc->pf) | 4184 V_FW_EQ_CTRL_CMD_VFN(0)); 4185 c.alloc_to_len16 = htobe32(F_FW_EQ_CTRL_CMD_ALLOC | 4186 F_FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c)); 4187 c.cmpliqid_eqid = htonl(V_FW_EQ_CTRL_CMD_CMPLIQID(eq->iqid)); 4188 c.physeqid_pkd = htobe32(0); 4189 c.fetchszm_to_iqid = 4190 htobe32(V_FW_EQ_CTRL_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 4191 V_FW_EQ_CTRL_CMD_PCIECHN(eq->tx_chan) | 4192 F_FW_EQ_CTRL_CMD_FETCHRO | V_FW_EQ_CTRL_CMD_IQID(eq->iqid)); 4193 c.dcaen_to_eqsize = 4194 htobe32(V_FW_EQ_CTRL_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ? 4195 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) | 4196 V_FW_EQ_CTRL_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 4197 V_FW_EQ_CTRL_CMD_CIDXFTHRESH(qsize_to_fthresh(qsize)) | 4198 V_FW_EQ_CTRL_CMD_EQSIZE(qsize)); 4199 c.eqaddr = htobe64(eq->ba); 4200 4201 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 4202 if (rc != 0) { 4203 CH_ERR(sc, "failed to create hw ctrlq for tx_chan %d: %d\n", 4204 eq->tx_chan, rc); 4205 return (rc); 4206 } 4207 4208 eq->cntxt_id = G_FW_EQ_CTRL_CMD_EQID(be32toh(c.cmpliqid_eqid)); 4209 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 4210 if (cntxt_id >= sc->sge.eqmap_sz) 4211 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 4212 cntxt_id, sc->sge.eqmap_sz - 1); 4213 sc->sge.eqmap[cntxt_id] = eq; 4214 4215 return (rc); 4216 } 4217 4218 static int 4219 eth_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 4220 { 4221 int rc, cntxt_id; 4222 struct fw_eq_eth_cmd c; 4223 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 4224 4225 bzero(&c, sizeof(c)); 4226 4227 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST | 4228 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) | 4229 V_FW_EQ_ETH_CMD_VFN(0)); 4230 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC | 4231 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c)); 4232 c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE | 4233 F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(vi->viid)); 4234 c.fetchszm_to_iqid = 4235 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) | 4236 V_FW_EQ_ETH_CMD_PCIECHN(eq->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO | 4237 V_FW_EQ_ETH_CMD_IQID(eq->iqid)); 4238 c.dcaen_to_eqsize = 4239 htobe32(V_FW_EQ_ETH_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ? 4240 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) | 4241 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 4242 V_FW_EQ_ETH_CMD_EQSIZE(qsize)); 4243 c.eqaddr = htobe64(eq->ba); 4244 4245 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 4246 if (rc != 0) { 4247 device_printf(vi->dev, 4248 "failed to create Ethernet egress queue: %d\n", rc); 4249 return (rc); 4250 } 4251 4252 eq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd)); 4253 eq->abs_id = G_FW_EQ_ETH_CMD_PHYSEQID(be32toh(c.physeqid_pkd)); 4254 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 4255 if (cntxt_id >= sc->sge.eqmap_sz) 4256 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 4257 cntxt_id, sc->sge.eqmap_sz - 1); 4258 sc->sge.eqmap[cntxt_id] = eq; 4259 4260 return (rc); 4261 } 4262 4263 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 4264 static int 4265 ofld_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 4266 { 4267 int rc, cntxt_id; 4268 struct fw_eq_ofld_cmd c; 4269 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 4270 4271 bzero(&c, sizeof(c)); 4272 4273 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | F_FW_CMD_REQUEST | 4274 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_OFLD_CMD_PFN(sc->pf) | 4275 V_FW_EQ_OFLD_CMD_VFN(0)); 4276 c.alloc_to_len16 = htonl(F_FW_EQ_OFLD_CMD_ALLOC | 4277 F_FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c)); 4278 c.fetchszm_to_iqid = 4279 htonl(V_FW_EQ_OFLD_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 4280 V_FW_EQ_OFLD_CMD_PCIECHN(eq->tx_chan) | 4281 F_FW_EQ_OFLD_CMD_FETCHRO | V_FW_EQ_OFLD_CMD_IQID(eq->iqid)); 4282 c.dcaen_to_eqsize = 4283 htobe32(V_FW_EQ_OFLD_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ? 4284 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) | 4285 V_FW_EQ_OFLD_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 4286 V_FW_EQ_OFLD_CMD_CIDXFTHRESH(qsize_to_fthresh(qsize)) | 4287 V_FW_EQ_OFLD_CMD_EQSIZE(qsize)); 4288 c.eqaddr = htobe64(eq->ba); 4289 4290 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 4291 if (rc != 0) { 4292 device_printf(vi->dev, 4293 "failed to create egress queue for TCP offload: %d\n", rc); 4294 return (rc); 4295 } 4296 4297 eq->cntxt_id = G_FW_EQ_OFLD_CMD_EQID(be32toh(c.eqid_pkd)); 4298 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 4299 if (cntxt_id >= sc->sge.eqmap_sz) 4300 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 4301 cntxt_id, sc->sge.eqmap_sz - 1); 4302 sc->sge.eqmap[cntxt_id] = eq; 4303 4304 return (rc); 4305 } 4306 #endif 4307 4308 /* SW only */ 4309 static int 4310 alloc_eq(struct adapter *sc, struct sge_eq *eq, struct sysctl_ctx_list *ctx, 4311 struct sysctl_oid *oid) 4312 { 4313 int rc, qsize; 4314 size_t len; 4315 4316 MPASS(!(eq->flags & EQ_SW_ALLOCATED)); 4317 4318 qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 4319 len = qsize * EQ_ESIZE; 4320 rc = alloc_ring(sc, len, &eq->desc_tag, &eq->desc_map, &eq->ba, 4321 (void **)&eq->desc); 4322 if (rc) 4323 return (rc); 4324 if (ctx != NULL && oid != NULL) 4325 add_eq_sysctls(sc, ctx, oid, eq); 4326 eq->flags |= EQ_SW_ALLOCATED; 4327 4328 return (0); 4329 } 4330 4331 /* SW only */ 4332 static void 4333 free_eq(struct adapter *sc, struct sge_eq *eq) 4334 { 4335 MPASS(eq->flags & EQ_SW_ALLOCATED); 4336 MPASS(eq->pidx == eq->cidx); 4337 4338 free_ring(sc, eq->desc_tag, eq->desc_map, eq->ba, eq->desc); 4339 mtx_destroy(&eq->eq_lock); 4340 bzero(eq, sizeof(*eq)); 4341 } 4342 4343 static void 4344 add_eq_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx, 4345 struct sysctl_oid *oid, struct sge_eq *eq) 4346 { 4347 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 4348 4349 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, &eq->ba, 4350 "bus address of descriptor ring"); 4351 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 4352 eq->sidx * EQ_ESIZE + sc->params.sge.spg_len, 4353 "desc ring size in bytes"); 4354 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "abs_id", CTLFLAG_RD, 4355 &eq->abs_id, 0, "absolute id of the queue"); 4356 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 4357 &eq->cntxt_id, 0, "SGE context id of the queue"); 4358 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &eq->cidx, 4359 0, "consumer index"); 4360 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &eq->pidx, 4361 0, "producer index"); 4362 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL, 4363 eq->sidx, "status page index"); 4364 } 4365 4366 static int 4367 alloc_eq_hwq(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 4368 { 4369 int rc; 4370 4371 MPASS(!(eq->flags & EQ_HW_ALLOCATED)); 4372 4373 eq->iqid = eq->iq->cntxt_id; 4374 eq->pidx = eq->cidx = eq->dbidx = 0; 4375 /* Note that equeqidx is not used with sge_wrq (OFLD/CTRL) queues. */ 4376 eq->equeqidx = 0; 4377 eq->doorbells = sc->doorbells; 4378 bzero(eq->desc, eq->sidx * EQ_ESIZE + sc->params.sge.spg_len); 4379 4380 switch (eq->type) { 4381 case EQ_CTRL: 4382 rc = ctrl_eq_alloc(sc, eq); 4383 break; 4384 4385 case EQ_ETH: 4386 rc = eth_eq_alloc(sc, vi, eq); 4387 break; 4388 4389 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 4390 case EQ_OFLD: 4391 rc = ofld_eq_alloc(sc, vi, eq); 4392 break; 4393 #endif 4394 4395 default: 4396 panic("%s: invalid eq type %d.", __func__, eq->type); 4397 } 4398 if (rc != 0) { 4399 CH_ERR(sc, "failed to allocate egress queue(%d): %d\n", 4400 eq->type, rc); 4401 return (rc); 4402 } 4403 4404 if (isset(&eq->doorbells, DOORBELL_UDB) || 4405 isset(&eq->doorbells, DOORBELL_UDBWC) || 4406 isset(&eq->doorbells, DOORBELL_WCWR)) { 4407 uint32_t s_qpp = sc->params.sge.eq_s_qpp; 4408 uint32_t mask = (1 << s_qpp) - 1; 4409 volatile uint8_t *udb; 4410 4411 udb = sc->udbs_base + UDBS_DB_OFFSET; 4412 udb += (eq->cntxt_id >> s_qpp) << PAGE_SHIFT; /* pg offset */ 4413 eq->udb_qid = eq->cntxt_id & mask; /* id in page */ 4414 if (eq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE) 4415 clrbit(&eq->doorbells, DOORBELL_WCWR); 4416 else { 4417 udb += eq->udb_qid << UDBS_SEG_SHIFT; /* seg offset */ 4418 eq->udb_qid = 0; 4419 } 4420 eq->udb = (volatile void *)udb; 4421 } 4422 4423 eq->flags |= EQ_HW_ALLOCATED; 4424 return (0); 4425 } 4426 4427 static int 4428 free_eq_hwq(struct adapter *sc, struct vi_info *vi __unused, struct sge_eq *eq) 4429 { 4430 int rc; 4431 4432 MPASS(eq->flags & EQ_HW_ALLOCATED); 4433 4434 switch (eq->type) { 4435 case EQ_CTRL: 4436 rc = -t4_ctrl_eq_free(sc, sc->mbox, sc->pf, 0, eq->cntxt_id); 4437 break; 4438 case EQ_ETH: 4439 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0, eq->cntxt_id); 4440 break; 4441 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 4442 case EQ_OFLD: 4443 rc = -t4_ofld_eq_free(sc, sc->mbox, sc->pf, 0, eq->cntxt_id); 4444 break; 4445 #endif 4446 default: 4447 panic("%s: invalid eq type %d.", __func__, eq->type); 4448 } 4449 if (rc != 0) { 4450 CH_ERR(sc, "failed to free eq (type %d): %d\n", eq->type, rc); 4451 return (rc); 4452 } 4453 eq->flags &= ~EQ_HW_ALLOCATED; 4454 4455 return (0); 4456 } 4457 4458 static int 4459 alloc_wrq(struct adapter *sc, struct vi_info *vi, struct sge_wrq *wrq, 4460 struct sysctl_ctx_list *ctx, struct sysctl_oid *oid) 4461 { 4462 struct sge_eq *eq = &wrq->eq; 4463 int rc; 4464 4465 MPASS(!(eq->flags & EQ_SW_ALLOCATED)); 4466 4467 rc = alloc_eq(sc, eq, ctx, oid); 4468 if (rc) 4469 return (rc); 4470 MPASS(eq->flags & EQ_SW_ALLOCATED); 4471 /* Can't fail after this. */ 4472 4473 wrq->adapter = sc; 4474 TASK_INIT(&wrq->wrq_tx_task, 0, wrq_tx_drain, wrq); 4475 TAILQ_INIT(&wrq->incomplete_wrs); 4476 STAILQ_INIT(&wrq->wr_list); 4477 wrq->nwr_pending = 0; 4478 wrq->ndesc_needed = 0; 4479 add_wrq_sysctls(ctx, oid, wrq); 4480 4481 return (0); 4482 } 4483 4484 static void 4485 free_wrq(struct adapter *sc, struct sge_wrq *wrq) 4486 { 4487 free_eq(sc, &wrq->eq); 4488 MPASS(wrq->nwr_pending == 0); 4489 bzero(wrq, sizeof(*wrq)); 4490 } 4491 4492 static void 4493 add_wrq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid, 4494 struct sge_wrq *wrq) 4495 { 4496 struct sysctl_oid_list *children; 4497 4498 if (ctx == NULL || oid == NULL) 4499 return; 4500 4501 children = SYSCTL_CHILDREN(oid); 4502 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_direct", CTLFLAG_RD, 4503 &wrq->tx_wrs_direct, "# of work requests (direct)"); 4504 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_copied", CTLFLAG_RD, 4505 &wrq->tx_wrs_copied, "# of work requests (copied)"); 4506 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_sspace", CTLFLAG_RD, 4507 &wrq->tx_wrs_ss, "# of work requests (copied from scratch space)"); 4508 } 4509 4510 /* 4511 * Idempotent. 4512 */ 4513 static int 4514 alloc_txq(struct vi_info *vi, struct sge_txq *txq, int idx) 4515 { 4516 int rc, iqidx; 4517 struct port_info *pi = vi->pi; 4518 struct adapter *sc = vi->adapter; 4519 struct sge_eq *eq = &txq->eq; 4520 struct txpkts *txp; 4521 char name[16]; 4522 struct sysctl_oid *oid; 4523 4524 if (!(eq->flags & EQ_SW_ALLOCATED)) { 4525 MPASS(!(eq->flags & EQ_HW_ALLOCATED)); 4526 4527 snprintf(name, sizeof(name), "%d", idx); 4528 oid = SYSCTL_ADD_NODE(&vi->ctx, SYSCTL_CHILDREN(vi->txq_oid), 4529 OID_AUTO, name, CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 4530 "tx queue"); 4531 4532 iqidx = vi->first_rxq + (idx % vi->nrxq); 4533 snprintf(name, sizeof(name), "%s txq%d", 4534 device_get_nameunit(vi->dev), idx); 4535 init_eq(sc, &txq->eq, EQ_ETH, vi->qsize_txq, pi->tx_chan, 4536 &sc->sge.rxq[iqidx].iq, name); 4537 4538 rc = mp_ring_alloc(&txq->r, eq->sidx, txq, eth_tx, 4539 can_resume_eth_tx, M_CXGBE, &eq->eq_lock, M_WAITOK); 4540 if (rc != 0) { 4541 CH_ERR(vi, "failed to allocate mp_ring for txq%d: %d\n", 4542 idx, rc); 4543 failed: 4544 sysctl_remove_oid(oid, 1, 1); 4545 return (rc); 4546 } 4547 4548 rc = alloc_eq(sc, eq, &vi->ctx, oid); 4549 if (rc) { 4550 CH_ERR(vi, "failed to allocate txq%d: %d\n", idx, rc); 4551 mp_ring_free(txq->r); 4552 goto failed; 4553 } 4554 MPASS(eq->flags & EQ_SW_ALLOCATED); 4555 /* Can't fail after this point. */ 4556 4557 TASK_INIT(&txq->tx_reclaim_task, 0, tx_reclaim, eq); 4558 txq->ifp = vi->ifp; 4559 txq->gl = sglist_alloc(TX_SGL_SEGS, M_WAITOK); 4560 txq->sdesc = malloc(eq->sidx * sizeof(struct tx_sdesc), M_CXGBE, 4561 M_ZERO | M_WAITOK); 4562 4563 add_txq_sysctls(vi, &vi->ctx, oid, txq); 4564 } 4565 4566 if (!(eq->flags & EQ_HW_ALLOCATED)) { 4567 MPASS(eq->flags & EQ_SW_ALLOCATED); 4568 rc = alloc_eq_hwq(sc, vi, eq); 4569 if (rc != 0) { 4570 CH_ERR(vi, "failed to create hw txq%d: %d\n", idx, rc); 4571 return (rc); 4572 } 4573 MPASS(eq->flags & EQ_HW_ALLOCATED); 4574 /* Can't fail after this point. */ 4575 4576 if (idx == 0) 4577 sc->sge.eq_base = eq->abs_id - eq->cntxt_id; 4578 else 4579 KASSERT(eq->cntxt_id + sc->sge.eq_base == eq->abs_id, 4580 ("eq_base mismatch")); 4581 KASSERT(sc->sge.eq_base == 0 || sc->flags & IS_VF, 4582 ("PF with non-zero eq_base")); 4583 4584 txp = &txq->txp; 4585 MPASS(nitems(txp->mb) >= sc->params.max_pkts_per_eth_tx_pkts_wr); 4586 txq->txp.max_npkt = min(nitems(txp->mb), 4587 sc->params.max_pkts_per_eth_tx_pkts_wr); 4588 if (vi->flags & TX_USES_VM_WR && !(sc->flags & IS_VF)) 4589 txq->txp.max_npkt--; 4590 4591 if (vi->flags & TX_USES_VM_WR) 4592 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) | 4593 V_TXPKT_INTF(pi->tx_chan)); 4594 else 4595 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) | 4596 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(sc->pf) | 4597 V_TXPKT_VF(vi->vin) | V_TXPKT_VF_VLD(vi->vfvld)); 4598 4599 txq->tc_idx = -1; 4600 } 4601 4602 return (0); 4603 } 4604 4605 /* 4606 * Idempotent. 4607 */ 4608 static void 4609 free_txq(struct vi_info *vi, struct sge_txq *txq) 4610 { 4611 struct adapter *sc = vi->adapter; 4612 struct sge_eq *eq = &txq->eq; 4613 4614 if (eq->flags & EQ_HW_ALLOCATED) { 4615 MPASS(eq->flags & EQ_SW_ALLOCATED); 4616 free_eq_hwq(sc, NULL, eq); 4617 MPASS(!(eq->flags & EQ_HW_ALLOCATED)); 4618 } 4619 4620 if (eq->flags & EQ_SW_ALLOCATED) { 4621 MPASS(!(eq->flags & EQ_HW_ALLOCATED)); 4622 sglist_free(txq->gl); 4623 free(txq->sdesc, M_CXGBE); 4624 mp_ring_free(txq->r); 4625 free_eq(sc, eq); 4626 MPASS(!(eq->flags & EQ_SW_ALLOCATED)); 4627 bzero(txq, sizeof(*txq)); 4628 } 4629 } 4630 4631 static void 4632 add_txq_sysctls(struct vi_info *vi, struct sysctl_ctx_list *ctx, 4633 struct sysctl_oid *oid, struct sge_txq *txq) 4634 { 4635 struct adapter *sc; 4636 struct sysctl_oid_list *children; 4637 4638 if (ctx == NULL || oid == NULL) 4639 return; 4640 4641 sc = vi->adapter; 4642 children = SYSCTL_CHILDREN(oid); 4643 4644 mp_ring_sysctls(txq->r, ctx, children); 4645 4646 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tc", 4647 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, txq - sc->sge.txq, 4648 sysctl_tc, "I", "traffic class (-1 means none)"); 4649 4650 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txcsum", CTLFLAG_RD, 4651 &txq->txcsum, "# of times hardware assisted with checksum"); 4652 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "vlan_insertion", CTLFLAG_RD, 4653 &txq->vlan_insertion, "# of times hardware inserted 802.1Q tag"); 4654 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tso_wrs", CTLFLAG_RD, 4655 &txq->tso_wrs, "# of TSO work requests"); 4656 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "imm_wrs", CTLFLAG_RD, 4657 &txq->imm_wrs, "# of work requests with immediate data"); 4658 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "sgl_wrs", CTLFLAG_RD, 4659 &txq->sgl_wrs, "# of work requests with direct SGL"); 4660 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkt_wrs", CTLFLAG_RD, 4661 &txq->txpkt_wrs, "# of txpkt work requests (one pkt/WR)"); 4662 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkts0_wrs", CTLFLAG_RD, 4663 &txq->txpkts0_wrs, "# of txpkts (type 0) work requests"); 4664 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkts1_wrs", CTLFLAG_RD, 4665 &txq->txpkts1_wrs, "# of txpkts (type 1) work requests"); 4666 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkts0_pkts", CTLFLAG_RD, 4667 &txq->txpkts0_pkts, 4668 "# of frames tx'd using type0 txpkts work requests"); 4669 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkts1_pkts", CTLFLAG_RD, 4670 &txq->txpkts1_pkts, 4671 "# of frames tx'd using type1 txpkts work requests"); 4672 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkts_flush", CTLFLAG_RD, 4673 &txq->txpkts_flush, 4674 "# of times txpkts had to be flushed out by an egress-update"); 4675 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "raw_wrs", CTLFLAG_RD, 4676 &txq->raw_wrs, "# of raw work requests (non-packets)"); 4677 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "vxlan_tso_wrs", CTLFLAG_RD, 4678 &txq->vxlan_tso_wrs, "# of VXLAN TSO work requests"); 4679 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "vxlan_txcsum", CTLFLAG_RD, 4680 &txq->vxlan_txcsum, 4681 "# of times hardware assisted with inner checksums (VXLAN)"); 4682 4683 #ifdef KERN_TLS 4684 if (is_ktls(sc)) { 4685 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_records", 4686 CTLFLAG_RD, &txq->kern_tls_records, 4687 "# of NIC TLS records transmitted"); 4688 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_short", 4689 CTLFLAG_RD, &txq->kern_tls_short, 4690 "# of short NIC TLS records transmitted"); 4691 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_partial", 4692 CTLFLAG_RD, &txq->kern_tls_partial, 4693 "# of partial NIC TLS records transmitted"); 4694 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_full", 4695 CTLFLAG_RD, &txq->kern_tls_full, 4696 "# of full NIC TLS records transmitted"); 4697 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_octets", 4698 CTLFLAG_RD, &txq->kern_tls_octets, 4699 "# of payload octets in transmitted NIC TLS records"); 4700 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_waste", 4701 CTLFLAG_RD, &txq->kern_tls_waste, 4702 "# of octets DMAd but not transmitted in NIC TLS records"); 4703 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_options", 4704 CTLFLAG_RD, &txq->kern_tls_options, 4705 "# of NIC TLS options-only packets transmitted"); 4706 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_header", 4707 CTLFLAG_RD, &txq->kern_tls_header, 4708 "# of NIC TLS header-only packets transmitted"); 4709 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_fin", 4710 CTLFLAG_RD, &txq->kern_tls_fin, 4711 "# of NIC TLS FIN-only packets transmitted"); 4712 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_fin_short", 4713 CTLFLAG_RD, &txq->kern_tls_fin_short, 4714 "# of NIC TLS padded FIN packets on short TLS records"); 4715 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_cbc", 4716 CTLFLAG_RD, &txq->kern_tls_cbc, 4717 "# of NIC TLS sessions using AES-CBC"); 4718 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_gcm", 4719 CTLFLAG_RD, &txq->kern_tls_gcm, 4720 "# of NIC TLS sessions using AES-GCM"); 4721 } 4722 #endif 4723 } 4724 4725 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 4726 /* 4727 * Idempotent. 4728 */ 4729 static int 4730 alloc_ofld_txq(struct vi_info *vi, struct sge_ofld_txq *ofld_txq, int idx) 4731 { 4732 struct sysctl_oid *oid; 4733 struct port_info *pi = vi->pi; 4734 struct adapter *sc = vi->adapter; 4735 struct sge_eq *eq = &ofld_txq->wrq.eq; 4736 int rc, iqidx; 4737 char name[16]; 4738 4739 MPASS(idx >= 0); 4740 MPASS(idx < vi->nofldtxq); 4741 4742 if (!(eq->flags & EQ_SW_ALLOCATED)) { 4743 snprintf(name, sizeof(name), "%d", idx); 4744 oid = SYSCTL_ADD_NODE(&vi->ctx, 4745 SYSCTL_CHILDREN(vi->ofld_txq_oid), OID_AUTO, name, 4746 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "offload tx queue"); 4747 4748 snprintf(name, sizeof(name), "%s ofld_txq%d", 4749 device_get_nameunit(vi->dev), idx); 4750 if (vi->nofldrxq > 0) { 4751 iqidx = vi->first_ofld_rxq + (idx % vi->nofldrxq); 4752 init_eq(sc, eq, EQ_OFLD, vi->qsize_txq, pi->tx_chan, 4753 &sc->sge.ofld_rxq[iqidx].iq, name); 4754 } else { 4755 iqidx = vi->first_rxq + (idx % vi->nrxq); 4756 init_eq(sc, eq, EQ_OFLD, vi->qsize_txq, pi->tx_chan, 4757 &sc->sge.rxq[iqidx].iq, name); 4758 } 4759 4760 rc = alloc_wrq(sc, vi, &ofld_txq->wrq, &vi->ctx, oid); 4761 if (rc != 0) { 4762 CH_ERR(vi, "failed to allocate ofld_txq%d: %d\n", idx, 4763 rc); 4764 sysctl_remove_oid(oid, 1, 1); 4765 return (rc); 4766 } 4767 MPASS(eq->flags & EQ_SW_ALLOCATED); 4768 /* Can't fail after this point. */ 4769 4770 ofld_txq->tx_iscsi_pdus = counter_u64_alloc(M_WAITOK); 4771 ofld_txq->tx_iscsi_octets = counter_u64_alloc(M_WAITOK); 4772 ofld_txq->tx_toe_tls_records = counter_u64_alloc(M_WAITOK); 4773 ofld_txq->tx_toe_tls_octets = counter_u64_alloc(M_WAITOK); 4774 add_ofld_txq_sysctls(&vi->ctx, oid, ofld_txq); 4775 } 4776 4777 if (!(eq->flags & EQ_HW_ALLOCATED)) { 4778 rc = alloc_eq_hwq(sc, vi, eq); 4779 if (rc != 0) { 4780 CH_ERR(vi, "failed to create hw ofld_txq%d: %d\n", idx, 4781 rc); 4782 return (rc); 4783 } 4784 MPASS(eq->flags & EQ_HW_ALLOCATED); 4785 } 4786 4787 return (0); 4788 } 4789 4790 /* 4791 * Idempotent. 4792 */ 4793 static void 4794 free_ofld_txq(struct vi_info *vi, struct sge_ofld_txq *ofld_txq) 4795 { 4796 struct adapter *sc = vi->adapter; 4797 struct sge_eq *eq = &ofld_txq->wrq.eq; 4798 4799 if (eq->flags & EQ_HW_ALLOCATED) { 4800 MPASS(eq->flags & EQ_SW_ALLOCATED); 4801 free_eq_hwq(sc, NULL, eq); 4802 MPASS(!(eq->flags & EQ_HW_ALLOCATED)); 4803 } 4804 4805 if (eq->flags & EQ_SW_ALLOCATED) { 4806 MPASS(!(eq->flags & EQ_HW_ALLOCATED)); 4807 counter_u64_free(ofld_txq->tx_iscsi_pdus); 4808 counter_u64_free(ofld_txq->tx_iscsi_octets); 4809 counter_u64_free(ofld_txq->tx_toe_tls_records); 4810 counter_u64_free(ofld_txq->tx_toe_tls_octets); 4811 free_wrq(sc, &ofld_txq->wrq); 4812 MPASS(!(eq->flags & EQ_SW_ALLOCATED)); 4813 bzero(ofld_txq, sizeof(*ofld_txq)); 4814 } 4815 } 4816 4817 static void 4818 add_ofld_txq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid, 4819 struct sge_ofld_txq *ofld_txq) 4820 { 4821 struct sysctl_oid_list *children; 4822 4823 if (ctx == NULL || oid == NULL) 4824 return; 4825 4826 children = SYSCTL_CHILDREN(oid); 4827 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_iscsi_pdus", 4828 CTLFLAG_RD, &ofld_txq->tx_iscsi_pdus, 4829 "# of iSCSI PDUs transmitted"); 4830 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_iscsi_octets", 4831 CTLFLAG_RD, &ofld_txq->tx_iscsi_octets, 4832 "# of payload octets in transmitted iSCSI PDUs"); 4833 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_toe_tls_records", 4834 CTLFLAG_RD, &ofld_txq->tx_toe_tls_records, 4835 "# of TOE TLS records transmitted"); 4836 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_toe_tls_octets", 4837 CTLFLAG_RD, &ofld_txq->tx_toe_tls_octets, 4838 "# of payload octets in transmitted TOE TLS records"); 4839 } 4840 #endif 4841 4842 static void 4843 oneseg_dma_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error) 4844 { 4845 bus_addr_t *ba = arg; 4846 4847 KASSERT(nseg == 1, 4848 ("%s meant for single segment mappings only.", __func__)); 4849 4850 *ba = error ? 0 : segs->ds_addr; 4851 } 4852 4853 static inline void 4854 ring_fl_db(struct adapter *sc, struct sge_fl *fl) 4855 { 4856 uint32_t n, v; 4857 4858 n = IDXDIFF(fl->pidx >> 3, fl->dbidx, fl->sidx); 4859 MPASS(n > 0); 4860 4861 wmb(); 4862 v = fl->dbval | V_PIDX(n); 4863 if (fl->udb) 4864 *fl->udb = htole32(v); 4865 else 4866 t4_write_reg(sc, sc->sge_kdoorbell_reg, v); 4867 IDXINCR(fl->dbidx, n, fl->sidx); 4868 } 4869 4870 /* 4871 * Fills up the freelist by allocating up to 'n' buffers. Buffers that are 4872 * recycled do not count towards this allocation budget. 4873 * 4874 * Returns non-zero to indicate that this freelist should be added to the list 4875 * of starving freelists. 4876 */ 4877 static int 4878 refill_fl(struct adapter *sc, struct sge_fl *fl, int n) 4879 { 4880 __be64 *d; 4881 struct fl_sdesc *sd; 4882 uintptr_t pa; 4883 caddr_t cl; 4884 struct rx_buf_info *rxb; 4885 struct cluster_metadata *clm; 4886 uint16_t max_pidx, zidx = fl->zidx; 4887 uint16_t hw_cidx = fl->hw_cidx; /* stable snapshot */ 4888 4889 FL_LOCK_ASSERT_OWNED(fl); 4890 4891 /* 4892 * We always stop at the beginning of the hardware descriptor that's just 4893 * before the one with the hw cidx. This is to avoid hw pidx = hw cidx, 4894 * which would mean an empty freelist to the chip. 4895 */ 4896 max_pidx = __predict_false(hw_cidx == 0) ? fl->sidx - 1 : hw_cidx - 1; 4897 if (fl->pidx == max_pidx * 8) 4898 return (0); 4899 4900 d = &fl->desc[fl->pidx]; 4901 sd = &fl->sdesc[fl->pidx]; 4902 rxb = &sc->sge.rx_buf_info[zidx]; 4903 4904 while (n > 0) { 4905 4906 if (sd->cl != NULL) { 4907 4908 if (sd->nmbuf == 0) { 4909 /* 4910 * Fast recycle without involving any atomics on 4911 * the cluster's metadata (if the cluster has 4912 * metadata). This happens when all frames 4913 * received in the cluster were small enough to 4914 * fit within a single mbuf each. 4915 */ 4916 fl->cl_fast_recycled++; 4917 goto recycled; 4918 } 4919 4920 /* 4921 * Cluster is guaranteed to have metadata. Clusters 4922 * without metadata always take the fast recycle path 4923 * when they're recycled. 4924 */ 4925 clm = cl_metadata(sd); 4926 MPASS(clm != NULL); 4927 4928 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) { 4929 fl->cl_recycled++; 4930 counter_u64_add(extfree_rels, 1); 4931 goto recycled; 4932 } 4933 sd->cl = NULL; /* gave up my reference */ 4934 } 4935 MPASS(sd->cl == NULL); 4936 cl = uma_zalloc(rxb->zone, M_NOWAIT); 4937 if (__predict_false(cl == NULL)) { 4938 if (zidx != fl->safe_zidx) { 4939 zidx = fl->safe_zidx; 4940 rxb = &sc->sge.rx_buf_info[zidx]; 4941 cl = uma_zalloc(rxb->zone, M_NOWAIT); 4942 } 4943 if (cl == NULL) 4944 break; 4945 } 4946 fl->cl_allocated++; 4947 n--; 4948 4949 pa = pmap_kextract((vm_offset_t)cl); 4950 sd->cl = cl; 4951 sd->zidx = zidx; 4952 4953 if (fl->flags & FL_BUF_PACKING) { 4954 *d = htobe64(pa | rxb->hwidx2); 4955 sd->moff = rxb->size2; 4956 } else { 4957 *d = htobe64(pa | rxb->hwidx1); 4958 sd->moff = 0; 4959 } 4960 recycled: 4961 sd->nmbuf = 0; 4962 d++; 4963 sd++; 4964 if (__predict_false((++fl->pidx & 7) == 0)) { 4965 uint16_t pidx = fl->pidx >> 3; 4966 4967 if (__predict_false(pidx == fl->sidx)) { 4968 fl->pidx = 0; 4969 pidx = 0; 4970 sd = fl->sdesc; 4971 d = fl->desc; 4972 } 4973 if (n < 8 || pidx == max_pidx) 4974 break; 4975 4976 if (IDXDIFF(pidx, fl->dbidx, fl->sidx) >= 4) 4977 ring_fl_db(sc, fl); 4978 } 4979 } 4980 4981 if ((fl->pidx >> 3) != fl->dbidx) 4982 ring_fl_db(sc, fl); 4983 4984 return (FL_RUNNING_LOW(fl) && !(fl->flags & FL_STARVING)); 4985 } 4986 4987 /* 4988 * Attempt to refill all starving freelists. 4989 */ 4990 static void 4991 refill_sfl(void *arg) 4992 { 4993 struct adapter *sc = arg; 4994 struct sge_fl *fl, *fl_temp; 4995 4996 mtx_assert(&sc->sfl_lock, MA_OWNED); 4997 TAILQ_FOREACH_SAFE(fl, &sc->sfl, link, fl_temp) { 4998 FL_LOCK(fl); 4999 refill_fl(sc, fl, 64); 5000 if (FL_NOT_RUNNING_LOW(fl) || fl->flags & FL_DOOMED) { 5001 TAILQ_REMOVE(&sc->sfl, fl, link); 5002 fl->flags &= ~FL_STARVING; 5003 } 5004 FL_UNLOCK(fl); 5005 } 5006 5007 if (!TAILQ_EMPTY(&sc->sfl)) 5008 callout_schedule(&sc->sfl_callout, hz / 5); 5009 } 5010 5011 /* 5012 * Release the driver's reference on all buffers in the given freelist. Buffers 5013 * with kernel references cannot be freed and will prevent the driver from being 5014 * unloaded safely. 5015 */ 5016 void 5017 free_fl_buffers(struct adapter *sc, struct sge_fl *fl) 5018 { 5019 struct fl_sdesc *sd; 5020 struct cluster_metadata *clm; 5021 int i; 5022 5023 sd = fl->sdesc; 5024 for (i = 0; i < fl->sidx * 8; i++, sd++) { 5025 if (sd->cl == NULL) 5026 continue; 5027 5028 if (sd->nmbuf == 0) 5029 uma_zfree(sc->sge.rx_buf_info[sd->zidx].zone, sd->cl); 5030 else if (fl->flags & FL_BUF_PACKING) { 5031 clm = cl_metadata(sd); 5032 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) { 5033 uma_zfree(sc->sge.rx_buf_info[sd->zidx].zone, 5034 sd->cl); 5035 counter_u64_add(extfree_rels, 1); 5036 } 5037 } 5038 sd->cl = NULL; 5039 } 5040 5041 if (fl->flags & FL_BUF_RESUME) { 5042 m_freem(fl->m0); 5043 fl->flags &= ~FL_BUF_RESUME; 5044 } 5045 } 5046 5047 static inline void 5048 get_pkt_gl(struct mbuf *m, struct sglist *gl) 5049 { 5050 int rc; 5051 5052 M_ASSERTPKTHDR(m); 5053 5054 sglist_reset(gl); 5055 rc = sglist_append_mbuf(gl, m); 5056 if (__predict_false(rc != 0)) { 5057 panic("%s: mbuf %p (%d segs) was vetted earlier but now fails " 5058 "with %d.", __func__, m, mbuf_nsegs(m), rc); 5059 } 5060 5061 KASSERT(gl->sg_nseg == mbuf_nsegs(m), 5062 ("%s: nsegs changed for mbuf %p from %d to %d", __func__, m, 5063 mbuf_nsegs(m), gl->sg_nseg)); 5064 #if 0 /* vm_wr not readily available here. */ 5065 KASSERT(gl->sg_nseg > 0 && gl->sg_nseg <= max_nsegs_allowed(m, vm_wr), 5066 ("%s: %d segments, should have been 1 <= nsegs <= %d", __func__, 5067 gl->sg_nseg, max_nsegs_allowed(m, vm_wr))); 5068 #endif 5069 } 5070 5071 /* 5072 * len16 for a txpkt WR with a GL. Includes the firmware work request header. 5073 */ 5074 static inline u_int 5075 txpkt_len16(u_int nsegs, const u_int extra) 5076 { 5077 u_int n; 5078 5079 MPASS(nsegs > 0); 5080 5081 nsegs--; /* first segment is part of ulptx_sgl */ 5082 n = extra + sizeof(struct fw_eth_tx_pkt_wr) + 5083 sizeof(struct cpl_tx_pkt_core) + 5084 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 5085 5086 return (howmany(n, 16)); 5087 } 5088 5089 /* 5090 * len16 for a txpkt_vm WR with a GL. Includes the firmware work 5091 * request header. 5092 */ 5093 static inline u_int 5094 txpkt_vm_len16(u_int nsegs, const u_int extra) 5095 { 5096 u_int n; 5097 5098 MPASS(nsegs > 0); 5099 5100 nsegs--; /* first segment is part of ulptx_sgl */ 5101 n = extra + sizeof(struct fw_eth_tx_pkt_vm_wr) + 5102 sizeof(struct cpl_tx_pkt_core) + 5103 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 5104 5105 return (howmany(n, 16)); 5106 } 5107 5108 static inline void 5109 calculate_mbuf_len16(struct mbuf *m, bool vm_wr) 5110 { 5111 const int lso = sizeof(struct cpl_tx_pkt_lso_core); 5112 const int tnl_lso = sizeof(struct cpl_tx_tnl_lso); 5113 5114 if (vm_wr) { 5115 if (needs_tso(m)) 5116 set_mbuf_len16(m, txpkt_vm_len16(mbuf_nsegs(m), lso)); 5117 else 5118 set_mbuf_len16(m, txpkt_vm_len16(mbuf_nsegs(m), 0)); 5119 return; 5120 } 5121 5122 if (needs_tso(m)) { 5123 if (needs_vxlan_tso(m)) 5124 set_mbuf_len16(m, txpkt_len16(mbuf_nsegs(m), tnl_lso)); 5125 else 5126 set_mbuf_len16(m, txpkt_len16(mbuf_nsegs(m), lso)); 5127 } else 5128 set_mbuf_len16(m, txpkt_len16(mbuf_nsegs(m), 0)); 5129 } 5130 5131 /* 5132 * len16 for a txpkts type 0 WR with a GL. Does not include the firmware work 5133 * request header. 5134 */ 5135 static inline u_int 5136 txpkts0_len16(u_int nsegs) 5137 { 5138 u_int n; 5139 5140 MPASS(nsegs > 0); 5141 5142 nsegs--; /* first segment is part of ulptx_sgl */ 5143 n = sizeof(struct ulp_txpkt) + sizeof(struct ulptx_idata) + 5144 sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl) + 5145 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 5146 5147 return (howmany(n, 16)); 5148 } 5149 5150 /* 5151 * len16 for a txpkts type 1 WR with a GL. Does not include the firmware work 5152 * request header. 5153 */ 5154 static inline u_int 5155 txpkts1_len16(void) 5156 { 5157 u_int n; 5158 5159 n = sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl); 5160 5161 return (howmany(n, 16)); 5162 } 5163 5164 static inline u_int 5165 imm_payload(u_int ndesc) 5166 { 5167 u_int n; 5168 5169 n = ndesc * EQ_ESIZE - sizeof(struct fw_eth_tx_pkt_wr) - 5170 sizeof(struct cpl_tx_pkt_core); 5171 5172 return (n); 5173 } 5174 5175 static inline uint64_t 5176 csum_to_ctrl(struct adapter *sc, struct mbuf *m) 5177 { 5178 uint64_t ctrl; 5179 int csum_type, l2hlen, l3hlen; 5180 int x, y; 5181 static const int csum_types[3][2] = { 5182 {TX_CSUM_TCPIP, TX_CSUM_TCPIP6}, 5183 {TX_CSUM_UDPIP, TX_CSUM_UDPIP6}, 5184 {TX_CSUM_IP, 0} 5185 }; 5186 5187 M_ASSERTPKTHDR(m); 5188 5189 if (!needs_hwcsum(m)) 5190 return (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS); 5191 5192 MPASS(m->m_pkthdr.l2hlen >= ETHER_HDR_LEN); 5193 MPASS(m->m_pkthdr.l3hlen >= sizeof(struct ip)); 5194 5195 if (needs_vxlan_csum(m)) { 5196 MPASS(m->m_pkthdr.l4hlen > 0); 5197 MPASS(m->m_pkthdr.l5hlen > 0); 5198 MPASS(m->m_pkthdr.inner_l2hlen >= ETHER_HDR_LEN); 5199 MPASS(m->m_pkthdr.inner_l3hlen >= sizeof(struct ip)); 5200 5201 l2hlen = m->m_pkthdr.l2hlen + m->m_pkthdr.l3hlen + 5202 m->m_pkthdr.l4hlen + m->m_pkthdr.l5hlen + 5203 m->m_pkthdr.inner_l2hlen - ETHER_HDR_LEN; 5204 l3hlen = m->m_pkthdr.inner_l3hlen; 5205 } else { 5206 l2hlen = m->m_pkthdr.l2hlen - ETHER_HDR_LEN; 5207 l3hlen = m->m_pkthdr.l3hlen; 5208 } 5209 5210 ctrl = 0; 5211 if (!needs_l3_csum(m)) 5212 ctrl |= F_TXPKT_IPCSUM_DIS; 5213 5214 if (m->m_pkthdr.csum_flags & (CSUM_IP_TCP | CSUM_INNER_IP_TCP | 5215 CSUM_IP6_TCP | CSUM_INNER_IP6_TCP)) 5216 x = 0; /* TCP */ 5217 else if (m->m_pkthdr.csum_flags & (CSUM_IP_UDP | CSUM_INNER_IP_UDP | 5218 CSUM_IP6_UDP | CSUM_INNER_IP6_UDP)) 5219 x = 1; /* UDP */ 5220 else 5221 x = 2; 5222 5223 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_IP_TCP | CSUM_IP_UDP | 5224 CSUM_INNER_IP | CSUM_INNER_IP_TCP | CSUM_INNER_IP_UDP)) 5225 y = 0; /* IPv4 */ 5226 else { 5227 MPASS(m->m_pkthdr.csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | 5228 CSUM_INNER_IP6_TCP | CSUM_INNER_IP6_UDP)); 5229 y = 1; /* IPv6 */ 5230 } 5231 /* 5232 * needs_hwcsum returned true earlier so there must be some kind of 5233 * checksum to calculate. 5234 */ 5235 csum_type = csum_types[x][y]; 5236 MPASS(csum_type != 0); 5237 if (csum_type == TX_CSUM_IP) 5238 ctrl |= F_TXPKT_L4CSUM_DIS; 5239 ctrl |= V_TXPKT_CSUM_TYPE(csum_type) | V_TXPKT_IPHDR_LEN(l3hlen); 5240 if (chip_id(sc) <= CHELSIO_T5) 5241 ctrl |= V_TXPKT_ETHHDR_LEN(l2hlen); 5242 else 5243 ctrl |= V_T6_TXPKT_ETHHDR_LEN(l2hlen); 5244 5245 return (ctrl); 5246 } 5247 5248 static inline void * 5249 write_lso_cpl(void *cpl, struct mbuf *m0) 5250 { 5251 struct cpl_tx_pkt_lso_core *lso; 5252 uint32_t ctrl; 5253 5254 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 5255 m0->m_pkthdr.l4hlen > 0, 5256 ("%s: mbuf %p needs TSO but missing header lengths", 5257 __func__, m0)); 5258 5259 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | 5260 F_LSO_FIRST_SLICE | F_LSO_LAST_SLICE | 5261 V_LSO_ETHHDR_LEN((m0->m_pkthdr.l2hlen - ETHER_HDR_LEN) >> 2) | 5262 V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) | 5263 V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2); 5264 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 5265 ctrl |= F_LSO_IPV6; 5266 5267 lso = cpl; 5268 lso->lso_ctrl = htobe32(ctrl); 5269 lso->ipid_ofst = htobe16(0); 5270 lso->mss = htobe16(m0->m_pkthdr.tso_segsz); 5271 lso->seqno_offset = htobe32(0); 5272 lso->len = htobe32(m0->m_pkthdr.len); 5273 5274 return (lso + 1); 5275 } 5276 5277 static void * 5278 write_tnl_lso_cpl(void *cpl, struct mbuf *m0) 5279 { 5280 struct cpl_tx_tnl_lso *tnl_lso = cpl; 5281 uint32_t ctrl; 5282 5283 KASSERT(m0->m_pkthdr.inner_l2hlen > 0 && 5284 m0->m_pkthdr.inner_l3hlen > 0 && m0->m_pkthdr.inner_l4hlen > 0 && 5285 m0->m_pkthdr.inner_l5hlen > 0, 5286 ("%s: mbuf %p needs VXLAN_TSO but missing inner header lengths", 5287 __func__, m0)); 5288 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 5289 m0->m_pkthdr.l4hlen > 0 && m0->m_pkthdr.l5hlen > 0, 5290 ("%s: mbuf %p needs VXLAN_TSO but missing outer header lengths", 5291 __func__, m0)); 5292 5293 /* Outer headers. */ 5294 ctrl = V_CPL_TX_TNL_LSO_OPCODE(CPL_TX_TNL_LSO) | 5295 F_CPL_TX_TNL_LSO_FIRST | F_CPL_TX_TNL_LSO_LAST | 5296 V_CPL_TX_TNL_LSO_ETHHDRLENOUT( 5297 (m0->m_pkthdr.l2hlen - ETHER_HDR_LEN) >> 2) | 5298 V_CPL_TX_TNL_LSO_IPHDRLENOUT(m0->m_pkthdr.l3hlen >> 2) | 5299 F_CPL_TX_TNL_LSO_IPLENSETOUT; 5300 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 5301 ctrl |= F_CPL_TX_TNL_LSO_IPV6OUT; 5302 else { 5303 ctrl |= F_CPL_TX_TNL_LSO_IPHDRCHKOUT | 5304 F_CPL_TX_TNL_LSO_IPIDINCOUT; 5305 } 5306 tnl_lso->op_to_IpIdSplitOut = htobe32(ctrl); 5307 tnl_lso->IpIdOffsetOut = 0; 5308 tnl_lso->UdpLenSetOut_to_TnlHdrLen = 5309 htobe16(F_CPL_TX_TNL_LSO_UDPCHKCLROUT | 5310 F_CPL_TX_TNL_LSO_UDPLENSETOUT | 5311 V_CPL_TX_TNL_LSO_TNLHDRLEN(m0->m_pkthdr.l2hlen + 5312 m0->m_pkthdr.l3hlen + m0->m_pkthdr.l4hlen + 5313 m0->m_pkthdr.l5hlen) | 5314 V_CPL_TX_TNL_LSO_TNLTYPE(TX_TNL_TYPE_VXLAN)); 5315 tnl_lso->r1 = 0; 5316 5317 /* Inner headers. */ 5318 ctrl = V_CPL_TX_TNL_LSO_ETHHDRLEN( 5319 (m0->m_pkthdr.inner_l2hlen - ETHER_HDR_LEN) >> 2) | 5320 V_CPL_TX_TNL_LSO_IPHDRLEN(m0->m_pkthdr.inner_l3hlen >> 2) | 5321 V_CPL_TX_TNL_LSO_TCPHDRLEN(m0->m_pkthdr.inner_l4hlen >> 2); 5322 if (m0->m_pkthdr.inner_l3hlen == sizeof(struct ip6_hdr)) 5323 ctrl |= F_CPL_TX_TNL_LSO_IPV6; 5324 tnl_lso->Flow_to_TcpHdrLen = htobe32(ctrl); 5325 tnl_lso->IpIdOffset = 0; 5326 tnl_lso->IpIdSplit_to_Mss = 5327 htobe16(V_CPL_TX_TNL_LSO_MSS(m0->m_pkthdr.tso_segsz)); 5328 tnl_lso->TCPSeqOffset = 0; 5329 tnl_lso->EthLenOffset_Size = 5330 htobe32(V_CPL_TX_TNL_LSO_SIZE(m0->m_pkthdr.len)); 5331 5332 return (tnl_lso + 1); 5333 } 5334 5335 #define VM_TX_L2HDR_LEN 16 /* ethmacdst to vlantci */ 5336 5337 /* 5338 * Write a VM txpkt WR for this packet to the hardware descriptors, update the 5339 * software descriptor, and advance the pidx. It is guaranteed that enough 5340 * descriptors are available. 5341 * 5342 * The return value is the # of hardware descriptors used. 5343 */ 5344 static u_int 5345 write_txpkt_vm_wr(struct adapter *sc, struct sge_txq *txq, struct mbuf *m0) 5346 { 5347 struct sge_eq *eq; 5348 struct fw_eth_tx_pkt_vm_wr *wr; 5349 struct tx_sdesc *txsd; 5350 struct cpl_tx_pkt_core *cpl; 5351 uint32_t ctrl; /* used in many unrelated places */ 5352 uint64_t ctrl1; 5353 int len16, ndesc, pktlen, nsegs; 5354 caddr_t dst; 5355 5356 TXQ_LOCK_ASSERT_OWNED(txq); 5357 M_ASSERTPKTHDR(m0); 5358 5359 len16 = mbuf_len16(m0); 5360 nsegs = mbuf_nsegs(m0); 5361 pktlen = m0->m_pkthdr.len; 5362 ctrl = sizeof(struct cpl_tx_pkt_core); 5363 if (needs_tso(m0)) 5364 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 5365 ndesc = tx_len16_to_desc(len16); 5366 5367 /* Firmware work request header */ 5368 eq = &txq->eq; 5369 wr = (void *)&eq->desc[eq->pidx]; 5370 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_VM_WR) | 5371 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl)); 5372 5373 ctrl = V_FW_WR_LEN16(len16); 5374 wr->equiq_to_len16 = htobe32(ctrl); 5375 wr->r3[0] = 0; 5376 wr->r3[1] = 0; 5377 5378 /* 5379 * Copy over ethmacdst, ethmacsrc, ethtype, and vlantci. 5380 * vlantci is ignored unless the ethtype is 0x8100, so it's 5381 * simpler to always copy it rather than making it 5382 * conditional. Also, it seems that we do not have to set 5383 * vlantci or fake the ethtype when doing VLAN tag insertion. 5384 */ 5385 m_copydata(m0, 0, VM_TX_L2HDR_LEN, wr->ethmacdst); 5386 5387 if (needs_tso(m0)) { 5388 cpl = write_lso_cpl(wr + 1, m0); 5389 txq->tso_wrs++; 5390 } else 5391 cpl = (void *)(wr + 1); 5392 5393 /* Checksum offload */ 5394 ctrl1 = csum_to_ctrl(sc, m0); 5395 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS)) 5396 txq->txcsum++; /* some hardware assistance provided */ 5397 5398 /* VLAN tag insertion */ 5399 if (needs_vlan_insertion(m0)) { 5400 ctrl1 |= F_TXPKT_VLAN_VLD | 5401 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 5402 txq->vlan_insertion++; 5403 } 5404 5405 /* CPL header */ 5406 cpl->ctrl0 = txq->cpl_ctrl0; 5407 cpl->pack = 0; 5408 cpl->len = htobe16(pktlen); 5409 cpl->ctrl1 = htobe64(ctrl1); 5410 5411 /* SGL */ 5412 dst = (void *)(cpl + 1); 5413 5414 /* 5415 * A packet using TSO will use up an entire descriptor for the 5416 * firmware work request header, LSO CPL, and TX_PKT_XT CPL. 5417 * If this descriptor is the last descriptor in the ring, wrap 5418 * around to the front of the ring explicitly for the start of 5419 * the sgl. 5420 */ 5421 if (dst == (void *)&eq->desc[eq->sidx]) { 5422 dst = (void *)&eq->desc[0]; 5423 write_gl_to_txd(txq, m0, &dst, 0); 5424 } else 5425 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx); 5426 txq->sgl_wrs++; 5427 txq->txpkt_wrs++; 5428 5429 txsd = &txq->sdesc[eq->pidx]; 5430 txsd->m = m0; 5431 txsd->desc_used = ndesc; 5432 5433 return (ndesc); 5434 } 5435 5436 /* 5437 * Write a raw WR to the hardware descriptors, update the software 5438 * descriptor, and advance the pidx. It is guaranteed that enough 5439 * descriptors are available. 5440 * 5441 * The return value is the # of hardware descriptors used. 5442 */ 5443 static u_int 5444 write_raw_wr(struct sge_txq *txq, void *wr, struct mbuf *m0, u_int available) 5445 { 5446 struct sge_eq *eq = &txq->eq; 5447 struct tx_sdesc *txsd; 5448 struct mbuf *m; 5449 caddr_t dst; 5450 int len16, ndesc; 5451 5452 len16 = mbuf_len16(m0); 5453 ndesc = tx_len16_to_desc(len16); 5454 MPASS(ndesc <= available); 5455 5456 dst = wr; 5457 for (m = m0; m != NULL; m = m->m_next) 5458 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len); 5459 5460 txq->raw_wrs++; 5461 5462 txsd = &txq->sdesc[eq->pidx]; 5463 txsd->m = m0; 5464 txsd->desc_used = ndesc; 5465 5466 return (ndesc); 5467 } 5468 5469 /* 5470 * Write a txpkt WR for this packet to the hardware descriptors, update the 5471 * software descriptor, and advance the pidx. It is guaranteed that enough 5472 * descriptors are available. 5473 * 5474 * The return value is the # of hardware descriptors used. 5475 */ 5476 static u_int 5477 write_txpkt_wr(struct adapter *sc, struct sge_txq *txq, struct mbuf *m0, 5478 u_int available) 5479 { 5480 struct sge_eq *eq; 5481 struct fw_eth_tx_pkt_wr *wr; 5482 struct tx_sdesc *txsd; 5483 struct cpl_tx_pkt_core *cpl; 5484 uint32_t ctrl; /* used in many unrelated places */ 5485 uint64_t ctrl1; 5486 int len16, ndesc, pktlen, nsegs; 5487 caddr_t dst; 5488 5489 TXQ_LOCK_ASSERT_OWNED(txq); 5490 M_ASSERTPKTHDR(m0); 5491 5492 len16 = mbuf_len16(m0); 5493 nsegs = mbuf_nsegs(m0); 5494 pktlen = m0->m_pkthdr.len; 5495 ctrl = sizeof(struct cpl_tx_pkt_core); 5496 if (needs_tso(m0)) { 5497 if (needs_vxlan_tso(m0)) 5498 ctrl += sizeof(struct cpl_tx_tnl_lso); 5499 else 5500 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 5501 } else if (!(mbuf_cflags(m0) & MC_NOMAP) && pktlen <= imm_payload(2) && 5502 available >= 2) { 5503 /* Immediate data. Recalculate len16 and set nsegs to 0. */ 5504 ctrl += pktlen; 5505 len16 = howmany(sizeof(struct fw_eth_tx_pkt_wr) + 5506 sizeof(struct cpl_tx_pkt_core) + pktlen, 16); 5507 nsegs = 0; 5508 } 5509 ndesc = tx_len16_to_desc(len16); 5510 MPASS(ndesc <= available); 5511 5512 /* Firmware work request header */ 5513 eq = &txq->eq; 5514 wr = (void *)&eq->desc[eq->pidx]; 5515 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_WR) | 5516 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl)); 5517 5518 ctrl = V_FW_WR_LEN16(len16); 5519 wr->equiq_to_len16 = htobe32(ctrl); 5520 wr->r3 = 0; 5521 5522 if (needs_tso(m0)) { 5523 if (needs_vxlan_tso(m0)) { 5524 cpl = write_tnl_lso_cpl(wr + 1, m0); 5525 txq->vxlan_tso_wrs++; 5526 } else { 5527 cpl = write_lso_cpl(wr + 1, m0); 5528 txq->tso_wrs++; 5529 } 5530 } else 5531 cpl = (void *)(wr + 1); 5532 5533 /* Checksum offload */ 5534 ctrl1 = csum_to_ctrl(sc, m0); 5535 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS)) { 5536 /* some hardware assistance provided */ 5537 if (needs_vxlan_csum(m0)) 5538 txq->vxlan_txcsum++; 5539 else 5540 txq->txcsum++; 5541 } 5542 5543 /* VLAN tag insertion */ 5544 if (needs_vlan_insertion(m0)) { 5545 ctrl1 |= F_TXPKT_VLAN_VLD | 5546 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 5547 txq->vlan_insertion++; 5548 } 5549 5550 /* CPL header */ 5551 cpl->ctrl0 = txq->cpl_ctrl0; 5552 cpl->pack = 0; 5553 cpl->len = htobe16(pktlen); 5554 cpl->ctrl1 = htobe64(ctrl1); 5555 5556 /* SGL */ 5557 dst = (void *)(cpl + 1); 5558 if (__predict_false((uintptr_t)dst == (uintptr_t)&eq->desc[eq->sidx])) 5559 dst = (caddr_t)&eq->desc[0]; 5560 if (nsegs > 0) { 5561 5562 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx); 5563 txq->sgl_wrs++; 5564 } else { 5565 struct mbuf *m; 5566 5567 for (m = m0; m != NULL; m = m->m_next) { 5568 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len); 5569 #ifdef INVARIANTS 5570 pktlen -= m->m_len; 5571 #endif 5572 } 5573 #ifdef INVARIANTS 5574 KASSERT(pktlen == 0, ("%s: %d bytes left.", __func__, pktlen)); 5575 #endif 5576 txq->imm_wrs++; 5577 } 5578 5579 txq->txpkt_wrs++; 5580 5581 txsd = &txq->sdesc[eq->pidx]; 5582 txsd->m = m0; 5583 txsd->desc_used = ndesc; 5584 5585 return (ndesc); 5586 } 5587 5588 static inline bool 5589 cmp_l2hdr(struct txpkts *txp, struct mbuf *m) 5590 { 5591 int len; 5592 5593 MPASS(txp->npkt > 0); 5594 MPASS(m->m_len >= VM_TX_L2HDR_LEN); 5595 5596 if (txp->ethtype == be16toh(ETHERTYPE_VLAN)) 5597 len = VM_TX_L2HDR_LEN; 5598 else 5599 len = sizeof(struct ether_header); 5600 5601 return (memcmp(m->m_data, &txp->ethmacdst[0], len) != 0); 5602 } 5603 5604 static inline void 5605 save_l2hdr(struct txpkts *txp, struct mbuf *m) 5606 { 5607 MPASS(m->m_len >= VM_TX_L2HDR_LEN); 5608 5609 memcpy(&txp->ethmacdst[0], mtod(m, const void *), VM_TX_L2HDR_LEN); 5610 } 5611 5612 static int 5613 add_to_txpkts_vf(struct adapter *sc, struct sge_txq *txq, struct mbuf *m, 5614 int avail, bool *send) 5615 { 5616 struct txpkts *txp = &txq->txp; 5617 5618 /* Cannot have TSO and coalesce at the same time. */ 5619 if (cannot_use_txpkts(m)) { 5620 cannot_coalesce: 5621 *send = txp->npkt > 0; 5622 return (EINVAL); 5623 } 5624 5625 /* VF allows coalescing of type 1 (1 GL) only */ 5626 if (mbuf_nsegs(m) > 1) 5627 goto cannot_coalesce; 5628 5629 *send = false; 5630 if (txp->npkt > 0) { 5631 MPASS(tx_len16_to_desc(txp->len16) <= avail); 5632 MPASS(txp->npkt < txp->max_npkt); 5633 MPASS(txp->wr_type == 1); /* VF supports type 1 only */ 5634 5635 if (tx_len16_to_desc(txp->len16 + txpkts1_len16()) > avail) { 5636 retry_after_send: 5637 *send = true; 5638 return (EAGAIN); 5639 } 5640 if (m->m_pkthdr.len + txp->plen > 65535) 5641 goto retry_after_send; 5642 if (cmp_l2hdr(txp, m)) 5643 goto retry_after_send; 5644 5645 txp->len16 += txpkts1_len16(); 5646 txp->plen += m->m_pkthdr.len; 5647 txp->mb[txp->npkt++] = m; 5648 if (txp->npkt == txp->max_npkt) 5649 *send = true; 5650 } else { 5651 txp->len16 = howmany(sizeof(struct fw_eth_tx_pkts_vm_wr), 16) + 5652 txpkts1_len16(); 5653 if (tx_len16_to_desc(txp->len16) > avail) 5654 goto cannot_coalesce; 5655 txp->npkt = 1; 5656 txp->wr_type = 1; 5657 txp->plen = m->m_pkthdr.len; 5658 txp->mb[0] = m; 5659 save_l2hdr(txp, m); 5660 } 5661 return (0); 5662 } 5663 5664 static int 5665 add_to_txpkts_pf(struct adapter *sc, struct sge_txq *txq, struct mbuf *m, 5666 int avail, bool *send) 5667 { 5668 struct txpkts *txp = &txq->txp; 5669 int nsegs; 5670 5671 MPASS(!(sc->flags & IS_VF)); 5672 5673 /* Cannot have TSO and coalesce at the same time. */ 5674 if (cannot_use_txpkts(m)) { 5675 cannot_coalesce: 5676 *send = txp->npkt > 0; 5677 return (EINVAL); 5678 } 5679 5680 *send = false; 5681 nsegs = mbuf_nsegs(m); 5682 if (txp->npkt == 0) { 5683 if (m->m_pkthdr.len > 65535) 5684 goto cannot_coalesce; 5685 if (nsegs > 1) { 5686 txp->wr_type = 0; 5687 txp->len16 = 5688 howmany(sizeof(struct fw_eth_tx_pkts_wr), 16) + 5689 txpkts0_len16(nsegs); 5690 } else { 5691 txp->wr_type = 1; 5692 txp->len16 = 5693 howmany(sizeof(struct fw_eth_tx_pkts_wr), 16) + 5694 txpkts1_len16(); 5695 } 5696 if (tx_len16_to_desc(txp->len16) > avail) 5697 goto cannot_coalesce; 5698 txp->npkt = 1; 5699 txp->plen = m->m_pkthdr.len; 5700 txp->mb[0] = m; 5701 } else { 5702 MPASS(tx_len16_to_desc(txp->len16) <= avail); 5703 MPASS(txp->npkt < txp->max_npkt); 5704 5705 if (m->m_pkthdr.len + txp->plen > 65535) { 5706 retry_after_send: 5707 *send = true; 5708 return (EAGAIN); 5709 } 5710 5711 MPASS(txp->wr_type == 0 || txp->wr_type == 1); 5712 if (txp->wr_type == 0) { 5713 if (tx_len16_to_desc(txp->len16 + 5714 txpkts0_len16(nsegs)) > min(avail, SGE_MAX_WR_NDESC)) 5715 goto retry_after_send; 5716 txp->len16 += txpkts0_len16(nsegs); 5717 } else { 5718 if (nsegs != 1) 5719 goto retry_after_send; 5720 if (tx_len16_to_desc(txp->len16 + txpkts1_len16()) > 5721 avail) 5722 goto retry_after_send; 5723 txp->len16 += txpkts1_len16(); 5724 } 5725 5726 txp->plen += m->m_pkthdr.len; 5727 txp->mb[txp->npkt++] = m; 5728 if (txp->npkt == txp->max_npkt) 5729 *send = true; 5730 } 5731 return (0); 5732 } 5733 5734 /* 5735 * Write a txpkts WR for the packets in txp to the hardware descriptors, update 5736 * the software descriptor, and advance the pidx. It is guaranteed that enough 5737 * descriptors are available. 5738 * 5739 * The return value is the # of hardware descriptors used. 5740 */ 5741 static u_int 5742 write_txpkts_wr(struct adapter *sc, struct sge_txq *txq) 5743 { 5744 const struct txpkts *txp = &txq->txp; 5745 struct sge_eq *eq = &txq->eq; 5746 struct fw_eth_tx_pkts_wr *wr; 5747 struct tx_sdesc *txsd; 5748 struct cpl_tx_pkt_core *cpl; 5749 uint64_t ctrl1; 5750 int ndesc, i, checkwrap; 5751 struct mbuf *m, *last; 5752 void *flitp; 5753 5754 TXQ_LOCK_ASSERT_OWNED(txq); 5755 MPASS(txp->npkt > 0); 5756 MPASS(txp->len16 <= howmany(SGE_MAX_WR_LEN, 16)); 5757 5758 wr = (void *)&eq->desc[eq->pidx]; 5759 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR)); 5760 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(txp->len16)); 5761 wr->plen = htobe16(txp->plen); 5762 wr->npkt = txp->npkt; 5763 wr->r3 = 0; 5764 wr->type = txp->wr_type; 5765 flitp = wr + 1; 5766 5767 /* 5768 * At this point we are 16B into a hardware descriptor. If checkwrap is 5769 * set then we know the WR is going to wrap around somewhere. We'll 5770 * check for that at appropriate points. 5771 */ 5772 ndesc = tx_len16_to_desc(txp->len16); 5773 last = NULL; 5774 checkwrap = eq->sidx - ndesc < eq->pidx; 5775 for (i = 0; i < txp->npkt; i++) { 5776 m = txp->mb[i]; 5777 if (txp->wr_type == 0) { 5778 struct ulp_txpkt *ulpmc; 5779 struct ulptx_idata *ulpsc; 5780 5781 /* ULP master command */ 5782 ulpmc = flitp; 5783 ulpmc->cmd_dest = htobe32(V_ULPTX_CMD(ULP_TX_PKT) | 5784 V_ULP_TXPKT_DEST(0) | V_ULP_TXPKT_FID(eq->iqid)); 5785 ulpmc->len = htobe32(txpkts0_len16(mbuf_nsegs(m))); 5786 5787 /* ULP subcommand */ 5788 ulpsc = (void *)(ulpmc + 1); 5789 ulpsc->cmd_more = htobe32(V_ULPTX_CMD(ULP_TX_SC_IMM) | 5790 F_ULP_TX_SC_MORE); 5791 ulpsc->len = htobe32(sizeof(struct cpl_tx_pkt_core)); 5792 5793 cpl = (void *)(ulpsc + 1); 5794 if (checkwrap && 5795 (uintptr_t)cpl == (uintptr_t)&eq->desc[eq->sidx]) 5796 cpl = (void *)&eq->desc[0]; 5797 } else { 5798 cpl = flitp; 5799 } 5800 5801 /* Checksum offload */ 5802 ctrl1 = csum_to_ctrl(sc, m); 5803 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS)) { 5804 /* some hardware assistance provided */ 5805 if (needs_vxlan_csum(m)) 5806 txq->vxlan_txcsum++; 5807 else 5808 txq->txcsum++; 5809 } 5810 5811 /* VLAN tag insertion */ 5812 if (needs_vlan_insertion(m)) { 5813 ctrl1 |= F_TXPKT_VLAN_VLD | 5814 V_TXPKT_VLAN(m->m_pkthdr.ether_vtag); 5815 txq->vlan_insertion++; 5816 } 5817 5818 /* CPL header */ 5819 cpl->ctrl0 = txq->cpl_ctrl0; 5820 cpl->pack = 0; 5821 cpl->len = htobe16(m->m_pkthdr.len); 5822 cpl->ctrl1 = htobe64(ctrl1); 5823 5824 flitp = cpl + 1; 5825 if (checkwrap && 5826 (uintptr_t)flitp == (uintptr_t)&eq->desc[eq->sidx]) 5827 flitp = (void *)&eq->desc[0]; 5828 5829 write_gl_to_txd(txq, m, (caddr_t *)(&flitp), checkwrap); 5830 5831 if (last != NULL) 5832 last->m_nextpkt = m; 5833 last = m; 5834 } 5835 5836 txq->sgl_wrs++; 5837 if (txp->wr_type == 0) { 5838 txq->txpkts0_pkts += txp->npkt; 5839 txq->txpkts0_wrs++; 5840 } else { 5841 txq->txpkts1_pkts += txp->npkt; 5842 txq->txpkts1_wrs++; 5843 } 5844 5845 txsd = &txq->sdesc[eq->pidx]; 5846 txsd->m = txp->mb[0]; 5847 txsd->desc_used = ndesc; 5848 5849 return (ndesc); 5850 } 5851 5852 static u_int 5853 write_txpkts_vm_wr(struct adapter *sc, struct sge_txq *txq) 5854 { 5855 const struct txpkts *txp = &txq->txp; 5856 struct sge_eq *eq = &txq->eq; 5857 struct fw_eth_tx_pkts_vm_wr *wr; 5858 struct tx_sdesc *txsd; 5859 struct cpl_tx_pkt_core *cpl; 5860 uint64_t ctrl1; 5861 int ndesc, i; 5862 struct mbuf *m, *last; 5863 void *flitp; 5864 5865 TXQ_LOCK_ASSERT_OWNED(txq); 5866 MPASS(txp->npkt > 0); 5867 MPASS(txp->wr_type == 1); /* VF supports type 1 only */ 5868 MPASS(txp->mb[0] != NULL); 5869 MPASS(txp->len16 <= howmany(SGE_MAX_WR_LEN, 16)); 5870 5871 wr = (void *)&eq->desc[eq->pidx]; 5872 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_VM_WR)); 5873 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(txp->len16)); 5874 wr->r3 = 0; 5875 wr->plen = htobe16(txp->plen); 5876 wr->npkt = txp->npkt; 5877 wr->r4 = 0; 5878 memcpy(&wr->ethmacdst[0], &txp->ethmacdst[0], 16); 5879 flitp = wr + 1; 5880 5881 /* 5882 * At this point we are 32B into a hardware descriptor. Each mbuf in 5883 * the WR will take 32B so we check for the end of the descriptor ring 5884 * before writing odd mbufs (mb[1], 3, 5, ..) 5885 */ 5886 ndesc = tx_len16_to_desc(txp->len16); 5887 last = NULL; 5888 for (i = 0; i < txp->npkt; i++) { 5889 m = txp->mb[i]; 5890 if (i & 1 && (uintptr_t)flitp == (uintptr_t)&eq->desc[eq->sidx]) 5891 flitp = &eq->desc[0]; 5892 cpl = flitp; 5893 5894 /* Checksum offload */ 5895 ctrl1 = csum_to_ctrl(sc, m); 5896 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS)) 5897 txq->txcsum++; /* some hardware assistance provided */ 5898 5899 /* VLAN tag insertion */ 5900 if (needs_vlan_insertion(m)) { 5901 ctrl1 |= F_TXPKT_VLAN_VLD | 5902 V_TXPKT_VLAN(m->m_pkthdr.ether_vtag); 5903 txq->vlan_insertion++; 5904 } 5905 5906 /* CPL header */ 5907 cpl->ctrl0 = txq->cpl_ctrl0; 5908 cpl->pack = 0; 5909 cpl->len = htobe16(m->m_pkthdr.len); 5910 cpl->ctrl1 = htobe64(ctrl1); 5911 5912 flitp = cpl + 1; 5913 MPASS(mbuf_nsegs(m) == 1); 5914 write_gl_to_txd(txq, m, (caddr_t *)(&flitp), 0); 5915 5916 if (last != NULL) 5917 last->m_nextpkt = m; 5918 last = m; 5919 } 5920 5921 txq->sgl_wrs++; 5922 txq->txpkts1_pkts += txp->npkt; 5923 txq->txpkts1_wrs++; 5924 5925 txsd = &txq->sdesc[eq->pidx]; 5926 txsd->m = txp->mb[0]; 5927 txsd->desc_used = ndesc; 5928 5929 return (ndesc); 5930 } 5931 5932 /* 5933 * If the SGL ends on an address that is not 16 byte aligned, this function will 5934 * add a 0 filled flit at the end. 5935 */ 5936 static void 5937 write_gl_to_txd(struct sge_txq *txq, struct mbuf *m, caddr_t *to, int checkwrap) 5938 { 5939 struct sge_eq *eq = &txq->eq; 5940 struct sglist *gl = txq->gl; 5941 struct sglist_seg *seg; 5942 __be64 *flitp, *wrap; 5943 struct ulptx_sgl *usgl; 5944 int i, nflits, nsegs; 5945 5946 KASSERT(((uintptr_t)(*to) & 0xf) == 0, 5947 ("%s: SGL must start at a 16 byte boundary: %p", __func__, *to)); 5948 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]); 5949 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]); 5950 5951 get_pkt_gl(m, gl); 5952 nsegs = gl->sg_nseg; 5953 MPASS(nsegs > 0); 5954 5955 nflits = (3 * (nsegs - 1)) / 2 + ((nsegs - 1) & 1) + 2; 5956 flitp = (__be64 *)(*to); 5957 wrap = (__be64 *)(&eq->desc[eq->sidx]); 5958 seg = &gl->sg_segs[0]; 5959 usgl = (void *)flitp; 5960 5961 /* 5962 * We start at a 16 byte boundary somewhere inside the tx descriptor 5963 * ring, so we're at least 16 bytes away from the status page. There is 5964 * no chance of a wrap around in the middle of usgl (which is 16 bytes). 5965 */ 5966 5967 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 5968 V_ULPTX_NSGE(nsegs)); 5969 usgl->len0 = htobe32(seg->ss_len); 5970 usgl->addr0 = htobe64(seg->ss_paddr); 5971 seg++; 5972 5973 if (checkwrap == 0 || (uintptr_t)(flitp + nflits) <= (uintptr_t)wrap) { 5974 5975 /* Won't wrap around at all */ 5976 5977 for (i = 0; i < nsegs - 1; i++, seg++) { 5978 usgl->sge[i / 2].len[i & 1] = htobe32(seg->ss_len); 5979 usgl->sge[i / 2].addr[i & 1] = htobe64(seg->ss_paddr); 5980 } 5981 if (i & 1) 5982 usgl->sge[i / 2].len[1] = htobe32(0); 5983 flitp += nflits; 5984 } else { 5985 5986 /* Will wrap somewhere in the rest of the SGL */ 5987 5988 /* 2 flits already written, write the rest flit by flit */ 5989 flitp = (void *)(usgl + 1); 5990 for (i = 0; i < nflits - 2; i++) { 5991 if (flitp == wrap) 5992 flitp = (void *)eq->desc; 5993 *flitp++ = get_flit(seg, nsegs - 1, i); 5994 } 5995 } 5996 5997 if (nflits & 1) { 5998 MPASS(((uintptr_t)flitp) & 0xf); 5999 *flitp++ = 0; 6000 } 6001 6002 MPASS((((uintptr_t)flitp) & 0xf) == 0); 6003 if (__predict_false(flitp == wrap)) 6004 *to = (void *)eq->desc; 6005 else 6006 *to = (void *)flitp; 6007 } 6008 6009 static inline void 6010 copy_to_txd(struct sge_eq *eq, caddr_t from, caddr_t *to, int len) 6011 { 6012 6013 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]); 6014 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]); 6015 6016 if (__predict_true((uintptr_t)(*to) + len <= 6017 (uintptr_t)&eq->desc[eq->sidx])) { 6018 bcopy(from, *to, len); 6019 (*to) += len; 6020 } else { 6021 int portion = (uintptr_t)&eq->desc[eq->sidx] - (uintptr_t)(*to); 6022 6023 bcopy(from, *to, portion); 6024 from += portion; 6025 portion = len - portion; /* remaining */ 6026 bcopy(from, (void *)eq->desc, portion); 6027 (*to) = (caddr_t)eq->desc + portion; 6028 } 6029 } 6030 6031 static inline void 6032 ring_eq_db(struct adapter *sc, struct sge_eq *eq, u_int n) 6033 { 6034 u_int db; 6035 6036 MPASS(n > 0); 6037 6038 db = eq->doorbells; 6039 if (n > 1) 6040 clrbit(&db, DOORBELL_WCWR); 6041 wmb(); 6042 6043 switch (ffs(db) - 1) { 6044 case DOORBELL_UDB: 6045 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n)); 6046 break; 6047 6048 case DOORBELL_WCWR: { 6049 volatile uint64_t *dst, *src; 6050 int i; 6051 6052 /* 6053 * Queues whose 128B doorbell segment fits in the page do not 6054 * use relative qid (udb_qid is always 0). Only queues with 6055 * doorbell segments can do WCWR. 6056 */ 6057 KASSERT(eq->udb_qid == 0 && n == 1, 6058 ("%s: inappropriate doorbell (0x%x, %d, %d) for eq %p", 6059 __func__, eq->doorbells, n, eq->dbidx, eq)); 6060 6061 dst = (volatile void *)((uintptr_t)eq->udb + UDBS_WR_OFFSET - 6062 UDBS_DB_OFFSET); 6063 i = eq->dbidx; 6064 src = (void *)&eq->desc[i]; 6065 while (src != (void *)&eq->desc[i + 1]) 6066 *dst++ = *src++; 6067 wmb(); 6068 break; 6069 } 6070 6071 case DOORBELL_UDBWC: 6072 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n)); 6073 wmb(); 6074 break; 6075 6076 case DOORBELL_KDB: 6077 t4_write_reg(sc, sc->sge_kdoorbell_reg, 6078 V_QID(eq->cntxt_id) | V_PIDX(n)); 6079 break; 6080 } 6081 6082 IDXINCR(eq->dbidx, n, eq->sidx); 6083 } 6084 6085 static inline u_int 6086 reclaimable_tx_desc(struct sge_eq *eq) 6087 { 6088 uint16_t hw_cidx; 6089 6090 hw_cidx = read_hw_cidx(eq); 6091 return (IDXDIFF(hw_cidx, eq->cidx, eq->sidx)); 6092 } 6093 6094 static inline u_int 6095 total_available_tx_desc(struct sge_eq *eq) 6096 { 6097 uint16_t hw_cidx, pidx; 6098 6099 hw_cidx = read_hw_cidx(eq); 6100 pidx = eq->pidx; 6101 6102 if (pidx == hw_cidx) 6103 return (eq->sidx - 1); 6104 else 6105 return (IDXDIFF(hw_cidx, pidx, eq->sidx) - 1); 6106 } 6107 6108 static inline uint16_t 6109 read_hw_cidx(struct sge_eq *eq) 6110 { 6111 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx]; 6112 uint16_t cidx = spg->cidx; /* stable snapshot */ 6113 6114 return (be16toh(cidx)); 6115 } 6116 6117 /* 6118 * Reclaim 'n' descriptors approximately. 6119 */ 6120 static u_int 6121 reclaim_tx_descs(struct sge_txq *txq, u_int n) 6122 { 6123 struct tx_sdesc *txsd; 6124 struct sge_eq *eq = &txq->eq; 6125 u_int can_reclaim, reclaimed; 6126 6127 TXQ_LOCK_ASSERT_OWNED(txq); 6128 MPASS(n > 0); 6129 6130 reclaimed = 0; 6131 can_reclaim = reclaimable_tx_desc(eq); 6132 while (can_reclaim && reclaimed < n) { 6133 int ndesc; 6134 struct mbuf *m, *nextpkt; 6135 6136 txsd = &txq->sdesc[eq->cidx]; 6137 ndesc = txsd->desc_used; 6138 6139 /* Firmware doesn't return "partial" credits. */ 6140 KASSERT(can_reclaim >= ndesc, 6141 ("%s: unexpected number of credits: %d, %d", 6142 __func__, can_reclaim, ndesc)); 6143 KASSERT(ndesc != 0, 6144 ("%s: descriptor with no credits: cidx %d", 6145 __func__, eq->cidx)); 6146 6147 for (m = txsd->m; m != NULL; m = nextpkt) { 6148 nextpkt = m->m_nextpkt; 6149 m->m_nextpkt = NULL; 6150 m_freem(m); 6151 } 6152 reclaimed += ndesc; 6153 can_reclaim -= ndesc; 6154 IDXINCR(eq->cidx, ndesc, eq->sidx); 6155 } 6156 6157 return (reclaimed); 6158 } 6159 6160 static void 6161 tx_reclaim(void *arg, int n) 6162 { 6163 struct sge_txq *txq = arg; 6164 struct sge_eq *eq = &txq->eq; 6165 6166 do { 6167 if (TXQ_TRYLOCK(txq) == 0) 6168 break; 6169 n = reclaim_tx_descs(txq, 32); 6170 if (eq->cidx == eq->pidx) 6171 eq->equeqidx = eq->pidx; 6172 TXQ_UNLOCK(txq); 6173 } while (n > 0); 6174 } 6175 6176 static __be64 6177 get_flit(struct sglist_seg *segs, int nsegs, int idx) 6178 { 6179 int i = (idx / 3) * 2; 6180 6181 switch (idx % 3) { 6182 case 0: { 6183 uint64_t rc; 6184 6185 rc = (uint64_t)segs[i].ss_len << 32; 6186 if (i + 1 < nsegs) 6187 rc |= (uint64_t)(segs[i + 1].ss_len); 6188 6189 return (htobe64(rc)); 6190 } 6191 case 1: 6192 return (htobe64(segs[i].ss_paddr)); 6193 case 2: 6194 return (htobe64(segs[i + 1].ss_paddr)); 6195 } 6196 6197 return (0); 6198 } 6199 6200 static int 6201 find_refill_source(struct adapter *sc, int maxp, bool packing) 6202 { 6203 int i, zidx = -1; 6204 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[0]; 6205 6206 if (packing) { 6207 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) { 6208 if (rxb->hwidx2 == -1) 6209 continue; 6210 if (rxb->size1 < PAGE_SIZE && 6211 rxb->size1 < largest_rx_cluster) 6212 continue; 6213 if (rxb->size1 > largest_rx_cluster) 6214 break; 6215 MPASS(rxb->size1 - rxb->size2 >= CL_METADATA_SIZE); 6216 if (rxb->size2 >= maxp) 6217 return (i); 6218 zidx = i; 6219 } 6220 } else { 6221 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) { 6222 if (rxb->hwidx1 == -1) 6223 continue; 6224 if (rxb->size1 > largest_rx_cluster) 6225 break; 6226 if (rxb->size1 >= maxp) 6227 return (i); 6228 zidx = i; 6229 } 6230 } 6231 6232 return (zidx); 6233 } 6234 6235 static void 6236 add_fl_to_sfl(struct adapter *sc, struct sge_fl *fl) 6237 { 6238 mtx_lock(&sc->sfl_lock); 6239 FL_LOCK(fl); 6240 if ((fl->flags & FL_DOOMED) == 0) { 6241 fl->flags |= FL_STARVING; 6242 TAILQ_INSERT_TAIL(&sc->sfl, fl, link); 6243 callout_reset(&sc->sfl_callout, hz / 5, refill_sfl, sc); 6244 } 6245 FL_UNLOCK(fl); 6246 mtx_unlock(&sc->sfl_lock); 6247 } 6248 6249 static void 6250 handle_wrq_egr_update(struct adapter *sc, struct sge_eq *eq) 6251 { 6252 struct sge_wrq *wrq = (void *)eq; 6253 6254 atomic_readandclear_int(&eq->equiq); 6255 taskqueue_enqueue(sc->tq[eq->tx_chan], &wrq->wrq_tx_task); 6256 } 6257 6258 static void 6259 handle_eth_egr_update(struct adapter *sc, struct sge_eq *eq) 6260 { 6261 struct sge_txq *txq = (void *)eq; 6262 6263 MPASS(eq->type == EQ_ETH); 6264 6265 atomic_readandclear_int(&eq->equiq); 6266 if (mp_ring_is_idle(txq->r)) 6267 taskqueue_enqueue(sc->tq[eq->tx_chan], &txq->tx_reclaim_task); 6268 else 6269 mp_ring_check_drainage(txq->r, 64); 6270 } 6271 6272 static int 6273 handle_sge_egr_update(struct sge_iq *iq, const struct rss_header *rss, 6274 struct mbuf *m) 6275 { 6276 const struct cpl_sge_egr_update *cpl = (const void *)(rss + 1); 6277 unsigned int qid = G_EGR_QID(ntohl(cpl->opcode_qid)); 6278 struct adapter *sc = iq->adapter; 6279 struct sge *s = &sc->sge; 6280 struct sge_eq *eq; 6281 static void (*h[])(struct adapter *, struct sge_eq *) = {NULL, 6282 &handle_wrq_egr_update, &handle_eth_egr_update, 6283 &handle_wrq_egr_update}; 6284 6285 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 6286 rss->opcode)); 6287 6288 eq = s->eqmap[qid - s->eq_start - s->eq_base]; 6289 (*h[eq->type])(sc, eq); 6290 6291 return (0); 6292 } 6293 6294 /* handle_fw_msg works for both fw4_msg and fw6_msg because this is valid */ 6295 CTASSERT(offsetof(struct cpl_fw4_msg, data) == \ 6296 offsetof(struct cpl_fw6_msg, data)); 6297 6298 static int 6299 handle_fw_msg(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 6300 { 6301 struct adapter *sc = iq->adapter; 6302 const struct cpl_fw6_msg *cpl = (const void *)(rss + 1); 6303 6304 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 6305 rss->opcode)); 6306 6307 if (cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL) { 6308 const struct rss_header *rss2; 6309 6310 rss2 = (const struct rss_header *)&cpl->data[0]; 6311 return (t4_cpl_handler[rss2->opcode](iq, rss2, m)); 6312 } 6313 6314 return (t4_fw_msg_handler[cpl->type](sc, &cpl->data[0])); 6315 } 6316 6317 /** 6318 * t4_handle_wrerr_rpl - process a FW work request error message 6319 * @adap: the adapter 6320 * @rpl: start of the FW message 6321 */ 6322 static int 6323 t4_handle_wrerr_rpl(struct adapter *adap, const __be64 *rpl) 6324 { 6325 u8 opcode = *(const u8 *)rpl; 6326 const struct fw_error_cmd *e = (const void *)rpl; 6327 unsigned int i; 6328 6329 if (opcode != FW_ERROR_CMD) { 6330 log(LOG_ERR, 6331 "%s: Received WRERR_RPL message with opcode %#x\n", 6332 device_get_nameunit(adap->dev), opcode); 6333 return (EINVAL); 6334 } 6335 log(LOG_ERR, "%s: FW_ERROR (%s) ", device_get_nameunit(adap->dev), 6336 G_FW_ERROR_CMD_FATAL(be32toh(e->op_to_type)) ? "fatal" : 6337 "non-fatal"); 6338 switch (G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type))) { 6339 case FW_ERROR_TYPE_EXCEPTION: 6340 log(LOG_ERR, "exception info:\n"); 6341 for (i = 0; i < nitems(e->u.exception.info); i++) 6342 log(LOG_ERR, "%s%08x", i == 0 ? "\t" : " ", 6343 be32toh(e->u.exception.info[i])); 6344 log(LOG_ERR, "\n"); 6345 break; 6346 case FW_ERROR_TYPE_HWMODULE: 6347 log(LOG_ERR, "HW module regaddr %08x regval %08x\n", 6348 be32toh(e->u.hwmodule.regaddr), 6349 be32toh(e->u.hwmodule.regval)); 6350 break; 6351 case FW_ERROR_TYPE_WR: 6352 log(LOG_ERR, "WR cidx %d PF %d VF %d eqid %d hdr:\n", 6353 be16toh(e->u.wr.cidx), 6354 G_FW_ERROR_CMD_PFN(be16toh(e->u.wr.pfn_vfn)), 6355 G_FW_ERROR_CMD_VFN(be16toh(e->u.wr.pfn_vfn)), 6356 be32toh(e->u.wr.eqid)); 6357 for (i = 0; i < nitems(e->u.wr.wrhdr); i++) 6358 log(LOG_ERR, "%s%02x", i == 0 ? "\t" : " ", 6359 e->u.wr.wrhdr[i]); 6360 log(LOG_ERR, "\n"); 6361 break; 6362 case FW_ERROR_TYPE_ACL: 6363 log(LOG_ERR, "ACL cidx %d PF %d VF %d eqid %d %s", 6364 be16toh(e->u.acl.cidx), 6365 G_FW_ERROR_CMD_PFN(be16toh(e->u.acl.pfn_vfn)), 6366 G_FW_ERROR_CMD_VFN(be16toh(e->u.acl.pfn_vfn)), 6367 be32toh(e->u.acl.eqid), 6368 G_FW_ERROR_CMD_MV(be16toh(e->u.acl.mv_pkd)) ? "vlanid" : 6369 "MAC"); 6370 for (i = 0; i < nitems(e->u.acl.val); i++) 6371 log(LOG_ERR, " %02x", e->u.acl.val[i]); 6372 log(LOG_ERR, "\n"); 6373 break; 6374 default: 6375 log(LOG_ERR, "type %#x\n", 6376 G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type))); 6377 return (EINVAL); 6378 } 6379 return (0); 6380 } 6381 6382 static inline bool 6383 bufidx_used(struct adapter *sc, int idx) 6384 { 6385 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[0]; 6386 int i; 6387 6388 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) { 6389 if (rxb->size1 > largest_rx_cluster) 6390 continue; 6391 if (rxb->hwidx1 == idx || rxb->hwidx2 == idx) 6392 return (true); 6393 } 6394 6395 return (false); 6396 } 6397 6398 static int 6399 sysctl_bufsizes(SYSCTL_HANDLER_ARGS) 6400 { 6401 struct adapter *sc = arg1; 6402 struct sge_params *sp = &sc->params.sge; 6403 int i, rc; 6404 struct sbuf sb; 6405 char c; 6406 6407 sbuf_new(&sb, NULL, 128, SBUF_AUTOEXTEND); 6408 for (i = 0; i < SGE_FLBUF_SIZES; i++) { 6409 if (bufidx_used(sc, i)) 6410 c = '*'; 6411 else 6412 c = '\0'; 6413 6414 sbuf_printf(&sb, "%u%c ", sp->sge_fl_buffer_size[i], c); 6415 } 6416 sbuf_trim(&sb); 6417 sbuf_finish(&sb); 6418 rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req); 6419 sbuf_delete(&sb); 6420 return (rc); 6421 } 6422 6423 #ifdef RATELIMIT 6424 /* 6425 * len16 for a txpkt WR with a GL. Includes the firmware work request header. 6426 */ 6427 static inline u_int 6428 txpkt_eo_len16(u_int nsegs, u_int immhdrs, u_int tso) 6429 { 6430 u_int n; 6431 6432 MPASS(immhdrs > 0); 6433 6434 n = roundup2(sizeof(struct fw_eth_tx_eo_wr) + 6435 sizeof(struct cpl_tx_pkt_core) + immhdrs, 16); 6436 if (__predict_false(nsegs == 0)) 6437 goto done; 6438 6439 nsegs--; /* first segment is part of ulptx_sgl */ 6440 n += sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 6441 if (tso) 6442 n += sizeof(struct cpl_tx_pkt_lso_core); 6443 6444 done: 6445 return (howmany(n, 16)); 6446 } 6447 6448 #define ETID_FLOWC_NPARAMS 6 6449 #define ETID_FLOWC_LEN (roundup2((sizeof(struct fw_flowc_wr) + \ 6450 ETID_FLOWC_NPARAMS * sizeof(struct fw_flowc_mnemval)), 16)) 6451 #define ETID_FLOWC_LEN16 (howmany(ETID_FLOWC_LEN, 16)) 6452 6453 static int 6454 send_etid_flowc_wr(struct cxgbe_rate_tag *cst, struct port_info *pi, 6455 struct vi_info *vi) 6456 { 6457 struct wrq_cookie cookie; 6458 u_int pfvf = pi->adapter->pf << S_FW_VIID_PFN; 6459 struct fw_flowc_wr *flowc; 6460 6461 mtx_assert(&cst->lock, MA_OWNED); 6462 MPASS((cst->flags & (EO_FLOWC_PENDING | EO_FLOWC_RPL_PENDING)) == 6463 EO_FLOWC_PENDING); 6464 6465 flowc = start_wrq_wr(&cst->eo_txq->wrq, ETID_FLOWC_LEN16, &cookie); 6466 if (__predict_false(flowc == NULL)) 6467 return (ENOMEM); 6468 6469 bzero(flowc, ETID_FLOWC_LEN); 6470 flowc->op_to_nparams = htobe32(V_FW_WR_OP(FW_FLOWC_WR) | 6471 V_FW_FLOWC_WR_NPARAMS(ETID_FLOWC_NPARAMS) | V_FW_WR_COMPL(0)); 6472 flowc->flowid_len16 = htonl(V_FW_WR_LEN16(ETID_FLOWC_LEN16) | 6473 V_FW_WR_FLOWID(cst->etid)); 6474 flowc->mnemval[0].mnemonic = FW_FLOWC_MNEM_PFNVFN; 6475 flowc->mnemval[0].val = htobe32(pfvf); 6476 flowc->mnemval[1].mnemonic = FW_FLOWC_MNEM_CH; 6477 flowc->mnemval[1].val = htobe32(pi->tx_chan); 6478 flowc->mnemval[2].mnemonic = FW_FLOWC_MNEM_PORT; 6479 flowc->mnemval[2].val = htobe32(pi->tx_chan); 6480 flowc->mnemval[3].mnemonic = FW_FLOWC_MNEM_IQID; 6481 flowc->mnemval[3].val = htobe32(cst->iqid); 6482 flowc->mnemval[4].mnemonic = FW_FLOWC_MNEM_EOSTATE; 6483 flowc->mnemval[4].val = htobe32(FW_FLOWC_MNEM_EOSTATE_ESTABLISHED); 6484 flowc->mnemval[5].mnemonic = FW_FLOWC_MNEM_SCHEDCLASS; 6485 flowc->mnemval[5].val = htobe32(cst->schedcl); 6486 6487 commit_wrq_wr(&cst->eo_txq->wrq, flowc, &cookie); 6488 6489 cst->flags &= ~EO_FLOWC_PENDING; 6490 cst->flags |= EO_FLOWC_RPL_PENDING; 6491 MPASS(cst->tx_credits >= ETID_FLOWC_LEN16); /* flowc is first WR. */ 6492 cst->tx_credits -= ETID_FLOWC_LEN16; 6493 6494 return (0); 6495 } 6496 6497 #define ETID_FLUSH_LEN16 (howmany(sizeof (struct fw_flowc_wr), 16)) 6498 6499 void 6500 send_etid_flush_wr(struct cxgbe_rate_tag *cst) 6501 { 6502 struct fw_flowc_wr *flowc; 6503 struct wrq_cookie cookie; 6504 6505 mtx_assert(&cst->lock, MA_OWNED); 6506 6507 flowc = start_wrq_wr(&cst->eo_txq->wrq, ETID_FLUSH_LEN16, &cookie); 6508 if (__predict_false(flowc == NULL)) 6509 CXGBE_UNIMPLEMENTED(__func__); 6510 6511 bzero(flowc, ETID_FLUSH_LEN16 * 16); 6512 flowc->op_to_nparams = htobe32(V_FW_WR_OP(FW_FLOWC_WR) | 6513 V_FW_FLOWC_WR_NPARAMS(0) | F_FW_WR_COMPL); 6514 flowc->flowid_len16 = htobe32(V_FW_WR_LEN16(ETID_FLUSH_LEN16) | 6515 V_FW_WR_FLOWID(cst->etid)); 6516 6517 commit_wrq_wr(&cst->eo_txq->wrq, flowc, &cookie); 6518 6519 cst->flags |= EO_FLUSH_RPL_PENDING; 6520 MPASS(cst->tx_credits >= ETID_FLUSH_LEN16); 6521 cst->tx_credits -= ETID_FLUSH_LEN16; 6522 cst->ncompl++; 6523 } 6524 6525 static void 6526 write_ethofld_wr(struct cxgbe_rate_tag *cst, struct fw_eth_tx_eo_wr *wr, 6527 struct mbuf *m0, int compl) 6528 { 6529 struct cpl_tx_pkt_core *cpl; 6530 uint64_t ctrl1; 6531 uint32_t ctrl; /* used in many unrelated places */ 6532 int len16, pktlen, nsegs, immhdrs; 6533 caddr_t dst; 6534 uintptr_t p; 6535 struct ulptx_sgl *usgl; 6536 struct sglist sg; 6537 struct sglist_seg segs[38]; /* XXX: find real limit. XXX: get off the stack */ 6538 6539 mtx_assert(&cst->lock, MA_OWNED); 6540 M_ASSERTPKTHDR(m0); 6541 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 6542 m0->m_pkthdr.l4hlen > 0, 6543 ("%s: ethofld mbuf %p is missing header lengths", __func__, m0)); 6544 6545 len16 = mbuf_eo_len16(m0); 6546 nsegs = mbuf_eo_nsegs(m0); 6547 pktlen = m0->m_pkthdr.len; 6548 ctrl = sizeof(struct cpl_tx_pkt_core); 6549 if (needs_tso(m0)) 6550 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 6551 immhdrs = m0->m_pkthdr.l2hlen + m0->m_pkthdr.l3hlen + m0->m_pkthdr.l4hlen; 6552 ctrl += immhdrs; 6553 6554 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_EO_WR) | 6555 V_FW_ETH_TX_EO_WR_IMMDLEN(ctrl) | V_FW_WR_COMPL(!!compl)); 6556 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(len16) | 6557 V_FW_WR_FLOWID(cst->etid)); 6558 wr->r3 = 0; 6559 if (needs_outer_udp_csum(m0)) { 6560 wr->u.udpseg.type = FW_ETH_TX_EO_TYPE_UDPSEG; 6561 wr->u.udpseg.ethlen = m0->m_pkthdr.l2hlen; 6562 wr->u.udpseg.iplen = htobe16(m0->m_pkthdr.l3hlen); 6563 wr->u.udpseg.udplen = m0->m_pkthdr.l4hlen; 6564 wr->u.udpseg.rtplen = 0; 6565 wr->u.udpseg.r4 = 0; 6566 wr->u.udpseg.mss = htobe16(pktlen - immhdrs); 6567 wr->u.udpseg.schedpktsize = wr->u.udpseg.mss; 6568 wr->u.udpseg.plen = htobe32(pktlen - immhdrs); 6569 cpl = (void *)(wr + 1); 6570 } else { 6571 MPASS(needs_outer_tcp_csum(m0)); 6572 wr->u.tcpseg.type = FW_ETH_TX_EO_TYPE_TCPSEG; 6573 wr->u.tcpseg.ethlen = m0->m_pkthdr.l2hlen; 6574 wr->u.tcpseg.iplen = htobe16(m0->m_pkthdr.l3hlen); 6575 wr->u.tcpseg.tcplen = m0->m_pkthdr.l4hlen; 6576 wr->u.tcpseg.tsclk_tsoff = mbuf_eo_tsclk_tsoff(m0); 6577 wr->u.tcpseg.r4 = 0; 6578 wr->u.tcpseg.r5 = 0; 6579 wr->u.tcpseg.plen = htobe32(pktlen - immhdrs); 6580 6581 if (needs_tso(m0)) { 6582 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1); 6583 6584 wr->u.tcpseg.mss = htobe16(m0->m_pkthdr.tso_segsz); 6585 6586 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | 6587 F_LSO_FIRST_SLICE | F_LSO_LAST_SLICE | 6588 V_LSO_ETHHDR_LEN((m0->m_pkthdr.l2hlen - 6589 ETHER_HDR_LEN) >> 2) | 6590 V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) | 6591 V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2); 6592 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 6593 ctrl |= F_LSO_IPV6; 6594 lso->lso_ctrl = htobe32(ctrl); 6595 lso->ipid_ofst = htobe16(0); 6596 lso->mss = htobe16(m0->m_pkthdr.tso_segsz); 6597 lso->seqno_offset = htobe32(0); 6598 lso->len = htobe32(pktlen); 6599 6600 cpl = (void *)(lso + 1); 6601 } else { 6602 wr->u.tcpseg.mss = htobe16(0xffff); 6603 cpl = (void *)(wr + 1); 6604 } 6605 } 6606 6607 /* Checksum offload must be requested for ethofld. */ 6608 MPASS(needs_outer_l4_csum(m0)); 6609 ctrl1 = csum_to_ctrl(cst->adapter, m0); 6610 6611 /* VLAN tag insertion */ 6612 if (needs_vlan_insertion(m0)) { 6613 ctrl1 |= F_TXPKT_VLAN_VLD | 6614 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 6615 } 6616 6617 /* CPL header */ 6618 cpl->ctrl0 = cst->ctrl0; 6619 cpl->pack = 0; 6620 cpl->len = htobe16(pktlen); 6621 cpl->ctrl1 = htobe64(ctrl1); 6622 6623 /* Copy Ethernet, IP & TCP/UDP hdrs as immediate data */ 6624 p = (uintptr_t)(cpl + 1); 6625 m_copydata(m0, 0, immhdrs, (void *)p); 6626 6627 /* SGL */ 6628 dst = (void *)(cpl + 1); 6629 if (nsegs > 0) { 6630 int i, pad; 6631 6632 /* zero-pad upto next 16Byte boundary, if not 16Byte aligned */ 6633 p += immhdrs; 6634 pad = 16 - (immhdrs & 0xf); 6635 bzero((void *)p, pad); 6636 6637 usgl = (void *)(p + pad); 6638 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 6639 V_ULPTX_NSGE(nsegs)); 6640 6641 sglist_init(&sg, nitems(segs), segs); 6642 for (; m0 != NULL; m0 = m0->m_next) { 6643 if (__predict_false(m0->m_len == 0)) 6644 continue; 6645 if (immhdrs >= m0->m_len) { 6646 immhdrs -= m0->m_len; 6647 continue; 6648 } 6649 if (m0->m_flags & M_EXTPG) 6650 sglist_append_mbuf_epg(&sg, m0, 6651 mtod(m0, vm_offset_t), m0->m_len); 6652 else 6653 sglist_append(&sg, mtod(m0, char *) + immhdrs, 6654 m0->m_len - immhdrs); 6655 immhdrs = 0; 6656 } 6657 MPASS(sg.sg_nseg == nsegs); 6658 6659 /* 6660 * Zero pad last 8B in case the WR doesn't end on a 16B 6661 * boundary. 6662 */ 6663 *(uint64_t *)((char *)wr + len16 * 16 - 8) = 0; 6664 6665 usgl->len0 = htobe32(segs[0].ss_len); 6666 usgl->addr0 = htobe64(segs[0].ss_paddr); 6667 for (i = 0; i < nsegs - 1; i++) { 6668 usgl->sge[i / 2].len[i & 1] = htobe32(segs[i + 1].ss_len); 6669 usgl->sge[i / 2].addr[i & 1] = htobe64(segs[i + 1].ss_paddr); 6670 } 6671 if (i & 1) 6672 usgl->sge[i / 2].len[1] = htobe32(0); 6673 } 6674 6675 } 6676 6677 static void 6678 ethofld_tx(struct cxgbe_rate_tag *cst) 6679 { 6680 struct mbuf *m; 6681 struct wrq_cookie cookie; 6682 int next_credits, compl; 6683 struct fw_eth_tx_eo_wr *wr; 6684 6685 mtx_assert(&cst->lock, MA_OWNED); 6686 6687 while ((m = mbufq_first(&cst->pending_tx)) != NULL) { 6688 M_ASSERTPKTHDR(m); 6689 6690 /* How many len16 credits do we need to send this mbuf. */ 6691 next_credits = mbuf_eo_len16(m); 6692 MPASS(next_credits > 0); 6693 if (next_credits > cst->tx_credits) { 6694 /* 6695 * Tx will make progress eventually because there is at 6696 * least one outstanding fw4_ack that will return 6697 * credits and kick the tx. 6698 */ 6699 MPASS(cst->ncompl > 0); 6700 return; 6701 } 6702 wr = start_wrq_wr(&cst->eo_txq->wrq, next_credits, &cookie); 6703 if (__predict_false(wr == NULL)) { 6704 /* XXX: wishful thinking, not a real assertion. */ 6705 MPASS(cst->ncompl > 0); 6706 return; 6707 } 6708 cst->tx_credits -= next_credits; 6709 cst->tx_nocompl += next_credits; 6710 compl = cst->ncompl == 0 || cst->tx_nocompl >= cst->tx_total / 2; 6711 ETHER_BPF_MTAP(cst->com.ifp, m); 6712 write_ethofld_wr(cst, wr, m, compl); 6713 commit_wrq_wr(&cst->eo_txq->wrq, wr, &cookie); 6714 if (compl) { 6715 cst->ncompl++; 6716 cst->tx_nocompl = 0; 6717 } 6718 (void) mbufq_dequeue(&cst->pending_tx); 6719 6720 /* 6721 * Drop the mbuf's reference on the tag now rather 6722 * than waiting until m_freem(). This ensures that 6723 * cxgbe_rate_tag_free gets called when the inp drops 6724 * its reference on the tag and there are no more 6725 * mbufs in the pending_tx queue and can flush any 6726 * pending requests. Otherwise if the last mbuf 6727 * doesn't request a completion the etid will never be 6728 * released. 6729 */ 6730 m->m_pkthdr.snd_tag = NULL; 6731 m->m_pkthdr.csum_flags &= ~CSUM_SND_TAG; 6732 m_snd_tag_rele(&cst->com); 6733 6734 mbufq_enqueue(&cst->pending_fwack, m); 6735 } 6736 } 6737 6738 int 6739 ethofld_transmit(struct ifnet *ifp, struct mbuf *m0) 6740 { 6741 struct cxgbe_rate_tag *cst; 6742 int rc; 6743 6744 MPASS(m0->m_nextpkt == NULL); 6745 MPASS(m0->m_pkthdr.csum_flags & CSUM_SND_TAG); 6746 MPASS(m0->m_pkthdr.snd_tag != NULL); 6747 cst = mst_to_crt(m0->m_pkthdr.snd_tag); 6748 6749 mtx_lock(&cst->lock); 6750 MPASS(cst->flags & EO_SND_TAG_REF); 6751 6752 if (__predict_false(cst->flags & EO_FLOWC_PENDING)) { 6753 struct vi_info *vi = ifp->if_softc; 6754 struct port_info *pi = vi->pi; 6755 struct adapter *sc = pi->adapter; 6756 const uint32_t rss_mask = vi->rss_size - 1; 6757 uint32_t rss_hash; 6758 6759 cst->eo_txq = &sc->sge.ofld_txq[vi->first_ofld_txq]; 6760 if (M_HASHTYPE_ISHASH(m0)) 6761 rss_hash = m0->m_pkthdr.flowid; 6762 else 6763 rss_hash = arc4random(); 6764 /* We assume RSS hashing */ 6765 cst->iqid = vi->rss[rss_hash & rss_mask]; 6766 cst->eo_txq += rss_hash % vi->nofldtxq; 6767 rc = send_etid_flowc_wr(cst, pi, vi); 6768 if (rc != 0) 6769 goto done; 6770 } 6771 6772 if (__predict_false(cst->plen + m0->m_pkthdr.len > eo_max_backlog)) { 6773 rc = ENOBUFS; 6774 goto done; 6775 } 6776 6777 mbufq_enqueue(&cst->pending_tx, m0); 6778 cst->plen += m0->m_pkthdr.len; 6779 6780 /* 6781 * Hold an extra reference on the tag while generating work 6782 * requests to ensure that we don't try to free the tag during 6783 * ethofld_tx() in case we are sending the final mbuf after 6784 * the inp was freed. 6785 */ 6786 m_snd_tag_ref(&cst->com); 6787 ethofld_tx(cst); 6788 mtx_unlock(&cst->lock); 6789 m_snd_tag_rele(&cst->com); 6790 return (0); 6791 6792 done: 6793 mtx_unlock(&cst->lock); 6794 if (__predict_false(rc != 0)) 6795 m_freem(m0); 6796 return (rc); 6797 } 6798 6799 static int 6800 ethofld_fw4_ack(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0) 6801 { 6802 struct adapter *sc = iq->adapter; 6803 const struct cpl_fw4_ack *cpl = (const void *)(rss + 1); 6804 struct mbuf *m; 6805 u_int etid = G_CPL_FW4_ACK_FLOWID(be32toh(OPCODE_TID(cpl))); 6806 struct cxgbe_rate_tag *cst; 6807 uint8_t credits = cpl->credits; 6808 6809 cst = lookup_etid(sc, etid); 6810 mtx_lock(&cst->lock); 6811 if (__predict_false(cst->flags & EO_FLOWC_RPL_PENDING)) { 6812 MPASS(credits >= ETID_FLOWC_LEN16); 6813 credits -= ETID_FLOWC_LEN16; 6814 cst->flags &= ~EO_FLOWC_RPL_PENDING; 6815 } 6816 6817 KASSERT(cst->ncompl > 0, 6818 ("%s: etid %u (%p) wasn't expecting completion.", 6819 __func__, etid, cst)); 6820 cst->ncompl--; 6821 6822 while (credits > 0) { 6823 m = mbufq_dequeue(&cst->pending_fwack); 6824 if (__predict_false(m == NULL)) { 6825 /* 6826 * The remaining credits are for the final flush that 6827 * was issued when the tag was freed by the kernel. 6828 */ 6829 MPASS((cst->flags & 6830 (EO_FLUSH_RPL_PENDING | EO_SND_TAG_REF)) == 6831 EO_FLUSH_RPL_PENDING); 6832 MPASS(credits == ETID_FLUSH_LEN16); 6833 MPASS(cst->tx_credits + cpl->credits == cst->tx_total); 6834 MPASS(cst->ncompl == 0); 6835 6836 cst->flags &= ~EO_FLUSH_RPL_PENDING; 6837 cst->tx_credits += cpl->credits; 6838 cxgbe_rate_tag_free_locked(cst); 6839 return (0); /* cst is gone. */ 6840 } 6841 KASSERT(m != NULL, 6842 ("%s: too many credits (%u, %u)", __func__, cpl->credits, 6843 credits)); 6844 KASSERT(credits >= mbuf_eo_len16(m), 6845 ("%s: too few credits (%u, %u, %u)", __func__, 6846 cpl->credits, credits, mbuf_eo_len16(m))); 6847 credits -= mbuf_eo_len16(m); 6848 cst->plen -= m->m_pkthdr.len; 6849 m_freem(m); 6850 } 6851 6852 cst->tx_credits += cpl->credits; 6853 MPASS(cst->tx_credits <= cst->tx_total); 6854 6855 if (cst->flags & EO_SND_TAG_REF) { 6856 /* 6857 * As with ethofld_transmit(), hold an extra reference 6858 * so that the tag is stable across ethold_tx(). 6859 */ 6860 m_snd_tag_ref(&cst->com); 6861 m = mbufq_first(&cst->pending_tx); 6862 if (m != NULL && cst->tx_credits >= mbuf_eo_len16(m)) 6863 ethofld_tx(cst); 6864 mtx_unlock(&cst->lock); 6865 m_snd_tag_rele(&cst->com); 6866 } else { 6867 /* 6868 * There shouldn't be any pending packets if the tag 6869 * was freed by the kernel since any pending packet 6870 * should hold a reference to the tag. 6871 */ 6872 MPASS(mbufq_first(&cst->pending_tx) == NULL); 6873 mtx_unlock(&cst->lock); 6874 } 6875 6876 return (0); 6877 } 6878 #endif 6879