1 /*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 34 #include <sys/types.h> 35 #include <sys/eventhandler.h> 36 #include <sys/mbuf.h> 37 #include <sys/socket.h> 38 #include <sys/kernel.h> 39 #include <sys/malloc.h> 40 #include <sys/queue.h> 41 #include <sys/sbuf.h> 42 #include <sys/taskqueue.h> 43 #include <sys/time.h> 44 #include <sys/sglist.h> 45 #include <sys/sysctl.h> 46 #include <sys/smp.h> 47 #include <sys/counter.h> 48 #include <net/bpf.h> 49 #include <net/ethernet.h> 50 #include <net/if.h> 51 #include <net/if_vlan_var.h> 52 #include <netinet/in.h> 53 #include <netinet/ip.h> 54 #include <netinet/ip6.h> 55 #include <netinet/tcp.h> 56 #include <machine/md_var.h> 57 #include <vm/vm.h> 58 #include <vm/pmap.h> 59 #ifdef DEV_NETMAP 60 #include <machine/bus.h> 61 #include <sys/selinfo.h> 62 #include <net/if_var.h> 63 #include <net/netmap.h> 64 #include <dev/netmap/netmap_kern.h> 65 #endif 66 67 #include "common/common.h" 68 #include "common/t4_regs.h" 69 #include "common/t4_regs_values.h" 70 #include "common/t4_msg.h" 71 #include "t4_mp_ring.h" 72 73 #ifdef T4_PKT_TIMESTAMP 74 #define RX_COPY_THRESHOLD (MINCLSIZE - 8) 75 #else 76 #define RX_COPY_THRESHOLD MINCLSIZE 77 #endif 78 79 /* 80 * Ethernet frames are DMA'd at this byte offset into the freelist buffer. 81 * 0-7 are valid values. 82 */ 83 int fl_pktshift = 2; 84 TUNABLE_INT("hw.cxgbe.fl_pktshift", &fl_pktshift); 85 86 /* 87 * Pad ethernet payload up to this boundary. 88 * -1: driver should figure out a good value. 89 * 0: disable padding. 90 * Any power of 2 from 32 to 4096 (both inclusive) is also a valid value. 91 */ 92 int fl_pad = -1; 93 TUNABLE_INT("hw.cxgbe.fl_pad", &fl_pad); 94 95 /* 96 * Status page length. 97 * -1: driver should figure out a good value. 98 * 64 or 128 are the only other valid values. 99 */ 100 int spg_len = -1; 101 TUNABLE_INT("hw.cxgbe.spg_len", &spg_len); 102 103 /* 104 * Congestion drops. 105 * -1: no congestion feedback (not recommended). 106 * 0: backpressure the channel instead of dropping packets right away. 107 * 1: no backpressure, drop packets for the congested queue immediately. 108 */ 109 static int cong_drop = 0; 110 TUNABLE_INT("hw.cxgbe.cong_drop", &cong_drop); 111 112 /* 113 * Deliver multiple frames in the same free list buffer if they fit. 114 * -1: let the driver decide whether to enable buffer packing or not. 115 * 0: disable buffer packing. 116 * 1: enable buffer packing. 117 */ 118 static int buffer_packing = -1; 119 TUNABLE_INT("hw.cxgbe.buffer_packing", &buffer_packing); 120 121 /* 122 * Start next frame in a packed buffer at this boundary. 123 * -1: driver should figure out a good value. 124 * T4: driver will ignore this and use the same value as fl_pad above. 125 * T5: 16, or a power of 2 from 64 to 4096 (both inclusive) is a valid value. 126 */ 127 static int fl_pack = -1; 128 TUNABLE_INT("hw.cxgbe.fl_pack", &fl_pack); 129 130 /* 131 * Allow the driver to create mbuf(s) in a cluster allocated for rx. 132 * 0: never; always allocate mbufs from the zone_mbuf UMA zone. 133 * 1: ok to create mbuf(s) within a cluster if there is room. 134 */ 135 static int allow_mbufs_in_cluster = 1; 136 TUNABLE_INT("hw.cxgbe.allow_mbufs_in_cluster", &allow_mbufs_in_cluster); 137 138 /* 139 * Largest rx cluster size that the driver is allowed to allocate. 140 */ 141 static int largest_rx_cluster = MJUM16BYTES; 142 TUNABLE_INT("hw.cxgbe.largest_rx_cluster", &largest_rx_cluster); 143 144 /* 145 * Size of cluster allocation that's most likely to succeed. The driver will 146 * fall back to this size if it fails to allocate clusters larger than this. 147 */ 148 static int safest_rx_cluster = PAGE_SIZE; 149 TUNABLE_INT("hw.cxgbe.safest_rx_cluster", &safest_rx_cluster); 150 151 struct txpkts { 152 u_int wr_type; /* type 0 or type 1 */ 153 u_int npkt; /* # of packets in this work request */ 154 u_int plen; /* total payload (sum of all packets) */ 155 u_int len16; /* # of 16B pieces used by this work request */ 156 }; 157 158 /* A packet's SGL. This + m_pkthdr has all info needed for tx */ 159 struct sgl { 160 struct sglist sg; 161 struct sglist_seg seg[TX_SGL_SEGS]; 162 }; 163 164 static int service_iq(struct sge_iq *, int); 165 static struct mbuf *get_fl_payload(struct adapter *, struct sge_fl *, uint32_t); 166 static int t4_eth_rx(struct sge_iq *, const struct rss_header *, struct mbuf *); 167 static inline void init_iq(struct sge_iq *, struct adapter *, int, int, int); 168 static inline void init_fl(struct adapter *, struct sge_fl *, int, int, char *); 169 static inline void init_eq(struct adapter *, struct sge_eq *, int, int, uint8_t, 170 uint16_t, char *); 171 static int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *, 172 bus_addr_t *, void **); 173 static int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 174 void *); 175 static int alloc_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *, 176 int, int); 177 static int free_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *); 178 static void add_fl_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *, 179 struct sge_fl *); 180 static int alloc_fwq(struct adapter *); 181 static int free_fwq(struct adapter *); 182 static int alloc_mgmtq(struct adapter *); 183 static int free_mgmtq(struct adapter *); 184 static int alloc_rxq(struct vi_info *, struct sge_rxq *, int, int, 185 struct sysctl_oid *); 186 static int free_rxq(struct vi_info *, struct sge_rxq *); 187 #ifdef TCP_OFFLOAD 188 static int alloc_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *, int, int, 189 struct sysctl_oid *); 190 static int free_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *); 191 #endif 192 #ifdef DEV_NETMAP 193 static int alloc_nm_rxq(struct vi_info *, struct sge_nm_rxq *, int, int, 194 struct sysctl_oid *); 195 static int free_nm_rxq(struct vi_info *, struct sge_nm_rxq *); 196 static int alloc_nm_txq(struct vi_info *, struct sge_nm_txq *, int, int, 197 struct sysctl_oid *); 198 static int free_nm_txq(struct vi_info *, struct sge_nm_txq *); 199 #endif 200 static int ctrl_eq_alloc(struct adapter *, struct sge_eq *); 201 static int eth_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *); 202 #ifdef TCP_OFFLOAD 203 static int ofld_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *); 204 #endif 205 static int alloc_eq(struct adapter *, struct vi_info *, struct sge_eq *); 206 static int free_eq(struct adapter *, struct sge_eq *); 207 static int alloc_wrq(struct adapter *, struct vi_info *, struct sge_wrq *, 208 struct sysctl_oid *); 209 static int free_wrq(struct adapter *, struct sge_wrq *); 210 static int alloc_txq(struct vi_info *, struct sge_txq *, int, 211 struct sysctl_oid *); 212 static int free_txq(struct vi_info *, struct sge_txq *); 213 static void oneseg_dma_callback(void *, bus_dma_segment_t *, int, int); 214 static inline void ring_fl_db(struct adapter *, struct sge_fl *); 215 static int refill_fl(struct adapter *, struct sge_fl *, int); 216 static void refill_sfl(void *); 217 static int alloc_fl_sdesc(struct sge_fl *); 218 static void free_fl_sdesc(struct adapter *, struct sge_fl *); 219 static void find_best_refill_source(struct adapter *, struct sge_fl *, int); 220 static void find_safe_refill_source(struct adapter *, struct sge_fl *); 221 static void add_fl_to_sfl(struct adapter *, struct sge_fl *); 222 223 static inline void get_pkt_gl(struct mbuf *, struct sglist *); 224 static inline u_int txpkt_len16(u_int, u_int); 225 static inline u_int txpkts0_len16(u_int); 226 static inline u_int txpkts1_len16(void); 227 static u_int write_txpkt_wr(struct sge_txq *, struct fw_eth_tx_pkt_wr *, 228 struct mbuf *, u_int); 229 static int try_txpkts(struct mbuf *, struct mbuf *, struct txpkts *, u_int); 230 static int add_to_txpkts(struct mbuf *, struct txpkts *, u_int); 231 static u_int write_txpkts_wr(struct sge_txq *, struct fw_eth_tx_pkts_wr *, 232 struct mbuf *, const struct txpkts *, u_int); 233 static void write_gl_to_txd(struct sge_txq *, struct mbuf *, caddr_t *, int); 234 static inline void copy_to_txd(struct sge_eq *, caddr_t, caddr_t *, int); 235 static inline void ring_eq_db(struct adapter *, struct sge_eq *, u_int); 236 static inline uint16_t read_hw_cidx(struct sge_eq *); 237 static inline u_int reclaimable_tx_desc(struct sge_eq *); 238 static inline u_int total_available_tx_desc(struct sge_eq *); 239 static u_int reclaim_tx_descs(struct sge_txq *, u_int); 240 static void tx_reclaim(void *, int); 241 static __be64 get_flit(struct sglist_seg *, int, int); 242 static int handle_sge_egr_update(struct sge_iq *, const struct rss_header *, 243 struct mbuf *); 244 static int handle_fw_msg(struct sge_iq *, const struct rss_header *, 245 struct mbuf *); 246 static void wrq_tx_drain(void *, int); 247 static void drain_wrq_wr_list(struct adapter *, struct sge_wrq *); 248 249 static int sysctl_uint16(SYSCTL_HANDLER_ARGS); 250 static int sysctl_bufsizes(SYSCTL_HANDLER_ARGS); 251 252 static counter_u64_t extfree_refs; 253 static counter_u64_t extfree_rels; 254 255 /* 256 * Called on MOD_LOAD. Validates and calculates the SGE tunables. 257 */ 258 void 259 t4_sge_modload(void) 260 { 261 262 if (fl_pktshift < 0 || fl_pktshift > 7) { 263 printf("Invalid hw.cxgbe.fl_pktshift value (%d)," 264 " using 2 instead.\n", fl_pktshift); 265 fl_pktshift = 2; 266 } 267 268 if (spg_len != 64 && spg_len != 128) { 269 int len; 270 271 #if defined(__i386__) || defined(__amd64__) 272 len = cpu_clflush_line_size > 64 ? 128 : 64; 273 #else 274 len = 64; 275 #endif 276 if (spg_len != -1) { 277 printf("Invalid hw.cxgbe.spg_len value (%d)," 278 " using %d instead.\n", spg_len, len); 279 } 280 spg_len = len; 281 } 282 283 if (cong_drop < -1 || cong_drop > 1) { 284 printf("Invalid hw.cxgbe.cong_drop value (%d)," 285 " using 0 instead.\n", cong_drop); 286 cong_drop = 0; 287 } 288 289 extfree_refs = counter_u64_alloc(M_WAITOK); 290 extfree_rels = counter_u64_alloc(M_WAITOK); 291 counter_u64_zero(extfree_refs); 292 counter_u64_zero(extfree_rels); 293 } 294 295 void 296 t4_sge_modunload(void) 297 { 298 299 counter_u64_free(extfree_refs); 300 counter_u64_free(extfree_rels); 301 } 302 303 uint64_t 304 t4_sge_extfree_refs(void) 305 { 306 uint64_t refs, rels; 307 308 rels = counter_u64_fetch(extfree_rels); 309 refs = counter_u64_fetch(extfree_refs); 310 311 return (refs - rels); 312 } 313 314 void 315 t4_init_sge_cpl_handlers(struct adapter *sc) 316 { 317 318 t4_register_cpl_handler(sc, CPL_FW4_MSG, handle_fw_msg); 319 t4_register_cpl_handler(sc, CPL_FW6_MSG, handle_fw_msg); 320 t4_register_cpl_handler(sc, CPL_SGE_EGR_UPDATE, handle_sge_egr_update); 321 t4_register_cpl_handler(sc, CPL_RX_PKT, t4_eth_rx); 322 t4_register_fw_msg_handler(sc, FW6_TYPE_CMD_RPL, t4_handle_fw_rpl); 323 } 324 325 static inline void 326 setup_pad_and_pack_boundaries(struct adapter *sc) 327 { 328 uint32_t v, m; 329 int pad, pack; 330 331 pad = fl_pad; 332 if (fl_pad < 32 || fl_pad > 4096 || !powerof2(fl_pad)) { 333 /* 334 * If there is any chance that we might use buffer packing and 335 * the chip is a T4, then pick 64 as the pad/pack boundary. Set 336 * it to 32 in all other cases. 337 */ 338 pad = is_t4(sc) && buffer_packing ? 64 : 32; 339 340 /* 341 * For fl_pad = 0 we'll still write a reasonable value to the 342 * register but all the freelists will opt out of padding. 343 * We'll complain here only if the user tried to set it to a 344 * value greater than 0 that was invalid. 345 */ 346 if (fl_pad > 0) { 347 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pad value" 348 " (%d), using %d instead.\n", fl_pad, pad); 349 } 350 } 351 m = V_INGPADBOUNDARY(M_INGPADBOUNDARY); 352 v = V_INGPADBOUNDARY(ilog2(pad) - 5); 353 t4_set_reg_field(sc, A_SGE_CONTROL, m, v); 354 355 if (is_t4(sc)) { 356 if (fl_pack != -1 && fl_pack != pad) { 357 /* Complain but carry on. */ 358 device_printf(sc->dev, "hw.cxgbe.fl_pack (%d) ignored," 359 " using %d instead.\n", fl_pack, pad); 360 } 361 return; 362 } 363 364 pack = fl_pack; 365 if (fl_pack < 16 || fl_pack == 32 || fl_pack > 4096 || 366 !powerof2(fl_pack)) { 367 pack = max(sc->params.pci.mps, CACHE_LINE_SIZE); 368 MPASS(powerof2(pack)); 369 if (pack < 16) 370 pack = 16; 371 if (pack == 32) 372 pack = 64; 373 if (pack > 4096) 374 pack = 4096; 375 if (fl_pack != -1) { 376 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pack value" 377 " (%d), using %d instead.\n", fl_pack, pack); 378 } 379 } 380 m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY); 381 if (pack == 16) 382 v = V_INGPACKBOUNDARY(0); 383 else 384 v = V_INGPACKBOUNDARY(ilog2(pack) - 5); 385 386 MPASS(!is_t4(sc)); /* T4 doesn't have SGE_CONTROL2 */ 387 t4_set_reg_field(sc, A_SGE_CONTROL2, m, v); 388 } 389 390 /* 391 * adap->params.vpd.cclk must be set up before this is called. 392 */ 393 void 394 t4_tweak_chip_settings(struct adapter *sc) 395 { 396 int i; 397 uint32_t v, m; 398 int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200}; 399 int timer_max = M_TIMERVALUE0 * 1000 / sc->params.vpd.cclk; 400 int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */ 401 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 402 static int sge_flbuf_sizes[] = { 403 MCLBYTES, 404 #if MJUMPAGESIZE != MCLBYTES 405 MJUMPAGESIZE, 406 MJUMPAGESIZE - CL_METADATA_SIZE, 407 MJUMPAGESIZE - 2 * MSIZE - CL_METADATA_SIZE, 408 #endif 409 MJUM9BYTES, 410 MJUM16BYTES, 411 MCLBYTES - MSIZE - CL_METADATA_SIZE, 412 MJUM9BYTES - CL_METADATA_SIZE, 413 MJUM16BYTES - CL_METADATA_SIZE, 414 }; 415 416 KASSERT(sc->flags & MASTER_PF, 417 ("%s: trying to change chip settings when not master.", __func__)); 418 419 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE; 420 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE | 421 V_EGRSTATUSPAGESIZE(spg_len == 128); 422 t4_set_reg_field(sc, A_SGE_CONTROL, m, v); 423 424 setup_pad_and_pack_boundaries(sc); 425 426 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) | 427 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) | 428 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) | 429 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) | 430 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) | 431 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) | 432 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) | 433 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10); 434 t4_write_reg(sc, A_SGE_HOST_PAGE_SIZE, v); 435 436 KASSERT(nitems(sge_flbuf_sizes) <= SGE_FLBUF_SIZES, 437 ("%s: hw buffer size table too big", __func__)); 438 for (i = 0; i < min(nitems(sge_flbuf_sizes), SGE_FLBUF_SIZES); i++) { 439 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0 + (4 * i), 440 sge_flbuf_sizes[i]); 441 } 442 443 v = V_THRESHOLD_0(intr_pktcount[0]) | V_THRESHOLD_1(intr_pktcount[1]) | 444 V_THRESHOLD_2(intr_pktcount[2]) | V_THRESHOLD_3(intr_pktcount[3]); 445 t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD, v); 446 447 KASSERT(intr_timer[0] <= timer_max, 448 ("%s: not a single usable timer (%d, %d)", __func__, intr_timer[0], 449 timer_max)); 450 for (i = 1; i < nitems(intr_timer); i++) { 451 KASSERT(intr_timer[i] >= intr_timer[i - 1], 452 ("%s: timers not listed in increasing order (%d)", 453 __func__, i)); 454 455 while (intr_timer[i] > timer_max) { 456 if (i == nitems(intr_timer) - 1) { 457 intr_timer[i] = timer_max; 458 break; 459 } 460 intr_timer[i] += intr_timer[i - 1]; 461 intr_timer[i] /= 2; 462 } 463 } 464 465 v = V_TIMERVALUE0(us_to_core_ticks(sc, intr_timer[0])) | 466 V_TIMERVALUE1(us_to_core_ticks(sc, intr_timer[1])); 467 t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1, v); 468 v = V_TIMERVALUE2(us_to_core_ticks(sc, intr_timer[2])) | 469 V_TIMERVALUE3(us_to_core_ticks(sc, intr_timer[3])); 470 t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3, v); 471 v = V_TIMERVALUE4(us_to_core_ticks(sc, intr_timer[4])) | 472 V_TIMERVALUE5(us_to_core_ticks(sc, intr_timer[5])); 473 t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5, v); 474 475 /* 4K, 16K, 64K, 256K DDP "page sizes" */ 476 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 477 t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, v); 478 479 m = v = F_TDDPTAGTCB; 480 t4_set_reg_field(sc, A_ULP_RX_CTL, m, v); 481 482 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 483 F_RESETDDPOFFSET; 484 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 485 t4_set_reg_field(sc, A_TP_PARA_REG5, m, v); 486 } 487 488 /* 489 * SGE wants the buffer to be at least 64B and then a multiple of 16. If 490 * padding is is use the buffer's start and end need to be aligned to the pad 491 * boundary as well. We'll just make sure that the size is a multiple of the 492 * boundary here, it is up to the buffer allocation code to make sure the start 493 * of the buffer is aligned as well. 494 */ 495 static inline int 496 hwsz_ok(struct adapter *sc, int hwsz) 497 { 498 int mask = fl_pad ? sc->params.sge.pad_boundary - 1 : 16 - 1; 499 500 return (hwsz >= 64 && (hwsz & mask) == 0); 501 } 502 503 /* 504 * XXX: driver really should be able to deal with unexpected settings. 505 */ 506 int 507 t4_read_chip_settings(struct adapter *sc) 508 { 509 struct sge *s = &sc->sge; 510 struct sge_params *sp = &sc->params.sge; 511 int i, j, n, rc = 0; 512 uint32_t m, v, r; 513 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 514 static int sw_buf_sizes[] = { /* Sorted by size */ 515 MCLBYTES, 516 #if MJUMPAGESIZE != MCLBYTES 517 MJUMPAGESIZE, 518 #endif 519 MJUM9BYTES, 520 MJUM16BYTES 521 }; 522 struct sw_zone_info *swz, *safe_swz; 523 struct hw_buf_info *hwb; 524 525 t4_init_sge_params(sc); 526 527 m = F_RXPKTCPLMODE; 528 v = F_RXPKTCPLMODE; 529 r = t4_read_reg(sc, A_SGE_CONTROL); 530 if ((r & m) != v) { 531 device_printf(sc->dev, "invalid SGE_CONTROL(0x%x)\n", r); 532 rc = EINVAL; 533 } 534 535 /* 536 * If this changes then every single use of PAGE_SHIFT in the driver 537 * needs to be carefully reviewed for PAGE_SHIFT vs sp->page_shift. 538 */ 539 if (sp->page_shift != PAGE_SHIFT) { 540 device_printf(sc->dev, "invalid SGE_HOST_PAGE_SIZE(0x%x)\n", r); 541 rc = EINVAL; 542 } 543 544 /* Filter out unusable hw buffer sizes entirely (mark with -2). */ 545 hwb = &s->hw_buf_info[0]; 546 for (i = 0; i < nitems(s->hw_buf_info); i++, hwb++) { 547 r = t4_read_reg(sc, A_SGE_FL_BUFFER_SIZE0 + (4 * i)); 548 hwb->size = r; 549 hwb->zidx = hwsz_ok(sc, r) ? -1 : -2; 550 hwb->next = -1; 551 } 552 553 /* 554 * Create a sorted list in decreasing order of hw buffer sizes (and so 555 * increasing order of spare area) for each software zone. 556 * 557 * If padding is enabled then the start and end of the buffer must align 558 * to the pad boundary; if packing is enabled then they must align with 559 * the pack boundary as well. Allocations from the cluster zones are 560 * aligned to min(size, 4K), so the buffer starts at that alignment and 561 * ends at hwb->size alignment. If mbuf inlining is allowed the 562 * starting alignment will be reduced to MSIZE and the driver will 563 * exercise appropriate caution when deciding on the best buffer layout 564 * to use. 565 */ 566 n = 0; /* no usable buffer size to begin with */ 567 swz = &s->sw_zone_info[0]; 568 safe_swz = NULL; 569 for (i = 0; i < SW_ZONE_SIZES; i++, swz++) { 570 int8_t head = -1, tail = -1; 571 572 swz->size = sw_buf_sizes[i]; 573 swz->zone = m_getzone(swz->size); 574 swz->type = m_gettype(swz->size); 575 576 if (swz->size < PAGE_SIZE) { 577 MPASS(powerof2(swz->size)); 578 if (fl_pad && (swz->size % sp->pad_boundary != 0)) 579 continue; 580 } 581 582 if (swz->size == safest_rx_cluster) 583 safe_swz = swz; 584 585 hwb = &s->hw_buf_info[0]; 586 for (j = 0; j < SGE_FLBUF_SIZES; j++, hwb++) { 587 if (hwb->zidx != -1 || hwb->size > swz->size) 588 continue; 589 #ifdef INVARIANTS 590 if (fl_pad) 591 MPASS(hwb->size % sp->pad_boundary == 0); 592 #endif 593 hwb->zidx = i; 594 if (head == -1) 595 head = tail = j; 596 else if (hwb->size < s->hw_buf_info[tail].size) { 597 s->hw_buf_info[tail].next = j; 598 tail = j; 599 } else { 600 int8_t *cur; 601 struct hw_buf_info *t; 602 603 for (cur = &head; *cur != -1; cur = &t->next) { 604 t = &s->hw_buf_info[*cur]; 605 if (hwb->size == t->size) { 606 hwb->zidx = -2; 607 break; 608 } 609 if (hwb->size > t->size) { 610 hwb->next = *cur; 611 *cur = j; 612 break; 613 } 614 } 615 } 616 } 617 swz->head_hwidx = head; 618 swz->tail_hwidx = tail; 619 620 if (tail != -1) { 621 n++; 622 if (swz->size - s->hw_buf_info[tail].size >= 623 CL_METADATA_SIZE) 624 sc->flags |= BUF_PACKING_OK; 625 } 626 } 627 if (n == 0) { 628 device_printf(sc->dev, "no usable SGE FL buffer size.\n"); 629 rc = EINVAL; 630 } 631 632 s->safe_hwidx1 = -1; 633 s->safe_hwidx2 = -1; 634 if (safe_swz != NULL) { 635 s->safe_hwidx1 = safe_swz->head_hwidx; 636 for (i = safe_swz->head_hwidx; i != -1; i = hwb->next) { 637 int spare; 638 639 hwb = &s->hw_buf_info[i]; 640 #ifdef INVARIANTS 641 if (fl_pad) 642 MPASS(hwb->size % sp->pad_boundary == 0); 643 #endif 644 spare = safe_swz->size - hwb->size; 645 if (spare >= CL_METADATA_SIZE) { 646 s->safe_hwidx2 = i; 647 break; 648 } 649 } 650 } 651 652 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 653 r = t4_read_reg(sc, A_ULP_RX_TDDP_PSZ); 654 if (r != v) { 655 device_printf(sc->dev, "invalid ULP_RX_TDDP_PSZ(0x%x)\n", r); 656 rc = EINVAL; 657 } 658 659 m = v = F_TDDPTAGTCB; 660 r = t4_read_reg(sc, A_ULP_RX_CTL); 661 if ((r & m) != v) { 662 device_printf(sc->dev, "invalid ULP_RX_CTL(0x%x)\n", r); 663 rc = EINVAL; 664 } 665 666 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 667 F_RESETDDPOFFSET; 668 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 669 r = t4_read_reg(sc, A_TP_PARA_REG5); 670 if ((r & m) != v) { 671 device_printf(sc->dev, "invalid TP_PARA_REG5(0x%x)\n", r); 672 rc = EINVAL; 673 } 674 675 t4_init_tp_params(sc); 676 677 t4_read_mtu_tbl(sc, sc->params.mtus, NULL); 678 t4_load_mtus(sc, sc->params.mtus, sc->params.a_wnd, sc->params.b_wnd); 679 680 return (rc); 681 } 682 683 int 684 t4_create_dma_tag(struct adapter *sc) 685 { 686 int rc; 687 688 rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0, 689 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE, 690 BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL, 691 NULL, &sc->dmat); 692 if (rc != 0) { 693 device_printf(sc->dev, 694 "failed to create main DMA tag: %d\n", rc); 695 } 696 697 return (rc); 698 } 699 700 void 701 t4_sge_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx, 702 struct sysctl_oid_list *children) 703 { 704 struct sge_params *sp = &sc->params.sge; 705 706 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "buffer_sizes", 707 CTLTYPE_STRING | CTLFLAG_RD, &sc->sge, 0, sysctl_bufsizes, "A", 708 "freelist buffer sizes"); 709 710 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pktshift", CTLFLAG_RD, 711 NULL, sp->fl_pktshift, "payload DMA offset in rx buffer (bytes)"); 712 713 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pad", CTLFLAG_RD, 714 NULL, sp->pad_boundary, "payload pad boundary (bytes)"); 715 716 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "spg_len", CTLFLAG_RD, 717 NULL, sp->spg_len, "status page size (bytes)"); 718 719 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_drop", CTLFLAG_RD, 720 NULL, cong_drop, "congestion drop setting"); 721 722 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pack", CTLFLAG_RD, 723 NULL, sp->pack_boundary, "payload pack boundary (bytes)"); 724 } 725 726 int 727 t4_destroy_dma_tag(struct adapter *sc) 728 { 729 if (sc->dmat) 730 bus_dma_tag_destroy(sc->dmat); 731 732 return (0); 733 } 734 735 /* 736 * Allocate and initialize the firmware event queue and the management queue. 737 * 738 * Returns errno on failure. Resources allocated up to that point may still be 739 * allocated. Caller is responsible for cleanup in case this function fails. 740 */ 741 int 742 t4_setup_adapter_queues(struct adapter *sc) 743 { 744 int rc; 745 746 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 747 748 sysctl_ctx_init(&sc->ctx); 749 sc->flags |= ADAP_SYSCTL_CTX; 750 751 /* 752 * Firmware event queue 753 */ 754 rc = alloc_fwq(sc); 755 if (rc != 0) 756 return (rc); 757 758 /* 759 * Management queue. This is just a control queue that uses the fwq as 760 * its associated iq. 761 */ 762 rc = alloc_mgmtq(sc); 763 764 return (rc); 765 } 766 767 /* 768 * Idempotent 769 */ 770 int 771 t4_teardown_adapter_queues(struct adapter *sc) 772 { 773 774 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 775 776 /* Do this before freeing the queue */ 777 if (sc->flags & ADAP_SYSCTL_CTX) { 778 sysctl_ctx_free(&sc->ctx); 779 sc->flags &= ~ADAP_SYSCTL_CTX; 780 } 781 782 free_mgmtq(sc); 783 free_fwq(sc); 784 785 return (0); 786 } 787 788 static inline int 789 first_vector(struct vi_info *vi) 790 { 791 struct adapter *sc = vi->pi->adapter; 792 793 if (sc->intr_count == 1) 794 return (0); 795 796 return (vi->first_intr); 797 } 798 799 /* 800 * Given an arbitrary "index," come up with an iq that can be used by other 801 * queues (of this VI) for interrupt forwarding, SGE egress updates, etc. 802 * The iq returned is guaranteed to be something that takes direct interrupts. 803 */ 804 static struct sge_iq * 805 vi_intr_iq(struct vi_info *vi, int idx) 806 { 807 struct adapter *sc = vi->pi->adapter; 808 struct sge *s = &sc->sge; 809 struct sge_iq *iq = NULL; 810 int nintr, i; 811 812 if (sc->intr_count == 1) 813 return (&sc->sge.fwq); 814 815 KASSERT(!(vi->flags & VI_NETMAP), 816 ("%s: called on netmap VI", __func__)); 817 nintr = vi->nintr; 818 KASSERT(nintr != 0, 819 ("%s: vi %p has no exclusive interrupts, total interrupts = %d", 820 __func__, vi, sc->intr_count)); 821 i = idx % nintr; 822 823 if (vi->flags & INTR_RXQ) { 824 if (i < vi->nrxq) { 825 iq = &s->rxq[vi->first_rxq + i].iq; 826 goto done; 827 } 828 i -= vi->nrxq; 829 } 830 #ifdef TCP_OFFLOAD 831 if (vi->flags & INTR_OFLD_RXQ) { 832 if (i < vi->nofldrxq) { 833 iq = &s->ofld_rxq[vi->first_ofld_rxq + i].iq; 834 goto done; 835 } 836 i -= vi->nofldrxq; 837 } 838 #endif 839 panic("%s: vi %p, intr_flags 0x%lx, idx %d, total intr %d\n", __func__, 840 vi, vi->flags & INTR_ALL, idx, nintr); 841 done: 842 MPASS(iq != NULL); 843 KASSERT(iq->flags & IQ_INTR, 844 ("%s: iq %p (vi %p, intr_flags 0x%lx, idx %d)", __func__, iq, vi, 845 vi->flags & INTR_ALL, idx)); 846 return (iq); 847 } 848 849 /* Maximum payload that can be delivered with a single iq descriptor */ 850 static inline int 851 mtu_to_max_payload(struct adapter *sc, int mtu, const int toe) 852 { 853 int payload; 854 855 #ifdef TCP_OFFLOAD 856 if (toe) { 857 payload = sc->tt.rx_coalesce ? 858 G_RXCOALESCESIZE(t4_read_reg(sc, A_TP_PARA_REG2)) : mtu; 859 } else { 860 #endif 861 /* large enough even when hw VLAN extraction is disabled */ 862 payload = sc->params.sge.fl_pktshift + ETHER_HDR_LEN + 863 ETHER_VLAN_ENCAP_LEN + mtu; 864 #ifdef TCP_OFFLOAD 865 } 866 #endif 867 868 return (payload); 869 } 870 871 int 872 t4_setup_vi_queues(struct vi_info *vi) 873 { 874 int rc = 0, i, j, intr_idx, iqid; 875 struct sge_rxq *rxq; 876 struct sge_txq *txq; 877 struct sge_wrq *ctrlq; 878 #ifdef TCP_OFFLOAD 879 struct sge_ofld_rxq *ofld_rxq; 880 struct sge_wrq *ofld_txq; 881 #endif 882 #ifdef DEV_NETMAP 883 struct sge_nm_rxq *nm_rxq; 884 struct sge_nm_txq *nm_txq; 885 #endif 886 char name[16]; 887 struct port_info *pi = vi->pi; 888 struct adapter *sc = pi->adapter; 889 struct ifnet *ifp = vi->ifp; 890 struct sysctl_oid *oid = device_get_sysctl_tree(vi->dev); 891 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 892 int maxp, mtu = ifp->if_mtu; 893 894 /* Interrupt vector to start from (when using multiple vectors) */ 895 intr_idx = first_vector(vi); 896 897 #ifdef DEV_NETMAP 898 if (vi->flags & VI_NETMAP) { 899 /* 900 * We don't have buffers to back the netmap rx queues 901 * right now so we create the queues in a way that 902 * doesn't set off any congestion signal in the chip. 903 */ 904 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "rxq", 905 CTLFLAG_RD, NULL, "rx queues"); 906 for_each_nm_rxq(vi, i, nm_rxq) { 907 rc = alloc_nm_rxq(vi, nm_rxq, intr_idx, i, oid); 908 if (rc != 0) 909 goto done; 910 intr_idx++; 911 } 912 913 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "txq", 914 CTLFLAG_RD, NULL, "tx queues"); 915 for_each_nm_txq(vi, i, nm_txq) { 916 iqid = vi->first_rxq + (i % vi->nrxq); 917 rc = alloc_nm_txq(vi, nm_txq, iqid, i, oid); 918 if (rc != 0) 919 goto done; 920 } 921 goto done; 922 } 923 #endif 924 925 /* 926 * First pass over all NIC and TOE rx queues: 927 * a) initialize iq and fl 928 * b) allocate queue iff it will take direct interrupts. 929 */ 930 maxp = mtu_to_max_payload(sc, mtu, 0); 931 if (vi->flags & INTR_RXQ) { 932 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "rxq", 933 CTLFLAG_RD, NULL, "rx queues"); 934 } 935 for_each_rxq(vi, i, rxq) { 936 937 init_iq(&rxq->iq, sc, vi->tmr_idx, vi->pktc_idx, vi->qsize_rxq); 938 939 snprintf(name, sizeof(name), "%s rxq%d-fl", 940 device_get_nameunit(vi->dev), i); 941 init_fl(sc, &rxq->fl, vi->qsize_rxq / 8, maxp, name); 942 943 if (vi->flags & INTR_RXQ) { 944 rxq->iq.flags |= IQ_INTR; 945 rc = alloc_rxq(vi, rxq, intr_idx, i, oid); 946 if (rc != 0) 947 goto done; 948 intr_idx++; 949 } 950 } 951 #ifdef TCP_OFFLOAD 952 maxp = mtu_to_max_payload(sc, mtu, 1); 953 if (vi->flags & INTR_OFLD_RXQ) { 954 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_rxq", 955 CTLFLAG_RD, NULL, 956 "rx queues for offloaded TCP connections"); 957 } 958 for_each_ofld_rxq(vi, i, ofld_rxq) { 959 960 init_iq(&ofld_rxq->iq, sc, vi->tmr_idx, vi->pktc_idx, 961 vi->qsize_rxq); 962 963 snprintf(name, sizeof(name), "%s ofld_rxq%d-fl", 964 device_get_nameunit(vi->dev), i); 965 init_fl(sc, &ofld_rxq->fl, vi->qsize_rxq / 8, maxp, name); 966 967 if (vi->flags & INTR_OFLD_RXQ) { 968 ofld_rxq->iq.flags |= IQ_INTR; 969 rc = alloc_ofld_rxq(vi, ofld_rxq, intr_idx, i, oid); 970 if (rc != 0) 971 goto done; 972 intr_idx++; 973 } 974 } 975 #endif 976 977 /* 978 * Second pass over all NIC and TOE rx queues. The queues forwarding 979 * their interrupts are allocated now. 980 */ 981 j = 0; 982 if (!(vi->flags & INTR_RXQ)) { 983 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "rxq", 984 CTLFLAG_RD, NULL, "rx queues"); 985 for_each_rxq(vi, i, rxq) { 986 MPASS(!(rxq->iq.flags & IQ_INTR)); 987 988 intr_idx = vi_intr_iq(vi, j)->abs_id; 989 990 rc = alloc_rxq(vi, rxq, intr_idx, i, oid); 991 if (rc != 0) 992 goto done; 993 j++; 994 } 995 } 996 #ifdef TCP_OFFLOAD 997 if (vi->nofldrxq != 0 && !(vi->flags & INTR_OFLD_RXQ)) { 998 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_rxq", 999 CTLFLAG_RD, NULL, 1000 "rx queues for offloaded TCP connections"); 1001 for_each_ofld_rxq(vi, i, ofld_rxq) { 1002 MPASS(!(ofld_rxq->iq.flags & IQ_INTR)); 1003 1004 intr_idx = vi_intr_iq(vi, j)->abs_id; 1005 1006 rc = alloc_ofld_rxq(vi, ofld_rxq, intr_idx, i, oid); 1007 if (rc != 0) 1008 goto done; 1009 j++; 1010 } 1011 } 1012 #endif 1013 1014 /* 1015 * Now the tx queues. Only one pass needed. 1016 */ 1017 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "txq", CTLFLAG_RD, 1018 NULL, "tx queues"); 1019 j = 0; 1020 for_each_txq(vi, i, txq) { 1021 iqid = vi_intr_iq(vi, j)->cntxt_id; 1022 snprintf(name, sizeof(name), "%s txq%d", 1023 device_get_nameunit(vi->dev), i); 1024 init_eq(sc, &txq->eq, EQ_ETH, vi->qsize_txq, pi->tx_chan, iqid, 1025 name); 1026 1027 rc = alloc_txq(vi, txq, i, oid); 1028 if (rc != 0) 1029 goto done; 1030 j++; 1031 } 1032 #ifdef TCP_OFFLOAD 1033 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_txq", 1034 CTLFLAG_RD, NULL, "tx queues for offloaded TCP connections"); 1035 for_each_ofld_txq(vi, i, ofld_txq) { 1036 struct sysctl_oid *oid2; 1037 1038 iqid = vi_intr_iq(vi, j)->cntxt_id; 1039 snprintf(name, sizeof(name), "%s ofld_txq%d", 1040 device_get_nameunit(vi->dev), i); 1041 init_eq(sc, &ofld_txq->eq, EQ_OFLD, vi->qsize_txq, pi->tx_chan, 1042 iqid, name); 1043 1044 snprintf(name, sizeof(name), "%d", i); 1045 oid2 = SYSCTL_ADD_NODE(&vi->ctx, SYSCTL_CHILDREN(oid), OID_AUTO, 1046 name, CTLFLAG_RD, NULL, "offload tx queue"); 1047 1048 rc = alloc_wrq(sc, vi, ofld_txq, oid2); 1049 if (rc != 0) 1050 goto done; 1051 j++; 1052 } 1053 #endif 1054 1055 /* 1056 * Finally, the control queue. 1057 */ 1058 if (!IS_MAIN_VI(vi)) 1059 goto done; 1060 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ctrlq", CTLFLAG_RD, 1061 NULL, "ctrl queue"); 1062 ctrlq = &sc->sge.ctrlq[pi->port_id]; 1063 iqid = vi_intr_iq(vi, 0)->cntxt_id; 1064 snprintf(name, sizeof(name), "%s ctrlq", device_get_nameunit(vi->dev)); 1065 init_eq(sc, &ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE, pi->tx_chan, iqid, 1066 name); 1067 rc = alloc_wrq(sc, vi, ctrlq, oid); 1068 1069 done: 1070 if (rc) 1071 t4_teardown_vi_queues(vi); 1072 1073 return (rc); 1074 } 1075 1076 /* 1077 * Idempotent 1078 */ 1079 int 1080 t4_teardown_vi_queues(struct vi_info *vi) 1081 { 1082 int i; 1083 struct port_info *pi = vi->pi; 1084 struct adapter *sc = pi->adapter; 1085 struct sge_rxq *rxq; 1086 struct sge_txq *txq; 1087 #ifdef TCP_OFFLOAD 1088 struct sge_ofld_rxq *ofld_rxq; 1089 struct sge_wrq *ofld_txq; 1090 #endif 1091 #ifdef DEV_NETMAP 1092 struct sge_nm_rxq *nm_rxq; 1093 struct sge_nm_txq *nm_txq; 1094 #endif 1095 1096 /* Do this before freeing the queues */ 1097 if (vi->flags & VI_SYSCTL_CTX) { 1098 sysctl_ctx_free(&vi->ctx); 1099 vi->flags &= ~VI_SYSCTL_CTX; 1100 } 1101 1102 #ifdef DEV_NETMAP 1103 if (vi->flags & VI_NETMAP) { 1104 for_each_nm_txq(vi, i, nm_txq) { 1105 free_nm_txq(vi, nm_txq); 1106 } 1107 1108 for_each_nm_rxq(vi, i, nm_rxq) { 1109 free_nm_rxq(vi, nm_rxq); 1110 } 1111 return (0); 1112 } 1113 #endif 1114 1115 /* 1116 * Take down all the tx queues first, as they reference the rx queues 1117 * (for egress updates, etc.). 1118 */ 1119 1120 if (IS_MAIN_VI(vi)) 1121 free_wrq(sc, &sc->sge.ctrlq[pi->port_id]); 1122 1123 for_each_txq(vi, i, txq) { 1124 free_txq(vi, txq); 1125 } 1126 #ifdef TCP_OFFLOAD 1127 for_each_ofld_txq(vi, i, ofld_txq) { 1128 free_wrq(sc, ofld_txq); 1129 } 1130 #endif 1131 1132 /* 1133 * Then take down the rx queues that forward their interrupts, as they 1134 * reference other rx queues. 1135 */ 1136 1137 for_each_rxq(vi, i, rxq) { 1138 if ((rxq->iq.flags & IQ_INTR) == 0) 1139 free_rxq(vi, rxq); 1140 } 1141 #ifdef TCP_OFFLOAD 1142 for_each_ofld_rxq(vi, i, ofld_rxq) { 1143 if ((ofld_rxq->iq.flags & IQ_INTR) == 0) 1144 free_ofld_rxq(vi, ofld_rxq); 1145 } 1146 #endif 1147 1148 /* 1149 * Then take down the rx queues that take direct interrupts. 1150 */ 1151 1152 for_each_rxq(vi, i, rxq) { 1153 if (rxq->iq.flags & IQ_INTR) 1154 free_rxq(vi, rxq); 1155 } 1156 #ifdef TCP_OFFLOAD 1157 for_each_ofld_rxq(vi, i, ofld_rxq) { 1158 if (ofld_rxq->iq.flags & IQ_INTR) 1159 free_ofld_rxq(vi, ofld_rxq); 1160 } 1161 #endif 1162 1163 return (0); 1164 } 1165 1166 /* 1167 * Deals with errors and the firmware event queue. All data rx queues forward 1168 * their interrupt to the firmware event queue. 1169 */ 1170 void 1171 t4_intr_all(void *arg) 1172 { 1173 struct adapter *sc = arg; 1174 struct sge_iq *fwq = &sc->sge.fwq; 1175 1176 t4_intr_err(arg); 1177 if (atomic_cmpset_int(&fwq->state, IQS_IDLE, IQS_BUSY)) { 1178 service_iq(fwq, 0); 1179 atomic_cmpset_int(&fwq->state, IQS_BUSY, IQS_IDLE); 1180 } 1181 } 1182 1183 /* Deals with error interrupts */ 1184 void 1185 t4_intr_err(void *arg) 1186 { 1187 struct adapter *sc = arg; 1188 1189 t4_write_reg(sc, MYPF_REG(A_PCIE_PF_CLI), 0); 1190 t4_slow_intr_handler(sc); 1191 } 1192 1193 void 1194 t4_intr_evt(void *arg) 1195 { 1196 struct sge_iq *iq = arg; 1197 1198 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 1199 service_iq(iq, 0); 1200 atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 1201 } 1202 } 1203 1204 void 1205 t4_intr(void *arg) 1206 { 1207 struct sge_iq *iq = arg; 1208 1209 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 1210 service_iq(iq, 0); 1211 atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 1212 } 1213 } 1214 1215 /* 1216 * Deals with anything and everything on the given ingress queue. 1217 */ 1218 static int 1219 service_iq(struct sge_iq *iq, int budget) 1220 { 1221 struct sge_iq *q; 1222 struct sge_rxq *rxq = iq_to_rxq(iq); /* Use iff iq is part of rxq */ 1223 struct sge_fl *fl; /* Use iff IQ_HAS_FL */ 1224 struct adapter *sc = iq->adapter; 1225 struct iq_desc *d = &iq->desc[iq->cidx]; 1226 int ndescs = 0, limit; 1227 int rsp_type, refill; 1228 uint32_t lq; 1229 uint16_t fl_hw_cidx; 1230 struct mbuf *m0; 1231 STAILQ_HEAD(, sge_iq) iql = STAILQ_HEAD_INITIALIZER(iql); 1232 #if defined(INET) || defined(INET6) 1233 const struct timeval lro_timeout = {0, sc->lro_timeout}; 1234 #endif 1235 1236 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq)); 1237 1238 limit = budget ? budget : iq->qsize / 16; 1239 1240 if (iq->flags & IQ_HAS_FL) { 1241 fl = &rxq->fl; 1242 fl_hw_cidx = fl->hw_cidx; /* stable snapshot */ 1243 } else { 1244 fl = NULL; 1245 fl_hw_cidx = 0; /* to silence gcc warning */ 1246 } 1247 1248 /* 1249 * We always come back and check the descriptor ring for new indirect 1250 * interrupts and other responses after running a single handler. 1251 */ 1252 for (;;) { 1253 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) { 1254 1255 rmb(); 1256 1257 refill = 0; 1258 m0 = NULL; 1259 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen); 1260 lq = be32toh(d->rsp.pldbuflen_qid); 1261 1262 switch (rsp_type) { 1263 case X_RSPD_TYPE_FLBUF: 1264 1265 KASSERT(iq->flags & IQ_HAS_FL, 1266 ("%s: data for an iq (%p) with no freelist", 1267 __func__, iq)); 1268 1269 m0 = get_fl_payload(sc, fl, lq); 1270 if (__predict_false(m0 == NULL)) 1271 goto process_iql; 1272 refill = IDXDIFF(fl->hw_cidx, fl_hw_cidx, fl->sidx) > 2; 1273 #ifdef T4_PKT_TIMESTAMP 1274 /* 1275 * 60 bit timestamp for the payload is 1276 * *(uint64_t *)m0->m_pktdat. Note that it is 1277 * in the leading free-space in the mbuf. The 1278 * kernel can clobber it during a pullup, 1279 * m_copymdata, etc. You need to make sure that 1280 * the mbuf reaches you unmolested if you care 1281 * about the timestamp. 1282 */ 1283 *(uint64_t *)m0->m_pktdat = 1284 be64toh(ctrl->u.last_flit) & 1285 0xfffffffffffffff; 1286 #endif 1287 1288 /* fall through */ 1289 1290 case X_RSPD_TYPE_CPL: 1291 KASSERT(d->rss.opcode < NUM_CPL_CMDS, 1292 ("%s: bad opcode %02x.", __func__, 1293 d->rss.opcode)); 1294 sc->cpl_handler[d->rss.opcode](iq, &d->rss, m0); 1295 break; 1296 1297 case X_RSPD_TYPE_INTR: 1298 1299 /* 1300 * Interrupts should be forwarded only to queues 1301 * that are not forwarding their interrupts. 1302 * This means service_iq can recurse but only 1 1303 * level deep. 1304 */ 1305 KASSERT(budget == 0, 1306 ("%s: budget %u, rsp_type %u", __func__, 1307 budget, rsp_type)); 1308 1309 /* 1310 * There are 1K interrupt-capable queues (qids 0 1311 * through 1023). A response type indicating a 1312 * forwarded interrupt with a qid >= 1K is an 1313 * iWARP async notification. 1314 */ 1315 if (lq >= 1024) { 1316 sc->an_handler(iq, &d->rsp); 1317 break; 1318 } 1319 1320 q = sc->sge.iqmap[lq - sc->sge.iq_start]; 1321 if (atomic_cmpset_int(&q->state, IQS_IDLE, 1322 IQS_BUSY)) { 1323 if (service_iq(q, q->qsize / 16) == 0) { 1324 atomic_cmpset_int(&q->state, 1325 IQS_BUSY, IQS_IDLE); 1326 } else { 1327 STAILQ_INSERT_TAIL(&iql, q, 1328 link); 1329 } 1330 } 1331 break; 1332 1333 default: 1334 KASSERT(0, 1335 ("%s: illegal response type %d on iq %p", 1336 __func__, rsp_type, iq)); 1337 log(LOG_ERR, 1338 "%s: illegal response type %d on iq %p", 1339 device_get_nameunit(sc->dev), rsp_type, iq); 1340 break; 1341 } 1342 1343 d++; 1344 if (__predict_false(++iq->cidx == iq->sidx)) { 1345 iq->cidx = 0; 1346 iq->gen ^= F_RSPD_GEN; 1347 d = &iq->desc[0]; 1348 } 1349 if (__predict_false(++ndescs == limit)) { 1350 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), 1351 V_CIDXINC(ndescs) | 1352 V_INGRESSQID(iq->cntxt_id) | 1353 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); 1354 ndescs = 0; 1355 1356 #if defined(INET) || defined(INET6) 1357 if (iq->flags & IQ_LRO_ENABLED && 1358 sc->lro_timeout != 0) { 1359 tcp_lro_flush_inactive(&rxq->lro, 1360 &lro_timeout); 1361 } 1362 #endif 1363 1364 if (budget) { 1365 if (iq->flags & IQ_HAS_FL) { 1366 FL_LOCK(fl); 1367 refill_fl(sc, fl, 32); 1368 FL_UNLOCK(fl); 1369 } 1370 return (EINPROGRESS); 1371 } 1372 } 1373 if (refill) { 1374 FL_LOCK(fl); 1375 refill_fl(sc, fl, 32); 1376 FL_UNLOCK(fl); 1377 fl_hw_cidx = fl->hw_cidx; 1378 } 1379 } 1380 1381 process_iql: 1382 if (STAILQ_EMPTY(&iql)) 1383 break; 1384 1385 /* 1386 * Process the head only, and send it to the back of the list if 1387 * it's still not done. 1388 */ 1389 q = STAILQ_FIRST(&iql); 1390 STAILQ_REMOVE_HEAD(&iql, link); 1391 if (service_iq(q, q->qsize / 8) == 0) 1392 atomic_cmpset_int(&q->state, IQS_BUSY, IQS_IDLE); 1393 else 1394 STAILQ_INSERT_TAIL(&iql, q, link); 1395 } 1396 1397 #if defined(INET) || defined(INET6) 1398 if (iq->flags & IQ_LRO_ENABLED) { 1399 struct lro_ctrl *lro = &rxq->lro; 1400 1401 tcp_lro_flush_all(lro); 1402 } 1403 #endif 1404 1405 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), V_CIDXINC(ndescs) | 1406 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params)); 1407 1408 if (iq->flags & IQ_HAS_FL) { 1409 int starved; 1410 1411 FL_LOCK(fl); 1412 starved = refill_fl(sc, fl, 64); 1413 FL_UNLOCK(fl); 1414 if (__predict_false(starved != 0)) 1415 add_fl_to_sfl(sc, fl); 1416 } 1417 1418 return (0); 1419 } 1420 1421 static inline int 1422 cl_has_metadata(struct sge_fl *fl, struct cluster_layout *cll) 1423 { 1424 int rc = fl->flags & FL_BUF_PACKING || cll->region1 > 0; 1425 1426 if (rc) 1427 MPASS(cll->region3 >= CL_METADATA_SIZE); 1428 1429 return (rc); 1430 } 1431 1432 static inline struct cluster_metadata * 1433 cl_metadata(struct adapter *sc, struct sge_fl *fl, struct cluster_layout *cll, 1434 caddr_t cl) 1435 { 1436 1437 if (cl_has_metadata(fl, cll)) { 1438 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx]; 1439 1440 return ((struct cluster_metadata *)(cl + swz->size) - 1); 1441 } 1442 return (NULL); 1443 } 1444 1445 static void 1446 rxb_free(struct mbuf *m, void *arg1, void *arg2) 1447 { 1448 uma_zone_t zone = arg1; 1449 caddr_t cl = arg2; 1450 1451 uma_zfree(zone, cl); 1452 counter_u64_add(extfree_rels, 1); 1453 } 1454 1455 /* 1456 * The mbuf returned by this function could be allocated from zone_mbuf or 1457 * constructed in spare room in the cluster. 1458 * 1459 * The mbuf carries the payload in one of these ways 1460 * a) frame inside the mbuf (mbuf from zone_mbuf) 1461 * b) m_cljset (for clusters without metadata) zone_mbuf 1462 * c) m_extaddref (cluster with metadata) inline mbuf 1463 * d) m_extaddref (cluster with metadata) zone_mbuf 1464 */ 1465 static struct mbuf * 1466 get_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset, 1467 int remaining) 1468 { 1469 struct mbuf *m; 1470 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 1471 struct cluster_layout *cll = &sd->cll; 1472 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx]; 1473 struct hw_buf_info *hwb = &sc->sge.hw_buf_info[cll->hwidx]; 1474 struct cluster_metadata *clm = cl_metadata(sc, fl, cll, sd->cl); 1475 int len, blen; 1476 caddr_t payload; 1477 1478 blen = hwb->size - fl->rx_offset; /* max possible in this buf */ 1479 len = min(remaining, blen); 1480 payload = sd->cl + cll->region1 + fl->rx_offset; 1481 if (fl->flags & FL_BUF_PACKING) { 1482 const u_int l = fr_offset + len; 1483 const u_int pad = roundup2(l, fl->buf_boundary) - l; 1484 1485 if (fl->rx_offset + len + pad < hwb->size) 1486 blen = len + pad; 1487 MPASS(fl->rx_offset + blen <= hwb->size); 1488 } else { 1489 MPASS(fl->rx_offset == 0); /* not packing */ 1490 } 1491 1492 1493 if (sc->sc_do_rxcopy && len < RX_COPY_THRESHOLD) { 1494 1495 /* 1496 * Copy payload into a freshly allocated mbuf. 1497 */ 1498 1499 m = fr_offset == 0 ? 1500 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA); 1501 if (m == NULL) 1502 return (NULL); 1503 fl->mbuf_allocated++; 1504 #ifdef T4_PKT_TIMESTAMP 1505 /* Leave room for a timestamp */ 1506 m->m_data += 8; 1507 #endif 1508 /* copy data to mbuf */ 1509 bcopy(payload, mtod(m, caddr_t), len); 1510 1511 } else if (sd->nmbuf * MSIZE < cll->region1) { 1512 1513 /* 1514 * There's spare room in the cluster for an mbuf. Create one 1515 * and associate it with the payload that's in the cluster. 1516 */ 1517 1518 MPASS(clm != NULL); 1519 m = (struct mbuf *)(sd->cl + sd->nmbuf * MSIZE); 1520 /* No bzero required */ 1521 if (m_init(m, M_NOWAIT, MT_DATA, 1522 fr_offset == 0 ? M_PKTHDR | M_NOFREE : M_NOFREE)) 1523 return (NULL); 1524 fl->mbuf_inlined++; 1525 m_extaddref(m, payload, blen, &clm->refcount, rxb_free, 1526 swz->zone, sd->cl); 1527 if (sd->nmbuf++ == 0) 1528 counter_u64_add(extfree_refs, 1); 1529 1530 } else { 1531 1532 /* 1533 * Grab an mbuf from zone_mbuf and associate it with the 1534 * payload in the cluster. 1535 */ 1536 1537 m = fr_offset == 0 ? 1538 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA); 1539 if (m == NULL) 1540 return (NULL); 1541 fl->mbuf_allocated++; 1542 if (clm != NULL) { 1543 m_extaddref(m, payload, blen, &clm->refcount, 1544 rxb_free, swz->zone, sd->cl); 1545 if (sd->nmbuf++ == 0) 1546 counter_u64_add(extfree_refs, 1); 1547 } else { 1548 m_cljset(m, sd->cl, swz->type); 1549 sd->cl = NULL; /* consumed, not a recycle candidate */ 1550 } 1551 } 1552 if (fr_offset == 0) 1553 m->m_pkthdr.len = remaining; 1554 m->m_len = len; 1555 1556 if (fl->flags & FL_BUF_PACKING) { 1557 fl->rx_offset += blen; 1558 MPASS(fl->rx_offset <= hwb->size); 1559 if (fl->rx_offset < hwb->size) 1560 return (m); /* without advancing the cidx */ 1561 } 1562 1563 if (__predict_false(++fl->cidx % 8 == 0)) { 1564 uint16_t cidx = fl->cidx / 8; 1565 1566 if (__predict_false(cidx == fl->sidx)) 1567 fl->cidx = cidx = 0; 1568 fl->hw_cidx = cidx; 1569 } 1570 fl->rx_offset = 0; 1571 1572 return (m); 1573 } 1574 1575 static struct mbuf * 1576 get_fl_payload(struct adapter *sc, struct sge_fl *fl, uint32_t len_newbuf) 1577 { 1578 struct mbuf *m0, *m, **pnext; 1579 u_int remaining; 1580 const u_int total = G_RSPD_LEN(len_newbuf); 1581 1582 if (__predict_false(fl->flags & FL_BUF_RESUME)) { 1583 M_ASSERTPKTHDR(fl->m0); 1584 MPASS(fl->m0->m_pkthdr.len == total); 1585 MPASS(fl->remaining < total); 1586 1587 m0 = fl->m0; 1588 pnext = fl->pnext; 1589 remaining = fl->remaining; 1590 fl->flags &= ~FL_BUF_RESUME; 1591 goto get_segment; 1592 } 1593 1594 if (fl->rx_offset > 0 && len_newbuf & F_RSPD_NEWBUF) { 1595 fl->rx_offset = 0; 1596 if (__predict_false(++fl->cidx % 8 == 0)) { 1597 uint16_t cidx = fl->cidx / 8; 1598 1599 if (__predict_false(cidx == fl->sidx)) 1600 fl->cidx = cidx = 0; 1601 fl->hw_cidx = cidx; 1602 } 1603 } 1604 1605 /* 1606 * Payload starts at rx_offset in the current hw buffer. Its length is 1607 * 'len' and it may span multiple hw buffers. 1608 */ 1609 1610 m0 = get_scatter_segment(sc, fl, 0, total); 1611 if (m0 == NULL) 1612 return (NULL); 1613 remaining = total - m0->m_len; 1614 pnext = &m0->m_next; 1615 while (remaining > 0) { 1616 get_segment: 1617 MPASS(fl->rx_offset == 0); 1618 m = get_scatter_segment(sc, fl, total - remaining, remaining); 1619 if (__predict_false(m == NULL)) { 1620 fl->m0 = m0; 1621 fl->pnext = pnext; 1622 fl->remaining = remaining; 1623 fl->flags |= FL_BUF_RESUME; 1624 return (NULL); 1625 } 1626 *pnext = m; 1627 pnext = &m->m_next; 1628 remaining -= m->m_len; 1629 } 1630 *pnext = NULL; 1631 1632 M_ASSERTPKTHDR(m0); 1633 return (m0); 1634 } 1635 1636 static int 1637 t4_eth_rx(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0) 1638 { 1639 struct sge_rxq *rxq = iq_to_rxq(iq); 1640 struct ifnet *ifp = rxq->ifp; 1641 struct adapter *sc = iq->adapter; 1642 const struct cpl_rx_pkt *cpl = (const void *)(rss + 1); 1643 #if defined(INET) || defined(INET6) 1644 struct lro_ctrl *lro = &rxq->lro; 1645 #endif 1646 static const int sw_hashtype[4][2] = { 1647 {M_HASHTYPE_NONE, M_HASHTYPE_NONE}, 1648 {M_HASHTYPE_RSS_IPV4, M_HASHTYPE_RSS_IPV6}, 1649 {M_HASHTYPE_RSS_TCP_IPV4, M_HASHTYPE_RSS_TCP_IPV6}, 1650 {M_HASHTYPE_RSS_UDP_IPV4, M_HASHTYPE_RSS_UDP_IPV6}, 1651 }; 1652 1653 KASSERT(m0 != NULL, ("%s: no payload with opcode %02x", __func__, 1654 rss->opcode)); 1655 1656 m0->m_pkthdr.len -= sc->params.sge.fl_pktshift; 1657 m0->m_len -= sc->params.sge.fl_pktshift; 1658 m0->m_data += sc->params.sge.fl_pktshift; 1659 1660 m0->m_pkthdr.rcvif = ifp; 1661 M_HASHTYPE_SET(m0, sw_hashtype[rss->hash_type][rss->ipv6]); 1662 m0->m_pkthdr.flowid = be32toh(rss->hash_val); 1663 1664 if (cpl->csum_calc && !cpl->err_vec) { 1665 if (ifp->if_capenable & IFCAP_RXCSUM && 1666 cpl->l2info & htobe32(F_RXF_IP)) { 1667 m0->m_pkthdr.csum_flags = (CSUM_IP_CHECKED | 1668 CSUM_IP_VALID | CSUM_DATA_VALID | CSUM_PSEUDO_HDR); 1669 rxq->rxcsum++; 1670 } else if (ifp->if_capenable & IFCAP_RXCSUM_IPV6 && 1671 cpl->l2info & htobe32(F_RXF_IP6)) { 1672 m0->m_pkthdr.csum_flags = (CSUM_DATA_VALID_IPV6 | 1673 CSUM_PSEUDO_HDR); 1674 rxq->rxcsum++; 1675 } 1676 1677 if (__predict_false(cpl->ip_frag)) 1678 m0->m_pkthdr.csum_data = be16toh(cpl->csum); 1679 else 1680 m0->m_pkthdr.csum_data = 0xffff; 1681 } 1682 1683 if (cpl->vlan_ex) { 1684 m0->m_pkthdr.ether_vtag = be16toh(cpl->vlan); 1685 m0->m_flags |= M_VLANTAG; 1686 rxq->vlan_extraction++; 1687 } 1688 1689 #if defined(INET) || defined(INET6) 1690 if (cpl->l2info & htobe32(F_RXF_LRO) && 1691 iq->flags & IQ_LRO_ENABLED && 1692 tcp_lro_rx(lro, m0, 0) == 0) { 1693 /* queued for LRO */ 1694 } else 1695 #endif 1696 ifp->if_input(ifp, m0); 1697 1698 return (0); 1699 } 1700 1701 /* 1702 * Must drain the wrq or make sure that someone else will. 1703 */ 1704 static void 1705 wrq_tx_drain(void *arg, int n) 1706 { 1707 struct sge_wrq *wrq = arg; 1708 struct sge_eq *eq = &wrq->eq; 1709 1710 EQ_LOCK(eq); 1711 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 1712 drain_wrq_wr_list(wrq->adapter, wrq); 1713 EQ_UNLOCK(eq); 1714 } 1715 1716 static void 1717 drain_wrq_wr_list(struct adapter *sc, struct sge_wrq *wrq) 1718 { 1719 struct sge_eq *eq = &wrq->eq; 1720 u_int available, dbdiff; /* # of hardware descriptors */ 1721 u_int n; 1722 struct wrqe *wr; 1723 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */ 1724 1725 EQ_LOCK_ASSERT_OWNED(eq); 1726 MPASS(TAILQ_EMPTY(&wrq->incomplete_wrs)); 1727 wr = STAILQ_FIRST(&wrq->wr_list); 1728 MPASS(wr != NULL); /* Must be called with something useful to do */ 1729 MPASS(eq->pidx == eq->dbidx); 1730 dbdiff = 0; 1731 1732 do { 1733 eq->cidx = read_hw_cidx(eq); 1734 if (eq->pidx == eq->cidx) 1735 available = eq->sidx - 1; 1736 else 1737 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 1738 1739 MPASS(wr->wrq == wrq); 1740 n = howmany(wr->wr_len, EQ_ESIZE); 1741 if (available < n) 1742 break; 1743 1744 dst = (void *)&eq->desc[eq->pidx]; 1745 if (__predict_true(eq->sidx - eq->pidx > n)) { 1746 /* Won't wrap, won't end exactly at the status page. */ 1747 bcopy(&wr->wr[0], dst, wr->wr_len); 1748 eq->pidx += n; 1749 } else { 1750 int first_portion = (eq->sidx - eq->pidx) * EQ_ESIZE; 1751 1752 bcopy(&wr->wr[0], dst, first_portion); 1753 if (wr->wr_len > first_portion) { 1754 bcopy(&wr->wr[first_portion], &eq->desc[0], 1755 wr->wr_len - first_portion); 1756 } 1757 eq->pidx = n - (eq->sidx - eq->pidx); 1758 } 1759 1760 if (available < eq->sidx / 4 && 1761 atomic_cmpset_int(&eq->equiq, 0, 1)) { 1762 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ | 1763 F_FW_WR_EQUEQ); 1764 eq->equeqidx = eq->pidx; 1765 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 32) { 1766 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ); 1767 eq->equeqidx = eq->pidx; 1768 } 1769 1770 dbdiff += n; 1771 if (dbdiff >= 16) { 1772 ring_eq_db(sc, eq, dbdiff); 1773 dbdiff = 0; 1774 } 1775 1776 STAILQ_REMOVE_HEAD(&wrq->wr_list, link); 1777 free_wrqe(wr); 1778 MPASS(wrq->nwr_pending > 0); 1779 wrq->nwr_pending--; 1780 MPASS(wrq->ndesc_needed >= n); 1781 wrq->ndesc_needed -= n; 1782 } while ((wr = STAILQ_FIRST(&wrq->wr_list)) != NULL); 1783 1784 if (dbdiff) 1785 ring_eq_db(sc, eq, dbdiff); 1786 } 1787 1788 /* 1789 * Doesn't fail. Holds on to work requests it can't send right away. 1790 */ 1791 void 1792 t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, struct wrqe *wr) 1793 { 1794 #ifdef INVARIANTS 1795 struct sge_eq *eq = &wrq->eq; 1796 #endif 1797 1798 EQ_LOCK_ASSERT_OWNED(eq); 1799 MPASS(wr != NULL); 1800 MPASS(wr->wr_len > 0 && wr->wr_len <= SGE_MAX_WR_LEN); 1801 MPASS((wr->wr_len & 0x7) == 0); 1802 1803 STAILQ_INSERT_TAIL(&wrq->wr_list, wr, link); 1804 wrq->nwr_pending++; 1805 wrq->ndesc_needed += howmany(wr->wr_len, EQ_ESIZE); 1806 1807 if (!TAILQ_EMPTY(&wrq->incomplete_wrs)) 1808 return; /* commit_wrq_wr will drain wr_list as well. */ 1809 1810 drain_wrq_wr_list(sc, wrq); 1811 1812 /* Doorbell must have caught up to the pidx. */ 1813 MPASS(eq->pidx == eq->dbidx); 1814 } 1815 1816 void 1817 t4_update_fl_bufsize(struct ifnet *ifp) 1818 { 1819 struct vi_info *vi = ifp->if_softc; 1820 struct adapter *sc = vi->pi->adapter; 1821 struct sge_rxq *rxq; 1822 #ifdef TCP_OFFLOAD 1823 struct sge_ofld_rxq *ofld_rxq; 1824 #endif 1825 struct sge_fl *fl; 1826 int i, maxp, mtu = ifp->if_mtu; 1827 1828 maxp = mtu_to_max_payload(sc, mtu, 0); 1829 for_each_rxq(vi, i, rxq) { 1830 fl = &rxq->fl; 1831 1832 FL_LOCK(fl); 1833 find_best_refill_source(sc, fl, maxp); 1834 FL_UNLOCK(fl); 1835 } 1836 #ifdef TCP_OFFLOAD 1837 maxp = mtu_to_max_payload(sc, mtu, 1); 1838 for_each_ofld_rxq(vi, i, ofld_rxq) { 1839 fl = &ofld_rxq->fl; 1840 1841 FL_LOCK(fl); 1842 find_best_refill_source(sc, fl, maxp); 1843 FL_UNLOCK(fl); 1844 } 1845 #endif 1846 } 1847 1848 static inline int 1849 mbuf_nsegs(struct mbuf *m) 1850 { 1851 1852 M_ASSERTPKTHDR(m); 1853 KASSERT(m->m_pkthdr.l5hlen > 0, 1854 ("%s: mbuf %p missing information on # of segments.", __func__, m)); 1855 1856 return (m->m_pkthdr.l5hlen); 1857 } 1858 1859 static inline void 1860 set_mbuf_nsegs(struct mbuf *m, uint8_t nsegs) 1861 { 1862 1863 M_ASSERTPKTHDR(m); 1864 m->m_pkthdr.l5hlen = nsegs; 1865 } 1866 1867 static inline int 1868 mbuf_len16(struct mbuf *m) 1869 { 1870 int n; 1871 1872 M_ASSERTPKTHDR(m); 1873 n = m->m_pkthdr.PH_loc.eight[0]; 1874 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16); 1875 1876 return (n); 1877 } 1878 1879 static inline void 1880 set_mbuf_len16(struct mbuf *m, uint8_t len16) 1881 { 1882 1883 M_ASSERTPKTHDR(m); 1884 m->m_pkthdr.PH_loc.eight[0] = len16; 1885 } 1886 1887 static inline int 1888 needs_tso(struct mbuf *m) 1889 { 1890 1891 M_ASSERTPKTHDR(m); 1892 1893 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 1894 KASSERT(m->m_pkthdr.tso_segsz > 0, 1895 ("%s: TSO requested in mbuf %p but MSS not provided", 1896 __func__, m)); 1897 return (1); 1898 } 1899 1900 return (0); 1901 } 1902 1903 static inline int 1904 needs_l3_csum(struct mbuf *m) 1905 { 1906 1907 M_ASSERTPKTHDR(m); 1908 1909 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TSO)) 1910 return (1); 1911 return (0); 1912 } 1913 1914 static inline int 1915 needs_l4_csum(struct mbuf *m) 1916 { 1917 1918 M_ASSERTPKTHDR(m); 1919 1920 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_UDP_IPV6 | 1921 CSUM_TCP_IPV6 | CSUM_TSO)) 1922 return (1); 1923 return (0); 1924 } 1925 1926 static inline int 1927 needs_vlan_insertion(struct mbuf *m) 1928 { 1929 1930 M_ASSERTPKTHDR(m); 1931 1932 if (m->m_flags & M_VLANTAG) { 1933 KASSERT(m->m_pkthdr.ether_vtag != 0, 1934 ("%s: HWVLAN requested in mbuf %p but tag not provided", 1935 __func__, m)); 1936 return (1); 1937 } 1938 return (0); 1939 } 1940 1941 static void * 1942 m_advance(struct mbuf **pm, int *poffset, int len) 1943 { 1944 struct mbuf *m = *pm; 1945 int offset = *poffset; 1946 uintptr_t p = 0; 1947 1948 MPASS(len > 0); 1949 1950 while (len) { 1951 if (offset + len < m->m_len) { 1952 offset += len; 1953 p = mtod(m, uintptr_t) + offset; 1954 break; 1955 } 1956 len -= m->m_len - offset; 1957 m = m->m_next; 1958 offset = 0; 1959 MPASS(m != NULL); 1960 } 1961 *poffset = offset; 1962 *pm = m; 1963 return ((void *)p); 1964 } 1965 1966 static inline int 1967 same_paddr(char *a, char *b) 1968 { 1969 1970 if (a == b) 1971 return (1); 1972 else if (a != NULL && b != NULL) { 1973 vm_offset_t x = (vm_offset_t)a; 1974 vm_offset_t y = (vm_offset_t)b; 1975 1976 if ((x & PAGE_MASK) == (y & PAGE_MASK) && 1977 pmap_kextract(x) == pmap_kextract(y)) 1978 return (1); 1979 } 1980 1981 return (0); 1982 } 1983 1984 /* 1985 * Can deal with empty mbufs in the chain that have m_len = 0, but the chain 1986 * must have at least one mbuf that's not empty. 1987 */ 1988 static inline int 1989 count_mbuf_nsegs(struct mbuf *m) 1990 { 1991 char *prev_end, *start; 1992 int len, nsegs; 1993 1994 MPASS(m != NULL); 1995 1996 nsegs = 0; 1997 prev_end = NULL; 1998 for (; m; m = m->m_next) { 1999 2000 len = m->m_len; 2001 if (__predict_false(len == 0)) 2002 continue; 2003 start = mtod(m, char *); 2004 2005 nsegs += sglist_count(start, len); 2006 if (same_paddr(prev_end, start)) 2007 nsegs--; 2008 prev_end = start + len; 2009 } 2010 2011 MPASS(nsegs > 0); 2012 return (nsegs); 2013 } 2014 2015 /* 2016 * Analyze the mbuf to determine its tx needs. The mbuf passed in may change: 2017 * a) caller can assume it's been freed if this function returns with an error. 2018 * b) it may get defragged up if the gather list is too long for the hardware. 2019 */ 2020 int 2021 parse_pkt(struct mbuf **mp) 2022 { 2023 struct mbuf *m0 = *mp, *m; 2024 int rc, nsegs, defragged = 0, offset; 2025 struct ether_header *eh; 2026 void *l3hdr; 2027 #if defined(INET) || defined(INET6) 2028 struct tcphdr *tcp; 2029 #endif 2030 uint16_t eh_type; 2031 2032 M_ASSERTPKTHDR(m0); 2033 if (__predict_false(m0->m_pkthdr.len < ETHER_HDR_LEN)) { 2034 rc = EINVAL; 2035 fail: 2036 m_freem(m0); 2037 *mp = NULL; 2038 return (rc); 2039 } 2040 restart: 2041 /* 2042 * First count the number of gather list segments in the payload. 2043 * Defrag the mbuf if nsegs exceeds the hardware limit. 2044 */ 2045 M_ASSERTPKTHDR(m0); 2046 MPASS(m0->m_pkthdr.len > 0); 2047 nsegs = count_mbuf_nsegs(m0); 2048 if (nsegs > (needs_tso(m0) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS)) { 2049 if (defragged++ > 0 || (m = m_defrag(m0, M_NOWAIT)) == NULL) { 2050 rc = EFBIG; 2051 goto fail; 2052 } 2053 *mp = m0 = m; /* update caller's copy after defrag */ 2054 goto restart; 2055 } 2056 2057 if (__predict_false(nsegs > 2 && m0->m_pkthdr.len <= MHLEN)) { 2058 m0 = m_pullup(m0, m0->m_pkthdr.len); 2059 if (m0 == NULL) { 2060 /* Should have left well enough alone. */ 2061 rc = EFBIG; 2062 goto fail; 2063 } 2064 *mp = m0; /* update caller's copy after pullup */ 2065 goto restart; 2066 } 2067 set_mbuf_nsegs(m0, nsegs); 2068 set_mbuf_len16(m0, txpkt_len16(nsegs, needs_tso(m0))); 2069 2070 if (!needs_tso(m0)) 2071 return (0); 2072 2073 m = m0; 2074 eh = mtod(m, struct ether_header *); 2075 eh_type = ntohs(eh->ether_type); 2076 if (eh_type == ETHERTYPE_VLAN) { 2077 struct ether_vlan_header *evh = (void *)eh; 2078 2079 eh_type = ntohs(evh->evl_proto); 2080 m0->m_pkthdr.l2hlen = sizeof(*evh); 2081 } else 2082 m0->m_pkthdr.l2hlen = sizeof(*eh); 2083 2084 offset = 0; 2085 l3hdr = m_advance(&m, &offset, m0->m_pkthdr.l2hlen); 2086 2087 switch (eh_type) { 2088 #ifdef INET6 2089 case ETHERTYPE_IPV6: 2090 { 2091 struct ip6_hdr *ip6 = l3hdr; 2092 2093 MPASS(ip6->ip6_nxt == IPPROTO_TCP); 2094 2095 m0->m_pkthdr.l3hlen = sizeof(*ip6); 2096 break; 2097 } 2098 #endif 2099 #ifdef INET 2100 case ETHERTYPE_IP: 2101 { 2102 struct ip *ip = l3hdr; 2103 2104 m0->m_pkthdr.l3hlen = ip->ip_hl * 4; 2105 break; 2106 } 2107 #endif 2108 default: 2109 panic("%s: ethertype 0x%04x unknown. if_cxgbe must be compiled" 2110 " with the same INET/INET6 options as the kernel.", 2111 __func__, eh_type); 2112 } 2113 2114 #if defined(INET) || defined(INET6) 2115 tcp = m_advance(&m, &offset, m0->m_pkthdr.l3hlen); 2116 m0->m_pkthdr.l4hlen = tcp->th_off * 4; 2117 #endif 2118 MPASS(m0 == *mp); 2119 return (0); 2120 } 2121 2122 void * 2123 start_wrq_wr(struct sge_wrq *wrq, int len16, struct wrq_cookie *cookie) 2124 { 2125 struct sge_eq *eq = &wrq->eq; 2126 struct adapter *sc = wrq->adapter; 2127 int ndesc, available; 2128 struct wrqe *wr; 2129 void *w; 2130 2131 MPASS(len16 > 0); 2132 ndesc = howmany(len16, EQ_ESIZE / 16); 2133 MPASS(ndesc > 0 && ndesc <= SGE_MAX_WR_NDESC); 2134 2135 EQ_LOCK(eq); 2136 2137 if (!STAILQ_EMPTY(&wrq->wr_list)) 2138 drain_wrq_wr_list(sc, wrq); 2139 2140 if (!STAILQ_EMPTY(&wrq->wr_list)) { 2141 slowpath: 2142 EQ_UNLOCK(eq); 2143 wr = alloc_wrqe(len16 * 16, wrq); 2144 if (__predict_false(wr == NULL)) 2145 return (NULL); 2146 cookie->pidx = -1; 2147 cookie->ndesc = ndesc; 2148 return (&wr->wr); 2149 } 2150 2151 eq->cidx = read_hw_cidx(eq); 2152 if (eq->pidx == eq->cidx) 2153 available = eq->sidx - 1; 2154 else 2155 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2156 if (available < ndesc) 2157 goto slowpath; 2158 2159 cookie->pidx = eq->pidx; 2160 cookie->ndesc = ndesc; 2161 TAILQ_INSERT_TAIL(&wrq->incomplete_wrs, cookie, link); 2162 2163 w = &eq->desc[eq->pidx]; 2164 IDXINCR(eq->pidx, ndesc, eq->sidx); 2165 if (__predict_false(eq->pidx < ndesc - 1)) { 2166 w = &wrq->ss[0]; 2167 wrq->ss_pidx = cookie->pidx; 2168 wrq->ss_len = len16 * 16; 2169 } 2170 2171 EQ_UNLOCK(eq); 2172 2173 return (w); 2174 } 2175 2176 void 2177 commit_wrq_wr(struct sge_wrq *wrq, void *w, struct wrq_cookie *cookie) 2178 { 2179 struct sge_eq *eq = &wrq->eq; 2180 struct adapter *sc = wrq->adapter; 2181 int ndesc, pidx; 2182 struct wrq_cookie *prev, *next; 2183 2184 if (cookie->pidx == -1) { 2185 struct wrqe *wr = __containerof(w, struct wrqe, wr); 2186 2187 t4_wrq_tx(sc, wr); 2188 return; 2189 } 2190 2191 ndesc = cookie->ndesc; /* Can be more than SGE_MAX_WR_NDESC here. */ 2192 pidx = cookie->pidx; 2193 MPASS(pidx >= 0 && pidx < eq->sidx); 2194 if (__predict_false(w == &wrq->ss[0])) { 2195 int n = (eq->sidx - wrq->ss_pidx) * EQ_ESIZE; 2196 2197 MPASS(wrq->ss_len > n); /* WR had better wrap around. */ 2198 bcopy(&wrq->ss[0], &eq->desc[wrq->ss_pidx], n); 2199 bcopy(&wrq->ss[n], &eq->desc[0], wrq->ss_len - n); 2200 wrq->tx_wrs_ss++; 2201 } else 2202 wrq->tx_wrs_direct++; 2203 2204 EQ_LOCK(eq); 2205 prev = TAILQ_PREV(cookie, wrq_incomplete_wrs, link); 2206 next = TAILQ_NEXT(cookie, link); 2207 if (prev == NULL) { 2208 MPASS(pidx == eq->dbidx); 2209 if (next == NULL || ndesc >= 16) 2210 ring_eq_db(wrq->adapter, eq, ndesc); 2211 else { 2212 MPASS(IDXDIFF(next->pidx, pidx, eq->sidx) == ndesc); 2213 next->pidx = pidx; 2214 next->ndesc += ndesc; 2215 } 2216 } else { 2217 MPASS(IDXDIFF(pidx, prev->pidx, eq->sidx) == prev->ndesc); 2218 prev->ndesc += ndesc; 2219 } 2220 TAILQ_REMOVE(&wrq->incomplete_wrs, cookie, link); 2221 2222 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 2223 drain_wrq_wr_list(sc, wrq); 2224 2225 #ifdef INVARIANTS 2226 if (TAILQ_EMPTY(&wrq->incomplete_wrs)) { 2227 /* Doorbell must have caught up to the pidx. */ 2228 MPASS(wrq->eq.pidx == wrq->eq.dbidx); 2229 } 2230 #endif 2231 EQ_UNLOCK(eq); 2232 } 2233 2234 static u_int 2235 can_resume_eth_tx(struct mp_ring *r) 2236 { 2237 struct sge_eq *eq = r->cookie; 2238 2239 return (total_available_tx_desc(eq) > eq->sidx / 8); 2240 } 2241 2242 static inline int 2243 cannot_use_txpkts(struct mbuf *m) 2244 { 2245 /* maybe put a GL limit too, to avoid silliness? */ 2246 2247 return (needs_tso(m)); 2248 } 2249 2250 /* 2251 * r->items[cidx] to r->items[pidx], with a wraparound at r->size, are ready to 2252 * be consumed. Return the actual number consumed. 0 indicates a stall. 2253 */ 2254 static u_int 2255 eth_tx(struct mp_ring *r, u_int cidx, u_int pidx) 2256 { 2257 struct sge_txq *txq = r->cookie; 2258 struct sge_eq *eq = &txq->eq; 2259 struct ifnet *ifp = txq->ifp; 2260 struct vi_info *vi = ifp->if_softc; 2261 struct port_info *pi = vi->pi; 2262 struct adapter *sc = pi->adapter; 2263 u_int total, remaining; /* # of packets */ 2264 u_int available, dbdiff; /* # of hardware descriptors */ 2265 u_int n, next_cidx; 2266 struct mbuf *m0, *tail; 2267 struct txpkts txp; 2268 struct fw_eth_tx_pkts_wr *wr; /* any fw WR struct will do */ 2269 2270 remaining = IDXDIFF(pidx, cidx, r->size); 2271 MPASS(remaining > 0); /* Must not be called without work to do. */ 2272 total = 0; 2273 2274 TXQ_LOCK(txq); 2275 if (__predict_false((eq->flags & EQ_ENABLED) == 0)) { 2276 while (cidx != pidx) { 2277 m0 = r->items[cidx]; 2278 m_freem(m0); 2279 if (++cidx == r->size) 2280 cidx = 0; 2281 } 2282 reclaim_tx_descs(txq, 2048); 2283 total = remaining; 2284 goto done; 2285 } 2286 2287 /* How many hardware descriptors do we have readily available. */ 2288 if (eq->pidx == eq->cidx) 2289 available = eq->sidx - 1; 2290 else 2291 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2292 dbdiff = IDXDIFF(eq->pidx, eq->dbidx, eq->sidx); 2293 2294 while (remaining > 0) { 2295 2296 m0 = r->items[cidx]; 2297 M_ASSERTPKTHDR(m0); 2298 MPASS(m0->m_nextpkt == NULL); 2299 2300 if (available < SGE_MAX_WR_NDESC) { 2301 available += reclaim_tx_descs(txq, 64); 2302 if (available < howmany(mbuf_len16(m0), EQ_ESIZE / 16)) 2303 break; /* out of descriptors */ 2304 } 2305 2306 next_cidx = cidx + 1; 2307 if (__predict_false(next_cidx == r->size)) 2308 next_cidx = 0; 2309 2310 wr = (void *)&eq->desc[eq->pidx]; 2311 if (remaining > 1 && 2312 try_txpkts(m0, r->items[next_cidx], &txp, available) == 0) { 2313 2314 /* pkts at cidx, next_cidx should both be in txp. */ 2315 MPASS(txp.npkt == 2); 2316 tail = r->items[next_cidx]; 2317 MPASS(tail->m_nextpkt == NULL); 2318 ETHER_BPF_MTAP(ifp, m0); 2319 ETHER_BPF_MTAP(ifp, tail); 2320 m0->m_nextpkt = tail; 2321 2322 if (__predict_false(++next_cidx == r->size)) 2323 next_cidx = 0; 2324 2325 while (next_cidx != pidx) { 2326 if (add_to_txpkts(r->items[next_cidx], &txp, 2327 available) != 0) 2328 break; 2329 tail->m_nextpkt = r->items[next_cidx]; 2330 tail = tail->m_nextpkt; 2331 ETHER_BPF_MTAP(ifp, tail); 2332 if (__predict_false(++next_cidx == r->size)) 2333 next_cidx = 0; 2334 } 2335 2336 n = write_txpkts_wr(txq, wr, m0, &txp, available); 2337 total += txp.npkt; 2338 remaining -= txp.npkt; 2339 } else { 2340 total++; 2341 remaining--; 2342 ETHER_BPF_MTAP(ifp, m0); 2343 n = write_txpkt_wr(txq, (void *)wr, m0, available); 2344 } 2345 MPASS(n >= 1 && n <= available && n <= SGE_MAX_WR_NDESC); 2346 2347 available -= n; 2348 dbdiff += n; 2349 IDXINCR(eq->pidx, n, eq->sidx); 2350 2351 if (total_available_tx_desc(eq) < eq->sidx / 4 && 2352 atomic_cmpset_int(&eq->equiq, 0, 1)) { 2353 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ | 2354 F_FW_WR_EQUEQ); 2355 eq->equeqidx = eq->pidx; 2356 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 32) { 2357 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ); 2358 eq->equeqidx = eq->pidx; 2359 } 2360 2361 if (dbdiff >= 16 && remaining >= 4) { 2362 ring_eq_db(sc, eq, dbdiff); 2363 available += reclaim_tx_descs(txq, 4 * dbdiff); 2364 dbdiff = 0; 2365 } 2366 2367 cidx = next_cidx; 2368 } 2369 if (dbdiff != 0) { 2370 ring_eq_db(sc, eq, dbdiff); 2371 reclaim_tx_descs(txq, 32); 2372 } 2373 done: 2374 TXQ_UNLOCK(txq); 2375 2376 return (total); 2377 } 2378 2379 static inline void 2380 init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int pktc_idx, 2381 int qsize) 2382 { 2383 2384 KASSERT(tmr_idx >= 0 && tmr_idx < SGE_NTIMERS, 2385 ("%s: bad tmr_idx %d", __func__, tmr_idx)); 2386 KASSERT(pktc_idx < SGE_NCOUNTERS, /* -ve is ok, means don't use */ 2387 ("%s: bad pktc_idx %d", __func__, pktc_idx)); 2388 2389 iq->flags = 0; 2390 iq->adapter = sc; 2391 iq->intr_params = V_QINTR_TIMER_IDX(tmr_idx); 2392 iq->intr_pktc_idx = SGE_NCOUNTERS - 1; 2393 if (pktc_idx >= 0) { 2394 iq->intr_params |= F_QINTR_CNT_EN; 2395 iq->intr_pktc_idx = pktc_idx; 2396 } 2397 iq->qsize = roundup2(qsize, 16); /* See FW_IQ_CMD/iqsize */ 2398 iq->sidx = iq->qsize - sc->params.sge.spg_len / IQ_ESIZE; 2399 } 2400 2401 static inline void 2402 init_fl(struct adapter *sc, struct sge_fl *fl, int qsize, int maxp, char *name) 2403 { 2404 2405 fl->qsize = qsize; 2406 fl->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE; 2407 strlcpy(fl->lockname, name, sizeof(fl->lockname)); 2408 if (sc->flags & BUF_PACKING_OK && 2409 ((!is_t4(sc) && buffer_packing) || /* T5+: enabled unless 0 */ 2410 (is_t4(sc) && buffer_packing == 1)))/* T4: disabled unless 1 */ 2411 fl->flags |= FL_BUF_PACKING; 2412 find_best_refill_source(sc, fl, maxp); 2413 find_safe_refill_source(sc, fl); 2414 } 2415 2416 static inline void 2417 init_eq(struct adapter *sc, struct sge_eq *eq, int eqtype, int qsize, 2418 uint8_t tx_chan, uint16_t iqid, char *name) 2419 { 2420 KASSERT(eqtype <= EQ_TYPEMASK, ("%s: bad qtype %d", __func__, eqtype)); 2421 2422 eq->flags = eqtype & EQ_TYPEMASK; 2423 eq->tx_chan = tx_chan; 2424 eq->iqid = iqid; 2425 eq->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE; 2426 strlcpy(eq->lockname, name, sizeof(eq->lockname)); 2427 } 2428 2429 static int 2430 alloc_ring(struct adapter *sc, size_t len, bus_dma_tag_t *tag, 2431 bus_dmamap_t *map, bus_addr_t *pa, void **va) 2432 { 2433 int rc; 2434 2435 rc = bus_dma_tag_create(sc->dmat, 512, 0, BUS_SPACE_MAXADDR, 2436 BUS_SPACE_MAXADDR, NULL, NULL, len, 1, len, 0, NULL, NULL, tag); 2437 if (rc != 0) { 2438 device_printf(sc->dev, "cannot allocate DMA tag: %d\n", rc); 2439 goto done; 2440 } 2441 2442 rc = bus_dmamem_alloc(*tag, va, 2443 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, map); 2444 if (rc != 0) { 2445 device_printf(sc->dev, "cannot allocate DMA memory: %d\n", rc); 2446 goto done; 2447 } 2448 2449 rc = bus_dmamap_load(*tag, *map, *va, len, oneseg_dma_callback, pa, 0); 2450 if (rc != 0) { 2451 device_printf(sc->dev, "cannot load DMA map: %d\n", rc); 2452 goto done; 2453 } 2454 done: 2455 if (rc) 2456 free_ring(sc, *tag, *map, *pa, *va); 2457 2458 return (rc); 2459 } 2460 2461 static int 2462 free_ring(struct adapter *sc, bus_dma_tag_t tag, bus_dmamap_t map, 2463 bus_addr_t pa, void *va) 2464 { 2465 if (pa) 2466 bus_dmamap_unload(tag, map); 2467 if (va) 2468 bus_dmamem_free(tag, va, map); 2469 if (tag) 2470 bus_dma_tag_destroy(tag); 2471 2472 return (0); 2473 } 2474 2475 /* 2476 * Allocates the ring for an ingress queue and an optional freelist. If the 2477 * freelist is specified it will be allocated and then associated with the 2478 * ingress queue. 2479 * 2480 * Returns errno on failure. Resources allocated up to that point may still be 2481 * allocated. Caller is responsible for cleanup in case this function fails. 2482 * 2483 * If the ingress queue will take interrupts directly (iq->flags & IQ_INTR) then 2484 * the intr_idx specifies the vector, starting from 0. Otherwise it specifies 2485 * the abs_id of the ingress queue to which its interrupts should be forwarded. 2486 */ 2487 static int 2488 alloc_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl, 2489 int intr_idx, int cong) 2490 { 2491 int rc, i, cntxt_id; 2492 size_t len; 2493 struct fw_iq_cmd c; 2494 struct port_info *pi = vi->pi; 2495 struct adapter *sc = iq->adapter; 2496 struct sge_params *sp = &sc->params.sge; 2497 __be32 v = 0; 2498 2499 len = iq->qsize * IQ_ESIZE; 2500 rc = alloc_ring(sc, len, &iq->desc_tag, &iq->desc_map, &iq->ba, 2501 (void **)&iq->desc); 2502 if (rc != 0) 2503 return (rc); 2504 2505 bzero(&c, sizeof(c)); 2506 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 2507 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) | 2508 V_FW_IQ_CMD_VFN(0)); 2509 2510 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART | 2511 FW_LEN16(c)); 2512 2513 /* Special handling for firmware event queue */ 2514 if (iq == &sc->sge.fwq) 2515 v |= F_FW_IQ_CMD_IQASYNCH; 2516 2517 if (iq->flags & IQ_INTR) { 2518 KASSERT(intr_idx < sc->intr_count, 2519 ("%s: invalid direct intr_idx %d", __func__, intr_idx)); 2520 } else 2521 v |= F_FW_IQ_CMD_IQANDST; 2522 v |= V_FW_IQ_CMD_IQANDSTINDEX(intr_idx); 2523 2524 c.type_to_iqandstindex = htobe32(v | 2525 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) | 2526 V_FW_IQ_CMD_VIID(vi->viid) | 2527 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT)); 2528 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->tx_chan) | 2529 F_FW_IQ_CMD_IQGTSMODE | 2530 V_FW_IQ_CMD_IQINTCNTTHRESH(iq->intr_pktc_idx) | 2531 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4)); 2532 c.iqsize = htobe16(iq->qsize); 2533 c.iqaddr = htobe64(iq->ba); 2534 if (cong >= 0) 2535 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN); 2536 2537 if (fl) { 2538 mtx_init(&fl->fl_lock, fl->lockname, NULL, MTX_DEF); 2539 2540 len = fl->qsize * EQ_ESIZE; 2541 rc = alloc_ring(sc, len, &fl->desc_tag, &fl->desc_map, 2542 &fl->ba, (void **)&fl->desc); 2543 if (rc) 2544 return (rc); 2545 2546 /* Allocate space for one software descriptor per buffer. */ 2547 rc = alloc_fl_sdesc(fl); 2548 if (rc != 0) { 2549 device_printf(sc->dev, 2550 "failed to setup fl software descriptors: %d\n", 2551 rc); 2552 return (rc); 2553 } 2554 2555 if (fl->flags & FL_BUF_PACKING) { 2556 fl->lowat = roundup2(sp->fl_starve_threshold2, 8); 2557 fl->buf_boundary = sp->pack_boundary; 2558 } else { 2559 fl->lowat = roundup2(sp->fl_starve_threshold, 8); 2560 fl->buf_boundary = 16; 2561 } 2562 if (fl_pad && fl->buf_boundary < sp->pad_boundary) 2563 fl->buf_boundary = sp->pad_boundary; 2564 2565 c.iqns_to_fl0congen |= 2566 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) | 2567 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO | 2568 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) | 2569 (fl->flags & FL_BUF_PACKING ? F_FW_IQ_CMD_FL0PACKEN : 2570 0)); 2571 if (cong >= 0) { 2572 c.iqns_to_fl0congen |= 2573 htobe32(V_FW_IQ_CMD_FL0CNGCHMAP(cong) | 2574 F_FW_IQ_CMD_FL0CONGCIF | 2575 F_FW_IQ_CMD_FL0CONGEN); 2576 } 2577 c.fl0dcaen_to_fl0cidxfthresh = 2578 htobe16(V_FW_IQ_CMD_FL0FBMIN(X_FETCHBURSTMIN_128B) | 2579 V_FW_IQ_CMD_FL0FBMAX(X_FETCHBURSTMAX_512B)); 2580 c.fl0size = htobe16(fl->qsize); 2581 c.fl0addr = htobe64(fl->ba); 2582 } 2583 2584 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 2585 if (rc != 0) { 2586 device_printf(sc->dev, 2587 "failed to create ingress queue: %d\n", rc); 2588 return (rc); 2589 } 2590 2591 iq->cidx = 0; 2592 iq->gen = F_RSPD_GEN; 2593 iq->intr_next = iq->intr_params; 2594 iq->cntxt_id = be16toh(c.iqid); 2595 iq->abs_id = be16toh(c.physiqid); 2596 iq->flags |= IQ_ALLOCATED; 2597 2598 cntxt_id = iq->cntxt_id - sc->sge.iq_start; 2599 if (cntxt_id >= sc->sge.niq) { 2600 panic ("%s: iq->cntxt_id (%d) more than the max (%d)", __func__, 2601 cntxt_id, sc->sge.niq - 1); 2602 } 2603 sc->sge.iqmap[cntxt_id] = iq; 2604 2605 if (fl) { 2606 u_int qid; 2607 2608 iq->flags |= IQ_HAS_FL; 2609 fl->cntxt_id = be16toh(c.fl0id); 2610 fl->pidx = fl->cidx = 0; 2611 2612 cntxt_id = fl->cntxt_id - sc->sge.eq_start; 2613 if (cntxt_id >= sc->sge.neq) { 2614 panic("%s: fl->cntxt_id (%d) more than the max (%d)", 2615 __func__, cntxt_id, sc->sge.neq - 1); 2616 } 2617 sc->sge.eqmap[cntxt_id] = (void *)fl; 2618 2619 qid = fl->cntxt_id; 2620 if (isset(&sc->doorbells, DOORBELL_UDB)) { 2621 uint32_t s_qpp = sc->params.sge.eq_s_qpp; 2622 uint32_t mask = (1 << s_qpp) - 1; 2623 volatile uint8_t *udb; 2624 2625 udb = sc->udbs_base + UDBS_DB_OFFSET; 2626 udb += (qid >> s_qpp) << PAGE_SHIFT; 2627 qid &= mask; 2628 if (qid < PAGE_SIZE / UDBS_SEG_SIZE) { 2629 udb += qid << UDBS_SEG_SHIFT; 2630 qid = 0; 2631 } 2632 fl->udb = (volatile void *)udb; 2633 } 2634 fl->dbval = V_QID(qid) | sc->chip_params->sge_fl_db; 2635 2636 FL_LOCK(fl); 2637 /* Enough to make sure the SGE doesn't think it's starved */ 2638 refill_fl(sc, fl, fl->lowat); 2639 FL_UNLOCK(fl); 2640 } 2641 2642 if (is_t5(sc) && cong >= 0) { 2643 uint32_t param, val; 2644 2645 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 2646 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) | 2647 V_FW_PARAMS_PARAM_YZ(iq->cntxt_id); 2648 if (cong == 0) 2649 val = 1 << 19; 2650 else { 2651 val = 2 << 19; 2652 for (i = 0; i < 4; i++) { 2653 if (cong & (1 << i)) 2654 val |= 1 << (i << 2); 2655 } 2656 } 2657 2658 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 2659 if (rc != 0) { 2660 /* report error but carry on */ 2661 device_printf(sc->dev, 2662 "failed to set congestion manager context for " 2663 "ingress queue %d: %d\n", iq->cntxt_id, rc); 2664 } 2665 } 2666 2667 /* Enable IQ interrupts */ 2668 atomic_store_rel_int(&iq->state, IQS_IDLE); 2669 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), V_SEINTARM(iq->intr_params) | 2670 V_INGRESSQID(iq->cntxt_id)); 2671 2672 return (0); 2673 } 2674 2675 static int 2676 free_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl) 2677 { 2678 int rc; 2679 struct adapter *sc = iq->adapter; 2680 device_t dev; 2681 2682 if (sc == NULL) 2683 return (0); /* nothing to do */ 2684 2685 dev = vi ? vi->dev : sc->dev; 2686 2687 if (iq->flags & IQ_ALLOCATED) { 2688 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0, 2689 FW_IQ_TYPE_FL_INT_CAP, iq->cntxt_id, 2690 fl ? fl->cntxt_id : 0xffff, 0xffff); 2691 if (rc != 0) { 2692 device_printf(dev, 2693 "failed to free queue %p: %d\n", iq, rc); 2694 return (rc); 2695 } 2696 iq->flags &= ~IQ_ALLOCATED; 2697 } 2698 2699 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, iq->desc); 2700 2701 bzero(iq, sizeof(*iq)); 2702 2703 if (fl) { 2704 free_ring(sc, fl->desc_tag, fl->desc_map, fl->ba, 2705 fl->desc); 2706 2707 if (fl->sdesc) 2708 free_fl_sdesc(sc, fl); 2709 2710 if (mtx_initialized(&fl->fl_lock)) 2711 mtx_destroy(&fl->fl_lock); 2712 2713 bzero(fl, sizeof(*fl)); 2714 } 2715 2716 return (0); 2717 } 2718 2719 static void 2720 add_fl_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid, 2721 struct sge_fl *fl) 2722 { 2723 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 2724 2725 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL, 2726 "freelist"); 2727 children = SYSCTL_CHILDREN(oid); 2728 2729 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 2730 CTLTYPE_INT | CTLFLAG_RD, &fl->cntxt_id, 0, sysctl_uint16, "I", 2731 "SGE context id of the freelist"); 2732 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "padding", CTLFLAG_RD, NULL, 2733 fl_pad ? 1 : 0, "padding enabled"); 2734 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "packing", CTLFLAG_RD, NULL, 2735 fl->flags & FL_BUF_PACKING ? 1 : 0, "packing enabled"); 2736 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &fl->cidx, 2737 0, "consumer index"); 2738 if (fl->flags & FL_BUF_PACKING) { 2739 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rx_offset", 2740 CTLFLAG_RD, &fl->rx_offset, 0, "packing rx offset"); 2741 } 2742 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &fl->pidx, 2743 0, "producer index"); 2744 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_allocated", 2745 CTLFLAG_RD, &fl->mbuf_allocated, "# of mbuf allocated"); 2746 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_inlined", 2747 CTLFLAG_RD, &fl->mbuf_inlined, "# of mbuf inlined in clusters"); 2748 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_allocated", 2749 CTLFLAG_RD, &fl->cl_allocated, "# of clusters allocated"); 2750 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_recycled", 2751 CTLFLAG_RD, &fl->cl_recycled, "# of clusters recycled"); 2752 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_fast_recycled", 2753 CTLFLAG_RD, &fl->cl_fast_recycled, "# of clusters recycled (fast)"); 2754 } 2755 2756 static int 2757 alloc_fwq(struct adapter *sc) 2758 { 2759 int rc, intr_idx; 2760 struct sge_iq *fwq = &sc->sge.fwq; 2761 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev); 2762 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 2763 2764 init_iq(fwq, sc, 0, 0, FW_IQ_QSIZE); 2765 fwq->flags |= IQ_INTR; /* always */ 2766 intr_idx = sc->intr_count > 1 ? 1 : 0; 2767 rc = alloc_iq_fl(&sc->port[0]->vi[0], fwq, NULL, intr_idx, -1); 2768 if (rc != 0) { 2769 device_printf(sc->dev, 2770 "failed to create firmware event queue: %d\n", rc); 2771 return (rc); 2772 } 2773 2774 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "fwq", CTLFLAG_RD, 2775 NULL, "firmware event queue"); 2776 children = SYSCTL_CHILDREN(oid); 2777 2778 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "abs_id", 2779 CTLTYPE_INT | CTLFLAG_RD, &fwq->abs_id, 0, sysctl_uint16, "I", 2780 "absolute id of the queue"); 2781 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "cntxt_id", 2782 CTLTYPE_INT | CTLFLAG_RD, &fwq->cntxt_id, 0, sysctl_uint16, "I", 2783 "SGE context id of the queue"); 2784 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "cidx", 2785 CTLTYPE_INT | CTLFLAG_RD, &fwq->cidx, 0, sysctl_uint16, "I", 2786 "consumer index"); 2787 2788 return (0); 2789 } 2790 2791 static int 2792 free_fwq(struct adapter *sc) 2793 { 2794 return free_iq_fl(NULL, &sc->sge.fwq, NULL); 2795 } 2796 2797 static int 2798 alloc_mgmtq(struct adapter *sc) 2799 { 2800 int rc; 2801 struct sge_wrq *mgmtq = &sc->sge.mgmtq; 2802 char name[16]; 2803 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev); 2804 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 2805 2806 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "mgmtq", CTLFLAG_RD, 2807 NULL, "management queue"); 2808 2809 snprintf(name, sizeof(name), "%s mgmtq", device_get_nameunit(sc->dev)); 2810 init_eq(sc, &mgmtq->eq, EQ_CTRL, CTRL_EQ_QSIZE, sc->port[0]->tx_chan, 2811 sc->sge.fwq.cntxt_id, name); 2812 rc = alloc_wrq(sc, NULL, mgmtq, oid); 2813 if (rc != 0) { 2814 device_printf(sc->dev, 2815 "failed to create management queue: %d\n", rc); 2816 return (rc); 2817 } 2818 2819 return (0); 2820 } 2821 2822 static int 2823 free_mgmtq(struct adapter *sc) 2824 { 2825 2826 return free_wrq(sc, &sc->sge.mgmtq); 2827 } 2828 2829 int 2830 tnl_cong(struct port_info *pi, int drop) 2831 { 2832 2833 if (drop == -1) 2834 return (-1); 2835 else if (drop == 1) 2836 return (0); 2837 else 2838 return (pi->rx_chan_map); 2839 } 2840 2841 static int 2842 alloc_rxq(struct vi_info *vi, struct sge_rxq *rxq, int intr_idx, int idx, 2843 struct sysctl_oid *oid) 2844 { 2845 int rc; 2846 struct sysctl_oid_list *children; 2847 char name[16]; 2848 2849 rc = alloc_iq_fl(vi, &rxq->iq, &rxq->fl, intr_idx, 2850 tnl_cong(vi->pi, cong_drop)); 2851 if (rc != 0) 2852 return (rc); 2853 2854 /* 2855 * The freelist is just barely above the starvation threshold right now, 2856 * fill it up a bit more. 2857 */ 2858 FL_LOCK(&rxq->fl); 2859 refill_fl(vi->pi->adapter, &rxq->fl, 128); 2860 FL_UNLOCK(&rxq->fl); 2861 2862 #if defined(INET) || defined(INET6) 2863 rc = tcp_lro_init(&rxq->lro); 2864 if (rc != 0) 2865 return (rc); 2866 rxq->lro.ifp = vi->ifp; /* also indicates LRO init'ed */ 2867 2868 if (vi->ifp->if_capenable & IFCAP_LRO) 2869 rxq->iq.flags |= IQ_LRO_ENABLED; 2870 #endif 2871 rxq->ifp = vi->ifp; 2872 2873 children = SYSCTL_CHILDREN(oid); 2874 2875 snprintf(name, sizeof(name), "%d", idx); 2876 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 2877 NULL, "rx queue"); 2878 children = SYSCTL_CHILDREN(oid); 2879 2880 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "abs_id", 2881 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.abs_id, 0, sysctl_uint16, "I", 2882 "absolute id of the queue"); 2883 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cntxt_id", 2884 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.cntxt_id, 0, sysctl_uint16, "I", 2885 "SGE context id of the queue"); 2886 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx", 2887 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.cidx, 0, sysctl_uint16, "I", 2888 "consumer index"); 2889 #if defined(INET) || defined(INET6) 2890 SYSCTL_ADD_U64(&vi->ctx, children, OID_AUTO, "lro_queued", CTLFLAG_RD, 2891 &rxq->lro.lro_queued, 0, NULL); 2892 SYSCTL_ADD_U64(&vi->ctx, children, OID_AUTO, "lro_flushed", CTLFLAG_RD, 2893 &rxq->lro.lro_flushed, 0, NULL); 2894 #endif 2895 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "rxcsum", CTLFLAG_RD, 2896 &rxq->rxcsum, "# of times hardware assisted with checksum"); 2897 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_extraction", 2898 CTLFLAG_RD, &rxq->vlan_extraction, 2899 "# of times hardware extracted 802.1Q tag"); 2900 2901 add_fl_sysctls(&vi->ctx, oid, &rxq->fl); 2902 2903 return (rc); 2904 } 2905 2906 static int 2907 free_rxq(struct vi_info *vi, struct sge_rxq *rxq) 2908 { 2909 int rc; 2910 2911 #if defined(INET) || defined(INET6) 2912 if (rxq->lro.ifp) { 2913 tcp_lro_free(&rxq->lro); 2914 rxq->lro.ifp = NULL; 2915 } 2916 #endif 2917 2918 rc = free_iq_fl(vi, &rxq->iq, &rxq->fl); 2919 if (rc == 0) 2920 bzero(rxq, sizeof(*rxq)); 2921 2922 return (rc); 2923 } 2924 2925 #ifdef TCP_OFFLOAD 2926 static int 2927 alloc_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq, 2928 int intr_idx, int idx, struct sysctl_oid *oid) 2929 { 2930 int rc; 2931 struct sysctl_oid_list *children; 2932 char name[16]; 2933 2934 rc = alloc_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl, intr_idx, 2935 vi->pi->rx_chan_map); 2936 if (rc != 0) 2937 return (rc); 2938 2939 children = SYSCTL_CHILDREN(oid); 2940 2941 snprintf(name, sizeof(name), "%d", idx); 2942 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 2943 NULL, "rx queue"); 2944 children = SYSCTL_CHILDREN(oid); 2945 2946 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "abs_id", 2947 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.abs_id, 0, sysctl_uint16, 2948 "I", "absolute id of the queue"); 2949 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cntxt_id", 2950 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.cntxt_id, 0, sysctl_uint16, 2951 "I", "SGE context id of the queue"); 2952 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx", 2953 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.cidx, 0, sysctl_uint16, "I", 2954 "consumer index"); 2955 2956 add_fl_sysctls(&vi->ctx, oid, &ofld_rxq->fl); 2957 2958 return (rc); 2959 } 2960 2961 static int 2962 free_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq) 2963 { 2964 int rc; 2965 2966 rc = free_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl); 2967 if (rc == 0) 2968 bzero(ofld_rxq, sizeof(*ofld_rxq)); 2969 2970 return (rc); 2971 } 2972 #endif 2973 2974 #ifdef DEV_NETMAP 2975 static int 2976 alloc_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq, int intr_idx, 2977 int idx, struct sysctl_oid *oid) 2978 { 2979 int rc; 2980 struct sysctl_oid_list *children; 2981 struct sysctl_ctx_list *ctx; 2982 char name[16]; 2983 size_t len; 2984 struct adapter *sc = vi->pi->adapter; 2985 struct netmap_adapter *na = NA(vi->ifp); 2986 2987 MPASS(na != NULL); 2988 2989 len = vi->qsize_rxq * IQ_ESIZE; 2990 rc = alloc_ring(sc, len, &nm_rxq->iq_desc_tag, &nm_rxq->iq_desc_map, 2991 &nm_rxq->iq_ba, (void **)&nm_rxq->iq_desc); 2992 if (rc != 0) 2993 return (rc); 2994 2995 len = na->num_rx_desc * EQ_ESIZE + sc->params.sge.spg_len; 2996 rc = alloc_ring(sc, len, &nm_rxq->fl_desc_tag, &nm_rxq->fl_desc_map, 2997 &nm_rxq->fl_ba, (void **)&nm_rxq->fl_desc); 2998 if (rc != 0) 2999 return (rc); 3000 3001 nm_rxq->vi = vi; 3002 nm_rxq->nid = idx; 3003 nm_rxq->iq_cidx = 0; 3004 nm_rxq->iq_sidx = vi->qsize_rxq - sc->params.sge.spg_len / IQ_ESIZE; 3005 nm_rxq->iq_gen = F_RSPD_GEN; 3006 nm_rxq->fl_pidx = nm_rxq->fl_cidx = 0; 3007 nm_rxq->fl_sidx = na->num_rx_desc; 3008 nm_rxq->intr_idx = intr_idx; 3009 3010 ctx = &vi->ctx; 3011 children = SYSCTL_CHILDREN(oid); 3012 3013 snprintf(name, sizeof(name), "%d", idx); 3014 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, name, CTLFLAG_RD, NULL, 3015 "rx queue"); 3016 children = SYSCTL_CHILDREN(oid); 3017 3018 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "abs_id", 3019 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_abs_id, 0, sysctl_uint16, 3020 "I", "absolute id of the queue"); 3021 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 3022 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cntxt_id, 0, sysctl_uint16, 3023 "I", "SGE context id of the queue"); 3024 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx", 3025 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cidx, 0, sysctl_uint16, "I", 3026 "consumer index"); 3027 3028 children = SYSCTL_CHILDREN(oid); 3029 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL, 3030 "freelist"); 3031 children = SYSCTL_CHILDREN(oid); 3032 3033 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 3034 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->fl_cntxt_id, 0, sysctl_uint16, 3035 "I", "SGE context id of the freelist"); 3036 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, 3037 &nm_rxq->fl_cidx, 0, "consumer index"); 3038 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, 3039 &nm_rxq->fl_pidx, 0, "producer index"); 3040 3041 return (rc); 3042 } 3043 3044 3045 static int 3046 free_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq) 3047 { 3048 struct adapter *sc = vi->pi->adapter; 3049 3050 free_ring(sc, nm_rxq->iq_desc_tag, nm_rxq->iq_desc_map, nm_rxq->iq_ba, 3051 nm_rxq->iq_desc); 3052 free_ring(sc, nm_rxq->fl_desc_tag, nm_rxq->fl_desc_map, nm_rxq->fl_ba, 3053 nm_rxq->fl_desc); 3054 3055 return (0); 3056 } 3057 3058 static int 3059 alloc_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq, int iqidx, int idx, 3060 struct sysctl_oid *oid) 3061 { 3062 int rc; 3063 size_t len; 3064 struct port_info *pi = vi->pi; 3065 struct adapter *sc = pi->adapter; 3066 struct netmap_adapter *na = NA(vi->ifp); 3067 char name[16]; 3068 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3069 3070 len = na->num_tx_desc * EQ_ESIZE + sc->params.sge.spg_len; 3071 rc = alloc_ring(sc, len, &nm_txq->desc_tag, &nm_txq->desc_map, 3072 &nm_txq->ba, (void **)&nm_txq->desc); 3073 if (rc) 3074 return (rc); 3075 3076 nm_txq->pidx = nm_txq->cidx = 0; 3077 nm_txq->sidx = na->num_tx_desc; 3078 nm_txq->nid = idx; 3079 nm_txq->iqidx = iqidx; 3080 nm_txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) | 3081 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_VF_VLD(1) | 3082 V_TXPKT_VF(vi->viid)); 3083 3084 snprintf(name, sizeof(name), "%d", idx); 3085 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 3086 NULL, "netmap tx queue"); 3087 children = SYSCTL_CHILDREN(oid); 3088 3089 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 3090 &nm_txq->cntxt_id, 0, "SGE context id of the queue"); 3091 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx", 3092 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->cidx, 0, sysctl_uint16, "I", 3093 "consumer index"); 3094 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "pidx", 3095 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->pidx, 0, sysctl_uint16, "I", 3096 "producer index"); 3097 3098 return (rc); 3099 } 3100 3101 static int 3102 free_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq) 3103 { 3104 struct adapter *sc = vi->pi->adapter; 3105 3106 free_ring(sc, nm_txq->desc_tag, nm_txq->desc_map, nm_txq->ba, 3107 nm_txq->desc); 3108 3109 return (0); 3110 } 3111 #endif 3112 3113 static int 3114 ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq) 3115 { 3116 int rc, cntxt_id; 3117 struct fw_eq_ctrl_cmd c; 3118 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 3119 3120 bzero(&c, sizeof(c)); 3121 3122 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | F_FW_CMD_REQUEST | 3123 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_CTRL_CMD_PFN(sc->pf) | 3124 V_FW_EQ_CTRL_CMD_VFN(0)); 3125 c.alloc_to_len16 = htobe32(F_FW_EQ_CTRL_CMD_ALLOC | 3126 F_FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c)); 3127 c.cmpliqid_eqid = htonl(V_FW_EQ_CTRL_CMD_CMPLIQID(eq->iqid)); 3128 c.physeqid_pkd = htobe32(0); 3129 c.fetchszm_to_iqid = 3130 htobe32(V_FW_EQ_CTRL_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) | 3131 V_FW_EQ_CTRL_CMD_PCIECHN(eq->tx_chan) | 3132 F_FW_EQ_CTRL_CMD_FETCHRO | V_FW_EQ_CTRL_CMD_IQID(eq->iqid)); 3133 c.dcaen_to_eqsize = 3134 htobe32(V_FW_EQ_CTRL_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 3135 V_FW_EQ_CTRL_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 3136 V_FW_EQ_CTRL_CMD_EQSIZE(qsize)); 3137 c.eqaddr = htobe64(eq->ba); 3138 3139 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3140 if (rc != 0) { 3141 device_printf(sc->dev, 3142 "failed to create control queue %d: %d\n", eq->tx_chan, rc); 3143 return (rc); 3144 } 3145 eq->flags |= EQ_ALLOCATED; 3146 3147 eq->cntxt_id = G_FW_EQ_CTRL_CMD_EQID(be32toh(c.cmpliqid_eqid)); 3148 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 3149 if (cntxt_id >= sc->sge.neq) 3150 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 3151 cntxt_id, sc->sge.neq - 1); 3152 sc->sge.eqmap[cntxt_id] = eq; 3153 3154 return (rc); 3155 } 3156 3157 static int 3158 eth_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 3159 { 3160 int rc, cntxt_id; 3161 struct fw_eq_eth_cmd c; 3162 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 3163 3164 bzero(&c, sizeof(c)); 3165 3166 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST | 3167 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) | 3168 V_FW_EQ_ETH_CMD_VFN(0)); 3169 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC | 3170 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c)); 3171 c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE | 3172 F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(vi->viid)); 3173 c.fetchszm_to_iqid = 3174 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) | 3175 V_FW_EQ_ETH_CMD_PCIECHN(eq->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO | 3176 V_FW_EQ_ETH_CMD_IQID(eq->iqid)); 3177 c.dcaen_to_eqsize = htobe32(V_FW_EQ_ETH_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 3178 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 3179 V_FW_EQ_ETH_CMD_EQSIZE(qsize)); 3180 c.eqaddr = htobe64(eq->ba); 3181 3182 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3183 if (rc != 0) { 3184 device_printf(vi->dev, 3185 "failed to create Ethernet egress queue: %d\n", rc); 3186 return (rc); 3187 } 3188 eq->flags |= EQ_ALLOCATED; 3189 3190 eq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd)); 3191 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 3192 if (cntxt_id >= sc->sge.neq) 3193 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 3194 cntxt_id, sc->sge.neq - 1); 3195 sc->sge.eqmap[cntxt_id] = eq; 3196 3197 return (rc); 3198 } 3199 3200 #ifdef TCP_OFFLOAD 3201 static int 3202 ofld_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 3203 { 3204 int rc, cntxt_id; 3205 struct fw_eq_ofld_cmd c; 3206 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 3207 3208 bzero(&c, sizeof(c)); 3209 3210 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | F_FW_CMD_REQUEST | 3211 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_OFLD_CMD_PFN(sc->pf) | 3212 V_FW_EQ_OFLD_CMD_VFN(0)); 3213 c.alloc_to_len16 = htonl(F_FW_EQ_OFLD_CMD_ALLOC | 3214 F_FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c)); 3215 c.fetchszm_to_iqid = 3216 htonl(V_FW_EQ_OFLD_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) | 3217 V_FW_EQ_OFLD_CMD_PCIECHN(eq->tx_chan) | 3218 F_FW_EQ_OFLD_CMD_FETCHRO | V_FW_EQ_OFLD_CMD_IQID(eq->iqid)); 3219 c.dcaen_to_eqsize = 3220 htobe32(V_FW_EQ_OFLD_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 3221 V_FW_EQ_OFLD_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 3222 V_FW_EQ_OFLD_CMD_EQSIZE(qsize)); 3223 c.eqaddr = htobe64(eq->ba); 3224 3225 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3226 if (rc != 0) { 3227 device_printf(vi->dev, 3228 "failed to create egress queue for TCP offload: %d\n", rc); 3229 return (rc); 3230 } 3231 eq->flags |= EQ_ALLOCATED; 3232 3233 eq->cntxt_id = G_FW_EQ_OFLD_CMD_EQID(be32toh(c.eqid_pkd)); 3234 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 3235 if (cntxt_id >= sc->sge.neq) 3236 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 3237 cntxt_id, sc->sge.neq - 1); 3238 sc->sge.eqmap[cntxt_id] = eq; 3239 3240 return (rc); 3241 } 3242 #endif 3243 3244 static int 3245 alloc_eq(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 3246 { 3247 int rc, qsize; 3248 size_t len; 3249 3250 mtx_init(&eq->eq_lock, eq->lockname, NULL, MTX_DEF); 3251 3252 qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 3253 len = qsize * EQ_ESIZE; 3254 rc = alloc_ring(sc, len, &eq->desc_tag, &eq->desc_map, 3255 &eq->ba, (void **)&eq->desc); 3256 if (rc) 3257 return (rc); 3258 3259 eq->pidx = eq->cidx = 0; 3260 eq->equeqidx = eq->dbidx = 0; 3261 eq->doorbells = sc->doorbells; 3262 3263 switch (eq->flags & EQ_TYPEMASK) { 3264 case EQ_CTRL: 3265 rc = ctrl_eq_alloc(sc, eq); 3266 break; 3267 3268 case EQ_ETH: 3269 rc = eth_eq_alloc(sc, vi, eq); 3270 break; 3271 3272 #ifdef TCP_OFFLOAD 3273 case EQ_OFLD: 3274 rc = ofld_eq_alloc(sc, vi, eq); 3275 break; 3276 #endif 3277 3278 default: 3279 panic("%s: invalid eq type %d.", __func__, 3280 eq->flags & EQ_TYPEMASK); 3281 } 3282 if (rc != 0) { 3283 device_printf(sc->dev, 3284 "failed to allocate egress queue(%d): %d\n", 3285 eq->flags & EQ_TYPEMASK, rc); 3286 } 3287 3288 if (isset(&eq->doorbells, DOORBELL_UDB) || 3289 isset(&eq->doorbells, DOORBELL_UDBWC) || 3290 isset(&eq->doorbells, DOORBELL_WCWR)) { 3291 uint32_t s_qpp = sc->params.sge.eq_s_qpp; 3292 uint32_t mask = (1 << s_qpp) - 1; 3293 volatile uint8_t *udb; 3294 3295 udb = sc->udbs_base + UDBS_DB_OFFSET; 3296 udb += (eq->cntxt_id >> s_qpp) << PAGE_SHIFT; /* pg offset */ 3297 eq->udb_qid = eq->cntxt_id & mask; /* id in page */ 3298 if (eq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE) 3299 clrbit(&eq->doorbells, DOORBELL_WCWR); 3300 else { 3301 udb += eq->udb_qid << UDBS_SEG_SHIFT; /* seg offset */ 3302 eq->udb_qid = 0; 3303 } 3304 eq->udb = (volatile void *)udb; 3305 } 3306 3307 return (rc); 3308 } 3309 3310 static int 3311 free_eq(struct adapter *sc, struct sge_eq *eq) 3312 { 3313 int rc; 3314 3315 if (eq->flags & EQ_ALLOCATED) { 3316 switch (eq->flags & EQ_TYPEMASK) { 3317 case EQ_CTRL: 3318 rc = -t4_ctrl_eq_free(sc, sc->mbox, sc->pf, 0, 3319 eq->cntxt_id); 3320 break; 3321 3322 case EQ_ETH: 3323 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0, 3324 eq->cntxt_id); 3325 break; 3326 3327 #ifdef TCP_OFFLOAD 3328 case EQ_OFLD: 3329 rc = -t4_ofld_eq_free(sc, sc->mbox, sc->pf, 0, 3330 eq->cntxt_id); 3331 break; 3332 #endif 3333 3334 default: 3335 panic("%s: invalid eq type %d.", __func__, 3336 eq->flags & EQ_TYPEMASK); 3337 } 3338 if (rc != 0) { 3339 device_printf(sc->dev, 3340 "failed to free egress queue (%d): %d\n", 3341 eq->flags & EQ_TYPEMASK, rc); 3342 return (rc); 3343 } 3344 eq->flags &= ~EQ_ALLOCATED; 3345 } 3346 3347 free_ring(sc, eq->desc_tag, eq->desc_map, eq->ba, eq->desc); 3348 3349 if (mtx_initialized(&eq->eq_lock)) 3350 mtx_destroy(&eq->eq_lock); 3351 3352 bzero(eq, sizeof(*eq)); 3353 return (0); 3354 } 3355 3356 static int 3357 alloc_wrq(struct adapter *sc, struct vi_info *vi, struct sge_wrq *wrq, 3358 struct sysctl_oid *oid) 3359 { 3360 int rc; 3361 struct sysctl_ctx_list *ctx = vi ? &vi->ctx : &sc->ctx; 3362 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3363 3364 rc = alloc_eq(sc, vi, &wrq->eq); 3365 if (rc) 3366 return (rc); 3367 3368 wrq->adapter = sc; 3369 TASK_INIT(&wrq->wrq_tx_task, 0, wrq_tx_drain, wrq); 3370 TAILQ_INIT(&wrq->incomplete_wrs); 3371 STAILQ_INIT(&wrq->wr_list); 3372 wrq->nwr_pending = 0; 3373 wrq->ndesc_needed = 0; 3374 3375 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 3376 &wrq->eq.cntxt_id, 0, "SGE context id of the queue"); 3377 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx", 3378 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.cidx, 0, sysctl_uint16, "I", 3379 "consumer index"); 3380 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pidx", 3381 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.pidx, 0, sysctl_uint16, "I", 3382 "producer index"); 3383 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_direct", CTLFLAG_RD, 3384 &wrq->tx_wrs_direct, "# of work requests (direct)"); 3385 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_copied", CTLFLAG_RD, 3386 &wrq->tx_wrs_copied, "# of work requests (copied)"); 3387 3388 return (rc); 3389 } 3390 3391 static int 3392 free_wrq(struct adapter *sc, struct sge_wrq *wrq) 3393 { 3394 int rc; 3395 3396 rc = free_eq(sc, &wrq->eq); 3397 if (rc) 3398 return (rc); 3399 3400 bzero(wrq, sizeof(*wrq)); 3401 return (0); 3402 } 3403 3404 static int 3405 alloc_txq(struct vi_info *vi, struct sge_txq *txq, int idx, 3406 struct sysctl_oid *oid) 3407 { 3408 int rc; 3409 struct port_info *pi = vi->pi; 3410 struct adapter *sc = pi->adapter; 3411 struct sge_eq *eq = &txq->eq; 3412 char name[16]; 3413 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3414 3415 rc = mp_ring_alloc(&txq->r, eq->sidx, txq, eth_tx, can_resume_eth_tx, 3416 M_CXGBE, M_WAITOK); 3417 if (rc != 0) { 3418 device_printf(sc->dev, "failed to allocate mp_ring: %d\n", rc); 3419 return (rc); 3420 } 3421 3422 rc = alloc_eq(sc, vi, eq); 3423 if (rc != 0) { 3424 mp_ring_free(txq->r); 3425 txq->r = NULL; 3426 return (rc); 3427 } 3428 3429 /* Can't fail after this point. */ 3430 3431 TASK_INIT(&txq->tx_reclaim_task, 0, tx_reclaim, eq); 3432 txq->ifp = vi->ifp; 3433 txq->gl = sglist_alloc(TX_SGL_SEGS, M_WAITOK); 3434 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) | 3435 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_VF_VLD(1) | 3436 V_TXPKT_VF(vi->viid)); 3437 txq->sdesc = malloc(eq->sidx * sizeof(struct tx_sdesc), M_CXGBE, 3438 M_ZERO | M_WAITOK); 3439 3440 snprintf(name, sizeof(name), "%d", idx); 3441 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 3442 NULL, "tx queue"); 3443 children = SYSCTL_CHILDREN(oid); 3444 3445 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 3446 &eq->cntxt_id, 0, "SGE context id of the queue"); 3447 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx", 3448 CTLTYPE_INT | CTLFLAG_RD, &eq->cidx, 0, sysctl_uint16, "I", 3449 "consumer index"); 3450 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "pidx", 3451 CTLTYPE_INT | CTLFLAG_RD, &eq->pidx, 0, sysctl_uint16, "I", 3452 "producer index"); 3453 3454 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txcsum", CTLFLAG_RD, 3455 &txq->txcsum, "# of times hardware assisted with checksum"); 3456 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_insertion", 3457 CTLFLAG_RD, &txq->vlan_insertion, 3458 "# of times hardware inserted 802.1Q tag"); 3459 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "tso_wrs", CTLFLAG_RD, 3460 &txq->tso_wrs, "# of TSO work requests"); 3461 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "imm_wrs", CTLFLAG_RD, 3462 &txq->imm_wrs, "# of work requests with immediate data"); 3463 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "sgl_wrs", CTLFLAG_RD, 3464 &txq->sgl_wrs, "# of work requests with direct SGL"); 3465 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkt_wrs", CTLFLAG_RD, 3466 &txq->txpkt_wrs, "# of txpkt work requests (one pkt/WR)"); 3467 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_wrs", 3468 CTLFLAG_RD, &txq->txpkts0_wrs, 3469 "# of txpkts (type 0) work requests"); 3470 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_wrs", 3471 CTLFLAG_RD, &txq->txpkts1_wrs, 3472 "# of txpkts (type 1) work requests"); 3473 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_pkts", 3474 CTLFLAG_RD, &txq->txpkts0_pkts, 3475 "# of frames tx'd using type0 txpkts work requests"); 3476 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_pkts", 3477 CTLFLAG_RD, &txq->txpkts1_pkts, 3478 "# of frames tx'd using type1 txpkts work requests"); 3479 3480 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_enqueues", 3481 CTLFLAG_RD, &txq->r->enqueues, 3482 "# of enqueues to the mp_ring for this queue"); 3483 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_drops", 3484 CTLFLAG_RD, &txq->r->drops, 3485 "# of drops in the mp_ring for this queue"); 3486 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_starts", 3487 CTLFLAG_RD, &txq->r->starts, 3488 "# of normal consumer starts in the mp_ring for this queue"); 3489 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_stalls", 3490 CTLFLAG_RD, &txq->r->stalls, 3491 "# of consumer stalls in the mp_ring for this queue"); 3492 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_restarts", 3493 CTLFLAG_RD, &txq->r->restarts, 3494 "# of consumer restarts in the mp_ring for this queue"); 3495 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_abdications", 3496 CTLFLAG_RD, &txq->r->abdications, 3497 "# of consumer abdications in the mp_ring for this queue"); 3498 3499 return (0); 3500 } 3501 3502 static int 3503 free_txq(struct vi_info *vi, struct sge_txq *txq) 3504 { 3505 int rc; 3506 struct adapter *sc = vi->pi->adapter; 3507 struct sge_eq *eq = &txq->eq; 3508 3509 rc = free_eq(sc, eq); 3510 if (rc) 3511 return (rc); 3512 3513 sglist_free(txq->gl); 3514 free(txq->sdesc, M_CXGBE); 3515 mp_ring_free(txq->r); 3516 3517 bzero(txq, sizeof(*txq)); 3518 return (0); 3519 } 3520 3521 static void 3522 oneseg_dma_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3523 { 3524 bus_addr_t *ba = arg; 3525 3526 KASSERT(nseg == 1, 3527 ("%s meant for single segment mappings only.", __func__)); 3528 3529 *ba = error ? 0 : segs->ds_addr; 3530 } 3531 3532 static inline void 3533 ring_fl_db(struct adapter *sc, struct sge_fl *fl) 3534 { 3535 uint32_t n, v; 3536 3537 n = IDXDIFF(fl->pidx / 8, fl->dbidx, fl->sidx); 3538 MPASS(n > 0); 3539 3540 wmb(); 3541 v = fl->dbval | V_PIDX(n); 3542 if (fl->udb) 3543 *fl->udb = htole32(v); 3544 else 3545 t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL), v); 3546 IDXINCR(fl->dbidx, n, fl->sidx); 3547 } 3548 3549 /* 3550 * Fills up the freelist by allocating upto 'n' buffers. Buffers that are 3551 * recycled do not count towards this allocation budget. 3552 * 3553 * Returns non-zero to indicate that this freelist should be added to the list 3554 * of starving freelists. 3555 */ 3556 static int 3557 refill_fl(struct adapter *sc, struct sge_fl *fl, int n) 3558 { 3559 __be64 *d; 3560 struct fl_sdesc *sd; 3561 uintptr_t pa; 3562 caddr_t cl; 3563 struct cluster_layout *cll; 3564 struct sw_zone_info *swz; 3565 struct cluster_metadata *clm; 3566 uint16_t max_pidx; 3567 uint16_t hw_cidx = fl->hw_cidx; /* stable snapshot */ 3568 3569 FL_LOCK_ASSERT_OWNED(fl); 3570 3571 /* 3572 * We always stop at the begining of the hardware descriptor that's just 3573 * before the one with the hw cidx. This is to avoid hw pidx = hw cidx, 3574 * which would mean an empty freelist to the chip. 3575 */ 3576 max_pidx = __predict_false(hw_cidx == 0) ? fl->sidx - 1 : hw_cidx - 1; 3577 if (fl->pidx == max_pidx * 8) 3578 return (0); 3579 3580 d = &fl->desc[fl->pidx]; 3581 sd = &fl->sdesc[fl->pidx]; 3582 cll = &fl->cll_def; /* default layout */ 3583 swz = &sc->sge.sw_zone_info[cll->zidx]; 3584 3585 while (n > 0) { 3586 3587 if (sd->cl != NULL) { 3588 3589 if (sd->nmbuf == 0) { 3590 /* 3591 * Fast recycle without involving any atomics on 3592 * the cluster's metadata (if the cluster has 3593 * metadata). This happens when all frames 3594 * received in the cluster were small enough to 3595 * fit within a single mbuf each. 3596 */ 3597 fl->cl_fast_recycled++; 3598 #ifdef INVARIANTS 3599 clm = cl_metadata(sc, fl, &sd->cll, sd->cl); 3600 if (clm != NULL) 3601 MPASS(clm->refcount == 1); 3602 #endif 3603 goto recycled_fast; 3604 } 3605 3606 /* 3607 * Cluster is guaranteed to have metadata. Clusters 3608 * without metadata always take the fast recycle path 3609 * when they're recycled. 3610 */ 3611 clm = cl_metadata(sc, fl, &sd->cll, sd->cl); 3612 MPASS(clm != NULL); 3613 3614 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) { 3615 fl->cl_recycled++; 3616 counter_u64_add(extfree_rels, 1); 3617 goto recycled; 3618 } 3619 sd->cl = NULL; /* gave up my reference */ 3620 } 3621 MPASS(sd->cl == NULL); 3622 alloc: 3623 cl = uma_zalloc(swz->zone, M_NOWAIT); 3624 if (__predict_false(cl == NULL)) { 3625 if (cll == &fl->cll_alt || fl->cll_alt.zidx == -1 || 3626 fl->cll_def.zidx == fl->cll_alt.zidx) 3627 break; 3628 3629 /* fall back to the safe zone */ 3630 cll = &fl->cll_alt; 3631 swz = &sc->sge.sw_zone_info[cll->zidx]; 3632 goto alloc; 3633 } 3634 fl->cl_allocated++; 3635 n--; 3636 3637 pa = pmap_kextract((vm_offset_t)cl); 3638 pa += cll->region1; 3639 sd->cl = cl; 3640 sd->cll = *cll; 3641 *d = htobe64(pa | cll->hwidx); 3642 clm = cl_metadata(sc, fl, cll, cl); 3643 if (clm != NULL) { 3644 recycled: 3645 #ifdef INVARIANTS 3646 clm->sd = sd; 3647 #endif 3648 clm->refcount = 1; 3649 } 3650 sd->nmbuf = 0; 3651 recycled_fast: 3652 d++; 3653 sd++; 3654 if (__predict_false(++fl->pidx % 8 == 0)) { 3655 uint16_t pidx = fl->pidx / 8; 3656 3657 if (__predict_false(pidx == fl->sidx)) { 3658 fl->pidx = 0; 3659 pidx = 0; 3660 sd = fl->sdesc; 3661 d = fl->desc; 3662 } 3663 if (pidx == max_pidx) 3664 break; 3665 3666 if (IDXDIFF(pidx, fl->dbidx, fl->sidx) >= 4) 3667 ring_fl_db(sc, fl); 3668 } 3669 } 3670 3671 if (fl->pidx / 8 != fl->dbidx) 3672 ring_fl_db(sc, fl); 3673 3674 return (FL_RUNNING_LOW(fl) && !(fl->flags & FL_STARVING)); 3675 } 3676 3677 /* 3678 * Attempt to refill all starving freelists. 3679 */ 3680 static void 3681 refill_sfl(void *arg) 3682 { 3683 struct adapter *sc = arg; 3684 struct sge_fl *fl, *fl_temp; 3685 3686 mtx_assert(&sc->sfl_lock, MA_OWNED); 3687 TAILQ_FOREACH_SAFE(fl, &sc->sfl, link, fl_temp) { 3688 FL_LOCK(fl); 3689 refill_fl(sc, fl, 64); 3690 if (FL_NOT_RUNNING_LOW(fl) || fl->flags & FL_DOOMED) { 3691 TAILQ_REMOVE(&sc->sfl, fl, link); 3692 fl->flags &= ~FL_STARVING; 3693 } 3694 FL_UNLOCK(fl); 3695 } 3696 3697 if (!TAILQ_EMPTY(&sc->sfl)) 3698 callout_schedule(&sc->sfl_callout, hz / 5); 3699 } 3700 3701 static int 3702 alloc_fl_sdesc(struct sge_fl *fl) 3703 { 3704 3705 fl->sdesc = malloc(fl->sidx * 8 * sizeof(struct fl_sdesc), M_CXGBE, 3706 M_ZERO | M_WAITOK); 3707 3708 return (0); 3709 } 3710 3711 static void 3712 free_fl_sdesc(struct adapter *sc, struct sge_fl *fl) 3713 { 3714 struct fl_sdesc *sd; 3715 struct cluster_metadata *clm; 3716 struct cluster_layout *cll; 3717 int i; 3718 3719 sd = fl->sdesc; 3720 for (i = 0; i < fl->sidx * 8; i++, sd++) { 3721 if (sd->cl == NULL) 3722 continue; 3723 3724 cll = &sd->cll; 3725 clm = cl_metadata(sc, fl, cll, sd->cl); 3726 if (sd->nmbuf == 0) 3727 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl); 3728 else if (clm && atomic_fetchadd_int(&clm->refcount, -1) == 1) { 3729 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl); 3730 counter_u64_add(extfree_rels, 1); 3731 } 3732 sd->cl = NULL; 3733 } 3734 3735 free(fl->sdesc, M_CXGBE); 3736 fl->sdesc = NULL; 3737 } 3738 3739 static inline void 3740 get_pkt_gl(struct mbuf *m, struct sglist *gl) 3741 { 3742 int rc; 3743 3744 M_ASSERTPKTHDR(m); 3745 3746 sglist_reset(gl); 3747 rc = sglist_append_mbuf(gl, m); 3748 if (__predict_false(rc != 0)) { 3749 panic("%s: mbuf %p (%d segs) was vetted earlier but now fails " 3750 "with %d.", __func__, m, mbuf_nsegs(m), rc); 3751 } 3752 3753 KASSERT(gl->sg_nseg == mbuf_nsegs(m), 3754 ("%s: nsegs changed for mbuf %p from %d to %d", __func__, m, 3755 mbuf_nsegs(m), gl->sg_nseg)); 3756 KASSERT(gl->sg_nseg > 0 && 3757 gl->sg_nseg <= (needs_tso(m) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS), 3758 ("%s: %d segments, should have been 1 <= nsegs <= %d", __func__, 3759 gl->sg_nseg, needs_tso(m) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS)); 3760 } 3761 3762 /* 3763 * len16 for a txpkt WR with a GL. Includes the firmware work request header. 3764 */ 3765 static inline u_int 3766 txpkt_len16(u_int nsegs, u_int tso) 3767 { 3768 u_int n; 3769 3770 MPASS(nsegs > 0); 3771 3772 nsegs--; /* first segment is part of ulptx_sgl */ 3773 n = sizeof(struct fw_eth_tx_pkt_wr) + sizeof(struct cpl_tx_pkt_core) + 3774 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 3775 if (tso) 3776 n += sizeof(struct cpl_tx_pkt_lso_core); 3777 3778 return (howmany(n, 16)); 3779 } 3780 3781 /* 3782 * len16 for a txpkts type 0 WR with a GL. Does not include the firmware work 3783 * request header. 3784 */ 3785 static inline u_int 3786 txpkts0_len16(u_int nsegs) 3787 { 3788 u_int n; 3789 3790 MPASS(nsegs > 0); 3791 3792 nsegs--; /* first segment is part of ulptx_sgl */ 3793 n = sizeof(struct ulp_txpkt) + sizeof(struct ulptx_idata) + 3794 sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl) + 3795 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 3796 3797 return (howmany(n, 16)); 3798 } 3799 3800 /* 3801 * len16 for a txpkts type 1 WR with a GL. Does not include the firmware work 3802 * request header. 3803 */ 3804 static inline u_int 3805 txpkts1_len16(void) 3806 { 3807 u_int n; 3808 3809 n = sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl); 3810 3811 return (howmany(n, 16)); 3812 } 3813 3814 static inline u_int 3815 imm_payload(u_int ndesc) 3816 { 3817 u_int n; 3818 3819 n = ndesc * EQ_ESIZE - sizeof(struct fw_eth_tx_pkt_wr) - 3820 sizeof(struct cpl_tx_pkt_core); 3821 3822 return (n); 3823 } 3824 3825 /* 3826 * Write a txpkt WR for this packet to the hardware descriptors, update the 3827 * software descriptor, and advance the pidx. It is guaranteed that enough 3828 * descriptors are available. 3829 * 3830 * The return value is the # of hardware descriptors used. 3831 */ 3832 static u_int 3833 write_txpkt_wr(struct sge_txq *txq, struct fw_eth_tx_pkt_wr *wr, 3834 struct mbuf *m0, u_int available) 3835 { 3836 struct sge_eq *eq = &txq->eq; 3837 struct tx_sdesc *txsd; 3838 struct cpl_tx_pkt_core *cpl; 3839 uint32_t ctrl; /* used in many unrelated places */ 3840 uint64_t ctrl1; 3841 int len16, ndesc, pktlen, nsegs; 3842 caddr_t dst; 3843 3844 TXQ_LOCK_ASSERT_OWNED(txq); 3845 M_ASSERTPKTHDR(m0); 3846 MPASS(available > 0 && available < eq->sidx); 3847 3848 len16 = mbuf_len16(m0); 3849 nsegs = mbuf_nsegs(m0); 3850 pktlen = m0->m_pkthdr.len; 3851 ctrl = sizeof(struct cpl_tx_pkt_core); 3852 if (needs_tso(m0)) 3853 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 3854 else if (pktlen <= imm_payload(2) && available >= 2) { 3855 /* Immediate data. Recalculate len16 and set nsegs to 0. */ 3856 ctrl += pktlen; 3857 len16 = howmany(sizeof(struct fw_eth_tx_pkt_wr) + 3858 sizeof(struct cpl_tx_pkt_core) + pktlen, 16); 3859 nsegs = 0; 3860 } 3861 ndesc = howmany(len16, EQ_ESIZE / 16); 3862 MPASS(ndesc <= available); 3863 3864 /* Firmware work request header */ 3865 MPASS(wr == (void *)&eq->desc[eq->pidx]); 3866 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_WR) | 3867 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl)); 3868 3869 ctrl = V_FW_WR_LEN16(len16); 3870 wr->equiq_to_len16 = htobe32(ctrl); 3871 wr->r3 = 0; 3872 3873 if (needs_tso(m0)) { 3874 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1); 3875 3876 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 3877 m0->m_pkthdr.l4hlen > 0, 3878 ("%s: mbuf %p needs TSO but missing header lengths", 3879 __func__, m0)); 3880 3881 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE | 3882 F_LSO_LAST_SLICE | V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) 3883 | V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2); 3884 if (m0->m_pkthdr.l2hlen == sizeof(struct ether_vlan_header)) 3885 ctrl |= V_LSO_ETHHDR_LEN(1); 3886 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 3887 ctrl |= F_LSO_IPV6; 3888 3889 lso->lso_ctrl = htobe32(ctrl); 3890 lso->ipid_ofst = htobe16(0); 3891 lso->mss = htobe16(m0->m_pkthdr.tso_segsz); 3892 lso->seqno_offset = htobe32(0); 3893 lso->len = htobe32(pktlen); 3894 3895 cpl = (void *)(lso + 1); 3896 3897 txq->tso_wrs++; 3898 } else 3899 cpl = (void *)(wr + 1); 3900 3901 /* Checksum offload */ 3902 ctrl1 = 0; 3903 if (needs_l3_csum(m0) == 0) 3904 ctrl1 |= F_TXPKT_IPCSUM_DIS; 3905 if (needs_l4_csum(m0) == 0) 3906 ctrl1 |= F_TXPKT_L4CSUM_DIS; 3907 if (m0->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | 3908 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO)) 3909 txq->txcsum++; /* some hardware assistance provided */ 3910 3911 /* VLAN tag insertion */ 3912 if (needs_vlan_insertion(m0)) { 3913 ctrl1 |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 3914 txq->vlan_insertion++; 3915 } 3916 3917 /* CPL header */ 3918 cpl->ctrl0 = txq->cpl_ctrl0; 3919 cpl->pack = 0; 3920 cpl->len = htobe16(pktlen); 3921 cpl->ctrl1 = htobe64(ctrl1); 3922 3923 /* SGL */ 3924 dst = (void *)(cpl + 1); 3925 if (nsegs > 0) { 3926 3927 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx); 3928 txq->sgl_wrs++; 3929 } else { 3930 struct mbuf *m; 3931 3932 for (m = m0; m != NULL; m = m->m_next) { 3933 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len); 3934 #ifdef INVARIANTS 3935 pktlen -= m->m_len; 3936 #endif 3937 } 3938 #ifdef INVARIANTS 3939 KASSERT(pktlen == 0, ("%s: %d bytes left.", __func__, pktlen)); 3940 #endif 3941 txq->imm_wrs++; 3942 } 3943 3944 txq->txpkt_wrs++; 3945 3946 txsd = &txq->sdesc[eq->pidx]; 3947 txsd->m = m0; 3948 txsd->desc_used = ndesc; 3949 3950 return (ndesc); 3951 } 3952 3953 static int 3954 try_txpkts(struct mbuf *m, struct mbuf *n, struct txpkts *txp, u_int available) 3955 { 3956 u_int needed, nsegs1, nsegs2, l1, l2; 3957 3958 if (cannot_use_txpkts(m) || cannot_use_txpkts(n)) 3959 return (1); 3960 3961 nsegs1 = mbuf_nsegs(m); 3962 nsegs2 = mbuf_nsegs(n); 3963 if (nsegs1 + nsegs2 == 2) { 3964 txp->wr_type = 1; 3965 l1 = l2 = txpkts1_len16(); 3966 } else { 3967 txp->wr_type = 0; 3968 l1 = txpkts0_len16(nsegs1); 3969 l2 = txpkts0_len16(nsegs2); 3970 } 3971 txp->len16 = howmany(sizeof(struct fw_eth_tx_pkts_wr), 16) + l1 + l2; 3972 needed = howmany(txp->len16, EQ_ESIZE / 16); 3973 if (needed > SGE_MAX_WR_NDESC || needed > available) 3974 return (1); 3975 3976 txp->plen = m->m_pkthdr.len + n->m_pkthdr.len; 3977 if (txp->plen > 65535) 3978 return (1); 3979 3980 txp->npkt = 2; 3981 set_mbuf_len16(m, l1); 3982 set_mbuf_len16(n, l2); 3983 3984 return (0); 3985 } 3986 3987 static int 3988 add_to_txpkts(struct mbuf *m, struct txpkts *txp, u_int available) 3989 { 3990 u_int plen, len16, needed, nsegs; 3991 3992 MPASS(txp->wr_type == 0 || txp->wr_type == 1); 3993 3994 nsegs = mbuf_nsegs(m); 3995 if (needs_tso(m) || (txp->wr_type == 1 && nsegs != 1)) 3996 return (1); 3997 3998 plen = txp->plen + m->m_pkthdr.len; 3999 if (plen > 65535) 4000 return (1); 4001 4002 if (txp->wr_type == 0) 4003 len16 = txpkts0_len16(nsegs); 4004 else 4005 len16 = txpkts1_len16(); 4006 needed = howmany(txp->len16 + len16, EQ_ESIZE / 16); 4007 if (needed > SGE_MAX_WR_NDESC || needed > available) 4008 return (1); 4009 4010 txp->npkt++; 4011 txp->plen = plen; 4012 txp->len16 += len16; 4013 set_mbuf_len16(m, len16); 4014 4015 return (0); 4016 } 4017 4018 /* 4019 * Write a txpkts WR for the packets in txp to the hardware descriptors, update 4020 * the software descriptor, and advance the pidx. It is guaranteed that enough 4021 * descriptors are available. 4022 * 4023 * The return value is the # of hardware descriptors used. 4024 */ 4025 static u_int 4026 write_txpkts_wr(struct sge_txq *txq, struct fw_eth_tx_pkts_wr *wr, 4027 struct mbuf *m0, const struct txpkts *txp, u_int available) 4028 { 4029 struct sge_eq *eq = &txq->eq; 4030 struct tx_sdesc *txsd; 4031 struct cpl_tx_pkt_core *cpl; 4032 uint32_t ctrl; 4033 uint64_t ctrl1; 4034 int ndesc, checkwrap; 4035 struct mbuf *m; 4036 void *flitp; 4037 4038 TXQ_LOCK_ASSERT_OWNED(txq); 4039 MPASS(txp->npkt > 0); 4040 MPASS(txp->plen < 65536); 4041 MPASS(m0 != NULL); 4042 MPASS(m0->m_nextpkt != NULL); 4043 MPASS(txp->len16 <= howmany(SGE_MAX_WR_LEN, 16)); 4044 MPASS(available > 0 && available < eq->sidx); 4045 4046 ndesc = howmany(txp->len16, EQ_ESIZE / 16); 4047 MPASS(ndesc <= available); 4048 4049 MPASS(wr == (void *)&eq->desc[eq->pidx]); 4050 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR)); 4051 ctrl = V_FW_WR_LEN16(txp->len16); 4052 wr->equiq_to_len16 = htobe32(ctrl); 4053 wr->plen = htobe16(txp->plen); 4054 wr->npkt = txp->npkt; 4055 wr->r3 = 0; 4056 wr->type = txp->wr_type; 4057 flitp = wr + 1; 4058 4059 /* 4060 * At this point we are 16B into a hardware descriptor. If checkwrap is 4061 * set then we know the WR is going to wrap around somewhere. We'll 4062 * check for that at appropriate points. 4063 */ 4064 checkwrap = eq->sidx - ndesc < eq->pidx; 4065 for (m = m0; m != NULL; m = m->m_nextpkt) { 4066 if (txp->wr_type == 0) { 4067 struct ulp_txpkt *ulpmc; 4068 struct ulptx_idata *ulpsc; 4069 4070 /* ULP master command */ 4071 ulpmc = flitp; 4072 ulpmc->cmd_dest = htobe32(V_ULPTX_CMD(ULP_TX_PKT) | 4073 V_ULP_TXPKT_DEST(0) | V_ULP_TXPKT_FID(eq->iqid)); 4074 ulpmc->len = htobe32(mbuf_len16(m)); 4075 4076 /* ULP subcommand */ 4077 ulpsc = (void *)(ulpmc + 1); 4078 ulpsc->cmd_more = htobe32(V_ULPTX_CMD(ULP_TX_SC_IMM) | 4079 F_ULP_TX_SC_MORE); 4080 ulpsc->len = htobe32(sizeof(struct cpl_tx_pkt_core)); 4081 4082 cpl = (void *)(ulpsc + 1); 4083 if (checkwrap && 4084 (uintptr_t)cpl == (uintptr_t)&eq->desc[eq->sidx]) 4085 cpl = (void *)&eq->desc[0]; 4086 txq->txpkts0_pkts += txp->npkt; 4087 txq->txpkts0_wrs++; 4088 } else { 4089 cpl = flitp; 4090 txq->txpkts1_pkts += txp->npkt; 4091 txq->txpkts1_wrs++; 4092 } 4093 4094 /* Checksum offload */ 4095 ctrl1 = 0; 4096 if (needs_l3_csum(m) == 0) 4097 ctrl1 |= F_TXPKT_IPCSUM_DIS; 4098 if (needs_l4_csum(m) == 0) 4099 ctrl1 |= F_TXPKT_L4CSUM_DIS; 4100 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | 4101 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO)) 4102 txq->txcsum++; /* some hardware assistance provided */ 4103 4104 /* VLAN tag insertion */ 4105 if (needs_vlan_insertion(m)) { 4106 ctrl1 |= F_TXPKT_VLAN_VLD | 4107 V_TXPKT_VLAN(m->m_pkthdr.ether_vtag); 4108 txq->vlan_insertion++; 4109 } 4110 4111 /* CPL header */ 4112 cpl->ctrl0 = txq->cpl_ctrl0; 4113 cpl->pack = 0; 4114 cpl->len = htobe16(m->m_pkthdr.len); 4115 cpl->ctrl1 = htobe64(ctrl1); 4116 4117 flitp = cpl + 1; 4118 if (checkwrap && 4119 (uintptr_t)flitp == (uintptr_t)&eq->desc[eq->sidx]) 4120 flitp = (void *)&eq->desc[0]; 4121 4122 write_gl_to_txd(txq, m, (caddr_t *)(&flitp), checkwrap); 4123 4124 } 4125 4126 txsd = &txq->sdesc[eq->pidx]; 4127 txsd->m = m0; 4128 txsd->desc_used = ndesc; 4129 4130 return (ndesc); 4131 } 4132 4133 /* 4134 * If the SGL ends on an address that is not 16 byte aligned, this function will 4135 * add a 0 filled flit at the end. 4136 */ 4137 static void 4138 write_gl_to_txd(struct sge_txq *txq, struct mbuf *m, caddr_t *to, int checkwrap) 4139 { 4140 struct sge_eq *eq = &txq->eq; 4141 struct sglist *gl = txq->gl; 4142 struct sglist_seg *seg; 4143 __be64 *flitp, *wrap; 4144 struct ulptx_sgl *usgl; 4145 int i, nflits, nsegs; 4146 4147 KASSERT(((uintptr_t)(*to) & 0xf) == 0, 4148 ("%s: SGL must start at a 16 byte boundary: %p", __func__, *to)); 4149 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]); 4150 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]); 4151 4152 get_pkt_gl(m, gl); 4153 nsegs = gl->sg_nseg; 4154 MPASS(nsegs > 0); 4155 4156 nflits = (3 * (nsegs - 1)) / 2 + ((nsegs - 1) & 1) + 2; 4157 flitp = (__be64 *)(*to); 4158 wrap = (__be64 *)(&eq->desc[eq->sidx]); 4159 seg = &gl->sg_segs[0]; 4160 usgl = (void *)flitp; 4161 4162 /* 4163 * We start at a 16 byte boundary somewhere inside the tx descriptor 4164 * ring, so we're at least 16 bytes away from the status page. There is 4165 * no chance of a wrap around in the middle of usgl (which is 16 bytes). 4166 */ 4167 4168 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 4169 V_ULPTX_NSGE(nsegs)); 4170 usgl->len0 = htobe32(seg->ss_len); 4171 usgl->addr0 = htobe64(seg->ss_paddr); 4172 seg++; 4173 4174 if (checkwrap == 0 || (uintptr_t)(flitp + nflits) <= (uintptr_t)wrap) { 4175 4176 /* Won't wrap around at all */ 4177 4178 for (i = 0; i < nsegs - 1; i++, seg++) { 4179 usgl->sge[i / 2].len[i & 1] = htobe32(seg->ss_len); 4180 usgl->sge[i / 2].addr[i & 1] = htobe64(seg->ss_paddr); 4181 } 4182 if (i & 1) 4183 usgl->sge[i / 2].len[1] = htobe32(0); 4184 flitp += nflits; 4185 } else { 4186 4187 /* Will wrap somewhere in the rest of the SGL */ 4188 4189 /* 2 flits already written, write the rest flit by flit */ 4190 flitp = (void *)(usgl + 1); 4191 for (i = 0; i < nflits - 2; i++) { 4192 if (flitp == wrap) 4193 flitp = (void *)eq->desc; 4194 *flitp++ = get_flit(seg, nsegs - 1, i); 4195 } 4196 } 4197 4198 if (nflits & 1) { 4199 MPASS(((uintptr_t)flitp) & 0xf); 4200 *flitp++ = 0; 4201 } 4202 4203 MPASS((((uintptr_t)flitp) & 0xf) == 0); 4204 if (__predict_false(flitp == wrap)) 4205 *to = (void *)eq->desc; 4206 else 4207 *to = (void *)flitp; 4208 } 4209 4210 static inline void 4211 copy_to_txd(struct sge_eq *eq, caddr_t from, caddr_t *to, int len) 4212 { 4213 4214 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]); 4215 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]); 4216 4217 if (__predict_true((uintptr_t)(*to) + len <= 4218 (uintptr_t)&eq->desc[eq->sidx])) { 4219 bcopy(from, *to, len); 4220 (*to) += len; 4221 } else { 4222 int portion = (uintptr_t)&eq->desc[eq->sidx] - (uintptr_t)(*to); 4223 4224 bcopy(from, *to, portion); 4225 from += portion; 4226 portion = len - portion; /* remaining */ 4227 bcopy(from, (void *)eq->desc, portion); 4228 (*to) = (caddr_t)eq->desc + portion; 4229 } 4230 } 4231 4232 static inline void 4233 ring_eq_db(struct adapter *sc, struct sge_eq *eq, u_int n) 4234 { 4235 u_int db; 4236 4237 MPASS(n > 0); 4238 4239 db = eq->doorbells; 4240 if (n > 1) 4241 clrbit(&db, DOORBELL_WCWR); 4242 wmb(); 4243 4244 switch (ffs(db) - 1) { 4245 case DOORBELL_UDB: 4246 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n)); 4247 break; 4248 4249 case DOORBELL_WCWR: { 4250 volatile uint64_t *dst, *src; 4251 int i; 4252 4253 /* 4254 * Queues whose 128B doorbell segment fits in the page do not 4255 * use relative qid (udb_qid is always 0). Only queues with 4256 * doorbell segments can do WCWR. 4257 */ 4258 KASSERT(eq->udb_qid == 0 && n == 1, 4259 ("%s: inappropriate doorbell (0x%x, %d, %d) for eq %p", 4260 __func__, eq->doorbells, n, eq->dbidx, eq)); 4261 4262 dst = (volatile void *)((uintptr_t)eq->udb + UDBS_WR_OFFSET - 4263 UDBS_DB_OFFSET); 4264 i = eq->dbidx; 4265 src = (void *)&eq->desc[i]; 4266 while (src != (void *)&eq->desc[i + 1]) 4267 *dst++ = *src++; 4268 wmb(); 4269 break; 4270 } 4271 4272 case DOORBELL_UDBWC: 4273 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n)); 4274 wmb(); 4275 break; 4276 4277 case DOORBELL_KDB: 4278 t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL), 4279 V_QID(eq->cntxt_id) | V_PIDX(n)); 4280 break; 4281 } 4282 4283 IDXINCR(eq->dbidx, n, eq->sidx); 4284 } 4285 4286 static inline u_int 4287 reclaimable_tx_desc(struct sge_eq *eq) 4288 { 4289 uint16_t hw_cidx; 4290 4291 hw_cidx = read_hw_cidx(eq); 4292 return (IDXDIFF(hw_cidx, eq->cidx, eq->sidx)); 4293 } 4294 4295 static inline u_int 4296 total_available_tx_desc(struct sge_eq *eq) 4297 { 4298 uint16_t hw_cidx, pidx; 4299 4300 hw_cidx = read_hw_cidx(eq); 4301 pidx = eq->pidx; 4302 4303 if (pidx == hw_cidx) 4304 return (eq->sidx - 1); 4305 else 4306 return (IDXDIFF(hw_cidx, pidx, eq->sidx) - 1); 4307 } 4308 4309 static inline uint16_t 4310 read_hw_cidx(struct sge_eq *eq) 4311 { 4312 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx]; 4313 uint16_t cidx = spg->cidx; /* stable snapshot */ 4314 4315 return (be16toh(cidx)); 4316 } 4317 4318 /* 4319 * Reclaim 'n' descriptors approximately. 4320 */ 4321 static u_int 4322 reclaim_tx_descs(struct sge_txq *txq, u_int n) 4323 { 4324 struct tx_sdesc *txsd; 4325 struct sge_eq *eq = &txq->eq; 4326 u_int can_reclaim, reclaimed; 4327 4328 TXQ_LOCK_ASSERT_OWNED(txq); 4329 MPASS(n > 0); 4330 4331 reclaimed = 0; 4332 can_reclaim = reclaimable_tx_desc(eq); 4333 while (can_reclaim && reclaimed < n) { 4334 int ndesc; 4335 struct mbuf *m, *nextpkt; 4336 4337 txsd = &txq->sdesc[eq->cidx]; 4338 ndesc = txsd->desc_used; 4339 4340 /* Firmware doesn't return "partial" credits. */ 4341 KASSERT(can_reclaim >= ndesc, 4342 ("%s: unexpected number of credits: %d, %d", 4343 __func__, can_reclaim, ndesc)); 4344 4345 for (m = txsd->m; m != NULL; m = nextpkt) { 4346 nextpkt = m->m_nextpkt; 4347 m->m_nextpkt = NULL; 4348 m_freem(m); 4349 } 4350 reclaimed += ndesc; 4351 can_reclaim -= ndesc; 4352 IDXINCR(eq->cidx, ndesc, eq->sidx); 4353 } 4354 4355 return (reclaimed); 4356 } 4357 4358 static void 4359 tx_reclaim(void *arg, int n) 4360 { 4361 struct sge_txq *txq = arg; 4362 struct sge_eq *eq = &txq->eq; 4363 4364 do { 4365 if (TXQ_TRYLOCK(txq) == 0) 4366 break; 4367 n = reclaim_tx_descs(txq, 32); 4368 if (eq->cidx == eq->pidx) 4369 eq->equeqidx = eq->pidx; 4370 TXQ_UNLOCK(txq); 4371 } while (n > 0); 4372 } 4373 4374 static __be64 4375 get_flit(struct sglist_seg *segs, int nsegs, int idx) 4376 { 4377 int i = (idx / 3) * 2; 4378 4379 switch (idx % 3) { 4380 case 0: { 4381 __be64 rc; 4382 4383 rc = htobe32(segs[i].ss_len); 4384 if (i + 1 < nsegs) 4385 rc |= (uint64_t)htobe32(segs[i + 1].ss_len) << 32; 4386 4387 return (rc); 4388 } 4389 case 1: 4390 return (htobe64(segs[i].ss_paddr)); 4391 case 2: 4392 return (htobe64(segs[i + 1].ss_paddr)); 4393 } 4394 4395 return (0); 4396 } 4397 4398 static void 4399 find_best_refill_source(struct adapter *sc, struct sge_fl *fl, int maxp) 4400 { 4401 int8_t zidx, hwidx, idx; 4402 uint16_t region1, region3; 4403 int spare, spare_needed, n; 4404 struct sw_zone_info *swz; 4405 struct hw_buf_info *hwb, *hwb_list = &sc->sge.hw_buf_info[0]; 4406 4407 /* 4408 * Buffer Packing: Look for PAGE_SIZE or larger zone which has a bufsize 4409 * large enough for the max payload and cluster metadata. Otherwise 4410 * settle for the largest bufsize that leaves enough room in the cluster 4411 * for metadata. 4412 * 4413 * Without buffer packing: Look for the smallest zone which has a 4414 * bufsize large enough for the max payload. Settle for the largest 4415 * bufsize available if there's nothing big enough for max payload. 4416 */ 4417 spare_needed = fl->flags & FL_BUF_PACKING ? CL_METADATA_SIZE : 0; 4418 swz = &sc->sge.sw_zone_info[0]; 4419 hwidx = -1; 4420 for (zidx = 0; zidx < SW_ZONE_SIZES; zidx++, swz++) { 4421 if (swz->size > largest_rx_cluster) { 4422 if (__predict_true(hwidx != -1)) 4423 break; 4424 4425 /* 4426 * This is a misconfiguration. largest_rx_cluster is 4427 * preventing us from finding a refill source. See 4428 * dev.t5nex.<n>.buffer_sizes to figure out why. 4429 */ 4430 device_printf(sc->dev, "largest_rx_cluster=%u leaves no" 4431 " refill source for fl %p (dma %u). Ignored.\n", 4432 largest_rx_cluster, fl, maxp); 4433 } 4434 for (idx = swz->head_hwidx; idx != -1; idx = hwb->next) { 4435 hwb = &hwb_list[idx]; 4436 spare = swz->size - hwb->size; 4437 if (spare < spare_needed) 4438 continue; 4439 4440 hwidx = idx; /* best option so far */ 4441 if (hwb->size >= maxp) { 4442 4443 if ((fl->flags & FL_BUF_PACKING) == 0) 4444 goto done; /* stop looking (not packing) */ 4445 4446 if (swz->size >= safest_rx_cluster) 4447 goto done; /* stop looking (packing) */ 4448 } 4449 break; /* keep looking, next zone */ 4450 } 4451 } 4452 done: 4453 /* A usable hwidx has been located. */ 4454 MPASS(hwidx != -1); 4455 hwb = &hwb_list[hwidx]; 4456 zidx = hwb->zidx; 4457 swz = &sc->sge.sw_zone_info[zidx]; 4458 region1 = 0; 4459 region3 = swz->size - hwb->size; 4460 4461 /* 4462 * Stay within this zone and see if there is a better match when mbuf 4463 * inlining is allowed. Remember that the hwidx's are sorted in 4464 * decreasing order of size (so in increasing order of spare area). 4465 */ 4466 for (idx = hwidx; idx != -1; idx = hwb->next) { 4467 hwb = &hwb_list[idx]; 4468 spare = swz->size - hwb->size; 4469 4470 if (allow_mbufs_in_cluster == 0 || hwb->size < maxp) 4471 break; 4472 4473 /* 4474 * Do not inline mbufs if doing so would violate the pad/pack 4475 * boundary alignment requirement. 4476 */ 4477 if (fl_pad && (MSIZE % sc->params.sge.pad_boundary) != 0) 4478 continue; 4479 if (fl->flags & FL_BUF_PACKING && 4480 (MSIZE % sc->params.sge.pack_boundary) != 0) 4481 continue; 4482 4483 if (spare < CL_METADATA_SIZE + MSIZE) 4484 continue; 4485 n = (spare - CL_METADATA_SIZE) / MSIZE; 4486 if (n > howmany(hwb->size, maxp)) 4487 break; 4488 4489 hwidx = idx; 4490 if (fl->flags & FL_BUF_PACKING) { 4491 region1 = n * MSIZE; 4492 region3 = spare - region1; 4493 } else { 4494 region1 = MSIZE; 4495 region3 = spare - region1; 4496 break; 4497 } 4498 } 4499 4500 KASSERT(zidx >= 0 && zidx < SW_ZONE_SIZES, 4501 ("%s: bad zone %d for fl %p, maxp %d", __func__, zidx, fl, maxp)); 4502 KASSERT(hwidx >= 0 && hwidx <= SGE_FLBUF_SIZES, 4503 ("%s: bad hwidx %d for fl %p, maxp %d", __func__, hwidx, fl, maxp)); 4504 KASSERT(region1 + sc->sge.hw_buf_info[hwidx].size + region3 == 4505 sc->sge.sw_zone_info[zidx].size, 4506 ("%s: bad buffer layout for fl %p, maxp %d. " 4507 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp, 4508 sc->sge.sw_zone_info[zidx].size, region1, 4509 sc->sge.hw_buf_info[hwidx].size, region3)); 4510 if (fl->flags & FL_BUF_PACKING || region1 > 0) { 4511 KASSERT(region3 >= CL_METADATA_SIZE, 4512 ("%s: no room for metadata. fl %p, maxp %d; " 4513 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp, 4514 sc->sge.sw_zone_info[zidx].size, region1, 4515 sc->sge.hw_buf_info[hwidx].size, region3)); 4516 KASSERT(region1 % MSIZE == 0, 4517 ("%s: bad mbuf region for fl %p, maxp %d. " 4518 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp, 4519 sc->sge.sw_zone_info[zidx].size, region1, 4520 sc->sge.hw_buf_info[hwidx].size, region3)); 4521 } 4522 4523 fl->cll_def.zidx = zidx; 4524 fl->cll_def.hwidx = hwidx; 4525 fl->cll_def.region1 = region1; 4526 fl->cll_def.region3 = region3; 4527 } 4528 4529 static void 4530 find_safe_refill_source(struct adapter *sc, struct sge_fl *fl) 4531 { 4532 struct sge *s = &sc->sge; 4533 struct hw_buf_info *hwb; 4534 struct sw_zone_info *swz; 4535 int spare; 4536 int8_t hwidx; 4537 4538 if (fl->flags & FL_BUF_PACKING) 4539 hwidx = s->safe_hwidx2; /* with room for metadata */ 4540 else if (allow_mbufs_in_cluster && s->safe_hwidx2 != -1) { 4541 hwidx = s->safe_hwidx2; 4542 hwb = &s->hw_buf_info[hwidx]; 4543 swz = &s->sw_zone_info[hwb->zidx]; 4544 spare = swz->size - hwb->size; 4545 4546 /* no good if there isn't room for an mbuf as well */ 4547 if (spare < CL_METADATA_SIZE + MSIZE) 4548 hwidx = s->safe_hwidx1; 4549 } else 4550 hwidx = s->safe_hwidx1; 4551 4552 if (hwidx == -1) { 4553 /* No fallback source */ 4554 fl->cll_alt.hwidx = -1; 4555 fl->cll_alt.zidx = -1; 4556 4557 return; 4558 } 4559 4560 hwb = &s->hw_buf_info[hwidx]; 4561 swz = &s->sw_zone_info[hwb->zidx]; 4562 spare = swz->size - hwb->size; 4563 fl->cll_alt.hwidx = hwidx; 4564 fl->cll_alt.zidx = hwb->zidx; 4565 if (allow_mbufs_in_cluster && 4566 (fl_pad == 0 || (MSIZE % sc->params.sge.pad_boundary) == 0)) 4567 fl->cll_alt.region1 = ((spare - CL_METADATA_SIZE) / MSIZE) * MSIZE; 4568 else 4569 fl->cll_alt.region1 = 0; 4570 fl->cll_alt.region3 = spare - fl->cll_alt.region1; 4571 } 4572 4573 static void 4574 add_fl_to_sfl(struct adapter *sc, struct sge_fl *fl) 4575 { 4576 mtx_lock(&sc->sfl_lock); 4577 FL_LOCK(fl); 4578 if ((fl->flags & FL_DOOMED) == 0) { 4579 fl->flags |= FL_STARVING; 4580 TAILQ_INSERT_TAIL(&sc->sfl, fl, link); 4581 callout_reset(&sc->sfl_callout, hz / 5, refill_sfl, sc); 4582 } 4583 FL_UNLOCK(fl); 4584 mtx_unlock(&sc->sfl_lock); 4585 } 4586 4587 static void 4588 handle_wrq_egr_update(struct adapter *sc, struct sge_eq *eq) 4589 { 4590 struct sge_wrq *wrq = (void *)eq; 4591 4592 atomic_readandclear_int(&eq->equiq); 4593 taskqueue_enqueue(sc->tq[eq->tx_chan], &wrq->wrq_tx_task); 4594 } 4595 4596 static void 4597 handle_eth_egr_update(struct adapter *sc, struct sge_eq *eq) 4598 { 4599 struct sge_txq *txq = (void *)eq; 4600 4601 MPASS((eq->flags & EQ_TYPEMASK) == EQ_ETH); 4602 4603 atomic_readandclear_int(&eq->equiq); 4604 mp_ring_check_drainage(txq->r, 0); 4605 taskqueue_enqueue(sc->tq[eq->tx_chan], &txq->tx_reclaim_task); 4606 } 4607 4608 static int 4609 handle_sge_egr_update(struct sge_iq *iq, const struct rss_header *rss, 4610 struct mbuf *m) 4611 { 4612 const struct cpl_sge_egr_update *cpl = (const void *)(rss + 1); 4613 unsigned int qid = G_EGR_QID(ntohl(cpl->opcode_qid)); 4614 struct adapter *sc = iq->adapter; 4615 struct sge *s = &sc->sge; 4616 struct sge_eq *eq; 4617 static void (*h[])(struct adapter *, struct sge_eq *) = {NULL, 4618 &handle_wrq_egr_update, &handle_eth_egr_update, 4619 &handle_wrq_egr_update}; 4620 4621 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 4622 rss->opcode)); 4623 4624 eq = s->eqmap[qid - s->eq_start]; 4625 (*h[eq->flags & EQ_TYPEMASK])(sc, eq); 4626 4627 return (0); 4628 } 4629 4630 /* handle_fw_msg works for both fw4_msg and fw6_msg because this is valid */ 4631 CTASSERT(offsetof(struct cpl_fw4_msg, data) == \ 4632 offsetof(struct cpl_fw6_msg, data)); 4633 4634 static int 4635 handle_fw_msg(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 4636 { 4637 struct adapter *sc = iq->adapter; 4638 const struct cpl_fw6_msg *cpl = (const void *)(rss + 1); 4639 4640 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 4641 rss->opcode)); 4642 4643 if (cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL) { 4644 const struct rss_header *rss2; 4645 4646 rss2 = (const struct rss_header *)&cpl->data[0]; 4647 return (sc->cpl_handler[rss2->opcode](iq, rss2, m)); 4648 } 4649 4650 return (sc->fw_msg_handler[cpl->type](sc, &cpl->data[0])); 4651 } 4652 4653 static int 4654 sysctl_uint16(SYSCTL_HANDLER_ARGS) 4655 { 4656 uint16_t *id = arg1; 4657 int i = *id; 4658 4659 return sysctl_handle_int(oidp, &i, 0, req); 4660 } 4661 4662 static int 4663 sysctl_bufsizes(SYSCTL_HANDLER_ARGS) 4664 { 4665 struct sge *s = arg1; 4666 struct hw_buf_info *hwb = &s->hw_buf_info[0]; 4667 struct sw_zone_info *swz = &s->sw_zone_info[0]; 4668 int i, rc; 4669 struct sbuf sb; 4670 char c; 4671 4672 sbuf_new(&sb, NULL, 32, SBUF_AUTOEXTEND); 4673 for (i = 0; i < SGE_FLBUF_SIZES; i++, hwb++) { 4674 if (hwb->zidx >= 0 && swz[hwb->zidx].size <= largest_rx_cluster) 4675 c = '*'; 4676 else 4677 c = '\0'; 4678 4679 sbuf_printf(&sb, "%u%c ", hwb->size, c); 4680 } 4681 sbuf_trim(&sb); 4682 sbuf_finish(&sb); 4683 rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req); 4684 sbuf_delete(&sb); 4685 return (rc); 4686 } 4687