1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 Chelsio Communications, Inc. 5 * All rights reserved. 6 * Written by: Navdeep Parhar <np@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include "opt_inet.h" 34 #include "opt_inet6.h" 35 #include "opt_kern_tls.h" 36 #include "opt_ratelimit.h" 37 38 #include <sys/types.h> 39 #include <sys/eventhandler.h> 40 #include <sys/mbuf.h> 41 #include <sys/socket.h> 42 #include <sys/kernel.h> 43 #include <sys/ktls.h> 44 #include <sys/malloc.h> 45 #include <sys/queue.h> 46 #include <sys/sbuf.h> 47 #include <sys/taskqueue.h> 48 #include <sys/time.h> 49 #include <sys/sglist.h> 50 #include <sys/sysctl.h> 51 #include <sys/smp.h> 52 #include <sys/socketvar.h> 53 #include <sys/counter.h> 54 #include <net/bpf.h> 55 #include <net/ethernet.h> 56 #include <net/if.h> 57 #include <net/if_vlan_var.h> 58 #include <netinet/in.h> 59 #include <netinet/ip.h> 60 #include <netinet/ip6.h> 61 #include <netinet/tcp.h> 62 #include <netinet/udp.h> 63 #include <machine/in_cksum.h> 64 #include <machine/md_var.h> 65 #include <vm/vm.h> 66 #include <vm/pmap.h> 67 #ifdef DEV_NETMAP 68 #include <machine/bus.h> 69 #include <sys/selinfo.h> 70 #include <net/if_var.h> 71 #include <net/netmap.h> 72 #include <dev/netmap/netmap_kern.h> 73 #endif 74 75 #include "common/common.h" 76 #include "common/t4_regs.h" 77 #include "common/t4_regs_values.h" 78 #include "common/t4_msg.h" 79 #include "t4_l2t.h" 80 #include "t4_mp_ring.h" 81 82 #ifdef T4_PKT_TIMESTAMP 83 #define RX_COPY_THRESHOLD (MINCLSIZE - 8) 84 #else 85 #define RX_COPY_THRESHOLD MINCLSIZE 86 #endif 87 88 /* Internal mbuf flags stored in PH_loc.eight[1]. */ 89 #define MC_NOMAP 0x01 90 #define MC_RAW_WR 0x02 91 #define MC_TLS 0x04 92 93 /* 94 * Ethernet frames are DMA'd at this byte offset into the freelist buffer. 95 * 0-7 are valid values. 96 */ 97 static int fl_pktshift = 0; 98 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pktshift, CTLFLAG_RDTUN, &fl_pktshift, 0, 99 "payload DMA offset in rx buffer (bytes)"); 100 101 /* 102 * Pad ethernet payload up to this boundary. 103 * -1: driver should figure out a good value. 104 * 0: disable padding. 105 * Any power of 2 from 32 to 4096 (both inclusive) is also a valid value. 106 */ 107 int fl_pad = -1; 108 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pad, CTLFLAG_RDTUN, &fl_pad, 0, 109 "payload pad boundary (bytes)"); 110 111 /* 112 * Status page length. 113 * -1: driver should figure out a good value. 114 * 64 or 128 are the only other valid values. 115 */ 116 static int spg_len = -1; 117 SYSCTL_INT(_hw_cxgbe, OID_AUTO, spg_len, CTLFLAG_RDTUN, &spg_len, 0, 118 "status page size (bytes)"); 119 120 /* 121 * Congestion drops. 122 * -1: no congestion feedback (not recommended). 123 * 0: backpressure the channel instead of dropping packets right away. 124 * 1: no backpressure, drop packets for the congested queue immediately. 125 */ 126 static int cong_drop = 0; 127 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cong_drop, CTLFLAG_RDTUN, &cong_drop, 0, 128 "Congestion control for RX queues (0 = backpressure, 1 = drop"); 129 130 /* 131 * Deliver multiple frames in the same free list buffer if they fit. 132 * -1: let the driver decide whether to enable buffer packing or not. 133 * 0: disable buffer packing. 134 * 1: enable buffer packing. 135 */ 136 static int buffer_packing = -1; 137 SYSCTL_INT(_hw_cxgbe, OID_AUTO, buffer_packing, CTLFLAG_RDTUN, &buffer_packing, 138 0, "Enable buffer packing"); 139 140 /* 141 * Start next frame in a packed buffer at this boundary. 142 * -1: driver should figure out a good value. 143 * T4: driver will ignore this and use the same value as fl_pad above. 144 * T5: 16, or a power of 2 from 64 to 4096 (both inclusive) is a valid value. 145 */ 146 static int fl_pack = -1; 147 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pack, CTLFLAG_RDTUN, &fl_pack, 0, 148 "payload pack boundary (bytes)"); 149 150 /* 151 * Allow the driver to create mbuf(s) in a cluster allocated for rx. 152 * 0: never; always allocate mbufs from the zone_mbuf UMA zone. 153 * 1: ok to create mbuf(s) within a cluster if there is room. 154 */ 155 static int allow_mbufs_in_cluster = 1; 156 SYSCTL_INT(_hw_cxgbe, OID_AUTO, allow_mbufs_in_cluster, CTLFLAG_RDTUN, 157 &allow_mbufs_in_cluster, 0, 158 "Allow driver to create mbufs within a rx cluster"); 159 160 /* 161 * Largest rx cluster size that the driver is allowed to allocate. 162 */ 163 static int largest_rx_cluster = MJUM16BYTES; 164 SYSCTL_INT(_hw_cxgbe, OID_AUTO, largest_rx_cluster, CTLFLAG_RDTUN, 165 &largest_rx_cluster, 0, "Largest rx cluster (bytes)"); 166 167 /* 168 * Size of cluster allocation that's most likely to succeed. The driver will 169 * fall back to this size if it fails to allocate clusters larger than this. 170 */ 171 static int safest_rx_cluster = PAGE_SIZE; 172 SYSCTL_INT(_hw_cxgbe, OID_AUTO, safest_rx_cluster, CTLFLAG_RDTUN, 173 &safest_rx_cluster, 0, "Safe rx cluster (bytes)"); 174 175 #ifdef RATELIMIT 176 /* 177 * Knob to control TCP timestamp rewriting, and the granularity of the tick used 178 * for rewriting. -1 and 0-3 are all valid values. 179 * -1: hardware should leave the TCP timestamps alone. 180 * 0: 1ms 181 * 1: 100us 182 * 2: 10us 183 * 3: 1us 184 */ 185 static int tsclk = -1; 186 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tsclk, CTLFLAG_RDTUN, &tsclk, 0, 187 "Control TCP timestamp rewriting when using pacing"); 188 189 static int eo_max_backlog = 1024 * 1024; 190 SYSCTL_INT(_hw_cxgbe, OID_AUTO, eo_max_backlog, CTLFLAG_RDTUN, &eo_max_backlog, 191 0, "Maximum backlog of ratelimited data per flow"); 192 #endif 193 194 /* 195 * The interrupt holdoff timers are multiplied by this value on T6+. 196 * 1 and 3-17 (both inclusive) are legal values. 197 */ 198 static int tscale = 1; 199 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tscale, CTLFLAG_RDTUN, &tscale, 0, 200 "Interrupt holdoff timer scale on T6+"); 201 202 /* 203 * Number of LRO entries in the lro_ctrl structure per rx queue. 204 */ 205 static int lro_entries = TCP_LRO_ENTRIES; 206 SYSCTL_INT(_hw_cxgbe, OID_AUTO, lro_entries, CTLFLAG_RDTUN, &lro_entries, 0, 207 "Number of LRO entries per RX queue"); 208 209 /* 210 * This enables presorting of frames before they're fed into tcp_lro_rx. 211 */ 212 static int lro_mbufs = 0; 213 SYSCTL_INT(_hw_cxgbe, OID_AUTO, lro_mbufs, CTLFLAG_RDTUN, &lro_mbufs, 0, 214 "Enable presorting of LRO frames"); 215 216 struct txpkts { 217 u_int wr_type; /* type 0 or type 1 */ 218 u_int npkt; /* # of packets in this work request */ 219 u_int plen; /* total payload (sum of all packets) */ 220 u_int len16; /* # of 16B pieces used by this work request */ 221 }; 222 223 /* A packet's SGL. This + m_pkthdr has all info needed for tx */ 224 struct sgl { 225 struct sglist sg; 226 struct sglist_seg seg[TX_SGL_SEGS]; 227 }; 228 229 static int service_iq(struct sge_iq *, int); 230 static int service_iq_fl(struct sge_iq *, int); 231 static struct mbuf *get_fl_payload(struct adapter *, struct sge_fl *, uint32_t); 232 static int t4_eth_rx(struct sge_iq *, const struct rss_header *, struct mbuf *); 233 static inline void init_iq(struct sge_iq *, struct adapter *, int, int, int); 234 static inline void init_fl(struct adapter *, struct sge_fl *, int, int, char *); 235 static inline void init_eq(struct adapter *, struct sge_eq *, int, int, uint8_t, 236 uint16_t, char *); 237 static int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *, 238 bus_addr_t *, void **); 239 static int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 240 void *); 241 static int alloc_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *, 242 int, int); 243 static int free_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *); 244 static void add_iq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *, 245 struct sge_iq *); 246 static void add_fl_sysctls(struct adapter *, struct sysctl_ctx_list *, 247 struct sysctl_oid *, struct sge_fl *); 248 static int alloc_fwq(struct adapter *); 249 static int free_fwq(struct adapter *); 250 static int alloc_ctrlq(struct adapter *, struct sge_wrq *, int, 251 struct sysctl_oid *); 252 static int alloc_rxq(struct vi_info *, struct sge_rxq *, int, int, 253 struct sysctl_oid *); 254 static int free_rxq(struct vi_info *, struct sge_rxq *); 255 #ifdef TCP_OFFLOAD 256 static int alloc_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *, int, int, 257 struct sysctl_oid *); 258 static int free_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *); 259 #endif 260 #ifdef DEV_NETMAP 261 static int alloc_nm_rxq(struct vi_info *, struct sge_nm_rxq *, int, int, 262 struct sysctl_oid *); 263 static int free_nm_rxq(struct vi_info *, struct sge_nm_rxq *); 264 static int alloc_nm_txq(struct vi_info *, struct sge_nm_txq *, int, int, 265 struct sysctl_oid *); 266 static int free_nm_txq(struct vi_info *, struct sge_nm_txq *); 267 #endif 268 static int ctrl_eq_alloc(struct adapter *, struct sge_eq *); 269 static int eth_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *); 270 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 271 static int ofld_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *); 272 #endif 273 static int alloc_eq(struct adapter *, struct vi_info *, struct sge_eq *); 274 static int free_eq(struct adapter *, struct sge_eq *); 275 static int alloc_wrq(struct adapter *, struct vi_info *, struct sge_wrq *, 276 struct sysctl_oid *); 277 static int free_wrq(struct adapter *, struct sge_wrq *); 278 static int alloc_txq(struct vi_info *, struct sge_txq *, int, 279 struct sysctl_oid *); 280 static int free_txq(struct vi_info *, struct sge_txq *); 281 static void oneseg_dma_callback(void *, bus_dma_segment_t *, int, int); 282 static inline void ring_fl_db(struct adapter *, struct sge_fl *); 283 static int refill_fl(struct adapter *, struct sge_fl *, int); 284 static void refill_sfl(void *); 285 static int alloc_fl_sdesc(struct sge_fl *); 286 static void free_fl_sdesc(struct adapter *, struct sge_fl *); 287 static void find_best_refill_source(struct adapter *, struct sge_fl *, int); 288 static void find_safe_refill_source(struct adapter *, struct sge_fl *); 289 static void add_fl_to_sfl(struct adapter *, struct sge_fl *); 290 291 static inline void get_pkt_gl(struct mbuf *, struct sglist *); 292 static inline u_int txpkt_len16(u_int, u_int); 293 static inline u_int txpkt_vm_len16(u_int, u_int); 294 static inline u_int txpkts0_len16(u_int); 295 static inline u_int txpkts1_len16(void); 296 static u_int write_raw_wr(struct sge_txq *, void *, struct mbuf *, u_int); 297 static u_int write_txpkt_wr(struct adapter *, struct sge_txq *, 298 struct fw_eth_tx_pkt_wr *, struct mbuf *, u_int); 299 static u_int write_txpkt_vm_wr(struct adapter *, struct sge_txq *, 300 struct fw_eth_tx_pkt_vm_wr *, struct mbuf *, u_int); 301 static int try_txpkts(struct mbuf *, struct mbuf *, struct txpkts *, u_int); 302 static int add_to_txpkts(struct mbuf *, struct txpkts *, u_int); 303 static u_int write_txpkts_wr(struct adapter *, struct sge_txq *, 304 struct fw_eth_tx_pkts_wr *, struct mbuf *, const struct txpkts *, u_int); 305 static void write_gl_to_txd(struct sge_txq *, struct mbuf *, caddr_t *, int); 306 static inline void copy_to_txd(struct sge_eq *, caddr_t, caddr_t *, int); 307 static inline void ring_eq_db(struct adapter *, struct sge_eq *, u_int); 308 static inline uint16_t read_hw_cidx(struct sge_eq *); 309 static inline u_int reclaimable_tx_desc(struct sge_eq *); 310 static inline u_int total_available_tx_desc(struct sge_eq *); 311 static u_int reclaim_tx_descs(struct sge_txq *, u_int); 312 static void tx_reclaim(void *, int); 313 static __be64 get_flit(struct sglist_seg *, int, int); 314 static int handle_sge_egr_update(struct sge_iq *, const struct rss_header *, 315 struct mbuf *); 316 static int handle_fw_msg(struct sge_iq *, const struct rss_header *, 317 struct mbuf *); 318 static int t4_handle_wrerr_rpl(struct adapter *, const __be64 *); 319 static void wrq_tx_drain(void *, int); 320 static void drain_wrq_wr_list(struct adapter *, struct sge_wrq *); 321 322 static int sysctl_uint16(SYSCTL_HANDLER_ARGS); 323 static int sysctl_bufsizes(SYSCTL_HANDLER_ARGS); 324 #ifdef RATELIMIT 325 static inline u_int txpkt_eo_len16(u_int, u_int, u_int); 326 static int ethofld_fw4_ack(struct sge_iq *, const struct rss_header *, 327 struct mbuf *); 328 #endif 329 330 static counter_u64_t extfree_refs; 331 static counter_u64_t extfree_rels; 332 333 an_handler_t t4_an_handler; 334 fw_msg_handler_t t4_fw_msg_handler[NUM_FW6_TYPES]; 335 cpl_handler_t t4_cpl_handler[NUM_CPL_CMDS]; 336 cpl_handler_t set_tcb_rpl_handlers[NUM_CPL_COOKIES]; 337 cpl_handler_t l2t_write_rpl_handlers[NUM_CPL_COOKIES]; 338 cpl_handler_t act_open_rpl_handlers[NUM_CPL_COOKIES]; 339 cpl_handler_t abort_rpl_rss_handlers[NUM_CPL_COOKIES]; 340 cpl_handler_t fw4_ack_handlers[NUM_CPL_COOKIES]; 341 342 void 343 t4_register_an_handler(an_handler_t h) 344 { 345 uintptr_t *loc; 346 347 MPASS(h == NULL || t4_an_handler == NULL); 348 349 loc = (uintptr_t *)&t4_an_handler; 350 atomic_store_rel_ptr(loc, (uintptr_t)h); 351 } 352 353 void 354 t4_register_fw_msg_handler(int type, fw_msg_handler_t h) 355 { 356 uintptr_t *loc; 357 358 MPASS(type < nitems(t4_fw_msg_handler)); 359 MPASS(h == NULL || t4_fw_msg_handler[type] == NULL); 360 /* 361 * These are dispatched by the handler for FW{4|6}_CPL_MSG using the CPL 362 * handler dispatch table. Reject any attempt to install a handler for 363 * this subtype. 364 */ 365 MPASS(type != FW_TYPE_RSSCPL); 366 MPASS(type != FW6_TYPE_RSSCPL); 367 368 loc = (uintptr_t *)&t4_fw_msg_handler[type]; 369 atomic_store_rel_ptr(loc, (uintptr_t)h); 370 } 371 372 void 373 t4_register_cpl_handler(int opcode, cpl_handler_t h) 374 { 375 uintptr_t *loc; 376 377 MPASS(opcode < nitems(t4_cpl_handler)); 378 MPASS(h == NULL || t4_cpl_handler[opcode] == NULL); 379 380 loc = (uintptr_t *)&t4_cpl_handler[opcode]; 381 atomic_store_rel_ptr(loc, (uintptr_t)h); 382 } 383 384 static int 385 set_tcb_rpl_handler(struct sge_iq *iq, const struct rss_header *rss, 386 struct mbuf *m) 387 { 388 const struct cpl_set_tcb_rpl *cpl = (const void *)(rss + 1); 389 u_int tid; 390 int cookie; 391 392 MPASS(m == NULL); 393 394 tid = GET_TID(cpl); 395 if (is_hpftid(iq->adapter, tid) || is_ftid(iq->adapter, tid)) { 396 /* 397 * The return code for filter-write is put in the CPL cookie so 398 * we have to rely on the hardware tid (is_ftid) to determine 399 * that this is a response to a filter. 400 */ 401 cookie = CPL_COOKIE_FILTER; 402 } else { 403 cookie = G_COOKIE(cpl->cookie); 404 } 405 MPASS(cookie > CPL_COOKIE_RESERVED); 406 MPASS(cookie < nitems(set_tcb_rpl_handlers)); 407 408 return (set_tcb_rpl_handlers[cookie](iq, rss, m)); 409 } 410 411 static int 412 l2t_write_rpl_handler(struct sge_iq *iq, const struct rss_header *rss, 413 struct mbuf *m) 414 { 415 const struct cpl_l2t_write_rpl *rpl = (const void *)(rss + 1); 416 unsigned int cookie; 417 418 MPASS(m == NULL); 419 420 cookie = GET_TID(rpl) & F_SYNC_WR ? CPL_COOKIE_TOM : CPL_COOKIE_FILTER; 421 return (l2t_write_rpl_handlers[cookie](iq, rss, m)); 422 } 423 424 static int 425 act_open_rpl_handler(struct sge_iq *iq, const struct rss_header *rss, 426 struct mbuf *m) 427 { 428 const struct cpl_act_open_rpl *cpl = (const void *)(rss + 1); 429 u_int cookie = G_TID_COOKIE(G_AOPEN_ATID(be32toh(cpl->atid_status))); 430 431 MPASS(m == NULL); 432 MPASS(cookie != CPL_COOKIE_RESERVED); 433 434 return (act_open_rpl_handlers[cookie](iq, rss, m)); 435 } 436 437 static int 438 abort_rpl_rss_handler(struct sge_iq *iq, const struct rss_header *rss, 439 struct mbuf *m) 440 { 441 struct adapter *sc = iq->adapter; 442 u_int cookie; 443 444 MPASS(m == NULL); 445 if (is_hashfilter(sc)) 446 cookie = CPL_COOKIE_HASHFILTER; 447 else 448 cookie = CPL_COOKIE_TOM; 449 450 return (abort_rpl_rss_handlers[cookie](iq, rss, m)); 451 } 452 453 static int 454 fw4_ack_handler(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 455 { 456 struct adapter *sc = iq->adapter; 457 const struct cpl_fw4_ack *cpl = (const void *)(rss + 1); 458 unsigned int tid = G_CPL_FW4_ACK_FLOWID(be32toh(OPCODE_TID(cpl))); 459 u_int cookie; 460 461 MPASS(m == NULL); 462 if (is_etid(sc, tid)) 463 cookie = CPL_COOKIE_ETHOFLD; 464 else 465 cookie = CPL_COOKIE_TOM; 466 467 return (fw4_ack_handlers[cookie](iq, rss, m)); 468 } 469 470 static void 471 t4_init_shared_cpl_handlers(void) 472 { 473 474 t4_register_cpl_handler(CPL_SET_TCB_RPL, set_tcb_rpl_handler); 475 t4_register_cpl_handler(CPL_L2T_WRITE_RPL, l2t_write_rpl_handler); 476 t4_register_cpl_handler(CPL_ACT_OPEN_RPL, act_open_rpl_handler); 477 t4_register_cpl_handler(CPL_ABORT_RPL_RSS, abort_rpl_rss_handler); 478 t4_register_cpl_handler(CPL_FW4_ACK, fw4_ack_handler); 479 } 480 481 void 482 t4_register_shared_cpl_handler(int opcode, cpl_handler_t h, int cookie) 483 { 484 uintptr_t *loc; 485 486 MPASS(opcode < nitems(t4_cpl_handler)); 487 MPASS(cookie > CPL_COOKIE_RESERVED); 488 MPASS(cookie < NUM_CPL_COOKIES); 489 MPASS(t4_cpl_handler[opcode] != NULL); 490 491 switch (opcode) { 492 case CPL_SET_TCB_RPL: 493 loc = (uintptr_t *)&set_tcb_rpl_handlers[cookie]; 494 break; 495 case CPL_L2T_WRITE_RPL: 496 loc = (uintptr_t *)&l2t_write_rpl_handlers[cookie]; 497 break; 498 case CPL_ACT_OPEN_RPL: 499 loc = (uintptr_t *)&act_open_rpl_handlers[cookie]; 500 break; 501 case CPL_ABORT_RPL_RSS: 502 loc = (uintptr_t *)&abort_rpl_rss_handlers[cookie]; 503 break; 504 case CPL_FW4_ACK: 505 loc = (uintptr_t *)&fw4_ack_handlers[cookie]; 506 break; 507 default: 508 MPASS(0); 509 return; 510 } 511 MPASS(h == NULL || *loc == (uintptr_t)NULL); 512 atomic_store_rel_ptr(loc, (uintptr_t)h); 513 } 514 515 /* 516 * Called on MOD_LOAD. Validates and calculates the SGE tunables. 517 */ 518 void 519 t4_sge_modload(void) 520 { 521 522 if (fl_pktshift < 0 || fl_pktshift > 7) { 523 printf("Invalid hw.cxgbe.fl_pktshift value (%d)," 524 " using 0 instead.\n", fl_pktshift); 525 fl_pktshift = 0; 526 } 527 528 if (spg_len != 64 && spg_len != 128) { 529 int len; 530 531 #if defined(__i386__) || defined(__amd64__) 532 len = cpu_clflush_line_size > 64 ? 128 : 64; 533 #else 534 len = 64; 535 #endif 536 if (spg_len != -1) { 537 printf("Invalid hw.cxgbe.spg_len value (%d)," 538 " using %d instead.\n", spg_len, len); 539 } 540 spg_len = len; 541 } 542 543 if (cong_drop < -1 || cong_drop > 1) { 544 printf("Invalid hw.cxgbe.cong_drop value (%d)," 545 " using 0 instead.\n", cong_drop); 546 cong_drop = 0; 547 } 548 549 if (tscale != 1 && (tscale < 3 || tscale > 17)) { 550 printf("Invalid hw.cxgbe.tscale value (%d)," 551 " using 1 instead.\n", tscale); 552 tscale = 1; 553 } 554 555 extfree_refs = counter_u64_alloc(M_WAITOK); 556 extfree_rels = counter_u64_alloc(M_WAITOK); 557 counter_u64_zero(extfree_refs); 558 counter_u64_zero(extfree_rels); 559 560 t4_init_shared_cpl_handlers(); 561 t4_register_cpl_handler(CPL_FW4_MSG, handle_fw_msg); 562 t4_register_cpl_handler(CPL_FW6_MSG, handle_fw_msg); 563 t4_register_cpl_handler(CPL_SGE_EGR_UPDATE, handle_sge_egr_update); 564 t4_register_cpl_handler(CPL_RX_PKT, t4_eth_rx); 565 #ifdef RATELIMIT 566 t4_register_shared_cpl_handler(CPL_FW4_ACK, ethofld_fw4_ack, 567 CPL_COOKIE_ETHOFLD); 568 #endif 569 t4_register_fw_msg_handler(FW6_TYPE_CMD_RPL, t4_handle_fw_rpl); 570 t4_register_fw_msg_handler(FW6_TYPE_WRERR_RPL, t4_handle_wrerr_rpl); 571 } 572 573 void 574 t4_sge_modunload(void) 575 { 576 577 counter_u64_free(extfree_refs); 578 counter_u64_free(extfree_rels); 579 } 580 581 uint64_t 582 t4_sge_extfree_refs(void) 583 { 584 uint64_t refs, rels; 585 586 rels = counter_u64_fetch(extfree_rels); 587 refs = counter_u64_fetch(extfree_refs); 588 589 return (refs - rels); 590 } 591 592 static inline void 593 setup_pad_and_pack_boundaries(struct adapter *sc) 594 { 595 uint32_t v, m; 596 int pad, pack, pad_shift; 597 598 pad_shift = chip_id(sc) > CHELSIO_T5 ? X_T6_INGPADBOUNDARY_SHIFT : 599 X_INGPADBOUNDARY_SHIFT; 600 pad = fl_pad; 601 if (fl_pad < (1 << pad_shift) || 602 fl_pad > (1 << (pad_shift + M_INGPADBOUNDARY)) || 603 !powerof2(fl_pad)) { 604 /* 605 * If there is any chance that we might use buffer packing and 606 * the chip is a T4, then pick 64 as the pad/pack boundary. Set 607 * it to the minimum allowed in all other cases. 608 */ 609 pad = is_t4(sc) && buffer_packing ? 64 : 1 << pad_shift; 610 611 /* 612 * For fl_pad = 0 we'll still write a reasonable value to the 613 * register but all the freelists will opt out of padding. 614 * We'll complain here only if the user tried to set it to a 615 * value greater than 0 that was invalid. 616 */ 617 if (fl_pad > 0) { 618 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pad value" 619 " (%d), using %d instead.\n", fl_pad, pad); 620 } 621 } 622 m = V_INGPADBOUNDARY(M_INGPADBOUNDARY); 623 v = V_INGPADBOUNDARY(ilog2(pad) - pad_shift); 624 t4_set_reg_field(sc, A_SGE_CONTROL, m, v); 625 626 if (is_t4(sc)) { 627 if (fl_pack != -1 && fl_pack != pad) { 628 /* Complain but carry on. */ 629 device_printf(sc->dev, "hw.cxgbe.fl_pack (%d) ignored," 630 " using %d instead.\n", fl_pack, pad); 631 } 632 return; 633 } 634 635 pack = fl_pack; 636 if (fl_pack < 16 || fl_pack == 32 || fl_pack > 4096 || 637 !powerof2(fl_pack)) { 638 pack = max(sc->params.pci.mps, CACHE_LINE_SIZE); 639 MPASS(powerof2(pack)); 640 if (pack < 16) 641 pack = 16; 642 if (pack == 32) 643 pack = 64; 644 if (pack > 4096) 645 pack = 4096; 646 if (fl_pack != -1) { 647 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pack value" 648 " (%d), using %d instead.\n", fl_pack, pack); 649 } 650 } 651 m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY); 652 if (pack == 16) 653 v = V_INGPACKBOUNDARY(0); 654 else 655 v = V_INGPACKBOUNDARY(ilog2(pack) - 5); 656 657 MPASS(!is_t4(sc)); /* T4 doesn't have SGE_CONTROL2 */ 658 t4_set_reg_field(sc, A_SGE_CONTROL2, m, v); 659 } 660 661 /* 662 * adap->params.vpd.cclk must be set up before this is called. 663 */ 664 void 665 t4_tweak_chip_settings(struct adapter *sc) 666 { 667 int i; 668 uint32_t v, m; 669 int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200}; 670 int timer_max = M_TIMERVALUE0 * 1000 / sc->params.vpd.cclk; 671 int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */ 672 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 673 static int sge_flbuf_sizes[] = { 674 MCLBYTES, 675 #if MJUMPAGESIZE != MCLBYTES 676 MJUMPAGESIZE, 677 MJUMPAGESIZE - CL_METADATA_SIZE, 678 MJUMPAGESIZE - 2 * MSIZE - CL_METADATA_SIZE, 679 #endif 680 MJUM9BYTES, 681 MJUM16BYTES, 682 MCLBYTES - MSIZE - CL_METADATA_SIZE, 683 MJUM9BYTES - CL_METADATA_SIZE, 684 MJUM16BYTES - CL_METADATA_SIZE, 685 }; 686 687 KASSERT(sc->flags & MASTER_PF, 688 ("%s: trying to change chip settings when not master.", __func__)); 689 690 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE; 691 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE | 692 V_EGRSTATUSPAGESIZE(spg_len == 128); 693 t4_set_reg_field(sc, A_SGE_CONTROL, m, v); 694 695 setup_pad_and_pack_boundaries(sc); 696 697 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) | 698 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) | 699 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) | 700 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) | 701 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) | 702 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) | 703 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) | 704 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10); 705 t4_write_reg(sc, A_SGE_HOST_PAGE_SIZE, v); 706 707 KASSERT(nitems(sge_flbuf_sizes) <= SGE_FLBUF_SIZES, 708 ("%s: hw buffer size table too big", __func__)); 709 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0, 4096); 710 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE1, 65536); 711 for (i = 0; i < min(nitems(sge_flbuf_sizes), SGE_FLBUF_SIZES); i++) { 712 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE15 - (4 * i), 713 sge_flbuf_sizes[i]); 714 } 715 716 v = V_THRESHOLD_0(intr_pktcount[0]) | V_THRESHOLD_1(intr_pktcount[1]) | 717 V_THRESHOLD_2(intr_pktcount[2]) | V_THRESHOLD_3(intr_pktcount[3]); 718 t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD, v); 719 720 KASSERT(intr_timer[0] <= timer_max, 721 ("%s: not a single usable timer (%d, %d)", __func__, intr_timer[0], 722 timer_max)); 723 for (i = 1; i < nitems(intr_timer); i++) { 724 KASSERT(intr_timer[i] >= intr_timer[i - 1], 725 ("%s: timers not listed in increasing order (%d)", 726 __func__, i)); 727 728 while (intr_timer[i] > timer_max) { 729 if (i == nitems(intr_timer) - 1) { 730 intr_timer[i] = timer_max; 731 break; 732 } 733 intr_timer[i] += intr_timer[i - 1]; 734 intr_timer[i] /= 2; 735 } 736 } 737 738 v = V_TIMERVALUE0(us_to_core_ticks(sc, intr_timer[0])) | 739 V_TIMERVALUE1(us_to_core_ticks(sc, intr_timer[1])); 740 t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1, v); 741 v = V_TIMERVALUE2(us_to_core_ticks(sc, intr_timer[2])) | 742 V_TIMERVALUE3(us_to_core_ticks(sc, intr_timer[3])); 743 t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3, v); 744 v = V_TIMERVALUE4(us_to_core_ticks(sc, intr_timer[4])) | 745 V_TIMERVALUE5(us_to_core_ticks(sc, intr_timer[5])); 746 t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5, v); 747 748 if (chip_id(sc) >= CHELSIO_T6) { 749 m = V_TSCALE(M_TSCALE); 750 if (tscale == 1) 751 v = 0; 752 else 753 v = V_TSCALE(tscale - 2); 754 t4_set_reg_field(sc, A_SGE_ITP_CONTROL, m, v); 755 756 if (sc->debug_flags & DF_DISABLE_TCB_CACHE) { 757 m = V_RDTHRESHOLD(M_RDTHRESHOLD) | F_WRTHRTHRESHEN | 758 V_WRTHRTHRESH(M_WRTHRTHRESH); 759 t4_tp_pio_read(sc, &v, 1, A_TP_CMM_CONFIG, 1); 760 v &= ~m; 761 v |= V_RDTHRESHOLD(1) | F_WRTHRTHRESHEN | 762 V_WRTHRTHRESH(16); 763 t4_tp_pio_write(sc, &v, 1, A_TP_CMM_CONFIG, 1); 764 } 765 } 766 767 /* 4K, 16K, 64K, 256K DDP "page sizes" for TDDP */ 768 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 769 t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, v); 770 771 /* 772 * 4K, 8K, 16K, 64K DDP "page sizes" for iSCSI DDP. These have been 773 * chosen with MAXPHYS = 128K in mind. The largest DDP buffer that we 774 * may have to deal with is MAXPHYS + 1 page. 775 */ 776 v = V_HPZ0(0) | V_HPZ1(1) | V_HPZ2(2) | V_HPZ3(4); 777 t4_write_reg(sc, A_ULP_RX_ISCSI_PSZ, v); 778 779 /* We use multiple DDP page sizes both in plain-TOE and ISCSI modes. */ 780 m = v = F_TDDPTAGTCB | F_ISCSITAGTCB; 781 t4_set_reg_field(sc, A_ULP_RX_CTL, m, v); 782 783 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 784 F_RESETDDPOFFSET; 785 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 786 t4_set_reg_field(sc, A_TP_PARA_REG5, m, v); 787 } 788 789 /* 790 * SGE wants the buffer to be at least 64B and then a multiple of 16. If 791 * padding is in use, the buffer's start and end need to be aligned to the pad 792 * boundary as well. We'll just make sure that the size is a multiple of the 793 * boundary here, it is up to the buffer allocation code to make sure the start 794 * of the buffer is aligned as well. 795 */ 796 static inline int 797 hwsz_ok(struct adapter *sc, int hwsz) 798 { 799 int mask = fl_pad ? sc->params.sge.pad_boundary - 1 : 16 - 1; 800 801 return (hwsz >= 64 && (hwsz & mask) == 0); 802 } 803 804 /* 805 * XXX: driver really should be able to deal with unexpected settings. 806 */ 807 int 808 t4_read_chip_settings(struct adapter *sc) 809 { 810 struct sge *s = &sc->sge; 811 struct sge_params *sp = &sc->params.sge; 812 int i, j, n, rc = 0; 813 uint32_t m, v, r; 814 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 815 static int sw_buf_sizes[] = { /* Sorted by size */ 816 MCLBYTES, 817 #if MJUMPAGESIZE != MCLBYTES 818 MJUMPAGESIZE, 819 #endif 820 MJUM9BYTES, 821 MJUM16BYTES 822 }; 823 struct sw_zone_info *swz, *safe_swz; 824 struct hw_buf_info *hwb; 825 826 m = F_RXPKTCPLMODE; 827 v = F_RXPKTCPLMODE; 828 r = sc->params.sge.sge_control; 829 if ((r & m) != v) { 830 device_printf(sc->dev, "invalid SGE_CONTROL(0x%x)\n", r); 831 rc = EINVAL; 832 } 833 834 /* 835 * If this changes then every single use of PAGE_SHIFT in the driver 836 * needs to be carefully reviewed for PAGE_SHIFT vs sp->page_shift. 837 */ 838 if (sp->page_shift != PAGE_SHIFT) { 839 device_printf(sc->dev, "invalid SGE_HOST_PAGE_SIZE(0x%x)\n", r); 840 rc = EINVAL; 841 } 842 843 /* Filter out unusable hw buffer sizes entirely (mark with -2). */ 844 hwb = &s->hw_buf_info[0]; 845 for (i = 0; i < nitems(s->hw_buf_info); i++, hwb++) { 846 r = sc->params.sge.sge_fl_buffer_size[i]; 847 hwb->size = r; 848 hwb->zidx = hwsz_ok(sc, r) ? -1 : -2; 849 hwb->next = -1; 850 } 851 852 /* 853 * Create a sorted list in decreasing order of hw buffer sizes (and so 854 * increasing order of spare area) for each software zone. 855 * 856 * If padding is enabled then the start and end of the buffer must align 857 * to the pad boundary; if packing is enabled then they must align with 858 * the pack boundary as well. Allocations from the cluster zones are 859 * aligned to min(size, 4K), so the buffer starts at that alignment and 860 * ends at hwb->size alignment. If mbuf inlining is allowed the 861 * starting alignment will be reduced to MSIZE and the driver will 862 * exercise appropriate caution when deciding on the best buffer layout 863 * to use. 864 */ 865 n = 0; /* no usable buffer size to begin with */ 866 swz = &s->sw_zone_info[0]; 867 safe_swz = NULL; 868 for (i = 0; i < SW_ZONE_SIZES; i++, swz++) { 869 int8_t head = -1, tail = -1; 870 871 swz->size = sw_buf_sizes[i]; 872 swz->zone = m_getzone(swz->size); 873 swz->type = m_gettype(swz->size); 874 875 if (swz->size < PAGE_SIZE) { 876 MPASS(powerof2(swz->size)); 877 if (fl_pad && (swz->size % sp->pad_boundary != 0)) 878 continue; 879 } 880 881 if (swz->size == safest_rx_cluster) 882 safe_swz = swz; 883 884 hwb = &s->hw_buf_info[0]; 885 for (j = 0; j < SGE_FLBUF_SIZES; j++, hwb++) { 886 if (hwb->zidx != -1 || hwb->size > swz->size) 887 continue; 888 #ifdef INVARIANTS 889 if (fl_pad) 890 MPASS(hwb->size % sp->pad_boundary == 0); 891 #endif 892 hwb->zidx = i; 893 if (head == -1) 894 head = tail = j; 895 else if (hwb->size < s->hw_buf_info[tail].size) { 896 s->hw_buf_info[tail].next = j; 897 tail = j; 898 } else { 899 int8_t *cur; 900 struct hw_buf_info *t; 901 902 for (cur = &head; *cur != -1; cur = &t->next) { 903 t = &s->hw_buf_info[*cur]; 904 if (hwb->size == t->size) { 905 hwb->zidx = -2; 906 break; 907 } 908 if (hwb->size > t->size) { 909 hwb->next = *cur; 910 *cur = j; 911 break; 912 } 913 } 914 } 915 } 916 swz->head_hwidx = head; 917 swz->tail_hwidx = tail; 918 919 if (tail != -1) { 920 n++; 921 if (swz->size - s->hw_buf_info[tail].size >= 922 CL_METADATA_SIZE) 923 sc->flags |= BUF_PACKING_OK; 924 } 925 } 926 if (n == 0) { 927 device_printf(sc->dev, "no usable SGE FL buffer size.\n"); 928 rc = EINVAL; 929 } 930 931 s->safe_hwidx1 = -1; 932 s->safe_hwidx2 = -1; 933 if (safe_swz != NULL) { 934 s->safe_hwidx1 = safe_swz->head_hwidx; 935 for (i = safe_swz->head_hwidx; i != -1; i = hwb->next) { 936 int spare; 937 938 hwb = &s->hw_buf_info[i]; 939 #ifdef INVARIANTS 940 if (fl_pad) 941 MPASS(hwb->size % sp->pad_boundary == 0); 942 #endif 943 spare = safe_swz->size - hwb->size; 944 if (spare >= CL_METADATA_SIZE) { 945 s->safe_hwidx2 = i; 946 break; 947 } 948 } 949 } 950 951 if (sc->flags & IS_VF) 952 return (0); 953 954 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 955 r = t4_read_reg(sc, A_ULP_RX_TDDP_PSZ); 956 if (r != v) { 957 device_printf(sc->dev, "invalid ULP_RX_TDDP_PSZ(0x%x)\n", r); 958 rc = EINVAL; 959 } 960 961 m = v = F_TDDPTAGTCB; 962 r = t4_read_reg(sc, A_ULP_RX_CTL); 963 if ((r & m) != v) { 964 device_printf(sc->dev, "invalid ULP_RX_CTL(0x%x)\n", r); 965 rc = EINVAL; 966 } 967 968 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 969 F_RESETDDPOFFSET; 970 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 971 r = t4_read_reg(sc, A_TP_PARA_REG5); 972 if ((r & m) != v) { 973 device_printf(sc->dev, "invalid TP_PARA_REG5(0x%x)\n", r); 974 rc = EINVAL; 975 } 976 977 t4_init_tp_params(sc, 1); 978 979 t4_read_mtu_tbl(sc, sc->params.mtus, NULL); 980 t4_load_mtus(sc, sc->params.mtus, sc->params.a_wnd, sc->params.b_wnd); 981 982 return (rc); 983 } 984 985 int 986 t4_create_dma_tag(struct adapter *sc) 987 { 988 int rc; 989 990 rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0, 991 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE, 992 BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL, 993 NULL, &sc->dmat); 994 if (rc != 0) { 995 device_printf(sc->dev, 996 "failed to create main DMA tag: %d\n", rc); 997 } 998 999 return (rc); 1000 } 1001 1002 void 1003 t4_sge_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx, 1004 struct sysctl_oid_list *children) 1005 { 1006 struct sge_params *sp = &sc->params.sge; 1007 1008 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "buffer_sizes", 1009 CTLTYPE_STRING | CTLFLAG_RD, &sc->sge, 0, sysctl_bufsizes, "A", 1010 "freelist buffer sizes"); 1011 1012 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pktshift", CTLFLAG_RD, 1013 NULL, sp->fl_pktshift, "payload DMA offset in rx buffer (bytes)"); 1014 1015 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pad", CTLFLAG_RD, 1016 NULL, sp->pad_boundary, "payload pad boundary (bytes)"); 1017 1018 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "spg_len", CTLFLAG_RD, 1019 NULL, sp->spg_len, "status page size (bytes)"); 1020 1021 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_drop", CTLFLAG_RD, 1022 NULL, cong_drop, "congestion drop setting"); 1023 1024 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pack", CTLFLAG_RD, 1025 NULL, sp->pack_boundary, "payload pack boundary (bytes)"); 1026 } 1027 1028 int 1029 t4_destroy_dma_tag(struct adapter *sc) 1030 { 1031 if (sc->dmat) 1032 bus_dma_tag_destroy(sc->dmat); 1033 1034 return (0); 1035 } 1036 1037 /* 1038 * Allocate and initialize the firmware event queue, control queues, and special 1039 * purpose rx queues owned by the adapter. 1040 * 1041 * Returns errno on failure. Resources allocated up to that point may still be 1042 * allocated. Caller is responsible for cleanup in case this function fails. 1043 */ 1044 int 1045 t4_setup_adapter_queues(struct adapter *sc) 1046 { 1047 struct sysctl_oid *oid; 1048 struct sysctl_oid_list *children; 1049 int rc, i; 1050 1051 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 1052 1053 sysctl_ctx_init(&sc->ctx); 1054 sc->flags |= ADAP_SYSCTL_CTX; 1055 1056 /* 1057 * Firmware event queue 1058 */ 1059 rc = alloc_fwq(sc); 1060 if (rc != 0) 1061 return (rc); 1062 1063 /* 1064 * That's all for the VF driver. 1065 */ 1066 if (sc->flags & IS_VF) 1067 return (rc); 1068 1069 oid = device_get_sysctl_tree(sc->dev); 1070 children = SYSCTL_CHILDREN(oid); 1071 1072 /* 1073 * XXX: General purpose rx queues, one per port. 1074 */ 1075 1076 /* 1077 * Control queues, one per port. 1078 */ 1079 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "ctrlq", 1080 CTLFLAG_RD, NULL, "control queues"); 1081 for_each_port(sc, i) { 1082 struct sge_wrq *ctrlq = &sc->sge.ctrlq[i]; 1083 1084 rc = alloc_ctrlq(sc, ctrlq, i, oid); 1085 if (rc != 0) 1086 return (rc); 1087 } 1088 1089 return (rc); 1090 } 1091 1092 /* 1093 * Idempotent 1094 */ 1095 int 1096 t4_teardown_adapter_queues(struct adapter *sc) 1097 { 1098 int i; 1099 1100 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 1101 1102 /* Do this before freeing the queue */ 1103 if (sc->flags & ADAP_SYSCTL_CTX) { 1104 sysctl_ctx_free(&sc->ctx); 1105 sc->flags &= ~ADAP_SYSCTL_CTX; 1106 } 1107 1108 if (!(sc->flags & IS_VF)) { 1109 for_each_port(sc, i) 1110 free_wrq(sc, &sc->sge.ctrlq[i]); 1111 } 1112 free_fwq(sc); 1113 1114 return (0); 1115 } 1116 1117 /* Maximum payload that can be delivered with a single iq descriptor */ 1118 static inline int 1119 mtu_to_max_payload(struct adapter *sc, int mtu) 1120 { 1121 1122 /* large enough even when hw VLAN extraction is disabled */ 1123 return (sc->params.sge.fl_pktshift + ETHER_HDR_LEN + 1124 ETHER_VLAN_ENCAP_LEN + mtu); 1125 } 1126 1127 int 1128 t4_setup_vi_queues(struct vi_info *vi) 1129 { 1130 int rc = 0, i, intr_idx, iqidx; 1131 struct sge_rxq *rxq; 1132 struct sge_txq *txq; 1133 #ifdef TCP_OFFLOAD 1134 struct sge_ofld_rxq *ofld_rxq; 1135 #endif 1136 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1137 struct sge_wrq *ofld_txq; 1138 #endif 1139 #ifdef DEV_NETMAP 1140 int saved_idx; 1141 struct sge_nm_rxq *nm_rxq; 1142 struct sge_nm_txq *nm_txq; 1143 #endif 1144 char name[16]; 1145 struct port_info *pi = vi->pi; 1146 struct adapter *sc = pi->adapter; 1147 struct ifnet *ifp = vi->ifp; 1148 struct sysctl_oid *oid = device_get_sysctl_tree(vi->dev); 1149 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 1150 int maxp, mtu = ifp->if_mtu; 1151 1152 /* Interrupt vector to start from (when using multiple vectors) */ 1153 intr_idx = vi->first_intr; 1154 1155 #ifdef DEV_NETMAP 1156 saved_idx = intr_idx; 1157 if (ifp->if_capabilities & IFCAP_NETMAP) { 1158 1159 /* netmap is supported with direct interrupts only. */ 1160 MPASS(!forwarding_intr_to_fwq(sc)); 1161 1162 /* 1163 * We don't have buffers to back the netmap rx queues 1164 * right now so we create the queues in a way that 1165 * doesn't set off any congestion signal in the chip. 1166 */ 1167 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "nm_rxq", 1168 CTLFLAG_RD, NULL, "rx queues"); 1169 for_each_nm_rxq(vi, i, nm_rxq) { 1170 rc = alloc_nm_rxq(vi, nm_rxq, intr_idx, i, oid); 1171 if (rc != 0) 1172 goto done; 1173 intr_idx++; 1174 } 1175 1176 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "nm_txq", 1177 CTLFLAG_RD, NULL, "tx queues"); 1178 for_each_nm_txq(vi, i, nm_txq) { 1179 iqidx = vi->first_nm_rxq + (i % vi->nnmrxq); 1180 rc = alloc_nm_txq(vi, nm_txq, iqidx, i, oid); 1181 if (rc != 0) 1182 goto done; 1183 } 1184 } 1185 1186 /* Normal rx queues and netmap rx queues share the same interrupts. */ 1187 intr_idx = saved_idx; 1188 #endif 1189 1190 /* 1191 * Allocate rx queues first because a default iqid is required when 1192 * creating a tx queue. 1193 */ 1194 maxp = mtu_to_max_payload(sc, mtu); 1195 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "rxq", 1196 CTLFLAG_RD, NULL, "rx queues"); 1197 for_each_rxq(vi, i, rxq) { 1198 1199 init_iq(&rxq->iq, sc, vi->tmr_idx, vi->pktc_idx, vi->qsize_rxq); 1200 1201 snprintf(name, sizeof(name), "%s rxq%d-fl", 1202 device_get_nameunit(vi->dev), i); 1203 init_fl(sc, &rxq->fl, vi->qsize_rxq / 8, maxp, name); 1204 1205 rc = alloc_rxq(vi, rxq, 1206 forwarding_intr_to_fwq(sc) ? -1 : intr_idx, i, oid); 1207 if (rc != 0) 1208 goto done; 1209 intr_idx++; 1210 } 1211 #ifdef DEV_NETMAP 1212 if (ifp->if_capabilities & IFCAP_NETMAP) 1213 intr_idx = saved_idx + max(vi->nrxq, vi->nnmrxq); 1214 #endif 1215 #ifdef TCP_OFFLOAD 1216 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_rxq", 1217 CTLFLAG_RD, NULL, "rx queues for offloaded TCP connections"); 1218 for_each_ofld_rxq(vi, i, ofld_rxq) { 1219 1220 init_iq(&ofld_rxq->iq, sc, vi->ofld_tmr_idx, vi->ofld_pktc_idx, 1221 vi->qsize_rxq); 1222 1223 snprintf(name, sizeof(name), "%s ofld_rxq%d-fl", 1224 device_get_nameunit(vi->dev), i); 1225 init_fl(sc, &ofld_rxq->fl, vi->qsize_rxq / 8, maxp, name); 1226 1227 rc = alloc_ofld_rxq(vi, ofld_rxq, 1228 forwarding_intr_to_fwq(sc) ? -1 : intr_idx, i, oid); 1229 if (rc != 0) 1230 goto done; 1231 intr_idx++; 1232 } 1233 #endif 1234 1235 /* 1236 * Now the tx queues. 1237 */ 1238 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "txq", CTLFLAG_RD, 1239 NULL, "tx queues"); 1240 for_each_txq(vi, i, txq) { 1241 iqidx = vi->first_rxq + (i % vi->nrxq); 1242 snprintf(name, sizeof(name), "%s txq%d", 1243 device_get_nameunit(vi->dev), i); 1244 init_eq(sc, &txq->eq, EQ_ETH, vi->qsize_txq, pi->tx_chan, 1245 sc->sge.rxq[iqidx].iq.cntxt_id, name); 1246 1247 rc = alloc_txq(vi, txq, i, oid); 1248 if (rc != 0) 1249 goto done; 1250 } 1251 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1252 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_txq", 1253 CTLFLAG_RD, NULL, "tx queues for TOE/ETHOFLD"); 1254 for_each_ofld_txq(vi, i, ofld_txq) { 1255 struct sysctl_oid *oid2; 1256 1257 snprintf(name, sizeof(name), "%s ofld_txq%d", 1258 device_get_nameunit(vi->dev), i); 1259 if (vi->nofldrxq > 0) { 1260 iqidx = vi->first_ofld_rxq + (i % vi->nofldrxq); 1261 init_eq(sc, &ofld_txq->eq, EQ_OFLD, vi->qsize_txq, 1262 pi->tx_chan, sc->sge.ofld_rxq[iqidx].iq.cntxt_id, 1263 name); 1264 } else { 1265 iqidx = vi->first_rxq + (i % vi->nrxq); 1266 init_eq(sc, &ofld_txq->eq, EQ_OFLD, vi->qsize_txq, 1267 pi->tx_chan, sc->sge.rxq[iqidx].iq.cntxt_id, name); 1268 } 1269 1270 snprintf(name, sizeof(name), "%d", i); 1271 oid2 = SYSCTL_ADD_NODE(&vi->ctx, SYSCTL_CHILDREN(oid), OID_AUTO, 1272 name, CTLFLAG_RD, NULL, "offload tx queue"); 1273 1274 rc = alloc_wrq(sc, vi, ofld_txq, oid2); 1275 if (rc != 0) 1276 goto done; 1277 } 1278 #endif 1279 done: 1280 if (rc) 1281 t4_teardown_vi_queues(vi); 1282 1283 return (rc); 1284 } 1285 1286 /* 1287 * Idempotent 1288 */ 1289 int 1290 t4_teardown_vi_queues(struct vi_info *vi) 1291 { 1292 int i; 1293 struct sge_rxq *rxq; 1294 struct sge_txq *txq; 1295 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1296 struct port_info *pi = vi->pi; 1297 struct adapter *sc = pi->adapter; 1298 struct sge_wrq *ofld_txq; 1299 #endif 1300 #ifdef TCP_OFFLOAD 1301 struct sge_ofld_rxq *ofld_rxq; 1302 #endif 1303 #ifdef DEV_NETMAP 1304 struct sge_nm_rxq *nm_rxq; 1305 struct sge_nm_txq *nm_txq; 1306 #endif 1307 1308 /* Do this before freeing the queues */ 1309 if (vi->flags & VI_SYSCTL_CTX) { 1310 sysctl_ctx_free(&vi->ctx); 1311 vi->flags &= ~VI_SYSCTL_CTX; 1312 } 1313 1314 #ifdef DEV_NETMAP 1315 if (vi->ifp->if_capabilities & IFCAP_NETMAP) { 1316 for_each_nm_txq(vi, i, nm_txq) { 1317 free_nm_txq(vi, nm_txq); 1318 } 1319 1320 for_each_nm_rxq(vi, i, nm_rxq) { 1321 free_nm_rxq(vi, nm_rxq); 1322 } 1323 } 1324 #endif 1325 1326 /* 1327 * Take down all the tx queues first, as they reference the rx queues 1328 * (for egress updates, etc.). 1329 */ 1330 1331 for_each_txq(vi, i, txq) { 1332 free_txq(vi, txq); 1333 } 1334 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1335 for_each_ofld_txq(vi, i, ofld_txq) { 1336 free_wrq(sc, ofld_txq); 1337 } 1338 #endif 1339 1340 /* 1341 * Then take down the rx queues. 1342 */ 1343 1344 for_each_rxq(vi, i, rxq) { 1345 free_rxq(vi, rxq); 1346 } 1347 #ifdef TCP_OFFLOAD 1348 for_each_ofld_rxq(vi, i, ofld_rxq) { 1349 free_ofld_rxq(vi, ofld_rxq); 1350 } 1351 #endif 1352 1353 return (0); 1354 } 1355 1356 /* 1357 * Interrupt handler when the driver is using only 1 interrupt. This is a very 1358 * unusual scenario. 1359 * 1360 * a) Deals with errors, if any. 1361 * b) Services firmware event queue, which is taking interrupts for all other 1362 * queues. 1363 */ 1364 void 1365 t4_intr_all(void *arg) 1366 { 1367 struct adapter *sc = arg; 1368 struct sge_iq *fwq = &sc->sge.fwq; 1369 1370 MPASS(sc->intr_count == 1); 1371 1372 if (sc->intr_type == INTR_INTX) 1373 t4_write_reg(sc, MYPF_REG(A_PCIE_PF_CLI), 0); 1374 1375 t4_intr_err(arg); 1376 t4_intr_evt(fwq); 1377 } 1378 1379 /* 1380 * Interrupt handler for errors (installed directly when multiple interrupts are 1381 * being used, or called by t4_intr_all). 1382 */ 1383 void 1384 t4_intr_err(void *arg) 1385 { 1386 struct adapter *sc = arg; 1387 uint32_t v; 1388 const bool verbose = (sc->debug_flags & DF_VERBOSE_SLOWINTR) != 0; 1389 1390 if (sc->flags & ADAP_ERR) 1391 return; 1392 1393 v = t4_read_reg(sc, MYPF_REG(A_PL_PF_INT_CAUSE)); 1394 if (v & F_PFSW) { 1395 sc->swintr++; 1396 t4_write_reg(sc, MYPF_REG(A_PL_PF_INT_CAUSE), v); 1397 } 1398 1399 t4_slow_intr_handler(sc, verbose); 1400 } 1401 1402 /* 1403 * Interrupt handler for iq-only queues. The firmware event queue is the only 1404 * such queue right now. 1405 */ 1406 void 1407 t4_intr_evt(void *arg) 1408 { 1409 struct sge_iq *iq = arg; 1410 1411 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 1412 service_iq(iq, 0); 1413 (void) atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 1414 } 1415 } 1416 1417 /* 1418 * Interrupt handler for iq+fl queues. 1419 */ 1420 void 1421 t4_intr(void *arg) 1422 { 1423 struct sge_iq *iq = arg; 1424 1425 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 1426 service_iq_fl(iq, 0); 1427 (void) atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 1428 } 1429 } 1430 1431 #ifdef DEV_NETMAP 1432 /* 1433 * Interrupt handler for netmap rx queues. 1434 */ 1435 void 1436 t4_nm_intr(void *arg) 1437 { 1438 struct sge_nm_rxq *nm_rxq = arg; 1439 1440 if (atomic_cmpset_int(&nm_rxq->nm_state, NM_ON, NM_BUSY)) { 1441 service_nm_rxq(nm_rxq); 1442 (void) atomic_cmpset_int(&nm_rxq->nm_state, NM_BUSY, NM_ON); 1443 } 1444 } 1445 1446 /* 1447 * Interrupt handler for vectors shared between NIC and netmap rx queues. 1448 */ 1449 void 1450 t4_vi_intr(void *arg) 1451 { 1452 struct irq *irq = arg; 1453 1454 MPASS(irq->nm_rxq != NULL); 1455 t4_nm_intr(irq->nm_rxq); 1456 1457 MPASS(irq->rxq != NULL); 1458 t4_intr(irq->rxq); 1459 } 1460 #endif 1461 1462 /* 1463 * Deals with interrupts on an iq-only (no freelist) queue. 1464 */ 1465 static int 1466 service_iq(struct sge_iq *iq, int budget) 1467 { 1468 struct sge_iq *q; 1469 struct adapter *sc = iq->adapter; 1470 struct iq_desc *d = &iq->desc[iq->cidx]; 1471 int ndescs = 0, limit; 1472 int rsp_type; 1473 uint32_t lq; 1474 STAILQ_HEAD(, sge_iq) iql = STAILQ_HEAD_INITIALIZER(iql); 1475 1476 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq)); 1477 KASSERT((iq->flags & IQ_HAS_FL) == 0, 1478 ("%s: called for iq %p with fl (iq->flags 0x%x)", __func__, iq, 1479 iq->flags)); 1480 MPASS((iq->flags & IQ_ADJ_CREDIT) == 0); 1481 MPASS((iq->flags & IQ_LRO_ENABLED) == 0); 1482 1483 limit = budget ? budget : iq->qsize / 16; 1484 1485 /* 1486 * We always come back and check the descriptor ring for new indirect 1487 * interrupts and other responses after running a single handler. 1488 */ 1489 for (;;) { 1490 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) { 1491 1492 rmb(); 1493 1494 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen); 1495 lq = be32toh(d->rsp.pldbuflen_qid); 1496 1497 switch (rsp_type) { 1498 case X_RSPD_TYPE_FLBUF: 1499 panic("%s: data for an iq (%p) with no freelist", 1500 __func__, iq); 1501 1502 /* NOTREACHED */ 1503 1504 case X_RSPD_TYPE_CPL: 1505 KASSERT(d->rss.opcode < NUM_CPL_CMDS, 1506 ("%s: bad opcode %02x.", __func__, 1507 d->rss.opcode)); 1508 t4_cpl_handler[d->rss.opcode](iq, &d->rss, NULL); 1509 break; 1510 1511 case X_RSPD_TYPE_INTR: 1512 /* 1513 * There are 1K interrupt-capable queues (qids 0 1514 * through 1023). A response type indicating a 1515 * forwarded interrupt with a qid >= 1K is an 1516 * iWARP async notification. 1517 */ 1518 if (__predict_true(lq >= 1024)) { 1519 t4_an_handler(iq, &d->rsp); 1520 break; 1521 } 1522 1523 q = sc->sge.iqmap[lq - sc->sge.iq_start - 1524 sc->sge.iq_base]; 1525 if (atomic_cmpset_int(&q->state, IQS_IDLE, 1526 IQS_BUSY)) { 1527 if (service_iq_fl(q, q->qsize / 16) == 0) { 1528 (void) atomic_cmpset_int(&q->state, 1529 IQS_BUSY, IQS_IDLE); 1530 } else { 1531 STAILQ_INSERT_TAIL(&iql, q, 1532 link); 1533 } 1534 } 1535 break; 1536 1537 default: 1538 KASSERT(0, 1539 ("%s: illegal response type %d on iq %p", 1540 __func__, rsp_type, iq)); 1541 log(LOG_ERR, 1542 "%s: illegal response type %d on iq %p", 1543 device_get_nameunit(sc->dev), rsp_type, iq); 1544 break; 1545 } 1546 1547 d++; 1548 if (__predict_false(++iq->cidx == iq->sidx)) { 1549 iq->cidx = 0; 1550 iq->gen ^= F_RSPD_GEN; 1551 d = &iq->desc[0]; 1552 } 1553 if (__predict_false(++ndescs == limit)) { 1554 t4_write_reg(sc, sc->sge_gts_reg, 1555 V_CIDXINC(ndescs) | 1556 V_INGRESSQID(iq->cntxt_id) | 1557 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); 1558 ndescs = 0; 1559 1560 if (budget) { 1561 return (EINPROGRESS); 1562 } 1563 } 1564 } 1565 1566 if (STAILQ_EMPTY(&iql)) 1567 break; 1568 1569 /* 1570 * Process the head only, and send it to the back of the list if 1571 * it's still not done. 1572 */ 1573 q = STAILQ_FIRST(&iql); 1574 STAILQ_REMOVE_HEAD(&iql, link); 1575 if (service_iq_fl(q, q->qsize / 8) == 0) 1576 (void) atomic_cmpset_int(&q->state, IQS_BUSY, IQS_IDLE); 1577 else 1578 STAILQ_INSERT_TAIL(&iql, q, link); 1579 } 1580 1581 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) | 1582 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params)); 1583 1584 return (0); 1585 } 1586 1587 static inline int 1588 sort_before_lro(struct lro_ctrl *lro) 1589 { 1590 1591 return (lro->lro_mbuf_max != 0); 1592 } 1593 1594 static inline uint64_t 1595 last_flit_to_ns(struct adapter *sc, uint64_t lf) 1596 { 1597 uint64_t n = be64toh(lf) & 0xfffffffffffffff; /* 60b, not 64b. */ 1598 1599 if (n > UINT64_MAX / 1000000) 1600 return (n / sc->params.vpd.cclk * 1000000); 1601 else 1602 return (n * 1000000 / sc->params.vpd.cclk); 1603 } 1604 1605 /* 1606 * Deals with interrupts on an iq+fl queue. 1607 */ 1608 static int 1609 service_iq_fl(struct sge_iq *iq, int budget) 1610 { 1611 struct sge_rxq *rxq = iq_to_rxq(iq); 1612 struct sge_fl *fl; 1613 struct adapter *sc = iq->adapter; 1614 struct iq_desc *d = &iq->desc[iq->cidx]; 1615 int ndescs = 0, limit; 1616 int rsp_type, refill, starved; 1617 uint32_t lq; 1618 uint16_t fl_hw_cidx; 1619 struct mbuf *m0; 1620 #if defined(INET) || defined(INET6) 1621 const struct timeval lro_timeout = {0, sc->lro_timeout}; 1622 struct lro_ctrl *lro = &rxq->lro; 1623 #endif 1624 1625 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq)); 1626 MPASS(iq->flags & IQ_HAS_FL); 1627 1628 limit = budget ? budget : iq->qsize / 16; 1629 fl = &rxq->fl; 1630 fl_hw_cidx = fl->hw_cidx; /* stable snapshot */ 1631 1632 #if defined(INET) || defined(INET6) 1633 if (iq->flags & IQ_ADJ_CREDIT) { 1634 MPASS(sort_before_lro(lro)); 1635 iq->flags &= ~IQ_ADJ_CREDIT; 1636 if ((d->rsp.u.type_gen & F_RSPD_GEN) != iq->gen) { 1637 tcp_lro_flush_all(lro); 1638 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(1) | 1639 V_INGRESSQID((u32)iq->cntxt_id) | 1640 V_SEINTARM(iq->intr_params)); 1641 return (0); 1642 } 1643 ndescs = 1; 1644 } 1645 #else 1646 MPASS((iq->flags & IQ_ADJ_CREDIT) == 0); 1647 #endif 1648 1649 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) { 1650 1651 rmb(); 1652 1653 refill = 0; 1654 m0 = NULL; 1655 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen); 1656 lq = be32toh(d->rsp.pldbuflen_qid); 1657 1658 switch (rsp_type) { 1659 case X_RSPD_TYPE_FLBUF: 1660 1661 m0 = get_fl_payload(sc, fl, lq); 1662 if (__predict_false(m0 == NULL)) 1663 goto out; 1664 refill = IDXDIFF(fl->hw_cidx, fl_hw_cidx, fl->sidx) > 2; 1665 1666 if (iq->flags & IQ_RX_TIMESTAMP) { 1667 /* 1668 * Fill up rcv_tstmp but do not set M_TSTMP. 1669 * rcv_tstmp is not in the format that the 1670 * kernel expects and we don't want to mislead 1671 * it. For now this is only for custom code 1672 * that knows how to interpret cxgbe's stamp. 1673 */ 1674 m0->m_pkthdr.rcv_tstmp = 1675 last_flit_to_ns(sc, d->rsp.u.last_flit); 1676 #ifdef notyet 1677 m0->m_flags |= M_TSTMP; 1678 #endif 1679 } 1680 1681 /* fall through */ 1682 1683 case X_RSPD_TYPE_CPL: 1684 KASSERT(d->rss.opcode < NUM_CPL_CMDS, 1685 ("%s: bad opcode %02x.", __func__, d->rss.opcode)); 1686 t4_cpl_handler[d->rss.opcode](iq, &d->rss, m0); 1687 break; 1688 1689 case X_RSPD_TYPE_INTR: 1690 1691 /* 1692 * There are 1K interrupt-capable queues (qids 0 1693 * through 1023). A response type indicating a 1694 * forwarded interrupt with a qid >= 1K is an 1695 * iWARP async notification. That is the only 1696 * acceptable indirect interrupt on this queue. 1697 */ 1698 if (__predict_false(lq < 1024)) { 1699 panic("%s: indirect interrupt on iq_fl %p " 1700 "with qid %u", __func__, iq, lq); 1701 } 1702 1703 t4_an_handler(iq, &d->rsp); 1704 break; 1705 1706 default: 1707 KASSERT(0, ("%s: illegal response type %d on iq %p", 1708 __func__, rsp_type, iq)); 1709 log(LOG_ERR, "%s: illegal response type %d on iq %p", 1710 device_get_nameunit(sc->dev), rsp_type, iq); 1711 break; 1712 } 1713 1714 d++; 1715 if (__predict_false(++iq->cidx == iq->sidx)) { 1716 iq->cidx = 0; 1717 iq->gen ^= F_RSPD_GEN; 1718 d = &iq->desc[0]; 1719 } 1720 if (__predict_false(++ndescs == limit)) { 1721 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) | 1722 V_INGRESSQID(iq->cntxt_id) | 1723 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); 1724 ndescs = 0; 1725 1726 #if defined(INET) || defined(INET6) 1727 if (iq->flags & IQ_LRO_ENABLED && 1728 !sort_before_lro(lro) && 1729 sc->lro_timeout != 0) { 1730 tcp_lro_flush_inactive(lro, &lro_timeout); 1731 } 1732 #endif 1733 if (budget) { 1734 FL_LOCK(fl); 1735 refill_fl(sc, fl, 32); 1736 FL_UNLOCK(fl); 1737 1738 return (EINPROGRESS); 1739 } 1740 } 1741 if (refill) { 1742 FL_LOCK(fl); 1743 refill_fl(sc, fl, 32); 1744 FL_UNLOCK(fl); 1745 fl_hw_cidx = fl->hw_cidx; 1746 } 1747 } 1748 out: 1749 #if defined(INET) || defined(INET6) 1750 if (iq->flags & IQ_LRO_ENABLED) { 1751 if (ndescs > 0 && lro->lro_mbuf_count > 8) { 1752 MPASS(sort_before_lro(lro)); 1753 /* hold back one credit and don't flush LRO state */ 1754 iq->flags |= IQ_ADJ_CREDIT; 1755 ndescs--; 1756 } else { 1757 tcp_lro_flush_all(lro); 1758 } 1759 } 1760 #endif 1761 1762 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) | 1763 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params)); 1764 1765 FL_LOCK(fl); 1766 starved = refill_fl(sc, fl, 64); 1767 FL_UNLOCK(fl); 1768 if (__predict_false(starved != 0)) 1769 add_fl_to_sfl(sc, fl); 1770 1771 return (0); 1772 } 1773 1774 static inline int 1775 cl_has_metadata(struct sge_fl *fl, struct cluster_layout *cll) 1776 { 1777 int rc = fl->flags & FL_BUF_PACKING || cll->region1 > 0; 1778 1779 if (rc) 1780 MPASS(cll->region3 >= CL_METADATA_SIZE); 1781 1782 return (rc); 1783 } 1784 1785 static inline struct cluster_metadata * 1786 cl_metadata(struct adapter *sc, struct sge_fl *fl, struct cluster_layout *cll, 1787 caddr_t cl) 1788 { 1789 1790 if (cl_has_metadata(fl, cll)) { 1791 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx]; 1792 1793 return ((struct cluster_metadata *)(cl + swz->size) - 1); 1794 } 1795 return (NULL); 1796 } 1797 1798 static void 1799 rxb_free(struct mbuf *m) 1800 { 1801 uma_zone_t zone = m->m_ext.ext_arg1; 1802 void *cl = m->m_ext.ext_arg2; 1803 1804 uma_zfree(zone, cl); 1805 counter_u64_add(extfree_rels, 1); 1806 } 1807 1808 /* 1809 * The mbuf returned by this function could be allocated from zone_mbuf or 1810 * constructed in spare room in the cluster. 1811 * 1812 * The mbuf carries the payload in one of these ways 1813 * a) frame inside the mbuf (mbuf from zone_mbuf) 1814 * b) m_cljset (for clusters without metadata) zone_mbuf 1815 * c) m_extaddref (cluster with metadata) inline mbuf 1816 * d) m_extaddref (cluster with metadata) zone_mbuf 1817 */ 1818 static struct mbuf * 1819 get_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset, 1820 int remaining) 1821 { 1822 struct mbuf *m; 1823 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 1824 struct cluster_layout *cll = &sd->cll; 1825 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx]; 1826 struct hw_buf_info *hwb = &sc->sge.hw_buf_info[cll->hwidx]; 1827 struct cluster_metadata *clm = cl_metadata(sc, fl, cll, sd->cl); 1828 int len, blen; 1829 caddr_t payload; 1830 1831 blen = hwb->size - fl->rx_offset; /* max possible in this buf */ 1832 len = min(remaining, blen); 1833 payload = sd->cl + cll->region1 + fl->rx_offset; 1834 if (fl->flags & FL_BUF_PACKING) { 1835 const u_int l = fr_offset + len; 1836 const u_int pad = roundup2(l, fl->buf_boundary) - l; 1837 1838 if (fl->rx_offset + len + pad < hwb->size) 1839 blen = len + pad; 1840 MPASS(fl->rx_offset + blen <= hwb->size); 1841 } else { 1842 MPASS(fl->rx_offset == 0); /* not packing */ 1843 } 1844 1845 1846 if (sc->sc_do_rxcopy && len < RX_COPY_THRESHOLD) { 1847 1848 /* 1849 * Copy payload into a freshly allocated mbuf. 1850 */ 1851 1852 m = fr_offset == 0 ? 1853 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA); 1854 if (m == NULL) 1855 return (NULL); 1856 fl->mbuf_allocated++; 1857 1858 /* copy data to mbuf */ 1859 bcopy(payload, mtod(m, caddr_t), len); 1860 1861 } else if (sd->nmbuf * MSIZE < cll->region1) { 1862 1863 /* 1864 * There's spare room in the cluster for an mbuf. Create one 1865 * and associate it with the payload that's in the cluster. 1866 */ 1867 1868 MPASS(clm != NULL); 1869 m = (struct mbuf *)(sd->cl + sd->nmbuf * MSIZE); 1870 /* No bzero required */ 1871 if (m_init(m, M_NOWAIT, MT_DATA, 1872 fr_offset == 0 ? M_PKTHDR | M_NOFREE : M_NOFREE)) 1873 return (NULL); 1874 fl->mbuf_inlined++; 1875 m_extaddref(m, payload, blen, &clm->refcount, rxb_free, 1876 swz->zone, sd->cl); 1877 if (sd->nmbuf++ == 0) 1878 counter_u64_add(extfree_refs, 1); 1879 1880 } else { 1881 1882 /* 1883 * Grab an mbuf from zone_mbuf and associate it with the 1884 * payload in the cluster. 1885 */ 1886 1887 m = fr_offset == 0 ? 1888 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA); 1889 if (m == NULL) 1890 return (NULL); 1891 fl->mbuf_allocated++; 1892 if (clm != NULL) { 1893 m_extaddref(m, payload, blen, &clm->refcount, 1894 rxb_free, swz->zone, sd->cl); 1895 if (sd->nmbuf++ == 0) 1896 counter_u64_add(extfree_refs, 1); 1897 } else { 1898 m_cljset(m, sd->cl, swz->type); 1899 sd->cl = NULL; /* consumed, not a recycle candidate */ 1900 } 1901 } 1902 if (fr_offset == 0) 1903 m->m_pkthdr.len = remaining; 1904 m->m_len = len; 1905 1906 if (fl->flags & FL_BUF_PACKING) { 1907 fl->rx_offset += blen; 1908 MPASS(fl->rx_offset <= hwb->size); 1909 if (fl->rx_offset < hwb->size) 1910 return (m); /* without advancing the cidx */ 1911 } 1912 1913 if (__predict_false(++fl->cidx % 8 == 0)) { 1914 uint16_t cidx = fl->cidx / 8; 1915 1916 if (__predict_false(cidx == fl->sidx)) 1917 fl->cidx = cidx = 0; 1918 fl->hw_cidx = cidx; 1919 } 1920 fl->rx_offset = 0; 1921 1922 return (m); 1923 } 1924 1925 static struct mbuf * 1926 get_fl_payload(struct adapter *sc, struct sge_fl *fl, uint32_t len_newbuf) 1927 { 1928 struct mbuf *m0, *m, **pnext; 1929 u_int remaining; 1930 const u_int total = G_RSPD_LEN(len_newbuf); 1931 1932 if (__predict_false(fl->flags & FL_BUF_RESUME)) { 1933 M_ASSERTPKTHDR(fl->m0); 1934 MPASS(fl->m0->m_pkthdr.len == total); 1935 MPASS(fl->remaining < total); 1936 1937 m0 = fl->m0; 1938 pnext = fl->pnext; 1939 remaining = fl->remaining; 1940 fl->flags &= ~FL_BUF_RESUME; 1941 goto get_segment; 1942 } 1943 1944 if (fl->rx_offset > 0 && len_newbuf & F_RSPD_NEWBUF) { 1945 fl->rx_offset = 0; 1946 if (__predict_false(++fl->cidx % 8 == 0)) { 1947 uint16_t cidx = fl->cidx / 8; 1948 1949 if (__predict_false(cidx == fl->sidx)) 1950 fl->cidx = cidx = 0; 1951 fl->hw_cidx = cidx; 1952 } 1953 } 1954 1955 /* 1956 * Payload starts at rx_offset in the current hw buffer. Its length is 1957 * 'len' and it may span multiple hw buffers. 1958 */ 1959 1960 m0 = get_scatter_segment(sc, fl, 0, total); 1961 if (m0 == NULL) 1962 return (NULL); 1963 remaining = total - m0->m_len; 1964 pnext = &m0->m_next; 1965 while (remaining > 0) { 1966 get_segment: 1967 MPASS(fl->rx_offset == 0); 1968 m = get_scatter_segment(sc, fl, total - remaining, remaining); 1969 if (__predict_false(m == NULL)) { 1970 fl->m0 = m0; 1971 fl->pnext = pnext; 1972 fl->remaining = remaining; 1973 fl->flags |= FL_BUF_RESUME; 1974 return (NULL); 1975 } 1976 *pnext = m; 1977 pnext = &m->m_next; 1978 remaining -= m->m_len; 1979 } 1980 *pnext = NULL; 1981 1982 M_ASSERTPKTHDR(m0); 1983 return (m0); 1984 } 1985 1986 static int 1987 t4_eth_rx(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0) 1988 { 1989 struct sge_rxq *rxq = iq_to_rxq(iq); 1990 struct ifnet *ifp = rxq->ifp; 1991 struct adapter *sc = iq->adapter; 1992 const struct cpl_rx_pkt *cpl = (const void *)(rss + 1); 1993 #if defined(INET) || defined(INET6) 1994 struct lro_ctrl *lro = &rxq->lro; 1995 #endif 1996 static const int sw_hashtype[4][2] = { 1997 {M_HASHTYPE_NONE, M_HASHTYPE_NONE}, 1998 {M_HASHTYPE_RSS_IPV4, M_HASHTYPE_RSS_IPV6}, 1999 {M_HASHTYPE_RSS_TCP_IPV4, M_HASHTYPE_RSS_TCP_IPV6}, 2000 {M_HASHTYPE_RSS_UDP_IPV4, M_HASHTYPE_RSS_UDP_IPV6}, 2001 }; 2002 2003 KASSERT(m0 != NULL, ("%s: no payload with opcode %02x", __func__, 2004 rss->opcode)); 2005 2006 m0->m_pkthdr.len -= sc->params.sge.fl_pktshift; 2007 m0->m_len -= sc->params.sge.fl_pktshift; 2008 m0->m_data += sc->params.sge.fl_pktshift; 2009 2010 m0->m_pkthdr.rcvif = ifp; 2011 M_HASHTYPE_SET(m0, sw_hashtype[rss->hash_type][rss->ipv6]); 2012 m0->m_pkthdr.flowid = be32toh(rss->hash_val); 2013 2014 if (cpl->csum_calc && !(cpl->err_vec & sc->params.tp.err_vec_mask)) { 2015 if (ifp->if_capenable & IFCAP_RXCSUM && 2016 cpl->l2info & htobe32(F_RXF_IP)) { 2017 m0->m_pkthdr.csum_flags = (CSUM_IP_CHECKED | 2018 CSUM_IP_VALID | CSUM_DATA_VALID | CSUM_PSEUDO_HDR); 2019 rxq->rxcsum++; 2020 } else if (ifp->if_capenable & IFCAP_RXCSUM_IPV6 && 2021 cpl->l2info & htobe32(F_RXF_IP6)) { 2022 m0->m_pkthdr.csum_flags = (CSUM_DATA_VALID_IPV6 | 2023 CSUM_PSEUDO_HDR); 2024 rxq->rxcsum++; 2025 } 2026 2027 if (__predict_false(cpl->ip_frag)) 2028 m0->m_pkthdr.csum_data = be16toh(cpl->csum); 2029 else 2030 m0->m_pkthdr.csum_data = 0xffff; 2031 } 2032 2033 if (cpl->vlan_ex) { 2034 m0->m_pkthdr.ether_vtag = be16toh(cpl->vlan); 2035 m0->m_flags |= M_VLANTAG; 2036 rxq->vlan_extraction++; 2037 } 2038 2039 #ifdef NUMA 2040 m0->m_pkthdr.numa_domain = ifp->if_numa_domain; 2041 #endif 2042 #if defined(INET) || defined(INET6) 2043 if (iq->flags & IQ_LRO_ENABLED) { 2044 if (sort_before_lro(lro)) { 2045 tcp_lro_queue_mbuf(lro, m0); 2046 return (0); /* queued for sort, then LRO */ 2047 } 2048 if (tcp_lro_rx(lro, m0, 0) == 0) 2049 return (0); /* queued for LRO */ 2050 } 2051 #endif 2052 ifp->if_input(ifp, m0); 2053 2054 return (0); 2055 } 2056 2057 /* 2058 * Must drain the wrq or make sure that someone else will. 2059 */ 2060 static void 2061 wrq_tx_drain(void *arg, int n) 2062 { 2063 struct sge_wrq *wrq = arg; 2064 struct sge_eq *eq = &wrq->eq; 2065 2066 EQ_LOCK(eq); 2067 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 2068 drain_wrq_wr_list(wrq->adapter, wrq); 2069 EQ_UNLOCK(eq); 2070 } 2071 2072 static void 2073 drain_wrq_wr_list(struct adapter *sc, struct sge_wrq *wrq) 2074 { 2075 struct sge_eq *eq = &wrq->eq; 2076 u_int available, dbdiff; /* # of hardware descriptors */ 2077 u_int n; 2078 struct wrqe *wr; 2079 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */ 2080 2081 EQ_LOCK_ASSERT_OWNED(eq); 2082 MPASS(TAILQ_EMPTY(&wrq->incomplete_wrs)); 2083 wr = STAILQ_FIRST(&wrq->wr_list); 2084 MPASS(wr != NULL); /* Must be called with something useful to do */ 2085 MPASS(eq->pidx == eq->dbidx); 2086 dbdiff = 0; 2087 2088 do { 2089 eq->cidx = read_hw_cidx(eq); 2090 if (eq->pidx == eq->cidx) 2091 available = eq->sidx - 1; 2092 else 2093 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2094 2095 MPASS(wr->wrq == wrq); 2096 n = howmany(wr->wr_len, EQ_ESIZE); 2097 if (available < n) 2098 break; 2099 2100 dst = (void *)&eq->desc[eq->pidx]; 2101 if (__predict_true(eq->sidx - eq->pidx > n)) { 2102 /* Won't wrap, won't end exactly at the status page. */ 2103 bcopy(&wr->wr[0], dst, wr->wr_len); 2104 eq->pidx += n; 2105 } else { 2106 int first_portion = (eq->sidx - eq->pidx) * EQ_ESIZE; 2107 2108 bcopy(&wr->wr[0], dst, first_portion); 2109 if (wr->wr_len > first_portion) { 2110 bcopy(&wr->wr[first_portion], &eq->desc[0], 2111 wr->wr_len - first_portion); 2112 } 2113 eq->pidx = n - (eq->sidx - eq->pidx); 2114 } 2115 wrq->tx_wrs_copied++; 2116 2117 if (available < eq->sidx / 4 && 2118 atomic_cmpset_int(&eq->equiq, 0, 1)) { 2119 /* 2120 * XXX: This is not 100% reliable with some 2121 * types of WRs. But this is a very unusual 2122 * situation for an ofld/ctrl queue anyway. 2123 */ 2124 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ | 2125 F_FW_WR_EQUEQ); 2126 } 2127 2128 dbdiff += n; 2129 if (dbdiff >= 16) { 2130 ring_eq_db(sc, eq, dbdiff); 2131 dbdiff = 0; 2132 } 2133 2134 STAILQ_REMOVE_HEAD(&wrq->wr_list, link); 2135 free_wrqe(wr); 2136 MPASS(wrq->nwr_pending > 0); 2137 wrq->nwr_pending--; 2138 MPASS(wrq->ndesc_needed >= n); 2139 wrq->ndesc_needed -= n; 2140 } while ((wr = STAILQ_FIRST(&wrq->wr_list)) != NULL); 2141 2142 if (dbdiff) 2143 ring_eq_db(sc, eq, dbdiff); 2144 } 2145 2146 /* 2147 * Doesn't fail. Holds on to work requests it can't send right away. 2148 */ 2149 void 2150 t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, struct wrqe *wr) 2151 { 2152 #ifdef INVARIANTS 2153 struct sge_eq *eq = &wrq->eq; 2154 #endif 2155 2156 EQ_LOCK_ASSERT_OWNED(eq); 2157 MPASS(wr != NULL); 2158 MPASS(wr->wr_len > 0 && wr->wr_len <= SGE_MAX_WR_LEN); 2159 MPASS((wr->wr_len & 0x7) == 0); 2160 2161 STAILQ_INSERT_TAIL(&wrq->wr_list, wr, link); 2162 wrq->nwr_pending++; 2163 wrq->ndesc_needed += howmany(wr->wr_len, EQ_ESIZE); 2164 2165 if (!TAILQ_EMPTY(&wrq->incomplete_wrs)) 2166 return; /* commit_wrq_wr will drain wr_list as well. */ 2167 2168 drain_wrq_wr_list(sc, wrq); 2169 2170 /* Doorbell must have caught up to the pidx. */ 2171 MPASS(eq->pidx == eq->dbidx); 2172 } 2173 2174 void 2175 t4_update_fl_bufsize(struct ifnet *ifp) 2176 { 2177 struct vi_info *vi = ifp->if_softc; 2178 struct adapter *sc = vi->pi->adapter; 2179 struct sge_rxq *rxq; 2180 #ifdef TCP_OFFLOAD 2181 struct sge_ofld_rxq *ofld_rxq; 2182 #endif 2183 struct sge_fl *fl; 2184 int i, maxp, mtu = ifp->if_mtu; 2185 2186 maxp = mtu_to_max_payload(sc, mtu); 2187 for_each_rxq(vi, i, rxq) { 2188 fl = &rxq->fl; 2189 2190 FL_LOCK(fl); 2191 find_best_refill_source(sc, fl, maxp); 2192 FL_UNLOCK(fl); 2193 } 2194 #ifdef TCP_OFFLOAD 2195 for_each_ofld_rxq(vi, i, ofld_rxq) { 2196 fl = &ofld_rxq->fl; 2197 2198 FL_LOCK(fl); 2199 find_best_refill_source(sc, fl, maxp); 2200 FL_UNLOCK(fl); 2201 } 2202 #endif 2203 } 2204 2205 static inline int 2206 mbuf_nsegs(struct mbuf *m) 2207 { 2208 2209 M_ASSERTPKTHDR(m); 2210 KASSERT(m->m_pkthdr.l5hlen > 0, 2211 ("%s: mbuf %p missing information on # of segments.", __func__, m)); 2212 2213 return (m->m_pkthdr.l5hlen); 2214 } 2215 2216 static inline void 2217 set_mbuf_nsegs(struct mbuf *m, uint8_t nsegs) 2218 { 2219 2220 M_ASSERTPKTHDR(m); 2221 m->m_pkthdr.l5hlen = nsegs; 2222 } 2223 2224 static inline int 2225 mbuf_cflags(struct mbuf *m) 2226 { 2227 2228 M_ASSERTPKTHDR(m); 2229 return (m->m_pkthdr.PH_loc.eight[4]); 2230 } 2231 2232 static inline void 2233 set_mbuf_cflags(struct mbuf *m, uint8_t flags) 2234 { 2235 2236 M_ASSERTPKTHDR(m); 2237 m->m_pkthdr.PH_loc.eight[4] = flags; 2238 } 2239 2240 static inline int 2241 mbuf_len16(struct mbuf *m) 2242 { 2243 int n; 2244 2245 M_ASSERTPKTHDR(m); 2246 n = m->m_pkthdr.PH_loc.eight[0]; 2247 if (!(mbuf_cflags(m) & MC_TLS)) 2248 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16); 2249 2250 return (n); 2251 } 2252 2253 static inline void 2254 set_mbuf_len16(struct mbuf *m, uint8_t len16) 2255 { 2256 2257 M_ASSERTPKTHDR(m); 2258 m->m_pkthdr.PH_loc.eight[0] = len16; 2259 } 2260 2261 #ifdef RATELIMIT 2262 static inline int 2263 mbuf_eo_nsegs(struct mbuf *m) 2264 { 2265 2266 M_ASSERTPKTHDR(m); 2267 return (m->m_pkthdr.PH_loc.eight[1]); 2268 } 2269 2270 static inline void 2271 set_mbuf_eo_nsegs(struct mbuf *m, uint8_t nsegs) 2272 { 2273 2274 M_ASSERTPKTHDR(m); 2275 m->m_pkthdr.PH_loc.eight[1] = nsegs; 2276 } 2277 2278 static inline int 2279 mbuf_eo_len16(struct mbuf *m) 2280 { 2281 int n; 2282 2283 M_ASSERTPKTHDR(m); 2284 n = m->m_pkthdr.PH_loc.eight[2]; 2285 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16); 2286 2287 return (n); 2288 } 2289 2290 static inline void 2291 set_mbuf_eo_len16(struct mbuf *m, uint8_t len16) 2292 { 2293 2294 M_ASSERTPKTHDR(m); 2295 m->m_pkthdr.PH_loc.eight[2] = len16; 2296 } 2297 2298 static inline int 2299 mbuf_eo_tsclk_tsoff(struct mbuf *m) 2300 { 2301 2302 M_ASSERTPKTHDR(m); 2303 return (m->m_pkthdr.PH_loc.eight[3]); 2304 } 2305 2306 static inline void 2307 set_mbuf_eo_tsclk_tsoff(struct mbuf *m, uint8_t tsclk_tsoff) 2308 { 2309 2310 M_ASSERTPKTHDR(m); 2311 m->m_pkthdr.PH_loc.eight[3] = tsclk_tsoff; 2312 } 2313 2314 static inline int 2315 needs_eo(struct cxgbe_snd_tag *cst) 2316 { 2317 2318 return (cst != NULL && cst->type == IF_SND_TAG_TYPE_RATE_LIMIT); 2319 } 2320 #endif 2321 2322 /* 2323 * Try to allocate an mbuf to contain a raw work request. To make it 2324 * easy to construct the work request, don't allocate a chain but a 2325 * single mbuf. 2326 */ 2327 struct mbuf * 2328 alloc_wr_mbuf(int len, int how) 2329 { 2330 struct mbuf *m; 2331 2332 if (len <= MHLEN) 2333 m = m_gethdr(how, MT_DATA); 2334 else if (len <= MCLBYTES) 2335 m = m_getcl(how, MT_DATA, M_PKTHDR); 2336 else 2337 m = NULL; 2338 if (m == NULL) 2339 return (NULL); 2340 m->m_pkthdr.len = len; 2341 m->m_len = len; 2342 set_mbuf_cflags(m, MC_RAW_WR); 2343 set_mbuf_len16(m, howmany(len, 16)); 2344 return (m); 2345 } 2346 2347 static inline int 2348 needs_hwcsum(struct mbuf *m) 2349 { 2350 2351 M_ASSERTPKTHDR(m); 2352 2353 return (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_IP | 2354 CSUM_TSO | CSUM_UDP_IPV6 | CSUM_TCP_IPV6)); 2355 } 2356 2357 static inline int 2358 needs_tso(struct mbuf *m) 2359 { 2360 2361 M_ASSERTPKTHDR(m); 2362 2363 return (m->m_pkthdr.csum_flags & CSUM_TSO); 2364 } 2365 2366 static inline int 2367 needs_l3_csum(struct mbuf *m) 2368 { 2369 2370 M_ASSERTPKTHDR(m); 2371 2372 return (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TSO)); 2373 } 2374 2375 static inline int 2376 needs_tcp_csum(struct mbuf *m) 2377 { 2378 2379 M_ASSERTPKTHDR(m); 2380 return (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_TCP_IPV6 | CSUM_TSO)); 2381 } 2382 2383 #ifdef RATELIMIT 2384 static inline int 2385 needs_l4_csum(struct mbuf *m) 2386 { 2387 2388 M_ASSERTPKTHDR(m); 2389 2390 return (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_UDP_IPV6 | 2391 CSUM_TCP_IPV6 | CSUM_TSO)); 2392 } 2393 2394 static inline int 2395 needs_udp_csum(struct mbuf *m) 2396 { 2397 2398 M_ASSERTPKTHDR(m); 2399 return (m->m_pkthdr.csum_flags & (CSUM_UDP | CSUM_UDP_IPV6)); 2400 } 2401 #endif 2402 2403 static inline int 2404 needs_vlan_insertion(struct mbuf *m) 2405 { 2406 2407 M_ASSERTPKTHDR(m); 2408 2409 return (m->m_flags & M_VLANTAG); 2410 } 2411 2412 static void * 2413 m_advance(struct mbuf **pm, int *poffset, int len) 2414 { 2415 struct mbuf *m = *pm; 2416 int offset = *poffset; 2417 uintptr_t p = 0; 2418 2419 MPASS(len > 0); 2420 2421 for (;;) { 2422 if (offset + len < m->m_len) { 2423 offset += len; 2424 p = mtod(m, uintptr_t) + offset; 2425 break; 2426 } 2427 len -= m->m_len - offset; 2428 m = m->m_next; 2429 offset = 0; 2430 MPASS(m != NULL); 2431 } 2432 *poffset = offset; 2433 *pm = m; 2434 return ((void *)p); 2435 } 2436 2437 static inline int 2438 count_mbuf_ext_pgs(struct mbuf *m, int skip, vm_paddr_t *nextaddr) 2439 { 2440 struct mbuf_ext_pgs *ext_pgs; 2441 vm_paddr_t paddr; 2442 int i, len, off, pglen, pgoff, seglen, segoff; 2443 int nsegs = 0; 2444 2445 MBUF_EXT_PGS_ASSERT(m); 2446 ext_pgs = m->m_ext.ext_pgs; 2447 off = mtod(m, vm_offset_t); 2448 len = m->m_len; 2449 off += skip; 2450 len -= skip; 2451 2452 if (ext_pgs->hdr_len != 0) { 2453 if (off >= ext_pgs->hdr_len) { 2454 off -= ext_pgs->hdr_len; 2455 } else { 2456 seglen = ext_pgs->hdr_len - off; 2457 segoff = off; 2458 seglen = min(seglen, len); 2459 off = 0; 2460 len -= seglen; 2461 paddr = pmap_kextract( 2462 (vm_offset_t)&ext_pgs->hdr[segoff]); 2463 if (*nextaddr != paddr) 2464 nsegs++; 2465 *nextaddr = paddr + seglen; 2466 } 2467 } 2468 pgoff = ext_pgs->first_pg_off; 2469 for (i = 0; i < ext_pgs->npgs && len > 0; i++) { 2470 pglen = mbuf_ext_pg_len(ext_pgs, i, pgoff); 2471 if (off >= pglen) { 2472 off -= pglen; 2473 pgoff = 0; 2474 continue; 2475 } 2476 seglen = pglen - off; 2477 segoff = pgoff + off; 2478 off = 0; 2479 seglen = min(seglen, len); 2480 len -= seglen; 2481 paddr = ext_pgs->pa[i] + segoff; 2482 if (*nextaddr != paddr) 2483 nsegs++; 2484 *nextaddr = paddr + seglen; 2485 pgoff = 0; 2486 }; 2487 if (len != 0) { 2488 seglen = min(len, ext_pgs->trail_len - off); 2489 len -= seglen; 2490 paddr = pmap_kextract((vm_offset_t)&ext_pgs->trail[off]); 2491 if (*nextaddr != paddr) 2492 nsegs++; 2493 *nextaddr = paddr + seglen; 2494 } 2495 2496 return (nsegs); 2497 } 2498 2499 2500 /* 2501 * Can deal with empty mbufs in the chain that have m_len = 0, but the chain 2502 * must have at least one mbuf that's not empty. It is possible for this 2503 * routine to return 0 if skip accounts for all the contents of the mbuf chain. 2504 */ 2505 static inline int 2506 count_mbuf_nsegs(struct mbuf *m, int skip, uint8_t *cflags) 2507 { 2508 vm_paddr_t nextaddr, paddr; 2509 vm_offset_t va; 2510 int len, nsegs; 2511 2512 M_ASSERTPKTHDR(m); 2513 MPASS(m->m_pkthdr.len > 0); 2514 MPASS(m->m_pkthdr.len >= skip); 2515 2516 nsegs = 0; 2517 nextaddr = 0; 2518 for (; m; m = m->m_next) { 2519 len = m->m_len; 2520 if (__predict_false(len == 0)) 2521 continue; 2522 if (skip >= len) { 2523 skip -= len; 2524 continue; 2525 } 2526 if ((m->m_flags & M_NOMAP) != 0) { 2527 *cflags |= MC_NOMAP; 2528 nsegs += count_mbuf_ext_pgs(m, skip, &nextaddr); 2529 skip = 0; 2530 continue; 2531 } 2532 va = mtod(m, vm_offset_t) + skip; 2533 len -= skip; 2534 skip = 0; 2535 paddr = pmap_kextract(va); 2536 nsegs += sglist_count((void *)(uintptr_t)va, len); 2537 if (paddr == nextaddr) 2538 nsegs--; 2539 nextaddr = pmap_kextract(va + len - 1) + 1; 2540 } 2541 2542 return (nsegs); 2543 } 2544 2545 /* 2546 * Analyze the mbuf to determine its tx needs. The mbuf passed in may change: 2547 * a) caller can assume it's been freed if this function returns with an error. 2548 * b) it may get defragged up if the gather list is too long for the hardware. 2549 */ 2550 int 2551 parse_pkt(struct adapter *sc, struct mbuf **mp) 2552 { 2553 struct mbuf *m0 = *mp, *m; 2554 int rc, nsegs, defragged = 0, offset; 2555 struct ether_header *eh; 2556 void *l3hdr; 2557 #if defined(INET) || defined(INET6) 2558 struct tcphdr *tcp; 2559 #endif 2560 #if defined(KERN_TLS) || defined(RATELIMIT) 2561 struct cxgbe_snd_tag *cst; 2562 #endif 2563 uint16_t eh_type; 2564 uint8_t cflags; 2565 2566 cflags = 0; 2567 M_ASSERTPKTHDR(m0); 2568 if (__predict_false(m0->m_pkthdr.len < ETHER_HDR_LEN)) { 2569 rc = EINVAL; 2570 fail: 2571 m_freem(m0); 2572 *mp = NULL; 2573 return (rc); 2574 } 2575 restart: 2576 /* 2577 * First count the number of gather list segments in the payload. 2578 * Defrag the mbuf if nsegs exceeds the hardware limit. 2579 */ 2580 M_ASSERTPKTHDR(m0); 2581 MPASS(m0->m_pkthdr.len > 0); 2582 nsegs = count_mbuf_nsegs(m0, 0, &cflags); 2583 #if defined(KERN_TLS) || defined(RATELIMIT) 2584 if (m0->m_pkthdr.csum_flags & CSUM_SND_TAG) 2585 cst = mst_to_cst(m0->m_pkthdr.snd_tag); 2586 else 2587 cst = NULL; 2588 #endif 2589 #ifdef KERN_TLS 2590 if (cst != NULL && cst->type == IF_SND_TAG_TYPE_TLS) { 2591 int len16; 2592 2593 cflags |= MC_TLS; 2594 set_mbuf_cflags(m0, cflags); 2595 rc = t6_ktls_parse_pkt(m0, &nsegs, &len16); 2596 if (rc != 0) 2597 goto fail; 2598 set_mbuf_nsegs(m0, nsegs); 2599 set_mbuf_len16(m0, len16); 2600 return (0); 2601 } 2602 #endif 2603 if (nsegs > (needs_tso(m0) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS)) { 2604 if (defragged++ > 0 || (m = m_defrag(m0, M_NOWAIT)) == NULL) { 2605 rc = EFBIG; 2606 goto fail; 2607 } 2608 *mp = m0 = m; /* update caller's copy after defrag */ 2609 goto restart; 2610 } 2611 2612 if (__predict_false(nsegs > 2 && m0->m_pkthdr.len <= MHLEN && 2613 !(cflags & MC_NOMAP))) { 2614 m0 = m_pullup(m0, m0->m_pkthdr.len); 2615 if (m0 == NULL) { 2616 /* Should have left well enough alone. */ 2617 rc = EFBIG; 2618 goto fail; 2619 } 2620 *mp = m0; /* update caller's copy after pullup */ 2621 goto restart; 2622 } 2623 set_mbuf_nsegs(m0, nsegs); 2624 set_mbuf_cflags(m0, cflags); 2625 if (sc->flags & IS_VF) 2626 set_mbuf_len16(m0, txpkt_vm_len16(nsegs, needs_tso(m0))); 2627 else 2628 set_mbuf_len16(m0, txpkt_len16(nsegs, needs_tso(m0))); 2629 2630 #ifdef RATELIMIT 2631 /* 2632 * Ethofld is limited to TCP and UDP for now, and only when L4 hw 2633 * checksumming is enabled. needs_l4_csum happens to check for all the 2634 * right things. 2635 */ 2636 if (__predict_false(needs_eo(cst) && !needs_l4_csum(m0))) { 2637 m_snd_tag_rele(m0->m_pkthdr.snd_tag); 2638 m0->m_pkthdr.snd_tag = NULL; 2639 m0->m_pkthdr.csum_flags &= ~CSUM_SND_TAG; 2640 cst = NULL; 2641 } 2642 #endif 2643 2644 if (!needs_hwcsum(m0) 2645 #ifdef RATELIMIT 2646 && !needs_eo(cst) 2647 #endif 2648 ) 2649 return (0); 2650 2651 m = m0; 2652 eh = mtod(m, struct ether_header *); 2653 eh_type = ntohs(eh->ether_type); 2654 if (eh_type == ETHERTYPE_VLAN) { 2655 struct ether_vlan_header *evh = (void *)eh; 2656 2657 eh_type = ntohs(evh->evl_proto); 2658 m0->m_pkthdr.l2hlen = sizeof(*evh); 2659 } else 2660 m0->m_pkthdr.l2hlen = sizeof(*eh); 2661 2662 offset = 0; 2663 l3hdr = m_advance(&m, &offset, m0->m_pkthdr.l2hlen); 2664 2665 switch (eh_type) { 2666 #ifdef INET6 2667 case ETHERTYPE_IPV6: 2668 { 2669 struct ip6_hdr *ip6 = l3hdr; 2670 2671 MPASS(!needs_tso(m0) || ip6->ip6_nxt == IPPROTO_TCP); 2672 2673 m0->m_pkthdr.l3hlen = sizeof(*ip6); 2674 break; 2675 } 2676 #endif 2677 #ifdef INET 2678 case ETHERTYPE_IP: 2679 { 2680 struct ip *ip = l3hdr; 2681 2682 m0->m_pkthdr.l3hlen = ip->ip_hl * 4; 2683 break; 2684 } 2685 #endif 2686 default: 2687 panic("%s: ethertype 0x%04x unknown. if_cxgbe must be compiled" 2688 " with the same INET/INET6 options as the kernel.", 2689 __func__, eh_type); 2690 } 2691 2692 #if defined(INET) || defined(INET6) 2693 if (needs_tcp_csum(m0)) { 2694 tcp = m_advance(&m, &offset, m0->m_pkthdr.l3hlen); 2695 m0->m_pkthdr.l4hlen = tcp->th_off * 4; 2696 #ifdef RATELIMIT 2697 if (tsclk >= 0 && *(uint32_t *)(tcp + 1) == ntohl(0x0101080a)) { 2698 set_mbuf_eo_tsclk_tsoff(m0, 2699 V_FW_ETH_TX_EO_WR_TSCLK(tsclk) | 2700 V_FW_ETH_TX_EO_WR_TSOFF(sizeof(*tcp) / 2 + 1)); 2701 } else 2702 set_mbuf_eo_tsclk_tsoff(m0, 0); 2703 } else if (needs_udp_csum(m0)) { 2704 m0->m_pkthdr.l4hlen = sizeof(struct udphdr); 2705 #endif 2706 } 2707 #ifdef RATELIMIT 2708 if (needs_eo(cst)) { 2709 u_int immhdrs; 2710 2711 /* EO WRs have the headers in the WR and not the GL. */ 2712 immhdrs = m0->m_pkthdr.l2hlen + m0->m_pkthdr.l3hlen + 2713 m0->m_pkthdr.l4hlen; 2714 cflags = 0; 2715 nsegs = count_mbuf_nsegs(m0, immhdrs, &cflags); 2716 MPASS(cflags == mbuf_cflags(m0)); 2717 set_mbuf_eo_nsegs(m0, nsegs); 2718 set_mbuf_eo_len16(m0, 2719 txpkt_eo_len16(nsegs, immhdrs, needs_tso(m0))); 2720 } 2721 #endif 2722 #endif 2723 MPASS(m0 == *mp); 2724 return (0); 2725 } 2726 2727 void * 2728 start_wrq_wr(struct sge_wrq *wrq, int len16, struct wrq_cookie *cookie) 2729 { 2730 struct sge_eq *eq = &wrq->eq; 2731 struct adapter *sc = wrq->adapter; 2732 int ndesc, available; 2733 struct wrqe *wr; 2734 void *w; 2735 2736 MPASS(len16 > 0); 2737 ndesc = howmany(len16, EQ_ESIZE / 16); 2738 MPASS(ndesc > 0 && ndesc <= SGE_MAX_WR_NDESC); 2739 2740 EQ_LOCK(eq); 2741 2742 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 2743 drain_wrq_wr_list(sc, wrq); 2744 2745 if (!STAILQ_EMPTY(&wrq->wr_list)) { 2746 slowpath: 2747 EQ_UNLOCK(eq); 2748 wr = alloc_wrqe(len16 * 16, wrq); 2749 if (__predict_false(wr == NULL)) 2750 return (NULL); 2751 cookie->pidx = -1; 2752 cookie->ndesc = ndesc; 2753 return (&wr->wr); 2754 } 2755 2756 eq->cidx = read_hw_cidx(eq); 2757 if (eq->pidx == eq->cidx) 2758 available = eq->sidx - 1; 2759 else 2760 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2761 if (available < ndesc) 2762 goto slowpath; 2763 2764 cookie->pidx = eq->pidx; 2765 cookie->ndesc = ndesc; 2766 TAILQ_INSERT_TAIL(&wrq->incomplete_wrs, cookie, link); 2767 2768 w = &eq->desc[eq->pidx]; 2769 IDXINCR(eq->pidx, ndesc, eq->sidx); 2770 if (__predict_false(cookie->pidx + ndesc > eq->sidx)) { 2771 w = &wrq->ss[0]; 2772 wrq->ss_pidx = cookie->pidx; 2773 wrq->ss_len = len16 * 16; 2774 } 2775 2776 EQ_UNLOCK(eq); 2777 2778 return (w); 2779 } 2780 2781 void 2782 commit_wrq_wr(struct sge_wrq *wrq, void *w, struct wrq_cookie *cookie) 2783 { 2784 struct sge_eq *eq = &wrq->eq; 2785 struct adapter *sc = wrq->adapter; 2786 int ndesc, pidx; 2787 struct wrq_cookie *prev, *next; 2788 2789 if (cookie->pidx == -1) { 2790 struct wrqe *wr = __containerof(w, struct wrqe, wr); 2791 2792 t4_wrq_tx(sc, wr); 2793 return; 2794 } 2795 2796 if (__predict_false(w == &wrq->ss[0])) { 2797 int n = (eq->sidx - wrq->ss_pidx) * EQ_ESIZE; 2798 2799 MPASS(wrq->ss_len > n); /* WR had better wrap around. */ 2800 bcopy(&wrq->ss[0], &eq->desc[wrq->ss_pidx], n); 2801 bcopy(&wrq->ss[n], &eq->desc[0], wrq->ss_len - n); 2802 wrq->tx_wrs_ss++; 2803 } else 2804 wrq->tx_wrs_direct++; 2805 2806 EQ_LOCK(eq); 2807 ndesc = cookie->ndesc; /* Can be more than SGE_MAX_WR_NDESC here. */ 2808 pidx = cookie->pidx; 2809 MPASS(pidx >= 0 && pidx < eq->sidx); 2810 prev = TAILQ_PREV(cookie, wrq_incomplete_wrs, link); 2811 next = TAILQ_NEXT(cookie, link); 2812 if (prev == NULL) { 2813 MPASS(pidx == eq->dbidx); 2814 if (next == NULL || ndesc >= 16) { 2815 int available; 2816 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */ 2817 2818 /* 2819 * Note that the WR via which we'll request tx updates 2820 * is at pidx and not eq->pidx, which has moved on 2821 * already. 2822 */ 2823 dst = (void *)&eq->desc[pidx]; 2824 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2825 if (available < eq->sidx / 4 && 2826 atomic_cmpset_int(&eq->equiq, 0, 1)) { 2827 /* 2828 * XXX: This is not 100% reliable with some 2829 * types of WRs. But this is a very unusual 2830 * situation for an ofld/ctrl queue anyway. 2831 */ 2832 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ | 2833 F_FW_WR_EQUEQ); 2834 } 2835 2836 ring_eq_db(wrq->adapter, eq, ndesc); 2837 } else { 2838 MPASS(IDXDIFF(next->pidx, pidx, eq->sidx) == ndesc); 2839 next->pidx = pidx; 2840 next->ndesc += ndesc; 2841 } 2842 } else { 2843 MPASS(IDXDIFF(pidx, prev->pidx, eq->sidx) == prev->ndesc); 2844 prev->ndesc += ndesc; 2845 } 2846 TAILQ_REMOVE(&wrq->incomplete_wrs, cookie, link); 2847 2848 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 2849 drain_wrq_wr_list(sc, wrq); 2850 2851 #ifdef INVARIANTS 2852 if (TAILQ_EMPTY(&wrq->incomplete_wrs)) { 2853 /* Doorbell must have caught up to the pidx. */ 2854 MPASS(wrq->eq.pidx == wrq->eq.dbidx); 2855 } 2856 #endif 2857 EQ_UNLOCK(eq); 2858 } 2859 2860 static u_int 2861 can_resume_eth_tx(struct mp_ring *r) 2862 { 2863 struct sge_eq *eq = r->cookie; 2864 2865 return (total_available_tx_desc(eq) > eq->sidx / 8); 2866 } 2867 2868 static inline int 2869 cannot_use_txpkts(struct mbuf *m) 2870 { 2871 /* maybe put a GL limit too, to avoid silliness? */ 2872 2873 return (needs_tso(m) || (mbuf_cflags(m) & (MC_RAW_WR | MC_TLS)) != 0); 2874 } 2875 2876 static inline int 2877 discard_tx(struct sge_eq *eq) 2878 { 2879 2880 return ((eq->flags & (EQ_ENABLED | EQ_QFLUSH)) != EQ_ENABLED); 2881 } 2882 2883 static inline int 2884 wr_can_update_eq(struct fw_eth_tx_pkts_wr *wr) 2885 { 2886 2887 switch (G_FW_WR_OP(be32toh(wr->op_pkd))) { 2888 case FW_ULPTX_WR: 2889 case FW_ETH_TX_PKT_WR: 2890 case FW_ETH_TX_PKTS_WR: 2891 case FW_ETH_TX_PKTS2_WR: 2892 case FW_ETH_TX_PKT_VM_WR: 2893 return (1); 2894 default: 2895 return (0); 2896 } 2897 } 2898 2899 /* 2900 * r->items[cidx] to r->items[pidx], with a wraparound at r->size, are ready to 2901 * be consumed. Return the actual number consumed. 0 indicates a stall. 2902 */ 2903 static u_int 2904 eth_tx(struct mp_ring *r, u_int cidx, u_int pidx) 2905 { 2906 struct sge_txq *txq = r->cookie; 2907 struct sge_eq *eq = &txq->eq; 2908 struct ifnet *ifp = txq->ifp; 2909 struct vi_info *vi = ifp->if_softc; 2910 struct port_info *pi = vi->pi; 2911 struct adapter *sc = pi->adapter; 2912 u_int total, remaining; /* # of packets */ 2913 u_int available, dbdiff; /* # of hardware descriptors */ 2914 u_int n, next_cidx; 2915 struct mbuf *m0, *tail; 2916 struct txpkts txp; 2917 struct fw_eth_tx_pkts_wr *wr; /* any fw WR struct will do */ 2918 2919 remaining = IDXDIFF(pidx, cidx, r->size); 2920 MPASS(remaining > 0); /* Must not be called without work to do. */ 2921 total = 0; 2922 2923 TXQ_LOCK(txq); 2924 if (__predict_false(discard_tx(eq))) { 2925 while (cidx != pidx) { 2926 m0 = r->items[cidx]; 2927 m_freem(m0); 2928 if (++cidx == r->size) 2929 cidx = 0; 2930 } 2931 reclaim_tx_descs(txq, 2048); 2932 total = remaining; 2933 goto done; 2934 } 2935 2936 /* How many hardware descriptors do we have readily available. */ 2937 if (eq->pidx == eq->cidx) 2938 available = eq->sidx - 1; 2939 else 2940 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2941 dbdiff = IDXDIFF(eq->pidx, eq->dbidx, eq->sidx); 2942 2943 while (remaining > 0) { 2944 2945 m0 = r->items[cidx]; 2946 M_ASSERTPKTHDR(m0); 2947 MPASS(m0->m_nextpkt == NULL); 2948 2949 if (available < howmany(mbuf_len16(m0), EQ_ESIZE / 16)) { 2950 MPASS(howmany(mbuf_len16(m0), EQ_ESIZE / 16) <= 64); 2951 available += reclaim_tx_descs(txq, 64); 2952 if (available < howmany(mbuf_len16(m0), EQ_ESIZE / 16)) 2953 break; /* out of descriptors */ 2954 } 2955 2956 next_cidx = cidx + 1; 2957 if (__predict_false(next_cidx == r->size)) 2958 next_cidx = 0; 2959 2960 wr = (void *)&eq->desc[eq->pidx]; 2961 if (mbuf_cflags(m0) & MC_RAW_WR) { 2962 total++; 2963 remaining--; 2964 n = write_raw_wr(txq, (void *)wr, m0, available); 2965 #ifdef KERN_TLS 2966 } else if (mbuf_cflags(m0) & MC_TLS) { 2967 total++; 2968 remaining--; 2969 ETHER_BPF_MTAP(ifp, m0); 2970 n = t6_ktls_write_wr(txq,(void *)wr, m0, 2971 mbuf_nsegs(m0), available); 2972 #endif 2973 } else if (sc->flags & IS_VF) { 2974 total++; 2975 remaining--; 2976 ETHER_BPF_MTAP(ifp, m0); 2977 n = write_txpkt_vm_wr(sc, txq, (void *)wr, m0, 2978 available); 2979 } else if (remaining > 1 && 2980 try_txpkts(m0, r->items[next_cidx], &txp, available) == 0) { 2981 2982 /* pkts at cidx, next_cidx should both be in txp. */ 2983 MPASS(txp.npkt == 2); 2984 tail = r->items[next_cidx]; 2985 MPASS(tail->m_nextpkt == NULL); 2986 ETHER_BPF_MTAP(ifp, m0); 2987 ETHER_BPF_MTAP(ifp, tail); 2988 m0->m_nextpkt = tail; 2989 2990 if (__predict_false(++next_cidx == r->size)) 2991 next_cidx = 0; 2992 2993 while (next_cidx != pidx) { 2994 if (add_to_txpkts(r->items[next_cidx], &txp, 2995 available) != 0) 2996 break; 2997 tail->m_nextpkt = r->items[next_cidx]; 2998 tail = tail->m_nextpkt; 2999 ETHER_BPF_MTAP(ifp, tail); 3000 if (__predict_false(++next_cidx == r->size)) 3001 next_cidx = 0; 3002 } 3003 3004 n = write_txpkts_wr(sc, txq, wr, m0, &txp, available); 3005 total += txp.npkt; 3006 remaining -= txp.npkt; 3007 } else { 3008 total++; 3009 remaining--; 3010 ETHER_BPF_MTAP(ifp, m0); 3011 n = write_txpkt_wr(sc, txq, (void *)wr, m0, available); 3012 } 3013 MPASS(n >= 1 && n <= available); 3014 if (!(mbuf_cflags(m0) & MC_TLS)) 3015 MPASS(n <= SGE_MAX_WR_NDESC); 3016 3017 available -= n; 3018 dbdiff += n; 3019 IDXINCR(eq->pidx, n, eq->sidx); 3020 3021 if (wr_can_update_eq(wr)) { 3022 if (total_available_tx_desc(eq) < eq->sidx / 4 && 3023 atomic_cmpset_int(&eq->equiq, 0, 1)) { 3024 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ | 3025 F_FW_WR_EQUEQ); 3026 eq->equeqidx = eq->pidx; 3027 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 3028 32) { 3029 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ); 3030 eq->equeqidx = eq->pidx; 3031 } 3032 } 3033 3034 if (dbdiff >= 16 && remaining >= 4) { 3035 ring_eq_db(sc, eq, dbdiff); 3036 available += reclaim_tx_descs(txq, 4 * dbdiff); 3037 dbdiff = 0; 3038 } 3039 3040 cidx = next_cidx; 3041 } 3042 if (dbdiff != 0) { 3043 ring_eq_db(sc, eq, dbdiff); 3044 reclaim_tx_descs(txq, 32); 3045 } 3046 done: 3047 TXQ_UNLOCK(txq); 3048 3049 return (total); 3050 } 3051 3052 static inline void 3053 init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int pktc_idx, 3054 int qsize) 3055 { 3056 3057 KASSERT(tmr_idx >= 0 && tmr_idx < SGE_NTIMERS, 3058 ("%s: bad tmr_idx %d", __func__, tmr_idx)); 3059 KASSERT(pktc_idx < SGE_NCOUNTERS, /* -ve is ok, means don't use */ 3060 ("%s: bad pktc_idx %d", __func__, pktc_idx)); 3061 3062 iq->flags = 0; 3063 iq->adapter = sc; 3064 iq->intr_params = V_QINTR_TIMER_IDX(tmr_idx); 3065 iq->intr_pktc_idx = SGE_NCOUNTERS - 1; 3066 if (pktc_idx >= 0) { 3067 iq->intr_params |= F_QINTR_CNT_EN; 3068 iq->intr_pktc_idx = pktc_idx; 3069 } 3070 iq->qsize = roundup2(qsize, 16); /* See FW_IQ_CMD/iqsize */ 3071 iq->sidx = iq->qsize - sc->params.sge.spg_len / IQ_ESIZE; 3072 } 3073 3074 static inline void 3075 init_fl(struct adapter *sc, struct sge_fl *fl, int qsize, int maxp, char *name) 3076 { 3077 3078 fl->qsize = qsize; 3079 fl->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE; 3080 strlcpy(fl->lockname, name, sizeof(fl->lockname)); 3081 if (sc->flags & BUF_PACKING_OK && 3082 ((!is_t4(sc) && buffer_packing) || /* T5+: enabled unless 0 */ 3083 (is_t4(sc) && buffer_packing == 1)))/* T4: disabled unless 1 */ 3084 fl->flags |= FL_BUF_PACKING; 3085 find_best_refill_source(sc, fl, maxp); 3086 find_safe_refill_source(sc, fl); 3087 } 3088 3089 static inline void 3090 init_eq(struct adapter *sc, struct sge_eq *eq, int eqtype, int qsize, 3091 uint8_t tx_chan, uint16_t iqid, char *name) 3092 { 3093 KASSERT(eqtype <= EQ_TYPEMASK, ("%s: bad qtype %d", __func__, eqtype)); 3094 3095 eq->flags = eqtype & EQ_TYPEMASK; 3096 eq->tx_chan = tx_chan; 3097 eq->iqid = iqid; 3098 eq->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE; 3099 strlcpy(eq->lockname, name, sizeof(eq->lockname)); 3100 } 3101 3102 static int 3103 alloc_ring(struct adapter *sc, size_t len, bus_dma_tag_t *tag, 3104 bus_dmamap_t *map, bus_addr_t *pa, void **va) 3105 { 3106 int rc; 3107 3108 rc = bus_dma_tag_create(sc->dmat, 512, 0, BUS_SPACE_MAXADDR, 3109 BUS_SPACE_MAXADDR, NULL, NULL, len, 1, len, 0, NULL, NULL, tag); 3110 if (rc != 0) { 3111 device_printf(sc->dev, "cannot allocate DMA tag: %d\n", rc); 3112 goto done; 3113 } 3114 3115 rc = bus_dmamem_alloc(*tag, va, 3116 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, map); 3117 if (rc != 0) { 3118 device_printf(sc->dev, "cannot allocate DMA memory: %d\n", rc); 3119 goto done; 3120 } 3121 3122 rc = bus_dmamap_load(*tag, *map, *va, len, oneseg_dma_callback, pa, 0); 3123 if (rc != 0) { 3124 device_printf(sc->dev, "cannot load DMA map: %d\n", rc); 3125 goto done; 3126 } 3127 done: 3128 if (rc) 3129 free_ring(sc, *tag, *map, *pa, *va); 3130 3131 return (rc); 3132 } 3133 3134 static int 3135 free_ring(struct adapter *sc, bus_dma_tag_t tag, bus_dmamap_t map, 3136 bus_addr_t pa, void *va) 3137 { 3138 if (pa) 3139 bus_dmamap_unload(tag, map); 3140 if (va) 3141 bus_dmamem_free(tag, va, map); 3142 if (tag) 3143 bus_dma_tag_destroy(tag); 3144 3145 return (0); 3146 } 3147 3148 /* 3149 * Allocates the ring for an ingress queue and an optional freelist. If the 3150 * freelist is specified it will be allocated and then associated with the 3151 * ingress queue. 3152 * 3153 * Returns errno on failure. Resources allocated up to that point may still be 3154 * allocated. Caller is responsible for cleanup in case this function fails. 3155 * 3156 * If the ingress queue will take interrupts directly then the intr_idx 3157 * specifies the vector, starting from 0. -1 means the interrupts for this 3158 * queue should be forwarded to the fwq. 3159 */ 3160 static int 3161 alloc_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl, 3162 int intr_idx, int cong) 3163 { 3164 int rc, i, cntxt_id; 3165 size_t len; 3166 struct fw_iq_cmd c; 3167 struct port_info *pi = vi->pi; 3168 struct adapter *sc = iq->adapter; 3169 struct sge_params *sp = &sc->params.sge; 3170 __be32 v = 0; 3171 3172 len = iq->qsize * IQ_ESIZE; 3173 rc = alloc_ring(sc, len, &iq->desc_tag, &iq->desc_map, &iq->ba, 3174 (void **)&iq->desc); 3175 if (rc != 0) 3176 return (rc); 3177 3178 bzero(&c, sizeof(c)); 3179 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 3180 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) | 3181 V_FW_IQ_CMD_VFN(0)); 3182 3183 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART | 3184 FW_LEN16(c)); 3185 3186 /* Special handling for firmware event queue */ 3187 if (iq == &sc->sge.fwq) 3188 v |= F_FW_IQ_CMD_IQASYNCH; 3189 3190 if (intr_idx < 0) { 3191 /* Forwarded interrupts, all headed to fwq */ 3192 v |= F_FW_IQ_CMD_IQANDST; 3193 v |= V_FW_IQ_CMD_IQANDSTINDEX(sc->sge.fwq.cntxt_id); 3194 } else { 3195 KASSERT(intr_idx < sc->intr_count, 3196 ("%s: invalid direct intr_idx %d", __func__, intr_idx)); 3197 v |= V_FW_IQ_CMD_IQANDSTINDEX(intr_idx); 3198 } 3199 3200 c.type_to_iqandstindex = htobe32(v | 3201 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) | 3202 V_FW_IQ_CMD_VIID(vi->viid) | 3203 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT)); 3204 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->tx_chan) | 3205 F_FW_IQ_CMD_IQGTSMODE | 3206 V_FW_IQ_CMD_IQINTCNTTHRESH(iq->intr_pktc_idx) | 3207 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4)); 3208 c.iqsize = htobe16(iq->qsize); 3209 c.iqaddr = htobe64(iq->ba); 3210 if (cong >= 0) 3211 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN); 3212 3213 if (fl) { 3214 mtx_init(&fl->fl_lock, fl->lockname, NULL, MTX_DEF); 3215 3216 len = fl->qsize * EQ_ESIZE; 3217 rc = alloc_ring(sc, len, &fl->desc_tag, &fl->desc_map, 3218 &fl->ba, (void **)&fl->desc); 3219 if (rc) 3220 return (rc); 3221 3222 /* Allocate space for one software descriptor per buffer. */ 3223 rc = alloc_fl_sdesc(fl); 3224 if (rc != 0) { 3225 device_printf(sc->dev, 3226 "failed to setup fl software descriptors: %d\n", 3227 rc); 3228 return (rc); 3229 } 3230 3231 if (fl->flags & FL_BUF_PACKING) { 3232 fl->lowat = roundup2(sp->fl_starve_threshold2, 8); 3233 fl->buf_boundary = sp->pack_boundary; 3234 } else { 3235 fl->lowat = roundup2(sp->fl_starve_threshold, 8); 3236 fl->buf_boundary = 16; 3237 } 3238 if (fl_pad && fl->buf_boundary < sp->pad_boundary) 3239 fl->buf_boundary = sp->pad_boundary; 3240 3241 c.iqns_to_fl0congen |= 3242 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) | 3243 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO | 3244 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) | 3245 (fl->flags & FL_BUF_PACKING ? F_FW_IQ_CMD_FL0PACKEN : 3246 0)); 3247 if (cong >= 0) { 3248 c.iqns_to_fl0congen |= 3249 htobe32(V_FW_IQ_CMD_FL0CNGCHMAP(cong) | 3250 F_FW_IQ_CMD_FL0CONGCIF | 3251 F_FW_IQ_CMD_FL0CONGEN); 3252 } 3253 c.fl0dcaen_to_fl0cidxfthresh = 3254 htobe16(V_FW_IQ_CMD_FL0FBMIN(chip_id(sc) <= CHELSIO_T5 ? 3255 X_FETCHBURSTMIN_128B : X_FETCHBURSTMIN_64B_T6) | 3256 V_FW_IQ_CMD_FL0FBMAX(chip_id(sc) <= CHELSIO_T5 ? 3257 X_FETCHBURSTMAX_512B : X_FETCHBURSTMAX_256B)); 3258 c.fl0size = htobe16(fl->qsize); 3259 c.fl0addr = htobe64(fl->ba); 3260 } 3261 3262 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3263 if (rc != 0) { 3264 device_printf(sc->dev, 3265 "failed to create ingress queue: %d\n", rc); 3266 return (rc); 3267 } 3268 3269 iq->cidx = 0; 3270 iq->gen = F_RSPD_GEN; 3271 iq->intr_next = iq->intr_params; 3272 iq->cntxt_id = be16toh(c.iqid); 3273 iq->abs_id = be16toh(c.physiqid); 3274 iq->flags |= IQ_ALLOCATED; 3275 3276 cntxt_id = iq->cntxt_id - sc->sge.iq_start; 3277 if (cntxt_id >= sc->sge.niq) { 3278 panic ("%s: iq->cntxt_id (%d) more than the max (%d)", __func__, 3279 cntxt_id, sc->sge.niq - 1); 3280 } 3281 sc->sge.iqmap[cntxt_id] = iq; 3282 3283 if (fl) { 3284 u_int qid; 3285 3286 iq->flags |= IQ_HAS_FL; 3287 fl->cntxt_id = be16toh(c.fl0id); 3288 fl->pidx = fl->cidx = 0; 3289 3290 cntxt_id = fl->cntxt_id - sc->sge.eq_start; 3291 if (cntxt_id >= sc->sge.neq) { 3292 panic("%s: fl->cntxt_id (%d) more than the max (%d)", 3293 __func__, cntxt_id, sc->sge.neq - 1); 3294 } 3295 sc->sge.eqmap[cntxt_id] = (void *)fl; 3296 3297 qid = fl->cntxt_id; 3298 if (isset(&sc->doorbells, DOORBELL_UDB)) { 3299 uint32_t s_qpp = sc->params.sge.eq_s_qpp; 3300 uint32_t mask = (1 << s_qpp) - 1; 3301 volatile uint8_t *udb; 3302 3303 udb = sc->udbs_base + UDBS_DB_OFFSET; 3304 udb += (qid >> s_qpp) << PAGE_SHIFT; 3305 qid &= mask; 3306 if (qid < PAGE_SIZE / UDBS_SEG_SIZE) { 3307 udb += qid << UDBS_SEG_SHIFT; 3308 qid = 0; 3309 } 3310 fl->udb = (volatile void *)udb; 3311 } 3312 fl->dbval = V_QID(qid) | sc->chip_params->sge_fl_db; 3313 3314 FL_LOCK(fl); 3315 /* Enough to make sure the SGE doesn't think it's starved */ 3316 refill_fl(sc, fl, fl->lowat); 3317 FL_UNLOCK(fl); 3318 } 3319 3320 if (chip_id(sc) >= CHELSIO_T5 && !(sc->flags & IS_VF) && cong >= 0) { 3321 uint32_t param, val; 3322 3323 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 3324 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) | 3325 V_FW_PARAMS_PARAM_YZ(iq->cntxt_id); 3326 if (cong == 0) 3327 val = 1 << 19; 3328 else { 3329 val = 2 << 19; 3330 for (i = 0; i < 4; i++) { 3331 if (cong & (1 << i)) 3332 val |= 1 << (i << 2); 3333 } 3334 } 3335 3336 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 3337 if (rc != 0) { 3338 /* report error but carry on */ 3339 device_printf(sc->dev, 3340 "failed to set congestion manager context for " 3341 "ingress queue %d: %d\n", iq->cntxt_id, rc); 3342 } 3343 } 3344 3345 /* Enable IQ interrupts */ 3346 atomic_store_rel_int(&iq->state, IQS_IDLE); 3347 t4_write_reg(sc, sc->sge_gts_reg, V_SEINTARM(iq->intr_params) | 3348 V_INGRESSQID(iq->cntxt_id)); 3349 3350 return (0); 3351 } 3352 3353 static int 3354 free_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl) 3355 { 3356 int rc; 3357 struct adapter *sc = iq->adapter; 3358 device_t dev; 3359 3360 if (sc == NULL) 3361 return (0); /* nothing to do */ 3362 3363 dev = vi ? vi->dev : sc->dev; 3364 3365 if (iq->flags & IQ_ALLOCATED) { 3366 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0, 3367 FW_IQ_TYPE_FL_INT_CAP, iq->cntxt_id, 3368 fl ? fl->cntxt_id : 0xffff, 0xffff); 3369 if (rc != 0) { 3370 device_printf(dev, 3371 "failed to free queue %p: %d\n", iq, rc); 3372 return (rc); 3373 } 3374 iq->flags &= ~IQ_ALLOCATED; 3375 } 3376 3377 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, iq->desc); 3378 3379 bzero(iq, sizeof(*iq)); 3380 3381 if (fl) { 3382 free_ring(sc, fl->desc_tag, fl->desc_map, fl->ba, 3383 fl->desc); 3384 3385 if (fl->sdesc) 3386 free_fl_sdesc(sc, fl); 3387 3388 if (mtx_initialized(&fl->fl_lock)) 3389 mtx_destroy(&fl->fl_lock); 3390 3391 bzero(fl, sizeof(*fl)); 3392 } 3393 3394 return (0); 3395 } 3396 3397 static void 3398 add_iq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid, 3399 struct sge_iq *iq) 3400 { 3401 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3402 3403 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, &iq->ba, 3404 "bus address of descriptor ring"); 3405 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3406 iq->qsize * IQ_ESIZE, "descriptor ring size in bytes"); 3407 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "abs_id", 3408 CTLTYPE_INT | CTLFLAG_RD, &iq->abs_id, 0, sysctl_uint16, "I", 3409 "absolute id of the queue"); 3410 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 3411 CTLTYPE_INT | CTLFLAG_RD, &iq->cntxt_id, 0, sysctl_uint16, "I", 3412 "SGE context id of the queue"); 3413 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx", 3414 CTLTYPE_INT | CTLFLAG_RD, &iq->cidx, 0, sysctl_uint16, "I", 3415 "consumer index"); 3416 } 3417 3418 static void 3419 add_fl_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx, 3420 struct sysctl_oid *oid, struct sge_fl *fl) 3421 { 3422 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3423 3424 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL, 3425 "freelist"); 3426 children = SYSCTL_CHILDREN(oid); 3427 3428 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, 3429 &fl->ba, "bus address of descriptor ring"); 3430 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3431 fl->sidx * EQ_ESIZE + sc->params.sge.spg_len, 3432 "desc ring size in bytes"); 3433 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 3434 CTLTYPE_INT | CTLFLAG_RD, &fl->cntxt_id, 0, sysctl_uint16, "I", 3435 "SGE context id of the freelist"); 3436 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "padding", CTLFLAG_RD, NULL, 3437 fl_pad ? 1 : 0, "padding enabled"); 3438 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "packing", CTLFLAG_RD, NULL, 3439 fl->flags & FL_BUF_PACKING ? 1 : 0, "packing enabled"); 3440 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &fl->cidx, 3441 0, "consumer index"); 3442 if (fl->flags & FL_BUF_PACKING) { 3443 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rx_offset", 3444 CTLFLAG_RD, &fl->rx_offset, 0, "packing rx offset"); 3445 } 3446 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &fl->pidx, 3447 0, "producer index"); 3448 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_allocated", 3449 CTLFLAG_RD, &fl->mbuf_allocated, "# of mbuf allocated"); 3450 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_inlined", 3451 CTLFLAG_RD, &fl->mbuf_inlined, "# of mbuf inlined in clusters"); 3452 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_allocated", 3453 CTLFLAG_RD, &fl->cl_allocated, "# of clusters allocated"); 3454 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_recycled", 3455 CTLFLAG_RD, &fl->cl_recycled, "# of clusters recycled"); 3456 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_fast_recycled", 3457 CTLFLAG_RD, &fl->cl_fast_recycled, "# of clusters recycled (fast)"); 3458 } 3459 3460 static int 3461 alloc_fwq(struct adapter *sc) 3462 { 3463 int rc, intr_idx; 3464 struct sge_iq *fwq = &sc->sge.fwq; 3465 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev); 3466 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3467 3468 init_iq(fwq, sc, 0, 0, FW_IQ_QSIZE); 3469 if (sc->flags & IS_VF) 3470 intr_idx = 0; 3471 else 3472 intr_idx = sc->intr_count > 1 ? 1 : 0; 3473 rc = alloc_iq_fl(&sc->port[0]->vi[0], fwq, NULL, intr_idx, -1); 3474 if (rc != 0) { 3475 device_printf(sc->dev, 3476 "failed to create firmware event queue: %d\n", rc); 3477 return (rc); 3478 } 3479 3480 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "fwq", CTLFLAG_RD, 3481 NULL, "firmware event queue"); 3482 add_iq_sysctls(&sc->ctx, oid, fwq); 3483 3484 return (0); 3485 } 3486 3487 static int 3488 free_fwq(struct adapter *sc) 3489 { 3490 return free_iq_fl(NULL, &sc->sge.fwq, NULL); 3491 } 3492 3493 static int 3494 alloc_ctrlq(struct adapter *sc, struct sge_wrq *ctrlq, int idx, 3495 struct sysctl_oid *oid) 3496 { 3497 int rc; 3498 char name[16]; 3499 struct sysctl_oid_list *children; 3500 3501 snprintf(name, sizeof(name), "%s ctrlq%d", device_get_nameunit(sc->dev), 3502 idx); 3503 init_eq(sc, &ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE, sc->port[idx]->tx_chan, 3504 sc->sge.fwq.cntxt_id, name); 3505 3506 children = SYSCTL_CHILDREN(oid); 3507 snprintf(name, sizeof(name), "%d", idx); 3508 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, name, CTLFLAG_RD, 3509 NULL, "ctrl queue"); 3510 rc = alloc_wrq(sc, NULL, ctrlq, oid); 3511 3512 return (rc); 3513 } 3514 3515 int 3516 tnl_cong(struct port_info *pi, int drop) 3517 { 3518 3519 if (drop == -1) 3520 return (-1); 3521 else if (drop == 1) 3522 return (0); 3523 else 3524 return (pi->rx_e_chan_map); 3525 } 3526 3527 static int 3528 alloc_rxq(struct vi_info *vi, struct sge_rxq *rxq, int intr_idx, int idx, 3529 struct sysctl_oid *oid) 3530 { 3531 int rc; 3532 struct adapter *sc = vi->pi->adapter; 3533 struct sysctl_oid_list *children; 3534 char name[16]; 3535 3536 rc = alloc_iq_fl(vi, &rxq->iq, &rxq->fl, intr_idx, 3537 tnl_cong(vi->pi, cong_drop)); 3538 if (rc != 0) 3539 return (rc); 3540 3541 if (idx == 0) 3542 sc->sge.iq_base = rxq->iq.abs_id - rxq->iq.cntxt_id; 3543 else 3544 KASSERT(rxq->iq.cntxt_id + sc->sge.iq_base == rxq->iq.abs_id, 3545 ("iq_base mismatch")); 3546 KASSERT(sc->sge.iq_base == 0 || sc->flags & IS_VF, 3547 ("PF with non-zero iq_base")); 3548 3549 /* 3550 * The freelist is just barely above the starvation threshold right now, 3551 * fill it up a bit more. 3552 */ 3553 FL_LOCK(&rxq->fl); 3554 refill_fl(sc, &rxq->fl, 128); 3555 FL_UNLOCK(&rxq->fl); 3556 3557 #if defined(INET) || defined(INET6) 3558 rc = tcp_lro_init_args(&rxq->lro, vi->ifp, lro_entries, lro_mbufs); 3559 if (rc != 0) 3560 return (rc); 3561 MPASS(rxq->lro.ifp == vi->ifp); /* also indicates LRO init'ed */ 3562 3563 if (vi->ifp->if_capenable & IFCAP_LRO) 3564 rxq->iq.flags |= IQ_LRO_ENABLED; 3565 #endif 3566 if (vi->ifp->if_capenable & IFCAP_HWRXTSTMP) 3567 rxq->iq.flags |= IQ_RX_TIMESTAMP; 3568 rxq->ifp = vi->ifp; 3569 3570 children = SYSCTL_CHILDREN(oid); 3571 3572 snprintf(name, sizeof(name), "%d", idx); 3573 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 3574 NULL, "rx queue"); 3575 children = SYSCTL_CHILDREN(oid); 3576 3577 add_iq_sysctls(&vi->ctx, oid, &rxq->iq); 3578 #if defined(INET) || defined(INET6) 3579 SYSCTL_ADD_U64(&vi->ctx, children, OID_AUTO, "lro_queued", CTLFLAG_RD, 3580 &rxq->lro.lro_queued, 0, NULL); 3581 SYSCTL_ADD_U64(&vi->ctx, children, OID_AUTO, "lro_flushed", CTLFLAG_RD, 3582 &rxq->lro.lro_flushed, 0, NULL); 3583 #endif 3584 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "rxcsum", CTLFLAG_RD, 3585 &rxq->rxcsum, "# of times hardware assisted with checksum"); 3586 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_extraction", 3587 CTLFLAG_RD, &rxq->vlan_extraction, 3588 "# of times hardware extracted 802.1Q tag"); 3589 3590 add_fl_sysctls(sc, &vi->ctx, oid, &rxq->fl); 3591 3592 return (rc); 3593 } 3594 3595 static int 3596 free_rxq(struct vi_info *vi, struct sge_rxq *rxq) 3597 { 3598 int rc; 3599 3600 #if defined(INET) || defined(INET6) 3601 if (rxq->lro.ifp) { 3602 tcp_lro_free(&rxq->lro); 3603 rxq->lro.ifp = NULL; 3604 } 3605 #endif 3606 3607 rc = free_iq_fl(vi, &rxq->iq, &rxq->fl); 3608 if (rc == 0) 3609 bzero(rxq, sizeof(*rxq)); 3610 3611 return (rc); 3612 } 3613 3614 #ifdef TCP_OFFLOAD 3615 static int 3616 alloc_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq, 3617 int intr_idx, int idx, struct sysctl_oid *oid) 3618 { 3619 struct port_info *pi = vi->pi; 3620 int rc; 3621 struct sysctl_oid_list *children; 3622 char name[16]; 3623 3624 rc = alloc_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl, intr_idx, 0); 3625 if (rc != 0) 3626 return (rc); 3627 3628 children = SYSCTL_CHILDREN(oid); 3629 3630 snprintf(name, sizeof(name), "%d", idx); 3631 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 3632 NULL, "rx queue"); 3633 add_iq_sysctls(&vi->ctx, oid, &ofld_rxq->iq); 3634 add_fl_sysctls(pi->adapter, &vi->ctx, oid, &ofld_rxq->fl); 3635 3636 return (rc); 3637 } 3638 3639 static int 3640 free_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq) 3641 { 3642 int rc; 3643 3644 rc = free_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl); 3645 if (rc == 0) 3646 bzero(ofld_rxq, sizeof(*ofld_rxq)); 3647 3648 return (rc); 3649 } 3650 #endif 3651 3652 #ifdef DEV_NETMAP 3653 static int 3654 alloc_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq, int intr_idx, 3655 int idx, struct sysctl_oid *oid) 3656 { 3657 int rc; 3658 struct sysctl_oid_list *children; 3659 struct sysctl_ctx_list *ctx; 3660 char name[16]; 3661 size_t len; 3662 struct adapter *sc = vi->pi->adapter; 3663 struct netmap_adapter *na = NA(vi->ifp); 3664 3665 MPASS(na != NULL); 3666 3667 len = vi->qsize_rxq * IQ_ESIZE; 3668 rc = alloc_ring(sc, len, &nm_rxq->iq_desc_tag, &nm_rxq->iq_desc_map, 3669 &nm_rxq->iq_ba, (void **)&nm_rxq->iq_desc); 3670 if (rc != 0) 3671 return (rc); 3672 3673 len = na->num_rx_desc * EQ_ESIZE + sc->params.sge.spg_len; 3674 rc = alloc_ring(sc, len, &nm_rxq->fl_desc_tag, &nm_rxq->fl_desc_map, 3675 &nm_rxq->fl_ba, (void **)&nm_rxq->fl_desc); 3676 if (rc != 0) 3677 return (rc); 3678 3679 nm_rxq->vi = vi; 3680 nm_rxq->nid = idx; 3681 nm_rxq->iq_cidx = 0; 3682 nm_rxq->iq_sidx = vi->qsize_rxq - sc->params.sge.spg_len / IQ_ESIZE; 3683 nm_rxq->iq_gen = F_RSPD_GEN; 3684 nm_rxq->fl_pidx = nm_rxq->fl_cidx = 0; 3685 nm_rxq->fl_sidx = na->num_rx_desc; 3686 nm_rxq->intr_idx = intr_idx; 3687 nm_rxq->iq_cntxt_id = INVALID_NM_RXQ_CNTXT_ID; 3688 3689 ctx = &vi->ctx; 3690 children = SYSCTL_CHILDREN(oid); 3691 3692 snprintf(name, sizeof(name), "%d", idx); 3693 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, name, CTLFLAG_RD, NULL, 3694 "rx queue"); 3695 children = SYSCTL_CHILDREN(oid); 3696 3697 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "abs_id", 3698 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_abs_id, 0, sysctl_uint16, 3699 "I", "absolute id of the queue"); 3700 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 3701 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cntxt_id, 0, sysctl_uint16, 3702 "I", "SGE context id of the queue"); 3703 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx", 3704 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cidx, 0, sysctl_uint16, "I", 3705 "consumer index"); 3706 3707 children = SYSCTL_CHILDREN(oid); 3708 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL, 3709 "freelist"); 3710 children = SYSCTL_CHILDREN(oid); 3711 3712 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 3713 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->fl_cntxt_id, 0, sysctl_uint16, 3714 "I", "SGE context id of the freelist"); 3715 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, 3716 &nm_rxq->fl_cidx, 0, "consumer index"); 3717 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, 3718 &nm_rxq->fl_pidx, 0, "producer index"); 3719 3720 return (rc); 3721 } 3722 3723 3724 static int 3725 free_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq) 3726 { 3727 struct adapter *sc = vi->pi->adapter; 3728 3729 if (vi->flags & VI_INIT_DONE) 3730 MPASS(nm_rxq->iq_cntxt_id == INVALID_NM_RXQ_CNTXT_ID); 3731 else 3732 MPASS(nm_rxq->iq_cntxt_id == 0); 3733 3734 free_ring(sc, nm_rxq->iq_desc_tag, nm_rxq->iq_desc_map, nm_rxq->iq_ba, 3735 nm_rxq->iq_desc); 3736 free_ring(sc, nm_rxq->fl_desc_tag, nm_rxq->fl_desc_map, nm_rxq->fl_ba, 3737 nm_rxq->fl_desc); 3738 3739 return (0); 3740 } 3741 3742 static int 3743 alloc_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq, int iqidx, int idx, 3744 struct sysctl_oid *oid) 3745 { 3746 int rc; 3747 size_t len; 3748 struct port_info *pi = vi->pi; 3749 struct adapter *sc = pi->adapter; 3750 struct netmap_adapter *na = NA(vi->ifp); 3751 char name[16]; 3752 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3753 3754 len = na->num_tx_desc * EQ_ESIZE + sc->params.sge.spg_len; 3755 rc = alloc_ring(sc, len, &nm_txq->desc_tag, &nm_txq->desc_map, 3756 &nm_txq->ba, (void **)&nm_txq->desc); 3757 if (rc) 3758 return (rc); 3759 3760 nm_txq->pidx = nm_txq->cidx = 0; 3761 nm_txq->sidx = na->num_tx_desc; 3762 nm_txq->nid = idx; 3763 nm_txq->iqidx = iqidx; 3764 nm_txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) | 3765 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(sc->pf) | 3766 V_TXPKT_VF(vi->vin) | V_TXPKT_VF_VLD(vi->vfvld)); 3767 if (sc->params.fw_vers >= FW_VERSION32(1, 24, 11, 0)) 3768 nm_txq->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS2_WR)); 3769 else 3770 nm_txq->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR)); 3771 nm_txq->cntxt_id = INVALID_NM_TXQ_CNTXT_ID; 3772 3773 snprintf(name, sizeof(name), "%d", idx); 3774 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 3775 NULL, "netmap tx queue"); 3776 children = SYSCTL_CHILDREN(oid); 3777 3778 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 3779 &nm_txq->cntxt_id, 0, "SGE context id of the queue"); 3780 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx", 3781 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->cidx, 0, sysctl_uint16, "I", 3782 "consumer index"); 3783 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "pidx", 3784 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->pidx, 0, sysctl_uint16, "I", 3785 "producer index"); 3786 3787 return (rc); 3788 } 3789 3790 static int 3791 free_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq) 3792 { 3793 struct adapter *sc = vi->pi->adapter; 3794 3795 if (vi->flags & VI_INIT_DONE) 3796 MPASS(nm_txq->cntxt_id == INVALID_NM_TXQ_CNTXT_ID); 3797 else 3798 MPASS(nm_txq->cntxt_id == 0); 3799 3800 free_ring(sc, nm_txq->desc_tag, nm_txq->desc_map, nm_txq->ba, 3801 nm_txq->desc); 3802 3803 return (0); 3804 } 3805 #endif 3806 3807 /* 3808 * Returns a reasonable automatic cidx flush threshold for a given queue size. 3809 */ 3810 static u_int 3811 qsize_to_fthresh(int qsize) 3812 { 3813 u_int fthresh; 3814 3815 while (!powerof2(qsize)) 3816 qsize++; 3817 fthresh = ilog2(qsize); 3818 if (fthresh > X_CIDXFLUSHTHRESH_128) 3819 fthresh = X_CIDXFLUSHTHRESH_128; 3820 3821 return (fthresh); 3822 } 3823 3824 static int 3825 ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq) 3826 { 3827 int rc, cntxt_id; 3828 struct fw_eq_ctrl_cmd c; 3829 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 3830 3831 bzero(&c, sizeof(c)); 3832 3833 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | F_FW_CMD_REQUEST | 3834 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_CTRL_CMD_PFN(sc->pf) | 3835 V_FW_EQ_CTRL_CMD_VFN(0)); 3836 c.alloc_to_len16 = htobe32(F_FW_EQ_CTRL_CMD_ALLOC | 3837 F_FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c)); 3838 c.cmpliqid_eqid = htonl(V_FW_EQ_CTRL_CMD_CMPLIQID(eq->iqid)); 3839 c.physeqid_pkd = htobe32(0); 3840 c.fetchszm_to_iqid = 3841 htobe32(V_FW_EQ_CTRL_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 3842 V_FW_EQ_CTRL_CMD_PCIECHN(eq->tx_chan) | 3843 F_FW_EQ_CTRL_CMD_FETCHRO | V_FW_EQ_CTRL_CMD_IQID(eq->iqid)); 3844 c.dcaen_to_eqsize = 3845 htobe32(V_FW_EQ_CTRL_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ? 3846 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) | 3847 V_FW_EQ_CTRL_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 3848 V_FW_EQ_CTRL_CMD_CIDXFTHRESH(qsize_to_fthresh(qsize)) | 3849 V_FW_EQ_CTRL_CMD_EQSIZE(qsize)); 3850 c.eqaddr = htobe64(eq->ba); 3851 3852 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3853 if (rc != 0) { 3854 device_printf(sc->dev, 3855 "failed to create control queue %d: %d\n", eq->tx_chan, rc); 3856 return (rc); 3857 } 3858 eq->flags |= EQ_ALLOCATED; 3859 3860 eq->cntxt_id = G_FW_EQ_CTRL_CMD_EQID(be32toh(c.cmpliqid_eqid)); 3861 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 3862 if (cntxt_id >= sc->sge.neq) 3863 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 3864 cntxt_id, sc->sge.neq - 1); 3865 sc->sge.eqmap[cntxt_id] = eq; 3866 3867 return (rc); 3868 } 3869 3870 static int 3871 eth_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 3872 { 3873 int rc, cntxt_id; 3874 struct fw_eq_eth_cmd c; 3875 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 3876 3877 bzero(&c, sizeof(c)); 3878 3879 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST | 3880 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) | 3881 V_FW_EQ_ETH_CMD_VFN(0)); 3882 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC | 3883 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c)); 3884 c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE | 3885 F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(vi->viid)); 3886 c.fetchszm_to_iqid = 3887 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) | 3888 V_FW_EQ_ETH_CMD_PCIECHN(eq->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO | 3889 V_FW_EQ_ETH_CMD_IQID(eq->iqid)); 3890 c.dcaen_to_eqsize = 3891 htobe32(V_FW_EQ_ETH_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ? 3892 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) | 3893 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 3894 V_FW_EQ_ETH_CMD_EQSIZE(qsize)); 3895 c.eqaddr = htobe64(eq->ba); 3896 3897 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3898 if (rc != 0) { 3899 device_printf(vi->dev, 3900 "failed to create Ethernet egress queue: %d\n", rc); 3901 return (rc); 3902 } 3903 eq->flags |= EQ_ALLOCATED; 3904 3905 eq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd)); 3906 eq->abs_id = G_FW_EQ_ETH_CMD_PHYSEQID(be32toh(c.physeqid_pkd)); 3907 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 3908 if (cntxt_id >= sc->sge.neq) 3909 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 3910 cntxt_id, sc->sge.neq - 1); 3911 sc->sge.eqmap[cntxt_id] = eq; 3912 3913 return (rc); 3914 } 3915 3916 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 3917 static int 3918 ofld_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 3919 { 3920 int rc, cntxt_id; 3921 struct fw_eq_ofld_cmd c; 3922 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 3923 3924 bzero(&c, sizeof(c)); 3925 3926 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | F_FW_CMD_REQUEST | 3927 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_OFLD_CMD_PFN(sc->pf) | 3928 V_FW_EQ_OFLD_CMD_VFN(0)); 3929 c.alloc_to_len16 = htonl(F_FW_EQ_OFLD_CMD_ALLOC | 3930 F_FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c)); 3931 c.fetchszm_to_iqid = 3932 htonl(V_FW_EQ_OFLD_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 3933 V_FW_EQ_OFLD_CMD_PCIECHN(eq->tx_chan) | 3934 F_FW_EQ_OFLD_CMD_FETCHRO | V_FW_EQ_OFLD_CMD_IQID(eq->iqid)); 3935 c.dcaen_to_eqsize = 3936 htobe32(V_FW_EQ_OFLD_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ? 3937 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) | 3938 V_FW_EQ_OFLD_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 3939 V_FW_EQ_OFLD_CMD_CIDXFTHRESH(qsize_to_fthresh(qsize)) | 3940 V_FW_EQ_OFLD_CMD_EQSIZE(qsize)); 3941 c.eqaddr = htobe64(eq->ba); 3942 3943 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3944 if (rc != 0) { 3945 device_printf(vi->dev, 3946 "failed to create egress queue for TCP offload: %d\n", rc); 3947 return (rc); 3948 } 3949 eq->flags |= EQ_ALLOCATED; 3950 3951 eq->cntxt_id = G_FW_EQ_OFLD_CMD_EQID(be32toh(c.eqid_pkd)); 3952 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 3953 if (cntxt_id >= sc->sge.neq) 3954 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 3955 cntxt_id, sc->sge.neq - 1); 3956 sc->sge.eqmap[cntxt_id] = eq; 3957 3958 return (rc); 3959 } 3960 #endif 3961 3962 static int 3963 alloc_eq(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 3964 { 3965 int rc, qsize; 3966 size_t len; 3967 3968 mtx_init(&eq->eq_lock, eq->lockname, NULL, MTX_DEF); 3969 3970 qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 3971 len = qsize * EQ_ESIZE; 3972 rc = alloc_ring(sc, len, &eq->desc_tag, &eq->desc_map, 3973 &eq->ba, (void **)&eq->desc); 3974 if (rc) 3975 return (rc); 3976 3977 eq->pidx = eq->cidx = eq->dbidx = 0; 3978 /* Note that equeqidx is not used with sge_wrq (OFLD/CTRL) queues. */ 3979 eq->equeqidx = 0; 3980 eq->doorbells = sc->doorbells; 3981 3982 switch (eq->flags & EQ_TYPEMASK) { 3983 case EQ_CTRL: 3984 rc = ctrl_eq_alloc(sc, eq); 3985 break; 3986 3987 case EQ_ETH: 3988 rc = eth_eq_alloc(sc, vi, eq); 3989 break; 3990 3991 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 3992 case EQ_OFLD: 3993 rc = ofld_eq_alloc(sc, vi, eq); 3994 break; 3995 #endif 3996 3997 default: 3998 panic("%s: invalid eq type %d.", __func__, 3999 eq->flags & EQ_TYPEMASK); 4000 } 4001 if (rc != 0) { 4002 device_printf(sc->dev, 4003 "failed to allocate egress queue(%d): %d\n", 4004 eq->flags & EQ_TYPEMASK, rc); 4005 } 4006 4007 if (isset(&eq->doorbells, DOORBELL_UDB) || 4008 isset(&eq->doorbells, DOORBELL_UDBWC) || 4009 isset(&eq->doorbells, DOORBELL_WCWR)) { 4010 uint32_t s_qpp = sc->params.sge.eq_s_qpp; 4011 uint32_t mask = (1 << s_qpp) - 1; 4012 volatile uint8_t *udb; 4013 4014 udb = sc->udbs_base + UDBS_DB_OFFSET; 4015 udb += (eq->cntxt_id >> s_qpp) << PAGE_SHIFT; /* pg offset */ 4016 eq->udb_qid = eq->cntxt_id & mask; /* id in page */ 4017 if (eq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE) 4018 clrbit(&eq->doorbells, DOORBELL_WCWR); 4019 else { 4020 udb += eq->udb_qid << UDBS_SEG_SHIFT; /* seg offset */ 4021 eq->udb_qid = 0; 4022 } 4023 eq->udb = (volatile void *)udb; 4024 } 4025 4026 return (rc); 4027 } 4028 4029 static int 4030 free_eq(struct adapter *sc, struct sge_eq *eq) 4031 { 4032 int rc; 4033 4034 if (eq->flags & EQ_ALLOCATED) { 4035 switch (eq->flags & EQ_TYPEMASK) { 4036 case EQ_CTRL: 4037 rc = -t4_ctrl_eq_free(sc, sc->mbox, sc->pf, 0, 4038 eq->cntxt_id); 4039 break; 4040 4041 case EQ_ETH: 4042 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0, 4043 eq->cntxt_id); 4044 break; 4045 4046 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 4047 case EQ_OFLD: 4048 rc = -t4_ofld_eq_free(sc, sc->mbox, sc->pf, 0, 4049 eq->cntxt_id); 4050 break; 4051 #endif 4052 4053 default: 4054 panic("%s: invalid eq type %d.", __func__, 4055 eq->flags & EQ_TYPEMASK); 4056 } 4057 if (rc != 0) { 4058 device_printf(sc->dev, 4059 "failed to free egress queue (%d): %d\n", 4060 eq->flags & EQ_TYPEMASK, rc); 4061 return (rc); 4062 } 4063 eq->flags &= ~EQ_ALLOCATED; 4064 } 4065 4066 free_ring(sc, eq->desc_tag, eq->desc_map, eq->ba, eq->desc); 4067 4068 if (mtx_initialized(&eq->eq_lock)) 4069 mtx_destroy(&eq->eq_lock); 4070 4071 bzero(eq, sizeof(*eq)); 4072 return (0); 4073 } 4074 4075 static int 4076 alloc_wrq(struct adapter *sc, struct vi_info *vi, struct sge_wrq *wrq, 4077 struct sysctl_oid *oid) 4078 { 4079 int rc; 4080 struct sysctl_ctx_list *ctx = vi ? &vi->ctx : &sc->ctx; 4081 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 4082 4083 rc = alloc_eq(sc, vi, &wrq->eq); 4084 if (rc) 4085 return (rc); 4086 4087 wrq->adapter = sc; 4088 TASK_INIT(&wrq->wrq_tx_task, 0, wrq_tx_drain, wrq); 4089 TAILQ_INIT(&wrq->incomplete_wrs); 4090 STAILQ_INIT(&wrq->wr_list); 4091 wrq->nwr_pending = 0; 4092 wrq->ndesc_needed = 0; 4093 4094 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, 4095 &wrq->eq.ba, "bus address of descriptor ring"); 4096 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 4097 wrq->eq.sidx * EQ_ESIZE + sc->params.sge.spg_len, 4098 "desc ring size in bytes"); 4099 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 4100 &wrq->eq.cntxt_id, 0, "SGE context id of the queue"); 4101 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx", 4102 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.cidx, 0, sysctl_uint16, "I", 4103 "consumer index"); 4104 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pidx", 4105 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.pidx, 0, sysctl_uint16, "I", 4106 "producer index"); 4107 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL, 4108 wrq->eq.sidx, "status page index"); 4109 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_direct", CTLFLAG_RD, 4110 &wrq->tx_wrs_direct, "# of work requests (direct)"); 4111 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_copied", CTLFLAG_RD, 4112 &wrq->tx_wrs_copied, "# of work requests (copied)"); 4113 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_sspace", CTLFLAG_RD, 4114 &wrq->tx_wrs_ss, "# of work requests (copied from scratch space)"); 4115 4116 return (rc); 4117 } 4118 4119 static int 4120 free_wrq(struct adapter *sc, struct sge_wrq *wrq) 4121 { 4122 int rc; 4123 4124 rc = free_eq(sc, &wrq->eq); 4125 if (rc) 4126 return (rc); 4127 4128 bzero(wrq, sizeof(*wrq)); 4129 return (0); 4130 } 4131 4132 static int 4133 alloc_txq(struct vi_info *vi, struct sge_txq *txq, int idx, 4134 struct sysctl_oid *oid) 4135 { 4136 int rc; 4137 struct port_info *pi = vi->pi; 4138 struct adapter *sc = pi->adapter; 4139 struct sge_eq *eq = &txq->eq; 4140 char name[16]; 4141 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 4142 4143 rc = mp_ring_alloc(&txq->r, eq->sidx, txq, eth_tx, can_resume_eth_tx, 4144 M_CXGBE, M_WAITOK); 4145 if (rc != 0) { 4146 device_printf(sc->dev, "failed to allocate mp_ring: %d\n", rc); 4147 return (rc); 4148 } 4149 4150 rc = alloc_eq(sc, vi, eq); 4151 if (rc != 0) { 4152 mp_ring_free(txq->r); 4153 txq->r = NULL; 4154 return (rc); 4155 } 4156 4157 /* Can't fail after this point. */ 4158 4159 if (idx == 0) 4160 sc->sge.eq_base = eq->abs_id - eq->cntxt_id; 4161 else 4162 KASSERT(eq->cntxt_id + sc->sge.eq_base == eq->abs_id, 4163 ("eq_base mismatch")); 4164 KASSERT(sc->sge.eq_base == 0 || sc->flags & IS_VF, 4165 ("PF with non-zero eq_base")); 4166 4167 TASK_INIT(&txq->tx_reclaim_task, 0, tx_reclaim, eq); 4168 txq->ifp = vi->ifp; 4169 txq->gl = sglist_alloc(TX_SGL_SEGS, M_WAITOK); 4170 if (sc->flags & IS_VF) 4171 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) | 4172 V_TXPKT_INTF(pi->tx_chan)); 4173 else 4174 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) | 4175 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(sc->pf) | 4176 V_TXPKT_VF(vi->vin) | V_TXPKT_VF_VLD(vi->vfvld)); 4177 txq->tc_idx = -1; 4178 txq->sdesc = malloc(eq->sidx * sizeof(struct tx_sdesc), M_CXGBE, 4179 M_ZERO | M_WAITOK); 4180 4181 snprintf(name, sizeof(name), "%d", idx); 4182 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 4183 NULL, "tx queue"); 4184 children = SYSCTL_CHILDREN(oid); 4185 4186 SYSCTL_ADD_UAUTO(&vi->ctx, children, OID_AUTO, "ba", CTLFLAG_RD, 4187 &eq->ba, "bus address of descriptor ring"); 4188 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 4189 eq->sidx * EQ_ESIZE + sc->params.sge.spg_len, 4190 "desc ring size in bytes"); 4191 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "abs_id", CTLFLAG_RD, 4192 &eq->abs_id, 0, "absolute id of the queue"); 4193 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 4194 &eq->cntxt_id, 0, "SGE context id of the queue"); 4195 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx", 4196 CTLTYPE_INT | CTLFLAG_RD, &eq->cidx, 0, sysctl_uint16, "I", 4197 "consumer index"); 4198 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "pidx", 4199 CTLTYPE_INT | CTLFLAG_RD, &eq->pidx, 0, sysctl_uint16, "I", 4200 "producer index"); 4201 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL, 4202 eq->sidx, "status page index"); 4203 4204 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "tc", 4205 CTLTYPE_INT | CTLFLAG_RW, vi, idx, sysctl_tc, "I", 4206 "traffic class (-1 means none)"); 4207 4208 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txcsum", CTLFLAG_RD, 4209 &txq->txcsum, "# of times hardware assisted with checksum"); 4210 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_insertion", 4211 CTLFLAG_RD, &txq->vlan_insertion, 4212 "# of times hardware inserted 802.1Q tag"); 4213 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "tso_wrs", CTLFLAG_RD, 4214 &txq->tso_wrs, "# of TSO work requests"); 4215 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "imm_wrs", CTLFLAG_RD, 4216 &txq->imm_wrs, "# of work requests with immediate data"); 4217 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "sgl_wrs", CTLFLAG_RD, 4218 &txq->sgl_wrs, "# of work requests with direct SGL"); 4219 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkt_wrs", CTLFLAG_RD, 4220 &txq->txpkt_wrs, "# of txpkt work requests (one pkt/WR)"); 4221 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_wrs", 4222 CTLFLAG_RD, &txq->txpkts0_wrs, 4223 "# of txpkts (type 0) work requests"); 4224 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_wrs", 4225 CTLFLAG_RD, &txq->txpkts1_wrs, 4226 "# of txpkts (type 1) work requests"); 4227 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_pkts", 4228 CTLFLAG_RD, &txq->txpkts0_pkts, 4229 "# of frames tx'd using type0 txpkts work requests"); 4230 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_pkts", 4231 CTLFLAG_RD, &txq->txpkts1_pkts, 4232 "# of frames tx'd using type1 txpkts work requests"); 4233 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "raw_wrs", CTLFLAG_RD, 4234 &txq->raw_wrs, "# of raw work requests (non-packets)"); 4235 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "tls_wrs", CTLFLAG_RD, 4236 &txq->tls_wrs, "# of TLS work requests (TLS records)"); 4237 4238 #ifdef KERN_TLS 4239 if (sc->flags & KERN_TLS_OK) { 4240 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, 4241 "kern_tls_records", CTLFLAG_RD, &txq->kern_tls_records, 4242 "# of NIC TLS records transmitted"); 4243 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, 4244 "kern_tls_short", CTLFLAG_RD, &txq->kern_tls_short, 4245 "# of short NIC TLS records transmitted"); 4246 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, 4247 "kern_tls_partial", CTLFLAG_RD, &txq->kern_tls_partial, 4248 "# of partial NIC TLS records transmitted"); 4249 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, 4250 "kern_tls_full", CTLFLAG_RD, &txq->kern_tls_full, 4251 "# of full NIC TLS records transmitted"); 4252 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, 4253 "kern_tls_octets", CTLFLAG_RD, &txq->kern_tls_octets, 4254 "# of payload octets in transmitted NIC TLS records"); 4255 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, 4256 "kern_tls_waste", CTLFLAG_RD, &txq->kern_tls_waste, 4257 "# of octets DMAd but not transmitted in NIC TLS records"); 4258 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, 4259 "kern_tls_options", CTLFLAG_RD, &txq->kern_tls_options, 4260 "# of NIC TLS options-only packets transmitted"); 4261 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, 4262 "kern_tls_header", CTLFLAG_RD, &txq->kern_tls_header, 4263 "# of NIC TLS header-only packets transmitted"); 4264 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, 4265 "kern_tls_fin", CTLFLAG_RD, &txq->kern_tls_fin, 4266 "# of NIC TLS FIN-only packets transmitted"); 4267 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, 4268 "kern_tls_fin_short", CTLFLAG_RD, &txq->kern_tls_fin_short, 4269 "# of NIC TLS padded FIN packets on short TLS records"); 4270 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, 4271 "kern_tls_cbc", CTLFLAG_RD, &txq->kern_tls_cbc, 4272 "# of NIC TLS sessions using AES-CBC"); 4273 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, 4274 "kern_tls_gcm", CTLFLAG_RD, &txq->kern_tls_gcm, 4275 "# of NIC TLS sessions using AES-GCM"); 4276 } 4277 #endif 4278 4279 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_enqueues", 4280 CTLFLAG_RD, &txq->r->enqueues, 4281 "# of enqueues to the mp_ring for this queue"); 4282 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_drops", 4283 CTLFLAG_RD, &txq->r->drops, 4284 "# of drops in the mp_ring for this queue"); 4285 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_starts", 4286 CTLFLAG_RD, &txq->r->starts, 4287 "# of normal consumer starts in the mp_ring for this queue"); 4288 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_stalls", 4289 CTLFLAG_RD, &txq->r->stalls, 4290 "# of consumer stalls in the mp_ring for this queue"); 4291 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_restarts", 4292 CTLFLAG_RD, &txq->r->restarts, 4293 "# of consumer restarts in the mp_ring for this queue"); 4294 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_abdications", 4295 CTLFLAG_RD, &txq->r->abdications, 4296 "# of consumer abdications in the mp_ring for this queue"); 4297 4298 return (0); 4299 } 4300 4301 static int 4302 free_txq(struct vi_info *vi, struct sge_txq *txq) 4303 { 4304 int rc; 4305 struct adapter *sc = vi->pi->adapter; 4306 struct sge_eq *eq = &txq->eq; 4307 4308 rc = free_eq(sc, eq); 4309 if (rc) 4310 return (rc); 4311 4312 sglist_free(txq->gl); 4313 free(txq->sdesc, M_CXGBE); 4314 mp_ring_free(txq->r); 4315 4316 bzero(txq, sizeof(*txq)); 4317 return (0); 4318 } 4319 4320 static void 4321 oneseg_dma_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error) 4322 { 4323 bus_addr_t *ba = arg; 4324 4325 KASSERT(nseg == 1, 4326 ("%s meant for single segment mappings only.", __func__)); 4327 4328 *ba = error ? 0 : segs->ds_addr; 4329 } 4330 4331 static inline void 4332 ring_fl_db(struct adapter *sc, struct sge_fl *fl) 4333 { 4334 uint32_t n, v; 4335 4336 n = IDXDIFF(fl->pidx / 8, fl->dbidx, fl->sidx); 4337 MPASS(n > 0); 4338 4339 wmb(); 4340 v = fl->dbval | V_PIDX(n); 4341 if (fl->udb) 4342 *fl->udb = htole32(v); 4343 else 4344 t4_write_reg(sc, sc->sge_kdoorbell_reg, v); 4345 IDXINCR(fl->dbidx, n, fl->sidx); 4346 } 4347 4348 /* 4349 * Fills up the freelist by allocating up to 'n' buffers. Buffers that are 4350 * recycled do not count towards this allocation budget. 4351 * 4352 * Returns non-zero to indicate that this freelist should be added to the list 4353 * of starving freelists. 4354 */ 4355 static int 4356 refill_fl(struct adapter *sc, struct sge_fl *fl, int n) 4357 { 4358 __be64 *d; 4359 struct fl_sdesc *sd; 4360 uintptr_t pa; 4361 caddr_t cl; 4362 struct cluster_layout *cll; 4363 struct sw_zone_info *swz; 4364 struct cluster_metadata *clm; 4365 uint16_t max_pidx; 4366 uint16_t hw_cidx = fl->hw_cidx; /* stable snapshot */ 4367 4368 FL_LOCK_ASSERT_OWNED(fl); 4369 4370 /* 4371 * We always stop at the beginning of the hardware descriptor that's just 4372 * before the one with the hw cidx. This is to avoid hw pidx = hw cidx, 4373 * which would mean an empty freelist to the chip. 4374 */ 4375 max_pidx = __predict_false(hw_cidx == 0) ? fl->sidx - 1 : hw_cidx - 1; 4376 if (fl->pidx == max_pidx * 8) 4377 return (0); 4378 4379 d = &fl->desc[fl->pidx]; 4380 sd = &fl->sdesc[fl->pidx]; 4381 cll = &fl->cll_def; /* default layout */ 4382 swz = &sc->sge.sw_zone_info[cll->zidx]; 4383 4384 while (n > 0) { 4385 4386 if (sd->cl != NULL) { 4387 4388 if (sd->nmbuf == 0) { 4389 /* 4390 * Fast recycle without involving any atomics on 4391 * the cluster's metadata (if the cluster has 4392 * metadata). This happens when all frames 4393 * received in the cluster were small enough to 4394 * fit within a single mbuf each. 4395 */ 4396 fl->cl_fast_recycled++; 4397 #ifdef INVARIANTS 4398 clm = cl_metadata(sc, fl, &sd->cll, sd->cl); 4399 if (clm != NULL) 4400 MPASS(clm->refcount == 1); 4401 #endif 4402 goto recycled_fast; 4403 } 4404 4405 /* 4406 * Cluster is guaranteed to have metadata. Clusters 4407 * without metadata always take the fast recycle path 4408 * when they're recycled. 4409 */ 4410 clm = cl_metadata(sc, fl, &sd->cll, sd->cl); 4411 MPASS(clm != NULL); 4412 4413 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) { 4414 fl->cl_recycled++; 4415 counter_u64_add(extfree_rels, 1); 4416 goto recycled; 4417 } 4418 sd->cl = NULL; /* gave up my reference */ 4419 } 4420 MPASS(sd->cl == NULL); 4421 alloc: 4422 cl = uma_zalloc(swz->zone, M_NOWAIT); 4423 if (__predict_false(cl == NULL)) { 4424 if (cll == &fl->cll_alt || fl->cll_alt.zidx == -1 || 4425 fl->cll_def.zidx == fl->cll_alt.zidx) 4426 break; 4427 4428 /* fall back to the safe zone */ 4429 cll = &fl->cll_alt; 4430 swz = &sc->sge.sw_zone_info[cll->zidx]; 4431 goto alloc; 4432 } 4433 fl->cl_allocated++; 4434 n--; 4435 4436 pa = pmap_kextract((vm_offset_t)cl); 4437 pa += cll->region1; 4438 sd->cl = cl; 4439 sd->cll = *cll; 4440 *d = htobe64(pa | cll->hwidx); 4441 clm = cl_metadata(sc, fl, cll, cl); 4442 if (clm != NULL) { 4443 recycled: 4444 #ifdef INVARIANTS 4445 clm->sd = sd; 4446 #endif 4447 clm->refcount = 1; 4448 } 4449 sd->nmbuf = 0; 4450 recycled_fast: 4451 d++; 4452 sd++; 4453 if (__predict_false(++fl->pidx % 8 == 0)) { 4454 uint16_t pidx = fl->pidx / 8; 4455 4456 if (__predict_false(pidx == fl->sidx)) { 4457 fl->pidx = 0; 4458 pidx = 0; 4459 sd = fl->sdesc; 4460 d = fl->desc; 4461 } 4462 if (pidx == max_pidx) 4463 break; 4464 4465 if (IDXDIFF(pidx, fl->dbidx, fl->sidx) >= 4) 4466 ring_fl_db(sc, fl); 4467 } 4468 } 4469 4470 if (fl->pidx / 8 != fl->dbidx) 4471 ring_fl_db(sc, fl); 4472 4473 return (FL_RUNNING_LOW(fl) && !(fl->flags & FL_STARVING)); 4474 } 4475 4476 /* 4477 * Attempt to refill all starving freelists. 4478 */ 4479 static void 4480 refill_sfl(void *arg) 4481 { 4482 struct adapter *sc = arg; 4483 struct sge_fl *fl, *fl_temp; 4484 4485 mtx_assert(&sc->sfl_lock, MA_OWNED); 4486 TAILQ_FOREACH_SAFE(fl, &sc->sfl, link, fl_temp) { 4487 FL_LOCK(fl); 4488 refill_fl(sc, fl, 64); 4489 if (FL_NOT_RUNNING_LOW(fl) || fl->flags & FL_DOOMED) { 4490 TAILQ_REMOVE(&sc->sfl, fl, link); 4491 fl->flags &= ~FL_STARVING; 4492 } 4493 FL_UNLOCK(fl); 4494 } 4495 4496 if (!TAILQ_EMPTY(&sc->sfl)) 4497 callout_schedule(&sc->sfl_callout, hz / 5); 4498 } 4499 4500 static int 4501 alloc_fl_sdesc(struct sge_fl *fl) 4502 { 4503 4504 fl->sdesc = malloc(fl->sidx * 8 * sizeof(struct fl_sdesc), M_CXGBE, 4505 M_ZERO | M_WAITOK); 4506 4507 return (0); 4508 } 4509 4510 static void 4511 free_fl_sdesc(struct adapter *sc, struct sge_fl *fl) 4512 { 4513 struct fl_sdesc *sd; 4514 struct cluster_metadata *clm; 4515 struct cluster_layout *cll; 4516 int i; 4517 4518 sd = fl->sdesc; 4519 for (i = 0; i < fl->sidx * 8; i++, sd++) { 4520 if (sd->cl == NULL) 4521 continue; 4522 4523 cll = &sd->cll; 4524 clm = cl_metadata(sc, fl, cll, sd->cl); 4525 if (sd->nmbuf == 0) 4526 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl); 4527 else if (clm && atomic_fetchadd_int(&clm->refcount, -1) == 1) { 4528 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl); 4529 counter_u64_add(extfree_rels, 1); 4530 } 4531 sd->cl = NULL; 4532 } 4533 4534 free(fl->sdesc, M_CXGBE); 4535 fl->sdesc = NULL; 4536 } 4537 4538 static inline void 4539 get_pkt_gl(struct mbuf *m, struct sglist *gl) 4540 { 4541 int rc; 4542 4543 M_ASSERTPKTHDR(m); 4544 4545 sglist_reset(gl); 4546 rc = sglist_append_mbuf(gl, m); 4547 if (__predict_false(rc != 0)) { 4548 panic("%s: mbuf %p (%d segs) was vetted earlier but now fails " 4549 "with %d.", __func__, m, mbuf_nsegs(m), rc); 4550 } 4551 4552 KASSERT(gl->sg_nseg == mbuf_nsegs(m), 4553 ("%s: nsegs changed for mbuf %p from %d to %d", __func__, m, 4554 mbuf_nsegs(m), gl->sg_nseg)); 4555 KASSERT(gl->sg_nseg > 0 && 4556 gl->sg_nseg <= (needs_tso(m) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS), 4557 ("%s: %d segments, should have been 1 <= nsegs <= %d", __func__, 4558 gl->sg_nseg, needs_tso(m) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS)); 4559 } 4560 4561 /* 4562 * len16 for a txpkt WR with a GL. Includes the firmware work request header. 4563 */ 4564 static inline u_int 4565 txpkt_len16(u_int nsegs, u_int tso) 4566 { 4567 u_int n; 4568 4569 MPASS(nsegs > 0); 4570 4571 nsegs--; /* first segment is part of ulptx_sgl */ 4572 n = sizeof(struct fw_eth_tx_pkt_wr) + sizeof(struct cpl_tx_pkt_core) + 4573 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 4574 if (tso) 4575 n += sizeof(struct cpl_tx_pkt_lso_core); 4576 4577 return (howmany(n, 16)); 4578 } 4579 4580 /* 4581 * len16 for a txpkt_vm WR with a GL. Includes the firmware work 4582 * request header. 4583 */ 4584 static inline u_int 4585 txpkt_vm_len16(u_int nsegs, u_int tso) 4586 { 4587 u_int n; 4588 4589 MPASS(nsegs > 0); 4590 4591 nsegs--; /* first segment is part of ulptx_sgl */ 4592 n = sizeof(struct fw_eth_tx_pkt_vm_wr) + 4593 sizeof(struct cpl_tx_pkt_core) + 4594 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 4595 if (tso) 4596 n += sizeof(struct cpl_tx_pkt_lso_core); 4597 4598 return (howmany(n, 16)); 4599 } 4600 4601 /* 4602 * len16 for a txpkts type 0 WR with a GL. Does not include the firmware work 4603 * request header. 4604 */ 4605 static inline u_int 4606 txpkts0_len16(u_int nsegs) 4607 { 4608 u_int n; 4609 4610 MPASS(nsegs > 0); 4611 4612 nsegs--; /* first segment is part of ulptx_sgl */ 4613 n = sizeof(struct ulp_txpkt) + sizeof(struct ulptx_idata) + 4614 sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl) + 4615 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 4616 4617 return (howmany(n, 16)); 4618 } 4619 4620 /* 4621 * len16 for a txpkts type 1 WR with a GL. Does not include the firmware work 4622 * request header. 4623 */ 4624 static inline u_int 4625 txpkts1_len16(void) 4626 { 4627 u_int n; 4628 4629 n = sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl); 4630 4631 return (howmany(n, 16)); 4632 } 4633 4634 static inline u_int 4635 imm_payload(u_int ndesc) 4636 { 4637 u_int n; 4638 4639 n = ndesc * EQ_ESIZE - sizeof(struct fw_eth_tx_pkt_wr) - 4640 sizeof(struct cpl_tx_pkt_core); 4641 4642 return (n); 4643 } 4644 4645 static inline uint64_t 4646 csum_to_ctrl(struct adapter *sc, struct mbuf *m) 4647 { 4648 uint64_t ctrl; 4649 int csum_type; 4650 4651 M_ASSERTPKTHDR(m); 4652 4653 if (needs_hwcsum(m) == 0) 4654 return (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS); 4655 4656 ctrl = 0; 4657 if (needs_l3_csum(m) == 0) 4658 ctrl |= F_TXPKT_IPCSUM_DIS; 4659 switch (m->m_pkthdr.csum_flags & 4660 (CSUM_IP_TCP | CSUM_IP_UDP | CSUM_IP6_TCP | CSUM_IP6_UDP)) { 4661 case CSUM_IP_TCP: 4662 csum_type = TX_CSUM_TCPIP; 4663 break; 4664 case CSUM_IP_UDP: 4665 csum_type = TX_CSUM_UDPIP; 4666 break; 4667 case CSUM_IP6_TCP: 4668 csum_type = TX_CSUM_TCPIP6; 4669 break; 4670 case CSUM_IP6_UDP: 4671 csum_type = TX_CSUM_UDPIP6; 4672 break; 4673 default: 4674 /* needs_hwcsum told us that at least some hwcsum is needed. */ 4675 MPASS(ctrl == 0); 4676 MPASS(m->m_pkthdr.csum_flags & CSUM_IP); 4677 ctrl |= F_TXPKT_L4CSUM_DIS; 4678 csum_type = TX_CSUM_IP; 4679 break; 4680 } 4681 4682 MPASS(m->m_pkthdr.l2hlen > 0); 4683 MPASS(m->m_pkthdr.l3hlen > 0); 4684 ctrl |= V_TXPKT_CSUM_TYPE(csum_type) | 4685 V_TXPKT_IPHDR_LEN(m->m_pkthdr.l3hlen); 4686 if (chip_id(sc) <= CHELSIO_T5) 4687 ctrl |= V_TXPKT_ETHHDR_LEN(m->m_pkthdr.l2hlen - ETHER_HDR_LEN); 4688 else 4689 ctrl |= V_T6_TXPKT_ETHHDR_LEN(m->m_pkthdr.l2hlen - ETHER_HDR_LEN); 4690 4691 return (ctrl); 4692 } 4693 4694 /* 4695 * Write a VM txpkt WR for this packet to the hardware descriptors, update the 4696 * software descriptor, and advance the pidx. It is guaranteed that enough 4697 * descriptors are available. 4698 * 4699 * The return value is the # of hardware descriptors used. 4700 */ 4701 static u_int 4702 write_txpkt_vm_wr(struct adapter *sc, struct sge_txq *txq, 4703 struct fw_eth_tx_pkt_vm_wr *wr, struct mbuf *m0, u_int available) 4704 { 4705 struct sge_eq *eq = &txq->eq; 4706 struct tx_sdesc *txsd; 4707 struct cpl_tx_pkt_core *cpl; 4708 uint32_t ctrl; /* used in many unrelated places */ 4709 uint64_t ctrl1; 4710 int len16, ndesc, pktlen, nsegs; 4711 caddr_t dst; 4712 4713 TXQ_LOCK_ASSERT_OWNED(txq); 4714 M_ASSERTPKTHDR(m0); 4715 MPASS(available > 0 && available < eq->sidx); 4716 4717 len16 = mbuf_len16(m0); 4718 nsegs = mbuf_nsegs(m0); 4719 pktlen = m0->m_pkthdr.len; 4720 ctrl = sizeof(struct cpl_tx_pkt_core); 4721 if (needs_tso(m0)) 4722 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 4723 ndesc = howmany(len16, EQ_ESIZE / 16); 4724 MPASS(ndesc <= available); 4725 4726 /* Firmware work request header */ 4727 MPASS(wr == (void *)&eq->desc[eq->pidx]); 4728 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_VM_WR) | 4729 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl)); 4730 4731 ctrl = V_FW_WR_LEN16(len16); 4732 wr->equiq_to_len16 = htobe32(ctrl); 4733 wr->r3[0] = 0; 4734 wr->r3[1] = 0; 4735 4736 /* 4737 * Copy over ethmacdst, ethmacsrc, ethtype, and vlantci. 4738 * vlantci is ignored unless the ethtype is 0x8100, so it's 4739 * simpler to always copy it rather than making it 4740 * conditional. Also, it seems that we do not have to set 4741 * vlantci or fake the ethtype when doing VLAN tag insertion. 4742 */ 4743 m_copydata(m0, 0, sizeof(struct ether_header) + 2, wr->ethmacdst); 4744 4745 if (needs_tso(m0)) { 4746 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1); 4747 4748 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 4749 m0->m_pkthdr.l4hlen > 0, 4750 ("%s: mbuf %p needs TSO but missing header lengths", 4751 __func__, m0)); 4752 4753 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE | 4754 F_LSO_LAST_SLICE | V_LSO_ETHHDR_LEN((m0->m_pkthdr.l2hlen - 4755 ETHER_HDR_LEN) >> 2) | 4756 V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) | 4757 V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2); 4758 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 4759 ctrl |= F_LSO_IPV6; 4760 4761 lso->lso_ctrl = htobe32(ctrl); 4762 lso->ipid_ofst = htobe16(0); 4763 lso->mss = htobe16(m0->m_pkthdr.tso_segsz); 4764 lso->seqno_offset = htobe32(0); 4765 lso->len = htobe32(pktlen); 4766 4767 cpl = (void *)(lso + 1); 4768 4769 txq->tso_wrs++; 4770 } else 4771 cpl = (void *)(wr + 1); 4772 4773 /* Checksum offload */ 4774 ctrl1 = csum_to_ctrl(sc, m0); 4775 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS)) 4776 txq->txcsum++; /* some hardware assistance provided */ 4777 4778 /* VLAN tag insertion */ 4779 if (needs_vlan_insertion(m0)) { 4780 ctrl1 |= F_TXPKT_VLAN_VLD | 4781 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 4782 txq->vlan_insertion++; 4783 } 4784 4785 /* CPL header */ 4786 cpl->ctrl0 = txq->cpl_ctrl0; 4787 cpl->pack = 0; 4788 cpl->len = htobe16(pktlen); 4789 cpl->ctrl1 = htobe64(ctrl1); 4790 4791 /* SGL */ 4792 dst = (void *)(cpl + 1); 4793 4794 /* 4795 * A packet using TSO will use up an entire descriptor for the 4796 * firmware work request header, LSO CPL, and TX_PKT_XT CPL. 4797 * If this descriptor is the last descriptor in the ring, wrap 4798 * around to the front of the ring explicitly for the start of 4799 * the sgl. 4800 */ 4801 if (dst == (void *)&eq->desc[eq->sidx]) { 4802 dst = (void *)&eq->desc[0]; 4803 write_gl_to_txd(txq, m0, &dst, 0); 4804 } else 4805 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx); 4806 txq->sgl_wrs++; 4807 4808 txq->txpkt_wrs++; 4809 4810 txsd = &txq->sdesc[eq->pidx]; 4811 txsd->m = m0; 4812 txsd->desc_used = ndesc; 4813 4814 return (ndesc); 4815 } 4816 4817 /* 4818 * Write a raw WR to the hardware descriptors, update the software 4819 * descriptor, and advance the pidx. It is guaranteed that enough 4820 * descriptors are available. 4821 * 4822 * The return value is the # of hardware descriptors used. 4823 */ 4824 static u_int 4825 write_raw_wr(struct sge_txq *txq, void *wr, struct mbuf *m0, u_int available) 4826 { 4827 struct sge_eq *eq = &txq->eq; 4828 struct tx_sdesc *txsd; 4829 struct mbuf *m; 4830 caddr_t dst; 4831 int len16, ndesc; 4832 4833 len16 = mbuf_len16(m0); 4834 ndesc = howmany(len16, EQ_ESIZE / 16); 4835 MPASS(ndesc <= available); 4836 4837 dst = wr; 4838 for (m = m0; m != NULL; m = m->m_next) 4839 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len); 4840 4841 txq->raw_wrs++; 4842 4843 txsd = &txq->sdesc[eq->pidx]; 4844 txsd->m = m0; 4845 txsd->desc_used = ndesc; 4846 4847 return (ndesc); 4848 } 4849 4850 /* 4851 * Write a txpkt WR for this packet to the hardware descriptors, update the 4852 * software descriptor, and advance the pidx. It is guaranteed that enough 4853 * descriptors are available. 4854 * 4855 * The return value is the # of hardware descriptors used. 4856 */ 4857 static u_int 4858 write_txpkt_wr(struct adapter *sc, struct sge_txq *txq, 4859 struct fw_eth_tx_pkt_wr *wr, struct mbuf *m0, u_int available) 4860 { 4861 struct sge_eq *eq = &txq->eq; 4862 struct tx_sdesc *txsd; 4863 struct cpl_tx_pkt_core *cpl; 4864 uint32_t ctrl; /* used in many unrelated places */ 4865 uint64_t ctrl1; 4866 int len16, ndesc, pktlen, nsegs; 4867 caddr_t dst; 4868 4869 TXQ_LOCK_ASSERT_OWNED(txq); 4870 M_ASSERTPKTHDR(m0); 4871 MPASS(available > 0 && available < eq->sidx); 4872 4873 len16 = mbuf_len16(m0); 4874 nsegs = mbuf_nsegs(m0); 4875 pktlen = m0->m_pkthdr.len; 4876 ctrl = sizeof(struct cpl_tx_pkt_core); 4877 if (needs_tso(m0)) 4878 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 4879 else if (!(mbuf_cflags(m0) & MC_NOMAP) && pktlen <= imm_payload(2) && 4880 available >= 2) { 4881 /* Immediate data. Recalculate len16 and set nsegs to 0. */ 4882 ctrl += pktlen; 4883 len16 = howmany(sizeof(struct fw_eth_tx_pkt_wr) + 4884 sizeof(struct cpl_tx_pkt_core) + pktlen, 16); 4885 nsegs = 0; 4886 } 4887 ndesc = howmany(len16, EQ_ESIZE / 16); 4888 MPASS(ndesc <= available); 4889 4890 /* Firmware work request header */ 4891 MPASS(wr == (void *)&eq->desc[eq->pidx]); 4892 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_WR) | 4893 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl)); 4894 4895 ctrl = V_FW_WR_LEN16(len16); 4896 wr->equiq_to_len16 = htobe32(ctrl); 4897 wr->r3 = 0; 4898 4899 if (needs_tso(m0)) { 4900 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1); 4901 4902 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 4903 m0->m_pkthdr.l4hlen > 0, 4904 ("%s: mbuf %p needs TSO but missing header lengths", 4905 __func__, m0)); 4906 4907 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE | 4908 F_LSO_LAST_SLICE | V_LSO_ETHHDR_LEN((m0->m_pkthdr.l2hlen - 4909 ETHER_HDR_LEN) >> 2) | 4910 V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) | 4911 V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2); 4912 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 4913 ctrl |= F_LSO_IPV6; 4914 4915 lso->lso_ctrl = htobe32(ctrl); 4916 lso->ipid_ofst = htobe16(0); 4917 lso->mss = htobe16(m0->m_pkthdr.tso_segsz); 4918 lso->seqno_offset = htobe32(0); 4919 lso->len = htobe32(pktlen); 4920 4921 cpl = (void *)(lso + 1); 4922 4923 txq->tso_wrs++; 4924 } else 4925 cpl = (void *)(wr + 1); 4926 4927 /* Checksum offload */ 4928 ctrl1 = csum_to_ctrl(sc, m0); 4929 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS)) 4930 txq->txcsum++; /* some hardware assistance provided */ 4931 4932 /* VLAN tag insertion */ 4933 if (needs_vlan_insertion(m0)) { 4934 ctrl1 |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 4935 txq->vlan_insertion++; 4936 } 4937 4938 /* CPL header */ 4939 cpl->ctrl0 = txq->cpl_ctrl0; 4940 cpl->pack = 0; 4941 cpl->len = htobe16(pktlen); 4942 cpl->ctrl1 = htobe64(ctrl1); 4943 4944 /* SGL */ 4945 dst = (void *)(cpl + 1); 4946 if (nsegs > 0) { 4947 4948 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx); 4949 txq->sgl_wrs++; 4950 } else { 4951 struct mbuf *m; 4952 4953 for (m = m0; m != NULL; m = m->m_next) { 4954 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len); 4955 #ifdef INVARIANTS 4956 pktlen -= m->m_len; 4957 #endif 4958 } 4959 #ifdef INVARIANTS 4960 KASSERT(pktlen == 0, ("%s: %d bytes left.", __func__, pktlen)); 4961 #endif 4962 txq->imm_wrs++; 4963 } 4964 4965 txq->txpkt_wrs++; 4966 4967 txsd = &txq->sdesc[eq->pidx]; 4968 txsd->m = m0; 4969 txsd->desc_used = ndesc; 4970 4971 return (ndesc); 4972 } 4973 4974 static int 4975 try_txpkts(struct mbuf *m, struct mbuf *n, struct txpkts *txp, u_int available) 4976 { 4977 u_int needed, nsegs1, nsegs2, l1, l2; 4978 4979 if (cannot_use_txpkts(m) || cannot_use_txpkts(n)) 4980 return (1); 4981 4982 nsegs1 = mbuf_nsegs(m); 4983 nsegs2 = mbuf_nsegs(n); 4984 if (nsegs1 + nsegs2 == 2) { 4985 txp->wr_type = 1; 4986 l1 = l2 = txpkts1_len16(); 4987 } else { 4988 txp->wr_type = 0; 4989 l1 = txpkts0_len16(nsegs1); 4990 l2 = txpkts0_len16(nsegs2); 4991 } 4992 txp->len16 = howmany(sizeof(struct fw_eth_tx_pkts_wr), 16) + l1 + l2; 4993 needed = howmany(txp->len16, EQ_ESIZE / 16); 4994 if (needed > SGE_MAX_WR_NDESC || needed > available) 4995 return (1); 4996 4997 txp->plen = m->m_pkthdr.len + n->m_pkthdr.len; 4998 if (txp->plen > 65535) 4999 return (1); 5000 5001 txp->npkt = 2; 5002 set_mbuf_len16(m, l1); 5003 set_mbuf_len16(n, l2); 5004 5005 return (0); 5006 } 5007 5008 static int 5009 add_to_txpkts(struct mbuf *m, struct txpkts *txp, u_int available) 5010 { 5011 u_int plen, len16, needed, nsegs; 5012 5013 MPASS(txp->wr_type == 0 || txp->wr_type == 1); 5014 5015 if (cannot_use_txpkts(m)) 5016 return (1); 5017 5018 nsegs = mbuf_nsegs(m); 5019 if (txp->wr_type == 1 && nsegs != 1) 5020 return (1); 5021 5022 plen = txp->plen + m->m_pkthdr.len; 5023 if (plen > 65535) 5024 return (1); 5025 5026 if (txp->wr_type == 0) 5027 len16 = txpkts0_len16(nsegs); 5028 else 5029 len16 = txpkts1_len16(); 5030 needed = howmany(txp->len16 + len16, EQ_ESIZE / 16); 5031 if (needed > SGE_MAX_WR_NDESC || needed > available) 5032 return (1); 5033 5034 txp->npkt++; 5035 txp->plen = plen; 5036 txp->len16 += len16; 5037 set_mbuf_len16(m, len16); 5038 5039 return (0); 5040 } 5041 5042 /* 5043 * Write a txpkts WR for the packets in txp to the hardware descriptors, update 5044 * the software descriptor, and advance the pidx. It is guaranteed that enough 5045 * descriptors are available. 5046 * 5047 * The return value is the # of hardware descriptors used. 5048 */ 5049 static u_int 5050 write_txpkts_wr(struct adapter *sc, struct sge_txq *txq, 5051 struct fw_eth_tx_pkts_wr *wr, struct mbuf *m0, const struct txpkts *txp, 5052 u_int available) 5053 { 5054 struct sge_eq *eq = &txq->eq; 5055 struct tx_sdesc *txsd; 5056 struct cpl_tx_pkt_core *cpl; 5057 uint32_t ctrl; 5058 uint64_t ctrl1; 5059 int ndesc, checkwrap; 5060 struct mbuf *m; 5061 void *flitp; 5062 5063 TXQ_LOCK_ASSERT_OWNED(txq); 5064 MPASS(txp->npkt > 0); 5065 MPASS(txp->plen < 65536); 5066 MPASS(m0 != NULL); 5067 MPASS(m0->m_nextpkt != NULL); 5068 MPASS(txp->len16 <= howmany(SGE_MAX_WR_LEN, 16)); 5069 MPASS(available > 0 && available < eq->sidx); 5070 5071 ndesc = howmany(txp->len16, EQ_ESIZE / 16); 5072 MPASS(ndesc <= available); 5073 5074 MPASS(wr == (void *)&eq->desc[eq->pidx]); 5075 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR)); 5076 ctrl = V_FW_WR_LEN16(txp->len16); 5077 wr->equiq_to_len16 = htobe32(ctrl); 5078 wr->plen = htobe16(txp->plen); 5079 wr->npkt = txp->npkt; 5080 wr->r3 = 0; 5081 wr->type = txp->wr_type; 5082 flitp = wr + 1; 5083 5084 /* 5085 * At this point we are 16B into a hardware descriptor. If checkwrap is 5086 * set then we know the WR is going to wrap around somewhere. We'll 5087 * check for that at appropriate points. 5088 */ 5089 checkwrap = eq->sidx - ndesc < eq->pidx; 5090 for (m = m0; m != NULL; m = m->m_nextpkt) { 5091 if (txp->wr_type == 0) { 5092 struct ulp_txpkt *ulpmc; 5093 struct ulptx_idata *ulpsc; 5094 5095 /* ULP master command */ 5096 ulpmc = flitp; 5097 ulpmc->cmd_dest = htobe32(V_ULPTX_CMD(ULP_TX_PKT) | 5098 V_ULP_TXPKT_DEST(0) | V_ULP_TXPKT_FID(eq->iqid)); 5099 ulpmc->len = htobe32(mbuf_len16(m)); 5100 5101 /* ULP subcommand */ 5102 ulpsc = (void *)(ulpmc + 1); 5103 ulpsc->cmd_more = htobe32(V_ULPTX_CMD(ULP_TX_SC_IMM) | 5104 F_ULP_TX_SC_MORE); 5105 ulpsc->len = htobe32(sizeof(struct cpl_tx_pkt_core)); 5106 5107 cpl = (void *)(ulpsc + 1); 5108 if (checkwrap && 5109 (uintptr_t)cpl == (uintptr_t)&eq->desc[eq->sidx]) 5110 cpl = (void *)&eq->desc[0]; 5111 } else { 5112 cpl = flitp; 5113 } 5114 5115 /* Checksum offload */ 5116 ctrl1 = csum_to_ctrl(sc, m); 5117 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS)) 5118 txq->txcsum++; /* some hardware assistance provided */ 5119 5120 /* VLAN tag insertion */ 5121 if (needs_vlan_insertion(m)) { 5122 ctrl1 |= F_TXPKT_VLAN_VLD | 5123 V_TXPKT_VLAN(m->m_pkthdr.ether_vtag); 5124 txq->vlan_insertion++; 5125 } 5126 5127 /* CPL header */ 5128 cpl->ctrl0 = txq->cpl_ctrl0; 5129 cpl->pack = 0; 5130 cpl->len = htobe16(m->m_pkthdr.len); 5131 cpl->ctrl1 = htobe64(ctrl1); 5132 5133 flitp = cpl + 1; 5134 if (checkwrap && 5135 (uintptr_t)flitp == (uintptr_t)&eq->desc[eq->sidx]) 5136 flitp = (void *)&eq->desc[0]; 5137 5138 write_gl_to_txd(txq, m, (caddr_t *)(&flitp), checkwrap); 5139 5140 } 5141 5142 if (txp->wr_type == 0) { 5143 txq->txpkts0_pkts += txp->npkt; 5144 txq->txpkts0_wrs++; 5145 } else { 5146 txq->txpkts1_pkts += txp->npkt; 5147 txq->txpkts1_wrs++; 5148 } 5149 5150 txsd = &txq->sdesc[eq->pidx]; 5151 txsd->m = m0; 5152 txsd->desc_used = ndesc; 5153 5154 return (ndesc); 5155 } 5156 5157 /* 5158 * If the SGL ends on an address that is not 16 byte aligned, this function will 5159 * add a 0 filled flit at the end. 5160 */ 5161 static void 5162 write_gl_to_txd(struct sge_txq *txq, struct mbuf *m, caddr_t *to, int checkwrap) 5163 { 5164 struct sge_eq *eq = &txq->eq; 5165 struct sglist *gl = txq->gl; 5166 struct sglist_seg *seg; 5167 __be64 *flitp, *wrap; 5168 struct ulptx_sgl *usgl; 5169 int i, nflits, nsegs; 5170 5171 KASSERT(((uintptr_t)(*to) & 0xf) == 0, 5172 ("%s: SGL must start at a 16 byte boundary: %p", __func__, *to)); 5173 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]); 5174 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]); 5175 5176 get_pkt_gl(m, gl); 5177 nsegs = gl->sg_nseg; 5178 MPASS(nsegs > 0); 5179 5180 nflits = (3 * (nsegs - 1)) / 2 + ((nsegs - 1) & 1) + 2; 5181 flitp = (__be64 *)(*to); 5182 wrap = (__be64 *)(&eq->desc[eq->sidx]); 5183 seg = &gl->sg_segs[0]; 5184 usgl = (void *)flitp; 5185 5186 /* 5187 * We start at a 16 byte boundary somewhere inside the tx descriptor 5188 * ring, so we're at least 16 bytes away from the status page. There is 5189 * no chance of a wrap around in the middle of usgl (which is 16 bytes). 5190 */ 5191 5192 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 5193 V_ULPTX_NSGE(nsegs)); 5194 usgl->len0 = htobe32(seg->ss_len); 5195 usgl->addr0 = htobe64(seg->ss_paddr); 5196 seg++; 5197 5198 if (checkwrap == 0 || (uintptr_t)(flitp + nflits) <= (uintptr_t)wrap) { 5199 5200 /* Won't wrap around at all */ 5201 5202 for (i = 0; i < nsegs - 1; i++, seg++) { 5203 usgl->sge[i / 2].len[i & 1] = htobe32(seg->ss_len); 5204 usgl->sge[i / 2].addr[i & 1] = htobe64(seg->ss_paddr); 5205 } 5206 if (i & 1) 5207 usgl->sge[i / 2].len[1] = htobe32(0); 5208 flitp += nflits; 5209 } else { 5210 5211 /* Will wrap somewhere in the rest of the SGL */ 5212 5213 /* 2 flits already written, write the rest flit by flit */ 5214 flitp = (void *)(usgl + 1); 5215 for (i = 0; i < nflits - 2; i++) { 5216 if (flitp == wrap) 5217 flitp = (void *)eq->desc; 5218 *flitp++ = get_flit(seg, nsegs - 1, i); 5219 } 5220 } 5221 5222 if (nflits & 1) { 5223 MPASS(((uintptr_t)flitp) & 0xf); 5224 *flitp++ = 0; 5225 } 5226 5227 MPASS((((uintptr_t)flitp) & 0xf) == 0); 5228 if (__predict_false(flitp == wrap)) 5229 *to = (void *)eq->desc; 5230 else 5231 *to = (void *)flitp; 5232 } 5233 5234 static inline void 5235 copy_to_txd(struct sge_eq *eq, caddr_t from, caddr_t *to, int len) 5236 { 5237 5238 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]); 5239 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]); 5240 5241 if (__predict_true((uintptr_t)(*to) + len <= 5242 (uintptr_t)&eq->desc[eq->sidx])) { 5243 bcopy(from, *to, len); 5244 (*to) += len; 5245 } else { 5246 int portion = (uintptr_t)&eq->desc[eq->sidx] - (uintptr_t)(*to); 5247 5248 bcopy(from, *to, portion); 5249 from += portion; 5250 portion = len - portion; /* remaining */ 5251 bcopy(from, (void *)eq->desc, portion); 5252 (*to) = (caddr_t)eq->desc + portion; 5253 } 5254 } 5255 5256 static inline void 5257 ring_eq_db(struct adapter *sc, struct sge_eq *eq, u_int n) 5258 { 5259 u_int db; 5260 5261 MPASS(n > 0); 5262 5263 db = eq->doorbells; 5264 if (n > 1) 5265 clrbit(&db, DOORBELL_WCWR); 5266 wmb(); 5267 5268 switch (ffs(db) - 1) { 5269 case DOORBELL_UDB: 5270 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n)); 5271 break; 5272 5273 case DOORBELL_WCWR: { 5274 volatile uint64_t *dst, *src; 5275 int i; 5276 5277 /* 5278 * Queues whose 128B doorbell segment fits in the page do not 5279 * use relative qid (udb_qid is always 0). Only queues with 5280 * doorbell segments can do WCWR. 5281 */ 5282 KASSERT(eq->udb_qid == 0 && n == 1, 5283 ("%s: inappropriate doorbell (0x%x, %d, %d) for eq %p", 5284 __func__, eq->doorbells, n, eq->dbidx, eq)); 5285 5286 dst = (volatile void *)((uintptr_t)eq->udb + UDBS_WR_OFFSET - 5287 UDBS_DB_OFFSET); 5288 i = eq->dbidx; 5289 src = (void *)&eq->desc[i]; 5290 while (src != (void *)&eq->desc[i + 1]) 5291 *dst++ = *src++; 5292 wmb(); 5293 break; 5294 } 5295 5296 case DOORBELL_UDBWC: 5297 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n)); 5298 wmb(); 5299 break; 5300 5301 case DOORBELL_KDB: 5302 t4_write_reg(sc, sc->sge_kdoorbell_reg, 5303 V_QID(eq->cntxt_id) | V_PIDX(n)); 5304 break; 5305 } 5306 5307 IDXINCR(eq->dbidx, n, eq->sidx); 5308 } 5309 5310 static inline u_int 5311 reclaimable_tx_desc(struct sge_eq *eq) 5312 { 5313 uint16_t hw_cidx; 5314 5315 hw_cidx = read_hw_cidx(eq); 5316 return (IDXDIFF(hw_cidx, eq->cidx, eq->sidx)); 5317 } 5318 5319 static inline u_int 5320 total_available_tx_desc(struct sge_eq *eq) 5321 { 5322 uint16_t hw_cidx, pidx; 5323 5324 hw_cidx = read_hw_cidx(eq); 5325 pidx = eq->pidx; 5326 5327 if (pidx == hw_cidx) 5328 return (eq->sidx - 1); 5329 else 5330 return (IDXDIFF(hw_cidx, pidx, eq->sidx) - 1); 5331 } 5332 5333 static inline uint16_t 5334 read_hw_cidx(struct sge_eq *eq) 5335 { 5336 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx]; 5337 uint16_t cidx = spg->cidx; /* stable snapshot */ 5338 5339 return (be16toh(cidx)); 5340 } 5341 5342 /* 5343 * Reclaim 'n' descriptors approximately. 5344 */ 5345 static u_int 5346 reclaim_tx_descs(struct sge_txq *txq, u_int n) 5347 { 5348 struct tx_sdesc *txsd; 5349 struct sge_eq *eq = &txq->eq; 5350 u_int can_reclaim, reclaimed; 5351 5352 TXQ_LOCK_ASSERT_OWNED(txq); 5353 MPASS(n > 0); 5354 5355 reclaimed = 0; 5356 can_reclaim = reclaimable_tx_desc(eq); 5357 while (can_reclaim && reclaimed < n) { 5358 int ndesc; 5359 struct mbuf *m, *nextpkt; 5360 5361 txsd = &txq->sdesc[eq->cidx]; 5362 ndesc = txsd->desc_used; 5363 5364 /* Firmware doesn't return "partial" credits. */ 5365 KASSERT(can_reclaim >= ndesc, 5366 ("%s: unexpected number of credits: %d, %d", 5367 __func__, can_reclaim, ndesc)); 5368 KASSERT(ndesc != 0, 5369 ("%s: descriptor with no credits: cidx %d", 5370 __func__, eq->cidx)); 5371 5372 for (m = txsd->m; m != NULL; m = nextpkt) { 5373 nextpkt = m->m_nextpkt; 5374 m->m_nextpkt = NULL; 5375 m_freem(m); 5376 } 5377 reclaimed += ndesc; 5378 can_reclaim -= ndesc; 5379 IDXINCR(eq->cidx, ndesc, eq->sidx); 5380 } 5381 5382 return (reclaimed); 5383 } 5384 5385 static void 5386 tx_reclaim(void *arg, int n) 5387 { 5388 struct sge_txq *txq = arg; 5389 struct sge_eq *eq = &txq->eq; 5390 5391 do { 5392 if (TXQ_TRYLOCK(txq) == 0) 5393 break; 5394 n = reclaim_tx_descs(txq, 32); 5395 if (eq->cidx == eq->pidx) 5396 eq->equeqidx = eq->pidx; 5397 TXQ_UNLOCK(txq); 5398 } while (n > 0); 5399 } 5400 5401 static __be64 5402 get_flit(struct sglist_seg *segs, int nsegs, int idx) 5403 { 5404 int i = (idx / 3) * 2; 5405 5406 switch (idx % 3) { 5407 case 0: { 5408 uint64_t rc; 5409 5410 rc = (uint64_t)segs[i].ss_len << 32; 5411 if (i + 1 < nsegs) 5412 rc |= (uint64_t)(segs[i + 1].ss_len); 5413 5414 return (htobe64(rc)); 5415 } 5416 case 1: 5417 return (htobe64(segs[i].ss_paddr)); 5418 case 2: 5419 return (htobe64(segs[i + 1].ss_paddr)); 5420 } 5421 5422 return (0); 5423 } 5424 5425 static void 5426 find_best_refill_source(struct adapter *sc, struct sge_fl *fl, int maxp) 5427 { 5428 int8_t zidx, hwidx, idx; 5429 uint16_t region1, region3; 5430 int spare, spare_needed, n; 5431 struct sw_zone_info *swz; 5432 struct hw_buf_info *hwb, *hwb_list = &sc->sge.hw_buf_info[0]; 5433 5434 /* 5435 * Buffer Packing: Look for PAGE_SIZE or larger zone which has a bufsize 5436 * large enough for the max payload and cluster metadata. Otherwise 5437 * settle for the largest bufsize that leaves enough room in the cluster 5438 * for metadata. 5439 * 5440 * Without buffer packing: Look for the smallest zone which has a 5441 * bufsize large enough for the max payload. Settle for the largest 5442 * bufsize available if there's nothing big enough for max payload. 5443 */ 5444 spare_needed = fl->flags & FL_BUF_PACKING ? CL_METADATA_SIZE : 0; 5445 swz = &sc->sge.sw_zone_info[0]; 5446 hwidx = -1; 5447 for (zidx = 0; zidx < SW_ZONE_SIZES; zidx++, swz++) { 5448 if (swz->size > largest_rx_cluster) { 5449 if (__predict_true(hwidx != -1)) 5450 break; 5451 5452 /* 5453 * This is a misconfiguration. largest_rx_cluster is 5454 * preventing us from finding a refill source. See 5455 * dev.t5nex.<n>.buffer_sizes to figure out why. 5456 */ 5457 device_printf(sc->dev, "largest_rx_cluster=%u leaves no" 5458 " refill source for fl %p (dma %u). Ignored.\n", 5459 largest_rx_cluster, fl, maxp); 5460 } 5461 for (idx = swz->head_hwidx; idx != -1; idx = hwb->next) { 5462 hwb = &hwb_list[idx]; 5463 spare = swz->size - hwb->size; 5464 if (spare < spare_needed) 5465 continue; 5466 5467 hwidx = idx; /* best option so far */ 5468 if (hwb->size >= maxp) { 5469 5470 if ((fl->flags & FL_BUF_PACKING) == 0) 5471 goto done; /* stop looking (not packing) */ 5472 5473 if (swz->size >= safest_rx_cluster) 5474 goto done; /* stop looking (packing) */ 5475 } 5476 break; /* keep looking, next zone */ 5477 } 5478 } 5479 done: 5480 /* A usable hwidx has been located. */ 5481 MPASS(hwidx != -1); 5482 hwb = &hwb_list[hwidx]; 5483 zidx = hwb->zidx; 5484 swz = &sc->sge.sw_zone_info[zidx]; 5485 region1 = 0; 5486 region3 = swz->size - hwb->size; 5487 5488 /* 5489 * Stay within this zone and see if there is a better match when mbuf 5490 * inlining is allowed. Remember that the hwidx's are sorted in 5491 * decreasing order of size (so in increasing order of spare area). 5492 */ 5493 for (idx = hwidx; idx != -1; idx = hwb->next) { 5494 hwb = &hwb_list[idx]; 5495 spare = swz->size - hwb->size; 5496 5497 if (allow_mbufs_in_cluster == 0 || hwb->size < maxp) 5498 break; 5499 5500 /* 5501 * Do not inline mbufs if doing so would violate the pad/pack 5502 * boundary alignment requirement. 5503 */ 5504 if (fl_pad && (MSIZE % sc->params.sge.pad_boundary) != 0) 5505 continue; 5506 if (fl->flags & FL_BUF_PACKING && 5507 (MSIZE % sc->params.sge.pack_boundary) != 0) 5508 continue; 5509 5510 if (spare < CL_METADATA_SIZE + MSIZE) 5511 continue; 5512 n = (spare - CL_METADATA_SIZE) / MSIZE; 5513 if (n > howmany(hwb->size, maxp)) 5514 break; 5515 5516 hwidx = idx; 5517 if (fl->flags & FL_BUF_PACKING) { 5518 region1 = n * MSIZE; 5519 region3 = spare - region1; 5520 } else { 5521 region1 = MSIZE; 5522 region3 = spare - region1; 5523 break; 5524 } 5525 } 5526 5527 KASSERT(zidx >= 0 && zidx < SW_ZONE_SIZES, 5528 ("%s: bad zone %d for fl %p, maxp %d", __func__, zidx, fl, maxp)); 5529 KASSERT(hwidx >= 0 && hwidx <= SGE_FLBUF_SIZES, 5530 ("%s: bad hwidx %d for fl %p, maxp %d", __func__, hwidx, fl, maxp)); 5531 KASSERT(region1 + sc->sge.hw_buf_info[hwidx].size + region3 == 5532 sc->sge.sw_zone_info[zidx].size, 5533 ("%s: bad buffer layout for fl %p, maxp %d. " 5534 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp, 5535 sc->sge.sw_zone_info[zidx].size, region1, 5536 sc->sge.hw_buf_info[hwidx].size, region3)); 5537 if (fl->flags & FL_BUF_PACKING || region1 > 0) { 5538 KASSERT(region3 >= CL_METADATA_SIZE, 5539 ("%s: no room for metadata. fl %p, maxp %d; " 5540 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp, 5541 sc->sge.sw_zone_info[zidx].size, region1, 5542 sc->sge.hw_buf_info[hwidx].size, region3)); 5543 KASSERT(region1 % MSIZE == 0, 5544 ("%s: bad mbuf region for fl %p, maxp %d. " 5545 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp, 5546 sc->sge.sw_zone_info[zidx].size, region1, 5547 sc->sge.hw_buf_info[hwidx].size, region3)); 5548 } 5549 5550 fl->cll_def.zidx = zidx; 5551 fl->cll_def.hwidx = hwidx; 5552 fl->cll_def.region1 = region1; 5553 fl->cll_def.region3 = region3; 5554 } 5555 5556 static void 5557 find_safe_refill_source(struct adapter *sc, struct sge_fl *fl) 5558 { 5559 struct sge *s = &sc->sge; 5560 struct hw_buf_info *hwb; 5561 struct sw_zone_info *swz; 5562 int spare; 5563 int8_t hwidx; 5564 5565 if (fl->flags & FL_BUF_PACKING) 5566 hwidx = s->safe_hwidx2; /* with room for metadata */ 5567 else if (allow_mbufs_in_cluster && s->safe_hwidx2 != -1) { 5568 hwidx = s->safe_hwidx2; 5569 hwb = &s->hw_buf_info[hwidx]; 5570 swz = &s->sw_zone_info[hwb->zidx]; 5571 spare = swz->size - hwb->size; 5572 5573 /* no good if there isn't room for an mbuf as well */ 5574 if (spare < CL_METADATA_SIZE + MSIZE) 5575 hwidx = s->safe_hwidx1; 5576 } else 5577 hwidx = s->safe_hwidx1; 5578 5579 if (hwidx == -1) { 5580 /* No fallback source */ 5581 fl->cll_alt.hwidx = -1; 5582 fl->cll_alt.zidx = -1; 5583 5584 return; 5585 } 5586 5587 hwb = &s->hw_buf_info[hwidx]; 5588 swz = &s->sw_zone_info[hwb->zidx]; 5589 spare = swz->size - hwb->size; 5590 fl->cll_alt.hwidx = hwidx; 5591 fl->cll_alt.zidx = hwb->zidx; 5592 if (allow_mbufs_in_cluster && 5593 (fl_pad == 0 || (MSIZE % sc->params.sge.pad_boundary) == 0)) 5594 fl->cll_alt.region1 = ((spare - CL_METADATA_SIZE) / MSIZE) * MSIZE; 5595 else 5596 fl->cll_alt.region1 = 0; 5597 fl->cll_alt.region3 = spare - fl->cll_alt.region1; 5598 } 5599 5600 static void 5601 add_fl_to_sfl(struct adapter *sc, struct sge_fl *fl) 5602 { 5603 mtx_lock(&sc->sfl_lock); 5604 FL_LOCK(fl); 5605 if ((fl->flags & FL_DOOMED) == 0) { 5606 fl->flags |= FL_STARVING; 5607 TAILQ_INSERT_TAIL(&sc->sfl, fl, link); 5608 callout_reset(&sc->sfl_callout, hz / 5, refill_sfl, sc); 5609 } 5610 FL_UNLOCK(fl); 5611 mtx_unlock(&sc->sfl_lock); 5612 } 5613 5614 static void 5615 handle_wrq_egr_update(struct adapter *sc, struct sge_eq *eq) 5616 { 5617 struct sge_wrq *wrq = (void *)eq; 5618 5619 atomic_readandclear_int(&eq->equiq); 5620 taskqueue_enqueue(sc->tq[eq->tx_chan], &wrq->wrq_tx_task); 5621 } 5622 5623 static void 5624 handle_eth_egr_update(struct adapter *sc, struct sge_eq *eq) 5625 { 5626 struct sge_txq *txq = (void *)eq; 5627 5628 MPASS((eq->flags & EQ_TYPEMASK) == EQ_ETH); 5629 5630 atomic_readandclear_int(&eq->equiq); 5631 mp_ring_check_drainage(txq->r, 0); 5632 taskqueue_enqueue(sc->tq[eq->tx_chan], &txq->tx_reclaim_task); 5633 } 5634 5635 static int 5636 handle_sge_egr_update(struct sge_iq *iq, const struct rss_header *rss, 5637 struct mbuf *m) 5638 { 5639 const struct cpl_sge_egr_update *cpl = (const void *)(rss + 1); 5640 unsigned int qid = G_EGR_QID(ntohl(cpl->opcode_qid)); 5641 struct adapter *sc = iq->adapter; 5642 struct sge *s = &sc->sge; 5643 struct sge_eq *eq; 5644 static void (*h[])(struct adapter *, struct sge_eq *) = {NULL, 5645 &handle_wrq_egr_update, &handle_eth_egr_update, 5646 &handle_wrq_egr_update}; 5647 5648 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 5649 rss->opcode)); 5650 5651 eq = s->eqmap[qid - s->eq_start - s->eq_base]; 5652 (*h[eq->flags & EQ_TYPEMASK])(sc, eq); 5653 5654 return (0); 5655 } 5656 5657 /* handle_fw_msg works for both fw4_msg and fw6_msg because this is valid */ 5658 CTASSERT(offsetof(struct cpl_fw4_msg, data) == \ 5659 offsetof(struct cpl_fw6_msg, data)); 5660 5661 static int 5662 handle_fw_msg(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 5663 { 5664 struct adapter *sc = iq->adapter; 5665 const struct cpl_fw6_msg *cpl = (const void *)(rss + 1); 5666 5667 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 5668 rss->opcode)); 5669 5670 if (cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL) { 5671 const struct rss_header *rss2; 5672 5673 rss2 = (const struct rss_header *)&cpl->data[0]; 5674 return (t4_cpl_handler[rss2->opcode](iq, rss2, m)); 5675 } 5676 5677 return (t4_fw_msg_handler[cpl->type](sc, &cpl->data[0])); 5678 } 5679 5680 /** 5681 * t4_handle_wrerr_rpl - process a FW work request error message 5682 * @adap: the adapter 5683 * @rpl: start of the FW message 5684 */ 5685 static int 5686 t4_handle_wrerr_rpl(struct adapter *adap, const __be64 *rpl) 5687 { 5688 u8 opcode = *(const u8 *)rpl; 5689 const struct fw_error_cmd *e = (const void *)rpl; 5690 unsigned int i; 5691 5692 if (opcode != FW_ERROR_CMD) { 5693 log(LOG_ERR, 5694 "%s: Received WRERR_RPL message with opcode %#x\n", 5695 device_get_nameunit(adap->dev), opcode); 5696 return (EINVAL); 5697 } 5698 log(LOG_ERR, "%s: FW_ERROR (%s) ", device_get_nameunit(adap->dev), 5699 G_FW_ERROR_CMD_FATAL(be32toh(e->op_to_type)) ? "fatal" : 5700 "non-fatal"); 5701 switch (G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type))) { 5702 case FW_ERROR_TYPE_EXCEPTION: 5703 log(LOG_ERR, "exception info:\n"); 5704 for (i = 0; i < nitems(e->u.exception.info); i++) 5705 log(LOG_ERR, "%s%08x", i == 0 ? "\t" : " ", 5706 be32toh(e->u.exception.info[i])); 5707 log(LOG_ERR, "\n"); 5708 break; 5709 case FW_ERROR_TYPE_HWMODULE: 5710 log(LOG_ERR, "HW module regaddr %08x regval %08x\n", 5711 be32toh(e->u.hwmodule.regaddr), 5712 be32toh(e->u.hwmodule.regval)); 5713 break; 5714 case FW_ERROR_TYPE_WR: 5715 log(LOG_ERR, "WR cidx %d PF %d VF %d eqid %d hdr:\n", 5716 be16toh(e->u.wr.cidx), 5717 G_FW_ERROR_CMD_PFN(be16toh(e->u.wr.pfn_vfn)), 5718 G_FW_ERROR_CMD_VFN(be16toh(e->u.wr.pfn_vfn)), 5719 be32toh(e->u.wr.eqid)); 5720 for (i = 0; i < nitems(e->u.wr.wrhdr); i++) 5721 log(LOG_ERR, "%s%02x", i == 0 ? "\t" : " ", 5722 e->u.wr.wrhdr[i]); 5723 log(LOG_ERR, "\n"); 5724 break; 5725 case FW_ERROR_TYPE_ACL: 5726 log(LOG_ERR, "ACL cidx %d PF %d VF %d eqid %d %s", 5727 be16toh(e->u.acl.cidx), 5728 G_FW_ERROR_CMD_PFN(be16toh(e->u.acl.pfn_vfn)), 5729 G_FW_ERROR_CMD_VFN(be16toh(e->u.acl.pfn_vfn)), 5730 be32toh(e->u.acl.eqid), 5731 G_FW_ERROR_CMD_MV(be16toh(e->u.acl.mv_pkd)) ? "vlanid" : 5732 "MAC"); 5733 for (i = 0; i < nitems(e->u.acl.val); i++) 5734 log(LOG_ERR, " %02x", e->u.acl.val[i]); 5735 log(LOG_ERR, "\n"); 5736 break; 5737 default: 5738 log(LOG_ERR, "type %#x\n", 5739 G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type))); 5740 return (EINVAL); 5741 } 5742 return (0); 5743 } 5744 5745 static int 5746 sysctl_uint16(SYSCTL_HANDLER_ARGS) 5747 { 5748 uint16_t *id = arg1; 5749 int i = *id; 5750 5751 return sysctl_handle_int(oidp, &i, 0, req); 5752 } 5753 5754 static int 5755 sysctl_bufsizes(SYSCTL_HANDLER_ARGS) 5756 { 5757 struct sge *s = arg1; 5758 struct hw_buf_info *hwb = &s->hw_buf_info[0]; 5759 struct sw_zone_info *swz = &s->sw_zone_info[0]; 5760 int i, rc; 5761 struct sbuf sb; 5762 char c; 5763 5764 sbuf_new(&sb, NULL, 32, SBUF_AUTOEXTEND); 5765 for (i = 0; i < SGE_FLBUF_SIZES; i++, hwb++) { 5766 if (hwb->zidx >= 0 && swz[hwb->zidx].size <= largest_rx_cluster) 5767 c = '*'; 5768 else 5769 c = '\0'; 5770 5771 sbuf_printf(&sb, "%u%c ", hwb->size, c); 5772 } 5773 sbuf_trim(&sb); 5774 sbuf_finish(&sb); 5775 rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req); 5776 sbuf_delete(&sb); 5777 return (rc); 5778 } 5779 5780 #ifdef RATELIMIT 5781 /* 5782 * len16 for a txpkt WR with a GL. Includes the firmware work request header. 5783 */ 5784 static inline u_int 5785 txpkt_eo_len16(u_int nsegs, u_int immhdrs, u_int tso) 5786 { 5787 u_int n; 5788 5789 MPASS(immhdrs > 0); 5790 5791 n = roundup2(sizeof(struct fw_eth_tx_eo_wr) + 5792 sizeof(struct cpl_tx_pkt_core) + immhdrs, 16); 5793 if (__predict_false(nsegs == 0)) 5794 goto done; 5795 5796 nsegs--; /* first segment is part of ulptx_sgl */ 5797 n += sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 5798 if (tso) 5799 n += sizeof(struct cpl_tx_pkt_lso_core); 5800 5801 done: 5802 return (howmany(n, 16)); 5803 } 5804 5805 #define ETID_FLOWC_NPARAMS 6 5806 #define ETID_FLOWC_LEN (roundup2((sizeof(struct fw_flowc_wr) + \ 5807 ETID_FLOWC_NPARAMS * sizeof(struct fw_flowc_mnemval)), 16)) 5808 #define ETID_FLOWC_LEN16 (howmany(ETID_FLOWC_LEN, 16)) 5809 5810 static int 5811 send_etid_flowc_wr(struct cxgbe_rate_tag *cst, struct port_info *pi, 5812 struct vi_info *vi) 5813 { 5814 struct wrq_cookie cookie; 5815 u_int pfvf = pi->adapter->pf << S_FW_VIID_PFN; 5816 struct fw_flowc_wr *flowc; 5817 5818 mtx_assert(&cst->lock, MA_OWNED); 5819 MPASS((cst->flags & (EO_FLOWC_PENDING | EO_FLOWC_RPL_PENDING)) == 5820 EO_FLOWC_PENDING); 5821 5822 flowc = start_wrq_wr(cst->eo_txq, ETID_FLOWC_LEN16, &cookie); 5823 if (__predict_false(flowc == NULL)) 5824 return (ENOMEM); 5825 5826 bzero(flowc, ETID_FLOWC_LEN); 5827 flowc->op_to_nparams = htobe32(V_FW_WR_OP(FW_FLOWC_WR) | 5828 V_FW_FLOWC_WR_NPARAMS(ETID_FLOWC_NPARAMS) | V_FW_WR_COMPL(0)); 5829 flowc->flowid_len16 = htonl(V_FW_WR_LEN16(ETID_FLOWC_LEN16) | 5830 V_FW_WR_FLOWID(cst->etid)); 5831 flowc->mnemval[0].mnemonic = FW_FLOWC_MNEM_PFNVFN; 5832 flowc->mnemval[0].val = htobe32(pfvf); 5833 flowc->mnemval[1].mnemonic = FW_FLOWC_MNEM_CH; 5834 flowc->mnemval[1].val = htobe32(pi->tx_chan); 5835 flowc->mnemval[2].mnemonic = FW_FLOWC_MNEM_PORT; 5836 flowc->mnemval[2].val = htobe32(pi->tx_chan); 5837 flowc->mnemval[3].mnemonic = FW_FLOWC_MNEM_IQID; 5838 flowc->mnemval[3].val = htobe32(cst->iqid); 5839 flowc->mnemval[4].mnemonic = FW_FLOWC_MNEM_EOSTATE; 5840 flowc->mnemval[4].val = htobe32(FW_FLOWC_MNEM_EOSTATE_ESTABLISHED); 5841 flowc->mnemval[5].mnemonic = FW_FLOWC_MNEM_SCHEDCLASS; 5842 flowc->mnemval[5].val = htobe32(cst->schedcl); 5843 5844 commit_wrq_wr(cst->eo_txq, flowc, &cookie); 5845 5846 cst->flags &= ~EO_FLOWC_PENDING; 5847 cst->flags |= EO_FLOWC_RPL_PENDING; 5848 MPASS(cst->tx_credits >= ETID_FLOWC_LEN16); /* flowc is first WR. */ 5849 cst->tx_credits -= ETID_FLOWC_LEN16; 5850 5851 return (0); 5852 } 5853 5854 #define ETID_FLUSH_LEN16 (howmany(sizeof (struct fw_flowc_wr), 16)) 5855 5856 void 5857 send_etid_flush_wr(struct cxgbe_rate_tag *cst) 5858 { 5859 struct fw_flowc_wr *flowc; 5860 struct wrq_cookie cookie; 5861 5862 mtx_assert(&cst->lock, MA_OWNED); 5863 5864 flowc = start_wrq_wr(cst->eo_txq, ETID_FLUSH_LEN16, &cookie); 5865 if (__predict_false(flowc == NULL)) 5866 CXGBE_UNIMPLEMENTED(__func__); 5867 5868 bzero(flowc, ETID_FLUSH_LEN16 * 16); 5869 flowc->op_to_nparams = htobe32(V_FW_WR_OP(FW_FLOWC_WR) | 5870 V_FW_FLOWC_WR_NPARAMS(0) | F_FW_WR_COMPL); 5871 flowc->flowid_len16 = htobe32(V_FW_WR_LEN16(ETID_FLUSH_LEN16) | 5872 V_FW_WR_FLOWID(cst->etid)); 5873 5874 commit_wrq_wr(cst->eo_txq, flowc, &cookie); 5875 5876 cst->flags |= EO_FLUSH_RPL_PENDING; 5877 MPASS(cst->tx_credits >= ETID_FLUSH_LEN16); 5878 cst->tx_credits -= ETID_FLUSH_LEN16; 5879 cst->ncompl++; 5880 } 5881 5882 static void 5883 write_ethofld_wr(struct cxgbe_rate_tag *cst, struct fw_eth_tx_eo_wr *wr, 5884 struct mbuf *m0, int compl) 5885 { 5886 struct cpl_tx_pkt_core *cpl; 5887 uint64_t ctrl1; 5888 uint32_t ctrl; /* used in many unrelated places */ 5889 int len16, pktlen, nsegs, immhdrs; 5890 caddr_t dst; 5891 uintptr_t p; 5892 struct ulptx_sgl *usgl; 5893 struct sglist sg; 5894 struct sglist_seg segs[38]; /* XXX: find real limit. XXX: get off the stack */ 5895 5896 mtx_assert(&cst->lock, MA_OWNED); 5897 M_ASSERTPKTHDR(m0); 5898 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 5899 m0->m_pkthdr.l4hlen > 0, 5900 ("%s: ethofld mbuf %p is missing header lengths", __func__, m0)); 5901 5902 len16 = mbuf_eo_len16(m0); 5903 nsegs = mbuf_eo_nsegs(m0); 5904 pktlen = m0->m_pkthdr.len; 5905 ctrl = sizeof(struct cpl_tx_pkt_core); 5906 if (needs_tso(m0)) 5907 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 5908 immhdrs = m0->m_pkthdr.l2hlen + m0->m_pkthdr.l3hlen + m0->m_pkthdr.l4hlen; 5909 ctrl += immhdrs; 5910 5911 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_EO_WR) | 5912 V_FW_ETH_TX_EO_WR_IMMDLEN(ctrl) | V_FW_WR_COMPL(!!compl)); 5913 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(len16) | 5914 V_FW_WR_FLOWID(cst->etid)); 5915 wr->r3 = 0; 5916 if (needs_udp_csum(m0)) { 5917 wr->u.udpseg.type = FW_ETH_TX_EO_TYPE_UDPSEG; 5918 wr->u.udpseg.ethlen = m0->m_pkthdr.l2hlen; 5919 wr->u.udpseg.iplen = htobe16(m0->m_pkthdr.l3hlen); 5920 wr->u.udpseg.udplen = m0->m_pkthdr.l4hlen; 5921 wr->u.udpseg.rtplen = 0; 5922 wr->u.udpseg.r4 = 0; 5923 wr->u.udpseg.mss = htobe16(pktlen - immhdrs); 5924 wr->u.udpseg.schedpktsize = wr->u.udpseg.mss; 5925 wr->u.udpseg.plen = htobe32(pktlen - immhdrs); 5926 cpl = (void *)(wr + 1); 5927 } else { 5928 MPASS(needs_tcp_csum(m0)); 5929 wr->u.tcpseg.type = FW_ETH_TX_EO_TYPE_TCPSEG; 5930 wr->u.tcpseg.ethlen = m0->m_pkthdr.l2hlen; 5931 wr->u.tcpseg.iplen = htobe16(m0->m_pkthdr.l3hlen); 5932 wr->u.tcpseg.tcplen = m0->m_pkthdr.l4hlen; 5933 wr->u.tcpseg.tsclk_tsoff = mbuf_eo_tsclk_tsoff(m0); 5934 wr->u.tcpseg.r4 = 0; 5935 wr->u.tcpseg.r5 = 0; 5936 wr->u.tcpseg.plen = htobe32(pktlen - immhdrs); 5937 5938 if (needs_tso(m0)) { 5939 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1); 5940 5941 wr->u.tcpseg.mss = htobe16(m0->m_pkthdr.tso_segsz); 5942 5943 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | 5944 F_LSO_FIRST_SLICE | F_LSO_LAST_SLICE | 5945 V_LSO_ETHHDR_LEN((m0->m_pkthdr.l2hlen - 5946 ETHER_HDR_LEN) >> 2) | 5947 V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) | 5948 V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2); 5949 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 5950 ctrl |= F_LSO_IPV6; 5951 lso->lso_ctrl = htobe32(ctrl); 5952 lso->ipid_ofst = htobe16(0); 5953 lso->mss = htobe16(m0->m_pkthdr.tso_segsz); 5954 lso->seqno_offset = htobe32(0); 5955 lso->len = htobe32(pktlen); 5956 5957 cpl = (void *)(lso + 1); 5958 } else { 5959 wr->u.tcpseg.mss = htobe16(0xffff); 5960 cpl = (void *)(wr + 1); 5961 } 5962 } 5963 5964 /* Checksum offload must be requested for ethofld. */ 5965 MPASS(needs_l4_csum(m0)); 5966 ctrl1 = csum_to_ctrl(cst->adapter, m0); 5967 5968 /* VLAN tag insertion */ 5969 if (needs_vlan_insertion(m0)) { 5970 ctrl1 |= F_TXPKT_VLAN_VLD | 5971 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 5972 } 5973 5974 /* CPL header */ 5975 cpl->ctrl0 = cst->ctrl0; 5976 cpl->pack = 0; 5977 cpl->len = htobe16(pktlen); 5978 cpl->ctrl1 = htobe64(ctrl1); 5979 5980 /* Copy Ethernet, IP & TCP/UDP hdrs as immediate data */ 5981 p = (uintptr_t)(cpl + 1); 5982 m_copydata(m0, 0, immhdrs, (void *)p); 5983 5984 /* SGL */ 5985 dst = (void *)(cpl + 1); 5986 if (nsegs > 0) { 5987 int i, pad; 5988 5989 /* zero-pad upto next 16Byte boundary, if not 16Byte aligned */ 5990 p += immhdrs; 5991 pad = 16 - (immhdrs & 0xf); 5992 bzero((void *)p, pad); 5993 5994 usgl = (void *)(p + pad); 5995 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 5996 V_ULPTX_NSGE(nsegs)); 5997 5998 sglist_init(&sg, nitems(segs), segs); 5999 for (; m0 != NULL; m0 = m0->m_next) { 6000 if (__predict_false(m0->m_len == 0)) 6001 continue; 6002 if (immhdrs >= m0->m_len) { 6003 immhdrs -= m0->m_len; 6004 continue; 6005 } 6006 6007 sglist_append(&sg, mtod(m0, char *) + immhdrs, 6008 m0->m_len - immhdrs); 6009 immhdrs = 0; 6010 } 6011 MPASS(sg.sg_nseg == nsegs); 6012 6013 /* 6014 * Zero pad last 8B in case the WR doesn't end on a 16B 6015 * boundary. 6016 */ 6017 *(uint64_t *)((char *)wr + len16 * 16 - 8) = 0; 6018 6019 usgl->len0 = htobe32(segs[0].ss_len); 6020 usgl->addr0 = htobe64(segs[0].ss_paddr); 6021 for (i = 0; i < nsegs - 1; i++) { 6022 usgl->sge[i / 2].len[i & 1] = htobe32(segs[i + 1].ss_len); 6023 usgl->sge[i / 2].addr[i & 1] = htobe64(segs[i + 1].ss_paddr); 6024 } 6025 if (i & 1) 6026 usgl->sge[i / 2].len[1] = htobe32(0); 6027 } 6028 6029 } 6030 6031 static void 6032 ethofld_tx(struct cxgbe_rate_tag *cst) 6033 { 6034 struct mbuf *m; 6035 struct wrq_cookie cookie; 6036 int next_credits, compl; 6037 struct fw_eth_tx_eo_wr *wr; 6038 6039 mtx_assert(&cst->lock, MA_OWNED); 6040 6041 while ((m = mbufq_first(&cst->pending_tx)) != NULL) { 6042 M_ASSERTPKTHDR(m); 6043 6044 /* How many len16 credits do we need to send this mbuf. */ 6045 next_credits = mbuf_eo_len16(m); 6046 MPASS(next_credits > 0); 6047 if (next_credits > cst->tx_credits) { 6048 /* 6049 * Tx will make progress eventually because there is at 6050 * least one outstanding fw4_ack that will return 6051 * credits and kick the tx. 6052 */ 6053 MPASS(cst->ncompl > 0); 6054 return; 6055 } 6056 wr = start_wrq_wr(cst->eo_txq, next_credits, &cookie); 6057 if (__predict_false(wr == NULL)) { 6058 /* XXX: wishful thinking, not a real assertion. */ 6059 MPASS(cst->ncompl > 0); 6060 return; 6061 } 6062 cst->tx_credits -= next_credits; 6063 cst->tx_nocompl += next_credits; 6064 compl = cst->ncompl == 0 || cst->tx_nocompl >= cst->tx_total / 2; 6065 ETHER_BPF_MTAP(cst->com.com.ifp, m); 6066 write_ethofld_wr(cst, wr, m, compl); 6067 commit_wrq_wr(cst->eo_txq, wr, &cookie); 6068 if (compl) { 6069 cst->ncompl++; 6070 cst->tx_nocompl = 0; 6071 } 6072 (void) mbufq_dequeue(&cst->pending_tx); 6073 6074 /* 6075 * Drop the mbuf's reference on the tag now rather 6076 * than waiting until m_freem(). This ensures that 6077 * cxgbe_rate_tag_free gets called when the inp drops 6078 * its reference on the tag and there are no more 6079 * mbufs in the pending_tx queue and can flush any 6080 * pending requests. Otherwise if the last mbuf 6081 * doesn't request a completion the etid will never be 6082 * released. 6083 */ 6084 m->m_pkthdr.snd_tag = NULL; 6085 m->m_pkthdr.csum_flags &= ~CSUM_SND_TAG; 6086 m_snd_tag_rele(&cst->com.com); 6087 6088 mbufq_enqueue(&cst->pending_fwack, m); 6089 } 6090 } 6091 6092 int 6093 ethofld_transmit(struct ifnet *ifp, struct mbuf *m0) 6094 { 6095 struct cxgbe_rate_tag *cst; 6096 int rc; 6097 6098 MPASS(m0->m_nextpkt == NULL); 6099 MPASS(m0->m_pkthdr.csum_flags & CSUM_SND_TAG); 6100 MPASS(m0->m_pkthdr.snd_tag != NULL); 6101 cst = mst_to_crt(m0->m_pkthdr.snd_tag); 6102 6103 mtx_lock(&cst->lock); 6104 MPASS(cst->flags & EO_SND_TAG_REF); 6105 6106 if (__predict_false(cst->flags & EO_FLOWC_PENDING)) { 6107 struct vi_info *vi = ifp->if_softc; 6108 struct port_info *pi = vi->pi; 6109 struct adapter *sc = pi->adapter; 6110 const uint32_t rss_mask = vi->rss_size - 1; 6111 uint32_t rss_hash; 6112 6113 cst->eo_txq = &sc->sge.ofld_txq[vi->first_ofld_txq]; 6114 if (M_HASHTYPE_ISHASH(m0)) 6115 rss_hash = m0->m_pkthdr.flowid; 6116 else 6117 rss_hash = arc4random(); 6118 /* We assume RSS hashing */ 6119 cst->iqid = vi->rss[rss_hash & rss_mask]; 6120 cst->eo_txq += rss_hash % vi->nofldtxq; 6121 rc = send_etid_flowc_wr(cst, pi, vi); 6122 if (rc != 0) 6123 goto done; 6124 } 6125 6126 if (__predict_false(cst->plen + m0->m_pkthdr.len > eo_max_backlog)) { 6127 rc = ENOBUFS; 6128 goto done; 6129 } 6130 6131 mbufq_enqueue(&cst->pending_tx, m0); 6132 cst->plen += m0->m_pkthdr.len; 6133 6134 /* 6135 * Hold an extra reference on the tag while generating work 6136 * requests to ensure that we don't try to free the tag during 6137 * ethofld_tx() in case we are sending the final mbuf after 6138 * the inp was freed. 6139 */ 6140 m_snd_tag_ref(&cst->com.com); 6141 ethofld_tx(cst); 6142 mtx_unlock(&cst->lock); 6143 m_snd_tag_rele(&cst->com.com); 6144 return (0); 6145 6146 done: 6147 mtx_unlock(&cst->lock); 6148 if (__predict_false(rc != 0)) 6149 m_freem(m0); 6150 return (rc); 6151 } 6152 6153 static int 6154 ethofld_fw4_ack(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0) 6155 { 6156 struct adapter *sc = iq->adapter; 6157 const struct cpl_fw4_ack *cpl = (const void *)(rss + 1); 6158 struct mbuf *m; 6159 u_int etid = G_CPL_FW4_ACK_FLOWID(be32toh(OPCODE_TID(cpl))); 6160 struct cxgbe_rate_tag *cst; 6161 uint8_t credits = cpl->credits; 6162 6163 cst = lookup_etid(sc, etid); 6164 mtx_lock(&cst->lock); 6165 if (__predict_false(cst->flags & EO_FLOWC_RPL_PENDING)) { 6166 MPASS(credits >= ETID_FLOWC_LEN16); 6167 credits -= ETID_FLOWC_LEN16; 6168 cst->flags &= ~EO_FLOWC_RPL_PENDING; 6169 } 6170 6171 KASSERT(cst->ncompl > 0, 6172 ("%s: etid %u (%p) wasn't expecting completion.", 6173 __func__, etid, cst)); 6174 cst->ncompl--; 6175 6176 while (credits > 0) { 6177 m = mbufq_dequeue(&cst->pending_fwack); 6178 if (__predict_false(m == NULL)) { 6179 /* 6180 * The remaining credits are for the final flush that 6181 * was issued when the tag was freed by the kernel. 6182 */ 6183 MPASS((cst->flags & 6184 (EO_FLUSH_RPL_PENDING | EO_SND_TAG_REF)) == 6185 EO_FLUSH_RPL_PENDING); 6186 MPASS(credits == ETID_FLUSH_LEN16); 6187 MPASS(cst->tx_credits + cpl->credits == cst->tx_total); 6188 MPASS(cst->ncompl == 0); 6189 6190 cst->flags &= ~EO_FLUSH_RPL_PENDING; 6191 cst->tx_credits += cpl->credits; 6192 cxgbe_rate_tag_free_locked(cst); 6193 return (0); /* cst is gone. */ 6194 } 6195 KASSERT(m != NULL, 6196 ("%s: too many credits (%u, %u)", __func__, cpl->credits, 6197 credits)); 6198 KASSERT(credits >= mbuf_eo_len16(m), 6199 ("%s: too few credits (%u, %u, %u)", __func__, 6200 cpl->credits, credits, mbuf_eo_len16(m))); 6201 credits -= mbuf_eo_len16(m); 6202 cst->plen -= m->m_pkthdr.len; 6203 m_freem(m); 6204 } 6205 6206 cst->tx_credits += cpl->credits; 6207 MPASS(cst->tx_credits <= cst->tx_total); 6208 6209 if (cst->flags & EO_SND_TAG_REF) { 6210 /* 6211 * As with ethofld_transmit(), hold an extra reference 6212 * so that the tag is stable across ethold_tx(). 6213 */ 6214 m_snd_tag_ref(&cst->com.com); 6215 m = mbufq_first(&cst->pending_tx); 6216 if (m != NULL && cst->tx_credits >= mbuf_eo_len16(m)) 6217 ethofld_tx(cst); 6218 mtx_unlock(&cst->lock); 6219 m_snd_tag_rele(&cst->com.com); 6220 } else { 6221 /* 6222 * There shouldn't be any pending packets if the tag 6223 * was freed by the kernel since any pending packet 6224 * should hold a reference to the tag. 6225 */ 6226 MPASS(mbufq_first(&cst->pending_tx) == NULL); 6227 mtx_unlock(&cst->lock); 6228 } 6229 6230 return (0); 6231 } 6232 #endif 6233