1 /*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 34 #include <sys/types.h> 35 #include <sys/mbuf.h> 36 #include <sys/socket.h> 37 #include <sys/kernel.h> 38 #include <sys/kdb.h> 39 #include <sys/malloc.h> 40 #include <sys/queue.h> 41 #include <sys/taskqueue.h> 42 #include <sys/sysctl.h> 43 #include <sys/smp.h> 44 #include <net/bpf.h> 45 #include <net/ethernet.h> 46 #include <net/if.h> 47 #include <net/if_vlan_var.h> 48 #include <netinet/in.h> 49 #include <netinet/ip.h> 50 #include <netinet/ip6.h> 51 #include <netinet/tcp.h> 52 53 #include "common/common.h" 54 #include "common/t4_regs.h" 55 #include "common/t4_regs_values.h" 56 #include "common/t4_msg.h" 57 58 struct fl_buf_info { 59 int size; 60 int type; 61 uma_zone_t zone; 62 }; 63 64 /* Filled up by t4_sge_modload */ 65 static struct fl_buf_info fl_buf_info[FL_BUF_SIZES]; 66 67 #define FL_BUF_SIZE(x) (fl_buf_info[x].size) 68 #define FL_BUF_TYPE(x) (fl_buf_info[x].type) 69 #define FL_BUF_ZONE(x) (fl_buf_info[x].zone) 70 71 #ifdef T4_PKT_TIMESTAMP 72 #define RX_COPY_THRESHOLD (MINCLSIZE - 8) 73 #else 74 #define RX_COPY_THRESHOLD MINCLSIZE 75 #endif 76 77 /* 78 * Ethernet frames are DMA'd at this byte offset into the freelist buffer. 79 * 0-7 are valid values. 80 */ 81 static int fl_pktshift = 2; 82 TUNABLE_INT("hw.cxgbe.fl_pktshift", &fl_pktshift); 83 84 /* 85 * Pad ethernet payload up to this boundary. 86 * -1: driver should figure out a good value. 87 * Any power of 2, from 32 to 4096 (both inclusive) is a valid value. 88 */ 89 static int fl_pad = -1; 90 TUNABLE_INT("hw.cxgbe.fl_pad", &fl_pad); 91 92 /* 93 * Status page length. 94 * -1: driver should figure out a good value. 95 * 64 or 128 are the only other valid values. 96 */ 97 static int spg_len = -1; 98 TUNABLE_INT("hw.cxgbe.spg_len", &spg_len); 99 100 /* 101 * Congestion drops. 102 * -1: no congestion feedback (not recommended). 103 * 0: backpressure the channel instead of dropping packets right away. 104 * 1: no backpressure, drop packets for the congested queue immediately. 105 */ 106 static int cong_drop = 0; 107 TUNABLE_INT("hw.cxgbe.cong_drop", &cong_drop); 108 109 /* Used to track coalesced tx work request */ 110 struct txpkts { 111 uint64_t *flitp; /* ptr to flit where next pkt should start */ 112 uint8_t npkt; /* # of packets in this work request */ 113 uint8_t nflits; /* # of flits used by this work request */ 114 uint16_t plen; /* total payload (sum of all packets) */ 115 }; 116 117 /* A packet's SGL. This + m_pkthdr has all info needed for tx */ 118 struct sgl { 119 int nsegs; /* # of segments in the SGL, 0 means imm. tx */ 120 int nflits; /* # of flits needed for the SGL */ 121 bus_dma_segment_t seg[TX_SGL_SEGS]; 122 }; 123 124 static int service_iq(struct sge_iq *, int); 125 static struct mbuf *get_fl_payload(struct adapter *, struct sge_fl *, uint32_t, 126 int *); 127 static int t4_eth_rx(struct sge_iq *, const struct rss_header *, struct mbuf *); 128 static inline void init_iq(struct sge_iq *, struct adapter *, int, int, int, 129 int); 130 static inline void init_fl(struct sge_fl *, int, int, char *); 131 static inline void init_eq(struct sge_eq *, int, int, uint8_t, uint16_t, 132 char *); 133 static int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *, 134 bus_addr_t *, void **); 135 static int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 136 void *); 137 static int alloc_iq_fl(struct port_info *, struct sge_iq *, struct sge_fl *, 138 int, int); 139 static int free_iq_fl(struct port_info *, struct sge_iq *, struct sge_fl *); 140 static int alloc_fwq(struct adapter *); 141 static int free_fwq(struct adapter *); 142 static int alloc_mgmtq(struct adapter *); 143 static int free_mgmtq(struct adapter *); 144 static int alloc_rxq(struct port_info *, struct sge_rxq *, int, int, 145 struct sysctl_oid *); 146 static int free_rxq(struct port_info *, struct sge_rxq *); 147 #ifdef TCP_OFFLOAD 148 static int alloc_ofld_rxq(struct port_info *, struct sge_ofld_rxq *, int, int, 149 struct sysctl_oid *); 150 static int free_ofld_rxq(struct port_info *, struct sge_ofld_rxq *); 151 #endif 152 static int ctrl_eq_alloc(struct adapter *, struct sge_eq *); 153 static int eth_eq_alloc(struct adapter *, struct port_info *, struct sge_eq *); 154 #ifdef TCP_OFFLOAD 155 static int ofld_eq_alloc(struct adapter *, struct port_info *, struct sge_eq *); 156 #endif 157 static int alloc_eq(struct adapter *, struct port_info *, struct sge_eq *); 158 static int free_eq(struct adapter *, struct sge_eq *); 159 static int alloc_wrq(struct adapter *, struct port_info *, struct sge_wrq *, 160 struct sysctl_oid *); 161 static int free_wrq(struct adapter *, struct sge_wrq *); 162 static int alloc_txq(struct port_info *, struct sge_txq *, int, 163 struct sysctl_oid *); 164 static int free_txq(struct port_info *, struct sge_txq *); 165 static void oneseg_dma_callback(void *, bus_dma_segment_t *, int, int); 166 static inline bool is_new_response(const struct sge_iq *, struct rsp_ctrl **); 167 static inline void iq_next(struct sge_iq *); 168 static inline void ring_fl_db(struct adapter *, struct sge_fl *); 169 static int refill_fl(struct adapter *, struct sge_fl *, int); 170 static void refill_sfl(void *); 171 static int alloc_fl_sdesc(struct sge_fl *); 172 static void free_fl_sdesc(struct sge_fl *); 173 static void set_fl_tag_idx(struct sge_fl *, int); 174 static void add_fl_to_sfl(struct adapter *, struct sge_fl *); 175 176 static int get_pkt_sgl(struct sge_txq *, struct mbuf **, struct sgl *, int); 177 static int free_pkt_sgl(struct sge_txq *, struct sgl *); 178 static int write_txpkt_wr(struct port_info *, struct sge_txq *, struct mbuf *, 179 struct sgl *); 180 static int add_to_txpkts(struct port_info *, struct sge_txq *, struct txpkts *, 181 struct mbuf *, struct sgl *); 182 static void write_txpkts_wr(struct sge_txq *, struct txpkts *); 183 static inline void write_ulp_cpl_sgl(struct port_info *, struct sge_txq *, 184 struct txpkts *, struct mbuf *, struct sgl *); 185 static int write_sgl_to_txd(struct sge_eq *, struct sgl *, caddr_t *); 186 static inline void copy_to_txd(struct sge_eq *, caddr_t, caddr_t *, int); 187 static inline void ring_eq_db(struct adapter *, struct sge_eq *); 188 static inline int reclaimable(struct sge_eq *); 189 static int reclaim_tx_descs(struct sge_txq *, int, int); 190 static void write_eqflush_wr(struct sge_eq *); 191 static __be64 get_flit(bus_dma_segment_t *, int, int); 192 static int handle_sge_egr_update(struct sge_iq *, const struct rss_header *, 193 struct mbuf *); 194 static int handle_fw_msg(struct sge_iq *, const struct rss_header *, 195 struct mbuf *); 196 197 static int sysctl_uint16(SYSCTL_HANDLER_ARGS); 198 199 #if defined(__i386__) || defined(__amd64__) 200 extern u_int cpu_clflush_line_size; 201 #endif 202 203 /* 204 * Called on MOD_LOAD. Fills up fl_buf_info[] and validates/calculates the SGE 205 * tunables. 206 */ 207 void 208 t4_sge_modload(void) 209 { 210 int i; 211 int bufsize[FL_BUF_SIZES] = { 212 MCLBYTES, 213 #if MJUMPAGESIZE != MCLBYTES 214 MJUMPAGESIZE, 215 #endif 216 MJUM9BYTES, 217 MJUM16BYTES 218 }; 219 220 for (i = 0; i < FL_BUF_SIZES; i++) { 221 FL_BUF_SIZE(i) = bufsize[i]; 222 FL_BUF_TYPE(i) = m_gettype(bufsize[i]); 223 FL_BUF_ZONE(i) = m_getzone(bufsize[i]); 224 } 225 226 if (fl_pktshift < 0 || fl_pktshift > 7) { 227 printf("Invalid hw.cxgbe.fl_pktshift value (%d)," 228 " using 2 instead.\n", fl_pktshift); 229 fl_pktshift = 2; 230 } 231 232 if (fl_pad < 32 || fl_pad > 4096 || !powerof2(fl_pad)) { 233 int pad; 234 235 #if defined(__i386__) || defined(__amd64__) 236 pad = max(cpu_clflush_line_size, 32); 237 #else 238 pad = max(CACHE_LINE_SIZE, 32); 239 #endif 240 pad = min(pad, 4096); 241 242 if (fl_pad != -1) { 243 printf("Invalid hw.cxgbe.fl_pad value (%d)," 244 " using %d instead.\n", fl_pad, pad); 245 } 246 fl_pad = pad; 247 } 248 249 if (spg_len != 64 && spg_len != 128) { 250 int len; 251 252 #if defined(__i386__) || defined(__amd64__) 253 len = cpu_clflush_line_size > 64 ? 128 : 64; 254 #else 255 len = 64; 256 #endif 257 if (spg_len != -1) { 258 printf("Invalid hw.cxgbe.spg_len value (%d)," 259 " using %d instead.\n", spg_len, len); 260 } 261 spg_len = len; 262 } 263 264 if (cong_drop < -1 || cong_drop > 1) { 265 printf("Invalid hw.cxgbe.cong_drop value (%d)," 266 " using 0 instead.\n", cong_drop); 267 cong_drop = 0; 268 } 269 } 270 271 void 272 t4_init_sge_cpl_handlers(struct adapter *sc) 273 { 274 275 t4_register_cpl_handler(sc, CPL_FW4_MSG, handle_fw_msg); 276 t4_register_cpl_handler(sc, CPL_FW6_MSG, handle_fw_msg); 277 t4_register_cpl_handler(sc, CPL_SGE_EGR_UPDATE, handle_sge_egr_update); 278 t4_register_cpl_handler(sc, CPL_RX_PKT, t4_eth_rx); 279 t4_register_fw_msg_handler(sc, FW6_TYPE_CMD_RPL, t4_handle_fw_rpl); 280 } 281 282 /* 283 * adap->params.vpd.cclk must be set up before this is called. 284 */ 285 void 286 t4_tweak_chip_settings(struct adapter *sc) 287 { 288 int i; 289 uint32_t v, m; 290 int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200}; 291 int timer_max = M_TIMERVALUE0 * 1000 / sc->params.vpd.cclk; 292 int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */ 293 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 294 295 KASSERT(sc->flags & MASTER_PF, 296 ("%s: trying to change chip settings when not master.", __func__)); 297 298 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | 299 V_INGPADBOUNDARY(M_INGPADBOUNDARY) | F_EGRSTATUSPAGESIZE; 300 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE | 301 V_INGPADBOUNDARY(ilog2(fl_pad) - 5) | 302 V_EGRSTATUSPAGESIZE(spg_len == 128); 303 t4_set_reg_field(sc, A_SGE_CONTROL, m, v); 304 305 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) | 306 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) | 307 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) | 308 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) | 309 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) | 310 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) | 311 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) | 312 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10); 313 t4_write_reg(sc, A_SGE_HOST_PAGE_SIZE, v); 314 315 for (i = 0; i < FL_BUF_SIZES; i++) { 316 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0 + (4 * i), 317 FL_BUF_SIZE(i)); 318 } 319 320 v = V_THRESHOLD_0(intr_pktcount[0]) | V_THRESHOLD_1(intr_pktcount[1]) | 321 V_THRESHOLD_2(intr_pktcount[2]) | V_THRESHOLD_3(intr_pktcount[3]); 322 t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD, v); 323 324 KASSERT(intr_timer[0] <= timer_max, 325 ("%s: not a single usable timer (%d, %d)", __func__, intr_timer[0], 326 timer_max)); 327 for (i = 1; i < nitems(intr_timer); i++) { 328 KASSERT(intr_timer[i] >= intr_timer[i - 1], 329 ("%s: timers not listed in increasing order (%d)", 330 __func__, i)); 331 332 while (intr_timer[i] > timer_max) { 333 if (i == nitems(intr_timer) - 1) { 334 intr_timer[i] = timer_max; 335 break; 336 } 337 intr_timer[i] += intr_timer[i - 1]; 338 intr_timer[i] /= 2; 339 } 340 } 341 342 v = V_TIMERVALUE0(us_to_core_ticks(sc, intr_timer[0])) | 343 V_TIMERVALUE1(us_to_core_ticks(sc, intr_timer[1])); 344 t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1, v); 345 v = V_TIMERVALUE2(us_to_core_ticks(sc, intr_timer[2])) | 346 V_TIMERVALUE3(us_to_core_ticks(sc, intr_timer[3])); 347 t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3, v); 348 v = V_TIMERVALUE4(us_to_core_ticks(sc, intr_timer[4])) | 349 V_TIMERVALUE5(us_to_core_ticks(sc, intr_timer[5])); 350 t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5, v); 351 352 if (cong_drop == 0) { 353 m = F_TUNNELCNGDROP0 | F_TUNNELCNGDROP1 | F_TUNNELCNGDROP2 | 354 F_TUNNELCNGDROP3; 355 t4_set_reg_field(sc, A_TP_PARA_REG3, m, 0); 356 } 357 358 /* 4K, 16K, 64K, 256K DDP "page sizes" */ 359 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 360 t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, v); 361 362 m = v = F_TDDPTAGTCB; 363 t4_set_reg_field(sc, A_ULP_RX_CTL, m, v); 364 365 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 366 F_RESETDDPOFFSET; 367 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 368 t4_set_reg_field(sc, A_TP_PARA_REG5, m, v); 369 } 370 371 /* 372 * XXX: driver really should be able to deal with unexpected settings. 373 */ 374 int 375 t4_read_chip_settings(struct adapter *sc) 376 { 377 struct sge *s = &sc->sge; 378 int i, rc = 0; 379 uint32_t m, v, r; 380 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 381 382 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | 383 V_INGPADBOUNDARY(M_INGPADBOUNDARY) | F_EGRSTATUSPAGESIZE; 384 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE | 385 V_INGPADBOUNDARY(ilog2(fl_pad) - 5) | 386 V_EGRSTATUSPAGESIZE(spg_len == 128); 387 r = t4_read_reg(sc, A_SGE_CONTROL); 388 if ((r & m) != v) { 389 device_printf(sc->dev, "invalid SGE_CONTROL(0x%x)\n", r); 390 rc = EINVAL; 391 } 392 393 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) | 394 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) | 395 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) | 396 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) | 397 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) | 398 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) | 399 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) | 400 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10); 401 r = t4_read_reg(sc, A_SGE_HOST_PAGE_SIZE); 402 if (r != v) { 403 device_printf(sc->dev, "invalid SGE_HOST_PAGE_SIZE(0x%x)\n", r); 404 rc = EINVAL; 405 } 406 407 for (i = 0; i < FL_BUF_SIZES; i++) { 408 v = t4_read_reg(sc, A_SGE_FL_BUFFER_SIZE0 + (4 * i)); 409 if (v != FL_BUF_SIZE(i)) { 410 device_printf(sc->dev, 411 "invalid SGE_FL_BUFFER_SIZE[%d](0x%x)\n", i, v); 412 rc = EINVAL; 413 } 414 } 415 416 r = t4_read_reg(sc, A_SGE_INGRESS_RX_THRESHOLD); 417 s->counter_val[0] = G_THRESHOLD_0(r); 418 s->counter_val[1] = G_THRESHOLD_1(r); 419 s->counter_val[2] = G_THRESHOLD_2(r); 420 s->counter_val[3] = G_THRESHOLD_3(r); 421 422 r = t4_read_reg(sc, A_SGE_TIMER_VALUE_0_AND_1); 423 s->timer_val[0] = G_TIMERVALUE0(r) / core_ticks_per_usec(sc); 424 s->timer_val[1] = G_TIMERVALUE1(r) / core_ticks_per_usec(sc); 425 r = t4_read_reg(sc, A_SGE_TIMER_VALUE_2_AND_3); 426 s->timer_val[2] = G_TIMERVALUE2(r) / core_ticks_per_usec(sc); 427 s->timer_val[3] = G_TIMERVALUE3(r) / core_ticks_per_usec(sc); 428 r = t4_read_reg(sc, A_SGE_TIMER_VALUE_4_AND_5); 429 s->timer_val[4] = G_TIMERVALUE4(r) / core_ticks_per_usec(sc); 430 s->timer_val[5] = G_TIMERVALUE5(r) / core_ticks_per_usec(sc); 431 432 if (cong_drop == 0) { 433 m = F_TUNNELCNGDROP0 | F_TUNNELCNGDROP1 | F_TUNNELCNGDROP2 | 434 F_TUNNELCNGDROP3; 435 r = t4_read_reg(sc, A_TP_PARA_REG3); 436 if (r & m) { 437 device_printf(sc->dev, 438 "invalid TP_PARA_REG3(0x%x)\n", r); 439 rc = EINVAL; 440 } 441 } 442 443 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 444 r = t4_read_reg(sc, A_ULP_RX_TDDP_PSZ); 445 if (r != v) { 446 device_printf(sc->dev, "invalid ULP_RX_TDDP_PSZ(0x%x)\n", r); 447 rc = EINVAL; 448 } 449 450 m = v = F_TDDPTAGTCB; 451 r = t4_read_reg(sc, A_ULP_RX_CTL); 452 if ((r & m) != v) { 453 device_printf(sc->dev, "invalid ULP_RX_CTL(0x%x)\n", r); 454 rc = EINVAL; 455 } 456 457 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 458 F_RESETDDPOFFSET; 459 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 460 r = t4_read_reg(sc, A_TP_PARA_REG5); 461 if ((r & m) != v) { 462 device_printf(sc->dev, "invalid TP_PARA_REG5(0x%x)\n", r); 463 rc = EINVAL; 464 } 465 466 r = t4_read_reg(sc, A_SGE_CONM_CTRL); 467 s->fl_starve_threshold = G_EGRTHRESHOLD(r) * 2 + 1; 468 469 if (is_t5(sc)) { 470 r = t4_read_reg(sc, A_SGE_EGRESS_QUEUES_PER_PAGE_PF); 471 r >>= S_QUEUESPERPAGEPF0 + 472 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * sc->pf; 473 s->s_qpp = r & M_QUEUESPERPAGEPF0; 474 } 475 476 t4_init_tp_params(sc); 477 478 t4_read_mtu_tbl(sc, sc->params.mtus, NULL); 479 t4_load_mtus(sc, sc->params.mtus, sc->params.a_wnd, sc->params.b_wnd); 480 481 return (rc); 482 } 483 484 int 485 t4_create_dma_tag(struct adapter *sc) 486 { 487 int rc; 488 489 rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0, 490 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE, 491 BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL, 492 NULL, &sc->dmat); 493 if (rc != 0) { 494 device_printf(sc->dev, 495 "failed to create main DMA tag: %d\n", rc); 496 } 497 498 return (rc); 499 } 500 501 int 502 t4_destroy_dma_tag(struct adapter *sc) 503 { 504 if (sc->dmat) 505 bus_dma_tag_destroy(sc->dmat); 506 507 return (0); 508 } 509 510 /* 511 * Allocate and initialize the firmware event queue and the management queue. 512 * 513 * Returns errno on failure. Resources allocated up to that point may still be 514 * allocated. Caller is responsible for cleanup in case this function fails. 515 */ 516 int 517 t4_setup_adapter_queues(struct adapter *sc) 518 { 519 int rc; 520 521 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 522 523 sysctl_ctx_init(&sc->ctx); 524 sc->flags |= ADAP_SYSCTL_CTX; 525 526 /* 527 * Firmware event queue 528 */ 529 rc = alloc_fwq(sc); 530 if (rc != 0) 531 return (rc); 532 533 /* 534 * Management queue. This is just a control queue that uses the fwq as 535 * its associated iq. 536 */ 537 rc = alloc_mgmtq(sc); 538 539 return (rc); 540 } 541 542 /* 543 * Idempotent 544 */ 545 int 546 t4_teardown_adapter_queues(struct adapter *sc) 547 { 548 549 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 550 551 /* Do this before freeing the queue */ 552 if (sc->flags & ADAP_SYSCTL_CTX) { 553 sysctl_ctx_free(&sc->ctx); 554 sc->flags &= ~ADAP_SYSCTL_CTX; 555 } 556 557 free_mgmtq(sc); 558 free_fwq(sc); 559 560 return (0); 561 } 562 563 static inline int 564 first_vector(struct port_info *pi) 565 { 566 struct adapter *sc = pi->adapter; 567 int rc = T4_EXTRA_INTR, i; 568 569 if (sc->intr_count == 1) 570 return (0); 571 572 for_each_port(sc, i) { 573 struct port_info *p = sc->port[i]; 574 575 if (i == pi->port_id) 576 break; 577 578 #ifdef TCP_OFFLOAD 579 if (sc->flags & INTR_DIRECT) 580 rc += p->nrxq + p->nofldrxq; 581 else 582 rc += max(p->nrxq, p->nofldrxq); 583 #else 584 /* 585 * Not compiled with offload support and intr_count > 1. Only 586 * NIC queues exist and they'd better be taking direct 587 * interrupts. 588 */ 589 KASSERT(sc->flags & INTR_DIRECT, 590 ("%s: intr_count %d, !INTR_DIRECT", __func__, 591 sc->intr_count)); 592 593 rc += p->nrxq; 594 #endif 595 } 596 597 return (rc); 598 } 599 600 /* 601 * Given an arbitrary "index," come up with an iq that can be used by other 602 * queues (of this port) for interrupt forwarding, SGE egress updates, etc. 603 * The iq returned is guaranteed to be something that takes direct interrupts. 604 */ 605 static struct sge_iq * 606 port_intr_iq(struct port_info *pi, int idx) 607 { 608 struct adapter *sc = pi->adapter; 609 struct sge *s = &sc->sge; 610 struct sge_iq *iq = NULL; 611 612 if (sc->intr_count == 1) 613 return (&sc->sge.fwq); 614 615 #ifdef TCP_OFFLOAD 616 if (sc->flags & INTR_DIRECT) { 617 idx %= pi->nrxq + pi->nofldrxq; 618 619 if (idx >= pi->nrxq) { 620 idx -= pi->nrxq; 621 iq = &s->ofld_rxq[pi->first_ofld_rxq + idx].iq; 622 } else 623 iq = &s->rxq[pi->first_rxq + idx].iq; 624 625 } else { 626 idx %= max(pi->nrxq, pi->nofldrxq); 627 628 if (pi->nrxq >= pi->nofldrxq) 629 iq = &s->rxq[pi->first_rxq + idx].iq; 630 else 631 iq = &s->ofld_rxq[pi->first_ofld_rxq + idx].iq; 632 } 633 #else 634 /* 635 * Not compiled with offload support and intr_count > 1. Only NIC 636 * queues exist and they'd better be taking direct interrupts. 637 */ 638 KASSERT(sc->flags & INTR_DIRECT, 639 ("%s: intr_count %d, !INTR_DIRECT", __func__, sc->intr_count)); 640 641 idx %= pi->nrxq; 642 iq = &s->rxq[pi->first_rxq + idx].iq; 643 #endif 644 645 KASSERT(iq->flags & IQ_INTR, ("%s: EDOOFUS", __func__)); 646 return (iq); 647 } 648 649 static inline int 650 mtu_to_bufsize(int mtu) 651 { 652 int bufsize; 653 654 /* large enough for a frame even when VLAN extraction is disabled */ 655 bufsize = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + mtu; 656 bufsize = roundup2(bufsize + fl_pktshift, fl_pad); 657 658 return (bufsize); 659 } 660 661 #ifdef TCP_OFFLOAD 662 static inline int 663 mtu_to_bufsize_toe(struct adapter *sc, int mtu) 664 { 665 666 if (sc->tt.rx_coalesce) 667 return (G_RXCOALESCESIZE(t4_read_reg(sc, A_TP_PARA_REG2))); 668 669 return (mtu); 670 } 671 #endif 672 673 int 674 t4_setup_port_queues(struct port_info *pi) 675 { 676 int rc = 0, i, j, intr_idx, iqid; 677 struct sge_rxq *rxq; 678 struct sge_txq *txq; 679 struct sge_wrq *ctrlq; 680 #ifdef TCP_OFFLOAD 681 struct sge_ofld_rxq *ofld_rxq; 682 struct sge_wrq *ofld_txq; 683 struct sysctl_oid *oid2 = NULL; 684 #endif 685 char name[16]; 686 struct adapter *sc = pi->adapter; 687 struct ifnet *ifp = pi->ifp; 688 struct sysctl_oid *oid = device_get_sysctl_tree(pi->dev); 689 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 690 int bufsize; 691 692 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "rxq", CTLFLAG_RD, 693 NULL, "rx queues"); 694 695 #ifdef TCP_OFFLOAD 696 if (is_offload(sc)) { 697 oid2 = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "ofld_rxq", 698 CTLFLAG_RD, NULL, 699 "rx queues for offloaded TCP connections"); 700 } 701 #endif 702 703 /* Interrupt vector to start from (when using multiple vectors) */ 704 intr_idx = first_vector(pi); 705 706 /* 707 * First pass over all rx queues (NIC and TOE): 708 * a) initialize iq and fl 709 * b) allocate queue iff it will take direct interrupts. 710 */ 711 bufsize = mtu_to_bufsize(ifp->if_mtu); 712 for_each_rxq(pi, i, rxq) { 713 714 init_iq(&rxq->iq, sc, pi->tmr_idx, pi->pktc_idx, pi->qsize_rxq, 715 RX_IQ_ESIZE); 716 717 snprintf(name, sizeof(name), "%s rxq%d-fl", 718 device_get_nameunit(pi->dev), i); 719 init_fl(&rxq->fl, pi->qsize_rxq / 8, bufsize, name); 720 721 if (sc->flags & INTR_DIRECT 722 #ifdef TCP_OFFLOAD 723 || (sc->intr_count > 1 && pi->nrxq >= pi->nofldrxq) 724 #endif 725 ) { 726 rxq->iq.flags |= IQ_INTR; 727 rc = alloc_rxq(pi, rxq, intr_idx, i, oid); 728 if (rc != 0) 729 goto done; 730 intr_idx++; 731 } 732 } 733 734 #ifdef TCP_OFFLOAD 735 bufsize = mtu_to_bufsize_toe(sc, ifp->if_mtu); 736 for_each_ofld_rxq(pi, i, ofld_rxq) { 737 738 init_iq(&ofld_rxq->iq, sc, pi->tmr_idx, pi->pktc_idx, 739 pi->qsize_rxq, RX_IQ_ESIZE); 740 741 snprintf(name, sizeof(name), "%s ofld_rxq%d-fl", 742 device_get_nameunit(pi->dev), i); 743 init_fl(&ofld_rxq->fl, pi->qsize_rxq / 8, bufsize, name); 744 745 if (sc->flags & INTR_DIRECT || 746 (sc->intr_count > 1 && pi->nofldrxq > pi->nrxq)) { 747 ofld_rxq->iq.flags |= IQ_INTR; 748 rc = alloc_ofld_rxq(pi, ofld_rxq, intr_idx, i, oid2); 749 if (rc != 0) 750 goto done; 751 intr_idx++; 752 } 753 } 754 #endif 755 756 /* 757 * Second pass over all rx queues (NIC and TOE). The queues forwarding 758 * their interrupts are allocated now. 759 */ 760 j = 0; 761 for_each_rxq(pi, i, rxq) { 762 if (rxq->iq.flags & IQ_INTR) 763 continue; 764 765 intr_idx = port_intr_iq(pi, j)->abs_id; 766 767 rc = alloc_rxq(pi, rxq, intr_idx, i, oid); 768 if (rc != 0) 769 goto done; 770 j++; 771 } 772 773 #ifdef TCP_OFFLOAD 774 for_each_ofld_rxq(pi, i, ofld_rxq) { 775 if (ofld_rxq->iq.flags & IQ_INTR) 776 continue; 777 778 intr_idx = port_intr_iq(pi, j)->abs_id; 779 780 rc = alloc_ofld_rxq(pi, ofld_rxq, intr_idx, i, oid2); 781 if (rc != 0) 782 goto done; 783 j++; 784 } 785 #endif 786 787 /* 788 * Now the tx queues. Only one pass needed. 789 */ 790 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "txq", CTLFLAG_RD, 791 NULL, "tx queues"); 792 j = 0; 793 for_each_txq(pi, i, txq) { 794 uint16_t iqid; 795 796 iqid = port_intr_iq(pi, j)->cntxt_id; 797 798 snprintf(name, sizeof(name), "%s txq%d", 799 device_get_nameunit(pi->dev), i); 800 init_eq(&txq->eq, EQ_ETH, pi->qsize_txq, pi->tx_chan, iqid, 801 name); 802 803 rc = alloc_txq(pi, txq, i, oid); 804 if (rc != 0) 805 goto done; 806 j++; 807 } 808 809 #ifdef TCP_OFFLOAD 810 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "ofld_txq", 811 CTLFLAG_RD, NULL, "tx queues for offloaded TCP connections"); 812 for_each_ofld_txq(pi, i, ofld_txq) { 813 uint16_t iqid; 814 815 iqid = port_intr_iq(pi, j)->cntxt_id; 816 817 snprintf(name, sizeof(name), "%s ofld_txq%d", 818 device_get_nameunit(pi->dev), i); 819 init_eq(&ofld_txq->eq, EQ_OFLD, pi->qsize_txq, pi->tx_chan, 820 iqid, name); 821 822 snprintf(name, sizeof(name), "%d", i); 823 oid2 = SYSCTL_ADD_NODE(&pi->ctx, SYSCTL_CHILDREN(oid), OID_AUTO, 824 name, CTLFLAG_RD, NULL, "offload tx queue"); 825 826 rc = alloc_wrq(sc, pi, ofld_txq, oid2); 827 if (rc != 0) 828 goto done; 829 j++; 830 } 831 #endif 832 833 /* 834 * Finally, the control queue. 835 */ 836 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "ctrlq", CTLFLAG_RD, 837 NULL, "ctrl queue"); 838 ctrlq = &sc->sge.ctrlq[pi->port_id]; 839 iqid = port_intr_iq(pi, 0)->cntxt_id; 840 snprintf(name, sizeof(name), "%s ctrlq", device_get_nameunit(pi->dev)); 841 init_eq(&ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE, pi->tx_chan, iqid, name); 842 rc = alloc_wrq(sc, pi, ctrlq, oid); 843 844 done: 845 if (rc) 846 t4_teardown_port_queues(pi); 847 848 return (rc); 849 } 850 851 /* 852 * Idempotent 853 */ 854 int 855 t4_teardown_port_queues(struct port_info *pi) 856 { 857 int i; 858 struct adapter *sc = pi->adapter; 859 struct sge_rxq *rxq; 860 struct sge_txq *txq; 861 #ifdef TCP_OFFLOAD 862 struct sge_ofld_rxq *ofld_rxq; 863 struct sge_wrq *ofld_txq; 864 #endif 865 866 /* Do this before freeing the queues */ 867 if (pi->flags & PORT_SYSCTL_CTX) { 868 sysctl_ctx_free(&pi->ctx); 869 pi->flags &= ~PORT_SYSCTL_CTX; 870 } 871 872 /* 873 * Take down all the tx queues first, as they reference the rx queues 874 * (for egress updates, etc.). 875 */ 876 877 free_wrq(sc, &sc->sge.ctrlq[pi->port_id]); 878 879 for_each_txq(pi, i, txq) { 880 free_txq(pi, txq); 881 } 882 883 #ifdef TCP_OFFLOAD 884 for_each_ofld_txq(pi, i, ofld_txq) { 885 free_wrq(sc, ofld_txq); 886 } 887 #endif 888 889 /* 890 * Then take down the rx queues that forward their interrupts, as they 891 * reference other rx queues. 892 */ 893 894 for_each_rxq(pi, i, rxq) { 895 if ((rxq->iq.flags & IQ_INTR) == 0) 896 free_rxq(pi, rxq); 897 } 898 899 #ifdef TCP_OFFLOAD 900 for_each_ofld_rxq(pi, i, ofld_rxq) { 901 if ((ofld_rxq->iq.flags & IQ_INTR) == 0) 902 free_ofld_rxq(pi, ofld_rxq); 903 } 904 #endif 905 906 /* 907 * Then take down the rx queues that take direct interrupts. 908 */ 909 910 for_each_rxq(pi, i, rxq) { 911 if (rxq->iq.flags & IQ_INTR) 912 free_rxq(pi, rxq); 913 } 914 915 #ifdef TCP_OFFLOAD 916 for_each_ofld_rxq(pi, i, ofld_rxq) { 917 if (ofld_rxq->iq.flags & IQ_INTR) 918 free_ofld_rxq(pi, ofld_rxq); 919 } 920 #endif 921 922 return (0); 923 } 924 925 /* 926 * Deals with errors and the firmware event queue. All data rx queues forward 927 * their interrupt to the firmware event queue. 928 */ 929 void 930 t4_intr_all(void *arg) 931 { 932 struct adapter *sc = arg; 933 struct sge_iq *fwq = &sc->sge.fwq; 934 935 t4_intr_err(arg); 936 if (atomic_cmpset_int(&fwq->state, IQS_IDLE, IQS_BUSY)) { 937 service_iq(fwq, 0); 938 atomic_cmpset_int(&fwq->state, IQS_BUSY, IQS_IDLE); 939 } 940 } 941 942 /* Deals with error interrupts */ 943 void 944 t4_intr_err(void *arg) 945 { 946 struct adapter *sc = arg; 947 948 t4_write_reg(sc, MYPF_REG(A_PCIE_PF_CLI), 0); 949 t4_slow_intr_handler(sc); 950 } 951 952 void 953 t4_intr_evt(void *arg) 954 { 955 struct sge_iq *iq = arg; 956 957 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 958 service_iq(iq, 0); 959 atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 960 } 961 } 962 963 void 964 t4_intr(void *arg) 965 { 966 struct sge_iq *iq = arg; 967 968 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 969 service_iq(iq, 0); 970 atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 971 } 972 } 973 974 /* 975 * Deals with anything and everything on the given ingress queue. 976 */ 977 static int 978 service_iq(struct sge_iq *iq, int budget) 979 { 980 struct sge_iq *q; 981 struct sge_rxq *rxq = iq_to_rxq(iq); /* Use iff iq is part of rxq */ 982 struct sge_fl *fl = &rxq->fl; /* Use iff IQ_HAS_FL */ 983 struct adapter *sc = iq->adapter; 984 struct rsp_ctrl *ctrl; 985 const struct rss_header *rss; 986 int ndescs = 0, limit, fl_bufs_used = 0; 987 int rsp_type; 988 uint32_t lq; 989 struct mbuf *m0; 990 STAILQ_HEAD(, sge_iq) iql = STAILQ_HEAD_INITIALIZER(iql); 991 992 limit = budget ? budget : iq->qsize / 8; 993 994 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq)); 995 996 /* 997 * We always come back and check the descriptor ring for new indirect 998 * interrupts and other responses after running a single handler. 999 */ 1000 for (;;) { 1001 while (is_new_response(iq, &ctrl)) { 1002 1003 rmb(); 1004 1005 m0 = NULL; 1006 rsp_type = G_RSPD_TYPE(ctrl->u.type_gen); 1007 lq = be32toh(ctrl->pldbuflen_qid); 1008 rss = (const void *)iq->cdesc; 1009 1010 switch (rsp_type) { 1011 case X_RSPD_TYPE_FLBUF: 1012 1013 KASSERT(iq->flags & IQ_HAS_FL, 1014 ("%s: data for an iq (%p) with no freelist", 1015 __func__, iq)); 1016 1017 m0 = get_fl_payload(sc, fl, lq, &fl_bufs_used); 1018 #ifdef T4_PKT_TIMESTAMP 1019 /* 1020 * 60 bit timestamp for the payload is 1021 * *(uint64_t *)m0->m_pktdat. Note that it is 1022 * in the leading free-space in the mbuf. The 1023 * kernel can clobber it during a pullup, 1024 * m_copymdata, etc. You need to make sure that 1025 * the mbuf reaches you unmolested if you care 1026 * about the timestamp. 1027 */ 1028 *(uint64_t *)m0->m_pktdat = 1029 be64toh(ctrl->u.last_flit) & 1030 0xfffffffffffffff; 1031 #endif 1032 1033 /* fall through */ 1034 1035 case X_RSPD_TYPE_CPL: 1036 KASSERT(rss->opcode < NUM_CPL_CMDS, 1037 ("%s: bad opcode %02x.", __func__, 1038 rss->opcode)); 1039 sc->cpl_handler[rss->opcode](iq, rss, m0); 1040 break; 1041 1042 case X_RSPD_TYPE_INTR: 1043 1044 /* 1045 * Interrupts should be forwarded only to queues 1046 * that are not forwarding their interrupts. 1047 * This means service_iq can recurse but only 1 1048 * level deep. 1049 */ 1050 KASSERT(budget == 0, 1051 ("%s: budget %u, rsp_type %u", __func__, 1052 budget, rsp_type)); 1053 1054 q = sc->sge.iqmap[lq - sc->sge.iq_start]; 1055 if (atomic_cmpset_int(&q->state, IQS_IDLE, 1056 IQS_BUSY)) { 1057 if (service_iq(q, q->qsize / 8) == 0) { 1058 atomic_cmpset_int(&q->state, 1059 IQS_BUSY, IQS_IDLE); 1060 } else { 1061 STAILQ_INSERT_TAIL(&iql, q, 1062 link); 1063 } 1064 } 1065 break; 1066 1067 default: 1068 sc->an_handler(iq, ctrl); 1069 break; 1070 } 1071 1072 iq_next(iq); 1073 if (++ndescs == limit) { 1074 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), 1075 V_CIDXINC(ndescs) | 1076 V_INGRESSQID(iq->cntxt_id) | 1077 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); 1078 ndescs = 0; 1079 1080 if (fl_bufs_used > 0) { 1081 FL_LOCK(fl); 1082 fl->needed += fl_bufs_used; 1083 refill_fl(sc, fl, fl->cap / 8); 1084 FL_UNLOCK(fl); 1085 fl_bufs_used = 0; 1086 } 1087 1088 if (budget) 1089 return (EINPROGRESS); 1090 } 1091 } 1092 1093 if (STAILQ_EMPTY(&iql)) 1094 break; 1095 1096 /* 1097 * Process the head only, and send it to the back of the list if 1098 * it's still not done. 1099 */ 1100 q = STAILQ_FIRST(&iql); 1101 STAILQ_REMOVE_HEAD(&iql, link); 1102 if (service_iq(q, q->qsize / 8) == 0) 1103 atomic_cmpset_int(&q->state, IQS_BUSY, IQS_IDLE); 1104 else 1105 STAILQ_INSERT_TAIL(&iql, q, link); 1106 } 1107 1108 #if defined(INET) || defined(INET6) 1109 if (iq->flags & IQ_LRO_ENABLED) { 1110 struct lro_ctrl *lro = &rxq->lro; 1111 struct lro_entry *l; 1112 1113 while (!SLIST_EMPTY(&lro->lro_active)) { 1114 l = SLIST_FIRST(&lro->lro_active); 1115 SLIST_REMOVE_HEAD(&lro->lro_active, next); 1116 tcp_lro_flush(lro, l); 1117 } 1118 } 1119 #endif 1120 1121 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), V_CIDXINC(ndescs) | 1122 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params)); 1123 1124 if (iq->flags & IQ_HAS_FL) { 1125 int starved; 1126 1127 FL_LOCK(fl); 1128 fl->needed += fl_bufs_used; 1129 starved = refill_fl(sc, fl, fl->cap / 4); 1130 FL_UNLOCK(fl); 1131 if (__predict_false(starved != 0)) 1132 add_fl_to_sfl(sc, fl); 1133 } 1134 1135 return (0); 1136 } 1137 1138 static struct mbuf * 1139 get_fl_payload(struct adapter *sc, struct sge_fl *fl, uint32_t len_newbuf, 1140 int *fl_bufs_used) 1141 { 1142 struct mbuf *m0, *m; 1143 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 1144 unsigned int nbuf, len; 1145 1146 /* 1147 * No assertion for the fl lock because we don't need it. This routine 1148 * is called only from the rx interrupt handler and it only updates 1149 * fl->cidx. (Contrast that with fl->pidx/fl->needed which could be 1150 * updated in the rx interrupt handler or the starvation helper routine. 1151 * That's why code that manipulates fl->pidx/fl->needed needs the fl 1152 * lock but this routine does not). 1153 */ 1154 1155 if (__predict_false((len_newbuf & F_RSPD_NEWBUF) == 0)) 1156 panic("%s: cannot handle packed frames", __func__); 1157 len = G_RSPD_LEN(len_newbuf); 1158 1159 m0 = sd->m; 1160 sd->m = NULL; /* consumed */ 1161 1162 bus_dmamap_sync(fl->tag[sd->tag_idx], sd->map, BUS_DMASYNC_POSTREAD); 1163 m_init(m0, NULL, 0, M_NOWAIT, MT_DATA, M_PKTHDR); 1164 #ifdef T4_PKT_TIMESTAMP 1165 /* Leave room for a timestamp */ 1166 m0->m_data += 8; 1167 #endif 1168 1169 if (len < RX_COPY_THRESHOLD) { 1170 /* copy data to mbuf, buffer will be recycled */ 1171 bcopy(sd->cl, mtod(m0, caddr_t), len); 1172 m0->m_len = len; 1173 } else { 1174 bus_dmamap_unload(fl->tag[sd->tag_idx], sd->map); 1175 m_cljset(m0, sd->cl, FL_BUF_TYPE(sd->tag_idx)); 1176 sd->cl = NULL; /* consumed */ 1177 m0->m_len = min(len, FL_BUF_SIZE(sd->tag_idx)); 1178 } 1179 m0->m_pkthdr.len = len; 1180 1181 sd++; 1182 if (__predict_false(++fl->cidx == fl->cap)) { 1183 sd = fl->sdesc; 1184 fl->cidx = 0; 1185 } 1186 1187 m = m0; 1188 len -= m->m_len; 1189 nbuf = 1; /* # of fl buffers used */ 1190 1191 while (len > 0) { 1192 m->m_next = sd->m; 1193 sd->m = NULL; /* consumed */ 1194 m = m->m_next; 1195 1196 bus_dmamap_sync(fl->tag[sd->tag_idx], sd->map, 1197 BUS_DMASYNC_POSTREAD); 1198 1199 m_init(m, NULL, 0, M_NOWAIT, MT_DATA, 0); 1200 if (len <= MLEN) { 1201 bcopy(sd->cl, mtod(m, caddr_t), len); 1202 m->m_len = len; 1203 } else { 1204 bus_dmamap_unload(fl->tag[sd->tag_idx], 1205 sd->map); 1206 m_cljset(m, sd->cl, FL_BUF_TYPE(sd->tag_idx)); 1207 sd->cl = NULL; /* consumed */ 1208 m->m_len = min(len, FL_BUF_SIZE(sd->tag_idx)); 1209 } 1210 1211 sd++; 1212 if (__predict_false(++fl->cidx == fl->cap)) { 1213 sd = fl->sdesc; 1214 fl->cidx = 0; 1215 } 1216 1217 len -= m->m_len; 1218 nbuf++; 1219 } 1220 1221 (*fl_bufs_used) += nbuf; 1222 1223 return (m0); 1224 } 1225 1226 static int 1227 t4_eth_rx(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0) 1228 { 1229 struct sge_rxq *rxq = iq_to_rxq(iq); 1230 struct ifnet *ifp = rxq->ifp; 1231 const struct cpl_rx_pkt *cpl = (const void *)(rss + 1); 1232 #if defined(INET) || defined(INET6) 1233 struct lro_ctrl *lro = &rxq->lro; 1234 #endif 1235 1236 KASSERT(m0 != NULL, ("%s: no payload with opcode %02x", __func__, 1237 rss->opcode)); 1238 1239 m0->m_pkthdr.len -= fl_pktshift; 1240 m0->m_len -= fl_pktshift; 1241 m0->m_data += fl_pktshift; 1242 1243 m0->m_pkthdr.rcvif = ifp; 1244 m0->m_flags |= M_FLOWID; 1245 m0->m_pkthdr.flowid = rss->hash_val; 1246 1247 if (cpl->csum_calc && !cpl->err_vec) { 1248 if (ifp->if_capenable & IFCAP_RXCSUM && 1249 cpl->l2info & htobe32(F_RXF_IP)) { 1250 m0->m_pkthdr.csum_flags = (CSUM_IP_CHECKED | 1251 CSUM_IP_VALID | CSUM_DATA_VALID | CSUM_PSEUDO_HDR); 1252 rxq->rxcsum++; 1253 } else if (ifp->if_capenable & IFCAP_RXCSUM_IPV6 && 1254 cpl->l2info & htobe32(F_RXF_IP6)) { 1255 m0->m_pkthdr.csum_flags = (CSUM_DATA_VALID_IPV6 | 1256 CSUM_PSEUDO_HDR); 1257 rxq->rxcsum++; 1258 } 1259 1260 if (__predict_false(cpl->ip_frag)) 1261 m0->m_pkthdr.csum_data = be16toh(cpl->csum); 1262 else 1263 m0->m_pkthdr.csum_data = 0xffff; 1264 } 1265 1266 if (cpl->vlan_ex) { 1267 m0->m_pkthdr.ether_vtag = be16toh(cpl->vlan); 1268 m0->m_flags |= M_VLANTAG; 1269 rxq->vlan_extraction++; 1270 } 1271 1272 #if defined(INET) || defined(INET6) 1273 if (cpl->l2info & htobe32(F_RXF_LRO) && 1274 iq->flags & IQ_LRO_ENABLED && 1275 tcp_lro_rx(lro, m0, 0) == 0) { 1276 /* queued for LRO */ 1277 } else 1278 #endif 1279 ifp->if_input(ifp, m0); 1280 1281 return (0); 1282 } 1283 1284 /* 1285 * Doesn't fail. Holds on to work requests it can't send right away. 1286 */ 1287 void 1288 t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, struct wrqe *wr) 1289 { 1290 struct sge_eq *eq = &wrq->eq; 1291 int can_reclaim; 1292 caddr_t dst; 1293 1294 TXQ_LOCK_ASSERT_OWNED(wrq); 1295 #ifdef TCP_OFFLOAD 1296 KASSERT((eq->flags & EQ_TYPEMASK) == EQ_OFLD || 1297 (eq->flags & EQ_TYPEMASK) == EQ_CTRL, 1298 ("%s: eq type %d", __func__, eq->flags & EQ_TYPEMASK)); 1299 #else 1300 KASSERT((eq->flags & EQ_TYPEMASK) == EQ_CTRL, 1301 ("%s: eq type %d", __func__, eq->flags & EQ_TYPEMASK)); 1302 #endif 1303 1304 if (__predict_true(wr != NULL)) 1305 STAILQ_INSERT_TAIL(&wrq->wr_list, wr, link); 1306 1307 can_reclaim = reclaimable(eq); 1308 if (__predict_false(eq->flags & EQ_STALLED)) { 1309 if (can_reclaim < tx_resume_threshold(eq)) 1310 return; 1311 eq->flags &= ~EQ_STALLED; 1312 eq->unstalled++; 1313 } 1314 eq->cidx += can_reclaim; 1315 eq->avail += can_reclaim; 1316 if (__predict_false(eq->cidx >= eq->cap)) 1317 eq->cidx -= eq->cap; 1318 1319 while ((wr = STAILQ_FIRST(&wrq->wr_list)) != NULL) { 1320 int ndesc; 1321 1322 if (__predict_false(wr->wr_len < 0 || 1323 wr->wr_len > SGE_MAX_WR_LEN || (wr->wr_len & 0x7))) { 1324 1325 #ifdef INVARIANTS 1326 panic("%s: work request with length %d", __func__, 1327 wr->wr_len); 1328 #endif 1329 #ifdef KDB 1330 kdb_backtrace(); 1331 #endif 1332 log(LOG_ERR, "%s: %s work request with length %d", 1333 device_get_nameunit(sc->dev), __func__, wr->wr_len); 1334 STAILQ_REMOVE_HEAD(&wrq->wr_list, link); 1335 free_wrqe(wr); 1336 continue; 1337 } 1338 1339 ndesc = howmany(wr->wr_len, EQ_ESIZE); 1340 if (eq->avail < ndesc) { 1341 wrq->no_desc++; 1342 break; 1343 } 1344 1345 dst = (void *)&eq->desc[eq->pidx]; 1346 copy_to_txd(eq, wrtod(wr), &dst, wr->wr_len); 1347 1348 eq->pidx += ndesc; 1349 eq->avail -= ndesc; 1350 if (__predict_false(eq->pidx >= eq->cap)) 1351 eq->pidx -= eq->cap; 1352 1353 eq->pending += ndesc; 1354 if (eq->pending >= 8) 1355 ring_eq_db(sc, eq); 1356 1357 wrq->tx_wrs++; 1358 STAILQ_REMOVE_HEAD(&wrq->wr_list, link); 1359 free_wrqe(wr); 1360 1361 if (eq->avail < 8) { 1362 can_reclaim = reclaimable(eq); 1363 eq->cidx += can_reclaim; 1364 eq->avail += can_reclaim; 1365 if (__predict_false(eq->cidx >= eq->cap)) 1366 eq->cidx -= eq->cap; 1367 } 1368 } 1369 1370 if (eq->pending) 1371 ring_eq_db(sc, eq); 1372 1373 if (wr != NULL) { 1374 eq->flags |= EQ_STALLED; 1375 if (callout_pending(&eq->tx_callout) == 0) 1376 callout_reset(&eq->tx_callout, 1, t4_tx_callout, eq); 1377 } 1378 } 1379 1380 /* Per-packet header in a coalesced tx WR, before the SGL starts (in flits) */ 1381 #define TXPKTS_PKT_HDR ((\ 1382 sizeof(struct ulp_txpkt) + \ 1383 sizeof(struct ulptx_idata) + \ 1384 sizeof(struct cpl_tx_pkt_core) \ 1385 ) / 8) 1386 1387 /* Header of a coalesced tx WR, before SGL of first packet (in flits) */ 1388 #define TXPKTS_WR_HDR (\ 1389 sizeof(struct fw_eth_tx_pkts_wr) / 8 + \ 1390 TXPKTS_PKT_HDR) 1391 1392 /* Header of a tx WR, before SGL of first packet (in flits) */ 1393 #define TXPKT_WR_HDR ((\ 1394 sizeof(struct fw_eth_tx_pkt_wr) + \ 1395 sizeof(struct cpl_tx_pkt_core) \ 1396 ) / 8 ) 1397 1398 /* Header of a tx LSO WR, before SGL of first packet (in flits) */ 1399 #define TXPKT_LSO_WR_HDR ((\ 1400 sizeof(struct fw_eth_tx_pkt_wr) + \ 1401 sizeof(struct cpl_tx_pkt_lso_core) + \ 1402 sizeof(struct cpl_tx_pkt_core) \ 1403 ) / 8 ) 1404 1405 int 1406 t4_eth_tx(struct ifnet *ifp, struct sge_txq *txq, struct mbuf *m) 1407 { 1408 struct port_info *pi = (void *)ifp->if_softc; 1409 struct adapter *sc = pi->adapter; 1410 struct sge_eq *eq = &txq->eq; 1411 struct buf_ring *br = txq->br; 1412 struct mbuf *next; 1413 int rc, coalescing, can_reclaim; 1414 struct txpkts txpkts; 1415 struct sgl sgl; 1416 1417 TXQ_LOCK_ASSERT_OWNED(txq); 1418 KASSERT(m, ("%s: called with nothing to do.", __func__)); 1419 KASSERT((eq->flags & EQ_TYPEMASK) == EQ_ETH, 1420 ("%s: eq type %d", __func__, eq->flags & EQ_TYPEMASK)); 1421 1422 prefetch(&eq->desc[eq->pidx]); 1423 prefetch(&txq->sdesc[eq->pidx]); 1424 1425 txpkts.npkt = 0;/* indicates there's nothing in txpkts */ 1426 coalescing = 0; 1427 1428 can_reclaim = reclaimable(eq); 1429 if (__predict_false(eq->flags & EQ_STALLED)) { 1430 if (can_reclaim < tx_resume_threshold(eq)) { 1431 txq->m = m; 1432 return (0); 1433 } 1434 eq->flags &= ~EQ_STALLED; 1435 eq->unstalled++; 1436 } 1437 1438 if (__predict_false(eq->flags & EQ_DOOMED)) { 1439 m_freem(m); 1440 while ((m = buf_ring_dequeue_sc(txq->br)) != NULL) 1441 m_freem(m); 1442 return (ENETDOWN); 1443 } 1444 1445 if (eq->avail < 8 && can_reclaim) 1446 reclaim_tx_descs(txq, can_reclaim, 32); 1447 1448 for (; m; m = next ? next : drbr_dequeue(ifp, br)) { 1449 1450 if (eq->avail < 8) 1451 break; 1452 1453 next = m->m_nextpkt; 1454 m->m_nextpkt = NULL; 1455 1456 if (next || buf_ring_peek(br)) 1457 coalescing = 1; 1458 1459 rc = get_pkt_sgl(txq, &m, &sgl, coalescing); 1460 if (rc != 0) { 1461 if (rc == ENOMEM) { 1462 1463 /* Short of resources, suspend tx */ 1464 1465 m->m_nextpkt = next; 1466 break; 1467 } 1468 1469 /* 1470 * Unrecoverable error for this packet, throw it away 1471 * and move on to the next. get_pkt_sgl may already 1472 * have freed m (it will be NULL in that case and the 1473 * m_freem here is still safe). 1474 */ 1475 1476 m_freem(m); 1477 continue; 1478 } 1479 1480 if (coalescing && 1481 add_to_txpkts(pi, txq, &txpkts, m, &sgl) == 0) { 1482 1483 /* Successfully absorbed into txpkts */ 1484 1485 write_ulp_cpl_sgl(pi, txq, &txpkts, m, &sgl); 1486 goto doorbell; 1487 } 1488 1489 /* 1490 * We weren't coalescing to begin with, or current frame could 1491 * not be coalesced (add_to_txpkts flushes txpkts if a frame 1492 * given to it can't be coalesced). Either way there should be 1493 * nothing in txpkts. 1494 */ 1495 KASSERT(txpkts.npkt == 0, 1496 ("%s: txpkts not empty: %d", __func__, txpkts.npkt)); 1497 1498 /* We're sending out individual packets now */ 1499 coalescing = 0; 1500 1501 if (eq->avail < 8) 1502 reclaim_tx_descs(txq, 0, 8); 1503 rc = write_txpkt_wr(pi, txq, m, &sgl); 1504 if (rc != 0) { 1505 1506 /* Short of hardware descriptors, suspend tx */ 1507 1508 /* 1509 * This is an unlikely but expensive failure. We've 1510 * done all the hard work (DMA mappings etc.) and now we 1511 * can't send out the packet. What's worse, we have to 1512 * spend even more time freeing up everything in sgl. 1513 */ 1514 txq->no_desc++; 1515 free_pkt_sgl(txq, &sgl); 1516 1517 m->m_nextpkt = next; 1518 break; 1519 } 1520 1521 ETHER_BPF_MTAP(ifp, m); 1522 if (sgl.nsegs == 0) 1523 m_freem(m); 1524 doorbell: 1525 if (eq->pending >= 8) 1526 ring_eq_db(sc, eq); 1527 1528 can_reclaim = reclaimable(eq); 1529 if (can_reclaim >= 32) 1530 reclaim_tx_descs(txq, can_reclaim, 64); 1531 } 1532 1533 if (txpkts.npkt > 0) 1534 write_txpkts_wr(txq, &txpkts); 1535 1536 /* 1537 * m not NULL means there was an error but we haven't thrown it away. 1538 * This can happen when we're short of tx descriptors (no_desc) or maybe 1539 * even DMA maps (no_dmamap). Either way, a credit flush and reclaim 1540 * will get things going again. 1541 */ 1542 if (m && !(eq->flags & EQ_CRFLUSHED)) { 1543 struct tx_sdesc *txsd = &txq->sdesc[eq->pidx]; 1544 1545 /* 1546 * If EQ_CRFLUSHED is not set then we know we have at least one 1547 * available descriptor because any WR that reduces eq->avail to 1548 * 0 also sets EQ_CRFLUSHED. 1549 */ 1550 KASSERT(eq->avail > 0, ("%s: no space for eqflush.", __func__)); 1551 1552 txsd->desc_used = 1; 1553 txsd->credits = 0; 1554 write_eqflush_wr(eq); 1555 } 1556 txq->m = m; 1557 1558 if (eq->pending) 1559 ring_eq_db(sc, eq); 1560 1561 reclaim_tx_descs(txq, 0, 128); 1562 1563 if (eq->flags & EQ_STALLED && callout_pending(&eq->tx_callout) == 0) 1564 callout_reset(&eq->tx_callout, 1, t4_tx_callout, eq); 1565 1566 return (0); 1567 } 1568 1569 void 1570 t4_update_fl_bufsize(struct ifnet *ifp) 1571 { 1572 struct port_info *pi = ifp->if_softc; 1573 struct sge_rxq *rxq; 1574 #ifdef TCP_OFFLOAD 1575 struct sge_ofld_rxq *ofld_rxq; 1576 #endif 1577 struct sge_fl *fl; 1578 int i, bufsize; 1579 1580 bufsize = mtu_to_bufsize(ifp->if_mtu); 1581 for_each_rxq(pi, i, rxq) { 1582 fl = &rxq->fl; 1583 1584 FL_LOCK(fl); 1585 set_fl_tag_idx(fl, bufsize); 1586 FL_UNLOCK(fl); 1587 } 1588 #ifdef TCP_OFFLOAD 1589 bufsize = mtu_to_bufsize_toe(pi->adapter, ifp->if_mtu); 1590 for_each_ofld_rxq(pi, i, ofld_rxq) { 1591 fl = &ofld_rxq->fl; 1592 1593 FL_LOCK(fl); 1594 set_fl_tag_idx(fl, bufsize); 1595 FL_UNLOCK(fl); 1596 } 1597 #endif 1598 } 1599 1600 int 1601 can_resume_tx(struct sge_eq *eq) 1602 { 1603 return (reclaimable(eq) >= tx_resume_threshold(eq)); 1604 } 1605 1606 static inline void 1607 init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int pktc_idx, 1608 int qsize, int esize) 1609 { 1610 KASSERT(tmr_idx >= 0 && tmr_idx < SGE_NTIMERS, 1611 ("%s: bad tmr_idx %d", __func__, tmr_idx)); 1612 KASSERT(pktc_idx < SGE_NCOUNTERS, /* -ve is ok, means don't use */ 1613 ("%s: bad pktc_idx %d", __func__, pktc_idx)); 1614 1615 iq->flags = 0; 1616 iq->adapter = sc; 1617 iq->intr_params = V_QINTR_TIMER_IDX(tmr_idx); 1618 iq->intr_pktc_idx = SGE_NCOUNTERS - 1; 1619 if (pktc_idx >= 0) { 1620 iq->intr_params |= F_QINTR_CNT_EN; 1621 iq->intr_pktc_idx = pktc_idx; 1622 } 1623 iq->qsize = roundup2(qsize, 16); /* See FW_IQ_CMD/iqsize */ 1624 iq->esize = max(esize, 16); /* See FW_IQ_CMD/iqesize */ 1625 } 1626 1627 static inline void 1628 init_fl(struct sge_fl *fl, int qsize, int bufsize, char *name) 1629 { 1630 fl->qsize = qsize; 1631 strlcpy(fl->lockname, name, sizeof(fl->lockname)); 1632 set_fl_tag_idx(fl, bufsize); 1633 } 1634 1635 static inline void 1636 init_eq(struct sge_eq *eq, int eqtype, int qsize, uint8_t tx_chan, 1637 uint16_t iqid, char *name) 1638 { 1639 KASSERT(tx_chan < NCHAN, ("%s: bad tx channel %d", __func__, tx_chan)); 1640 KASSERT(eqtype <= EQ_TYPEMASK, ("%s: bad qtype %d", __func__, eqtype)); 1641 1642 eq->flags = eqtype & EQ_TYPEMASK; 1643 eq->tx_chan = tx_chan; 1644 eq->iqid = iqid; 1645 eq->qsize = qsize; 1646 strlcpy(eq->lockname, name, sizeof(eq->lockname)); 1647 1648 TASK_INIT(&eq->tx_task, 0, t4_tx_task, eq); 1649 callout_init(&eq->tx_callout, CALLOUT_MPSAFE); 1650 } 1651 1652 static int 1653 alloc_ring(struct adapter *sc, size_t len, bus_dma_tag_t *tag, 1654 bus_dmamap_t *map, bus_addr_t *pa, void **va) 1655 { 1656 int rc; 1657 1658 rc = bus_dma_tag_create(sc->dmat, 512, 0, BUS_SPACE_MAXADDR, 1659 BUS_SPACE_MAXADDR, NULL, NULL, len, 1, len, 0, NULL, NULL, tag); 1660 if (rc != 0) { 1661 device_printf(sc->dev, "cannot allocate DMA tag: %d\n", rc); 1662 goto done; 1663 } 1664 1665 rc = bus_dmamem_alloc(*tag, va, 1666 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, map); 1667 if (rc != 0) { 1668 device_printf(sc->dev, "cannot allocate DMA memory: %d\n", rc); 1669 goto done; 1670 } 1671 1672 rc = bus_dmamap_load(*tag, *map, *va, len, oneseg_dma_callback, pa, 0); 1673 if (rc != 0) { 1674 device_printf(sc->dev, "cannot load DMA map: %d\n", rc); 1675 goto done; 1676 } 1677 done: 1678 if (rc) 1679 free_ring(sc, *tag, *map, *pa, *va); 1680 1681 return (rc); 1682 } 1683 1684 static int 1685 free_ring(struct adapter *sc, bus_dma_tag_t tag, bus_dmamap_t map, 1686 bus_addr_t pa, void *va) 1687 { 1688 if (pa) 1689 bus_dmamap_unload(tag, map); 1690 if (va) 1691 bus_dmamem_free(tag, va, map); 1692 if (tag) 1693 bus_dma_tag_destroy(tag); 1694 1695 return (0); 1696 } 1697 1698 /* 1699 * Allocates the ring for an ingress queue and an optional freelist. If the 1700 * freelist is specified it will be allocated and then associated with the 1701 * ingress queue. 1702 * 1703 * Returns errno on failure. Resources allocated up to that point may still be 1704 * allocated. Caller is responsible for cleanup in case this function fails. 1705 * 1706 * If the ingress queue will take interrupts directly (iq->flags & IQ_INTR) then 1707 * the intr_idx specifies the vector, starting from 0. Otherwise it specifies 1708 * the abs_id of the ingress queue to which its interrupts should be forwarded. 1709 */ 1710 static int 1711 alloc_iq_fl(struct port_info *pi, struct sge_iq *iq, struct sge_fl *fl, 1712 int intr_idx, int cong) 1713 { 1714 int rc, i, cntxt_id; 1715 size_t len; 1716 struct fw_iq_cmd c; 1717 struct adapter *sc = iq->adapter; 1718 __be32 v = 0; 1719 1720 len = iq->qsize * iq->esize; 1721 rc = alloc_ring(sc, len, &iq->desc_tag, &iq->desc_map, &iq->ba, 1722 (void **)&iq->desc); 1723 if (rc != 0) 1724 return (rc); 1725 1726 bzero(&c, sizeof(c)); 1727 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 1728 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) | 1729 V_FW_IQ_CMD_VFN(0)); 1730 1731 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART | 1732 FW_LEN16(c)); 1733 1734 /* Special handling for firmware event queue */ 1735 if (iq == &sc->sge.fwq) 1736 v |= F_FW_IQ_CMD_IQASYNCH; 1737 1738 if (iq->flags & IQ_INTR) { 1739 KASSERT(intr_idx < sc->intr_count, 1740 ("%s: invalid direct intr_idx %d", __func__, intr_idx)); 1741 } else 1742 v |= F_FW_IQ_CMD_IQANDST; 1743 v |= V_FW_IQ_CMD_IQANDSTINDEX(intr_idx); 1744 1745 c.type_to_iqandstindex = htobe32(v | 1746 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) | 1747 V_FW_IQ_CMD_VIID(pi->viid) | 1748 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT)); 1749 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->tx_chan) | 1750 F_FW_IQ_CMD_IQGTSMODE | 1751 V_FW_IQ_CMD_IQINTCNTTHRESH(iq->intr_pktc_idx) | 1752 V_FW_IQ_CMD_IQESIZE(ilog2(iq->esize) - 4)); 1753 c.iqsize = htobe16(iq->qsize); 1754 c.iqaddr = htobe64(iq->ba); 1755 if (cong >= 0) 1756 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN); 1757 1758 if (fl) { 1759 mtx_init(&fl->fl_lock, fl->lockname, NULL, MTX_DEF); 1760 1761 for (i = 0; i < FL_BUF_SIZES; i++) { 1762 1763 /* 1764 * A freelist buffer must be 16 byte aligned as the SGE 1765 * uses the low 4 bits of the bus addr to figure out the 1766 * buffer size. 1767 */ 1768 rc = bus_dma_tag_create(sc->dmat, 16, 0, 1769 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1770 FL_BUF_SIZE(i), 1, FL_BUF_SIZE(i), BUS_DMA_ALLOCNOW, 1771 NULL, NULL, &fl->tag[i]); 1772 if (rc != 0) { 1773 device_printf(sc->dev, 1774 "failed to create fl DMA tag[%d]: %d\n", 1775 i, rc); 1776 return (rc); 1777 } 1778 } 1779 len = fl->qsize * RX_FL_ESIZE; 1780 rc = alloc_ring(sc, len, &fl->desc_tag, &fl->desc_map, 1781 &fl->ba, (void **)&fl->desc); 1782 if (rc) 1783 return (rc); 1784 1785 /* Allocate space for one software descriptor per buffer. */ 1786 fl->cap = (fl->qsize - spg_len / RX_FL_ESIZE) * 8; 1787 FL_LOCK(fl); 1788 rc = alloc_fl_sdesc(fl); 1789 FL_UNLOCK(fl); 1790 if (rc != 0) { 1791 device_printf(sc->dev, 1792 "failed to setup fl software descriptors: %d\n", 1793 rc); 1794 return (rc); 1795 } 1796 fl->needed = fl->cap; 1797 fl->lowat = roundup2(sc->sge.fl_starve_threshold, 8); 1798 1799 c.iqns_to_fl0congen |= 1800 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) | 1801 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO | 1802 F_FW_IQ_CMD_FL0PADEN); 1803 if (cong >= 0) { 1804 c.iqns_to_fl0congen |= 1805 htobe32(V_FW_IQ_CMD_FL0CNGCHMAP(cong) | 1806 F_FW_IQ_CMD_FL0CONGCIF | 1807 F_FW_IQ_CMD_FL0CONGEN); 1808 } 1809 c.fl0dcaen_to_fl0cidxfthresh = 1810 htobe16(V_FW_IQ_CMD_FL0FBMIN(X_FETCHBURSTMIN_64B) | 1811 V_FW_IQ_CMD_FL0FBMAX(X_FETCHBURSTMAX_512B)); 1812 c.fl0size = htobe16(fl->qsize); 1813 c.fl0addr = htobe64(fl->ba); 1814 } 1815 1816 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 1817 if (rc != 0) { 1818 device_printf(sc->dev, 1819 "failed to create ingress queue: %d\n", rc); 1820 return (rc); 1821 } 1822 1823 iq->cdesc = iq->desc; 1824 iq->cidx = 0; 1825 iq->gen = 1; 1826 iq->intr_next = iq->intr_params; 1827 iq->cntxt_id = be16toh(c.iqid); 1828 iq->abs_id = be16toh(c.physiqid); 1829 iq->flags |= IQ_ALLOCATED; 1830 1831 cntxt_id = iq->cntxt_id - sc->sge.iq_start; 1832 if (cntxt_id >= sc->sge.niq) { 1833 panic ("%s: iq->cntxt_id (%d) more than the max (%d)", __func__, 1834 cntxt_id, sc->sge.niq - 1); 1835 } 1836 sc->sge.iqmap[cntxt_id] = iq; 1837 1838 if (fl) { 1839 fl->cntxt_id = be16toh(c.fl0id); 1840 fl->pidx = fl->cidx = 0; 1841 1842 cntxt_id = fl->cntxt_id - sc->sge.eq_start; 1843 if (cntxt_id >= sc->sge.neq) { 1844 panic("%s: fl->cntxt_id (%d) more than the max (%d)", 1845 __func__, cntxt_id, sc->sge.neq - 1); 1846 } 1847 sc->sge.eqmap[cntxt_id] = (void *)fl; 1848 1849 FL_LOCK(fl); 1850 /* Enough to make sure the SGE doesn't think it's starved */ 1851 refill_fl(sc, fl, fl->lowat); 1852 FL_UNLOCK(fl); 1853 1854 iq->flags |= IQ_HAS_FL; 1855 } 1856 1857 /* Enable IQ interrupts */ 1858 atomic_store_rel_int(&iq->state, IQS_IDLE); 1859 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), V_SEINTARM(iq->intr_params) | 1860 V_INGRESSQID(iq->cntxt_id)); 1861 1862 return (0); 1863 } 1864 1865 static int 1866 free_iq_fl(struct port_info *pi, struct sge_iq *iq, struct sge_fl *fl) 1867 { 1868 int i, rc; 1869 struct adapter *sc = iq->adapter; 1870 device_t dev; 1871 1872 if (sc == NULL) 1873 return (0); /* nothing to do */ 1874 1875 dev = pi ? pi->dev : sc->dev; 1876 1877 if (iq->flags & IQ_ALLOCATED) { 1878 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0, 1879 FW_IQ_TYPE_FL_INT_CAP, iq->cntxt_id, 1880 fl ? fl->cntxt_id : 0xffff, 0xffff); 1881 if (rc != 0) { 1882 device_printf(dev, 1883 "failed to free queue %p: %d\n", iq, rc); 1884 return (rc); 1885 } 1886 iq->flags &= ~IQ_ALLOCATED; 1887 } 1888 1889 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, iq->desc); 1890 1891 bzero(iq, sizeof(*iq)); 1892 1893 if (fl) { 1894 free_ring(sc, fl->desc_tag, fl->desc_map, fl->ba, 1895 fl->desc); 1896 1897 if (fl->sdesc) { 1898 FL_LOCK(fl); 1899 free_fl_sdesc(fl); 1900 FL_UNLOCK(fl); 1901 } 1902 1903 if (mtx_initialized(&fl->fl_lock)) 1904 mtx_destroy(&fl->fl_lock); 1905 1906 for (i = 0; i < FL_BUF_SIZES; i++) { 1907 if (fl->tag[i]) 1908 bus_dma_tag_destroy(fl->tag[i]); 1909 } 1910 1911 bzero(fl, sizeof(*fl)); 1912 } 1913 1914 return (0); 1915 } 1916 1917 static int 1918 alloc_fwq(struct adapter *sc) 1919 { 1920 int rc, intr_idx; 1921 struct sge_iq *fwq = &sc->sge.fwq; 1922 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev); 1923 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 1924 1925 init_iq(fwq, sc, 0, 0, FW_IQ_QSIZE, FW_IQ_ESIZE); 1926 fwq->flags |= IQ_INTR; /* always */ 1927 intr_idx = sc->intr_count > 1 ? 1 : 0; 1928 rc = alloc_iq_fl(sc->port[0], fwq, NULL, intr_idx, -1); 1929 if (rc != 0) { 1930 device_printf(sc->dev, 1931 "failed to create firmware event queue: %d\n", rc); 1932 return (rc); 1933 } 1934 1935 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "fwq", CTLFLAG_RD, 1936 NULL, "firmware event queue"); 1937 children = SYSCTL_CHILDREN(oid); 1938 1939 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "abs_id", 1940 CTLTYPE_INT | CTLFLAG_RD, &fwq->abs_id, 0, sysctl_uint16, "I", 1941 "absolute id of the queue"); 1942 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "cntxt_id", 1943 CTLTYPE_INT | CTLFLAG_RD, &fwq->cntxt_id, 0, sysctl_uint16, "I", 1944 "SGE context id of the queue"); 1945 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "cidx", 1946 CTLTYPE_INT | CTLFLAG_RD, &fwq->cidx, 0, sysctl_uint16, "I", 1947 "consumer index"); 1948 1949 return (0); 1950 } 1951 1952 static int 1953 free_fwq(struct adapter *sc) 1954 { 1955 return free_iq_fl(NULL, &sc->sge.fwq, NULL); 1956 } 1957 1958 static int 1959 alloc_mgmtq(struct adapter *sc) 1960 { 1961 int rc; 1962 struct sge_wrq *mgmtq = &sc->sge.mgmtq; 1963 char name[16]; 1964 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev); 1965 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 1966 1967 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "mgmtq", CTLFLAG_RD, 1968 NULL, "management queue"); 1969 1970 snprintf(name, sizeof(name), "%s mgmtq", device_get_nameunit(sc->dev)); 1971 init_eq(&mgmtq->eq, EQ_CTRL, CTRL_EQ_QSIZE, sc->port[0]->tx_chan, 1972 sc->sge.fwq.cntxt_id, name); 1973 rc = alloc_wrq(sc, NULL, mgmtq, oid); 1974 if (rc != 0) { 1975 device_printf(sc->dev, 1976 "failed to create management queue: %d\n", rc); 1977 return (rc); 1978 } 1979 1980 return (0); 1981 } 1982 1983 static int 1984 free_mgmtq(struct adapter *sc) 1985 { 1986 1987 return free_wrq(sc, &sc->sge.mgmtq); 1988 } 1989 1990 static inline int 1991 tnl_cong(struct port_info *pi) 1992 { 1993 1994 if (cong_drop == -1) 1995 return (-1); 1996 else if (cong_drop == 1) 1997 return (0); 1998 else 1999 return (1 << pi->tx_chan); 2000 } 2001 2002 static int 2003 alloc_rxq(struct port_info *pi, struct sge_rxq *rxq, int intr_idx, int idx, 2004 struct sysctl_oid *oid) 2005 { 2006 int rc; 2007 struct sysctl_oid_list *children; 2008 char name[16]; 2009 2010 rc = alloc_iq_fl(pi, &rxq->iq, &rxq->fl, intr_idx, tnl_cong(pi)); 2011 if (rc != 0) 2012 return (rc); 2013 2014 FL_LOCK(&rxq->fl); 2015 refill_fl(pi->adapter, &rxq->fl, rxq->fl.needed / 8); 2016 FL_UNLOCK(&rxq->fl); 2017 2018 #if defined(INET) || defined(INET6) 2019 rc = tcp_lro_init(&rxq->lro); 2020 if (rc != 0) 2021 return (rc); 2022 rxq->lro.ifp = pi->ifp; /* also indicates LRO init'ed */ 2023 2024 if (pi->ifp->if_capenable & IFCAP_LRO) 2025 rxq->iq.flags |= IQ_LRO_ENABLED; 2026 #endif 2027 rxq->ifp = pi->ifp; 2028 2029 children = SYSCTL_CHILDREN(oid); 2030 2031 snprintf(name, sizeof(name), "%d", idx); 2032 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 2033 NULL, "rx queue"); 2034 children = SYSCTL_CHILDREN(oid); 2035 2036 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "abs_id", 2037 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.abs_id, 0, sysctl_uint16, "I", 2038 "absolute id of the queue"); 2039 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cntxt_id", 2040 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.cntxt_id, 0, sysctl_uint16, "I", 2041 "SGE context id of the queue"); 2042 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cidx", 2043 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.cidx, 0, sysctl_uint16, "I", 2044 "consumer index"); 2045 #if defined(INET) || defined(INET6) 2046 SYSCTL_ADD_INT(&pi->ctx, children, OID_AUTO, "lro_queued", CTLFLAG_RD, 2047 &rxq->lro.lro_queued, 0, NULL); 2048 SYSCTL_ADD_INT(&pi->ctx, children, OID_AUTO, "lro_flushed", CTLFLAG_RD, 2049 &rxq->lro.lro_flushed, 0, NULL); 2050 #endif 2051 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "rxcsum", CTLFLAG_RD, 2052 &rxq->rxcsum, "# of times hardware assisted with checksum"); 2053 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "vlan_extraction", 2054 CTLFLAG_RD, &rxq->vlan_extraction, 2055 "# of times hardware extracted 802.1Q tag"); 2056 2057 children = SYSCTL_CHILDREN(oid); 2058 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "fl", CTLFLAG_RD, 2059 NULL, "freelist"); 2060 children = SYSCTL_CHILDREN(oid); 2061 2062 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cntxt_id", 2063 CTLTYPE_INT | CTLFLAG_RD, &rxq->fl.cntxt_id, 0, sysctl_uint16, "I", 2064 "SGE context id of the queue"); 2065 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, 2066 &rxq->fl.cidx, 0, "consumer index"); 2067 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, 2068 &rxq->fl.pidx, 0, "producer index"); 2069 2070 return (rc); 2071 } 2072 2073 static int 2074 free_rxq(struct port_info *pi, struct sge_rxq *rxq) 2075 { 2076 int rc; 2077 2078 #if defined(INET) || defined(INET6) 2079 if (rxq->lro.ifp) { 2080 tcp_lro_free(&rxq->lro); 2081 rxq->lro.ifp = NULL; 2082 } 2083 #endif 2084 2085 rc = free_iq_fl(pi, &rxq->iq, &rxq->fl); 2086 if (rc == 0) 2087 bzero(rxq, sizeof(*rxq)); 2088 2089 return (rc); 2090 } 2091 2092 #ifdef TCP_OFFLOAD 2093 static int 2094 alloc_ofld_rxq(struct port_info *pi, struct sge_ofld_rxq *ofld_rxq, 2095 int intr_idx, int idx, struct sysctl_oid *oid) 2096 { 2097 int rc; 2098 struct sysctl_oid_list *children; 2099 char name[16]; 2100 2101 rc = alloc_iq_fl(pi, &ofld_rxq->iq, &ofld_rxq->fl, intr_idx, 2102 1 << pi->tx_chan); 2103 if (rc != 0) 2104 return (rc); 2105 2106 children = SYSCTL_CHILDREN(oid); 2107 2108 snprintf(name, sizeof(name), "%d", idx); 2109 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 2110 NULL, "rx queue"); 2111 children = SYSCTL_CHILDREN(oid); 2112 2113 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "abs_id", 2114 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.abs_id, 0, sysctl_uint16, 2115 "I", "absolute id of the queue"); 2116 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cntxt_id", 2117 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.cntxt_id, 0, sysctl_uint16, 2118 "I", "SGE context id of the queue"); 2119 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cidx", 2120 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.cidx, 0, sysctl_uint16, "I", 2121 "consumer index"); 2122 2123 children = SYSCTL_CHILDREN(oid); 2124 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "fl", CTLFLAG_RD, 2125 NULL, "freelist"); 2126 children = SYSCTL_CHILDREN(oid); 2127 2128 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cntxt_id", 2129 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->fl.cntxt_id, 0, sysctl_uint16, 2130 "I", "SGE context id of the queue"); 2131 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, 2132 &ofld_rxq->fl.cidx, 0, "consumer index"); 2133 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, 2134 &ofld_rxq->fl.pidx, 0, "producer index"); 2135 2136 return (rc); 2137 } 2138 2139 static int 2140 free_ofld_rxq(struct port_info *pi, struct sge_ofld_rxq *ofld_rxq) 2141 { 2142 int rc; 2143 2144 rc = free_iq_fl(pi, &ofld_rxq->iq, &ofld_rxq->fl); 2145 if (rc == 0) 2146 bzero(ofld_rxq, sizeof(*ofld_rxq)); 2147 2148 return (rc); 2149 } 2150 #endif 2151 2152 static int 2153 ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq) 2154 { 2155 int rc, cntxt_id; 2156 struct fw_eq_ctrl_cmd c; 2157 2158 bzero(&c, sizeof(c)); 2159 2160 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | F_FW_CMD_REQUEST | 2161 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_CTRL_CMD_PFN(sc->pf) | 2162 V_FW_EQ_CTRL_CMD_VFN(0)); 2163 c.alloc_to_len16 = htobe32(F_FW_EQ_CTRL_CMD_ALLOC | 2164 F_FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c)); 2165 c.cmpliqid_eqid = htonl(V_FW_EQ_CTRL_CMD_CMPLIQID(eq->iqid)); /* XXX */ 2166 c.physeqid_pkd = htobe32(0); 2167 c.fetchszm_to_iqid = 2168 htobe32(V_FW_EQ_CTRL_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 2169 V_FW_EQ_CTRL_CMD_PCIECHN(eq->tx_chan) | 2170 F_FW_EQ_CTRL_CMD_FETCHRO | V_FW_EQ_CTRL_CMD_IQID(eq->iqid)); 2171 c.dcaen_to_eqsize = 2172 htobe32(V_FW_EQ_CTRL_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 2173 V_FW_EQ_CTRL_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 2174 V_FW_EQ_CTRL_CMD_CIDXFTHRESH(X_CIDXFLUSHTHRESH_32) | 2175 V_FW_EQ_CTRL_CMD_EQSIZE(eq->qsize)); 2176 c.eqaddr = htobe64(eq->ba); 2177 2178 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 2179 if (rc != 0) { 2180 device_printf(sc->dev, 2181 "failed to create control queue %d: %d\n", eq->tx_chan, rc); 2182 return (rc); 2183 } 2184 eq->flags |= EQ_ALLOCATED; 2185 2186 eq->cntxt_id = G_FW_EQ_CTRL_CMD_EQID(be32toh(c.cmpliqid_eqid)); 2187 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 2188 if (cntxt_id >= sc->sge.neq) 2189 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 2190 cntxt_id, sc->sge.neq - 1); 2191 sc->sge.eqmap[cntxt_id] = eq; 2192 2193 return (rc); 2194 } 2195 2196 static int 2197 eth_eq_alloc(struct adapter *sc, struct port_info *pi, struct sge_eq *eq) 2198 { 2199 int rc, cntxt_id; 2200 struct fw_eq_eth_cmd c; 2201 2202 bzero(&c, sizeof(c)); 2203 2204 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST | 2205 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) | 2206 V_FW_EQ_ETH_CMD_VFN(0)); 2207 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC | 2208 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c)); 2209 c.viid_pkd = htobe32(V_FW_EQ_ETH_CMD_VIID(pi->viid)); 2210 c.fetchszm_to_iqid = 2211 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 2212 V_FW_EQ_ETH_CMD_PCIECHN(eq->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO | 2213 V_FW_EQ_ETH_CMD_IQID(eq->iqid)); 2214 c.dcaen_to_eqsize = htobe32(V_FW_EQ_ETH_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 2215 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 2216 V_FW_EQ_ETH_CMD_CIDXFTHRESH(X_CIDXFLUSHTHRESH_32) | 2217 V_FW_EQ_ETH_CMD_EQSIZE(eq->qsize)); 2218 c.eqaddr = htobe64(eq->ba); 2219 2220 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 2221 if (rc != 0) { 2222 device_printf(pi->dev, 2223 "failed to create Ethernet egress queue: %d\n", rc); 2224 return (rc); 2225 } 2226 eq->flags |= EQ_ALLOCATED; 2227 2228 eq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd)); 2229 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 2230 if (cntxt_id >= sc->sge.neq) 2231 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 2232 cntxt_id, sc->sge.neq - 1); 2233 sc->sge.eqmap[cntxt_id] = eq; 2234 2235 return (rc); 2236 } 2237 2238 #ifdef TCP_OFFLOAD 2239 static int 2240 ofld_eq_alloc(struct adapter *sc, struct port_info *pi, struct sge_eq *eq) 2241 { 2242 int rc, cntxt_id; 2243 struct fw_eq_ofld_cmd c; 2244 2245 bzero(&c, sizeof(c)); 2246 2247 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | F_FW_CMD_REQUEST | 2248 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_OFLD_CMD_PFN(sc->pf) | 2249 V_FW_EQ_OFLD_CMD_VFN(0)); 2250 c.alloc_to_len16 = htonl(F_FW_EQ_OFLD_CMD_ALLOC | 2251 F_FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c)); 2252 c.fetchszm_to_iqid = 2253 htonl(V_FW_EQ_OFLD_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 2254 V_FW_EQ_OFLD_CMD_PCIECHN(eq->tx_chan) | 2255 F_FW_EQ_OFLD_CMD_FETCHRO | V_FW_EQ_OFLD_CMD_IQID(eq->iqid)); 2256 c.dcaen_to_eqsize = 2257 htobe32(V_FW_EQ_OFLD_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 2258 V_FW_EQ_OFLD_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 2259 V_FW_EQ_OFLD_CMD_CIDXFTHRESH(X_CIDXFLUSHTHRESH_32) | 2260 V_FW_EQ_OFLD_CMD_EQSIZE(eq->qsize)); 2261 c.eqaddr = htobe64(eq->ba); 2262 2263 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 2264 if (rc != 0) { 2265 device_printf(pi->dev, 2266 "failed to create egress queue for TCP offload: %d\n", rc); 2267 return (rc); 2268 } 2269 eq->flags |= EQ_ALLOCATED; 2270 2271 eq->cntxt_id = G_FW_EQ_OFLD_CMD_EQID(be32toh(c.eqid_pkd)); 2272 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 2273 if (cntxt_id >= sc->sge.neq) 2274 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 2275 cntxt_id, sc->sge.neq - 1); 2276 sc->sge.eqmap[cntxt_id] = eq; 2277 2278 return (rc); 2279 } 2280 #endif 2281 2282 static int 2283 alloc_eq(struct adapter *sc, struct port_info *pi, struct sge_eq *eq) 2284 { 2285 int rc; 2286 size_t len; 2287 2288 mtx_init(&eq->eq_lock, eq->lockname, NULL, MTX_DEF); 2289 2290 len = eq->qsize * EQ_ESIZE; 2291 rc = alloc_ring(sc, len, &eq->desc_tag, &eq->desc_map, 2292 &eq->ba, (void **)&eq->desc); 2293 if (rc) 2294 return (rc); 2295 2296 eq->cap = eq->qsize - spg_len / EQ_ESIZE; 2297 eq->spg = (void *)&eq->desc[eq->cap]; 2298 eq->avail = eq->cap - 1; /* one less to avoid cidx = pidx */ 2299 eq->pidx = eq->cidx = 0; 2300 eq->doorbells = sc->doorbells; 2301 2302 switch (eq->flags & EQ_TYPEMASK) { 2303 case EQ_CTRL: 2304 rc = ctrl_eq_alloc(sc, eq); 2305 break; 2306 2307 case EQ_ETH: 2308 rc = eth_eq_alloc(sc, pi, eq); 2309 break; 2310 2311 #ifdef TCP_OFFLOAD 2312 case EQ_OFLD: 2313 rc = ofld_eq_alloc(sc, pi, eq); 2314 break; 2315 #endif 2316 2317 default: 2318 panic("%s: invalid eq type %d.", __func__, 2319 eq->flags & EQ_TYPEMASK); 2320 } 2321 if (rc != 0) { 2322 device_printf(sc->dev, 2323 "failed to allocate egress queue(%d): %d", 2324 eq->flags & EQ_TYPEMASK, rc); 2325 } 2326 2327 eq->tx_callout.c_cpu = eq->cntxt_id % mp_ncpus; 2328 2329 if (isset(&eq->doorbells, DOORBELL_UDB) || 2330 isset(&eq->doorbells, DOORBELL_UDBWC) || 2331 isset(&eq->doorbells, DOORBELL_WCWR)) { 2332 uint32_t s_qpp = sc->sge.s_qpp; 2333 uint32_t mask = (1 << s_qpp) - 1; 2334 volatile uint8_t *udb; 2335 2336 udb = sc->udbs_base + UDBS_DB_OFFSET; 2337 udb += (eq->cntxt_id >> s_qpp) << PAGE_SHIFT; /* pg offset */ 2338 eq->udb_qid = eq->cntxt_id & mask; /* id in page */ 2339 if (eq->udb_qid > PAGE_SIZE / UDBS_SEG_SIZE) 2340 clrbit(&eq->doorbells, DOORBELL_WCWR); 2341 else { 2342 udb += eq->udb_qid << UDBS_SEG_SHIFT; /* seg offset */ 2343 eq->udb_qid = 0; 2344 } 2345 eq->udb = (volatile void *)udb; 2346 } 2347 2348 return (rc); 2349 } 2350 2351 static int 2352 free_eq(struct adapter *sc, struct sge_eq *eq) 2353 { 2354 int rc; 2355 2356 if (eq->flags & EQ_ALLOCATED) { 2357 switch (eq->flags & EQ_TYPEMASK) { 2358 case EQ_CTRL: 2359 rc = -t4_ctrl_eq_free(sc, sc->mbox, sc->pf, 0, 2360 eq->cntxt_id); 2361 break; 2362 2363 case EQ_ETH: 2364 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0, 2365 eq->cntxt_id); 2366 break; 2367 2368 #ifdef TCP_OFFLOAD 2369 case EQ_OFLD: 2370 rc = -t4_ofld_eq_free(sc, sc->mbox, sc->pf, 0, 2371 eq->cntxt_id); 2372 break; 2373 #endif 2374 2375 default: 2376 panic("%s: invalid eq type %d.", __func__, 2377 eq->flags & EQ_TYPEMASK); 2378 } 2379 if (rc != 0) { 2380 device_printf(sc->dev, 2381 "failed to free egress queue (%d): %d\n", 2382 eq->flags & EQ_TYPEMASK, rc); 2383 return (rc); 2384 } 2385 eq->flags &= ~EQ_ALLOCATED; 2386 } 2387 2388 free_ring(sc, eq->desc_tag, eq->desc_map, eq->ba, eq->desc); 2389 2390 if (mtx_initialized(&eq->eq_lock)) 2391 mtx_destroy(&eq->eq_lock); 2392 2393 bzero(eq, sizeof(*eq)); 2394 return (0); 2395 } 2396 2397 static int 2398 alloc_wrq(struct adapter *sc, struct port_info *pi, struct sge_wrq *wrq, 2399 struct sysctl_oid *oid) 2400 { 2401 int rc; 2402 struct sysctl_ctx_list *ctx = pi ? &pi->ctx : &sc->ctx; 2403 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 2404 2405 rc = alloc_eq(sc, pi, &wrq->eq); 2406 if (rc) 2407 return (rc); 2408 2409 wrq->adapter = sc; 2410 STAILQ_INIT(&wrq->wr_list); 2411 2412 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 2413 &wrq->eq.cntxt_id, 0, "SGE context id of the queue"); 2414 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx", 2415 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.cidx, 0, sysctl_uint16, "I", 2416 "consumer index"); 2417 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pidx", 2418 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.pidx, 0, sysctl_uint16, "I", 2419 "producer index"); 2420 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs", CTLFLAG_RD, 2421 &wrq->tx_wrs, "# of work requests"); 2422 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "no_desc", CTLFLAG_RD, 2423 &wrq->no_desc, 0, 2424 "# of times queue ran out of hardware descriptors"); 2425 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "unstalled", CTLFLAG_RD, 2426 &wrq->eq.unstalled, 0, "# of times queue recovered after stall"); 2427 2428 2429 return (rc); 2430 } 2431 2432 static int 2433 free_wrq(struct adapter *sc, struct sge_wrq *wrq) 2434 { 2435 int rc; 2436 2437 rc = free_eq(sc, &wrq->eq); 2438 if (rc) 2439 return (rc); 2440 2441 bzero(wrq, sizeof(*wrq)); 2442 return (0); 2443 } 2444 2445 static int 2446 alloc_txq(struct port_info *pi, struct sge_txq *txq, int idx, 2447 struct sysctl_oid *oid) 2448 { 2449 int rc; 2450 struct adapter *sc = pi->adapter; 2451 struct sge_eq *eq = &txq->eq; 2452 char name[16]; 2453 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 2454 2455 rc = alloc_eq(sc, pi, eq); 2456 if (rc) 2457 return (rc); 2458 2459 txq->ifp = pi->ifp; 2460 2461 txq->sdesc = malloc(eq->cap * sizeof(struct tx_sdesc), M_CXGBE, 2462 M_ZERO | M_WAITOK); 2463 txq->br = buf_ring_alloc(eq->qsize, M_CXGBE, M_WAITOK, &eq->eq_lock); 2464 2465 rc = bus_dma_tag_create(sc->dmat, 1, 0, BUS_SPACE_MAXADDR, 2466 BUS_SPACE_MAXADDR, NULL, NULL, 64 * 1024, TX_SGL_SEGS, 2467 BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL, NULL, &txq->tx_tag); 2468 if (rc != 0) { 2469 device_printf(sc->dev, 2470 "failed to create tx DMA tag: %d\n", rc); 2471 return (rc); 2472 } 2473 2474 /* 2475 * We can stuff ~10 frames in an 8-descriptor txpkts WR (8 is the SGE 2476 * limit for any WR). txq->no_dmamap events shouldn't occur if maps is 2477 * sized for the worst case. 2478 */ 2479 rc = t4_alloc_tx_maps(&txq->txmaps, txq->tx_tag, eq->qsize * 10 / 8, 2480 M_WAITOK); 2481 if (rc != 0) { 2482 device_printf(sc->dev, "failed to setup tx DMA maps: %d\n", rc); 2483 return (rc); 2484 } 2485 2486 snprintf(name, sizeof(name), "%d", idx); 2487 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 2488 NULL, "tx queue"); 2489 children = SYSCTL_CHILDREN(oid); 2490 2491 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 2492 &eq->cntxt_id, 0, "SGE context id of the queue"); 2493 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cidx", 2494 CTLTYPE_INT | CTLFLAG_RD, &eq->cidx, 0, sysctl_uint16, "I", 2495 "consumer index"); 2496 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "pidx", 2497 CTLTYPE_INT | CTLFLAG_RD, &eq->pidx, 0, sysctl_uint16, "I", 2498 "producer index"); 2499 2500 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "txcsum", CTLFLAG_RD, 2501 &txq->txcsum, "# of times hardware assisted with checksum"); 2502 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "vlan_insertion", 2503 CTLFLAG_RD, &txq->vlan_insertion, 2504 "# of times hardware inserted 802.1Q tag"); 2505 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "tso_wrs", CTLFLAG_RD, 2506 &txq->tso_wrs, "# of TSO work requests"); 2507 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "imm_wrs", CTLFLAG_RD, 2508 &txq->imm_wrs, "# of work requests with immediate data"); 2509 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "sgl_wrs", CTLFLAG_RD, 2510 &txq->sgl_wrs, "# of work requests with direct SGL"); 2511 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "txpkt_wrs", CTLFLAG_RD, 2512 &txq->txpkt_wrs, "# of txpkt work requests (one pkt/WR)"); 2513 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "txpkts_wrs", CTLFLAG_RD, 2514 &txq->txpkts_wrs, "# of txpkts work requests (multiple pkts/WR)"); 2515 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "txpkts_pkts", CTLFLAG_RD, 2516 &txq->txpkts_pkts, "# of frames tx'd using txpkts work requests"); 2517 2518 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "br_drops", CTLFLAG_RD, 2519 &txq->br->br_drops, "# of drops in the buf_ring for this queue"); 2520 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "no_dmamap", CTLFLAG_RD, 2521 &txq->no_dmamap, 0, "# of times txq ran out of DMA maps"); 2522 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "no_desc", CTLFLAG_RD, 2523 &txq->no_desc, 0, "# of times txq ran out of hardware descriptors"); 2524 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "egr_update", CTLFLAG_RD, 2525 &eq->egr_update, 0, "egress update notifications from the SGE"); 2526 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "unstalled", CTLFLAG_RD, 2527 &eq->unstalled, 0, "# of times txq recovered after stall"); 2528 2529 return (rc); 2530 } 2531 2532 static int 2533 free_txq(struct port_info *pi, struct sge_txq *txq) 2534 { 2535 int rc; 2536 struct adapter *sc = pi->adapter; 2537 struct sge_eq *eq = &txq->eq; 2538 2539 rc = free_eq(sc, eq); 2540 if (rc) 2541 return (rc); 2542 2543 free(txq->sdesc, M_CXGBE); 2544 2545 if (txq->txmaps.maps) 2546 t4_free_tx_maps(&txq->txmaps, txq->tx_tag); 2547 2548 buf_ring_free(txq->br, M_CXGBE); 2549 2550 if (txq->tx_tag) 2551 bus_dma_tag_destroy(txq->tx_tag); 2552 2553 bzero(txq, sizeof(*txq)); 2554 return (0); 2555 } 2556 2557 static void 2558 oneseg_dma_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2559 { 2560 bus_addr_t *ba = arg; 2561 2562 KASSERT(nseg == 1, 2563 ("%s meant for single segment mappings only.", __func__)); 2564 2565 *ba = error ? 0 : segs->ds_addr; 2566 } 2567 2568 static inline bool 2569 is_new_response(const struct sge_iq *iq, struct rsp_ctrl **ctrl) 2570 { 2571 *ctrl = (void *)((uintptr_t)iq->cdesc + 2572 (iq->esize - sizeof(struct rsp_ctrl))); 2573 2574 return (((*ctrl)->u.type_gen >> S_RSPD_GEN) == iq->gen); 2575 } 2576 2577 static inline void 2578 iq_next(struct sge_iq *iq) 2579 { 2580 iq->cdesc = (void *) ((uintptr_t)iq->cdesc + iq->esize); 2581 if (__predict_false(++iq->cidx == iq->qsize - 1)) { 2582 iq->cidx = 0; 2583 iq->gen ^= 1; 2584 iq->cdesc = iq->desc; 2585 } 2586 } 2587 2588 #define FL_HW_IDX(x) ((x) >> 3) 2589 static inline void 2590 ring_fl_db(struct adapter *sc, struct sge_fl *fl) 2591 { 2592 int ndesc = fl->pending / 8; 2593 uint32_t v; 2594 2595 if (FL_HW_IDX(fl->pidx) == FL_HW_IDX(fl->cidx)) 2596 ndesc--; /* hold back one credit */ 2597 2598 if (ndesc <= 0) 2599 return; /* nothing to do */ 2600 2601 v = F_DBPRIO | V_QID(fl->cntxt_id) | V_PIDX(ndesc); 2602 if (is_t5(sc)) 2603 v |= F_DBTYPE; 2604 2605 wmb(); 2606 2607 t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL), v); 2608 fl->pending -= ndesc * 8; 2609 } 2610 2611 /* 2612 * Fill up the freelist by upto nbufs and maybe ring its doorbell. 2613 * 2614 * Returns non-zero to indicate that it should be added to the list of starving 2615 * freelists. 2616 */ 2617 static int 2618 refill_fl(struct adapter *sc, struct sge_fl *fl, int nbufs) 2619 { 2620 __be64 *d = &fl->desc[fl->pidx]; 2621 struct fl_sdesc *sd = &fl->sdesc[fl->pidx]; 2622 bus_dma_tag_t tag; 2623 bus_addr_t pa; 2624 caddr_t cl; 2625 int rc; 2626 2627 FL_LOCK_ASSERT_OWNED(fl); 2628 2629 if (nbufs > fl->needed) 2630 nbufs = fl->needed; 2631 2632 while (nbufs--) { 2633 2634 if (sd->cl != NULL) { 2635 2636 /* 2637 * This happens when a frame small enough to fit 2638 * entirely in an mbuf was received in cl last time. 2639 * We'd held on to cl and can reuse it now. Note that 2640 * we reuse a cluster of the old size if fl->tag_idx is 2641 * no longer the same as sd->tag_idx. 2642 */ 2643 2644 KASSERT(*d == sd->ba_tag, 2645 ("%s: recyling problem at pidx %d", 2646 __func__, fl->pidx)); 2647 2648 d++; 2649 goto recycled; 2650 } 2651 2652 2653 if (fl->tag_idx != sd->tag_idx) { 2654 bus_dmamap_t map; 2655 bus_dma_tag_t newtag = fl->tag[fl->tag_idx]; 2656 bus_dma_tag_t oldtag = fl->tag[sd->tag_idx]; 2657 2658 /* 2659 * An MTU change can get us here. Discard the old map 2660 * which was created with the old tag, but only if 2661 * we're able to get a new one. 2662 */ 2663 rc = bus_dmamap_create(newtag, 0, &map); 2664 if (rc == 0) { 2665 bus_dmamap_destroy(oldtag, sd->map); 2666 sd->map = map; 2667 sd->tag_idx = fl->tag_idx; 2668 } 2669 } 2670 2671 tag = fl->tag[sd->tag_idx]; 2672 2673 cl = m_cljget(NULL, M_NOWAIT, FL_BUF_SIZE(sd->tag_idx)); 2674 if (cl == NULL) 2675 break; 2676 2677 rc = bus_dmamap_load(tag, sd->map, cl, FL_BUF_SIZE(sd->tag_idx), 2678 oneseg_dma_callback, &pa, 0); 2679 if (rc != 0 || pa == 0) { 2680 fl->dmamap_failed++; 2681 uma_zfree(FL_BUF_ZONE(sd->tag_idx), cl); 2682 break; 2683 } 2684 2685 sd->cl = cl; 2686 *d++ = htobe64(pa | sd->tag_idx); 2687 2688 #ifdef INVARIANTS 2689 sd->ba_tag = htobe64(pa | sd->tag_idx); 2690 #endif 2691 2692 recycled: 2693 /* sd->m is never recycled, should always be NULL */ 2694 KASSERT(sd->m == NULL, ("%s: stray mbuf", __func__)); 2695 2696 sd->m = m_gethdr(M_NOWAIT, MT_NOINIT); 2697 if (sd->m == NULL) 2698 break; 2699 2700 fl->pending++; 2701 fl->needed--; 2702 sd++; 2703 if (++fl->pidx == fl->cap) { 2704 fl->pidx = 0; 2705 sd = fl->sdesc; 2706 d = fl->desc; 2707 } 2708 } 2709 2710 if (fl->pending >= 8) 2711 ring_fl_db(sc, fl); 2712 2713 return (FL_RUNNING_LOW(fl) && !(fl->flags & FL_STARVING)); 2714 } 2715 2716 /* 2717 * Attempt to refill all starving freelists. 2718 */ 2719 static void 2720 refill_sfl(void *arg) 2721 { 2722 struct adapter *sc = arg; 2723 struct sge_fl *fl, *fl_temp; 2724 2725 mtx_lock(&sc->sfl_lock); 2726 TAILQ_FOREACH_SAFE(fl, &sc->sfl, link, fl_temp) { 2727 FL_LOCK(fl); 2728 refill_fl(sc, fl, 64); 2729 if (FL_NOT_RUNNING_LOW(fl) || fl->flags & FL_DOOMED) { 2730 TAILQ_REMOVE(&sc->sfl, fl, link); 2731 fl->flags &= ~FL_STARVING; 2732 } 2733 FL_UNLOCK(fl); 2734 } 2735 2736 if (!TAILQ_EMPTY(&sc->sfl)) 2737 callout_schedule(&sc->sfl_callout, hz / 5); 2738 mtx_unlock(&sc->sfl_lock); 2739 } 2740 2741 static int 2742 alloc_fl_sdesc(struct sge_fl *fl) 2743 { 2744 struct fl_sdesc *sd; 2745 bus_dma_tag_t tag; 2746 int i, rc; 2747 2748 FL_LOCK_ASSERT_OWNED(fl); 2749 2750 fl->sdesc = malloc(fl->cap * sizeof(struct fl_sdesc), M_CXGBE, 2751 M_ZERO | M_WAITOK); 2752 2753 tag = fl->tag[fl->tag_idx]; 2754 sd = fl->sdesc; 2755 for (i = 0; i < fl->cap; i++, sd++) { 2756 2757 sd->tag_idx = fl->tag_idx; 2758 rc = bus_dmamap_create(tag, 0, &sd->map); 2759 if (rc != 0) 2760 goto failed; 2761 } 2762 2763 return (0); 2764 failed: 2765 while (--i >= 0) { 2766 sd--; 2767 bus_dmamap_destroy(tag, sd->map); 2768 if (sd->m) { 2769 m_init(sd->m, NULL, 0, M_NOWAIT, MT_DATA, 0); 2770 m_free(sd->m); 2771 sd->m = NULL; 2772 } 2773 } 2774 KASSERT(sd == fl->sdesc, ("%s: EDOOFUS", __func__)); 2775 2776 free(fl->sdesc, M_CXGBE); 2777 fl->sdesc = NULL; 2778 2779 return (rc); 2780 } 2781 2782 static void 2783 free_fl_sdesc(struct sge_fl *fl) 2784 { 2785 struct fl_sdesc *sd; 2786 int i; 2787 2788 FL_LOCK_ASSERT_OWNED(fl); 2789 2790 sd = fl->sdesc; 2791 for (i = 0; i < fl->cap; i++, sd++) { 2792 2793 if (sd->m) { 2794 m_init(sd->m, NULL, 0, M_NOWAIT, MT_DATA, 0); 2795 m_free(sd->m); 2796 sd->m = NULL; 2797 } 2798 2799 if (sd->cl) { 2800 bus_dmamap_unload(fl->tag[sd->tag_idx], sd->map); 2801 uma_zfree(FL_BUF_ZONE(sd->tag_idx), sd->cl); 2802 sd->cl = NULL; 2803 } 2804 2805 bus_dmamap_destroy(fl->tag[sd->tag_idx], sd->map); 2806 } 2807 2808 free(fl->sdesc, M_CXGBE); 2809 fl->sdesc = NULL; 2810 } 2811 2812 int 2813 t4_alloc_tx_maps(struct tx_maps *txmaps, bus_dma_tag_t tx_tag, int count, 2814 int flags) 2815 { 2816 struct tx_map *txm; 2817 int i, rc; 2818 2819 txmaps->map_total = txmaps->map_avail = count; 2820 txmaps->map_cidx = txmaps->map_pidx = 0; 2821 2822 txmaps->maps = malloc(count * sizeof(struct tx_map), M_CXGBE, 2823 M_ZERO | flags); 2824 2825 txm = txmaps->maps; 2826 for (i = 0; i < count; i++, txm++) { 2827 rc = bus_dmamap_create(tx_tag, 0, &txm->map); 2828 if (rc != 0) 2829 goto failed; 2830 } 2831 2832 return (0); 2833 failed: 2834 while (--i >= 0) { 2835 txm--; 2836 bus_dmamap_destroy(tx_tag, txm->map); 2837 } 2838 KASSERT(txm == txmaps->maps, ("%s: EDOOFUS", __func__)); 2839 2840 free(txmaps->maps, M_CXGBE); 2841 txmaps->maps = NULL; 2842 2843 return (rc); 2844 } 2845 2846 void 2847 t4_free_tx_maps(struct tx_maps *txmaps, bus_dma_tag_t tx_tag) 2848 { 2849 struct tx_map *txm; 2850 int i; 2851 2852 txm = txmaps->maps; 2853 for (i = 0; i < txmaps->map_total; i++, txm++) { 2854 2855 if (txm->m) { 2856 bus_dmamap_unload(tx_tag, txm->map); 2857 m_freem(txm->m); 2858 txm->m = NULL; 2859 } 2860 2861 bus_dmamap_destroy(tx_tag, txm->map); 2862 } 2863 2864 free(txmaps->maps, M_CXGBE); 2865 txmaps->maps = NULL; 2866 } 2867 2868 /* 2869 * We'll do immediate data tx for non-TSO, but only when not coalescing. We're 2870 * willing to use upto 2 hardware descriptors which means a maximum of 96 bytes 2871 * of immediate data. 2872 */ 2873 #define IMM_LEN ( \ 2874 2 * EQ_ESIZE \ 2875 - sizeof(struct fw_eth_tx_pkt_wr) \ 2876 - sizeof(struct cpl_tx_pkt_core)) 2877 2878 /* 2879 * Returns non-zero on failure, no need to cleanup anything in that case. 2880 * 2881 * Note 1: We always try to defrag the mbuf if required and return EFBIG only 2882 * if the resulting chain still won't fit in a tx descriptor. 2883 * 2884 * Note 2: We'll pullup the mbuf chain if TSO is requested and the first mbuf 2885 * does not have the TCP header in it. 2886 */ 2887 static int 2888 get_pkt_sgl(struct sge_txq *txq, struct mbuf **fp, struct sgl *sgl, 2889 int sgl_only) 2890 { 2891 struct mbuf *m = *fp; 2892 struct tx_maps *txmaps; 2893 struct tx_map *txm; 2894 int rc, defragged = 0, n; 2895 2896 TXQ_LOCK_ASSERT_OWNED(txq); 2897 2898 if (m->m_pkthdr.tso_segsz) 2899 sgl_only = 1; /* Do not allow immediate data with LSO */ 2900 2901 start: sgl->nsegs = 0; 2902 2903 if (m->m_pkthdr.len <= IMM_LEN && !sgl_only) 2904 return (0); /* nsegs = 0 tells caller to use imm. tx */ 2905 2906 txmaps = &txq->txmaps; 2907 if (txmaps->map_avail == 0) { 2908 txq->no_dmamap++; 2909 return (ENOMEM); 2910 } 2911 txm = &txmaps->maps[txmaps->map_pidx]; 2912 2913 if (m->m_pkthdr.tso_segsz && m->m_len < 50) { 2914 *fp = m_pullup(m, 50); 2915 m = *fp; 2916 if (m == NULL) 2917 return (ENOBUFS); 2918 } 2919 2920 rc = bus_dmamap_load_mbuf_sg(txq->tx_tag, txm->map, m, sgl->seg, 2921 &sgl->nsegs, BUS_DMA_NOWAIT); 2922 if (rc == EFBIG && defragged == 0) { 2923 m = m_defrag(m, M_NOWAIT); 2924 if (m == NULL) 2925 return (EFBIG); 2926 2927 defragged = 1; 2928 *fp = m; 2929 goto start; 2930 } 2931 if (rc != 0) 2932 return (rc); 2933 2934 txm->m = m; 2935 txmaps->map_avail--; 2936 if (++txmaps->map_pidx == txmaps->map_total) 2937 txmaps->map_pidx = 0; 2938 2939 KASSERT(sgl->nsegs > 0 && sgl->nsegs <= TX_SGL_SEGS, 2940 ("%s: bad DMA mapping (%d segments)", __func__, sgl->nsegs)); 2941 2942 /* 2943 * Store the # of flits required to hold this frame's SGL in nflits. An 2944 * SGL has a (ULPTX header + len0, addr0) tuple optionally followed by 2945 * multiple (len0 + len1, addr0, addr1) tuples. If addr1 is not used 2946 * then len1 must be set to 0. 2947 */ 2948 n = sgl->nsegs - 1; 2949 sgl->nflits = (3 * n) / 2 + (n & 1) + 2; 2950 2951 return (0); 2952 } 2953 2954 2955 /* 2956 * Releases all the txq resources used up in the specified sgl. 2957 */ 2958 static int 2959 free_pkt_sgl(struct sge_txq *txq, struct sgl *sgl) 2960 { 2961 struct tx_maps *txmaps; 2962 struct tx_map *txm; 2963 2964 TXQ_LOCK_ASSERT_OWNED(txq); 2965 2966 if (sgl->nsegs == 0) 2967 return (0); /* didn't use any map */ 2968 2969 txmaps = &txq->txmaps; 2970 2971 /* 1 pkt uses exactly 1 map, back it out */ 2972 2973 txmaps->map_avail++; 2974 if (txmaps->map_pidx > 0) 2975 txmaps->map_pidx--; 2976 else 2977 txmaps->map_pidx = txmaps->map_total - 1; 2978 2979 txm = &txmaps->maps[txmaps->map_pidx]; 2980 bus_dmamap_unload(txq->tx_tag, txm->map); 2981 txm->m = NULL; 2982 2983 return (0); 2984 } 2985 2986 static int 2987 write_txpkt_wr(struct port_info *pi, struct sge_txq *txq, struct mbuf *m, 2988 struct sgl *sgl) 2989 { 2990 struct sge_eq *eq = &txq->eq; 2991 struct fw_eth_tx_pkt_wr *wr; 2992 struct cpl_tx_pkt_core *cpl; 2993 uint32_t ctrl; /* used in many unrelated places */ 2994 uint64_t ctrl1; 2995 int nflits, ndesc, pktlen; 2996 struct tx_sdesc *txsd; 2997 caddr_t dst; 2998 2999 TXQ_LOCK_ASSERT_OWNED(txq); 3000 3001 pktlen = m->m_pkthdr.len; 3002 3003 /* 3004 * Do we have enough flits to send this frame out? 3005 */ 3006 ctrl = sizeof(struct cpl_tx_pkt_core); 3007 if (m->m_pkthdr.tso_segsz) { 3008 nflits = TXPKT_LSO_WR_HDR; 3009 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 3010 } else 3011 nflits = TXPKT_WR_HDR; 3012 if (sgl->nsegs > 0) 3013 nflits += sgl->nflits; 3014 else { 3015 nflits += howmany(pktlen, 8); 3016 ctrl += pktlen; 3017 } 3018 ndesc = howmany(nflits, 8); 3019 if (ndesc > eq->avail) 3020 return (ENOMEM); 3021 3022 /* Firmware work request header */ 3023 wr = (void *)&eq->desc[eq->pidx]; 3024 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_WR) | 3025 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl)); 3026 ctrl = V_FW_WR_LEN16(howmany(nflits, 2)); 3027 if (eq->avail == ndesc) { 3028 if (!(eq->flags & EQ_CRFLUSHED)) { 3029 ctrl |= F_FW_WR_EQUEQ | F_FW_WR_EQUIQ; 3030 eq->flags |= EQ_CRFLUSHED; 3031 } 3032 eq->flags |= EQ_STALLED; 3033 } 3034 3035 wr->equiq_to_len16 = htobe32(ctrl); 3036 wr->r3 = 0; 3037 3038 if (m->m_pkthdr.tso_segsz) { 3039 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1); 3040 struct ether_header *eh; 3041 void *l3hdr; 3042 #if defined(INET) || defined(INET6) 3043 struct tcphdr *tcp; 3044 #endif 3045 uint16_t eh_type; 3046 3047 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE | 3048 F_LSO_LAST_SLICE; 3049 3050 eh = mtod(m, struct ether_header *); 3051 eh_type = ntohs(eh->ether_type); 3052 if (eh_type == ETHERTYPE_VLAN) { 3053 struct ether_vlan_header *evh = (void *)eh; 3054 3055 ctrl |= V_LSO_ETHHDR_LEN(1); 3056 l3hdr = evh + 1; 3057 eh_type = ntohs(evh->evl_proto); 3058 } else 3059 l3hdr = eh + 1; 3060 3061 switch (eh_type) { 3062 #ifdef INET6 3063 case ETHERTYPE_IPV6: 3064 { 3065 struct ip6_hdr *ip6 = l3hdr; 3066 3067 /* 3068 * XXX-BZ For now we do not pretend to support 3069 * IPv6 extension headers. 3070 */ 3071 KASSERT(ip6->ip6_nxt == IPPROTO_TCP, ("%s: CSUM_TSO " 3072 "with ip6_nxt != TCP: %u", __func__, ip6->ip6_nxt)); 3073 tcp = (struct tcphdr *)(ip6 + 1); 3074 ctrl |= F_LSO_IPV6; 3075 ctrl |= V_LSO_IPHDR_LEN(sizeof(*ip6) >> 2) | 3076 V_LSO_TCPHDR_LEN(tcp->th_off); 3077 break; 3078 } 3079 #endif 3080 #ifdef INET 3081 case ETHERTYPE_IP: 3082 { 3083 struct ip *ip = l3hdr; 3084 3085 tcp = (void *)((uintptr_t)ip + ip->ip_hl * 4); 3086 ctrl |= V_LSO_IPHDR_LEN(ip->ip_hl) | 3087 V_LSO_TCPHDR_LEN(tcp->th_off); 3088 break; 3089 } 3090 #endif 3091 default: 3092 panic("%s: CSUM_TSO but no supported IP version " 3093 "(0x%04x)", __func__, eh_type); 3094 } 3095 3096 lso->lso_ctrl = htobe32(ctrl); 3097 lso->ipid_ofst = htobe16(0); 3098 lso->mss = htobe16(m->m_pkthdr.tso_segsz); 3099 lso->seqno_offset = htobe32(0); 3100 lso->len = htobe32(pktlen); 3101 3102 cpl = (void *)(lso + 1); 3103 3104 txq->tso_wrs++; 3105 } else 3106 cpl = (void *)(wr + 1); 3107 3108 /* Checksum offload */ 3109 ctrl1 = 0; 3110 if (!(m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TSO))) 3111 ctrl1 |= F_TXPKT_IPCSUM_DIS; 3112 if (!(m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_UDP_IPV6 | 3113 CSUM_TCP_IPV6 | CSUM_TSO))) 3114 ctrl1 |= F_TXPKT_L4CSUM_DIS; 3115 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | 3116 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO)) 3117 txq->txcsum++; /* some hardware assistance provided */ 3118 3119 /* VLAN tag insertion */ 3120 if (m->m_flags & M_VLANTAG) { 3121 ctrl1 |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(m->m_pkthdr.ether_vtag); 3122 txq->vlan_insertion++; 3123 } 3124 3125 /* CPL header */ 3126 cpl->ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) | 3127 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(pi->adapter->pf)); 3128 cpl->pack = 0; 3129 cpl->len = htobe16(pktlen); 3130 cpl->ctrl1 = htobe64(ctrl1); 3131 3132 /* Software descriptor */ 3133 txsd = &txq->sdesc[eq->pidx]; 3134 txsd->desc_used = ndesc; 3135 3136 eq->pending += ndesc; 3137 eq->avail -= ndesc; 3138 eq->pidx += ndesc; 3139 if (eq->pidx >= eq->cap) 3140 eq->pidx -= eq->cap; 3141 3142 /* SGL */ 3143 dst = (void *)(cpl + 1); 3144 if (sgl->nsegs > 0) { 3145 txsd->credits = 1; 3146 txq->sgl_wrs++; 3147 write_sgl_to_txd(eq, sgl, &dst); 3148 } else { 3149 txsd->credits = 0; 3150 txq->imm_wrs++; 3151 for (; m; m = m->m_next) { 3152 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len); 3153 #ifdef INVARIANTS 3154 pktlen -= m->m_len; 3155 #endif 3156 } 3157 #ifdef INVARIANTS 3158 KASSERT(pktlen == 0, ("%s: %d bytes left.", __func__, pktlen)); 3159 #endif 3160 3161 } 3162 3163 txq->txpkt_wrs++; 3164 return (0); 3165 } 3166 3167 /* 3168 * Returns 0 to indicate that m has been accepted into a coalesced tx work 3169 * request. It has either been folded into txpkts or txpkts was flushed and m 3170 * has started a new coalesced work request (as the first frame in a fresh 3171 * txpkts). 3172 * 3173 * Returns non-zero to indicate a failure - caller is responsible for 3174 * transmitting m, if there was anything in txpkts it has been flushed. 3175 */ 3176 static int 3177 add_to_txpkts(struct port_info *pi, struct sge_txq *txq, struct txpkts *txpkts, 3178 struct mbuf *m, struct sgl *sgl) 3179 { 3180 struct sge_eq *eq = &txq->eq; 3181 int can_coalesce; 3182 struct tx_sdesc *txsd; 3183 int flits; 3184 3185 TXQ_LOCK_ASSERT_OWNED(txq); 3186 3187 KASSERT(sgl->nsegs, ("%s: can't coalesce imm data", __func__)); 3188 3189 if (txpkts->npkt > 0) { 3190 flits = TXPKTS_PKT_HDR + sgl->nflits; 3191 can_coalesce = m->m_pkthdr.tso_segsz == 0 && 3192 txpkts->nflits + flits <= TX_WR_FLITS && 3193 txpkts->nflits + flits <= eq->avail * 8 && 3194 txpkts->plen + m->m_pkthdr.len < 65536; 3195 3196 if (can_coalesce) { 3197 txpkts->npkt++; 3198 txpkts->nflits += flits; 3199 txpkts->plen += m->m_pkthdr.len; 3200 3201 txsd = &txq->sdesc[eq->pidx]; 3202 txsd->credits++; 3203 3204 return (0); 3205 } 3206 3207 /* 3208 * Couldn't coalesce m into txpkts. The first order of business 3209 * is to send txpkts on its way. Then we'll revisit m. 3210 */ 3211 write_txpkts_wr(txq, txpkts); 3212 } 3213 3214 /* 3215 * Check if we can start a new coalesced tx work request with m as 3216 * the first packet in it. 3217 */ 3218 3219 KASSERT(txpkts->npkt == 0, ("%s: txpkts not empty", __func__)); 3220 3221 flits = TXPKTS_WR_HDR + sgl->nflits; 3222 can_coalesce = m->m_pkthdr.tso_segsz == 0 && 3223 flits <= eq->avail * 8 && flits <= TX_WR_FLITS; 3224 3225 if (can_coalesce == 0) 3226 return (EINVAL); 3227 3228 /* 3229 * Start a fresh coalesced tx WR with m as the first frame in it. 3230 */ 3231 txpkts->npkt = 1; 3232 txpkts->nflits = flits; 3233 txpkts->flitp = &eq->desc[eq->pidx].flit[2]; 3234 txpkts->plen = m->m_pkthdr.len; 3235 3236 txsd = &txq->sdesc[eq->pidx]; 3237 txsd->credits = 1; 3238 3239 return (0); 3240 } 3241 3242 /* 3243 * Note that write_txpkts_wr can never run out of hardware descriptors (but 3244 * write_txpkt_wr can). add_to_txpkts ensures that a frame is accepted for 3245 * coalescing only if sufficient hardware descriptors are available. 3246 */ 3247 static void 3248 write_txpkts_wr(struct sge_txq *txq, struct txpkts *txpkts) 3249 { 3250 struct sge_eq *eq = &txq->eq; 3251 struct fw_eth_tx_pkts_wr *wr; 3252 struct tx_sdesc *txsd; 3253 uint32_t ctrl; 3254 int ndesc; 3255 3256 TXQ_LOCK_ASSERT_OWNED(txq); 3257 3258 ndesc = howmany(txpkts->nflits, 8); 3259 3260 wr = (void *)&eq->desc[eq->pidx]; 3261 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR)); 3262 ctrl = V_FW_WR_LEN16(howmany(txpkts->nflits, 2)); 3263 if (eq->avail == ndesc) { 3264 if (!(eq->flags & EQ_CRFLUSHED)) { 3265 ctrl |= F_FW_WR_EQUEQ | F_FW_WR_EQUIQ; 3266 eq->flags |= EQ_CRFLUSHED; 3267 } 3268 eq->flags |= EQ_STALLED; 3269 } 3270 wr->equiq_to_len16 = htobe32(ctrl); 3271 wr->plen = htobe16(txpkts->plen); 3272 wr->npkt = txpkts->npkt; 3273 wr->r3 = wr->type = 0; 3274 3275 /* Everything else already written */ 3276 3277 txsd = &txq->sdesc[eq->pidx]; 3278 txsd->desc_used = ndesc; 3279 3280 KASSERT(eq->avail >= ndesc, ("%s: out of descriptors", __func__)); 3281 3282 eq->pending += ndesc; 3283 eq->avail -= ndesc; 3284 eq->pidx += ndesc; 3285 if (eq->pidx >= eq->cap) 3286 eq->pidx -= eq->cap; 3287 3288 txq->txpkts_pkts += txpkts->npkt; 3289 txq->txpkts_wrs++; 3290 txpkts->npkt = 0; /* emptied */ 3291 } 3292 3293 static inline void 3294 write_ulp_cpl_sgl(struct port_info *pi, struct sge_txq *txq, 3295 struct txpkts *txpkts, struct mbuf *m, struct sgl *sgl) 3296 { 3297 struct ulp_txpkt *ulpmc; 3298 struct ulptx_idata *ulpsc; 3299 struct cpl_tx_pkt_core *cpl; 3300 struct sge_eq *eq = &txq->eq; 3301 uintptr_t flitp, start, end; 3302 uint64_t ctrl; 3303 caddr_t dst; 3304 3305 KASSERT(txpkts->npkt > 0, ("%s: txpkts is empty", __func__)); 3306 3307 start = (uintptr_t)eq->desc; 3308 end = (uintptr_t)eq->spg; 3309 3310 /* Checksum offload */ 3311 ctrl = 0; 3312 if (!(m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TSO))) 3313 ctrl |= F_TXPKT_IPCSUM_DIS; 3314 if (!(m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_UDP_IPV6 | 3315 CSUM_TCP_IPV6 | CSUM_TSO))) 3316 ctrl |= F_TXPKT_L4CSUM_DIS; 3317 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | 3318 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO)) 3319 txq->txcsum++; /* some hardware assistance provided */ 3320 3321 /* VLAN tag insertion */ 3322 if (m->m_flags & M_VLANTAG) { 3323 ctrl |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(m->m_pkthdr.ether_vtag); 3324 txq->vlan_insertion++; 3325 } 3326 3327 /* 3328 * The previous packet's SGL must have ended at a 16 byte boundary (this 3329 * is required by the firmware/hardware). It follows that flitp cannot 3330 * wrap around between the ULPTX master command and ULPTX subcommand (8 3331 * bytes each), and that it can not wrap around in the middle of the 3332 * cpl_tx_pkt_core either. 3333 */ 3334 flitp = (uintptr_t)txpkts->flitp; 3335 KASSERT((flitp & 0xf) == 0, 3336 ("%s: last SGL did not end at 16 byte boundary: %p", 3337 __func__, txpkts->flitp)); 3338 3339 /* ULP master command */ 3340 ulpmc = (void *)flitp; 3341 ulpmc->cmd_dest = htonl(V_ULPTX_CMD(ULP_TX_PKT) | V_ULP_TXPKT_DEST(0) | 3342 V_ULP_TXPKT_FID(eq->iqid)); 3343 ulpmc->len = htonl(howmany(sizeof(*ulpmc) + sizeof(*ulpsc) + 3344 sizeof(*cpl) + 8 * sgl->nflits, 16)); 3345 3346 /* ULP subcommand */ 3347 ulpsc = (void *)(ulpmc + 1); 3348 ulpsc->cmd_more = htobe32(V_ULPTX_CMD((u32)ULP_TX_SC_IMM) | 3349 F_ULP_TX_SC_MORE); 3350 ulpsc->len = htobe32(sizeof(struct cpl_tx_pkt_core)); 3351 3352 flitp += sizeof(*ulpmc) + sizeof(*ulpsc); 3353 if (flitp == end) 3354 flitp = start; 3355 3356 /* CPL_TX_PKT */ 3357 cpl = (void *)flitp; 3358 cpl->ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) | 3359 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(pi->adapter->pf)); 3360 cpl->pack = 0; 3361 cpl->len = htobe16(m->m_pkthdr.len); 3362 cpl->ctrl1 = htobe64(ctrl); 3363 3364 flitp += sizeof(*cpl); 3365 if (flitp == end) 3366 flitp = start; 3367 3368 /* SGL for this frame */ 3369 dst = (caddr_t)flitp; 3370 txpkts->nflits += write_sgl_to_txd(eq, sgl, &dst); 3371 txpkts->flitp = (void *)dst; 3372 3373 KASSERT(((uintptr_t)dst & 0xf) == 0, 3374 ("%s: SGL ends at %p (not a 16 byte boundary)", __func__, dst)); 3375 } 3376 3377 /* 3378 * If the SGL ends on an address that is not 16 byte aligned, this function will 3379 * add a 0 filled flit at the end. It returns 1 in that case. 3380 */ 3381 static int 3382 write_sgl_to_txd(struct sge_eq *eq, struct sgl *sgl, caddr_t *to) 3383 { 3384 __be64 *flitp, *end; 3385 struct ulptx_sgl *usgl; 3386 bus_dma_segment_t *seg; 3387 int i, padded; 3388 3389 KASSERT(sgl->nsegs > 0 && sgl->nflits > 0, 3390 ("%s: bad SGL - nsegs=%d, nflits=%d", 3391 __func__, sgl->nsegs, sgl->nflits)); 3392 3393 KASSERT(((uintptr_t)(*to) & 0xf) == 0, 3394 ("%s: SGL must start at a 16 byte boundary: %p", __func__, *to)); 3395 3396 flitp = (__be64 *)(*to); 3397 end = flitp + sgl->nflits; 3398 seg = &sgl->seg[0]; 3399 usgl = (void *)flitp; 3400 3401 /* 3402 * We start at a 16 byte boundary somewhere inside the tx descriptor 3403 * ring, so we're at least 16 bytes away from the status page. There is 3404 * no chance of a wrap around in the middle of usgl (which is 16 bytes). 3405 */ 3406 3407 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 3408 V_ULPTX_NSGE(sgl->nsegs)); 3409 usgl->len0 = htobe32(seg->ds_len); 3410 usgl->addr0 = htobe64(seg->ds_addr); 3411 seg++; 3412 3413 if ((uintptr_t)end <= (uintptr_t)eq->spg) { 3414 3415 /* Won't wrap around at all */ 3416 3417 for (i = 0; i < sgl->nsegs - 1; i++, seg++) { 3418 usgl->sge[i / 2].len[i & 1] = htobe32(seg->ds_len); 3419 usgl->sge[i / 2].addr[i & 1] = htobe64(seg->ds_addr); 3420 } 3421 if (i & 1) 3422 usgl->sge[i / 2].len[1] = htobe32(0); 3423 } else { 3424 3425 /* Will wrap somewhere in the rest of the SGL */ 3426 3427 /* 2 flits already written, write the rest flit by flit */ 3428 flitp = (void *)(usgl + 1); 3429 for (i = 0; i < sgl->nflits - 2; i++) { 3430 if ((uintptr_t)flitp == (uintptr_t)eq->spg) 3431 flitp = (void *)eq->desc; 3432 *flitp++ = get_flit(seg, sgl->nsegs - 1, i); 3433 } 3434 end = flitp; 3435 } 3436 3437 if ((uintptr_t)end & 0xf) { 3438 *(uint64_t *)end = 0; 3439 end++; 3440 padded = 1; 3441 } else 3442 padded = 0; 3443 3444 if ((uintptr_t)end == (uintptr_t)eq->spg) 3445 *to = (void *)eq->desc; 3446 else 3447 *to = (void *)end; 3448 3449 return (padded); 3450 } 3451 3452 static inline void 3453 copy_to_txd(struct sge_eq *eq, caddr_t from, caddr_t *to, int len) 3454 { 3455 if (__predict_true((uintptr_t)(*to) + len <= (uintptr_t)eq->spg)) { 3456 bcopy(from, *to, len); 3457 (*to) += len; 3458 } else { 3459 int portion = (uintptr_t)eq->spg - (uintptr_t)(*to); 3460 3461 bcopy(from, *to, portion); 3462 from += portion; 3463 portion = len - portion; /* remaining */ 3464 bcopy(from, (void *)eq->desc, portion); 3465 (*to) = (caddr_t)eq->desc + portion; 3466 } 3467 } 3468 3469 static inline void 3470 ring_eq_db(struct adapter *sc, struct sge_eq *eq) 3471 { 3472 u_int db, pending; 3473 3474 db = eq->doorbells; 3475 pending = eq->pending; 3476 if (pending > 1) 3477 clrbit(&db, DOORBELL_WCWR); 3478 eq->pending = 0; 3479 wmb(); 3480 3481 switch (ffs(db) - 1) { 3482 case DOORBELL_UDB: 3483 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(pending)); 3484 return; 3485 3486 case DOORBELL_WCWR: { 3487 volatile uint64_t *dst, *src; 3488 int i; 3489 3490 /* 3491 * Queues whose 128B doorbell segment fits in the page do not 3492 * use relative qid (udb_qid is always 0). Only queues with 3493 * doorbell segments can do WCWR. 3494 */ 3495 KASSERT(eq->udb_qid == 0 && pending == 1, 3496 ("%s: inappropriate doorbell (0x%x, %d, %d) for eq %p", 3497 __func__, eq->doorbells, pending, eq->pidx, eq)); 3498 3499 dst = (volatile void *)((uintptr_t)eq->udb + UDBS_WR_OFFSET - 3500 UDBS_DB_OFFSET); 3501 i = eq->pidx ? eq->pidx - 1 : eq->cap - 1; 3502 src = (void *)&eq->desc[i]; 3503 while (src != (void *)&eq->desc[i + 1]) 3504 *dst++ = *src++; 3505 wmb(); 3506 return; 3507 } 3508 3509 case DOORBELL_UDBWC: 3510 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(pending)); 3511 wmb(); 3512 return; 3513 3514 case DOORBELL_KDB: 3515 t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL), 3516 V_QID(eq->cntxt_id) | V_PIDX(pending)); 3517 return; 3518 } 3519 } 3520 3521 static inline int 3522 reclaimable(struct sge_eq *eq) 3523 { 3524 unsigned int cidx; 3525 3526 cidx = eq->spg->cidx; /* stable snapshot */ 3527 cidx = be16toh(cidx); 3528 3529 if (cidx >= eq->cidx) 3530 return (cidx - eq->cidx); 3531 else 3532 return (cidx + eq->cap - eq->cidx); 3533 } 3534 3535 /* 3536 * There are "can_reclaim" tx descriptors ready to be reclaimed. Reclaim as 3537 * many as possible but stop when there are around "n" mbufs to free. 3538 * 3539 * The actual number reclaimed is provided as the return value. 3540 */ 3541 static int 3542 reclaim_tx_descs(struct sge_txq *txq, int can_reclaim, int n) 3543 { 3544 struct tx_sdesc *txsd; 3545 struct tx_maps *txmaps; 3546 struct tx_map *txm; 3547 unsigned int reclaimed, maps; 3548 struct sge_eq *eq = &txq->eq; 3549 3550 TXQ_LOCK_ASSERT_OWNED(txq); 3551 3552 if (can_reclaim == 0) 3553 can_reclaim = reclaimable(eq); 3554 3555 maps = reclaimed = 0; 3556 while (can_reclaim && maps < n) { 3557 int ndesc; 3558 3559 txsd = &txq->sdesc[eq->cidx]; 3560 ndesc = txsd->desc_used; 3561 3562 /* Firmware doesn't return "partial" credits. */ 3563 KASSERT(can_reclaim >= ndesc, 3564 ("%s: unexpected number of credits: %d, %d", 3565 __func__, can_reclaim, ndesc)); 3566 3567 maps += txsd->credits; 3568 3569 reclaimed += ndesc; 3570 can_reclaim -= ndesc; 3571 3572 eq->cidx += ndesc; 3573 if (__predict_false(eq->cidx >= eq->cap)) 3574 eq->cidx -= eq->cap; 3575 } 3576 3577 txmaps = &txq->txmaps; 3578 txm = &txmaps->maps[txmaps->map_cidx]; 3579 if (maps) 3580 prefetch(txm->m); 3581 3582 eq->avail += reclaimed; 3583 KASSERT(eq->avail < eq->cap, /* avail tops out at (cap - 1) */ 3584 ("%s: too many descriptors available", __func__)); 3585 3586 txmaps->map_avail += maps; 3587 KASSERT(txmaps->map_avail <= txmaps->map_total, 3588 ("%s: too many maps available", __func__)); 3589 3590 while (maps--) { 3591 struct tx_map *next; 3592 3593 next = txm + 1; 3594 if (__predict_false(txmaps->map_cidx + 1 == txmaps->map_total)) 3595 next = txmaps->maps; 3596 prefetch(next->m); 3597 3598 bus_dmamap_unload(txq->tx_tag, txm->map); 3599 m_freem(txm->m); 3600 txm->m = NULL; 3601 3602 txm = next; 3603 if (__predict_false(++txmaps->map_cidx == txmaps->map_total)) 3604 txmaps->map_cidx = 0; 3605 } 3606 3607 return (reclaimed); 3608 } 3609 3610 static void 3611 write_eqflush_wr(struct sge_eq *eq) 3612 { 3613 struct fw_eq_flush_wr *wr; 3614 3615 EQ_LOCK_ASSERT_OWNED(eq); 3616 KASSERT(eq->avail > 0, ("%s: no descriptors left.", __func__)); 3617 KASSERT(!(eq->flags & EQ_CRFLUSHED), ("%s: flushed already", __func__)); 3618 3619 wr = (void *)&eq->desc[eq->pidx]; 3620 bzero(wr, sizeof(*wr)); 3621 wr->opcode = FW_EQ_FLUSH_WR; 3622 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(sizeof(*wr) / 16) | 3623 F_FW_WR_EQUEQ | F_FW_WR_EQUIQ); 3624 3625 eq->flags |= (EQ_CRFLUSHED | EQ_STALLED); 3626 eq->pending++; 3627 eq->avail--; 3628 if (++eq->pidx == eq->cap) 3629 eq->pidx = 0; 3630 } 3631 3632 static __be64 3633 get_flit(bus_dma_segment_t *sgl, int nsegs, int idx) 3634 { 3635 int i = (idx / 3) * 2; 3636 3637 switch (idx % 3) { 3638 case 0: { 3639 __be64 rc; 3640 3641 rc = htobe32(sgl[i].ds_len); 3642 if (i + 1 < nsegs) 3643 rc |= (uint64_t)htobe32(sgl[i + 1].ds_len) << 32; 3644 3645 return (rc); 3646 } 3647 case 1: 3648 return htobe64(sgl[i].ds_addr); 3649 case 2: 3650 return htobe64(sgl[i + 1].ds_addr); 3651 } 3652 3653 return (0); 3654 } 3655 3656 static void 3657 set_fl_tag_idx(struct sge_fl *fl, int bufsize) 3658 { 3659 int i; 3660 3661 for (i = 0; i < FL_BUF_SIZES - 1; i++) { 3662 if (FL_BUF_SIZE(i) >= bufsize) 3663 break; 3664 } 3665 3666 fl->tag_idx = i; 3667 } 3668 3669 static void 3670 add_fl_to_sfl(struct adapter *sc, struct sge_fl *fl) 3671 { 3672 mtx_lock(&sc->sfl_lock); 3673 FL_LOCK(fl); 3674 if ((fl->flags & FL_DOOMED) == 0) { 3675 fl->flags |= FL_STARVING; 3676 TAILQ_INSERT_TAIL(&sc->sfl, fl, link); 3677 callout_reset(&sc->sfl_callout, hz / 5, refill_sfl, sc); 3678 } 3679 FL_UNLOCK(fl); 3680 mtx_unlock(&sc->sfl_lock); 3681 } 3682 3683 static int 3684 handle_sge_egr_update(struct sge_iq *iq, const struct rss_header *rss, 3685 struct mbuf *m) 3686 { 3687 const struct cpl_sge_egr_update *cpl = (const void *)(rss + 1); 3688 unsigned int qid = G_EGR_QID(ntohl(cpl->opcode_qid)); 3689 struct adapter *sc = iq->adapter; 3690 struct sge *s = &sc->sge; 3691 struct sge_eq *eq; 3692 3693 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 3694 rss->opcode)); 3695 3696 eq = s->eqmap[qid - s->eq_start]; 3697 EQ_LOCK(eq); 3698 KASSERT(eq->flags & EQ_CRFLUSHED, 3699 ("%s: unsolicited egress update", __func__)); 3700 eq->flags &= ~EQ_CRFLUSHED; 3701 eq->egr_update++; 3702 3703 if (__predict_false(eq->flags & EQ_DOOMED)) 3704 wakeup_one(eq); 3705 else if (eq->flags & EQ_STALLED && can_resume_tx(eq)) 3706 taskqueue_enqueue(sc->tq[eq->tx_chan], &eq->tx_task); 3707 EQ_UNLOCK(eq); 3708 3709 return (0); 3710 } 3711 3712 /* handle_fw_msg works for both fw4_msg and fw6_msg because this is valid */ 3713 CTASSERT(offsetof(struct cpl_fw4_msg, data) == \ 3714 offsetof(struct cpl_fw6_msg, data)); 3715 3716 static int 3717 handle_fw_msg(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 3718 { 3719 struct adapter *sc = iq->adapter; 3720 const struct cpl_fw6_msg *cpl = (const void *)(rss + 1); 3721 3722 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 3723 rss->opcode)); 3724 3725 if (cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL) { 3726 const struct rss_header *rss2; 3727 3728 rss2 = (const struct rss_header *)&cpl->data[0]; 3729 return (sc->cpl_handler[rss2->opcode](iq, rss2, m)); 3730 } 3731 3732 return (sc->fw_msg_handler[cpl->type](sc, &cpl->data[0])); 3733 } 3734 3735 static int 3736 sysctl_uint16(SYSCTL_HANDLER_ARGS) 3737 { 3738 uint16_t *id = arg1; 3739 int i = *id; 3740 3741 return sysctl_handle_int(oidp, &i, 0, req); 3742 } 3743