1 /*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 33 #include <sys/types.h> 34 #include <sys/mbuf.h> 35 #include <sys/socket.h> 36 #include <sys/kernel.h> 37 #include <sys/malloc.h> 38 #include <sys/queue.h> 39 #include <sys/taskqueue.h> 40 #include <sys/sysctl.h> 41 #include <sys/smp.h> 42 #include <net/bpf.h> 43 #include <net/ethernet.h> 44 #include <net/if.h> 45 #include <net/if_vlan_var.h> 46 #include <netinet/in.h> 47 #include <netinet/ip.h> 48 #include <netinet/tcp.h> 49 50 #include "common/common.h" 51 #include "common/t4_regs.h" 52 #include "common/t4_regs_values.h" 53 #include "common/t4_msg.h" 54 #include "t4_l2t.h" 55 56 struct fl_buf_info { 57 int size; 58 int type; 59 uma_zone_t zone; 60 }; 61 62 /* Filled up by t4_sge_modload */ 63 static struct fl_buf_info fl_buf_info[FL_BUF_SIZES]; 64 65 #define FL_BUF_SIZE(x) (fl_buf_info[x].size) 66 #define FL_BUF_TYPE(x) (fl_buf_info[x].type) 67 #define FL_BUF_ZONE(x) (fl_buf_info[x].zone) 68 69 enum { 70 FL_PKTSHIFT = 2 71 }; 72 73 #define FL_ALIGN min(CACHE_LINE_SIZE, 32) 74 #if CACHE_LINE_SIZE > 64 75 #define SPG_LEN 128 76 #else 77 #define SPG_LEN 64 78 #endif 79 80 /* Used to track coalesced tx work request */ 81 struct txpkts { 82 uint64_t *flitp; /* ptr to flit where next pkt should start */ 83 uint8_t npkt; /* # of packets in this work request */ 84 uint8_t nflits; /* # of flits used by this work request */ 85 uint16_t plen; /* total payload (sum of all packets) */ 86 }; 87 88 /* A packet's SGL. This + m_pkthdr has all info needed for tx */ 89 struct sgl { 90 int nsegs; /* # of segments in the SGL, 0 means imm. tx */ 91 int nflits; /* # of flits needed for the SGL */ 92 bus_dma_segment_t seg[TX_SGL_SEGS]; 93 }; 94 95 static int service_iq(struct sge_iq *, int); 96 static struct mbuf *get_fl_payload(struct adapter *, struct sge_fl *, uint32_t, 97 int *); 98 static int t4_eth_rx(struct sge_iq *, const struct rss_header *, struct mbuf *); 99 static inline void init_iq(struct sge_iq *, struct adapter *, int, int, int, 100 int, char *); 101 static inline void init_fl(struct sge_fl *, int, int, char *); 102 static inline void init_eq(struct sge_eq *, int, int, uint8_t, uint16_t, 103 char *); 104 static int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *, 105 bus_addr_t *, void **); 106 static int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 107 void *); 108 static int alloc_iq_fl(struct port_info *, struct sge_iq *, struct sge_fl *, 109 int, int); 110 static int free_iq_fl(struct port_info *, struct sge_iq *, struct sge_fl *); 111 static int alloc_fwq(struct adapter *); 112 static int free_fwq(struct adapter *); 113 static int alloc_mgmtq(struct adapter *); 114 static int free_mgmtq(struct adapter *); 115 static int alloc_rxq(struct port_info *, struct sge_rxq *, int, int, 116 struct sysctl_oid *); 117 static int free_rxq(struct port_info *, struct sge_rxq *); 118 #ifndef TCP_OFFLOAD_DISABLE 119 static int alloc_ofld_rxq(struct port_info *, struct sge_ofld_rxq *, int, int, 120 struct sysctl_oid *); 121 static int free_ofld_rxq(struct port_info *, struct sge_ofld_rxq *); 122 #endif 123 static int ctrl_eq_alloc(struct adapter *, struct sge_eq *); 124 static int eth_eq_alloc(struct adapter *, struct port_info *, struct sge_eq *); 125 #ifndef TCP_OFFLOAD_DISABLE 126 static int ofld_eq_alloc(struct adapter *, struct port_info *, struct sge_eq *); 127 #endif 128 static int alloc_eq(struct adapter *, struct port_info *, struct sge_eq *); 129 static int free_eq(struct adapter *, struct sge_eq *); 130 static int alloc_wrq(struct adapter *, struct port_info *, struct sge_wrq *, 131 struct sysctl_oid *); 132 static int free_wrq(struct adapter *, struct sge_wrq *); 133 static int alloc_txq(struct port_info *, struct sge_txq *, int, 134 struct sysctl_oid *); 135 static int free_txq(struct port_info *, struct sge_txq *); 136 static void oneseg_dma_callback(void *, bus_dma_segment_t *, int, int); 137 static inline bool is_new_response(const struct sge_iq *, struct rsp_ctrl **); 138 static inline void iq_next(struct sge_iq *); 139 static inline void ring_fl_db(struct adapter *, struct sge_fl *); 140 static int refill_fl(struct adapter *, struct sge_fl *, int); 141 static void refill_sfl(void *); 142 static int alloc_fl_sdesc(struct sge_fl *); 143 static void free_fl_sdesc(struct sge_fl *); 144 static void set_fl_tag_idx(struct sge_fl *, int); 145 static void add_fl_to_sfl(struct adapter *, struct sge_fl *); 146 147 static int get_pkt_sgl(struct sge_txq *, struct mbuf **, struct sgl *, int); 148 static int free_pkt_sgl(struct sge_txq *, struct sgl *); 149 static int write_txpkt_wr(struct port_info *, struct sge_txq *, struct mbuf *, 150 struct sgl *); 151 static int add_to_txpkts(struct port_info *, struct sge_txq *, struct txpkts *, 152 struct mbuf *, struct sgl *); 153 static void write_txpkts_wr(struct sge_txq *, struct txpkts *); 154 static inline void write_ulp_cpl_sgl(struct port_info *, struct sge_txq *, 155 struct txpkts *, struct mbuf *, struct sgl *); 156 static int write_sgl_to_txd(struct sge_eq *, struct sgl *, caddr_t *); 157 static inline void copy_to_txd(struct sge_eq *, caddr_t, caddr_t *, int); 158 static inline void ring_eq_db(struct adapter *, struct sge_eq *); 159 static inline int reclaimable(struct sge_eq *); 160 static int reclaim_tx_descs(struct sge_txq *, int, int); 161 static void write_eqflush_wr(struct sge_eq *); 162 static __be64 get_flit(bus_dma_segment_t *, int, int); 163 static int handle_sge_egr_update(struct sge_iq *, const struct rss_header *, 164 struct mbuf *); 165 static int handle_fw_rpl(struct sge_iq *, const struct rss_header *, 166 struct mbuf *); 167 168 static int sysctl_uint16(SYSCTL_HANDLER_ARGS); 169 170 /* 171 * Called on MOD_LOAD and fills up fl_buf_info[]. 172 */ 173 void 174 t4_sge_modload(void) 175 { 176 int i; 177 int bufsize[FL_BUF_SIZES] = { 178 MCLBYTES, 179 #if MJUMPAGESIZE != MCLBYTES 180 MJUMPAGESIZE, 181 #endif 182 MJUM9BYTES, 183 MJUM16BYTES 184 }; 185 186 for (i = 0; i < FL_BUF_SIZES; i++) { 187 FL_BUF_SIZE(i) = bufsize[i]; 188 FL_BUF_TYPE(i) = m_gettype(bufsize[i]); 189 FL_BUF_ZONE(i) = m_getzone(bufsize[i]); 190 } 191 } 192 193 /** 194 * t4_sge_init - initialize SGE 195 * @sc: the adapter 196 * 197 * Performs SGE initialization needed every time after a chip reset. 198 * We do not initialize any of the queues here, instead the driver 199 * top-level must request them individually. 200 */ 201 int 202 t4_sge_init(struct adapter *sc) 203 { 204 struct sge *s = &sc->sge; 205 int i, rc = 0; 206 uint32_t ctrl_mask, ctrl_val, hpsize, v; 207 208 ctrl_mask = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | 209 V_INGPADBOUNDARY(M_INGPADBOUNDARY) | 210 F_EGRSTATUSPAGESIZE; 211 ctrl_val = V_PKTSHIFT(FL_PKTSHIFT) | F_RXPKTCPLMODE | 212 V_INGPADBOUNDARY(ilog2(FL_ALIGN) - 5) | 213 V_EGRSTATUSPAGESIZE(SPG_LEN == 128); 214 215 hpsize = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) | 216 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) | 217 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) | 218 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) | 219 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) | 220 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) | 221 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) | 222 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10); 223 224 if (sc->flags & MASTER_PF) { 225 int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200}; 226 int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */ 227 228 t4_set_reg_field(sc, A_SGE_CONTROL, ctrl_mask, ctrl_val); 229 t4_write_reg(sc, A_SGE_HOST_PAGE_SIZE, hpsize); 230 for (i = 0; i < FL_BUF_SIZES; i++) { 231 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0 + (4 * i), 232 FL_BUF_SIZE(i)); 233 } 234 235 t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD, 236 V_THRESHOLD_0(intr_pktcount[0]) | 237 V_THRESHOLD_1(intr_pktcount[1]) | 238 V_THRESHOLD_2(intr_pktcount[2]) | 239 V_THRESHOLD_3(intr_pktcount[3])); 240 241 t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1, 242 V_TIMERVALUE0(us_to_core_ticks(sc, intr_timer[0])) | 243 V_TIMERVALUE1(us_to_core_ticks(sc, intr_timer[1]))); 244 t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3, 245 V_TIMERVALUE2(us_to_core_ticks(sc, intr_timer[2])) | 246 V_TIMERVALUE3(us_to_core_ticks(sc, intr_timer[3]))); 247 t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5, 248 V_TIMERVALUE4(us_to_core_ticks(sc, intr_timer[4])) | 249 V_TIMERVALUE5(us_to_core_ticks(sc, intr_timer[5]))); 250 } 251 252 v = t4_read_reg(sc, A_SGE_CONTROL); 253 if ((v & ctrl_mask) != ctrl_val) { 254 device_printf(sc->dev, "invalid SGE_CONTROL(0x%x)\n", v); 255 rc = EINVAL; 256 } 257 258 v = t4_read_reg(sc, A_SGE_HOST_PAGE_SIZE); 259 if (v != hpsize) { 260 device_printf(sc->dev, "invalid SGE_HOST_PAGE_SIZE(0x%x)\n", v); 261 rc = EINVAL; 262 } 263 264 for (i = 0; i < FL_BUF_SIZES; i++) { 265 v = t4_read_reg(sc, A_SGE_FL_BUFFER_SIZE0 + (4 * i)); 266 if (v != FL_BUF_SIZE(i)) { 267 device_printf(sc->dev, 268 "invalid SGE_FL_BUFFER_SIZE[%d](0x%x)\n", i, v); 269 rc = EINVAL; 270 } 271 } 272 273 v = t4_read_reg(sc, A_SGE_CONM_CTRL); 274 s->fl_starve_threshold = G_EGRTHRESHOLD(v) * 2 + 1; 275 276 v = t4_read_reg(sc, A_SGE_INGRESS_RX_THRESHOLD); 277 sc->sge.counter_val[0] = G_THRESHOLD_0(v); 278 sc->sge.counter_val[1] = G_THRESHOLD_1(v); 279 sc->sge.counter_val[2] = G_THRESHOLD_2(v); 280 sc->sge.counter_val[3] = G_THRESHOLD_3(v); 281 282 v = t4_read_reg(sc, A_SGE_TIMER_VALUE_0_AND_1); 283 sc->sge.timer_val[0] = G_TIMERVALUE0(v) / core_ticks_per_usec(sc); 284 sc->sge.timer_val[1] = G_TIMERVALUE1(v) / core_ticks_per_usec(sc); 285 v = t4_read_reg(sc, A_SGE_TIMER_VALUE_2_AND_3); 286 sc->sge.timer_val[2] = G_TIMERVALUE2(v) / core_ticks_per_usec(sc); 287 sc->sge.timer_val[3] = G_TIMERVALUE3(v) / core_ticks_per_usec(sc); 288 v = t4_read_reg(sc, A_SGE_TIMER_VALUE_4_AND_5); 289 sc->sge.timer_val[4] = G_TIMERVALUE4(v) / core_ticks_per_usec(sc); 290 sc->sge.timer_val[5] = G_TIMERVALUE5(v) / core_ticks_per_usec(sc); 291 292 t4_register_cpl_handler(sc, CPL_FW4_MSG, handle_fw_rpl); 293 t4_register_cpl_handler(sc, CPL_FW6_MSG, handle_fw_rpl); 294 t4_register_cpl_handler(sc, CPL_SGE_EGR_UPDATE, handle_sge_egr_update); 295 t4_register_cpl_handler(sc, CPL_RX_PKT, t4_eth_rx); 296 297 return (rc); 298 } 299 300 int 301 t4_create_dma_tag(struct adapter *sc) 302 { 303 int rc; 304 305 rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0, 306 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE, 307 BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL, 308 NULL, &sc->dmat); 309 if (rc != 0) { 310 device_printf(sc->dev, 311 "failed to create main DMA tag: %d\n", rc); 312 } 313 314 return (rc); 315 } 316 317 int 318 t4_destroy_dma_tag(struct adapter *sc) 319 { 320 if (sc->dmat) 321 bus_dma_tag_destroy(sc->dmat); 322 323 return (0); 324 } 325 326 /* 327 * Allocate and initialize the firmware event queue and the management queue. 328 * 329 * Returns errno on failure. Resources allocated up to that point may still be 330 * allocated. Caller is responsible for cleanup in case this function fails. 331 */ 332 int 333 t4_setup_adapter_queues(struct adapter *sc) 334 { 335 int rc; 336 337 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 338 339 sysctl_ctx_init(&sc->ctx); 340 sc->flags |= ADAP_SYSCTL_CTX; 341 342 /* 343 * Firmware event queue 344 */ 345 rc = alloc_fwq(sc); 346 if (rc != 0) { 347 device_printf(sc->dev, 348 "failed to create firmware event queue: %d\n", rc); 349 return (rc); 350 } 351 352 /* 353 * Management queue. This is just a control queue that uses the fwq as 354 * its associated iq. 355 */ 356 rc = alloc_mgmtq(sc); 357 if (rc != 0) { 358 device_printf(sc->dev, 359 "failed to create management queue: %d\n", rc); 360 return (rc); 361 } 362 363 return (rc); 364 } 365 366 /* 367 * Idempotent 368 */ 369 int 370 t4_teardown_adapter_queues(struct adapter *sc) 371 { 372 373 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 374 375 /* Do this before freeing the queue */ 376 if (sc->flags & ADAP_SYSCTL_CTX) { 377 sysctl_ctx_free(&sc->ctx); 378 sc->flags &= ~ADAP_SYSCTL_CTX; 379 } 380 381 free_mgmtq(sc); 382 free_fwq(sc); 383 384 return (0); 385 } 386 387 static inline int 388 first_vector(struct port_info *pi) 389 { 390 struct adapter *sc = pi->adapter; 391 int rc = T4_EXTRA_INTR, i; 392 393 if (sc->intr_count == 1) 394 return (0); 395 396 for_each_port(sc, i) { 397 if (i == pi->port_id) 398 break; 399 400 #ifndef TCP_OFFLOAD_DISABLE 401 if (sc->flags & INTR_DIRECT) 402 rc += pi->nrxq + pi->nofldrxq; 403 else 404 rc += max(pi->nrxq, pi->nofldrxq); 405 #else 406 /* 407 * Not compiled with offload support and intr_count > 1. Only 408 * NIC queues exist and they'd better be taking direct 409 * interrupts. 410 */ 411 KASSERT(sc->flags & INTR_DIRECT, 412 ("%s: intr_count %d, !INTR_DIRECT", __func__, 413 sc->intr_count)); 414 415 rc += pi->nrxq; 416 #endif 417 } 418 419 return (rc); 420 } 421 422 /* 423 * Given an arbitrary "index," come up with an iq that can be used by other 424 * queues (of this port) for interrupt forwarding, SGE egress updates, etc. 425 * The iq returned is guaranteed to be something that takes direct interrupts. 426 */ 427 static struct sge_iq * 428 port_intr_iq(struct port_info *pi, int idx) 429 { 430 struct adapter *sc = pi->adapter; 431 struct sge *s = &sc->sge; 432 struct sge_iq *iq = NULL; 433 434 if (sc->intr_count == 1) 435 return (&sc->sge.fwq); 436 437 #ifndef TCP_OFFLOAD_DISABLE 438 if (sc->flags & INTR_DIRECT) { 439 idx %= pi->nrxq + pi->nofldrxq; 440 441 if (idx >= pi->nrxq) { 442 idx -= pi->nrxq; 443 iq = &s->ofld_rxq[pi->first_ofld_rxq + idx].iq; 444 } else 445 iq = &s->rxq[pi->first_rxq + idx].iq; 446 447 } else { 448 idx %= max(pi->nrxq, pi->nofldrxq); 449 450 if (pi->nrxq >= pi->nofldrxq) 451 iq = &s->rxq[pi->first_rxq + idx].iq; 452 else 453 iq = &s->ofld_rxq[pi->first_ofld_rxq + idx].iq; 454 } 455 #else 456 /* 457 * Not compiled with offload support and intr_count > 1. Only NIC 458 * queues exist and they'd better be taking direct interrupts. 459 */ 460 KASSERT(sc->flags & INTR_DIRECT, 461 ("%s: intr_count %d, !INTR_DIRECT", __func__, sc->intr_count)); 462 463 idx %= pi->nrxq; 464 iq = &s->rxq[pi->first_rxq + idx].iq; 465 #endif 466 467 KASSERT(iq->flags & IQ_INTR, ("%s: EDOOFUS", __func__)); 468 return (iq); 469 } 470 471 int 472 t4_setup_port_queues(struct port_info *pi) 473 { 474 int rc = 0, i, j, intr_idx, iqid; 475 struct sge_rxq *rxq; 476 struct sge_txq *txq; 477 struct sge_wrq *ctrlq; 478 #ifndef TCP_OFFLOAD_DISABLE 479 struct sge_ofld_rxq *ofld_rxq; 480 struct sge_wrq *ofld_txq; 481 #endif 482 char name[16]; 483 struct adapter *sc = pi->adapter; 484 struct sysctl_oid *oid = device_get_sysctl_tree(pi->dev), *oid2 = NULL; 485 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 486 487 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "rxq", CTLFLAG_RD, 488 NULL, "rx queues"); 489 490 #ifndef TCP_OFFLOAD_DISABLE 491 if (is_offload(sc)) { 492 oid2 = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "ofld_rxq", 493 CTLFLAG_RD, NULL, 494 "rx queues for offloaded TCP connections"); 495 } 496 #endif 497 498 /* Interrupt vector to start from (when using multiple vectors) */ 499 intr_idx = first_vector(pi); 500 501 /* 502 * First pass over all rx queues (NIC and TOE): 503 * a) initialize iq and fl 504 * b) allocate queue iff it will take direct interrupts. 505 */ 506 for_each_rxq(pi, i, rxq) { 507 508 snprintf(name, sizeof(name), "%s rxq%d-iq", 509 device_get_nameunit(pi->dev), i); 510 init_iq(&rxq->iq, sc, pi->tmr_idx, pi->pktc_idx, pi->qsize_rxq, 511 RX_IQ_ESIZE, name); 512 513 snprintf(name, sizeof(name), "%s rxq%d-fl", 514 device_get_nameunit(pi->dev), i); 515 init_fl(&rxq->fl, pi->qsize_rxq / 8, pi->ifp->if_mtu, name); 516 517 if (sc->flags & INTR_DIRECT 518 #ifndef TCP_OFFLOAD_DISABLE 519 || (sc->intr_count > 1 && pi->nrxq >= pi->nofldrxq) 520 #endif 521 ) { 522 rxq->iq.flags |= IQ_INTR; 523 rc = alloc_rxq(pi, rxq, intr_idx, i, oid); 524 if (rc != 0) 525 goto done; 526 intr_idx++; 527 } 528 } 529 530 #ifndef TCP_OFFLOAD_DISABLE 531 for_each_ofld_rxq(pi, i, ofld_rxq) { 532 533 snprintf(name, sizeof(name), "%s ofld_rxq%d-iq", 534 device_get_nameunit(pi->dev), i); 535 init_iq(&ofld_rxq->iq, sc, pi->tmr_idx, pi->pktc_idx, 536 pi->qsize_rxq, RX_IQ_ESIZE, name); 537 538 snprintf(name, sizeof(name), "%s ofld_rxq%d-fl", 539 device_get_nameunit(pi->dev), i); 540 init_fl(&ofld_rxq->fl, pi->qsize_rxq / 8, MJUM16BYTES, name); 541 542 if (sc->flags & INTR_DIRECT || 543 (sc->intr_count > 1 && pi->nofldrxq > pi->nrxq)) { 544 ofld_rxq->iq.flags |= IQ_INTR; 545 rc = alloc_ofld_rxq(pi, ofld_rxq, intr_idx, i, oid2); 546 if (rc != 0) 547 goto done; 548 intr_idx++; 549 } 550 } 551 #endif 552 553 /* 554 * Second pass over all rx queues (NIC and TOE). The queues forwarding 555 * their interrupts are allocated now. 556 */ 557 j = 0; 558 for_each_rxq(pi, i, rxq) { 559 if (rxq->iq.flags & IQ_INTR) 560 continue; 561 562 intr_idx = port_intr_iq(pi, j)->abs_id; 563 564 rc = alloc_rxq(pi, rxq, intr_idx, i, oid); 565 if (rc != 0) 566 goto done; 567 j++; 568 } 569 570 #ifndef TCP_OFFLOAD_DISABLE 571 for_each_ofld_rxq(pi, i, ofld_rxq) { 572 if (ofld_rxq->iq.flags & IQ_INTR) 573 continue; 574 575 intr_idx = port_intr_iq(pi, j)->abs_id; 576 577 rc = alloc_ofld_rxq(pi, ofld_rxq, intr_idx, i, oid2); 578 if (rc != 0) 579 goto done; 580 j++; 581 } 582 #endif 583 584 /* 585 * Now the tx queues. Only one pass needed. 586 */ 587 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "txq", CTLFLAG_RD, 588 NULL, "tx queues"); 589 j = 0; 590 for_each_txq(pi, i, txq) { 591 uint16_t iqid; 592 593 iqid = port_intr_iq(pi, j)->cntxt_id; 594 595 snprintf(name, sizeof(name), "%s txq%d", 596 device_get_nameunit(pi->dev), i); 597 init_eq(&txq->eq, EQ_ETH, pi->qsize_txq, pi->tx_chan, iqid, 598 name); 599 600 rc = alloc_txq(pi, txq, i, oid); 601 if (rc != 0) 602 goto done; 603 j++; 604 } 605 606 #ifndef TCP_OFFLOAD_DISABLE 607 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "ofld_txq", 608 CTLFLAG_RD, NULL, "tx queues for offloaded TCP connections"); 609 for_each_ofld_txq(pi, i, ofld_txq) { 610 uint16_t iqid; 611 612 iqid = port_intr_iq(pi, j)->cntxt_id; 613 614 snprintf(name, sizeof(name), "%s ofld_txq%d", 615 device_get_nameunit(pi->dev), i); 616 init_eq(&ofld_txq->eq, EQ_OFLD, pi->qsize_txq, pi->tx_chan, 617 iqid, name); 618 619 snprintf(name, sizeof(name), "%d", i); 620 oid2 = SYSCTL_ADD_NODE(&pi->ctx, SYSCTL_CHILDREN(oid), OID_AUTO, 621 name, CTLFLAG_RD, NULL, "offload tx queue"); 622 623 rc = alloc_wrq(sc, pi, ofld_txq, oid2); 624 if (rc != 0) 625 goto done; 626 j++; 627 } 628 #endif 629 630 /* 631 * Finally, the control queue. 632 */ 633 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "ctrlq", CTLFLAG_RD, 634 NULL, "ctrl queue"); 635 ctrlq = &sc->sge.ctrlq[pi->port_id]; 636 iqid = port_intr_iq(pi, 0)->cntxt_id; 637 snprintf(name, sizeof(name), "%s ctrlq", device_get_nameunit(pi->dev)); 638 init_eq(&ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE, pi->tx_chan, iqid, name); 639 rc = alloc_wrq(sc, pi, ctrlq, oid); 640 641 done: 642 if (rc) 643 t4_teardown_port_queues(pi); 644 645 return (rc); 646 } 647 648 /* 649 * Idempotent 650 */ 651 int 652 t4_teardown_port_queues(struct port_info *pi) 653 { 654 int i; 655 struct adapter *sc = pi->adapter; 656 struct sge_rxq *rxq; 657 struct sge_txq *txq; 658 #ifndef TCP_OFFLOAD_DISABLE 659 struct sge_ofld_rxq *ofld_rxq; 660 struct sge_wrq *ofld_txq; 661 #endif 662 663 /* Do this before freeing the queues */ 664 if (pi->flags & PORT_SYSCTL_CTX) { 665 sysctl_ctx_free(&pi->ctx); 666 pi->flags &= ~PORT_SYSCTL_CTX; 667 } 668 669 /* 670 * Take down all the tx queues first, as they reference the rx queues 671 * (for egress updates, etc.). 672 */ 673 674 free_wrq(sc, &sc->sge.ctrlq[pi->port_id]); 675 676 for_each_txq(pi, i, txq) { 677 free_txq(pi, txq); 678 } 679 680 #ifndef TCP_OFFLOAD_DISABLE 681 for_each_ofld_txq(pi, i, ofld_txq) { 682 free_wrq(sc, ofld_txq); 683 } 684 #endif 685 686 /* 687 * Then take down the rx queues that forward their interrupts, as they 688 * reference other rx queues. 689 */ 690 691 for_each_rxq(pi, i, rxq) { 692 if ((rxq->iq.flags & IQ_INTR) == 0) 693 free_rxq(pi, rxq); 694 } 695 696 #ifndef TCP_OFFLOAD_DISABLE 697 for_each_ofld_rxq(pi, i, ofld_rxq) { 698 if ((ofld_rxq->iq.flags & IQ_INTR) == 0) 699 free_ofld_rxq(pi, ofld_rxq); 700 } 701 #endif 702 703 /* 704 * Then take down the rx queues that take direct interrupts. 705 */ 706 707 for_each_rxq(pi, i, rxq) { 708 if (rxq->iq.flags & IQ_INTR) 709 free_rxq(pi, rxq); 710 } 711 712 #ifndef TCP_OFFLOAD_DISABLE 713 for_each_ofld_rxq(pi, i, ofld_rxq) { 714 if (ofld_rxq->iq.flags & IQ_INTR) 715 free_ofld_rxq(pi, ofld_rxq); 716 } 717 #endif 718 719 return (0); 720 } 721 722 /* 723 * Deals with errors and the firmware event queue. All data rx queues forward 724 * their interrupt to the firmware event queue. 725 */ 726 void 727 t4_intr_all(void *arg) 728 { 729 struct adapter *sc = arg; 730 struct sge_iq *fwq = &sc->sge.fwq; 731 732 t4_intr_err(arg); 733 if (atomic_cmpset_int(&fwq->state, IQS_IDLE, IQS_BUSY)) { 734 service_iq(fwq, 0); 735 atomic_cmpset_int(&fwq->state, IQS_BUSY, IQS_IDLE); 736 } 737 } 738 739 /* Deals with error interrupts */ 740 void 741 t4_intr_err(void *arg) 742 { 743 struct adapter *sc = arg; 744 745 t4_write_reg(sc, MYPF_REG(A_PCIE_PF_CLI), 0); 746 t4_slow_intr_handler(sc); 747 } 748 749 void 750 t4_intr_evt(void *arg) 751 { 752 struct sge_iq *iq = arg; 753 754 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 755 service_iq(iq, 0); 756 atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 757 } 758 } 759 760 void 761 t4_intr(void *arg) 762 { 763 struct sge_iq *iq = arg; 764 765 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 766 service_iq(iq, 0); 767 atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 768 } 769 } 770 771 /* 772 * Deals with anything and everything on the given ingress queue. 773 */ 774 static int 775 service_iq(struct sge_iq *iq, int budget) 776 { 777 struct sge_iq *q; 778 struct sge_rxq *rxq = (void *)iq; /* Use iff iq is part of rxq */ 779 struct sge_fl *fl = &rxq->fl; /* Use iff IQ_HAS_FL */ 780 struct adapter *sc = iq->adapter; 781 struct rsp_ctrl *ctrl; 782 const struct rss_header *rss; 783 int ndescs = 0, limit, fl_bufs_used = 0; 784 int rsp_type; 785 uint32_t lq; 786 struct mbuf *m0; 787 STAILQ_HEAD(, sge_iq) iql = STAILQ_HEAD_INITIALIZER(iql); 788 789 limit = budget ? budget : iq->qsize / 8; 790 791 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq)); 792 793 /* 794 * We always come back and check the descriptor ring for new indirect 795 * interrupts and other responses after running a single handler. 796 */ 797 for (;;) { 798 while (is_new_response(iq, &ctrl)) { 799 800 rmb(); 801 802 m0 = NULL; 803 rsp_type = G_RSPD_TYPE(ctrl->u.type_gen); 804 lq = be32toh(ctrl->pldbuflen_qid); 805 rss = (const void *)iq->cdesc; 806 807 switch (rsp_type) { 808 case X_RSPD_TYPE_FLBUF: 809 810 KASSERT(iq->flags & IQ_HAS_FL, 811 ("%s: data for an iq (%p) with no freelist", 812 __func__, iq)); 813 814 m0 = get_fl_payload(sc, fl, lq, &fl_bufs_used); 815 #ifdef T4_PKT_TIMESTAMP 816 /* 817 * 60 bit timestamp for the payload is 818 * *(uint64_t *)m0->m_pktdat. Note that it is 819 * in the leading free-space in the mbuf. The 820 * kernel can clobber it during a pullup, 821 * m_copymdata, etc. You need to make sure that 822 * the mbuf reaches you unmolested if you care 823 * about the timestamp. 824 */ 825 *(uint64_t *)m0->m_pktdat = 826 be64toh(ctrl->u.last_flit) & 827 0xfffffffffffffff; 828 #endif 829 830 /* fall through */ 831 832 case X_RSPD_TYPE_CPL: 833 KASSERT(rss->opcode < NUM_CPL_CMDS, 834 ("%s: bad opcode %02x.", __func__, 835 rss->opcode)); 836 sc->cpl_handler[rss->opcode](iq, rss, m0); 837 break; 838 839 case X_RSPD_TYPE_INTR: 840 841 /* 842 * Interrupts should be forwarded only to queues 843 * that are not forwarding their interrupts. 844 * This means service_iq can recurse but only 1 845 * level deep. 846 */ 847 KASSERT(budget == 0, 848 ("%s: budget %u, rsp_type %u", __func__, 849 budget, rsp_type)); 850 851 q = sc->sge.iqmap[lq - sc->sge.iq_start]; 852 if (atomic_cmpset_int(&q->state, IQS_IDLE, 853 IQS_BUSY)) { 854 if (service_iq(q, q->qsize / 8) == 0) { 855 atomic_cmpset_int(&q->state, 856 IQS_BUSY, IQS_IDLE); 857 } else { 858 STAILQ_INSERT_TAIL(&iql, q, 859 link); 860 } 861 } 862 break; 863 864 default: 865 panic("%s: rsp_type %u", __func__, rsp_type); 866 } 867 868 iq_next(iq); 869 if (++ndescs == limit) { 870 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), 871 V_CIDXINC(ndescs) | 872 V_INGRESSQID(iq->cntxt_id) | 873 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); 874 ndescs = 0; 875 876 if (fl_bufs_used > 0) { 877 FL_LOCK(fl); 878 fl->needed += fl_bufs_used; 879 refill_fl(sc, fl, fl->cap / 8); 880 FL_UNLOCK(fl); 881 fl_bufs_used = 0; 882 } 883 884 if (budget) 885 return (EINPROGRESS); 886 } 887 } 888 889 if (STAILQ_EMPTY(&iql)) 890 break; 891 892 /* 893 * Process the head only, and send it to the back of the list if 894 * it's still not done. 895 */ 896 q = STAILQ_FIRST(&iql); 897 STAILQ_REMOVE_HEAD(&iql, link); 898 if (service_iq(q, q->qsize / 8) == 0) 899 atomic_cmpset_int(&q->state, IQS_BUSY, IQS_IDLE); 900 else 901 STAILQ_INSERT_TAIL(&iql, q, link); 902 } 903 904 #ifdef INET 905 if (iq->flags & IQ_LRO_ENABLED) { 906 struct lro_ctrl *lro = &rxq->lro; 907 struct lro_entry *l; 908 909 while (!SLIST_EMPTY(&lro->lro_active)) { 910 l = SLIST_FIRST(&lro->lro_active); 911 SLIST_REMOVE_HEAD(&lro->lro_active, next); 912 tcp_lro_flush(lro, l); 913 } 914 } 915 #endif 916 917 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), V_CIDXINC(ndescs) | 918 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params)); 919 920 if (iq->flags & IQ_HAS_FL) { 921 int starved; 922 923 FL_LOCK(fl); 924 fl->needed += fl_bufs_used; 925 starved = refill_fl(sc, fl, fl->cap / 4); 926 FL_UNLOCK(fl); 927 if (__predict_false(starved != 0)) 928 add_fl_to_sfl(sc, fl); 929 } 930 931 return (0); 932 } 933 934 935 #ifdef T4_PKT_TIMESTAMP 936 #define RX_COPY_THRESHOLD (MINCLSIZE - 8) 937 #else 938 #define RX_COPY_THRESHOLD MINCLSIZE 939 #endif 940 941 static struct mbuf * 942 get_fl_payload(struct adapter *sc, struct sge_fl *fl, uint32_t len_newbuf, 943 int *fl_bufs_used) 944 { 945 struct mbuf *m0, *m; 946 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 947 unsigned int nbuf, len; 948 949 /* 950 * No assertion for the fl lock because we don't need it. This routine 951 * is called only from the rx interrupt handler and it only updates 952 * fl->cidx. (Contrast that with fl->pidx/fl->needed which could be 953 * updated in the rx interrupt handler or the starvation helper routine. 954 * That's why code that manipulates fl->pidx/fl->needed needs the fl 955 * lock but this routine does not). 956 */ 957 958 if (__predict_false((len_newbuf & F_RSPD_NEWBUF) == 0)) 959 panic("%s: cannot handle packed frames", __func__); 960 len = G_RSPD_LEN(len_newbuf); 961 962 m0 = sd->m; 963 sd->m = NULL; /* consumed */ 964 965 bus_dmamap_sync(fl->tag[sd->tag_idx], sd->map, BUS_DMASYNC_POSTREAD); 966 m_init(m0, NULL, 0, M_NOWAIT, MT_DATA, M_PKTHDR); 967 #ifdef T4_PKT_TIMESTAMP 968 /* Leave room for a timestamp */ 969 m0->m_data += 8; 970 #endif 971 972 if (len < RX_COPY_THRESHOLD) { 973 /* copy data to mbuf, buffer will be recycled */ 974 bcopy(sd->cl, mtod(m0, caddr_t), len); 975 m0->m_len = len; 976 } else { 977 bus_dmamap_unload(fl->tag[sd->tag_idx], sd->map); 978 m_cljset(m0, sd->cl, FL_BUF_TYPE(sd->tag_idx)); 979 sd->cl = NULL; /* consumed */ 980 m0->m_len = min(len, FL_BUF_SIZE(sd->tag_idx)); 981 } 982 m0->m_pkthdr.len = len; 983 984 sd++; 985 if (__predict_false(++fl->cidx == fl->cap)) { 986 sd = fl->sdesc; 987 fl->cidx = 0; 988 } 989 990 m = m0; 991 len -= m->m_len; 992 nbuf = 1; /* # of fl buffers used */ 993 994 while (len > 0) { 995 m->m_next = sd->m; 996 sd->m = NULL; /* consumed */ 997 m = m->m_next; 998 999 bus_dmamap_sync(fl->tag[sd->tag_idx], sd->map, 1000 BUS_DMASYNC_POSTREAD); 1001 1002 m_init(m, NULL, 0, M_NOWAIT, MT_DATA, 0); 1003 if (len <= MLEN) { 1004 bcopy(sd->cl, mtod(m, caddr_t), len); 1005 m->m_len = len; 1006 } else { 1007 bus_dmamap_unload(fl->tag[sd->tag_idx], 1008 sd->map); 1009 m_cljset(m, sd->cl, FL_BUF_TYPE(sd->tag_idx)); 1010 sd->cl = NULL; /* consumed */ 1011 m->m_len = min(len, FL_BUF_SIZE(sd->tag_idx)); 1012 } 1013 1014 sd++; 1015 if (__predict_false(++fl->cidx == fl->cap)) { 1016 sd = fl->sdesc; 1017 fl->cidx = 0; 1018 } 1019 1020 len -= m->m_len; 1021 nbuf++; 1022 } 1023 1024 (*fl_bufs_used) += nbuf; 1025 1026 return (m0); 1027 } 1028 1029 static int 1030 t4_eth_rx(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0) 1031 { 1032 struct sge_rxq *rxq = (void *)iq; 1033 struct ifnet *ifp = rxq->ifp; 1034 const struct cpl_rx_pkt *cpl = (const void *)(rss + 1); 1035 #ifdef INET 1036 struct lro_ctrl *lro = &rxq->lro; 1037 #endif 1038 1039 KASSERT(m0 != NULL, ("%s: no payload with opcode %02x", __func__, 1040 rss->opcode)); 1041 1042 m0->m_pkthdr.len -= FL_PKTSHIFT; 1043 m0->m_len -= FL_PKTSHIFT; 1044 m0->m_data += FL_PKTSHIFT; 1045 1046 m0->m_pkthdr.rcvif = ifp; 1047 m0->m_flags |= M_FLOWID; 1048 m0->m_pkthdr.flowid = rss->hash_val; 1049 1050 if (cpl->csum_calc && !cpl->err_vec && 1051 ifp->if_capenable & IFCAP_RXCSUM) { 1052 m0->m_pkthdr.csum_flags |= (CSUM_IP_CHECKED | 1053 CSUM_IP_VALID | CSUM_DATA_VALID | CSUM_PSEUDO_HDR); 1054 if (cpl->ip_frag) 1055 m0->m_pkthdr.csum_data = be16toh(cpl->csum); 1056 else 1057 m0->m_pkthdr.csum_data = 0xffff; 1058 rxq->rxcsum++; 1059 } 1060 1061 if (cpl->vlan_ex) { 1062 m0->m_pkthdr.ether_vtag = be16toh(cpl->vlan); 1063 m0->m_flags |= M_VLANTAG; 1064 rxq->vlan_extraction++; 1065 } 1066 1067 #ifdef INET 1068 if (cpl->l2info & htobe32(F_RXF_LRO) && 1069 iq->flags & IQ_LRO_ENABLED && 1070 tcp_lro_rx(lro, m0, 0) == 0) { 1071 /* queued for LRO */ 1072 } else 1073 #endif 1074 ifp->if_input(ifp, m0); 1075 1076 return (0); 1077 } 1078 1079 int 1080 t4_mgmt_tx(struct adapter *sc, struct mbuf *m) 1081 { 1082 return t4_wrq_tx(sc, &sc->sge.mgmtq, m); 1083 } 1084 1085 /* 1086 * Doesn't fail. Holds on to work requests it can't send right away. 1087 */ 1088 int 1089 t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, struct mbuf *m0) 1090 { 1091 struct sge_eq *eq = &wrq->eq; 1092 int can_reclaim; 1093 caddr_t dst; 1094 struct mbuf *wr, *next; 1095 1096 TXQ_LOCK_ASSERT_OWNED(wrq); 1097 KASSERT((eq->flags & EQ_TYPEMASK) == EQ_OFLD || 1098 (eq->flags & EQ_TYPEMASK) == EQ_CTRL, 1099 ("%s: eq type %d", __func__, eq->flags & EQ_TYPEMASK)); 1100 1101 if (__predict_true(m0 != NULL)) { 1102 if (wrq->head) 1103 wrq->tail->m_nextpkt = m0; 1104 else 1105 wrq->head = m0; 1106 while (m0->m_nextpkt) 1107 m0 = m0->m_nextpkt; 1108 wrq->tail = m0; 1109 } 1110 1111 can_reclaim = reclaimable(eq); 1112 if (__predict_false(eq->flags & EQ_STALLED)) { 1113 if (can_reclaim < tx_resume_threshold(eq)) 1114 return (0); 1115 eq->flags &= ~EQ_STALLED; 1116 eq->unstalled++; 1117 } 1118 eq->cidx += can_reclaim; 1119 eq->avail += can_reclaim; 1120 if (__predict_false(eq->cidx >= eq->cap)) 1121 eq->cidx -= eq->cap; 1122 1123 for (wr = wrq->head; wr; wr = next) { 1124 int ndesc; 1125 struct mbuf *m; 1126 1127 next = wr->m_nextpkt; 1128 wr->m_nextpkt = NULL; 1129 1130 M_ASSERTPKTHDR(wr); 1131 KASSERT(wr->m_pkthdr.len > 0 && (wr->m_pkthdr.len & 0x7) == 0, 1132 ("%s: work request len %d.", __func__, wr->m_pkthdr.len)); 1133 1134 if (wr->m_pkthdr.len > SGE_MAX_WR_LEN) { 1135 #ifdef INVARIANTS 1136 panic("%s: oversized work request", __func__); 1137 #else 1138 log(LOG_ERR, "%s: %s work request too long (%d)", 1139 device_get_nameunit(sc->dev), __func__, 1140 wr->m_pkthdr.len); 1141 m_freem(wr); 1142 continue; 1143 #endif 1144 } 1145 1146 ndesc = howmany(wr->m_pkthdr.len, EQ_ESIZE); 1147 if (eq->avail < ndesc) { 1148 wr->m_nextpkt = next; 1149 wrq->no_desc++; 1150 break; 1151 } 1152 1153 dst = (void *)&eq->desc[eq->pidx]; 1154 for (m = wr; m; m = m->m_next) 1155 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len); 1156 1157 eq->pidx += ndesc; 1158 eq->avail -= ndesc; 1159 if (__predict_false(eq->pidx >= eq->cap)) 1160 eq->pidx -= eq->cap; 1161 1162 eq->pending += ndesc; 1163 if (eq->pending > 16) 1164 ring_eq_db(sc, eq); 1165 1166 wrq->tx_wrs++; 1167 m_freem(wr); 1168 1169 if (eq->avail < 8) { 1170 can_reclaim = reclaimable(eq); 1171 eq->cidx += can_reclaim; 1172 eq->avail += can_reclaim; 1173 if (__predict_false(eq->cidx >= eq->cap)) 1174 eq->cidx -= eq->cap; 1175 } 1176 } 1177 1178 if (eq->pending) 1179 ring_eq_db(sc, eq); 1180 1181 if (wr == NULL) 1182 wrq->head = wrq->tail = NULL; 1183 else { 1184 wrq->head = wr; 1185 1186 KASSERT(wrq->tail->m_nextpkt == NULL, 1187 ("%s: wrq->tail grew a tail of its own", __func__)); 1188 1189 eq->flags |= EQ_STALLED; 1190 if (callout_pending(&eq->tx_callout) == 0) 1191 callout_reset(&eq->tx_callout, 1, t4_tx_callout, eq); 1192 } 1193 1194 return (0); 1195 } 1196 1197 /* Per-packet header in a coalesced tx WR, before the SGL starts (in flits) */ 1198 #define TXPKTS_PKT_HDR ((\ 1199 sizeof(struct ulp_txpkt) + \ 1200 sizeof(struct ulptx_idata) + \ 1201 sizeof(struct cpl_tx_pkt_core) \ 1202 ) / 8) 1203 1204 /* Header of a coalesced tx WR, before SGL of first packet (in flits) */ 1205 #define TXPKTS_WR_HDR (\ 1206 sizeof(struct fw_eth_tx_pkts_wr) / 8 + \ 1207 TXPKTS_PKT_HDR) 1208 1209 /* Header of a tx WR, before SGL of first packet (in flits) */ 1210 #define TXPKT_WR_HDR ((\ 1211 sizeof(struct fw_eth_tx_pkt_wr) + \ 1212 sizeof(struct cpl_tx_pkt_core) \ 1213 ) / 8 ) 1214 1215 /* Header of a tx LSO WR, before SGL of first packet (in flits) */ 1216 #define TXPKT_LSO_WR_HDR ((\ 1217 sizeof(struct fw_eth_tx_pkt_wr) + \ 1218 sizeof(struct cpl_tx_pkt_lso) + \ 1219 sizeof(struct cpl_tx_pkt_core) \ 1220 ) / 8 ) 1221 1222 int 1223 t4_eth_tx(struct ifnet *ifp, struct sge_txq *txq, struct mbuf *m) 1224 { 1225 struct port_info *pi = (void *)ifp->if_softc; 1226 struct adapter *sc = pi->adapter; 1227 struct sge_eq *eq = &txq->eq; 1228 struct buf_ring *br = txq->br; 1229 struct mbuf *next; 1230 int rc, coalescing, can_reclaim; 1231 struct txpkts txpkts; 1232 struct sgl sgl; 1233 1234 TXQ_LOCK_ASSERT_OWNED(txq); 1235 KASSERT(m, ("%s: called with nothing to do.", __func__)); 1236 KASSERT((eq->flags & EQ_TYPEMASK) == EQ_ETH, 1237 ("%s: eq type %d", __func__, eq->flags & EQ_TYPEMASK)); 1238 1239 prefetch(&eq->desc[eq->pidx]); 1240 prefetch(&txq->sdesc[eq->pidx]); 1241 1242 txpkts.npkt = 0;/* indicates there's nothing in txpkts */ 1243 coalescing = 0; 1244 1245 can_reclaim = reclaimable(eq); 1246 if (__predict_false(eq->flags & EQ_STALLED)) { 1247 if (can_reclaim < tx_resume_threshold(eq)) { 1248 txq->m = m; 1249 return (0); 1250 } 1251 eq->flags &= ~EQ_STALLED; 1252 eq->unstalled++; 1253 } 1254 1255 if (__predict_false(eq->flags & EQ_DOOMED)) { 1256 m_freem(m); 1257 while ((m = buf_ring_dequeue_sc(txq->br)) != NULL) 1258 m_freem(m); 1259 return (ENETDOWN); 1260 } 1261 1262 if (eq->avail < 8 && can_reclaim) 1263 reclaim_tx_descs(txq, can_reclaim, 32); 1264 1265 for (; m; m = next ? next : drbr_dequeue(ifp, br)) { 1266 1267 if (eq->avail < 8) 1268 break; 1269 1270 next = m->m_nextpkt; 1271 m->m_nextpkt = NULL; 1272 1273 if (next || buf_ring_peek(br)) 1274 coalescing = 1; 1275 1276 rc = get_pkt_sgl(txq, &m, &sgl, coalescing); 1277 if (rc != 0) { 1278 if (rc == ENOMEM) { 1279 1280 /* Short of resources, suspend tx */ 1281 1282 m->m_nextpkt = next; 1283 break; 1284 } 1285 1286 /* 1287 * Unrecoverable error for this packet, throw it away 1288 * and move on to the next. get_pkt_sgl may already 1289 * have freed m (it will be NULL in that case and the 1290 * m_freem here is still safe). 1291 */ 1292 1293 m_freem(m); 1294 continue; 1295 } 1296 1297 if (coalescing && 1298 add_to_txpkts(pi, txq, &txpkts, m, &sgl) == 0) { 1299 1300 /* Successfully absorbed into txpkts */ 1301 1302 write_ulp_cpl_sgl(pi, txq, &txpkts, m, &sgl); 1303 goto doorbell; 1304 } 1305 1306 /* 1307 * We weren't coalescing to begin with, or current frame could 1308 * not be coalesced (add_to_txpkts flushes txpkts if a frame 1309 * given to it can't be coalesced). Either way there should be 1310 * nothing in txpkts. 1311 */ 1312 KASSERT(txpkts.npkt == 0, 1313 ("%s: txpkts not empty: %d", __func__, txpkts.npkt)); 1314 1315 /* We're sending out individual packets now */ 1316 coalescing = 0; 1317 1318 if (eq->avail < 8) 1319 reclaim_tx_descs(txq, 0, 8); 1320 rc = write_txpkt_wr(pi, txq, m, &sgl); 1321 if (rc != 0) { 1322 1323 /* Short of hardware descriptors, suspend tx */ 1324 1325 /* 1326 * This is an unlikely but expensive failure. We've 1327 * done all the hard work (DMA mappings etc.) and now we 1328 * can't send out the packet. What's worse, we have to 1329 * spend even more time freeing up everything in sgl. 1330 */ 1331 txq->no_desc++; 1332 free_pkt_sgl(txq, &sgl); 1333 1334 m->m_nextpkt = next; 1335 break; 1336 } 1337 1338 ETHER_BPF_MTAP(ifp, m); 1339 if (sgl.nsegs == 0) 1340 m_freem(m); 1341 doorbell: 1342 if (eq->pending >= 64) 1343 ring_eq_db(sc, eq); 1344 1345 can_reclaim = reclaimable(eq); 1346 if (can_reclaim >= 32) 1347 reclaim_tx_descs(txq, can_reclaim, 64); 1348 } 1349 1350 if (txpkts.npkt > 0) 1351 write_txpkts_wr(txq, &txpkts); 1352 1353 /* 1354 * m not NULL means there was an error but we haven't thrown it away. 1355 * This can happen when we're short of tx descriptors (no_desc) or maybe 1356 * even DMA maps (no_dmamap). Either way, a credit flush and reclaim 1357 * will get things going again. 1358 */ 1359 if (m && !(eq->flags & EQ_CRFLUSHED)) { 1360 struct tx_sdesc *txsd = &txq->sdesc[eq->pidx]; 1361 1362 /* 1363 * If EQ_CRFLUSHED is not set then we know we have at least one 1364 * available descriptor because any WR that reduces eq->avail to 1365 * 0 also sets EQ_CRFLUSHED. 1366 */ 1367 KASSERT(eq->avail > 0, ("%s: no space for eqflush.", __func__)); 1368 1369 txsd->desc_used = 1; 1370 txsd->credits = 0; 1371 write_eqflush_wr(eq); 1372 } 1373 txq->m = m; 1374 1375 if (eq->pending) 1376 ring_eq_db(sc, eq); 1377 1378 reclaim_tx_descs(txq, 0, 128); 1379 1380 if (eq->flags & EQ_STALLED && callout_pending(&eq->tx_callout) == 0) 1381 callout_reset(&eq->tx_callout, 1, t4_tx_callout, eq); 1382 1383 return (0); 1384 } 1385 1386 void 1387 t4_update_fl_bufsize(struct ifnet *ifp) 1388 { 1389 struct port_info *pi = ifp->if_softc; 1390 struct sge_rxq *rxq; 1391 struct sge_fl *fl; 1392 int i, bufsize; 1393 1394 /* large enough for a frame even when VLAN extraction is disabled */ 1395 bufsize = FL_PKTSHIFT + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 1396 ifp->if_mtu; 1397 for_each_rxq(pi, i, rxq) { 1398 fl = &rxq->fl; 1399 1400 FL_LOCK(fl); 1401 set_fl_tag_idx(fl, bufsize); 1402 FL_UNLOCK(fl); 1403 } 1404 } 1405 1406 int 1407 can_resume_tx(struct sge_eq *eq) 1408 { 1409 return (reclaimable(eq) >= tx_resume_threshold(eq)); 1410 } 1411 1412 static inline void 1413 init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int pktc_idx, 1414 int qsize, int esize, char *name) 1415 { 1416 KASSERT(tmr_idx >= 0 && tmr_idx < SGE_NTIMERS, 1417 ("%s: bad tmr_idx %d", __func__, tmr_idx)); 1418 KASSERT(pktc_idx < SGE_NCOUNTERS, /* -ve is ok, means don't use */ 1419 ("%s: bad pktc_idx %d", __func__, pktc_idx)); 1420 1421 iq->flags = 0; 1422 iq->adapter = sc; 1423 iq->intr_params = V_QINTR_TIMER_IDX(tmr_idx) | 1424 V_QINTR_CNT_EN(pktc_idx >= 0); 1425 iq->intr_pktc_idx = pktc_idx; 1426 iq->qsize = roundup(qsize, 16); /* See FW_IQ_CMD/iqsize */ 1427 iq->esize = max(esize, 16); /* See FW_IQ_CMD/iqesize */ 1428 strlcpy(iq->lockname, name, sizeof(iq->lockname)); 1429 } 1430 1431 static inline void 1432 init_fl(struct sge_fl *fl, int qsize, int bufsize, char *name) 1433 { 1434 fl->qsize = qsize; 1435 strlcpy(fl->lockname, name, sizeof(fl->lockname)); 1436 set_fl_tag_idx(fl, bufsize); 1437 } 1438 1439 static inline void 1440 init_eq(struct sge_eq *eq, int eqtype, int qsize, uint8_t tx_chan, 1441 uint16_t iqid, char *name) 1442 { 1443 KASSERT(tx_chan < NCHAN, ("%s: bad tx channel %d", __func__, tx_chan)); 1444 KASSERT(eqtype <= EQ_TYPEMASK, ("%s: bad qtype %d", __func__, eqtype)); 1445 1446 eq->flags = eqtype & EQ_TYPEMASK; 1447 eq->tx_chan = tx_chan; 1448 eq->iqid = iqid; 1449 eq->qsize = qsize; 1450 strlcpy(eq->lockname, name, sizeof(eq->lockname)); 1451 1452 TASK_INIT(&eq->tx_task, 0, t4_tx_task, eq); 1453 callout_init(&eq->tx_callout, CALLOUT_MPSAFE); 1454 } 1455 1456 static int 1457 alloc_ring(struct adapter *sc, size_t len, bus_dma_tag_t *tag, 1458 bus_dmamap_t *map, bus_addr_t *pa, void **va) 1459 { 1460 int rc; 1461 1462 rc = bus_dma_tag_create(sc->dmat, 512, 0, BUS_SPACE_MAXADDR, 1463 BUS_SPACE_MAXADDR, NULL, NULL, len, 1, len, 0, NULL, NULL, tag); 1464 if (rc != 0) { 1465 device_printf(sc->dev, "cannot allocate DMA tag: %d\n", rc); 1466 goto done; 1467 } 1468 1469 rc = bus_dmamem_alloc(*tag, va, 1470 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, map); 1471 if (rc != 0) { 1472 device_printf(sc->dev, "cannot allocate DMA memory: %d\n", rc); 1473 goto done; 1474 } 1475 1476 rc = bus_dmamap_load(*tag, *map, *va, len, oneseg_dma_callback, pa, 0); 1477 if (rc != 0) { 1478 device_printf(sc->dev, "cannot load DMA map: %d\n", rc); 1479 goto done; 1480 } 1481 done: 1482 if (rc) 1483 free_ring(sc, *tag, *map, *pa, *va); 1484 1485 return (rc); 1486 } 1487 1488 static int 1489 free_ring(struct adapter *sc, bus_dma_tag_t tag, bus_dmamap_t map, 1490 bus_addr_t pa, void *va) 1491 { 1492 if (pa) 1493 bus_dmamap_unload(tag, map); 1494 if (va) 1495 bus_dmamem_free(tag, va, map); 1496 if (tag) 1497 bus_dma_tag_destroy(tag); 1498 1499 return (0); 1500 } 1501 1502 /* 1503 * Allocates the ring for an ingress queue and an optional freelist. If the 1504 * freelist is specified it will be allocated and then associated with the 1505 * ingress queue. 1506 * 1507 * Returns errno on failure. Resources allocated up to that point may still be 1508 * allocated. Caller is responsible for cleanup in case this function fails. 1509 * 1510 * If the ingress queue will take interrupts directly (iq->flags & IQ_INTR) then 1511 * the intr_idx specifies the vector, starting from 0. Otherwise it specifies 1512 * the abs_id of the ingress queue to which its interrupts should be forwarded. 1513 */ 1514 static int 1515 alloc_iq_fl(struct port_info *pi, struct sge_iq *iq, struct sge_fl *fl, 1516 int intr_idx, int cong) 1517 { 1518 int rc, i, cntxt_id; 1519 size_t len; 1520 struct fw_iq_cmd c; 1521 struct adapter *sc = iq->adapter; 1522 __be32 v = 0; 1523 1524 len = iq->qsize * iq->esize; 1525 rc = alloc_ring(sc, len, &iq->desc_tag, &iq->desc_map, &iq->ba, 1526 (void **)&iq->desc); 1527 if (rc != 0) 1528 return (rc); 1529 1530 bzero(&c, sizeof(c)); 1531 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 1532 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) | 1533 V_FW_IQ_CMD_VFN(0)); 1534 1535 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART | 1536 FW_LEN16(c)); 1537 1538 /* Special handling for firmware event queue */ 1539 if (iq == &sc->sge.fwq) 1540 v |= F_FW_IQ_CMD_IQASYNCH; 1541 1542 if (iq->flags & IQ_INTR) { 1543 KASSERT(intr_idx < sc->intr_count, 1544 ("%s: invalid direct intr_idx %d", __func__, intr_idx)); 1545 } else 1546 v |= F_FW_IQ_CMD_IQANDST; 1547 v |= V_FW_IQ_CMD_IQANDSTINDEX(intr_idx); 1548 1549 c.type_to_iqandstindex = htobe32(v | 1550 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) | 1551 V_FW_IQ_CMD_VIID(pi->viid) | 1552 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT)); 1553 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->tx_chan) | 1554 F_FW_IQ_CMD_IQGTSMODE | 1555 V_FW_IQ_CMD_IQINTCNTTHRESH(iq->intr_pktc_idx) | 1556 V_FW_IQ_CMD_IQESIZE(ilog2(iq->esize) - 4)); 1557 c.iqsize = htobe16(iq->qsize); 1558 c.iqaddr = htobe64(iq->ba); 1559 if (cong >= 0) 1560 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN); 1561 1562 if (fl) { 1563 mtx_init(&fl->fl_lock, fl->lockname, NULL, MTX_DEF); 1564 1565 for (i = 0; i < FL_BUF_SIZES; i++) { 1566 1567 /* 1568 * A freelist buffer must be 16 byte aligned as the SGE 1569 * uses the low 4 bits of the bus addr to figure out the 1570 * buffer size. 1571 */ 1572 rc = bus_dma_tag_create(sc->dmat, 16, 0, 1573 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1574 FL_BUF_SIZE(i), 1, FL_BUF_SIZE(i), BUS_DMA_ALLOCNOW, 1575 NULL, NULL, &fl->tag[i]); 1576 if (rc != 0) { 1577 device_printf(sc->dev, 1578 "failed to create fl DMA tag[%d]: %d\n", 1579 i, rc); 1580 return (rc); 1581 } 1582 } 1583 len = fl->qsize * RX_FL_ESIZE; 1584 rc = alloc_ring(sc, len, &fl->desc_tag, &fl->desc_map, 1585 &fl->ba, (void **)&fl->desc); 1586 if (rc) 1587 return (rc); 1588 1589 /* Allocate space for one software descriptor per buffer. */ 1590 fl->cap = (fl->qsize - SPG_LEN / RX_FL_ESIZE) * 8; 1591 FL_LOCK(fl); 1592 rc = alloc_fl_sdesc(fl); 1593 FL_UNLOCK(fl); 1594 if (rc != 0) { 1595 device_printf(sc->dev, 1596 "failed to setup fl software descriptors: %d\n", 1597 rc); 1598 return (rc); 1599 } 1600 fl->needed = fl->cap; 1601 fl->lowat = roundup(sc->sge.fl_starve_threshold, 8); 1602 1603 c.iqns_to_fl0congen |= 1604 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) | 1605 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO | 1606 F_FW_IQ_CMD_FL0PADEN); 1607 if (cong >= 0) { 1608 c.iqns_to_fl0congen |= 1609 htobe32(V_FW_IQ_CMD_FL0CNGCHMAP(cong) | 1610 F_FW_IQ_CMD_FL0CONGCIF | 1611 F_FW_IQ_CMD_FL0CONGEN); 1612 } 1613 c.fl0dcaen_to_fl0cidxfthresh = 1614 htobe16(V_FW_IQ_CMD_FL0FBMIN(X_FETCHBURSTMIN_64B) | 1615 V_FW_IQ_CMD_FL0FBMAX(X_FETCHBURSTMAX_512B)); 1616 c.fl0size = htobe16(fl->qsize); 1617 c.fl0addr = htobe64(fl->ba); 1618 } 1619 1620 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 1621 if (rc != 0) { 1622 device_printf(sc->dev, 1623 "failed to create ingress queue: %d\n", rc); 1624 return (rc); 1625 } 1626 1627 iq->cdesc = iq->desc; 1628 iq->cidx = 0; 1629 iq->gen = 1; 1630 iq->intr_next = iq->intr_params; 1631 iq->cntxt_id = be16toh(c.iqid); 1632 iq->abs_id = be16toh(c.physiqid); 1633 iq->flags |= IQ_ALLOCATED; 1634 1635 cntxt_id = iq->cntxt_id - sc->sge.iq_start; 1636 if (cntxt_id >= sc->sge.niq) { 1637 panic ("%s: iq->cntxt_id (%d) more than the max (%d)", __func__, 1638 cntxt_id, sc->sge.niq - 1); 1639 } 1640 sc->sge.iqmap[cntxt_id] = iq; 1641 1642 if (fl) { 1643 fl->cntxt_id = be16toh(c.fl0id); 1644 fl->pidx = fl->cidx = 0; 1645 1646 cntxt_id = fl->cntxt_id - sc->sge.eq_start; 1647 if (cntxt_id >= sc->sge.neq) { 1648 panic("%s: fl->cntxt_id (%d) more than the max (%d)", 1649 __func__, cntxt_id, sc->sge.neq - 1); 1650 } 1651 sc->sge.eqmap[cntxt_id] = (void *)fl; 1652 1653 FL_LOCK(fl); 1654 /* Enough to make sure the SGE doesn't think it's starved */ 1655 refill_fl(sc, fl, fl->lowat); 1656 FL_UNLOCK(fl); 1657 1658 iq->flags |= IQ_HAS_FL; 1659 } 1660 1661 /* Enable IQ interrupts */ 1662 atomic_store_rel_int(&iq->state, IQS_IDLE); 1663 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), V_SEINTARM(iq->intr_params) | 1664 V_INGRESSQID(iq->cntxt_id)); 1665 1666 return (0); 1667 } 1668 1669 static int 1670 free_iq_fl(struct port_info *pi, struct sge_iq *iq, struct sge_fl *fl) 1671 { 1672 int i, rc; 1673 struct adapter *sc = iq->adapter; 1674 device_t dev; 1675 1676 if (sc == NULL) 1677 return (0); /* nothing to do */ 1678 1679 dev = pi ? pi->dev : sc->dev; 1680 1681 if (iq->flags & IQ_ALLOCATED) { 1682 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0, 1683 FW_IQ_TYPE_FL_INT_CAP, iq->cntxt_id, 1684 fl ? fl->cntxt_id : 0xffff, 0xffff); 1685 if (rc != 0) { 1686 device_printf(dev, 1687 "failed to free queue %p: %d\n", iq, rc); 1688 return (rc); 1689 } 1690 iq->flags &= ~IQ_ALLOCATED; 1691 } 1692 1693 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, iq->desc); 1694 1695 bzero(iq, sizeof(*iq)); 1696 1697 if (fl) { 1698 free_ring(sc, fl->desc_tag, fl->desc_map, fl->ba, 1699 fl->desc); 1700 1701 if (fl->sdesc) { 1702 FL_LOCK(fl); 1703 free_fl_sdesc(fl); 1704 FL_UNLOCK(fl); 1705 } 1706 1707 if (mtx_initialized(&fl->fl_lock)) 1708 mtx_destroy(&fl->fl_lock); 1709 1710 for (i = 0; i < FL_BUF_SIZES; i++) { 1711 if (fl->tag[i]) 1712 bus_dma_tag_destroy(fl->tag[i]); 1713 } 1714 1715 bzero(fl, sizeof(*fl)); 1716 } 1717 1718 return (0); 1719 } 1720 1721 static int 1722 alloc_fwq(struct adapter *sc) 1723 { 1724 int rc, intr_idx; 1725 struct sge_iq *fwq = &sc->sge.fwq; 1726 char name[16]; 1727 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev); 1728 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 1729 1730 snprintf(name, sizeof(name), "%s fwq", device_get_nameunit(sc->dev)); 1731 init_iq(fwq, sc, 0, 0, FW_IQ_QSIZE, FW_IQ_ESIZE, name); 1732 fwq->flags |= IQ_INTR; /* always */ 1733 intr_idx = sc->intr_count > 1 ? 1 : 0; 1734 rc = alloc_iq_fl(sc->port[0], fwq, NULL, intr_idx, -1); 1735 if (rc != 0) { 1736 device_printf(sc->dev, 1737 "failed to create firmware event queue: %d\n", rc); 1738 return (rc); 1739 } 1740 1741 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "fwq", CTLFLAG_RD, 1742 NULL, "firmware event queue"); 1743 children = SYSCTL_CHILDREN(oid); 1744 1745 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "abs_id", 1746 CTLTYPE_INT | CTLFLAG_RD, &fwq->abs_id, 0, sysctl_uint16, "I", 1747 "absolute id of the queue"); 1748 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "cntxt_id", 1749 CTLTYPE_INT | CTLFLAG_RD, &fwq->cntxt_id, 0, sysctl_uint16, "I", 1750 "SGE context id of the queue"); 1751 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "cidx", 1752 CTLTYPE_INT | CTLFLAG_RD, &fwq->cidx, 0, sysctl_uint16, "I", 1753 "consumer index"); 1754 1755 return (0); 1756 } 1757 1758 static int 1759 free_fwq(struct adapter *sc) 1760 { 1761 return free_iq_fl(NULL, &sc->sge.fwq, NULL); 1762 } 1763 1764 static int 1765 alloc_mgmtq(struct adapter *sc) 1766 { 1767 int rc; 1768 struct sge_wrq *mgmtq = &sc->sge.mgmtq; 1769 char name[16]; 1770 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev); 1771 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 1772 1773 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "mgmtq", CTLFLAG_RD, 1774 NULL, "management queue"); 1775 1776 snprintf(name, sizeof(name), "%s mgmtq", device_get_nameunit(sc->dev)); 1777 init_eq(&mgmtq->eq, EQ_CTRL, CTRL_EQ_QSIZE, sc->port[0]->tx_chan, 1778 sc->sge.fwq.cntxt_id, name); 1779 rc = alloc_wrq(sc, NULL, mgmtq, oid); 1780 if (rc != 0) { 1781 device_printf(sc->dev, 1782 "failed to create management queue: %d\n", rc); 1783 return (rc); 1784 } 1785 1786 return (0); 1787 } 1788 1789 static int 1790 free_mgmtq(struct adapter *sc) 1791 { 1792 return free_wrq(sc, &sc->sge.mgmtq); 1793 } 1794 1795 static int 1796 alloc_rxq(struct port_info *pi, struct sge_rxq *rxq, int intr_idx, int idx, 1797 struct sysctl_oid *oid) 1798 { 1799 int rc; 1800 struct sysctl_oid_list *children; 1801 char name[16]; 1802 1803 rc = alloc_iq_fl(pi, &rxq->iq, &rxq->fl, intr_idx, 1 << pi->tx_chan); 1804 if (rc != 0) 1805 return (rc); 1806 1807 FL_LOCK(&rxq->fl); 1808 refill_fl(pi->adapter, &rxq->fl, rxq->fl.needed / 8); 1809 FL_UNLOCK(&rxq->fl); 1810 1811 #ifdef INET 1812 rc = tcp_lro_init(&rxq->lro); 1813 if (rc != 0) 1814 return (rc); 1815 rxq->lro.ifp = pi->ifp; /* also indicates LRO init'ed */ 1816 1817 if (pi->ifp->if_capenable & IFCAP_LRO) 1818 rxq->iq.flags |= IQ_LRO_ENABLED; 1819 #endif 1820 rxq->ifp = pi->ifp; 1821 1822 children = SYSCTL_CHILDREN(oid); 1823 1824 snprintf(name, sizeof(name), "%d", idx); 1825 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 1826 NULL, "rx queue"); 1827 children = SYSCTL_CHILDREN(oid); 1828 1829 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "abs_id", 1830 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.abs_id, 0, sysctl_uint16, "I", 1831 "absolute id of the queue"); 1832 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cntxt_id", 1833 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.cntxt_id, 0, sysctl_uint16, "I", 1834 "SGE context id of the queue"); 1835 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cidx", 1836 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.cidx, 0, sysctl_uint16, "I", 1837 "consumer index"); 1838 #ifdef INET 1839 SYSCTL_ADD_INT(&pi->ctx, children, OID_AUTO, "lro_queued", CTLFLAG_RD, 1840 &rxq->lro.lro_queued, 0, NULL); 1841 SYSCTL_ADD_INT(&pi->ctx, children, OID_AUTO, "lro_flushed", CTLFLAG_RD, 1842 &rxq->lro.lro_flushed, 0, NULL); 1843 #endif 1844 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "rxcsum", CTLFLAG_RD, 1845 &rxq->rxcsum, "# of times hardware assisted with checksum"); 1846 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "vlan_extraction", 1847 CTLFLAG_RD, &rxq->vlan_extraction, 1848 "# of times hardware extracted 802.1Q tag"); 1849 1850 children = SYSCTL_CHILDREN(oid); 1851 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "fl", CTLFLAG_RD, 1852 NULL, "freelist"); 1853 children = SYSCTL_CHILDREN(oid); 1854 1855 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cntxt_id", 1856 CTLTYPE_INT | CTLFLAG_RD, &rxq->fl.cntxt_id, 0, sysctl_uint16, "I", 1857 "SGE context id of the queue"); 1858 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, 1859 &rxq->fl.cidx, 0, "consumer index"); 1860 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, 1861 &rxq->fl.pidx, 0, "producer index"); 1862 1863 return (rc); 1864 } 1865 1866 static int 1867 free_rxq(struct port_info *pi, struct sge_rxq *rxq) 1868 { 1869 int rc; 1870 1871 #ifdef INET 1872 if (rxq->lro.ifp) { 1873 tcp_lro_free(&rxq->lro); 1874 rxq->lro.ifp = NULL; 1875 } 1876 #endif 1877 1878 rc = free_iq_fl(pi, &rxq->iq, &rxq->fl); 1879 if (rc == 0) 1880 bzero(rxq, sizeof(*rxq)); 1881 1882 return (rc); 1883 } 1884 1885 #ifndef TCP_OFFLOAD_DISABLE 1886 static int 1887 alloc_ofld_rxq(struct port_info *pi, struct sge_ofld_rxq *ofld_rxq, 1888 int intr_idx, int idx, struct sysctl_oid *oid) 1889 { 1890 int rc; 1891 struct sysctl_oid_list *children; 1892 char name[16]; 1893 1894 rc = alloc_iq_fl(pi, &ofld_rxq->iq, &ofld_rxq->fl, intr_idx, 1895 1 << pi->tx_chan); 1896 if (rc != 0) 1897 return (rc); 1898 1899 children = SYSCTL_CHILDREN(oid); 1900 1901 snprintf(name, sizeof(name), "%d", idx); 1902 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 1903 NULL, "rx queue"); 1904 children = SYSCTL_CHILDREN(oid); 1905 1906 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "abs_id", 1907 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.abs_id, 0, sysctl_uint16, 1908 "I", "absolute id of the queue"); 1909 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cntxt_id", 1910 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.cntxt_id, 0, sysctl_uint16, 1911 "I", "SGE context id of the queue"); 1912 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cidx", 1913 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.cidx, 0, sysctl_uint16, "I", 1914 "consumer index"); 1915 1916 children = SYSCTL_CHILDREN(oid); 1917 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "fl", CTLFLAG_RD, 1918 NULL, "freelist"); 1919 children = SYSCTL_CHILDREN(oid); 1920 1921 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cntxt_id", 1922 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->fl.cntxt_id, 0, sysctl_uint16, 1923 "I", "SGE context id of the queue"); 1924 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, 1925 &ofld_rxq->fl.cidx, 0, "consumer index"); 1926 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, 1927 &ofld_rxq->fl.pidx, 0, "producer index"); 1928 1929 return (rc); 1930 } 1931 1932 static int 1933 free_ofld_rxq(struct port_info *pi, struct sge_ofld_rxq *ofld_rxq) 1934 { 1935 int rc; 1936 1937 rc = free_iq_fl(pi, &ofld_rxq->iq, &ofld_rxq->fl); 1938 if (rc == 0) 1939 bzero(ofld_rxq, sizeof(*ofld_rxq)); 1940 1941 return (rc); 1942 } 1943 #endif 1944 1945 static int 1946 ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq) 1947 { 1948 int rc, cntxt_id; 1949 struct fw_eq_ctrl_cmd c; 1950 1951 bzero(&c, sizeof(c)); 1952 1953 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | F_FW_CMD_REQUEST | 1954 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_CTRL_CMD_PFN(sc->pf) | 1955 V_FW_EQ_CTRL_CMD_VFN(0)); 1956 c.alloc_to_len16 = htobe32(F_FW_EQ_CTRL_CMD_ALLOC | 1957 F_FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c)); 1958 c.cmpliqid_eqid = htonl(V_FW_EQ_CTRL_CMD_CMPLIQID(eq->iqid)); /* XXX */ 1959 c.physeqid_pkd = htobe32(0); 1960 c.fetchszm_to_iqid = 1961 htobe32(V_FW_EQ_CTRL_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 1962 V_FW_EQ_CTRL_CMD_PCIECHN(eq->tx_chan) | 1963 F_FW_EQ_CTRL_CMD_FETCHRO | V_FW_EQ_CTRL_CMD_IQID(eq->iqid)); 1964 c.dcaen_to_eqsize = 1965 htobe32(V_FW_EQ_CTRL_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 1966 V_FW_EQ_CTRL_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 1967 V_FW_EQ_CTRL_CMD_CIDXFTHRESH(X_CIDXFLUSHTHRESH_32) | 1968 V_FW_EQ_CTRL_CMD_EQSIZE(eq->qsize)); 1969 c.eqaddr = htobe64(eq->ba); 1970 1971 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 1972 if (rc != 0) { 1973 device_printf(sc->dev, 1974 "failed to create control queue %d: %d\n", eq->tx_chan, rc); 1975 return (rc); 1976 } 1977 eq->flags |= EQ_ALLOCATED; 1978 1979 eq->cntxt_id = G_FW_EQ_CTRL_CMD_EQID(be32toh(c.cmpliqid_eqid)); 1980 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 1981 if (cntxt_id >= sc->sge.neq) 1982 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 1983 cntxt_id, sc->sge.neq - 1); 1984 sc->sge.eqmap[cntxt_id] = eq; 1985 1986 return (rc); 1987 } 1988 1989 static int 1990 eth_eq_alloc(struct adapter *sc, struct port_info *pi, struct sge_eq *eq) 1991 { 1992 int rc, cntxt_id; 1993 struct fw_eq_eth_cmd c; 1994 1995 bzero(&c, sizeof(c)); 1996 1997 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST | 1998 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) | 1999 V_FW_EQ_ETH_CMD_VFN(0)); 2000 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC | 2001 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c)); 2002 c.viid_pkd = htobe32(V_FW_EQ_ETH_CMD_VIID(pi->viid)); 2003 c.fetchszm_to_iqid = 2004 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 2005 V_FW_EQ_ETH_CMD_PCIECHN(eq->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO | 2006 V_FW_EQ_ETH_CMD_IQID(eq->iqid)); 2007 c.dcaen_to_eqsize = htobe32(V_FW_EQ_ETH_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 2008 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 2009 V_FW_EQ_ETH_CMD_CIDXFTHRESH(X_CIDXFLUSHTHRESH_32) | 2010 V_FW_EQ_ETH_CMD_EQSIZE(eq->qsize)); 2011 c.eqaddr = htobe64(eq->ba); 2012 2013 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 2014 if (rc != 0) { 2015 device_printf(pi->dev, 2016 "failed to create Ethernet egress queue: %d\n", rc); 2017 return (rc); 2018 } 2019 eq->flags |= EQ_ALLOCATED; 2020 2021 eq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd)); 2022 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 2023 if (cntxt_id >= sc->sge.neq) 2024 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 2025 cntxt_id, sc->sge.neq - 1); 2026 sc->sge.eqmap[cntxt_id] = eq; 2027 2028 return (rc); 2029 } 2030 2031 #ifndef TCP_OFFLOAD_DISABLE 2032 static int 2033 ofld_eq_alloc(struct adapter *sc, struct port_info *pi, struct sge_eq *eq) 2034 { 2035 int rc, cntxt_id; 2036 struct fw_eq_ofld_cmd c; 2037 2038 bzero(&c, sizeof(c)); 2039 2040 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | F_FW_CMD_REQUEST | 2041 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_OFLD_CMD_PFN(sc->pf) | 2042 V_FW_EQ_OFLD_CMD_VFN(0)); 2043 c.alloc_to_len16 = htonl(F_FW_EQ_OFLD_CMD_ALLOC | 2044 F_FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c)); 2045 c.fetchszm_to_iqid = 2046 htonl(V_FW_EQ_OFLD_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 2047 V_FW_EQ_OFLD_CMD_PCIECHN(eq->tx_chan) | 2048 F_FW_EQ_OFLD_CMD_FETCHRO | V_FW_EQ_OFLD_CMD_IQID(eq->iqid)); 2049 c.dcaen_to_eqsize = 2050 htobe32(V_FW_EQ_OFLD_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 2051 V_FW_EQ_OFLD_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 2052 V_FW_EQ_OFLD_CMD_CIDXFTHRESH(X_CIDXFLUSHTHRESH_32) | 2053 V_FW_EQ_OFLD_CMD_EQSIZE(eq->qsize)); 2054 c.eqaddr = htobe64(eq->ba); 2055 2056 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 2057 if (rc != 0) { 2058 device_printf(pi->dev, 2059 "failed to create egress queue for TCP offload: %d\n", rc); 2060 return (rc); 2061 } 2062 eq->flags |= EQ_ALLOCATED; 2063 2064 eq->cntxt_id = G_FW_EQ_OFLD_CMD_EQID(be32toh(c.eqid_pkd)); 2065 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 2066 if (cntxt_id >= sc->sge.neq) 2067 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 2068 cntxt_id, sc->sge.neq - 1); 2069 sc->sge.eqmap[cntxt_id] = eq; 2070 2071 return (rc); 2072 } 2073 #endif 2074 2075 static int 2076 alloc_eq(struct adapter *sc, struct port_info *pi, struct sge_eq *eq) 2077 { 2078 int rc; 2079 size_t len; 2080 2081 mtx_init(&eq->eq_lock, eq->lockname, NULL, MTX_DEF); 2082 2083 len = eq->qsize * EQ_ESIZE; 2084 rc = alloc_ring(sc, len, &eq->desc_tag, &eq->desc_map, 2085 &eq->ba, (void **)&eq->desc); 2086 if (rc) 2087 return (rc); 2088 2089 eq->cap = eq->qsize - SPG_LEN / EQ_ESIZE; 2090 eq->spg = (void *)&eq->desc[eq->cap]; 2091 eq->avail = eq->cap - 1; /* one less to avoid cidx = pidx */ 2092 eq->pidx = eq->cidx = 0; 2093 2094 switch (eq->flags & EQ_TYPEMASK) { 2095 case EQ_CTRL: 2096 rc = ctrl_eq_alloc(sc, eq); 2097 break; 2098 2099 case EQ_ETH: 2100 rc = eth_eq_alloc(sc, pi, eq); 2101 break; 2102 2103 #ifndef TCP_OFFLOAD_DISABLE 2104 case EQ_OFLD: 2105 rc = ofld_eq_alloc(sc, pi, eq); 2106 break; 2107 #endif 2108 2109 default: 2110 panic("%s: invalid eq type %d.", __func__, 2111 eq->flags & EQ_TYPEMASK); 2112 } 2113 if (rc != 0) { 2114 device_printf(sc->dev, 2115 "failed to allocate egress queue(%d): %d", 2116 eq->flags & EQ_TYPEMASK, rc); 2117 } 2118 2119 eq->tx_callout.c_cpu = eq->cntxt_id % mp_ncpus; 2120 2121 return (rc); 2122 } 2123 2124 static int 2125 free_eq(struct adapter *sc, struct sge_eq *eq) 2126 { 2127 int rc; 2128 2129 if (eq->flags & EQ_ALLOCATED) { 2130 switch (eq->flags & EQ_TYPEMASK) { 2131 case EQ_CTRL: 2132 rc = -t4_ctrl_eq_free(sc, sc->mbox, sc->pf, 0, 2133 eq->cntxt_id); 2134 break; 2135 2136 case EQ_ETH: 2137 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0, 2138 eq->cntxt_id); 2139 break; 2140 2141 #ifndef TCP_OFFLOAD_DISABLE 2142 case EQ_OFLD: 2143 rc = -t4_ofld_eq_free(sc, sc->mbox, sc->pf, 0, 2144 eq->cntxt_id); 2145 break; 2146 #endif 2147 2148 default: 2149 panic("%s: invalid eq type %d.", __func__, 2150 eq->flags & EQ_TYPEMASK); 2151 } 2152 if (rc != 0) { 2153 device_printf(sc->dev, 2154 "failed to free egress queue (%d): %d\n", 2155 eq->flags & EQ_TYPEMASK, rc); 2156 return (rc); 2157 } 2158 eq->flags &= ~EQ_ALLOCATED; 2159 } 2160 2161 free_ring(sc, eq->desc_tag, eq->desc_map, eq->ba, eq->desc); 2162 2163 if (mtx_initialized(&eq->eq_lock)) 2164 mtx_destroy(&eq->eq_lock); 2165 2166 bzero(eq, sizeof(*eq)); 2167 return (0); 2168 } 2169 2170 static int 2171 alloc_wrq(struct adapter *sc, struct port_info *pi, struct sge_wrq *wrq, 2172 struct sysctl_oid *oid) 2173 { 2174 int rc; 2175 struct sysctl_ctx_list *ctx = pi ? &pi->ctx : &sc->ctx; 2176 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 2177 2178 rc = alloc_eq(sc, pi, &wrq->eq); 2179 if (rc) 2180 return (rc); 2181 2182 wrq->adapter = sc; 2183 2184 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 2185 &wrq->eq.cntxt_id, 0, "SGE context id of the queue"); 2186 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx", 2187 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.cidx, 0, sysctl_uint16, "I", 2188 "consumer index"); 2189 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pidx", 2190 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.pidx, 0, sysctl_uint16, "I", 2191 "producer index"); 2192 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs", CTLFLAG_RD, 2193 &wrq->tx_wrs, "# of work requests"); 2194 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "no_desc", CTLFLAG_RD, 2195 &wrq->no_desc, 0, 2196 "# of times queue ran out of hardware descriptors"); 2197 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "unstalled", CTLFLAG_RD, 2198 &wrq->eq.unstalled, 0, "# of times queue recovered after stall"); 2199 2200 2201 return (rc); 2202 } 2203 2204 static int 2205 free_wrq(struct adapter *sc, struct sge_wrq *wrq) 2206 { 2207 int rc; 2208 2209 rc = free_eq(sc, &wrq->eq); 2210 if (rc) 2211 return (rc); 2212 2213 bzero(wrq, sizeof(*wrq)); 2214 return (0); 2215 } 2216 2217 static int 2218 alloc_txq(struct port_info *pi, struct sge_txq *txq, int idx, 2219 struct sysctl_oid *oid) 2220 { 2221 int rc; 2222 struct adapter *sc = pi->adapter; 2223 struct sge_eq *eq = &txq->eq; 2224 char name[16]; 2225 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 2226 2227 rc = alloc_eq(sc, pi, eq); 2228 if (rc) 2229 return (rc); 2230 2231 txq->ifp = pi->ifp; 2232 2233 txq->sdesc = malloc(eq->cap * sizeof(struct tx_sdesc), M_CXGBE, 2234 M_ZERO | M_WAITOK); 2235 txq->br = buf_ring_alloc(eq->qsize, M_CXGBE, M_WAITOK, &eq->eq_lock); 2236 2237 rc = bus_dma_tag_create(sc->dmat, 1, 0, BUS_SPACE_MAXADDR, 2238 BUS_SPACE_MAXADDR, NULL, NULL, 64 * 1024, TX_SGL_SEGS, 2239 BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL, NULL, &txq->tx_tag); 2240 if (rc != 0) { 2241 device_printf(sc->dev, 2242 "failed to create tx DMA tag: %d\n", rc); 2243 return (rc); 2244 } 2245 2246 /* 2247 * We can stuff ~10 frames in an 8-descriptor txpkts WR (8 is the SGE 2248 * limit for any WR). txq->no_dmamap events shouldn't occur if maps is 2249 * sized for the worst case. 2250 */ 2251 rc = t4_alloc_tx_maps(&txq->txmaps, txq->tx_tag, eq->qsize * 10 / 8, 2252 M_WAITOK); 2253 if (rc != 0) { 2254 device_printf(sc->dev, "failed to setup tx DMA maps: %d\n", rc); 2255 return (rc); 2256 } 2257 2258 snprintf(name, sizeof(name), "%d", idx); 2259 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 2260 NULL, "tx queue"); 2261 children = SYSCTL_CHILDREN(oid); 2262 2263 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 2264 &eq->cntxt_id, 0, "SGE context id of the queue"); 2265 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cidx", 2266 CTLTYPE_INT | CTLFLAG_RD, &eq->cidx, 0, sysctl_uint16, "I", 2267 "consumer index"); 2268 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "pidx", 2269 CTLTYPE_INT | CTLFLAG_RD, &eq->pidx, 0, sysctl_uint16, "I", 2270 "producer index"); 2271 2272 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "txcsum", CTLFLAG_RD, 2273 &txq->txcsum, "# of times hardware assisted with checksum"); 2274 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "vlan_insertion", 2275 CTLFLAG_RD, &txq->vlan_insertion, 2276 "# of times hardware inserted 802.1Q tag"); 2277 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "tso_wrs", CTLFLAG_RD, 2278 &txq->tso_wrs, "# of IPv4 TSO work requests"); 2279 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "imm_wrs", CTLFLAG_RD, 2280 &txq->imm_wrs, "# of work requests with immediate data"); 2281 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "sgl_wrs", CTLFLAG_RD, 2282 &txq->sgl_wrs, "# of work requests with direct SGL"); 2283 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "txpkt_wrs", CTLFLAG_RD, 2284 &txq->txpkt_wrs, "# of txpkt work requests (one pkt/WR)"); 2285 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "txpkts_wrs", CTLFLAG_RD, 2286 &txq->txpkts_wrs, "# of txpkts work requests (multiple pkts/WR)"); 2287 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "txpkts_pkts", CTLFLAG_RD, 2288 &txq->txpkts_pkts, "# of frames tx'd using txpkts work requests"); 2289 2290 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "no_dmamap", CTLFLAG_RD, 2291 &txq->no_dmamap, 0, "# of times txq ran out of DMA maps"); 2292 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "no_desc", CTLFLAG_RD, 2293 &txq->no_desc, 0, "# of times txq ran out of hardware descriptors"); 2294 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "egr_update", CTLFLAG_RD, 2295 &eq->egr_update, 0, "egress update notifications from the SGE"); 2296 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "unstalled", CTLFLAG_RD, 2297 &eq->unstalled, 0, "# of times txq recovered after stall"); 2298 2299 return (rc); 2300 } 2301 2302 static int 2303 free_txq(struct port_info *pi, struct sge_txq *txq) 2304 { 2305 int rc; 2306 struct adapter *sc = pi->adapter; 2307 struct sge_eq *eq = &txq->eq; 2308 2309 rc = free_eq(sc, eq); 2310 if (rc) 2311 return (rc); 2312 2313 free(txq->sdesc, M_CXGBE); 2314 2315 if (txq->txmaps.maps) 2316 t4_free_tx_maps(&txq->txmaps, txq->tx_tag); 2317 2318 buf_ring_free(txq->br, M_CXGBE); 2319 2320 if (txq->tx_tag) 2321 bus_dma_tag_destroy(txq->tx_tag); 2322 2323 bzero(txq, sizeof(*txq)); 2324 return (0); 2325 } 2326 2327 static void 2328 oneseg_dma_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2329 { 2330 bus_addr_t *ba = arg; 2331 2332 KASSERT(nseg == 1, 2333 ("%s meant for single segment mappings only.", __func__)); 2334 2335 *ba = error ? 0 : segs->ds_addr; 2336 } 2337 2338 static inline bool 2339 is_new_response(const struct sge_iq *iq, struct rsp_ctrl **ctrl) 2340 { 2341 *ctrl = (void *)((uintptr_t)iq->cdesc + 2342 (iq->esize - sizeof(struct rsp_ctrl))); 2343 2344 return (((*ctrl)->u.type_gen >> S_RSPD_GEN) == iq->gen); 2345 } 2346 2347 static inline void 2348 iq_next(struct sge_iq *iq) 2349 { 2350 iq->cdesc = (void *) ((uintptr_t)iq->cdesc + iq->esize); 2351 if (__predict_false(++iq->cidx == iq->qsize - 1)) { 2352 iq->cidx = 0; 2353 iq->gen ^= 1; 2354 iq->cdesc = iq->desc; 2355 } 2356 } 2357 2358 #define FL_HW_IDX(x) ((x) >> 3) 2359 static inline void 2360 ring_fl_db(struct adapter *sc, struct sge_fl *fl) 2361 { 2362 int ndesc = fl->pending / 8; 2363 2364 if (FL_HW_IDX(fl->pidx) == FL_HW_IDX(fl->cidx)) 2365 ndesc--; /* hold back one credit */ 2366 2367 if (ndesc <= 0) 2368 return; /* nothing to do */ 2369 2370 wmb(); 2371 2372 t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL), F_DBPRIO | 2373 V_QID(fl->cntxt_id) | V_PIDX(ndesc)); 2374 fl->pending -= ndesc * 8; 2375 } 2376 2377 /* 2378 * Fill up the freelist by upto nbufs and maybe ring its doorbell. 2379 * 2380 * Returns non-zero to indicate that it should be added to the list of starving 2381 * freelists. 2382 */ 2383 static int 2384 refill_fl(struct adapter *sc, struct sge_fl *fl, int nbufs) 2385 { 2386 __be64 *d = &fl->desc[fl->pidx]; 2387 struct fl_sdesc *sd = &fl->sdesc[fl->pidx]; 2388 bus_dma_tag_t tag; 2389 bus_addr_t pa; 2390 caddr_t cl; 2391 int rc; 2392 2393 FL_LOCK_ASSERT_OWNED(fl); 2394 2395 if (nbufs > fl->needed) 2396 nbufs = fl->needed; 2397 2398 while (nbufs--) { 2399 2400 if (sd->cl != NULL) { 2401 2402 /* 2403 * This happens when a frame small enough to fit 2404 * entirely in an mbuf was received in cl last time. 2405 * We'd held on to cl and can reuse it now. Note that 2406 * we reuse a cluster of the old size if fl->tag_idx is 2407 * no longer the same as sd->tag_idx. 2408 */ 2409 2410 KASSERT(*d == sd->ba_tag, 2411 ("%s: recyling problem at pidx %d", 2412 __func__, fl->pidx)); 2413 2414 d++; 2415 goto recycled; 2416 } 2417 2418 2419 if (fl->tag_idx != sd->tag_idx) { 2420 bus_dmamap_t map; 2421 bus_dma_tag_t newtag = fl->tag[fl->tag_idx]; 2422 bus_dma_tag_t oldtag = fl->tag[sd->tag_idx]; 2423 2424 /* 2425 * An MTU change can get us here. Discard the old map 2426 * which was created with the old tag, but only if 2427 * we're able to get a new one. 2428 */ 2429 rc = bus_dmamap_create(newtag, 0, &map); 2430 if (rc == 0) { 2431 bus_dmamap_destroy(oldtag, sd->map); 2432 sd->map = map; 2433 sd->tag_idx = fl->tag_idx; 2434 } 2435 } 2436 2437 tag = fl->tag[sd->tag_idx]; 2438 2439 cl = m_cljget(NULL, M_NOWAIT, FL_BUF_SIZE(sd->tag_idx)); 2440 if (cl == NULL) 2441 break; 2442 2443 rc = bus_dmamap_load(tag, sd->map, cl, FL_BUF_SIZE(sd->tag_idx), 2444 oneseg_dma_callback, &pa, 0); 2445 if (rc != 0 || pa == 0) { 2446 fl->dmamap_failed++; 2447 uma_zfree(FL_BUF_ZONE(sd->tag_idx), cl); 2448 break; 2449 } 2450 2451 sd->cl = cl; 2452 *d++ = htobe64(pa | sd->tag_idx); 2453 2454 #ifdef INVARIANTS 2455 sd->ba_tag = htobe64(pa | sd->tag_idx); 2456 #endif 2457 2458 recycled: 2459 /* sd->m is never recycled, should always be NULL */ 2460 KASSERT(sd->m == NULL, ("%s: stray mbuf", __func__)); 2461 2462 sd->m = m_gethdr(M_NOWAIT, MT_NOINIT); 2463 if (sd->m == NULL) 2464 break; 2465 2466 fl->pending++; 2467 fl->needed--; 2468 sd++; 2469 if (++fl->pidx == fl->cap) { 2470 fl->pidx = 0; 2471 sd = fl->sdesc; 2472 d = fl->desc; 2473 } 2474 } 2475 2476 if (fl->pending >= 8) 2477 ring_fl_db(sc, fl); 2478 2479 return (FL_RUNNING_LOW(fl) && !(fl->flags & FL_STARVING)); 2480 } 2481 2482 /* 2483 * Attempt to refill all starving freelists. 2484 */ 2485 static void 2486 refill_sfl(void *arg) 2487 { 2488 struct adapter *sc = arg; 2489 struct sge_fl *fl, *fl_temp; 2490 2491 mtx_lock(&sc->sfl_lock); 2492 TAILQ_FOREACH_SAFE(fl, &sc->sfl, link, fl_temp) { 2493 FL_LOCK(fl); 2494 refill_fl(sc, fl, 64); 2495 if (FL_NOT_RUNNING_LOW(fl) || fl->flags & FL_DOOMED) { 2496 TAILQ_REMOVE(&sc->sfl, fl, link); 2497 fl->flags &= ~FL_STARVING; 2498 } 2499 FL_UNLOCK(fl); 2500 } 2501 2502 if (!TAILQ_EMPTY(&sc->sfl)) 2503 callout_schedule(&sc->sfl_callout, hz / 5); 2504 mtx_unlock(&sc->sfl_lock); 2505 } 2506 2507 static int 2508 alloc_fl_sdesc(struct sge_fl *fl) 2509 { 2510 struct fl_sdesc *sd; 2511 bus_dma_tag_t tag; 2512 int i, rc; 2513 2514 FL_LOCK_ASSERT_OWNED(fl); 2515 2516 fl->sdesc = malloc(fl->cap * sizeof(struct fl_sdesc), M_CXGBE, 2517 M_ZERO | M_WAITOK); 2518 2519 tag = fl->tag[fl->tag_idx]; 2520 sd = fl->sdesc; 2521 for (i = 0; i < fl->cap; i++, sd++) { 2522 2523 sd->tag_idx = fl->tag_idx; 2524 rc = bus_dmamap_create(tag, 0, &sd->map); 2525 if (rc != 0) 2526 goto failed; 2527 } 2528 2529 return (0); 2530 failed: 2531 while (--i >= 0) { 2532 sd--; 2533 bus_dmamap_destroy(tag, sd->map); 2534 if (sd->m) { 2535 m_init(sd->m, NULL, 0, M_NOWAIT, MT_DATA, 0); 2536 m_free(sd->m); 2537 sd->m = NULL; 2538 } 2539 } 2540 KASSERT(sd == fl->sdesc, ("%s: EDOOFUS", __func__)); 2541 2542 free(fl->sdesc, M_CXGBE); 2543 fl->sdesc = NULL; 2544 2545 return (rc); 2546 } 2547 2548 static void 2549 free_fl_sdesc(struct sge_fl *fl) 2550 { 2551 struct fl_sdesc *sd; 2552 int i; 2553 2554 FL_LOCK_ASSERT_OWNED(fl); 2555 2556 sd = fl->sdesc; 2557 for (i = 0; i < fl->cap; i++, sd++) { 2558 2559 if (sd->m) { 2560 m_init(sd->m, NULL, 0, M_NOWAIT, MT_DATA, 0); 2561 m_free(sd->m); 2562 sd->m = NULL; 2563 } 2564 2565 if (sd->cl) { 2566 bus_dmamap_unload(fl->tag[sd->tag_idx], sd->map); 2567 uma_zfree(FL_BUF_ZONE(sd->tag_idx), sd->cl); 2568 sd->cl = NULL; 2569 } 2570 2571 bus_dmamap_destroy(fl->tag[sd->tag_idx], sd->map); 2572 } 2573 2574 free(fl->sdesc, M_CXGBE); 2575 fl->sdesc = NULL; 2576 } 2577 2578 int 2579 t4_alloc_tx_maps(struct tx_maps *txmaps, bus_dma_tag_t tx_tag, int count, 2580 int flags) 2581 { 2582 struct tx_map *txm; 2583 int i, rc; 2584 2585 txmaps->map_total = txmaps->map_avail = count; 2586 txmaps->map_cidx = txmaps->map_pidx = 0; 2587 2588 txmaps->maps = malloc(count * sizeof(struct tx_map), M_CXGBE, 2589 M_ZERO | flags); 2590 2591 txm = txmaps->maps; 2592 for (i = 0; i < count; i++, txm++) { 2593 rc = bus_dmamap_create(tx_tag, 0, &txm->map); 2594 if (rc != 0) 2595 goto failed; 2596 } 2597 2598 return (0); 2599 failed: 2600 while (--i >= 0) { 2601 txm--; 2602 bus_dmamap_destroy(tx_tag, txm->map); 2603 } 2604 KASSERT(txm == txmaps->maps, ("%s: EDOOFUS", __func__)); 2605 2606 free(txmaps->maps, M_CXGBE); 2607 txmaps->maps = NULL; 2608 2609 return (rc); 2610 } 2611 2612 void 2613 t4_free_tx_maps(struct tx_maps *txmaps, bus_dma_tag_t tx_tag) 2614 { 2615 struct tx_map *txm; 2616 int i; 2617 2618 txm = txmaps->maps; 2619 for (i = 0; i < txmaps->map_total; i++, txm++) { 2620 2621 if (txm->m) { 2622 bus_dmamap_unload(tx_tag, txm->map); 2623 m_freem(txm->m); 2624 txm->m = NULL; 2625 } 2626 2627 bus_dmamap_destroy(tx_tag, txm->map); 2628 } 2629 2630 free(txmaps->maps, M_CXGBE); 2631 txmaps->maps = NULL; 2632 } 2633 2634 /* 2635 * We'll do immediate data tx for non-TSO, but only when not coalescing. We're 2636 * willing to use upto 2 hardware descriptors which means a maximum of 96 bytes 2637 * of immediate data. 2638 */ 2639 #define IMM_LEN ( \ 2640 2 * EQ_ESIZE \ 2641 - sizeof(struct fw_eth_tx_pkt_wr) \ 2642 - sizeof(struct cpl_tx_pkt_core)) 2643 2644 /* 2645 * Returns non-zero on failure, no need to cleanup anything in that case. 2646 * 2647 * Note 1: We always try to defrag the mbuf if required and return EFBIG only 2648 * if the resulting chain still won't fit in a tx descriptor. 2649 * 2650 * Note 2: We'll pullup the mbuf chain if TSO is requested and the first mbuf 2651 * does not have the TCP header in it. 2652 */ 2653 static int 2654 get_pkt_sgl(struct sge_txq *txq, struct mbuf **fp, struct sgl *sgl, 2655 int sgl_only) 2656 { 2657 struct mbuf *m = *fp; 2658 struct tx_maps *txmaps; 2659 struct tx_map *txm; 2660 int rc, defragged = 0, n; 2661 2662 TXQ_LOCK_ASSERT_OWNED(txq); 2663 2664 if (m->m_pkthdr.tso_segsz) 2665 sgl_only = 1; /* Do not allow immediate data with LSO */ 2666 2667 start: sgl->nsegs = 0; 2668 2669 if (m->m_pkthdr.len <= IMM_LEN && !sgl_only) 2670 return (0); /* nsegs = 0 tells caller to use imm. tx */ 2671 2672 txmaps = &txq->txmaps; 2673 if (txmaps->map_avail == 0) { 2674 txq->no_dmamap++; 2675 return (ENOMEM); 2676 } 2677 txm = &txmaps->maps[txmaps->map_pidx]; 2678 2679 if (m->m_pkthdr.tso_segsz && m->m_len < 50) { 2680 *fp = m_pullup(m, 50); 2681 m = *fp; 2682 if (m == NULL) 2683 return (ENOBUFS); 2684 } 2685 2686 rc = bus_dmamap_load_mbuf_sg(txq->tx_tag, txm->map, m, sgl->seg, 2687 &sgl->nsegs, BUS_DMA_NOWAIT); 2688 if (rc == EFBIG && defragged == 0) { 2689 m = m_defrag(m, M_DONTWAIT); 2690 if (m == NULL) 2691 return (EFBIG); 2692 2693 defragged = 1; 2694 *fp = m; 2695 goto start; 2696 } 2697 if (rc != 0) 2698 return (rc); 2699 2700 txm->m = m; 2701 txmaps->map_avail--; 2702 if (++txmaps->map_pidx == txmaps->map_total) 2703 txmaps->map_pidx = 0; 2704 2705 KASSERT(sgl->nsegs > 0 && sgl->nsegs <= TX_SGL_SEGS, 2706 ("%s: bad DMA mapping (%d segments)", __func__, sgl->nsegs)); 2707 2708 /* 2709 * Store the # of flits required to hold this frame's SGL in nflits. An 2710 * SGL has a (ULPTX header + len0, addr0) tuple optionally followed by 2711 * multiple (len0 + len1, addr0, addr1) tuples. If addr1 is not used 2712 * then len1 must be set to 0. 2713 */ 2714 n = sgl->nsegs - 1; 2715 sgl->nflits = (3 * n) / 2 + (n & 1) + 2; 2716 2717 return (0); 2718 } 2719 2720 2721 /* 2722 * Releases all the txq resources used up in the specified sgl. 2723 */ 2724 static int 2725 free_pkt_sgl(struct sge_txq *txq, struct sgl *sgl) 2726 { 2727 struct tx_maps *txmaps; 2728 struct tx_map *txm; 2729 2730 TXQ_LOCK_ASSERT_OWNED(txq); 2731 2732 if (sgl->nsegs == 0) 2733 return (0); /* didn't use any map */ 2734 2735 txmaps = &txq->txmaps; 2736 2737 /* 1 pkt uses exactly 1 map, back it out */ 2738 2739 txmaps->map_avail++; 2740 if (txmaps->map_pidx > 0) 2741 txmaps->map_pidx--; 2742 else 2743 txmaps->map_pidx = txmaps->map_total - 1; 2744 2745 txm = &txmaps->maps[txmaps->map_pidx]; 2746 bus_dmamap_unload(txq->tx_tag, txm->map); 2747 txm->m = NULL; 2748 2749 return (0); 2750 } 2751 2752 static int 2753 write_txpkt_wr(struct port_info *pi, struct sge_txq *txq, struct mbuf *m, 2754 struct sgl *sgl) 2755 { 2756 struct sge_eq *eq = &txq->eq; 2757 struct fw_eth_tx_pkt_wr *wr; 2758 struct cpl_tx_pkt_core *cpl; 2759 uint32_t ctrl; /* used in many unrelated places */ 2760 uint64_t ctrl1; 2761 int nflits, ndesc, pktlen; 2762 struct tx_sdesc *txsd; 2763 caddr_t dst; 2764 2765 TXQ_LOCK_ASSERT_OWNED(txq); 2766 2767 pktlen = m->m_pkthdr.len; 2768 2769 /* 2770 * Do we have enough flits to send this frame out? 2771 */ 2772 ctrl = sizeof(struct cpl_tx_pkt_core); 2773 if (m->m_pkthdr.tso_segsz) { 2774 nflits = TXPKT_LSO_WR_HDR; 2775 ctrl += sizeof(struct cpl_tx_pkt_lso); 2776 } else 2777 nflits = TXPKT_WR_HDR; 2778 if (sgl->nsegs > 0) 2779 nflits += sgl->nflits; 2780 else { 2781 nflits += howmany(pktlen, 8); 2782 ctrl += pktlen; 2783 } 2784 ndesc = howmany(nflits, 8); 2785 if (ndesc > eq->avail) 2786 return (ENOMEM); 2787 2788 /* Firmware work request header */ 2789 wr = (void *)&eq->desc[eq->pidx]; 2790 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_WR) | 2791 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl)); 2792 ctrl = V_FW_WR_LEN16(howmany(nflits, 2)); 2793 if (eq->avail == ndesc) { 2794 if (!(eq->flags & EQ_CRFLUSHED)) { 2795 ctrl |= F_FW_WR_EQUEQ | F_FW_WR_EQUIQ; 2796 eq->flags |= EQ_CRFLUSHED; 2797 } 2798 eq->flags |= EQ_STALLED; 2799 } 2800 2801 wr->equiq_to_len16 = htobe32(ctrl); 2802 wr->r3 = 0; 2803 2804 if (m->m_pkthdr.tso_segsz) { 2805 struct cpl_tx_pkt_lso *lso = (void *)(wr + 1); 2806 struct ether_header *eh; 2807 struct ip *ip; 2808 struct tcphdr *tcp; 2809 2810 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE | 2811 F_LSO_LAST_SLICE; 2812 2813 eh = mtod(m, struct ether_header *); 2814 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 2815 ctrl |= V_LSO_ETHHDR_LEN(1); 2816 ip = (void *)((struct ether_vlan_header *)eh + 1); 2817 } else 2818 ip = (void *)(eh + 1); 2819 2820 tcp = (void *)((uintptr_t)ip + ip->ip_hl * 4); 2821 ctrl |= V_LSO_IPHDR_LEN(ip->ip_hl) | 2822 V_LSO_TCPHDR_LEN(tcp->th_off); 2823 2824 lso->lso_ctrl = htobe32(ctrl); 2825 lso->ipid_ofst = htobe16(0); 2826 lso->mss = htobe16(m->m_pkthdr.tso_segsz); 2827 lso->seqno_offset = htobe32(0); 2828 lso->len = htobe32(pktlen); 2829 2830 cpl = (void *)(lso + 1); 2831 2832 txq->tso_wrs++; 2833 } else 2834 cpl = (void *)(wr + 1); 2835 2836 /* Checksum offload */ 2837 ctrl1 = 0; 2838 if (!(m->m_pkthdr.csum_flags & CSUM_IP)) 2839 ctrl1 |= F_TXPKT_IPCSUM_DIS; 2840 if (!(m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))) 2841 ctrl1 |= F_TXPKT_L4CSUM_DIS; 2842 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP)) 2843 txq->txcsum++; /* some hardware assistance provided */ 2844 2845 /* VLAN tag insertion */ 2846 if (m->m_flags & M_VLANTAG) { 2847 ctrl1 |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(m->m_pkthdr.ether_vtag); 2848 txq->vlan_insertion++; 2849 } 2850 2851 /* CPL header */ 2852 cpl->ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) | 2853 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(pi->adapter->pf)); 2854 cpl->pack = 0; 2855 cpl->len = htobe16(pktlen); 2856 cpl->ctrl1 = htobe64(ctrl1); 2857 2858 /* Software descriptor */ 2859 txsd = &txq->sdesc[eq->pidx]; 2860 txsd->desc_used = ndesc; 2861 2862 eq->pending += ndesc; 2863 eq->avail -= ndesc; 2864 eq->pidx += ndesc; 2865 if (eq->pidx >= eq->cap) 2866 eq->pidx -= eq->cap; 2867 2868 /* SGL */ 2869 dst = (void *)(cpl + 1); 2870 if (sgl->nsegs > 0) { 2871 txsd->credits = 1; 2872 txq->sgl_wrs++; 2873 write_sgl_to_txd(eq, sgl, &dst); 2874 } else { 2875 txsd->credits = 0; 2876 txq->imm_wrs++; 2877 for (; m; m = m->m_next) { 2878 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len); 2879 #ifdef INVARIANTS 2880 pktlen -= m->m_len; 2881 #endif 2882 } 2883 #ifdef INVARIANTS 2884 KASSERT(pktlen == 0, ("%s: %d bytes left.", __func__, pktlen)); 2885 #endif 2886 2887 } 2888 2889 txq->txpkt_wrs++; 2890 return (0); 2891 } 2892 2893 /* 2894 * Returns 0 to indicate that m has been accepted into a coalesced tx work 2895 * request. It has either been folded into txpkts or txpkts was flushed and m 2896 * has started a new coalesced work request (as the first frame in a fresh 2897 * txpkts). 2898 * 2899 * Returns non-zero to indicate a failure - caller is responsible for 2900 * transmitting m, if there was anything in txpkts it has been flushed. 2901 */ 2902 static int 2903 add_to_txpkts(struct port_info *pi, struct sge_txq *txq, struct txpkts *txpkts, 2904 struct mbuf *m, struct sgl *sgl) 2905 { 2906 struct sge_eq *eq = &txq->eq; 2907 int can_coalesce; 2908 struct tx_sdesc *txsd; 2909 int flits; 2910 2911 TXQ_LOCK_ASSERT_OWNED(txq); 2912 2913 KASSERT(sgl->nsegs, ("%s: can't coalesce imm data", __func__)); 2914 2915 if (txpkts->npkt > 0) { 2916 flits = TXPKTS_PKT_HDR + sgl->nflits; 2917 can_coalesce = m->m_pkthdr.tso_segsz == 0 && 2918 txpkts->nflits + flits <= TX_WR_FLITS && 2919 txpkts->nflits + flits <= eq->avail * 8 && 2920 txpkts->plen + m->m_pkthdr.len < 65536; 2921 2922 if (can_coalesce) { 2923 txpkts->npkt++; 2924 txpkts->nflits += flits; 2925 txpkts->plen += m->m_pkthdr.len; 2926 2927 txsd = &txq->sdesc[eq->pidx]; 2928 txsd->credits++; 2929 2930 return (0); 2931 } 2932 2933 /* 2934 * Couldn't coalesce m into txpkts. The first order of business 2935 * is to send txpkts on its way. Then we'll revisit m. 2936 */ 2937 write_txpkts_wr(txq, txpkts); 2938 } 2939 2940 /* 2941 * Check if we can start a new coalesced tx work request with m as 2942 * the first packet in it. 2943 */ 2944 2945 KASSERT(txpkts->npkt == 0, ("%s: txpkts not empty", __func__)); 2946 2947 flits = TXPKTS_WR_HDR + sgl->nflits; 2948 can_coalesce = m->m_pkthdr.tso_segsz == 0 && 2949 flits <= eq->avail * 8 && flits <= TX_WR_FLITS; 2950 2951 if (can_coalesce == 0) 2952 return (EINVAL); 2953 2954 /* 2955 * Start a fresh coalesced tx WR with m as the first frame in it. 2956 */ 2957 txpkts->npkt = 1; 2958 txpkts->nflits = flits; 2959 txpkts->flitp = &eq->desc[eq->pidx].flit[2]; 2960 txpkts->plen = m->m_pkthdr.len; 2961 2962 txsd = &txq->sdesc[eq->pidx]; 2963 txsd->credits = 1; 2964 2965 return (0); 2966 } 2967 2968 /* 2969 * Note that write_txpkts_wr can never run out of hardware descriptors (but 2970 * write_txpkt_wr can). add_to_txpkts ensures that a frame is accepted for 2971 * coalescing only if sufficient hardware descriptors are available. 2972 */ 2973 static void 2974 write_txpkts_wr(struct sge_txq *txq, struct txpkts *txpkts) 2975 { 2976 struct sge_eq *eq = &txq->eq; 2977 struct fw_eth_tx_pkts_wr *wr; 2978 struct tx_sdesc *txsd; 2979 uint32_t ctrl; 2980 int ndesc; 2981 2982 TXQ_LOCK_ASSERT_OWNED(txq); 2983 2984 ndesc = howmany(txpkts->nflits, 8); 2985 2986 wr = (void *)&eq->desc[eq->pidx]; 2987 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR)); 2988 ctrl = V_FW_WR_LEN16(howmany(txpkts->nflits, 2)); 2989 if (eq->avail == ndesc) { 2990 if (!(eq->flags & EQ_CRFLUSHED)) { 2991 ctrl |= F_FW_WR_EQUEQ | F_FW_WR_EQUIQ; 2992 eq->flags |= EQ_CRFLUSHED; 2993 } 2994 eq->flags |= EQ_STALLED; 2995 } 2996 wr->equiq_to_len16 = htobe32(ctrl); 2997 wr->plen = htobe16(txpkts->plen); 2998 wr->npkt = txpkts->npkt; 2999 wr->r3 = wr->type = 0; 3000 3001 /* Everything else already written */ 3002 3003 txsd = &txq->sdesc[eq->pidx]; 3004 txsd->desc_used = ndesc; 3005 3006 KASSERT(eq->avail >= ndesc, ("%s: out of descriptors", __func__)); 3007 3008 eq->pending += ndesc; 3009 eq->avail -= ndesc; 3010 eq->pidx += ndesc; 3011 if (eq->pidx >= eq->cap) 3012 eq->pidx -= eq->cap; 3013 3014 txq->txpkts_pkts += txpkts->npkt; 3015 txq->txpkts_wrs++; 3016 txpkts->npkt = 0; /* emptied */ 3017 } 3018 3019 static inline void 3020 write_ulp_cpl_sgl(struct port_info *pi, struct sge_txq *txq, 3021 struct txpkts *txpkts, struct mbuf *m, struct sgl *sgl) 3022 { 3023 struct ulp_txpkt *ulpmc; 3024 struct ulptx_idata *ulpsc; 3025 struct cpl_tx_pkt_core *cpl; 3026 struct sge_eq *eq = &txq->eq; 3027 uintptr_t flitp, start, end; 3028 uint64_t ctrl; 3029 caddr_t dst; 3030 3031 KASSERT(txpkts->npkt > 0, ("%s: txpkts is empty", __func__)); 3032 3033 start = (uintptr_t)eq->desc; 3034 end = (uintptr_t)eq->spg; 3035 3036 /* Checksum offload */ 3037 ctrl = 0; 3038 if (!(m->m_pkthdr.csum_flags & CSUM_IP)) 3039 ctrl |= F_TXPKT_IPCSUM_DIS; 3040 if (!(m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))) 3041 ctrl |= F_TXPKT_L4CSUM_DIS; 3042 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP)) 3043 txq->txcsum++; /* some hardware assistance provided */ 3044 3045 /* VLAN tag insertion */ 3046 if (m->m_flags & M_VLANTAG) { 3047 ctrl |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(m->m_pkthdr.ether_vtag); 3048 txq->vlan_insertion++; 3049 } 3050 3051 /* 3052 * The previous packet's SGL must have ended at a 16 byte boundary (this 3053 * is required by the firmware/hardware). It follows that flitp cannot 3054 * wrap around between the ULPTX master command and ULPTX subcommand (8 3055 * bytes each), and that it can not wrap around in the middle of the 3056 * cpl_tx_pkt_core either. 3057 */ 3058 flitp = (uintptr_t)txpkts->flitp; 3059 KASSERT((flitp & 0xf) == 0, 3060 ("%s: last SGL did not end at 16 byte boundary: %p", 3061 __func__, txpkts->flitp)); 3062 3063 /* ULP master command */ 3064 ulpmc = (void *)flitp; 3065 ulpmc->cmd_dest = htonl(V_ULPTX_CMD(ULP_TX_PKT) | V_ULP_TXPKT_DEST(0) | 3066 V_ULP_TXPKT_FID(eq->iqid)); 3067 ulpmc->len = htonl(howmany(sizeof(*ulpmc) + sizeof(*ulpsc) + 3068 sizeof(*cpl) + 8 * sgl->nflits, 16)); 3069 3070 /* ULP subcommand */ 3071 ulpsc = (void *)(ulpmc + 1); 3072 ulpsc->cmd_more = htobe32(V_ULPTX_CMD((u32)ULP_TX_SC_IMM) | 3073 F_ULP_TX_SC_MORE); 3074 ulpsc->len = htobe32(sizeof(struct cpl_tx_pkt_core)); 3075 3076 flitp += sizeof(*ulpmc) + sizeof(*ulpsc); 3077 if (flitp == end) 3078 flitp = start; 3079 3080 /* CPL_TX_PKT */ 3081 cpl = (void *)flitp; 3082 cpl->ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) | 3083 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(pi->adapter->pf)); 3084 cpl->pack = 0; 3085 cpl->len = htobe16(m->m_pkthdr.len); 3086 cpl->ctrl1 = htobe64(ctrl); 3087 3088 flitp += sizeof(*cpl); 3089 if (flitp == end) 3090 flitp = start; 3091 3092 /* SGL for this frame */ 3093 dst = (caddr_t)flitp; 3094 txpkts->nflits += write_sgl_to_txd(eq, sgl, &dst); 3095 txpkts->flitp = (void *)dst; 3096 3097 KASSERT(((uintptr_t)dst & 0xf) == 0, 3098 ("%s: SGL ends at %p (not a 16 byte boundary)", __func__, dst)); 3099 } 3100 3101 /* 3102 * If the SGL ends on an address that is not 16 byte aligned, this function will 3103 * add a 0 filled flit at the end. It returns 1 in that case. 3104 */ 3105 static int 3106 write_sgl_to_txd(struct sge_eq *eq, struct sgl *sgl, caddr_t *to) 3107 { 3108 __be64 *flitp, *end; 3109 struct ulptx_sgl *usgl; 3110 bus_dma_segment_t *seg; 3111 int i, padded; 3112 3113 KASSERT(sgl->nsegs > 0 && sgl->nflits > 0, 3114 ("%s: bad SGL - nsegs=%d, nflits=%d", 3115 __func__, sgl->nsegs, sgl->nflits)); 3116 3117 KASSERT(((uintptr_t)(*to) & 0xf) == 0, 3118 ("%s: SGL must start at a 16 byte boundary: %p", __func__, *to)); 3119 3120 flitp = (__be64 *)(*to); 3121 end = flitp + sgl->nflits; 3122 seg = &sgl->seg[0]; 3123 usgl = (void *)flitp; 3124 3125 /* 3126 * We start at a 16 byte boundary somewhere inside the tx descriptor 3127 * ring, so we're at least 16 bytes away from the status page. There is 3128 * no chance of a wrap around in the middle of usgl (which is 16 bytes). 3129 */ 3130 3131 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 3132 V_ULPTX_NSGE(sgl->nsegs)); 3133 usgl->len0 = htobe32(seg->ds_len); 3134 usgl->addr0 = htobe64(seg->ds_addr); 3135 seg++; 3136 3137 if ((uintptr_t)end <= (uintptr_t)eq->spg) { 3138 3139 /* Won't wrap around at all */ 3140 3141 for (i = 0; i < sgl->nsegs - 1; i++, seg++) { 3142 usgl->sge[i / 2].len[i & 1] = htobe32(seg->ds_len); 3143 usgl->sge[i / 2].addr[i & 1] = htobe64(seg->ds_addr); 3144 } 3145 if (i & 1) 3146 usgl->sge[i / 2].len[1] = htobe32(0); 3147 } else { 3148 3149 /* Will wrap somewhere in the rest of the SGL */ 3150 3151 /* 2 flits already written, write the rest flit by flit */ 3152 flitp = (void *)(usgl + 1); 3153 for (i = 0; i < sgl->nflits - 2; i++) { 3154 if ((uintptr_t)flitp == (uintptr_t)eq->spg) 3155 flitp = (void *)eq->desc; 3156 *flitp++ = get_flit(seg, sgl->nsegs - 1, i); 3157 } 3158 end = flitp; 3159 } 3160 3161 if ((uintptr_t)end & 0xf) { 3162 *(uint64_t *)end = 0; 3163 end++; 3164 padded = 1; 3165 } else 3166 padded = 0; 3167 3168 if ((uintptr_t)end == (uintptr_t)eq->spg) 3169 *to = (void *)eq->desc; 3170 else 3171 *to = (void *)end; 3172 3173 return (padded); 3174 } 3175 3176 static inline void 3177 copy_to_txd(struct sge_eq *eq, caddr_t from, caddr_t *to, int len) 3178 { 3179 if ((uintptr_t)(*to) + len <= (uintptr_t)eq->spg) { 3180 bcopy(from, *to, len); 3181 (*to) += len; 3182 } else { 3183 int portion = (uintptr_t)eq->spg - (uintptr_t)(*to); 3184 3185 bcopy(from, *to, portion); 3186 from += portion; 3187 portion = len - portion; /* remaining */ 3188 bcopy(from, (void *)eq->desc, portion); 3189 (*to) = (caddr_t)eq->desc + portion; 3190 } 3191 } 3192 3193 static inline void 3194 ring_eq_db(struct adapter *sc, struct sge_eq *eq) 3195 { 3196 wmb(); 3197 t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL), 3198 V_QID(eq->cntxt_id) | V_PIDX(eq->pending)); 3199 eq->pending = 0; 3200 } 3201 3202 static inline int 3203 reclaimable(struct sge_eq *eq) 3204 { 3205 unsigned int cidx; 3206 3207 cidx = eq->spg->cidx; /* stable snapshot */ 3208 cidx = be16toh(cidx); 3209 3210 if (cidx >= eq->cidx) 3211 return (cidx - eq->cidx); 3212 else 3213 return (cidx + eq->cap - eq->cidx); 3214 } 3215 3216 /* 3217 * There are "can_reclaim" tx descriptors ready to be reclaimed. Reclaim as 3218 * many as possible but stop when there are around "n" mbufs to free. 3219 * 3220 * The actual number reclaimed is provided as the return value. 3221 */ 3222 static int 3223 reclaim_tx_descs(struct sge_txq *txq, int can_reclaim, int n) 3224 { 3225 struct tx_sdesc *txsd; 3226 struct tx_maps *txmaps; 3227 struct tx_map *txm; 3228 unsigned int reclaimed, maps; 3229 struct sge_eq *eq = &txq->eq; 3230 3231 TXQ_LOCK_ASSERT_OWNED(txq); 3232 3233 if (can_reclaim == 0) 3234 can_reclaim = reclaimable(eq); 3235 3236 maps = reclaimed = 0; 3237 while (can_reclaim && maps < n) { 3238 int ndesc; 3239 3240 txsd = &txq->sdesc[eq->cidx]; 3241 ndesc = txsd->desc_used; 3242 3243 /* Firmware doesn't return "partial" credits. */ 3244 KASSERT(can_reclaim >= ndesc, 3245 ("%s: unexpected number of credits: %d, %d", 3246 __func__, can_reclaim, ndesc)); 3247 3248 maps += txsd->credits; 3249 3250 reclaimed += ndesc; 3251 can_reclaim -= ndesc; 3252 3253 eq->cidx += ndesc; 3254 if (__predict_false(eq->cidx >= eq->cap)) 3255 eq->cidx -= eq->cap; 3256 } 3257 3258 txmaps = &txq->txmaps; 3259 txm = &txmaps->maps[txmaps->map_cidx]; 3260 if (maps) 3261 prefetch(txm->m); 3262 3263 eq->avail += reclaimed; 3264 KASSERT(eq->avail < eq->cap, /* avail tops out at (cap - 1) */ 3265 ("%s: too many descriptors available", __func__)); 3266 3267 txmaps->map_avail += maps; 3268 KASSERT(txmaps->map_avail <= txmaps->map_total, 3269 ("%s: too many maps available", __func__)); 3270 3271 while (maps--) { 3272 struct tx_map *next; 3273 3274 next = txm + 1; 3275 if (__predict_false(txmaps->map_cidx + 1 == txmaps->map_total)) 3276 next = txmaps->maps; 3277 prefetch(next->m); 3278 3279 bus_dmamap_unload(txq->tx_tag, txm->map); 3280 m_freem(txm->m); 3281 txm->m = NULL; 3282 3283 txm = next; 3284 if (__predict_false(++txmaps->map_cidx == txmaps->map_total)) 3285 txmaps->map_cidx = 0; 3286 } 3287 3288 return (reclaimed); 3289 } 3290 3291 static void 3292 write_eqflush_wr(struct sge_eq *eq) 3293 { 3294 struct fw_eq_flush_wr *wr; 3295 3296 EQ_LOCK_ASSERT_OWNED(eq); 3297 KASSERT(eq->avail > 0, ("%s: no descriptors left.", __func__)); 3298 KASSERT(!(eq->flags & EQ_CRFLUSHED), ("%s: flushed already", __func__)); 3299 3300 wr = (void *)&eq->desc[eq->pidx]; 3301 bzero(wr, sizeof(*wr)); 3302 wr->opcode = FW_EQ_FLUSH_WR; 3303 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(sizeof(*wr) / 16) | 3304 F_FW_WR_EQUEQ | F_FW_WR_EQUIQ); 3305 3306 eq->flags |= (EQ_CRFLUSHED | EQ_STALLED); 3307 eq->pending++; 3308 eq->avail--; 3309 if (++eq->pidx == eq->cap) 3310 eq->pidx = 0; 3311 } 3312 3313 static __be64 3314 get_flit(bus_dma_segment_t *sgl, int nsegs, int idx) 3315 { 3316 int i = (idx / 3) * 2; 3317 3318 switch (idx % 3) { 3319 case 0: { 3320 __be64 rc; 3321 3322 rc = htobe32(sgl[i].ds_len); 3323 if (i + 1 < nsegs) 3324 rc |= (uint64_t)htobe32(sgl[i + 1].ds_len) << 32; 3325 3326 return (rc); 3327 } 3328 case 1: 3329 return htobe64(sgl[i].ds_addr); 3330 case 2: 3331 return htobe64(sgl[i + 1].ds_addr); 3332 } 3333 3334 return (0); 3335 } 3336 3337 static void 3338 set_fl_tag_idx(struct sge_fl *fl, int bufsize) 3339 { 3340 int i; 3341 3342 for (i = 0; i < FL_BUF_SIZES - 1; i++) { 3343 if (FL_BUF_SIZE(i) >= bufsize) 3344 break; 3345 } 3346 3347 fl->tag_idx = i; 3348 } 3349 3350 static void 3351 add_fl_to_sfl(struct adapter *sc, struct sge_fl *fl) 3352 { 3353 mtx_lock(&sc->sfl_lock); 3354 FL_LOCK(fl); 3355 if ((fl->flags & FL_DOOMED) == 0) { 3356 fl->flags |= FL_STARVING; 3357 TAILQ_INSERT_TAIL(&sc->sfl, fl, link); 3358 callout_reset(&sc->sfl_callout, hz / 5, refill_sfl, sc); 3359 } 3360 FL_UNLOCK(fl); 3361 mtx_unlock(&sc->sfl_lock); 3362 } 3363 3364 static int 3365 handle_sge_egr_update(struct sge_iq *iq, const struct rss_header *rss, 3366 struct mbuf *m) 3367 { 3368 const struct cpl_sge_egr_update *cpl = (const void *)(rss + 1); 3369 unsigned int qid = G_EGR_QID(ntohl(cpl->opcode_qid)); 3370 struct adapter *sc = iq->adapter; 3371 struct sge *s = &sc->sge; 3372 struct sge_eq *eq; 3373 3374 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 3375 rss->opcode)); 3376 3377 eq = s->eqmap[qid - s->eq_start]; 3378 EQ_LOCK(eq); 3379 KASSERT(eq->flags & EQ_CRFLUSHED, 3380 ("%s: unsolicited egress update", __func__)); 3381 eq->flags &= ~EQ_CRFLUSHED; 3382 eq->egr_update++; 3383 3384 if (__predict_false(eq->flags & EQ_DOOMED)) 3385 wakeup_one(eq); 3386 else if (eq->flags & EQ_STALLED && can_resume_tx(eq)) 3387 taskqueue_enqueue(sc->tq[eq->tx_chan], &eq->tx_task); 3388 EQ_UNLOCK(eq); 3389 3390 return (0); 3391 } 3392 3393 static int 3394 handle_fw_rpl(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 3395 { 3396 const struct cpl_fw6_msg *cpl = (const void *)(rss + 1); 3397 3398 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 3399 rss->opcode)); 3400 3401 if (cpl->type == FW6_TYPE_CMD_RPL) 3402 t4_handle_fw_rpl(iq->adapter, cpl->data); 3403 3404 return (0); 3405 } 3406 3407 static int 3408 sysctl_uint16(SYSCTL_HANDLER_ARGS) 3409 { 3410 uint16_t *id = arg1; 3411 int i = *id; 3412 3413 return sysctl_handle_int(oidp, &i, 0, req); 3414 } 3415