1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 Chelsio Communications, Inc. 5 * All rights reserved. 6 * Written by: Navdeep Parhar <np@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include "opt_inet.h" 34 #include "opt_inet6.h" 35 #include "opt_kern_tls.h" 36 #include "opt_ratelimit.h" 37 38 #include <sys/types.h> 39 #include <sys/eventhandler.h> 40 #include <sys/mbuf.h> 41 #include <sys/socket.h> 42 #include <sys/kernel.h> 43 #include <sys/ktls.h> 44 #include <sys/malloc.h> 45 #include <sys/msan.h> 46 #include <sys/queue.h> 47 #include <sys/sbuf.h> 48 #include <sys/taskqueue.h> 49 #include <sys/time.h> 50 #include <sys/sglist.h> 51 #include <sys/sysctl.h> 52 #include <sys/smp.h> 53 #include <sys/socketvar.h> 54 #include <sys/counter.h> 55 #include <net/bpf.h> 56 #include <net/ethernet.h> 57 #include <net/if.h> 58 #include <net/if_vlan_var.h> 59 #include <net/if_vxlan.h> 60 #include <netinet/in.h> 61 #include <netinet/ip.h> 62 #include <netinet/ip6.h> 63 #include <netinet/tcp.h> 64 #include <netinet/udp.h> 65 #include <machine/in_cksum.h> 66 #include <machine/md_var.h> 67 #include <vm/vm.h> 68 #include <vm/pmap.h> 69 #ifdef DEV_NETMAP 70 #include <machine/bus.h> 71 #include <sys/selinfo.h> 72 #include <net/if_var.h> 73 #include <net/netmap.h> 74 #include <dev/netmap/netmap_kern.h> 75 #endif 76 77 #include "common/common.h" 78 #include "common/t4_regs.h" 79 #include "common/t4_regs_values.h" 80 #include "common/t4_msg.h" 81 #include "t4_l2t.h" 82 #include "t4_mp_ring.h" 83 84 #ifdef T4_PKT_TIMESTAMP 85 #define RX_COPY_THRESHOLD (MINCLSIZE - 8) 86 #else 87 #define RX_COPY_THRESHOLD MINCLSIZE 88 #endif 89 90 /* Internal mbuf flags stored in PH_loc.eight[1]. */ 91 #define MC_NOMAP 0x01 92 #define MC_RAW_WR 0x02 93 #define MC_TLS 0x04 94 95 /* 96 * Ethernet frames are DMA'd at this byte offset into the freelist buffer. 97 * 0-7 are valid values. 98 */ 99 static int fl_pktshift = 0; 100 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pktshift, CTLFLAG_RDTUN, &fl_pktshift, 0, 101 "payload DMA offset in rx buffer (bytes)"); 102 103 /* 104 * Pad ethernet payload up to this boundary. 105 * -1: driver should figure out a good value. 106 * 0: disable padding. 107 * Any power of 2 from 32 to 4096 (both inclusive) is also a valid value. 108 */ 109 int fl_pad = -1; 110 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pad, CTLFLAG_RDTUN, &fl_pad, 0, 111 "payload pad boundary (bytes)"); 112 113 /* 114 * Status page length. 115 * -1: driver should figure out a good value. 116 * 64 or 128 are the only other valid values. 117 */ 118 static int spg_len = -1; 119 SYSCTL_INT(_hw_cxgbe, OID_AUTO, spg_len, CTLFLAG_RDTUN, &spg_len, 0, 120 "status page size (bytes)"); 121 122 /* 123 * Congestion drops. 124 * -1: no congestion feedback (not recommended). 125 * 0: backpressure the channel instead of dropping packets right away. 126 * 1: no backpressure, drop packets for the congested queue immediately. 127 */ 128 static int cong_drop = 0; 129 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cong_drop, CTLFLAG_RDTUN, &cong_drop, 0, 130 "Congestion control for RX queues (0 = backpressure, 1 = drop"); 131 132 /* 133 * Deliver multiple frames in the same free list buffer if they fit. 134 * -1: let the driver decide whether to enable buffer packing or not. 135 * 0: disable buffer packing. 136 * 1: enable buffer packing. 137 */ 138 static int buffer_packing = -1; 139 SYSCTL_INT(_hw_cxgbe, OID_AUTO, buffer_packing, CTLFLAG_RDTUN, &buffer_packing, 140 0, "Enable buffer packing"); 141 142 /* 143 * Start next frame in a packed buffer at this boundary. 144 * -1: driver should figure out a good value. 145 * T4: driver will ignore this and use the same value as fl_pad above. 146 * T5: 16, or a power of 2 from 64 to 4096 (both inclusive) is a valid value. 147 */ 148 static int fl_pack = -1; 149 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pack, CTLFLAG_RDTUN, &fl_pack, 0, 150 "payload pack boundary (bytes)"); 151 152 /* 153 * Largest rx cluster size that the driver is allowed to allocate. 154 */ 155 static int largest_rx_cluster = MJUM16BYTES; 156 SYSCTL_INT(_hw_cxgbe, OID_AUTO, largest_rx_cluster, CTLFLAG_RDTUN, 157 &largest_rx_cluster, 0, "Largest rx cluster (bytes)"); 158 159 /* 160 * Size of cluster allocation that's most likely to succeed. The driver will 161 * fall back to this size if it fails to allocate clusters larger than this. 162 */ 163 static int safest_rx_cluster = PAGE_SIZE; 164 SYSCTL_INT(_hw_cxgbe, OID_AUTO, safest_rx_cluster, CTLFLAG_RDTUN, 165 &safest_rx_cluster, 0, "Safe rx cluster (bytes)"); 166 167 #ifdef RATELIMIT 168 /* 169 * Knob to control TCP timestamp rewriting, and the granularity of the tick used 170 * for rewriting. -1 and 0-3 are all valid values. 171 * -1: hardware should leave the TCP timestamps alone. 172 * 0: 1ms 173 * 1: 100us 174 * 2: 10us 175 * 3: 1us 176 */ 177 static int tsclk = -1; 178 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tsclk, CTLFLAG_RDTUN, &tsclk, 0, 179 "Control TCP timestamp rewriting when using pacing"); 180 181 static int eo_max_backlog = 1024 * 1024; 182 SYSCTL_INT(_hw_cxgbe, OID_AUTO, eo_max_backlog, CTLFLAG_RDTUN, &eo_max_backlog, 183 0, "Maximum backlog of ratelimited data per flow"); 184 #endif 185 186 /* 187 * The interrupt holdoff timers are multiplied by this value on T6+. 188 * 1 and 3-17 (both inclusive) are legal values. 189 */ 190 static int tscale = 1; 191 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tscale, CTLFLAG_RDTUN, &tscale, 0, 192 "Interrupt holdoff timer scale on T6+"); 193 194 /* 195 * Number of LRO entries in the lro_ctrl structure per rx queue. 196 */ 197 static int lro_entries = TCP_LRO_ENTRIES; 198 SYSCTL_INT(_hw_cxgbe, OID_AUTO, lro_entries, CTLFLAG_RDTUN, &lro_entries, 0, 199 "Number of LRO entries per RX queue"); 200 201 /* 202 * This enables presorting of frames before they're fed into tcp_lro_rx. 203 */ 204 static int lro_mbufs = 0; 205 SYSCTL_INT(_hw_cxgbe, OID_AUTO, lro_mbufs, CTLFLAG_RDTUN, &lro_mbufs, 0, 206 "Enable presorting of LRO frames"); 207 208 static counter_u64_t pullups; 209 SYSCTL_COUNTER_U64(_hw_cxgbe, OID_AUTO, pullups, CTLFLAG_RD, &pullups, 210 "Number of mbuf pullups performed"); 211 212 static counter_u64_t defrags; 213 SYSCTL_COUNTER_U64(_hw_cxgbe, OID_AUTO, defrags, CTLFLAG_RD, &defrags, 214 "Number of mbuf defrags performed"); 215 216 static int t4_tx_coalesce = 1; 217 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tx_coalesce, CTLFLAG_RWTUN, &t4_tx_coalesce, 0, 218 "tx coalescing allowed"); 219 220 /* 221 * The driver will make aggressive attempts at tx coalescing if it sees these 222 * many packets eligible for coalescing in quick succession, with no more than 223 * the specified gap in between the eth_tx calls that delivered the packets. 224 */ 225 static int t4_tx_coalesce_pkts = 32; 226 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tx_coalesce_pkts, CTLFLAG_RWTUN, 227 &t4_tx_coalesce_pkts, 0, 228 "# of consecutive packets (1 - 255) that will trigger tx coalescing"); 229 static int t4_tx_coalesce_gap = 5; 230 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tx_coalesce_gap, CTLFLAG_RWTUN, 231 &t4_tx_coalesce_gap, 0, "tx gap (in microseconds)"); 232 233 static int service_iq(struct sge_iq *, int); 234 static int service_iq_fl(struct sge_iq *, int); 235 static struct mbuf *get_fl_payload(struct adapter *, struct sge_fl *, uint32_t); 236 static int eth_rx(struct adapter *, struct sge_rxq *, const struct iq_desc *, 237 u_int); 238 static inline void init_iq(struct sge_iq *, struct adapter *, int, int, int, 239 int, int); 240 static inline void init_fl(struct adapter *, struct sge_fl *, int, int, char *); 241 static inline void init_eq(struct adapter *, struct sge_eq *, int, int, uint8_t, 242 struct sge_iq *, char *); 243 static int alloc_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *, 244 struct sysctl_ctx_list *, struct sysctl_oid *); 245 static void free_iq_fl(struct adapter *, struct sge_iq *, struct sge_fl *); 246 static void add_iq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *, 247 struct sge_iq *); 248 static void add_fl_sysctls(struct adapter *, struct sysctl_ctx_list *, 249 struct sysctl_oid *, struct sge_fl *); 250 static int alloc_iq_fl_hwq(struct vi_info *, struct sge_iq *, struct sge_fl *); 251 static int free_iq_fl_hwq(struct adapter *, struct sge_iq *, struct sge_fl *); 252 static int alloc_fwq(struct adapter *); 253 static void free_fwq(struct adapter *); 254 static int alloc_ctrlq(struct adapter *, int); 255 static void free_ctrlq(struct adapter *, int); 256 static int alloc_rxq(struct vi_info *, struct sge_rxq *, int, int, int); 257 static void free_rxq(struct vi_info *, struct sge_rxq *); 258 static void add_rxq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *, 259 struct sge_rxq *); 260 #ifdef TCP_OFFLOAD 261 static int alloc_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *, int, int, 262 int); 263 static void free_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *); 264 static void add_ofld_rxq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *, 265 struct sge_ofld_rxq *); 266 #endif 267 static int ctrl_eq_alloc(struct adapter *, struct sge_eq *); 268 static int eth_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *); 269 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 270 static int ofld_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *); 271 #endif 272 static int alloc_eq(struct adapter *, struct sge_eq *, struct sysctl_ctx_list *, 273 struct sysctl_oid *); 274 static void free_eq(struct adapter *, struct sge_eq *); 275 static void add_eq_sysctls(struct adapter *, struct sysctl_ctx_list *, 276 struct sysctl_oid *, struct sge_eq *); 277 static int alloc_eq_hwq(struct adapter *, struct vi_info *, struct sge_eq *); 278 static int free_eq_hwq(struct adapter *, struct vi_info *, struct sge_eq *); 279 static int alloc_wrq(struct adapter *, struct vi_info *, struct sge_wrq *, 280 struct sysctl_ctx_list *, struct sysctl_oid *); 281 static void free_wrq(struct adapter *, struct sge_wrq *); 282 static void add_wrq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *, 283 struct sge_wrq *); 284 static int alloc_txq(struct vi_info *, struct sge_txq *, int); 285 static void free_txq(struct vi_info *, struct sge_txq *); 286 static void add_txq_sysctls(struct vi_info *, struct sysctl_ctx_list *, 287 struct sysctl_oid *, struct sge_txq *); 288 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 289 static int alloc_ofld_txq(struct vi_info *, struct sge_ofld_txq *, int); 290 static void free_ofld_txq(struct vi_info *, struct sge_ofld_txq *); 291 static void add_ofld_txq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *, 292 struct sge_ofld_txq *); 293 #endif 294 static void oneseg_dma_callback(void *, bus_dma_segment_t *, int, int); 295 static inline void ring_fl_db(struct adapter *, struct sge_fl *); 296 static int refill_fl(struct adapter *, struct sge_fl *, int); 297 static void refill_sfl(void *); 298 static int find_refill_source(struct adapter *, int, bool); 299 static void add_fl_to_sfl(struct adapter *, struct sge_fl *); 300 301 static inline void get_pkt_gl(struct mbuf *, struct sglist *); 302 static inline u_int txpkt_len16(u_int, const u_int); 303 static inline u_int txpkt_vm_len16(u_int, const u_int); 304 static inline void calculate_mbuf_len16(struct mbuf *, bool); 305 static inline u_int txpkts0_len16(u_int); 306 static inline u_int txpkts1_len16(void); 307 static u_int write_raw_wr(struct sge_txq *, void *, struct mbuf *, u_int); 308 static u_int write_txpkt_wr(struct adapter *, struct sge_txq *, struct mbuf *, 309 u_int); 310 static u_int write_txpkt_vm_wr(struct adapter *, struct sge_txq *, 311 struct mbuf *); 312 static int add_to_txpkts_vf(struct adapter *, struct sge_txq *, struct mbuf *, 313 int, bool *); 314 static int add_to_txpkts_pf(struct adapter *, struct sge_txq *, struct mbuf *, 315 int, bool *); 316 static u_int write_txpkts_wr(struct adapter *, struct sge_txq *); 317 static u_int write_txpkts_vm_wr(struct adapter *, struct sge_txq *); 318 static void write_gl_to_txd(struct sge_txq *, struct mbuf *, caddr_t *, int); 319 static inline void copy_to_txd(struct sge_eq *, caddr_t, caddr_t *, int); 320 static inline void ring_eq_db(struct adapter *, struct sge_eq *, u_int); 321 static inline uint16_t read_hw_cidx(struct sge_eq *); 322 static inline u_int reclaimable_tx_desc(struct sge_eq *); 323 static inline u_int total_available_tx_desc(struct sge_eq *); 324 static u_int reclaim_tx_descs(struct sge_txq *, u_int); 325 static void tx_reclaim(void *, int); 326 static __be64 get_flit(struct sglist_seg *, int, int); 327 static int handle_sge_egr_update(struct sge_iq *, const struct rss_header *, 328 struct mbuf *); 329 static int handle_fw_msg(struct sge_iq *, const struct rss_header *, 330 struct mbuf *); 331 static int t4_handle_wrerr_rpl(struct adapter *, const __be64 *); 332 static void wrq_tx_drain(void *, int); 333 static void drain_wrq_wr_list(struct adapter *, struct sge_wrq *); 334 335 static int sysctl_bufsizes(SYSCTL_HANDLER_ARGS); 336 #ifdef RATELIMIT 337 #if defined(INET) || defined(INET6) 338 static inline u_int txpkt_eo_len16(u_int, u_int, u_int); 339 #endif 340 static int ethofld_fw4_ack(struct sge_iq *, const struct rss_header *, 341 struct mbuf *); 342 #endif 343 344 static counter_u64_t extfree_refs; 345 static counter_u64_t extfree_rels; 346 347 an_handler_t t4_an_handler; 348 fw_msg_handler_t t4_fw_msg_handler[NUM_FW6_TYPES]; 349 cpl_handler_t t4_cpl_handler[NUM_CPL_CMDS]; 350 cpl_handler_t set_tcb_rpl_handlers[NUM_CPL_COOKIES]; 351 cpl_handler_t l2t_write_rpl_handlers[NUM_CPL_COOKIES]; 352 cpl_handler_t act_open_rpl_handlers[NUM_CPL_COOKIES]; 353 cpl_handler_t abort_rpl_rss_handlers[NUM_CPL_COOKIES]; 354 cpl_handler_t fw4_ack_handlers[NUM_CPL_COOKIES]; 355 356 void 357 t4_register_an_handler(an_handler_t h) 358 { 359 uintptr_t *loc; 360 361 MPASS(h == NULL || t4_an_handler == NULL); 362 363 loc = (uintptr_t *)&t4_an_handler; 364 atomic_store_rel_ptr(loc, (uintptr_t)h); 365 } 366 367 void 368 t4_register_fw_msg_handler(int type, fw_msg_handler_t h) 369 { 370 uintptr_t *loc; 371 372 MPASS(type < nitems(t4_fw_msg_handler)); 373 MPASS(h == NULL || t4_fw_msg_handler[type] == NULL); 374 /* 375 * These are dispatched by the handler for FW{4|6}_CPL_MSG using the CPL 376 * handler dispatch table. Reject any attempt to install a handler for 377 * this subtype. 378 */ 379 MPASS(type != FW_TYPE_RSSCPL); 380 MPASS(type != FW6_TYPE_RSSCPL); 381 382 loc = (uintptr_t *)&t4_fw_msg_handler[type]; 383 atomic_store_rel_ptr(loc, (uintptr_t)h); 384 } 385 386 void 387 t4_register_cpl_handler(int opcode, cpl_handler_t h) 388 { 389 uintptr_t *loc; 390 391 MPASS(opcode < nitems(t4_cpl_handler)); 392 MPASS(h == NULL || t4_cpl_handler[opcode] == NULL); 393 394 loc = (uintptr_t *)&t4_cpl_handler[opcode]; 395 atomic_store_rel_ptr(loc, (uintptr_t)h); 396 } 397 398 static int 399 set_tcb_rpl_handler(struct sge_iq *iq, const struct rss_header *rss, 400 struct mbuf *m) 401 { 402 const struct cpl_set_tcb_rpl *cpl = (const void *)(rss + 1); 403 u_int tid; 404 int cookie; 405 406 MPASS(m == NULL); 407 408 tid = GET_TID(cpl); 409 if (is_hpftid(iq->adapter, tid) || is_ftid(iq->adapter, tid)) { 410 /* 411 * The return code for filter-write is put in the CPL cookie so 412 * we have to rely on the hardware tid (is_ftid) to determine 413 * that this is a response to a filter. 414 */ 415 cookie = CPL_COOKIE_FILTER; 416 } else { 417 cookie = G_COOKIE(cpl->cookie); 418 } 419 MPASS(cookie > CPL_COOKIE_RESERVED); 420 MPASS(cookie < nitems(set_tcb_rpl_handlers)); 421 422 return (set_tcb_rpl_handlers[cookie](iq, rss, m)); 423 } 424 425 static int 426 l2t_write_rpl_handler(struct sge_iq *iq, const struct rss_header *rss, 427 struct mbuf *m) 428 { 429 const struct cpl_l2t_write_rpl *rpl = (const void *)(rss + 1); 430 unsigned int cookie; 431 432 MPASS(m == NULL); 433 434 cookie = GET_TID(rpl) & F_SYNC_WR ? CPL_COOKIE_TOM : CPL_COOKIE_FILTER; 435 return (l2t_write_rpl_handlers[cookie](iq, rss, m)); 436 } 437 438 static int 439 act_open_rpl_handler(struct sge_iq *iq, const struct rss_header *rss, 440 struct mbuf *m) 441 { 442 const struct cpl_act_open_rpl *cpl = (const void *)(rss + 1); 443 u_int cookie = G_TID_COOKIE(G_AOPEN_ATID(be32toh(cpl->atid_status))); 444 445 MPASS(m == NULL); 446 MPASS(cookie != CPL_COOKIE_RESERVED); 447 448 return (act_open_rpl_handlers[cookie](iq, rss, m)); 449 } 450 451 static int 452 abort_rpl_rss_handler(struct sge_iq *iq, const struct rss_header *rss, 453 struct mbuf *m) 454 { 455 struct adapter *sc = iq->adapter; 456 u_int cookie; 457 458 MPASS(m == NULL); 459 if (is_hashfilter(sc)) 460 cookie = CPL_COOKIE_HASHFILTER; 461 else 462 cookie = CPL_COOKIE_TOM; 463 464 return (abort_rpl_rss_handlers[cookie](iq, rss, m)); 465 } 466 467 static int 468 fw4_ack_handler(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 469 { 470 struct adapter *sc = iq->adapter; 471 const struct cpl_fw4_ack *cpl = (const void *)(rss + 1); 472 unsigned int tid = G_CPL_FW4_ACK_FLOWID(be32toh(OPCODE_TID(cpl))); 473 u_int cookie; 474 475 MPASS(m == NULL); 476 if (is_etid(sc, tid)) 477 cookie = CPL_COOKIE_ETHOFLD; 478 else 479 cookie = CPL_COOKIE_TOM; 480 481 return (fw4_ack_handlers[cookie](iq, rss, m)); 482 } 483 484 static void 485 t4_init_shared_cpl_handlers(void) 486 { 487 488 t4_register_cpl_handler(CPL_SET_TCB_RPL, set_tcb_rpl_handler); 489 t4_register_cpl_handler(CPL_L2T_WRITE_RPL, l2t_write_rpl_handler); 490 t4_register_cpl_handler(CPL_ACT_OPEN_RPL, act_open_rpl_handler); 491 t4_register_cpl_handler(CPL_ABORT_RPL_RSS, abort_rpl_rss_handler); 492 t4_register_cpl_handler(CPL_FW4_ACK, fw4_ack_handler); 493 } 494 495 void 496 t4_register_shared_cpl_handler(int opcode, cpl_handler_t h, int cookie) 497 { 498 uintptr_t *loc; 499 500 MPASS(opcode < nitems(t4_cpl_handler)); 501 MPASS(cookie > CPL_COOKIE_RESERVED); 502 MPASS(cookie < NUM_CPL_COOKIES); 503 MPASS(t4_cpl_handler[opcode] != NULL); 504 505 switch (opcode) { 506 case CPL_SET_TCB_RPL: 507 loc = (uintptr_t *)&set_tcb_rpl_handlers[cookie]; 508 break; 509 case CPL_L2T_WRITE_RPL: 510 loc = (uintptr_t *)&l2t_write_rpl_handlers[cookie]; 511 break; 512 case CPL_ACT_OPEN_RPL: 513 loc = (uintptr_t *)&act_open_rpl_handlers[cookie]; 514 break; 515 case CPL_ABORT_RPL_RSS: 516 loc = (uintptr_t *)&abort_rpl_rss_handlers[cookie]; 517 break; 518 case CPL_FW4_ACK: 519 loc = (uintptr_t *)&fw4_ack_handlers[cookie]; 520 break; 521 default: 522 MPASS(0); 523 return; 524 } 525 MPASS(h == NULL || *loc == (uintptr_t)NULL); 526 atomic_store_rel_ptr(loc, (uintptr_t)h); 527 } 528 529 /* 530 * Called on MOD_LOAD. Validates and calculates the SGE tunables. 531 */ 532 void 533 t4_sge_modload(void) 534 { 535 536 if (fl_pktshift < 0 || fl_pktshift > 7) { 537 printf("Invalid hw.cxgbe.fl_pktshift value (%d)," 538 " using 0 instead.\n", fl_pktshift); 539 fl_pktshift = 0; 540 } 541 542 if (spg_len != 64 && spg_len != 128) { 543 int len; 544 545 #if defined(__i386__) || defined(__amd64__) 546 len = cpu_clflush_line_size > 64 ? 128 : 64; 547 #else 548 len = 64; 549 #endif 550 if (spg_len != -1) { 551 printf("Invalid hw.cxgbe.spg_len value (%d)," 552 " using %d instead.\n", spg_len, len); 553 } 554 spg_len = len; 555 } 556 557 if (cong_drop < -1 || cong_drop > 1) { 558 printf("Invalid hw.cxgbe.cong_drop value (%d)," 559 " using 0 instead.\n", cong_drop); 560 cong_drop = 0; 561 } 562 563 if (tscale != 1 && (tscale < 3 || tscale > 17)) { 564 printf("Invalid hw.cxgbe.tscale value (%d)," 565 " using 1 instead.\n", tscale); 566 tscale = 1; 567 } 568 569 if (largest_rx_cluster != MCLBYTES && 570 #if MJUMPAGESIZE != MCLBYTES 571 largest_rx_cluster != MJUMPAGESIZE && 572 #endif 573 largest_rx_cluster != MJUM9BYTES && 574 largest_rx_cluster != MJUM16BYTES) { 575 printf("Invalid hw.cxgbe.largest_rx_cluster value (%d)," 576 " using %d instead.\n", largest_rx_cluster, MJUM16BYTES); 577 largest_rx_cluster = MJUM16BYTES; 578 } 579 580 if (safest_rx_cluster != MCLBYTES && 581 #if MJUMPAGESIZE != MCLBYTES 582 safest_rx_cluster != MJUMPAGESIZE && 583 #endif 584 safest_rx_cluster != MJUM9BYTES && 585 safest_rx_cluster != MJUM16BYTES) { 586 printf("Invalid hw.cxgbe.safest_rx_cluster value (%d)," 587 " using %d instead.\n", safest_rx_cluster, MJUMPAGESIZE); 588 safest_rx_cluster = MJUMPAGESIZE; 589 } 590 591 extfree_refs = counter_u64_alloc(M_WAITOK); 592 extfree_rels = counter_u64_alloc(M_WAITOK); 593 pullups = counter_u64_alloc(M_WAITOK); 594 defrags = counter_u64_alloc(M_WAITOK); 595 counter_u64_zero(extfree_refs); 596 counter_u64_zero(extfree_rels); 597 counter_u64_zero(pullups); 598 counter_u64_zero(defrags); 599 600 t4_init_shared_cpl_handlers(); 601 t4_register_cpl_handler(CPL_FW4_MSG, handle_fw_msg); 602 t4_register_cpl_handler(CPL_FW6_MSG, handle_fw_msg); 603 t4_register_cpl_handler(CPL_SGE_EGR_UPDATE, handle_sge_egr_update); 604 #ifdef RATELIMIT 605 t4_register_shared_cpl_handler(CPL_FW4_ACK, ethofld_fw4_ack, 606 CPL_COOKIE_ETHOFLD); 607 #endif 608 t4_register_fw_msg_handler(FW6_TYPE_CMD_RPL, t4_handle_fw_rpl); 609 t4_register_fw_msg_handler(FW6_TYPE_WRERR_RPL, t4_handle_wrerr_rpl); 610 } 611 612 void 613 t4_sge_modunload(void) 614 { 615 616 counter_u64_free(extfree_refs); 617 counter_u64_free(extfree_rels); 618 counter_u64_free(pullups); 619 counter_u64_free(defrags); 620 } 621 622 uint64_t 623 t4_sge_extfree_refs(void) 624 { 625 uint64_t refs, rels; 626 627 rels = counter_u64_fetch(extfree_rels); 628 refs = counter_u64_fetch(extfree_refs); 629 630 return (refs - rels); 631 } 632 633 /* max 4096 */ 634 #define MAX_PACK_BOUNDARY 512 635 636 static inline void 637 setup_pad_and_pack_boundaries(struct adapter *sc) 638 { 639 uint32_t v, m; 640 int pad, pack, pad_shift; 641 642 pad_shift = chip_id(sc) > CHELSIO_T5 ? X_T6_INGPADBOUNDARY_SHIFT : 643 X_INGPADBOUNDARY_SHIFT; 644 pad = fl_pad; 645 if (fl_pad < (1 << pad_shift) || 646 fl_pad > (1 << (pad_shift + M_INGPADBOUNDARY)) || 647 !powerof2(fl_pad)) { 648 /* 649 * If there is any chance that we might use buffer packing and 650 * the chip is a T4, then pick 64 as the pad/pack boundary. Set 651 * it to the minimum allowed in all other cases. 652 */ 653 pad = is_t4(sc) && buffer_packing ? 64 : 1 << pad_shift; 654 655 /* 656 * For fl_pad = 0 we'll still write a reasonable value to the 657 * register but all the freelists will opt out of padding. 658 * We'll complain here only if the user tried to set it to a 659 * value greater than 0 that was invalid. 660 */ 661 if (fl_pad > 0) { 662 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pad value" 663 " (%d), using %d instead.\n", fl_pad, pad); 664 } 665 } 666 m = V_INGPADBOUNDARY(M_INGPADBOUNDARY); 667 v = V_INGPADBOUNDARY(ilog2(pad) - pad_shift); 668 t4_set_reg_field(sc, A_SGE_CONTROL, m, v); 669 670 if (is_t4(sc)) { 671 if (fl_pack != -1 && fl_pack != pad) { 672 /* Complain but carry on. */ 673 device_printf(sc->dev, "hw.cxgbe.fl_pack (%d) ignored," 674 " using %d instead.\n", fl_pack, pad); 675 } 676 return; 677 } 678 679 pack = fl_pack; 680 if (fl_pack < 16 || fl_pack == 32 || fl_pack > 4096 || 681 !powerof2(fl_pack)) { 682 if (sc->params.pci.mps > MAX_PACK_BOUNDARY) 683 pack = MAX_PACK_BOUNDARY; 684 else 685 pack = max(sc->params.pci.mps, CACHE_LINE_SIZE); 686 MPASS(powerof2(pack)); 687 if (pack < 16) 688 pack = 16; 689 if (pack == 32) 690 pack = 64; 691 if (pack > 4096) 692 pack = 4096; 693 if (fl_pack != -1) { 694 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pack value" 695 " (%d), using %d instead.\n", fl_pack, pack); 696 } 697 } 698 m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY); 699 if (pack == 16) 700 v = V_INGPACKBOUNDARY(0); 701 else 702 v = V_INGPACKBOUNDARY(ilog2(pack) - 5); 703 704 MPASS(!is_t4(sc)); /* T4 doesn't have SGE_CONTROL2 */ 705 t4_set_reg_field(sc, A_SGE_CONTROL2, m, v); 706 } 707 708 /* 709 * adap->params.vpd.cclk must be set up before this is called. 710 */ 711 void 712 t4_tweak_chip_settings(struct adapter *sc) 713 { 714 int i, reg; 715 uint32_t v, m; 716 int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200}; 717 int timer_max = M_TIMERVALUE0 * 1000 / sc->params.vpd.cclk; 718 int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */ 719 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 720 static int sw_buf_sizes[] = { 721 MCLBYTES, 722 #if MJUMPAGESIZE != MCLBYTES 723 MJUMPAGESIZE, 724 #endif 725 MJUM9BYTES, 726 MJUM16BYTES 727 }; 728 729 KASSERT(sc->flags & MASTER_PF, 730 ("%s: trying to change chip settings when not master.", __func__)); 731 732 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE; 733 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE | 734 V_EGRSTATUSPAGESIZE(spg_len == 128); 735 t4_set_reg_field(sc, A_SGE_CONTROL, m, v); 736 737 setup_pad_and_pack_boundaries(sc); 738 739 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) | 740 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) | 741 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) | 742 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) | 743 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) | 744 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) | 745 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) | 746 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10); 747 t4_write_reg(sc, A_SGE_HOST_PAGE_SIZE, v); 748 749 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0, 4096); 750 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE1, 65536); 751 reg = A_SGE_FL_BUFFER_SIZE2; 752 for (i = 0; i < nitems(sw_buf_sizes); i++) { 753 MPASS(reg <= A_SGE_FL_BUFFER_SIZE15); 754 t4_write_reg(sc, reg, sw_buf_sizes[i]); 755 reg += 4; 756 MPASS(reg <= A_SGE_FL_BUFFER_SIZE15); 757 t4_write_reg(sc, reg, sw_buf_sizes[i] - CL_METADATA_SIZE); 758 reg += 4; 759 } 760 761 v = V_THRESHOLD_0(intr_pktcount[0]) | V_THRESHOLD_1(intr_pktcount[1]) | 762 V_THRESHOLD_2(intr_pktcount[2]) | V_THRESHOLD_3(intr_pktcount[3]); 763 t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD, v); 764 765 KASSERT(intr_timer[0] <= timer_max, 766 ("%s: not a single usable timer (%d, %d)", __func__, intr_timer[0], 767 timer_max)); 768 for (i = 1; i < nitems(intr_timer); i++) { 769 KASSERT(intr_timer[i] >= intr_timer[i - 1], 770 ("%s: timers not listed in increasing order (%d)", 771 __func__, i)); 772 773 while (intr_timer[i] > timer_max) { 774 if (i == nitems(intr_timer) - 1) { 775 intr_timer[i] = timer_max; 776 break; 777 } 778 intr_timer[i] += intr_timer[i - 1]; 779 intr_timer[i] /= 2; 780 } 781 } 782 783 v = V_TIMERVALUE0(us_to_core_ticks(sc, intr_timer[0])) | 784 V_TIMERVALUE1(us_to_core_ticks(sc, intr_timer[1])); 785 t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1, v); 786 v = V_TIMERVALUE2(us_to_core_ticks(sc, intr_timer[2])) | 787 V_TIMERVALUE3(us_to_core_ticks(sc, intr_timer[3])); 788 t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3, v); 789 v = V_TIMERVALUE4(us_to_core_ticks(sc, intr_timer[4])) | 790 V_TIMERVALUE5(us_to_core_ticks(sc, intr_timer[5])); 791 t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5, v); 792 793 if (chip_id(sc) >= CHELSIO_T6) { 794 m = V_TSCALE(M_TSCALE); 795 if (tscale == 1) 796 v = 0; 797 else 798 v = V_TSCALE(tscale - 2); 799 t4_set_reg_field(sc, A_SGE_ITP_CONTROL, m, v); 800 801 if (sc->debug_flags & DF_DISABLE_TCB_CACHE) { 802 m = V_RDTHRESHOLD(M_RDTHRESHOLD) | F_WRTHRTHRESHEN | 803 V_WRTHRTHRESH(M_WRTHRTHRESH); 804 t4_tp_pio_read(sc, &v, 1, A_TP_CMM_CONFIG, 1); 805 v &= ~m; 806 v |= V_RDTHRESHOLD(1) | F_WRTHRTHRESHEN | 807 V_WRTHRTHRESH(16); 808 t4_tp_pio_write(sc, &v, 1, A_TP_CMM_CONFIG, 1); 809 } 810 } 811 812 /* 4K, 16K, 64K, 256K DDP "page sizes" for TDDP */ 813 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 814 t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, v); 815 816 /* 817 * 4K, 8K, 16K, 64K DDP "page sizes" for iSCSI DDP. These have been 818 * chosen with MAXPHYS = 128K in mind. The largest DDP buffer that we 819 * may have to deal with is MAXPHYS + 1 page. 820 */ 821 v = V_HPZ0(0) | V_HPZ1(1) | V_HPZ2(2) | V_HPZ3(4); 822 t4_write_reg(sc, A_ULP_RX_ISCSI_PSZ, v); 823 824 /* We use multiple DDP page sizes both in plain-TOE and ISCSI modes. */ 825 m = v = F_TDDPTAGTCB | F_ISCSITAGTCB; 826 t4_set_reg_field(sc, A_ULP_RX_CTL, m, v); 827 828 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 829 F_RESETDDPOFFSET; 830 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 831 t4_set_reg_field(sc, A_TP_PARA_REG5, m, v); 832 } 833 834 /* 835 * SGE wants the buffer to be at least 64B and then a multiple of 16. Its 836 * address mut be 16B aligned. If padding is in use the buffer's start and end 837 * need to be aligned to the pad boundary as well. We'll just make sure that 838 * the size is a multiple of the pad boundary here, it is up to the buffer 839 * allocation code to make sure the start of the buffer is aligned. 840 */ 841 static inline int 842 hwsz_ok(struct adapter *sc, int hwsz) 843 { 844 int mask = fl_pad ? sc->params.sge.pad_boundary - 1 : 16 - 1; 845 846 return (hwsz >= 64 && (hwsz & mask) == 0); 847 } 848 849 /* 850 * Initialize the rx buffer sizes and figure out which zones the buffers will 851 * be allocated from. 852 */ 853 void 854 t4_init_rx_buf_info(struct adapter *sc) 855 { 856 struct sge *s = &sc->sge; 857 struct sge_params *sp = &sc->params.sge; 858 int i, j, n; 859 static int sw_buf_sizes[] = { /* Sorted by size */ 860 MCLBYTES, 861 #if MJUMPAGESIZE != MCLBYTES 862 MJUMPAGESIZE, 863 #endif 864 MJUM9BYTES, 865 MJUM16BYTES 866 }; 867 struct rx_buf_info *rxb; 868 869 s->safe_zidx = -1; 870 rxb = &s->rx_buf_info[0]; 871 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) { 872 rxb->size1 = sw_buf_sizes[i]; 873 rxb->zone = m_getzone(rxb->size1); 874 rxb->type = m_gettype(rxb->size1); 875 rxb->size2 = 0; 876 rxb->hwidx1 = -1; 877 rxb->hwidx2 = -1; 878 for (j = 0; j < SGE_FLBUF_SIZES; j++) { 879 int hwsize = sp->sge_fl_buffer_size[j]; 880 881 if (!hwsz_ok(sc, hwsize)) 882 continue; 883 884 /* hwidx for size1 */ 885 if (rxb->hwidx1 == -1 && rxb->size1 == hwsize) 886 rxb->hwidx1 = j; 887 888 /* hwidx for size2 (buffer packing) */ 889 if (rxb->size1 - CL_METADATA_SIZE < hwsize) 890 continue; 891 n = rxb->size1 - hwsize - CL_METADATA_SIZE; 892 if (n == 0) { 893 rxb->hwidx2 = j; 894 rxb->size2 = hwsize; 895 break; /* stop looking */ 896 } 897 if (rxb->hwidx2 != -1) { 898 if (n < sp->sge_fl_buffer_size[rxb->hwidx2] - 899 hwsize - CL_METADATA_SIZE) { 900 rxb->hwidx2 = j; 901 rxb->size2 = hwsize; 902 } 903 } else if (n <= 2 * CL_METADATA_SIZE) { 904 rxb->hwidx2 = j; 905 rxb->size2 = hwsize; 906 } 907 } 908 if (rxb->hwidx2 != -1) 909 sc->flags |= BUF_PACKING_OK; 910 if (s->safe_zidx == -1 && rxb->size1 == safest_rx_cluster) 911 s->safe_zidx = i; 912 } 913 } 914 915 /* 916 * Verify some basic SGE settings for the PF and VF driver, and other 917 * miscellaneous settings for the PF driver. 918 */ 919 int 920 t4_verify_chip_settings(struct adapter *sc) 921 { 922 struct sge_params *sp = &sc->params.sge; 923 uint32_t m, v, r; 924 int rc = 0; 925 const uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 926 927 m = F_RXPKTCPLMODE; 928 v = F_RXPKTCPLMODE; 929 r = sp->sge_control; 930 if ((r & m) != v) { 931 device_printf(sc->dev, "invalid SGE_CONTROL(0x%x)\n", r); 932 rc = EINVAL; 933 } 934 935 /* 936 * If this changes then every single use of PAGE_SHIFT in the driver 937 * needs to be carefully reviewed for PAGE_SHIFT vs sp->page_shift. 938 */ 939 if (sp->page_shift != PAGE_SHIFT) { 940 device_printf(sc->dev, "invalid SGE_HOST_PAGE_SIZE(0x%x)\n", r); 941 rc = EINVAL; 942 } 943 944 if (sc->flags & IS_VF) 945 return (0); 946 947 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 948 r = t4_read_reg(sc, A_ULP_RX_TDDP_PSZ); 949 if (r != v) { 950 device_printf(sc->dev, "invalid ULP_RX_TDDP_PSZ(0x%x)\n", r); 951 if (sc->vres.ddp.size != 0) 952 rc = EINVAL; 953 } 954 955 m = v = F_TDDPTAGTCB; 956 r = t4_read_reg(sc, A_ULP_RX_CTL); 957 if ((r & m) != v) { 958 device_printf(sc->dev, "invalid ULP_RX_CTL(0x%x)\n", r); 959 if (sc->vres.ddp.size != 0) 960 rc = EINVAL; 961 } 962 963 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 964 F_RESETDDPOFFSET; 965 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 966 r = t4_read_reg(sc, A_TP_PARA_REG5); 967 if ((r & m) != v) { 968 device_printf(sc->dev, "invalid TP_PARA_REG5(0x%x)\n", r); 969 if (sc->vres.ddp.size != 0) 970 rc = EINVAL; 971 } 972 973 return (rc); 974 } 975 976 int 977 t4_create_dma_tag(struct adapter *sc) 978 { 979 int rc; 980 981 rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0, 982 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE, 983 BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL, 984 NULL, &sc->dmat); 985 if (rc != 0) { 986 device_printf(sc->dev, 987 "failed to create main DMA tag: %d\n", rc); 988 } 989 990 return (rc); 991 } 992 993 void 994 t4_sge_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx, 995 struct sysctl_oid_list *children) 996 { 997 struct sge_params *sp = &sc->params.sge; 998 999 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "buffer_sizes", 1000 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 1001 sysctl_bufsizes, "A", "freelist buffer sizes"); 1002 1003 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pktshift", CTLFLAG_RD, 1004 NULL, sp->fl_pktshift, "payload DMA offset in rx buffer (bytes)"); 1005 1006 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pad", CTLFLAG_RD, 1007 NULL, sp->pad_boundary, "payload pad boundary (bytes)"); 1008 1009 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "spg_len", CTLFLAG_RD, 1010 NULL, sp->spg_len, "status page size (bytes)"); 1011 1012 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_drop", CTLFLAG_RD, 1013 NULL, cong_drop, "congestion drop setting"); 1014 1015 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pack", CTLFLAG_RD, 1016 NULL, sp->pack_boundary, "payload pack boundary (bytes)"); 1017 } 1018 1019 int 1020 t4_destroy_dma_tag(struct adapter *sc) 1021 { 1022 if (sc->dmat) 1023 bus_dma_tag_destroy(sc->dmat); 1024 1025 return (0); 1026 } 1027 1028 /* 1029 * Allocate and initialize the firmware event queue, control queues, and special 1030 * purpose rx queues owned by the adapter. 1031 * 1032 * Returns errno on failure. Resources allocated up to that point may still be 1033 * allocated. Caller is responsible for cleanup in case this function fails. 1034 */ 1035 int 1036 t4_setup_adapter_queues(struct adapter *sc) 1037 { 1038 int rc, i; 1039 1040 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 1041 1042 /* 1043 * Firmware event queue 1044 */ 1045 rc = alloc_fwq(sc); 1046 if (rc != 0) 1047 return (rc); 1048 1049 /* 1050 * That's all for the VF driver. 1051 */ 1052 if (sc->flags & IS_VF) 1053 return (rc); 1054 1055 /* 1056 * XXX: General purpose rx queues, one per port. 1057 */ 1058 1059 /* 1060 * Control queues, one per port. 1061 */ 1062 for_each_port(sc, i) { 1063 rc = alloc_ctrlq(sc, i); 1064 if (rc != 0) 1065 return (rc); 1066 } 1067 1068 return (rc); 1069 } 1070 1071 /* 1072 * Idempotent 1073 */ 1074 int 1075 t4_teardown_adapter_queues(struct adapter *sc) 1076 { 1077 int i; 1078 1079 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 1080 1081 if (!(sc->flags & IS_VF)) { 1082 for_each_port(sc, i) 1083 free_ctrlq(sc, i); 1084 } 1085 free_fwq(sc); 1086 1087 return (0); 1088 } 1089 1090 /* Maximum payload that could arrive with a single iq descriptor. */ 1091 static inline int 1092 max_rx_payload(struct adapter *sc, struct ifnet *ifp, const bool ofld) 1093 { 1094 int maxp; 1095 1096 /* large enough even when hw VLAN extraction is disabled */ 1097 maxp = sc->params.sge.fl_pktshift + ETHER_HDR_LEN + 1098 ETHER_VLAN_ENCAP_LEN + ifp->if_mtu; 1099 if (ofld && sc->tt.tls && sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS && 1100 maxp < sc->params.tp.max_rx_pdu) 1101 maxp = sc->params.tp.max_rx_pdu; 1102 return (maxp); 1103 } 1104 1105 int 1106 t4_setup_vi_queues(struct vi_info *vi) 1107 { 1108 int rc = 0, i, intr_idx; 1109 struct sge_rxq *rxq; 1110 struct sge_txq *txq; 1111 #ifdef TCP_OFFLOAD 1112 struct sge_ofld_rxq *ofld_rxq; 1113 #endif 1114 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1115 struct sge_ofld_txq *ofld_txq; 1116 #endif 1117 #ifdef DEV_NETMAP 1118 int saved_idx, iqidx; 1119 struct sge_nm_rxq *nm_rxq; 1120 struct sge_nm_txq *nm_txq; 1121 #endif 1122 struct adapter *sc = vi->adapter; 1123 struct ifnet *ifp = vi->ifp; 1124 int maxp; 1125 1126 /* Interrupt vector to start from (when using multiple vectors) */ 1127 intr_idx = vi->first_intr; 1128 1129 #ifdef DEV_NETMAP 1130 saved_idx = intr_idx; 1131 if (ifp->if_capabilities & IFCAP_NETMAP) { 1132 1133 /* netmap is supported with direct interrupts only. */ 1134 MPASS(!forwarding_intr_to_fwq(sc)); 1135 MPASS(vi->first_intr >= 0); 1136 1137 /* 1138 * We don't have buffers to back the netmap rx queues 1139 * right now so we create the queues in a way that 1140 * doesn't set off any congestion signal in the chip. 1141 */ 1142 for_each_nm_rxq(vi, i, nm_rxq) { 1143 rc = alloc_nm_rxq(vi, nm_rxq, intr_idx, i); 1144 if (rc != 0) 1145 goto done; 1146 intr_idx++; 1147 } 1148 1149 for_each_nm_txq(vi, i, nm_txq) { 1150 iqidx = vi->first_nm_rxq + (i % vi->nnmrxq); 1151 rc = alloc_nm_txq(vi, nm_txq, iqidx, i); 1152 if (rc != 0) 1153 goto done; 1154 } 1155 } 1156 1157 /* Normal rx queues and netmap rx queues share the same interrupts. */ 1158 intr_idx = saved_idx; 1159 #endif 1160 1161 /* 1162 * Allocate rx queues first because a default iqid is required when 1163 * creating a tx queue. 1164 */ 1165 maxp = max_rx_payload(sc, ifp, false); 1166 for_each_rxq(vi, i, rxq) { 1167 rc = alloc_rxq(vi, rxq, i, intr_idx, maxp); 1168 if (rc != 0) 1169 goto done; 1170 if (!forwarding_intr_to_fwq(sc)) 1171 intr_idx++; 1172 } 1173 #ifdef DEV_NETMAP 1174 if (ifp->if_capabilities & IFCAP_NETMAP) 1175 intr_idx = saved_idx + max(vi->nrxq, vi->nnmrxq); 1176 #endif 1177 #ifdef TCP_OFFLOAD 1178 maxp = max_rx_payload(sc, ifp, true); 1179 for_each_ofld_rxq(vi, i, ofld_rxq) { 1180 rc = alloc_ofld_rxq(vi, ofld_rxq, i, intr_idx, maxp); 1181 if (rc != 0) 1182 goto done; 1183 if (!forwarding_intr_to_fwq(sc)) 1184 intr_idx++; 1185 } 1186 #endif 1187 1188 /* 1189 * Now the tx queues. 1190 */ 1191 for_each_txq(vi, i, txq) { 1192 rc = alloc_txq(vi, txq, i); 1193 if (rc != 0) 1194 goto done; 1195 } 1196 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1197 for_each_ofld_txq(vi, i, ofld_txq) { 1198 rc = alloc_ofld_txq(vi, ofld_txq, i); 1199 if (rc != 0) 1200 goto done; 1201 } 1202 #endif 1203 done: 1204 if (rc) 1205 t4_teardown_vi_queues(vi); 1206 1207 return (rc); 1208 } 1209 1210 /* 1211 * Idempotent 1212 */ 1213 int 1214 t4_teardown_vi_queues(struct vi_info *vi) 1215 { 1216 int i; 1217 struct sge_rxq *rxq; 1218 struct sge_txq *txq; 1219 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1220 struct sge_ofld_txq *ofld_txq; 1221 #endif 1222 #ifdef TCP_OFFLOAD 1223 struct sge_ofld_rxq *ofld_rxq; 1224 #endif 1225 #ifdef DEV_NETMAP 1226 struct sge_nm_rxq *nm_rxq; 1227 struct sge_nm_txq *nm_txq; 1228 #endif 1229 1230 #ifdef DEV_NETMAP 1231 if (vi->ifp->if_capabilities & IFCAP_NETMAP) { 1232 for_each_nm_txq(vi, i, nm_txq) { 1233 free_nm_txq(vi, nm_txq); 1234 } 1235 1236 for_each_nm_rxq(vi, i, nm_rxq) { 1237 free_nm_rxq(vi, nm_rxq); 1238 } 1239 } 1240 #endif 1241 1242 /* 1243 * Take down all the tx queues first, as they reference the rx queues 1244 * (for egress updates, etc.). 1245 */ 1246 1247 for_each_txq(vi, i, txq) { 1248 free_txq(vi, txq); 1249 } 1250 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1251 for_each_ofld_txq(vi, i, ofld_txq) { 1252 free_ofld_txq(vi, ofld_txq); 1253 } 1254 #endif 1255 1256 /* 1257 * Then take down the rx queues. 1258 */ 1259 1260 for_each_rxq(vi, i, rxq) { 1261 free_rxq(vi, rxq); 1262 } 1263 #ifdef TCP_OFFLOAD 1264 for_each_ofld_rxq(vi, i, ofld_rxq) { 1265 free_ofld_rxq(vi, ofld_rxq); 1266 } 1267 #endif 1268 1269 return (0); 1270 } 1271 1272 /* 1273 * Interrupt handler when the driver is using only 1 interrupt. This is a very 1274 * unusual scenario. 1275 * 1276 * a) Deals with errors, if any. 1277 * b) Services firmware event queue, which is taking interrupts for all other 1278 * queues. 1279 */ 1280 void 1281 t4_intr_all(void *arg) 1282 { 1283 struct adapter *sc = arg; 1284 struct sge_iq *fwq = &sc->sge.fwq; 1285 1286 MPASS(sc->intr_count == 1); 1287 1288 if (sc->intr_type == INTR_INTX) 1289 t4_write_reg(sc, MYPF_REG(A_PCIE_PF_CLI), 0); 1290 1291 t4_intr_err(arg); 1292 t4_intr_evt(fwq); 1293 } 1294 1295 /* 1296 * Interrupt handler for errors (installed directly when multiple interrupts are 1297 * being used, or called by t4_intr_all). 1298 */ 1299 void 1300 t4_intr_err(void *arg) 1301 { 1302 struct adapter *sc = arg; 1303 uint32_t v; 1304 const bool verbose = (sc->debug_flags & DF_VERBOSE_SLOWINTR) != 0; 1305 1306 if (sc->flags & ADAP_ERR) 1307 return; 1308 1309 v = t4_read_reg(sc, MYPF_REG(A_PL_PF_INT_CAUSE)); 1310 if (v & F_PFSW) { 1311 sc->swintr++; 1312 t4_write_reg(sc, MYPF_REG(A_PL_PF_INT_CAUSE), v); 1313 } 1314 1315 t4_slow_intr_handler(sc, verbose); 1316 } 1317 1318 /* 1319 * Interrupt handler for iq-only queues. The firmware event queue is the only 1320 * such queue right now. 1321 */ 1322 void 1323 t4_intr_evt(void *arg) 1324 { 1325 struct sge_iq *iq = arg; 1326 1327 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 1328 service_iq(iq, 0); 1329 (void) atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 1330 } 1331 } 1332 1333 /* 1334 * Interrupt handler for iq+fl queues. 1335 */ 1336 void 1337 t4_intr(void *arg) 1338 { 1339 struct sge_iq *iq = arg; 1340 1341 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 1342 service_iq_fl(iq, 0); 1343 (void) atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 1344 } 1345 } 1346 1347 #ifdef DEV_NETMAP 1348 /* 1349 * Interrupt handler for netmap rx queues. 1350 */ 1351 void 1352 t4_nm_intr(void *arg) 1353 { 1354 struct sge_nm_rxq *nm_rxq = arg; 1355 1356 if (atomic_cmpset_int(&nm_rxq->nm_state, NM_ON, NM_BUSY)) { 1357 service_nm_rxq(nm_rxq); 1358 (void) atomic_cmpset_int(&nm_rxq->nm_state, NM_BUSY, NM_ON); 1359 } 1360 } 1361 1362 /* 1363 * Interrupt handler for vectors shared between NIC and netmap rx queues. 1364 */ 1365 void 1366 t4_vi_intr(void *arg) 1367 { 1368 struct irq *irq = arg; 1369 1370 MPASS(irq->nm_rxq != NULL); 1371 t4_nm_intr(irq->nm_rxq); 1372 1373 MPASS(irq->rxq != NULL); 1374 t4_intr(irq->rxq); 1375 } 1376 #endif 1377 1378 /* 1379 * Deals with interrupts on an iq-only (no freelist) queue. 1380 */ 1381 static int 1382 service_iq(struct sge_iq *iq, int budget) 1383 { 1384 struct sge_iq *q; 1385 struct adapter *sc = iq->adapter; 1386 struct iq_desc *d = &iq->desc[iq->cidx]; 1387 int ndescs = 0, limit; 1388 int rsp_type; 1389 uint32_t lq; 1390 STAILQ_HEAD(, sge_iq) iql = STAILQ_HEAD_INITIALIZER(iql); 1391 1392 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq)); 1393 KASSERT((iq->flags & IQ_HAS_FL) == 0, 1394 ("%s: called for iq %p with fl (iq->flags 0x%x)", __func__, iq, 1395 iq->flags)); 1396 MPASS((iq->flags & IQ_ADJ_CREDIT) == 0); 1397 MPASS((iq->flags & IQ_LRO_ENABLED) == 0); 1398 1399 limit = budget ? budget : iq->qsize / 16; 1400 1401 /* 1402 * We always come back and check the descriptor ring for new indirect 1403 * interrupts and other responses after running a single handler. 1404 */ 1405 for (;;) { 1406 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) { 1407 1408 rmb(); 1409 1410 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen); 1411 lq = be32toh(d->rsp.pldbuflen_qid); 1412 1413 switch (rsp_type) { 1414 case X_RSPD_TYPE_FLBUF: 1415 panic("%s: data for an iq (%p) with no freelist", 1416 __func__, iq); 1417 1418 /* NOTREACHED */ 1419 1420 case X_RSPD_TYPE_CPL: 1421 KASSERT(d->rss.opcode < NUM_CPL_CMDS, 1422 ("%s: bad opcode %02x.", __func__, 1423 d->rss.opcode)); 1424 t4_cpl_handler[d->rss.opcode](iq, &d->rss, NULL); 1425 break; 1426 1427 case X_RSPD_TYPE_INTR: 1428 /* 1429 * There are 1K interrupt-capable queues (qids 0 1430 * through 1023). A response type indicating a 1431 * forwarded interrupt with a qid >= 1K is an 1432 * iWARP async notification. 1433 */ 1434 if (__predict_true(lq >= 1024)) { 1435 t4_an_handler(iq, &d->rsp); 1436 break; 1437 } 1438 1439 q = sc->sge.iqmap[lq - sc->sge.iq_start - 1440 sc->sge.iq_base]; 1441 if (atomic_cmpset_int(&q->state, IQS_IDLE, 1442 IQS_BUSY)) { 1443 if (service_iq_fl(q, q->qsize / 16) == 0) { 1444 (void) atomic_cmpset_int(&q->state, 1445 IQS_BUSY, IQS_IDLE); 1446 } else { 1447 STAILQ_INSERT_TAIL(&iql, q, 1448 link); 1449 } 1450 } 1451 break; 1452 1453 default: 1454 KASSERT(0, 1455 ("%s: illegal response type %d on iq %p", 1456 __func__, rsp_type, iq)); 1457 log(LOG_ERR, 1458 "%s: illegal response type %d on iq %p", 1459 device_get_nameunit(sc->dev), rsp_type, iq); 1460 break; 1461 } 1462 1463 d++; 1464 if (__predict_false(++iq->cidx == iq->sidx)) { 1465 iq->cidx = 0; 1466 iq->gen ^= F_RSPD_GEN; 1467 d = &iq->desc[0]; 1468 } 1469 if (__predict_false(++ndescs == limit)) { 1470 t4_write_reg(sc, sc->sge_gts_reg, 1471 V_CIDXINC(ndescs) | 1472 V_INGRESSQID(iq->cntxt_id) | 1473 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); 1474 ndescs = 0; 1475 1476 if (budget) { 1477 return (EINPROGRESS); 1478 } 1479 } 1480 } 1481 1482 if (STAILQ_EMPTY(&iql)) 1483 break; 1484 1485 /* 1486 * Process the head only, and send it to the back of the list if 1487 * it's still not done. 1488 */ 1489 q = STAILQ_FIRST(&iql); 1490 STAILQ_REMOVE_HEAD(&iql, link); 1491 if (service_iq_fl(q, q->qsize / 8) == 0) 1492 (void) atomic_cmpset_int(&q->state, IQS_BUSY, IQS_IDLE); 1493 else 1494 STAILQ_INSERT_TAIL(&iql, q, link); 1495 } 1496 1497 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) | 1498 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params)); 1499 1500 return (0); 1501 } 1502 1503 #if defined(INET) || defined(INET6) 1504 static inline int 1505 sort_before_lro(struct lro_ctrl *lro) 1506 { 1507 1508 return (lro->lro_mbuf_max != 0); 1509 } 1510 #endif 1511 1512 static inline uint64_t 1513 last_flit_to_ns(struct adapter *sc, uint64_t lf) 1514 { 1515 uint64_t n = be64toh(lf) & 0xfffffffffffffff; /* 60b, not 64b. */ 1516 1517 if (n > UINT64_MAX / 1000000) 1518 return (n / sc->params.vpd.cclk * 1000000); 1519 else 1520 return (n * 1000000 / sc->params.vpd.cclk); 1521 } 1522 1523 static inline void 1524 move_to_next_rxbuf(struct sge_fl *fl) 1525 { 1526 1527 fl->rx_offset = 0; 1528 if (__predict_false((++fl->cidx & 7) == 0)) { 1529 uint16_t cidx = fl->cidx >> 3; 1530 1531 if (__predict_false(cidx == fl->sidx)) 1532 fl->cidx = cidx = 0; 1533 fl->hw_cidx = cidx; 1534 } 1535 } 1536 1537 /* 1538 * Deals with interrupts on an iq+fl queue. 1539 */ 1540 static int 1541 service_iq_fl(struct sge_iq *iq, int budget) 1542 { 1543 struct sge_rxq *rxq = iq_to_rxq(iq); 1544 struct sge_fl *fl; 1545 struct adapter *sc = iq->adapter; 1546 struct iq_desc *d = &iq->desc[iq->cidx]; 1547 int ndescs, limit; 1548 int rsp_type, starved; 1549 uint32_t lq; 1550 uint16_t fl_hw_cidx; 1551 struct mbuf *m0; 1552 #if defined(INET) || defined(INET6) 1553 const struct timeval lro_timeout = {0, sc->lro_timeout}; 1554 struct lro_ctrl *lro = &rxq->lro; 1555 #endif 1556 1557 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq)); 1558 MPASS(iq->flags & IQ_HAS_FL); 1559 1560 ndescs = 0; 1561 #if defined(INET) || defined(INET6) 1562 if (iq->flags & IQ_ADJ_CREDIT) { 1563 MPASS(sort_before_lro(lro)); 1564 iq->flags &= ~IQ_ADJ_CREDIT; 1565 if ((d->rsp.u.type_gen & F_RSPD_GEN) != iq->gen) { 1566 tcp_lro_flush_all(lro); 1567 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(1) | 1568 V_INGRESSQID((u32)iq->cntxt_id) | 1569 V_SEINTARM(iq->intr_params)); 1570 return (0); 1571 } 1572 ndescs = 1; 1573 } 1574 #else 1575 MPASS((iq->flags & IQ_ADJ_CREDIT) == 0); 1576 #endif 1577 1578 limit = budget ? budget : iq->qsize / 16; 1579 fl = &rxq->fl; 1580 fl_hw_cidx = fl->hw_cidx; /* stable snapshot */ 1581 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) { 1582 1583 rmb(); 1584 1585 m0 = NULL; 1586 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen); 1587 lq = be32toh(d->rsp.pldbuflen_qid); 1588 1589 switch (rsp_type) { 1590 case X_RSPD_TYPE_FLBUF: 1591 if (lq & F_RSPD_NEWBUF) { 1592 if (fl->rx_offset > 0) 1593 move_to_next_rxbuf(fl); 1594 lq = G_RSPD_LEN(lq); 1595 } 1596 if (IDXDIFF(fl->hw_cidx, fl_hw_cidx, fl->sidx) > 4) { 1597 FL_LOCK(fl); 1598 refill_fl(sc, fl, 64); 1599 FL_UNLOCK(fl); 1600 fl_hw_cidx = fl->hw_cidx; 1601 } 1602 1603 if (d->rss.opcode == CPL_RX_PKT) { 1604 if (__predict_true(eth_rx(sc, rxq, d, lq) == 0)) 1605 break; 1606 goto out; 1607 } 1608 m0 = get_fl_payload(sc, fl, lq); 1609 if (__predict_false(m0 == NULL)) 1610 goto out; 1611 1612 /* fall through */ 1613 1614 case X_RSPD_TYPE_CPL: 1615 KASSERT(d->rss.opcode < NUM_CPL_CMDS, 1616 ("%s: bad opcode %02x.", __func__, d->rss.opcode)); 1617 t4_cpl_handler[d->rss.opcode](iq, &d->rss, m0); 1618 break; 1619 1620 case X_RSPD_TYPE_INTR: 1621 1622 /* 1623 * There are 1K interrupt-capable queues (qids 0 1624 * through 1023). A response type indicating a 1625 * forwarded interrupt with a qid >= 1K is an 1626 * iWARP async notification. That is the only 1627 * acceptable indirect interrupt on this queue. 1628 */ 1629 if (__predict_false(lq < 1024)) { 1630 panic("%s: indirect interrupt on iq_fl %p " 1631 "with qid %u", __func__, iq, lq); 1632 } 1633 1634 t4_an_handler(iq, &d->rsp); 1635 break; 1636 1637 default: 1638 KASSERT(0, ("%s: illegal response type %d on iq %p", 1639 __func__, rsp_type, iq)); 1640 log(LOG_ERR, "%s: illegal response type %d on iq %p", 1641 device_get_nameunit(sc->dev), rsp_type, iq); 1642 break; 1643 } 1644 1645 d++; 1646 if (__predict_false(++iq->cidx == iq->sidx)) { 1647 iq->cidx = 0; 1648 iq->gen ^= F_RSPD_GEN; 1649 d = &iq->desc[0]; 1650 } 1651 if (__predict_false(++ndescs == limit)) { 1652 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) | 1653 V_INGRESSQID(iq->cntxt_id) | 1654 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); 1655 1656 #if defined(INET) || defined(INET6) 1657 if (iq->flags & IQ_LRO_ENABLED && 1658 !sort_before_lro(lro) && 1659 sc->lro_timeout != 0) { 1660 tcp_lro_flush_inactive(lro, &lro_timeout); 1661 } 1662 #endif 1663 if (budget) 1664 return (EINPROGRESS); 1665 ndescs = 0; 1666 } 1667 } 1668 out: 1669 #if defined(INET) || defined(INET6) 1670 if (iq->flags & IQ_LRO_ENABLED) { 1671 if (ndescs > 0 && lro->lro_mbuf_count > 8) { 1672 MPASS(sort_before_lro(lro)); 1673 /* hold back one credit and don't flush LRO state */ 1674 iq->flags |= IQ_ADJ_CREDIT; 1675 ndescs--; 1676 } else { 1677 tcp_lro_flush_all(lro); 1678 } 1679 } 1680 #endif 1681 1682 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) | 1683 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params)); 1684 1685 FL_LOCK(fl); 1686 starved = refill_fl(sc, fl, 64); 1687 FL_UNLOCK(fl); 1688 if (__predict_false(starved != 0)) 1689 add_fl_to_sfl(sc, fl); 1690 1691 return (0); 1692 } 1693 1694 static inline struct cluster_metadata * 1695 cl_metadata(struct fl_sdesc *sd) 1696 { 1697 1698 return ((void *)(sd->cl + sd->moff)); 1699 } 1700 1701 static void 1702 rxb_free(struct mbuf *m) 1703 { 1704 struct cluster_metadata *clm = m->m_ext.ext_arg1; 1705 1706 uma_zfree(clm->zone, clm->cl); 1707 counter_u64_add(extfree_rels, 1); 1708 } 1709 1710 /* 1711 * The mbuf returned comes from zone_muf and carries the payload in one of these 1712 * ways 1713 * a) complete frame inside the mbuf 1714 * b) m_cljset (for clusters without metadata) 1715 * d) m_extaddref (cluster with metadata) 1716 */ 1717 static struct mbuf * 1718 get_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset, 1719 int remaining) 1720 { 1721 struct mbuf *m; 1722 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 1723 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[sd->zidx]; 1724 struct cluster_metadata *clm; 1725 int len, blen; 1726 caddr_t payload; 1727 1728 if (fl->flags & FL_BUF_PACKING) { 1729 u_int l, pad; 1730 1731 blen = rxb->size2 - fl->rx_offset; /* max possible in this buf */ 1732 len = min(remaining, blen); 1733 payload = sd->cl + fl->rx_offset; 1734 1735 l = fr_offset + len; 1736 pad = roundup2(l, fl->buf_boundary) - l; 1737 if (fl->rx_offset + len + pad < rxb->size2) 1738 blen = len + pad; 1739 MPASS(fl->rx_offset + blen <= rxb->size2); 1740 } else { 1741 MPASS(fl->rx_offset == 0); /* not packing */ 1742 blen = rxb->size1; 1743 len = min(remaining, blen); 1744 payload = sd->cl; 1745 } 1746 1747 if (fr_offset == 0) { 1748 m = m_gethdr(M_NOWAIT, MT_DATA); 1749 if (__predict_false(m == NULL)) 1750 return (NULL); 1751 m->m_pkthdr.len = remaining; 1752 } else { 1753 m = m_get(M_NOWAIT, MT_DATA); 1754 if (__predict_false(m == NULL)) 1755 return (NULL); 1756 } 1757 m->m_len = len; 1758 kmsan_mark(payload, len, KMSAN_STATE_INITED); 1759 1760 if (sc->sc_do_rxcopy && len < RX_COPY_THRESHOLD) { 1761 /* copy data to mbuf */ 1762 bcopy(payload, mtod(m, caddr_t), len); 1763 if (fl->flags & FL_BUF_PACKING) { 1764 fl->rx_offset += blen; 1765 MPASS(fl->rx_offset <= rxb->size2); 1766 if (fl->rx_offset < rxb->size2) 1767 return (m); /* without advancing the cidx */ 1768 } 1769 } else if (fl->flags & FL_BUF_PACKING) { 1770 clm = cl_metadata(sd); 1771 if (sd->nmbuf++ == 0) { 1772 clm->refcount = 1; 1773 clm->zone = rxb->zone; 1774 clm->cl = sd->cl; 1775 counter_u64_add(extfree_refs, 1); 1776 } 1777 m_extaddref(m, payload, blen, &clm->refcount, rxb_free, clm, 1778 NULL); 1779 1780 fl->rx_offset += blen; 1781 MPASS(fl->rx_offset <= rxb->size2); 1782 if (fl->rx_offset < rxb->size2) 1783 return (m); /* without advancing the cidx */ 1784 } else { 1785 m_cljset(m, sd->cl, rxb->type); 1786 sd->cl = NULL; /* consumed, not a recycle candidate */ 1787 } 1788 1789 move_to_next_rxbuf(fl); 1790 1791 return (m); 1792 } 1793 1794 static struct mbuf * 1795 get_fl_payload(struct adapter *sc, struct sge_fl *fl, const u_int plen) 1796 { 1797 struct mbuf *m0, *m, **pnext; 1798 u_int remaining; 1799 1800 if (__predict_false(fl->flags & FL_BUF_RESUME)) { 1801 M_ASSERTPKTHDR(fl->m0); 1802 MPASS(fl->m0->m_pkthdr.len == plen); 1803 MPASS(fl->remaining < plen); 1804 1805 m0 = fl->m0; 1806 pnext = fl->pnext; 1807 remaining = fl->remaining; 1808 fl->flags &= ~FL_BUF_RESUME; 1809 goto get_segment; 1810 } 1811 1812 /* 1813 * Payload starts at rx_offset in the current hw buffer. Its length is 1814 * 'len' and it may span multiple hw buffers. 1815 */ 1816 1817 m0 = get_scatter_segment(sc, fl, 0, plen); 1818 if (m0 == NULL) 1819 return (NULL); 1820 remaining = plen - m0->m_len; 1821 pnext = &m0->m_next; 1822 while (remaining > 0) { 1823 get_segment: 1824 MPASS(fl->rx_offset == 0); 1825 m = get_scatter_segment(sc, fl, plen - remaining, remaining); 1826 if (__predict_false(m == NULL)) { 1827 fl->m0 = m0; 1828 fl->pnext = pnext; 1829 fl->remaining = remaining; 1830 fl->flags |= FL_BUF_RESUME; 1831 return (NULL); 1832 } 1833 *pnext = m; 1834 pnext = &m->m_next; 1835 remaining -= m->m_len; 1836 } 1837 *pnext = NULL; 1838 1839 M_ASSERTPKTHDR(m0); 1840 return (m0); 1841 } 1842 1843 static int 1844 skip_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset, 1845 int remaining) 1846 { 1847 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 1848 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[sd->zidx]; 1849 int len, blen; 1850 1851 if (fl->flags & FL_BUF_PACKING) { 1852 u_int l, pad; 1853 1854 blen = rxb->size2 - fl->rx_offset; /* max possible in this buf */ 1855 len = min(remaining, blen); 1856 1857 l = fr_offset + len; 1858 pad = roundup2(l, fl->buf_boundary) - l; 1859 if (fl->rx_offset + len + pad < rxb->size2) 1860 blen = len + pad; 1861 fl->rx_offset += blen; 1862 MPASS(fl->rx_offset <= rxb->size2); 1863 if (fl->rx_offset < rxb->size2) 1864 return (len); /* without advancing the cidx */ 1865 } else { 1866 MPASS(fl->rx_offset == 0); /* not packing */ 1867 blen = rxb->size1; 1868 len = min(remaining, blen); 1869 } 1870 move_to_next_rxbuf(fl); 1871 return (len); 1872 } 1873 1874 static inline void 1875 skip_fl_payload(struct adapter *sc, struct sge_fl *fl, int plen) 1876 { 1877 int remaining, fr_offset, len; 1878 1879 fr_offset = 0; 1880 remaining = plen; 1881 while (remaining > 0) { 1882 len = skip_scatter_segment(sc, fl, fr_offset, remaining); 1883 fr_offset += len; 1884 remaining -= len; 1885 } 1886 } 1887 1888 static inline int 1889 get_segment_len(struct adapter *sc, struct sge_fl *fl, int plen) 1890 { 1891 int len; 1892 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 1893 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[sd->zidx]; 1894 1895 if (fl->flags & FL_BUF_PACKING) 1896 len = rxb->size2 - fl->rx_offset; 1897 else 1898 len = rxb->size1; 1899 1900 return (min(plen, len)); 1901 } 1902 1903 static int 1904 eth_rx(struct adapter *sc, struct sge_rxq *rxq, const struct iq_desc *d, 1905 u_int plen) 1906 { 1907 struct mbuf *m0; 1908 struct ifnet *ifp = rxq->ifp; 1909 struct sge_fl *fl = &rxq->fl; 1910 struct vi_info *vi = ifp->if_softc; 1911 const struct cpl_rx_pkt *cpl; 1912 #if defined(INET) || defined(INET6) 1913 struct lro_ctrl *lro = &rxq->lro; 1914 #endif 1915 uint16_t err_vec, tnl_type, tnlhdr_len; 1916 static const int sw_hashtype[4][2] = { 1917 {M_HASHTYPE_NONE, M_HASHTYPE_NONE}, 1918 {M_HASHTYPE_RSS_IPV4, M_HASHTYPE_RSS_IPV6}, 1919 {M_HASHTYPE_RSS_TCP_IPV4, M_HASHTYPE_RSS_TCP_IPV6}, 1920 {M_HASHTYPE_RSS_UDP_IPV4, M_HASHTYPE_RSS_UDP_IPV6}, 1921 }; 1922 static const int sw_csum_flags[2][2] = { 1923 { 1924 /* IP, inner IP */ 1925 CSUM_ENCAP_VXLAN | 1926 CSUM_L3_CALC | CSUM_L3_VALID | 1927 CSUM_L4_CALC | CSUM_L4_VALID | 1928 CSUM_INNER_L3_CALC | CSUM_INNER_L3_VALID | 1929 CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID, 1930 1931 /* IP, inner IP6 */ 1932 CSUM_ENCAP_VXLAN | 1933 CSUM_L3_CALC | CSUM_L3_VALID | 1934 CSUM_L4_CALC | CSUM_L4_VALID | 1935 CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID, 1936 }, 1937 { 1938 /* IP6, inner IP */ 1939 CSUM_ENCAP_VXLAN | 1940 CSUM_L4_CALC | CSUM_L4_VALID | 1941 CSUM_INNER_L3_CALC | CSUM_INNER_L3_VALID | 1942 CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID, 1943 1944 /* IP6, inner IP6 */ 1945 CSUM_ENCAP_VXLAN | 1946 CSUM_L4_CALC | CSUM_L4_VALID | 1947 CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID, 1948 }, 1949 }; 1950 1951 MPASS(plen > sc->params.sge.fl_pktshift); 1952 if (vi->pfil != NULL && PFIL_HOOKED_IN(vi->pfil) && 1953 __predict_true((fl->flags & FL_BUF_RESUME) == 0)) { 1954 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 1955 caddr_t frame; 1956 int rc, slen; 1957 1958 slen = get_segment_len(sc, fl, plen) - 1959 sc->params.sge.fl_pktshift; 1960 frame = sd->cl + fl->rx_offset + sc->params.sge.fl_pktshift; 1961 CURVNET_SET_QUIET(ifp->if_vnet); 1962 rc = pfil_run_hooks(vi->pfil, frame, ifp, 1963 slen | PFIL_MEMPTR | PFIL_IN, NULL); 1964 CURVNET_RESTORE(); 1965 if (rc == PFIL_DROPPED || rc == PFIL_CONSUMED) { 1966 skip_fl_payload(sc, fl, plen); 1967 return (0); 1968 } 1969 if (rc == PFIL_REALLOCED) { 1970 skip_fl_payload(sc, fl, plen); 1971 m0 = pfil_mem2mbuf(frame); 1972 goto have_mbuf; 1973 } 1974 } 1975 1976 m0 = get_fl_payload(sc, fl, plen); 1977 if (__predict_false(m0 == NULL)) 1978 return (ENOMEM); 1979 1980 m0->m_pkthdr.len -= sc->params.sge.fl_pktshift; 1981 m0->m_len -= sc->params.sge.fl_pktshift; 1982 m0->m_data += sc->params.sge.fl_pktshift; 1983 1984 have_mbuf: 1985 m0->m_pkthdr.rcvif = ifp; 1986 M_HASHTYPE_SET(m0, sw_hashtype[d->rss.hash_type][d->rss.ipv6]); 1987 m0->m_pkthdr.flowid = be32toh(d->rss.hash_val); 1988 1989 cpl = (const void *)(&d->rss + 1); 1990 if (sc->params.tp.rx_pkt_encap) { 1991 const uint16_t ev = be16toh(cpl->err_vec); 1992 1993 err_vec = G_T6_COMPR_RXERR_VEC(ev); 1994 tnl_type = G_T6_RX_TNL_TYPE(ev); 1995 tnlhdr_len = G_T6_RX_TNLHDR_LEN(ev); 1996 } else { 1997 err_vec = be16toh(cpl->err_vec); 1998 tnl_type = 0; 1999 tnlhdr_len = 0; 2000 } 2001 if (cpl->csum_calc && err_vec == 0) { 2002 int ipv6 = !!(cpl->l2info & htobe32(F_RXF_IP6)); 2003 2004 /* checksum(s) calculated and found to be correct. */ 2005 2006 MPASS((cpl->l2info & htobe32(F_RXF_IP)) ^ 2007 (cpl->l2info & htobe32(F_RXF_IP6))); 2008 m0->m_pkthdr.csum_data = be16toh(cpl->csum); 2009 if (tnl_type == 0) { 2010 if (!ipv6 && ifp->if_capenable & IFCAP_RXCSUM) { 2011 m0->m_pkthdr.csum_flags = CSUM_L3_CALC | 2012 CSUM_L3_VALID | CSUM_L4_CALC | 2013 CSUM_L4_VALID; 2014 } else if (ipv6 && ifp->if_capenable & IFCAP_RXCSUM_IPV6) { 2015 m0->m_pkthdr.csum_flags = CSUM_L4_CALC | 2016 CSUM_L4_VALID; 2017 } 2018 rxq->rxcsum++; 2019 } else { 2020 MPASS(tnl_type == RX_PKT_TNL_TYPE_VXLAN); 2021 2022 M_HASHTYPE_SETINNER(m0); 2023 if (__predict_false(cpl->ip_frag)) { 2024 /* 2025 * csum_data is for the inner frame (which is an 2026 * IP fragment) and is not 0xffff. There is no 2027 * way to pass the inner csum_data to the stack. 2028 * We don't want the stack to use the inner 2029 * csum_data to validate the outer frame or it 2030 * will get rejected. So we fix csum_data here 2031 * and let sw do the checksum of inner IP 2032 * fragments. 2033 * 2034 * XXX: Need 32b for csum_data2 in an rx mbuf. 2035 * Maybe stuff it into rcv_tstmp? 2036 */ 2037 m0->m_pkthdr.csum_data = 0xffff; 2038 if (ipv6) { 2039 m0->m_pkthdr.csum_flags = CSUM_L4_CALC | 2040 CSUM_L4_VALID; 2041 } else { 2042 m0->m_pkthdr.csum_flags = CSUM_L3_CALC | 2043 CSUM_L3_VALID | CSUM_L4_CALC | 2044 CSUM_L4_VALID; 2045 } 2046 } else { 2047 int outer_ipv6; 2048 2049 MPASS(m0->m_pkthdr.csum_data == 0xffff); 2050 2051 outer_ipv6 = tnlhdr_len >= 2052 sizeof(struct ether_header) + 2053 sizeof(struct ip6_hdr); 2054 m0->m_pkthdr.csum_flags = 2055 sw_csum_flags[outer_ipv6][ipv6]; 2056 } 2057 rxq->vxlan_rxcsum++; 2058 } 2059 } 2060 2061 if (cpl->vlan_ex) { 2062 m0->m_pkthdr.ether_vtag = be16toh(cpl->vlan); 2063 m0->m_flags |= M_VLANTAG; 2064 rxq->vlan_extraction++; 2065 } 2066 2067 if (rxq->iq.flags & IQ_RX_TIMESTAMP) { 2068 /* 2069 * Fill up rcv_tstmp but do not set M_TSTMP. 2070 * rcv_tstmp is not in the format that the 2071 * kernel expects and we don't want to mislead 2072 * it. For now this is only for custom code 2073 * that knows how to interpret cxgbe's stamp. 2074 */ 2075 m0->m_pkthdr.rcv_tstmp = 2076 last_flit_to_ns(sc, d->rsp.u.last_flit); 2077 #ifdef notyet 2078 m0->m_flags |= M_TSTMP; 2079 #endif 2080 } 2081 2082 #ifdef NUMA 2083 m0->m_pkthdr.numa_domain = ifp->if_numa_domain; 2084 #endif 2085 #if defined(INET) || defined(INET6) 2086 if (rxq->iq.flags & IQ_LRO_ENABLED && tnl_type == 0 && 2087 (M_HASHTYPE_GET(m0) == M_HASHTYPE_RSS_TCP_IPV4 || 2088 M_HASHTYPE_GET(m0) == M_HASHTYPE_RSS_TCP_IPV6)) { 2089 if (sort_before_lro(lro)) { 2090 tcp_lro_queue_mbuf(lro, m0); 2091 return (0); /* queued for sort, then LRO */ 2092 } 2093 if (tcp_lro_rx(lro, m0, 0) == 0) 2094 return (0); /* queued for LRO */ 2095 } 2096 #endif 2097 ifp->if_input(ifp, m0); 2098 2099 return (0); 2100 } 2101 2102 /* 2103 * Must drain the wrq or make sure that someone else will. 2104 */ 2105 static void 2106 wrq_tx_drain(void *arg, int n) 2107 { 2108 struct sge_wrq *wrq = arg; 2109 struct sge_eq *eq = &wrq->eq; 2110 2111 EQ_LOCK(eq); 2112 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 2113 drain_wrq_wr_list(wrq->adapter, wrq); 2114 EQ_UNLOCK(eq); 2115 } 2116 2117 static void 2118 drain_wrq_wr_list(struct adapter *sc, struct sge_wrq *wrq) 2119 { 2120 struct sge_eq *eq = &wrq->eq; 2121 u_int available, dbdiff; /* # of hardware descriptors */ 2122 u_int n; 2123 struct wrqe *wr; 2124 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */ 2125 2126 EQ_LOCK_ASSERT_OWNED(eq); 2127 MPASS(TAILQ_EMPTY(&wrq->incomplete_wrs)); 2128 wr = STAILQ_FIRST(&wrq->wr_list); 2129 MPASS(wr != NULL); /* Must be called with something useful to do */ 2130 MPASS(eq->pidx == eq->dbidx); 2131 dbdiff = 0; 2132 2133 do { 2134 eq->cidx = read_hw_cidx(eq); 2135 if (eq->pidx == eq->cidx) 2136 available = eq->sidx - 1; 2137 else 2138 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2139 2140 MPASS(wr->wrq == wrq); 2141 n = howmany(wr->wr_len, EQ_ESIZE); 2142 if (available < n) 2143 break; 2144 2145 dst = (void *)&eq->desc[eq->pidx]; 2146 if (__predict_true(eq->sidx - eq->pidx > n)) { 2147 /* Won't wrap, won't end exactly at the status page. */ 2148 bcopy(&wr->wr[0], dst, wr->wr_len); 2149 eq->pidx += n; 2150 } else { 2151 int first_portion = (eq->sidx - eq->pidx) * EQ_ESIZE; 2152 2153 bcopy(&wr->wr[0], dst, first_portion); 2154 if (wr->wr_len > first_portion) { 2155 bcopy(&wr->wr[first_portion], &eq->desc[0], 2156 wr->wr_len - first_portion); 2157 } 2158 eq->pidx = n - (eq->sidx - eq->pidx); 2159 } 2160 wrq->tx_wrs_copied++; 2161 2162 if (available < eq->sidx / 4 && 2163 atomic_cmpset_int(&eq->equiq, 0, 1)) { 2164 /* 2165 * XXX: This is not 100% reliable with some 2166 * types of WRs. But this is a very unusual 2167 * situation for an ofld/ctrl queue anyway. 2168 */ 2169 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ | 2170 F_FW_WR_EQUEQ); 2171 } 2172 2173 dbdiff += n; 2174 if (dbdiff >= 16) { 2175 ring_eq_db(sc, eq, dbdiff); 2176 dbdiff = 0; 2177 } 2178 2179 STAILQ_REMOVE_HEAD(&wrq->wr_list, link); 2180 free_wrqe(wr); 2181 MPASS(wrq->nwr_pending > 0); 2182 wrq->nwr_pending--; 2183 MPASS(wrq->ndesc_needed >= n); 2184 wrq->ndesc_needed -= n; 2185 } while ((wr = STAILQ_FIRST(&wrq->wr_list)) != NULL); 2186 2187 if (dbdiff) 2188 ring_eq_db(sc, eq, dbdiff); 2189 } 2190 2191 /* 2192 * Doesn't fail. Holds on to work requests it can't send right away. 2193 */ 2194 void 2195 t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, struct wrqe *wr) 2196 { 2197 #ifdef INVARIANTS 2198 struct sge_eq *eq = &wrq->eq; 2199 #endif 2200 2201 EQ_LOCK_ASSERT_OWNED(eq); 2202 MPASS(wr != NULL); 2203 MPASS(wr->wr_len > 0 && wr->wr_len <= SGE_MAX_WR_LEN); 2204 MPASS((wr->wr_len & 0x7) == 0); 2205 2206 STAILQ_INSERT_TAIL(&wrq->wr_list, wr, link); 2207 wrq->nwr_pending++; 2208 wrq->ndesc_needed += howmany(wr->wr_len, EQ_ESIZE); 2209 2210 if (!TAILQ_EMPTY(&wrq->incomplete_wrs)) 2211 return; /* commit_wrq_wr will drain wr_list as well. */ 2212 2213 drain_wrq_wr_list(sc, wrq); 2214 2215 /* Doorbell must have caught up to the pidx. */ 2216 MPASS(eq->pidx == eq->dbidx); 2217 } 2218 2219 void 2220 t4_update_fl_bufsize(struct ifnet *ifp) 2221 { 2222 struct vi_info *vi = ifp->if_softc; 2223 struct adapter *sc = vi->adapter; 2224 struct sge_rxq *rxq; 2225 #ifdef TCP_OFFLOAD 2226 struct sge_ofld_rxq *ofld_rxq; 2227 #endif 2228 struct sge_fl *fl; 2229 int i, maxp; 2230 2231 maxp = max_rx_payload(sc, ifp, false); 2232 for_each_rxq(vi, i, rxq) { 2233 fl = &rxq->fl; 2234 2235 FL_LOCK(fl); 2236 fl->zidx = find_refill_source(sc, maxp, 2237 fl->flags & FL_BUF_PACKING); 2238 FL_UNLOCK(fl); 2239 } 2240 #ifdef TCP_OFFLOAD 2241 maxp = max_rx_payload(sc, ifp, true); 2242 for_each_ofld_rxq(vi, i, ofld_rxq) { 2243 fl = &ofld_rxq->fl; 2244 2245 FL_LOCK(fl); 2246 fl->zidx = find_refill_source(sc, maxp, 2247 fl->flags & FL_BUF_PACKING); 2248 FL_UNLOCK(fl); 2249 } 2250 #endif 2251 } 2252 2253 static inline int 2254 mbuf_nsegs(struct mbuf *m) 2255 { 2256 2257 M_ASSERTPKTHDR(m); 2258 KASSERT(m->m_pkthdr.inner_l5hlen > 0, 2259 ("%s: mbuf %p missing information on # of segments.", __func__, m)); 2260 2261 return (m->m_pkthdr.inner_l5hlen); 2262 } 2263 2264 static inline void 2265 set_mbuf_nsegs(struct mbuf *m, uint8_t nsegs) 2266 { 2267 2268 M_ASSERTPKTHDR(m); 2269 m->m_pkthdr.inner_l5hlen = nsegs; 2270 } 2271 2272 static inline int 2273 mbuf_cflags(struct mbuf *m) 2274 { 2275 2276 M_ASSERTPKTHDR(m); 2277 return (m->m_pkthdr.PH_loc.eight[4]); 2278 } 2279 2280 static inline void 2281 set_mbuf_cflags(struct mbuf *m, uint8_t flags) 2282 { 2283 2284 M_ASSERTPKTHDR(m); 2285 m->m_pkthdr.PH_loc.eight[4] = flags; 2286 } 2287 2288 static inline int 2289 mbuf_len16(struct mbuf *m) 2290 { 2291 int n; 2292 2293 M_ASSERTPKTHDR(m); 2294 n = m->m_pkthdr.PH_loc.eight[0]; 2295 if (!(mbuf_cflags(m) & MC_TLS)) 2296 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16); 2297 2298 return (n); 2299 } 2300 2301 static inline void 2302 set_mbuf_len16(struct mbuf *m, uint8_t len16) 2303 { 2304 2305 M_ASSERTPKTHDR(m); 2306 if (!(mbuf_cflags(m) & MC_TLS)) 2307 MPASS(len16 > 0 && len16 <= SGE_MAX_WR_LEN / 16); 2308 m->m_pkthdr.PH_loc.eight[0] = len16; 2309 } 2310 2311 #ifdef RATELIMIT 2312 static inline int 2313 mbuf_eo_nsegs(struct mbuf *m) 2314 { 2315 2316 M_ASSERTPKTHDR(m); 2317 return (m->m_pkthdr.PH_loc.eight[1]); 2318 } 2319 2320 #if defined(INET) || defined(INET6) 2321 static inline void 2322 set_mbuf_eo_nsegs(struct mbuf *m, uint8_t nsegs) 2323 { 2324 2325 M_ASSERTPKTHDR(m); 2326 m->m_pkthdr.PH_loc.eight[1] = nsegs; 2327 } 2328 #endif 2329 2330 static inline int 2331 mbuf_eo_len16(struct mbuf *m) 2332 { 2333 int n; 2334 2335 M_ASSERTPKTHDR(m); 2336 n = m->m_pkthdr.PH_loc.eight[2]; 2337 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16); 2338 2339 return (n); 2340 } 2341 2342 #if defined(INET) || defined(INET6) 2343 static inline void 2344 set_mbuf_eo_len16(struct mbuf *m, uint8_t len16) 2345 { 2346 2347 M_ASSERTPKTHDR(m); 2348 m->m_pkthdr.PH_loc.eight[2] = len16; 2349 } 2350 #endif 2351 2352 static inline int 2353 mbuf_eo_tsclk_tsoff(struct mbuf *m) 2354 { 2355 2356 M_ASSERTPKTHDR(m); 2357 return (m->m_pkthdr.PH_loc.eight[3]); 2358 } 2359 2360 #if defined(INET) || defined(INET6) 2361 static inline void 2362 set_mbuf_eo_tsclk_tsoff(struct mbuf *m, uint8_t tsclk_tsoff) 2363 { 2364 2365 M_ASSERTPKTHDR(m); 2366 m->m_pkthdr.PH_loc.eight[3] = tsclk_tsoff; 2367 } 2368 #endif 2369 2370 static inline int 2371 needs_eo(struct m_snd_tag *mst) 2372 { 2373 2374 return (mst != NULL && mst->sw->type == IF_SND_TAG_TYPE_RATE_LIMIT); 2375 } 2376 #endif 2377 2378 /* 2379 * Try to allocate an mbuf to contain a raw work request. To make it 2380 * easy to construct the work request, don't allocate a chain but a 2381 * single mbuf. 2382 */ 2383 struct mbuf * 2384 alloc_wr_mbuf(int len, int how) 2385 { 2386 struct mbuf *m; 2387 2388 if (len <= MHLEN) 2389 m = m_gethdr(how, MT_DATA); 2390 else if (len <= MCLBYTES) 2391 m = m_getcl(how, MT_DATA, M_PKTHDR); 2392 else 2393 m = NULL; 2394 if (m == NULL) 2395 return (NULL); 2396 m->m_pkthdr.len = len; 2397 m->m_len = len; 2398 set_mbuf_cflags(m, MC_RAW_WR); 2399 set_mbuf_len16(m, howmany(len, 16)); 2400 return (m); 2401 } 2402 2403 static inline bool 2404 needs_hwcsum(struct mbuf *m) 2405 { 2406 const uint32_t csum_flags = CSUM_IP | CSUM_IP_UDP | CSUM_IP_TCP | 2407 CSUM_IP_TSO | CSUM_INNER_IP | CSUM_INNER_IP_UDP | 2408 CSUM_INNER_IP_TCP | CSUM_INNER_IP_TSO | CSUM_IP6_UDP | 2409 CSUM_IP6_TCP | CSUM_IP6_TSO | CSUM_INNER_IP6_UDP | 2410 CSUM_INNER_IP6_TCP | CSUM_INNER_IP6_TSO; 2411 2412 M_ASSERTPKTHDR(m); 2413 2414 return (m->m_pkthdr.csum_flags & csum_flags); 2415 } 2416 2417 static inline bool 2418 needs_tso(struct mbuf *m) 2419 { 2420 const uint32_t csum_flags = CSUM_IP_TSO | CSUM_IP6_TSO | 2421 CSUM_INNER_IP_TSO | CSUM_INNER_IP6_TSO; 2422 2423 M_ASSERTPKTHDR(m); 2424 2425 return (m->m_pkthdr.csum_flags & csum_flags); 2426 } 2427 2428 static inline bool 2429 needs_vxlan_csum(struct mbuf *m) 2430 { 2431 2432 M_ASSERTPKTHDR(m); 2433 2434 return (m->m_pkthdr.csum_flags & CSUM_ENCAP_VXLAN); 2435 } 2436 2437 static inline bool 2438 needs_vxlan_tso(struct mbuf *m) 2439 { 2440 const uint32_t csum_flags = CSUM_ENCAP_VXLAN | CSUM_INNER_IP_TSO | 2441 CSUM_INNER_IP6_TSO; 2442 2443 M_ASSERTPKTHDR(m); 2444 2445 return ((m->m_pkthdr.csum_flags & csum_flags) != 0 && 2446 (m->m_pkthdr.csum_flags & csum_flags) != CSUM_ENCAP_VXLAN); 2447 } 2448 2449 #if defined(INET) || defined(INET6) 2450 static inline bool 2451 needs_inner_tcp_csum(struct mbuf *m) 2452 { 2453 const uint32_t csum_flags = CSUM_INNER_IP_TSO | CSUM_INNER_IP6_TSO; 2454 2455 M_ASSERTPKTHDR(m); 2456 2457 return (m->m_pkthdr.csum_flags & csum_flags); 2458 } 2459 #endif 2460 2461 static inline bool 2462 needs_l3_csum(struct mbuf *m) 2463 { 2464 const uint32_t csum_flags = CSUM_IP | CSUM_IP_TSO | CSUM_INNER_IP | 2465 CSUM_INNER_IP_TSO; 2466 2467 M_ASSERTPKTHDR(m); 2468 2469 return (m->m_pkthdr.csum_flags & csum_flags); 2470 } 2471 2472 static inline bool 2473 needs_outer_tcp_csum(struct mbuf *m) 2474 { 2475 const uint32_t csum_flags = CSUM_IP_TCP | CSUM_IP_TSO | CSUM_IP6_TCP | 2476 CSUM_IP6_TSO; 2477 2478 M_ASSERTPKTHDR(m); 2479 2480 return (m->m_pkthdr.csum_flags & csum_flags); 2481 } 2482 2483 #ifdef RATELIMIT 2484 static inline bool 2485 needs_outer_l4_csum(struct mbuf *m) 2486 { 2487 const uint32_t csum_flags = CSUM_IP_UDP | CSUM_IP_TCP | CSUM_IP_TSO | 2488 CSUM_IP6_UDP | CSUM_IP6_TCP | CSUM_IP6_TSO; 2489 2490 M_ASSERTPKTHDR(m); 2491 2492 return (m->m_pkthdr.csum_flags & csum_flags); 2493 } 2494 2495 static inline bool 2496 needs_outer_udp_csum(struct mbuf *m) 2497 { 2498 const uint32_t csum_flags = CSUM_IP_UDP | CSUM_IP6_UDP; 2499 2500 M_ASSERTPKTHDR(m); 2501 2502 return (m->m_pkthdr.csum_flags & csum_flags); 2503 } 2504 #endif 2505 2506 static inline bool 2507 needs_vlan_insertion(struct mbuf *m) 2508 { 2509 2510 M_ASSERTPKTHDR(m); 2511 2512 return (m->m_flags & M_VLANTAG); 2513 } 2514 2515 static void * 2516 m_advance(struct mbuf **pm, int *poffset, int len) 2517 { 2518 struct mbuf *m = *pm; 2519 int offset = *poffset; 2520 uintptr_t p = 0; 2521 2522 MPASS(len > 0); 2523 2524 for (;;) { 2525 if (offset + len < m->m_len) { 2526 offset += len; 2527 p = mtod(m, uintptr_t) + offset; 2528 break; 2529 } 2530 len -= m->m_len - offset; 2531 m = m->m_next; 2532 offset = 0; 2533 MPASS(m != NULL); 2534 } 2535 *poffset = offset; 2536 *pm = m; 2537 return ((void *)p); 2538 } 2539 2540 static inline int 2541 count_mbuf_ext_pgs(struct mbuf *m, int skip, vm_paddr_t *nextaddr) 2542 { 2543 vm_paddr_t paddr; 2544 int i, len, off, pglen, pgoff, seglen, segoff; 2545 int nsegs = 0; 2546 2547 M_ASSERTEXTPG(m); 2548 off = mtod(m, vm_offset_t); 2549 len = m->m_len; 2550 off += skip; 2551 len -= skip; 2552 2553 if (m->m_epg_hdrlen != 0) { 2554 if (off >= m->m_epg_hdrlen) { 2555 off -= m->m_epg_hdrlen; 2556 } else { 2557 seglen = m->m_epg_hdrlen - off; 2558 segoff = off; 2559 seglen = min(seglen, len); 2560 off = 0; 2561 len -= seglen; 2562 paddr = pmap_kextract( 2563 (vm_offset_t)&m->m_epg_hdr[segoff]); 2564 if (*nextaddr != paddr) 2565 nsegs++; 2566 *nextaddr = paddr + seglen; 2567 } 2568 } 2569 pgoff = m->m_epg_1st_off; 2570 for (i = 0; i < m->m_epg_npgs && len > 0; i++) { 2571 pglen = m_epg_pagelen(m, i, pgoff); 2572 if (off >= pglen) { 2573 off -= pglen; 2574 pgoff = 0; 2575 continue; 2576 } 2577 seglen = pglen - off; 2578 segoff = pgoff + off; 2579 off = 0; 2580 seglen = min(seglen, len); 2581 len -= seglen; 2582 paddr = m->m_epg_pa[i] + segoff; 2583 if (*nextaddr != paddr) 2584 nsegs++; 2585 *nextaddr = paddr + seglen; 2586 pgoff = 0; 2587 }; 2588 if (len != 0) { 2589 seglen = min(len, m->m_epg_trllen - off); 2590 len -= seglen; 2591 paddr = pmap_kextract((vm_offset_t)&m->m_epg_trail[off]); 2592 if (*nextaddr != paddr) 2593 nsegs++; 2594 *nextaddr = paddr + seglen; 2595 } 2596 2597 return (nsegs); 2598 } 2599 2600 2601 /* 2602 * Can deal with empty mbufs in the chain that have m_len = 0, but the chain 2603 * must have at least one mbuf that's not empty. It is possible for this 2604 * routine to return 0 if skip accounts for all the contents of the mbuf chain. 2605 */ 2606 static inline int 2607 count_mbuf_nsegs(struct mbuf *m, int skip, uint8_t *cflags) 2608 { 2609 vm_paddr_t nextaddr, paddr; 2610 vm_offset_t va; 2611 int len, nsegs; 2612 2613 M_ASSERTPKTHDR(m); 2614 MPASS(m->m_pkthdr.len > 0); 2615 MPASS(m->m_pkthdr.len >= skip); 2616 2617 nsegs = 0; 2618 nextaddr = 0; 2619 for (; m; m = m->m_next) { 2620 len = m->m_len; 2621 if (__predict_false(len == 0)) 2622 continue; 2623 if (skip >= len) { 2624 skip -= len; 2625 continue; 2626 } 2627 if ((m->m_flags & M_EXTPG) != 0) { 2628 *cflags |= MC_NOMAP; 2629 nsegs += count_mbuf_ext_pgs(m, skip, &nextaddr); 2630 skip = 0; 2631 continue; 2632 } 2633 va = mtod(m, vm_offset_t) + skip; 2634 len -= skip; 2635 skip = 0; 2636 paddr = pmap_kextract(va); 2637 nsegs += sglist_count((void *)(uintptr_t)va, len); 2638 if (paddr == nextaddr) 2639 nsegs--; 2640 nextaddr = pmap_kextract(va + len - 1) + 1; 2641 } 2642 2643 return (nsegs); 2644 } 2645 2646 /* 2647 * The maximum number of segments that can fit in a WR. 2648 */ 2649 static int 2650 max_nsegs_allowed(struct mbuf *m, bool vm_wr) 2651 { 2652 2653 if (vm_wr) { 2654 if (needs_tso(m)) 2655 return (TX_SGL_SEGS_VM_TSO); 2656 return (TX_SGL_SEGS_VM); 2657 } 2658 2659 if (needs_tso(m)) { 2660 if (needs_vxlan_tso(m)) 2661 return (TX_SGL_SEGS_VXLAN_TSO); 2662 else 2663 return (TX_SGL_SEGS_TSO); 2664 } 2665 2666 return (TX_SGL_SEGS); 2667 } 2668 2669 static struct timeval txerr_ratecheck = {0}; 2670 static const struct timeval txerr_interval = {3, 0}; 2671 2672 /* 2673 * Analyze the mbuf to determine its tx needs. The mbuf passed in may change: 2674 * a) caller can assume it's been freed if this function returns with an error. 2675 * b) it may get defragged up if the gather list is too long for the hardware. 2676 */ 2677 int 2678 parse_pkt(struct mbuf **mp, bool vm_wr) 2679 { 2680 struct mbuf *m0 = *mp, *m; 2681 int rc, nsegs, defragged = 0, offset; 2682 struct ether_header *eh; 2683 void *l3hdr; 2684 #if defined(INET) || defined(INET6) 2685 struct tcphdr *tcp; 2686 #endif 2687 #if defined(KERN_TLS) || defined(RATELIMIT) 2688 struct m_snd_tag *mst; 2689 #endif 2690 uint16_t eh_type; 2691 uint8_t cflags; 2692 2693 cflags = 0; 2694 M_ASSERTPKTHDR(m0); 2695 if (__predict_false(m0->m_pkthdr.len < ETHER_HDR_LEN)) { 2696 rc = EINVAL; 2697 fail: 2698 m_freem(m0); 2699 *mp = NULL; 2700 return (rc); 2701 } 2702 restart: 2703 /* 2704 * First count the number of gather list segments in the payload. 2705 * Defrag the mbuf if nsegs exceeds the hardware limit. 2706 */ 2707 M_ASSERTPKTHDR(m0); 2708 MPASS(m0->m_pkthdr.len > 0); 2709 nsegs = count_mbuf_nsegs(m0, 0, &cflags); 2710 #if defined(KERN_TLS) || defined(RATELIMIT) 2711 if (m0->m_pkthdr.csum_flags & CSUM_SND_TAG) 2712 mst = m0->m_pkthdr.snd_tag; 2713 else 2714 mst = NULL; 2715 #endif 2716 #ifdef KERN_TLS 2717 if (mst != NULL && mst->sw->type == IF_SND_TAG_TYPE_TLS) { 2718 int len16; 2719 2720 cflags |= MC_TLS; 2721 set_mbuf_cflags(m0, cflags); 2722 rc = t6_ktls_parse_pkt(m0, &nsegs, &len16); 2723 if (rc != 0) 2724 goto fail; 2725 set_mbuf_nsegs(m0, nsegs); 2726 set_mbuf_len16(m0, len16); 2727 return (0); 2728 } 2729 #endif 2730 if (nsegs > max_nsegs_allowed(m0, vm_wr)) { 2731 if (defragged++ > 0) { 2732 rc = EFBIG; 2733 goto fail; 2734 } 2735 counter_u64_add(defrags, 1); 2736 if ((m = m_defrag(m0, M_NOWAIT)) == NULL) { 2737 rc = ENOMEM; 2738 goto fail; 2739 } 2740 *mp = m0 = m; /* update caller's copy after defrag */ 2741 goto restart; 2742 } 2743 2744 if (__predict_false(nsegs > 2 && m0->m_pkthdr.len <= MHLEN && 2745 !(cflags & MC_NOMAP))) { 2746 counter_u64_add(pullups, 1); 2747 m0 = m_pullup(m0, m0->m_pkthdr.len); 2748 if (m0 == NULL) { 2749 /* Should have left well enough alone. */ 2750 rc = EFBIG; 2751 goto fail; 2752 } 2753 *mp = m0; /* update caller's copy after pullup */ 2754 goto restart; 2755 } 2756 set_mbuf_nsegs(m0, nsegs); 2757 set_mbuf_cflags(m0, cflags); 2758 calculate_mbuf_len16(m0, vm_wr); 2759 2760 #ifdef RATELIMIT 2761 /* 2762 * Ethofld is limited to TCP and UDP for now, and only when L4 hw 2763 * checksumming is enabled. needs_outer_l4_csum happens to check for 2764 * all the right things. 2765 */ 2766 if (__predict_false(needs_eo(mst) && !needs_outer_l4_csum(m0))) { 2767 m_snd_tag_rele(m0->m_pkthdr.snd_tag); 2768 m0->m_pkthdr.snd_tag = NULL; 2769 m0->m_pkthdr.csum_flags &= ~CSUM_SND_TAG; 2770 mst = NULL; 2771 } 2772 #endif 2773 2774 if (!needs_hwcsum(m0) 2775 #ifdef RATELIMIT 2776 && !needs_eo(mst) 2777 #endif 2778 ) 2779 return (0); 2780 2781 m = m0; 2782 eh = mtod(m, struct ether_header *); 2783 eh_type = ntohs(eh->ether_type); 2784 if (eh_type == ETHERTYPE_VLAN) { 2785 struct ether_vlan_header *evh = (void *)eh; 2786 2787 eh_type = ntohs(evh->evl_proto); 2788 m0->m_pkthdr.l2hlen = sizeof(*evh); 2789 } else 2790 m0->m_pkthdr.l2hlen = sizeof(*eh); 2791 2792 offset = 0; 2793 l3hdr = m_advance(&m, &offset, m0->m_pkthdr.l2hlen); 2794 2795 switch (eh_type) { 2796 #ifdef INET6 2797 case ETHERTYPE_IPV6: 2798 m0->m_pkthdr.l3hlen = sizeof(struct ip6_hdr); 2799 break; 2800 #endif 2801 #ifdef INET 2802 case ETHERTYPE_IP: 2803 { 2804 struct ip *ip = l3hdr; 2805 2806 if (needs_vxlan_csum(m0)) { 2807 /* Driver will do the outer IP hdr checksum. */ 2808 ip->ip_sum = 0; 2809 if (needs_vxlan_tso(m0)) { 2810 const uint16_t ipl = ip->ip_len; 2811 2812 ip->ip_len = 0; 2813 ip->ip_sum = ~in_cksum_hdr(ip); 2814 ip->ip_len = ipl; 2815 } else 2816 ip->ip_sum = in_cksum_hdr(ip); 2817 } 2818 m0->m_pkthdr.l3hlen = ip->ip_hl << 2; 2819 break; 2820 } 2821 #endif 2822 default: 2823 if (ratecheck(&txerr_ratecheck, &txerr_interval)) { 2824 log(LOG_ERR, "%s: ethertype 0x%04x unknown. " 2825 "if_cxgbe must be compiled with the same " 2826 "INET/INET6 options as the kernel.\n", __func__, 2827 eh_type); 2828 } 2829 rc = EINVAL; 2830 goto fail; 2831 } 2832 2833 if (needs_vxlan_csum(m0)) { 2834 m0->m_pkthdr.l4hlen = sizeof(struct udphdr); 2835 m0->m_pkthdr.l5hlen = sizeof(struct vxlan_header); 2836 2837 /* Inner headers. */ 2838 eh = m_advance(&m, &offset, m0->m_pkthdr.l3hlen + 2839 sizeof(struct udphdr) + sizeof(struct vxlan_header)); 2840 eh_type = ntohs(eh->ether_type); 2841 if (eh_type == ETHERTYPE_VLAN) { 2842 struct ether_vlan_header *evh = (void *)eh; 2843 2844 eh_type = ntohs(evh->evl_proto); 2845 m0->m_pkthdr.inner_l2hlen = sizeof(*evh); 2846 } else 2847 m0->m_pkthdr.inner_l2hlen = sizeof(*eh); 2848 l3hdr = m_advance(&m, &offset, m0->m_pkthdr.inner_l2hlen); 2849 2850 switch (eh_type) { 2851 #ifdef INET6 2852 case ETHERTYPE_IPV6: 2853 m0->m_pkthdr.inner_l3hlen = sizeof(struct ip6_hdr); 2854 break; 2855 #endif 2856 #ifdef INET 2857 case ETHERTYPE_IP: 2858 { 2859 struct ip *ip = l3hdr; 2860 2861 m0->m_pkthdr.inner_l3hlen = ip->ip_hl << 2; 2862 break; 2863 } 2864 #endif 2865 default: 2866 if (ratecheck(&txerr_ratecheck, &txerr_interval)) { 2867 log(LOG_ERR, "%s: VXLAN hw offload requested" 2868 "with unknown ethertype 0x%04x. if_cxgbe " 2869 "must be compiled with the same INET/INET6 " 2870 "options as the kernel.\n", __func__, 2871 eh_type); 2872 } 2873 rc = EINVAL; 2874 goto fail; 2875 } 2876 #if defined(INET) || defined(INET6) 2877 if (needs_inner_tcp_csum(m0)) { 2878 tcp = m_advance(&m, &offset, m0->m_pkthdr.inner_l3hlen); 2879 m0->m_pkthdr.inner_l4hlen = tcp->th_off * 4; 2880 } 2881 #endif 2882 MPASS((m0->m_pkthdr.csum_flags & CSUM_SND_TAG) == 0); 2883 m0->m_pkthdr.csum_flags &= CSUM_INNER_IP6_UDP | 2884 CSUM_INNER_IP6_TCP | CSUM_INNER_IP6_TSO | CSUM_INNER_IP | 2885 CSUM_INNER_IP_UDP | CSUM_INNER_IP_TCP | CSUM_INNER_IP_TSO | 2886 CSUM_ENCAP_VXLAN; 2887 } 2888 2889 #if defined(INET) || defined(INET6) 2890 if (needs_outer_tcp_csum(m0)) { 2891 tcp = m_advance(&m, &offset, m0->m_pkthdr.l3hlen); 2892 m0->m_pkthdr.l4hlen = tcp->th_off * 4; 2893 #ifdef RATELIMIT 2894 if (tsclk >= 0 && *(uint32_t *)(tcp + 1) == ntohl(0x0101080a)) { 2895 set_mbuf_eo_tsclk_tsoff(m0, 2896 V_FW_ETH_TX_EO_WR_TSCLK(tsclk) | 2897 V_FW_ETH_TX_EO_WR_TSOFF(sizeof(*tcp) / 2 + 1)); 2898 } else 2899 set_mbuf_eo_tsclk_tsoff(m0, 0); 2900 } else if (needs_outer_udp_csum(m0)) { 2901 m0->m_pkthdr.l4hlen = sizeof(struct udphdr); 2902 #endif 2903 } 2904 #ifdef RATELIMIT 2905 if (needs_eo(mst)) { 2906 u_int immhdrs; 2907 2908 /* EO WRs have the headers in the WR and not the GL. */ 2909 immhdrs = m0->m_pkthdr.l2hlen + m0->m_pkthdr.l3hlen + 2910 m0->m_pkthdr.l4hlen; 2911 cflags = 0; 2912 nsegs = count_mbuf_nsegs(m0, immhdrs, &cflags); 2913 MPASS(cflags == mbuf_cflags(m0)); 2914 set_mbuf_eo_nsegs(m0, nsegs); 2915 set_mbuf_eo_len16(m0, 2916 txpkt_eo_len16(nsegs, immhdrs, needs_tso(m0))); 2917 } 2918 #endif 2919 #endif 2920 MPASS(m0 == *mp); 2921 return (0); 2922 } 2923 2924 void * 2925 start_wrq_wr(struct sge_wrq *wrq, int len16, struct wrq_cookie *cookie) 2926 { 2927 struct sge_eq *eq = &wrq->eq; 2928 struct adapter *sc = wrq->adapter; 2929 int ndesc, available; 2930 struct wrqe *wr; 2931 void *w; 2932 2933 MPASS(len16 > 0); 2934 ndesc = tx_len16_to_desc(len16); 2935 MPASS(ndesc > 0 && ndesc <= SGE_MAX_WR_NDESC); 2936 2937 EQ_LOCK(eq); 2938 2939 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 2940 drain_wrq_wr_list(sc, wrq); 2941 2942 if (!STAILQ_EMPTY(&wrq->wr_list)) { 2943 slowpath: 2944 EQ_UNLOCK(eq); 2945 wr = alloc_wrqe(len16 * 16, wrq); 2946 if (__predict_false(wr == NULL)) 2947 return (NULL); 2948 cookie->pidx = -1; 2949 cookie->ndesc = ndesc; 2950 return (&wr->wr); 2951 } 2952 2953 eq->cidx = read_hw_cidx(eq); 2954 if (eq->pidx == eq->cidx) 2955 available = eq->sidx - 1; 2956 else 2957 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2958 if (available < ndesc) 2959 goto slowpath; 2960 2961 cookie->pidx = eq->pidx; 2962 cookie->ndesc = ndesc; 2963 TAILQ_INSERT_TAIL(&wrq->incomplete_wrs, cookie, link); 2964 2965 w = &eq->desc[eq->pidx]; 2966 IDXINCR(eq->pidx, ndesc, eq->sidx); 2967 if (__predict_false(cookie->pidx + ndesc > eq->sidx)) { 2968 w = &wrq->ss[0]; 2969 wrq->ss_pidx = cookie->pidx; 2970 wrq->ss_len = len16 * 16; 2971 } 2972 2973 EQ_UNLOCK(eq); 2974 2975 return (w); 2976 } 2977 2978 void 2979 commit_wrq_wr(struct sge_wrq *wrq, void *w, struct wrq_cookie *cookie) 2980 { 2981 struct sge_eq *eq = &wrq->eq; 2982 struct adapter *sc = wrq->adapter; 2983 int ndesc, pidx; 2984 struct wrq_cookie *prev, *next; 2985 2986 if (cookie->pidx == -1) { 2987 struct wrqe *wr = __containerof(w, struct wrqe, wr); 2988 2989 t4_wrq_tx(sc, wr); 2990 return; 2991 } 2992 2993 if (__predict_false(w == &wrq->ss[0])) { 2994 int n = (eq->sidx - wrq->ss_pidx) * EQ_ESIZE; 2995 2996 MPASS(wrq->ss_len > n); /* WR had better wrap around. */ 2997 bcopy(&wrq->ss[0], &eq->desc[wrq->ss_pidx], n); 2998 bcopy(&wrq->ss[n], &eq->desc[0], wrq->ss_len - n); 2999 wrq->tx_wrs_ss++; 3000 } else 3001 wrq->tx_wrs_direct++; 3002 3003 EQ_LOCK(eq); 3004 ndesc = cookie->ndesc; /* Can be more than SGE_MAX_WR_NDESC here. */ 3005 pidx = cookie->pidx; 3006 MPASS(pidx >= 0 && pidx < eq->sidx); 3007 prev = TAILQ_PREV(cookie, wrq_incomplete_wrs, link); 3008 next = TAILQ_NEXT(cookie, link); 3009 if (prev == NULL) { 3010 MPASS(pidx == eq->dbidx); 3011 if (next == NULL || ndesc >= 16) { 3012 int available; 3013 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */ 3014 3015 /* 3016 * Note that the WR via which we'll request tx updates 3017 * is at pidx and not eq->pidx, which has moved on 3018 * already. 3019 */ 3020 dst = (void *)&eq->desc[pidx]; 3021 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 3022 if (available < eq->sidx / 4 && 3023 atomic_cmpset_int(&eq->equiq, 0, 1)) { 3024 /* 3025 * XXX: This is not 100% reliable with some 3026 * types of WRs. But this is a very unusual 3027 * situation for an ofld/ctrl queue anyway. 3028 */ 3029 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ | 3030 F_FW_WR_EQUEQ); 3031 } 3032 3033 ring_eq_db(wrq->adapter, eq, ndesc); 3034 } else { 3035 MPASS(IDXDIFF(next->pidx, pidx, eq->sidx) == ndesc); 3036 next->pidx = pidx; 3037 next->ndesc += ndesc; 3038 } 3039 } else { 3040 MPASS(IDXDIFF(pidx, prev->pidx, eq->sidx) == prev->ndesc); 3041 prev->ndesc += ndesc; 3042 } 3043 TAILQ_REMOVE(&wrq->incomplete_wrs, cookie, link); 3044 3045 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 3046 drain_wrq_wr_list(sc, wrq); 3047 3048 #ifdef INVARIANTS 3049 if (TAILQ_EMPTY(&wrq->incomplete_wrs)) { 3050 /* Doorbell must have caught up to the pidx. */ 3051 MPASS(wrq->eq.pidx == wrq->eq.dbidx); 3052 } 3053 #endif 3054 EQ_UNLOCK(eq); 3055 } 3056 3057 static u_int 3058 can_resume_eth_tx(struct mp_ring *r) 3059 { 3060 struct sge_eq *eq = r->cookie; 3061 3062 return (total_available_tx_desc(eq) > eq->sidx / 8); 3063 } 3064 3065 static inline bool 3066 cannot_use_txpkts(struct mbuf *m) 3067 { 3068 /* maybe put a GL limit too, to avoid silliness? */ 3069 3070 return (needs_tso(m) || (mbuf_cflags(m) & (MC_RAW_WR | MC_TLS)) != 0); 3071 } 3072 3073 static inline int 3074 discard_tx(struct sge_eq *eq) 3075 { 3076 3077 return ((eq->flags & (EQ_ENABLED | EQ_QFLUSH)) != EQ_ENABLED); 3078 } 3079 3080 static inline int 3081 wr_can_update_eq(void *p) 3082 { 3083 struct fw_eth_tx_pkts_wr *wr = p; 3084 3085 switch (G_FW_WR_OP(be32toh(wr->op_pkd))) { 3086 case FW_ULPTX_WR: 3087 case FW_ETH_TX_PKT_WR: 3088 case FW_ETH_TX_PKTS_WR: 3089 case FW_ETH_TX_PKTS2_WR: 3090 case FW_ETH_TX_PKT_VM_WR: 3091 case FW_ETH_TX_PKTS_VM_WR: 3092 return (1); 3093 default: 3094 return (0); 3095 } 3096 } 3097 3098 static inline void 3099 set_txupdate_flags(struct sge_txq *txq, u_int avail, 3100 struct fw_eth_tx_pkt_wr *wr) 3101 { 3102 struct sge_eq *eq = &txq->eq; 3103 struct txpkts *txp = &txq->txp; 3104 3105 if ((txp->npkt > 0 || avail < eq->sidx / 2) && 3106 atomic_cmpset_int(&eq->equiq, 0, 1)) { 3107 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ | F_FW_WR_EQUIQ); 3108 eq->equeqidx = eq->pidx; 3109 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 32) { 3110 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ); 3111 eq->equeqidx = eq->pidx; 3112 } 3113 } 3114 3115 #if defined(__i386__) || defined(__amd64__) 3116 extern uint64_t tsc_freq; 3117 #endif 3118 3119 static inline bool 3120 record_eth_tx_time(struct sge_txq *txq) 3121 { 3122 const uint64_t cycles = get_cyclecount(); 3123 const uint64_t last_tx = txq->last_tx; 3124 #if defined(__i386__) || defined(__amd64__) 3125 const uint64_t itg = tsc_freq * t4_tx_coalesce_gap / 1000000; 3126 #else 3127 const uint64_t itg = 0; 3128 #endif 3129 3130 MPASS(cycles >= last_tx); 3131 txq->last_tx = cycles; 3132 return (cycles - last_tx < itg); 3133 } 3134 3135 /* 3136 * r->items[cidx] to r->items[pidx], with a wraparound at r->size, are ready to 3137 * be consumed. Return the actual number consumed. 0 indicates a stall. 3138 */ 3139 static u_int 3140 eth_tx(struct mp_ring *r, u_int cidx, u_int pidx, bool *coalescing) 3141 { 3142 struct sge_txq *txq = r->cookie; 3143 struct ifnet *ifp = txq->ifp; 3144 struct sge_eq *eq = &txq->eq; 3145 struct txpkts *txp = &txq->txp; 3146 struct vi_info *vi = ifp->if_softc; 3147 struct adapter *sc = vi->adapter; 3148 u_int total, remaining; /* # of packets */ 3149 u_int n, avail, dbdiff; /* # of hardware descriptors */ 3150 int i, rc; 3151 struct mbuf *m0; 3152 bool snd, recent_tx; 3153 void *wr; /* start of the last WR written to the ring */ 3154 3155 TXQ_LOCK_ASSERT_OWNED(txq); 3156 recent_tx = record_eth_tx_time(txq); 3157 3158 remaining = IDXDIFF(pidx, cidx, r->size); 3159 if (__predict_false(discard_tx(eq))) { 3160 for (i = 0; i < txp->npkt; i++) 3161 m_freem(txp->mb[i]); 3162 txp->npkt = 0; 3163 while (cidx != pidx) { 3164 m0 = r->items[cidx]; 3165 m_freem(m0); 3166 if (++cidx == r->size) 3167 cidx = 0; 3168 } 3169 reclaim_tx_descs(txq, eq->sidx); 3170 *coalescing = false; 3171 return (remaining); /* emptied */ 3172 } 3173 3174 /* How many hardware descriptors do we have readily available. */ 3175 if (eq->pidx == eq->cidx) 3176 avail = eq->sidx - 1; 3177 else 3178 avail = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 3179 3180 total = 0; 3181 if (remaining == 0) { 3182 txp->score = 0; 3183 txq->txpkts_flush++; 3184 goto send_txpkts; 3185 } 3186 3187 dbdiff = 0; 3188 MPASS(remaining > 0); 3189 while (remaining > 0) { 3190 m0 = r->items[cidx]; 3191 M_ASSERTPKTHDR(m0); 3192 MPASS(m0->m_nextpkt == NULL); 3193 3194 if (avail < 2 * SGE_MAX_WR_NDESC) 3195 avail += reclaim_tx_descs(txq, 64); 3196 3197 if (t4_tx_coalesce == 0 && txp->npkt == 0) 3198 goto skip_coalescing; 3199 if (cannot_use_txpkts(m0)) 3200 txp->score = 0; 3201 else if (recent_tx) { 3202 if (++txp->score == 0) 3203 txp->score = UINT8_MAX; 3204 } else 3205 txp->score = 1; 3206 if (txp->npkt > 0 || remaining > 1 || 3207 txp->score >= t4_tx_coalesce_pkts || 3208 atomic_load_int(&txq->eq.equiq) != 0) { 3209 if (vi->flags & TX_USES_VM_WR) 3210 rc = add_to_txpkts_vf(sc, txq, m0, avail, &snd); 3211 else 3212 rc = add_to_txpkts_pf(sc, txq, m0, avail, &snd); 3213 } else { 3214 snd = false; 3215 rc = EINVAL; 3216 } 3217 if (snd) { 3218 MPASS(txp->npkt > 0); 3219 for (i = 0; i < txp->npkt; i++) 3220 ETHER_BPF_MTAP(ifp, txp->mb[i]); 3221 if (txp->npkt > 1) { 3222 MPASS(avail >= tx_len16_to_desc(txp->len16)); 3223 if (vi->flags & TX_USES_VM_WR) 3224 n = write_txpkts_vm_wr(sc, txq); 3225 else 3226 n = write_txpkts_wr(sc, txq); 3227 } else { 3228 MPASS(avail >= 3229 tx_len16_to_desc(mbuf_len16(txp->mb[0]))); 3230 if (vi->flags & TX_USES_VM_WR) 3231 n = write_txpkt_vm_wr(sc, txq, 3232 txp->mb[0]); 3233 else 3234 n = write_txpkt_wr(sc, txq, txp->mb[0], 3235 avail); 3236 } 3237 MPASS(n <= SGE_MAX_WR_NDESC); 3238 avail -= n; 3239 dbdiff += n; 3240 wr = &eq->desc[eq->pidx]; 3241 IDXINCR(eq->pidx, n, eq->sidx); 3242 txp->npkt = 0; /* emptied */ 3243 } 3244 if (rc == 0) { 3245 /* m0 was coalesced into txq->txpkts. */ 3246 goto next_mbuf; 3247 } 3248 if (rc == EAGAIN) { 3249 /* 3250 * m0 is suitable for tx coalescing but could not be 3251 * combined with the existing txq->txpkts, which has now 3252 * been transmitted. Start a new txpkts with m0. 3253 */ 3254 MPASS(snd); 3255 MPASS(txp->npkt == 0); 3256 continue; 3257 } 3258 3259 MPASS(rc != 0 && rc != EAGAIN); 3260 MPASS(txp->npkt == 0); 3261 skip_coalescing: 3262 n = tx_len16_to_desc(mbuf_len16(m0)); 3263 if (__predict_false(avail < n)) { 3264 avail += reclaim_tx_descs(txq, min(n, 32)); 3265 if (avail < n) 3266 break; /* out of descriptors */ 3267 } 3268 3269 wr = &eq->desc[eq->pidx]; 3270 if (mbuf_cflags(m0) & MC_RAW_WR) { 3271 n = write_raw_wr(txq, wr, m0, avail); 3272 #ifdef KERN_TLS 3273 } else if (mbuf_cflags(m0) & MC_TLS) { 3274 ETHER_BPF_MTAP(ifp, m0); 3275 n = t6_ktls_write_wr(txq, wr, m0, mbuf_nsegs(m0), 3276 avail); 3277 #endif 3278 } else { 3279 ETHER_BPF_MTAP(ifp, m0); 3280 if (vi->flags & TX_USES_VM_WR) 3281 n = write_txpkt_vm_wr(sc, txq, m0); 3282 else 3283 n = write_txpkt_wr(sc, txq, m0, avail); 3284 } 3285 MPASS(n >= 1 && n <= avail); 3286 if (!(mbuf_cflags(m0) & MC_TLS)) 3287 MPASS(n <= SGE_MAX_WR_NDESC); 3288 3289 avail -= n; 3290 dbdiff += n; 3291 IDXINCR(eq->pidx, n, eq->sidx); 3292 3293 if (dbdiff >= 512 / EQ_ESIZE) { /* X_FETCHBURSTMAX_512B */ 3294 if (wr_can_update_eq(wr)) 3295 set_txupdate_flags(txq, avail, wr); 3296 ring_eq_db(sc, eq, dbdiff); 3297 avail += reclaim_tx_descs(txq, 32); 3298 dbdiff = 0; 3299 } 3300 next_mbuf: 3301 total++; 3302 remaining--; 3303 if (__predict_false(++cidx == r->size)) 3304 cidx = 0; 3305 } 3306 if (dbdiff != 0) { 3307 if (wr_can_update_eq(wr)) 3308 set_txupdate_flags(txq, avail, wr); 3309 ring_eq_db(sc, eq, dbdiff); 3310 reclaim_tx_descs(txq, 32); 3311 } else if (eq->pidx == eq->cidx && txp->npkt > 0 && 3312 atomic_load_int(&txq->eq.equiq) == 0) { 3313 /* 3314 * If nothing was submitted to the chip for tx (it was coalesced 3315 * into txpkts instead) and there is no tx update outstanding 3316 * then we need to send txpkts now. 3317 */ 3318 send_txpkts: 3319 MPASS(txp->npkt > 0); 3320 for (i = 0; i < txp->npkt; i++) 3321 ETHER_BPF_MTAP(ifp, txp->mb[i]); 3322 if (txp->npkt > 1) { 3323 MPASS(avail >= tx_len16_to_desc(txp->len16)); 3324 if (vi->flags & TX_USES_VM_WR) 3325 n = write_txpkts_vm_wr(sc, txq); 3326 else 3327 n = write_txpkts_wr(sc, txq); 3328 } else { 3329 MPASS(avail >= 3330 tx_len16_to_desc(mbuf_len16(txp->mb[0]))); 3331 if (vi->flags & TX_USES_VM_WR) 3332 n = write_txpkt_vm_wr(sc, txq, txp->mb[0]); 3333 else 3334 n = write_txpkt_wr(sc, txq, txp->mb[0], avail); 3335 } 3336 MPASS(n <= SGE_MAX_WR_NDESC); 3337 wr = &eq->desc[eq->pidx]; 3338 IDXINCR(eq->pidx, n, eq->sidx); 3339 txp->npkt = 0; /* emptied */ 3340 3341 MPASS(wr_can_update_eq(wr)); 3342 set_txupdate_flags(txq, avail - n, wr); 3343 ring_eq_db(sc, eq, n); 3344 reclaim_tx_descs(txq, 32); 3345 } 3346 *coalescing = txp->npkt > 0; 3347 3348 return (total); 3349 } 3350 3351 static inline void 3352 init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int pktc_idx, 3353 int qsize, int intr_idx, int cong) 3354 { 3355 3356 KASSERT(tmr_idx >= 0 && tmr_idx < SGE_NTIMERS, 3357 ("%s: bad tmr_idx %d", __func__, tmr_idx)); 3358 KASSERT(pktc_idx < SGE_NCOUNTERS, /* -ve is ok, means don't use */ 3359 ("%s: bad pktc_idx %d", __func__, pktc_idx)); 3360 KASSERT(intr_idx >= -1 && intr_idx < sc->intr_count, 3361 ("%s: bad intr_idx %d", __func__, intr_idx)); 3362 3363 iq->flags = 0; 3364 iq->state = IQS_DISABLED; 3365 iq->adapter = sc; 3366 iq->intr_params = V_QINTR_TIMER_IDX(tmr_idx); 3367 iq->intr_pktc_idx = SGE_NCOUNTERS - 1; 3368 if (pktc_idx >= 0) { 3369 iq->intr_params |= F_QINTR_CNT_EN; 3370 iq->intr_pktc_idx = pktc_idx; 3371 } 3372 iq->qsize = roundup2(qsize, 16); /* See FW_IQ_CMD/iqsize */ 3373 iq->sidx = iq->qsize - sc->params.sge.spg_len / IQ_ESIZE; 3374 iq->intr_idx = intr_idx; 3375 iq->cong = cong; 3376 } 3377 3378 static inline void 3379 init_fl(struct adapter *sc, struct sge_fl *fl, int qsize, int maxp, char *name) 3380 { 3381 struct sge_params *sp = &sc->params.sge; 3382 3383 fl->qsize = qsize; 3384 fl->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE; 3385 strlcpy(fl->lockname, name, sizeof(fl->lockname)); 3386 mtx_init(&fl->fl_lock, fl->lockname, NULL, MTX_DEF); 3387 if (sc->flags & BUF_PACKING_OK && 3388 ((!is_t4(sc) && buffer_packing) || /* T5+: enabled unless 0 */ 3389 (is_t4(sc) && buffer_packing == 1)))/* T4: disabled unless 1 */ 3390 fl->flags |= FL_BUF_PACKING; 3391 fl->zidx = find_refill_source(sc, maxp, fl->flags & FL_BUF_PACKING); 3392 fl->safe_zidx = sc->sge.safe_zidx; 3393 if (fl->flags & FL_BUF_PACKING) { 3394 fl->lowat = roundup2(sp->fl_starve_threshold2, 8); 3395 fl->buf_boundary = sp->pack_boundary; 3396 } else { 3397 fl->lowat = roundup2(sp->fl_starve_threshold, 8); 3398 fl->buf_boundary = 16; 3399 } 3400 if (fl_pad && fl->buf_boundary < sp->pad_boundary) 3401 fl->buf_boundary = sp->pad_boundary; 3402 } 3403 3404 static inline void 3405 init_eq(struct adapter *sc, struct sge_eq *eq, int eqtype, int qsize, 3406 uint8_t tx_chan, struct sge_iq *iq, char *name) 3407 { 3408 KASSERT(eqtype >= EQ_CTRL && eqtype <= EQ_OFLD, 3409 ("%s: bad qtype %d", __func__, eqtype)); 3410 3411 eq->type = eqtype; 3412 eq->tx_chan = tx_chan; 3413 eq->iq = iq; 3414 eq->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE; 3415 strlcpy(eq->lockname, name, sizeof(eq->lockname)); 3416 mtx_init(&eq->eq_lock, eq->lockname, NULL, MTX_DEF); 3417 } 3418 3419 int 3420 alloc_ring(struct adapter *sc, size_t len, bus_dma_tag_t *tag, 3421 bus_dmamap_t *map, bus_addr_t *pa, void **va) 3422 { 3423 int rc; 3424 3425 rc = bus_dma_tag_create(sc->dmat, 512, 0, BUS_SPACE_MAXADDR, 3426 BUS_SPACE_MAXADDR, NULL, NULL, len, 1, len, 0, NULL, NULL, tag); 3427 if (rc != 0) { 3428 CH_ERR(sc, "cannot allocate DMA tag: %d\n", rc); 3429 goto done; 3430 } 3431 3432 rc = bus_dmamem_alloc(*tag, va, 3433 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, map); 3434 if (rc != 0) { 3435 CH_ERR(sc, "cannot allocate DMA memory: %d\n", rc); 3436 goto done; 3437 } 3438 3439 rc = bus_dmamap_load(*tag, *map, *va, len, oneseg_dma_callback, pa, 0); 3440 if (rc != 0) { 3441 CH_ERR(sc, "cannot load DMA map: %d\n", rc); 3442 goto done; 3443 } 3444 done: 3445 if (rc) 3446 free_ring(sc, *tag, *map, *pa, *va); 3447 3448 return (rc); 3449 } 3450 3451 int 3452 free_ring(struct adapter *sc, bus_dma_tag_t tag, bus_dmamap_t map, 3453 bus_addr_t pa, void *va) 3454 { 3455 if (pa) 3456 bus_dmamap_unload(tag, map); 3457 if (va) 3458 bus_dmamem_free(tag, va, map); 3459 if (tag) 3460 bus_dma_tag_destroy(tag); 3461 3462 return (0); 3463 } 3464 3465 /* 3466 * Allocates the software resources (mainly memory and sysctl nodes) for an 3467 * ingress queue and an optional freelist. 3468 * 3469 * Sets IQ_SW_ALLOCATED and returns 0 on success. 3470 */ 3471 static int 3472 alloc_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl, 3473 struct sysctl_ctx_list *ctx, struct sysctl_oid *oid) 3474 { 3475 int rc; 3476 size_t len; 3477 struct adapter *sc = vi->adapter; 3478 3479 MPASS(!(iq->flags & IQ_SW_ALLOCATED)); 3480 3481 len = iq->qsize * IQ_ESIZE; 3482 rc = alloc_ring(sc, len, &iq->desc_tag, &iq->desc_map, &iq->ba, 3483 (void **)&iq->desc); 3484 if (rc != 0) 3485 return (rc); 3486 3487 if (fl) { 3488 len = fl->qsize * EQ_ESIZE; 3489 rc = alloc_ring(sc, len, &fl->desc_tag, &fl->desc_map, 3490 &fl->ba, (void **)&fl->desc); 3491 if (rc) { 3492 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, 3493 iq->desc); 3494 return (rc); 3495 } 3496 3497 /* Allocate space for one software descriptor per buffer. */ 3498 fl->sdesc = malloc(fl->sidx * 8 * sizeof(struct fl_sdesc), 3499 M_CXGBE, M_ZERO | M_WAITOK); 3500 3501 add_fl_sysctls(sc, ctx, oid, fl); 3502 iq->flags |= IQ_HAS_FL; 3503 } 3504 add_iq_sysctls(ctx, oid, iq); 3505 iq->flags |= IQ_SW_ALLOCATED; 3506 3507 return (0); 3508 } 3509 3510 /* 3511 * Frees all software resources (memory and locks) associated with an ingress 3512 * queue and an optional freelist. 3513 */ 3514 static void 3515 free_iq_fl(struct adapter *sc, struct sge_iq *iq, struct sge_fl *fl) 3516 { 3517 MPASS(iq->flags & IQ_SW_ALLOCATED); 3518 3519 if (fl) { 3520 MPASS(iq->flags & IQ_HAS_FL); 3521 free_ring(sc, fl->desc_tag, fl->desc_map, fl->ba, fl->desc); 3522 free_fl_buffers(sc, fl); 3523 free(fl->sdesc, M_CXGBE); 3524 mtx_destroy(&fl->fl_lock); 3525 bzero(fl, sizeof(*fl)); 3526 } 3527 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, iq->desc); 3528 bzero(iq, sizeof(*iq)); 3529 } 3530 3531 /* 3532 * Allocates a hardware ingress queue and an optional freelist that will be 3533 * associated with it. 3534 * 3535 * Returns errno on failure. Resources allocated up to that point may still be 3536 * allocated. Caller is responsible for cleanup in case this function fails. 3537 */ 3538 static int 3539 alloc_iq_fl_hwq(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl) 3540 { 3541 int rc, i, cntxt_id; 3542 struct fw_iq_cmd c; 3543 struct adapter *sc = vi->adapter; 3544 __be32 v = 0; 3545 3546 MPASS (!(iq->flags & IQ_HW_ALLOCATED)); 3547 3548 bzero(&c, sizeof(c)); 3549 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 3550 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) | 3551 V_FW_IQ_CMD_VFN(0)); 3552 3553 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART | 3554 FW_LEN16(c)); 3555 3556 /* Special handling for firmware event queue */ 3557 if (iq == &sc->sge.fwq) 3558 v |= F_FW_IQ_CMD_IQASYNCH; 3559 3560 if (iq->intr_idx < 0) { 3561 /* Forwarded interrupts, all headed to fwq */ 3562 v |= F_FW_IQ_CMD_IQANDST; 3563 v |= V_FW_IQ_CMD_IQANDSTINDEX(sc->sge.fwq.cntxt_id); 3564 } else { 3565 KASSERT(iq->intr_idx < sc->intr_count, 3566 ("%s: invalid direct intr_idx %d", __func__, iq->intr_idx)); 3567 v |= V_FW_IQ_CMD_IQANDSTINDEX(iq->intr_idx); 3568 } 3569 3570 bzero(iq->desc, iq->qsize * IQ_ESIZE); 3571 c.type_to_iqandstindex = htobe32(v | 3572 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) | 3573 V_FW_IQ_CMD_VIID(vi->viid) | 3574 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT)); 3575 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(vi->pi->tx_chan) | 3576 F_FW_IQ_CMD_IQGTSMODE | 3577 V_FW_IQ_CMD_IQINTCNTTHRESH(iq->intr_pktc_idx) | 3578 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4)); 3579 c.iqsize = htobe16(iq->qsize); 3580 c.iqaddr = htobe64(iq->ba); 3581 if (iq->cong >= 0) 3582 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN); 3583 3584 if (fl) { 3585 bzero(fl->desc, fl->sidx * EQ_ESIZE + sc->params.sge.spg_len); 3586 c.iqns_to_fl0congen |= 3587 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) | 3588 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO | 3589 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) | 3590 (fl->flags & FL_BUF_PACKING ? F_FW_IQ_CMD_FL0PACKEN : 3591 0)); 3592 if (iq->cong >= 0) { 3593 c.iqns_to_fl0congen |= 3594 htobe32(V_FW_IQ_CMD_FL0CNGCHMAP(iq->cong) | 3595 F_FW_IQ_CMD_FL0CONGCIF | 3596 F_FW_IQ_CMD_FL0CONGEN); 3597 } 3598 c.fl0dcaen_to_fl0cidxfthresh = 3599 htobe16(V_FW_IQ_CMD_FL0FBMIN(chip_id(sc) <= CHELSIO_T5 ? 3600 X_FETCHBURSTMIN_128B : X_FETCHBURSTMIN_64B_T6) | 3601 V_FW_IQ_CMD_FL0FBMAX(chip_id(sc) <= CHELSIO_T5 ? 3602 X_FETCHBURSTMAX_512B : X_FETCHBURSTMAX_256B)); 3603 c.fl0size = htobe16(fl->qsize); 3604 c.fl0addr = htobe64(fl->ba); 3605 } 3606 3607 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3608 if (rc != 0) { 3609 CH_ERR(sc, "failed to create hw ingress queue: %d\n", rc); 3610 return (rc); 3611 } 3612 3613 iq->cidx = 0; 3614 iq->gen = F_RSPD_GEN; 3615 iq->cntxt_id = be16toh(c.iqid); 3616 iq->abs_id = be16toh(c.physiqid); 3617 3618 cntxt_id = iq->cntxt_id - sc->sge.iq_start; 3619 if (cntxt_id >= sc->sge.iqmap_sz) { 3620 panic ("%s: iq->cntxt_id (%d) more than the max (%d)", __func__, 3621 cntxt_id, sc->sge.iqmap_sz - 1); 3622 } 3623 sc->sge.iqmap[cntxt_id] = iq; 3624 3625 if (fl) { 3626 u_int qid; 3627 #ifdef INVARIANTS 3628 MPASS(!(fl->flags & FL_BUF_RESUME)); 3629 for (i = 0; i < fl->sidx * 8; i++) 3630 MPASS(fl->sdesc[i].cl == NULL); 3631 #endif 3632 fl->cntxt_id = be16toh(c.fl0id); 3633 fl->pidx = fl->cidx = fl->hw_cidx = fl->dbidx = 0; 3634 fl->rx_offset = 0; 3635 fl->flags &= ~(FL_STARVING | FL_DOOMED); 3636 3637 cntxt_id = fl->cntxt_id - sc->sge.eq_start; 3638 if (cntxt_id >= sc->sge.eqmap_sz) { 3639 panic("%s: fl->cntxt_id (%d) more than the max (%d)", 3640 __func__, cntxt_id, sc->sge.eqmap_sz - 1); 3641 } 3642 sc->sge.eqmap[cntxt_id] = (void *)fl; 3643 3644 qid = fl->cntxt_id; 3645 if (isset(&sc->doorbells, DOORBELL_UDB)) { 3646 uint32_t s_qpp = sc->params.sge.eq_s_qpp; 3647 uint32_t mask = (1 << s_qpp) - 1; 3648 volatile uint8_t *udb; 3649 3650 udb = sc->udbs_base + UDBS_DB_OFFSET; 3651 udb += (qid >> s_qpp) << PAGE_SHIFT; 3652 qid &= mask; 3653 if (qid < PAGE_SIZE / UDBS_SEG_SIZE) { 3654 udb += qid << UDBS_SEG_SHIFT; 3655 qid = 0; 3656 } 3657 fl->udb = (volatile void *)udb; 3658 } 3659 fl->dbval = V_QID(qid) | sc->chip_params->sge_fl_db; 3660 3661 FL_LOCK(fl); 3662 /* Enough to make sure the SGE doesn't think it's starved */ 3663 refill_fl(sc, fl, fl->lowat); 3664 FL_UNLOCK(fl); 3665 } 3666 3667 if (chip_id(sc) >= CHELSIO_T5 && !(sc->flags & IS_VF) && iq->cong >= 0) { 3668 uint32_t param, val; 3669 3670 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 3671 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) | 3672 V_FW_PARAMS_PARAM_YZ(iq->cntxt_id); 3673 if (iq->cong == 0) 3674 val = 1 << 19; 3675 else { 3676 val = 2 << 19; 3677 for (i = 0; i < 4; i++) { 3678 if (iq->cong & (1 << i)) 3679 val |= 1 << (i << 2); 3680 } 3681 } 3682 3683 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 3684 if (rc != 0) { 3685 /* report error but carry on */ 3686 CH_ERR(sc, "failed to set congestion manager context " 3687 "for ingress queue %d: %d\n", iq->cntxt_id, rc); 3688 } 3689 } 3690 3691 /* Enable IQ interrupts */ 3692 atomic_store_rel_int(&iq->state, IQS_IDLE); 3693 t4_write_reg(sc, sc->sge_gts_reg, V_SEINTARM(iq->intr_params) | 3694 V_INGRESSQID(iq->cntxt_id)); 3695 3696 iq->flags |= IQ_HW_ALLOCATED; 3697 3698 return (0); 3699 } 3700 3701 static int 3702 free_iq_fl_hwq(struct adapter *sc, struct sge_iq *iq, struct sge_fl *fl) 3703 { 3704 int rc; 3705 3706 MPASS(iq->flags & IQ_HW_ALLOCATED); 3707 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0, FW_IQ_TYPE_FL_INT_CAP, 3708 iq->cntxt_id, fl ? fl->cntxt_id : 0xffff, 0xffff); 3709 if (rc != 0) { 3710 CH_ERR(sc, "failed to free iq %p: %d\n", iq, rc); 3711 return (rc); 3712 } 3713 iq->flags &= ~IQ_HW_ALLOCATED; 3714 3715 return (0); 3716 } 3717 3718 static void 3719 add_iq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid, 3720 struct sge_iq *iq) 3721 { 3722 struct sysctl_oid_list *children; 3723 3724 if (ctx == NULL || oid == NULL) 3725 return; 3726 3727 children = SYSCTL_CHILDREN(oid); 3728 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, &iq->ba, 3729 "bus address of descriptor ring"); 3730 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3731 iq->qsize * IQ_ESIZE, "descriptor ring size in bytes"); 3732 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "abs_id", CTLFLAG_RD, 3733 &iq->abs_id, 0, "absolute id of the queue"); 3734 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 3735 &iq->cntxt_id, 0, "SGE context id of the queue"); 3736 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &iq->cidx, 3737 0, "consumer index"); 3738 } 3739 3740 static void 3741 add_fl_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx, 3742 struct sysctl_oid *oid, struct sge_fl *fl) 3743 { 3744 struct sysctl_oid_list *children; 3745 3746 if (ctx == NULL || oid == NULL) 3747 return; 3748 3749 children = SYSCTL_CHILDREN(oid); 3750 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", 3751 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "freelist"); 3752 children = SYSCTL_CHILDREN(oid); 3753 3754 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, 3755 &fl->ba, "bus address of descriptor ring"); 3756 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3757 fl->sidx * EQ_ESIZE + sc->params.sge.spg_len, 3758 "desc ring size in bytes"); 3759 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 3760 &fl->cntxt_id, 0, "SGE context id of the freelist"); 3761 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "padding", CTLFLAG_RD, NULL, 3762 fl_pad ? 1 : 0, "padding enabled"); 3763 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "packing", CTLFLAG_RD, NULL, 3764 fl->flags & FL_BUF_PACKING ? 1 : 0, "packing enabled"); 3765 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &fl->cidx, 3766 0, "consumer index"); 3767 if (fl->flags & FL_BUF_PACKING) { 3768 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rx_offset", 3769 CTLFLAG_RD, &fl->rx_offset, 0, "packing rx offset"); 3770 } 3771 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &fl->pidx, 3772 0, "producer index"); 3773 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_allocated", 3774 CTLFLAG_RD, &fl->cl_allocated, "# of clusters allocated"); 3775 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_recycled", 3776 CTLFLAG_RD, &fl->cl_recycled, "# of clusters recycled"); 3777 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_fast_recycled", 3778 CTLFLAG_RD, &fl->cl_fast_recycled, "# of clusters recycled (fast)"); 3779 } 3780 3781 /* 3782 * Idempotent. 3783 */ 3784 static int 3785 alloc_fwq(struct adapter *sc) 3786 { 3787 int rc, intr_idx; 3788 struct sge_iq *fwq = &sc->sge.fwq; 3789 struct vi_info *vi = &sc->port[0]->vi[0]; 3790 3791 if (!(fwq->flags & IQ_SW_ALLOCATED)) { 3792 MPASS(!(fwq->flags & IQ_HW_ALLOCATED)); 3793 3794 if (sc->flags & IS_VF) 3795 intr_idx = 0; 3796 else 3797 intr_idx = sc->intr_count > 1 ? 1 : 0; 3798 init_iq(fwq, sc, 0, 0, FW_IQ_QSIZE, intr_idx, -1); 3799 rc = alloc_iq_fl(vi, fwq, NULL, &sc->ctx, sc->fwq_oid); 3800 if (rc != 0) { 3801 CH_ERR(sc, "failed to allocate fwq: %d\n", rc); 3802 return (rc); 3803 } 3804 MPASS(fwq->flags & IQ_SW_ALLOCATED); 3805 } 3806 3807 if (!(fwq->flags & IQ_HW_ALLOCATED)) { 3808 MPASS(fwq->flags & IQ_SW_ALLOCATED); 3809 3810 rc = alloc_iq_fl_hwq(vi, fwq, NULL); 3811 if (rc != 0) { 3812 CH_ERR(sc, "failed to create hw fwq: %d\n", rc); 3813 return (rc); 3814 } 3815 MPASS(fwq->flags & IQ_HW_ALLOCATED); 3816 } 3817 3818 return (0); 3819 } 3820 3821 /* 3822 * Idempotent. 3823 */ 3824 static void 3825 free_fwq(struct adapter *sc) 3826 { 3827 struct sge_iq *fwq = &sc->sge.fwq; 3828 3829 if (fwq->flags & IQ_HW_ALLOCATED) { 3830 MPASS(fwq->flags & IQ_SW_ALLOCATED); 3831 free_iq_fl_hwq(sc, fwq, NULL); 3832 MPASS(!(fwq->flags & IQ_HW_ALLOCATED)); 3833 } 3834 3835 if (fwq->flags & IQ_SW_ALLOCATED) { 3836 MPASS(!(fwq->flags & IQ_HW_ALLOCATED)); 3837 free_iq_fl(sc, fwq, NULL); 3838 MPASS(!(fwq->flags & IQ_SW_ALLOCATED)); 3839 } 3840 } 3841 3842 /* 3843 * Idempotent. 3844 */ 3845 static int 3846 alloc_ctrlq(struct adapter *sc, int idx) 3847 { 3848 int rc; 3849 char name[16]; 3850 struct sysctl_oid *oid; 3851 struct sge_wrq *ctrlq = &sc->sge.ctrlq[idx]; 3852 3853 MPASS(idx < sc->params.nports); 3854 3855 if (!(ctrlq->eq.flags & EQ_SW_ALLOCATED)) { 3856 MPASS(!(ctrlq->eq.flags & EQ_HW_ALLOCATED)); 3857 3858 snprintf(name, sizeof(name), "%d", idx); 3859 oid = SYSCTL_ADD_NODE(&sc->ctx, SYSCTL_CHILDREN(sc->ctrlq_oid), 3860 OID_AUTO, name, CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 3861 "ctrl queue"); 3862 3863 snprintf(name, sizeof(name), "%s ctrlq%d", 3864 device_get_nameunit(sc->dev), idx); 3865 init_eq(sc, &ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE, 3866 sc->port[idx]->tx_chan, &sc->sge.fwq, name); 3867 rc = alloc_wrq(sc, NULL, ctrlq, &sc->ctx, oid); 3868 if (rc != 0) { 3869 CH_ERR(sc, "failed to allocate ctrlq%d: %d\n", idx, rc); 3870 sysctl_remove_oid(oid, 1, 1); 3871 return (rc); 3872 } 3873 MPASS(ctrlq->eq.flags & EQ_SW_ALLOCATED); 3874 } 3875 3876 if (!(ctrlq->eq.flags & EQ_HW_ALLOCATED)) { 3877 MPASS(ctrlq->eq.flags & EQ_SW_ALLOCATED); 3878 3879 rc = alloc_eq_hwq(sc, NULL, &ctrlq->eq); 3880 if (rc != 0) { 3881 CH_ERR(sc, "failed to create hw ctrlq%d: %d\n", idx, rc); 3882 return (rc); 3883 } 3884 MPASS(ctrlq->eq.flags & EQ_HW_ALLOCATED); 3885 } 3886 3887 return (0); 3888 } 3889 3890 /* 3891 * Idempotent. 3892 */ 3893 static void 3894 free_ctrlq(struct adapter *sc, int idx) 3895 { 3896 struct sge_wrq *ctrlq = &sc->sge.ctrlq[idx]; 3897 3898 if (ctrlq->eq.flags & EQ_HW_ALLOCATED) { 3899 MPASS(ctrlq->eq.flags & EQ_SW_ALLOCATED); 3900 free_eq_hwq(sc, NULL, &ctrlq->eq); 3901 MPASS(!(ctrlq->eq.flags & EQ_HW_ALLOCATED)); 3902 } 3903 3904 if (ctrlq->eq.flags & EQ_SW_ALLOCATED) { 3905 MPASS(!(ctrlq->eq.flags & EQ_HW_ALLOCATED)); 3906 free_wrq(sc, ctrlq); 3907 MPASS(!(ctrlq->eq.flags & EQ_SW_ALLOCATED)); 3908 } 3909 } 3910 3911 int 3912 tnl_cong(struct port_info *pi, int drop) 3913 { 3914 3915 if (drop == -1) 3916 return (-1); 3917 else if (drop == 1) 3918 return (0); 3919 else 3920 return (pi->rx_e_chan_map); 3921 } 3922 3923 /* 3924 * Idempotent. 3925 */ 3926 static int 3927 alloc_rxq(struct vi_info *vi, struct sge_rxq *rxq, int idx, int intr_idx, 3928 int maxp) 3929 { 3930 int rc; 3931 struct adapter *sc = vi->adapter; 3932 struct ifnet *ifp = vi->ifp; 3933 struct sysctl_oid *oid; 3934 char name[16]; 3935 3936 if (!(rxq->iq.flags & IQ_SW_ALLOCATED)) { 3937 MPASS(!(rxq->iq.flags & IQ_HW_ALLOCATED)); 3938 #if defined(INET) || defined(INET6) 3939 rc = tcp_lro_init_args(&rxq->lro, ifp, lro_entries, lro_mbufs); 3940 if (rc != 0) 3941 return (rc); 3942 MPASS(rxq->lro.ifp == ifp); /* also indicates LRO init'ed */ 3943 #endif 3944 rxq->ifp = ifp; 3945 3946 snprintf(name, sizeof(name), "%d", idx); 3947 oid = SYSCTL_ADD_NODE(&vi->ctx, SYSCTL_CHILDREN(vi->rxq_oid), 3948 OID_AUTO, name, CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 3949 "rx queue"); 3950 3951 init_iq(&rxq->iq, sc, vi->tmr_idx, vi->pktc_idx, vi->qsize_rxq, 3952 intr_idx, tnl_cong(vi->pi, cong_drop)); 3953 #if defined(INET) || defined(INET6) 3954 if (ifp->if_capenable & IFCAP_LRO) 3955 rxq->iq.flags |= IQ_LRO_ENABLED; 3956 #endif 3957 if (ifp->if_capenable & IFCAP_HWRXTSTMP) 3958 rxq->iq.flags |= IQ_RX_TIMESTAMP; 3959 snprintf(name, sizeof(name), "%s rxq%d-fl", 3960 device_get_nameunit(vi->dev), idx); 3961 init_fl(sc, &rxq->fl, vi->qsize_rxq / 8, maxp, name); 3962 rc = alloc_iq_fl(vi, &rxq->iq, &rxq->fl, &vi->ctx, oid); 3963 if (rc != 0) { 3964 CH_ERR(vi, "failed to allocate rxq%d: %d\n", idx, rc); 3965 sysctl_remove_oid(oid, 1, 1); 3966 #if defined(INET) || defined(INET6) 3967 tcp_lro_free(&rxq->lro); 3968 rxq->lro.ifp = NULL; 3969 #endif 3970 return (rc); 3971 } 3972 MPASS(rxq->iq.flags & IQ_SW_ALLOCATED); 3973 add_rxq_sysctls(&vi->ctx, oid, rxq); 3974 } 3975 3976 if (!(rxq->iq.flags & IQ_HW_ALLOCATED)) { 3977 MPASS(rxq->iq.flags & IQ_SW_ALLOCATED); 3978 rc = alloc_iq_fl_hwq(vi, &rxq->iq, &rxq->fl); 3979 if (rc != 0) { 3980 CH_ERR(vi, "failed to create hw rxq%d: %d\n", idx, rc); 3981 return (rc); 3982 } 3983 MPASS(rxq->iq.flags & IQ_HW_ALLOCATED); 3984 3985 if (idx == 0) 3986 sc->sge.iq_base = rxq->iq.abs_id - rxq->iq.cntxt_id; 3987 else 3988 KASSERT(rxq->iq.cntxt_id + sc->sge.iq_base == rxq->iq.abs_id, 3989 ("iq_base mismatch")); 3990 KASSERT(sc->sge.iq_base == 0 || sc->flags & IS_VF, 3991 ("PF with non-zero iq_base")); 3992 3993 /* 3994 * The freelist is just barely above the starvation threshold 3995 * right now, fill it up a bit more. 3996 */ 3997 FL_LOCK(&rxq->fl); 3998 refill_fl(sc, &rxq->fl, 128); 3999 FL_UNLOCK(&rxq->fl); 4000 } 4001 4002 return (0); 4003 } 4004 4005 /* 4006 * Idempotent. 4007 */ 4008 static void 4009 free_rxq(struct vi_info *vi, struct sge_rxq *rxq) 4010 { 4011 if (rxq->iq.flags & IQ_HW_ALLOCATED) { 4012 MPASS(rxq->iq.flags & IQ_SW_ALLOCATED); 4013 free_iq_fl_hwq(vi->adapter, &rxq->iq, &rxq->fl); 4014 MPASS(!(rxq->iq.flags & IQ_HW_ALLOCATED)); 4015 } 4016 4017 if (rxq->iq.flags & IQ_SW_ALLOCATED) { 4018 MPASS(!(rxq->iq.flags & IQ_HW_ALLOCATED)); 4019 #if defined(INET) || defined(INET6) 4020 tcp_lro_free(&rxq->lro); 4021 #endif 4022 free_iq_fl(vi->adapter, &rxq->iq, &rxq->fl); 4023 MPASS(!(rxq->iq.flags & IQ_SW_ALLOCATED)); 4024 bzero(rxq, sizeof(*rxq)); 4025 } 4026 } 4027 4028 static void 4029 add_rxq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid, 4030 struct sge_rxq *rxq) 4031 { 4032 struct sysctl_oid_list *children; 4033 4034 if (ctx == NULL || oid == NULL) 4035 return; 4036 4037 children = SYSCTL_CHILDREN(oid); 4038 #if defined(INET) || defined(INET6) 4039 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "lro_queued", CTLFLAG_RD, 4040 &rxq->lro.lro_queued, 0, NULL); 4041 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "lro_flushed", CTLFLAG_RD, 4042 &rxq->lro.lro_flushed, 0, NULL); 4043 #endif 4044 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "rxcsum", CTLFLAG_RD, 4045 &rxq->rxcsum, "# of times hardware assisted with checksum"); 4046 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "vlan_extraction", CTLFLAG_RD, 4047 &rxq->vlan_extraction, "# of times hardware extracted 802.1Q tag"); 4048 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "vxlan_rxcsum", CTLFLAG_RD, 4049 &rxq->vxlan_rxcsum, 4050 "# of times hardware assisted with inner checksum (VXLAN)"); 4051 } 4052 4053 #ifdef TCP_OFFLOAD 4054 /* 4055 * Idempotent. 4056 */ 4057 static int 4058 alloc_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq, int idx, 4059 int intr_idx, int maxp) 4060 { 4061 int rc; 4062 struct adapter *sc = vi->adapter; 4063 struct sysctl_oid *oid; 4064 char name[16]; 4065 4066 if (!(ofld_rxq->iq.flags & IQ_SW_ALLOCATED)) { 4067 MPASS(!(ofld_rxq->iq.flags & IQ_HW_ALLOCATED)); 4068 4069 snprintf(name, sizeof(name), "%d", idx); 4070 oid = SYSCTL_ADD_NODE(&vi->ctx, 4071 SYSCTL_CHILDREN(vi->ofld_rxq_oid), OID_AUTO, name, 4072 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "offload rx queue"); 4073 4074 init_iq(&ofld_rxq->iq, sc, vi->ofld_tmr_idx, vi->ofld_pktc_idx, 4075 vi->qsize_rxq, intr_idx, 0); 4076 snprintf(name, sizeof(name), "%s ofld_rxq%d-fl", 4077 device_get_nameunit(vi->dev), idx); 4078 init_fl(sc, &ofld_rxq->fl, vi->qsize_rxq / 8, maxp, name); 4079 rc = alloc_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl, &vi->ctx, 4080 oid); 4081 if (rc != 0) { 4082 CH_ERR(vi, "failed to allocate ofld_rxq%d: %d\n", idx, 4083 rc); 4084 sysctl_remove_oid(oid, 1, 1); 4085 return (rc); 4086 } 4087 MPASS(ofld_rxq->iq.flags & IQ_SW_ALLOCATED); 4088 ofld_rxq->rx_iscsi_ddp_setup_ok = counter_u64_alloc(M_WAITOK); 4089 ofld_rxq->rx_iscsi_ddp_setup_error = 4090 counter_u64_alloc(M_WAITOK); 4091 add_ofld_rxq_sysctls(&vi->ctx, oid, ofld_rxq); 4092 } 4093 4094 if (!(ofld_rxq->iq.flags & IQ_HW_ALLOCATED)) { 4095 MPASS(ofld_rxq->iq.flags & IQ_SW_ALLOCATED); 4096 rc = alloc_iq_fl_hwq(vi, &ofld_rxq->iq, &ofld_rxq->fl); 4097 if (rc != 0) { 4098 CH_ERR(vi, "failed to create hw ofld_rxq%d: %d\n", idx, 4099 rc); 4100 return (rc); 4101 } 4102 MPASS(ofld_rxq->iq.flags & IQ_HW_ALLOCATED); 4103 } 4104 return (rc); 4105 } 4106 4107 /* 4108 * Idempotent. 4109 */ 4110 static void 4111 free_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq) 4112 { 4113 if (ofld_rxq->iq.flags & IQ_HW_ALLOCATED) { 4114 MPASS(ofld_rxq->iq.flags & IQ_SW_ALLOCATED); 4115 free_iq_fl_hwq(vi->adapter, &ofld_rxq->iq, &ofld_rxq->fl); 4116 MPASS(!(ofld_rxq->iq.flags & IQ_HW_ALLOCATED)); 4117 } 4118 4119 if (ofld_rxq->iq.flags & IQ_SW_ALLOCATED) { 4120 MPASS(!(ofld_rxq->iq.flags & IQ_HW_ALLOCATED)); 4121 free_iq_fl(vi->adapter, &ofld_rxq->iq, &ofld_rxq->fl); 4122 MPASS(!(ofld_rxq->iq.flags & IQ_SW_ALLOCATED)); 4123 counter_u64_free(ofld_rxq->rx_iscsi_ddp_setup_ok); 4124 counter_u64_free(ofld_rxq->rx_iscsi_ddp_setup_error); 4125 bzero(ofld_rxq, sizeof(*ofld_rxq)); 4126 } 4127 } 4128 4129 static void 4130 add_ofld_rxq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid, 4131 struct sge_ofld_rxq *ofld_rxq) 4132 { 4133 struct sysctl_oid_list *children; 4134 4135 if (ctx == NULL || oid == NULL) 4136 return; 4137 4138 children = SYSCTL_CHILDREN(oid); 4139 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 4140 "rx_toe_tls_records", CTLFLAG_RD, &ofld_rxq->rx_toe_tls_records, 4141 "# of TOE TLS records received"); 4142 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 4143 "rx_toe_tls_octets", CTLFLAG_RD, &ofld_rxq->rx_toe_tls_octets, 4144 "# of payload octets in received TOE TLS records"); 4145 4146 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "iscsi", 4147 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TOE iSCSI statistics"); 4148 children = SYSCTL_CHILDREN(oid); 4149 4150 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "ddp_setup_ok", 4151 CTLFLAG_RD, &ofld_rxq->rx_iscsi_ddp_setup_ok, 4152 "# of times DDP buffer was setup successfully."); 4153 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "ddp_setup_error", 4154 CTLFLAG_RD, &ofld_rxq->rx_iscsi_ddp_setup_error, 4155 "# of times DDP buffer setup failed."); 4156 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "ddp_octets", 4157 CTLFLAG_RD, &ofld_rxq->rx_iscsi_ddp_octets, 0, 4158 "# of octets placed directly"); 4159 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "ddp_pdus", 4160 CTLFLAG_RD, &ofld_rxq->rx_iscsi_ddp_pdus, 0, 4161 "# of PDUs with data placed directly."); 4162 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "fl_octets", 4163 CTLFLAG_RD, &ofld_rxq->rx_iscsi_fl_octets, 0, 4164 "# of data octets delivered in freelist"); 4165 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "fl_pdus", 4166 CTLFLAG_RD, &ofld_rxq->rx_iscsi_fl_pdus, 0, 4167 "# of PDUs with data delivered in freelist"); 4168 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "padding_errors", 4169 CTLFLAG_RD, &ofld_rxq->rx_iscsi_padding_errors, 0, 4170 "# of PDUs with invalid padding"); 4171 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "header_digest_errors", 4172 CTLFLAG_RD, &ofld_rxq->rx_iscsi_header_digest_errors, 0, 4173 "# of PDUs with invalid header digests"); 4174 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "data_digest_errors", 4175 CTLFLAG_RD, &ofld_rxq->rx_iscsi_data_digest_errors, 0, 4176 "# of PDUs with invalid data digests"); 4177 } 4178 #endif 4179 4180 /* 4181 * Returns a reasonable automatic cidx flush threshold for a given queue size. 4182 */ 4183 static u_int 4184 qsize_to_fthresh(int qsize) 4185 { 4186 u_int fthresh; 4187 4188 while (!powerof2(qsize)) 4189 qsize++; 4190 fthresh = ilog2(qsize); 4191 if (fthresh > X_CIDXFLUSHTHRESH_128) 4192 fthresh = X_CIDXFLUSHTHRESH_128; 4193 4194 return (fthresh); 4195 } 4196 4197 static int 4198 ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq) 4199 { 4200 int rc, cntxt_id; 4201 struct fw_eq_ctrl_cmd c; 4202 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 4203 4204 bzero(&c, sizeof(c)); 4205 4206 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | F_FW_CMD_REQUEST | 4207 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_CTRL_CMD_PFN(sc->pf) | 4208 V_FW_EQ_CTRL_CMD_VFN(0)); 4209 c.alloc_to_len16 = htobe32(F_FW_EQ_CTRL_CMD_ALLOC | 4210 F_FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c)); 4211 c.cmpliqid_eqid = htonl(V_FW_EQ_CTRL_CMD_CMPLIQID(eq->iqid)); 4212 c.physeqid_pkd = htobe32(0); 4213 c.fetchszm_to_iqid = 4214 htobe32(V_FW_EQ_CTRL_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 4215 V_FW_EQ_CTRL_CMD_PCIECHN(eq->tx_chan) | 4216 F_FW_EQ_CTRL_CMD_FETCHRO | V_FW_EQ_CTRL_CMD_IQID(eq->iqid)); 4217 c.dcaen_to_eqsize = 4218 htobe32(V_FW_EQ_CTRL_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ? 4219 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) | 4220 V_FW_EQ_CTRL_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 4221 V_FW_EQ_CTRL_CMD_CIDXFTHRESH(qsize_to_fthresh(qsize)) | 4222 V_FW_EQ_CTRL_CMD_EQSIZE(qsize)); 4223 c.eqaddr = htobe64(eq->ba); 4224 4225 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 4226 if (rc != 0) { 4227 CH_ERR(sc, "failed to create hw ctrlq for tx_chan %d: %d\n", 4228 eq->tx_chan, rc); 4229 return (rc); 4230 } 4231 4232 eq->cntxt_id = G_FW_EQ_CTRL_CMD_EQID(be32toh(c.cmpliqid_eqid)); 4233 eq->abs_id = G_FW_EQ_CTRL_CMD_PHYSEQID(be32toh(c.physeqid_pkd)); 4234 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 4235 if (cntxt_id >= sc->sge.eqmap_sz) 4236 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 4237 cntxt_id, sc->sge.eqmap_sz - 1); 4238 sc->sge.eqmap[cntxt_id] = eq; 4239 4240 return (rc); 4241 } 4242 4243 static int 4244 eth_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 4245 { 4246 int rc, cntxt_id; 4247 struct fw_eq_eth_cmd c; 4248 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 4249 4250 bzero(&c, sizeof(c)); 4251 4252 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST | 4253 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) | 4254 V_FW_EQ_ETH_CMD_VFN(0)); 4255 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC | 4256 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c)); 4257 c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE | 4258 F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(vi->viid)); 4259 c.fetchszm_to_iqid = 4260 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) | 4261 V_FW_EQ_ETH_CMD_PCIECHN(eq->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO | 4262 V_FW_EQ_ETH_CMD_IQID(eq->iqid)); 4263 c.dcaen_to_eqsize = 4264 htobe32(V_FW_EQ_ETH_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ? 4265 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) | 4266 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 4267 V_FW_EQ_ETH_CMD_EQSIZE(qsize)); 4268 c.eqaddr = htobe64(eq->ba); 4269 4270 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 4271 if (rc != 0) { 4272 device_printf(vi->dev, 4273 "failed to create Ethernet egress queue: %d\n", rc); 4274 return (rc); 4275 } 4276 4277 eq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd)); 4278 eq->abs_id = G_FW_EQ_ETH_CMD_PHYSEQID(be32toh(c.physeqid_pkd)); 4279 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 4280 if (cntxt_id >= sc->sge.eqmap_sz) 4281 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 4282 cntxt_id, sc->sge.eqmap_sz - 1); 4283 sc->sge.eqmap[cntxt_id] = eq; 4284 4285 return (rc); 4286 } 4287 4288 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 4289 static int 4290 ofld_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 4291 { 4292 int rc, cntxt_id; 4293 struct fw_eq_ofld_cmd c; 4294 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 4295 4296 bzero(&c, sizeof(c)); 4297 4298 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | F_FW_CMD_REQUEST | 4299 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_OFLD_CMD_PFN(sc->pf) | 4300 V_FW_EQ_OFLD_CMD_VFN(0)); 4301 c.alloc_to_len16 = htonl(F_FW_EQ_OFLD_CMD_ALLOC | 4302 F_FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c)); 4303 c.fetchszm_to_iqid = 4304 htonl(V_FW_EQ_OFLD_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 4305 V_FW_EQ_OFLD_CMD_PCIECHN(eq->tx_chan) | 4306 F_FW_EQ_OFLD_CMD_FETCHRO | V_FW_EQ_OFLD_CMD_IQID(eq->iqid)); 4307 c.dcaen_to_eqsize = 4308 htobe32(V_FW_EQ_OFLD_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ? 4309 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) | 4310 V_FW_EQ_OFLD_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 4311 V_FW_EQ_OFLD_CMD_CIDXFTHRESH(qsize_to_fthresh(qsize)) | 4312 V_FW_EQ_OFLD_CMD_EQSIZE(qsize)); 4313 c.eqaddr = htobe64(eq->ba); 4314 4315 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 4316 if (rc != 0) { 4317 device_printf(vi->dev, 4318 "failed to create egress queue for TCP offload: %d\n", rc); 4319 return (rc); 4320 } 4321 4322 eq->cntxt_id = G_FW_EQ_OFLD_CMD_EQID(be32toh(c.eqid_pkd)); 4323 eq->abs_id = G_FW_EQ_OFLD_CMD_PHYSEQID(be32toh(c.physeqid_pkd)); 4324 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 4325 if (cntxt_id >= sc->sge.eqmap_sz) 4326 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 4327 cntxt_id, sc->sge.eqmap_sz - 1); 4328 sc->sge.eqmap[cntxt_id] = eq; 4329 4330 return (rc); 4331 } 4332 #endif 4333 4334 /* SW only */ 4335 static int 4336 alloc_eq(struct adapter *sc, struct sge_eq *eq, struct sysctl_ctx_list *ctx, 4337 struct sysctl_oid *oid) 4338 { 4339 int rc, qsize; 4340 size_t len; 4341 4342 MPASS(!(eq->flags & EQ_SW_ALLOCATED)); 4343 4344 qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 4345 len = qsize * EQ_ESIZE; 4346 rc = alloc_ring(sc, len, &eq->desc_tag, &eq->desc_map, &eq->ba, 4347 (void **)&eq->desc); 4348 if (rc) 4349 return (rc); 4350 if (ctx != NULL && oid != NULL) 4351 add_eq_sysctls(sc, ctx, oid, eq); 4352 eq->flags |= EQ_SW_ALLOCATED; 4353 4354 return (0); 4355 } 4356 4357 /* SW only */ 4358 static void 4359 free_eq(struct adapter *sc, struct sge_eq *eq) 4360 { 4361 MPASS(eq->flags & EQ_SW_ALLOCATED); 4362 if (eq->type == EQ_ETH) 4363 MPASS(eq->pidx == eq->cidx); 4364 4365 free_ring(sc, eq->desc_tag, eq->desc_map, eq->ba, eq->desc); 4366 mtx_destroy(&eq->eq_lock); 4367 bzero(eq, sizeof(*eq)); 4368 } 4369 4370 static void 4371 add_eq_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx, 4372 struct sysctl_oid *oid, struct sge_eq *eq) 4373 { 4374 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 4375 4376 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, &eq->ba, 4377 "bus address of descriptor ring"); 4378 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 4379 eq->sidx * EQ_ESIZE + sc->params.sge.spg_len, 4380 "desc ring size in bytes"); 4381 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "abs_id", CTLFLAG_RD, 4382 &eq->abs_id, 0, "absolute id of the queue"); 4383 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 4384 &eq->cntxt_id, 0, "SGE context id of the queue"); 4385 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &eq->cidx, 4386 0, "consumer index"); 4387 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &eq->pidx, 4388 0, "producer index"); 4389 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL, 4390 eq->sidx, "status page index"); 4391 } 4392 4393 static int 4394 alloc_eq_hwq(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 4395 { 4396 int rc; 4397 4398 MPASS(!(eq->flags & EQ_HW_ALLOCATED)); 4399 4400 eq->iqid = eq->iq->cntxt_id; 4401 eq->pidx = eq->cidx = eq->dbidx = 0; 4402 /* Note that equeqidx is not used with sge_wrq (OFLD/CTRL) queues. */ 4403 eq->equeqidx = 0; 4404 eq->doorbells = sc->doorbells; 4405 bzero(eq->desc, eq->sidx * EQ_ESIZE + sc->params.sge.spg_len); 4406 4407 switch (eq->type) { 4408 case EQ_CTRL: 4409 rc = ctrl_eq_alloc(sc, eq); 4410 break; 4411 4412 case EQ_ETH: 4413 rc = eth_eq_alloc(sc, vi, eq); 4414 break; 4415 4416 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 4417 case EQ_OFLD: 4418 rc = ofld_eq_alloc(sc, vi, eq); 4419 break; 4420 #endif 4421 4422 default: 4423 panic("%s: invalid eq type %d.", __func__, eq->type); 4424 } 4425 if (rc != 0) { 4426 CH_ERR(sc, "failed to allocate egress queue(%d): %d\n", 4427 eq->type, rc); 4428 return (rc); 4429 } 4430 4431 if (isset(&eq->doorbells, DOORBELL_UDB) || 4432 isset(&eq->doorbells, DOORBELL_UDBWC) || 4433 isset(&eq->doorbells, DOORBELL_WCWR)) { 4434 uint32_t s_qpp = sc->params.sge.eq_s_qpp; 4435 uint32_t mask = (1 << s_qpp) - 1; 4436 volatile uint8_t *udb; 4437 4438 udb = sc->udbs_base + UDBS_DB_OFFSET; 4439 udb += (eq->cntxt_id >> s_qpp) << PAGE_SHIFT; /* pg offset */ 4440 eq->udb_qid = eq->cntxt_id & mask; /* id in page */ 4441 if (eq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE) 4442 clrbit(&eq->doorbells, DOORBELL_WCWR); 4443 else { 4444 udb += eq->udb_qid << UDBS_SEG_SHIFT; /* seg offset */ 4445 eq->udb_qid = 0; 4446 } 4447 eq->udb = (volatile void *)udb; 4448 } 4449 4450 eq->flags |= EQ_HW_ALLOCATED; 4451 return (0); 4452 } 4453 4454 static int 4455 free_eq_hwq(struct adapter *sc, struct vi_info *vi __unused, struct sge_eq *eq) 4456 { 4457 int rc; 4458 4459 MPASS(eq->flags & EQ_HW_ALLOCATED); 4460 4461 switch (eq->type) { 4462 case EQ_CTRL: 4463 rc = -t4_ctrl_eq_free(sc, sc->mbox, sc->pf, 0, eq->cntxt_id); 4464 break; 4465 case EQ_ETH: 4466 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0, eq->cntxt_id); 4467 break; 4468 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 4469 case EQ_OFLD: 4470 rc = -t4_ofld_eq_free(sc, sc->mbox, sc->pf, 0, eq->cntxt_id); 4471 break; 4472 #endif 4473 default: 4474 panic("%s: invalid eq type %d.", __func__, eq->type); 4475 } 4476 if (rc != 0) { 4477 CH_ERR(sc, "failed to free eq (type %d): %d\n", eq->type, rc); 4478 return (rc); 4479 } 4480 eq->flags &= ~EQ_HW_ALLOCATED; 4481 4482 return (0); 4483 } 4484 4485 static int 4486 alloc_wrq(struct adapter *sc, struct vi_info *vi, struct sge_wrq *wrq, 4487 struct sysctl_ctx_list *ctx, struct sysctl_oid *oid) 4488 { 4489 struct sge_eq *eq = &wrq->eq; 4490 int rc; 4491 4492 MPASS(!(eq->flags & EQ_SW_ALLOCATED)); 4493 4494 rc = alloc_eq(sc, eq, ctx, oid); 4495 if (rc) 4496 return (rc); 4497 MPASS(eq->flags & EQ_SW_ALLOCATED); 4498 /* Can't fail after this. */ 4499 4500 wrq->adapter = sc; 4501 TASK_INIT(&wrq->wrq_tx_task, 0, wrq_tx_drain, wrq); 4502 TAILQ_INIT(&wrq->incomplete_wrs); 4503 STAILQ_INIT(&wrq->wr_list); 4504 wrq->nwr_pending = 0; 4505 wrq->ndesc_needed = 0; 4506 add_wrq_sysctls(ctx, oid, wrq); 4507 4508 return (0); 4509 } 4510 4511 static void 4512 free_wrq(struct adapter *sc, struct sge_wrq *wrq) 4513 { 4514 free_eq(sc, &wrq->eq); 4515 MPASS(wrq->nwr_pending == 0); 4516 MPASS(TAILQ_EMPTY(&wrq->incomplete_wrs)); 4517 MPASS(STAILQ_EMPTY(&wrq->wr_list)); 4518 bzero(wrq, sizeof(*wrq)); 4519 } 4520 4521 static void 4522 add_wrq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid, 4523 struct sge_wrq *wrq) 4524 { 4525 struct sysctl_oid_list *children; 4526 4527 if (ctx == NULL || oid == NULL) 4528 return; 4529 4530 children = SYSCTL_CHILDREN(oid); 4531 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_direct", CTLFLAG_RD, 4532 &wrq->tx_wrs_direct, "# of work requests (direct)"); 4533 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_copied", CTLFLAG_RD, 4534 &wrq->tx_wrs_copied, "# of work requests (copied)"); 4535 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_sspace", CTLFLAG_RD, 4536 &wrq->tx_wrs_ss, "# of work requests (copied from scratch space)"); 4537 } 4538 4539 /* 4540 * Idempotent. 4541 */ 4542 static int 4543 alloc_txq(struct vi_info *vi, struct sge_txq *txq, int idx) 4544 { 4545 int rc, iqidx; 4546 struct port_info *pi = vi->pi; 4547 struct adapter *sc = vi->adapter; 4548 struct sge_eq *eq = &txq->eq; 4549 struct txpkts *txp; 4550 char name[16]; 4551 struct sysctl_oid *oid; 4552 4553 if (!(eq->flags & EQ_SW_ALLOCATED)) { 4554 MPASS(!(eq->flags & EQ_HW_ALLOCATED)); 4555 4556 snprintf(name, sizeof(name), "%d", idx); 4557 oid = SYSCTL_ADD_NODE(&vi->ctx, SYSCTL_CHILDREN(vi->txq_oid), 4558 OID_AUTO, name, CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 4559 "tx queue"); 4560 4561 iqidx = vi->first_rxq + (idx % vi->nrxq); 4562 snprintf(name, sizeof(name), "%s txq%d", 4563 device_get_nameunit(vi->dev), idx); 4564 init_eq(sc, &txq->eq, EQ_ETH, vi->qsize_txq, pi->tx_chan, 4565 &sc->sge.rxq[iqidx].iq, name); 4566 4567 rc = mp_ring_alloc(&txq->r, eq->sidx, txq, eth_tx, 4568 can_resume_eth_tx, M_CXGBE, &eq->eq_lock, M_WAITOK); 4569 if (rc != 0) { 4570 CH_ERR(vi, "failed to allocate mp_ring for txq%d: %d\n", 4571 idx, rc); 4572 failed: 4573 sysctl_remove_oid(oid, 1, 1); 4574 return (rc); 4575 } 4576 4577 rc = alloc_eq(sc, eq, &vi->ctx, oid); 4578 if (rc) { 4579 CH_ERR(vi, "failed to allocate txq%d: %d\n", idx, rc); 4580 mp_ring_free(txq->r); 4581 goto failed; 4582 } 4583 MPASS(eq->flags & EQ_SW_ALLOCATED); 4584 /* Can't fail after this point. */ 4585 4586 TASK_INIT(&txq->tx_reclaim_task, 0, tx_reclaim, eq); 4587 txq->ifp = vi->ifp; 4588 txq->gl = sglist_alloc(TX_SGL_SEGS, M_WAITOK); 4589 txq->sdesc = malloc(eq->sidx * sizeof(struct tx_sdesc), M_CXGBE, 4590 M_ZERO | M_WAITOK); 4591 4592 add_txq_sysctls(vi, &vi->ctx, oid, txq); 4593 } 4594 4595 if (!(eq->flags & EQ_HW_ALLOCATED)) { 4596 MPASS(eq->flags & EQ_SW_ALLOCATED); 4597 rc = alloc_eq_hwq(sc, vi, eq); 4598 if (rc != 0) { 4599 CH_ERR(vi, "failed to create hw txq%d: %d\n", idx, rc); 4600 return (rc); 4601 } 4602 MPASS(eq->flags & EQ_HW_ALLOCATED); 4603 /* Can't fail after this point. */ 4604 4605 if (idx == 0) 4606 sc->sge.eq_base = eq->abs_id - eq->cntxt_id; 4607 else 4608 KASSERT(eq->cntxt_id + sc->sge.eq_base == eq->abs_id, 4609 ("eq_base mismatch")); 4610 KASSERT(sc->sge.eq_base == 0 || sc->flags & IS_VF, 4611 ("PF with non-zero eq_base")); 4612 4613 txp = &txq->txp; 4614 MPASS(nitems(txp->mb) >= sc->params.max_pkts_per_eth_tx_pkts_wr); 4615 txq->txp.max_npkt = min(nitems(txp->mb), 4616 sc->params.max_pkts_per_eth_tx_pkts_wr); 4617 if (vi->flags & TX_USES_VM_WR && !(sc->flags & IS_VF)) 4618 txq->txp.max_npkt--; 4619 4620 if (vi->flags & TX_USES_VM_WR) 4621 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) | 4622 V_TXPKT_INTF(pi->tx_chan)); 4623 else 4624 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) | 4625 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(sc->pf) | 4626 V_TXPKT_VF(vi->vin) | V_TXPKT_VF_VLD(vi->vfvld)); 4627 4628 txq->tc_idx = -1; 4629 } 4630 4631 return (0); 4632 } 4633 4634 /* 4635 * Idempotent. 4636 */ 4637 static void 4638 free_txq(struct vi_info *vi, struct sge_txq *txq) 4639 { 4640 struct adapter *sc = vi->adapter; 4641 struct sge_eq *eq = &txq->eq; 4642 4643 if (eq->flags & EQ_HW_ALLOCATED) { 4644 MPASS(eq->flags & EQ_SW_ALLOCATED); 4645 free_eq_hwq(sc, NULL, eq); 4646 MPASS(!(eq->flags & EQ_HW_ALLOCATED)); 4647 } 4648 4649 if (eq->flags & EQ_SW_ALLOCATED) { 4650 MPASS(!(eq->flags & EQ_HW_ALLOCATED)); 4651 sglist_free(txq->gl); 4652 free(txq->sdesc, M_CXGBE); 4653 mp_ring_free(txq->r); 4654 free_eq(sc, eq); 4655 MPASS(!(eq->flags & EQ_SW_ALLOCATED)); 4656 bzero(txq, sizeof(*txq)); 4657 } 4658 } 4659 4660 static void 4661 add_txq_sysctls(struct vi_info *vi, struct sysctl_ctx_list *ctx, 4662 struct sysctl_oid *oid, struct sge_txq *txq) 4663 { 4664 struct adapter *sc; 4665 struct sysctl_oid_list *children; 4666 4667 if (ctx == NULL || oid == NULL) 4668 return; 4669 4670 sc = vi->adapter; 4671 children = SYSCTL_CHILDREN(oid); 4672 4673 mp_ring_sysctls(txq->r, ctx, children); 4674 4675 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tc", 4676 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, txq - sc->sge.txq, 4677 sysctl_tc, "I", "traffic class (-1 means none)"); 4678 4679 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txcsum", CTLFLAG_RD, 4680 &txq->txcsum, "# of times hardware assisted with checksum"); 4681 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "vlan_insertion", CTLFLAG_RD, 4682 &txq->vlan_insertion, "# of times hardware inserted 802.1Q tag"); 4683 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tso_wrs", CTLFLAG_RD, 4684 &txq->tso_wrs, "# of TSO work requests"); 4685 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "imm_wrs", CTLFLAG_RD, 4686 &txq->imm_wrs, "# of work requests with immediate data"); 4687 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "sgl_wrs", CTLFLAG_RD, 4688 &txq->sgl_wrs, "# of work requests with direct SGL"); 4689 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkt_wrs", CTLFLAG_RD, 4690 &txq->txpkt_wrs, "# of txpkt work requests (one pkt/WR)"); 4691 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkts0_wrs", CTLFLAG_RD, 4692 &txq->txpkts0_wrs, "# of txpkts (type 0) work requests"); 4693 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkts1_wrs", CTLFLAG_RD, 4694 &txq->txpkts1_wrs, "# of txpkts (type 1) work requests"); 4695 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkts0_pkts", CTLFLAG_RD, 4696 &txq->txpkts0_pkts, 4697 "# of frames tx'd using type0 txpkts work requests"); 4698 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkts1_pkts", CTLFLAG_RD, 4699 &txq->txpkts1_pkts, 4700 "# of frames tx'd using type1 txpkts work requests"); 4701 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkts_flush", CTLFLAG_RD, 4702 &txq->txpkts_flush, 4703 "# of times txpkts had to be flushed out by an egress-update"); 4704 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "raw_wrs", CTLFLAG_RD, 4705 &txq->raw_wrs, "# of raw work requests (non-packets)"); 4706 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "vxlan_tso_wrs", CTLFLAG_RD, 4707 &txq->vxlan_tso_wrs, "# of VXLAN TSO work requests"); 4708 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "vxlan_txcsum", CTLFLAG_RD, 4709 &txq->vxlan_txcsum, 4710 "# of times hardware assisted with inner checksums (VXLAN)"); 4711 4712 #ifdef KERN_TLS 4713 if (is_ktls(sc)) { 4714 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_records", 4715 CTLFLAG_RD, &txq->kern_tls_records, 4716 "# of NIC TLS records transmitted"); 4717 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_short", 4718 CTLFLAG_RD, &txq->kern_tls_short, 4719 "# of short NIC TLS records transmitted"); 4720 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_partial", 4721 CTLFLAG_RD, &txq->kern_tls_partial, 4722 "# of partial NIC TLS records transmitted"); 4723 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_full", 4724 CTLFLAG_RD, &txq->kern_tls_full, 4725 "# of full NIC TLS records transmitted"); 4726 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_octets", 4727 CTLFLAG_RD, &txq->kern_tls_octets, 4728 "# of payload octets in transmitted NIC TLS records"); 4729 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_waste", 4730 CTLFLAG_RD, &txq->kern_tls_waste, 4731 "# of octets DMAd but not transmitted in NIC TLS records"); 4732 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_options", 4733 CTLFLAG_RD, &txq->kern_tls_options, 4734 "# of NIC TLS options-only packets transmitted"); 4735 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_header", 4736 CTLFLAG_RD, &txq->kern_tls_header, 4737 "# of NIC TLS header-only packets transmitted"); 4738 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_fin", 4739 CTLFLAG_RD, &txq->kern_tls_fin, 4740 "# of NIC TLS FIN-only packets transmitted"); 4741 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_fin_short", 4742 CTLFLAG_RD, &txq->kern_tls_fin_short, 4743 "# of NIC TLS padded FIN packets on short TLS records"); 4744 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_cbc", 4745 CTLFLAG_RD, &txq->kern_tls_cbc, 4746 "# of NIC TLS sessions using AES-CBC"); 4747 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_gcm", 4748 CTLFLAG_RD, &txq->kern_tls_gcm, 4749 "# of NIC TLS sessions using AES-GCM"); 4750 } 4751 #endif 4752 } 4753 4754 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 4755 /* 4756 * Idempotent. 4757 */ 4758 static int 4759 alloc_ofld_txq(struct vi_info *vi, struct sge_ofld_txq *ofld_txq, int idx) 4760 { 4761 struct sysctl_oid *oid; 4762 struct port_info *pi = vi->pi; 4763 struct adapter *sc = vi->adapter; 4764 struct sge_eq *eq = &ofld_txq->wrq.eq; 4765 int rc, iqidx; 4766 char name[16]; 4767 4768 MPASS(idx >= 0); 4769 MPASS(idx < vi->nofldtxq); 4770 4771 if (!(eq->flags & EQ_SW_ALLOCATED)) { 4772 snprintf(name, sizeof(name), "%d", idx); 4773 oid = SYSCTL_ADD_NODE(&vi->ctx, 4774 SYSCTL_CHILDREN(vi->ofld_txq_oid), OID_AUTO, name, 4775 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "offload tx queue"); 4776 4777 snprintf(name, sizeof(name), "%s ofld_txq%d", 4778 device_get_nameunit(vi->dev), idx); 4779 if (vi->nofldrxq > 0) { 4780 iqidx = vi->first_ofld_rxq + (idx % vi->nofldrxq); 4781 init_eq(sc, eq, EQ_OFLD, vi->qsize_txq, pi->tx_chan, 4782 &sc->sge.ofld_rxq[iqidx].iq, name); 4783 } else { 4784 iqidx = vi->first_rxq + (idx % vi->nrxq); 4785 init_eq(sc, eq, EQ_OFLD, vi->qsize_txq, pi->tx_chan, 4786 &sc->sge.rxq[iqidx].iq, name); 4787 } 4788 4789 rc = alloc_wrq(sc, vi, &ofld_txq->wrq, &vi->ctx, oid); 4790 if (rc != 0) { 4791 CH_ERR(vi, "failed to allocate ofld_txq%d: %d\n", idx, 4792 rc); 4793 sysctl_remove_oid(oid, 1, 1); 4794 return (rc); 4795 } 4796 MPASS(eq->flags & EQ_SW_ALLOCATED); 4797 /* Can't fail after this point. */ 4798 4799 ofld_txq->tx_iscsi_pdus = counter_u64_alloc(M_WAITOK); 4800 ofld_txq->tx_iscsi_octets = counter_u64_alloc(M_WAITOK); 4801 ofld_txq->tx_iscsi_iso_wrs = counter_u64_alloc(M_WAITOK); 4802 ofld_txq->tx_toe_tls_records = counter_u64_alloc(M_WAITOK); 4803 ofld_txq->tx_toe_tls_octets = counter_u64_alloc(M_WAITOK); 4804 add_ofld_txq_sysctls(&vi->ctx, oid, ofld_txq); 4805 } 4806 4807 if (!(eq->flags & EQ_HW_ALLOCATED)) { 4808 rc = alloc_eq_hwq(sc, vi, eq); 4809 if (rc != 0) { 4810 CH_ERR(vi, "failed to create hw ofld_txq%d: %d\n", idx, 4811 rc); 4812 return (rc); 4813 } 4814 MPASS(eq->flags & EQ_HW_ALLOCATED); 4815 } 4816 4817 return (0); 4818 } 4819 4820 /* 4821 * Idempotent. 4822 */ 4823 static void 4824 free_ofld_txq(struct vi_info *vi, struct sge_ofld_txq *ofld_txq) 4825 { 4826 struct adapter *sc = vi->adapter; 4827 struct sge_eq *eq = &ofld_txq->wrq.eq; 4828 4829 if (eq->flags & EQ_HW_ALLOCATED) { 4830 MPASS(eq->flags & EQ_SW_ALLOCATED); 4831 free_eq_hwq(sc, NULL, eq); 4832 MPASS(!(eq->flags & EQ_HW_ALLOCATED)); 4833 } 4834 4835 if (eq->flags & EQ_SW_ALLOCATED) { 4836 MPASS(!(eq->flags & EQ_HW_ALLOCATED)); 4837 counter_u64_free(ofld_txq->tx_iscsi_pdus); 4838 counter_u64_free(ofld_txq->tx_iscsi_octets); 4839 counter_u64_free(ofld_txq->tx_iscsi_iso_wrs); 4840 counter_u64_free(ofld_txq->tx_toe_tls_records); 4841 counter_u64_free(ofld_txq->tx_toe_tls_octets); 4842 free_wrq(sc, &ofld_txq->wrq); 4843 MPASS(!(eq->flags & EQ_SW_ALLOCATED)); 4844 bzero(ofld_txq, sizeof(*ofld_txq)); 4845 } 4846 } 4847 4848 static void 4849 add_ofld_txq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid, 4850 struct sge_ofld_txq *ofld_txq) 4851 { 4852 struct sysctl_oid_list *children; 4853 4854 if (ctx == NULL || oid == NULL) 4855 return; 4856 4857 children = SYSCTL_CHILDREN(oid); 4858 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_iscsi_pdus", 4859 CTLFLAG_RD, &ofld_txq->tx_iscsi_pdus, 4860 "# of iSCSI PDUs transmitted"); 4861 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_iscsi_octets", 4862 CTLFLAG_RD, &ofld_txq->tx_iscsi_octets, 4863 "# of payload octets in transmitted iSCSI PDUs"); 4864 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_iscsi_iso_wrs", 4865 CTLFLAG_RD, &ofld_txq->tx_iscsi_iso_wrs, 4866 "# of iSCSI segmentation offload work requests"); 4867 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_toe_tls_records", 4868 CTLFLAG_RD, &ofld_txq->tx_toe_tls_records, 4869 "# of TOE TLS records transmitted"); 4870 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_toe_tls_octets", 4871 CTLFLAG_RD, &ofld_txq->tx_toe_tls_octets, 4872 "# of payload octets in transmitted TOE TLS records"); 4873 } 4874 #endif 4875 4876 static void 4877 oneseg_dma_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error) 4878 { 4879 bus_addr_t *ba = arg; 4880 4881 KASSERT(nseg == 1, 4882 ("%s meant for single segment mappings only.", __func__)); 4883 4884 *ba = error ? 0 : segs->ds_addr; 4885 } 4886 4887 static inline void 4888 ring_fl_db(struct adapter *sc, struct sge_fl *fl) 4889 { 4890 uint32_t n, v; 4891 4892 n = IDXDIFF(fl->pidx >> 3, fl->dbidx, fl->sidx); 4893 MPASS(n > 0); 4894 4895 wmb(); 4896 v = fl->dbval | V_PIDX(n); 4897 if (fl->udb) 4898 *fl->udb = htole32(v); 4899 else 4900 t4_write_reg(sc, sc->sge_kdoorbell_reg, v); 4901 IDXINCR(fl->dbidx, n, fl->sidx); 4902 } 4903 4904 /* 4905 * Fills up the freelist by allocating up to 'n' buffers. Buffers that are 4906 * recycled do not count towards this allocation budget. 4907 * 4908 * Returns non-zero to indicate that this freelist should be added to the list 4909 * of starving freelists. 4910 */ 4911 static int 4912 refill_fl(struct adapter *sc, struct sge_fl *fl, int n) 4913 { 4914 __be64 *d; 4915 struct fl_sdesc *sd; 4916 uintptr_t pa; 4917 caddr_t cl; 4918 struct rx_buf_info *rxb; 4919 struct cluster_metadata *clm; 4920 uint16_t max_pidx, zidx = fl->zidx; 4921 uint16_t hw_cidx = fl->hw_cidx; /* stable snapshot */ 4922 4923 FL_LOCK_ASSERT_OWNED(fl); 4924 4925 /* 4926 * We always stop at the beginning of the hardware descriptor that's just 4927 * before the one with the hw cidx. This is to avoid hw pidx = hw cidx, 4928 * which would mean an empty freelist to the chip. 4929 */ 4930 max_pidx = __predict_false(hw_cidx == 0) ? fl->sidx - 1 : hw_cidx - 1; 4931 if (fl->pidx == max_pidx * 8) 4932 return (0); 4933 4934 d = &fl->desc[fl->pidx]; 4935 sd = &fl->sdesc[fl->pidx]; 4936 rxb = &sc->sge.rx_buf_info[zidx]; 4937 4938 while (n > 0) { 4939 4940 if (sd->cl != NULL) { 4941 4942 if (sd->nmbuf == 0) { 4943 /* 4944 * Fast recycle without involving any atomics on 4945 * the cluster's metadata (if the cluster has 4946 * metadata). This happens when all frames 4947 * received in the cluster were small enough to 4948 * fit within a single mbuf each. 4949 */ 4950 fl->cl_fast_recycled++; 4951 goto recycled; 4952 } 4953 4954 /* 4955 * Cluster is guaranteed to have metadata. Clusters 4956 * without metadata always take the fast recycle path 4957 * when they're recycled. 4958 */ 4959 clm = cl_metadata(sd); 4960 MPASS(clm != NULL); 4961 4962 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) { 4963 fl->cl_recycled++; 4964 counter_u64_add(extfree_rels, 1); 4965 goto recycled; 4966 } 4967 sd->cl = NULL; /* gave up my reference */ 4968 } 4969 MPASS(sd->cl == NULL); 4970 cl = uma_zalloc(rxb->zone, M_NOWAIT); 4971 if (__predict_false(cl == NULL)) { 4972 if (zidx != fl->safe_zidx) { 4973 zidx = fl->safe_zidx; 4974 rxb = &sc->sge.rx_buf_info[zidx]; 4975 cl = uma_zalloc(rxb->zone, M_NOWAIT); 4976 } 4977 if (cl == NULL) 4978 break; 4979 } 4980 fl->cl_allocated++; 4981 n--; 4982 4983 pa = pmap_kextract((vm_offset_t)cl); 4984 sd->cl = cl; 4985 sd->zidx = zidx; 4986 4987 if (fl->flags & FL_BUF_PACKING) { 4988 *d = htobe64(pa | rxb->hwidx2); 4989 sd->moff = rxb->size2; 4990 } else { 4991 *d = htobe64(pa | rxb->hwidx1); 4992 sd->moff = 0; 4993 } 4994 recycled: 4995 sd->nmbuf = 0; 4996 d++; 4997 sd++; 4998 if (__predict_false((++fl->pidx & 7) == 0)) { 4999 uint16_t pidx = fl->pidx >> 3; 5000 5001 if (__predict_false(pidx == fl->sidx)) { 5002 fl->pidx = 0; 5003 pidx = 0; 5004 sd = fl->sdesc; 5005 d = fl->desc; 5006 } 5007 if (n < 8 || pidx == max_pidx) 5008 break; 5009 5010 if (IDXDIFF(pidx, fl->dbidx, fl->sidx) >= 4) 5011 ring_fl_db(sc, fl); 5012 } 5013 } 5014 5015 if ((fl->pidx >> 3) != fl->dbidx) 5016 ring_fl_db(sc, fl); 5017 5018 return (FL_RUNNING_LOW(fl) && !(fl->flags & FL_STARVING)); 5019 } 5020 5021 /* 5022 * Attempt to refill all starving freelists. 5023 */ 5024 static void 5025 refill_sfl(void *arg) 5026 { 5027 struct adapter *sc = arg; 5028 struct sge_fl *fl, *fl_temp; 5029 5030 mtx_assert(&sc->sfl_lock, MA_OWNED); 5031 TAILQ_FOREACH_SAFE(fl, &sc->sfl, link, fl_temp) { 5032 FL_LOCK(fl); 5033 refill_fl(sc, fl, 64); 5034 if (FL_NOT_RUNNING_LOW(fl) || fl->flags & FL_DOOMED) { 5035 TAILQ_REMOVE(&sc->sfl, fl, link); 5036 fl->flags &= ~FL_STARVING; 5037 } 5038 FL_UNLOCK(fl); 5039 } 5040 5041 if (!TAILQ_EMPTY(&sc->sfl)) 5042 callout_schedule(&sc->sfl_callout, hz / 5); 5043 } 5044 5045 /* 5046 * Release the driver's reference on all buffers in the given freelist. Buffers 5047 * with kernel references cannot be freed and will prevent the driver from being 5048 * unloaded safely. 5049 */ 5050 void 5051 free_fl_buffers(struct adapter *sc, struct sge_fl *fl) 5052 { 5053 struct fl_sdesc *sd; 5054 struct cluster_metadata *clm; 5055 int i; 5056 5057 sd = fl->sdesc; 5058 for (i = 0; i < fl->sidx * 8; i++, sd++) { 5059 if (sd->cl == NULL) 5060 continue; 5061 5062 if (sd->nmbuf == 0) 5063 uma_zfree(sc->sge.rx_buf_info[sd->zidx].zone, sd->cl); 5064 else if (fl->flags & FL_BUF_PACKING) { 5065 clm = cl_metadata(sd); 5066 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) { 5067 uma_zfree(sc->sge.rx_buf_info[sd->zidx].zone, 5068 sd->cl); 5069 counter_u64_add(extfree_rels, 1); 5070 } 5071 } 5072 sd->cl = NULL; 5073 } 5074 5075 if (fl->flags & FL_BUF_RESUME) { 5076 m_freem(fl->m0); 5077 fl->flags &= ~FL_BUF_RESUME; 5078 } 5079 } 5080 5081 static inline void 5082 get_pkt_gl(struct mbuf *m, struct sglist *gl) 5083 { 5084 int rc; 5085 5086 M_ASSERTPKTHDR(m); 5087 5088 sglist_reset(gl); 5089 rc = sglist_append_mbuf(gl, m); 5090 if (__predict_false(rc != 0)) { 5091 panic("%s: mbuf %p (%d segs) was vetted earlier but now fails " 5092 "with %d.", __func__, m, mbuf_nsegs(m), rc); 5093 } 5094 5095 KASSERT(gl->sg_nseg == mbuf_nsegs(m), 5096 ("%s: nsegs changed for mbuf %p from %d to %d", __func__, m, 5097 mbuf_nsegs(m), gl->sg_nseg)); 5098 #if 0 /* vm_wr not readily available here. */ 5099 KASSERT(gl->sg_nseg > 0 && gl->sg_nseg <= max_nsegs_allowed(m, vm_wr), 5100 ("%s: %d segments, should have been 1 <= nsegs <= %d", __func__, 5101 gl->sg_nseg, max_nsegs_allowed(m, vm_wr))); 5102 #endif 5103 } 5104 5105 /* 5106 * len16 for a txpkt WR with a GL. Includes the firmware work request header. 5107 */ 5108 static inline u_int 5109 txpkt_len16(u_int nsegs, const u_int extra) 5110 { 5111 u_int n; 5112 5113 MPASS(nsegs > 0); 5114 5115 nsegs--; /* first segment is part of ulptx_sgl */ 5116 n = extra + sizeof(struct fw_eth_tx_pkt_wr) + 5117 sizeof(struct cpl_tx_pkt_core) + 5118 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 5119 5120 return (howmany(n, 16)); 5121 } 5122 5123 /* 5124 * len16 for a txpkt_vm WR with a GL. Includes the firmware work 5125 * request header. 5126 */ 5127 static inline u_int 5128 txpkt_vm_len16(u_int nsegs, const u_int extra) 5129 { 5130 u_int n; 5131 5132 MPASS(nsegs > 0); 5133 5134 nsegs--; /* first segment is part of ulptx_sgl */ 5135 n = extra + sizeof(struct fw_eth_tx_pkt_vm_wr) + 5136 sizeof(struct cpl_tx_pkt_core) + 5137 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 5138 5139 return (howmany(n, 16)); 5140 } 5141 5142 static inline void 5143 calculate_mbuf_len16(struct mbuf *m, bool vm_wr) 5144 { 5145 const int lso = sizeof(struct cpl_tx_pkt_lso_core); 5146 const int tnl_lso = sizeof(struct cpl_tx_tnl_lso); 5147 5148 if (vm_wr) { 5149 if (needs_tso(m)) 5150 set_mbuf_len16(m, txpkt_vm_len16(mbuf_nsegs(m), lso)); 5151 else 5152 set_mbuf_len16(m, txpkt_vm_len16(mbuf_nsegs(m), 0)); 5153 return; 5154 } 5155 5156 if (needs_tso(m)) { 5157 if (needs_vxlan_tso(m)) 5158 set_mbuf_len16(m, txpkt_len16(mbuf_nsegs(m), tnl_lso)); 5159 else 5160 set_mbuf_len16(m, txpkt_len16(mbuf_nsegs(m), lso)); 5161 } else 5162 set_mbuf_len16(m, txpkt_len16(mbuf_nsegs(m), 0)); 5163 } 5164 5165 /* 5166 * len16 for a txpkts type 0 WR with a GL. Does not include the firmware work 5167 * request header. 5168 */ 5169 static inline u_int 5170 txpkts0_len16(u_int nsegs) 5171 { 5172 u_int n; 5173 5174 MPASS(nsegs > 0); 5175 5176 nsegs--; /* first segment is part of ulptx_sgl */ 5177 n = sizeof(struct ulp_txpkt) + sizeof(struct ulptx_idata) + 5178 sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl) + 5179 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 5180 5181 return (howmany(n, 16)); 5182 } 5183 5184 /* 5185 * len16 for a txpkts type 1 WR with a GL. Does not include the firmware work 5186 * request header. 5187 */ 5188 static inline u_int 5189 txpkts1_len16(void) 5190 { 5191 u_int n; 5192 5193 n = sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl); 5194 5195 return (howmany(n, 16)); 5196 } 5197 5198 static inline u_int 5199 imm_payload(u_int ndesc) 5200 { 5201 u_int n; 5202 5203 n = ndesc * EQ_ESIZE - sizeof(struct fw_eth_tx_pkt_wr) - 5204 sizeof(struct cpl_tx_pkt_core); 5205 5206 return (n); 5207 } 5208 5209 static inline uint64_t 5210 csum_to_ctrl(struct adapter *sc, struct mbuf *m) 5211 { 5212 uint64_t ctrl; 5213 int csum_type, l2hlen, l3hlen; 5214 int x, y; 5215 static const int csum_types[3][2] = { 5216 {TX_CSUM_TCPIP, TX_CSUM_TCPIP6}, 5217 {TX_CSUM_UDPIP, TX_CSUM_UDPIP6}, 5218 {TX_CSUM_IP, 0} 5219 }; 5220 5221 M_ASSERTPKTHDR(m); 5222 5223 if (!needs_hwcsum(m)) 5224 return (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS); 5225 5226 MPASS(m->m_pkthdr.l2hlen >= ETHER_HDR_LEN); 5227 MPASS(m->m_pkthdr.l3hlen >= sizeof(struct ip)); 5228 5229 if (needs_vxlan_csum(m)) { 5230 MPASS(m->m_pkthdr.l4hlen > 0); 5231 MPASS(m->m_pkthdr.l5hlen > 0); 5232 MPASS(m->m_pkthdr.inner_l2hlen >= ETHER_HDR_LEN); 5233 MPASS(m->m_pkthdr.inner_l3hlen >= sizeof(struct ip)); 5234 5235 l2hlen = m->m_pkthdr.l2hlen + m->m_pkthdr.l3hlen + 5236 m->m_pkthdr.l4hlen + m->m_pkthdr.l5hlen + 5237 m->m_pkthdr.inner_l2hlen - ETHER_HDR_LEN; 5238 l3hlen = m->m_pkthdr.inner_l3hlen; 5239 } else { 5240 l2hlen = m->m_pkthdr.l2hlen - ETHER_HDR_LEN; 5241 l3hlen = m->m_pkthdr.l3hlen; 5242 } 5243 5244 ctrl = 0; 5245 if (!needs_l3_csum(m)) 5246 ctrl |= F_TXPKT_IPCSUM_DIS; 5247 5248 if (m->m_pkthdr.csum_flags & (CSUM_IP_TCP | CSUM_INNER_IP_TCP | 5249 CSUM_IP6_TCP | CSUM_INNER_IP6_TCP)) 5250 x = 0; /* TCP */ 5251 else if (m->m_pkthdr.csum_flags & (CSUM_IP_UDP | CSUM_INNER_IP_UDP | 5252 CSUM_IP6_UDP | CSUM_INNER_IP6_UDP)) 5253 x = 1; /* UDP */ 5254 else 5255 x = 2; 5256 5257 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_IP_TCP | CSUM_IP_UDP | 5258 CSUM_INNER_IP | CSUM_INNER_IP_TCP | CSUM_INNER_IP_UDP)) 5259 y = 0; /* IPv4 */ 5260 else { 5261 MPASS(m->m_pkthdr.csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | 5262 CSUM_INNER_IP6_TCP | CSUM_INNER_IP6_UDP)); 5263 y = 1; /* IPv6 */ 5264 } 5265 /* 5266 * needs_hwcsum returned true earlier so there must be some kind of 5267 * checksum to calculate. 5268 */ 5269 csum_type = csum_types[x][y]; 5270 MPASS(csum_type != 0); 5271 if (csum_type == TX_CSUM_IP) 5272 ctrl |= F_TXPKT_L4CSUM_DIS; 5273 ctrl |= V_TXPKT_CSUM_TYPE(csum_type) | V_TXPKT_IPHDR_LEN(l3hlen); 5274 if (chip_id(sc) <= CHELSIO_T5) 5275 ctrl |= V_TXPKT_ETHHDR_LEN(l2hlen); 5276 else 5277 ctrl |= V_T6_TXPKT_ETHHDR_LEN(l2hlen); 5278 5279 return (ctrl); 5280 } 5281 5282 static inline void * 5283 write_lso_cpl(void *cpl, struct mbuf *m0) 5284 { 5285 struct cpl_tx_pkt_lso_core *lso; 5286 uint32_t ctrl; 5287 5288 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 5289 m0->m_pkthdr.l4hlen > 0, 5290 ("%s: mbuf %p needs TSO but missing header lengths", 5291 __func__, m0)); 5292 5293 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | 5294 F_LSO_FIRST_SLICE | F_LSO_LAST_SLICE | 5295 V_LSO_ETHHDR_LEN((m0->m_pkthdr.l2hlen - ETHER_HDR_LEN) >> 2) | 5296 V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) | 5297 V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2); 5298 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 5299 ctrl |= F_LSO_IPV6; 5300 5301 lso = cpl; 5302 lso->lso_ctrl = htobe32(ctrl); 5303 lso->ipid_ofst = htobe16(0); 5304 lso->mss = htobe16(m0->m_pkthdr.tso_segsz); 5305 lso->seqno_offset = htobe32(0); 5306 lso->len = htobe32(m0->m_pkthdr.len); 5307 5308 return (lso + 1); 5309 } 5310 5311 static void * 5312 write_tnl_lso_cpl(void *cpl, struct mbuf *m0) 5313 { 5314 struct cpl_tx_tnl_lso *tnl_lso = cpl; 5315 uint32_t ctrl; 5316 5317 KASSERT(m0->m_pkthdr.inner_l2hlen > 0 && 5318 m0->m_pkthdr.inner_l3hlen > 0 && m0->m_pkthdr.inner_l4hlen > 0 && 5319 m0->m_pkthdr.inner_l5hlen > 0, 5320 ("%s: mbuf %p needs VXLAN_TSO but missing inner header lengths", 5321 __func__, m0)); 5322 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 5323 m0->m_pkthdr.l4hlen > 0 && m0->m_pkthdr.l5hlen > 0, 5324 ("%s: mbuf %p needs VXLAN_TSO but missing outer header lengths", 5325 __func__, m0)); 5326 5327 /* Outer headers. */ 5328 ctrl = V_CPL_TX_TNL_LSO_OPCODE(CPL_TX_TNL_LSO) | 5329 F_CPL_TX_TNL_LSO_FIRST | F_CPL_TX_TNL_LSO_LAST | 5330 V_CPL_TX_TNL_LSO_ETHHDRLENOUT( 5331 (m0->m_pkthdr.l2hlen - ETHER_HDR_LEN) >> 2) | 5332 V_CPL_TX_TNL_LSO_IPHDRLENOUT(m0->m_pkthdr.l3hlen >> 2) | 5333 F_CPL_TX_TNL_LSO_IPLENSETOUT; 5334 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 5335 ctrl |= F_CPL_TX_TNL_LSO_IPV6OUT; 5336 else { 5337 ctrl |= F_CPL_TX_TNL_LSO_IPHDRCHKOUT | 5338 F_CPL_TX_TNL_LSO_IPIDINCOUT; 5339 } 5340 tnl_lso->op_to_IpIdSplitOut = htobe32(ctrl); 5341 tnl_lso->IpIdOffsetOut = 0; 5342 tnl_lso->UdpLenSetOut_to_TnlHdrLen = 5343 htobe16(F_CPL_TX_TNL_LSO_UDPCHKCLROUT | 5344 F_CPL_TX_TNL_LSO_UDPLENSETOUT | 5345 V_CPL_TX_TNL_LSO_TNLHDRLEN(m0->m_pkthdr.l2hlen + 5346 m0->m_pkthdr.l3hlen + m0->m_pkthdr.l4hlen + 5347 m0->m_pkthdr.l5hlen) | 5348 V_CPL_TX_TNL_LSO_TNLTYPE(TX_TNL_TYPE_VXLAN)); 5349 tnl_lso->r1 = 0; 5350 5351 /* Inner headers. */ 5352 ctrl = V_CPL_TX_TNL_LSO_ETHHDRLEN( 5353 (m0->m_pkthdr.inner_l2hlen - ETHER_HDR_LEN) >> 2) | 5354 V_CPL_TX_TNL_LSO_IPHDRLEN(m0->m_pkthdr.inner_l3hlen >> 2) | 5355 V_CPL_TX_TNL_LSO_TCPHDRLEN(m0->m_pkthdr.inner_l4hlen >> 2); 5356 if (m0->m_pkthdr.inner_l3hlen == sizeof(struct ip6_hdr)) 5357 ctrl |= F_CPL_TX_TNL_LSO_IPV6; 5358 tnl_lso->Flow_to_TcpHdrLen = htobe32(ctrl); 5359 tnl_lso->IpIdOffset = 0; 5360 tnl_lso->IpIdSplit_to_Mss = 5361 htobe16(V_CPL_TX_TNL_LSO_MSS(m0->m_pkthdr.tso_segsz)); 5362 tnl_lso->TCPSeqOffset = 0; 5363 tnl_lso->EthLenOffset_Size = 5364 htobe32(V_CPL_TX_TNL_LSO_SIZE(m0->m_pkthdr.len)); 5365 5366 return (tnl_lso + 1); 5367 } 5368 5369 #define VM_TX_L2HDR_LEN 16 /* ethmacdst to vlantci */ 5370 5371 /* 5372 * Write a VM txpkt WR for this packet to the hardware descriptors, update the 5373 * software descriptor, and advance the pidx. It is guaranteed that enough 5374 * descriptors are available. 5375 * 5376 * The return value is the # of hardware descriptors used. 5377 */ 5378 static u_int 5379 write_txpkt_vm_wr(struct adapter *sc, struct sge_txq *txq, struct mbuf *m0) 5380 { 5381 struct sge_eq *eq; 5382 struct fw_eth_tx_pkt_vm_wr *wr; 5383 struct tx_sdesc *txsd; 5384 struct cpl_tx_pkt_core *cpl; 5385 uint32_t ctrl; /* used in many unrelated places */ 5386 uint64_t ctrl1; 5387 int len16, ndesc, pktlen, nsegs; 5388 caddr_t dst; 5389 5390 TXQ_LOCK_ASSERT_OWNED(txq); 5391 M_ASSERTPKTHDR(m0); 5392 5393 len16 = mbuf_len16(m0); 5394 nsegs = mbuf_nsegs(m0); 5395 pktlen = m0->m_pkthdr.len; 5396 ctrl = sizeof(struct cpl_tx_pkt_core); 5397 if (needs_tso(m0)) 5398 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 5399 ndesc = tx_len16_to_desc(len16); 5400 5401 /* Firmware work request header */ 5402 eq = &txq->eq; 5403 wr = (void *)&eq->desc[eq->pidx]; 5404 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_VM_WR) | 5405 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl)); 5406 5407 ctrl = V_FW_WR_LEN16(len16); 5408 wr->equiq_to_len16 = htobe32(ctrl); 5409 wr->r3[0] = 0; 5410 wr->r3[1] = 0; 5411 5412 /* 5413 * Copy over ethmacdst, ethmacsrc, ethtype, and vlantci. 5414 * vlantci is ignored unless the ethtype is 0x8100, so it's 5415 * simpler to always copy it rather than making it 5416 * conditional. Also, it seems that we do not have to set 5417 * vlantci or fake the ethtype when doing VLAN tag insertion. 5418 */ 5419 m_copydata(m0, 0, VM_TX_L2HDR_LEN, wr->ethmacdst); 5420 5421 if (needs_tso(m0)) { 5422 cpl = write_lso_cpl(wr + 1, m0); 5423 txq->tso_wrs++; 5424 } else 5425 cpl = (void *)(wr + 1); 5426 5427 /* Checksum offload */ 5428 ctrl1 = csum_to_ctrl(sc, m0); 5429 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS)) 5430 txq->txcsum++; /* some hardware assistance provided */ 5431 5432 /* VLAN tag insertion */ 5433 if (needs_vlan_insertion(m0)) { 5434 ctrl1 |= F_TXPKT_VLAN_VLD | 5435 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 5436 txq->vlan_insertion++; 5437 } 5438 5439 /* CPL header */ 5440 cpl->ctrl0 = txq->cpl_ctrl0; 5441 cpl->pack = 0; 5442 cpl->len = htobe16(pktlen); 5443 cpl->ctrl1 = htobe64(ctrl1); 5444 5445 /* SGL */ 5446 dst = (void *)(cpl + 1); 5447 5448 /* 5449 * A packet using TSO will use up an entire descriptor for the 5450 * firmware work request header, LSO CPL, and TX_PKT_XT CPL. 5451 * If this descriptor is the last descriptor in the ring, wrap 5452 * around to the front of the ring explicitly for the start of 5453 * the sgl. 5454 */ 5455 if (dst == (void *)&eq->desc[eq->sidx]) { 5456 dst = (void *)&eq->desc[0]; 5457 write_gl_to_txd(txq, m0, &dst, 0); 5458 } else 5459 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx); 5460 txq->sgl_wrs++; 5461 txq->txpkt_wrs++; 5462 5463 txsd = &txq->sdesc[eq->pidx]; 5464 txsd->m = m0; 5465 txsd->desc_used = ndesc; 5466 5467 return (ndesc); 5468 } 5469 5470 /* 5471 * Write a raw WR to the hardware descriptors, update the software 5472 * descriptor, and advance the pidx. It is guaranteed that enough 5473 * descriptors are available. 5474 * 5475 * The return value is the # of hardware descriptors used. 5476 */ 5477 static u_int 5478 write_raw_wr(struct sge_txq *txq, void *wr, struct mbuf *m0, u_int available) 5479 { 5480 struct sge_eq *eq = &txq->eq; 5481 struct tx_sdesc *txsd; 5482 struct mbuf *m; 5483 caddr_t dst; 5484 int len16, ndesc; 5485 5486 len16 = mbuf_len16(m0); 5487 ndesc = tx_len16_to_desc(len16); 5488 MPASS(ndesc <= available); 5489 5490 dst = wr; 5491 for (m = m0; m != NULL; m = m->m_next) 5492 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len); 5493 5494 txq->raw_wrs++; 5495 5496 txsd = &txq->sdesc[eq->pidx]; 5497 txsd->m = m0; 5498 txsd->desc_used = ndesc; 5499 5500 return (ndesc); 5501 } 5502 5503 /* 5504 * Write a txpkt WR for this packet to the hardware descriptors, update the 5505 * software descriptor, and advance the pidx. It is guaranteed that enough 5506 * descriptors are available. 5507 * 5508 * The return value is the # of hardware descriptors used. 5509 */ 5510 static u_int 5511 write_txpkt_wr(struct adapter *sc, struct sge_txq *txq, struct mbuf *m0, 5512 u_int available) 5513 { 5514 struct sge_eq *eq; 5515 struct fw_eth_tx_pkt_wr *wr; 5516 struct tx_sdesc *txsd; 5517 struct cpl_tx_pkt_core *cpl; 5518 uint32_t ctrl; /* used in many unrelated places */ 5519 uint64_t ctrl1; 5520 int len16, ndesc, pktlen, nsegs; 5521 caddr_t dst; 5522 5523 TXQ_LOCK_ASSERT_OWNED(txq); 5524 M_ASSERTPKTHDR(m0); 5525 5526 len16 = mbuf_len16(m0); 5527 nsegs = mbuf_nsegs(m0); 5528 pktlen = m0->m_pkthdr.len; 5529 ctrl = sizeof(struct cpl_tx_pkt_core); 5530 if (needs_tso(m0)) { 5531 if (needs_vxlan_tso(m0)) 5532 ctrl += sizeof(struct cpl_tx_tnl_lso); 5533 else 5534 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 5535 } else if (!(mbuf_cflags(m0) & MC_NOMAP) && pktlen <= imm_payload(2) && 5536 available >= 2) { 5537 /* Immediate data. Recalculate len16 and set nsegs to 0. */ 5538 ctrl += pktlen; 5539 len16 = howmany(sizeof(struct fw_eth_tx_pkt_wr) + 5540 sizeof(struct cpl_tx_pkt_core) + pktlen, 16); 5541 nsegs = 0; 5542 } 5543 ndesc = tx_len16_to_desc(len16); 5544 MPASS(ndesc <= available); 5545 5546 /* Firmware work request header */ 5547 eq = &txq->eq; 5548 wr = (void *)&eq->desc[eq->pidx]; 5549 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_WR) | 5550 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl)); 5551 5552 ctrl = V_FW_WR_LEN16(len16); 5553 wr->equiq_to_len16 = htobe32(ctrl); 5554 wr->r3 = 0; 5555 5556 if (needs_tso(m0)) { 5557 if (needs_vxlan_tso(m0)) { 5558 cpl = write_tnl_lso_cpl(wr + 1, m0); 5559 txq->vxlan_tso_wrs++; 5560 } else { 5561 cpl = write_lso_cpl(wr + 1, m0); 5562 txq->tso_wrs++; 5563 } 5564 } else 5565 cpl = (void *)(wr + 1); 5566 5567 /* Checksum offload */ 5568 ctrl1 = csum_to_ctrl(sc, m0); 5569 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS)) { 5570 /* some hardware assistance provided */ 5571 if (needs_vxlan_csum(m0)) 5572 txq->vxlan_txcsum++; 5573 else 5574 txq->txcsum++; 5575 } 5576 5577 /* VLAN tag insertion */ 5578 if (needs_vlan_insertion(m0)) { 5579 ctrl1 |= F_TXPKT_VLAN_VLD | 5580 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 5581 txq->vlan_insertion++; 5582 } 5583 5584 /* CPL header */ 5585 cpl->ctrl0 = txq->cpl_ctrl0; 5586 cpl->pack = 0; 5587 cpl->len = htobe16(pktlen); 5588 cpl->ctrl1 = htobe64(ctrl1); 5589 5590 /* SGL */ 5591 dst = (void *)(cpl + 1); 5592 if (__predict_false((uintptr_t)dst == (uintptr_t)&eq->desc[eq->sidx])) 5593 dst = (caddr_t)&eq->desc[0]; 5594 if (nsegs > 0) { 5595 5596 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx); 5597 txq->sgl_wrs++; 5598 } else { 5599 struct mbuf *m; 5600 5601 for (m = m0; m != NULL; m = m->m_next) { 5602 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len); 5603 #ifdef INVARIANTS 5604 pktlen -= m->m_len; 5605 #endif 5606 } 5607 #ifdef INVARIANTS 5608 KASSERT(pktlen == 0, ("%s: %d bytes left.", __func__, pktlen)); 5609 #endif 5610 txq->imm_wrs++; 5611 } 5612 5613 txq->txpkt_wrs++; 5614 5615 txsd = &txq->sdesc[eq->pidx]; 5616 txsd->m = m0; 5617 txsd->desc_used = ndesc; 5618 5619 return (ndesc); 5620 } 5621 5622 static inline bool 5623 cmp_l2hdr(struct txpkts *txp, struct mbuf *m) 5624 { 5625 int len; 5626 5627 MPASS(txp->npkt > 0); 5628 MPASS(m->m_len >= VM_TX_L2HDR_LEN); 5629 5630 if (txp->ethtype == be16toh(ETHERTYPE_VLAN)) 5631 len = VM_TX_L2HDR_LEN; 5632 else 5633 len = sizeof(struct ether_header); 5634 5635 return (memcmp(m->m_data, &txp->ethmacdst[0], len) != 0); 5636 } 5637 5638 static inline void 5639 save_l2hdr(struct txpkts *txp, struct mbuf *m) 5640 { 5641 MPASS(m->m_len >= VM_TX_L2HDR_LEN); 5642 5643 memcpy(&txp->ethmacdst[0], mtod(m, const void *), VM_TX_L2HDR_LEN); 5644 } 5645 5646 static int 5647 add_to_txpkts_vf(struct adapter *sc, struct sge_txq *txq, struct mbuf *m, 5648 int avail, bool *send) 5649 { 5650 struct txpkts *txp = &txq->txp; 5651 5652 /* Cannot have TSO and coalesce at the same time. */ 5653 if (cannot_use_txpkts(m)) { 5654 cannot_coalesce: 5655 *send = txp->npkt > 0; 5656 return (EINVAL); 5657 } 5658 5659 /* VF allows coalescing of type 1 (1 GL) only */ 5660 if (mbuf_nsegs(m) > 1) 5661 goto cannot_coalesce; 5662 5663 *send = false; 5664 if (txp->npkt > 0) { 5665 MPASS(tx_len16_to_desc(txp->len16) <= avail); 5666 MPASS(txp->npkt < txp->max_npkt); 5667 MPASS(txp->wr_type == 1); /* VF supports type 1 only */ 5668 5669 if (tx_len16_to_desc(txp->len16 + txpkts1_len16()) > avail) { 5670 retry_after_send: 5671 *send = true; 5672 return (EAGAIN); 5673 } 5674 if (m->m_pkthdr.len + txp->plen > 65535) 5675 goto retry_after_send; 5676 if (cmp_l2hdr(txp, m)) 5677 goto retry_after_send; 5678 5679 txp->len16 += txpkts1_len16(); 5680 txp->plen += m->m_pkthdr.len; 5681 txp->mb[txp->npkt++] = m; 5682 if (txp->npkt == txp->max_npkt) 5683 *send = true; 5684 } else { 5685 txp->len16 = howmany(sizeof(struct fw_eth_tx_pkts_vm_wr), 16) + 5686 txpkts1_len16(); 5687 if (tx_len16_to_desc(txp->len16) > avail) 5688 goto cannot_coalesce; 5689 txp->npkt = 1; 5690 txp->wr_type = 1; 5691 txp->plen = m->m_pkthdr.len; 5692 txp->mb[0] = m; 5693 save_l2hdr(txp, m); 5694 } 5695 return (0); 5696 } 5697 5698 static int 5699 add_to_txpkts_pf(struct adapter *sc, struct sge_txq *txq, struct mbuf *m, 5700 int avail, bool *send) 5701 { 5702 struct txpkts *txp = &txq->txp; 5703 int nsegs; 5704 5705 MPASS(!(sc->flags & IS_VF)); 5706 5707 /* Cannot have TSO and coalesce at the same time. */ 5708 if (cannot_use_txpkts(m)) { 5709 cannot_coalesce: 5710 *send = txp->npkt > 0; 5711 return (EINVAL); 5712 } 5713 5714 *send = false; 5715 nsegs = mbuf_nsegs(m); 5716 if (txp->npkt == 0) { 5717 if (m->m_pkthdr.len > 65535) 5718 goto cannot_coalesce; 5719 if (nsegs > 1) { 5720 txp->wr_type = 0; 5721 txp->len16 = 5722 howmany(sizeof(struct fw_eth_tx_pkts_wr), 16) + 5723 txpkts0_len16(nsegs); 5724 } else { 5725 txp->wr_type = 1; 5726 txp->len16 = 5727 howmany(sizeof(struct fw_eth_tx_pkts_wr), 16) + 5728 txpkts1_len16(); 5729 } 5730 if (tx_len16_to_desc(txp->len16) > avail) 5731 goto cannot_coalesce; 5732 txp->npkt = 1; 5733 txp->plen = m->m_pkthdr.len; 5734 txp->mb[0] = m; 5735 } else { 5736 MPASS(tx_len16_to_desc(txp->len16) <= avail); 5737 MPASS(txp->npkt < txp->max_npkt); 5738 5739 if (m->m_pkthdr.len + txp->plen > 65535) { 5740 retry_after_send: 5741 *send = true; 5742 return (EAGAIN); 5743 } 5744 5745 MPASS(txp->wr_type == 0 || txp->wr_type == 1); 5746 if (txp->wr_type == 0) { 5747 if (tx_len16_to_desc(txp->len16 + 5748 txpkts0_len16(nsegs)) > min(avail, SGE_MAX_WR_NDESC)) 5749 goto retry_after_send; 5750 txp->len16 += txpkts0_len16(nsegs); 5751 } else { 5752 if (nsegs != 1) 5753 goto retry_after_send; 5754 if (tx_len16_to_desc(txp->len16 + txpkts1_len16()) > 5755 avail) 5756 goto retry_after_send; 5757 txp->len16 += txpkts1_len16(); 5758 } 5759 5760 txp->plen += m->m_pkthdr.len; 5761 txp->mb[txp->npkt++] = m; 5762 if (txp->npkt == txp->max_npkt) 5763 *send = true; 5764 } 5765 return (0); 5766 } 5767 5768 /* 5769 * Write a txpkts WR for the packets in txp to the hardware descriptors, update 5770 * the software descriptor, and advance the pidx. It is guaranteed that enough 5771 * descriptors are available. 5772 * 5773 * The return value is the # of hardware descriptors used. 5774 */ 5775 static u_int 5776 write_txpkts_wr(struct adapter *sc, struct sge_txq *txq) 5777 { 5778 const struct txpkts *txp = &txq->txp; 5779 struct sge_eq *eq = &txq->eq; 5780 struct fw_eth_tx_pkts_wr *wr; 5781 struct tx_sdesc *txsd; 5782 struct cpl_tx_pkt_core *cpl; 5783 uint64_t ctrl1; 5784 int ndesc, i, checkwrap; 5785 struct mbuf *m, *last; 5786 void *flitp; 5787 5788 TXQ_LOCK_ASSERT_OWNED(txq); 5789 MPASS(txp->npkt > 0); 5790 MPASS(txp->len16 <= howmany(SGE_MAX_WR_LEN, 16)); 5791 5792 wr = (void *)&eq->desc[eq->pidx]; 5793 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR)); 5794 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(txp->len16)); 5795 wr->plen = htobe16(txp->plen); 5796 wr->npkt = txp->npkt; 5797 wr->r3 = 0; 5798 wr->type = txp->wr_type; 5799 flitp = wr + 1; 5800 5801 /* 5802 * At this point we are 16B into a hardware descriptor. If checkwrap is 5803 * set then we know the WR is going to wrap around somewhere. We'll 5804 * check for that at appropriate points. 5805 */ 5806 ndesc = tx_len16_to_desc(txp->len16); 5807 last = NULL; 5808 checkwrap = eq->sidx - ndesc < eq->pidx; 5809 for (i = 0; i < txp->npkt; i++) { 5810 m = txp->mb[i]; 5811 if (txp->wr_type == 0) { 5812 struct ulp_txpkt *ulpmc; 5813 struct ulptx_idata *ulpsc; 5814 5815 /* ULP master command */ 5816 ulpmc = flitp; 5817 ulpmc->cmd_dest = htobe32(V_ULPTX_CMD(ULP_TX_PKT) | 5818 V_ULP_TXPKT_DEST(0) | V_ULP_TXPKT_FID(eq->iqid)); 5819 ulpmc->len = htobe32(txpkts0_len16(mbuf_nsegs(m))); 5820 5821 /* ULP subcommand */ 5822 ulpsc = (void *)(ulpmc + 1); 5823 ulpsc->cmd_more = htobe32(V_ULPTX_CMD(ULP_TX_SC_IMM) | 5824 F_ULP_TX_SC_MORE); 5825 ulpsc->len = htobe32(sizeof(struct cpl_tx_pkt_core)); 5826 5827 cpl = (void *)(ulpsc + 1); 5828 if (checkwrap && 5829 (uintptr_t)cpl == (uintptr_t)&eq->desc[eq->sidx]) 5830 cpl = (void *)&eq->desc[0]; 5831 } else { 5832 cpl = flitp; 5833 } 5834 5835 /* Checksum offload */ 5836 ctrl1 = csum_to_ctrl(sc, m); 5837 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS)) { 5838 /* some hardware assistance provided */ 5839 if (needs_vxlan_csum(m)) 5840 txq->vxlan_txcsum++; 5841 else 5842 txq->txcsum++; 5843 } 5844 5845 /* VLAN tag insertion */ 5846 if (needs_vlan_insertion(m)) { 5847 ctrl1 |= F_TXPKT_VLAN_VLD | 5848 V_TXPKT_VLAN(m->m_pkthdr.ether_vtag); 5849 txq->vlan_insertion++; 5850 } 5851 5852 /* CPL header */ 5853 cpl->ctrl0 = txq->cpl_ctrl0; 5854 cpl->pack = 0; 5855 cpl->len = htobe16(m->m_pkthdr.len); 5856 cpl->ctrl1 = htobe64(ctrl1); 5857 5858 flitp = cpl + 1; 5859 if (checkwrap && 5860 (uintptr_t)flitp == (uintptr_t)&eq->desc[eq->sidx]) 5861 flitp = (void *)&eq->desc[0]; 5862 5863 write_gl_to_txd(txq, m, (caddr_t *)(&flitp), checkwrap); 5864 5865 if (last != NULL) 5866 last->m_nextpkt = m; 5867 last = m; 5868 } 5869 5870 txq->sgl_wrs++; 5871 if (txp->wr_type == 0) { 5872 txq->txpkts0_pkts += txp->npkt; 5873 txq->txpkts0_wrs++; 5874 } else { 5875 txq->txpkts1_pkts += txp->npkt; 5876 txq->txpkts1_wrs++; 5877 } 5878 5879 txsd = &txq->sdesc[eq->pidx]; 5880 txsd->m = txp->mb[0]; 5881 txsd->desc_used = ndesc; 5882 5883 return (ndesc); 5884 } 5885 5886 static u_int 5887 write_txpkts_vm_wr(struct adapter *sc, struct sge_txq *txq) 5888 { 5889 const struct txpkts *txp = &txq->txp; 5890 struct sge_eq *eq = &txq->eq; 5891 struct fw_eth_tx_pkts_vm_wr *wr; 5892 struct tx_sdesc *txsd; 5893 struct cpl_tx_pkt_core *cpl; 5894 uint64_t ctrl1; 5895 int ndesc, i; 5896 struct mbuf *m, *last; 5897 void *flitp; 5898 5899 TXQ_LOCK_ASSERT_OWNED(txq); 5900 MPASS(txp->npkt > 0); 5901 MPASS(txp->wr_type == 1); /* VF supports type 1 only */ 5902 MPASS(txp->mb[0] != NULL); 5903 MPASS(txp->len16 <= howmany(SGE_MAX_WR_LEN, 16)); 5904 5905 wr = (void *)&eq->desc[eq->pidx]; 5906 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_VM_WR)); 5907 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(txp->len16)); 5908 wr->r3 = 0; 5909 wr->plen = htobe16(txp->plen); 5910 wr->npkt = txp->npkt; 5911 wr->r4 = 0; 5912 memcpy(&wr->ethmacdst[0], &txp->ethmacdst[0], 16); 5913 flitp = wr + 1; 5914 5915 /* 5916 * At this point we are 32B into a hardware descriptor. Each mbuf in 5917 * the WR will take 32B so we check for the end of the descriptor ring 5918 * before writing odd mbufs (mb[1], 3, 5, ..) 5919 */ 5920 ndesc = tx_len16_to_desc(txp->len16); 5921 last = NULL; 5922 for (i = 0; i < txp->npkt; i++) { 5923 m = txp->mb[i]; 5924 if (i & 1 && (uintptr_t)flitp == (uintptr_t)&eq->desc[eq->sidx]) 5925 flitp = &eq->desc[0]; 5926 cpl = flitp; 5927 5928 /* Checksum offload */ 5929 ctrl1 = csum_to_ctrl(sc, m); 5930 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS)) 5931 txq->txcsum++; /* some hardware assistance provided */ 5932 5933 /* VLAN tag insertion */ 5934 if (needs_vlan_insertion(m)) { 5935 ctrl1 |= F_TXPKT_VLAN_VLD | 5936 V_TXPKT_VLAN(m->m_pkthdr.ether_vtag); 5937 txq->vlan_insertion++; 5938 } 5939 5940 /* CPL header */ 5941 cpl->ctrl0 = txq->cpl_ctrl0; 5942 cpl->pack = 0; 5943 cpl->len = htobe16(m->m_pkthdr.len); 5944 cpl->ctrl1 = htobe64(ctrl1); 5945 5946 flitp = cpl + 1; 5947 MPASS(mbuf_nsegs(m) == 1); 5948 write_gl_to_txd(txq, m, (caddr_t *)(&flitp), 0); 5949 5950 if (last != NULL) 5951 last->m_nextpkt = m; 5952 last = m; 5953 } 5954 5955 txq->sgl_wrs++; 5956 txq->txpkts1_pkts += txp->npkt; 5957 txq->txpkts1_wrs++; 5958 5959 txsd = &txq->sdesc[eq->pidx]; 5960 txsd->m = txp->mb[0]; 5961 txsd->desc_used = ndesc; 5962 5963 return (ndesc); 5964 } 5965 5966 /* 5967 * If the SGL ends on an address that is not 16 byte aligned, this function will 5968 * add a 0 filled flit at the end. 5969 */ 5970 static void 5971 write_gl_to_txd(struct sge_txq *txq, struct mbuf *m, caddr_t *to, int checkwrap) 5972 { 5973 struct sge_eq *eq = &txq->eq; 5974 struct sglist *gl = txq->gl; 5975 struct sglist_seg *seg; 5976 __be64 *flitp, *wrap; 5977 struct ulptx_sgl *usgl; 5978 int i, nflits, nsegs; 5979 5980 KASSERT(((uintptr_t)(*to) & 0xf) == 0, 5981 ("%s: SGL must start at a 16 byte boundary: %p", __func__, *to)); 5982 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]); 5983 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]); 5984 5985 get_pkt_gl(m, gl); 5986 nsegs = gl->sg_nseg; 5987 MPASS(nsegs > 0); 5988 5989 nflits = (3 * (nsegs - 1)) / 2 + ((nsegs - 1) & 1) + 2; 5990 flitp = (__be64 *)(*to); 5991 wrap = (__be64 *)(&eq->desc[eq->sidx]); 5992 seg = &gl->sg_segs[0]; 5993 usgl = (void *)flitp; 5994 5995 /* 5996 * We start at a 16 byte boundary somewhere inside the tx descriptor 5997 * ring, so we're at least 16 bytes away from the status page. There is 5998 * no chance of a wrap around in the middle of usgl (which is 16 bytes). 5999 */ 6000 6001 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 6002 V_ULPTX_NSGE(nsegs)); 6003 usgl->len0 = htobe32(seg->ss_len); 6004 usgl->addr0 = htobe64(seg->ss_paddr); 6005 seg++; 6006 6007 if (checkwrap == 0 || (uintptr_t)(flitp + nflits) <= (uintptr_t)wrap) { 6008 6009 /* Won't wrap around at all */ 6010 6011 for (i = 0; i < nsegs - 1; i++, seg++) { 6012 usgl->sge[i / 2].len[i & 1] = htobe32(seg->ss_len); 6013 usgl->sge[i / 2].addr[i & 1] = htobe64(seg->ss_paddr); 6014 } 6015 if (i & 1) 6016 usgl->sge[i / 2].len[1] = htobe32(0); 6017 flitp += nflits; 6018 } else { 6019 6020 /* Will wrap somewhere in the rest of the SGL */ 6021 6022 /* 2 flits already written, write the rest flit by flit */ 6023 flitp = (void *)(usgl + 1); 6024 for (i = 0; i < nflits - 2; i++) { 6025 if (flitp == wrap) 6026 flitp = (void *)eq->desc; 6027 *flitp++ = get_flit(seg, nsegs - 1, i); 6028 } 6029 } 6030 6031 if (nflits & 1) { 6032 MPASS(((uintptr_t)flitp) & 0xf); 6033 *flitp++ = 0; 6034 } 6035 6036 MPASS((((uintptr_t)flitp) & 0xf) == 0); 6037 if (__predict_false(flitp == wrap)) 6038 *to = (void *)eq->desc; 6039 else 6040 *to = (void *)flitp; 6041 } 6042 6043 static inline void 6044 copy_to_txd(struct sge_eq *eq, caddr_t from, caddr_t *to, int len) 6045 { 6046 6047 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]); 6048 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]); 6049 6050 if (__predict_true((uintptr_t)(*to) + len <= 6051 (uintptr_t)&eq->desc[eq->sidx])) { 6052 bcopy(from, *to, len); 6053 (*to) += len; 6054 } else { 6055 int portion = (uintptr_t)&eq->desc[eq->sidx] - (uintptr_t)(*to); 6056 6057 bcopy(from, *to, portion); 6058 from += portion; 6059 portion = len - portion; /* remaining */ 6060 bcopy(from, (void *)eq->desc, portion); 6061 (*to) = (caddr_t)eq->desc + portion; 6062 } 6063 } 6064 6065 static inline void 6066 ring_eq_db(struct adapter *sc, struct sge_eq *eq, u_int n) 6067 { 6068 u_int db; 6069 6070 MPASS(n > 0); 6071 6072 db = eq->doorbells; 6073 if (n > 1) 6074 clrbit(&db, DOORBELL_WCWR); 6075 wmb(); 6076 6077 switch (ffs(db) - 1) { 6078 case DOORBELL_UDB: 6079 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n)); 6080 break; 6081 6082 case DOORBELL_WCWR: { 6083 volatile uint64_t *dst, *src; 6084 int i; 6085 6086 /* 6087 * Queues whose 128B doorbell segment fits in the page do not 6088 * use relative qid (udb_qid is always 0). Only queues with 6089 * doorbell segments can do WCWR. 6090 */ 6091 KASSERT(eq->udb_qid == 0 && n == 1, 6092 ("%s: inappropriate doorbell (0x%x, %d, %d) for eq %p", 6093 __func__, eq->doorbells, n, eq->dbidx, eq)); 6094 6095 dst = (volatile void *)((uintptr_t)eq->udb + UDBS_WR_OFFSET - 6096 UDBS_DB_OFFSET); 6097 i = eq->dbidx; 6098 src = (void *)&eq->desc[i]; 6099 while (src != (void *)&eq->desc[i + 1]) 6100 *dst++ = *src++; 6101 wmb(); 6102 break; 6103 } 6104 6105 case DOORBELL_UDBWC: 6106 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n)); 6107 wmb(); 6108 break; 6109 6110 case DOORBELL_KDB: 6111 t4_write_reg(sc, sc->sge_kdoorbell_reg, 6112 V_QID(eq->cntxt_id) | V_PIDX(n)); 6113 break; 6114 } 6115 6116 IDXINCR(eq->dbidx, n, eq->sidx); 6117 } 6118 6119 static inline u_int 6120 reclaimable_tx_desc(struct sge_eq *eq) 6121 { 6122 uint16_t hw_cidx; 6123 6124 hw_cidx = read_hw_cidx(eq); 6125 return (IDXDIFF(hw_cidx, eq->cidx, eq->sidx)); 6126 } 6127 6128 static inline u_int 6129 total_available_tx_desc(struct sge_eq *eq) 6130 { 6131 uint16_t hw_cidx, pidx; 6132 6133 hw_cidx = read_hw_cidx(eq); 6134 pidx = eq->pidx; 6135 6136 if (pidx == hw_cidx) 6137 return (eq->sidx - 1); 6138 else 6139 return (IDXDIFF(hw_cidx, pidx, eq->sidx) - 1); 6140 } 6141 6142 static inline uint16_t 6143 read_hw_cidx(struct sge_eq *eq) 6144 { 6145 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx]; 6146 uint16_t cidx = spg->cidx; /* stable snapshot */ 6147 6148 return (be16toh(cidx)); 6149 } 6150 6151 /* 6152 * Reclaim 'n' descriptors approximately. 6153 */ 6154 static u_int 6155 reclaim_tx_descs(struct sge_txq *txq, u_int n) 6156 { 6157 struct tx_sdesc *txsd; 6158 struct sge_eq *eq = &txq->eq; 6159 u_int can_reclaim, reclaimed; 6160 6161 TXQ_LOCK_ASSERT_OWNED(txq); 6162 MPASS(n > 0); 6163 6164 reclaimed = 0; 6165 can_reclaim = reclaimable_tx_desc(eq); 6166 while (can_reclaim && reclaimed < n) { 6167 int ndesc; 6168 struct mbuf *m, *nextpkt; 6169 6170 txsd = &txq->sdesc[eq->cidx]; 6171 ndesc = txsd->desc_used; 6172 6173 /* Firmware doesn't return "partial" credits. */ 6174 KASSERT(can_reclaim >= ndesc, 6175 ("%s: unexpected number of credits: %d, %d", 6176 __func__, can_reclaim, ndesc)); 6177 KASSERT(ndesc != 0, 6178 ("%s: descriptor with no credits: cidx %d", 6179 __func__, eq->cidx)); 6180 6181 for (m = txsd->m; m != NULL; m = nextpkt) { 6182 nextpkt = m->m_nextpkt; 6183 m->m_nextpkt = NULL; 6184 m_freem(m); 6185 } 6186 reclaimed += ndesc; 6187 can_reclaim -= ndesc; 6188 IDXINCR(eq->cidx, ndesc, eq->sidx); 6189 } 6190 6191 return (reclaimed); 6192 } 6193 6194 static void 6195 tx_reclaim(void *arg, int n) 6196 { 6197 struct sge_txq *txq = arg; 6198 struct sge_eq *eq = &txq->eq; 6199 6200 do { 6201 if (TXQ_TRYLOCK(txq) == 0) 6202 break; 6203 n = reclaim_tx_descs(txq, 32); 6204 if (eq->cidx == eq->pidx) 6205 eq->equeqidx = eq->pidx; 6206 TXQ_UNLOCK(txq); 6207 } while (n > 0); 6208 } 6209 6210 static __be64 6211 get_flit(struct sglist_seg *segs, int nsegs, int idx) 6212 { 6213 int i = (idx / 3) * 2; 6214 6215 switch (idx % 3) { 6216 case 0: { 6217 uint64_t rc; 6218 6219 rc = (uint64_t)segs[i].ss_len << 32; 6220 if (i + 1 < nsegs) 6221 rc |= (uint64_t)(segs[i + 1].ss_len); 6222 6223 return (htobe64(rc)); 6224 } 6225 case 1: 6226 return (htobe64(segs[i].ss_paddr)); 6227 case 2: 6228 return (htobe64(segs[i + 1].ss_paddr)); 6229 } 6230 6231 return (0); 6232 } 6233 6234 static int 6235 find_refill_source(struct adapter *sc, int maxp, bool packing) 6236 { 6237 int i, zidx = -1; 6238 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[0]; 6239 6240 if (packing) { 6241 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) { 6242 if (rxb->hwidx2 == -1) 6243 continue; 6244 if (rxb->size1 < PAGE_SIZE && 6245 rxb->size1 < largest_rx_cluster) 6246 continue; 6247 if (rxb->size1 > largest_rx_cluster) 6248 break; 6249 MPASS(rxb->size1 - rxb->size2 >= CL_METADATA_SIZE); 6250 if (rxb->size2 >= maxp) 6251 return (i); 6252 zidx = i; 6253 } 6254 } else { 6255 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) { 6256 if (rxb->hwidx1 == -1) 6257 continue; 6258 if (rxb->size1 > largest_rx_cluster) 6259 break; 6260 if (rxb->size1 >= maxp) 6261 return (i); 6262 zidx = i; 6263 } 6264 } 6265 6266 return (zidx); 6267 } 6268 6269 static void 6270 add_fl_to_sfl(struct adapter *sc, struct sge_fl *fl) 6271 { 6272 mtx_lock(&sc->sfl_lock); 6273 FL_LOCK(fl); 6274 if ((fl->flags & FL_DOOMED) == 0) { 6275 fl->flags |= FL_STARVING; 6276 TAILQ_INSERT_TAIL(&sc->sfl, fl, link); 6277 callout_reset(&sc->sfl_callout, hz / 5, refill_sfl, sc); 6278 } 6279 FL_UNLOCK(fl); 6280 mtx_unlock(&sc->sfl_lock); 6281 } 6282 6283 static void 6284 handle_wrq_egr_update(struct adapter *sc, struct sge_eq *eq) 6285 { 6286 struct sge_wrq *wrq = (void *)eq; 6287 6288 atomic_readandclear_int(&eq->equiq); 6289 taskqueue_enqueue(sc->tq[eq->tx_chan], &wrq->wrq_tx_task); 6290 } 6291 6292 static void 6293 handle_eth_egr_update(struct adapter *sc, struct sge_eq *eq) 6294 { 6295 struct sge_txq *txq = (void *)eq; 6296 6297 MPASS(eq->type == EQ_ETH); 6298 6299 atomic_readandclear_int(&eq->equiq); 6300 if (mp_ring_is_idle(txq->r)) 6301 taskqueue_enqueue(sc->tq[eq->tx_chan], &txq->tx_reclaim_task); 6302 else 6303 mp_ring_check_drainage(txq->r, 64); 6304 } 6305 6306 static int 6307 handle_sge_egr_update(struct sge_iq *iq, const struct rss_header *rss, 6308 struct mbuf *m) 6309 { 6310 const struct cpl_sge_egr_update *cpl = (const void *)(rss + 1); 6311 unsigned int qid = G_EGR_QID(ntohl(cpl->opcode_qid)); 6312 struct adapter *sc = iq->adapter; 6313 struct sge *s = &sc->sge; 6314 struct sge_eq *eq; 6315 static void (*h[])(struct adapter *, struct sge_eq *) = {NULL, 6316 &handle_wrq_egr_update, &handle_eth_egr_update, 6317 &handle_wrq_egr_update}; 6318 6319 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 6320 rss->opcode)); 6321 6322 eq = s->eqmap[qid - s->eq_start - s->eq_base]; 6323 (*h[eq->type])(sc, eq); 6324 6325 return (0); 6326 } 6327 6328 /* handle_fw_msg works for both fw4_msg and fw6_msg because this is valid */ 6329 CTASSERT(offsetof(struct cpl_fw4_msg, data) == \ 6330 offsetof(struct cpl_fw6_msg, data)); 6331 6332 static int 6333 handle_fw_msg(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 6334 { 6335 struct adapter *sc = iq->adapter; 6336 const struct cpl_fw6_msg *cpl = (const void *)(rss + 1); 6337 6338 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 6339 rss->opcode)); 6340 6341 if (cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL) { 6342 const struct rss_header *rss2; 6343 6344 rss2 = (const struct rss_header *)&cpl->data[0]; 6345 return (t4_cpl_handler[rss2->opcode](iq, rss2, m)); 6346 } 6347 6348 return (t4_fw_msg_handler[cpl->type](sc, &cpl->data[0])); 6349 } 6350 6351 /** 6352 * t4_handle_wrerr_rpl - process a FW work request error message 6353 * @adap: the adapter 6354 * @rpl: start of the FW message 6355 */ 6356 static int 6357 t4_handle_wrerr_rpl(struct adapter *adap, const __be64 *rpl) 6358 { 6359 u8 opcode = *(const u8 *)rpl; 6360 const struct fw_error_cmd *e = (const void *)rpl; 6361 unsigned int i; 6362 6363 if (opcode != FW_ERROR_CMD) { 6364 log(LOG_ERR, 6365 "%s: Received WRERR_RPL message with opcode %#x\n", 6366 device_get_nameunit(adap->dev), opcode); 6367 return (EINVAL); 6368 } 6369 log(LOG_ERR, "%s: FW_ERROR (%s) ", device_get_nameunit(adap->dev), 6370 G_FW_ERROR_CMD_FATAL(be32toh(e->op_to_type)) ? "fatal" : 6371 "non-fatal"); 6372 switch (G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type))) { 6373 case FW_ERROR_TYPE_EXCEPTION: 6374 log(LOG_ERR, "exception info:\n"); 6375 for (i = 0; i < nitems(e->u.exception.info); i++) 6376 log(LOG_ERR, "%s%08x", i == 0 ? "\t" : " ", 6377 be32toh(e->u.exception.info[i])); 6378 log(LOG_ERR, "\n"); 6379 break; 6380 case FW_ERROR_TYPE_HWMODULE: 6381 log(LOG_ERR, "HW module regaddr %08x regval %08x\n", 6382 be32toh(e->u.hwmodule.regaddr), 6383 be32toh(e->u.hwmodule.regval)); 6384 break; 6385 case FW_ERROR_TYPE_WR: 6386 log(LOG_ERR, "WR cidx %d PF %d VF %d eqid %d hdr:\n", 6387 be16toh(e->u.wr.cidx), 6388 G_FW_ERROR_CMD_PFN(be16toh(e->u.wr.pfn_vfn)), 6389 G_FW_ERROR_CMD_VFN(be16toh(e->u.wr.pfn_vfn)), 6390 be32toh(e->u.wr.eqid)); 6391 for (i = 0; i < nitems(e->u.wr.wrhdr); i++) 6392 log(LOG_ERR, "%s%02x", i == 0 ? "\t" : " ", 6393 e->u.wr.wrhdr[i]); 6394 log(LOG_ERR, "\n"); 6395 break; 6396 case FW_ERROR_TYPE_ACL: 6397 log(LOG_ERR, "ACL cidx %d PF %d VF %d eqid %d %s", 6398 be16toh(e->u.acl.cidx), 6399 G_FW_ERROR_CMD_PFN(be16toh(e->u.acl.pfn_vfn)), 6400 G_FW_ERROR_CMD_VFN(be16toh(e->u.acl.pfn_vfn)), 6401 be32toh(e->u.acl.eqid), 6402 G_FW_ERROR_CMD_MV(be16toh(e->u.acl.mv_pkd)) ? "vlanid" : 6403 "MAC"); 6404 for (i = 0; i < nitems(e->u.acl.val); i++) 6405 log(LOG_ERR, " %02x", e->u.acl.val[i]); 6406 log(LOG_ERR, "\n"); 6407 break; 6408 default: 6409 log(LOG_ERR, "type %#x\n", 6410 G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type))); 6411 return (EINVAL); 6412 } 6413 return (0); 6414 } 6415 6416 static inline bool 6417 bufidx_used(struct adapter *sc, int idx) 6418 { 6419 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[0]; 6420 int i; 6421 6422 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) { 6423 if (rxb->size1 > largest_rx_cluster) 6424 continue; 6425 if (rxb->hwidx1 == idx || rxb->hwidx2 == idx) 6426 return (true); 6427 } 6428 6429 return (false); 6430 } 6431 6432 static int 6433 sysctl_bufsizes(SYSCTL_HANDLER_ARGS) 6434 { 6435 struct adapter *sc = arg1; 6436 struct sge_params *sp = &sc->params.sge; 6437 int i, rc; 6438 struct sbuf sb; 6439 char c; 6440 6441 sbuf_new(&sb, NULL, 128, SBUF_AUTOEXTEND); 6442 for (i = 0; i < SGE_FLBUF_SIZES; i++) { 6443 if (bufidx_used(sc, i)) 6444 c = '*'; 6445 else 6446 c = '\0'; 6447 6448 sbuf_printf(&sb, "%u%c ", sp->sge_fl_buffer_size[i], c); 6449 } 6450 sbuf_trim(&sb); 6451 sbuf_finish(&sb); 6452 rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req); 6453 sbuf_delete(&sb); 6454 return (rc); 6455 } 6456 6457 #ifdef RATELIMIT 6458 #if defined(INET) || defined(INET6) 6459 /* 6460 * len16 for a txpkt WR with a GL. Includes the firmware work request header. 6461 */ 6462 static inline u_int 6463 txpkt_eo_len16(u_int nsegs, u_int immhdrs, u_int tso) 6464 { 6465 u_int n; 6466 6467 MPASS(immhdrs > 0); 6468 6469 n = roundup2(sizeof(struct fw_eth_tx_eo_wr) + 6470 sizeof(struct cpl_tx_pkt_core) + immhdrs, 16); 6471 if (__predict_false(nsegs == 0)) 6472 goto done; 6473 6474 nsegs--; /* first segment is part of ulptx_sgl */ 6475 n += sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 6476 if (tso) 6477 n += sizeof(struct cpl_tx_pkt_lso_core); 6478 6479 done: 6480 return (howmany(n, 16)); 6481 } 6482 #endif 6483 6484 #define ETID_FLOWC_NPARAMS 6 6485 #define ETID_FLOWC_LEN (roundup2((sizeof(struct fw_flowc_wr) + \ 6486 ETID_FLOWC_NPARAMS * sizeof(struct fw_flowc_mnemval)), 16)) 6487 #define ETID_FLOWC_LEN16 (howmany(ETID_FLOWC_LEN, 16)) 6488 6489 static int 6490 send_etid_flowc_wr(struct cxgbe_rate_tag *cst, struct port_info *pi, 6491 struct vi_info *vi) 6492 { 6493 struct wrq_cookie cookie; 6494 u_int pfvf = pi->adapter->pf << S_FW_VIID_PFN; 6495 struct fw_flowc_wr *flowc; 6496 6497 mtx_assert(&cst->lock, MA_OWNED); 6498 MPASS((cst->flags & (EO_FLOWC_PENDING | EO_FLOWC_RPL_PENDING)) == 6499 EO_FLOWC_PENDING); 6500 6501 flowc = start_wrq_wr(&cst->eo_txq->wrq, ETID_FLOWC_LEN16, &cookie); 6502 if (__predict_false(flowc == NULL)) 6503 return (ENOMEM); 6504 6505 bzero(flowc, ETID_FLOWC_LEN); 6506 flowc->op_to_nparams = htobe32(V_FW_WR_OP(FW_FLOWC_WR) | 6507 V_FW_FLOWC_WR_NPARAMS(ETID_FLOWC_NPARAMS) | V_FW_WR_COMPL(0)); 6508 flowc->flowid_len16 = htonl(V_FW_WR_LEN16(ETID_FLOWC_LEN16) | 6509 V_FW_WR_FLOWID(cst->etid)); 6510 flowc->mnemval[0].mnemonic = FW_FLOWC_MNEM_PFNVFN; 6511 flowc->mnemval[0].val = htobe32(pfvf); 6512 flowc->mnemval[1].mnemonic = FW_FLOWC_MNEM_CH; 6513 flowc->mnemval[1].val = htobe32(pi->tx_chan); 6514 flowc->mnemval[2].mnemonic = FW_FLOWC_MNEM_PORT; 6515 flowc->mnemval[2].val = htobe32(pi->tx_chan); 6516 flowc->mnemval[3].mnemonic = FW_FLOWC_MNEM_IQID; 6517 flowc->mnemval[3].val = htobe32(cst->iqid); 6518 flowc->mnemval[4].mnemonic = FW_FLOWC_MNEM_EOSTATE; 6519 flowc->mnemval[4].val = htobe32(FW_FLOWC_MNEM_EOSTATE_ESTABLISHED); 6520 flowc->mnemval[5].mnemonic = FW_FLOWC_MNEM_SCHEDCLASS; 6521 flowc->mnemval[5].val = htobe32(cst->schedcl); 6522 6523 commit_wrq_wr(&cst->eo_txq->wrq, flowc, &cookie); 6524 6525 cst->flags &= ~EO_FLOWC_PENDING; 6526 cst->flags |= EO_FLOWC_RPL_PENDING; 6527 MPASS(cst->tx_credits >= ETID_FLOWC_LEN16); /* flowc is first WR. */ 6528 cst->tx_credits -= ETID_FLOWC_LEN16; 6529 6530 return (0); 6531 } 6532 6533 #define ETID_FLUSH_LEN16 (howmany(sizeof (struct fw_flowc_wr), 16)) 6534 6535 void 6536 send_etid_flush_wr(struct cxgbe_rate_tag *cst) 6537 { 6538 struct fw_flowc_wr *flowc; 6539 struct wrq_cookie cookie; 6540 6541 mtx_assert(&cst->lock, MA_OWNED); 6542 6543 flowc = start_wrq_wr(&cst->eo_txq->wrq, ETID_FLUSH_LEN16, &cookie); 6544 if (__predict_false(flowc == NULL)) 6545 CXGBE_UNIMPLEMENTED(__func__); 6546 6547 bzero(flowc, ETID_FLUSH_LEN16 * 16); 6548 flowc->op_to_nparams = htobe32(V_FW_WR_OP(FW_FLOWC_WR) | 6549 V_FW_FLOWC_WR_NPARAMS(0) | F_FW_WR_COMPL); 6550 flowc->flowid_len16 = htobe32(V_FW_WR_LEN16(ETID_FLUSH_LEN16) | 6551 V_FW_WR_FLOWID(cst->etid)); 6552 6553 commit_wrq_wr(&cst->eo_txq->wrq, flowc, &cookie); 6554 6555 cst->flags |= EO_FLUSH_RPL_PENDING; 6556 MPASS(cst->tx_credits >= ETID_FLUSH_LEN16); 6557 cst->tx_credits -= ETID_FLUSH_LEN16; 6558 cst->ncompl++; 6559 } 6560 6561 static void 6562 write_ethofld_wr(struct cxgbe_rate_tag *cst, struct fw_eth_tx_eo_wr *wr, 6563 struct mbuf *m0, int compl) 6564 { 6565 struct cpl_tx_pkt_core *cpl; 6566 uint64_t ctrl1; 6567 uint32_t ctrl; /* used in many unrelated places */ 6568 int len16, pktlen, nsegs, immhdrs; 6569 caddr_t dst; 6570 uintptr_t p; 6571 struct ulptx_sgl *usgl; 6572 struct sglist sg; 6573 struct sglist_seg segs[38]; /* XXX: find real limit. XXX: get off the stack */ 6574 6575 mtx_assert(&cst->lock, MA_OWNED); 6576 M_ASSERTPKTHDR(m0); 6577 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 6578 m0->m_pkthdr.l4hlen > 0, 6579 ("%s: ethofld mbuf %p is missing header lengths", __func__, m0)); 6580 6581 len16 = mbuf_eo_len16(m0); 6582 nsegs = mbuf_eo_nsegs(m0); 6583 pktlen = m0->m_pkthdr.len; 6584 ctrl = sizeof(struct cpl_tx_pkt_core); 6585 if (needs_tso(m0)) 6586 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 6587 immhdrs = m0->m_pkthdr.l2hlen + m0->m_pkthdr.l3hlen + m0->m_pkthdr.l4hlen; 6588 ctrl += immhdrs; 6589 6590 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_EO_WR) | 6591 V_FW_ETH_TX_EO_WR_IMMDLEN(ctrl) | V_FW_WR_COMPL(!!compl)); 6592 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(len16) | 6593 V_FW_WR_FLOWID(cst->etid)); 6594 wr->r3 = 0; 6595 if (needs_outer_udp_csum(m0)) { 6596 wr->u.udpseg.type = FW_ETH_TX_EO_TYPE_UDPSEG; 6597 wr->u.udpseg.ethlen = m0->m_pkthdr.l2hlen; 6598 wr->u.udpseg.iplen = htobe16(m0->m_pkthdr.l3hlen); 6599 wr->u.udpseg.udplen = m0->m_pkthdr.l4hlen; 6600 wr->u.udpseg.rtplen = 0; 6601 wr->u.udpseg.r4 = 0; 6602 wr->u.udpseg.mss = htobe16(pktlen - immhdrs); 6603 wr->u.udpseg.schedpktsize = wr->u.udpseg.mss; 6604 wr->u.udpseg.plen = htobe32(pktlen - immhdrs); 6605 cpl = (void *)(wr + 1); 6606 } else { 6607 MPASS(needs_outer_tcp_csum(m0)); 6608 wr->u.tcpseg.type = FW_ETH_TX_EO_TYPE_TCPSEG; 6609 wr->u.tcpseg.ethlen = m0->m_pkthdr.l2hlen; 6610 wr->u.tcpseg.iplen = htobe16(m0->m_pkthdr.l3hlen); 6611 wr->u.tcpseg.tcplen = m0->m_pkthdr.l4hlen; 6612 wr->u.tcpseg.tsclk_tsoff = mbuf_eo_tsclk_tsoff(m0); 6613 wr->u.tcpseg.r4 = 0; 6614 wr->u.tcpseg.r5 = 0; 6615 wr->u.tcpseg.plen = htobe32(pktlen - immhdrs); 6616 6617 if (needs_tso(m0)) { 6618 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1); 6619 6620 wr->u.tcpseg.mss = htobe16(m0->m_pkthdr.tso_segsz); 6621 6622 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | 6623 F_LSO_FIRST_SLICE | F_LSO_LAST_SLICE | 6624 V_LSO_ETHHDR_LEN((m0->m_pkthdr.l2hlen - 6625 ETHER_HDR_LEN) >> 2) | 6626 V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) | 6627 V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2); 6628 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 6629 ctrl |= F_LSO_IPV6; 6630 lso->lso_ctrl = htobe32(ctrl); 6631 lso->ipid_ofst = htobe16(0); 6632 lso->mss = htobe16(m0->m_pkthdr.tso_segsz); 6633 lso->seqno_offset = htobe32(0); 6634 lso->len = htobe32(pktlen); 6635 6636 cpl = (void *)(lso + 1); 6637 } else { 6638 wr->u.tcpseg.mss = htobe16(0xffff); 6639 cpl = (void *)(wr + 1); 6640 } 6641 } 6642 6643 /* Checksum offload must be requested for ethofld. */ 6644 MPASS(needs_outer_l4_csum(m0)); 6645 ctrl1 = csum_to_ctrl(cst->adapter, m0); 6646 6647 /* VLAN tag insertion */ 6648 if (needs_vlan_insertion(m0)) { 6649 ctrl1 |= F_TXPKT_VLAN_VLD | 6650 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 6651 } 6652 6653 /* CPL header */ 6654 cpl->ctrl0 = cst->ctrl0; 6655 cpl->pack = 0; 6656 cpl->len = htobe16(pktlen); 6657 cpl->ctrl1 = htobe64(ctrl1); 6658 6659 /* Copy Ethernet, IP & TCP/UDP hdrs as immediate data */ 6660 p = (uintptr_t)(cpl + 1); 6661 m_copydata(m0, 0, immhdrs, (void *)p); 6662 6663 /* SGL */ 6664 dst = (void *)(cpl + 1); 6665 if (nsegs > 0) { 6666 int i, pad; 6667 6668 /* zero-pad upto next 16Byte boundary, if not 16Byte aligned */ 6669 p += immhdrs; 6670 pad = 16 - (immhdrs & 0xf); 6671 bzero((void *)p, pad); 6672 6673 usgl = (void *)(p + pad); 6674 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 6675 V_ULPTX_NSGE(nsegs)); 6676 6677 sglist_init(&sg, nitems(segs), segs); 6678 for (; m0 != NULL; m0 = m0->m_next) { 6679 if (__predict_false(m0->m_len == 0)) 6680 continue; 6681 if (immhdrs >= m0->m_len) { 6682 immhdrs -= m0->m_len; 6683 continue; 6684 } 6685 if (m0->m_flags & M_EXTPG) 6686 sglist_append_mbuf_epg(&sg, m0, 6687 mtod(m0, vm_offset_t), m0->m_len); 6688 else 6689 sglist_append(&sg, mtod(m0, char *) + immhdrs, 6690 m0->m_len - immhdrs); 6691 immhdrs = 0; 6692 } 6693 MPASS(sg.sg_nseg == nsegs); 6694 6695 /* 6696 * Zero pad last 8B in case the WR doesn't end on a 16B 6697 * boundary. 6698 */ 6699 *(uint64_t *)((char *)wr + len16 * 16 - 8) = 0; 6700 6701 usgl->len0 = htobe32(segs[0].ss_len); 6702 usgl->addr0 = htobe64(segs[0].ss_paddr); 6703 for (i = 0; i < nsegs - 1; i++) { 6704 usgl->sge[i / 2].len[i & 1] = htobe32(segs[i + 1].ss_len); 6705 usgl->sge[i / 2].addr[i & 1] = htobe64(segs[i + 1].ss_paddr); 6706 } 6707 if (i & 1) 6708 usgl->sge[i / 2].len[1] = htobe32(0); 6709 } 6710 6711 } 6712 6713 static void 6714 ethofld_tx(struct cxgbe_rate_tag *cst) 6715 { 6716 struct mbuf *m; 6717 struct wrq_cookie cookie; 6718 int next_credits, compl; 6719 struct fw_eth_tx_eo_wr *wr; 6720 6721 mtx_assert(&cst->lock, MA_OWNED); 6722 6723 while ((m = mbufq_first(&cst->pending_tx)) != NULL) { 6724 M_ASSERTPKTHDR(m); 6725 6726 /* How many len16 credits do we need to send this mbuf. */ 6727 next_credits = mbuf_eo_len16(m); 6728 MPASS(next_credits > 0); 6729 if (next_credits > cst->tx_credits) { 6730 /* 6731 * Tx will make progress eventually because there is at 6732 * least one outstanding fw4_ack that will return 6733 * credits and kick the tx. 6734 */ 6735 MPASS(cst->ncompl > 0); 6736 return; 6737 } 6738 wr = start_wrq_wr(&cst->eo_txq->wrq, next_credits, &cookie); 6739 if (__predict_false(wr == NULL)) { 6740 /* XXX: wishful thinking, not a real assertion. */ 6741 MPASS(cst->ncompl > 0); 6742 return; 6743 } 6744 cst->tx_credits -= next_credits; 6745 cst->tx_nocompl += next_credits; 6746 compl = cst->ncompl == 0 || cst->tx_nocompl >= cst->tx_total / 2; 6747 ETHER_BPF_MTAP(cst->com.ifp, m); 6748 write_ethofld_wr(cst, wr, m, compl); 6749 commit_wrq_wr(&cst->eo_txq->wrq, wr, &cookie); 6750 if (compl) { 6751 cst->ncompl++; 6752 cst->tx_nocompl = 0; 6753 } 6754 (void) mbufq_dequeue(&cst->pending_tx); 6755 6756 /* 6757 * Drop the mbuf's reference on the tag now rather 6758 * than waiting until m_freem(). This ensures that 6759 * cxgbe_rate_tag_free gets called when the inp drops 6760 * its reference on the tag and there are no more 6761 * mbufs in the pending_tx queue and can flush any 6762 * pending requests. Otherwise if the last mbuf 6763 * doesn't request a completion the etid will never be 6764 * released. 6765 */ 6766 m->m_pkthdr.snd_tag = NULL; 6767 m->m_pkthdr.csum_flags &= ~CSUM_SND_TAG; 6768 m_snd_tag_rele(&cst->com); 6769 6770 mbufq_enqueue(&cst->pending_fwack, m); 6771 } 6772 } 6773 6774 int 6775 ethofld_transmit(struct ifnet *ifp, struct mbuf *m0) 6776 { 6777 struct cxgbe_rate_tag *cst; 6778 int rc; 6779 6780 MPASS(m0->m_nextpkt == NULL); 6781 MPASS(m0->m_pkthdr.csum_flags & CSUM_SND_TAG); 6782 MPASS(m0->m_pkthdr.snd_tag != NULL); 6783 cst = mst_to_crt(m0->m_pkthdr.snd_tag); 6784 6785 mtx_lock(&cst->lock); 6786 MPASS(cst->flags & EO_SND_TAG_REF); 6787 6788 if (__predict_false(cst->flags & EO_FLOWC_PENDING)) { 6789 struct vi_info *vi = ifp->if_softc; 6790 struct port_info *pi = vi->pi; 6791 struct adapter *sc = pi->adapter; 6792 const uint32_t rss_mask = vi->rss_size - 1; 6793 uint32_t rss_hash; 6794 6795 cst->eo_txq = &sc->sge.ofld_txq[vi->first_ofld_txq]; 6796 if (M_HASHTYPE_ISHASH(m0)) 6797 rss_hash = m0->m_pkthdr.flowid; 6798 else 6799 rss_hash = arc4random(); 6800 /* We assume RSS hashing */ 6801 cst->iqid = vi->rss[rss_hash & rss_mask]; 6802 cst->eo_txq += rss_hash % vi->nofldtxq; 6803 rc = send_etid_flowc_wr(cst, pi, vi); 6804 if (rc != 0) 6805 goto done; 6806 } 6807 6808 if (__predict_false(cst->plen + m0->m_pkthdr.len > eo_max_backlog)) { 6809 rc = ENOBUFS; 6810 goto done; 6811 } 6812 6813 mbufq_enqueue(&cst->pending_tx, m0); 6814 cst->plen += m0->m_pkthdr.len; 6815 6816 /* 6817 * Hold an extra reference on the tag while generating work 6818 * requests to ensure that we don't try to free the tag during 6819 * ethofld_tx() in case we are sending the final mbuf after 6820 * the inp was freed. 6821 */ 6822 m_snd_tag_ref(&cst->com); 6823 ethofld_tx(cst); 6824 mtx_unlock(&cst->lock); 6825 m_snd_tag_rele(&cst->com); 6826 return (0); 6827 6828 done: 6829 mtx_unlock(&cst->lock); 6830 if (__predict_false(rc != 0)) 6831 m_freem(m0); 6832 return (rc); 6833 } 6834 6835 static int 6836 ethofld_fw4_ack(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0) 6837 { 6838 struct adapter *sc = iq->adapter; 6839 const struct cpl_fw4_ack *cpl = (const void *)(rss + 1); 6840 struct mbuf *m; 6841 u_int etid = G_CPL_FW4_ACK_FLOWID(be32toh(OPCODE_TID(cpl))); 6842 struct cxgbe_rate_tag *cst; 6843 uint8_t credits = cpl->credits; 6844 6845 cst = lookup_etid(sc, etid); 6846 mtx_lock(&cst->lock); 6847 if (__predict_false(cst->flags & EO_FLOWC_RPL_PENDING)) { 6848 MPASS(credits >= ETID_FLOWC_LEN16); 6849 credits -= ETID_FLOWC_LEN16; 6850 cst->flags &= ~EO_FLOWC_RPL_PENDING; 6851 } 6852 6853 KASSERT(cst->ncompl > 0, 6854 ("%s: etid %u (%p) wasn't expecting completion.", 6855 __func__, etid, cst)); 6856 cst->ncompl--; 6857 6858 while (credits > 0) { 6859 m = mbufq_dequeue(&cst->pending_fwack); 6860 if (__predict_false(m == NULL)) { 6861 /* 6862 * The remaining credits are for the final flush that 6863 * was issued when the tag was freed by the kernel. 6864 */ 6865 MPASS((cst->flags & 6866 (EO_FLUSH_RPL_PENDING | EO_SND_TAG_REF)) == 6867 EO_FLUSH_RPL_PENDING); 6868 MPASS(credits == ETID_FLUSH_LEN16); 6869 MPASS(cst->tx_credits + cpl->credits == cst->tx_total); 6870 MPASS(cst->ncompl == 0); 6871 6872 cst->flags &= ~EO_FLUSH_RPL_PENDING; 6873 cst->tx_credits += cpl->credits; 6874 cxgbe_rate_tag_free_locked(cst); 6875 return (0); /* cst is gone. */ 6876 } 6877 KASSERT(m != NULL, 6878 ("%s: too many credits (%u, %u)", __func__, cpl->credits, 6879 credits)); 6880 KASSERT(credits >= mbuf_eo_len16(m), 6881 ("%s: too few credits (%u, %u, %u)", __func__, 6882 cpl->credits, credits, mbuf_eo_len16(m))); 6883 credits -= mbuf_eo_len16(m); 6884 cst->plen -= m->m_pkthdr.len; 6885 m_freem(m); 6886 } 6887 6888 cst->tx_credits += cpl->credits; 6889 MPASS(cst->tx_credits <= cst->tx_total); 6890 6891 if (cst->flags & EO_SND_TAG_REF) { 6892 /* 6893 * As with ethofld_transmit(), hold an extra reference 6894 * so that the tag is stable across ethold_tx(). 6895 */ 6896 m_snd_tag_ref(&cst->com); 6897 m = mbufq_first(&cst->pending_tx); 6898 if (m != NULL && cst->tx_credits >= mbuf_eo_len16(m)) 6899 ethofld_tx(cst); 6900 mtx_unlock(&cst->lock); 6901 m_snd_tag_rele(&cst->com); 6902 } else { 6903 /* 6904 * There shouldn't be any pending packets if the tag 6905 * was freed by the kernel since any pending packet 6906 * should hold a reference to the tag. 6907 */ 6908 MPASS(mbufq_first(&cst->pending_tx) == NULL); 6909 mtx_unlock(&cst->lock); 6910 } 6911 6912 return (0); 6913 } 6914 #endif 6915