1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 Chelsio Communications, Inc. 5 * All rights reserved. 6 * Written by: Navdeep Parhar <np@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include "opt_inet.h" 34 #include "opt_inet6.h" 35 #include "opt_ratelimit.h" 36 37 #include <sys/types.h> 38 #include <sys/eventhandler.h> 39 #include <sys/mbuf.h> 40 #include <sys/socket.h> 41 #include <sys/kernel.h> 42 #include <sys/malloc.h> 43 #include <sys/queue.h> 44 #include <sys/sbuf.h> 45 #include <sys/taskqueue.h> 46 #include <sys/time.h> 47 #include <sys/sglist.h> 48 #include <sys/sysctl.h> 49 #include <sys/smp.h> 50 #include <sys/counter.h> 51 #include <net/bpf.h> 52 #include <net/ethernet.h> 53 #include <net/if.h> 54 #include <net/if_vlan_var.h> 55 #include <netinet/in.h> 56 #include <netinet/ip.h> 57 #include <netinet/ip6.h> 58 #include <netinet/tcp.h> 59 #include <netinet/udp.h> 60 #include <machine/in_cksum.h> 61 #include <machine/md_var.h> 62 #include <vm/vm.h> 63 #include <vm/pmap.h> 64 #ifdef DEV_NETMAP 65 #include <machine/bus.h> 66 #include <sys/selinfo.h> 67 #include <net/if_var.h> 68 #include <net/netmap.h> 69 #include <dev/netmap/netmap_kern.h> 70 #endif 71 72 #include "common/common.h" 73 #include "common/t4_regs.h" 74 #include "common/t4_regs_values.h" 75 #include "common/t4_msg.h" 76 #include "t4_l2t.h" 77 #include "t4_mp_ring.h" 78 79 #ifdef T4_PKT_TIMESTAMP 80 #define RX_COPY_THRESHOLD (MINCLSIZE - 8) 81 #else 82 #define RX_COPY_THRESHOLD MINCLSIZE 83 #endif 84 85 /* 86 * Ethernet frames are DMA'd at this byte offset into the freelist buffer. 87 * 0-7 are valid values. 88 */ 89 static int fl_pktshift = 0; 90 TUNABLE_INT("hw.cxgbe.fl_pktshift", &fl_pktshift); 91 92 /* 93 * Pad ethernet payload up to this boundary. 94 * -1: driver should figure out a good value. 95 * 0: disable padding. 96 * Any power of 2 from 32 to 4096 (both inclusive) is also a valid value. 97 */ 98 int fl_pad = -1; 99 TUNABLE_INT("hw.cxgbe.fl_pad", &fl_pad); 100 101 /* 102 * Status page length. 103 * -1: driver should figure out a good value. 104 * 64 or 128 are the only other valid values. 105 */ 106 static int spg_len = -1; 107 TUNABLE_INT("hw.cxgbe.spg_len", &spg_len); 108 109 /* 110 * Congestion drops. 111 * -1: no congestion feedback (not recommended). 112 * 0: backpressure the channel instead of dropping packets right away. 113 * 1: no backpressure, drop packets for the congested queue immediately. 114 */ 115 static int cong_drop = 0; 116 TUNABLE_INT("hw.cxgbe.cong_drop", &cong_drop); 117 118 /* 119 * Deliver multiple frames in the same free list buffer if they fit. 120 * -1: let the driver decide whether to enable buffer packing or not. 121 * 0: disable buffer packing. 122 * 1: enable buffer packing. 123 */ 124 static int buffer_packing = -1; 125 TUNABLE_INT("hw.cxgbe.buffer_packing", &buffer_packing); 126 127 /* 128 * Start next frame in a packed buffer at this boundary. 129 * -1: driver should figure out a good value. 130 * T4: driver will ignore this and use the same value as fl_pad above. 131 * T5: 16, or a power of 2 from 64 to 4096 (both inclusive) is a valid value. 132 */ 133 static int fl_pack = -1; 134 TUNABLE_INT("hw.cxgbe.fl_pack", &fl_pack); 135 136 /* 137 * Allow the driver to create mbuf(s) in a cluster allocated for rx. 138 * 0: never; always allocate mbufs from the zone_mbuf UMA zone. 139 * 1: ok to create mbuf(s) within a cluster if there is room. 140 */ 141 static int allow_mbufs_in_cluster = 1; 142 TUNABLE_INT("hw.cxgbe.allow_mbufs_in_cluster", &allow_mbufs_in_cluster); 143 144 /* 145 * Largest rx cluster size that the driver is allowed to allocate. 146 */ 147 static int largest_rx_cluster = MJUM16BYTES; 148 TUNABLE_INT("hw.cxgbe.largest_rx_cluster", &largest_rx_cluster); 149 150 /* 151 * Size of cluster allocation that's most likely to succeed. The driver will 152 * fall back to this size if it fails to allocate clusters larger than this. 153 */ 154 static int safest_rx_cluster = PAGE_SIZE; 155 TUNABLE_INT("hw.cxgbe.safest_rx_cluster", &safest_rx_cluster); 156 157 #ifdef RATELIMIT 158 /* 159 * Knob to control TCP timestamp rewriting, and the granularity of the tick used 160 * for rewriting. -1 and 0-3 are all valid values. 161 * -1: hardware should leave the TCP timestamps alone. 162 * 0: 1ms 163 * 1: 100us 164 * 2: 10us 165 * 3: 1us 166 */ 167 static int tsclk = -1; 168 TUNABLE_INT("hw.cxgbe.tsclk", &tsclk); 169 170 static int eo_max_backlog = 1024 * 1024; 171 TUNABLE_INT("hw.cxgbe.eo_max_backlog", &eo_max_backlog); 172 #endif 173 174 /* 175 * The interrupt holdoff timers are multiplied by this value on T6+. 176 * 1 and 3-17 (both inclusive) are legal values. 177 */ 178 static int tscale = 1; 179 TUNABLE_INT("hw.cxgbe.tscale", &tscale); 180 181 /* 182 * Number of LRO entries in the lro_ctrl structure per rx queue. 183 */ 184 static int lro_entries = TCP_LRO_ENTRIES; 185 TUNABLE_INT("hw.cxgbe.lro_entries", &lro_entries); 186 187 /* 188 * This enables presorting of frames before they're fed into tcp_lro_rx. 189 */ 190 static int lro_mbufs = 0; 191 TUNABLE_INT("hw.cxgbe.lro_mbufs", &lro_mbufs); 192 193 struct txpkts { 194 u_int wr_type; /* type 0 or type 1 */ 195 u_int npkt; /* # of packets in this work request */ 196 u_int plen; /* total payload (sum of all packets) */ 197 u_int len16; /* # of 16B pieces used by this work request */ 198 }; 199 200 /* A packet's SGL. This + m_pkthdr has all info needed for tx */ 201 struct sgl { 202 struct sglist sg; 203 struct sglist_seg seg[TX_SGL_SEGS]; 204 }; 205 206 static int service_iq(struct sge_iq *, int); 207 static int service_iq_fl(struct sge_iq *, int); 208 static struct mbuf *get_fl_payload(struct adapter *, struct sge_fl *, uint32_t); 209 static int t4_eth_rx(struct sge_iq *, const struct rss_header *, struct mbuf *); 210 static inline void init_iq(struct sge_iq *, struct adapter *, int, int, int); 211 static inline void init_fl(struct adapter *, struct sge_fl *, int, int, char *); 212 static inline void init_eq(struct adapter *, struct sge_eq *, int, int, uint8_t, 213 uint16_t, char *); 214 static int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *, 215 bus_addr_t *, void **); 216 static int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 217 void *); 218 static int alloc_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *, 219 int, int); 220 static int free_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *); 221 static void add_iq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *, 222 struct sge_iq *); 223 static void add_fl_sysctls(struct adapter *, struct sysctl_ctx_list *, 224 struct sysctl_oid *, struct sge_fl *); 225 static int alloc_fwq(struct adapter *); 226 static int free_fwq(struct adapter *); 227 static int alloc_ctrlq(struct adapter *, struct sge_wrq *, int, 228 struct sysctl_oid *); 229 static int alloc_rxq(struct vi_info *, struct sge_rxq *, int, int, 230 struct sysctl_oid *); 231 static int free_rxq(struct vi_info *, struct sge_rxq *); 232 #ifdef TCP_OFFLOAD 233 static int alloc_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *, int, int, 234 struct sysctl_oid *); 235 static int free_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *); 236 #endif 237 #ifdef DEV_NETMAP 238 static int alloc_nm_rxq(struct vi_info *, struct sge_nm_rxq *, int, int, 239 struct sysctl_oid *); 240 static int free_nm_rxq(struct vi_info *, struct sge_nm_rxq *); 241 static int alloc_nm_txq(struct vi_info *, struct sge_nm_txq *, int, int, 242 struct sysctl_oid *); 243 static int free_nm_txq(struct vi_info *, struct sge_nm_txq *); 244 #endif 245 static int ctrl_eq_alloc(struct adapter *, struct sge_eq *); 246 static int eth_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *); 247 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 248 static int ofld_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *); 249 #endif 250 static int alloc_eq(struct adapter *, struct vi_info *, struct sge_eq *); 251 static int free_eq(struct adapter *, struct sge_eq *); 252 static int alloc_wrq(struct adapter *, struct vi_info *, struct sge_wrq *, 253 struct sysctl_oid *); 254 static int free_wrq(struct adapter *, struct sge_wrq *); 255 static int alloc_txq(struct vi_info *, struct sge_txq *, int, 256 struct sysctl_oid *); 257 static int free_txq(struct vi_info *, struct sge_txq *); 258 static void oneseg_dma_callback(void *, bus_dma_segment_t *, int, int); 259 static inline void ring_fl_db(struct adapter *, struct sge_fl *); 260 static int refill_fl(struct adapter *, struct sge_fl *, int); 261 static void refill_sfl(void *); 262 static int alloc_fl_sdesc(struct sge_fl *); 263 static void free_fl_sdesc(struct adapter *, struct sge_fl *); 264 static void find_best_refill_source(struct adapter *, struct sge_fl *, int); 265 static void find_safe_refill_source(struct adapter *, struct sge_fl *); 266 static void add_fl_to_sfl(struct adapter *, struct sge_fl *); 267 268 static inline void get_pkt_gl(struct mbuf *, struct sglist *); 269 static inline u_int txpkt_len16(u_int, u_int); 270 static inline u_int txpkt_vm_len16(u_int, u_int); 271 static inline u_int txpkts0_len16(u_int); 272 static inline u_int txpkts1_len16(void); 273 static u_int write_txpkt_wr(struct sge_txq *, struct fw_eth_tx_pkt_wr *, 274 struct mbuf *, u_int); 275 static u_int write_txpkt_vm_wr(struct adapter *, struct sge_txq *, 276 struct fw_eth_tx_pkt_vm_wr *, struct mbuf *, u_int); 277 static int try_txpkts(struct mbuf *, struct mbuf *, struct txpkts *, u_int); 278 static int add_to_txpkts(struct mbuf *, struct txpkts *, u_int); 279 static u_int write_txpkts_wr(struct sge_txq *, struct fw_eth_tx_pkts_wr *, 280 struct mbuf *, const struct txpkts *, u_int); 281 static void write_gl_to_txd(struct sge_txq *, struct mbuf *, caddr_t *, int); 282 static inline void copy_to_txd(struct sge_eq *, caddr_t, caddr_t *, int); 283 static inline void ring_eq_db(struct adapter *, struct sge_eq *, u_int); 284 static inline uint16_t read_hw_cidx(struct sge_eq *); 285 static inline u_int reclaimable_tx_desc(struct sge_eq *); 286 static inline u_int total_available_tx_desc(struct sge_eq *); 287 static u_int reclaim_tx_descs(struct sge_txq *, u_int); 288 static void tx_reclaim(void *, int); 289 static __be64 get_flit(struct sglist_seg *, int, int); 290 static int handle_sge_egr_update(struct sge_iq *, const struct rss_header *, 291 struct mbuf *); 292 static int handle_fw_msg(struct sge_iq *, const struct rss_header *, 293 struct mbuf *); 294 static int t4_handle_wrerr_rpl(struct adapter *, const __be64 *); 295 static void wrq_tx_drain(void *, int); 296 static void drain_wrq_wr_list(struct adapter *, struct sge_wrq *); 297 298 static int sysctl_uint16(SYSCTL_HANDLER_ARGS); 299 static int sysctl_bufsizes(SYSCTL_HANDLER_ARGS); 300 #ifdef RATELIMIT 301 static inline u_int txpkt_eo_len16(u_int, u_int, u_int); 302 static int ethofld_fw4_ack(struct sge_iq *, const struct rss_header *, 303 struct mbuf *); 304 #endif 305 306 static counter_u64_t extfree_refs; 307 static counter_u64_t extfree_rels; 308 309 an_handler_t t4_an_handler; 310 fw_msg_handler_t t4_fw_msg_handler[NUM_FW6_TYPES]; 311 cpl_handler_t t4_cpl_handler[NUM_CPL_CMDS]; 312 cpl_handler_t set_tcb_rpl_handlers[NUM_CPL_COOKIES]; 313 cpl_handler_t l2t_write_rpl_handlers[NUM_CPL_COOKIES]; 314 cpl_handler_t act_open_rpl_handlers[NUM_CPL_COOKIES]; 315 cpl_handler_t abort_rpl_rss_handlers[NUM_CPL_COOKIES]; 316 cpl_handler_t fw4_ack_handlers[NUM_CPL_COOKIES]; 317 318 void 319 t4_register_an_handler(an_handler_t h) 320 { 321 uintptr_t *loc; 322 323 MPASS(h == NULL || t4_an_handler == NULL); 324 325 loc = (uintptr_t *)&t4_an_handler; 326 atomic_store_rel_ptr(loc, (uintptr_t)h); 327 } 328 329 void 330 t4_register_fw_msg_handler(int type, fw_msg_handler_t h) 331 { 332 uintptr_t *loc; 333 334 MPASS(type < nitems(t4_fw_msg_handler)); 335 MPASS(h == NULL || t4_fw_msg_handler[type] == NULL); 336 /* 337 * These are dispatched by the handler for FW{4|6}_CPL_MSG using the CPL 338 * handler dispatch table. Reject any attempt to install a handler for 339 * this subtype. 340 */ 341 MPASS(type != FW_TYPE_RSSCPL); 342 MPASS(type != FW6_TYPE_RSSCPL); 343 344 loc = (uintptr_t *)&t4_fw_msg_handler[type]; 345 atomic_store_rel_ptr(loc, (uintptr_t)h); 346 } 347 348 void 349 t4_register_cpl_handler(int opcode, cpl_handler_t h) 350 { 351 uintptr_t *loc; 352 353 MPASS(opcode < nitems(t4_cpl_handler)); 354 MPASS(h == NULL || t4_cpl_handler[opcode] == NULL); 355 356 loc = (uintptr_t *)&t4_cpl_handler[opcode]; 357 atomic_store_rel_ptr(loc, (uintptr_t)h); 358 } 359 360 static int 361 set_tcb_rpl_handler(struct sge_iq *iq, const struct rss_header *rss, 362 struct mbuf *m) 363 { 364 const struct cpl_set_tcb_rpl *cpl = (const void *)(rss + 1); 365 u_int tid; 366 int cookie; 367 368 MPASS(m == NULL); 369 370 tid = GET_TID(cpl); 371 if (is_hpftid(iq->adapter, tid) || is_ftid(iq->adapter, tid)) { 372 /* 373 * The return code for filter-write is put in the CPL cookie so 374 * we have to rely on the hardware tid (is_ftid) to determine 375 * that this is a response to a filter. 376 */ 377 cookie = CPL_COOKIE_FILTER; 378 } else { 379 cookie = G_COOKIE(cpl->cookie); 380 } 381 MPASS(cookie > CPL_COOKIE_RESERVED); 382 MPASS(cookie < nitems(set_tcb_rpl_handlers)); 383 384 return (set_tcb_rpl_handlers[cookie](iq, rss, m)); 385 } 386 387 static int 388 l2t_write_rpl_handler(struct sge_iq *iq, const struct rss_header *rss, 389 struct mbuf *m) 390 { 391 const struct cpl_l2t_write_rpl *rpl = (const void *)(rss + 1); 392 unsigned int cookie; 393 394 MPASS(m == NULL); 395 396 cookie = GET_TID(rpl) & F_SYNC_WR ? CPL_COOKIE_TOM : CPL_COOKIE_FILTER; 397 return (l2t_write_rpl_handlers[cookie](iq, rss, m)); 398 } 399 400 static int 401 act_open_rpl_handler(struct sge_iq *iq, const struct rss_header *rss, 402 struct mbuf *m) 403 { 404 const struct cpl_act_open_rpl *cpl = (const void *)(rss + 1); 405 u_int cookie = G_TID_COOKIE(G_AOPEN_ATID(be32toh(cpl->atid_status))); 406 407 MPASS(m == NULL); 408 MPASS(cookie != CPL_COOKIE_RESERVED); 409 410 return (act_open_rpl_handlers[cookie](iq, rss, m)); 411 } 412 413 static int 414 abort_rpl_rss_handler(struct sge_iq *iq, const struct rss_header *rss, 415 struct mbuf *m) 416 { 417 struct adapter *sc = iq->adapter; 418 u_int cookie; 419 420 MPASS(m == NULL); 421 if (is_hashfilter(sc)) 422 cookie = CPL_COOKIE_HASHFILTER; 423 else 424 cookie = CPL_COOKIE_TOM; 425 426 return (abort_rpl_rss_handlers[cookie](iq, rss, m)); 427 } 428 429 static int 430 fw4_ack_handler(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 431 { 432 struct adapter *sc = iq->adapter; 433 const struct cpl_fw4_ack *cpl = (const void *)(rss + 1); 434 unsigned int tid = G_CPL_FW4_ACK_FLOWID(be32toh(OPCODE_TID(cpl))); 435 u_int cookie; 436 437 MPASS(m == NULL); 438 if (is_etid(sc, tid)) 439 cookie = CPL_COOKIE_ETHOFLD; 440 else 441 cookie = CPL_COOKIE_TOM; 442 443 return (fw4_ack_handlers[cookie](iq, rss, m)); 444 } 445 446 static void 447 t4_init_shared_cpl_handlers(void) 448 { 449 450 t4_register_cpl_handler(CPL_SET_TCB_RPL, set_tcb_rpl_handler); 451 t4_register_cpl_handler(CPL_L2T_WRITE_RPL, l2t_write_rpl_handler); 452 t4_register_cpl_handler(CPL_ACT_OPEN_RPL, act_open_rpl_handler); 453 t4_register_cpl_handler(CPL_ABORT_RPL_RSS, abort_rpl_rss_handler); 454 t4_register_cpl_handler(CPL_FW4_ACK, fw4_ack_handler); 455 } 456 457 void 458 t4_register_shared_cpl_handler(int opcode, cpl_handler_t h, int cookie) 459 { 460 uintptr_t *loc; 461 462 MPASS(opcode < nitems(t4_cpl_handler)); 463 MPASS(cookie > CPL_COOKIE_RESERVED); 464 MPASS(cookie < NUM_CPL_COOKIES); 465 MPASS(t4_cpl_handler[opcode] != NULL); 466 467 switch (opcode) { 468 case CPL_SET_TCB_RPL: 469 loc = (uintptr_t *)&set_tcb_rpl_handlers[cookie]; 470 break; 471 case CPL_L2T_WRITE_RPL: 472 loc = (uintptr_t *)&l2t_write_rpl_handlers[cookie]; 473 break; 474 case CPL_ACT_OPEN_RPL: 475 loc = (uintptr_t *)&act_open_rpl_handlers[cookie]; 476 break; 477 case CPL_ABORT_RPL_RSS: 478 loc = (uintptr_t *)&abort_rpl_rss_handlers[cookie]; 479 break; 480 case CPL_FW4_ACK: 481 loc = (uintptr_t *)&fw4_ack_handlers[cookie]; 482 break; 483 default: 484 MPASS(0); 485 return; 486 } 487 MPASS(h == NULL || *loc == (uintptr_t)NULL); 488 atomic_store_rel_ptr(loc, (uintptr_t)h); 489 } 490 491 /* 492 * Called on MOD_LOAD. Validates and calculates the SGE tunables. 493 */ 494 void 495 t4_sge_modload(void) 496 { 497 498 if (fl_pktshift < 0 || fl_pktshift > 7) { 499 printf("Invalid hw.cxgbe.fl_pktshift value (%d)," 500 " using 0 instead.\n", fl_pktshift); 501 fl_pktshift = 0; 502 } 503 504 if (spg_len != 64 && spg_len != 128) { 505 int len; 506 507 #if defined(__i386__) || defined(__amd64__) 508 len = cpu_clflush_line_size > 64 ? 128 : 64; 509 #else 510 len = 64; 511 #endif 512 if (spg_len != -1) { 513 printf("Invalid hw.cxgbe.spg_len value (%d)," 514 " using %d instead.\n", spg_len, len); 515 } 516 spg_len = len; 517 } 518 519 if (cong_drop < -1 || cong_drop > 1) { 520 printf("Invalid hw.cxgbe.cong_drop value (%d)," 521 " using 0 instead.\n", cong_drop); 522 cong_drop = 0; 523 } 524 525 if (tscale != 1 && (tscale < 3 || tscale > 17)) { 526 printf("Invalid hw.cxgbe.tscale value (%d)," 527 " using 1 instead.\n", tscale); 528 tscale = 1; 529 } 530 531 extfree_refs = counter_u64_alloc(M_WAITOK); 532 extfree_rels = counter_u64_alloc(M_WAITOK); 533 counter_u64_zero(extfree_refs); 534 counter_u64_zero(extfree_rels); 535 536 t4_init_shared_cpl_handlers(); 537 t4_register_cpl_handler(CPL_FW4_MSG, handle_fw_msg); 538 t4_register_cpl_handler(CPL_FW6_MSG, handle_fw_msg); 539 t4_register_cpl_handler(CPL_SGE_EGR_UPDATE, handle_sge_egr_update); 540 t4_register_cpl_handler(CPL_RX_PKT, t4_eth_rx); 541 #ifdef RATELIMIT 542 t4_register_shared_cpl_handler(CPL_FW4_ACK, ethofld_fw4_ack, 543 CPL_COOKIE_ETHOFLD); 544 #endif 545 t4_register_fw_msg_handler(FW6_TYPE_CMD_RPL, t4_handle_fw_rpl); 546 t4_register_fw_msg_handler(FW6_TYPE_WRERR_RPL, t4_handle_wrerr_rpl); 547 } 548 549 void 550 t4_sge_modunload(void) 551 { 552 553 counter_u64_free(extfree_refs); 554 counter_u64_free(extfree_rels); 555 } 556 557 uint64_t 558 t4_sge_extfree_refs(void) 559 { 560 uint64_t refs, rels; 561 562 rels = counter_u64_fetch(extfree_rels); 563 refs = counter_u64_fetch(extfree_refs); 564 565 return (refs - rels); 566 } 567 568 static inline void 569 setup_pad_and_pack_boundaries(struct adapter *sc) 570 { 571 uint32_t v, m; 572 int pad, pack, pad_shift; 573 574 pad_shift = chip_id(sc) > CHELSIO_T5 ? X_T6_INGPADBOUNDARY_SHIFT : 575 X_INGPADBOUNDARY_SHIFT; 576 pad = fl_pad; 577 if (fl_pad < (1 << pad_shift) || 578 fl_pad > (1 << (pad_shift + M_INGPADBOUNDARY)) || 579 !powerof2(fl_pad)) { 580 /* 581 * If there is any chance that we might use buffer packing and 582 * the chip is a T4, then pick 64 as the pad/pack boundary. Set 583 * it to the minimum allowed in all other cases. 584 */ 585 pad = is_t4(sc) && buffer_packing ? 64 : 1 << pad_shift; 586 587 /* 588 * For fl_pad = 0 we'll still write a reasonable value to the 589 * register but all the freelists will opt out of padding. 590 * We'll complain here only if the user tried to set it to a 591 * value greater than 0 that was invalid. 592 */ 593 if (fl_pad > 0) { 594 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pad value" 595 " (%d), using %d instead.\n", fl_pad, pad); 596 } 597 } 598 m = V_INGPADBOUNDARY(M_INGPADBOUNDARY); 599 v = V_INGPADBOUNDARY(ilog2(pad) - pad_shift); 600 t4_set_reg_field(sc, A_SGE_CONTROL, m, v); 601 602 if (is_t4(sc)) { 603 if (fl_pack != -1 && fl_pack != pad) { 604 /* Complain but carry on. */ 605 device_printf(sc->dev, "hw.cxgbe.fl_pack (%d) ignored," 606 " using %d instead.\n", fl_pack, pad); 607 } 608 return; 609 } 610 611 pack = fl_pack; 612 if (fl_pack < 16 || fl_pack == 32 || fl_pack > 4096 || 613 !powerof2(fl_pack)) { 614 pack = max(sc->params.pci.mps, CACHE_LINE_SIZE); 615 MPASS(powerof2(pack)); 616 if (pack < 16) 617 pack = 16; 618 if (pack == 32) 619 pack = 64; 620 if (pack > 4096) 621 pack = 4096; 622 if (fl_pack != -1) { 623 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pack value" 624 " (%d), using %d instead.\n", fl_pack, pack); 625 } 626 } 627 m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY); 628 if (pack == 16) 629 v = V_INGPACKBOUNDARY(0); 630 else 631 v = V_INGPACKBOUNDARY(ilog2(pack) - 5); 632 633 MPASS(!is_t4(sc)); /* T4 doesn't have SGE_CONTROL2 */ 634 t4_set_reg_field(sc, A_SGE_CONTROL2, m, v); 635 } 636 637 /* 638 * adap->params.vpd.cclk must be set up before this is called. 639 */ 640 void 641 t4_tweak_chip_settings(struct adapter *sc) 642 { 643 int i; 644 uint32_t v, m; 645 int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200}; 646 int timer_max = M_TIMERVALUE0 * 1000 / sc->params.vpd.cclk; 647 int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */ 648 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 649 static int sge_flbuf_sizes[] = { 650 MCLBYTES, 651 #if MJUMPAGESIZE != MCLBYTES 652 MJUMPAGESIZE, 653 MJUMPAGESIZE - CL_METADATA_SIZE, 654 MJUMPAGESIZE - 2 * MSIZE - CL_METADATA_SIZE, 655 #endif 656 MJUM9BYTES, 657 MJUM16BYTES, 658 MCLBYTES - MSIZE - CL_METADATA_SIZE, 659 MJUM9BYTES - CL_METADATA_SIZE, 660 MJUM16BYTES - CL_METADATA_SIZE, 661 }; 662 663 KASSERT(sc->flags & MASTER_PF, 664 ("%s: trying to change chip settings when not master.", __func__)); 665 666 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE; 667 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE | 668 V_EGRSTATUSPAGESIZE(spg_len == 128); 669 t4_set_reg_field(sc, A_SGE_CONTROL, m, v); 670 671 setup_pad_and_pack_boundaries(sc); 672 673 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) | 674 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) | 675 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) | 676 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) | 677 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) | 678 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) | 679 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) | 680 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10); 681 t4_write_reg(sc, A_SGE_HOST_PAGE_SIZE, v); 682 683 KASSERT(nitems(sge_flbuf_sizes) <= SGE_FLBUF_SIZES, 684 ("%s: hw buffer size table too big", __func__)); 685 for (i = 0; i < min(nitems(sge_flbuf_sizes), SGE_FLBUF_SIZES); i++) { 686 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0 + (4 * i), 687 sge_flbuf_sizes[i]); 688 } 689 690 v = V_THRESHOLD_0(intr_pktcount[0]) | V_THRESHOLD_1(intr_pktcount[1]) | 691 V_THRESHOLD_2(intr_pktcount[2]) | V_THRESHOLD_3(intr_pktcount[3]); 692 t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD, v); 693 694 KASSERT(intr_timer[0] <= timer_max, 695 ("%s: not a single usable timer (%d, %d)", __func__, intr_timer[0], 696 timer_max)); 697 for (i = 1; i < nitems(intr_timer); i++) { 698 KASSERT(intr_timer[i] >= intr_timer[i - 1], 699 ("%s: timers not listed in increasing order (%d)", 700 __func__, i)); 701 702 while (intr_timer[i] > timer_max) { 703 if (i == nitems(intr_timer) - 1) { 704 intr_timer[i] = timer_max; 705 break; 706 } 707 intr_timer[i] += intr_timer[i - 1]; 708 intr_timer[i] /= 2; 709 } 710 } 711 712 v = V_TIMERVALUE0(us_to_core_ticks(sc, intr_timer[0])) | 713 V_TIMERVALUE1(us_to_core_ticks(sc, intr_timer[1])); 714 t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1, v); 715 v = V_TIMERVALUE2(us_to_core_ticks(sc, intr_timer[2])) | 716 V_TIMERVALUE3(us_to_core_ticks(sc, intr_timer[3])); 717 t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3, v); 718 v = V_TIMERVALUE4(us_to_core_ticks(sc, intr_timer[4])) | 719 V_TIMERVALUE5(us_to_core_ticks(sc, intr_timer[5])); 720 t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5, v); 721 722 if (chip_id(sc) >= CHELSIO_T6) { 723 m = V_TSCALE(M_TSCALE); 724 if (tscale == 1) 725 v = 0; 726 else 727 v = V_TSCALE(tscale - 2); 728 t4_set_reg_field(sc, A_SGE_ITP_CONTROL, m, v); 729 730 if (sc->debug_flags & DF_DISABLE_TCB_CACHE) { 731 m = V_RDTHRESHOLD(M_RDTHRESHOLD) | F_WRTHRTHRESHEN | 732 V_WRTHRTHRESH(M_WRTHRTHRESH); 733 t4_tp_pio_read(sc, &v, 1, A_TP_CMM_CONFIG, 1); 734 v &= ~m; 735 v |= V_RDTHRESHOLD(1) | F_WRTHRTHRESHEN | 736 V_WRTHRTHRESH(16); 737 t4_tp_pio_write(sc, &v, 1, A_TP_CMM_CONFIG, 1); 738 } 739 } 740 741 /* 4K, 16K, 64K, 256K DDP "page sizes" for TDDP */ 742 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 743 t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, v); 744 745 /* 746 * 4K, 8K, 16K, 64K DDP "page sizes" for iSCSI DDP. These have been 747 * chosen with MAXPHYS = 128K in mind. The largest DDP buffer that we 748 * may have to deal with is MAXPHYS + 1 page. 749 */ 750 v = V_HPZ0(0) | V_HPZ1(1) | V_HPZ2(2) | V_HPZ3(4); 751 t4_write_reg(sc, A_ULP_RX_ISCSI_PSZ, v); 752 753 /* We use multiple DDP page sizes both in plain-TOE and ISCSI modes. */ 754 m = v = F_TDDPTAGTCB | F_ISCSITAGTCB; 755 t4_set_reg_field(sc, A_ULP_RX_CTL, m, v); 756 757 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 758 F_RESETDDPOFFSET; 759 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 760 t4_set_reg_field(sc, A_TP_PARA_REG5, m, v); 761 } 762 763 /* 764 * SGE wants the buffer to be at least 64B and then a multiple of 16. If 765 * padding is in use, the buffer's start and end need to be aligned to the pad 766 * boundary as well. We'll just make sure that the size is a multiple of the 767 * boundary here, it is up to the buffer allocation code to make sure the start 768 * of the buffer is aligned as well. 769 */ 770 static inline int 771 hwsz_ok(struct adapter *sc, int hwsz) 772 { 773 int mask = fl_pad ? sc->params.sge.pad_boundary - 1 : 16 - 1; 774 775 return (hwsz >= 64 && (hwsz & mask) == 0); 776 } 777 778 /* 779 * XXX: driver really should be able to deal with unexpected settings. 780 */ 781 int 782 t4_read_chip_settings(struct adapter *sc) 783 { 784 struct sge *s = &sc->sge; 785 struct sge_params *sp = &sc->params.sge; 786 int i, j, n, rc = 0; 787 uint32_t m, v, r; 788 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 789 static int sw_buf_sizes[] = { /* Sorted by size */ 790 MCLBYTES, 791 #if MJUMPAGESIZE != MCLBYTES 792 MJUMPAGESIZE, 793 #endif 794 MJUM9BYTES, 795 MJUM16BYTES 796 }; 797 struct sw_zone_info *swz, *safe_swz; 798 struct hw_buf_info *hwb; 799 800 m = F_RXPKTCPLMODE; 801 v = F_RXPKTCPLMODE; 802 r = sc->params.sge.sge_control; 803 if ((r & m) != v) { 804 device_printf(sc->dev, "invalid SGE_CONTROL(0x%x)\n", r); 805 rc = EINVAL; 806 } 807 808 /* 809 * If this changes then every single use of PAGE_SHIFT in the driver 810 * needs to be carefully reviewed for PAGE_SHIFT vs sp->page_shift. 811 */ 812 if (sp->page_shift != PAGE_SHIFT) { 813 device_printf(sc->dev, "invalid SGE_HOST_PAGE_SIZE(0x%x)\n", r); 814 rc = EINVAL; 815 } 816 817 /* Filter out unusable hw buffer sizes entirely (mark with -2). */ 818 hwb = &s->hw_buf_info[0]; 819 for (i = 0; i < nitems(s->hw_buf_info); i++, hwb++) { 820 r = sc->params.sge.sge_fl_buffer_size[i]; 821 hwb->size = r; 822 hwb->zidx = hwsz_ok(sc, r) ? -1 : -2; 823 hwb->next = -1; 824 } 825 826 /* 827 * Create a sorted list in decreasing order of hw buffer sizes (and so 828 * increasing order of spare area) for each software zone. 829 * 830 * If padding is enabled then the start and end of the buffer must align 831 * to the pad boundary; if packing is enabled then they must align with 832 * the pack boundary as well. Allocations from the cluster zones are 833 * aligned to min(size, 4K), so the buffer starts at that alignment and 834 * ends at hwb->size alignment. If mbuf inlining is allowed the 835 * starting alignment will be reduced to MSIZE and the driver will 836 * exercise appropriate caution when deciding on the best buffer layout 837 * to use. 838 */ 839 n = 0; /* no usable buffer size to begin with */ 840 swz = &s->sw_zone_info[0]; 841 safe_swz = NULL; 842 for (i = 0; i < SW_ZONE_SIZES; i++, swz++) { 843 int8_t head = -1, tail = -1; 844 845 swz->size = sw_buf_sizes[i]; 846 swz->zone = m_getzone(swz->size); 847 swz->type = m_gettype(swz->size); 848 849 if (swz->size < PAGE_SIZE) { 850 MPASS(powerof2(swz->size)); 851 if (fl_pad && (swz->size % sp->pad_boundary != 0)) 852 continue; 853 } 854 855 if (swz->size == safest_rx_cluster) 856 safe_swz = swz; 857 858 hwb = &s->hw_buf_info[0]; 859 for (j = 0; j < SGE_FLBUF_SIZES; j++, hwb++) { 860 if (hwb->zidx != -1 || hwb->size > swz->size) 861 continue; 862 #ifdef INVARIANTS 863 if (fl_pad) 864 MPASS(hwb->size % sp->pad_boundary == 0); 865 #endif 866 hwb->zidx = i; 867 if (head == -1) 868 head = tail = j; 869 else if (hwb->size < s->hw_buf_info[tail].size) { 870 s->hw_buf_info[tail].next = j; 871 tail = j; 872 } else { 873 int8_t *cur; 874 struct hw_buf_info *t; 875 876 for (cur = &head; *cur != -1; cur = &t->next) { 877 t = &s->hw_buf_info[*cur]; 878 if (hwb->size == t->size) { 879 hwb->zidx = -2; 880 break; 881 } 882 if (hwb->size > t->size) { 883 hwb->next = *cur; 884 *cur = j; 885 break; 886 } 887 } 888 } 889 } 890 swz->head_hwidx = head; 891 swz->tail_hwidx = tail; 892 893 if (tail != -1) { 894 n++; 895 if (swz->size - s->hw_buf_info[tail].size >= 896 CL_METADATA_SIZE) 897 sc->flags |= BUF_PACKING_OK; 898 } 899 } 900 if (n == 0) { 901 device_printf(sc->dev, "no usable SGE FL buffer size.\n"); 902 rc = EINVAL; 903 } 904 905 s->safe_hwidx1 = -1; 906 s->safe_hwidx2 = -1; 907 if (safe_swz != NULL) { 908 s->safe_hwidx1 = safe_swz->head_hwidx; 909 for (i = safe_swz->head_hwidx; i != -1; i = hwb->next) { 910 int spare; 911 912 hwb = &s->hw_buf_info[i]; 913 #ifdef INVARIANTS 914 if (fl_pad) 915 MPASS(hwb->size % sp->pad_boundary == 0); 916 #endif 917 spare = safe_swz->size - hwb->size; 918 if (spare >= CL_METADATA_SIZE) { 919 s->safe_hwidx2 = i; 920 break; 921 } 922 } 923 } 924 925 if (sc->flags & IS_VF) 926 return (0); 927 928 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 929 r = t4_read_reg(sc, A_ULP_RX_TDDP_PSZ); 930 if (r != v) { 931 device_printf(sc->dev, "invalid ULP_RX_TDDP_PSZ(0x%x)\n", r); 932 rc = EINVAL; 933 } 934 935 m = v = F_TDDPTAGTCB; 936 r = t4_read_reg(sc, A_ULP_RX_CTL); 937 if ((r & m) != v) { 938 device_printf(sc->dev, "invalid ULP_RX_CTL(0x%x)\n", r); 939 rc = EINVAL; 940 } 941 942 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 943 F_RESETDDPOFFSET; 944 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 945 r = t4_read_reg(sc, A_TP_PARA_REG5); 946 if ((r & m) != v) { 947 device_printf(sc->dev, "invalid TP_PARA_REG5(0x%x)\n", r); 948 rc = EINVAL; 949 } 950 951 t4_init_tp_params(sc, 1); 952 953 t4_read_mtu_tbl(sc, sc->params.mtus, NULL); 954 t4_load_mtus(sc, sc->params.mtus, sc->params.a_wnd, sc->params.b_wnd); 955 956 return (rc); 957 } 958 959 int 960 t4_create_dma_tag(struct adapter *sc) 961 { 962 int rc; 963 964 rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0, 965 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE, 966 BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL, 967 NULL, &sc->dmat); 968 if (rc != 0) { 969 device_printf(sc->dev, 970 "failed to create main DMA tag: %d\n", rc); 971 } 972 973 return (rc); 974 } 975 976 void 977 t4_sge_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx, 978 struct sysctl_oid_list *children) 979 { 980 struct sge_params *sp = &sc->params.sge; 981 982 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "buffer_sizes", 983 CTLTYPE_STRING | CTLFLAG_RD, &sc->sge, 0, sysctl_bufsizes, "A", 984 "freelist buffer sizes"); 985 986 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pktshift", CTLFLAG_RD, 987 NULL, sp->fl_pktshift, "payload DMA offset in rx buffer (bytes)"); 988 989 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pad", CTLFLAG_RD, 990 NULL, sp->pad_boundary, "payload pad boundary (bytes)"); 991 992 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "spg_len", CTLFLAG_RD, 993 NULL, sp->spg_len, "status page size (bytes)"); 994 995 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_drop", CTLFLAG_RD, 996 NULL, cong_drop, "congestion drop setting"); 997 998 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pack", CTLFLAG_RD, 999 NULL, sp->pack_boundary, "payload pack boundary (bytes)"); 1000 } 1001 1002 int 1003 t4_destroy_dma_tag(struct adapter *sc) 1004 { 1005 if (sc->dmat) 1006 bus_dma_tag_destroy(sc->dmat); 1007 1008 return (0); 1009 } 1010 1011 /* 1012 * Allocate and initialize the firmware event queue, control queues, and special 1013 * purpose rx queues owned by the adapter. 1014 * 1015 * Returns errno on failure. Resources allocated up to that point may still be 1016 * allocated. Caller is responsible for cleanup in case this function fails. 1017 */ 1018 int 1019 t4_setup_adapter_queues(struct adapter *sc) 1020 { 1021 struct sysctl_oid *oid; 1022 struct sysctl_oid_list *children; 1023 int rc, i; 1024 1025 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 1026 1027 sysctl_ctx_init(&sc->ctx); 1028 sc->flags |= ADAP_SYSCTL_CTX; 1029 1030 /* 1031 * Firmware event queue 1032 */ 1033 rc = alloc_fwq(sc); 1034 if (rc != 0) 1035 return (rc); 1036 1037 /* 1038 * That's all for the VF driver. 1039 */ 1040 if (sc->flags & IS_VF) 1041 return (rc); 1042 1043 oid = device_get_sysctl_tree(sc->dev); 1044 children = SYSCTL_CHILDREN(oid); 1045 1046 /* 1047 * XXX: General purpose rx queues, one per port. 1048 */ 1049 1050 /* 1051 * Control queues, one per port. 1052 */ 1053 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "ctrlq", 1054 CTLFLAG_RD, NULL, "control queues"); 1055 for_each_port(sc, i) { 1056 struct sge_wrq *ctrlq = &sc->sge.ctrlq[i]; 1057 1058 rc = alloc_ctrlq(sc, ctrlq, i, oid); 1059 if (rc != 0) 1060 return (rc); 1061 } 1062 1063 return (rc); 1064 } 1065 1066 /* 1067 * Idempotent 1068 */ 1069 int 1070 t4_teardown_adapter_queues(struct adapter *sc) 1071 { 1072 int i; 1073 1074 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 1075 1076 /* Do this before freeing the queue */ 1077 if (sc->flags & ADAP_SYSCTL_CTX) { 1078 sysctl_ctx_free(&sc->ctx); 1079 sc->flags &= ~ADAP_SYSCTL_CTX; 1080 } 1081 1082 if (!(sc->flags & IS_VF)) { 1083 for_each_port(sc, i) 1084 free_wrq(sc, &sc->sge.ctrlq[i]); 1085 } 1086 free_fwq(sc); 1087 1088 return (0); 1089 } 1090 1091 /* Maximum payload that can be delivered with a single iq descriptor */ 1092 static inline int 1093 mtu_to_max_payload(struct adapter *sc, int mtu, const int toe) 1094 { 1095 int payload; 1096 1097 #ifdef TCP_OFFLOAD 1098 if (toe) { 1099 int rxcs = G_RXCOALESCESIZE(t4_read_reg(sc, A_TP_PARA_REG2)); 1100 1101 /* Note that COP can set rx_coalesce on/off per connection. */ 1102 payload = max(mtu, rxcs); 1103 } else { 1104 #endif 1105 /* large enough even when hw VLAN extraction is disabled */ 1106 payload = sc->params.sge.fl_pktshift + ETHER_HDR_LEN + 1107 ETHER_VLAN_ENCAP_LEN + mtu; 1108 #ifdef TCP_OFFLOAD 1109 } 1110 #endif 1111 1112 return (payload); 1113 } 1114 1115 int 1116 t4_setup_vi_queues(struct vi_info *vi) 1117 { 1118 int rc = 0, i, intr_idx, iqidx; 1119 struct sge_rxq *rxq; 1120 struct sge_txq *txq; 1121 #ifdef TCP_OFFLOAD 1122 struct sge_ofld_rxq *ofld_rxq; 1123 #endif 1124 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1125 struct sge_wrq *ofld_txq; 1126 #endif 1127 #ifdef DEV_NETMAP 1128 int saved_idx; 1129 struct sge_nm_rxq *nm_rxq; 1130 struct sge_nm_txq *nm_txq; 1131 #endif 1132 char name[16]; 1133 struct port_info *pi = vi->pi; 1134 struct adapter *sc = pi->adapter; 1135 struct ifnet *ifp = vi->ifp; 1136 struct sysctl_oid *oid = device_get_sysctl_tree(vi->dev); 1137 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 1138 int maxp, mtu = ifp->if_mtu; 1139 1140 /* Interrupt vector to start from (when using multiple vectors) */ 1141 intr_idx = vi->first_intr; 1142 1143 #ifdef DEV_NETMAP 1144 saved_idx = intr_idx; 1145 if (ifp->if_capabilities & IFCAP_NETMAP) { 1146 1147 /* netmap is supported with direct interrupts only. */ 1148 MPASS(!forwarding_intr_to_fwq(sc)); 1149 1150 /* 1151 * We don't have buffers to back the netmap rx queues 1152 * right now so we create the queues in a way that 1153 * doesn't set off any congestion signal in the chip. 1154 */ 1155 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "nm_rxq", 1156 CTLFLAG_RD, NULL, "rx queues"); 1157 for_each_nm_rxq(vi, i, nm_rxq) { 1158 rc = alloc_nm_rxq(vi, nm_rxq, intr_idx, i, oid); 1159 if (rc != 0) 1160 goto done; 1161 intr_idx++; 1162 } 1163 1164 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "nm_txq", 1165 CTLFLAG_RD, NULL, "tx queues"); 1166 for_each_nm_txq(vi, i, nm_txq) { 1167 iqidx = vi->first_nm_rxq + (i % vi->nnmrxq); 1168 rc = alloc_nm_txq(vi, nm_txq, iqidx, i, oid); 1169 if (rc != 0) 1170 goto done; 1171 } 1172 } 1173 1174 /* Normal rx queues and netmap rx queues share the same interrupts. */ 1175 intr_idx = saved_idx; 1176 #endif 1177 1178 /* 1179 * Allocate rx queues first because a default iqid is required when 1180 * creating a tx queue. 1181 */ 1182 maxp = mtu_to_max_payload(sc, mtu, 0); 1183 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "rxq", 1184 CTLFLAG_RD, NULL, "rx queues"); 1185 for_each_rxq(vi, i, rxq) { 1186 1187 init_iq(&rxq->iq, sc, vi->tmr_idx, vi->pktc_idx, vi->qsize_rxq); 1188 1189 snprintf(name, sizeof(name), "%s rxq%d-fl", 1190 device_get_nameunit(vi->dev), i); 1191 init_fl(sc, &rxq->fl, vi->qsize_rxq / 8, maxp, name); 1192 1193 rc = alloc_rxq(vi, rxq, 1194 forwarding_intr_to_fwq(sc) ? -1 : intr_idx, i, oid); 1195 if (rc != 0) 1196 goto done; 1197 intr_idx++; 1198 } 1199 #ifdef DEV_NETMAP 1200 if (ifp->if_capabilities & IFCAP_NETMAP) 1201 intr_idx = saved_idx + max(vi->nrxq, vi->nnmrxq); 1202 #endif 1203 #ifdef TCP_OFFLOAD 1204 maxp = mtu_to_max_payload(sc, mtu, 1); 1205 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_rxq", 1206 CTLFLAG_RD, NULL, "rx queues for offloaded TCP connections"); 1207 for_each_ofld_rxq(vi, i, ofld_rxq) { 1208 1209 init_iq(&ofld_rxq->iq, sc, vi->ofld_tmr_idx, vi->ofld_pktc_idx, 1210 vi->qsize_rxq); 1211 1212 snprintf(name, sizeof(name), "%s ofld_rxq%d-fl", 1213 device_get_nameunit(vi->dev), i); 1214 init_fl(sc, &ofld_rxq->fl, vi->qsize_rxq / 8, maxp, name); 1215 1216 rc = alloc_ofld_rxq(vi, ofld_rxq, 1217 forwarding_intr_to_fwq(sc) ? -1 : intr_idx, i, oid); 1218 if (rc != 0) 1219 goto done; 1220 intr_idx++; 1221 } 1222 #endif 1223 1224 /* 1225 * Now the tx queues. 1226 */ 1227 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "txq", CTLFLAG_RD, 1228 NULL, "tx queues"); 1229 for_each_txq(vi, i, txq) { 1230 iqidx = vi->first_rxq + (i % vi->nrxq); 1231 snprintf(name, sizeof(name), "%s txq%d", 1232 device_get_nameunit(vi->dev), i); 1233 init_eq(sc, &txq->eq, EQ_ETH, vi->qsize_txq, pi->tx_chan, 1234 sc->sge.rxq[iqidx].iq.cntxt_id, name); 1235 1236 rc = alloc_txq(vi, txq, i, oid); 1237 if (rc != 0) 1238 goto done; 1239 } 1240 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1241 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_txq", 1242 CTLFLAG_RD, NULL, "tx queues for TOE/ETHOFLD"); 1243 for_each_ofld_txq(vi, i, ofld_txq) { 1244 struct sysctl_oid *oid2; 1245 1246 snprintf(name, sizeof(name), "%s ofld_txq%d", 1247 device_get_nameunit(vi->dev), i); 1248 if (vi->nofldrxq > 0) { 1249 iqidx = vi->first_ofld_rxq + (i % vi->nofldrxq); 1250 init_eq(sc, &ofld_txq->eq, EQ_OFLD, vi->qsize_txq, 1251 pi->tx_chan, sc->sge.ofld_rxq[iqidx].iq.cntxt_id, 1252 name); 1253 } else { 1254 iqidx = vi->first_rxq + (i % vi->nrxq); 1255 init_eq(sc, &ofld_txq->eq, EQ_OFLD, vi->qsize_txq, 1256 pi->tx_chan, sc->sge.rxq[iqidx].iq.cntxt_id, name); 1257 } 1258 1259 snprintf(name, sizeof(name), "%d", i); 1260 oid2 = SYSCTL_ADD_NODE(&vi->ctx, SYSCTL_CHILDREN(oid), OID_AUTO, 1261 name, CTLFLAG_RD, NULL, "offload tx queue"); 1262 1263 rc = alloc_wrq(sc, vi, ofld_txq, oid2); 1264 if (rc != 0) 1265 goto done; 1266 } 1267 #endif 1268 done: 1269 if (rc) 1270 t4_teardown_vi_queues(vi); 1271 1272 return (rc); 1273 } 1274 1275 /* 1276 * Idempotent 1277 */ 1278 int 1279 t4_teardown_vi_queues(struct vi_info *vi) 1280 { 1281 int i; 1282 struct sge_rxq *rxq; 1283 struct sge_txq *txq; 1284 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1285 struct port_info *pi = vi->pi; 1286 struct adapter *sc = pi->adapter; 1287 struct sge_wrq *ofld_txq; 1288 #endif 1289 #ifdef TCP_OFFLOAD 1290 struct sge_ofld_rxq *ofld_rxq; 1291 #endif 1292 #ifdef DEV_NETMAP 1293 struct sge_nm_rxq *nm_rxq; 1294 struct sge_nm_txq *nm_txq; 1295 #endif 1296 1297 /* Do this before freeing the queues */ 1298 if (vi->flags & VI_SYSCTL_CTX) { 1299 sysctl_ctx_free(&vi->ctx); 1300 vi->flags &= ~VI_SYSCTL_CTX; 1301 } 1302 1303 #ifdef DEV_NETMAP 1304 if (vi->ifp->if_capabilities & IFCAP_NETMAP) { 1305 for_each_nm_txq(vi, i, nm_txq) { 1306 free_nm_txq(vi, nm_txq); 1307 } 1308 1309 for_each_nm_rxq(vi, i, nm_rxq) { 1310 free_nm_rxq(vi, nm_rxq); 1311 } 1312 } 1313 #endif 1314 1315 /* 1316 * Take down all the tx queues first, as they reference the rx queues 1317 * (for egress updates, etc.). 1318 */ 1319 1320 for_each_txq(vi, i, txq) { 1321 free_txq(vi, txq); 1322 } 1323 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1324 for_each_ofld_txq(vi, i, ofld_txq) { 1325 free_wrq(sc, ofld_txq); 1326 } 1327 #endif 1328 1329 /* 1330 * Then take down the rx queues. 1331 */ 1332 1333 for_each_rxq(vi, i, rxq) { 1334 free_rxq(vi, rxq); 1335 } 1336 #ifdef TCP_OFFLOAD 1337 for_each_ofld_rxq(vi, i, ofld_rxq) { 1338 free_ofld_rxq(vi, ofld_rxq); 1339 } 1340 #endif 1341 1342 return (0); 1343 } 1344 1345 /* 1346 * Interrupt handler when the driver is using only 1 interrupt. This is a very 1347 * unusual scenario. 1348 * 1349 * a) Deals with errors, if any. 1350 * b) Services firmware event queue, which is taking interrupts for all other 1351 * queues. 1352 */ 1353 void 1354 t4_intr_all(void *arg) 1355 { 1356 struct adapter *sc = arg; 1357 struct sge_iq *fwq = &sc->sge.fwq; 1358 1359 MPASS(sc->intr_count == 1); 1360 1361 t4_intr_err(arg); 1362 t4_intr_evt(fwq); 1363 } 1364 1365 /* 1366 * Interrupt handler for errors (installed directly when multiple interrupts are 1367 * being used, or called by t4_intr_all). 1368 */ 1369 void 1370 t4_intr_err(void *arg) 1371 { 1372 struct adapter *sc = arg; 1373 1374 t4_write_reg(sc, MYPF_REG(A_PCIE_PF_CLI), 0); 1375 t4_slow_intr_handler(sc); 1376 } 1377 1378 /* 1379 * Interrupt handler for iq-only queues. The firmware event queue is the only 1380 * such queue right now. 1381 */ 1382 void 1383 t4_intr_evt(void *arg) 1384 { 1385 struct sge_iq *iq = arg; 1386 1387 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 1388 service_iq(iq, 0); 1389 (void) atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 1390 } 1391 } 1392 1393 /* 1394 * Interrupt handler for iq+fl queues. 1395 */ 1396 void 1397 t4_intr(void *arg) 1398 { 1399 struct sge_iq *iq = arg; 1400 1401 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 1402 service_iq_fl(iq, 0); 1403 (void) atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 1404 } 1405 } 1406 1407 #ifdef DEV_NETMAP 1408 /* 1409 * Interrupt handler for netmap rx queues. 1410 */ 1411 void 1412 t4_nm_intr(void *arg) 1413 { 1414 struct sge_nm_rxq *nm_rxq = arg; 1415 1416 if (atomic_cmpset_int(&nm_rxq->nm_state, NM_ON, NM_BUSY)) { 1417 service_nm_rxq(nm_rxq); 1418 (void) atomic_cmpset_int(&nm_rxq->nm_state, NM_BUSY, NM_ON); 1419 } 1420 } 1421 1422 /* 1423 * Interrupt handler for vectors shared between NIC and netmap rx queues. 1424 */ 1425 void 1426 t4_vi_intr(void *arg) 1427 { 1428 struct irq *irq = arg; 1429 1430 MPASS(irq->nm_rxq != NULL); 1431 t4_nm_intr(irq->nm_rxq); 1432 1433 MPASS(irq->rxq != NULL); 1434 t4_intr(irq->rxq); 1435 } 1436 #endif 1437 1438 /* 1439 * Deals with interrupts on an iq-only (no freelist) queue. 1440 */ 1441 static int 1442 service_iq(struct sge_iq *iq, int budget) 1443 { 1444 struct sge_iq *q; 1445 struct adapter *sc = iq->adapter; 1446 struct iq_desc *d = &iq->desc[iq->cidx]; 1447 int ndescs = 0, limit; 1448 int rsp_type; 1449 uint32_t lq; 1450 STAILQ_HEAD(, sge_iq) iql = STAILQ_HEAD_INITIALIZER(iql); 1451 1452 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq)); 1453 KASSERT((iq->flags & IQ_HAS_FL) == 0, 1454 ("%s: called for iq %p with fl (iq->flags 0x%x)", __func__, iq, 1455 iq->flags)); 1456 MPASS((iq->flags & IQ_ADJ_CREDIT) == 0); 1457 MPASS((iq->flags & IQ_LRO_ENABLED) == 0); 1458 1459 limit = budget ? budget : iq->qsize / 16; 1460 1461 /* 1462 * We always come back and check the descriptor ring for new indirect 1463 * interrupts and other responses after running a single handler. 1464 */ 1465 for (;;) { 1466 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) { 1467 1468 rmb(); 1469 1470 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen); 1471 lq = be32toh(d->rsp.pldbuflen_qid); 1472 1473 switch (rsp_type) { 1474 case X_RSPD_TYPE_FLBUF: 1475 panic("%s: data for an iq (%p) with no freelist", 1476 __func__, iq); 1477 1478 /* NOTREACHED */ 1479 1480 case X_RSPD_TYPE_CPL: 1481 KASSERT(d->rss.opcode < NUM_CPL_CMDS, 1482 ("%s: bad opcode %02x.", __func__, 1483 d->rss.opcode)); 1484 t4_cpl_handler[d->rss.opcode](iq, &d->rss, NULL); 1485 break; 1486 1487 case X_RSPD_TYPE_INTR: 1488 /* 1489 * There are 1K interrupt-capable queues (qids 0 1490 * through 1023). A response type indicating a 1491 * forwarded interrupt with a qid >= 1K is an 1492 * iWARP async notification. 1493 */ 1494 if (__predict_true(lq >= 1024)) { 1495 t4_an_handler(iq, &d->rsp); 1496 break; 1497 } 1498 1499 q = sc->sge.iqmap[lq - sc->sge.iq_start - 1500 sc->sge.iq_base]; 1501 if (atomic_cmpset_int(&q->state, IQS_IDLE, 1502 IQS_BUSY)) { 1503 if (service_iq_fl(q, q->qsize / 16) == 0) { 1504 (void) atomic_cmpset_int(&q->state, 1505 IQS_BUSY, IQS_IDLE); 1506 } else { 1507 STAILQ_INSERT_TAIL(&iql, q, 1508 link); 1509 } 1510 } 1511 break; 1512 1513 default: 1514 KASSERT(0, 1515 ("%s: illegal response type %d on iq %p", 1516 __func__, rsp_type, iq)); 1517 log(LOG_ERR, 1518 "%s: illegal response type %d on iq %p", 1519 device_get_nameunit(sc->dev), rsp_type, iq); 1520 break; 1521 } 1522 1523 d++; 1524 if (__predict_false(++iq->cidx == iq->sidx)) { 1525 iq->cidx = 0; 1526 iq->gen ^= F_RSPD_GEN; 1527 d = &iq->desc[0]; 1528 } 1529 if (__predict_false(++ndescs == limit)) { 1530 t4_write_reg(sc, sc->sge_gts_reg, 1531 V_CIDXINC(ndescs) | 1532 V_INGRESSQID(iq->cntxt_id) | 1533 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); 1534 ndescs = 0; 1535 1536 if (budget) { 1537 return (EINPROGRESS); 1538 } 1539 } 1540 } 1541 1542 if (STAILQ_EMPTY(&iql)) 1543 break; 1544 1545 /* 1546 * Process the head only, and send it to the back of the list if 1547 * it's still not done. 1548 */ 1549 q = STAILQ_FIRST(&iql); 1550 STAILQ_REMOVE_HEAD(&iql, link); 1551 if (service_iq_fl(q, q->qsize / 8) == 0) 1552 (void) atomic_cmpset_int(&q->state, IQS_BUSY, IQS_IDLE); 1553 else 1554 STAILQ_INSERT_TAIL(&iql, q, link); 1555 } 1556 1557 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) | 1558 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params)); 1559 1560 return (0); 1561 } 1562 1563 static inline int 1564 sort_before_lro(struct lro_ctrl *lro) 1565 { 1566 1567 return (lro->lro_mbuf_max != 0); 1568 } 1569 1570 static inline uint64_t 1571 last_flit_to_ns(struct adapter *sc, uint64_t lf) 1572 { 1573 uint64_t n = be64toh(lf) & 0xfffffffffffffff; /* 60b, not 64b. */ 1574 1575 if (n > UINT64_MAX / 1000000) 1576 return (n / sc->params.vpd.cclk * 1000000); 1577 else 1578 return (n * 1000000 / sc->params.vpd.cclk); 1579 } 1580 1581 /* 1582 * Deals with interrupts on an iq+fl queue. 1583 */ 1584 static int 1585 service_iq_fl(struct sge_iq *iq, int budget) 1586 { 1587 struct sge_rxq *rxq = iq_to_rxq(iq); 1588 struct sge_fl *fl; 1589 struct adapter *sc = iq->adapter; 1590 struct iq_desc *d = &iq->desc[iq->cidx]; 1591 int ndescs = 0, limit; 1592 int rsp_type, refill, starved; 1593 uint32_t lq; 1594 uint16_t fl_hw_cidx; 1595 struct mbuf *m0; 1596 #if defined(INET) || defined(INET6) 1597 const struct timeval lro_timeout = {0, sc->lro_timeout}; 1598 struct lro_ctrl *lro = &rxq->lro; 1599 #endif 1600 1601 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq)); 1602 MPASS(iq->flags & IQ_HAS_FL); 1603 1604 limit = budget ? budget : iq->qsize / 16; 1605 fl = &rxq->fl; 1606 fl_hw_cidx = fl->hw_cidx; /* stable snapshot */ 1607 1608 #if defined(INET) || defined(INET6) 1609 if (iq->flags & IQ_ADJ_CREDIT) { 1610 MPASS(sort_before_lro(lro)); 1611 iq->flags &= ~IQ_ADJ_CREDIT; 1612 if ((d->rsp.u.type_gen & F_RSPD_GEN) != iq->gen) { 1613 tcp_lro_flush_all(lro); 1614 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(1) | 1615 V_INGRESSQID((u32)iq->cntxt_id) | 1616 V_SEINTARM(iq->intr_params)); 1617 return (0); 1618 } 1619 ndescs = 1; 1620 } 1621 #else 1622 MPASS((iq->flags & IQ_ADJ_CREDIT) == 0); 1623 #endif 1624 1625 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) { 1626 1627 rmb(); 1628 1629 refill = 0; 1630 m0 = NULL; 1631 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen); 1632 lq = be32toh(d->rsp.pldbuflen_qid); 1633 1634 switch (rsp_type) { 1635 case X_RSPD_TYPE_FLBUF: 1636 1637 m0 = get_fl_payload(sc, fl, lq); 1638 if (__predict_false(m0 == NULL)) 1639 goto out; 1640 refill = IDXDIFF(fl->hw_cidx, fl_hw_cidx, fl->sidx) > 2; 1641 1642 if (iq->flags & IQ_RX_TIMESTAMP) { 1643 /* 1644 * Fill up rcv_tstmp but do not set M_TSTMP. 1645 * rcv_tstmp is not in the format that the 1646 * kernel expects and we don't want to mislead 1647 * it. For now this is only for custom code 1648 * that knows how to interpret cxgbe's stamp. 1649 */ 1650 m0->m_pkthdr.rcv_tstmp = 1651 last_flit_to_ns(sc, d->rsp.u.last_flit); 1652 #ifdef notyet 1653 m0->m_flags |= M_TSTMP; 1654 #endif 1655 } 1656 1657 /* fall through */ 1658 1659 case X_RSPD_TYPE_CPL: 1660 KASSERT(d->rss.opcode < NUM_CPL_CMDS, 1661 ("%s: bad opcode %02x.", __func__, d->rss.opcode)); 1662 t4_cpl_handler[d->rss.opcode](iq, &d->rss, m0); 1663 break; 1664 1665 case X_RSPD_TYPE_INTR: 1666 1667 /* 1668 * There are 1K interrupt-capable queues (qids 0 1669 * through 1023). A response type indicating a 1670 * forwarded interrupt with a qid >= 1K is an 1671 * iWARP async notification. That is the only 1672 * acceptable indirect interrupt on this queue. 1673 */ 1674 if (__predict_false(lq < 1024)) { 1675 panic("%s: indirect interrupt on iq_fl %p " 1676 "with qid %u", __func__, iq, lq); 1677 } 1678 1679 t4_an_handler(iq, &d->rsp); 1680 break; 1681 1682 default: 1683 KASSERT(0, ("%s: illegal response type %d on iq %p", 1684 __func__, rsp_type, iq)); 1685 log(LOG_ERR, "%s: illegal response type %d on iq %p", 1686 device_get_nameunit(sc->dev), rsp_type, iq); 1687 break; 1688 } 1689 1690 d++; 1691 if (__predict_false(++iq->cidx == iq->sidx)) { 1692 iq->cidx = 0; 1693 iq->gen ^= F_RSPD_GEN; 1694 d = &iq->desc[0]; 1695 } 1696 if (__predict_false(++ndescs == limit)) { 1697 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) | 1698 V_INGRESSQID(iq->cntxt_id) | 1699 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); 1700 ndescs = 0; 1701 1702 #if defined(INET) || defined(INET6) 1703 if (iq->flags & IQ_LRO_ENABLED && 1704 !sort_before_lro(lro) && 1705 sc->lro_timeout != 0) { 1706 tcp_lro_flush_inactive(lro, &lro_timeout); 1707 } 1708 #endif 1709 if (budget) { 1710 FL_LOCK(fl); 1711 refill_fl(sc, fl, 32); 1712 FL_UNLOCK(fl); 1713 1714 return (EINPROGRESS); 1715 } 1716 } 1717 if (refill) { 1718 FL_LOCK(fl); 1719 refill_fl(sc, fl, 32); 1720 FL_UNLOCK(fl); 1721 fl_hw_cidx = fl->hw_cidx; 1722 } 1723 } 1724 out: 1725 #if defined(INET) || defined(INET6) 1726 if (iq->flags & IQ_LRO_ENABLED) { 1727 if (ndescs > 0 && lro->lro_mbuf_count > 8) { 1728 MPASS(sort_before_lro(lro)); 1729 /* hold back one credit and don't flush LRO state */ 1730 iq->flags |= IQ_ADJ_CREDIT; 1731 ndescs--; 1732 } else { 1733 tcp_lro_flush_all(lro); 1734 } 1735 } 1736 #endif 1737 1738 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) | 1739 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params)); 1740 1741 FL_LOCK(fl); 1742 starved = refill_fl(sc, fl, 64); 1743 FL_UNLOCK(fl); 1744 if (__predict_false(starved != 0)) 1745 add_fl_to_sfl(sc, fl); 1746 1747 return (0); 1748 } 1749 1750 static inline int 1751 cl_has_metadata(struct sge_fl *fl, struct cluster_layout *cll) 1752 { 1753 int rc = fl->flags & FL_BUF_PACKING || cll->region1 > 0; 1754 1755 if (rc) 1756 MPASS(cll->region3 >= CL_METADATA_SIZE); 1757 1758 return (rc); 1759 } 1760 1761 static inline struct cluster_metadata * 1762 cl_metadata(struct adapter *sc, struct sge_fl *fl, struct cluster_layout *cll, 1763 caddr_t cl) 1764 { 1765 1766 if (cl_has_metadata(fl, cll)) { 1767 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx]; 1768 1769 return ((struct cluster_metadata *)(cl + swz->size) - 1); 1770 } 1771 return (NULL); 1772 } 1773 1774 static void 1775 rxb_free(struct mbuf *m) 1776 { 1777 uma_zone_t zone = m->m_ext.ext_arg1; 1778 void *cl = m->m_ext.ext_arg2; 1779 1780 uma_zfree(zone, cl); 1781 counter_u64_add(extfree_rels, 1); 1782 } 1783 1784 /* 1785 * The mbuf returned by this function could be allocated from zone_mbuf or 1786 * constructed in spare room in the cluster. 1787 * 1788 * The mbuf carries the payload in one of these ways 1789 * a) frame inside the mbuf (mbuf from zone_mbuf) 1790 * b) m_cljset (for clusters without metadata) zone_mbuf 1791 * c) m_extaddref (cluster with metadata) inline mbuf 1792 * d) m_extaddref (cluster with metadata) zone_mbuf 1793 */ 1794 static struct mbuf * 1795 get_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset, 1796 int remaining) 1797 { 1798 struct mbuf *m; 1799 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 1800 struct cluster_layout *cll = &sd->cll; 1801 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx]; 1802 struct hw_buf_info *hwb = &sc->sge.hw_buf_info[cll->hwidx]; 1803 struct cluster_metadata *clm = cl_metadata(sc, fl, cll, sd->cl); 1804 int len, blen; 1805 caddr_t payload; 1806 1807 blen = hwb->size - fl->rx_offset; /* max possible in this buf */ 1808 len = min(remaining, blen); 1809 payload = sd->cl + cll->region1 + fl->rx_offset; 1810 if (fl->flags & FL_BUF_PACKING) { 1811 const u_int l = fr_offset + len; 1812 const u_int pad = roundup2(l, fl->buf_boundary) - l; 1813 1814 if (fl->rx_offset + len + pad < hwb->size) 1815 blen = len + pad; 1816 MPASS(fl->rx_offset + blen <= hwb->size); 1817 } else { 1818 MPASS(fl->rx_offset == 0); /* not packing */ 1819 } 1820 1821 1822 if (sc->sc_do_rxcopy && len < RX_COPY_THRESHOLD) { 1823 1824 /* 1825 * Copy payload into a freshly allocated mbuf. 1826 */ 1827 1828 m = fr_offset == 0 ? 1829 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA); 1830 if (m == NULL) 1831 return (NULL); 1832 fl->mbuf_allocated++; 1833 1834 /* copy data to mbuf */ 1835 bcopy(payload, mtod(m, caddr_t), len); 1836 1837 } else if (sd->nmbuf * MSIZE < cll->region1) { 1838 1839 /* 1840 * There's spare room in the cluster for an mbuf. Create one 1841 * and associate it with the payload that's in the cluster. 1842 */ 1843 1844 MPASS(clm != NULL); 1845 m = (struct mbuf *)(sd->cl + sd->nmbuf * MSIZE); 1846 /* No bzero required */ 1847 if (m_init(m, M_NOWAIT, MT_DATA, 1848 fr_offset == 0 ? M_PKTHDR | M_NOFREE : M_NOFREE)) 1849 return (NULL); 1850 fl->mbuf_inlined++; 1851 m_extaddref(m, payload, blen, &clm->refcount, rxb_free, 1852 swz->zone, sd->cl); 1853 if (sd->nmbuf++ == 0) 1854 counter_u64_add(extfree_refs, 1); 1855 1856 } else { 1857 1858 /* 1859 * Grab an mbuf from zone_mbuf and associate it with the 1860 * payload in the cluster. 1861 */ 1862 1863 m = fr_offset == 0 ? 1864 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA); 1865 if (m == NULL) 1866 return (NULL); 1867 fl->mbuf_allocated++; 1868 if (clm != NULL) { 1869 m_extaddref(m, payload, blen, &clm->refcount, 1870 rxb_free, swz->zone, sd->cl); 1871 if (sd->nmbuf++ == 0) 1872 counter_u64_add(extfree_refs, 1); 1873 } else { 1874 m_cljset(m, sd->cl, swz->type); 1875 sd->cl = NULL; /* consumed, not a recycle candidate */ 1876 } 1877 } 1878 if (fr_offset == 0) 1879 m->m_pkthdr.len = remaining; 1880 m->m_len = len; 1881 1882 if (fl->flags & FL_BUF_PACKING) { 1883 fl->rx_offset += blen; 1884 MPASS(fl->rx_offset <= hwb->size); 1885 if (fl->rx_offset < hwb->size) 1886 return (m); /* without advancing the cidx */ 1887 } 1888 1889 if (__predict_false(++fl->cidx % 8 == 0)) { 1890 uint16_t cidx = fl->cidx / 8; 1891 1892 if (__predict_false(cidx == fl->sidx)) 1893 fl->cidx = cidx = 0; 1894 fl->hw_cidx = cidx; 1895 } 1896 fl->rx_offset = 0; 1897 1898 return (m); 1899 } 1900 1901 static struct mbuf * 1902 get_fl_payload(struct adapter *sc, struct sge_fl *fl, uint32_t len_newbuf) 1903 { 1904 struct mbuf *m0, *m, **pnext; 1905 u_int remaining; 1906 const u_int total = G_RSPD_LEN(len_newbuf); 1907 1908 if (__predict_false(fl->flags & FL_BUF_RESUME)) { 1909 M_ASSERTPKTHDR(fl->m0); 1910 MPASS(fl->m0->m_pkthdr.len == total); 1911 MPASS(fl->remaining < total); 1912 1913 m0 = fl->m0; 1914 pnext = fl->pnext; 1915 remaining = fl->remaining; 1916 fl->flags &= ~FL_BUF_RESUME; 1917 goto get_segment; 1918 } 1919 1920 if (fl->rx_offset > 0 && len_newbuf & F_RSPD_NEWBUF) { 1921 fl->rx_offset = 0; 1922 if (__predict_false(++fl->cidx % 8 == 0)) { 1923 uint16_t cidx = fl->cidx / 8; 1924 1925 if (__predict_false(cidx == fl->sidx)) 1926 fl->cidx = cidx = 0; 1927 fl->hw_cidx = cidx; 1928 } 1929 } 1930 1931 /* 1932 * Payload starts at rx_offset in the current hw buffer. Its length is 1933 * 'len' and it may span multiple hw buffers. 1934 */ 1935 1936 m0 = get_scatter_segment(sc, fl, 0, total); 1937 if (m0 == NULL) 1938 return (NULL); 1939 remaining = total - m0->m_len; 1940 pnext = &m0->m_next; 1941 while (remaining > 0) { 1942 get_segment: 1943 MPASS(fl->rx_offset == 0); 1944 m = get_scatter_segment(sc, fl, total - remaining, remaining); 1945 if (__predict_false(m == NULL)) { 1946 fl->m0 = m0; 1947 fl->pnext = pnext; 1948 fl->remaining = remaining; 1949 fl->flags |= FL_BUF_RESUME; 1950 return (NULL); 1951 } 1952 *pnext = m; 1953 pnext = &m->m_next; 1954 remaining -= m->m_len; 1955 } 1956 *pnext = NULL; 1957 1958 M_ASSERTPKTHDR(m0); 1959 return (m0); 1960 } 1961 1962 static int 1963 t4_eth_rx(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0) 1964 { 1965 struct sge_rxq *rxq = iq_to_rxq(iq); 1966 struct ifnet *ifp = rxq->ifp; 1967 struct adapter *sc = iq->adapter; 1968 const struct cpl_rx_pkt *cpl = (const void *)(rss + 1); 1969 #if defined(INET) || defined(INET6) 1970 struct lro_ctrl *lro = &rxq->lro; 1971 #endif 1972 static const int sw_hashtype[4][2] = { 1973 {M_HASHTYPE_NONE, M_HASHTYPE_NONE}, 1974 {M_HASHTYPE_RSS_IPV4, M_HASHTYPE_RSS_IPV6}, 1975 {M_HASHTYPE_RSS_TCP_IPV4, M_HASHTYPE_RSS_TCP_IPV6}, 1976 {M_HASHTYPE_RSS_UDP_IPV4, M_HASHTYPE_RSS_UDP_IPV6}, 1977 }; 1978 1979 KASSERT(m0 != NULL, ("%s: no payload with opcode %02x", __func__, 1980 rss->opcode)); 1981 1982 m0->m_pkthdr.len -= sc->params.sge.fl_pktshift; 1983 m0->m_len -= sc->params.sge.fl_pktshift; 1984 m0->m_data += sc->params.sge.fl_pktshift; 1985 1986 m0->m_pkthdr.rcvif = ifp; 1987 M_HASHTYPE_SET(m0, sw_hashtype[rss->hash_type][rss->ipv6]); 1988 m0->m_pkthdr.flowid = be32toh(rss->hash_val); 1989 1990 if (cpl->csum_calc && !(cpl->err_vec & sc->params.tp.err_vec_mask)) { 1991 if (ifp->if_capenable & IFCAP_RXCSUM && 1992 cpl->l2info & htobe32(F_RXF_IP)) { 1993 m0->m_pkthdr.csum_flags = (CSUM_IP_CHECKED | 1994 CSUM_IP_VALID | CSUM_DATA_VALID | CSUM_PSEUDO_HDR); 1995 rxq->rxcsum++; 1996 } else if (ifp->if_capenable & IFCAP_RXCSUM_IPV6 && 1997 cpl->l2info & htobe32(F_RXF_IP6)) { 1998 m0->m_pkthdr.csum_flags = (CSUM_DATA_VALID_IPV6 | 1999 CSUM_PSEUDO_HDR); 2000 rxq->rxcsum++; 2001 } 2002 2003 if (__predict_false(cpl->ip_frag)) 2004 m0->m_pkthdr.csum_data = be16toh(cpl->csum); 2005 else 2006 m0->m_pkthdr.csum_data = 0xffff; 2007 } 2008 2009 if (cpl->vlan_ex) { 2010 m0->m_pkthdr.ether_vtag = be16toh(cpl->vlan); 2011 m0->m_flags |= M_VLANTAG; 2012 rxq->vlan_extraction++; 2013 } 2014 2015 #if defined(INET) || defined(INET6) 2016 if (iq->flags & IQ_LRO_ENABLED) { 2017 if (sort_before_lro(lro)) { 2018 tcp_lro_queue_mbuf(lro, m0); 2019 return (0); /* queued for sort, then LRO */ 2020 } 2021 if (tcp_lro_rx(lro, m0, 0) == 0) 2022 return (0); /* queued for LRO */ 2023 } 2024 #endif 2025 ifp->if_input(ifp, m0); 2026 2027 return (0); 2028 } 2029 2030 /* 2031 * Must drain the wrq or make sure that someone else will. 2032 */ 2033 static void 2034 wrq_tx_drain(void *arg, int n) 2035 { 2036 struct sge_wrq *wrq = arg; 2037 struct sge_eq *eq = &wrq->eq; 2038 2039 EQ_LOCK(eq); 2040 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 2041 drain_wrq_wr_list(wrq->adapter, wrq); 2042 EQ_UNLOCK(eq); 2043 } 2044 2045 static void 2046 drain_wrq_wr_list(struct adapter *sc, struct sge_wrq *wrq) 2047 { 2048 struct sge_eq *eq = &wrq->eq; 2049 u_int available, dbdiff; /* # of hardware descriptors */ 2050 u_int n; 2051 struct wrqe *wr; 2052 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */ 2053 2054 EQ_LOCK_ASSERT_OWNED(eq); 2055 MPASS(TAILQ_EMPTY(&wrq->incomplete_wrs)); 2056 wr = STAILQ_FIRST(&wrq->wr_list); 2057 MPASS(wr != NULL); /* Must be called with something useful to do */ 2058 MPASS(eq->pidx == eq->dbidx); 2059 dbdiff = 0; 2060 2061 do { 2062 eq->cidx = read_hw_cidx(eq); 2063 if (eq->pidx == eq->cidx) 2064 available = eq->sidx - 1; 2065 else 2066 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2067 2068 MPASS(wr->wrq == wrq); 2069 n = howmany(wr->wr_len, EQ_ESIZE); 2070 if (available < n) 2071 break; 2072 2073 dst = (void *)&eq->desc[eq->pidx]; 2074 if (__predict_true(eq->sidx - eq->pidx > n)) { 2075 /* Won't wrap, won't end exactly at the status page. */ 2076 bcopy(&wr->wr[0], dst, wr->wr_len); 2077 eq->pidx += n; 2078 } else { 2079 int first_portion = (eq->sidx - eq->pidx) * EQ_ESIZE; 2080 2081 bcopy(&wr->wr[0], dst, first_portion); 2082 if (wr->wr_len > first_portion) { 2083 bcopy(&wr->wr[first_portion], &eq->desc[0], 2084 wr->wr_len - first_portion); 2085 } 2086 eq->pidx = n - (eq->sidx - eq->pidx); 2087 } 2088 wrq->tx_wrs_copied++; 2089 2090 if (available < eq->sidx / 4 && 2091 atomic_cmpset_int(&eq->equiq, 0, 1)) { 2092 /* 2093 * XXX: This is not 100% reliable with some 2094 * types of WRs. But this is a very unusual 2095 * situation for an ofld/ctrl queue anyway. 2096 */ 2097 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ | 2098 F_FW_WR_EQUEQ); 2099 } 2100 2101 dbdiff += n; 2102 if (dbdiff >= 16) { 2103 ring_eq_db(sc, eq, dbdiff); 2104 dbdiff = 0; 2105 } 2106 2107 STAILQ_REMOVE_HEAD(&wrq->wr_list, link); 2108 free_wrqe(wr); 2109 MPASS(wrq->nwr_pending > 0); 2110 wrq->nwr_pending--; 2111 MPASS(wrq->ndesc_needed >= n); 2112 wrq->ndesc_needed -= n; 2113 } while ((wr = STAILQ_FIRST(&wrq->wr_list)) != NULL); 2114 2115 if (dbdiff) 2116 ring_eq_db(sc, eq, dbdiff); 2117 } 2118 2119 /* 2120 * Doesn't fail. Holds on to work requests it can't send right away. 2121 */ 2122 void 2123 t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, struct wrqe *wr) 2124 { 2125 #ifdef INVARIANTS 2126 struct sge_eq *eq = &wrq->eq; 2127 #endif 2128 2129 EQ_LOCK_ASSERT_OWNED(eq); 2130 MPASS(wr != NULL); 2131 MPASS(wr->wr_len > 0 && wr->wr_len <= SGE_MAX_WR_LEN); 2132 MPASS((wr->wr_len & 0x7) == 0); 2133 2134 STAILQ_INSERT_TAIL(&wrq->wr_list, wr, link); 2135 wrq->nwr_pending++; 2136 wrq->ndesc_needed += howmany(wr->wr_len, EQ_ESIZE); 2137 2138 if (!TAILQ_EMPTY(&wrq->incomplete_wrs)) 2139 return; /* commit_wrq_wr will drain wr_list as well. */ 2140 2141 drain_wrq_wr_list(sc, wrq); 2142 2143 /* Doorbell must have caught up to the pidx. */ 2144 MPASS(eq->pidx == eq->dbidx); 2145 } 2146 2147 void 2148 t4_update_fl_bufsize(struct ifnet *ifp) 2149 { 2150 struct vi_info *vi = ifp->if_softc; 2151 struct adapter *sc = vi->pi->adapter; 2152 struct sge_rxq *rxq; 2153 #ifdef TCP_OFFLOAD 2154 struct sge_ofld_rxq *ofld_rxq; 2155 #endif 2156 struct sge_fl *fl; 2157 int i, maxp, mtu = ifp->if_mtu; 2158 2159 maxp = mtu_to_max_payload(sc, mtu, 0); 2160 for_each_rxq(vi, i, rxq) { 2161 fl = &rxq->fl; 2162 2163 FL_LOCK(fl); 2164 find_best_refill_source(sc, fl, maxp); 2165 FL_UNLOCK(fl); 2166 } 2167 #ifdef TCP_OFFLOAD 2168 maxp = mtu_to_max_payload(sc, mtu, 1); 2169 for_each_ofld_rxq(vi, i, ofld_rxq) { 2170 fl = &ofld_rxq->fl; 2171 2172 FL_LOCK(fl); 2173 find_best_refill_source(sc, fl, maxp); 2174 FL_UNLOCK(fl); 2175 } 2176 #endif 2177 } 2178 2179 static inline int 2180 mbuf_nsegs(struct mbuf *m) 2181 { 2182 2183 M_ASSERTPKTHDR(m); 2184 KASSERT(m->m_pkthdr.l5hlen > 0, 2185 ("%s: mbuf %p missing information on # of segments.", __func__, m)); 2186 2187 return (m->m_pkthdr.l5hlen); 2188 } 2189 2190 static inline void 2191 set_mbuf_nsegs(struct mbuf *m, uint8_t nsegs) 2192 { 2193 2194 M_ASSERTPKTHDR(m); 2195 m->m_pkthdr.l5hlen = nsegs; 2196 } 2197 2198 static inline int 2199 mbuf_len16(struct mbuf *m) 2200 { 2201 int n; 2202 2203 M_ASSERTPKTHDR(m); 2204 n = m->m_pkthdr.PH_loc.eight[0]; 2205 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16); 2206 2207 return (n); 2208 } 2209 2210 static inline void 2211 set_mbuf_len16(struct mbuf *m, uint8_t len16) 2212 { 2213 2214 M_ASSERTPKTHDR(m); 2215 m->m_pkthdr.PH_loc.eight[0] = len16; 2216 } 2217 2218 #ifdef RATELIMIT 2219 static inline int 2220 mbuf_eo_nsegs(struct mbuf *m) 2221 { 2222 2223 M_ASSERTPKTHDR(m); 2224 return (m->m_pkthdr.PH_loc.eight[1]); 2225 } 2226 2227 static inline void 2228 set_mbuf_eo_nsegs(struct mbuf *m, uint8_t nsegs) 2229 { 2230 2231 M_ASSERTPKTHDR(m); 2232 m->m_pkthdr.PH_loc.eight[1] = nsegs; 2233 } 2234 2235 static inline int 2236 mbuf_eo_len16(struct mbuf *m) 2237 { 2238 int n; 2239 2240 M_ASSERTPKTHDR(m); 2241 n = m->m_pkthdr.PH_loc.eight[2]; 2242 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16); 2243 2244 return (n); 2245 } 2246 2247 static inline void 2248 set_mbuf_eo_len16(struct mbuf *m, uint8_t len16) 2249 { 2250 2251 M_ASSERTPKTHDR(m); 2252 m->m_pkthdr.PH_loc.eight[2] = len16; 2253 } 2254 2255 static inline int 2256 mbuf_eo_tsclk_tsoff(struct mbuf *m) 2257 { 2258 2259 M_ASSERTPKTHDR(m); 2260 return (m->m_pkthdr.PH_loc.eight[3]); 2261 } 2262 2263 static inline void 2264 set_mbuf_eo_tsclk_tsoff(struct mbuf *m, uint8_t tsclk_tsoff) 2265 { 2266 2267 M_ASSERTPKTHDR(m); 2268 m->m_pkthdr.PH_loc.eight[3] = tsclk_tsoff; 2269 } 2270 2271 static inline int 2272 needs_eo(struct mbuf *m) 2273 { 2274 2275 return (m->m_pkthdr.snd_tag != NULL); 2276 } 2277 #endif 2278 2279 static inline int 2280 needs_tso(struct mbuf *m) 2281 { 2282 2283 M_ASSERTPKTHDR(m); 2284 2285 return (m->m_pkthdr.csum_flags & CSUM_TSO); 2286 } 2287 2288 static inline int 2289 needs_l3_csum(struct mbuf *m) 2290 { 2291 2292 M_ASSERTPKTHDR(m); 2293 2294 return (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TSO)); 2295 } 2296 2297 static inline int 2298 needs_l4_csum(struct mbuf *m) 2299 { 2300 2301 M_ASSERTPKTHDR(m); 2302 2303 return (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_UDP_IPV6 | 2304 CSUM_TCP_IPV6 | CSUM_TSO)); 2305 } 2306 2307 static inline int 2308 needs_tcp_csum(struct mbuf *m) 2309 { 2310 2311 M_ASSERTPKTHDR(m); 2312 return (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_TCP_IPV6 | CSUM_TSO)); 2313 } 2314 2315 #ifdef RATELIMIT 2316 static inline int 2317 needs_udp_csum(struct mbuf *m) 2318 { 2319 2320 M_ASSERTPKTHDR(m); 2321 return (m->m_pkthdr.csum_flags & (CSUM_UDP | CSUM_UDP_IPV6)); 2322 } 2323 #endif 2324 2325 static inline int 2326 needs_vlan_insertion(struct mbuf *m) 2327 { 2328 2329 M_ASSERTPKTHDR(m); 2330 2331 return (m->m_flags & M_VLANTAG); 2332 } 2333 2334 static void * 2335 m_advance(struct mbuf **pm, int *poffset, int len) 2336 { 2337 struct mbuf *m = *pm; 2338 int offset = *poffset; 2339 uintptr_t p = 0; 2340 2341 MPASS(len > 0); 2342 2343 for (;;) { 2344 if (offset + len < m->m_len) { 2345 offset += len; 2346 p = mtod(m, uintptr_t) + offset; 2347 break; 2348 } 2349 len -= m->m_len - offset; 2350 m = m->m_next; 2351 offset = 0; 2352 MPASS(m != NULL); 2353 } 2354 *poffset = offset; 2355 *pm = m; 2356 return ((void *)p); 2357 } 2358 2359 /* 2360 * Can deal with empty mbufs in the chain that have m_len = 0, but the chain 2361 * must have at least one mbuf that's not empty. It is possible for this 2362 * routine to return 0 if skip accounts for all the contents of the mbuf chain. 2363 */ 2364 static inline int 2365 count_mbuf_nsegs(struct mbuf *m, int skip) 2366 { 2367 vm_paddr_t lastb, next; 2368 vm_offset_t va; 2369 int len, nsegs; 2370 2371 M_ASSERTPKTHDR(m); 2372 MPASS(m->m_pkthdr.len > 0); 2373 MPASS(m->m_pkthdr.len >= skip); 2374 2375 nsegs = 0; 2376 lastb = 0; 2377 for (; m; m = m->m_next) { 2378 2379 len = m->m_len; 2380 if (__predict_false(len == 0)) 2381 continue; 2382 if (skip >= len) { 2383 skip -= len; 2384 continue; 2385 } 2386 va = mtod(m, vm_offset_t) + skip; 2387 len -= skip; 2388 skip = 0; 2389 next = pmap_kextract(va); 2390 nsegs += sglist_count((void *)(uintptr_t)va, len); 2391 if (lastb + 1 == next) 2392 nsegs--; 2393 lastb = pmap_kextract(va + len - 1); 2394 } 2395 2396 return (nsegs); 2397 } 2398 2399 /* 2400 * Analyze the mbuf to determine its tx needs. The mbuf passed in may change: 2401 * a) caller can assume it's been freed if this function returns with an error. 2402 * b) it may get defragged up if the gather list is too long for the hardware. 2403 */ 2404 int 2405 parse_pkt(struct adapter *sc, struct mbuf **mp) 2406 { 2407 struct mbuf *m0 = *mp, *m; 2408 int rc, nsegs, defragged = 0, offset; 2409 struct ether_header *eh; 2410 void *l3hdr; 2411 #if defined(INET) || defined(INET6) 2412 struct tcphdr *tcp; 2413 #endif 2414 uint16_t eh_type; 2415 2416 M_ASSERTPKTHDR(m0); 2417 if (__predict_false(m0->m_pkthdr.len < ETHER_HDR_LEN)) { 2418 rc = EINVAL; 2419 fail: 2420 m_freem(m0); 2421 *mp = NULL; 2422 return (rc); 2423 } 2424 restart: 2425 /* 2426 * First count the number of gather list segments in the payload. 2427 * Defrag the mbuf if nsegs exceeds the hardware limit. 2428 */ 2429 M_ASSERTPKTHDR(m0); 2430 MPASS(m0->m_pkthdr.len > 0); 2431 nsegs = count_mbuf_nsegs(m0, 0); 2432 if (nsegs > (needs_tso(m0) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS)) { 2433 if (defragged++ > 0 || (m = m_defrag(m0, M_NOWAIT)) == NULL) { 2434 rc = EFBIG; 2435 goto fail; 2436 } 2437 *mp = m0 = m; /* update caller's copy after defrag */ 2438 goto restart; 2439 } 2440 2441 if (__predict_false(nsegs > 2 && m0->m_pkthdr.len <= MHLEN)) { 2442 m0 = m_pullup(m0, m0->m_pkthdr.len); 2443 if (m0 == NULL) { 2444 /* Should have left well enough alone. */ 2445 rc = EFBIG; 2446 goto fail; 2447 } 2448 *mp = m0; /* update caller's copy after pullup */ 2449 goto restart; 2450 } 2451 set_mbuf_nsegs(m0, nsegs); 2452 if (sc->flags & IS_VF) 2453 set_mbuf_len16(m0, txpkt_vm_len16(nsegs, needs_tso(m0))); 2454 else 2455 set_mbuf_len16(m0, txpkt_len16(nsegs, needs_tso(m0))); 2456 2457 #ifdef RATELIMIT 2458 /* 2459 * Ethofld is limited to TCP and UDP for now, and only when L4 hw 2460 * checksumming is enabled. needs_l4_csum happens to check for all the 2461 * right things. 2462 */ 2463 if (__predict_false(needs_eo(m0) && !needs_l4_csum(m0))) 2464 m0->m_pkthdr.snd_tag = NULL; 2465 #endif 2466 2467 if (!needs_tso(m0) && 2468 #ifdef RATELIMIT 2469 !needs_eo(m0) && 2470 #endif 2471 !(sc->flags & IS_VF && (needs_l3_csum(m0) || needs_l4_csum(m0)))) 2472 return (0); 2473 2474 m = m0; 2475 eh = mtod(m, struct ether_header *); 2476 eh_type = ntohs(eh->ether_type); 2477 if (eh_type == ETHERTYPE_VLAN) { 2478 struct ether_vlan_header *evh = (void *)eh; 2479 2480 eh_type = ntohs(evh->evl_proto); 2481 m0->m_pkthdr.l2hlen = sizeof(*evh); 2482 } else 2483 m0->m_pkthdr.l2hlen = sizeof(*eh); 2484 2485 offset = 0; 2486 l3hdr = m_advance(&m, &offset, m0->m_pkthdr.l2hlen); 2487 2488 switch (eh_type) { 2489 #ifdef INET6 2490 case ETHERTYPE_IPV6: 2491 { 2492 struct ip6_hdr *ip6 = l3hdr; 2493 2494 MPASS(!needs_tso(m0) || ip6->ip6_nxt == IPPROTO_TCP); 2495 2496 m0->m_pkthdr.l3hlen = sizeof(*ip6); 2497 break; 2498 } 2499 #endif 2500 #ifdef INET 2501 case ETHERTYPE_IP: 2502 { 2503 struct ip *ip = l3hdr; 2504 2505 m0->m_pkthdr.l3hlen = ip->ip_hl * 4; 2506 break; 2507 } 2508 #endif 2509 default: 2510 panic("%s: ethertype 0x%04x unknown. if_cxgbe must be compiled" 2511 " with the same INET/INET6 options as the kernel.", 2512 __func__, eh_type); 2513 } 2514 2515 #if defined(INET) || defined(INET6) 2516 if (needs_tcp_csum(m0)) { 2517 tcp = m_advance(&m, &offset, m0->m_pkthdr.l3hlen); 2518 m0->m_pkthdr.l4hlen = tcp->th_off * 4; 2519 #ifdef RATELIMIT 2520 if (tsclk >= 0 && *(uint32_t *)(tcp + 1) == ntohl(0x0101080a)) { 2521 set_mbuf_eo_tsclk_tsoff(m0, 2522 V_FW_ETH_TX_EO_WR_TSCLK(tsclk) | 2523 V_FW_ETH_TX_EO_WR_TSOFF(sizeof(*tcp) / 2 + 1)); 2524 } else 2525 set_mbuf_eo_tsclk_tsoff(m0, 0); 2526 } else if (needs_udp_csum(m)) { 2527 m0->m_pkthdr.l4hlen = sizeof(struct udphdr); 2528 #endif 2529 } 2530 #ifdef RATELIMIT 2531 if (needs_eo(m0)) { 2532 u_int immhdrs; 2533 2534 /* EO WRs have the headers in the WR and not the GL. */ 2535 immhdrs = m0->m_pkthdr.l2hlen + m0->m_pkthdr.l3hlen + 2536 m0->m_pkthdr.l4hlen; 2537 nsegs = count_mbuf_nsegs(m0, immhdrs); 2538 set_mbuf_eo_nsegs(m0, nsegs); 2539 set_mbuf_eo_len16(m0, 2540 txpkt_eo_len16(nsegs, immhdrs, needs_tso(m0))); 2541 } 2542 #endif 2543 #endif 2544 MPASS(m0 == *mp); 2545 return (0); 2546 } 2547 2548 void * 2549 start_wrq_wr(struct sge_wrq *wrq, int len16, struct wrq_cookie *cookie) 2550 { 2551 struct sge_eq *eq = &wrq->eq; 2552 struct adapter *sc = wrq->adapter; 2553 int ndesc, available; 2554 struct wrqe *wr; 2555 void *w; 2556 2557 MPASS(len16 > 0); 2558 ndesc = howmany(len16, EQ_ESIZE / 16); 2559 MPASS(ndesc > 0 && ndesc <= SGE_MAX_WR_NDESC); 2560 2561 EQ_LOCK(eq); 2562 2563 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 2564 drain_wrq_wr_list(sc, wrq); 2565 2566 if (!STAILQ_EMPTY(&wrq->wr_list)) { 2567 slowpath: 2568 EQ_UNLOCK(eq); 2569 wr = alloc_wrqe(len16 * 16, wrq); 2570 if (__predict_false(wr == NULL)) 2571 return (NULL); 2572 cookie->pidx = -1; 2573 cookie->ndesc = ndesc; 2574 return (&wr->wr); 2575 } 2576 2577 eq->cidx = read_hw_cidx(eq); 2578 if (eq->pidx == eq->cidx) 2579 available = eq->sidx - 1; 2580 else 2581 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2582 if (available < ndesc) 2583 goto slowpath; 2584 2585 cookie->pidx = eq->pidx; 2586 cookie->ndesc = ndesc; 2587 TAILQ_INSERT_TAIL(&wrq->incomplete_wrs, cookie, link); 2588 2589 w = &eq->desc[eq->pidx]; 2590 IDXINCR(eq->pidx, ndesc, eq->sidx); 2591 if (__predict_false(cookie->pidx + ndesc > eq->sidx)) { 2592 w = &wrq->ss[0]; 2593 wrq->ss_pidx = cookie->pidx; 2594 wrq->ss_len = len16 * 16; 2595 } 2596 2597 EQ_UNLOCK(eq); 2598 2599 return (w); 2600 } 2601 2602 void 2603 commit_wrq_wr(struct sge_wrq *wrq, void *w, struct wrq_cookie *cookie) 2604 { 2605 struct sge_eq *eq = &wrq->eq; 2606 struct adapter *sc = wrq->adapter; 2607 int ndesc, pidx; 2608 struct wrq_cookie *prev, *next; 2609 2610 if (cookie->pidx == -1) { 2611 struct wrqe *wr = __containerof(w, struct wrqe, wr); 2612 2613 t4_wrq_tx(sc, wr); 2614 return; 2615 } 2616 2617 if (__predict_false(w == &wrq->ss[0])) { 2618 int n = (eq->sidx - wrq->ss_pidx) * EQ_ESIZE; 2619 2620 MPASS(wrq->ss_len > n); /* WR had better wrap around. */ 2621 bcopy(&wrq->ss[0], &eq->desc[wrq->ss_pidx], n); 2622 bcopy(&wrq->ss[n], &eq->desc[0], wrq->ss_len - n); 2623 wrq->tx_wrs_ss++; 2624 } else 2625 wrq->tx_wrs_direct++; 2626 2627 EQ_LOCK(eq); 2628 ndesc = cookie->ndesc; /* Can be more than SGE_MAX_WR_NDESC here. */ 2629 pidx = cookie->pidx; 2630 MPASS(pidx >= 0 && pidx < eq->sidx); 2631 prev = TAILQ_PREV(cookie, wrq_incomplete_wrs, link); 2632 next = TAILQ_NEXT(cookie, link); 2633 if (prev == NULL) { 2634 MPASS(pidx == eq->dbidx); 2635 if (next == NULL || ndesc >= 16) { 2636 int available; 2637 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */ 2638 2639 /* 2640 * Note that the WR via which we'll request tx updates 2641 * is at pidx and not eq->pidx, which has moved on 2642 * already. 2643 */ 2644 dst = (void *)&eq->desc[pidx]; 2645 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2646 if (available < eq->sidx / 4 && 2647 atomic_cmpset_int(&eq->equiq, 0, 1)) { 2648 /* 2649 * XXX: This is not 100% reliable with some 2650 * types of WRs. But this is a very unusual 2651 * situation for an ofld/ctrl queue anyway. 2652 */ 2653 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ | 2654 F_FW_WR_EQUEQ); 2655 } 2656 2657 ring_eq_db(wrq->adapter, eq, ndesc); 2658 } else { 2659 MPASS(IDXDIFF(next->pidx, pidx, eq->sidx) == ndesc); 2660 next->pidx = pidx; 2661 next->ndesc += ndesc; 2662 } 2663 } else { 2664 MPASS(IDXDIFF(pidx, prev->pidx, eq->sidx) == prev->ndesc); 2665 prev->ndesc += ndesc; 2666 } 2667 TAILQ_REMOVE(&wrq->incomplete_wrs, cookie, link); 2668 2669 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 2670 drain_wrq_wr_list(sc, wrq); 2671 2672 #ifdef INVARIANTS 2673 if (TAILQ_EMPTY(&wrq->incomplete_wrs)) { 2674 /* Doorbell must have caught up to the pidx. */ 2675 MPASS(wrq->eq.pidx == wrq->eq.dbidx); 2676 } 2677 #endif 2678 EQ_UNLOCK(eq); 2679 } 2680 2681 static u_int 2682 can_resume_eth_tx(struct mp_ring *r) 2683 { 2684 struct sge_eq *eq = r->cookie; 2685 2686 return (total_available_tx_desc(eq) > eq->sidx / 8); 2687 } 2688 2689 static inline int 2690 cannot_use_txpkts(struct mbuf *m) 2691 { 2692 /* maybe put a GL limit too, to avoid silliness? */ 2693 2694 return (needs_tso(m)); 2695 } 2696 2697 static inline int 2698 discard_tx(struct sge_eq *eq) 2699 { 2700 2701 return ((eq->flags & (EQ_ENABLED | EQ_QFLUSH)) != EQ_ENABLED); 2702 } 2703 2704 /* 2705 * r->items[cidx] to r->items[pidx], with a wraparound at r->size, are ready to 2706 * be consumed. Return the actual number consumed. 0 indicates a stall. 2707 */ 2708 static u_int 2709 eth_tx(struct mp_ring *r, u_int cidx, u_int pidx) 2710 { 2711 struct sge_txq *txq = r->cookie; 2712 struct sge_eq *eq = &txq->eq; 2713 struct ifnet *ifp = txq->ifp; 2714 struct vi_info *vi = ifp->if_softc; 2715 struct port_info *pi = vi->pi; 2716 struct adapter *sc = pi->adapter; 2717 u_int total, remaining; /* # of packets */ 2718 u_int available, dbdiff; /* # of hardware descriptors */ 2719 u_int n, next_cidx; 2720 struct mbuf *m0, *tail; 2721 struct txpkts txp; 2722 struct fw_eth_tx_pkts_wr *wr; /* any fw WR struct will do */ 2723 2724 remaining = IDXDIFF(pidx, cidx, r->size); 2725 MPASS(remaining > 0); /* Must not be called without work to do. */ 2726 total = 0; 2727 2728 TXQ_LOCK(txq); 2729 if (__predict_false(discard_tx(eq))) { 2730 while (cidx != pidx) { 2731 m0 = r->items[cidx]; 2732 m_freem(m0); 2733 if (++cidx == r->size) 2734 cidx = 0; 2735 } 2736 reclaim_tx_descs(txq, 2048); 2737 total = remaining; 2738 goto done; 2739 } 2740 2741 /* How many hardware descriptors do we have readily available. */ 2742 if (eq->pidx == eq->cidx) 2743 available = eq->sidx - 1; 2744 else 2745 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2746 dbdiff = IDXDIFF(eq->pidx, eq->dbidx, eq->sidx); 2747 2748 while (remaining > 0) { 2749 2750 m0 = r->items[cidx]; 2751 M_ASSERTPKTHDR(m0); 2752 MPASS(m0->m_nextpkt == NULL); 2753 2754 if (available < SGE_MAX_WR_NDESC) { 2755 available += reclaim_tx_descs(txq, 64); 2756 if (available < howmany(mbuf_len16(m0), EQ_ESIZE / 16)) 2757 break; /* out of descriptors */ 2758 } 2759 2760 next_cidx = cidx + 1; 2761 if (__predict_false(next_cidx == r->size)) 2762 next_cidx = 0; 2763 2764 wr = (void *)&eq->desc[eq->pidx]; 2765 if (sc->flags & IS_VF) { 2766 total++; 2767 remaining--; 2768 ETHER_BPF_MTAP(ifp, m0); 2769 n = write_txpkt_vm_wr(sc, txq, (void *)wr, m0, 2770 available); 2771 } else if (remaining > 1 && 2772 try_txpkts(m0, r->items[next_cidx], &txp, available) == 0) { 2773 2774 /* pkts at cidx, next_cidx should both be in txp. */ 2775 MPASS(txp.npkt == 2); 2776 tail = r->items[next_cidx]; 2777 MPASS(tail->m_nextpkt == NULL); 2778 ETHER_BPF_MTAP(ifp, m0); 2779 ETHER_BPF_MTAP(ifp, tail); 2780 m0->m_nextpkt = tail; 2781 2782 if (__predict_false(++next_cidx == r->size)) 2783 next_cidx = 0; 2784 2785 while (next_cidx != pidx) { 2786 if (add_to_txpkts(r->items[next_cidx], &txp, 2787 available) != 0) 2788 break; 2789 tail->m_nextpkt = r->items[next_cidx]; 2790 tail = tail->m_nextpkt; 2791 ETHER_BPF_MTAP(ifp, tail); 2792 if (__predict_false(++next_cidx == r->size)) 2793 next_cidx = 0; 2794 } 2795 2796 n = write_txpkts_wr(txq, wr, m0, &txp, available); 2797 total += txp.npkt; 2798 remaining -= txp.npkt; 2799 } else { 2800 total++; 2801 remaining--; 2802 ETHER_BPF_MTAP(ifp, m0); 2803 n = write_txpkt_wr(txq, (void *)wr, m0, available); 2804 } 2805 MPASS(n >= 1 && n <= available && n <= SGE_MAX_WR_NDESC); 2806 2807 available -= n; 2808 dbdiff += n; 2809 IDXINCR(eq->pidx, n, eq->sidx); 2810 2811 if (total_available_tx_desc(eq) < eq->sidx / 4 && 2812 atomic_cmpset_int(&eq->equiq, 0, 1)) { 2813 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ | 2814 F_FW_WR_EQUEQ); 2815 eq->equeqidx = eq->pidx; 2816 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 32) { 2817 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ); 2818 eq->equeqidx = eq->pidx; 2819 } 2820 2821 if (dbdiff >= 16 && remaining >= 4) { 2822 ring_eq_db(sc, eq, dbdiff); 2823 available += reclaim_tx_descs(txq, 4 * dbdiff); 2824 dbdiff = 0; 2825 } 2826 2827 cidx = next_cidx; 2828 } 2829 if (dbdiff != 0) { 2830 ring_eq_db(sc, eq, dbdiff); 2831 reclaim_tx_descs(txq, 32); 2832 } 2833 done: 2834 TXQ_UNLOCK(txq); 2835 2836 return (total); 2837 } 2838 2839 static inline void 2840 init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int pktc_idx, 2841 int qsize) 2842 { 2843 2844 KASSERT(tmr_idx >= 0 && tmr_idx < SGE_NTIMERS, 2845 ("%s: bad tmr_idx %d", __func__, tmr_idx)); 2846 KASSERT(pktc_idx < SGE_NCOUNTERS, /* -ve is ok, means don't use */ 2847 ("%s: bad pktc_idx %d", __func__, pktc_idx)); 2848 2849 iq->flags = 0; 2850 iq->adapter = sc; 2851 iq->intr_params = V_QINTR_TIMER_IDX(tmr_idx); 2852 iq->intr_pktc_idx = SGE_NCOUNTERS - 1; 2853 if (pktc_idx >= 0) { 2854 iq->intr_params |= F_QINTR_CNT_EN; 2855 iq->intr_pktc_idx = pktc_idx; 2856 } 2857 iq->qsize = roundup2(qsize, 16); /* See FW_IQ_CMD/iqsize */ 2858 iq->sidx = iq->qsize - sc->params.sge.spg_len / IQ_ESIZE; 2859 } 2860 2861 static inline void 2862 init_fl(struct adapter *sc, struct sge_fl *fl, int qsize, int maxp, char *name) 2863 { 2864 2865 fl->qsize = qsize; 2866 fl->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE; 2867 strlcpy(fl->lockname, name, sizeof(fl->lockname)); 2868 if (sc->flags & BUF_PACKING_OK && 2869 ((!is_t4(sc) && buffer_packing) || /* T5+: enabled unless 0 */ 2870 (is_t4(sc) && buffer_packing == 1)))/* T4: disabled unless 1 */ 2871 fl->flags |= FL_BUF_PACKING; 2872 find_best_refill_source(sc, fl, maxp); 2873 find_safe_refill_source(sc, fl); 2874 } 2875 2876 static inline void 2877 init_eq(struct adapter *sc, struct sge_eq *eq, int eqtype, int qsize, 2878 uint8_t tx_chan, uint16_t iqid, char *name) 2879 { 2880 KASSERT(eqtype <= EQ_TYPEMASK, ("%s: bad qtype %d", __func__, eqtype)); 2881 2882 eq->flags = eqtype & EQ_TYPEMASK; 2883 eq->tx_chan = tx_chan; 2884 eq->iqid = iqid; 2885 eq->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE; 2886 strlcpy(eq->lockname, name, sizeof(eq->lockname)); 2887 } 2888 2889 static int 2890 alloc_ring(struct adapter *sc, size_t len, bus_dma_tag_t *tag, 2891 bus_dmamap_t *map, bus_addr_t *pa, void **va) 2892 { 2893 int rc; 2894 2895 rc = bus_dma_tag_create(sc->dmat, 512, 0, BUS_SPACE_MAXADDR, 2896 BUS_SPACE_MAXADDR, NULL, NULL, len, 1, len, 0, NULL, NULL, tag); 2897 if (rc != 0) { 2898 device_printf(sc->dev, "cannot allocate DMA tag: %d\n", rc); 2899 goto done; 2900 } 2901 2902 rc = bus_dmamem_alloc(*tag, va, 2903 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, map); 2904 if (rc != 0) { 2905 device_printf(sc->dev, "cannot allocate DMA memory: %d\n", rc); 2906 goto done; 2907 } 2908 2909 rc = bus_dmamap_load(*tag, *map, *va, len, oneseg_dma_callback, pa, 0); 2910 if (rc != 0) { 2911 device_printf(sc->dev, "cannot load DMA map: %d\n", rc); 2912 goto done; 2913 } 2914 done: 2915 if (rc) 2916 free_ring(sc, *tag, *map, *pa, *va); 2917 2918 return (rc); 2919 } 2920 2921 static int 2922 free_ring(struct adapter *sc, bus_dma_tag_t tag, bus_dmamap_t map, 2923 bus_addr_t pa, void *va) 2924 { 2925 if (pa) 2926 bus_dmamap_unload(tag, map); 2927 if (va) 2928 bus_dmamem_free(tag, va, map); 2929 if (tag) 2930 bus_dma_tag_destroy(tag); 2931 2932 return (0); 2933 } 2934 2935 /* 2936 * Allocates the ring for an ingress queue and an optional freelist. If the 2937 * freelist is specified it will be allocated and then associated with the 2938 * ingress queue. 2939 * 2940 * Returns errno on failure. Resources allocated up to that point may still be 2941 * allocated. Caller is responsible for cleanup in case this function fails. 2942 * 2943 * If the ingress queue will take interrupts directly then the intr_idx 2944 * specifies the vector, starting from 0. -1 means the interrupts for this 2945 * queue should be forwarded to the fwq. 2946 */ 2947 static int 2948 alloc_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl, 2949 int intr_idx, int cong) 2950 { 2951 int rc, i, cntxt_id; 2952 size_t len; 2953 struct fw_iq_cmd c; 2954 struct port_info *pi = vi->pi; 2955 struct adapter *sc = iq->adapter; 2956 struct sge_params *sp = &sc->params.sge; 2957 __be32 v = 0; 2958 2959 len = iq->qsize * IQ_ESIZE; 2960 rc = alloc_ring(sc, len, &iq->desc_tag, &iq->desc_map, &iq->ba, 2961 (void **)&iq->desc); 2962 if (rc != 0) 2963 return (rc); 2964 2965 bzero(&c, sizeof(c)); 2966 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 2967 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) | 2968 V_FW_IQ_CMD_VFN(0)); 2969 2970 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART | 2971 FW_LEN16(c)); 2972 2973 /* Special handling for firmware event queue */ 2974 if (iq == &sc->sge.fwq) 2975 v |= F_FW_IQ_CMD_IQASYNCH; 2976 2977 if (intr_idx < 0) { 2978 /* Forwarded interrupts, all headed to fwq */ 2979 v |= F_FW_IQ_CMD_IQANDST; 2980 v |= V_FW_IQ_CMD_IQANDSTINDEX(sc->sge.fwq.cntxt_id); 2981 } else { 2982 KASSERT(intr_idx < sc->intr_count, 2983 ("%s: invalid direct intr_idx %d", __func__, intr_idx)); 2984 v |= V_FW_IQ_CMD_IQANDSTINDEX(intr_idx); 2985 } 2986 2987 c.type_to_iqandstindex = htobe32(v | 2988 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) | 2989 V_FW_IQ_CMD_VIID(vi->viid) | 2990 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT)); 2991 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->tx_chan) | 2992 F_FW_IQ_CMD_IQGTSMODE | 2993 V_FW_IQ_CMD_IQINTCNTTHRESH(iq->intr_pktc_idx) | 2994 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4)); 2995 c.iqsize = htobe16(iq->qsize); 2996 c.iqaddr = htobe64(iq->ba); 2997 if (cong >= 0) 2998 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN); 2999 3000 if (fl) { 3001 mtx_init(&fl->fl_lock, fl->lockname, NULL, MTX_DEF); 3002 3003 len = fl->qsize * EQ_ESIZE; 3004 rc = alloc_ring(sc, len, &fl->desc_tag, &fl->desc_map, 3005 &fl->ba, (void **)&fl->desc); 3006 if (rc) 3007 return (rc); 3008 3009 /* Allocate space for one software descriptor per buffer. */ 3010 rc = alloc_fl_sdesc(fl); 3011 if (rc != 0) { 3012 device_printf(sc->dev, 3013 "failed to setup fl software descriptors: %d\n", 3014 rc); 3015 return (rc); 3016 } 3017 3018 if (fl->flags & FL_BUF_PACKING) { 3019 fl->lowat = roundup2(sp->fl_starve_threshold2, 8); 3020 fl->buf_boundary = sp->pack_boundary; 3021 } else { 3022 fl->lowat = roundup2(sp->fl_starve_threshold, 8); 3023 fl->buf_boundary = 16; 3024 } 3025 if (fl_pad && fl->buf_boundary < sp->pad_boundary) 3026 fl->buf_boundary = sp->pad_boundary; 3027 3028 c.iqns_to_fl0congen |= 3029 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) | 3030 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO | 3031 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) | 3032 (fl->flags & FL_BUF_PACKING ? F_FW_IQ_CMD_FL0PACKEN : 3033 0)); 3034 if (cong >= 0) { 3035 c.iqns_to_fl0congen |= 3036 htobe32(V_FW_IQ_CMD_FL0CNGCHMAP(cong) | 3037 F_FW_IQ_CMD_FL0CONGCIF | 3038 F_FW_IQ_CMD_FL0CONGEN); 3039 } 3040 c.fl0dcaen_to_fl0cidxfthresh = 3041 htobe16(V_FW_IQ_CMD_FL0FBMIN(chip_id(sc) <= CHELSIO_T5 ? 3042 X_FETCHBURSTMIN_128B : X_FETCHBURSTMIN_64B) | 3043 V_FW_IQ_CMD_FL0FBMAX(chip_id(sc) <= CHELSIO_T5 ? 3044 X_FETCHBURSTMAX_512B : X_FETCHBURSTMAX_256B)); 3045 c.fl0size = htobe16(fl->qsize); 3046 c.fl0addr = htobe64(fl->ba); 3047 } 3048 3049 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3050 if (rc != 0) { 3051 device_printf(sc->dev, 3052 "failed to create ingress queue: %d\n", rc); 3053 return (rc); 3054 } 3055 3056 iq->cidx = 0; 3057 iq->gen = F_RSPD_GEN; 3058 iq->intr_next = iq->intr_params; 3059 iq->cntxt_id = be16toh(c.iqid); 3060 iq->abs_id = be16toh(c.physiqid); 3061 iq->flags |= IQ_ALLOCATED; 3062 3063 cntxt_id = iq->cntxt_id - sc->sge.iq_start; 3064 if (cntxt_id >= sc->sge.niq) { 3065 panic ("%s: iq->cntxt_id (%d) more than the max (%d)", __func__, 3066 cntxt_id, sc->sge.niq - 1); 3067 } 3068 sc->sge.iqmap[cntxt_id] = iq; 3069 3070 if (fl) { 3071 u_int qid; 3072 3073 iq->flags |= IQ_HAS_FL; 3074 fl->cntxt_id = be16toh(c.fl0id); 3075 fl->pidx = fl->cidx = 0; 3076 3077 cntxt_id = fl->cntxt_id - sc->sge.eq_start; 3078 if (cntxt_id >= sc->sge.neq) { 3079 panic("%s: fl->cntxt_id (%d) more than the max (%d)", 3080 __func__, cntxt_id, sc->sge.neq - 1); 3081 } 3082 sc->sge.eqmap[cntxt_id] = (void *)fl; 3083 3084 qid = fl->cntxt_id; 3085 if (isset(&sc->doorbells, DOORBELL_UDB)) { 3086 uint32_t s_qpp = sc->params.sge.eq_s_qpp; 3087 uint32_t mask = (1 << s_qpp) - 1; 3088 volatile uint8_t *udb; 3089 3090 udb = sc->udbs_base + UDBS_DB_OFFSET; 3091 udb += (qid >> s_qpp) << PAGE_SHIFT; 3092 qid &= mask; 3093 if (qid < PAGE_SIZE / UDBS_SEG_SIZE) { 3094 udb += qid << UDBS_SEG_SHIFT; 3095 qid = 0; 3096 } 3097 fl->udb = (volatile void *)udb; 3098 } 3099 fl->dbval = V_QID(qid) | sc->chip_params->sge_fl_db; 3100 3101 FL_LOCK(fl); 3102 /* Enough to make sure the SGE doesn't think it's starved */ 3103 refill_fl(sc, fl, fl->lowat); 3104 FL_UNLOCK(fl); 3105 } 3106 3107 if (chip_id(sc) >= CHELSIO_T5 && !(sc->flags & IS_VF) && cong >= 0) { 3108 uint32_t param, val; 3109 3110 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 3111 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) | 3112 V_FW_PARAMS_PARAM_YZ(iq->cntxt_id); 3113 if (cong == 0) 3114 val = 1 << 19; 3115 else { 3116 val = 2 << 19; 3117 for (i = 0; i < 4; i++) { 3118 if (cong & (1 << i)) 3119 val |= 1 << (i << 2); 3120 } 3121 } 3122 3123 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 3124 if (rc != 0) { 3125 /* report error but carry on */ 3126 device_printf(sc->dev, 3127 "failed to set congestion manager context for " 3128 "ingress queue %d: %d\n", iq->cntxt_id, rc); 3129 } 3130 } 3131 3132 /* Enable IQ interrupts */ 3133 atomic_store_rel_int(&iq->state, IQS_IDLE); 3134 t4_write_reg(sc, sc->sge_gts_reg, V_SEINTARM(iq->intr_params) | 3135 V_INGRESSQID(iq->cntxt_id)); 3136 3137 return (0); 3138 } 3139 3140 static int 3141 free_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl) 3142 { 3143 int rc; 3144 struct adapter *sc = iq->adapter; 3145 device_t dev; 3146 3147 if (sc == NULL) 3148 return (0); /* nothing to do */ 3149 3150 dev = vi ? vi->dev : sc->dev; 3151 3152 if (iq->flags & IQ_ALLOCATED) { 3153 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0, 3154 FW_IQ_TYPE_FL_INT_CAP, iq->cntxt_id, 3155 fl ? fl->cntxt_id : 0xffff, 0xffff); 3156 if (rc != 0) { 3157 device_printf(dev, 3158 "failed to free queue %p: %d\n", iq, rc); 3159 return (rc); 3160 } 3161 iq->flags &= ~IQ_ALLOCATED; 3162 } 3163 3164 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, iq->desc); 3165 3166 bzero(iq, sizeof(*iq)); 3167 3168 if (fl) { 3169 free_ring(sc, fl->desc_tag, fl->desc_map, fl->ba, 3170 fl->desc); 3171 3172 if (fl->sdesc) 3173 free_fl_sdesc(sc, fl); 3174 3175 if (mtx_initialized(&fl->fl_lock)) 3176 mtx_destroy(&fl->fl_lock); 3177 3178 bzero(fl, sizeof(*fl)); 3179 } 3180 3181 return (0); 3182 } 3183 3184 static void 3185 add_iq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid, 3186 struct sge_iq *iq) 3187 { 3188 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3189 3190 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, &iq->ba, 3191 "bus address of descriptor ring"); 3192 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3193 iq->qsize * IQ_ESIZE, "descriptor ring size in bytes"); 3194 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "abs_id", 3195 CTLTYPE_INT | CTLFLAG_RD, &iq->abs_id, 0, sysctl_uint16, "I", 3196 "absolute id of the queue"); 3197 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 3198 CTLTYPE_INT | CTLFLAG_RD, &iq->cntxt_id, 0, sysctl_uint16, "I", 3199 "SGE context id of the queue"); 3200 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx", 3201 CTLTYPE_INT | CTLFLAG_RD, &iq->cidx, 0, sysctl_uint16, "I", 3202 "consumer index"); 3203 } 3204 3205 static void 3206 add_fl_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx, 3207 struct sysctl_oid *oid, struct sge_fl *fl) 3208 { 3209 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3210 3211 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL, 3212 "freelist"); 3213 children = SYSCTL_CHILDREN(oid); 3214 3215 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, 3216 &fl->ba, "bus address of descriptor ring"); 3217 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3218 fl->sidx * EQ_ESIZE + sc->params.sge.spg_len, 3219 "desc ring size in bytes"); 3220 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 3221 CTLTYPE_INT | CTLFLAG_RD, &fl->cntxt_id, 0, sysctl_uint16, "I", 3222 "SGE context id of the freelist"); 3223 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "padding", CTLFLAG_RD, NULL, 3224 fl_pad ? 1 : 0, "padding enabled"); 3225 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "packing", CTLFLAG_RD, NULL, 3226 fl->flags & FL_BUF_PACKING ? 1 : 0, "packing enabled"); 3227 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &fl->cidx, 3228 0, "consumer index"); 3229 if (fl->flags & FL_BUF_PACKING) { 3230 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rx_offset", 3231 CTLFLAG_RD, &fl->rx_offset, 0, "packing rx offset"); 3232 } 3233 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &fl->pidx, 3234 0, "producer index"); 3235 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_allocated", 3236 CTLFLAG_RD, &fl->mbuf_allocated, "# of mbuf allocated"); 3237 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_inlined", 3238 CTLFLAG_RD, &fl->mbuf_inlined, "# of mbuf inlined in clusters"); 3239 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_allocated", 3240 CTLFLAG_RD, &fl->cl_allocated, "# of clusters allocated"); 3241 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_recycled", 3242 CTLFLAG_RD, &fl->cl_recycled, "# of clusters recycled"); 3243 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_fast_recycled", 3244 CTLFLAG_RD, &fl->cl_fast_recycled, "# of clusters recycled (fast)"); 3245 } 3246 3247 static int 3248 alloc_fwq(struct adapter *sc) 3249 { 3250 int rc, intr_idx; 3251 struct sge_iq *fwq = &sc->sge.fwq; 3252 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev); 3253 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3254 3255 init_iq(fwq, sc, 0, 0, FW_IQ_QSIZE); 3256 if (sc->flags & IS_VF) 3257 intr_idx = 0; 3258 else 3259 intr_idx = sc->intr_count > 1 ? 1 : 0; 3260 rc = alloc_iq_fl(&sc->port[0]->vi[0], fwq, NULL, intr_idx, -1); 3261 if (rc != 0) { 3262 device_printf(sc->dev, 3263 "failed to create firmware event queue: %d\n", rc); 3264 return (rc); 3265 } 3266 3267 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "fwq", CTLFLAG_RD, 3268 NULL, "firmware event queue"); 3269 add_iq_sysctls(&sc->ctx, oid, fwq); 3270 3271 return (0); 3272 } 3273 3274 static int 3275 free_fwq(struct adapter *sc) 3276 { 3277 return free_iq_fl(NULL, &sc->sge.fwq, NULL); 3278 } 3279 3280 static int 3281 alloc_ctrlq(struct adapter *sc, struct sge_wrq *ctrlq, int idx, 3282 struct sysctl_oid *oid) 3283 { 3284 int rc; 3285 char name[16]; 3286 struct sysctl_oid_list *children; 3287 3288 snprintf(name, sizeof(name), "%s ctrlq%d", device_get_nameunit(sc->dev), 3289 idx); 3290 init_eq(sc, &ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE, sc->port[idx]->tx_chan, 3291 sc->sge.fwq.cntxt_id, name); 3292 3293 children = SYSCTL_CHILDREN(oid); 3294 snprintf(name, sizeof(name), "%d", idx); 3295 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, name, CTLFLAG_RD, 3296 NULL, "ctrl queue"); 3297 rc = alloc_wrq(sc, NULL, ctrlq, oid); 3298 3299 return (rc); 3300 } 3301 3302 int 3303 tnl_cong(struct port_info *pi, int drop) 3304 { 3305 3306 if (drop == -1) 3307 return (-1); 3308 else if (drop == 1) 3309 return (0); 3310 else 3311 return (pi->rx_e_chan_map); 3312 } 3313 3314 static int 3315 alloc_rxq(struct vi_info *vi, struct sge_rxq *rxq, int intr_idx, int idx, 3316 struct sysctl_oid *oid) 3317 { 3318 int rc; 3319 struct adapter *sc = vi->pi->adapter; 3320 struct sysctl_oid_list *children; 3321 char name[16]; 3322 3323 rc = alloc_iq_fl(vi, &rxq->iq, &rxq->fl, intr_idx, 3324 tnl_cong(vi->pi, cong_drop)); 3325 if (rc != 0) 3326 return (rc); 3327 3328 if (idx == 0) 3329 sc->sge.iq_base = rxq->iq.abs_id - rxq->iq.cntxt_id; 3330 else 3331 KASSERT(rxq->iq.cntxt_id + sc->sge.iq_base == rxq->iq.abs_id, 3332 ("iq_base mismatch")); 3333 KASSERT(sc->sge.iq_base == 0 || sc->flags & IS_VF, 3334 ("PF with non-zero iq_base")); 3335 3336 /* 3337 * The freelist is just barely above the starvation threshold right now, 3338 * fill it up a bit more. 3339 */ 3340 FL_LOCK(&rxq->fl); 3341 refill_fl(sc, &rxq->fl, 128); 3342 FL_UNLOCK(&rxq->fl); 3343 3344 #if defined(INET) || defined(INET6) 3345 rc = tcp_lro_init_args(&rxq->lro, vi->ifp, lro_entries, lro_mbufs); 3346 if (rc != 0) 3347 return (rc); 3348 MPASS(rxq->lro.ifp == vi->ifp); /* also indicates LRO init'ed */ 3349 3350 if (vi->ifp->if_capenable & IFCAP_LRO) 3351 rxq->iq.flags |= IQ_LRO_ENABLED; 3352 #endif 3353 rxq->ifp = vi->ifp; 3354 3355 children = SYSCTL_CHILDREN(oid); 3356 3357 snprintf(name, sizeof(name), "%d", idx); 3358 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 3359 NULL, "rx queue"); 3360 children = SYSCTL_CHILDREN(oid); 3361 3362 add_iq_sysctls(&vi->ctx, oid, &rxq->iq); 3363 #if defined(INET) || defined(INET6) 3364 SYSCTL_ADD_U64(&vi->ctx, children, OID_AUTO, "lro_queued", CTLFLAG_RD, 3365 &rxq->lro.lro_queued, 0, NULL); 3366 SYSCTL_ADD_U64(&vi->ctx, children, OID_AUTO, "lro_flushed", CTLFLAG_RD, 3367 &rxq->lro.lro_flushed, 0, NULL); 3368 #endif 3369 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "rxcsum", CTLFLAG_RD, 3370 &rxq->rxcsum, "# of times hardware assisted with checksum"); 3371 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_extraction", 3372 CTLFLAG_RD, &rxq->vlan_extraction, 3373 "# of times hardware extracted 802.1Q tag"); 3374 3375 add_fl_sysctls(sc, &vi->ctx, oid, &rxq->fl); 3376 3377 return (rc); 3378 } 3379 3380 static int 3381 free_rxq(struct vi_info *vi, struct sge_rxq *rxq) 3382 { 3383 int rc; 3384 3385 #if defined(INET) || defined(INET6) 3386 if (rxq->lro.ifp) { 3387 tcp_lro_free(&rxq->lro); 3388 rxq->lro.ifp = NULL; 3389 } 3390 #endif 3391 3392 rc = free_iq_fl(vi, &rxq->iq, &rxq->fl); 3393 if (rc == 0) 3394 bzero(rxq, sizeof(*rxq)); 3395 3396 return (rc); 3397 } 3398 3399 #ifdef TCP_OFFLOAD 3400 static int 3401 alloc_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq, 3402 int intr_idx, int idx, struct sysctl_oid *oid) 3403 { 3404 struct port_info *pi = vi->pi; 3405 int rc; 3406 struct sysctl_oid_list *children; 3407 char name[16]; 3408 3409 rc = alloc_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl, intr_idx, 0); 3410 if (rc != 0) 3411 return (rc); 3412 3413 children = SYSCTL_CHILDREN(oid); 3414 3415 snprintf(name, sizeof(name), "%d", idx); 3416 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 3417 NULL, "rx queue"); 3418 add_iq_sysctls(&vi->ctx, oid, &ofld_rxq->iq); 3419 add_fl_sysctls(pi->adapter, &vi->ctx, oid, &ofld_rxq->fl); 3420 3421 return (rc); 3422 } 3423 3424 static int 3425 free_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq) 3426 { 3427 int rc; 3428 3429 rc = free_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl); 3430 if (rc == 0) 3431 bzero(ofld_rxq, sizeof(*ofld_rxq)); 3432 3433 return (rc); 3434 } 3435 #endif 3436 3437 #ifdef DEV_NETMAP 3438 static int 3439 alloc_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq, int intr_idx, 3440 int idx, struct sysctl_oid *oid) 3441 { 3442 int rc; 3443 struct sysctl_oid_list *children; 3444 struct sysctl_ctx_list *ctx; 3445 char name[16]; 3446 size_t len; 3447 struct adapter *sc = vi->pi->adapter; 3448 struct netmap_adapter *na = NA(vi->ifp); 3449 3450 MPASS(na != NULL); 3451 3452 len = vi->qsize_rxq * IQ_ESIZE; 3453 rc = alloc_ring(sc, len, &nm_rxq->iq_desc_tag, &nm_rxq->iq_desc_map, 3454 &nm_rxq->iq_ba, (void **)&nm_rxq->iq_desc); 3455 if (rc != 0) 3456 return (rc); 3457 3458 len = na->num_rx_desc * EQ_ESIZE + sc->params.sge.spg_len; 3459 rc = alloc_ring(sc, len, &nm_rxq->fl_desc_tag, &nm_rxq->fl_desc_map, 3460 &nm_rxq->fl_ba, (void **)&nm_rxq->fl_desc); 3461 if (rc != 0) 3462 return (rc); 3463 3464 nm_rxq->vi = vi; 3465 nm_rxq->nid = idx; 3466 nm_rxq->iq_cidx = 0; 3467 nm_rxq->iq_sidx = vi->qsize_rxq - sc->params.sge.spg_len / IQ_ESIZE; 3468 nm_rxq->iq_gen = F_RSPD_GEN; 3469 nm_rxq->fl_pidx = nm_rxq->fl_cidx = 0; 3470 nm_rxq->fl_sidx = na->num_rx_desc; 3471 nm_rxq->intr_idx = intr_idx; 3472 nm_rxq->iq_cntxt_id = INVALID_NM_RXQ_CNTXT_ID; 3473 3474 ctx = &vi->ctx; 3475 children = SYSCTL_CHILDREN(oid); 3476 3477 snprintf(name, sizeof(name), "%d", idx); 3478 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, name, CTLFLAG_RD, NULL, 3479 "rx queue"); 3480 children = SYSCTL_CHILDREN(oid); 3481 3482 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "abs_id", 3483 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_abs_id, 0, sysctl_uint16, 3484 "I", "absolute id of the queue"); 3485 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 3486 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cntxt_id, 0, sysctl_uint16, 3487 "I", "SGE context id of the queue"); 3488 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx", 3489 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cidx, 0, sysctl_uint16, "I", 3490 "consumer index"); 3491 3492 children = SYSCTL_CHILDREN(oid); 3493 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL, 3494 "freelist"); 3495 children = SYSCTL_CHILDREN(oid); 3496 3497 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 3498 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->fl_cntxt_id, 0, sysctl_uint16, 3499 "I", "SGE context id of the freelist"); 3500 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, 3501 &nm_rxq->fl_cidx, 0, "consumer index"); 3502 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, 3503 &nm_rxq->fl_pidx, 0, "producer index"); 3504 3505 return (rc); 3506 } 3507 3508 3509 static int 3510 free_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq) 3511 { 3512 struct adapter *sc = vi->pi->adapter; 3513 3514 if (vi->flags & VI_INIT_DONE) 3515 MPASS(nm_rxq->iq_cntxt_id == INVALID_NM_RXQ_CNTXT_ID); 3516 else 3517 MPASS(nm_rxq->iq_cntxt_id == 0); 3518 3519 free_ring(sc, nm_rxq->iq_desc_tag, nm_rxq->iq_desc_map, nm_rxq->iq_ba, 3520 nm_rxq->iq_desc); 3521 free_ring(sc, nm_rxq->fl_desc_tag, nm_rxq->fl_desc_map, nm_rxq->fl_ba, 3522 nm_rxq->fl_desc); 3523 3524 return (0); 3525 } 3526 3527 static int 3528 alloc_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq, int iqidx, int idx, 3529 struct sysctl_oid *oid) 3530 { 3531 int rc; 3532 size_t len; 3533 struct port_info *pi = vi->pi; 3534 struct adapter *sc = pi->adapter; 3535 struct netmap_adapter *na = NA(vi->ifp); 3536 char name[16]; 3537 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3538 3539 len = na->num_tx_desc * EQ_ESIZE + sc->params.sge.spg_len; 3540 rc = alloc_ring(sc, len, &nm_txq->desc_tag, &nm_txq->desc_map, 3541 &nm_txq->ba, (void **)&nm_txq->desc); 3542 if (rc) 3543 return (rc); 3544 3545 nm_txq->pidx = nm_txq->cidx = 0; 3546 nm_txq->sidx = na->num_tx_desc; 3547 nm_txq->nid = idx; 3548 nm_txq->iqidx = iqidx; 3549 nm_txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) | 3550 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(G_FW_VIID_PFN(vi->viid)) | 3551 V_TXPKT_VF(G_FW_VIID_VIN(vi->viid)) | 3552 V_TXPKT_VF_VLD(G_FW_VIID_VIVLD(vi->viid))); 3553 nm_txq->cntxt_id = INVALID_NM_TXQ_CNTXT_ID; 3554 3555 snprintf(name, sizeof(name), "%d", idx); 3556 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 3557 NULL, "netmap tx queue"); 3558 children = SYSCTL_CHILDREN(oid); 3559 3560 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 3561 &nm_txq->cntxt_id, 0, "SGE context id of the queue"); 3562 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx", 3563 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->cidx, 0, sysctl_uint16, "I", 3564 "consumer index"); 3565 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "pidx", 3566 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->pidx, 0, sysctl_uint16, "I", 3567 "producer index"); 3568 3569 return (rc); 3570 } 3571 3572 static int 3573 free_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq) 3574 { 3575 struct adapter *sc = vi->pi->adapter; 3576 3577 if (vi->flags & VI_INIT_DONE) 3578 MPASS(nm_txq->cntxt_id == INVALID_NM_TXQ_CNTXT_ID); 3579 else 3580 MPASS(nm_txq->cntxt_id == 0); 3581 3582 free_ring(sc, nm_txq->desc_tag, nm_txq->desc_map, nm_txq->ba, 3583 nm_txq->desc); 3584 3585 return (0); 3586 } 3587 #endif 3588 3589 /* 3590 * Returns a reasonable automatic cidx flush threshold for a given queue size. 3591 */ 3592 static u_int 3593 qsize_to_fthresh(int qsize) 3594 { 3595 u_int fthresh; 3596 3597 while (!powerof2(qsize)) 3598 qsize++; 3599 fthresh = ilog2(qsize); 3600 if (fthresh > X_CIDXFLUSHTHRESH_128) 3601 fthresh = X_CIDXFLUSHTHRESH_128; 3602 3603 return (fthresh); 3604 } 3605 3606 static int 3607 ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq) 3608 { 3609 int rc, cntxt_id; 3610 struct fw_eq_ctrl_cmd c; 3611 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 3612 3613 bzero(&c, sizeof(c)); 3614 3615 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | F_FW_CMD_REQUEST | 3616 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_CTRL_CMD_PFN(sc->pf) | 3617 V_FW_EQ_CTRL_CMD_VFN(0)); 3618 c.alloc_to_len16 = htobe32(F_FW_EQ_CTRL_CMD_ALLOC | 3619 F_FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c)); 3620 c.cmpliqid_eqid = htonl(V_FW_EQ_CTRL_CMD_CMPLIQID(eq->iqid)); 3621 c.physeqid_pkd = htobe32(0); 3622 c.fetchszm_to_iqid = 3623 htobe32(V_FW_EQ_CTRL_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 3624 V_FW_EQ_CTRL_CMD_PCIECHN(eq->tx_chan) | 3625 F_FW_EQ_CTRL_CMD_FETCHRO | V_FW_EQ_CTRL_CMD_IQID(eq->iqid)); 3626 c.dcaen_to_eqsize = 3627 htobe32(V_FW_EQ_CTRL_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 3628 V_FW_EQ_CTRL_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 3629 V_FW_EQ_CTRL_CMD_CIDXFTHRESH(qsize_to_fthresh(qsize)) | 3630 V_FW_EQ_CTRL_CMD_EQSIZE(qsize)); 3631 c.eqaddr = htobe64(eq->ba); 3632 3633 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3634 if (rc != 0) { 3635 device_printf(sc->dev, 3636 "failed to create control queue %d: %d\n", eq->tx_chan, rc); 3637 return (rc); 3638 } 3639 eq->flags |= EQ_ALLOCATED; 3640 3641 eq->cntxt_id = G_FW_EQ_CTRL_CMD_EQID(be32toh(c.cmpliqid_eqid)); 3642 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 3643 if (cntxt_id >= sc->sge.neq) 3644 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 3645 cntxt_id, sc->sge.neq - 1); 3646 sc->sge.eqmap[cntxt_id] = eq; 3647 3648 return (rc); 3649 } 3650 3651 static int 3652 eth_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 3653 { 3654 int rc, cntxt_id; 3655 struct fw_eq_eth_cmd c; 3656 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 3657 3658 bzero(&c, sizeof(c)); 3659 3660 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST | 3661 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) | 3662 V_FW_EQ_ETH_CMD_VFN(0)); 3663 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC | 3664 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c)); 3665 c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE | 3666 F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(vi->viid)); 3667 c.fetchszm_to_iqid = 3668 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) | 3669 V_FW_EQ_ETH_CMD_PCIECHN(eq->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO | 3670 V_FW_EQ_ETH_CMD_IQID(eq->iqid)); 3671 c.dcaen_to_eqsize = htobe32(V_FW_EQ_ETH_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 3672 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 3673 V_FW_EQ_ETH_CMD_EQSIZE(qsize)); 3674 c.eqaddr = htobe64(eq->ba); 3675 3676 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3677 if (rc != 0) { 3678 device_printf(vi->dev, 3679 "failed to create Ethernet egress queue: %d\n", rc); 3680 return (rc); 3681 } 3682 eq->flags |= EQ_ALLOCATED; 3683 3684 eq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd)); 3685 eq->abs_id = G_FW_EQ_ETH_CMD_PHYSEQID(be32toh(c.physeqid_pkd)); 3686 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 3687 if (cntxt_id >= sc->sge.neq) 3688 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 3689 cntxt_id, sc->sge.neq - 1); 3690 sc->sge.eqmap[cntxt_id] = eq; 3691 3692 return (rc); 3693 } 3694 3695 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 3696 static int 3697 ofld_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 3698 { 3699 int rc, cntxt_id; 3700 struct fw_eq_ofld_cmd c; 3701 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 3702 3703 bzero(&c, sizeof(c)); 3704 3705 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | F_FW_CMD_REQUEST | 3706 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_OFLD_CMD_PFN(sc->pf) | 3707 V_FW_EQ_OFLD_CMD_VFN(0)); 3708 c.alloc_to_len16 = htonl(F_FW_EQ_OFLD_CMD_ALLOC | 3709 F_FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c)); 3710 c.fetchszm_to_iqid = 3711 htonl(V_FW_EQ_OFLD_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 3712 V_FW_EQ_OFLD_CMD_PCIECHN(eq->tx_chan) | 3713 F_FW_EQ_OFLD_CMD_FETCHRO | V_FW_EQ_OFLD_CMD_IQID(eq->iqid)); 3714 c.dcaen_to_eqsize = 3715 htobe32(V_FW_EQ_OFLD_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 3716 V_FW_EQ_OFLD_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 3717 V_FW_EQ_OFLD_CMD_CIDXFTHRESH(qsize_to_fthresh(qsize)) | 3718 V_FW_EQ_OFLD_CMD_EQSIZE(qsize)); 3719 c.eqaddr = htobe64(eq->ba); 3720 3721 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3722 if (rc != 0) { 3723 device_printf(vi->dev, 3724 "failed to create egress queue for TCP offload: %d\n", rc); 3725 return (rc); 3726 } 3727 eq->flags |= EQ_ALLOCATED; 3728 3729 eq->cntxt_id = G_FW_EQ_OFLD_CMD_EQID(be32toh(c.eqid_pkd)); 3730 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 3731 if (cntxt_id >= sc->sge.neq) 3732 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 3733 cntxt_id, sc->sge.neq - 1); 3734 sc->sge.eqmap[cntxt_id] = eq; 3735 3736 return (rc); 3737 } 3738 #endif 3739 3740 static int 3741 alloc_eq(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 3742 { 3743 int rc, qsize; 3744 size_t len; 3745 3746 mtx_init(&eq->eq_lock, eq->lockname, NULL, MTX_DEF); 3747 3748 qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 3749 len = qsize * EQ_ESIZE; 3750 rc = alloc_ring(sc, len, &eq->desc_tag, &eq->desc_map, 3751 &eq->ba, (void **)&eq->desc); 3752 if (rc) 3753 return (rc); 3754 3755 eq->pidx = eq->cidx = eq->dbidx = 0; 3756 /* Note that equeqidx is not used with sge_wrq (OFLD/CTRL) queues. */ 3757 eq->equeqidx = 0; 3758 eq->doorbells = sc->doorbells; 3759 3760 switch (eq->flags & EQ_TYPEMASK) { 3761 case EQ_CTRL: 3762 rc = ctrl_eq_alloc(sc, eq); 3763 break; 3764 3765 case EQ_ETH: 3766 rc = eth_eq_alloc(sc, vi, eq); 3767 break; 3768 3769 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 3770 case EQ_OFLD: 3771 rc = ofld_eq_alloc(sc, vi, eq); 3772 break; 3773 #endif 3774 3775 default: 3776 panic("%s: invalid eq type %d.", __func__, 3777 eq->flags & EQ_TYPEMASK); 3778 } 3779 if (rc != 0) { 3780 device_printf(sc->dev, 3781 "failed to allocate egress queue(%d): %d\n", 3782 eq->flags & EQ_TYPEMASK, rc); 3783 } 3784 3785 if (isset(&eq->doorbells, DOORBELL_UDB) || 3786 isset(&eq->doorbells, DOORBELL_UDBWC) || 3787 isset(&eq->doorbells, DOORBELL_WCWR)) { 3788 uint32_t s_qpp = sc->params.sge.eq_s_qpp; 3789 uint32_t mask = (1 << s_qpp) - 1; 3790 volatile uint8_t *udb; 3791 3792 udb = sc->udbs_base + UDBS_DB_OFFSET; 3793 udb += (eq->cntxt_id >> s_qpp) << PAGE_SHIFT; /* pg offset */ 3794 eq->udb_qid = eq->cntxt_id & mask; /* id in page */ 3795 if (eq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE) 3796 clrbit(&eq->doorbells, DOORBELL_WCWR); 3797 else { 3798 udb += eq->udb_qid << UDBS_SEG_SHIFT; /* seg offset */ 3799 eq->udb_qid = 0; 3800 } 3801 eq->udb = (volatile void *)udb; 3802 } 3803 3804 return (rc); 3805 } 3806 3807 static int 3808 free_eq(struct adapter *sc, struct sge_eq *eq) 3809 { 3810 int rc; 3811 3812 if (eq->flags & EQ_ALLOCATED) { 3813 switch (eq->flags & EQ_TYPEMASK) { 3814 case EQ_CTRL: 3815 rc = -t4_ctrl_eq_free(sc, sc->mbox, sc->pf, 0, 3816 eq->cntxt_id); 3817 break; 3818 3819 case EQ_ETH: 3820 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0, 3821 eq->cntxt_id); 3822 break; 3823 3824 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 3825 case EQ_OFLD: 3826 rc = -t4_ofld_eq_free(sc, sc->mbox, sc->pf, 0, 3827 eq->cntxt_id); 3828 break; 3829 #endif 3830 3831 default: 3832 panic("%s: invalid eq type %d.", __func__, 3833 eq->flags & EQ_TYPEMASK); 3834 } 3835 if (rc != 0) { 3836 device_printf(sc->dev, 3837 "failed to free egress queue (%d): %d\n", 3838 eq->flags & EQ_TYPEMASK, rc); 3839 return (rc); 3840 } 3841 eq->flags &= ~EQ_ALLOCATED; 3842 } 3843 3844 free_ring(sc, eq->desc_tag, eq->desc_map, eq->ba, eq->desc); 3845 3846 if (mtx_initialized(&eq->eq_lock)) 3847 mtx_destroy(&eq->eq_lock); 3848 3849 bzero(eq, sizeof(*eq)); 3850 return (0); 3851 } 3852 3853 static int 3854 alloc_wrq(struct adapter *sc, struct vi_info *vi, struct sge_wrq *wrq, 3855 struct sysctl_oid *oid) 3856 { 3857 int rc; 3858 struct sysctl_ctx_list *ctx = vi ? &vi->ctx : &sc->ctx; 3859 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3860 3861 rc = alloc_eq(sc, vi, &wrq->eq); 3862 if (rc) 3863 return (rc); 3864 3865 wrq->adapter = sc; 3866 TASK_INIT(&wrq->wrq_tx_task, 0, wrq_tx_drain, wrq); 3867 TAILQ_INIT(&wrq->incomplete_wrs); 3868 STAILQ_INIT(&wrq->wr_list); 3869 wrq->nwr_pending = 0; 3870 wrq->ndesc_needed = 0; 3871 3872 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, 3873 &wrq->eq.ba, "bus address of descriptor ring"); 3874 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3875 wrq->eq.sidx * EQ_ESIZE + sc->params.sge.spg_len, 3876 "desc ring size in bytes"); 3877 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 3878 &wrq->eq.cntxt_id, 0, "SGE context id of the queue"); 3879 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx", 3880 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.cidx, 0, sysctl_uint16, "I", 3881 "consumer index"); 3882 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pidx", 3883 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.pidx, 0, sysctl_uint16, "I", 3884 "producer index"); 3885 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL, 3886 wrq->eq.sidx, "status page index"); 3887 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_direct", CTLFLAG_RD, 3888 &wrq->tx_wrs_direct, "# of work requests (direct)"); 3889 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_copied", CTLFLAG_RD, 3890 &wrq->tx_wrs_copied, "# of work requests (copied)"); 3891 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_sspace", CTLFLAG_RD, 3892 &wrq->tx_wrs_ss, "# of work requests (copied from scratch space)"); 3893 3894 return (rc); 3895 } 3896 3897 static int 3898 free_wrq(struct adapter *sc, struct sge_wrq *wrq) 3899 { 3900 int rc; 3901 3902 rc = free_eq(sc, &wrq->eq); 3903 if (rc) 3904 return (rc); 3905 3906 bzero(wrq, sizeof(*wrq)); 3907 return (0); 3908 } 3909 3910 static int 3911 alloc_txq(struct vi_info *vi, struct sge_txq *txq, int idx, 3912 struct sysctl_oid *oid) 3913 { 3914 int rc; 3915 struct port_info *pi = vi->pi; 3916 struct adapter *sc = pi->adapter; 3917 struct sge_eq *eq = &txq->eq; 3918 char name[16]; 3919 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3920 3921 rc = mp_ring_alloc(&txq->r, eq->sidx, txq, eth_tx, can_resume_eth_tx, 3922 M_CXGBE, M_WAITOK); 3923 if (rc != 0) { 3924 device_printf(sc->dev, "failed to allocate mp_ring: %d\n", rc); 3925 return (rc); 3926 } 3927 3928 rc = alloc_eq(sc, vi, eq); 3929 if (rc != 0) { 3930 mp_ring_free(txq->r); 3931 txq->r = NULL; 3932 return (rc); 3933 } 3934 3935 /* Can't fail after this point. */ 3936 3937 if (idx == 0) 3938 sc->sge.eq_base = eq->abs_id - eq->cntxt_id; 3939 else 3940 KASSERT(eq->cntxt_id + sc->sge.eq_base == eq->abs_id, 3941 ("eq_base mismatch")); 3942 KASSERT(sc->sge.eq_base == 0 || sc->flags & IS_VF, 3943 ("PF with non-zero eq_base")); 3944 3945 TASK_INIT(&txq->tx_reclaim_task, 0, tx_reclaim, eq); 3946 txq->ifp = vi->ifp; 3947 txq->gl = sglist_alloc(TX_SGL_SEGS, M_WAITOK); 3948 if (sc->flags & IS_VF) 3949 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) | 3950 V_TXPKT_INTF(pi->tx_chan)); 3951 else 3952 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) | 3953 V_TXPKT_INTF(pi->tx_chan) | 3954 V_TXPKT_PF(G_FW_VIID_PFN(vi->viid)) | 3955 V_TXPKT_VF(G_FW_VIID_VIN(vi->viid)) | 3956 V_TXPKT_VF_VLD(G_FW_VIID_VIVLD(vi->viid))); 3957 txq->tc_idx = -1; 3958 txq->sdesc = malloc(eq->sidx * sizeof(struct tx_sdesc), M_CXGBE, 3959 M_ZERO | M_WAITOK); 3960 3961 snprintf(name, sizeof(name), "%d", idx); 3962 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 3963 NULL, "tx queue"); 3964 children = SYSCTL_CHILDREN(oid); 3965 3966 SYSCTL_ADD_UAUTO(&vi->ctx, children, OID_AUTO, "ba", CTLFLAG_RD, 3967 &eq->ba, "bus address of descriptor ring"); 3968 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3969 eq->sidx * EQ_ESIZE + sc->params.sge.spg_len, 3970 "desc ring size in bytes"); 3971 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "abs_id", CTLFLAG_RD, 3972 &eq->abs_id, 0, "absolute id of the queue"); 3973 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 3974 &eq->cntxt_id, 0, "SGE context id of the queue"); 3975 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx", 3976 CTLTYPE_INT | CTLFLAG_RD, &eq->cidx, 0, sysctl_uint16, "I", 3977 "consumer index"); 3978 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "pidx", 3979 CTLTYPE_INT | CTLFLAG_RD, &eq->pidx, 0, sysctl_uint16, "I", 3980 "producer index"); 3981 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL, 3982 eq->sidx, "status page index"); 3983 3984 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "tc", 3985 CTLTYPE_INT | CTLFLAG_RW, vi, idx, sysctl_tc, "I", 3986 "traffic class (-1 means none)"); 3987 3988 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txcsum", CTLFLAG_RD, 3989 &txq->txcsum, "# of times hardware assisted with checksum"); 3990 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_insertion", 3991 CTLFLAG_RD, &txq->vlan_insertion, 3992 "# of times hardware inserted 802.1Q tag"); 3993 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "tso_wrs", CTLFLAG_RD, 3994 &txq->tso_wrs, "# of TSO work requests"); 3995 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "imm_wrs", CTLFLAG_RD, 3996 &txq->imm_wrs, "# of work requests with immediate data"); 3997 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "sgl_wrs", CTLFLAG_RD, 3998 &txq->sgl_wrs, "# of work requests with direct SGL"); 3999 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkt_wrs", CTLFLAG_RD, 4000 &txq->txpkt_wrs, "# of txpkt work requests (one pkt/WR)"); 4001 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_wrs", 4002 CTLFLAG_RD, &txq->txpkts0_wrs, 4003 "# of txpkts (type 0) work requests"); 4004 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_wrs", 4005 CTLFLAG_RD, &txq->txpkts1_wrs, 4006 "# of txpkts (type 1) work requests"); 4007 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_pkts", 4008 CTLFLAG_RD, &txq->txpkts0_pkts, 4009 "# of frames tx'd using type0 txpkts work requests"); 4010 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_pkts", 4011 CTLFLAG_RD, &txq->txpkts1_pkts, 4012 "# of frames tx'd using type1 txpkts work requests"); 4013 4014 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_enqueues", 4015 CTLFLAG_RD, &txq->r->enqueues, 4016 "# of enqueues to the mp_ring for this queue"); 4017 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_drops", 4018 CTLFLAG_RD, &txq->r->drops, 4019 "# of drops in the mp_ring for this queue"); 4020 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_starts", 4021 CTLFLAG_RD, &txq->r->starts, 4022 "# of normal consumer starts in the mp_ring for this queue"); 4023 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_stalls", 4024 CTLFLAG_RD, &txq->r->stalls, 4025 "# of consumer stalls in the mp_ring for this queue"); 4026 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_restarts", 4027 CTLFLAG_RD, &txq->r->restarts, 4028 "# of consumer restarts in the mp_ring for this queue"); 4029 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_abdications", 4030 CTLFLAG_RD, &txq->r->abdications, 4031 "# of consumer abdications in the mp_ring for this queue"); 4032 4033 return (0); 4034 } 4035 4036 static int 4037 free_txq(struct vi_info *vi, struct sge_txq *txq) 4038 { 4039 int rc; 4040 struct adapter *sc = vi->pi->adapter; 4041 struct sge_eq *eq = &txq->eq; 4042 4043 rc = free_eq(sc, eq); 4044 if (rc) 4045 return (rc); 4046 4047 sglist_free(txq->gl); 4048 free(txq->sdesc, M_CXGBE); 4049 mp_ring_free(txq->r); 4050 4051 bzero(txq, sizeof(*txq)); 4052 return (0); 4053 } 4054 4055 static void 4056 oneseg_dma_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error) 4057 { 4058 bus_addr_t *ba = arg; 4059 4060 KASSERT(nseg == 1, 4061 ("%s meant for single segment mappings only.", __func__)); 4062 4063 *ba = error ? 0 : segs->ds_addr; 4064 } 4065 4066 static inline void 4067 ring_fl_db(struct adapter *sc, struct sge_fl *fl) 4068 { 4069 uint32_t n, v; 4070 4071 n = IDXDIFF(fl->pidx / 8, fl->dbidx, fl->sidx); 4072 MPASS(n > 0); 4073 4074 wmb(); 4075 v = fl->dbval | V_PIDX(n); 4076 if (fl->udb) 4077 *fl->udb = htole32(v); 4078 else 4079 t4_write_reg(sc, sc->sge_kdoorbell_reg, v); 4080 IDXINCR(fl->dbidx, n, fl->sidx); 4081 } 4082 4083 /* 4084 * Fills up the freelist by allocating up to 'n' buffers. Buffers that are 4085 * recycled do not count towards this allocation budget. 4086 * 4087 * Returns non-zero to indicate that this freelist should be added to the list 4088 * of starving freelists. 4089 */ 4090 static int 4091 refill_fl(struct adapter *sc, struct sge_fl *fl, int n) 4092 { 4093 __be64 *d; 4094 struct fl_sdesc *sd; 4095 uintptr_t pa; 4096 caddr_t cl; 4097 struct cluster_layout *cll; 4098 struct sw_zone_info *swz; 4099 struct cluster_metadata *clm; 4100 uint16_t max_pidx; 4101 uint16_t hw_cidx = fl->hw_cidx; /* stable snapshot */ 4102 4103 FL_LOCK_ASSERT_OWNED(fl); 4104 4105 /* 4106 * We always stop at the beginning of the hardware descriptor that's just 4107 * before the one with the hw cidx. This is to avoid hw pidx = hw cidx, 4108 * which would mean an empty freelist to the chip. 4109 */ 4110 max_pidx = __predict_false(hw_cidx == 0) ? fl->sidx - 1 : hw_cidx - 1; 4111 if (fl->pidx == max_pidx * 8) 4112 return (0); 4113 4114 d = &fl->desc[fl->pidx]; 4115 sd = &fl->sdesc[fl->pidx]; 4116 cll = &fl->cll_def; /* default layout */ 4117 swz = &sc->sge.sw_zone_info[cll->zidx]; 4118 4119 while (n > 0) { 4120 4121 if (sd->cl != NULL) { 4122 4123 if (sd->nmbuf == 0) { 4124 /* 4125 * Fast recycle without involving any atomics on 4126 * the cluster's metadata (if the cluster has 4127 * metadata). This happens when all frames 4128 * received in the cluster were small enough to 4129 * fit within a single mbuf each. 4130 */ 4131 fl->cl_fast_recycled++; 4132 #ifdef INVARIANTS 4133 clm = cl_metadata(sc, fl, &sd->cll, sd->cl); 4134 if (clm != NULL) 4135 MPASS(clm->refcount == 1); 4136 #endif 4137 goto recycled_fast; 4138 } 4139 4140 /* 4141 * Cluster is guaranteed to have metadata. Clusters 4142 * without metadata always take the fast recycle path 4143 * when they're recycled. 4144 */ 4145 clm = cl_metadata(sc, fl, &sd->cll, sd->cl); 4146 MPASS(clm != NULL); 4147 4148 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) { 4149 fl->cl_recycled++; 4150 counter_u64_add(extfree_rels, 1); 4151 goto recycled; 4152 } 4153 sd->cl = NULL; /* gave up my reference */ 4154 } 4155 MPASS(sd->cl == NULL); 4156 alloc: 4157 cl = uma_zalloc(swz->zone, M_NOWAIT); 4158 if (__predict_false(cl == NULL)) { 4159 if (cll == &fl->cll_alt || fl->cll_alt.zidx == -1 || 4160 fl->cll_def.zidx == fl->cll_alt.zidx) 4161 break; 4162 4163 /* fall back to the safe zone */ 4164 cll = &fl->cll_alt; 4165 swz = &sc->sge.sw_zone_info[cll->zidx]; 4166 goto alloc; 4167 } 4168 fl->cl_allocated++; 4169 n--; 4170 4171 pa = pmap_kextract((vm_offset_t)cl); 4172 pa += cll->region1; 4173 sd->cl = cl; 4174 sd->cll = *cll; 4175 *d = htobe64(pa | cll->hwidx); 4176 clm = cl_metadata(sc, fl, cll, cl); 4177 if (clm != NULL) { 4178 recycled: 4179 #ifdef INVARIANTS 4180 clm->sd = sd; 4181 #endif 4182 clm->refcount = 1; 4183 } 4184 sd->nmbuf = 0; 4185 recycled_fast: 4186 d++; 4187 sd++; 4188 if (__predict_false(++fl->pidx % 8 == 0)) { 4189 uint16_t pidx = fl->pidx / 8; 4190 4191 if (__predict_false(pidx == fl->sidx)) { 4192 fl->pidx = 0; 4193 pidx = 0; 4194 sd = fl->sdesc; 4195 d = fl->desc; 4196 } 4197 if (pidx == max_pidx) 4198 break; 4199 4200 if (IDXDIFF(pidx, fl->dbidx, fl->sidx) >= 4) 4201 ring_fl_db(sc, fl); 4202 } 4203 } 4204 4205 if (fl->pidx / 8 != fl->dbidx) 4206 ring_fl_db(sc, fl); 4207 4208 return (FL_RUNNING_LOW(fl) && !(fl->flags & FL_STARVING)); 4209 } 4210 4211 /* 4212 * Attempt to refill all starving freelists. 4213 */ 4214 static void 4215 refill_sfl(void *arg) 4216 { 4217 struct adapter *sc = arg; 4218 struct sge_fl *fl, *fl_temp; 4219 4220 mtx_assert(&sc->sfl_lock, MA_OWNED); 4221 TAILQ_FOREACH_SAFE(fl, &sc->sfl, link, fl_temp) { 4222 FL_LOCK(fl); 4223 refill_fl(sc, fl, 64); 4224 if (FL_NOT_RUNNING_LOW(fl) || fl->flags & FL_DOOMED) { 4225 TAILQ_REMOVE(&sc->sfl, fl, link); 4226 fl->flags &= ~FL_STARVING; 4227 } 4228 FL_UNLOCK(fl); 4229 } 4230 4231 if (!TAILQ_EMPTY(&sc->sfl)) 4232 callout_schedule(&sc->sfl_callout, hz / 5); 4233 } 4234 4235 static int 4236 alloc_fl_sdesc(struct sge_fl *fl) 4237 { 4238 4239 fl->sdesc = malloc(fl->sidx * 8 * sizeof(struct fl_sdesc), M_CXGBE, 4240 M_ZERO | M_WAITOK); 4241 4242 return (0); 4243 } 4244 4245 static void 4246 free_fl_sdesc(struct adapter *sc, struct sge_fl *fl) 4247 { 4248 struct fl_sdesc *sd; 4249 struct cluster_metadata *clm; 4250 struct cluster_layout *cll; 4251 int i; 4252 4253 sd = fl->sdesc; 4254 for (i = 0; i < fl->sidx * 8; i++, sd++) { 4255 if (sd->cl == NULL) 4256 continue; 4257 4258 cll = &sd->cll; 4259 clm = cl_metadata(sc, fl, cll, sd->cl); 4260 if (sd->nmbuf == 0) 4261 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl); 4262 else if (clm && atomic_fetchadd_int(&clm->refcount, -1) == 1) { 4263 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl); 4264 counter_u64_add(extfree_rels, 1); 4265 } 4266 sd->cl = NULL; 4267 } 4268 4269 free(fl->sdesc, M_CXGBE); 4270 fl->sdesc = NULL; 4271 } 4272 4273 static inline void 4274 get_pkt_gl(struct mbuf *m, struct sglist *gl) 4275 { 4276 int rc; 4277 4278 M_ASSERTPKTHDR(m); 4279 4280 sglist_reset(gl); 4281 rc = sglist_append_mbuf(gl, m); 4282 if (__predict_false(rc != 0)) { 4283 panic("%s: mbuf %p (%d segs) was vetted earlier but now fails " 4284 "with %d.", __func__, m, mbuf_nsegs(m), rc); 4285 } 4286 4287 KASSERT(gl->sg_nseg == mbuf_nsegs(m), 4288 ("%s: nsegs changed for mbuf %p from %d to %d", __func__, m, 4289 mbuf_nsegs(m), gl->sg_nseg)); 4290 KASSERT(gl->sg_nseg > 0 && 4291 gl->sg_nseg <= (needs_tso(m) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS), 4292 ("%s: %d segments, should have been 1 <= nsegs <= %d", __func__, 4293 gl->sg_nseg, needs_tso(m) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS)); 4294 } 4295 4296 /* 4297 * len16 for a txpkt WR with a GL. Includes the firmware work request header. 4298 */ 4299 static inline u_int 4300 txpkt_len16(u_int nsegs, u_int tso) 4301 { 4302 u_int n; 4303 4304 MPASS(nsegs > 0); 4305 4306 nsegs--; /* first segment is part of ulptx_sgl */ 4307 n = sizeof(struct fw_eth_tx_pkt_wr) + sizeof(struct cpl_tx_pkt_core) + 4308 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 4309 if (tso) 4310 n += sizeof(struct cpl_tx_pkt_lso_core); 4311 4312 return (howmany(n, 16)); 4313 } 4314 4315 /* 4316 * len16 for a txpkt_vm WR with a GL. Includes the firmware work 4317 * request header. 4318 */ 4319 static inline u_int 4320 txpkt_vm_len16(u_int nsegs, u_int tso) 4321 { 4322 u_int n; 4323 4324 MPASS(nsegs > 0); 4325 4326 nsegs--; /* first segment is part of ulptx_sgl */ 4327 n = sizeof(struct fw_eth_tx_pkt_vm_wr) + 4328 sizeof(struct cpl_tx_pkt_core) + 4329 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 4330 if (tso) 4331 n += sizeof(struct cpl_tx_pkt_lso_core); 4332 4333 return (howmany(n, 16)); 4334 } 4335 4336 /* 4337 * len16 for a txpkts type 0 WR with a GL. Does not include the firmware work 4338 * request header. 4339 */ 4340 static inline u_int 4341 txpkts0_len16(u_int nsegs) 4342 { 4343 u_int n; 4344 4345 MPASS(nsegs > 0); 4346 4347 nsegs--; /* first segment is part of ulptx_sgl */ 4348 n = sizeof(struct ulp_txpkt) + sizeof(struct ulptx_idata) + 4349 sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl) + 4350 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 4351 4352 return (howmany(n, 16)); 4353 } 4354 4355 /* 4356 * len16 for a txpkts type 1 WR with a GL. Does not include the firmware work 4357 * request header. 4358 */ 4359 static inline u_int 4360 txpkts1_len16(void) 4361 { 4362 u_int n; 4363 4364 n = sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl); 4365 4366 return (howmany(n, 16)); 4367 } 4368 4369 static inline u_int 4370 imm_payload(u_int ndesc) 4371 { 4372 u_int n; 4373 4374 n = ndesc * EQ_ESIZE - sizeof(struct fw_eth_tx_pkt_wr) - 4375 sizeof(struct cpl_tx_pkt_core); 4376 4377 return (n); 4378 } 4379 4380 /* 4381 * Write a VM txpkt WR for this packet to the hardware descriptors, update the 4382 * software descriptor, and advance the pidx. It is guaranteed that enough 4383 * descriptors are available. 4384 * 4385 * The return value is the # of hardware descriptors used. 4386 */ 4387 static u_int 4388 write_txpkt_vm_wr(struct adapter *sc, struct sge_txq *txq, 4389 struct fw_eth_tx_pkt_vm_wr *wr, struct mbuf *m0, u_int available) 4390 { 4391 struct sge_eq *eq = &txq->eq; 4392 struct tx_sdesc *txsd; 4393 struct cpl_tx_pkt_core *cpl; 4394 uint32_t ctrl; /* used in many unrelated places */ 4395 uint64_t ctrl1; 4396 int csum_type, len16, ndesc, pktlen, nsegs; 4397 caddr_t dst; 4398 4399 TXQ_LOCK_ASSERT_OWNED(txq); 4400 M_ASSERTPKTHDR(m0); 4401 MPASS(available > 0 && available < eq->sidx); 4402 4403 len16 = mbuf_len16(m0); 4404 nsegs = mbuf_nsegs(m0); 4405 pktlen = m0->m_pkthdr.len; 4406 ctrl = sizeof(struct cpl_tx_pkt_core); 4407 if (needs_tso(m0)) 4408 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 4409 ndesc = howmany(len16, EQ_ESIZE / 16); 4410 MPASS(ndesc <= available); 4411 4412 /* Firmware work request header */ 4413 MPASS(wr == (void *)&eq->desc[eq->pidx]); 4414 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_VM_WR) | 4415 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl)); 4416 4417 ctrl = V_FW_WR_LEN16(len16); 4418 wr->equiq_to_len16 = htobe32(ctrl); 4419 wr->r3[0] = 0; 4420 wr->r3[1] = 0; 4421 4422 /* 4423 * Copy over ethmacdst, ethmacsrc, ethtype, and vlantci. 4424 * vlantci is ignored unless the ethtype is 0x8100, so it's 4425 * simpler to always copy it rather than making it 4426 * conditional. Also, it seems that we do not have to set 4427 * vlantci or fake the ethtype when doing VLAN tag insertion. 4428 */ 4429 m_copydata(m0, 0, sizeof(struct ether_header) + 2, wr->ethmacdst); 4430 4431 csum_type = -1; 4432 if (needs_tso(m0)) { 4433 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1); 4434 4435 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 4436 m0->m_pkthdr.l4hlen > 0, 4437 ("%s: mbuf %p needs TSO but missing header lengths", 4438 __func__, m0)); 4439 4440 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE | 4441 F_LSO_LAST_SLICE | V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) 4442 | V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2); 4443 if (m0->m_pkthdr.l2hlen == sizeof(struct ether_vlan_header)) 4444 ctrl |= V_LSO_ETHHDR_LEN(1); 4445 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 4446 ctrl |= F_LSO_IPV6; 4447 4448 lso->lso_ctrl = htobe32(ctrl); 4449 lso->ipid_ofst = htobe16(0); 4450 lso->mss = htobe16(m0->m_pkthdr.tso_segsz); 4451 lso->seqno_offset = htobe32(0); 4452 lso->len = htobe32(pktlen); 4453 4454 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 4455 csum_type = TX_CSUM_TCPIP6; 4456 else 4457 csum_type = TX_CSUM_TCPIP; 4458 4459 cpl = (void *)(lso + 1); 4460 4461 txq->tso_wrs++; 4462 } else { 4463 if (m0->m_pkthdr.csum_flags & CSUM_IP_TCP) 4464 csum_type = TX_CSUM_TCPIP; 4465 else if (m0->m_pkthdr.csum_flags & CSUM_IP_UDP) 4466 csum_type = TX_CSUM_UDPIP; 4467 else if (m0->m_pkthdr.csum_flags & CSUM_IP6_TCP) 4468 csum_type = TX_CSUM_TCPIP6; 4469 else if (m0->m_pkthdr.csum_flags & CSUM_IP6_UDP) 4470 csum_type = TX_CSUM_UDPIP6; 4471 #if defined(INET) 4472 else if (m0->m_pkthdr.csum_flags & CSUM_IP) { 4473 /* 4474 * XXX: The firmware appears to stomp on the 4475 * fragment/flags field of the IP header when 4476 * using TX_CSUM_IP. Fall back to doing 4477 * software checksums. 4478 */ 4479 u_short *sump; 4480 struct mbuf *m; 4481 int offset; 4482 4483 m = m0; 4484 offset = 0; 4485 sump = m_advance(&m, &offset, m0->m_pkthdr.l2hlen + 4486 offsetof(struct ip, ip_sum)); 4487 *sump = in_cksum_skip(m0, m0->m_pkthdr.l2hlen + 4488 m0->m_pkthdr.l3hlen, m0->m_pkthdr.l2hlen); 4489 m0->m_pkthdr.csum_flags &= ~CSUM_IP; 4490 } 4491 #endif 4492 4493 cpl = (void *)(wr + 1); 4494 } 4495 4496 /* Checksum offload */ 4497 ctrl1 = 0; 4498 if (needs_l3_csum(m0) == 0) 4499 ctrl1 |= F_TXPKT_IPCSUM_DIS; 4500 if (csum_type >= 0) { 4501 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0, 4502 ("%s: mbuf %p needs checksum offload but missing header lengths", 4503 __func__, m0)); 4504 4505 if (chip_id(sc) <= CHELSIO_T5) { 4506 ctrl1 |= V_TXPKT_ETHHDR_LEN(m0->m_pkthdr.l2hlen - 4507 ETHER_HDR_LEN); 4508 } else { 4509 ctrl1 |= V_T6_TXPKT_ETHHDR_LEN(m0->m_pkthdr.l2hlen - 4510 ETHER_HDR_LEN); 4511 } 4512 ctrl1 |= V_TXPKT_IPHDR_LEN(m0->m_pkthdr.l3hlen); 4513 ctrl1 |= V_TXPKT_CSUM_TYPE(csum_type); 4514 } else 4515 ctrl1 |= F_TXPKT_L4CSUM_DIS; 4516 if (m0->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | 4517 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO)) 4518 txq->txcsum++; /* some hardware assistance provided */ 4519 4520 /* VLAN tag insertion */ 4521 if (needs_vlan_insertion(m0)) { 4522 ctrl1 |= F_TXPKT_VLAN_VLD | 4523 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 4524 txq->vlan_insertion++; 4525 } 4526 4527 /* CPL header */ 4528 cpl->ctrl0 = txq->cpl_ctrl0; 4529 cpl->pack = 0; 4530 cpl->len = htobe16(pktlen); 4531 cpl->ctrl1 = htobe64(ctrl1); 4532 4533 /* SGL */ 4534 dst = (void *)(cpl + 1); 4535 4536 /* 4537 * A packet using TSO will use up an entire descriptor for the 4538 * firmware work request header, LSO CPL, and TX_PKT_XT CPL. 4539 * If this descriptor is the last descriptor in the ring, wrap 4540 * around to the front of the ring explicitly for the start of 4541 * the sgl. 4542 */ 4543 if (dst == (void *)&eq->desc[eq->sidx]) { 4544 dst = (void *)&eq->desc[0]; 4545 write_gl_to_txd(txq, m0, &dst, 0); 4546 } else 4547 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx); 4548 txq->sgl_wrs++; 4549 4550 txq->txpkt_wrs++; 4551 4552 txsd = &txq->sdesc[eq->pidx]; 4553 txsd->m = m0; 4554 txsd->desc_used = ndesc; 4555 4556 return (ndesc); 4557 } 4558 4559 /* 4560 * Write a txpkt WR for this packet to the hardware descriptors, update the 4561 * software descriptor, and advance the pidx. It is guaranteed that enough 4562 * descriptors are available. 4563 * 4564 * The return value is the # of hardware descriptors used. 4565 */ 4566 static u_int 4567 write_txpkt_wr(struct sge_txq *txq, struct fw_eth_tx_pkt_wr *wr, 4568 struct mbuf *m0, u_int available) 4569 { 4570 struct sge_eq *eq = &txq->eq; 4571 struct tx_sdesc *txsd; 4572 struct cpl_tx_pkt_core *cpl; 4573 uint32_t ctrl; /* used in many unrelated places */ 4574 uint64_t ctrl1; 4575 int len16, ndesc, pktlen, nsegs; 4576 caddr_t dst; 4577 4578 TXQ_LOCK_ASSERT_OWNED(txq); 4579 M_ASSERTPKTHDR(m0); 4580 MPASS(available > 0 && available < eq->sidx); 4581 4582 len16 = mbuf_len16(m0); 4583 nsegs = mbuf_nsegs(m0); 4584 pktlen = m0->m_pkthdr.len; 4585 ctrl = sizeof(struct cpl_tx_pkt_core); 4586 if (needs_tso(m0)) 4587 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 4588 else if (pktlen <= imm_payload(2) && available >= 2) { 4589 /* Immediate data. Recalculate len16 and set nsegs to 0. */ 4590 ctrl += pktlen; 4591 len16 = howmany(sizeof(struct fw_eth_tx_pkt_wr) + 4592 sizeof(struct cpl_tx_pkt_core) + pktlen, 16); 4593 nsegs = 0; 4594 } 4595 ndesc = howmany(len16, EQ_ESIZE / 16); 4596 MPASS(ndesc <= available); 4597 4598 /* Firmware work request header */ 4599 MPASS(wr == (void *)&eq->desc[eq->pidx]); 4600 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_WR) | 4601 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl)); 4602 4603 ctrl = V_FW_WR_LEN16(len16); 4604 wr->equiq_to_len16 = htobe32(ctrl); 4605 wr->r3 = 0; 4606 4607 if (needs_tso(m0)) { 4608 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1); 4609 4610 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 4611 m0->m_pkthdr.l4hlen > 0, 4612 ("%s: mbuf %p needs TSO but missing header lengths", 4613 __func__, m0)); 4614 4615 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE | 4616 F_LSO_LAST_SLICE | V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) 4617 | V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2); 4618 if (m0->m_pkthdr.l2hlen == sizeof(struct ether_vlan_header)) 4619 ctrl |= V_LSO_ETHHDR_LEN(1); 4620 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 4621 ctrl |= F_LSO_IPV6; 4622 4623 lso->lso_ctrl = htobe32(ctrl); 4624 lso->ipid_ofst = htobe16(0); 4625 lso->mss = htobe16(m0->m_pkthdr.tso_segsz); 4626 lso->seqno_offset = htobe32(0); 4627 lso->len = htobe32(pktlen); 4628 4629 cpl = (void *)(lso + 1); 4630 4631 txq->tso_wrs++; 4632 } else 4633 cpl = (void *)(wr + 1); 4634 4635 /* Checksum offload */ 4636 ctrl1 = 0; 4637 if (needs_l3_csum(m0) == 0) 4638 ctrl1 |= F_TXPKT_IPCSUM_DIS; 4639 if (needs_l4_csum(m0) == 0) 4640 ctrl1 |= F_TXPKT_L4CSUM_DIS; 4641 if (m0->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | 4642 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO)) 4643 txq->txcsum++; /* some hardware assistance provided */ 4644 4645 /* VLAN tag insertion */ 4646 if (needs_vlan_insertion(m0)) { 4647 ctrl1 |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 4648 txq->vlan_insertion++; 4649 } 4650 4651 /* CPL header */ 4652 cpl->ctrl0 = txq->cpl_ctrl0; 4653 cpl->pack = 0; 4654 cpl->len = htobe16(pktlen); 4655 cpl->ctrl1 = htobe64(ctrl1); 4656 4657 /* SGL */ 4658 dst = (void *)(cpl + 1); 4659 if (nsegs > 0) { 4660 4661 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx); 4662 txq->sgl_wrs++; 4663 } else { 4664 struct mbuf *m; 4665 4666 for (m = m0; m != NULL; m = m->m_next) { 4667 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len); 4668 #ifdef INVARIANTS 4669 pktlen -= m->m_len; 4670 #endif 4671 } 4672 #ifdef INVARIANTS 4673 KASSERT(pktlen == 0, ("%s: %d bytes left.", __func__, pktlen)); 4674 #endif 4675 txq->imm_wrs++; 4676 } 4677 4678 txq->txpkt_wrs++; 4679 4680 txsd = &txq->sdesc[eq->pidx]; 4681 txsd->m = m0; 4682 txsd->desc_used = ndesc; 4683 4684 return (ndesc); 4685 } 4686 4687 static int 4688 try_txpkts(struct mbuf *m, struct mbuf *n, struct txpkts *txp, u_int available) 4689 { 4690 u_int needed, nsegs1, nsegs2, l1, l2; 4691 4692 if (cannot_use_txpkts(m) || cannot_use_txpkts(n)) 4693 return (1); 4694 4695 nsegs1 = mbuf_nsegs(m); 4696 nsegs2 = mbuf_nsegs(n); 4697 if (nsegs1 + nsegs2 == 2) { 4698 txp->wr_type = 1; 4699 l1 = l2 = txpkts1_len16(); 4700 } else { 4701 txp->wr_type = 0; 4702 l1 = txpkts0_len16(nsegs1); 4703 l2 = txpkts0_len16(nsegs2); 4704 } 4705 txp->len16 = howmany(sizeof(struct fw_eth_tx_pkts_wr), 16) + l1 + l2; 4706 needed = howmany(txp->len16, EQ_ESIZE / 16); 4707 if (needed > SGE_MAX_WR_NDESC || needed > available) 4708 return (1); 4709 4710 txp->plen = m->m_pkthdr.len + n->m_pkthdr.len; 4711 if (txp->plen > 65535) 4712 return (1); 4713 4714 txp->npkt = 2; 4715 set_mbuf_len16(m, l1); 4716 set_mbuf_len16(n, l2); 4717 4718 return (0); 4719 } 4720 4721 static int 4722 add_to_txpkts(struct mbuf *m, struct txpkts *txp, u_int available) 4723 { 4724 u_int plen, len16, needed, nsegs; 4725 4726 MPASS(txp->wr_type == 0 || txp->wr_type == 1); 4727 4728 nsegs = mbuf_nsegs(m); 4729 if (needs_tso(m) || (txp->wr_type == 1 && nsegs != 1)) 4730 return (1); 4731 4732 plen = txp->plen + m->m_pkthdr.len; 4733 if (plen > 65535) 4734 return (1); 4735 4736 if (txp->wr_type == 0) 4737 len16 = txpkts0_len16(nsegs); 4738 else 4739 len16 = txpkts1_len16(); 4740 needed = howmany(txp->len16 + len16, EQ_ESIZE / 16); 4741 if (needed > SGE_MAX_WR_NDESC || needed > available) 4742 return (1); 4743 4744 txp->npkt++; 4745 txp->plen = plen; 4746 txp->len16 += len16; 4747 set_mbuf_len16(m, len16); 4748 4749 return (0); 4750 } 4751 4752 /* 4753 * Write a txpkts WR for the packets in txp to the hardware descriptors, update 4754 * the software descriptor, and advance the pidx. It is guaranteed that enough 4755 * descriptors are available. 4756 * 4757 * The return value is the # of hardware descriptors used. 4758 */ 4759 static u_int 4760 write_txpkts_wr(struct sge_txq *txq, struct fw_eth_tx_pkts_wr *wr, 4761 struct mbuf *m0, const struct txpkts *txp, u_int available) 4762 { 4763 struct sge_eq *eq = &txq->eq; 4764 struct tx_sdesc *txsd; 4765 struct cpl_tx_pkt_core *cpl; 4766 uint32_t ctrl; 4767 uint64_t ctrl1; 4768 int ndesc, checkwrap; 4769 struct mbuf *m; 4770 void *flitp; 4771 4772 TXQ_LOCK_ASSERT_OWNED(txq); 4773 MPASS(txp->npkt > 0); 4774 MPASS(txp->plen < 65536); 4775 MPASS(m0 != NULL); 4776 MPASS(m0->m_nextpkt != NULL); 4777 MPASS(txp->len16 <= howmany(SGE_MAX_WR_LEN, 16)); 4778 MPASS(available > 0 && available < eq->sidx); 4779 4780 ndesc = howmany(txp->len16, EQ_ESIZE / 16); 4781 MPASS(ndesc <= available); 4782 4783 MPASS(wr == (void *)&eq->desc[eq->pidx]); 4784 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR)); 4785 ctrl = V_FW_WR_LEN16(txp->len16); 4786 wr->equiq_to_len16 = htobe32(ctrl); 4787 wr->plen = htobe16(txp->plen); 4788 wr->npkt = txp->npkt; 4789 wr->r3 = 0; 4790 wr->type = txp->wr_type; 4791 flitp = wr + 1; 4792 4793 /* 4794 * At this point we are 16B into a hardware descriptor. If checkwrap is 4795 * set then we know the WR is going to wrap around somewhere. We'll 4796 * check for that at appropriate points. 4797 */ 4798 checkwrap = eq->sidx - ndesc < eq->pidx; 4799 for (m = m0; m != NULL; m = m->m_nextpkt) { 4800 if (txp->wr_type == 0) { 4801 struct ulp_txpkt *ulpmc; 4802 struct ulptx_idata *ulpsc; 4803 4804 /* ULP master command */ 4805 ulpmc = flitp; 4806 ulpmc->cmd_dest = htobe32(V_ULPTX_CMD(ULP_TX_PKT) | 4807 V_ULP_TXPKT_DEST(0) | V_ULP_TXPKT_FID(eq->iqid)); 4808 ulpmc->len = htobe32(mbuf_len16(m)); 4809 4810 /* ULP subcommand */ 4811 ulpsc = (void *)(ulpmc + 1); 4812 ulpsc->cmd_more = htobe32(V_ULPTX_CMD(ULP_TX_SC_IMM) | 4813 F_ULP_TX_SC_MORE); 4814 ulpsc->len = htobe32(sizeof(struct cpl_tx_pkt_core)); 4815 4816 cpl = (void *)(ulpsc + 1); 4817 if (checkwrap && 4818 (uintptr_t)cpl == (uintptr_t)&eq->desc[eq->sidx]) 4819 cpl = (void *)&eq->desc[0]; 4820 } else { 4821 cpl = flitp; 4822 } 4823 4824 /* Checksum offload */ 4825 ctrl1 = 0; 4826 if (needs_l3_csum(m) == 0) 4827 ctrl1 |= F_TXPKT_IPCSUM_DIS; 4828 if (needs_l4_csum(m) == 0) 4829 ctrl1 |= F_TXPKT_L4CSUM_DIS; 4830 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | 4831 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO)) 4832 txq->txcsum++; /* some hardware assistance provided */ 4833 4834 /* VLAN tag insertion */ 4835 if (needs_vlan_insertion(m)) { 4836 ctrl1 |= F_TXPKT_VLAN_VLD | 4837 V_TXPKT_VLAN(m->m_pkthdr.ether_vtag); 4838 txq->vlan_insertion++; 4839 } 4840 4841 /* CPL header */ 4842 cpl->ctrl0 = txq->cpl_ctrl0; 4843 cpl->pack = 0; 4844 cpl->len = htobe16(m->m_pkthdr.len); 4845 cpl->ctrl1 = htobe64(ctrl1); 4846 4847 flitp = cpl + 1; 4848 if (checkwrap && 4849 (uintptr_t)flitp == (uintptr_t)&eq->desc[eq->sidx]) 4850 flitp = (void *)&eq->desc[0]; 4851 4852 write_gl_to_txd(txq, m, (caddr_t *)(&flitp), checkwrap); 4853 4854 } 4855 4856 if (txp->wr_type == 0) { 4857 txq->txpkts0_pkts += txp->npkt; 4858 txq->txpkts0_wrs++; 4859 } else { 4860 txq->txpkts1_pkts += txp->npkt; 4861 txq->txpkts1_wrs++; 4862 } 4863 4864 txsd = &txq->sdesc[eq->pidx]; 4865 txsd->m = m0; 4866 txsd->desc_used = ndesc; 4867 4868 return (ndesc); 4869 } 4870 4871 /* 4872 * If the SGL ends on an address that is not 16 byte aligned, this function will 4873 * add a 0 filled flit at the end. 4874 */ 4875 static void 4876 write_gl_to_txd(struct sge_txq *txq, struct mbuf *m, caddr_t *to, int checkwrap) 4877 { 4878 struct sge_eq *eq = &txq->eq; 4879 struct sglist *gl = txq->gl; 4880 struct sglist_seg *seg; 4881 __be64 *flitp, *wrap; 4882 struct ulptx_sgl *usgl; 4883 int i, nflits, nsegs; 4884 4885 KASSERT(((uintptr_t)(*to) & 0xf) == 0, 4886 ("%s: SGL must start at a 16 byte boundary: %p", __func__, *to)); 4887 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]); 4888 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]); 4889 4890 get_pkt_gl(m, gl); 4891 nsegs = gl->sg_nseg; 4892 MPASS(nsegs > 0); 4893 4894 nflits = (3 * (nsegs - 1)) / 2 + ((nsegs - 1) & 1) + 2; 4895 flitp = (__be64 *)(*to); 4896 wrap = (__be64 *)(&eq->desc[eq->sidx]); 4897 seg = &gl->sg_segs[0]; 4898 usgl = (void *)flitp; 4899 4900 /* 4901 * We start at a 16 byte boundary somewhere inside the tx descriptor 4902 * ring, so we're at least 16 bytes away from the status page. There is 4903 * no chance of a wrap around in the middle of usgl (which is 16 bytes). 4904 */ 4905 4906 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 4907 V_ULPTX_NSGE(nsegs)); 4908 usgl->len0 = htobe32(seg->ss_len); 4909 usgl->addr0 = htobe64(seg->ss_paddr); 4910 seg++; 4911 4912 if (checkwrap == 0 || (uintptr_t)(flitp + nflits) <= (uintptr_t)wrap) { 4913 4914 /* Won't wrap around at all */ 4915 4916 for (i = 0; i < nsegs - 1; i++, seg++) { 4917 usgl->sge[i / 2].len[i & 1] = htobe32(seg->ss_len); 4918 usgl->sge[i / 2].addr[i & 1] = htobe64(seg->ss_paddr); 4919 } 4920 if (i & 1) 4921 usgl->sge[i / 2].len[1] = htobe32(0); 4922 flitp += nflits; 4923 } else { 4924 4925 /* Will wrap somewhere in the rest of the SGL */ 4926 4927 /* 2 flits already written, write the rest flit by flit */ 4928 flitp = (void *)(usgl + 1); 4929 for (i = 0; i < nflits - 2; i++) { 4930 if (flitp == wrap) 4931 flitp = (void *)eq->desc; 4932 *flitp++ = get_flit(seg, nsegs - 1, i); 4933 } 4934 } 4935 4936 if (nflits & 1) { 4937 MPASS(((uintptr_t)flitp) & 0xf); 4938 *flitp++ = 0; 4939 } 4940 4941 MPASS((((uintptr_t)flitp) & 0xf) == 0); 4942 if (__predict_false(flitp == wrap)) 4943 *to = (void *)eq->desc; 4944 else 4945 *to = (void *)flitp; 4946 } 4947 4948 static inline void 4949 copy_to_txd(struct sge_eq *eq, caddr_t from, caddr_t *to, int len) 4950 { 4951 4952 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]); 4953 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]); 4954 4955 if (__predict_true((uintptr_t)(*to) + len <= 4956 (uintptr_t)&eq->desc[eq->sidx])) { 4957 bcopy(from, *to, len); 4958 (*to) += len; 4959 } else { 4960 int portion = (uintptr_t)&eq->desc[eq->sidx] - (uintptr_t)(*to); 4961 4962 bcopy(from, *to, portion); 4963 from += portion; 4964 portion = len - portion; /* remaining */ 4965 bcopy(from, (void *)eq->desc, portion); 4966 (*to) = (caddr_t)eq->desc + portion; 4967 } 4968 } 4969 4970 static inline void 4971 ring_eq_db(struct adapter *sc, struct sge_eq *eq, u_int n) 4972 { 4973 u_int db; 4974 4975 MPASS(n > 0); 4976 4977 db = eq->doorbells; 4978 if (n > 1) 4979 clrbit(&db, DOORBELL_WCWR); 4980 wmb(); 4981 4982 switch (ffs(db) - 1) { 4983 case DOORBELL_UDB: 4984 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n)); 4985 break; 4986 4987 case DOORBELL_WCWR: { 4988 volatile uint64_t *dst, *src; 4989 int i; 4990 4991 /* 4992 * Queues whose 128B doorbell segment fits in the page do not 4993 * use relative qid (udb_qid is always 0). Only queues with 4994 * doorbell segments can do WCWR. 4995 */ 4996 KASSERT(eq->udb_qid == 0 && n == 1, 4997 ("%s: inappropriate doorbell (0x%x, %d, %d) for eq %p", 4998 __func__, eq->doorbells, n, eq->dbidx, eq)); 4999 5000 dst = (volatile void *)((uintptr_t)eq->udb + UDBS_WR_OFFSET - 5001 UDBS_DB_OFFSET); 5002 i = eq->dbidx; 5003 src = (void *)&eq->desc[i]; 5004 while (src != (void *)&eq->desc[i + 1]) 5005 *dst++ = *src++; 5006 wmb(); 5007 break; 5008 } 5009 5010 case DOORBELL_UDBWC: 5011 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n)); 5012 wmb(); 5013 break; 5014 5015 case DOORBELL_KDB: 5016 t4_write_reg(sc, sc->sge_kdoorbell_reg, 5017 V_QID(eq->cntxt_id) | V_PIDX(n)); 5018 break; 5019 } 5020 5021 IDXINCR(eq->dbidx, n, eq->sidx); 5022 } 5023 5024 static inline u_int 5025 reclaimable_tx_desc(struct sge_eq *eq) 5026 { 5027 uint16_t hw_cidx; 5028 5029 hw_cidx = read_hw_cidx(eq); 5030 return (IDXDIFF(hw_cidx, eq->cidx, eq->sidx)); 5031 } 5032 5033 static inline u_int 5034 total_available_tx_desc(struct sge_eq *eq) 5035 { 5036 uint16_t hw_cidx, pidx; 5037 5038 hw_cidx = read_hw_cidx(eq); 5039 pidx = eq->pidx; 5040 5041 if (pidx == hw_cidx) 5042 return (eq->sidx - 1); 5043 else 5044 return (IDXDIFF(hw_cidx, pidx, eq->sidx) - 1); 5045 } 5046 5047 static inline uint16_t 5048 read_hw_cidx(struct sge_eq *eq) 5049 { 5050 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx]; 5051 uint16_t cidx = spg->cidx; /* stable snapshot */ 5052 5053 return (be16toh(cidx)); 5054 } 5055 5056 /* 5057 * Reclaim 'n' descriptors approximately. 5058 */ 5059 static u_int 5060 reclaim_tx_descs(struct sge_txq *txq, u_int n) 5061 { 5062 struct tx_sdesc *txsd; 5063 struct sge_eq *eq = &txq->eq; 5064 u_int can_reclaim, reclaimed; 5065 5066 TXQ_LOCK_ASSERT_OWNED(txq); 5067 MPASS(n > 0); 5068 5069 reclaimed = 0; 5070 can_reclaim = reclaimable_tx_desc(eq); 5071 while (can_reclaim && reclaimed < n) { 5072 int ndesc; 5073 struct mbuf *m, *nextpkt; 5074 5075 txsd = &txq->sdesc[eq->cidx]; 5076 ndesc = txsd->desc_used; 5077 5078 /* Firmware doesn't return "partial" credits. */ 5079 KASSERT(can_reclaim >= ndesc, 5080 ("%s: unexpected number of credits: %d, %d", 5081 __func__, can_reclaim, ndesc)); 5082 5083 for (m = txsd->m; m != NULL; m = nextpkt) { 5084 nextpkt = m->m_nextpkt; 5085 m->m_nextpkt = NULL; 5086 m_freem(m); 5087 } 5088 reclaimed += ndesc; 5089 can_reclaim -= ndesc; 5090 IDXINCR(eq->cidx, ndesc, eq->sidx); 5091 } 5092 5093 return (reclaimed); 5094 } 5095 5096 static void 5097 tx_reclaim(void *arg, int n) 5098 { 5099 struct sge_txq *txq = arg; 5100 struct sge_eq *eq = &txq->eq; 5101 5102 do { 5103 if (TXQ_TRYLOCK(txq) == 0) 5104 break; 5105 n = reclaim_tx_descs(txq, 32); 5106 if (eq->cidx == eq->pidx) 5107 eq->equeqidx = eq->pidx; 5108 TXQ_UNLOCK(txq); 5109 } while (n > 0); 5110 } 5111 5112 static __be64 5113 get_flit(struct sglist_seg *segs, int nsegs, int idx) 5114 { 5115 int i = (idx / 3) * 2; 5116 5117 switch (idx % 3) { 5118 case 0: { 5119 uint64_t rc; 5120 5121 rc = (uint64_t)segs[i].ss_len << 32; 5122 if (i + 1 < nsegs) 5123 rc |= (uint64_t)(segs[i + 1].ss_len); 5124 5125 return (htobe64(rc)); 5126 } 5127 case 1: 5128 return (htobe64(segs[i].ss_paddr)); 5129 case 2: 5130 return (htobe64(segs[i + 1].ss_paddr)); 5131 } 5132 5133 return (0); 5134 } 5135 5136 static void 5137 find_best_refill_source(struct adapter *sc, struct sge_fl *fl, int maxp) 5138 { 5139 int8_t zidx, hwidx, idx; 5140 uint16_t region1, region3; 5141 int spare, spare_needed, n; 5142 struct sw_zone_info *swz; 5143 struct hw_buf_info *hwb, *hwb_list = &sc->sge.hw_buf_info[0]; 5144 5145 /* 5146 * Buffer Packing: Look for PAGE_SIZE or larger zone which has a bufsize 5147 * large enough for the max payload and cluster metadata. Otherwise 5148 * settle for the largest bufsize that leaves enough room in the cluster 5149 * for metadata. 5150 * 5151 * Without buffer packing: Look for the smallest zone which has a 5152 * bufsize large enough for the max payload. Settle for the largest 5153 * bufsize available if there's nothing big enough for max payload. 5154 */ 5155 spare_needed = fl->flags & FL_BUF_PACKING ? CL_METADATA_SIZE : 0; 5156 swz = &sc->sge.sw_zone_info[0]; 5157 hwidx = -1; 5158 for (zidx = 0; zidx < SW_ZONE_SIZES; zidx++, swz++) { 5159 if (swz->size > largest_rx_cluster) { 5160 if (__predict_true(hwidx != -1)) 5161 break; 5162 5163 /* 5164 * This is a misconfiguration. largest_rx_cluster is 5165 * preventing us from finding a refill source. See 5166 * dev.t5nex.<n>.buffer_sizes to figure out why. 5167 */ 5168 device_printf(sc->dev, "largest_rx_cluster=%u leaves no" 5169 " refill source for fl %p (dma %u). Ignored.\n", 5170 largest_rx_cluster, fl, maxp); 5171 } 5172 for (idx = swz->head_hwidx; idx != -1; idx = hwb->next) { 5173 hwb = &hwb_list[idx]; 5174 spare = swz->size - hwb->size; 5175 if (spare < spare_needed) 5176 continue; 5177 5178 hwidx = idx; /* best option so far */ 5179 if (hwb->size >= maxp) { 5180 5181 if ((fl->flags & FL_BUF_PACKING) == 0) 5182 goto done; /* stop looking (not packing) */ 5183 5184 if (swz->size >= safest_rx_cluster) 5185 goto done; /* stop looking (packing) */ 5186 } 5187 break; /* keep looking, next zone */ 5188 } 5189 } 5190 done: 5191 /* A usable hwidx has been located. */ 5192 MPASS(hwidx != -1); 5193 hwb = &hwb_list[hwidx]; 5194 zidx = hwb->zidx; 5195 swz = &sc->sge.sw_zone_info[zidx]; 5196 region1 = 0; 5197 region3 = swz->size - hwb->size; 5198 5199 /* 5200 * Stay within this zone and see if there is a better match when mbuf 5201 * inlining is allowed. Remember that the hwidx's are sorted in 5202 * decreasing order of size (so in increasing order of spare area). 5203 */ 5204 for (idx = hwidx; idx != -1; idx = hwb->next) { 5205 hwb = &hwb_list[idx]; 5206 spare = swz->size - hwb->size; 5207 5208 if (allow_mbufs_in_cluster == 0 || hwb->size < maxp) 5209 break; 5210 5211 /* 5212 * Do not inline mbufs if doing so would violate the pad/pack 5213 * boundary alignment requirement. 5214 */ 5215 if (fl_pad && (MSIZE % sc->params.sge.pad_boundary) != 0) 5216 continue; 5217 if (fl->flags & FL_BUF_PACKING && 5218 (MSIZE % sc->params.sge.pack_boundary) != 0) 5219 continue; 5220 5221 if (spare < CL_METADATA_SIZE + MSIZE) 5222 continue; 5223 n = (spare - CL_METADATA_SIZE) / MSIZE; 5224 if (n > howmany(hwb->size, maxp)) 5225 break; 5226 5227 hwidx = idx; 5228 if (fl->flags & FL_BUF_PACKING) { 5229 region1 = n * MSIZE; 5230 region3 = spare - region1; 5231 } else { 5232 region1 = MSIZE; 5233 region3 = spare - region1; 5234 break; 5235 } 5236 } 5237 5238 KASSERT(zidx >= 0 && zidx < SW_ZONE_SIZES, 5239 ("%s: bad zone %d for fl %p, maxp %d", __func__, zidx, fl, maxp)); 5240 KASSERT(hwidx >= 0 && hwidx <= SGE_FLBUF_SIZES, 5241 ("%s: bad hwidx %d for fl %p, maxp %d", __func__, hwidx, fl, maxp)); 5242 KASSERT(region1 + sc->sge.hw_buf_info[hwidx].size + region3 == 5243 sc->sge.sw_zone_info[zidx].size, 5244 ("%s: bad buffer layout for fl %p, maxp %d. " 5245 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp, 5246 sc->sge.sw_zone_info[zidx].size, region1, 5247 sc->sge.hw_buf_info[hwidx].size, region3)); 5248 if (fl->flags & FL_BUF_PACKING || region1 > 0) { 5249 KASSERT(region3 >= CL_METADATA_SIZE, 5250 ("%s: no room for metadata. fl %p, maxp %d; " 5251 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp, 5252 sc->sge.sw_zone_info[zidx].size, region1, 5253 sc->sge.hw_buf_info[hwidx].size, region3)); 5254 KASSERT(region1 % MSIZE == 0, 5255 ("%s: bad mbuf region for fl %p, maxp %d. " 5256 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp, 5257 sc->sge.sw_zone_info[zidx].size, region1, 5258 sc->sge.hw_buf_info[hwidx].size, region3)); 5259 } 5260 5261 fl->cll_def.zidx = zidx; 5262 fl->cll_def.hwidx = hwidx; 5263 fl->cll_def.region1 = region1; 5264 fl->cll_def.region3 = region3; 5265 } 5266 5267 static void 5268 find_safe_refill_source(struct adapter *sc, struct sge_fl *fl) 5269 { 5270 struct sge *s = &sc->sge; 5271 struct hw_buf_info *hwb; 5272 struct sw_zone_info *swz; 5273 int spare; 5274 int8_t hwidx; 5275 5276 if (fl->flags & FL_BUF_PACKING) 5277 hwidx = s->safe_hwidx2; /* with room for metadata */ 5278 else if (allow_mbufs_in_cluster && s->safe_hwidx2 != -1) { 5279 hwidx = s->safe_hwidx2; 5280 hwb = &s->hw_buf_info[hwidx]; 5281 swz = &s->sw_zone_info[hwb->zidx]; 5282 spare = swz->size - hwb->size; 5283 5284 /* no good if there isn't room for an mbuf as well */ 5285 if (spare < CL_METADATA_SIZE + MSIZE) 5286 hwidx = s->safe_hwidx1; 5287 } else 5288 hwidx = s->safe_hwidx1; 5289 5290 if (hwidx == -1) { 5291 /* No fallback source */ 5292 fl->cll_alt.hwidx = -1; 5293 fl->cll_alt.zidx = -1; 5294 5295 return; 5296 } 5297 5298 hwb = &s->hw_buf_info[hwidx]; 5299 swz = &s->sw_zone_info[hwb->zidx]; 5300 spare = swz->size - hwb->size; 5301 fl->cll_alt.hwidx = hwidx; 5302 fl->cll_alt.zidx = hwb->zidx; 5303 if (allow_mbufs_in_cluster && 5304 (fl_pad == 0 || (MSIZE % sc->params.sge.pad_boundary) == 0)) 5305 fl->cll_alt.region1 = ((spare - CL_METADATA_SIZE) / MSIZE) * MSIZE; 5306 else 5307 fl->cll_alt.region1 = 0; 5308 fl->cll_alt.region3 = spare - fl->cll_alt.region1; 5309 } 5310 5311 static void 5312 add_fl_to_sfl(struct adapter *sc, struct sge_fl *fl) 5313 { 5314 mtx_lock(&sc->sfl_lock); 5315 FL_LOCK(fl); 5316 if ((fl->flags & FL_DOOMED) == 0) { 5317 fl->flags |= FL_STARVING; 5318 TAILQ_INSERT_TAIL(&sc->sfl, fl, link); 5319 callout_reset(&sc->sfl_callout, hz / 5, refill_sfl, sc); 5320 } 5321 FL_UNLOCK(fl); 5322 mtx_unlock(&sc->sfl_lock); 5323 } 5324 5325 static void 5326 handle_wrq_egr_update(struct adapter *sc, struct sge_eq *eq) 5327 { 5328 struct sge_wrq *wrq = (void *)eq; 5329 5330 atomic_readandclear_int(&eq->equiq); 5331 taskqueue_enqueue(sc->tq[eq->tx_chan], &wrq->wrq_tx_task); 5332 } 5333 5334 static void 5335 handle_eth_egr_update(struct adapter *sc, struct sge_eq *eq) 5336 { 5337 struct sge_txq *txq = (void *)eq; 5338 5339 MPASS((eq->flags & EQ_TYPEMASK) == EQ_ETH); 5340 5341 atomic_readandclear_int(&eq->equiq); 5342 mp_ring_check_drainage(txq->r, 0); 5343 taskqueue_enqueue(sc->tq[eq->tx_chan], &txq->tx_reclaim_task); 5344 } 5345 5346 static int 5347 handle_sge_egr_update(struct sge_iq *iq, const struct rss_header *rss, 5348 struct mbuf *m) 5349 { 5350 const struct cpl_sge_egr_update *cpl = (const void *)(rss + 1); 5351 unsigned int qid = G_EGR_QID(ntohl(cpl->opcode_qid)); 5352 struct adapter *sc = iq->adapter; 5353 struct sge *s = &sc->sge; 5354 struct sge_eq *eq; 5355 static void (*h[])(struct adapter *, struct sge_eq *) = {NULL, 5356 &handle_wrq_egr_update, &handle_eth_egr_update, 5357 &handle_wrq_egr_update}; 5358 5359 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 5360 rss->opcode)); 5361 5362 eq = s->eqmap[qid - s->eq_start - s->eq_base]; 5363 (*h[eq->flags & EQ_TYPEMASK])(sc, eq); 5364 5365 return (0); 5366 } 5367 5368 /* handle_fw_msg works for both fw4_msg and fw6_msg because this is valid */ 5369 CTASSERT(offsetof(struct cpl_fw4_msg, data) == \ 5370 offsetof(struct cpl_fw6_msg, data)); 5371 5372 static int 5373 handle_fw_msg(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 5374 { 5375 struct adapter *sc = iq->adapter; 5376 const struct cpl_fw6_msg *cpl = (const void *)(rss + 1); 5377 5378 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 5379 rss->opcode)); 5380 5381 if (cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL) { 5382 const struct rss_header *rss2; 5383 5384 rss2 = (const struct rss_header *)&cpl->data[0]; 5385 return (t4_cpl_handler[rss2->opcode](iq, rss2, m)); 5386 } 5387 5388 return (t4_fw_msg_handler[cpl->type](sc, &cpl->data[0])); 5389 } 5390 5391 /** 5392 * t4_handle_wrerr_rpl - process a FW work request error message 5393 * @adap: the adapter 5394 * @rpl: start of the FW message 5395 */ 5396 static int 5397 t4_handle_wrerr_rpl(struct adapter *adap, const __be64 *rpl) 5398 { 5399 u8 opcode = *(const u8 *)rpl; 5400 const struct fw_error_cmd *e = (const void *)rpl; 5401 unsigned int i; 5402 5403 if (opcode != FW_ERROR_CMD) { 5404 log(LOG_ERR, 5405 "%s: Received WRERR_RPL message with opcode %#x\n", 5406 device_get_nameunit(adap->dev), opcode); 5407 return (EINVAL); 5408 } 5409 log(LOG_ERR, "%s: FW_ERROR (%s) ", device_get_nameunit(adap->dev), 5410 G_FW_ERROR_CMD_FATAL(be32toh(e->op_to_type)) ? "fatal" : 5411 "non-fatal"); 5412 switch (G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type))) { 5413 case FW_ERROR_TYPE_EXCEPTION: 5414 log(LOG_ERR, "exception info:\n"); 5415 for (i = 0; i < nitems(e->u.exception.info); i++) 5416 log(LOG_ERR, "%s%08x", i == 0 ? "\t" : " ", 5417 be32toh(e->u.exception.info[i])); 5418 log(LOG_ERR, "\n"); 5419 break; 5420 case FW_ERROR_TYPE_HWMODULE: 5421 log(LOG_ERR, "HW module regaddr %08x regval %08x\n", 5422 be32toh(e->u.hwmodule.regaddr), 5423 be32toh(e->u.hwmodule.regval)); 5424 break; 5425 case FW_ERROR_TYPE_WR: 5426 log(LOG_ERR, "WR cidx %d PF %d VF %d eqid %d hdr:\n", 5427 be16toh(e->u.wr.cidx), 5428 G_FW_ERROR_CMD_PFN(be16toh(e->u.wr.pfn_vfn)), 5429 G_FW_ERROR_CMD_VFN(be16toh(e->u.wr.pfn_vfn)), 5430 be32toh(e->u.wr.eqid)); 5431 for (i = 0; i < nitems(e->u.wr.wrhdr); i++) 5432 log(LOG_ERR, "%s%02x", i == 0 ? "\t" : " ", 5433 e->u.wr.wrhdr[i]); 5434 log(LOG_ERR, "\n"); 5435 break; 5436 case FW_ERROR_TYPE_ACL: 5437 log(LOG_ERR, "ACL cidx %d PF %d VF %d eqid %d %s", 5438 be16toh(e->u.acl.cidx), 5439 G_FW_ERROR_CMD_PFN(be16toh(e->u.acl.pfn_vfn)), 5440 G_FW_ERROR_CMD_VFN(be16toh(e->u.acl.pfn_vfn)), 5441 be32toh(e->u.acl.eqid), 5442 G_FW_ERROR_CMD_MV(be16toh(e->u.acl.mv_pkd)) ? "vlanid" : 5443 "MAC"); 5444 for (i = 0; i < nitems(e->u.acl.val); i++) 5445 log(LOG_ERR, " %02x", e->u.acl.val[i]); 5446 log(LOG_ERR, "\n"); 5447 break; 5448 default: 5449 log(LOG_ERR, "type %#x\n", 5450 G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type))); 5451 return (EINVAL); 5452 } 5453 return (0); 5454 } 5455 5456 static int 5457 sysctl_uint16(SYSCTL_HANDLER_ARGS) 5458 { 5459 uint16_t *id = arg1; 5460 int i = *id; 5461 5462 return sysctl_handle_int(oidp, &i, 0, req); 5463 } 5464 5465 static int 5466 sysctl_bufsizes(SYSCTL_HANDLER_ARGS) 5467 { 5468 struct sge *s = arg1; 5469 struct hw_buf_info *hwb = &s->hw_buf_info[0]; 5470 struct sw_zone_info *swz = &s->sw_zone_info[0]; 5471 int i, rc; 5472 struct sbuf sb; 5473 char c; 5474 5475 sbuf_new(&sb, NULL, 32, SBUF_AUTOEXTEND); 5476 for (i = 0; i < SGE_FLBUF_SIZES; i++, hwb++) { 5477 if (hwb->zidx >= 0 && swz[hwb->zidx].size <= largest_rx_cluster) 5478 c = '*'; 5479 else 5480 c = '\0'; 5481 5482 sbuf_printf(&sb, "%u%c ", hwb->size, c); 5483 } 5484 sbuf_trim(&sb); 5485 sbuf_finish(&sb); 5486 rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req); 5487 sbuf_delete(&sb); 5488 return (rc); 5489 } 5490 5491 #ifdef RATELIMIT 5492 /* 5493 * len16 for a txpkt WR with a GL. Includes the firmware work request header. 5494 */ 5495 static inline u_int 5496 txpkt_eo_len16(u_int nsegs, u_int immhdrs, u_int tso) 5497 { 5498 u_int n; 5499 5500 MPASS(immhdrs > 0); 5501 5502 n = roundup2(sizeof(struct fw_eth_tx_eo_wr) + 5503 sizeof(struct cpl_tx_pkt_core) + immhdrs, 16); 5504 if (__predict_false(nsegs == 0)) 5505 goto done; 5506 5507 nsegs--; /* first segment is part of ulptx_sgl */ 5508 n += sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 5509 if (tso) 5510 n += sizeof(struct cpl_tx_pkt_lso_core); 5511 5512 done: 5513 return (howmany(n, 16)); 5514 } 5515 5516 #define ETID_FLOWC_NPARAMS 6 5517 #define ETID_FLOWC_LEN (roundup2((sizeof(struct fw_flowc_wr) + \ 5518 ETID_FLOWC_NPARAMS * sizeof(struct fw_flowc_mnemval)), 16)) 5519 #define ETID_FLOWC_LEN16 (howmany(ETID_FLOWC_LEN, 16)) 5520 5521 static int 5522 send_etid_flowc_wr(struct cxgbe_snd_tag *cst, struct port_info *pi, 5523 struct vi_info *vi) 5524 { 5525 struct wrq_cookie cookie; 5526 u_int pfvf = G_FW_VIID_PFN(vi->viid) << S_FW_VIID_PFN; 5527 struct fw_flowc_wr *flowc; 5528 5529 mtx_assert(&cst->lock, MA_OWNED); 5530 MPASS((cst->flags & (EO_FLOWC_PENDING | EO_FLOWC_RPL_PENDING)) == 5531 EO_FLOWC_PENDING); 5532 5533 flowc = start_wrq_wr(cst->eo_txq, ETID_FLOWC_LEN16, &cookie); 5534 if (__predict_false(flowc == NULL)) 5535 return (ENOMEM); 5536 5537 bzero(flowc, ETID_FLOWC_LEN); 5538 flowc->op_to_nparams = htobe32(V_FW_WR_OP(FW_FLOWC_WR) | 5539 V_FW_FLOWC_WR_NPARAMS(ETID_FLOWC_NPARAMS) | V_FW_WR_COMPL(0)); 5540 flowc->flowid_len16 = htonl(V_FW_WR_LEN16(ETID_FLOWC_LEN16) | 5541 V_FW_WR_FLOWID(cst->etid)); 5542 flowc->mnemval[0].mnemonic = FW_FLOWC_MNEM_PFNVFN; 5543 flowc->mnemval[0].val = htobe32(pfvf); 5544 flowc->mnemval[1].mnemonic = FW_FLOWC_MNEM_CH; 5545 flowc->mnemval[1].val = htobe32(pi->tx_chan); 5546 flowc->mnemval[2].mnemonic = FW_FLOWC_MNEM_PORT; 5547 flowc->mnemval[2].val = htobe32(pi->tx_chan); 5548 flowc->mnemval[3].mnemonic = FW_FLOWC_MNEM_IQID; 5549 flowc->mnemval[3].val = htobe32(cst->iqid); 5550 flowc->mnemval[4].mnemonic = FW_FLOWC_MNEM_EOSTATE; 5551 flowc->mnemval[4].val = htobe32(FW_FLOWC_MNEM_EOSTATE_ESTABLISHED); 5552 flowc->mnemval[5].mnemonic = FW_FLOWC_MNEM_SCHEDCLASS; 5553 flowc->mnemval[5].val = htobe32(cst->schedcl); 5554 5555 commit_wrq_wr(cst->eo_txq, flowc, &cookie); 5556 5557 cst->flags &= ~EO_FLOWC_PENDING; 5558 cst->flags |= EO_FLOWC_RPL_PENDING; 5559 MPASS(cst->tx_credits >= ETID_FLOWC_LEN16); /* flowc is first WR. */ 5560 cst->tx_credits -= ETID_FLOWC_LEN16; 5561 5562 return (0); 5563 } 5564 5565 #define ETID_FLUSH_LEN16 (howmany(sizeof (struct fw_flowc_wr), 16)) 5566 5567 void 5568 send_etid_flush_wr(struct cxgbe_snd_tag *cst) 5569 { 5570 struct fw_flowc_wr *flowc; 5571 struct wrq_cookie cookie; 5572 5573 mtx_assert(&cst->lock, MA_OWNED); 5574 5575 flowc = start_wrq_wr(cst->eo_txq, ETID_FLUSH_LEN16, &cookie); 5576 if (__predict_false(flowc == NULL)) 5577 CXGBE_UNIMPLEMENTED(__func__); 5578 5579 bzero(flowc, ETID_FLUSH_LEN16 * 16); 5580 flowc->op_to_nparams = htobe32(V_FW_WR_OP(FW_FLOWC_WR) | 5581 V_FW_FLOWC_WR_NPARAMS(0) | F_FW_WR_COMPL); 5582 flowc->flowid_len16 = htobe32(V_FW_WR_LEN16(ETID_FLUSH_LEN16) | 5583 V_FW_WR_FLOWID(cst->etid)); 5584 5585 commit_wrq_wr(cst->eo_txq, flowc, &cookie); 5586 5587 cst->flags |= EO_FLUSH_RPL_PENDING; 5588 MPASS(cst->tx_credits >= ETID_FLUSH_LEN16); 5589 cst->tx_credits -= ETID_FLUSH_LEN16; 5590 cst->ncompl++; 5591 } 5592 5593 static void 5594 write_ethofld_wr(struct cxgbe_snd_tag *cst, struct fw_eth_tx_eo_wr *wr, 5595 struct mbuf *m0, int compl) 5596 { 5597 struct cpl_tx_pkt_core *cpl; 5598 uint64_t ctrl1; 5599 uint32_t ctrl; /* used in many unrelated places */ 5600 int len16, pktlen, nsegs, immhdrs; 5601 caddr_t dst; 5602 uintptr_t p; 5603 struct ulptx_sgl *usgl; 5604 struct sglist sg; 5605 struct sglist_seg segs[38]; /* XXX: find real limit. XXX: get off the stack */ 5606 5607 mtx_assert(&cst->lock, MA_OWNED); 5608 M_ASSERTPKTHDR(m0); 5609 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 5610 m0->m_pkthdr.l4hlen > 0, 5611 ("%s: ethofld mbuf %p is missing header lengths", __func__, m0)); 5612 5613 if (needs_udp_csum(m0)) { 5614 CXGBE_UNIMPLEMENTED("UDP ethofld"); 5615 } 5616 5617 len16 = mbuf_eo_len16(m0); 5618 nsegs = mbuf_eo_nsegs(m0); 5619 pktlen = m0->m_pkthdr.len; 5620 ctrl = sizeof(struct cpl_tx_pkt_core); 5621 if (needs_tso(m0)) 5622 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 5623 immhdrs = m0->m_pkthdr.l2hlen + m0->m_pkthdr.l3hlen + m0->m_pkthdr.l4hlen; 5624 ctrl += immhdrs; 5625 5626 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_EO_WR) | 5627 V_FW_ETH_TX_EO_WR_IMMDLEN(ctrl) | V_FW_WR_COMPL(!!compl)); 5628 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(len16) | 5629 V_FW_WR_FLOWID(cst->etid)); 5630 wr->r3 = 0; 5631 wr->u.tcpseg.type = FW_ETH_TX_EO_TYPE_TCPSEG; 5632 wr->u.tcpseg.ethlen = m0->m_pkthdr.l2hlen; 5633 wr->u.tcpseg.iplen = htobe16(m0->m_pkthdr.l3hlen); 5634 wr->u.tcpseg.tcplen = m0->m_pkthdr.l4hlen; 5635 wr->u.tcpseg.tsclk_tsoff = mbuf_eo_tsclk_tsoff(m0); 5636 wr->u.tcpseg.r4 = 0; 5637 wr->u.tcpseg.r5 = 0; 5638 wr->u.tcpseg.plen = htobe32(pktlen - immhdrs); 5639 5640 if (needs_tso(m0)) { 5641 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1); 5642 5643 wr->u.tcpseg.mss = htobe16(m0->m_pkthdr.tso_segsz); 5644 5645 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE | 5646 F_LSO_LAST_SLICE | V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) 5647 | V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2); 5648 if (m0->m_pkthdr.l2hlen == sizeof(struct ether_vlan_header)) 5649 ctrl |= V_LSO_ETHHDR_LEN(1); 5650 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 5651 ctrl |= F_LSO_IPV6; 5652 lso->lso_ctrl = htobe32(ctrl); 5653 lso->ipid_ofst = htobe16(0); 5654 lso->mss = htobe16(m0->m_pkthdr.tso_segsz); 5655 lso->seqno_offset = htobe32(0); 5656 lso->len = htobe32(pktlen); 5657 5658 cpl = (void *)(lso + 1); 5659 } else { 5660 wr->u.tcpseg.mss = htobe16(0xffff); 5661 cpl = (void *)(wr + 1); 5662 } 5663 5664 /* Checksum offload must be requested for ethofld. */ 5665 ctrl1 = 0; 5666 MPASS(needs_l4_csum(m0)); 5667 5668 /* VLAN tag insertion */ 5669 if (needs_vlan_insertion(m0)) { 5670 ctrl1 |= F_TXPKT_VLAN_VLD | 5671 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 5672 } 5673 5674 /* CPL header */ 5675 cpl->ctrl0 = cst->ctrl0; 5676 cpl->pack = 0; 5677 cpl->len = htobe16(pktlen); 5678 cpl->ctrl1 = htobe64(ctrl1); 5679 5680 /* Copy Ethernet, IP & TCP hdrs as immediate data */ 5681 p = (uintptr_t)(cpl + 1); 5682 m_copydata(m0, 0, immhdrs, (void *)p); 5683 5684 /* SGL */ 5685 dst = (void *)(cpl + 1); 5686 if (nsegs > 0) { 5687 int i, pad; 5688 5689 /* zero-pad upto next 16Byte boundary, if not 16Byte aligned */ 5690 p += immhdrs; 5691 pad = 16 - (immhdrs & 0xf); 5692 bzero((void *)p, pad); 5693 5694 usgl = (void *)(p + pad); 5695 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 5696 V_ULPTX_NSGE(nsegs)); 5697 5698 sglist_init(&sg, nitems(segs), segs); 5699 for (; m0 != NULL; m0 = m0->m_next) { 5700 if (__predict_false(m0->m_len == 0)) 5701 continue; 5702 if (immhdrs >= m0->m_len) { 5703 immhdrs -= m0->m_len; 5704 continue; 5705 } 5706 5707 sglist_append(&sg, mtod(m0, char *) + immhdrs, 5708 m0->m_len - immhdrs); 5709 immhdrs = 0; 5710 } 5711 MPASS(sg.sg_nseg == nsegs); 5712 5713 /* 5714 * Zero pad last 8B in case the WR doesn't end on a 16B 5715 * boundary. 5716 */ 5717 *(uint64_t *)((char *)wr + len16 * 16 - 8) = 0; 5718 5719 usgl->len0 = htobe32(segs[0].ss_len); 5720 usgl->addr0 = htobe64(segs[0].ss_paddr); 5721 for (i = 0; i < nsegs - 1; i++) { 5722 usgl->sge[i / 2].len[i & 1] = htobe32(segs[i + 1].ss_len); 5723 usgl->sge[i / 2].addr[i & 1] = htobe64(segs[i + 1].ss_paddr); 5724 } 5725 if (i & 1) 5726 usgl->sge[i / 2].len[1] = htobe32(0); 5727 } 5728 5729 } 5730 5731 static void 5732 ethofld_tx(struct cxgbe_snd_tag *cst) 5733 { 5734 struct mbuf *m; 5735 struct wrq_cookie cookie; 5736 int next_credits, compl; 5737 struct fw_eth_tx_eo_wr *wr; 5738 5739 mtx_assert(&cst->lock, MA_OWNED); 5740 5741 while ((m = mbufq_first(&cst->pending_tx)) != NULL) { 5742 M_ASSERTPKTHDR(m); 5743 5744 /* How many len16 credits do we need to send this mbuf. */ 5745 next_credits = mbuf_eo_len16(m); 5746 MPASS(next_credits > 0); 5747 if (next_credits > cst->tx_credits) { 5748 /* 5749 * Tx will make progress eventually because there is at 5750 * least one outstanding fw4_ack that will return 5751 * credits and kick the tx. 5752 */ 5753 MPASS(cst->ncompl > 0); 5754 return; 5755 } 5756 wr = start_wrq_wr(cst->eo_txq, next_credits, &cookie); 5757 if (__predict_false(wr == NULL)) { 5758 /* XXX: wishful thinking, not a real assertion. */ 5759 MPASS(cst->ncompl > 0); 5760 return; 5761 } 5762 cst->tx_credits -= next_credits; 5763 cst->tx_nocompl += next_credits; 5764 compl = cst->ncompl == 0 || cst->tx_nocompl >= cst->tx_total / 2; 5765 ETHER_BPF_MTAP(cst->com.ifp, m); 5766 write_ethofld_wr(cst, wr, m, compl); 5767 commit_wrq_wr(cst->eo_txq, wr, &cookie); 5768 if (compl) { 5769 cst->ncompl++; 5770 cst->tx_nocompl = 0; 5771 } 5772 (void) mbufq_dequeue(&cst->pending_tx); 5773 mbufq_enqueue(&cst->pending_fwack, m); 5774 } 5775 } 5776 5777 int 5778 ethofld_transmit(struct ifnet *ifp, struct mbuf *m0) 5779 { 5780 struct cxgbe_snd_tag *cst; 5781 int rc; 5782 5783 MPASS(m0->m_nextpkt == NULL); 5784 MPASS(m0->m_pkthdr.snd_tag != NULL); 5785 cst = mst_to_cst(m0->m_pkthdr.snd_tag); 5786 5787 mtx_lock(&cst->lock); 5788 MPASS(cst->flags & EO_SND_TAG_REF); 5789 5790 if (__predict_false(cst->flags & EO_FLOWC_PENDING)) { 5791 struct vi_info *vi = ifp->if_softc; 5792 struct port_info *pi = vi->pi; 5793 struct adapter *sc = pi->adapter; 5794 const uint32_t rss_mask = vi->rss_size - 1; 5795 uint32_t rss_hash; 5796 5797 cst->eo_txq = &sc->sge.ofld_txq[vi->first_ofld_txq]; 5798 if (M_HASHTYPE_ISHASH(m0)) 5799 rss_hash = m0->m_pkthdr.flowid; 5800 else 5801 rss_hash = arc4random(); 5802 /* We assume RSS hashing */ 5803 cst->iqid = vi->rss[rss_hash & rss_mask]; 5804 cst->eo_txq += rss_hash % vi->nofldtxq; 5805 rc = send_etid_flowc_wr(cst, pi, vi); 5806 if (rc != 0) 5807 goto done; 5808 } 5809 5810 if (__predict_false(cst->plen + m0->m_pkthdr.len > eo_max_backlog)) { 5811 rc = ENOBUFS; 5812 goto done; 5813 } 5814 5815 mbufq_enqueue(&cst->pending_tx, m0); 5816 cst->plen += m0->m_pkthdr.len; 5817 5818 ethofld_tx(cst); 5819 rc = 0; 5820 done: 5821 mtx_unlock(&cst->lock); 5822 if (__predict_false(rc != 0)) 5823 m_freem(m0); 5824 return (rc); 5825 } 5826 5827 static int 5828 ethofld_fw4_ack(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0) 5829 { 5830 struct adapter *sc = iq->adapter; 5831 const struct cpl_fw4_ack *cpl = (const void *)(rss + 1); 5832 struct mbuf *m; 5833 u_int etid = G_CPL_FW4_ACK_FLOWID(be32toh(OPCODE_TID(cpl))); 5834 struct cxgbe_snd_tag *cst; 5835 uint8_t credits = cpl->credits; 5836 5837 cst = lookup_etid(sc, etid); 5838 mtx_lock(&cst->lock); 5839 if (__predict_false(cst->flags & EO_FLOWC_RPL_PENDING)) { 5840 MPASS(credits >= ETID_FLOWC_LEN16); 5841 credits -= ETID_FLOWC_LEN16; 5842 cst->flags &= ~EO_FLOWC_RPL_PENDING; 5843 } 5844 5845 KASSERT(cst->ncompl > 0, 5846 ("%s: etid %u (%p) wasn't expecting completion.", 5847 __func__, etid, cst)); 5848 cst->ncompl--; 5849 5850 while (credits > 0) { 5851 m = mbufq_dequeue(&cst->pending_fwack); 5852 if (__predict_false(m == NULL)) { 5853 /* 5854 * The remaining credits are for the final flush that 5855 * was issued when the tag was freed by the kernel. 5856 */ 5857 MPASS((cst->flags & 5858 (EO_FLUSH_RPL_PENDING | EO_SND_TAG_REF)) == 5859 EO_FLUSH_RPL_PENDING); 5860 MPASS(credits == ETID_FLUSH_LEN16); 5861 MPASS(cst->tx_credits + cpl->credits == cst->tx_total); 5862 MPASS(cst->ncompl == 0); 5863 5864 cst->flags &= ~EO_FLUSH_RPL_PENDING; 5865 cst->tx_credits += cpl->credits; 5866 freetag: 5867 cxgbe_snd_tag_free_locked(cst); 5868 return (0); /* cst is gone. */ 5869 } 5870 KASSERT(m != NULL, 5871 ("%s: too many credits (%u, %u)", __func__, cpl->credits, 5872 credits)); 5873 KASSERT(credits >= mbuf_eo_len16(m), 5874 ("%s: too few credits (%u, %u, %u)", __func__, 5875 cpl->credits, credits, mbuf_eo_len16(m))); 5876 credits -= mbuf_eo_len16(m); 5877 cst->plen -= m->m_pkthdr.len; 5878 m_freem(m); 5879 } 5880 5881 cst->tx_credits += cpl->credits; 5882 MPASS(cst->tx_credits <= cst->tx_total); 5883 5884 m = mbufq_first(&cst->pending_tx); 5885 if (m != NULL && cst->tx_credits >= mbuf_eo_len16(m)) 5886 ethofld_tx(cst); 5887 5888 if (__predict_false((cst->flags & EO_SND_TAG_REF) == 0) && 5889 cst->ncompl == 0) { 5890 if (cst->tx_credits == cst->tx_total) 5891 goto freetag; 5892 else { 5893 MPASS((cst->flags & EO_FLUSH_RPL_PENDING) == 0); 5894 send_etid_flush_wr(cst); 5895 } 5896 } 5897 5898 mtx_unlock(&cst->lock); 5899 5900 return (0); 5901 } 5902 #endif 5903