xref: /freebsd/sys/dev/cxgbe/t4_sge.c (revision 31ba4ce8898f9dfa5e7f054fdbc26e50a599a6e3)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3  *
4  * Copyright (c) 2011 Chelsio Communications, Inc.
5  * All rights reserved.
6  * Written by: Navdeep Parhar <np@FreeBSD.org>
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions and the following disclaimer.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27  * SUCH DAMAGE.
28  */
29 
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
32 
33 #include "opt_inet.h"
34 #include "opt_inet6.h"
35 #include "opt_kern_tls.h"
36 #include "opt_ratelimit.h"
37 
38 #include <sys/types.h>
39 #include <sys/eventhandler.h>
40 #include <sys/mbuf.h>
41 #include <sys/socket.h>
42 #include <sys/kernel.h>
43 #include <sys/ktls.h>
44 #include <sys/malloc.h>
45 #include <sys/queue.h>
46 #include <sys/sbuf.h>
47 #include <sys/taskqueue.h>
48 #include <sys/time.h>
49 #include <sys/sglist.h>
50 #include <sys/sysctl.h>
51 #include <sys/smp.h>
52 #include <sys/socketvar.h>
53 #include <sys/counter.h>
54 #include <net/bpf.h>
55 #include <net/ethernet.h>
56 #include <net/if.h>
57 #include <net/if_vlan_var.h>
58 #include <net/if_vxlan.h>
59 #include <netinet/in.h>
60 #include <netinet/ip.h>
61 #include <netinet/ip6.h>
62 #include <netinet/tcp.h>
63 #include <netinet/udp.h>
64 #include <machine/in_cksum.h>
65 #include <machine/md_var.h>
66 #include <vm/vm.h>
67 #include <vm/pmap.h>
68 #ifdef DEV_NETMAP
69 #include <machine/bus.h>
70 #include <sys/selinfo.h>
71 #include <net/if_var.h>
72 #include <net/netmap.h>
73 #include <dev/netmap/netmap_kern.h>
74 #endif
75 
76 #include "common/common.h"
77 #include "common/t4_regs.h"
78 #include "common/t4_regs_values.h"
79 #include "common/t4_msg.h"
80 #include "t4_l2t.h"
81 #include "t4_mp_ring.h"
82 
83 #ifdef T4_PKT_TIMESTAMP
84 #define RX_COPY_THRESHOLD (MINCLSIZE - 8)
85 #else
86 #define RX_COPY_THRESHOLD MINCLSIZE
87 #endif
88 
89 /* Internal mbuf flags stored in PH_loc.eight[1]. */
90 #define	MC_NOMAP		0x01
91 #define	MC_RAW_WR		0x02
92 #define	MC_TLS			0x04
93 
94 /*
95  * Ethernet frames are DMA'd at this byte offset into the freelist buffer.
96  * 0-7 are valid values.
97  */
98 static int fl_pktshift = 0;
99 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pktshift, CTLFLAG_RDTUN, &fl_pktshift, 0,
100     "payload DMA offset in rx buffer (bytes)");
101 
102 /*
103  * Pad ethernet payload up to this boundary.
104  * -1: driver should figure out a good value.
105  *  0: disable padding.
106  *  Any power of 2 from 32 to 4096 (both inclusive) is also a valid value.
107  */
108 int fl_pad = -1;
109 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pad, CTLFLAG_RDTUN, &fl_pad, 0,
110     "payload pad boundary (bytes)");
111 
112 /*
113  * Status page length.
114  * -1: driver should figure out a good value.
115  *  64 or 128 are the only other valid values.
116  */
117 static int spg_len = -1;
118 SYSCTL_INT(_hw_cxgbe, OID_AUTO, spg_len, CTLFLAG_RDTUN, &spg_len, 0,
119     "status page size (bytes)");
120 
121 /*
122  * Congestion drops.
123  * -1: no congestion feedback (not recommended).
124  *  0: backpressure the channel instead of dropping packets right away.
125  *  1: no backpressure, drop packets for the congested queue immediately.
126  */
127 static int cong_drop = 0;
128 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cong_drop, CTLFLAG_RDTUN, &cong_drop, 0,
129     "Congestion control for RX queues (0 = backpressure, 1 = drop");
130 
131 /*
132  * Deliver multiple frames in the same free list buffer if they fit.
133  * -1: let the driver decide whether to enable buffer packing or not.
134  *  0: disable buffer packing.
135  *  1: enable buffer packing.
136  */
137 static int buffer_packing = -1;
138 SYSCTL_INT(_hw_cxgbe, OID_AUTO, buffer_packing, CTLFLAG_RDTUN, &buffer_packing,
139     0, "Enable buffer packing");
140 
141 /*
142  * Start next frame in a packed buffer at this boundary.
143  * -1: driver should figure out a good value.
144  * T4: driver will ignore this and use the same value as fl_pad above.
145  * T5: 16, or a power of 2 from 64 to 4096 (both inclusive) is a valid value.
146  */
147 static int fl_pack = -1;
148 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pack, CTLFLAG_RDTUN, &fl_pack, 0,
149     "payload pack boundary (bytes)");
150 
151 /*
152  * Largest rx cluster size that the driver is allowed to allocate.
153  */
154 static int largest_rx_cluster = MJUM16BYTES;
155 SYSCTL_INT(_hw_cxgbe, OID_AUTO, largest_rx_cluster, CTLFLAG_RDTUN,
156     &largest_rx_cluster, 0, "Largest rx cluster (bytes)");
157 
158 /*
159  * Size of cluster allocation that's most likely to succeed.  The driver will
160  * fall back to this size if it fails to allocate clusters larger than this.
161  */
162 static int safest_rx_cluster = PAGE_SIZE;
163 SYSCTL_INT(_hw_cxgbe, OID_AUTO, safest_rx_cluster, CTLFLAG_RDTUN,
164     &safest_rx_cluster, 0, "Safe rx cluster (bytes)");
165 
166 #ifdef RATELIMIT
167 /*
168  * Knob to control TCP timestamp rewriting, and the granularity of the tick used
169  * for rewriting.  -1 and 0-3 are all valid values.
170  * -1: hardware should leave the TCP timestamps alone.
171  * 0: 1ms
172  * 1: 100us
173  * 2: 10us
174  * 3: 1us
175  */
176 static int tsclk = -1;
177 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tsclk, CTLFLAG_RDTUN, &tsclk, 0,
178     "Control TCP timestamp rewriting when using pacing");
179 
180 static int eo_max_backlog = 1024 * 1024;
181 SYSCTL_INT(_hw_cxgbe, OID_AUTO, eo_max_backlog, CTLFLAG_RDTUN, &eo_max_backlog,
182     0, "Maximum backlog of ratelimited data per flow");
183 #endif
184 
185 /*
186  * The interrupt holdoff timers are multiplied by this value on T6+.
187  * 1 and 3-17 (both inclusive) are legal values.
188  */
189 static int tscale = 1;
190 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tscale, CTLFLAG_RDTUN, &tscale, 0,
191     "Interrupt holdoff timer scale on T6+");
192 
193 /*
194  * Number of LRO entries in the lro_ctrl structure per rx queue.
195  */
196 static int lro_entries = TCP_LRO_ENTRIES;
197 SYSCTL_INT(_hw_cxgbe, OID_AUTO, lro_entries, CTLFLAG_RDTUN, &lro_entries, 0,
198     "Number of LRO entries per RX queue");
199 
200 /*
201  * This enables presorting of frames before they're fed into tcp_lro_rx.
202  */
203 static int lro_mbufs = 0;
204 SYSCTL_INT(_hw_cxgbe, OID_AUTO, lro_mbufs, CTLFLAG_RDTUN, &lro_mbufs, 0,
205     "Enable presorting of LRO frames");
206 
207 static counter_u64_t pullups;
208 SYSCTL_COUNTER_U64(_hw_cxgbe, OID_AUTO, pullups, CTLFLAG_RD, &pullups,
209     "Number of mbuf pullups performed");
210 
211 static counter_u64_t defrags;
212 SYSCTL_COUNTER_U64(_hw_cxgbe, OID_AUTO, defrags, CTLFLAG_RD, &defrags,
213     "Number of mbuf defrags performed");
214 
215 static int t4_tx_coalesce = 1;
216 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tx_coalesce, CTLFLAG_RWTUN, &t4_tx_coalesce, 0,
217     "tx coalescing allowed");
218 
219 /*
220  * The driver will make aggressive attempts at tx coalescing if it sees these
221  * many packets eligible for coalescing in quick succession, with no more than
222  * the specified gap in between the eth_tx calls that delivered the packets.
223  */
224 static int t4_tx_coalesce_pkts = 32;
225 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tx_coalesce_pkts, CTLFLAG_RWTUN,
226     &t4_tx_coalesce_pkts, 0,
227     "# of consecutive packets (1 - 255) that will trigger tx coalescing");
228 static int t4_tx_coalesce_gap = 5;
229 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tx_coalesce_gap, CTLFLAG_RWTUN,
230     &t4_tx_coalesce_gap, 0, "tx gap (in microseconds)");
231 
232 static int service_iq(struct sge_iq *, int);
233 static int service_iq_fl(struct sge_iq *, int);
234 static struct mbuf *get_fl_payload(struct adapter *, struct sge_fl *, uint32_t);
235 static int eth_rx(struct adapter *, struct sge_rxq *, const struct iq_desc *,
236     u_int);
237 static inline void init_iq(struct sge_iq *, struct adapter *, int, int, int,
238     int, int);
239 static inline void init_fl(struct adapter *, struct sge_fl *, int, int, char *);
240 static inline void init_eq(struct adapter *, struct sge_eq *, int, int, uint8_t,
241     struct sge_iq *, char *);
242 static int alloc_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *,
243     struct sysctl_ctx_list *, struct sysctl_oid *);
244 static void free_iq_fl(struct adapter *, struct sge_iq *, struct sge_fl *);
245 static void add_iq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *,
246     struct sge_iq *);
247 static void add_fl_sysctls(struct adapter *, struct sysctl_ctx_list *,
248     struct sysctl_oid *, struct sge_fl *);
249 static int alloc_iq_fl_hwq(struct vi_info *, struct sge_iq *, struct sge_fl *);
250 static int free_iq_fl_hwq(struct adapter *, struct sge_iq *, struct sge_fl *);
251 static int alloc_fwq(struct adapter *);
252 static void free_fwq(struct adapter *);
253 static int alloc_ctrlq(struct adapter *, int);
254 static void free_ctrlq(struct adapter *, int);
255 static int alloc_rxq(struct vi_info *, struct sge_rxq *, int, int, int);
256 static void free_rxq(struct vi_info *, struct sge_rxq *);
257 static void add_rxq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *,
258     struct sge_rxq *);
259 #ifdef TCP_OFFLOAD
260 static int alloc_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *, int, int,
261     int);
262 static void free_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *);
263 static void add_ofld_rxq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *,
264     struct sge_ofld_rxq *);
265 #endif
266 static int ctrl_eq_alloc(struct adapter *, struct sge_eq *);
267 static int eth_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *);
268 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
269 static int ofld_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *);
270 #endif
271 static int alloc_eq(struct adapter *, struct sge_eq *, struct sysctl_ctx_list *,
272     struct sysctl_oid *);
273 static void free_eq(struct adapter *, struct sge_eq *);
274 static void add_eq_sysctls(struct adapter *, struct sysctl_ctx_list *,
275     struct sysctl_oid *, struct sge_eq *);
276 static int alloc_eq_hwq(struct adapter *, struct vi_info *, struct sge_eq *);
277 static int free_eq_hwq(struct adapter *, struct vi_info *, struct sge_eq *);
278 static int alloc_wrq(struct adapter *, struct vi_info *, struct sge_wrq *,
279     struct sysctl_ctx_list *, struct sysctl_oid *);
280 static void free_wrq(struct adapter *, struct sge_wrq *);
281 static void add_wrq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *,
282     struct sge_wrq *);
283 static int alloc_txq(struct vi_info *, struct sge_txq *, int);
284 static void free_txq(struct vi_info *, struct sge_txq *);
285 static void add_txq_sysctls(struct vi_info *, struct sysctl_ctx_list *,
286     struct sysctl_oid *, struct sge_txq *);
287 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
288 static int alloc_ofld_txq(struct vi_info *, struct sge_ofld_txq *, int);
289 static void free_ofld_txq(struct vi_info *, struct sge_ofld_txq *);
290 static void add_ofld_txq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *,
291     struct sge_ofld_txq *);
292 #endif
293 static void oneseg_dma_callback(void *, bus_dma_segment_t *, int, int);
294 static inline void ring_fl_db(struct adapter *, struct sge_fl *);
295 static int refill_fl(struct adapter *, struct sge_fl *, int);
296 static void refill_sfl(void *);
297 static int find_refill_source(struct adapter *, int, bool);
298 static void add_fl_to_sfl(struct adapter *, struct sge_fl *);
299 
300 static inline void get_pkt_gl(struct mbuf *, struct sglist *);
301 static inline u_int txpkt_len16(u_int, const u_int);
302 static inline u_int txpkt_vm_len16(u_int, const u_int);
303 static inline void calculate_mbuf_len16(struct mbuf *, bool);
304 static inline u_int txpkts0_len16(u_int);
305 static inline u_int txpkts1_len16(void);
306 static u_int write_raw_wr(struct sge_txq *, void *, struct mbuf *, u_int);
307 static u_int write_txpkt_wr(struct adapter *, struct sge_txq *, struct mbuf *,
308     u_int);
309 static u_int write_txpkt_vm_wr(struct adapter *, struct sge_txq *,
310     struct mbuf *);
311 static int add_to_txpkts_vf(struct adapter *, struct sge_txq *, struct mbuf *,
312     int, bool *);
313 static int add_to_txpkts_pf(struct adapter *, struct sge_txq *, struct mbuf *,
314     int, bool *);
315 static u_int write_txpkts_wr(struct adapter *, struct sge_txq *);
316 static u_int write_txpkts_vm_wr(struct adapter *, struct sge_txq *);
317 static void write_gl_to_txd(struct sge_txq *, struct mbuf *, caddr_t *, int);
318 static inline void copy_to_txd(struct sge_eq *, caddr_t, caddr_t *, int);
319 static inline void ring_eq_db(struct adapter *, struct sge_eq *, u_int);
320 static inline uint16_t read_hw_cidx(struct sge_eq *);
321 static inline u_int reclaimable_tx_desc(struct sge_eq *);
322 static inline u_int total_available_tx_desc(struct sge_eq *);
323 static u_int reclaim_tx_descs(struct sge_txq *, u_int);
324 static void tx_reclaim(void *, int);
325 static __be64 get_flit(struct sglist_seg *, int, int);
326 static int handle_sge_egr_update(struct sge_iq *, const struct rss_header *,
327     struct mbuf *);
328 static int handle_fw_msg(struct sge_iq *, const struct rss_header *,
329     struct mbuf *);
330 static int t4_handle_wrerr_rpl(struct adapter *, const __be64 *);
331 static void wrq_tx_drain(void *, int);
332 static void drain_wrq_wr_list(struct adapter *, struct sge_wrq *);
333 
334 static int sysctl_bufsizes(SYSCTL_HANDLER_ARGS);
335 #ifdef RATELIMIT
336 #if defined(INET) || defined(INET6)
337 static inline u_int txpkt_eo_len16(u_int, u_int, u_int);
338 #endif
339 static int ethofld_fw4_ack(struct sge_iq *, const struct rss_header *,
340     struct mbuf *);
341 #endif
342 
343 static counter_u64_t extfree_refs;
344 static counter_u64_t extfree_rels;
345 
346 an_handler_t t4_an_handler;
347 fw_msg_handler_t t4_fw_msg_handler[NUM_FW6_TYPES];
348 cpl_handler_t t4_cpl_handler[NUM_CPL_CMDS];
349 cpl_handler_t set_tcb_rpl_handlers[NUM_CPL_COOKIES];
350 cpl_handler_t l2t_write_rpl_handlers[NUM_CPL_COOKIES];
351 cpl_handler_t act_open_rpl_handlers[NUM_CPL_COOKIES];
352 cpl_handler_t abort_rpl_rss_handlers[NUM_CPL_COOKIES];
353 cpl_handler_t fw4_ack_handlers[NUM_CPL_COOKIES];
354 
355 void
356 t4_register_an_handler(an_handler_t h)
357 {
358 	uintptr_t *loc;
359 
360 	MPASS(h == NULL || t4_an_handler == NULL);
361 
362 	loc = (uintptr_t *)&t4_an_handler;
363 	atomic_store_rel_ptr(loc, (uintptr_t)h);
364 }
365 
366 void
367 t4_register_fw_msg_handler(int type, fw_msg_handler_t h)
368 {
369 	uintptr_t *loc;
370 
371 	MPASS(type < nitems(t4_fw_msg_handler));
372 	MPASS(h == NULL || t4_fw_msg_handler[type] == NULL);
373 	/*
374 	 * These are dispatched by the handler for FW{4|6}_CPL_MSG using the CPL
375 	 * handler dispatch table.  Reject any attempt to install a handler for
376 	 * this subtype.
377 	 */
378 	MPASS(type != FW_TYPE_RSSCPL);
379 	MPASS(type != FW6_TYPE_RSSCPL);
380 
381 	loc = (uintptr_t *)&t4_fw_msg_handler[type];
382 	atomic_store_rel_ptr(loc, (uintptr_t)h);
383 }
384 
385 void
386 t4_register_cpl_handler(int opcode, cpl_handler_t h)
387 {
388 	uintptr_t *loc;
389 
390 	MPASS(opcode < nitems(t4_cpl_handler));
391 	MPASS(h == NULL || t4_cpl_handler[opcode] == NULL);
392 
393 	loc = (uintptr_t *)&t4_cpl_handler[opcode];
394 	atomic_store_rel_ptr(loc, (uintptr_t)h);
395 }
396 
397 static int
398 set_tcb_rpl_handler(struct sge_iq *iq, const struct rss_header *rss,
399     struct mbuf *m)
400 {
401 	const struct cpl_set_tcb_rpl *cpl = (const void *)(rss + 1);
402 	u_int tid;
403 	int cookie;
404 
405 	MPASS(m == NULL);
406 
407 	tid = GET_TID(cpl);
408 	if (is_hpftid(iq->adapter, tid) || is_ftid(iq->adapter, tid)) {
409 		/*
410 		 * The return code for filter-write is put in the CPL cookie so
411 		 * we have to rely on the hardware tid (is_ftid) to determine
412 		 * that this is a response to a filter.
413 		 */
414 		cookie = CPL_COOKIE_FILTER;
415 	} else {
416 		cookie = G_COOKIE(cpl->cookie);
417 	}
418 	MPASS(cookie > CPL_COOKIE_RESERVED);
419 	MPASS(cookie < nitems(set_tcb_rpl_handlers));
420 
421 	return (set_tcb_rpl_handlers[cookie](iq, rss, m));
422 }
423 
424 static int
425 l2t_write_rpl_handler(struct sge_iq *iq, const struct rss_header *rss,
426     struct mbuf *m)
427 {
428 	const struct cpl_l2t_write_rpl *rpl = (const void *)(rss + 1);
429 	unsigned int cookie;
430 
431 	MPASS(m == NULL);
432 
433 	cookie = GET_TID(rpl) & F_SYNC_WR ? CPL_COOKIE_TOM : CPL_COOKIE_FILTER;
434 	return (l2t_write_rpl_handlers[cookie](iq, rss, m));
435 }
436 
437 static int
438 act_open_rpl_handler(struct sge_iq *iq, const struct rss_header *rss,
439     struct mbuf *m)
440 {
441 	const struct cpl_act_open_rpl *cpl = (const void *)(rss + 1);
442 	u_int cookie = G_TID_COOKIE(G_AOPEN_ATID(be32toh(cpl->atid_status)));
443 
444 	MPASS(m == NULL);
445 	MPASS(cookie != CPL_COOKIE_RESERVED);
446 
447 	return (act_open_rpl_handlers[cookie](iq, rss, m));
448 }
449 
450 static int
451 abort_rpl_rss_handler(struct sge_iq *iq, const struct rss_header *rss,
452     struct mbuf *m)
453 {
454 	struct adapter *sc = iq->adapter;
455 	u_int cookie;
456 
457 	MPASS(m == NULL);
458 	if (is_hashfilter(sc))
459 		cookie = CPL_COOKIE_HASHFILTER;
460 	else
461 		cookie = CPL_COOKIE_TOM;
462 
463 	return (abort_rpl_rss_handlers[cookie](iq, rss, m));
464 }
465 
466 static int
467 fw4_ack_handler(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
468 {
469 	struct adapter *sc = iq->adapter;
470 	const struct cpl_fw4_ack *cpl = (const void *)(rss + 1);
471 	unsigned int tid = G_CPL_FW4_ACK_FLOWID(be32toh(OPCODE_TID(cpl)));
472 	u_int cookie;
473 
474 	MPASS(m == NULL);
475 	if (is_etid(sc, tid))
476 		cookie = CPL_COOKIE_ETHOFLD;
477 	else
478 		cookie = CPL_COOKIE_TOM;
479 
480 	return (fw4_ack_handlers[cookie](iq, rss, m));
481 }
482 
483 static void
484 t4_init_shared_cpl_handlers(void)
485 {
486 
487 	t4_register_cpl_handler(CPL_SET_TCB_RPL, set_tcb_rpl_handler);
488 	t4_register_cpl_handler(CPL_L2T_WRITE_RPL, l2t_write_rpl_handler);
489 	t4_register_cpl_handler(CPL_ACT_OPEN_RPL, act_open_rpl_handler);
490 	t4_register_cpl_handler(CPL_ABORT_RPL_RSS, abort_rpl_rss_handler);
491 	t4_register_cpl_handler(CPL_FW4_ACK, fw4_ack_handler);
492 }
493 
494 void
495 t4_register_shared_cpl_handler(int opcode, cpl_handler_t h, int cookie)
496 {
497 	uintptr_t *loc;
498 
499 	MPASS(opcode < nitems(t4_cpl_handler));
500 	MPASS(cookie > CPL_COOKIE_RESERVED);
501 	MPASS(cookie < NUM_CPL_COOKIES);
502 	MPASS(t4_cpl_handler[opcode] != NULL);
503 
504 	switch (opcode) {
505 	case CPL_SET_TCB_RPL:
506 		loc = (uintptr_t *)&set_tcb_rpl_handlers[cookie];
507 		break;
508 	case CPL_L2T_WRITE_RPL:
509 		loc = (uintptr_t *)&l2t_write_rpl_handlers[cookie];
510 		break;
511 	case CPL_ACT_OPEN_RPL:
512 		loc = (uintptr_t *)&act_open_rpl_handlers[cookie];
513 		break;
514 	case CPL_ABORT_RPL_RSS:
515 		loc = (uintptr_t *)&abort_rpl_rss_handlers[cookie];
516 		break;
517 	case CPL_FW4_ACK:
518 		loc = (uintptr_t *)&fw4_ack_handlers[cookie];
519 		break;
520 	default:
521 		MPASS(0);
522 		return;
523 	}
524 	MPASS(h == NULL || *loc == (uintptr_t)NULL);
525 	atomic_store_rel_ptr(loc, (uintptr_t)h);
526 }
527 
528 /*
529  * Called on MOD_LOAD.  Validates and calculates the SGE tunables.
530  */
531 void
532 t4_sge_modload(void)
533 {
534 
535 	if (fl_pktshift < 0 || fl_pktshift > 7) {
536 		printf("Invalid hw.cxgbe.fl_pktshift value (%d),"
537 		    " using 0 instead.\n", fl_pktshift);
538 		fl_pktshift = 0;
539 	}
540 
541 	if (spg_len != 64 && spg_len != 128) {
542 		int len;
543 
544 #if defined(__i386__) || defined(__amd64__)
545 		len = cpu_clflush_line_size > 64 ? 128 : 64;
546 #else
547 		len = 64;
548 #endif
549 		if (spg_len != -1) {
550 			printf("Invalid hw.cxgbe.spg_len value (%d),"
551 			    " using %d instead.\n", spg_len, len);
552 		}
553 		spg_len = len;
554 	}
555 
556 	if (cong_drop < -1 || cong_drop > 1) {
557 		printf("Invalid hw.cxgbe.cong_drop value (%d),"
558 		    " using 0 instead.\n", cong_drop);
559 		cong_drop = 0;
560 	}
561 
562 	if (tscale != 1 && (tscale < 3 || tscale > 17)) {
563 		printf("Invalid hw.cxgbe.tscale value (%d),"
564 		    " using 1 instead.\n", tscale);
565 		tscale = 1;
566 	}
567 
568 	if (largest_rx_cluster != MCLBYTES &&
569 #if MJUMPAGESIZE != MCLBYTES
570 	    largest_rx_cluster != MJUMPAGESIZE &&
571 #endif
572 	    largest_rx_cluster != MJUM9BYTES &&
573 	    largest_rx_cluster != MJUM16BYTES) {
574 		printf("Invalid hw.cxgbe.largest_rx_cluster value (%d),"
575 		    " using %d instead.\n", largest_rx_cluster, MJUM16BYTES);
576 		largest_rx_cluster = MJUM16BYTES;
577 	}
578 
579 	if (safest_rx_cluster != MCLBYTES &&
580 #if MJUMPAGESIZE != MCLBYTES
581 	    safest_rx_cluster != MJUMPAGESIZE &&
582 #endif
583 	    safest_rx_cluster != MJUM9BYTES &&
584 	    safest_rx_cluster != MJUM16BYTES) {
585 		printf("Invalid hw.cxgbe.safest_rx_cluster value (%d),"
586 		    " using %d instead.\n", safest_rx_cluster, MJUMPAGESIZE);
587 		safest_rx_cluster = MJUMPAGESIZE;
588 	}
589 
590 	extfree_refs = counter_u64_alloc(M_WAITOK);
591 	extfree_rels = counter_u64_alloc(M_WAITOK);
592 	pullups = counter_u64_alloc(M_WAITOK);
593 	defrags = counter_u64_alloc(M_WAITOK);
594 	counter_u64_zero(extfree_refs);
595 	counter_u64_zero(extfree_rels);
596 	counter_u64_zero(pullups);
597 	counter_u64_zero(defrags);
598 
599 	t4_init_shared_cpl_handlers();
600 	t4_register_cpl_handler(CPL_FW4_MSG, handle_fw_msg);
601 	t4_register_cpl_handler(CPL_FW6_MSG, handle_fw_msg);
602 	t4_register_cpl_handler(CPL_SGE_EGR_UPDATE, handle_sge_egr_update);
603 #ifdef RATELIMIT
604 	t4_register_shared_cpl_handler(CPL_FW4_ACK, ethofld_fw4_ack,
605 	    CPL_COOKIE_ETHOFLD);
606 #endif
607 	t4_register_fw_msg_handler(FW6_TYPE_CMD_RPL, t4_handle_fw_rpl);
608 	t4_register_fw_msg_handler(FW6_TYPE_WRERR_RPL, t4_handle_wrerr_rpl);
609 }
610 
611 void
612 t4_sge_modunload(void)
613 {
614 
615 	counter_u64_free(extfree_refs);
616 	counter_u64_free(extfree_rels);
617 	counter_u64_free(pullups);
618 	counter_u64_free(defrags);
619 }
620 
621 uint64_t
622 t4_sge_extfree_refs(void)
623 {
624 	uint64_t refs, rels;
625 
626 	rels = counter_u64_fetch(extfree_rels);
627 	refs = counter_u64_fetch(extfree_refs);
628 
629 	return (refs - rels);
630 }
631 
632 /* max 4096 */
633 #define MAX_PACK_BOUNDARY 512
634 
635 static inline void
636 setup_pad_and_pack_boundaries(struct adapter *sc)
637 {
638 	uint32_t v, m;
639 	int pad, pack, pad_shift;
640 
641 	pad_shift = chip_id(sc) > CHELSIO_T5 ? X_T6_INGPADBOUNDARY_SHIFT :
642 	    X_INGPADBOUNDARY_SHIFT;
643 	pad = fl_pad;
644 	if (fl_pad < (1 << pad_shift) ||
645 	    fl_pad > (1 << (pad_shift + M_INGPADBOUNDARY)) ||
646 	    !powerof2(fl_pad)) {
647 		/*
648 		 * If there is any chance that we might use buffer packing and
649 		 * the chip is a T4, then pick 64 as the pad/pack boundary.  Set
650 		 * it to the minimum allowed in all other cases.
651 		 */
652 		pad = is_t4(sc) && buffer_packing ? 64 : 1 << pad_shift;
653 
654 		/*
655 		 * For fl_pad = 0 we'll still write a reasonable value to the
656 		 * register but all the freelists will opt out of padding.
657 		 * We'll complain here only if the user tried to set it to a
658 		 * value greater than 0 that was invalid.
659 		 */
660 		if (fl_pad > 0) {
661 			device_printf(sc->dev, "Invalid hw.cxgbe.fl_pad value"
662 			    " (%d), using %d instead.\n", fl_pad, pad);
663 		}
664 	}
665 	m = V_INGPADBOUNDARY(M_INGPADBOUNDARY);
666 	v = V_INGPADBOUNDARY(ilog2(pad) - pad_shift);
667 	t4_set_reg_field(sc, A_SGE_CONTROL, m, v);
668 
669 	if (is_t4(sc)) {
670 		if (fl_pack != -1 && fl_pack != pad) {
671 			/* Complain but carry on. */
672 			device_printf(sc->dev, "hw.cxgbe.fl_pack (%d) ignored,"
673 			    " using %d instead.\n", fl_pack, pad);
674 		}
675 		return;
676 	}
677 
678 	pack = fl_pack;
679 	if (fl_pack < 16 || fl_pack == 32 || fl_pack > 4096 ||
680 	    !powerof2(fl_pack)) {
681 		if (sc->params.pci.mps > MAX_PACK_BOUNDARY)
682 			pack = MAX_PACK_BOUNDARY;
683 		else
684 			pack = max(sc->params.pci.mps, CACHE_LINE_SIZE);
685 		MPASS(powerof2(pack));
686 		if (pack < 16)
687 			pack = 16;
688 		if (pack == 32)
689 			pack = 64;
690 		if (pack > 4096)
691 			pack = 4096;
692 		if (fl_pack != -1) {
693 			device_printf(sc->dev, "Invalid hw.cxgbe.fl_pack value"
694 			    " (%d), using %d instead.\n", fl_pack, pack);
695 		}
696 	}
697 	m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY);
698 	if (pack == 16)
699 		v = V_INGPACKBOUNDARY(0);
700 	else
701 		v = V_INGPACKBOUNDARY(ilog2(pack) - 5);
702 
703 	MPASS(!is_t4(sc));	/* T4 doesn't have SGE_CONTROL2 */
704 	t4_set_reg_field(sc, A_SGE_CONTROL2, m, v);
705 }
706 
707 /*
708  * adap->params.vpd.cclk must be set up before this is called.
709  */
710 void
711 t4_tweak_chip_settings(struct adapter *sc)
712 {
713 	int i, reg;
714 	uint32_t v, m;
715 	int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200};
716 	int timer_max = M_TIMERVALUE0 * 1000 / sc->params.vpd.cclk;
717 	int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */
718 	uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE);
719 	static int sw_buf_sizes[] = {
720 		MCLBYTES,
721 #if MJUMPAGESIZE != MCLBYTES
722 		MJUMPAGESIZE,
723 #endif
724 		MJUM9BYTES,
725 		MJUM16BYTES
726 	};
727 
728 	KASSERT(sc->flags & MASTER_PF,
729 	    ("%s: trying to change chip settings when not master.", __func__));
730 
731 	m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE;
732 	v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE |
733 	    V_EGRSTATUSPAGESIZE(spg_len == 128);
734 	t4_set_reg_field(sc, A_SGE_CONTROL, m, v);
735 
736 	setup_pad_and_pack_boundaries(sc);
737 
738 	v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) |
739 	    V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) |
740 	    V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) |
741 	    V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) |
742 	    V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) |
743 	    V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) |
744 	    V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) |
745 	    V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10);
746 	t4_write_reg(sc, A_SGE_HOST_PAGE_SIZE, v);
747 
748 	t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0, 4096);
749 	t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE1, 65536);
750 	reg = A_SGE_FL_BUFFER_SIZE2;
751 	for (i = 0; i < nitems(sw_buf_sizes); i++) {
752 		MPASS(reg <= A_SGE_FL_BUFFER_SIZE15);
753 		t4_write_reg(sc, reg, sw_buf_sizes[i]);
754 		reg += 4;
755 		MPASS(reg <= A_SGE_FL_BUFFER_SIZE15);
756 		t4_write_reg(sc, reg, sw_buf_sizes[i] - CL_METADATA_SIZE);
757 		reg += 4;
758 	}
759 
760 	v = V_THRESHOLD_0(intr_pktcount[0]) | V_THRESHOLD_1(intr_pktcount[1]) |
761 	    V_THRESHOLD_2(intr_pktcount[2]) | V_THRESHOLD_3(intr_pktcount[3]);
762 	t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD, v);
763 
764 	KASSERT(intr_timer[0] <= timer_max,
765 	    ("%s: not a single usable timer (%d, %d)", __func__, intr_timer[0],
766 	    timer_max));
767 	for (i = 1; i < nitems(intr_timer); i++) {
768 		KASSERT(intr_timer[i] >= intr_timer[i - 1],
769 		    ("%s: timers not listed in increasing order (%d)",
770 		    __func__, i));
771 
772 		while (intr_timer[i] > timer_max) {
773 			if (i == nitems(intr_timer) - 1) {
774 				intr_timer[i] = timer_max;
775 				break;
776 			}
777 			intr_timer[i] += intr_timer[i - 1];
778 			intr_timer[i] /= 2;
779 		}
780 	}
781 
782 	v = V_TIMERVALUE0(us_to_core_ticks(sc, intr_timer[0])) |
783 	    V_TIMERVALUE1(us_to_core_ticks(sc, intr_timer[1]));
784 	t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1, v);
785 	v = V_TIMERVALUE2(us_to_core_ticks(sc, intr_timer[2])) |
786 	    V_TIMERVALUE3(us_to_core_ticks(sc, intr_timer[3]));
787 	t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3, v);
788 	v = V_TIMERVALUE4(us_to_core_ticks(sc, intr_timer[4])) |
789 	    V_TIMERVALUE5(us_to_core_ticks(sc, intr_timer[5]));
790 	t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5, v);
791 
792 	if (chip_id(sc) >= CHELSIO_T6) {
793 		m = V_TSCALE(M_TSCALE);
794 		if (tscale == 1)
795 			v = 0;
796 		else
797 			v = V_TSCALE(tscale - 2);
798 		t4_set_reg_field(sc, A_SGE_ITP_CONTROL, m, v);
799 
800 		if (sc->debug_flags & DF_DISABLE_TCB_CACHE) {
801 			m = V_RDTHRESHOLD(M_RDTHRESHOLD) | F_WRTHRTHRESHEN |
802 			    V_WRTHRTHRESH(M_WRTHRTHRESH);
803 			t4_tp_pio_read(sc, &v, 1, A_TP_CMM_CONFIG, 1);
804 			v &= ~m;
805 			v |= V_RDTHRESHOLD(1) | F_WRTHRTHRESHEN |
806 			    V_WRTHRTHRESH(16);
807 			t4_tp_pio_write(sc, &v, 1, A_TP_CMM_CONFIG, 1);
808 		}
809 	}
810 
811 	/* 4K, 16K, 64K, 256K DDP "page sizes" for TDDP */
812 	v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6);
813 	t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, v);
814 
815 	/*
816 	 * 4K, 8K, 16K, 64K DDP "page sizes" for iSCSI DDP.  These have been
817 	 * chosen with MAXPHYS = 128K in mind.  The largest DDP buffer that we
818 	 * may have to deal with is MAXPHYS + 1 page.
819 	 */
820 	v = V_HPZ0(0) | V_HPZ1(1) | V_HPZ2(2) | V_HPZ3(4);
821 	t4_write_reg(sc, A_ULP_RX_ISCSI_PSZ, v);
822 
823 	/* We use multiple DDP page sizes both in plain-TOE and ISCSI modes. */
824 	m = v = F_TDDPTAGTCB | F_ISCSITAGTCB;
825 	t4_set_reg_field(sc, A_ULP_RX_CTL, m, v);
826 
827 	m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET |
828 	    F_RESETDDPOFFSET;
829 	v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET;
830 	t4_set_reg_field(sc, A_TP_PARA_REG5, m, v);
831 }
832 
833 /*
834  * SGE wants the buffer to be at least 64B and then a multiple of 16.  Its
835  * address mut be 16B aligned.  If padding is in use the buffer's start and end
836  * need to be aligned to the pad boundary as well.  We'll just make sure that
837  * the size is a multiple of the pad boundary here, it is up to the buffer
838  * allocation code to make sure the start of the buffer is aligned.
839  */
840 static inline int
841 hwsz_ok(struct adapter *sc, int hwsz)
842 {
843 	int mask = fl_pad ? sc->params.sge.pad_boundary - 1 : 16 - 1;
844 
845 	return (hwsz >= 64 && (hwsz & mask) == 0);
846 }
847 
848 /*
849  * Initialize the rx buffer sizes and figure out which zones the buffers will
850  * be allocated from.
851  */
852 void
853 t4_init_rx_buf_info(struct adapter *sc)
854 {
855 	struct sge *s = &sc->sge;
856 	struct sge_params *sp = &sc->params.sge;
857 	int i, j, n;
858 	static int sw_buf_sizes[] = {	/* Sorted by size */
859 		MCLBYTES,
860 #if MJUMPAGESIZE != MCLBYTES
861 		MJUMPAGESIZE,
862 #endif
863 		MJUM9BYTES,
864 		MJUM16BYTES
865 	};
866 	struct rx_buf_info *rxb;
867 
868 	s->safe_zidx = -1;
869 	rxb = &s->rx_buf_info[0];
870 	for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) {
871 		rxb->size1 = sw_buf_sizes[i];
872 		rxb->zone = m_getzone(rxb->size1);
873 		rxb->type = m_gettype(rxb->size1);
874 		rxb->size2 = 0;
875 		rxb->hwidx1 = -1;
876 		rxb->hwidx2 = -1;
877 		for (j = 0; j < SGE_FLBUF_SIZES; j++) {
878 			int hwsize = sp->sge_fl_buffer_size[j];
879 
880 			if (!hwsz_ok(sc, hwsize))
881 				continue;
882 
883 			/* hwidx for size1 */
884 			if (rxb->hwidx1 == -1 && rxb->size1 == hwsize)
885 				rxb->hwidx1 = j;
886 
887 			/* hwidx for size2 (buffer packing) */
888 			if (rxb->size1 - CL_METADATA_SIZE < hwsize)
889 				continue;
890 			n = rxb->size1 - hwsize - CL_METADATA_SIZE;
891 			if (n == 0) {
892 				rxb->hwidx2 = j;
893 				rxb->size2 = hwsize;
894 				break;	/* stop looking */
895 			}
896 			if (rxb->hwidx2 != -1) {
897 				if (n < sp->sge_fl_buffer_size[rxb->hwidx2] -
898 				    hwsize - CL_METADATA_SIZE) {
899 					rxb->hwidx2 = j;
900 					rxb->size2 = hwsize;
901 				}
902 			} else if (n <= 2 * CL_METADATA_SIZE) {
903 				rxb->hwidx2 = j;
904 				rxb->size2 = hwsize;
905 			}
906 		}
907 		if (rxb->hwidx2 != -1)
908 			sc->flags |= BUF_PACKING_OK;
909 		if (s->safe_zidx == -1 && rxb->size1 == safest_rx_cluster)
910 			s->safe_zidx = i;
911 	}
912 }
913 
914 /*
915  * Verify some basic SGE settings for the PF and VF driver, and other
916  * miscellaneous settings for the PF driver.
917  */
918 int
919 t4_verify_chip_settings(struct adapter *sc)
920 {
921 	struct sge_params *sp = &sc->params.sge;
922 	uint32_t m, v, r;
923 	int rc = 0;
924 	const uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE);
925 
926 	m = F_RXPKTCPLMODE;
927 	v = F_RXPKTCPLMODE;
928 	r = sp->sge_control;
929 	if ((r & m) != v) {
930 		device_printf(sc->dev, "invalid SGE_CONTROL(0x%x)\n", r);
931 		rc = EINVAL;
932 	}
933 
934 	/*
935 	 * If this changes then every single use of PAGE_SHIFT in the driver
936 	 * needs to be carefully reviewed for PAGE_SHIFT vs sp->page_shift.
937 	 */
938 	if (sp->page_shift != PAGE_SHIFT) {
939 		device_printf(sc->dev, "invalid SGE_HOST_PAGE_SIZE(0x%x)\n", r);
940 		rc = EINVAL;
941 	}
942 
943 	if (sc->flags & IS_VF)
944 		return (0);
945 
946 	v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6);
947 	r = t4_read_reg(sc, A_ULP_RX_TDDP_PSZ);
948 	if (r != v) {
949 		device_printf(sc->dev, "invalid ULP_RX_TDDP_PSZ(0x%x)\n", r);
950 		if (sc->vres.ddp.size != 0)
951 			rc = EINVAL;
952 	}
953 
954 	m = v = F_TDDPTAGTCB;
955 	r = t4_read_reg(sc, A_ULP_RX_CTL);
956 	if ((r & m) != v) {
957 		device_printf(sc->dev, "invalid ULP_RX_CTL(0x%x)\n", r);
958 		if (sc->vres.ddp.size != 0)
959 			rc = EINVAL;
960 	}
961 
962 	m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET |
963 	    F_RESETDDPOFFSET;
964 	v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET;
965 	r = t4_read_reg(sc, A_TP_PARA_REG5);
966 	if ((r & m) != v) {
967 		device_printf(sc->dev, "invalid TP_PARA_REG5(0x%x)\n", r);
968 		if (sc->vres.ddp.size != 0)
969 			rc = EINVAL;
970 	}
971 
972 	return (rc);
973 }
974 
975 int
976 t4_create_dma_tag(struct adapter *sc)
977 {
978 	int rc;
979 
980 	rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0,
981 	    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE,
982 	    BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL,
983 	    NULL, &sc->dmat);
984 	if (rc != 0) {
985 		device_printf(sc->dev,
986 		    "failed to create main DMA tag: %d\n", rc);
987 	}
988 
989 	return (rc);
990 }
991 
992 void
993 t4_sge_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx,
994     struct sysctl_oid_list *children)
995 {
996 	struct sge_params *sp = &sc->params.sge;
997 
998 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "buffer_sizes",
999 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
1000 	    sysctl_bufsizes, "A", "freelist buffer sizes");
1001 
1002 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pktshift", CTLFLAG_RD,
1003 	    NULL, sp->fl_pktshift, "payload DMA offset in rx buffer (bytes)");
1004 
1005 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pad", CTLFLAG_RD,
1006 	    NULL, sp->pad_boundary, "payload pad boundary (bytes)");
1007 
1008 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "spg_len", CTLFLAG_RD,
1009 	    NULL, sp->spg_len, "status page size (bytes)");
1010 
1011 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_drop", CTLFLAG_RD,
1012 	    NULL, cong_drop, "congestion drop setting");
1013 
1014 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pack", CTLFLAG_RD,
1015 	    NULL, sp->pack_boundary, "payload pack boundary (bytes)");
1016 }
1017 
1018 int
1019 t4_destroy_dma_tag(struct adapter *sc)
1020 {
1021 	if (sc->dmat)
1022 		bus_dma_tag_destroy(sc->dmat);
1023 
1024 	return (0);
1025 }
1026 
1027 /*
1028  * Allocate and initialize the firmware event queue, control queues, and special
1029  * purpose rx queues owned by the adapter.
1030  *
1031  * Returns errno on failure.  Resources allocated up to that point may still be
1032  * allocated.  Caller is responsible for cleanup in case this function fails.
1033  */
1034 int
1035 t4_setup_adapter_queues(struct adapter *sc)
1036 {
1037 	int rc, i;
1038 
1039 	ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
1040 
1041 	/*
1042 	 * Firmware event queue
1043 	 */
1044 	rc = alloc_fwq(sc);
1045 	if (rc != 0)
1046 		return (rc);
1047 
1048 	/*
1049 	 * That's all for the VF driver.
1050 	 */
1051 	if (sc->flags & IS_VF)
1052 		return (rc);
1053 
1054 	/*
1055 	 * XXX: General purpose rx queues, one per port.
1056 	 */
1057 
1058 	/*
1059 	 * Control queues, one per port.
1060 	 */
1061 	for_each_port(sc, i) {
1062 		rc = alloc_ctrlq(sc, i);
1063 		if (rc != 0)
1064 			return (rc);
1065 	}
1066 
1067 	return (rc);
1068 }
1069 
1070 /*
1071  * Idempotent
1072  */
1073 int
1074 t4_teardown_adapter_queues(struct adapter *sc)
1075 {
1076 	int i;
1077 
1078 	ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
1079 
1080 	if (!(sc->flags & IS_VF)) {
1081 		for_each_port(sc, i)
1082 			free_ctrlq(sc, i);
1083 	}
1084 	free_fwq(sc);
1085 
1086 	return (0);
1087 }
1088 
1089 /* Maximum payload that could arrive with a single iq descriptor. */
1090 static inline int
1091 max_rx_payload(struct adapter *sc, struct ifnet *ifp, const bool ofld)
1092 {
1093 	int maxp;
1094 
1095 	/* large enough even when hw VLAN extraction is disabled */
1096 	maxp = sc->params.sge.fl_pktshift + ETHER_HDR_LEN +
1097 	    ETHER_VLAN_ENCAP_LEN + ifp->if_mtu;
1098 	if (ofld && sc->tt.tls && sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS &&
1099 	    maxp < sc->params.tp.max_rx_pdu)
1100 		maxp = sc->params.tp.max_rx_pdu;
1101 	return (maxp);
1102 }
1103 
1104 int
1105 t4_setup_vi_queues(struct vi_info *vi)
1106 {
1107 	int rc = 0, i, intr_idx;
1108 	struct sge_rxq *rxq;
1109 	struct sge_txq *txq;
1110 #ifdef TCP_OFFLOAD
1111 	struct sge_ofld_rxq *ofld_rxq;
1112 #endif
1113 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1114 	struct sge_ofld_txq *ofld_txq;
1115 #endif
1116 #ifdef DEV_NETMAP
1117 	int saved_idx, iqidx;
1118 	struct sge_nm_rxq *nm_rxq;
1119 	struct sge_nm_txq *nm_txq;
1120 #endif
1121 	struct adapter *sc = vi->adapter;
1122 	struct ifnet *ifp = vi->ifp;
1123 	int maxp;
1124 
1125 	/* Interrupt vector to start from (when using multiple vectors) */
1126 	intr_idx = vi->first_intr;
1127 
1128 #ifdef DEV_NETMAP
1129 	saved_idx = intr_idx;
1130 	if (ifp->if_capabilities & IFCAP_NETMAP) {
1131 
1132 		/* netmap is supported with direct interrupts only. */
1133 		MPASS(!forwarding_intr_to_fwq(sc));
1134 		MPASS(vi->first_intr >= 0);
1135 
1136 		/*
1137 		 * We don't have buffers to back the netmap rx queues
1138 		 * right now so we create the queues in a way that
1139 		 * doesn't set off any congestion signal in the chip.
1140 		 */
1141 		for_each_nm_rxq(vi, i, nm_rxq) {
1142 			rc = alloc_nm_rxq(vi, nm_rxq, intr_idx, i);
1143 			if (rc != 0)
1144 				goto done;
1145 			intr_idx++;
1146 		}
1147 
1148 		for_each_nm_txq(vi, i, nm_txq) {
1149 			iqidx = vi->first_nm_rxq + (i % vi->nnmrxq);
1150 			rc = alloc_nm_txq(vi, nm_txq, iqidx, i);
1151 			if (rc != 0)
1152 				goto done;
1153 		}
1154 	}
1155 
1156 	/* Normal rx queues and netmap rx queues share the same interrupts. */
1157 	intr_idx = saved_idx;
1158 #endif
1159 
1160 	/*
1161 	 * Allocate rx queues first because a default iqid is required when
1162 	 * creating a tx queue.
1163 	 */
1164 	maxp = max_rx_payload(sc, ifp, false);
1165 	for_each_rxq(vi, i, rxq) {
1166 		rc = alloc_rxq(vi, rxq, i, intr_idx, maxp);
1167 		if (rc != 0)
1168 			goto done;
1169 		if (!forwarding_intr_to_fwq(sc))
1170 			intr_idx++;
1171 	}
1172 #ifdef DEV_NETMAP
1173 	if (ifp->if_capabilities & IFCAP_NETMAP)
1174 		intr_idx = saved_idx + max(vi->nrxq, vi->nnmrxq);
1175 #endif
1176 #ifdef TCP_OFFLOAD
1177 	maxp = max_rx_payload(sc, ifp, true);
1178 	for_each_ofld_rxq(vi, i, ofld_rxq) {
1179 		rc = alloc_ofld_rxq(vi, ofld_rxq, i, intr_idx, maxp);
1180 		if (rc != 0)
1181 			goto done;
1182 		if (!forwarding_intr_to_fwq(sc))
1183 			intr_idx++;
1184 	}
1185 #endif
1186 
1187 	/*
1188 	 * Now the tx queues.
1189 	 */
1190 	for_each_txq(vi, i, txq) {
1191 		rc = alloc_txq(vi, txq, i);
1192 		if (rc != 0)
1193 			goto done;
1194 	}
1195 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1196 	for_each_ofld_txq(vi, i, ofld_txq) {
1197 		rc = alloc_ofld_txq(vi, ofld_txq, i);
1198 		if (rc != 0)
1199 			goto done;
1200 	}
1201 #endif
1202 done:
1203 	if (rc)
1204 		t4_teardown_vi_queues(vi);
1205 
1206 	return (rc);
1207 }
1208 
1209 /*
1210  * Idempotent
1211  */
1212 int
1213 t4_teardown_vi_queues(struct vi_info *vi)
1214 {
1215 	int i;
1216 	struct sge_rxq *rxq;
1217 	struct sge_txq *txq;
1218 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1219 	struct sge_ofld_txq *ofld_txq;
1220 #endif
1221 #ifdef TCP_OFFLOAD
1222 	struct sge_ofld_rxq *ofld_rxq;
1223 #endif
1224 #ifdef DEV_NETMAP
1225 	struct sge_nm_rxq *nm_rxq;
1226 	struct sge_nm_txq *nm_txq;
1227 #endif
1228 
1229 #ifdef DEV_NETMAP
1230 	if (vi->ifp->if_capabilities & IFCAP_NETMAP) {
1231 		for_each_nm_txq(vi, i, nm_txq) {
1232 			free_nm_txq(vi, nm_txq);
1233 		}
1234 
1235 		for_each_nm_rxq(vi, i, nm_rxq) {
1236 			free_nm_rxq(vi, nm_rxq);
1237 		}
1238 	}
1239 #endif
1240 
1241 	/*
1242 	 * Take down all the tx queues first, as they reference the rx queues
1243 	 * (for egress updates, etc.).
1244 	 */
1245 
1246 	for_each_txq(vi, i, txq) {
1247 		free_txq(vi, txq);
1248 	}
1249 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1250 	for_each_ofld_txq(vi, i, ofld_txq) {
1251 		free_ofld_txq(vi, ofld_txq);
1252 	}
1253 #endif
1254 
1255 	/*
1256 	 * Then take down the rx queues.
1257 	 */
1258 
1259 	for_each_rxq(vi, i, rxq) {
1260 		free_rxq(vi, rxq);
1261 	}
1262 #ifdef TCP_OFFLOAD
1263 	for_each_ofld_rxq(vi, i, ofld_rxq) {
1264 		free_ofld_rxq(vi, ofld_rxq);
1265 	}
1266 #endif
1267 
1268 	return (0);
1269 }
1270 
1271 /*
1272  * Interrupt handler when the driver is using only 1 interrupt.  This is a very
1273  * unusual scenario.
1274  *
1275  * a) Deals with errors, if any.
1276  * b) Services firmware event queue, which is taking interrupts for all other
1277  *    queues.
1278  */
1279 void
1280 t4_intr_all(void *arg)
1281 {
1282 	struct adapter *sc = arg;
1283 	struct sge_iq *fwq = &sc->sge.fwq;
1284 
1285 	MPASS(sc->intr_count == 1);
1286 
1287 	if (sc->intr_type == INTR_INTX)
1288 		t4_write_reg(sc, MYPF_REG(A_PCIE_PF_CLI), 0);
1289 
1290 	t4_intr_err(arg);
1291 	t4_intr_evt(fwq);
1292 }
1293 
1294 /*
1295  * Interrupt handler for errors (installed directly when multiple interrupts are
1296  * being used, or called by t4_intr_all).
1297  */
1298 void
1299 t4_intr_err(void *arg)
1300 {
1301 	struct adapter *sc = arg;
1302 	uint32_t v;
1303 	const bool verbose = (sc->debug_flags & DF_VERBOSE_SLOWINTR) != 0;
1304 
1305 	if (sc->flags & ADAP_ERR)
1306 		return;
1307 
1308 	v = t4_read_reg(sc, MYPF_REG(A_PL_PF_INT_CAUSE));
1309 	if (v & F_PFSW) {
1310 		sc->swintr++;
1311 		t4_write_reg(sc, MYPF_REG(A_PL_PF_INT_CAUSE), v);
1312 	}
1313 
1314 	t4_slow_intr_handler(sc, verbose);
1315 }
1316 
1317 /*
1318  * Interrupt handler for iq-only queues.  The firmware event queue is the only
1319  * such queue right now.
1320  */
1321 void
1322 t4_intr_evt(void *arg)
1323 {
1324 	struct sge_iq *iq = arg;
1325 
1326 	if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) {
1327 		service_iq(iq, 0);
1328 		(void) atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE);
1329 	}
1330 }
1331 
1332 /*
1333  * Interrupt handler for iq+fl queues.
1334  */
1335 void
1336 t4_intr(void *arg)
1337 {
1338 	struct sge_iq *iq = arg;
1339 
1340 	if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) {
1341 		service_iq_fl(iq, 0);
1342 		(void) atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE);
1343 	}
1344 }
1345 
1346 #ifdef DEV_NETMAP
1347 /*
1348  * Interrupt handler for netmap rx queues.
1349  */
1350 void
1351 t4_nm_intr(void *arg)
1352 {
1353 	struct sge_nm_rxq *nm_rxq = arg;
1354 
1355 	if (atomic_cmpset_int(&nm_rxq->nm_state, NM_ON, NM_BUSY)) {
1356 		service_nm_rxq(nm_rxq);
1357 		(void) atomic_cmpset_int(&nm_rxq->nm_state, NM_BUSY, NM_ON);
1358 	}
1359 }
1360 
1361 /*
1362  * Interrupt handler for vectors shared between NIC and netmap rx queues.
1363  */
1364 void
1365 t4_vi_intr(void *arg)
1366 {
1367 	struct irq *irq = arg;
1368 
1369 	MPASS(irq->nm_rxq != NULL);
1370 	t4_nm_intr(irq->nm_rxq);
1371 
1372 	MPASS(irq->rxq != NULL);
1373 	t4_intr(irq->rxq);
1374 }
1375 #endif
1376 
1377 /*
1378  * Deals with interrupts on an iq-only (no freelist) queue.
1379  */
1380 static int
1381 service_iq(struct sge_iq *iq, int budget)
1382 {
1383 	struct sge_iq *q;
1384 	struct adapter *sc = iq->adapter;
1385 	struct iq_desc *d = &iq->desc[iq->cidx];
1386 	int ndescs = 0, limit;
1387 	int rsp_type;
1388 	uint32_t lq;
1389 	STAILQ_HEAD(, sge_iq) iql = STAILQ_HEAD_INITIALIZER(iql);
1390 
1391 	KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq));
1392 	KASSERT((iq->flags & IQ_HAS_FL) == 0,
1393 	    ("%s: called for iq %p with fl (iq->flags 0x%x)", __func__, iq,
1394 	    iq->flags));
1395 	MPASS((iq->flags & IQ_ADJ_CREDIT) == 0);
1396 	MPASS((iq->flags & IQ_LRO_ENABLED) == 0);
1397 
1398 	limit = budget ? budget : iq->qsize / 16;
1399 
1400 	/*
1401 	 * We always come back and check the descriptor ring for new indirect
1402 	 * interrupts and other responses after running a single handler.
1403 	 */
1404 	for (;;) {
1405 		while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) {
1406 
1407 			rmb();
1408 
1409 			rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen);
1410 			lq = be32toh(d->rsp.pldbuflen_qid);
1411 
1412 			switch (rsp_type) {
1413 			case X_RSPD_TYPE_FLBUF:
1414 				panic("%s: data for an iq (%p) with no freelist",
1415 				    __func__, iq);
1416 
1417 				/* NOTREACHED */
1418 
1419 			case X_RSPD_TYPE_CPL:
1420 				KASSERT(d->rss.opcode < NUM_CPL_CMDS,
1421 				    ("%s: bad opcode %02x.", __func__,
1422 				    d->rss.opcode));
1423 				t4_cpl_handler[d->rss.opcode](iq, &d->rss, NULL);
1424 				break;
1425 
1426 			case X_RSPD_TYPE_INTR:
1427 				/*
1428 				 * There are 1K interrupt-capable queues (qids 0
1429 				 * through 1023).  A response type indicating a
1430 				 * forwarded interrupt with a qid >= 1K is an
1431 				 * iWARP async notification.
1432 				 */
1433 				if (__predict_true(lq >= 1024)) {
1434 					t4_an_handler(iq, &d->rsp);
1435 					break;
1436 				}
1437 
1438 				q = sc->sge.iqmap[lq - sc->sge.iq_start -
1439 				    sc->sge.iq_base];
1440 				if (atomic_cmpset_int(&q->state, IQS_IDLE,
1441 				    IQS_BUSY)) {
1442 					if (service_iq_fl(q, q->qsize / 16) == 0) {
1443 						(void) atomic_cmpset_int(&q->state,
1444 						    IQS_BUSY, IQS_IDLE);
1445 					} else {
1446 						STAILQ_INSERT_TAIL(&iql, q,
1447 						    link);
1448 					}
1449 				}
1450 				break;
1451 
1452 			default:
1453 				KASSERT(0,
1454 				    ("%s: illegal response type %d on iq %p",
1455 				    __func__, rsp_type, iq));
1456 				log(LOG_ERR,
1457 				    "%s: illegal response type %d on iq %p",
1458 				    device_get_nameunit(sc->dev), rsp_type, iq);
1459 				break;
1460 			}
1461 
1462 			d++;
1463 			if (__predict_false(++iq->cidx == iq->sidx)) {
1464 				iq->cidx = 0;
1465 				iq->gen ^= F_RSPD_GEN;
1466 				d = &iq->desc[0];
1467 			}
1468 			if (__predict_false(++ndescs == limit)) {
1469 				t4_write_reg(sc, sc->sge_gts_reg,
1470 				    V_CIDXINC(ndescs) |
1471 				    V_INGRESSQID(iq->cntxt_id) |
1472 				    V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX)));
1473 				ndescs = 0;
1474 
1475 				if (budget) {
1476 					return (EINPROGRESS);
1477 				}
1478 			}
1479 		}
1480 
1481 		if (STAILQ_EMPTY(&iql))
1482 			break;
1483 
1484 		/*
1485 		 * Process the head only, and send it to the back of the list if
1486 		 * it's still not done.
1487 		 */
1488 		q = STAILQ_FIRST(&iql);
1489 		STAILQ_REMOVE_HEAD(&iql, link);
1490 		if (service_iq_fl(q, q->qsize / 8) == 0)
1491 			(void) atomic_cmpset_int(&q->state, IQS_BUSY, IQS_IDLE);
1492 		else
1493 			STAILQ_INSERT_TAIL(&iql, q, link);
1494 	}
1495 
1496 	t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) |
1497 	    V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params));
1498 
1499 	return (0);
1500 }
1501 
1502 #if defined(INET) || defined(INET6)
1503 static inline int
1504 sort_before_lro(struct lro_ctrl *lro)
1505 {
1506 
1507 	return (lro->lro_mbuf_max != 0);
1508 }
1509 #endif
1510 
1511 static inline uint64_t
1512 last_flit_to_ns(struct adapter *sc, uint64_t lf)
1513 {
1514 	uint64_t n = be64toh(lf) & 0xfffffffffffffff;	/* 60b, not 64b. */
1515 
1516 	if (n > UINT64_MAX / 1000000)
1517 		return (n / sc->params.vpd.cclk * 1000000);
1518 	else
1519 		return (n * 1000000 / sc->params.vpd.cclk);
1520 }
1521 
1522 static inline void
1523 move_to_next_rxbuf(struct sge_fl *fl)
1524 {
1525 
1526 	fl->rx_offset = 0;
1527 	if (__predict_false((++fl->cidx & 7) == 0)) {
1528 		uint16_t cidx = fl->cidx >> 3;
1529 
1530 		if (__predict_false(cidx == fl->sidx))
1531 			fl->cidx = cidx = 0;
1532 		fl->hw_cidx = cidx;
1533 	}
1534 }
1535 
1536 /*
1537  * Deals with interrupts on an iq+fl queue.
1538  */
1539 static int
1540 service_iq_fl(struct sge_iq *iq, int budget)
1541 {
1542 	struct sge_rxq *rxq = iq_to_rxq(iq);
1543 	struct sge_fl *fl;
1544 	struct adapter *sc = iq->adapter;
1545 	struct iq_desc *d = &iq->desc[iq->cidx];
1546 	int ndescs, limit;
1547 	int rsp_type, starved;
1548 	uint32_t lq;
1549 	uint16_t fl_hw_cidx;
1550 	struct mbuf *m0;
1551 #if defined(INET) || defined(INET6)
1552 	const struct timeval lro_timeout = {0, sc->lro_timeout};
1553 	struct lro_ctrl *lro = &rxq->lro;
1554 #endif
1555 
1556 	KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq));
1557 	MPASS(iq->flags & IQ_HAS_FL);
1558 
1559 	ndescs = 0;
1560 #if defined(INET) || defined(INET6)
1561 	if (iq->flags & IQ_ADJ_CREDIT) {
1562 		MPASS(sort_before_lro(lro));
1563 		iq->flags &= ~IQ_ADJ_CREDIT;
1564 		if ((d->rsp.u.type_gen & F_RSPD_GEN) != iq->gen) {
1565 			tcp_lro_flush_all(lro);
1566 			t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(1) |
1567 			    V_INGRESSQID((u32)iq->cntxt_id) |
1568 			    V_SEINTARM(iq->intr_params));
1569 			return (0);
1570 		}
1571 		ndescs = 1;
1572 	}
1573 #else
1574 	MPASS((iq->flags & IQ_ADJ_CREDIT) == 0);
1575 #endif
1576 
1577 	limit = budget ? budget : iq->qsize / 16;
1578 	fl = &rxq->fl;
1579 	fl_hw_cidx = fl->hw_cidx;	/* stable snapshot */
1580 	while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) {
1581 
1582 		rmb();
1583 
1584 		m0 = NULL;
1585 		rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen);
1586 		lq = be32toh(d->rsp.pldbuflen_qid);
1587 
1588 		switch (rsp_type) {
1589 		case X_RSPD_TYPE_FLBUF:
1590 			if (lq & F_RSPD_NEWBUF) {
1591 				if (fl->rx_offset > 0)
1592 					move_to_next_rxbuf(fl);
1593 				lq = G_RSPD_LEN(lq);
1594 			}
1595 			if (IDXDIFF(fl->hw_cidx, fl_hw_cidx, fl->sidx) > 4) {
1596 				FL_LOCK(fl);
1597 				refill_fl(sc, fl, 64);
1598 				FL_UNLOCK(fl);
1599 				fl_hw_cidx = fl->hw_cidx;
1600 			}
1601 
1602 			if (d->rss.opcode == CPL_RX_PKT) {
1603 				if (__predict_true(eth_rx(sc, rxq, d, lq) == 0))
1604 					break;
1605 				goto out;
1606 			}
1607 			m0 = get_fl_payload(sc, fl, lq);
1608 			if (__predict_false(m0 == NULL))
1609 				goto out;
1610 
1611 			/* fall through */
1612 
1613 		case X_RSPD_TYPE_CPL:
1614 			KASSERT(d->rss.opcode < NUM_CPL_CMDS,
1615 			    ("%s: bad opcode %02x.", __func__, d->rss.opcode));
1616 			t4_cpl_handler[d->rss.opcode](iq, &d->rss, m0);
1617 			break;
1618 
1619 		case X_RSPD_TYPE_INTR:
1620 
1621 			/*
1622 			 * There are 1K interrupt-capable queues (qids 0
1623 			 * through 1023).  A response type indicating a
1624 			 * forwarded interrupt with a qid >= 1K is an
1625 			 * iWARP async notification.  That is the only
1626 			 * acceptable indirect interrupt on this queue.
1627 			 */
1628 			if (__predict_false(lq < 1024)) {
1629 				panic("%s: indirect interrupt on iq_fl %p "
1630 				    "with qid %u", __func__, iq, lq);
1631 			}
1632 
1633 			t4_an_handler(iq, &d->rsp);
1634 			break;
1635 
1636 		default:
1637 			KASSERT(0, ("%s: illegal response type %d on iq %p",
1638 			    __func__, rsp_type, iq));
1639 			log(LOG_ERR, "%s: illegal response type %d on iq %p",
1640 			    device_get_nameunit(sc->dev), rsp_type, iq);
1641 			break;
1642 		}
1643 
1644 		d++;
1645 		if (__predict_false(++iq->cidx == iq->sidx)) {
1646 			iq->cidx = 0;
1647 			iq->gen ^= F_RSPD_GEN;
1648 			d = &iq->desc[0];
1649 		}
1650 		if (__predict_false(++ndescs == limit)) {
1651 			t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) |
1652 			    V_INGRESSQID(iq->cntxt_id) |
1653 			    V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX)));
1654 
1655 #if defined(INET) || defined(INET6)
1656 			if (iq->flags & IQ_LRO_ENABLED &&
1657 			    !sort_before_lro(lro) &&
1658 			    sc->lro_timeout != 0) {
1659 				tcp_lro_flush_inactive(lro, &lro_timeout);
1660 			}
1661 #endif
1662 			if (budget)
1663 				return (EINPROGRESS);
1664 			ndescs = 0;
1665 		}
1666 	}
1667 out:
1668 #if defined(INET) || defined(INET6)
1669 	if (iq->flags & IQ_LRO_ENABLED) {
1670 		if (ndescs > 0 && lro->lro_mbuf_count > 8) {
1671 			MPASS(sort_before_lro(lro));
1672 			/* hold back one credit and don't flush LRO state */
1673 			iq->flags |= IQ_ADJ_CREDIT;
1674 			ndescs--;
1675 		} else {
1676 			tcp_lro_flush_all(lro);
1677 		}
1678 	}
1679 #endif
1680 
1681 	t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) |
1682 	    V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params));
1683 
1684 	FL_LOCK(fl);
1685 	starved = refill_fl(sc, fl, 64);
1686 	FL_UNLOCK(fl);
1687 	if (__predict_false(starved != 0))
1688 		add_fl_to_sfl(sc, fl);
1689 
1690 	return (0);
1691 }
1692 
1693 static inline struct cluster_metadata *
1694 cl_metadata(struct fl_sdesc *sd)
1695 {
1696 
1697 	return ((void *)(sd->cl + sd->moff));
1698 }
1699 
1700 static void
1701 rxb_free(struct mbuf *m)
1702 {
1703 	struct cluster_metadata *clm = m->m_ext.ext_arg1;
1704 
1705 	uma_zfree(clm->zone, clm->cl);
1706 	counter_u64_add(extfree_rels, 1);
1707 }
1708 
1709 /*
1710  * The mbuf returned comes from zone_muf and carries the payload in one of these
1711  * ways
1712  * a) complete frame inside the mbuf
1713  * b) m_cljset (for clusters without metadata)
1714  * d) m_extaddref (cluster with metadata)
1715  */
1716 static struct mbuf *
1717 get_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset,
1718     int remaining)
1719 {
1720 	struct mbuf *m;
1721 	struct fl_sdesc *sd = &fl->sdesc[fl->cidx];
1722 	struct rx_buf_info *rxb = &sc->sge.rx_buf_info[sd->zidx];
1723 	struct cluster_metadata *clm;
1724 	int len, blen;
1725 	caddr_t payload;
1726 
1727 	if (fl->flags & FL_BUF_PACKING) {
1728 		u_int l, pad;
1729 
1730 		blen = rxb->size2 - fl->rx_offset;	/* max possible in this buf */
1731 		len = min(remaining, blen);
1732 		payload = sd->cl + fl->rx_offset;
1733 
1734 		l = fr_offset + len;
1735 		pad = roundup2(l, fl->buf_boundary) - l;
1736 		if (fl->rx_offset + len + pad < rxb->size2)
1737 			blen = len + pad;
1738 		MPASS(fl->rx_offset + blen <= rxb->size2);
1739 	} else {
1740 		MPASS(fl->rx_offset == 0);	/* not packing */
1741 		blen = rxb->size1;
1742 		len = min(remaining, blen);
1743 		payload = sd->cl;
1744 	}
1745 
1746 	if (fr_offset == 0) {
1747 		m = m_gethdr(M_NOWAIT, MT_DATA);
1748 		if (__predict_false(m == NULL))
1749 			return (NULL);
1750 		m->m_pkthdr.len = remaining;
1751 	} else {
1752 		m = m_get(M_NOWAIT, MT_DATA);
1753 		if (__predict_false(m == NULL))
1754 			return (NULL);
1755 	}
1756 	m->m_len = len;
1757 
1758 	if (sc->sc_do_rxcopy && len < RX_COPY_THRESHOLD) {
1759 		/* copy data to mbuf */
1760 		bcopy(payload, mtod(m, caddr_t), len);
1761 		if (fl->flags & FL_BUF_PACKING) {
1762 			fl->rx_offset += blen;
1763 			MPASS(fl->rx_offset <= rxb->size2);
1764 			if (fl->rx_offset < rxb->size2)
1765 				return (m);	/* without advancing the cidx */
1766 		}
1767 	} else if (fl->flags & FL_BUF_PACKING) {
1768 		clm = cl_metadata(sd);
1769 		if (sd->nmbuf++ == 0) {
1770 			clm->refcount = 1;
1771 			clm->zone = rxb->zone;
1772 			clm->cl = sd->cl;
1773 			counter_u64_add(extfree_refs, 1);
1774 		}
1775 		m_extaddref(m, payload, blen, &clm->refcount, rxb_free, clm,
1776 		    NULL);
1777 
1778 		fl->rx_offset += blen;
1779 		MPASS(fl->rx_offset <= rxb->size2);
1780 		if (fl->rx_offset < rxb->size2)
1781 			return (m);	/* without advancing the cidx */
1782 	} else {
1783 		m_cljset(m, sd->cl, rxb->type);
1784 		sd->cl = NULL;	/* consumed, not a recycle candidate */
1785 	}
1786 
1787 	move_to_next_rxbuf(fl);
1788 
1789 	return (m);
1790 }
1791 
1792 static struct mbuf *
1793 get_fl_payload(struct adapter *sc, struct sge_fl *fl, const u_int plen)
1794 {
1795 	struct mbuf *m0, *m, **pnext;
1796 	u_int remaining;
1797 
1798 	if (__predict_false(fl->flags & FL_BUF_RESUME)) {
1799 		M_ASSERTPKTHDR(fl->m0);
1800 		MPASS(fl->m0->m_pkthdr.len == plen);
1801 		MPASS(fl->remaining < plen);
1802 
1803 		m0 = fl->m0;
1804 		pnext = fl->pnext;
1805 		remaining = fl->remaining;
1806 		fl->flags &= ~FL_BUF_RESUME;
1807 		goto get_segment;
1808 	}
1809 
1810 	/*
1811 	 * Payload starts at rx_offset in the current hw buffer.  Its length is
1812 	 * 'len' and it may span multiple hw buffers.
1813 	 */
1814 
1815 	m0 = get_scatter_segment(sc, fl, 0, plen);
1816 	if (m0 == NULL)
1817 		return (NULL);
1818 	remaining = plen - m0->m_len;
1819 	pnext = &m0->m_next;
1820 	while (remaining > 0) {
1821 get_segment:
1822 		MPASS(fl->rx_offset == 0);
1823 		m = get_scatter_segment(sc, fl, plen - remaining, remaining);
1824 		if (__predict_false(m == NULL)) {
1825 			fl->m0 = m0;
1826 			fl->pnext = pnext;
1827 			fl->remaining = remaining;
1828 			fl->flags |= FL_BUF_RESUME;
1829 			return (NULL);
1830 		}
1831 		*pnext = m;
1832 		pnext = &m->m_next;
1833 		remaining -= m->m_len;
1834 	}
1835 	*pnext = NULL;
1836 
1837 	M_ASSERTPKTHDR(m0);
1838 	return (m0);
1839 }
1840 
1841 static int
1842 skip_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset,
1843     int remaining)
1844 {
1845 	struct fl_sdesc *sd = &fl->sdesc[fl->cidx];
1846 	struct rx_buf_info *rxb = &sc->sge.rx_buf_info[sd->zidx];
1847 	int len, blen;
1848 
1849 	if (fl->flags & FL_BUF_PACKING) {
1850 		u_int l, pad;
1851 
1852 		blen = rxb->size2 - fl->rx_offset;	/* max possible in this buf */
1853 		len = min(remaining, blen);
1854 
1855 		l = fr_offset + len;
1856 		pad = roundup2(l, fl->buf_boundary) - l;
1857 		if (fl->rx_offset + len + pad < rxb->size2)
1858 			blen = len + pad;
1859 		fl->rx_offset += blen;
1860 		MPASS(fl->rx_offset <= rxb->size2);
1861 		if (fl->rx_offset < rxb->size2)
1862 			return (len);	/* without advancing the cidx */
1863 	} else {
1864 		MPASS(fl->rx_offset == 0);	/* not packing */
1865 		blen = rxb->size1;
1866 		len = min(remaining, blen);
1867 	}
1868 	move_to_next_rxbuf(fl);
1869 	return (len);
1870 }
1871 
1872 static inline void
1873 skip_fl_payload(struct adapter *sc, struct sge_fl *fl, int plen)
1874 {
1875 	int remaining, fr_offset, len;
1876 
1877 	fr_offset = 0;
1878 	remaining = plen;
1879 	while (remaining > 0) {
1880 		len = skip_scatter_segment(sc, fl, fr_offset, remaining);
1881 		fr_offset += len;
1882 		remaining -= len;
1883 	}
1884 }
1885 
1886 static inline int
1887 get_segment_len(struct adapter *sc, struct sge_fl *fl, int plen)
1888 {
1889 	int len;
1890 	struct fl_sdesc *sd = &fl->sdesc[fl->cidx];
1891 	struct rx_buf_info *rxb = &sc->sge.rx_buf_info[sd->zidx];
1892 
1893 	if (fl->flags & FL_BUF_PACKING)
1894 		len = rxb->size2 - fl->rx_offset;
1895 	else
1896 		len = rxb->size1;
1897 
1898 	return (min(plen, len));
1899 }
1900 
1901 static int
1902 eth_rx(struct adapter *sc, struct sge_rxq *rxq, const struct iq_desc *d,
1903     u_int plen)
1904 {
1905 	struct mbuf *m0;
1906 	struct ifnet *ifp = rxq->ifp;
1907 	struct sge_fl *fl = &rxq->fl;
1908 	struct vi_info *vi = ifp->if_softc;
1909 	const struct cpl_rx_pkt *cpl;
1910 #if defined(INET) || defined(INET6)
1911 	struct lro_ctrl *lro = &rxq->lro;
1912 #endif
1913 	uint16_t err_vec, tnl_type, tnlhdr_len;
1914 	static const int sw_hashtype[4][2] = {
1915 		{M_HASHTYPE_NONE, M_HASHTYPE_NONE},
1916 		{M_HASHTYPE_RSS_IPV4, M_HASHTYPE_RSS_IPV6},
1917 		{M_HASHTYPE_RSS_TCP_IPV4, M_HASHTYPE_RSS_TCP_IPV6},
1918 		{M_HASHTYPE_RSS_UDP_IPV4, M_HASHTYPE_RSS_UDP_IPV6},
1919 	};
1920 	static const int sw_csum_flags[2][2] = {
1921 		{
1922 			/* IP, inner IP */
1923 			CSUM_ENCAP_VXLAN |
1924 			    CSUM_L3_CALC | CSUM_L3_VALID |
1925 			    CSUM_L4_CALC | CSUM_L4_VALID |
1926 			    CSUM_INNER_L3_CALC | CSUM_INNER_L3_VALID |
1927 			    CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID,
1928 
1929 			/* IP, inner IP6 */
1930 			CSUM_ENCAP_VXLAN |
1931 			    CSUM_L3_CALC | CSUM_L3_VALID |
1932 			    CSUM_L4_CALC | CSUM_L4_VALID |
1933 			    CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID,
1934 		},
1935 		{
1936 			/* IP6, inner IP */
1937 			CSUM_ENCAP_VXLAN |
1938 			    CSUM_L4_CALC | CSUM_L4_VALID |
1939 			    CSUM_INNER_L3_CALC | CSUM_INNER_L3_VALID |
1940 			    CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID,
1941 
1942 			/* IP6, inner IP6 */
1943 			CSUM_ENCAP_VXLAN |
1944 			    CSUM_L4_CALC | CSUM_L4_VALID |
1945 			    CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID,
1946 		},
1947 	};
1948 
1949 	MPASS(plen > sc->params.sge.fl_pktshift);
1950 	if (vi->pfil != NULL && PFIL_HOOKED_IN(vi->pfil) &&
1951 	    __predict_true((fl->flags & FL_BUF_RESUME) == 0)) {
1952 		struct fl_sdesc *sd = &fl->sdesc[fl->cidx];
1953 		caddr_t frame;
1954 		int rc, slen;
1955 
1956 		slen = get_segment_len(sc, fl, plen) -
1957 		    sc->params.sge.fl_pktshift;
1958 		frame = sd->cl + fl->rx_offset + sc->params.sge.fl_pktshift;
1959 		CURVNET_SET_QUIET(ifp->if_vnet);
1960 		rc = pfil_run_hooks(vi->pfil, frame, ifp,
1961 		    slen | PFIL_MEMPTR | PFIL_IN, NULL);
1962 		CURVNET_RESTORE();
1963 		if (rc == PFIL_DROPPED || rc == PFIL_CONSUMED) {
1964 			skip_fl_payload(sc, fl, plen);
1965 			return (0);
1966 		}
1967 		if (rc == PFIL_REALLOCED) {
1968 			skip_fl_payload(sc, fl, plen);
1969 			m0 = pfil_mem2mbuf(frame);
1970 			goto have_mbuf;
1971 		}
1972 	}
1973 
1974 	m0 = get_fl_payload(sc, fl, plen);
1975 	if (__predict_false(m0 == NULL))
1976 		return (ENOMEM);
1977 
1978 	m0->m_pkthdr.len -= sc->params.sge.fl_pktshift;
1979 	m0->m_len -= sc->params.sge.fl_pktshift;
1980 	m0->m_data += sc->params.sge.fl_pktshift;
1981 
1982 have_mbuf:
1983 	m0->m_pkthdr.rcvif = ifp;
1984 	M_HASHTYPE_SET(m0, sw_hashtype[d->rss.hash_type][d->rss.ipv6]);
1985 	m0->m_pkthdr.flowid = be32toh(d->rss.hash_val);
1986 
1987 	cpl = (const void *)(&d->rss + 1);
1988 	if (sc->params.tp.rx_pkt_encap) {
1989 		const uint16_t ev = be16toh(cpl->err_vec);
1990 
1991 		err_vec = G_T6_COMPR_RXERR_VEC(ev);
1992 		tnl_type = G_T6_RX_TNL_TYPE(ev);
1993 		tnlhdr_len = G_T6_RX_TNLHDR_LEN(ev);
1994 	} else {
1995 		err_vec = be16toh(cpl->err_vec);
1996 		tnl_type = 0;
1997 		tnlhdr_len = 0;
1998 	}
1999 	if (cpl->csum_calc && err_vec == 0) {
2000 		int ipv6 = !!(cpl->l2info & htobe32(F_RXF_IP6));
2001 
2002 		/* checksum(s) calculated and found to be correct. */
2003 
2004 		MPASS((cpl->l2info & htobe32(F_RXF_IP)) ^
2005 		    (cpl->l2info & htobe32(F_RXF_IP6)));
2006 		m0->m_pkthdr.csum_data = be16toh(cpl->csum);
2007 		if (tnl_type == 0) {
2008 	    		if (!ipv6 && ifp->if_capenable & IFCAP_RXCSUM) {
2009 				m0->m_pkthdr.csum_flags = CSUM_L3_CALC |
2010 				    CSUM_L3_VALID | CSUM_L4_CALC |
2011 				    CSUM_L4_VALID;
2012 			} else if (ipv6 && ifp->if_capenable & IFCAP_RXCSUM_IPV6) {
2013 				m0->m_pkthdr.csum_flags = CSUM_L4_CALC |
2014 				    CSUM_L4_VALID;
2015 			}
2016 			rxq->rxcsum++;
2017 		} else {
2018 			MPASS(tnl_type == RX_PKT_TNL_TYPE_VXLAN);
2019 
2020 			M_HASHTYPE_SETINNER(m0);
2021 			if (__predict_false(cpl->ip_frag)) {
2022 				/*
2023 				 * csum_data is for the inner frame (which is an
2024 				 * IP fragment) and is not 0xffff.  There is no
2025 				 * way to pass the inner csum_data to the stack.
2026 				 * We don't want the stack to use the inner
2027 				 * csum_data to validate the outer frame or it
2028 				 * will get rejected.  So we fix csum_data here
2029 				 * and let sw do the checksum of inner IP
2030 				 * fragments.
2031 				 *
2032 				 * XXX: Need 32b for csum_data2 in an rx mbuf.
2033 				 * Maybe stuff it into rcv_tstmp?
2034 				 */
2035 				m0->m_pkthdr.csum_data = 0xffff;
2036 				if (ipv6) {
2037 					m0->m_pkthdr.csum_flags = CSUM_L4_CALC |
2038 					    CSUM_L4_VALID;
2039 				} else {
2040 					m0->m_pkthdr.csum_flags = CSUM_L3_CALC |
2041 					    CSUM_L3_VALID | CSUM_L4_CALC |
2042 					    CSUM_L4_VALID;
2043 				}
2044 			} else {
2045 				int outer_ipv6;
2046 
2047 				MPASS(m0->m_pkthdr.csum_data == 0xffff);
2048 
2049 				outer_ipv6 = tnlhdr_len >=
2050 				    sizeof(struct ether_header) +
2051 				    sizeof(struct ip6_hdr);
2052 				m0->m_pkthdr.csum_flags =
2053 				    sw_csum_flags[outer_ipv6][ipv6];
2054 			}
2055 			rxq->vxlan_rxcsum++;
2056 		}
2057 	}
2058 
2059 	if (cpl->vlan_ex) {
2060 		m0->m_pkthdr.ether_vtag = be16toh(cpl->vlan);
2061 		m0->m_flags |= M_VLANTAG;
2062 		rxq->vlan_extraction++;
2063 	}
2064 
2065 	if (rxq->iq.flags & IQ_RX_TIMESTAMP) {
2066 		/*
2067 		 * Fill up rcv_tstmp but do not set M_TSTMP.
2068 		 * rcv_tstmp is not in the format that the
2069 		 * kernel expects and we don't want to mislead
2070 		 * it.  For now this is only for custom code
2071 		 * that knows how to interpret cxgbe's stamp.
2072 		 */
2073 		m0->m_pkthdr.rcv_tstmp =
2074 		    last_flit_to_ns(sc, d->rsp.u.last_flit);
2075 #ifdef notyet
2076 		m0->m_flags |= M_TSTMP;
2077 #endif
2078 	}
2079 
2080 #ifdef NUMA
2081 	m0->m_pkthdr.numa_domain = ifp->if_numa_domain;
2082 #endif
2083 #if defined(INET) || defined(INET6)
2084 	if (rxq->iq.flags & IQ_LRO_ENABLED && tnl_type == 0 &&
2085 	    (M_HASHTYPE_GET(m0) == M_HASHTYPE_RSS_TCP_IPV4 ||
2086 	    M_HASHTYPE_GET(m0) == M_HASHTYPE_RSS_TCP_IPV6)) {
2087 		if (sort_before_lro(lro)) {
2088 			tcp_lro_queue_mbuf(lro, m0);
2089 			return (0); /* queued for sort, then LRO */
2090 		}
2091 		if (tcp_lro_rx(lro, m0, 0) == 0)
2092 			return (0); /* queued for LRO */
2093 	}
2094 #endif
2095 	ifp->if_input(ifp, m0);
2096 
2097 	return (0);
2098 }
2099 
2100 /*
2101  * Must drain the wrq or make sure that someone else will.
2102  */
2103 static void
2104 wrq_tx_drain(void *arg, int n)
2105 {
2106 	struct sge_wrq *wrq = arg;
2107 	struct sge_eq *eq = &wrq->eq;
2108 
2109 	EQ_LOCK(eq);
2110 	if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list))
2111 		drain_wrq_wr_list(wrq->adapter, wrq);
2112 	EQ_UNLOCK(eq);
2113 }
2114 
2115 static void
2116 drain_wrq_wr_list(struct adapter *sc, struct sge_wrq *wrq)
2117 {
2118 	struct sge_eq *eq = &wrq->eq;
2119 	u_int available, dbdiff;	/* # of hardware descriptors */
2120 	u_int n;
2121 	struct wrqe *wr;
2122 	struct fw_eth_tx_pkt_wr *dst;	/* any fw WR struct will do */
2123 
2124 	EQ_LOCK_ASSERT_OWNED(eq);
2125 	MPASS(TAILQ_EMPTY(&wrq->incomplete_wrs));
2126 	wr = STAILQ_FIRST(&wrq->wr_list);
2127 	MPASS(wr != NULL);	/* Must be called with something useful to do */
2128 	MPASS(eq->pidx == eq->dbidx);
2129 	dbdiff = 0;
2130 
2131 	do {
2132 		eq->cidx = read_hw_cidx(eq);
2133 		if (eq->pidx == eq->cidx)
2134 			available = eq->sidx - 1;
2135 		else
2136 			available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
2137 
2138 		MPASS(wr->wrq == wrq);
2139 		n = howmany(wr->wr_len, EQ_ESIZE);
2140 		if (available < n)
2141 			break;
2142 
2143 		dst = (void *)&eq->desc[eq->pidx];
2144 		if (__predict_true(eq->sidx - eq->pidx > n)) {
2145 			/* Won't wrap, won't end exactly at the status page. */
2146 			bcopy(&wr->wr[0], dst, wr->wr_len);
2147 			eq->pidx += n;
2148 		} else {
2149 			int first_portion = (eq->sidx - eq->pidx) * EQ_ESIZE;
2150 
2151 			bcopy(&wr->wr[0], dst, first_portion);
2152 			if (wr->wr_len > first_portion) {
2153 				bcopy(&wr->wr[first_portion], &eq->desc[0],
2154 				    wr->wr_len - first_portion);
2155 			}
2156 			eq->pidx = n - (eq->sidx - eq->pidx);
2157 		}
2158 		wrq->tx_wrs_copied++;
2159 
2160 		if (available < eq->sidx / 4 &&
2161 		    atomic_cmpset_int(&eq->equiq, 0, 1)) {
2162 				/*
2163 				 * XXX: This is not 100% reliable with some
2164 				 * types of WRs.  But this is a very unusual
2165 				 * situation for an ofld/ctrl queue anyway.
2166 				 */
2167 			dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ |
2168 			    F_FW_WR_EQUEQ);
2169 		}
2170 
2171 		dbdiff += n;
2172 		if (dbdiff >= 16) {
2173 			ring_eq_db(sc, eq, dbdiff);
2174 			dbdiff = 0;
2175 		}
2176 
2177 		STAILQ_REMOVE_HEAD(&wrq->wr_list, link);
2178 		free_wrqe(wr);
2179 		MPASS(wrq->nwr_pending > 0);
2180 		wrq->nwr_pending--;
2181 		MPASS(wrq->ndesc_needed >= n);
2182 		wrq->ndesc_needed -= n;
2183 	} while ((wr = STAILQ_FIRST(&wrq->wr_list)) != NULL);
2184 
2185 	if (dbdiff)
2186 		ring_eq_db(sc, eq, dbdiff);
2187 }
2188 
2189 /*
2190  * Doesn't fail.  Holds on to work requests it can't send right away.
2191  */
2192 void
2193 t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, struct wrqe *wr)
2194 {
2195 #ifdef INVARIANTS
2196 	struct sge_eq *eq = &wrq->eq;
2197 #endif
2198 
2199 	EQ_LOCK_ASSERT_OWNED(eq);
2200 	MPASS(wr != NULL);
2201 	MPASS(wr->wr_len > 0 && wr->wr_len <= SGE_MAX_WR_LEN);
2202 	MPASS((wr->wr_len & 0x7) == 0);
2203 
2204 	STAILQ_INSERT_TAIL(&wrq->wr_list, wr, link);
2205 	wrq->nwr_pending++;
2206 	wrq->ndesc_needed += howmany(wr->wr_len, EQ_ESIZE);
2207 
2208 	if (!TAILQ_EMPTY(&wrq->incomplete_wrs))
2209 		return;	/* commit_wrq_wr will drain wr_list as well. */
2210 
2211 	drain_wrq_wr_list(sc, wrq);
2212 
2213 	/* Doorbell must have caught up to the pidx. */
2214 	MPASS(eq->pidx == eq->dbidx);
2215 }
2216 
2217 void
2218 t4_update_fl_bufsize(struct ifnet *ifp)
2219 {
2220 	struct vi_info *vi = ifp->if_softc;
2221 	struct adapter *sc = vi->adapter;
2222 	struct sge_rxq *rxq;
2223 #ifdef TCP_OFFLOAD
2224 	struct sge_ofld_rxq *ofld_rxq;
2225 #endif
2226 	struct sge_fl *fl;
2227 	int i, maxp;
2228 
2229 	maxp = max_rx_payload(sc, ifp, false);
2230 	for_each_rxq(vi, i, rxq) {
2231 		fl = &rxq->fl;
2232 
2233 		FL_LOCK(fl);
2234 		fl->zidx = find_refill_source(sc, maxp,
2235 		    fl->flags & FL_BUF_PACKING);
2236 		FL_UNLOCK(fl);
2237 	}
2238 #ifdef TCP_OFFLOAD
2239 	maxp = max_rx_payload(sc, ifp, true);
2240 	for_each_ofld_rxq(vi, i, ofld_rxq) {
2241 		fl = &ofld_rxq->fl;
2242 
2243 		FL_LOCK(fl);
2244 		fl->zidx = find_refill_source(sc, maxp,
2245 		    fl->flags & FL_BUF_PACKING);
2246 		FL_UNLOCK(fl);
2247 	}
2248 #endif
2249 }
2250 
2251 static inline int
2252 mbuf_nsegs(struct mbuf *m)
2253 {
2254 
2255 	M_ASSERTPKTHDR(m);
2256 	KASSERT(m->m_pkthdr.inner_l5hlen > 0,
2257 	    ("%s: mbuf %p missing information on # of segments.", __func__, m));
2258 
2259 	return (m->m_pkthdr.inner_l5hlen);
2260 }
2261 
2262 static inline void
2263 set_mbuf_nsegs(struct mbuf *m, uint8_t nsegs)
2264 {
2265 
2266 	M_ASSERTPKTHDR(m);
2267 	m->m_pkthdr.inner_l5hlen = nsegs;
2268 }
2269 
2270 static inline int
2271 mbuf_cflags(struct mbuf *m)
2272 {
2273 
2274 	M_ASSERTPKTHDR(m);
2275 	return (m->m_pkthdr.PH_loc.eight[4]);
2276 }
2277 
2278 static inline void
2279 set_mbuf_cflags(struct mbuf *m, uint8_t flags)
2280 {
2281 
2282 	M_ASSERTPKTHDR(m);
2283 	m->m_pkthdr.PH_loc.eight[4] = flags;
2284 }
2285 
2286 static inline int
2287 mbuf_len16(struct mbuf *m)
2288 {
2289 	int n;
2290 
2291 	M_ASSERTPKTHDR(m);
2292 	n = m->m_pkthdr.PH_loc.eight[0];
2293 	if (!(mbuf_cflags(m) & MC_TLS))
2294 		MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16);
2295 
2296 	return (n);
2297 }
2298 
2299 static inline void
2300 set_mbuf_len16(struct mbuf *m, uint8_t len16)
2301 {
2302 
2303 	M_ASSERTPKTHDR(m);
2304 	if (!(mbuf_cflags(m) & MC_TLS))
2305 		MPASS(len16 > 0 && len16 <= SGE_MAX_WR_LEN / 16);
2306 	m->m_pkthdr.PH_loc.eight[0] = len16;
2307 }
2308 
2309 #ifdef RATELIMIT
2310 static inline int
2311 mbuf_eo_nsegs(struct mbuf *m)
2312 {
2313 
2314 	M_ASSERTPKTHDR(m);
2315 	return (m->m_pkthdr.PH_loc.eight[1]);
2316 }
2317 
2318 #if defined(INET) || defined(INET6)
2319 static inline void
2320 set_mbuf_eo_nsegs(struct mbuf *m, uint8_t nsegs)
2321 {
2322 
2323 	M_ASSERTPKTHDR(m);
2324 	m->m_pkthdr.PH_loc.eight[1] = nsegs;
2325 }
2326 #endif
2327 
2328 static inline int
2329 mbuf_eo_len16(struct mbuf *m)
2330 {
2331 	int n;
2332 
2333 	M_ASSERTPKTHDR(m);
2334 	n = m->m_pkthdr.PH_loc.eight[2];
2335 	MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16);
2336 
2337 	return (n);
2338 }
2339 
2340 #if defined(INET) || defined(INET6)
2341 static inline void
2342 set_mbuf_eo_len16(struct mbuf *m, uint8_t len16)
2343 {
2344 
2345 	M_ASSERTPKTHDR(m);
2346 	m->m_pkthdr.PH_loc.eight[2] = len16;
2347 }
2348 #endif
2349 
2350 static inline int
2351 mbuf_eo_tsclk_tsoff(struct mbuf *m)
2352 {
2353 
2354 	M_ASSERTPKTHDR(m);
2355 	return (m->m_pkthdr.PH_loc.eight[3]);
2356 }
2357 
2358 #if defined(INET) || defined(INET6)
2359 static inline void
2360 set_mbuf_eo_tsclk_tsoff(struct mbuf *m, uint8_t tsclk_tsoff)
2361 {
2362 
2363 	M_ASSERTPKTHDR(m);
2364 	m->m_pkthdr.PH_loc.eight[3] = tsclk_tsoff;
2365 }
2366 #endif
2367 
2368 static inline int
2369 needs_eo(struct m_snd_tag *mst)
2370 {
2371 
2372 	return (mst != NULL && mst->type == IF_SND_TAG_TYPE_RATE_LIMIT);
2373 }
2374 #endif
2375 
2376 /*
2377  * Try to allocate an mbuf to contain a raw work request.  To make it
2378  * easy to construct the work request, don't allocate a chain but a
2379  * single mbuf.
2380  */
2381 struct mbuf *
2382 alloc_wr_mbuf(int len, int how)
2383 {
2384 	struct mbuf *m;
2385 
2386 	if (len <= MHLEN)
2387 		m = m_gethdr(how, MT_DATA);
2388 	else if (len <= MCLBYTES)
2389 		m = m_getcl(how, MT_DATA, M_PKTHDR);
2390 	else
2391 		m = NULL;
2392 	if (m == NULL)
2393 		return (NULL);
2394 	m->m_pkthdr.len = len;
2395 	m->m_len = len;
2396 	set_mbuf_cflags(m, MC_RAW_WR);
2397 	set_mbuf_len16(m, howmany(len, 16));
2398 	return (m);
2399 }
2400 
2401 static inline bool
2402 needs_hwcsum(struct mbuf *m)
2403 {
2404 	const uint32_t csum_flags = CSUM_IP | CSUM_IP_UDP | CSUM_IP_TCP |
2405 	    CSUM_IP_TSO | CSUM_INNER_IP | CSUM_INNER_IP_UDP |
2406 	    CSUM_INNER_IP_TCP | CSUM_INNER_IP_TSO | CSUM_IP6_UDP |
2407 	    CSUM_IP6_TCP | CSUM_IP6_TSO | CSUM_INNER_IP6_UDP |
2408 	    CSUM_INNER_IP6_TCP | CSUM_INNER_IP6_TSO;
2409 
2410 	M_ASSERTPKTHDR(m);
2411 
2412 	return (m->m_pkthdr.csum_flags & csum_flags);
2413 }
2414 
2415 static inline bool
2416 needs_tso(struct mbuf *m)
2417 {
2418 	const uint32_t csum_flags = CSUM_IP_TSO | CSUM_IP6_TSO |
2419 	    CSUM_INNER_IP_TSO | CSUM_INNER_IP6_TSO;
2420 
2421 	M_ASSERTPKTHDR(m);
2422 
2423 	return (m->m_pkthdr.csum_flags & csum_flags);
2424 }
2425 
2426 static inline bool
2427 needs_vxlan_csum(struct mbuf *m)
2428 {
2429 
2430 	M_ASSERTPKTHDR(m);
2431 
2432 	return (m->m_pkthdr.csum_flags & CSUM_ENCAP_VXLAN);
2433 }
2434 
2435 static inline bool
2436 needs_vxlan_tso(struct mbuf *m)
2437 {
2438 	const uint32_t csum_flags = CSUM_ENCAP_VXLAN | CSUM_INNER_IP_TSO |
2439 	    CSUM_INNER_IP6_TSO;
2440 
2441 	M_ASSERTPKTHDR(m);
2442 
2443 	return ((m->m_pkthdr.csum_flags & csum_flags) != 0 &&
2444 	    (m->m_pkthdr.csum_flags & csum_flags) != CSUM_ENCAP_VXLAN);
2445 }
2446 
2447 #if defined(INET) || defined(INET6)
2448 static inline bool
2449 needs_inner_tcp_csum(struct mbuf *m)
2450 {
2451 	const uint32_t csum_flags = CSUM_INNER_IP_TSO | CSUM_INNER_IP6_TSO;
2452 
2453 	M_ASSERTPKTHDR(m);
2454 
2455 	return (m->m_pkthdr.csum_flags & csum_flags);
2456 }
2457 #endif
2458 
2459 static inline bool
2460 needs_l3_csum(struct mbuf *m)
2461 {
2462 	const uint32_t csum_flags = CSUM_IP | CSUM_IP_TSO | CSUM_INNER_IP |
2463 	    CSUM_INNER_IP_TSO;
2464 
2465 	M_ASSERTPKTHDR(m);
2466 
2467 	return (m->m_pkthdr.csum_flags & csum_flags);
2468 }
2469 
2470 static inline bool
2471 needs_outer_tcp_csum(struct mbuf *m)
2472 {
2473 	const uint32_t csum_flags = CSUM_IP_TCP | CSUM_IP_TSO | CSUM_IP6_TCP |
2474 	    CSUM_IP6_TSO;
2475 
2476 	M_ASSERTPKTHDR(m);
2477 
2478 	return (m->m_pkthdr.csum_flags & csum_flags);
2479 }
2480 
2481 #ifdef RATELIMIT
2482 static inline bool
2483 needs_outer_l4_csum(struct mbuf *m)
2484 {
2485 	const uint32_t csum_flags = CSUM_IP_UDP | CSUM_IP_TCP | CSUM_IP_TSO |
2486 	    CSUM_IP6_UDP | CSUM_IP6_TCP | CSUM_IP6_TSO;
2487 
2488 	M_ASSERTPKTHDR(m);
2489 
2490 	return (m->m_pkthdr.csum_flags & csum_flags);
2491 }
2492 
2493 static inline bool
2494 needs_outer_udp_csum(struct mbuf *m)
2495 {
2496 	const uint32_t csum_flags = CSUM_IP_UDP | CSUM_IP6_UDP;
2497 
2498 	M_ASSERTPKTHDR(m);
2499 
2500 	return (m->m_pkthdr.csum_flags & csum_flags);
2501 }
2502 #endif
2503 
2504 static inline bool
2505 needs_vlan_insertion(struct mbuf *m)
2506 {
2507 
2508 	M_ASSERTPKTHDR(m);
2509 
2510 	return (m->m_flags & M_VLANTAG);
2511 }
2512 
2513 static void *
2514 m_advance(struct mbuf **pm, int *poffset, int len)
2515 {
2516 	struct mbuf *m = *pm;
2517 	int offset = *poffset;
2518 	uintptr_t p = 0;
2519 
2520 	MPASS(len > 0);
2521 
2522 	for (;;) {
2523 		if (offset + len < m->m_len) {
2524 			offset += len;
2525 			p = mtod(m, uintptr_t) + offset;
2526 			break;
2527 		}
2528 		len -= m->m_len - offset;
2529 		m = m->m_next;
2530 		offset = 0;
2531 		MPASS(m != NULL);
2532 	}
2533 	*poffset = offset;
2534 	*pm = m;
2535 	return ((void *)p);
2536 }
2537 
2538 static inline int
2539 count_mbuf_ext_pgs(struct mbuf *m, int skip, vm_paddr_t *nextaddr)
2540 {
2541 	vm_paddr_t paddr;
2542 	int i, len, off, pglen, pgoff, seglen, segoff;
2543 	int nsegs = 0;
2544 
2545 	M_ASSERTEXTPG(m);
2546 	off = mtod(m, vm_offset_t);
2547 	len = m->m_len;
2548 	off += skip;
2549 	len -= skip;
2550 
2551 	if (m->m_epg_hdrlen != 0) {
2552 		if (off >= m->m_epg_hdrlen) {
2553 			off -= m->m_epg_hdrlen;
2554 		} else {
2555 			seglen = m->m_epg_hdrlen - off;
2556 			segoff = off;
2557 			seglen = min(seglen, len);
2558 			off = 0;
2559 			len -= seglen;
2560 			paddr = pmap_kextract(
2561 			    (vm_offset_t)&m->m_epg_hdr[segoff]);
2562 			if (*nextaddr != paddr)
2563 				nsegs++;
2564 			*nextaddr = paddr + seglen;
2565 		}
2566 	}
2567 	pgoff = m->m_epg_1st_off;
2568 	for (i = 0; i < m->m_epg_npgs && len > 0; i++) {
2569 		pglen = m_epg_pagelen(m, i, pgoff);
2570 		if (off >= pglen) {
2571 			off -= pglen;
2572 			pgoff = 0;
2573 			continue;
2574 		}
2575 		seglen = pglen - off;
2576 		segoff = pgoff + off;
2577 		off = 0;
2578 		seglen = min(seglen, len);
2579 		len -= seglen;
2580 		paddr = m->m_epg_pa[i] + segoff;
2581 		if (*nextaddr != paddr)
2582 			nsegs++;
2583 		*nextaddr = paddr + seglen;
2584 		pgoff = 0;
2585 	};
2586 	if (len != 0) {
2587 		seglen = min(len, m->m_epg_trllen - off);
2588 		len -= seglen;
2589 		paddr = pmap_kextract((vm_offset_t)&m->m_epg_trail[off]);
2590 		if (*nextaddr != paddr)
2591 			nsegs++;
2592 		*nextaddr = paddr + seglen;
2593 	}
2594 
2595 	return (nsegs);
2596 }
2597 
2598 
2599 /*
2600  * Can deal with empty mbufs in the chain that have m_len = 0, but the chain
2601  * must have at least one mbuf that's not empty.  It is possible for this
2602  * routine to return 0 if skip accounts for all the contents of the mbuf chain.
2603  */
2604 static inline int
2605 count_mbuf_nsegs(struct mbuf *m, int skip, uint8_t *cflags)
2606 {
2607 	vm_paddr_t nextaddr, paddr;
2608 	vm_offset_t va;
2609 	int len, nsegs;
2610 
2611 	M_ASSERTPKTHDR(m);
2612 	MPASS(m->m_pkthdr.len > 0);
2613 	MPASS(m->m_pkthdr.len >= skip);
2614 
2615 	nsegs = 0;
2616 	nextaddr = 0;
2617 	for (; m; m = m->m_next) {
2618 		len = m->m_len;
2619 		if (__predict_false(len == 0))
2620 			continue;
2621 		if (skip >= len) {
2622 			skip -= len;
2623 			continue;
2624 		}
2625 		if ((m->m_flags & M_EXTPG) != 0) {
2626 			*cflags |= MC_NOMAP;
2627 			nsegs += count_mbuf_ext_pgs(m, skip, &nextaddr);
2628 			skip = 0;
2629 			continue;
2630 		}
2631 		va = mtod(m, vm_offset_t) + skip;
2632 		len -= skip;
2633 		skip = 0;
2634 		paddr = pmap_kextract(va);
2635 		nsegs += sglist_count((void *)(uintptr_t)va, len);
2636 		if (paddr == nextaddr)
2637 			nsegs--;
2638 		nextaddr = pmap_kextract(va + len - 1) + 1;
2639 	}
2640 
2641 	return (nsegs);
2642 }
2643 
2644 /*
2645  * The maximum number of segments that can fit in a WR.
2646  */
2647 static int
2648 max_nsegs_allowed(struct mbuf *m, bool vm_wr)
2649 {
2650 
2651 	if (vm_wr) {
2652 		if (needs_tso(m))
2653 			return (TX_SGL_SEGS_VM_TSO);
2654 		return (TX_SGL_SEGS_VM);
2655 	}
2656 
2657 	if (needs_tso(m)) {
2658 		if (needs_vxlan_tso(m))
2659 			return (TX_SGL_SEGS_VXLAN_TSO);
2660 		else
2661 			return (TX_SGL_SEGS_TSO);
2662 	}
2663 
2664 	return (TX_SGL_SEGS);
2665 }
2666 
2667 static struct timeval txerr_ratecheck = {0};
2668 static const struct timeval txerr_interval = {3, 0};
2669 
2670 /*
2671  * Analyze the mbuf to determine its tx needs.  The mbuf passed in may change:
2672  * a) caller can assume it's been freed if this function returns with an error.
2673  * b) it may get defragged up if the gather list is too long for the hardware.
2674  */
2675 int
2676 parse_pkt(struct mbuf **mp, bool vm_wr)
2677 {
2678 	struct mbuf *m0 = *mp, *m;
2679 	int rc, nsegs, defragged = 0, offset;
2680 	struct ether_header *eh;
2681 	void *l3hdr;
2682 #if defined(INET) || defined(INET6)
2683 	struct tcphdr *tcp;
2684 #endif
2685 #if defined(KERN_TLS) || defined(RATELIMIT)
2686 	struct m_snd_tag *mst;
2687 #endif
2688 	uint16_t eh_type;
2689 	uint8_t cflags;
2690 
2691 	cflags = 0;
2692 	M_ASSERTPKTHDR(m0);
2693 	if (__predict_false(m0->m_pkthdr.len < ETHER_HDR_LEN)) {
2694 		rc = EINVAL;
2695 fail:
2696 		m_freem(m0);
2697 		*mp = NULL;
2698 		return (rc);
2699 	}
2700 restart:
2701 	/*
2702 	 * First count the number of gather list segments in the payload.
2703 	 * Defrag the mbuf if nsegs exceeds the hardware limit.
2704 	 */
2705 	M_ASSERTPKTHDR(m0);
2706 	MPASS(m0->m_pkthdr.len > 0);
2707 	nsegs = count_mbuf_nsegs(m0, 0, &cflags);
2708 #if defined(KERN_TLS) || defined(RATELIMIT)
2709 	if (m0->m_pkthdr.csum_flags & CSUM_SND_TAG)
2710 		mst = m0->m_pkthdr.snd_tag;
2711 	else
2712 		mst = NULL;
2713 #endif
2714 #ifdef KERN_TLS
2715 	if (mst != NULL && mst->type == IF_SND_TAG_TYPE_TLS) {
2716 		int len16;
2717 
2718 		cflags |= MC_TLS;
2719 		set_mbuf_cflags(m0, cflags);
2720 		rc = t6_ktls_parse_pkt(m0, &nsegs, &len16);
2721 		if (rc != 0)
2722 			goto fail;
2723 		set_mbuf_nsegs(m0, nsegs);
2724 		set_mbuf_len16(m0, len16);
2725 		return (0);
2726 	}
2727 #endif
2728 	if (nsegs > max_nsegs_allowed(m0, vm_wr)) {
2729 		if (defragged++ > 0) {
2730 			rc = EFBIG;
2731 			goto fail;
2732 		}
2733 		counter_u64_add(defrags, 1);
2734 		if ((m = m_defrag(m0, M_NOWAIT)) == NULL) {
2735 			rc = ENOMEM;
2736 			goto fail;
2737 		}
2738 		*mp = m0 = m;	/* update caller's copy after defrag */
2739 		goto restart;
2740 	}
2741 
2742 	if (__predict_false(nsegs > 2 && m0->m_pkthdr.len <= MHLEN &&
2743 	    !(cflags & MC_NOMAP))) {
2744 		counter_u64_add(pullups, 1);
2745 		m0 = m_pullup(m0, m0->m_pkthdr.len);
2746 		if (m0 == NULL) {
2747 			/* Should have left well enough alone. */
2748 			rc = EFBIG;
2749 			goto fail;
2750 		}
2751 		*mp = m0;	/* update caller's copy after pullup */
2752 		goto restart;
2753 	}
2754 	set_mbuf_nsegs(m0, nsegs);
2755 	set_mbuf_cflags(m0, cflags);
2756 	calculate_mbuf_len16(m0, vm_wr);
2757 
2758 #ifdef RATELIMIT
2759 	/*
2760 	 * Ethofld is limited to TCP and UDP for now, and only when L4 hw
2761 	 * checksumming is enabled.  needs_outer_l4_csum happens to check for
2762 	 * all the right things.
2763 	 */
2764 	if (__predict_false(needs_eo(mst) && !needs_outer_l4_csum(m0))) {
2765 		m_snd_tag_rele(m0->m_pkthdr.snd_tag);
2766 		m0->m_pkthdr.snd_tag = NULL;
2767 		m0->m_pkthdr.csum_flags &= ~CSUM_SND_TAG;
2768 		mst = NULL;
2769 	}
2770 #endif
2771 
2772 	if (!needs_hwcsum(m0)
2773 #ifdef RATELIMIT
2774    		 && !needs_eo(mst)
2775 #endif
2776 	)
2777 		return (0);
2778 
2779 	m = m0;
2780 	eh = mtod(m, struct ether_header *);
2781 	eh_type = ntohs(eh->ether_type);
2782 	if (eh_type == ETHERTYPE_VLAN) {
2783 		struct ether_vlan_header *evh = (void *)eh;
2784 
2785 		eh_type = ntohs(evh->evl_proto);
2786 		m0->m_pkthdr.l2hlen = sizeof(*evh);
2787 	} else
2788 		m0->m_pkthdr.l2hlen = sizeof(*eh);
2789 
2790 	offset = 0;
2791 	l3hdr = m_advance(&m, &offset, m0->m_pkthdr.l2hlen);
2792 
2793 	switch (eh_type) {
2794 #ifdef INET6
2795 	case ETHERTYPE_IPV6:
2796 		m0->m_pkthdr.l3hlen = sizeof(struct ip6_hdr);
2797 		break;
2798 #endif
2799 #ifdef INET
2800 	case ETHERTYPE_IP:
2801 	{
2802 		struct ip *ip = l3hdr;
2803 
2804 		if (needs_vxlan_csum(m0)) {
2805 			/* Driver will do the outer IP hdr checksum. */
2806 			ip->ip_sum = 0;
2807 			if (needs_vxlan_tso(m0)) {
2808 				const uint16_t ipl = ip->ip_len;
2809 
2810 				ip->ip_len = 0;
2811 				ip->ip_sum = ~in_cksum_hdr(ip);
2812 				ip->ip_len = ipl;
2813 			} else
2814 				ip->ip_sum = in_cksum_hdr(ip);
2815 		}
2816 		m0->m_pkthdr.l3hlen = ip->ip_hl << 2;
2817 		break;
2818 	}
2819 #endif
2820 	default:
2821 		if (ratecheck(&txerr_ratecheck, &txerr_interval)) {
2822 			log(LOG_ERR, "%s: ethertype 0x%04x unknown.  "
2823 			    "if_cxgbe must be compiled with the same "
2824 			    "INET/INET6 options as the kernel.\n", __func__,
2825 			    eh_type);
2826 		}
2827 		rc = EINVAL;
2828 		goto fail;
2829 	}
2830 
2831 	if (needs_vxlan_csum(m0)) {
2832 		m0->m_pkthdr.l4hlen = sizeof(struct udphdr);
2833 		m0->m_pkthdr.l5hlen = sizeof(struct vxlan_header);
2834 
2835 		/* Inner headers. */
2836 		eh = m_advance(&m, &offset, m0->m_pkthdr.l3hlen +
2837 		    sizeof(struct udphdr) + sizeof(struct vxlan_header));
2838 		eh_type = ntohs(eh->ether_type);
2839 		if (eh_type == ETHERTYPE_VLAN) {
2840 			struct ether_vlan_header *evh = (void *)eh;
2841 
2842 			eh_type = ntohs(evh->evl_proto);
2843 			m0->m_pkthdr.inner_l2hlen = sizeof(*evh);
2844 		} else
2845 			m0->m_pkthdr.inner_l2hlen = sizeof(*eh);
2846 		l3hdr = m_advance(&m, &offset, m0->m_pkthdr.inner_l2hlen);
2847 
2848 		switch (eh_type) {
2849 #ifdef INET6
2850 		case ETHERTYPE_IPV6:
2851 			m0->m_pkthdr.inner_l3hlen = sizeof(struct ip6_hdr);
2852 			break;
2853 #endif
2854 #ifdef INET
2855 		case ETHERTYPE_IP:
2856 		{
2857 			struct ip *ip = l3hdr;
2858 
2859 			m0->m_pkthdr.inner_l3hlen = ip->ip_hl << 2;
2860 			break;
2861 		}
2862 #endif
2863 		default:
2864 			if (ratecheck(&txerr_ratecheck, &txerr_interval)) {
2865 				log(LOG_ERR, "%s: VXLAN hw offload requested"
2866 				    "with unknown ethertype 0x%04x.  if_cxgbe "
2867 				    "must be compiled with the same INET/INET6 "
2868 				    "options as the kernel.\n", __func__,
2869 				    eh_type);
2870 			}
2871 			rc = EINVAL;
2872 			goto fail;
2873 		}
2874 #if defined(INET) || defined(INET6)
2875 		if (needs_inner_tcp_csum(m0)) {
2876 			tcp = m_advance(&m, &offset, m0->m_pkthdr.inner_l3hlen);
2877 			m0->m_pkthdr.inner_l4hlen = tcp->th_off * 4;
2878 		}
2879 #endif
2880 		MPASS((m0->m_pkthdr.csum_flags & CSUM_SND_TAG) == 0);
2881 		m0->m_pkthdr.csum_flags &= CSUM_INNER_IP6_UDP |
2882 		    CSUM_INNER_IP6_TCP | CSUM_INNER_IP6_TSO | CSUM_INNER_IP |
2883 		    CSUM_INNER_IP_UDP | CSUM_INNER_IP_TCP | CSUM_INNER_IP_TSO |
2884 		    CSUM_ENCAP_VXLAN;
2885 	}
2886 
2887 #if defined(INET) || defined(INET6)
2888 	if (needs_outer_tcp_csum(m0)) {
2889 		tcp = m_advance(&m, &offset, m0->m_pkthdr.l3hlen);
2890 		m0->m_pkthdr.l4hlen = tcp->th_off * 4;
2891 #ifdef RATELIMIT
2892 		if (tsclk >= 0 && *(uint32_t *)(tcp + 1) == ntohl(0x0101080a)) {
2893 			set_mbuf_eo_tsclk_tsoff(m0,
2894 			    V_FW_ETH_TX_EO_WR_TSCLK(tsclk) |
2895 			    V_FW_ETH_TX_EO_WR_TSOFF(sizeof(*tcp) / 2 + 1));
2896 		} else
2897 			set_mbuf_eo_tsclk_tsoff(m0, 0);
2898 	} else if (needs_outer_udp_csum(m0)) {
2899 		m0->m_pkthdr.l4hlen = sizeof(struct udphdr);
2900 #endif
2901 	}
2902 #ifdef RATELIMIT
2903 	if (needs_eo(mst)) {
2904 		u_int immhdrs;
2905 
2906 		/* EO WRs have the headers in the WR and not the GL. */
2907 		immhdrs = m0->m_pkthdr.l2hlen + m0->m_pkthdr.l3hlen +
2908 		    m0->m_pkthdr.l4hlen;
2909 		cflags = 0;
2910 		nsegs = count_mbuf_nsegs(m0, immhdrs, &cflags);
2911 		MPASS(cflags == mbuf_cflags(m0));
2912 		set_mbuf_eo_nsegs(m0, nsegs);
2913 		set_mbuf_eo_len16(m0,
2914 		    txpkt_eo_len16(nsegs, immhdrs, needs_tso(m0)));
2915 	}
2916 #endif
2917 #endif
2918 	MPASS(m0 == *mp);
2919 	return (0);
2920 }
2921 
2922 void *
2923 start_wrq_wr(struct sge_wrq *wrq, int len16, struct wrq_cookie *cookie)
2924 {
2925 	struct sge_eq *eq = &wrq->eq;
2926 	struct adapter *sc = wrq->adapter;
2927 	int ndesc, available;
2928 	struct wrqe *wr;
2929 	void *w;
2930 
2931 	MPASS(len16 > 0);
2932 	ndesc = tx_len16_to_desc(len16);
2933 	MPASS(ndesc > 0 && ndesc <= SGE_MAX_WR_NDESC);
2934 
2935 	EQ_LOCK(eq);
2936 
2937 	if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list))
2938 		drain_wrq_wr_list(sc, wrq);
2939 
2940 	if (!STAILQ_EMPTY(&wrq->wr_list)) {
2941 slowpath:
2942 		EQ_UNLOCK(eq);
2943 		wr = alloc_wrqe(len16 * 16, wrq);
2944 		if (__predict_false(wr == NULL))
2945 			return (NULL);
2946 		cookie->pidx = -1;
2947 		cookie->ndesc = ndesc;
2948 		return (&wr->wr);
2949 	}
2950 
2951 	eq->cidx = read_hw_cidx(eq);
2952 	if (eq->pidx == eq->cidx)
2953 		available = eq->sidx - 1;
2954 	else
2955 		available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
2956 	if (available < ndesc)
2957 		goto slowpath;
2958 
2959 	cookie->pidx = eq->pidx;
2960 	cookie->ndesc = ndesc;
2961 	TAILQ_INSERT_TAIL(&wrq->incomplete_wrs, cookie, link);
2962 
2963 	w = &eq->desc[eq->pidx];
2964 	IDXINCR(eq->pidx, ndesc, eq->sidx);
2965 	if (__predict_false(cookie->pidx + ndesc > eq->sidx)) {
2966 		w = &wrq->ss[0];
2967 		wrq->ss_pidx = cookie->pidx;
2968 		wrq->ss_len = len16 * 16;
2969 	}
2970 
2971 	EQ_UNLOCK(eq);
2972 
2973 	return (w);
2974 }
2975 
2976 void
2977 commit_wrq_wr(struct sge_wrq *wrq, void *w, struct wrq_cookie *cookie)
2978 {
2979 	struct sge_eq *eq = &wrq->eq;
2980 	struct adapter *sc = wrq->adapter;
2981 	int ndesc, pidx;
2982 	struct wrq_cookie *prev, *next;
2983 
2984 	if (cookie->pidx == -1) {
2985 		struct wrqe *wr = __containerof(w, struct wrqe, wr);
2986 
2987 		t4_wrq_tx(sc, wr);
2988 		return;
2989 	}
2990 
2991 	if (__predict_false(w == &wrq->ss[0])) {
2992 		int n = (eq->sidx - wrq->ss_pidx) * EQ_ESIZE;
2993 
2994 		MPASS(wrq->ss_len > n);	/* WR had better wrap around. */
2995 		bcopy(&wrq->ss[0], &eq->desc[wrq->ss_pidx], n);
2996 		bcopy(&wrq->ss[n], &eq->desc[0], wrq->ss_len - n);
2997 		wrq->tx_wrs_ss++;
2998 	} else
2999 		wrq->tx_wrs_direct++;
3000 
3001 	EQ_LOCK(eq);
3002 	ndesc = cookie->ndesc;	/* Can be more than SGE_MAX_WR_NDESC here. */
3003 	pidx = cookie->pidx;
3004 	MPASS(pidx >= 0 && pidx < eq->sidx);
3005 	prev = TAILQ_PREV(cookie, wrq_incomplete_wrs, link);
3006 	next = TAILQ_NEXT(cookie, link);
3007 	if (prev == NULL) {
3008 		MPASS(pidx == eq->dbidx);
3009 		if (next == NULL || ndesc >= 16) {
3010 			int available;
3011 			struct fw_eth_tx_pkt_wr *dst;	/* any fw WR struct will do */
3012 
3013 			/*
3014 			 * Note that the WR via which we'll request tx updates
3015 			 * is at pidx and not eq->pidx, which has moved on
3016 			 * already.
3017 			 */
3018 			dst = (void *)&eq->desc[pidx];
3019 			available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
3020 			if (available < eq->sidx / 4 &&
3021 			    atomic_cmpset_int(&eq->equiq, 0, 1)) {
3022 				/*
3023 				 * XXX: This is not 100% reliable with some
3024 				 * types of WRs.  But this is a very unusual
3025 				 * situation for an ofld/ctrl queue anyway.
3026 				 */
3027 				dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ |
3028 				    F_FW_WR_EQUEQ);
3029 			}
3030 
3031 			ring_eq_db(wrq->adapter, eq, ndesc);
3032 		} else {
3033 			MPASS(IDXDIFF(next->pidx, pidx, eq->sidx) == ndesc);
3034 			next->pidx = pidx;
3035 			next->ndesc += ndesc;
3036 		}
3037 	} else {
3038 		MPASS(IDXDIFF(pidx, prev->pidx, eq->sidx) == prev->ndesc);
3039 		prev->ndesc += ndesc;
3040 	}
3041 	TAILQ_REMOVE(&wrq->incomplete_wrs, cookie, link);
3042 
3043 	if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list))
3044 		drain_wrq_wr_list(sc, wrq);
3045 
3046 #ifdef INVARIANTS
3047 	if (TAILQ_EMPTY(&wrq->incomplete_wrs)) {
3048 		/* Doorbell must have caught up to the pidx. */
3049 		MPASS(wrq->eq.pidx == wrq->eq.dbidx);
3050 	}
3051 #endif
3052 	EQ_UNLOCK(eq);
3053 }
3054 
3055 static u_int
3056 can_resume_eth_tx(struct mp_ring *r)
3057 {
3058 	struct sge_eq *eq = r->cookie;
3059 
3060 	return (total_available_tx_desc(eq) > eq->sidx / 8);
3061 }
3062 
3063 static inline bool
3064 cannot_use_txpkts(struct mbuf *m)
3065 {
3066 	/* maybe put a GL limit too, to avoid silliness? */
3067 
3068 	return (needs_tso(m) || (mbuf_cflags(m) & (MC_RAW_WR | MC_TLS)) != 0);
3069 }
3070 
3071 static inline int
3072 discard_tx(struct sge_eq *eq)
3073 {
3074 
3075 	return ((eq->flags & (EQ_ENABLED | EQ_QFLUSH)) != EQ_ENABLED);
3076 }
3077 
3078 static inline int
3079 wr_can_update_eq(void *p)
3080 {
3081 	struct fw_eth_tx_pkts_wr *wr = p;
3082 
3083 	switch (G_FW_WR_OP(be32toh(wr->op_pkd))) {
3084 	case FW_ULPTX_WR:
3085 	case FW_ETH_TX_PKT_WR:
3086 	case FW_ETH_TX_PKTS_WR:
3087 	case FW_ETH_TX_PKTS2_WR:
3088 	case FW_ETH_TX_PKT_VM_WR:
3089 	case FW_ETH_TX_PKTS_VM_WR:
3090 		return (1);
3091 	default:
3092 		return (0);
3093 	}
3094 }
3095 
3096 static inline void
3097 set_txupdate_flags(struct sge_txq *txq, u_int avail,
3098     struct fw_eth_tx_pkt_wr *wr)
3099 {
3100 	struct sge_eq *eq = &txq->eq;
3101 	struct txpkts *txp = &txq->txp;
3102 
3103 	if ((txp->npkt > 0 || avail < eq->sidx / 2) &&
3104 	    atomic_cmpset_int(&eq->equiq, 0, 1)) {
3105 		wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ | F_FW_WR_EQUIQ);
3106 		eq->equeqidx = eq->pidx;
3107 	} else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 32) {
3108 		wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ);
3109 		eq->equeqidx = eq->pidx;
3110 	}
3111 }
3112 
3113 #if defined(__i386__) || defined(__amd64__)
3114 extern uint64_t tsc_freq;
3115 #endif
3116 
3117 static inline bool
3118 record_eth_tx_time(struct sge_txq *txq)
3119 {
3120 	const uint64_t cycles = get_cyclecount();
3121 	const uint64_t last_tx = txq->last_tx;
3122 #if defined(__i386__) || defined(__amd64__)
3123 	const uint64_t itg = tsc_freq * t4_tx_coalesce_gap / 1000000;
3124 #else
3125 	const uint64_t itg = 0;
3126 #endif
3127 
3128 	MPASS(cycles >= last_tx);
3129 	txq->last_tx = cycles;
3130 	return (cycles - last_tx < itg);
3131 }
3132 
3133 /*
3134  * r->items[cidx] to r->items[pidx], with a wraparound at r->size, are ready to
3135  * be consumed.  Return the actual number consumed.  0 indicates a stall.
3136  */
3137 static u_int
3138 eth_tx(struct mp_ring *r, u_int cidx, u_int pidx, bool *coalescing)
3139 {
3140 	struct sge_txq *txq = r->cookie;
3141 	struct ifnet *ifp = txq->ifp;
3142 	struct sge_eq *eq = &txq->eq;
3143 	struct txpkts *txp = &txq->txp;
3144 	struct vi_info *vi = ifp->if_softc;
3145 	struct adapter *sc = vi->adapter;
3146 	u_int total, remaining;		/* # of packets */
3147 	u_int n, avail, dbdiff;		/* # of hardware descriptors */
3148 	int i, rc;
3149 	struct mbuf *m0;
3150 	bool snd, recent_tx;
3151 	void *wr;	/* start of the last WR written to the ring */
3152 
3153 	TXQ_LOCK_ASSERT_OWNED(txq);
3154 	recent_tx = record_eth_tx_time(txq);
3155 
3156 	remaining = IDXDIFF(pidx, cidx, r->size);
3157 	if (__predict_false(discard_tx(eq))) {
3158 		for (i = 0; i < txp->npkt; i++)
3159 			m_freem(txp->mb[i]);
3160 		txp->npkt = 0;
3161 		while (cidx != pidx) {
3162 			m0 = r->items[cidx];
3163 			m_freem(m0);
3164 			if (++cidx == r->size)
3165 				cidx = 0;
3166 		}
3167 		reclaim_tx_descs(txq, eq->sidx);
3168 		*coalescing = false;
3169 		return (remaining);	/* emptied */
3170 	}
3171 
3172 	/* How many hardware descriptors do we have readily available. */
3173 	if (eq->pidx == eq->cidx)
3174 		avail = eq->sidx - 1;
3175 	else
3176 		avail = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
3177 
3178 	total = 0;
3179 	if (remaining == 0) {
3180 		txp->score = 0;
3181 		txq->txpkts_flush++;
3182 		goto send_txpkts;
3183 	}
3184 
3185 	dbdiff = 0;
3186 	MPASS(remaining > 0);
3187 	while (remaining > 0) {
3188 		m0 = r->items[cidx];
3189 		M_ASSERTPKTHDR(m0);
3190 		MPASS(m0->m_nextpkt == NULL);
3191 
3192 		if (avail < 2 * SGE_MAX_WR_NDESC)
3193 			avail += reclaim_tx_descs(txq, 64);
3194 
3195 		if (t4_tx_coalesce == 0 && txp->npkt == 0)
3196 			goto skip_coalescing;
3197 		if (cannot_use_txpkts(m0))
3198 			txp->score = 0;
3199 		else if (recent_tx) {
3200 			if (++txp->score == 0)
3201 				txp->score = UINT8_MAX;
3202 		} else
3203 			txp->score = 1;
3204 		if (txp->npkt > 0 || remaining > 1 ||
3205 		    txp->score >= t4_tx_coalesce_pkts ||
3206 		    atomic_load_int(&txq->eq.equiq) != 0) {
3207 			if (vi->flags & TX_USES_VM_WR)
3208 				rc = add_to_txpkts_vf(sc, txq, m0, avail, &snd);
3209 			else
3210 				rc = add_to_txpkts_pf(sc, txq, m0, avail, &snd);
3211 		} else {
3212 			snd = false;
3213 			rc = EINVAL;
3214 		}
3215 		if (snd) {
3216 			MPASS(txp->npkt > 0);
3217 			for (i = 0; i < txp->npkt; i++)
3218 				ETHER_BPF_MTAP(ifp, txp->mb[i]);
3219 			if (txp->npkt > 1) {
3220 				MPASS(avail >= tx_len16_to_desc(txp->len16));
3221 				if (vi->flags & TX_USES_VM_WR)
3222 					n = write_txpkts_vm_wr(sc, txq);
3223 				else
3224 					n = write_txpkts_wr(sc, txq);
3225 			} else {
3226 				MPASS(avail >=
3227 				    tx_len16_to_desc(mbuf_len16(txp->mb[0])));
3228 				if (vi->flags & TX_USES_VM_WR)
3229 					n = write_txpkt_vm_wr(sc, txq,
3230 					    txp->mb[0]);
3231 				else
3232 					n = write_txpkt_wr(sc, txq, txp->mb[0],
3233 					    avail);
3234 			}
3235 			MPASS(n <= SGE_MAX_WR_NDESC);
3236 			avail -= n;
3237 			dbdiff += n;
3238 			wr = &eq->desc[eq->pidx];
3239 			IDXINCR(eq->pidx, n, eq->sidx);
3240 			txp->npkt = 0;	/* emptied */
3241 		}
3242 		if (rc == 0) {
3243 			/* m0 was coalesced into txq->txpkts. */
3244 			goto next_mbuf;
3245 		}
3246 		if (rc == EAGAIN) {
3247 			/*
3248 			 * m0 is suitable for tx coalescing but could not be
3249 			 * combined with the existing txq->txpkts, which has now
3250 			 * been transmitted.  Start a new txpkts with m0.
3251 			 */
3252 			MPASS(snd);
3253 			MPASS(txp->npkt == 0);
3254 			continue;
3255 		}
3256 
3257 		MPASS(rc != 0 && rc != EAGAIN);
3258 		MPASS(txp->npkt == 0);
3259 skip_coalescing:
3260 		n = tx_len16_to_desc(mbuf_len16(m0));
3261 		if (__predict_false(avail < n)) {
3262 			avail += reclaim_tx_descs(txq, min(n, 32));
3263 			if (avail < n)
3264 				break;	/* out of descriptors */
3265 		}
3266 
3267 		wr = &eq->desc[eq->pidx];
3268 		if (mbuf_cflags(m0) & MC_RAW_WR) {
3269 			n = write_raw_wr(txq, wr, m0, avail);
3270 #ifdef KERN_TLS
3271 		} else if (mbuf_cflags(m0) & MC_TLS) {
3272 			ETHER_BPF_MTAP(ifp, m0);
3273 			n = t6_ktls_write_wr(txq, wr, m0, mbuf_nsegs(m0),
3274 			    avail);
3275 #endif
3276 		} else {
3277 			ETHER_BPF_MTAP(ifp, m0);
3278 			if (vi->flags & TX_USES_VM_WR)
3279 				n = write_txpkt_vm_wr(sc, txq, m0);
3280 			else
3281 				n = write_txpkt_wr(sc, txq, m0, avail);
3282 		}
3283 		MPASS(n >= 1 && n <= avail);
3284 		if (!(mbuf_cflags(m0) & MC_TLS))
3285 			MPASS(n <= SGE_MAX_WR_NDESC);
3286 
3287 		avail -= n;
3288 		dbdiff += n;
3289 		IDXINCR(eq->pidx, n, eq->sidx);
3290 
3291 		if (dbdiff >= 512 / EQ_ESIZE) {	/* X_FETCHBURSTMAX_512B */
3292 			if (wr_can_update_eq(wr))
3293 				set_txupdate_flags(txq, avail, wr);
3294 			ring_eq_db(sc, eq, dbdiff);
3295 			avail += reclaim_tx_descs(txq, 32);
3296 			dbdiff = 0;
3297 		}
3298 next_mbuf:
3299 		total++;
3300 		remaining--;
3301 		if (__predict_false(++cidx == r->size))
3302 			cidx = 0;
3303 	}
3304 	if (dbdiff != 0) {
3305 		if (wr_can_update_eq(wr))
3306 			set_txupdate_flags(txq, avail, wr);
3307 		ring_eq_db(sc, eq, dbdiff);
3308 		reclaim_tx_descs(txq, 32);
3309 	} else if (eq->pidx == eq->cidx && txp->npkt > 0 &&
3310 	    atomic_load_int(&txq->eq.equiq) == 0) {
3311 		/*
3312 		 * If nothing was submitted to the chip for tx (it was coalesced
3313 		 * into txpkts instead) and there is no tx update outstanding
3314 		 * then we need to send txpkts now.
3315 		 */
3316 send_txpkts:
3317 		MPASS(txp->npkt > 0);
3318 		for (i = 0; i < txp->npkt; i++)
3319 			ETHER_BPF_MTAP(ifp, txp->mb[i]);
3320 		if (txp->npkt > 1) {
3321 			MPASS(avail >= tx_len16_to_desc(txp->len16));
3322 			if (vi->flags & TX_USES_VM_WR)
3323 				n = write_txpkts_vm_wr(sc, txq);
3324 			else
3325 				n = write_txpkts_wr(sc, txq);
3326 		} else {
3327 			MPASS(avail >=
3328 			    tx_len16_to_desc(mbuf_len16(txp->mb[0])));
3329 			if (vi->flags & TX_USES_VM_WR)
3330 				n = write_txpkt_vm_wr(sc, txq, txp->mb[0]);
3331 			else
3332 				n = write_txpkt_wr(sc, txq, txp->mb[0], avail);
3333 		}
3334 		MPASS(n <= SGE_MAX_WR_NDESC);
3335 		wr = &eq->desc[eq->pidx];
3336 		IDXINCR(eq->pidx, n, eq->sidx);
3337 		txp->npkt = 0;	/* emptied */
3338 
3339 		MPASS(wr_can_update_eq(wr));
3340 		set_txupdate_flags(txq, avail - n, wr);
3341 		ring_eq_db(sc, eq, n);
3342 		reclaim_tx_descs(txq, 32);
3343 	}
3344 	*coalescing = txp->npkt > 0;
3345 
3346 	return (total);
3347 }
3348 
3349 static inline void
3350 init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int pktc_idx,
3351     int qsize, int intr_idx, int cong)
3352 {
3353 
3354 	KASSERT(tmr_idx >= 0 && tmr_idx < SGE_NTIMERS,
3355 	    ("%s: bad tmr_idx %d", __func__, tmr_idx));
3356 	KASSERT(pktc_idx < SGE_NCOUNTERS,	/* -ve is ok, means don't use */
3357 	    ("%s: bad pktc_idx %d", __func__, pktc_idx));
3358 	KASSERT(intr_idx >= -1 && intr_idx < sc->intr_count,
3359 	    ("%s: bad intr_idx %d", __func__, intr_idx));
3360 
3361 	iq->flags = 0;
3362 	iq->state = IQS_DISABLED;
3363 	iq->adapter = sc;
3364 	iq->intr_params = V_QINTR_TIMER_IDX(tmr_idx);
3365 	iq->intr_pktc_idx = SGE_NCOUNTERS - 1;
3366 	if (pktc_idx >= 0) {
3367 		iq->intr_params |= F_QINTR_CNT_EN;
3368 		iq->intr_pktc_idx = pktc_idx;
3369 	}
3370 	iq->qsize = roundup2(qsize, 16);	/* See FW_IQ_CMD/iqsize */
3371 	iq->sidx = iq->qsize - sc->params.sge.spg_len / IQ_ESIZE;
3372 	iq->intr_idx = intr_idx;
3373 	iq->cong = cong;
3374 }
3375 
3376 static inline void
3377 init_fl(struct adapter *sc, struct sge_fl *fl, int qsize, int maxp, char *name)
3378 {
3379 	struct sge_params *sp = &sc->params.sge;
3380 
3381 	fl->qsize = qsize;
3382 	fl->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE;
3383 	strlcpy(fl->lockname, name, sizeof(fl->lockname));
3384 	mtx_init(&fl->fl_lock, fl->lockname, NULL, MTX_DEF);
3385 	if (sc->flags & BUF_PACKING_OK &&
3386 	    ((!is_t4(sc) && buffer_packing) ||	/* T5+: enabled unless 0 */
3387 	    (is_t4(sc) && buffer_packing == 1)))/* T4: disabled unless 1 */
3388 		fl->flags |= FL_BUF_PACKING;
3389 	fl->zidx = find_refill_source(sc, maxp, fl->flags & FL_BUF_PACKING);
3390 	fl->safe_zidx = sc->sge.safe_zidx;
3391 	if (fl->flags & FL_BUF_PACKING) {
3392 		fl->lowat = roundup2(sp->fl_starve_threshold2, 8);
3393 		fl->buf_boundary = sp->pack_boundary;
3394 	} else {
3395 		fl->lowat = roundup2(sp->fl_starve_threshold, 8);
3396 		fl->buf_boundary = 16;
3397 	}
3398 	if (fl_pad && fl->buf_boundary < sp->pad_boundary)
3399 		fl->buf_boundary = sp->pad_boundary;
3400 }
3401 
3402 static inline void
3403 init_eq(struct adapter *sc, struct sge_eq *eq, int eqtype, int qsize,
3404     uint8_t tx_chan, struct sge_iq *iq, char *name)
3405 {
3406 	KASSERT(eqtype >= EQ_CTRL && eqtype <= EQ_OFLD,
3407 	    ("%s: bad qtype %d", __func__, eqtype));
3408 
3409 	eq->type = eqtype;
3410 	eq->tx_chan = tx_chan;
3411 	eq->iq = iq;
3412 	eq->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE;
3413 	strlcpy(eq->lockname, name, sizeof(eq->lockname));
3414 	mtx_init(&eq->eq_lock, eq->lockname, NULL, MTX_DEF);
3415 }
3416 
3417 int
3418 alloc_ring(struct adapter *sc, size_t len, bus_dma_tag_t *tag,
3419     bus_dmamap_t *map, bus_addr_t *pa, void **va)
3420 {
3421 	int rc;
3422 
3423 	rc = bus_dma_tag_create(sc->dmat, 512, 0, BUS_SPACE_MAXADDR,
3424 	    BUS_SPACE_MAXADDR, NULL, NULL, len, 1, len, 0, NULL, NULL, tag);
3425 	if (rc != 0) {
3426 		CH_ERR(sc, "cannot allocate DMA tag: %d\n", rc);
3427 		goto done;
3428 	}
3429 
3430 	rc = bus_dmamem_alloc(*tag, va,
3431 	    BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, map);
3432 	if (rc != 0) {
3433 		CH_ERR(sc, "cannot allocate DMA memory: %d\n", rc);
3434 		goto done;
3435 	}
3436 
3437 	rc = bus_dmamap_load(*tag, *map, *va, len, oneseg_dma_callback, pa, 0);
3438 	if (rc != 0) {
3439 		CH_ERR(sc, "cannot load DMA map: %d\n", rc);
3440 		goto done;
3441 	}
3442 done:
3443 	if (rc)
3444 		free_ring(sc, *tag, *map, *pa, *va);
3445 
3446 	return (rc);
3447 }
3448 
3449 int
3450 free_ring(struct adapter *sc, bus_dma_tag_t tag, bus_dmamap_t map,
3451     bus_addr_t pa, void *va)
3452 {
3453 	if (pa)
3454 		bus_dmamap_unload(tag, map);
3455 	if (va)
3456 		bus_dmamem_free(tag, va, map);
3457 	if (tag)
3458 		bus_dma_tag_destroy(tag);
3459 
3460 	return (0);
3461 }
3462 
3463 /*
3464  * Allocates the software resources (mainly memory and sysctl nodes) for an
3465  * ingress queue and an optional freelist.
3466  *
3467  * Sets IQ_SW_ALLOCATED and returns 0 on success.
3468  */
3469 static int
3470 alloc_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl,
3471     struct sysctl_ctx_list *ctx, struct sysctl_oid *oid)
3472 {
3473 	int rc;
3474 	size_t len;
3475 	struct adapter *sc = vi->adapter;
3476 
3477 	MPASS(!(iq->flags & IQ_SW_ALLOCATED));
3478 
3479 	len = iq->qsize * IQ_ESIZE;
3480 	rc = alloc_ring(sc, len, &iq->desc_tag, &iq->desc_map, &iq->ba,
3481 	    (void **)&iq->desc);
3482 	if (rc != 0)
3483 		return (rc);
3484 
3485 	if (fl) {
3486 		len = fl->qsize * EQ_ESIZE;
3487 		rc = alloc_ring(sc, len, &fl->desc_tag, &fl->desc_map,
3488 		    &fl->ba, (void **)&fl->desc);
3489 		if (rc) {
3490 			free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba,
3491 			    iq->desc);
3492 			return (rc);
3493 		}
3494 
3495 		/* Allocate space for one software descriptor per buffer. */
3496 		fl->sdesc = malloc(fl->sidx * 8 * sizeof(struct fl_sdesc),
3497 		    M_CXGBE, M_ZERO | M_WAITOK);
3498 
3499 		add_fl_sysctls(sc, ctx, oid, fl);
3500 		iq->flags |= IQ_HAS_FL;
3501 	}
3502 	add_iq_sysctls(ctx, oid, iq);
3503 	iq->flags |= IQ_SW_ALLOCATED;
3504 
3505 	return (0);
3506 }
3507 
3508 /*
3509  * Frees all software resources (memory and locks) associated with an ingress
3510  * queue and an optional freelist.
3511  */
3512 static void
3513 free_iq_fl(struct adapter *sc, struct sge_iq *iq, struct sge_fl *fl)
3514 {
3515 	MPASS(iq->flags & IQ_SW_ALLOCATED);
3516 
3517 	if (fl) {
3518 		MPASS(iq->flags & IQ_HAS_FL);
3519 		free_ring(sc, fl->desc_tag, fl->desc_map, fl->ba, fl->desc);
3520 		free_fl_buffers(sc, fl);
3521 		free(fl->sdesc, M_CXGBE);
3522 		mtx_destroy(&fl->fl_lock);
3523 		bzero(fl, sizeof(*fl));
3524 	}
3525 	free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, iq->desc);
3526 	bzero(iq, sizeof(*iq));
3527 }
3528 
3529 /*
3530  * Allocates a hardware ingress queue and an optional freelist that will be
3531  * associated with it.
3532  *
3533  * Returns errno on failure.  Resources allocated up to that point may still be
3534  * allocated.  Caller is responsible for cleanup in case this function fails.
3535  */
3536 static int
3537 alloc_iq_fl_hwq(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl)
3538 {
3539 	int rc, i, cntxt_id;
3540 	struct fw_iq_cmd c;
3541 	struct adapter *sc = vi->adapter;
3542 	__be32 v = 0;
3543 
3544 	MPASS (!(iq->flags & IQ_HW_ALLOCATED));
3545 
3546 	bzero(&c, sizeof(c));
3547 	c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
3548 	    F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) |
3549 	    V_FW_IQ_CMD_VFN(0));
3550 
3551 	c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART |
3552 	    FW_LEN16(c));
3553 
3554 	/* Special handling for firmware event queue */
3555 	if (iq == &sc->sge.fwq)
3556 		v |= F_FW_IQ_CMD_IQASYNCH;
3557 
3558 	if (iq->intr_idx < 0) {
3559 		/* Forwarded interrupts, all headed to fwq */
3560 		v |= F_FW_IQ_CMD_IQANDST;
3561 		v |= V_FW_IQ_CMD_IQANDSTINDEX(sc->sge.fwq.cntxt_id);
3562 	} else {
3563 		KASSERT(iq->intr_idx < sc->intr_count,
3564 		    ("%s: invalid direct intr_idx %d", __func__, iq->intr_idx));
3565 		v |= V_FW_IQ_CMD_IQANDSTINDEX(iq->intr_idx);
3566 	}
3567 
3568 	bzero(iq->desc, iq->qsize * IQ_ESIZE);
3569 	c.type_to_iqandstindex = htobe32(v |
3570 	    V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) |
3571 	    V_FW_IQ_CMD_VIID(vi->viid) |
3572 	    V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT));
3573 	c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(vi->pi->tx_chan) |
3574 	    F_FW_IQ_CMD_IQGTSMODE |
3575 	    V_FW_IQ_CMD_IQINTCNTTHRESH(iq->intr_pktc_idx) |
3576 	    V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4));
3577 	c.iqsize = htobe16(iq->qsize);
3578 	c.iqaddr = htobe64(iq->ba);
3579 	if (iq->cong >= 0)
3580 		c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN);
3581 
3582 	if (fl) {
3583 		bzero(fl->desc, fl->sidx * EQ_ESIZE + sc->params.sge.spg_len);
3584 		c.iqns_to_fl0congen |=
3585 		    htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) |
3586 			F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO |
3587 			(fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) |
3588 			(fl->flags & FL_BUF_PACKING ? F_FW_IQ_CMD_FL0PACKEN :
3589 			    0));
3590 		if (iq->cong >= 0) {
3591 			c.iqns_to_fl0congen |=
3592 				htobe32(V_FW_IQ_CMD_FL0CNGCHMAP(iq->cong) |
3593 				    F_FW_IQ_CMD_FL0CONGCIF |
3594 				    F_FW_IQ_CMD_FL0CONGEN);
3595 		}
3596 		c.fl0dcaen_to_fl0cidxfthresh =
3597 		    htobe16(V_FW_IQ_CMD_FL0FBMIN(chip_id(sc) <= CHELSIO_T5 ?
3598 			X_FETCHBURSTMIN_128B : X_FETCHBURSTMIN_64B_T6) |
3599 			V_FW_IQ_CMD_FL0FBMAX(chip_id(sc) <= CHELSIO_T5 ?
3600 			X_FETCHBURSTMAX_512B : X_FETCHBURSTMAX_256B));
3601 		c.fl0size = htobe16(fl->qsize);
3602 		c.fl0addr = htobe64(fl->ba);
3603 	}
3604 
3605 	rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
3606 	if (rc != 0) {
3607 		CH_ERR(sc, "failed to create hw ingress queue: %d\n", rc);
3608 		return (rc);
3609 	}
3610 
3611 	iq->cidx = 0;
3612 	iq->gen = F_RSPD_GEN;
3613 	iq->cntxt_id = be16toh(c.iqid);
3614 	iq->abs_id = be16toh(c.physiqid);
3615 
3616 	cntxt_id = iq->cntxt_id - sc->sge.iq_start;
3617 	if (cntxt_id >= sc->sge.iqmap_sz) {
3618 		panic ("%s: iq->cntxt_id (%d) more than the max (%d)", __func__,
3619 		    cntxt_id, sc->sge.iqmap_sz - 1);
3620 	}
3621 	sc->sge.iqmap[cntxt_id] = iq;
3622 
3623 	if (fl) {
3624 		u_int qid;
3625 #ifdef INVARIANTS
3626 		MPASS(!(fl->flags & FL_BUF_RESUME));
3627 		for (i = 0; i < fl->sidx * 8; i++)
3628 			MPASS(fl->sdesc[i].cl == NULL);
3629 #endif
3630 		fl->cntxt_id = be16toh(c.fl0id);
3631 		fl->pidx = fl->cidx = fl->hw_cidx = fl->dbidx = 0;
3632 		fl->rx_offset = 0;
3633 		fl->flags &= ~(FL_STARVING | FL_DOOMED);
3634 
3635 		cntxt_id = fl->cntxt_id - sc->sge.eq_start;
3636 		if (cntxt_id >= sc->sge.eqmap_sz) {
3637 			panic("%s: fl->cntxt_id (%d) more than the max (%d)",
3638 			    __func__, cntxt_id, sc->sge.eqmap_sz - 1);
3639 		}
3640 		sc->sge.eqmap[cntxt_id] = (void *)fl;
3641 
3642 		qid = fl->cntxt_id;
3643 		if (isset(&sc->doorbells, DOORBELL_UDB)) {
3644 			uint32_t s_qpp = sc->params.sge.eq_s_qpp;
3645 			uint32_t mask = (1 << s_qpp) - 1;
3646 			volatile uint8_t *udb;
3647 
3648 			udb = sc->udbs_base + UDBS_DB_OFFSET;
3649 			udb += (qid >> s_qpp) << PAGE_SHIFT;
3650 			qid &= mask;
3651 			if (qid < PAGE_SIZE / UDBS_SEG_SIZE) {
3652 				udb += qid << UDBS_SEG_SHIFT;
3653 				qid = 0;
3654 			}
3655 			fl->udb = (volatile void *)udb;
3656 		}
3657 		fl->dbval = V_QID(qid) | sc->chip_params->sge_fl_db;
3658 
3659 		FL_LOCK(fl);
3660 		/* Enough to make sure the SGE doesn't think it's starved */
3661 		refill_fl(sc, fl, fl->lowat);
3662 		FL_UNLOCK(fl);
3663 	}
3664 
3665 	if (chip_id(sc) >= CHELSIO_T5 && !(sc->flags & IS_VF) && iq->cong >= 0) {
3666 		uint32_t param, val;
3667 
3668 		param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
3669 		    V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) |
3670 		    V_FW_PARAMS_PARAM_YZ(iq->cntxt_id);
3671 		if (iq->cong == 0)
3672 			val = 1 << 19;
3673 		else {
3674 			val = 2 << 19;
3675 			for (i = 0; i < 4; i++) {
3676 				if (iq->cong & (1 << i))
3677 					val |= 1 << (i << 2);
3678 			}
3679 		}
3680 
3681 		rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &param, &val);
3682 		if (rc != 0) {
3683 			/* report error but carry on */
3684 			CH_ERR(sc, "failed to set congestion manager context "
3685 			    "for ingress queue %d: %d\n", iq->cntxt_id, rc);
3686 		}
3687 	}
3688 
3689 	/* Enable IQ interrupts */
3690 	atomic_store_rel_int(&iq->state, IQS_IDLE);
3691 	t4_write_reg(sc, sc->sge_gts_reg, V_SEINTARM(iq->intr_params) |
3692 	    V_INGRESSQID(iq->cntxt_id));
3693 
3694 	iq->flags |= IQ_HW_ALLOCATED;
3695 
3696 	return (0);
3697 }
3698 
3699 static int
3700 free_iq_fl_hwq(struct adapter *sc, struct sge_iq *iq, struct sge_fl *fl)
3701 {
3702 	int rc;
3703 
3704 	MPASS(iq->flags & IQ_HW_ALLOCATED);
3705 	rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0, FW_IQ_TYPE_FL_INT_CAP,
3706 	    iq->cntxt_id, fl ? fl->cntxt_id : 0xffff, 0xffff);
3707 	if (rc != 0) {
3708 		CH_ERR(sc, "failed to free iq %p: %d\n", iq, rc);
3709 		return (rc);
3710 	}
3711 	iq->flags &= ~IQ_HW_ALLOCATED;
3712 
3713 	return (0);
3714 }
3715 
3716 static void
3717 add_iq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid,
3718     struct sge_iq *iq)
3719 {
3720 	struct sysctl_oid_list *children;
3721 
3722 	if (ctx == NULL || oid == NULL)
3723 		return;
3724 
3725 	children = SYSCTL_CHILDREN(oid);
3726 	SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, &iq->ba,
3727 	    "bus address of descriptor ring");
3728 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
3729 	    iq->qsize * IQ_ESIZE, "descriptor ring size in bytes");
3730 	SYSCTL_ADD_U16(ctx, children, OID_AUTO, "abs_id", CTLFLAG_RD,
3731 	    &iq->abs_id, 0, "absolute id of the queue");
3732 	SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
3733 	    &iq->cntxt_id, 0, "SGE context id of the queue");
3734 	SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &iq->cidx,
3735 	    0, "consumer index");
3736 }
3737 
3738 static void
3739 add_fl_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx,
3740     struct sysctl_oid *oid, struct sge_fl *fl)
3741 {
3742 	struct sysctl_oid_list *children;
3743 
3744 	if (ctx == NULL || oid == NULL)
3745 		return;
3746 
3747 	children = SYSCTL_CHILDREN(oid);
3748 	oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl",
3749 	    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "freelist");
3750 	children = SYSCTL_CHILDREN(oid);
3751 
3752 	SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD,
3753 	    &fl->ba, "bus address of descriptor ring");
3754 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
3755 	    fl->sidx * EQ_ESIZE + sc->params.sge.spg_len,
3756 	    "desc ring size in bytes");
3757 	SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
3758 	    &fl->cntxt_id, 0, "SGE context id of the freelist");
3759 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "padding", CTLFLAG_RD, NULL,
3760 	    fl_pad ? 1 : 0, "padding enabled");
3761 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "packing", CTLFLAG_RD, NULL,
3762 	    fl->flags & FL_BUF_PACKING ? 1 : 0, "packing enabled");
3763 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &fl->cidx,
3764 	    0, "consumer index");
3765 	if (fl->flags & FL_BUF_PACKING) {
3766 		SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rx_offset",
3767 		    CTLFLAG_RD, &fl->rx_offset, 0, "packing rx offset");
3768 	}
3769 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &fl->pidx,
3770 	    0, "producer index");
3771 	SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_allocated",
3772 	    CTLFLAG_RD, &fl->cl_allocated, "# of clusters allocated");
3773 	SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_recycled",
3774 	    CTLFLAG_RD, &fl->cl_recycled, "# of clusters recycled");
3775 	SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_fast_recycled",
3776 	    CTLFLAG_RD, &fl->cl_fast_recycled, "# of clusters recycled (fast)");
3777 }
3778 
3779 /*
3780  * Idempotent.
3781  */
3782 static int
3783 alloc_fwq(struct adapter *sc)
3784 {
3785 	int rc, intr_idx;
3786 	struct sge_iq *fwq = &sc->sge.fwq;
3787 	struct vi_info *vi = &sc->port[0]->vi[0];
3788 
3789 	if (!(fwq->flags & IQ_SW_ALLOCATED)) {
3790 		MPASS(!(fwq->flags & IQ_HW_ALLOCATED));
3791 
3792 		if (sc->flags & IS_VF)
3793 			intr_idx = 0;
3794 		else
3795 			intr_idx = sc->intr_count > 1 ? 1 : 0;
3796 		init_iq(fwq, sc, 0, 0, FW_IQ_QSIZE, intr_idx, -1);
3797 		rc = alloc_iq_fl(vi, fwq, NULL, &sc->ctx, sc->fwq_oid);
3798 		if (rc != 0) {
3799 			CH_ERR(sc, "failed to allocate fwq: %d\n", rc);
3800 			return (rc);
3801 		}
3802 		MPASS(fwq->flags & IQ_SW_ALLOCATED);
3803 	}
3804 
3805 	if (!(fwq->flags & IQ_HW_ALLOCATED)) {
3806 		MPASS(fwq->flags & IQ_SW_ALLOCATED);
3807 
3808 		rc = alloc_iq_fl_hwq(vi, fwq, NULL);
3809 		if (rc != 0) {
3810 			CH_ERR(sc, "failed to create hw fwq: %d\n", rc);
3811 			return (rc);
3812 		}
3813 		MPASS(fwq->flags & IQ_HW_ALLOCATED);
3814 	}
3815 
3816 	return (0);
3817 }
3818 
3819 /*
3820  * Idempotent.
3821  */
3822 static void
3823 free_fwq(struct adapter *sc)
3824 {
3825 	struct sge_iq *fwq = &sc->sge.fwq;
3826 
3827 	if (fwq->flags & IQ_HW_ALLOCATED) {
3828 		MPASS(fwq->flags & IQ_SW_ALLOCATED);
3829 		free_iq_fl_hwq(sc, fwq, NULL);
3830 		MPASS(!(fwq->flags & IQ_HW_ALLOCATED));
3831 	}
3832 
3833 	if (fwq->flags & IQ_SW_ALLOCATED) {
3834 		MPASS(!(fwq->flags & IQ_HW_ALLOCATED));
3835 		free_iq_fl(sc, fwq, NULL);
3836 		MPASS(!(fwq->flags & IQ_SW_ALLOCATED));
3837 	}
3838 }
3839 
3840 /*
3841  * Idempotent.
3842  */
3843 static int
3844 alloc_ctrlq(struct adapter *sc, int idx)
3845 {
3846 	int rc;
3847 	char name[16];
3848 	struct sysctl_oid *oid;
3849 	struct sge_wrq *ctrlq = &sc->sge.ctrlq[idx];
3850 
3851 	MPASS(idx < sc->params.nports);
3852 
3853 	if (!(ctrlq->eq.flags & EQ_SW_ALLOCATED)) {
3854 		MPASS(!(ctrlq->eq.flags & EQ_HW_ALLOCATED));
3855 
3856 		snprintf(name, sizeof(name), "%d", idx);
3857 		oid = SYSCTL_ADD_NODE(&sc->ctx, SYSCTL_CHILDREN(sc->ctrlq_oid),
3858 		    OID_AUTO, name, CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
3859 		    "ctrl queue");
3860 
3861 		snprintf(name, sizeof(name), "%s ctrlq%d",
3862 		    device_get_nameunit(sc->dev), idx);
3863 		init_eq(sc, &ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE,
3864 		    sc->port[idx]->tx_chan, &sc->sge.fwq, name);
3865 		rc = alloc_wrq(sc, NULL, ctrlq, &sc->ctx, oid);
3866 		if (rc != 0) {
3867 			CH_ERR(sc, "failed to allocate ctrlq%d: %d\n", idx, rc);
3868 			sysctl_remove_oid(oid, 1, 1);
3869 			return (rc);
3870 		}
3871 		MPASS(ctrlq->eq.flags & EQ_SW_ALLOCATED);
3872 	}
3873 
3874 	if (!(ctrlq->eq.flags & EQ_HW_ALLOCATED)) {
3875 		MPASS(ctrlq->eq.flags & EQ_SW_ALLOCATED);
3876 
3877 		rc = alloc_eq_hwq(sc, NULL, &ctrlq->eq);
3878 		if (rc != 0) {
3879 			CH_ERR(sc, "failed to create hw ctrlq%d: %d\n", idx, rc);
3880 			return (rc);
3881 		}
3882 		MPASS(ctrlq->eq.flags & EQ_HW_ALLOCATED);
3883 	}
3884 
3885 	return (0);
3886 }
3887 
3888 /*
3889  * Idempotent.
3890  */
3891 static void
3892 free_ctrlq(struct adapter *sc, int idx)
3893 {
3894 	struct sge_wrq *ctrlq = &sc->sge.ctrlq[idx];
3895 
3896 	if (ctrlq->eq.flags & EQ_HW_ALLOCATED) {
3897 		MPASS(ctrlq->eq.flags & EQ_SW_ALLOCATED);
3898 		free_eq_hwq(sc, NULL, &ctrlq->eq);
3899 		MPASS(!(ctrlq->eq.flags & EQ_HW_ALLOCATED));
3900 	}
3901 
3902 	if (ctrlq->eq.flags & EQ_SW_ALLOCATED) {
3903 		MPASS(!(ctrlq->eq.flags & EQ_HW_ALLOCATED));
3904 		free_wrq(sc, ctrlq);
3905 		MPASS(!(ctrlq->eq.flags & EQ_SW_ALLOCATED));
3906 	}
3907 }
3908 
3909 int
3910 tnl_cong(struct port_info *pi, int drop)
3911 {
3912 
3913 	if (drop == -1)
3914 		return (-1);
3915 	else if (drop == 1)
3916 		return (0);
3917 	else
3918 		return (pi->rx_e_chan_map);
3919 }
3920 
3921 /*
3922  * Idempotent.
3923  */
3924 static int
3925 alloc_rxq(struct vi_info *vi, struct sge_rxq *rxq, int idx, int intr_idx,
3926     int maxp)
3927 {
3928 	int rc;
3929 	struct adapter *sc = vi->adapter;
3930 	struct ifnet *ifp = vi->ifp;
3931 	struct sysctl_oid *oid;
3932 	char name[16];
3933 
3934 	if (!(rxq->iq.flags & IQ_SW_ALLOCATED)) {
3935 		MPASS(!(rxq->iq.flags & IQ_HW_ALLOCATED));
3936 #if defined(INET) || defined(INET6)
3937 		rc = tcp_lro_init_args(&rxq->lro, ifp, lro_entries, lro_mbufs);
3938 		if (rc != 0)
3939 			return (rc);
3940 		MPASS(rxq->lro.ifp == ifp);	/* also indicates LRO init'ed */
3941 #endif
3942 		rxq->ifp = ifp;
3943 
3944 		snprintf(name, sizeof(name), "%d", idx);
3945 		oid = SYSCTL_ADD_NODE(&vi->ctx, SYSCTL_CHILDREN(vi->rxq_oid),
3946 		    OID_AUTO, name, CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
3947 		    "rx queue");
3948 
3949 		init_iq(&rxq->iq, sc, vi->tmr_idx, vi->pktc_idx, vi->qsize_rxq,
3950 		    intr_idx, tnl_cong(vi->pi, cong_drop));
3951 #if defined(INET) || defined(INET6)
3952 		if (ifp->if_capenable & IFCAP_LRO)
3953 			rxq->iq.flags |= IQ_LRO_ENABLED;
3954 #endif
3955 		if (ifp->if_capenable & IFCAP_HWRXTSTMP)
3956 			rxq->iq.flags |= IQ_RX_TIMESTAMP;
3957 		snprintf(name, sizeof(name), "%s rxq%d-fl",
3958 		    device_get_nameunit(vi->dev), idx);
3959 		init_fl(sc, &rxq->fl, vi->qsize_rxq / 8, maxp, name);
3960 		rc = alloc_iq_fl(vi, &rxq->iq, &rxq->fl, &vi->ctx, oid);
3961 		if (rc != 0) {
3962 			CH_ERR(vi, "failed to allocate rxq%d: %d\n", idx, rc);
3963 			sysctl_remove_oid(oid, 1, 1);
3964 #if defined(INET) || defined(INET6)
3965 			tcp_lro_free(&rxq->lro);
3966 			rxq->lro.ifp = NULL;
3967 #endif
3968 			return (rc);
3969 		}
3970 		MPASS(rxq->iq.flags & IQ_SW_ALLOCATED);
3971 		add_rxq_sysctls(&vi->ctx, oid, rxq);
3972 	}
3973 
3974 	if (!(rxq->iq.flags & IQ_HW_ALLOCATED)) {
3975 		MPASS(rxq->iq.flags & IQ_SW_ALLOCATED);
3976 		rc = alloc_iq_fl_hwq(vi, &rxq->iq, &rxq->fl);
3977 		if (rc != 0) {
3978 			CH_ERR(vi, "failed to create hw rxq%d: %d\n", idx, rc);
3979 			return (rc);
3980 		}
3981 		MPASS(rxq->iq.flags & IQ_HW_ALLOCATED);
3982 
3983 		if (idx == 0)
3984 			sc->sge.iq_base = rxq->iq.abs_id - rxq->iq.cntxt_id;
3985 		else
3986 			KASSERT(rxq->iq.cntxt_id + sc->sge.iq_base == rxq->iq.abs_id,
3987 			    ("iq_base mismatch"));
3988 		KASSERT(sc->sge.iq_base == 0 || sc->flags & IS_VF,
3989 		    ("PF with non-zero iq_base"));
3990 
3991 		/*
3992 		 * The freelist is just barely above the starvation threshold
3993 		 * right now, fill it up a bit more.
3994 		 */
3995 		FL_LOCK(&rxq->fl);
3996 		refill_fl(sc, &rxq->fl, 128);
3997 		FL_UNLOCK(&rxq->fl);
3998 	}
3999 
4000 	return (0);
4001 }
4002 
4003 /*
4004  * Idempotent.
4005  */
4006 static void
4007 free_rxq(struct vi_info *vi, struct sge_rxq *rxq)
4008 {
4009 	if (rxq->iq.flags & IQ_HW_ALLOCATED) {
4010 		MPASS(rxq->iq.flags & IQ_SW_ALLOCATED);
4011 		free_iq_fl_hwq(vi->adapter, &rxq->iq, &rxq->fl);
4012 		MPASS(!(rxq->iq.flags & IQ_HW_ALLOCATED));
4013 	}
4014 
4015 	if (rxq->iq.flags & IQ_SW_ALLOCATED) {
4016 		MPASS(!(rxq->iq.flags & IQ_HW_ALLOCATED));
4017 #if defined(INET) || defined(INET6)
4018 		tcp_lro_free(&rxq->lro);
4019 #endif
4020 		free_iq_fl(vi->adapter, &rxq->iq, &rxq->fl);
4021 		MPASS(!(rxq->iq.flags & IQ_SW_ALLOCATED));
4022 		bzero(rxq, sizeof(*rxq));
4023 	}
4024 }
4025 
4026 static void
4027 add_rxq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid,
4028     struct sge_rxq *rxq)
4029 {
4030 	struct sysctl_oid_list *children;
4031 
4032 	if (ctx == NULL || oid == NULL)
4033 		return;
4034 
4035 	children = SYSCTL_CHILDREN(oid);
4036 #if defined(INET) || defined(INET6)
4037 	SYSCTL_ADD_U64(ctx, children, OID_AUTO, "lro_queued", CTLFLAG_RD,
4038 	    &rxq->lro.lro_queued, 0, NULL);
4039 	SYSCTL_ADD_U64(ctx, children, OID_AUTO, "lro_flushed", CTLFLAG_RD,
4040 	    &rxq->lro.lro_flushed, 0, NULL);
4041 #endif
4042 	SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "rxcsum", CTLFLAG_RD,
4043 	    &rxq->rxcsum, "# of times hardware assisted with checksum");
4044 	SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "vlan_extraction", CTLFLAG_RD,
4045 	    &rxq->vlan_extraction, "# of times hardware extracted 802.1Q tag");
4046 	SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "vxlan_rxcsum", CTLFLAG_RD,
4047 	    &rxq->vxlan_rxcsum,
4048 	    "# of times hardware assisted with inner checksum (VXLAN)");
4049 }
4050 
4051 #ifdef TCP_OFFLOAD
4052 /*
4053  * Idempotent.
4054  */
4055 static int
4056 alloc_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq, int idx,
4057     int intr_idx, int maxp)
4058 {
4059 	int rc;
4060 	struct adapter *sc = vi->adapter;
4061 	struct sysctl_oid *oid;
4062 	char name[16];
4063 
4064 	if (!(ofld_rxq->iq.flags & IQ_SW_ALLOCATED)) {
4065 		MPASS(!(ofld_rxq->iq.flags & IQ_HW_ALLOCATED));
4066 
4067 		snprintf(name, sizeof(name), "%d", idx);
4068 		oid = SYSCTL_ADD_NODE(&vi->ctx,
4069 		    SYSCTL_CHILDREN(vi->ofld_rxq_oid), OID_AUTO, name,
4070 		    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "offload rx queue");
4071 
4072 		init_iq(&ofld_rxq->iq, sc, vi->ofld_tmr_idx, vi->ofld_pktc_idx,
4073 		    vi->qsize_rxq, intr_idx, 0);
4074 		snprintf(name, sizeof(name), "%s ofld_rxq%d-fl",
4075 		    device_get_nameunit(vi->dev), idx);
4076 		init_fl(sc, &ofld_rxq->fl, vi->qsize_rxq / 8, maxp, name);
4077 		rc = alloc_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl, &vi->ctx,
4078 		    oid);
4079 		if (rc != 0) {
4080 			CH_ERR(vi, "failed to allocate ofld_rxq%d: %d\n", idx,
4081 			    rc);
4082 			sysctl_remove_oid(oid, 1, 1);
4083 			return (rc);
4084 		}
4085 		MPASS(ofld_rxq->iq.flags & IQ_SW_ALLOCATED);
4086 		ofld_rxq->rx_iscsi_ddp_setup_ok = counter_u64_alloc(M_WAITOK);
4087 		ofld_rxq->rx_iscsi_ddp_setup_error =
4088 		    counter_u64_alloc(M_WAITOK);
4089 		add_ofld_rxq_sysctls(&vi->ctx, oid, ofld_rxq);
4090 	}
4091 
4092 	if (!(ofld_rxq->iq.flags & IQ_HW_ALLOCATED)) {
4093 		MPASS(ofld_rxq->iq.flags & IQ_SW_ALLOCATED);
4094 		rc = alloc_iq_fl_hwq(vi, &ofld_rxq->iq, &ofld_rxq->fl);
4095 		if (rc != 0) {
4096 			CH_ERR(vi, "failed to create hw ofld_rxq%d: %d\n", idx,
4097 			    rc);
4098 			return (rc);
4099 		}
4100 		MPASS(ofld_rxq->iq.flags & IQ_HW_ALLOCATED);
4101 	}
4102 	return (rc);
4103 }
4104 
4105 /*
4106  * Idempotent.
4107  */
4108 static void
4109 free_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq)
4110 {
4111 	if (ofld_rxq->iq.flags & IQ_HW_ALLOCATED) {
4112 		MPASS(ofld_rxq->iq.flags & IQ_SW_ALLOCATED);
4113 		free_iq_fl_hwq(vi->adapter, &ofld_rxq->iq, &ofld_rxq->fl);
4114 		MPASS(!(ofld_rxq->iq.flags & IQ_HW_ALLOCATED));
4115 	}
4116 
4117 	if (ofld_rxq->iq.flags & IQ_SW_ALLOCATED) {
4118 		MPASS(!(ofld_rxq->iq.flags & IQ_HW_ALLOCATED));
4119 		free_iq_fl(vi->adapter, &ofld_rxq->iq, &ofld_rxq->fl);
4120 		MPASS(!(ofld_rxq->iq.flags & IQ_SW_ALLOCATED));
4121 		counter_u64_free(ofld_rxq->rx_iscsi_ddp_setup_ok);
4122 		counter_u64_free(ofld_rxq->rx_iscsi_ddp_setup_error);
4123 		bzero(ofld_rxq, sizeof(*ofld_rxq));
4124 	}
4125 }
4126 
4127 static void
4128 add_ofld_rxq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid,
4129     struct sge_ofld_rxq *ofld_rxq)
4130 {
4131 	struct sysctl_oid_list *children;
4132 
4133 	if (ctx == NULL || oid == NULL)
4134 		return;
4135 
4136 	children = SYSCTL_CHILDREN(oid);
4137 	SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
4138 	    "rx_toe_tls_records", CTLFLAG_RD, &ofld_rxq->rx_toe_tls_records,
4139 	    "# of TOE TLS records received");
4140 	SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
4141 	    "rx_toe_tls_octets", CTLFLAG_RD, &ofld_rxq->rx_toe_tls_octets,
4142 	    "# of payload octets in received TOE TLS records");
4143 
4144 	oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "iscsi",
4145 	    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TOE iSCSI statistics");
4146 	children = SYSCTL_CHILDREN(oid);
4147 
4148 	SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "ddp_setup_ok",
4149 	    CTLFLAG_RD, &ofld_rxq->rx_iscsi_ddp_setup_ok,
4150 	    "# of times DDP buffer was setup successfully.");
4151 	SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "ddp_setup_error",
4152 	    CTLFLAG_RD, &ofld_rxq->rx_iscsi_ddp_setup_error,
4153 	    "# of times DDP buffer setup failed.");
4154 	SYSCTL_ADD_U64(ctx, children, OID_AUTO, "ddp_octets",
4155 	    CTLFLAG_RD, &ofld_rxq->rx_iscsi_ddp_octets, 0,
4156 	    "# of octets placed directly");
4157 	SYSCTL_ADD_U64(ctx, children, OID_AUTO, "ddp_pdus",
4158 	    CTLFLAG_RD, &ofld_rxq->rx_iscsi_ddp_pdus, 0,
4159 	    "# of PDUs with data placed directly.");
4160 	SYSCTL_ADD_U64(ctx, children, OID_AUTO, "fl_octets",
4161 	    CTLFLAG_RD, &ofld_rxq->rx_iscsi_fl_octets, 0,
4162 	    "# of data octets delivered in freelist");
4163 	SYSCTL_ADD_U64(ctx, children, OID_AUTO, "fl_pdus",
4164 	    CTLFLAG_RD, &ofld_rxq->rx_iscsi_fl_pdus, 0,
4165 	    "# of PDUs with data delivered in freelist");
4166 }
4167 #endif
4168 
4169 /*
4170  * Returns a reasonable automatic cidx flush threshold for a given queue size.
4171  */
4172 static u_int
4173 qsize_to_fthresh(int qsize)
4174 {
4175 	u_int fthresh;
4176 
4177 	while (!powerof2(qsize))
4178 		qsize++;
4179 	fthresh = ilog2(qsize);
4180 	if (fthresh > X_CIDXFLUSHTHRESH_128)
4181 		fthresh = X_CIDXFLUSHTHRESH_128;
4182 
4183 	return (fthresh);
4184 }
4185 
4186 static int
4187 ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq)
4188 {
4189 	int rc, cntxt_id;
4190 	struct fw_eq_ctrl_cmd c;
4191 	int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
4192 
4193 	bzero(&c, sizeof(c));
4194 
4195 	c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | F_FW_CMD_REQUEST |
4196 	    F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_CTRL_CMD_PFN(sc->pf) |
4197 	    V_FW_EQ_CTRL_CMD_VFN(0));
4198 	c.alloc_to_len16 = htobe32(F_FW_EQ_CTRL_CMD_ALLOC |
4199 	    F_FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c));
4200 	c.cmpliqid_eqid = htonl(V_FW_EQ_CTRL_CMD_CMPLIQID(eq->iqid));
4201 	c.physeqid_pkd = htobe32(0);
4202 	c.fetchszm_to_iqid =
4203 	    htobe32(V_FW_EQ_CTRL_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) |
4204 		V_FW_EQ_CTRL_CMD_PCIECHN(eq->tx_chan) |
4205 		F_FW_EQ_CTRL_CMD_FETCHRO | V_FW_EQ_CTRL_CMD_IQID(eq->iqid));
4206 	c.dcaen_to_eqsize =
4207 	    htobe32(V_FW_EQ_CTRL_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ?
4208 		X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) |
4209 		V_FW_EQ_CTRL_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
4210 		V_FW_EQ_CTRL_CMD_CIDXFTHRESH(qsize_to_fthresh(qsize)) |
4211 		V_FW_EQ_CTRL_CMD_EQSIZE(qsize));
4212 	c.eqaddr = htobe64(eq->ba);
4213 
4214 	rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
4215 	if (rc != 0) {
4216 		CH_ERR(sc, "failed to create hw ctrlq for tx_chan %d: %d\n",
4217 		    eq->tx_chan, rc);
4218 		return (rc);
4219 	}
4220 
4221 	eq->cntxt_id = G_FW_EQ_CTRL_CMD_EQID(be32toh(c.cmpliqid_eqid));
4222 	eq->abs_id = G_FW_EQ_CTRL_CMD_PHYSEQID(be32toh(c.physeqid_pkd));
4223 	cntxt_id = eq->cntxt_id - sc->sge.eq_start;
4224 	if (cntxt_id >= sc->sge.eqmap_sz)
4225 	    panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
4226 		cntxt_id, sc->sge.eqmap_sz - 1);
4227 	sc->sge.eqmap[cntxt_id] = eq;
4228 
4229 	return (rc);
4230 }
4231 
4232 static int
4233 eth_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq)
4234 {
4235 	int rc, cntxt_id;
4236 	struct fw_eq_eth_cmd c;
4237 	int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
4238 
4239 	bzero(&c, sizeof(c));
4240 
4241 	c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST |
4242 	    F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) |
4243 	    V_FW_EQ_ETH_CMD_VFN(0));
4244 	c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC |
4245 	    F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c));
4246 	c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE |
4247 	    F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(vi->viid));
4248 	c.fetchszm_to_iqid =
4249 	    htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) |
4250 		V_FW_EQ_ETH_CMD_PCIECHN(eq->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO |
4251 		V_FW_EQ_ETH_CMD_IQID(eq->iqid));
4252 	c.dcaen_to_eqsize =
4253 	    htobe32(V_FW_EQ_ETH_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ?
4254 		X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) |
4255 		V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
4256 		V_FW_EQ_ETH_CMD_EQSIZE(qsize));
4257 	c.eqaddr = htobe64(eq->ba);
4258 
4259 	rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
4260 	if (rc != 0) {
4261 		device_printf(vi->dev,
4262 		    "failed to create Ethernet egress queue: %d\n", rc);
4263 		return (rc);
4264 	}
4265 
4266 	eq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd));
4267 	eq->abs_id = G_FW_EQ_ETH_CMD_PHYSEQID(be32toh(c.physeqid_pkd));
4268 	cntxt_id = eq->cntxt_id - sc->sge.eq_start;
4269 	if (cntxt_id >= sc->sge.eqmap_sz)
4270 	    panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
4271 		cntxt_id, sc->sge.eqmap_sz - 1);
4272 	sc->sge.eqmap[cntxt_id] = eq;
4273 
4274 	return (rc);
4275 }
4276 
4277 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
4278 static int
4279 ofld_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq)
4280 {
4281 	int rc, cntxt_id;
4282 	struct fw_eq_ofld_cmd c;
4283 	int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
4284 
4285 	bzero(&c, sizeof(c));
4286 
4287 	c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | F_FW_CMD_REQUEST |
4288 	    F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_OFLD_CMD_PFN(sc->pf) |
4289 	    V_FW_EQ_OFLD_CMD_VFN(0));
4290 	c.alloc_to_len16 = htonl(F_FW_EQ_OFLD_CMD_ALLOC |
4291 	    F_FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c));
4292 	c.fetchszm_to_iqid =
4293 		htonl(V_FW_EQ_OFLD_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) |
4294 		    V_FW_EQ_OFLD_CMD_PCIECHN(eq->tx_chan) |
4295 		    F_FW_EQ_OFLD_CMD_FETCHRO | V_FW_EQ_OFLD_CMD_IQID(eq->iqid));
4296 	c.dcaen_to_eqsize =
4297 	    htobe32(V_FW_EQ_OFLD_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ?
4298 		X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) |
4299 		V_FW_EQ_OFLD_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
4300 		V_FW_EQ_OFLD_CMD_CIDXFTHRESH(qsize_to_fthresh(qsize)) |
4301 		V_FW_EQ_OFLD_CMD_EQSIZE(qsize));
4302 	c.eqaddr = htobe64(eq->ba);
4303 
4304 	rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
4305 	if (rc != 0) {
4306 		device_printf(vi->dev,
4307 		    "failed to create egress queue for TCP offload: %d\n", rc);
4308 		return (rc);
4309 	}
4310 
4311 	eq->cntxt_id = G_FW_EQ_OFLD_CMD_EQID(be32toh(c.eqid_pkd));
4312 	eq->abs_id = G_FW_EQ_OFLD_CMD_PHYSEQID(be32toh(c.physeqid_pkd));
4313 	cntxt_id = eq->cntxt_id - sc->sge.eq_start;
4314 	if (cntxt_id >= sc->sge.eqmap_sz)
4315 	    panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
4316 		cntxt_id, sc->sge.eqmap_sz - 1);
4317 	sc->sge.eqmap[cntxt_id] = eq;
4318 
4319 	return (rc);
4320 }
4321 #endif
4322 
4323 /* SW only */
4324 static int
4325 alloc_eq(struct adapter *sc, struct sge_eq *eq, struct sysctl_ctx_list *ctx,
4326     struct sysctl_oid *oid)
4327 {
4328 	int rc, qsize;
4329 	size_t len;
4330 
4331 	MPASS(!(eq->flags & EQ_SW_ALLOCATED));
4332 
4333 	qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
4334 	len = qsize * EQ_ESIZE;
4335 	rc = alloc_ring(sc, len, &eq->desc_tag, &eq->desc_map, &eq->ba,
4336 	    (void **)&eq->desc);
4337 	if (rc)
4338 		return (rc);
4339 	if (ctx != NULL && oid != NULL)
4340 		add_eq_sysctls(sc, ctx, oid, eq);
4341 	eq->flags |= EQ_SW_ALLOCATED;
4342 
4343 	return (0);
4344 }
4345 
4346 /* SW only */
4347 static void
4348 free_eq(struct adapter *sc, struct sge_eq *eq)
4349 {
4350 	MPASS(eq->flags & EQ_SW_ALLOCATED);
4351 	if (eq->type == EQ_ETH)
4352 		MPASS(eq->pidx == eq->cidx);
4353 
4354 	free_ring(sc, eq->desc_tag, eq->desc_map, eq->ba, eq->desc);
4355 	mtx_destroy(&eq->eq_lock);
4356 	bzero(eq, sizeof(*eq));
4357 }
4358 
4359 static void
4360 add_eq_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx,
4361     struct sysctl_oid *oid, struct sge_eq *eq)
4362 {
4363 	struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
4364 
4365 	SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, &eq->ba,
4366 	    "bus address of descriptor ring");
4367 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
4368 	    eq->sidx * EQ_ESIZE + sc->params.sge.spg_len,
4369 	    "desc ring size in bytes");
4370 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "abs_id", CTLFLAG_RD,
4371 	    &eq->abs_id, 0, "absolute id of the queue");
4372 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
4373 	    &eq->cntxt_id, 0, "SGE context id of the queue");
4374 	SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &eq->cidx,
4375 	    0, "consumer index");
4376 	SYSCTL_ADD_U16(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &eq->pidx,
4377 	    0, "producer index");
4378 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL,
4379 	    eq->sidx, "status page index");
4380 }
4381 
4382 static int
4383 alloc_eq_hwq(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq)
4384 {
4385 	int rc;
4386 
4387 	MPASS(!(eq->flags & EQ_HW_ALLOCATED));
4388 
4389 	eq->iqid = eq->iq->cntxt_id;
4390 	eq->pidx = eq->cidx = eq->dbidx = 0;
4391 	/* Note that equeqidx is not used with sge_wrq (OFLD/CTRL) queues. */
4392 	eq->equeqidx = 0;
4393 	eq->doorbells = sc->doorbells;
4394 	bzero(eq->desc, eq->sidx * EQ_ESIZE + sc->params.sge.spg_len);
4395 
4396 	switch (eq->type) {
4397 	case EQ_CTRL:
4398 		rc = ctrl_eq_alloc(sc, eq);
4399 		break;
4400 
4401 	case EQ_ETH:
4402 		rc = eth_eq_alloc(sc, vi, eq);
4403 		break;
4404 
4405 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
4406 	case EQ_OFLD:
4407 		rc = ofld_eq_alloc(sc, vi, eq);
4408 		break;
4409 #endif
4410 
4411 	default:
4412 		panic("%s: invalid eq type %d.", __func__, eq->type);
4413 	}
4414 	if (rc != 0) {
4415 		CH_ERR(sc, "failed to allocate egress queue(%d): %d\n",
4416 		    eq->type, rc);
4417 		return (rc);
4418 	}
4419 
4420 	if (isset(&eq->doorbells, DOORBELL_UDB) ||
4421 	    isset(&eq->doorbells, DOORBELL_UDBWC) ||
4422 	    isset(&eq->doorbells, DOORBELL_WCWR)) {
4423 		uint32_t s_qpp = sc->params.sge.eq_s_qpp;
4424 		uint32_t mask = (1 << s_qpp) - 1;
4425 		volatile uint8_t *udb;
4426 
4427 		udb = sc->udbs_base + UDBS_DB_OFFSET;
4428 		udb += (eq->cntxt_id >> s_qpp) << PAGE_SHIFT;	/* pg offset */
4429 		eq->udb_qid = eq->cntxt_id & mask;		/* id in page */
4430 		if (eq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE)
4431 	    		clrbit(&eq->doorbells, DOORBELL_WCWR);
4432 		else {
4433 			udb += eq->udb_qid << UDBS_SEG_SHIFT;	/* seg offset */
4434 			eq->udb_qid = 0;
4435 		}
4436 		eq->udb = (volatile void *)udb;
4437 	}
4438 
4439 	eq->flags |= EQ_HW_ALLOCATED;
4440 	return (0);
4441 }
4442 
4443 static int
4444 free_eq_hwq(struct adapter *sc, struct vi_info *vi __unused, struct sge_eq *eq)
4445 {
4446 	int rc;
4447 
4448 	MPASS(eq->flags & EQ_HW_ALLOCATED);
4449 
4450 	switch (eq->type) {
4451 	case EQ_CTRL:
4452 		rc = -t4_ctrl_eq_free(sc, sc->mbox, sc->pf, 0, eq->cntxt_id);
4453 		break;
4454 	case EQ_ETH:
4455 		rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0, eq->cntxt_id);
4456 		break;
4457 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
4458 	case EQ_OFLD:
4459 		rc = -t4_ofld_eq_free(sc, sc->mbox, sc->pf, 0, eq->cntxt_id);
4460 		break;
4461 #endif
4462 	default:
4463 		panic("%s: invalid eq type %d.", __func__, eq->type);
4464 	}
4465 	if (rc != 0) {
4466 		CH_ERR(sc, "failed to free eq (type %d): %d\n", eq->type, rc);
4467 		return (rc);
4468 	}
4469 	eq->flags &= ~EQ_HW_ALLOCATED;
4470 
4471 	return (0);
4472 }
4473 
4474 static int
4475 alloc_wrq(struct adapter *sc, struct vi_info *vi, struct sge_wrq *wrq,
4476     struct sysctl_ctx_list *ctx, struct sysctl_oid *oid)
4477 {
4478 	struct sge_eq *eq = &wrq->eq;
4479 	int rc;
4480 
4481 	MPASS(!(eq->flags & EQ_SW_ALLOCATED));
4482 
4483 	rc = alloc_eq(sc, eq, ctx, oid);
4484 	if (rc)
4485 		return (rc);
4486 	MPASS(eq->flags & EQ_SW_ALLOCATED);
4487 	/* Can't fail after this. */
4488 
4489 	wrq->adapter = sc;
4490 	TASK_INIT(&wrq->wrq_tx_task, 0, wrq_tx_drain, wrq);
4491 	TAILQ_INIT(&wrq->incomplete_wrs);
4492 	STAILQ_INIT(&wrq->wr_list);
4493 	wrq->nwr_pending = 0;
4494 	wrq->ndesc_needed = 0;
4495 	add_wrq_sysctls(ctx, oid, wrq);
4496 
4497 	return (0);
4498 }
4499 
4500 static void
4501 free_wrq(struct adapter *sc, struct sge_wrq *wrq)
4502 {
4503 	free_eq(sc, &wrq->eq);
4504 	MPASS(wrq->nwr_pending == 0);
4505 	MPASS(TAILQ_EMPTY(&wrq->incomplete_wrs));
4506 	MPASS(STAILQ_EMPTY(&wrq->wr_list));
4507 	bzero(wrq, sizeof(*wrq));
4508 }
4509 
4510 static void
4511 add_wrq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid,
4512     struct sge_wrq *wrq)
4513 {
4514 	struct sysctl_oid_list *children;
4515 
4516 	if (ctx == NULL || oid == NULL)
4517 		return;
4518 
4519 	children = SYSCTL_CHILDREN(oid);
4520 	SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_direct", CTLFLAG_RD,
4521 	    &wrq->tx_wrs_direct, "# of work requests (direct)");
4522 	SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_copied", CTLFLAG_RD,
4523 	    &wrq->tx_wrs_copied, "# of work requests (copied)");
4524 	SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_sspace", CTLFLAG_RD,
4525 	    &wrq->tx_wrs_ss, "# of work requests (copied from scratch space)");
4526 }
4527 
4528 /*
4529  * Idempotent.
4530  */
4531 static int
4532 alloc_txq(struct vi_info *vi, struct sge_txq *txq, int idx)
4533 {
4534 	int rc, iqidx;
4535 	struct port_info *pi = vi->pi;
4536 	struct adapter *sc = vi->adapter;
4537 	struct sge_eq *eq = &txq->eq;
4538 	struct txpkts *txp;
4539 	char name[16];
4540 	struct sysctl_oid *oid;
4541 
4542 	if (!(eq->flags & EQ_SW_ALLOCATED)) {
4543 		MPASS(!(eq->flags & EQ_HW_ALLOCATED));
4544 
4545 		snprintf(name, sizeof(name), "%d", idx);
4546 		oid = SYSCTL_ADD_NODE(&vi->ctx, SYSCTL_CHILDREN(vi->txq_oid),
4547 		    OID_AUTO, name, CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
4548 		    "tx queue");
4549 
4550 		iqidx = vi->first_rxq + (idx % vi->nrxq);
4551 		snprintf(name, sizeof(name), "%s txq%d",
4552 		    device_get_nameunit(vi->dev), idx);
4553 		init_eq(sc, &txq->eq, EQ_ETH, vi->qsize_txq, pi->tx_chan,
4554 		    &sc->sge.rxq[iqidx].iq, name);
4555 
4556 		rc = mp_ring_alloc(&txq->r, eq->sidx, txq, eth_tx,
4557 		    can_resume_eth_tx, M_CXGBE, &eq->eq_lock, M_WAITOK);
4558 		if (rc != 0) {
4559 			CH_ERR(vi, "failed to allocate mp_ring for txq%d: %d\n",
4560 			    idx, rc);
4561 failed:
4562 			sysctl_remove_oid(oid, 1, 1);
4563 			return (rc);
4564 		}
4565 
4566 		rc = alloc_eq(sc, eq, &vi->ctx, oid);
4567 		if (rc) {
4568 			CH_ERR(vi, "failed to allocate txq%d: %d\n", idx, rc);
4569 			mp_ring_free(txq->r);
4570 			goto failed;
4571 		}
4572 		MPASS(eq->flags & EQ_SW_ALLOCATED);
4573 		/* Can't fail after this point. */
4574 
4575 		TASK_INIT(&txq->tx_reclaim_task, 0, tx_reclaim, eq);
4576 		txq->ifp = vi->ifp;
4577 		txq->gl = sglist_alloc(TX_SGL_SEGS, M_WAITOK);
4578 		txq->sdesc = malloc(eq->sidx * sizeof(struct tx_sdesc), M_CXGBE,
4579 		    M_ZERO | M_WAITOK);
4580 
4581 		add_txq_sysctls(vi, &vi->ctx, oid, txq);
4582 	}
4583 
4584 	if (!(eq->flags & EQ_HW_ALLOCATED)) {
4585 		MPASS(eq->flags & EQ_SW_ALLOCATED);
4586 		rc = alloc_eq_hwq(sc, vi, eq);
4587 		if (rc != 0) {
4588 			CH_ERR(vi, "failed to create hw txq%d: %d\n", idx, rc);
4589 			return (rc);
4590 		}
4591 		MPASS(eq->flags & EQ_HW_ALLOCATED);
4592 		/* Can't fail after this point. */
4593 
4594 		if (idx == 0)
4595 			sc->sge.eq_base = eq->abs_id - eq->cntxt_id;
4596 		else
4597 			KASSERT(eq->cntxt_id + sc->sge.eq_base == eq->abs_id,
4598 			    ("eq_base mismatch"));
4599 		KASSERT(sc->sge.eq_base == 0 || sc->flags & IS_VF,
4600 		    ("PF with non-zero eq_base"));
4601 
4602 		txp = &txq->txp;
4603 		MPASS(nitems(txp->mb) >= sc->params.max_pkts_per_eth_tx_pkts_wr);
4604 		txq->txp.max_npkt = min(nitems(txp->mb),
4605 		    sc->params.max_pkts_per_eth_tx_pkts_wr);
4606 		if (vi->flags & TX_USES_VM_WR && !(sc->flags & IS_VF))
4607 			txq->txp.max_npkt--;
4608 
4609 		if (vi->flags & TX_USES_VM_WR)
4610 			txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) |
4611 			    V_TXPKT_INTF(pi->tx_chan));
4612 		else
4613 			txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) |
4614 			    V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(sc->pf) |
4615 			    V_TXPKT_VF(vi->vin) | V_TXPKT_VF_VLD(vi->vfvld));
4616 
4617 		txq->tc_idx = -1;
4618 	}
4619 
4620 	return (0);
4621 }
4622 
4623 /*
4624  * Idempotent.
4625  */
4626 static void
4627 free_txq(struct vi_info *vi, struct sge_txq *txq)
4628 {
4629 	struct adapter *sc = vi->adapter;
4630 	struct sge_eq *eq = &txq->eq;
4631 
4632 	if (eq->flags & EQ_HW_ALLOCATED) {
4633 		MPASS(eq->flags & EQ_SW_ALLOCATED);
4634 		free_eq_hwq(sc, NULL, eq);
4635 		MPASS(!(eq->flags & EQ_HW_ALLOCATED));
4636 	}
4637 
4638 	if (eq->flags & EQ_SW_ALLOCATED) {
4639 		MPASS(!(eq->flags & EQ_HW_ALLOCATED));
4640 		sglist_free(txq->gl);
4641 		free(txq->sdesc, M_CXGBE);
4642 		mp_ring_free(txq->r);
4643 		free_eq(sc, eq);
4644 		MPASS(!(eq->flags & EQ_SW_ALLOCATED));
4645 		bzero(txq, sizeof(*txq));
4646 	}
4647 }
4648 
4649 static void
4650 add_txq_sysctls(struct vi_info *vi, struct sysctl_ctx_list *ctx,
4651     struct sysctl_oid *oid, struct sge_txq *txq)
4652 {
4653 	struct adapter *sc;
4654 	struct sysctl_oid_list *children;
4655 
4656 	if (ctx == NULL || oid == NULL)
4657 		return;
4658 
4659 	sc = vi->adapter;
4660 	children = SYSCTL_CHILDREN(oid);
4661 
4662 	mp_ring_sysctls(txq->r, ctx, children);
4663 
4664 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tc",
4665 	    CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, txq - sc->sge.txq,
4666 	    sysctl_tc, "I", "traffic class (-1 means none)");
4667 
4668 	SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txcsum", CTLFLAG_RD,
4669 	    &txq->txcsum, "# of times hardware assisted with checksum");
4670 	SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "vlan_insertion", CTLFLAG_RD,
4671 	    &txq->vlan_insertion, "# of times hardware inserted 802.1Q tag");
4672 	SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tso_wrs", CTLFLAG_RD,
4673 	    &txq->tso_wrs, "# of TSO work requests");
4674 	SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "imm_wrs", CTLFLAG_RD,
4675 	    &txq->imm_wrs, "# of work requests with immediate data");
4676 	SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "sgl_wrs", CTLFLAG_RD,
4677 	    &txq->sgl_wrs, "# of work requests with direct SGL");
4678 	SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkt_wrs", CTLFLAG_RD,
4679 	    &txq->txpkt_wrs, "# of txpkt work requests (one pkt/WR)");
4680 	SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkts0_wrs", CTLFLAG_RD,
4681 	    &txq->txpkts0_wrs, "# of txpkts (type 0) work requests");
4682 	SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkts1_wrs", CTLFLAG_RD,
4683 	    &txq->txpkts1_wrs, "# of txpkts (type 1) work requests");
4684 	SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkts0_pkts", CTLFLAG_RD,
4685 	    &txq->txpkts0_pkts,
4686 	    "# of frames tx'd using type0 txpkts work requests");
4687 	SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkts1_pkts", CTLFLAG_RD,
4688 	    &txq->txpkts1_pkts,
4689 	    "# of frames tx'd using type1 txpkts work requests");
4690 	SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkts_flush", CTLFLAG_RD,
4691 	    &txq->txpkts_flush,
4692 	    "# of times txpkts had to be flushed out by an egress-update");
4693 	SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "raw_wrs", CTLFLAG_RD,
4694 	    &txq->raw_wrs, "# of raw work requests (non-packets)");
4695 	SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "vxlan_tso_wrs", CTLFLAG_RD,
4696 	    &txq->vxlan_tso_wrs, "# of VXLAN TSO work requests");
4697 	SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "vxlan_txcsum", CTLFLAG_RD,
4698 	    &txq->vxlan_txcsum,
4699 	    "# of times hardware assisted with inner checksums (VXLAN)");
4700 
4701 #ifdef KERN_TLS
4702 	if (is_ktls(sc)) {
4703 		SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_records",
4704 		    CTLFLAG_RD, &txq->kern_tls_records,
4705 		    "# of NIC TLS records transmitted");
4706 		SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_short",
4707 		    CTLFLAG_RD, &txq->kern_tls_short,
4708 		    "# of short NIC TLS records transmitted");
4709 		SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_partial",
4710 		    CTLFLAG_RD, &txq->kern_tls_partial,
4711 		    "# of partial NIC TLS records transmitted");
4712 		SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_full",
4713 		    CTLFLAG_RD, &txq->kern_tls_full,
4714 		    "# of full NIC TLS records transmitted");
4715 		SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_octets",
4716 		    CTLFLAG_RD, &txq->kern_tls_octets,
4717 		    "# of payload octets in transmitted NIC TLS records");
4718 		SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_waste",
4719 		    CTLFLAG_RD, &txq->kern_tls_waste,
4720 		    "# of octets DMAd but not transmitted in NIC TLS records");
4721 		SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_options",
4722 		    CTLFLAG_RD, &txq->kern_tls_options,
4723 		    "# of NIC TLS options-only packets transmitted");
4724 		SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_header",
4725 		    CTLFLAG_RD, &txq->kern_tls_header,
4726 		    "# of NIC TLS header-only packets transmitted");
4727 		SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_fin",
4728 		    CTLFLAG_RD, &txq->kern_tls_fin,
4729 		    "# of NIC TLS FIN-only packets transmitted");
4730 		SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_fin_short",
4731 		    CTLFLAG_RD, &txq->kern_tls_fin_short,
4732 		    "# of NIC TLS padded FIN packets on short TLS records");
4733 		SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_cbc",
4734 		    CTLFLAG_RD, &txq->kern_tls_cbc,
4735 		    "# of NIC TLS sessions using AES-CBC");
4736 		SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_gcm",
4737 		    CTLFLAG_RD, &txq->kern_tls_gcm,
4738 		    "# of NIC TLS sessions using AES-GCM");
4739 	}
4740 #endif
4741 }
4742 
4743 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
4744 /*
4745  * Idempotent.
4746  */
4747 static int
4748 alloc_ofld_txq(struct vi_info *vi, struct sge_ofld_txq *ofld_txq, int idx)
4749 {
4750 	struct sysctl_oid *oid;
4751 	struct port_info *pi = vi->pi;
4752 	struct adapter *sc = vi->adapter;
4753 	struct sge_eq *eq = &ofld_txq->wrq.eq;
4754 	int rc, iqidx;
4755 	char name[16];
4756 
4757 	MPASS(idx >= 0);
4758 	MPASS(idx < vi->nofldtxq);
4759 
4760 	if (!(eq->flags & EQ_SW_ALLOCATED)) {
4761 		snprintf(name, sizeof(name), "%d", idx);
4762 		oid = SYSCTL_ADD_NODE(&vi->ctx,
4763 		    SYSCTL_CHILDREN(vi->ofld_txq_oid), OID_AUTO, name,
4764 		    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "offload tx queue");
4765 
4766 		snprintf(name, sizeof(name), "%s ofld_txq%d",
4767 		    device_get_nameunit(vi->dev), idx);
4768 		if (vi->nofldrxq > 0) {
4769 			iqidx = vi->first_ofld_rxq + (idx % vi->nofldrxq);
4770 			init_eq(sc, eq, EQ_OFLD, vi->qsize_txq, pi->tx_chan,
4771 			    &sc->sge.ofld_rxq[iqidx].iq, name);
4772 		} else {
4773 			iqidx = vi->first_rxq + (idx % vi->nrxq);
4774 			init_eq(sc, eq, EQ_OFLD, vi->qsize_txq, pi->tx_chan,
4775 			    &sc->sge.rxq[iqidx].iq, name);
4776 		}
4777 
4778 		rc = alloc_wrq(sc, vi, &ofld_txq->wrq, &vi->ctx, oid);
4779 		if (rc != 0) {
4780 			CH_ERR(vi, "failed to allocate ofld_txq%d: %d\n", idx,
4781 			    rc);
4782 			sysctl_remove_oid(oid, 1, 1);
4783 			return (rc);
4784 		}
4785 		MPASS(eq->flags & EQ_SW_ALLOCATED);
4786 		/* Can't fail after this point. */
4787 
4788 		ofld_txq->tx_iscsi_pdus = counter_u64_alloc(M_WAITOK);
4789 		ofld_txq->tx_iscsi_octets = counter_u64_alloc(M_WAITOK);
4790 		ofld_txq->tx_toe_tls_records = counter_u64_alloc(M_WAITOK);
4791 		ofld_txq->tx_toe_tls_octets = counter_u64_alloc(M_WAITOK);
4792 		add_ofld_txq_sysctls(&vi->ctx, oid, ofld_txq);
4793 	}
4794 
4795 	if (!(eq->flags & EQ_HW_ALLOCATED)) {
4796 		rc = alloc_eq_hwq(sc, vi, eq);
4797 		if (rc != 0) {
4798 			CH_ERR(vi, "failed to create hw ofld_txq%d: %d\n", idx,
4799 			    rc);
4800 			return (rc);
4801 		}
4802 		MPASS(eq->flags & EQ_HW_ALLOCATED);
4803 	}
4804 
4805 	return (0);
4806 }
4807 
4808 /*
4809  * Idempotent.
4810  */
4811 static void
4812 free_ofld_txq(struct vi_info *vi, struct sge_ofld_txq *ofld_txq)
4813 {
4814 	struct adapter *sc = vi->adapter;
4815 	struct sge_eq *eq = &ofld_txq->wrq.eq;
4816 
4817 	if (eq->flags & EQ_HW_ALLOCATED) {
4818 		MPASS(eq->flags & EQ_SW_ALLOCATED);
4819 		free_eq_hwq(sc, NULL, eq);
4820 		MPASS(!(eq->flags & EQ_HW_ALLOCATED));
4821 	}
4822 
4823 	if (eq->flags & EQ_SW_ALLOCATED) {
4824 		MPASS(!(eq->flags & EQ_HW_ALLOCATED));
4825 		counter_u64_free(ofld_txq->tx_iscsi_pdus);
4826 		counter_u64_free(ofld_txq->tx_iscsi_octets);
4827 		counter_u64_free(ofld_txq->tx_toe_tls_records);
4828 		counter_u64_free(ofld_txq->tx_toe_tls_octets);
4829 		free_wrq(sc, &ofld_txq->wrq);
4830 		MPASS(!(eq->flags & EQ_SW_ALLOCATED));
4831 		bzero(ofld_txq, sizeof(*ofld_txq));
4832 	}
4833 }
4834 
4835 static void
4836 add_ofld_txq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid,
4837     struct sge_ofld_txq *ofld_txq)
4838 {
4839 	struct sysctl_oid_list *children;
4840 
4841 	if (ctx == NULL || oid == NULL)
4842 		return;
4843 
4844 	children = SYSCTL_CHILDREN(oid);
4845 	SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_iscsi_pdus",
4846 	    CTLFLAG_RD, &ofld_txq->tx_iscsi_pdus,
4847 	    "# of iSCSI PDUs transmitted");
4848 	SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_iscsi_octets",
4849 	    CTLFLAG_RD, &ofld_txq->tx_iscsi_octets,
4850 	    "# of payload octets in transmitted iSCSI PDUs");
4851 	SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_toe_tls_records",
4852 	    CTLFLAG_RD, &ofld_txq->tx_toe_tls_records,
4853 	    "# of TOE TLS records transmitted");
4854 	SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_toe_tls_octets",
4855 	    CTLFLAG_RD, &ofld_txq->tx_toe_tls_octets,
4856 	    "# of payload octets in transmitted TOE TLS records");
4857 }
4858 #endif
4859 
4860 static void
4861 oneseg_dma_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error)
4862 {
4863 	bus_addr_t *ba = arg;
4864 
4865 	KASSERT(nseg == 1,
4866 	    ("%s meant for single segment mappings only.", __func__));
4867 
4868 	*ba = error ? 0 : segs->ds_addr;
4869 }
4870 
4871 static inline void
4872 ring_fl_db(struct adapter *sc, struct sge_fl *fl)
4873 {
4874 	uint32_t n, v;
4875 
4876 	n = IDXDIFF(fl->pidx >> 3, fl->dbidx, fl->sidx);
4877 	MPASS(n > 0);
4878 
4879 	wmb();
4880 	v = fl->dbval | V_PIDX(n);
4881 	if (fl->udb)
4882 		*fl->udb = htole32(v);
4883 	else
4884 		t4_write_reg(sc, sc->sge_kdoorbell_reg, v);
4885 	IDXINCR(fl->dbidx, n, fl->sidx);
4886 }
4887 
4888 /*
4889  * Fills up the freelist by allocating up to 'n' buffers.  Buffers that are
4890  * recycled do not count towards this allocation budget.
4891  *
4892  * Returns non-zero to indicate that this freelist should be added to the list
4893  * of starving freelists.
4894  */
4895 static int
4896 refill_fl(struct adapter *sc, struct sge_fl *fl, int n)
4897 {
4898 	__be64 *d;
4899 	struct fl_sdesc *sd;
4900 	uintptr_t pa;
4901 	caddr_t cl;
4902 	struct rx_buf_info *rxb;
4903 	struct cluster_metadata *clm;
4904 	uint16_t max_pidx, zidx = fl->zidx;
4905 	uint16_t hw_cidx = fl->hw_cidx;		/* stable snapshot */
4906 
4907 	FL_LOCK_ASSERT_OWNED(fl);
4908 
4909 	/*
4910 	 * We always stop at the beginning of the hardware descriptor that's just
4911 	 * before the one with the hw cidx.  This is to avoid hw pidx = hw cidx,
4912 	 * which would mean an empty freelist to the chip.
4913 	 */
4914 	max_pidx = __predict_false(hw_cidx == 0) ? fl->sidx - 1 : hw_cidx - 1;
4915 	if (fl->pidx == max_pidx * 8)
4916 		return (0);
4917 
4918 	d = &fl->desc[fl->pidx];
4919 	sd = &fl->sdesc[fl->pidx];
4920 	rxb = &sc->sge.rx_buf_info[zidx];
4921 
4922 	while (n > 0) {
4923 
4924 		if (sd->cl != NULL) {
4925 
4926 			if (sd->nmbuf == 0) {
4927 				/*
4928 				 * Fast recycle without involving any atomics on
4929 				 * the cluster's metadata (if the cluster has
4930 				 * metadata).  This happens when all frames
4931 				 * received in the cluster were small enough to
4932 				 * fit within a single mbuf each.
4933 				 */
4934 				fl->cl_fast_recycled++;
4935 				goto recycled;
4936 			}
4937 
4938 			/*
4939 			 * Cluster is guaranteed to have metadata.  Clusters
4940 			 * without metadata always take the fast recycle path
4941 			 * when they're recycled.
4942 			 */
4943 			clm = cl_metadata(sd);
4944 			MPASS(clm != NULL);
4945 
4946 			if (atomic_fetchadd_int(&clm->refcount, -1) == 1) {
4947 				fl->cl_recycled++;
4948 				counter_u64_add(extfree_rels, 1);
4949 				goto recycled;
4950 			}
4951 			sd->cl = NULL;	/* gave up my reference */
4952 		}
4953 		MPASS(sd->cl == NULL);
4954 		cl = uma_zalloc(rxb->zone, M_NOWAIT);
4955 		if (__predict_false(cl == NULL)) {
4956 			if (zidx != fl->safe_zidx) {
4957 				zidx = fl->safe_zidx;
4958 				rxb = &sc->sge.rx_buf_info[zidx];
4959 				cl = uma_zalloc(rxb->zone, M_NOWAIT);
4960 			}
4961 			if (cl == NULL)
4962 				break;
4963 		}
4964 		fl->cl_allocated++;
4965 		n--;
4966 
4967 		pa = pmap_kextract((vm_offset_t)cl);
4968 		sd->cl = cl;
4969 		sd->zidx = zidx;
4970 
4971 		if (fl->flags & FL_BUF_PACKING) {
4972 			*d = htobe64(pa | rxb->hwidx2);
4973 			sd->moff = rxb->size2;
4974 		} else {
4975 			*d = htobe64(pa | rxb->hwidx1);
4976 			sd->moff = 0;
4977 		}
4978 recycled:
4979 		sd->nmbuf = 0;
4980 		d++;
4981 		sd++;
4982 		if (__predict_false((++fl->pidx & 7) == 0)) {
4983 			uint16_t pidx = fl->pidx >> 3;
4984 
4985 			if (__predict_false(pidx == fl->sidx)) {
4986 				fl->pidx = 0;
4987 				pidx = 0;
4988 				sd = fl->sdesc;
4989 				d = fl->desc;
4990 			}
4991 			if (n < 8 || pidx == max_pidx)
4992 				break;
4993 
4994 			if (IDXDIFF(pidx, fl->dbidx, fl->sidx) >= 4)
4995 				ring_fl_db(sc, fl);
4996 		}
4997 	}
4998 
4999 	if ((fl->pidx >> 3) != fl->dbidx)
5000 		ring_fl_db(sc, fl);
5001 
5002 	return (FL_RUNNING_LOW(fl) && !(fl->flags & FL_STARVING));
5003 }
5004 
5005 /*
5006  * Attempt to refill all starving freelists.
5007  */
5008 static void
5009 refill_sfl(void *arg)
5010 {
5011 	struct adapter *sc = arg;
5012 	struct sge_fl *fl, *fl_temp;
5013 
5014 	mtx_assert(&sc->sfl_lock, MA_OWNED);
5015 	TAILQ_FOREACH_SAFE(fl, &sc->sfl, link, fl_temp) {
5016 		FL_LOCK(fl);
5017 		refill_fl(sc, fl, 64);
5018 		if (FL_NOT_RUNNING_LOW(fl) || fl->flags & FL_DOOMED) {
5019 			TAILQ_REMOVE(&sc->sfl, fl, link);
5020 			fl->flags &= ~FL_STARVING;
5021 		}
5022 		FL_UNLOCK(fl);
5023 	}
5024 
5025 	if (!TAILQ_EMPTY(&sc->sfl))
5026 		callout_schedule(&sc->sfl_callout, hz / 5);
5027 }
5028 
5029 /*
5030  * Release the driver's reference on all buffers in the given freelist.  Buffers
5031  * with kernel references cannot be freed and will prevent the driver from being
5032  * unloaded safely.
5033  */
5034 void
5035 free_fl_buffers(struct adapter *sc, struct sge_fl *fl)
5036 {
5037 	struct fl_sdesc *sd;
5038 	struct cluster_metadata *clm;
5039 	int i;
5040 
5041 	sd = fl->sdesc;
5042 	for (i = 0; i < fl->sidx * 8; i++, sd++) {
5043 		if (sd->cl == NULL)
5044 			continue;
5045 
5046 		if (sd->nmbuf == 0)
5047 			uma_zfree(sc->sge.rx_buf_info[sd->zidx].zone, sd->cl);
5048 		else if (fl->flags & FL_BUF_PACKING) {
5049 			clm = cl_metadata(sd);
5050 			if (atomic_fetchadd_int(&clm->refcount, -1) == 1) {
5051 				uma_zfree(sc->sge.rx_buf_info[sd->zidx].zone,
5052 				    sd->cl);
5053 				counter_u64_add(extfree_rels, 1);
5054 			}
5055 		}
5056 		sd->cl = NULL;
5057 	}
5058 
5059 	if (fl->flags & FL_BUF_RESUME) {
5060 		m_freem(fl->m0);
5061 		fl->flags &= ~FL_BUF_RESUME;
5062 	}
5063 }
5064 
5065 static inline void
5066 get_pkt_gl(struct mbuf *m, struct sglist *gl)
5067 {
5068 	int rc;
5069 
5070 	M_ASSERTPKTHDR(m);
5071 
5072 	sglist_reset(gl);
5073 	rc = sglist_append_mbuf(gl, m);
5074 	if (__predict_false(rc != 0)) {
5075 		panic("%s: mbuf %p (%d segs) was vetted earlier but now fails "
5076 		    "with %d.", __func__, m, mbuf_nsegs(m), rc);
5077 	}
5078 
5079 	KASSERT(gl->sg_nseg == mbuf_nsegs(m),
5080 	    ("%s: nsegs changed for mbuf %p from %d to %d", __func__, m,
5081 	    mbuf_nsegs(m), gl->sg_nseg));
5082 #if 0	/* vm_wr not readily available here. */
5083 	KASSERT(gl->sg_nseg > 0 && gl->sg_nseg <= max_nsegs_allowed(m, vm_wr),
5084 	    ("%s: %d segments, should have been 1 <= nsegs <= %d", __func__,
5085 		gl->sg_nseg, max_nsegs_allowed(m, vm_wr)));
5086 #endif
5087 }
5088 
5089 /*
5090  * len16 for a txpkt WR with a GL.  Includes the firmware work request header.
5091  */
5092 static inline u_int
5093 txpkt_len16(u_int nsegs, const u_int extra)
5094 {
5095 	u_int n;
5096 
5097 	MPASS(nsegs > 0);
5098 
5099 	nsegs--; /* first segment is part of ulptx_sgl */
5100 	n = extra + sizeof(struct fw_eth_tx_pkt_wr) +
5101 	    sizeof(struct cpl_tx_pkt_core) +
5102 	    sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1));
5103 
5104 	return (howmany(n, 16));
5105 }
5106 
5107 /*
5108  * len16 for a txpkt_vm WR with a GL.  Includes the firmware work
5109  * request header.
5110  */
5111 static inline u_int
5112 txpkt_vm_len16(u_int nsegs, const u_int extra)
5113 {
5114 	u_int n;
5115 
5116 	MPASS(nsegs > 0);
5117 
5118 	nsegs--; /* first segment is part of ulptx_sgl */
5119 	n = extra + sizeof(struct fw_eth_tx_pkt_vm_wr) +
5120 	    sizeof(struct cpl_tx_pkt_core) +
5121 	    sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1));
5122 
5123 	return (howmany(n, 16));
5124 }
5125 
5126 static inline void
5127 calculate_mbuf_len16(struct mbuf *m, bool vm_wr)
5128 {
5129 	const int lso = sizeof(struct cpl_tx_pkt_lso_core);
5130 	const int tnl_lso = sizeof(struct cpl_tx_tnl_lso);
5131 
5132 	if (vm_wr) {
5133 		if (needs_tso(m))
5134 			set_mbuf_len16(m, txpkt_vm_len16(mbuf_nsegs(m), lso));
5135 		else
5136 			set_mbuf_len16(m, txpkt_vm_len16(mbuf_nsegs(m), 0));
5137 		return;
5138 	}
5139 
5140 	if (needs_tso(m)) {
5141 		if (needs_vxlan_tso(m))
5142 			set_mbuf_len16(m, txpkt_len16(mbuf_nsegs(m), tnl_lso));
5143 		else
5144 			set_mbuf_len16(m, txpkt_len16(mbuf_nsegs(m), lso));
5145 	} else
5146 		set_mbuf_len16(m, txpkt_len16(mbuf_nsegs(m), 0));
5147 }
5148 
5149 /*
5150  * len16 for a txpkts type 0 WR with a GL.  Does not include the firmware work
5151  * request header.
5152  */
5153 static inline u_int
5154 txpkts0_len16(u_int nsegs)
5155 {
5156 	u_int n;
5157 
5158 	MPASS(nsegs > 0);
5159 
5160 	nsegs--; /* first segment is part of ulptx_sgl */
5161 	n = sizeof(struct ulp_txpkt) + sizeof(struct ulptx_idata) +
5162 	    sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl) +
5163 	    8 * ((3 * nsegs) / 2 + (nsegs & 1));
5164 
5165 	return (howmany(n, 16));
5166 }
5167 
5168 /*
5169  * len16 for a txpkts type 1 WR with a GL.  Does not include the firmware work
5170  * request header.
5171  */
5172 static inline u_int
5173 txpkts1_len16(void)
5174 {
5175 	u_int n;
5176 
5177 	n = sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl);
5178 
5179 	return (howmany(n, 16));
5180 }
5181 
5182 static inline u_int
5183 imm_payload(u_int ndesc)
5184 {
5185 	u_int n;
5186 
5187 	n = ndesc * EQ_ESIZE - sizeof(struct fw_eth_tx_pkt_wr) -
5188 	    sizeof(struct cpl_tx_pkt_core);
5189 
5190 	return (n);
5191 }
5192 
5193 static inline uint64_t
5194 csum_to_ctrl(struct adapter *sc, struct mbuf *m)
5195 {
5196 	uint64_t ctrl;
5197 	int csum_type, l2hlen, l3hlen;
5198 	int x, y;
5199 	static const int csum_types[3][2] = {
5200 		{TX_CSUM_TCPIP, TX_CSUM_TCPIP6},
5201 		{TX_CSUM_UDPIP, TX_CSUM_UDPIP6},
5202 		{TX_CSUM_IP, 0}
5203 	};
5204 
5205 	M_ASSERTPKTHDR(m);
5206 
5207 	if (!needs_hwcsum(m))
5208 		return (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS);
5209 
5210 	MPASS(m->m_pkthdr.l2hlen >= ETHER_HDR_LEN);
5211 	MPASS(m->m_pkthdr.l3hlen >= sizeof(struct ip));
5212 
5213 	if (needs_vxlan_csum(m)) {
5214 		MPASS(m->m_pkthdr.l4hlen > 0);
5215 		MPASS(m->m_pkthdr.l5hlen > 0);
5216 		MPASS(m->m_pkthdr.inner_l2hlen >= ETHER_HDR_LEN);
5217 		MPASS(m->m_pkthdr.inner_l3hlen >= sizeof(struct ip));
5218 
5219 		l2hlen = m->m_pkthdr.l2hlen + m->m_pkthdr.l3hlen +
5220 		    m->m_pkthdr.l4hlen + m->m_pkthdr.l5hlen +
5221 		    m->m_pkthdr.inner_l2hlen - ETHER_HDR_LEN;
5222 		l3hlen = m->m_pkthdr.inner_l3hlen;
5223 	} else {
5224 		l2hlen = m->m_pkthdr.l2hlen - ETHER_HDR_LEN;
5225 		l3hlen = m->m_pkthdr.l3hlen;
5226 	}
5227 
5228 	ctrl = 0;
5229 	if (!needs_l3_csum(m))
5230 		ctrl |= F_TXPKT_IPCSUM_DIS;
5231 
5232 	if (m->m_pkthdr.csum_flags & (CSUM_IP_TCP | CSUM_INNER_IP_TCP |
5233 	    CSUM_IP6_TCP | CSUM_INNER_IP6_TCP))
5234 		x = 0;	/* TCP */
5235 	else if (m->m_pkthdr.csum_flags & (CSUM_IP_UDP | CSUM_INNER_IP_UDP |
5236 	    CSUM_IP6_UDP | CSUM_INNER_IP6_UDP))
5237 		x = 1;	/* UDP */
5238 	else
5239 		x = 2;
5240 
5241 	if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_IP_TCP | CSUM_IP_UDP |
5242 	    CSUM_INNER_IP | CSUM_INNER_IP_TCP | CSUM_INNER_IP_UDP))
5243 		y = 0;	/* IPv4 */
5244 	else {
5245 		MPASS(m->m_pkthdr.csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP |
5246 		    CSUM_INNER_IP6_TCP | CSUM_INNER_IP6_UDP));
5247 		y = 1;	/* IPv6 */
5248 	}
5249 	/*
5250 	 * needs_hwcsum returned true earlier so there must be some kind of
5251 	 * checksum to calculate.
5252 	 */
5253 	csum_type = csum_types[x][y];
5254 	MPASS(csum_type != 0);
5255 	if (csum_type == TX_CSUM_IP)
5256 		ctrl |= F_TXPKT_L4CSUM_DIS;
5257 	ctrl |= V_TXPKT_CSUM_TYPE(csum_type) | V_TXPKT_IPHDR_LEN(l3hlen);
5258 	if (chip_id(sc) <= CHELSIO_T5)
5259 		ctrl |= V_TXPKT_ETHHDR_LEN(l2hlen);
5260 	else
5261 		ctrl |= V_T6_TXPKT_ETHHDR_LEN(l2hlen);
5262 
5263 	return (ctrl);
5264 }
5265 
5266 static inline void *
5267 write_lso_cpl(void *cpl, struct mbuf *m0)
5268 {
5269 	struct cpl_tx_pkt_lso_core *lso;
5270 	uint32_t ctrl;
5271 
5272 	KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 &&
5273 	    m0->m_pkthdr.l4hlen > 0,
5274 	    ("%s: mbuf %p needs TSO but missing header lengths",
5275 		__func__, m0));
5276 
5277 	ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) |
5278 	    F_LSO_FIRST_SLICE | F_LSO_LAST_SLICE |
5279 	    V_LSO_ETHHDR_LEN((m0->m_pkthdr.l2hlen - ETHER_HDR_LEN) >> 2) |
5280 	    V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) |
5281 	    V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2);
5282 	if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr))
5283 		ctrl |= F_LSO_IPV6;
5284 
5285 	lso = cpl;
5286 	lso->lso_ctrl = htobe32(ctrl);
5287 	lso->ipid_ofst = htobe16(0);
5288 	lso->mss = htobe16(m0->m_pkthdr.tso_segsz);
5289 	lso->seqno_offset = htobe32(0);
5290 	lso->len = htobe32(m0->m_pkthdr.len);
5291 
5292 	return (lso + 1);
5293 }
5294 
5295 static void *
5296 write_tnl_lso_cpl(void *cpl, struct mbuf *m0)
5297 {
5298 	struct cpl_tx_tnl_lso *tnl_lso = cpl;
5299 	uint32_t ctrl;
5300 
5301 	KASSERT(m0->m_pkthdr.inner_l2hlen > 0 &&
5302 	    m0->m_pkthdr.inner_l3hlen > 0 && m0->m_pkthdr.inner_l4hlen > 0 &&
5303 	    m0->m_pkthdr.inner_l5hlen > 0,
5304 	    ("%s: mbuf %p needs VXLAN_TSO but missing inner header lengths",
5305 		__func__, m0));
5306 	KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 &&
5307 	    m0->m_pkthdr.l4hlen > 0 && m0->m_pkthdr.l5hlen > 0,
5308 	    ("%s: mbuf %p needs VXLAN_TSO but missing outer header lengths",
5309 		__func__, m0));
5310 
5311 	/* Outer headers. */
5312 	ctrl = V_CPL_TX_TNL_LSO_OPCODE(CPL_TX_TNL_LSO) |
5313 	    F_CPL_TX_TNL_LSO_FIRST | F_CPL_TX_TNL_LSO_LAST |
5314 	    V_CPL_TX_TNL_LSO_ETHHDRLENOUT(
5315 		(m0->m_pkthdr.l2hlen - ETHER_HDR_LEN) >> 2) |
5316 	    V_CPL_TX_TNL_LSO_IPHDRLENOUT(m0->m_pkthdr.l3hlen >> 2) |
5317 	    F_CPL_TX_TNL_LSO_IPLENSETOUT;
5318 	if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr))
5319 		ctrl |= F_CPL_TX_TNL_LSO_IPV6OUT;
5320 	else {
5321 		ctrl |= F_CPL_TX_TNL_LSO_IPHDRCHKOUT |
5322 		    F_CPL_TX_TNL_LSO_IPIDINCOUT;
5323 	}
5324 	tnl_lso->op_to_IpIdSplitOut = htobe32(ctrl);
5325 	tnl_lso->IpIdOffsetOut = 0;
5326 	tnl_lso->UdpLenSetOut_to_TnlHdrLen =
5327 		htobe16(F_CPL_TX_TNL_LSO_UDPCHKCLROUT |
5328 		    F_CPL_TX_TNL_LSO_UDPLENSETOUT |
5329 		    V_CPL_TX_TNL_LSO_TNLHDRLEN(m0->m_pkthdr.l2hlen +
5330 			m0->m_pkthdr.l3hlen + m0->m_pkthdr.l4hlen +
5331 			m0->m_pkthdr.l5hlen) |
5332 		    V_CPL_TX_TNL_LSO_TNLTYPE(TX_TNL_TYPE_VXLAN));
5333 	tnl_lso->r1 = 0;
5334 
5335 	/* Inner headers. */
5336 	ctrl = V_CPL_TX_TNL_LSO_ETHHDRLEN(
5337 	    (m0->m_pkthdr.inner_l2hlen - ETHER_HDR_LEN) >> 2) |
5338 	    V_CPL_TX_TNL_LSO_IPHDRLEN(m0->m_pkthdr.inner_l3hlen >> 2) |
5339 	    V_CPL_TX_TNL_LSO_TCPHDRLEN(m0->m_pkthdr.inner_l4hlen >> 2);
5340 	if (m0->m_pkthdr.inner_l3hlen == sizeof(struct ip6_hdr))
5341 		ctrl |= F_CPL_TX_TNL_LSO_IPV6;
5342 	tnl_lso->Flow_to_TcpHdrLen = htobe32(ctrl);
5343 	tnl_lso->IpIdOffset = 0;
5344 	tnl_lso->IpIdSplit_to_Mss =
5345 	    htobe16(V_CPL_TX_TNL_LSO_MSS(m0->m_pkthdr.tso_segsz));
5346 	tnl_lso->TCPSeqOffset = 0;
5347 	tnl_lso->EthLenOffset_Size =
5348 	    htobe32(V_CPL_TX_TNL_LSO_SIZE(m0->m_pkthdr.len));
5349 
5350 	return (tnl_lso + 1);
5351 }
5352 
5353 #define VM_TX_L2HDR_LEN	16	/* ethmacdst to vlantci */
5354 
5355 /*
5356  * Write a VM txpkt WR for this packet to the hardware descriptors, update the
5357  * software descriptor, and advance the pidx.  It is guaranteed that enough
5358  * descriptors are available.
5359  *
5360  * The return value is the # of hardware descriptors used.
5361  */
5362 static u_int
5363 write_txpkt_vm_wr(struct adapter *sc, struct sge_txq *txq, struct mbuf *m0)
5364 {
5365 	struct sge_eq *eq;
5366 	struct fw_eth_tx_pkt_vm_wr *wr;
5367 	struct tx_sdesc *txsd;
5368 	struct cpl_tx_pkt_core *cpl;
5369 	uint32_t ctrl;	/* used in many unrelated places */
5370 	uint64_t ctrl1;
5371 	int len16, ndesc, pktlen, nsegs;
5372 	caddr_t dst;
5373 
5374 	TXQ_LOCK_ASSERT_OWNED(txq);
5375 	M_ASSERTPKTHDR(m0);
5376 
5377 	len16 = mbuf_len16(m0);
5378 	nsegs = mbuf_nsegs(m0);
5379 	pktlen = m0->m_pkthdr.len;
5380 	ctrl = sizeof(struct cpl_tx_pkt_core);
5381 	if (needs_tso(m0))
5382 		ctrl += sizeof(struct cpl_tx_pkt_lso_core);
5383 	ndesc = tx_len16_to_desc(len16);
5384 
5385 	/* Firmware work request header */
5386 	eq = &txq->eq;
5387 	wr = (void *)&eq->desc[eq->pidx];
5388 	wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_VM_WR) |
5389 	    V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl));
5390 
5391 	ctrl = V_FW_WR_LEN16(len16);
5392 	wr->equiq_to_len16 = htobe32(ctrl);
5393 	wr->r3[0] = 0;
5394 	wr->r3[1] = 0;
5395 
5396 	/*
5397 	 * Copy over ethmacdst, ethmacsrc, ethtype, and vlantci.
5398 	 * vlantci is ignored unless the ethtype is 0x8100, so it's
5399 	 * simpler to always copy it rather than making it
5400 	 * conditional.  Also, it seems that we do not have to set
5401 	 * vlantci or fake the ethtype when doing VLAN tag insertion.
5402 	 */
5403 	m_copydata(m0, 0, VM_TX_L2HDR_LEN, wr->ethmacdst);
5404 
5405 	if (needs_tso(m0)) {
5406 		cpl = write_lso_cpl(wr + 1, m0);
5407 		txq->tso_wrs++;
5408 	} else
5409 		cpl = (void *)(wr + 1);
5410 
5411 	/* Checksum offload */
5412 	ctrl1 = csum_to_ctrl(sc, m0);
5413 	if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS))
5414 		txq->txcsum++;	/* some hardware assistance provided */
5415 
5416 	/* VLAN tag insertion */
5417 	if (needs_vlan_insertion(m0)) {
5418 		ctrl1 |= F_TXPKT_VLAN_VLD |
5419 		    V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag);
5420 		txq->vlan_insertion++;
5421 	}
5422 
5423 	/* CPL header */
5424 	cpl->ctrl0 = txq->cpl_ctrl0;
5425 	cpl->pack = 0;
5426 	cpl->len = htobe16(pktlen);
5427 	cpl->ctrl1 = htobe64(ctrl1);
5428 
5429 	/* SGL */
5430 	dst = (void *)(cpl + 1);
5431 
5432 	/*
5433 	 * A packet using TSO will use up an entire descriptor for the
5434 	 * firmware work request header, LSO CPL, and TX_PKT_XT CPL.
5435 	 * If this descriptor is the last descriptor in the ring, wrap
5436 	 * around to the front of the ring explicitly for the start of
5437 	 * the sgl.
5438 	 */
5439 	if (dst == (void *)&eq->desc[eq->sidx]) {
5440 		dst = (void *)&eq->desc[0];
5441 		write_gl_to_txd(txq, m0, &dst, 0);
5442 	} else
5443 		write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx);
5444 	txq->sgl_wrs++;
5445 	txq->txpkt_wrs++;
5446 
5447 	txsd = &txq->sdesc[eq->pidx];
5448 	txsd->m = m0;
5449 	txsd->desc_used = ndesc;
5450 
5451 	return (ndesc);
5452 }
5453 
5454 /*
5455  * Write a raw WR to the hardware descriptors, update the software
5456  * descriptor, and advance the pidx.  It is guaranteed that enough
5457  * descriptors are available.
5458  *
5459  * The return value is the # of hardware descriptors used.
5460  */
5461 static u_int
5462 write_raw_wr(struct sge_txq *txq, void *wr, struct mbuf *m0, u_int available)
5463 {
5464 	struct sge_eq *eq = &txq->eq;
5465 	struct tx_sdesc *txsd;
5466 	struct mbuf *m;
5467 	caddr_t dst;
5468 	int len16, ndesc;
5469 
5470 	len16 = mbuf_len16(m0);
5471 	ndesc = tx_len16_to_desc(len16);
5472 	MPASS(ndesc <= available);
5473 
5474 	dst = wr;
5475 	for (m = m0; m != NULL; m = m->m_next)
5476 		copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len);
5477 
5478 	txq->raw_wrs++;
5479 
5480 	txsd = &txq->sdesc[eq->pidx];
5481 	txsd->m = m0;
5482 	txsd->desc_used = ndesc;
5483 
5484 	return (ndesc);
5485 }
5486 
5487 /*
5488  * Write a txpkt WR for this packet to the hardware descriptors, update the
5489  * software descriptor, and advance the pidx.  It is guaranteed that enough
5490  * descriptors are available.
5491  *
5492  * The return value is the # of hardware descriptors used.
5493  */
5494 static u_int
5495 write_txpkt_wr(struct adapter *sc, struct sge_txq *txq, struct mbuf *m0,
5496     u_int available)
5497 {
5498 	struct sge_eq *eq;
5499 	struct fw_eth_tx_pkt_wr *wr;
5500 	struct tx_sdesc *txsd;
5501 	struct cpl_tx_pkt_core *cpl;
5502 	uint32_t ctrl;	/* used in many unrelated places */
5503 	uint64_t ctrl1;
5504 	int len16, ndesc, pktlen, nsegs;
5505 	caddr_t dst;
5506 
5507 	TXQ_LOCK_ASSERT_OWNED(txq);
5508 	M_ASSERTPKTHDR(m0);
5509 
5510 	len16 = mbuf_len16(m0);
5511 	nsegs = mbuf_nsegs(m0);
5512 	pktlen = m0->m_pkthdr.len;
5513 	ctrl = sizeof(struct cpl_tx_pkt_core);
5514 	if (needs_tso(m0)) {
5515 		if (needs_vxlan_tso(m0))
5516 			ctrl += sizeof(struct cpl_tx_tnl_lso);
5517 		else
5518 			ctrl += sizeof(struct cpl_tx_pkt_lso_core);
5519 	} else if (!(mbuf_cflags(m0) & MC_NOMAP) && pktlen <= imm_payload(2) &&
5520 	    available >= 2) {
5521 		/* Immediate data.  Recalculate len16 and set nsegs to 0. */
5522 		ctrl += pktlen;
5523 		len16 = howmany(sizeof(struct fw_eth_tx_pkt_wr) +
5524 		    sizeof(struct cpl_tx_pkt_core) + pktlen, 16);
5525 		nsegs = 0;
5526 	}
5527 	ndesc = tx_len16_to_desc(len16);
5528 	MPASS(ndesc <= available);
5529 
5530 	/* Firmware work request header */
5531 	eq = &txq->eq;
5532 	wr = (void *)&eq->desc[eq->pidx];
5533 	wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_WR) |
5534 	    V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl));
5535 
5536 	ctrl = V_FW_WR_LEN16(len16);
5537 	wr->equiq_to_len16 = htobe32(ctrl);
5538 	wr->r3 = 0;
5539 
5540 	if (needs_tso(m0)) {
5541 		if (needs_vxlan_tso(m0)) {
5542 			cpl = write_tnl_lso_cpl(wr + 1, m0);
5543 			txq->vxlan_tso_wrs++;
5544 		} else {
5545 			cpl = write_lso_cpl(wr + 1, m0);
5546 			txq->tso_wrs++;
5547 		}
5548 	} else
5549 		cpl = (void *)(wr + 1);
5550 
5551 	/* Checksum offload */
5552 	ctrl1 = csum_to_ctrl(sc, m0);
5553 	if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS)) {
5554 		/* some hardware assistance provided */
5555 		if (needs_vxlan_csum(m0))
5556 			txq->vxlan_txcsum++;
5557 		else
5558 			txq->txcsum++;
5559 	}
5560 
5561 	/* VLAN tag insertion */
5562 	if (needs_vlan_insertion(m0)) {
5563 		ctrl1 |= F_TXPKT_VLAN_VLD |
5564 		    V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag);
5565 		txq->vlan_insertion++;
5566 	}
5567 
5568 	/* CPL header */
5569 	cpl->ctrl0 = txq->cpl_ctrl0;
5570 	cpl->pack = 0;
5571 	cpl->len = htobe16(pktlen);
5572 	cpl->ctrl1 = htobe64(ctrl1);
5573 
5574 	/* SGL */
5575 	dst = (void *)(cpl + 1);
5576 	if (__predict_false((uintptr_t)dst == (uintptr_t)&eq->desc[eq->sidx]))
5577 		dst = (caddr_t)&eq->desc[0];
5578 	if (nsegs > 0) {
5579 
5580 		write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx);
5581 		txq->sgl_wrs++;
5582 	} else {
5583 		struct mbuf *m;
5584 
5585 		for (m = m0; m != NULL; m = m->m_next) {
5586 			copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len);
5587 #ifdef INVARIANTS
5588 			pktlen -= m->m_len;
5589 #endif
5590 		}
5591 #ifdef INVARIANTS
5592 		KASSERT(pktlen == 0, ("%s: %d bytes left.", __func__, pktlen));
5593 #endif
5594 		txq->imm_wrs++;
5595 	}
5596 
5597 	txq->txpkt_wrs++;
5598 
5599 	txsd = &txq->sdesc[eq->pidx];
5600 	txsd->m = m0;
5601 	txsd->desc_used = ndesc;
5602 
5603 	return (ndesc);
5604 }
5605 
5606 static inline bool
5607 cmp_l2hdr(struct txpkts *txp, struct mbuf *m)
5608 {
5609 	int len;
5610 
5611 	MPASS(txp->npkt > 0);
5612 	MPASS(m->m_len >= VM_TX_L2HDR_LEN);
5613 
5614 	if (txp->ethtype == be16toh(ETHERTYPE_VLAN))
5615 		len = VM_TX_L2HDR_LEN;
5616 	else
5617 		len = sizeof(struct ether_header);
5618 
5619 	return (memcmp(m->m_data, &txp->ethmacdst[0], len) != 0);
5620 }
5621 
5622 static inline void
5623 save_l2hdr(struct txpkts *txp, struct mbuf *m)
5624 {
5625 	MPASS(m->m_len >= VM_TX_L2HDR_LEN);
5626 
5627 	memcpy(&txp->ethmacdst[0], mtod(m, const void *), VM_TX_L2HDR_LEN);
5628 }
5629 
5630 static int
5631 add_to_txpkts_vf(struct adapter *sc, struct sge_txq *txq, struct mbuf *m,
5632     int avail, bool *send)
5633 {
5634 	struct txpkts *txp = &txq->txp;
5635 
5636 	/* Cannot have TSO and coalesce at the same time. */
5637 	if (cannot_use_txpkts(m)) {
5638 cannot_coalesce:
5639 		*send = txp->npkt > 0;
5640 		return (EINVAL);
5641 	}
5642 
5643 	/* VF allows coalescing of type 1 (1 GL) only */
5644 	if (mbuf_nsegs(m) > 1)
5645 		goto cannot_coalesce;
5646 
5647 	*send = false;
5648 	if (txp->npkt > 0) {
5649 		MPASS(tx_len16_to_desc(txp->len16) <= avail);
5650 		MPASS(txp->npkt < txp->max_npkt);
5651 		MPASS(txp->wr_type == 1);	/* VF supports type 1 only */
5652 
5653 		if (tx_len16_to_desc(txp->len16 + txpkts1_len16()) > avail) {
5654 retry_after_send:
5655 			*send = true;
5656 			return (EAGAIN);
5657 		}
5658 		if (m->m_pkthdr.len + txp->plen > 65535)
5659 			goto retry_after_send;
5660 		if (cmp_l2hdr(txp, m))
5661 			goto retry_after_send;
5662 
5663 		txp->len16 += txpkts1_len16();
5664 		txp->plen += m->m_pkthdr.len;
5665 		txp->mb[txp->npkt++] = m;
5666 		if (txp->npkt == txp->max_npkt)
5667 			*send = true;
5668 	} else {
5669 		txp->len16 = howmany(sizeof(struct fw_eth_tx_pkts_vm_wr), 16) +
5670 		    txpkts1_len16();
5671 		if (tx_len16_to_desc(txp->len16) > avail)
5672 			goto cannot_coalesce;
5673 		txp->npkt = 1;
5674 		txp->wr_type = 1;
5675 		txp->plen = m->m_pkthdr.len;
5676 		txp->mb[0] = m;
5677 		save_l2hdr(txp, m);
5678 	}
5679 	return (0);
5680 }
5681 
5682 static int
5683 add_to_txpkts_pf(struct adapter *sc, struct sge_txq *txq, struct mbuf *m,
5684     int avail, bool *send)
5685 {
5686 	struct txpkts *txp = &txq->txp;
5687 	int nsegs;
5688 
5689 	MPASS(!(sc->flags & IS_VF));
5690 
5691 	/* Cannot have TSO and coalesce at the same time. */
5692 	if (cannot_use_txpkts(m)) {
5693 cannot_coalesce:
5694 		*send = txp->npkt > 0;
5695 		return (EINVAL);
5696 	}
5697 
5698 	*send = false;
5699 	nsegs = mbuf_nsegs(m);
5700 	if (txp->npkt == 0) {
5701 		if (m->m_pkthdr.len > 65535)
5702 			goto cannot_coalesce;
5703 		if (nsegs > 1) {
5704 			txp->wr_type = 0;
5705 			txp->len16 =
5706 			    howmany(sizeof(struct fw_eth_tx_pkts_wr), 16) +
5707 			    txpkts0_len16(nsegs);
5708 		} else {
5709 			txp->wr_type = 1;
5710 			txp->len16 =
5711 			    howmany(sizeof(struct fw_eth_tx_pkts_wr), 16) +
5712 			    txpkts1_len16();
5713 		}
5714 		if (tx_len16_to_desc(txp->len16) > avail)
5715 			goto cannot_coalesce;
5716 		txp->npkt = 1;
5717 		txp->plen = m->m_pkthdr.len;
5718 		txp->mb[0] = m;
5719 	} else {
5720 		MPASS(tx_len16_to_desc(txp->len16) <= avail);
5721 		MPASS(txp->npkt < txp->max_npkt);
5722 
5723 		if (m->m_pkthdr.len + txp->plen > 65535) {
5724 retry_after_send:
5725 			*send = true;
5726 			return (EAGAIN);
5727 		}
5728 
5729 		MPASS(txp->wr_type == 0 || txp->wr_type == 1);
5730 		if (txp->wr_type == 0) {
5731 			if (tx_len16_to_desc(txp->len16 +
5732 			    txpkts0_len16(nsegs)) > min(avail, SGE_MAX_WR_NDESC))
5733 				goto retry_after_send;
5734 			txp->len16 += txpkts0_len16(nsegs);
5735 		} else {
5736 			if (nsegs != 1)
5737 				goto retry_after_send;
5738 			if (tx_len16_to_desc(txp->len16 + txpkts1_len16()) >
5739 			    avail)
5740 				goto retry_after_send;
5741 			txp->len16 += txpkts1_len16();
5742 		}
5743 
5744 		txp->plen += m->m_pkthdr.len;
5745 		txp->mb[txp->npkt++] = m;
5746 		if (txp->npkt == txp->max_npkt)
5747 			*send = true;
5748 	}
5749 	return (0);
5750 }
5751 
5752 /*
5753  * Write a txpkts WR for the packets in txp to the hardware descriptors, update
5754  * the software descriptor, and advance the pidx.  It is guaranteed that enough
5755  * descriptors are available.
5756  *
5757  * The return value is the # of hardware descriptors used.
5758  */
5759 static u_int
5760 write_txpkts_wr(struct adapter *sc, struct sge_txq *txq)
5761 {
5762 	const struct txpkts *txp = &txq->txp;
5763 	struct sge_eq *eq = &txq->eq;
5764 	struct fw_eth_tx_pkts_wr *wr;
5765 	struct tx_sdesc *txsd;
5766 	struct cpl_tx_pkt_core *cpl;
5767 	uint64_t ctrl1;
5768 	int ndesc, i, checkwrap;
5769 	struct mbuf *m, *last;
5770 	void *flitp;
5771 
5772 	TXQ_LOCK_ASSERT_OWNED(txq);
5773 	MPASS(txp->npkt > 0);
5774 	MPASS(txp->len16 <= howmany(SGE_MAX_WR_LEN, 16));
5775 
5776 	wr = (void *)&eq->desc[eq->pidx];
5777 	wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR));
5778 	wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(txp->len16));
5779 	wr->plen = htobe16(txp->plen);
5780 	wr->npkt = txp->npkt;
5781 	wr->r3 = 0;
5782 	wr->type = txp->wr_type;
5783 	flitp = wr + 1;
5784 
5785 	/*
5786 	 * At this point we are 16B into a hardware descriptor.  If checkwrap is
5787 	 * set then we know the WR is going to wrap around somewhere.  We'll
5788 	 * check for that at appropriate points.
5789 	 */
5790 	ndesc = tx_len16_to_desc(txp->len16);
5791 	last = NULL;
5792 	checkwrap = eq->sidx - ndesc < eq->pidx;
5793 	for (i = 0; i < txp->npkt; i++) {
5794 		m = txp->mb[i];
5795 		if (txp->wr_type == 0) {
5796 			struct ulp_txpkt *ulpmc;
5797 			struct ulptx_idata *ulpsc;
5798 
5799 			/* ULP master command */
5800 			ulpmc = flitp;
5801 			ulpmc->cmd_dest = htobe32(V_ULPTX_CMD(ULP_TX_PKT) |
5802 			    V_ULP_TXPKT_DEST(0) | V_ULP_TXPKT_FID(eq->iqid));
5803 			ulpmc->len = htobe32(txpkts0_len16(mbuf_nsegs(m)));
5804 
5805 			/* ULP subcommand */
5806 			ulpsc = (void *)(ulpmc + 1);
5807 			ulpsc->cmd_more = htobe32(V_ULPTX_CMD(ULP_TX_SC_IMM) |
5808 			    F_ULP_TX_SC_MORE);
5809 			ulpsc->len = htobe32(sizeof(struct cpl_tx_pkt_core));
5810 
5811 			cpl = (void *)(ulpsc + 1);
5812 			if (checkwrap &&
5813 			    (uintptr_t)cpl == (uintptr_t)&eq->desc[eq->sidx])
5814 				cpl = (void *)&eq->desc[0];
5815 		} else {
5816 			cpl = flitp;
5817 		}
5818 
5819 		/* Checksum offload */
5820 		ctrl1 = csum_to_ctrl(sc, m);
5821 		if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS)) {
5822 			/* some hardware assistance provided */
5823 			if (needs_vxlan_csum(m))
5824 				txq->vxlan_txcsum++;
5825 			else
5826 				txq->txcsum++;
5827 		}
5828 
5829 		/* VLAN tag insertion */
5830 		if (needs_vlan_insertion(m)) {
5831 			ctrl1 |= F_TXPKT_VLAN_VLD |
5832 			    V_TXPKT_VLAN(m->m_pkthdr.ether_vtag);
5833 			txq->vlan_insertion++;
5834 		}
5835 
5836 		/* CPL header */
5837 		cpl->ctrl0 = txq->cpl_ctrl0;
5838 		cpl->pack = 0;
5839 		cpl->len = htobe16(m->m_pkthdr.len);
5840 		cpl->ctrl1 = htobe64(ctrl1);
5841 
5842 		flitp = cpl + 1;
5843 		if (checkwrap &&
5844 		    (uintptr_t)flitp == (uintptr_t)&eq->desc[eq->sidx])
5845 			flitp = (void *)&eq->desc[0];
5846 
5847 		write_gl_to_txd(txq, m, (caddr_t *)(&flitp), checkwrap);
5848 
5849 		if (last != NULL)
5850 			last->m_nextpkt = m;
5851 		last = m;
5852 	}
5853 
5854 	txq->sgl_wrs++;
5855 	if (txp->wr_type == 0) {
5856 		txq->txpkts0_pkts += txp->npkt;
5857 		txq->txpkts0_wrs++;
5858 	} else {
5859 		txq->txpkts1_pkts += txp->npkt;
5860 		txq->txpkts1_wrs++;
5861 	}
5862 
5863 	txsd = &txq->sdesc[eq->pidx];
5864 	txsd->m = txp->mb[0];
5865 	txsd->desc_used = ndesc;
5866 
5867 	return (ndesc);
5868 }
5869 
5870 static u_int
5871 write_txpkts_vm_wr(struct adapter *sc, struct sge_txq *txq)
5872 {
5873 	const struct txpkts *txp = &txq->txp;
5874 	struct sge_eq *eq = &txq->eq;
5875 	struct fw_eth_tx_pkts_vm_wr *wr;
5876 	struct tx_sdesc *txsd;
5877 	struct cpl_tx_pkt_core *cpl;
5878 	uint64_t ctrl1;
5879 	int ndesc, i;
5880 	struct mbuf *m, *last;
5881 	void *flitp;
5882 
5883 	TXQ_LOCK_ASSERT_OWNED(txq);
5884 	MPASS(txp->npkt > 0);
5885 	MPASS(txp->wr_type == 1);	/* VF supports type 1 only */
5886 	MPASS(txp->mb[0] != NULL);
5887 	MPASS(txp->len16 <= howmany(SGE_MAX_WR_LEN, 16));
5888 
5889 	wr = (void *)&eq->desc[eq->pidx];
5890 	wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_VM_WR));
5891 	wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(txp->len16));
5892 	wr->r3 = 0;
5893 	wr->plen = htobe16(txp->plen);
5894 	wr->npkt = txp->npkt;
5895 	wr->r4 = 0;
5896 	memcpy(&wr->ethmacdst[0], &txp->ethmacdst[0], 16);
5897 	flitp = wr + 1;
5898 
5899 	/*
5900 	 * At this point we are 32B into a hardware descriptor.  Each mbuf in
5901 	 * the WR will take 32B so we check for the end of the descriptor ring
5902 	 * before writing odd mbufs (mb[1], 3, 5, ..)
5903 	 */
5904 	ndesc = tx_len16_to_desc(txp->len16);
5905 	last = NULL;
5906 	for (i = 0; i < txp->npkt; i++) {
5907 		m = txp->mb[i];
5908 		if (i & 1 && (uintptr_t)flitp == (uintptr_t)&eq->desc[eq->sidx])
5909 			flitp = &eq->desc[0];
5910 		cpl = flitp;
5911 
5912 		/* Checksum offload */
5913 		ctrl1 = csum_to_ctrl(sc, m);
5914 		if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS))
5915 			txq->txcsum++;	/* some hardware assistance provided */
5916 
5917 		/* VLAN tag insertion */
5918 		if (needs_vlan_insertion(m)) {
5919 			ctrl1 |= F_TXPKT_VLAN_VLD |
5920 			    V_TXPKT_VLAN(m->m_pkthdr.ether_vtag);
5921 			txq->vlan_insertion++;
5922 		}
5923 
5924 		/* CPL header */
5925 		cpl->ctrl0 = txq->cpl_ctrl0;
5926 		cpl->pack = 0;
5927 		cpl->len = htobe16(m->m_pkthdr.len);
5928 		cpl->ctrl1 = htobe64(ctrl1);
5929 
5930 		flitp = cpl + 1;
5931 		MPASS(mbuf_nsegs(m) == 1);
5932 		write_gl_to_txd(txq, m, (caddr_t *)(&flitp), 0);
5933 
5934 		if (last != NULL)
5935 			last->m_nextpkt = m;
5936 		last = m;
5937 	}
5938 
5939 	txq->sgl_wrs++;
5940 	txq->txpkts1_pkts += txp->npkt;
5941 	txq->txpkts1_wrs++;
5942 
5943 	txsd = &txq->sdesc[eq->pidx];
5944 	txsd->m = txp->mb[0];
5945 	txsd->desc_used = ndesc;
5946 
5947 	return (ndesc);
5948 }
5949 
5950 /*
5951  * If the SGL ends on an address that is not 16 byte aligned, this function will
5952  * add a 0 filled flit at the end.
5953  */
5954 static void
5955 write_gl_to_txd(struct sge_txq *txq, struct mbuf *m, caddr_t *to, int checkwrap)
5956 {
5957 	struct sge_eq *eq = &txq->eq;
5958 	struct sglist *gl = txq->gl;
5959 	struct sglist_seg *seg;
5960 	__be64 *flitp, *wrap;
5961 	struct ulptx_sgl *usgl;
5962 	int i, nflits, nsegs;
5963 
5964 	KASSERT(((uintptr_t)(*to) & 0xf) == 0,
5965 	    ("%s: SGL must start at a 16 byte boundary: %p", __func__, *to));
5966 	MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]);
5967 	MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]);
5968 
5969 	get_pkt_gl(m, gl);
5970 	nsegs = gl->sg_nseg;
5971 	MPASS(nsegs > 0);
5972 
5973 	nflits = (3 * (nsegs - 1)) / 2 + ((nsegs - 1) & 1) + 2;
5974 	flitp = (__be64 *)(*to);
5975 	wrap = (__be64 *)(&eq->desc[eq->sidx]);
5976 	seg = &gl->sg_segs[0];
5977 	usgl = (void *)flitp;
5978 
5979 	/*
5980 	 * We start at a 16 byte boundary somewhere inside the tx descriptor
5981 	 * ring, so we're at least 16 bytes away from the status page.  There is
5982 	 * no chance of a wrap around in the middle of usgl (which is 16 bytes).
5983 	 */
5984 
5985 	usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) |
5986 	    V_ULPTX_NSGE(nsegs));
5987 	usgl->len0 = htobe32(seg->ss_len);
5988 	usgl->addr0 = htobe64(seg->ss_paddr);
5989 	seg++;
5990 
5991 	if (checkwrap == 0 || (uintptr_t)(flitp + nflits) <= (uintptr_t)wrap) {
5992 
5993 		/* Won't wrap around at all */
5994 
5995 		for (i = 0; i < nsegs - 1; i++, seg++) {
5996 			usgl->sge[i / 2].len[i & 1] = htobe32(seg->ss_len);
5997 			usgl->sge[i / 2].addr[i & 1] = htobe64(seg->ss_paddr);
5998 		}
5999 		if (i & 1)
6000 			usgl->sge[i / 2].len[1] = htobe32(0);
6001 		flitp += nflits;
6002 	} else {
6003 
6004 		/* Will wrap somewhere in the rest of the SGL */
6005 
6006 		/* 2 flits already written, write the rest flit by flit */
6007 		flitp = (void *)(usgl + 1);
6008 		for (i = 0; i < nflits - 2; i++) {
6009 			if (flitp == wrap)
6010 				flitp = (void *)eq->desc;
6011 			*flitp++ = get_flit(seg, nsegs - 1, i);
6012 		}
6013 	}
6014 
6015 	if (nflits & 1) {
6016 		MPASS(((uintptr_t)flitp) & 0xf);
6017 		*flitp++ = 0;
6018 	}
6019 
6020 	MPASS((((uintptr_t)flitp) & 0xf) == 0);
6021 	if (__predict_false(flitp == wrap))
6022 		*to = (void *)eq->desc;
6023 	else
6024 		*to = (void *)flitp;
6025 }
6026 
6027 static inline void
6028 copy_to_txd(struct sge_eq *eq, caddr_t from, caddr_t *to, int len)
6029 {
6030 
6031 	MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]);
6032 	MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]);
6033 
6034 	if (__predict_true((uintptr_t)(*to) + len <=
6035 	    (uintptr_t)&eq->desc[eq->sidx])) {
6036 		bcopy(from, *to, len);
6037 		(*to) += len;
6038 	} else {
6039 		int portion = (uintptr_t)&eq->desc[eq->sidx] - (uintptr_t)(*to);
6040 
6041 		bcopy(from, *to, portion);
6042 		from += portion;
6043 		portion = len - portion;	/* remaining */
6044 		bcopy(from, (void *)eq->desc, portion);
6045 		(*to) = (caddr_t)eq->desc + portion;
6046 	}
6047 }
6048 
6049 static inline void
6050 ring_eq_db(struct adapter *sc, struct sge_eq *eq, u_int n)
6051 {
6052 	u_int db;
6053 
6054 	MPASS(n > 0);
6055 
6056 	db = eq->doorbells;
6057 	if (n > 1)
6058 		clrbit(&db, DOORBELL_WCWR);
6059 	wmb();
6060 
6061 	switch (ffs(db) - 1) {
6062 	case DOORBELL_UDB:
6063 		*eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n));
6064 		break;
6065 
6066 	case DOORBELL_WCWR: {
6067 		volatile uint64_t *dst, *src;
6068 		int i;
6069 
6070 		/*
6071 		 * Queues whose 128B doorbell segment fits in the page do not
6072 		 * use relative qid (udb_qid is always 0).  Only queues with
6073 		 * doorbell segments can do WCWR.
6074 		 */
6075 		KASSERT(eq->udb_qid == 0 && n == 1,
6076 		    ("%s: inappropriate doorbell (0x%x, %d, %d) for eq %p",
6077 		    __func__, eq->doorbells, n, eq->dbidx, eq));
6078 
6079 		dst = (volatile void *)((uintptr_t)eq->udb + UDBS_WR_OFFSET -
6080 		    UDBS_DB_OFFSET);
6081 		i = eq->dbidx;
6082 		src = (void *)&eq->desc[i];
6083 		while (src != (void *)&eq->desc[i + 1])
6084 			*dst++ = *src++;
6085 		wmb();
6086 		break;
6087 	}
6088 
6089 	case DOORBELL_UDBWC:
6090 		*eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n));
6091 		wmb();
6092 		break;
6093 
6094 	case DOORBELL_KDB:
6095 		t4_write_reg(sc, sc->sge_kdoorbell_reg,
6096 		    V_QID(eq->cntxt_id) | V_PIDX(n));
6097 		break;
6098 	}
6099 
6100 	IDXINCR(eq->dbidx, n, eq->sidx);
6101 }
6102 
6103 static inline u_int
6104 reclaimable_tx_desc(struct sge_eq *eq)
6105 {
6106 	uint16_t hw_cidx;
6107 
6108 	hw_cidx = read_hw_cidx(eq);
6109 	return (IDXDIFF(hw_cidx, eq->cidx, eq->sidx));
6110 }
6111 
6112 static inline u_int
6113 total_available_tx_desc(struct sge_eq *eq)
6114 {
6115 	uint16_t hw_cidx, pidx;
6116 
6117 	hw_cidx = read_hw_cidx(eq);
6118 	pidx = eq->pidx;
6119 
6120 	if (pidx == hw_cidx)
6121 		return (eq->sidx - 1);
6122 	else
6123 		return (IDXDIFF(hw_cidx, pidx, eq->sidx) - 1);
6124 }
6125 
6126 static inline uint16_t
6127 read_hw_cidx(struct sge_eq *eq)
6128 {
6129 	struct sge_qstat *spg = (void *)&eq->desc[eq->sidx];
6130 	uint16_t cidx = spg->cidx;	/* stable snapshot */
6131 
6132 	return (be16toh(cidx));
6133 }
6134 
6135 /*
6136  * Reclaim 'n' descriptors approximately.
6137  */
6138 static u_int
6139 reclaim_tx_descs(struct sge_txq *txq, u_int n)
6140 {
6141 	struct tx_sdesc *txsd;
6142 	struct sge_eq *eq = &txq->eq;
6143 	u_int can_reclaim, reclaimed;
6144 
6145 	TXQ_LOCK_ASSERT_OWNED(txq);
6146 	MPASS(n > 0);
6147 
6148 	reclaimed = 0;
6149 	can_reclaim = reclaimable_tx_desc(eq);
6150 	while (can_reclaim && reclaimed < n) {
6151 		int ndesc;
6152 		struct mbuf *m, *nextpkt;
6153 
6154 		txsd = &txq->sdesc[eq->cidx];
6155 		ndesc = txsd->desc_used;
6156 
6157 		/* Firmware doesn't return "partial" credits. */
6158 		KASSERT(can_reclaim >= ndesc,
6159 		    ("%s: unexpected number of credits: %d, %d",
6160 		    __func__, can_reclaim, ndesc));
6161 		KASSERT(ndesc != 0,
6162 		    ("%s: descriptor with no credits: cidx %d",
6163 		    __func__, eq->cidx));
6164 
6165 		for (m = txsd->m; m != NULL; m = nextpkt) {
6166 			nextpkt = m->m_nextpkt;
6167 			m->m_nextpkt = NULL;
6168 			m_freem(m);
6169 		}
6170 		reclaimed += ndesc;
6171 		can_reclaim -= ndesc;
6172 		IDXINCR(eq->cidx, ndesc, eq->sidx);
6173 	}
6174 
6175 	return (reclaimed);
6176 }
6177 
6178 static void
6179 tx_reclaim(void *arg, int n)
6180 {
6181 	struct sge_txq *txq = arg;
6182 	struct sge_eq *eq = &txq->eq;
6183 
6184 	do {
6185 		if (TXQ_TRYLOCK(txq) == 0)
6186 			break;
6187 		n = reclaim_tx_descs(txq, 32);
6188 		if (eq->cidx == eq->pidx)
6189 			eq->equeqidx = eq->pidx;
6190 		TXQ_UNLOCK(txq);
6191 	} while (n > 0);
6192 }
6193 
6194 static __be64
6195 get_flit(struct sglist_seg *segs, int nsegs, int idx)
6196 {
6197 	int i = (idx / 3) * 2;
6198 
6199 	switch (idx % 3) {
6200 	case 0: {
6201 		uint64_t rc;
6202 
6203 		rc = (uint64_t)segs[i].ss_len << 32;
6204 		if (i + 1 < nsegs)
6205 			rc |= (uint64_t)(segs[i + 1].ss_len);
6206 
6207 		return (htobe64(rc));
6208 	}
6209 	case 1:
6210 		return (htobe64(segs[i].ss_paddr));
6211 	case 2:
6212 		return (htobe64(segs[i + 1].ss_paddr));
6213 	}
6214 
6215 	return (0);
6216 }
6217 
6218 static int
6219 find_refill_source(struct adapter *sc, int maxp, bool packing)
6220 {
6221 	int i, zidx = -1;
6222 	struct rx_buf_info *rxb = &sc->sge.rx_buf_info[0];
6223 
6224 	if (packing) {
6225 		for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) {
6226 			if (rxb->hwidx2 == -1)
6227 				continue;
6228 			if (rxb->size1 < PAGE_SIZE &&
6229 			    rxb->size1 < largest_rx_cluster)
6230 				continue;
6231 			if (rxb->size1 > largest_rx_cluster)
6232 				break;
6233 			MPASS(rxb->size1 - rxb->size2 >= CL_METADATA_SIZE);
6234 			if (rxb->size2 >= maxp)
6235 				return (i);
6236 			zidx = i;
6237 		}
6238 	} else {
6239 		for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) {
6240 			if (rxb->hwidx1 == -1)
6241 				continue;
6242 			if (rxb->size1 > largest_rx_cluster)
6243 				break;
6244 			if (rxb->size1 >= maxp)
6245 				return (i);
6246 			zidx = i;
6247 		}
6248 	}
6249 
6250 	return (zidx);
6251 }
6252 
6253 static void
6254 add_fl_to_sfl(struct adapter *sc, struct sge_fl *fl)
6255 {
6256 	mtx_lock(&sc->sfl_lock);
6257 	FL_LOCK(fl);
6258 	if ((fl->flags & FL_DOOMED) == 0) {
6259 		fl->flags |= FL_STARVING;
6260 		TAILQ_INSERT_TAIL(&sc->sfl, fl, link);
6261 		callout_reset(&sc->sfl_callout, hz / 5, refill_sfl, sc);
6262 	}
6263 	FL_UNLOCK(fl);
6264 	mtx_unlock(&sc->sfl_lock);
6265 }
6266 
6267 static void
6268 handle_wrq_egr_update(struct adapter *sc, struct sge_eq *eq)
6269 {
6270 	struct sge_wrq *wrq = (void *)eq;
6271 
6272 	atomic_readandclear_int(&eq->equiq);
6273 	taskqueue_enqueue(sc->tq[eq->tx_chan], &wrq->wrq_tx_task);
6274 }
6275 
6276 static void
6277 handle_eth_egr_update(struct adapter *sc, struct sge_eq *eq)
6278 {
6279 	struct sge_txq *txq = (void *)eq;
6280 
6281 	MPASS(eq->type == EQ_ETH);
6282 
6283 	atomic_readandclear_int(&eq->equiq);
6284 	if (mp_ring_is_idle(txq->r))
6285 		taskqueue_enqueue(sc->tq[eq->tx_chan], &txq->tx_reclaim_task);
6286 	else
6287 		mp_ring_check_drainage(txq->r, 64);
6288 }
6289 
6290 static int
6291 handle_sge_egr_update(struct sge_iq *iq, const struct rss_header *rss,
6292     struct mbuf *m)
6293 {
6294 	const struct cpl_sge_egr_update *cpl = (const void *)(rss + 1);
6295 	unsigned int qid = G_EGR_QID(ntohl(cpl->opcode_qid));
6296 	struct adapter *sc = iq->adapter;
6297 	struct sge *s = &sc->sge;
6298 	struct sge_eq *eq;
6299 	static void (*h[])(struct adapter *, struct sge_eq *) = {NULL,
6300 		&handle_wrq_egr_update, &handle_eth_egr_update,
6301 		&handle_wrq_egr_update};
6302 
6303 	KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
6304 	    rss->opcode));
6305 
6306 	eq = s->eqmap[qid - s->eq_start - s->eq_base];
6307 	(*h[eq->type])(sc, eq);
6308 
6309 	return (0);
6310 }
6311 
6312 /* handle_fw_msg works for both fw4_msg and fw6_msg because this is valid */
6313 CTASSERT(offsetof(struct cpl_fw4_msg, data) == \
6314     offsetof(struct cpl_fw6_msg, data));
6315 
6316 static int
6317 handle_fw_msg(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
6318 {
6319 	struct adapter *sc = iq->adapter;
6320 	const struct cpl_fw6_msg *cpl = (const void *)(rss + 1);
6321 
6322 	KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
6323 	    rss->opcode));
6324 
6325 	if (cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL) {
6326 		const struct rss_header *rss2;
6327 
6328 		rss2 = (const struct rss_header *)&cpl->data[0];
6329 		return (t4_cpl_handler[rss2->opcode](iq, rss2, m));
6330 	}
6331 
6332 	return (t4_fw_msg_handler[cpl->type](sc, &cpl->data[0]));
6333 }
6334 
6335 /**
6336  *	t4_handle_wrerr_rpl - process a FW work request error message
6337  *	@adap: the adapter
6338  *	@rpl: start of the FW message
6339  */
6340 static int
6341 t4_handle_wrerr_rpl(struct adapter *adap, const __be64 *rpl)
6342 {
6343 	u8 opcode = *(const u8 *)rpl;
6344 	const struct fw_error_cmd *e = (const void *)rpl;
6345 	unsigned int i;
6346 
6347 	if (opcode != FW_ERROR_CMD) {
6348 		log(LOG_ERR,
6349 		    "%s: Received WRERR_RPL message with opcode %#x\n",
6350 		    device_get_nameunit(adap->dev), opcode);
6351 		return (EINVAL);
6352 	}
6353 	log(LOG_ERR, "%s: FW_ERROR (%s) ", device_get_nameunit(adap->dev),
6354 	    G_FW_ERROR_CMD_FATAL(be32toh(e->op_to_type)) ? "fatal" :
6355 	    "non-fatal");
6356 	switch (G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type))) {
6357 	case FW_ERROR_TYPE_EXCEPTION:
6358 		log(LOG_ERR, "exception info:\n");
6359 		for (i = 0; i < nitems(e->u.exception.info); i++)
6360 			log(LOG_ERR, "%s%08x", i == 0 ? "\t" : " ",
6361 			    be32toh(e->u.exception.info[i]));
6362 		log(LOG_ERR, "\n");
6363 		break;
6364 	case FW_ERROR_TYPE_HWMODULE:
6365 		log(LOG_ERR, "HW module regaddr %08x regval %08x\n",
6366 		    be32toh(e->u.hwmodule.regaddr),
6367 		    be32toh(e->u.hwmodule.regval));
6368 		break;
6369 	case FW_ERROR_TYPE_WR:
6370 		log(LOG_ERR, "WR cidx %d PF %d VF %d eqid %d hdr:\n",
6371 		    be16toh(e->u.wr.cidx),
6372 		    G_FW_ERROR_CMD_PFN(be16toh(e->u.wr.pfn_vfn)),
6373 		    G_FW_ERROR_CMD_VFN(be16toh(e->u.wr.pfn_vfn)),
6374 		    be32toh(e->u.wr.eqid));
6375 		for (i = 0; i < nitems(e->u.wr.wrhdr); i++)
6376 			log(LOG_ERR, "%s%02x", i == 0 ? "\t" : " ",
6377 			    e->u.wr.wrhdr[i]);
6378 		log(LOG_ERR, "\n");
6379 		break;
6380 	case FW_ERROR_TYPE_ACL:
6381 		log(LOG_ERR, "ACL cidx %d PF %d VF %d eqid %d %s",
6382 		    be16toh(e->u.acl.cidx),
6383 		    G_FW_ERROR_CMD_PFN(be16toh(e->u.acl.pfn_vfn)),
6384 		    G_FW_ERROR_CMD_VFN(be16toh(e->u.acl.pfn_vfn)),
6385 		    be32toh(e->u.acl.eqid),
6386 		    G_FW_ERROR_CMD_MV(be16toh(e->u.acl.mv_pkd)) ? "vlanid" :
6387 		    "MAC");
6388 		for (i = 0; i < nitems(e->u.acl.val); i++)
6389 			log(LOG_ERR, " %02x", e->u.acl.val[i]);
6390 		log(LOG_ERR, "\n");
6391 		break;
6392 	default:
6393 		log(LOG_ERR, "type %#x\n",
6394 		    G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type)));
6395 		return (EINVAL);
6396 	}
6397 	return (0);
6398 }
6399 
6400 static inline bool
6401 bufidx_used(struct adapter *sc, int idx)
6402 {
6403 	struct rx_buf_info *rxb = &sc->sge.rx_buf_info[0];
6404 	int i;
6405 
6406 	for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) {
6407 		if (rxb->size1 > largest_rx_cluster)
6408 			continue;
6409 		if (rxb->hwidx1 == idx || rxb->hwidx2 == idx)
6410 			return (true);
6411 	}
6412 
6413 	return (false);
6414 }
6415 
6416 static int
6417 sysctl_bufsizes(SYSCTL_HANDLER_ARGS)
6418 {
6419 	struct adapter *sc = arg1;
6420 	struct sge_params *sp = &sc->params.sge;
6421 	int i, rc;
6422 	struct sbuf sb;
6423 	char c;
6424 
6425 	sbuf_new(&sb, NULL, 128, SBUF_AUTOEXTEND);
6426 	for (i = 0; i < SGE_FLBUF_SIZES; i++) {
6427 		if (bufidx_used(sc, i))
6428 			c = '*';
6429 		else
6430 			c = '\0';
6431 
6432 		sbuf_printf(&sb, "%u%c ", sp->sge_fl_buffer_size[i], c);
6433 	}
6434 	sbuf_trim(&sb);
6435 	sbuf_finish(&sb);
6436 	rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req);
6437 	sbuf_delete(&sb);
6438 	return (rc);
6439 }
6440 
6441 #ifdef RATELIMIT
6442 #if defined(INET) || defined(INET6)
6443 /*
6444  * len16 for a txpkt WR with a GL.  Includes the firmware work request header.
6445  */
6446 static inline u_int
6447 txpkt_eo_len16(u_int nsegs, u_int immhdrs, u_int tso)
6448 {
6449 	u_int n;
6450 
6451 	MPASS(immhdrs > 0);
6452 
6453 	n = roundup2(sizeof(struct fw_eth_tx_eo_wr) +
6454 	    sizeof(struct cpl_tx_pkt_core) + immhdrs, 16);
6455 	if (__predict_false(nsegs == 0))
6456 		goto done;
6457 
6458 	nsegs--; /* first segment is part of ulptx_sgl */
6459 	n += sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1));
6460 	if (tso)
6461 		n += sizeof(struct cpl_tx_pkt_lso_core);
6462 
6463 done:
6464 	return (howmany(n, 16));
6465 }
6466 #endif
6467 
6468 #define ETID_FLOWC_NPARAMS 6
6469 #define ETID_FLOWC_LEN (roundup2((sizeof(struct fw_flowc_wr) + \
6470     ETID_FLOWC_NPARAMS * sizeof(struct fw_flowc_mnemval)), 16))
6471 #define ETID_FLOWC_LEN16 (howmany(ETID_FLOWC_LEN, 16))
6472 
6473 static int
6474 send_etid_flowc_wr(struct cxgbe_rate_tag *cst, struct port_info *pi,
6475     struct vi_info *vi)
6476 {
6477 	struct wrq_cookie cookie;
6478 	u_int pfvf = pi->adapter->pf << S_FW_VIID_PFN;
6479 	struct fw_flowc_wr *flowc;
6480 
6481 	mtx_assert(&cst->lock, MA_OWNED);
6482 	MPASS((cst->flags & (EO_FLOWC_PENDING | EO_FLOWC_RPL_PENDING)) ==
6483 	    EO_FLOWC_PENDING);
6484 
6485 	flowc = start_wrq_wr(&cst->eo_txq->wrq, ETID_FLOWC_LEN16, &cookie);
6486 	if (__predict_false(flowc == NULL))
6487 		return (ENOMEM);
6488 
6489 	bzero(flowc, ETID_FLOWC_LEN);
6490 	flowc->op_to_nparams = htobe32(V_FW_WR_OP(FW_FLOWC_WR) |
6491 	    V_FW_FLOWC_WR_NPARAMS(ETID_FLOWC_NPARAMS) | V_FW_WR_COMPL(0));
6492 	flowc->flowid_len16 = htonl(V_FW_WR_LEN16(ETID_FLOWC_LEN16) |
6493 	    V_FW_WR_FLOWID(cst->etid));
6494 	flowc->mnemval[0].mnemonic = FW_FLOWC_MNEM_PFNVFN;
6495 	flowc->mnemval[0].val = htobe32(pfvf);
6496 	flowc->mnemval[1].mnemonic = FW_FLOWC_MNEM_CH;
6497 	flowc->mnemval[1].val = htobe32(pi->tx_chan);
6498 	flowc->mnemval[2].mnemonic = FW_FLOWC_MNEM_PORT;
6499 	flowc->mnemval[2].val = htobe32(pi->tx_chan);
6500 	flowc->mnemval[3].mnemonic = FW_FLOWC_MNEM_IQID;
6501 	flowc->mnemval[3].val = htobe32(cst->iqid);
6502 	flowc->mnemval[4].mnemonic = FW_FLOWC_MNEM_EOSTATE;
6503 	flowc->mnemval[4].val = htobe32(FW_FLOWC_MNEM_EOSTATE_ESTABLISHED);
6504 	flowc->mnemval[5].mnemonic = FW_FLOWC_MNEM_SCHEDCLASS;
6505 	flowc->mnemval[5].val = htobe32(cst->schedcl);
6506 
6507 	commit_wrq_wr(&cst->eo_txq->wrq, flowc, &cookie);
6508 
6509 	cst->flags &= ~EO_FLOWC_PENDING;
6510 	cst->flags |= EO_FLOWC_RPL_PENDING;
6511 	MPASS(cst->tx_credits >= ETID_FLOWC_LEN16);	/* flowc is first WR. */
6512 	cst->tx_credits -= ETID_FLOWC_LEN16;
6513 
6514 	return (0);
6515 }
6516 
6517 #define ETID_FLUSH_LEN16 (howmany(sizeof (struct fw_flowc_wr), 16))
6518 
6519 void
6520 send_etid_flush_wr(struct cxgbe_rate_tag *cst)
6521 {
6522 	struct fw_flowc_wr *flowc;
6523 	struct wrq_cookie cookie;
6524 
6525 	mtx_assert(&cst->lock, MA_OWNED);
6526 
6527 	flowc = start_wrq_wr(&cst->eo_txq->wrq, ETID_FLUSH_LEN16, &cookie);
6528 	if (__predict_false(flowc == NULL))
6529 		CXGBE_UNIMPLEMENTED(__func__);
6530 
6531 	bzero(flowc, ETID_FLUSH_LEN16 * 16);
6532 	flowc->op_to_nparams = htobe32(V_FW_WR_OP(FW_FLOWC_WR) |
6533 	    V_FW_FLOWC_WR_NPARAMS(0) | F_FW_WR_COMPL);
6534 	flowc->flowid_len16 = htobe32(V_FW_WR_LEN16(ETID_FLUSH_LEN16) |
6535 	    V_FW_WR_FLOWID(cst->etid));
6536 
6537 	commit_wrq_wr(&cst->eo_txq->wrq, flowc, &cookie);
6538 
6539 	cst->flags |= EO_FLUSH_RPL_PENDING;
6540 	MPASS(cst->tx_credits >= ETID_FLUSH_LEN16);
6541 	cst->tx_credits -= ETID_FLUSH_LEN16;
6542 	cst->ncompl++;
6543 }
6544 
6545 static void
6546 write_ethofld_wr(struct cxgbe_rate_tag *cst, struct fw_eth_tx_eo_wr *wr,
6547     struct mbuf *m0, int compl)
6548 {
6549 	struct cpl_tx_pkt_core *cpl;
6550 	uint64_t ctrl1;
6551 	uint32_t ctrl;	/* used in many unrelated places */
6552 	int len16, pktlen, nsegs, immhdrs;
6553 	caddr_t dst;
6554 	uintptr_t p;
6555 	struct ulptx_sgl *usgl;
6556 	struct sglist sg;
6557 	struct sglist_seg segs[38];	/* XXX: find real limit.  XXX: get off the stack */
6558 
6559 	mtx_assert(&cst->lock, MA_OWNED);
6560 	M_ASSERTPKTHDR(m0);
6561 	KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 &&
6562 	    m0->m_pkthdr.l4hlen > 0,
6563 	    ("%s: ethofld mbuf %p is missing header lengths", __func__, m0));
6564 
6565 	len16 = mbuf_eo_len16(m0);
6566 	nsegs = mbuf_eo_nsegs(m0);
6567 	pktlen = m0->m_pkthdr.len;
6568 	ctrl = sizeof(struct cpl_tx_pkt_core);
6569 	if (needs_tso(m0))
6570 		ctrl += sizeof(struct cpl_tx_pkt_lso_core);
6571 	immhdrs = m0->m_pkthdr.l2hlen + m0->m_pkthdr.l3hlen + m0->m_pkthdr.l4hlen;
6572 	ctrl += immhdrs;
6573 
6574 	wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_EO_WR) |
6575 	    V_FW_ETH_TX_EO_WR_IMMDLEN(ctrl) | V_FW_WR_COMPL(!!compl));
6576 	wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(len16) |
6577 	    V_FW_WR_FLOWID(cst->etid));
6578 	wr->r3 = 0;
6579 	if (needs_outer_udp_csum(m0)) {
6580 		wr->u.udpseg.type = FW_ETH_TX_EO_TYPE_UDPSEG;
6581 		wr->u.udpseg.ethlen = m0->m_pkthdr.l2hlen;
6582 		wr->u.udpseg.iplen = htobe16(m0->m_pkthdr.l3hlen);
6583 		wr->u.udpseg.udplen = m0->m_pkthdr.l4hlen;
6584 		wr->u.udpseg.rtplen = 0;
6585 		wr->u.udpseg.r4 = 0;
6586 		wr->u.udpseg.mss = htobe16(pktlen - immhdrs);
6587 		wr->u.udpseg.schedpktsize = wr->u.udpseg.mss;
6588 		wr->u.udpseg.plen = htobe32(pktlen - immhdrs);
6589 		cpl = (void *)(wr + 1);
6590 	} else {
6591 		MPASS(needs_outer_tcp_csum(m0));
6592 		wr->u.tcpseg.type = FW_ETH_TX_EO_TYPE_TCPSEG;
6593 		wr->u.tcpseg.ethlen = m0->m_pkthdr.l2hlen;
6594 		wr->u.tcpseg.iplen = htobe16(m0->m_pkthdr.l3hlen);
6595 		wr->u.tcpseg.tcplen = m0->m_pkthdr.l4hlen;
6596 		wr->u.tcpseg.tsclk_tsoff = mbuf_eo_tsclk_tsoff(m0);
6597 		wr->u.tcpseg.r4 = 0;
6598 		wr->u.tcpseg.r5 = 0;
6599 		wr->u.tcpseg.plen = htobe32(pktlen - immhdrs);
6600 
6601 		if (needs_tso(m0)) {
6602 			struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1);
6603 
6604 			wr->u.tcpseg.mss = htobe16(m0->m_pkthdr.tso_segsz);
6605 
6606 			ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) |
6607 			    F_LSO_FIRST_SLICE | F_LSO_LAST_SLICE |
6608 			    V_LSO_ETHHDR_LEN((m0->m_pkthdr.l2hlen -
6609 				ETHER_HDR_LEN) >> 2) |
6610 			    V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) |
6611 			    V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2);
6612 			if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr))
6613 				ctrl |= F_LSO_IPV6;
6614 			lso->lso_ctrl = htobe32(ctrl);
6615 			lso->ipid_ofst = htobe16(0);
6616 			lso->mss = htobe16(m0->m_pkthdr.tso_segsz);
6617 			lso->seqno_offset = htobe32(0);
6618 			lso->len = htobe32(pktlen);
6619 
6620 			cpl = (void *)(lso + 1);
6621 		} else {
6622 			wr->u.tcpseg.mss = htobe16(0xffff);
6623 			cpl = (void *)(wr + 1);
6624 		}
6625 	}
6626 
6627 	/* Checksum offload must be requested for ethofld. */
6628 	MPASS(needs_outer_l4_csum(m0));
6629 	ctrl1 = csum_to_ctrl(cst->adapter, m0);
6630 
6631 	/* VLAN tag insertion */
6632 	if (needs_vlan_insertion(m0)) {
6633 		ctrl1 |= F_TXPKT_VLAN_VLD |
6634 		    V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag);
6635 	}
6636 
6637 	/* CPL header */
6638 	cpl->ctrl0 = cst->ctrl0;
6639 	cpl->pack = 0;
6640 	cpl->len = htobe16(pktlen);
6641 	cpl->ctrl1 = htobe64(ctrl1);
6642 
6643 	/* Copy Ethernet, IP & TCP/UDP hdrs as immediate data */
6644 	p = (uintptr_t)(cpl + 1);
6645 	m_copydata(m0, 0, immhdrs, (void *)p);
6646 
6647 	/* SGL */
6648 	dst = (void *)(cpl + 1);
6649 	if (nsegs > 0) {
6650 		int i, pad;
6651 
6652 		/* zero-pad upto next 16Byte boundary, if not 16Byte aligned */
6653 		p += immhdrs;
6654 		pad = 16 - (immhdrs & 0xf);
6655 		bzero((void *)p, pad);
6656 
6657 		usgl = (void *)(p + pad);
6658 		usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) |
6659 		    V_ULPTX_NSGE(nsegs));
6660 
6661 		sglist_init(&sg, nitems(segs), segs);
6662 		for (; m0 != NULL; m0 = m0->m_next) {
6663 			if (__predict_false(m0->m_len == 0))
6664 				continue;
6665 			if (immhdrs >= m0->m_len) {
6666 				immhdrs -= m0->m_len;
6667 				continue;
6668 			}
6669 			if (m0->m_flags & M_EXTPG)
6670 				sglist_append_mbuf_epg(&sg, m0,
6671 				    mtod(m0, vm_offset_t), m0->m_len);
6672                         else
6673 				sglist_append(&sg, mtod(m0, char *) + immhdrs,
6674 				    m0->m_len - immhdrs);
6675 			immhdrs = 0;
6676 		}
6677 		MPASS(sg.sg_nseg == nsegs);
6678 
6679 		/*
6680 		 * Zero pad last 8B in case the WR doesn't end on a 16B
6681 		 * boundary.
6682 		 */
6683 		*(uint64_t *)((char *)wr + len16 * 16 - 8) = 0;
6684 
6685 		usgl->len0 = htobe32(segs[0].ss_len);
6686 		usgl->addr0 = htobe64(segs[0].ss_paddr);
6687 		for (i = 0; i < nsegs - 1; i++) {
6688 			usgl->sge[i / 2].len[i & 1] = htobe32(segs[i + 1].ss_len);
6689 			usgl->sge[i / 2].addr[i & 1] = htobe64(segs[i + 1].ss_paddr);
6690 		}
6691 		if (i & 1)
6692 			usgl->sge[i / 2].len[1] = htobe32(0);
6693 	}
6694 
6695 }
6696 
6697 static void
6698 ethofld_tx(struct cxgbe_rate_tag *cst)
6699 {
6700 	struct mbuf *m;
6701 	struct wrq_cookie cookie;
6702 	int next_credits, compl;
6703 	struct fw_eth_tx_eo_wr *wr;
6704 
6705 	mtx_assert(&cst->lock, MA_OWNED);
6706 
6707 	while ((m = mbufq_first(&cst->pending_tx)) != NULL) {
6708 		M_ASSERTPKTHDR(m);
6709 
6710 		/* How many len16 credits do we need to send this mbuf. */
6711 		next_credits = mbuf_eo_len16(m);
6712 		MPASS(next_credits > 0);
6713 		if (next_credits > cst->tx_credits) {
6714 			/*
6715 			 * Tx will make progress eventually because there is at
6716 			 * least one outstanding fw4_ack that will return
6717 			 * credits and kick the tx.
6718 			 */
6719 			MPASS(cst->ncompl > 0);
6720 			return;
6721 		}
6722 		wr = start_wrq_wr(&cst->eo_txq->wrq, next_credits, &cookie);
6723 		if (__predict_false(wr == NULL)) {
6724 			/* XXX: wishful thinking, not a real assertion. */
6725 			MPASS(cst->ncompl > 0);
6726 			return;
6727 		}
6728 		cst->tx_credits -= next_credits;
6729 		cst->tx_nocompl += next_credits;
6730 		compl = cst->ncompl == 0 || cst->tx_nocompl >= cst->tx_total / 2;
6731 		ETHER_BPF_MTAP(cst->com.ifp, m);
6732 		write_ethofld_wr(cst, wr, m, compl);
6733 		commit_wrq_wr(&cst->eo_txq->wrq, wr, &cookie);
6734 		if (compl) {
6735 			cst->ncompl++;
6736 			cst->tx_nocompl	= 0;
6737 		}
6738 		(void) mbufq_dequeue(&cst->pending_tx);
6739 
6740 		/*
6741 		 * Drop the mbuf's reference on the tag now rather
6742 		 * than waiting until m_freem().  This ensures that
6743 		 * cxgbe_rate_tag_free gets called when the inp drops
6744 		 * its reference on the tag and there are no more
6745 		 * mbufs in the pending_tx queue and can flush any
6746 		 * pending requests.  Otherwise if the last mbuf
6747 		 * doesn't request a completion the etid will never be
6748 		 * released.
6749 		 */
6750 		m->m_pkthdr.snd_tag = NULL;
6751 		m->m_pkthdr.csum_flags &= ~CSUM_SND_TAG;
6752 		m_snd_tag_rele(&cst->com);
6753 
6754 		mbufq_enqueue(&cst->pending_fwack, m);
6755 	}
6756 }
6757 
6758 int
6759 ethofld_transmit(struct ifnet *ifp, struct mbuf *m0)
6760 {
6761 	struct cxgbe_rate_tag *cst;
6762 	int rc;
6763 
6764 	MPASS(m0->m_nextpkt == NULL);
6765 	MPASS(m0->m_pkthdr.csum_flags & CSUM_SND_TAG);
6766 	MPASS(m0->m_pkthdr.snd_tag != NULL);
6767 	cst = mst_to_crt(m0->m_pkthdr.snd_tag);
6768 
6769 	mtx_lock(&cst->lock);
6770 	MPASS(cst->flags & EO_SND_TAG_REF);
6771 
6772 	if (__predict_false(cst->flags & EO_FLOWC_PENDING)) {
6773 		struct vi_info *vi = ifp->if_softc;
6774 		struct port_info *pi = vi->pi;
6775 		struct adapter *sc = pi->adapter;
6776 		const uint32_t rss_mask = vi->rss_size - 1;
6777 		uint32_t rss_hash;
6778 
6779 		cst->eo_txq = &sc->sge.ofld_txq[vi->first_ofld_txq];
6780 		if (M_HASHTYPE_ISHASH(m0))
6781 			rss_hash = m0->m_pkthdr.flowid;
6782 		else
6783 			rss_hash = arc4random();
6784 		/* We assume RSS hashing */
6785 		cst->iqid = vi->rss[rss_hash & rss_mask];
6786 		cst->eo_txq += rss_hash % vi->nofldtxq;
6787 		rc = send_etid_flowc_wr(cst, pi, vi);
6788 		if (rc != 0)
6789 			goto done;
6790 	}
6791 
6792 	if (__predict_false(cst->plen + m0->m_pkthdr.len > eo_max_backlog)) {
6793 		rc = ENOBUFS;
6794 		goto done;
6795 	}
6796 
6797 	mbufq_enqueue(&cst->pending_tx, m0);
6798 	cst->plen += m0->m_pkthdr.len;
6799 
6800 	/*
6801 	 * Hold an extra reference on the tag while generating work
6802 	 * requests to ensure that we don't try to free the tag during
6803 	 * ethofld_tx() in case we are sending the final mbuf after
6804 	 * the inp was freed.
6805 	 */
6806 	m_snd_tag_ref(&cst->com);
6807 	ethofld_tx(cst);
6808 	mtx_unlock(&cst->lock);
6809 	m_snd_tag_rele(&cst->com);
6810 	return (0);
6811 
6812 done:
6813 	mtx_unlock(&cst->lock);
6814 	if (__predict_false(rc != 0))
6815 		m_freem(m0);
6816 	return (rc);
6817 }
6818 
6819 static int
6820 ethofld_fw4_ack(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0)
6821 {
6822 	struct adapter *sc = iq->adapter;
6823 	const struct cpl_fw4_ack *cpl = (const void *)(rss + 1);
6824 	struct mbuf *m;
6825 	u_int etid = G_CPL_FW4_ACK_FLOWID(be32toh(OPCODE_TID(cpl)));
6826 	struct cxgbe_rate_tag *cst;
6827 	uint8_t credits = cpl->credits;
6828 
6829 	cst = lookup_etid(sc, etid);
6830 	mtx_lock(&cst->lock);
6831 	if (__predict_false(cst->flags & EO_FLOWC_RPL_PENDING)) {
6832 		MPASS(credits >= ETID_FLOWC_LEN16);
6833 		credits -= ETID_FLOWC_LEN16;
6834 		cst->flags &= ~EO_FLOWC_RPL_PENDING;
6835 	}
6836 
6837 	KASSERT(cst->ncompl > 0,
6838 	    ("%s: etid %u (%p) wasn't expecting completion.",
6839 	    __func__, etid, cst));
6840 	cst->ncompl--;
6841 
6842 	while (credits > 0) {
6843 		m = mbufq_dequeue(&cst->pending_fwack);
6844 		if (__predict_false(m == NULL)) {
6845 			/*
6846 			 * The remaining credits are for the final flush that
6847 			 * was issued when the tag was freed by the kernel.
6848 			 */
6849 			MPASS((cst->flags &
6850 			    (EO_FLUSH_RPL_PENDING | EO_SND_TAG_REF)) ==
6851 			    EO_FLUSH_RPL_PENDING);
6852 			MPASS(credits == ETID_FLUSH_LEN16);
6853 			MPASS(cst->tx_credits + cpl->credits == cst->tx_total);
6854 			MPASS(cst->ncompl == 0);
6855 
6856 			cst->flags &= ~EO_FLUSH_RPL_PENDING;
6857 			cst->tx_credits += cpl->credits;
6858 			cxgbe_rate_tag_free_locked(cst);
6859 			return (0);	/* cst is gone. */
6860 		}
6861 		KASSERT(m != NULL,
6862 		    ("%s: too many credits (%u, %u)", __func__, cpl->credits,
6863 		    credits));
6864 		KASSERT(credits >= mbuf_eo_len16(m),
6865 		    ("%s: too few credits (%u, %u, %u)", __func__,
6866 		    cpl->credits, credits, mbuf_eo_len16(m)));
6867 		credits -= mbuf_eo_len16(m);
6868 		cst->plen -= m->m_pkthdr.len;
6869 		m_freem(m);
6870 	}
6871 
6872 	cst->tx_credits += cpl->credits;
6873 	MPASS(cst->tx_credits <= cst->tx_total);
6874 
6875 	if (cst->flags & EO_SND_TAG_REF) {
6876 		/*
6877 		 * As with ethofld_transmit(), hold an extra reference
6878 		 * so that the tag is stable across ethold_tx().
6879 		 */
6880 		m_snd_tag_ref(&cst->com);
6881 		m = mbufq_first(&cst->pending_tx);
6882 		if (m != NULL && cst->tx_credits >= mbuf_eo_len16(m))
6883 			ethofld_tx(cst);
6884 		mtx_unlock(&cst->lock);
6885 		m_snd_tag_rele(&cst->com);
6886 	} else {
6887 		/*
6888 		 * There shouldn't be any pending packets if the tag
6889 		 * was freed by the kernel since any pending packet
6890 		 * should hold a reference to the tag.
6891 		 */
6892 		MPASS(mbufq_first(&cst->pending_tx) == NULL);
6893 		mtx_unlock(&cst->lock);
6894 	}
6895 
6896 	return (0);
6897 }
6898 #endif
6899