1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 Chelsio Communications, Inc. 5 * All rights reserved. 6 * Written by: Navdeep Parhar <np@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include "opt_inet.h" 34 #include "opt_inet6.h" 35 #include "opt_kern_tls.h" 36 #include "opt_ratelimit.h" 37 38 #include <sys/types.h> 39 #include <sys/eventhandler.h> 40 #include <sys/mbuf.h> 41 #include <sys/socket.h> 42 #include <sys/kernel.h> 43 #include <sys/ktls.h> 44 #include <sys/malloc.h> 45 #include <sys/msan.h> 46 #include <sys/queue.h> 47 #include <sys/sbuf.h> 48 #include <sys/taskqueue.h> 49 #include <sys/time.h> 50 #include <sys/sglist.h> 51 #include <sys/sysctl.h> 52 #include <sys/smp.h> 53 #include <sys/socketvar.h> 54 #include <sys/counter.h> 55 #include <net/bpf.h> 56 #include <net/ethernet.h> 57 #include <net/if.h> 58 #include <net/if_vlan_var.h> 59 #include <net/if_vxlan.h> 60 #include <netinet/in.h> 61 #include <netinet/ip.h> 62 #include <netinet/ip6.h> 63 #include <netinet/tcp.h> 64 #include <netinet/udp.h> 65 #include <machine/in_cksum.h> 66 #include <machine/md_var.h> 67 #include <vm/vm.h> 68 #include <vm/pmap.h> 69 #ifdef DEV_NETMAP 70 #include <machine/bus.h> 71 #include <sys/selinfo.h> 72 #include <net/if_var.h> 73 #include <net/netmap.h> 74 #include <dev/netmap/netmap_kern.h> 75 #endif 76 77 #include "common/common.h" 78 #include "common/t4_regs.h" 79 #include "common/t4_regs_values.h" 80 #include "common/t4_msg.h" 81 #include "t4_l2t.h" 82 #include "t4_mp_ring.h" 83 84 #ifdef T4_PKT_TIMESTAMP 85 #define RX_COPY_THRESHOLD (MINCLSIZE - 8) 86 #else 87 #define RX_COPY_THRESHOLD MINCLSIZE 88 #endif 89 90 /* Internal mbuf flags stored in PH_loc.eight[1]. */ 91 #define MC_NOMAP 0x01 92 #define MC_RAW_WR 0x02 93 #define MC_TLS 0x04 94 95 /* 96 * Ethernet frames are DMA'd at this byte offset into the freelist buffer. 97 * 0-7 are valid values. 98 */ 99 static int fl_pktshift = 0; 100 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pktshift, CTLFLAG_RDTUN, &fl_pktshift, 0, 101 "payload DMA offset in rx buffer (bytes)"); 102 103 /* 104 * Pad ethernet payload up to this boundary. 105 * -1: driver should figure out a good value. 106 * 0: disable padding. 107 * Any power of 2 from 32 to 4096 (both inclusive) is also a valid value. 108 */ 109 int fl_pad = -1; 110 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pad, CTLFLAG_RDTUN, &fl_pad, 0, 111 "payload pad boundary (bytes)"); 112 113 /* 114 * Status page length. 115 * -1: driver should figure out a good value. 116 * 64 or 128 are the only other valid values. 117 */ 118 static int spg_len = -1; 119 SYSCTL_INT(_hw_cxgbe, OID_AUTO, spg_len, CTLFLAG_RDTUN, &spg_len, 0, 120 "status page size (bytes)"); 121 122 /* 123 * Congestion drops. 124 * -1: no congestion feedback (not recommended). 125 * 0: backpressure the channel instead of dropping packets right away. 126 * 1: no backpressure, drop packets for the congested queue immediately. 127 * 2: both backpressure and drop. 128 */ 129 static int cong_drop = 0; 130 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cong_drop, CTLFLAG_RDTUN, &cong_drop, 0, 131 "Congestion control for NIC RX queues (0 = backpressure, 1 = drop, 2 = both"); 132 #ifdef TCP_OFFLOAD 133 static int ofld_cong_drop = 0; 134 SYSCTL_INT(_hw_cxgbe, OID_AUTO, ofld_cong_drop, CTLFLAG_RDTUN, &ofld_cong_drop, 0, 135 "Congestion control for TOE RX queues (0 = backpressure, 1 = drop, 2 = both"); 136 #endif 137 138 /* 139 * Deliver multiple frames in the same free list buffer if they fit. 140 * -1: let the driver decide whether to enable buffer packing or not. 141 * 0: disable buffer packing. 142 * 1: enable buffer packing. 143 */ 144 static int buffer_packing = -1; 145 SYSCTL_INT(_hw_cxgbe, OID_AUTO, buffer_packing, CTLFLAG_RDTUN, &buffer_packing, 146 0, "Enable buffer packing"); 147 148 /* 149 * Start next frame in a packed buffer at this boundary. 150 * -1: driver should figure out a good value. 151 * T4: driver will ignore this and use the same value as fl_pad above. 152 * T5: 16, or a power of 2 from 64 to 4096 (both inclusive) is a valid value. 153 */ 154 static int fl_pack = -1; 155 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pack, CTLFLAG_RDTUN, &fl_pack, 0, 156 "payload pack boundary (bytes)"); 157 158 /* 159 * Largest rx cluster size that the driver is allowed to allocate. 160 */ 161 static int largest_rx_cluster = MJUM16BYTES; 162 SYSCTL_INT(_hw_cxgbe, OID_AUTO, largest_rx_cluster, CTLFLAG_RDTUN, 163 &largest_rx_cluster, 0, "Largest rx cluster (bytes)"); 164 165 /* 166 * Size of cluster allocation that's most likely to succeed. The driver will 167 * fall back to this size if it fails to allocate clusters larger than this. 168 */ 169 static int safest_rx_cluster = PAGE_SIZE; 170 SYSCTL_INT(_hw_cxgbe, OID_AUTO, safest_rx_cluster, CTLFLAG_RDTUN, 171 &safest_rx_cluster, 0, "Safe rx cluster (bytes)"); 172 173 #ifdef RATELIMIT 174 /* 175 * Knob to control TCP timestamp rewriting, and the granularity of the tick used 176 * for rewriting. -1 and 0-3 are all valid values. 177 * -1: hardware should leave the TCP timestamps alone. 178 * 0: 1ms 179 * 1: 100us 180 * 2: 10us 181 * 3: 1us 182 */ 183 static int tsclk = -1; 184 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tsclk, CTLFLAG_RDTUN, &tsclk, 0, 185 "Control TCP timestamp rewriting when using pacing"); 186 187 static int eo_max_backlog = 1024 * 1024; 188 SYSCTL_INT(_hw_cxgbe, OID_AUTO, eo_max_backlog, CTLFLAG_RDTUN, &eo_max_backlog, 189 0, "Maximum backlog of ratelimited data per flow"); 190 #endif 191 192 /* 193 * The interrupt holdoff timers are multiplied by this value on T6+. 194 * 1 and 3-17 (both inclusive) are legal values. 195 */ 196 static int tscale = 1; 197 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tscale, CTLFLAG_RDTUN, &tscale, 0, 198 "Interrupt holdoff timer scale on T6+"); 199 200 /* 201 * Number of LRO entries in the lro_ctrl structure per rx queue. 202 */ 203 static int lro_entries = TCP_LRO_ENTRIES; 204 SYSCTL_INT(_hw_cxgbe, OID_AUTO, lro_entries, CTLFLAG_RDTUN, &lro_entries, 0, 205 "Number of LRO entries per RX queue"); 206 207 /* 208 * This enables presorting of frames before they're fed into tcp_lro_rx. 209 */ 210 static int lro_mbufs = 0; 211 SYSCTL_INT(_hw_cxgbe, OID_AUTO, lro_mbufs, CTLFLAG_RDTUN, &lro_mbufs, 0, 212 "Enable presorting of LRO frames"); 213 214 static counter_u64_t pullups; 215 SYSCTL_COUNTER_U64(_hw_cxgbe, OID_AUTO, pullups, CTLFLAG_RD, &pullups, 216 "Number of mbuf pullups performed"); 217 218 static counter_u64_t defrags; 219 SYSCTL_COUNTER_U64(_hw_cxgbe, OID_AUTO, defrags, CTLFLAG_RD, &defrags, 220 "Number of mbuf defrags performed"); 221 222 static int t4_tx_coalesce = 1; 223 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tx_coalesce, CTLFLAG_RWTUN, &t4_tx_coalesce, 0, 224 "tx coalescing allowed"); 225 226 /* 227 * The driver will make aggressive attempts at tx coalescing if it sees these 228 * many packets eligible for coalescing in quick succession, with no more than 229 * the specified gap in between the eth_tx calls that delivered the packets. 230 */ 231 static int t4_tx_coalesce_pkts = 32; 232 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tx_coalesce_pkts, CTLFLAG_RWTUN, 233 &t4_tx_coalesce_pkts, 0, 234 "# of consecutive packets (1 - 255) that will trigger tx coalescing"); 235 static int t4_tx_coalesce_gap = 5; 236 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tx_coalesce_gap, CTLFLAG_RWTUN, 237 &t4_tx_coalesce_gap, 0, "tx gap (in microseconds)"); 238 239 static int service_iq(struct sge_iq *, int); 240 static int service_iq_fl(struct sge_iq *, int); 241 static struct mbuf *get_fl_payload(struct adapter *, struct sge_fl *, uint32_t); 242 static int eth_rx(struct adapter *, struct sge_rxq *, const struct iq_desc *, 243 u_int); 244 static inline void init_iq(struct sge_iq *, struct adapter *, int, int, int, 245 int, int, int); 246 static inline void init_fl(struct adapter *, struct sge_fl *, int, int, char *); 247 static inline void init_eq(struct adapter *, struct sge_eq *, int, int, uint8_t, 248 struct sge_iq *, char *); 249 static int alloc_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *, 250 struct sysctl_ctx_list *, struct sysctl_oid *); 251 static void free_iq_fl(struct adapter *, struct sge_iq *, struct sge_fl *); 252 static void add_iq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *, 253 struct sge_iq *); 254 static void add_fl_sysctls(struct adapter *, struct sysctl_ctx_list *, 255 struct sysctl_oid *, struct sge_fl *); 256 static int alloc_iq_fl_hwq(struct vi_info *, struct sge_iq *, struct sge_fl *); 257 static int free_iq_fl_hwq(struct adapter *, struct sge_iq *, struct sge_fl *); 258 static int alloc_fwq(struct adapter *); 259 static void free_fwq(struct adapter *); 260 static int alloc_ctrlq(struct adapter *, int); 261 static void free_ctrlq(struct adapter *, int); 262 static int alloc_rxq(struct vi_info *, struct sge_rxq *, int, int, int); 263 static void free_rxq(struct vi_info *, struct sge_rxq *); 264 static void add_rxq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *, 265 struct sge_rxq *); 266 #ifdef TCP_OFFLOAD 267 static int alloc_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *, int, int, 268 int); 269 static void free_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *); 270 static void add_ofld_rxq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *, 271 struct sge_ofld_rxq *); 272 #endif 273 static int ctrl_eq_alloc(struct adapter *, struct sge_eq *); 274 static int eth_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *); 275 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 276 static int ofld_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *); 277 #endif 278 static int alloc_eq(struct adapter *, struct sge_eq *, struct sysctl_ctx_list *, 279 struct sysctl_oid *); 280 static void free_eq(struct adapter *, struct sge_eq *); 281 static void add_eq_sysctls(struct adapter *, struct sysctl_ctx_list *, 282 struct sysctl_oid *, struct sge_eq *); 283 static int alloc_eq_hwq(struct adapter *, struct vi_info *, struct sge_eq *); 284 static int free_eq_hwq(struct adapter *, struct vi_info *, struct sge_eq *); 285 static int alloc_wrq(struct adapter *, struct vi_info *, struct sge_wrq *, 286 struct sysctl_ctx_list *, struct sysctl_oid *); 287 static void free_wrq(struct adapter *, struct sge_wrq *); 288 static void add_wrq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *, 289 struct sge_wrq *); 290 static int alloc_txq(struct vi_info *, struct sge_txq *, int); 291 static void free_txq(struct vi_info *, struct sge_txq *); 292 static void add_txq_sysctls(struct vi_info *, struct sysctl_ctx_list *, 293 struct sysctl_oid *, struct sge_txq *); 294 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 295 static int alloc_ofld_txq(struct vi_info *, struct sge_ofld_txq *, int); 296 static void free_ofld_txq(struct vi_info *, struct sge_ofld_txq *); 297 static void add_ofld_txq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *, 298 struct sge_ofld_txq *); 299 #endif 300 static void oneseg_dma_callback(void *, bus_dma_segment_t *, int, int); 301 static inline void ring_fl_db(struct adapter *, struct sge_fl *); 302 static int refill_fl(struct adapter *, struct sge_fl *, int); 303 static void refill_sfl(void *); 304 static int find_refill_source(struct adapter *, int, bool); 305 static void add_fl_to_sfl(struct adapter *, struct sge_fl *); 306 307 static inline void get_pkt_gl(struct mbuf *, struct sglist *); 308 static inline u_int txpkt_len16(u_int, const u_int); 309 static inline u_int txpkt_vm_len16(u_int, const u_int); 310 static inline void calculate_mbuf_len16(struct mbuf *, bool); 311 static inline u_int txpkts0_len16(u_int); 312 static inline u_int txpkts1_len16(void); 313 static u_int write_raw_wr(struct sge_txq *, void *, struct mbuf *, u_int); 314 static u_int write_txpkt_wr(struct adapter *, struct sge_txq *, struct mbuf *, 315 u_int); 316 static u_int write_txpkt_vm_wr(struct adapter *, struct sge_txq *, 317 struct mbuf *); 318 static int add_to_txpkts_vf(struct adapter *, struct sge_txq *, struct mbuf *, 319 int, bool *); 320 static int add_to_txpkts_pf(struct adapter *, struct sge_txq *, struct mbuf *, 321 int, bool *); 322 static u_int write_txpkts_wr(struct adapter *, struct sge_txq *); 323 static u_int write_txpkts_vm_wr(struct adapter *, struct sge_txq *); 324 static void write_gl_to_txd(struct sge_txq *, struct mbuf *, caddr_t *, int); 325 static inline void copy_to_txd(struct sge_eq *, caddr_t, caddr_t *, int); 326 static inline void ring_eq_db(struct adapter *, struct sge_eq *, u_int); 327 static inline uint16_t read_hw_cidx(struct sge_eq *); 328 static inline u_int reclaimable_tx_desc(struct sge_eq *); 329 static inline u_int total_available_tx_desc(struct sge_eq *); 330 static u_int reclaim_tx_descs(struct sge_txq *, u_int); 331 static void tx_reclaim(void *, int); 332 static __be64 get_flit(struct sglist_seg *, int, int); 333 static int handle_sge_egr_update(struct sge_iq *, const struct rss_header *, 334 struct mbuf *); 335 static int handle_fw_msg(struct sge_iq *, const struct rss_header *, 336 struct mbuf *); 337 static int t4_handle_wrerr_rpl(struct adapter *, const __be64 *); 338 static void wrq_tx_drain(void *, int); 339 static void drain_wrq_wr_list(struct adapter *, struct sge_wrq *); 340 341 static int sysctl_bufsizes(SYSCTL_HANDLER_ARGS); 342 #ifdef RATELIMIT 343 #if defined(INET) || defined(INET6) 344 static inline u_int txpkt_eo_len16(u_int, u_int, u_int); 345 #endif 346 static int ethofld_fw4_ack(struct sge_iq *, const struct rss_header *, 347 struct mbuf *); 348 #endif 349 350 static counter_u64_t extfree_refs; 351 static counter_u64_t extfree_rels; 352 353 an_handler_t t4_an_handler; 354 fw_msg_handler_t t4_fw_msg_handler[NUM_FW6_TYPES]; 355 cpl_handler_t t4_cpl_handler[NUM_CPL_CMDS]; 356 cpl_handler_t set_tcb_rpl_handlers[NUM_CPL_COOKIES]; 357 cpl_handler_t l2t_write_rpl_handlers[NUM_CPL_COOKIES]; 358 cpl_handler_t act_open_rpl_handlers[NUM_CPL_COOKIES]; 359 cpl_handler_t abort_rpl_rss_handlers[NUM_CPL_COOKIES]; 360 cpl_handler_t fw4_ack_handlers[NUM_CPL_COOKIES]; 361 362 void 363 t4_register_an_handler(an_handler_t h) 364 { 365 uintptr_t *loc; 366 367 MPASS(h == NULL || t4_an_handler == NULL); 368 369 loc = (uintptr_t *)&t4_an_handler; 370 atomic_store_rel_ptr(loc, (uintptr_t)h); 371 } 372 373 void 374 t4_register_fw_msg_handler(int type, fw_msg_handler_t h) 375 { 376 uintptr_t *loc; 377 378 MPASS(type < nitems(t4_fw_msg_handler)); 379 MPASS(h == NULL || t4_fw_msg_handler[type] == NULL); 380 /* 381 * These are dispatched by the handler for FW{4|6}_CPL_MSG using the CPL 382 * handler dispatch table. Reject any attempt to install a handler for 383 * this subtype. 384 */ 385 MPASS(type != FW_TYPE_RSSCPL); 386 MPASS(type != FW6_TYPE_RSSCPL); 387 388 loc = (uintptr_t *)&t4_fw_msg_handler[type]; 389 atomic_store_rel_ptr(loc, (uintptr_t)h); 390 } 391 392 void 393 t4_register_cpl_handler(int opcode, cpl_handler_t h) 394 { 395 uintptr_t *loc; 396 397 MPASS(opcode < nitems(t4_cpl_handler)); 398 MPASS(h == NULL || t4_cpl_handler[opcode] == NULL); 399 400 loc = (uintptr_t *)&t4_cpl_handler[opcode]; 401 atomic_store_rel_ptr(loc, (uintptr_t)h); 402 } 403 404 static int 405 set_tcb_rpl_handler(struct sge_iq *iq, const struct rss_header *rss, 406 struct mbuf *m) 407 { 408 const struct cpl_set_tcb_rpl *cpl = (const void *)(rss + 1); 409 u_int tid; 410 int cookie; 411 412 MPASS(m == NULL); 413 414 tid = GET_TID(cpl); 415 if (is_hpftid(iq->adapter, tid) || is_ftid(iq->adapter, tid)) { 416 /* 417 * The return code for filter-write is put in the CPL cookie so 418 * we have to rely on the hardware tid (is_ftid) to determine 419 * that this is a response to a filter. 420 */ 421 cookie = CPL_COOKIE_FILTER; 422 } else { 423 cookie = G_COOKIE(cpl->cookie); 424 } 425 MPASS(cookie > CPL_COOKIE_RESERVED); 426 MPASS(cookie < nitems(set_tcb_rpl_handlers)); 427 428 return (set_tcb_rpl_handlers[cookie](iq, rss, m)); 429 } 430 431 static int 432 l2t_write_rpl_handler(struct sge_iq *iq, const struct rss_header *rss, 433 struct mbuf *m) 434 { 435 const struct cpl_l2t_write_rpl *rpl = (const void *)(rss + 1); 436 unsigned int cookie; 437 438 MPASS(m == NULL); 439 440 cookie = GET_TID(rpl) & F_SYNC_WR ? CPL_COOKIE_TOM : CPL_COOKIE_FILTER; 441 return (l2t_write_rpl_handlers[cookie](iq, rss, m)); 442 } 443 444 static int 445 act_open_rpl_handler(struct sge_iq *iq, const struct rss_header *rss, 446 struct mbuf *m) 447 { 448 const struct cpl_act_open_rpl *cpl = (const void *)(rss + 1); 449 u_int cookie = G_TID_COOKIE(G_AOPEN_ATID(be32toh(cpl->atid_status))); 450 451 MPASS(m == NULL); 452 MPASS(cookie != CPL_COOKIE_RESERVED); 453 454 return (act_open_rpl_handlers[cookie](iq, rss, m)); 455 } 456 457 static int 458 abort_rpl_rss_handler(struct sge_iq *iq, const struct rss_header *rss, 459 struct mbuf *m) 460 { 461 struct adapter *sc = iq->adapter; 462 u_int cookie; 463 464 MPASS(m == NULL); 465 if (is_hashfilter(sc)) 466 cookie = CPL_COOKIE_HASHFILTER; 467 else 468 cookie = CPL_COOKIE_TOM; 469 470 return (abort_rpl_rss_handlers[cookie](iq, rss, m)); 471 } 472 473 static int 474 fw4_ack_handler(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 475 { 476 struct adapter *sc = iq->adapter; 477 const struct cpl_fw4_ack *cpl = (const void *)(rss + 1); 478 unsigned int tid = G_CPL_FW4_ACK_FLOWID(be32toh(OPCODE_TID(cpl))); 479 u_int cookie; 480 481 MPASS(m == NULL); 482 if (is_etid(sc, tid)) 483 cookie = CPL_COOKIE_ETHOFLD; 484 else 485 cookie = CPL_COOKIE_TOM; 486 487 return (fw4_ack_handlers[cookie](iq, rss, m)); 488 } 489 490 static void 491 t4_init_shared_cpl_handlers(void) 492 { 493 494 t4_register_cpl_handler(CPL_SET_TCB_RPL, set_tcb_rpl_handler); 495 t4_register_cpl_handler(CPL_L2T_WRITE_RPL, l2t_write_rpl_handler); 496 t4_register_cpl_handler(CPL_ACT_OPEN_RPL, act_open_rpl_handler); 497 t4_register_cpl_handler(CPL_ABORT_RPL_RSS, abort_rpl_rss_handler); 498 t4_register_cpl_handler(CPL_FW4_ACK, fw4_ack_handler); 499 } 500 501 void 502 t4_register_shared_cpl_handler(int opcode, cpl_handler_t h, int cookie) 503 { 504 uintptr_t *loc; 505 506 MPASS(opcode < nitems(t4_cpl_handler)); 507 MPASS(cookie > CPL_COOKIE_RESERVED); 508 MPASS(cookie < NUM_CPL_COOKIES); 509 MPASS(t4_cpl_handler[opcode] != NULL); 510 511 switch (opcode) { 512 case CPL_SET_TCB_RPL: 513 loc = (uintptr_t *)&set_tcb_rpl_handlers[cookie]; 514 break; 515 case CPL_L2T_WRITE_RPL: 516 loc = (uintptr_t *)&l2t_write_rpl_handlers[cookie]; 517 break; 518 case CPL_ACT_OPEN_RPL: 519 loc = (uintptr_t *)&act_open_rpl_handlers[cookie]; 520 break; 521 case CPL_ABORT_RPL_RSS: 522 loc = (uintptr_t *)&abort_rpl_rss_handlers[cookie]; 523 break; 524 case CPL_FW4_ACK: 525 loc = (uintptr_t *)&fw4_ack_handlers[cookie]; 526 break; 527 default: 528 MPASS(0); 529 return; 530 } 531 MPASS(h == NULL || *loc == (uintptr_t)NULL); 532 atomic_store_rel_ptr(loc, (uintptr_t)h); 533 } 534 535 /* 536 * Called on MOD_LOAD. Validates and calculates the SGE tunables. 537 */ 538 void 539 t4_sge_modload(void) 540 { 541 542 if (fl_pktshift < 0 || fl_pktshift > 7) { 543 printf("Invalid hw.cxgbe.fl_pktshift value (%d)," 544 " using 0 instead.\n", fl_pktshift); 545 fl_pktshift = 0; 546 } 547 548 if (spg_len != 64 && spg_len != 128) { 549 int len; 550 551 #if defined(__i386__) || defined(__amd64__) 552 len = cpu_clflush_line_size > 64 ? 128 : 64; 553 #else 554 len = 64; 555 #endif 556 if (spg_len != -1) { 557 printf("Invalid hw.cxgbe.spg_len value (%d)," 558 " using %d instead.\n", spg_len, len); 559 } 560 spg_len = len; 561 } 562 563 if (cong_drop < -1 || cong_drop > 2) { 564 printf("Invalid hw.cxgbe.cong_drop value (%d)," 565 " using 0 instead.\n", cong_drop); 566 cong_drop = 0; 567 } 568 #ifdef TCP_OFFLOAD 569 if (ofld_cong_drop < -1 || ofld_cong_drop > 2) { 570 printf("Invalid hw.cxgbe.ofld_cong_drop value (%d)," 571 " using 0 instead.\n", ofld_cong_drop); 572 ofld_cong_drop = 0; 573 } 574 #endif 575 576 if (tscale != 1 && (tscale < 3 || tscale > 17)) { 577 printf("Invalid hw.cxgbe.tscale value (%d)," 578 " using 1 instead.\n", tscale); 579 tscale = 1; 580 } 581 582 if (largest_rx_cluster != MCLBYTES && 583 largest_rx_cluster != MJUMPAGESIZE && 584 largest_rx_cluster != MJUM9BYTES && 585 largest_rx_cluster != MJUM16BYTES) { 586 printf("Invalid hw.cxgbe.largest_rx_cluster value (%d)," 587 " using %d instead.\n", largest_rx_cluster, MJUM16BYTES); 588 largest_rx_cluster = MJUM16BYTES; 589 } 590 591 if (safest_rx_cluster != MCLBYTES && 592 safest_rx_cluster != MJUMPAGESIZE && 593 safest_rx_cluster != MJUM9BYTES && 594 safest_rx_cluster != MJUM16BYTES) { 595 printf("Invalid hw.cxgbe.safest_rx_cluster value (%d)," 596 " using %d instead.\n", safest_rx_cluster, MJUMPAGESIZE); 597 safest_rx_cluster = MJUMPAGESIZE; 598 } 599 600 extfree_refs = counter_u64_alloc(M_WAITOK); 601 extfree_rels = counter_u64_alloc(M_WAITOK); 602 pullups = counter_u64_alloc(M_WAITOK); 603 defrags = counter_u64_alloc(M_WAITOK); 604 counter_u64_zero(extfree_refs); 605 counter_u64_zero(extfree_rels); 606 counter_u64_zero(pullups); 607 counter_u64_zero(defrags); 608 609 t4_init_shared_cpl_handlers(); 610 t4_register_cpl_handler(CPL_FW4_MSG, handle_fw_msg); 611 t4_register_cpl_handler(CPL_FW6_MSG, handle_fw_msg); 612 t4_register_cpl_handler(CPL_SGE_EGR_UPDATE, handle_sge_egr_update); 613 #ifdef RATELIMIT 614 t4_register_shared_cpl_handler(CPL_FW4_ACK, ethofld_fw4_ack, 615 CPL_COOKIE_ETHOFLD); 616 #endif 617 t4_register_fw_msg_handler(FW6_TYPE_CMD_RPL, t4_handle_fw_rpl); 618 t4_register_fw_msg_handler(FW6_TYPE_WRERR_RPL, t4_handle_wrerr_rpl); 619 } 620 621 void 622 t4_sge_modunload(void) 623 { 624 625 counter_u64_free(extfree_refs); 626 counter_u64_free(extfree_rels); 627 counter_u64_free(pullups); 628 counter_u64_free(defrags); 629 } 630 631 uint64_t 632 t4_sge_extfree_refs(void) 633 { 634 uint64_t refs, rels; 635 636 rels = counter_u64_fetch(extfree_rels); 637 refs = counter_u64_fetch(extfree_refs); 638 639 return (refs - rels); 640 } 641 642 /* max 4096 */ 643 #define MAX_PACK_BOUNDARY 512 644 645 static inline void 646 setup_pad_and_pack_boundaries(struct adapter *sc) 647 { 648 uint32_t v, m; 649 int pad, pack, pad_shift; 650 651 pad_shift = chip_id(sc) > CHELSIO_T5 ? X_T6_INGPADBOUNDARY_SHIFT : 652 X_INGPADBOUNDARY_SHIFT; 653 pad = fl_pad; 654 if (fl_pad < (1 << pad_shift) || 655 fl_pad > (1 << (pad_shift + M_INGPADBOUNDARY)) || 656 !powerof2(fl_pad)) { 657 /* 658 * If there is any chance that we might use buffer packing and 659 * the chip is a T4, then pick 64 as the pad/pack boundary. Set 660 * it to the minimum allowed in all other cases. 661 */ 662 pad = is_t4(sc) && buffer_packing ? 64 : 1 << pad_shift; 663 664 /* 665 * For fl_pad = 0 we'll still write a reasonable value to the 666 * register but all the freelists will opt out of padding. 667 * We'll complain here only if the user tried to set it to a 668 * value greater than 0 that was invalid. 669 */ 670 if (fl_pad > 0) { 671 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pad value" 672 " (%d), using %d instead.\n", fl_pad, pad); 673 } 674 } 675 m = V_INGPADBOUNDARY(M_INGPADBOUNDARY); 676 v = V_INGPADBOUNDARY(ilog2(pad) - pad_shift); 677 t4_set_reg_field(sc, A_SGE_CONTROL, m, v); 678 679 if (is_t4(sc)) { 680 if (fl_pack != -1 && fl_pack != pad) { 681 /* Complain but carry on. */ 682 device_printf(sc->dev, "hw.cxgbe.fl_pack (%d) ignored," 683 " using %d instead.\n", fl_pack, pad); 684 } 685 return; 686 } 687 688 pack = fl_pack; 689 if (fl_pack < 16 || fl_pack == 32 || fl_pack > 4096 || 690 !powerof2(fl_pack)) { 691 if (sc->params.pci.mps > MAX_PACK_BOUNDARY) 692 pack = MAX_PACK_BOUNDARY; 693 else 694 pack = max(sc->params.pci.mps, CACHE_LINE_SIZE); 695 MPASS(powerof2(pack)); 696 if (pack < 16) 697 pack = 16; 698 if (pack == 32) 699 pack = 64; 700 if (pack > 4096) 701 pack = 4096; 702 if (fl_pack != -1) { 703 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pack value" 704 " (%d), using %d instead.\n", fl_pack, pack); 705 } 706 } 707 m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY); 708 if (pack == 16) 709 v = V_INGPACKBOUNDARY(0); 710 else 711 v = V_INGPACKBOUNDARY(ilog2(pack) - 5); 712 713 MPASS(!is_t4(sc)); /* T4 doesn't have SGE_CONTROL2 */ 714 t4_set_reg_field(sc, A_SGE_CONTROL2, m, v); 715 } 716 717 /* 718 * adap->params.vpd.cclk must be set up before this is called. 719 */ 720 void 721 t4_tweak_chip_settings(struct adapter *sc) 722 { 723 int i, reg; 724 uint32_t v, m; 725 int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200}; 726 int timer_max = M_TIMERVALUE0 * 1000 / sc->params.vpd.cclk; 727 int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */ 728 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 729 static int sw_buf_sizes[] = { 730 MCLBYTES, 731 MJUMPAGESIZE, 732 MJUM9BYTES, 733 MJUM16BYTES 734 }; 735 736 KASSERT(sc->flags & MASTER_PF, 737 ("%s: trying to change chip settings when not master.", __func__)); 738 739 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE; 740 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE | 741 V_EGRSTATUSPAGESIZE(spg_len == 128); 742 t4_set_reg_field(sc, A_SGE_CONTROL, m, v); 743 744 setup_pad_and_pack_boundaries(sc); 745 746 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) | 747 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) | 748 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) | 749 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) | 750 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) | 751 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) | 752 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) | 753 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10); 754 t4_write_reg(sc, A_SGE_HOST_PAGE_SIZE, v); 755 756 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0, 4096); 757 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE1, 65536); 758 reg = A_SGE_FL_BUFFER_SIZE2; 759 for (i = 0; i < nitems(sw_buf_sizes); i++) { 760 MPASS(reg <= A_SGE_FL_BUFFER_SIZE15); 761 t4_write_reg(sc, reg, sw_buf_sizes[i]); 762 reg += 4; 763 MPASS(reg <= A_SGE_FL_BUFFER_SIZE15); 764 t4_write_reg(sc, reg, sw_buf_sizes[i] - CL_METADATA_SIZE); 765 reg += 4; 766 } 767 768 v = V_THRESHOLD_0(intr_pktcount[0]) | V_THRESHOLD_1(intr_pktcount[1]) | 769 V_THRESHOLD_2(intr_pktcount[2]) | V_THRESHOLD_3(intr_pktcount[3]); 770 t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD, v); 771 772 KASSERT(intr_timer[0] <= timer_max, 773 ("%s: not a single usable timer (%d, %d)", __func__, intr_timer[0], 774 timer_max)); 775 for (i = 1; i < nitems(intr_timer); i++) { 776 KASSERT(intr_timer[i] >= intr_timer[i - 1], 777 ("%s: timers not listed in increasing order (%d)", 778 __func__, i)); 779 780 while (intr_timer[i] > timer_max) { 781 if (i == nitems(intr_timer) - 1) { 782 intr_timer[i] = timer_max; 783 break; 784 } 785 intr_timer[i] += intr_timer[i - 1]; 786 intr_timer[i] /= 2; 787 } 788 } 789 790 v = V_TIMERVALUE0(us_to_core_ticks(sc, intr_timer[0])) | 791 V_TIMERVALUE1(us_to_core_ticks(sc, intr_timer[1])); 792 t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1, v); 793 v = V_TIMERVALUE2(us_to_core_ticks(sc, intr_timer[2])) | 794 V_TIMERVALUE3(us_to_core_ticks(sc, intr_timer[3])); 795 t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3, v); 796 v = V_TIMERVALUE4(us_to_core_ticks(sc, intr_timer[4])) | 797 V_TIMERVALUE5(us_to_core_ticks(sc, intr_timer[5])); 798 t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5, v); 799 800 if (chip_id(sc) >= CHELSIO_T6) { 801 m = V_TSCALE(M_TSCALE); 802 if (tscale == 1) 803 v = 0; 804 else 805 v = V_TSCALE(tscale - 2); 806 t4_set_reg_field(sc, A_SGE_ITP_CONTROL, m, v); 807 808 if (sc->debug_flags & DF_DISABLE_TCB_CACHE) { 809 m = V_RDTHRESHOLD(M_RDTHRESHOLD) | F_WRTHRTHRESHEN | 810 V_WRTHRTHRESH(M_WRTHRTHRESH); 811 t4_tp_pio_read(sc, &v, 1, A_TP_CMM_CONFIG, 1); 812 v &= ~m; 813 v |= V_RDTHRESHOLD(1) | F_WRTHRTHRESHEN | 814 V_WRTHRTHRESH(16); 815 t4_tp_pio_write(sc, &v, 1, A_TP_CMM_CONFIG, 1); 816 } 817 } 818 819 /* 4K, 16K, 64K, 256K DDP "page sizes" for TDDP */ 820 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 821 t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, v); 822 823 /* 824 * 4K, 8K, 16K, 64K DDP "page sizes" for iSCSI DDP. These have been 825 * chosen with MAXPHYS = 128K in mind. The largest DDP buffer that we 826 * may have to deal with is MAXPHYS + 1 page. 827 */ 828 v = V_HPZ0(0) | V_HPZ1(1) | V_HPZ2(2) | V_HPZ3(4); 829 t4_write_reg(sc, A_ULP_RX_ISCSI_PSZ, v); 830 831 /* We use multiple DDP page sizes both in plain-TOE and ISCSI modes. */ 832 m = v = F_TDDPTAGTCB | F_ISCSITAGTCB; 833 t4_set_reg_field(sc, A_ULP_RX_CTL, m, v); 834 835 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 836 F_RESETDDPOFFSET; 837 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 838 t4_set_reg_field(sc, A_TP_PARA_REG5, m, v); 839 } 840 841 /* 842 * SGE wants the buffer to be at least 64B and then a multiple of 16. Its 843 * address mut be 16B aligned. If padding is in use the buffer's start and end 844 * need to be aligned to the pad boundary as well. We'll just make sure that 845 * the size is a multiple of the pad boundary here, it is up to the buffer 846 * allocation code to make sure the start of the buffer is aligned. 847 */ 848 static inline int 849 hwsz_ok(struct adapter *sc, int hwsz) 850 { 851 int mask = fl_pad ? sc->params.sge.pad_boundary - 1 : 16 - 1; 852 853 return (hwsz >= 64 && (hwsz & mask) == 0); 854 } 855 856 /* 857 * Initialize the rx buffer sizes and figure out which zones the buffers will 858 * be allocated from. 859 */ 860 void 861 t4_init_rx_buf_info(struct adapter *sc) 862 { 863 struct sge *s = &sc->sge; 864 struct sge_params *sp = &sc->params.sge; 865 int i, j, n; 866 static int sw_buf_sizes[] = { /* Sorted by size */ 867 MCLBYTES, 868 MJUMPAGESIZE, 869 MJUM9BYTES, 870 MJUM16BYTES 871 }; 872 struct rx_buf_info *rxb; 873 874 s->safe_zidx = -1; 875 rxb = &s->rx_buf_info[0]; 876 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) { 877 rxb->size1 = sw_buf_sizes[i]; 878 rxb->zone = m_getzone(rxb->size1); 879 rxb->type = m_gettype(rxb->size1); 880 rxb->size2 = 0; 881 rxb->hwidx1 = -1; 882 rxb->hwidx2 = -1; 883 for (j = 0; j < SGE_FLBUF_SIZES; j++) { 884 int hwsize = sp->sge_fl_buffer_size[j]; 885 886 if (!hwsz_ok(sc, hwsize)) 887 continue; 888 889 /* hwidx for size1 */ 890 if (rxb->hwidx1 == -1 && rxb->size1 == hwsize) 891 rxb->hwidx1 = j; 892 893 /* hwidx for size2 (buffer packing) */ 894 if (rxb->size1 - CL_METADATA_SIZE < hwsize) 895 continue; 896 n = rxb->size1 - hwsize - CL_METADATA_SIZE; 897 if (n == 0) { 898 rxb->hwidx2 = j; 899 rxb->size2 = hwsize; 900 break; /* stop looking */ 901 } 902 if (rxb->hwidx2 != -1) { 903 if (n < sp->sge_fl_buffer_size[rxb->hwidx2] - 904 hwsize - CL_METADATA_SIZE) { 905 rxb->hwidx2 = j; 906 rxb->size2 = hwsize; 907 } 908 } else if (n <= 2 * CL_METADATA_SIZE) { 909 rxb->hwidx2 = j; 910 rxb->size2 = hwsize; 911 } 912 } 913 if (rxb->hwidx2 != -1) 914 sc->flags |= BUF_PACKING_OK; 915 if (s->safe_zidx == -1 && rxb->size1 == safest_rx_cluster) 916 s->safe_zidx = i; 917 } 918 } 919 920 /* 921 * Verify some basic SGE settings for the PF and VF driver, and other 922 * miscellaneous settings for the PF driver. 923 */ 924 int 925 t4_verify_chip_settings(struct adapter *sc) 926 { 927 struct sge_params *sp = &sc->params.sge; 928 uint32_t m, v, r; 929 int rc = 0; 930 const uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 931 932 m = F_RXPKTCPLMODE; 933 v = F_RXPKTCPLMODE; 934 r = sp->sge_control; 935 if ((r & m) != v) { 936 device_printf(sc->dev, "invalid SGE_CONTROL(0x%x)\n", r); 937 rc = EINVAL; 938 } 939 940 /* 941 * If this changes then every single use of PAGE_SHIFT in the driver 942 * needs to be carefully reviewed for PAGE_SHIFT vs sp->page_shift. 943 */ 944 if (sp->page_shift != PAGE_SHIFT) { 945 device_printf(sc->dev, "invalid SGE_HOST_PAGE_SIZE(0x%x)\n", r); 946 rc = EINVAL; 947 } 948 949 if (sc->flags & IS_VF) 950 return (0); 951 952 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 953 r = t4_read_reg(sc, A_ULP_RX_TDDP_PSZ); 954 if (r != v) { 955 device_printf(sc->dev, "invalid ULP_RX_TDDP_PSZ(0x%x)\n", r); 956 if (sc->vres.ddp.size != 0) 957 rc = EINVAL; 958 } 959 960 m = v = F_TDDPTAGTCB; 961 r = t4_read_reg(sc, A_ULP_RX_CTL); 962 if ((r & m) != v) { 963 device_printf(sc->dev, "invalid ULP_RX_CTL(0x%x)\n", r); 964 if (sc->vres.ddp.size != 0) 965 rc = EINVAL; 966 } 967 968 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 969 F_RESETDDPOFFSET; 970 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 971 r = t4_read_reg(sc, A_TP_PARA_REG5); 972 if ((r & m) != v) { 973 device_printf(sc->dev, "invalid TP_PARA_REG5(0x%x)\n", r); 974 if (sc->vres.ddp.size != 0) 975 rc = EINVAL; 976 } 977 978 return (rc); 979 } 980 981 int 982 t4_create_dma_tag(struct adapter *sc) 983 { 984 int rc; 985 986 rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0, 987 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE, 988 BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL, 989 NULL, &sc->dmat); 990 if (rc != 0) { 991 device_printf(sc->dev, 992 "failed to create main DMA tag: %d\n", rc); 993 } 994 995 return (rc); 996 } 997 998 void 999 t4_sge_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx, 1000 struct sysctl_oid_list *children) 1001 { 1002 struct sge_params *sp = &sc->params.sge; 1003 1004 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "buffer_sizes", 1005 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 1006 sysctl_bufsizes, "A", "freelist buffer sizes"); 1007 1008 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pktshift", CTLFLAG_RD, 1009 NULL, sp->fl_pktshift, "payload DMA offset in rx buffer (bytes)"); 1010 1011 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pad", CTLFLAG_RD, 1012 NULL, sp->pad_boundary, "payload pad boundary (bytes)"); 1013 1014 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "spg_len", CTLFLAG_RD, 1015 NULL, sp->spg_len, "status page size (bytes)"); 1016 1017 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_drop", CTLFLAG_RD, 1018 NULL, cong_drop, "congestion drop setting"); 1019 #ifdef TCP_OFFLOAD 1020 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ofld_cong_drop", CTLFLAG_RD, 1021 NULL, ofld_cong_drop, "congestion drop setting"); 1022 #endif 1023 1024 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pack", CTLFLAG_RD, 1025 NULL, sp->pack_boundary, "payload pack boundary (bytes)"); 1026 } 1027 1028 int 1029 t4_destroy_dma_tag(struct adapter *sc) 1030 { 1031 if (sc->dmat) 1032 bus_dma_tag_destroy(sc->dmat); 1033 1034 return (0); 1035 } 1036 1037 /* 1038 * Allocate and initialize the firmware event queue, control queues, and special 1039 * purpose rx queues owned by the adapter. 1040 * 1041 * Returns errno on failure. Resources allocated up to that point may still be 1042 * allocated. Caller is responsible for cleanup in case this function fails. 1043 */ 1044 int 1045 t4_setup_adapter_queues(struct adapter *sc) 1046 { 1047 int rc, i; 1048 1049 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 1050 1051 /* 1052 * Firmware event queue 1053 */ 1054 rc = alloc_fwq(sc); 1055 if (rc != 0) 1056 return (rc); 1057 1058 /* 1059 * That's all for the VF driver. 1060 */ 1061 if (sc->flags & IS_VF) 1062 return (rc); 1063 1064 /* 1065 * XXX: General purpose rx queues, one per port. 1066 */ 1067 1068 /* 1069 * Control queues, one per port. 1070 */ 1071 for_each_port(sc, i) { 1072 rc = alloc_ctrlq(sc, i); 1073 if (rc != 0) 1074 return (rc); 1075 } 1076 1077 return (rc); 1078 } 1079 1080 /* 1081 * Idempotent 1082 */ 1083 int 1084 t4_teardown_adapter_queues(struct adapter *sc) 1085 { 1086 int i; 1087 1088 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 1089 1090 if (sc->sge.ctrlq != NULL) { 1091 MPASS(!(sc->flags & IS_VF)); /* VFs don't allocate ctrlq. */ 1092 for_each_port(sc, i) 1093 free_ctrlq(sc, i); 1094 } 1095 free_fwq(sc); 1096 1097 return (0); 1098 } 1099 1100 /* Maximum payload that could arrive with a single iq descriptor. */ 1101 static inline int 1102 max_rx_payload(struct adapter *sc, struct ifnet *ifp, const bool ofld) 1103 { 1104 int maxp; 1105 1106 /* large enough even when hw VLAN extraction is disabled */ 1107 maxp = sc->params.sge.fl_pktshift + ETHER_HDR_LEN + 1108 ETHER_VLAN_ENCAP_LEN + ifp->if_mtu; 1109 if (ofld && sc->tt.tls && sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS && 1110 maxp < sc->params.tp.max_rx_pdu) 1111 maxp = sc->params.tp.max_rx_pdu; 1112 return (maxp); 1113 } 1114 1115 int 1116 t4_setup_vi_queues(struct vi_info *vi) 1117 { 1118 int rc = 0, i, intr_idx; 1119 struct sge_rxq *rxq; 1120 struct sge_txq *txq; 1121 #ifdef TCP_OFFLOAD 1122 struct sge_ofld_rxq *ofld_rxq; 1123 #endif 1124 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1125 struct sge_ofld_txq *ofld_txq; 1126 #endif 1127 #ifdef DEV_NETMAP 1128 int saved_idx, iqidx; 1129 struct sge_nm_rxq *nm_rxq; 1130 struct sge_nm_txq *nm_txq; 1131 #endif 1132 struct adapter *sc = vi->adapter; 1133 struct ifnet *ifp = vi->ifp; 1134 int maxp; 1135 1136 /* Interrupt vector to start from (when using multiple vectors) */ 1137 intr_idx = vi->first_intr; 1138 1139 #ifdef DEV_NETMAP 1140 saved_idx = intr_idx; 1141 if (ifp->if_capabilities & IFCAP_NETMAP) { 1142 1143 /* netmap is supported with direct interrupts only. */ 1144 MPASS(!forwarding_intr_to_fwq(sc)); 1145 MPASS(vi->first_intr >= 0); 1146 1147 /* 1148 * We don't have buffers to back the netmap rx queues 1149 * right now so we create the queues in a way that 1150 * doesn't set off any congestion signal in the chip. 1151 */ 1152 for_each_nm_rxq(vi, i, nm_rxq) { 1153 rc = alloc_nm_rxq(vi, nm_rxq, intr_idx, i); 1154 if (rc != 0) 1155 goto done; 1156 intr_idx++; 1157 } 1158 1159 for_each_nm_txq(vi, i, nm_txq) { 1160 iqidx = vi->first_nm_rxq + (i % vi->nnmrxq); 1161 rc = alloc_nm_txq(vi, nm_txq, iqidx, i); 1162 if (rc != 0) 1163 goto done; 1164 } 1165 } 1166 1167 /* Normal rx queues and netmap rx queues share the same interrupts. */ 1168 intr_idx = saved_idx; 1169 #endif 1170 1171 /* 1172 * Allocate rx queues first because a default iqid is required when 1173 * creating a tx queue. 1174 */ 1175 maxp = max_rx_payload(sc, ifp, false); 1176 for_each_rxq(vi, i, rxq) { 1177 rc = alloc_rxq(vi, rxq, i, intr_idx, maxp); 1178 if (rc != 0) 1179 goto done; 1180 if (!forwarding_intr_to_fwq(sc)) 1181 intr_idx++; 1182 } 1183 #ifdef DEV_NETMAP 1184 if (ifp->if_capabilities & IFCAP_NETMAP) 1185 intr_idx = saved_idx + max(vi->nrxq, vi->nnmrxq); 1186 #endif 1187 #ifdef TCP_OFFLOAD 1188 maxp = max_rx_payload(sc, ifp, true); 1189 for_each_ofld_rxq(vi, i, ofld_rxq) { 1190 rc = alloc_ofld_rxq(vi, ofld_rxq, i, intr_idx, maxp); 1191 if (rc != 0) 1192 goto done; 1193 if (!forwarding_intr_to_fwq(sc)) 1194 intr_idx++; 1195 } 1196 #endif 1197 1198 /* 1199 * Now the tx queues. 1200 */ 1201 for_each_txq(vi, i, txq) { 1202 rc = alloc_txq(vi, txq, i); 1203 if (rc != 0) 1204 goto done; 1205 } 1206 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1207 for_each_ofld_txq(vi, i, ofld_txq) { 1208 rc = alloc_ofld_txq(vi, ofld_txq, i); 1209 if (rc != 0) 1210 goto done; 1211 } 1212 #endif 1213 done: 1214 if (rc) 1215 t4_teardown_vi_queues(vi); 1216 1217 return (rc); 1218 } 1219 1220 /* 1221 * Idempotent 1222 */ 1223 int 1224 t4_teardown_vi_queues(struct vi_info *vi) 1225 { 1226 int i; 1227 struct sge_rxq *rxq; 1228 struct sge_txq *txq; 1229 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1230 struct sge_ofld_txq *ofld_txq; 1231 #endif 1232 #ifdef TCP_OFFLOAD 1233 struct sge_ofld_rxq *ofld_rxq; 1234 #endif 1235 #ifdef DEV_NETMAP 1236 struct sge_nm_rxq *nm_rxq; 1237 struct sge_nm_txq *nm_txq; 1238 #endif 1239 1240 #ifdef DEV_NETMAP 1241 if (vi->ifp->if_capabilities & IFCAP_NETMAP) { 1242 for_each_nm_txq(vi, i, nm_txq) { 1243 free_nm_txq(vi, nm_txq); 1244 } 1245 1246 for_each_nm_rxq(vi, i, nm_rxq) { 1247 free_nm_rxq(vi, nm_rxq); 1248 } 1249 } 1250 #endif 1251 1252 /* 1253 * Take down all the tx queues first, as they reference the rx queues 1254 * (for egress updates, etc.). 1255 */ 1256 1257 for_each_txq(vi, i, txq) { 1258 free_txq(vi, txq); 1259 } 1260 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1261 for_each_ofld_txq(vi, i, ofld_txq) { 1262 free_ofld_txq(vi, ofld_txq); 1263 } 1264 #endif 1265 1266 /* 1267 * Then take down the rx queues. 1268 */ 1269 1270 for_each_rxq(vi, i, rxq) { 1271 free_rxq(vi, rxq); 1272 } 1273 #ifdef TCP_OFFLOAD 1274 for_each_ofld_rxq(vi, i, ofld_rxq) { 1275 free_ofld_rxq(vi, ofld_rxq); 1276 } 1277 #endif 1278 1279 return (0); 1280 } 1281 1282 /* 1283 * Interrupt handler when the driver is using only 1 interrupt. This is a very 1284 * unusual scenario. 1285 * 1286 * a) Deals with errors, if any. 1287 * b) Services firmware event queue, which is taking interrupts for all other 1288 * queues. 1289 */ 1290 void 1291 t4_intr_all(void *arg) 1292 { 1293 struct adapter *sc = arg; 1294 struct sge_iq *fwq = &sc->sge.fwq; 1295 1296 MPASS(sc->intr_count == 1); 1297 1298 if (sc->intr_type == INTR_INTX) 1299 t4_write_reg(sc, MYPF_REG(A_PCIE_PF_CLI), 0); 1300 1301 t4_intr_err(arg); 1302 t4_intr_evt(fwq); 1303 } 1304 1305 /* 1306 * Interrupt handler for errors (installed directly when multiple interrupts are 1307 * being used, or called by t4_intr_all). 1308 */ 1309 void 1310 t4_intr_err(void *arg) 1311 { 1312 struct adapter *sc = arg; 1313 uint32_t v; 1314 const bool verbose = (sc->debug_flags & DF_VERBOSE_SLOWINTR) != 0; 1315 1316 if (atomic_load_int(&sc->error_flags) & ADAP_FATAL_ERR) 1317 return; 1318 1319 v = t4_read_reg(sc, MYPF_REG(A_PL_PF_INT_CAUSE)); 1320 if (v & F_PFSW) { 1321 sc->swintr++; 1322 t4_write_reg(sc, MYPF_REG(A_PL_PF_INT_CAUSE), v); 1323 } 1324 1325 if (t4_slow_intr_handler(sc, verbose)) 1326 t4_fatal_err(sc, false); 1327 } 1328 1329 /* 1330 * Interrupt handler for iq-only queues. The firmware event queue is the only 1331 * such queue right now. 1332 */ 1333 void 1334 t4_intr_evt(void *arg) 1335 { 1336 struct sge_iq *iq = arg; 1337 1338 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 1339 service_iq(iq, 0); 1340 (void) atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 1341 } 1342 } 1343 1344 /* 1345 * Interrupt handler for iq+fl queues. 1346 */ 1347 void 1348 t4_intr(void *arg) 1349 { 1350 struct sge_iq *iq = arg; 1351 1352 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 1353 service_iq_fl(iq, 0); 1354 (void) atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 1355 } 1356 } 1357 1358 #ifdef DEV_NETMAP 1359 /* 1360 * Interrupt handler for netmap rx queues. 1361 */ 1362 void 1363 t4_nm_intr(void *arg) 1364 { 1365 struct sge_nm_rxq *nm_rxq = arg; 1366 1367 if (atomic_cmpset_int(&nm_rxq->nm_state, NM_ON, NM_BUSY)) { 1368 service_nm_rxq(nm_rxq); 1369 (void) atomic_cmpset_int(&nm_rxq->nm_state, NM_BUSY, NM_ON); 1370 } 1371 } 1372 1373 /* 1374 * Interrupt handler for vectors shared between NIC and netmap rx queues. 1375 */ 1376 void 1377 t4_vi_intr(void *arg) 1378 { 1379 struct irq *irq = arg; 1380 1381 MPASS(irq->nm_rxq != NULL); 1382 t4_nm_intr(irq->nm_rxq); 1383 1384 MPASS(irq->rxq != NULL); 1385 t4_intr(irq->rxq); 1386 } 1387 #endif 1388 1389 /* 1390 * Deals with interrupts on an iq-only (no freelist) queue. 1391 */ 1392 static int 1393 service_iq(struct sge_iq *iq, int budget) 1394 { 1395 struct sge_iq *q; 1396 struct adapter *sc = iq->adapter; 1397 struct iq_desc *d = &iq->desc[iq->cidx]; 1398 int ndescs = 0, limit; 1399 int rsp_type; 1400 uint32_t lq; 1401 STAILQ_HEAD(, sge_iq) iql = STAILQ_HEAD_INITIALIZER(iql); 1402 1403 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq)); 1404 KASSERT((iq->flags & IQ_HAS_FL) == 0, 1405 ("%s: called for iq %p with fl (iq->flags 0x%x)", __func__, iq, 1406 iq->flags)); 1407 MPASS((iq->flags & IQ_ADJ_CREDIT) == 0); 1408 MPASS((iq->flags & IQ_LRO_ENABLED) == 0); 1409 1410 limit = budget ? budget : iq->qsize / 16; 1411 1412 /* 1413 * We always come back and check the descriptor ring for new indirect 1414 * interrupts and other responses after running a single handler. 1415 */ 1416 for (;;) { 1417 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) { 1418 1419 rmb(); 1420 1421 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen); 1422 lq = be32toh(d->rsp.pldbuflen_qid); 1423 1424 switch (rsp_type) { 1425 case X_RSPD_TYPE_FLBUF: 1426 panic("%s: data for an iq (%p) with no freelist", 1427 __func__, iq); 1428 1429 /* NOTREACHED */ 1430 1431 case X_RSPD_TYPE_CPL: 1432 KASSERT(d->rss.opcode < NUM_CPL_CMDS, 1433 ("%s: bad opcode %02x.", __func__, 1434 d->rss.opcode)); 1435 t4_cpl_handler[d->rss.opcode](iq, &d->rss, NULL); 1436 break; 1437 1438 case X_RSPD_TYPE_INTR: 1439 /* 1440 * There are 1K interrupt-capable queues (qids 0 1441 * through 1023). A response type indicating a 1442 * forwarded interrupt with a qid >= 1K is an 1443 * iWARP async notification. 1444 */ 1445 if (__predict_true(lq >= 1024)) { 1446 t4_an_handler(iq, &d->rsp); 1447 break; 1448 } 1449 1450 q = sc->sge.iqmap[lq - sc->sge.iq_start - 1451 sc->sge.iq_base]; 1452 if (atomic_cmpset_int(&q->state, IQS_IDLE, 1453 IQS_BUSY)) { 1454 if (service_iq_fl(q, q->qsize / 16) == 0) { 1455 (void) atomic_cmpset_int(&q->state, 1456 IQS_BUSY, IQS_IDLE); 1457 } else { 1458 STAILQ_INSERT_TAIL(&iql, q, 1459 link); 1460 } 1461 } 1462 break; 1463 1464 default: 1465 KASSERT(0, 1466 ("%s: illegal response type %d on iq %p", 1467 __func__, rsp_type, iq)); 1468 log(LOG_ERR, 1469 "%s: illegal response type %d on iq %p", 1470 device_get_nameunit(sc->dev), rsp_type, iq); 1471 break; 1472 } 1473 1474 d++; 1475 if (__predict_false(++iq->cidx == iq->sidx)) { 1476 iq->cidx = 0; 1477 iq->gen ^= F_RSPD_GEN; 1478 d = &iq->desc[0]; 1479 } 1480 if (__predict_false(++ndescs == limit)) { 1481 t4_write_reg(sc, sc->sge_gts_reg, 1482 V_CIDXINC(ndescs) | 1483 V_INGRESSQID(iq->cntxt_id) | 1484 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); 1485 ndescs = 0; 1486 1487 if (budget) { 1488 return (EINPROGRESS); 1489 } 1490 } 1491 } 1492 1493 if (STAILQ_EMPTY(&iql)) 1494 break; 1495 1496 /* 1497 * Process the head only, and send it to the back of the list if 1498 * it's still not done. 1499 */ 1500 q = STAILQ_FIRST(&iql); 1501 STAILQ_REMOVE_HEAD(&iql, link); 1502 if (service_iq_fl(q, q->qsize / 8) == 0) 1503 (void) atomic_cmpset_int(&q->state, IQS_BUSY, IQS_IDLE); 1504 else 1505 STAILQ_INSERT_TAIL(&iql, q, link); 1506 } 1507 1508 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) | 1509 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params)); 1510 1511 return (0); 1512 } 1513 1514 #if defined(INET) || defined(INET6) 1515 static inline int 1516 sort_before_lro(struct lro_ctrl *lro) 1517 { 1518 1519 return (lro->lro_mbuf_max != 0); 1520 } 1521 #endif 1522 1523 #define CGBE_SHIFT_SCALE 10 1524 1525 static inline uint64_t 1526 t4_tstmp_to_ns(struct adapter *sc, uint64_t lf) 1527 { 1528 struct clock_sync *cur, dcur; 1529 uint64_t hw_clocks; 1530 uint64_t hw_clk_div; 1531 sbintime_t sbt_cur_to_prev, sbt; 1532 uint64_t hw_tstmp = lf & 0xfffffffffffffffULL; /* 60b, not 64b. */ 1533 uint32_t gen; 1534 1535 do { 1536 cur = &sc->cal_info[sc->cal_current]; 1537 gen = atomic_load_acq_int(&cur->gen); 1538 if (gen == 0) 1539 return (0); 1540 dcur = *cur; 1541 atomic_thread_fence_acq(); 1542 } while (gen != dcur.gen); 1543 1544 /* 1545 * Our goal here is to have a result that is: 1546 * 1547 * ( (cur_time - prev_time) ) 1548 * ((hw_tstmp - hw_prev) * ----------------------------- ) + prev_time 1549 * ( (hw_cur - hw_prev) ) 1550 * 1551 * With the constraints that we cannot use float and we 1552 * don't want to overflow the uint64_t numbers we are using. 1553 */ 1554 hw_clocks = hw_tstmp - dcur.hw_prev; 1555 sbt_cur_to_prev = (dcur.sbt_cur - dcur.sbt_prev); 1556 hw_clk_div = dcur.hw_cur - dcur.hw_prev; 1557 sbt = hw_clocks * sbt_cur_to_prev / hw_clk_div + dcur.sbt_prev; 1558 return (sbttons(sbt)); 1559 } 1560 1561 static inline void 1562 move_to_next_rxbuf(struct sge_fl *fl) 1563 { 1564 1565 fl->rx_offset = 0; 1566 if (__predict_false((++fl->cidx & 7) == 0)) { 1567 uint16_t cidx = fl->cidx >> 3; 1568 1569 if (__predict_false(cidx == fl->sidx)) 1570 fl->cidx = cidx = 0; 1571 fl->hw_cidx = cidx; 1572 } 1573 } 1574 1575 /* 1576 * Deals with interrupts on an iq+fl queue. 1577 */ 1578 static int 1579 service_iq_fl(struct sge_iq *iq, int budget) 1580 { 1581 struct sge_rxq *rxq = iq_to_rxq(iq); 1582 struct sge_fl *fl; 1583 struct adapter *sc = iq->adapter; 1584 struct iq_desc *d = &iq->desc[iq->cidx]; 1585 int ndescs, limit; 1586 int rsp_type, starved; 1587 uint32_t lq; 1588 uint16_t fl_hw_cidx; 1589 struct mbuf *m0; 1590 #if defined(INET) || defined(INET6) 1591 const struct timeval lro_timeout = {0, sc->lro_timeout}; 1592 struct lro_ctrl *lro = &rxq->lro; 1593 #endif 1594 1595 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq)); 1596 MPASS(iq->flags & IQ_HAS_FL); 1597 1598 ndescs = 0; 1599 #if defined(INET) || defined(INET6) 1600 if (iq->flags & IQ_ADJ_CREDIT) { 1601 MPASS(sort_before_lro(lro)); 1602 iq->flags &= ~IQ_ADJ_CREDIT; 1603 if ((d->rsp.u.type_gen & F_RSPD_GEN) != iq->gen) { 1604 tcp_lro_flush_all(lro); 1605 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(1) | 1606 V_INGRESSQID((u32)iq->cntxt_id) | 1607 V_SEINTARM(iq->intr_params)); 1608 return (0); 1609 } 1610 ndescs = 1; 1611 } 1612 #else 1613 MPASS((iq->flags & IQ_ADJ_CREDIT) == 0); 1614 #endif 1615 1616 limit = budget ? budget : iq->qsize / 16; 1617 fl = &rxq->fl; 1618 fl_hw_cidx = fl->hw_cidx; /* stable snapshot */ 1619 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) { 1620 1621 rmb(); 1622 1623 m0 = NULL; 1624 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen); 1625 lq = be32toh(d->rsp.pldbuflen_qid); 1626 1627 switch (rsp_type) { 1628 case X_RSPD_TYPE_FLBUF: 1629 if (lq & F_RSPD_NEWBUF) { 1630 if (fl->rx_offset > 0) 1631 move_to_next_rxbuf(fl); 1632 lq = G_RSPD_LEN(lq); 1633 } 1634 if (IDXDIFF(fl->hw_cidx, fl_hw_cidx, fl->sidx) > 4) { 1635 FL_LOCK(fl); 1636 refill_fl(sc, fl, 64); 1637 FL_UNLOCK(fl); 1638 fl_hw_cidx = fl->hw_cidx; 1639 } 1640 1641 if (d->rss.opcode == CPL_RX_PKT) { 1642 if (__predict_true(eth_rx(sc, rxq, d, lq) == 0)) 1643 break; 1644 goto out; 1645 } 1646 m0 = get_fl_payload(sc, fl, lq); 1647 if (__predict_false(m0 == NULL)) 1648 goto out; 1649 1650 /* fall through */ 1651 1652 case X_RSPD_TYPE_CPL: 1653 KASSERT(d->rss.opcode < NUM_CPL_CMDS, 1654 ("%s: bad opcode %02x.", __func__, d->rss.opcode)); 1655 t4_cpl_handler[d->rss.opcode](iq, &d->rss, m0); 1656 break; 1657 1658 case X_RSPD_TYPE_INTR: 1659 1660 /* 1661 * There are 1K interrupt-capable queues (qids 0 1662 * through 1023). A response type indicating a 1663 * forwarded interrupt with a qid >= 1K is an 1664 * iWARP async notification. That is the only 1665 * acceptable indirect interrupt on this queue. 1666 */ 1667 if (__predict_false(lq < 1024)) { 1668 panic("%s: indirect interrupt on iq_fl %p " 1669 "with qid %u", __func__, iq, lq); 1670 } 1671 1672 t4_an_handler(iq, &d->rsp); 1673 break; 1674 1675 default: 1676 KASSERT(0, ("%s: illegal response type %d on iq %p", 1677 __func__, rsp_type, iq)); 1678 log(LOG_ERR, "%s: illegal response type %d on iq %p", 1679 device_get_nameunit(sc->dev), rsp_type, iq); 1680 break; 1681 } 1682 1683 d++; 1684 if (__predict_false(++iq->cidx == iq->sidx)) { 1685 iq->cidx = 0; 1686 iq->gen ^= F_RSPD_GEN; 1687 d = &iq->desc[0]; 1688 } 1689 if (__predict_false(++ndescs == limit)) { 1690 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) | 1691 V_INGRESSQID(iq->cntxt_id) | 1692 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); 1693 1694 #if defined(INET) || defined(INET6) 1695 if (iq->flags & IQ_LRO_ENABLED && 1696 !sort_before_lro(lro) && 1697 sc->lro_timeout != 0) { 1698 tcp_lro_flush_inactive(lro, &lro_timeout); 1699 } 1700 #endif 1701 if (budget) 1702 return (EINPROGRESS); 1703 ndescs = 0; 1704 } 1705 } 1706 out: 1707 #if defined(INET) || defined(INET6) 1708 if (iq->flags & IQ_LRO_ENABLED) { 1709 if (ndescs > 0 && lro->lro_mbuf_count > 8) { 1710 MPASS(sort_before_lro(lro)); 1711 /* hold back one credit and don't flush LRO state */ 1712 iq->flags |= IQ_ADJ_CREDIT; 1713 ndescs--; 1714 } else { 1715 tcp_lro_flush_all(lro); 1716 } 1717 } 1718 #endif 1719 1720 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) | 1721 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params)); 1722 1723 FL_LOCK(fl); 1724 starved = refill_fl(sc, fl, 64); 1725 FL_UNLOCK(fl); 1726 if (__predict_false(starved != 0)) 1727 add_fl_to_sfl(sc, fl); 1728 1729 return (0); 1730 } 1731 1732 static inline struct cluster_metadata * 1733 cl_metadata(struct fl_sdesc *sd) 1734 { 1735 1736 return ((void *)(sd->cl + sd->moff)); 1737 } 1738 1739 static void 1740 rxb_free(struct mbuf *m) 1741 { 1742 struct cluster_metadata *clm = m->m_ext.ext_arg1; 1743 1744 uma_zfree(clm->zone, clm->cl); 1745 counter_u64_add(extfree_rels, 1); 1746 } 1747 1748 /* 1749 * The mbuf returned comes from zone_muf and carries the payload in one of these 1750 * ways 1751 * a) complete frame inside the mbuf 1752 * b) m_cljset (for clusters without metadata) 1753 * d) m_extaddref (cluster with metadata) 1754 */ 1755 static struct mbuf * 1756 get_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset, 1757 int remaining) 1758 { 1759 struct mbuf *m; 1760 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 1761 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[sd->zidx]; 1762 struct cluster_metadata *clm; 1763 int len, blen; 1764 caddr_t payload; 1765 1766 if (fl->flags & FL_BUF_PACKING) { 1767 u_int l, pad; 1768 1769 blen = rxb->size2 - fl->rx_offset; /* max possible in this buf */ 1770 len = min(remaining, blen); 1771 payload = sd->cl + fl->rx_offset; 1772 1773 l = fr_offset + len; 1774 pad = roundup2(l, fl->buf_boundary) - l; 1775 if (fl->rx_offset + len + pad < rxb->size2) 1776 blen = len + pad; 1777 MPASS(fl->rx_offset + blen <= rxb->size2); 1778 } else { 1779 MPASS(fl->rx_offset == 0); /* not packing */ 1780 blen = rxb->size1; 1781 len = min(remaining, blen); 1782 payload = sd->cl; 1783 } 1784 1785 if (fr_offset == 0) { 1786 m = m_gethdr(M_NOWAIT, MT_DATA); 1787 if (__predict_false(m == NULL)) 1788 return (NULL); 1789 m->m_pkthdr.len = remaining; 1790 } else { 1791 m = m_get(M_NOWAIT, MT_DATA); 1792 if (__predict_false(m == NULL)) 1793 return (NULL); 1794 } 1795 m->m_len = len; 1796 kmsan_mark(payload, len, KMSAN_STATE_INITED); 1797 1798 if (sc->sc_do_rxcopy && len < RX_COPY_THRESHOLD) { 1799 /* copy data to mbuf */ 1800 bcopy(payload, mtod(m, caddr_t), len); 1801 if (fl->flags & FL_BUF_PACKING) { 1802 fl->rx_offset += blen; 1803 MPASS(fl->rx_offset <= rxb->size2); 1804 if (fl->rx_offset < rxb->size2) 1805 return (m); /* without advancing the cidx */ 1806 } 1807 } else if (fl->flags & FL_BUF_PACKING) { 1808 clm = cl_metadata(sd); 1809 if (sd->nmbuf++ == 0) { 1810 clm->refcount = 1; 1811 clm->zone = rxb->zone; 1812 clm->cl = sd->cl; 1813 counter_u64_add(extfree_refs, 1); 1814 } 1815 m_extaddref(m, payload, blen, &clm->refcount, rxb_free, clm, 1816 NULL); 1817 1818 fl->rx_offset += blen; 1819 MPASS(fl->rx_offset <= rxb->size2); 1820 if (fl->rx_offset < rxb->size2) 1821 return (m); /* without advancing the cidx */ 1822 } else { 1823 m_cljset(m, sd->cl, rxb->type); 1824 sd->cl = NULL; /* consumed, not a recycle candidate */ 1825 } 1826 1827 move_to_next_rxbuf(fl); 1828 1829 return (m); 1830 } 1831 1832 static struct mbuf * 1833 get_fl_payload(struct adapter *sc, struct sge_fl *fl, const u_int plen) 1834 { 1835 struct mbuf *m0, *m, **pnext; 1836 u_int remaining; 1837 1838 if (__predict_false(fl->flags & FL_BUF_RESUME)) { 1839 M_ASSERTPKTHDR(fl->m0); 1840 MPASS(fl->m0->m_pkthdr.len == plen); 1841 MPASS(fl->remaining < plen); 1842 1843 m0 = fl->m0; 1844 pnext = fl->pnext; 1845 remaining = fl->remaining; 1846 fl->flags &= ~FL_BUF_RESUME; 1847 goto get_segment; 1848 } 1849 1850 /* 1851 * Payload starts at rx_offset in the current hw buffer. Its length is 1852 * 'len' and it may span multiple hw buffers. 1853 */ 1854 1855 m0 = get_scatter_segment(sc, fl, 0, plen); 1856 if (m0 == NULL) 1857 return (NULL); 1858 remaining = plen - m0->m_len; 1859 pnext = &m0->m_next; 1860 while (remaining > 0) { 1861 get_segment: 1862 MPASS(fl->rx_offset == 0); 1863 m = get_scatter_segment(sc, fl, plen - remaining, remaining); 1864 if (__predict_false(m == NULL)) { 1865 fl->m0 = m0; 1866 fl->pnext = pnext; 1867 fl->remaining = remaining; 1868 fl->flags |= FL_BUF_RESUME; 1869 return (NULL); 1870 } 1871 *pnext = m; 1872 pnext = &m->m_next; 1873 remaining -= m->m_len; 1874 } 1875 *pnext = NULL; 1876 1877 M_ASSERTPKTHDR(m0); 1878 return (m0); 1879 } 1880 1881 static int 1882 skip_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset, 1883 int remaining) 1884 { 1885 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 1886 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[sd->zidx]; 1887 int len, blen; 1888 1889 if (fl->flags & FL_BUF_PACKING) { 1890 u_int l, pad; 1891 1892 blen = rxb->size2 - fl->rx_offset; /* max possible in this buf */ 1893 len = min(remaining, blen); 1894 1895 l = fr_offset + len; 1896 pad = roundup2(l, fl->buf_boundary) - l; 1897 if (fl->rx_offset + len + pad < rxb->size2) 1898 blen = len + pad; 1899 fl->rx_offset += blen; 1900 MPASS(fl->rx_offset <= rxb->size2); 1901 if (fl->rx_offset < rxb->size2) 1902 return (len); /* without advancing the cidx */ 1903 } else { 1904 MPASS(fl->rx_offset == 0); /* not packing */ 1905 blen = rxb->size1; 1906 len = min(remaining, blen); 1907 } 1908 move_to_next_rxbuf(fl); 1909 return (len); 1910 } 1911 1912 static inline void 1913 skip_fl_payload(struct adapter *sc, struct sge_fl *fl, int plen) 1914 { 1915 int remaining, fr_offset, len; 1916 1917 fr_offset = 0; 1918 remaining = plen; 1919 while (remaining > 0) { 1920 len = skip_scatter_segment(sc, fl, fr_offset, remaining); 1921 fr_offset += len; 1922 remaining -= len; 1923 } 1924 } 1925 1926 static inline int 1927 get_segment_len(struct adapter *sc, struct sge_fl *fl, int plen) 1928 { 1929 int len; 1930 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 1931 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[sd->zidx]; 1932 1933 if (fl->flags & FL_BUF_PACKING) 1934 len = rxb->size2 - fl->rx_offset; 1935 else 1936 len = rxb->size1; 1937 1938 return (min(plen, len)); 1939 } 1940 1941 static int 1942 eth_rx(struct adapter *sc, struct sge_rxq *rxq, const struct iq_desc *d, 1943 u_int plen) 1944 { 1945 struct mbuf *m0; 1946 struct ifnet *ifp = rxq->ifp; 1947 struct sge_fl *fl = &rxq->fl; 1948 struct vi_info *vi = ifp->if_softc; 1949 const struct cpl_rx_pkt *cpl; 1950 #if defined(INET) || defined(INET6) 1951 struct lro_ctrl *lro = &rxq->lro; 1952 #endif 1953 uint16_t err_vec, tnl_type, tnlhdr_len; 1954 static const int sw_hashtype[4][2] = { 1955 {M_HASHTYPE_NONE, M_HASHTYPE_NONE}, 1956 {M_HASHTYPE_RSS_IPV4, M_HASHTYPE_RSS_IPV6}, 1957 {M_HASHTYPE_RSS_TCP_IPV4, M_HASHTYPE_RSS_TCP_IPV6}, 1958 {M_HASHTYPE_RSS_UDP_IPV4, M_HASHTYPE_RSS_UDP_IPV6}, 1959 }; 1960 static const int sw_csum_flags[2][2] = { 1961 { 1962 /* IP, inner IP */ 1963 CSUM_ENCAP_VXLAN | 1964 CSUM_L3_CALC | CSUM_L3_VALID | 1965 CSUM_L4_CALC | CSUM_L4_VALID | 1966 CSUM_INNER_L3_CALC | CSUM_INNER_L3_VALID | 1967 CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID, 1968 1969 /* IP, inner IP6 */ 1970 CSUM_ENCAP_VXLAN | 1971 CSUM_L3_CALC | CSUM_L3_VALID | 1972 CSUM_L4_CALC | CSUM_L4_VALID | 1973 CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID, 1974 }, 1975 { 1976 /* IP6, inner IP */ 1977 CSUM_ENCAP_VXLAN | 1978 CSUM_L4_CALC | CSUM_L4_VALID | 1979 CSUM_INNER_L3_CALC | CSUM_INNER_L3_VALID | 1980 CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID, 1981 1982 /* IP6, inner IP6 */ 1983 CSUM_ENCAP_VXLAN | 1984 CSUM_L4_CALC | CSUM_L4_VALID | 1985 CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID, 1986 }, 1987 }; 1988 1989 MPASS(plen > sc->params.sge.fl_pktshift); 1990 if (vi->pfil != NULL && PFIL_HOOKED_IN(vi->pfil) && 1991 __predict_true((fl->flags & FL_BUF_RESUME) == 0)) { 1992 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 1993 caddr_t frame; 1994 int rc, slen; 1995 1996 slen = get_segment_len(sc, fl, plen) - 1997 sc->params.sge.fl_pktshift; 1998 frame = sd->cl + fl->rx_offset + sc->params.sge.fl_pktshift; 1999 CURVNET_SET_QUIET(ifp->if_vnet); 2000 rc = pfil_run_hooks(vi->pfil, frame, ifp, 2001 slen | PFIL_MEMPTR | PFIL_IN, NULL); 2002 CURVNET_RESTORE(); 2003 if (rc == PFIL_DROPPED || rc == PFIL_CONSUMED) { 2004 skip_fl_payload(sc, fl, plen); 2005 return (0); 2006 } 2007 if (rc == PFIL_REALLOCED) { 2008 skip_fl_payload(sc, fl, plen); 2009 m0 = pfil_mem2mbuf(frame); 2010 goto have_mbuf; 2011 } 2012 } 2013 2014 m0 = get_fl_payload(sc, fl, plen); 2015 if (__predict_false(m0 == NULL)) 2016 return (ENOMEM); 2017 2018 m0->m_pkthdr.len -= sc->params.sge.fl_pktshift; 2019 m0->m_len -= sc->params.sge.fl_pktshift; 2020 m0->m_data += sc->params.sge.fl_pktshift; 2021 2022 have_mbuf: 2023 m0->m_pkthdr.rcvif = ifp; 2024 M_HASHTYPE_SET(m0, sw_hashtype[d->rss.hash_type][d->rss.ipv6]); 2025 m0->m_pkthdr.flowid = be32toh(d->rss.hash_val); 2026 2027 cpl = (const void *)(&d->rss + 1); 2028 if (sc->params.tp.rx_pkt_encap) { 2029 const uint16_t ev = be16toh(cpl->err_vec); 2030 2031 err_vec = G_T6_COMPR_RXERR_VEC(ev); 2032 tnl_type = G_T6_RX_TNL_TYPE(ev); 2033 tnlhdr_len = G_T6_RX_TNLHDR_LEN(ev); 2034 } else { 2035 err_vec = be16toh(cpl->err_vec); 2036 tnl_type = 0; 2037 tnlhdr_len = 0; 2038 } 2039 if (cpl->csum_calc && err_vec == 0) { 2040 int ipv6 = !!(cpl->l2info & htobe32(F_RXF_IP6)); 2041 2042 /* checksum(s) calculated and found to be correct. */ 2043 2044 MPASS((cpl->l2info & htobe32(F_RXF_IP)) ^ 2045 (cpl->l2info & htobe32(F_RXF_IP6))); 2046 m0->m_pkthdr.csum_data = be16toh(cpl->csum); 2047 if (tnl_type == 0) { 2048 if (!ipv6 && ifp->if_capenable & IFCAP_RXCSUM) { 2049 m0->m_pkthdr.csum_flags = CSUM_L3_CALC | 2050 CSUM_L3_VALID | CSUM_L4_CALC | 2051 CSUM_L4_VALID; 2052 } else if (ipv6 && ifp->if_capenable & IFCAP_RXCSUM_IPV6) { 2053 m0->m_pkthdr.csum_flags = CSUM_L4_CALC | 2054 CSUM_L4_VALID; 2055 } 2056 rxq->rxcsum++; 2057 } else { 2058 MPASS(tnl_type == RX_PKT_TNL_TYPE_VXLAN); 2059 2060 M_HASHTYPE_SETINNER(m0); 2061 if (__predict_false(cpl->ip_frag)) { 2062 /* 2063 * csum_data is for the inner frame (which is an 2064 * IP fragment) and is not 0xffff. There is no 2065 * way to pass the inner csum_data to the stack. 2066 * We don't want the stack to use the inner 2067 * csum_data to validate the outer frame or it 2068 * will get rejected. So we fix csum_data here 2069 * and let sw do the checksum of inner IP 2070 * fragments. 2071 * 2072 * XXX: Need 32b for csum_data2 in an rx mbuf. 2073 * Maybe stuff it into rcv_tstmp? 2074 */ 2075 m0->m_pkthdr.csum_data = 0xffff; 2076 if (ipv6) { 2077 m0->m_pkthdr.csum_flags = CSUM_L4_CALC | 2078 CSUM_L4_VALID; 2079 } else { 2080 m0->m_pkthdr.csum_flags = CSUM_L3_CALC | 2081 CSUM_L3_VALID | CSUM_L4_CALC | 2082 CSUM_L4_VALID; 2083 } 2084 } else { 2085 int outer_ipv6; 2086 2087 MPASS(m0->m_pkthdr.csum_data == 0xffff); 2088 2089 outer_ipv6 = tnlhdr_len >= 2090 sizeof(struct ether_header) + 2091 sizeof(struct ip6_hdr); 2092 m0->m_pkthdr.csum_flags = 2093 sw_csum_flags[outer_ipv6][ipv6]; 2094 } 2095 rxq->vxlan_rxcsum++; 2096 } 2097 } 2098 2099 if (cpl->vlan_ex) { 2100 m0->m_pkthdr.ether_vtag = be16toh(cpl->vlan); 2101 m0->m_flags |= M_VLANTAG; 2102 rxq->vlan_extraction++; 2103 } 2104 2105 if (rxq->iq.flags & IQ_RX_TIMESTAMP) { 2106 /* 2107 * Fill up rcv_tstmp but do not set M_TSTMP as 2108 * long as we get a non-zero back from t4_tstmp_to_ns(). 2109 */ 2110 m0->m_pkthdr.rcv_tstmp = t4_tstmp_to_ns(sc, 2111 be64toh(d->rsp.u.last_flit)); 2112 if (m0->m_pkthdr.rcv_tstmp != 0) 2113 m0->m_flags |= M_TSTMP; 2114 } 2115 2116 #ifdef NUMA 2117 m0->m_pkthdr.numa_domain = ifp->if_numa_domain; 2118 #endif 2119 #if defined(INET) || defined(INET6) 2120 if (rxq->iq.flags & IQ_LRO_ENABLED && tnl_type == 0 && 2121 (M_HASHTYPE_GET(m0) == M_HASHTYPE_RSS_TCP_IPV4 || 2122 M_HASHTYPE_GET(m0) == M_HASHTYPE_RSS_TCP_IPV6)) { 2123 if (sort_before_lro(lro)) { 2124 tcp_lro_queue_mbuf(lro, m0); 2125 return (0); /* queued for sort, then LRO */ 2126 } 2127 if (tcp_lro_rx(lro, m0, 0) == 0) 2128 return (0); /* queued for LRO */ 2129 } 2130 #endif 2131 ifp->if_input(ifp, m0); 2132 2133 return (0); 2134 } 2135 2136 /* 2137 * Must drain the wrq or make sure that someone else will. 2138 */ 2139 static void 2140 wrq_tx_drain(void *arg, int n) 2141 { 2142 struct sge_wrq *wrq = arg; 2143 struct sge_eq *eq = &wrq->eq; 2144 2145 EQ_LOCK(eq); 2146 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 2147 drain_wrq_wr_list(wrq->adapter, wrq); 2148 EQ_UNLOCK(eq); 2149 } 2150 2151 static void 2152 drain_wrq_wr_list(struct adapter *sc, struct sge_wrq *wrq) 2153 { 2154 struct sge_eq *eq = &wrq->eq; 2155 u_int available, dbdiff; /* # of hardware descriptors */ 2156 u_int n; 2157 struct wrqe *wr; 2158 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */ 2159 2160 EQ_LOCK_ASSERT_OWNED(eq); 2161 MPASS(TAILQ_EMPTY(&wrq->incomplete_wrs)); 2162 wr = STAILQ_FIRST(&wrq->wr_list); 2163 MPASS(wr != NULL); /* Must be called with something useful to do */ 2164 MPASS(eq->pidx == eq->dbidx); 2165 dbdiff = 0; 2166 2167 do { 2168 eq->cidx = read_hw_cidx(eq); 2169 if (eq->pidx == eq->cidx) 2170 available = eq->sidx - 1; 2171 else 2172 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2173 2174 MPASS(wr->wrq == wrq); 2175 n = howmany(wr->wr_len, EQ_ESIZE); 2176 if (available < n) 2177 break; 2178 2179 dst = (void *)&eq->desc[eq->pidx]; 2180 if (__predict_true(eq->sidx - eq->pidx > n)) { 2181 /* Won't wrap, won't end exactly at the status page. */ 2182 bcopy(&wr->wr[0], dst, wr->wr_len); 2183 eq->pidx += n; 2184 } else { 2185 int first_portion = (eq->sidx - eq->pidx) * EQ_ESIZE; 2186 2187 bcopy(&wr->wr[0], dst, first_portion); 2188 if (wr->wr_len > first_portion) { 2189 bcopy(&wr->wr[first_portion], &eq->desc[0], 2190 wr->wr_len - first_portion); 2191 } 2192 eq->pidx = n - (eq->sidx - eq->pidx); 2193 } 2194 wrq->tx_wrs_copied++; 2195 2196 if (available < eq->sidx / 4 && 2197 atomic_cmpset_int(&eq->equiq, 0, 1)) { 2198 /* 2199 * XXX: This is not 100% reliable with some 2200 * types of WRs. But this is a very unusual 2201 * situation for an ofld/ctrl queue anyway. 2202 */ 2203 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ | 2204 F_FW_WR_EQUEQ); 2205 } 2206 2207 dbdiff += n; 2208 if (dbdiff >= 16) { 2209 ring_eq_db(sc, eq, dbdiff); 2210 dbdiff = 0; 2211 } 2212 2213 STAILQ_REMOVE_HEAD(&wrq->wr_list, link); 2214 free_wrqe(wr); 2215 MPASS(wrq->nwr_pending > 0); 2216 wrq->nwr_pending--; 2217 MPASS(wrq->ndesc_needed >= n); 2218 wrq->ndesc_needed -= n; 2219 } while ((wr = STAILQ_FIRST(&wrq->wr_list)) != NULL); 2220 2221 if (dbdiff) 2222 ring_eq_db(sc, eq, dbdiff); 2223 } 2224 2225 /* 2226 * Doesn't fail. Holds on to work requests it can't send right away. 2227 */ 2228 void 2229 t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, struct wrqe *wr) 2230 { 2231 #ifdef INVARIANTS 2232 struct sge_eq *eq = &wrq->eq; 2233 #endif 2234 2235 EQ_LOCK_ASSERT_OWNED(eq); 2236 MPASS(wr != NULL); 2237 MPASS(wr->wr_len > 0 && wr->wr_len <= SGE_MAX_WR_LEN); 2238 MPASS((wr->wr_len & 0x7) == 0); 2239 2240 STAILQ_INSERT_TAIL(&wrq->wr_list, wr, link); 2241 wrq->nwr_pending++; 2242 wrq->ndesc_needed += howmany(wr->wr_len, EQ_ESIZE); 2243 2244 if (!TAILQ_EMPTY(&wrq->incomplete_wrs)) 2245 return; /* commit_wrq_wr will drain wr_list as well. */ 2246 2247 drain_wrq_wr_list(sc, wrq); 2248 2249 /* Doorbell must have caught up to the pidx. */ 2250 MPASS(eq->pidx == eq->dbidx); 2251 } 2252 2253 void 2254 t4_update_fl_bufsize(struct ifnet *ifp) 2255 { 2256 struct vi_info *vi = ifp->if_softc; 2257 struct adapter *sc = vi->adapter; 2258 struct sge_rxq *rxq; 2259 #ifdef TCP_OFFLOAD 2260 struct sge_ofld_rxq *ofld_rxq; 2261 #endif 2262 struct sge_fl *fl; 2263 int i, maxp; 2264 2265 maxp = max_rx_payload(sc, ifp, false); 2266 for_each_rxq(vi, i, rxq) { 2267 fl = &rxq->fl; 2268 2269 FL_LOCK(fl); 2270 fl->zidx = find_refill_source(sc, maxp, 2271 fl->flags & FL_BUF_PACKING); 2272 FL_UNLOCK(fl); 2273 } 2274 #ifdef TCP_OFFLOAD 2275 maxp = max_rx_payload(sc, ifp, true); 2276 for_each_ofld_rxq(vi, i, ofld_rxq) { 2277 fl = &ofld_rxq->fl; 2278 2279 FL_LOCK(fl); 2280 fl->zidx = find_refill_source(sc, maxp, 2281 fl->flags & FL_BUF_PACKING); 2282 FL_UNLOCK(fl); 2283 } 2284 #endif 2285 } 2286 2287 static inline int 2288 mbuf_nsegs(struct mbuf *m) 2289 { 2290 2291 M_ASSERTPKTHDR(m); 2292 KASSERT(m->m_pkthdr.inner_l5hlen > 0, 2293 ("%s: mbuf %p missing information on # of segments.", __func__, m)); 2294 2295 return (m->m_pkthdr.inner_l5hlen); 2296 } 2297 2298 static inline void 2299 set_mbuf_nsegs(struct mbuf *m, uint8_t nsegs) 2300 { 2301 2302 M_ASSERTPKTHDR(m); 2303 m->m_pkthdr.inner_l5hlen = nsegs; 2304 } 2305 2306 static inline int 2307 mbuf_cflags(struct mbuf *m) 2308 { 2309 2310 M_ASSERTPKTHDR(m); 2311 return (m->m_pkthdr.PH_loc.eight[4]); 2312 } 2313 2314 static inline void 2315 set_mbuf_cflags(struct mbuf *m, uint8_t flags) 2316 { 2317 2318 M_ASSERTPKTHDR(m); 2319 m->m_pkthdr.PH_loc.eight[4] = flags; 2320 } 2321 2322 static inline int 2323 mbuf_len16(struct mbuf *m) 2324 { 2325 int n; 2326 2327 M_ASSERTPKTHDR(m); 2328 n = m->m_pkthdr.PH_loc.eight[0]; 2329 if (!(mbuf_cflags(m) & MC_TLS)) 2330 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16); 2331 2332 return (n); 2333 } 2334 2335 static inline void 2336 set_mbuf_len16(struct mbuf *m, uint8_t len16) 2337 { 2338 2339 M_ASSERTPKTHDR(m); 2340 if (!(mbuf_cflags(m) & MC_TLS)) 2341 MPASS(len16 > 0 && len16 <= SGE_MAX_WR_LEN / 16); 2342 m->m_pkthdr.PH_loc.eight[0] = len16; 2343 } 2344 2345 #ifdef RATELIMIT 2346 static inline int 2347 mbuf_eo_nsegs(struct mbuf *m) 2348 { 2349 2350 M_ASSERTPKTHDR(m); 2351 return (m->m_pkthdr.PH_loc.eight[1]); 2352 } 2353 2354 #if defined(INET) || defined(INET6) 2355 static inline void 2356 set_mbuf_eo_nsegs(struct mbuf *m, uint8_t nsegs) 2357 { 2358 2359 M_ASSERTPKTHDR(m); 2360 m->m_pkthdr.PH_loc.eight[1] = nsegs; 2361 } 2362 #endif 2363 2364 static inline int 2365 mbuf_eo_len16(struct mbuf *m) 2366 { 2367 int n; 2368 2369 M_ASSERTPKTHDR(m); 2370 n = m->m_pkthdr.PH_loc.eight[2]; 2371 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16); 2372 2373 return (n); 2374 } 2375 2376 #if defined(INET) || defined(INET6) 2377 static inline void 2378 set_mbuf_eo_len16(struct mbuf *m, uint8_t len16) 2379 { 2380 2381 M_ASSERTPKTHDR(m); 2382 m->m_pkthdr.PH_loc.eight[2] = len16; 2383 } 2384 #endif 2385 2386 static inline int 2387 mbuf_eo_tsclk_tsoff(struct mbuf *m) 2388 { 2389 2390 M_ASSERTPKTHDR(m); 2391 return (m->m_pkthdr.PH_loc.eight[3]); 2392 } 2393 2394 #if defined(INET) || defined(INET6) 2395 static inline void 2396 set_mbuf_eo_tsclk_tsoff(struct mbuf *m, uint8_t tsclk_tsoff) 2397 { 2398 2399 M_ASSERTPKTHDR(m); 2400 m->m_pkthdr.PH_loc.eight[3] = tsclk_tsoff; 2401 } 2402 #endif 2403 2404 static inline int 2405 needs_eo(struct m_snd_tag *mst) 2406 { 2407 2408 return (mst != NULL && mst->sw->type == IF_SND_TAG_TYPE_RATE_LIMIT); 2409 } 2410 #endif 2411 2412 /* 2413 * Try to allocate an mbuf to contain a raw work request. To make it 2414 * easy to construct the work request, don't allocate a chain but a 2415 * single mbuf. 2416 */ 2417 struct mbuf * 2418 alloc_wr_mbuf(int len, int how) 2419 { 2420 struct mbuf *m; 2421 2422 if (len <= MHLEN) 2423 m = m_gethdr(how, MT_DATA); 2424 else if (len <= MCLBYTES) 2425 m = m_getcl(how, MT_DATA, M_PKTHDR); 2426 else 2427 m = NULL; 2428 if (m == NULL) 2429 return (NULL); 2430 m->m_pkthdr.len = len; 2431 m->m_len = len; 2432 set_mbuf_cflags(m, MC_RAW_WR); 2433 set_mbuf_len16(m, howmany(len, 16)); 2434 return (m); 2435 } 2436 2437 static inline bool 2438 needs_hwcsum(struct mbuf *m) 2439 { 2440 const uint32_t csum_flags = CSUM_IP | CSUM_IP_UDP | CSUM_IP_TCP | 2441 CSUM_IP_TSO | CSUM_INNER_IP | CSUM_INNER_IP_UDP | 2442 CSUM_INNER_IP_TCP | CSUM_INNER_IP_TSO | CSUM_IP6_UDP | 2443 CSUM_IP6_TCP | CSUM_IP6_TSO | CSUM_INNER_IP6_UDP | 2444 CSUM_INNER_IP6_TCP | CSUM_INNER_IP6_TSO; 2445 2446 M_ASSERTPKTHDR(m); 2447 2448 return (m->m_pkthdr.csum_flags & csum_flags); 2449 } 2450 2451 static inline bool 2452 needs_tso(struct mbuf *m) 2453 { 2454 const uint32_t csum_flags = CSUM_IP_TSO | CSUM_IP6_TSO | 2455 CSUM_INNER_IP_TSO | CSUM_INNER_IP6_TSO; 2456 2457 M_ASSERTPKTHDR(m); 2458 2459 return (m->m_pkthdr.csum_flags & csum_flags); 2460 } 2461 2462 static inline bool 2463 needs_vxlan_csum(struct mbuf *m) 2464 { 2465 2466 M_ASSERTPKTHDR(m); 2467 2468 return (m->m_pkthdr.csum_flags & CSUM_ENCAP_VXLAN); 2469 } 2470 2471 static inline bool 2472 needs_vxlan_tso(struct mbuf *m) 2473 { 2474 const uint32_t csum_flags = CSUM_ENCAP_VXLAN | CSUM_INNER_IP_TSO | 2475 CSUM_INNER_IP6_TSO; 2476 2477 M_ASSERTPKTHDR(m); 2478 2479 return ((m->m_pkthdr.csum_flags & csum_flags) != 0 && 2480 (m->m_pkthdr.csum_flags & csum_flags) != CSUM_ENCAP_VXLAN); 2481 } 2482 2483 #if defined(INET) || defined(INET6) 2484 static inline bool 2485 needs_inner_tcp_csum(struct mbuf *m) 2486 { 2487 const uint32_t csum_flags = CSUM_INNER_IP_TSO | CSUM_INNER_IP6_TSO; 2488 2489 M_ASSERTPKTHDR(m); 2490 2491 return (m->m_pkthdr.csum_flags & csum_flags); 2492 } 2493 #endif 2494 2495 static inline bool 2496 needs_l3_csum(struct mbuf *m) 2497 { 2498 const uint32_t csum_flags = CSUM_IP | CSUM_IP_TSO | CSUM_INNER_IP | 2499 CSUM_INNER_IP_TSO; 2500 2501 M_ASSERTPKTHDR(m); 2502 2503 return (m->m_pkthdr.csum_flags & csum_flags); 2504 } 2505 2506 static inline bool 2507 needs_outer_tcp_csum(struct mbuf *m) 2508 { 2509 const uint32_t csum_flags = CSUM_IP_TCP | CSUM_IP_TSO | CSUM_IP6_TCP | 2510 CSUM_IP6_TSO; 2511 2512 M_ASSERTPKTHDR(m); 2513 2514 return (m->m_pkthdr.csum_flags & csum_flags); 2515 } 2516 2517 #ifdef RATELIMIT 2518 static inline bool 2519 needs_outer_l4_csum(struct mbuf *m) 2520 { 2521 const uint32_t csum_flags = CSUM_IP_UDP | CSUM_IP_TCP | CSUM_IP_TSO | 2522 CSUM_IP6_UDP | CSUM_IP6_TCP | CSUM_IP6_TSO; 2523 2524 M_ASSERTPKTHDR(m); 2525 2526 return (m->m_pkthdr.csum_flags & csum_flags); 2527 } 2528 2529 static inline bool 2530 needs_outer_udp_csum(struct mbuf *m) 2531 { 2532 const uint32_t csum_flags = CSUM_IP_UDP | CSUM_IP6_UDP; 2533 2534 M_ASSERTPKTHDR(m); 2535 2536 return (m->m_pkthdr.csum_flags & csum_flags); 2537 } 2538 #endif 2539 2540 static inline bool 2541 needs_vlan_insertion(struct mbuf *m) 2542 { 2543 2544 M_ASSERTPKTHDR(m); 2545 2546 return (m->m_flags & M_VLANTAG); 2547 } 2548 2549 #if defined(INET) || defined(INET6) 2550 static void * 2551 m_advance(struct mbuf **pm, int *poffset, int len) 2552 { 2553 struct mbuf *m = *pm; 2554 int offset = *poffset; 2555 uintptr_t p = 0; 2556 2557 MPASS(len > 0); 2558 2559 for (;;) { 2560 if (offset + len < m->m_len) { 2561 offset += len; 2562 p = mtod(m, uintptr_t) + offset; 2563 break; 2564 } 2565 len -= m->m_len - offset; 2566 m = m->m_next; 2567 offset = 0; 2568 MPASS(m != NULL); 2569 } 2570 *poffset = offset; 2571 *pm = m; 2572 return ((void *)p); 2573 } 2574 #endif 2575 2576 static inline int 2577 count_mbuf_ext_pgs(struct mbuf *m, int skip, vm_paddr_t *nextaddr) 2578 { 2579 vm_paddr_t paddr; 2580 int i, len, off, pglen, pgoff, seglen, segoff; 2581 int nsegs = 0; 2582 2583 M_ASSERTEXTPG(m); 2584 off = mtod(m, vm_offset_t); 2585 len = m->m_len; 2586 off += skip; 2587 len -= skip; 2588 2589 if (m->m_epg_hdrlen != 0) { 2590 if (off >= m->m_epg_hdrlen) { 2591 off -= m->m_epg_hdrlen; 2592 } else { 2593 seglen = m->m_epg_hdrlen - off; 2594 segoff = off; 2595 seglen = min(seglen, len); 2596 off = 0; 2597 len -= seglen; 2598 paddr = pmap_kextract( 2599 (vm_offset_t)&m->m_epg_hdr[segoff]); 2600 if (*nextaddr != paddr) 2601 nsegs++; 2602 *nextaddr = paddr + seglen; 2603 } 2604 } 2605 pgoff = m->m_epg_1st_off; 2606 for (i = 0; i < m->m_epg_npgs && len > 0; i++) { 2607 pglen = m_epg_pagelen(m, i, pgoff); 2608 if (off >= pglen) { 2609 off -= pglen; 2610 pgoff = 0; 2611 continue; 2612 } 2613 seglen = pglen - off; 2614 segoff = pgoff + off; 2615 off = 0; 2616 seglen = min(seglen, len); 2617 len -= seglen; 2618 paddr = m->m_epg_pa[i] + segoff; 2619 if (*nextaddr != paddr) 2620 nsegs++; 2621 *nextaddr = paddr + seglen; 2622 pgoff = 0; 2623 }; 2624 if (len != 0) { 2625 seglen = min(len, m->m_epg_trllen - off); 2626 len -= seglen; 2627 paddr = pmap_kextract((vm_offset_t)&m->m_epg_trail[off]); 2628 if (*nextaddr != paddr) 2629 nsegs++; 2630 *nextaddr = paddr + seglen; 2631 } 2632 2633 return (nsegs); 2634 } 2635 2636 2637 /* 2638 * Can deal with empty mbufs in the chain that have m_len = 0, but the chain 2639 * must have at least one mbuf that's not empty. It is possible for this 2640 * routine to return 0 if skip accounts for all the contents of the mbuf chain. 2641 */ 2642 static inline int 2643 count_mbuf_nsegs(struct mbuf *m, int skip, uint8_t *cflags) 2644 { 2645 vm_paddr_t nextaddr, paddr; 2646 vm_offset_t va; 2647 int len, nsegs; 2648 2649 M_ASSERTPKTHDR(m); 2650 MPASS(m->m_pkthdr.len > 0); 2651 MPASS(m->m_pkthdr.len >= skip); 2652 2653 nsegs = 0; 2654 nextaddr = 0; 2655 for (; m; m = m->m_next) { 2656 len = m->m_len; 2657 if (__predict_false(len == 0)) 2658 continue; 2659 if (skip >= len) { 2660 skip -= len; 2661 continue; 2662 } 2663 if ((m->m_flags & M_EXTPG) != 0) { 2664 *cflags |= MC_NOMAP; 2665 nsegs += count_mbuf_ext_pgs(m, skip, &nextaddr); 2666 skip = 0; 2667 continue; 2668 } 2669 va = mtod(m, vm_offset_t) + skip; 2670 len -= skip; 2671 skip = 0; 2672 paddr = pmap_kextract(va); 2673 nsegs += sglist_count((void *)(uintptr_t)va, len); 2674 if (paddr == nextaddr) 2675 nsegs--; 2676 nextaddr = pmap_kextract(va + len - 1) + 1; 2677 } 2678 2679 return (nsegs); 2680 } 2681 2682 /* 2683 * The maximum number of segments that can fit in a WR. 2684 */ 2685 static int 2686 max_nsegs_allowed(struct mbuf *m, bool vm_wr) 2687 { 2688 2689 if (vm_wr) { 2690 if (needs_tso(m)) 2691 return (TX_SGL_SEGS_VM_TSO); 2692 return (TX_SGL_SEGS_VM); 2693 } 2694 2695 if (needs_tso(m)) { 2696 if (needs_vxlan_tso(m)) 2697 return (TX_SGL_SEGS_VXLAN_TSO); 2698 else 2699 return (TX_SGL_SEGS_TSO); 2700 } 2701 2702 return (TX_SGL_SEGS); 2703 } 2704 2705 static struct timeval txerr_ratecheck = {0}; 2706 static const struct timeval txerr_interval = {3, 0}; 2707 2708 /* 2709 * Analyze the mbuf to determine its tx needs. The mbuf passed in may change: 2710 * a) caller can assume it's been freed if this function returns with an error. 2711 * b) it may get defragged up if the gather list is too long for the hardware. 2712 */ 2713 int 2714 parse_pkt(struct mbuf **mp, bool vm_wr) 2715 { 2716 struct mbuf *m0 = *mp, *m; 2717 int rc, nsegs, defragged = 0; 2718 struct ether_header *eh; 2719 #ifdef INET 2720 void *l3hdr; 2721 #endif 2722 #if defined(INET) || defined(INET6) 2723 int offset; 2724 struct tcphdr *tcp; 2725 #endif 2726 #if defined(KERN_TLS) || defined(RATELIMIT) 2727 struct m_snd_tag *mst; 2728 #endif 2729 uint16_t eh_type; 2730 uint8_t cflags; 2731 2732 cflags = 0; 2733 M_ASSERTPKTHDR(m0); 2734 if (__predict_false(m0->m_pkthdr.len < ETHER_HDR_LEN)) { 2735 rc = EINVAL; 2736 fail: 2737 m_freem(m0); 2738 *mp = NULL; 2739 return (rc); 2740 } 2741 restart: 2742 /* 2743 * First count the number of gather list segments in the payload. 2744 * Defrag the mbuf if nsegs exceeds the hardware limit. 2745 */ 2746 M_ASSERTPKTHDR(m0); 2747 MPASS(m0->m_pkthdr.len > 0); 2748 nsegs = count_mbuf_nsegs(m0, 0, &cflags); 2749 #if defined(KERN_TLS) || defined(RATELIMIT) 2750 if (m0->m_pkthdr.csum_flags & CSUM_SND_TAG) 2751 mst = m0->m_pkthdr.snd_tag; 2752 else 2753 mst = NULL; 2754 #endif 2755 #ifdef KERN_TLS 2756 if (mst != NULL && mst->sw->type == IF_SND_TAG_TYPE_TLS) { 2757 int len16; 2758 2759 cflags |= MC_TLS; 2760 set_mbuf_cflags(m0, cflags); 2761 rc = t6_ktls_parse_pkt(m0, &nsegs, &len16); 2762 if (rc != 0) 2763 goto fail; 2764 set_mbuf_nsegs(m0, nsegs); 2765 set_mbuf_len16(m0, len16); 2766 return (0); 2767 } 2768 #endif 2769 if (nsegs > max_nsegs_allowed(m0, vm_wr)) { 2770 if (defragged++ > 0) { 2771 rc = EFBIG; 2772 goto fail; 2773 } 2774 counter_u64_add(defrags, 1); 2775 if ((m = m_defrag(m0, M_NOWAIT)) == NULL) { 2776 rc = ENOMEM; 2777 goto fail; 2778 } 2779 *mp = m0 = m; /* update caller's copy after defrag */ 2780 goto restart; 2781 } 2782 2783 if (__predict_false(nsegs > 2 && m0->m_pkthdr.len <= MHLEN && 2784 !(cflags & MC_NOMAP))) { 2785 counter_u64_add(pullups, 1); 2786 m0 = m_pullup(m0, m0->m_pkthdr.len); 2787 if (m0 == NULL) { 2788 /* Should have left well enough alone. */ 2789 rc = EFBIG; 2790 goto fail; 2791 } 2792 *mp = m0; /* update caller's copy after pullup */ 2793 goto restart; 2794 } 2795 set_mbuf_nsegs(m0, nsegs); 2796 set_mbuf_cflags(m0, cflags); 2797 calculate_mbuf_len16(m0, vm_wr); 2798 2799 #ifdef RATELIMIT 2800 /* 2801 * Ethofld is limited to TCP and UDP for now, and only when L4 hw 2802 * checksumming is enabled. needs_outer_l4_csum happens to check for 2803 * all the right things. 2804 */ 2805 if (__predict_false(needs_eo(mst) && !needs_outer_l4_csum(m0))) { 2806 m_snd_tag_rele(m0->m_pkthdr.snd_tag); 2807 m0->m_pkthdr.snd_tag = NULL; 2808 m0->m_pkthdr.csum_flags &= ~CSUM_SND_TAG; 2809 mst = NULL; 2810 } 2811 #endif 2812 2813 if (!needs_hwcsum(m0) 2814 #ifdef RATELIMIT 2815 && !needs_eo(mst) 2816 #endif 2817 ) 2818 return (0); 2819 2820 m = m0; 2821 eh = mtod(m, struct ether_header *); 2822 eh_type = ntohs(eh->ether_type); 2823 if (eh_type == ETHERTYPE_VLAN) { 2824 struct ether_vlan_header *evh = (void *)eh; 2825 2826 eh_type = ntohs(evh->evl_proto); 2827 m0->m_pkthdr.l2hlen = sizeof(*evh); 2828 } else 2829 m0->m_pkthdr.l2hlen = sizeof(*eh); 2830 2831 #if defined(INET) || defined(INET6) 2832 offset = 0; 2833 #ifdef INET 2834 l3hdr = m_advance(&m, &offset, m0->m_pkthdr.l2hlen); 2835 #else 2836 m_advance(&m, &offset, m0->m_pkthdr.l2hlen); 2837 #endif 2838 #endif 2839 2840 switch (eh_type) { 2841 #ifdef INET6 2842 case ETHERTYPE_IPV6: 2843 m0->m_pkthdr.l3hlen = sizeof(struct ip6_hdr); 2844 break; 2845 #endif 2846 #ifdef INET 2847 case ETHERTYPE_IP: 2848 { 2849 struct ip *ip = l3hdr; 2850 2851 if (needs_vxlan_csum(m0)) { 2852 /* Driver will do the outer IP hdr checksum. */ 2853 ip->ip_sum = 0; 2854 if (needs_vxlan_tso(m0)) { 2855 const uint16_t ipl = ip->ip_len; 2856 2857 ip->ip_len = 0; 2858 ip->ip_sum = ~in_cksum_hdr(ip); 2859 ip->ip_len = ipl; 2860 } else 2861 ip->ip_sum = in_cksum_hdr(ip); 2862 } 2863 m0->m_pkthdr.l3hlen = ip->ip_hl << 2; 2864 break; 2865 } 2866 #endif 2867 default: 2868 if (ratecheck(&txerr_ratecheck, &txerr_interval)) { 2869 log(LOG_ERR, "%s: ethertype 0x%04x unknown. " 2870 "if_cxgbe must be compiled with the same " 2871 "INET/INET6 options as the kernel.\n", __func__, 2872 eh_type); 2873 } 2874 rc = EINVAL; 2875 goto fail; 2876 } 2877 2878 #if defined(INET) || defined(INET6) 2879 if (needs_vxlan_csum(m0)) { 2880 m0->m_pkthdr.l4hlen = sizeof(struct udphdr); 2881 m0->m_pkthdr.l5hlen = sizeof(struct vxlan_header); 2882 2883 /* Inner headers. */ 2884 eh = m_advance(&m, &offset, m0->m_pkthdr.l3hlen + 2885 sizeof(struct udphdr) + sizeof(struct vxlan_header)); 2886 eh_type = ntohs(eh->ether_type); 2887 if (eh_type == ETHERTYPE_VLAN) { 2888 struct ether_vlan_header *evh = (void *)eh; 2889 2890 eh_type = ntohs(evh->evl_proto); 2891 m0->m_pkthdr.inner_l2hlen = sizeof(*evh); 2892 } else 2893 m0->m_pkthdr.inner_l2hlen = sizeof(*eh); 2894 #ifdef INET 2895 l3hdr = m_advance(&m, &offset, m0->m_pkthdr.inner_l2hlen); 2896 #else 2897 m_advance(&m, &offset, m0->m_pkthdr.inner_l2hlen); 2898 #endif 2899 2900 switch (eh_type) { 2901 #ifdef INET6 2902 case ETHERTYPE_IPV6: 2903 m0->m_pkthdr.inner_l3hlen = sizeof(struct ip6_hdr); 2904 break; 2905 #endif 2906 #ifdef INET 2907 case ETHERTYPE_IP: 2908 { 2909 struct ip *ip = l3hdr; 2910 2911 m0->m_pkthdr.inner_l3hlen = ip->ip_hl << 2; 2912 break; 2913 } 2914 #endif 2915 default: 2916 if (ratecheck(&txerr_ratecheck, &txerr_interval)) { 2917 log(LOG_ERR, "%s: VXLAN hw offload requested" 2918 "with unknown ethertype 0x%04x. if_cxgbe " 2919 "must be compiled with the same INET/INET6 " 2920 "options as the kernel.\n", __func__, 2921 eh_type); 2922 } 2923 rc = EINVAL; 2924 goto fail; 2925 } 2926 if (needs_inner_tcp_csum(m0)) { 2927 tcp = m_advance(&m, &offset, m0->m_pkthdr.inner_l3hlen); 2928 m0->m_pkthdr.inner_l4hlen = tcp->th_off * 4; 2929 } 2930 MPASS((m0->m_pkthdr.csum_flags & CSUM_SND_TAG) == 0); 2931 m0->m_pkthdr.csum_flags &= CSUM_INNER_IP6_UDP | 2932 CSUM_INNER_IP6_TCP | CSUM_INNER_IP6_TSO | CSUM_INNER_IP | 2933 CSUM_INNER_IP_UDP | CSUM_INNER_IP_TCP | CSUM_INNER_IP_TSO | 2934 CSUM_ENCAP_VXLAN; 2935 } 2936 2937 if (needs_outer_tcp_csum(m0)) { 2938 tcp = m_advance(&m, &offset, m0->m_pkthdr.l3hlen); 2939 m0->m_pkthdr.l4hlen = tcp->th_off * 4; 2940 #ifdef RATELIMIT 2941 if (tsclk >= 0 && *(uint32_t *)(tcp + 1) == ntohl(0x0101080a)) { 2942 set_mbuf_eo_tsclk_tsoff(m0, 2943 V_FW_ETH_TX_EO_WR_TSCLK(tsclk) | 2944 V_FW_ETH_TX_EO_WR_TSOFF(sizeof(*tcp) / 2 + 1)); 2945 } else 2946 set_mbuf_eo_tsclk_tsoff(m0, 0); 2947 } else if (needs_outer_udp_csum(m0)) { 2948 m0->m_pkthdr.l4hlen = sizeof(struct udphdr); 2949 #endif 2950 } 2951 #ifdef RATELIMIT 2952 if (needs_eo(mst)) { 2953 u_int immhdrs; 2954 2955 /* EO WRs have the headers in the WR and not the GL. */ 2956 immhdrs = m0->m_pkthdr.l2hlen + m0->m_pkthdr.l3hlen + 2957 m0->m_pkthdr.l4hlen; 2958 cflags = 0; 2959 nsegs = count_mbuf_nsegs(m0, immhdrs, &cflags); 2960 MPASS(cflags == mbuf_cflags(m0)); 2961 set_mbuf_eo_nsegs(m0, nsegs); 2962 set_mbuf_eo_len16(m0, 2963 txpkt_eo_len16(nsegs, immhdrs, needs_tso(m0))); 2964 } 2965 #endif 2966 #endif 2967 MPASS(m0 == *mp); 2968 return (0); 2969 } 2970 2971 void * 2972 start_wrq_wr(struct sge_wrq *wrq, int len16, struct wrq_cookie *cookie) 2973 { 2974 struct sge_eq *eq = &wrq->eq; 2975 struct adapter *sc = wrq->adapter; 2976 int ndesc, available; 2977 struct wrqe *wr; 2978 void *w; 2979 2980 MPASS(len16 > 0); 2981 ndesc = tx_len16_to_desc(len16); 2982 MPASS(ndesc > 0 && ndesc <= SGE_MAX_WR_NDESC); 2983 2984 EQ_LOCK(eq); 2985 2986 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 2987 drain_wrq_wr_list(sc, wrq); 2988 2989 if (!STAILQ_EMPTY(&wrq->wr_list)) { 2990 slowpath: 2991 EQ_UNLOCK(eq); 2992 wr = alloc_wrqe(len16 * 16, wrq); 2993 if (__predict_false(wr == NULL)) 2994 return (NULL); 2995 cookie->pidx = -1; 2996 cookie->ndesc = ndesc; 2997 return (&wr->wr); 2998 } 2999 3000 eq->cidx = read_hw_cidx(eq); 3001 if (eq->pidx == eq->cidx) 3002 available = eq->sidx - 1; 3003 else 3004 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 3005 if (available < ndesc) 3006 goto slowpath; 3007 3008 cookie->pidx = eq->pidx; 3009 cookie->ndesc = ndesc; 3010 TAILQ_INSERT_TAIL(&wrq->incomplete_wrs, cookie, link); 3011 3012 w = &eq->desc[eq->pidx]; 3013 IDXINCR(eq->pidx, ndesc, eq->sidx); 3014 if (__predict_false(cookie->pidx + ndesc > eq->sidx)) { 3015 w = &wrq->ss[0]; 3016 wrq->ss_pidx = cookie->pidx; 3017 wrq->ss_len = len16 * 16; 3018 } 3019 3020 EQ_UNLOCK(eq); 3021 3022 return (w); 3023 } 3024 3025 void 3026 commit_wrq_wr(struct sge_wrq *wrq, void *w, struct wrq_cookie *cookie) 3027 { 3028 struct sge_eq *eq = &wrq->eq; 3029 struct adapter *sc = wrq->adapter; 3030 int ndesc, pidx; 3031 struct wrq_cookie *prev, *next; 3032 3033 if (cookie->pidx == -1) { 3034 struct wrqe *wr = __containerof(w, struct wrqe, wr); 3035 3036 t4_wrq_tx(sc, wr); 3037 return; 3038 } 3039 3040 if (__predict_false(w == &wrq->ss[0])) { 3041 int n = (eq->sidx - wrq->ss_pidx) * EQ_ESIZE; 3042 3043 MPASS(wrq->ss_len > n); /* WR had better wrap around. */ 3044 bcopy(&wrq->ss[0], &eq->desc[wrq->ss_pidx], n); 3045 bcopy(&wrq->ss[n], &eq->desc[0], wrq->ss_len - n); 3046 wrq->tx_wrs_ss++; 3047 } else 3048 wrq->tx_wrs_direct++; 3049 3050 EQ_LOCK(eq); 3051 ndesc = cookie->ndesc; /* Can be more than SGE_MAX_WR_NDESC here. */ 3052 pidx = cookie->pidx; 3053 MPASS(pidx >= 0 && pidx < eq->sidx); 3054 prev = TAILQ_PREV(cookie, wrq_incomplete_wrs, link); 3055 next = TAILQ_NEXT(cookie, link); 3056 if (prev == NULL) { 3057 MPASS(pidx == eq->dbidx); 3058 if (next == NULL || ndesc >= 16) { 3059 int available; 3060 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */ 3061 3062 /* 3063 * Note that the WR via which we'll request tx updates 3064 * is at pidx and not eq->pidx, which has moved on 3065 * already. 3066 */ 3067 dst = (void *)&eq->desc[pidx]; 3068 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 3069 if (available < eq->sidx / 4 && 3070 atomic_cmpset_int(&eq->equiq, 0, 1)) { 3071 /* 3072 * XXX: This is not 100% reliable with some 3073 * types of WRs. But this is a very unusual 3074 * situation for an ofld/ctrl queue anyway. 3075 */ 3076 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ | 3077 F_FW_WR_EQUEQ); 3078 } 3079 3080 ring_eq_db(wrq->adapter, eq, ndesc); 3081 } else { 3082 MPASS(IDXDIFF(next->pidx, pidx, eq->sidx) == ndesc); 3083 next->pidx = pidx; 3084 next->ndesc += ndesc; 3085 } 3086 } else { 3087 MPASS(IDXDIFF(pidx, prev->pidx, eq->sidx) == prev->ndesc); 3088 prev->ndesc += ndesc; 3089 } 3090 TAILQ_REMOVE(&wrq->incomplete_wrs, cookie, link); 3091 3092 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 3093 drain_wrq_wr_list(sc, wrq); 3094 3095 #ifdef INVARIANTS 3096 if (TAILQ_EMPTY(&wrq->incomplete_wrs)) { 3097 /* Doorbell must have caught up to the pidx. */ 3098 MPASS(wrq->eq.pidx == wrq->eq.dbidx); 3099 } 3100 #endif 3101 EQ_UNLOCK(eq); 3102 } 3103 3104 static u_int 3105 can_resume_eth_tx(struct mp_ring *r) 3106 { 3107 struct sge_eq *eq = r->cookie; 3108 3109 return (total_available_tx_desc(eq) > eq->sidx / 8); 3110 } 3111 3112 static inline bool 3113 cannot_use_txpkts(struct mbuf *m) 3114 { 3115 /* maybe put a GL limit too, to avoid silliness? */ 3116 3117 return (needs_tso(m) || (mbuf_cflags(m) & (MC_RAW_WR | MC_TLS)) != 0); 3118 } 3119 3120 static inline int 3121 discard_tx(struct sge_eq *eq) 3122 { 3123 3124 return ((eq->flags & (EQ_ENABLED | EQ_QFLUSH)) != EQ_ENABLED); 3125 } 3126 3127 static inline int 3128 wr_can_update_eq(void *p) 3129 { 3130 struct fw_eth_tx_pkts_wr *wr = p; 3131 3132 switch (G_FW_WR_OP(be32toh(wr->op_pkd))) { 3133 case FW_ULPTX_WR: 3134 case FW_ETH_TX_PKT_WR: 3135 case FW_ETH_TX_PKTS_WR: 3136 case FW_ETH_TX_PKTS2_WR: 3137 case FW_ETH_TX_PKT_VM_WR: 3138 case FW_ETH_TX_PKTS_VM_WR: 3139 return (1); 3140 default: 3141 return (0); 3142 } 3143 } 3144 3145 static inline void 3146 set_txupdate_flags(struct sge_txq *txq, u_int avail, 3147 struct fw_eth_tx_pkt_wr *wr) 3148 { 3149 struct sge_eq *eq = &txq->eq; 3150 struct txpkts *txp = &txq->txp; 3151 3152 if ((txp->npkt > 0 || avail < eq->sidx / 2) && 3153 atomic_cmpset_int(&eq->equiq, 0, 1)) { 3154 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ | F_FW_WR_EQUIQ); 3155 eq->equeqidx = eq->pidx; 3156 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 32) { 3157 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ); 3158 eq->equeqidx = eq->pidx; 3159 } 3160 } 3161 3162 #if defined(__i386__) || defined(__amd64__) 3163 extern uint64_t tsc_freq; 3164 #endif 3165 3166 static inline bool 3167 record_eth_tx_time(struct sge_txq *txq) 3168 { 3169 const uint64_t cycles = get_cyclecount(); 3170 const uint64_t last_tx = txq->last_tx; 3171 #if defined(__i386__) || defined(__amd64__) 3172 const uint64_t itg = tsc_freq * t4_tx_coalesce_gap / 1000000; 3173 #else 3174 const uint64_t itg = 0; 3175 #endif 3176 3177 MPASS(cycles >= last_tx); 3178 txq->last_tx = cycles; 3179 return (cycles - last_tx < itg); 3180 } 3181 3182 /* 3183 * r->items[cidx] to r->items[pidx], with a wraparound at r->size, are ready to 3184 * be consumed. Return the actual number consumed. 0 indicates a stall. 3185 */ 3186 static u_int 3187 eth_tx(struct mp_ring *r, u_int cidx, u_int pidx, bool *coalescing) 3188 { 3189 struct sge_txq *txq = r->cookie; 3190 struct ifnet *ifp = txq->ifp; 3191 struct sge_eq *eq = &txq->eq; 3192 struct txpkts *txp = &txq->txp; 3193 struct vi_info *vi = ifp->if_softc; 3194 struct adapter *sc = vi->adapter; 3195 u_int total, remaining; /* # of packets */ 3196 u_int n, avail, dbdiff; /* # of hardware descriptors */ 3197 int i, rc; 3198 struct mbuf *m0; 3199 bool snd, recent_tx; 3200 void *wr; /* start of the last WR written to the ring */ 3201 3202 TXQ_LOCK_ASSERT_OWNED(txq); 3203 recent_tx = record_eth_tx_time(txq); 3204 3205 remaining = IDXDIFF(pidx, cidx, r->size); 3206 if (__predict_false(discard_tx(eq))) { 3207 for (i = 0; i < txp->npkt; i++) 3208 m_freem(txp->mb[i]); 3209 txp->npkt = 0; 3210 while (cidx != pidx) { 3211 m0 = r->items[cidx]; 3212 m_freem(m0); 3213 if (++cidx == r->size) 3214 cidx = 0; 3215 } 3216 reclaim_tx_descs(txq, eq->sidx); 3217 *coalescing = false; 3218 return (remaining); /* emptied */ 3219 } 3220 3221 /* How many hardware descriptors do we have readily available. */ 3222 if (eq->pidx == eq->cidx) 3223 avail = eq->sidx - 1; 3224 else 3225 avail = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 3226 3227 total = 0; 3228 if (remaining == 0) { 3229 txp->score = 0; 3230 txq->txpkts_flush++; 3231 goto send_txpkts; 3232 } 3233 3234 dbdiff = 0; 3235 MPASS(remaining > 0); 3236 while (remaining > 0) { 3237 m0 = r->items[cidx]; 3238 M_ASSERTPKTHDR(m0); 3239 MPASS(m0->m_nextpkt == NULL); 3240 3241 if (avail < 2 * SGE_MAX_WR_NDESC) 3242 avail += reclaim_tx_descs(txq, 64); 3243 3244 if (t4_tx_coalesce == 0 && txp->npkt == 0) 3245 goto skip_coalescing; 3246 if (cannot_use_txpkts(m0)) 3247 txp->score = 0; 3248 else if (recent_tx) { 3249 if (++txp->score == 0) 3250 txp->score = UINT8_MAX; 3251 } else 3252 txp->score = 1; 3253 if (txp->npkt > 0 || remaining > 1 || 3254 txp->score >= t4_tx_coalesce_pkts || 3255 atomic_load_int(&txq->eq.equiq) != 0) { 3256 if (vi->flags & TX_USES_VM_WR) 3257 rc = add_to_txpkts_vf(sc, txq, m0, avail, &snd); 3258 else 3259 rc = add_to_txpkts_pf(sc, txq, m0, avail, &snd); 3260 } else { 3261 snd = false; 3262 rc = EINVAL; 3263 } 3264 if (snd) { 3265 MPASS(txp->npkt > 0); 3266 for (i = 0; i < txp->npkt; i++) 3267 ETHER_BPF_MTAP(ifp, txp->mb[i]); 3268 if (txp->npkt > 1) { 3269 MPASS(avail >= tx_len16_to_desc(txp->len16)); 3270 if (vi->flags & TX_USES_VM_WR) 3271 n = write_txpkts_vm_wr(sc, txq); 3272 else 3273 n = write_txpkts_wr(sc, txq); 3274 } else { 3275 MPASS(avail >= 3276 tx_len16_to_desc(mbuf_len16(txp->mb[0]))); 3277 if (vi->flags & TX_USES_VM_WR) 3278 n = write_txpkt_vm_wr(sc, txq, 3279 txp->mb[0]); 3280 else 3281 n = write_txpkt_wr(sc, txq, txp->mb[0], 3282 avail); 3283 } 3284 MPASS(n <= SGE_MAX_WR_NDESC); 3285 avail -= n; 3286 dbdiff += n; 3287 wr = &eq->desc[eq->pidx]; 3288 IDXINCR(eq->pidx, n, eq->sidx); 3289 txp->npkt = 0; /* emptied */ 3290 } 3291 if (rc == 0) { 3292 /* m0 was coalesced into txq->txpkts. */ 3293 goto next_mbuf; 3294 } 3295 if (rc == EAGAIN) { 3296 /* 3297 * m0 is suitable for tx coalescing but could not be 3298 * combined with the existing txq->txpkts, which has now 3299 * been transmitted. Start a new txpkts with m0. 3300 */ 3301 MPASS(snd); 3302 MPASS(txp->npkt == 0); 3303 continue; 3304 } 3305 3306 MPASS(rc != 0 && rc != EAGAIN); 3307 MPASS(txp->npkt == 0); 3308 skip_coalescing: 3309 n = tx_len16_to_desc(mbuf_len16(m0)); 3310 if (__predict_false(avail < n)) { 3311 avail += reclaim_tx_descs(txq, min(n, 32)); 3312 if (avail < n) 3313 break; /* out of descriptors */ 3314 } 3315 3316 wr = &eq->desc[eq->pidx]; 3317 if (mbuf_cflags(m0) & MC_RAW_WR) { 3318 n = write_raw_wr(txq, wr, m0, avail); 3319 #ifdef KERN_TLS 3320 } else if (mbuf_cflags(m0) & MC_TLS) { 3321 ETHER_BPF_MTAP(ifp, m0); 3322 n = t6_ktls_write_wr(txq, wr, m0, mbuf_nsegs(m0), 3323 avail); 3324 #endif 3325 } else { 3326 ETHER_BPF_MTAP(ifp, m0); 3327 if (vi->flags & TX_USES_VM_WR) 3328 n = write_txpkt_vm_wr(sc, txq, m0); 3329 else 3330 n = write_txpkt_wr(sc, txq, m0, avail); 3331 } 3332 MPASS(n >= 1 && n <= avail); 3333 if (!(mbuf_cflags(m0) & MC_TLS)) 3334 MPASS(n <= SGE_MAX_WR_NDESC); 3335 3336 avail -= n; 3337 dbdiff += n; 3338 IDXINCR(eq->pidx, n, eq->sidx); 3339 3340 if (dbdiff >= 512 / EQ_ESIZE) { /* X_FETCHBURSTMAX_512B */ 3341 if (wr_can_update_eq(wr)) 3342 set_txupdate_flags(txq, avail, wr); 3343 ring_eq_db(sc, eq, dbdiff); 3344 avail += reclaim_tx_descs(txq, 32); 3345 dbdiff = 0; 3346 } 3347 next_mbuf: 3348 total++; 3349 remaining--; 3350 if (__predict_false(++cidx == r->size)) 3351 cidx = 0; 3352 } 3353 if (dbdiff != 0) { 3354 if (wr_can_update_eq(wr)) 3355 set_txupdate_flags(txq, avail, wr); 3356 ring_eq_db(sc, eq, dbdiff); 3357 reclaim_tx_descs(txq, 32); 3358 } else if (eq->pidx == eq->cidx && txp->npkt > 0 && 3359 atomic_load_int(&txq->eq.equiq) == 0) { 3360 /* 3361 * If nothing was submitted to the chip for tx (it was coalesced 3362 * into txpkts instead) and there is no tx update outstanding 3363 * then we need to send txpkts now. 3364 */ 3365 send_txpkts: 3366 MPASS(txp->npkt > 0); 3367 for (i = 0; i < txp->npkt; i++) 3368 ETHER_BPF_MTAP(ifp, txp->mb[i]); 3369 if (txp->npkt > 1) { 3370 MPASS(avail >= tx_len16_to_desc(txp->len16)); 3371 if (vi->flags & TX_USES_VM_WR) 3372 n = write_txpkts_vm_wr(sc, txq); 3373 else 3374 n = write_txpkts_wr(sc, txq); 3375 } else { 3376 MPASS(avail >= 3377 tx_len16_to_desc(mbuf_len16(txp->mb[0]))); 3378 if (vi->flags & TX_USES_VM_WR) 3379 n = write_txpkt_vm_wr(sc, txq, txp->mb[0]); 3380 else 3381 n = write_txpkt_wr(sc, txq, txp->mb[0], avail); 3382 } 3383 MPASS(n <= SGE_MAX_WR_NDESC); 3384 wr = &eq->desc[eq->pidx]; 3385 IDXINCR(eq->pidx, n, eq->sidx); 3386 txp->npkt = 0; /* emptied */ 3387 3388 MPASS(wr_can_update_eq(wr)); 3389 set_txupdate_flags(txq, avail - n, wr); 3390 ring_eq_db(sc, eq, n); 3391 reclaim_tx_descs(txq, 32); 3392 } 3393 *coalescing = txp->npkt > 0; 3394 3395 return (total); 3396 } 3397 3398 static inline void 3399 init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int pktc_idx, 3400 int qsize, int intr_idx, int cong, int qtype) 3401 { 3402 3403 KASSERT(tmr_idx >= 0 && tmr_idx < SGE_NTIMERS, 3404 ("%s: bad tmr_idx %d", __func__, tmr_idx)); 3405 KASSERT(pktc_idx < SGE_NCOUNTERS, /* -ve is ok, means don't use */ 3406 ("%s: bad pktc_idx %d", __func__, pktc_idx)); 3407 KASSERT(intr_idx >= -1 && intr_idx < sc->intr_count, 3408 ("%s: bad intr_idx %d", __func__, intr_idx)); 3409 KASSERT(qtype == FW_IQ_IQTYPE_OTHER || qtype == FW_IQ_IQTYPE_NIC || 3410 qtype == FW_IQ_IQTYPE_OFLD, ("%s: bad qtype %d", __func__, qtype)); 3411 3412 iq->flags = 0; 3413 iq->state = IQS_DISABLED; 3414 iq->adapter = sc; 3415 iq->qtype = qtype; 3416 iq->intr_params = V_QINTR_TIMER_IDX(tmr_idx); 3417 iq->intr_pktc_idx = SGE_NCOUNTERS - 1; 3418 if (pktc_idx >= 0) { 3419 iq->intr_params |= F_QINTR_CNT_EN; 3420 iq->intr_pktc_idx = pktc_idx; 3421 } 3422 iq->qsize = roundup2(qsize, 16); /* See FW_IQ_CMD/iqsize */ 3423 iq->sidx = iq->qsize - sc->params.sge.spg_len / IQ_ESIZE; 3424 iq->intr_idx = intr_idx; 3425 iq->cong_drop = cong; 3426 } 3427 3428 static inline void 3429 init_fl(struct adapter *sc, struct sge_fl *fl, int qsize, int maxp, char *name) 3430 { 3431 struct sge_params *sp = &sc->params.sge; 3432 3433 fl->qsize = qsize; 3434 fl->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE; 3435 strlcpy(fl->lockname, name, sizeof(fl->lockname)); 3436 mtx_init(&fl->fl_lock, fl->lockname, NULL, MTX_DEF); 3437 if (sc->flags & BUF_PACKING_OK && 3438 ((!is_t4(sc) && buffer_packing) || /* T5+: enabled unless 0 */ 3439 (is_t4(sc) && buffer_packing == 1)))/* T4: disabled unless 1 */ 3440 fl->flags |= FL_BUF_PACKING; 3441 fl->zidx = find_refill_source(sc, maxp, fl->flags & FL_BUF_PACKING); 3442 fl->safe_zidx = sc->sge.safe_zidx; 3443 if (fl->flags & FL_BUF_PACKING) { 3444 fl->lowat = roundup2(sp->fl_starve_threshold2, 8); 3445 fl->buf_boundary = sp->pack_boundary; 3446 } else { 3447 fl->lowat = roundup2(sp->fl_starve_threshold, 8); 3448 fl->buf_boundary = 16; 3449 } 3450 if (fl_pad && fl->buf_boundary < sp->pad_boundary) 3451 fl->buf_boundary = sp->pad_boundary; 3452 } 3453 3454 static inline void 3455 init_eq(struct adapter *sc, struct sge_eq *eq, int eqtype, int qsize, 3456 uint8_t tx_chan, struct sge_iq *iq, char *name) 3457 { 3458 KASSERT(eqtype >= EQ_CTRL && eqtype <= EQ_OFLD, 3459 ("%s: bad qtype %d", __func__, eqtype)); 3460 3461 eq->type = eqtype; 3462 eq->tx_chan = tx_chan; 3463 eq->iq = iq; 3464 eq->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE; 3465 strlcpy(eq->lockname, name, sizeof(eq->lockname)); 3466 mtx_init(&eq->eq_lock, eq->lockname, NULL, MTX_DEF); 3467 } 3468 3469 int 3470 alloc_ring(struct adapter *sc, size_t len, bus_dma_tag_t *tag, 3471 bus_dmamap_t *map, bus_addr_t *pa, void **va) 3472 { 3473 int rc; 3474 3475 rc = bus_dma_tag_create(sc->dmat, 512, 0, BUS_SPACE_MAXADDR, 3476 BUS_SPACE_MAXADDR, NULL, NULL, len, 1, len, 0, NULL, NULL, tag); 3477 if (rc != 0) { 3478 CH_ERR(sc, "cannot allocate DMA tag: %d\n", rc); 3479 goto done; 3480 } 3481 3482 rc = bus_dmamem_alloc(*tag, va, 3483 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, map); 3484 if (rc != 0) { 3485 CH_ERR(sc, "cannot allocate DMA memory: %d\n", rc); 3486 goto done; 3487 } 3488 3489 rc = bus_dmamap_load(*tag, *map, *va, len, oneseg_dma_callback, pa, 0); 3490 if (rc != 0) { 3491 CH_ERR(sc, "cannot load DMA map: %d\n", rc); 3492 goto done; 3493 } 3494 done: 3495 if (rc) 3496 free_ring(sc, *tag, *map, *pa, *va); 3497 3498 return (rc); 3499 } 3500 3501 int 3502 free_ring(struct adapter *sc, bus_dma_tag_t tag, bus_dmamap_t map, 3503 bus_addr_t pa, void *va) 3504 { 3505 if (pa) 3506 bus_dmamap_unload(tag, map); 3507 if (va) 3508 bus_dmamem_free(tag, va, map); 3509 if (tag) 3510 bus_dma_tag_destroy(tag); 3511 3512 return (0); 3513 } 3514 3515 /* 3516 * Allocates the software resources (mainly memory and sysctl nodes) for an 3517 * ingress queue and an optional freelist. 3518 * 3519 * Sets IQ_SW_ALLOCATED and returns 0 on success. 3520 */ 3521 static int 3522 alloc_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl, 3523 struct sysctl_ctx_list *ctx, struct sysctl_oid *oid) 3524 { 3525 int rc; 3526 size_t len; 3527 struct adapter *sc = vi->adapter; 3528 3529 MPASS(!(iq->flags & IQ_SW_ALLOCATED)); 3530 3531 len = iq->qsize * IQ_ESIZE; 3532 rc = alloc_ring(sc, len, &iq->desc_tag, &iq->desc_map, &iq->ba, 3533 (void **)&iq->desc); 3534 if (rc != 0) 3535 return (rc); 3536 3537 if (fl) { 3538 len = fl->qsize * EQ_ESIZE; 3539 rc = alloc_ring(sc, len, &fl->desc_tag, &fl->desc_map, 3540 &fl->ba, (void **)&fl->desc); 3541 if (rc) { 3542 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, 3543 iq->desc); 3544 return (rc); 3545 } 3546 3547 /* Allocate space for one software descriptor per buffer. */ 3548 fl->sdesc = malloc(fl->sidx * 8 * sizeof(struct fl_sdesc), 3549 M_CXGBE, M_ZERO | M_WAITOK); 3550 3551 add_fl_sysctls(sc, ctx, oid, fl); 3552 iq->flags |= IQ_HAS_FL; 3553 } 3554 add_iq_sysctls(ctx, oid, iq); 3555 iq->flags |= IQ_SW_ALLOCATED; 3556 3557 return (0); 3558 } 3559 3560 /* 3561 * Frees all software resources (memory and locks) associated with an ingress 3562 * queue and an optional freelist. 3563 */ 3564 static void 3565 free_iq_fl(struct adapter *sc, struct sge_iq *iq, struct sge_fl *fl) 3566 { 3567 MPASS(iq->flags & IQ_SW_ALLOCATED); 3568 3569 if (fl) { 3570 MPASS(iq->flags & IQ_HAS_FL); 3571 free_ring(sc, fl->desc_tag, fl->desc_map, fl->ba, fl->desc); 3572 free_fl_buffers(sc, fl); 3573 free(fl->sdesc, M_CXGBE); 3574 mtx_destroy(&fl->fl_lock); 3575 bzero(fl, sizeof(*fl)); 3576 } 3577 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, iq->desc); 3578 bzero(iq, sizeof(*iq)); 3579 } 3580 3581 /* 3582 * Allocates a hardware ingress queue and an optional freelist that will be 3583 * associated with it. 3584 * 3585 * Returns errno on failure. Resources allocated up to that point may still be 3586 * allocated. Caller is responsible for cleanup in case this function fails. 3587 */ 3588 static int 3589 alloc_iq_fl_hwq(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl) 3590 { 3591 int rc, cntxt_id, cong_map; 3592 struct fw_iq_cmd c; 3593 struct adapter *sc = vi->adapter; 3594 struct port_info *pi = vi->pi; 3595 __be32 v = 0; 3596 3597 MPASS (!(iq->flags & IQ_HW_ALLOCATED)); 3598 3599 bzero(&c, sizeof(c)); 3600 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 3601 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) | 3602 V_FW_IQ_CMD_VFN(0)); 3603 3604 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART | 3605 FW_LEN16(c)); 3606 3607 /* Special handling for firmware event queue */ 3608 if (iq == &sc->sge.fwq) 3609 v |= F_FW_IQ_CMD_IQASYNCH; 3610 3611 if (iq->intr_idx < 0) { 3612 /* Forwarded interrupts, all headed to fwq */ 3613 v |= F_FW_IQ_CMD_IQANDST; 3614 v |= V_FW_IQ_CMD_IQANDSTINDEX(sc->sge.fwq.cntxt_id); 3615 } else { 3616 KASSERT(iq->intr_idx < sc->intr_count, 3617 ("%s: invalid direct intr_idx %d", __func__, iq->intr_idx)); 3618 v |= V_FW_IQ_CMD_IQANDSTINDEX(iq->intr_idx); 3619 } 3620 3621 bzero(iq->desc, iq->qsize * IQ_ESIZE); 3622 c.type_to_iqandstindex = htobe32(v | 3623 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) | 3624 V_FW_IQ_CMD_VIID(vi->viid) | 3625 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT)); 3626 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->tx_chan) | 3627 F_FW_IQ_CMD_IQGTSMODE | 3628 V_FW_IQ_CMD_IQINTCNTTHRESH(iq->intr_pktc_idx) | 3629 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4)); 3630 c.iqsize = htobe16(iq->qsize); 3631 c.iqaddr = htobe64(iq->ba); 3632 c.iqns_to_fl0congen = htobe32(V_FW_IQ_CMD_IQTYPE(iq->qtype)); 3633 if (iq->cong_drop != -1) { 3634 cong_map = iq->qtype == IQ_ETH ? pi->rx_e_chan_map : 0; 3635 c.iqns_to_fl0congen |= htobe32(F_FW_IQ_CMD_IQFLINTCONGEN); 3636 } 3637 3638 if (fl) { 3639 bzero(fl->desc, fl->sidx * EQ_ESIZE + sc->params.sge.spg_len); 3640 c.iqns_to_fl0congen |= 3641 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) | 3642 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO | 3643 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) | 3644 (fl->flags & FL_BUF_PACKING ? F_FW_IQ_CMD_FL0PACKEN : 3645 0)); 3646 if (iq->cong_drop != -1) { 3647 c.iqns_to_fl0congen |= 3648 htobe32(V_FW_IQ_CMD_FL0CNGCHMAP(cong_map) | 3649 F_FW_IQ_CMD_FL0CONGCIF | 3650 F_FW_IQ_CMD_FL0CONGEN); 3651 } 3652 c.fl0dcaen_to_fl0cidxfthresh = 3653 htobe16(V_FW_IQ_CMD_FL0FBMIN(chip_id(sc) <= CHELSIO_T5 ? 3654 X_FETCHBURSTMIN_128B : X_FETCHBURSTMIN_64B_T6) | 3655 V_FW_IQ_CMD_FL0FBMAX(chip_id(sc) <= CHELSIO_T5 ? 3656 X_FETCHBURSTMAX_512B : X_FETCHBURSTMAX_256B)); 3657 c.fl0size = htobe16(fl->qsize); 3658 c.fl0addr = htobe64(fl->ba); 3659 } 3660 3661 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3662 if (rc != 0) { 3663 CH_ERR(sc, "failed to create hw ingress queue: %d\n", rc); 3664 return (rc); 3665 } 3666 3667 iq->cidx = 0; 3668 iq->gen = F_RSPD_GEN; 3669 iq->cntxt_id = be16toh(c.iqid); 3670 iq->abs_id = be16toh(c.physiqid); 3671 3672 cntxt_id = iq->cntxt_id - sc->sge.iq_start; 3673 if (cntxt_id >= sc->sge.iqmap_sz) { 3674 panic ("%s: iq->cntxt_id (%d) more than the max (%d)", __func__, 3675 cntxt_id, sc->sge.iqmap_sz - 1); 3676 } 3677 sc->sge.iqmap[cntxt_id] = iq; 3678 3679 if (fl) { 3680 u_int qid; 3681 #ifdef INVARIANTS 3682 int i; 3683 3684 MPASS(!(fl->flags & FL_BUF_RESUME)); 3685 for (i = 0; i < fl->sidx * 8; i++) 3686 MPASS(fl->sdesc[i].cl == NULL); 3687 #endif 3688 fl->cntxt_id = be16toh(c.fl0id); 3689 fl->pidx = fl->cidx = fl->hw_cidx = fl->dbidx = 0; 3690 fl->rx_offset = 0; 3691 fl->flags &= ~(FL_STARVING | FL_DOOMED); 3692 3693 cntxt_id = fl->cntxt_id - sc->sge.eq_start; 3694 if (cntxt_id >= sc->sge.eqmap_sz) { 3695 panic("%s: fl->cntxt_id (%d) more than the max (%d)", 3696 __func__, cntxt_id, sc->sge.eqmap_sz - 1); 3697 } 3698 sc->sge.eqmap[cntxt_id] = (void *)fl; 3699 3700 qid = fl->cntxt_id; 3701 if (isset(&sc->doorbells, DOORBELL_UDB)) { 3702 uint32_t s_qpp = sc->params.sge.eq_s_qpp; 3703 uint32_t mask = (1 << s_qpp) - 1; 3704 volatile uint8_t *udb; 3705 3706 udb = sc->udbs_base + UDBS_DB_OFFSET; 3707 udb += (qid >> s_qpp) << PAGE_SHIFT; 3708 qid &= mask; 3709 if (qid < PAGE_SIZE / UDBS_SEG_SIZE) { 3710 udb += qid << UDBS_SEG_SHIFT; 3711 qid = 0; 3712 } 3713 fl->udb = (volatile void *)udb; 3714 } 3715 fl->dbval = V_QID(qid) | sc->chip_params->sge_fl_db; 3716 3717 FL_LOCK(fl); 3718 /* Enough to make sure the SGE doesn't think it's starved */ 3719 refill_fl(sc, fl, fl->lowat); 3720 FL_UNLOCK(fl); 3721 } 3722 3723 if (chip_id(sc) >= CHELSIO_T5 && !(sc->flags & IS_VF) && 3724 iq->cong_drop != -1) { 3725 t4_sge_set_conm_context(sc, iq->cntxt_id, iq->cong_drop, 3726 cong_map); 3727 } 3728 3729 /* Enable IQ interrupts */ 3730 atomic_store_rel_int(&iq->state, IQS_IDLE); 3731 t4_write_reg(sc, sc->sge_gts_reg, V_SEINTARM(iq->intr_params) | 3732 V_INGRESSQID(iq->cntxt_id)); 3733 3734 iq->flags |= IQ_HW_ALLOCATED; 3735 3736 return (0); 3737 } 3738 3739 static int 3740 free_iq_fl_hwq(struct adapter *sc, struct sge_iq *iq, struct sge_fl *fl) 3741 { 3742 int rc; 3743 3744 MPASS(iq->flags & IQ_HW_ALLOCATED); 3745 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0, FW_IQ_TYPE_FL_INT_CAP, 3746 iq->cntxt_id, fl ? fl->cntxt_id : 0xffff, 0xffff); 3747 if (rc != 0) { 3748 CH_ERR(sc, "failed to free iq %p: %d\n", iq, rc); 3749 return (rc); 3750 } 3751 iq->flags &= ~IQ_HW_ALLOCATED; 3752 3753 return (0); 3754 } 3755 3756 static void 3757 add_iq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid, 3758 struct sge_iq *iq) 3759 { 3760 struct sysctl_oid_list *children; 3761 3762 if (ctx == NULL || oid == NULL) 3763 return; 3764 3765 children = SYSCTL_CHILDREN(oid); 3766 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, &iq->ba, 3767 "bus address of descriptor ring"); 3768 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3769 iq->qsize * IQ_ESIZE, "descriptor ring size in bytes"); 3770 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "abs_id", CTLFLAG_RD, 3771 &iq->abs_id, 0, "absolute id of the queue"); 3772 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 3773 &iq->cntxt_id, 0, "SGE context id of the queue"); 3774 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &iq->cidx, 3775 0, "consumer index"); 3776 } 3777 3778 static void 3779 add_fl_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx, 3780 struct sysctl_oid *oid, struct sge_fl *fl) 3781 { 3782 struct sysctl_oid_list *children; 3783 3784 if (ctx == NULL || oid == NULL) 3785 return; 3786 3787 children = SYSCTL_CHILDREN(oid); 3788 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", 3789 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "freelist"); 3790 children = SYSCTL_CHILDREN(oid); 3791 3792 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, 3793 &fl->ba, "bus address of descriptor ring"); 3794 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3795 fl->sidx * EQ_ESIZE + sc->params.sge.spg_len, 3796 "desc ring size in bytes"); 3797 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 3798 &fl->cntxt_id, 0, "SGE context id of the freelist"); 3799 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "padding", CTLFLAG_RD, NULL, 3800 fl_pad ? 1 : 0, "padding enabled"); 3801 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "packing", CTLFLAG_RD, NULL, 3802 fl->flags & FL_BUF_PACKING ? 1 : 0, "packing enabled"); 3803 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &fl->cidx, 3804 0, "consumer index"); 3805 if (fl->flags & FL_BUF_PACKING) { 3806 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rx_offset", 3807 CTLFLAG_RD, &fl->rx_offset, 0, "packing rx offset"); 3808 } 3809 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &fl->pidx, 3810 0, "producer index"); 3811 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_allocated", 3812 CTLFLAG_RD, &fl->cl_allocated, "# of clusters allocated"); 3813 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_recycled", 3814 CTLFLAG_RD, &fl->cl_recycled, "# of clusters recycled"); 3815 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_fast_recycled", 3816 CTLFLAG_RD, &fl->cl_fast_recycled, "# of clusters recycled (fast)"); 3817 } 3818 3819 /* 3820 * Idempotent. 3821 */ 3822 static int 3823 alloc_fwq(struct adapter *sc) 3824 { 3825 int rc, intr_idx; 3826 struct sge_iq *fwq = &sc->sge.fwq; 3827 struct vi_info *vi = &sc->port[0]->vi[0]; 3828 3829 if (!(fwq->flags & IQ_SW_ALLOCATED)) { 3830 MPASS(!(fwq->flags & IQ_HW_ALLOCATED)); 3831 3832 if (sc->flags & IS_VF) 3833 intr_idx = 0; 3834 else 3835 intr_idx = sc->intr_count > 1 ? 1 : 0; 3836 init_iq(fwq, sc, 0, 0, FW_IQ_QSIZE, intr_idx, -1, IQ_OTHER); 3837 rc = alloc_iq_fl(vi, fwq, NULL, &sc->ctx, sc->fwq_oid); 3838 if (rc != 0) { 3839 CH_ERR(sc, "failed to allocate fwq: %d\n", rc); 3840 return (rc); 3841 } 3842 MPASS(fwq->flags & IQ_SW_ALLOCATED); 3843 } 3844 3845 if (!(fwq->flags & IQ_HW_ALLOCATED)) { 3846 MPASS(fwq->flags & IQ_SW_ALLOCATED); 3847 3848 rc = alloc_iq_fl_hwq(vi, fwq, NULL); 3849 if (rc != 0) { 3850 CH_ERR(sc, "failed to create hw fwq: %d\n", rc); 3851 return (rc); 3852 } 3853 MPASS(fwq->flags & IQ_HW_ALLOCATED); 3854 } 3855 3856 return (0); 3857 } 3858 3859 /* 3860 * Idempotent. 3861 */ 3862 static void 3863 free_fwq(struct adapter *sc) 3864 { 3865 struct sge_iq *fwq = &sc->sge.fwq; 3866 3867 if (fwq->flags & IQ_HW_ALLOCATED) { 3868 MPASS(fwq->flags & IQ_SW_ALLOCATED); 3869 free_iq_fl_hwq(sc, fwq, NULL); 3870 MPASS(!(fwq->flags & IQ_HW_ALLOCATED)); 3871 } 3872 3873 if (fwq->flags & IQ_SW_ALLOCATED) { 3874 MPASS(!(fwq->flags & IQ_HW_ALLOCATED)); 3875 free_iq_fl(sc, fwq, NULL); 3876 MPASS(!(fwq->flags & IQ_SW_ALLOCATED)); 3877 } 3878 } 3879 3880 /* 3881 * Idempotent. 3882 */ 3883 static int 3884 alloc_ctrlq(struct adapter *sc, int idx) 3885 { 3886 int rc; 3887 char name[16]; 3888 struct sysctl_oid *oid; 3889 struct sge_wrq *ctrlq = &sc->sge.ctrlq[idx]; 3890 3891 MPASS(idx < sc->params.nports); 3892 3893 if (!(ctrlq->eq.flags & EQ_SW_ALLOCATED)) { 3894 MPASS(!(ctrlq->eq.flags & EQ_HW_ALLOCATED)); 3895 3896 snprintf(name, sizeof(name), "%d", idx); 3897 oid = SYSCTL_ADD_NODE(&sc->ctx, SYSCTL_CHILDREN(sc->ctrlq_oid), 3898 OID_AUTO, name, CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 3899 "ctrl queue"); 3900 3901 snprintf(name, sizeof(name), "%s ctrlq%d", 3902 device_get_nameunit(sc->dev), idx); 3903 init_eq(sc, &ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE, 3904 sc->port[idx]->tx_chan, &sc->sge.fwq, name); 3905 rc = alloc_wrq(sc, NULL, ctrlq, &sc->ctx, oid); 3906 if (rc != 0) { 3907 CH_ERR(sc, "failed to allocate ctrlq%d: %d\n", idx, rc); 3908 sysctl_remove_oid(oid, 1, 1); 3909 return (rc); 3910 } 3911 MPASS(ctrlq->eq.flags & EQ_SW_ALLOCATED); 3912 } 3913 3914 if (!(ctrlq->eq.flags & EQ_HW_ALLOCATED)) { 3915 MPASS(ctrlq->eq.flags & EQ_SW_ALLOCATED); 3916 3917 rc = alloc_eq_hwq(sc, NULL, &ctrlq->eq); 3918 if (rc != 0) { 3919 CH_ERR(sc, "failed to create hw ctrlq%d: %d\n", idx, rc); 3920 return (rc); 3921 } 3922 MPASS(ctrlq->eq.flags & EQ_HW_ALLOCATED); 3923 } 3924 3925 return (0); 3926 } 3927 3928 /* 3929 * Idempotent. 3930 */ 3931 static void 3932 free_ctrlq(struct adapter *sc, int idx) 3933 { 3934 struct sge_wrq *ctrlq = &sc->sge.ctrlq[idx]; 3935 3936 if (ctrlq->eq.flags & EQ_HW_ALLOCATED) { 3937 MPASS(ctrlq->eq.flags & EQ_SW_ALLOCATED); 3938 free_eq_hwq(sc, NULL, &ctrlq->eq); 3939 MPASS(!(ctrlq->eq.flags & EQ_HW_ALLOCATED)); 3940 } 3941 3942 if (ctrlq->eq.flags & EQ_SW_ALLOCATED) { 3943 MPASS(!(ctrlq->eq.flags & EQ_HW_ALLOCATED)); 3944 free_wrq(sc, ctrlq); 3945 MPASS(!(ctrlq->eq.flags & EQ_SW_ALLOCATED)); 3946 } 3947 } 3948 3949 int 3950 t4_sge_set_conm_context(struct adapter *sc, int cntxt_id, int cong_drop, 3951 int cong_map) 3952 { 3953 const int cng_ch_bits_log = sc->chip_params->cng_ch_bits_log; 3954 uint32_t param, val; 3955 uint16_t ch_map; 3956 int cong_mode, rc, i; 3957 3958 if (chip_id(sc) < CHELSIO_T5) 3959 return (ENOTSUP); 3960 3961 /* Convert the driver knob to the mode understood by the firmware. */ 3962 switch (cong_drop) { 3963 case -1: 3964 cong_mode = X_CONMCTXT_CNGTPMODE_DISABLE; 3965 break; 3966 case 0: 3967 cong_mode = X_CONMCTXT_CNGTPMODE_CHANNEL; 3968 break; 3969 case 1: 3970 cong_mode = X_CONMCTXT_CNGTPMODE_QUEUE; 3971 break; 3972 case 2: 3973 cong_mode = X_CONMCTXT_CNGTPMODE_BOTH; 3974 break; 3975 default: 3976 MPASS(0); 3977 CH_ERR(sc, "cong_drop = %d is invalid (ingress queue %d).\n", 3978 cong_drop, cntxt_id); 3979 return (EINVAL); 3980 } 3981 3982 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 3983 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) | 3984 V_FW_PARAMS_PARAM_YZ(cntxt_id); 3985 val = V_CONMCTXT_CNGTPMODE(cong_mode); 3986 if (cong_mode == X_CONMCTXT_CNGTPMODE_CHANNEL || 3987 cong_mode == X_CONMCTXT_CNGTPMODE_BOTH) { 3988 for (i = 0, ch_map = 0; i < 4; i++) { 3989 if (cong_map & (1 << i)) 3990 ch_map |= 1 << (i << cng_ch_bits_log); 3991 } 3992 val |= V_CONMCTXT_CNGCHMAP(ch_map); 3993 } 3994 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 3995 if (rc != 0) { 3996 CH_ERR(sc, "failed to set congestion manager context " 3997 "for ingress queue %d: %d\n", cntxt_id, rc); 3998 } 3999 4000 return (rc); 4001 } 4002 4003 /* 4004 * Idempotent. 4005 */ 4006 static int 4007 alloc_rxq(struct vi_info *vi, struct sge_rxq *rxq, int idx, int intr_idx, 4008 int maxp) 4009 { 4010 int rc; 4011 struct adapter *sc = vi->adapter; 4012 struct ifnet *ifp = vi->ifp; 4013 struct sysctl_oid *oid; 4014 char name[16]; 4015 4016 if (!(rxq->iq.flags & IQ_SW_ALLOCATED)) { 4017 MPASS(!(rxq->iq.flags & IQ_HW_ALLOCATED)); 4018 #if defined(INET) || defined(INET6) 4019 rc = tcp_lro_init_args(&rxq->lro, ifp, lro_entries, lro_mbufs); 4020 if (rc != 0) 4021 return (rc); 4022 MPASS(rxq->lro.ifp == ifp); /* also indicates LRO init'ed */ 4023 #endif 4024 rxq->ifp = ifp; 4025 4026 snprintf(name, sizeof(name), "%d", idx); 4027 oid = SYSCTL_ADD_NODE(&vi->ctx, SYSCTL_CHILDREN(vi->rxq_oid), 4028 OID_AUTO, name, CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 4029 "rx queue"); 4030 4031 init_iq(&rxq->iq, sc, vi->tmr_idx, vi->pktc_idx, vi->qsize_rxq, 4032 intr_idx, cong_drop, IQ_ETH); 4033 #if defined(INET) || defined(INET6) 4034 if (ifp->if_capenable & IFCAP_LRO) 4035 rxq->iq.flags |= IQ_LRO_ENABLED; 4036 #endif 4037 if (ifp->if_capenable & IFCAP_HWRXTSTMP) 4038 rxq->iq.flags |= IQ_RX_TIMESTAMP; 4039 snprintf(name, sizeof(name), "%s rxq%d-fl", 4040 device_get_nameunit(vi->dev), idx); 4041 init_fl(sc, &rxq->fl, vi->qsize_rxq / 8, maxp, name); 4042 rc = alloc_iq_fl(vi, &rxq->iq, &rxq->fl, &vi->ctx, oid); 4043 if (rc != 0) { 4044 CH_ERR(vi, "failed to allocate rxq%d: %d\n", idx, rc); 4045 sysctl_remove_oid(oid, 1, 1); 4046 #if defined(INET) || defined(INET6) 4047 tcp_lro_free(&rxq->lro); 4048 rxq->lro.ifp = NULL; 4049 #endif 4050 return (rc); 4051 } 4052 MPASS(rxq->iq.flags & IQ_SW_ALLOCATED); 4053 add_rxq_sysctls(&vi->ctx, oid, rxq); 4054 } 4055 4056 if (!(rxq->iq.flags & IQ_HW_ALLOCATED)) { 4057 MPASS(rxq->iq.flags & IQ_SW_ALLOCATED); 4058 rc = alloc_iq_fl_hwq(vi, &rxq->iq, &rxq->fl); 4059 if (rc != 0) { 4060 CH_ERR(vi, "failed to create hw rxq%d: %d\n", idx, rc); 4061 return (rc); 4062 } 4063 MPASS(rxq->iq.flags & IQ_HW_ALLOCATED); 4064 4065 if (idx == 0) 4066 sc->sge.iq_base = rxq->iq.abs_id - rxq->iq.cntxt_id; 4067 else 4068 KASSERT(rxq->iq.cntxt_id + sc->sge.iq_base == rxq->iq.abs_id, 4069 ("iq_base mismatch")); 4070 KASSERT(sc->sge.iq_base == 0 || sc->flags & IS_VF, 4071 ("PF with non-zero iq_base")); 4072 4073 /* 4074 * The freelist is just barely above the starvation threshold 4075 * right now, fill it up a bit more. 4076 */ 4077 FL_LOCK(&rxq->fl); 4078 refill_fl(sc, &rxq->fl, 128); 4079 FL_UNLOCK(&rxq->fl); 4080 } 4081 4082 return (0); 4083 } 4084 4085 /* 4086 * Idempotent. 4087 */ 4088 static void 4089 free_rxq(struct vi_info *vi, struct sge_rxq *rxq) 4090 { 4091 if (rxq->iq.flags & IQ_HW_ALLOCATED) { 4092 MPASS(rxq->iq.flags & IQ_SW_ALLOCATED); 4093 free_iq_fl_hwq(vi->adapter, &rxq->iq, &rxq->fl); 4094 MPASS(!(rxq->iq.flags & IQ_HW_ALLOCATED)); 4095 } 4096 4097 if (rxq->iq.flags & IQ_SW_ALLOCATED) { 4098 MPASS(!(rxq->iq.flags & IQ_HW_ALLOCATED)); 4099 #if defined(INET) || defined(INET6) 4100 tcp_lro_free(&rxq->lro); 4101 #endif 4102 free_iq_fl(vi->adapter, &rxq->iq, &rxq->fl); 4103 MPASS(!(rxq->iq.flags & IQ_SW_ALLOCATED)); 4104 bzero(rxq, sizeof(*rxq)); 4105 } 4106 } 4107 4108 static void 4109 add_rxq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid, 4110 struct sge_rxq *rxq) 4111 { 4112 struct sysctl_oid_list *children; 4113 4114 if (ctx == NULL || oid == NULL) 4115 return; 4116 4117 children = SYSCTL_CHILDREN(oid); 4118 #if defined(INET) || defined(INET6) 4119 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "lro_queued", CTLFLAG_RD, 4120 &rxq->lro.lro_queued, 0, NULL); 4121 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "lro_flushed", CTLFLAG_RD, 4122 &rxq->lro.lro_flushed, 0, NULL); 4123 #endif 4124 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "rxcsum", CTLFLAG_RD, 4125 &rxq->rxcsum, "# of times hardware assisted with checksum"); 4126 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "vlan_extraction", CTLFLAG_RD, 4127 &rxq->vlan_extraction, "# of times hardware extracted 802.1Q tag"); 4128 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "vxlan_rxcsum", CTLFLAG_RD, 4129 &rxq->vxlan_rxcsum, 4130 "# of times hardware assisted with inner checksum (VXLAN)"); 4131 } 4132 4133 #ifdef TCP_OFFLOAD 4134 /* 4135 * Idempotent. 4136 */ 4137 static int 4138 alloc_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq, int idx, 4139 int intr_idx, int maxp) 4140 { 4141 int rc; 4142 struct adapter *sc = vi->adapter; 4143 struct sysctl_oid *oid; 4144 char name[16]; 4145 4146 if (!(ofld_rxq->iq.flags & IQ_SW_ALLOCATED)) { 4147 MPASS(!(ofld_rxq->iq.flags & IQ_HW_ALLOCATED)); 4148 4149 snprintf(name, sizeof(name), "%d", idx); 4150 oid = SYSCTL_ADD_NODE(&vi->ctx, 4151 SYSCTL_CHILDREN(vi->ofld_rxq_oid), OID_AUTO, name, 4152 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "offload rx queue"); 4153 4154 init_iq(&ofld_rxq->iq, sc, vi->ofld_tmr_idx, vi->ofld_pktc_idx, 4155 vi->qsize_rxq, intr_idx, ofld_cong_drop, IQ_OFLD); 4156 snprintf(name, sizeof(name), "%s ofld_rxq%d-fl", 4157 device_get_nameunit(vi->dev), idx); 4158 init_fl(sc, &ofld_rxq->fl, vi->qsize_rxq / 8, maxp, name); 4159 rc = alloc_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl, &vi->ctx, 4160 oid); 4161 if (rc != 0) { 4162 CH_ERR(vi, "failed to allocate ofld_rxq%d: %d\n", idx, 4163 rc); 4164 sysctl_remove_oid(oid, 1, 1); 4165 return (rc); 4166 } 4167 MPASS(ofld_rxq->iq.flags & IQ_SW_ALLOCATED); 4168 ofld_rxq->rx_iscsi_ddp_setup_ok = counter_u64_alloc(M_WAITOK); 4169 ofld_rxq->rx_iscsi_ddp_setup_error = 4170 counter_u64_alloc(M_WAITOK); 4171 add_ofld_rxq_sysctls(&vi->ctx, oid, ofld_rxq); 4172 } 4173 4174 if (!(ofld_rxq->iq.flags & IQ_HW_ALLOCATED)) { 4175 MPASS(ofld_rxq->iq.flags & IQ_SW_ALLOCATED); 4176 rc = alloc_iq_fl_hwq(vi, &ofld_rxq->iq, &ofld_rxq->fl); 4177 if (rc != 0) { 4178 CH_ERR(vi, "failed to create hw ofld_rxq%d: %d\n", idx, 4179 rc); 4180 return (rc); 4181 } 4182 MPASS(ofld_rxq->iq.flags & IQ_HW_ALLOCATED); 4183 } 4184 return (rc); 4185 } 4186 4187 /* 4188 * Idempotent. 4189 */ 4190 static void 4191 free_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq) 4192 { 4193 if (ofld_rxq->iq.flags & IQ_HW_ALLOCATED) { 4194 MPASS(ofld_rxq->iq.flags & IQ_SW_ALLOCATED); 4195 free_iq_fl_hwq(vi->adapter, &ofld_rxq->iq, &ofld_rxq->fl); 4196 MPASS(!(ofld_rxq->iq.flags & IQ_HW_ALLOCATED)); 4197 } 4198 4199 if (ofld_rxq->iq.flags & IQ_SW_ALLOCATED) { 4200 MPASS(!(ofld_rxq->iq.flags & IQ_HW_ALLOCATED)); 4201 free_iq_fl(vi->adapter, &ofld_rxq->iq, &ofld_rxq->fl); 4202 MPASS(!(ofld_rxq->iq.flags & IQ_SW_ALLOCATED)); 4203 counter_u64_free(ofld_rxq->rx_iscsi_ddp_setup_ok); 4204 counter_u64_free(ofld_rxq->rx_iscsi_ddp_setup_error); 4205 bzero(ofld_rxq, sizeof(*ofld_rxq)); 4206 } 4207 } 4208 4209 static void 4210 add_ofld_rxq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid, 4211 struct sge_ofld_rxq *ofld_rxq) 4212 { 4213 struct sysctl_oid_list *children; 4214 4215 if (ctx == NULL || oid == NULL) 4216 return; 4217 4218 children = SYSCTL_CHILDREN(oid); 4219 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 4220 "rx_toe_tls_records", CTLFLAG_RD, &ofld_rxq->rx_toe_tls_records, 4221 "# of TOE TLS records received"); 4222 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 4223 "rx_toe_tls_octets", CTLFLAG_RD, &ofld_rxq->rx_toe_tls_octets, 4224 "# of payload octets in received TOE TLS records"); 4225 4226 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "iscsi", 4227 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TOE iSCSI statistics"); 4228 children = SYSCTL_CHILDREN(oid); 4229 4230 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "ddp_setup_ok", 4231 CTLFLAG_RD, &ofld_rxq->rx_iscsi_ddp_setup_ok, 4232 "# of times DDP buffer was setup successfully."); 4233 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "ddp_setup_error", 4234 CTLFLAG_RD, &ofld_rxq->rx_iscsi_ddp_setup_error, 4235 "# of times DDP buffer setup failed."); 4236 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "ddp_octets", 4237 CTLFLAG_RD, &ofld_rxq->rx_iscsi_ddp_octets, 0, 4238 "# of octets placed directly"); 4239 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "ddp_pdus", 4240 CTLFLAG_RD, &ofld_rxq->rx_iscsi_ddp_pdus, 0, 4241 "# of PDUs with data placed directly."); 4242 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "fl_octets", 4243 CTLFLAG_RD, &ofld_rxq->rx_iscsi_fl_octets, 0, 4244 "# of data octets delivered in freelist"); 4245 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "fl_pdus", 4246 CTLFLAG_RD, &ofld_rxq->rx_iscsi_fl_pdus, 0, 4247 "# of PDUs with data delivered in freelist"); 4248 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "padding_errors", 4249 CTLFLAG_RD, &ofld_rxq->rx_iscsi_padding_errors, 0, 4250 "# of PDUs with invalid padding"); 4251 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "header_digest_errors", 4252 CTLFLAG_RD, &ofld_rxq->rx_iscsi_header_digest_errors, 0, 4253 "# of PDUs with invalid header digests"); 4254 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "data_digest_errors", 4255 CTLFLAG_RD, &ofld_rxq->rx_iscsi_data_digest_errors, 0, 4256 "# of PDUs with invalid data digests"); 4257 } 4258 #endif 4259 4260 /* 4261 * Returns a reasonable automatic cidx flush threshold for a given queue size. 4262 */ 4263 static u_int 4264 qsize_to_fthresh(int qsize) 4265 { 4266 u_int fthresh; 4267 4268 while (!powerof2(qsize)) 4269 qsize++; 4270 fthresh = ilog2(qsize); 4271 if (fthresh > X_CIDXFLUSHTHRESH_128) 4272 fthresh = X_CIDXFLUSHTHRESH_128; 4273 4274 return (fthresh); 4275 } 4276 4277 static int 4278 ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq) 4279 { 4280 int rc, cntxt_id; 4281 struct fw_eq_ctrl_cmd c; 4282 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 4283 4284 bzero(&c, sizeof(c)); 4285 4286 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | F_FW_CMD_REQUEST | 4287 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_CTRL_CMD_PFN(sc->pf) | 4288 V_FW_EQ_CTRL_CMD_VFN(0)); 4289 c.alloc_to_len16 = htobe32(F_FW_EQ_CTRL_CMD_ALLOC | 4290 F_FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c)); 4291 c.cmpliqid_eqid = htonl(V_FW_EQ_CTRL_CMD_CMPLIQID(eq->iqid)); 4292 c.physeqid_pkd = htobe32(0); 4293 c.fetchszm_to_iqid = 4294 htobe32(V_FW_EQ_CTRL_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 4295 V_FW_EQ_CTRL_CMD_PCIECHN(eq->tx_chan) | 4296 F_FW_EQ_CTRL_CMD_FETCHRO | V_FW_EQ_CTRL_CMD_IQID(eq->iqid)); 4297 c.dcaen_to_eqsize = 4298 htobe32(V_FW_EQ_CTRL_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ? 4299 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) | 4300 V_FW_EQ_CTRL_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 4301 V_FW_EQ_CTRL_CMD_CIDXFTHRESH(qsize_to_fthresh(qsize)) | 4302 V_FW_EQ_CTRL_CMD_EQSIZE(qsize)); 4303 c.eqaddr = htobe64(eq->ba); 4304 4305 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 4306 if (rc != 0) { 4307 CH_ERR(sc, "failed to create hw ctrlq for tx_chan %d: %d\n", 4308 eq->tx_chan, rc); 4309 return (rc); 4310 } 4311 4312 eq->cntxt_id = G_FW_EQ_CTRL_CMD_EQID(be32toh(c.cmpliqid_eqid)); 4313 eq->abs_id = G_FW_EQ_CTRL_CMD_PHYSEQID(be32toh(c.physeqid_pkd)); 4314 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 4315 if (cntxt_id >= sc->sge.eqmap_sz) 4316 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 4317 cntxt_id, sc->sge.eqmap_sz - 1); 4318 sc->sge.eqmap[cntxt_id] = eq; 4319 4320 return (rc); 4321 } 4322 4323 static int 4324 eth_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 4325 { 4326 int rc, cntxt_id; 4327 struct fw_eq_eth_cmd c; 4328 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 4329 4330 bzero(&c, sizeof(c)); 4331 4332 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST | 4333 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) | 4334 V_FW_EQ_ETH_CMD_VFN(0)); 4335 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC | 4336 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c)); 4337 c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE | 4338 F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(vi->viid)); 4339 c.fetchszm_to_iqid = 4340 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) | 4341 V_FW_EQ_ETH_CMD_PCIECHN(eq->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO | 4342 V_FW_EQ_ETH_CMD_IQID(eq->iqid)); 4343 c.dcaen_to_eqsize = 4344 htobe32(V_FW_EQ_ETH_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ? 4345 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) | 4346 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 4347 V_FW_EQ_ETH_CMD_EQSIZE(qsize)); 4348 c.eqaddr = htobe64(eq->ba); 4349 4350 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 4351 if (rc != 0) { 4352 device_printf(vi->dev, 4353 "failed to create Ethernet egress queue: %d\n", rc); 4354 return (rc); 4355 } 4356 4357 eq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd)); 4358 eq->abs_id = G_FW_EQ_ETH_CMD_PHYSEQID(be32toh(c.physeqid_pkd)); 4359 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 4360 if (cntxt_id >= sc->sge.eqmap_sz) 4361 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 4362 cntxt_id, sc->sge.eqmap_sz - 1); 4363 sc->sge.eqmap[cntxt_id] = eq; 4364 4365 return (rc); 4366 } 4367 4368 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 4369 static int 4370 ofld_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 4371 { 4372 int rc, cntxt_id; 4373 struct fw_eq_ofld_cmd c; 4374 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 4375 4376 bzero(&c, sizeof(c)); 4377 4378 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | F_FW_CMD_REQUEST | 4379 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_OFLD_CMD_PFN(sc->pf) | 4380 V_FW_EQ_OFLD_CMD_VFN(0)); 4381 c.alloc_to_len16 = htonl(F_FW_EQ_OFLD_CMD_ALLOC | 4382 F_FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c)); 4383 c.fetchszm_to_iqid = 4384 htonl(V_FW_EQ_OFLD_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 4385 V_FW_EQ_OFLD_CMD_PCIECHN(eq->tx_chan) | 4386 F_FW_EQ_OFLD_CMD_FETCHRO | V_FW_EQ_OFLD_CMD_IQID(eq->iqid)); 4387 c.dcaen_to_eqsize = 4388 htobe32(V_FW_EQ_OFLD_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ? 4389 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) | 4390 V_FW_EQ_OFLD_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 4391 V_FW_EQ_OFLD_CMD_CIDXFTHRESH(qsize_to_fthresh(qsize)) | 4392 V_FW_EQ_OFLD_CMD_EQSIZE(qsize)); 4393 c.eqaddr = htobe64(eq->ba); 4394 4395 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 4396 if (rc != 0) { 4397 device_printf(vi->dev, 4398 "failed to create egress queue for TCP offload: %d\n", rc); 4399 return (rc); 4400 } 4401 4402 eq->cntxt_id = G_FW_EQ_OFLD_CMD_EQID(be32toh(c.eqid_pkd)); 4403 eq->abs_id = G_FW_EQ_OFLD_CMD_PHYSEQID(be32toh(c.physeqid_pkd)); 4404 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 4405 if (cntxt_id >= sc->sge.eqmap_sz) 4406 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 4407 cntxt_id, sc->sge.eqmap_sz - 1); 4408 sc->sge.eqmap[cntxt_id] = eq; 4409 4410 return (rc); 4411 } 4412 #endif 4413 4414 /* SW only */ 4415 static int 4416 alloc_eq(struct adapter *sc, struct sge_eq *eq, struct sysctl_ctx_list *ctx, 4417 struct sysctl_oid *oid) 4418 { 4419 int rc, qsize; 4420 size_t len; 4421 4422 MPASS(!(eq->flags & EQ_SW_ALLOCATED)); 4423 4424 qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 4425 len = qsize * EQ_ESIZE; 4426 rc = alloc_ring(sc, len, &eq->desc_tag, &eq->desc_map, &eq->ba, 4427 (void **)&eq->desc); 4428 if (rc) 4429 return (rc); 4430 if (ctx != NULL && oid != NULL) 4431 add_eq_sysctls(sc, ctx, oid, eq); 4432 eq->flags |= EQ_SW_ALLOCATED; 4433 4434 return (0); 4435 } 4436 4437 /* SW only */ 4438 static void 4439 free_eq(struct adapter *sc, struct sge_eq *eq) 4440 { 4441 MPASS(eq->flags & EQ_SW_ALLOCATED); 4442 if (eq->type == EQ_ETH) 4443 MPASS(eq->pidx == eq->cidx); 4444 4445 free_ring(sc, eq->desc_tag, eq->desc_map, eq->ba, eq->desc); 4446 mtx_destroy(&eq->eq_lock); 4447 bzero(eq, sizeof(*eq)); 4448 } 4449 4450 static void 4451 add_eq_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx, 4452 struct sysctl_oid *oid, struct sge_eq *eq) 4453 { 4454 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 4455 4456 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, &eq->ba, 4457 "bus address of descriptor ring"); 4458 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 4459 eq->sidx * EQ_ESIZE + sc->params.sge.spg_len, 4460 "desc ring size in bytes"); 4461 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "abs_id", CTLFLAG_RD, 4462 &eq->abs_id, 0, "absolute id of the queue"); 4463 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 4464 &eq->cntxt_id, 0, "SGE context id of the queue"); 4465 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &eq->cidx, 4466 0, "consumer index"); 4467 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &eq->pidx, 4468 0, "producer index"); 4469 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL, 4470 eq->sidx, "status page index"); 4471 } 4472 4473 static int 4474 alloc_eq_hwq(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 4475 { 4476 int rc; 4477 4478 MPASS(!(eq->flags & EQ_HW_ALLOCATED)); 4479 4480 eq->iqid = eq->iq->cntxt_id; 4481 eq->pidx = eq->cidx = eq->dbidx = 0; 4482 /* Note that equeqidx is not used with sge_wrq (OFLD/CTRL) queues. */ 4483 eq->equeqidx = 0; 4484 eq->doorbells = sc->doorbells; 4485 bzero(eq->desc, eq->sidx * EQ_ESIZE + sc->params.sge.spg_len); 4486 4487 switch (eq->type) { 4488 case EQ_CTRL: 4489 rc = ctrl_eq_alloc(sc, eq); 4490 break; 4491 4492 case EQ_ETH: 4493 rc = eth_eq_alloc(sc, vi, eq); 4494 break; 4495 4496 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 4497 case EQ_OFLD: 4498 rc = ofld_eq_alloc(sc, vi, eq); 4499 break; 4500 #endif 4501 4502 default: 4503 panic("%s: invalid eq type %d.", __func__, eq->type); 4504 } 4505 if (rc != 0) { 4506 CH_ERR(sc, "failed to allocate egress queue(%d): %d\n", 4507 eq->type, rc); 4508 return (rc); 4509 } 4510 4511 if (isset(&eq->doorbells, DOORBELL_UDB) || 4512 isset(&eq->doorbells, DOORBELL_UDBWC) || 4513 isset(&eq->doorbells, DOORBELL_WCWR)) { 4514 uint32_t s_qpp = sc->params.sge.eq_s_qpp; 4515 uint32_t mask = (1 << s_qpp) - 1; 4516 volatile uint8_t *udb; 4517 4518 udb = sc->udbs_base + UDBS_DB_OFFSET; 4519 udb += (eq->cntxt_id >> s_qpp) << PAGE_SHIFT; /* pg offset */ 4520 eq->udb_qid = eq->cntxt_id & mask; /* id in page */ 4521 if (eq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE) 4522 clrbit(&eq->doorbells, DOORBELL_WCWR); 4523 else { 4524 udb += eq->udb_qid << UDBS_SEG_SHIFT; /* seg offset */ 4525 eq->udb_qid = 0; 4526 } 4527 eq->udb = (volatile void *)udb; 4528 } 4529 4530 eq->flags |= EQ_HW_ALLOCATED; 4531 return (0); 4532 } 4533 4534 static int 4535 free_eq_hwq(struct adapter *sc, struct vi_info *vi __unused, struct sge_eq *eq) 4536 { 4537 int rc; 4538 4539 MPASS(eq->flags & EQ_HW_ALLOCATED); 4540 4541 switch (eq->type) { 4542 case EQ_CTRL: 4543 rc = -t4_ctrl_eq_free(sc, sc->mbox, sc->pf, 0, eq->cntxt_id); 4544 break; 4545 case EQ_ETH: 4546 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0, eq->cntxt_id); 4547 break; 4548 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 4549 case EQ_OFLD: 4550 rc = -t4_ofld_eq_free(sc, sc->mbox, sc->pf, 0, eq->cntxt_id); 4551 break; 4552 #endif 4553 default: 4554 panic("%s: invalid eq type %d.", __func__, eq->type); 4555 } 4556 if (rc != 0) { 4557 CH_ERR(sc, "failed to free eq (type %d): %d\n", eq->type, rc); 4558 return (rc); 4559 } 4560 eq->flags &= ~EQ_HW_ALLOCATED; 4561 4562 return (0); 4563 } 4564 4565 static int 4566 alloc_wrq(struct adapter *sc, struct vi_info *vi, struct sge_wrq *wrq, 4567 struct sysctl_ctx_list *ctx, struct sysctl_oid *oid) 4568 { 4569 struct sge_eq *eq = &wrq->eq; 4570 int rc; 4571 4572 MPASS(!(eq->flags & EQ_SW_ALLOCATED)); 4573 4574 rc = alloc_eq(sc, eq, ctx, oid); 4575 if (rc) 4576 return (rc); 4577 MPASS(eq->flags & EQ_SW_ALLOCATED); 4578 /* Can't fail after this. */ 4579 4580 wrq->adapter = sc; 4581 TASK_INIT(&wrq->wrq_tx_task, 0, wrq_tx_drain, wrq); 4582 TAILQ_INIT(&wrq->incomplete_wrs); 4583 STAILQ_INIT(&wrq->wr_list); 4584 wrq->nwr_pending = 0; 4585 wrq->ndesc_needed = 0; 4586 add_wrq_sysctls(ctx, oid, wrq); 4587 4588 return (0); 4589 } 4590 4591 static void 4592 free_wrq(struct adapter *sc, struct sge_wrq *wrq) 4593 { 4594 free_eq(sc, &wrq->eq); 4595 MPASS(wrq->nwr_pending == 0); 4596 MPASS(TAILQ_EMPTY(&wrq->incomplete_wrs)); 4597 MPASS(STAILQ_EMPTY(&wrq->wr_list)); 4598 bzero(wrq, sizeof(*wrq)); 4599 } 4600 4601 static void 4602 add_wrq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid, 4603 struct sge_wrq *wrq) 4604 { 4605 struct sysctl_oid_list *children; 4606 4607 if (ctx == NULL || oid == NULL) 4608 return; 4609 4610 children = SYSCTL_CHILDREN(oid); 4611 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_direct", CTLFLAG_RD, 4612 &wrq->tx_wrs_direct, "# of work requests (direct)"); 4613 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_copied", CTLFLAG_RD, 4614 &wrq->tx_wrs_copied, "# of work requests (copied)"); 4615 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_sspace", CTLFLAG_RD, 4616 &wrq->tx_wrs_ss, "# of work requests (copied from scratch space)"); 4617 } 4618 4619 /* 4620 * Idempotent. 4621 */ 4622 static int 4623 alloc_txq(struct vi_info *vi, struct sge_txq *txq, int idx) 4624 { 4625 int rc, iqidx; 4626 struct port_info *pi = vi->pi; 4627 struct adapter *sc = vi->adapter; 4628 struct sge_eq *eq = &txq->eq; 4629 struct txpkts *txp; 4630 char name[16]; 4631 struct sysctl_oid *oid; 4632 4633 if (!(eq->flags & EQ_SW_ALLOCATED)) { 4634 MPASS(!(eq->flags & EQ_HW_ALLOCATED)); 4635 4636 snprintf(name, sizeof(name), "%d", idx); 4637 oid = SYSCTL_ADD_NODE(&vi->ctx, SYSCTL_CHILDREN(vi->txq_oid), 4638 OID_AUTO, name, CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 4639 "tx queue"); 4640 4641 iqidx = vi->first_rxq + (idx % vi->nrxq); 4642 snprintf(name, sizeof(name), "%s txq%d", 4643 device_get_nameunit(vi->dev), idx); 4644 init_eq(sc, &txq->eq, EQ_ETH, vi->qsize_txq, pi->tx_chan, 4645 &sc->sge.rxq[iqidx].iq, name); 4646 4647 rc = mp_ring_alloc(&txq->r, eq->sidx, txq, eth_tx, 4648 can_resume_eth_tx, M_CXGBE, &eq->eq_lock, M_WAITOK); 4649 if (rc != 0) { 4650 CH_ERR(vi, "failed to allocate mp_ring for txq%d: %d\n", 4651 idx, rc); 4652 failed: 4653 sysctl_remove_oid(oid, 1, 1); 4654 return (rc); 4655 } 4656 4657 rc = alloc_eq(sc, eq, &vi->ctx, oid); 4658 if (rc) { 4659 CH_ERR(vi, "failed to allocate txq%d: %d\n", idx, rc); 4660 mp_ring_free(txq->r); 4661 goto failed; 4662 } 4663 MPASS(eq->flags & EQ_SW_ALLOCATED); 4664 /* Can't fail after this point. */ 4665 4666 TASK_INIT(&txq->tx_reclaim_task, 0, tx_reclaim, eq); 4667 txq->ifp = vi->ifp; 4668 txq->gl = sglist_alloc(TX_SGL_SEGS, M_WAITOK); 4669 txq->sdesc = malloc(eq->sidx * sizeof(struct tx_sdesc), M_CXGBE, 4670 M_ZERO | M_WAITOK); 4671 4672 add_txq_sysctls(vi, &vi->ctx, oid, txq); 4673 } 4674 4675 if (!(eq->flags & EQ_HW_ALLOCATED)) { 4676 MPASS(eq->flags & EQ_SW_ALLOCATED); 4677 rc = alloc_eq_hwq(sc, vi, eq); 4678 if (rc != 0) { 4679 CH_ERR(vi, "failed to create hw txq%d: %d\n", idx, rc); 4680 return (rc); 4681 } 4682 MPASS(eq->flags & EQ_HW_ALLOCATED); 4683 /* Can't fail after this point. */ 4684 4685 if (idx == 0) 4686 sc->sge.eq_base = eq->abs_id - eq->cntxt_id; 4687 else 4688 KASSERT(eq->cntxt_id + sc->sge.eq_base == eq->abs_id, 4689 ("eq_base mismatch")); 4690 KASSERT(sc->sge.eq_base == 0 || sc->flags & IS_VF, 4691 ("PF with non-zero eq_base")); 4692 4693 txp = &txq->txp; 4694 MPASS(nitems(txp->mb) >= sc->params.max_pkts_per_eth_tx_pkts_wr); 4695 txq->txp.max_npkt = min(nitems(txp->mb), 4696 sc->params.max_pkts_per_eth_tx_pkts_wr); 4697 if (vi->flags & TX_USES_VM_WR && !(sc->flags & IS_VF)) 4698 txq->txp.max_npkt--; 4699 4700 if (vi->flags & TX_USES_VM_WR) 4701 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) | 4702 V_TXPKT_INTF(pi->tx_chan)); 4703 else 4704 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) | 4705 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(sc->pf) | 4706 V_TXPKT_VF(vi->vin) | V_TXPKT_VF_VLD(vi->vfvld)); 4707 4708 txq->tc_idx = -1; 4709 } 4710 4711 return (0); 4712 } 4713 4714 /* 4715 * Idempotent. 4716 */ 4717 static void 4718 free_txq(struct vi_info *vi, struct sge_txq *txq) 4719 { 4720 struct adapter *sc = vi->adapter; 4721 struct sge_eq *eq = &txq->eq; 4722 4723 if (eq->flags & EQ_HW_ALLOCATED) { 4724 MPASS(eq->flags & EQ_SW_ALLOCATED); 4725 free_eq_hwq(sc, NULL, eq); 4726 MPASS(!(eq->flags & EQ_HW_ALLOCATED)); 4727 } 4728 4729 if (eq->flags & EQ_SW_ALLOCATED) { 4730 MPASS(!(eq->flags & EQ_HW_ALLOCATED)); 4731 sglist_free(txq->gl); 4732 free(txq->sdesc, M_CXGBE); 4733 mp_ring_free(txq->r); 4734 free_eq(sc, eq); 4735 MPASS(!(eq->flags & EQ_SW_ALLOCATED)); 4736 bzero(txq, sizeof(*txq)); 4737 } 4738 } 4739 4740 static void 4741 add_txq_sysctls(struct vi_info *vi, struct sysctl_ctx_list *ctx, 4742 struct sysctl_oid *oid, struct sge_txq *txq) 4743 { 4744 struct adapter *sc; 4745 struct sysctl_oid_list *children; 4746 4747 if (ctx == NULL || oid == NULL) 4748 return; 4749 4750 sc = vi->adapter; 4751 children = SYSCTL_CHILDREN(oid); 4752 4753 mp_ring_sysctls(txq->r, ctx, children); 4754 4755 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tc", 4756 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, txq - sc->sge.txq, 4757 sysctl_tc, "I", "traffic class (-1 means none)"); 4758 4759 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txcsum", CTLFLAG_RD, 4760 &txq->txcsum, "# of times hardware assisted with checksum"); 4761 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "vlan_insertion", CTLFLAG_RD, 4762 &txq->vlan_insertion, "# of times hardware inserted 802.1Q tag"); 4763 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tso_wrs", CTLFLAG_RD, 4764 &txq->tso_wrs, "# of TSO work requests"); 4765 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "imm_wrs", CTLFLAG_RD, 4766 &txq->imm_wrs, "# of work requests with immediate data"); 4767 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "sgl_wrs", CTLFLAG_RD, 4768 &txq->sgl_wrs, "# of work requests with direct SGL"); 4769 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkt_wrs", CTLFLAG_RD, 4770 &txq->txpkt_wrs, "# of txpkt work requests (one pkt/WR)"); 4771 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkts0_wrs", CTLFLAG_RD, 4772 &txq->txpkts0_wrs, "# of txpkts (type 0) work requests"); 4773 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkts1_wrs", CTLFLAG_RD, 4774 &txq->txpkts1_wrs, "# of txpkts (type 1) work requests"); 4775 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkts0_pkts", CTLFLAG_RD, 4776 &txq->txpkts0_pkts, 4777 "# of frames tx'd using type0 txpkts work requests"); 4778 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkts1_pkts", CTLFLAG_RD, 4779 &txq->txpkts1_pkts, 4780 "# of frames tx'd using type1 txpkts work requests"); 4781 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkts_flush", CTLFLAG_RD, 4782 &txq->txpkts_flush, 4783 "# of times txpkts had to be flushed out by an egress-update"); 4784 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "raw_wrs", CTLFLAG_RD, 4785 &txq->raw_wrs, "# of raw work requests (non-packets)"); 4786 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "vxlan_tso_wrs", CTLFLAG_RD, 4787 &txq->vxlan_tso_wrs, "# of VXLAN TSO work requests"); 4788 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "vxlan_txcsum", CTLFLAG_RD, 4789 &txq->vxlan_txcsum, 4790 "# of times hardware assisted with inner checksums (VXLAN)"); 4791 4792 #ifdef KERN_TLS 4793 if (is_ktls(sc)) { 4794 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_records", 4795 CTLFLAG_RD, &txq->kern_tls_records, 4796 "# of NIC TLS records transmitted"); 4797 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_short", 4798 CTLFLAG_RD, &txq->kern_tls_short, 4799 "# of short NIC TLS records transmitted"); 4800 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_partial", 4801 CTLFLAG_RD, &txq->kern_tls_partial, 4802 "# of partial NIC TLS records transmitted"); 4803 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_full", 4804 CTLFLAG_RD, &txq->kern_tls_full, 4805 "# of full NIC TLS records transmitted"); 4806 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_octets", 4807 CTLFLAG_RD, &txq->kern_tls_octets, 4808 "# of payload octets in transmitted NIC TLS records"); 4809 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_waste", 4810 CTLFLAG_RD, &txq->kern_tls_waste, 4811 "# of octets DMAd but not transmitted in NIC TLS records"); 4812 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_options", 4813 CTLFLAG_RD, &txq->kern_tls_options, 4814 "# of NIC TLS options-only packets transmitted"); 4815 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_header", 4816 CTLFLAG_RD, &txq->kern_tls_header, 4817 "# of NIC TLS header-only packets transmitted"); 4818 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_fin", 4819 CTLFLAG_RD, &txq->kern_tls_fin, 4820 "# of NIC TLS FIN-only packets transmitted"); 4821 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_fin_short", 4822 CTLFLAG_RD, &txq->kern_tls_fin_short, 4823 "# of NIC TLS padded FIN packets on short TLS records"); 4824 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_cbc", 4825 CTLFLAG_RD, &txq->kern_tls_cbc, 4826 "# of NIC TLS sessions using AES-CBC"); 4827 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_gcm", 4828 CTLFLAG_RD, &txq->kern_tls_gcm, 4829 "# of NIC TLS sessions using AES-GCM"); 4830 } 4831 #endif 4832 } 4833 4834 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 4835 /* 4836 * Idempotent. 4837 */ 4838 static int 4839 alloc_ofld_txq(struct vi_info *vi, struct sge_ofld_txq *ofld_txq, int idx) 4840 { 4841 struct sysctl_oid *oid; 4842 struct port_info *pi = vi->pi; 4843 struct adapter *sc = vi->adapter; 4844 struct sge_eq *eq = &ofld_txq->wrq.eq; 4845 int rc, iqidx; 4846 char name[16]; 4847 4848 MPASS(idx >= 0); 4849 MPASS(idx < vi->nofldtxq); 4850 4851 if (!(eq->flags & EQ_SW_ALLOCATED)) { 4852 snprintf(name, sizeof(name), "%d", idx); 4853 oid = SYSCTL_ADD_NODE(&vi->ctx, 4854 SYSCTL_CHILDREN(vi->ofld_txq_oid), OID_AUTO, name, 4855 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "offload tx queue"); 4856 4857 snprintf(name, sizeof(name), "%s ofld_txq%d", 4858 device_get_nameunit(vi->dev), idx); 4859 if (vi->nofldrxq > 0) { 4860 iqidx = vi->first_ofld_rxq + (idx % vi->nofldrxq); 4861 init_eq(sc, eq, EQ_OFLD, vi->qsize_txq, pi->tx_chan, 4862 &sc->sge.ofld_rxq[iqidx].iq, name); 4863 } else { 4864 iqidx = vi->first_rxq + (idx % vi->nrxq); 4865 init_eq(sc, eq, EQ_OFLD, vi->qsize_txq, pi->tx_chan, 4866 &sc->sge.rxq[iqidx].iq, name); 4867 } 4868 4869 rc = alloc_wrq(sc, vi, &ofld_txq->wrq, &vi->ctx, oid); 4870 if (rc != 0) { 4871 CH_ERR(vi, "failed to allocate ofld_txq%d: %d\n", idx, 4872 rc); 4873 sysctl_remove_oid(oid, 1, 1); 4874 return (rc); 4875 } 4876 MPASS(eq->flags & EQ_SW_ALLOCATED); 4877 /* Can't fail after this point. */ 4878 4879 ofld_txq->tx_iscsi_pdus = counter_u64_alloc(M_WAITOK); 4880 ofld_txq->tx_iscsi_octets = counter_u64_alloc(M_WAITOK); 4881 ofld_txq->tx_iscsi_iso_wrs = counter_u64_alloc(M_WAITOK); 4882 ofld_txq->tx_toe_tls_records = counter_u64_alloc(M_WAITOK); 4883 ofld_txq->tx_toe_tls_octets = counter_u64_alloc(M_WAITOK); 4884 add_ofld_txq_sysctls(&vi->ctx, oid, ofld_txq); 4885 } 4886 4887 if (!(eq->flags & EQ_HW_ALLOCATED)) { 4888 rc = alloc_eq_hwq(sc, vi, eq); 4889 if (rc != 0) { 4890 CH_ERR(vi, "failed to create hw ofld_txq%d: %d\n", idx, 4891 rc); 4892 return (rc); 4893 } 4894 MPASS(eq->flags & EQ_HW_ALLOCATED); 4895 } 4896 4897 return (0); 4898 } 4899 4900 /* 4901 * Idempotent. 4902 */ 4903 static void 4904 free_ofld_txq(struct vi_info *vi, struct sge_ofld_txq *ofld_txq) 4905 { 4906 struct adapter *sc = vi->adapter; 4907 struct sge_eq *eq = &ofld_txq->wrq.eq; 4908 4909 if (eq->flags & EQ_HW_ALLOCATED) { 4910 MPASS(eq->flags & EQ_SW_ALLOCATED); 4911 free_eq_hwq(sc, NULL, eq); 4912 MPASS(!(eq->flags & EQ_HW_ALLOCATED)); 4913 } 4914 4915 if (eq->flags & EQ_SW_ALLOCATED) { 4916 MPASS(!(eq->flags & EQ_HW_ALLOCATED)); 4917 counter_u64_free(ofld_txq->tx_iscsi_pdus); 4918 counter_u64_free(ofld_txq->tx_iscsi_octets); 4919 counter_u64_free(ofld_txq->tx_iscsi_iso_wrs); 4920 counter_u64_free(ofld_txq->tx_toe_tls_records); 4921 counter_u64_free(ofld_txq->tx_toe_tls_octets); 4922 free_wrq(sc, &ofld_txq->wrq); 4923 MPASS(!(eq->flags & EQ_SW_ALLOCATED)); 4924 bzero(ofld_txq, sizeof(*ofld_txq)); 4925 } 4926 } 4927 4928 static void 4929 add_ofld_txq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid, 4930 struct sge_ofld_txq *ofld_txq) 4931 { 4932 struct sysctl_oid_list *children; 4933 4934 if (ctx == NULL || oid == NULL) 4935 return; 4936 4937 children = SYSCTL_CHILDREN(oid); 4938 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_iscsi_pdus", 4939 CTLFLAG_RD, &ofld_txq->tx_iscsi_pdus, 4940 "# of iSCSI PDUs transmitted"); 4941 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_iscsi_octets", 4942 CTLFLAG_RD, &ofld_txq->tx_iscsi_octets, 4943 "# of payload octets in transmitted iSCSI PDUs"); 4944 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_iscsi_iso_wrs", 4945 CTLFLAG_RD, &ofld_txq->tx_iscsi_iso_wrs, 4946 "# of iSCSI segmentation offload work requests"); 4947 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_toe_tls_records", 4948 CTLFLAG_RD, &ofld_txq->tx_toe_tls_records, 4949 "# of TOE TLS records transmitted"); 4950 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_toe_tls_octets", 4951 CTLFLAG_RD, &ofld_txq->tx_toe_tls_octets, 4952 "# of payload octets in transmitted TOE TLS records"); 4953 } 4954 #endif 4955 4956 static void 4957 oneseg_dma_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error) 4958 { 4959 bus_addr_t *ba = arg; 4960 4961 KASSERT(nseg == 1, 4962 ("%s meant for single segment mappings only.", __func__)); 4963 4964 *ba = error ? 0 : segs->ds_addr; 4965 } 4966 4967 static inline void 4968 ring_fl_db(struct adapter *sc, struct sge_fl *fl) 4969 { 4970 uint32_t n, v; 4971 4972 n = IDXDIFF(fl->pidx >> 3, fl->dbidx, fl->sidx); 4973 MPASS(n > 0); 4974 4975 wmb(); 4976 v = fl->dbval | V_PIDX(n); 4977 if (fl->udb) 4978 *fl->udb = htole32(v); 4979 else 4980 t4_write_reg(sc, sc->sge_kdoorbell_reg, v); 4981 IDXINCR(fl->dbidx, n, fl->sidx); 4982 } 4983 4984 /* 4985 * Fills up the freelist by allocating up to 'n' buffers. Buffers that are 4986 * recycled do not count towards this allocation budget. 4987 * 4988 * Returns non-zero to indicate that this freelist should be added to the list 4989 * of starving freelists. 4990 */ 4991 static int 4992 refill_fl(struct adapter *sc, struct sge_fl *fl, int n) 4993 { 4994 __be64 *d; 4995 struct fl_sdesc *sd; 4996 uintptr_t pa; 4997 caddr_t cl; 4998 struct rx_buf_info *rxb; 4999 struct cluster_metadata *clm; 5000 uint16_t max_pidx, zidx = fl->zidx; 5001 uint16_t hw_cidx = fl->hw_cidx; /* stable snapshot */ 5002 5003 FL_LOCK_ASSERT_OWNED(fl); 5004 5005 /* 5006 * We always stop at the beginning of the hardware descriptor that's just 5007 * before the one with the hw cidx. This is to avoid hw pidx = hw cidx, 5008 * which would mean an empty freelist to the chip. 5009 */ 5010 max_pidx = __predict_false(hw_cidx == 0) ? fl->sidx - 1 : hw_cidx - 1; 5011 if (fl->pidx == max_pidx * 8) 5012 return (0); 5013 5014 d = &fl->desc[fl->pidx]; 5015 sd = &fl->sdesc[fl->pidx]; 5016 rxb = &sc->sge.rx_buf_info[zidx]; 5017 5018 while (n > 0) { 5019 5020 if (sd->cl != NULL) { 5021 5022 if (sd->nmbuf == 0) { 5023 /* 5024 * Fast recycle without involving any atomics on 5025 * the cluster's metadata (if the cluster has 5026 * metadata). This happens when all frames 5027 * received in the cluster were small enough to 5028 * fit within a single mbuf each. 5029 */ 5030 fl->cl_fast_recycled++; 5031 goto recycled; 5032 } 5033 5034 /* 5035 * Cluster is guaranteed to have metadata. Clusters 5036 * without metadata always take the fast recycle path 5037 * when they're recycled. 5038 */ 5039 clm = cl_metadata(sd); 5040 MPASS(clm != NULL); 5041 5042 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) { 5043 fl->cl_recycled++; 5044 counter_u64_add(extfree_rels, 1); 5045 goto recycled; 5046 } 5047 sd->cl = NULL; /* gave up my reference */ 5048 } 5049 MPASS(sd->cl == NULL); 5050 cl = uma_zalloc(rxb->zone, M_NOWAIT); 5051 if (__predict_false(cl == NULL)) { 5052 if (zidx != fl->safe_zidx) { 5053 zidx = fl->safe_zidx; 5054 rxb = &sc->sge.rx_buf_info[zidx]; 5055 cl = uma_zalloc(rxb->zone, M_NOWAIT); 5056 } 5057 if (cl == NULL) 5058 break; 5059 } 5060 fl->cl_allocated++; 5061 n--; 5062 5063 pa = pmap_kextract((vm_offset_t)cl); 5064 sd->cl = cl; 5065 sd->zidx = zidx; 5066 5067 if (fl->flags & FL_BUF_PACKING) { 5068 *d = htobe64(pa | rxb->hwidx2); 5069 sd->moff = rxb->size2; 5070 } else { 5071 *d = htobe64(pa | rxb->hwidx1); 5072 sd->moff = 0; 5073 } 5074 recycled: 5075 sd->nmbuf = 0; 5076 d++; 5077 sd++; 5078 if (__predict_false((++fl->pidx & 7) == 0)) { 5079 uint16_t pidx = fl->pidx >> 3; 5080 5081 if (__predict_false(pidx == fl->sidx)) { 5082 fl->pidx = 0; 5083 pidx = 0; 5084 sd = fl->sdesc; 5085 d = fl->desc; 5086 } 5087 if (n < 8 || pidx == max_pidx) 5088 break; 5089 5090 if (IDXDIFF(pidx, fl->dbidx, fl->sidx) >= 4) 5091 ring_fl_db(sc, fl); 5092 } 5093 } 5094 5095 if ((fl->pidx >> 3) != fl->dbidx) 5096 ring_fl_db(sc, fl); 5097 5098 return (FL_RUNNING_LOW(fl) && !(fl->flags & FL_STARVING)); 5099 } 5100 5101 /* 5102 * Attempt to refill all starving freelists. 5103 */ 5104 static void 5105 refill_sfl(void *arg) 5106 { 5107 struct adapter *sc = arg; 5108 struct sge_fl *fl, *fl_temp; 5109 5110 mtx_assert(&sc->sfl_lock, MA_OWNED); 5111 TAILQ_FOREACH_SAFE(fl, &sc->sfl, link, fl_temp) { 5112 FL_LOCK(fl); 5113 refill_fl(sc, fl, 64); 5114 if (FL_NOT_RUNNING_LOW(fl) || fl->flags & FL_DOOMED) { 5115 TAILQ_REMOVE(&sc->sfl, fl, link); 5116 fl->flags &= ~FL_STARVING; 5117 } 5118 FL_UNLOCK(fl); 5119 } 5120 5121 if (!TAILQ_EMPTY(&sc->sfl)) 5122 callout_schedule(&sc->sfl_callout, hz / 5); 5123 } 5124 5125 /* 5126 * Release the driver's reference on all buffers in the given freelist. Buffers 5127 * with kernel references cannot be freed and will prevent the driver from being 5128 * unloaded safely. 5129 */ 5130 void 5131 free_fl_buffers(struct adapter *sc, struct sge_fl *fl) 5132 { 5133 struct fl_sdesc *sd; 5134 struct cluster_metadata *clm; 5135 int i; 5136 5137 sd = fl->sdesc; 5138 for (i = 0; i < fl->sidx * 8; i++, sd++) { 5139 if (sd->cl == NULL) 5140 continue; 5141 5142 if (sd->nmbuf == 0) 5143 uma_zfree(sc->sge.rx_buf_info[sd->zidx].zone, sd->cl); 5144 else if (fl->flags & FL_BUF_PACKING) { 5145 clm = cl_metadata(sd); 5146 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) { 5147 uma_zfree(sc->sge.rx_buf_info[sd->zidx].zone, 5148 sd->cl); 5149 counter_u64_add(extfree_rels, 1); 5150 } 5151 } 5152 sd->cl = NULL; 5153 } 5154 5155 if (fl->flags & FL_BUF_RESUME) { 5156 m_freem(fl->m0); 5157 fl->flags &= ~FL_BUF_RESUME; 5158 } 5159 } 5160 5161 static inline void 5162 get_pkt_gl(struct mbuf *m, struct sglist *gl) 5163 { 5164 int rc; 5165 5166 M_ASSERTPKTHDR(m); 5167 5168 sglist_reset(gl); 5169 rc = sglist_append_mbuf(gl, m); 5170 if (__predict_false(rc != 0)) { 5171 panic("%s: mbuf %p (%d segs) was vetted earlier but now fails " 5172 "with %d.", __func__, m, mbuf_nsegs(m), rc); 5173 } 5174 5175 KASSERT(gl->sg_nseg == mbuf_nsegs(m), 5176 ("%s: nsegs changed for mbuf %p from %d to %d", __func__, m, 5177 mbuf_nsegs(m), gl->sg_nseg)); 5178 #if 0 /* vm_wr not readily available here. */ 5179 KASSERT(gl->sg_nseg > 0 && gl->sg_nseg <= max_nsegs_allowed(m, vm_wr), 5180 ("%s: %d segments, should have been 1 <= nsegs <= %d", __func__, 5181 gl->sg_nseg, max_nsegs_allowed(m, vm_wr))); 5182 #endif 5183 } 5184 5185 /* 5186 * len16 for a txpkt WR with a GL. Includes the firmware work request header. 5187 */ 5188 static inline u_int 5189 txpkt_len16(u_int nsegs, const u_int extra) 5190 { 5191 u_int n; 5192 5193 MPASS(nsegs > 0); 5194 5195 nsegs--; /* first segment is part of ulptx_sgl */ 5196 n = extra + sizeof(struct fw_eth_tx_pkt_wr) + 5197 sizeof(struct cpl_tx_pkt_core) + 5198 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 5199 5200 return (howmany(n, 16)); 5201 } 5202 5203 /* 5204 * len16 for a txpkt_vm WR with a GL. Includes the firmware work 5205 * request header. 5206 */ 5207 static inline u_int 5208 txpkt_vm_len16(u_int nsegs, const u_int extra) 5209 { 5210 u_int n; 5211 5212 MPASS(nsegs > 0); 5213 5214 nsegs--; /* first segment is part of ulptx_sgl */ 5215 n = extra + sizeof(struct fw_eth_tx_pkt_vm_wr) + 5216 sizeof(struct cpl_tx_pkt_core) + 5217 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 5218 5219 return (howmany(n, 16)); 5220 } 5221 5222 static inline void 5223 calculate_mbuf_len16(struct mbuf *m, bool vm_wr) 5224 { 5225 const int lso = sizeof(struct cpl_tx_pkt_lso_core); 5226 const int tnl_lso = sizeof(struct cpl_tx_tnl_lso); 5227 5228 if (vm_wr) { 5229 if (needs_tso(m)) 5230 set_mbuf_len16(m, txpkt_vm_len16(mbuf_nsegs(m), lso)); 5231 else 5232 set_mbuf_len16(m, txpkt_vm_len16(mbuf_nsegs(m), 0)); 5233 return; 5234 } 5235 5236 if (needs_tso(m)) { 5237 if (needs_vxlan_tso(m)) 5238 set_mbuf_len16(m, txpkt_len16(mbuf_nsegs(m), tnl_lso)); 5239 else 5240 set_mbuf_len16(m, txpkt_len16(mbuf_nsegs(m), lso)); 5241 } else 5242 set_mbuf_len16(m, txpkt_len16(mbuf_nsegs(m), 0)); 5243 } 5244 5245 /* 5246 * len16 for a txpkts type 0 WR with a GL. Does not include the firmware work 5247 * request header. 5248 */ 5249 static inline u_int 5250 txpkts0_len16(u_int nsegs) 5251 { 5252 u_int n; 5253 5254 MPASS(nsegs > 0); 5255 5256 nsegs--; /* first segment is part of ulptx_sgl */ 5257 n = sizeof(struct ulp_txpkt) + sizeof(struct ulptx_idata) + 5258 sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl) + 5259 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 5260 5261 return (howmany(n, 16)); 5262 } 5263 5264 /* 5265 * len16 for a txpkts type 1 WR with a GL. Does not include the firmware work 5266 * request header. 5267 */ 5268 static inline u_int 5269 txpkts1_len16(void) 5270 { 5271 u_int n; 5272 5273 n = sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl); 5274 5275 return (howmany(n, 16)); 5276 } 5277 5278 static inline u_int 5279 imm_payload(u_int ndesc) 5280 { 5281 u_int n; 5282 5283 n = ndesc * EQ_ESIZE - sizeof(struct fw_eth_tx_pkt_wr) - 5284 sizeof(struct cpl_tx_pkt_core); 5285 5286 return (n); 5287 } 5288 5289 static inline uint64_t 5290 csum_to_ctrl(struct adapter *sc, struct mbuf *m) 5291 { 5292 uint64_t ctrl; 5293 int csum_type, l2hlen, l3hlen; 5294 int x, y; 5295 static const int csum_types[3][2] = { 5296 {TX_CSUM_TCPIP, TX_CSUM_TCPIP6}, 5297 {TX_CSUM_UDPIP, TX_CSUM_UDPIP6}, 5298 {TX_CSUM_IP, 0} 5299 }; 5300 5301 M_ASSERTPKTHDR(m); 5302 5303 if (!needs_hwcsum(m)) 5304 return (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS); 5305 5306 MPASS(m->m_pkthdr.l2hlen >= ETHER_HDR_LEN); 5307 MPASS(m->m_pkthdr.l3hlen >= sizeof(struct ip)); 5308 5309 if (needs_vxlan_csum(m)) { 5310 MPASS(m->m_pkthdr.l4hlen > 0); 5311 MPASS(m->m_pkthdr.l5hlen > 0); 5312 MPASS(m->m_pkthdr.inner_l2hlen >= ETHER_HDR_LEN); 5313 MPASS(m->m_pkthdr.inner_l3hlen >= sizeof(struct ip)); 5314 5315 l2hlen = m->m_pkthdr.l2hlen + m->m_pkthdr.l3hlen + 5316 m->m_pkthdr.l4hlen + m->m_pkthdr.l5hlen + 5317 m->m_pkthdr.inner_l2hlen - ETHER_HDR_LEN; 5318 l3hlen = m->m_pkthdr.inner_l3hlen; 5319 } else { 5320 l2hlen = m->m_pkthdr.l2hlen - ETHER_HDR_LEN; 5321 l3hlen = m->m_pkthdr.l3hlen; 5322 } 5323 5324 ctrl = 0; 5325 if (!needs_l3_csum(m)) 5326 ctrl |= F_TXPKT_IPCSUM_DIS; 5327 5328 if (m->m_pkthdr.csum_flags & (CSUM_IP_TCP | CSUM_INNER_IP_TCP | 5329 CSUM_IP6_TCP | CSUM_INNER_IP6_TCP)) 5330 x = 0; /* TCP */ 5331 else if (m->m_pkthdr.csum_flags & (CSUM_IP_UDP | CSUM_INNER_IP_UDP | 5332 CSUM_IP6_UDP | CSUM_INNER_IP6_UDP)) 5333 x = 1; /* UDP */ 5334 else 5335 x = 2; 5336 5337 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_IP_TCP | CSUM_IP_UDP | 5338 CSUM_INNER_IP | CSUM_INNER_IP_TCP | CSUM_INNER_IP_UDP)) 5339 y = 0; /* IPv4 */ 5340 else { 5341 MPASS(m->m_pkthdr.csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | 5342 CSUM_INNER_IP6_TCP | CSUM_INNER_IP6_UDP)); 5343 y = 1; /* IPv6 */ 5344 } 5345 /* 5346 * needs_hwcsum returned true earlier so there must be some kind of 5347 * checksum to calculate. 5348 */ 5349 csum_type = csum_types[x][y]; 5350 MPASS(csum_type != 0); 5351 if (csum_type == TX_CSUM_IP) 5352 ctrl |= F_TXPKT_L4CSUM_DIS; 5353 ctrl |= V_TXPKT_CSUM_TYPE(csum_type) | V_TXPKT_IPHDR_LEN(l3hlen); 5354 if (chip_id(sc) <= CHELSIO_T5) 5355 ctrl |= V_TXPKT_ETHHDR_LEN(l2hlen); 5356 else 5357 ctrl |= V_T6_TXPKT_ETHHDR_LEN(l2hlen); 5358 5359 return (ctrl); 5360 } 5361 5362 static inline void * 5363 write_lso_cpl(void *cpl, struct mbuf *m0) 5364 { 5365 struct cpl_tx_pkt_lso_core *lso; 5366 uint32_t ctrl; 5367 5368 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 5369 m0->m_pkthdr.l4hlen > 0, 5370 ("%s: mbuf %p needs TSO but missing header lengths", 5371 __func__, m0)); 5372 5373 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | 5374 F_LSO_FIRST_SLICE | F_LSO_LAST_SLICE | 5375 V_LSO_ETHHDR_LEN((m0->m_pkthdr.l2hlen - ETHER_HDR_LEN) >> 2) | 5376 V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) | 5377 V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2); 5378 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 5379 ctrl |= F_LSO_IPV6; 5380 5381 lso = cpl; 5382 lso->lso_ctrl = htobe32(ctrl); 5383 lso->ipid_ofst = htobe16(0); 5384 lso->mss = htobe16(m0->m_pkthdr.tso_segsz); 5385 lso->seqno_offset = htobe32(0); 5386 lso->len = htobe32(m0->m_pkthdr.len); 5387 5388 return (lso + 1); 5389 } 5390 5391 static void * 5392 write_tnl_lso_cpl(void *cpl, struct mbuf *m0) 5393 { 5394 struct cpl_tx_tnl_lso *tnl_lso = cpl; 5395 uint32_t ctrl; 5396 5397 KASSERT(m0->m_pkthdr.inner_l2hlen > 0 && 5398 m0->m_pkthdr.inner_l3hlen > 0 && m0->m_pkthdr.inner_l4hlen > 0 && 5399 m0->m_pkthdr.inner_l5hlen > 0, 5400 ("%s: mbuf %p needs VXLAN_TSO but missing inner header lengths", 5401 __func__, m0)); 5402 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 5403 m0->m_pkthdr.l4hlen > 0 && m0->m_pkthdr.l5hlen > 0, 5404 ("%s: mbuf %p needs VXLAN_TSO but missing outer header lengths", 5405 __func__, m0)); 5406 5407 /* Outer headers. */ 5408 ctrl = V_CPL_TX_TNL_LSO_OPCODE(CPL_TX_TNL_LSO) | 5409 F_CPL_TX_TNL_LSO_FIRST | F_CPL_TX_TNL_LSO_LAST | 5410 V_CPL_TX_TNL_LSO_ETHHDRLENOUT( 5411 (m0->m_pkthdr.l2hlen - ETHER_HDR_LEN) >> 2) | 5412 V_CPL_TX_TNL_LSO_IPHDRLENOUT(m0->m_pkthdr.l3hlen >> 2) | 5413 F_CPL_TX_TNL_LSO_IPLENSETOUT; 5414 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 5415 ctrl |= F_CPL_TX_TNL_LSO_IPV6OUT; 5416 else { 5417 ctrl |= F_CPL_TX_TNL_LSO_IPHDRCHKOUT | 5418 F_CPL_TX_TNL_LSO_IPIDINCOUT; 5419 } 5420 tnl_lso->op_to_IpIdSplitOut = htobe32(ctrl); 5421 tnl_lso->IpIdOffsetOut = 0; 5422 tnl_lso->UdpLenSetOut_to_TnlHdrLen = 5423 htobe16(F_CPL_TX_TNL_LSO_UDPCHKCLROUT | 5424 F_CPL_TX_TNL_LSO_UDPLENSETOUT | 5425 V_CPL_TX_TNL_LSO_TNLHDRLEN(m0->m_pkthdr.l2hlen + 5426 m0->m_pkthdr.l3hlen + m0->m_pkthdr.l4hlen + 5427 m0->m_pkthdr.l5hlen) | 5428 V_CPL_TX_TNL_LSO_TNLTYPE(TX_TNL_TYPE_VXLAN)); 5429 tnl_lso->r1 = 0; 5430 5431 /* Inner headers. */ 5432 ctrl = V_CPL_TX_TNL_LSO_ETHHDRLEN( 5433 (m0->m_pkthdr.inner_l2hlen - ETHER_HDR_LEN) >> 2) | 5434 V_CPL_TX_TNL_LSO_IPHDRLEN(m0->m_pkthdr.inner_l3hlen >> 2) | 5435 V_CPL_TX_TNL_LSO_TCPHDRLEN(m0->m_pkthdr.inner_l4hlen >> 2); 5436 if (m0->m_pkthdr.inner_l3hlen == sizeof(struct ip6_hdr)) 5437 ctrl |= F_CPL_TX_TNL_LSO_IPV6; 5438 tnl_lso->Flow_to_TcpHdrLen = htobe32(ctrl); 5439 tnl_lso->IpIdOffset = 0; 5440 tnl_lso->IpIdSplit_to_Mss = 5441 htobe16(V_CPL_TX_TNL_LSO_MSS(m0->m_pkthdr.tso_segsz)); 5442 tnl_lso->TCPSeqOffset = 0; 5443 tnl_lso->EthLenOffset_Size = 5444 htobe32(V_CPL_TX_TNL_LSO_SIZE(m0->m_pkthdr.len)); 5445 5446 return (tnl_lso + 1); 5447 } 5448 5449 #define VM_TX_L2HDR_LEN 16 /* ethmacdst to vlantci */ 5450 5451 /* 5452 * Write a VM txpkt WR for this packet to the hardware descriptors, update the 5453 * software descriptor, and advance the pidx. It is guaranteed that enough 5454 * descriptors are available. 5455 * 5456 * The return value is the # of hardware descriptors used. 5457 */ 5458 static u_int 5459 write_txpkt_vm_wr(struct adapter *sc, struct sge_txq *txq, struct mbuf *m0) 5460 { 5461 struct sge_eq *eq; 5462 struct fw_eth_tx_pkt_vm_wr *wr; 5463 struct tx_sdesc *txsd; 5464 struct cpl_tx_pkt_core *cpl; 5465 uint32_t ctrl; /* used in many unrelated places */ 5466 uint64_t ctrl1; 5467 int len16, ndesc, pktlen; 5468 caddr_t dst; 5469 5470 TXQ_LOCK_ASSERT_OWNED(txq); 5471 M_ASSERTPKTHDR(m0); 5472 5473 len16 = mbuf_len16(m0); 5474 pktlen = m0->m_pkthdr.len; 5475 ctrl = sizeof(struct cpl_tx_pkt_core); 5476 if (needs_tso(m0)) 5477 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 5478 ndesc = tx_len16_to_desc(len16); 5479 5480 /* Firmware work request header */ 5481 eq = &txq->eq; 5482 wr = (void *)&eq->desc[eq->pidx]; 5483 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_VM_WR) | 5484 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl)); 5485 5486 ctrl = V_FW_WR_LEN16(len16); 5487 wr->equiq_to_len16 = htobe32(ctrl); 5488 wr->r3[0] = 0; 5489 wr->r3[1] = 0; 5490 5491 /* 5492 * Copy over ethmacdst, ethmacsrc, ethtype, and vlantci. 5493 * vlantci is ignored unless the ethtype is 0x8100, so it's 5494 * simpler to always copy it rather than making it 5495 * conditional. Also, it seems that we do not have to set 5496 * vlantci or fake the ethtype when doing VLAN tag insertion. 5497 */ 5498 m_copydata(m0, 0, VM_TX_L2HDR_LEN, wr->ethmacdst); 5499 5500 if (needs_tso(m0)) { 5501 cpl = write_lso_cpl(wr + 1, m0); 5502 txq->tso_wrs++; 5503 } else 5504 cpl = (void *)(wr + 1); 5505 5506 /* Checksum offload */ 5507 ctrl1 = csum_to_ctrl(sc, m0); 5508 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS)) 5509 txq->txcsum++; /* some hardware assistance provided */ 5510 5511 /* VLAN tag insertion */ 5512 if (needs_vlan_insertion(m0)) { 5513 ctrl1 |= F_TXPKT_VLAN_VLD | 5514 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 5515 txq->vlan_insertion++; 5516 } 5517 5518 /* CPL header */ 5519 cpl->ctrl0 = txq->cpl_ctrl0; 5520 cpl->pack = 0; 5521 cpl->len = htobe16(pktlen); 5522 cpl->ctrl1 = htobe64(ctrl1); 5523 5524 /* SGL */ 5525 dst = (void *)(cpl + 1); 5526 5527 /* 5528 * A packet using TSO will use up an entire descriptor for the 5529 * firmware work request header, LSO CPL, and TX_PKT_XT CPL. 5530 * If this descriptor is the last descriptor in the ring, wrap 5531 * around to the front of the ring explicitly for the start of 5532 * the sgl. 5533 */ 5534 if (dst == (void *)&eq->desc[eq->sidx]) { 5535 dst = (void *)&eq->desc[0]; 5536 write_gl_to_txd(txq, m0, &dst, 0); 5537 } else 5538 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx); 5539 txq->sgl_wrs++; 5540 txq->txpkt_wrs++; 5541 5542 txsd = &txq->sdesc[eq->pidx]; 5543 txsd->m = m0; 5544 txsd->desc_used = ndesc; 5545 5546 return (ndesc); 5547 } 5548 5549 /* 5550 * Write a raw WR to the hardware descriptors, update the software 5551 * descriptor, and advance the pidx. It is guaranteed that enough 5552 * descriptors are available. 5553 * 5554 * The return value is the # of hardware descriptors used. 5555 */ 5556 static u_int 5557 write_raw_wr(struct sge_txq *txq, void *wr, struct mbuf *m0, u_int available) 5558 { 5559 struct sge_eq *eq = &txq->eq; 5560 struct tx_sdesc *txsd; 5561 struct mbuf *m; 5562 caddr_t dst; 5563 int len16, ndesc; 5564 5565 len16 = mbuf_len16(m0); 5566 ndesc = tx_len16_to_desc(len16); 5567 MPASS(ndesc <= available); 5568 5569 dst = wr; 5570 for (m = m0; m != NULL; m = m->m_next) 5571 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len); 5572 5573 txq->raw_wrs++; 5574 5575 txsd = &txq->sdesc[eq->pidx]; 5576 txsd->m = m0; 5577 txsd->desc_used = ndesc; 5578 5579 return (ndesc); 5580 } 5581 5582 /* 5583 * Write a txpkt WR for this packet to the hardware descriptors, update the 5584 * software descriptor, and advance the pidx. It is guaranteed that enough 5585 * descriptors are available. 5586 * 5587 * The return value is the # of hardware descriptors used. 5588 */ 5589 static u_int 5590 write_txpkt_wr(struct adapter *sc, struct sge_txq *txq, struct mbuf *m0, 5591 u_int available) 5592 { 5593 struct sge_eq *eq; 5594 struct fw_eth_tx_pkt_wr *wr; 5595 struct tx_sdesc *txsd; 5596 struct cpl_tx_pkt_core *cpl; 5597 uint32_t ctrl; /* used in many unrelated places */ 5598 uint64_t ctrl1; 5599 int len16, ndesc, pktlen, nsegs; 5600 caddr_t dst; 5601 5602 TXQ_LOCK_ASSERT_OWNED(txq); 5603 M_ASSERTPKTHDR(m0); 5604 5605 len16 = mbuf_len16(m0); 5606 nsegs = mbuf_nsegs(m0); 5607 pktlen = m0->m_pkthdr.len; 5608 ctrl = sizeof(struct cpl_tx_pkt_core); 5609 if (needs_tso(m0)) { 5610 if (needs_vxlan_tso(m0)) 5611 ctrl += sizeof(struct cpl_tx_tnl_lso); 5612 else 5613 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 5614 } else if (!(mbuf_cflags(m0) & MC_NOMAP) && pktlen <= imm_payload(2) && 5615 available >= 2) { 5616 /* Immediate data. Recalculate len16 and set nsegs to 0. */ 5617 ctrl += pktlen; 5618 len16 = howmany(sizeof(struct fw_eth_tx_pkt_wr) + 5619 sizeof(struct cpl_tx_pkt_core) + pktlen, 16); 5620 nsegs = 0; 5621 } 5622 ndesc = tx_len16_to_desc(len16); 5623 MPASS(ndesc <= available); 5624 5625 /* Firmware work request header */ 5626 eq = &txq->eq; 5627 wr = (void *)&eq->desc[eq->pidx]; 5628 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_WR) | 5629 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl)); 5630 5631 ctrl = V_FW_WR_LEN16(len16); 5632 wr->equiq_to_len16 = htobe32(ctrl); 5633 wr->r3 = 0; 5634 5635 if (needs_tso(m0)) { 5636 if (needs_vxlan_tso(m0)) { 5637 cpl = write_tnl_lso_cpl(wr + 1, m0); 5638 txq->vxlan_tso_wrs++; 5639 } else { 5640 cpl = write_lso_cpl(wr + 1, m0); 5641 txq->tso_wrs++; 5642 } 5643 } else 5644 cpl = (void *)(wr + 1); 5645 5646 /* Checksum offload */ 5647 ctrl1 = csum_to_ctrl(sc, m0); 5648 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS)) { 5649 /* some hardware assistance provided */ 5650 if (needs_vxlan_csum(m0)) 5651 txq->vxlan_txcsum++; 5652 else 5653 txq->txcsum++; 5654 } 5655 5656 /* VLAN tag insertion */ 5657 if (needs_vlan_insertion(m0)) { 5658 ctrl1 |= F_TXPKT_VLAN_VLD | 5659 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 5660 txq->vlan_insertion++; 5661 } 5662 5663 /* CPL header */ 5664 cpl->ctrl0 = txq->cpl_ctrl0; 5665 cpl->pack = 0; 5666 cpl->len = htobe16(pktlen); 5667 cpl->ctrl1 = htobe64(ctrl1); 5668 5669 /* SGL */ 5670 dst = (void *)(cpl + 1); 5671 if (__predict_false((uintptr_t)dst == (uintptr_t)&eq->desc[eq->sidx])) 5672 dst = (caddr_t)&eq->desc[0]; 5673 if (nsegs > 0) { 5674 5675 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx); 5676 txq->sgl_wrs++; 5677 } else { 5678 struct mbuf *m; 5679 5680 for (m = m0; m != NULL; m = m->m_next) { 5681 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len); 5682 #ifdef INVARIANTS 5683 pktlen -= m->m_len; 5684 #endif 5685 } 5686 #ifdef INVARIANTS 5687 KASSERT(pktlen == 0, ("%s: %d bytes left.", __func__, pktlen)); 5688 #endif 5689 txq->imm_wrs++; 5690 } 5691 5692 txq->txpkt_wrs++; 5693 5694 txsd = &txq->sdesc[eq->pidx]; 5695 txsd->m = m0; 5696 txsd->desc_used = ndesc; 5697 5698 return (ndesc); 5699 } 5700 5701 static inline bool 5702 cmp_l2hdr(struct txpkts *txp, struct mbuf *m) 5703 { 5704 int len; 5705 5706 MPASS(txp->npkt > 0); 5707 MPASS(m->m_len >= VM_TX_L2HDR_LEN); 5708 5709 if (txp->ethtype == be16toh(ETHERTYPE_VLAN)) 5710 len = VM_TX_L2HDR_LEN; 5711 else 5712 len = sizeof(struct ether_header); 5713 5714 return (memcmp(m->m_data, &txp->ethmacdst[0], len) != 0); 5715 } 5716 5717 static inline void 5718 save_l2hdr(struct txpkts *txp, struct mbuf *m) 5719 { 5720 MPASS(m->m_len >= VM_TX_L2HDR_LEN); 5721 5722 memcpy(&txp->ethmacdst[0], mtod(m, const void *), VM_TX_L2HDR_LEN); 5723 } 5724 5725 static int 5726 add_to_txpkts_vf(struct adapter *sc, struct sge_txq *txq, struct mbuf *m, 5727 int avail, bool *send) 5728 { 5729 struct txpkts *txp = &txq->txp; 5730 5731 /* Cannot have TSO and coalesce at the same time. */ 5732 if (cannot_use_txpkts(m)) { 5733 cannot_coalesce: 5734 *send = txp->npkt > 0; 5735 return (EINVAL); 5736 } 5737 5738 /* VF allows coalescing of type 1 (1 GL) only */ 5739 if (mbuf_nsegs(m) > 1) 5740 goto cannot_coalesce; 5741 5742 *send = false; 5743 if (txp->npkt > 0) { 5744 MPASS(tx_len16_to_desc(txp->len16) <= avail); 5745 MPASS(txp->npkt < txp->max_npkt); 5746 MPASS(txp->wr_type == 1); /* VF supports type 1 only */ 5747 5748 if (tx_len16_to_desc(txp->len16 + txpkts1_len16()) > avail) { 5749 retry_after_send: 5750 *send = true; 5751 return (EAGAIN); 5752 } 5753 if (m->m_pkthdr.len + txp->plen > 65535) 5754 goto retry_after_send; 5755 if (cmp_l2hdr(txp, m)) 5756 goto retry_after_send; 5757 5758 txp->len16 += txpkts1_len16(); 5759 txp->plen += m->m_pkthdr.len; 5760 txp->mb[txp->npkt++] = m; 5761 if (txp->npkt == txp->max_npkt) 5762 *send = true; 5763 } else { 5764 txp->len16 = howmany(sizeof(struct fw_eth_tx_pkts_vm_wr), 16) + 5765 txpkts1_len16(); 5766 if (tx_len16_to_desc(txp->len16) > avail) 5767 goto cannot_coalesce; 5768 txp->npkt = 1; 5769 txp->wr_type = 1; 5770 txp->plen = m->m_pkthdr.len; 5771 txp->mb[0] = m; 5772 save_l2hdr(txp, m); 5773 } 5774 return (0); 5775 } 5776 5777 static int 5778 add_to_txpkts_pf(struct adapter *sc, struct sge_txq *txq, struct mbuf *m, 5779 int avail, bool *send) 5780 { 5781 struct txpkts *txp = &txq->txp; 5782 int nsegs; 5783 5784 MPASS(!(sc->flags & IS_VF)); 5785 5786 /* Cannot have TSO and coalesce at the same time. */ 5787 if (cannot_use_txpkts(m)) { 5788 cannot_coalesce: 5789 *send = txp->npkt > 0; 5790 return (EINVAL); 5791 } 5792 5793 *send = false; 5794 nsegs = mbuf_nsegs(m); 5795 if (txp->npkt == 0) { 5796 if (m->m_pkthdr.len > 65535) 5797 goto cannot_coalesce; 5798 if (nsegs > 1) { 5799 txp->wr_type = 0; 5800 txp->len16 = 5801 howmany(sizeof(struct fw_eth_tx_pkts_wr), 16) + 5802 txpkts0_len16(nsegs); 5803 } else { 5804 txp->wr_type = 1; 5805 txp->len16 = 5806 howmany(sizeof(struct fw_eth_tx_pkts_wr), 16) + 5807 txpkts1_len16(); 5808 } 5809 if (tx_len16_to_desc(txp->len16) > avail) 5810 goto cannot_coalesce; 5811 txp->npkt = 1; 5812 txp->plen = m->m_pkthdr.len; 5813 txp->mb[0] = m; 5814 } else { 5815 MPASS(tx_len16_to_desc(txp->len16) <= avail); 5816 MPASS(txp->npkt < txp->max_npkt); 5817 5818 if (m->m_pkthdr.len + txp->plen > 65535) { 5819 retry_after_send: 5820 *send = true; 5821 return (EAGAIN); 5822 } 5823 5824 MPASS(txp->wr_type == 0 || txp->wr_type == 1); 5825 if (txp->wr_type == 0) { 5826 if (tx_len16_to_desc(txp->len16 + 5827 txpkts0_len16(nsegs)) > min(avail, SGE_MAX_WR_NDESC)) 5828 goto retry_after_send; 5829 txp->len16 += txpkts0_len16(nsegs); 5830 } else { 5831 if (nsegs != 1) 5832 goto retry_after_send; 5833 if (tx_len16_to_desc(txp->len16 + txpkts1_len16()) > 5834 avail) 5835 goto retry_after_send; 5836 txp->len16 += txpkts1_len16(); 5837 } 5838 5839 txp->plen += m->m_pkthdr.len; 5840 txp->mb[txp->npkt++] = m; 5841 if (txp->npkt == txp->max_npkt) 5842 *send = true; 5843 } 5844 return (0); 5845 } 5846 5847 /* 5848 * Write a txpkts WR for the packets in txp to the hardware descriptors, update 5849 * the software descriptor, and advance the pidx. It is guaranteed that enough 5850 * descriptors are available. 5851 * 5852 * The return value is the # of hardware descriptors used. 5853 */ 5854 static u_int 5855 write_txpkts_wr(struct adapter *sc, struct sge_txq *txq) 5856 { 5857 const struct txpkts *txp = &txq->txp; 5858 struct sge_eq *eq = &txq->eq; 5859 struct fw_eth_tx_pkts_wr *wr; 5860 struct tx_sdesc *txsd; 5861 struct cpl_tx_pkt_core *cpl; 5862 uint64_t ctrl1; 5863 int ndesc, i, checkwrap; 5864 struct mbuf *m, *last; 5865 void *flitp; 5866 5867 TXQ_LOCK_ASSERT_OWNED(txq); 5868 MPASS(txp->npkt > 0); 5869 MPASS(txp->len16 <= howmany(SGE_MAX_WR_LEN, 16)); 5870 5871 wr = (void *)&eq->desc[eq->pidx]; 5872 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR)); 5873 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(txp->len16)); 5874 wr->plen = htobe16(txp->plen); 5875 wr->npkt = txp->npkt; 5876 wr->r3 = 0; 5877 wr->type = txp->wr_type; 5878 flitp = wr + 1; 5879 5880 /* 5881 * At this point we are 16B into a hardware descriptor. If checkwrap is 5882 * set then we know the WR is going to wrap around somewhere. We'll 5883 * check for that at appropriate points. 5884 */ 5885 ndesc = tx_len16_to_desc(txp->len16); 5886 last = NULL; 5887 checkwrap = eq->sidx - ndesc < eq->pidx; 5888 for (i = 0; i < txp->npkt; i++) { 5889 m = txp->mb[i]; 5890 if (txp->wr_type == 0) { 5891 struct ulp_txpkt *ulpmc; 5892 struct ulptx_idata *ulpsc; 5893 5894 /* ULP master command */ 5895 ulpmc = flitp; 5896 ulpmc->cmd_dest = htobe32(V_ULPTX_CMD(ULP_TX_PKT) | 5897 V_ULP_TXPKT_DEST(0) | V_ULP_TXPKT_FID(eq->iqid)); 5898 ulpmc->len = htobe32(txpkts0_len16(mbuf_nsegs(m))); 5899 5900 /* ULP subcommand */ 5901 ulpsc = (void *)(ulpmc + 1); 5902 ulpsc->cmd_more = htobe32(V_ULPTX_CMD(ULP_TX_SC_IMM) | 5903 F_ULP_TX_SC_MORE); 5904 ulpsc->len = htobe32(sizeof(struct cpl_tx_pkt_core)); 5905 5906 cpl = (void *)(ulpsc + 1); 5907 if (checkwrap && 5908 (uintptr_t)cpl == (uintptr_t)&eq->desc[eq->sidx]) 5909 cpl = (void *)&eq->desc[0]; 5910 } else { 5911 cpl = flitp; 5912 } 5913 5914 /* Checksum offload */ 5915 ctrl1 = csum_to_ctrl(sc, m); 5916 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS)) { 5917 /* some hardware assistance provided */ 5918 if (needs_vxlan_csum(m)) 5919 txq->vxlan_txcsum++; 5920 else 5921 txq->txcsum++; 5922 } 5923 5924 /* VLAN tag insertion */ 5925 if (needs_vlan_insertion(m)) { 5926 ctrl1 |= F_TXPKT_VLAN_VLD | 5927 V_TXPKT_VLAN(m->m_pkthdr.ether_vtag); 5928 txq->vlan_insertion++; 5929 } 5930 5931 /* CPL header */ 5932 cpl->ctrl0 = txq->cpl_ctrl0; 5933 cpl->pack = 0; 5934 cpl->len = htobe16(m->m_pkthdr.len); 5935 cpl->ctrl1 = htobe64(ctrl1); 5936 5937 flitp = cpl + 1; 5938 if (checkwrap && 5939 (uintptr_t)flitp == (uintptr_t)&eq->desc[eq->sidx]) 5940 flitp = (void *)&eq->desc[0]; 5941 5942 write_gl_to_txd(txq, m, (caddr_t *)(&flitp), checkwrap); 5943 5944 if (last != NULL) 5945 last->m_nextpkt = m; 5946 last = m; 5947 } 5948 5949 txq->sgl_wrs++; 5950 if (txp->wr_type == 0) { 5951 txq->txpkts0_pkts += txp->npkt; 5952 txq->txpkts0_wrs++; 5953 } else { 5954 txq->txpkts1_pkts += txp->npkt; 5955 txq->txpkts1_wrs++; 5956 } 5957 5958 txsd = &txq->sdesc[eq->pidx]; 5959 txsd->m = txp->mb[0]; 5960 txsd->desc_used = ndesc; 5961 5962 return (ndesc); 5963 } 5964 5965 static u_int 5966 write_txpkts_vm_wr(struct adapter *sc, struct sge_txq *txq) 5967 { 5968 const struct txpkts *txp = &txq->txp; 5969 struct sge_eq *eq = &txq->eq; 5970 struct fw_eth_tx_pkts_vm_wr *wr; 5971 struct tx_sdesc *txsd; 5972 struct cpl_tx_pkt_core *cpl; 5973 uint64_t ctrl1; 5974 int ndesc, i; 5975 struct mbuf *m, *last; 5976 void *flitp; 5977 5978 TXQ_LOCK_ASSERT_OWNED(txq); 5979 MPASS(txp->npkt > 0); 5980 MPASS(txp->wr_type == 1); /* VF supports type 1 only */ 5981 MPASS(txp->mb[0] != NULL); 5982 MPASS(txp->len16 <= howmany(SGE_MAX_WR_LEN, 16)); 5983 5984 wr = (void *)&eq->desc[eq->pidx]; 5985 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_VM_WR)); 5986 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(txp->len16)); 5987 wr->r3 = 0; 5988 wr->plen = htobe16(txp->plen); 5989 wr->npkt = txp->npkt; 5990 wr->r4 = 0; 5991 memcpy(&wr->ethmacdst[0], &txp->ethmacdst[0], 16); 5992 flitp = wr + 1; 5993 5994 /* 5995 * At this point we are 32B into a hardware descriptor. Each mbuf in 5996 * the WR will take 32B so we check for the end of the descriptor ring 5997 * before writing odd mbufs (mb[1], 3, 5, ..) 5998 */ 5999 ndesc = tx_len16_to_desc(txp->len16); 6000 last = NULL; 6001 for (i = 0; i < txp->npkt; i++) { 6002 m = txp->mb[i]; 6003 if (i & 1 && (uintptr_t)flitp == (uintptr_t)&eq->desc[eq->sidx]) 6004 flitp = &eq->desc[0]; 6005 cpl = flitp; 6006 6007 /* Checksum offload */ 6008 ctrl1 = csum_to_ctrl(sc, m); 6009 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS)) 6010 txq->txcsum++; /* some hardware assistance provided */ 6011 6012 /* VLAN tag insertion */ 6013 if (needs_vlan_insertion(m)) { 6014 ctrl1 |= F_TXPKT_VLAN_VLD | 6015 V_TXPKT_VLAN(m->m_pkthdr.ether_vtag); 6016 txq->vlan_insertion++; 6017 } 6018 6019 /* CPL header */ 6020 cpl->ctrl0 = txq->cpl_ctrl0; 6021 cpl->pack = 0; 6022 cpl->len = htobe16(m->m_pkthdr.len); 6023 cpl->ctrl1 = htobe64(ctrl1); 6024 6025 flitp = cpl + 1; 6026 MPASS(mbuf_nsegs(m) == 1); 6027 write_gl_to_txd(txq, m, (caddr_t *)(&flitp), 0); 6028 6029 if (last != NULL) 6030 last->m_nextpkt = m; 6031 last = m; 6032 } 6033 6034 txq->sgl_wrs++; 6035 txq->txpkts1_pkts += txp->npkt; 6036 txq->txpkts1_wrs++; 6037 6038 txsd = &txq->sdesc[eq->pidx]; 6039 txsd->m = txp->mb[0]; 6040 txsd->desc_used = ndesc; 6041 6042 return (ndesc); 6043 } 6044 6045 /* 6046 * If the SGL ends on an address that is not 16 byte aligned, this function will 6047 * add a 0 filled flit at the end. 6048 */ 6049 static void 6050 write_gl_to_txd(struct sge_txq *txq, struct mbuf *m, caddr_t *to, int checkwrap) 6051 { 6052 struct sge_eq *eq = &txq->eq; 6053 struct sglist *gl = txq->gl; 6054 struct sglist_seg *seg; 6055 __be64 *flitp, *wrap; 6056 struct ulptx_sgl *usgl; 6057 int i, nflits, nsegs; 6058 6059 KASSERT(((uintptr_t)(*to) & 0xf) == 0, 6060 ("%s: SGL must start at a 16 byte boundary: %p", __func__, *to)); 6061 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]); 6062 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]); 6063 6064 get_pkt_gl(m, gl); 6065 nsegs = gl->sg_nseg; 6066 MPASS(nsegs > 0); 6067 6068 nflits = (3 * (nsegs - 1)) / 2 + ((nsegs - 1) & 1) + 2; 6069 flitp = (__be64 *)(*to); 6070 wrap = (__be64 *)(&eq->desc[eq->sidx]); 6071 seg = &gl->sg_segs[0]; 6072 usgl = (void *)flitp; 6073 6074 /* 6075 * We start at a 16 byte boundary somewhere inside the tx descriptor 6076 * ring, so we're at least 16 bytes away from the status page. There is 6077 * no chance of a wrap around in the middle of usgl (which is 16 bytes). 6078 */ 6079 6080 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 6081 V_ULPTX_NSGE(nsegs)); 6082 usgl->len0 = htobe32(seg->ss_len); 6083 usgl->addr0 = htobe64(seg->ss_paddr); 6084 seg++; 6085 6086 if (checkwrap == 0 || (uintptr_t)(flitp + nflits) <= (uintptr_t)wrap) { 6087 6088 /* Won't wrap around at all */ 6089 6090 for (i = 0; i < nsegs - 1; i++, seg++) { 6091 usgl->sge[i / 2].len[i & 1] = htobe32(seg->ss_len); 6092 usgl->sge[i / 2].addr[i & 1] = htobe64(seg->ss_paddr); 6093 } 6094 if (i & 1) 6095 usgl->sge[i / 2].len[1] = htobe32(0); 6096 flitp += nflits; 6097 } else { 6098 6099 /* Will wrap somewhere in the rest of the SGL */ 6100 6101 /* 2 flits already written, write the rest flit by flit */ 6102 flitp = (void *)(usgl + 1); 6103 for (i = 0; i < nflits - 2; i++) { 6104 if (flitp == wrap) 6105 flitp = (void *)eq->desc; 6106 *flitp++ = get_flit(seg, nsegs - 1, i); 6107 } 6108 } 6109 6110 if (nflits & 1) { 6111 MPASS(((uintptr_t)flitp) & 0xf); 6112 *flitp++ = 0; 6113 } 6114 6115 MPASS((((uintptr_t)flitp) & 0xf) == 0); 6116 if (__predict_false(flitp == wrap)) 6117 *to = (void *)eq->desc; 6118 else 6119 *to = (void *)flitp; 6120 } 6121 6122 static inline void 6123 copy_to_txd(struct sge_eq *eq, caddr_t from, caddr_t *to, int len) 6124 { 6125 6126 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]); 6127 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]); 6128 6129 if (__predict_true((uintptr_t)(*to) + len <= 6130 (uintptr_t)&eq->desc[eq->sidx])) { 6131 bcopy(from, *to, len); 6132 (*to) += len; 6133 } else { 6134 int portion = (uintptr_t)&eq->desc[eq->sidx] - (uintptr_t)(*to); 6135 6136 bcopy(from, *to, portion); 6137 from += portion; 6138 portion = len - portion; /* remaining */ 6139 bcopy(from, (void *)eq->desc, portion); 6140 (*to) = (caddr_t)eq->desc + portion; 6141 } 6142 } 6143 6144 static inline void 6145 ring_eq_db(struct adapter *sc, struct sge_eq *eq, u_int n) 6146 { 6147 u_int db; 6148 6149 MPASS(n > 0); 6150 6151 db = eq->doorbells; 6152 if (n > 1) 6153 clrbit(&db, DOORBELL_WCWR); 6154 wmb(); 6155 6156 switch (ffs(db) - 1) { 6157 case DOORBELL_UDB: 6158 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n)); 6159 break; 6160 6161 case DOORBELL_WCWR: { 6162 volatile uint64_t *dst, *src; 6163 int i; 6164 6165 /* 6166 * Queues whose 128B doorbell segment fits in the page do not 6167 * use relative qid (udb_qid is always 0). Only queues with 6168 * doorbell segments can do WCWR. 6169 */ 6170 KASSERT(eq->udb_qid == 0 && n == 1, 6171 ("%s: inappropriate doorbell (0x%x, %d, %d) for eq %p", 6172 __func__, eq->doorbells, n, eq->dbidx, eq)); 6173 6174 dst = (volatile void *)((uintptr_t)eq->udb + UDBS_WR_OFFSET - 6175 UDBS_DB_OFFSET); 6176 i = eq->dbidx; 6177 src = (void *)&eq->desc[i]; 6178 while (src != (void *)&eq->desc[i + 1]) 6179 *dst++ = *src++; 6180 wmb(); 6181 break; 6182 } 6183 6184 case DOORBELL_UDBWC: 6185 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n)); 6186 wmb(); 6187 break; 6188 6189 case DOORBELL_KDB: 6190 t4_write_reg(sc, sc->sge_kdoorbell_reg, 6191 V_QID(eq->cntxt_id) | V_PIDX(n)); 6192 break; 6193 } 6194 6195 IDXINCR(eq->dbidx, n, eq->sidx); 6196 } 6197 6198 static inline u_int 6199 reclaimable_tx_desc(struct sge_eq *eq) 6200 { 6201 uint16_t hw_cidx; 6202 6203 hw_cidx = read_hw_cidx(eq); 6204 return (IDXDIFF(hw_cidx, eq->cidx, eq->sidx)); 6205 } 6206 6207 static inline u_int 6208 total_available_tx_desc(struct sge_eq *eq) 6209 { 6210 uint16_t hw_cidx, pidx; 6211 6212 hw_cidx = read_hw_cidx(eq); 6213 pidx = eq->pidx; 6214 6215 if (pidx == hw_cidx) 6216 return (eq->sidx - 1); 6217 else 6218 return (IDXDIFF(hw_cidx, pidx, eq->sidx) - 1); 6219 } 6220 6221 static inline uint16_t 6222 read_hw_cidx(struct sge_eq *eq) 6223 { 6224 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx]; 6225 uint16_t cidx = spg->cidx; /* stable snapshot */ 6226 6227 return (be16toh(cidx)); 6228 } 6229 6230 /* 6231 * Reclaim 'n' descriptors approximately. 6232 */ 6233 static u_int 6234 reclaim_tx_descs(struct sge_txq *txq, u_int n) 6235 { 6236 struct tx_sdesc *txsd; 6237 struct sge_eq *eq = &txq->eq; 6238 u_int can_reclaim, reclaimed; 6239 6240 TXQ_LOCK_ASSERT_OWNED(txq); 6241 MPASS(n > 0); 6242 6243 reclaimed = 0; 6244 can_reclaim = reclaimable_tx_desc(eq); 6245 while (can_reclaim && reclaimed < n) { 6246 int ndesc; 6247 struct mbuf *m, *nextpkt; 6248 6249 txsd = &txq->sdesc[eq->cidx]; 6250 ndesc = txsd->desc_used; 6251 6252 /* Firmware doesn't return "partial" credits. */ 6253 KASSERT(can_reclaim >= ndesc, 6254 ("%s: unexpected number of credits: %d, %d", 6255 __func__, can_reclaim, ndesc)); 6256 KASSERT(ndesc != 0, 6257 ("%s: descriptor with no credits: cidx %d", 6258 __func__, eq->cidx)); 6259 6260 for (m = txsd->m; m != NULL; m = nextpkt) { 6261 nextpkt = m->m_nextpkt; 6262 m->m_nextpkt = NULL; 6263 m_freem(m); 6264 } 6265 reclaimed += ndesc; 6266 can_reclaim -= ndesc; 6267 IDXINCR(eq->cidx, ndesc, eq->sidx); 6268 } 6269 6270 return (reclaimed); 6271 } 6272 6273 static void 6274 tx_reclaim(void *arg, int n) 6275 { 6276 struct sge_txq *txq = arg; 6277 struct sge_eq *eq = &txq->eq; 6278 6279 do { 6280 if (TXQ_TRYLOCK(txq) == 0) 6281 break; 6282 n = reclaim_tx_descs(txq, 32); 6283 if (eq->cidx == eq->pidx) 6284 eq->equeqidx = eq->pidx; 6285 TXQ_UNLOCK(txq); 6286 } while (n > 0); 6287 } 6288 6289 static __be64 6290 get_flit(struct sglist_seg *segs, int nsegs, int idx) 6291 { 6292 int i = (idx / 3) * 2; 6293 6294 switch (idx % 3) { 6295 case 0: { 6296 uint64_t rc; 6297 6298 rc = (uint64_t)segs[i].ss_len << 32; 6299 if (i + 1 < nsegs) 6300 rc |= (uint64_t)(segs[i + 1].ss_len); 6301 6302 return (htobe64(rc)); 6303 } 6304 case 1: 6305 return (htobe64(segs[i].ss_paddr)); 6306 case 2: 6307 return (htobe64(segs[i + 1].ss_paddr)); 6308 } 6309 6310 return (0); 6311 } 6312 6313 static int 6314 find_refill_source(struct adapter *sc, int maxp, bool packing) 6315 { 6316 int i, zidx = -1; 6317 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[0]; 6318 6319 if (packing) { 6320 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) { 6321 if (rxb->hwidx2 == -1) 6322 continue; 6323 if (rxb->size1 < PAGE_SIZE && 6324 rxb->size1 < largest_rx_cluster) 6325 continue; 6326 if (rxb->size1 > largest_rx_cluster) 6327 break; 6328 MPASS(rxb->size1 - rxb->size2 >= CL_METADATA_SIZE); 6329 if (rxb->size2 >= maxp) 6330 return (i); 6331 zidx = i; 6332 } 6333 } else { 6334 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) { 6335 if (rxb->hwidx1 == -1) 6336 continue; 6337 if (rxb->size1 > largest_rx_cluster) 6338 break; 6339 if (rxb->size1 >= maxp) 6340 return (i); 6341 zidx = i; 6342 } 6343 } 6344 6345 return (zidx); 6346 } 6347 6348 static void 6349 add_fl_to_sfl(struct adapter *sc, struct sge_fl *fl) 6350 { 6351 mtx_lock(&sc->sfl_lock); 6352 FL_LOCK(fl); 6353 if ((fl->flags & FL_DOOMED) == 0) { 6354 fl->flags |= FL_STARVING; 6355 TAILQ_INSERT_TAIL(&sc->sfl, fl, link); 6356 callout_reset(&sc->sfl_callout, hz / 5, refill_sfl, sc); 6357 } 6358 FL_UNLOCK(fl); 6359 mtx_unlock(&sc->sfl_lock); 6360 } 6361 6362 static void 6363 handle_wrq_egr_update(struct adapter *sc, struct sge_eq *eq) 6364 { 6365 struct sge_wrq *wrq = (void *)eq; 6366 6367 atomic_readandclear_int(&eq->equiq); 6368 taskqueue_enqueue(sc->tq[eq->tx_chan], &wrq->wrq_tx_task); 6369 } 6370 6371 static void 6372 handle_eth_egr_update(struct adapter *sc, struct sge_eq *eq) 6373 { 6374 struct sge_txq *txq = (void *)eq; 6375 6376 MPASS(eq->type == EQ_ETH); 6377 6378 atomic_readandclear_int(&eq->equiq); 6379 if (mp_ring_is_idle(txq->r)) 6380 taskqueue_enqueue(sc->tq[eq->tx_chan], &txq->tx_reclaim_task); 6381 else 6382 mp_ring_check_drainage(txq->r, 64); 6383 } 6384 6385 static int 6386 handle_sge_egr_update(struct sge_iq *iq, const struct rss_header *rss, 6387 struct mbuf *m) 6388 { 6389 const struct cpl_sge_egr_update *cpl = (const void *)(rss + 1); 6390 unsigned int qid = G_EGR_QID(ntohl(cpl->opcode_qid)); 6391 struct adapter *sc = iq->adapter; 6392 struct sge *s = &sc->sge; 6393 struct sge_eq *eq; 6394 static void (*h[])(struct adapter *, struct sge_eq *) = {NULL, 6395 &handle_wrq_egr_update, &handle_eth_egr_update, 6396 &handle_wrq_egr_update}; 6397 6398 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 6399 rss->opcode)); 6400 6401 eq = s->eqmap[qid - s->eq_start - s->eq_base]; 6402 (*h[eq->type])(sc, eq); 6403 6404 return (0); 6405 } 6406 6407 /* handle_fw_msg works for both fw4_msg and fw6_msg because this is valid */ 6408 CTASSERT(offsetof(struct cpl_fw4_msg, data) == \ 6409 offsetof(struct cpl_fw6_msg, data)); 6410 6411 static int 6412 handle_fw_msg(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 6413 { 6414 struct adapter *sc = iq->adapter; 6415 const struct cpl_fw6_msg *cpl = (const void *)(rss + 1); 6416 6417 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 6418 rss->opcode)); 6419 6420 if (cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL) { 6421 const struct rss_header *rss2; 6422 6423 rss2 = (const struct rss_header *)&cpl->data[0]; 6424 return (t4_cpl_handler[rss2->opcode](iq, rss2, m)); 6425 } 6426 6427 return (t4_fw_msg_handler[cpl->type](sc, &cpl->data[0])); 6428 } 6429 6430 /** 6431 * t4_handle_wrerr_rpl - process a FW work request error message 6432 * @adap: the adapter 6433 * @rpl: start of the FW message 6434 */ 6435 static int 6436 t4_handle_wrerr_rpl(struct adapter *adap, const __be64 *rpl) 6437 { 6438 u8 opcode = *(const u8 *)rpl; 6439 const struct fw_error_cmd *e = (const void *)rpl; 6440 unsigned int i; 6441 6442 if (opcode != FW_ERROR_CMD) { 6443 log(LOG_ERR, 6444 "%s: Received WRERR_RPL message with opcode %#x\n", 6445 device_get_nameunit(adap->dev), opcode); 6446 return (EINVAL); 6447 } 6448 log(LOG_ERR, "%s: FW_ERROR (%s) ", device_get_nameunit(adap->dev), 6449 G_FW_ERROR_CMD_FATAL(be32toh(e->op_to_type)) ? "fatal" : 6450 "non-fatal"); 6451 switch (G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type))) { 6452 case FW_ERROR_TYPE_EXCEPTION: 6453 log(LOG_ERR, "exception info:\n"); 6454 for (i = 0; i < nitems(e->u.exception.info); i++) 6455 log(LOG_ERR, "%s%08x", i == 0 ? "\t" : " ", 6456 be32toh(e->u.exception.info[i])); 6457 log(LOG_ERR, "\n"); 6458 break; 6459 case FW_ERROR_TYPE_HWMODULE: 6460 log(LOG_ERR, "HW module regaddr %08x regval %08x\n", 6461 be32toh(e->u.hwmodule.regaddr), 6462 be32toh(e->u.hwmodule.regval)); 6463 break; 6464 case FW_ERROR_TYPE_WR: 6465 log(LOG_ERR, "WR cidx %d PF %d VF %d eqid %d hdr:\n", 6466 be16toh(e->u.wr.cidx), 6467 G_FW_ERROR_CMD_PFN(be16toh(e->u.wr.pfn_vfn)), 6468 G_FW_ERROR_CMD_VFN(be16toh(e->u.wr.pfn_vfn)), 6469 be32toh(e->u.wr.eqid)); 6470 for (i = 0; i < nitems(e->u.wr.wrhdr); i++) 6471 log(LOG_ERR, "%s%02x", i == 0 ? "\t" : " ", 6472 e->u.wr.wrhdr[i]); 6473 log(LOG_ERR, "\n"); 6474 break; 6475 case FW_ERROR_TYPE_ACL: 6476 log(LOG_ERR, "ACL cidx %d PF %d VF %d eqid %d %s", 6477 be16toh(e->u.acl.cidx), 6478 G_FW_ERROR_CMD_PFN(be16toh(e->u.acl.pfn_vfn)), 6479 G_FW_ERROR_CMD_VFN(be16toh(e->u.acl.pfn_vfn)), 6480 be32toh(e->u.acl.eqid), 6481 G_FW_ERROR_CMD_MV(be16toh(e->u.acl.mv_pkd)) ? "vlanid" : 6482 "MAC"); 6483 for (i = 0; i < nitems(e->u.acl.val); i++) 6484 log(LOG_ERR, " %02x", e->u.acl.val[i]); 6485 log(LOG_ERR, "\n"); 6486 break; 6487 default: 6488 log(LOG_ERR, "type %#x\n", 6489 G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type))); 6490 return (EINVAL); 6491 } 6492 return (0); 6493 } 6494 6495 static inline bool 6496 bufidx_used(struct adapter *sc, int idx) 6497 { 6498 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[0]; 6499 int i; 6500 6501 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) { 6502 if (rxb->size1 > largest_rx_cluster) 6503 continue; 6504 if (rxb->hwidx1 == idx || rxb->hwidx2 == idx) 6505 return (true); 6506 } 6507 6508 return (false); 6509 } 6510 6511 static int 6512 sysctl_bufsizes(SYSCTL_HANDLER_ARGS) 6513 { 6514 struct adapter *sc = arg1; 6515 struct sge_params *sp = &sc->params.sge; 6516 int i, rc; 6517 struct sbuf sb; 6518 char c; 6519 6520 sbuf_new(&sb, NULL, 128, SBUF_AUTOEXTEND); 6521 for (i = 0; i < SGE_FLBUF_SIZES; i++) { 6522 if (bufidx_used(sc, i)) 6523 c = '*'; 6524 else 6525 c = '\0'; 6526 6527 sbuf_printf(&sb, "%u%c ", sp->sge_fl_buffer_size[i], c); 6528 } 6529 sbuf_trim(&sb); 6530 sbuf_finish(&sb); 6531 rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req); 6532 sbuf_delete(&sb); 6533 return (rc); 6534 } 6535 6536 #ifdef RATELIMIT 6537 #if defined(INET) || defined(INET6) 6538 /* 6539 * len16 for a txpkt WR with a GL. Includes the firmware work request header. 6540 */ 6541 static inline u_int 6542 txpkt_eo_len16(u_int nsegs, u_int immhdrs, u_int tso) 6543 { 6544 u_int n; 6545 6546 MPASS(immhdrs > 0); 6547 6548 n = roundup2(sizeof(struct fw_eth_tx_eo_wr) + 6549 sizeof(struct cpl_tx_pkt_core) + immhdrs, 16); 6550 if (__predict_false(nsegs == 0)) 6551 goto done; 6552 6553 nsegs--; /* first segment is part of ulptx_sgl */ 6554 n += sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 6555 if (tso) 6556 n += sizeof(struct cpl_tx_pkt_lso_core); 6557 6558 done: 6559 return (howmany(n, 16)); 6560 } 6561 #endif 6562 6563 #define ETID_FLOWC_NPARAMS 6 6564 #define ETID_FLOWC_LEN (roundup2((sizeof(struct fw_flowc_wr) + \ 6565 ETID_FLOWC_NPARAMS * sizeof(struct fw_flowc_mnemval)), 16)) 6566 #define ETID_FLOWC_LEN16 (howmany(ETID_FLOWC_LEN, 16)) 6567 6568 static int 6569 send_etid_flowc_wr(struct cxgbe_rate_tag *cst, struct port_info *pi, 6570 struct vi_info *vi) 6571 { 6572 struct wrq_cookie cookie; 6573 u_int pfvf = pi->adapter->pf << S_FW_VIID_PFN; 6574 struct fw_flowc_wr *flowc; 6575 6576 mtx_assert(&cst->lock, MA_OWNED); 6577 MPASS((cst->flags & (EO_FLOWC_PENDING | EO_FLOWC_RPL_PENDING)) == 6578 EO_FLOWC_PENDING); 6579 6580 flowc = start_wrq_wr(&cst->eo_txq->wrq, ETID_FLOWC_LEN16, &cookie); 6581 if (__predict_false(flowc == NULL)) 6582 return (ENOMEM); 6583 6584 bzero(flowc, ETID_FLOWC_LEN); 6585 flowc->op_to_nparams = htobe32(V_FW_WR_OP(FW_FLOWC_WR) | 6586 V_FW_FLOWC_WR_NPARAMS(ETID_FLOWC_NPARAMS) | V_FW_WR_COMPL(0)); 6587 flowc->flowid_len16 = htonl(V_FW_WR_LEN16(ETID_FLOWC_LEN16) | 6588 V_FW_WR_FLOWID(cst->etid)); 6589 flowc->mnemval[0].mnemonic = FW_FLOWC_MNEM_PFNVFN; 6590 flowc->mnemval[0].val = htobe32(pfvf); 6591 flowc->mnemval[1].mnemonic = FW_FLOWC_MNEM_CH; 6592 flowc->mnemval[1].val = htobe32(pi->tx_chan); 6593 flowc->mnemval[2].mnemonic = FW_FLOWC_MNEM_PORT; 6594 flowc->mnemval[2].val = htobe32(pi->tx_chan); 6595 flowc->mnemval[3].mnemonic = FW_FLOWC_MNEM_IQID; 6596 flowc->mnemval[3].val = htobe32(cst->iqid); 6597 flowc->mnemval[4].mnemonic = FW_FLOWC_MNEM_EOSTATE; 6598 flowc->mnemval[4].val = htobe32(FW_FLOWC_MNEM_EOSTATE_ESTABLISHED); 6599 flowc->mnemval[5].mnemonic = FW_FLOWC_MNEM_SCHEDCLASS; 6600 flowc->mnemval[5].val = htobe32(cst->schedcl); 6601 6602 commit_wrq_wr(&cst->eo_txq->wrq, flowc, &cookie); 6603 6604 cst->flags &= ~EO_FLOWC_PENDING; 6605 cst->flags |= EO_FLOWC_RPL_PENDING; 6606 MPASS(cst->tx_credits >= ETID_FLOWC_LEN16); /* flowc is first WR. */ 6607 cst->tx_credits -= ETID_FLOWC_LEN16; 6608 6609 return (0); 6610 } 6611 6612 #define ETID_FLUSH_LEN16 (howmany(sizeof (struct fw_flowc_wr), 16)) 6613 6614 void 6615 send_etid_flush_wr(struct cxgbe_rate_tag *cst) 6616 { 6617 struct fw_flowc_wr *flowc; 6618 struct wrq_cookie cookie; 6619 6620 mtx_assert(&cst->lock, MA_OWNED); 6621 6622 flowc = start_wrq_wr(&cst->eo_txq->wrq, ETID_FLUSH_LEN16, &cookie); 6623 if (__predict_false(flowc == NULL)) 6624 CXGBE_UNIMPLEMENTED(__func__); 6625 6626 bzero(flowc, ETID_FLUSH_LEN16 * 16); 6627 flowc->op_to_nparams = htobe32(V_FW_WR_OP(FW_FLOWC_WR) | 6628 V_FW_FLOWC_WR_NPARAMS(0) | F_FW_WR_COMPL); 6629 flowc->flowid_len16 = htobe32(V_FW_WR_LEN16(ETID_FLUSH_LEN16) | 6630 V_FW_WR_FLOWID(cst->etid)); 6631 6632 commit_wrq_wr(&cst->eo_txq->wrq, flowc, &cookie); 6633 6634 cst->flags |= EO_FLUSH_RPL_PENDING; 6635 MPASS(cst->tx_credits >= ETID_FLUSH_LEN16); 6636 cst->tx_credits -= ETID_FLUSH_LEN16; 6637 cst->ncompl++; 6638 } 6639 6640 static void 6641 write_ethofld_wr(struct cxgbe_rate_tag *cst, struct fw_eth_tx_eo_wr *wr, 6642 struct mbuf *m0, int compl) 6643 { 6644 struct cpl_tx_pkt_core *cpl; 6645 uint64_t ctrl1; 6646 uint32_t ctrl; /* used in many unrelated places */ 6647 int len16, pktlen, nsegs, immhdrs; 6648 uintptr_t p; 6649 struct ulptx_sgl *usgl; 6650 struct sglist sg; 6651 struct sglist_seg segs[38]; /* XXX: find real limit. XXX: get off the stack */ 6652 6653 mtx_assert(&cst->lock, MA_OWNED); 6654 M_ASSERTPKTHDR(m0); 6655 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 6656 m0->m_pkthdr.l4hlen > 0, 6657 ("%s: ethofld mbuf %p is missing header lengths", __func__, m0)); 6658 6659 len16 = mbuf_eo_len16(m0); 6660 nsegs = mbuf_eo_nsegs(m0); 6661 pktlen = m0->m_pkthdr.len; 6662 ctrl = sizeof(struct cpl_tx_pkt_core); 6663 if (needs_tso(m0)) 6664 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 6665 immhdrs = m0->m_pkthdr.l2hlen + m0->m_pkthdr.l3hlen + m0->m_pkthdr.l4hlen; 6666 ctrl += immhdrs; 6667 6668 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_EO_WR) | 6669 V_FW_ETH_TX_EO_WR_IMMDLEN(ctrl) | V_FW_WR_COMPL(!!compl)); 6670 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(len16) | 6671 V_FW_WR_FLOWID(cst->etid)); 6672 wr->r3 = 0; 6673 if (needs_outer_udp_csum(m0)) { 6674 wr->u.udpseg.type = FW_ETH_TX_EO_TYPE_UDPSEG; 6675 wr->u.udpseg.ethlen = m0->m_pkthdr.l2hlen; 6676 wr->u.udpseg.iplen = htobe16(m0->m_pkthdr.l3hlen); 6677 wr->u.udpseg.udplen = m0->m_pkthdr.l4hlen; 6678 wr->u.udpseg.rtplen = 0; 6679 wr->u.udpseg.r4 = 0; 6680 wr->u.udpseg.mss = htobe16(pktlen - immhdrs); 6681 wr->u.udpseg.schedpktsize = wr->u.udpseg.mss; 6682 wr->u.udpseg.plen = htobe32(pktlen - immhdrs); 6683 cpl = (void *)(wr + 1); 6684 } else { 6685 MPASS(needs_outer_tcp_csum(m0)); 6686 wr->u.tcpseg.type = FW_ETH_TX_EO_TYPE_TCPSEG; 6687 wr->u.tcpseg.ethlen = m0->m_pkthdr.l2hlen; 6688 wr->u.tcpseg.iplen = htobe16(m0->m_pkthdr.l3hlen); 6689 wr->u.tcpseg.tcplen = m0->m_pkthdr.l4hlen; 6690 wr->u.tcpseg.tsclk_tsoff = mbuf_eo_tsclk_tsoff(m0); 6691 wr->u.tcpseg.r4 = 0; 6692 wr->u.tcpseg.r5 = 0; 6693 wr->u.tcpseg.plen = htobe32(pktlen - immhdrs); 6694 6695 if (needs_tso(m0)) { 6696 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1); 6697 6698 wr->u.tcpseg.mss = htobe16(m0->m_pkthdr.tso_segsz); 6699 6700 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | 6701 F_LSO_FIRST_SLICE | F_LSO_LAST_SLICE | 6702 V_LSO_ETHHDR_LEN((m0->m_pkthdr.l2hlen - 6703 ETHER_HDR_LEN) >> 2) | 6704 V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) | 6705 V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2); 6706 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 6707 ctrl |= F_LSO_IPV6; 6708 lso->lso_ctrl = htobe32(ctrl); 6709 lso->ipid_ofst = htobe16(0); 6710 lso->mss = htobe16(m0->m_pkthdr.tso_segsz); 6711 lso->seqno_offset = htobe32(0); 6712 lso->len = htobe32(pktlen); 6713 6714 cpl = (void *)(lso + 1); 6715 } else { 6716 wr->u.tcpseg.mss = htobe16(0xffff); 6717 cpl = (void *)(wr + 1); 6718 } 6719 } 6720 6721 /* Checksum offload must be requested for ethofld. */ 6722 MPASS(needs_outer_l4_csum(m0)); 6723 ctrl1 = csum_to_ctrl(cst->adapter, m0); 6724 6725 /* VLAN tag insertion */ 6726 if (needs_vlan_insertion(m0)) { 6727 ctrl1 |= F_TXPKT_VLAN_VLD | 6728 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 6729 } 6730 6731 /* CPL header */ 6732 cpl->ctrl0 = cst->ctrl0; 6733 cpl->pack = 0; 6734 cpl->len = htobe16(pktlen); 6735 cpl->ctrl1 = htobe64(ctrl1); 6736 6737 /* Copy Ethernet, IP & TCP/UDP hdrs as immediate data */ 6738 p = (uintptr_t)(cpl + 1); 6739 m_copydata(m0, 0, immhdrs, (void *)p); 6740 6741 /* SGL */ 6742 if (nsegs > 0) { 6743 int i, pad; 6744 6745 /* zero-pad upto next 16Byte boundary, if not 16Byte aligned */ 6746 p += immhdrs; 6747 pad = 16 - (immhdrs & 0xf); 6748 bzero((void *)p, pad); 6749 6750 usgl = (void *)(p + pad); 6751 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 6752 V_ULPTX_NSGE(nsegs)); 6753 6754 sglist_init(&sg, nitems(segs), segs); 6755 for (; m0 != NULL; m0 = m0->m_next) { 6756 if (__predict_false(m0->m_len == 0)) 6757 continue; 6758 if (immhdrs >= m0->m_len) { 6759 immhdrs -= m0->m_len; 6760 continue; 6761 } 6762 if (m0->m_flags & M_EXTPG) 6763 sglist_append_mbuf_epg(&sg, m0, 6764 mtod(m0, vm_offset_t), m0->m_len); 6765 else 6766 sglist_append(&sg, mtod(m0, char *) + immhdrs, 6767 m0->m_len - immhdrs); 6768 immhdrs = 0; 6769 } 6770 MPASS(sg.sg_nseg == nsegs); 6771 6772 /* 6773 * Zero pad last 8B in case the WR doesn't end on a 16B 6774 * boundary. 6775 */ 6776 *(uint64_t *)((char *)wr + len16 * 16 - 8) = 0; 6777 6778 usgl->len0 = htobe32(segs[0].ss_len); 6779 usgl->addr0 = htobe64(segs[0].ss_paddr); 6780 for (i = 0; i < nsegs - 1; i++) { 6781 usgl->sge[i / 2].len[i & 1] = htobe32(segs[i + 1].ss_len); 6782 usgl->sge[i / 2].addr[i & 1] = htobe64(segs[i + 1].ss_paddr); 6783 } 6784 if (i & 1) 6785 usgl->sge[i / 2].len[1] = htobe32(0); 6786 } 6787 6788 } 6789 6790 static void 6791 ethofld_tx(struct cxgbe_rate_tag *cst) 6792 { 6793 struct mbuf *m; 6794 struct wrq_cookie cookie; 6795 int next_credits, compl; 6796 struct fw_eth_tx_eo_wr *wr; 6797 6798 mtx_assert(&cst->lock, MA_OWNED); 6799 6800 while ((m = mbufq_first(&cst->pending_tx)) != NULL) { 6801 M_ASSERTPKTHDR(m); 6802 6803 /* How many len16 credits do we need to send this mbuf. */ 6804 next_credits = mbuf_eo_len16(m); 6805 MPASS(next_credits > 0); 6806 if (next_credits > cst->tx_credits) { 6807 /* 6808 * Tx will make progress eventually because there is at 6809 * least one outstanding fw4_ack that will return 6810 * credits and kick the tx. 6811 */ 6812 MPASS(cst->ncompl > 0); 6813 return; 6814 } 6815 wr = start_wrq_wr(&cst->eo_txq->wrq, next_credits, &cookie); 6816 if (__predict_false(wr == NULL)) { 6817 /* XXX: wishful thinking, not a real assertion. */ 6818 MPASS(cst->ncompl > 0); 6819 return; 6820 } 6821 cst->tx_credits -= next_credits; 6822 cst->tx_nocompl += next_credits; 6823 compl = cst->ncompl == 0 || cst->tx_nocompl >= cst->tx_total / 2; 6824 ETHER_BPF_MTAP(cst->com.ifp, m); 6825 write_ethofld_wr(cst, wr, m, compl); 6826 commit_wrq_wr(&cst->eo_txq->wrq, wr, &cookie); 6827 if (compl) { 6828 cst->ncompl++; 6829 cst->tx_nocompl = 0; 6830 } 6831 (void) mbufq_dequeue(&cst->pending_tx); 6832 6833 /* 6834 * Drop the mbuf's reference on the tag now rather 6835 * than waiting until m_freem(). This ensures that 6836 * cxgbe_rate_tag_free gets called when the inp drops 6837 * its reference on the tag and there are no more 6838 * mbufs in the pending_tx queue and can flush any 6839 * pending requests. Otherwise if the last mbuf 6840 * doesn't request a completion the etid will never be 6841 * released. 6842 */ 6843 m->m_pkthdr.snd_tag = NULL; 6844 m->m_pkthdr.csum_flags &= ~CSUM_SND_TAG; 6845 m_snd_tag_rele(&cst->com); 6846 6847 mbufq_enqueue(&cst->pending_fwack, m); 6848 } 6849 } 6850 6851 int 6852 ethofld_transmit(struct ifnet *ifp, struct mbuf *m0) 6853 { 6854 struct cxgbe_rate_tag *cst; 6855 int rc; 6856 6857 MPASS(m0->m_nextpkt == NULL); 6858 MPASS(m0->m_pkthdr.csum_flags & CSUM_SND_TAG); 6859 MPASS(m0->m_pkthdr.snd_tag != NULL); 6860 cst = mst_to_crt(m0->m_pkthdr.snd_tag); 6861 6862 mtx_lock(&cst->lock); 6863 MPASS(cst->flags & EO_SND_TAG_REF); 6864 6865 if (__predict_false(cst->flags & EO_FLOWC_PENDING)) { 6866 struct vi_info *vi = ifp->if_softc; 6867 struct port_info *pi = vi->pi; 6868 struct adapter *sc = pi->adapter; 6869 const uint32_t rss_mask = vi->rss_size - 1; 6870 uint32_t rss_hash; 6871 6872 cst->eo_txq = &sc->sge.ofld_txq[vi->first_ofld_txq]; 6873 if (M_HASHTYPE_ISHASH(m0)) 6874 rss_hash = m0->m_pkthdr.flowid; 6875 else 6876 rss_hash = arc4random(); 6877 /* We assume RSS hashing */ 6878 cst->iqid = vi->rss[rss_hash & rss_mask]; 6879 cst->eo_txq += rss_hash % vi->nofldtxq; 6880 rc = send_etid_flowc_wr(cst, pi, vi); 6881 if (rc != 0) 6882 goto done; 6883 } 6884 6885 if (__predict_false(cst->plen + m0->m_pkthdr.len > eo_max_backlog)) { 6886 rc = ENOBUFS; 6887 goto done; 6888 } 6889 6890 mbufq_enqueue(&cst->pending_tx, m0); 6891 cst->plen += m0->m_pkthdr.len; 6892 6893 /* 6894 * Hold an extra reference on the tag while generating work 6895 * requests to ensure that we don't try to free the tag during 6896 * ethofld_tx() in case we are sending the final mbuf after 6897 * the inp was freed. 6898 */ 6899 m_snd_tag_ref(&cst->com); 6900 ethofld_tx(cst); 6901 mtx_unlock(&cst->lock); 6902 m_snd_tag_rele(&cst->com); 6903 return (0); 6904 6905 done: 6906 mtx_unlock(&cst->lock); 6907 if (__predict_false(rc != 0)) 6908 m_freem(m0); 6909 return (rc); 6910 } 6911 6912 static int 6913 ethofld_fw4_ack(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0) 6914 { 6915 struct adapter *sc = iq->adapter; 6916 const struct cpl_fw4_ack *cpl = (const void *)(rss + 1); 6917 struct mbuf *m; 6918 u_int etid = G_CPL_FW4_ACK_FLOWID(be32toh(OPCODE_TID(cpl))); 6919 struct cxgbe_rate_tag *cst; 6920 uint8_t credits = cpl->credits; 6921 6922 cst = lookup_etid(sc, etid); 6923 mtx_lock(&cst->lock); 6924 if (__predict_false(cst->flags & EO_FLOWC_RPL_PENDING)) { 6925 MPASS(credits >= ETID_FLOWC_LEN16); 6926 credits -= ETID_FLOWC_LEN16; 6927 cst->flags &= ~EO_FLOWC_RPL_PENDING; 6928 } 6929 6930 KASSERT(cst->ncompl > 0, 6931 ("%s: etid %u (%p) wasn't expecting completion.", 6932 __func__, etid, cst)); 6933 cst->ncompl--; 6934 6935 while (credits > 0) { 6936 m = mbufq_dequeue(&cst->pending_fwack); 6937 if (__predict_false(m == NULL)) { 6938 /* 6939 * The remaining credits are for the final flush that 6940 * was issued when the tag was freed by the kernel. 6941 */ 6942 MPASS((cst->flags & 6943 (EO_FLUSH_RPL_PENDING | EO_SND_TAG_REF)) == 6944 EO_FLUSH_RPL_PENDING); 6945 MPASS(credits == ETID_FLUSH_LEN16); 6946 MPASS(cst->tx_credits + cpl->credits == cst->tx_total); 6947 MPASS(cst->ncompl == 0); 6948 6949 cst->flags &= ~EO_FLUSH_RPL_PENDING; 6950 cst->tx_credits += cpl->credits; 6951 cxgbe_rate_tag_free_locked(cst); 6952 return (0); /* cst is gone. */ 6953 } 6954 KASSERT(m != NULL, 6955 ("%s: too many credits (%u, %u)", __func__, cpl->credits, 6956 credits)); 6957 KASSERT(credits >= mbuf_eo_len16(m), 6958 ("%s: too few credits (%u, %u, %u)", __func__, 6959 cpl->credits, credits, mbuf_eo_len16(m))); 6960 credits -= mbuf_eo_len16(m); 6961 cst->plen -= m->m_pkthdr.len; 6962 m_freem(m); 6963 } 6964 6965 cst->tx_credits += cpl->credits; 6966 MPASS(cst->tx_credits <= cst->tx_total); 6967 6968 if (cst->flags & EO_SND_TAG_REF) { 6969 /* 6970 * As with ethofld_transmit(), hold an extra reference 6971 * so that the tag is stable across ethold_tx(). 6972 */ 6973 m_snd_tag_ref(&cst->com); 6974 m = mbufq_first(&cst->pending_tx); 6975 if (m != NULL && cst->tx_credits >= mbuf_eo_len16(m)) 6976 ethofld_tx(cst); 6977 mtx_unlock(&cst->lock); 6978 m_snd_tag_rele(&cst->com); 6979 } else { 6980 /* 6981 * There shouldn't be any pending packets if the tag 6982 * was freed by the kernel since any pending packet 6983 * should hold a reference to the tag. 6984 */ 6985 MPASS(mbufq_first(&cst->pending_tx) == NULL); 6986 mtx_unlock(&cst->lock); 6987 } 6988 6989 return (0); 6990 } 6991 #endif 6992