1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 Chelsio Communications, Inc. 5 * All rights reserved. 6 * Written by: Navdeep Parhar <np@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include "opt_inet.h" 34 #include "opt_inet6.h" 35 #include "opt_ratelimit.h" 36 37 #include <sys/types.h> 38 #include <sys/eventhandler.h> 39 #include <sys/mbuf.h> 40 #include <sys/socket.h> 41 #include <sys/kernel.h> 42 #include <sys/malloc.h> 43 #include <sys/queue.h> 44 #include <sys/sbuf.h> 45 #include <sys/taskqueue.h> 46 #include <sys/time.h> 47 #include <sys/sglist.h> 48 #include <sys/sysctl.h> 49 #include <sys/smp.h> 50 #include <sys/counter.h> 51 #include <net/bpf.h> 52 #include <net/ethernet.h> 53 #include <net/if.h> 54 #include <net/if_vlan_var.h> 55 #include <netinet/in.h> 56 #include <netinet/ip.h> 57 #include <netinet/ip6.h> 58 #include <netinet/tcp.h> 59 #include <netinet/udp.h> 60 #include <machine/in_cksum.h> 61 #include <machine/md_var.h> 62 #include <vm/vm.h> 63 #include <vm/pmap.h> 64 #ifdef DEV_NETMAP 65 #include <machine/bus.h> 66 #include <sys/selinfo.h> 67 #include <net/if_var.h> 68 #include <net/netmap.h> 69 #include <dev/netmap/netmap_kern.h> 70 #endif 71 72 #include "common/common.h" 73 #include "common/t4_regs.h" 74 #include "common/t4_regs_values.h" 75 #include "common/t4_msg.h" 76 #include "t4_l2t.h" 77 #include "t4_mp_ring.h" 78 79 #ifdef T4_PKT_TIMESTAMP 80 #define RX_COPY_THRESHOLD (MINCLSIZE - 8) 81 #else 82 #define RX_COPY_THRESHOLD MINCLSIZE 83 #endif 84 85 /* Internal mbuf flags stored in PH_loc.eight[1]. */ 86 #define MC_RAW_WR 0x02 87 88 /* 89 * Ethernet frames are DMA'd at this byte offset into the freelist buffer. 90 * 0-7 are valid values. 91 */ 92 static int fl_pktshift = 0; 93 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pktshift, CTLFLAG_RDTUN, &fl_pktshift, 0, 94 "payload DMA offset in rx buffer (bytes)"); 95 96 /* 97 * Pad ethernet payload up to this boundary. 98 * -1: driver should figure out a good value. 99 * 0: disable padding. 100 * Any power of 2 from 32 to 4096 (both inclusive) is also a valid value. 101 */ 102 int fl_pad = -1; 103 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pad, CTLFLAG_RDTUN, &fl_pad, 0, 104 "payload pad boundary (bytes)"); 105 106 /* 107 * Status page length. 108 * -1: driver should figure out a good value. 109 * 64 or 128 are the only other valid values. 110 */ 111 static int spg_len = -1; 112 SYSCTL_INT(_hw_cxgbe, OID_AUTO, spg_len, CTLFLAG_RDTUN, &spg_len, 0, 113 "status page size (bytes)"); 114 115 /* 116 * Congestion drops. 117 * -1: no congestion feedback (not recommended). 118 * 0: backpressure the channel instead of dropping packets right away. 119 * 1: no backpressure, drop packets for the congested queue immediately. 120 */ 121 static int cong_drop = 0; 122 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cong_drop, CTLFLAG_RDTUN, &cong_drop, 0, 123 "Congestion control for RX queues (0 = backpressure, 1 = drop"); 124 125 /* 126 * Deliver multiple frames in the same free list buffer if they fit. 127 * -1: let the driver decide whether to enable buffer packing or not. 128 * 0: disable buffer packing. 129 * 1: enable buffer packing. 130 */ 131 static int buffer_packing = -1; 132 SYSCTL_INT(_hw_cxgbe, OID_AUTO, buffer_packing, CTLFLAG_RDTUN, &buffer_packing, 133 0, "Enable buffer packing"); 134 135 /* 136 * Start next frame in a packed buffer at this boundary. 137 * -1: driver should figure out a good value. 138 * T4: driver will ignore this and use the same value as fl_pad above. 139 * T5: 16, or a power of 2 from 64 to 4096 (both inclusive) is a valid value. 140 */ 141 static int fl_pack = -1; 142 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pack, CTLFLAG_RDTUN, &fl_pack, 0, 143 "payload pack boundary (bytes)"); 144 145 /* 146 * Allow the driver to create mbuf(s) in a cluster allocated for rx. 147 * 0: never; always allocate mbufs from the zone_mbuf UMA zone. 148 * 1: ok to create mbuf(s) within a cluster if there is room. 149 */ 150 static int allow_mbufs_in_cluster = 1; 151 SYSCTL_INT(_hw_cxgbe, OID_AUTO, allow_mbufs_in_cluster, CTLFLAG_RDTUN, 152 &allow_mbufs_in_cluster, 0, 153 "Allow driver to create mbufs within a rx cluster"); 154 155 /* 156 * Largest rx cluster size that the driver is allowed to allocate. 157 */ 158 static int largest_rx_cluster = MJUM16BYTES; 159 SYSCTL_INT(_hw_cxgbe, OID_AUTO, largest_rx_cluster, CTLFLAG_RDTUN, 160 &largest_rx_cluster, 0, "Largest rx cluster (bytes)"); 161 162 /* 163 * Size of cluster allocation that's most likely to succeed. The driver will 164 * fall back to this size if it fails to allocate clusters larger than this. 165 */ 166 static int safest_rx_cluster = PAGE_SIZE; 167 SYSCTL_INT(_hw_cxgbe, OID_AUTO, safest_rx_cluster, CTLFLAG_RDTUN, 168 &safest_rx_cluster, 0, "Safe rx cluster (bytes)"); 169 170 #ifdef RATELIMIT 171 /* 172 * Knob to control TCP timestamp rewriting, and the granularity of the tick used 173 * for rewriting. -1 and 0-3 are all valid values. 174 * -1: hardware should leave the TCP timestamps alone. 175 * 0: 1ms 176 * 1: 100us 177 * 2: 10us 178 * 3: 1us 179 */ 180 static int tsclk = -1; 181 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tsclk, CTLFLAG_RDTUN, &tsclk, 0, 182 "Control TCP timestamp rewriting when using pacing"); 183 184 static int eo_max_backlog = 1024 * 1024; 185 SYSCTL_INT(_hw_cxgbe, OID_AUTO, eo_max_backlog, CTLFLAG_RDTUN, &eo_max_backlog, 186 0, "Maximum backlog of ratelimited data per flow"); 187 #endif 188 189 /* 190 * The interrupt holdoff timers are multiplied by this value on T6+. 191 * 1 and 3-17 (both inclusive) are legal values. 192 */ 193 static int tscale = 1; 194 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tscale, CTLFLAG_RDTUN, &tscale, 0, 195 "Interrupt holdoff timer scale on T6+"); 196 197 /* 198 * Number of LRO entries in the lro_ctrl structure per rx queue. 199 */ 200 static int lro_entries = TCP_LRO_ENTRIES; 201 SYSCTL_INT(_hw_cxgbe, OID_AUTO, lro_entries, CTLFLAG_RDTUN, &lro_entries, 0, 202 "Number of LRO entries per RX queue"); 203 204 /* 205 * This enables presorting of frames before they're fed into tcp_lro_rx. 206 */ 207 static int lro_mbufs = 0; 208 SYSCTL_INT(_hw_cxgbe, OID_AUTO, lro_mbufs, CTLFLAG_RDTUN, &lro_mbufs, 0, 209 "Enable presorting of LRO frames"); 210 211 struct txpkts { 212 u_int wr_type; /* type 0 or type 1 */ 213 u_int npkt; /* # of packets in this work request */ 214 u_int plen; /* total payload (sum of all packets) */ 215 u_int len16; /* # of 16B pieces used by this work request */ 216 }; 217 218 /* A packet's SGL. This + m_pkthdr has all info needed for tx */ 219 struct sgl { 220 struct sglist sg; 221 struct sglist_seg seg[TX_SGL_SEGS]; 222 }; 223 224 static int service_iq(struct sge_iq *, int); 225 static int service_iq_fl(struct sge_iq *, int); 226 static struct mbuf *get_fl_payload(struct adapter *, struct sge_fl *, uint32_t); 227 static int t4_eth_rx(struct sge_iq *, const struct rss_header *, struct mbuf *); 228 static inline void init_iq(struct sge_iq *, struct adapter *, int, int, int); 229 static inline void init_fl(struct adapter *, struct sge_fl *, int, int, char *); 230 static inline void init_eq(struct adapter *, struct sge_eq *, int, int, uint8_t, 231 uint16_t, char *); 232 static int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *, 233 bus_addr_t *, void **); 234 static int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 235 void *); 236 static int alloc_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *, 237 int, int); 238 static int free_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *); 239 static void add_iq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *, 240 struct sge_iq *); 241 static void add_fl_sysctls(struct adapter *, struct sysctl_ctx_list *, 242 struct sysctl_oid *, struct sge_fl *); 243 static int alloc_fwq(struct adapter *); 244 static int free_fwq(struct adapter *); 245 static int alloc_ctrlq(struct adapter *, struct sge_wrq *, int, 246 struct sysctl_oid *); 247 static int alloc_rxq(struct vi_info *, struct sge_rxq *, int, int, 248 struct sysctl_oid *); 249 static int free_rxq(struct vi_info *, struct sge_rxq *); 250 #ifdef TCP_OFFLOAD 251 static int alloc_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *, int, int, 252 struct sysctl_oid *); 253 static int free_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *); 254 #endif 255 #ifdef DEV_NETMAP 256 static int alloc_nm_rxq(struct vi_info *, struct sge_nm_rxq *, int, int, 257 struct sysctl_oid *); 258 static int free_nm_rxq(struct vi_info *, struct sge_nm_rxq *); 259 static int alloc_nm_txq(struct vi_info *, struct sge_nm_txq *, int, int, 260 struct sysctl_oid *); 261 static int free_nm_txq(struct vi_info *, struct sge_nm_txq *); 262 #endif 263 static int ctrl_eq_alloc(struct adapter *, struct sge_eq *); 264 static int eth_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *); 265 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 266 static int ofld_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *); 267 #endif 268 static int alloc_eq(struct adapter *, struct vi_info *, struct sge_eq *); 269 static int free_eq(struct adapter *, struct sge_eq *); 270 static int alloc_wrq(struct adapter *, struct vi_info *, struct sge_wrq *, 271 struct sysctl_oid *); 272 static int free_wrq(struct adapter *, struct sge_wrq *); 273 static int alloc_txq(struct vi_info *, struct sge_txq *, int, 274 struct sysctl_oid *); 275 static int free_txq(struct vi_info *, struct sge_txq *); 276 static void oneseg_dma_callback(void *, bus_dma_segment_t *, int, int); 277 static inline void ring_fl_db(struct adapter *, struct sge_fl *); 278 static int refill_fl(struct adapter *, struct sge_fl *, int); 279 static void refill_sfl(void *); 280 static int alloc_fl_sdesc(struct sge_fl *); 281 static void free_fl_sdesc(struct adapter *, struct sge_fl *); 282 static void find_best_refill_source(struct adapter *, struct sge_fl *, int); 283 static void find_safe_refill_source(struct adapter *, struct sge_fl *); 284 static void add_fl_to_sfl(struct adapter *, struct sge_fl *); 285 286 static inline void get_pkt_gl(struct mbuf *, struct sglist *); 287 static inline u_int txpkt_len16(u_int, u_int); 288 static inline u_int txpkt_vm_len16(u_int, u_int); 289 static inline u_int txpkts0_len16(u_int); 290 static inline u_int txpkts1_len16(void); 291 static u_int write_raw_wr(struct sge_txq *, void *, struct mbuf *, u_int); 292 static u_int write_txpkt_wr(struct sge_txq *, struct fw_eth_tx_pkt_wr *, 293 struct mbuf *, u_int); 294 static u_int write_txpkt_vm_wr(struct adapter *, struct sge_txq *, 295 struct fw_eth_tx_pkt_vm_wr *, struct mbuf *, u_int); 296 static int try_txpkts(struct mbuf *, struct mbuf *, struct txpkts *, u_int); 297 static int add_to_txpkts(struct mbuf *, struct txpkts *, u_int); 298 static u_int write_txpkts_wr(struct sge_txq *, struct fw_eth_tx_pkts_wr *, 299 struct mbuf *, const struct txpkts *, u_int); 300 static void write_gl_to_txd(struct sge_txq *, struct mbuf *, caddr_t *, int); 301 static inline void copy_to_txd(struct sge_eq *, caddr_t, caddr_t *, int); 302 static inline void ring_eq_db(struct adapter *, struct sge_eq *, u_int); 303 static inline uint16_t read_hw_cidx(struct sge_eq *); 304 static inline u_int reclaimable_tx_desc(struct sge_eq *); 305 static inline u_int total_available_tx_desc(struct sge_eq *); 306 static u_int reclaim_tx_descs(struct sge_txq *, u_int); 307 static void tx_reclaim(void *, int); 308 static __be64 get_flit(struct sglist_seg *, int, int); 309 static int handle_sge_egr_update(struct sge_iq *, const struct rss_header *, 310 struct mbuf *); 311 static int handle_fw_msg(struct sge_iq *, const struct rss_header *, 312 struct mbuf *); 313 static int t4_handle_wrerr_rpl(struct adapter *, const __be64 *); 314 static void wrq_tx_drain(void *, int); 315 static void drain_wrq_wr_list(struct adapter *, struct sge_wrq *); 316 317 static int sysctl_uint16(SYSCTL_HANDLER_ARGS); 318 static int sysctl_bufsizes(SYSCTL_HANDLER_ARGS); 319 #ifdef RATELIMIT 320 static inline u_int txpkt_eo_len16(u_int, u_int, u_int); 321 static int ethofld_fw4_ack(struct sge_iq *, const struct rss_header *, 322 struct mbuf *); 323 #endif 324 325 static counter_u64_t extfree_refs; 326 static counter_u64_t extfree_rels; 327 328 an_handler_t t4_an_handler; 329 fw_msg_handler_t t4_fw_msg_handler[NUM_FW6_TYPES]; 330 cpl_handler_t t4_cpl_handler[NUM_CPL_CMDS]; 331 cpl_handler_t set_tcb_rpl_handlers[NUM_CPL_COOKIES]; 332 cpl_handler_t l2t_write_rpl_handlers[NUM_CPL_COOKIES]; 333 cpl_handler_t act_open_rpl_handlers[NUM_CPL_COOKIES]; 334 cpl_handler_t abort_rpl_rss_handlers[NUM_CPL_COOKIES]; 335 cpl_handler_t fw4_ack_handlers[NUM_CPL_COOKIES]; 336 337 void 338 t4_register_an_handler(an_handler_t h) 339 { 340 uintptr_t *loc; 341 342 MPASS(h == NULL || t4_an_handler == NULL); 343 344 loc = (uintptr_t *)&t4_an_handler; 345 atomic_store_rel_ptr(loc, (uintptr_t)h); 346 } 347 348 void 349 t4_register_fw_msg_handler(int type, fw_msg_handler_t h) 350 { 351 uintptr_t *loc; 352 353 MPASS(type < nitems(t4_fw_msg_handler)); 354 MPASS(h == NULL || t4_fw_msg_handler[type] == NULL); 355 /* 356 * These are dispatched by the handler for FW{4|6}_CPL_MSG using the CPL 357 * handler dispatch table. Reject any attempt to install a handler for 358 * this subtype. 359 */ 360 MPASS(type != FW_TYPE_RSSCPL); 361 MPASS(type != FW6_TYPE_RSSCPL); 362 363 loc = (uintptr_t *)&t4_fw_msg_handler[type]; 364 atomic_store_rel_ptr(loc, (uintptr_t)h); 365 } 366 367 void 368 t4_register_cpl_handler(int opcode, cpl_handler_t h) 369 { 370 uintptr_t *loc; 371 372 MPASS(opcode < nitems(t4_cpl_handler)); 373 MPASS(h == NULL || t4_cpl_handler[opcode] == NULL); 374 375 loc = (uintptr_t *)&t4_cpl_handler[opcode]; 376 atomic_store_rel_ptr(loc, (uintptr_t)h); 377 } 378 379 static int 380 set_tcb_rpl_handler(struct sge_iq *iq, const struct rss_header *rss, 381 struct mbuf *m) 382 { 383 const struct cpl_set_tcb_rpl *cpl = (const void *)(rss + 1); 384 u_int tid; 385 int cookie; 386 387 MPASS(m == NULL); 388 389 tid = GET_TID(cpl); 390 if (is_hpftid(iq->adapter, tid) || is_ftid(iq->adapter, tid)) { 391 /* 392 * The return code for filter-write is put in the CPL cookie so 393 * we have to rely on the hardware tid (is_ftid) to determine 394 * that this is a response to a filter. 395 */ 396 cookie = CPL_COOKIE_FILTER; 397 } else { 398 cookie = G_COOKIE(cpl->cookie); 399 } 400 MPASS(cookie > CPL_COOKIE_RESERVED); 401 MPASS(cookie < nitems(set_tcb_rpl_handlers)); 402 403 return (set_tcb_rpl_handlers[cookie](iq, rss, m)); 404 } 405 406 static int 407 l2t_write_rpl_handler(struct sge_iq *iq, const struct rss_header *rss, 408 struct mbuf *m) 409 { 410 const struct cpl_l2t_write_rpl *rpl = (const void *)(rss + 1); 411 unsigned int cookie; 412 413 MPASS(m == NULL); 414 415 cookie = GET_TID(rpl) & F_SYNC_WR ? CPL_COOKIE_TOM : CPL_COOKIE_FILTER; 416 return (l2t_write_rpl_handlers[cookie](iq, rss, m)); 417 } 418 419 static int 420 act_open_rpl_handler(struct sge_iq *iq, const struct rss_header *rss, 421 struct mbuf *m) 422 { 423 const struct cpl_act_open_rpl *cpl = (const void *)(rss + 1); 424 u_int cookie = G_TID_COOKIE(G_AOPEN_ATID(be32toh(cpl->atid_status))); 425 426 MPASS(m == NULL); 427 MPASS(cookie != CPL_COOKIE_RESERVED); 428 429 return (act_open_rpl_handlers[cookie](iq, rss, m)); 430 } 431 432 static int 433 abort_rpl_rss_handler(struct sge_iq *iq, const struct rss_header *rss, 434 struct mbuf *m) 435 { 436 struct adapter *sc = iq->adapter; 437 u_int cookie; 438 439 MPASS(m == NULL); 440 if (is_hashfilter(sc)) 441 cookie = CPL_COOKIE_HASHFILTER; 442 else 443 cookie = CPL_COOKIE_TOM; 444 445 return (abort_rpl_rss_handlers[cookie](iq, rss, m)); 446 } 447 448 static int 449 fw4_ack_handler(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 450 { 451 struct adapter *sc = iq->adapter; 452 const struct cpl_fw4_ack *cpl = (const void *)(rss + 1); 453 unsigned int tid = G_CPL_FW4_ACK_FLOWID(be32toh(OPCODE_TID(cpl))); 454 u_int cookie; 455 456 MPASS(m == NULL); 457 if (is_etid(sc, tid)) 458 cookie = CPL_COOKIE_ETHOFLD; 459 else 460 cookie = CPL_COOKIE_TOM; 461 462 return (fw4_ack_handlers[cookie](iq, rss, m)); 463 } 464 465 static void 466 t4_init_shared_cpl_handlers(void) 467 { 468 469 t4_register_cpl_handler(CPL_SET_TCB_RPL, set_tcb_rpl_handler); 470 t4_register_cpl_handler(CPL_L2T_WRITE_RPL, l2t_write_rpl_handler); 471 t4_register_cpl_handler(CPL_ACT_OPEN_RPL, act_open_rpl_handler); 472 t4_register_cpl_handler(CPL_ABORT_RPL_RSS, abort_rpl_rss_handler); 473 t4_register_cpl_handler(CPL_FW4_ACK, fw4_ack_handler); 474 } 475 476 void 477 t4_register_shared_cpl_handler(int opcode, cpl_handler_t h, int cookie) 478 { 479 uintptr_t *loc; 480 481 MPASS(opcode < nitems(t4_cpl_handler)); 482 MPASS(cookie > CPL_COOKIE_RESERVED); 483 MPASS(cookie < NUM_CPL_COOKIES); 484 MPASS(t4_cpl_handler[opcode] != NULL); 485 486 switch (opcode) { 487 case CPL_SET_TCB_RPL: 488 loc = (uintptr_t *)&set_tcb_rpl_handlers[cookie]; 489 break; 490 case CPL_L2T_WRITE_RPL: 491 loc = (uintptr_t *)&l2t_write_rpl_handlers[cookie]; 492 break; 493 case CPL_ACT_OPEN_RPL: 494 loc = (uintptr_t *)&act_open_rpl_handlers[cookie]; 495 break; 496 case CPL_ABORT_RPL_RSS: 497 loc = (uintptr_t *)&abort_rpl_rss_handlers[cookie]; 498 break; 499 case CPL_FW4_ACK: 500 loc = (uintptr_t *)&fw4_ack_handlers[cookie]; 501 break; 502 default: 503 MPASS(0); 504 return; 505 } 506 MPASS(h == NULL || *loc == (uintptr_t)NULL); 507 atomic_store_rel_ptr(loc, (uintptr_t)h); 508 } 509 510 /* 511 * Called on MOD_LOAD. Validates and calculates the SGE tunables. 512 */ 513 void 514 t4_sge_modload(void) 515 { 516 517 if (fl_pktshift < 0 || fl_pktshift > 7) { 518 printf("Invalid hw.cxgbe.fl_pktshift value (%d)," 519 " using 0 instead.\n", fl_pktshift); 520 fl_pktshift = 0; 521 } 522 523 if (spg_len != 64 && spg_len != 128) { 524 int len; 525 526 #if defined(__i386__) || defined(__amd64__) 527 len = cpu_clflush_line_size > 64 ? 128 : 64; 528 #else 529 len = 64; 530 #endif 531 if (spg_len != -1) { 532 printf("Invalid hw.cxgbe.spg_len value (%d)," 533 " using %d instead.\n", spg_len, len); 534 } 535 spg_len = len; 536 } 537 538 if (cong_drop < -1 || cong_drop > 1) { 539 printf("Invalid hw.cxgbe.cong_drop value (%d)," 540 " using 0 instead.\n", cong_drop); 541 cong_drop = 0; 542 } 543 544 if (tscale != 1 && (tscale < 3 || tscale > 17)) { 545 printf("Invalid hw.cxgbe.tscale value (%d)," 546 " using 1 instead.\n", tscale); 547 tscale = 1; 548 } 549 550 extfree_refs = counter_u64_alloc(M_WAITOK); 551 extfree_rels = counter_u64_alloc(M_WAITOK); 552 counter_u64_zero(extfree_refs); 553 counter_u64_zero(extfree_rels); 554 555 t4_init_shared_cpl_handlers(); 556 t4_register_cpl_handler(CPL_FW4_MSG, handle_fw_msg); 557 t4_register_cpl_handler(CPL_FW6_MSG, handle_fw_msg); 558 t4_register_cpl_handler(CPL_SGE_EGR_UPDATE, handle_sge_egr_update); 559 t4_register_cpl_handler(CPL_RX_PKT, t4_eth_rx); 560 #ifdef RATELIMIT 561 t4_register_shared_cpl_handler(CPL_FW4_ACK, ethofld_fw4_ack, 562 CPL_COOKIE_ETHOFLD); 563 #endif 564 t4_register_fw_msg_handler(FW6_TYPE_CMD_RPL, t4_handle_fw_rpl); 565 t4_register_fw_msg_handler(FW6_TYPE_WRERR_RPL, t4_handle_wrerr_rpl); 566 } 567 568 void 569 t4_sge_modunload(void) 570 { 571 572 counter_u64_free(extfree_refs); 573 counter_u64_free(extfree_rels); 574 } 575 576 uint64_t 577 t4_sge_extfree_refs(void) 578 { 579 uint64_t refs, rels; 580 581 rels = counter_u64_fetch(extfree_rels); 582 refs = counter_u64_fetch(extfree_refs); 583 584 return (refs - rels); 585 } 586 587 static inline void 588 setup_pad_and_pack_boundaries(struct adapter *sc) 589 { 590 uint32_t v, m; 591 int pad, pack, pad_shift; 592 593 pad_shift = chip_id(sc) > CHELSIO_T5 ? X_T6_INGPADBOUNDARY_SHIFT : 594 X_INGPADBOUNDARY_SHIFT; 595 pad = fl_pad; 596 if (fl_pad < (1 << pad_shift) || 597 fl_pad > (1 << (pad_shift + M_INGPADBOUNDARY)) || 598 !powerof2(fl_pad)) { 599 /* 600 * If there is any chance that we might use buffer packing and 601 * the chip is a T4, then pick 64 as the pad/pack boundary. Set 602 * it to the minimum allowed in all other cases. 603 */ 604 pad = is_t4(sc) && buffer_packing ? 64 : 1 << pad_shift; 605 606 /* 607 * For fl_pad = 0 we'll still write a reasonable value to the 608 * register but all the freelists will opt out of padding. 609 * We'll complain here only if the user tried to set it to a 610 * value greater than 0 that was invalid. 611 */ 612 if (fl_pad > 0) { 613 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pad value" 614 " (%d), using %d instead.\n", fl_pad, pad); 615 } 616 } 617 m = V_INGPADBOUNDARY(M_INGPADBOUNDARY); 618 v = V_INGPADBOUNDARY(ilog2(pad) - pad_shift); 619 t4_set_reg_field(sc, A_SGE_CONTROL, m, v); 620 621 if (is_t4(sc)) { 622 if (fl_pack != -1 && fl_pack != pad) { 623 /* Complain but carry on. */ 624 device_printf(sc->dev, "hw.cxgbe.fl_pack (%d) ignored," 625 " using %d instead.\n", fl_pack, pad); 626 } 627 return; 628 } 629 630 pack = fl_pack; 631 if (fl_pack < 16 || fl_pack == 32 || fl_pack > 4096 || 632 !powerof2(fl_pack)) { 633 pack = max(sc->params.pci.mps, CACHE_LINE_SIZE); 634 MPASS(powerof2(pack)); 635 if (pack < 16) 636 pack = 16; 637 if (pack == 32) 638 pack = 64; 639 if (pack > 4096) 640 pack = 4096; 641 if (fl_pack != -1) { 642 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pack value" 643 " (%d), using %d instead.\n", fl_pack, pack); 644 } 645 } 646 m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY); 647 if (pack == 16) 648 v = V_INGPACKBOUNDARY(0); 649 else 650 v = V_INGPACKBOUNDARY(ilog2(pack) - 5); 651 652 MPASS(!is_t4(sc)); /* T4 doesn't have SGE_CONTROL2 */ 653 t4_set_reg_field(sc, A_SGE_CONTROL2, m, v); 654 } 655 656 /* 657 * adap->params.vpd.cclk must be set up before this is called. 658 */ 659 void 660 t4_tweak_chip_settings(struct adapter *sc) 661 { 662 int i; 663 uint32_t v, m; 664 int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200}; 665 int timer_max = M_TIMERVALUE0 * 1000 / sc->params.vpd.cclk; 666 int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */ 667 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 668 static int sge_flbuf_sizes[] = { 669 MCLBYTES, 670 #if MJUMPAGESIZE != MCLBYTES 671 MJUMPAGESIZE, 672 MJUMPAGESIZE - CL_METADATA_SIZE, 673 MJUMPAGESIZE - 2 * MSIZE - CL_METADATA_SIZE, 674 #endif 675 MJUM9BYTES, 676 MJUM16BYTES, 677 MCLBYTES - MSIZE - CL_METADATA_SIZE, 678 MJUM9BYTES - CL_METADATA_SIZE, 679 MJUM16BYTES - CL_METADATA_SIZE, 680 }; 681 682 KASSERT(sc->flags & MASTER_PF, 683 ("%s: trying to change chip settings when not master.", __func__)); 684 685 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE; 686 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE | 687 V_EGRSTATUSPAGESIZE(spg_len == 128); 688 t4_set_reg_field(sc, A_SGE_CONTROL, m, v); 689 690 setup_pad_and_pack_boundaries(sc); 691 692 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) | 693 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) | 694 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) | 695 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) | 696 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) | 697 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) | 698 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) | 699 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10); 700 t4_write_reg(sc, A_SGE_HOST_PAGE_SIZE, v); 701 702 KASSERT(nitems(sge_flbuf_sizes) <= SGE_FLBUF_SIZES, 703 ("%s: hw buffer size table too big", __func__)); 704 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0, 4096); 705 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE1, 65536); 706 for (i = 0; i < min(nitems(sge_flbuf_sizes), SGE_FLBUF_SIZES); i++) { 707 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE15 - (4 * i), 708 sge_flbuf_sizes[i]); 709 } 710 711 v = V_THRESHOLD_0(intr_pktcount[0]) | V_THRESHOLD_1(intr_pktcount[1]) | 712 V_THRESHOLD_2(intr_pktcount[2]) | V_THRESHOLD_3(intr_pktcount[3]); 713 t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD, v); 714 715 KASSERT(intr_timer[0] <= timer_max, 716 ("%s: not a single usable timer (%d, %d)", __func__, intr_timer[0], 717 timer_max)); 718 for (i = 1; i < nitems(intr_timer); i++) { 719 KASSERT(intr_timer[i] >= intr_timer[i - 1], 720 ("%s: timers not listed in increasing order (%d)", 721 __func__, i)); 722 723 while (intr_timer[i] > timer_max) { 724 if (i == nitems(intr_timer) - 1) { 725 intr_timer[i] = timer_max; 726 break; 727 } 728 intr_timer[i] += intr_timer[i - 1]; 729 intr_timer[i] /= 2; 730 } 731 } 732 733 v = V_TIMERVALUE0(us_to_core_ticks(sc, intr_timer[0])) | 734 V_TIMERVALUE1(us_to_core_ticks(sc, intr_timer[1])); 735 t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1, v); 736 v = V_TIMERVALUE2(us_to_core_ticks(sc, intr_timer[2])) | 737 V_TIMERVALUE3(us_to_core_ticks(sc, intr_timer[3])); 738 t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3, v); 739 v = V_TIMERVALUE4(us_to_core_ticks(sc, intr_timer[4])) | 740 V_TIMERVALUE5(us_to_core_ticks(sc, intr_timer[5])); 741 t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5, v); 742 743 if (chip_id(sc) >= CHELSIO_T6) { 744 m = V_TSCALE(M_TSCALE); 745 if (tscale == 1) 746 v = 0; 747 else 748 v = V_TSCALE(tscale - 2); 749 t4_set_reg_field(sc, A_SGE_ITP_CONTROL, m, v); 750 751 if (sc->debug_flags & DF_DISABLE_TCB_CACHE) { 752 m = V_RDTHRESHOLD(M_RDTHRESHOLD) | F_WRTHRTHRESHEN | 753 V_WRTHRTHRESH(M_WRTHRTHRESH); 754 t4_tp_pio_read(sc, &v, 1, A_TP_CMM_CONFIG, 1); 755 v &= ~m; 756 v |= V_RDTHRESHOLD(1) | F_WRTHRTHRESHEN | 757 V_WRTHRTHRESH(16); 758 t4_tp_pio_write(sc, &v, 1, A_TP_CMM_CONFIG, 1); 759 } 760 } 761 762 /* 4K, 16K, 64K, 256K DDP "page sizes" for TDDP */ 763 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 764 t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, v); 765 766 /* 767 * 4K, 8K, 16K, 64K DDP "page sizes" for iSCSI DDP. These have been 768 * chosen with MAXPHYS = 128K in mind. The largest DDP buffer that we 769 * may have to deal with is MAXPHYS + 1 page. 770 */ 771 v = V_HPZ0(0) | V_HPZ1(1) | V_HPZ2(2) | V_HPZ3(4); 772 t4_write_reg(sc, A_ULP_RX_ISCSI_PSZ, v); 773 774 /* We use multiple DDP page sizes both in plain-TOE and ISCSI modes. */ 775 m = v = F_TDDPTAGTCB | F_ISCSITAGTCB; 776 t4_set_reg_field(sc, A_ULP_RX_CTL, m, v); 777 778 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 779 F_RESETDDPOFFSET; 780 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 781 t4_set_reg_field(sc, A_TP_PARA_REG5, m, v); 782 } 783 784 /* 785 * SGE wants the buffer to be at least 64B and then a multiple of 16. If 786 * padding is in use, the buffer's start and end need to be aligned to the pad 787 * boundary as well. We'll just make sure that the size is a multiple of the 788 * boundary here, it is up to the buffer allocation code to make sure the start 789 * of the buffer is aligned as well. 790 */ 791 static inline int 792 hwsz_ok(struct adapter *sc, int hwsz) 793 { 794 int mask = fl_pad ? sc->params.sge.pad_boundary - 1 : 16 - 1; 795 796 return (hwsz >= 64 && (hwsz & mask) == 0); 797 } 798 799 /* 800 * XXX: driver really should be able to deal with unexpected settings. 801 */ 802 int 803 t4_read_chip_settings(struct adapter *sc) 804 { 805 struct sge *s = &sc->sge; 806 struct sge_params *sp = &sc->params.sge; 807 int i, j, n, rc = 0; 808 uint32_t m, v, r; 809 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 810 static int sw_buf_sizes[] = { /* Sorted by size */ 811 MCLBYTES, 812 #if MJUMPAGESIZE != MCLBYTES 813 MJUMPAGESIZE, 814 #endif 815 MJUM9BYTES, 816 MJUM16BYTES 817 }; 818 struct sw_zone_info *swz, *safe_swz; 819 struct hw_buf_info *hwb; 820 821 m = F_RXPKTCPLMODE; 822 v = F_RXPKTCPLMODE; 823 r = sc->params.sge.sge_control; 824 if ((r & m) != v) { 825 device_printf(sc->dev, "invalid SGE_CONTROL(0x%x)\n", r); 826 rc = EINVAL; 827 } 828 829 /* 830 * If this changes then every single use of PAGE_SHIFT in the driver 831 * needs to be carefully reviewed for PAGE_SHIFT vs sp->page_shift. 832 */ 833 if (sp->page_shift != PAGE_SHIFT) { 834 device_printf(sc->dev, "invalid SGE_HOST_PAGE_SIZE(0x%x)\n", r); 835 rc = EINVAL; 836 } 837 838 /* Filter out unusable hw buffer sizes entirely (mark with -2). */ 839 hwb = &s->hw_buf_info[0]; 840 for (i = 0; i < nitems(s->hw_buf_info); i++, hwb++) { 841 r = sc->params.sge.sge_fl_buffer_size[i]; 842 hwb->size = r; 843 hwb->zidx = hwsz_ok(sc, r) ? -1 : -2; 844 hwb->next = -1; 845 } 846 847 /* 848 * Create a sorted list in decreasing order of hw buffer sizes (and so 849 * increasing order of spare area) for each software zone. 850 * 851 * If padding is enabled then the start and end of the buffer must align 852 * to the pad boundary; if packing is enabled then they must align with 853 * the pack boundary as well. Allocations from the cluster zones are 854 * aligned to min(size, 4K), so the buffer starts at that alignment and 855 * ends at hwb->size alignment. If mbuf inlining is allowed the 856 * starting alignment will be reduced to MSIZE and the driver will 857 * exercise appropriate caution when deciding on the best buffer layout 858 * to use. 859 */ 860 n = 0; /* no usable buffer size to begin with */ 861 swz = &s->sw_zone_info[0]; 862 safe_swz = NULL; 863 for (i = 0; i < SW_ZONE_SIZES; i++, swz++) { 864 int8_t head = -1, tail = -1; 865 866 swz->size = sw_buf_sizes[i]; 867 swz->zone = m_getzone(swz->size); 868 swz->type = m_gettype(swz->size); 869 870 if (swz->size < PAGE_SIZE) { 871 MPASS(powerof2(swz->size)); 872 if (fl_pad && (swz->size % sp->pad_boundary != 0)) 873 continue; 874 } 875 876 if (swz->size == safest_rx_cluster) 877 safe_swz = swz; 878 879 hwb = &s->hw_buf_info[0]; 880 for (j = 0; j < SGE_FLBUF_SIZES; j++, hwb++) { 881 if (hwb->zidx != -1 || hwb->size > swz->size) 882 continue; 883 #ifdef INVARIANTS 884 if (fl_pad) 885 MPASS(hwb->size % sp->pad_boundary == 0); 886 #endif 887 hwb->zidx = i; 888 if (head == -1) 889 head = tail = j; 890 else if (hwb->size < s->hw_buf_info[tail].size) { 891 s->hw_buf_info[tail].next = j; 892 tail = j; 893 } else { 894 int8_t *cur; 895 struct hw_buf_info *t; 896 897 for (cur = &head; *cur != -1; cur = &t->next) { 898 t = &s->hw_buf_info[*cur]; 899 if (hwb->size == t->size) { 900 hwb->zidx = -2; 901 break; 902 } 903 if (hwb->size > t->size) { 904 hwb->next = *cur; 905 *cur = j; 906 break; 907 } 908 } 909 } 910 } 911 swz->head_hwidx = head; 912 swz->tail_hwidx = tail; 913 914 if (tail != -1) { 915 n++; 916 if (swz->size - s->hw_buf_info[tail].size >= 917 CL_METADATA_SIZE) 918 sc->flags |= BUF_PACKING_OK; 919 } 920 } 921 if (n == 0) { 922 device_printf(sc->dev, "no usable SGE FL buffer size.\n"); 923 rc = EINVAL; 924 } 925 926 s->safe_hwidx1 = -1; 927 s->safe_hwidx2 = -1; 928 if (safe_swz != NULL) { 929 s->safe_hwidx1 = safe_swz->head_hwidx; 930 for (i = safe_swz->head_hwidx; i != -1; i = hwb->next) { 931 int spare; 932 933 hwb = &s->hw_buf_info[i]; 934 #ifdef INVARIANTS 935 if (fl_pad) 936 MPASS(hwb->size % sp->pad_boundary == 0); 937 #endif 938 spare = safe_swz->size - hwb->size; 939 if (spare >= CL_METADATA_SIZE) { 940 s->safe_hwidx2 = i; 941 break; 942 } 943 } 944 } 945 946 if (sc->flags & IS_VF) 947 return (0); 948 949 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 950 r = t4_read_reg(sc, A_ULP_RX_TDDP_PSZ); 951 if (r != v) { 952 device_printf(sc->dev, "invalid ULP_RX_TDDP_PSZ(0x%x)\n", r); 953 rc = EINVAL; 954 } 955 956 m = v = F_TDDPTAGTCB; 957 r = t4_read_reg(sc, A_ULP_RX_CTL); 958 if ((r & m) != v) { 959 device_printf(sc->dev, "invalid ULP_RX_CTL(0x%x)\n", r); 960 rc = EINVAL; 961 } 962 963 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 964 F_RESETDDPOFFSET; 965 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 966 r = t4_read_reg(sc, A_TP_PARA_REG5); 967 if ((r & m) != v) { 968 device_printf(sc->dev, "invalid TP_PARA_REG5(0x%x)\n", r); 969 rc = EINVAL; 970 } 971 972 t4_init_tp_params(sc, 1); 973 974 t4_read_mtu_tbl(sc, sc->params.mtus, NULL); 975 t4_load_mtus(sc, sc->params.mtus, sc->params.a_wnd, sc->params.b_wnd); 976 977 return (rc); 978 } 979 980 int 981 t4_create_dma_tag(struct adapter *sc) 982 { 983 int rc; 984 985 rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0, 986 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE, 987 BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL, 988 NULL, &sc->dmat); 989 if (rc != 0) { 990 device_printf(sc->dev, 991 "failed to create main DMA tag: %d\n", rc); 992 } 993 994 return (rc); 995 } 996 997 void 998 t4_sge_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx, 999 struct sysctl_oid_list *children) 1000 { 1001 struct sge_params *sp = &sc->params.sge; 1002 1003 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "buffer_sizes", 1004 CTLTYPE_STRING | CTLFLAG_RD, &sc->sge, 0, sysctl_bufsizes, "A", 1005 "freelist buffer sizes"); 1006 1007 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pktshift", CTLFLAG_RD, 1008 NULL, sp->fl_pktshift, "payload DMA offset in rx buffer (bytes)"); 1009 1010 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pad", CTLFLAG_RD, 1011 NULL, sp->pad_boundary, "payload pad boundary (bytes)"); 1012 1013 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "spg_len", CTLFLAG_RD, 1014 NULL, sp->spg_len, "status page size (bytes)"); 1015 1016 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_drop", CTLFLAG_RD, 1017 NULL, cong_drop, "congestion drop setting"); 1018 1019 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pack", CTLFLAG_RD, 1020 NULL, sp->pack_boundary, "payload pack boundary (bytes)"); 1021 } 1022 1023 int 1024 t4_destroy_dma_tag(struct adapter *sc) 1025 { 1026 if (sc->dmat) 1027 bus_dma_tag_destroy(sc->dmat); 1028 1029 return (0); 1030 } 1031 1032 /* 1033 * Allocate and initialize the firmware event queue, control queues, and special 1034 * purpose rx queues owned by the adapter. 1035 * 1036 * Returns errno on failure. Resources allocated up to that point may still be 1037 * allocated. Caller is responsible for cleanup in case this function fails. 1038 */ 1039 int 1040 t4_setup_adapter_queues(struct adapter *sc) 1041 { 1042 struct sysctl_oid *oid; 1043 struct sysctl_oid_list *children; 1044 int rc, i; 1045 1046 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 1047 1048 sysctl_ctx_init(&sc->ctx); 1049 sc->flags |= ADAP_SYSCTL_CTX; 1050 1051 /* 1052 * Firmware event queue 1053 */ 1054 rc = alloc_fwq(sc); 1055 if (rc != 0) 1056 return (rc); 1057 1058 /* 1059 * That's all for the VF driver. 1060 */ 1061 if (sc->flags & IS_VF) 1062 return (rc); 1063 1064 oid = device_get_sysctl_tree(sc->dev); 1065 children = SYSCTL_CHILDREN(oid); 1066 1067 /* 1068 * XXX: General purpose rx queues, one per port. 1069 */ 1070 1071 /* 1072 * Control queues, one per port. 1073 */ 1074 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "ctrlq", 1075 CTLFLAG_RD, NULL, "control queues"); 1076 for_each_port(sc, i) { 1077 struct sge_wrq *ctrlq = &sc->sge.ctrlq[i]; 1078 1079 rc = alloc_ctrlq(sc, ctrlq, i, oid); 1080 if (rc != 0) 1081 return (rc); 1082 } 1083 1084 return (rc); 1085 } 1086 1087 /* 1088 * Idempotent 1089 */ 1090 int 1091 t4_teardown_adapter_queues(struct adapter *sc) 1092 { 1093 int i; 1094 1095 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 1096 1097 /* Do this before freeing the queue */ 1098 if (sc->flags & ADAP_SYSCTL_CTX) { 1099 sysctl_ctx_free(&sc->ctx); 1100 sc->flags &= ~ADAP_SYSCTL_CTX; 1101 } 1102 1103 if (!(sc->flags & IS_VF)) { 1104 for_each_port(sc, i) 1105 free_wrq(sc, &sc->sge.ctrlq[i]); 1106 } 1107 free_fwq(sc); 1108 1109 return (0); 1110 } 1111 1112 /* Maximum payload that can be delivered with a single iq descriptor */ 1113 static inline int 1114 mtu_to_max_payload(struct adapter *sc, int mtu, const int toe) 1115 { 1116 int payload; 1117 1118 #ifdef TCP_OFFLOAD 1119 if (toe) { 1120 int rxcs = G_RXCOALESCESIZE(t4_read_reg(sc, A_TP_PARA_REG2)); 1121 1122 /* Note that COP can set rx_coalesce on/off per connection. */ 1123 payload = max(mtu, rxcs); 1124 } else { 1125 #endif 1126 /* large enough even when hw VLAN extraction is disabled */ 1127 payload = sc->params.sge.fl_pktshift + ETHER_HDR_LEN + 1128 ETHER_VLAN_ENCAP_LEN + mtu; 1129 #ifdef TCP_OFFLOAD 1130 } 1131 #endif 1132 1133 return (payload); 1134 } 1135 1136 int 1137 t4_setup_vi_queues(struct vi_info *vi) 1138 { 1139 int rc = 0, i, intr_idx, iqidx; 1140 struct sge_rxq *rxq; 1141 struct sge_txq *txq; 1142 #ifdef TCP_OFFLOAD 1143 struct sge_ofld_rxq *ofld_rxq; 1144 #endif 1145 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1146 struct sge_wrq *ofld_txq; 1147 #endif 1148 #ifdef DEV_NETMAP 1149 int saved_idx; 1150 struct sge_nm_rxq *nm_rxq; 1151 struct sge_nm_txq *nm_txq; 1152 #endif 1153 char name[16]; 1154 struct port_info *pi = vi->pi; 1155 struct adapter *sc = pi->adapter; 1156 struct ifnet *ifp = vi->ifp; 1157 struct sysctl_oid *oid = device_get_sysctl_tree(vi->dev); 1158 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 1159 int maxp, mtu = ifp->if_mtu; 1160 1161 /* Interrupt vector to start from (when using multiple vectors) */ 1162 intr_idx = vi->first_intr; 1163 1164 #ifdef DEV_NETMAP 1165 saved_idx = intr_idx; 1166 if (ifp->if_capabilities & IFCAP_NETMAP) { 1167 1168 /* netmap is supported with direct interrupts only. */ 1169 MPASS(!forwarding_intr_to_fwq(sc)); 1170 1171 /* 1172 * We don't have buffers to back the netmap rx queues 1173 * right now so we create the queues in a way that 1174 * doesn't set off any congestion signal in the chip. 1175 */ 1176 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "nm_rxq", 1177 CTLFLAG_RD, NULL, "rx queues"); 1178 for_each_nm_rxq(vi, i, nm_rxq) { 1179 rc = alloc_nm_rxq(vi, nm_rxq, intr_idx, i, oid); 1180 if (rc != 0) 1181 goto done; 1182 intr_idx++; 1183 } 1184 1185 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "nm_txq", 1186 CTLFLAG_RD, NULL, "tx queues"); 1187 for_each_nm_txq(vi, i, nm_txq) { 1188 iqidx = vi->first_nm_rxq + (i % vi->nnmrxq); 1189 rc = alloc_nm_txq(vi, nm_txq, iqidx, i, oid); 1190 if (rc != 0) 1191 goto done; 1192 } 1193 } 1194 1195 /* Normal rx queues and netmap rx queues share the same interrupts. */ 1196 intr_idx = saved_idx; 1197 #endif 1198 1199 /* 1200 * Allocate rx queues first because a default iqid is required when 1201 * creating a tx queue. 1202 */ 1203 maxp = mtu_to_max_payload(sc, mtu, 0); 1204 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "rxq", 1205 CTLFLAG_RD, NULL, "rx queues"); 1206 for_each_rxq(vi, i, rxq) { 1207 1208 init_iq(&rxq->iq, sc, vi->tmr_idx, vi->pktc_idx, vi->qsize_rxq); 1209 1210 snprintf(name, sizeof(name), "%s rxq%d-fl", 1211 device_get_nameunit(vi->dev), i); 1212 init_fl(sc, &rxq->fl, vi->qsize_rxq / 8, maxp, name); 1213 1214 rc = alloc_rxq(vi, rxq, 1215 forwarding_intr_to_fwq(sc) ? -1 : intr_idx, i, oid); 1216 if (rc != 0) 1217 goto done; 1218 intr_idx++; 1219 } 1220 #ifdef DEV_NETMAP 1221 if (ifp->if_capabilities & IFCAP_NETMAP) 1222 intr_idx = saved_idx + max(vi->nrxq, vi->nnmrxq); 1223 #endif 1224 #ifdef TCP_OFFLOAD 1225 maxp = mtu_to_max_payload(sc, mtu, 1); 1226 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_rxq", 1227 CTLFLAG_RD, NULL, "rx queues for offloaded TCP connections"); 1228 for_each_ofld_rxq(vi, i, ofld_rxq) { 1229 1230 init_iq(&ofld_rxq->iq, sc, vi->ofld_tmr_idx, vi->ofld_pktc_idx, 1231 vi->qsize_rxq); 1232 1233 snprintf(name, sizeof(name), "%s ofld_rxq%d-fl", 1234 device_get_nameunit(vi->dev), i); 1235 init_fl(sc, &ofld_rxq->fl, vi->qsize_rxq / 8, maxp, name); 1236 1237 rc = alloc_ofld_rxq(vi, ofld_rxq, 1238 forwarding_intr_to_fwq(sc) ? -1 : intr_idx, i, oid); 1239 if (rc != 0) 1240 goto done; 1241 intr_idx++; 1242 } 1243 #endif 1244 1245 /* 1246 * Now the tx queues. 1247 */ 1248 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "txq", CTLFLAG_RD, 1249 NULL, "tx queues"); 1250 for_each_txq(vi, i, txq) { 1251 iqidx = vi->first_rxq + (i % vi->nrxq); 1252 snprintf(name, sizeof(name), "%s txq%d", 1253 device_get_nameunit(vi->dev), i); 1254 init_eq(sc, &txq->eq, EQ_ETH, vi->qsize_txq, pi->tx_chan, 1255 sc->sge.rxq[iqidx].iq.cntxt_id, name); 1256 1257 rc = alloc_txq(vi, txq, i, oid); 1258 if (rc != 0) 1259 goto done; 1260 } 1261 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1262 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_txq", 1263 CTLFLAG_RD, NULL, "tx queues for TOE/ETHOFLD"); 1264 for_each_ofld_txq(vi, i, ofld_txq) { 1265 struct sysctl_oid *oid2; 1266 1267 snprintf(name, sizeof(name), "%s ofld_txq%d", 1268 device_get_nameunit(vi->dev), i); 1269 if (vi->nofldrxq > 0) { 1270 iqidx = vi->first_ofld_rxq + (i % vi->nofldrxq); 1271 init_eq(sc, &ofld_txq->eq, EQ_OFLD, vi->qsize_txq, 1272 pi->tx_chan, sc->sge.ofld_rxq[iqidx].iq.cntxt_id, 1273 name); 1274 } else { 1275 iqidx = vi->first_rxq + (i % vi->nrxq); 1276 init_eq(sc, &ofld_txq->eq, EQ_OFLD, vi->qsize_txq, 1277 pi->tx_chan, sc->sge.rxq[iqidx].iq.cntxt_id, name); 1278 } 1279 1280 snprintf(name, sizeof(name), "%d", i); 1281 oid2 = SYSCTL_ADD_NODE(&vi->ctx, SYSCTL_CHILDREN(oid), OID_AUTO, 1282 name, CTLFLAG_RD, NULL, "offload tx queue"); 1283 1284 rc = alloc_wrq(sc, vi, ofld_txq, oid2); 1285 if (rc != 0) 1286 goto done; 1287 } 1288 #endif 1289 done: 1290 if (rc) 1291 t4_teardown_vi_queues(vi); 1292 1293 return (rc); 1294 } 1295 1296 /* 1297 * Idempotent 1298 */ 1299 int 1300 t4_teardown_vi_queues(struct vi_info *vi) 1301 { 1302 int i; 1303 struct sge_rxq *rxq; 1304 struct sge_txq *txq; 1305 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1306 struct port_info *pi = vi->pi; 1307 struct adapter *sc = pi->adapter; 1308 struct sge_wrq *ofld_txq; 1309 #endif 1310 #ifdef TCP_OFFLOAD 1311 struct sge_ofld_rxq *ofld_rxq; 1312 #endif 1313 #ifdef DEV_NETMAP 1314 struct sge_nm_rxq *nm_rxq; 1315 struct sge_nm_txq *nm_txq; 1316 #endif 1317 1318 /* Do this before freeing the queues */ 1319 if (vi->flags & VI_SYSCTL_CTX) { 1320 sysctl_ctx_free(&vi->ctx); 1321 vi->flags &= ~VI_SYSCTL_CTX; 1322 } 1323 1324 #ifdef DEV_NETMAP 1325 if (vi->ifp->if_capabilities & IFCAP_NETMAP) { 1326 for_each_nm_txq(vi, i, nm_txq) { 1327 free_nm_txq(vi, nm_txq); 1328 } 1329 1330 for_each_nm_rxq(vi, i, nm_rxq) { 1331 free_nm_rxq(vi, nm_rxq); 1332 } 1333 } 1334 #endif 1335 1336 /* 1337 * Take down all the tx queues first, as they reference the rx queues 1338 * (for egress updates, etc.). 1339 */ 1340 1341 for_each_txq(vi, i, txq) { 1342 free_txq(vi, txq); 1343 } 1344 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1345 for_each_ofld_txq(vi, i, ofld_txq) { 1346 free_wrq(sc, ofld_txq); 1347 } 1348 #endif 1349 1350 /* 1351 * Then take down the rx queues. 1352 */ 1353 1354 for_each_rxq(vi, i, rxq) { 1355 free_rxq(vi, rxq); 1356 } 1357 #ifdef TCP_OFFLOAD 1358 for_each_ofld_rxq(vi, i, ofld_rxq) { 1359 free_ofld_rxq(vi, ofld_rxq); 1360 } 1361 #endif 1362 1363 return (0); 1364 } 1365 1366 /* 1367 * Interrupt handler when the driver is using only 1 interrupt. This is a very 1368 * unusual scenario. 1369 * 1370 * a) Deals with errors, if any. 1371 * b) Services firmware event queue, which is taking interrupts for all other 1372 * queues. 1373 */ 1374 void 1375 t4_intr_all(void *arg) 1376 { 1377 struct adapter *sc = arg; 1378 struct sge_iq *fwq = &sc->sge.fwq; 1379 1380 MPASS(sc->intr_count == 1); 1381 1382 if (sc->intr_type == INTR_INTX) 1383 t4_write_reg(sc, MYPF_REG(A_PCIE_PF_CLI), 0); 1384 1385 t4_intr_err(arg); 1386 t4_intr_evt(fwq); 1387 } 1388 1389 /* 1390 * Interrupt handler for errors (installed directly when multiple interrupts are 1391 * being used, or called by t4_intr_all). 1392 */ 1393 void 1394 t4_intr_err(void *arg) 1395 { 1396 struct adapter *sc = arg; 1397 1398 t4_slow_intr_handler(sc); 1399 } 1400 1401 /* 1402 * Interrupt handler for iq-only queues. The firmware event queue is the only 1403 * such queue right now. 1404 */ 1405 void 1406 t4_intr_evt(void *arg) 1407 { 1408 struct sge_iq *iq = arg; 1409 1410 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 1411 service_iq(iq, 0); 1412 (void) atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 1413 } 1414 } 1415 1416 /* 1417 * Interrupt handler for iq+fl queues. 1418 */ 1419 void 1420 t4_intr(void *arg) 1421 { 1422 struct sge_iq *iq = arg; 1423 1424 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 1425 service_iq_fl(iq, 0); 1426 (void) atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 1427 } 1428 } 1429 1430 #ifdef DEV_NETMAP 1431 /* 1432 * Interrupt handler for netmap rx queues. 1433 */ 1434 void 1435 t4_nm_intr(void *arg) 1436 { 1437 struct sge_nm_rxq *nm_rxq = arg; 1438 1439 if (atomic_cmpset_int(&nm_rxq->nm_state, NM_ON, NM_BUSY)) { 1440 service_nm_rxq(nm_rxq); 1441 (void) atomic_cmpset_int(&nm_rxq->nm_state, NM_BUSY, NM_ON); 1442 } 1443 } 1444 1445 /* 1446 * Interrupt handler for vectors shared between NIC and netmap rx queues. 1447 */ 1448 void 1449 t4_vi_intr(void *arg) 1450 { 1451 struct irq *irq = arg; 1452 1453 MPASS(irq->nm_rxq != NULL); 1454 t4_nm_intr(irq->nm_rxq); 1455 1456 MPASS(irq->rxq != NULL); 1457 t4_intr(irq->rxq); 1458 } 1459 #endif 1460 1461 /* 1462 * Deals with interrupts on an iq-only (no freelist) queue. 1463 */ 1464 static int 1465 service_iq(struct sge_iq *iq, int budget) 1466 { 1467 struct sge_iq *q; 1468 struct adapter *sc = iq->adapter; 1469 struct iq_desc *d = &iq->desc[iq->cidx]; 1470 int ndescs = 0, limit; 1471 int rsp_type; 1472 uint32_t lq; 1473 STAILQ_HEAD(, sge_iq) iql = STAILQ_HEAD_INITIALIZER(iql); 1474 1475 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq)); 1476 KASSERT((iq->flags & IQ_HAS_FL) == 0, 1477 ("%s: called for iq %p with fl (iq->flags 0x%x)", __func__, iq, 1478 iq->flags)); 1479 MPASS((iq->flags & IQ_ADJ_CREDIT) == 0); 1480 MPASS((iq->flags & IQ_LRO_ENABLED) == 0); 1481 1482 limit = budget ? budget : iq->qsize / 16; 1483 1484 /* 1485 * We always come back and check the descriptor ring for new indirect 1486 * interrupts and other responses after running a single handler. 1487 */ 1488 for (;;) { 1489 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) { 1490 1491 rmb(); 1492 1493 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen); 1494 lq = be32toh(d->rsp.pldbuflen_qid); 1495 1496 switch (rsp_type) { 1497 case X_RSPD_TYPE_FLBUF: 1498 panic("%s: data for an iq (%p) with no freelist", 1499 __func__, iq); 1500 1501 /* NOTREACHED */ 1502 1503 case X_RSPD_TYPE_CPL: 1504 KASSERT(d->rss.opcode < NUM_CPL_CMDS, 1505 ("%s: bad opcode %02x.", __func__, 1506 d->rss.opcode)); 1507 t4_cpl_handler[d->rss.opcode](iq, &d->rss, NULL); 1508 break; 1509 1510 case X_RSPD_TYPE_INTR: 1511 /* 1512 * There are 1K interrupt-capable queues (qids 0 1513 * through 1023). A response type indicating a 1514 * forwarded interrupt with a qid >= 1K is an 1515 * iWARP async notification. 1516 */ 1517 if (__predict_true(lq >= 1024)) { 1518 t4_an_handler(iq, &d->rsp); 1519 break; 1520 } 1521 1522 q = sc->sge.iqmap[lq - sc->sge.iq_start - 1523 sc->sge.iq_base]; 1524 if (atomic_cmpset_int(&q->state, IQS_IDLE, 1525 IQS_BUSY)) { 1526 if (service_iq_fl(q, q->qsize / 16) == 0) { 1527 (void) atomic_cmpset_int(&q->state, 1528 IQS_BUSY, IQS_IDLE); 1529 } else { 1530 STAILQ_INSERT_TAIL(&iql, q, 1531 link); 1532 } 1533 } 1534 break; 1535 1536 default: 1537 KASSERT(0, 1538 ("%s: illegal response type %d on iq %p", 1539 __func__, rsp_type, iq)); 1540 log(LOG_ERR, 1541 "%s: illegal response type %d on iq %p", 1542 device_get_nameunit(sc->dev), rsp_type, iq); 1543 break; 1544 } 1545 1546 d++; 1547 if (__predict_false(++iq->cidx == iq->sidx)) { 1548 iq->cidx = 0; 1549 iq->gen ^= F_RSPD_GEN; 1550 d = &iq->desc[0]; 1551 } 1552 if (__predict_false(++ndescs == limit)) { 1553 t4_write_reg(sc, sc->sge_gts_reg, 1554 V_CIDXINC(ndescs) | 1555 V_INGRESSQID(iq->cntxt_id) | 1556 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); 1557 ndescs = 0; 1558 1559 if (budget) { 1560 return (EINPROGRESS); 1561 } 1562 } 1563 } 1564 1565 if (STAILQ_EMPTY(&iql)) 1566 break; 1567 1568 /* 1569 * Process the head only, and send it to the back of the list if 1570 * it's still not done. 1571 */ 1572 q = STAILQ_FIRST(&iql); 1573 STAILQ_REMOVE_HEAD(&iql, link); 1574 if (service_iq_fl(q, q->qsize / 8) == 0) 1575 (void) atomic_cmpset_int(&q->state, IQS_BUSY, IQS_IDLE); 1576 else 1577 STAILQ_INSERT_TAIL(&iql, q, link); 1578 } 1579 1580 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) | 1581 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params)); 1582 1583 return (0); 1584 } 1585 1586 static inline int 1587 sort_before_lro(struct lro_ctrl *lro) 1588 { 1589 1590 return (lro->lro_mbuf_max != 0); 1591 } 1592 1593 static inline uint64_t 1594 last_flit_to_ns(struct adapter *sc, uint64_t lf) 1595 { 1596 uint64_t n = be64toh(lf) & 0xfffffffffffffff; /* 60b, not 64b. */ 1597 1598 if (n > UINT64_MAX / 1000000) 1599 return (n / sc->params.vpd.cclk * 1000000); 1600 else 1601 return (n * 1000000 / sc->params.vpd.cclk); 1602 } 1603 1604 /* 1605 * Deals with interrupts on an iq+fl queue. 1606 */ 1607 static int 1608 service_iq_fl(struct sge_iq *iq, int budget) 1609 { 1610 struct sge_rxq *rxq = iq_to_rxq(iq); 1611 struct sge_fl *fl; 1612 struct adapter *sc = iq->adapter; 1613 struct iq_desc *d = &iq->desc[iq->cidx]; 1614 int ndescs = 0, limit; 1615 int rsp_type, refill, starved; 1616 uint32_t lq; 1617 uint16_t fl_hw_cidx; 1618 struct mbuf *m0; 1619 #if defined(INET) || defined(INET6) 1620 const struct timeval lro_timeout = {0, sc->lro_timeout}; 1621 struct lro_ctrl *lro = &rxq->lro; 1622 #endif 1623 1624 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq)); 1625 MPASS(iq->flags & IQ_HAS_FL); 1626 1627 limit = budget ? budget : iq->qsize / 16; 1628 fl = &rxq->fl; 1629 fl_hw_cidx = fl->hw_cidx; /* stable snapshot */ 1630 1631 #if defined(INET) || defined(INET6) 1632 if (iq->flags & IQ_ADJ_CREDIT) { 1633 MPASS(sort_before_lro(lro)); 1634 iq->flags &= ~IQ_ADJ_CREDIT; 1635 if ((d->rsp.u.type_gen & F_RSPD_GEN) != iq->gen) { 1636 tcp_lro_flush_all(lro); 1637 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(1) | 1638 V_INGRESSQID((u32)iq->cntxt_id) | 1639 V_SEINTARM(iq->intr_params)); 1640 return (0); 1641 } 1642 ndescs = 1; 1643 } 1644 #else 1645 MPASS((iq->flags & IQ_ADJ_CREDIT) == 0); 1646 #endif 1647 1648 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) { 1649 1650 rmb(); 1651 1652 refill = 0; 1653 m0 = NULL; 1654 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen); 1655 lq = be32toh(d->rsp.pldbuflen_qid); 1656 1657 switch (rsp_type) { 1658 case X_RSPD_TYPE_FLBUF: 1659 1660 m0 = get_fl_payload(sc, fl, lq); 1661 if (__predict_false(m0 == NULL)) 1662 goto out; 1663 refill = IDXDIFF(fl->hw_cidx, fl_hw_cidx, fl->sidx) > 2; 1664 1665 if (iq->flags & IQ_RX_TIMESTAMP) { 1666 /* 1667 * Fill up rcv_tstmp but do not set M_TSTMP. 1668 * rcv_tstmp is not in the format that the 1669 * kernel expects and we don't want to mislead 1670 * it. For now this is only for custom code 1671 * that knows how to interpret cxgbe's stamp. 1672 */ 1673 m0->m_pkthdr.rcv_tstmp = 1674 last_flit_to_ns(sc, d->rsp.u.last_flit); 1675 #ifdef notyet 1676 m0->m_flags |= M_TSTMP; 1677 #endif 1678 } 1679 1680 /* fall through */ 1681 1682 case X_RSPD_TYPE_CPL: 1683 KASSERT(d->rss.opcode < NUM_CPL_CMDS, 1684 ("%s: bad opcode %02x.", __func__, d->rss.opcode)); 1685 t4_cpl_handler[d->rss.opcode](iq, &d->rss, m0); 1686 break; 1687 1688 case X_RSPD_TYPE_INTR: 1689 1690 /* 1691 * There are 1K interrupt-capable queues (qids 0 1692 * through 1023). A response type indicating a 1693 * forwarded interrupt with a qid >= 1K is an 1694 * iWARP async notification. That is the only 1695 * acceptable indirect interrupt on this queue. 1696 */ 1697 if (__predict_false(lq < 1024)) { 1698 panic("%s: indirect interrupt on iq_fl %p " 1699 "with qid %u", __func__, iq, lq); 1700 } 1701 1702 t4_an_handler(iq, &d->rsp); 1703 break; 1704 1705 default: 1706 KASSERT(0, ("%s: illegal response type %d on iq %p", 1707 __func__, rsp_type, iq)); 1708 log(LOG_ERR, "%s: illegal response type %d on iq %p", 1709 device_get_nameunit(sc->dev), rsp_type, iq); 1710 break; 1711 } 1712 1713 d++; 1714 if (__predict_false(++iq->cidx == iq->sidx)) { 1715 iq->cidx = 0; 1716 iq->gen ^= F_RSPD_GEN; 1717 d = &iq->desc[0]; 1718 } 1719 if (__predict_false(++ndescs == limit)) { 1720 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) | 1721 V_INGRESSQID(iq->cntxt_id) | 1722 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); 1723 ndescs = 0; 1724 1725 #if defined(INET) || defined(INET6) 1726 if (iq->flags & IQ_LRO_ENABLED && 1727 !sort_before_lro(lro) && 1728 sc->lro_timeout != 0) { 1729 tcp_lro_flush_inactive(lro, &lro_timeout); 1730 } 1731 #endif 1732 if (budget) { 1733 FL_LOCK(fl); 1734 refill_fl(sc, fl, 32); 1735 FL_UNLOCK(fl); 1736 1737 return (EINPROGRESS); 1738 } 1739 } 1740 if (refill) { 1741 FL_LOCK(fl); 1742 refill_fl(sc, fl, 32); 1743 FL_UNLOCK(fl); 1744 fl_hw_cidx = fl->hw_cidx; 1745 } 1746 } 1747 out: 1748 #if defined(INET) || defined(INET6) 1749 if (iq->flags & IQ_LRO_ENABLED) { 1750 if (ndescs > 0 && lro->lro_mbuf_count > 8) { 1751 MPASS(sort_before_lro(lro)); 1752 /* hold back one credit and don't flush LRO state */ 1753 iq->flags |= IQ_ADJ_CREDIT; 1754 ndescs--; 1755 } else { 1756 tcp_lro_flush_all(lro); 1757 } 1758 } 1759 #endif 1760 1761 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) | 1762 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params)); 1763 1764 FL_LOCK(fl); 1765 starved = refill_fl(sc, fl, 64); 1766 FL_UNLOCK(fl); 1767 if (__predict_false(starved != 0)) 1768 add_fl_to_sfl(sc, fl); 1769 1770 return (0); 1771 } 1772 1773 static inline int 1774 cl_has_metadata(struct sge_fl *fl, struct cluster_layout *cll) 1775 { 1776 int rc = fl->flags & FL_BUF_PACKING || cll->region1 > 0; 1777 1778 if (rc) 1779 MPASS(cll->region3 >= CL_METADATA_SIZE); 1780 1781 return (rc); 1782 } 1783 1784 static inline struct cluster_metadata * 1785 cl_metadata(struct adapter *sc, struct sge_fl *fl, struct cluster_layout *cll, 1786 caddr_t cl) 1787 { 1788 1789 if (cl_has_metadata(fl, cll)) { 1790 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx]; 1791 1792 return ((struct cluster_metadata *)(cl + swz->size) - 1); 1793 } 1794 return (NULL); 1795 } 1796 1797 static void 1798 rxb_free(struct mbuf *m) 1799 { 1800 uma_zone_t zone = m->m_ext.ext_arg1; 1801 void *cl = m->m_ext.ext_arg2; 1802 1803 uma_zfree(zone, cl); 1804 counter_u64_add(extfree_rels, 1); 1805 } 1806 1807 /* 1808 * The mbuf returned by this function could be allocated from zone_mbuf or 1809 * constructed in spare room in the cluster. 1810 * 1811 * The mbuf carries the payload in one of these ways 1812 * a) frame inside the mbuf (mbuf from zone_mbuf) 1813 * b) m_cljset (for clusters without metadata) zone_mbuf 1814 * c) m_extaddref (cluster with metadata) inline mbuf 1815 * d) m_extaddref (cluster with metadata) zone_mbuf 1816 */ 1817 static struct mbuf * 1818 get_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset, 1819 int remaining) 1820 { 1821 struct mbuf *m; 1822 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 1823 struct cluster_layout *cll = &sd->cll; 1824 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx]; 1825 struct hw_buf_info *hwb = &sc->sge.hw_buf_info[cll->hwidx]; 1826 struct cluster_metadata *clm = cl_metadata(sc, fl, cll, sd->cl); 1827 int len, blen; 1828 caddr_t payload; 1829 1830 blen = hwb->size - fl->rx_offset; /* max possible in this buf */ 1831 len = min(remaining, blen); 1832 payload = sd->cl + cll->region1 + fl->rx_offset; 1833 if (fl->flags & FL_BUF_PACKING) { 1834 const u_int l = fr_offset + len; 1835 const u_int pad = roundup2(l, fl->buf_boundary) - l; 1836 1837 if (fl->rx_offset + len + pad < hwb->size) 1838 blen = len + pad; 1839 MPASS(fl->rx_offset + blen <= hwb->size); 1840 } else { 1841 MPASS(fl->rx_offset == 0); /* not packing */ 1842 } 1843 1844 1845 if (sc->sc_do_rxcopy && len < RX_COPY_THRESHOLD) { 1846 1847 /* 1848 * Copy payload into a freshly allocated mbuf. 1849 */ 1850 1851 m = fr_offset == 0 ? 1852 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA); 1853 if (m == NULL) 1854 return (NULL); 1855 fl->mbuf_allocated++; 1856 1857 /* copy data to mbuf */ 1858 bcopy(payload, mtod(m, caddr_t), len); 1859 1860 } else if (sd->nmbuf * MSIZE < cll->region1) { 1861 1862 /* 1863 * There's spare room in the cluster for an mbuf. Create one 1864 * and associate it with the payload that's in the cluster. 1865 */ 1866 1867 MPASS(clm != NULL); 1868 m = (struct mbuf *)(sd->cl + sd->nmbuf * MSIZE); 1869 /* No bzero required */ 1870 if (m_init(m, M_NOWAIT, MT_DATA, 1871 fr_offset == 0 ? M_PKTHDR | M_NOFREE : M_NOFREE)) 1872 return (NULL); 1873 fl->mbuf_inlined++; 1874 m_extaddref(m, payload, blen, &clm->refcount, rxb_free, 1875 swz->zone, sd->cl); 1876 if (sd->nmbuf++ == 0) 1877 counter_u64_add(extfree_refs, 1); 1878 1879 } else { 1880 1881 /* 1882 * Grab an mbuf from zone_mbuf and associate it with the 1883 * payload in the cluster. 1884 */ 1885 1886 m = fr_offset == 0 ? 1887 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA); 1888 if (m == NULL) 1889 return (NULL); 1890 fl->mbuf_allocated++; 1891 if (clm != NULL) { 1892 m_extaddref(m, payload, blen, &clm->refcount, 1893 rxb_free, swz->zone, sd->cl); 1894 if (sd->nmbuf++ == 0) 1895 counter_u64_add(extfree_refs, 1); 1896 } else { 1897 m_cljset(m, sd->cl, swz->type); 1898 sd->cl = NULL; /* consumed, not a recycle candidate */ 1899 } 1900 } 1901 if (fr_offset == 0) 1902 m->m_pkthdr.len = remaining; 1903 m->m_len = len; 1904 1905 if (fl->flags & FL_BUF_PACKING) { 1906 fl->rx_offset += blen; 1907 MPASS(fl->rx_offset <= hwb->size); 1908 if (fl->rx_offset < hwb->size) 1909 return (m); /* without advancing the cidx */ 1910 } 1911 1912 if (__predict_false(++fl->cidx % 8 == 0)) { 1913 uint16_t cidx = fl->cidx / 8; 1914 1915 if (__predict_false(cidx == fl->sidx)) 1916 fl->cidx = cidx = 0; 1917 fl->hw_cidx = cidx; 1918 } 1919 fl->rx_offset = 0; 1920 1921 return (m); 1922 } 1923 1924 static struct mbuf * 1925 get_fl_payload(struct adapter *sc, struct sge_fl *fl, uint32_t len_newbuf) 1926 { 1927 struct mbuf *m0, *m, **pnext; 1928 u_int remaining; 1929 const u_int total = G_RSPD_LEN(len_newbuf); 1930 1931 if (__predict_false(fl->flags & FL_BUF_RESUME)) { 1932 M_ASSERTPKTHDR(fl->m0); 1933 MPASS(fl->m0->m_pkthdr.len == total); 1934 MPASS(fl->remaining < total); 1935 1936 m0 = fl->m0; 1937 pnext = fl->pnext; 1938 remaining = fl->remaining; 1939 fl->flags &= ~FL_BUF_RESUME; 1940 goto get_segment; 1941 } 1942 1943 if (fl->rx_offset > 0 && len_newbuf & F_RSPD_NEWBUF) { 1944 fl->rx_offset = 0; 1945 if (__predict_false(++fl->cidx % 8 == 0)) { 1946 uint16_t cidx = fl->cidx / 8; 1947 1948 if (__predict_false(cidx == fl->sidx)) 1949 fl->cidx = cidx = 0; 1950 fl->hw_cidx = cidx; 1951 } 1952 } 1953 1954 /* 1955 * Payload starts at rx_offset in the current hw buffer. Its length is 1956 * 'len' and it may span multiple hw buffers. 1957 */ 1958 1959 m0 = get_scatter_segment(sc, fl, 0, total); 1960 if (m0 == NULL) 1961 return (NULL); 1962 remaining = total - m0->m_len; 1963 pnext = &m0->m_next; 1964 while (remaining > 0) { 1965 get_segment: 1966 MPASS(fl->rx_offset == 0); 1967 m = get_scatter_segment(sc, fl, total - remaining, remaining); 1968 if (__predict_false(m == NULL)) { 1969 fl->m0 = m0; 1970 fl->pnext = pnext; 1971 fl->remaining = remaining; 1972 fl->flags |= FL_BUF_RESUME; 1973 return (NULL); 1974 } 1975 *pnext = m; 1976 pnext = &m->m_next; 1977 remaining -= m->m_len; 1978 } 1979 *pnext = NULL; 1980 1981 M_ASSERTPKTHDR(m0); 1982 return (m0); 1983 } 1984 1985 static int 1986 t4_eth_rx(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0) 1987 { 1988 struct sge_rxq *rxq = iq_to_rxq(iq); 1989 struct ifnet *ifp = rxq->ifp; 1990 struct adapter *sc = iq->adapter; 1991 const struct cpl_rx_pkt *cpl = (const void *)(rss + 1); 1992 #if defined(INET) || defined(INET6) 1993 struct lro_ctrl *lro = &rxq->lro; 1994 #endif 1995 static const int sw_hashtype[4][2] = { 1996 {M_HASHTYPE_NONE, M_HASHTYPE_NONE}, 1997 {M_HASHTYPE_RSS_IPV4, M_HASHTYPE_RSS_IPV6}, 1998 {M_HASHTYPE_RSS_TCP_IPV4, M_HASHTYPE_RSS_TCP_IPV6}, 1999 {M_HASHTYPE_RSS_UDP_IPV4, M_HASHTYPE_RSS_UDP_IPV6}, 2000 }; 2001 2002 KASSERT(m0 != NULL, ("%s: no payload with opcode %02x", __func__, 2003 rss->opcode)); 2004 2005 m0->m_pkthdr.len -= sc->params.sge.fl_pktshift; 2006 m0->m_len -= sc->params.sge.fl_pktshift; 2007 m0->m_data += sc->params.sge.fl_pktshift; 2008 2009 m0->m_pkthdr.rcvif = ifp; 2010 M_HASHTYPE_SET(m0, sw_hashtype[rss->hash_type][rss->ipv6]); 2011 m0->m_pkthdr.flowid = be32toh(rss->hash_val); 2012 2013 if (cpl->csum_calc && !(cpl->err_vec & sc->params.tp.err_vec_mask)) { 2014 if (ifp->if_capenable & IFCAP_RXCSUM && 2015 cpl->l2info & htobe32(F_RXF_IP)) { 2016 m0->m_pkthdr.csum_flags = (CSUM_IP_CHECKED | 2017 CSUM_IP_VALID | CSUM_DATA_VALID | CSUM_PSEUDO_HDR); 2018 rxq->rxcsum++; 2019 } else if (ifp->if_capenable & IFCAP_RXCSUM_IPV6 && 2020 cpl->l2info & htobe32(F_RXF_IP6)) { 2021 m0->m_pkthdr.csum_flags = (CSUM_DATA_VALID_IPV6 | 2022 CSUM_PSEUDO_HDR); 2023 rxq->rxcsum++; 2024 } 2025 2026 if (__predict_false(cpl->ip_frag)) 2027 m0->m_pkthdr.csum_data = be16toh(cpl->csum); 2028 else 2029 m0->m_pkthdr.csum_data = 0xffff; 2030 } 2031 2032 if (cpl->vlan_ex) { 2033 m0->m_pkthdr.ether_vtag = be16toh(cpl->vlan); 2034 m0->m_flags |= M_VLANTAG; 2035 rxq->vlan_extraction++; 2036 } 2037 2038 #if defined(INET) || defined(INET6) 2039 if (iq->flags & IQ_LRO_ENABLED) { 2040 if (sort_before_lro(lro)) { 2041 tcp_lro_queue_mbuf(lro, m0); 2042 return (0); /* queued for sort, then LRO */ 2043 } 2044 if (tcp_lro_rx(lro, m0, 0) == 0) 2045 return (0); /* queued for LRO */ 2046 } 2047 #endif 2048 ifp->if_input(ifp, m0); 2049 2050 return (0); 2051 } 2052 2053 /* 2054 * Must drain the wrq or make sure that someone else will. 2055 */ 2056 static void 2057 wrq_tx_drain(void *arg, int n) 2058 { 2059 struct sge_wrq *wrq = arg; 2060 struct sge_eq *eq = &wrq->eq; 2061 2062 EQ_LOCK(eq); 2063 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 2064 drain_wrq_wr_list(wrq->adapter, wrq); 2065 EQ_UNLOCK(eq); 2066 } 2067 2068 static void 2069 drain_wrq_wr_list(struct adapter *sc, struct sge_wrq *wrq) 2070 { 2071 struct sge_eq *eq = &wrq->eq; 2072 u_int available, dbdiff; /* # of hardware descriptors */ 2073 u_int n; 2074 struct wrqe *wr; 2075 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */ 2076 2077 EQ_LOCK_ASSERT_OWNED(eq); 2078 MPASS(TAILQ_EMPTY(&wrq->incomplete_wrs)); 2079 wr = STAILQ_FIRST(&wrq->wr_list); 2080 MPASS(wr != NULL); /* Must be called with something useful to do */ 2081 MPASS(eq->pidx == eq->dbidx); 2082 dbdiff = 0; 2083 2084 do { 2085 eq->cidx = read_hw_cidx(eq); 2086 if (eq->pidx == eq->cidx) 2087 available = eq->sidx - 1; 2088 else 2089 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2090 2091 MPASS(wr->wrq == wrq); 2092 n = howmany(wr->wr_len, EQ_ESIZE); 2093 if (available < n) 2094 break; 2095 2096 dst = (void *)&eq->desc[eq->pidx]; 2097 if (__predict_true(eq->sidx - eq->pidx > n)) { 2098 /* Won't wrap, won't end exactly at the status page. */ 2099 bcopy(&wr->wr[0], dst, wr->wr_len); 2100 eq->pidx += n; 2101 } else { 2102 int first_portion = (eq->sidx - eq->pidx) * EQ_ESIZE; 2103 2104 bcopy(&wr->wr[0], dst, first_portion); 2105 if (wr->wr_len > first_portion) { 2106 bcopy(&wr->wr[first_portion], &eq->desc[0], 2107 wr->wr_len - first_portion); 2108 } 2109 eq->pidx = n - (eq->sidx - eq->pidx); 2110 } 2111 wrq->tx_wrs_copied++; 2112 2113 if (available < eq->sidx / 4 && 2114 atomic_cmpset_int(&eq->equiq, 0, 1)) { 2115 /* 2116 * XXX: This is not 100% reliable with some 2117 * types of WRs. But this is a very unusual 2118 * situation for an ofld/ctrl queue anyway. 2119 */ 2120 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ | 2121 F_FW_WR_EQUEQ); 2122 } 2123 2124 dbdiff += n; 2125 if (dbdiff >= 16) { 2126 ring_eq_db(sc, eq, dbdiff); 2127 dbdiff = 0; 2128 } 2129 2130 STAILQ_REMOVE_HEAD(&wrq->wr_list, link); 2131 free_wrqe(wr); 2132 MPASS(wrq->nwr_pending > 0); 2133 wrq->nwr_pending--; 2134 MPASS(wrq->ndesc_needed >= n); 2135 wrq->ndesc_needed -= n; 2136 } while ((wr = STAILQ_FIRST(&wrq->wr_list)) != NULL); 2137 2138 if (dbdiff) 2139 ring_eq_db(sc, eq, dbdiff); 2140 } 2141 2142 /* 2143 * Doesn't fail. Holds on to work requests it can't send right away. 2144 */ 2145 void 2146 t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, struct wrqe *wr) 2147 { 2148 #ifdef INVARIANTS 2149 struct sge_eq *eq = &wrq->eq; 2150 #endif 2151 2152 EQ_LOCK_ASSERT_OWNED(eq); 2153 MPASS(wr != NULL); 2154 MPASS(wr->wr_len > 0 && wr->wr_len <= SGE_MAX_WR_LEN); 2155 MPASS((wr->wr_len & 0x7) == 0); 2156 2157 STAILQ_INSERT_TAIL(&wrq->wr_list, wr, link); 2158 wrq->nwr_pending++; 2159 wrq->ndesc_needed += howmany(wr->wr_len, EQ_ESIZE); 2160 2161 if (!TAILQ_EMPTY(&wrq->incomplete_wrs)) 2162 return; /* commit_wrq_wr will drain wr_list as well. */ 2163 2164 drain_wrq_wr_list(sc, wrq); 2165 2166 /* Doorbell must have caught up to the pidx. */ 2167 MPASS(eq->pidx == eq->dbidx); 2168 } 2169 2170 void 2171 t4_update_fl_bufsize(struct ifnet *ifp) 2172 { 2173 struct vi_info *vi = ifp->if_softc; 2174 struct adapter *sc = vi->pi->adapter; 2175 struct sge_rxq *rxq; 2176 #ifdef TCP_OFFLOAD 2177 struct sge_ofld_rxq *ofld_rxq; 2178 #endif 2179 struct sge_fl *fl; 2180 int i, maxp, mtu = ifp->if_mtu; 2181 2182 maxp = mtu_to_max_payload(sc, mtu, 0); 2183 for_each_rxq(vi, i, rxq) { 2184 fl = &rxq->fl; 2185 2186 FL_LOCK(fl); 2187 find_best_refill_source(sc, fl, maxp); 2188 FL_UNLOCK(fl); 2189 } 2190 #ifdef TCP_OFFLOAD 2191 maxp = mtu_to_max_payload(sc, mtu, 1); 2192 for_each_ofld_rxq(vi, i, ofld_rxq) { 2193 fl = &ofld_rxq->fl; 2194 2195 FL_LOCK(fl); 2196 find_best_refill_source(sc, fl, maxp); 2197 FL_UNLOCK(fl); 2198 } 2199 #endif 2200 } 2201 2202 static inline int 2203 mbuf_nsegs(struct mbuf *m) 2204 { 2205 2206 M_ASSERTPKTHDR(m); 2207 KASSERT(m->m_pkthdr.l5hlen > 0, 2208 ("%s: mbuf %p missing information on # of segments.", __func__, m)); 2209 2210 return (m->m_pkthdr.l5hlen); 2211 } 2212 2213 static inline void 2214 set_mbuf_nsegs(struct mbuf *m, uint8_t nsegs) 2215 { 2216 2217 M_ASSERTPKTHDR(m); 2218 m->m_pkthdr.l5hlen = nsegs; 2219 } 2220 2221 static inline int 2222 mbuf_cflags(struct mbuf *m) 2223 { 2224 2225 M_ASSERTPKTHDR(m); 2226 return (m->m_pkthdr.PH_loc.eight[4]); 2227 } 2228 2229 static inline void 2230 set_mbuf_cflags(struct mbuf *m, uint8_t flags) 2231 { 2232 2233 M_ASSERTPKTHDR(m); 2234 m->m_pkthdr.PH_loc.eight[4] = flags; 2235 } 2236 2237 static inline int 2238 mbuf_len16(struct mbuf *m) 2239 { 2240 int n; 2241 2242 M_ASSERTPKTHDR(m); 2243 n = m->m_pkthdr.PH_loc.eight[0]; 2244 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16); 2245 2246 return (n); 2247 } 2248 2249 static inline void 2250 set_mbuf_len16(struct mbuf *m, uint8_t len16) 2251 { 2252 2253 M_ASSERTPKTHDR(m); 2254 m->m_pkthdr.PH_loc.eight[0] = len16; 2255 } 2256 2257 #ifdef RATELIMIT 2258 static inline int 2259 mbuf_eo_nsegs(struct mbuf *m) 2260 { 2261 2262 M_ASSERTPKTHDR(m); 2263 return (m->m_pkthdr.PH_loc.eight[1]); 2264 } 2265 2266 static inline void 2267 set_mbuf_eo_nsegs(struct mbuf *m, uint8_t nsegs) 2268 { 2269 2270 M_ASSERTPKTHDR(m); 2271 m->m_pkthdr.PH_loc.eight[1] = nsegs; 2272 } 2273 2274 static inline int 2275 mbuf_eo_len16(struct mbuf *m) 2276 { 2277 int n; 2278 2279 M_ASSERTPKTHDR(m); 2280 n = m->m_pkthdr.PH_loc.eight[2]; 2281 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16); 2282 2283 return (n); 2284 } 2285 2286 static inline void 2287 set_mbuf_eo_len16(struct mbuf *m, uint8_t len16) 2288 { 2289 2290 M_ASSERTPKTHDR(m); 2291 m->m_pkthdr.PH_loc.eight[2] = len16; 2292 } 2293 2294 static inline int 2295 mbuf_eo_tsclk_tsoff(struct mbuf *m) 2296 { 2297 2298 M_ASSERTPKTHDR(m); 2299 return (m->m_pkthdr.PH_loc.eight[3]); 2300 } 2301 2302 static inline void 2303 set_mbuf_eo_tsclk_tsoff(struct mbuf *m, uint8_t tsclk_tsoff) 2304 { 2305 2306 M_ASSERTPKTHDR(m); 2307 m->m_pkthdr.PH_loc.eight[3] = tsclk_tsoff; 2308 } 2309 2310 static inline int 2311 needs_eo(struct mbuf *m) 2312 { 2313 2314 return (m->m_pkthdr.snd_tag != NULL); 2315 } 2316 #endif 2317 2318 /* 2319 * Try to allocate an mbuf to contain a raw work request. To make it 2320 * easy to construct the work request, don't allocate a chain but a 2321 * single mbuf. 2322 */ 2323 struct mbuf * 2324 alloc_wr_mbuf(int len, int how) 2325 { 2326 struct mbuf *m; 2327 2328 if (len <= MHLEN) 2329 m = m_gethdr(how, MT_DATA); 2330 else if (len <= MCLBYTES) 2331 m = m_getcl(how, MT_DATA, M_PKTHDR); 2332 else 2333 m = NULL; 2334 if (m == NULL) 2335 return (NULL); 2336 m->m_pkthdr.len = len; 2337 m->m_len = len; 2338 set_mbuf_cflags(m, MC_RAW_WR); 2339 set_mbuf_len16(m, howmany(len, 16)); 2340 return (m); 2341 } 2342 2343 static inline int 2344 needs_tso(struct mbuf *m) 2345 { 2346 2347 M_ASSERTPKTHDR(m); 2348 2349 return (m->m_pkthdr.csum_flags & CSUM_TSO); 2350 } 2351 2352 static inline int 2353 needs_l3_csum(struct mbuf *m) 2354 { 2355 2356 M_ASSERTPKTHDR(m); 2357 2358 return (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TSO)); 2359 } 2360 2361 static inline int 2362 needs_l4_csum(struct mbuf *m) 2363 { 2364 2365 M_ASSERTPKTHDR(m); 2366 2367 return (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_UDP_IPV6 | 2368 CSUM_TCP_IPV6 | CSUM_TSO)); 2369 } 2370 2371 static inline int 2372 needs_tcp_csum(struct mbuf *m) 2373 { 2374 2375 M_ASSERTPKTHDR(m); 2376 return (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_TCP_IPV6 | CSUM_TSO)); 2377 } 2378 2379 #ifdef RATELIMIT 2380 static inline int 2381 needs_udp_csum(struct mbuf *m) 2382 { 2383 2384 M_ASSERTPKTHDR(m); 2385 return (m->m_pkthdr.csum_flags & (CSUM_UDP | CSUM_UDP_IPV6)); 2386 } 2387 #endif 2388 2389 static inline int 2390 needs_vlan_insertion(struct mbuf *m) 2391 { 2392 2393 M_ASSERTPKTHDR(m); 2394 2395 return (m->m_flags & M_VLANTAG); 2396 } 2397 2398 static void * 2399 m_advance(struct mbuf **pm, int *poffset, int len) 2400 { 2401 struct mbuf *m = *pm; 2402 int offset = *poffset; 2403 uintptr_t p = 0; 2404 2405 MPASS(len > 0); 2406 2407 for (;;) { 2408 if (offset + len < m->m_len) { 2409 offset += len; 2410 p = mtod(m, uintptr_t) + offset; 2411 break; 2412 } 2413 len -= m->m_len - offset; 2414 m = m->m_next; 2415 offset = 0; 2416 MPASS(m != NULL); 2417 } 2418 *poffset = offset; 2419 *pm = m; 2420 return ((void *)p); 2421 } 2422 2423 /* 2424 * Can deal with empty mbufs in the chain that have m_len = 0, but the chain 2425 * must have at least one mbuf that's not empty. It is possible for this 2426 * routine to return 0 if skip accounts for all the contents of the mbuf chain. 2427 */ 2428 static inline int 2429 count_mbuf_nsegs(struct mbuf *m, int skip) 2430 { 2431 vm_paddr_t lastb, next; 2432 vm_offset_t va; 2433 int len, nsegs; 2434 2435 M_ASSERTPKTHDR(m); 2436 MPASS(m->m_pkthdr.len > 0); 2437 MPASS(m->m_pkthdr.len >= skip); 2438 2439 nsegs = 0; 2440 lastb = 0; 2441 for (; m; m = m->m_next) { 2442 2443 len = m->m_len; 2444 if (__predict_false(len == 0)) 2445 continue; 2446 if (skip >= len) { 2447 skip -= len; 2448 continue; 2449 } 2450 va = mtod(m, vm_offset_t) + skip; 2451 len -= skip; 2452 skip = 0; 2453 next = pmap_kextract(va); 2454 nsegs += sglist_count((void *)(uintptr_t)va, len); 2455 if (lastb + 1 == next) 2456 nsegs--; 2457 lastb = pmap_kextract(va + len - 1); 2458 } 2459 2460 return (nsegs); 2461 } 2462 2463 /* 2464 * Analyze the mbuf to determine its tx needs. The mbuf passed in may change: 2465 * a) caller can assume it's been freed if this function returns with an error. 2466 * b) it may get defragged up if the gather list is too long for the hardware. 2467 */ 2468 int 2469 parse_pkt(struct adapter *sc, struct mbuf **mp) 2470 { 2471 struct mbuf *m0 = *mp, *m; 2472 int rc, nsegs, defragged = 0, offset; 2473 struct ether_header *eh; 2474 void *l3hdr; 2475 #if defined(INET) || defined(INET6) 2476 struct tcphdr *tcp; 2477 #endif 2478 uint16_t eh_type; 2479 2480 M_ASSERTPKTHDR(m0); 2481 if (__predict_false(m0->m_pkthdr.len < ETHER_HDR_LEN)) { 2482 rc = EINVAL; 2483 fail: 2484 m_freem(m0); 2485 *mp = NULL; 2486 return (rc); 2487 } 2488 restart: 2489 /* 2490 * First count the number of gather list segments in the payload. 2491 * Defrag the mbuf if nsegs exceeds the hardware limit. 2492 */ 2493 M_ASSERTPKTHDR(m0); 2494 MPASS(m0->m_pkthdr.len > 0); 2495 nsegs = count_mbuf_nsegs(m0, 0); 2496 if (nsegs > (needs_tso(m0) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS)) { 2497 if (defragged++ > 0 || (m = m_defrag(m0, M_NOWAIT)) == NULL) { 2498 rc = EFBIG; 2499 goto fail; 2500 } 2501 *mp = m0 = m; /* update caller's copy after defrag */ 2502 goto restart; 2503 } 2504 2505 if (__predict_false(nsegs > 2 && m0->m_pkthdr.len <= MHLEN)) { 2506 m0 = m_pullup(m0, m0->m_pkthdr.len); 2507 if (m0 == NULL) { 2508 /* Should have left well enough alone. */ 2509 rc = EFBIG; 2510 goto fail; 2511 } 2512 *mp = m0; /* update caller's copy after pullup */ 2513 goto restart; 2514 } 2515 set_mbuf_nsegs(m0, nsegs); 2516 set_mbuf_cflags(m0, 0); 2517 if (sc->flags & IS_VF) 2518 set_mbuf_len16(m0, txpkt_vm_len16(nsegs, needs_tso(m0))); 2519 else 2520 set_mbuf_len16(m0, txpkt_len16(nsegs, needs_tso(m0))); 2521 2522 #ifdef RATELIMIT 2523 /* 2524 * Ethofld is limited to TCP and UDP for now, and only when L4 hw 2525 * checksumming is enabled. needs_l4_csum happens to check for all the 2526 * right things. 2527 */ 2528 if (__predict_false(needs_eo(m0) && !needs_l4_csum(m0))) 2529 m0->m_pkthdr.snd_tag = NULL; 2530 #endif 2531 2532 if (!needs_tso(m0) && 2533 #ifdef RATELIMIT 2534 !needs_eo(m0) && 2535 #endif 2536 !(sc->flags & IS_VF && (needs_l3_csum(m0) || needs_l4_csum(m0)))) 2537 return (0); 2538 2539 m = m0; 2540 eh = mtod(m, struct ether_header *); 2541 eh_type = ntohs(eh->ether_type); 2542 if (eh_type == ETHERTYPE_VLAN) { 2543 struct ether_vlan_header *evh = (void *)eh; 2544 2545 eh_type = ntohs(evh->evl_proto); 2546 m0->m_pkthdr.l2hlen = sizeof(*evh); 2547 } else 2548 m0->m_pkthdr.l2hlen = sizeof(*eh); 2549 2550 offset = 0; 2551 l3hdr = m_advance(&m, &offset, m0->m_pkthdr.l2hlen); 2552 2553 switch (eh_type) { 2554 #ifdef INET6 2555 case ETHERTYPE_IPV6: 2556 { 2557 struct ip6_hdr *ip6 = l3hdr; 2558 2559 MPASS(!needs_tso(m0) || ip6->ip6_nxt == IPPROTO_TCP); 2560 2561 m0->m_pkthdr.l3hlen = sizeof(*ip6); 2562 break; 2563 } 2564 #endif 2565 #ifdef INET 2566 case ETHERTYPE_IP: 2567 { 2568 struct ip *ip = l3hdr; 2569 2570 m0->m_pkthdr.l3hlen = ip->ip_hl * 4; 2571 break; 2572 } 2573 #endif 2574 default: 2575 panic("%s: ethertype 0x%04x unknown. if_cxgbe must be compiled" 2576 " with the same INET/INET6 options as the kernel.", 2577 __func__, eh_type); 2578 } 2579 2580 #if defined(INET) || defined(INET6) 2581 if (needs_tcp_csum(m0)) { 2582 tcp = m_advance(&m, &offset, m0->m_pkthdr.l3hlen); 2583 m0->m_pkthdr.l4hlen = tcp->th_off * 4; 2584 #ifdef RATELIMIT 2585 if (tsclk >= 0 && *(uint32_t *)(tcp + 1) == ntohl(0x0101080a)) { 2586 set_mbuf_eo_tsclk_tsoff(m0, 2587 V_FW_ETH_TX_EO_WR_TSCLK(tsclk) | 2588 V_FW_ETH_TX_EO_WR_TSOFF(sizeof(*tcp) / 2 + 1)); 2589 } else 2590 set_mbuf_eo_tsclk_tsoff(m0, 0); 2591 } else if (needs_udp_csum(m)) { 2592 m0->m_pkthdr.l4hlen = sizeof(struct udphdr); 2593 #endif 2594 } 2595 #ifdef RATELIMIT 2596 if (needs_eo(m0)) { 2597 u_int immhdrs; 2598 2599 /* EO WRs have the headers in the WR and not the GL. */ 2600 immhdrs = m0->m_pkthdr.l2hlen + m0->m_pkthdr.l3hlen + 2601 m0->m_pkthdr.l4hlen; 2602 nsegs = count_mbuf_nsegs(m0, immhdrs); 2603 set_mbuf_eo_nsegs(m0, nsegs); 2604 set_mbuf_eo_len16(m0, 2605 txpkt_eo_len16(nsegs, immhdrs, needs_tso(m0))); 2606 } 2607 #endif 2608 #endif 2609 MPASS(m0 == *mp); 2610 return (0); 2611 } 2612 2613 void * 2614 start_wrq_wr(struct sge_wrq *wrq, int len16, struct wrq_cookie *cookie) 2615 { 2616 struct sge_eq *eq = &wrq->eq; 2617 struct adapter *sc = wrq->adapter; 2618 int ndesc, available; 2619 struct wrqe *wr; 2620 void *w; 2621 2622 MPASS(len16 > 0); 2623 ndesc = howmany(len16, EQ_ESIZE / 16); 2624 MPASS(ndesc > 0 && ndesc <= SGE_MAX_WR_NDESC); 2625 2626 EQ_LOCK(eq); 2627 2628 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 2629 drain_wrq_wr_list(sc, wrq); 2630 2631 if (!STAILQ_EMPTY(&wrq->wr_list)) { 2632 slowpath: 2633 EQ_UNLOCK(eq); 2634 wr = alloc_wrqe(len16 * 16, wrq); 2635 if (__predict_false(wr == NULL)) 2636 return (NULL); 2637 cookie->pidx = -1; 2638 cookie->ndesc = ndesc; 2639 return (&wr->wr); 2640 } 2641 2642 eq->cidx = read_hw_cidx(eq); 2643 if (eq->pidx == eq->cidx) 2644 available = eq->sidx - 1; 2645 else 2646 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2647 if (available < ndesc) 2648 goto slowpath; 2649 2650 cookie->pidx = eq->pidx; 2651 cookie->ndesc = ndesc; 2652 TAILQ_INSERT_TAIL(&wrq->incomplete_wrs, cookie, link); 2653 2654 w = &eq->desc[eq->pidx]; 2655 IDXINCR(eq->pidx, ndesc, eq->sidx); 2656 if (__predict_false(cookie->pidx + ndesc > eq->sidx)) { 2657 w = &wrq->ss[0]; 2658 wrq->ss_pidx = cookie->pidx; 2659 wrq->ss_len = len16 * 16; 2660 } 2661 2662 EQ_UNLOCK(eq); 2663 2664 return (w); 2665 } 2666 2667 void 2668 commit_wrq_wr(struct sge_wrq *wrq, void *w, struct wrq_cookie *cookie) 2669 { 2670 struct sge_eq *eq = &wrq->eq; 2671 struct adapter *sc = wrq->adapter; 2672 int ndesc, pidx; 2673 struct wrq_cookie *prev, *next; 2674 2675 if (cookie->pidx == -1) { 2676 struct wrqe *wr = __containerof(w, struct wrqe, wr); 2677 2678 t4_wrq_tx(sc, wr); 2679 return; 2680 } 2681 2682 if (__predict_false(w == &wrq->ss[0])) { 2683 int n = (eq->sidx - wrq->ss_pidx) * EQ_ESIZE; 2684 2685 MPASS(wrq->ss_len > n); /* WR had better wrap around. */ 2686 bcopy(&wrq->ss[0], &eq->desc[wrq->ss_pidx], n); 2687 bcopy(&wrq->ss[n], &eq->desc[0], wrq->ss_len - n); 2688 wrq->tx_wrs_ss++; 2689 } else 2690 wrq->tx_wrs_direct++; 2691 2692 EQ_LOCK(eq); 2693 ndesc = cookie->ndesc; /* Can be more than SGE_MAX_WR_NDESC here. */ 2694 pidx = cookie->pidx; 2695 MPASS(pidx >= 0 && pidx < eq->sidx); 2696 prev = TAILQ_PREV(cookie, wrq_incomplete_wrs, link); 2697 next = TAILQ_NEXT(cookie, link); 2698 if (prev == NULL) { 2699 MPASS(pidx == eq->dbidx); 2700 if (next == NULL || ndesc >= 16) { 2701 int available; 2702 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */ 2703 2704 /* 2705 * Note that the WR via which we'll request tx updates 2706 * is at pidx and not eq->pidx, which has moved on 2707 * already. 2708 */ 2709 dst = (void *)&eq->desc[pidx]; 2710 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2711 if (available < eq->sidx / 4 && 2712 atomic_cmpset_int(&eq->equiq, 0, 1)) { 2713 /* 2714 * XXX: This is not 100% reliable with some 2715 * types of WRs. But this is a very unusual 2716 * situation for an ofld/ctrl queue anyway. 2717 */ 2718 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ | 2719 F_FW_WR_EQUEQ); 2720 } 2721 2722 ring_eq_db(wrq->adapter, eq, ndesc); 2723 } else { 2724 MPASS(IDXDIFF(next->pidx, pidx, eq->sidx) == ndesc); 2725 next->pidx = pidx; 2726 next->ndesc += ndesc; 2727 } 2728 } else { 2729 MPASS(IDXDIFF(pidx, prev->pidx, eq->sidx) == prev->ndesc); 2730 prev->ndesc += ndesc; 2731 } 2732 TAILQ_REMOVE(&wrq->incomplete_wrs, cookie, link); 2733 2734 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 2735 drain_wrq_wr_list(sc, wrq); 2736 2737 #ifdef INVARIANTS 2738 if (TAILQ_EMPTY(&wrq->incomplete_wrs)) { 2739 /* Doorbell must have caught up to the pidx. */ 2740 MPASS(wrq->eq.pidx == wrq->eq.dbidx); 2741 } 2742 #endif 2743 EQ_UNLOCK(eq); 2744 } 2745 2746 static u_int 2747 can_resume_eth_tx(struct mp_ring *r) 2748 { 2749 struct sge_eq *eq = r->cookie; 2750 2751 return (total_available_tx_desc(eq) > eq->sidx / 8); 2752 } 2753 2754 static inline int 2755 cannot_use_txpkts(struct mbuf *m) 2756 { 2757 /* maybe put a GL limit too, to avoid silliness? */ 2758 2759 return (needs_tso(m) || (mbuf_cflags(m) & MC_RAW_WR) != 0); 2760 } 2761 2762 static inline int 2763 discard_tx(struct sge_eq *eq) 2764 { 2765 2766 return ((eq->flags & (EQ_ENABLED | EQ_QFLUSH)) != EQ_ENABLED); 2767 } 2768 2769 static inline int 2770 wr_can_update_eq(struct fw_eth_tx_pkts_wr *wr) 2771 { 2772 2773 switch (G_FW_WR_OP(be32toh(wr->op_pkd))) { 2774 case FW_ULPTX_WR: 2775 case FW_ETH_TX_PKT_WR: 2776 case FW_ETH_TX_PKTS_WR: 2777 case FW_ETH_TX_PKT_VM_WR: 2778 return (1); 2779 default: 2780 return (0); 2781 } 2782 } 2783 2784 /* 2785 * r->items[cidx] to r->items[pidx], with a wraparound at r->size, are ready to 2786 * be consumed. Return the actual number consumed. 0 indicates a stall. 2787 */ 2788 static u_int 2789 eth_tx(struct mp_ring *r, u_int cidx, u_int pidx) 2790 { 2791 struct sge_txq *txq = r->cookie; 2792 struct sge_eq *eq = &txq->eq; 2793 struct ifnet *ifp = txq->ifp; 2794 struct vi_info *vi = ifp->if_softc; 2795 struct port_info *pi = vi->pi; 2796 struct adapter *sc = pi->adapter; 2797 u_int total, remaining; /* # of packets */ 2798 u_int available, dbdiff; /* # of hardware descriptors */ 2799 u_int n, next_cidx; 2800 struct mbuf *m0, *tail; 2801 struct txpkts txp; 2802 struct fw_eth_tx_pkts_wr *wr; /* any fw WR struct will do */ 2803 2804 remaining = IDXDIFF(pidx, cidx, r->size); 2805 MPASS(remaining > 0); /* Must not be called without work to do. */ 2806 total = 0; 2807 2808 TXQ_LOCK(txq); 2809 if (__predict_false(discard_tx(eq))) { 2810 while (cidx != pidx) { 2811 m0 = r->items[cidx]; 2812 m_freem(m0); 2813 if (++cidx == r->size) 2814 cidx = 0; 2815 } 2816 reclaim_tx_descs(txq, 2048); 2817 total = remaining; 2818 goto done; 2819 } 2820 2821 /* How many hardware descriptors do we have readily available. */ 2822 if (eq->pidx == eq->cidx) 2823 available = eq->sidx - 1; 2824 else 2825 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2826 dbdiff = IDXDIFF(eq->pidx, eq->dbidx, eq->sidx); 2827 2828 while (remaining > 0) { 2829 2830 m0 = r->items[cidx]; 2831 M_ASSERTPKTHDR(m0); 2832 MPASS(m0->m_nextpkt == NULL); 2833 2834 if (available < SGE_MAX_WR_NDESC) { 2835 available += reclaim_tx_descs(txq, 64); 2836 if (available < howmany(mbuf_len16(m0), EQ_ESIZE / 16)) 2837 break; /* out of descriptors */ 2838 } 2839 2840 next_cidx = cidx + 1; 2841 if (__predict_false(next_cidx == r->size)) 2842 next_cidx = 0; 2843 2844 wr = (void *)&eq->desc[eq->pidx]; 2845 if (sc->flags & IS_VF) { 2846 total++; 2847 remaining--; 2848 ETHER_BPF_MTAP(ifp, m0); 2849 n = write_txpkt_vm_wr(sc, txq, (void *)wr, m0, 2850 available); 2851 } else if (remaining > 1 && 2852 try_txpkts(m0, r->items[next_cidx], &txp, available) == 0) { 2853 2854 /* pkts at cidx, next_cidx should both be in txp. */ 2855 MPASS(txp.npkt == 2); 2856 tail = r->items[next_cidx]; 2857 MPASS(tail->m_nextpkt == NULL); 2858 ETHER_BPF_MTAP(ifp, m0); 2859 ETHER_BPF_MTAP(ifp, tail); 2860 m0->m_nextpkt = tail; 2861 2862 if (__predict_false(++next_cidx == r->size)) 2863 next_cidx = 0; 2864 2865 while (next_cidx != pidx) { 2866 if (add_to_txpkts(r->items[next_cidx], &txp, 2867 available) != 0) 2868 break; 2869 tail->m_nextpkt = r->items[next_cidx]; 2870 tail = tail->m_nextpkt; 2871 ETHER_BPF_MTAP(ifp, tail); 2872 if (__predict_false(++next_cidx == r->size)) 2873 next_cidx = 0; 2874 } 2875 2876 n = write_txpkts_wr(txq, wr, m0, &txp, available); 2877 total += txp.npkt; 2878 remaining -= txp.npkt; 2879 } else if (mbuf_cflags(m0) & MC_RAW_WR) { 2880 total++; 2881 remaining--; 2882 n = write_raw_wr(txq, (void *)wr, m0, available); 2883 } else { 2884 total++; 2885 remaining--; 2886 ETHER_BPF_MTAP(ifp, m0); 2887 n = write_txpkt_wr(txq, (void *)wr, m0, available); 2888 } 2889 MPASS(n >= 1 && n <= available && n <= SGE_MAX_WR_NDESC); 2890 2891 available -= n; 2892 dbdiff += n; 2893 IDXINCR(eq->pidx, n, eq->sidx); 2894 2895 if (wr_can_update_eq(wr)) { 2896 if (total_available_tx_desc(eq) < eq->sidx / 4 && 2897 atomic_cmpset_int(&eq->equiq, 0, 1)) { 2898 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ | 2899 F_FW_WR_EQUEQ); 2900 eq->equeqidx = eq->pidx; 2901 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 2902 32) { 2903 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ); 2904 eq->equeqidx = eq->pidx; 2905 } 2906 } 2907 2908 if (dbdiff >= 16 && remaining >= 4) { 2909 ring_eq_db(sc, eq, dbdiff); 2910 available += reclaim_tx_descs(txq, 4 * dbdiff); 2911 dbdiff = 0; 2912 } 2913 2914 cidx = next_cidx; 2915 } 2916 if (dbdiff != 0) { 2917 ring_eq_db(sc, eq, dbdiff); 2918 reclaim_tx_descs(txq, 32); 2919 } 2920 done: 2921 TXQ_UNLOCK(txq); 2922 2923 return (total); 2924 } 2925 2926 static inline void 2927 init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int pktc_idx, 2928 int qsize) 2929 { 2930 2931 KASSERT(tmr_idx >= 0 && tmr_idx < SGE_NTIMERS, 2932 ("%s: bad tmr_idx %d", __func__, tmr_idx)); 2933 KASSERT(pktc_idx < SGE_NCOUNTERS, /* -ve is ok, means don't use */ 2934 ("%s: bad pktc_idx %d", __func__, pktc_idx)); 2935 2936 iq->flags = 0; 2937 iq->adapter = sc; 2938 iq->intr_params = V_QINTR_TIMER_IDX(tmr_idx); 2939 iq->intr_pktc_idx = SGE_NCOUNTERS - 1; 2940 if (pktc_idx >= 0) { 2941 iq->intr_params |= F_QINTR_CNT_EN; 2942 iq->intr_pktc_idx = pktc_idx; 2943 } 2944 iq->qsize = roundup2(qsize, 16); /* See FW_IQ_CMD/iqsize */ 2945 iq->sidx = iq->qsize - sc->params.sge.spg_len / IQ_ESIZE; 2946 } 2947 2948 static inline void 2949 init_fl(struct adapter *sc, struct sge_fl *fl, int qsize, int maxp, char *name) 2950 { 2951 2952 fl->qsize = qsize; 2953 fl->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE; 2954 strlcpy(fl->lockname, name, sizeof(fl->lockname)); 2955 if (sc->flags & BUF_PACKING_OK && 2956 ((!is_t4(sc) && buffer_packing) || /* T5+: enabled unless 0 */ 2957 (is_t4(sc) && buffer_packing == 1)))/* T4: disabled unless 1 */ 2958 fl->flags |= FL_BUF_PACKING; 2959 find_best_refill_source(sc, fl, maxp); 2960 find_safe_refill_source(sc, fl); 2961 } 2962 2963 static inline void 2964 init_eq(struct adapter *sc, struct sge_eq *eq, int eqtype, int qsize, 2965 uint8_t tx_chan, uint16_t iqid, char *name) 2966 { 2967 KASSERT(eqtype <= EQ_TYPEMASK, ("%s: bad qtype %d", __func__, eqtype)); 2968 2969 eq->flags = eqtype & EQ_TYPEMASK; 2970 eq->tx_chan = tx_chan; 2971 eq->iqid = iqid; 2972 eq->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE; 2973 strlcpy(eq->lockname, name, sizeof(eq->lockname)); 2974 } 2975 2976 static int 2977 alloc_ring(struct adapter *sc, size_t len, bus_dma_tag_t *tag, 2978 bus_dmamap_t *map, bus_addr_t *pa, void **va) 2979 { 2980 int rc; 2981 2982 rc = bus_dma_tag_create(sc->dmat, 512, 0, BUS_SPACE_MAXADDR, 2983 BUS_SPACE_MAXADDR, NULL, NULL, len, 1, len, 0, NULL, NULL, tag); 2984 if (rc != 0) { 2985 device_printf(sc->dev, "cannot allocate DMA tag: %d\n", rc); 2986 goto done; 2987 } 2988 2989 rc = bus_dmamem_alloc(*tag, va, 2990 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, map); 2991 if (rc != 0) { 2992 device_printf(sc->dev, "cannot allocate DMA memory: %d\n", rc); 2993 goto done; 2994 } 2995 2996 rc = bus_dmamap_load(*tag, *map, *va, len, oneseg_dma_callback, pa, 0); 2997 if (rc != 0) { 2998 device_printf(sc->dev, "cannot load DMA map: %d\n", rc); 2999 goto done; 3000 } 3001 done: 3002 if (rc) 3003 free_ring(sc, *tag, *map, *pa, *va); 3004 3005 return (rc); 3006 } 3007 3008 static int 3009 free_ring(struct adapter *sc, bus_dma_tag_t tag, bus_dmamap_t map, 3010 bus_addr_t pa, void *va) 3011 { 3012 if (pa) 3013 bus_dmamap_unload(tag, map); 3014 if (va) 3015 bus_dmamem_free(tag, va, map); 3016 if (tag) 3017 bus_dma_tag_destroy(tag); 3018 3019 return (0); 3020 } 3021 3022 /* 3023 * Allocates the ring for an ingress queue and an optional freelist. If the 3024 * freelist is specified it will be allocated and then associated with the 3025 * ingress queue. 3026 * 3027 * Returns errno on failure. Resources allocated up to that point may still be 3028 * allocated. Caller is responsible for cleanup in case this function fails. 3029 * 3030 * If the ingress queue will take interrupts directly then the intr_idx 3031 * specifies the vector, starting from 0. -1 means the interrupts for this 3032 * queue should be forwarded to the fwq. 3033 */ 3034 static int 3035 alloc_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl, 3036 int intr_idx, int cong) 3037 { 3038 int rc, i, cntxt_id; 3039 size_t len; 3040 struct fw_iq_cmd c; 3041 struct port_info *pi = vi->pi; 3042 struct adapter *sc = iq->adapter; 3043 struct sge_params *sp = &sc->params.sge; 3044 __be32 v = 0; 3045 3046 len = iq->qsize * IQ_ESIZE; 3047 rc = alloc_ring(sc, len, &iq->desc_tag, &iq->desc_map, &iq->ba, 3048 (void **)&iq->desc); 3049 if (rc != 0) 3050 return (rc); 3051 3052 bzero(&c, sizeof(c)); 3053 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 3054 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) | 3055 V_FW_IQ_CMD_VFN(0)); 3056 3057 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART | 3058 FW_LEN16(c)); 3059 3060 /* Special handling for firmware event queue */ 3061 if (iq == &sc->sge.fwq) 3062 v |= F_FW_IQ_CMD_IQASYNCH; 3063 3064 if (intr_idx < 0) { 3065 /* Forwarded interrupts, all headed to fwq */ 3066 v |= F_FW_IQ_CMD_IQANDST; 3067 v |= V_FW_IQ_CMD_IQANDSTINDEX(sc->sge.fwq.cntxt_id); 3068 } else { 3069 KASSERT(intr_idx < sc->intr_count, 3070 ("%s: invalid direct intr_idx %d", __func__, intr_idx)); 3071 v |= V_FW_IQ_CMD_IQANDSTINDEX(intr_idx); 3072 } 3073 3074 c.type_to_iqandstindex = htobe32(v | 3075 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) | 3076 V_FW_IQ_CMD_VIID(vi->viid) | 3077 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT)); 3078 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->tx_chan) | 3079 F_FW_IQ_CMD_IQGTSMODE | 3080 V_FW_IQ_CMD_IQINTCNTTHRESH(iq->intr_pktc_idx) | 3081 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4)); 3082 c.iqsize = htobe16(iq->qsize); 3083 c.iqaddr = htobe64(iq->ba); 3084 if (cong >= 0) 3085 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN); 3086 3087 if (fl) { 3088 mtx_init(&fl->fl_lock, fl->lockname, NULL, MTX_DEF); 3089 3090 len = fl->qsize * EQ_ESIZE; 3091 rc = alloc_ring(sc, len, &fl->desc_tag, &fl->desc_map, 3092 &fl->ba, (void **)&fl->desc); 3093 if (rc) 3094 return (rc); 3095 3096 /* Allocate space for one software descriptor per buffer. */ 3097 rc = alloc_fl_sdesc(fl); 3098 if (rc != 0) { 3099 device_printf(sc->dev, 3100 "failed to setup fl software descriptors: %d\n", 3101 rc); 3102 return (rc); 3103 } 3104 3105 if (fl->flags & FL_BUF_PACKING) { 3106 fl->lowat = roundup2(sp->fl_starve_threshold2, 8); 3107 fl->buf_boundary = sp->pack_boundary; 3108 } else { 3109 fl->lowat = roundup2(sp->fl_starve_threshold, 8); 3110 fl->buf_boundary = 16; 3111 } 3112 if (fl_pad && fl->buf_boundary < sp->pad_boundary) 3113 fl->buf_boundary = sp->pad_boundary; 3114 3115 c.iqns_to_fl0congen |= 3116 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) | 3117 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO | 3118 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) | 3119 (fl->flags & FL_BUF_PACKING ? F_FW_IQ_CMD_FL0PACKEN : 3120 0)); 3121 if (cong >= 0) { 3122 c.iqns_to_fl0congen |= 3123 htobe32(V_FW_IQ_CMD_FL0CNGCHMAP(cong) | 3124 F_FW_IQ_CMD_FL0CONGCIF | 3125 F_FW_IQ_CMD_FL0CONGEN); 3126 } 3127 c.fl0dcaen_to_fl0cidxfthresh = 3128 htobe16(V_FW_IQ_CMD_FL0FBMIN(chip_id(sc) <= CHELSIO_T5 ? 3129 X_FETCHBURSTMIN_128B : X_FETCHBURSTMIN_64B) | 3130 V_FW_IQ_CMD_FL0FBMAX(chip_id(sc) <= CHELSIO_T5 ? 3131 X_FETCHBURSTMAX_512B : X_FETCHBURSTMAX_256B)); 3132 c.fl0size = htobe16(fl->qsize); 3133 c.fl0addr = htobe64(fl->ba); 3134 } 3135 3136 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3137 if (rc != 0) { 3138 device_printf(sc->dev, 3139 "failed to create ingress queue: %d\n", rc); 3140 return (rc); 3141 } 3142 3143 iq->cidx = 0; 3144 iq->gen = F_RSPD_GEN; 3145 iq->intr_next = iq->intr_params; 3146 iq->cntxt_id = be16toh(c.iqid); 3147 iq->abs_id = be16toh(c.physiqid); 3148 iq->flags |= IQ_ALLOCATED; 3149 3150 cntxt_id = iq->cntxt_id - sc->sge.iq_start; 3151 if (cntxt_id >= sc->sge.niq) { 3152 panic ("%s: iq->cntxt_id (%d) more than the max (%d)", __func__, 3153 cntxt_id, sc->sge.niq - 1); 3154 } 3155 sc->sge.iqmap[cntxt_id] = iq; 3156 3157 if (fl) { 3158 u_int qid; 3159 3160 iq->flags |= IQ_HAS_FL; 3161 fl->cntxt_id = be16toh(c.fl0id); 3162 fl->pidx = fl->cidx = 0; 3163 3164 cntxt_id = fl->cntxt_id - sc->sge.eq_start; 3165 if (cntxt_id >= sc->sge.neq) { 3166 panic("%s: fl->cntxt_id (%d) more than the max (%d)", 3167 __func__, cntxt_id, sc->sge.neq - 1); 3168 } 3169 sc->sge.eqmap[cntxt_id] = (void *)fl; 3170 3171 qid = fl->cntxt_id; 3172 if (isset(&sc->doorbells, DOORBELL_UDB)) { 3173 uint32_t s_qpp = sc->params.sge.eq_s_qpp; 3174 uint32_t mask = (1 << s_qpp) - 1; 3175 volatile uint8_t *udb; 3176 3177 udb = sc->udbs_base + UDBS_DB_OFFSET; 3178 udb += (qid >> s_qpp) << PAGE_SHIFT; 3179 qid &= mask; 3180 if (qid < PAGE_SIZE / UDBS_SEG_SIZE) { 3181 udb += qid << UDBS_SEG_SHIFT; 3182 qid = 0; 3183 } 3184 fl->udb = (volatile void *)udb; 3185 } 3186 fl->dbval = V_QID(qid) | sc->chip_params->sge_fl_db; 3187 3188 FL_LOCK(fl); 3189 /* Enough to make sure the SGE doesn't think it's starved */ 3190 refill_fl(sc, fl, fl->lowat); 3191 FL_UNLOCK(fl); 3192 } 3193 3194 if (chip_id(sc) >= CHELSIO_T5 && !(sc->flags & IS_VF) && cong >= 0) { 3195 uint32_t param, val; 3196 3197 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 3198 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) | 3199 V_FW_PARAMS_PARAM_YZ(iq->cntxt_id); 3200 if (cong == 0) 3201 val = 1 << 19; 3202 else { 3203 val = 2 << 19; 3204 for (i = 0; i < 4; i++) { 3205 if (cong & (1 << i)) 3206 val |= 1 << (i << 2); 3207 } 3208 } 3209 3210 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 3211 if (rc != 0) { 3212 /* report error but carry on */ 3213 device_printf(sc->dev, 3214 "failed to set congestion manager context for " 3215 "ingress queue %d: %d\n", iq->cntxt_id, rc); 3216 } 3217 } 3218 3219 /* Enable IQ interrupts */ 3220 atomic_store_rel_int(&iq->state, IQS_IDLE); 3221 t4_write_reg(sc, sc->sge_gts_reg, V_SEINTARM(iq->intr_params) | 3222 V_INGRESSQID(iq->cntxt_id)); 3223 3224 return (0); 3225 } 3226 3227 static int 3228 free_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl) 3229 { 3230 int rc; 3231 struct adapter *sc = iq->adapter; 3232 device_t dev; 3233 3234 if (sc == NULL) 3235 return (0); /* nothing to do */ 3236 3237 dev = vi ? vi->dev : sc->dev; 3238 3239 if (iq->flags & IQ_ALLOCATED) { 3240 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0, 3241 FW_IQ_TYPE_FL_INT_CAP, iq->cntxt_id, 3242 fl ? fl->cntxt_id : 0xffff, 0xffff); 3243 if (rc != 0) { 3244 device_printf(dev, 3245 "failed to free queue %p: %d\n", iq, rc); 3246 return (rc); 3247 } 3248 iq->flags &= ~IQ_ALLOCATED; 3249 } 3250 3251 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, iq->desc); 3252 3253 bzero(iq, sizeof(*iq)); 3254 3255 if (fl) { 3256 free_ring(sc, fl->desc_tag, fl->desc_map, fl->ba, 3257 fl->desc); 3258 3259 if (fl->sdesc) 3260 free_fl_sdesc(sc, fl); 3261 3262 if (mtx_initialized(&fl->fl_lock)) 3263 mtx_destroy(&fl->fl_lock); 3264 3265 bzero(fl, sizeof(*fl)); 3266 } 3267 3268 return (0); 3269 } 3270 3271 static void 3272 add_iq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid, 3273 struct sge_iq *iq) 3274 { 3275 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3276 3277 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, &iq->ba, 3278 "bus address of descriptor ring"); 3279 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3280 iq->qsize * IQ_ESIZE, "descriptor ring size in bytes"); 3281 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "abs_id", 3282 CTLTYPE_INT | CTLFLAG_RD, &iq->abs_id, 0, sysctl_uint16, "I", 3283 "absolute id of the queue"); 3284 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 3285 CTLTYPE_INT | CTLFLAG_RD, &iq->cntxt_id, 0, sysctl_uint16, "I", 3286 "SGE context id of the queue"); 3287 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx", 3288 CTLTYPE_INT | CTLFLAG_RD, &iq->cidx, 0, sysctl_uint16, "I", 3289 "consumer index"); 3290 } 3291 3292 static void 3293 add_fl_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx, 3294 struct sysctl_oid *oid, struct sge_fl *fl) 3295 { 3296 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3297 3298 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL, 3299 "freelist"); 3300 children = SYSCTL_CHILDREN(oid); 3301 3302 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, 3303 &fl->ba, "bus address of descriptor ring"); 3304 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3305 fl->sidx * EQ_ESIZE + sc->params.sge.spg_len, 3306 "desc ring size in bytes"); 3307 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 3308 CTLTYPE_INT | CTLFLAG_RD, &fl->cntxt_id, 0, sysctl_uint16, "I", 3309 "SGE context id of the freelist"); 3310 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "padding", CTLFLAG_RD, NULL, 3311 fl_pad ? 1 : 0, "padding enabled"); 3312 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "packing", CTLFLAG_RD, NULL, 3313 fl->flags & FL_BUF_PACKING ? 1 : 0, "packing enabled"); 3314 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &fl->cidx, 3315 0, "consumer index"); 3316 if (fl->flags & FL_BUF_PACKING) { 3317 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rx_offset", 3318 CTLFLAG_RD, &fl->rx_offset, 0, "packing rx offset"); 3319 } 3320 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &fl->pidx, 3321 0, "producer index"); 3322 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_allocated", 3323 CTLFLAG_RD, &fl->mbuf_allocated, "# of mbuf allocated"); 3324 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_inlined", 3325 CTLFLAG_RD, &fl->mbuf_inlined, "# of mbuf inlined in clusters"); 3326 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_allocated", 3327 CTLFLAG_RD, &fl->cl_allocated, "# of clusters allocated"); 3328 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_recycled", 3329 CTLFLAG_RD, &fl->cl_recycled, "# of clusters recycled"); 3330 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_fast_recycled", 3331 CTLFLAG_RD, &fl->cl_fast_recycled, "# of clusters recycled (fast)"); 3332 } 3333 3334 static int 3335 alloc_fwq(struct adapter *sc) 3336 { 3337 int rc, intr_idx; 3338 struct sge_iq *fwq = &sc->sge.fwq; 3339 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev); 3340 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3341 3342 init_iq(fwq, sc, 0, 0, FW_IQ_QSIZE); 3343 if (sc->flags & IS_VF) 3344 intr_idx = 0; 3345 else 3346 intr_idx = sc->intr_count > 1 ? 1 : 0; 3347 rc = alloc_iq_fl(&sc->port[0]->vi[0], fwq, NULL, intr_idx, -1); 3348 if (rc != 0) { 3349 device_printf(sc->dev, 3350 "failed to create firmware event queue: %d\n", rc); 3351 return (rc); 3352 } 3353 3354 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "fwq", CTLFLAG_RD, 3355 NULL, "firmware event queue"); 3356 add_iq_sysctls(&sc->ctx, oid, fwq); 3357 3358 return (0); 3359 } 3360 3361 static int 3362 free_fwq(struct adapter *sc) 3363 { 3364 return free_iq_fl(NULL, &sc->sge.fwq, NULL); 3365 } 3366 3367 static int 3368 alloc_ctrlq(struct adapter *sc, struct sge_wrq *ctrlq, int idx, 3369 struct sysctl_oid *oid) 3370 { 3371 int rc; 3372 char name[16]; 3373 struct sysctl_oid_list *children; 3374 3375 snprintf(name, sizeof(name), "%s ctrlq%d", device_get_nameunit(sc->dev), 3376 idx); 3377 init_eq(sc, &ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE, sc->port[idx]->tx_chan, 3378 sc->sge.fwq.cntxt_id, name); 3379 3380 children = SYSCTL_CHILDREN(oid); 3381 snprintf(name, sizeof(name), "%d", idx); 3382 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, name, CTLFLAG_RD, 3383 NULL, "ctrl queue"); 3384 rc = alloc_wrq(sc, NULL, ctrlq, oid); 3385 3386 return (rc); 3387 } 3388 3389 int 3390 tnl_cong(struct port_info *pi, int drop) 3391 { 3392 3393 if (drop == -1) 3394 return (-1); 3395 else if (drop == 1) 3396 return (0); 3397 else 3398 return (pi->rx_e_chan_map); 3399 } 3400 3401 static int 3402 alloc_rxq(struct vi_info *vi, struct sge_rxq *rxq, int intr_idx, int idx, 3403 struct sysctl_oid *oid) 3404 { 3405 int rc; 3406 struct adapter *sc = vi->pi->adapter; 3407 struct sysctl_oid_list *children; 3408 char name[16]; 3409 3410 rc = alloc_iq_fl(vi, &rxq->iq, &rxq->fl, intr_idx, 3411 tnl_cong(vi->pi, cong_drop)); 3412 if (rc != 0) 3413 return (rc); 3414 3415 if (idx == 0) 3416 sc->sge.iq_base = rxq->iq.abs_id - rxq->iq.cntxt_id; 3417 else 3418 KASSERT(rxq->iq.cntxt_id + sc->sge.iq_base == rxq->iq.abs_id, 3419 ("iq_base mismatch")); 3420 KASSERT(sc->sge.iq_base == 0 || sc->flags & IS_VF, 3421 ("PF with non-zero iq_base")); 3422 3423 /* 3424 * The freelist is just barely above the starvation threshold right now, 3425 * fill it up a bit more. 3426 */ 3427 FL_LOCK(&rxq->fl); 3428 refill_fl(sc, &rxq->fl, 128); 3429 FL_UNLOCK(&rxq->fl); 3430 3431 #if defined(INET) || defined(INET6) 3432 rc = tcp_lro_init_args(&rxq->lro, vi->ifp, lro_entries, lro_mbufs); 3433 if (rc != 0) 3434 return (rc); 3435 MPASS(rxq->lro.ifp == vi->ifp); /* also indicates LRO init'ed */ 3436 3437 if (vi->ifp->if_capenable & IFCAP_LRO) 3438 rxq->iq.flags |= IQ_LRO_ENABLED; 3439 #endif 3440 if (vi->ifp->if_capenable & IFCAP_HWRXTSTMP) 3441 rxq->iq.flags |= IQ_RX_TIMESTAMP; 3442 rxq->ifp = vi->ifp; 3443 3444 children = SYSCTL_CHILDREN(oid); 3445 3446 snprintf(name, sizeof(name), "%d", idx); 3447 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 3448 NULL, "rx queue"); 3449 children = SYSCTL_CHILDREN(oid); 3450 3451 add_iq_sysctls(&vi->ctx, oid, &rxq->iq); 3452 #if defined(INET) || defined(INET6) 3453 SYSCTL_ADD_U64(&vi->ctx, children, OID_AUTO, "lro_queued", CTLFLAG_RD, 3454 &rxq->lro.lro_queued, 0, NULL); 3455 SYSCTL_ADD_U64(&vi->ctx, children, OID_AUTO, "lro_flushed", CTLFLAG_RD, 3456 &rxq->lro.lro_flushed, 0, NULL); 3457 #endif 3458 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "rxcsum", CTLFLAG_RD, 3459 &rxq->rxcsum, "# of times hardware assisted with checksum"); 3460 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_extraction", 3461 CTLFLAG_RD, &rxq->vlan_extraction, 3462 "# of times hardware extracted 802.1Q tag"); 3463 3464 add_fl_sysctls(sc, &vi->ctx, oid, &rxq->fl); 3465 3466 return (rc); 3467 } 3468 3469 static int 3470 free_rxq(struct vi_info *vi, struct sge_rxq *rxq) 3471 { 3472 int rc; 3473 3474 #if defined(INET) || defined(INET6) 3475 if (rxq->lro.ifp) { 3476 tcp_lro_free(&rxq->lro); 3477 rxq->lro.ifp = NULL; 3478 } 3479 #endif 3480 3481 rc = free_iq_fl(vi, &rxq->iq, &rxq->fl); 3482 if (rc == 0) 3483 bzero(rxq, sizeof(*rxq)); 3484 3485 return (rc); 3486 } 3487 3488 #ifdef TCP_OFFLOAD 3489 static int 3490 alloc_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq, 3491 int intr_idx, int idx, struct sysctl_oid *oid) 3492 { 3493 struct port_info *pi = vi->pi; 3494 int rc; 3495 struct sysctl_oid_list *children; 3496 char name[16]; 3497 3498 rc = alloc_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl, intr_idx, 0); 3499 if (rc != 0) 3500 return (rc); 3501 3502 children = SYSCTL_CHILDREN(oid); 3503 3504 snprintf(name, sizeof(name), "%d", idx); 3505 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 3506 NULL, "rx queue"); 3507 add_iq_sysctls(&vi->ctx, oid, &ofld_rxq->iq); 3508 add_fl_sysctls(pi->adapter, &vi->ctx, oid, &ofld_rxq->fl); 3509 3510 return (rc); 3511 } 3512 3513 static int 3514 free_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq) 3515 { 3516 int rc; 3517 3518 rc = free_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl); 3519 if (rc == 0) 3520 bzero(ofld_rxq, sizeof(*ofld_rxq)); 3521 3522 return (rc); 3523 } 3524 #endif 3525 3526 #ifdef DEV_NETMAP 3527 static int 3528 alloc_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq, int intr_idx, 3529 int idx, struct sysctl_oid *oid) 3530 { 3531 int rc; 3532 struct sysctl_oid_list *children; 3533 struct sysctl_ctx_list *ctx; 3534 char name[16]; 3535 size_t len; 3536 struct adapter *sc = vi->pi->adapter; 3537 struct netmap_adapter *na = NA(vi->ifp); 3538 3539 MPASS(na != NULL); 3540 3541 len = vi->qsize_rxq * IQ_ESIZE; 3542 rc = alloc_ring(sc, len, &nm_rxq->iq_desc_tag, &nm_rxq->iq_desc_map, 3543 &nm_rxq->iq_ba, (void **)&nm_rxq->iq_desc); 3544 if (rc != 0) 3545 return (rc); 3546 3547 len = na->num_rx_desc * EQ_ESIZE + sc->params.sge.spg_len; 3548 rc = alloc_ring(sc, len, &nm_rxq->fl_desc_tag, &nm_rxq->fl_desc_map, 3549 &nm_rxq->fl_ba, (void **)&nm_rxq->fl_desc); 3550 if (rc != 0) 3551 return (rc); 3552 3553 nm_rxq->vi = vi; 3554 nm_rxq->nid = idx; 3555 nm_rxq->iq_cidx = 0; 3556 nm_rxq->iq_sidx = vi->qsize_rxq - sc->params.sge.spg_len / IQ_ESIZE; 3557 nm_rxq->iq_gen = F_RSPD_GEN; 3558 nm_rxq->fl_pidx = nm_rxq->fl_cidx = 0; 3559 nm_rxq->fl_sidx = na->num_rx_desc; 3560 nm_rxq->intr_idx = intr_idx; 3561 nm_rxq->iq_cntxt_id = INVALID_NM_RXQ_CNTXT_ID; 3562 3563 ctx = &vi->ctx; 3564 children = SYSCTL_CHILDREN(oid); 3565 3566 snprintf(name, sizeof(name), "%d", idx); 3567 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, name, CTLFLAG_RD, NULL, 3568 "rx queue"); 3569 children = SYSCTL_CHILDREN(oid); 3570 3571 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "abs_id", 3572 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_abs_id, 0, sysctl_uint16, 3573 "I", "absolute id of the queue"); 3574 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 3575 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cntxt_id, 0, sysctl_uint16, 3576 "I", "SGE context id of the queue"); 3577 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx", 3578 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cidx, 0, sysctl_uint16, "I", 3579 "consumer index"); 3580 3581 children = SYSCTL_CHILDREN(oid); 3582 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL, 3583 "freelist"); 3584 children = SYSCTL_CHILDREN(oid); 3585 3586 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 3587 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->fl_cntxt_id, 0, sysctl_uint16, 3588 "I", "SGE context id of the freelist"); 3589 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, 3590 &nm_rxq->fl_cidx, 0, "consumer index"); 3591 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, 3592 &nm_rxq->fl_pidx, 0, "producer index"); 3593 3594 return (rc); 3595 } 3596 3597 3598 static int 3599 free_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq) 3600 { 3601 struct adapter *sc = vi->pi->adapter; 3602 3603 if (vi->flags & VI_INIT_DONE) 3604 MPASS(nm_rxq->iq_cntxt_id == INVALID_NM_RXQ_CNTXT_ID); 3605 else 3606 MPASS(nm_rxq->iq_cntxt_id == 0); 3607 3608 free_ring(sc, nm_rxq->iq_desc_tag, nm_rxq->iq_desc_map, nm_rxq->iq_ba, 3609 nm_rxq->iq_desc); 3610 free_ring(sc, nm_rxq->fl_desc_tag, nm_rxq->fl_desc_map, nm_rxq->fl_ba, 3611 nm_rxq->fl_desc); 3612 3613 return (0); 3614 } 3615 3616 static int 3617 alloc_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq, int iqidx, int idx, 3618 struct sysctl_oid *oid) 3619 { 3620 int rc; 3621 size_t len; 3622 struct port_info *pi = vi->pi; 3623 struct adapter *sc = pi->adapter; 3624 struct netmap_adapter *na = NA(vi->ifp); 3625 char name[16]; 3626 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3627 3628 len = na->num_tx_desc * EQ_ESIZE + sc->params.sge.spg_len; 3629 rc = alloc_ring(sc, len, &nm_txq->desc_tag, &nm_txq->desc_map, 3630 &nm_txq->ba, (void **)&nm_txq->desc); 3631 if (rc) 3632 return (rc); 3633 3634 nm_txq->pidx = nm_txq->cidx = 0; 3635 nm_txq->sidx = na->num_tx_desc; 3636 nm_txq->nid = idx; 3637 nm_txq->iqidx = iqidx; 3638 nm_txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) | 3639 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(G_FW_VIID_PFN(vi->viid)) | 3640 V_TXPKT_VF(G_FW_VIID_VIN(vi->viid)) | 3641 V_TXPKT_VF_VLD(G_FW_VIID_VIVLD(vi->viid))); 3642 nm_txq->cntxt_id = INVALID_NM_TXQ_CNTXT_ID; 3643 3644 snprintf(name, sizeof(name), "%d", idx); 3645 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 3646 NULL, "netmap tx queue"); 3647 children = SYSCTL_CHILDREN(oid); 3648 3649 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 3650 &nm_txq->cntxt_id, 0, "SGE context id of the queue"); 3651 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx", 3652 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->cidx, 0, sysctl_uint16, "I", 3653 "consumer index"); 3654 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "pidx", 3655 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->pidx, 0, sysctl_uint16, "I", 3656 "producer index"); 3657 3658 return (rc); 3659 } 3660 3661 static int 3662 free_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq) 3663 { 3664 struct adapter *sc = vi->pi->adapter; 3665 3666 if (vi->flags & VI_INIT_DONE) 3667 MPASS(nm_txq->cntxt_id == INVALID_NM_TXQ_CNTXT_ID); 3668 else 3669 MPASS(nm_txq->cntxt_id == 0); 3670 3671 free_ring(sc, nm_txq->desc_tag, nm_txq->desc_map, nm_txq->ba, 3672 nm_txq->desc); 3673 3674 return (0); 3675 } 3676 #endif 3677 3678 /* 3679 * Returns a reasonable automatic cidx flush threshold for a given queue size. 3680 */ 3681 static u_int 3682 qsize_to_fthresh(int qsize) 3683 { 3684 u_int fthresh; 3685 3686 while (!powerof2(qsize)) 3687 qsize++; 3688 fthresh = ilog2(qsize); 3689 if (fthresh > X_CIDXFLUSHTHRESH_128) 3690 fthresh = X_CIDXFLUSHTHRESH_128; 3691 3692 return (fthresh); 3693 } 3694 3695 static int 3696 ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq) 3697 { 3698 int rc, cntxt_id; 3699 struct fw_eq_ctrl_cmd c; 3700 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 3701 3702 bzero(&c, sizeof(c)); 3703 3704 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | F_FW_CMD_REQUEST | 3705 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_CTRL_CMD_PFN(sc->pf) | 3706 V_FW_EQ_CTRL_CMD_VFN(0)); 3707 c.alloc_to_len16 = htobe32(F_FW_EQ_CTRL_CMD_ALLOC | 3708 F_FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c)); 3709 c.cmpliqid_eqid = htonl(V_FW_EQ_CTRL_CMD_CMPLIQID(eq->iqid)); 3710 c.physeqid_pkd = htobe32(0); 3711 c.fetchszm_to_iqid = 3712 htobe32(V_FW_EQ_CTRL_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 3713 V_FW_EQ_CTRL_CMD_PCIECHN(eq->tx_chan) | 3714 F_FW_EQ_CTRL_CMD_FETCHRO | V_FW_EQ_CTRL_CMD_IQID(eq->iqid)); 3715 c.dcaen_to_eqsize = 3716 htobe32(V_FW_EQ_CTRL_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 3717 V_FW_EQ_CTRL_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 3718 V_FW_EQ_CTRL_CMD_CIDXFTHRESH(qsize_to_fthresh(qsize)) | 3719 V_FW_EQ_CTRL_CMD_EQSIZE(qsize)); 3720 c.eqaddr = htobe64(eq->ba); 3721 3722 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3723 if (rc != 0) { 3724 device_printf(sc->dev, 3725 "failed to create control queue %d: %d\n", eq->tx_chan, rc); 3726 return (rc); 3727 } 3728 eq->flags |= EQ_ALLOCATED; 3729 3730 eq->cntxt_id = G_FW_EQ_CTRL_CMD_EQID(be32toh(c.cmpliqid_eqid)); 3731 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 3732 if (cntxt_id >= sc->sge.neq) 3733 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 3734 cntxt_id, sc->sge.neq - 1); 3735 sc->sge.eqmap[cntxt_id] = eq; 3736 3737 return (rc); 3738 } 3739 3740 static int 3741 eth_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 3742 { 3743 int rc, cntxt_id; 3744 struct fw_eq_eth_cmd c; 3745 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 3746 3747 bzero(&c, sizeof(c)); 3748 3749 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST | 3750 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) | 3751 V_FW_EQ_ETH_CMD_VFN(0)); 3752 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC | 3753 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c)); 3754 c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE | 3755 F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(vi->viid)); 3756 c.fetchszm_to_iqid = 3757 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) | 3758 V_FW_EQ_ETH_CMD_PCIECHN(eq->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO | 3759 V_FW_EQ_ETH_CMD_IQID(eq->iqid)); 3760 c.dcaen_to_eqsize = htobe32(V_FW_EQ_ETH_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 3761 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 3762 V_FW_EQ_ETH_CMD_EQSIZE(qsize)); 3763 c.eqaddr = htobe64(eq->ba); 3764 3765 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3766 if (rc != 0) { 3767 device_printf(vi->dev, 3768 "failed to create Ethernet egress queue: %d\n", rc); 3769 return (rc); 3770 } 3771 eq->flags |= EQ_ALLOCATED; 3772 3773 eq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd)); 3774 eq->abs_id = G_FW_EQ_ETH_CMD_PHYSEQID(be32toh(c.physeqid_pkd)); 3775 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 3776 if (cntxt_id >= sc->sge.neq) 3777 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 3778 cntxt_id, sc->sge.neq - 1); 3779 sc->sge.eqmap[cntxt_id] = eq; 3780 3781 return (rc); 3782 } 3783 3784 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 3785 static int 3786 ofld_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 3787 { 3788 int rc, cntxt_id; 3789 struct fw_eq_ofld_cmd c; 3790 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 3791 3792 bzero(&c, sizeof(c)); 3793 3794 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | F_FW_CMD_REQUEST | 3795 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_OFLD_CMD_PFN(sc->pf) | 3796 V_FW_EQ_OFLD_CMD_VFN(0)); 3797 c.alloc_to_len16 = htonl(F_FW_EQ_OFLD_CMD_ALLOC | 3798 F_FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c)); 3799 c.fetchszm_to_iqid = 3800 htonl(V_FW_EQ_OFLD_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 3801 V_FW_EQ_OFLD_CMD_PCIECHN(eq->tx_chan) | 3802 F_FW_EQ_OFLD_CMD_FETCHRO | V_FW_EQ_OFLD_CMD_IQID(eq->iqid)); 3803 c.dcaen_to_eqsize = 3804 htobe32(V_FW_EQ_OFLD_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 3805 V_FW_EQ_OFLD_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 3806 V_FW_EQ_OFLD_CMD_CIDXFTHRESH(qsize_to_fthresh(qsize)) | 3807 V_FW_EQ_OFLD_CMD_EQSIZE(qsize)); 3808 c.eqaddr = htobe64(eq->ba); 3809 3810 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3811 if (rc != 0) { 3812 device_printf(vi->dev, 3813 "failed to create egress queue for TCP offload: %d\n", rc); 3814 return (rc); 3815 } 3816 eq->flags |= EQ_ALLOCATED; 3817 3818 eq->cntxt_id = G_FW_EQ_OFLD_CMD_EQID(be32toh(c.eqid_pkd)); 3819 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 3820 if (cntxt_id >= sc->sge.neq) 3821 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 3822 cntxt_id, sc->sge.neq - 1); 3823 sc->sge.eqmap[cntxt_id] = eq; 3824 3825 return (rc); 3826 } 3827 #endif 3828 3829 static int 3830 alloc_eq(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 3831 { 3832 int rc, qsize; 3833 size_t len; 3834 3835 mtx_init(&eq->eq_lock, eq->lockname, NULL, MTX_DEF); 3836 3837 qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 3838 len = qsize * EQ_ESIZE; 3839 rc = alloc_ring(sc, len, &eq->desc_tag, &eq->desc_map, 3840 &eq->ba, (void **)&eq->desc); 3841 if (rc) 3842 return (rc); 3843 3844 eq->pidx = eq->cidx = eq->dbidx = 0; 3845 /* Note that equeqidx is not used with sge_wrq (OFLD/CTRL) queues. */ 3846 eq->equeqidx = 0; 3847 eq->doorbells = sc->doorbells; 3848 3849 switch (eq->flags & EQ_TYPEMASK) { 3850 case EQ_CTRL: 3851 rc = ctrl_eq_alloc(sc, eq); 3852 break; 3853 3854 case EQ_ETH: 3855 rc = eth_eq_alloc(sc, vi, eq); 3856 break; 3857 3858 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 3859 case EQ_OFLD: 3860 rc = ofld_eq_alloc(sc, vi, eq); 3861 break; 3862 #endif 3863 3864 default: 3865 panic("%s: invalid eq type %d.", __func__, 3866 eq->flags & EQ_TYPEMASK); 3867 } 3868 if (rc != 0) { 3869 device_printf(sc->dev, 3870 "failed to allocate egress queue(%d): %d\n", 3871 eq->flags & EQ_TYPEMASK, rc); 3872 } 3873 3874 if (isset(&eq->doorbells, DOORBELL_UDB) || 3875 isset(&eq->doorbells, DOORBELL_UDBWC) || 3876 isset(&eq->doorbells, DOORBELL_WCWR)) { 3877 uint32_t s_qpp = sc->params.sge.eq_s_qpp; 3878 uint32_t mask = (1 << s_qpp) - 1; 3879 volatile uint8_t *udb; 3880 3881 udb = sc->udbs_base + UDBS_DB_OFFSET; 3882 udb += (eq->cntxt_id >> s_qpp) << PAGE_SHIFT; /* pg offset */ 3883 eq->udb_qid = eq->cntxt_id & mask; /* id in page */ 3884 if (eq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE) 3885 clrbit(&eq->doorbells, DOORBELL_WCWR); 3886 else { 3887 udb += eq->udb_qid << UDBS_SEG_SHIFT; /* seg offset */ 3888 eq->udb_qid = 0; 3889 } 3890 eq->udb = (volatile void *)udb; 3891 } 3892 3893 return (rc); 3894 } 3895 3896 static int 3897 free_eq(struct adapter *sc, struct sge_eq *eq) 3898 { 3899 int rc; 3900 3901 if (eq->flags & EQ_ALLOCATED) { 3902 switch (eq->flags & EQ_TYPEMASK) { 3903 case EQ_CTRL: 3904 rc = -t4_ctrl_eq_free(sc, sc->mbox, sc->pf, 0, 3905 eq->cntxt_id); 3906 break; 3907 3908 case EQ_ETH: 3909 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0, 3910 eq->cntxt_id); 3911 break; 3912 3913 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 3914 case EQ_OFLD: 3915 rc = -t4_ofld_eq_free(sc, sc->mbox, sc->pf, 0, 3916 eq->cntxt_id); 3917 break; 3918 #endif 3919 3920 default: 3921 panic("%s: invalid eq type %d.", __func__, 3922 eq->flags & EQ_TYPEMASK); 3923 } 3924 if (rc != 0) { 3925 device_printf(sc->dev, 3926 "failed to free egress queue (%d): %d\n", 3927 eq->flags & EQ_TYPEMASK, rc); 3928 return (rc); 3929 } 3930 eq->flags &= ~EQ_ALLOCATED; 3931 } 3932 3933 free_ring(sc, eq->desc_tag, eq->desc_map, eq->ba, eq->desc); 3934 3935 if (mtx_initialized(&eq->eq_lock)) 3936 mtx_destroy(&eq->eq_lock); 3937 3938 bzero(eq, sizeof(*eq)); 3939 return (0); 3940 } 3941 3942 static int 3943 alloc_wrq(struct adapter *sc, struct vi_info *vi, struct sge_wrq *wrq, 3944 struct sysctl_oid *oid) 3945 { 3946 int rc; 3947 struct sysctl_ctx_list *ctx = vi ? &vi->ctx : &sc->ctx; 3948 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3949 3950 rc = alloc_eq(sc, vi, &wrq->eq); 3951 if (rc) 3952 return (rc); 3953 3954 wrq->adapter = sc; 3955 TASK_INIT(&wrq->wrq_tx_task, 0, wrq_tx_drain, wrq); 3956 TAILQ_INIT(&wrq->incomplete_wrs); 3957 STAILQ_INIT(&wrq->wr_list); 3958 wrq->nwr_pending = 0; 3959 wrq->ndesc_needed = 0; 3960 3961 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, 3962 &wrq->eq.ba, "bus address of descriptor ring"); 3963 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3964 wrq->eq.sidx * EQ_ESIZE + sc->params.sge.spg_len, 3965 "desc ring size in bytes"); 3966 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 3967 &wrq->eq.cntxt_id, 0, "SGE context id of the queue"); 3968 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx", 3969 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.cidx, 0, sysctl_uint16, "I", 3970 "consumer index"); 3971 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pidx", 3972 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.pidx, 0, sysctl_uint16, "I", 3973 "producer index"); 3974 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL, 3975 wrq->eq.sidx, "status page index"); 3976 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_direct", CTLFLAG_RD, 3977 &wrq->tx_wrs_direct, "# of work requests (direct)"); 3978 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_copied", CTLFLAG_RD, 3979 &wrq->tx_wrs_copied, "# of work requests (copied)"); 3980 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_sspace", CTLFLAG_RD, 3981 &wrq->tx_wrs_ss, "# of work requests (copied from scratch space)"); 3982 3983 return (rc); 3984 } 3985 3986 static int 3987 free_wrq(struct adapter *sc, struct sge_wrq *wrq) 3988 { 3989 int rc; 3990 3991 rc = free_eq(sc, &wrq->eq); 3992 if (rc) 3993 return (rc); 3994 3995 bzero(wrq, sizeof(*wrq)); 3996 return (0); 3997 } 3998 3999 static int 4000 alloc_txq(struct vi_info *vi, struct sge_txq *txq, int idx, 4001 struct sysctl_oid *oid) 4002 { 4003 int rc; 4004 struct port_info *pi = vi->pi; 4005 struct adapter *sc = pi->adapter; 4006 struct sge_eq *eq = &txq->eq; 4007 char name[16]; 4008 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 4009 4010 rc = mp_ring_alloc(&txq->r, eq->sidx, txq, eth_tx, can_resume_eth_tx, 4011 M_CXGBE, M_WAITOK); 4012 if (rc != 0) { 4013 device_printf(sc->dev, "failed to allocate mp_ring: %d\n", rc); 4014 return (rc); 4015 } 4016 4017 rc = alloc_eq(sc, vi, eq); 4018 if (rc != 0) { 4019 mp_ring_free(txq->r); 4020 txq->r = NULL; 4021 return (rc); 4022 } 4023 4024 /* Can't fail after this point. */ 4025 4026 if (idx == 0) 4027 sc->sge.eq_base = eq->abs_id - eq->cntxt_id; 4028 else 4029 KASSERT(eq->cntxt_id + sc->sge.eq_base == eq->abs_id, 4030 ("eq_base mismatch")); 4031 KASSERT(sc->sge.eq_base == 0 || sc->flags & IS_VF, 4032 ("PF with non-zero eq_base")); 4033 4034 TASK_INIT(&txq->tx_reclaim_task, 0, tx_reclaim, eq); 4035 txq->ifp = vi->ifp; 4036 txq->gl = sglist_alloc(TX_SGL_SEGS, M_WAITOK); 4037 if (sc->flags & IS_VF) 4038 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) | 4039 V_TXPKT_INTF(pi->tx_chan)); 4040 else 4041 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) | 4042 V_TXPKT_INTF(pi->tx_chan) | 4043 V_TXPKT_PF(G_FW_VIID_PFN(vi->viid)) | 4044 V_TXPKT_VF(G_FW_VIID_VIN(vi->viid)) | 4045 V_TXPKT_VF_VLD(G_FW_VIID_VIVLD(vi->viid))); 4046 txq->tc_idx = -1; 4047 txq->sdesc = malloc(eq->sidx * sizeof(struct tx_sdesc), M_CXGBE, 4048 M_ZERO | M_WAITOK); 4049 4050 snprintf(name, sizeof(name), "%d", idx); 4051 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 4052 NULL, "tx queue"); 4053 children = SYSCTL_CHILDREN(oid); 4054 4055 SYSCTL_ADD_UAUTO(&vi->ctx, children, OID_AUTO, "ba", CTLFLAG_RD, 4056 &eq->ba, "bus address of descriptor ring"); 4057 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 4058 eq->sidx * EQ_ESIZE + sc->params.sge.spg_len, 4059 "desc ring size in bytes"); 4060 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "abs_id", CTLFLAG_RD, 4061 &eq->abs_id, 0, "absolute id of the queue"); 4062 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 4063 &eq->cntxt_id, 0, "SGE context id of the queue"); 4064 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx", 4065 CTLTYPE_INT | CTLFLAG_RD, &eq->cidx, 0, sysctl_uint16, "I", 4066 "consumer index"); 4067 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "pidx", 4068 CTLTYPE_INT | CTLFLAG_RD, &eq->pidx, 0, sysctl_uint16, "I", 4069 "producer index"); 4070 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL, 4071 eq->sidx, "status page index"); 4072 4073 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "tc", 4074 CTLTYPE_INT | CTLFLAG_RW, vi, idx, sysctl_tc, "I", 4075 "traffic class (-1 means none)"); 4076 4077 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txcsum", CTLFLAG_RD, 4078 &txq->txcsum, "# of times hardware assisted with checksum"); 4079 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_insertion", 4080 CTLFLAG_RD, &txq->vlan_insertion, 4081 "# of times hardware inserted 802.1Q tag"); 4082 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "tso_wrs", CTLFLAG_RD, 4083 &txq->tso_wrs, "# of TSO work requests"); 4084 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "imm_wrs", CTLFLAG_RD, 4085 &txq->imm_wrs, "# of work requests with immediate data"); 4086 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "sgl_wrs", CTLFLAG_RD, 4087 &txq->sgl_wrs, "# of work requests with direct SGL"); 4088 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkt_wrs", CTLFLAG_RD, 4089 &txq->txpkt_wrs, "# of txpkt work requests (one pkt/WR)"); 4090 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_wrs", 4091 CTLFLAG_RD, &txq->txpkts0_wrs, 4092 "# of txpkts (type 0) work requests"); 4093 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_wrs", 4094 CTLFLAG_RD, &txq->txpkts1_wrs, 4095 "# of txpkts (type 1) work requests"); 4096 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_pkts", 4097 CTLFLAG_RD, &txq->txpkts0_pkts, 4098 "# of frames tx'd using type0 txpkts work requests"); 4099 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_pkts", 4100 CTLFLAG_RD, &txq->txpkts1_pkts, 4101 "# of frames tx'd using type1 txpkts work requests"); 4102 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "raw_wrs", CTLFLAG_RD, 4103 &txq->raw_wrs, "# of raw work requests (non-packets)"); 4104 4105 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_enqueues", 4106 CTLFLAG_RD, &txq->r->enqueues, 4107 "# of enqueues to the mp_ring for this queue"); 4108 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_drops", 4109 CTLFLAG_RD, &txq->r->drops, 4110 "# of drops in the mp_ring for this queue"); 4111 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_starts", 4112 CTLFLAG_RD, &txq->r->starts, 4113 "# of normal consumer starts in the mp_ring for this queue"); 4114 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_stalls", 4115 CTLFLAG_RD, &txq->r->stalls, 4116 "# of consumer stalls in the mp_ring for this queue"); 4117 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_restarts", 4118 CTLFLAG_RD, &txq->r->restarts, 4119 "# of consumer restarts in the mp_ring for this queue"); 4120 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_abdications", 4121 CTLFLAG_RD, &txq->r->abdications, 4122 "# of consumer abdications in the mp_ring for this queue"); 4123 4124 return (0); 4125 } 4126 4127 static int 4128 free_txq(struct vi_info *vi, struct sge_txq *txq) 4129 { 4130 int rc; 4131 struct adapter *sc = vi->pi->adapter; 4132 struct sge_eq *eq = &txq->eq; 4133 4134 rc = free_eq(sc, eq); 4135 if (rc) 4136 return (rc); 4137 4138 sglist_free(txq->gl); 4139 free(txq->sdesc, M_CXGBE); 4140 mp_ring_free(txq->r); 4141 4142 bzero(txq, sizeof(*txq)); 4143 return (0); 4144 } 4145 4146 static void 4147 oneseg_dma_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error) 4148 { 4149 bus_addr_t *ba = arg; 4150 4151 KASSERT(nseg == 1, 4152 ("%s meant for single segment mappings only.", __func__)); 4153 4154 *ba = error ? 0 : segs->ds_addr; 4155 } 4156 4157 static inline void 4158 ring_fl_db(struct adapter *sc, struct sge_fl *fl) 4159 { 4160 uint32_t n, v; 4161 4162 n = IDXDIFF(fl->pidx / 8, fl->dbidx, fl->sidx); 4163 MPASS(n > 0); 4164 4165 wmb(); 4166 v = fl->dbval | V_PIDX(n); 4167 if (fl->udb) 4168 *fl->udb = htole32(v); 4169 else 4170 t4_write_reg(sc, sc->sge_kdoorbell_reg, v); 4171 IDXINCR(fl->dbidx, n, fl->sidx); 4172 } 4173 4174 /* 4175 * Fills up the freelist by allocating up to 'n' buffers. Buffers that are 4176 * recycled do not count towards this allocation budget. 4177 * 4178 * Returns non-zero to indicate that this freelist should be added to the list 4179 * of starving freelists. 4180 */ 4181 static int 4182 refill_fl(struct adapter *sc, struct sge_fl *fl, int n) 4183 { 4184 __be64 *d; 4185 struct fl_sdesc *sd; 4186 uintptr_t pa; 4187 caddr_t cl; 4188 struct cluster_layout *cll; 4189 struct sw_zone_info *swz; 4190 struct cluster_metadata *clm; 4191 uint16_t max_pidx; 4192 uint16_t hw_cidx = fl->hw_cidx; /* stable snapshot */ 4193 4194 FL_LOCK_ASSERT_OWNED(fl); 4195 4196 /* 4197 * We always stop at the beginning of the hardware descriptor that's just 4198 * before the one with the hw cidx. This is to avoid hw pidx = hw cidx, 4199 * which would mean an empty freelist to the chip. 4200 */ 4201 max_pidx = __predict_false(hw_cidx == 0) ? fl->sidx - 1 : hw_cidx - 1; 4202 if (fl->pidx == max_pidx * 8) 4203 return (0); 4204 4205 d = &fl->desc[fl->pidx]; 4206 sd = &fl->sdesc[fl->pidx]; 4207 cll = &fl->cll_def; /* default layout */ 4208 swz = &sc->sge.sw_zone_info[cll->zidx]; 4209 4210 while (n > 0) { 4211 4212 if (sd->cl != NULL) { 4213 4214 if (sd->nmbuf == 0) { 4215 /* 4216 * Fast recycle without involving any atomics on 4217 * the cluster's metadata (if the cluster has 4218 * metadata). This happens when all frames 4219 * received in the cluster were small enough to 4220 * fit within a single mbuf each. 4221 */ 4222 fl->cl_fast_recycled++; 4223 #ifdef INVARIANTS 4224 clm = cl_metadata(sc, fl, &sd->cll, sd->cl); 4225 if (clm != NULL) 4226 MPASS(clm->refcount == 1); 4227 #endif 4228 goto recycled_fast; 4229 } 4230 4231 /* 4232 * Cluster is guaranteed to have metadata. Clusters 4233 * without metadata always take the fast recycle path 4234 * when they're recycled. 4235 */ 4236 clm = cl_metadata(sc, fl, &sd->cll, sd->cl); 4237 MPASS(clm != NULL); 4238 4239 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) { 4240 fl->cl_recycled++; 4241 counter_u64_add(extfree_rels, 1); 4242 goto recycled; 4243 } 4244 sd->cl = NULL; /* gave up my reference */ 4245 } 4246 MPASS(sd->cl == NULL); 4247 alloc: 4248 cl = uma_zalloc(swz->zone, M_NOWAIT); 4249 if (__predict_false(cl == NULL)) { 4250 if (cll == &fl->cll_alt || fl->cll_alt.zidx == -1 || 4251 fl->cll_def.zidx == fl->cll_alt.zidx) 4252 break; 4253 4254 /* fall back to the safe zone */ 4255 cll = &fl->cll_alt; 4256 swz = &sc->sge.sw_zone_info[cll->zidx]; 4257 goto alloc; 4258 } 4259 fl->cl_allocated++; 4260 n--; 4261 4262 pa = pmap_kextract((vm_offset_t)cl); 4263 pa += cll->region1; 4264 sd->cl = cl; 4265 sd->cll = *cll; 4266 *d = htobe64(pa | cll->hwidx); 4267 clm = cl_metadata(sc, fl, cll, cl); 4268 if (clm != NULL) { 4269 recycled: 4270 #ifdef INVARIANTS 4271 clm->sd = sd; 4272 #endif 4273 clm->refcount = 1; 4274 } 4275 sd->nmbuf = 0; 4276 recycled_fast: 4277 d++; 4278 sd++; 4279 if (__predict_false(++fl->pidx % 8 == 0)) { 4280 uint16_t pidx = fl->pidx / 8; 4281 4282 if (__predict_false(pidx == fl->sidx)) { 4283 fl->pidx = 0; 4284 pidx = 0; 4285 sd = fl->sdesc; 4286 d = fl->desc; 4287 } 4288 if (pidx == max_pidx) 4289 break; 4290 4291 if (IDXDIFF(pidx, fl->dbidx, fl->sidx) >= 4) 4292 ring_fl_db(sc, fl); 4293 } 4294 } 4295 4296 if (fl->pidx / 8 != fl->dbidx) 4297 ring_fl_db(sc, fl); 4298 4299 return (FL_RUNNING_LOW(fl) && !(fl->flags & FL_STARVING)); 4300 } 4301 4302 /* 4303 * Attempt to refill all starving freelists. 4304 */ 4305 static void 4306 refill_sfl(void *arg) 4307 { 4308 struct adapter *sc = arg; 4309 struct sge_fl *fl, *fl_temp; 4310 4311 mtx_assert(&sc->sfl_lock, MA_OWNED); 4312 TAILQ_FOREACH_SAFE(fl, &sc->sfl, link, fl_temp) { 4313 FL_LOCK(fl); 4314 refill_fl(sc, fl, 64); 4315 if (FL_NOT_RUNNING_LOW(fl) || fl->flags & FL_DOOMED) { 4316 TAILQ_REMOVE(&sc->sfl, fl, link); 4317 fl->flags &= ~FL_STARVING; 4318 } 4319 FL_UNLOCK(fl); 4320 } 4321 4322 if (!TAILQ_EMPTY(&sc->sfl)) 4323 callout_schedule(&sc->sfl_callout, hz / 5); 4324 } 4325 4326 static int 4327 alloc_fl_sdesc(struct sge_fl *fl) 4328 { 4329 4330 fl->sdesc = malloc(fl->sidx * 8 * sizeof(struct fl_sdesc), M_CXGBE, 4331 M_ZERO | M_WAITOK); 4332 4333 return (0); 4334 } 4335 4336 static void 4337 free_fl_sdesc(struct adapter *sc, struct sge_fl *fl) 4338 { 4339 struct fl_sdesc *sd; 4340 struct cluster_metadata *clm; 4341 struct cluster_layout *cll; 4342 int i; 4343 4344 sd = fl->sdesc; 4345 for (i = 0; i < fl->sidx * 8; i++, sd++) { 4346 if (sd->cl == NULL) 4347 continue; 4348 4349 cll = &sd->cll; 4350 clm = cl_metadata(sc, fl, cll, sd->cl); 4351 if (sd->nmbuf == 0) 4352 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl); 4353 else if (clm && atomic_fetchadd_int(&clm->refcount, -1) == 1) { 4354 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl); 4355 counter_u64_add(extfree_rels, 1); 4356 } 4357 sd->cl = NULL; 4358 } 4359 4360 free(fl->sdesc, M_CXGBE); 4361 fl->sdesc = NULL; 4362 } 4363 4364 static inline void 4365 get_pkt_gl(struct mbuf *m, struct sglist *gl) 4366 { 4367 int rc; 4368 4369 M_ASSERTPKTHDR(m); 4370 4371 sglist_reset(gl); 4372 rc = sglist_append_mbuf(gl, m); 4373 if (__predict_false(rc != 0)) { 4374 panic("%s: mbuf %p (%d segs) was vetted earlier but now fails " 4375 "with %d.", __func__, m, mbuf_nsegs(m), rc); 4376 } 4377 4378 KASSERT(gl->sg_nseg == mbuf_nsegs(m), 4379 ("%s: nsegs changed for mbuf %p from %d to %d", __func__, m, 4380 mbuf_nsegs(m), gl->sg_nseg)); 4381 KASSERT(gl->sg_nseg > 0 && 4382 gl->sg_nseg <= (needs_tso(m) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS), 4383 ("%s: %d segments, should have been 1 <= nsegs <= %d", __func__, 4384 gl->sg_nseg, needs_tso(m) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS)); 4385 } 4386 4387 /* 4388 * len16 for a txpkt WR with a GL. Includes the firmware work request header. 4389 */ 4390 static inline u_int 4391 txpkt_len16(u_int nsegs, u_int tso) 4392 { 4393 u_int n; 4394 4395 MPASS(nsegs > 0); 4396 4397 nsegs--; /* first segment is part of ulptx_sgl */ 4398 n = sizeof(struct fw_eth_tx_pkt_wr) + sizeof(struct cpl_tx_pkt_core) + 4399 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 4400 if (tso) 4401 n += sizeof(struct cpl_tx_pkt_lso_core); 4402 4403 return (howmany(n, 16)); 4404 } 4405 4406 /* 4407 * len16 for a txpkt_vm WR with a GL. Includes the firmware work 4408 * request header. 4409 */ 4410 static inline u_int 4411 txpkt_vm_len16(u_int nsegs, u_int tso) 4412 { 4413 u_int n; 4414 4415 MPASS(nsegs > 0); 4416 4417 nsegs--; /* first segment is part of ulptx_sgl */ 4418 n = sizeof(struct fw_eth_tx_pkt_vm_wr) + 4419 sizeof(struct cpl_tx_pkt_core) + 4420 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 4421 if (tso) 4422 n += sizeof(struct cpl_tx_pkt_lso_core); 4423 4424 return (howmany(n, 16)); 4425 } 4426 4427 /* 4428 * len16 for a txpkts type 0 WR with a GL. Does not include the firmware work 4429 * request header. 4430 */ 4431 static inline u_int 4432 txpkts0_len16(u_int nsegs) 4433 { 4434 u_int n; 4435 4436 MPASS(nsegs > 0); 4437 4438 nsegs--; /* first segment is part of ulptx_sgl */ 4439 n = sizeof(struct ulp_txpkt) + sizeof(struct ulptx_idata) + 4440 sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl) + 4441 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 4442 4443 return (howmany(n, 16)); 4444 } 4445 4446 /* 4447 * len16 for a txpkts type 1 WR with a GL. Does not include the firmware work 4448 * request header. 4449 */ 4450 static inline u_int 4451 txpkts1_len16(void) 4452 { 4453 u_int n; 4454 4455 n = sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl); 4456 4457 return (howmany(n, 16)); 4458 } 4459 4460 static inline u_int 4461 imm_payload(u_int ndesc) 4462 { 4463 u_int n; 4464 4465 n = ndesc * EQ_ESIZE - sizeof(struct fw_eth_tx_pkt_wr) - 4466 sizeof(struct cpl_tx_pkt_core); 4467 4468 return (n); 4469 } 4470 4471 /* 4472 * Write a VM txpkt WR for this packet to the hardware descriptors, update the 4473 * software descriptor, and advance the pidx. It is guaranteed that enough 4474 * descriptors are available. 4475 * 4476 * The return value is the # of hardware descriptors used. 4477 */ 4478 static u_int 4479 write_txpkt_vm_wr(struct adapter *sc, struct sge_txq *txq, 4480 struct fw_eth_tx_pkt_vm_wr *wr, struct mbuf *m0, u_int available) 4481 { 4482 struct sge_eq *eq = &txq->eq; 4483 struct tx_sdesc *txsd; 4484 struct cpl_tx_pkt_core *cpl; 4485 uint32_t ctrl; /* used in many unrelated places */ 4486 uint64_t ctrl1; 4487 int csum_type, len16, ndesc, pktlen, nsegs; 4488 caddr_t dst; 4489 4490 TXQ_LOCK_ASSERT_OWNED(txq); 4491 M_ASSERTPKTHDR(m0); 4492 MPASS(available > 0 && available < eq->sidx); 4493 4494 len16 = mbuf_len16(m0); 4495 nsegs = mbuf_nsegs(m0); 4496 pktlen = m0->m_pkthdr.len; 4497 ctrl = sizeof(struct cpl_tx_pkt_core); 4498 if (needs_tso(m0)) 4499 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 4500 ndesc = howmany(len16, EQ_ESIZE / 16); 4501 MPASS(ndesc <= available); 4502 4503 /* Firmware work request header */ 4504 MPASS(wr == (void *)&eq->desc[eq->pidx]); 4505 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_VM_WR) | 4506 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl)); 4507 4508 ctrl = V_FW_WR_LEN16(len16); 4509 wr->equiq_to_len16 = htobe32(ctrl); 4510 wr->r3[0] = 0; 4511 wr->r3[1] = 0; 4512 4513 /* 4514 * Copy over ethmacdst, ethmacsrc, ethtype, and vlantci. 4515 * vlantci is ignored unless the ethtype is 0x8100, so it's 4516 * simpler to always copy it rather than making it 4517 * conditional. Also, it seems that we do not have to set 4518 * vlantci or fake the ethtype when doing VLAN tag insertion. 4519 */ 4520 m_copydata(m0, 0, sizeof(struct ether_header) + 2, wr->ethmacdst); 4521 4522 csum_type = -1; 4523 if (needs_tso(m0)) { 4524 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1); 4525 4526 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 4527 m0->m_pkthdr.l4hlen > 0, 4528 ("%s: mbuf %p needs TSO but missing header lengths", 4529 __func__, m0)); 4530 4531 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE | 4532 F_LSO_LAST_SLICE | V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) 4533 | V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2); 4534 if (m0->m_pkthdr.l2hlen == sizeof(struct ether_vlan_header)) 4535 ctrl |= V_LSO_ETHHDR_LEN(1); 4536 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 4537 ctrl |= F_LSO_IPV6; 4538 4539 lso->lso_ctrl = htobe32(ctrl); 4540 lso->ipid_ofst = htobe16(0); 4541 lso->mss = htobe16(m0->m_pkthdr.tso_segsz); 4542 lso->seqno_offset = htobe32(0); 4543 lso->len = htobe32(pktlen); 4544 4545 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 4546 csum_type = TX_CSUM_TCPIP6; 4547 else 4548 csum_type = TX_CSUM_TCPIP; 4549 4550 cpl = (void *)(lso + 1); 4551 4552 txq->tso_wrs++; 4553 } else { 4554 if (m0->m_pkthdr.csum_flags & CSUM_IP_TCP) 4555 csum_type = TX_CSUM_TCPIP; 4556 else if (m0->m_pkthdr.csum_flags & CSUM_IP_UDP) 4557 csum_type = TX_CSUM_UDPIP; 4558 else if (m0->m_pkthdr.csum_flags & CSUM_IP6_TCP) 4559 csum_type = TX_CSUM_TCPIP6; 4560 else if (m0->m_pkthdr.csum_flags & CSUM_IP6_UDP) 4561 csum_type = TX_CSUM_UDPIP6; 4562 #if defined(INET) 4563 else if (m0->m_pkthdr.csum_flags & CSUM_IP) { 4564 /* 4565 * XXX: The firmware appears to stomp on the 4566 * fragment/flags field of the IP header when 4567 * using TX_CSUM_IP. Fall back to doing 4568 * software checksums. 4569 */ 4570 u_short *sump; 4571 struct mbuf *m; 4572 int offset; 4573 4574 m = m0; 4575 offset = 0; 4576 sump = m_advance(&m, &offset, m0->m_pkthdr.l2hlen + 4577 offsetof(struct ip, ip_sum)); 4578 *sump = in_cksum_skip(m0, m0->m_pkthdr.l2hlen + 4579 m0->m_pkthdr.l3hlen, m0->m_pkthdr.l2hlen); 4580 m0->m_pkthdr.csum_flags &= ~CSUM_IP; 4581 } 4582 #endif 4583 4584 cpl = (void *)(wr + 1); 4585 } 4586 4587 /* Checksum offload */ 4588 ctrl1 = 0; 4589 if (needs_l3_csum(m0) == 0) 4590 ctrl1 |= F_TXPKT_IPCSUM_DIS; 4591 if (csum_type >= 0) { 4592 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0, 4593 ("%s: mbuf %p needs checksum offload but missing header lengths", 4594 __func__, m0)); 4595 4596 if (chip_id(sc) <= CHELSIO_T5) { 4597 ctrl1 |= V_TXPKT_ETHHDR_LEN(m0->m_pkthdr.l2hlen - 4598 ETHER_HDR_LEN); 4599 } else { 4600 ctrl1 |= V_T6_TXPKT_ETHHDR_LEN(m0->m_pkthdr.l2hlen - 4601 ETHER_HDR_LEN); 4602 } 4603 ctrl1 |= V_TXPKT_IPHDR_LEN(m0->m_pkthdr.l3hlen); 4604 ctrl1 |= V_TXPKT_CSUM_TYPE(csum_type); 4605 } else 4606 ctrl1 |= F_TXPKT_L4CSUM_DIS; 4607 if (m0->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | 4608 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO)) 4609 txq->txcsum++; /* some hardware assistance provided */ 4610 4611 /* VLAN tag insertion */ 4612 if (needs_vlan_insertion(m0)) { 4613 ctrl1 |= F_TXPKT_VLAN_VLD | 4614 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 4615 txq->vlan_insertion++; 4616 } 4617 4618 /* CPL header */ 4619 cpl->ctrl0 = txq->cpl_ctrl0; 4620 cpl->pack = 0; 4621 cpl->len = htobe16(pktlen); 4622 cpl->ctrl1 = htobe64(ctrl1); 4623 4624 /* SGL */ 4625 dst = (void *)(cpl + 1); 4626 4627 /* 4628 * A packet using TSO will use up an entire descriptor for the 4629 * firmware work request header, LSO CPL, and TX_PKT_XT CPL. 4630 * If this descriptor is the last descriptor in the ring, wrap 4631 * around to the front of the ring explicitly for the start of 4632 * the sgl. 4633 */ 4634 if (dst == (void *)&eq->desc[eq->sidx]) { 4635 dst = (void *)&eq->desc[0]; 4636 write_gl_to_txd(txq, m0, &dst, 0); 4637 } else 4638 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx); 4639 txq->sgl_wrs++; 4640 4641 txq->txpkt_wrs++; 4642 4643 txsd = &txq->sdesc[eq->pidx]; 4644 txsd->m = m0; 4645 txsd->desc_used = ndesc; 4646 4647 return (ndesc); 4648 } 4649 4650 /* 4651 * Write a raw WR to the hardware descriptors, update the software 4652 * descriptor, and advance the pidx. It is guaranteed that enough 4653 * descriptors are available. 4654 * 4655 * The return value is the # of hardware descriptors used. 4656 */ 4657 static u_int 4658 write_raw_wr(struct sge_txq *txq, void *wr, struct mbuf *m0, u_int available) 4659 { 4660 struct sge_eq *eq = &txq->eq; 4661 struct tx_sdesc *txsd; 4662 struct mbuf *m; 4663 caddr_t dst; 4664 int len16, ndesc; 4665 4666 len16 = mbuf_len16(m0); 4667 ndesc = howmany(len16, EQ_ESIZE / 16); 4668 MPASS(ndesc <= available); 4669 4670 dst = wr; 4671 for (m = m0; m != NULL; m = m->m_next) 4672 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len); 4673 4674 txq->raw_wrs++; 4675 4676 txsd = &txq->sdesc[eq->pidx]; 4677 txsd->m = m0; 4678 txsd->desc_used = ndesc; 4679 4680 return (ndesc); 4681 } 4682 4683 /* 4684 * Write a txpkt WR for this packet to the hardware descriptors, update the 4685 * software descriptor, and advance the pidx. It is guaranteed that enough 4686 * descriptors are available. 4687 * 4688 * The return value is the # of hardware descriptors used. 4689 */ 4690 static u_int 4691 write_txpkt_wr(struct sge_txq *txq, struct fw_eth_tx_pkt_wr *wr, 4692 struct mbuf *m0, u_int available) 4693 { 4694 struct sge_eq *eq = &txq->eq; 4695 struct tx_sdesc *txsd; 4696 struct cpl_tx_pkt_core *cpl; 4697 uint32_t ctrl; /* used in many unrelated places */ 4698 uint64_t ctrl1; 4699 int len16, ndesc, pktlen, nsegs; 4700 caddr_t dst; 4701 4702 TXQ_LOCK_ASSERT_OWNED(txq); 4703 M_ASSERTPKTHDR(m0); 4704 MPASS(available > 0 && available < eq->sidx); 4705 4706 len16 = mbuf_len16(m0); 4707 nsegs = mbuf_nsegs(m0); 4708 pktlen = m0->m_pkthdr.len; 4709 ctrl = sizeof(struct cpl_tx_pkt_core); 4710 if (needs_tso(m0)) 4711 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 4712 else if (pktlen <= imm_payload(2) && available >= 2) { 4713 /* Immediate data. Recalculate len16 and set nsegs to 0. */ 4714 ctrl += pktlen; 4715 len16 = howmany(sizeof(struct fw_eth_tx_pkt_wr) + 4716 sizeof(struct cpl_tx_pkt_core) + pktlen, 16); 4717 nsegs = 0; 4718 } 4719 ndesc = howmany(len16, EQ_ESIZE / 16); 4720 MPASS(ndesc <= available); 4721 4722 /* Firmware work request header */ 4723 MPASS(wr == (void *)&eq->desc[eq->pidx]); 4724 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_WR) | 4725 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl)); 4726 4727 ctrl = V_FW_WR_LEN16(len16); 4728 wr->equiq_to_len16 = htobe32(ctrl); 4729 wr->r3 = 0; 4730 4731 if (needs_tso(m0)) { 4732 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1); 4733 4734 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 4735 m0->m_pkthdr.l4hlen > 0, 4736 ("%s: mbuf %p needs TSO but missing header lengths", 4737 __func__, m0)); 4738 4739 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE | 4740 F_LSO_LAST_SLICE | V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) 4741 | V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2); 4742 if (m0->m_pkthdr.l2hlen == sizeof(struct ether_vlan_header)) 4743 ctrl |= V_LSO_ETHHDR_LEN(1); 4744 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 4745 ctrl |= F_LSO_IPV6; 4746 4747 lso->lso_ctrl = htobe32(ctrl); 4748 lso->ipid_ofst = htobe16(0); 4749 lso->mss = htobe16(m0->m_pkthdr.tso_segsz); 4750 lso->seqno_offset = htobe32(0); 4751 lso->len = htobe32(pktlen); 4752 4753 cpl = (void *)(lso + 1); 4754 4755 txq->tso_wrs++; 4756 } else 4757 cpl = (void *)(wr + 1); 4758 4759 /* Checksum offload */ 4760 ctrl1 = 0; 4761 if (needs_l3_csum(m0) == 0) 4762 ctrl1 |= F_TXPKT_IPCSUM_DIS; 4763 if (needs_l4_csum(m0) == 0) 4764 ctrl1 |= F_TXPKT_L4CSUM_DIS; 4765 if (m0->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | 4766 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO)) 4767 txq->txcsum++; /* some hardware assistance provided */ 4768 4769 /* VLAN tag insertion */ 4770 if (needs_vlan_insertion(m0)) { 4771 ctrl1 |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 4772 txq->vlan_insertion++; 4773 } 4774 4775 /* CPL header */ 4776 cpl->ctrl0 = txq->cpl_ctrl0; 4777 cpl->pack = 0; 4778 cpl->len = htobe16(pktlen); 4779 cpl->ctrl1 = htobe64(ctrl1); 4780 4781 /* SGL */ 4782 dst = (void *)(cpl + 1); 4783 if (nsegs > 0) { 4784 4785 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx); 4786 txq->sgl_wrs++; 4787 } else { 4788 struct mbuf *m; 4789 4790 for (m = m0; m != NULL; m = m->m_next) { 4791 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len); 4792 #ifdef INVARIANTS 4793 pktlen -= m->m_len; 4794 #endif 4795 } 4796 #ifdef INVARIANTS 4797 KASSERT(pktlen == 0, ("%s: %d bytes left.", __func__, pktlen)); 4798 #endif 4799 txq->imm_wrs++; 4800 } 4801 4802 txq->txpkt_wrs++; 4803 4804 txsd = &txq->sdesc[eq->pidx]; 4805 txsd->m = m0; 4806 txsd->desc_used = ndesc; 4807 4808 return (ndesc); 4809 } 4810 4811 static int 4812 try_txpkts(struct mbuf *m, struct mbuf *n, struct txpkts *txp, u_int available) 4813 { 4814 u_int needed, nsegs1, nsegs2, l1, l2; 4815 4816 if (cannot_use_txpkts(m) || cannot_use_txpkts(n)) 4817 return (1); 4818 4819 nsegs1 = mbuf_nsegs(m); 4820 nsegs2 = mbuf_nsegs(n); 4821 if (nsegs1 + nsegs2 == 2) { 4822 txp->wr_type = 1; 4823 l1 = l2 = txpkts1_len16(); 4824 } else { 4825 txp->wr_type = 0; 4826 l1 = txpkts0_len16(nsegs1); 4827 l2 = txpkts0_len16(nsegs2); 4828 } 4829 txp->len16 = howmany(sizeof(struct fw_eth_tx_pkts_wr), 16) + l1 + l2; 4830 needed = howmany(txp->len16, EQ_ESIZE / 16); 4831 if (needed > SGE_MAX_WR_NDESC || needed > available) 4832 return (1); 4833 4834 txp->plen = m->m_pkthdr.len + n->m_pkthdr.len; 4835 if (txp->plen > 65535) 4836 return (1); 4837 4838 txp->npkt = 2; 4839 set_mbuf_len16(m, l1); 4840 set_mbuf_len16(n, l2); 4841 4842 return (0); 4843 } 4844 4845 static int 4846 add_to_txpkts(struct mbuf *m, struct txpkts *txp, u_int available) 4847 { 4848 u_int plen, len16, needed, nsegs; 4849 4850 MPASS(txp->wr_type == 0 || txp->wr_type == 1); 4851 4852 if (cannot_use_txpkts(m)) 4853 return (1); 4854 4855 nsegs = mbuf_nsegs(m); 4856 if (txp->wr_type == 1 && nsegs != 1) 4857 return (1); 4858 4859 plen = txp->plen + m->m_pkthdr.len; 4860 if (plen > 65535) 4861 return (1); 4862 4863 if (txp->wr_type == 0) 4864 len16 = txpkts0_len16(nsegs); 4865 else 4866 len16 = txpkts1_len16(); 4867 needed = howmany(txp->len16 + len16, EQ_ESIZE / 16); 4868 if (needed > SGE_MAX_WR_NDESC || needed > available) 4869 return (1); 4870 4871 txp->npkt++; 4872 txp->plen = plen; 4873 txp->len16 += len16; 4874 set_mbuf_len16(m, len16); 4875 4876 return (0); 4877 } 4878 4879 /* 4880 * Write a txpkts WR for the packets in txp to the hardware descriptors, update 4881 * the software descriptor, and advance the pidx. It is guaranteed that enough 4882 * descriptors are available. 4883 * 4884 * The return value is the # of hardware descriptors used. 4885 */ 4886 static u_int 4887 write_txpkts_wr(struct sge_txq *txq, struct fw_eth_tx_pkts_wr *wr, 4888 struct mbuf *m0, const struct txpkts *txp, u_int available) 4889 { 4890 struct sge_eq *eq = &txq->eq; 4891 struct tx_sdesc *txsd; 4892 struct cpl_tx_pkt_core *cpl; 4893 uint32_t ctrl; 4894 uint64_t ctrl1; 4895 int ndesc, checkwrap; 4896 struct mbuf *m; 4897 void *flitp; 4898 4899 TXQ_LOCK_ASSERT_OWNED(txq); 4900 MPASS(txp->npkt > 0); 4901 MPASS(txp->plen < 65536); 4902 MPASS(m0 != NULL); 4903 MPASS(m0->m_nextpkt != NULL); 4904 MPASS(txp->len16 <= howmany(SGE_MAX_WR_LEN, 16)); 4905 MPASS(available > 0 && available < eq->sidx); 4906 4907 ndesc = howmany(txp->len16, EQ_ESIZE / 16); 4908 MPASS(ndesc <= available); 4909 4910 MPASS(wr == (void *)&eq->desc[eq->pidx]); 4911 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR)); 4912 ctrl = V_FW_WR_LEN16(txp->len16); 4913 wr->equiq_to_len16 = htobe32(ctrl); 4914 wr->plen = htobe16(txp->plen); 4915 wr->npkt = txp->npkt; 4916 wr->r3 = 0; 4917 wr->type = txp->wr_type; 4918 flitp = wr + 1; 4919 4920 /* 4921 * At this point we are 16B into a hardware descriptor. If checkwrap is 4922 * set then we know the WR is going to wrap around somewhere. We'll 4923 * check for that at appropriate points. 4924 */ 4925 checkwrap = eq->sidx - ndesc < eq->pidx; 4926 for (m = m0; m != NULL; m = m->m_nextpkt) { 4927 if (txp->wr_type == 0) { 4928 struct ulp_txpkt *ulpmc; 4929 struct ulptx_idata *ulpsc; 4930 4931 /* ULP master command */ 4932 ulpmc = flitp; 4933 ulpmc->cmd_dest = htobe32(V_ULPTX_CMD(ULP_TX_PKT) | 4934 V_ULP_TXPKT_DEST(0) | V_ULP_TXPKT_FID(eq->iqid)); 4935 ulpmc->len = htobe32(mbuf_len16(m)); 4936 4937 /* ULP subcommand */ 4938 ulpsc = (void *)(ulpmc + 1); 4939 ulpsc->cmd_more = htobe32(V_ULPTX_CMD(ULP_TX_SC_IMM) | 4940 F_ULP_TX_SC_MORE); 4941 ulpsc->len = htobe32(sizeof(struct cpl_tx_pkt_core)); 4942 4943 cpl = (void *)(ulpsc + 1); 4944 if (checkwrap && 4945 (uintptr_t)cpl == (uintptr_t)&eq->desc[eq->sidx]) 4946 cpl = (void *)&eq->desc[0]; 4947 } else { 4948 cpl = flitp; 4949 } 4950 4951 /* Checksum offload */ 4952 ctrl1 = 0; 4953 if (needs_l3_csum(m) == 0) 4954 ctrl1 |= F_TXPKT_IPCSUM_DIS; 4955 if (needs_l4_csum(m) == 0) 4956 ctrl1 |= F_TXPKT_L4CSUM_DIS; 4957 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | 4958 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO)) 4959 txq->txcsum++; /* some hardware assistance provided */ 4960 4961 /* VLAN tag insertion */ 4962 if (needs_vlan_insertion(m)) { 4963 ctrl1 |= F_TXPKT_VLAN_VLD | 4964 V_TXPKT_VLAN(m->m_pkthdr.ether_vtag); 4965 txq->vlan_insertion++; 4966 } 4967 4968 /* CPL header */ 4969 cpl->ctrl0 = txq->cpl_ctrl0; 4970 cpl->pack = 0; 4971 cpl->len = htobe16(m->m_pkthdr.len); 4972 cpl->ctrl1 = htobe64(ctrl1); 4973 4974 flitp = cpl + 1; 4975 if (checkwrap && 4976 (uintptr_t)flitp == (uintptr_t)&eq->desc[eq->sidx]) 4977 flitp = (void *)&eq->desc[0]; 4978 4979 write_gl_to_txd(txq, m, (caddr_t *)(&flitp), checkwrap); 4980 4981 } 4982 4983 if (txp->wr_type == 0) { 4984 txq->txpkts0_pkts += txp->npkt; 4985 txq->txpkts0_wrs++; 4986 } else { 4987 txq->txpkts1_pkts += txp->npkt; 4988 txq->txpkts1_wrs++; 4989 } 4990 4991 txsd = &txq->sdesc[eq->pidx]; 4992 txsd->m = m0; 4993 txsd->desc_used = ndesc; 4994 4995 return (ndesc); 4996 } 4997 4998 /* 4999 * If the SGL ends on an address that is not 16 byte aligned, this function will 5000 * add a 0 filled flit at the end. 5001 */ 5002 static void 5003 write_gl_to_txd(struct sge_txq *txq, struct mbuf *m, caddr_t *to, int checkwrap) 5004 { 5005 struct sge_eq *eq = &txq->eq; 5006 struct sglist *gl = txq->gl; 5007 struct sglist_seg *seg; 5008 __be64 *flitp, *wrap; 5009 struct ulptx_sgl *usgl; 5010 int i, nflits, nsegs; 5011 5012 KASSERT(((uintptr_t)(*to) & 0xf) == 0, 5013 ("%s: SGL must start at a 16 byte boundary: %p", __func__, *to)); 5014 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]); 5015 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]); 5016 5017 get_pkt_gl(m, gl); 5018 nsegs = gl->sg_nseg; 5019 MPASS(nsegs > 0); 5020 5021 nflits = (3 * (nsegs - 1)) / 2 + ((nsegs - 1) & 1) + 2; 5022 flitp = (__be64 *)(*to); 5023 wrap = (__be64 *)(&eq->desc[eq->sidx]); 5024 seg = &gl->sg_segs[0]; 5025 usgl = (void *)flitp; 5026 5027 /* 5028 * We start at a 16 byte boundary somewhere inside the tx descriptor 5029 * ring, so we're at least 16 bytes away from the status page. There is 5030 * no chance of a wrap around in the middle of usgl (which is 16 bytes). 5031 */ 5032 5033 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 5034 V_ULPTX_NSGE(nsegs)); 5035 usgl->len0 = htobe32(seg->ss_len); 5036 usgl->addr0 = htobe64(seg->ss_paddr); 5037 seg++; 5038 5039 if (checkwrap == 0 || (uintptr_t)(flitp + nflits) <= (uintptr_t)wrap) { 5040 5041 /* Won't wrap around at all */ 5042 5043 for (i = 0; i < nsegs - 1; i++, seg++) { 5044 usgl->sge[i / 2].len[i & 1] = htobe32(seg->ss_len); 5045 usgl->sge[i / 2].addr[i & 1] = htobe64(seg->ss_paddr); 5046 } 5047 if (i & 1) 5048 usgl->sge[i / 2].len[1] = htobe32(0); 5049 flitp += nflits; 5050 } else { 5051 5052 /* Will wrap somewhere in the rest of the SGL */ 5053 5054 /* 2 flits already written, write the rest flit by flit */ 5055 flitp = (void *)(usgl + 1); 5056 for (i = 0; i < nflits - 2; i++) { 5057 if (flitp == wrap) 5058 flitp = (void *)eq->desc; 5059 *flitp++ = get_flit(seg, nsegs - 1, i); 5060 } 5061 } 5062 5063 if (nflits & 1) { 5064 MPASS(((uintptr_t)flitp) & 0xf); 5065 *flitp++ = 0; 5066 } 5067 5068 MPASS((((uintptr_t)flitp) & 0xf) == 0); 5069 if (__predict_false(flitp == wrap)) 5070 *to = (void *)eq->desc; 5071 else 5072 *to = (void *)flitp; 5073 } 5074 5075 static inline void 5076 copy_to_txd(struct sge_eq *eq, caddr_t from, caddr_t *to, int len) 5077 { 5078 5079 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]); 5080 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]); 5081 5082 if (__predict_true((uintptr_t)(*to) + len <= 5083 (uintptr_t)&eq->desc[eq->sidx])) { 5084 bcopy(from, *to, len); 5085 (*to) += len; 5086 } else { 5087 int portion = (uintptr_t)&eq->desc[eq->sidx] - (uintptr_t)(*to); 5088 5089 bcopy(from, *to, portion); 5090 from += portion; 5091 portion = len - portion; /* remaining */ 5092 bcopy(from, (void *)eq->desc, portion); 5093 (*to) = (caddr_t)eq->desc + portion; 5094 } 5095 } 5096 5097 static inline void 5098 ring_eq_db(struct adapter *sc, struct sge_eq *eq, u_int n) 5099 { 5100 u_int db; 5101 5102 MPASS(n > 0); 5103 5104 db = eq->doorbells; 5105 if (n > 1) 5106 clrbit(&db, DOORBELL_WCWR); 5107 wmb(); 5108 5109 switch (ffs(db) - 1) { 5110 case DOORBELL_UDB: 5111 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n)); 5112 break; 5113 5114 case DOORBELL_WCWR: { 5115 volatile uint64_t *dst, *src; 5116 int i; 5117 5118 /* 5119 * Queues whose 128B doorbell segment fits in the page do not 5120 * use relative qid (udb_qid is always 0). Only queues with 5121 * doorbell segments can do WCWR. 5122 */ 5123 KASSERT(eq->udb_qid == 0 && n == 1, 5124 ("%s: inappropriate doorbell (0x%x, %d, %d) for eq %p", 5125 __func__, eq->doorbells, n, eq->dbidx, eq)); 5126 5127 dst = (volatile void *)((uintptr_t)eq->udb + UDBS_WR_OFFSET - 5128 UDBS_DB_OFFSET); 5129 i = eq->dbidx; 5130 src = (void *)&eq->desc[i]; 5131 while (src != (void *)&eq->desc[i + 1]) 5132 *dst++ = *src++; 5133 wmb(); 5134 break; 5135 } 5136 5137 case DOORBELL_UDBWC: 5138 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n)); 5139 wmb(); 5140 break; 5141 5142 case DOORBELL_KDB: 5143 t4_write_reg(sc, sc->sge_kdoorbell_reg, 5144 V_QID(eq->cntxt_id) | V_PIDX(n)); 5145 break; 5146 } 5147 5148 IDXINCR(eq->dbidx, n, eq->sidx); 5149 } 5150 5151 static inline u_int 5152 reclaimable_tx_desc(struct sge_eq *eq) 5153 { 5154 uint16_t hw_cidx; 5155 5156 hw_cidx = read_hw_cidx(eq); 5157 return (IDXDIFF(hw_cidx, eq->cidx, eq->sidx)); 5158 } 5159 5160 static inline u_int 5161 total_available_tx_desc(struct sge_eq *eq) 5162 { 5163 uint16_t hw_cidx, pidx; 5164 5165 hw_cidx = read_hw_cidx(eq); 5166 pidx = eq->pidx; 5167 5168 if (pidx == hw_cidx) 5169 return (eq->sidx - 1); 5170 else 5171 return (IDXDIFF(hw_cidx, pidx, eq->sidx) - 1); 5172 } 5173 5174 static inline uint16_t 5175 read_hw_cidx(struct sge_eq *eq) 5176 { 5177 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx]; 5178 uint16_t cidx = spg->cidx; /* stable snapshot */ 5179 5180 return (be16toh(cidx)); 5181 } 5182 5183 /* 5184 * Reclaim 'n' descriptors approximately. 5185 */ 5186 static u_int 5187 reclaim_tx_descs(struct sge_txq *txq, u_int n) 5188 { 5189 struct tx_sdesc *txsd; 5190 struct sge_eq *eq = &txq->eq; 5191 u_int can_reclaim, reclaimed; 5192 5193 TXQ_LOCK_ASSERT_OWNED(txq); 5194 MPASS(n > 0); 5195 5196 reclaimed = 0; 5197 can_reclaim = reclaimable_tx_desc(eq); 5198 while (can_reclaim && reclaimed < n) { 5199 int ndesc; 5200 struct mbuf *m, *nextpkt; 5201 5202 txsd = &txq->sdesc[eq->cidx]; 5203 ndesc = txsd->desc_used; 5204 5205 /* Firmware doesn't return "partial" credits. */ 5206 KASSERT(can_reclaim >= ndesc, 5207 ("%s: unexpected number of credits: %d, %d", 5208 __func__, can_reclaim, ndesc)); 5209 KASSERT(ndesc != 0, 5210 ("%s: descriptor with no credits: cidx %d", 5211 __func__, eq->cidx)); 5212 5213 for (m = txsd->m; m != NULL; m = nextpkt) { 5214 nextpkt = m->m_nextpkt; 5215 m->m_nextpkt = NULL; 5216 m_freem(m); 5217 } 5218 reclaimed += ndesc; 5219 can_reclaim -= ndesc; 5220 IDXINCR(eq->cidx, ndesc, eq->sidx); 5221 } 5222 5223 return (reclaimed); 5224 } 5225 5226 static void 5227 tx_reclaim(void *arg, int n) 5228 { 5229 struct sge_txq *txq = arg; 5230 struct sge_eq *eq = &txq->eq; 5231 5232 do { 5233 if (TXQ_TRYLOCK(txq) == 0) 5234 break; 5235 n = reclaim_tx_descs(txq, 32); 5236 if (eq->cidx == eq->pidx) 5237 eq->equeqidx = eq->pidx; 5238 TXQ_UNLOCK(txq); 5239 } while (n > 0); 5240 } 5241 5242 static __be64 5243 get_flit(struct sglist_seg *segs, int nsegs, int idx) 5244 { 5245 int i = (idx / 3) * 2; 5246 5247 switch (idx % 3) { 5248 case 0: { 5249 uint64_t rc; 5250 5251 rc = (uint64_t)segs[i].ss_len << 32; 5252 if (i + 1 < nsegs) 5253 rc |= (uint64_t)(segs[i + 1].ss_len); 5254 5255 return (htobe64(rc)); 5256 } 5257 case 1: 5258 return (htobe64(segs[i].ss_paddr)); 5259 case 2: 5260 return (htobe64(segs[i + 1].ss_paddr)); 5261 } 5262 5263 return (0); 5264 } 5265 5266 static void 5267 find_best_refill_source(struct adapter *sc, struct sge_fl *fl, int maxp) 5268 { 5269 int8_t zidx, hwidx, idx; 5270 uint16_t region1, region3; 5271 int spare, spare_needed, n; 5272 struct sw_zone_info *swz; 5273 struct hw_buf_info *hwb, *hwb_list = &sc->sge.hw_buf_info[0]; 5274 5275 /* 5276 * Buffer Packing: Look for PAGE_SIZE or larger zone which has a bufsize 5277 * large enough for the max payload and cluster metadata. Otherwise 5278 * settle for the largest bufsize that leaves enough room in the cluster 5279 * for metadata. 5280 * 5281 * Without buffer packing: Look for the smallest zone which has a 5282 * bufsize large enough for the max payload. Settle for the largest 5283 * bufsize available if there's nothing big enough for max payload. 5284 */ 5285 spare_needed = fl->flags & FL_BUF_PACKING ? CL_METADATA_SIZE : 0; 5286 swz = &sc->sge.sw_zone_info[0]; 5287 hwidx = -1; 5288 for (zidx = 0; zidx < SW_ZONE_SIZES; zidx++, swz++) { 5289 if (swz->size > largest_rx_cluster) { 5290 if (__predict_true(hwidx != -1)) 5291 break; 5292 5293 /* 5294 * This is a misconfiguration. largest_rx_cluster is 5295 * preventing us from finding a refill source. See 5296 * dev.t5nex.<n>.buffer_sizes to figure out why. 5297 */ 5298 device_printf(sc->dev, "largest_rx_cluster=%u leaves no" 5299 " refill source for fl %p (dma %u). Ignored.\n", 5300 largest_rx_cluster, fl, maxp); 5301 } 5302 for (idx = swz->head_hwidx; idx != -1; idx = hwb->next) { 5303 hwb = &hwb_list[idx]; 5304 spare = swz->size - hwb->size; 5305 if (spare < spare_needed) 5306 continue; 5307 5308 hwidx = idx; /* best option so far */ 5309 if (hwb->size >= maxp) { 5310 5311 if ((fl->flags & FL_BUF_PACKING) == 0) 5312 goto done; /* stop looking (not packing) */ 5313 5314 if (swz->size >= safest_rx_cluster) 5315 goto done; /* stop looking (packing) */ 5316 } 5317 break; /* keep looking, next zone */ 5318 } 5319 } 5320 done: 5321 /* A usable hwidx has been located. */ 5322 MPASS(hwidx != -1); 5323 hwb = &hwb_list[hwidx]; 5324 zidx = hwb->zidx; 5325 swz = &sc->sge.sw_zone_info[zidx]; 5326 region1 = 0; 5327 region3 = swz->size - hwb->size; 5328 5329 /* 5330 * Stay within this zone and see if there is a better match when mbuf 5331 * inlining is allowed. Remember that the hwidx's are sorted in 5332 * decreasing order of size (so in increasing order of spare area). 5333 */ 5334 for (idx = hwidx; idx != -1; idx = hwb->next) { 5335 hwb = &hwb_list[idx]; 5336 spare = swz->size - hwb->size; 5337 5338 if (allow_mbufs_in_cluster == 0 || hwb->size < maxp) 5339 break; 5340 5341 /* 5342 * Do not inline mbufs if doing so would violate the pad/pack 5343 * boundary alignment requirement. 5344 */ 5345 if (fl_pad && (MSIZE % sc->params.sge.pad_boundary) != 0) 5346 continue; 5347 if (fl->flags & FL_BUF_PACKING && 5348 (MSIZE % sc->params.sge.pack_boundary) != 0) 5349 continue; 5350 5351 if (spare < CL_METADATA_SIZE + MSIZE) 5352 continue; 5353 n = (spare - CL_METADATA_SIZE) / MSIZE; 5354 if (n > howmany(hwb->size, maxp)) 5355 break; 5356 5357 hwidx = idx; 5358 if (fl->flags & FL_BUF_PACKING) { 5359 region1 = n * MSIZE; 5360 region3 = spare - region1; 5361 } else { 5362 region1 = MSIZE; 5363 region3 = spare - region1; 5364 break; 5365 } 5366 } 5367 5368 KASSERT(zidx >= 0 && zidx < SW_ZONE_SIZES, 5369 ("%s: bad zone %d for fl %p, maxp %d", __func__, zidx, fl, maxp)); 5370 KASSERT(hwidx >= 0 && hwidx <= SGE_FLBUF_SIZES, 5371 ("%s: bad hwidx %d for fl %p, maxp %d", __func__, hwidx, fl, maxp)); 5372 KASSERT(region1 + sc->sge.hw_buf_info[hwidx].size + region3 == 5373 sc->sge.sw_zone_info[zidx].size, 5374 ("%s: bad buffer layout for fl %p, maxp %d. " 5375 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp, 5376 sc->sge.sw_zone_info[zidx].size, region1, 5377 sc->sge.hw_buf_info[hwidx].size, region3)); 5378 if (fl->flags & FL_BUF_PACKING || region1 > 0) { 5379 KASSERT(region3 >= CL_METADATA_SIZE, 5380 ("%s: no room for metadata. fl %p, maxp %d; " 5381 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp, 5382 sc->sge.sw_zone_info[zidx].size, region1, 5383 sc->sge.hw_buf_info[hwidx].size, region3)); 5384 KASSERT(region1 % MSIZE == 0, 5385 ("%s: bad mbuf region for fl %p, maxp %d. " 5386 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp, 5387 sc->sge.sw_zone_info[zidx].size, region1, 5388 sc->sge.hw_buf_info[hwidx].size, region3)); 5389 } 5390 5391 fl->cll_def.zidx = zidx; 5392 fl->cll_def.hwidx = hwidx; 5393 fl->cll_def.region1 = region1; 5394 fl->cll_def.region3 = region3; 5395 } 5396 5397 static void 5398 find_safe_refill_source(struct adapter *sc, struct sge_fl *fl) 5399 { 5400 struct sge *s = &sc->sge; 5401 struct hw_buf_info *hwb; 5402 struct sw_zone_info *swz; 5403 int spare; 5404 int8_t hwidx; 5405 5406 if (fl->flags & FL_BUF_PACKING) 5407 hwidx = s->safe_hwidx2; /* with room for metadata */ 5408 else if (allow_mbufs_in_cluster && s->safe_hwidx2 != -1) { 5409 hwidx = s->safe_hwidx2; 5410 hwb = &s->hw_buf_info[hwidx]; 5411 swz = &s->sw_zone_info[hwb->zidx]; 5412 spare = swz->size - hwb->size; 5413 5414 /* no good if there isn't room for an mbuf as well */ 5415 if (spare < CL_METADATA_SIZE + MSIZE) 5416 hwidx = s->safe_hwidx1; 5417 } else 5418 hwidx = s->safe_hwidx1; 5419 5420 if (hwidx == -1) { 5421 /* No fallback source */ 5422 fl->cll_alt.hwidx = -1; 5423 fl->cll_alt.zidx = -1; 5424 5425 return; 5426 } 5427 5428 hwb = &s->hw_buf_info[hwidx]; 5429 swz = &s->sw_zone_info[hwb->zidx]; 5430 spare = swz->size - hwb->size; 5431 fl->cll_alt.hwidx = hwidx; 5432 fl->cll_alt.zidx = hwb->zidx; 5433 if (allow_mbufs_in_cluster && 5434 (fl_pad == 0 || (MSIZE % sc->params.sge.pad_boundary) == 0)) 5435 fl->cll_alt.region1 = ((spare - CL_METADATA_SIZE) / MSIZE) * MSIZE; 5436 else 5437 fl->cll_alt.region1 = 0; 5438 fl->cll_alt.region3 = spare - fl->cll_alt.region1; 5439 } 5440 5441 static void 5442 add_fl_to_sfl(struct adapter *sc, struct sge_fl *fl) 5443 { 5444 mtx_lock(&sc->sfl_lock); 5445 FL_LOCK(fl); 5446 if ((fl->flags & FL_DOOMED) == 0) { 5447 fl->flags |= FL_STARVING; 5448 TAILQ_INSERT_TAIL(&sc->sfl, fl, link); 5449 callout_reset(&sc->sfl_callout, hz / 5, refill_sfl, sc); 5450 } 5451 FL_UNLOCK(fl); 5452 mtx_unlock(&sc->sfl_lock); 5453 } 5454 5455 static void 5456 handle_wrq_egr_update(struct adapter *sc, struct sge_eq *eq) 5457 { 5458 struct sge_wrq *wrq = (void *)eq; 5459 5460 atomic_readandclear_int(&eq->equiq); 5461 taskqueue_enqueue(sc->tq[eq->tx_chan], &wrq->wrq_tx_task); 5462 } 5463 5464 static void 5465 handle_eth_egr_update(struct adapter *sc, struct sge_eq *eq) 5466 { 5467 struct sge_txq *txq = (void *)eq; 5468 5469 MPASS((eq->flags & EQ_TYPEMASK) == EQ_ETH); 5470 5471 atomic_readandclear_int(&eq->equiq); 5472 mp_ring_check_drainage(txq->r, 0); 5473 taskqueue_enqueue(sc->tq[eq->tx_chan], &txq->tx_reclaim_task); 5474 } 5475 5476 static int 5477 handle_sge_egr_update(struct sge_iq *iq, const struct rss_header *rss, 5478 struct mbuf *m) 5479 { 5480 const struct cpl_sge_egr_update *cpl = (const void *)(rss + 1); 5481 unsigned int qid = G_EGR_QID(ntohl(cpl->opcode_qid)); 5482 struct adapter *sc = iq->adapter; 5483 struct sge *s = &sc->sge; 5484 struct sge_eq *eq; 5485 static void (*h[])(struct adapter *, struct sge_eq *) = {NULL, 5486 &handle_wrq_egr_update, &handle_eth_egr_update, 5487 &handle_wrq_egr_update}; 5488 5489 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 5490 rss->opcode)); 5491 5492 eq = s->eqmap[qid - s->eq_start - s->eq_base]; 5493 (*h[eq->flags & EQ_TYPEMASK])(sc, eq); 5494 5495 return (0); 5496 } 5497 5498 /* handle_fw_msg works for both fw4_msg and fw6_msg because this is valid */ 5499 CTASSERT(offsetof(struct cpl_fw4_msg, data) == \ 5500 offsetof(struct cpl_fw6_msg, data)); 5501 5502 static int 5503 handle_fw_msg(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 5504 { 5505 struct adapter *sc = iq->adapter; 5506 const struct cpl_fw6_msg *cpl = (const void *)(rss + 1); 5507 5508 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 5509 rss->opcode)); 5510 5511 if (cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL) { 5512 const struct rss_header *rss2; 5513 5514 rss2 = (const struct rss_header *)&cpl->data[0]; 5515 return (t4_cpl_handler[rss2->opcode](iq, rss2, m)); 5516 } 5517 5518 return (t4_fw_msg_handler[cpl->type](sc, &cpl->data[0])); 5519 } 5520 5521 /** 5522 * t4_handle_wrerr_rpl - process a FW work request error message 5523 * @adap: the adapter 5524 * @rpl: start of the FW message 5525 */ 5526 static int 5527 t4_handle_wrerr_rpl(struct adapter *adap, const __be64 *rpl) 5528 { 5529 u8 opcode = *(const u8 *)rpl; 5530 const struct fw_error_cmd *e = (const void *)rpl; 5531 unsigned int i; 5532 5533 if (opcode != FW_ERROR_CMD) { 5534 log(LOG_ERR, 5535 "%s: Received WRERR_RPL message with opcode %#x\n", 5536 device_get_nameunit(adap->dev), opcode); 5537 return (EINVAL); 5538 } 5539 log(LOG_ERR, "%s: FW_ERROR (%s) ", device_get_nameunit(adap->dev), 5540 G_FW_ERROR_CMD_FATAL(be32toh(e->op_to_type)) ? "fatal" : 5541 "non-fatal"); 5542 switch (G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type))) { 5543 case FW_ERROR_TYPE_EXCEPTION: 5544 log(LOG_ERR, "exception info:\n"); 5545 for (i = 0; i < nitems(e->u.exception.info); i++) 5546 log(LOG_ERR, "%s%08x", i == 0 ? "\t" : " ", 5547 be32toh(e->u.exception.info[i])); 5548 log(LOG_ERR, "\n"); 5549 break; 5550 case FW_ERROR_TYPE_HWMODULE: 5551 log(LOG_ERR, "HW module regaddr %08x regval %08x\n", 5552 be32toh(e->u.hwmodule.regaddr), 5553 be32toh(e->u.hwmodule.regval)); 5554 break; 5555 case FW_ERROR_TYPE_WR: 5556 log(LOG_ERR, "WR cidx %d PF %d VF %d eqid %d hdr:\n", 5557 be16toh(e->u.wr.cidx), 5558 G_FW_ERROR_CMD_PFN(be16toh(e->u.wr.pfn_vfn)), 5559 G_FW_ERROR_CMD_VFN(be16toh(e->u.wr.pfn_vfn)), 5560 be32toh(e->u.wr.eqid)); 5561 for (i = 0; i < nitems(e->u.wr.wrhdr); i++) 5562 log(LOG_ERR, "%s%02x", i == 0 ? "\t" : " ", 5563 e->u.wr.wrhdr[i]); 5564 log(LOG_ERR, "\n"); 5565 break; 5566 case FW_ERROR_TYPE_ACL: 5567 log(LOG_ERR, "ACL cidx %d PF %d VF %d eqid %d %s", 5568 be16toh(e->u.acl.cidx), 5569 G_FW_ERROR_CMD_PFN(be16toh(e->u.acl.pfn_vfn)), 5570 G_FW_ERROR_CMD_VFN(be16toh(e->u.acl.pfn_vfn)), 5571 be32toh(e->u.acl.eqid), 5572 G_FW_ERROR_CMD_MV(be16toh(e->u.acl.mv_pkd)) ? "vlanid" : 5573 "MAC"); 5574 for (i = 0; i < nitems(e->u.acl.val); i++) 5575 log(LOG_ERR, " %02x", e->u.acl.val[i]); 5576 log(LOG_ERR, "\n"); 5577 break; 5578 default: 5579 log(LOG_ERR, "type %#x\n", 5580 G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type))); 5581 return (EINVAL); 5582 } 5583 return (0); 5584 } 5585 5586 static int 5587 sysctl_uint16(SYSCTL_HANDLER_ARGS) 5588 { 5589 uint16_t *id = arg1; 5590 int i = *id; 5591 5592 return sysctl_handle_int(oidp, &i, 0, req); 5593 } 5594 5595 static int 5596 sysctl_bufsizes(SYSCTL_HANDLER_ARGS) 5597 { 5598 struct sge *s = arg1; 5599 struct hw_buf_info *hwb = &s->hw_buf_info[0]; 5600 struct sw_zone_info *swz = &s->sw_zone_info[0]; 5601 int i, rc; 5602 struct sbuf sb; 5603 char c; 5604 5605 sbuf_new(&sb, NULL, 32, SBUF_AUTOEXTEND); 5606 for (i = 0; i < SGE_FLBUF_SIZES; i++, hwb++) { 5607 if (hwb->zidx >= 0 && swz[hwb->zidx].size <= largest_rx_cluster) 5608 c = '*'; 5609 else 5610 c = '\0'; 5611 5612 sbuf_printf(&sb, "%u%c ", hwb->size, c); 5613 } 5614 sbuf_trim(&sb); 5615 sbuf_finish(&sb); 5616 rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req); 5617 sbuf_delete(&sb); 5618 return (rc); 5619 } 5620 5621 #ifdef RATELIMIT 5622 /* 5623 * len16 for a txpkt WR with a GL. Includes the firmware work request header. 5624 */ 5625 static inline u_int 5626 txpkt_eo_len16(u_int nsegs, u_int immhdrs, u_int tso) 5627 { 5628 u_int n; 5629 5630 MPASS(immhdrs > 0); 5631 5632 n = roundup2(sizeof(struct fw_eth_tx_eo_wr) + 5633 sizeof(struct cpl_tx_pkt_core) + immhdrs, 16); 5634 if (__predict_false(nsegs == 0)) 5635 goto done; 5636 5637 nsegs--; /* first segment is part of ulptx_sgl */ 5638 n += sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 5639 if (tso) 5640 n += sizeof(struct cpl_tx_pkt_lso_core); 5641 5642 done: 5643 return (howmany(n, 16)); 5644 } 5645 5646 #define ETID_FLOWC_NPARAMS 6 5647 #define ETID_FLOWC_LEN (roundup2((sizeof(struct fw_flowc_wr) + \ 5648 ETID_FLOWC_NPARAMS * sizeof(struct fw_flowc_mnemval)), 16)) 5649 #define ETID_FLOWC_LEN16 (howmany(ETID_FLOWC_LEN, 16)) 5650 5651 static int 5652 send_etid_flowc_wr(struct cxgbe_snd_tag *cst, struct port_info *pi, 5653 struct vi_info *vi) 5654 { 5655 struct wrq_cookie cookie; 5656 u_int pfvf = G_FW_VIID_PFN(vi->viid) << S_FW_VIID_PFN; 5657 struct fw_flowc_wr *flowc; 5658 5659 mtx_assert(&cst->lock, MA_OWNED); 5660 MPASS((cst->flags & (EO_FLOWC_PENDING | EO_FLOWC_RPL_PENDING)) == 5661 EO_FLOWC_PENDING); 5662 5663 flowc = start_wrq_wr(cst->eo_txq, ETID_FLOWC_LEN16, &cookie); 5664 if (__predict_false(flowc == NULL)) 5665 return (ENOMEM); 5666 5667 bzero(flowc, ETID_FLOWC_LEN); 5668 flowc->op_to_nparams = htobe32(V_FW_WR_OP(FW_FLOWC_WR) | 5669 V_FW_FLOWC_WR_NPARAMS(ETID_FLOWC_NPARAMS) | V_FW_WR_COMPL(0)); 5670 flowc->flowid_len16 = htonl(V_FW_WR_LEN16(ETID_FLOWC_LEN16) | 5671 V_FW_WR_FLOWID(cst->etid)); 5672 flowc->mnemval[0].mnemonic = FW_FLOWC_MNEM_PFNVFN; 5673 flowc->mnemval[0].val = htobe32(pfvf); 5674 flowc->mnemval[1].mnemonic = FW_FLOWC_MNEM_CH; 5675 flowc->mnemval[1].val = htobe32(pi->tx_chan); 5676 flowc->mnemval[2].mnemonic = FW_FLOWC_MNEM_PORT; 5677 flowc->mnemval[2].val = htobe32(pi->tx_chan); 5678 flowc->mnemval[3].mnemonic = FW_FLOWC_MNEM_IQID; 5679 flowc->mnemval[3].val = htobe32(cst->iqid); 5680 flowc->mnemval[4].mnemonic = FW_FLOWC_MNEM_EOSTATE; 5681 flowc->mnemval[4].val = htobe32(FW_FLOWC_MNEM_EOSTATE_ESTABLISHED); 5682 flowc->mnemval[5].mnemonic = FW_FLOWC_MNEM_SCHEDCLASS; 5683 flowc->mnemval[5].val = htobe32(cst->schedcl); 5684 5685 commit_wrq_wr(cst->eo_txq, flowc, &cookie); 5686 5687 cst->flags &= ~EO_FLOWC_PENDING; 5688 cst->flags |= EO_FLOWC_RPL_PENDING; 5689 MPASS(cst->tx_credits >= ETID_FLOWC_LEN16); /* flowc is first WR. */ 5690 cst->tx_credits -= ETID_FLOWC_LEN16; 5691 5692 return (0); 5693 } 5694 5695 #define ETID_FLUSH_LEN16 (howmany(sizeof (struct fw_flowc_wr), 16)) 5696 5697 void 5698 send_etid_flush_wr(struct cxgbe_snd_tag *cst) 5699 { 5700 struct fw_flowc_wr *flowc; 5701 struct wrq_cookie cookie; 5702 5703 mtx_assert(&cst->lock, MA_OWNED); 5704 5705 flowc = start_wrq_wr(cst->eo_txq, ETID_FLUSH_LEN16, &cookie); 5706 if (__predict_false(flowc == NULL)) 5707 CXGBE_UNIMPLEMENTED(__func__); 5708 5709 bzero(flowc, ETID_FLUSH_LEN16 * 16); 5710 flowc->op_to_nparams = htobe32(V_FW_WR_OP(FW_FLOWC_WR) | 5711 V_FW_FLOWC_WR_NPARAMS(0) | F_FW_WR_COMPL); 5712 flowc->flowid_len16 = htobe32(V_FW_WR_LEN16(ETID_FLUSH_LEN16) | 5713 V_FW_WR_FLOWID(cst->etid)); 5714 5715 commit_wrq_wr(cst->eo_txq, flowc, &cookie); 5716 5717 cst->flags |= EO_FLUSH_RPL_PENDING; 5718 MPASS(cst->tx_credits >= ETID_FLUSH_LEN16); 5719 cst->tx_credits -= ETID_FLUSH_LEN16; 5720 cst->ncompl++; 5721 } 5722 5723 static void 5724 write_ethofld_wr(struct cxgbe_snd_tag *cst, struct fw_eth_tx_eo_wr *wr, 5725 struct mbuf *m0, int compl) 5726 { 5727 struct cpl_tx_pkt_core *cpl; 5728 uint64_t ctrl1; 5729 uint32_t ctrl; /* used in many unrelated places */ 5730 int len16, pktlen, nsegs, immhdrs; 5731 caddr_t dst; 5732 uintptr_t p; 5733 struct ulptx_sgl *usgl; 5734 struct sglist sg; 5735 struct sglist_seg segs[38]; /* XXX: find real limit. XXX: get off the stack */ 5736 5737 mtx_assert(&cst->lock, MA_OWNED); 5738 M_ASSERTPKTHDR(m0); 5739 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 5740 m0->m_pkthdr.l4hlen > 0, 5741 ("%s: ethofld mbuf %p is missing header lengths", __func__, m0)); 5742 5743 len16 = mbuf_eo_len16(m0); 5744 nsegs = mbuf_eo_nsegs(m0); 5745 pktlen = m0->m_pkthdr.len; 5746 ctrl = sizeof(struct cpl_tx_pkt_core); 5747 if (needs_tso(m0)) 5748 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 5749 immhdrs = m0->m_pkthdr.l2hlen + m0->m_pkthdr.l3hlen + m0->m_pkthdr.l4hlen; 5750 ctrl += immhdrs; 5751 5752 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_EO_WR) | 5753 V_FW_ETH_TX_EO_WR_IMMDLEN(ctrl) | V_FW_WR_COMPL(!!compl)); 5754 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(len16) | 5755 V_FW_WR_FLOWID(cst->etid)); 5756 wr->r3 = 0; 5757 if (needs_udp_csum(m0)) { 5758 wr->u.udpseg.type = FW_ETH_TX_EO_TYPE_UDPSEG; 5759 wr->u.udpseg.ethlen = m0->m_pkthdr.l2hlen; 5760 wr->u.udpseg.iplen = htobe16(m0->m_pkthdr.l3hlen); 5761 wr->u.udpseg.udplen = m0->m_pkthdr.l4hlen; 5762 wr->u.udpseg.rtplen = 0; 5763 wr->u.udpseg.r4 = 0; 5764 wr->u.udpseg.mss = htobe16(pktlen - immhdrs); 5765 wr->u.udpseg.schedpktsize = wr->u.udpseg.mss; 5766 wr->u.udpseg.plen = htobe32(pktlen - immhdrs); 5767 cpl = (void *)(wr + 1); 5768 } else { 5769 MPASS(needs_tcp_csum(m0)); 5770 wr->u.tcpseg.type = FW_ETH_TX_EO_TYPE_TCPSEG; 5771 wr->u.tcpseg.ethlen = m0->m_pkthdr.l2hlen; 5772 wr->u.tcpseg.iplen = htobe16(m0->m_pkthdr.l3hlen); 5773 wr->u.tcpseg.tcplen = m0->m_pkthdr.l4hlen; 5774 wr->u.tcpseg.tsclk_tsoff = mbuf_eo_tsclk_tsoff(m0); 5775 wr->u.tcpseg.r4 = 0; 5776 wr->u.tcpseg.r5 = 0; 5777 wr->u.tcpseg.plen = htobe32(pktlen - immhdrs); 5778 5779 if (needs_tso(m0)) { 5780 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1); 5781 5782 wr->u.tcpseg.mss = htobe16(m0->m_pkthdr.tso_segsz); 5783 5784 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | 5785 F_LSO_FIRST_SLICE | F_LSO_LAST_SLICE | 5786 V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) | 5787 V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2); 5788 if (m0->m_pkthdr.l2hlen == sizeof(struct ether_vlan_header)) 5789 ctrl |= V_LSO_ETHHDR_LEN(1); 5790 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 5791 ctrl |= F_LSO_IPV6; 5792 lso->lso_ctrl = htobe32(ctrl); 5793 lso->ipid_ofst = htobe16(0); 5794 lso->mss = htobe16(m0->m_pkthdr.tso_segsz); 5795 lso->seqno_offset = htobe32(0); 5796 lso->len = htobe32(pktlen); 5797 5798 cpl = (void *)(lso + 1); 5799 } else { 5800 wr->u.tcpseg.mss = htobe16(0xffff); 5801 cpl = (void *)(wr + 1); 5802 } 5803 } 5804 5805 /* Checksum offload must be requested for ethofld. */ 5806 ctrl1 = 0; 5807 MPASS(needs_l4_csum(m0)); 5808 5809 /* VLAN tag insertion */ 5810 if (needs_vlan_insertion(m0)) { 5811 ctrl1 |= F_TXPKT_VLAN_VLD | 5812 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 5813 } 5814 5815 /* CPL header */ 5816 cpl->ctrl0 = cst->ctrl0; 5817 cpl->pack = 0; 5818 cpl->len = htobe16(pktlen); 5819 cpl->ctrl1 = htobe64(ctrl1); 5820 5821 /* Copy Ethernet, IP & TCP/UDP hdrs as immediate data */ 5822 p = (uintptr_t)(cpl + 1); 5823 m_copydata(m0, 0, immhdrs, (void *)p); 5824 5825 /* SGL */ 5826 dst = (void *)(cpl + 1); 5827 if (nsegs > 0) { 5828 int i, pad; 5829 5830 /* zero-pad upto next 16Byte boundary, if not 16Byte aligned */ 5831 p += immhdrs; 5832 pad = 16 - (immhdrs & 0xf); 5833 bzero((void *)p, pad); 5834 5835 usgl = (void *)(p + pad); 5836 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 5837 V_ULPTX_NSGE(nsegs)); 5838 5839 sglist_init(&sg, nitems(segs), segs); 5840 for (; m0 != NULL; m0 = m0->m_next) { 5841 if (__predict_false(m0->m_len == 0)) 5842 continue; 5843 if (immhdrs >= m0->m_len) { 5844 immhdrs -= m0->m_len; 5845 continue; 5846 } 5847 5848 sglist_append(&sg, mtod(m0, char *) + immhdrs, 5849 m0->m_len - immhdrs); 5850 immhdrs = 0; 5851 } 5852 MPASS(sg.sg_nseg == nsegs); 5853 5854 /* 5855 * Zero pad last 8B in case the WR doesn't end on a 16B 5856 * boundary. 5857 */ 5858 *(uint64_t *)((char *)wr + len16 * 16 - 8) = 0; 5859 5860 usgl->len0 = htobe32(segs[0].ss_len); 5861 usgl->addr0 = htobe64(segs[0].ss_paddr); 5862 for (i = 0; i < nsegs - 1; i++) { 5863 usgl->sge[i / 2].len[i & 1] = htobe32(segs[i + 1].ss_len); 5864 usgl->sge[i / 2].addr[i & 1] = htobe64(segs[i + 1].ss_paddr); 5865 } 5866 if (i & 1) 5867 usgl->sge[i / 2].len[1] = htobe32(0); 5868 } 5869 5870 } 5871 5872 static void 5873 ethofld_tx(struct cxgbe_snd_tag *cst) 5874 { 5875 struct mbuf *m; 5876 struct wrq_cookie cookie; 5877 int next_credits, compl; 5878 struct fw_eth_tx_eo_wr *wr; 5879 5880 mtx_assert(&cst->lock, MA_OWNED); 5881 5882 while ((m = mbufq_first(&cst->pending_tx)) != NULL) { 5883 M_ASSERTPKTHDR(m); 5884 5885 /* How many len16 credits do we need to send this mbuf. */ 5886 next_credits = mbuf_eo_len16(m); 5887 MPASS(next_credits > 0); 5888 if (next_credits > cst->tx_credits) { 5889 /* 5890 * Tx will make progress eventually because there is at 5891 * least one outstanding fw4_ack that will return 5892 * credits and kick the tx. 5893 */ 5894 MPASS(cst->ncompl > 0); 5895 return; 5896 } 5897 wr = start_wrq_wr(cst->eo_txq, next_credits, &cookie); 5898 if (__predict_false(wr == NULL)) { 5899 /* XXX: wishful thinking, not a real assertion. */ 5900 MPASS(cst->ncompl > 0); 5901 return; 5902 } 5903 cst->tx_credits -= next_credits; 5904 cst->tx_nocompl += next_credits; 5905 compl = cst->ncompl == 0 || cst->tx_nocompl >= cst->tx_total / 2; 5906 ETHER_BPF_MTAP(cst->com.ifp, m); 5907 write_ethofld_wr(cst, wr, m, compl); 5908 commit_wrq_wr(cst->eo_txq, wr, &cookie); 5909 if (compl) { 5910 cst->ncompl++; 5911 cst->tx_nocompl = 0; 5912 } 5913 (void) mbufq_dequeue(&cst->pending_tx); 5914 mbufq_enqueue(&cst->pending_fwack, m); 5915 } 5916 } 5917 5918 int 5919 ethofld_transmit(struct ifnet *ifp, struct mbuf *m0) 5920 { 5921 struct cxgbe_snd_tag *cst; 5922 int rc; 5923 5924 MPASS(m0->m_nextpkt == NULL); 5925 MPASS(m0->m_pkthdr.snd_tag != NULL); 5926 cst = mst_to_cst(m0->m_pkthdr.snd_tag); 5927 5928 mtx_lock(&cst->lock); 5929 MPASS(cst->flags & EO_SND_TAG_REF); 5930 5931 if (__predict_false(cst->flags & EO_FLOWC_PENDING)) { 5932 struct vi_info *vi = ifp->if_softc; 5933 struct port_info *pi = vi->pi; 5934 struct adapter *sc = pi->adapter; 5935 const uint32_t rss_mask = vi->rss_size - 1; 5936 uint32_t rss_hash; 5937 5938 cst->eo_txq = &sc->sge.ofld_txq[vi->first_ofld_txq]; 5939 if (M_HASHTYPE_ISHASH(m0)) 5940 rss_hash = m0->m_pkthdr.flowid; 5941 else 5942 rss_hash = arc4random(); 5943 /* We assume RSS hashing */ 5944 cst->iqid = vi->rss[rss_hash & rss_mask]; 5945 cst->eo_txq += rss_hash % vi->nofldtxq; 5946 rc = send_etid_flowc_wr(cst, pi, vi); 5947 if (rc != 0) 5948 goto done; 5949 } 5950 5951 if (__predict_false(cst->plen + m0->m_pkthdr.len > eo_max_backlog)) { 5952 rc = ENOBUFS; 5953 goto done; 5954 } 5955 5956 mbufq_enqueue(&cst->pending_tx, m0); 5957 cst->plen += m0->m_pkthdr.len; 5958 5959 ethofld_tx(cst); 5960 rc = 0; 5961 done: 5962 mtx_unlock(&cst->lock); 5963 if (__predict_false(rc != 0)) 5964 m_freem(m0); 5965 return (rc); 5966 } 5967 5968 static int 5969 ethofld_fw4_ack(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0) 5970 { 5971 struct adapter *sc = iq->adapter; 5972 const struct cpl_fw4_ack *cpl = (const void *)(rss + 1); 5973 struct mbuf *m; 5974 u_int etid = G_CPL_FW4_ACK_FLOWID(be32toh(OPCODE_TID(cpl))); 5975 struct cxgbe_snd_tag *cst; 5976 uint8_t credits = cpl->credits; 5977 5978 cst = lookup_etid(sc, etid); 5979 mtx_lock(&cst->lock); 5980 if (__predict_false(cst->flags & EO_FLOWC_RPL_PENDING)) { 5981 MPASS(credits >= ETID_FLOWC_LEN16); 5982 credits -= ETID_FLOWC_LEN16; 5983 cst->flags &= ~EO_FLOWC_RPL_PENDING; 5984 } 5985 5986 KASSERT(cst->ncompl > 0, 5987 ("%s: etid %u (%p) wasn't expecting completion.", 5988 __func__, etid, cst)); 5989 cst->ncompl--; 5990 5991 while (credits > 0) { 5992 m = mbufq_dequeue(&cst->pending_fwack); 5993 if (__predict_false(m == NULL)) { 5994 /* 5995 * The remaining credits are for the final flush that 5996 * was issued when the tag was freed by the kernel. 5997 */ 5998 MPASS((cst->flags & 5999 (EO_FLUSH_RPL_PENDING | EO_SND_TAG_REF)) == 6000 EO_FLUSH_RPL_PENDING); 6001 MPASS(credits == ETID_FLUSH_LEN16); 6002 MPASS(cst->tx_credits + cpl->credits == cst->tx_total); 6003 MPASS(cst->ncompl == 0); 6004 6005 cst->flags &= ~EO_FLUSH_RPL_PENDING; 6006 cst->tx_credits += cpl->credits; 6007 freetag: 6008 cxgbe_snd_tag_free_locked(cst); 6009 return (0); /* cst is gone. */ 6010 } 6011 KASSERT(m != NULL, 6012 ("%s: too many credits (%u, %u)", __func__, cpl->credits, 6013 credits)); 6014 KASSERT(credits >= mbuf_eo_len16(m), 6015 ("%s: too few credits (%u, %u, %u)", __func__, 6016 cpl->credits, credits, mbuf_eo_len16(m))); 6017 credits -= mbuf_eo_len16(m); 6018 cst->plen -= m->m_pkthdr.len; 6019 m_freem(m); 6020 } 6021 6022 cst->tx_credits += cpl->credits; 6023 MPASS(cst->tx_credits <= cst->tx_total); 6024 6025 m = mbufq_first(&cst->pending_tx); 6026 if (m != NULL && cst->tx_credits >= mbuf_eo_len16(m)) 6027 ethofld_tx(cst); 6028 6029 if (__predict_false((cst->flags & EO_SND_TAG_REF) == 0) && 6030 cst->ncompl == 0) { 6031 if (cst->tx_credits == cst->tx_total) 6032 goto freetag; 6033 else { 6034 MPASS((cst->flags & EO_FLUSH_RPL_PENDING) == 0); 6035 send_etid_flush_wr(cst); 6036 } 6037 } 6038 6039 mtx_unlock(&cst->lock); 6040 6041 return (0); 6042 } 6043 #endif 6044