1 /*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 34 #include <sys/types.h> 35 #include <sys/eventhandler.h> 36 #include <sys/mbuf.h> 37 #include <sys/socket.h> 38 #include <sys/kernel.h> 39 #include <sys/malloc.h> 40 #include <sys/queue.h> 41 #include <sys/sbuf.h> 42 #include <sys/taskqueue.h> 43 #include <sys/time.h> 44 #include <sys/sglist.h> 45 #include <sys/sysctl.h> 46 #include <sys/smp.h> 47 #include <sys/counter.h> 48 #include <net/bpf.h> 49 #include <net/ethernet.h> 50 #include <net/if.h> 51 #include <net/if_vlan_var.h> 52 #include <netinet/in.h> 53 #include <netinet/ip.h> 54 #include <netinet/ip6.h> 55 #include <netinet/tcp.h> 56 #include <machine/in_cksum.h> 57 #include <machine/md_var.h> 58 #include <vm/vm.h> 59 #include <vm/pmap.h> 60 #ifdef DEV_NETMAP 61 #include <machine/bus.h> 62 #include <sys/selinfo.h> 63 #include <net/if_var.h> 64 #include <net/netmap.h> 65 #include <dev/netmap/netmap_kern.h> 66 #endif 67 68 #include "common/common.h" 69 #include "common/t4_regs.h" 70 #include "common/t4_regs_values.h" 71 #include "common/t4_msg.h" 72 #include "t4_l2t.h" 73 #include "t4_mp_ring.h" 74 75 #ifdef T4_PKT_TIMESTAMP 76 #define RX_COPY_THRESHOLD (MINCLSIZE - 8) 77 #else 78 #define RX_COPY_THRESHOLD MINCLSIZE 79 #endif 80 81 /* 82 * Ethernet frames are DMA'd at this byte offset into the freelist buffer. 83 * 0-7 are valid values. 84 */ 85 static int fl_pktshift = 2; 86 TUNABLE_INT("hw.cxgbe.fl_pktshift", &fl_pktshift); 87 88 /* 89 * Pad ethernet payload up to this boundary. 90 * -1: driver should figure out a good value. 91 * 0: disable padding. 92 * Any power of 2 from 32 to 4096 (both inclusive) is also a valid value. 93 */ 94 int fl_pad = -1; 95 TUNABLE_INT("hw.cxgbe.fl_pad", &fl_pad); 96 97 /* 98 * Status page length. 99 * -1: driver should figure out a good value. 100 * 64 or 128 are the only other valid values. 101 */ 102 static int spg_len = -1; 103 TUNABLE_INT("hw.cxgbe.spg_len", &spg_len); 104 105 /* 106 * Congestion drops. 107 * -1: no congestion feedback (not recommended). 108 * 0: backpressure the channel instead of dropping packets right away. 109 * 1: no backpressure, drop packets for the congested queue immediately. 110 */ 111 static int cong_drop = 0; 112 TUNABLE_INT("hw.cxgbe.cong_drop", &cong_drop); 113 114 /* 115 * Deliver multiple frames in the same free list buffer if they fit. 116 * -1: let the driver decide whether to enable buffer packing or not. 117 * 0: disable buffer packing. 118 * 1: enable buffer packing. 119 */ 120 static int buffer_packing = -1; 121 TUNABLE_INT("hw.cxgbe.buffer_packing", &buffer_packing); 122 123 /* 124 * Start next frame in a packed buffer at this boundary. 125 * -1: driver should figure out a good value. 126 * T4: driver will ignore this and use the same value as fl_pad above. 127 * T5: 16, or a power of 2 from 64 to 4096 (both inclusive) is a valid value. 128 */ 129 static int fl_pack = -1; 130 TUNABLE_INT("hw.cxgbe.fl_pack", &fl_pack); 131 132 /* 133 * Allow the driver to create mbuf(s) in a cluster allocated for rx. 134 * 0: never; always allocate mbufs from the zone_mbuf UMA zone. 135 * 1: ok to create mbuf(s) within a cluster if there is room. 136 */ 137 static int allow_mbufs_in_cluster = 1; 138 TUNABLE_INT("hw.cxgbe.allow_mbufs_in_cluster", &allow_mbufs_in_cluster); 139 140 /* 141 * Largest rx cluster size that the driver is allowed to allocate. 142 */ 143 static int largest_rx_cluster = MJUM16BYTES; 144 TUNABLE_INT("hw.cxgbe.largest_rx_cluster", &largest_rx_cluster); 145 146 /* 147 * Size of cluster allocation that's most likely to succeed. The driver will 148 * fall back to this size if it fails to allocate clusters larger than this. 149 */ 150 static int safest_rx_cluster = PAGE_SIZE; 151 TUNABLE_INT("hw.cxgbe.safest_rx_cluster", &safest_rx_cluster); 152 153 /* 154 * The interrupt holdoff timers are multiplied by this value on T6+. 155 * 1 and 3-17 (both inclusive) are legal values. 156 */ 157 static int tscale = 1; 158 TUNABLE_INT("hw.cxgbe.tscale", &tscale); 159 160 /* 161 * Number of LRO entries in the lro_ctrl structure per rx queue. 162 */ 163 static int lro_entries = TCP_LRO_ENTRIES; 164 TUNABLE_INT("hw.cxgbe.lro_entries", &lro_entries); 165 166 /* 167 * This enables presorting of frames before they're fed into tcp_lro_rx. 168 */ 169 static int lro_mbufs = 0; 170 TUNABLE_INT("hw.cxgbe.lro_mbufs", &lro_mbufs); 171 172 struct txpkts { 173 u_int wr_type; /* type 0 or type 1 */ 174 u_int npkt; /* # of packets in this work request */ 175 u_int plen; /* total payload (sum of all packets) */ 176 u_int len16; /* # of 16B pieces used by this work request */ 177 }; 178 179 /* A packet's SGL. This + m_pkthdr has all info needed for tx */ 180 struct sgl { 181 struct sglist sg; 182 struct sglist_seg seg[TX_SGL_SEGS]; 183 }; 184 185 static int service_iq(struct sge_iq *, int); 186 static struct mbuf *get_fl_payload(struct adapter *, struct sge_fl *, uint32_t); 187 static int t4_eth_rx(struct sge_iq *, const struct rss_header *, struct mbuf *); 188 static inline void init_iq(struct sge_iq *, struct adapter *, int, int, int); 189 static inline void init_fl(struct adapter *, struct sge_fl *, int, int, char *); 190 static inline void init_eq(struct adapter *, struct sge_eq *, int, int, uint8_t, 191 uint16_t, char *); 192 static int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *, 193 bus_addr_t *, void **); 194 static int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 195 void *); 196 static int alloc_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *, 197 int, int); 198 static int free_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *); 199 static void add_fl_sysctls(struct adapter *, struct sysctl_ctx_list *, 200 struct sysctl_oid *, struct sge_fl *); 201 static int alloc_fwq(struct adapter *); 202 static int free_fwq(struct adapter *); 203 static int alloc_mgmtq(struct adapter *); 204 static int free_mgmtq(struct adapter *); 205 static int alloc_rxq(struct vi_info *, struct sge_rxq *, int, int, 206 struct sysctl_oid *); 207 static int free_rxq(struct vi_info *, struct sge_rxq *); 208 #ifdef TCP_OFFLOAD 209 static int alloc_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *, int, int, 210 struct sysctl_oid *); 211 static int free_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *); 212 #endif 213 #ifdef DEV_NETMAP 214 static int alloc_nm_rxq(struct vi_info *, struct sge_nm_rxq *, int, int, 215 struct sysctl_oid *); 216 static int free_nm_rxq(struct vi_info *, struct sge_nm_rxq *); 217 static int alloc_nm_txq(struct vi_info *, struct sge_nm_txq *, int, int, 218 struct sysctl_oid *); 219 static int free_nm_txq(struct vi_info *, struct sge_nm_txq *); 220 #endif 221 static int ctrl_eq_alloc(struct adapter *, struct sge_eq *); 222 static int eth_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *); 223 #ifdef TCP_OFFLOAD 224 static int ofld_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *); 225 #endif 226 static int alloc_eq(struct adapter *, struct vi_info *, struct sge_eq *); 227 static int free_eq(struct adapter *, struct sge_eq *); 228 static int alloc_wrq(struct adapter *, struct vi_info *, struct sge_wrq *, 229 struct sysctl_oid *); 230 static int free_wrq(struct adapter *, struct sge_wrq *); 231 static int alloc_txq(struct vi_info *, struct sge_txq *, int, 232 struct sysctl_oid *); 233 static int free_txq(struct vi_info *, struct sge_txq *); 234 static void oneseg_dma_callback(void *, bus_dma_segment_t *, int, int); 235 static inline void ring_fl_db(struct adapter *, struct sge_fl *); 236 static int refill_fl(struct adapter *, struct sge_fl *, int); 237 static void refill_sfl(void *); 238 static int alloc_fl_sdesc(struct sge_fl *); 239 static void free_fl_sdesc(struct adapter *, struct sge_fl *); 240 static void find_best_refill_source(struct adapter *, struct sge_fl *, int); 241 static void find_safe_refill_source(struct adapter *, struct sge_fl *); 242 static void add_fl_to_sfl(struct adapter *, struct sge_fl *); 243 244 static inline void get_pkt_gl(struct mbuf *, struct sglist *); 245 static inline u_int txpkt_len16(u_int, u_int); 246 static inline u_int txpkt_vm_len16(u_int, u_int); 247 static inline u_int txpkts0_len16(u_int); 248 static inline u_int txpkts1_len16(void); 249 static u_int write_txpkt_wr(struct sge_txq *, struct fw_eth_tx_pkt_wr *, 250 struct mbuf *, u_int); 251 static u_int write_txpkt_vm_wr(struct adapter *, struct sge_txq *, 252 struct fw_eth_tx_pkt_vm_wr *, struct mbuf *, u_int); 253 static int try_txpkts(struct mbuf *, struct mbuf *, struct txpkts *, u_int); 254 static int add_to_txpkts(struct mbuf *, struct txpkts *, u_int); 255 static u_int write_txpkts_wr(struct sge_txq *, struct fw_eth_tx_pkts_wr *, 256 struct mbuf *, const struct txpkts *, u_int); 257 static void write_gl_to_txd(struct sge_txq *, struct mbuf *, caddr_t *, int); 258 static inline void copy_to_txd(struct sge_eq *, caddr_t, caddr_t *, int); 259 static inline void ring_eq_db(struct adapter *, struct sge_eq *, u_int); 260 static inline uint16_t read_hw_cidx(struct sge_eq *); 261 static inline u_int reclaimable_tx_desc(struct sge_eq *); 262 static inline u_int total_available_tx_desc(struct sge_eq *); 263 static u_int reclaim_tx_descs(struct sge_txq *, u_int); 264 static void tx_reclaim(void *, int); 265 static __be64 get_flit(struct sglist_seg *, int, int); 266 static int handle_sge_egr_update(struct sge_iq *, const struct rss_header *, 267 struct mbuf *); 268 static int handle_fw_msg(struct sge_iq *, const struct rss_header *, 269 struct mbuf *); 270 static int t4_handle_wrerr_rpl(struct adapter *, const __be64 *); 271 static void wrq_tx_drain(void *, int); 272 static void drain_wrq_wr_list(struct adapter *, struct sge_wrq *); 273 274 static int sysctl_uint16(SYSCTL_HANDLER_ARGS); 275 static int sysctl_bufsizes(SYSCTL_HANDLER_ARGS); 276 static int sysctl_tc(SYSCTL_HANDLER_ARGS); 277 278 static counter_u64_t extfree_refs; 279 static counter_u64_t extfree_rels; 280 281 an_handler_t t4_an_handler; 282 fw_msg_handler_t t4_fw_msg_handler[NUM_FW6_TYPES]; 283 cpl_handler_t t4_cpl_handler[NUM_CPL_CMDS]; 284 285 286 static int 287 an_not_handled(struct sge_iq *iq, const struct rsp_ctrl *ctrl) 288 { 289 290 #ifdef INVARIANTS 291 panic("%s: async notification on iq %p (ctrl %p)", __func__, iq, ctrl); 292 #else 293 log(LOG_ERR, "%s: async notification on iq %p (ctrl %p)\n", 294 __func__, iq, ctrl); 295 #endif 296 return (EDOOFUS); 297 } 298 299 int 300 t4_register_an_handler(an_handler_t h) 301 { 302 uintptr_t *loc, new; 303 304 new = h ? (uintptr_t)h : (uintptr_t)an_not_handled; 305 loc = (uintptr_t *) &t4_an_handler; 306 atomic_store_rel_ptr(loc, new); 307 308 return (0); 309 } 310 311 static int 312 fw_msg_not_handled(struct adapter *sc, const __be64 *rpl) 313 { 314 const struct cpl_fw6_msg *cpl = 315 __containerof(rpl, struct cpl_fw6_msg, data[0]); 316 317 #ifdef INVARIANTS 318 panic("%s: fw_msg type %d", __func__, cpl->type); 319 #else 320 log(LOG_ERR, "%s: fw_msg type %d\n", __func__, cpl->type); 321 #endif 322 return (EDOOFUS); 323 } 324 325 int 326 t4_register_fw_msg_handler(int type, fw_msg_handler_t h) 327 { 328 uintptr_t *loc, new; 329 330 if (type >= nitems(t4_fw_msg_handler)) 331 return (EINVAL); 332 333 /* 334 * These are dispatched by the handler for FW{4|6}_CPL_MSG using the CPL 335 * handler dispatch table. Reject any attempt to install a handler for 336 * this subtype. 337 */ 338 if (type == FW_TYPE_RSSCPL || type == FW6_TYPE_RSSCPL) 339 return (EINVAL); 340 341 new = h ? (uintptr_t)h : (uintptr_t)fw_msg_not_handled; 342 loc = (uintptr_t *) &t4_fw_msg_handler[type]; 343 atomic_store_rel_ptr(loc, new); 344 345 return (0); 346 } 347 348 static int 349 cpl_not_handled(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 350 { 351 352 #ifdef INVARIANTS 353 panic("%s: opcode 0x%02x on iq %p with payload %p", 354 __func__, rss->opcode, iq, m); 355 #else 356 log(LOG_ERR, "%s: opcode 0x%02x on iq %p with payload %p\n", 357 __func__, rss->opcode, iq, m); 358 m_freem(m); 359 #endif 360 return (EDOOFUS); 361 } 362 363 int 364 t4_register_cpl_handler(int opcode, cpl_handler_t h) 365 { 366 uintptr_t *loc, new; 367 368 if (opcode >= nitems(t4_cpl_handler)) 369 return (EINVAL); 370 371 new = h ? (uintptr_t)h : (uintptr_t)cpl_not_handled; 372 loc = (uintptr_t *) &t4_cpl_handler[opcode]; 373 atomic_store_rel_ptr(loc, new); 374 375 return (0); 376 } 377 378 /* 379 * Called on MOD_LOAD. Validates and calculates the SGE tunables. 380 */ 381 void 382 t4_sge_modload(void) 383 { 384 int i; 385 386 if (fl_pktshift < 0 || fl_pktshift > 7) { 387 printf("Invalid hw.cxgbe.fl_pktshift value (%d)," 388 " using 2 instead.\n", fl_pktshift); 389 fl_pktshift = 2; 390 } 391 392 if (spg_len != 64 && spg_len != 128) { 393 int len; 394 395 #if defined(__i386__) || defined(__amd64__) 396 len = cpu_clflush_line_size > 64 ? 128 : 64; 397 #else 398 len = 64; 399 #endif 400 if (spg_len != -1) { 401 printf("Invalid hw.cxgbe.spg_len value (%d)," 402 " using %d instead.\n", spg_len, len); 403 } 404 spg_len = len; 405 } 406 407 if (cong_drop < -1 || cong_drop > 1) { 408 printf("Invalid hw.cxgbe.cong_drop value (%d)," 409 " using 0 instead.\n", cong_drop); 410 cong_drop = 0; 411 } 412 413 if (tscale != 1 && (tscale < 3 || tscale > 17)) { 414 printf("Invalid hw.cxgbe.tscale value (%d)," 415 " using 1 instead.\n", tscale); 416 tscale = 1; 417 } 418 419 extfree_refs = counter_u64_alloc(M_WAITOK); 420 extfree_rels = counter_u64_alloc(M_WAITOK); 421 counter_u64_zero(extfree_refs); 422 counter_u64_zero(extfree_rels); 423 424 t4_an_handler = an_not_handled; 425 for (i = 0; i < nitems(t4_fw_msg_handler); i++) 426 t4_fw_msg_handler[i] = fw_msg_not_handled; 427 for (i = 0; i < nitems(t4_cpl_handler); i++) 428 t4_cpl_handler[i] = cpl_not_handled; 429 430 t4_register_cpl_handler(CPL_FW4_MSG, handle_fw_msg); 431 t4_register_cpl_handler(CPL_FW6_MSG, handle_fw_msg); 432 t4_register_cpl_handler(CPL_SGE_EGR_UPDATE, handle_sge_egr_update); 433 t4_register_cpl_handler(CPL_RX_PKT, t4_eth_rx); 434 t4_register_fw_msg_handler(FW6_TYPE_CMD_RPL, t4_handle_fw_rpl); 435 t4_register_fw_msg_handler(FW6_TYPE_WRERR_RPL, t4_handle_wrerr_rpl); 436 } 437 438 void 439 t4_sge_modunload(void) 440 { 441 442 counter_u64_free(extfree_refs); 443 counter_u64_free(extfree_rels); 444 } 445 446 uint64_t 447 t4_sge_extfree_refs(void) 448 { 449 uint64_t refs, rels; 450 451 rels = counter_u64_fetch(extfree_rels); 452 refs = counter_u64_fetch(extfree_refs); 453 454 return (refs - rels); 455 } 456 457 static inline void 458 setup_pad_and_pack_boundaries(struct adapter *sc) 459 { 460 uint32_t v, m; 461 int pad, pack, pad_shift; 462 463 pad_shift = chip_id(sc) > CHELSIO_T5 ? X_T6_INGPADBOUNDARY_SHIFT : 464 X_INGPADBOUNDARY_SHIFT; 465 pad = fl_pad; 466 if (fl_pad < (1 << pad_shift) || 467 fl_pad > (1 << (pad_shift + M_INGPADBOUNDARY)) || 468 !powerof2(fl_pad)) { 469 /* 470 * If there is any chance that we might use buffer packing and 471 * the chip is a T4, then pick 64 as the pad/pack boundary. Set 472 * it to the minimum allowed in all other cases. 473 */ 474 pad = is_t4(sc) && buffer_packing ? 64 : 1 << pad_shift; 475 476 /* 477 * For fl_pad = 0 we'll still write a reasonable value to the 478 * register but all the freelists will opt out of padding. 479 * We'll complain here only if the user tried to set it to a 480 * value greater than 0 that was invalid. 481 */ 482 if (fl_pad > 0) { 483 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pad value" 484 " (%d), using %d instead.\n", fl_pad, pad); 485 } 486 } 487 m = V_INGPADBOUNDARY(M_INGPADBOUNDARY); 488 v = V_INGPADBOUNDARY(ilog2(pad) - pad_shift); 489 t4_set_reg_field(sc, A_SGE_CONTROL, m, v); 490 491 if (is_t4(sc)) { 492 if (fl_pack != -1 && fl_pack != pad) { 493 /* Complain but carry on. */ 494 device_printf(sc->dev, "hw.cxgbe.fl_pack (%d) ignored," 495 " using %d instead.\n", fl_pack, pad); 496 } 497 return; 498 } 499 500 pack = fl_pack; 501 if (fl_pack < 16 || fl_pack == 32 || fl_pack > 4096 || 502 !powerof2(fl_pack)) { 503 pack = max(sc->params.pci.mps, CACHE_LINE_SIZE); 504 MPASS(powerof2(pack)); 505 if (pack < 16) 506 pack = 16; 507 if (pack == 32) 508 pack = 64; 509 if (pack > 4096) 510 pack = 4096; 511 if (fl_pack != -1) { 512 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pack value" 513 " (%d), using %d instead.\n", fl_pack, pack); 514 } 515 } 516 m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY); 517 if (pack == 16) 518 v = V_INGPACKBOUNDARY(0); 519 else 520 v = V_INGPACKBOUNDARY(ilog2(pack) - 5); 521 522 MPASS(!is_t4(sc)); /* T4 doesn't have SGE_CONTROL2 */ 523 t4_set_reg_field(sc, A_SGE_CONTROL2, m, v); 524 } 525 526 /* 527 * adap->params.vpd.cclk must be set up before this is called. 528 */ 529 void 530 t4_tweak_chip_settings(struct adapter *sc) 531 { 532 int i; 533 uint32_t v, m; 534 int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200}; 535 int timer_max = M_TIMERVALUE0 * 1000 / sc->params.vpd.cclk; 536 int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */ 537 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 538 static int sge_flbuf_sizes[] = { 539 MCLBYTES, 540 #if MJUMPAGESIZE != MCLBYTES 541 MJUMPAGESIZE, 542 MJUMPAGESIZE - CL_METADATA_SIZE, 543 MJUMPAGESIZE - 2 * MSIZE - CL_METADATA_SIZE, 544 #endif 545 MJUM9BYTES, 546 MJUM16BYTES, 547 MCLBYTES - MSIZE - CL_METADATA_SIZE, 548 MJUM9BYTES - CL_METADATA_SIZE, 549 MJUM16BYTES - CL_METADATA_SIZE, 550 }; 551 552 KASSERT(sc->flags & MASTER_PF, 553 ("%s: trying to change chip settings when not master.", __func__)); 554 555 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE; 556 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE | 557 V_EGRSTATUSPAGESIZE(spg_len == 128); 558 t4_set_reg_field(sc, A_SGE_CONTROL, m, v); 559 560 setup_pad_and_pack_boundaries(sc); 561 562 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) | 563 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) | 564 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) | 565 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) | 566 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) | 567 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) | 568 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) | 569 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10); 570 t4_write_reg(sc, A_SGE_HOST_PAGE_SIZE, v); 571 572 KASSERT(nitems(sge_flbuf_sizes) <= SGE_FLBUF_SIZES, 573 ("%s: hw buffer size table too big", __func__)); 574 for (i = 0; i < min(nitems(sge_flbuf_sizes), SGE_FLBUF_SIZES); i++) { 575 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0 + (4 * i), 576 sge_flbuf_sizes[i]); 577 } 578 579 v = V_THRESHOLD_0(intr_pktcount[0]) | V_THRESHOLD_1(intr_pktcount[1]) | 580 V_THRESHOLD_2(intr_pktcount[2]) | V_THRESHOLD_3(intr_pktcount[3]); 581 t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD, v); 582 583 KASSERT(intr_timer[0] <= timer_max, 584 ("%s: not a single usable timer (%d, %d)", __func__, intr_timer[0], 585 timer_max)); 586 for (i = 1; i < nitems(intr_timer); i++) { 587 KASSERT(intr_timer[i] >= intr_timer[i - 1], 588 ("%s: timers not listed in increasing order (%d)", 589 __func__, i)); 590 591 while (intr_timer[i] > timer_max) { 592 if (i == nitems(intr_timer) - 1) { 593 intr_timer[i] = timer_max; 594 break; 595 } 596 intr_timer[i] += intr_timer[i - 1]; 597 intr_timer[i] /= 2; 598 } 599 } 600 601 v = V_TIMERVALUE0(us_to_core_ticks(sc, intr_timer[0])) | 602 V_TIMERVALUE1(us_to_core_ticks(sc, intr_timer[1])); 603 t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1, v); 604 v = V_TIMERVALUE2(us_to_core_ticks(sc, intr_timer[2])) | 605 V_TIMERVALUE3(us_to_core_ticks(sc, intr_timer[3])); 606 t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3, v); 607 v = V_TIMERVALUE4(us_to_core_ticks(sc, intr_timer[4])) | 608 V_TIMERVALUE5(us_to_core_ticks(sc, intr_timer[5])); 609 t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5, v); 610 611 if (chip_id(sc) >= CHELSIO_T6) { 612 m = V_TSCALE(M_TSCALE); 613 if (tscale == 1) 614 v = 0; 615 else 616 v = V_TSCALE(tscale - 2); 617 t4_set_reg_field(sc, A_SGE_ITP_CONTROL, m, v); 618 } 619 620 /* 4K, 16K, 64K, 256K DDP "page sizes" for TDDP */ 621 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 622 t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, v); 623 624 /* 625 * 4K, 8K, 16K, 64K DDP "page sizes" for iSCSI DDP. These have been 626 * chosen with MAXPHYS = 128K in mind. The largest DDP buffer that we 627 * may have to deal with is MAXPHYS + 1 page. 628 */ 629 v = V_HPZ0(0) | V_HPZ1(1) | V_HPZ2(2) | V_HPZ3(4); 630 t4_write_reg(sc, A_ULP_RX_ISCSI_PSZ, v); 631 632 /* We use multiple DDP page sizes both in plain-TOE and ISCSI modes. */ 633 m = v = F_TDDPTAGTCB | F_ISCSITAGTCB; 634 t4_set_reg_field(sc, A_ULP_RX_CTL, m, v); 635 636 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 637 F_RESETDDPOFFSET; 638 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 639 t4_set_reg_field(sc, A_TP_PARA_REG5, m, v); 640 } 641 642 /* 643 * SGE wants the buffer to be at least 64B and then a multiple of 16. If 644 * padding is in use, the buffer's start and end need to be aligned to the pad 645 * boundary as well. We'll just make sure that the size is a multiple of the 646 * boundary here, it is up to the buffer allocation code to make sure the start 647 * of the buffer is aligned as well. 648 */ 649 static inline int 650 hwsz_ok(struct adapter *sc, int hwsz) 651 { 652 int mask = fl_pad ? sc->params.sge.pad_boundary - 1 : 16 - 1; 653 654 return (hwsz >= 64 && (hwsz & mask) == 0); 655 } 656 657 /* 658 * XXX: driver really should be able to deal with unexpected settings. 659 */ 660 int 661 t4_read_chip_settings(struct adapter *sc) 662 { 663 struct sge *s = &sc->sge; 664 struct sge_params *sp = &sc->params.sge; 665 int i, j, n, rc = 0; 666 uint32_t m, v, r; 667 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 668 static int sw_buf_sizes[] = { /* Sorted by size */ 669 MCLBYTES, 670 #if MJUMPAGESIZE != MCLBYTES 671 MJUMPAGESIZE, 672 #endif 673 MJUM9BYTES, 674 MJUM16BYTES 675 }; 676 struct sw_zone_info *swz, *safe_swz; 677 struct hw_buf_info *hwb; 678 679 m = F_RXPKTCPLMODE; 680 v = F_RXPKTCPLMODE; 681 r = sc->params.sge.sge_control; 682 if ((r & m) != v) { 683 device_printf(sc->dev, "invalid SGE_CONTROL(0x%x)\n", r); 684 rc = EINVAL; 685 } 686 687 /* 688 * If this changes then every single use of PAGE_SHIFT in the driver 689 * needs to be carefully reviewed for PAGE_SHIFT vs sp->page_shift. 690 */ 691 if (sp->page_shift != PAGE_SHIFT) { 692 device_printf(sc->dev, "invalid SGE_HOST_PAGE_SIZE(0x%x)\n", r); 693 rc = EINVAL; 694 } 695 696 /* Filter out unusable hw buffer sizes entirely (mark with -2). */ 697 hwb = &s->hw_buf_info[0]; 698 for (i = 0; i < nitems(s->hw_buf_info); i++, hwb++) { 699 r = sc->params.sge.sge_fl_buffer_size[i]; 700 hwb->size = r; 701 hwb->zidx = hwsz_ok(sc, r) ? -1 : -2; 702 hwb->next = -1; 703 } 704 705 /* 706 * Create a sorted list in decreasing order of hw buffer sizes (and so 707 * increasing order of spare area) for each software zone. 708 * 709 * If padding is enabled then the start and end of the buffer must align 710 * to the pad boundary; if packing is enabled then they must align with 711 * the pack boundary as well. Allocations from the cluster zones are 712 * aligned to min(size, 4K), so the buffer starts at that alignment and 713 * ends at hwb->size alignment. If mbuf inlining is allowed the 714 * starting alignment will be reduced to MSIZE and the driver will 715 * exercise appropriate caution when deciding on the best buffer layout 716 * to use. 717 */ 718 n = 0; /* no usable buffer size to begin with */ 719 swz = &s->sw_zone_info[0]; 720 safe_swz = NULL; 721 for (i = 0; i < SW_ZONE_SIZES; i++, swz++) { 722 int8_t head = -1, tail = -1; 723 724 swz->size = sw_buf_sizes[i]; 725 swz->zone = m_getzone(swz->size); 726 swz->type = m_gettype(swz->size); 727 728 if (swz->size < PAGE_SIZE) { 729 MPASS(powerof2(swz->size)); 730 if (fl_pad && (swz->size % sp->pad_boundary != 0)) 731 continue; 732 } 733 734 if (swz->size == safest_rx_cluster) 735 safe_swz = swz; 736 737 hwb = &s->hw_buf_info[0]; 738 for (j = 0; j < SGE_FLBUF_SIZES; j++, hwb++) { 739 if (hwb->zidx != -1 || hwb->size > swz->size) 740 continue; 741 #ifdef INVARIANTS 742 if (fl_pad) 743 MPASS(hwb->size % sp->pad_boundary == 0); 744 #endif 745 hwb->zidx = i; 746 if (head == -1) 747 head = tail = j; 748 else if (hwb->size < s->hw_buf_info[tail].size) { 749 s->hw_buf_info[tail].next = j; 750 tail = j; 751 } else { 752 int8_t *cur; 753 struct hw_buf_info *t; 754 755 for (cur = &head; *cur != -1; cur = &t->next) { 756 t = &s->hw_buf_info[*cur]; 757 if (hwb->size == t->size) { 758 hwb->zidx = -2; 759 break; 760 } 761 if (hwb->size > t->size) { 762 hwb->next = *cur; 763 *cur = j; 764 break; 765 } 766 } 767 } 768 } 769 swz->head_hwidx = head; 770 swz->tail_hwidx = tail; 771 772 if (tail != -1) { 773 n++; 774 if (swz->size - s->hw_buf_info[tail].size >= 775 CL_METADATA_SIZE) 776 sc->flags |= BUF_PACKING_OK; 777 } 778 } 779 if (n == 0) { 780 device_printf(sc->dev, "no usable SGE FL buffer size.\n"); 781 rc = EINVAL; 782 } 783 784 s->safe_hwidx1 = -1; 785 s->safe_hwidx2 = -1; 786 if (safe_swz != NULL) { 787 s->safe_hwidx1 = safe_swz->head_hwidx; 788 for (i = safe_swz->head_hwidx; i != -1; i = hwb->next) { 789 int spare; 790 791 hwb = &s->hw_buf_info[i]; 792 #ifdef INVARIANTS 793 if (fl_pad) 794 MPASS(hwb->size % sp->pad_boundary == 0); 795 #endif 796 spare = safe_swz->size - hwb->size; 797 if (spare >= CL_METADATA_SIZE) { 798 s->safe_hwidx2 = i; 799 break; 800 } 801 } 802 } 803 804 if (sc->flags & IS_VF) 805 return (0); 806 807 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 808 r = t4_read_reg(sc, A_ULP_RX_TDDP_PSZ); 809 if (r != v) { 810 device_printf(sc->dev, "invalid ULP_RX_TDDP_PSZ(0x%x)\n", r); 811 rc = EINVAL; 812 } 813 814 m = v = F_TDDPTAGTCB; 815 r = t4_read_reg(sc, A_ULP_RX_CTL); 816 if ((r & m) != v) { 817 device_printf(sc->dev, "invalid ULP_RX_CTL(0x%x)\n", r); 818 rc = EINVAL; 819 } 820 821 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 822 F_RESETDDPOFFSET; 823 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 824 r = t4_read_reg(sc, A_TP_PARA_REG5); 825 if ((r & m) != v) { 826 device_printf(sc->dev, "invalid TP_PARA_REG5(0x%x)\n", r); 827 rc = EINVAL; 828 } 829 830 t4_init_tp_params(sc); 831 832 t4_read_mtu_tbl(sc, sc->params.mtus, NULL); 833 t4_load_mtus(sc, sc->params.mtus, sc->params.a_wnd, sc->params.b_wnd); 834 835 return (rc); 836 } 837 838 int 839 t4_create_dma_tag(struct adapter *sc) 840 { 841 int rc; 842 843 rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0, 844 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE, 845 BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL, 846 NULL, &sc->dmat); 847 if (rc != 0) { 848 device_printf(sc->dev, 849 "failed to create main DMA tag: %d\n", rc); 850 } 851 852 return (rc); 853 } 854 855 void 856 t4_sge_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx, 857 struct sysctl_oid_list *children) 858 { 859 struct sge_params *sp = &sc->params.sge; 860 861 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "buffer_sizes", 862 CTLTYPE_STRING | CTLFLAG_RD, &sc->sge, 0, sysctl_bufsizes, "A", 863 "freelist buffer sizes"); 864 865 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pktshift", CTLFLAG_RD, 866 NULL, sp->fl_pktshift, "payload DMA offset in rx buffer (bytes)"); 867 868 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pad", CTLFLAG_RD, 869 NULL, sp->pad_boundary, "payload pad boundary (bytes)"); 870 871 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "spg_len", CTLFLAG_RD, 872 NULL, sp->spg_len, "status page size (bytes)"); 873 874 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_drop", CTLFLAG_RD, 875 NULL, cong_drop, "congestion drop setting"); 876 877 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pack", CTLFLAG_RD, 878 NULL, sp->pack_boundary, "payload pack boundary (bytes)"); 879 } 880 881 int 882 t4_destroy_dma_tag(struct adapter *sc) 883 { 884 if (sc->dmat) 885 bus_dma_tag_destroy(sc->dmat); 886 887 return (0); 888 } 889 890 /* 891 * Allocate and initialize the firmware event queue and the management queue. 892 * 893 * Returns errno on failure. Resources allocated up to that point may still be 894 * allocated. Caller is responsible for cleanup in case this function fails. 895 */ 896 int 897 t4_setup_adapter_queues(struct adapter *sc) 898 { 899 int rc; 900 901 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 902 903 sysctl_ctx_init(&sc->ctx); 904 sc->flags |= ADAP_SYSCTL_CTX; 905 906 /* 907 * Firmware event queue 908 */ 909 rc = alloc_fwq(sc); 910 if (rc != 0) 911 return (rc); 912 913 /* 914 * Management queue. This is just a control queue that uses the fwq as 915 * its associated iq. 916 */ 917 if (!(sc->flags & IS_VF)) 918 rc = alloc_mgmtq(sc); 919 920 return (rc); 921 } 922 923 /* 924 * Idempotent 925 */ 926 int 927 t4_teardown_adapter_queues(struct adapter *sc) 928 { 929 930 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 931 932 /* Do this before freeing the queue */ 933 if (sc->flags & ADAP_SYSCTL_CTX) { 934 sysctl_ctx_free(&sc->ctx); 935 sc->flags &= ~ADAP_SYSCTL_CTX; 936 } 937 938 free_mgmtq(sc); 939 free_fwq(sc); 940 941 return (0); 942 } 943 944 static inline int 945 first_vector(struct vi_info *vi) 946 { 947 struct adapter *sc = vi->pi->adapter; 948 949 if (sc->intr_count == 1) 950 return (0); 951 952 return (vi->first_intr); 953 } 954 955 /* 956 * Given an arbitrary "index," come up with an iq that can be used by other 957 * queues (of this VI) for interrupt forwarding, SGE egress updates, etc. 958 * The iq returned is guaranteed to be something that takes direct interrupts. 959 */ 960 static struct sge_iq * 961 vi_intr_iq(struct vi_info *vi, int idx) 962 { 963 struct adapter *sc = vi->pi->adapter; 964 struct sge *s = &sc->sge; 965 struct sge_iq *iq = NULL; 966 int nintr, i; 967 968 if (sc->intr_count == 1) 969 return (&sc->sge.fwq); 970 971 nintr = vi->nintr; 972 KASSERT(nintr != 0, 973 ("%s: vi %p has no exclusive interrupts, total interrupts = %d", 974 __func__, vi, sc->intr_count)); 975 i = idx % nintr; 976 977 if (vi->flags & INTR_RXQ) { 978 if (i < vi->nrxq) { 979 iq = &s->rxq[vi->first_rxq + i].iq; 980 goto done; 981 } 982 i -= vi->nrxq; 983 } 984 #ifdef TCP_OFFLOAD 985 if (vi->flags & INTR_OFLD_RXQ) { 986 if (i < vi->nofldrxq) { 987 iq = &s->ofld_rxq[vi->first_ofld_rxq + i].iq; 988 goto done; 989 } 990 i -= vi->nofldrxq; 991 } 992 #endif 993 panic("%s: vi %p, intr_flags 0x%lx, idx %d, total intr %d\n", __func__, 994 vi, vi->flags & INTR_ALL, idx, nintr); 995 done: 996 MPASS(iq != NULL); 997 KASSERT(iq->flags & IQ_INTR, 998 ("%s: iq %p (vi %p, intr_flags 0x%lx, idx %d)", __func__, iq, vi, 999 vi->flags & INTR_ALL, idx)); 1000 return (iq); 1001 } 1002 1003 /* Maximum payload that can be delivered with a single iq descriptor */ 1004 static inline int 1005 mtu_to_max_payload(struct adapter *sc, int mtu, const int toe) 1006 { 1007 int payload; 1008 1009 #ifdef TCP_OFFLOAD 1010 if (toe) { 1011 payload = sc->tt.rx_coalesce ? 1012 G_RXCOALESCESIZE(t4_read_reg(sc, A_TP_PARA_REG2)) : mtu; 1013 } else { 1014 #endif 1015 /* large enough even when hw VLAN extraction is disabled */ 1016 payload = sc->params.sge.fl_pktshift + ETHER_HDR_LEN + 1017 ETHER_VLAN_ENCAP_LEN + mtu; 1018 #ifdef TCP_OFFLOAD 1019 } 1020 #endif 1021 1022 return (payload); 1023 } 1024 1025 int 1026 t4_setup_vi_queues(struct vi_info *vi) 1027 { 1028 int rc = 0, i, j, intr_idx, iqid; 1029 struct sge_rxq *rxq; 1030 struct sge_txq *txq; 1031 struct sge_wrq *ctrlq; 1032 #ifdef TCP_OFFLOAD 1033 struct sge_ofld_rxq *ofld_rxq; 1034 struct sge_wrq *ofld_txq; 1035 #endif 1036 #ifdef DEV_NETMAP 1037 int saved_idx; 1038 struct sge_nm_rxq *nm_rxq; 1039 struct sge_nm_txq *nm_txq; 1040 #endif 1041 char name[16]; 1042 struct port_info *pi = vi->pi; 1043 struct adapter *sc = pi->adapter; 1044 struct ifnet *ifp = vi->ifp; 1045 struct sysctl_oid *oid = device_get_sysctl_tree(vi->dev); 1046 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 1047 int maxp, mtu = ifp->if_mtu; 1048 1049 /* Interrupt vector to start from (when using multiple vectors) */ 1050 intr_idx = first_vector(vi); 1051 1052 #ifdef DEV_NETMAP 1053 saved_idx = intr_idx; 1054 if (ifp->if_capabilities & IFCAP_NETMAP) { 1055 1056 /* netmap is supported with direct interrupts only. */ 1057 MPASS(vi->flags & INTR_RXQ); 1058 1059 /* 1060 * We don't have buffers to back the netmap rx queues 1061 * right now so we create the queues in a way that 1062 * doesn't set off any congestion signal in the chip. 1063 */ 1064 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "nm_rxq", 1065 CTLFLAG_RD, NULL, "rx queues"); 1066 for_each_nm_rxq(vi, i, nm_rxq) { 1067 rc = alloc_nm_rxq(vi, nm_rxq, intr_idx, i, oid); 1068 if (rc != 0) 1069 goto done; 1070 intr_idx++; 1071 } 1072 1073 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "nm_txq", 1074 CTLFLAG_RD, NULL, "tx queues"); 1075 for_each_nm_txq(vi, i, nm_txq) { 1076 iqid = vi->first_nm_rxq + (i % vi->nnmrxq); 1077 rc = alloc_nm_txq(vi, nm_txq, iqid, i, oid); 1078 if (rc != 0) 1079 goto done; 1080 } 1081 } 1082 1083 /* Normal rx queues and netmap rx queues share the same interrupts. */ 1084 intr_idx = saved_idx; 1085 #endif 1086 1087 /* 1088 * First pass over all NIC and TOE rx queues: 1089 * a) initialize iq and fl 1090 * b) allocate queue iff it will take direct interrupts. 1091 */ 1092 maxp = mtu_to_max_payload(sc, mtu, 0); 1093 if (vi->flags & INTR_RXQ) { 1094 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "rxq", 1095 CTLFLAG_RD, NULL, "rx queues"); 1096 } 1097 for_each_rxq(vi, i, rxq) { 1098 1099 init_iq(&rxq->iq, sc, vi->tmr_idx, vi->pktc_idx, vi->qsize_rxq); 1100 1101 snprintf(name, sizeof(name), "%s rxq%d-fl", 1102 device_get_nameunit(vi->dev), i); 1103 init_fl(sc, &rxq->fl, vi->qsize_rxq / 8, maxp, name); 1104 1105 if (vi->flags & INTR_RXQ) { 1106 rxq->iq.flags |= IQ_INTR; 1107 rc = alloc_rxq(vi, rxq, intr_idx, i, oid); 1108 if (rc != 0) 1109 goto done; 1110 intr_idx++; 1111 } 1112 } 1113 #ifdef DEV_NETMAP 1114 if (ifp->if_capabilities & IFCAP_NETMAP) 1115 intr_idx = saved_idx + max(vi->nrxq, vi->nnmrxq); 1116 #endif 1117 #ifdef TCP_OFFLOAD 1118 maxp = mtu_to_max_payload(sc, mtu, 1); 1119 if (vi->flags & INTR_OFLD_RXQ) { 1120 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_rxq", 1121 CTLFLAG_RD, NULL, 1122 "rx queues for offloaded TCP connections"); 1123 } 1124 for_each_ofld_rxq(vi, i, ofld_rxq) { 1125 1126 init_iq(&ofld_rxq->iq, sc, vi->tmr_idx, vi->pktc_idx, 1127 vi->qsize_rxq); 1128 1129 snprintf(name, sizeof(name), "%s ofld_rxq%d-fl", 1130 device_get_nameunit(vi->dev), i); 1131 init_fl(sc, &ofld_rxq->fl, vi->qsize_rxq / 8, maxp, name); 1132 1133 if (vi->flags & INTR_OFLD_RXQ) { 1134 ofld_rxq->iq.flags |= IQ_INTR; 1135 rc = alloc_ofld_rxq(vi, ofld_rxq, intr_idx, i, oid); 1136 if (rc != 0) 1137 goto done; 1138 intr_idx++; 1139 } 1140 } 1141 #endif 1142 1143 /* 1144 * Second pass over all NIC and TOE rx queues. The queues forwarding 1145 * their interrupts are allocated now. 1146 */ 1147 j = 0; 1148 if (!(vi->flags & INTR_RXQ)) { 1149 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "rxq", 1150 CTLFLAG_RD, NULL, "rx queues"); 1151 for_each_rxq(vi, i, rxq) { 1152 MPASS(!(rxq->iq.flags & IQ_INTR)); 1153 1154 intr_idx = vi_intr_iq(vi, j)->abs_id; 1155 1156 rc = alloc_rxq(vi, rxq, intr_idx, i, oid); 1157 if (rc != 0) 1158 goto done; 1159 j++; 1160 } 1161 } 1162 #ifdef TCP_OFFLOAD 1163 if (vi->nofldrxq != 0 && !(vi->flags & INTR_OFLD_RXQ)) { 1164 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_rxq", 1165 CTLFLAG_RD, NULL, 1166 "rx queues for offloaded TCP connections"); 1167 for_each_ofld_rxq(vi, i, ofld_rxq) { 1168 MPASS(!(ofld_rxq->iq.flags & IQ_INTR)); 1169 1170 intr_idx = vi_intr_iq(vi, j)->abs_id; 1171 1172 rc = alloc_ofld_rxq(vi, ofld_rxq, intr_idx, i, oid); 1173 if (rc != 0) 1174 goto done; 1175 j++; 1176 } 1177 } 1178 #endif 1179 1180 /* 1181 * Now the tx queues. Only one pass needed. 1182 */ 1183 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "txq", CTLFLAG_RD, 1184 NULL, "tx queues"); 1185 j = 0; 1186 for_each_txq(vi, i, txq) { 1187 iqid = vi_intr_iq(vi, j)->cntxt_id; 1188 snprintf(name, sizeof(name), "%s txq%d", 1189 device_get_nameunit(vi->dev), i); 1190 init_eq(sc, &txq->eq, EQ_ETH, vi->qsize_txq, pi->tx_chan, iqid, 1191 name); 1192 1193 rc = alloc_txq(vi, txq, i, oid); 1194 if (rc != 0) 1195 goto done; 1196 j++; 1197 } 1198 #ifdef TCP_OFFLOAD 1199 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_txq", 1200 CTLFLAG_RD, NULL, "tx queues for offloaded TCP connections"); 1201 for_each_ofld_txq(vi, i, ofld_txq) { 1202 struct sysctl_oid *oid2; 1203 1204 iqid = vi_intr_iq(vi, j)->cntxt_id; 1205 snprintf(name, sizeof(name), "%s ofld_txq%d", 1206 device_get_nameunit(vi->dev), i); 1207 init_eq(sc, &ofld_txq->eq, EQ_OFLD, vi->qsize_txq, pi->tx_chan, 1208 iqid, name); 1209 1210 snprintf(name, sizeof(name), "%d", i); 1211 oid2 = SYSCTL_ADD_NODE(&vi->ctx, SYSCTL_CHILDREN(oid), OID_AUTO, 1212 name, CTLFLAG_RD, NULL, "offload tx queue"); 1213 1214 rc = alloc_wrq(sc, vi, ofld_txq, oid2); 1215 if (rc != 0) 1216 goto done; 1217 j++; 1218 } 1219 #endif 1220 1221 /* 1222 * Finally, the control queue. 1223 */ 1224 if (!IS_MAIN_VI(vi) || sc->flags & IS_VF) 1225 goto done; 1226 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ctrlq", CTLFLAG_RD, 1227 NULL, "ctrl queue"); 1228 ctrlq = &sc->sge.ctrlq[pi->port_id]; 1229 iqid = vi_intr_iq(vi, 0)->cntxt_id; 1230 snprintf(name, sizeof(name), "%s ctrlq", device_get_nameunit(vi->dev)); 1231 init_eq(sc, &ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE, pi->tx_chan, iqid, 1232 name); 1233 rc = alloc_wrq(sc, vi, ctrlq, oid); 1234 1235 done: 1236 if (rc) 1237 t4_teardown_vi_queues(vi); 1238 1239 return (rc); 1240 } 1241 1242 /* 1243 * Idempotent 1244 */ 1245 int 1246 t4_teardown_vi_queues(struct vi_info *vi) 1247 { 1248 int i; 1249 struct port_info *pi = vi->pi; 1250 struct adapter *sc = pi->adapter; 1251 struct sge_rxq *rxq; 1252 struct sge_txq *txq; 1253 #ifdef TCP_OFFLOAD 1254 struct sge_ofld_rxq *ofld_rxq; 1255 struct sge_wrq *ofld_txq; 1256 #endif 1257 #ifdef DEV_NETMAP 1258 struct sge_nm_rxq *nm_rxq; 1259 struct sge_nm_txq *nm_txq; 1260 #endif 1261 1262 /* Do this before freeing the queues */ 1263 if (vi->flags & VI_SYSCTL_CTX) { 1264 sysctl_ctx_free(&vi->ctx); 1265 vi->flags &= ~VI_SYSCTL_CTX; 1266 } 1267 1268 #ifdef DEV_NETMAP 1269 if (vi->ifp->if_capabilities & IFCAP_NETMAP) { 1270 for_each_nm_txq(vi, i, nm_txq) { 1271 free_nm_txq(vi, nm_txq); 1272 } 1273 1274 for_each_nm_rxq(vi, i, nm_rxq) { 1275 free_nm_rxq(vi, nm_rxq); 1276 } 1277 } 1278 #endif 1279 1280 /* 1281 * Take down all the tx queues first, as they reference the rx queues 1282 * (for egress updates, etc.). 1283 */ 1284 1285 if (IS_MAIN_VI(vi) && !(sc->flags & IS_VF)) 1286 free_wrq(sc, &sc->sge.ctrlq[pi->port_id]); 1287 1288 for_each_txq(vi, i, txq) { 1289 free_txq(vi, txq); 1290 } 1291 #ifdef TCP_OFFLOAD 1292 for_each_ofld_txq(vi, i, ofld_txq) { 1293 free_wrq(sc, ofld_txq); 1294 } 1295 #endif 1296 1297 /* 1298 * Then take down the rx queues that forward their interrupts, as they 1299 * reference other rx queues. 1300 */ 1301 1302 for_each_rxq(vi, i, rxq) { 1303 if ((rxq->iq.flags & IQ_INTR) == 0) 1304 free_rxq(vi, rxq); 1305 } 1306 #ifdef TCP_OFFLOAD 1307 for_each_ofld_rxq(vi, i, ofld_rxq) { 1308 if ((ofld_rxq->iq.flags & IQ_INTR) == 0) 1309 free_ofld_rxq(vi, ofld_rxq); 1310 } 1311 #endif 1312 1313 /* 1314 * Then take down the rx queues that take direct interrupts. 1315 */ 1316 1317 for_each_rxq(vi, i, rxq) { 1318 if (rxq->iq.flags & IQ_INTR) 1319 free_rxq(vi, rxq); 1320 } 1321 #ifdef TCP_OFFLOAD 1322 for_each_ofld_rxq(vi, i, ofld_rxq) { 1323 if (ofld_rxq->iq.flags & IQ_INTR) 1324 free_ofld_rxq(vi, ofld_rxq); 1325 } 1326 #endif 1327 1328 return (0); 1329 } 1330 1331 /* 1332 * Deals with errors and the firmware event queue. All data rx queues forward 1333 * their interrupt to the firmware event queue. 1334 */ 1335 void 1336 t4_intr_all(void *arg) 1337 { 1338 struct adapter *sc = arg; 1339 struct sge_iq *fwq = &sc->sge.fwq; 1340 1341 t4_intr_err(arg); 1342 if (atomic_cmpset_int(&fwq->state, IQS_IDLE, IQS_BUSY)) { 1343 service_iq(fwq, 0); 1344 atomic_cmpset_int(&fwq->state, IQS_BUSY, IQS_IDLE); 1345 } 1346 } 1347 1348 /* Deals with error interrupts */ 1349 void 1350 t4_intr_err(void *arg) 1351 { 1352 struct adapter *sc = arg; 1353 1354 t4_write_reg(sc, MYPF_REG(A_PCIE_PF_CLI), 0); 1355 t4_slow_intr_handler(sc); 1356 } 1357 1358 void 1359 t4_intr_evt(void *arg) 1360 { 1361 struct sge_iq *iq = arg; 1362 1363 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 1364 service_iq(iq, 0); 1365 atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 1366 } 1367 } 1368 1369 void 1370 t4_intr(void *arg) 1371 { 1372 struct sge_iq *iq = arg; 1373 1374 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 1375 service_iq(iq, 0); 1376 atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 1377 } 1378 } 1379 1380 void 1381 t4_vi_intr(void *arg) 1382 { 1383 struct irq *irq = arg; 1384 1385 #ifdef DEV_NETMAP 1386 if (atomic_cmpset_int(&irq->nm_state, NM_ON, NM_BUSY)) { 1387 t4_nm_intr(irq->nm_rxq); 1388 atomic_cmpset_int(&irq->nm_state, NM_BUSY, NM_ON); 1389 } 1390 #endif 1391 if (irq->rxq != NULL) 1392 t4_intr(irq->rxq); 1393 } 1394 1395 static inline int 1396 sort_before_lro(struct lro_ctrl *lro) 1397 { 1398 1399 return (lro->lro_mbuf_max != 0); 1400 } 1401 1402 /* 1403 * Deals with anything and everything on the given ingress queue. 1404 */ 1405 static int 1406 service_iq(struct sge_iq *iq, int budget) 1407 { 1408 struct sge_iq *q; 1409 struct sge_rxq *rxq = iq_to_rxq(iq); /* Use iff iq is part of rxq */ 1410 struct sge_fl *fl; /* Use iff IQ_HAS_FL */ 1411 struct adapter *sc = iq->adapter; 1412 struct iq_desc *d = &iq->desc[iq->cidx]; 1413 int ndescs = 0, limit; 1414 int rsp_type, refill; 1415 uint32_t lq; 1416 uint16_t fl_hw_cidx; 1417 struct mbuf *m0; 1418 STAILQ_HEAD(, sge_iq) iql = STAILQ_HEAD_INITIALIZER(iql); 1419 #if defined(INET) || defined(INET6) 1420 const struct timeval lro_timeout = {0, sc->lro_timeout}; 1421 struct lro_ctrl *lro = &rxq->lro; 1422 #endif 1423 1424 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq)); 1425 1426 limit = budget ? budget : iq->qsize / 16; 1427 1428 if (iq->flags & IQ_HAS_FL) { 1429 fl = &rxq->fl; 1430 fl_hw_cidx = fl->hw_cidx; /* stable snapshot */ 1431 } else { 1432 fl = NULL; 1433 fl_hw_cidx = 0; /* to silence gcc warning */ 1434 } 1435 1436 #if defined(INET) || defined(INET6) 1437 if (iq->flags & IQ_ADJ_CREDIT) { 1438 MPASS(sort_before_lro(lro)); 1439 iq->flags &= ~IQ_ADJ_CREDIT; 1440 if ((d->rsp.u.type_gen & F_RSPD_GEN) != iq->gen) { 1441 tcp_lro_flush_all(lro); 1442 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(1) | 1443 V_INGRESSQID((u32)iq->cntxt_id) | 1444 V_SEINTARM(iq->intr_params)); 1445 return (0); 1446 } 1447 ndescs = 1; 1448 } 1449 #else 1450 MPASS((iq->flags & IQ_ADJ_CREDIT) == 0); 1451 #endif 1452 1453 /* 1454 * We always come back and check the descriptor ring for new indirect 1455 * interrupts and other responses after running a single handler. 1456 */ 1457 for (;;) { 1458 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) { 1459 1460 rmb(); 1461 1462 refill = 0; 1463 m0 = NULL; 1464 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen); 1465 lq = be32toh(d->rsp.pldbuflen_qid); 1466 1467 switch (rsp_type) { 1468 case X_RSPD_TYPE_FLBUF: 1469 1470 KASSERT(iq->flags & IQ_HAS_FL, 1471 ("%s: data for an iq (%p) with no freelist", 1472 __func__, iq)); 1473 1474 m0 = get_fl_payload(sc, fl, lq); 1475 if (__predict_false(m0 == NULL)) 1476 goto process_iql; 1477 refill = IDXDIFF(fl->hw_cidx, fl_hw_cidx, fl->sidx) > 2; 1478 #ifdef T4_PKT_TIMESTAMP 1479 /* 1480 * 60 bit timestamp for the payload is 1481 * *(uint64_t *)m0->m_pktdat. Note that it is 1482 * in the leading free-space in the mbuf. The 1483 * kernel can clobber it during a pullup, 1484 * m_copymdata, etc. You need to make sure that 1485 * the mbuf reaches you unmolested if you care 1486 * about the timestamp. 1487 */ 1488 *(uint64_t *)m0->m_pktdat = 1489 be64toh(ctrl->u.last_flit) & 1490 0xfffffffffffffff; 1491 #endif 1492 1493 /* fall through */ 1494 1495 case X_RSPD_TYPE_CPL: 1496 KASSERT(d->rss.opcode < NUM_CPL_CMDS, 1497 ("%s: bad opcode %02x.", __func__, 1498 d->rss.opcode)); 1499 t4_cpl_handler[d->rss.opcode](iq, &d->rss, m0); 1500 break; 1501 1502 case X_RSPD_TYPE_INTR: 1503 1504 /* 1505 * Interrupts should be forwarded only to queues 1506 * that are not forwarding their interrupts. 1507 * This means service_iq can recurse but only 1 1508 * level deep. 1509 */ 1510 KASSERT(budget == 0, 1511 ("%s: budget %u, rsp_type %u", __func__, 1512 budget, rsp_type)); 1513 1514 /* 1515 * There are 1K interrupt-capable queues (qids 0 1516 * through 1023). A response type indicating a 1517 * forwarded interrupt with a qid >= 1K is an 1518 * iWARP async notification. 1519 */ 1520 if (lq >= 1024) { 1521 t4_an_handler(iq, &d->rsp); 1522 break; 1523 } 1524 1525 q = sc->sge.iqmap[lq - sc->sge.iq_start - 1526 sc->sge.iq_base]; 1527 if (atomic_cmpset_int(&q->state, IQS_IDLE, 1528 IQS_BUSY)) { 1529 if (service_iq(q, q->qsize / 16) == 0) { 1530 atomic_cmpset_int(&q->state, 1531 IQS_BUSY, IQS_IDLE); 1532 } else { 1533 STAILQ_INSERT_TAIL(&iql, q, 1534 link); 1535 } 1536 } 1537 break; 1538 1539 default: 1540 KASSERT(0, 1541 ("%s: illegal response type %d on iq %p", 1542 __func__, rsp_type, iq)); 1543 log(LOG_ERR, 1544 "%s: illegal response type %d on iq %p", 1545 device_get_nameunit(sc->dev), rsp_type, iq); 1546 break; 1547 } 1548 1549 d++; 1550 if (__predict_false(++iq->cidx == iq->sidx)) { 1551 iq->cidx = 0; 1552 iq->gen ^= F_RSPD_GEN; 1553 d = &iq->desc[0]; 1554 } 1555 if (__predict_false(++ndescs == limit)) { 1556 t4_write_reg(sc, sc->sge_gts_reg, 1557 V_CIDXINC(ndescs) | 1558 V_INGRESSQID(iq->cntxt_id) | 1559 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); 1560 ndescs = 0; 1561 1562 #if defined(INET) || defined(INET6) 1563 if (iq->flags & IQ_LRO_ENABLED && 1564 !sort_before_lro(lro) && 1565 sc->lro_timeout != 0) { 1566 tcp_lro_flush_inactive(lro, 1567 &lro_timeout); 1568 } 1569 #endif 1570 1571 if (budget) { 1572 if (iq->flags & IQ_HAS_FL) { 1573 FL_LOCK(fl); 1574 refill_fl(sc, fl, 32); 1575 FL_UNLOCK(fl); 1576 } 1577 return (EINPROGRESS); 1578 } 1579 } 1580 if (refill) { 1581 FL_LOCK(fl); 1582 refill_fl(sc, fl, 32); 1583 FL_UNLOCK(fl); 1584 fl_hw_cidx = fl->hw_cidx; 1585 } 1586 } 1587 1588 process_iql: 1589 if (STAILQ_EMPTY(&iql)) 1590 break; 1591 1592 /* 1593 * Process the head only, and send it to the back of the list if 1594 * it's still not done. 1595 */ 1596 q = STAILQ_FIRST(&iql); 1597 STAILQ_REMOVE_HEAD(&iql, link); 1598 if (service_iq(q, q->qsize / 8) == 0) 1599 atomic_cmpset_int(&q->state, IQS_BUSY, IQS_IDLE); 1600 else 1601 STAILQ_INSERT_TAIL(&iql, q, link); 1602 } 1603 1604 #if defined(INET) || defined(INET6) 1605 if (iq->flags & IQ_LRO_ENABLED) { 1606 if (ndescs > 0 && lro->lro_mbuf_count > 8) { 1607 MPASS(sort_before_lro(lro)); 1608 /* hold back one credit and don't flush LRO state */ 1609 iq->flags |= IQ_ADJ_CREDIT; 1610 ndescs--; 1611 } else { 1612 tcp_lro_flush_all(lro); 1613 } 1614 } 1615 #endif 1616 1617 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) | 1618 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params)); 1619 1620 if (iq->flags & IQ_HAS_FL) { 1621 int starved; 1622 1623 FL_LOCK(fl); 1624 starved = refill_fl(sc, fl, 64); 1625 FL_UNLOCK(fl); 1626 if (__predict_false(starved != 0)) 1627 add_fl_to_sfl(sc, fl); 1628 } 1629 1630 return (0); 1631 } 1632 1633 static inline int 1634 cl_has_metadata(struct sge_fl *fl, struct cluster_layout *cll) 1635 { 1636 int rc = fl->flags & FL_BUF_PACKING || cll->region1 > 0; 1637 1638 if (rc) 1639 MPASS(cll->region3 >= CL_METADATA_SIZE); 1640 1641 return (rc); 1642 } 1643 1644 static inline struct cluster_metadata * 1645 cl_metadata(struct adapter *sc, struct sge_fl *fl, struct cluster_layout *cll, 1646 caddr_t cl) 1647 { 1648 1649 if (cl_has_metadata(fl, cll)) { 1650 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx]; 1651 1652 return ((struct cluster_metadata *)(cl + swz->size) - 1); 1653 } 1654 return (NULL); 1655 } 1656 1657 static void 1658 rxb_free(struct mbuf *m, void *arg1, void *arg2) 1659 { 1660 uma_zone_t zone = arg1; 1661 caddr_t cl = arg2; 1662 1663 uma_zfree(zone, cl); 1664 counter_u64_add(extfree_rels, 1); 1665 } 1666 1667 /* 1668 * The mbuf returned by this function could be allocated from zone_mbuf or 1669 * constructed in spare room in the cluster. 1670 * 1671 * The mbuf carries the payload in one of these ways 1672 * a) frame inside the mbuf (mbuf from zone_mbuf) 1673 * b) m_cljset (for clusters without metadata) zone_mbuf 1674 * c) m_extaddref (cluster with metadata) inline mbuf 1675 * d) m_extaddref (cluster with metadata) zone_mbuf 1676 */ 1677 static struct mbuf * 1678 get_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset, 1679 int remaining) 1680 { 1681 struct mbuf *m; 1682 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 1683 struct cluster_layout *cll = &sd->cll; 1684 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx]; 1685 struct hw_buf_info *hwb = &sc->sge.hw_buf_info[cll->hwidx]; 1686 struct cluster_metadata *clm = cl_metadata(sc, fl, cll, sd->cl); 1687 int len, blen; 1688 caddr_t payload; 1689 1690 blen = hwb->size - fl->rx_offset; /* max possible in this buf */ 1691 len = min(remaining, blen); 1692 payload = sd->cl + cll->region1 + fl->rx_offset; 1693 if (fl->flags & FL_BUF_PACKING) { 1694 const u_int l = fr_offset + len; 1695 const u_int pad = roundup2(l, fl->buf_boundary) - l; 1696 1697 if (fl->rx_offset + len + pad < hwb->size) 1698 blen = len + pad; 1699 MPASS(fl->rx_offset + blen <= hwb->size); 1700 } else { 1701 MPASS(fl->rx_offset == 0); /* not packing */ 1702 } 1703 1704 1705 if (sc->sc_do_rxcopy && len < RX_COPY_THRESHOLD) { 1706 1707 /* 1708 * Copy payload into a freshly allocated mbuf. 1709 */ 1710 1711 m = fr_offset == 0 ? 1712 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA); 1713 if (m == NULL) 1714 return (NULL); 1715 fl->mbuf_allocated++; 1716 #ifdef T4_PKT_TIMESTAMP 1717 /* Leave room for a timestamp */ 1718 m->m_data += 8; 1719 #endif 1720 /* copy data to mbuf */ 1721 bcopy(payload, mtod(m, caddr_t), len); 1722 1723 } else if (sd->nmbuf * MSIZE < cll->region1) { 1724 1725 /* 1726 * There's spare room in the cluster for an mbuf. Create one 1727 * and associate it with the payload that's in the cluster. 1728 */ 1729 1730 MPASS(clm != NULL); 1731 m = (struct mbuf *)(sd->cl + sd->nmbuf * MSIZE); 1732 /* No bzero required */ 1733 if (m_init(m, M_NOWAIT, MT_DATA, 1734 fr_offset == 0 ? M_PKTHDR | M_NOFREE : M_NOFREE)) 1735 return (NULL); 1736 fl->mbuf_inlined++; 1737 m_extaddref(m, payload, blen, &clm->refcount, rxb_free, 1738 swz->zone, sd->cl); 1739 if (sd->nmbuf++ == 0) 1740 counter_u64_add(extfree_refs, 1); 1741 1742 } else { 1743 1744 /* 1745 * Grab an mbuf from zone_mbuf and associate it with the 1746 * payload in the cluster. 1747 */ 1748 1749 m = fr_offset == 0 ? 1750 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA); 1751 if (m == NULL) 1752 return (NULL); 1753 fl->mbuf_allocated++; 1754 if (clm != NULL) { 1755 m_extaddref(m, payload, blen, &clm->refcount, 1756 rxb_free, swz->zone, sd->cl); 1757 if (sd->nmbuf++ == 0) 1758 counter_u64_add(extfree_refs, 1); 1759 } else { 1760 m_cljset(m, sd->cl, swz->type); 1761 sd->cl = NULL; /* consumed, not a recycle candidate */ 1762 } 1763 } 1764 if (fr_offset == 0) 1765 m->m_pkthdr.len = remaining; 1766 m->m_len = len; 1767 1768 if (fl->flags & FL_BUF_PACKING) { 1769 fl->rx_offset += blen; 1770 MPASS(fl->rx_offset <= hwb->size); 1771 if (fl->rx_offset < hwb->size) 1772 return (m); /* without advancing the cidx */ 1773 } 1774 1775 if (__predict_false(++fl->cidx % 8 == 0)) { 1776 uint16_t cidx = fl->cidx / 8; 1777 1778 if (__predict_false(cidx == fl->sidx)) 1779 fl->cidx = cidx = 0; 1780 fl->hw_cidx = cidx; 1781 } 1782 fl->rx_offset = 0; 1783 1784 return (m); 1785 } 1786 1787 static struct mbuf * 1788 get_fl_payload(struct adapter *sc, struct sge_fl *fl, uint32_t len_newbuf) 1789 { 1790 struct mbuf *m0, *m, **pnext; 1791 u_int remaining; 1792 const u_int total = G_RSPD_LEN(len_newbuf); 1793 1794 if (__predict_false(fl->flags & FL_BUF_RESUME)) { 1795 M_ASSERTPKTHDR(fl->m0); 1796 MPASS(fl->m0->m_pkthdr.len == total); 1797 MPASS(fl->remaining < total); 1798 1799 m0 = fl->m0; 1800 pnext = fl->pnext; 1801 remaining = fl->remaining; 1802 fl->flags &= ~FL_BUF_RESUME; 1803 goto get_segment; 1804 } 1805 1806 if (fl->rx_offset > 0 && len_newbuf & F_RSPD_NEWBUF) { 1807 fl->rx_offset = 0; 1808 if (__predict_false(++fl->cidx % 8 == 0)) { 1809 uint16_t cidx = fl->cidx / 8; 1810 1811 if (__predict_false(cidx == fl->sidx)) 1812 fl->cidx = cidx = 0; 1813 fl->hw_cidx = cidx; 1814 } 1815 } 1816 1817 /* 1818 * Payload starts at rx_offset in the current hw buffer. Its length is 1819 * 'len' and it may span multiple hw buffers. 1820 */ 1821 1822 m0 = get_scatter_segment(sc, fl, 0, total); 1823 if (m0 == NULL) 1824 return (NULL); 1825 remaining = total - m0->m_len; 1826 pnext = &m0->m_next; 1827 while (remaining > 0) { 1828 get_segment: 1829 MPASS(fl->rx_offset == 0); 1830 m = get_scatter_segment(sc, fl, total - remaining, remaining); 1831 if (__predict_false(m == NULL)) { 1832 fl->m0 = m0; 1833 fl->pnext = pnext; 1834 fl->remaining = remaining; 1835 fl->flags |= FL_BUF_RESUME; 1836 return (NULL); 1837 } 1838 *pnext = m; 1839 pnext = &m->m_next; 1840 remaining -= m->m_len; 1841 } 1842 *pnext = NULL; 1843 1844 M_ASSERTPKTHDR(m0); 1845 return (m0); 1846 } 1847 1848 static int 1849 t4_eth_rx(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0) 1850 { 1851 struct sge_rxq *rxq = iq_to_rxq(iq); 1852 struct ifnet *ifp = rxq->ifp; 1853 struct adapter *sc = iq->adapter; 1854 const struct cpl_rx_pkt *cpl = (const void *)(rss + 1); 1855 #if defined(INET) || defined(INET6) 1856 struct lro_ctrl *lro = &rxq->lro; 1857 #endif 1858 static const int sw_hashtype[4][2] = { 1859 {M_HASHTYPE_NONE, M_HASHTYPE_NONE}, 1860 {M_HASHTYPE_RSS_IPV4, M_HASHTYPE_RSS_IPV6}, 1861 {M_HASHTYPE_RSS_TCP_IPV4, M_HASHTYPE_RSS_TCP_IPV6}, 1862 {M_HASHTYPE_RSS_UDP_IPV4, M_HASHTYPE_RSS_UDP_IPV6}, 1863 }; 1864 1865 KASSERT(m0 != NULL, ("%s: no payload with opcode %02x", __func__, 1866 rss->opcode)); 1867 1868 m0->m_pkthdr.len -= sc->params.sge.fl_pktshift; 1869 m0->m_len -= sc->params.sge.fl_pktshift; 1870 m0->m_data += sc->params.sge.fl_pktshift; 1871 1872 m0->m_pkthdr.rcvif = ifp; 1873 M_HASHTYPE_SET(m0, sw_hashtype[rss->hash_type][rss->ipv6]); 1874 m0->m_pkthdr.flowid = be32toh(rss->hash_val); 1875 1876 if (cpl->csum_calc && !(cpl->err_vec & sc->params.tp.err_vec_mask)) { 1877 if (ifp->if_capenable & IFCAP_RXCSUM && 1878 cpl->l2info & htobe32(F_RXF_IP)) { 1879 m0->m_pkthdr.csum_flags = (CSUM_IP_CHECKED | 1880 CSUM_IP_VALID | CSUM_DATA_VALID | CSUM_PSEUDO_HDR); 1881 rxq->rxcsum++; 1882 } else if (ifp->if_capenable & IFCAP_RXCSUM_IPV6 && 1883 cpl->l2info & htobe32(F_RXF_IP6)) { 1884 m0->m_pkthdr.csum_flags = (CSUM_DATA_VALID_IPV6 | 1885 CSUM_PSEUDO_HDR); 1886 rxq->rxcsum++; 1887 } 1888 1889 if (__predict_false(cpl->ip_frag)) 1890 m0->m_pkthdr.csum_data = be16toh(cpl->csum); 1891 else 1892 m0->m_pkthdr.csum_data = 0xffff; 1893 } 1894 1895 if (cpl->vlan_ex) { 1896 m0->m_pkthdr.ether_vtag = be16toh(cpl->vlan); 1897 m0->m_flags |= M_VLANTAG; 1898 rxq->vlan_extraction++; 1899 } 1900 1901 #if defined(INET) || defined(INET6) 1902 if (iq->flags & IQ_LRO_ENABLED) { 1903 if (sort_before_lro(lro)) { 1904 tcp_lro_queue_mbuf(lro, m0); 1905 return (0); /* queued for sort, then LRO */ 1906 } 1907 if (tcp_lro_rx(lro, m0, 0) == 0) 1908 return (0); /* queued for LRO */ 1909 } 1910 #endif 1911 ifp->if_input(ifp, m0); 1912 1913 return (0); 1914 } 1915 1916 /* 1917 * Must drain the wrq or make sure that someone else will. 1918 */ 1919 static void 1920 wrq_tx_drain(void *arg, int n) 1921 { 1922 struct sge_wrq *wrq = arg; 1923 struct sge_eq *eq = &wrq->eq; 1924 1925 EQ_LOCK(eq); 1926 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 1927 drain_wrq_wr_list(wrq->adapter, wrq); 1928 EQ_UNLOCK(eq); 1929 } 1930 1931 static void 1932 drain_wrq_wr_list(struct adapter *sc, struct sge_wrq *wrq) 1933 { 1934 struct sge_eq *eq = &wrq->eq; 1935 u_int available, dbdiff; /* # of hardware descriptors */ 1936 u_int n; 1937 struct wrqe *wr; 1938 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */ 1939 1940 EQ_LOCK_ASSERT_OWNED(eq); 1941 MPASS(TAILQ_EMPTY(&wrq->incomplete_wrs)); 1942 wr = STAILQ_FIRST(&wrq->wr_list); 1943 MPASS(wr != NULL); /* Must be called with something useful to do */ 1944 MPASS(eq->pidx == eq->dbidx); 1945 dbdiff = 0; 1946 1947 do { 1948 eq->cidx = read_hw_cidx(eq); 1949 if (eq->pidx == eq->cidx) 1950 available = eq->sidx - 1; 1951 else 1952 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 1953 1954 MPASS(wr->wrq == wrq); 1955 n = howmany(wr->wr_len, EQ_ESIZE); 1956 if (available < n) 1957 break; 1958 1959 dst = (void *)&eq->desc[eq->pidx]; 1960 if (__predict_true(eq->sidx - eq->pidx > n)) { 1961 /* Won't wrap, won't end exactly at the status page. */ 1962 bcopy(&wr->wr[0], dst, wr->wr_len); 1963 eq->pidx += n; 1964 } else { 1965 int first_portion = (eq->sidx - eq->pidx) * EQ_ESIZE; 1966 1967 bcopy(&wr->wr[0], dst, first_portion); 1968 if (wr->wr_len > first_portion) { 1969 bcopy(&wr->wr[first_portion], &eq->desc[0], 1970 wr->wr_len - first_portion); 1971 } 1972 eq->pidx = n - (eq->sidx - eq->pidx); 1973 } 1974 wrq->tx_wrs_copied++; 1975 1976 if (available < eq->sidx / 4 && 1977 atomic_cmpset_int(&eq->equiq, 0, 1)) { 1978 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ | 1979 F_FW_WR_EQUEQ); 1980 eq->equeqidx = eq->pidx; 1981 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 32) { 1982 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ); 1983 eq->equeqidx = eq->pidx; 1984 } 1985 1986 dbdiff += n; 1987 if (dbdiff >= 16) { 1988 ring_eq_db(sc, eq, dbdiff); 1989 dbdiff = 0; 1990 } 1991 1992 STAILQ_REMOVE_HEAD(&wrq->wr_list, link); 1993 free_wrqe(wr); 1994 MPASS(wrq->nwr_pending > 0); 1995 wrq->nwr_pending--; 1996 MPASS(wrq->ndesc_needed >= n); 1997 wrq->ndesc_needed -= n; 1998 } while ((wr = STAILQ_FIRST(&wrq->wr_list)) != NULL); 1999 2000 if (dbdiff) 2001 ring_eq_db(sc, eq, dbdiff); 2002 } 2003 2004 /* 2005 * Doesn't fail. Holds on to work requests it can't send right away. 2006 */ 2007 void 2008 t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, struct wrqe *wr) 2009 { 2010 #ifdef INVARIANTS 2011 struct sge_eq *eq = &wrq->eq; 2012 #endif 2013 2014 EQ_LOCK_ASSERT_OWNED(eq); 2015 MPASS(wr != NULL); 2016 MPASS(wr->wr_len > 0 && wr->wr_len <= SGE_MAX_WR_LEN); 2017 MPASS((wr->wr_len & 0x7) == 0); 2018 2019 STAILQ_INSERT_TAIL(&wrq->wr_list, wr, link); 2020 wrq->nwr_pending++; 2021 wrq->ndesc_needed += howmany(wr->wr_len, EQ_ESIZE); 2022 2023 if (!TAILQ_EMPTY(&wrq->incomplete_wrs)) 2024 return; /* commit_wrq_wr will drain wr_list as well. */ 2025 2026 drain_wrq_wr_list(sc, wrq); 2027 2028 /* Doorbell must have caught up to the pidx. */ 2029 MPASS(eq->pidx == eq->dbidx); 2030 } 2031 2032 void 2033 t4_update_fl_bufsize(struct ifnet *ifp) 2034 { 2035 struct vi_info *vi = ifp->if_softc; 2036 struct adapter *sc = vi->pi->adapter; 2037 struct sge_rxq *rxq; 2038 #ifdef TCP_OFFLOAD 2039 struct sge_ofld_rxq *ofld_rxq; 2040 #endif 2041 struct sge_fl *fl; 2042 int i, maxp, mtu = ifp->if_mtu; 2043 2044 maxp = mtu_to_max_payload(sc, mtu, 0); 2045 for_each_rxq(vi, i, rxq) { 2046 fl = &rxq->fl; 2047 2048 FL_LOCK(fl); 2049 find_best_refill_source(sc, fl, maxp); 2050 FL_UNLOCK(fl); 2051 } 2052 #ifdef TCP_OFFLOAD 2053 maxp = mtu_to_max_payload(sc, mtu, 1); 2054 for_each_ofld_rxq(vi, i, ofld_rxq) { 2055 fl = &ofld_rxq->fl; 2056 2057 FL_LOCK(fl); 2058 find_best_refill_source(sc, fl, maxp); 2059 FL_UNLOCK(fl); 2060 } 2061 #endif 2062 } 2063 2064 static inline int 2065 mbuf_nsegs(struct mbuf *m) 2066 { 2067 2068 M_ASSERTPKTHDR(m); 2069 KASSERT(m->m_pkthdr.l5hlen > 0, 2070 ("%s: mbuf %p missing information on # of segments.", __func__, m)); 2071 2072 return (m->m_pkthdr.l5hlen); 2073 } 2074 2075 static inline void 2076 set_mbuf_nsegs(struct mbuf *m, uint8_t nsegs) 2077 { 2078 2079 M_ASSERTPKTHDR(m); 2080 m->m_pkthdr.l5hlen = nsegs; 2081 } 2082 2083 static inline int 2084 mbuf_len16(struct mbuf *m) 2085 { 2086 int n; 2087 2088 M_ASSERTPKTHDR(m); 2089 n = m->m_pkthdr.PH_loc.eight[0]; 2090 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16); 2091 2092 return (n); 2093 } 2094 2095 static inline void 2096 set_mbuf_len16(struct mbuf *m, uint8_t len16) 2097 { 2098 2099 M_ASSERTPKTHDR(m); 2100 m->m_pkthdr.PH_loc.eight[0] = len16; 2101 } 2102 2103 static inline int 2104 needs_tso(struct mbuf *m) 2105 { 2106 2107 M_ASSERTPKTHDR(m); 2108 2109 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 2110 KASSERT(m->m_pkthdr.tso_segsz > 0, 2111 ("%s: TSO requested in mbuf %p but MSS not provided", 2112 __func__, m)); 2113 return (1); 2114 } 2115 2116 return (0); 2117 } 2118 2119 static inline int 2120 needs_l3_csum(struct mbuf *m) 2121 { 2122 2123 M_ASSERTPKTHDR(m); 2124 2125 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TSO)) 2126 return (1); 2127 return (0); 2128 } 2129 2130 static inline int 2131 needs_l4_csum(struct mbuf *m) 2132 { 2133 2134 M_ASSERTPKTHDR(m); 2135 2136 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_UDP_IPV6 | 2137 CSUM_TCP_IPV6 | CSUM_TSO)) 2138 return (1); 2139 return (0); 2140 } 2141 2142 static inline int 2143 needs_vlan_insertion(struct mbuf *m) 2144 { 2145 2146 M_ASSERTPKTHDR(m); 2147 2148 if (m->m_flags & M_VLANTAG) { 2149 KASSERT(m->m_pkthdr.ether_vtag != 0, 2150 ("%s: HWVLAN requested in mbuf %p but tag not provided", 2151 __func__, m)); 2152 return (1); 2153 } 2154 return (0); 2155 } 2156 2157 static void * 2158 m_advance(struct mbuf **pm, int *poffset, int len) 2159 { 2160 struct mbuf *m = *pm; 2161 int offset = *poffset; 2162 uintptr_t p = 0; 2163 2164 MPASS(len > 0); 2165 2166 for (;;) { 2167 if (offset + len < m->m_len) { 2168 offset += len; 2169 p = mtod(m, uintptr_t) + offset; 2170 break; 2171 } 2172 len -= m->m_len - offset; 2173 m = m->m_next; 2174 offset = 0; 2175 MPASS(m != NULL); 2176 } 2177 *poffset = offset; 2178 *pm = m; 2179 return ((void *)p); 2180 } 2181 2182 /* 2183 * Can deal with empty mbufs in the chain that have m_len = 0, but the chain 2184 * must have at least one mbuf that's not empty. 2185 */ 2186 static inline int 2187 count_mbuf_nsegs(struct mbuf *m) 2188 { 2189 vm_paddr_t lastb, next; 2190 vm_offset_t va; 2191 int len, nsegs; 2192 2193 MPASS(m != NULL); 2194 2195 nsegs = 0; 2196 lastb = 0; 2197 for (; m; m = m->m_next) { 2198 2199 len = m->m_len; 2200 if (__predict_false(len == 0)) 2201 continue; 2202 va = mtod(m, vm_offset_t); 2203 next = pmap_kextract(va); 2204 nsegs += sglist_count(m->m_data, len); 2205 if (lastb + 1 == next) 2206 nsegs--; 2207 lastb = pmap_kextract(va + len - 1); 2208 } 2209 2210 MPASS(nsegs > 0); 2211 return (nsegs); 2212 } 2213 2214 /* 2215 * Analyze the mbuf to determine its tx needs. The mbuf passed in may change: 2216 * a) caller can assume it's been freed if this function returns with an error. 2217 * b) it may get defragged up if the gather list is too long for the hardware. 2218 */ 2219 int 2220 parse_pkt(struct adapter *sc, struct mbuf **mp) 2221 { 2222 struct mbuf *m0 = *mp, *m; 2223 int rc, nsegs, defragged = 0, offset; 2224 struct ether_header *eh; 2225 void *l3hdr; 2226 #if defined(INET) || defined(INET6) 2227 struct tcphdr *tcp; 2228 #endif 2229 uint16_t eh_type; 2230 2231 M_ASSERTPKTHDR(m0); 2232 if (__predict_false(m0->m_pkthdr.len < ETHER_HDR_LEN)) { 2233 rc = EINVAL; 2234 fail: 2235 m_freem(m0); 2236 *mp = NULL; 2237 return (rc); 2238 } 2239 restart: 2240 /* 2241 * First count the number of gather list segments in the payload. 2242 * Defrag the mbuf if nsegs exceeds the hardware limit. 2243 */ 2244 M_ASSERTPKTHDR(m0); 2245 MPASS(m0->m_pkthdr.len > 0); 2246 nsegs = count_mbuf_nsegs(m0); 2247 if (nsegs > (needs_tso(m0) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS)) { 2248 if (defragged++ > 0 || (m = m_defrag(m0, M_NOWAIT)) == NULL) { 2249 rc = EFBIG; 2250 goto fail; 2251 } 2252 *mp = m0 = m; /* update caller's copy after defrag */ 2253 goto restart; 2254 } 2255 2256 if (__predict_false(nsegs > 2 && m0->m_pkthdr.len <= MHLEN)) { 2257 m0 = m_pullup(m0, m0->m_pkthdr.len); 2258 if (m0 == NULL) { 2259 /* Should have left well enough alone. */ 2260 rc = EFBIG; 2261 goto fail; 2262 } 2263 *mp = m0; /* update caller's copy after pullup */ 2264 goto restart; 2265 } 2266 set_mbuf_nsegs(m0, nsegs); 2267 if (sc->flags & IS_VF) 2268 set_mbuf_len16(m0, txpkt_vm_len16(nsegs, needs_tso(m0))); 2269 else 2270 set_mbuf_len16(m0, txpkt_len16(nsegs, needs_tso(m0))); 2271 2272 if (!needs_tso(m0) && 2273 !(sc->flags & IS_VF && (needs_l3_csum(m0) || needs_l4_csum(m0)))) 2274 return (0); 2275 2276 m = m0; 2277 eh = mtod(m, struct ether_header *); 2278 eh_type = ntohs(eh->ether_type); 2279 if (eh_type == ETHERTYPE_VLAN) { 2280 struct ether_vlan_header *evh = (void *)eh; 2281 2282 eh_type = ntohs(evh->evl_proto); 2283 m0->m_pkthdr.l2hlen = sizeof(*evh); 2284 } else 2285 m0->m_pkthdr.l2hlen = sizeof(*eh); 2286 2287 offset = 0; 2288 l3hdr = m_advance(&m, &offset, m0->m_pkthdr.l2hlen); 2289 2290 switch (eh_type) { 2291 #ifdef INET6 2292 case ETHERTYPE_IPV6: 2293 { 2294 struct ip6_hdr *ip6 = l3hdr; 2295 2296 MPASS(!needs_tso(m0) || ip6->ip6_nxt == IPPROTO_TCP); 2297 2298 m0->m_pkthdr.l3hlen = sizeof(*ip6); 2299 break; 2300 } 2301 #endif 2302 #ifdef INET 2303 case ETHERTYPE_IP: 2304 { 2305 struct ip *ip = l3hdr; 2306 2307 m0->m_pkthdr.l3hlen = ip->ip_hl * 4; 2308 break; 2309 } 2310 #endif 2311 default: 2312 panic("%s: ethertype 0x%04x unknown. if_cxgbe must be compiled" 2313 " with the same INET/INET6 options as the kernel.", 2314 __func__, eh_type); 2315 } 2316 2317 #if defined(INET) || defined(INET6) 2318 if (needs_tso(m0)) { 2319 tcp = m_advance(&m, &offset, m0->m_pkthdr.l3hlen); 2320 m0->m_pkthdr.l4hlen = tcp->th_off * 4; 2321 } 2322 #endif 2323 MPASS(m0 == *mp); 2324 return (0); 2325 } 2326 2327 void * 2328 start_wrq_wr(struct sge_wrq *wrq, int len16, struct wrq_cookie *cookie) 2329 { 2330 struct sge_eq *eq = &wrq->eq; 2331 struct adapter *sc = wrq->adapter; 2332 int ndesc, available; 2333 struct wrqe *wr; 2334 void *w; 2335 2336 MPASS(len16 > 0); 2337 ndesc = howmany(len16, EQ_ESIZE / 16); 2338 MPASS(ndesc > 0 && ndesc <= SGE_MAX_WR_NDESC); 2339 2340 EQ_LOCK(eq); 2341 2342 if (!STAILQ_EMPTY(&wrq->wr_list)) 2343 drain_wrq_wr_list(sc, wrq); 2344 2345 if (!STAILQ_EMPTY(&wrq->wr_list)) { 2346 slowpath: 2347 EQ_UNLOCK(eq); 2348 wr = alloc_wrqe(len16 * 16, wrq); 2349 if (__predict_false(wr == NULL)) 2350 return (NULL); 2351 cookie->pidx = -1; 2352 cookie->ndesc = ndesc; 2353 return (&wr->wr); 2354 } 2355 2356 eq->cidx = read_hw_cidx(eq); 2357 if (eq->pidx == eq->cidx) 2358 available = eq->sidx - 1; 2359 else 2360 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2361 if (available < ndesc) 2362 goto slowpath; 2363 2364 cookie->pidx = eq->pidx; 2365 cookie->ndesc = ndesc; 2366 TAILQ_INSERT_TAIL(&wrq->incomplete_wrs, cookie, link); 2367 2368 w = &eq->desc[eq->pidx]; 2369 IDXINCR(eq->pidx, ndesc, eq->sidx); 2370 if (__predict_false(cookie->pidx + ndesc > eq->sidx)) { 2371 w = &wrq->ss[0]; 2372 wrq->ss_pidx = cookie->pidx; 2373 wrq->ss_len = len16 * 16; 2374 } 2375 2376 EQ_UNLOCK(eq); 2377 2378 return (w); 2379 } 2380 2381 void 2382 commit_wrq_wr(struct sge_wrq *wrq, void *w, struct wrq_cookie *cookie) 2383 { 2384 struct sge_eq *eq = &wrq->eq; 2385 struct adapter *sc = wrq->adapter; 2386 int ndesc, pidx; 2387 struct wrq_cookie *prev, *next; 2388 2389 if (cookie->pidx == -1) { 2390 struct wrqe *wr = __containerof(w, struct wrqe, wr); 2391 2392 t4_wrq_tx(sc, wr); 2393 return; 2394 } 2395 2396 ndesc = cookie->ndesc; /* Can be more than SGE_MAX_WR_NDESC here. */ 2397 pidx = cookie->pidx; 2398 MPASS(pidx >= 0 && pidx < eq->sidx); 2399 if (__predict_false(w == &wrq->ss[0])) { 2400 int n = (eq->sidx - wrq->ss_pidx) * EQ_ESIZE; 2401 2402 MPASS(wrq->ss_len > n); /* WR had better wrap around. */ 2403 bcopy(&wrq->ss[0], &eq->desc[wrq->ss_pidx], n); 2404 bcopy(&wrq->ss[n], &eq->desc[0], wrq->ss_len - n); 2405 wrq->tx_wrs_ss++; 2406 } else 2407 wrq->tx_wrs_direct++; 2408 2409 EQ_LOCK(eq); 2410 prev = TAILQ_PREV(cookie, wrq_incomplete_wrs, link); 2411 next = TAILQ_NEXT(cookie, link); 2412 if (prev == NULL) { 2413 MPASS(pidx == eq->dbidx); 2414 if (next == NULL || ndesc >= 16) 2415 ring_eq_db(wrq->adapter, eq, ndesc); 2416 else { 2417 MPASS(IDXDIFF(next->pidx, pidx, eq->sidx) == ndesc); 2418 next->pidx = pidx; 2419 next->ndesc += ndesc; 2420 } 2421 } else { 2422 MPASS(IDXDIFF(pidx, prev->pidx, eq->sidx) == prev->ndesc); 2423 prev->ndesc += ndesc; 2424 } 2425 TAILQ_REMOVE(&wrq->incomplete_wrs, cookie, link); 2426 2427 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 2428 drain_wrq_wr_list(sc, wrq); 2429 2430 #ifdef INVARIANTS 2431 if (TAILQ_EMPTY(&wrq->incomplete_wrs)) { 2432 /* Doorbell must have caught up to the pidx. */ 2433 MPASS(wrq->eq.pidx == wrq->eq.dbidx); 2434 } 2435 #endif 2436 EQ_UNLOCK(eq); 2437 } 2438 2439 static u_int 2440 can_resume_eth_tx(struct mp_ring *r) 2441 { 2442 struct sge_eq *eq = r->cookie; 2443 2444 return (total_available_tx_desc(eq) > eq->sidx / 8); 2445 } 2446 2447 static inline int 2448 cannot_use_txpkts(struct mbuf *m) 2449 { 2450 /* maybe put a GL limit too, to avoid silliness? */ 2451 2452 return (needs_tso(m)); 2453 } 2454 2455 static inline int 2456 discard_tx(struct sge_eq *eq) 2457 { 2458 2459 return ((eq->flags & (EQ_ENABLED | EQ_QFLUSH)) != EQ_ENABLED); 2460 } 2461 2462 /* 2463 * r->items[cidx] to r->items[pidx], with a wraparound at r->size, are ready to 2464 * be consumed. Return the actual number consumed. 0 indicates a stall. 2465 */ 2466 static u_int 2467 eth_tx(struct mp_ring *r, u_int cidx, u_int pidx) 2468 { 2469 struct sge_txq *txq = r->cookie; 2470 struct sge_eq *eq = &txq->eq; 2471 struct ifnet *ifp = txq->ifp; 2472 struct vi_info *vi = ifp->if_softc; 2473 struct port_info *pi = vi->pi; 2474 struct adapter *sc = pi->adapter; 2475 u_int total, remaining; /* # of packets */ 2476 u_int available, dbdiff; /* # of hardware descriptors */ 2477 u_int n, next_cidx; 2478 struct mbuf *m0, *tail; 2479 struct txpkts txp; 2480 struct fw_eth_tx_pkts_wr *wr; /* any fw WR struct will do */ 2481 2482 remaining = IDXDIFF(pidx, cidx, r->size); 2483 MPASS(remaining > 0); /* Must not be called without work to do. */ 2484 total = 0; 2485 2486 TXQ_LOCK(txq); 2487 if (__predict_false(discard_tx(eq))) { 2488 while (cidx != pidx) { 2489 m0 = r->items[cidx]; 2490 m_freem(m0); 2491 if (++cidx == r->size) 2492 cidx = 0; 2493 } 2494 reclaim_tx_descs(txq, 2048); 2495 total = remaining; 2496 goto done; 2497 } 2498 2499 /* How many hardware descriptors do we have readily available. */ 2500 if (eq->pidx == eq->cidx) 2501 available = eq->sidx - 1; 2502 else 2503 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 2504 dbdiff = IDXDIFF(eq->pidx, eq->dbidx, eq->sidx); 2505 2506 while (remaining > 0) { 2507 2508 m0 = r->items[cidx]; 2509 M_ASSERTPKTHDR(m0); 2510 MPASS(m0->m_nextpkt == NULL); 2511 2512 if (available < SGE_MAX_WR_NDESC) { 2513 available += reclaim_tx_descs(txq, 64); 2514 if (available < howmany(mbuf_len16(m0), EQ_ESIZE / 16)) 2515 break; /* out of descriptors */ 2516 } 2517 2518 next_cidx = cidx + 1; 2519 if (__predict_false(next_cidx == r->size)) 2520 next_cidx = 0; 2521 2522 wr = (void *)&eq->desc[eq->pidx]; 2523 if (sc->flags & IS_VF) { 2524 total++; 2525 remaining--; 2526 ETHER_BPF_MTAP(ifp, m0); 2527 n = write_txpkt_vm_wr(sc, txq, (void *)wr, m0, 2528 available); 2529 } else if (remaining > 1 && 2530 try_txpkts(m0, r->items[next_cidx], &txp, available) == 0) { 2531 2532 /* pkts at cidx, next_cidx should both be in txp. */ 2533 MPASS(txp.npkt == 2); 2534 tail = r->items[next_cidx]; 2535 MPASS(tail->m_nextpkt == NULL); 2536 ETHER_BPF_MTAP(ifp, m0); 2537 ETHER_BPF_MTAP(ifp, tail); 2538 m0->m_nextpkt = tail; 2539 2540 if (__predict_false(++next_cidx == r->size)) 2541 next_cidx = 0; 2542 2543 while (next_cidx != pidx) { 2544 if (add_to_txpkts(r->items[next_cidx], &txp, 2545 available) != 0) 2546 break; 2547 tail->m_nextpkt = r->items[next_cidx]; 2548 tail = tail->m_nextpkt; 2549 ETHER_BPF_MTAP(ifp, tail); 2550 if (__predict_false(++next_cidx == r->size)) 2551 next_cidx = 0; 2552 } 2553 2554 n = write_txpkts_wr(txq, wr, m0, &txp, available); 2555 total += txp.npkt; 2556 remaining -= txp.npkt; 2557 } else { 2558 total++; 2559 remaining--; 2560 ETHER_BPF_MTAP(ifp, m0); 2561 n = write_txpkt_wr(txq, (void *)wr, m0, available); 2562 } 2563 MPASS(n >= 1 && n <= available && n <= SGE_MAX_WR_NDESC); 2564 2565 available -= n; 2566 dbdiff += n; 2567 IDXINCR(eq->pidx, n, eq->sidx); 2568 2569 if (total_available_tx_desc(eq) < eq->sidx / 4 && 2570 atomic_cmpset_int(&eq->equiq, 0, 1)) { 2571 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ | 2572 F_FW_WR_EQUEQ); 2573 eq->equeqidx = eq->pidx; 2574 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 32) { 2575 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ); 2576 eq->equeqidx = eq->pidx; 2577 } 2578 2579 if (dbdiff >= 16 && remaining >= 4) { 2580 ring_eq_db(sc, eq, dbdiff); 2581 available += reclaim_tx_descs(txq, 4 * dbdiff); 2582 dbdiff = 0; 2583 } 2584 2585 cidx = next_cidx; 2586 } 2587 if (dbdiff != 0) { 2588 ring_eq_db(sc, eq, dbdiff); 2589 reclaim_tx_descs(txq, 32); 2590 } 2591 done: 2592 TXQ_UNLOCK(txq); 2593 2594 return (total); 2595 } 2596 2597 static inline void 2598 init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int pktc_idx, 2599 int qsize) 2600 { 2601 2602 KASSERT(tmr_idx >= 0 && tmr_idx < SGE_NTIMERS, 2603 ("%s: bad tmr_idx %d", __func__, tmr_idx)); 2604 KASSERT(pktc_idx < SGE_NCOUNTERS, /* -ve is ok, means don't use */ 2605 ("%s: bad pktc_idx %d", __func__, pktc_idx)); 2606 2607 iq->flags = 0; 2608 iq->adapter = sc; 2609 iq->intr_params = V_QINTR_TIMER_IDX(tmr_idx); 2610 iq->intr_pktc_idx = SGE_NCOUNTERS - 1; 2611 if (pktc_idx >= 0) { 2612 iq->intr_params |= F_QINTR_CNT_EN; 2613 iq->intr_pktc_idx = pktc_idx; 2614 } 2615 iq->qsize = roundup2(qsize, 16); /* See FW_IQ_CMD/iqsize */ 2616 iq->sidx = iq->qsize - sc->params.sge.spg_len / IQ_ESIZE; 2617 } 2618 2619 static inline void 2620 init_fl(struct adapter *sc, struct sge_fl *fl, int qsize, int maxp, char *name) 2621 { 2622 2623 fl->qsize = qsize; 2624 fl->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE; 2625 strlcpy(fl->lockname, name, sizeof(fl->lockname)); 2626 if (sc->flags & BUF_PACKING_OK && 2627 ((!is_t4(sc) && buffer_packing) || /* T5+: enabled unless 0 */ 2628 (is_t4(sc) && buffer_packing == 1)))/* T4: disabled unless 1 */ 2629 fl->flags |= FL_BUF_PACKING; 2630 find_best_refill_source(sc, fl, maxp); 2631 find_safe_refill_source(sc, fl); 2632 } 2633 2634 static inline void 2635 init_eq(struct adapter *sc, struct sge_eq *eq, int eqtype, int qsize, 2636 uint8_t tx_chan, uint16_t iqid, char *name) 2637 { 2638 KASSERT(eqtype <= EQ_TYPEMASK, ("%s: bad qtype %d", __func__, eqtype)); 2639 2640 eq->flags = eqtype & EQ_TYPEMASK; 2641 eq->tx_chan = tx_chan; 2642 eq->iqid = iqid; 2643 eq->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE; 2644 strlcpy(eq->lockname, name, sizeof(eq->lockname)); 2645 } 2646 2647 static int 2648 alloc_ring(struct adapter *sc, size_t len, bus_dma_tag_t *tag, 2649 bus_dmamap_t *map, bus_addr_t *pa, void **va) 2650 { 2651 int rc; 2652 2653 rc = bus_dma_tag_create(sc->dmat, 512, 0, BUS_SPACE_MAXADDR, 2654 BUS_SPACE_MAXADDR, NULL, NULL, len, 1, len, 0, NULL, NULL, tag); 2655 if (rc != 0) { 2656 device_printf(sc->dev, "cannot allocate DMA tag: %d\n", rc); 2657 goto done; 2658 } 2659 2660 rc = bus_dmamem_alloc(*tag, va, 2661 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, map); 2662 if (rc != 0) { 2663 device_printf(sc->dev, "cannot allocate DMA memory: %d\n", rc); 2664 goto done; 2665 } 2666 2667 rc = bus_dmamap_load(*tag, *map, *va, len, oneseg_dma_callback, pa, 0); 2668 if (rc != 0) { 2669 device_printf(sc->dev, "cannot load DMA map: %d\n", rc); 2670 goto done; 2671 } 2672 done: 2673 if (rc) 2674 free_ring(sc, *tag, *map, *pa, *va); 2675 2676 return (rc); 2677 } 2678 2679 static int 2680 free_ring(struct adapter *sc, bus_dma_tag_t tag, bus_dmamap_t map, 2681 bus_addr_t pa, void *va) 2682 { 2683 if (pa) 2684 bus_dmamap_unload(tag, map); 2685 if (va) 2686 bus_dmamem_free(tag, va, map); 2687 if (tag) 2688 bus_dma_tag_destroy(tag); 2689 2690 return (0); 2691 } 2692 2693 /* 2694 * Allocates the ring for an ingress queue and an optional freelist. If the 2695 * freelist is specified it will be allocated and then associated with the 2696 * ingress queue. 2697 * 2698 * Returns errno on failure. Resources allocated up to that point may still be 2699 * allocated. Caller is responsible for cleanup in case this function fails. 2700 * 2701 * If the ingress queue will take interrupts directly (iq->flags & IQ_INTR) then 2702 * the intr_idx specifies the vector, starting from 0. Otherwise it specifies 2703 * the abs_id of the ingress queue to which its interrupts should be forwarded. 2704 */ 2705 static int 2706 alloc_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl, 2707 int intr_idx, int cong) 2708 { 2709 int rc, i, cntxt_id; 2710 size_t len; 2711 struct fw_iq_cmd c; 2712 struct port_info *pi = vi->pi; 2713 struct adapter *sc = iq->adapter; 2714 struct sge_params *sp = &sc->params.sge; 2715 __be32 v = 0; 2716 2717 len = iq->qsize * IQ_ESIZE; 2718 rc = alloc_ring(sc, len, &iq->desc_tag, &iq->desc_map, &iq->ba, 2719 (void **)&iq->desc); 2720 if (rc != 0) 2721 return (rc); 2722 2723 bzero(&c, sizeof(c)); 2724 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 2725 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) | 2726 V_FW_IQ_CMD_VFN(0)); 2727 2728 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART | 2729 FW_LEN16(c)); 2730 2731 /* Special handling for firmware event queue */ 2732 if (iq == &sc->sge.fwq) 2733 v |= F_FW_IQ_CMD_IQASYNCH; 2734 2735 if (iq->flags & IQ_INTR) { 2736 KASSERT(intr_idx < sc->intr_count, 2737 ("%s: invalid direct intr_idx %d", __func__, intr_idx)); 2738 } else 2739 v |= F_FW_IQ_CMD_IQANDST; 2740 v |= V_FW_IQ_CMD_IQANDSTINDEX(intr_idx); 2741 2742 c.type_to_iqandstindex = htobe32(v | 2743 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) | 2744 V_FW_IQ_CMD_VIID(vi->viid) | 2745 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT)); 2746 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->tx_chan) | 2747 F_FW_IQ_CMD_IQGTSMODE | 2748 V_FW_IQ_CMD_IQINTCNTTHRESH(iq->intr_pktc_idx) | 2749 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4)); 2750 c.iqsize = htobe16(iq->qsize); 2751 c.iqaddr = htobe64(iq->ba); 2752 if (cong >= 0) 2753 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN); 2754 2755 if (fl) { 2756 mtx_init(&fl->fl_lock, fl->lockname, NULL, MTX_DEF); 2757 2758 len = fl->qsize * EQ_ESIZE; 2759 rc = alloc_ring(sc, len, &fl->desc_tag, &fl->desc_map, 2760 &fl->ba, (void **)&fl->desc); 2761 if (rc) 2762 return (rc); 2763 2764 /* Allocate space for one software descriptor per buffer. */ 2765 rc = alloc_fl_sdesc(fl); 2766 if (rc != 0) { 2767 device_printf(sc->dev, 2768 "failed to setup fl software descriptors: %d\n", 2769 rc); 2770 return (rc); 2771 } 2772 2773 if (fl->flags & FL_BUF_PACKING) { 2774 fl->lowat = roundup2(sp->fl_starve_threshold2, 8); 2775 fl->buf_boundary = sp->pack_boundary; 2776 } else { 2777 fl->lowat = roundup2(sp->fl_starve_threshold, 8); 2778 fl->buf_boundary = 16; 2779 } 2780 if (fl_pad && fl->buf_boundary < sp->pad_boundary) 2781 fl->buf_boundary = sp->pad_boundary; 2782 2783 c.iqns_to_fl0congen |= 2784 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) | 2785 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO | 2786 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) | 2787 (fl->flags & FL_BUF_PACKING ? F_FW_IQ_CMD_FL0PACKEN : 2788 0)); 2789 if (cong >= 0) { 2790 c.iqns_to_fl0congen |= 2791 htobe32(V_FW_IQ_CMD_FL0CNGCHMAP(cong) | 2792 F_FW_IQ_CMD_FL0CONGCIF | 2793 F_FW_IQ_CMD_FL0CONGEN); 2794 } 2795 c.fl0dcaen_to_fl0cidxfthresh = 2796 htobe16(V_FW_IQ_CMD_FL0FBMIN(chip_id(sc) <= CHELSIO_T5 ? 2797 X_FETCHBURSTMIN_128B : X_FETCHBURSTMIN_64B) | 2798 V_FW_IQ_CMD_FL0FBMAX(chip_id(sc) <= CHELSIO_T5 ? 2799 X_FETCHBURSTMAX_512B : X_FETCHBURSTMAX_256B)); 2800 c.fl0size = htobe16(fl->qsize); 2801 c.fl0addr = htobe64(fl->ba); 2802 } 2803 2804 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 2805 if (rc != 0) { 2806 device_printf(sc->dev, 2807 "failed to create ingress queue: %d\n", rc); 2808 return (rc); 2809 } 2810 2811 iq->cidx = 0; 2812 iq->gen = F_RSPD_GEN; 2813 iq->intr_next = iq->intr_params; 2814 iq->cntxt_id = be16toh(c.iqid); 2815 iq->abs_id = be16toh(c.physiqid); 2816 iq->flags |= IQ_ALLOCATED; 2817 2818 cntxt_id = iq->cntxt_id - sc->sge.iq_start; 2819 if (cntxt_id >= sc->sge.niq) { 2820 panic ("%s: iq->cntxt_id (%d) more than the max (%d)", __func__, 2821 cntxt_id, sc->sge.niq - 1); 2822 } 2823 sc->sge.iqmap[cntxt_id] = iq; 2824 2825 if (fl) { 2826 u_int qid; 2827 2828 iq->flags |= IQ_HAS_FL; 2829 fl->cntxt_id = be16toh(c.fl0id); 2830 fl->pidx = fl->cidx = 0; 2831 2832 cntxt_id = fl->cntxt_id - sc->sge.eq_start; 2833 if (cntxt_id >= sc->sge.neq) { 2834 panic("%s: fl->cntxt_id (%d) more than the max (%d)", 2835 __func__, cntxt_id, sc->sge.neq - 1); 2836 } 2837 sc->sge.eqmap[cntxt_id] = (void *)fl; 2838 2839 qid = fl->cntxt_id; 2840 if (isset(&sc->doorbells, DOORBELL_UDB)) { 2841 uint32_t s_qpp = sc->params.sge.eq_s_qpp; 2842 uint32_t mask = (1 << s_qpp) - 1; 2843 volatile uint8_t *udb; 2844 2845 udb = sc->udbs_base + UDBS_DB_OFFSET; 2846 udb += (qid >> s_qpp) << PAGE_SHIFT; 2847 qid &= mask; 2848 if (qid < PAGE_SIZE / UDBS_SEG_SIZE) { 2849 udb += qid << UDBS_SEG_SHIFT; 2850 qid = 0; 2851 } 2852 fl->udb = (volatile void *)udb; 2853 } 2854 fl->dbval = V_QID(qid) | sc->chip_params->sge_fl_db; 2855 2856 FL_LOCK(fl); 2857 /* Enough to make sure the SGE doesn't think it's starved */ 2858 refill_fl(sc, fl, fl->lowat); 2859 FL_UNLOCK(fl); 2860 } 2861 2862 if (chip_id(sc) >= CHELSIO_T5 && !(sc->flags & IS_VF) && cong >= 0) { 2863 uint32_t param, val; 2864 2865 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 2866 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) | 2867 V_FW_PARAMS_PARAM_YZ(iq->cntxt_id); 2868 if (cong == 0) 2869 val = 1 << 19; 2870 else { 2871 val = 2 << 19; 2872 for (i = 0; i < 4; i++) { 2873 if (cong & (1 << i)) 2874 val |= 1 << (i << 2); 2875 } 2876 } 2877 2878 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 2879 if (rc != 0) { 2880 /* report error but carry on */ 2881 device_printf(sc->dev, 2882 "failed to set congestion manager context for " 2883 "ingress queue %d: %d\n", iq->cntxt_id, rc); 2884 } 2885 } 2886 2887 /* Enable IQ interrupts */ 2888 atomic_store_rel_int(&iq->state, IQS_IDLE); 2889 t4_write_reg(sc, sc->sge_gts_reg, V_SEINTARM(iq->intr_params) | 2890 V_INGRESSQID(iq->cntxt_id)); 2891 2892 return (0); 2893 } 2894 2895 static int 2896 free_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl) 2897 { 2898 int rc; 2899 struct adapter *sc = iq->adapter; 2900 device_t dev; 2901 2902 if (sc == NULL) 2903 return (0); /* nothing to do */ 2904 2905 dev = vi ? vi->dev : sc->dev; 2906 2907 if (iq->flags & IQ_ALLOCATED) { 2908 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0, 2909 FW_IQ_TYPE_FL_INT_CAP, iq->cntxt_id, 2910 fl ? fl->cntxt_id : 0xffff, 0xffff); 2911 if (rc != 0) { 2912 device_printf(dev, 2913 "failed to free queue %p: %d\n", iq, rc); 2914 return (rc); 2915 } 2916 iq->flags &= ~IQ_ALLOCATED; 2917 } 2918 2919 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, iq->desc); 2920 2921 bzero(iq, sizeof(*iq)); 2922 2923 if (fl) { 2924 free_ring(sc, fl->desc_tag, fl->desc_map, fl->ba, 2925 fl->desc); 2926 2927 if (fl->sdesc) 2928 free_fl_sdesc(sc, fl); 2929 2930 if (mtx_initialized(&fl->fl_lock)) 2931 mtx_destroy(&fl->fl_lock); 2932 2933 bzero(fl, sizeof(*fl)); 2934 } 2935 2936 return (0); 2937 } 2938 2939 static void 2940 add_fl_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx, 2941 struct sysctl_oid *oid, struct sge_fl *fl) 2942 { 2943 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 2944 2945 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL, 2946 "freelist"); 2947 children = SYSCTL_CHILDREN(oid); 2948 2949 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, 2950 &fl->ba, "bus address of descriptor ring"); 2951 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 2952 fl->sidx * EQ_ESIZE + sc->params.sge.spg_len, 2953 "desc ring size in bytes"); 2954 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 2955 CTLTYPE_INT | CTLFLAG_RD, &fl->cntxt_id, 0, sysctl_uint16, "I", 2956 "SGE context id of the freelist"); 2957 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "padding", CTLFLAG_RD, NULL, 2958 fl_pad ? 1 : 0, "padding enabled"); 2959 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "packing", CTLFLAG_RD, NULL, 2960 fl->flags & FL_BUF_PACKING ? 1 : 0, "packing enabled"); 2961 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &fl->cidx, 2962 0, "consumer index"); 2963 if (fl->flags & FL_BUF_PACKING) { 2964 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rx_offset", 2965 CTLFLAG_RD, &fl->rx_offset, 0, "packing rx offset"); 2966 } 2967 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &fl->pidx, 2968 0, "producer index"); 2969 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_allocated", 2970 CTLFLAG_RD, &fl->mbuf_allocated, "# of mbuf allocated"); 2971 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_inlined", 2972 CTLFLAG_RD, &fl->mbuf_inlined, "# of mbuf inlined in clusters"); 2973 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_allocated", 2974 CTLFLAG_RD, &fl->cl_allocated, "# of clusters allocated"); 2975 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_recycled", 2976 CTLFLAG_RD, &fl->cl_recycled, "# of clusters recycled"); 2977 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_fast_recycled", 2978 CTLFLAG_RD, &fl->cl_fast_recycled, "# of clusters recycled (fast)"); 2979 } 2980 2981 static int 2982 alloc_fwq(struct adapter *sc) 2983 { 2984 int rc, intr_idx; 2985 struct sge_iq *fwq = &sc->sge.fwq; 2986 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev); 2987 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 2988 2989 init_iq(fwq, sc, 0, 0, FW_IQ_QSIZE); 2990 fwq->flags |= IQ_INTR; /* always */ 2991 if (sc->flags & IS_VF) 2992 intr_idx = 0; 2993 else { 2994 intr_idx = sc->intr_count > 1 ? 1 : 0; 2995 fwq->set_tcb_rpl = t4_filter_rpl; 2996 fwq->l2t_write_rpl = do_l2t_write_rpl; 2997 } 2998 rc = alloc_iq_fl(&sc->port[0]->vi[0], fwq, NULL, intr_idx, -1); 2999 if (rc != 0) { 3000 device_printf(sc->dev, 3001 "failed to create firmware event queue: %d\n", rc); 3002 return (rc); 3003 } 3004 3005 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "fwq", CTLFLAG_RD, 3006 NULL, "firmware event queue"); 3007 children = SYSCTL_CHILDREN(oid); 3008 3009 SYSCTL_ADD_UAUTO(&sc->ctx, children, OID_AUTO, "ba", CTLFLAG_RD, 3010 &fwq->ba, "bus address of descriptor ring"); 3011 SYSCTL_ADD_INT(&sc->ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3012 fwq->qsize * IQ_ESIZE, "descriptor ring size in bytes"); 3013 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "abs_id", 3014 CTLTYPE_INT | CTLFLAG_RD, &fwq->abs_id, 0, sysctl_uint16, "I", 3015 "absolute id of the queue"); 3016 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "cntxt_id", 3017 CTLTYPE_INT | CTLFLAG_RD, &fwq->cntxt_id, 0, sysctl_uint16, "I", 3018 "SGE context id of the queue"); 3019 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "cidx", 3020 CTLTYPE_INT | CTLFLAG_RD, &fwq->cidx, 0, sysctl_uint16, "I", 3021 "consumer index"); 3022 3023 return (0); 3024 } 3025 3026 static int 3027 free_fwq(struct adapter *sc) 3028 { 3029 return free_iq_fl(NULL, &sc->sge.fwq, NULL); 3030 } 3031 3032 static int 3033 alloc_mgmtq(struct adapter *sc) 3034 { 3035 int rc; 3036 struct sge_wrq *mgmtq = &sc->sge.mgmtq; 3037 char name[16]; 3038 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev); 3039 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3040 3041 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "mgmtq", CTLFLAG_RD, 3042 NULL, "management queue"); 3043 3044 snprintf(name, sizeof(name), "%s mgmtq", device_get_nameunit(sc->dev)); 3045 init_eq(sc, &mgmtq->eq, EQ_CTRL, CTRL_EQ_QSIZE, sc->port[0]->tx_chan, 3046 sc->sge.fwq.cntxt_id, name); 3047 rc = alloc_wrq(sc, NULL, mgmtq, oid); 3048 if (rc != 0) { 3049 device_printf(sc->dev, 3050 "failed to create management queue: %d\n", rc); 3051 return (rc); 3052 } 3053 3054 return (0); 3055 } 3056 3057 static int 3058 free_mgmtq(struct adapter *sc) 3059 { 3060 3061 return free_wrq(sc, &sc->sge.mgmtq); 3062 } 3063 3064 int 3065 tnl_cong(struct port_info *pi, int drop) 3066 { 3067 3068 if (drop == -1) 3069 return (-1); 3070 else if (drop == 1) 3071 return (0); 3072 else 3073 return (pi->rx_chan_map); 3074 } 3075 3076 static int 3077 alloc_rxq(struct vi_info *vi, struct sge_rxq *rxq, int intr_idx, int idx, 3078 struct sysctl_oid *oid) 3079 { 3080 int rc; 3081 struct adapter *sc = vi->pi->adapter; 3082 struct sysctl_oid_list *children; 3083 char name[16]; 3084 3085 rc = alloc_iq_fl(vi, &rxq->iq, &rxq->fl, intr_idx, 3086 tnl_cong(vi->pi, cong_drop)); 3087 if (rc != 0) 3088 return (rc); 3089 3090 if (idx == 0) 3091 sc->sge.iq_base = rxq->iq.abs_id - rxq->iq.cntxt_id; 3092 else 3093 KASSERT(rxq->iq.cntxt_id + sc->sge.iq_base == rxq->iq.abs_id, 3094 ("iq_base mismatch")); 3095 KASSERT(sc->sge.iq_base == 0 || sc->flags & IS_VF, 3096 ("PF with non-zero iq_base")); 3097 3098 /* 3099 * The freelist is just barely above the starvation threshold right now, 3100 * fill it up a bit more. 3101 */ 3102 FL_LOCK(&rxq->fl); 3103 refill_fl(sc, &rxq->fl, 128); 3104 FL_UNLOCK(&rxq->fl); 3105 3106 #if defined(INET) || defined(INET6) 3107 rc = tcp_lro_init_args(&rxq->lro, vi->ifp, lro_entries, lro_mbufs); 3108 if (rc != 0) 3109 return (rc); 3110 MPASS(rxq->lro.ifp == vi->ifp); /* also indicates LRO init'ed */ 3111 3112 if (vi->ifp->if_capenable & IFCAP_LRO) 3113 rxq->iq.flags |= IQ_LRO_ENABLED; 3114 #endif 3115 rxq->ifp = vi->ifp; 3116 3117 children = SYSCTL_CHILDREN(oid); 3118 3119 snprintf(name, sizeof(name), "%d", idx); 3120 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 3121 NULL, "rx queue"); 3122 children = SYSCTL_CHILDREN(oid); 3123 3124 SYSCTL_ADD_UAUTO(&vi->ctx, children, OID_AUTO, "ba", CTLFLAG_RD, 3125 &rxq->iq.ba, "bus address of descriptor ring"); 3126 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3127 rxq->iq.qsize * IQ_ESIZE, "descriptor ring size in bytes"); 3128 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "abs_id", 3129 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.abs_id, 0, sysctl_uint16, "I", 3130 "absolute id of the queue"); 3131 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cntxt_id", 3132 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.cntxt_id, 0, sysctl_uint16, "I", 3133 "SGE context id of the queue"); 3134 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx", 3135 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.cidx, 0, sysctl_uint16, "I", 3136 "consumer index"); 3137 #if defined(INET) || defined(INET6) 3138 SYSCTL_ADD_U64(&vi->ctx, children, OID_AUTO, "lro_queued", CTLFLAG_RD, 3139 &rxq->lro.lro_queued, 0, NULL); 3140 SYSCTL_ADD_U64(&vi->ctx, children, OID_AUTO, "lro_flushed", CTLFLAG_RD, 3141 &rxq->lro.lro_flushed, 0, NULL); 3142 #endif 3143 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "rxcsum", CTLFLAG_RD, 3144 &rxq->rxcsum, "# of times hardware assisted with checksum"); 3145 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_extraction", 3146 CTLFLAG_RD, &rxq->vlan_extraction, 3147 "# of times hardware extracted 802.1Q tag"); 3148 3149 add_fl_sysctls(sc, &vi->ctx, oid, &rxq->fl); 3150 3151 return (rc); 3152 } 3153 3154 static int 3155 free_rxq(struct vi_info *vi, struct sge_rxq *rxq) 3156 { 3157 int rc; 3158 3159 #if defined(INET) || defined(INET6) 3160 if (rxq->lro.ifp) { 3161 tcp_lro_free(&rxq->lro); 3162 rxq->lro.ifp = NULL; 3163 } 3164 #endif 3165 3166 rc = free_iq_fl(vi, &rxq->iq, &rxq->fl); 3167 if (rc == 0) 3168 bzero(rxq, sizeof(*rxq)); 3169 3170 return (rc); 3171 } 3172 3173 #ifdef TCP_OFFLOAD 3174 static int 3175 alloc_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq, 3176 int intr_idx, int idx, struct sysctl_oid *oid) 3177 { 3178 struct port_info *pi = vi->pi; 3179 int rc; 3180 struct sysctl_oid_list *children; 3181 char name[16]; 3182 3183 rc = alloc_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl, intr_idx, 3184 pi->rx_chan_map); 3185 if (rc != 0) 3186 return (rc); 3187 3188 children = SYSCTL_CHILDREN(oid); 3189 3190 snprintf(name, sizeof(name), "%d", idx); 3191 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 3192 NULL, "rx queue"); 3193 children = SYSCTL_CHILDREN(oid); 3194 3195 SYSCTL_ADD_UAUTO(&vi->ctx, children, OID_AUTO, "ba", CTLFLAG_RD, 3196 &ofld_rxq->iq.ba, "bus address of descriptor ring"); 3197 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3198 ofld_rxq->iq.qsize * IQ_ESIZE, "descriptor ring size in bytes"); 3199 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "abs_id", 3200 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.abs_id, 0, sysctl_uint16, 3201 "I", "absolute id of the queue"); 3202 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cntxt_id", 3203 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.cntxt_id, 0, sysctl_uint16, 3204 "I", "SGE context id of the queue"); 3205 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx", 3206 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.cidx, 0, sysctl_uint16, "I", 3207 "consumer index"); 3208 3209 add_fl_sysctls(pi->adapter, &vi->ctx, oid, &ofld_rxq->fl); 3210 3211 return (rc); 3212 } 3213 3214 static int 3215 free_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq) 3216 { 3217 int rc; 3218 3219 rc = free_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl); 3220 if (rc == 0) 3221 bzero(ofld_rxq, sizeof(*ofld_rxq)); 3222 3223 return (rc); 3224 } 3225 #endif 3226 3227 #ifdef DEV_NETMAP 3228 static int 3229 alloc_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq, int intr_idx, 3230 int idx, struct sysctl_oid *oid) 3231 { 3232 int rc; 3233 struct sysctl_oid_list *children; 3234 struct sysctl_ctx_list *ctx; 3235 char name[16]; 3236 size_t len; 3237 struct adapter *sc = vi->pi->adapter; 3238 struct netmap_adapter *na = NA(vi->ifp); 3239 3240 MPASS(na != NULL); 3241 3242 len = vi->qsize_rxq * IQ_ESIZE; 3243 rc = alloc_ring(sc, len, &nm_rxq->iq_desc_tag, &nm_rxq->iq_desc_map, 3244 &nm_rxq->iq_ba, (void **)&nm_rxq->iq_desc); 3245 if (rc != 0) 3246 return (rc); 3247 3248 len = na->num_rx_desc * EQ_ESIZE + sc->params.sge.spg_len; 3249 rc = alloc_ring(sc, len, &nm_rxq->fl_desc_tag, &nm_rxq->fl_desc_map, 3250 &nm_rxq->fl_ba, (void **)&nm_rxq->fl_desc); 3251 if (rc != 0) 3252 return (rc); 3253 3254 nm_rxq->vi = vi; 3255 nm_rxq->nid = idx; 3256 nm_rxq->iq_cidx = 0; 3257 nm_rxq->iq_sidx = vi->qsize_rxq - sc->params.sge.spg_len / IQ_ESIZE; 3258 nm_rxq->iq_gen = F_RSPD_GEN; 3259 nm_rxq->fl_pidx = nm_rxq->fl_cidx = 0; 3260 nm_rxq->fl_sidx = na->num_rx_desc; 3261 nm_rxq->intr_idx = intr_idx; 3262 3263 ctx = &vi->ctx; 3264 children = SYSCTL_CHILDREN(oid); 3265 3266 snprintf(name, sizeof(name), "%d", idx); 3267 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, name, CTLFLAG_RD, NULL, 3268 "rx queue"); 3269 children = SYSCTL_CHILDREN(oid); 3270 3271 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "abs_id", 3272 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_abs_id, 0, sysctl_uint16, 3273 "I", "absolute id of the queue"); 3274 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 3275 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cntxt_id, 0, sysctl_uint16, 3276 "I", "SGE context id of the queue"); 3277 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx", 3278 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cidx, 0, sysctl_uint16, "I", 3279 "consumer index"); 3280 3281 children = SYSCTL_CHILDREN(oid); 3282 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL, 3283 "freelist"); 3284 children = SYSCTL_CHILDREN(oid); 3285 3286 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 3287 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->fl_cntxt_id, 0, sysctl_uint16, 3288 "I", "SGE context id of the freelist"); 3289 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, 3290 &nm_rxq->fl_cidx, 0, "consumer index"); 3291 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, 3292 &nm_rxq->fl_pidx, 0, "producer index"); 3293 3294 return (rc); 3295 } 3296 3297 3298 static int 3299 free_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq) 3300 { 3301 struct adapter *sc = vi->pi->adapter; 3302 3303 free_ring(sc, nm_rxq->iq_desc_tag, nm_rxq->iq_desc_map, nm_rxq->iq_ba, 3304 nm_rxq->iq_desc); 3305 free_ring(sc, nm_rxq->fl_desc_tag, nm_rxq->fl_desc_map, nm_rxq->fl_ba, 3306 nm_rxq->fl_desc); 3307 3308 return (0); 3309 } 3310 3311 static int 3312 alloc_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq, int iqidx, int idx, 3313 struct sysctl_oid *oid) 3314 { 3315 int rc; 3316 size_t len; 3317 struct port_info *pi = vi->pi; 3318 struct adapter *sc = pi->adapter; 3319 struct netmap_adapter *na = NA(vi->ifp); 3320 char name[16]; 3321 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3322 3323 len = na->num_tx_desc * EQ_ESIZE + sc->params.sge.spg_len; 3324 rc = alloc_ring(sc, len, &nm_txq->desc_tag, &nm_txq->desc_map, 3325 &nm_txq->ba, (void **)&nm_txq->desc); 3326 if (rc) 3327 return (rc); 3328 3329 nm_txq->pidx = nm_txq->cidx = 0; 3330 nm_txq->sidx = na->num_tx_desc; 3331 nm_txq->nid = idx; 3332 nm_txq->iqidx = iqidx; 3333 nm_txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) | 3334 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(G_FW_VIID_PFN(vi->viid)) | 3335 V_TXPKT_VF(G_FW_VIID_VIN(vi->viid)) | 3336 V_TXPKT_VF_VLD(G_FW_VIID_VIVLD(vi->viid))); 3337 3338 snprintf(name, sizeof(name), "%d", idx); 3339 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 3340 NULL, "netmap tx queue"); 3341 children = SYSCTL_CHILDREN(oid); 3342 3343 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 3344 &nm_txq->cntxt_id, 0, "SGE context id of the queue"); 3345 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx", 3346 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->cidx, 0, sysctl_uint16, "I", 3347 "consumer index"); 3348 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "pidx", 3349 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->pidx, 0, sysctl_uint16, "I", 3350 "producer index"); 3351 3352 return (rc); 3353 } 3354 3355 static int 3356 free_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq) 3357 { 3358 struct adapter *sc = vi->pi->adapter; 3359 3360 free_ring(sc, nm_txq->desc_tag, nm_txq->desc_map, nm_txq->ba, 3361 nm_txq->desc); 3362 3363 return (0); 3364 } 3365 #endif 3366 3367 static int 3368 ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq) 3369 { 3370 int rc, cntxt_id; 3371 struct fw_eq_ctrl_cmd c; 3372 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 3373 3374 bzero(&c, sizeof(c)); 3375 3376 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | F_FW_CMD_REQUEST | 3377 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_CTRL_CMD_PFN(sc->pf) | 3378 V_FW_EQ_CTRL_CMD_VFN(0)); 3379 c.alloc_to_len16 = htobe32(F_FW_EQ_CTRL_CMD_ALLOC | 3380 F_FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c)); 3381 c.cmpliqid_eqid = htonl(V_FW_EQ_CTRL_CMD_CMPLIQID(eq->iqid)); 3382 c.physeqid_pkd = htobe32(0); 3383 c.fetchszm_to_iqid = 3384 htobe32(V_FW_EQ_CTRL_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 3385 V_FW_EQ_CTRL_CMD_PCIECHN(eq->tx_chan) | 3386 F_FW_EQ_CTRL_CMD_FETCHRO | V_FW_EQ_CTRL_CMD_IQID(eq->iqid)); 3387 c.dcaen_to_eqsize = 3388 htobe32(V_FW_EQ_CTRL_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 3389 V_FW_EQ_CTRL_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 3390 V_FW_EQ_CTRL_CMD_CIDXFTHRESH(X_CIDXFLUSHTHRESH_32) | 3391 V_FW_EQ_CTRL_CMD_EQSIZE(qsize)); 3392 c.eqaddr = htobe64(eq->ba); 3393 3394 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3395 if (rc != 0) { 3396 device_printf(sc->dev, 3397 "failed to create control queue %d: %d\n", eq->tx_chan, rc); 3398 return (rc); 3399 } 3400 eq->flags |= EQ_ALLOCATED; 3401 3402 eq->cntxt_id = G_FW_EQ_CTRL_CMD_EQID(be32toh(c.cmpliqid_eqid)); 3403 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 3404 if (cntxt_id >= sc->sge.neq) 3405 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 3406 cntxt_id, sc->sge.neq - 1); 3407 sc->sge.eqmap[cntxt_id] = eq; 3408 3409 return (rc); 3410 } 3411 3412 static int 3413 eth_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 3414 { 3415 int rc, cntxt_id; 3416 struct fw_eq_eth_cmd c; 3417 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 3418 3419 bzero(&c, sizeof(c)); 3420 3421 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST | 3422 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) | 3423 V_FW_EQ_ETH_CMD_VFN(0)); 3424 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC | 3425 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c)); 3426 c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE | 3427 F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(vi->viid)); 3428 c.fetchszm_to_iqid = 3429 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) | 3430 V_FW_EQ_ETH_CMD_PCIECHN(eq->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO | 3431 V_FW_EQ_ETH_CMD_IQID(eq->iqid)); 3432 c.dcaen_to_eqsize = htobe32(V_FW_EQ_ETH_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 3433 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 3434 V_FW_EQ_ETH_CMD_EQSIZE(qsize)); 3435 c.eqaddr = htobe64(eq->ba); 3436 3437 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3438 if (rc != 0) { 3439 device_printf(vi->dev, 3440 "failed to create Ethernet egress queue: %d\n", rc); 3441 return (rc); 3442 } 3443 eq->flags |= EQ_ALLOCATED; 3444 3445 eq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd)); 3446 eq->abs_id = G_FW_EQ_ETH_CMD_PHYSEQID(be32toh(c.physeqid_pkd)); 3447 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 3448 if (cntxt_id >= sc->sge.neq) 3449 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 3450 cntxt_id, sc->sge.neq - 1); 3451 sc->sge.eqmap[cntxt_id] = eq; 3452 3453 return (rc); 3454 } 3455 3456 #ifdef TCP_OFFLOAD 3457 static int 3458 ofld_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 3459 { 3460 int rc, cntxt_id; 3461 struct fw_eq_ofld_cmd c; 3462 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 3463 3464 bzero(&c, sizeof(c)); 3465 3466 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | F_FW_CMD_REQUEST | 3467 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_OFLD_CMD_PFN(sc->pf) | 3468 V_FW_EQ_OFLD_CMD_VFN(0)); 3469 c.alloc_to_len16 = htonl(F_FW_EQ_OFLD_CMD_ALLOC | 3470 F_FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c)); 3471 c.fetchszm_to_iqid = 3472 htonl(V_FW_EQ_OFLD_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) | 3473 V_FW_EQ_OFLD_CMD_PCIECHN(eq->tx_chan) | 3474 F_FW_EQ_OFLD_CMD_FETCHRO | V_FW_EQ_OFLD_CMD_IQID(eq->iqid)); 3475 c.dcaen_to_eqsize = 3476 htobe32(V_FW_EQ_OFLD_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 3477 V_FW_EQ_OFLD_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 3478 V_FW_EQ_OFLD_CMD_EQSIZE(qsize)); 3479 c.eqaddr = htobe64(eq->ba); 3480 3481 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3482 if (rc != 0) { 3483 device_printf(vi->dev, 3484 "failed to create egress queue for TCP offload: %d\n", rc); 3485 return (rc); 3486 } 3487 eq->flags |= EQ_ALLOCATED; 3488 3489 eq->cntxt_id = G_FW_EQ_OFLD_CMD_EQID(be32toh(c.eqid_pkd)); 3490 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 3491 if (cntxt_id >= sc->sge.neq) 3492 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 3493 cntxt_id, sc->sge.neq - 1); 3494 sc->sge.eqmap[cntxt_id] = eq; 3495 3496 return (rc); 3497 } 3498 #endif 3499 3500 static int 3501 alloc_eq(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 3502 { 3503 int rc, qsize; 3504 size_t len; 3505 3506 mtx_init(&eq->eq_lock, eq->lockname, NULL, MTX_DEF); 3507 3508 qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 3509 len = qsize * EQ_ESIZE; 3510 rc = alloc_ring(sc, len, &eq->desc_tag, &eq->desc_map, 3511 &eq->ba, (void **)&eq->desc); 3512 if (rc) 3513 return (rc); 3514 3515 eq->pidx = eq->cidx = 0; 3516 eq->equeqidx = eq->dbidx = 0; 3517 eq->doorbells = sc->doorbells; 3518 3519 switch (eq->flags & EQ_TYPEMASK) { 3520 case EQ_CTRL: 3521 rc = ctrl_eq_alloc(sc, eq); 3522 break; 3523 3524 case EQ_ETH: 3525 rc = eth_eq_alloc(sc, vi, eq); 3526 break; 3527 3528 #ifdef TCP_OFFLOAD 3529 case EQ_OFLD: 3530 rc = ofld_eq_alloc(sc, vi, eq); 3531 break; 3532 #endif 3533 3534 default: 3535 panic("%s: invalid eq type %d.", __func__, 3536 eq->flags & EQ_TYPEMASK); 3537 } 3538 if (rc != 0) { 3539 device_printf(sc->dev, 3540 "failed to allocate egress queue(%d): %d\n", 3541 eq->flags & EQ_TYPEMASK, rc); 3542 } 3543 3544 if (isset(&eq->doorbells, DOORBELL_UDB) || 3545 isset(&eq->doorbells, DOORBELL_UDBWC) || 3546 isset(&eq->doorbells, DOORBELL_WCWR)) { 3547 uint32_t s_qpp = sc->params.sge.eq_s_qpp; 3548 uint32_t mask = (1 << s_qpp) - 1; 3549 volatile uint8_t *udb; 3550 3551 udb = sc->udbs_base + UDBS_DB_OFFSET; 3552 udb += (eq->cntxt_id >> s_qpp) << PAGE_SHIFT; /* pg offset */ 3553 eq->udb_qid = eq->cntxt_id & mask; /* id in page */ 3554 if (eq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE) 3555 clrbit(&eq->doorbells, DOORBELL_WCWR); 3556 else { 3557 udb += eq->udb_qid << UDBS_SEG_SHIFT; /* seg offset */ 3558 eq->udb_qid = 0; 3559 } 3560 eq->udb = (volatile void *)udb; 3561 } 3562 3563 return (rc); 3564 } 3565 3566 static int 3567 free_eq(struct adapter *sc, struct sge_eq *eq) 3568 { 3569 int rc; 3570 3571 if (eq->flags & EQ_ALLOCATED) { 3572 switch (eq->flags & EQ_TYPEMASK) { 3573 case EQ_CTRL: 3574 rc = -t4_ctrl_eq_free(sc, sc->mbox, sc->pf, 0, 3575 eq->cntxt_id); 3576 break; 3577 3578 case EQ_ETH: 3579 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0, 3580 eq->cntxt_id); 3581 break; 3582 3583 #ifdef TCP_OFFLOAD 3584 case EQ_OFLD: 3585 rc = -t4_ofld_eq_free(sc, sc->mbox, sc->pf, 0, 3586 eq->cntxt_id); 3587 break; 3588 #endif 3589 3590 default: 3591 panic("%s: invalid eq type %d.", __func__, 3592 eq->flags & EQ_TYPEMASK); 3593 } 3594 if (rc != 0) { 3595 device_printf(sc->dev, 3596 "failed to free egress queue (%d): %d\n", 3597 eq->flags & EQ_TYPEMASK, rc); 3598 return (rc); 3599 } 3600 eq->flags &= ~EQ_ALLOCATED; 3601 } 3602 3603 free_ring(sc, eq->desc_tag, eq->desc_map, eq->ba, eq->desc); 3604 3605 if (mtx_initialized(&eq->eq_lock)) 3606 mtx_destroy(&eq->eq_lock); 3607 3608 bzero(eq, sizeof(*eq)); 3609 return (0); 3610 } 3611 3612 static int 3613 alloc_wrq(struct adapter *sc, struct vi_info *vi, struct sge_wrq *wrq, 3614 struct sysctl_oid *oid) 3615 { 3616 int rc; 3617 struct sysctl_ctx_list *ctx = vi ? &vi->ctx : &sc->ctx; 3618 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3619 3620 rc = alloc_eq(sc, vi, &wrq->eq); 3621 if (rc) 3622 return (rc); 3623 3624 wrq->adapter = sc; 3625 TASK_INIT(&wrq->wrq_tx_task, 0, wrq_tx_drain, wrq); 3626 TAILQ_INIT(&wrq->incomplete_wrs); 3627 STAILQ_INIT(&wrq->wr_list); 3628 wrq->nwr_pending = 0; 3629 wrq->ndesc_needed = 0; 3630 3631 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, 3632 &wrq->eq.ba, "bus address of descriptor ring"); 3633 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3634 wrq->eq.sidx * EQ_ESIZE + sc->params.sge.spg_len, 3635 "desc ring size in bytes"); 3636 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 3637 &wrq->eq.cntxt_id, 0, "SGE context id of the queue"); 3638 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx", 3639 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.cidx, 0, sysctl_uint16, "I", 3640 "consumer index"); 3641 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pidx", 3642 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.pidx, 0, sysctl_uint16, "I", 3643 "producer index"); 3644 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL, 3645 wrq->eq.sidx, "status page index"); 3646 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_direct", CTLFLAG_RD, 3647 &wrq->tx_wrs_direct, "# of work requests (direct)"); 3648 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_copied", CTLFLAG_RD, 3649 &wrq->tx_wrs_copied, "# of work requests (copied)"); 3650 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_sspace", CTLFLAG_RD, 3651 &wrq->tx_wrs_ss, "# of work requests (copied from scratch space)"); 3652 3653 return (rc); 3654 } 3655 3656 static int 3657 free_wrq(struct adapter *sc, struct sge_wrq *wrq) 3658 { 3659 int rc; 3660 3661 rc = free_eq(sc, &wrq->eq); 3662 if (rc) 3663 return (rc); 3664 3665 bzero(wrq, sizeof(*wrq)); 3666 return (0); 3667 } 3668 3669 static int 3670 alloc_txq(struct vi_info *vi, struct sge_txq *txq, int idx, 3671 struct sysctl_oid *oid) 3672 { 3673 int rc; 3674 struct port_info *pi = vi->pi; 3675 struct adapter *sc = pi->adapter; 3676 struct sge_eq *eq = &txq->eq; 3677 char name[16]; 3678 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3679 3680 rc = mp_ring_alloc(&txq->r, eq->sidx, txq, eth_tx, can_resume_eth_tx, 3681 M_CXGBE, M_WAITOK); 3682 if (rc != 0) { 3683 device_printf(sc->dev, "failed to allocate mp_ring: %d\n", rc); 3684 return (rc); 3685 } 3686 3687 rc = alloc_eq(sc, vi, eq); 3688 if (rc != 0) { 3689 mp_ring_free(txq->r); 3690 txq->r = NULL; 3691 return (rc); 3692 } 3693 3694 /* Can't fail after this point. */ 3695 3696 if (idx == 0) 3697 sc->sge.eq_base = eq->abs_id - eq->cntxt_id; 3698 else 3699 KASSERT(eq->cntxt_id + sc->sge.eq_base == eq->abs_id, 3700 ("eq_base mismatch")); 3701 KASSERT(sc->sge.eq_base == 0 || sc->flags & IS_VF, 3702 ("PF with non-zero eq_base")); 3703 3704 TASK_INIT(&txq->tx_reclaim_task, 0, tx_reclaim, eq); 3705 txq->ifp = vi->ifp; 3706 txq->gl = sglist_alloc(TX_SGL_SEGS, M_WAITOK); 3707 if (sc->flags & IS_VF) 3708 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) | 3709 V_TXPKT_INTF(pi->tx_chan)); 3710 else 3711 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) | 3712 V_TXPKT_INTF(pi->tx_chan) | 3713 V_TXPKT_PF(G_FW_VIID_PFN(vi->viid)) | 3714 V_TXPKT_VF(G_FW_VIID_VIN(vi->viid)) | 3715 V_TXPKT_VF_VLD(G_FW_VIID_VIVLD(vi->viid))); 3716 txq->tc_idx = -1; 3717 txq->sdesc = malloc(eq->sidx * sizeof(struct tx_sdesc), M_CXGBE, 3718 M_ZERO | M_WAITOK); 3719 3720 snprintf(name, sizeof(name), "%d", idx); 3721 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 3722 NULL, "tx queue"); 3723 children = SYSCTL_CHILDREN(oid); 3724 3725 SYSCTL_ADD_UAUTO(&vi->ctx, children, OID_AUTO, "ba", CTLFLAG_RD, 3726 &eq->ba, "bus address of descriptor ring"); 3727 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3728 eq->sidx * EQ_ESIZE + sc->params.sge.spg_len, 3729 "desc ring size in bytes"); 3730 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "abs_id", CTLFLAG_RD, 3731 &eq->abs_id, 0, "absolute id of the queue"); 3732 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 3733 &eq->cntxt_id, 0, "SGE context id of the queue"); 3734 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx", 3735 CTLTYPE_INT | CTLFLAG_RD, &eq->cidx, 0, sysctl_uint16, "I", 3736 "consumer index"); 3737 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "pidx", 3738 CTLTYPE_INT | CTLFLAG_RD, &eq->pidx, 0, sysctl_uint16, "I", 3739 "producer index"); 3740 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL, 3741 eq->sidx, "status page index"); 3742 3743 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "tc", 3744 CTLTYPE_INT | CTLFLAG_RW, vi, idx, sysctl_tc, "I", 3745 "traffic class (-1 means none)"); 3746 3747 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txcsum", CTLFLAG_RD, 3748 &txq->txcsum, "# of times hardware assisted with checksum"); 3749 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_insertion", 3750 CTLFLAG_RD, &txq->vlan_insertion, 3751 "# of times hardware inserted 802.1Q tag"); 3752 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "tso_wrs", CTLFLAG_RD, 3753 &txq->tso_wrs, "# of TSO work requests"); 3754 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "imm_wrs", CTLFLAG_RD, 3755 &txq->imm_wrs, "# of work requests with immediate data"); 3756 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "sgl_wrs", CTLFLAG_RD, 3757 &txq->sgl_wrs, "# of work requests with direct SGL"); 3758 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkt_wrs", CTLFLAG_RD, 3759 &txq->txpkt_wrs, "# of txpkt work requests (one pkt/WR)"); 3760 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_wrs", 3761 CTLFLAG_RD, &txq->txpkts0_wrs, 3762 "# of txpkts (type 0) work requests"); 3763 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_wrs", 3764 CTLFLAG_RD, &txq->txpkts1_wrs, 3765 "# of txpkts (type 1) work requests"); 3766 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_pkts", 3767 CTLFLAG_RD, &txq->txpkts0_pkts, 3768 "# of frames tx'd using type0 txpkts work requests"); 3769 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_pkts", 3770 CTLFLAG_RD, &txq->txpkts1_pkts, 3771 "# of frames tx'd using type1 txpkts work requests"); 3772 3773 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_enqueues", 3774 CTLFLAG_RD, &txq->r->enqueues, 3775 "# of enqueues to the mp_ring for this queue"); 3776 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_drops", 3777 CTLFLAG_RD, &txq->r->drops, 3778 "# of drops in the mp_ring for this queue"); 3779 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_starts", 3780 CTLFLAG_RD, &txq->r->starts, 3781 "# of normal consumer starts in the mp_ring for this queue"); 3782 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_stalls", 3783 CTLFLAG_RD, &txq->r->stalls, 3784 "# of consumer stalls in the mp_ring for this queue"); 3785 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_restarts", 3786 CTLFLAG_RD, &txq->r->restarts, 3787 "# of consumer restarts in the mp_ring for this queue"); 3788 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_abdications", 3789 CTLFLAG_RD, &txq->r->abdications, 3790 "# of consumer abdications in the mp_ring for this queue"); 3791 3792 return (0); 3793 } 3794 3795 static int 3796 free_txq(struct vi_info *vi, struct sge_txq *txq) 3797 { 3798 int rc; 3799 struct adapter *sc = vi->pi->adapter; 3800 struct sge_eq *eq = &txq->eq; 3801 3802 rc = free_eq(sc, eq); 3803 if (rc) 3804 return (rc); 3805 3806 sglist_free(txq->gl); 3807 free(txq->sdesc, M_CXGBE); 3808 mp_ring_free(txq->r); 3809 3810 bzero(txq, sizeof(*txq)); 3811 return (0); 3812 } 3813 3814 static void 3815 oneseg_dma_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3816 { 3817 bus_addr_t *ba = arg; 3818 3819 KASSERT(nseg == 1, 3820 ("%s meant for single segment mappings only.", __func__)); 3821 3822 *ba = error ? 0 : segs->ds_addr; 3823 } 3824 3825 static inline void 3826 ring_fl_db(struct adapter *sc, struct sge_fl *fl) 3827 { 3828 uint32_t n, v; 3829 3830 n = IDXDIFF(fl->pidx / 8, fl->dbidx, fl->sidx); 3831 MPASS(n > 0); 3832 3833 wmb(); 3834 v = fl->dbval | V_PIDX(n); 3835 if (fl->udb) 3836 *fl->udb = htole32(v); 3837 else 3838 t4_write_reg(sc, sc->sge_kdoorbell_reg, v); 3839 IDXINCR(fl->dbidx, n, fl->sidx); 3840 } 3841 3842 /* 3843 * Fills up the freelist by allocating up to 'n' buffers. Buffers that are 3844 * recycled do not count towards this allocation budget. 3845 * 3846 * Returns non-zero to indicate that this freelist should be added to the list 3847 * of starving freelists. 3848 */ 3849 static int 3850 refill_fl(struct adapter *sc, struct sge_fl *fl, int n) 3851 { 3852 __be64 *d; 3853 struct fl_sdesc *sd; 3854 uintptr_t pa; 3855 caddr_t cl; 3856 struct cluster_layout *cll; 3857 struct sw_zone_info *swz; 3858 struct cluster_metadata *clm; 3859 uint16_t max_pidx; 3860 uint16_t hw_cidx = fl->hw_cidx; /* stable snapshot */ 3861 3862 FL_LOCK_ASSERT_OWNED(fl); 3863 3864 /* 3865 * We always stop at the beginning of the hardware descriptor that's just 3866 * before the one with the hw cidx. This is to avoid hw pidx = hw cidx, 3867 * which would mean an empty freelist to the chip. 3868 */ 3869 max_pidx = __predict_false(hw_cidx == 0) ? fl->sidx - 1 : hw_cidx - 1; 3870 if (fl->pidx == max_pidx * 8) 3871 return (0); 3872 3873 d = &fl->desc[fl->pidx]; 3874 sd = &fl->sdesc[fl->pidx]; 3875 cll = &fl->cll_def; /* default layout */ 3876 swz = &sc->sge.sw_zone_info[cll->zidx]; 3877 3878 while (n > 0) { 3879 3880 if (sd->cl != NULL) { 3881 3882 if (sd->nmbuf == 0) { 3883 /* 3884 * Fast recycle without involving any atomics on 3885 * the cluster's metadata (if the cluster has 3886 * metadata). This happens when all frames 3887 * received in the cluster were small enough to 3888 * fit within a single mbuf each. 3889 */ 3890 fl->cl_fast_recycled++; 3891 #ifdef INVARIANTS 3892 clm = cl_metadata(sc, fl, &sd->cll, sd->cl); 3893 if (clm != NULL) 3894 MPASS(clm->refcount == 1); 3895 #endif 3896 goto recycled_fast; 3897 } 3898 3899 /* 3900 * Cluster is guaranteed to have metadata. Clusters 3901 * without metadata always take the fast recycle path 3902 * when they're recycled. 3903 */ 3904 clm = cl_metadata(sc, fl, &sd->cll, sd->cl); 3905 MPASS(clm != NULL); 3906 3907 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) { 3908 fl->cl_recycled++; 3909 counter_u64_add(extfree_rels, 1); 3910 goto recycled; 3911 } 3912 sd->cl = NULL; /* gave up my reference */ 3913 } 3914 MPASS(sd->cl == NULL); 3915 alloc: 3916 cl = uma_zalloc(swz->zone, M_NOWAIT); 3917 if (__predict_false(cl == NULL)) { 3918 if (cll == &fl->cll_alt || fl->cll_alt.zidx == -1 || 3919 fl->cll_def.zidx == fl->cll_alt.zidx) 3920 break; 3921 3922 /* fall back to the safe zone */ 3923 cll = &fl->cll_alt; 3924 swz = &sc->sge.sw_zone_info[cll->zidx]; 3925 goto alloc; 3926 } 3927 fl->cl_allocated++; 3928 n--; 3929 3930 pa = pmap_kextract((vm_offset_t)cl); 3931 pa += cll->region1; 3932 sd->cl = cl; 3933 sd->cll = *cll; 3934 *d = htobe64(pa | cll->hwidx); 3935 clm = cl_metadata(sc, fl, cll, cl); 3936 if (clm != NULL) { 3937 recycled: 3938 #ifdef INVARIANTS 3939 clm->sd = sd; 3940 #endif 3941 clm->refcount = 1; 3942 } 3943 sd->nmbuf = 0; 3944 recycled_fast: 3945 d++; 3946 sd++; 3947 if (__predict_false(++fl->pidx % 8 == 0)) { 3948 uint16_t pidx = fl->pidx / 8; 3949 3950 if (__predict_false(pidx == fl->sidx)) { 3951 fl->pidx = 0; 3952 pidx = 0; 3953 sd = fl->sdesc; 3954 d = fl->desc; 3955 } 3956 if (pidx == max_pidx) 3957 break; 3958 3959 if (IDXDIFF(pidx, fl->dbidx, fl->sidx) >= 4) 3960 ring_fl_db(sc, fl); 3961 } 3962 } 3963 3964 if (fl->pidx / 8 != fl->dbidx) 3965 ring_fl_db(sc, fl); 3966 3967 return (FL_RUNNING_LOW(fl) && !(fl->flags & FL_STARVING)); 3968 } 3969 3970 /* 3971 * Attempt to refill all starving freelists. 3972 */ 3973 static void 3974 refill_sfl(void *arg) 3975 { 3976 struct adapter *sc = arg; 3977 struct sge_fl *fl, *fl_temp; 3978 3979 mtx_assert(&sc->sfl_lock, MA_OWNED); 3980 TAILQ_FOREACH_SAFE(fl, &sc->sfl, link, fl_temp) { 3981 FL_LOCK(fl); 3982 refill_fl(sc, fl, 64); 3983 if (FL_NOT_RUNNING_LOW(fl) || fl->flags & FL_DOOMED) { 3984 TAILQ_REMOVE(&sc->sfl, fl, link); 3985 fl->flags &= ~FL_STARVING; 3986 } 3987 FL_UNLOCK(fl); 3988 } 3989 3990 if (!TAILQ_EMPTY(&sc->sfl)) 3991 callout_schedule(&sc->sfl_callout, hz / 5); 3992 } 3993 3994 static int 3995 alloc_fl_sdesc(struct sge_fl *fl) 3996 { 3997 3998 fl->sdesc = malloc(fl->sidx * 8 * sizeof(struct fl_sdesc), M_CXGBE, 3999 M_ZERO | M_WAITOK); 4000 4001 return (0); 4002 } 4003 4004 static void 4005 free_fl_sdesc(struct adapter *sc, struct sge_fl *fl) 4006 { 4007 struct fl_sdesc *sd; 4008 struct cluster_metadata *clm; 4009 struct cluster_layout *cll; 4010 int i; 4011 4012 sd = fl->sdesc; 4013 for (i = 0; i < fl->sidx * 8; i++, sd++) { 4014 if (sd->cl == NULL) 4015 continue; 4016 4017 cll = &sd->cll; 4018 clm = cl_metadata(sc, fl, cll, sd->cl); 4019 if (sd->nmbuf == 0) 4020 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl); 4021 else if (clm && atomic_fetchadd_int(&clm->refcount, -1) == 1) { 4022 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl); 4023 counter_u64_add(extfree_rels, 1); 4024 } 4025 sd->cl = NULL; 4026 } 4027 4028 free(fl->sdesc, M_CXGBE); 4029 fl->sdesc = NULL; 4030 } 4031 4032 static inline void 4033 get_pkt_gl(struct mbuf *m, struct sglist *gl) 4034 { 4035 int rc; 4036 4037 M_ASSERTPKTHDR(m); 4038 4039 sglist_reset(gl); 4040 rc = sglist_append_mbuf(gl, m); 4041 if (__predict_false(rc != 0)) { 4042 panic("%s: mbuf %p (%d segs) was vetted earlier but now fails " 4043 "with %d.", __func__, m, mbuf_nsegs(m), rc); 4044 } 4045 4046 KASSERT(gl->sg_nseg == mbuf_nsegs(m), 4047 ("%s: nsegs changed for mbuf %p from %d to %d", __func__, m, 4048 mbuf_nsegs(m), gl->sg_nseg)); 4049 KASSERT(gl->sg_nseg > 0 && 4050 gl->sg_nseg <= (needs_tso(m) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS), 4051 ("%s: %d segments, should have been 1 <= nsegs <= %d", __func__, 4052 gl->sg_nseg, needs_tso(m) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS)); 4053 } 4054 4055 /* 4056 * len16 for a txpkt WR with a GL. Includes the firmware work request header. 4057 */ 4058 static inline u_int 4059 txpkt_len16(u_int nsegs, u_int tso) 4060 { 4061 u_int n; 4062 4063 MPASS(nsegs > 0); 4064 4065 nsegs--; /* first segment is part of ulptx_sgl */ 4066 n = sizeof(struct fw_eth_tx_pkt_wr) + sizeof(struct cpl_tx_pkt_core) + 4067 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 4068 if (tso) 4069 n += sizeof(struct cpl_tx_pkt_lso_core); 4070 4071 return (howmany(n, 16)); 4072 } 4073 4074 /* 4075 * len16 for a txpkt_vm WR with a GL. Includes the firmware work 4076 * request header. 4077 */ 4078 static inline u_int 4079 txpkt_vm_len16(u_int nsegs, u_int tso) 4080 { 4081 u_int n; 4082 4083 MPASS(nsegs > 0); 4084 4085 nsegs--; /* first segment is part of ulptx_sgl */ 4086 n = sizeof(struct fw_eth_tx_pkt_vm_wr) + 4087 sizeof(struct cpl_tx_pkt_core) + 4088 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 4089 if (tso) 4090 n += sizeof(struct cpl_tx_pkt_lso_core); 4091 4092 return (howmany(n, 16)); 4093 } 4094 4095 /* 4096 * len16 for a txpkts type 0 WR with a GL. Does not include the firmware work 4097 * request header. 4098 */ 4099 static inline u_int 4100 txpkts0_len16(u_int nsegs) 4101 { 4102 u_int n; 4103 4104 MPASS(nsegs > 0); 4105 4106 nsegs--; /* first segment is part of ulptx_sgl */ 4107 n = sizeof(struct ulp_txpkt) + sizeof(struct ulptx_idata) + 4108 sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl) + 4109 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 4110 4111 return (howmany(n, 16)); 4112 } 4113 4114 /* 4115 * len16 for a txpkts type 1 WR with a GL. Does not include the firmware work 4116 * request header. 4117 */ 4118 static inline u_int 4119 txpkts1_len16(void) 4120 { 4121 u_int n; 4122 4123 n = sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl); 4124 4125 return (howmany(n, 16)); 4126 } 4127 4128 static inline u_int 4129 imm_payload(u_int ndesc) 4130 { 4131 u_int n; 4132 4133 n = ndesc * EQ_ESIZE - sizeof(struct fw_eth_tx_pkt_wr) - 4134 sizeof(struct cpl_tx_pkt_core); 4135 4136 return (n); 4137 } 4138 4139 /* 4140 * Write a VM txpkt WR for this packet to the hardware descriptors, update the 4141 * software descriptor, and advance the pidx. It is guaranteed that enough 4142 * descriptors are available. 4143 * 4144 * The return value is the # of hardware descriptors used. 4145 */ 4146 static u_int 4147 write_txpkt_vm_wr(struct adapter *sc, struct sge_txq *txq, 4148 struct fw_eth_tx_pkt_vm_wr *wr, struct mbuf *m0, u_int available) 4149 { 4150 struct sge_eq *eq = &txq->eq; 4151 struct tx_sdesc *txsd; 4152 struct cpl_tx_pkt_core *cpl; 4153 uint32_t ctrl; /* used in many unrelated places */ 4154 uint64_t ctrl1; 4155 int csum_type, len16, ndesc, pktlen, nsegs; 4156 caddr_t dst; 4157 4158 TXQ_LOCK_ASSERT_OWNED(txq); 4159 M_ASSERTPKTHDR(m0); 4160 MPASS(available > 0 && available < eq->sidx); 4161 4162 len16 = mbuf_len16(m0); 4163 nsegs = mbuf_nsegs(m0); 4164 pktlen = m0->m_pkthdr.len; 4165 ctrl = sizeof(struct cpl_tx_pkt_core); 4166 if (needs_tso(m0)) 4167 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 4168 ndesc = howmany(len16, EQ_ESIZE / 16); 4169 MPASS(ndesc <= available); 4170 4171 /* Firmware work request header */ 4172 MPASS(wr == (void *)&eq->desc[eq->pidx]); 4173 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_VM_WR) | 4174 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl)); 4175 4176 ctrl = V_FW_WR_LEN16(len16); 4177 wr->equiq_to_len16 = htobe32(ctrl); 4178 wr->r3[0] = 0; 4179 wr->r3[1] = 0; 4180 4181 /* 4182 * Copy over ethmacdst, ethmacsrc, ethtype, and vlantci. 4183 * vlantci is ignored unless the ethtype is 0x8100, so it's 4184 * simpler to always copy it rather than making it 4185 * conditional. Also, it seems that we do not have to set 4186 * vlantci or fake the ethtype when doing VLAN tag insertion. 4187 */ 4188 m_copydata(m0, 0, sizeof(struct ether_header) + 2, wr->ethmacdst); 4189 4190 csum_type = -1; 4191 if (needs_tso(m0)) { 4192 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1); 4193 4194 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 4195 m0->m_pkthdr.l4hlen > 0, 4196 ("%s: mbuf %p needs TSO but missing header lengths", 4197 __func__, m0)); 4198 4199 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE | 4200 F_LSO_LAST_SLICE | V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) 4201 | V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2); 4202 if (m0->m_pkthdr.l2hlen == sizeof(struct ether_vlan_header)) 4203 ctrl |= V_LSO_ETHHDR_LEN(1); 4204 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 4205 ctrl |= F_LSO_IPV6; 4206 4207 lso->lso_ctrl = htobe32(ctrl); 4208 lso->ipid_ofst = htobe16(0); 4209 lso->mss = htobe16(m0->m_pkthdr.tso_segsz); 4210 lso->seqno_offset = htobe32(0); 4211 lso->len = htobe32(pktlen); 4212 4213 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 4214 csum_type = TX_CSUM_TCPIP6; 4215 else 4216 csum_type = TX_CSUM_TCPIP; 4217 4218 cpl = (void *)(lso + 1); 4219 4220 txq->tso_wrs++; 4221 } else { 4222 if (m0->m_pkthdr.csum_flags & CSUM_IP_TCP) 4223 csum_type = TX_CSUM_TCPIP; 4224 else if (m0->m_pkthdr.csum_flags & CSUM_IP_UDP) 4225 csum_type = TX_CSUM_UDPIP; 4226 else if (m0->m_pkthdr.csum_flags & CSUM_IP6_TCP) 4227 csum_type = TX_CSUM_TCPIP6; 4228 else if (m0->m_pkthdr.csum_flags & CSUM_IP6_UDP) 4229 csum_type = TX_CSUM_UDPIP6; 4230 #if defined(INET) 4231 else if (m0->m_pkthdr.csum_flags & CSUM_IP) { 4232 /* 4233 * XXX: The firmware appears to stomp on the 4234 * fragment/flags field of the IP header when 4235 * using TX_CSUM_IP. Fall back to doing 4236 * software checksums. 4237 */ 4238 u_short *sump; 4239 struct mbuf *m; 4240 int offset; 4241 4242 m = m0; 4243 offset = 0; 4244 sump = m_advance(&m, &offset, m0->m_pkthdr.l2hlen + 4245 offsetof(struct ip, ip_sum)); 4246 *sump = in_cksum_skip(m0, m0->m_pkthdr.l2hlen + 4247 m0->m_pkthdr.l3hlen, m0->m_pkthdr.l2hlen); 4248 m0->m_pkthdr.csum_flags &= ~CSUM_IP; 4249 } 4250 #endif 4251 4252 cpl = (void *)(wr + 1); 4253 } 4254 4255 /* Checksum offload */ 4256 ctrl1 = 0; 4257 if (needs_l3_csum(m0) == 0) 4258 ctrl1 |= F_TXPKT_IPCSUM_DIS; 4259 if (csum_type >= 0) { 4260 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0, 4261 ("%s: mbuf %p needs checksum offload but missing header lengths", 4262 __func__, m0)); 4263 4264 if (chip_id(sc) <= CHELSIO_T5) { 4265 ctrl1 |= V_TXPKT_ETHHDR_LEN(m0->m_pkthdr.l2hlen - 4266 ETHER_HDR_LEN); 4267 } else { 4268 ctrl1 |= V_T6_TXPKT_ETHHDR_LEN(m0->m_pkthdr.l2hlen - 4269 ETHER_HDR_LEN); 4270 } 4271 ctrl1 |= V_TXPKT_IPHDR_LEN(m0->m_pkthdr.l3hlen); 4272 ctrl1 |= V_TXPKT_CSUM_TYPE(csum_type); 4273 } else 4274 ctrl1 |= F_TXPKT_L4CSUM_DIS; 4275 if (m0->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | 4276 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO)) 4277 txq->txcsum++; /* some hardware assistance provided */ 4278 4279 /* VLAN tag insertion */ 4280 if (needs_vlan_insertion(m0)) { 4281 ctrl1 |= F_TXPKT_VLAN_VLD | 4282 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 4283 txq->vlan_insertion++; 4284 } 4285 4286 /* CPL header */ 4287 cpl->ctrl0 = txq->cpl_ctrl0; 4288 cpl->pack = 0; 4289 cpl->len = htobe16(pktlen); 4290 cpl->ctrl1 = htobe64(ctrl1); 4291 4292 /* SGL */ 4293 dst = (void *)(cpl + 1); 4294 4295 /* 4296 * A packet using TSO will use up an entire descriptor for the 4297 * firmware work request header, LSO CPL, and TX_PKT_XT CPL. 4298 * If this descriptor is the last descriptor in the ring, wrap 4299 * around to the front of the ring explicitly for the start of 4300 * the sgl. 4301 */ 4302 if (dst == (void *)&eq->desc[eq->sidx]) { 4303 dst = (void *)&eq->desc[0]; 4304 write_gl_to_txd(txq, m0, &dst, 0); 4305 } else 4306 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx); 4307 txq->sgl_wrs++; 4308 4309 txq->txpkt_wrs++; 4310 4311 txsd = &txq->sdesc[eq->pidx]; 4312 txsd->m = m0; 4313 txsd->desc_used = ndesc; 4314 4315 return (ndesc); 4316 } 4317 4318 /* 4319 * Write a txpkt WR for this packet to the hardware descriptors, update the 4320 * software descriptor, and advance the pidx. It is guaranteed that enough 4321 * descriptors are available. 4322 * 4323 * The return value is the # of hardware descriptors used. 4324 */ 4325 static u_int 4326 write_txpkt_wr(struct sge_txq *txq, struct fw_eth_tx_pkt_wr *wr, 4327 struct mbuf *m0, u_int available) 4328 { 4329 struct sge_eq *eq = &txq->eq; 4330 struct tx_sdesc *txsd; 4331 struct cpl_tx_pkt_core *cpl; 4332 uint32_t ctrl; /* used in many unrelated places */ 4333 uint64_t ctrl1; 4334 int len16, ndesc, pktlen, nsegs; 4335 caddr_t dst; 4336 4337 TXQ_LOCK_ASSERT_OWNED(txq); 4338 M_ASSERTPKTHDR(m0); 4339 MPASS(available > 0 && available < eq->sidx); 4340 4341 len16 = mbuf_len16(m0); 4342 nsegs = mbuf_nsegs(m0); 4343 pktlen = m0->m_pkthdr.len; 4344 ctrl = sizeof(struct cpl_tx_pkt_core); 4345 if (needs_tso(m0)) 4346 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 4347 else if (pktlen <= imm_payload(2) && available >= 2) { 4348 /* Immediate data. Recalculate len16 and set nsegs to 0. */ 4349 ctrl += pktlen; 4350 len16 = howmany(sizeof(struct fw_eth_tx_pkt_wr) + 4351 sizeof(struct cpl_tx_pkt_core) + pktlen, 16); 4352 nsegs = 0; 4353 } 4354 ndesc = howmany(len16, EQ_ESIZE / 16); 4355 MPASS(ndesc <= available); 4356 4357 /* Firmware work request header */ 4358 MPASS(wr == (void *)&eq->desc[eq->pidx]); 4359 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_WR) | 4360 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl)); 4361 4362 ctrl = V_FW_WR_LEN16(len16); 4363 wr->equiq_to_len16 = htobe32(ctrl); 4364 wr->r3 = 0; 4365 4366 if (needs_tso(m0)) { 4367 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1); 4368 4369 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 4370 m0->m_pkthdr.l4hlen > 0, 4371 ("%s: mbuf %p needs TSO but missing header lengths", 4372 __func__, m0)); 4373 4374 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE | 4375 F_LSO_LAST_SLICE | V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) 4376 | V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2); 4377 if (m0->m_pkthdr.l2hlen == sizeof(struct ether_vlan_header)) 4378 ctrl |= V_LSO_ETHHDR_LEN(1); 4379 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 4380 ctrl |= F_LSO_IPV6; 4381 4382 lso->lso_ctrl = htobe32(ctrl); 4383 lso->ipid_ofst = htobe16(0); 4384 lso->mss = htobe16(m0->m_pkthdr.tso_segsz); 4385 lso->seqno_offset = htobe32(0); 4386 lso->len = htobe32(pktlen); 4387 4388 cpl = (void *)(lso + 1); 4389 4390 txq->tso_wrs++; 4391 } else 4392 cpl = (void *)(wr + 1); 4393 4394 /* Checksum offload */ 4395 ctrl1 = 0; 4396 if (needs_l3_csum(m0) == 0) 4397 ctrl1 |= F_TXPKT_IPCSUM_DIS; 4398 if (needs_l4_csum(m0) == 0) 4399 ctrl1 |= F_TXPKT_L4CSUM_DIS; 4400 if (m0->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | 4401 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO)) 4402 txq->txcsum++; /* some hardware assistance provided */ 4403 4404 /* VLAN tag insertion */ 4405 if (needs_vlan_insertion(m0)) { 4406 ctrl1 |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 4407 txq->vlan_insertion++; 4408 } 4409 4410 /* CPL header */ 4411 cpl->ctrl0 = txq->cpl_ctrl0; 4412 cpl->pack = 0; 4413 cpl->len = htobe16(pktlen); 4414 cpl->ctrl1 = htobe64(ctrl1); 4415 4416 /* SGL */ 4417 dst = (void *)(cpl + 1); 4418 if (nsegs > 0) { 4419 4420 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx); 4421 txq->sgl_wrs++; 4422 } else { 4423 struct mbuf *m; 4424 4425 for (m = m0; m != NULL; m = m->m_next) { 4426 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len); 4427 #ifdef INVARIANTS 4428 pktlen -= m->m_len; 4429 #endif 4430 } 4431 #ifdef INVARIANTS 4432 KASSERT(pktlen == 0, ("%s: %d bytes left.", __func__, pktlen)); 4433 #endif 4434 txq->imm_wrs++; 4435 } 4436 4437 txq->txpkt_wrs++; 4438 4439 txsd = &txq->sdesc[eq->pidx]; 4440 txsd->m = m0; 4441 txsd->desc_used = ndesc; 4442 4443 return (ndesc); 4444 } 4445 4446 static int 4447 try_txpkts(struct mbuf *m, struct mbuf *n, struct txpkts *txp, u_int available) 4448 { 4449 u_int needed, nsegs1, nsegs2, l1, l2; 4450 4451 if (cannot_use_txpkts(m) || cannot_use_txpkts(n)) 4452 return (1); 4453 4454 nsegs1 = mbuf_nsegs(m); 4455 nsegs2 = mbuf_nsegs(n); 4456 if (nsegs1 + nsegs2 == 2) { 4457 txp->wr_type = 1; 4458 l1 = l2 = txpkts1_len16(); 4459 } else { 4460 txp->wr_type = 0; 4461 l1 = txpkts0_len16(nsegs1); 4462 l2 = txpkts0_len16(nsegs2); 4463 } 4464 txp->len16 = howmany(sizeof(struct fw_eth_tx_pkts_wr), 16) + l1 + l2; 4465 needed = howmany(txp->len16, EQ_ESIZE / 16); 4466 if (needed > SGE_MAX_WR_NDESC || needed > available) 4467 return (1); 4468 4469 txp->plen = m->m_pkthdr.len + n->m_pkthdr.len; 4470 if (txp->plen > 65535) 4471 return (1); 4472 4473 txp->npkt = 2; 4474 set_mbuf_len16(m, l1); 4475 set_mbuf_len16(n, l2); 4476 4477 return (0); 4478 } 4479 4480 static int 4481 add_to_txpkts(struct mbuf *m, struct txpkts *txp, u_int available) 4482 { 4483 u_int plen, len16, needed, nsegs; 4484 4485 MPASS(txp->wr_type == 0 || txp->wr_type == 1); 4486 4487 nsegs = mbuf_nsegs(m); 4488 if (needs_tso(m) || (txp->wr_type == 1 && nsegs != 1)) 4489 return (1); 4490 4491 plen = txp->plen + m->m_pkthdr.len; 4492 if (plen > 65535) 4493 return (1); 4494 4495 if (txp->wr_type == 0) 4496 len16 = txpkts0_len16(nsegs); 4497 else 4498 len16 = txpkts1_len16(); 4499 needed = howmany(txp->len16 + len16, EQ_ESIZE / 16); 4500 if (needed > SGE_MAX_WR_NDESC || needed > available) 4501 return (1); 4502 4503 txp->npkt++; 4504 txp->plen = plen; 4505 txp->len16 += len16; 4506 set_mbuf_len16(m, len16); 4507 4508 return (0); 4509 } 4510 4511 /* 4512 * Write a txpkts WR for the packets in txp to the hardware descriptors, update 4513 * the software descriptor, and advance the pidx. It is guaranteed that enough 4514 * descriptors are available. 4515 * 4516 * The return value is the # of hardware descriptors used. 4517 */ 4518 static u_int 4519 write_txpkts_wr(struct sge_txq *txq, struct fw_eth_tx_pkts_wr *wr, 4520 struct mbuf *m0, const struct txpkts *txp, u_int available) 4521 { 4522 struct sge_eq *eq = &txq->eq; 4523 struct tx_sdesc *txsd; 4524 struct cpl_tx_pkt_core *cpl; 4525 uint32_t ctrl; 4526 uint64_t ctrl1; 4527 int ndesc, checkwrap; 4528 struct mbuf *m; 4529 void *flitp; 4530 4531 TXQ_LOCK_ASSERT_OWNED(txq); 4532 MPASS(txp->npkt > 0); 4533 MPASS(txp->plen < 65536); 4534 MPASS(m0 != NULL); 4535 MPASS(m0->m_nextpkt != NULL); 4536 MPASS(txp->len16 <= howmany(SGE_MAX_WR_LEN, 16)); 4537 MPASS(available > 0 && available < eq->sidx); 4538 4539 ndesc = howmany(txp->len16, EQ_ESIZE / 16); 4540 MPASS(ndesc <= available); 4541 4542 MPASS(wr == (void *)&eq->desc[eq->pidx]); 4543 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR)); 4544 ctrl = V_FW_WR_LEN16(txp->len16); 4545 wr->equiq_to_len16 = htobe32(ctrl); 4546 wr->plen = htobe16(txp->plen); 4547 wr->npkt = txp->npkt; 4548 wr->r3 = 0; 4549 wr->type = txp->wr_type; 4550 flitp = wr + 1; 4551 4552 /* 4553 * At this point we are 16B into a hardware descriptor. If checkwrap is 4554 * set then we know the WR is going to wrap around somewhere. We'll 4555 * check for that at appropriate points. 4556 */ 4557 checkwrap = eq->sidx - ndesc < eq->pidx; 4558 for (m = m0; m != NULL; m = m->m_nextpkt) { 4559 if (txp->wr_type == 0) { 4560 struct ulp_txpkt *ulpmc; 4561 struct ulptx_idata *ulpsc; 4562 4563 /* ULP master command */ 4564 ulpmc = flitp; 4565 ulpmc->cmd_dest = htobe32(V_ULPTX_CMD(ULP_TX_PKT) | 4566 V_ULP_TXPKT_DEST(0) | V_ULP_TXPKT_FID(eq->iqid)); 4567 ulpmc->len = htobe32(mbuf_len16(m)); 4568 4569 /* ULP subcommand */ 4570 ulpsc = (void *)(ulpmc + 1); 4571 ulpsc->cmd_more = htobe32(V_ULPTX_CMD(ULP_TX_SC_IMM) | 4572 F_ULP_TX_SC_MORE); 4573 ulpsc->len = htobe32(sizeof(struct cpl_tx_pkt_core)); 4574 4575 cpl = (void *)(ulpsc + 1); 4576 if (checkwrap && 4577 (uintptr_t)cpl == (uintptr_t)&eq->desc[eq->sidx]) 4578 cpl = (void *)&eq->desc[0]; 4579 txq->txpkts0_pkts += txp->npkt; 4580 txq->txpkts0_wrs++; 4581 } else { 4582 cpl = flitp; 4583 txq->txpkts1_pkts += txp->npkt; 4584 txq->txpkts1_wrs++; 4585 } 4586 4587 /* Checksum offload */ 4588 ctrl1 = 0; 4589 if (needs_l3_csum(m) == 0) 4590 ctrl1 |= F_TXPKT_IPCSUM_DIS; 4591 if (needs_l4_csum(m) == 0) 4592 ctrl1 |= F_TXPKT_L4CSUM_DIS; 4593 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | 4594 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO)) 4595 txq->txcsum++; /* some hardware assistance provided */ 4596 4597 /* VLAN tag insertion */ 4598 if (needs_vlan_insertion(m)) { 4599 ctrl1 |= F_TXPKT_VLAN_VLD | 4600 V_TXPKT_VLAN(m->m_pkthdr.ether_vtag); 4601 txq->vlan_insertion++; 4602 } 4603 4604 /* CPL header */ 4605 cpl->ctrl0 = txq->cpl_ctrl0; 4606 cpl->pack = 0; 4607 cpl->len = htobe16(m->m_pkthdr.len); 4608 cpl->ctrl1 = htobe64(ctrl1); 4609 4610 flitp = cpl + 1; 4611 if (checkwrap && 4612 (uintptr_t)flitp == (uintptr_t)&eq->desc[eq->sidx]) 4613 flitp = (void *)&eq->desc[0]; 4614 4615 write_gl_to_txd(txq, m, (caddr_t *)(&flitp), checkwrap); 4616 4617 } 4618 4619 txsd = &txq->sdesc[eq->pidx]; 4620 txsd->m = m0; 4621 txsd->desc_used = ndesc; 4622 4623 return (ndesc); 4624 } 4625 4626 /* 4627 * If the SGL ends on an address that is not 16 byte aligned, this function will 4628 * add a 0 filled flit at the end. 4629 */ 4630 static void 4631 write_gl_to_txd(struct sge_txq *txq, struct mbuf *m, caddr_t *to, int checkwrap) 4632 { 4633 struct sge_eq *eq = &txq->eq; 4634 struct sglist *gl = txq->gl; 4635 struct sglist_seg *seg; 4636 __be64 *flitp, *wrap; 4637 struct ulptx_sgl *usgl; 4638 int i, nflits, nsegs; 4639 4640 KASSERT(((uintptr_t)(*to) & 0xf) == 0, 4641 ("%s: SGL must start at a 16 byte boundary: %p", __func__, *to)); 4642 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]); 4643 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]); 4644 4645 get_pkt_gl(m, gl); 4646 nsegs = gl->sg_nseg; 4647 MPASS(nsegs > 0); 4648 4649 nflits = (3 * (nsegs - 1)) / 2 + ((nsegs - 1) & 1) + 2; 4650 flitp = (__be64 *)(*to); 4651 wrap = (__be64 *)(&eq->desc[eq->sidx]); 4652 seg = &gl->sg_segs[0]; 4653 usgl = (void *)flitp; 4654 4655 /* 4656 * We start at a 16 byte boundary somewhere inside the tx descriptor 4657 * ring, so we're at least 16 bytes away from the status page. There is 4658 * no chance of a wrap around in the middle of usgl (which is 16 bytes). 4659 */ 4660 4661 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 4662 V_ULPTX_NSGE(nsegs)); 4663 usgl->len0 = htobe32(seg->ss_len); 4664 usgl->addr0 = htobe64(seg->ss_paddr); 4665 seg++; 4666 4667 if (checkwrap == 0 || (uintptr_t)(flitp + nflits) <= (uintptr_t)wrap) { 4668 4669 /* Won't wrap around at all */ 4670 4671 for (i = 0; i < nsegs - 1; i++, seg++) { 4672 usgl->sge[i / 2].len[i & 1] = htobe32(seg->ss_len); 4673 usgl->sge[i / 2].addr[i & 1] = htobe64(seg->ss_paddr); 4674 } 4675 if (i & 1) 4676 usgl->sge[i / 2].len[1] = htobe32(0); 4677 flitp += nflits; 4678 } else { 4679 4680 /* Will wrap somewhere in the rest of the SGL */ 4681 4682 /* 2 flits already written, write the rest flit by flit */ 4683 flitp = (void *)(usgl + 1); 4684 for (i = 0; i < nflits - 2; i++) { 4685 if (flitp == wrap) 4686 flitp = (void *)eq->desc; 4687 *flitp++ = get_flit(seg, nsegs - 1, i); 4688 } 4689 } 4690 4691 if (nflits & 1) { 4692 MPASS(((uintptr_t)flitp) & 0xf); 4693 *flitp++ = 0; 4694 } 4695 4696 MPASS((((uintptr_t)flitp) & 0xf) == 0); 4697 if (__predict_false(flitp == wrap)) 4698 *to = (void *)eq->desc; 4699 else 4700 *to = (void *)flitp; 4701 } 4702 4703 static inline void 4704 copy_to_txd(struct sge_eq *eq, caddr_t from, caddr_t *to, int len) 4705 { 4706 4707 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]); 4708 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]); 4709 4710 if (__predict_true((uintptr_t)(*to) + len <= 4711 (uintptr_t)&eq->desc[eq->sidx])) { 4712 bcopy(from, *to, len); 4713 (*to) += len; 4714 } else { 4715 int portion = (uintptr_t)&eq->desc[eq->sidx] - (uintptr_t)(*to); 4716 4717 bcopy(from, *to, portion); 4718 from += portion; 4719 portion = len - portion; /* remaining */ 4720 bcopy(from, (void *)eq->desc, portion); 4721 (*to) = (caddr_t)eq->desc + portion; 4722 } 4723 } 4724 4725 static inline void 4726 ring_eq_db(struct adapter *sc, struct sge_eq *eq, u_int n) 4727 { 4728 u_int db; 4729 4730 MPASS(n > 0); 4731 4732 db = eq->doorbells; 4733 if (n > 1) 4734 clrbit(&db, DOORBELL_WCWR); 4735 wmb(); 4736 4737 switch (ffs(db) - 1) { 4738 case DOORBELL_UDB: 4739 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n)); 4740 break; 4741 4742 case DOORBELL_WCWR: { 4743 volatile uint64_t *dst, *src; 4744 int i; 4745 4746 /* 4747 * Queues whose 128B doorbell segment fits in the page do not 4748 * use relative qid (udb_qid is always 0). Only queues with 4749 * doorbell segments can do WCWR. 4750 */ 4751 KASSERT(eq->udb_qid == 0 && n == 1, 4752 ("%s: inappropriate doorbell (0x%x, %d, %d) for eq %p", 4753 __func__, eq->doorbells, n, eq->dbidx, eq)); 4754 4755 dst = (volatile void *)((uintptr_t)eq->udb + UDBS_WR_OFFSET - 4756 UDBS_DB_OFFSET); 4757 i = eq->dbidx; 4758 src = (void *)&eq->desc[i]; 4759 while (src != (void *)&eq->desc[i + 1]) 4760 *dst++ = *src++; 4761 wmb(); 4762 break; 4763 } 4764 4765 case DOORBELL_UDBWC: 4766 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n)); 4767 wmb(); 4768 break; 4769 4770 case DOORBELL_KDB: 4771 t4_write_reg(sc, sc->sge_kdoorbell_reg, 4772 V_QID(eq->cntxt_id) | V_PIDX(n)); 4773 break; 4774 } 4775 4776 IDXINCR(eq->dbidx, n, eq->sidx); 4777 } 4778 4779 static inline u_int 4780 reclaimable_tx_desc(struct sge_eq *eq) 4781 { 4782 uint16_t hw_cidx; 4783 4784 hw_cidx = read_hw_cidx(eq); 4785 return (IDXDIFF(hw_cidx, eq->cidx, eq->sidx)); 4786 } 4787 4788 static inline u_int 4789 total_available_tx_desc(struct sge_eq *eq) 4790 { 4791 uint16_t hw_cidx, pidx; 4792 4793 hw_cidx = read_hw_cidx(eq); 4794 pidx = eq->pidx; 4795 4796 if (pidx == hw_cidx) 4797 return (eq->sidx - 1); 4798 else 4799 return (IDXDIFF(hw_cidx, pidx, eq->sidx) - 1); 4800 } 4801 4802 static inline uint16_t 4803 read_hw_cidx(struct sge_eq *eq) 4804 { 4805 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx]; 4806 uint16_t cidx = spg->cidx; /* stable snapshot */ 4807 4808 return (be16toh(cidx)); 4809 } 4810 4811 /* 4812 * Reclaim 'n' descriptors approximately. 4813 */ 4814 static u_int 4815 reclaim_tx_descs(struct sge_txq *txq, u_int n) 4816 { 4817 struct tx_sdesc *txsd; 4818 struct sge_eq *eq = &txq->eq; 4819 u_int can_reclaim, reclaimed; 4820 4821 TXQ_LOCK_ASSERT_OWNED(txq); 4822 MPASS(n > 0); 4823 4824 reclaimed = 0; 4825 can_reclaim = reclaimable_tx_desc(eq); 4826 while (can_reclaim && reclaimed < n) { 4827 int ndesc; 4828 struct mbuf *m, *nextpkt; 4829 4830 txsd = &txq->sdesc[eq->cidx]; 4831 ndesc = txsd->desc_used; 4832 4833 /* Firmware doesn't return "partial" credits. */ 4834 KASSERT(can_reclaim >= ndesc, 4835 ("%s: unexpected number of credits: %d, %d", 4836 __func__, can_reclaim, ndesc)); 4837 4838 for (m = txsd->m; m != NULL; m = nextpkt) { 4839 nextpkt = m->m_nextpkt; 4840 m->m_nextpkt = NULL; 4841 m_freem(m); 4842 } 4843 reclaimed += ndesc; 4844 can_reclaim -= ndesc; 4845 IDXINCR(eq->cidx, ndesc, eq->sidx); 4846 } 4847 4848 return (reclaimed); 4849 } 4850 4851 static void 4852 tx_reclaim(void *arg, int n) 4853 { 4854 struct sge_txq *txq = arg; 4855 struct sge_eq *eq = &txq->eq; 4856 4857 do { 4858 if (TXQ_TRYLOCK(txq) == 0) 4859 break; 4860 n = reclaim_tx_descs(txq, 32); 4861 if (eq->cidx == eq->pidx) 4862 eq->equeqidx = eq->pidx; 4863 TXQ_UNLOCK(txq); 4864 } while (n > 0); 4865 } 4866 4867 static __be64 4868 get_flit(struct sglist_seg *segs, int nsegs, int idx) 4869 { 4870 int i = (idx / 3) * 2; 4871 4872 switch (idx % 3) { 4873 case 0: { 4874 __be64 rc; 4875 4876 rc = htobe32(segs[i].ss_len); 4877 if (i + 1 < nsegs) 4878 rc |= (uint64_t)htobe32(segs[i + 1].ss_len) << 32; 4879 4880 return (rc); 4881 } 4882 case 1: 4883 return (htobe64(segs[i].ss_paddr)); 4884 case 2: 4885 return (htobe64(segs[i + 1].ss_paddr)); 4886 } 4887 4888 return (0); 4889 } 4890 4891 static void 4892 find_best_refill_source(struct adapter *sc, struct sge_fl *fl, int maxp) 4893 { 4894 int8_t zidx, hwidx, idx; 4895 uint16_t region1, region3; 4896 int spare, spare_needed, n; 4897 struct sw_zone_info *swz; 4898 struct hw_buf_info *hwb, *hwb_list = &sc->sge.hw_buf_info[0]; 4899 4900 /* 4901 * Buffer Packing: Look for PAGE_SIZE or larger zone which has a bufsize 4902 * large enough for the max payload and cluster metadata. Otherwise 4903 * settle for the largest bufsize that leaves enough room in the cluster 4904 * for metadata. 4905 * 4906 * Without buffer packing: Look for the smallest zone which has a 4907 * bufsize large enough for the max payload. Settle for the largest 4908 * bufsize available if there's nothing big enough for max payload. 4909 */ 4910 spare_needed = fl->flags & FL_BUF_PACKING ? CL_METADATA_SIZE : 0; 4911 swz = &sc->sge.sw_zone_info[0]; 4912 hwidx = -1; 4913 for (zidx = 0; zidx < SW_ZONE_SIZES; zidx++, swz++) { 4914 if (swz->size > largest_rx_cluster) { 4915 if (__predict_true(hwidx != -1)) 4916 break; 4917 4918 /* 4919 * This is a misconfiguration. largest_rx_cluster is 4920 * preventing us from finding a refill source. See 4921 * dev.t5nex.<n>.buffer_sizes to figure out why. 4922 */ 4923 device_printf(sc->dev, "largest_rx_cluster=%u leaves no" 4924 " refill source for fl %p (dma %u). Ignored.\n", 4925 largest_rx_cluster, fl, maxp); 4926 } 4927 for (idx = swz->head_hwidx; idx != -1; idx = hwb->next) { 4928 hwb = &hwb_list[idx]; 4929 spare = swz->size - hwb->size; 4930 if (spare < spare_needed) 4931 continue; 4932 4933 hwidx = idx; /* best option so far */ 4934 if (hwb->size >= maxp) { 4935 4936 if ((fl->flags & FL_BUF_PACKING) == 0) 4937 goto done; /* stop looking (not packing) */ 4938 4939 if (swz->size >= safest_rx_cluster) 4940 goto done; /* stop looking (packing) */ 4941 } 4942 break; /* keep looking, next zone */ 4943 } 4944 } 4945 done: 4946 /* A usable hwidx has been located. */ 4947 MPASS(hwidx != -1); 4948 hwb = &hwb_list[hwidx]; 4949 zidx = hwb->zidx; 4950 swz = &sc->sge.sw_zone_info[zidx]; 4951 region1 = 0; 4952 region3 = swz->size - hwb->size; 4953 4954 /* 4955 * Stay within this zone and see if there is a better match when mbuf 4956 * inlining is allowed. Remember that the hwidx's are sorted in 4957 * decreasing order of size (so in increasing order of spare area). 4958 */ 4959 for (idx = hwidx; idx != -1; idx = hwb->next) { 4960 hwb = &hwb_list[idx]; 4961 spare = swz->size - hwb->size; 4962 4963 if (allow_mbufs_in_cluster == 0 || hwb->size < maxp) 4964 break; 4965 4966 /* 4967 * Do not inline mbufs if doing so would violate the pad/pack 4968 * boundary alignment requirement. 4969 */ 4970 if (fl_pad && (MSIZE % sc->params.sge.pad_boundary) != 0) 4971 continue; 4972 if (fl->flags & FL_BUF_PACKING && 4973 (MSIZE % sc->params.sge.pack_boundary) != 0) 4974 continue; 4975 4976 if (spare < CL_METADATA_SIZE + MSIZE) 4977 continue; 4978 n = (spare - CL_METADATA_SIZE) / MSIZE; 4979 if (n > howmany(hwb->size, maxp)) 4980 break; 4981 4982 hwidx = idx; 4983 if (fl->flags & FL_BUF_PACKING) { 4984 region1 = n * MSIZE; 4985 region3 = spare - region1; 4986 } else { 4987 region1 = MSIZE; 4988 region3 = spare - region1; 4989 break; 4990 } 4991 } 4992 4993 KASSERT(zidx >= 0 && zidx < SW_ZONE_SIZES, 4994 ("%s: bad zone %d for fl %p, maxp %d", __func__, zidx, fl, maxp)); 4995 KASSERT(hwidx >= 0 && hwidx <= SGE_FLBUF_SIZES, 4996 ("%s: bad hwidx %d for fl %p, maxp %d", __func__, hwidx, fl, maxp)); 4997 KASSERT(region1 + sc->sge.hw_buf_info[hwidx].size + region3 == 4998 sc->sge.sw_zone_info[zidx].size, 4999 ("%s: bad buffer layout for fl %p, maxp %d. " 5000 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp, 5001 sc->sge.sw_zone_info[zidx].size, region1, 5002 sc->sge.hw_buf_info[hwidx].size, region3)); 5003 if (fl->flags & FL_BUF_PACKING || region1 > 0) { 5004 KASSERT(region3 >= CL_METADATA_SIZE, 5005 ("%s: no room for metadata. fl %p, maxp %d; " 5006 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp, 5007 sc->sge.sw_zone_info[zidx].size, region1, 5008 sc->sge.hw_buf_info[hwidx].size, region3)); 5009 KASSERT(region1 % MSIZE == 0, 5010 ("%s: bad mbuf region for fl %p, maxp %d. " 5011 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp, 5012 sc->sge.sw_zone_info[zidx].size, region1, 5013 sc->sge.hw_buf_info[hwidx].size, region3)); 5014 } 5015 5016 fl->cll_def.zidx = zidx; 5017 fl->cll_def.hwidx = hwidx; 5018 fl->cll_def.region1 = region1; 5019 fl->cll_def.region3 = region3; 5020 } 5021 5022 static void 5023 find_safe_refill_source(struct adapter *sc, struct sge_fl *fl) 5024 { 5025 struct sge *s = &sc->sge; 5026 struct hw_buf_info *hwb; 5027 struct sw_zone_info *swz; 5028 int spare; 5029 int8_t hwidx; 5030 5031 if (fl->flags & FL_BUF_PACKING) 5032 hwidx = s->safe_hwidx2; /* with room for metadata */ 5033 else if (allow_mbufs_in_cluster && s->safe_hwidx2 != -1) { 5034 hwidx = s->safe_hwidx2; 5035 hwb = &s->hw_buf_info[hwidx]; 5036 swz = &s->sw_zone_info[hwb->zidx]; 5037 spare = swz->size - hwb->size; 5038 5039 /* no good if there isn't room for an mbuf as well */ 5040 if (spare < CL_METADATA_SIZE + MSIZE) 5041 hwidx = s->safe_hwidx1; 5042 } else 5043 hwidx = s->safe_hwidx1; 5044 5045 if (hwidx == -1) { 5046 /* No fallback source */ 5047 fl->cll_alt.hwidx = -1; 5048 fl->cll_alt.zidx = -1; 5049 5050 return; 5051 } 5052 5053 hwb = &s->hw_buf_info[hwidx]; 5054 swz = &s->sw_zone_info[hwb->zidx]; 5055 spare = swz->size - hwb->size; 5056 fl->cll_alt.hwidx = hwidx; 5057 fl->cll_alt.zidx = hwb->zidx; 5058 if (allow_mbufs_in_cluster && 5059 (fl_pad == 0 || (MSIZE % sc->params.sge.pad_boundary) == 0)) 5060 fl->cll_alt.region1 = ((spare - CL_METADATA_SIZE) / MSIZE) * MSIZE; 5061 else 5062 fl->cll_alt.region1 = 0; 5063 fl->cll_alt.region3 = spare - fl->cll_alt.region1; 5064 } 5065 5066 static void 5067 add_fl_to_sfl(struct adapter *sc, struct sge_fl *fl) 5068 { 5069 mtx_lock(&sc->sfl_lock); 5070 FL_LOCK(fl); 5071 if ((fl->flags & FL_DOOMED) == 0) { 5072 fl->flags |= FL_STARVING; 5073 TAILQ_INSERT_TAIL(&sc->sfl, fl, link); 5074 callout_reset(&sc->sfl_callout, hz / 5, refill_sfl, sc); 5075 } 5076 FL_UNLOCK(fl); 5077 mtx_unlock(&sc->sfl_lock); 5078 } 5079 5080 static void 5081 handle_wrq_egr_update(struct adapter *sc, struct sge_eq *eq) 5082 { 5083 struct sge_wrq *wrq = (void *)eq; 5084 5085 atomic_readandclear_int(&eq->equiq); 5086 taskqueue_enqueue(sc->tq[eq->tx_chan], &wrq->wrq_tx_task); 5087 } 5088 5089 static void 5090 handle_eth_egr_update(struct adapter *sc, struct sge_eq *eq) 5091 { 5092 struct sge_txq *txq = (void *)eq; 5093 5094 MPASS((eq->flags & EQ_TYPEMASK) == EQ_ETH); 5095 5096 atomic_readandclear_int(&eq->equiq); 5097 mp_ring_check_drainage(txq->r, 0); 5098 taskqueue_enqueue(sc->tq[eq->tx_chan], &txq->tx_reclaim_task); 5099 } 5100 5101 static int 5102 handle_sge_egr_update(struct sge_iq *iq, const struct rss_header *rss, 5103 struct mbuf *m) 5104 { 5105 const struct cpl_sge_egr_update *cpl = (const void *)(rss + 1); 5106 unsigned int qid = G_EGR_QID(ntohl(cpl->opcode_qid)); 5107 struct adapter *sc = iq->adapter; 5108 struct sge *s = &sc->sge; 5109 struct sge_eq *eq; 5110 static void (*h[])(struct adapter *, struct sge_eq *) = {NULL, 5111 &handle_wrq_egr_update, &handle_eth_egr_update, 5112 &handle_wrq_egr_update}; 5113 5114 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 5115 rss->opcode)); 5116 5117 eq = s->eqmap[qid - s->eq_start - s->eq_base]; 5118 (*h[eq->flags & EQ_TYPEMASK])(sc, eq); 5119 5120 return (0); 5121 } 5122 5123 /* handle_fw_msg works for both fw4_msg and fw6_msg because this is valid */ 5124 CTASSERT(offsetof(struct cpl_fw4_msg, data) == \ 5125 offsetof(struct cpl_fw6_msg, data)); 5126 5127 static int 5128 handle_fw_msg(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 5129 { 5130 struct adapter *sc = iq->adapter; 5131 const struct cpl_fw6_msg *cpl = (const void *)(rss + 1); 5132 5133 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 5134 rss->opcode)); 5135 5136 if (cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL) { 5137 const struct rss_header *rss2; 5138 5139 rss2 = (const struct rss_header *)&cpl->data[0]; 5140 return (t4_cpl_handler[rss2->opcode](iq, rss2, m)); 5141 } 5142 5143 return (t4_fw_msg_handler[cpl->type](sc, &cpl->data[0])); 5144 } 5145 5146 /** 5147 * t4_handle_wrerr_rpl - process a FW work request error message 5148 * @adap: the adapter 5149 * @rpl: start of the FW message 5150 */ 5151 static int 5152 t4_handle_wrerr_rpl(struct adapter *adap, const __be64 *rpl) 5153 { 5154 u8 opcode = *(const u8 *)rpl; 5155 const struct fw_error_cmd *e = (const void *)rpl; 5156 unsigned int i; 5157 5158 if (opcode != FW_ERROR_CMD) { 5159 log(LOG_ERR, 5160 "%s: Received WRERR_RPL message with opcode %#x\n", 5161 device_get_nameunit(adap->dev), opcode); 5162 return (EINVAL); 5163 } 5164 log(LOG_ERR, "%s: FW_ERROR (%s) ", device_get_nameunit(adap->dev), 5165 G_FW_ERROR_CMD_FATAL(be32toh(e->op_to_type)) ? "fatal" : 5166 "non-fatal"); 5167 switch (G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type))) { 5168 case FW_ERROR_TYPE_EXCEPTION: 5169 log(LOG_ERR, "exception info:\n"); 5170 for (i = 0; i < nitems(e->u.exception.info); i++) 5171 log(LOG_ERR, "%s%08x", i == 0 ? "\t" : " ", 5172 be32toh(e->u.exception.info[i])); 5173 log(LOG_ERR, "\n"); 5174 break; 5175 case FW_ERROR_TYPE_HWMODULE: 5176 log(LOG_ERR, "HW module regaddr %08x regval %08x\n", 5177 be32toh(e->u.hwmodule.regaddr), 5178 be32toh(e->u.hwmodule.regval)); 5179 break; 5180 case FW_ERROR_TYPE_WR: 5181 log(LOG_ERR, "WR cidx %d PF %d VF %d eqid %d hdr:\n", 5182 be16toh(e->u.wr.cidx), 5183 G_FW_ERROR_CMD_PFN(be16toh(e->u.wr.pfn_vfn)), 5184 G_FW_ERROR_CMD_VFN(be16toh(e->u.wr.pfn_vfn)), 5185 be32toh(e->u.wr.eqid)); 5186 for (i = 0; i < nitems(e->u.wr.wrhdr); i++) 5187 log(LOG_ERR, "%s%02x", i == 0 ? "\t" : " ", 5188 e->u.wr.wrhdr[i]); 5189 log(LOG_ERR, "\n"); 5190 break; 5191 case FW_ERROR_TYPE_ACL: 5192 log(LOG_ERR, "ACL cidx %d PF %d VF %d eqid %d %s", 5193 be16toh(e->u.acl.cidx), 5194 G_FW_ERROR_CMD_PFN(be16toh(e->u.acl.pfn_vfn)), 5195 G_FW_ERROR_CMD_VFN(be16toh(e->u.acl.pfn_vfn)), 5196 be32toh(e->u.acl.eqid), 5197 G_FW_ERROR_CMD_MV(be16toh(e->u.acl.mv_pkd)) ? "vlanid" : 5198 "MAC"); 5199 for (i = 0; i < nitems(e->u.acl.val); i++) 5200 log(LOG_ERR, " %02x", e->u.acl.val[i]); 5201 log(LOG_ERR, "\n"); 5202 break; 5203 default: 5204 log(LOG_ERR, "type %#x\n", 5205 G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type))); 5206 return (EINVAL); 5207 } 5208 return (0); 5209 } 5210 5211 static int 5212 sysctl_uint16(SYSCTL_HANDLER_ARGS) 5213 { 5214 uint16_t *id = arg1; 5215 int i = *id; 5216 5217 return sysctl_handle_int(oidp, &i, 0, req); 5218 } 5219 5220 static int 5221 sysctl_bufsizes(SYSCTL_HANDLER_ARGS) 5222 { 5223 struct sge *s = arg1; 5224 struct hw_buf_info *hwb = &s->hw_buf_info[0]; 5225 struct sw_zone_info *swz = &s->sw_zone_info[0]; 5226 int i, rc; 5227 struct sbuf sb; 5228 char c; 5229 5230 sbuf_new(&sb, NULL, 32, SBUF_AUTOEXTEND); 5231 for (i = 0; i < SGE_FLBUF_SIZES; i++, hwb++) { 5232 if (hwb->zidx >= 0 && swz[hwb->zidx].size <= largest_rx_cluster) 5233 c = '*'; 5234 else 5235 c = '\0'; 5236 5237 sbuf_printf(&sb, "%u%c ", hwb->size, c); 5238 } 5239 sbuf_trim(&sb); 5240 sbuf_finish(&sb); 5241 rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req); 5242 sbuf_delete(&sb); 5243 return (rc); 5244 } 5245 5246 static int 5247 sysctl_tc(SYSCTL_HANDLER_ARGS) 5248 { 5249 struct vi_info *vi = arg1; 5250 struct port_info *pi; 5251 struct adapter *sc; 5252 struct sge_txq *txq; 5253 struct tx_cl_rl_params *tc; 5254 int qidx = arg2, rc, tc_idx; 5255 uint32_t fw_queue, fw_class; 5256 5257 MPASS(qidx >= 0 && qidx < vi->ntxq); 5258 pi = vi->pi; 5259 sc = pi->adapter; 5260 txq = &sc->sge.txq[vi->first_txq + qidx]; 5261 5262 tc_idx = txq->tc_idx; 5263 rc = sysctl_handle_int(oidp, &tc_idx, 0, req); 5264 if (rc != 0 || req->newptr == NULL) 5265 return (rc); 5266 5267 if (sc->flags & IS_VF) 5268 return (EPERM); 5269 5270 /* Note that -1 is legitimate input (it means unbind). */ 5271 if (tc_idx < -1 || tc_idx >= sc->chip_params->nsched_cls) 5272 return (EINVAL); 5273 5274 mtx_lock(&sc->tc_lock); 5275 if (tc_idx == txq->tc_idx) { 5276 rc = 0; /* No change, nothing to do. */ 5277 goto done; 5278 } 5279 5280 fw_queue = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 5281 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH) | 5282 V_FW_PARAMS_PARAM_YZ(txq->eq.cntxt_id); 5283 5284 if (tc_idx == -1) 5285 fw_class = 0xffffffff; /* Unbind. */ 5286 else { 5287 /* 5288 * Bind to a different class. 5289 */ 5290 tc = &pi->sched_params->cl_rl[tc_idx]; 5291 if (tc->flags & TX_CLRL_ERROR) { 5292 /* Previous attempt to set the cl-rl params failed. */ 5293 rc = EIO; 5294 goto done; 5295 } else { 5296 /* 5297 * Ok to proceed. Place a reference on the new class 5298 * while still holding on to the reference on the 5299 * previous class, if any. 5300 */ 5301 fw_class = tc_idx; 5302 tc->refcount++; 5303 } 5304 } 5305 mtx_unlock(&sc->tc_lock); 5306 5307 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4stc"); 5308 if (rc) 5309 return (rc); 5310 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &fw_queue, &fw_class); 5311 end_synchronized_op(sc, 0); 5312 5313 mtx_lock(&sc->tc_lock); 5314 if (rc == 0) { 5315 if (txq->tc_idx != -1) { 5316 tc = &pi->sched_params->cl_rl[txq->tc_idx]; 5317 MPASS(tc->refcount > 0); 5318 tc->refcount--; 5319 } 5320 txq->tc_idx = tc_idx; 5321 } else { 5322 tc = &pi->sched_params->cl_rl[tc_idx]; 5323 MPASS(tc->refcount > 0); 5324 tc->refcount--; 5325 } 5326 done: 5327 mtx_unlock(&sc->tc_lock); 5328 return (rc); 5329 } 5330