154e4ee71SNavdeep Parhar /*- 2718cf2ccSPedro F. Giffuni * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3718cf2ccSPedro F. Giffuni * 454e4ee71SNavdeep Parhar * Copyright (c) 2011 Chelsio Communications, Inc. 554e4ee71SNavdeep Parhar * All rights reserved. 654e4ee71SNavdeep Parhar * Written by: Navdeep Parhar <np@FreeBSD.org> 754e4ee71SNavdeep Parhar * 854e4ee71SNavdeep Parhar * Redistribution and use in source and binary forms, with or without 954e4ee71SNavdeep Parhar * modification, are permitted provided that the following conditions 1054e4ee71SNavdeep Parhar * are met: 1154e4ee71SNavdeep Parhar * 1. Redistributions of source code must retain the above copyright 1254e4ee71SNavdeep Parhar * notice, this list of conditions and the following disclaimer. 1354e4ee71SNavdeep Parhar * 2. Redistributions in binary form must reproduce the above copyright 1454e4ee71SNavdeep Parhar * notice, this list of conditions and the following disclaimer in the 1554e4ee71SNavdeep Parhar * documentation and/or other materials provided with the distribution. 1654e4ee71SNavdeep Parhar * 1754e4ee71SNavdeep Parhar * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1854e4ee71SNavdeep Parhar * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1954e4ee71SNavdeep Parhar * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2054e4ee71SNavdeep Parhar * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 2154e4ee71SNavdeep Parhar * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2254e4ee71SNavdeep Parhar * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2354e4ee71SNavdeep Parhar * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2454e4ee71SNavdeep Parhar * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2554e4ee71SNavdeep Parhar * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2654e4ee71SNavdeep Parhar * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2754e4ee71SNavdeep Parhar * SUCH DAMAGE. 2854e4ee71SNavdeep Parhar */ 2954e4ee71SNavdeep Parhar 3054e4ee71SNavdeep Parhar #include <sys/cdefs.h> 3154e4ee71SNavdeep Parhar __FBSDID("$FreeBSD$"); 3254e4ee71SNavdeep Parhar 3354e4ee71SNavdeep Parhar #include "opt_inet.h" 34a1ea9a82SNavdeep Parhar #include "opt_inet6.h" 3554e4ee71SNavdeep Parhar 3654e4ee71SNavdeep Parhar #include <sys/types.h> 37c3322cb9SGleb Smirnoff #include <sys/eventhandler.h> 3854e4ee71SNavdeep Parhar #include <sys/mbuf.h> 3954e4ee71SNavdeep Parhar #include <sys/socket.h> 4054e4ee71SNavdeep Parhar #include <sys/kernel.h> 41ecb79ca4SNavdeep Parhar #include <sys/malloc.h> 42ecb79ca4SNavdeep Parhar #include <sys/queue.h> 4338035ed6SNavdeep Parhar #include <sys/sbuf.h> 44ecb79ca4SNavdeep Parhar #include <sys/taskqueue.h> 45480e603cSNavdeep Parhar #include <sys/time.h> 467951040fSNavdeep Parhar #include <sys/sglist.h> 4754e4ee71SNavdeep Parhar #include <sys/sysctl.h> 48733b9277SNavdeep Parhar #include <sys/smp.h> 4982eff304SNavdeep Parhar #include <sys/counter.h> 5054e4ee71SNavdeep Parhar #include <net/bpf.h> 5154e4ee71SNavdeep Parhar #include <net/ethernet.h> 5254e4ee71SNavdeep Parhar #include <net/if.h> 5354e4ee71SNavdeep Parhar #include <net/if_vlan_var.h> 5454e4ee71SNavdeep Parhar #include <netinet/in.h> 5554e4ee71SNavdeep Parhar #include <netinet/ip.h> 56a1ea9a82SNavdeep Parhar #include <netinet/ip6.h> 5754e4ee71SNavdeep Parhar #include <netinet/tcp.h> 586af45170SJohn Baldwin #include <machine/in_cksum.h> 5964db8966SDimitry Andric #include <machine/md_var.h> 6038035ed6SNavdeep Parhar #include <vm/vm.h> 6138035ed6SNavdeep Parhar #include <vm/pmap.h> 62298d969cSNavdeep Parhar #ifdef DEV_NETMAP 63298d969cSNavdeep Parhar #include <machine/bus.h> 64298d969cSNavdeep Parhar #include <sys/selinfo.h> 65298d969cSNavdeep Parhar #include <net/if_var.h> 66298d969cSNavdeep Parhar #include <net/netmap.h> 67298d969cSNavdeep Parhar #include <dev/netmap/netmap_kern.h> 68298d969cSNavdeep Parhar #endif 6954e4ee71SNavdeep Parhar 7054e4ee71SNavdeep Parhar #include "common/common.h" 7154e4ee71SNavdeep Parhar #include "common/t4_regs.h" 7254e4ee71SNavdeep Parhar #include "common/t4_regs_values.h" 7354e4ee71SNavdeep Parhar #include "common/t4_msg.h" 74671bf2b8SNavdeep Parhar #include "t4_l2t.h" 757951040fSNavdeep Parhar #include "t4_mp_ring.h" 7654e4ee71SNavdeep Parhar 77d14b0ac1SNavdeep Parhar #ifdef T4_PKT_TIMESTAMP 78d14b0ac1SNavdeep Parhar #define RX_COPY_THRESHOLD (MINCLSIZE - 8) 79d14b0ac1SNavdeep Parhar #else 80d14b0ac1SNavdeep Parhar #define RX_COPY_THRESHOLD MINCLSIZE 81d14b0ac1SNavdeep Parhar #endif 82d14b0ac1SNavdeep Parhar 839fb8886bSNavdeep Parhar /* 849fb8886bSNavdeep Parhar * Ethernet frames are DMA'd at this byte offset into the freelist buffer. 859fb8886bSNavdeep Parhar * 0-7 are valid values. 869fb8886bSNavdeep Parhar */ 8729c229e9SJohn Baldwin static int fl_pktshift = 2; 889fb8886bSNavdeep Parhar TUNABLE_INT("hw.cxgbe.fl_pktshift", &fl_pktshift); 8954e4ee71SNavdeep Parhar 909fb8886bSNavdeep Parhar /* 919fb8886bSNavdeep Parhar * Pad ethernet payload up to this boundary. 929fb8886bSNavdeep Parhar * -1: driver should figure out a good value. 931458bff9SNavdeep Parhar * 0: disable padding. 941458bff9SNavdeep Parhar * Any power of 2 from 32 to 4096 (both inclusive) is also a valid value. 959fb8886bSNavdeep Parhar */ 96298d969cSNavdeep Parhar int fl_pad = -1; 979fb8886bSNavdeep Parhar TUNABLE_INT("hw.cxgbe.fl_pad", &fl_pad); 989fb8886bSNavdeep Parhar 999fb8886bSNavdeep Parhar /* 1009fb8886bSNavdeep Parhar * Status page length. 1019fb8886bSNavdeep Parhar * -1: driver should figure out a good value. 1029fb8886bSNavdeep Parhar * 64 or 128 are the only other valid values. 1039fb8886bSNavdeep Parhar */ 10429c229e9SJohn Baldwin static int spg_len = -1; 1059fb8886bSNavdeep Parhar TUNABLE_INT("hw.cxgbe.spg_len", &spg_len); 1069fb8886bSNavdeep Parhar 1079fb8886bSNavdeep Parhar /* 1089fb8886bSNavdeep Parhar * Congestion drops. 1099fb8886bSNavdeep Parhar * -1: no congestion feedback (not recommended). 1109fb8886bSNavdeep Parhar * 0: backpressure the channel instead of dropping packets right away. 1119fb8886bSNavdeep Parhar * 1: no backpressure, drop packets for the congested queue immediately. 1129fb8886bSNavdeep Parhar */ 1139fb8886bSNavdeep Parhar static int cong_drop = 0; 1149fb8886bSNavdeep Parhar TUNABLE_INT("hw.cxgbe.cong_drop", &cong_drop); 11554e4ee71SNavdeep Parhar 1161458bff9SNavdeep Parhar /* 1171458bff9SNavdeep Parhar * Deliver multiple frames in the same free list buffer if they fit. 1181458bff9SNavdeep Parhar * -1: let the driver decide whether to enable buffer packing or not. 1191458bff9SNavdeep Parhar * 0: disable buffer packing. 1201458bff9SNavdeep Parhar * 1: enable buffer packing. 1211458bff9SNavdeep Parhar */ 1221458bff9SNavdeep Parhar static int buffer_packing = -1; 1231458bff9SNavdeep Parhar TUNABLE_INT("hw.cxgbe.buffer_packing", &buffer_packing); 1241458bff9SNavdeep Parhar 1251458bff9SNavdeep Parhar /* 1261458bff9SNavdeep Parhar * Start next frame in a packed buffer at this boundary. 1271458bff9SNavdeep Parhar * -1: driver should figure out a good value. 128e3207e19SNavdeep Parhar * T4: driver will ignore this and use the same value as fl_pad above. 129e3207e19SNavdeep Parhar * T5: 16, or a power of 2 from 64 to 4096 (both inclusive) is a valid value. 1301458bff9SNavdeep Parhar */ 1311458bff9SNavdeep Parhar static int fl_pack = -1; 1321458bff9SNavdeep Parhar TUNABLE_INT("hw.cxgbe.fl_pack", &fl_pack); 1331458bff9SNavdeep Parhar 13438035ed6SNavdeep Parhar /* 13538035ed6SNavdeep Parhar * Allow the driver to create mbuf(s) in a cluster allocated for rx. 13638035ed6SNavdeep Parhar * 0: never; always allocate mbufs from the zone_mbuf UMA zone. 13738035ed6SNavdeep Parhar * 1: ok to create mbuf(s) within a cluster if there is room. 13838035ed6SNavdeep Parhar */ 13938035ed6SNavdeep Parhar static int allow_mbufs_in_cluster = 1; 14038035ed6SNavdeep Parhar TUNABLE_INT("hw.cxgbe.allow_mbufs_in_cluster", &allow_mbufs_in_cluster); 14138035ed6SNavdeep Parhar 14238035ed6SNavdeep Parhar /* 14338035ed6SNavdeep Parhar * Largest rx cluster size that the driver is allowed to allocate. 14438035ed6SNavdeep Parhar */ 14538035ed6SNavdeep Parhar static int largest_rx_cluster = MJUM16BYTES; 14638035ed6SNavdeep Parhar TUNABLE_INT("hw.cxgbe.largest_rx_cluster", &largest_rx_cluster); 14738035ed6SNavdeep Parhar 14838035ed6SNavdeep Parhar /* 14938035ed6SNavdeep Parhar * Size of cluster allocation that's most likely to succeed. The driver will 15038035ed6SNavdeep Parhar * fall back to this size if it fails to allocate clusters larger than this. 15138035ed6SNavdeep Parhar */ 15238035ed6SNavdeep Parhar static int safest_rx_cluster = PAGE_SIZE; 15338035ed6SNavdeep Parhar TUNABLE_INT("hw.cxgbe.safest_rx_cluster", &safest_rx_cluster); 15438035ed6SNavdeep Parhar 155d491f8caSNavdeep Parhar /* 156d491f8caSNavdeep Parhar * The interrupt holdoff timers are multiplied by this value on T6+. 157d491f8caSNavdeep Parhar * 1 and 3-17 (both inclusive) are legal values. 158d491f8caSNavdeep Parhar */ 159d491f8caSNavdeep Parhar static int tscale = 1; 160d491f8caSNavdeep Parhar TUNABLE_INT("hw.cxgbe.tscale", &tscale); 161d491f8caSNavdeep Parhar 16246f48ee5SNavdeep Parhar /* 16346f48ee5SNavdeep Parhar * Number of LRO entries in the lro_ctrl structure per rx queue. 16446f48ee5SNavdeep Parhar */ 16546f48ee5SNavdeep Parhar static int lro_entries = TCP_LRO_ENTRIES; 16646f48ee5SNavdeep Parhar TUNABLE_INT("hw.cxgbe.lro_entries", &lro_entries); 16746f48ee5SNavdeep Parhar 16846f48ee5SNavdeep Parhar /* 16946f48ee5SNavdeep Parhar * This enables presorting of frames before they're fed into tcp_lro_rx. 17046f48ee5SNavdeep Parhar */ 17146f48ee5SNavdeep Parhar static int lro_mbufs = 0; 17246f48ee5SNavdeep Parhar TUNABLE_INT("hw.cxgbe.lro_mbufs", &lro_mbufs); 17346f48ee5SNavdeep Parhar 17454e4ee71SNavdeep Parhar struct txpkts { 1757951040fSNavdeep Parhar u_int wr_type; /* type 0 or type 1 */ 1767951040fSNavdeep Parhar u_int npkt; /* # of packets in this work request */ 1777951040fSNavdeep Parhar u_int plen; /* total payload (sum of all packets) */ 1787951040fSNavdeep Parhar u_int len16; /* # of 16B pieces used by this work request */ 17954e4ee71SNavdeep Parhar }; 18054e4ee71SNavdeep Parhar 18154e4ee71SNavdeep Parhar /* A packet's SGL. This + m_pkthdr has all info needed for tx */ 18254e4ee71SNavdeep Parhar struct sgl { 1837951040fSNavdeep Parhar struct sglist sg; 1847951040fSNavdeep Parhar struct sglist_seg seg[TX_SGL_SEGS]; 18554e4ee71SNavdeep Parhar }; 18654e4ee71SNavdeep Parhar 187733b9277SNavdeep Parhar static int service_iq(struct sge_iq *, int); 1884d6db4e0SNavdeep Parhar static struct mbuf *get_fl_payload(struct adapter *, struct sge_fl *, uint32_t); 189733b9277SNavdeep Parhar static int t4_eth_rx(struct sge_iq *, const struct rss_header *, struct mbuf *); 190b2daa9a9SNavdeep Parhar static inline void init_iq(struct sge_iq *, struct adapter *, int, int, int); 191e3207e19SNavdeep Parhar static inline void init_fl(struct adapter *, struct sge_fl *, int, int, char *); 19290e7434aSNavdeep Parhar static inline void init_eq(struct adapter *, struct sge_eq *, int, int, uint8_t, 19390e7434aSNavdeep Parhar uint16_t, char *); 19454e4ee71SNavdeep Parhar static int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *, 19554e4ee71SNavdeep Parhar bus_addr_t *, void **); 19654e4ee71SNavdeep Parhar static int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 19754e4ee71SNavdeep Parhar void *); 198fe2ebb76SJohn Baldwin static int alloc_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *, 199bc14b14dSNavdeep Parhar int, int); 200fe2ebb76SJohn Baldwin static int free_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *); 201348694daSNavdeep Parhar static void add_iq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *, 202348694daSNavdeep Parhar struct sge_iq *); 203aa93b99aSNavdeep Parhar static void add_fl_sysctls(struct adapter *, struct sysctl_ctx_list *, 204aa93b99aSNavdeep Parhar struct sysctl_oid *, struct sge_fl *); 205733b9277SNavdeep Parhar static int alloc_fwq(struct adapter *); 206733b9277SNavdeep Parhar static int free_fwq(struct adapter *); 207733b9277SNavdeep Parhar static int alloc_mgmtq(struct adapter *); 208733b9277SNavdeep Parhar static int free_mgmtq(struct adapter *); 209fe2ebb76SJohn Baldwin static int alloc_rxq(struct vi_info *, struct sge_rxq *, int, int, 210733b9277SNavdeep Parhar struct sysctl_oid *); 211fe2ebb76SJohn Baldwin static int free_rxq(struct vi_info *, struct sge_rxq *); 21209fe6320SNavdeep Parhar #ifdef TCP_OFFLOAD 213fe2ebb76SJohn Baldwin static int alloc_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *, int, int, 214733b9277SNavdeep Parhar struct sysctl_oid *); 215fe2ebb76SJohn Baldwin static int free_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *); 216733b9277SNavdeep Parhar #endif 217298d969cSNavdeep Parhar #ifdef DEV_NETMAP 218fe2ebb76SJohn Baldwin static int alloc_nm_rxq(struct vi_info *, struct sge_nm_rxq *, int, int, 219298d969cSNavdeep Parhar struct sysctl_oid *); 220fe2ebb76SJohn Baldwin static int free_nm_rxq(struct vi_info *, struct sge_nm_rxq *); 221fe2ebb76SJohn Baldwin static int alloc_nm_txq(struct vi_info *, struct sge_nm_txq *, int, int, 222298d969cSNavdeep Parhar struct sysctl_oid *); 223fe2ebb76SJohn Baldwin static int free_nm_txq(struct vi_info *, struct sge_nm_txq *); 224298d969cSNavdeep Parhar #endif 225733b9277SNavdeep Parhar static int ctrl_eq_alloc(struct adapter *, struct sge_eq *); 226fe2ebb76SJohn Baldwin static int eth_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *); 22709fe6320SNavdeep Parhar #ifdef TCP_OFFLOAD 228fe2ebb76SJohn Baldwin static int ofld_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *); 229733b9277SNavdeep Parhar #endif 230fe2ebb76SJohn Baldwin static int alloc_eq(struct adapter *, struct vi_info *, struct sge_eq *); 231733b9277SNavdeep Parhar static int free_eq(struct adapter *, struct sge_eq *); 232fe2ebb76SJohn Baldwin static int alloc_wrq(struct adapter *, struct vi_info *, struct sge_wrq *, 233733b9277SNavdeep Parhar struct sysctl_oid *); 234733b9277SNavdeep Parhar static int free_wrq(struct adapter *, struct sge_wrq *); 235fe2ebb76SJohn Baldwin static int alloc_txq(struct vi_info *, struct sge_txq *, int, 236733b9277SNavdeep Parhar struct sysctl_oid *); 237fe2ebb76SJohn Baldwin static int free_txq(struct vi_info *, struct sge_txq *); 23854e4ee71SNavdeep Parhar static void oneseg_dma_callback(void *, bus_dma_segment_t *, int, int); 23954e4ee71SNavdeep Parhar static inline void ring_fl_db(struct adapter *, struct sge_fl *); 240733b9277SNavdeep Parhar static int refill_fl(struct adapter *, struct sge_fl *, int); 241733b9277SNavdeep Parhar static void refill_sfl(void *); 24254e4ee71SNavdeep Parhar static int alloc_fl_sdesc(struct sge_fl *); 2431458bff9SNavdeep Parhar static void free_fl_sdesc(struct adapter *, struct sge_fl *); 24438035ed6SNavdeep Parhar static void find_best_refill_source(struct adapter *, struct sge_fl *, int); 24538035ed6SNavdeep Parhar static void find_safe_refill_source(struct adapter *, struct sge_fl *); 246733b9277SNavdeep Parhar static void add_fl_to_sfl(struct adapter *, struct sge_fl *); 24754e4ee71SNavdeep Parhar 2487951040fSNavdeep Parhar static inline void get_pkt_gl(struct mbuf *, struct sglist *); 2497951040fSNavdeep Parhar static inline u_int txpkt_len16(u_int, u_int); 2506af45170SJohn Baldwin static inline u_int txpkt_vm_len16(u_int, u_int); 2517951040fSNavdeep Parhar static inline u_int txpkts0_len16(u_int); 2527951040fSNavdeep Parhar static inline u_int txpkts1_len16(void); 2537951040fSNavdeep Parhar static u_int write_txpkt_wr(struct sge_txq *, struct fw_eth_tx_pkt_wr *, 2547951040fSNavdeep Parhar struct mbuf *, u_int); 255472a6004SNavdeep Parhar static u_int write_txpkt_vm_wr(struct adapter *, struct sge_txq *, 256472a6004SNavdeep Parhar struct fw_eth_tx_pkt_vm_wr *, struct mbuf *, u_int); 2577951040fSNavdeep Parhar static int try_txpkts(struct mbuf *, struct mbuf *, struct txpkts *, u_int); 2587951040fSNavdeep Parhar static int add_to_txpkts(struct mbuf *, struct txpkts *, u_int); 2597951040fSNavdeep Parhar static u_int write_txpkts_wr(struct sge_txq *, struct fw_eth_tx_pkts_wr *, 2607951040fSNavdeep Parhar struct mbuf *, const struct txpkts *, u_int); 2617951040fSNavdeep Parhar static void write_gl_to_txd(struct sge_txq *, struct mbuf *, caddr_t *, int); 26254e4ee71SNavdeep Parhar static inline void copy_to_txd(struct sge_eq *, caddr_t, caddr_t *, int); 2637951040fSNavdeep Parhar static inline void ring_eq_db(struct adapter *, struct sge_eq *, u_int); 2647951040fSNavdeep Parhar static inline uint16_t read_hw_cidx(struct sge_eq *); 2657951040fSNavdeep Parhar static inline u_int reclaimable_tx_desc(struct sge_eq *); 2667951040fSNavdeep Parhar static inline u_int total_available_tx_desc(struct sge_eq *); 2677951040fSNavdeep Parhar static u_int reclaim_tx_descs(struct sge_txq *, u_int); 2687951040fSNavdeep Parhar static void tx_reclaim(void *, int); 2697951040fSNavdeep Parhar static __be64 get_flit(struct sglist_seg *, int, int); 270733b9277SNavdeep Parhar static int handle_sge_egr_update(struct sge_iq *, const struct rss_header *, 271733b9277SNavdeep Parhar struct mbuf *); 2721b4cc91fSNavdeep Parhar static int handle_fw_msg(struct sge_iq *, const struct rss_header *, 273733b9277SNavdeep Parhar struct mbuf *); 274069af0ebSJohn Baldwin static int t4_handle_wrerr_rpl(struct adapter *, const __be64 *); 2757951040fSNavdeep Parhar static void wrq_tx_drain(void *, int); 2767951040fSNavdeep Parhar static void drain_wrq_wr_list(struct adapter *, struct sge_wrq *); 27754e4ee71SNavdeep Parhar 27856599263SNavdeep Parhar static int sysctl_uint16(SYSCTL_HANDLER_ARGS); 27938035ed6SNavdeep Parhar static int sysctl_bufsizes(SYSCTL_HANDLER_ARGS); 28002f972e8SNavdeep Parhar static int sysctl_tc(SYSCTL_HANDLER_ARGS); 281f7dfe243SNavdeep Parhar 28282eff304SNavdeep Parhar static counter_u64_t extfree_refs; 28382eff304SNavdeep Parhar static counter_u64_t extfree_rels; 28482eff304SNavdeep Parhar 285671bf2b8SNavdeep Parhar an_handler_t t4_an_handler; 286671bf2b8SNavdeep Parhar fw_msg_handler_t t4_fw_msg_handler[NUM_FW6_TYPES]; 287671bf2b8SNavdeep Parhar cpl_handler_t t4_cpl_handler[NUM_CPL_CMDS]; 2884535e804SNavdeep Parhar cpl_handler_t set_tcb_rpl_handlers[NUM_CPL_COOKIES]; 2894535e804SNavdeep Parhar cpl_handler_t l2t_write_rpl_handlers[NUM_CPL_COOKIES]; 290*111638bfSNavdeep Parhar cpl_handler_t act_open_rpl_handlers[NUM_CPL_COOKIES]; 291671bf2b8SNavdeep Parhar 2924535e804SNavdeep Parhar void 293671bf2b8SNavdeep Parhar t4_register_an_handler(an_handler_t h) 294671bf2b8SNavdeep Parhar { 2954535e804SNavdeep Parhar uintptr_t *loc; 296671bf2b8SNavdeep Parhar 2974535e804SNavdeep Parhar MPASS(h == NULL || t4_an_handler == NULL); 2984535e804SNavdeep Parhar 299671bf2b8SNavdeep Parhar loc = (uintptr_t *)&t4_an_handler; 3004535e804SNavdeep Parhar atomic_store_rel_ptr(loc, (uintptr_t)h); 301671bf2b8SNavdeep Parhar } 302671bf2b8SNavdeep Parhar 3034535e804SNavdeep Parhar void 304671bf2b8SNavdeep Parhar t4_register_fw_msg_handler(int type, fw_msg_handler_t h) 305671bf2b8SNavdeep Parhar { 3064535e804SNavdeep Parhar uintptr_t *loc; 307671bf2b8SNavdeep Parhar 3084535e804SNavdeep Parhar MPASS(type < nitems(t4_fw_msg_handler)); 3094535e804SNavdeep Parhar MPASS(h == NULL || t4_fw_msg_handler[type] == NULL); 310671bf2b8SNavdeep Parhar /* 311671bf2b8SNavdeep Parhar * These are dispatched by the handler for FW{4|6}_CPL_MSG using the CPL 312671bf2b8SNavdeep Parhar * handler dispatch table. Reject any attempt to install a handler for 313671bf2b8SNavdeep Parhar * this subtype. 314671bf2b8SNavdeep Parhar */ 3154535e804SNavdeep Parhar MPASS(type != FW_TYPE_RSSCPL); 3164535e804SNavdeep Parhar MPASS(type != FW6_TYPE_RSSCPL); 317671bf2b8SNavdeep Parhar 318671bf2b8SNavdeep Parhar loc = (uintptr_t *)&t4_fw_msg_handler[type]; 3194535e804SNavdeep Parhar atomic_store_rel_ptr(loc, (uintptr_t)h); 3204535e804SNavdeep Parhar } 321671bf2b8SNavdeep Parhar 3224535e804SNavdeep Parhar void 3234535e804SNavdeep Parhar t4_register_cpl_handler(int opcode, cpl_handler_t h) 3244535e804SNavdeep Parhar { 3254535e804SNavdeep Parhar uintptr_t *loc; 3264535e804SNavdeep Parhar 3274535e804SNavdeep Parhar MPASS(opcode < nitems(t4_cpl_handler)); 3284535e804SNavdeep Parhar MPASS(h == NULL || t4_cpl_handler[opcode] == NULL); 3294535e804SNavdeep Parhar 3304535e804SNavdeep Parhar loc = (uintptr_t *)&t4_cpl_handler[opcode]; 3314535e804SNavdeep Parhar atomic_store_rel_ptr(loc, (uintptr_t)h); 332671bf2b8SNavdeep Parhar } 333671bf2b8SNavdeep Parhar 334671bf2b8SNavdeep Parhar static int 3354535e804SNavdeep Parhar set_tcb_rpl_handler(struct sge_iq *iq, const struct rss_header *rss, 3364535e804SNavdeep Parhar struct mbuf *m) 337671bf2b8SNavdeep Parhar { 3384535e804SNavdeep Parhar const struct cpl_set_tcb_rpl *cpl = (const void *)(rss + 1); 3394535e804SNavdeep Parhar u_int tid; 3404535e804SNavdeep Parhar int cookie; 341671bf2b8SNavdeep Parhar 3424535e804SNavdeep Parhar MPASS(m == NULL); 3434535e804SNavdeep Parhar 3444535e804SNavdeep Parhar tid = GET_TID(cpl); 3454535e804SNavdeep Parhar if (is_ftid(iq->adapter, tid)) { 3464535e804SNavdeep Parhar /* 3474535e804SNavdeep Parhar * The return code for filter-write is put in the CPL cookie so 3484535e804SNavdeep Parhar * we have to rely on the hardware tid (is_ftid) to determine 3494535e804SNavdeep Parhar * that this is a response to a filter. 3504535e804SNavdeep Parhar */ 3514535e804SNavdeep Parhar cookie = CPL_COOKIE_FILTER; 3524535e804SNavdeep Parhar } else { 3534535e804SNavdeep Parhar cookie = G_COOKIE(cpl->cookie); 3544535e804SNavdeep Parhar } 3554535e804SNavdeep Parhar MPASS(cookie > CPL_COOKIE_RESERVED); 3564535e804SNavdeep Parhar MPASS(cookie < nitems(set_tcb_rpl_handlers)); 3574535e804SNavdeep Parhar 3584535e804SNavdeep Parhar return (set_tcb_rpl_handlers[cookie](iq, rss, m)); 359671bf2b8SNavdeep Parhar } 360671bf2b8SNavdeep Parhar 3614535e804SNavdeep Parhar static int 3624535e804SNavdeep Parhar l2t_write_rpl_handler(struct sge_iq *iq, const struct rss_header *rss, 3634535e804SNavdeep Parhar struct mbuf *m) 364671bf2b8SNavdeep Parhar { 3654535e804SNavdeep Parhar const struct cpl_l2t_write_rpl *rpl = (const void *)(rss + 1); 3664535e804SNavdeep Parhar unsigned int cookie; 367671bf2b8SNavdeep Parhar 3684535e804SNavdeep Parhar MPASS(m == NULL); 369671bf2b8SNavdeep Parhar 3704535e804SNavdeep Parhar cookie = GET_TID(rpl) & F_SYNC_WR ? CPL_COOKIE_TOM : CPL_COOKIE_FILTER; 3714535e804SNavdeep Parhar return (l2t_write_rpl_handlers[cookie](iq, rss, m)); 3724535e804SNavdeep Parhar } 373671bf2b8SNavdeep Parhar 374*111638bfSNavdeep Parhar static int 375*111638bfSNavdeep Parhar act_open_rpl_handler(struct sge_iq *iq, const struct rss_header *rss, 376*111638bfSNavdeep Parhar struct mbuf *m) 377*111638bfSNavdeep Parhar { 378*111638bfSNavdeep Parhar const struct cpl_act_open_rpl *cpl = (const void *)(rss + 1); 379*111638bfSNavdeep Parhar u_int cookie = G_TID_COOKIE(G_AOPEN_ATID(be32toh(cpl->atid_status))); 380*111638bfSNavdeep Parhar 381*111638bfSNavdeep Parhar MPASS(m == NULL); 382*111638bfSNavdeep Parhar MPASS(cookie != CPL_COOKIE_RESERVED); 383*111638bfSNavdeep Parhar 384*111638bfSNavdeep Parhar return (act_open_rpl_handlers[cookie](iq, rss, m)); 385*111638bfSNavdeep Parhar } 386*111638bfSNavdeep Parhar 3874535e804SNavdeep Parhar static void 3884535e804SNavdeep Parhar t4_init_shared_cpl_handlers(void) 3894535e804SNavdeep Parhar { 3904535e804SNavdeep Parhar 3914535e804SNavdeep Parhar t4_register_cpl_handler(CPL_SET_TCB_RPL, set_tcb_rpl_handler); 3924535e804SNavdeep Parhar t4_register_cpl_handler(CPL_L2T_WRITE_RPL, l2t_write_rpl_handler); 393*111638bfSNavdeep Parhar t4_register_cpl_handler(CPL_ACT_OPEN_RPL, act_open_rpl_handler); 3944535e804SNavdeep Parhar } 3954535e804SNavdeep Parhar 3964535e804SNavdeep Parhar void 3974535e804SNavdeep Parhar t4_register_shared_cpl_handler(int opcode, cpl_handler_t h, int cookie) 3984535e804SNavdeep Parhar { 3994535e804SNavdeep Parhar uintptr_t *loc; 4004535e804SNavdeep Parhar 4014535e804SNavdeep Parhar MPASS(opcode < nitems(t4_cpl_handler)); 4024535e804SNavdeep Parhar MPASS(cookie > CPL_COOKIE_RESERVED); 4034535e804SNavdeep Parhar MPASS(cookie < NUM_CPL_COOKIES); 4044535e804SNavdeep Parhar MPASS(t4_cpl_handler[opcode] != NULL); 4054535e804SNavdeep Parhar 4064535e804SNavdeep Parhar switch (opcode) { 4074535e804SNavdeep Parhar case CPL_SET_TCB_RPL: 4084535e804SNavdeep Parhar loc = (uintptr_t *)&set_tcb_rpl_handlers[cookie]; 4094535e804SNavdeep Parhar break; 4104535e804SNavdeep Parhar case CPL_L2T_WRITE_RPL: 4114535e804SNavdeep Parhar loc = (uintptr_t *)&l2t_write_rpl_handlers[cookie]; 4124535e804SNavdeep Parhar break; 413*111638bfSNavdeep Parhar case CPL_ACT_OPEN_RPL: 414*111638bfSNavdeep Parhar loc = (uintptr_t *)&act_open_rpl_handlers[cookie]; 415*111638bfSNavdeep Parhar break; 4164535e804SNavdeep Parhar default: 4174535e804SNavdeep Parhar MPASS(0); 4184535e804SNavdeep Parhar return; 4194535e804SNavdeep Parhar } 4204535e804SNavdeep Parhar MPASS(h == NULL || *loc == (uintptr_t)NULL); 4214535e804SNavdeep Parhar atomic_store_rel_ptr(loc, (uintptr_t)h); 422671bf2b8SNavdeep Parhar } 423671bf2b8SNavdeep Parhar 42494586193SNavdeep Parhar /* 4251458bff9SNavdeep Parhar * Called on MOD_LOAD. Validates and calculates the SGE tunables. 42694586193SNavdeep Parhar */ 42794586193SNavdeep Parhar void 42894586193SNavdeep Parhar t4_sge_modload(void) 42994586193SNavdeep Parhar { 4304defc81bSNavdeep Parhar 4319fb8886bSNavdeep Parhar if (fl_pktshift < 0 || fl_pktshift > 7) { 4329fb8886bSNavdeep Parhar printf("Invalid hw.cxgbe.fl_pktshift value (%d)," 4339fb8886bSNavdeep Parhar " using 2 instead.\n", fl_pktshift); 4349fb8886bSNavdeep Parhar fl_pktshift = 2; 4359fb8886bSNavdeep Parhar } 4369fb8886bSNavdeep Parhar 4379fb8886bSNavdeep Parhar if (spg_len != 64 && spg_len != 128) { 4389fb8886bSNavdeep Parhar int len; 4399fb8886bSNavdeep Parhar 4409fb8886bSNavdeep Parhar #if defined(__i386__) || defined(__amd64__) 4419fb8886bSNavdeep Parhar len = cpu_clflush_line_size > 64 ? 128 : 64; 4429fb8886bSNavdeep Parhar #else 4439fb8886bSNavdeep Parhar len = 64; 4449fb8886bSNavdeep Parhar #endif 4459fb8886bSNavdeep Parhar if (spg_len != -1) { 4469fb8886bSNavdeep Parhar printf("Invalid hw.cxgbe.spg_len value (%d)," 4479fb8886bSNavdeep Parhar " using %d instead.\n", spg_len, len); 4489fb8886bSNavdeep Parhar } 4499fb8886bSNavdeep Parhar spg_len = len; 4509fb8886bSNavdeep Parhar } 4519fb8886bSNavdeep Parhar 4529fb8886bSNavdeep Parhar if (cong_drop < -1 || cong_drop > 1) { 4539fb8886bSNavdeep Parhar printf("Invalid hw.cxgbe.cong_drop value (%d)," 4549fb8886bSNavdeep Parhar " using 0 instead.\n", cong_drop); 4559fb8886bSNavdeep Parhar cong_drop = 0; 4569fb8886bSNavdeep Parhar } 45782eff304SNavdeep Parhar 458d491f8caSNavdeep Parhar if (tscale != 1 && (tscale < 3 || tscale > 17)) { 459d491f8caSNavdeep Parhar printf("Invalid hw.cxgbe.tscale value (%d)," 460d491f8caSNavdeep Parhar " using 1 instead.\n", tscale); 461d491f8caSNavdeep Parhar tscale = 1; 462d491f8caSNavdeep Parhar } 463d491f8caSNavdeep Parhar 46482eff304SNavdeep Parhar extfree_refs = counter_u64_alloc(M_WAITOK); 46582eff304SNavdeep Parhar extfree_rels = counter_u64_alloc(M_WAITOK); 46682eff304SNavdeep Parhar counter_u64_zero(extfree_refs); 46782eff304SNavdeep Parhar counter_u64_zero(extfree_rels); 468671bf2b8SNavdeep Parhar 4694535e804SNavdeep Parhar t4_init_shared_cpl_handlers(); 470671bf2b8SNavdeep Parhar t4_register_cpl_handler(CPL_FW4_MSG, handle_fw_msg); 471671bf2b8SNavdeep Parhar t4_register_cpl_handler(CPL_FW6_MSG, handle_fw_msg); 472671bf2b8SNavdeep Parhar t4_register_cpl_handler(CPL_SGE_EGR_UPDATE, handle_sge_egr_update); 473671bf2b8SNavdeep Parhar t4_register_cpl_handler(CPL_RX_PKT, t4_eth_rx); 474671bf2b8SNavdeep Parhar t4_register_fw_msg_handler(FW6_TYPE_CMD_RPL, t4_handle_fw_rpl); 475069af0ebSJohn Baldwin t4_register_fw_msg_handler(FW6_TYPE_WRERR_RPL, t4_handle_wrerr_rpl); 47682eff304SNavdeep Parhar } 47782eff304SNavdeep Parhar 47882eff304SNavdeep Parhar void 47982eff304SNavdeep Parhar t4_sge_modunload(void) 48082eff304SNavdeep Parhar { 48182eff304SNavdeep Parhar 48282eff304SNavdeep Parhar counter_u64_free(extfree_refs); 48382eff304SNavdeep Parhar counter_u64_free(extfree_rels); 48482eff304SNavdeep Parhar } 48582eff304SNavdeep Parhar 48682eff304SNavdeep Parhar uint64_t 48782eff304SNavdeep Parhar t4_sge_extfree_refs(void) 48882eff304SNavdeep Parhar { 48982eff304SNavdeep Parhar uint64_t refs, rels; 49082eff304SNavdeep Parhar 49182eff304SNavdeep Parhar rels = counter_u64_fetch(extfree_rels); 49282eff304SNavdeep Parhar refs = counter_u64_fetch(extfree_refs); 49382eff304SNavdeep Parhar 49482eff304SNavdeep Parhar return (refs - rels); 49594586193SNavdeep Parhar } 49694586193SNavdeep Parhar 497e3207e19SNavdeep Parhar static inline void 498e3207e19SNavdeep Parhar setup_pad_and_pack_boundaries(struct adapter *sc) 499e3207e19SNavdeep Parhar { 500e3207e19SNavdeep Parhar uint32_t v, m; 5010dbc6cfdSNavdeep Parhar int pad, pack, pad_shift; 502e3207e19SNavdeep Parhar 5030dbc6cfdSNavdeep Parhar pad_shift = chip_id(sc) > CHELSIO_T5 ? X_T6_INGPADBOUNDARY_SHIFT : 5040dbc6cfdSNavdeep Parhar X_INGPADBOUNDARY_SHIFT; 505e3207e19SNavdeep Parhar pad = fl_pad; 5060dbc6cfdSNavdeep Parhar if (fl_pad < (1 << pad_shift) || 5070dbc6cfdSNavdeep Parhar fl_pad > (1 << (pad_shift + M_INGPADBOUNDARY)) || 5080dbc6cfdSNavdeep Parhar !powerof2(fl_pad)) { 509e3207e19SNavdeep Parhar /* 510e3207e19SNavdeep Parhar * If there is any chance that we might use buffer packing and 511e3207e19SNavdeep Parhar * the chip is a T4, then pick 64 as the pad/pack boundary. Set 5120dbc6cfdSNavdeep Parhar * it to the minimum allowed in all other cases. 513e3207e19SNavdeep Parhar */ 5140dbc6cfdSNavdeep Parhar pad = is_t4(sc) && buffer_packing ? 64 : 1 << pad_shift; 515e3207e19SNavdeep Parhar 516e3207e19SNavdeep Parhar /* 517e3207e19SNavdeep Parhar * For fl_pad = 0 we'll still write a reasonable value to the 518e3207e19SNavdeep Parhar * register but all the freelists will opt out of padding. 519e3207e19SNavdeep Parhar * We'll complain here only if the user tried to set it to a 520e3207e19SNavdeep Parhar * value greater than 0 that was invalid. 521e3207e19SNavdeep Parhar */ 522e3207e19SNavdeep Parhar if (fl_pad > 0) { 523e3207e19SNavdeep Parhar device_printf(sc->dev, "Invalid hw.cxgbe.fl_pad value" 524e3207e19SNavdeep Parhar " (%d), using %d instead.\n", fl_pad, pad); 525e3207e19SNavdeep Parhar } 526e3207e19SNavdeep Parhar } 527e3207e19SNavdeep Parhar m = V_INGPADBOUNDARY(M_INGPADBOUNDARY); 5280dbc6cfdSNavdeep Parhar v = V_INGPADBOUNDARY(ilog2(pad) - pad_shift); 529e3207e19SNavdeep Parhar t4_set_reg_field(sc, A_SGE_CONTROL, m, v); 530e3207e19SNavdeep Parhar 531e3207e19SNavdeep Parhar if (is_t4(sc)) { 532e3207e19SNavdeep Parhar if (fl_pack != -1 && fl_pack != pad) { 533e3207e19SNavdeep Parhar /* Complain but carry on. */ 534e3207e19SNavdeep Parhar device_printf(sc->dev, "hw.cxgbe.fl_pack (%d) ignored," 535e3207e19SNavdeep Parhar " using %d instead.\n", fl_pack, pad); 536e3207e19SNavdeep Parhar } 537e3207e19SNavdeep Parhar return; 538e3207e19SNavdeep Parhar } 539e3207e19SNavdeep Parhar 540e3207e19SNavdeep Parhar pack = fl_pack; 541e3207e19SNavdeep Parhar if (fl_pack < 16 || fl_pack == 32 || fl_pack > 4096 || 542e3207e19SNavdeep Parhar !powerof2(fl_pack)) { 543e3207e19SNavdeep Parhar pack = max(sc->params.pci.mps, CACHE_LINE_SIZE); 544e3207e19SNavdeep Parhar MPASS(powerof2(pack)); 545e3207e19SNavdeep Parhar if (pack < 16) 546e3207e19SNavdeep Parhar pack = 16; 547e3207e19SNavdeep Parhar if (pack == 32) 548e3207e19SNavdeep Parhar pack = 64; 549e3207e19SNavdeep Parhar if (pack > 4096) 550e3207e19SNavdeep Parhar pack = 4096; 551e3207e19SNavdeep Parhar if (fl_pack != -1) { 552e3207e19SNavdeep Parhar device_printf(sc->dev, "Invalid hw.cxgbe.fl_pack value" 553e3207e19SNavdeep Parhar " (%d), using %d instead.\n", fl_pack, pack); 554e3207e19SNavdeep Parhar } 555e3207e19SNavdeep Parhar } 556e3207e19SNavdeep Parhar m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY); 557e3207e19SNavdeep Parhar if (pack == 16) 558e3207e19SNavdeep Parhar v = V_INGPACKBOUNDARY(0); 559e3207e19SNavdeep Parhar else 560e3207e19SNavdeep Parhar v = V_INGPACKBOUNDARY(ilog2(pack) - 5); 561e3207e19SNavdeep Parhar 562e3207e19SNavdeep Parhar MPASS(!is_t4(sc)); /* T4 doesn't have SGE_CONTROL2 */ 563e3207e19SNavdeep Parhar t4_set_reg_field(sc, A_SGE_CONTROL2, m, v); 564e3207e19SNavdeep Parhar } 565e3207e19SNavdeep Parhar 566cf738022SNavdeep Parhar /* 567cf738022SNavdeep Parhar * adap->params.vpd.cclk must be set up before this is called. 568cf738022SNavdeep Parhar */ 569d14b0ac1SNavdeep Parhar void 570d14b0ac1SNavdeep Parhar t4_tweak_chip_settings(struct adapter *sc) 571d14b0ac1SNavdeep Parhar { 572d14b0ac1SNavdeep Parhar int i; 573d14b0ac1SNavdeep Parhar uint32_t v, m; 574d14b0ac1SNavdeep Parhar int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200}; 575cf738022SNavdeep Parhar int timer_max = M_TIMERVALUE0 * 1000 / sc->params.vpd.cclk; 576d14b0ac1SNavdeep Parhar int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */ 577d14b0ac1SNavdeep Parhar uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 57838035ed6SNavdeep Parhar static int sge_flbuf_sizes[] = { 5791458bff9SNavdeep Parhar MCLBYTES, 5801458bff9SNavdeep Parhar #if MJUMPAGESIZE != MCLBYTES 5811458bff9SNavdeep Parhar MJUMPAGESIZE, 58238035ed6SNavdeep Parhar MJUMPAGESIZE - CL_METADATA_SIZE, 58338035ed6SNavdeep Parhar MJUMPAGESIZE - 2 * MSIZE - CL_METADATA_SIZE, 5841458bff9SNavdeep Parhar #endif 5851458bff9SNavdeep Parhar MJUM9BYTES, 5861458bff9SNavdeep Parhar MJUM16BYTES, 58738035ed6SNavdeep Parhar MCLBYTES - MSIZE - CL_METADATA_SIZE, 58838035ed6SNavdeep Parhar MJUM9BYTES - CL_METADATA_SIZE, 58938035ed6SNavdeep Parhar MJUM16BYTES - CL_METADATA_SIZE, 5901458bff9SNavdeep Parhar }; 591d14b0ac1SNavdeep Parhar 592d14b0ac1SNavdeep Parhar KASSERT(sc->flags & MASTER_PF, 593d14b0ac1SNavdeep Parhar ("%s: trying to change chip settings when not master.", __func__)); 594d14b0ac1SNavdeep Parhar 5951458bff9SNavdeep Parhar m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE; 596d14b0ac1SNavdeep Parhar v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE | 5974defc81bSNavdeep Parhar V_EGRSTATUSPAGESIZE(spg_len == 128); 598d14b0ac1SNavdeep Parhar t4_set_reg_field(sc, A_SGE_CONTROL, m, v); 59954e4ee71SNavdeep Parhar 600e3207e19SNavdeep Parhar setup_pad_and_pack_boundaries(sc); 6011458bff9SNavdeep Parhar 602d14b0ac1SNavdeep Parhar v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) | 603733b9277SNavdeep Parhar V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) | 604733b9277SNavdeep Parhar V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) | 605733b9277SNavdeep Parhar V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) | 606733b9277SNavdeep Parhar V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) | 607733b9277SNavdeep Parhar V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) | 608733b9277SNavdeep Parhar V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) | 609733b9277SNavdeep Parhar V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10); 610d14b0ac1SNavdeep Parhar t4_write_reg(sc, A_SGE_HOST_PAGE_SIZE, v); 611733b9277SNavdeep Parhar 61238035ed6SNavdeep Parhar KASSERT(nitems(sge_flbuf_sizes) <= SGE_FLBUF_SIZES, 61338035ed6SNavdeep Parhar ("%s: hw buffer size table too big", __func__)); 61438035ed6SNavdeep Parhar for (i = 0; i < min(nitems(sge_flbuf_sizes), SGE_FLBUF_SIZES); i++) { 61554e4ee71SNavdeep Parhar t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0 + (4 * i), 61638035ed6SNavdeep Parhar sge_flbuf_sizes[i]); 61754e4ee71SNavdeep Parhar } 61854e4ee71SNavdeep Parhar 619d14b0ac1SNavdeep Parhar v = V_THRESHOLD_0(intr_pktcount[0]) | V_THRESHOLD_1(intr_pktcount[1]) | 620d14b0ac1SNavdeep Parhar V_THRESHOLD_2(intr_pktcount[2]) | V_THRESHOLD_3(intr_pktcount[3]); 621d14b0ac1SNavdeep Parhar t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD, v); 62254e4ee71SNavdeep Parhar 623cf738022SNavdeep Parhar KASSERT(intr_timer[0] <= timer_max, 624cf738022SNavdeep Parhar ("%s: not a single usable timer (%d, %d)", __func__, intr_timer[0], 625cf738022SNavdeep Parhar timer_max)); 626cf738022SNavdeep Parhar for (i = 1; i < nitems(intr_timer); i++) { 627cf738022SNavdeep Parhar KASSERT(intr_timer[i] >= intr_timer[i - 1], 628cf738022SNavdeep Parhar ("%s: timers not listed in increasing order (%d)", 629cf738022SNavdeep Parhar __func__, i)); 630cf738022SNavdeep Parhar 631cf738022SNavdeep Parhar while (intr_timer[i] > timer_max) { 632cf738022SNavdeep Parhar if (i == nitems(intr_timer) - 1) { 633cf738022SNavdeep Parhar intr_timer[i] = timer_max; 634cf738022SNavdeep Parhar break; 635cf738022SNavdeep Parhar } 636cf738022SNavdeep Parhar intr_timer[i] += intr_timer[i - 1]; 637cf738022SNavdeep Parhar intr_timer[i] /= 2; 638cf738022SNavdeep Parhar } 639cf738022SNavdeep Parhar } 640cf738022SNavdeep Parhar 641d14b0ac1SNavdeep Parhar v = V_TIMERVALUE0(us_to_core_ticks(sc, intr_timer[0])) | 642d14b0ac1SNavdeep Parhar V_TIMERVALUE1(us_to_core_ticks(sc, intr_timer[1])); 643d14b0ac1SNavdeep Parhar t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1, v); 644d14b0ac1SNavdeep Parhar v = V_TIMERVALUE2(us_to_core_ticks(sc, intr_timer[2])) | 645d14b0ac1SNavdeep Parhar V_TIMERVALUE3(us_to_core_ticks(sc, intr_timer[3])); 646d14b0ac1SNavdeep Parhar t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3, v); 647d14b0ac1SNavdeep Parhar v = V_TIMERVALUE4(us_to_core_ticks(sc, intr_timer[4])) | 648d14b0ac1SNavdeep Parhar V_TIMERVALUE5(us_to_core_ticks(sc, intr_timer[5])); 649d14b0ac1SNavdeep Parhar t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5, v); 65086e02bf2SNavdeep Parhar 651d491f8caSNavdeep Parhar if (chip_id(sc) >= CHELSIO_T6) { 652d491f8caSNavdeep Parhar m = V_TSCALE(M_TSCALE); 653d491f8caSNavdeep Parhar if (tscale == 1) 654d491f8caSNavdeep Parhar v = 0; 655d491f8caSNavdeep Parhar else 656d491f8caSNavdeep Parhar v = V_TSCALE(tscale - 2); 657d491f8caSNavdeep Parhar t4_set_reg_field(sc, A_SGE_ITP_CONTROL, m, v); 6582f318252SNavdeep Parhar 6592f318252SNavdeep Parhar if (sc->debug_flags & DF_DISABLE_TCB_CACHE) { 6602f318252SNavdeep Parhar m = V_RDTHRESHOLD(M_RDTHRESHOLD) | F_WRTHRTHRESHEN | 6612f318252SNavdeep Parhar V_WRTHRTHRESH(M_WRTHRTHRESH); 6622f318252SNavdeep Parhar t4_tp_pio_read(sc, &v, 1, A_TP_CMM_CONFIG, 1); 6632f318252SNavdeep Parhar v &= ~m; 6642f318252SNavdeep Parhar v |= V_RDTHRESHOLD(1) | F_WRTHRTHRESHEN | 6652f318252SNavdeep Parhar V_WRTHRTHRESH(16); 6662f318252SNavdeep Parhar t4_tp_pio_write(sc, &v, 1, A_TP_CMM_CONFIG, 1); 6672f318252SNavdeep Parhar } 668d491f8caSNavdeep Parhar } 669d491f8caSNavdeep Parhar 6707cba15b1SNavdeep Parhar /* 4K, 16K, 64K, 256K DDP "page sizes" for TDDP */ 671d14b0ac1SNavdeep Parhar v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 672d14b0ac1SNavdeep Parhar t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, v); 673d14b0ac1SNavdeep Parhar 6747cba15b1SNavdeep Parhar /* 6757cba15b1SNavdeep Parhar * 4K, 8K, 16K, 64K DDP "page sizes" for iSCSI DDP. These have been 6767cba15b1SNavdeep Parhar * chosen with MAXPHYS = 128K in mind. The largest DDP buffer that we 6777cba15b1SNavdeep Parhar * may have to deal with is MAXPHYS + 1 page. 6787cba15b1SNavdeep Parhar */ 6797cba15b1SNavdeep Parhar v = V_HPZ0(0) | V_HPZ1(1) | V_HPZ2(2) | V_HPZ3(4); 6807cba15b1SNavdeep Parhar t4_write_reg(sc, A_ULP_RX_ISCSI_PSZ, v); 6817cba15b1SNavdeep Parhar 6827cba15b1SNavdeep Parhar /* We use multiple DDP page sizes both in plain-TOE and ISCSI modes. */ 6837cba15b1SNavdeep Parhar m = v = F_TDDPTAGTCB | F_ISCSITAGTCB; 684d14b0ac1SNavdeep Parhar t4_set_reg_field(sc, A_ULP_RX_CTL, m, v); 685d14b0ac1SNavdeep Parhar 686d14b0ac1SNavdeep Parhar m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 687d14b0ac1SNavdeep Parhar F_RESETDDPOFFSET; 688d14b0ac1SNavdeep Parhar v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 689d14b0ac1SNavdeep Parhar t4_set_reg_field(sc, A_TP_PARA_REG5, m, v); 690d14b0ac1SNavdeep Parhar } 691d14b0ac1SNavdeep Parhar 692d14b0ac1SNavdeep Parhar /* 693e3207e19SNavdeep Parhar * SGE wants the buffer to be at least 64B and then a multiple of 16. If 6948f6690d3SJohn Baldwin * padding is in use, the buffer's start and end need to be aligned to the pad 695b741402cSNavdeep Parhar * boundary as well. We'll just make sure that the size is a multiple of the 696b741402cSNavdeep Parhar * boundary here, it is up to the buffer allocation code to make sure the start 697b741402cSNavdeep Parhar * of the buffer is aligned as well. 69838035ed6SNavdeep Parhar */ 69938035ed6SNavdeep Parhar static inline int 700e3207e19SNavdeep Parhar hwsz_ok(struct adapter *sc, int hwsz) 70138035ed6SNavdeep Parhar { 70290e7434aSNavdeep Parhar int mask = fl_pad ? sc->params.sge.pad_boundary - 1 : 16 - 1; 70338035ed6SNavdeep Parhar 704b741402cSNavdeep Parhar return (hwsz >= 64 && (hwsz & mask) == 0); 70538035ed6SNavdeep Parhar } 70638035ed6SNavdeep Parhar 70738035ed6SNavdeep Parhar /* 708d14b0ac1SNavdeep Parhar * XXX: driver really should be able to deal with unexpected settings. 709d14b0ac1SNavdeep Parhar */ 710d14b0ac1SNavdeep Parhar int 711d14b0ac1SNavdeep Parhar t4_read_chip_settings(struct adapter *sc) 712d14b0ac1SNavdeep Parhar { 713d14b0ac1SNavdeep Parhar struct sge *s = &sc->sge; 71490e7434aSNavdeep Parhar struct sge_params *sp = &sc->params.sge; 7151458bff9SNavdeep Parhar int i, j, n, rc = 0; 716d14b0ac1SNavdeep Parhar uint32_t m, v, r; 717d14b0ac1SNavdeep Parhar uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 71838035ed6SNavdeep Parhar static int sw_buf_sizes[] = { /* Sorted by size */ 7191458bff9SNavdeep Parhar MCLBYTES, 7201458bff9SNavdeep Parhar #if MJUMPAGESIZE != MCLBYTES 7211458bff9SNavdeep Parhar MJUMPAGESIZE, 7221458bff9SNavdeep Parhar #endif 7231458bff9SNavdeep Parhar MJUM9BYTES, 7241458bff9SNavdeep Parhar MJUM16BYTES 7251458bff9SNavdeep Parhar }; 72638035ed6SNavdeep Parhar struct sw_zone_info *swz, *safe_swz; 72738035ed6SNavdeep Parhar struct hw_buf_info *hwb; 728d14b0ac1SNavdeep Parhar 72990e7434aSNavdeep Parhar m = F_RXPKTCPLMODE; 73090e7434aSNavdeep Parhar v = F_RXPKTCPLMODE; 73159c1e950SJohn Baldwin r = sc->params.sge.sge_control; 732d14b0ac1SNavdeep Parhar if ((r & m) != v) { 733d14b0ac1SNavdeep Parhar device_printf(sc->dev, "invalid SGE_CONTROL(0x%x)\n", r); 734733b9277SNavdeep Parhar rc = EINVAL; 735733b9277SNavdeep Parhar } 736733b9277SNavdeep Parhar 73790e7434aSNavdeep Parhar /* 73890e7434aSNavdeep Parhar * If this changes then every single use of PAGE_SHIFT in the driver 73990e7434aSNavdeep Parhar * needs to be carefully reviewed for PAGE_SHIFT vs sp->page_shift. 74090e7434aSNavdeep Parhar */ 74190e7434aSNavdeep Parhar if (sp->page_shift != PAGE_SHIFT) { 742d14b0ac1SNavdeep Parhar device_printf(sc->dev, "invalid SGE_HOST_PAGE_SIZE(0x%x)\n", r); 743733b9277SNavdeep Parhar rc = EINVAL; 744733b9277SNavdeep Parhar } 745733b9277SNavdeep Parhar 74638035ed6SNavdeep Parhar /* Filter out unusable hw buffer sizes entirely (mark with -2). */ 74738035ed6SNavdeep Parhar hwb = &s->hw_buf_info[0]; 74838035ed6SNavdeep Parhar for (i = 0; i < nitems(s->hw_buf_info); i++, hwb++) { 74959c1e950SJohn Baldwin r = sc->params.sge.sge_fl_buffer_size[i]; 75038035ed6SNavdeep Parhar hwb->size = r; 751e3207e19SNavdeep Parhar hwb->zidx = hwsz_ok(sc, r) ? -1 : -2; 75238035ed6SNavdeep Parhar hwb->next = -1; 7531458bff9SNavdeep Parhar } 75438035ed6SNavdeep Parhar 75538035ed6SNavdeep Parhar /* 75638035ed6SNavdeep Parhar * Create a sorted list in decreasing order of hw buffer sizes (and so 75738035ed6SNavdeep Parhar * increasing order of spare area) for each software zone. 758e3207e19SNavdeep Parhar * 759e3207e19SNavdeep Parhar * If padding is enabled then the start and end of the buffer must align 760e3207e19SNavdeep Parhar * to the pad boundary; if packing is enabled then they must align with 761e3207e19SNavdeep Parhar * the pack boundary as well. Allocations from the cluster zones are 762e3207e19SNavdeep Parhar * aligned to min(size, 4K), so the buffer starts at that alignment and 763e3207e19SNavdeep Parhar * ends at hwb->size alignment. If mbuf inlining is allowed the 764e3207e19SNavdeep Parhar * starting alignment will be reduced to MSIZE and the driver will 765e3207e19SNavdeep Parhar * exercise appropriate caution when deciding on the best buffer layout 766e3207e19SNavdeep Parhar * to use. 76738035ed6SNavdeep Parhar */ 76838035ed6SNavdeep Parhar n = 0; /* no usable buffer size to begin with */ 76938035ed6SNavdeep Parhar swz = &s->sw_zone_info[0]; 77038035ed6SNavdeep Parhar safe_swz = NULL; 77138035ed6SNavdeep Parhar for (i = 0; i < SW_ZONE_SIZES; i++, swz++) { 77238035ed6SNavdeep Parhar int8_t head = -1, tail = -1; 77338035ed6SNavdeep Parhar 77438035ed6SNavdeep Parhar swz->size = sw_buf_sizes[i]; 77538035ed6SNavdeep Parhar swz->zone = m_getzone(swz->size); 77638035ed6SNavdeep Parhar swz->type = m_gettype(swz->size); 77738035ed6SNavdeep Parhar 778e3207e19SNavdeep Parhar if (swz->size < PAGE_SIZE) { 779e3207e19SNavdeep Parhar MPASS(powerof2(swz->size)); 78090e7434aSNavdeep Parhar if (fl_pad && (swz->size % sp->pad_boundary != 0)) 781e3207e19SNavdeep Parhar continue; 782e3207e19SNavdeep Parhar } 783e3207e19SNavdeep Parhar 78438035ed6SNavdeep Parhar if (swz->size == safest_rx_cluster) 78538035ed6SNavdeep Parhar safe_swz = swz; 78638035ed6SNavdeep Parhar 78738035ed6SNavdeep Parhar hwb = &s->hw_buf_info[0]; 78838035ed6SNavdeep Parhar for (j = 0; j < SGE_FLBUF_SIZES; j++, hwb++) { 78938035ed6SNavdeep Parhar if (hwb->zidx != -1 || hwb->size > swz->size) 7901458bff9SNavdeep Parhar continue; 791e3207e19SNavdeep Parhar #ifdef INVARIANTS 792e3207e19SNavdeep Parhar if (fl_pad) 79390e7434aSNavdeep Parhar MPASS(hwb->size % sp->pad_boundary == 0); 794e3207e19SNavdeep Parhar #endif 79538035ed6SNavdeep Parhar hwb->zidx = i; 79638035ed6SNavdeep Parhar if (head == -1) 79738035ed6SNavdeep Parhar head = tail = j; 79838035ed6SNavdeep Parhar else if (hwb->size < s->hw_buf_info[tail].size) { 79938035ed6SNavdeep Parhar s->hw_buf_info[tail].next = j; 80038035ed6SNavdeep Parhar tail = j; 80138035ed6SNavdeep Parhar } else { 80238035ed6SNavdeep Parhar int8_t *cur; 80338035ed6SNavdeep Parhar struct hw_buf_info *t; 80438035ed6SNavdeep Parhar 80538035ed6SNavdeep Parhar for (cur = &head; *cur != -1; cur = &t->next) { 80638035ed6SNavdeep Parhar t = &s->hw_buf_info[*cur]; 80738035ed6SNavdeep Parhar if (hwb->size == t->size) { 80838035ed6SNavdeep Parhar hwb->zidx = -2; 8091458bff9SNavdeep Parhar break; 8101458bff9SNavdeep Parhar } 81138035ed6SNavdeep Parhar if (hwb->size > t->size) { 81238035ed6SNavdeep Parhar hwb->next = *cur; 81338035ed6SNavdeep Parhar *cur = j; 81438035ed6SNavdeep Parhar break; 81538035ed6SNavdeep Parhar } 81638035ed6SNavdeep Parhar } 81738035ed6SNavdeep Parhar } 81838035ed6SNavdeep Parhar } 81938035ed6SNavdeep Parhar swz->head_hwidx = head; 82038035ed6SNavdeep Parhar swz->tail_hwidx = tail; 82138035ed6SNavdeep Parhar 82238035ed6SNavdeep Parhar if (tail != -1) { 82338035ed6SNavdeep Parhar n++; 82438035ed6SNavdeep Parhar if (swz->size - s->hw_buf_info[tail].size >= 82538035ed6SNavdeep Parhar CL_METADATA_SIZE) 82638035ed6SNavdeep Parhar sc->flags |= BUF_PACKING_OK; 82738035ed6SNavdeep Parhar } 8281458bff9SNavdeep Parhar } 8291458bff9SNavdeep Parhar if (n == 0) { 8301458bff9SNavdeep Parhar device_printf(sc->dev, "no usable SGE FL buffer size.\n"); 8311458bff9SNavdeep Parhar rc = EINVAL; 832733b9277SNavdeep Parhar } 83338035ed6SNavdeep Parhar 83438035ed6SNavdeep Parhar s->safe_hwidx1 = -1; 83538035ed6SNavdeep Parhar s->safe_hwidx2 = -1; 83638035ed6SNavdeep Parhar if (safe_swz != NULL) { 83738035ed6SNavdeep Parhar s->safe_hwidx1 = safe_swz->head_hwidx; 83838035ed6SNavdeep Parhar for (i = safe_swz->head_hwidx; i != -1; i = hwb->next) { 83938035ed6SNavdeep Parhar int spare; 84038035ed6SNavdeep Parhar 84138035ed6SNavdeep Parhar hwb = &s->hw_buf_info[i]; 842e3207e19SNavdeep Parhar #ifdef INVARIANTS 843e3207e19SNavdeep Parhar if (fl_pad) 84490e7434aSNavdeep Parhar MPASS(hwb->size % sp->pad_boundary == 0); 845e3207e19SNavdeep Parhar #endif 84638035ed6SNavdeep Parhar spare = safe_swz->size - hwb->size; 847e3207e19SNavdeep Parhar if (spare >= CL_METADATA_SIZE) { 84838035ed6SNavdeep Parhar s->safe_hwidx2 = i; 84938035ed6SNavdeep Parhar break; 85038035ed6SNavdeep Parhar } 85138035ed6SNavdeep Parhar } 852e3207e19SNavdeep Parhar } 853733b9277SNavdeep Parhar 8546af45170SJohn Baldwin if (sc->flags & IS_VF) 8556af45170SJohn Baldwin return (0); 8566af45170SJohn Baldwin 857d14b0ac1SNavdeep Parhar v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 858d14b0ac1SNavdeep Parhar r = t4_read_reg(sc, A_ULP_RX_TDDP_PSZ); 859d14b0ac1SNavdeep Parhar if (r != v) { 860d14b0ac1SNavdeep Parhar device_printf(sc->dev, "invalid ULP_RX_TDDP_PSZ(0x%x)\n", r); 861d14b0ac1SNavdeep Parhar rc = EINVAL; 862d14b0ac1SNavdeep Parhar } 863733b9277SNavdeep Parhar 864d14b0ac1SNavdeep Parhar m = v = F_TDDPTAGTCB; 865d14b0ac1SNavdeep Parhar r = t4_read_reg(sc, A_ULP_RX_CTL); 866d14b0ac1SNavdeep Parhar if ((r & m) != v) { 867d14b0ac1SNavdeep Parhar device_printf(sc->dev, "invalid ULP_RX_CTL(0x%x)\n", r); 868d14b0ac1SNavdeep Parhar rc = EINVAL; 869d14b0ac1SNavdeep Parhar } 870d14b0ac1SNavdeep Parhar 871d14b0ac1SNavdeep Parhar m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 872d14b0ac1SNavdeep Parhar F_RESETDDPOFFSET; 873d14b0ac1SNavdeep Parhar v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 874d14b0ac1SNavdeep Parhar r = t4_read_reg(sc, A_TP_PARA_REG5); 875d14b0ac1SNavdeep Parhar if ((r & m) != v) { 876d14b0ac1SNavdeep Parhar device_printf(sc->dev, "invalid TP_PARA_REG5(0x%x)\n", r); 877d14b0ac1SNavdeep Parhar rc = EINVAL; 878d14b0ac1SNavdeep Parhar } 879d14b0ac1SNavdeep Parhar 880c45b1868SNavdeep Parhar t4_init_tp_params(sc, 1); 881d14b0ac1SNavdeep Parhar 882d14b0ac1SNavdeep Parhar t4_read_mtu_tbl(sc, sc->params.mtus, NULL); 883d14b0ac1SNavdeep Parhar t4_load_mtus(sc, sc->params.mtus, sc->params.a_wnd, sc->params.b_wnd); 884d14b0ac1SNavdeep Parhar 885733b9277SNavdeep Parhar return (rc); 88654e4ee71SNavdeep Parhar } 88754e4ee71SNavdeep Parhar 88854e4ee71SNavdeep Parhar int 88954e4ee71SNavdeep Parhar t4_create_dma_tag(struct adapter *sc) 89054e4ee71SNavdeep Parhar { 89154e4ee71SNavdeep Parhar int rc; 89254e4ee71SNavdeep Parhar 89354e4ee71SNavdeep Parhar rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0, 89454e4ee71SNavdeep Parhar BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE, 89554e4ee71SNavdeep Parhar BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL, 89654e4ee71SNavdeep Parhar NULL, &sc->dmat); 89754e4ee71SNavdeep Parhar if (rc != 0) { 89854e4ee71SNavdeep Parhar device_printf(sc->dev, 89954e4ee71SNavdeep Parhar "failed to create main DMA tag: %d\n", rc); 90054e4ee71SNavdeep Parhar } 90154e4ee71SNavdeep Parhar 90254e4ee71SNavdeep Parhar return (rc); 90354e4ee71SNavdeep Parhar } 90454e4ee71SNavdeep Parhar 9056e22f9f3SNavdeep Parhar void 9066e22f9f3SNavdeep Parhar t4_sge_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx, 9076e22f9f3SNavdeep Parhar struct sysctl_oid_list *children) 9086e22f9f3SNavdeep Parhar { 90990e7434aSNavdeep Parhar struct sge_params *sp = &sc->params.sge; 9106e22f9f3SNavdeep Parhar 91138035ed6SNavdeep Parhar SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "buffer_sizes", 91238035ed6SNavdeep Parhar CTLTYPE_STRING | CTLFLAG_RD, &sc->sge, 0, sysctl_bufsizes, "A", 91338035ed6SNavdeep Parhar "freelist buffer sizes"); 91438035ed6SNavdeep Parhar 9156e22f9f3SNavdeep Parhar SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pktshift", CTLFLAG_RD, 91690e7434aSNavdeep Parhar NULL, sp->fl_pktshift, "payload DMA offset in rx buffer (bytes)"); 9176e22f9f3SNavdeep Parhar 9186e22f9f3SNavdeep Parhar SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pad", CTLFLAG_RD, 91990e7434aSNavdeep Parhar NULL, sp->pad_boundary, "payload pad boundary (bytes)"); 9206e22f9f3SNavdeep Parhar 9216e22f9f3SNavdeep Parhar SYSCTL_ADD_INT(ctx, children, OID_AUTO, "spg_len", CTLFLAG_RD, 92290e7434aSNavdeep Parhar NULL, sp->spg_len, "status page size (bytes)"); 9236e22f9f3SNavdeep Parhar 9246e22f9f3SNavdeep Parhar SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_drop", CTLFLAG_RD, 9256e22f9f3SNavdeep Parhar NULL, cong_drop, "congestion drop setting"); 9261458bff9SNavdeep Parhar 9271458bff9SNavdeep Parhar SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pack", CTLFLAG_RD, 92890e7434aSNavdeep Parhar NULL, sp->pack_boundary, "payload pack boundary (bytes)"); 9296e22f9f3SNavdeep Parhar } 9306e22f9f3SNavdeep Parhar 93154e4ee71SNavdeep Parhar int 93254e4ee71SNavdeep Parhar t4_destroy_dma_tag(struct adapter *sc) 93354e4ee71SNavdeep Parhar { 93454e4ee71SNavdeep Parhar if (sc->dmat) 93554e4ee71SNavdeep Parhar bus_dma_tag_destroy(sc->dmat); 93654e4ee71SNavdeep Parhar 93754e4ee71SNavdeep Parhar return (0); 93854e4ee71SNavdeep Parhar } 93954e4ee71SNavdeep Parhar 94054e4ee71SNavdeep Parhar /* 941733b9277SNavdeep Parhar * Allocate and initialize the firmware event queue and the management queue. 94254e4ee71SNavdeep Parhar * 94354e4ee71SNavdeep Parhar * Returns errno on failure. Resources allocated up to that point may still be 94454e4ee71SNavdeep Parhar * allocated. Caller is responsible for cleanup in case this function fails. 94554e4ee71SNavdeep Parhar */ 94654e4ee71SNavdeep Parhar int 947f7dfe243SNavdeep Parhar t4_setup_adapter_queues(struct adapter *sc) 94854e4ee71SNavdeep Parhar { 949733b9277SNavdeep Parhar int rc; 95054e4ee71SNavdeep Parhar 95154e4ee71SNavdeep Parhar ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 95254e4ee71SNavdeep Parhar 953733b9277SNavdeep Parhar sysctl_ctx_init(&sc->ctx); 954733b9277SNavdeep Parhar sc->flags |= ADAP_SYSCTL_CTX; 95554e4ee71SNavdeep Parhar 95656599263SNavdeep Parhar /* 95756599263SNavdeep Parhar * Firmware event queue 95856599263SNavdeep Parhar */ 959733b9277SNavdeep Parhar rc = alloc_fwq(sc); 960aa95b653SNavdeep Parhar if (rc != 0) 961f7dfe243SNavdeep Parhar return (rc); 962f7dfe243SNavdeep Parhar 963f7dfe243SNavdeep Parhar /* 964733b9277SNavdeep Parhar * Management queue. This is just a control queue that uses the fwq as 965733b9277SNavdeep Parhar * its associated iq. 966f7dfe243SNavdeep Parhar */ 9676af45170SJohn Baldwin if (!(sc->flags & IS_VF)) 968733b9277SNavdeep Parhar rc = alloc_mgmtq(sc); 96954e4ee71SNavdeep Parhar 97054e4ee71SNavdeep Parhar return (rc); 97154e4ee71SNavdeep Parhar } 97254e4ee71SNavdeep Parhar 97354e4ee71SNavdeep Parhar /* 97454e4ee71SNavdeep Parhar * Idempotent 97554e4ee71SNavdeep Parhar */ 97654e4ee71SNavdeep Parhar int 977f7dfe243SNavdeep Parhar t4_teardown_adapter_queues(struct adapter *sc) 97854e4ee71SNavdeep Parhar { 97954e4ee71SNavdeep Parhar 98054e4ee71SNavdeep Parhar ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 98154e4ee71SNavdeep Parhar 982733b9277SNavdeep Parhar /* Do this before freeing the queue */ 983733b9277SNavdeep Parhar if (sc->flags & ADAP_SYSCTL_CTX) { 984f7dfe243SNavdeep Parhar sysctl_ctx_free(&sc->ctx); 985733b9277SNavdeep Parhar sc->flags &= ~ADAP_SYSCTL_CTX; 986f7dfe243SNavdeep Parhar } 987f7dfe243SNavdeep Parhar 988733b9277SNavdeep Parhar free_mgmtq(sc); 989733b9277SNavdeep Parhar free_fwq(sc); 99054e4ee71SNavdeep Parhar 99154e4ee71SNavdeep Parhar return (0); 99254e4ee71SNavdeep Parhar } 99354e4ee71SNavdeep Parhar 99438035ed6SNavdeep Parhar /* Maximum payload that can be delivered with a single iq descriptor */ 9958340ece5SNavdeep Parhar static inline int 99638035ed6SNavdeep Parhar mtu_to_max_payload(struct adapter *sc, int mtu, const int toe) 9978340ece5SNavdeep Parhar { 99838035ed6SNavdeep Parhar int payload; 9998340ece5SNavdeep Parhar 10006eb3180fSNavdeep Parhar #ifdef TCP_OFFLOAD 100138035ed6SNavdeep Parhar if (toe) { 10021131c927SNavdeep Parhar int rxcs = G_RXCOALESCESIZE(t4_read_reg(sc, A_TP_PARA_REG2)); 10031131c927SNavdeep Parhar 10041131c927SNavdeep Parhar /* Note that COP can set rx_coalesce on/off per connection. */ 10051131c927SNavdeep Parhar payload = max(mtu, rxcs); 100638035ed6SNavdeep Parhar } else { 100738035ed6SNavdeep Parhar #endif 100838035ed6SNavdeep Parhar /* large enough even when hw VLAN extraction is disabled */ 100990e7434aSNavdeep Parhar payload = sc->params.sge.fl_pktshift + ETHER_HDR_LEN + 101090e7434aSNavdeep Parhar ETHER_VLAN_ENCAP_LEN + mtu; 101138035ed6SNavdeep Parhar #ifdef TCP_OFFLOAD 10126eb3180fSNavdeep Parhar } 10136eb3180fSNavdeep Parhar #endif 101438035ed6SNavdeep Parhar 101538035ed6SNavdeep Parhar return (payload); 101638035ed6SNavdeep Parhar } 10176eb3180fSNavdeep Parhar 1018733b9277SNavdeep Parhar int 1019fe2ebb76SJohn Baldwin t4_setup_vi_queues(struct vi_info *vi) 1020733b9277SNavdeep Parhar { 1021f549e352SNavdeep Parhar int rc = 0, i, intr_idx, iqidx; 1022733b9277SNavdeep Parhar struct sge_rxq *rxq; 1023733b9277SNavdeep Parhar struct sge_txq *txq; 1024733b9277SNavdeep Parhar struct sge_wrq *ctrlq; 102509fe6320SNavdeep Parhar #ifdef TCP_OFFLOAD 1026733b9277SNavdeep Parhar struct sge_ofld_rxq *ofld_rxq; 1027733b9277SNavdeep Parhar struct sge_wrq *ofld_txq; 1028298d969cSNavdeep Parhar #endif 1029298d969cSNavdeep Parhar #ifdef DEV_NETMAP 103062291463SNavdeep Parhar int saved_idx; 1031298d969cSNavdeep Parhar struct sge_nm_rxq *nm_rxq; 1032298d969cSNavdeep Parhar struct sge_nm_txq *nm_txq; 1033733b9277SNavdeep Parhar #endif 1034733b9277SNavdeep Parhar char name[16]; 1035fe2ebb76SJohn Baldwin struct port_info *pi = vi->pi; 1036733b9277SNavdeep Parhar struct adapter *sc = pi->adapter; 1037fe2ebb76SJohn Baldwin struct ifnet *ifp = vi->ifp; 1038fe2ebb76SJohn Baldwin struct sysctl_oid *oid = device_get_sysctl_tree(vi->dev); 1039733b9277SNavdeep Parhar struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 1040e3207e19SNavdeep Parhar int maxp, mtu = ifp->if_mtu; 1041733b9277SNavdeep Parhar 1042733b9277SNavdeep Parhar /* Interrupt vector to start from (when using multiple vectors) */ 1043f549e352SNavdeep Parhar intr_idx = vi->first_intr; 1044fe2ebb76SJohn Baldwin 1045fe2ebb76SJohn Baldwin #ifdef DEV_NETMAP 104662291463SNavdeep Parhar saved_idx = intr_idx; 104762291463SNavdeep Parhar if (ifp->if_capabilities & IFCAP_NETMAP) { 104862291463SNavdeep Parhar 104962291463SNavdeep Parhar /* netmap is supported with direct interrupts only. */ 1050f549e352SNavdeep Parhar MPASS(!forwarding_intr_to_fwq(sc)); 105162291463SNavdeep Parhar 1052fe2ebb76SJohn Baldwin /* 1053fe2ebb76SJohn Baldwin * We don't have buffers to back the netmap rx queues 1054fe2ebb76SJohn Baldwin * right now so we create the queues in a way that 1055fe2ebb76SJohn Baldwin * doesn't set off any congestion signal in the chip. 1056fe2ebb76SJohn Baldwin */ 105762291463SNavdeep Parhar oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "nm_rxq", 1058fe2ebb76SJohn Baldwin CTLFLAG_RD, NULL, "rx queues"); 1059fe2ebb76SJohn Baldwin for_each_nm_rxq(vi, i, nm_rxq) { 1060fe2ebb76SJohn Baldwin rc = alloc_nm_rxq(vi, nm_rxq, intr_idx, i, oid); 1061fe2ebb76SJohn Baldwin if (rc != 0) 1062fe2ebb76SJohn Baldwin goto done; 1063fe2ebb76SJohn Baldwin intr_idx++; 1064fe2ebb76SJohn Baldwin } 1065fe2ebb76SJohn Baldwin 106662291463SNavdeep Parhar oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "nm_txq", 1067fe2ebb76SJohn Baldwin CTLFLAG_RD, NULL, "tx queues"); 1068fe2ebb76SJohn Baldwin for_each_nm_txq(vi, i, nm_txq) { 1069f549e352SNavdeep Parhar iqidx = vi->first_nm_rxq + (i % vi->nnmrxq); 1070f549e352SNavdeep Parhar rc = alloc_nm_txq(vi, nm_txq, iqidx, i, oid); 1071fe2ebb76SJohn Baldwin if (rc != 0) 1072fe2ebb76SJohn Baldwin goto done; 1073fe2ebb76SJohn Baldwin } 1074fe2ebb76SJohn Baldwin } 107562291463SNavdeep Parhar 107662291463SNavdeep Parhar /* Normal rx queues and netmap rx queues share the same interrupts. */ 107762291463SNavdeep Parhar intr_idx = saved_idx; 1078fe2ebb76SJohn Baldwin #endif 1079733b9277SNavdeep Parhar 1080733b9277SNavdeep Parhar /* 1081f549e352SNavdeep Parhar * Allocate rx queues first because a default iqid is required when 1082f549e352SNavdeep Parhar * creating a tx queue. 1083733b9277SNavdeep Parhar */ 108438035ed6SNavdeep Parhar maxp = mtu_to_max_payload(sc, mtu, 0); 1085fe2ebb76SJohn Baldwin oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "rxq", 1086298d969cSNavdeep Parhar CTLFLAG_RD, NULL, "rx queues"); 1087fe2ebb76SJohn Baldwin for_each_rxq(vi, i, rxq) { 108854e4ee71SNavdeep Parhar 1089fe2ebb76SJohn Baldwin init_iq(&rxq->iq, sc, vi->tmr_idx, vi->pktc_idx, vi->qsize_rxq); 109054e4ee71SNavdeep Parhar 109154e4ee71SNavdeep Parhar snprintf(name, sizeof(name), "%s rxq%d-fl", 1092fe2ebb76SJohn Baldwin device_get_nameunit(vi->dev), i); 1093fe2ebb76SJohn Baldwin init_fl(sc, &rxq->fl, vi->qsize_rxq / 8, maxp, name); 109454e4ee71SNavdeep Parhar 1095f549e352SNavdeep Parhar rc = alloc_rxq(vi, rxq, 1096f549e352SNavdeep Parhar forwarding_intr_to_fwq(sc) ? -1 : intr_idx, i, oid); 109754e4ee71SNavdeep Parhar if (rc != 0) 109854e4ee71SNavdeep Parhar goto done; 1099733b9277SNavdeep Parhar intr_idx++; 1100733b9277SNavdeep Parhar } 110162291463SNavdeep Parhar #ifdef DEV_NETMAP 110262291463SNavdeep Parhar if (ifp->if_capabilities & IFCAP_NETMAP) 110362291463SNavdeep Parhar intr_idx = saved_idx + max(vi->nrxq, vi->nnmrxq); 110462291463SNavdeep Parhar #endif 110509fe6320SNavdeep Parhar #ifdef TCP_OFFLOAD 110638035ed6SNavdeep Parhar maxp = mtu_to_max_payload(sc, mtu, 1); 1107fe2ebb76SJohn Baldwin oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_rxq", 1108f549e352SNavdeep Parhar CTLFLAG_RD, NULL, "rx queues for offloaded TCP connections"); 1109fe2ebb76SJohn Baldwin for_each_ofld_rxq(vi, i, ofld_rxq) { 1110733b9277SNavdeep Parhar 111108cd1f11SNavdeep Parhar init_iq(&ofld_rxq->iq, sc, vi->ofld_tmr_idx, vi->ofld_pktc_idx, 1112fe2ebb76SJohn Baldwin vi->qsize_rxq); 1113733b9277SNavdeep Parhar 1114733b9277SNavdeep Parhar snprintf(name, sizeof(name), "%s ofld_rxq%d-fl", 1115fe2ebb76SJohn Baldwin device_get_nameunit(vi->dev), i); 1116fe2ebb76SJohn Baldwin init_fl(sc, &ofld_rxq->fl, vi->qsize_rxq / 8, maxp, name); 1117733b9277SNavdeep Parhar 1118f549e352SNavdeep Parhar rc = alloc_ofld_rxq(vi, ofld_rxq, 1119f549e352SNavdeep Parhar forwarding_intr_to_fwq(sc) ? -1 : intr_idx, i, oid); 1120733b9277SNavdeep Parhar if (rc != 0) 1121733b9277SNavdeep Parhar goto done; 1122733b9277SNavdeep Parhar intr_idx++; 1123733b9277SNavdeep Parhar } 1124733b9277SNavdeep Parhar #endif 1125733b9277SNavdeep Parhar 1126733b9277SNavdeep Parhar /* 1127f549e352SNavdeep Parhar * Now the tx queues. 1128733b9277SNavdeep Parhar */ 1129fe2ebb76SJohn Baldwin oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "txq", CTLFLAG_RD, 1130733b9277SNavdeep Parhar NULL, "tx queues"); 1131fe2ebb76SJohn Baldwin for_each_txq(vi, i, txq) { 1132f549e352SNavdeep Parhar iqidx = vi->first_rxq + (i % vi->nrxq); 113354e4ee71SNavdeep Parhar snprintf(name, sizeof(name), "%s txq%d", 1134fe2ebb76SJohn Baldwin device_get_nameunit(vi->dev), i); 1135f549e352SNavdeep Parhar init_eq(sc, &txq->eq, EQ_ETH, vi->qsize_txq, pi->tx_chan, 1136f549e352SNavdeep Parhar sc->sge.rxq[iqidx].iq.cntxt_id, name); 113754e4ee71SNavdeep Parhar 1138fe2ebb76SJohn Baldwin rc = alloc_txq(vi, txq, i, oid); 113954e4ee71SNavdeep Parhar if (rc != 0) 114054e4ee71SNavdeep Parhar goto done; 114154e4ee71SNavdeep Parhar } 114209fe6320SNavdeep Parhar #ifdef TCP_OFFLOAD 1143fe2ebb76SJohn Baldwin oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_txq", 1144733b9277SNavdeep Parhar CTLFLAG_RD, NULL, "tx queues for offloaded TCP connections"); 1145fe2ebb76SJohn Baldwin for_each_ofld_txq(vi, i, ofld_txq) { 1146298d969cSNavdeep Parhar struct sysctl_oid *oid2; 1147733b9277SNavdeep Parhar 1148f549e352SNavdeep Parhar iqidx = vi->first_ofld_rxq + (i % vi->nofldrxq); 1149733b9277SNavdeep Parhar snprintf(name, sizeof(name), "%s ofld_txq%d", 1150fe2ebb76SJohn Baldwin device_get_nameunit(vi->dev), i); 115190e7434aSNavdeep Parhar init_eq(sc, &ofld_txq->eq, EQ_OFLD, vi->qsize_txq, pi->tx_chan, 1152f549e352SNavdeep Parhar sc->sge.ofld_rxq[iqidx].iq.cntxt_id, name); 1153733b9277SNavdeep Parhar 1154733b9277SNavdeep Parhar snprintf(name, sizeof(name), "%d", i); 1155fe2ebb76SJohn Baldwin oid2 = SYSCTL_ADD_NODE(&vi->ctx, SYSCTL_CHILDREN(oid), OID_AUTO, 1156733b9277SNavdeep Parhar name, CTLFLAG_RD, NULL, "offload tx queue"); 1157733b9277SNavdeep Parhar 1158fe2ebb76SJohn Baldwin rc = alloc_wrq(sc, vi, ofld_txq, oid2); 1159298d969cSNavdeep Parhar if (rc != 0) 1160298d969cSNavdeep Parhar goto done; 1161298d969cSNavdeep Parhar } 1162298d969cSNavdeep Parhar #endif 1163733b9277SNavdeep Parhar 1164733b9277SNavdeep Parhar /* 1165733b9277SNavdeep Parhar * Finally, the control queue. 1166733b9277SNavdeep Parhar */ 11676af45170SJohn Baldwin if (!IS_MAIN_VI(vi) || sc->flags & IS_VF) 1168fe2ebb76SJohn Baldwin goto done; 1169fe2ebb76SJohn Baldwin oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ctrlq", CTLFLAG_RD, 1170733b9277SNavdeep Parhar NULL, "ctrl queue"); 1171733b9277SNavdeep Parhar ctrlq = &sc->sge.ctrlq[pi->port_id]; 1172fe2ebb76SJohn Baldwin snprintf(name, sizeof(name), "%s ctrlq", device_get_nameunit(vi->dev)); 1173f549e352SNavdeep Parhar init_eq(sc, &ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE, pi->tx_chan, 1174f549e352SNavdeep Parhar sc->sge.rxq[vi->first_rxq].iq.cntxt_id, name); 1175fe2ebb76SJohn Baldwin rc = alloc_wrq(sc, vi, ctrlq, oid); 1176733b9277SNavdeep Parhar 117754e4ee71SNavdeep Parhar done: 117854e4ee71SNavdeep Parhar if (rc) 1179fe2ebb76SJohn Baldwin t4_teardown_vi_queues(vi); 118054e4ee71SNavdeep Parhar 118154e4ee71SNavdeep Parhar return (rc); 118254e4ee71SNavdeep Parhar } 118354e4ee71SNavdeep Parhar 118454e4ee71SNavdeep Parhar /* 118554e4ee71SNavdeep Parhar * Idempotent 118654e4ee71SNavdeep Parhar */ 118754e4ee71SNavdeep Parhar int 1188fe2ebb76SJohn Baldwin t4_teardown_vi_queues(struct vi_info *vi) 118954e4ee71SNavdeep Parhar { 119054e4ee71SNavdeep Parhar int i; 1191fe2ebb76SJohn Baldwin struct port_info *pi = vi->pi; 1192733b9277SNavdeep Parhar struct adapter *sc = pi->adapter; 119354e4ee71SNavdeep Parhar struct sge_rxq *rxq; 119454e4ee71SNavdeep Parhar struct sge_txq *txq; 119509fe6320SNavdeep Parhar #ifdef TCP_OFFLOAD 1196733b9277SNavdeep Parhar struct sge_ofld_rxq *ofld_rxq; 1197733b9277SNavdeep Parhar struct sge_wrq *ofld_txq; 1198733b9277SNavdeep Parhar #endif 1199298d969cSNavdeep Parhar #ifdef DEV_NETMAP 1200298d969cSNavdeep Parhar struct sge_nm_rxq *nm_rxq; 1201298d969cSNavdeep Parhar struct sge_nm_txq *nm_txq; 1202298d969cSNavdeep Parhar #endif 120354e4ee71SNavdeep Parhar 120454e4ee71SNavdeep Parhar /* Do this before freeing the queues */ 1205fe2ebb76SJohn Baldwin if (vi->flags & VI_SYSCTL_CTX) { 1206fe2ebb76SJohn Baldwin sysctl_ctx_free(&vi->ctx); 1207fe2ebb76SJohn Baldwin vi->flags &= ~VI_SYSCTL_CTX; 120854e4ee71SNavdeep Parhar } 120954e4ee71SNavdeep Parhar 1210fe2ebb76SJohn Baldwin #ifdef DEV_NETMAP 121162291463SNavdeep Parhar if (vi->ifp->if_capabilities & IFCAP_NETMAP) { 1212fe2ebb76SJohn Baldwin for_each_nm_txq(vi, i, nm_txq) { 1213fe2ebb76SJohn Baldwin free_nm_txq(vi, nm_txq); 1214fe2ebb76SJohn Baldwin } 1215fe2ebb76SJohn Baldwin 1216fe2ebb76SJohn Baldwin for_each_nm_rxq(vi, i, nm_rxq) { 1217fe2ebb76SJohn Baldwin free_nm_rxq(vi, nm_rxq); 1218fe2ebb76SJohn Baldwin } 1219fe2ebb76SJohn Baldwin } 1220fe2ebb76SJohn Baldwin #endif 1221fe2ebb76SJohn Baldwin 1222733b9277SNavdeep Parhar /* 1223733b9277SNavdeep Parhar * Take down all the tx queues first, as they reference the rx queues 1224733b9277SNavdeep Parhar * (for egress updates, etc.). 1225733b9277SNavdeep Parhar */ 1226733b9277SNavdeep Parhar 12276af45170SJohn Baldwin if (IS_MAIN_VI(vi) && !(sc->flags & IS_VF)) 1228733b9277SNavdeep Parhar free_wrq(sc, &sc->sge.ctrlq[pi->port_id]); 1229733b9277SNavdeep Parhar 1230fe2ebb76SJohn Baldwin for_each_txq(vi, i, txq) { 1231fe2ebb76SJohn Baldwin free_txq(vi, txq); 123254e4ee71SNavdeep Parhar } 123309fe6320SNavdeep Parhar #ifdef TCP_OFFLOAD 1234fe2ebb76SJohn Baldwin for_each_ofld_txq(vi, i, ofld_txq) { 1235733b9277SNavdeep Parhar free_wrq(sc, ofld_txq); 1236733b9277SNavdeep Parhar } 1237733b9277SNavdeep Parhar #endif 1238733b9277SNavdeep Parhar 1239733b9277SNavdeep Parhar /* 1240f549e352SNavdeep Parhar * Then take down the rx queues. 1241733b9277SNavdeep Parhar */ 1242733b9277SNavdeep Parhar 1243fe2ebb76SJohn Baldwin for_each_rxq(vi, i, rxq) { 1244fe2ebb76SJohn Baldwin free_rxq(vi, rxq); 124554e4ee71SNavdeep Parhar } 124609fe6320SNavdeep Parhar #ifdef TCP_OFFLOAD 1247fe2ebb76SJohn Baldwin for_each_ofld_rxq(vi, i, ofld_rxq) { 1248fe2ebb76SJohn Baldwin free_ofld_rxq(vi, ofld_rxq); 1249733b9277SNavdeep Parhar } 1250733b9277SNavdeep Parhar #endif 1251733b9277SNavdeep Parhar 125254e4ee71SNavdeep Parhar return (0); 125354e4ee71SNavdeep Parhar } 125454e4ee71SNavdeep Parhar 1255733b9277SNavdeep Parhar /* 1256733b9277SNavdeep Parhar * Deals with errors and the firmware event queue. All data rx queues forward 1257733b9277SNavdeep Parhar * their interrupt to the firmware event queue. 1258733b9277SNavdeep Parhar */ 125954e4ee71SNavdeep Parhar void 126054e4ee71SNavdeep Parhar t4_intr_all(void *arg) 126154e4ee71SNavdeep Parhar { 126254e4ee71SNavdeep Parhar struct adapter *sc = arg; 1263733b9277SNavdeep Parhar struct sge_iq *fwq = &sc->sge.fwq; 126454e4ee71SNavdeep Parhar 126554e4ee71SNavdeep Parhar t4_intr_err(arg); 1266733b9277SNavdeep Parhar if (atomic_cmpset_int(&fwq->state, IQS_IDLE, IQS_BUSY)) { 1267733b9277SNavdeep Parhar service_iq(fwq, 0); 1268733b9277SNavdeep Parhar atomic_cmpset_int(&fwq->state, IQS_BUSY, IQS_IDLE); 126954e4ee71SNavdeep Parhar } 127054e4ee71SNavdeep Parhar } 127154e4ee71SNavdeep Parhar 127254e4ee71SNavdeep Parhar /* Deals with error interrupts */ 127354e4ee71SNavdeep Parhar void 127454e4ee71SNavdeep Parhar t4_intr_err(void *arg) 127554e4ee71SNavdeep Parhar { 127654e4ee71SNavdeep Parhar struct adapter *sc = arg; 127754e4ee71SNavdeep Parhar 127854e4ee71SNavdeep Parhar t4_write_reg(sc, MYPF_REG(A_PCIE_PF_CLI), 0); 127954e4ee71SNavdeep Parhar t4_slow_intr_handler(sc); 128054e4ee71SNavdeep Parhar } 128154e4ee71SNavdeep Parhar 128254e4ee71SNavdeep Parhar void 128354e4ee71SNavdeep Parhar t4_intr_evt(void *arg) 128454e4ee71SNavdeep Parhar { 128554e4ee71SNavdeep Parhar struct sge_iq *iq = arg; 12862be67d29SNavdeep Parhar 1287733b9277SNavdeep Parhar if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 1288733b9277SNavdeep Parhar service_iq(iq, 0); 1289733b9277SNavdeep Parhar atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 12902be67d29SNavdeep Parhar } 12912be67d29SNavdeep Parhar } 12922be67d29SNavdeep Parhar 1293733b9277SNavdeep Parhar void 1294733b9277SNavdeep Parhar t4_intr(void *arg) 12952be67d29SNavdeep Parhar { 12962be67d29SNavdeep Parhar struct sge_iq *iq = arg; 1297733b9277SNavdeep Parhar 1298733b9277SNavdeep Parhar if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 1299733b9277SNavdeep Parhar service_iq(iq, 0); 1300733b9277SNavdeep Parhar atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 1301733b9277SNavdeep Parhar } 1302733b9277SNavdeep Parhar } 1303733b9277SNavdeep Parhar 130462291463SNavdeep Parhar void 130562291463SNavdeep Parhar t4_vi_intr(void *arg) 130662291463SNavdeep Parhar { 130762291463SNavdeep Parhar struct irq *irq = arg; 130862291463SNavdeep Parhar 130962291463SNavdeep Parhar #ifdef DEV_NETMAP 131062291463SNavdeep Parhar if (atomic_cmpset_int(&irq->nm_state, NM_ON, NM_BUSY)) { 131162291463SNavdeep Parhar t4_nm_intr(irq->nm_rxq); 131262291463SNavdeep Parhar atomic_cmpset_int(&irq->nm_state, NM_BUSY, NM_ON); 131362291463SNavdeep Parhar } 131462291463SNavdeep Parhar #endif 131562291463SNavdeep Parhar if (irq->rxq != NULL) 131662291463SNavdeep Parhar t4_intr(irq->rxq); 131762291463SNavdeep Parhar } 131862291463SNavdeep Parhar 131946f48ee5SNavdeep Parhar static inline int 132046f48ee5SNavdeep Parhar sort_before_lro(struct lro_ctrl *lro) 132146f48ee5SNavdeep Parhar { 132246f48ee5SNavdeep Parhar 132346f48ee5SNavdeep Parhar return (lro->lro_mbuf_max != 0); 132446f48ee5SNavdeep Parhar } 132546f48ee5SNavdeep Parhar 1326733b9277SNavdeep Parhar /* 1327733b9277SNavdeep Parhar * Deals with anything and everything on the given ingress queue. 1328733b9277SNavdeep Parhar */ 1329733b9277SNavdeep Parhar static int 1330733b9277SNavdeep Parhar service_iq(struct sge_iq *iq, int budget) 1331733b9277SNavdeep Parhar { 1332733b9277SNavdeep Parhar struct sge_iq *q; 133309fe6320SNavdeep Parhar struct sge_rxq *rxq = iq_to_rxq(iq); /* Use iff iq is part of rxq */ 13344d6db4e0SNavdeep Parhar struct sge_fl *fl; /* Use iff IQ_HAS_FL */ 133554e4ee71SNavdeep Parhar struct adapter *sc = iq->adapter; 1336b2daa9a9SNavdeep Parhar struct iq_desc *d = &iq->desc[iq->cidx]; 13374d6db4e0SNavdeep Parhar int ndescs = 0, limit; 13384d6db4e0SNavdeep Parhar int rsp_type, refill; 1339733b9277SNavdeep Parhar uint32_t lq; 13404d6db4e0SNavdeep Parhar uint16_t fl_hw_cidx; 1341733b9277SNavdeep Parhar struct mbuf *m0; 1342733b9277SNavdeep Parhar STAILQ_HEAD(, sge_iq) iql = STAILQ_HEAD_INITIALIZER(iql); 1343480e603cSNavdeep Parhar #if defined(INET) || defined(INET6) 1344480e603cSNavdeep Parhar const struct timeval lro_timeout = {0, sc->lro_timeout}; 134546f48ee5SNavdeep Parhar struct lro_ctrl *lro = &rxq->lro; 1346480e603cSNavdeep Parhar #endif 1347733b9277SNavdeep Parhar 1348733b9277SNavdeep Parhar KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq)); 1349733b9277SNavdeep Parhar 13504d6db4e0SNavdeep Parhar limit = budget ? budget : iq->qsize / 16; 13514d6db4e0SNavdeep Parhar 13524d6db4e0SNavdeep Parhar if (iq->flags & IQ_HAS_FL) { 13534d6db4e0SNavdeep Parhar fl = &rxq->fl; 13544d6db4e0SNavdeep Parhar fl_hw_cidx = fl->hw_cidx; /* stable snapshot */ 13554d6db4e0SNavdeep Parhar } else { 13564d6db4e0SNavdeep Parhar fl = NULL; 13574d6db4e0SNavdeep Parhar fl_hw_cidx = 0; /* to silence gcc warning */ 13584d6db4e0SNavdeep Parhar } 13594d6db4e0SNavdeep Parhar 136046f48ee5SNavdeep Parhar #if defined(INET) || defined(INET6) 136146f48ee5SNavdeep Parhar if (iq->flags & IQ_ADJ_CREDIT) { 136246f48ee5SNavdeep Parhar MPASS(sort_before_lro(lro)); 136346f48ee5SNavdeep Parhar iq->flags &= ~IQ_ADJ_CREDIT; 136446f48ee5SNavdeep Parhar if ((d->rsp.u.type_gen & F_RSPD_GEN) != iq->gen) { 136546f48ee5SNavdeep Parhar tcp_lro_flush_all(lro); 136646f48ee5SNavdeep Parhar t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(1) | 136746f48ee5SNavdeep Parhar V_INGRESSQID((u32)iq->cntxt_id) | 136846f48ee5SNavdeep Parhar V_SEINTARM(iq->intr_params)); 136946f48ee5SNavdeep Parhar return (0); 137046f48ee5SNavdeep Parhar } 137146f48ee5SNavdeep Parhar ndescs = 1; 137246f48ee5SNavdeep Parhar } 137346f48ee5SNavdeep Parhar #else 137446f48ee5SNavdeep Parhar MPASS((iq->flags & IQ_ADJ_CREDIT) == 0); 137546f48ee5SNavdeep Parhar #endif 137646f48ee5SNavdeep Parhar 1377733b9277SNavdeep Parhar /* 1378733b9277SNavdeep Parhar * We always come back and check the descriptor ring for new indirect 1379733b9277SNavdeep Parhar * interrupts and other responses after running a single handler. 1380733b9277SNavdeep Parhar */ 1381733b9277SNavdeep Parhar for (;;) { 1382b2daa9a9SNavdeep Parhar while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) { 138354e4ee71SNavdeep Parhar 138454e4ee71SNavdeep Parhar rmb(); 138554e4ee71SNavdeep Parhar 13864d6db4e0SNavdeep Parhar refill = 0; 1387733b9277SNavdeep Parhar m0 = NULL; 1388b2daa9a9SNavdeep Parhar rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen); 1389b2daa9a9SNavdeep Parhar lq = be32toh(d->rsp.pldbuflen_qid); 139054e4ee71SNavdeep Parhar 1391733b9277SNavdeep Parhar switch (rsp_type) { 1392733b9277SNavdeep Parhar case X_RSPD_TYPE_FLBUF: 139354e4ee71SNavdeep Parhar 1394733b9277SNavdeep Parhar KASSERT(iq->flags & IQ_HAS_FL, 1395733b9277SNavdeep Parhar ("%s: data for an iq (%p) with no freelist", 1396733b9277SNavdeep Parhar __func__, iq)); 1397733b9277SNavdeep Parhar 13984d6db4e0SNavdeep Parhar m0 = get_fl_payload(sc, fl, lq); 13991458bff9SNavdeep Parhar if (__predict_false(m0 == NULL)) 14001458bff9SNavdeep Parhar goto process_iql; 14014d6db4e0SNavdeep Parhar refill = IDXDIFF(fl->hw_cidx, fl_hw_cidx, fl->sidx) > 2; 1402733b9277SNavdeep Parhar #ifdef T4_PKT_TIMESTAMP 1403733b9277SNavdeep Parhar /* 1404733b9277SNavdeep Parhar * 60 bit timestamp for the payload is 1405733b9277SNavdeep Parhar * *(uint64_t *)m0->m_pktdat. Note that it is 1406733b9277SNavdeep Parhar * in the leading free-space in the mbuf. The 1407733b9277SNavdeep Parhar * kernel can clobber it during a pullup, 1408733b9277SNavdeep Parhar * m_copymdata, etc. You need to make sure that 1409733b9277SNavdeep Parhar * the mbuf reaches you unmolested if you care 1410733b9277SNavdeep Parhar * about the timestamp. 1411733b9277SNavdeep Parhar */ 1412733b9277SNavdeep Parhar *(uint64_t *)m0->m_pktdat = 1413733b9277SNavdeep Parhar be64toh(ctrl->u.last_flit) & 1414733b9277SNavdeep Parhar 0xfffffffffffffff; 1415733b9277SNavdeep Parhar #endif 1416733b9277SNavdeep Parhar 1417733b9277SNavdeep Parhar /* fall through */ 1418733b9277SNavdeep Parhar 1419733b9277SNavdeep Parhar case X_RSPD_TYPE_CPL: 1420b2daa9a9SNavdeep Parhar KASSERT(d->rss.opcode < NUM_CPL_CMDS, 1421733b9277SNavdeep Parhar ("%s: bad opcode %02x.", __func__, 1422b2daa9a9SNavdeep Parhar d->rss.opcode)); 1423671bf2b8SNavdeep Parhar t4_cpl_handler[d->rss.opcode](iq, &d->rss, m0); 1424733b9277SNavdeep Parhar break; 1425733b9277SNavdeep Parhar 1426733b9277SNavdeep Parhar case X_RSPD_TYPE_INTR: 1427733b9277SNavdeep Parhar 1428733b9277SNavdeep Parhar /* 1429733b9277SNavdeep Parhar * Interrupts should be forwarded only to queues 1430733b9277SNavdeep Parhar * that are not forwarding their interrupts. 1431733b9277SNavdeep Parhar * This means service_iq can recurse but only 1 1432733b9277SNavdeep Parhar * level deep. 1433733b9277SNavdeep Parhar */ 1434733b9277SNavdeep Parhar KASSERT(budget == 0, 1435733b9277SNavdeep Parhar ("%s: budget %u, rsp_type %u", __func__, 1436733b9277SNavdeep Parhar budget, rsp_type)); 1437733b9277SNavdeep Parhar 143898005176SNavdeep Parhar /* 143998005176SNavdeep Parhar * There are 1K interrupt-capable queues (qids 0 144098005176SNavdeep Parhar * through 1023). A response type indicating a 144198005176SNavdeep Parhar * forwarded interrupt with a qid >= 1K is an 144298005176SNavdeep Parhar * iWARP async notification. 144398005176SNavdeep Parhar */ 144498005176SNavdeep Parhar if (lq >= 1024) { 1445671bf2b8SNavdeep Parhar t4_an_handler(iq, &d->rsp); 144698005176SNavdeep Parhar break; 144798005176SNavdeep Parhar } 144898005176SNavdeep Parhar 1449ec55567cSJohn Baldwin q = sc->sge.iqmap[lq - sc->sge.iq_start - 1450ec55567cSJohn Baldwin sc->sge.iq_base]; 1451733b9277SNavdeep Parhar if (atomic_cmpset_int(&q->state, IQS_IDLE, 1452733b9277SNavdeep Parhar IQS_BUSY)) { 14534d6db4e0SNavdeep Parhar if (service_iq(q, q->qsize / 16) == 0) { 1454733b9277SNavdeep Parhar atomic_cmpset_int(&q->state, 1455733b9277SNavdeep Parhar IQS_BUSY, IQS_IDLE); 1456733b9277SNavdeep Parhar } else { 1457733b9277SNavdeep Parhar STAILQ_INSERT_TAIL(&iql, q, 1458733b9277SNavdeep Parhar link); 1459733b9277SNavdeep Parhar } 1460733b9277SNavdeep Parhar } 1461733b9277SNavdeep Parhar break; 1462733b9277SNavdeep Parhar 1463733b9277SNavdeep Parhar default: 146498005176SNavdeep Parhar KASSERT(0, 146598005176SNavdeep Parhar ("%s: illegal response type %d on iq %p", 146698005176SNavdeep Parhar __func__, rsp_type, iq)); 146798005176SNavdeep Parhar log(LOG_ERR, 146898005176SNavdeep Parhar "%s: illegal response type %d on iq %p", 146998005176SNavdeep Parhar device_get_nameunit(sc->dev), rsp_type, iq); 147009fe6320SNavdeep Parhar break; 147154e4ee71SNavdeep Parhar } 147256599263SNavdeep Parhar 1473b2daa9a9SNavdeep Parhar d++; 1474b2daa9a9SNavdeep Parhar if (__predict_false(++iq->cidx == iq->sidx)) { 1475b2daa9a9SNavdeep Parhar iq->cidx = 0; 1476b2daa9a9SNavdeep Parhar iq->gen ^= F_RSPD_GEN; 1477b2daa9a9SNavdeep Parhar d = &iq->desc[0]; 1478b2daa9a9SNavdeep Parhar } 1479b2daa9a9SNavdeep Parhar if (__predict_false(++ndescs == limit)) { 1480315048f2SJohn Baldwin t4_write_reg(sc, sc->sge_gts_reg, 1481733b9277SNavdeep Parhar V_CIDXINC(ndescs) | 1482733b9277SNavdeep Parhar V_INGRESSQID(iq->cntxt_id) | 1483733b9277SNavdeep Parhar V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); 1484733b9277SNavdeep Parhar ndescs = 0; 1485733b9277SNavdeep Parhar 1486480e603cSNavdeep Parhar #if defined(INET) || defined(INET6) 1487480e603cSNavdeep Parhar if (iq->flags & IQ_LRO_ENABLED && 148846f48ee5SNavdeep Parhar !sort_before_lro(lro) && 1489480e603cSNavdeep Parhar sc->lro_timeout != 0) { 149046f48ee5SNavdeep Parhar tcp_lro_flush_inactive(lro, 1491480e603cSNavdeep Parhar &lro_timeout); 1492480e603cSNavdeep Parhar } 1493480e603cSNavdeep Parhar #endif 1494480e603cSNavdeep Parhar 1495861e42b2SNavdeep Parhar if (budget) { 14964d6db4e0SNavdeep Parhar if (iq->flags & IQ_HAS_FL) { 1497861e42b2SNavdeep Parhar FL_LOCK(fl); 1498861e42b2SNavdeep Parhar refill_fl(sc, fl, 32); 1499861e42b2SNavdeep Parhar FL_UNLOCK(fl); 1500861e42b2SNavdeep Parhar } 1501733b9277SNavdeep Parhar return (EINPROGRESS); 150254e4ee71SNavdeep Parhar } 1503733b9277SNavdeep Parhar } 15044d6db4e0SNavdeep Parhar if (refill) { 15054d6db4e0SNavdeep Parhar FL_LOCK(fl); 15064d6db4e0SNavdeep Parhar refill_fl(sc, fl, 32); 15074d6db4e0SNavdeep Parhar FL_UNLOCK(fl); 15084d6db4e0SNavdeep Parhar fl_hw_cidx = fl->hw_cidx; 15094d6db4e0SNavdeep Parhar } 1510861e42b2SNavdeep Parhar } 1511733b9277SNavdeep Parhar 15121458bff9SNavdeep Parhar process_iql: 1513733b9277SNavdeep Parhar if (STAILQ_EMPTY(&iql)) 1514733b9277SNavdeep Parhar break; 1515733b9277SNavdeep Parhar 1516733b9277SNavdeep Parhar /* 1517733b9277SNavdeep Parhar * Process the head only, and send it to the back of the list if 1518733b9277SNavdeep Parhar * it's still not done. 1519733b9277SNavdeep Parhar */ 1520733b9277SNavdeep Parhar q = STAILQ_FIRST(&iql); 1521733b9277SNavdeep Parhar STAILQ_REMOVE_HEAD(&iql, link); 1522733b9277SNavdeep Parhar if (service_iq(q, q->qsize / 8) == 0) 1523733b9277SNavdeep Parhar atomic_cmpset_int(&q->state, IQS_BUSY, IQS_IDLE); 1524733b9277SNavdeep Parhar else 1525733b9277SNavdeep Parhar STAILQ_INSERT_TAIL(&iql, q, link); 1526733b9277SNavdeep Parhar } 1527733b9277SNavdeep Parhar 1528a1ea9a82SNavdeep Parhar #if defined(INET) || defined(INET6) 1529733b9277SNavdeep Parhar if (iq->flags & IQ_LRO_ENABLED) { 153046f48ee5SNavdeep Parhar if (ndescs > 0 && lro->lro_mbuf_count > 8) { 153146f48ee5SNavdeep Parhar MPASS(sort_before_lro(lro)); 153246f48ee5SNavdeep Parhar /* hold back one credit and don't flush LRO state */ 153346f48ee5SNavdeep Parhar iq->flags |= IQ_ADJ_CREDIT; 153446f48ee5SNavdeep Parhar ndescs--; 153546f48ee5SNavdeep Parhar } else { 15366dd38b87SSepherosa Ziehau tcp_lro_flush_all(lro); 1537733b9277SNavdeep Parhar } 153846f48ee5SNavdeep Parhar } 1539733b9277SNavdeep Parhar #endif 1540733b9277SNavdeep Parhar 1541315048f2SJohn Baldwin t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) | 1542733b9277SNavdeep Parhar V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params)); 1543733b9277SNavdeep Parhar 1544733b9277SNavdeep Parhar if (iq->flags & IQ_HAS_FL) { 1545733b9277SNavdeep Parhar int starved; 1546733b9277SNavdeep Parhar 1547733b9277SNavdeep Parhar FL_LOCK(fl); 154838035ed6SNavdeep Parhar starved = refill_fl(sc, fl, 64); 1549733b9277SNavdeep Parhar FL_UNLOCK(fl); 1550733b9277SNavdeep Parhar if (__predict_false(starved != 0)) 1551733b9277SNavdeep Parhar add_fl_to_sfl(sc, fl); 1552733b9277SNavdeep Parhar } 1553733b9277SNavdeep Parhar 1554733b9277SNavdeep Parhar return (0); 1555733b9277SNavdeep Parhar } 1556733b9277SNavdeep Parhar 155738035ed6SNavdeep Parhar static inline int 155838035ed6SNavdeep Parhar cl_has_metadata(struct sge_fl *fl, struct cluster_layout *cll) 15591458bff9SNavdeep Parhar { 156038035ed6SNavdeep Parhar int rc = fl->flags & FL_BUF_PACKING || cll->region1 > 0; 15611458bff9SNavdeep Parhar 156238035ed6SNavdeep Parhar if (rc) 156338035ed6SNavdeep Parhar MPASS(cll->region3 >= CL_METADATA_SIZE); 156438035ed6SNavdeep Parhar 156538035ed6SNavdeep Parhar return (rc); 15661458bff9SNavdeep Parhar } 15671458bff9SNavdeep Parhar 156838035ed6SNavdeep Parhar static inline struct cluster_metadata * 156938035ed6SNavdeep Parhar cl_metadata(struct adapter *sc, struct sge_fl *fl, struct cluster_layout *cll, 157038035ed6SNavdeep Parhar caddr_t cl) 15711458bff9SNavdeep Parhar { 15721458bff9SNavdeep Parhar 157338035ed6SNavdeep Parhar if (cl_has_metadata(fl, cll)) { 157438035ed6SNavdeep Parhar struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx]; 15751458bff9SNavdeep Parhar 157638035ed6SNavdeep Parhar return ((struct cluster_metadata *)(cl + swz->size) - 1); 15771458bff9SNavdeep Parhar } 157838035ed6SNavdeep Parhar return (NULL); 15791458bff9SNavdeep Parhar } 15801458bff9SNavdeep Parhar 158115c28f87SGleb Smirnoff static void 1582e8fd18f3SGleb Smirnoff rxb_free(struct mbuf *m) 15831458bff9SNavdeep Parhar { 1584e8fd18f3SGleb Smirnoff uma_zone_t zone = m->m_ext.ext_arg1; 1585e8fd18f3SGleb Smirnoff void *cl = m->m_ext.ext_arg2; 15861458bff9SNavdeep Parhar 15871458bff9SNavdeep Parhar uma_zfree(zone, cl); 158882eff304SNavdeep Parhar counter_u64_add(extfree_rels, 1); 15891458bff9SNavdeep Parhar } 15901458bff9SNavdeep Parhar 159138035ed6SNavdeep Parhar /* 159238035ed6SNavdeep Parhar * The mbuf returned by this function could be allocated from zone_mbuf or 159338035ed6SNavdeep Parhar * constructed in spare room in the cluster. 159438035ed6SNavdeep Parhar * 159538035ed6SNavdeep Parhar * The mbuf carries the payload in one of these ways 159638035ed6SNavdeep Parhar * a) frame inside the mbuf (mbuf from zone_mbuf) 159738035ed6SNavdeep Parhar * b) m_cljset (for clusters without metadata) zone_mbuf 159838035ed6SNavdeep Parhar * c) m_extaddref (cluster with metadata) inline mbuf 159938035ed6SNavdeep Parhar * d) m_extaddref (cluster with metadata) zone_mbuf 160038035ed6SNavdeep Parhar */ 16011458bff9SNavdeep Parhar static struct mbuf * 1602b741402cSNavdeep Parhar get_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset, 1603b741402cSNavdeep Parhar int remaining) 160438035ed6SNavdeep Parhar { 160538035ed6SNavdeep Parhar struct mbuf *m; 160638035ed6SNavdeep Parhar struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 160738035ed6SNavdeep Parhar struct cluster_layout *cll = &sd->cll; 160838035ed6SNavdeep Parhar struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx]; 160938035ed6SNavdeep Parhar struct hw_buf_info *hwb = &sc->sge.hw_buf_info[cll->hwidx]; 161038035ed6SNavdeep Parhar struct cluster_metadata *clm = cl_metadata(sc, fl, cll, sd->cl); 1611b741402cSNavdeep Parhar int len, blen; 161238035ed6SNavdeep Parhar caddr_t payload; 161338035ed6SNavdeep Parhar 1614b741402cSNavdeep Parhar blen = hwb->size - fl->rx_offset; /* max possible in this buf */ 1615b741402cSNavdeep Parhar len = min(remaining, blen); 161638035ed6SNavdeep Parhar payload = sd->cl + cll->region1 + fl->rx_offset; 1617e3207e19SNavdeep Parhar if (fl->flags & FL_BUF_PACKING) { 1618b741402cSNavdeep Parhar const u_int l = fr_offset + len; 1619b741402cSNavdeep Parhar const u_int pad = roundup2(l, fl->buf_boundary) - l; 1620b741402cSNavdeep Parhar 1621b741402cSNavdeep Parhar if (fl->rx_offset + len + pad < hwb->size) 1622b741402cSNavdeep Parhar blen = len + pad; 1623b741402cSNavdeep Parhar MPASS(fl->rx_offset + blen <= hwb->size); 1624e3207e19SNavdeep Parhar } else { 1625e3207e19SNavdeep Parhar MPASS(fl->rx_offset == 0); /* not packing */ 1626e3207e19SNavdeep Parhar } 162738035ed6SNavdeep Parhar 1628b741402cSNavdeep Parhar 162938035ed6SNavdeep Parhar if (sc->sc_do_rxcopy && len < RX_COPY_THRESHOLD) { 163038035ed6SNavdeep Parhar 163138035ed6SNavdeep Parhar /* 163238035ed6SNavdeep Parhar * Copy payload into a freshly allocated mbuf. 163338035ed6SNavdeep Parhar */ 163438035ed6SNavdeep Parhar 1635b741402cSNavdeep Parhar m = fr_offset == 0 ? 163638035ed6SNavdeep Parhar m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA); 163738035ed6SNavdeep Parhar if (m == NULL) 163838035ed6SNavdeep Parhar return (NULL); 163938035ed6SNavdeep Parhar fl->mbuf_allocated++; 164038035ed6SNavdeep Parhar #ifdef T4_PKT_TIMESTAMP 164138035ed6SNavdeep Parhar /* Leave room for a timestamp */ 164238035ed6SNavdeep Parhar m->m_data += 8; 164338035ed6SNavdeep Parhar #endif 164438035ed6SNavdeep Parhar /* copy data to mbuf */ 164538035ed6SNavdeep Parhar bcopy(payload, mtod(m, caddr_t), len); 164638035ed6SNavdeep Parhar 1647c3fb7725SNavdeep Parhar } else if (sd->nmbuf * MSIZE < cll->region1) { 164838035ed6SNavdeep Parhar 164938035ed6SNavdeep Parhar /* 165038035ed6SNavdeep Parhar * There's spare room in the cluster for an mbuf. Create one 1651ccc69b2fSNavdeep Parhar * and associate it with the payload that's in the cluster. 165238035ed6SNavdeep Parhar */ 165338035ed6SNavdeep Parhar 165438035ed6SNavdeep Parhar MPASS(clm != NULL); 1655c3fb7725SNavdeep Parhar m = (struct mbuf *)(sd->cl + sd->nmbuf * MSIZE); 165638035ed6SNavdeep Parhar /* No bzero required */ 1657b4b12e52SGleb Smirnoff if (m_init(m, M_NOWAIT, MT_DATA, 1658b741402cSNavdeep Parhar fr_offset == 0 ? M_PKTHDR | M_NOFREE : M_NOFREE)) 165938035ed6SNavdeep Parhar return (NULL); 166038035ed6SNavdeep Parhar fl->mbuf_inlined++; 1661b741402cSNavdeep Parhar m_extaddref(m, payload, blen, &clm->refcount, rxb_free, 166238035ed6SNavdeep Parhar swz->zone, sd->cl); 166382eff304SNavdeep Parhar if (sd->nmbuf++ == 0) 166482eff304SNavdeep Parhar counter_u64_add(extfree_refs, 1); 166538035ed6SNavdeep Parhar 166638035ed6SNavdeep Parhar } else { 166738035ed6SNavdeep Parhar 166838035ed6SNavdeep Parhar /* 166938035ed6SNavdeep Parhar * Grab an mbuf from zone_mbuf and associate it with the 167038035ed6SNavdeep Parhar * payload in the cluster. 167138035ed6SNavdeep Parhar */ 167238035ed6SNavdeep Parhar 1673b741402cSNavdeep Parhar m = fr_offset == 0 ? 167438035ed6SNavdeep Parhar m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA); 167538035ed6SNavdeep Parhar if (m == NULL) 167638035ed6SNavdeep Parhar return (NULL); 167738035ed6SNavdeep Parhar fl->mbuf_allocated++; 1678ccc69b2fSNavdeep Parhar if (clm != NULL) { 1679b741402cSNavdeep Parhar m_extaddref(m, payload, blen, &clm->refcount, 168038035ed6SNavdeep Parhar rxb_free, swz->zone, sd->cl); 168182eff304SNavdeep Parhar if (sd->nmbuf++ == 0) 168282eff304SNavdeep Parhar counter_u64_add(extfree_refs, 1); 1683ccc69b2fSNavdeep Parhar } else { 168438035ed6SNavdeep Parhar m_cljset(m, sd->cl, swz->type); 168538035ed6SNavdeep Parhar sd->cl = NULL; /* consumed, not a recycle candidate */ 168638035ed6SNavdeep Parhar } 168738035ed6SNavdeep Parhar } 1688b741402cSNavdeep Parhar if (fr_offset == 0) 1689b741402cSNavdeep Parhar m->m_pkthdr.len = remaining; 169038035ed6SNavdeep Parhar m->m_len = len; 169138035ed6SNavdeep Parhar 169238035ed6SNavdeep Parhar if (fl->flags & FL_BUF_PACKING) { 1693b741402cSNavdeep Parhar fl->rx_offset += blen; 169438035ed6SNavdeep Parhar MPASS(fl->rx_offset <= hwb->size); 169538035ed6SNavdeep Parhar if (fl->rx_offset < hwb->size) 169638035ed6SNavdeep Parhar return (m); /* without advancing the cidx */ 169738035ed6SNavdeep Parhar } 169838035ed6SNavdeep Parhar 16994d6db4e0SNavdeep Parhar if (__predict_false(++fl->cidx % 8 == 0)) { 17004d6db4e0SNavdeep Parhar uint16_t cidx = fl->cidx / 8; 17014d6db4e0SNavdeep Parhar 17024d6db4e0SNavdeep Parhar if (__predict_false(cidx == fl->sidx)) 17034d6db4e0SNavdeep Parhar fl->cidx = cidx = 0; 17044d6db4e0SNavdeep Parhar fl->hw_cidx = cidx; 17054d6db4e0SNavdeep Parhar } 170638035ed6SNavdeep Parhar fl->rx_offset = 0; 170738035ed6SNavdeep Parhar 170838035ed6SNavdeep Parhar return (m); 170938035ed6SNavdeep Parhar } 171038035ed6SNavdeep Parhar 171138035ed6SNavdeep Parhar static struct mbuf * 17124d6db4e0SNavdeep Parhar get_fl_payload(struct adapter *sc, struct sge_fl *fl, uint32_t len_newbuf) 17131458bff9SNavdeep Parhar { 171438035ed6SNavdeep Parhar struct mbuf *m0, *m, **pnext; 1715b741402cSNavdeep Parhar u_int remaining; 1716b741402cSNavdeep Parhar const u_int total = G_RSPD_LEN(len_newbuf); 17171458bff9SNavdeep Parhar 17184d6db4e0SNavdeep Parhar if (__predict_false(fl->flags & FL_BUF_RESUME)) { 1719368541baSNavdeep Parhar M_ASSERTPKTHDR(fl->m0); 1720b741402cSNavdeep Parhar MPASS(fl->m0->m_pkthdr.len == total); 1721b741402cSNavdeep Parhar MPASS(fl->remaining < total); 17221458bff9SNavdeep Parhar 172338035ed6SNavdeep Parhar m0 = fl->m0; 172438035ed6SNavdeep Parhar pnext = fl->pnext; 1725b741402cSNavdeep Parhar remaining = fl->remaining; 17264d6db4e0SNavdeep Parhar fl->flags &= ~FL_BUF_RESUME; 172738035ed6SNavdeep Parhar goto get_segment; 17281458bff9SNavdeep Parhar } 17291458bff9SNavdeep Parhar 173038035ed6SNavdeep Parhar if (fl->rx_offset > 0 && len_newbuf & F_RSPD_NEWBUF) { 17311458bff9SNavdeep Parhar fl->rx_offset = 0; 17324d6db4e0SNavdeep Parhar if (__predict_false(++fl->cidx % 8 == 0)) { 17334d6db4e0SNavdeep Parhar uint16_t cidx = fl->cidx / 8; 17344d6db4e0SNavdeep Parhar 17354d6db4e0SNavdeep Parhar if (__predict_false(cidx == fl->sidx)) 17364d6db4e0SNavdeep Parhar fl->cidx = cidx = 0; 17374d6db4e0SNavdeep Parhar fl->hw_cidx = cidx; 17384d6db4e0SNavdeep Parhar } 17391458bff9SNavdeep Parhar } 17401458bff9SNavdeep Parhar 17411458bff9SNavdeep Parhar /* 174238035ed6SNavdeep Parhar * Payload starts at rx_offset in the current hw buffer. Its length is 174338035ed6SNavdeep Parhar * 'len' and it may span multiple hw buffers. 17441458bff9SNavdeep Parhar */ 17451458bff9SNavdeep Parhar 1746b741402cSNavdeep Parhar m0 = get_scatter_segment(sc, fl, 0, total); 1747368541baSNavdeep Parhar if (m0 == NULL) 17484d6db4e0SNavdeep Parhar return (NULL); 1749b741402cSNavdeep Parhar remaining = total - m0->m_len; 175038035ed6SNavdeep Parhar pnext = &m0->m_next; 1751b741402cSNavdeep Parhar while (remaining > 0) { 175238035ed6SNavdeep Parhar get_segment: 175338035ed6SNavdeep Parhar MPASS(fl->rx_offset == 0); 1754b741402cSNavdeep Parhar m = get_scatter_segment(sc, fl, total - remaining, remaining); 17554d6db4e0SNavdeep Parhar if (__predict_false(m == NULL)) { 175638035ed6SNavdeep Parhar fl->m0 = m0; 175738035ed6SNavdeep Parhar fl->pnext = pnext; 1758b741402cSNavdeep Parhar fl->remaining = remaining; 17594d6db4e0SNavdeep Parhar fl->flags |= FL_BUF_RESUME; 17604d6db4e0SNavdeep Parhar return (NULL); 17611458bff9SNavdeep Parhar } 176238035ed6SNavdeep Parhar *pnext = m; 176338035ed6SNavdeep Parhar pnext = &m->m_next; 1764b741402cSNavdeep Parhar remaining -= m->m_len; 1765733b9277SNavdeep Parhar } 176638035ed6SNavdeep Parhar *pnext = NULL; 17674d6db4e0SNavdeep Parhar 1768dbbf46c4SNavdeep Parhar M_ASSERTPKTHDR(m0); 1769733b9277SNavdeep Parhar return (m0); 1770733b9277SNavdeep Parhar } 1771733b9277SNavdeep Parhar 1772733b9277SNavdeep Parhar static int 1773733b9277SNavdeep Parhar t4_eth_rx(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0) 1774733b9277SNavdeep Parhar { 17753c51d154SNavdeep Parhar struct sge_rxq *rxq = iq_to_rxq(iq); 1776733b9277SNavdeep Parhar struct ifnet *ifp = rxq->ifp; 177790e7434aSNavdeep Parhar struct adapter *sc = iq->adapter; 1778733b9277SNavdeep Parhar const struct cpl_rx_pkt *cpl = (const void *)(rss + 1); 1779a1ea9a82SNavdeep Parhar #if defined(INET) || defined(INET6) 1780733b9277SNavdeep Parhar struct lro_ctrl *lro = &rxq->lro; 1781733b9277SNavdeep Parhar #endif 178270ca6229SNavdeep Parhar static const int sw_hashtype[4][2] = { 178370ca6229SNavdeep Parhar {M_HASHTYPE_NONE, M_HASHTYPE_NONE}, 178470ca6229SNavdeep Parhar {M_HASHTYPE_RSS_IPV4, M_HASHTYPE_RSS_IPV6}, 178570ca6229SNavdeep Parhar {M_HASHTYPE_RSS_TCP_IPV4, M_HASHTYPE_RSS_TCP_IPV6}, 178670ca6229SNavdeep Parhar {M_HASHTYPE_RSS_UDP_IPV4, M_HASHTYPE_RSS_UDP_IPV6}, 178770ca6229SNavdeep Parhar }; 1788733b9277SNavdeep Parhar 1789733b9277SNavdeep Parhar KASSERT(m0 != NULL, ("%s: no payload with opcode %02x", __func__, 1790733b9277SNavdeep Parhar rss->opcode)); 1791733b9277SNavdeep Parhar 179290e7434aSNavdeep Parhar m0->m_pkthdr.len -= sc->params.sge.fl_pktshift; 179390e7434aSNavdeep Parhar m0->m_len -= sc->params.sge.fl_pktshift; 179490e7434aSNavdeep Parhar m0->m_data += sc->params.sge.fl_pktshift; 179554e4ee71SNavdeep Parhar 179654e4ee71SNavdeep Parhar m0->m_pkthdr.rcvif = ifp; 179770ca6229SNavdeep Parhar M_HASHTYPE_SET(m0, sw_hashtype[rss->hash_type][rss->ipv6]); 1798273ef991SNavdeep Parhar m0->m_pkthdr.flowid = be32toh(rss->hash_val); 179954e4ee71SNavdeep Parhar 18001de8c69dSNavdeep Parhar if (cpl->csum_calc && !(cpl->err_vec & sc->params.tp.err_vec_mask)) { 18019600bf00SNavdeep Parhar if (ifp->if_capenable & IFCAP_RXCSUM && 18029600bf00SNavdeep Parhar cpl->l2info & htobe32(F_RXF_IP)) { 1803932b1a5fSNavdeep Parhar m0->m_pkthdr.csum_flags = (CSUM_IP_CHECKED | 180454e4ee71SNavdeep Parhar CSUM_IP_VALID | CSUM_DATA_VALID | CSUM_PSEUDO_HDR); 18059600bf00SNavdeep Parhar rxq->rxcsum++; 18069600bf00SNavdeep Parhar } else if (ifp->if_capenable & IFCAP_RXCSUM_IPV6 && 18079600bf00SNavdeep Parhar cpl->l2info & htobe32(F_RXF_IP6)) { 1808932b1a5fSNavdeep Parhar m0->m_pkthdr.csum_flags = (CSUM_DATA_VALID_IPV6 | 18099600bf00SNavdeep Parhar CSUM_PSEUDO_HDR); 18109600bf00SNavdeep Parhar rxq->rxcsum++; 18119600bf00SNavdeep Parhar } 18129600bf00SNavdeep Parhar 18139600bf00SNavdeep Parhar if (__predict_false(cpl->ip_frag)) 181454e4ee71SNavdeep Parhar m0->m_pkthdr.csum_data = be16toh(cpl->csum); 181554e4ee71SNavdeep Parhar else 181654e4ee71SNavdeep Parhar m0->m_pkthdr.csum_data = 0xffff; 181754e4ee71SNavdeep Parhar } 181854e4ee71SNavdeep Parhar 181954e4ee71SNavdeep Parhar if (cpl->vlan_ex) { 182054e4ee71SNavdeep Parhar m0->m_pkthdr.ether_vtag = be16toh(cpl->vlan); 182154e4ee71SNavdeep Parhar m0->m_flags |= M_VLANTAG; 182254e4ee71SNavdeep Parhar rxq->vlan_extraction++; 182354e4ee71SNavdeep Parhar } 182454e4ee71SNavdeep Parhar 1825a1ea9a82SNavdeep Parhar #if defined(INET) || defined(INET6) 182646f48ee5SNavdeep Parhar if (iq->flags & IQ_LRO_ENABLED) { 182746f48ee5SNavdeep Parhar if (sort_before_lro(lro)) { 182846f48ee5SNavdeep Parhar tcp_lro_queue_mbuf(lro, m0); 182946f48ee5SNavdeep Parhar return (0); /* queued for sort, then LRO */ 183046f48ee5SNavdeep Parhar } 183146f48ee5SNavdeep Parhar if (tcp_lro_rx(lro, m0, 0) == 0) 183246f48ee5SNavdeep Parhar return (0); /* queued for LRO */ 183346f48ee5SNavdeep Parhar } 183454e4ee71SNavdeep Parhar #endif 18357d29df59SNavdeep Parhar ifp->if_input(ifp, m0); 183654e4ee71SNavdeep Parhar 1837733b9277SNavdeep Parhar return (0); 183854e4ee71SNavdeep Parhar } 183954e4ee71SNavdeep Parhar 1840733b9277SNavdeep Parhar /* 18417951040fSNavdeep Parhar * Must drain the wrq or make sure that someone else will. 18427951040fSNavdeep Parhar */ 18437951040fSNavdeep Parhar static void 18447951040fSNavdeep Parhar wrq_tx_drain(void *arg, int n) 18457951040fSNavdeep Parhar { 18467951040fSNavdeep Parhar struct sge_wrq *wrq = arg; 18477951040fSNavdeep Parhar struct sge_eq *eq = &wrq->eq; 18487951040fSNavdeep Parhar 18497951040fSNavdeep Parhar EQ_LOCK(eq); 18507951040fSNavdeep Parhar if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 18517951040fSNavdeep Parhar drain_wrq_wr_list(wrq->adapter, wrq); 18527951040fSNavdeep Parhar EQ_UNLOCK(eq); 18537951040fSNavdeep Parhar } 18547951040fSNavdeep Parhar 18557951040fSNavdeep Parhar static void 18567951040fSNavdeep Parhar drain_wrq_wr_list(struct adapter *sc, struct sge_wrq *wrq) 18577951040fSNavdeep Parhar { 18587951040fSNavdeep Parhar struct sge_eq *eq = &wrq->eq; 18597951040fSNavdeep Parhar u_int available, dbdiff; /* # of hardware descriptors */ 18607951040fSNavdeep Parhar u_int n; 18617951040fSNavdeep Parhar struct wrqe *wr; 18627951040fSNavdeep Parhar struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */ 18637951040fSNavdeep Parhar 18647951040fSNavdeep Parhar EQ_LOCK_ASSERT_OWNED(eq); 18657951040fSNavdeep Parhar MPASS(TAILQ_EMPTY(&wrq->incomplete_wrs)); 18667951040fSNavdeep Parhar wr = STAILQ_FIRST(&wrq->wr_list); 18677951040fSNavdeep Parhar MPASS(wr != NULL); /* Must be called with something useful to do */ 1868cda2ab0eSNavdeep Parhar MPASS(eq->pidx == eq->dbidx); 1869cda2ab0eSNavdeep Parhar dbdiff = 0; 18707951040fSNavdeep Parhar 18717951040fSNavdeep Parhar do { 18727951040fSNavdeep Parhar eq->cidx = read_hw_cidx(eq); 18737951040fSNavdeep Parhar if (eq->pidx == eq->cidx) 18747951040fSNavdeep Parhar available = eq->sidx - 1; 18757951040fSNavdeep Parhar else 18767951040fSNavdeep Parhar available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 18777951040fSNavdeep Parhar 18787951040fSNavdeep Parhar MPASS(wr->wrq == wrq); 18797951040fSNavdeep Parhar n = howmany(wr->wr_len, EQ_ESIZE); 18807951040fSNavdeep Parhar if (available < n) 1881cda2ab0eSNavdeep Parhar break; 18827951040fSNavdeep Parhar 18837951040fSNavdeep Parhar dst = (void *)&eq->desc[eq->pidx]; 18847951040fSNavdeep Parhar if (__predict_true(eq->sidx - eq->pidx > n)) { 18857951040fSNavdeep Parhar /* Won't wrap, won't end exactly at the status page. */ 18867951040fSNavdeep Parhar bcopy(&wr->wr[0], dst, wr->wr_len); 18877951040fSNavdeep Parhar eq->pidx += n; 18887951040fSNavdeep Parhar } else { 18897951040fSNavdeep Parhar int first_portion = (eq->sidx - eq->pidx) * EQ_ESIZE; 18907951040fSNavdeep Parhar 18917951040fSNavdeep Parhar bcopy(&wr->wr[0], dst, first_portion); 18927951040fSNavdeep Parhar if (wr->wr_len > first_portion) { 18937951040fSNavdeep Parhar bcopy(&wr->wr[first_portion], &eq->desc[0], 18947951040fSNavdeep Parhar wr->wr_len - first_portion); 18957951040fSNavdeep Parhar } 18967951040fSNavdeep Parhar eq->pidx = n - (eq->sidx - eq->pidx); 18977951040fSNavdeep Parhar } 18980459a175SNavdeep Parhar wrq->tx_wrs_copied++; 18997951040fSNavdeep Parhar 19007951040fSNavdeep Parhar if (available < eq->sidx / 4 && 19017951040fSNavdeep Parhar atomic_cmpset_int(&eq->equiq, 0, 1)) { 19027951040fSNavdeep Parhar dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ | 19037951040fSNavdeep Parhar F_FW_WR_EQUEQ); 19047951040fSNavdeep Parhar eq->equeqidx = eq->pidx; 19057951040fSNavdeep Parhar } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 32) { 19067951040fSNavdeep Parhar dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ); 19077951040fSNavdeep Parhar eq->equeqidx = eq->pidx; 19087951040fSNavdeep Parhar } 19097951040fSNavdeep Parhar 19107951040fSNavdeep Parhar dbdiff += n; 19117951040fSNavdeep Parhar if (dbdiff >= 16) { 19127951040fSNavdeep Parhar ring_eq_db(sc, eq, dbdiff); 19137951040fSNavdeep Parhar dbdiff = 0; 19147951040fSNavdeep Parhar } 19157951040fSNavdeep Parhar 19167951040fSNavdeep Parhar STAILQ_REMOVE_HEAD(&wrq->wr_list, link); 19177951040fSNavdeep Parhar free_wrqe(wr); 19187951040fSNavdeep Parhar MPASS(wrq->nwr_pending > 0); 19197951040fSNavdeep Parhar wrq->nwr_pending--; 19207951040fSNavdeep Parhar MPASS(wrq->ndesc_needed >= n); 19217951040fSNavdeep Parhar wrq->ndesc_needed -= n; 19227951040fSNavdeep Parhar } while ((wr = STAILQ_FIRST(&wrq->wr_list)) != NULL); 19237951040fSNavdeep Parhar 19247951040fSNavdeep Parhar if (dbdiff) 19257951040fSNavdeep Parhar ring_eq_db(sc, eq, dbdiff); 19267951040fSNavdeep Parhar } 19277951040fSNavdeep Parhar 19287951040fSNavdeep Parhar /* 1929733b9277SNavdeep Parhar * Doesn't fail. Holds on to work requests it can't send right away. 1930733b9277SNavdeep Parhar */ 193109fe6320SNavdeep Parhar void 193209fe6320SNavdeep Parhar t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, struct wrqe *wr) 1933733b9277SNavdeep Parhar { 1934733b9277SNavdeep Parhar #ifdef INVARIANTS 19357951040fSNavdeep Parhar struct sge_eq *eq = &wrq->eq; 1936733b9277SNavdeep Parhar #endif 1937733b9277SNavdeep Parhar 19387951040fSNavdeep Parhar EQ_LOCK_ASSERT_OWNED(eq); 19397951040fSNavdeep Parhar MPASS(wr != NULL); 19407951040fSNavdeep Parhar MPASS(wr->wr_len > 0 && wr->wr_len <= SGE_MAX_WR_LEN); 19417951040fSNavdeep Parhar MPASS((wr->wr_len & 0x7) == 0); 1942733b9277SNavdeep Parhar 19437951040fSNavdeep Parhar STAILQ_INSERT_TAIL(&wrq->wr_list, wr, link); 19447951040fSNavdeep Parhar wrq->nwr_pending++; 19457951040fSNavdeep Parhar wrq->ndesc_needed += howmany(wr->wr_len, EQ_ESIZE); 1946733b9277SNavdeep Parhar 19477951040fSNavdeep Parhar if (!TAILQ_EMPTY(&wrq->incomplete_wrs)) 19487951040fSNavdeep Parhar return; /* commit_wrq_wr will drain wr_list as well. */ 1949733b9277SNavdeep Parhar 19507951040fSNavdeep Parhar drain_wrq_wr_list(sc, wrq); 1951733b9277SNavdeep Parhar 19527951040fSNavdeep Parhar /* Doorbell must have caught up to the pidx. */ 19537951040fSNavdeep Parhar MPASS(eq->pidx == eq->dbidx); 195454e4ee71SNavdeep Parhar } 195554e4ee71SNavdeep Parhar 195654e4ee71SNavdeep Parhar void 195754e4ee71SNavdeep Parhar t4_update_fl_bufsize(struct ifnet *ifp) 195854e4ee71SNavdeep Parhar { 1959fe2ebb76SJohn Baldwin struct vi_info *vi = ifp->if_softc; 1960fe2ebb76SJohn Baldwin struct adapter *sc = vi->pi->adapter; 196154e4ee71SNavdeep Parhar struct sge_rxq *rxq; 19626eb3180fSNavdeep Parhar #ifdef TCP_OFFLOAD 19636eb3180fSNavdeep Parhar struct sge_ofld_rxq *ofld_rxq; 19646eb3180fSNavdeep Parhar #endif 196554e4ee71SNavdeep Parhar struct sge_fl *fl; 196638035ed6SNavdeep Parhar int i, maxp, mtu = ifp->if_mtu; 196754e4ee71SNavdeep Parhar 196838035ed6SNavdeep Parhar maxp = mtu_to_max_payload(sc, mtu, 0); 1969fe2ebb76SJohn Baldwin for_each_rxq(vi, i, rxq) { 197054e4ee71SNavdeep Parhar fl = &rxq->fl; 197154e4ee71SNavdeep Parhar 197254e4ee71SNavdeep Parhar FL_LOCK(fl); 197338035ed6SNavdeep Parhar find_best_refill_source(sc, fl, maxp); 197454e4ee71SNavdeep Parhar FL_UNLOCK(fl); 197554e4ee71SNavdeep Parhar } 19766eb3180fSNavdeep Parhar #ifdef TCP_OFFLOAD 197738035ed6SNavdeep Parhar maxp = mtu_to_max_payload(sc, mtu, 1); 1978fe2ebb76SJohn Baldwin for_each_ofld_rxq(vi, i, ofld_rxq) { 19796eb3180fSNavdeep Parhar fl = &ofld_rxq->fl; 19806eb3180fSNavdeep Parhar 19816eb3180fSNavdeep Parhar FL_LOCK(fl); 198238035ed6SNavdeep Parhar find_best_refill_source(sc, fl, maxp); 19836eb3180fSNavdeep Parhar FL_UNLOCK(fl); 19846eb3180fSNavdeep Parhar } 19856eb3180fSNavdeep Parhar #endif 198654e4ee71SNavdeep Parhar } 198754e4ee71SNavdeep Parhar 19887951040fSNavdeep Parhar static inline int 19897951040fSNavdeep Parhar mbuf_nsegs(struct mbuf *m) 1990733b9277SNavdeep Parhar { 19910835ddc7SNavdeep Parhar 19927951040fSNavdeep Parhar M_ASSERTPKTHDR(m); 19937951040fSNavdeep Parhar KASSERT(m->m_pkthdr.l5hlen > 0, 19947951040fSNavdeep Parhar ("%s: mbuf %p missing information on # of segments.", __func__, m)); 19957951040fSNavdeep Parhar 19967951040fSNavdeep Parhar return (m->m_pkthdr.l5hlen); 19977951040fSNavdeep Parhar } 19987951040fSNavdeep Parhar 19997951040fSNavdeep Parhar static inline void 20007951040fSNavdeep Parhar set_mbuf_nsegs(struct mbuf *m, uint8_t nsegs) 20017951040fSNavdeep Parhar { 20027951040fSNavdeep Parhar 20037951040fSNavdeep Parhar M_ASSERTPKTHDR(m); 20047951040fSNavdeep Parhar m->m_pkthdr.l5hlen = nsegs; 20057951040fSNavdeep Parhar } 20067951040fSNavdeep Parhar 20077951040fSNavdeep Parhar static inline int 20087951040fSNavdeep Parhar mbuf_len16(struct mbuf *m) 20097951040fSNavdeep Parhar { 20107951040fSNavdeep Parhar int n; 20117951040fSNavdeep Parhar 20127951040fSNavdeep Parhar M_ASSERTPKTHDR(m); 20137951040fSNavdeep Parhar n = m->m_pkthdr.PH_loc.eight[0]; 20147951040fSNavdeep Parhar MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16); 20157951040fSNavdeep Parhar 20167951040fSNavdeep Parhar return (n); 20177951040fSNavdeep Parhar } 20187951040fSNavdeep Parhar 20197951040fSNavdeep Parhar static inline void 20207951040fSNavdeep Parhar set_mbuf_len16(struct mbuf *m, uint8_t len16) 20217951040fSNavdeep Parhar { 20227951040fSNavdeep Parhar 20237951040fSNavdeep Parhar M_ASSERTPKTHDR(m); 20247951040fSNavdeep Parhar m->m_pkthdr.PH_loc.eight[0] = len16; 20257951040fSNavdeep Parhar } 20267951040fSNavdeep Parhar 20277951040fSNavdeep Parhar static inline int 20287951040fSNavdeep Parhar needs_tso(struct mbuf *m) 20297951040fSNavdeep Parhar { 20307951040fSNavdeep Parhar 20317951040fSNavdeep Parhar M_ASSERTPKTHDR(m); 20327951040fSNavdeep Parhar 20337951040fSNavdeep Parhar if (m->m_pkthdr.csum_flags & CSUM_TSO) { 20347951040fSNavdeep Parhar KASSERT(m->m_pkthdr.tso_segsz > 0, 20357951040fSNavdeep Parhar ("%s: TSO requested in mbuf %p but MSS not provided", 20367951040fSNavdeep Parhar __func__, m)); 20377951040fSNavdeep Parhar return (1); 20387951040fSNavdeep Parhar } 20397951040fSNavdeep Parhar 20407951040fSNavdeep Parhar return (0); 20417951040fSNavdeep Parhar } 20427951040fSNavdeep Parhar 20437951040fSNavdeep Parhar static inline int 20447951040fSNavdeep Parhar needs_l3_csum(struct mbuf *m) 20457951040fSNavdeep Parhar { 20467951040fSNavdeep Parhar 20477951040fSNavdeep Parhar M_ASSERTPKTHDR(m); 20487951040fSNavdeep Parhar 20497951040fSNavdeep Parhar if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TSO)) 20507951040fSNavdeep Parhar return (1); 20517951040fSNavdeep Parhar return (0); 20527951040fSNavdeep Parhar } 20537951040fSNavdeep Parhar 20547951040fSNavdeep Parhar static inline int 20557951040fSNavdeep Parhar needs_l4_csum(struct mbuf *m) 20567951040fSNavdeep Parhar { 20577951040fSNavdeep Parhar 20587951040fSNavdeep Parhar M_ASSERTPKTHDR(m); 20597951040fSNavdeep Parhar 20607951040fSNavdeep Parhar if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_UDP_IPV6 | 20617951040fSNavdeep Parhar CSUM_TCP_IPV6 | CSUM_TSO)) 20627951040fSNavdeep Parhar return (1); 20637951040fSNavdeep Parhar return (0); 20647951040fSNavdeep Parhar } 20657951040fSNavdeep Parhar 20667951040fSNavdeep Parhar static inline int 20677951040fSNavdeep Parhar needs_vlan_insertion(struct mbuf *m) 20687951040fSNavdeep Parhar { 20697951040fSNavdeep Parhar 20707951040fSNavdeep Parhar M_ASSERTPKTHDR(m); 20717951040fSNavdeep Parhar 20727951040fSNavdeep Parhar if (m->m_flags & M_VLANTAG) { 20737951040fSNavdeep Parhar KASSERT(m->m_pkthdr.ether_vtag != 0, 20747951040fSNavdeep Parhar ("%s: HWVLAN requested in mbuf %p but tag not provided", 20757951040fSNavdeep Parhar __func__, m)); 20767951040fSNavdeep Parhar return (1); 20777951040fSNavdeep Parhar } 20787951040fSNavdeep Parhar return (0); 20797951040fSNavdeep Parhar } 20807951040fSNavdeep Parhar 20817951040fSNavdeep Parhar static void * 20827951040fSNavdeep Parhar m_advance(struct mbuf **pm, int *poffset, int len) 20837951040fSNavdeep Parhar { 20847951040fSNavdeep Parhar struct mbuf *m = *pm; 20857951040fSNavdeep Parhar int offset = *poffset; 20867951040fSNavdeep Parhar uintptr_t p = 0; 20877951040fSNavdeep Parhar 20887951040fSNavdeep Parhar MPASS(len > 0); 20897951040fSNavdeep Parhar 2090e06ab612SJohn Baldwin for (;;) { 20917951040fSNavdeep Parhar if (offset + len < m->m_len) { 20927951040fSNavdeep Parhar offset += len; 20937951040fSNavdeep Parhar p = mtod(m, uintptr_t) + offset; 20947951040fSNavdeep Parhar break; 20957951040fSNavdeep Parhar } 20967951040fSNavdeep Parhar len -= m->m_len - offset; 20977951040fSNavdeep Parhar m = m->m_next; 20987951040fSNavdeep Parhar offset = 0; 20997951040fSNavdeep Parhar MPASS(m != NULL); 21007951040fSNavdeep Parhar } 21017951040fSNavdeep Parhar *poffset = offset; 21027951040fSNavdeep Parhar *pm = m; 21037951040fSNavdeep Parhar return ((void *)p); 21047951040fSNavdeep Parhar } 21057951040fSNavdeep Parhar 21067951040fSNavdeep Parhar /* 21077951040fSNavdeep Parhar * Can deal with empty mbufs in the chain that have m_len = 0, but the chain 21087951040fSNavdeep Parhar * must have at least one mbuf that's not empty. 21097951040fSNavdeep Parhar */ 21107951040fSNavdeep Parhar static inline int 21117951040fSNavdeep Parhar count_mbuf_nsegs(struct mbuf *m) 21127951040fSNavdeep Parhar { 211377e9044cSNavdeep Parhar vm_paddr_t lastb, next; 211477e9044cSNavdeep Parhar vm_offset_t va; 21157951040fSNavdeep Parhar int len, nsegs; 21167951040fSNavdeep Parhar 21177951040fSNavdeep Parhar MPASS(m != NULL); 21187951040fSNavdeep Parhar 21197951040fSNavdeep Parhar nsegs = 0; 212077e9044cSNavdeep Parhar lastb = 0; 21217951040fSNavdeep Parhar for (; m; m = m->m_next) { 21227951040fSNavdeep Parhar 21237951040fSNavdeep Parhar len = m->m_len; 21247951040fSNavdeep Parhar if (__predict_false(len == 0)) 21257951040fSNavdeep Parhar continue; 212677e9044cSNavdeep Parhar va = mtod(m, vm_offset_t); 212777e9044cSNavdeep Parhar next = pmap_kextract(va); 212877e9044cSNavdeep Parhar nsegs += sglist_count(m->m_data, len); 212977e9044cSNavdeep Parhar if (lastb + 1 == next) 21307951040fSNavdeep Parhar nsegs--; 213177e9044cSNavdeep Parhar lastb = pmap_kextract(va + len - 1); 21327951040fSNavdeep Parhar } 21337951040fSNavdeep Parhar 21347951040fSNavdeep Parhar MPASS(nsegs > 0); 21357951040fSNavdeep Parhar return (nsegs); 21367951040fSNavdeep Parhar } 21377951040fSNavdeep Parhar 21387951040fSNavdeep Parhar /* 21397951040fSNavdeep Parhar * Analyze the mbuf to determine its tx needs. The mbuf passed in may change: 21407951040fSNavdeep Parhar * a) caller can assume it's been freed if this function returns with an error. 21417951040fSNavdeep Parhar * b) it may get defragged up if the gather list is too long for the hardware. 21427951040fSNavdeep Parhar */ 21437951040fSNavdeep Parhar int 21446af45170SJohn Baldwin parse_pkt(struct adapter *sc, struct mbuf **mp) 21457951040fSNavdeep Parhar { 21467951040fSNavdeep Parhar struct mbuf *m0 = *mp, *m; 21477951040fSNavdeep Parhar int rc, nsegs, defragged = 0, offset; 21487951040fSNavdeep Parhar struct ether_header *eh; 21497951040fSNavdeep Parhar void *l3hdr; 21507951040fSNavdeep Parhar #if defined(INET) || defined(INET6) 21517951040fSNavdeep Parhar struct tcphdr *tcp; 21527951040fSNavdeep Parhar #endif 21537951040fSNavdeep Parhar uint16_t eh_type; 21547951040fSNavdeep Parhar 21557951040fSNavdeep Parhar M_ASSERTPKTHDR(m0); 21567951040fSNavdeep Parhar if (__predict_false(m0->m_pkthdr.len < ETHER_HDR_LEN)) { 21577951040fSNavdeep Parhar rc = EINVAL; 21587951040fSNavdeep Parhar fail: 21597951040fSNavdeep Parhar m_freem(m0); 21607951040fSNavdeep Parhar *mp = NULL; 21617951040fSNavdeep Parhar return (rc); 21627951040fSNavdeep Parhar } 21637951040fSNavdeep Parhar restart: 21647951040fSNavdeep Parhar /* 21657951040fSNavdeep Parhar * First count the number of gather list segments in the payload. 21667951040fSNavdeep Parhar * Defrag the mbuf if nsegs exceeds the hardware limit. 21677951040fSNavdeep Parhar */ 21687951040fSNavdeep Parhar M_ASSERTPKTHDR(m0); 21697951040fSNavdeep Parhar MPASS(m0->m_pkthdr.len > 0); 21707951040fSNavdeep Parhar nsegs = count_mbuf_nsegs(m0); 21717951040fSNavdeep Parhar if (nsegs > (needs_tso(m0) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS)) { 21727951040fSNavdeep Parhar if (defragged++ > 0 || (m = m_defrag(m0, M_NOWAIT)) == NULL) { 21737951040fSNavdeep Parhar rc = EFBIG; 21747951040fSNavdeep Parhar goto fail; 21757951040fSNavdeep Parhar } 21767951040fSNavdeep Parhar *mp = m0 = m; /* update caller's copy after defrag */ 21777951040fSNavdeep Parhar goto restart; 21787951040fSNavdeep Parhar } 21797951040fSNavdeep Parhar 21807951040fSNavdeep Parhar if (__predict_false(nsegs > 2 && m0->m_pkthdr.len <= MHLEN)) { 21817951040fSNavdeep Parhar m0 = m_pullup(m0, m0->m_pkthdr.len); 21827951040fSNavdeep Parhar if (m0 == NULL) { 21837951040fSNavdeep Parhar /* Should have left well enough alone. */ 21847951040fSNavdeep Parhar rc = EFBIG; 21857951040fSNavdeep Parhar goto fail; 21867951040fSNavdeep Parhar } 21877951040fSNavdeep Parhar *mp = m0; /* update caller's copy after pullup */ 21887951040fSNavdeep Parhar goto restart; 21897951040fSNavdeep Parhar } 21907951040fSNavdeep Parhar set_mbuf_nsegs(m0, nsegs); 21916af45170SJohn Baldwin if (sc->flags & IS_VF) 21926af45170SJohn Baldwin set_mbuf_len16(m0, txpkt_vm_len16(nsegs, needs_tso(m0))); 21936af45170SJohn Baldwin else 21947951040fSNavdeep Parhar set_mbuf_len16(m0, txpkt_len16(nsegs, needs_tso(m0))); 21957951040fSNavdeep Parhar 21966af45170SJohn Baldwin if (!needs_tso(m0) && 21976af45170SJohn Baldwin !(sc->flags & IS_VF && (needs_l3_csum(m0) || needs_l4_csum(m0)))) 21987951040fSNavdeep Parhar return (0); 21997951040fSNavdeep Parhar 22007951040fSNavdeep Parhar m = m0; 22017951040fSNavdeep Parhar eh = mtod(m, struct ether_header *); 22027951040fSNavdeep Parhar eh_type = ntohs(eh->ether_type); 22037951040fSNavdeep Parhar if (eh_type == ETHERTYPE_VLAN) { 22047951040fSNavdeep Parhar struct ether_vlan_header *evh = (void *)eh; 22057951040fSNavdeep Parhar 22067951040fSNavdeep Parhar eh_type = ntohs(evh->evl_proto); 22077951040fSNavdeep Parhar m0->m_pkthdr.l2hlen = sizeof(*evh); 22087951040fSNavdeep Parhar } else 22097951040fSNavdeep Parhar m0->m_pkthdr.l2hlen = sizeof(*eh); 22107951040fSNavdeep Parhar 22117951040fSNavdeep Parhar offset = 0; 22127951040fSNavdeep Parhar l3hdr = m_advance(&m, &offset, m0->m_pkthdr.l2hlen); 22137951040fSNavdeep Parhar 22147951040fSNavdeep Parhar switch (eh_type) { 22157951040fSNavdeep Parhar #ifdef INET6 22167951040fSNavdeep Parhar case ETHERTYPE_IPV6: 22177951040fSNavdeep Parhar { 22187951040fSNavdeep Parhar struct ip6_hdr *ip6 = l3hdr; 22197951040fSNavdeep Parhar 22206af45170SJohn Baldwin MPASS(!needs_tso(m0) || ip6->ip6_nxt == IPPROTO_TCP); 22217951040fSNavdeep Parhar 22227951040fSNavdeep Parhar m0->m_pkthdr.l3hlen = sizeof(*ip6); 22237951040fSNavdeep Parhar break; 22247951040fSNavdeep Parhar } 22257951040fSNavdeep Parhar #endif 22267951040fSNavdeep Parhar #ifdef INET 22277951040fSNavdeep Parhar case ETHERTYPE_IP: 22287951040fSNavdeep Parhar { 22297951040fSNavdeep Parhar struct ip *ip = l3hdr; 22307951040fSNavdeep Parhar 22317951040fSNavdeep Parhar m0->m_pkthdr.l3hlen = ip->ip_hl * 4; 22327951040fSNavdeep Parhar break; 22337951040fSNavdeep Parhar } 22347951040fSNavdeep Parhar #endif 22357951040fSNavdeep Parhar default: 22367951040fSNavdeep Parhar panic("%s: ethertype 0x%04x unknown. if_cxgbe must be compiled" 22377951040fSNavdeep Parhar " with the same INET/INET6 options as the kernel.", 22387951040fSNavdeep Parhar __func__, eh_type); 22397951040fSNavdeep Parhar } 22407951040fSNavdeep Parhar 22417951040fSNavdeep Parhar #if defined(INET) || defined(INET6) 22426af45170SJohn Baldwin if (needs_tso(m0)) { 22437951040fSNavdeep Parhar tcp = m_advance(&m, &offset, m0->m_pkthdr.l3hlen); 22447951040fSNavdeep Parhar m0->m_pkthdr.l4hlen = tcp->th_off * 4; 22456af45170SJohn Baldwin } 22467951040fSNavdeep Parhar #endif 22477951040fSNavdeep Parhar MPASS(m0 == *mp); 22487951040fSNavdeep Parhar return (0); 22497951040fSNavdeep Parhar } 22507951040fSNavdeep Parhar 22517951040fSNavdeep Parhar void * 22527951040fSNavdeep Parhar start_wrq_wr(struct sge_wrq *wrq, int len16, struct wrq_cookie *cookie) 22537951040fSNavdeep Parhar { 22547951040fSNavdeep Parhar struct sge_eq *eq = &wrq->eq; 22557951040fSNavdeep Parhar struct adapter *sc = wrq->adapter; 22567951040fSNavdeep Parhar int ndesc, available; 22577951040fSNavdeep Parhar struct wrqe *wr; 22587951040fSNavdeep Parhar void *w; 22597951040fSNavdeep Parhar 22607951040fSNavdeep Parhar MPASS(len16 > 0); 22617951040fSNavdeep Parhar ndesc = howmany(len16, EQ_ESIZE / 16); 22627951040fSNavdeep Parhar MPASS(ndesc > 0 && ndesc <= SGE_MAX_WR_NDESC); 22637951040fSNavdeep Parhar 22647951040fSNavdeep Parhar EQ_LOCK(eq); 22657951040fSNavdeep Parhar 22668d6ae10aSNavdeep Parhar if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 22677951040fSNavdeep Parhar drain_wrq_wr_list(sc, wrq); 22687951040fSNavdeep Parhar 22697951040fSNavdeep Parhar if (!STAILQ_EMPTY(&wrq->wr_list)) { 22707951040fSNavdeep Parhar slowpath: 22717951040fSNavdeep Parhar EQ_UNLOCK(eq); 22727951040fSNavdeep Parhar wr = alloc_wrqe(len16 * 16, wrq); 22737951040fSNavdeep Parhar if (__predict_false(wr == NULL)) 22747951040fSNavdeep Parhar return (NULL); 22757951040fSNavdeep Parhar cookie->pidx = -1; 22767951040fSNavdeep Parhar cookie->ndesc = ndesc; 22777951040fSNavdeep Parhar return (&wr->wr); 22787951040fSNavdeep Parhar } 22797951040fSNavdeep Parhar 22807951040fSNavdeep Parhar eq->cidx = read_hw_cidx(eq); 22817951040fSNavdeep Parhar if (eq->pidx == eq->cidx) 22827951040fSNavdeep Parhar available = eq->sidx - 1; 22837951040fSNavdeep Parhar else 22847951040fSNavdeep Parhar available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 22857951040fSNavdeep Parhar if (available < ndesc) 22867951040fSNavdeep Parhar goto slowpath; 22877951040fSNavdeep Parhar 22887951040fSNavdeep Parhar cookie->pidx = eq->pidx; 22897951040fSNavdeep Parhar cookie->ndesc = ndesc; 22907951040fSNavdeep Parhar TAILQ_INSERT_TAIL(&wrq->incomplete_wrs, cookie, link); 22917951040fSNavdeep Parhar 22927951040fSNavdeep Parhar w = &eq->desc[eq->pidx]; 22937951040fSNavdeep Parhar IDXINCR(eq->pidx, ndesc, eq->sidx); 2294f50c49ccSNavdeep Parhar if (__predict_false(cookie->pidx + ndesc > eq->sidx)) { 22957951040fSNavdeep Parhar w = &wrq->ss[0]; 22967951040fSNavdeep Parhar wrq->ss_pidx = cookie->pidx; 22977951040fSNavdeep Parhar wrq->ss_len = len16 * 16; 22987951040fSNavdeep Parhar } 22997951040fSNavdeep Parhar 23007951040fSNavdeep Parhar EQ_UNLOCK(eq); 23017951040fSNavdeep Parhar 23027951040fSNavdeep Parhar return (w); 23037951040fSNavdeep Parhar } 23047951040fSNavdeep Parhar 23057951040fSNavdeep Parhar void 23067951040fSNavdeep Parhar commit_wrq_wr(struct sge_wrq *wrq, void *w, struct wrq_cookie *cookie) 23077951040fSNavdeep Parhar { 23087951040fSNavdeep Parhar struct sge_eq *eq = &wrq->eq; 23097951040fSNavdeep Parhar struct adapter *sc = wrq->adapter; 23107951040fSNavdeep Parhar int ndesc, pidx; 23117951040fSNavdeep Parhar struct wrq_cookie *prev, *next; 23127951040fSNavdeep Parhar 23137951040fSNavdeep Parhar if (cookie->pidx == -1) { 23147951040fSNavdeep Parhar struct wrqe *wr = __containerof(w, struct wrqe, wr); 23157951040fSNavdeep Parhar 23167951040fSNavdeep Parhar t4_wrq_tx(sc, wr); 23177951040fSNavdeep Parhar return; 23187951040fSNavdeep Parhar } 23197951040fSNavdeep Parhar 23207951040fSNavdeep Parhar if (__predict_false(w == &wrq->ss[0])) { 23217951040fSNavdeep Parhar int n = (eq->sidx - wrq->ss_pidx) * EQ_ESIZE; 23227951040fSNavdeep Parhar 23237951040fSNavdeep Parhar MPASS(wrq->ss_len > n); /* WR had better wrap around. */ 23247951040fSNavdeep Parhar bcopy(&wrq->ss[0], &eq->desc[wrq->ss_pidx], n); 23257951040fSNavdeep Parhar bcopy(&wrq->ss[n], &eq->desc[0], wrq->ss_len - n); 23267951040fSNavdeep Parhar wrq->tx_wrs_ss++; 23277951040fSNavdeep Parhar } else 23287951040fSNavdeep Parhar wrq->tx_wrs_direct++; 23297951040fSNavdeep Parhar 23307951040fSNavdeep Parhar EQ_LOCK(eq); 23318d6ae10aSNavdeep Parhar ndesc = cookie->ndesc; /* Can be more than SGE_MAX_WR_NDESC here. */ 23328d6ae10aSNavdeep Parhar pidx = cookie->pidx; 23338d6ae10aSNavdeep Parhar MPASS(pidx >= 0 && pidx < eq->sidx); 23347951040fSNavdeep Parhar prev = TAILQ_PREV(cookie, wrq_incomplete_wrs, link); 23357951040fSNavdeep Parhar next = TAILQ_NEXT(cookie, link); 23367951040fSNavdeep Parhar if (prev == NULL) { 23377951040fSNavdeep Parhar MPASS(pidx == eq->dbidx); 23387951040fSNavdeep Parhar if (next == NULL || ndesc >= 16) 23397951040fSNavdeep Parhar ring_eq_db(wrq->adapter, eq, ndesc); 23407951040fSNavdeep Parhar else { 23417951040fSNavdeep Parhar MPASS(IDXDIFF(next->pidx, pidx, eq->sidx) == ndesc); 23427951040fSNavdeep Parhar next->pidx = pidx; 23437951040fSNavdeep Parhar next->ndesc += ndesc; 23447951040fSNavdeep Parhar } 23457951040fSNavdeep Parhar } else { 23467951040fSNavdeep Parhar MPASS(IDXDIFF(pidx, prev->pidx, eq->sidx) == prev->ndesc); 23477951040fSNavdeep Parhar prev->ndesc += ndesc; 23487951040fSNavdeep Parhar } 23497951040fSNavdeep Parhar TAILQ_REMOVE(&wrq->incomplete_wrs, cookie, link); 23507951040fSNavdeep Parhar 23517951040fSNavdeep Parhar if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list)) 23527951040fSNavdeep Parhar drain_wrq_wr_list(sc, wrq); 23537951040fSNavdeep Parhar 23547951040fSNavdeep Parhar #ifdef INVARIANTS 23557951040fSNavdeep Parhar if (TAILQ_EMPTY(&wrq->incomplete_wrs)) { 23567951040fSNavdeep Parhar /* Doorbell must have caught up to the pidx. */ 23577951040fSNavdeep Parhar MPASS(wrq->eq.pidx == wrq->eq.dbidx); 23587951040fSNavdeep Parhar } 23597951040fSNavdeep Parhar #endif 23607951040fSNavdeep Parhar EQ_UNLOCK(eq); 23617951040fSNavdeep Parhar } 23627951040fSNavdeep Parhar 23637951040fSNavdeep Parhar static u_int 23647951040fSNavdeep Parhar can_resume_eth_tx(struct mp_ring *r) 23657951040fSNavdeep Parhar { 23667951040fSNavdeep Parhar struct sge_eq *eq = r->cookie; 23677951040fSNavdeep Parhar 23687951040fSNavdeep Parhar return (total_available_tx_desc(eq) > eq->sidx / 8); 23697951040fSNavdeep Parhar } 23707951040fSNavdeep Parhar 23717951040fSNavdeep Parhar static inline int 23727951040fSNavdeep Parhar cannot_use_txpkts(struct mbuf *m) 23737951040fSNavdeep Parhar { 23747951040fSNavdeep Parhar /* maybe put a GL limit too, to avoid silliness? */ 23757951040fSNavdeep Parhar 23767951040fSNavdeep Parhar return (needs_tso(m)); 23777951040fSNavdeep Parhar } 23787951040fSNavdeep Parhar 23791404daa7SNavdeep Parhar static inline int 23801404daa7SNavdeep Parhar discard_tx(struct sge_eq *eq) 23811404daa7SNavdeep Parhar { 23821404daa7SNavdeep Parhar 23831404daa7SNavdeep Parhar return ((eq->flags & (EQ_ENABLED | EQ_QFLUSH)) != EQ_ENABLED); 23841404daa7SNavdeep Parhar } 23851404daa7SNavdeep Parhar 23867951040fSNavdeep Parhar /* 23877951040fSNavdeep Parhar * r->items[cidx] to r->items[pidx], with a wraparound at r->size, are ready to 23887951040fSNavdeep Parhar * be consumed. Return the actual number consumed. 0 indicates a stall. 23897951040fSNavdeep Parhar */ 23907951040fSNavdeep Parhar static u_int 23917951040fSNavdeep Parhar eth_tx(struct mp_ring *r, u_int cidx, u_int pidx) 23927951040fSNavdeep Parhar { 23937951040fSNavdeep Parhar struct sge_txq *txq = r->cookie; 23947951040fSNavdeep Parhar struct sge_eq *eq = &txq->eq; 23957951040fSNavdeep Parhar struct ifnet *ifp = txq->ifp; 2396fe2ebb76SJohn Baldwin struct vi_info *vi = ifp->if_softc; 2397fe2ebb76SJohn Baldwin struct port_info *pi = vi->pi; 23987951040fSNavdeep Parhar struct adapter *sc = pi->adapter; 23997951040fSNavdeep Parhar u_int total, remaining; /* # of packets */ 24007951040fSNavdeep Parhar u_int available, dbdiff; /* # of hardware descriptors */ 24017951040fSNavdeep Parhar u_int n, next_cidx; 24027951040fSNavdeep Parhar struct mbuf *m0, *tail; 24037951040fSNavdeep Parhar struct txpkts txp; 24047951040fSNavdeep Parhar struct fw_eth_tx_pkts_wr *wr; /* any fw WR struct will do */ 24057951040fSNavdeep Parhar 24067951040fSNavdeep Parhar remaining = IDXDIFF(pidx, cidx, r->size); 24077951040fSNavdeep Parhar MPASS(remaining > 0); /* Must not be called without work to do. */ 24087951040fSNavdeep Parhar total = 0; 24097951040fSNavdeep Parhar 24107951040fSNavdeep Parhar TXQ_LOCK(txq); 24111404daa7SNavdeep Parhar if (__predict_false(discard_tx(eq))) { 24127951040fSNavdeep Parhar while (cidx != pidx) { 24137951040fSNavdeep Parhar m0 = r->items[cidx]; 24147951040fSNavdeep Parhar m_freem(m0); 24157951040fSNavdeep Parhar if (++cidx == r->size) 24167951040fSNavdeep Parhar cidx = 0; 24177951040fSNavdeep Parhar } 24187951040fSNavdeep Parhar reclaim_tx_descs(txq, 2048); 24197951040fSNavdeep Parhar total = remaining; 24207951040fSNavdeep Parhar goto done; 24217951040fSNavdeep Parhar } 24227951040fSNavdeep Parhar 24237951040fSNavdeep Parhar /* How many hardware descriptors do we have readily available. */ 24247951040fSNavdeep Parhar if (eq->pidx == eq->cidx) 24257951040fSNavdeep Parhar available = eq->sidx - 1; 24267951040fSNavdeep Parhar else 24277951040fSNavdeep Parhar available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; 24287951040fSNavdeep Parhar dbdiff = IDXDIFF(eq->pidx, eq->dbidx, eq->sidx); 24297951040fSNavdeep Parhar 24307951040fSNavdeep Parhar while (remaining > 0) { 24317951040fSNavdeep Parhar 24327951040fSNavdeep Parhar m0 = r->items[cidx]; 24337951040fSNavdeep Parhar M_ASSERTPKTHDR(m0); 24347951040fSNavdeep Parhar MPASS(m0->m_nextpkt == NULL); 24357951040fSNavdeep Parhar 24367951040fSNavdeep Parhar if (available < SGE_MAX_WR_NDESC) { 24377951040fSNavdeep Parhar available += reclaim_tx_descs(txq, 64); 24387951040fSNavdeep Parhar if (available < howmany(mbuf_len16(m0), EQ_ESIZE / 16)) 24397951040fSNavdeep Parhar break; /* out of descriptors */ 24407951040fSNavdeep Parhar } 24417951040fSNavdeep Parhar 24427951040fSNavdeep Parhar next_cidx = cidx + 1; 24437951040fSNavdeep Parhar if (__predict_false(next_cidx == r->size)) 24447951040fSNavdeep Parhar next_cidx = 0; 24457951040fSNavdeep Parhar 24467951040fSNavdeep Parhar wr = (void *)&eq->desc[eq->pidx]; 24476af45170SJohn Baldwin if (sc->flags & IS_VF) { 24486af45170SJohn Baldwin total++; 24496af45170SJohn Baldwin remaining--; 24506af45170SJohn Baldwin ETHER_BPF_MTAP(ifp, m0); 2451472a6004SNavdeep Parhar n = write_txpkt_vm_wr(sc, txq, (void *)wr, m0, 2452472a6004SNavdeep Parhar available); 24536af45170SJohn Baldwin } else if (remaining > 1 && 24547951040fSNavdeep Parhar try_txpkts(m0, r->items[next_cidx], &txp, available) == 0) { 24557951040fSNavdeep Parhar 24567951040fSNavdeep Parhar /* pkts at cidx, next_cidx should both be in txp. */ 24577951040fSNavdeep Parhar MPASS(txp.npkt == 2); 24587951040fSNavdeep Parhar tail = r->items[next_cidx]; 24597951040fSNavdeep Parhar MPASS(tail->m_nextpkt == NULL); 24607951040fSNavdeep Parhar ETHER_BPF_MTAP(ifp, m0); 24617951040fSNavdeep Parhar ETHER_BPF_MTAP(ifp, tail); 24627951040fSNavdeep Parhar m0->m_nextpkt = tail; 24637951040fSNavdeep Parhar 24647951040fSNavdeep Parhar if (__predict_false(++next_cidx == r->size)) 24657951040fSNavdeep Parhar next_cidx = 0; 24667951040fSNavdeep Parhar 24677951040fSNavdeep Parhar while (next_cidx != pidx) { 24687951040fSNavdeep Parhar if (add_to_txpkts(r->items[next_cidx], &txp, 24697951040fSNavdeep Parhar available) != 0) 24707951040fSNavdeep Parhar break; 24717951040fSNavdeep Parhar tail->m_nextpkt = r->items[next_cidx]; 24727951040fSNavdeep Parhar tail = tail->m_nextpkt; 24737951040fSNavdeep Parhar ETHER_BPF_MTAP(ifp, tail); 24747951040fSNavdeep Parhar if (__predict_false(++next_cidx == r->size)) 24757951040fSNavdeep Parhar next_cidx = 0; 24767951040fSNavdeep Parhar } 24777951040fSNavdeep Parhar 24787951040fSNavdeep Parhar n = write_txpkts_wr(txq, wr, m0, &txp, available); 24797951040fSNavdeep Parhar total += txp.npkt; 24807951040fSNavdeep Parhar remaining -= txp.npkt; 24817951040fSNavdeep Parhar } else { 24827951040fSNavdeep Parhar total++; 24837951040fSNavdeep Parhar remaining--; 24847951040fSNavdeep Parhar ETHER_BPF_MTAP(ifp, m0); 248578552b23SNavdeep Parhar n = write_txpkt_wr(txq, (void *)wr, m0, available); 24867951040fSNavdeep Parhar } 24877951040fSNavdeep Parhar MPASS(n >= 1 && n <= available && n <= SGE_MAX_WR_NDESC); 24887951040fSNavdeep Parhar 24897951040fSNavdeep Parhar available -= n; 24907951040fSNavdeep Parhar dbdiff += n; 24917951040fSNavdeep Parhar IDXINCR(eq->pidx, n, eq->sidx); 24927951040fSNavdeep Parhar 24937951040fSNavdeep Parhar if (total_available_tx_desc(eq) < eq->sidx / 4 && 24947951040fSNavdeep Parhar atomic_cmpset_int(&eq->equiq, 0, 1)) { 24957951040fSNavdeep Parhar wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ | 24967951040fSNavdeep Parhar F_FW_WR_EQUEQ); 24977951040fSNavdeep Parhar eq->equeqidx = eq->pidx; 24987951040fSNavdeep Parhar } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 32) { 24997951040fSNavdeep Parhar wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ); 25007951040fSNavdeep Parhar eq->equeqidx = eq->pidx; 25017951040fSNavdeep Parhar } 25027951040fSNavdeep Parhar 25037951040fSNavdeep Parhar if (dbdiff >= 16 && remaining >= 4) { 25047951040fSNavdeep Parhar ring_eq_db(sc, eq, dbdiff); 25057951040fSNavdeep Parhar available += reclaim_tx_descs(txq, 4 * dbdiff); 25067951040fSNavdeep Parhar dbdiff = 0; 25077951040fSNavdeep Parhar } 25087951040fSNavdeep Parhar 25097951040fSNavdeep Parhar cidx = next_cidx; 25107951040fSNavdeep Parhar } 25117951040fSNavdeep Parhar if (dbdiff != 0) { 25127951040fSNavdeep Parhar ring_eq_db(sc, eq, dbdiff); 25137951040fSNavdeep Parhar reclaim_tx_descs(txq, 32); 25147951040fSNavdeep Parhar } 25157951040fSNavdeep Parhar done: 25167951040fSNavdeep Parhar TXQ_UNLOCK(txq); 25177951040fSNavdeep Parhar 25187951040fSNavdeep Parhar return (total); 2519733b9277SNavdeep Parhar } 2520733b9277SNavdeep Parhar 252154e4ee71SNavdeep Parhar static inline void 252254e4ee71SNavdeep Parhar init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int pktc_idx, 2523b2daa9a9SNavdeep Parhar int qsize) 252454e4ee71SNavdeep Parhar { 2525b2daa9a9SNavdeep Parhar 252654e4ee71SNavdeep Parhar KASSERT(tmr_idx >= 0 && tmr_idx < SGE_NTIMERS, 252754e4ee71SNavdeep Parhar ("%s: bad tmr_idx %d", __func__, tmr_idx)); 252854e4ee71SNavdeep Parhar KASSERT(pktc_idx < SGE_NCOUNTERS, /* -ve is ok, means don't use */ 252954e4ee71SNavdeep Parhar ("%s: bad pktc_idx %d", __func__, pktc_idx)); 253054e4ee71SNavdeep Parhar 253154e4ee71SNavdeep Parhar iq->flags = 0; 253254e4ee71SNavdeep Parhar iq->adapter = sc; 25337a32954cSNavdeep Parhar iq->intr_params = V_QINTR_TIMER_IDX(tmr_idx); 25347a32954cSNavdeep Parhar iq->intr_pktc_idx = SGE_NCOUNTERS - 1; 25357a32954cSNavdeep Parhar if (pktc_idx >= 0) { 25367a32954cSNavdeep Parhar iq->intr_params |= F_QINTR_CNT_EN; 253754e4ee71SNavdeep Parhar iq->intr_pktc_idx = pktc_idx; 25387a32954cSNavdeep Parhar } 2539d14b0ac1SNavdeep Parhar iq->qsize = roundup2(qsize, 16); /* See FW_IQ_CMD/iqsize */ 254090e7434aSNavdeep Parhar iq->sidx = iq->qsize - sc->params.sge.spg_len / IQ_ESIZE; 254154e4ee71SNavdeep Parhar } 254254e4ee71SNavdeep Parhar 254354e4ee71SNavdeep Parhar static inline void 2544e3207e19SNavdeep Parhar init_fl(struct adapter *sc, struct sge_fl *fl, int qsize, int maxp, char *name) 254554e4ee71SNavdeep Parhar { 25461458bff9SNavdeep Parhar 254754e4ee71SNavdeep Parhar fl->qsize = qsize; 254890e7434aSNavdeep Parhar fl->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE; 254954e4ee71SNavdeep Parhar strlcpy(fl->lockname, name, sizeof(fl->lockname)); 2550e3207e19SNavdeep Parhar if (sc->flags & BUF_PACKING_OK && 2551e3207e19SNavdeep Parhar ((!is_t4(sc) && buffer_packing) || /* T5+: enabled unless 0 */ 2552e3207e19SNavdeep Parhar (is_t4(sc) && buffer_packing == 1)))/* T4: disabled unless 1 */ 25531458bff9SNavdeep Parhar fl->flags |= FL_BUF_PACKING; 255438035ed6SNavdeep Parhar find_best_refill_source(sc, fl, maxp); 255538035ed6SNavdeep Parhar find_safe_refill_source(sc, fl); 255654e4ee71SNavdeep Parhar } 255754e4ee71SNavdeep Parhar 255854e4ee71SNavdeep Parhar static inline void 255990e7434aSNavdeep Parhar init_eq(struct adapter *sc, struct sge_eq *eq, int eqtype, int qsize, 256090e7434aSNavdeep Parhar uint8_t tx_chan, uint16_t iqid, char *name) 256154e4ee71SNavdeep Parhar { 2562733b9277SNavdeep Parhar KASSERT(eqtype <= EQ_TYPEMASK, ("%s: bad qtype %d", __func__, eqtype)); 2563733b9277SNavdeep Parhar 2564733b9277SNavdeep Parhar eq->flags = eqtype & EQ_TYPEMASK; 2565733b9277SNavdeep Parhar eq->tx_chan = tx_chan; 2566733b9277SNavdeep Parhar eq->iqid = iqid; 256790e7434aSNavdeep Parhar eq->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE; 2568f7dfe243SNavdeep Parhar strlcpy(eq->lockname, name, sizeof(eq->lockname)); 256954e4ee71SNavdeep Parhar } 257054e4ee71SNavdeep Parhar 257154e4ee71SNavdeep Parhar static int 257254e4ee71SNavdeep Parhar alloc_ring(struct adapter *sc, size_t len, bus_dma_tag_t *tag, 257354e4ee71SNavdeep Parhar bus_dmamap_t *map, bus_addr_t *pa, void **va) 257454e4ee71SNavdeep Parhar { 257554e4ee71SNavdeep Parhar int rc; 257654e4ee71SNavdeep Parhar 257754e4ee71SNavdeep Parhar rc = bus_dma_tag_create(sc->dmat, 512, 0, BUS_SPACE_MAXADDR, 257854e4ee71SNavdeep Parhar BUS_SPACE_MAXADDR, NULL, NULL, len, 1, len, 0, NULL, NULL, tag); 257954e4ee71SNavdeep Parhar if (rc != 0) { 258054e4ee71SNavdeep Parhar device_printf(sc->dev, "cannot allocate DMA tag: %d\n", rc); 258154e4ee71SNavdeep Parhar goto done; 258254e4ee71SNavdeep Parhar } 258354e4ee71SNavdeep Parhar 258454e4ee71SNavdeep Parhar rc = bus_dmamem_alloc(*tag, va, 258554e4ee71SNavdeep Parhar BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, map); 258654e4ee71SNavdeep Parhar if (rc != 0) { 258754e4ee71SNavdeep Parhar device_printf(sc->dev, "cannot allocate DMA memory: %d\n", rc); 258854e4ee71SNavdeep Parhar goto done; 258954e4ee71SNavdeep Parhar } 259054e4ee71SNavdeep Parhar 259154e4ee71SNavdeep Parhar rc = bus_dmamap_load(*tag, *map, *va, len, oneseg_dma_callback, pa, 0); 259254e4ee71SNavdeep Parhar if (rc != 0) { 259354e4ee71SNavdeep Parhar device_printf(sc->dev, "cannot load DMA map: %d\n", rc); 259454e4ee71SNavdeep Parhar goto done; 259554e4ee71SNavdeep Parhar } 259654e4ee71SNavdeep Parhar done: 259754e4ee71SNavdeep Parhar if (rc) 259854e4ee71SNavdeep Parhar free_ring(sc, *tag, *map, *pa, *va); 259954e4ee71SNavdeep Parhar 260054e4ee71SNavdeep Parhar return (rc); 260154e4ee71SNavdeep Parhar } 260254e4ee71SNavdeep Parhar 260354e4ee71SNavdeep Parhar static int 260454e4ee71SNavdeep Parhar free_ring(struct adapter *sc, bus_dma_tag_t tag, bus_dmamap_t map, 260554e4ee71SNavdeep Parhar bus_addr_t pa, void *va) 260654e4ee71SNavdeep Parhar { 260754e4ee71SNavdeep Parhar if (pa) 260854e4ee71SNavdeep Parhar bus_dmamap_unload(tag, map); 260954e4ee71SNavdeep Parhar if (va) 261054e4ee71SNavdeep Parhar bus_dmamem_free(tag, va, map); 261154e4ee71SNavdeep Parhar if (tag) 261254e4ee71SNavdeep Parhar bus_dma_tag_destroy(tag); 261354e4ee71SNavdeep Parhar 261454e4ee71SNavdeep Parhar return (0); 261554e4ee71SNavdeep Parhar } 261654e4ee71SNavdeep Parhar 261754e4ee71SNavdeep Parhar /* 261854e4ee71SNavdeep Parhar * Allocates the ring for an ingress queue and an optional freelist. If the 261954e4ee71SNavdeep Parhar * freelist is specified it will be allocated and then associated with the 262054e4ee71SNavdeep Parhar * ingress queue. 262154e4ee71SNavdeep Parhar * 262254e4ee71SNavdeep Parhar * Returns errno on failure. Resources allocated up to that point may still be 262354e4ee71SNavdeep Parhar * allocated. Caller is responsible for cleanup in case this function fails. 262454e4ee71SNavdeep Parhar * 2625f549e352SNavdeep Parhar * If the ingress queue will take interrupts directly then the intr_idx 2626f549e352SNavdeep Parhar * specifies the vector, starting from 0. -1 means the interrupts for this 2627f549e352SNavdeep Parhar * queue should be forwarded to the fwq. 262854e4ee71SNavdeep Parhar */ 262954e4ee71SNavdeep Parhar static int 2630fe2ebb76SJohn Baldwin alloc_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl, 2631bc14b14dSNavdeep Parhar int intr_idx, int cong) 263254e4ee71SNavdeep Parhar { 263354e4ee71SNavdeep Parhar int rc, i, cntxt_id; 263454e4ee71SNavdeep Parhar size_t len; 263554e4ee71SNavdeep Parhar struct fw_iq_cmd c; 2636fe2ebb76SJohn Baldwin struct port_info *pi = vi->pi; 263754e4ee71SNavdeep Parhar struct adapter *sc = iq->adapter; 263890e7434aSNavdeep Parhar struct sge_params *sp = &sc->params.sge; 263954e4ee71SNavdeep Parhar __be32 v = 0; 264054e4ee71SNavdeep Parhar 2641b2daa9a9SNavdeep Parhar len = iq->qsize * IQ_ESIZE; 264254e4ee71SNavdeep Parhar rc = alloc_ring(sc, len, &iq->desc_tag, &iq->desc_map, &iq->ba, 264354e4ee71SNavdeep Parhar (void **)&iq->desc); 264454e4ee71SNavdeep Parhar if (rc != 0) 264554e4ee71SNavdeep Parhar return (rc); 264654e4ee71SNavdeep Parhar 264754e4ee71SNavdeep Parhar bzero(&c, sizeof(c)); 264854e4ee71SNavdeep Parhar c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 264954e4ee71SNavdeep Parhar F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) | 265054e4ee71SNavdeep Parhar V_FW_IQ_CMD_VFN(0)); 265154e4ee71SNavdeep Parhar 265254e4ee71SNavdeep Parhar c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART | 265354e4ee71SNavdeep Parhar FW_LEN16(c)); 265454e4ee71SNavdeep Parhar 265554e4ee71SNavdeep Parhar /* Special handling for firmware event queue */ 265654e4ee71SNavdeep Parhar if (iq == &sc->sge.fwq) 265754e4ee71SNavdeep Parhar v |= F_FW_IQ_CMD_IQASYNCH; 265854e4ee71SNavdeep Parhar 2659f549e352SNavdeep Parhar if (intr_idx < 0) { 2660f549e352SNavdeep Parhar /* Forwarded interrupts, all headed to fwq */ 2661f549e352SNavdeep Parhar v |= F_FW_IQ_CMD_IQANDST; 2662f549e352SNavdeep Parhar v |= V_FW_IQ_CMD_IQANDSTINDEX(sc->sge.fwq.cntxt_id); 2663f549e352SNavdeep Parhar } else { 266454e4ee71SNavdeep Parhar KASSERT(intr_idx < sc->intr_count, 266554e4ee71SNavdeep Parhar ("%s: invalid direct intr_idx %d", __func__, intr_idx)); 266654e4ee71SNavdeep Parhar v |= V_FW_IQ_CMD_IQANDSTINDEX(intr_idx); 2667f549e352SNavdeep Parhar } 266854e4ee71SNavdeep Parhar 266954e4ee71SNavdeep Parhar c.type_to_iqandstindex = htobe32(v | 267054e4ee71SNavdeep Parhar V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) | 2671fe2ebb76SJohn Baldwin V_FW_IQ_CMD_VIID(vi->viid) | 267254e4ee71SNavdeep Parhar V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT)); 267354e4ee71SNavdeep Parhar c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->tx_chan) | 267454e4ee71SNavdeep Parhar F_FW_IQ_CMD_IQGTSMODE | 267554e4ee71SNavdeep Parhar V_FW_IQ_CMD_IQINTCNTTHRESH(iq->intr_pktc_idx) | 2676b2daa9a9SNavdeep Parhar V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4)); 267754e4ee71SNavdeep Parhar c.iqsize = htobe16(iq->qsize); 267854e4ee71SNavdeep Parhar c.iqaddr = htobe64(iq->ba); 2679bc14b14dSNavdeep Parhar if (cong >= 0) 2680bc14b14dSNavdeep Parhar c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN); 268154e4ee71SNavdeep Parhar 268254e4ee71SNavdeep Parhar if (fl) { 268354e4ee71SNavdeep Parhar mtx_init(&fl->fl_lock, fl->lockname, NULL, MTX_DEF); 268454e4ee71SNavdeep Parhar 2685b2daa9a9SNavdeep Parhar len = fl->qsize * EQ_ESIZE; 268654e4ee71SNavdeep Parhar rc = alloc_ring(sc, len, &fl->desc_tag, &fl->desc_map, 268754e4ee71SNavdeep Parhar &fl->ba, (void **)&fl->desc); 268854e4ee71SNavdeep Parhar if (rc) 268954e4ee71SNavdeep Parhar return (rc); 269054e4ee71SNavdeep Parhar 269154e4ee71SNavdeep Parhar /* Allocate space for one software descriptor per buffer. */ 269254e4ee71SNavdeep Parhar rc = alloc_fl_sdesc(fl); 269354e4ee71SNavdeep Parhar if (rc != 0) { 269454e4ee71SNavdeep Parhar device_printf(sc->dev, 269554e4ee71SNavdeep Parhar "failed to setup fl software descriptors: %d\n", 269654e4ee71SNavdeep Parhar rc); 269754e4ee71SNavdeep Parhar return (rc); 269854e4ee71SNavdeep Parhar } 26994d6db4e0SNavdeep Parhar 27004d6db4e0SNavdeep Parhar if (fl->flags & FL_BUF_PACKING) { 270190e7434aSNavdeep Parhar fl->lowat = roundup2(sp->fl_starve_threshold2, 8); 270290e7434aSNavdeep Parhar fl->buf_boundary = sp->pack_boundary; 27034d6db4e0SNavdeep Parhar } else { 270490e7434aSNavdeep Parhar fl->lowat = roundup2(sp->fl_starve_threshold, 8); 2705e3207e19SNavdeep Parhar fl->buf_boundary = 16; 27064d6db4e0SNavdeep Parhar } 270790e7434aSNavdeep Parhar if (fl_pad && fl->buf_boundary < sp->pad_boundary) 270890e7434aSNavdeep Parhar fl->buf_boundary = sp->pad_boundary; 270954e4ee71SNavdeep Parhar 2710214c3582SNavdeep Parhar c.iqns_to_fl0congen |= 2711bc14b14dSNavdeep Parhar htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) | 2712bc14b14dSNavdeep Parhar F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO | 27131458bff9SNavdeep Parhar (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) | 27141458bff9SNavdeep Parhar (fl->flags & FL_BUF_PACKING ? F_FW_IQ_CMD_FL0PACKEN : 27151458bff9SNavdeep Parhar 0)); 2716bc14b14dSNavdeep Parhar if (cong >= 0) { 2717bc14b14dSNavdeep Parhar c.iqns_to_fl0congen |= 2718bc14b14dSNavdeep Parhar htobe32(V_FW_IQ_CMD_FL0CNGCHMAP(cong) | 2719bc14b14dSNavdeep Parhar F_FW_IQ_CMD_FL0CONGCIF | 2720bc14b14dSNavdeep Parhar F_FW_IQ_CMD_FL0CONGEN); 2721bc14b14dSNavdeep Parhar } 272254e4ee71SNavdeep Parhar c.fl0dcaen_to_fl0cidxfthresh = 2723ed7e5640SNavdeep Parhar htobe16(V_FW_IQ_CMD_FL0FBMIN(chip_id(sc) <= CHELSIO_T5 ? 2724ed7e5640SNavdeep Parhar X_FETCHBURSTMIN_128B : X_FETCHBURSTMIN_64B) | 2725ed7e5640SNavdeep Parhar V_FW_IQ_CMD_FL0FBMAX(chip_id(sc) <= CHELSIO_T5 ? 2726ed7e5640SNavdeep Parhar X_FETCHBURSTMAX_512B : X_FETCHBURSTMAX_256B)); 272754e4ee71SNavdeep Parhar c.fl0size = htobe16(fl->qsize); 272854e4ee71SNavdeep Parhar c.fl0addr = htobe64(fl->ba); 272954e4ee71SNavdeep Parhar } 273054e4ee71SNavdeep Parhar 273154e4ee71SNavdeep Parhar rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 273254e4ee71SNavdeep Parhar if (rc != 0) { 273354e4ee71SNavdeep Parhar device_printf(sc->dev, 273454e4ee71SNavdeep Parhar "failed to create ingress queue: %d\n", rc); 273554e4ee71SNavdeep Parhar return (rc); 273654e4ee71SNavdeep Parhar } 273754e4ee71SNavdeep Parhar 273854e4ee71SNavdeep Parhar iq->cidx = 0; 2739b2daa9a9SNavdeep Parhar iq->gen = F_RSPD_GEN; 274054e4ee71SNavdeep Parhar iq->intr_next = iq->intr_params; 274154e4ee71SNavdeep Parhar iq->cntxt_id = be16toh(c.iqid); 274254e4ee71SNavdeep Parhar iq->abs_id = be16toh(c.physiqid); 2743733b9277SNavdeep Parhar iq->flags |= IQ_ALLOCATED; 274454e4ee71SNavdeep Parhar 274554e4ee71SNavdeep Parhar cntxt_id = iq->cntxt_id - sc->sge.iq_start; 2746733b9277SNavdeep Parhar if (cntxt_id >= sc->sge.niq) { 2747733b9277SNavdeep Parhar panic ("%s: iq->cntxt_id (%d) more than the max (%d)", __func__, 2748733b9277SNavdeep Parhar cntxt_id, sc->sge.niq - 1); 2749733b9277SNavdeep Parhar } 275054e4ee71SNavdeep Parhar sc->sge.iqmap[cntxt_id] = iq; 275154e4ee71SNavdeep Parhar 275254e4ee71SNavdeep Parhar if (fl) { 27534d6db4e0SNavdeep Parhar u_int qid; 27544d6db4e0SNavdeep Parhar 27554d6db4e0SNavdeep Parhar iq->flags |= IQ_HAS_FL; 275654e4ee71SNavdeep Parhar fl->cntxt_id = be16toh(c.fl0id); 275754e4ee71SNavdeep Parhar fl->pidx = fl->cidx = 0; 275854e4ee71SNavdeep Parhar 27599f1f7ec9SNavdeep Parhar cntxt_id = fl->cntxt_id - sc->sge.eq_start; 2760733b9277SNavdeep Parhar if (cntxt_id >= sc->sge.neq) { 2761733b9277SNavdeep Parhar panic("%s: fl->cntxt_id (%d) more than the max (%d)", 2762733b9277SNavdeep Parhar __func__, cntxt_id, sc->sge.neq - 1); 2763733b9277SNavdeep Parhar } 276454e4ee71SNavdeep Parhar sc->sge.eqmap[cntxt_id] = (void *)fl; 276554e4ee71SNavdeep Parhar 27664d6db4e0SNavdeep Parhar qid = fl->cntxt_id; 27674d6db4e0SNavdeep Parhar if (isset(&sc->doorbells, DOORBELL_UDB)) { 276890e7434aSNavdeep Parhar uint32_t s_qpp = sc->params.sge.eq_s_qpp; 27694d6db4e0SNavdeep Parhar uint32_t mask = (1 << s_qpp) - 1; 27704d6db4e0SNavdeep Parhar volatile uint8_t *udb; 27714d6db4e0SNavdeep Parhar 27724d6db4e0SNavdeep Parhar udb = sc->udbs_base + UDBS_DB_OFFSET; 27734d6db4e0SNavdeep Parhar udb += (qid >> s_qpp) << PAGE_SHIFT; 27744d6db4e0SNavdeep Parhar qid &= mask; 27754d6db4e0SNavdeep Parhar if (qid < PAGE_SIZE / UDBS_SEG_SIZE) { 27764d6db4e0SNavdeep Parhar udb += qid << UDBS_SEG_SHIFT; 27774d6db4e0SNavdeep Parhar qid = 0; 27784d6db4e0SNavdeep Parhar } 27794d6db4e0SNavdeep Parhar fl->udb = (volatile void *)udb; 27804d6db4e0SNavdeep Parhar } 2781d1205d09SNavdeep Parhar fl->dbval = V_QID(qid) | sc->chip_params->sge_fl_db; 27824d6db4e0SNavdeep Parhar 278354e4ee71SNavdeep Parhar FL_LOCK(fl); 2784733b9277SNavdeep Parhar /* Enough to make sure the SGE doesn't think it's starved */ 2785733b9277SNavdeep Parhar refill_fl(sc, fl, fl->lowat); 278654e4ee71SNavdeep Parhar FL_UNLOCK(fl); 278754e4ee71SNavdeep Parhar } 278854e4ee71SNavdeep Parhar 27898c0ca00bSNavdeep Parhar if (chip_id(sc) >= CHELSIO_T5 && !(sc->flags & IS_VF) && cong >= 0) { 2790ba41ec48SNavdeep Parhar uint32_t param, val; 2791ba41ec48SNavdeep Parhar 2792ba41ec48SNavdeep Parhar param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 2793ba41ec48SNavdeep Parhar V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) | 2794ba41ec48SNavdeep Parhar V_FW_PARAMS_PARAM_YZ(iq->cntxt_id); 279573cd9220SNavdeep Parhar if (cong == 0) 279673cd9220SNavdeep Parhar val = 1 << 19; 279773cd9220SNavdeep Parhar else { 279873cd9220SNavdeep Parhar val = 2 << 19; 279973cd9220SNavdeep Parhar for (i = 0; i < 4; i++) { 280073cd9220SNavdeep Parhar if (cong & (1 << i)) 280173cd9220SNavdeep Parhar val |= 1 << (i << 2); 280273cd9220SNavdeep Parhar } 280373cd9220SNavdeep Parhar } 280473cd9220SNavdeep Parhar 2805ba41ec48SNavdeep Parhar rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 2806ba41ec48SNavdeep Parhar if (rc != 0) { 2807ba41ec48SNavdeep Parhar /* report error but carry on */ 2808ba41ec48SNavdeep Parhar device_printf(sc->dev, 2809ba41ec48SNavdeep Parhar "failed to set congestion manager context for " 2810ba41ec48SNavdeep Parhar "ingress queue %d: %d\n", iq->cntxt_id, rc); 2811ba41ec48SNavdeep Parhar } 2812ba41ec48SNavdeep Parhar } 2813ba41ec48SNavdeep Parhar 281454e4ee71SNavdeep Parhar /* Enable IQ interrupts */ 2815733b9277SNavdeep Parhar atomic_store_rel_int(&iq->state, IQS_IDLE); 2816315048f2SJohn Baldwin t4_write_reg(sc, sc->sge_gts_reg, V_SEINTARM(iq->intr_params) | 281754e4ee71SNavdeep Parhar V_INGRESSQID(iq->cntxt_id)); 281854e4ee71SNavdeep Parhar 281954e4ee71SNavdeep Parhar return (0); 282054e4ee71SNavdeep Parhar } 282154e4ee71SNavdeep Parhar 282254e4ee71SNavdeep Parhar static int 2823fe2ebb76SJohn Baldwin free_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl) 282454e4ee71SNavdeep Parhar { 282538035ed6SNavdeep Parhar int rc; 282654e4ee71SNavdeep Parhar struct adapter *sc = iq->adapter; 282754e4ee71SNavdeep Parhar device_t dev; 282854e4ee71SNavdeep Parhar 282954e4ee71SNavdeep Parhar if (sc == NULL) 283054e4ee71SNavdeep Parhar return (0); /* nothing to do */ 283154e4ee71SNavdeep Parhar 2832fe2ebb76SJohn Baldwin dev = vi ? vi->dev : sc->dev; 283354e4ee71SNavdeep Parhar 283454e4ee71SNavdeep Parhar if (iq->flags & IQ_ALLOCATED) { 283554e4ee71SNavdeep Parhar rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0, 283654e4ee71SNavdeep Parhar FW_IQ_TYPE_FL_INT_CAP, iq->cntxt_id, 283754e4ee71SNavdeep Parhar fl ? fl->cntxt_id : 0xffff, 0xffff); 283854e4ee71SNavdeep Parhar if (rc != 0) { 283954e4ee71SNavdeep Parhar device_printf(dev, 284054e4ee71SNavdeep Parhar "failed to free queue %p: %d\n", iq, rc); 284154e4ee71SNavdeep Parhar return (rc); 284254e4ee71SNavdeep Parhar } 284354e4ee71SNavdeep Parhar iq->flags &= ~IQ_ALLOCATED; 284454e4ee71SNavdeep Parhar } 284554e4ee71SNavdeep Parhar 284654e4ee71SNavdeep Parhar free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, iq->desc); 284754e4ee71SNavdeep Parhar 284854e4ee71SNavdeep Parhar bzero(iq, sizeof(*iq)); 284954e4ee71SNavdeep Parhar 285054e4ee71SNavdeep Parhar if (fl) { 285154e4ee71SNavdeep Parhar free_ring(sc, fl->desc_tag, fl->desc_map, fl->ba, 285254e4ee71SNavdeep Parhar fl->desc); 285354e4ee71SNavdeep Parhar 2854aa9a5cc0SNavdeep Parhar if (fl->sdesc) 28551458bff9SNavdeep Parhar free_fl_sdesc(sc, fl); 28561458bff9SNavdeep Parhar 285754e4ee71SNavdeep Parhar if (mtx_initialized(&fl->fl_lock)) 285854e4ee71SNavdeep Parhar mtx_destroy(&fl->fl_lock); 285954e4ee71SNavdeep Parhar 286054e4ee71SNavdeep Parhar bzero(fl, sizeof(*fl)); 286154e4ee71SNavdeep Parhar } 286254e4ee71SNavdeep Parhar 286354e4ee71SNavdeep Parhar return (0); 286454e4ee71SNavdeep Parhar } 286554e4ee71SNavdeep Parhar 286638035ed6SNavdeep Parhar static void 2867348694daSNavdeep Parhar add_iq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid, 2868348694daSNavdeep Parhar struct sge_iq *iq) 2869348694daSNavdeep Parhar { 2870348694daSNavdeep Parhar struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 2871348694daSNavdeep Parhar 2872348694daSNavdeep Parhar SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, &iq->ba, 2873348694daSNavdeep Parhar "bus address of descriptor ring"); 2874348694daSNavdeep Parhar SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 2875348694daSNavdeep Parhar iq->qsize * IQ_ESIZE, "descriptor ring size in bytes"); 2876348694daSNavdeep Parhar SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "abs_id", 2877348694daSNavdeep Parhar CTLTYPE_INT | CTLFLAG_RD, &iq->abs_id, 0, sysctl_uint16, "I", 2878348694daSNavdeep Parhar "absolute id of the queue"); 2879348694daSNavdeep Parhar SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 2880348694daSNavdeep Parhar CTLTYPE_INT | CTLFLAG_RD, &iq->cntxt_id, 0, sysctl_uint16, "I", 2881348694daSNavdeep Parhar "SGE context id of the queue"); 2882348694daSNavdeep Parhar SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx", 2883348694daSNavdeep Parhar CTLTYPE_INT | CTLFLAG_RD, &iq->cidx, 0, sysctl_uint16, "I", 2884348694daSNavdeep Parhar "consumer index"); 2885348694daSNavdeep Parhar } 2886348694daSNavdeep Parhar 2887348694daSNavdeep Parhar static void 2888aa93b99aSNavdeep Parhar add_fl_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx, 2889aa93b99aSNavdeep Parhar struct sysctl_oid *oid, struct sge_fl *fl) 289038035ed6SNavdeep Parhar { 289138035ed6SNavdeep Parhar struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 289238035ed6SNavdeep Parhar 289338035ed6SNavdeep Parhar oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL, 289438035ed6SNavdeep Parhar "freelist"); 289538035ed6SNavdeep Parhar children = SYSCTL_CHILDREN(oid); 289638035ed6SNavdeep Parhar 2897aa93b99aSNavdeep Parhar SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, 2898aa93b99aSNavdeep Parhar &fl->ba, "bus address of descriptor ring"); 2899aa93b99aSNavdeep Parhar SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 2900aa93b99aSNavdeep Parhar fl->sidx * EQ_ESIZE + sc->params.sge.spg_len, 2901aa93b99aSNavdeep Parhar "desc ring size in bytes"); 290238035ed6SNavdeep Parhar SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 290338035ed6SNavdeep Parhar CTLTYPE_INT | CTLFLAG_RD, &fl->cntxt_id, 0, sysctl_uint16, "I", 290438035ed6SNavdeep Parhar "SGE context id of the freelist"); 2905e3207e19SNavdeep Parhar SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "padding", CTLFLAG_RD, NULL, 2906e3207e19SNavdeep Parhar fl_pad ? 1 : 0, "padding enabled"); 2907e3207e19SNavdeep Parhar SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "packing", CTLFLAG_RD, NULL, 2908e3207e19SNavdeep Parhar fl->flags & FL_BUF_PACKING ? 1 : 0, "packing enabled"); 290938035ed6SNavdeep Parhar SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &fl->cidx, 291038035ed6SNavdeep Parhar 0, "consumer index"); 291138035ed6SNavdeep Parhar if (fl->flags & FL_BUF_PACKING) { 291238035ed6SNavdeep Parhar SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rx_offset", 291338035ed6SNavdeep Parhar CTLFLAG_RD, &fl->rx_offset, 0, "packing rx offset"); 291438035ed6SNavdeep Parhar } 291538035ed6SNavdeep Parhar SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &fl->pidx, 291638035ed6SNavdeep Parhar 0, "producer index"); 291738035ed6SNavdeep Parhar SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_allocated", 291838035ed6SNavdeep Parhar CTLFLAG_RD, &fl->mbuf_allocated, "# of mbuf allocated"); 291938035ed6SNavdeep Parhar SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_inlined", 292038035ed6SNavdeep Parhar CTLFLAG_RD, &fl->mbuf_inlined, "# of mbuf inlined in clusters"); 292138035ed6SNavdeep Parhar SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_allocated", 292238035ed6SNavdeep Parhar CTLFLAG_RD, &fl->cl_allocated, "# of clusters allocated"); 292338035ed6SNavdeep Parhar SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_recycled", 292438035ed6SNavdeep Parhar CTLFLAG_RD, &fl->cl_recycled, "# of clusters recycled"); 292538035ed6SNavdeep Parhar SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_fast_recycled", 292638035ed6SNavdeep Parhar CTLFLAG_RD, &fl->cl_fast_recycled, "# of clusters recycled (fast)"); 292738035ed6SNavdeep Parhar } 292838035ed6SNavdeep Parhar 292954e4ee71SNavdeep Parhar static int 2930733b9277SNavdeep Parhar alloc_fwq(struct adapter *sc) 293154e4ee71SNavdeep Parhar { 2932733b9277SNavdeep Parhar int rc, intr_idx; 293356599263SNavdeep Parhar struct sge_iq *fwq = &sc->sge.fwq; 2934733b9277SNavdeep Parhar struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev); 2935733b9277SNavdeep Parhar struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 293656599263SNavdeep Parhar 2937b2daa9a9SNavdeep Parhar init_iq(fwq, sc, 0, 0, FW_IQ_QSIZE); 29386af45170SJohn Baldwin if (sc->flags & IS_VF) 29396af45170SJohn Baldwin intr_idx = 0; 29404535e804SNavdeep Parhar else 2941733b9277SNavdeep Parhar intr_idx = sc->intr_count > 1 ? 1 : 0; 2942fe2ebb76SJohn Baldwin rc = alloc_iq_fl(&sc->port[0]->vi[0], fwq, NULL, intr_idx, -1); 2943733b9277SNavdeep Parhar if (rc != 0) { 2944733b9277SNavdeep Parhar device_printf(sc->dev, 2945733b9277SNavdeep Parhar "failed to create firmware event queue: %d\n", rc); 294656599263SNavdeep Parhar return (rc); 2947733b9277SNavdeep Parhar } 294856599263SNavdeep Parhar 2949733b9277SNavdeep Parhar oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "fwq", CTLFLAG_RD, 2950733b9277SNavdeep Parhar NULL, "firmware event queue"); 2951348694daSNavdeep Parhar add_iq_sysctls(&sc->ctx, oid, fwq); 295256599263SNavdeep Parhar 2953733b9277SNavdeep Parhar return (0); 2954733b9277SNavdeep Parhar } 2955733b9277SNavdeep Parhar 2956733b9277SNavdeep Parhar static int 2957733b9277SNavdeep Parhar free_fwq(struct adapter *sc) 2958733b9277SNavdeep Parhar { 2959733b9277SNavdeep Parhar return free_iq_fl(NULL, &sc->sge.fwq, NULL); 2960733b9277SNavdeep Parhar } 2961733b9277SNavdeep Parhar 2962733b9277SNavdeep Parhar static int 2963733b9277SNavdeep Parhar alloc_mgmtq(struct adapter *sc) 2964733b9277SNavdeep Parhar { 2965733b9277SNavdeep Parhar int rc; 2966733b9277SNavdeep Parhar struct sge_wrq *mgmtq = &sc->sge.mgmtq; 2967733b9277SNavdeep Parhar char name[16]; 2968733b9277SNavdeep Parhar struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev); 2969733b9277SNavdeep Parhar struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 2970733b9277SNavdeep Parhar 2971733b9277SNavdeep Parhar oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "mgmtq", CTLFLAG_RD, 2972733b9277SNavdeep Parhar NULL, "management queue"); 2973733b9277SNavdeep Parhar 2974733b9277SNavdeep Parhar snprintf(name, sizeof(name), "%s mgmtq", device_get_nameunit(sc->dev)); 297590e7434aSNavdeep Parhar init_eq(sc, &mgmtq->eq, EQ_CTRL, CTRL_EQ_QSIZE, sc->port[0]->tx_chan, 2976733b9277SNavdeep Parhar sc->sge.fwq.cntxt_id, name); 2977733b9277SNavdeep Parhar rc = alloc_wrq(sc, NULL, mgmtq, oid); 2978733b9277SNavdeep Parhar if (rc != 0) { 2979733b9277SNavdeep Parhar device_printf(sc->dev, 2980733b9277SNavdeep Parhar "failed to create management queue: %d\n", rc); 298156599263SNavdeep Parhar return (rc); 298256599263SNavdeep Parhar } 298356599263SNavdeep Parhar 2984733b9277SNavdeep Parhar return (0); 298554e4ee71SNavdeep Parhar } 298654e4ee71SNavdeep Parhar 298754e4ee71SNavdeep Parhar static int 2988733b9277SNavdeep Parhar free_mgmtq(struct adapter *sc) 2989733b9277SNavdeep Parhar { 299009fe6320SNavdeep Parhar 2991733b9277SNavdeep Parhar return free_wrq(sc, &sc->sge.mgmtq); 2992733b9277SNavdeep Parhar } 2993733b9277SNavdeep Parhar 29941605bac6SNavdeep Parhar int 29959af71ab3SNavdeep Parhar tnl_cong(struct port_info *pi, int drop) 29969fb8886bSNavdeep Parhar { 29979fb8886bSNavdeep Parhar 29989af71ab3SNavdeep Parhar if (drop == -1) 29999fb8886bSNavdeep Parhar return (-1); 30009af71ab3SNavdeep Parhar else if (drop == 1) 30019fb8886bSNavdeep Parhar return (0); 30029fb8886bSNavdeep Parhar else 30035bcae8ddSNavdeep Parhar return (pi->rx_e_chan_map); 30049fb8886bSNavdeep Parhar } 30059fb8886bSNavdeep Parhar 3006733b9277SNavdeep Parhar static int 3007fe2ebb76SJohn Baldwin alloc_rxq(struct vi_info *vi, struct sge_rxq *rxq, int intr_idx, int idx, 3008733b9277SNavdeep Parhar struct sysctl_oid *oid) 300954e4ee71SNavdeep Parhar { 301054e4ee71SNavdeep Parhar int rc; 3011ec55567cSJohn Baldwin struct adapter *sc = vi->pi->adapter; 301254e4ee71SNavdeep Parhar struct sysctl_oid_list *children; 301354e4ee71SNavdeep Parhar char name[16]; 301454e4ee71SNavdeep Parhar 3015fe2ebb76SJohn Baldwin rc = alloc_iq_fl(vi, &rxq->iq, &rxq->fl, intr_idx, 3016fe2ebb76SJohn Baldwin tnl_cong(vi->pi, cong_drop)); 301754e4ee71SNavdeep Parhar if (rc != 0) 301854e4ee71SNavdeep Parhar return (rc); 301954e4ee71SNavdeep Parhar 3020ec55567cSJohn Baldwin if (idx == 0) 3021ec55567cSJohn Baldwin sc->sge.iq_base = rxq->iq.abs_id - rxq->iq.cntxt_id; 3022ec55567cSJohn Baldwin else 3023ec55567cSJohn Baldwin KASSERT(rxq->iq.cntxt_id + sc->sge.iq_base == rxq->iq.abs_id, 3024ec55567cSJohn Baldwin ("iq_base mismatch")); 3025ec55567cSJohn Baldwin KASSERT(sc->sge.iq_base == 0 || sc->flags & IS_VF, 3026ec55567cSJohn Baldwin ("PF with non-zero iq_base")); 3027ec55567cSJohn Baldwin 30284d6db4e0SNavdeep Parhar /* 30294d6db4e0SNavdeep Parhar * The freelist is just barely above the starvation threshold right now, 30304d6db4e0SNavdeep Parhar * fill it up a bit more. 30314d6db4e0SNavdeep Parhar */ 30329b4d7b4eSNavdeep Parhar FL_LOCK(&rxq->fl); 3033ec55567cSJohn Baldwin refill_fl(sc, &rxq->fl, 128); 30349b4d7b4eSNavdeep Parhar FL_UNLOCK(&rxq->fl); 30359b4d7b4eSNavdeep Parhar 3036a1ea9a82SNavdeep Parhar #if defined(INET) || defined(INET6) 303746f48ee5SNavdeep Parhar rc = tcp_lro_init_args(&rxq->lro, vi->ifp, lro_entries, lro_mbufs); 303854e4ee71SNavdeep Parhar if (rc != 0) 303954e4ee71SNavdeep Parhar return (rc); 304046f48ee5SNavdeep Parhar MPASS(rxq->lro.ifp == vi->ifp); /* also indicates LRO init'ed */ 304154e4ee71SNavdeep Parhar 3042fe2ebb76SJohn Baldwin if (vi->ifp->if_capenable & IFCAP_LRO) 3043733b9277SNavdeep Parhar rxq->iq.flags |= IQ_LRO_ENABLED; 304454e4ee71SNavdeep Parhar #endif 3045fe2ebb76SJohn Baldwin rxq->ifp = vi->ifp; 304654e4ee71SNavdeep Parhar 3047733b9277SNavdeep Parhar children = SYSCTL_CHILDREN(oid); 304854e4ee71SNavdeep Parhar 304954e4ee71SNavdeep Parhar snprintf(name, sizeof(name), "%d", idx); 3050fe2ebb76SJohn Baldwin oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 305154e4ee71SNavdeep Parhar NULL, "rx queue"); 305254e4ee71SNavdeep Parhar children = SYSCTL_CHILDREN(oid); 305354e4ee71SNavdeep Parhar 3054348694daSNavdeep Parhar add_iq_sysctls(&vi->ctx, oid, &rxq->iq); 3055a1ea9a82SNavdeep Parhar #if defined(INET) || defined(INET6) 3056e936121dSHans Petter Selasky SYSCTL_ADD_U64(&vi->ctx, children, OID_AUTO, "lro_queued", CTLFLAG_RD, 305754e4ee71SNavdeep Parhar &rxq->lro.lro_queued, 0, NULL); 3058e936121dSHans Petter Selasky SYSCTL_ADD_U64(&vi->ctx, children, OID_AUTO, "lro_flushed", CTLFLAG_RD, 305954e4ee71SNavdeep Parhar &rxq->lro.lro_flushed, 0, NULL); 30607d29df59SNavdeep Parhar #endif 3061fe2ebb76SJohn Baldwin SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "rxcsum", CTLFLAG_RD, 306254e4ee71SNavdeep Parhar &rxq->rxcsum, "# of times hardware assisted with checksum"); 3063fe2ebb76SJohn Baldwin SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_extraction", 306454e4ee71SNavdeep Parhar CTLFLAG_RD, &rxq->vlan_extraction, 306554e4ee71SNavdeep Parhar "# of times hardware extracted 802.1Q tag"); 306654e4ee71SNavdeep Parhar 3067aa93b99aSNavdeep Parhar add_fl_sysctls(sc, &vi->ctx, oid, &rxq->fl); 306859bc8ce0SNavdeep Parhar 306954e4ee71SNavdeep Parhar return (rc); 307054e4ee71SNavdeep Parhar } 307154e4ee71SNavdeep Parhar 307254e4ee71SNavdeep Parhar static int 3073fe2ebb76SJohn Baldwin free_rxq(struct vi_info *vi, struct sge_rxq *rxq) 307454e4ee71SNavdeep Parhar { 307554e4ee71SNavdeep Parhar int rc; 307654e4ee71SNavdeep Parhar 3077a1ea9a82SNavdeep Parhar #if defined(INET) || defined(INET6) 307854e4ee71SNavdeep Parhar if (rxq->lro.ifp) { 307954e4ee71SNavdeep Parhar tcp_lro_free(&rxq->lro); 308054e4ee71SNavdeep Parhar rxq->lro.ifp = NULL; 308154e4ee71SNavdeep Parhar } 308254e4ee71SNavdeep Parhar #endif 308354e4ee71SNavdeep Parhar 3084fe2ebb76SJohn Baldwin rc = free_iq_fl(vi, &rxq->iq, &rxq->fl); 308554e4ee71SNavdeep Parhar if (rc == 0) 308654e4ee71SNavdeep Parhar bzero(rxq, sizeof(*rxq)); 308754e4ee71SNavdeep Parhar 308854e4ee71SNavdeep Parhar return (rc); 308954e4ee71SNavdeep Parhar } 309054e4ee71SNavdeep Parhar 309109fe6320SNavdeep Parhar #ifdef TCP_OFFLOAD 309254e4ee71SNavdeep Parhar static int 3093fe2ebb76SJohn Baldwin alloc_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq, 3094733b9277SNavdeep Parhar int intr_idx, int idx, struct sysctl_oid *oid) 3095f7dfe243SNavdeep Parhar { 3096aa93b99aSNavdeep Parhar struct port_info *pi = vi->pi; 3097733b9277SNavdeep Parhar int rc; 3098f7dfe243SNavdeep Parhar struct sysctl_oid_list *children; 3099733b9277SNavdeep Parhar char name[16]; 3100f7dfe243SNavdeep Parhar 31015bcae8ddSNavdeep Parhar rc = alloc_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl, intr_idx, 0); 3102733b9277SNavdeep Parhar if (rc != 0) 3103f7dfe243SNavdeep Parhar return (rc); 3104f7dfe243SNavdeep Parhar 3105733b9277SNavdeep Parhar children = SYSCTL_CHILDREN(oid); 3106733b9277SNavdeep Parhar 3107733b9277SNavdeep Parhar snprintf(name, sizeof(name), "%d", idx); 3108fe2ebb76SJohn Baldwin oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 3109733b9277SNavdeep Parhar NULL, "rx queue"); 3110348694daSNavdeep Parhar add_iq_sysctls(&vi->ctx, oid, &ofld_rxq->iq); 3111aa93b99aSNavdeep Parhar add_fl_sysctls(pi->adapter, &vi->ctx, oid, &ofld_rxq->fl); 3112733b9277SNavdeep Parhar 3113733b9277SNavdeep Parhar return (rc); 3114733b9277SNavdeep Parhar } 3115733b9277SNavdeep Parhar 3116733b9277SNavdeep Parhar static int 3117fe2ebb76SJohn Baldwin free_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq) 3118733b9277SNavdeep Parhar { 3119733b9277SNavdeep Parhar int rc; 3120733b9277SNavdeep Parhar 3121fe2ebb76SJohn Baldwin rc = free_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl); 3122733b9277SNavdeep Parhar if (rc == 0) 3123733b9277SNavdeep Parhar bzero(ofld_rxq, sizeof(*ofld_rxq)); 3124733b9277SNavdeep Parhar 3125733b9277SNavdeep Parhar return (rc); 3126733b9277SNavdeep Parhar } 3127733b9277SNavdeep Parhar #endif 3128733b9277SNavdeep Parhar 3129298d969cSNavdeep Parhar #ifdef DEV_NETMAP 3130298d969cSNavdeep Parhar static int 3131fe2ebb76SJohn Baldwin alloc_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq, int intr_idx, 3132298d969cSNavdeep Parhar int idx, struct sysctl_oid *oid) 3133298d969cSNavdeep Parhar { 3134298d969cSNavdeep Parhar int rc; 3135298d969cSNavdeep Parhar struct sysctl_oid_list *children; 3136298d969cSNavdeep Parhar struct sysctl_ctx_list *ctx; 3137298d969cSNavdeep Parhar char name[16]; 3138298d969cSNavdeep Parhar size_t len; 3139fe2ebb76SJohn Baldwin struct adapter *sc = vi->pi->adapter; 3140fe2ebb76SJohn Baldwin struct netmap_adapter *na = NA(vi->ifp); 3141298d969cSNavdeep Parhar 3142298d969cSNavdeep Parhar MPASS(na != NULL); 3143298d969cSNavdeep Parhar 3144fe2ebb76SJohn Baldwin len = vi->qsize_rxq * IQ_ESIZE; 3145298d969cSNavdeep Parhar rc = alloc_ring(sc, len, &nm_rxq->iq_desc_tag, &nm_rxq->iq_desc_map, 3146298d969cSNavdeep Parhar &nm_rxq->iq_ba, (void **)&nm_rxq->iq_desc); 3147298d969cSNavdeep Parhar if (rc != 0) 3148298d969cSNavdeep Parhar return (rc); 3149298d969cSNavdeep Parhar 315090e7434aSNavdeep Parhar len = na->num_rx_desc * EQ_ESIZE + sc->params.sge.spg_len; 3151298d969cSNavdeep Parhar rc = alloc_ring(sc, len, &nm_rxq->fl_desc_tag, &nm_rxq->fl_desc_map, 3152298d969cSNavdeep Parhar &nm_rxq->fl_ba, (void **)&nm_rxq->fl_desc); 3153298d969cSNavdeep Parhar if (rc != 0) 3154298d969cSNavdeep Parhar return (rc); 3155298d969cSNavdeep Parhar 3156fe2ebb76SJohn Baldwin nm_rxq->vi = vi; 3157298d969cSNavdeep Parhar nm_rxq->nid = idx; 3158298d969cSNavdeep Parhar nm_rxq->iq_cidx = 0; 315990e7434aSNavdeep Parhar nm_rxq->iq_sidx = vi->qsize_rxq - sc->params.sge.spg_len / IQ_ESIZE; 3160298d969cSNavdeep Parhar nm_rxq->iq_gen = F_RSPD_GEN; 3161298d969cSNavdeep Parhar nm_rxq->fl_pidx = nm_rxq->fl_cidx = 0; 3162298d969cSNavdeep Parhar nm_rxq->fl_sidx = na->num_rx_desc; 3163298d969cSNavdeep Parhar nm_rxq->intr_idx = intr_idx; 3164a8c4fcb9SNavdeep Parhar nm_rxq->iq_cntxt_id = INVALID_NM_RXQ_CNTXT_ID; 3165298d969cSNavdeep Parhar 3166fe2ebb76SJohn Baldwin ctx = &vi->ctx; 3167298d969cSNavdeep Parhar children = SYSCTL_CHILDREN(oid); 3168298d969cSNavdeep Parhar 3169298d969cSNavdeep Parhar snprintf(name, sizeof(name), "%d", idx); 3170298d969cSNavdeep Parhar oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, name, CTLFLAG_RD, NULL, 3171298d969cSNavdeep Parhar "rx queue"); 3172298d969cSNavdeep Parhar children = SYSCTL_CHILDREN(oid); 3173298d969cSNavdeep Parhar 3174298d969cSNavdeep Parhar SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "abs_id", 3175298d969cSNavdeep Parhar CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_abs_id, 0, sysctl_uint16, 3176298d969cSNavdeep Parhar "I", "absolute id of the queue"); 3177298d969cSNavdeep Parhar SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 3178298d969cSNavdeep Parhar CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cntxt_id, 0, sysctl_uint16, 3179298d969cSNavdeep Parhar "I", "SGE context id of the queue"); 3180298d969cSNavdeep Parhar SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx", 3181298d969cSNavdeep Parhar CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cidx, 0, sysctl_uint16, "I", 3182298d969cSNavdeep Parhar "consumer index"); 3183298d969cSNavdeep Parhar 3184298d969cSNavdeep Parhar children = SYSCTL_CHILDREN(oid); 3185298d969cSNavdeep Parhar oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL, 3186298d969cSNavdeep Parhar "freelist"); 3187298d969cSNavdeep Parhar children = SYSCTL_CHILDREN(oid); 3188298d969cSNavdeep Parhar 3189298d969cSNavdeep Parhar SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 3190298d969cSNavdeep Parhar CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->fl_cntxt_id, 0, sysctl_uint16, 3191298d969cSNavdeep Parhar "I", "SGE context id of the freelist"); 3192298d969cSNavdeep Parhar SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, 3193298d969cSNavdeep Parhar &nm_rxq->fl_cidx, 0, "consumer index"); 3194298d969cSNavdeep Parhar SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, 3195298d969cSNavdeep Parhar &nm_rxq->fl_pidx, 0, "producer index"); 3196298d969cSNavdeep Parhar 3197298d969cSNavdeep Parhar return (rc); 3198298d969cSNavdeep Parhar } 3199298d969cSNavdeep Parhar 3200298d969cSNavdeep Parhar 3201298d969cSNavdeep Parhar static int 3202fe2ebb76SJohn Baldwin free_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq) 3203298d969cSNavdeep Parhar { 3204fe2ebb76SJohn Baldwin struct adapter *sc = vi->pi->adapter; 3205298d969cSNavdeep Parhar 32060fa7560dSNavdeep Parhar if (vi->flags & VI_INIT_DONE) 3207a8c4fcb9SNavdeep Parhar MPASS(nm_rxq->iq_cntxt_id == INVALID_NM_RXQ_CNTXT_ID); 32080fa7560dSNavdeep Parhar else 32090fa7560dSNavdeep Parhar MPASS(nm_rxq->iq_cntxt_id == 0); 3210a8c4fcb9SNavdeep Parhar 3211298d969cSNavdeep Parhar free_ring(sc, nm_rxq->iq_desc_tag, nm_rxq->iq_desc_map, nm_rxq->iq_ba, 3212298d969cSNavdeep Parhar nm_rxq->iq_desc); 3213298d969cSNavdeep Parhar free_ring(sc, nm_rxq->fl_desc_tag, nm_rxq->fl_desc_map, nm_rxq->fl_ba, 3214298d969cSNavdeep Parhar nm_rxq->fl_desc); 3215298d969cSNavdeep Parhar 3216298d969cSNavdeep Parhar return (0); 3217298d969cSNavdeep Parhar } 3218298d969cSNavdeep Parhar 3219298d969cSNavdeep Parhar static int 3220fe2ebb76SJohn Baldwin alloc_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq, int iqidx, int idx, 3221298d969cSNavdeep Parhar struct sysctl_oid *oid) 3222298d969cSNavdeep Parhar { 3223298d969cSNavdeep Parhar int rc; 3224298d969cSNavdeep Parhar size_t len; 3225fe2ebb76SJohn Baldwin struct port_info *pi = vi->pi; 3226298d969cSNavdeep Parhar struct adapter *sc = pi->adapter; 3227fe2ebb76SJohn Baldwin struct netmap_adapter *na = NA(vi->ifp); 3228298d969cSNavdeep Parhar char name[16]; 3229298d969cSNavdeep Parhar struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3230298d969cSNavdeep Parhar 323190e7434aSNavdeep Parhar len = na->num_tx_desc * EQ_ESIZE + sc->params.sge.spg_len; 3232298d969cSNavdeep Parhar rc = alloc_ring(sc, len, &nm_txq->desc_tag, &nm_txq->desc_map, 3233298d969cSNavdeep Parhar &nm_txq->ba, (void **)&nm_txq->desc); 3234298d969cSNavdeep Parhar if (rc) 3235298d969cSNavdeep Parhar return (rc); 3236298d969cSNavdeep Parhar 3237298d969cSNavdeep Parhar nm_txq->pidx = nm_txq->cidx = 0; 3238298d969cSNavdeep Parhar nm_txq->sidx = na->num_tx_desc; 3239298d969cSNavdeep Parhar nm_txq->nid = idx; 3240298d969cSNavdeep Parhar nm_txq->iqidx = iqidx; 3241298d969cSNavdeep Parhar nm_txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) | 324297f2919dSNavdeep Parhar V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(G_FW_VIID_PFN(vi->viid)) | 324397f2919dSNavdeep Parhar V_TXPKT_VF(G_FW_VIID_VIN(vi->viid)) | 324497f2919dSNavdeep Parhar V_TXPKT_VF_VLD(G_FW_VIID_VIVLD(vi->viid))); 3245a8c4fcb9SNavdeep Parhar nm_txq->cntxt_id = INVALID_NM_TXQ_CNTXT_ID; 3246298d969cSNavdeep Parhar 3247298d969cSNavdeep Parhar snprintf(name, sizeof(name), "%d", idx); 3248fe2ebb76SJohn Baldwin oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 3249298d969cSNavdeep Parhar NULL, "netmap tx queue"); 3250298d969cSNavdeep Parhar children = SYSCTL_CHILDREN(oid); 3251298d969cSNavdeep Parhar 3252fe2ebb76SJohn Baldwin SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 3253298d969cSNavdeep Parhar &nm_txq->cntxt_id, 0, "SGE context id of the queue"); 3254fe2ebb76SJohn Baldwin SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx", 3255298d969cSNavdeep Parhar CTLTYPE_INT | CTLFLAG_RD, &nm_txq->cidx, 0, sysctl_uint16, "I", 3256298d969cSNavdeep Parhar "consumer index"); 3257fe2ebb76SJohn Baldwin SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "pidx", 3258298d969cSNavdeep Parhar CTLTYPE_INT | CTLFLAG_RD, &nm_txq->pidx, 0, sysctl_uint16, "I", 3259298d969cSNavdeep Parhar "producer index"); 3260298d969cSNavdeep Parhar 3261298d969cSNavdeep Parhar return (rc); 3262298d969cSNavdeep Parhar } 3263298d969cSNavdeep Parhar 3264298d969cSNavdeep Parhar static int 3265fe2ebb76SJohn Baldwin free_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq) 3266298d969cSNavdeep Parhar { 3267fe2ebb76SJohn Baldwin struct adapter *sc = vi->pi->adapter; 3268298d969cSNavdeep Parhar 32690fa7560dSNavdeep Parhar if (vi->flags & VI_INIT_DONE) 3270a8c4fcb9SNavdeep Parhar MPASS(nm_txq->cntxt_id == INVALID_NM_TXQ_CNTXT_ID); 32710fa7560dSNavdeep Parhar else 32720fa7560dSNavdeep Parhar MPASS(nm_txq->cntxt_id == 0); 3273a8c4fcb9SNavdeep Parhar 3274298d969cSNavdeep Parhar free_ring(sc, nm_txq->desc_tag, nm_txq->desc_map, nm_txq->ba, 3275298d969cSNavdeep Parhar nm_txq->desc); 3276298d969cSNavdeep Parhar 3277298d969cSNavdeep Parhar return (0); 3278298d969cSNavdeep Parhar } 3279298d969cSNavdeep Parhar #endif 3280298d969cSNavdeep Parhar 3281733b9277SNavdeep Parhar static int 3282733b9277SNavdeep Parhar ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq) 3283733b9277SNavdeep Parhar { 3284733b9277SNavdeep Parhar int rc, cntxt_id; 3285733b9277SNavdeep Parhar struct fw_eq_ctrl_cmd c; 328690e7434aSNavdeep Parhar int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 3287f7dfe243SNavdeep Parhar 3288f7dfe243SNavdeep Parhar bzero(&c, sizeof(c)); 3289f7dfe243SNavdeep Parhar 3290f7dfe243SNavdeep Parhar c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | F_FW_CMD_REQUEST | 3291f7dfe243SNavdeep Parhar F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_CTRL_CMD_PFN(sc->pf) | 3292f7dfe243SNavdeep Parhar V_FW_EQ_CTRL_CMD_VFN(0)); 3293f7dfe243SNavdeep Parhar c.alloc_to_len16 = htobe32(F_FW_EQ_CTRL_CMD_ALLOC | 3294f7dfe243SNavdeep Parhar F_FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c)); 32957951040fSNavdeep Parhar c.cmpliqid_eqid = htonl(V_FW_EQ_CTRL_CMD_CMPLIQID(eq->iqid)); 3296f7dfe243SNavdeep Parhar c.physeqid_pkd = htobe32(0); 3297f7dfe243SNavdeep Parhar c.fetchszm_to_iqid = 329887b027baSNavdeep Parhar htobe32(V_FW_EQ_CTRL_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 3299733b9277SNavdeep Parhar V_FW_EQ_CTRL_CMD_PCIECHN(eq->tx_chan) | 330056599263SNavdeep Parhar F_FW_EQ_CTRL_CMD_FETCHRO | V_FW_EQ_CTRL_CMD_IQID(eq->iqid)); 3301f7dfe243SNavdeep Parhar c.dcaen_to_eqsize = 3302f7dfe243SNavdeep Parhar htobe32(V_FW_EQ_CTRL_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 3303f7dfe243SNavdeep Parhar V_FW_EQ_CTRL_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 330487b027baSNavdeep Parhar V_FW_EQ_CTRL_CMD_CIDXFTHRESH(X_CIDXFLUSHTHRESH_32) | 33057951040fSNavdeep Parhar V_FW_EQ_CTRL_CMD_EQSIZE(qsize)); 3306f7dfe243SNavdeep Parhar c.eqaddr = htobe64(eq->ba); 3307f7dfe243SNavdeep Parhar 3308f7dfe243SNavdeep Parhar rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3309f7dfe243SNavdeep Parhar if (rc != 0) { 3310f7dfe243SNavdeep Parhar device_printf(sc->dev, 3311733b9277SNavdeep Parhar "failed to create control queue %d: %d\n", eq->tx_chan, rc); 3312f7dfe243SNavdeep Parhar return (rc); 3313f7dfe243SNavdeep Parhar } 3314733b9277SNavdeep Parhar eq->flags |= EQ_ALLOCATED; 3315f7dfe243SNavdeep Parhar 3316f7dfe243SNavdeep Parhar eq->cntxt_id = G_FW_EQ_CTRL_CMD_EQID(be32toh(c.cmpliqid_eqid)); 3317f7dfe243SNavdeep Parhar cntxt_id = eq->cntxt_id - sc->sge.eq_start; 3318733b9277SNavdeep Parhar if (cntxt_id >= sc->sge.neq) 3319733b9277SNavdeep Parhar panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 3320733b9277SNavdeep Parhar cntxt_id, sc->sge.neq - 1); 3321f7dfe243SNavdeep Parhar sc->sge.eqmap[cntxt_id] = eq; 3322f7dfe243SNavdeep Parhar 3323f7dfe243SNavdeep Parhar return (rc); 3324f7dfe243SNavdeep Parhar } 3325f7dfe243SNavdeep Parhar 3326f7dfe243SNavdeep Parhar static int 3327fe2ebb76SJohn Baldwin eth_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 332854e4ee71SNavdeep Parhar { 332954e4ee71SNavdeep Parhar int rc, cntxt_id; 333054e4ee71SNavdeep Parhar struct fw_eq_eth_cmd c; 333190e7434aSNavdeep Parhar int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 333254e4ee71SNavdeep Parhar 333354e4ee71SNavdeep Parhar bzero(&c, sizeof(c)); 333454e4ee71SNavdeep Parhar 333554e4ee71SNavdeep Parhar c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST | 333654e4ee71SNavdeep Parhar F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) | 333754e4ee71SNavdeep Parhar V_FW_EQ_ETH_CMD_VFN(0)); 333854e4ee71SNavdeep Parhar c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC | 333954e4ee71SNavdeep Parhar F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c)); 33407951040fSNavdeep Parhar c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE | 3341fe2ebb76SJohn Baldwin F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(vi->viid)); 334254e4ee71SNavdeep Parhar c.fetchszm_to_iqid = 33437951040fSNavdeep Parhar htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) | 3344733b9277SNavdeep Parhar V_FW_EQ_ETH_CMD_PCIECHN(eq->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO | 3345aa2457e1SNavdeep Parhar V_FW_EQ_ETH_CMD_IQID(eq->iqid)); 334654e4ee71SNavdeep Parhar c.dcaen_to_eqsize = htobe32(V_FW_EQ_ETH_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 334754e4ee71SNavdeep Parhar V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 33487951040fSNavdeep Parhar V_FW_EQ_ETH_CMD_EQSIZE(qsize)); 334954e4ee71SNavdeep Parhar c.eqaddr = htobe64(eq->ba); 335054e4ee71SNavdeep Parhar 335154e4ee71SNavdeep Parhar rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 335254e4ee71SNavdeep Parhar if (rc != 0) { 3353fe2ebb76SJohn Baldwin device_printf(vi->dev, 3354733b9277SNavdeep Parhar "failed to create Ethernet egress queue: %d\n", rc); 3355733b9277SNavdeep Parhar return (rc); 3356733b9277SNavdeep Parhar } 3357733b9277SNavdeep Parhar eq->flags |= EQ_ALLOCATED; 3358733b9277SNavdeep Parhar 3359733b9277SNavdeep Parhar eq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd)); 3360ec55567cSJohn Baldwin eq->abs_id = G_FW_EQ_ETH_CMD_PHYSEQID(be32toh(c.physeqid_pkd)); 3361733b9277SNavdeep Parhar cntxt_id = eq->cntxt_id - sc->sge.eq_start; 3362733b9277SNavdeep Parhar if (cntxt_id >= sc->sge.neq) 3363733b9277SNavdeep Parhar panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 3364733b9277SNavdeep Parhar cntxt_id, sc->sge.neq - 1); 3365733b9277SNavdeep Parhar sc->sge.eqmap[cntxt_id] = eq; 3366733b9277SNavdeep Parhar 336754e4ee71SNavdeep Parhar return (rc); 336854e4ee71SNavdeep Parhar } 336954e4ee71SNavdeep Parhar 337009fe6320SNavdeep Parhar #ifdef TCP_OFFLOAD 3371733b9277SNavdeep Parhar static int 3372fe2ebb76SJohn Baldwin ofld_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 3373733b9277SNavdeep Parhar { 3374733b9277SNavdeep Parhar int rc, cntxt_id; 3375733b9277SNavdeep Parhar struct fw_eq_ofld_cmd c; 337690e7434aSNavdeep Parhar int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 337754e4ee71SNavdeep Parhar 3378733b9277SNavdeep Parhar bzero(&c, sizeof(c)); 3379733b9277SNavdeep Parhar 3380733b9277SNavdeep Parhar c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | F_FW_CMD_REQUEST | 3381733b9277SNavdeep Parhar F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_OFLD_CMD_PFN(sc->pf) | 3382733b9277SNavdeep Parhar V_FW_EQ_OFLD_CMD_VFN(0)); 3383733b9277SNavdeep Parhar c.alloc_to_len16 = htonl(F_FW_EQ_OFLD_CMD_ALLOC | 3384733b9277SNavdeep Parhar F_FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c)); 3385733b9277SNavdeep Parhar c.fetchszm_to_iqid = 33867951040fSNavdeep Parhar htonl(V_FW_EQ_OFLD_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) | 3387733b9277SNavdeep Parhar V_FW_EQ_OFLD_CMD_PCIECHN(eq->tx_chan) | 3388733b9277SNavdeep Parhar F_FW_EQ_OFLD_CMD_FETCHRO | V_FW_EQ_OFLD_CMD_IQID(eq->iqid)); 3389733b9277SNavdeep Parhar c.dcaen_to_eqsize = 3390733b9277SNavdeep Parhar htobe32(V_FW_EQ_OFLD_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 3391733b9277SNavdeep Parhar V_FW_EQ_OFLD_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 33927951040fSNavdeep Parhar V_FW_EQ_OFLD_CMD_EQSIZE(qsize)); 3393733b9277SNavdeep Parhar c.eqaddr = htobe64(eq->ba); 3394733b9277SNavdeep Parhar 3395733b9277SNavdeep Parhar rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 3396733b9277SNavdeep Parhar if (rc != 0) { 3397fe2ebb76SJohn Baldwin device_printf(vi->dev, 3398733b9277SNavdeep Parhar "failed to create egress queue for TCP offload: %d\n", rc); 3399733b9277SNavdeep Parhar return (rc); 3400733b9277SNavdeep Parhar } 3401733b9277SNavdeep Parhar eq->flags |= EQ_ALLOCATED; 3402733b9277SNavdeep Parhar 3403733b9277SNavdeep Parhar eq->cntxt_id = G_FW_EQ_OFLD_CMD_EQID(be32toh(c.eqid_pkd)); 340454e4ee71SNavdeep Parhar cntxt_id = eq->cntxt_id - sc->sge.eq_start; 3405733b9277SNavdeep Parhar if (cntxt_id >= sc->sge.neq) 3406733b9277SNavdeep Parhar panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 3407733b9277SNavdeep Parhar cntxt_id, sc->sge.neq - 1); 340854e4ee71SNavdeep Parhar sc->sge.eqmap[cntxt_id] = eq; 340954e4ee71SNavdeep Parhar 3410733b9277SNavdeep Parhar return (rc); 3411733b9277SNavdeep Parhar } 3412733b9277SNavdeep Parhar #endif 3413733b9277SNavdeep Parhar 3414733b9277SNavdeep Parhar static int 3415fe2ebb76SJohn Baldwin alloc_eq(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq) 3416733b9277SNavdeep Parhar { 34177951040fSNavdeep Parhar int rc, qsize; 3418733b9277SNavdeep Parhar size_t len; 3419733b9277SNavdeep Parhar 3420733b9277SNavdeep Parhar mtx_init(&eq->eq_lock, eq->lockname, NULL, MTX_DEF); 3421733b9277SNavdeep Parhar 342290e7434aSNavdeep Parhar qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE; 34237951040fSNavdeep Parhar len = qsize * EQ_ESIZE; 3424733b9277SNavdeep Parhar rc = alloc_ring(sc, len, &eq->desc_tag, &eq->desc_map, 3425733b9277SNavdeep Parhar &eq->ba, (void **)&eq->desc); 3426733b9277SNavdeep Parhar if (rc) 3427733b9277SNavdeep Parhar return (rc); 3428733b9277SNavdeep Parhar 3429733b9277SNavdeep Parhar eq->pidx = eq->cidx = 0; 34307951040fSNavdeep Parhar eq->equeqidx = eq->dbidx = 0; 3431d14b0ac1SNavdeep Parhar eq->doorbells = sc->doorbells; 3432733b9277SNavdeep Parhar 3433733b9277SNavdeep Parhar switch (eq->flags & EQ_TYPEMASK) { 3434733b9277SNavdeep Parhar case EQ_CTRL: 3435733b9277SNavdeep Parhar rc = ctrl_eq_alloc(sc, eq); 3436733b9277SNavdeep Parhar break; 3437733b9277SNavdeep Parhar 3438733b9277SNavdeep Parhar case EQ_ETH: 3439fe2ebb76SJohn Baldwin rc = eth_eq_alloc(sc, vi, eq); 3440733b9277SNavdeep Parhar break; 3441733b9277SNavdeep Parhar 344209fe6320SNavdeep Parhar #ifdef TCP_OFFLOAD 3443733b9277SNavdeep Parhar case EQ_OFLD: 3444fe2ebb76SJohn Baldwin rc = ofld_eq_alloc(sc, vi, eq); 3445733b9277SNavdeep Parhar break; 3446733b9277SNavdeep Parhar #endif 3447733b9277SNavdeep Parhar 3448733b9277SNavdeep Parhar default: 3449733b9277SNavdeep Parhar panic("%s: invalid eq type %d.", __func__, 3450733b9277SNavdeep Parhar eq->flags & EQ_TYPEMASK); 3451733b9277SNavdeep Parhar } 3452733b9277SNavdeep Parhar if (rc != 0) { 3453733b9277SNavdeep Parhar device_printf(sc->dev, 3454c086e3d1SNavdeep Parhar "failed to allocate egress queue(%d): %d\n", 3455733b9277SNavdeep Parhar eq->flags & EQ_TYPEMASK, rc); 3456733b9277SNavdeep Parhar } 3457733b9277SNavdeep Parhar 3458d14b0ac1SNavdeep Parhar if (isset(&eq->doorbells, DOORBELL_UDB) || 3459d14b0ac1SNavdeep Parhar isset(&eq->doorbells, DOORBELL_UDBWC) || 346077ad3c41SNavdeep Parhar isset(&eq->doorbells, DOORBELL_WCWR)) { 346190e7434aSNavdeep Parhar uint32_t s_qpp = sc->params.sge.eq_s_qpp; 3462d14b0ac1SNavdeep Parhar uint32_t mask = (1 << s_qpp) - 1; 3463d14b0ac1SNavdeep Parhar volatile uint8_t *udb; 3464d14b0ac1SNavdeep Parhar 3465d14b0ac1SNavdeep Parhar udb = sc->udbs_base + UDBS_DB_OFFSET; 3466d14b0ac1SNavdeep Parhar udb += (eq->cntxt_id >> s_qpp) << PAGE_SHIFT; /* pg offset */ 3467d14b0ac1SNavdeep Parhar eq->udb_qid = eq->cntxt_id & mask; /* id in page */ 3468f10405b3SNavdeep Parhar if (eq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE) 346977ad3c41SNavdeep Parhar clrbit(&eq->doorbells, DOORBELL_WCWR); 3470d14b0ac1SNavdeep Parhar else { 3471d14b0ac1SNavdeep Parhar udb += eq->udb_qid << UDBS_SEG_SHIFT; /* seg offset */ 3472d14b0ac1SNavdeep Parhar eq->udb_qid = 0; 3473d14b0ac1SNavdeep Parhar } 3474d14b0ac1SNavdeep Parhar eq->udb = (volatile void *)udb; 3475d14b0ac1SNavdeep Parhar } 3476d14b0ac1SNavdeep Parhar 3477733b9277SNavdeep Parhar return (rc); 3478733b9277SNavdeep Parhar } 3479733b9277SNavdeep Parhar 3480733b9277SNavdeep Parhar static int 3481733b9277SNavdeep Parhar free_eq(struct adapter *sc, struct sge_eq *eq) 3482733b9277SNavdeep Parhar { 3483733b9277SNavdeep Parhar int rc; 3484733b9277SNavdeep Parhar 3485733b9277SNavdeep Parhar if (eq->flags & EQ_ALLOCATED) { 3486733b9277SNavdeep Parhar switch (eq->flags & EQ_TYPEMASK) { 3487733b9277SNavdeep Parhar case EQ_CTRL: 3488733b9277SNavdeep Parhar rc = -t4_ctrl_eq_free(sc, sc->mbox, sc->pf, 0, 3489733b9277SNavdeep Parhar eq->cntxt_id); 3490733b9277SNavdeep Parhar break; 3491733b9277SNavdeep Parhar 3492733b9277SNavdeep Parhar case EQ_ETH: 3493733b9277SNavdeep Parhar rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0, 3494733b9277SNavdeep Parhar eq->cntxt_id); 3495733b9277SNavdeep Parhar break; 3496733b9277SNavdeep Parhar 349709fe6320SNavdeep Parhar #ifdef TCP_OFFLOAD 3498733b9277SNavdeep Parhar case EQ_OFLD: 3499733b9277SNavdeep Parhar rc = -t4_ofld_eq_free(sc, sc->mbox, sc->pf, 0, 3500733b9277SNavdeep Parhar eq->cntxt_id); 3501733b9277SNavdeep Parhar break; 3502733b9277SNavdeep Parhar #endif 3503733b9277SNavdeep Parhar 3504733b9277SNavdeep Parhar default: 3505733b9277SNavdeep Parhar panic("%s: invalid eq type %d.", __func__, 3506733b9277SNavdeep Parhar eq->flags & EQ_TYPEMASK); 3507733b9277SNavdeep Parhar } 3508733b9277SNavdeep Parhar if (rc != 0) { 3509733b9277SNavdeep Parhar device_printf(sc->dev, 3510733b9277SNavdeep Parhar "failed to free egress queue (%d): %d\n", 3511733b9277SNavdeep Parhar eq->flags & EQ_TYPEMASK, rc); 3512733b9277SNavdeep Parhar return (rc); 3513733b9277SNavdeep Parhar } 3514733b9277SNavdeep Parhar eq->flags &= ~EQ_ALLOCATED; 3515733b9277SNavdeep Parhar } 3516733b9277SNavdeep Parhar 3517733b9277SNavdeep Parhar free_ring(sc, eq->desc_tag, eq->desc_map, eq->ba, eq->desc); 3518733b9277SNavdeep Parhar 3519733b9277SNavdeep Parhar if (mtx_initialized(&eq->eq_lock)) 3520733b9277SNavdeep Parhar mtx_destroy(&eq->eq_lock); 3521733b9277SNavdeep Parhar 3522733b9277SNavdeep Parhar bzero(eq, sizeof(*eq)); 3523733b9277SNavdeep Parhar return (0); 3524733b9277SNavdeep Parhar } 3525733b9277SNavdeep Parhar 3526733b9277SNavdeep Parhar static int 3527fe2ebb76SJohn Baldwin alloc_wrq(struct adapter *sc, struct vi_info *vi, struct sge_wrq *wrq, 3528733b9277SNavdeep Parhar struct sysctl_oid *oid) 3529733b9277SNavdeep Parhar { 3530733b9277SNavdeep Parhar int rc; 3531fe2ebb76SJohn Baldwin struct sysctl_ctx_list *ctx = vi ? &vi->ctx : &sc->ctx; 3532733b9277SNavdeep Parhar struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3533733b9277SNavdeep Parhar 3534fe2ebb76SJohn Baldwin rc = alloc_eq(sc, vi, &wrq->eq); 3535733b9277SNavdeep Parhar if (rc) 3536733b9277SNavdeep Parhar return (rc); 3537733b9277SNavdeep Parhar 3538733b9277SNavdeep Parhar wrq->adapter = sc; 35397951040fSNavdeep Parhar TASK_INIT(&wrq->wrq_tx_task, 0, wrq_tx_drain, wrq); 35407951040fSNavdeep Parhar TAILQ_INIT(&wrq->incomplete_wrs); 354109fe6320SNavdeep Parhar STAILQ_INIT(&wrq->wr_list); 35427951040fSNavdeep Parhar wrq->nwr_pending = 0; 35437951040fSNavdeep Parhar wrq->ndesc_needed = 0; 3544733b9277SNavdeep Parhar 3545aa93b99aSNavdeep Parhar SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, 3546aa93b99aSNavdeep Parhar &wrq->eq.ba, "bus address of descriptor ring"); 3547aa93b99aSNavdeep Parhar SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3548aa93b99aSNavdeep Parhar wrq->eq.sidx * EQ_ESIZE + sc->params.sge.spg_len, 3549aa93b99aSNavdeep Parhar "desc ring size in bytes"); 3550733b9277SNavdeep Parhar SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 3551733b9277SNavdeep Parhar &wrq->eq.cntxt_id, 0, "SGE context id of the queue"); 3552733b9277SNavdeep Parhar SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx", 3553733b9277SNavdeep Parhar CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.cidx, 0, sysctl_uint16, "I", 3554733b9277SNavdeep Parhar "consumer index"); 3555733b9277SNavdeep Parhar SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pidx", 3556733b9277SNavdeep Parhar CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.pidx, 0, sysctl_uint16, "I", 3557733b9277SNavdeep Parhar "producer index"); 3558aa93b99aSNavdeep Parhar SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL, 3559aa93b99aSNavdeep Parhar wrq->eq.sidx, "status page index"); 35607951040fSNavdeep Parhar SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_direct", CTLFLAG_RD, 35617951040fSNavdeep Parhar &wrq->tx_wrs_direct, "# of work requests (direct)"); 35627951040fSNavdeep Parhar SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_copied", CTLFLAG_RD, 35637951040fSNavdeep Parhar &wrq->tx_wrs_copied, "# of work requests (copied)"); 35640459a175SNavdeep Parhar SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_sspace", CTLFLAG_RD, 35650459a175SNavdeep Parhar &wrq->tx_wrs_ss, "# of work requests (copied from scratch space)"); 3566733b9277SNavdeep Parhar 3567733b9277SNavdeep Parhar return (rc); 3568733b9277SNavdeep Parhar } 3569733b9277SNavdeep Parhar 3570733b9277SNavdeep Parhar static int 3571733b9277SNavdeep Parhar free_wrq(struct adapter *sc, struct sge_wrq *wrq) 3572733b9277SNavdeep Parhar { 3573733b9277SNavdeep Parhar int rc; 3574733b9277SNavdeep Parhar 3575733b9277SNavdeep Parhar rc = free_eq(sc, &wrq->eq); 3576733b9277SNavdeep Parhar if (rc) 3577733b9277SNavdeep Parhar return (rc); 3578733b9277SNavdeep Parhar 3579733b9277SNavdeep Parhar bzero(wrq, sizeof(*wrq)); 3580733b9277SNavdeep Parhar return (0); 3581733b9277SNavdeep Parhar } 3582733b9277SNavdeep Parhar 3583733b9277SNavdeep Parhar static int 3584fe2ebb76SJohn Baldwin alloc_txq(struct vi_info *vi, struct sge_txq *txq, int idx, 3585733b9277SNavdeep Parhar struct sysctl_oid *oid) 3586733b9277SNavdeep Parhar { 3587733b9277SNavdeep Parhar int rc; 3588fe2ebb76SJohn Baldwin struct port_info *pi = vi->pi; 3589733b9277SNavdeep Parhar struct adapter *sc = pi->adapter; 3590733b9277SNavdeep Parhar struct sge_eq *eq = &txq->eq; 3591733b9277SNavdeep Parhar char name[16]; 3592733b9277SNavdeep Parhar struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3593733b9277SNavdeep Parhar 35947951040fSNavdeep Parhar rc = mp_ring_alloc(&txq->r, eq->sidx, txq, eth_tx, can_resume_eth_tx, 35957951040fSNavdeep Parhar M_CXGBE, M_WAITOK); 35967951040fSNavdeep Parhar if (rc != 0) { 35977951040fSNavdeep Parhar device_printf(sc->dev, "failed to allocate mp_ring: %d\n", rc); 35987951040fSNavdeep Parhar return (rc); 35997951040fSNavdeep Parhar } 36007951040fSNavdeep Parhar 3601fe2ebb76SJohn Baldwin rc = alloc_eq(sc, vi, eq); 36027951040fSNavdeep Parhar if (rc != 0) { 36037951040fSNavdeep Parhar mp_ring_free(txq->r); 36047951040fSNavdeep Parhar txq->r = NULL; 3605733b9277SNavdeep Parhar return (rc); 36067951040fSNavdeep Parhar } 3607733b9277SNavdeep Parhar 36087951040fSNavdeep Parhar /* Can't fail after this point. */ 36097951040fSNavdeep Parhar 3610ec55567cSJohn Baldwin if (idx == 0) 3611ec55567cSJohn Baldwin sc->sge.eq_base = eq->abs_id - eq->cntxt_id; 3612ec55567cSJohn Baldwin else 3613ec55567cSJohn Baldwin KASSERT(eq->cntxt_id + sc->sge.eq_base == eq->abs_id, 3614ec55567cSJohn Baldwin ("eq_base mismatch")); 3615ec55567cSJohn Baldwin KASSERT(sc->sge.eq_base == 0 || sc->flags & IS_VF, 3616ec55567cSJohn Baldwin ("PF with non-zero eq_base")); 3617ec55567cSJohn Baldwin 36187951040fSNavdeep Parhar TASK_INIT(&txq->tx_reclaim_task, 0, tx_reclaim, eq); 3619fe2ebb76SJohn Baldwin txq->ifp = vi->ifp; 36207951040fSNavdeep Parhar txq->gl = sglist_alloc(TX_SGL_SEGS, M_WAITOK); 36216af45170SJohn Baldwin if (sc->flags & IS_VF) 36226af45170SJohn Baldwin txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) | 36236af45170SJohn Baldwin V_TXPKT_INTF(pi->tx_chan)); 36246af45170SJohn Baldwin else 36257951040fSNavdeep Parhar txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) | 362697f2919dSNavdeep Parhar V_TXPKT_INTF(pi->tx_chan) | 362797f2919dSNavdeep Parhar V_TXPKT_PF(G_FW_VIID_PFN(vi->viid)) | 362897f2919dSNavdeep Parhar V_TXPKT_VF(G_FW_VIID_VIN(vi->viid)) | 362997f2919dSNavdeep Parhar V_TXPKT_VF_VLD(G_FW_VIID_VIVLD(vi->viid))); 363002f972e8SNavdeep Parhar txq->tc_idx = -1; 36317951040fSNavdeep Parhar txq->sdesc = malloc(eq->sidx * sizeof(struct tx_sdesc), M_CXGBE, 3632733b9277SNavdeep Parhar M_ZERO | M_WAITOK); 363354e4ee71SNavdeep Parhar 363454e4ee71SNavdeep Parhar snprintf(name, sizeof(name), "%d", idx); 3635fe2ebb76SJohn Baldwin oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 363654e4ee71SNavdeep Parhar NULL, "tx queue"); 363754e4ee71SNavdeep Parhar children = SYSCTL_CHILDREN(oid); 363854e4ee71SNavdeep Parhar 3639aa93b99aSNavdeep Parhar SYSCTL_ADD_UAUTO(&vi->ctx, children, OID_AUTO, "ba", CTLFLAG_RD, 3640aa93b99aSNavdeep Parhar &eq->ba, "bus address of descriptor ring"); 3641aa93b99aSNavdeep Parhar SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL, 3642aa93b99aSNavdeep Parhar eq->sidx * EQ_ESIZE + sc->params.sge.spg_len, 3643aa93b99aSNavdeep Parhar "desc ring size in bytes"); 3644ec55567cSJohn Baldwin SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "abs_id", CTLFLAG_RD, 3645ec55567cSJohn Baldwin &eq->abs_id, 0, "absolute id of the queue"); 3646fe2ebb76SJohn Baldwin SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 364759bc8ce0SNavdeep Parhar &eq->cntxt_id, 0, "SGE context id of the queue"); 3648fe2ebb76SJohn Baldwin SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx", 364959bc8ce0SNavdeep Parhar CTLTYPE_INT | CTLFLAG_RD, &eq->cidx, 0, sysctl_uint16, "I", 365059bc8ce0SNavdeep Parhar "consumer index"); 3651fe2ebb76SJohn Baldwin SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "pidx", 365259bc8ce0SNavdeep Parhar CTLTYPE_INT | CTLFLAG_RD, &eq->pidx, 0, sysctl_uint16, "I", 365359bc8ce0SNavdeep Parhar "producer index"); 3654aa93b99aSNavdeep Parhar SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL, 3655aa93b99aSNavdeep Parhar eq->sidx, "status page index"); 365659bc8ce0SNavdeep Parhar 365702f972e8SNavdeep Parhar SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "tc", 365802f972e8SNavdeep Parhar CTLTYPE_INT | CTLFLAG_RW, vi, idx, sysctl_tc, "I", 365902f972e8SNavdeep Parhar "traffic class (-1 means none)"); 366002f972e8SNavdeep Parhar 3661fe2ebb76SJohn Baldwin SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txcsum", CTLFLAG_RD, 366254e4ee71SNavdeep Parhar &txq->txcsum, "# of times hardware assisted with checksum"); 3663fe2ebb76SJohn Baldwin SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_insertion", 366454e4ee71SNavdeep Parhar CTLFLAG_RD, &txq->vlan_insertion, 366554e4ee71SNavdeep Parhar "# of times hardware inserted 802.1Q tag"); 3666fe2ebb76SJohn Baldwin SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "tso_wrs", CTLFLAG_RD, 3667a1ea9a82SNavdeep Parhar &txq->tso_wrs, "# of TSO work requests"); 3668fe2ebb76SJohn Baldwin SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "imm_wrs", CTLFLAG_RD, 366954e4ee71SNavdeep Parhar &txq->imm_wrs, "# of work requests with immediate data"); 3670fe2ebb76SJohn Baldwin SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "sgl_wrs", CTLFLAG_RD, 367154e4ee71SNavdeep Parhar &txq->sgl_wrs, "# of work requests with direct SGL"); 3672fe2ebb76SJohn Baldwin SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkt_wrs", CTLFLAG_RD, 367354e4ee71SNavdeep Parhar &txq->txpkt_wrs, "# of txpkt work requests (one pkt/WR)"); 3674fe2ebb76SJohn Baldwin SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_wrs", 36757951040fSNavdeep Parhar CTLFLAG_RD, &txq->txpkts0_wrs, 36767951040fSNavdeep Parhar "# of txpkts (type 0) work requests"); 3677fe2ebb76SJohn Baldwin SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_wrs", 36787951040fSNavdeep Parhar CTLFLAG_RD, &txq->txpkts1_wrs, 36797951040fSNavdeep Parhar "# of txpkts (type 1) work requests"); 3680fe2ebb76SJohn Baldwin SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_pkts", 36817951040fSNavdeep Parhar CTLFLAG_RD, &txq->txpkts0_pkts, 36827951040fSNavdeep Parhar "# of frames tx'd using type0 txpkts work requests"); 3683fe2ebb76SJohn Baldwin SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_pkts", 36847951040fSNavdeep Parhar CTLFLAG_RD, &txq->txpkts1_pkts, 36857951040fSNavdeep Parhar "# of frames tx'd using type1 txpkts work requests"); 368654e4ee71SNavdeep Parhar 3687fe2ebb76SJohn Baldwin SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_enqueues", 36887951040fSNavdeep Parhar CTLFLAG_RD, &txq->r->enqueues, 36897951040fSNavdeep Parhar "# of enqueues to the mp_ring for this queue"); 3690fe2ebb76SJohn Baldwin SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_drops", 36917951040fSNavdeep Parhar CTLFLAG_RD, &txq->r->drops, 36927951040fSNavdeep Parhar "# of drops in the mp_ring for this queue"); 3693fe2ebb76SJohn Baldwin SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_starts", 36947951040fSNavdeep Parhar CTLFLAG_RD, &txq->r->starts, 36957951040fSNavdeep Parhar "# of normal consumer starts in the mp_ring for this queue"); 3696fe2ebb76SJohn Baldwin SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_stalls", 36977951040fSNavdeep Parhar CTLFLAG_RD, &txq->r->stalls, 36987951040fSNavdeep Parhar "# of consumer stalls in the mp_ring for this queue"); 3699fe2ebb76SJohn Baldwin SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_restarts", 37007951040fSNavdeep Parhar CTLFLAG_RD, &txq->r->restarts, 37017951040fSNavdeep Parhar "# of consumer restarts in the mp_ring for this queue"); 3702fe2ebb76SJohn Baldwin SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_abdications", 37037951040fSNavdeep Parhar CTLFLAG_RD, &txq->r->abdications, 37047951040fSNavdeep Parhar "# of consumer abdications in the mp_ring for this queue"); 370554e4ee71SNavdeep Parhar 37067951040fSNavdeep Parhar return (0); 370754e4ee71SNavdeep Parhar } 370854e4ee71SNavdeep Parhar 370954e4ee71SNavdeep Parhar static int 3710fe2ebb76SJohn Baldwin free_txq(struct vi_info *vi, struct sge_txq *txq) 371154e4ee71SNavdeep Parhar { 371254e4ee71SNavdeep Parhar int rc; 3713fe2ebb76SJohn Baldwin struct adapter *sc = vi->pi->adapter; 371454e4ee71SNavdeep Parhar struct sge_eq *eq = &txq->eq; 371554e4ee71SNavdeep Parhar 3716733b9277SNavdeep Parhar rc = free_eq(sc, eq); 3717733b9277SNavdeep Parhar if (rc) 371854e4ee71SNavdeep Parhar return (rc); 371954e4ee71SNavdeep Parhar 37207951040fSNavdeep Parhar sglist_free(txq->gl); 3721f7dfe243SNavdeep Parhar free(txq->sdesc, M_CXGBE); 37227951040fSNavdeep Parhar mp_ring_free(txq->r); 372354e4ee71SNavdeep Parhar 372454e4ee71SNavdeep Parhar bzero(txq, sizeof(*txq)); 372554e4ee71SNavdeep Parhar return (0); 372654e4ee71SNavdeep Parhar } 372754e4ee71SNavdeep Parhar 372854e4ee71SNavdeep Parhar static void 372954e4ee71SNavdeep Parhar oneseg_dma_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error) 373054e4ee71SNavdeep Parhar { 373154e4ee71SNavdeep Parhar bus_addr_t *ba = arg; 373254e4ee71SNavdeep Parhar 373354e4ee71SNavdeep Parhar KASSERT(nseg == 1, 373454e4ee71SNavdeep Parhar ("%s meant for single segment mappings only.", __func__)); 373554e4ee71SNavdeep Parhar 373654e4ee71SNavdeep Parhar *ba = error ? 0 : segs->ds_addr; 373754e4ee71SNavdeep Parhar } 373854e4ee71SNavdeep Parhar 373954e4ee71SNavdeep Parhar static inline void 374054e4ee71SNavdeep Parhar ring_fl_db(struct adapter *sc, struct sge_fl *fl) 374154e4ee71SNavdeep Parhar { 37424d6db4e0SNavdeep Parhar uint32_t n, v; 374354e4ee71SNavdeep Parhar 37444d6db4e0SNavdeep Parhar n = IDXDIFF(fl->pidx / 8, fl->dbidx, fl->sidx); 37454d6db4e0SNavdeep Parhar MPASS(n > 0); 3746d14b0ac1SNavdeep Parhar 374754e4ee71SNavdeep Parhar wmb(); 37484d6db4e0SNavdeep Parhar v = fl->dbval | V_PIDX(n); 37494d6db4e0SNavdeep Parhar if (fl->udb) 37504d6db4e0SNavdeep Parhar *fl->udb = htole32(v); 37514d6db4e0SNavdeep Parhar else 3752315048f2SJohn Baldwin t4_write_reg(sc, sc->sge_kdoorbell_reg, v); 37534d6db4e0SNavdeep Parhar IDXINCR(fl->dbidx, n, fl->sidx); 375454e4ee71SNavdeep Parhar } 375554e4ee71SNavdeep Parhar 3756fb12416cSNavdeep Parhar /* 37574d6db4e0SNavdeep Parhar * Fills up the freelist by allocating up to 'n' buffers. Buffers that are 37584d6db4e0SNavdeep Parhar * recycled do not count towards this allocation budget. 3759733b9277SNavdeep Parhar * 37604d6db4e0SNavdeep Parhar * Returns non-zero to indicate that this freelist should be added to the list 37614d6db4e0SNavdeep Parhar * of starving freelists. 3762fb12416cSNavdeep Parhar */ 3763733b9277SNavdeep Parhar static int 37644d6db4e0SNavdeep Parhar refill_fl(struct adapter *sc, struct sge_fl *fl, int n) 376554e4ee71SNavdeep Parhar { 37664d6db4e0SNavdeep Parhar __be64 *d; 37674d6db4e0SNavdeep Parhar struct fl_sdesc *sd; 376838035ed6SNavdeep Parhar uintptr_t pa; 376954e4ee71SNavdeep Parhar caddr_t cl; 37704d6db4e0SNavdeep Parhar struct cluster_layout *cll; 37714d6db4e0SNavdeep Parhar struct sw_zone_info *swz; 377238035ed6SNavdeep Parhar struct cluster_metadata *clm; 37734d6db4e0SNavdeep Parhar uint16_t max_pidx; 37744d6db4e0SNavdeep Parhar uint16_t hw_cidx = fl->hw_cidx; /* stable snapshot */ 377554e4ee71SNavdeep Parhar 377654e4ee71SNavdeep Parhar FL_LOCK_ASSERT_OWNED(fl); 377754e4ee71SNavdeep Parhar 37784d6db4e0SNavdeep Parhar /* 3779453130d9SPedro F. Giffuni * We always stop at the beginning of the hardware descriptor that's just 37804d6db4e0SNavdeep Parhar * before the one with the hw cidx. This is to avoid hw pidx = hw cidx, 37814d6db4e0SNavdeep Parhar * which would mean an empty freelist to the chip. 37824d6db4e0SNavdeep Parhar */ 37834d6db4e0SNavdeep Parhar max_pidx = __predict_false(hw_cidx == 0) ? fl->sidx - 1 : hw_cidx - 1; 37844d6db4e0SNavdeep Parhar if (fl->pidx == max_pidx * 8) 37854d6db4e0SNavdeep Parhar return (0); 378654e4ee71SNavdeep Parhar 37874d6db4e0SNavdeep Parhar d = &fl->desc[fl->pidx]; 37884d6db4e0SNavdeep Parhar sd = &fl->sdesc[fl->pidx]; 37894d6db4e0SNavdeep Parhar cll = &fl->cll_def; /* default layout */ 37904d6db4e0SNavdeep Parhar swz = &sc->sge.sw_zone_info[cll->zidx]; 37914d6db4e0SNavdeep Parhar 37924d6db4e0SNavdeep Parhar while (n > 0) { 379354e4ee71SNavdeep Parhar 379454e4ee71SNavdeep Parhar if (sd->cl != NULL) { 379554e4ee71SNavdeep Parhar 3796c3fb7725SNavdeep Parhar if (sd->nmbuf == 0) { 379738035ed6SNavdeep Parhar /* 379838035ed6SNavdeep Parhar * Fast recycle without involving any atomics on 379938035ed6SNavdeep Parhar * the cluster's metadata (if the cluster has 380038035ed6SNavdeep Parhar * metadata). This happens when all frames 380138035ed6SNavdeep Parhar * received in the cluster were small enough to 380238035ed6SNavdeep Parhar * fit within a single mbuf each. 380338035ed6SNavdeep Parhar */ 380438035ed6SNavdeep Parhar fl->cl_fast_recycled++; 3805ccc69b2fSNavdeep Parhar #ifdef INVARIANTS 3806ccc69b2fSNavdeep Parhar clm = cl_metadata(sc, fl, &sd->cll, sd->cl); 3807ccc69b2fSNavdeep Parhar if (clm != NULL) 3808ccc69b2fSNavdeep Parhar MPASS(clm->refcount == 1); 3809ccc69b2fSNavdeep Parhar #endif 381038035ed6SNavdeep Parhar goto recycled_fast; 381138035ed6SNavdeep Parhar } 381254e4ee71SNavdeep Parhar 381338035ed6SNavdeep Parhar /* 381438035ed6SNavdeep Parhar * Cluster is guaranteed to have metadata. Clusters 381538035ed6SNavdeep Parhar * without metadata always take the fast recycle path 381638035ed6SNavdeep Parhar * when they're recycled. 381738035ed6SNavdeep Parhar */ 381838035ed6SNavdeep Parhar clm = cl_metadata(sc, fl, &sd->cll, sd->cl); 381938035ed6SNavdeep Parhar MPASS(clm != NULL); 38201458bff9SNavdeep Parhar 382138035ed6SNavdeep Parhar if (atomic_fetchadd_int(&clm->refcount, -1) == 1) { 382238035ed6SNavdeep Parhar fl->cl_recycled++; 382382eff304SNavdeep Parhar counter_u64_add(extfree_rels, 1); 382454e4ee71SNavdeep Parhar goto recycled; 382554e4ee71SNavdeep Parhar } 38261458bff9SNavdeep Parhar sd->cl = NULL; /* gave up my reference */ 38271458bff9SNavdeep Parhar } 382838035ed6SNavdeep Parhar MPASS(sd->cl == NULL); 382938035ed6SNavdeep Parhar alloc: 383038035ed6SNavdeep Parhar cl = uma_zalloc(swz->zone, M_NOWAIT); 383138035ed6SNavdeep Parhar if (__predict_false(cl == NULL)) { 383238035ed6SNavdeep Parhar if (cll == &fl->cll_alt || fl->cll_alt.zidx == -1 || 383338035ed6SNavdeep Parhar fl->cll_def.zidx == fl->cll_alt.zidx) 383454e4ee71SNavdeep Parhar break; 383554e4ee71SNavdeep Parhar 383638035ed6SNavdeep Parhar /* fall back to the safe zone */ 383738035ed6SNavdeep Parhar cll = &fl->cll_alt; 383838035ed6SNavdeep Parhar swz = &sc->sge.sw_zone_info[cll->zidx]; 383938035ed6SNavdeep Parhar goto alloc; 384054e4ee71SNavdeep Parhar } 384138035ed6SNavdeep Parhar fl->cl_allocated++; 38424d6db4e0SNavdeep Parhar n--; 384354e4ee71SNavdeep Parhar 384438035ed6SNavdeep Parhar pa = pmap_kextract((vm_offset_t)cl); 384538035ed6SNavdeep Parhar pa += cll->region1; 384654e4ee71SNavdeep Parhar sd->cl = cl; 384738035ed6SNavdeep Parhar sd->cll = *cll; 384838035ed6SNavdeep Parhar *d = htobe64(pa | cll->hwidx); 384938035ed6SNavdeep Parhar clm = cl_metadata(sc, fl, cll, cl); 385038035ed6SNavdeep Parhar if (clm != NULL) { 38517d29df59SNavdeep Parhar recycled: 385238035ed6SNavdeep Parhar #ifdef INVARIANTS 385338035ed6SNavdeep Parhar clm->sd = sd; 385438035ed6SNavdeep Parhar #endif 385538035ed6SNavdeep Parhar clm->refcount = 1; 385638035ed6SNavdeep Parhar } 3857c3fb7725SNavdeep Parhar sd->nmbuf = 0; 385838035ed6SNavdeep Parhar recycled_fast: 385938035ed6SNavdeep Parhar d++; 386054e4ee71SNavdeep Parhar sd++; 38614d6db4e0SNavdeep Parhar if (__predict_false(++fl->pidx % 8 == 0)) { 38624d6db4e0SNavdeep Parhar uint16_t pidx = fl->pidx / 8; 38634d6db4e0SNavdeep Parhar 38644d6db4e0SNavdeep Parhar if (__predict_false(pidx == fl->sidx)) { 386554e4ee71SNavdeep Parhar fl->pidx = 0; 38664d6db4e0SNavdeep Parhar pidx = 0; 386754e4ee71SNavdeep Parhar sd = fl->sdesc; 386854e4ee71SNavdeep Parhar d = fl->desc; 386954e4ee71SNavdeep Parhar } 38704d6db4e0SNavdeep Parhar if (pidx == max_pidx) 38714d6db4e0SNavdeep Parhar break; 38724d6db4e0SNavdeep Parhar 38734d6db4e0SNavdeep Parhar if (IDXDIFF(pidx, fl->dbidx, fl->sidx) >= 4) 38744d6db4e0SNavdeep Parhar ring_fl_db(sc, fl); 38754d6db4e0SNavdeep Parhar } 387654e4ee71SNavdeep Parhar } 3877fb12416cSNavdeep Parhar 38784d6db4e0SNavdeep Parhar if (fl->pidx / 8 != fl->dbidx) 3879fb12416cSNavdeep Parhar ring_fl_db(sc, fl); 3880733b9277SNavdeep Parhar 3881733b9277SNavdeep Parhar return (FL_RUNNING_LOW(fl) && !(fl->flags & FL_STARVING)); 3882733b9277SNavdeep Parhar } 3883733b9277SNavdeep Parhar 3884733b9277SNavdeep Parhar /* 3885733b9277SNavdeep Parhar * Attempt to refill all starving freelists. 3886733b9277SNavdeep Parhar */ 3887733b9277SNavdeep Parhar static void 3888733b9277SNavdeep Parhar refill_sfl(void *arg) 3889733b9277SNavdeep Parhar { 3890733b9277SNavdeep Parhar struct adapter *sc = arg; 3891733b9277SNavdeep Parhar struct sge_fl *fl, *fl_temp; 3892733b9277SNavdeep Parhar 3893fe2ebb76SJohn Baldwin mtx_assert(&sc->sfl_lock, MA_OWNED); 3894733b9277SNavdeep Parhar TAILQ_FOREACH_SAFE(fl, &sc->sfl, link, fl_temp) { 3895733b9277SNavdeep Parhar FL_LOCK(fl); 3896733b9277SNavdeep Parhar refill_fl(sc, fl, 64); 3897733b9277SNavdeep Parhar if (FL_NOT_RUNNING_LOW(fl) || fl->flags & FL_DOOMED) { 3898733b9277SNavdeep Parhar TAILQ_REMOVE(&sc->sfl, fl, link); 3899733b9277SNavdeep Parhar fl->flags &= ~FL_STARVING; 3900733b9277SNavdeep Parhar } 3901733b9277SNavdeep Parhar FL_UNLOCK(fl); 3902733b9277SNavdeep Parhar } 3903733b9277SNavdeep Parhar 3904733b9277SNavdeep Parhar if (!TAILQ_EMPTY(&sc->sfl)) 3905733b9277SNavdeep Parhar callout_schedule(&sc->sfl_callout, hz / 5); 390654e4ee71SNavdeep Parhar } 390754e4ee71SNavdeep Parhar 390854e4ee71SNavdeep Parhar static int 390954e4ee71SNavdeep Parhar alloc_fl_sdesc(struct sge_fl *fl) 391054e4ee71SNavdeep Parhar { 391154e4ee71SNavdeep Parhar 39124d6db4e0SNavdeep Parhar fl->sdesc = malloc(fl->sidx * 8 * sizeof(struct fl_sdesc), M_CXGBE, 391354e4ee71SNavdeep Parhar M_ZERO | M_WAITOK); 391454e4ee71SNavdeep Parhar 391554e4ee71SNavdeep Parhar return (0); 391654e4ee71SNavdeep Parhar } 391754e4ee71SNavdeep Parhar 391854e4ee71SNavdeep Parhar static void 39191458bff9SNavdeep Parhar free_fl_sdesc(struct adapter *sc, struct sge_fl *fl) 392054e4ee71SNavdeep Parhar { 392154e4ee71SNavdeep Parhar struct fl_sdesc *sd; 392238035ed6SNavdeep Parhar struct cluster_metadata *clm; 392338035ed6SNavdeep Parhar struct cluster_layout *cll; 392454e4ee71SNavdeep Parhar int i; 392554e4ee71SNavdeep Parhar 392654e4ee71SNavdeep Parhar sd = fl->sdesc; 39274d6db4e0SNavdeep Parhar for (i = 0; i < fl->sidx * 8; i++, sd++) { 392838035ed6SNavdeep Parhar if (sd->cl == NULL) 392938035ed6SNavdeep Parhar continue; 393054e4ee71SNavdeep Parhar 393138035ed6SNavdeep Parhar cll = &sd->cll; 393238035ed6SNavdeep Parhar clm = cl_metadata(sc, fl, cll, sd->cl); 393382eff304SNavdeep Parhar if (sd->nmbuf == 0) 393438035ed6SNavdeep Parhar uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl); 393582eff304SNavdeep Parhar else if (clm && atomic_fetchadd_int(&clm->refcount, -1) == 1) { 393682eff304SNavdeep Parhar uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl); 393782eff304SNavdeep Parhar counter_u64_add(extfree_rels, 1); 393854e4ee71SNavdeep Parhar } 393938035ed6SNavdeep Parhar sd->cl = NULL; 394054e4ee71SNavdeep Parhar } 394154e4ee71SNavdeep Parhar 394254e4ee71SNavdeep Parhar free(fl->sdesc, M_CXGBE); 394354e4ee71SNavdeep Parhar fl->sdesc = NULL; 394454e4ee71SNavdeep Parhar } 394554e4ee71SNavdeep Parhar 39467951040fSNavdeep Parhar static inline void 39477951040fSNavdeep Parhar get_pkt_gl(struct mbuf *m, struct sglist *gl) 394854e4ee71SNavdeep Parhar { 39497951040fSNavdeep Parhar int rc; 395054e4ee71SNavdeep Parhar 39517951040fSNavdeep Parhar M_ASSERTPKTHDR(m); 395254e4ee71SNavdeep Parhar 39537951040fSNavdeep Parhar sglist_reset(gl); 39547951040fSNavdeep Parhar rc = sglist_append_mbuf(gl, m); 39557951040fSNavdeep Parhar if (__predict_false(rc != 0)) { 39567951040fSNavdeep Parhar panic("%s: mbuf %p (%d segs) was vetted earlier but now fails " 39577951040fSNavdeep Parhar "with %d.", __func__, m, mbuf_nsegs(m), rc); 395854e4ee71SNavdeep Parhar } 395954e4ee71SNavdeep Parhar 39607951040fSNavdeep Parhar KASSERT(gl->sg_nseg == mbuf_nsegs(m), 39617951040fSNavdeep Parhar ("%s: nsegs changed for mbuf %p from %d to %d", __func__, m, 39627951040fSNavdeep Parhar mbuf_nsegs(m), gl->sg_nseg)); 39637951040fSNavdeep Parhar KASSERT(gl->sg_nseg > 0 && 39647951040fSNavdeep Parhar gl->sg_nseg <= (needs_tso(m) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS), 39657951040fSNavdeep Parhar ("%s: %d segments, should have been 1 <= nsegs <= %d", __func__, 39667951040fSNavdeep Parhar gl->sg_nseg, needs_tso(m) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS)); 396754e4ee71SNavdeep Parhar } 396854e4ee71SNavdeep Parhar 396954e4ee71SNavdeep Parhar /* 39707951040fSNavdeep Parhar * len16 for a txpkt WR with a GL. Includes the firmware work request header. 397154e4ee71SNavdeep Parhar */ 39727951040fSNavdeep Parhar static inline u_int 39737951040fSNavdeep Parhar txpkt_len16(u_int nsegs, u_int tso) 39747951040fSNavdeep Parhar { 39757951040fSNavdeep Parhar u_int n; 39767951040fSNavdeep Parhar 39777951040fSNavdeep Parhar MPASS(nsegs > 0); 39787951040fSNavdeep Parhar 39797951040fSNavdeep Parhar nsegs--; /* first segment is part of ulptx_sgl */ 39807951040fSNavdeep Parhar n = sizeof(struct fw_eth_tx_pkt_wr) + sizeof(struct cpl_tx_pkt_core) + 39817951040fSNavdeep Parhar sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 39827951040fSNavdeep Parhar if (tso) 39837951040fSNavdeep Parhar n += sizeof(struct cpl_tx_pkt_lso_core); 39847951040fSNavdeep Parhar 39857951040fSNavdeep Parhar return (howmany(n, 16)); 39867951040fSNavdeep Parhar } 398754e4ee71SNavdeep Parhar 398854e4ee71SNavdeep Parhar /* 39896af45170SJohn Baldwin * len16 for a txpkt_vm WR with a GL. Includes the firmware work 39906af45170SJohn Baldwin * request header. 39916af45170SJohn Baldwin */ 39926af45170SJohn Baldwin static inline u_int 39936af45170SJohn Baldwin txpkt_vm_len16(u_int nsegs, u_int tso) 39946af45170SJohn Baldwin { 39956af45170SJohn Baldwin u_int n; 39966af45170SJohn Baldwin 39976af45170SJohn Baldwin MPASS(nsegs > 0); 39986af45170SJohn Baldwin 39996af45170SJohn Baldwin nsegs--; /* first segment is part of ulptx_sgl */ 40006af45170SJohn Baldwin n = sizeof(struct fw_eth_tx_pkt_vm_wr) + 40016af45170SJohn Baldwin sizeof(struct cpl_tx_pkt_core) + 40026af45170SJohn Baldwin sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 40036af45170SJohn Baldwin if (tso) 40046af45170SJohn Baldwin n += sizeof(struct cpl_tx_pkt_lso_core); 40056af45170SJohn Baldwin 40066af45170SJohn Baldwin return (howmany(n, 16)); 40076af45170SJohn Baldwin } 40086af45170SJohn Baldwin 40096af45170SJohn Baldwin /* 40107951040fSNavdeep Parhar * len16 for a txpkts type 0 WR with a GL. Does not include the firmware work 40117951040fSNavdeep Parhar * request header. 40127951040fSNavdeep Parhar */ 40137951040fSNavdeep Parhar static inline u_int 40147951040fSNavdeep Parhar txpkts0_len16(u_int nsegs) 40157951040fSNavdeep Parhar { 40167951040fSNavdeep Parhar u_int n; 40177951040fSNavdeep Parhar 40187951040fSNavdeep Parhar MPASS(nsegs > 0); 40197951040fSNavdeep Parhar 40207951040fSNavdeep Parhar nsegs--; /* first segment is part of ulptx_sgl */ 40217951040fSNavdeep Parhar n = sizeof(struct ulp_txpkt) + sizeof(struct ulptx_idata) + 40227951040fSNavdeep Parhar sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl) + 40237951040fSNavdeep Parhar 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 40247951040fSNavdeep Parhar 40257951040fSNavdeep Parhar return (howmany(n, 16)); 40267951040fSNavdeep Parhar } 40277951040fSNavdeep Parhar 40287951040fSNavdeep Parhar /* 40297951040fSNavdeep Parhar * len16 for a txpkts type 1 WR with a GL. Does not include the firmware work 40307951040fSNavdeep Parhar * request header. 40317951040fSNavdeep Parhar */ 40327951040fSNavdeep Parhar static inline u_int 40337951040fSNavdeep Parhar txpkts1_len16(void) 40347951040fSNavdeep Parhar { 40357951040fSNavdeep Parhar u_int n; 40367951040fSNavdeep Parhar 40377951040fSNavdeep Parhar n = sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl); 40387951040fSNavdeep Parhar 40397951040fSNavdeep Parhar return (howmany(n, 16)); 40407951040fSNavdeep Parhar } 40417951040fSNavdeep Parhar 40427951040fSNavdeep Parhar static inline u_int 40437951040fSNavdeep Parhar imm_payload(u_int ndesc) 40447951040fSNavdeep Parhar { 40457951040fSNavdeep Parhar u_int n; 40467951040fSNavdeep Parhar 40477951040fSNavdeep Parhar n = ndesc * EQ_ESIZE - sizeof(struct fw_eth_tx_pkt_wr) - 40487951040fSNavdeep Parhar sizeof(struct cpl_tx_pkt_core); 40497951040fSNavdeep Parhar 40507951040fSNavdeep Parhar return (n); 40517951040fSNavdeep Parhar } 40527951040fSNavdeep Parhar 40537951040fSNavdeep Parhar /* 40546af45170SJohn Baldwin * Write a VM txpkt WR for this packet to the hardware descriptors, update the 40556af45170SJohn Baldwin * software descriptor, and advance the pidx. It is guaranteed that enough 40566af45170SJohn Baldwin * descriptors are available. 40576af45170SJohn Baldwin * 40586af45170SJohn Baldwin * The return value is the # of hardware descriptors used. 40596af45170SJohn Baldwin */ 40606af45170SJohn Baldwin static u_int 4061472a6004SNavdeep Parhar write_txpkt_vm_wr(struct adapter *sc, struct sge_txq *txq, 4062472a6004SNavdeep Parhar struct fw_eth_tx_pkt_vm_wr *wr, struct mbuf *m0, u_int available) 40636af45170SJohn Baldwin { 40646af45170SJohn Baldwin struct sge_eq *eq = &txq->eq; 40656af45170SJohn Baldwin struct tx_sdesc *txsd; 40666af45170SJohn Baldwin struct cpl_tx_pkt_core *cpl; 40676af45170SJohn Baldwin uint32_t ctrl; /* used in many unrelated places */ 40686af45170SJohn Baldwin uint64_t ctrl1; 40696af45170SJohn Baldwin int csum_type, len16, ndesc, pktlen, nsegs; 40706af45170SJohn Baldwin caddr_t dst; 40716af45170SJohn Baldwin 40726af45170SJohn Baldwin TXQ_LOCK_ASSERT_OWNED(txq); 40736af45170SJohn Baldwin M_ASSERTPKTHDR(m0); 40746af45170SJohn Baldwin MPASS(available > 0 && available < eq->sidx); 40756af45170SJohn Baldwin 40766af45170SJohn Baldwin len16 = mbuf_len16(m0); 40776af45170SJohn Baldwin nsegs = mbuf_nsegs(m0); 40786af45170SJohn Baldwin pktlen = m0->m_pkthdr.len; 40796af45170SJohn Baldwin ctrl = sizeof(struct cpl_tx_pkt_core); 40806af45170SJohn Baldwin if (needs_tso(m0)) 40816af45170SJohn Baldwin ctrl += sizeof(struct cpl_tx_pkt_lso_core); 40826af45170SJohn Baldwin ndesc = howmany(len16, EQ_ESIZE / 16); 40836af45170SJohn Baldwin MPASS(ndesc <= available); 40846af45170SJohn Baldwin 40856af45170SJohn Baldwin /* Firmware work request header */ 40866af45170SJohn Baldwin MPASS(wr == (void *)&eq->desc[eq->pidx]); 40876af45170SJohn Baldwin wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_VM_WR) | 40886af45170SJohn Baldwin V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl)); 40896af45170SJohn Baldwin 40906af45170SJohn Baldwin ctrl = V_FW_WR_LEN16(len16); 40916af45170SJohn Baldwin wr->equiq_to_len16 = htobe32(ctrl); 40926af45170SJohn Baldwin wr->r3[0] = 0; 40936af45170SJohn Baldwin wr->r3[1] = 0; 40946af45170SJohn Baldwin 40956af45170SJohn Baldwin /* 40966af45170SJohn Baldwin * Copy over ethmacdst, ethmacsrc, ethtype, and vlantci. 40976af45170SJohn Baldwin * vlantci is ignored unless the ethtype is 0x8100, so it's 40986af45170SJohn Baldwin * simpler to always copy it rather than making it 40996af45170SJohn Baldwin * conditional. Also, it seems that we do not have to set 41006af45170SJohn Baldwin * vlantci or fake the ethtype when doing VLAN tag insertion. 41016af45170SJohn Baldwin */ 41026af45170SJohn Baldwin m_copydata(m0, 0, sizeof(struct ether_header) + 2, wr->ethmacdst); 41036af45170SJohn Baldwin 41046af45170SJohn Baldwin csum_type = -1; 41056af45170SJohn Baldwin if (needs_tso(m0)) { 41066af45170SJohn Baldwin struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1); 41076af45170SJohn Baldwin 41086af45170SJohn Baldwin KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 41096af45170SJohn Baldwin m0->m_pkthdr.l4hlen > 0, 41106af45170SJohn Baldwin ("%s: mbuf %p needs TSO but missing header lengths", 41116af45170SJohn Baldwin __func__, m0)); 41126af45170SJohn Baldwin 41136af45170SJohn Baldwin ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE | 41146af45170SJohn Baldwin F_LSO_LAST_SLICE | V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) 41156af45170SJohn Baldwin | V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2); 41166af45170SJohn Baldwin if (m0->m_pkthdr.l2hlen == sizeof(struct ether_vlan_header)) 41176af45170SJohn Baldwin ctrl |= V_LSO_ETHHDR_LEN(1); 41186af45170SJohn Baldwin if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 41196af45170SJohn Baldwin ctrl |= F_LSO_IPV6; 41206af45170SJohn Baldwin 41216af45170SJohn Baldwin lso->lso_ctrl = htobe32(ctrl); 41226af45170SJohn Baldwin lso->ipid_ofst = htobe16(0); 41236af45170SJohn Baldwin lso->mss = htobe16(m0->m_pkthdr.tso_segsz); 41246af45170SJohn Baldwin lso->seqno_offset = htobe32(0); 41256af45170SJohn Baldwin lso->len = htobe32(pktlen); 41266af45170SJohn Baldwin 41276af45170SJohn Baldwin if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 41286af45170SJohn Baldwin csum_type = TX_CSUM_TCPIP6; 41296af45170SJohn Baldwin else 41306af45170SJohn Baldwin csum_type = TX_CSUM_TCPIP; 41316af45170SJohn Baldwin 41326af45170SJohn Baldwin cpl = (void *)(lso + 1); 41336af45170SJohn Baldwin 41346af45170SJohn Baldwin txq->tso_wrs++; 41356af45170SJohn Baldwin } else { 41366af45170SJohn Baldwin if (m0->m_pkthdr.csum_flags & CSUM_IP_TCP) 41376af45170SJohn Baldwin csum_type = TX_CSUM_TCPIP; 41386af45170SJohn Baldwin else if (m0->m_pkthdr.csum_flags & CSUM_IP_UDP) 41396af45170SJohn Baldwin csum_type = TX_CSUM_UDPIP; 41406af45170SJohn Baldwin else if (m0->m_pkthdr.csum_flags & CSUM_IP6_TCP) 41416af45170SJohn Baldwin csum_type = TX_CSUM_TCPIP6; 41426af45170SJohn Baldwin else if (m0->m_pkthdr.csum_flags & CSUM_IP6_UDP) 41436af45170SJohn Baldwin csum_type = TX_CSUM_UDPIP6; 41446af45170SJohn Baldwin #if defined(INET) 41456af45170SJohn Baldwin else if (m0->m_pkthdr.csum_flags & CSUM_IP) { 41466af45170SJohn Baldwin /* 41476af45170SJohn Baldwin * XXX: The firmware appears to stomp on the 41486af45170SJohn Baldwin * fragment/flags field of the IP header when 41496af45170SJohn Baldwin * using TX_CSUM_IP. Fall back to doing 41506af45170SJohn Baldwin * software checksums. 41516af45170SJohn Baldwin */ 41526af45170SJohn Baldwin u_short *sump; 41536af45170SJohn Baldwin struct mbuf *m; 41546af45170SJohn Baldwin int offset; 41556af45170SJohn Baldwin 41566af45170SJohn Baldwin m = m0; 41576af45170SJohn Baldwin offset = 0; 41586af45170SJohn Baldwin sump = m_advance(&m, &offset, m0->m_pkthdr.l2hlen + 41596af45170SJohn Baldwin offsetof(struct ip, ip_sum)); 41606af45170SJohn Baldwin *sump = in_cksum_skip(m0, m0->m_pkthdr.l2hlen + 41616af45170SJohn Baldwin m0->m_pkthdr.l3hlen, m0->m_pkthdr.l2hlen); 41626af45170SJohn Baldwin m0->m_pkthdr.csum_flags &= ~CSUM_IP; 41636af45170SJohn Baldwin } 41646af45170SJohn Baldwin #endif 41656af45170SJohn Baldwin 41666af45170SJohn Baldwin cpl = (void *)(wr + 1); 41676af45170SJohn Baldwin } 41686af45170SJohn Baldwin 41696af45170SJohn Baldwin /* Checksum offload */ 41706af45170SJohn Baldwin ctrl1 = 0; 41716af45170SJohn Baldwin if (needs_l3_csum(m0) == 0) 41726af45170SJohn Baldwin ctrl1 |= F_TXPKT_IPCSUM_DIS; 41736af45170SJohn Baldwin if (csum_type >= 0) { 41746af45170SJohn Baldwin KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0, 41756af45170SJohn Baldwin ("%s: mbuf %p needs checksum offload but missing header lengths", 41766af45170SJohn Baldwin __func__, m0)); 41776af45170SJohn Baldwin 4178472a6004SNavdeep Parhar if (chip_id(sc) <= CHELSIO_T5) { 41796af45170SJohn Baldwin ctrl1 |= V_TXPKT_ETHHDR_LEN(m0->m_pkthdr.l2hlen - 41806af45170SJohn Baldwin ETHER_HDR_LEN); 4181472a6004SNavdeep Parhar } else { 4182472a6004SNavdeep Parhar ctrl1 |= V_T6_TXPKT_ETHHDR_LEN(m0->m_pkthdr.l2hlen - 4183472a6004SNavdeep Parhar ETHER_HDR_LEN); 4184472a6004SNavdeep Parhar } 41856af45170SJohn Baldwin ctrl1 |= V_TXPKT_IPHDR_LEN(m0->m_pkthdr.l3hlen); 41866af45170SJohn Baldwin ctrl1 |= V_TXPKT_CSUM_TYPE(csum_type); 41876af45170SJohn Baldwin } else 41886af45170SJohn Baldwin ctrl1 |= F_TXPKT_L4CSUM_DIS; 41896af45170SJohn Baldwin if (m0->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | 41906af45170SJohn Baldwin CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO)) 41916af45170SJohn Baldwin txq->txcsum++; /* some hardware assistance provided */ 41926af45170SJohn Baldwin 41936af45170SJohn Baldwin /* VLAN tag insertion */ 41946af45170SJohn Baldwin if (needs_vlan_insertion(m0)) { 41956af45170SJohn Baldwin ctrl1 |= F_TXPKT_VLAN_VLD | 41966af45170SJohn Baldwin V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 41976af45170SJohn Baldwin txq->vlan_insertion++; 41986af45170SJohn Baldwin } 41996af45170SJohn Baldwin 42006af45170SJohn Baldwin /* CPL header */ 42016af45170SJohn Baldwin cpl->ctrl0 = txq->cpl_ctrl0; 42026af45170SJohn Baldwin cpl->pack = 0; 42036af45170SJohn Baldwin cpl->len = htobe16(pktlen); 42046af45170SJohn Baldwin cpl->ctrl1 = htobe64(ctrl1); 42056af45170SJohn Baldwin 42066af45170SJohn Baldwin /* SGL */ 42076af45170SJohn Baldwin dst = (void *)(cpl + 1); 42086af45170SJohn Baldwin 42096af45170SJohn Baldwin /* 42106af45170SJohn Baldwin * A packet using TSO will use up an entire descriptor for the 42116af45170SJohn Baldwin * firmware work request header, LSO CPL, and TX_PKT_XT CPL. 42126af45170SJohn Baldwin * If this descriptor is the last descriptor in the ring, wrap 42136af45170SJohn Baldwin * around to the front of the ring explicitly for the start of 42146af45170SJohn Baldwin * the sgl. 42156af45170SJohn Baldwin */ 42166af45170SJohn Baldwin if (dst == (void *)&eq->desc[eq->sidx]) { 42176af45170SJohn Baldwin dst = (void *)&eq->desc[0]; 42186af45170SJohn Baldwin write_gl_to_txd(txq, m0, &dst, 0); 42196af45170SJohn Baldwin } else 42206af45170SJohn Baldwin write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx); 42216af45170SJohn Baldwin txq->sgl_wrs++; 42226af45170SJohn Baldwin 42236af45170SJohn Baldwin txq->txpkt_wrs++; 42246af45170SJohn Baldwin 42256af45170SJohn Baldwin txsd = &txq->sdesc[eq->pidx]; 42266af45170SJohn Baldwin txsd->m = m0; 42276af45170SJohn Baldwin txsd->desc_used = ndesc; 42286af45170SJohn Baldwin 42296af45170SJohn Baldwin return (ndesc); 42306af45170SJohn Baldwin } 42316af45170SJohn Baldwin 42326af45170SJohn Baldwin /* 42337951040fSNavdeep Parhar * Write a txpkt WR for this packet to the hardware descriptors, update the 42347951040fSNavdeep Parhar * software descriptor, and advance the pidx. It is guaranteed that enough 42357951040fSNavdeep Parhar * descriptors are available. 423654e4ee71SNavdeep Parhar * 42377951040fSNavdeep Parhar * The return value is the # of hardware descriptors used. 423854e4ee71SNavdeep Parhar */ 42397951040fSNavdeep Parhar static u_int 42407951040fSNavdeep Parhar write_txpkt_wr(struct sge_txq *txq, struct fw_eth_tx_pkt_wr *wr, 42417951040fSNavdeep Parhar struct mbuf *m0, u_int available) 424254e4ee71SNavdeep Parhar { 424354e4ee71SNavdeep Parhar struct sge_eq *eq = &txq->eq; 42447951040fSNavdeep Parhar struct tx_sdesc *txsd; 424554e4ee71SNavdeep Parhar struct cpl_tx_pkt_core *cpl; 424654e4ee71SNavdeep Parhar uint32_t ctrl; /* used in many unrelated places */ 424754e4ee71SNavdeep Parhar uint64_t ctrl1; 42487951040fSNavdeep Parhar int len16, ndesc, pktlen, nsegs; 424954e4ee71SNavdeep Parhar caddr_t dst; 425054e4ee71SNavdeep Parhar 425154e4ee71SNavdeep Parhar TXQ_LOCK_ASSERT_OWNED(txq); 42527951040fSNavdeep Parhar M_ASSERTPKTHDR(m0); 42537951040fSNavdeep Parhar MPASS(available > 0 && available < eq->sidx); 425454e4ee71SNavdeep Parhar 42557951040fSNavdeep Parhar len16 = mbuf_len16(m0); 42567951040fSNavdeep Parhar nsegs = mbuf_nsegs(m0); 42577951040fSNavdeep Parhar pktlen = m0->m_pkthdr.len; 425854e4ee71SNavdeep Parhar ctrl = sizeof(struct cpl_tx_pkt_core); 42597951040fSNavdeep Parhar if (needs_tso(m0)) 42602a5f6b0eSNavdeep Parhar ctrl += sizeof(struct cpl_tx_pkt_lso_core); 42617951040fSNavdeep Parhar else if (pktlen <= imm_payload(2) && available >= 2) { 42627951040fSNavdeep Parhar /* Immediate data. Recalculate len16 and set nsegs to 0. */ 4263ecb79ca4SNavdeep Parhar ctrl += pktlen; 42647951040fSNavdeep Parhar len16 = howmany(sizeof(struct fw_eth_tx_pkt_wr) + 42657951040fSNavdeep Parhar sizeof(struct cpl_tx_pkt_core) + pktlen, 16); 42667951040fSNavdeep Parhar nsegs = 0; 426754e4ee71SNavdeep Parhar } 42687951040fSNavdeep Parhar ndesc = howmany(len16, EQ_ESIZE / 16); 42697951040fSNavdeep Parhar MPASS(ndesc <= available); 427054e4ee71SNavdeep Parhar 427154e4ee71SNavdeep Parhar /* Firmware work request header */ 42727951040fSNavdeep Parhar MPASS(wr == (void *)&eq->desc[eq->pidx]); 427354e4ee71SNavdeep Parhar wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_WR) | 4274733b9277SNavdeep Parhar V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl)); 42756b49a4ecSNavdeep Parhar 42767951040fSNavdeep Parhar ctrl = V_FW_WR_LEN16(len16); 427754e4ee71SNavdeep Parhar wr->equiq_to_len16 = htobe32(ctrl); 427854e4ee71SNavdeep Parhar wr->r3 = 0; 427954e4ee71SNavdeep Parhar 42807951040fSNavdeep Parhar if (needs_tso(m0)) { 42812a5f6b0eSNavdeep Parhar struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1); 42827951040fSNavdeep Parhar 42837951040fSNavdeep Parhar KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 && 42847951040fSNavdeep Parhar m0->m_pkthdr.l4hlen > 0, 42857951040fSNavdeep Parhar ("%s: mbuf %p needs TSO but missing header lengths", 42867951040fSNavdeep Parhar __func__, m0)); 428754e4ee71SNavdeep Parhar 428854e4ee71SNavdeep Parhar ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE | 42897951040fSNavdeep Parhar F_LSO_LAST_SLICE | V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) 42907951040fSNavdeep Parhar | V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2); 42917951040fSNavdeep Parhar if (m0->m_pkthdr.l2hlen == sizeof(struct ether_vlan_header)) 429254e4ee71SNavdeep Parhar ctrl |= V_LSO_ETHHDR_LEN(1); 42937951040fSNavdeep Parhar if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr)) 4294a1ea9a82SNavdeep Parhar ctrl |= F_LSO_IPV6; 429554e4ee71SNavdeep Parhar 429654e4ee71SNavdeep Parhar lso->lso_ctrl = htobe32(ctrl); 429754e4ee71SNavdeep Parhar lso->ipid_ofst = htobe16(0); 42987951040fSNavdeep Parhar lso->mss = htobe16(m0->m_pkthdr.tso_segsz); 429954e4ee71SNavdeep Parhar lso->seqno_offset = htobe32(0); 4300ecb79ca4SNavdeep Parhar lso->len = htobe32(pktlen); 430154e4ee71SNavdeep Parhar 430254e4ee71SNavdeep Parhar cpl = (void *)(lso + 1); 430354e4ee71SNavdeep Parhar 430454e4ee71SNavdeep Parhar txq->tso_wrs++; 430554e4ee71SNavdeep Parhar } else 430654e4ee71SNavdeep Parhar cpl = (void *)(wr + 1); 430754e4ee71SNavdeep Parhar 430854e4ee71SNavdeep Parhar /* Checksum offload */ 430954e4ee71SNavdeep Parhar ctrl1 = 0; 43107951040fSNavdeep Parhar if (needs_l3_csum(m0) == 0) 431154e4ee71SNavdeep Parhar ctrl1 |= F_TXPKT_IPCSUM_DIS; 43127951040fSNavdeep Parhar if (needs_l4_csum(m0) == 0) 431354e4ee71SNavdeep Parhar ctrl1 |= F_TXPKT_L4CSUM_DIS; 43147951040fSNavdeep Parhar if (m0->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | 4315b8531380SNavdeep Parhar CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO)) 431654e4ee71SNavdeep Parhar txq->txcsum++; /* some hardware assistance provided */ 431754e4ee71SNavdeep Parhar 431854e4ee71SNavdeep Parhar /* VLAN tag insertion */ 43197951040fSNavdeep Parhar if (needs_vlan_insertion(m0)) { 43207951040fSNavdeep Parhar ctrl1 |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag); 432154e4ee71SNavdeep Parhar txq->vlan_insertion++; 432254e4ee71SNavdeep Parhar } 432354e4ee71SNavdeep Parhar 432454e4ee71SNavdeep Parhar /* CPL header */ 43257951040fSNavdeep Parhar cpl->ctrl0 = txq->cpl_ctrl0; 432654e4ee71SNavdeep Parhar cpl->pack = 0; 4327ecb79ca4SNavdeep Parhar cpl->len = htobe16(pktlen); 432854e4ee71SNavdeep Parhar cpl->ctrl1 = htobe64(ctrl1); 432954e4ee71SNavdeep Parhar 433054e4ee71SNavdeep Parhar /* SGL */ 433154e4ee71SNavdeep Parhar dst = (void *)(cpl + 1); 43327951040fSNavdeep Parhar if (nsegs > 0) { 43337951040fSNavdeep Parhar 43347951040fSNavdeep Parhar write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx); 433554e4ee71SNavdeep Parhar txq->sgl_wrs++; 433654e4ee71SNavdeep Parhar } else { 43377951040fSNavdeep Parhar struct mbuf *m; 43387951040fSNavdeep Parhar 43397951040fSNavdeep Parhar for (m = m0; m != NULL; m = m->m_next) { 434054e4ee71SNavdeep Parhar copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len); 4341ecb79ca4SNavdeep Parhar #ifdef INVARIANTS 4342ecb79ca4SNavdeep Parhar pktlen -= m->m_len; 4343ecb79ca4SNavdeep Parhar #endif 434454e4ee71SNavdeep Parhar } 4345ecb79ca4SNavdeep Parhar #ifdef INVARIANTS 4346ecb79ca4SNavdeep Parhar KASSERT(pktlen == 0, ("%s: %d bytes left.", __func__, pktlen)); 4347ecb79ca4SNavdeep Parhar #endif 43487951040fSNavdeep Parhar txq->imm_wrs++; 434954e4ee71SNavdeep Parhar } 435054e4ee71SNavdeep Parhar 435154e4ee71SNavdeep Parhar txq->txpkt_wrs++; 435254e4ee71SNavdeep Parhar 4353f7dfe243SNavdeep Parhar txsd = &txq->sdesc[eq->pidx]; 43547951040fSNavdeep Parhar txsd->m = m0; 435554e4ee71SNavdeep Parhar txsd->desc_used = ndesc; 435654e4ee71SNavdeep Parhar 43577951040fSNavdeep Parhar return (ndesc); 435854e4ee71SNavdeep Parhar } 435954e4ee71SNavdeep Parhar 43607951040fSNavdeep Parhar static int 43617951040fSNavdeep Parhar try_txpkts(struct mbuf *m, struct mbuf *n, struct txpkts *txp, u_int available) 436254e4ee71SNavdeep Parhar { 43637951040fSNavdeep Parhar u_int needed, nsegs1, nsegs2, l1, l2; 43647951040fSNavdeep Parhar 43657951040fSNavdeep Parhar if (cannot_use_txpkts(m) || cannot_use_txpkts(n)) 43667951040fSNavdeep Parhar return (1); 43677951040fSNavdeep Parhar 43687951040fSNavdeep Parhar nsegs1 = mbuf_nsegs(m); 43697951040fSNavdeep Parhar nsegs2 = mbuf_nsegs(n); 43707951040fSNavdeep Parhar if (nsegs1 + nsegs2 == 2) { 43717951040fSNavdeep Parhar txp->wr_type = 1; 43727951040fSNavdeep Parhar l1 = l2 = txpkts1_len16(); 43737951040fSNavdeep Parhar } else { 43747951040fSNavdeep Parhar txp->wr_type = 0; 43757951040fSNavdeep Parhar l1 = txpkts0_len16(nsegs1); 43767951040fSNavdeep Parhar l2 = txpkts0_len16(nsegs2); 43777951040fSNavdeep Parhar } 43787951040fSNavdeep Parhar txp->len16 = howmany(sizeof(struct fw_eth_tx_pkts_wr), 16) + l1 + l2; 43797951040fSNavdeep Parhar needed = howmany(txp->len16, EQ_ESIZE / 16); 43807951040fSNavdeep Parhar if (needed > SGE_MAX_WR_NDESC || needed > available) 43817951040fSNavdeep Parhar return (1); 43827951040fSNavdeep Parhar 43837951040fSNavdeep Parhar txp->plen = m->m_pkthdr.len + n->m_pkthdr.len; 43847951040fSNavdeep Parhar if (txp->plen > 65535) 43857951040fSNavdeep Parhar return (1); 43867951040fSNavdeep Parhar 43877951040fSNavdeep Parhar txp->npkt = 2; 43887951040fSNavdeep Parhar set_mbuf_len16(m, l1); 43897951040fSNavdeep Parhar set_mbuf_len16(n, l2); 43907951040fSNavdeep Parhar 43917951040fSNavdeep Parhar return (0); 43927951040fSNavdeep Parhar } 43937951040fSNavdeep Parhar 43947951040fSNavdeep Parhar static int 43957951040fSNavdeep Parhar add_to_txpkts(struct mbuf *m, struct txpkts *txp, u_int available) 43967951040fSNavdeep Parhar { 43977951040fSNavdeep Parhar u_int plen, len16, needed, nsegs; 43987951040fSNavdeep Parhar 43997951040fSNavdeep Parhar MPASS(txp->wr_type == 0 || txp->wr_type == 1); 44007951040fSNavdeep Parhar 44017951040fSNavdeep Parhar nsegs = mbuf_nsegs(m); 44027951040fSNavdeep Parhar if (needs_tso(m) || (txp->wr_type == 1 && nsegs != 1)) 44037951040fSNavdeep Parhar return (1); 44047951040fSNavdeep Parhar 44057951040fSNavdeep Parhar plen = txp->plen + m->m_pkthdr.len; 44067951040fSNavdeep Parhar if (plen > 65535) 44077951040fSNavdeep Parhar return (1); 44087951040fSNavdeep Parhar 44097951040fSNavdeep Parhar if (txp->wr_type == 0) 44107951040fSNavdeep Parhar len16 = txpkts0_len16(nsegs); 44117951040fSNavdeep Parhar else 44127951040fSNavdeep Parhar len16 = txpkts1_len16(); 44137951040fSNavdeep Parhar needed = howmany(txp->len16 + len16, EQ_ESIZE / 16); 44147951040fSNavdeep Parhar if (needed > SGE_MAX_WR_NDESC || needed > available) 44157951040fSNavdeep Parhar return (1); 44167951040fSNavdeep Parhar 44177951040fSNavdeep Parhar txp->npkt++; 44187951040fSNavdeep Parhar txp->plen = plen; 44197951040fSNavdeep Parhar txp->len16 += len16; 44207951040fSNavdeep Parhar set_mbuf_len16(m, len16); 44217951040fSNavdeep Parhar 44227951040fSNavdeep Parhar return (0); 44237951040fSNavdeep Parhar } 44247951040fSNavdeep Parhar 44257951040fSNavdeep Parhar /* 44267951040fSNavdeep Parhar * Write a txpkts WR for the packets in txp to the hardware descriptors, update 44277951040fSNavdeep Parhar * the software descriptor, and advance the pidx. It is guaranteed that enough 44287951040fSNavdeep Parhar * descriptors are available. 44297951040fSNavdeep Parhar * 44307951040fSNavdeep Parhar * The return value is the # of hardware descriptors used. 44317951040fSNavdeep Parhar */ 44327951040fSNavdeep Parhar static u_int 44337951040fSNavdeep Parhar write_txpkts_wr(struct sge_txq *txq, struct fw_eth_tx_pkts_wr *wr, 44347951040fSNavdeep Parhar struct mbuf *m0, const struct txpkts *txp, u_int available) 44357951040fSNavdeep Parhar { 44367951040fSNavdeep Parhar struct sge_eq *eq = &txq->eq; 44377951040fSNavdeep Parhar struct tx_sdesc *txsd; 44387951040fSNavdeep Parhar struct cpl_tx_pkt_core *cpl; 44397951040fSNavdeep Parhar uint32_t ctrl; 44407951040fSNavdeep Parhar uint64_t ctrl1; 44417951040fSNavdeep Parhar int ndesc, checkwrap; 44427951040fSNavdeep Parhar struct mbuf *m; 44437951040fSNavdeep Parhar void *flitp; 44447951040fSNavdeep Parhar 44457951040fSNavdeep Parhar TXQ_LOCK_ASSERT_OWNED(txq); 44467951040fSNavdeep Parhar MPASS(txp->npkt > 0); 44477951040fSNavdeep Parhar MPASS(txp->plen < 65536); 44487951040fSNavdeep Parhar MPASS(m0 != NULL); 44497951040fSNavdeep Parhar MPASS(m0->m_nextpkt != NULL); 44507951040fSNavdeep Parhar MPASS(txp->len16 <= howmany(SGE_MAX_WR_LEN, 16)); 44517951040fSNavdeep Parhar MPASS(available > 0 && available < eq->sidx); 44527951040fSNavdeep Parhar 44537951040fSNavdeep Parhar ndesc = howmany(txp->len16, EQ_ESIZE / 16); 44547951040fSNavdeep Parhar MPASS(ndesc <= available); 44557951040fSNavdeep Parhar 44567951040fSNavdeep Parhar MPASS(wr == (void *)&eq->desc[eq->pidx]); 44577951040fSNavdeep Parhar wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR)); 44587951040fSNavdeep Parhar ctrl = V_FW_WR_LEN16(txp->len16); 44597951040fSNavdeep Parhar wr->equiq_to_len16 = htobe32(ctrl); 44607951040fSNavdeep Parhar wr->plen = htobe16(txp->plen); 44617951040fSNavdeep Parhar wr->npkt = txp->npkt; 44627951040fSNavdeep Parhar wr->r3 = 0; 44637951040fSNavdeep Parhar wr->type = txp->wr_type; 44647951040fSNavdeep Parhar flitp = wr + 1; 44657951040fSNavdeep Parhar 44667951040fSNavdeep Parhar /* 44677951040fSNavdeep Parhar * At this point we are 16B into a hardware descriptor. If checkwrap is 44687951040fSNavdeep Parhar * set then we know the WR is going to wrap around somewhere. We'll 44697951040fSNavdeep Parhar * check for that at appropriate points. 44707951040fSNavdeep Parhar */ 44717951040fSNavdeep Parhar checkwrap = eq->sidx - ndesc < eq->pidx; 44727951040fSNavdeep Parhar for (m = m0; m != NULL; m = m->m_nextpkt) { 44737951040fSNavdeep Parhar if (txp->wr_type == 0) { 447454e4ee71SNavdeep Parhar struct ulp_txpkt *ulpmc; 447554e4ee71SNavdeep Parhar struct ulptx_idata *ulpsc; 447654e4ee71SNavdeep Parhar 44777951040fSNavdeep Parhar /* ULP master command */ 44787951040fSNavdeep Parhar ulpmc = flitp; 44797951040fSNavdeep Parhar ulpmc->cmd_dest = htobe32(V_ULPTX_CMD(ULP_TX_PKT) | 44807951040fSNavdeep Parhar V_ULP_TXPKT_DEST(0) | V_ULP_TXPKT_FID(eq->iqid)); 44817951040fSNavdeep Parhar ulpmc->len = htobe32(mbuf_len16(m)); 448254e4ee71SNavdeep Parhar 44837951040fSNavdeep Parhar /* ULP subcommand */ 44847951040fSNavdeep Parhar ulpsc = (void *)(ulpmc + 1); 44857951040fSNavdeep Parhar ulpsc->cmd_more = htobe32(V_ULPTX_CMD(ULP_TX_SC_IMM) | 44867951040fSNavdeep Parhar F_ULP_TX_SC_MORE); 44877951040fSNavdeep Parhar ulpsc->len = htobe32(sizeof(struct cpl_tx_pkt_core)); 44887951040fSNavdeep Parhar 44897951040fSNavdeep Parhar cpl = (void *)(ulpsc + 1); 44907951040fSNavdeep Parhar if (checkwrap && 44917951040fSNavdeep Parhar (uintptr_t)cpl == (uintptr_t)&eq->desc[eq->sidx]) 44927951040fSNavdeep Parhar cpl = (void *)&eq->desc[0]; 44937951040fSNavdeep Parhar } else { 44947951040fSNavdeep Parhar cpl = flitp; 44957951040fSNavdeep Parhar } 449654e4ee71SNavdeep Parhar 449754e4ee71SNavdeep Parhar /* Checksum offload */ 44987951040fSNavdeep Parhar ctrl1 = 0; 44997951040fSNavdeep Parhar if (needs_l3_csum(m) == 0) 45007951040fSNavdeep Parhar ctrl1 |= F_TXPKT_IPCSUM_DIS; 45017951040fSNavdeep Parhar if (needs_l4_csum(m) == 0) 45027951040fSNavdeep Parhar ctrl1 |= F_TXPKT_L4CSUM_DIS; 4503b8531380SNavdeep Parhar if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | 4504b8531380SNavdeep Parhar CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO)) 450554e4ee71SNavdeep Parhar txq->txcsum++; /* some hardware assistance provided */ 450654e4ee71SNavdeep Parhar 450754e4ee71SNavdeep Parhar /* VLAN tag insertion */ 45087951040fSNavdeep Parhar if (needs_vlan_insertion(m)) { 45097951040fSNavdeep Parhar ctrl1 |= F_TXPKT_VLAN_VLD | 45107951040fSNavdeep Parhar V_TXPKT_VLAN(m->m_pkthdr.ether_vtag); 451154e4ee71SNavdeep Parhar txq->vlan_insertion++; 451254e4ee71SNavdeep Parhar } 451354e4ee71SNavdeep Parhar 45147951040fSNavdeep Parhar /* CPL header */ 45157951040fSNavdeep Parhar cpl->ctrl0 = txq->cpl_ctrl0; 451654e4ee71SNavdeep Parhar cpl->pack = 0; 451754e4ee71SNavdeep Parhar cpl->len = htobe16(m->m_pkthdr.len); 45187951040fSNavdeep Parhar cpl->ctrl1 = htobe64(ctrl1); 451954e4ee71SNavdeep Parhar 45207951040fSNavdeep Parhar flitp = cpl + 1; 45217951040fSNavdeep Parhar if (checkwrap && 45227951040fSNavdeep Parhar (uintptr_t)flitp == (uintptr_t)&eq->desc[eq->sidx]) 45237951040fSNavdeep Parhar flitp = (void *)&eq->desc[0]; 452454e4ee71SNavdeep Parhar 45257951040fSNavdeep Parhar write_gl_to_txd(txq, m, (caddr_t *)(&flitp), checkwrap); 452654e4ee71SNavdeep Parhar 45277951040fSNavdeep Parhar } 45287951040fSNavdeep Parhar 4529a59a1477SNavdeep Parhar if (txp->wr_type == 0) { 4530a59a1477SNavdeep Parhar txq->txpkts0_pkts += txp->npkt; 4531a59a1477SNavdeep Parhar txq->txpkts0_wrs++; 4532a59a1477SNavdeep Parhar } else { 4533a59a1477SNavdeep Parhar txq->txpkts1_pkts += txp->npkt; 4534a59a1477SNavdeep Parhar txq->txpkts1_wrs++; 4535a59a1477SNavdeep Parhar } 4536a59a1477SNavdeep Parhar 45377951040fSNavdeep Parhar txsd = &txq->sdesc[eq->pidx]; 45387951040fSNavdeep Parhar txsd->m = m0; 45397951040fSNavdeep Parhar txsd->desc_used = ndesc; 45407951040fSNavdeep Parhar 45417951040fSNavdeep Parhar return (ndesc); 454254e4ee71SNavdeep Parhar } 454354e4ee71SNavdeep Parhar 454454e4ee71SNavdeep Parhar /* 454554e4ee71SNavdeep Parhar * If the SGL ends on an address that is not 16 byte aligned, this function will 45467951040fSNavdeep Parhar * add a 0 filled flit at the end. 454754e4ee71SNavdeep Parhar */ 45487951040fSNavdeep Parhar static void 45497951040fSNavdeep Parhar write_gl_to_txd(struct sge_txq *txq, struct mbuf *m, caddr_t *to, int checkwrap) 455054e4ee71SNavdeep Parhar { 45517951040fSNavdeep Parhar struct sge_eq *eq = &txq->eq; 45527951040fSNavdeep Parhar struct sglist *gl = txq->gl; 45537951040fSNavdeep Parhar struct sglist_seg *seg; 45547951040fSNavdeep Parhar __be64 *flitp, *wrap; 455554e4ee71SNavdeep Parhar struct ulptx_sgl *usgl; 45567951040fSNavdeep Parhar int i, nflits, nsegs; 455754e4ee71SNavdeep Parhar 455854e4ee71SNavdeep Parhar KASSERT(((uintptr_t)(*to) & 0xf) == 0, 455954e4ee71SNavdeep Parhar ("%s: SGL must start at a 16 byte boundary: %p", __func__, *to)); 45607951040fSNavdeep Parhar MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]); 45617951040fSNavdeep Parhar MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]); 456254e4ee71SNavdeep Parhar 45637951040fSNavdeep Parhar get_pkt_gl(m, gl); 45647951040fSNavdeep Parhar nsegs = gl->sg_nseg; 45657951040fSNavdeep Parhar MPASS(nsegs > 0); 45667951040fSNavdeep Parhar 45677951040fSNavdeep Parhar nflits = (3 * (nsegs - 1)) / 2 + ((nsegs - 1) & 1) + 2; 456854e4ee71SNavdeep Parhar flitp = (__be64 *)(*to); 45697951040fSNavdeep Parhar wrap = (__be64 *)(&eq->desc[eq->sidx]); 45707951040fSNavdeep Parhar seg = &gl->sg_segs[0]; 457154e4ee71SNavdeep Parhar usgl = (void *)flitp; 457254e4ee71SNavdeep Parhar 457354e4ee71SNavdeep Parhar /* 457454e4ee71SNavdeep Parhar * We start at a 16 byte boundary somewhere inside the tx descriptor 457554e4ee71SNavdeep Parhar * ring, so we're at least 16 bytes away from the status page. There is 457654e4ee71SNavdeep Parhar * no chance of a wrap around in the middle of usgl (which is 16 bytes). 457754e4ee71SNavdeep Parhar */ 457854e4ee71SNavdeep Parhar 457954e4ee71SNavdeep Parhar usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 45807951040fSNavdeep Parhar V_ULPTX_NSGE(nsegs)); 45817951040fSNavdeep Parhar usgl->len0 = htobe32(seg->ss_len); 45827951040fSNavdeep Parhar usgl->addr0 = htobe64(seg->ss_paddr); 458354e4ee71SNavdeep Parhar seg++; 458454e4ee71SNavdeep Parhar 45857951040fSNavdeep Parhar if (checkwrap == 0 || (uintptr_t)(flitp + nflits) <= (uintptr_t)wrap) { 458654e4ee71SNavdeep Parhar 458754e4ee71SNavdeep Parhar /* Won't wrap around at all */ 458854e4ee71SNavdeep Parhar 45897951040fSNavdeep Parhar for (i = 0; i < nsegs - 1; i++, seg++) { 45907951040fSNavdeep Parhar usgl->sge[i / 2].len[i & 1] = htobe32(seg->ss_len); 45917951040fSNavdeep Parhar usgl->sge[i / 2].addr[i & 1] = htobe64(seg->ss_paddr); 459254e4ee71SNavdeep Parhar } 459354e4ee71SNavdeep Parhar if (i & 1) 459454e4ee71SNavdeep Parhar usgl->sge[i / 2].len[1] = htobe32(0); 45957951040fSNavdeep Parhar flitp += nflits; 459654e4ee71SNavdeep Parhar } else { 459754e4ee71SNavdeep Parhar 459854e4ee71SNavdeep Parhar /* Will wrap somewhere in the rest of the SGL */ 459954e4ee71SNavdeep Parhar 460054e4ee71SNavdeep Parhar /* 2 flits already written, write the rest flit by flit */ 460154e4ee71SNavdeep Parhar flitp = (void *)(usgl + 1); 46027951040fSNavdeep Parhar for (i = 0; i < nflits - 2; i++) { 46037951040fSNavdeep Parhar if (flitp == wrap) 460454e4ee71SNavdeep Parhar flitp = (void *)eq->desc; 46057951040fSNavdeep Parhar *flitp++ = get_flit(seg, nsegs - 1, i); 460654e4ee71SNavdeep Parhar } 460754e4ee71SNavdeep Parhar } 460854e4ee71SNavdeep Parhar 46097951040fSNavdeep Parhar if (nflits & 1) { 46107951040fSNavdeep Parhar MPASS(((uintptr_t)flitp) & 0xf); 46117951040fSNavdeep Parhar *flitp++ = 0; 46127951040fSNavdeep Parhar } 461354e4ee71SNavdeep Parhar 46147951040fSNavdeep Parhar MPASS((((uintptr_t)flitp) & 0xf) == 0); 46157951040fSNavdeep Parhar if (__predict_false(flitp == wrap)) 461654e4ee71SNavdeep Parhar *to = (void *)eq->desc; 461754e4ee71SNavdeep Parhar else 46187951040fSNavdeep Parhar *to = (void *)flitp; 461954e4ee71SNavdeep Parhar } 462054e4ee71SNavdeep Parhar 462154e4ee71SNavdeep Parhar static inline void 462254e4ee71SNavdeep Parhar copy_to_txd(struct sge_eq *eq, caddr_t from, caddr_t *to, int len) 462354e4ee71SNavdeep Parhar { 46247951040fSNavdeep Parhar 46257951040fSNavdeep Parhar MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]); 46267951040fSNavdeep Parhar MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]); 46277951040fSNavdeep Parhar 46287951040fSNavdeep Parhar if (__predict_true((uintptr_t)(*to) + len <= 46297951040fSNavdeep Parhar (uintptr_t)&eq->desc[eq->sidx])) { 463054e4ee71SNavdeep Parhar bcopy(from, *to, len); 463154e4ee71SNavdeep Parhar (*to) += len; 463254e4ee71SNavdeep Parhar } else { 46337951040fSNavdeep Parhar int portion = (uintptr_t)&eq->desc[eq->sidx] - (uintptr_t)(*to); 463454e4ee71SNavdeep Parhar 463554e4ee71SNavdeep Parhar bcopy(from, *to, portion); 463654e4ee71SNavdeep Parhar from += portion; 463754e4ee71SNavdeep Parhar portion = len - portion; /* remaining */ 463854e4ee71SNavdeep Parhar bcopy(from, (void *)eq->desc, portion); 463954e4ee71SNavdeep Parhar (*to) = (caddr_t)eq->desc + portion; 464054e4ee71SNavdeep Parhar } 464154e4ee71SNavdeep Parhar } 464254e4ee71SNavdeep Parhar 464354e4ee71SNavdeep Parhar static inline void 46447951040fSNavdeep Parhar ring_eq_db(struct adapter *sc, struct sge_eq *eq, u_int n) 464554e4ee71SNavdeep Parhar { 46467951040fSNavdeep Parhar u_int db; 46477951040fSNavdeep Parhar 46487951040fSNavdeep Parhar MPASS(n > 0); 4649d14b0ac1SNavdeep Parhar 4650d14b0ac1SNavdeep Parhar db = eq->doorbells; 46517951040fSNavdeep Parhar if (n > 1) 465277ad3c41SNavdeep Parhar clrbit(&db, DOORBELL_WCWR); 4653d14b0ac1SNavdeep Parhar wmb(); 4654d14b0ac1SNavdeep Parhar 4655d14b0ac1SNavdeep Parhar switch (ffs(db) - 1) { 4656d14b0ac1SNavdeep Parhar case DOORBELL_UDB: 46577951040fSNavdeep Parhar *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n)); 46587951040fSNavdeep Parhar break; 4659d14b0ac1SNavdeep Parhar 466077ad3c41SNavdeep Parhar case DOORBELL_WCWR: { 4661d14b0ac1SNavdeep Parhar volatile uint64_t *dst, *src; 4662d14b0ac1SNavdeep Parhar int i; 4663d14b0ac1SNavdeep Parhar 4664d14b0ac1SNavdeep Parhar /* 4665d14b0ac1SNavdeep Parhar * Queues whose 128B doorbell segment fits in the page do not 4666d14b0ac1SNavdeep Parhar * use relative qid (udb_qid is always 0). Only queues with 466777ad3c41SNavdeep Parhar * doorbell segments can do WCWR. 4668d14b0ac1SNavdeep Parhar */ 46697951040fSNavdeep Parhar KASSERT(eq->udb_qid == 0 && n == 1, 4670d14b0ac1SNavdeep Parhar ("%s: inappropriate doorbell (0x%x, %d, %d) for eq %p", 46717951040fSNavdeep Parhar __func__, eq->doorbells, n, eq->dbidx, eq)); 4672d14b0ac1SNavdeep Parhar 4673d14b0ac1SNavdeep Parhar dst = (volatile void *)((uintptr_t)eq->udb + UDBS_WR_OFFSET - 4674d14b0ac1SNavdeep Parhar UDBS_DB_OFFSET); 46757951040fSNavdeep Parhar i = eq->dbidx; 4676d14b0ac1SNavdeep Parhar src = (void *)&eq->desc[i]; 4677d14b0ac1SNavdeep Parhar while (src != (void *)&eq->desc[i + 1]) 4678d14b0ac1SNavdeep Parhar *dst++ = *src++; 4679d14b0ac1SNavdeep Parhar wmb(); 46807951040fSNavdeep Parhar break; 4681d14b0ac1SNavdeep Parhar } 4682d14b0ac1SNavdeep Parhar 4683d14b0ac1SNavdeep Parhar case DOORBELL_UDBWC: 46847951040fSNavdeep Parhar *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n)); 4685d14b0ac1SNavdeep Parhar wmb(); 46867951040fSNavdeep Parhar break; 4687d14b0ac1SNavdeep Parhar 4688d14b0ac1SNavdeep Parhar case DOORBELL_KDB: 4689315048f2SJohn Baldwin t4_write_reg(sc, sc->sge_kdoorbell_reg, 46907951040fSNavdeep Parhar V_QID(eq->cntxt_id) | V_PIDX(n)); 46917951040fSNavdeep Parhar break; 469254e4ee71SNavdeep Parhar } 469354e4ee71SNavdeep Parhar 46947951040fSNavdeep Parhar IDXINCR(eq->dbidx, n, eq->sidx); 46957951040fSNavdeep Parhar } 46967951040fSNavdeep Parhar 46977951040fSNavdeep Parhar static inline u_int 46987951040fSNavdeep Parhar reclaimable_tx_desc(struct sge_eq *eq) 469954e4ee71SNavdeep Parhar { 47007951040fSNavdeep Parhar uint16_t hw_cidx; 470154e4ee71SNavdeep Parhar 47027951040fSNavdeep Parhar hw_cidx = read_hw_cidx(eq); 47037951040fSNavdeep Parhar return (IDXDIFF(hw_cidx, eq->cidx, eq->sidx)); 47047951040fSNavdeep Parhar } 470554e4ee71SNavdeep Parhar 47067951040fSNavdeep Parhar static inline u_int 47077951040fSNavdeep Parhar total_available_tx_desc(struct sge_eq *eq) 47087951040fSNavdeep Parhar { 47097951040fSNavdeep Parhar uint16_t hw_cidx, pidx; 47107951040fSNavdeep Parhar 47117951040fSNavdeep Parhar hw_cidx = read_hw_cidx(eq); 47127951040fSNavdeep Parhar pidx = eq->pidx; 47137951040fSNavdeep Parhar 47147951040fSNavdeep Parhar if (pidx == hw_cidx) 47157951040fSNavdeep Parhar return (eq->sidx - 1); 471654e4ee71SNavdeep Parhar else 47177951040fSNavdeep Parhar return (IDXDIFF(hw_cidx, pidx, eq->sidx) - 1); 47187951040fSNavdeep Parhar } 47197951040fSNavdeep Parhar 47207951040fSNavdeep Parhar static inline uint16_t 47217951040fSNavdeep Parhar read_hw_cidx(struct sge_eq *eq) 47227951040fSNavdeep Parhar { 47237951040fSNavdeep Parhar struct sge_qstat *spg = (void *)&eq->desc[eq->sidx]; 47247951040fSNavdeep Parhar uint16_t cidx = spg->cidx; /* stable snapshot */ 47257951040fSNavdeep Parhar 47267951040fSNavdeep Parhar return (be16toh(cidx)); 4727e874ff7aSNavdeep Parhar } 472854e4ee71SNavdeep Parhar 4729e874ff7aSNavdeep Parhar /* 47307951040fSNavdeep Parhar * Reclaim 'n' descriptors approximately. 4731e874ff7aSNavdeep Parhar */ 47327951040fSNavdeep Parhar static u_int 47337951040fSNavdeep Parhar reclaim_tx_descs(struct sge_txq *txq, u_int n) 4734e874ff7aSNavdeep Parhar { 4735e874ff7aSNavdeep Parhar struct tx_sdesc *txsd; 4736f7dfe243SNavdeep Parhar struct sge_eq *eq = &txq->eq; 47377951040fSNavdeep Parhar u_int can_reclaim, reclaimed; 473854e4ee71SNavdeep Parhar 4739733b9277SNavdeep Parhar TXQ_LOCK_ASSERT_OWNED(txq); 47407951040fSNavdeep Parhar MPASS(n > 0); 4741e874ff7aSNavdeep Parhar 47427951040fSNavdeep Parhar reclaimed = 0; 47437951040fSNavdeep Parhar can_reclaim = reclaimable_tx_desc(eq); 47447951040fSNavdeep Parhar while (can_reclaim && reclaimed < n) { 474554e4ee71SNavdeep Parhar int ndesc; 47467951040fSNavdeep Parhar struct mbuf *m, *nextpkt; 474754e4ee71SNavdeep Parhar 4748f7dfe243SNavdeep Parhar txsd = &txq->sdesc[eq->cidx]; 474954e4ee71SNavdeep Parhar ndesc = txsd->desc_used; 475054e4ee71SNavdeep Parhar 475154e4ee71SNavdeep Parhar /* Firmware doesn't return "partial" credits. */ 475254e4ee71SNavdeep Parhar KASSERT(can_reclaim >= ndesc, 475354e4ee71SNavdeep Parhar ("%s: unexpected number of credits: %d, %d", 475454e4ee71SNavdeep Parhar __func__, can_reclaim, ndesc)); 475554e4ee71SNavdeep Parhar 47567951040fSNavdeep Parhar for (m = txsd->m; m != NULL; m = nextpkt) { 47577951040fSNavdeep Parhar nextpkt = m->m_nextpkt; 47587951040fSNavdeep Parhar m->m_nextpkt = NULL; 47597951040fSNavdeep Parhar m_freem(m); 47607951040fSNavdeep Parhar } 476154e4ee71SNavdeep Parhar reclaimed += ndesc; 476254e4ee71SNavdeep Parhar can_reclaim -= ndesc; 47637951040fSNavdeep Parhar IDXINCR(eq->cidx, ndesc, eq->sidx); 476454e4ee71SNavdeep Parhar } 476554e4ee71SNavdeep Parhar 476654e4ee71SNavdeep Parhar return (reclaimed); 476754e4ee71SNavdeep Parhar } 476854e4ee71SNavdeep Parhar 476954e4ee71SNavdeep Parhar static void 47707951040fSNavdeep Parhar tx_reclaim(void *arg, int n) 477154e4ee71SNavdeep Parhar { 47727951040fSNavdeep Parhar struct sge_txq *txq = arg; 47737951040fSNavdeep Parhar struct sge_eq *eq = &txq->eq; 477454e4ee71SNavdeep Parhar 47757951040fSNavdeep Parhar do { 47767951040fSNavdeep Parhar if (TXQ_TRYLOCK(txq) == 0) 47777951040fSNavdeep Parhar break; 47787951040fSNavdeep Parhar n = reclaim_tx_descs(txq, 32); 47797951040fSNavdeep Parhar if (eq->cidx == eq->pidx) 47807951040fSNavdeep Parhar eq->equeqidx = eq->pidx; 47817951040fSNavdeep Parhar TXQ_UNLOCK(txq); 47827951040fSNavdeep Parhar } while (n > 0); 478354e4ee71SNavdeep Parhar } 478454e4ee71SNavdeep Parhar 478554e4ee71SNavdeep Parhar static __be64 47867951040fSNavdeep Parhar get_flit(struct sglist_seg *segs, int nsegs, int idx) 478754e4ee71SNavdeep Parhar { 478854e4ee71SNavdeep Parhar int i = (idx / 3) * 2; 478954e4ee71SNavdeep Parhar 479054e4ee71SNavdeep Parhar switch (idx % 3) { 479154e4ee71SNavdeep Parhar case 0: { 4792f078ecf6SWojciech Macek uint64_t rc; 479354e4ee71SNavdeep Parhar 4794f078ecf6SWojciech Macek rc = (uint64_t)segs[i].ss_len << 32; 479554e4ee71SNavdeep Parhar if (i + 1 < nsegs) 4796f078ecf6SWojciech Macek rc |= (uint64_t)(segs[i + 1].ss_len); 479754e4ee71SNavdeep Parhar 4798f078ecf6SWojciech Macek return (htobe64(rc)); 479954e4ee71SNavdeep Parhar } 480054e4ee71SNavdeep Parhar case 1: 48017951040fSNavdeep Parhar return (htobe64(segs[i].ss_paddr)); 480254e4ee71SNavdeep Parhar case 2: 48037951040fSNavdeep Parhar return (htobe64(segs[i + 1].ss_paddr)); 480454e4ee71SNavdeep Parhar } 480554e4ee71SNavdeep Parhar 480654e4ee71SNavdeep Parhar return (0); 480754e4ee71SNavdeep Parhar } 480854e4ee71SNavdeep Parhar 480954e4ee71SNavdeep Parhar static void 481038035ed6SNavdeep Parhar find_best_refill_source(struct adapter *sc, struct sge_fl *fl, int maxp) 481154e4ee71SNavdeep Parhar { 481238035ed6SNavdeep Parhar int8_t zidx, hwidx, idx; 481338035ed6SNavdeep Parhar uint16_t region1, region3; 481438035ed6SNavdeep Parhar int spare, spare_needed, n; 481538035ed6SNavdeep Parhar struct sw_zone_info *swz; 481638035ed6SNavdeep Parhar struct hw_buf_info *hwb, *hwb_list = &sc->sge.hw_buf_info[0]; 481754e4ee71SNavdeep Parhar 481838035ed6SNavdeep Parhar /* 481938035ed6SNavdeep Parhar * Buffer Packing: Look for PAGE_SIZE or larger zone which has a bufsize 482038035ed6SNavdeep Parhar * large enough for the max payload and cluster metadata. Otherwise 482138035ed6SNavdeep Parhar * settle for the largest bufsize that leaves enough room in the cluster 482238035ed6SNavdeep Parhar * for metadata. 482338035ed6SNavdeep Parhar * 482438035ed6SNavdeep Parhar * Without buffer packing: Look for the smallest zone which has a 482538035ed6SNavdeep Parhar * bufsize large enough for the max payload. Settle for the largest 482638035ed6SNavdeep Parhar * bufsize available if there's nothing big enough for max payload. 482738035ed6SNavdeep Parhar */ 482838035ed6SNavdeep Parhar spare_needed = fl->flags & FL_BUF_PACKING ? CL_METADATA_SIZE : 0; 482938035ed6SNavdeep Parhar swz = &sc->sge.sw_zone_info[0]; 483038035ed6SNavdeep Parhar hwidx = -1; 483138035ed6SNavdeep Parhar for (zidx = 0; zidx < SW_ZONE_SIZES; zidx++, swz++) { 483238035ed6SNavdeep Parhar if (swz->size > largest_rx_cluster) { 483338035ed6SNavdeep Parhar if (__predict_true(hwidx != -1)) 483438035ed6SNavdeep Parhar break; 483538035ed6SNavdeep Parhar 483638035ed6SNavdeep Parhar /* 483738035ed6SNavdeep Parhar * This is a misconfiguration. largest_rx_cluster is 483838035ed6SNavdeep Parhar * preventing us from finding a refill source. See 483938035ed6SNavdeep Parhar * dev.t5nex.<n>.buffer_sizes to figure out why. 484038035ed6SNavdeep Parhar */ 484138035ed6SNavdeep Parhar device_printf(sc->dev, "largest_rx_cluster=%u leaves no" 484238035ed6SNavdeep Parhar " refill source for fl %p (dma %u). Ignored.\n", 484338035ed6SNavdeep Parhar largest_rx_cluster, fl, maxp); 484438035ed6SNavdeep Parhar } 484538035ed6SNavdeep Parhar for (idx = swz->head_hwidx; idx != -1; idx = hwb->next) { 484638035ed6SNavdeep Parhar hwb = &hwb_list[idx]; 484738035ed6SNavdeep Parhar spare = swz->size - hwb->size; 484838035ed6SNavdeep Parhar if (spare < spare_needed) 484938035ed6SNavdeep Parhar continue; 485038035ed6SNavdeep Parhar 485138035ed6SNavdeep Parhar hwidx = idx; /* best option so far */ 485238035ed6SNavdeep Parhar if (hwb->size >= maxp) { 485338035ed6SNavdeep Parhar 485438035ed6SNavdeep Parhar if ((fl->flags & FL_BUF_PACKING) == 0) 485538035ed6SNavdeep Parhar goto done; /* stop looking (not packing) */ 485638035ed6SNavdeep Parhar 485738035ed6SNavdeep Parhar if (swz->size >= safest_rx_cluster) 485838035ed6SNavdeep Parhar goto done; /* stop looking (packing) */ 485938035ed6SNavdeep Parhar } 486038035ed6SNavdeep Parhar break; /* keep looking, next zone */ 486138035ed6SNavdeep Parhar } 486238035ed6SNavdeep Parhar } 486338035ed6SNavdeep Parhar done: 486438035ed6SNavdeep Parhar /* A usable hwidx has been located. */ 486538035ed6SNavdeep Parhar MPASS(hwidx != -1); 486638035ed6SNavdeep Parhar hwb = &hwb_list[hwidx]; 486738035ed6SNavdeep Parhar zidx = hwb->zidx; 486838035ed6SNavdeep Parhar swz = &sc->sge.sw_zone_info[zidx]; 486938035ed6SNavdeep Parhar region1 = 0; 487038035ed6SNavdeep Parhar region3 = swz->size - hwb->size; 487138035ed6SNavdeep Parhar 487238035ed6SNavdeep Parhar /* 487338035ed6SNavdeep Parhar * Stay within this zone and see if there is a better match when mbuf 487438035ed6SNavdeep Parhar * inlining is allowed. Remember that the hwidx's are sorted in 487538035ed6SNavdeep Parhar * decreasing order of size (so in increasing order of spare area). 487638035ed6SNavdeep Parhar */ 487738035ed6SNavdeep Parhar for (idx = hwidx; idx != -1; idx = hwb->next) { 487838035ed6SNavdeep Parhar hwb = &hwb_list[idx]; 487938035ed6SNavdeep Parhar spare = swz->size - hwb->size; 488038035ed6SNavdeep Parhar 488138035ed6SNavdeep Parhar if (allow_mbufs_in_cluster == 0 || hwb->size < maxp) 488238035ed6SNavdeep Parhar break; 4883e3207e19SNavdeep Parhar 4884e3207e19SNavdeep Parhar /* 4885e3207e19SNavdeep Parhar * Do not inline mbufs if doing so would violate the pad/pack 4886e3207e19SNavdeep Parhar * boundary alignment requirement. 4887e3207e19SNavdeep Parhar */ 488890e7434aSNavdeep Parhar if (fl_pad && (MSIZE % sc->params.sge.pad_boundary) != 0) 4889e3207e19SNavdeep Parhar continue; 4890e3207e19SNavdeep Parhar if (fl->flags & FL_BUF_PACKING && 489190e7434aSNavdeep Parhar (MSIZE % sc->params.sge.pack_boundary) != 0) 4892e3207e19SNavdeep Parhar continue; 4893e3207e19SNavdeep Parhar 489438035ed6SNavdeep Parhar if (spare < CL_METADATA_SIZE + MSIZE) 489538035ed6SNavdeep Parhar continue; 489638035ed6SNavdeep Parhar n = (spare - CL_METADATA_SIZE) / MSIZE; 489738035ed6SNavdeep Parhar if (n > howmany(hwb->size, maxp)) 489838035ed6SNavdeep Parhar break; 489938035ed6SNavdeep Parhar 490038035ed6SNavdeep Parhar hwidx = idx; 49011458bff9SNavdeep Parhar if (fl->flags & FL_BUF_PACKING) { 490238035ed6SNavdeep Parhar region1 = n * MSIZE; 490338035ed6SNavdeep Parhar region3 = spare - region1; 490438035ed6SNavdeep Parhar } else { 490538035ed6SNavdeep Parhar region1 = MSIZE; 490638035ed6SNavdeep Parhar region3 = spare - region1; 490738035ed6SNavdeep Parhar break; 490838035ed6SNavdeep Parhar } 490938035ed6SNavdeep Parhar } 491038035ed6SNavdeep Parhar 491138035ed6SNavdeep Parhar KASSERT(zidx >= 0 && zidx < SW_ZONE_SIZES, 491238035ed6SNavdeep Parhar ("%s: bad zone %d for fl %p, maxp %d", __func__, zidx, fl, maxp)); 491338035ed6SNavdeep Parhar KASSERT(hwidx >= 0 && hwidx <= SGE_FLBUF_SIZES, 491438035ed6SNavdeep Parhar ("%s: bad hwidx %d for fl %p, maxp %d", __func__, hwidx, fl, maxp)); 491538035ed6SNavdeep Parhar KASSERT(region1 + sc->sge.hw_buf_info[hwidx].size + region3 == 491638035ed6SNavdeep Parhar sc->sge.sw_zone_info[zidx].size, 491738035ed6SNavdeep Parhar ("%s: bad buffer layout for fl %p, maxp %d. " 491838035ed6SNavdeep Parhar "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp, 491938035ed6SNavdeep Parhar sc->sge.sw_zone_info[zidx].size, region1, 492038035ed6SNavdeep Parhar sc->sge.hw_buf_info[hwidx].size, region3)); 492138035ed6SNavdeep Parhar if (fl->flags & FL_BUF_PACKING || region1 > 0) { 492238035ed6SNavdeep Parhar KASSERT(region3 >= CL_METADATA_SIZE, 492338035ed6SNavdeep Parhar ("%s: no room for metadata. fl %p, maxp %d; " 492438035ed6SNavdeep Parhar "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp, 492538035ed6SNavdeep Parhar sc->sge.sw_zone_info[zidx].size, region1, 492638035ed6SNavdeep Parhar sc->sge.hw_buf_info[hwidx].size, region3)); 492738035ed6SNavdeep Parhar KASSERT(region1 % MSIZE == 0, 492838035ed6SNavdeep Parhar ("%s: bad mbuf region for fl %p, maxp %d. " 492938035ed6SNavdeep Parhar "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp, 493038035ed6SNavdeep Parhar sc->sge.sw_zone_info[zidx].size, region1, 493138035ed6SNavdeep Parhar sc->sge.hw_buf_info[hwidx].size, region3)); 493238035ed6SNavdeep Parhar } 493338035ed6SNavdeep Parhar 493438035ed6SNavdeep Parhar fl->cll_def.zidx = zidx; 493538035ed6SNavdeep Parhar fl->cll_def.hwidx = hwidx; 493638035ed6SNavdeep Parhar fl->cll_def.region1 = region1; 493738035ed6SNavdeep Parhar fl->cll_def.region3 = region3; 493838035ed6SNavdeep Parhar } 493938035ed6SNavdeep Parhar 494038035ed6SNavdeep Parhar static void 494138035ed6SNavdeep Parhar find_safe_refill_source(struct adapter *sc, struct sge_fl *fl) 494238035ed6SNavdeep Parhar { 494338035ed6SNavdeep Parhar struct sge *s = &sc->sge; 494438035ed6SNavdeep Parhar struct hw_buf_info *hwb; 494538035ed6SNavdeep Parhar struct sw_zone_info *swz; 494638035ed6SNavdeep Parhar int spare; 494738035ed6SNavdeep Parhar int8_t hwidx; 494838035ed6SNavdeep Parhar 494938035ed6SNavdeep Parhar if (fl->flags & FL_BUF_PACKING) 495038035ed6SNavdeep Parhar hwidx = s->safe_hwidx2; /* with room for metadata */ 495138035ed6SNavdeep Parhar else if (allow_mbufs_in_cluster && s->safe_hwidx2 != -1) { 495238035ed6SNavdeep Parhar hwidx = s->safe_hwidx2; 495338035ed6SNavdeep Parhar hwb = &s->hw_buf_info[hwidx]; 495438035ed6SNavdeep Parhar swz = &s->sw_zone_info[hwb->zidx]; 495538035ed6SNavdeep Parhar spare = swz->size - hwb->size; 495638035ed6SNavdeep Parhar 495738035ed6SNavdeep Parhar /* no good if there isn't room for an mbuf as well */ 495838035ed6SNavdeep Parhar if (spare < CL_METADATA_SIZE + MSIZE) 495938035ed6SNavdeep Parhar hwidx = s->safe_hwidx1; 496038035ed6SNavdeep Parhar } else 496138035ed6SNavdeep Parhar hwidx = s->safe_hwidx1; 496238035ed6SNavdeep Parhar 496338035ed6SNavdeep Parhar if (hwidx == -1) { 496438035ed6SNavdeep Parhar /* No fallback source */ 496538035ed6SNavdeep Parhar fl->cll_alt.hwidx = -1; 496638035ed6SNavdeep Parhar fl->cll_alt.zidx = -1; 496738035ed6SNavdeep Parhar 49681458bff9SNavdeep Parhar return; 496954e4ee71SNavdeep Parhar } 497054e4ee71SNavdeep Parhar 497138035ed6SNavdeep Parhar hwb = &s->hw_buf_info[hwidx]; 497238035ed6SNavdeep Parhar swz = &s->sw_zone_info[hwb->zidx]; 497338035ed6SNavdeep Parhar spare = swz->size - hwb->size; 497438035ed6SNavdeep Parhar fl->cll_alt.hwidx = hwidx; 497538035ed6SNavdeep Parhar fl->cll_alt.zidx = hwb->zidx; 4976e3207e19SNavdeep Parhar if (allow_mbufs_in_cluster && 497790e7434aSNavdeep Parhar (fl_pad == 0 || (MSIZE % sc->params.sge.pad_boundary) == 0)) 497838035ed6SNavdeep Parhar fl->cll_alt.region1 = ((spare - CL_METADATA_SIZE) / MSIZE) * MSIZE; 49791458bff9SNavdeep Parhar else 498038035ed6SNavdeep Parhar fl->cll_alt.region1 = 0; 498138035ed6SNavdeep Parhar fl->cll_alt.region3 = spare - fl->cll_alt.region1; 498254e4ee71SNavdeep Parhar } 4983ecb79ca4SNavdeep Parhar 4984733b9277SNavdeep Parhar static void 4985733b9277SNavdeep Parhar add_fl_to_sfl(struct adapter *sc, struct sge_fl *fl) 4986ecb79ca4SNavdeep Parhar { 4987733b9277SNavdeep Parhar mtx_lock(&sc->sfl_lock); 4988733b9277SNavdeep Parhar FL_LOCK(fl); 4989733b9277SNavdeep Parhar if ((fl->flags & FL_DOOMED) == 0) { 4990733b9277SNavdeep Parhar fl->flags |= FL_STARVING; 4991733b9277SNavdeep Parhar TAILQ_INSERT_TAIL(&sc->sfl, fl, link); 4992733b9277SNavdeep Parhar callout_reset(&sc->sfl_callout, hz / 5, refill_sfl, sc); 4993733b9277SNavdeep Parhar } 4994733b9277SNavdeep Parhar FL_UNLOCK(fl); 4995733b9277SNavdeep Parhar mtx_unlock(&sc->sfl_lock); 4996733b9277SNavdeep Parhar } 4997ecb79ca4SNavdeep Parhar 49987951040fSNavdeep Parhar static void 49997951040fSNavdeep Parhar handle_wrq_egr_update(struct adapter *sc, struct sge_eq *eq) 50007951040fSNavdeep Parhar { 50017951040fSNavdeep Parhar struct sge_wrq *wrq = (void *)eq; 50027951040fSNavdeep Parhar 50037951040fSNavdeep Parhar atomic_readandclear_int(&eq->equiq); 50047951040fSNavdeep Parhar taskqueue_enqueue(sc->tq[eq->tx_chan], &wrq->wrq_tx_task); 50057951040fSNavdeep Parhar } 50067951040fSNavdeep Parhar 50077951040fSNavdeep Parhar static void 50087951040fSNavdeep Parhar handle_eth_egr_update(struct adapter *sc, struct sge_eq *eq) 50097951040fSNavdeep Parhar { 50107951040fSNavdeep Parhar struct sge_txq *txq = (void *)eq; 50117951040fSNavdeep Parhar 50127951040fSNavdeep Parhar MPASS((eq->flags & EQ_TYPEMASK) == EQ_ETH); 50137951040fSNavdeep Parhar 50147951040fSNavdeep Parhar atomic_readandclear_int(&eq->equiq); 50157951040fSNavdeep Parhar mp_ring_check_drainage(txq->r, 0); 50167951040fSNavdeep Parhar taskqueue_enqueue(sc->tq[eq->tx_chan], &txq->tx_reclaim_task); 50177951040fSNavdeep Parhar } 50187951040fSNavdeep Parhar 5019733b9277SNavdeep Parhar static int 5020733b9277SNavdeep Parhar handle_sge_egr_update(struct sge_iq *iq, const struct rss_header *rss, 5021733b9277SNavdeep Parhar struct mbuf *m) 5022733b9277SNavdeep Parhar { 5023733b9277SNavdeep Parhar const struct cpl_sge_egr_update *cpl = (const void *)(rss + 1); 5024733b9277SNavdeep Parhar unsigned int qid = G_EGR_QID(ntohl(cpl->opcode_qid)); 5025733b9277SNavdeep Parhar struct adapter *sc = iq->adapter; 5026733b9277SNavdeep Parhar struct sge *s = &sc->sge; 5027733b9277SNavdeep Parhar struct sge_eq *eq; 50287951040fSNavdeep Parhar static void (*h[])(struct adapter *, struct sge_eq *) = {NULL, 50297951040fSNavdeep Parhar &handle_wrq_egr_update, &handle_eth_egr_update, 50307951040fSNavdeep Parhar &handle_wrq_egr_update}; 5031733b9277SNavdeep Parhar 5032733b9277SNavdeep Parhar KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 5033733b9277SNavdeep Parhar rss->opcode)); 5034733b9277SNavdeep Parhar 5035ec55567cSJohn Baldwin eq = s->eqmap[qid - s->eq_start - s->eq_base]; 50367951040fSNavdeep Parhar (*h[eq->flags & EQ_TYPEMASK])(sc, eq); 5037ecb79ca4SNavdeep Parhar 5038ecb79ca4SNavdeep Parhar return (0); 5039ecb79ca4SNavdeep Parhar } 5040f7dfe243SNavdeep Parhar 50410abd31e2SNavdeep Parhar /* handle_fw_msg works for both fw4_msg and fw6_msg because this is valid */ 50420abd31e2SNavdeep Parhar CTASSERT(offsetof(struct cpl_fw4_msg, data) == \ 50430abd31e2SNavdeep Parhar offsetof(struct cpl_fw6_msg, data)); 50440abd31e2SNavdeep Parhar 5045733b9277SNavdeep Parhar static int 50461b4cc91fSNavdeep Parhar handle_fw_msg(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 504756599263SNavdeep Parhar { 50481b4cc91fSNavdeep Parhar struct adapter *sc = iq->adapter; 504956599263SNavdeep Parhar const struct cpl_fw6_msg *cpl = (const void *)(rss + 1); 505056599263SNavdeep Parhar 5051733b9277SNavdeep Parhar KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 5052733b9277SNavdeep Parhar rss->opcode)); 5053733b9277SNavdeep Parhar 50540abd31e2SNavdeep Parhar if (cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL) { 50550abd31e2SNavdeep Parhar const struct rss_header *rss2; 50560abd31e2SNavdeep Parhar 50570abd31e2SNavdeep Parhar rss2 = (const struct rss_header *)&cpl->data[0]; 5058671bf2b8SNavdeep Parhar return (t4_cpl_handler[rss2->opcode](iq, rss2, m)); 50590abd31e2SNavdeep Parhar } 50600abd31e2SNavdeep Parhar 5061671bf2b8SNavdeep Parhar return (t4_fw_msg_handler[cpl->type](sc, &cpl->data[0])); 5062f7dfe243SNavdeep Parhar } 5063af49c942SNavdeep Parhar 5064069af0ebSJohn Baldwin /** 5065069af0ebSJohn Baldwin * t4_handle_wrerr_rpl - process a FW work request error message 5066069af0ebSJohn Baldwin * @adap: the adapter 5067069af0ebSJohn Baldwin * @rpl: start of the FW message 5068069af0ebSJohn Baldwin */ 5069069af0ebSJohn Baldwin static int 5070069af0ebSJohn Baldwin t4_handle_wrerr_rpl(struct adapter *adap, const __be64 *rpl) 5071069af0ebSJohn Baldwin { 5072069af0ebSJohn Baldwin u8 opcode = *(const u8 *)rpl; 5073069af0ebSJohn Baldwin const struct fw_error_cmd *e = (const void *)rpl; 5074069af0ebSJohn Baldwin unsigned int i; 5075069af0ebSJohn Baldwin 5076069af0ebSJohn Baldwin if (opcode != FW_ERROR_CMD) { 5077069af0ebSJohn Baldwin log(LOG_ERR, 5078069af0ebSJohn Baldwin "%s: Received WRERR_RPL message with opcode %#x\n", 5079069af0ebSJohn Baldwin device_get_nameunit(adap->dev), opcode); 5080069af0ebSJohn Baldwin return (EINVAL); 5081069af0ebSJohn Baldwin } 5082069af0ebSJohn Baldwin log(LOG_ERR, "%s: FW_ERROR (%s) ", device_get_nameunit(adap->dev), 5083069af0ebSJohn Baldwin G_FW_ERROR_CMD_FATAL(be32toh(e->op_to_type)) ? "fatal" : 5084069af0ebSJohn Baldwin "non-fatal"); 5085069af0ebSJohn Baldwin switch (G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type))) { 5086069af0ebSJohn Baldwin case FW_ERROR_TYPE_EXCEPTION: 5087069af0ebSJohn Baldwin log(LOG_ERR, "exception info:\n"); 5088069af0ebSJohn Baldwin for (i = 0; i < nitems(e->u.exception.info); i++) 5089069af0ebSJohn Baldwin log(LOG_ERR, "%s%08x", i == 0 ? "\t" : " ", 5090069af0ebSJohn Baldwin be32toh(e->u.exception.info[i])); 5091069af0ebSJohn Baldwin log(LOG_ERR, "\n"); 5092069af0ebSJohn Baldwin break; 5093069af0ebSJohn Baldwin case FW_ERROR_TYPE_HWMODULE: 5094069af0ebSJohn Baldwin log(LOG_ERR, "HW module regaddr %08x regval %08x\n", 5095069af0ebSJohn Baldwin be32toh(e->u.hwmodule.regaddr), 5096069af0ebSJohn Baldwin be32toh(e->u.hwmodule.regval)); 5097069af0ebSJohn Baldwin break; 5098069af0ebSJohn Baldwin case FW_ERROR_TYPE_WR: 5099069af0ebSJohn Baldwin log(LOG_ERR, "WR cidx %d PF %d VF %d eqid %d hdr:\n", 5100069af0ebSJohn Baldwin be16toh(e->u.wr.cidx), 5101069af0ebSJohn Baldwin G_FW_ERROR_CMD_PFN(be16toh(e->u.wr.pfn_vfn)), 5102069af0ebSJohn Baldwin G_FW_ERROR_CMD_VFN(be16toh(e->u.wr.pfn_vfn)), 5103069af0ebSJohn Baldwin be32toh(e->u.wr.eqid)); 5104069af0ebSJohn Baldwin for (i = 0; i < nitems(e->u.wr.wrhdr); i++) 5105069af0ebSJohn Baldwin log(LOG_ERR, "%s%02x", i == 0 ? "\t" : " ", 5106069af0ebSJohn Baldwin e->u.wr.wrhdr[i]); 5107069af0ebSJohn Baldwin log(LOG_ERR, "\n"); 5108069af0ebSJohn Baldwin break; 5109069af0ebSJohn Baldwin case FW_ERROR_TYPE_ACL: 5110069af0ebSJohn Baldwin log(LOG_ERR, "ACL cidx %d PF %d VF %d eqid %d %s", 5111069af0ebSJohn Baldwin be16toh(e->u.acl.cidx), 5112069af0ebSJohn Baldwin G_FW_ERROR_CMD_PFN(be16toh(e->u.acl.pfn_vfn)), 5113069af0ebSJohn Baldwin G_FW_ERROR_CMD_VFN(be16toh(e->u.acl.pfn_vfn)), 5114069af0ebSJohn Baldwin be32toh(e->u.acl.eqid), 5115069af0ebSJohn Baldwin G_FW_ERROR_CMD_MV(be16toh(e->u.acl.mv_pkd)) ? "vlanid" : 5116069af0ebSJohn Baldwin "MAC"); 5117069af0ebSJohn Baldwin for (i = 0; i < nitems(e->u.acl.val); i++) 5118069af0ebSJohn Baldwin log(LOG_ERR, " %02x", e->u.acl.val[i]); 5119069af0ebSJohn Baldwin log(LOG_ERR, "\n"); 5120069af0ebSJohn Baldwin break; 5121069af0ebSJohn Baldwin default: 5122069af0ebSJohn Baldwin log(LOG_ERR, "type %#x\n", 5123069af0ebSJohn Baldwin G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type))); 5124069af0ebSJohn Baldwin return (EINVAL); 5125069af0ebSJohn Baldwin } 5126069af0ebSJohn Baldwin return (0); 5127069af0ebSJohn Baldwin } 5128069af0ebSJohn Baldwin 5129af49c942SNavdeep Parhar static int 513056599263SNavdeep Parhar sysctl_uint16(SYSCTL_HANDLER_ARGS) 5131af49c942SNavdeep Parhar { 5132af49c942SNavdeep Parhar uint16_t *id = arg1; 5133af49c942SNavdeep Parhar int i = *id; 5134af49c942SNavdeep Parhar 5135af49c942SNavdeep Parhar return sysctl_handle_int(oidp, &i, 0, req); 5136af49c942SNavdeep Parhar } 513738035ed6SNavdeep Parhar 513838035ed6SNavdeep Parhar static int 513938035ed6SNavdeep Parhar sysctl_bufsizes(SYSCTL_HANDLER_ARGS) 514038035ed6SNavdeep Parhar { 514138035ed6SNavdeep Parhar struct sge *s = arg1; 514238035ed6SNavdeep Parhar struct hw_buf_info *hwb = &s->hw_buf_info[0]; 514338035ed6SNavdeep Parhar struct sw_zone_info *swz = &s->sw_zone_info[0]; 514438035ed6SNavdeep Parhar int i, rc; 514538035ed6SNavdeep Parhar struct sbuf sb; 514638035ed6SNavdeep Parhar char c; 514738035ed6SNavdeep Parhar 514838035ed6SNavdeep Parhar sbuf_new(&sb, NULL, 32, SBUF_AUTOEXTEND); 514938035ed6SNavdeep Parhar for (i = 0; i < SGE_FLBUF_SIZES; i++, hwb++) { 515038035ed6SNavdeep Parhar if (hwb->zidx >= 0 && swz[hwb->zidx].size <= largest_rx_cluster) 515138035ed6SNavdeep Parhar c = '*'; 515238035ed6SNavdeep Parhar else 515338035ed6SNavdeep Parhar c = '\0'; 515438035ed6SNavdeep Parhar 515538035ed6SNavdeep Parhar sbuf_printf(&sb, "%u%c ", hwb->size, c); 515638035ed6SNavdeep Parhar } 515738035ed6SNavdeep Parhar sbuf_trim(&sb); 515838035ed6SNavdeep Parhar sbuf_finish(&sb); 515938035ed6SNavdeep Parhar rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req); 516038035ed6SNavdeep Parhar sbuf_delete(&sb); 516138035ed6SNavdeep Parhar return (rc); 516238035ed6SNavdeep Parhar } 516302f972e8SNavdeep Parhar 516402f972e8SNavdeep Parhar static int 516502f972e8SNavdeep Parhar sysctl_tc(SYSCTL_HANDLER_ARGS) 516602f972e8SNavdeep Parhar { 516702f972e8SNavdeep Parhar struct vi_info *vi = arg1; 516802f972e8SNavdeep Parhar struct port_info *pi; 516902f972e8SNavdeep Parhar struct adapter *sc; 517002f972e8SNavdeep Parhar struct sge_txq *txq; 51712204b427SNavdeep Parhar struct tx_cl_rl_params *tc; 517202f972e8SNavdeep Parhar int qidx = arg2, rc, tc_idx; 517302f972e8SNavdeep Parhar uint32_t fw_queue, fw_class; 517402f972e8SNavdeep Parhar 517502f972e8SNavdeep Parhar MPASS(qidx >= 0 && qidx < vi->ntxq); 517602f972e8SNavdeep Parhar pi = vi->pi; 517702f972e8SNavdeep Parhar sc = pi->adapter; 517802f972e8SNavdeep Parhar txq = &sc->sge.txq[vi->first_txq + qidx]; 517902f972e8SNavdeep Parhar 518002f972e8SNavdeep Parhar tc_idx = txq->tc_idx; 518102f972e8SNavdeep Parhar rc = sysctl_handle_int(oidp, &tc_idx, 0, req); 518202f972e8SNavdeep Parhar if (rc != 0 || req->newptr == NULL) 518302f972e8SNavdeep Parhar return (rc); 518402f972e8SNavdeep Parhar 51852204b427SNavdeep Parhar if (sc->flags & IS_VF) 51862204b427SNavdeep Parhar return (EPERM); 51872204b427SNavdeep Parhar 518802f972e8SNavdeep Parhar /* Note that -1 is legitimate input (it means unbind). */ 518902f972e8SNavdeep Parhar if (tc_idx < -1 || tc_idx >= sc->chip_params->nsched_cls) 519002f972e8SNavdeep Parhar return (EINVAL); 519102f972e8SNavdeep Parhar 51922204b427SNavdeep Parhar mtx_lock(&sc->tc_lock); 519302f972e8SNavdeep Parhar if (tc_idx == txq->tc_idx) { 519402f972e8SNavdeep Parhar rc = 0; /* No change, nothing to do. */ 519502f972e8SNavdeep Parhar goto done; 519602f972e8SNavdeep Parhar } 519702f972e8SNavdeep Parhar 519802f972e8SNavdeep Parhar fw_queue = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 519902f972e8SNavdeep Parhar V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH) | 520002f972e8SNavdeep Parhar V_FW_PARAMS_PARAM_YZ(txq->eq.cntxt_id); 520102f972e8SNavdeep Parhar 520202f972e8SNavdeep Parhar if (tc_idx == -1) 520302f972e8SNavdeep Parhar fw_class = 0xffffffff; /* Unbind. */ 520402f972e8SNavdeep Parhar else { 520502f972e8SNavdeep Parhar /* 52062204b427SNavdeep Parhar * Bind to a different class. 520702f972e8SNavdeep Parhar */ 52082204b427SNavdeep Parhar tc = &pi->sched_params->cl_rl[tc_idx]; 52092204b427SNavdeep Parhar if (tc->flags & TX_CLRL_ERROR) { 52102204b427SNavdeep Parhar /* Previous attempt to set the cl-rl params failed. */ 52112204b427SNavdeep Parhar rc = EIO; 521202f972e8SNavdeep Parhar goto done; 52132204b427SNavdeep Parhar } else { 52142204b427SNavdeep Parhar /* 52152204b427SNavdeep Parhar * Ok to proceed. Place a reference on the new class 52162204b427SNavdeep Parhar * while still holding on to the reference on the 52172204b427SNavdeep Parhar * previous class, if any. 52182204b427SNavdeep Parhar */ 52192204b427SNavdeep Parhar fw_class = tc_idx; 52202204b427SNavdeep Parhar tc->refcount++; 522102f972e8SNavdeep Parhar } 522202f972e8SNavdeep Parhar } 52232204b427SNavdeep Parhar mtx_unlock(&sc->tc_lock); 522402f972e8SNavdeep Parhar 52252204b427SNavdeep Parhar rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4stc"); 52262204b427SNavdeep Parhar if (rc) 52272204b427SNavdeep Parhar return (rc); 522802f972e8SNavdeep Parhar rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &fw_queue, &fw_class); 52292204b427SNavdeep Parhar end_synchronized_op(sc, 0); 52302204b427SNavdeep Parhar 52312204b427SNavdeep Parhar mtx_lock(&sc->tc_lock); 523202f972e8SNavdeep Parhar if (rc == 0) { 523302f972e8SNavdeep Parhar if (txq->tc_idx != -1) { 52342204b427SNavdeep Parhar tc = &pi->sched_params->cl_rl[txq->tc_idx]; 523502f972e8SNavdeep Parhar MPASS(tc->refcount > 0); 523602f972e8SNavdeep Parhar tc->refcount--; 523702f972e8SNavdeep Parhar } 523802f972e8SNavdeep Parhar txq->tc_idx = tc_idx; 52393f1466a5SNavdeep Parhar } else if (tc_idx != -1) { 52402204b427SNavdeep Parhar tc = &pi->sched_params->cl_rl[tc_idx]; 52412204b427SNavdeep Parhar MPASS(tc->refcount > 0); 52422204b427SNavdeep Parhar tc->refcount--; 524302f972e8SNavdeep Parhar } 524402f972e8SNavdeep Parhar done: 52452204b427SNavdeep Parhar mtx_unlock(&sc->tc_lock); 524602f972e8SNavdeep Parhar return (rc); 524702f972e8SNavdeep Parhar } 5248