1 /*- 2 * Copyright (c) 2014 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 34 #ifdef DEV_NETMAP 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/eventhandler.h> 38 #include <sys/lock.h> 39 #include <sys/mbuf.h> 40 #include <sys/module.h> 41 #include <sys/selinfo.h> 42 #include <sys/socket.h> 43 #include <sys/sockio.h> 44 #include <machine/bus.h> 45 #include <net/ethernet.h> 46 #include <net/if.h> 47 #include <net/if_media.h> 48 #include <net/if_var.h> 49 #include <net/if_clone.h> 50 #include <net/if_types.h> 51 #include <net/netmap.h> 52 #include <dev/netmap/netmap_kern.h> 53 54 #include "common/common.h" 55 #include "common/t4_regs.h" 56 #include "common/t4_regs_values.h" 57 58 extern int fl_pad; /* XXXNM */ 59 60 SYSCTL_NODE(_hw, OID_AUTO, cxgbe, CTLFLAG_RD, 0, "cxgbe netmap parameters"); 61 62 /* 63 * 0 = normal netmap rx 64 * 1 = black hole 65 * 2 = supermassive black hole (buffer packing enabled) 66 */ 67 int black_hole = 0; 68 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_black_hole, CTLFLAG_RDTUN, &black_hole, 0, 69 "Sink incoming packets."); 70 71 int rx_ndesc = 256; 72 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_rx_ndesc, CTLFLAG_RWTUN, 73 &rx_ndesc, 0, "# of rx descriptors after which the hw cidx is updated."); 74 75 int rx_nframes = 64; 76 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_rx_nframes, CTLFLAG_RWTUN, 77 &rx_nframes, 0, "max # of frames received before waking up netmap rx."); 78 79 int holdoff_tmr_idx = 2; 80 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_holdoff_tmr_idx, CTLFLAG_RWTUN, 81 &holdoff_tmr_idx, 0, "Holdoff timer index for netmap rx queues."); 82 83 /* 84 * Congestion drops. 85 * -1: no congestion feedback (not recommended). 86 * 0: backpressure the channel instead of dropping packets right away. 87 * 1: no backpressure, drop packets for the congested queue immediately. 88 */ 89 static int nm_cong_drop = 1; 90 TUNABLE_INT("hw.cxgbe.nm_cong_drop", &nm_cong_drop); 91 92 int starve_fl = 0; 93 SYSCTL_INT(_hw_cxgbe, OID_AUTO, starve_fl, CTLFLAG_RWTUN, 94 &starve_fl, 0, "Don't ring fl db for netmap rx queues."); 95 96 /* 97 * Try to process tx credits in bulk. This may cause a delay in the return of 98 * tx credits and is suitable for bursty or non-stop tx only. 99 */ 100 int lazy_tx_credit_flush = 1; 101 SYSCTL_INT(_hw_cxgbe, OID_AUTO, lazy_tx_credit_flush, CTLFLAG_RWTUN, 102 &lazy_tx_credit_flush, 0, "lazy credit flush for netmap tx queues."); 103 104 /* 105 * Split the netmap rx queues into two groups that populate separate halves of 106 * the RSS indirection table. This allows filters with hashmask to steer to a 107 * particular group of queues. 108 */ 109 static int nm_split_rss = 0; 110 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_split_rss, CTLFLAG_RWTUN, 111 &nm_split_rss, 0, "Split the netmap rx queues into two groups."); 112 113 static int 114 alloc_nm_rxq_hwq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq, int cong) 115 { 116 int rc, cntxt_id, i; 117 __be32 v; 118 struct adapter *sc = vi->pi->adapter; 119 struct sge_params *sp = &sc->params.sge; 120 struct netmap_adapter *na = NA(vi->ifp); 121 struct fw_iq_cmd c; 122 123 MPASS(na != NULL); 124 MPASS(nm_rxq->iq_desc != NULL); 125 MPASS(nm_rxq->fl_desc != NULL); 126 127 bzero(nm_rxq->iq_desc, vi->qsize_rxq * IQ_ESIZE); 128 bzero(nm_rxq->fl_desc, na->num_rx_desc * EQ_ESIZE + sp->spg_len); 129 130 bzero(&c, sizeof(c)); 131 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 132 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) | 133 V_FW_IQ_CMD_VFN(0)); 134 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART | 135 FW_LEN16(c)); 136 MPASS(!forwarding_intr_to_fwq(sc)); 137 KASSERT(nm_rxq->intr_idx < sc->intr_count, 138 ("%s: invalid direct intr_idx %d", __func__, nm_rxq->intr_idx)); 139 v = V_FW_IQ_CMD_IQANDSTINDEX(nm_rxq->intr_idx); 140 c.type_to_iqandstindex = htobe32(v | 141 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) | 142 V_FW_IQ_CMD_VIID(vi->viid) | 143 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT)); 144 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(vi->pi->tx_chan) | 145 F_FW_IQ_CMD_IQGTSMODE | 146 V_FW_IQ_CMD_IQINTCNTTHRESH(0) | 147 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4)); 148 c.iqsize = htobe16(vi->qsize_rxq); 149 c.iqaddr = htobe64(nm_rxq->iq_ba); 150 if (cong >= 0) { 151 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN | 152 V_FW_IQ_CMD_FL0CNGCHMAP(cong) | F_FW_IQ_CMD_FL0CONGCIF | 153 F_FW_IQ_CMD_FL0CONGEN); 154 } 155 c.iqns_to_fl0congen |= 156 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) | 157 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO | 158 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) | 159 (black_hole == 2 ? F_FW_IQ_CMD_FL0PACKEN : 0)); 160 c.fl0dcaen_to_fl0cidxfthresh = 161 htobe16(V_FW_IQ_CMD_FL0FBMIN(chip_id(sc) <= CHELSIO_T5 ? 162 X_FETCHBURSTMIN_128B : X_FETCHBURSTMIN_64B) | 163 V_FW_IQ_CMD_FL0FBMAX(chip_id(sc) <= CHELSIO_T5 ? 164 X_FETCHBURSTMAX_512B : X_FETCHBURSTMAX_256B)); 165 c.fl0size = htobe16(na->num_rx_desc / 8 + sp->spg_len / EQ_ESIZE); 166 c.fl0addr = htobe64(nm_rxq->fl_ba); 167 168 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 169 if (rc != 0) { 170 device_printf(sc->dev, 171 "failed to create netmap ingress queue: %d\n", rc); 172 return (rc); 173 } 174 175 nm_rxq->iq_cidx = 0; 176 MPASS(nm_rxq->iq_sidx == vi->qsize_rxq - sp->spg_len / IQ_ESIZE); 177 nm_rxq->iq_gen = F_RSPD_GEN; 178 nm_rxq->iq_cntxt_id = be16toh(c.iqid); 179 nm_rxq->iq_abs_id = be16toh(c.physiqid); 180 cntxt_id = nm_rxq->iq_cntxt_id - sc->sge.iq_start; 181 if (cntxt_id >= sc->sge.niq) { 182 panic ("%s: nm_rxq->iq_cntxt_id (%d) more than the max (%d)", 183 __func__, cntxt_id, sc->sge.niq - 1); 184 } 185 sc->sge.iqmap[cntxt_id] = (void *)nm_rxq; 186 187 nm_rxq->fl_cntxt_id = be16toh(c.fl0id); 188 nm_rxq->fl_pidx = nm_rxq->fl_cidx = 0; 189 MPASS(nm_rxq->fl_sidx == na->num_rx_desc); 190 cntxt_id = nm_rxq->fl_cntxt_id - sc->sge.eq_start; 191 if (cntxt_id >= sc->sge.neq) { 192 panic("%s: nm_rxq->fl_cntxt_id (%d) more than the max (%d)", 193 __func__, cntxt_id, sc->sge.neq - 1); 194 } 195 sc->sge.eqmap[cntxt_id] = (void *)nm_rxq; 196 197 nm_rxq->fl_db_val = V_QID(nm_rxq->fl_cntxt_id) | 198 sc->chip_params->sge_fl_db; 199 200 if (chip_id(sc) >= CHELSIO_T5 && cong >= 0) { 201 uint32_t param, val; 202 203 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 204 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) | 205 V_FW_PARAMS_PARAM_YZ(nm_rxq->iq_cntxt_id); 206 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 207 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) | 208 V_FW_PARAMS_PARAM_YZ(nm_rxq->iq_cntxt_id); 209 if (cong == 0) 210 val = 1 << 19; 211 else { 212 val = 2 << 19; 213 for (i = 0; i < 4; i++) { 214 if (cong & (1 << i)) 215 val |= 1 << (i << 2); 216 } 217 } 218 219 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 220 if (rc != 0) { 221 /* report error but carry on */ 222 device_printf(sc->dev, 223 "failed to set congestion manager context for " 224 "ingress queue %d: %d\n", nm_rxq->iq_cntxt_id, rc); 225 } 226 } 227 228 t4_write_reg(sc, sc->sge_gts_reg, 229 V_INGRESSQID(nm_rxq->iq_cntxt_id) | 230 V_SEINTARM(V_QINTR_TIMER_IDX(holdoff_tmr_idx))); 231 232 return (rc); 233 } 234 235 static int 236 free_nm_rxq_hwq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq) 237 { 238 struct adapter *sc = vi->pi->adapter; 239 int rc; 240 241 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0, FW_IQ_TYPE_FL_INT_CAP, 242 nm_rxq->iq_cntxt_id, nm_rxq->fl_cntxt_id, 0xffff); 243 if (rc != 0) 244 device_printf(sc->dev, "%s: failed for iq %d, fl %d: %d\n", 245 __func__, nm_rxq->iq_cntxt_id, nm_rxq->fl_cntxt_id, rc); 246 nm_rxq->iq_cntxt_id = INVALID_NM_RXQ_CNTXT_ID; 247 return (rc); 248 } 249 250 static int 251 alloc_nm_txq_hwq(struct vi_info *vi, struct sge_nm_txq *nm_txq) 252 { 253 int rc, cntxt_id; 254 size_t len; 255 struct adapter *sc = vi->pi->adapter; 256 struct netmap_adapter *na = NA(vi->ifp); 257 struct fw_eq_eth_cmd c; 258 259 MPASS(na != NULL); 260 MPASS(nm_txq->desc != NULL); 261 262 len = na->num_tx_desc * EQ_ESIZE + sc->params.sge.spg_len; 263 bzero(nm_txq->desc, len); 264 265 bzero(&c, sizeof(c)); 266 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST | 267 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) | 268 V_FW_EQ_ETH_CMD_VFN(0)); 269 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC | 270 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c)); 271 c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE | 272 F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(vi->viid)); 273 c.fetchszm_to_iqid = 274 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) | 275 V_FW_EQ_ETH_CMD_PCIECHN(vi->pi->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO | 276 V_FW_EQ_ETH_CMD_IQID(sc->sge.nm_rxq[nm_txq->iqidx].iq_cntxt_id)); 277 c.dcaen_to_eqsize = htobe32(V_FW_EQ_ETH_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 278 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 279 V_FW_EQ_ETH_CMD_EQSIZE(len / EQ_ESIZE)); 280 c.eqaddr = htobe64(nm_txq->ba); 281 282 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 283 if (rc != 0) { 284 device_printf(vi->dev, 285 "failed to create netmap egress queue: %d\n", rc); 286 return (rc); 287 } 288 289 nm_txq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd)); 290 cntxt_id = nm_txq->cntxt_id - sc->sge.eq_start; 291 if (cntxt_id >= sc->sge.neq) 292 panic("%s: nm_txq->cntxt_id (%d) more than the max (%d)", __func__, 293 cntxt_id, sc->sge.neq - 1); 294 sc->sge.eqmap[cntxt_id] = (void *)nm_txq; 295 296 nm_txq->pidx = nm_txq->cidx = 0; 297 MPASS(nm_txq->sidx == na->num_tx_desc); 298 nm_txq->equiqidx = nm_txq->equeqidx = nm_txq->dbidx = 0; 299 300 nm_txq->doorbells = sc->doorbells; 301 if (isset(&nm_txq->doorbells, DOORBELL_UDB) || 302 isset(&nm_txq->doorbells, DOORBELL_UDBWC) || 303 isset(&nm_txq->doorbells, DOORBELL_WCWR)) { 304 uint32_t s_qpp = sc->params.sge.eq_s_qpp; 305 uint32_t mask = (1 << s_qpp) - 1; 306 volatile uint8_t *udb; 307 308 udb = sc->udbs_base + UDBS_DB_OFFSET; 309 udb += (nm_txq->cntxt_id >> s_qpp) << PAGE_SHIFT; 310 nm_txq->udb_qid = nm_txq->cntxt_id & mask; 311 if (nm_txq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE) 312 clrbit(&nm_txq->doorbells, DOORBELL_WCWR); 313 else { 314 udb += nm_txq->udb_qid << UDBS_SEG_SHIFT; 315 nm_txq->udb_qid = 0; 316 } 317 nm_txq->udb = (volatile void *)udb; 318 } 319 320 return (rc); 321 } 322 323 static int 324 free_nm_txq_hwq(struct vi_info *vi, struct sge_nm_txq *nm_txq) 325 { 326 struct adapter *sc = vi->pi->adapter; 327 int rc; 328 329 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0, nm_txq->cntxt_id); 330 if (rc != 0) 331 device_printf(sc->dev, "%s: failed for eq %d: %d\n", __func__, 332 nm_txq->cntxt_id, rc); 333 nm_txq->cntxt_id = INVALID_NM_TXQ_CNTXT_ID; 334 return (rc); 335 } 336 337 static int 338 cxgbe_netmap_on(struct adapter *sc, struct vi_info *vi, struct ifnet *ifp, 339 struct netmap_adapter *na) 340 { 341 struct netmap_slot *slot; 342 struct netmap_kring *kring; 343 struct sge_nm_rxq *nm_rxq; 344 struct sge_nm_txq *nm_txq; 345 int rc, i, j, hwidx, defq, nrssq; 346 struct hw_buf_info *hwb; 347 348 ASSERT_SYNCHRONIZED_OP(sc); 349 350 if ((vi->flags & VI_INIT_DONE) == 0 || 351 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 352 return (EAGAIN); 353 354 hwb = &sc->sge.hw_buf_info[0]; 355 for (i = 0; i < SGE_FLBUF_SIZES; i++, hwb++) { 356 if (hwb->size == NETMAP_BUF_SIZE(na)) 357 break; 358 } 359 if (i >= SGE_FLBUF_SIZES) { 360 if_printf(ifp, "no hwidx for netmap buffer size %d.\n", 361 NETMAP_BUF_SIZE(na)); 362 return (ENXIO); 363 } 364 hwidx = i; 365 366 /* Must set caps before calling netmap_reset */ 367 nm_set_native_flags(na); 368 369 for_each_nm_rxq(vi, i, nm_rxq) { 370 kring = na->rx_rings[nm_rxq->nid]; 371 if (!nm_kring_pending_on(kring) || 372 nm_rxq->iq_cntxt_id != INVALID_NM_RXQ_CNTXT_ID) 373 continue; 374 375 alloc_nm_rxq_hwq(vi, nm_rxq, tnl_cong(vi->pi, nm_cong_drop)); 376 nm_rxq->fl_hwidx = hwidx; 377 slot = netmap_reset(na, NR_RX, i, 0); 378 MPASS(slot != NULL); /* XXXNM: error check, not assert */ 379 380 /* We deal with 8 bufs at a time */ 381 MPASS((na->num_rx_desc & 7) == 0); 382 MPASS(na->num_rx_desc == nm_rxq->fl_sidx); 383 for (j = 0; j < nm_rxq->fl_sidx; j++) { 384 uint64_t ba; 385 386 PNMB(na, &slot[j], &ba); 387 MPASS(ba != 0); 388 nm_rxq->fl_desc[j] = htobe64(ba | hwidx); 389 } 390 j = nm_rxq->fl_pidx = nm_rxq->fl_sidx - 8; 391 MPASS((j & 7) == 0); 392 j /= 8; /* driver pidx to hardware pidx */ 393 wmb(); 394 t4_write_reg(sc, sc->sge_kdoorbell_reg, 395 nm_rxq->fl_db_val | V_PIDX(j)); 396 397 (void) atomic_cmpset_int(&nm_rxq->nm_state, NM_OFF, NM_ON); 398 } 399 400 for_each_nm_txq(vi, i, nm_txq) { 401 kring = na->tx_rings[nm_txq->nid]; 402 if (!nm_kring_pending_on(kring) || 403 nm_txq->cntxt_id != INVALID_NM_TXQ_CNTXT_ID) 404 continue; 405 406 alloc_nm_txq_hwq(vi, nm_txq); 407 slot = netmap_reset(na, NR_TX, i, 0); 408 MPASS(slot != NULL); /* XXXNM: error check, not assert */ 409 } 410 411 if (vi->nm_rss == NULL) { 412 vi->nm_rss = malloc(vi->rss_size * sizeof(uint16_t), M_CXGBE, 413 M_ZERO | M_WAITOK); 414 } 415 416 MPASS(vi->nnmrxq > 0); 417 if (nm_split_rss == 0 || vi->nnmrxq == 1) { 418 for (i = 0; i < vi->rss_size;) { 419 for_each_nm_rxq(vi, j, nm_rxq) { 420 vi->nm_rss[i++] = nm_rxq->iq_abs_id; 421 if (i == vi->rss_size) 422 break; 423 } 424 } 425 defq = vi->nm_rss[0]; 426 } else { 427 /* We have multiple queues and we want to split the table. */ 428 MPASS(nm_split_rss != 0); 429 MPASS(vi->nnmrxq > 1); 430 431 nm_rxq = &sc->sge.nm_rxq[vi->first_nm_rxq]; 432 nrssq = vi->nnmrxq; 433 if (vi->nnmrxq & 1) { 434 /* 435 * Odd number of queues. The first rxq is designated the 436 * default queue, the rest are split evenly. 437 */ 438 defq = nm_rxq->iq_abs_id; 439 nm_rxq++; 440 nrssq--; 441 } else { 442 /* 443 * Even number of queues split into two halves. The 444 * first rxq in one of the halves is designated the 445 * default queue. 446 */ 447 #if 1 448 /* First rxq in the first half. */ 449 defq = nm_rxq->iq_abs_id; 450 #else 451 /* First rxq in the second half. */ 452 defq = nm_rxq[vi->nnmrxq / 2].iq_abs_id; 453 #endif 454 } 455 456 i = 0; 457 while (i < vi->rss_size / 2) { 458 for (j = 0; j < nrssq / 2; j++) { 459 vi->nm_rss[i++] = nm_rxq[j].iq_abs_id; 460 if (i == vi->rss_size / 2) 461 break; 462 } 463 } 464 while (i < vi->rss_size) { 465 for (j = nrssq / 2; j < nrssq; j++) { 466 vi->nm_rss[i++] = nm_rxq[j].iq_abs_id; 467 if (i == vi->rss_size) 468 break; 469 } 470 } 471 } 472 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, 473 vi->nm_rss, vi->rss_size); 474 if (rc != 0) 475 if_printf(ifp, "netmap rss_config failed: %d\n", rc); 476 477 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, vi->hashen, defq, 0, 0); 478 if (rc != 0) 479 if_printf(ifp, "netmap rss hash/defaultq config failed: %d\n", rc); 480 481 return (rc); 482 } 483 484 static int 485 cxgbe_netmap_off(struct adapter *sc, struct vi_info *vi, struct ifnet *ifp, 486 struct netmap_adapter *na) 487 { 488 struct netmap_kring *kring; 489 int rc, i; 490 struct sge_nm_txq *nm_txq; 491 struct sge_nm_rxq *nm_rxq; 492 493 ASSERT_SYNCHRONIZED_OP(sc); 494 495 if ((vi->flags & VI_INIT_DONE) == 0) 496 return (0); 497 498 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, 499 vi->rss, vi->rss_size); 500 if (rc != 0) 501 if_printf(ifp, "failed to restore RSS config: %d\n", rc); 502 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, vi->hashen, vi->rss[0], 0, 0); 503 if (rc != 0) 504 if_printf(ifp, "failed to restore RSS hash/defaultq: %d\n", rc); 505 nm_clear_native_flags(na); 506 507 for_each_nm_txq(vi, i, nm_txq) { 508 struct sge_qstat *spg = (void *)&nm_txq->desc[nm_txq->sidx]; 509 510 kring = na->tx_rings[nm_txq->nid]; 511 if (!nm_kring_pending_off(kring) || 512 nm_txq->cntxt_id == INVALID_NM_TXQ_CNTXT_ID) 513 continue; 514 515 /* Wait for hw pidx to catch up ... */ 516 while (be16toh(nm_txq->pidx) != spg->pidx) 517 pause("nmpidx", 1); 518 519 /* ... and then for the cidx. */ 520 while (spg->pidx != spg->cidx) 521 pause("nmcidx", 1); 522 523 free_nm_txq_hwq(vi, nm_txq); 524 } 525 for_each_nm_rxq(vi, i, nm_rxq) { 526 kring = na->rx_rings[nm_rxq->nid]; 527 if (!nm_kring_pending_off(kring) || 528 nm_rxq->iq_cntxt_id == INVALID_NM_RXQ_CNTXT_ID) 529 continue; 530 531 while (!atomic_cmpset_int(&nm_rxq->nm_state, NM_ON, NM_OFF)) 532 pause("nmst", 1); 533 534 free_nm_rxq_hwq(vi, nm_rxq); 535 } 536 537 return (rc); 538 } 539 540 static int 541 cxgbe_netmap_reg(struct netmap_adapter *na, int on) 542 { 543 struct ifnet *ifp = na->ifp; 544 struct vi_info *vi = ifp->if_softc; 545 struct adapter *sc = vi->pi->adapter; 546 int rc; 547 548 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4nmreg"); 549 if (rc != 0) 550 return (rc); 551 if (on) 552 rc = cxgbe_netmap_on(sc, vi, ifp, na); 553 else 554 rc = cxgbe_netmap_off(sc, vi, ifp, na); 555 end_synchronized_op(sc, 0); 556 557 return (rc); 558 } 559 560 /* How many packets can a single type1 WR carry in n descriptors */ 561 static inline int 562 ndesc_to_npkt(const int n) 563 { 564 565 MPASS(n > 0 && n <= SGE_MAX_WR_NDESC); 566 567 return (n * 2 - 1); 568 } 569 #define MAX_NPKT_IN_TYPE1_WR (ndesc_to_npkt(SGE_MAX_WR_NDESC)) 570 571 /* Space (in descriptors) needed for a type1 WR that carries n packets */ 572 static inline int 573 npkt_to_ndesc(const int n) 574 { 575 576 MPASS(n > 0 && n <= MAX_NPKT_IN_TYPE1_WR); 577 578 return ((n + 2) / 2); 579 } 580 581 /* Space (in 16B units) needed for a type1 WR that carries n packets */ 582 static inline int 583 npkt_to_len16(const int n) 584 { 585 586 MPASS(n > 0 && n <= MAX_NPKT_IN_TYPE1_WR); 587 588 return (n * 2 + 1); 589 } 590 591 #define NMIDXDIFF(q, idx) IDXDIFF((q)->pidx, (q)->idx, (q)->sidx) 592 593 static void 594 ring_nm_txq_db(struct adapter *sc, struct sge_nm_txq *nm_txq) 595 { 596 int n; 597 u_int db = nm_txq->doorbells; 598 599 MPASS(nm_txq->pidx != nm_txq->dbidx); 600 601 n = NMIDXDIFF(nm_txq, dbidx); 602 if (n > 1) 603 clrbit(&db, DOORBELL_WCWR); 604 wmb(); 605 606 switch (ffs(db) - 1) { 607 case DOORBELL_UDB: 608 *nm_txq->udb = htole32(V_QID(nm_txq->udb_qid) | V_PIDX(n)); 609 break; 610 611 case DOORBELL_WCWR: { 612 volatile uint64_t *dst, *src; 613 614 /* 615 * Queues whose 128B doorbell segment fits in the page do not 616 * use relative qid (udb_qid is always 0). Only queues with 617 * doorbell segments can do WCWR. 618 */ 619 KASSERT(nm_txq->udb_qid == 0 && n == 1, 620 ("%s: inappropriate doorbell (0x%x, %d, %d) for nm_txq %p", 621 __func__, nm_txq->doorbells, n, nm_txq->pidx, nm_txq)); 622 623 dst = (volatile void *)((uintptr_t)nm_txq->udb + 624 UDBS_WR_OFFSET - UDBS_DB_OFFSET); 625 src = (void *)&nm_txq->desc[nm_txq->dbidx]; 626 while (src != (void *)&nm_txq->desc[nm_txq->dbidx + 1]) 627 *dst++ = *src++; 628 wmb(); 629 break; 630 } 631 632 case DOORBELL_UDBWC: 633 *nm_txq->udb = htole32(V_QID(nm_txq->udb_qid) | V_PIDX(n)); 634 wmb(); 635 break; 636 637 case DOORBELL_KDB: 638 t4_write_reg(sc, sc->sge_kdoorbell_reg, 639 V_QID(nm_txq->cntxt_id) | V_PIDX(n)); 640 break; 641 } 642 nm_txq->dbidx = nm_txq->pidx; 643 } 644 645 /* 646 * Write work requests to send 'npkt' frames and ring the doorbell to send them 647 * on their way. No need to check for wraparound. 648 */ 649 static void 650 cxgbe_nm_tx(struct adapter *sc, struct sge_nm_txq *nm_txq, 651 struct netmap_kring *kring, int npkt, int npkt_remaining, int txcsum) 652 { 653 struct netmap_ring *ring = kring->ring; 654 struct netmap_slot *slot; 655 const u_int lim = kring->nkr_num_slots - 1; 656 struct fw_eth_tx_pkts_wr *wr = (void *)&nm_txq->desc[nm_txq->pidx]; 657 uint16_t len; 658 uint64_t ba; 659 struct cpl_tx_pkt_core *cpl; 660 struct ulptx_sgl *usgl; 661 int i, n; 662 663 while (npkt) { 664 n = min(npkt, MAX_NPKT_IN_TYPE1_WR); 665 len = 0; 666 667 wr = (void *)&nm_txq->desc[nm_txq->pidx]; 668 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR)); 669 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(npkt_to_len16(n))); 670 wr->npkt = n; 671 wr->r3 = 0; 672 wr->type = 1; 673 cpl = (void *)(wr + 1); 674 675 for (i = 0; i < n; i++) { 676 slot = &ring->slot[kring->nr_hwcur]; 677 PNMB(kring->na, slot, &ba); 678 MPASS(ba != 0); 679 680 cpl->ctrl0 = nm_txq->cpl_ctrl0; 681 cpl->pack = 0; 682 cpl->len = htobe16(slot->len); 683 /* 684 * netmap(4) says "netmap does not use features such as 685 * checksum offloading, TCP segmentation offloading, 686 * encryption, VLAN encapsulation/decapsulation, etc." 687 * 688 * So the ncxl interfaces have tx hardware checksumming 689 * disabled by default. But you can override netmap by 690 * enabling IFCAP_TXCSUM on the interface manully. 691 */ 692 cpl->ctrl1 = txcsum ? 0 : 693 htobe64(F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS); 694 695 usgl = (void *)(cpl + 1); 696 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 697 V_ULPTX_NSGE(1)); 698 usgl->len0 = htobe32(slot->len); 699 usgl->addr0 = htobe64(ba); 700 701 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); 702 cpl = (void *)(usgl + 1); 703 MPASS(slot->len + len <= UINT16_MAX); 704 len += slot->len; 705 kring->nr_hwcur = nm_next(kring->nr_hwcur, lim); 706 } 707 wr->plen = htobe16(len); 708 709 npkt -= n; 710 nm_txq->pidx += npkt_to_ndesc(n); 711 MPASS(nm_txq->pidx <= nm_txq->sidx); 712 if (__predict_false(nm_txq->pidx == nm_txq->sidx)) { 713 /* 714 * This routine doesn't know how to write WRs that wrap 715 * around. Make sure it wasn't asked to. 716 */ 717 MPASS(npkt == 0); 718 nm_txq->pidx = 0; 719 } 720 721 if (npkt == 0 && npkt_remaining == 0) { 722 /* All done. */ 723 if (lazy_tx_credit_flush == 0) { 724 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ | 725 F_FW_WR_EQUIQ); 726 nm_txq->equeqidx = nm_txq->pidx; 727 nm_txq->equiqidx = nm_txq->pidx; 728 } 729 ring_nm_txq_db(sc, nm_txq); 730 return; 731 } 732 733 if (NMIDXDIFF(nm_txq, equiqidx) >= nm_txq->sidx / 2) { 734 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ | 735 F_FW_WR_EQUIQ); 736 nm_txq->equeqidx = nm_txq->pidx; 737 nm_txq->equiqidx = nm_txq->pidx; 738 } else if (NMIDXDIFF(nm_txq, equeqidx) >= 64) { 739 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ); 740 nm_txq->equeqidx = nm_txq->pidx; 741 } 742 if (NMIDXDIFF(nm_txq, dbidx) >= 2 * SGE_MAX_WR_NDESC) 743 ring_nm_txq_db(sc, nm_txq); 744 } 745 746 /* Will get called again. */ 747 MPASS(npkt_remaining); 748 } 749 750 /* How many contiguous free descriptors starting at pidx */ 751 static inline int 752 contiguous_ndesc_available(struct sge_nm_txq *nm_txq) 753 { 754 755 if (nm_txq->cidx > nm_txq->pidx) 756 return (nm_txq->cidx - nm_txq->pidx - 1); 757 else if (nm_txq->cidx > 0) 758 return (nm_txq->sidx - nm_txq->pidx); 759 else 760 return (nm_txq->sidx - nm_txq->pidx - 1); 761 } 762 763 static int 764 reclaim_nm_tx_desc(struct sge_nm_txq *nm_txq) 765 { 766 struct sge_qstat *spg = (void *)&nm_txq->desc[nm_txq->sidx]; 767 uint16_t hw_cidx = spg->cidx; /* snapshot */ 768 struct fw_eth_tx_pkts_wr *wr; 769 int n = 0; 770 771 hw_cidx = be16toh(hw_cidx); 772 773 while (nm_txq->cidx != hw_cidx) { 774 wr = (void *)&nm_txq->desc[nm_txq->cidx]; 775 776 MPASS(wr->op_pkd == htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR))); 777 MPASS(wr->type == 1); 778 MPASS(wr->npkt > 0 && wr->npkt <= MAX_NPKT_IN_TYPE1_WR); 779 780 n += wr->npkt; 781 nm_txq->cidx += npkt_to_ndesc(wr->npkt); 782 783 /* 784 * We never sent a WR that wrapped around so the credits coming 785 * back, WR by WR, should never cause the cidx to wrap around 786 * either. 787 */ 788 MPASS(nm_txq->cidx <= nm_txq->sidx); 789 if (__predict_false(nm_txq->cidx == nm_txq->sidx)) 790 nm_txq->cidx = 0; 791 } 792 793 return (n); 794 } 795 796 static int 797 cxgbe_netmap_txsync(struct netmap_kring *kring, int flags) 798 { 799 struct netmap_adapter *na = kring->na; 800 struct ifnet *ifp = na->ifp; 801 struct vi_info *vi = ifp->if_softc; 802 struct adapter *sc = vi->pi->adapter; 803 struct sge_nm_txq *nm_txq = &sc->sge.nm_txq[vi->first_nm_txq + kring->ring_id]; 804 const u_int head = kring->rhead; 805 u_int reclaimed = 0; 806 int n, d, npkt_remaining, ndesc_remaining, txcsum; 807 808 /* 809 * Tx was at kring->nr_hwcur last time around and now we need to advance 810 * to kring->rhead. Note that the driver's pidx moves independent of 811 * netmap's kring->nr_hwcur (pidx counts descriptors and the relation 812 * between descriptors and frames isn't 1:1). 813 */ 814 815 npkt_remaining = head >= kring->nr_hwcur ? head - kring->nr_hwcur : 816 kring->nkr_num_slots - kring->nr_hwcur + head; 817 txcsum = ifp->if_capenable & (IFCAP_TXCSUM | IFCAP_TXCSUM_IPV6); 818 while (npkt_remaining) { 819 reclaimed += reclaim_nm_tx_desc(nm_txq); 820 ndesc_remaining = contiguous_ndesc_available(nm_txq); 821 /* Can't run out of descriptors with packets still remaining */ 822 MPASS(ndesc_remaining > 0); 823 824 /* # of desc needed to tx all remaining packets */ 825 d = (npkt_remaining / MAX_NPKT_IN_TYPE1_WR) * SGE_MAX_WR_NDESC; 826 if (npkt_remaining % MAX_NPKT_IN_TYPE1_WR) 827 d += npkt_to_ndesc(npkt_remaining % MAX_NPKT_IN_TYPE1_WR); 828 829 if (d <= ndesc_remaining) 830 n = npkt_remaining; 831 else { 832 /* Can't send all, calculate how many can be sent */ 833 n = (ndesc_remaining / SGE_MAX_WR_NDESC) * 834 MAX_NPKT_IN_TYPE1_WR; 835 if (ndesc_remaining % SGE_MAX_WR_NDESC) 836 n += ndesc_to_npkt(ndesc_remaining % SGE_MAX_WR_NDESC); 837 } 838 839 /* Send n packets and update nm_txq->pidx and kring->nr_hwcur */ 840 npkt_remaining -= n; 841 cxgbe_nm_tx(sc, nm_txq, kring, n, npkt_remaining, txcsum); 842 } 843 MPASS(npkt_remaining == 0); 844 MPASS(kring->nr_hwcur == head); 845 MPASS(nm_txq->dbidx == nm_txq->pidx); 846 847 /* 848 * Second part: reclaim buffers for completed transmissions. 849 */ 850 if (reclaimed || flags & NAF_FORCE_RECLAIM || nm_kr_txempty(kring)) { 851 reclaimed += reclaim_nm_tx_desc(nm_txq); 852 kring->nr_hwtail += reclaimed; 853 if (kring->nr_hwtail >= kring->nkr_num_slots) 854 kring->nr_hwtail -= kring->nkr_num_slots; 855 } 856 857 return (0); 858 } 859 860 static int 861 cxgbe_netmap_rxsync(struct netmap_kring *kring, int flags) 862 { 863 struct netmap_adapter *na = kring->na; 864 struct netmap_ring *ring = kring->ring; 865 struct ifnet *ifp = na->ifp; 866 struct vi_info *vi = ifp->if_softc; 867 struct adapter *sc = vi->pi->adapter; 868 struct sge_nm_rxq *nm_rxq = &sc->sge.nm_rxq[vi->first_nm_rxq + kring->ring_id]; 869 u_int const head = kring->rhead; 870 u_int n; 871 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 872 873 if (black_hole) 874 return (0); /* No updates ever. */ 875 876 if (netmap_no_pendintr || force_update) { 877 kring->nr_hwtail = atomic_load_acq_32(&nm_rxq->fl_cidx); 878 kring->nr_kflags &= ~NKR_PENDINTR; 879 } 880 881 if (nm_rxq->fl_db_saved > 0 && starve_fl == 0) { 882 wmb(); 883 t4_write_reg(sc, sc->sge_kdoorbell_reg, 884 nm_rxq->fl_db_val | V_PIDX(nm_rxq->fl_db_saved)); 885 nm_rxq->fl_db_saved = 0; 886 } 887 888 /* Userspace done with buffers from kring->nr_hwcur to head */ 889 n = head >= kring->nr_hwcur ? head - kring->nr_hwcur : 890 kring->nkr_num_slots - kring->nr_hwcur + head; 891 n &= ~7U; 892 if (n > 0) { 893 u_int fl_pidx = nm_rxq->fl_pidx; 894 struct netmap_slot *slot = &ring->slot[fl_pidx]; 895 uint64_t ba; 896 int i, dbinc = 0, hwidx = nm_rxq->fl_hwidx; 897 898 /* 899 * We always deal with 8 buffers at a time. We must have 900 * stopped at an 8B boundary (fl_pidx) last time around and we 901 * must have a multiple of 8B buffers to give to the freelist. 902 */ 903 MPASS((fl_pidx & 7) == 0); 904 MPASS((n & 7) == 0); 905 906 IDXINCR(kring->nr_hwcur, n, kring->nkr_num_slots); 907 IDXINCR(nm_rxq->fl_pidx, n, nm_rxq->fl_sidx); 908 909 while (n > 0) { 910 for (i = 0; i < 8; i++, fl_pidx++, slot++) { 911 PNMB(na, slot, &ba); 912 MPASS(ba != 0); 913 nm_rxq->fl_desc[fl_pidx] = htobe64(ba | hwidx); 914 slot->flags &= ~NS_BUF_CHANGED; 915 MPASS(fl_pidx <= nm_rxq->fl_sidx); 916 } 917 n -= 8; 918 if (fl_pidx == nm_rxq->fl_sidx) { 919 fl_pidx = 0; 920 slot = &ring->slot[0]; 921 } 922 if (++dbinc == 8 && n >= 32) { 923 wmb(); 924 if (starve_fl) 925 nm_rxq->fl_db_saved += dbinc; 926 else { 927 t4_write_reg(sc, sc->sge_kdoorbell_reg, 928 nm_rxq->fl_db_val | V_PIDX(dbinc)); 929 } 930 dbinc = 0; 931 } 932 } 933 MPASS(nm_rxq->fl_pidx == fl_pidx); 934 935 if (dbinc > 0) { 936 wmb(); 937 if (starve_fl) 938 nm_rxq->fl_db_saved += dbinc; 939 else { 940 t4_write_reg(sc, sc->sge_kdoorbell_reg, 941 nm_rxq->fl_db_val | V_PIDX(dbinc)); 942 } 943 } 944 } 945 946 return (0); 947 } 948 949 void 950 cxgbe_nm_attach(struct vi_info *vi) 951 { 952 struct port_info *pi; 953 struct adapter *sc; 954 struct netmap_adapter na; 955 956 MPASS(vi->nnmrxq > 0); 957 MPASS(vi->ifp != NULL); 958 959 pi = vi->pi; 960 sc = pi->adapter; 961 962 bzero(&na, sizeof(na)); 963 964 na.ifp = vi->ifp; 965 na.na_flags = NAF_BDG_MAYSLEEP; 966 967 /* Netmap doesn't know about the space reserved for the status page. */ 968 na.num_tx_desc = vi->qsize_txq - sc->params.sge.spg_len / EQ_ESIZE; 969 970 /* 971 * The freelist's cidx/pidx drives netmap's rx cidx/pidx. So 972 * num_rx_desc is based on the number of buffers that can be held in the 973 * freelist, and not the number of entries in the iq. (These two are 974 * not exactly the same due to the space taken up by the status page). 975 */ 976 na.num_rx_desc = rounddown(vi->qsize_rxq, 8); 977 na.nm_txsync = cxgbe_netmap_txsync; 978 na.nm_rxsync = cxgbe_netmap_rxsync; 979 na.nm_register = cxgbe_netmap_reg; 980 na.num_tx_rings = vi->nnmtxq; 981 na.num_rx_rings = vi->nnmrxq; 982 netmap_attach(&na); 983 } 984 985 void 986 cxgbe_nm_detach(struct vi_info *vi) 987 { 988 989 MPASS(vi->nnmrxq > 0); 990 MPASS(vi->ifp != NULL); 991 992 netmap_detach(vi->ifp); 993 } 994 995 static inline const void * 996 unwrap_nm_fw6_msg(const struct cpl_fw6_msg *cpl) 997 { 998 999 MPASS(cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL); 1000 1001 /* data[0] is RSS header */ 1002 return (&cpl->data[1]); 1003 } 1004 1005 static void 1006 handle_nm_sge_egr_update(struct adapter *sc, struct ifnet *ifp, 1007 const struct cpl_sge_egr_update *egr) 1008 { 1009 uint32_t oq; 1010 struct sge_nm_txq *nm_txq; 1011 1012 oq = be32toh(egr->opcode_qid); 1013 MPASS(G_CPL_OPCODE(oq) == CPL_SGE_EGR_UPDATE); 1014 nm_txq = (void *)sc->sge.eqmap[G_EGR_QID(oq) - sc->sge.eq_start]; 1015 1016 netmap_tx_irq(ifp, nm_txq->nid); 1017 } 1018 1019 void 1020 service_nm_rxq(struct sge_nm_rxq *nm_rxq) 1021 { 1022 struct vi_info *vi = nm_rxq->vi; 1023 struct adapter *sc = vi->pi->adapter; 1024 struct ifnet *ifp = vi->ifp; 1025 struct netmap_adapter *na = NA(ifp); 1026 struct netmap_kring *kring = na->rx_rings[nm_rxq->nid]; 1027 struct netmap_ring *ring = kring->ring; 1028 struct iq_desc *d = &nm_rxq->iq_desc[nm_rxq->iq_cidx]; 1029 const void *cpl; 1030 uint32_t lq; 1031 u_int work = 0; 1032 uint8_t opcode; 1033 uint32_t fl_cidx = atomic_load_acq_32(&nm_rxq->fl_cidx); 1034 u_int fl_credits = fl_cidx & 7; 1035 u_int ndesc = 0; /* desc processed since last cidx update */ 1036 u_int nframes = 0; /* frames processed since last netmap wakeup */ 1037 1038 while ((d->rsp.u.type_gen & F_RSPD_GEN) == nm_rxq->iq_gen) { 1039 1040 rmb(); 1041 1042 lq = be32toh(d->rsp.pldbuflen_qid); 1043 opcode = d->rss.opcode; 1044 cpl = &d->cpl[0]; 1045 1046 switch (G_RSPD_TYPE(d->rsp.u.type_gen)) { 1047 case X_RSPD_TYPE_FLBUF: 1048 1049 /* fall through */ 1050 1051 case X_RSPD_TYPE_CPL: 1052 MPASS(opcode < NUM_CPL_CMDS); 1053 1054 switch (opcode) { 1055 case CPL_FW4_MSG: 1056 case CPL_FW6_MSG: 1057 cpl = unwrap_nm_fw6_msg(cpl); 1058 /* fall through */ 1059 case CPL_SGE_EGR_UPDATE: 1060 handle_nm_sge_egr_update(sc, ifp, cpl); 1061 break; 1062 case CPL_RX_PKT: 1063 ring->slot[fl_cidx].len = G_RSPD_LEN(lq) - 1064 sc->params.sge.fl_pktshift; 1065 ring->slot[fl_cidx].flags = 0; 1066 nframes++; 1067 if (!(lq & F_RSPD_NEWBUF)) { 1068 MPASS(black_hole == 2); 1069 break; 1070 } 1071 fl_credits++; 1072 if (__predict_false(++fl_cidx == nm_rxq->fl_sidx)) 1073 fl_cidx = 0; 1074 break; 1075 default: 1076 panic("%s: unexpected opcode 0x%x on nm_rxq %p", 1077 __func__, opcode, nm_rxq); 1078 } 1079 break; 1080 1081 case X_RSPD_TYPE_INTR: 1082 /* Not equipped to handle forwarded interrupts. */ 1083 panic("%s: netmap queue received interrupt for iq %u\n", 1084 __func__, lq); 1085 1086 default: 1087 panic("%s: illegal response type %d on nm_rxq %p", 1088 __func__, G_RSPD_TYPE(d->rsp.u.type_gen), nm_rxq); 1089 } 1090 1091 d++; 1092 if (__predict_false(++nm_rxq->iq_cidx == nm_rxq->iq_sidx)) { 1093 nm_rxq->iq_cidx = 0; 1094 d = &nm_rxq->iq_desc[0]; 1095 nm_rxq->iq_gen ^= F_RSPD_GEN; 1096 } 1097 1098 if (__predict_false(++nframes == rx_nframes) && !black_hole) { 1099 atomic_store_rel_32(&nm_rxq->fl_cidx, fl_cidx); 1100 netmap_rx_irq(ifp, nm_rxq->nid, &work); 1101 nframes = 0; 1102 } 1103 1104 if (__predict_false(++ndesc == rx_ndesc)) { 1105 if (black_hole && fl_credits >= 8) { 1106 fl_credits /= 8; 1107 IDXINCR(nm_rxq->fl_pidx, fl_credits * 8, 1108 nm_rxq->fl_sidx); 1109 t4_write_reg(sc, sc->sge_kdoorbell_reg, 1110 nm_rxq->fl_db_val | V_PIDX(fl_credits)); 1111 fl_credits = fl_cidx & 7; 1112 } 1113 t4_write_reg(sc, sc->sge_gts_reg, 1114 V_CIDXINC(ndesc) | 1115 V_INGRESSQID(nm_rxq->iq_cntxt_id) | 1116 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); 1117 ndesc = 0; 1118 } 1119 } 1120 1121 atomic_store_rel_32(&nm_rxq->fl_cidx, fl_cidx); 1122 if (black_hole) { 1123 fl_credits /= 8; 1124 IDXINCR(nm_rxq->fl_pidx, fl_credits * 8, nm_rxq->fl_sidx); 1125 t4_write_reg(sc, sc->sge_kdoorbell_reg, 1126 nm_rxq->fl_db_val | V_PIDX(fl_credits)); 1127 } else if (nframes > 0) 1128 netmap_rx_irq(ifp, nm_rxq->nid, &work); 1129 1130 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndesc) | 1131 V_INGRESSQID((u32)nm_rxq->iq_cntxt_id) | 1132 V_SEINTARM(V_QINTR_TIMER_IDX(holdoff_tmr_idx))); 1133 } 1134 #endif 1135