1 /*- 2 * Copyright (c) 2014 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 34 #ifdef DEV_NETMAP 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/eventhandler.h> 38 #include <sys/lock.h> 39 #include <sys/mbuf.h> 40 #include <sys/module.h> 41 #include <sys/selinfo.h> 42 #include <sys/socket.h> 43 #include <sys/sockio.h> 44 #include <machine/bus.h> 45 #include <net/ethernet.h> 46 #include <net/if.h> 47 #include <net/if_media.h> 48 #include <net/if_var.h> 49 #include <net/if_clone.h> 50 #include <net/if_types.h> 51 #include <net/netmap.h> 52 #include <dev/netmap/netmap_kern.h> 53 54 #include "common/common.h" 55 #include "common/t4_regs.h" 56 #include "common/t4_regs_values.h" 57 58 extern int fl_pad; /* XXXNM */ 59 60 /* 61 * 0 = normal netmap rx 62 * 1 = black hole 63 * 2 = supermassive black hole (buffer packing enabled) 64 */ 65 int black_hole = 0; 66 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_black_hole, CTLFLAG_RWTUN, &black_hole, 0, 67 "Sink incoming packets."); 68 69 int rx_ndesc = 256; 70 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_rx_ndesc, CTLFLAG_RWTUN, 71 &rx_ndesc, 0, "# of rx descriptors after which the hw cidx is updated."); 72 73 int rx_nframes = 64; 74 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_rx_nframes, CTLFLAG_RWTUN, 75 &rx_nframes, 0, "max # of frames received before waking up netmap rx."); 76 77 int holdoff_tmr_idx = 2; 78 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_holdoff_tmr_idx, CTLFLAG_RWTUN, 79 &holdoff_tmr_idx, 0, "Holdoff timer index for netmap rx queues."); 80 81 /* 82 * Congestion drops. 83 * -1: no congestion feedback (not recommended). 84 * 0: backpressure the channel instead of dropping packets right away. 85 * 1: no backpressure, drop packets for the congested queue immediately. 86 */ 87 static int nm_cong_drop = 1; 88 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_cong_drop, CTLFLAG_RWTUN, 89 &nm_cong_drop, 0, 90 "Congestion control for netmap rx queues (0 = backpressure, 1 = drop"); 91 92 int starve_fl = 0; 93 SYSCTL_INT(_hw_cxgbe, OID_AUTO, starve_fl, CTLFLAG_RWTUN, 94 &starve_fl, 0, "Don't ring fl db for netmap rx queues."); 95 96 /* 97 * Try to process tx credits in bulk. This may cause a delay in the return of 98 * tx credits and is suitable for bursty or non-stop tx only. 99 */ 100 int lazy_tx_credit_flush = 1; 101 SYSCTL_INT(_hw_cxgbe, OID_AUTO, lazy_tx_credit_flush, CTLFLAG_RWTUN, 102 &lazy_tx_credit_flush, 0, "lazy credit flush for netmap tx queues."); 103 104 /* 105 * Split the netmap rx queues into two groups that populate separate halves of 106 * the RSS indirection table. This allows filters with hashmask to steer to a 107 * particular group of queues. 108 */ 109 static int nm_split_rss = 0; 110 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_split_rss, CTLFLAG_RWTUN, 111 &nm_split_rss, 0, "Split the netmap rx queues into two groups."); 112 113 /* 114 * netmap(4) says "netmap does not use features such as checksum offloading, TCP 115 * segmentation offloading, encryption, VLAN encapsulation/decapsulation, etc." 116 * but this knob can be used to get the hardware to checksum all tx traffic 117 * anyway. 118 */ 119 static int nm_txcsum = 0; 120 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_txcsum, CTLFLAG_RWTUN, 121 &nm_txcsum, 0, "Enable transmit checksum offloading."); 122 123 static int free_nm_rxq_hwq(struct vi_info *, struct sge_nm_rxq *); 124 static int free_nm_txq_hwq(struct vi_info *, struct sge_nm_txq *); 125 126 int 127 alloc_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq, int intr_idx, 128 int idx, struct sysctl_oid *oid) 129 { 130 int rc; 131 struct sysctl_oid_list *children; 132 struct sysctl_ctx_list *ctx; 133 char name[16]; 134 size_t len; 135 struct adapter *sc = vi->adapter; 136 struct netmap_adapter *na = NA(vi->ifp); 137 138 MPASS(na != NULL); 139 140 len = vi->qsize_rxq * IQ_ESIZE; 141 rc = alloc_ring(sc, len, &nm_rxq->iq_desc_tag, &nm_rxq->iq_desc_map, 142 &nm_rxq->iq_ba, (void **)&nm_rxq->iq_desc); 143 if (rc != 0) 144 return (rc); 145 146 len = na->num_rx_desc * EQ_ESIZE + sc->params.sge.spg_len; 147 rc = alloc_ring(sc, len, &nm_rxq->fl_desc_tag, &nm_rxq->fl_desc_map, 148 &nm_rxq->fl_ba, (void **)&nm_rxq->fl_desc); 149 if (rc != 0) 150 return (rc); 151 152 nm_rxq->vi = vi; 153 nm_rxq->nid = idx; 154 nm_rxq->iq_cidx = 0; 155 nm_rxq->iq_sidx = vi->qsize_rxq - sc->params.sge.spg_len / IQ_ESIZE; 156 nm_rxq->iq_gen = F_RSPD_GEN; 157 nm_rxq->fl_pidx = nm_rxq->fl_cidx = 0; 158 nm_rxq->fl_sidx = na->num_rx_desc; 159 nm_rxq->fl_sidx2 = nm_rxq->fl_sidx; /* copy for rxsync cacheline */ 160 nm_rxq->intr_idx = intr_idx; 161 nm_rxq->iq_cntxt_id = INVALID_NM_RXQ_CNTXT_ID; 162 163 ctx = &vi->ctx; 164 children = SYSCTL_CHILDREN(oid); 165 166 snprintf(name, sizeof(name), "%d", idx); 167 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, name, 168 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "rx queue"); 169 children = SYSCTL_CHILDREN(oid); 170 171 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "abs_id", 172 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, &nm_rxq->iq_abs_id, 173 0, sysctl_uint16, "I", "absolute id of the queue"); 174 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 175 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, &nm_rxq->iq_cntxt_id, 176 0, sysctl_uint16, "I", "SGE context id of the queue"); 177 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx", 178 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, &nm_rxq->iq_cidx, 0, 179 sysctl_uint16, "I", "consumer index"); 180 181 children = SYSCTL_CHILDREN(oid); 182 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", 183 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "freelist"); 184 children = SYSCTL_CHILDREN(oid); 185 186 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 187 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, &nm_rxq->fl_cntxt_id, 188 0, sysctl_uint16, "I", "SGE context id of the freelist"); 189 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, 190 &nm_rxq->fl_cidx, 0, "consumer index"); 191 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, 192 &nm_rxq->fl_pidx, 0, "producer index"); 193 194 return (rc); 195 } 196 197 int 198 free_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq) 199 { 200 struct adapter *sc = vi->adapter; 201 202 if (!(vi->flags & VI_INIT_DONE)) 203 return (0); 204 205 if (nm_rxq->iq_cntxt_id != INVALID_NM_RXQ_CNTXT_ID) 206 free_nm_rxq_hwq(vi, nm_rxq); 207 MPASS(nm_rxq->iq_cntxt_id == INVALID_NM_RXQ_CNTXT_ID); 208 209 free_ring(sc, nm_rxq->iq_desc_tag, nm_rxq->iq_desc_map, nm_rxq->iq_ba, 210 nm_rxq->iq_desc); 211 free_ring(sc, nm_rxq->fl_desc_tag, nm_rxq->fl_desc_map, nm_rxq->fl_ba, 212 nm_rxq->fl_desc); 213 214 return (0); 215 } 216 217 int 218 alloc_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq, int iqidx, int idx, 219 struct sysctl_oid *oid) 220 { 221 int rc; 222 size_t len; 223 struct port_info *pi = vi->pi; 224 struct adapter *sc = pi->adapter; 225 struct netmap_adapter *na = NA(vi->ifp); 226 char name[16]; 227 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 228 229 len = na->num_tx_desc * EQ_ESIZE + sc->params.sge.spg_len; 230 rc = alloc_ring(sc, len, &nm_txq->desc_tag, &nm_txq->desc_map, 231 &nm_txq->ba, (void **)&nm_txq->desc); 232 if (rc) 233 return (rc); 234 235 nm_txq->pidx = nm_txq->cidx = 0; 236 nm_txq->sidx = na->num_tx_desc; 237 nm_txq->nid = idx; 238 nm_txq->iqidx = iqidx; 239 nm_txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) | 240 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(sc->pf) | 241 V_TXPKT_VF(vi->vin) | V_TXPKT_VF_VLD(vi->vfvld)); 242 if (sc->params.fw_vers >= FW_VERSION32(1, 24, 11, 0)) 243 nm_txq->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS2_WR)); 244 else 245 nm_txq->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR)); 246 nm_txq->cntxt_id = INVALID_NM_TXQ_CNTXT_ID; 247 248 snprintf(name, sizeof(name), "%d", idx); 249 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, 250 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "netmap tx queue"); 251 children = SYSCTL_CHILDREN(oid); 252 253 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 254 &nm_txq->cntxt_id, 0, "SGE context id of the queue"); 255 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx", 256 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, &nm_txq->cidx, 0, 257 sysctl_uint16, "I", "consumer index"); 258 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "pidx", 259 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, &nm_txq->pidx, 0, 260 sysctl_uint16, "I", "producer index"); 261 262 return (rc); 263 } 264 265 int 266 free_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq) 267 { 268 struct adapter *sc = vi->adapter; 269 270 if (!(vi->flags & VI_INIT_DONE)) 271 return (0); 272 273 if (nm_txq->cntxt_id != INVALID_NM_TXQ_CNTXT_ID) 274 free_nm_txq_hwq(vi, nm_txq); 275 MPASS(nm_txq->cntxt_id == INVALID_NM_TXQ_CNTXT_ID); 276 277 free_ring(sc, nm_txq->desc_tag, nm_txq->desc_map, nm_txq->ba, 278 nm_txq->desc); 279 280 return (0); 281 } 282 283 static int 284 alloc_nm_rxq_hwq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq, int cong) 285 { 286 int rc, cntxt_id, i; 287 __be32 v; 288 struct adapter *sc = vi->adapter; 289 struct sge_params *sp = &sc->params.sge; 290 struct netmap_adapter *na = NA(vi->ifp); 291 struct fw_iq_cmd c; 292 293 MPASS(na != NULL); 294 MPASS(nm_rxq->iq_desc != NULL); 295 MPASS(nm_rxq->fl_desc != NULL); 296 297 bzero(nm_rxq->iq_desc, vi->qsize_rxq * IQ_ESIZE); 298 bzero(nm_rxq->fl_desc, na->num_rx_desc * EQ_ESIZE + sp->spg_len); 299 300 bzero(&c, sizeof(c)); 301 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 302 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) | 303 V_FW_IQ_CMD_VFN(0)); 304 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_IQSTART | FW_LEN16(c)); 305 if (nm_rxq->iq_cntxt_id == INVALID_NM_RXQ_CNTXT_ID) 306 c.alloc_to_len16 |= htobe32(F_FW_IQ_CMD_ALLOC); 307 else { 308 c.iqid = htobe16(nm_rxq->iq_cntxt_id); 309 c.fl0id = htobe16(nm_rxq->fl_cntxt_id); 310 c.fl1id = htobe16(0xffff); 311 c.physiqid = htobe16(nm_rxq->iq_abs_id); 312 } 313 MPASS(!forwarding_intr_to_fwq(sc)); 314 KASSERT(nm_rxq->intr_idx < sc->intr_count, 315 ("%s: invalid direct intr_idx %d", __func__, nm_rxq->intr_idx)); 316 v = V_FW_IQ_CMD_IQANDSTINDEX(nm_rxq->intr_idx); 317 c.type_to_iqandstindex = htobe32(v | 318 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) | 319 V_FW_IQ_CMD_VIID(vi->viid) | 320 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT)); 321 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(vi->pi->tx_chan) | 322 F_FW_IQ_CMD_IQGTSMODE | 323 V_FW_IQ_CMD_IQINTCNTTHRESH(0) | 324 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4)); 325 c.iqsize = htobe16(vi->qsize_rxq); 326 c.iqaddr = htobe64(nm_rxq->iq_ba); 327 if (cong >= 0) { 328 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN | 329 V_FW_IQ_CMD_FL0CNGCHMAP(cong) | F_FW_IQ_CMD_FL0CONGCIF | 330 F_FW_IQ_CMD_FL0CONGEN); 331 } 332 c.iqns_to_fl0congen |= 333 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) | 334 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO | 335 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) | 336 (black_hole == 2 ? F_FW_IQ_CMD_FL0PACKEN : 0)); 337 c.fl0dcaen_to_fl0cidxfthresh = 338 htobe16(V_FW_IQ_CMD_FL0FBMIN(chip_id(sc) <= CHELSIO_T5 ? 339 X_FETCHBURSTMIN_128B : X_FETCHBURSTMIN_64B_T6) | 340 V_FW_IQ_CMD_FL0FBMAX(chip_id(sc) <= CHELSIO_T5 ? 341 X_FETCHBURSTMAX_512B : X_FETCHBURSTMAX_256B)); 342 c.fl0size = htobe16(na->num_rx_desc / 8 + sp->spg_len / EQ_ESIZE); 343 c.fl0addr = htobe64(nm_rxq->fl_ba); 344 345 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 346 if (rc != 0) { 347 device_printf(sc->dev, 348 "failed to create netmap ingress queue: %d\n", rc); 349 return (rc); 350 } 351 352 nm_rxq->iq_cidx = 0; 353 MPASS(nm_rxq->iq_sidx == vi->qsize_rxq - sp->spg_len / IQ_ESIZE); 354 nm_rxq->iq_gen = F_RSPD_GEN; 355 nm_rxq->iq_cntxt_id = be16toh(c.iqid); 356 nm_rxq->iq_abs_id = be16toh(c.physiqid); 357 cntxt_id = nm_rxq->iq_cntxt_id - sc->sge.iq_start; 358 if (cntxt_id >= sc->sge.iqmap_sz) { 359 panic ("%s: nm_rxq->iq_cntxt_id (%d) more than the max (%d)", 360 __func__, cntxt_id, sc->sge.iqmap_sz - 1); 361 } 362 sc->sge.iqmap[cntxt_id] = (void *)nm_rxq; 363 364 nm_rxq->fl_cntxt_id = be16toh(c.fl0id); 365 nm_rxq->fl_pidx = nm_rxq->fl_cidx = 0; 366 nm_rxq->fl_db_saved = 0; 367 /* matches the X_FETCHBURSTMAX_512B or X_FETCHBURSTMAX_256B above. */ 368 nm_rxq->fl_db_threshold = chip_id(sc) <= CHELSIO_T5 ? 8 : 4; 369 MPASS(nm_rxq->fl_sidx == na->num_rx_desc); 370 cntxt_id = nm_rxq->fl_cntxt_id - sc->sge.eq_start; 371 if (cntxt_id >= sc->sge.eqmap_sz) { 372 panic("%s: nm_rxq->fl_cntxt_id (%d) more than the max (%d)", 373 __func__, cntxt_id, sc->sge.eqmap_sz - 1); 374 } 375 sc->sge.eqmap[cntxt_id] = (void *)nm_rxq; 376 377 nm_rxq->fl_db_val = V_QID(nm_rxq->fl_cntxt_id) | 378 sc->chip_params->sge_fl_db; 379 380 if (chip_id(sc) >= CHELSIO_T5 && cong >= 0) { 381 uint32_t param, val; 382 383 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 384 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) | 385 V_FW_PARAMS_PARAM_YZ(nm_rxq->iq_cntxt_id); 386 if (cong == 0) 387 val = 1 << 19; 388 else { 389 val = 2 << 19; 390 for (i = 0; i < 4; i++) { 391 if (cong & (1 << i)) 392 val |= 1 << (i << 2); 393 } 394 } 395 396 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 397 if (rc != 0) { 398 /* report error but carry on */ 399 device_printf(sc->dev, 400 "failed to set congestion manager context for " 401 "ingress queue %d: %d\n", nm_rxq->iq_cntxt_id, rc); 402 } 403 } 404 405 t4_write_reg(sc, sc->sge_gts_reg, 406 V_INGRESSQID(nm_rxq->iq_cntxt_id) | 407 V_SEINTARM(V_QINTR_TIMER_IDX(holdoff_tmr_idx))); 408 409 return (rc); 410 } 411 412 static int 413 free_nm_rxq_hwq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq) 414 { 415 struct adapter *sc = vi->adapter; 416 int rc; 417 418 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0, FW_IQ_TYPE_FL_INT_CAP, 419 nm_rxq->iq_cntxt_id, nm_rxq->fl_cntxt_id, 0xffff); 420 if (rc != 0) 421 device_printf(sc->dev, "%s: failed for iq %d, fl %d: %d\n", 422 __func__, nm_rxq->iq_cntxt_id, nm_rxq->fl_cntxt_id, rc); 423 nm_rxq->iq_cntxt_id = INVALID_NM_RXQ_CNTXT_ID; 424 return (rc); 425 } 426 427 static int 428 alloc_nm_txq_hwq(struct vi_info *vi, struct sge_nm_txq *nm_txq) 429 { 430 int rc, cntxt_id; 431 size_t len; 432 struct adapter *sc = vi->adapter; 433 struct netmap_adapter *na = NA(vi->ifp); 434 struct fw_eq_eth_cmd c; 435 436 MPASS(na != NULL); 437 MPASS(nm_txq->desc != NULL); 438 439 len = na->num_tx_desc * EQ_ESIZE + sc->params.sge.spg_len; 440 bzero(nm_txq->desc, len); 441 442 bzero(&c, sizeof(c)); 443 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST | 444 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) | 445 V_FW_EQ_ETH_CMD_VFN(0)); 446 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c)); 447 if (nm_txq->cntxt_id == INVALID_NM_TXQ_CNTXT_ID) 448 c.alloc_to_len16 |= htobe32(F_FW_EQ_ETH_CMD_ALLOC); 449 else 450 c.eqid_pkd = htobe32(V_FW_EQ_ETH_CMD_EQID(nm_txq->cntxt_id)); 451 c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE | 452 F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(vi->viid)); 453 c.fetchszm_to_iqid = 454 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) | 455 V_FW_EQ_ETH_CMD_PCIECHN(vi->pi->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO | 456 V_FW_EQ_ETH_CMD_IQID(sc->sge.nm_rxq[nm_txq->iqidx].iq_cntxt_id)); 457 c.dcaen_to_eqsize = 458 htobe32(V_FW_EQ_ETH_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ? 459 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) | 460 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 461 V_FW_EQ_ETH_CMD_EQSIZE(len / EQ_ESIZE)); 462 c.eqaddr = htobe64(nm_txq->ba); 463 464 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 465 if (rc != 0) { 466 device_printf(vi->dev, 467 "failed to create netmap egress queue: %d\n", rc); 468 return (rc); 469 } 470 471 nm_txq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd)); 472 cntxt_id = nm_txq->cntxt_id - sc->sge.eq_start; 473 if (cntxt_id >= sc->sge.eqmap_sz) 474 panic("%s: nm_txq->cntxt_id (%d) more than the max (%d)", __func__, 475 cntxt_id, sc->sge.eqmap_sz - 1); 476 sc->sge.eqmap[cntxt_id] = (void *)nm_txq; 477 478 nm_txq->pidx = nm_txq->cidx = 0; 479 MPASS(nm_txq->sidx == na->num_tx_desc); 480 nm_txq->equiqidx = nm_txq->equeqidx = nm_txq->dbidx = 0; 481 482 nm_txq->doorbells = sc->doorbells; 483 if (isset(&nm_txq->doorbells, DOORBELL_UDB) || 484 isset(&nm_txq->doorbells, DOORBELL_UDBWC) || 485 isset(&nm_txq->doorbells, DOORBELL_WCWR)) { 486 uint32_t s_qpp = sc->params.sge.eq_s_qpp; 487 uint32_t mask = (1 << s_qpp) - 1; 488 volatile uint8_t *udb; 489 490 udb = sc->udbs_base + UDBS_DB_OFFSET; 491 udb += (nm_txq->cntxt_id >> s_qpp) << PAGE_SHIFT; 492 nm_txq->udb_qid = nm_txq->cntxt_id & mask; 493 if (nm_txq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE) 494 clrbit(&nm_txq->doorbells, DOORBELL_WCWR); 495 else { 496 udb += nm_txq->udb_qid << UDBS_SEG_SHIFT; 497 nm_txq->udb_qid = 0; 498 } 499 nm_txq->udb = (volatile void *)udb; 500 } 501 502 if (sc->params.fw_vers < FW_VERSION32(1, 25, 1, 0)) { 503 uint32_t param, val; 504 505 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 506 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH) | 507 V_FW_PARAMS_PARAM_YZ(nm_txq->cntxt_id); 508 val = 0xff; 509 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 510 if (rc != 0) { 511 device_printf(vi->dev, 512 "failed to bind netmap txq %d to class 0xff: %d\n", 513 nm_txq->cntxt_id, rc); 514 rc = 0; 515 } 516 } 517 518 return (rc); 519 } 520 521 static int 522 free_nm_txq_hwq(struct vi_info *vi, struct sge_nm_txq *nm_txq) 523 { 524 struct adapter *sc = vi->adapter; 525 int rc; 526 527 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0, nm_txq->cntxt_id); 528 if (rc != 0) 529 device_printf(sc->dev, "%s: failed for eq %d: %d\n", __func__, 530 nm_txq->cntxt_id, rc); 531 nm_txq->cntxt_id = INVALID_NM_TXQ_CNTXT_ID; 532 return (rc); 533 } 534 535 static int 536 cxgbe_netmap_simple_rss(struct adapter *sc, struct vi_info *vi, 537 struct ifnet *ifp, struct netmap_adapter *na) 538 { 539 struct netmap_kring *kring; 540 struct sge_nm_rxq *nm_rxq; 541 int rc, i, j, nm_state, defq; 542 uint16_t *rss; 543 544 /* 545 * Check if there's at least one active (or about to go active) netmap 546 * rx queue. 547 */ 548 defq = -1; 549 for_each_nm_rxq(vi, j, nm_rxq) { 550 nm_state = atomic_load_int(&nm_rxq->nm_state); 551 kring = na->rx_rings[nm_rxq->nid]; 552 if ((nm_state != NM_OFF && !nm_kring_pending_off(kring)) || 553 (nm_state == NM_OFF && nm_kring_pending_on(kring))) { 554 MPASS(nm_rxq->iq_cntxt_id != INVALID_NM_RXQ_CNTXT_ID); 555 if (defq == -1) { 556 defq = nm_rxq->iq_abs_id; 557 break; 558 } 559 } 560 } 561 562 if (defq == -1) { 563 /* No active netmap queues. Switch back to NIC queues. */ 564 rss = vi->rss; 565 defq = vi->rss[0]; 566 } else { 567 for (i = 0; i < vi->rss_size;) { 568 for_each_nm_rxq(vi, j, nm_rxq) { 569 nm_state = atomic_load_int(&nm_rxq->nm_state); 570 kring = na->rx_rings[nm_rxq->nid]; 571 if ((nm_state != NM_OFF && 572 !nm_kring_pending_off(kring)) || 573 (nm_state == NM_OFF && 574 nm_kring_pending_on(kring))) { 575 MPASS(nm_rxq->iq_cntxt_id != 576 INVALID_NM_RXQ_CNTXT_ID); 577 vi->nm_rss[i++] = nm_rxq->iq_abs_id; 578 if (i == vi->rss_size) 579 break; 580 } 581 } 582 } 583 rss = vi->nm_rss; 584 } 585 586 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, rss, 587 vi->rss_size); 588 if (rc != 0) 589 if_printf(ifp, "netmap rss_config failed: %d\n", rc); 590 591 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, vi->hashen, defq, 0, 0); 592 if (rc != 0) { 593 if_printf(ifp, "netmap defaultq config failed: %d\n", rc); 594 } 595 596 return (rc); 597 } 598 599 /* 600 * Odd number of rx queues work best for split RSS mode as the first queue can 601 * be dedicated for non-RSS traffic and the rest divided into two equal halves. 602 */ 603 static int 604 cxgbe_netmap_split_rss(struct adapter *sc, struct vi_info *vi, 605 struct ifnet *ifp, struct netmap_adapter *na) 606 { 607 struct netmap_kring *kring; 608 struct sge_nm_rxq *nm_rxq; 609 int rc, i, j, nm_state, defq; 610 int nactive[2] = {0, 0}; 611 int dq[2] = {-1, -1}; 612 bool dq_norss; /* default queue should not be in RSS table. */ 613 614 MPASS(nm_split_rss != 0); 615 MPASS(vi->nnmrxq > 1); 616 617 for_each_nm_rxq(vi, i, nm_rxq) { 618 j = i / ((vi->nnmrxq + 1) / 2); 619 nm_state = atomic_load_int(&nm_rxq->nm_state); 620 kring = na->rx_rings[nm_rxq->nid]; 621 if ((nm_state != NM_OFF && !nm_kring_pending_off(kring)) || 622 (nm_state == NM_OFF && nm_kring_pending_on(kring))) { 623 MPASS(nm_rxq->iq_cntxt_id != INVALID_NM_RXQ_CNTXT_ID); 624 nactive[j]++; 625 if (dq[j] == -1) { 626 dq[j] = nm_rxq->iq_abs_id; 627 break; 628 } 629 } 630 } 631 632 if (nactive[0] == 0 || nactive[1] == 0) 633 return (cxgbe_netmap_simple_rss(sc, vi, ifp, na)); 634 635 MPASS(dq[0] != -1 && dq[1] != -1); 636 if (nactive[0] > nactive[1]) { 637 defq = dq[0]; 638 dq_norss = true; 639 } else if (nactive[0] < nactive[1]) { 640 defq = dq[1]; 641 dq_norss = true; 642 } else { 643 defq = dq[0]; 644 dq_norss = false; 645 } 646 647 i = 0; 648 nm_rxq = &sc->sge.nm_rxq[vi->first_nm_rxq]; 649 while (i < vi->rss_size / 2) { 650 for (j = 0; j < (vi->nnmrxq + 1) / 2; j++) { 651 nm_state = atomic_load_int(&nm_rxq[j].nm_state); 652 kring = na->rx_rings[nm_rxq[j].nid]; 653 if ((nm_state == NM_OFF && 654 !nm_kring_pending_on(kring)) || 655 (nm_state == NM_ON && 656 nm_kring_pending_off(kring))) { 657 continue; 658 } 659 MPASS(nm_rxq[j].iq_cntxt_id != INVALID_NM_RXQ_CNTXT_ID); 660 if (dq_norss && defq == nm_rxq[j].iq_abs_id) 661 continue; 662 vi->nm_rss[i++] = nm_rxq[j].iq_abs_id; 663 if (i == vi->rss_size / 2) 664 break; 665 } 666 } 667 while (i < vi->rss_size) { 668 for (j = (vi->nnmrxq + 1) / 2; j < vi->nnmrxq; j++) { 669 nm_state = atomic_load_int(&nm_rxq[j].nm_state); 670 kring = na->rx_rings[nm_rxq[j].nid]; 671 if ((nm_state == NM_OFF && 672 !nm_kring_pending_on(kring)) || 673 (nm_state == NM_ON && 674 nm_kring_pending_off(kring))) { 675 continue; 676 } 677 MPASS(nm_rxq[j].iq_cntxt_id != INVALID_NM_RXQ_CNTXT_ID); 678 if (dq_norss && defq == nm_rxq[j].iq_abs_id) 679 continue; 680 vi->nm_rss[i++] = nm_rxq[j].iq_abs_id; 681 if (i == vi->rss_size) 682 break; 683 } 684 } 685 686 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, 687 vi->nm_rss, vi->rss_size); 688 if (rc != 0) 689 if_printf(ifp, "netmap split_rss_config failed: %d\n", rc); 690 691 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, vi->hashen, defq, 0, 0); 692 if (rc != 0) 693 if_printf(ifp, "netmap defaultq config failed: %d\n", rc); 694 695 return (rc); 696 } 697 698 static inline int 699 cxgbe_netmap_rss(struct adapter *sc, struct vi_info *vi, struct ifnet *ifp, 700 struct netmap_adapter *na) 701 { 702 703 if (nm_split_rss == 0 || vi->nnmrxq == 1) 704 return (cxgbe_netmap_simple_rss(sc, vi, ifp, na)); 705 else 706 return (cxgbe_netmap_split_rss(sc, vi, ifp, na)); 707 } 708 709 static int 710 cxgbe_netmap_on(struct adapter *sc, struct vi_info *vi, struct ifnet *ifp, 711 struct netmap_adapter *na) 712 { 713 struct netmap_slot *slot; 714 struct netmap_kring *kring; 715 struct sge_nm_rxq *nm_rxq; 716 struct sge_nm_txq *nm_txq; 717 int i, j, hwidx; 718 struct rx_buf_info *rxb; 719 720 ASSERT_SYNCHRONIZED_OP(sc); 721 MPASS(vi->nnmrxq > 0); 722 MPASS(vi->nnmtxq > 0); 723 724 if ((vi->flags & VI_INIT_DONE) == 0 || 725 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 726 if_printf(ifp, "cannot enable netmap operation because " 727 "interface is not UP.\n"); 728 return (EAGAIN); 729 } 730 731 rxb = &sc->sge.rx_buf_info[0]; 732 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) { 733 if (rxb->size1 == NETMAP_BUF_SIZE(na)) { 734 hwidx = rxb->hwidx1; 735 break; 736 } 737 if (rxb->size2 == NETMAP_BUF_SIZE(na)) { 738 hwidx = rxb->hwidx2; 739 break; 740 } 741 } 742 if (i >= SW_ZONE_SIZES) { 743 if_printf(ifp, "no hwidx for netmap buffer size %d.\n", 744 NETMAP_BUF_SIZE(na)); 745 return (ENXIO); 746 } 747 748 /* Must set caps before calling netmap_reset */ 749 nm_set_native_flags(na); 750 751 for_each_nm_rxq(vi, i, nm_rxq) { 752 kring = na->rx_rings[nm_rxq->nid]; 753 if (!nm_kring_pending_on(kring)) 754 continue; 755 756 alloc_nm_rxq_hwq(vi, nm_rxq, tnl_cong(vi->pi, nm_cong_drop)); 757 nm_rxq->fl_hwidx = hwidx; 758 slot = netmap_reset(na, NR_RX, i, 0); 759 MPASS(slot != NULL); /* XXXNM: error check, not assert */ 760 761 /* We deal with 8 bufs at a time */ 762 MPASS((na->num_rx_desc & 7) == 0); 763 MPASS(na->num_rx_desc == nm_rxq->fl_sidx); 764 for (j = 0; j < nm_rxq->fl_sidx; j++) { 765 uint64_t ba; 766 767 PNMB(na, &slot[j], &ba); 768 MPASS(ba != 0); 769 nm_rxq->fl_desc[j] = htobe64(ba | hwidx); 770 } 771 j = nm_rxq->fl_pidx = nm_rxq->fl_sidx - 8; 772 MPASS((j & 7) == 0); 773 j /= 8; /* driver pidx to hardware pidx */ 774 wmb(); 775 t4_write_reg(sc, sc->sge_kdoorbell_reg, 776 nm_rxq->fl_db_val | V_PIDX(j)); 777 778 (void) atomic_cmpset_int(&nm_rxq->nm_state, NM_OFF, NM_ON); 779 } 780 781 for_each_nm_txq(vi, i, nm_txq) { 782 kring = na->tx_rings[nm_txq->nid]; 783 if (!nm_kring_pending_on(kring)) 784 continue; 785 786 alloc_nm_txq_hwq(vi, nm_txq); 787 slot = netmap_reset(na, NR_TX, i, 0); 788 MPASS(slot != NULL); /* XXXNM: error check, not assert */ 789 } 790 791 if (vi->nm_rss == NULL) { 792 vi->nm_rss = malloc(vi->rss_size * sizeof(uint16_t), M_CXGBE, 793 M_ZERO | M_WAITOK); 794 } 795 796 return (cxgbe_netmap_rss(sc, vi, ifp, na)); 797 } 798 799 static int 800 cxgbe_netmap_off(struct adapter *sc, struct vi_info *vi, struct ifnet *ifp, 801 struct netmap_adapter *na) 802 { 803 struct netmap_kring *kring; 804 int rc, i, nm_state, nactive; 805 struct sge_nm_txq *nm_txq; 806 struct sge_nm_rxq *nm_rxq; 807 808 ASSERT_SYNCHRONIZED_OP(sc); 809 MPASS(vi->nnmrxq > 0); 810 MPASS(vi->nnmtxq > 0); 811 812 if (!nm_netmap_on(na)) 813 return (0); 814 815 if ((vi->flags & VI_INIT_DONE) == 0) 816 return (0); 817 818 /* First remove the queues that are stopping from the RSS table. */ 819 rc = cxgbe_netmap_rss(sc, vi, ifp, na); 820 if (rc != 0) 821 return (rc); /* error message logged already. */ 822 823 for_each_nm_txq(vi, i, nm_txq) { 824 kring = na->tx_rings[nm_txq->nid]; 825 if (!nm_kring_pending_off(kring)) 826 continue; 827 MPASS(nm_txq->cntxt_id != INVALID_NM_TXQ_CNTXT_ID); 828 829 rc = -t4_eth_eq_stop(sc, sc->mbox, sc->pf, 0, nm_txq->cntxt_id); 830 if (rc != 0) { 831 device_printf(vi->dev, 832 "failed to stop nm_txq[%d]: %d.\n", i, rc); 833 return (rc); 834 } 835 836 /* XXX: netmap, not the driver, should do this. */ 837 kring->rhead = kring->rcur = kring->nr_hwcur = 0; 838 kring->rtail = kring->nr_hwtail = kring->nkr_num_slots - 1; 839 } 840 nactive = 0; 841 for_each_nm_rxq(vi, i, nm_rxq) { 842 nm_state = atomic_load_int(&nm_rxq->nm_state); 843 kring = na->rx_rings[nm_rxq->nid]; 844 if (nm_state != NM_OFF && !nm_kring_pending_off(kring)) 845 nactive++; 846 if (!nm_kring_pending_off(kring)) 847 continue; 848 MPASS(nm_state != NM_OFF); 849 MPASS(nm_rxq->iq_cntxt_id != INVALID_NM_RXQ_CNTXT_ID); 850 851 rc = -t4_iq_stop(sc, sc->mbox, sc->pf, 0, FW_IQ_TYPE_FL_INT_CAP, 852 nm_rxq->iq_cntxt_id, nm_rxq->fl_cntxt_id, 0xffff); 853 if (rc != 0) { 854 device_printf(vi->dev, 855 "failed to stop nm_rxq[%d]: %d.\n", i, rc); 856 return (rc); 857 } 858 859 while (!atomic_cmpset_int(&nm_rxq->nm_state, NM_ON, NM_OFF)) 860 pause("nmst", 1); 861 862 /* XXX: netmap, not the driver, should do this. */ 863 kring->rhead = kring->rcur = kring->nr_hwcur = 0; 864 kring->rtail = kring->nr_hwtail = 0; 865 } 866 netmap_krings_mode_commit(na, 0); 867 if (nactive == 0) 868 nm_clear_native_flags(na); 869 870 return (rc); 871 } 872 873 static int 874 cxgbe_netmap_reg(struct netmap_adapter *na, int on) 875 { 876 struct ifnet *ifp = na->ifp; 877 struct vi_info *vi = ifp->if_softc; 878 struct adapter *sc = vi->adapter; 879 int rc; 880 881 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4nmreg"); 882 if (rc != 0) 883 return (rc); 884 if (on) 885 rc = cxgbe_netmap_on(sc, vi, ifp, na); 886 else 887 rc = cxgbe_netmap_off(sc, vi, ifp, na); 888 end_synchronized_op(sc, 0); 889 890 return (rc); 891 } 892 893 /* How many packets can a single type1 WR carry in n descriptors */ 894 static inline int 895 ndesc_to_npkt(const int n) 896 { 897 898 MPASS(n > 0 && n <= SGE_MAX_WR_NDESC); 899 900 return (n * 2 - 1); 901 } 902 #define MAX_NPKT_IN_TYPE1_WR (ndesc_to_npkt(SGE_MAX_WR_NDESC)) 903 904 /* 905 * Space (in descriptors) needed for a type1 WR (TX_PKTS or TX_PKTS2) that 906 * carries n packets 907 */ 908 static inline int 909 npkt_to_ndesc(const int n) 910 { 911 912 MPASS(n > 0 && n <= MAX_NPKT_IN_TYPE1_WR); 913 914 return ((n + 2) / 2); 915 } 916 917 /* 918 * Space (in 16B units) needed for a type1 WR (TX_PKTS or TX_PKTS2) that 919 * carries n packets 920 */ 921 static inline int 922 npkt_to_len16(const int n) 923 { 924 925 MPASS(n > 0 && n <= MAX_NPKT_IN_TYPE1_WR); 926 927 return (n * 2 + 1); 928 } 929 930 #define NMIDXDIFF(q, idx) IDXDIFF((q)->pidx, (q)->idx, (q)->sidx) 931 932 static void 933 ring_nm_txq_db(struct adapter *sc, struct sge_nm_txq *nm_txq) 934 { 935 int n; 936 u_int db = nm_txq->doorbells; 937 938 MPASS(nm_txq->pidx != nm_txq->dbidx); 939 940 n = NMIDXDIFF(nm_txq, dbidx); 941 if (n > 1) 942 clrbit(&db, DOORBELL_WCWR); 943 wmb(); 944 945 switch (ffs(db) - 1) { 946 case DOORBELL_UDB: 947 *nm_txq->udb = htole32(V_QID(nm_txq->udb_qid) | V_PIDX(n)); 948 break; 949 950 case DOORBELL_WCWR: { 951 volatile uint64_t *dst, *src; 952 953 /* 954 * Queues whose 128B doorbell segment fits in the page do not 955 * use relative qid (udb_qid is always 0). Only queues with 956 * doorbell segments can do WCWR. 957 */ 958 KASSERT(nm_txq->udb_qid == 0 && n == 1, 959 ("%s: inappropriate doorbell (0x%x, %d, %d) for nm_txq %p", 960 __func__, nm_txq->doorbells, n, nm_txq->pidx, nm_txq)); 961 962 dst = (volatile void *)((uintptr_t)nm_txq->udb + 963 UDBS_WR_OFFSET - UDBS_DB_OFFSET); 964 src = (void *)&nm_txq->desc[nm_txq->dbidx]; 965 while (src != (void *)&nm_txq->desc[nm_txq->dbidx + 1]) 966 *dst++ = *src++; 967 wmb(); 968 break; 969 } 970 971 case DOORBELL_UDBWC: 972 *nm_txq->udb = htole32(V_QID(nm_txq->udb_qid) | V_PIDX(n)); 973 wmb(); 974 break; 975 976 case DOORBELL_KDB: 977 t4_write_reg(sc, sc->sge_kdoorbell_reg, 978 V_QID(nm_txq->cntxt_id) | V_PIDX(n)); 979 break; 980 } 981 nm_txq->dbidx = nm_txq->pidx; 982 } 983 984 /* 985 * Write work requests to send 'npkt' frames and ring the doorbell to send them 986 * on their way. No need to check for wraparound. 987 */ 988 static void 989 cxgbe_nm_tx(struct adapter *sc, struct sge_nm_txq *nm_txq, 990 struct netmap_kring *kring, int npkt, int npkt_remaining) 991 { 992 struct netmap_ring *ring = kring->ring; 993 struct netmap_slot *slot; 994 const u_int lim = kring->nkr_num_slots - 1; 995 struct fw_eth_tx_pkts_wr *wr = (void *)&nm_txq->desc[nm_txq->pidx]; 996 uint16_t len; 997 uint64_t ba; 998 struct cpl_tx_pkt_core *cpl; 999 struct ulptx_sgl *usgl; 1000 int i, n; 1001 1002 while (npkt) { 1003 n = min(npkt, MAX_NPKT_IN_TYPE1_WR); 1004 len = 0; 1005 1006 wr = (void *)&nm_txq->desc[nm_txq->pidx]; 1007 wr->op_pkd = nm_txq->op_pkd; 1008 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(npkt_to_len16(n))); 1009 wr->npkt = n; 1010 wr->r3 = 0; 1011 wr->type = 1; 1012 cpl = (void *)(wr + 1); 1013 1014 for (i = 0; i < n; i++) { 1015 slot = &ring->slot[kring->nr_hwcur]; 1016 PNMB(kring->na, slot, &ba); 1017 MPASS(ba != 0); 1018 1019 cpl->ctrl0 = nm_txq->cpl_ctrl0; 1020 cpl->pack = 0; 1021 cpl->len = htobe16(slot->len); 1022 cpl->ctrl1 = nm_txcsum ? 0 : 1023 htobe64(F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS); 1024 1025 usgl = (void *)(cpl + 1); 1026 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 1027 V_ULPTX_NSGE(1)); 1028 usgl->len0 = htobe32(slot->len); 1029 usgl->addr0 = htobe64(ba); 1030 1031 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); 1032 cpl = (void *)(usgl + 1); 1033 MPASS(slot->len + len <= UINT16_MAX); 1034 len += slot->len; 1035 kring->nr_hwcur = nm_next(kring->nr_hwcur, lim); 1036 } 1037 wr->plen = htobe16(len); 1038 1039 npkt -= n; 1040 nm_txq->pidx += npkt_to_ndesc(n); 1041 MPASS(nm_txq->pidx <= nm_txq->sidx); 1042 if (__predict_false(nm_txq->pidx == nm_txq->sidx)) { 1043 /* 1044 * This routine doesn't know how to write WRs that wrap 1045 * around. Make sure it wasn't asked to. 1046 */ 1047 MPASS(npkt == 0); 1048 nm_txq->pidx = 0; 1049 } 1050 1051 if (npkt == 0 && npkt_remaining == 0) { 1052 /* All done. */ 1053 if (lazy_tx_credit_flush == 0) { 1054 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ | 1055 F_FW_WR_EQUIQ); 1056 nm_txq->equeqidx = nm_txq->pidx; 1057 nm_txq->equiqidx = nm_txq->pidx; 1058 } 1059 ring_nm_txq_db(sc, nm_txq); 1060 return; 1061 } 1062 1063 if (NMIDXDIFF(nm_txq, equiqidx) >= nm_txq->sidx / 2) { 1064 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ | 1065 F_FW_WR_EQUIQ); 1066 nm_txq->equeqidx = nm_txq->pidx; 1067 nm_txq->equiqidx = nm_txq->pidx; 1068 } else if (NMIDXDIFF(nm_txq, equeqidx) >= 64) { 1069 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ); 1070 nm_txq->equeqidx = nm_txq->pidx; 1071 } 1072 if (NMIDXDIFF(nm_txq, dbidx) >= 2 * SGE_MAX_WR_NDESC) 1073 ring_nm_txq_db(sc, nm_txq); 1074 } 1075 1076 /* Will get called again. */ 1077 MPASS(npkt_remaining); 1078 } 1079 1080 /* How many contiguous free descriptors starting at pidx */ 1081 static inline int 1082 contiguous_ndesc_available(struct sge_nm_txq *nm_txq) 1083 { 1084 1085 if (nm_txq->cidx > nm_txq->pidx) 1086 return (nm_txq->cidx - nm_txq->pidx - 1); 1087 else if (nm_txq->cidx > 0) 1088 return (nm_txq->sidx - nm_txq->pidx); 1089 else 1090 return (nm_txq->sidx - nm_txq->pidx - 1); 1091 } 1092 1093 static int 1094 reclaim_nm_tx_desc(struct sge_nm_txq *nm_txq) 1095 { 1096 struct sge_qstat *spg = (void *)&nm_txq->desc[nm_txq->sidx]; 1097 uint16_t hw_cidx = spg->cidx; /* snapshot */ 1098 struct fw_eth_tx_pkts_wr *wr; 1099 int n = 0; 1100 1101 hw_cidx = be16toh(hw_cidx); 1102 1103 while (nm_txq->cidx != hw_cidx) { 1104 wr = (void *)&nm_txq->desc[nm_txq->cidx]; 1105 1106 MPASS(wr->op_pkd == htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR)) || 1107 wr->op_pkd == htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS2_WR))); 1108 MPASS(wr->type == 1); 1109 MPASS(wr->npkt > 0 && wr->npkt <= MAX_NPKT_IN_TYPE1_WR); 1110 1111 n += wr->npkt; 1112 nm_txq->cidx += npkt_to_ndesc(wr->npkt); 1113 1114 /* 1115 * We never sent a WR that wrapped around so the credits coming 1116 * back, WR by WR, should never cause the cidx to wrap around 1117 * either. 1118 */ 1119 MPASS(nm_txq->cidx <= nm_txq->sidx); 1120 if (__predict_false(nm_txq->cidx == nm_txq->sidx)) 1121 nm_txq->cidx = 0; 1122 } 1123 1124 return (n); 1125 } 1126 1127 static int 1128 cxgbe_netmap_txsync(struct netmap_kring *kring, int flags) 1129 { 1130 struct netmap_adapter *na = kring->na; 1131 struct ifnet *ifp = na->ifp; 1132 struct vi_info *vi = ifp->if_softc; 1133 struct adapter *sc = vi->adapter; 1134 struct sge_nm_txq *nm_txq = &sc->sge.nm_txq[vi->first_nm_txq + kring->ring_id]; 1135 const u_int head = kring->rhead; 1136 u_int reclaimed = 0; 1137 int n, d, npkt_remaining, ndesc_remaining; 1138 1139 /* 1140 * Tx was at kring->nr_hwcur last time around and now we need to advance 1141 * to kring->rhead. Note that the driver's pidx moves independent of 1142 * netmap's kring->nr_hwcur (pidx counts descriptors and the relation 1143 * between descriptors and frames isn't 1:1). 1144 */ 1145 1146 npkt_remaining = head >= kring->nr_hwcur ? head - kring->nr_hwcur : 1147 kring->nkr_num_slots - kring->nr_hwcur + head; 1148 while (npkt_remaining) { 1149 reclaimed += reclaim_nm_tx_desc(nm_txq); 1150 ndesc_remaining = contiguous_ndesc_available(nm_txq); 1151 /* Can't run out of descriptors with packets still remaining */ 1152 MPASS(ndesc_remaining > 0); 1153 1154 /* # of desc needed to tx all remaining packets */ 1155 d = (npkt_remaining / MAX_NPKT_IN_TYPE1_WR) * SGE_MAX_WR_NDESC; 1156 if (npkt_remaining % MAX_NPKT_IN_TYPE1_WR) 1157 d += npkt_to_ndesc(npkt_remaining % MAX_NPKT_IN_TYPE1_WR); 1158 1159 if (d <= ndesc_remaining) 1160 n = npkt_remaining; 1161 else { 1162 /* Can't send all, calculate how many can be sent */ 1163 n = (ndesc_remaining / SGE_MAX_WR_NDESC) * 1164 MAX_NPKT_IN_TYPE1_WR; 1165 if (ndesc_remaining % SGE_MAX_WR_NDESC) 1166 n += ndesc_to_npkt(ndesc_remaining % SGE_MAX_WR_NDESC); 1167 } 1168 1169 /* Send n packets and update nm_txq->pidx and kring->nr_hwcur */ 1170 npkt_remaining -= n; 1171 cxgbe_nm_tx(sc, nm_txq, kring, n, npkt_remaining); 1172 } 1173 MPASS(npkt_remaining == 0); 1174 MPASS(kring->nr_hwcur == head); 1175 MPASS(nm_txq->dbidx == nm_txq->pidx); 1176 1177 /* 1178 * Second part: reclaim buffers for completed transmissions. 1179 */ 1180 if (reclaimed || flags & NAF_FORCE_RECLAIM || nm_kr_txempty(kring)) { 1181 reclaimed += reclaim_nm_tx_desc(nm_txq); 1182 kring->nr_hwtail += reclaimed; 1183 if (kring->nr_hwtail >= kring->nkr_num_slots) 1184 kring->nr_hwtail -= kring->nkr_num_slots; 1185 } 1186 1187 return (0); 1188 } 1189 1190 static int 1191 cxgbe_netmap_rxsync(struct netmap_kring *kring, int flags) 1192 { 1193 struct netmap_adapter *na = kring->na; 1194 struct netmap_ring *ring = kring->ring; 1195 struct ifnet *ifp = na->ifp; 1196 struct vi_info *vi = ifp->if_softc; 1197 struct adapter *sc = vi->adapter; 1198 struct sge_nm_rxq *nm_rxq = &sc->sge.nm_rxq[vi->first_nm_rxq + kring->ring_id]; 1199 u_int const head = kring->rhead; 1200 u_int n; 1201 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1202 1203 if (black_hole) 1204 return (0); /* No updates ever. */ 1205 1206 if (netmap_no_pendintr || force_update) { 1207 kring->nr_hwtail = atomic_load_acq_32(&nm_rxq->fl_cidx); 1208 kring->nr_kflags &= ~NKR_PENDINTR; 1209 } 1210 1211 if (nm_rxq->fl_db_saved > 0 && starve_fl == 0) { 1212 wmb(); 1213 t4_write_reg(sc, sc->sge_kdoorbell_reg, 1214 nm_rxq->fl_db_val | V_PIDX(nm_rxq->fl_db_saved)); 1215 nm_rxq->fl_db_saved = 0; 1216 } 1217 1218 /* Userspace done with buffers from kring->nr_hwcur to head */ 1219 n = head >= kring->nr_hwcur ? head - kring->nr_hwcur : 1220 kring->nkr_num_slots - kring->nr_hwcur + head; 1221 n &= ~7U; 1222 if (n > 0) { 1223 u_int fl_pidx = nm_rxq->fl_pidx; 1224 struct netmap_slot *slot = &ring->slot[fl_pidx]; 1225 uint64_t ba; 1226 int i, dbinc = 0, hwidx = nm_rxq->fl_hwidx; 1227 1228 /* 1229 * We always deal with 8 buffers at a time. We must have 1230 * stopped at an 8B boundary (fl_pidx) last time around and we 1231 * must have a multiple of 8B buffers to give to the freelist. 1232 */ 1233 MPASS((fl_pidx & 7) == 0); 1234 MPASS((n & 7) == 0); 1235 1236 IDXINCR(kring->nr_hwcur, n, kring->nkr_num_slots); 1237 IDXINCR(nm_rxq->fl_pidx, n, nm_rxq->fl_sidx2); 1238 1239 while (n > 0) { 1240 for (i = 0; i < 8; i++, fl_pidx++, slot++) { 1241 PNMB(na, slot, &ba); 1242 MPASS(ba != 0); 1243 nm_rxq->fl_desc[fl_pidx] = htobe64(ba | hwidx); 1244 slot->flags &= ~NS_BUF_CHANGED; 1245 MPASS(fl_pidx <= nm_rxq->fl_sidx2); 1246 } 1247 n -= 8; 1248 if (fl_pidx == nm_rxq->fl_sidx2) { 1249 fl_pidx = 0; 1250 slot = &ring->slot[0]; 1251 } 1252 if (++dbinc == nm_rxq->fl_db_threshold) { 1253 wmb(); 1254 if (starve_fl) 1255 nm_rxq->fl_db_saved += dbinc; 1256 else { 1257 t4_write_reg(sc, sc->sge_kdoorbell_reg, 1258 nm_rxq->fl_db_val | V_PIDX(dbinc)); 1259 } 1260 dbinc = 0; 1261 } 1262 } 1263 MPASS(nm_rxq->fl_pidx == fl_pidx); 1264 1265 if (dbinc > 0) { 1266 wmb(); 1267 if (starve_fl) 1268 nm_rxq->fl_db_saved += dbinc; 1269 else { 1270 t4_write_reg(sc, sc->sge_kdoorbell_reg, 1271 nm_rxq->fl_db_val | V_PIDX(dbinc)); 1272 } 1273 } 1274 } 1275 1276 return (0); 1277 } 1278 1279 void 1280 cxgbe_nm_attach(struct vi_info *vi) 1281 { 1282 struct port_info *pi; 1283 struct adapter *sc; 1284 struct netmap_adapter na; 1285 1286 MPASS(vi->nnmrxq > 0); 1287 MPASS(vi->ifp != NULL); 1288 1289 pi = vi->pi; 1290 sc = pi->adapter; 1291 1292 bzero(&na, sizeof(na)); 1293 1294 na.ifp = vi->ifp; 1295 na.na_flags = NAF_BDG_MAYSLEEP; 1296 1297 /* Netmap doesn't know about the space reserved for the status page. */ 1298 na.num_tx_desc = vi->qsize_txq - sc->params.sge.spg_len / EQ_ESIZE; 1299 1300 /* 1301 * The freelist's cidx/pidx drives netmap's rx cidx/pidx. So 1302 * num_rx_desc is based on the number of buffers that can be held in the 1303 * freelist, and not the number of entries in the iq. (These two are 1304 * not exactly the same due to the space taken up by the status page). 1305 */ 1306 na.num_rx_desc = rounddown(vi->qsize_rxq, 8); 1307 na.nm_txsync = cxgbe_netmap_txsync; 1308 na.nm_rxsync = cxgbe_netmap_rxsync; 1309 na.nm_register = cxgbe_netmap_reg; 1310 na.num_tx_rings = vi->nnmtxq; 1311 na.num_rx_rings = vi->nnmrxq; 1312 na.rx_buf_maxsize = MAX_MTU; 1313 netmap_attach(&na); /* This adds IFCAP_NETMAP to if_capabilities */ 1314 } 1315 1316 void 1317 cxgbe_nm_detach(struct vi_info *vi) 1318 { 1319 1320 MPASS(vi->nnmrxq > 0); 1321 MPASS(vi->ifp != NULL); 1322 1323 netmap_detach(vi->ifp); 1324 } 1325 1326 static inline const void * 1327 unwrap_nm_fw6_msg(const struct cpl_fw6_msg *cpl) 1328 { 1329 1330 MPASS(cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL); 1331 1332 /* data[0] is RSS header */ 1333 return (&cpl->data[1]); 1334 } 1335 1336 static void 1337 handle_nm_sge_egr_update(struct adapter *sc, struct ifnet *ifp, 1338 const struct cpl_sge_egr_update *egr) 1339 { 1340 uint32_t oq; 1341 struct sge_nm_txq *nm_txq; 1342 1343 oq = be32toh(egr->opcode_qid); 1344 MPASS(G_CPL_OPCODE(oq) == CPL_SGE_EGR_UPDATE); 1345 nm_txq = (void *)sc->sge.eqmap[G_EGR_QID(oq) - sc->sge.eq_start]; 1346 1347 netmap_tx_irq(ifp, nm_txq->nid); 1348 } 1349 1350 void 1351 service_nm_rxq(struct sge_nm_rxq *nm_rxq) 1352 { 1353 struct vi_info *vi = nm_rxq->vi; 1354 struct adapter *sc = vi->adapter; 1355 struct ifnet *ifp = vi->ifp; 1356 struct netmap_adapter *na = NA(ifp); 1357 struct netmap_kring *kring = na->rx_rings[nm_rxq->nid]; 1358 struct netmap_ring *ring = kring->ring; 1359 struct iq_desc *d = &nm_rxq->iq_desc[nm_rxq->iq_cidx]; 1360 const void *cpl; 1361 uint32_t lq; 1362 u_int work = 0; 1363 uint8_t opcode; 1364 uint32_t fl_cidx = atomic_load_acq_32(&nm_rxq->fl_cidx); 1365 u_int fl_credits = fl_cidx & 7; 1366 u_int ndesc = 0; /* desc processed since last cidx update */ 1367 u_int nframes = 0; /* frames processed since last netmap wakeup */ 1368 1369 while ((d->rsp.u.type_gen & F_RSPD_GEN) == nm_rxq->iq_gen) { 1370 1371 rmb(); 1372 1373 lq = be32toh(d->rsp.pldbuflen_qid); 1374 opcode = d->rss.opcode; 1375 cpl = &d->cpl[0]; 1376 1377 switch (G_RSPD_TYPE(d->rsp.u.type_gen)) { 1378 case X_RSPD_TYPE_FLBUF: 1379 1380 /* fall through */ 1381 1382 case X_RSPD_TYPE_CPL: 1383 MPASS(opcode < NUM_CPL_CMDS); 1384 1385 switch (opcode) { 1386 case CPL_FW4_MSG: 1387 case CPL_FW6_MSG: 1388 cpl = unwrap_nm_fw6_msg(cpl); 1389 /* fall through */ 1390 case CPL_SGE_EGR_UPDATE: 1391 handle_nm_sge_egr_update(sc, ifp, cpl); 1392 break; 1393 case CPL_RX_PKT: 1394 ring->slot[fl_cidx].len = G_RSPD_LEN(lq) - 1395 sc->params.sge.fl_pktshift; 1396 ring->slot[fl_cidx].flags = 0; 1397 nframes++; 1398 if (!(lq & F_RSPD_NEWBUF)) { 1399 MPASS(black_hole == 2); 1400 break; 1401 } 1402 fl_credits++; 1403 if (__predict_false(++fl_cidx == nm_rxq->fl_sidx)) 1404 fl_cidx = 0; 1405 break; 1406 default: 1407 panic("%s: unexpected opcode 0x%x on nm_rxq %p", 1408 __func__, opcode, nm_rxq); 1409 } 1410 break; 1411 1412 case X_RSPD_TYPE_INTR: 1413 /* Not equipped to handle forwarded interrupts. */ 1414 panic("%s: netmap queue received interrupt for iq %u\n", 1415 __func__, lq); 1416 1417 default: 1418 panic("%s: illegal response type %d on nm_rxq %p", 1419 __func__, G_RSPD_TYPE(d->rsp.u.type_gen), nm_rxq); 1420 } 1421 1422 d++; 1423 if (__predict_false(++nm_rxq->iq_cidx == nm_rxq->iq_sidx)) { 1424 nm_rxq->iq_cidx = 0; 1425 d = &nm_rxq->iq_desc[0]; 1426 nm_rxq->iq_gen ^= F_RSPD_GEN; 1427 } 1428 1429 if (__predict_false(++nframes == rx_nframes) && !black_hole) { 1430 atomic_store_rel_32(&nm_rxq->fl_cidx, fl_cidx); 1431 netmap_rx_irq(ifp, nm_rxq->nid, &work); 1432 nframes = 0; 1433 } 1434 1435 if (__predict_false(++ndesc == rx_ndesc)) { 1436 if (black_hole && fl_credits >= 8) { 1437 fl_credits /= 8; 1438 IDXINCR(nm_rxq->fl_pidx, fl_credits * 8, 1439 nm_rxq->fl_sidx); 1440 t4_write_reg(sc, sc->sge_kdoorbell_reg, 1441 nm_rxq->fl_db_val | V_PIDX(fl_credits)); 1442 fl_credits = fl_cidx & 7; 1443 } 1444 t4_write_reg(sc, sc->sge_gts_reg, 1445 V_CIDXINC(ndesc) | 1446 V_INGRESSQID(nm_rxq->iq_cntxt_id) | 1447 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); 1448 ndesc = 0; 1449 } 1450 } 1451 1452 atomic_store_rel_32(&nm_rxq->fl_cidx, fl_cidx); 1453 if (black_hole) { 1454 fl_credits /= 8; 1455 IDXINCR(nm_rxq->fl_pidx, fl_credits * 8, nm_rxq->fl_sidx); 1456 t4_write_reg(sc, sc->sge_kdoorbell_reg, 1457 nm_rxq->fl_db_val | V_PIDX(fl_credits)); 1458 } else if (nframes > 0) 1459 netmap_rx_irq(ifp, nm_rxq->nid, &work); 1460 1461 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndesc) | 1462 V_INGRESSQID((u32)nm_rxq->iq_cntxt_id) | 1463 V_SEINTARM(V_QINTR_TIMER_IDX(holdoff_tmr_idx))); 1464 } 1465 #endif 1466