1 /*- 2 * Copyright (c) 2014 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 34 #ifdef DEV_NETMAP 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/eventhandler.h> 38 #include <sys/lock.h> 39 #include <sys/mbuf.h> 40 #include <sys/module.h> 41 #include <sys/selinfo.h> 42 #include <sys/socket.h> 43 #include <sys/sockio.h> 44 #include <machine/bus.h> 45 #include <net/ethernet.h> 46 #include <net/if.h> 47 #include <net/if_media.h> 48 #include <net/if_var.h> 49 #include <net/if_clone.h> 50 #include <net/if_types.h> 51 #include <net/netmap.h> 52 #include <dev/netmap/netmap_kern.h> 53 54 #include "common/common.h" 55 #include "common/t4_regs.h" 56 #include "common/t4_regs_values.h" 57 58 extern int fl_pad; /* XXXNM */ 59 60 SYSCTL_NODE(_hw, OID_AUTO, cxgbe, CTLFLAG_RD, 0, "cxgbe netmap parameters"); 61 62 /* 63 * 0 = normal netmap rx 64 * 1 = black hole 65 * 2 = supermassive black hole (buffer packing enabled) 66 */ 67 int black_hole = 0; 68 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_black_hole, CTLFLAG_RDTUN, &black_hole, 0, 69 "Sink incoming packets."); 70 71 int rx_ndesc = 256; 72 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_rx_ndesc, CTLFLAG_RWTUN, 73 &rx_ndesc, 0, "# of rx descriptors after which the hw cidx is updated."); 74 75 int holdoff_tmr_idx = 2; 76 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_holdoff_tmr_idx, CTLFLAG_RWTUN, 77 &holdoff_tmr_idx, 0, "Holdoff timer index for netmap rx queues."); 78 79 /* 80 * Congestion drops. 81 * -1: no congestion feedback (not recommended). 82 * 0: backpressure the channel instead of dropping packets right away. 83 * 1: no backpressure, drop packets for the congested queue immediately. 84 */ 85 static int nm_cong_drop = 1; 86 TUNABLE_INT("hw.cxgbe.nm_cong_drop", &nm_cong_drop); 87 88 static int 89 alloc_nm_rxq_hwq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq, int cong) 90 { 91 int rc, cntxt_id, i; 92 __be32 v; 93 struct adapter *sc = vi->pi->adapter; 94 struct sge_params *sp = &sc->params.sge; 95 struct netmap_adapter *na = NA(vi->ifp); 96 struct fw_iq_cmd c; 97 98 MPASS(na != NULL); 99 MPASS(nm_rxq->iq_desc != NULL); 100 MPASS(nm_rxq->fl_desc != NULL); 101 102 bzero(nm_rxq->iq_desc, vi->qsize_rxq * IQ_ESIZE); 103 bzero(nm_rxq->fl_desc, na->num_rx_desc * EQ_ESIZE + sp->spg_len); 104 105 bzero(&c, sizeof(c)); 106 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 107 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) | 108 V_FW_IQ_CMD_VFN(0)); 109 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART | 110 FW_LEN16(c)); 111 if (vi->flags & INTR_RXQ) { 112 KASSERT(nm_rxq->intr_idx < sc->intr_count, 113 ("%s: invalid direct intr_idx %d", __func__, 114 nm_rxq->intr_idx)); 115 v = V_FW_IQ_CMD_IQANDSTINDEX(nm_rxq->intr_idx); 116 } else { 117 CXGBE_UNIMPLEMENTED(__func__); /* XXXNM: needs review */ 118 v = V_FW_IQ_CMD_IQANDSTINDEX(nm_rxq->intr_idx) | 119 F_FW_IQ_CMD_IQANDST; 120 } 121 c.type_to_iqandstindex = htobe32(v | 122 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) | 123 V_FW_IQ_CMD_VIID(vi->viid) | 124 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT)); 125 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(vi->pi->tx_chan) | 126 F_FW_IQ_CMD_IQGTSMODE | 127 V_FW_IQ_CMD_IQINTCNTTHRESH(0) | 128 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4)); 129 c.iqsize = htobe16(vi->qsize_rxq); 130 c.iqaddr = htobe64(nm_rxq->iq_ba); 131 if (cong >= 0) { 132 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN | 133 V_FW_IQ_CMD_FL0CNGCHMAP(cong) | F_FW_IQ_CMD_FL0CONGCIF | 134 F_FW_IQ_CMD_FL0CONGEN); 135 } 136 c.iqns_to_fl0congen |= 137 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) | 138 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO | 139 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) | 140 (black_hole == 2 ? F_FW_IQ_CMD_FL0PACKEN : 0)); 141 c.fl0dcaen_to_fl0cidxfthresh = 142 htobe16(V_FW_IQ_CMD_FL0FBMIN(chip_id(sc) <= CHELSIO_T5 ? 143 X_FETCHBURSTMIN_128B : X_FETCHBURSTMIN_64B) | 144 V_FW_IQ_CMD_FL0FBMAX(chip_id(sc) <= CHELSIO_T5 ? 145 X_FETCHBURSTMAX_512B : X_FETCHBURSTMAX_256B)); 146 c.fl0size = htobe16(na->num_rx_desc / 8 + sp->spg_len / EQ_ESIZE); 147 c.fl0addr = htobe64(nm_rxq->fl_ba); 148 149 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 150 if (rc != 0) { 151 device_printf(sc->dev, 152 "failed to create netmap ingress queue: %d\n", rc); 153 return (rc); 154 } 155 156 nm_rxq->iq_cidx = 0; 157 MPASS(nm_rxq->iq_sidx == vi->qsize_rxq - sp->spg_len / IQ_ESIZE); 158 nm_rxq->iq_gen = F_RSPD_GEN; 159 nm_rxq->iq_cntxt_id = be16toh(c.iqid); 160 nm_rxq->iq_abs_id = be16toh(c.physiqid); 161 cntxt_id = nm_rxq->iq_cntxt_id - sc->sge.iq_start; 162 if (cntxt_id >= sc->sge.niq) { 163 panic ("%s: nm_rxq->iq_cntxt_id (%d) more than the max (%d)", 164 __func__, cntxt_id, sc->sge.niq - 1); 165 } 166 sc->sge.iqmap[cntxt_id] = (void *)nm_rxq; 167 168 nm_rxq->fl_cntxt_id = be16toh(c.fl0id); 169 nm_rxq->fl_pidx = nm_rxq->fl_cidx = 0; 170 MPASS(nm_rxq->fl_sidx == na->num_rx_desc); 171 cntxt_id = nm_rxq->fl_cntxt_id - sc->sge.eq_start; 172 if (cntxt_id >= sc->sge.neq) { 173 panic("%s: nm_rxq->fl_cntxt_id (%d) more than the max (%d)", 174 __func__, cntxt_id, sc->sge.neq - 1); 175 } 176 sc->sge.eqmap[cntxt_id] = (void *)nm_rxq; 177 178 nm_rxq->fl_db_val = V_QID(nm_rxq->fl_cntxt_id) | 179 sc->chip_params->sge_fl_db; 180 181 if (chip_id(sc) >= CHELSIO_T5 && cong >= 0) { 182 uint32_t param, val; 183 184 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 185 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) | 186 V_FW_PARAMS_PARAM_YZ(nm_rxq->iq_cntxt_id); 187 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 188 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) | 189 V_FW_PARAMS_PARAM_YZ(nm_rxq->iq_cntxt_id); 190 if (cong == 0) 191 val = 1 << 19; 192 else { 193 val = 2 << 19; 194 for (i = 0; i < 4; i++) { 195 if (cong & (1 << i)) 196 val |= 1 << (i << 2); 197 } 198 } 199 200 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 201 if (rc != 0) { 202 /* report error but carry on */ 203 device_printf(sc->dev, 204 "failed to set congestion manager context for " 205 "ingress queue %d: %d\n", nm_rxq->iq_cntxt_id, rc); 206 } 207 } 208 209 t4_write_reg(sc, sc->sge_gts_reg, 210 V_INGRESSQID(nm_rxq->iq_cntxt_id) | 211 V_SEINTARM(V_QINTR_TIMER_IDX(holdoff_tmr_idx))); 212 213 return (rc); 214 } 215 216 static int 217 free_nm_rxq_hwq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq) 218 { 219 struct adapter *sc = vi->pi->adapter; 220 int rc; 221 222 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0, FW_IQ_TYPE_FL_INT_CAP, 223 nm_rxq->iq_cntxt_id, nm_rxq->fl_cntxt_id, 0xffff); 224 if (rc != 0) 225 device_printf(sc->dev, "%s: failed for iq %d, fl %d: %d\n", 226 __func__, nm_rxq->iq_cntxt_id, nm_rxq->fl_cntxt_id, rc); 227 nm_rxq->iq_cntxt_id = INVALID_NM_RXQ_CNTXT_ID; 228 return (rc); 229 } 230 231 static int 232 alloc_nm_txq_hwq(struct vi_info *vi, struct sge_nm_txq *nm_txq) 233 { 234 int rc, cntxt_id; 235 size_t len; 236 struct adapter *sc = vi->pi->adapter; 237 struct netmap_adapter *na = NA(vi->ifp); 238 struct fw_eq_eth_cmd c; 239 240 MPASS(na != NULL); 241 MPASS(nm_txq->desc != NULL); 242 243 len = na->num_tx_desc * EQ_ESIZE + sc->params.sge.spg_len; 244 bzero(nm_txq->desc, len); 245 246 bzero(&c, sizeof(c)); 247 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST | 248 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) | 249 V_FW_EQ_ETH_CMD_VFN(0)); 250 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC | 251 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c)); 252 c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE | 253 F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(vi->viid)); 254 c.fetchszm_to_iqid = 255 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) | 256 V_FW_EQ_ETH_CMD_PCIECHN(vi->pi->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO | 257 V_FW_EQ_ETH_CMD_IQID(sc->sge.nm_rxq[nm_txq->iqidx].iq_cntxt_id)); 258 c.dcaen_to_eqsize = htobe32(V_FW_EQ_ETH_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 259 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 260 V_FW_EQ_ETH_CMD_EQSIZE(len / EQ_ESIZE)); 261 c.eqaddr = htobe64(nm_txq->ba); 262 263 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 264 if (rc != 0) { 265 device_printf(vi->dev, 266 "failed to create netmap egress queue: %d\n", rc); 267 return (rc); 268 } 269 270 nm_txq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd)); 271 cntxt_id = nm_txq->cntxt_id - sc->sge.eq_start; 272 if (cntxt_id >= sc->sge.neq) 273 panic("%s: nm_txq->cntxt_id (%d) more than the max (%d)", __func__, 274 cntxt_id, sc->sge.neq - 1); 275 sc->sge.eqmap[cntxt_id] = (void *)nm_txq; 276 277 nm_txq->pidx = nm_txq->cidx = 0; 278 MPASS(nm_txq->sidx == na->num_tx_desc); 279 nm_txq->equiqidx = nm_txq->equeqidx = nm_txq->dbidx = 0; 280 281 nm_txq->doorbells = sc->doorbells; 282 if (isset(&nm_txq->doorbells, DOORBELL_UDB) || 283 isset(&nm_txq->doorbells, DOORBELL_UDBWC) || 284 isset(&nm_txq->doorbells, DOORBELL_WCWR)) { 285 uint32_t s_qpp = sc->params.sge.eq_s_qpp; 286 uint32_t mask = (1 << s_qpp) - 1; 287 volatile uint8_t *udb; 288 289 udb = sc->udbs_base + UDBS_DB_OFFSET; 290 udb += (nm_txq->cntxt_id >> s_qpp) << PAGE_SHIFT; 291 nm_txq->udb_qid = nm_txq->cntxt_id & mask; 292 if (nm_txq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE) 293 clrbit(&nm_txq->doorbells, DOORBELL_WCWR); 294 else { 295 udb += nm_txq->udb_qid << UDBS_SEG_SHIFT; 296 nm_txq->udb_qid = 0; 297 } 298 nm_txq->udb = (volatile void *)udb; 299 } 300 301 return (rc); 302 } 303 304 static int 305 free_nm_txq_hwq(struct vi_info *vi, struct sge_nm_txq *nm_txq) 306 { 307 struct adapter *sc = vi->pi->adapter; 308 int rc; 309 310 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0, nm_txq->cntxt_id); 311 if (rc != 0) 312 device_printf(sc->dev, "%s: failed for eq %d: %d\n", __func__, 313 nm_txq->cntxt_id, rc); 314 nm_txq->cntxt_id = INVALID_NM_TXQ_CNTXT_ID; 315 return (rc); 316 } 317 318 static int 319 cxgbe_netmap_on(struct adapter *sc, struct vi_info *vi, struct ifnet *ifp, 320 struct netmap_adapter *na) 321 { 322 struct netmap_slot *slot; 323 struct netmap_kring *kring; 324 struct sge_nm_rxq *nm_rxq; 325 struct sge_nm_txq *nm_txq; 326 int rc, i, j, hwidx; 327 struct hw_buf_info *hwb; 328 329 ASSERT_SYNCHRONIZED_OP(sc); 330 331 if ((vi->flags & VI_INIT_DONE) == 0 || 332 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 333 return (EAGAIN); 334 335 hwb = &sc->sge.hw_buf_info[0]; 336 for (i = 0; i < SGE_FLBUF_SIZES; i++, hwb++) { 337 if (hwb->size == NETMAP_BUF_SIZE(na)) 338 break; 339 } 340 if (i >= SGE_FLBUF_SIZES) { 341 if_printf(ifp, "no hwidx for netmap buffer size %d.\n", 342 NETMAP_BUF_SIZE(na)); 343 return (ENXIO); 344 } 345 hwidx = i; 346 347 /* Must set caps before calling netmap_reset */ 348 nm_set_native_flags(na); 349 350 for_each_nm_rxq(vi, i, nm_rxq) { 351 struct irq *irq = &sc->irq[vi->first_intr + i]; 352 353 kring = &na->rx_rings[nm_rxq->nid]; 354 if (!nm_kring_pending_on(kring) || 355 nm_rxq->iq_cntxt_id != INVALID_NM_RXQ_CNTXT_ID) 356 continue; 357 358 alloc_nm_rxq_hwq(vi, nm_rxq, tnl_cong(vi->pi, nm_cong_drop)); 359 nm_rxq->fl_hwidx = hwidx; 360 slot = netmap_reset(na, NR_RX, i, 0); 361 MPASS(slot != NULL); /* XXXNM: error check, not assert */ 362 363 /* We deal with 8 bufs at a time */ 364 MPASS((na->num_rx_desc & 7) == 0); 365 MPASS(na->num_rx_desc == nm_rxq->fl_sidx); 366 for (j = 0; j < nm_rxq->fl_sidx; j++) { 367 uint64_t ba; 368 369 PNMB(na, &slot[j], &ba); 370 MPASS(ba != 0); 371 nm_rxq->fl_desc[j] = htobe64(ba | hwidx); 372 } 373 j = nm_rxq->fl_pidx = nm_rxq->fl_sidx - 8; 374 MPASS((j & 7) == 0); 375 j /= 8; /* driver pidx to hardware pidx */ 376 wmb(); 377 t4_write_reg(sc, sc->sge_kdoorbell_reg, 378 nm_rxq->fl_db_val | V_PIDX(j)); 379 380 atomic_cmpset_int(&irq->nm_state, NM_OFF, NM_ON); 381 } 382 383 for_each_nm_txq(vi, i, nm_txq) { 384 kring = &na->tx_rings[nm_txq->nid]; 385 if (!nm_kring_pending_on(kring) || 386 nm_txq->cntxt_id != INVALID_NM_TXQ_CNTXT_ID) 387 continue; 388 389 alloc_nm_txq_hwq(vi, nm_txq); 390 slot = netmap_reset(na, NR_TX, i, 0); 391 MPASS(slot != NULL); /* XXXNM: error check, not assert */ 392 } 393 394 if (vi->nm_rss == NULL) { 395 vi->nm_rss = malloc(vi->rss_size * sizeof(uint16_t), M_CXGBE, 396 M_ZERO | M_WAITOK); 397 } 398 for (i = 0; i < vi->rss_size;) { 399 for_each_nm_rxq(vi, j, nm_rxq) { 400 vi->nm_rss[i++] = nm_rxq->iq_abs_id; 401 if (i == vi->rss_size) 402 break; 403 } 404 } 405 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, 406 vi->nm_rss, vi->rss_size); 407 if (rc != 0) 408 if_printf(ifp, "netmap rss_config failed: %d\n", rc); 409 410 return (rc); 411 } 412 413 static int 414 cxgbe_netmap_off(struct adapter *sc, struct vi_info *vi, struct ifnet *ifp, 415 struct netmap_adapter *na) 416 { 417 struct netmap_kring *kring; 418 int rc, i; 419 struct sge_nm_txq *nm_txq; 420 struct sge_nm_rxq *nm_rxq; 421 422 ASSERT_SYNCHRONIZED_OP(sc); 423 424 if ((vi->flags & VI_INIT_DONE) == 0) 425 return (0); 426 427 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, 428 vi->rss, vi->rss_size); 429 if (rc != 0) 430 if_printf(ifp, "failed to restore RSS config: %d\n", rc); 431 nm_clear_native_flags(na); 432 433 for_each_nm_txq(vi, i, nm_txq) { 434 struct sge_qstat *spg = (void *)&nm_txq->desc[nm_txq->sidx]; 435 436 kring = &na->tx_rings[nm_txq->nid]; 437 if (!nm_kring_pending_off(kring) || 438 nm_txq->cntxt_id == INVALID_NM_TXQ_CNTXT_ID) 439 continue; 440 441 /* Wait for hw pidx to catch up ... */ 442 while (be16toh(nm_txq->pidx) != spg->pidx) 443 pause("nmpidx", 1); 444 445 /* ... and then for the cidx. */ 446 while (spg->pidx != spg->cidx) 447 pause("nmcidx", 1); 448 449 free_nm_txq_hwq(vi, nm_txq); 450 } 451 for_each_nm_rxq(vi, i, nm_rxq) { 452 struct irq *irq = &sc->irq[vi->first_intr + i]; 453 454 kring = &na->rx_rings[nm_rxq->nid]; 455 if (!nm_kring_pending_off(kring) || 456 nm_rxq->iq_cntxt_id == INVALID_NM_RXQ_CNTXT_ID) 457 continue; 458 459 while (!atomic_cmpset_int(&irq->nm_state, NM_ON, NM_OFF)) 460 pause("nmst", 1); 461 462 free_nm_rxq_hwq(vi, nm_rxq); 463 } 464 465 return (rc); 466 } 467 468 static int 469 cxgbe_netmap_reg(struct netmap_adapter *na, int on) 470 { 471 struct ifnet *ifp = na->ifp; 472 struct vi_info *vi = ifp->if_softc; 473 struct adapter *sc = vi->pi->adapter; 474 int rc; 475 476 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4nmreg"); 477 if (rc != 0) 478 return (rc); 479 if (on) 480 rc = cxgbe_netmap_on(sc, vi, ifp, na); 481 else 482 rc = cxgbe_netmap_off(sc, vi, ifp, na); 483 end_synchronized_op(sc, 0); 484 485 return (rc); 486 } 487 488 /* How many packets can a single type1 WR carry in n descriptors */ 489 static inline int 490 ndesc_to_npkt(const int n) 491 { 492 493 MPASS(n > 0 && n <= SGE_MAX_WR_NDESC); 494 495 return (n * 2 - 1); 496 } 497 #define MAX_NPKT_IN_TYPE1_WR (ndesc_to_npkt(SGE_MAX_WR_NDESC)) 498 499 /* Space (in descriptors) needed for a type1 WR that carries n packets */ 500 static inline int 501 npkt_to_ndesc(const int n) 502 { 503 504 MPASS(n > 0 && n <= MAX_NPKT_IN_TYPE1_WR); 505 506 return ((n + 2) / 2); 507 } 508 509 /* Space (in 16B units) needed for a type1 WR that carries n packets */ 510 static inline int 511 npkt_to_len16(const int n) 512 { 513 514 MPASS(n > 0 && n <= MAX_NPKT_IN_TYPE1_WR); 515 516 return (n * 2 + 1); 517 } 518 519 #define NMIDXDIFF(q, idx) IDXDIFF((q)->pidx, (q)->idx, (q)->sidx) 520 521 static void 522 ring_nm_txq_db(struct adapter *sc, struct sge_nm_txq *nm_txq) 523 { 524 int n; 525 u_int db = nm_txq->doorbells; 526 527 MPASS(nm_txq->pidx != nm_txq->dbidx); 528 529 n = NMIDXDIFF(nm_txq, dbidx); 530 if (n > 1) 531 clrbit(&db, DOORBELL_WCWR); 532 wmb(); 533 534 switch (ffs(db) - 1) { 535 case DOORBELL_UDB: 536 *nm_txq->udb = htole32(V_QID(nm_txq->udb_qid) | V_PIDX(n)); 537 break; 538 539 case DOORBELL_WCWR: { 540 volatile uint64_t *dst, *src; 541 542 /* 543 * Queues whose 128B doorbell segment fits in the page do not 544 * use relative qid (udb_qid is always 0). Only queues with 545 * doorbell segments can do WCWR. 546 */ 547 KASSERT(nm_txq->udb_qid == 0 && n == 1, 548 ("%s: inappropriate doorbell (0x%x, %d, %d) for nm_txq %p", 549 __func__, nm_txq->doorbells, n, nm_txq->pidx, nm_txq)); 550 551 dst = (volatile void *)((uintptr_t)nm_txq->udb + 552 UDBS_WR_OFFSET - UDBS_DB_OFFSET); 553 src = (void *)&nm_txq->desc[nm_txq->dbidx]; 554 while (src != (void *)&nm_txq->desc[nm_txq->dbidx + 1]) 555 *dst++ = *src++; 556 wmb(); 557 break; 558 } 559 560 case DOORBELL_UDBWC: 561 *nm_txq->udb = htole32(V_QID(nm_txq->udb_qid) | V_PIDX(n)); 562 wmb(); 563 break; 564 565 case DOORBELL_KDB: 566 t4_write_reg(sc, sc->sge_kdoorbell_reg, 567 V_QID(nm_txq->cntxt_id) | V_PIDX(n)); 568 break; 569 } 570 nm_txq->dbidx = nm_txq->pidx; 571 } 572 573 int lazy_tx_credit_flush = 1; 574 575 /* 576 * Write work requests to send 'npkt' frames and ring the doorbell to send them 577 * on their way. No need to check for wraparound. 578 */ 579 static void 580 cxgbe_nm_tx(struct adapter *sc, struct sge_nm_txq *nm_txq, 581 struct netmap_kring *kring, int npkt, int npkt_remaining, int txcsum) 582 { 583 struct netmap_ring *ring = kring->ring; 584 struct netmap_slot *slot; 585 const u_int lim = kring->nkr_num_slots - 1; 586 struct fw_eth_tx_pkts_wr *wr = (void *)&nm_txq->desc[nm_txq->pidx]; 587 uint16_t len; 588 uint64_t ba; 589 struct cpl_tx_pkt_core *cpl; 590 struct ulptx_sgl *usgl; 591 int i, n; 592 593 while (npkt) { 594 n = min(npkt, MAX_NPKT_IN_TYPE1_WR); 595 len = 0; 596 597 wr = (void *)&nm_txq->desc[nm_txq->pidx]; 598 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR)); 599 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(npkt_to_len16(n))); 600 wr->npkt = n; 601 wr->r3 = 0; 602 wr->type = 1; 603 cpl = (void *)(wr + 1); 604 605 for (i = 0; i < n; i++) { 606 slot = &ring->slot[kring->nr_hwcur]; 607 PNMB(kring->na, slot, &ba); 608 MPASS(ba != 0); 609 610 cpl->ctrl0 = nm_txq->cpl_ctrl0; 611 cpl->pack = 0; 612 cpl->len = htobe16(slot->len); 613 /* 614 * netmap(4) says "netmap does not use features such as 615 * checksum offloading, TCP segmentation offloading, 616 * encryption, VLAN encapsulation/decapsulation, etc." 617 * 618 * So the ncxl interfaces have tx hardware checksumming 619 * disabled by default. But you can override netmap by 620 * enabling IFCAP_TXCSUM on the interface manully. 621 */ 622 cpl->ctrl1 = txcsum ? 0 : 623 htobe64(F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS); 624 625 usgl = (void *)(cpl + 1); 626 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 627 V_ULPTX_NSGE(1)); 628 usgl->len0 = htobe32(slot->len); 629 usgl->addr0 = htobe64(ba); 630 631 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); 632 cpl = (void *)(usgl + 1); 633 MPASS(slot->len + len <= UINT16_MAX); 634 len += slot->len; 635 kring->nr_hwcur = nm_next(kring->nr_hwcur, lim); 636 } 637 wr->plen = htobe16(len); 638 639 npkt -= n; 640 nm_txq->pidx += npkt_to_ndesc(n); 641 MPASS(nm_txq->pidx <= nm_txq->sidx); 642 if (__predict_false(nm_txq->pidx == nm_txq->sidx)) { 643 /* 644 * This routine doesn't know how to write WRs that wrap 645 * around. Make sure it wasn't asked to. 646 */ 647 MPASS(npkt == 0); 648 nm_txq->pidx = 0; 649 } 650 651 if (npkt == 0 && npkt_remaining == 0) { 652 /* All done. */ 653 if (lazy_tx_credit_flush == 0) { 654 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ | 655 F_FW_WR_EQUIQ); 656 nm_txq->equeqidx = nm_txq->pidx; 657 nm_txq->equiqidx = nm_txq->pidx; 658 } 659 ring_nm_txq_db(sc, nm_txq); 660 return; 661 } 662 663 if (NMIDXDIFF(nm_txq, equiqidx) >= nm_txq->sidx / 2) { 664 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ | 665 F_FW_WR_EQUIQ); 666 nm_txq->equeqidx = nm_txq->pidx; 667 nm_txq->equiqidx = nm_txq->pidx; 668 } else if (NMIDXDIFF(nm_txq, equeqidx) >= 64) { 669 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ); 670 nm_txq->equeqidx = nm_txq->pidx; 671 } 672 if (NMIDXDIFF(nm_txq, dbidx) >= 2 * SGE_MAX_WR_NDESC) 673 ring_nm_txq_db(sc, nm_txq); 674 } 675 676 /* Will get called again. */ 677 MPASS(npkt_remaining); 678 } 679 680 /* How many contiguous free descriptors starting at pidx */ 681 static inline int 682 contiguous_ndesc_available(struct sge_nm_txq *nm_txq) 683 { 684 685 if (nm_txq->cidx > nm_txq->pidx) 686 return (nm_txq->cidx - nm_txq->pidx - 1); 687 else if (nm_txq->cidx > 0) 688 return (nm_txq->sidx - nm_txq->pidx); 689 else 690 return (nm_txq->sidx - nm_txq->pidx - 1); 691 } 692 693 static int 694 reclaim_nm_tx_desc(struct sge_nm_txq *nm_txq) 695 { 696 struct sge_qstat *spg = (void *)&nm_txq->desc[nm_txq->sidx]; 697 uint16_t hw_cidx = spg->cidx; /* snapshot */ 698 struct fw_eth_tx_pkts_wr *wr; 699 int n = 0; 700 701 hw_cidx = be16toh(hw_cidx); 702 703 while (nm_txq->cidx != hw_cidx) { 704 wr = (void *)&nm_txq->desc[nm_txq->cidx]; 705 706 MPASS(wr->op_pkd == htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR))); 707 MPASS(wr->type == 1); 708 MPASS(wr->npkt > 0 && wr->npkt <= MAX_NPKT_IN_TYPE1_WR); 709 710 n += wr->npkt; 711 nm_txq->cidx += npkt_to_ndesc(wr->npkt); 712 713 /* 714 * We never sent a WR that wrapped around so the credits coming 715 * back, WR by WR, should never cause the cidx to wrap around 716 * either. 717 */ 718 MPASS(nm_txq->cidx <= nm_txq->sidx); 719 if (__predict_false(nm_txq->cidx == nm_txq->sidx)) 720 nm_txq->cidx = 0; 721 } 722 723 return (n); 724 } 725 726 static int 727 cxgbe_netmap_txsync(struct netmap_kring *kring, int flags) 728 { 729 struct netmap_adapter *na = kring->na; 730 struct ifnet *ifp = na->ifp; 731 struct vi_info *vi = ifp->if_softc; 732 struct adapter *sc = vi->pi->adapter; 733 struct sge_nm_txq *nm_txq = &sc->sge.nm_txq[vi->first_nm_txq + kring->ring_id]; 734 const u_int head = kring->rhead; 735 u_int reclaimed = 0; 736 int n, d, npkt_remaining, ndesc_remaining, txcsum; 737 738 /* 739 * Tx was at kring->nr_hwcur last time around and now we need to advance 740 * to kring->rhead. Note that the driver's pidx moves independent of 741 * netmap's kring->nr_hwcur (pidx counts descriptors and the relation 742 * between descriptors and frames isn't 1:1). 743 */ 744 745 npkt_remaining = head >= kring->nr_hwcur ? head - kring->nr_hwcur : 746 kring->nkr_num_slots - kring->nr_hwcur + head; 747 txcsum = ifp->if_capenable & (IFCAP_TXCSUM | IFCAP_TXCSUM_IPV6); 748 while (npkt_remaining) { 749 reclaimed += reclaim_nm_tx_desc(nm_txq); 750 ndesc_remaining = contiguous_ndesc_available(nm_txq); 751 /* Can't run out of descriptors with packets still remaining */ 752 MPASS(ndesc_remaining > 0); 753 754 /* # of desc needed to tx all remaining packets */ 755 d = (npkt_remaining / MAX_NPKT_IN_TYPE1_WR) * SGE_MAX_WR_NDESC; 756 if (npkt_remaining % MAX_NPKT_IN_TYPE1_WR) 757 d += npkt_to_ndesc(npkt_remaining % MAX_NPKT_IN_TYPE1_WR); 758 759 if (d <= ndesc_remaining) 760 n = npkt_remaining; 761 else { 762 /* Can't send all, calculate how many can be sent */ 763 n = (ndesc_remaining / SGE_MAX_WR_NDESC) * 764 MAX_NPKT_IN_TYPE1_WR; 765 if (ndesc_remaining % SGE_MAX_WR_NDESC) 766 n += ndesc_to_npkt(ndesc_remaining % SGE_MAX_WR_NDESC); 767 } 768 769 /* Send n packets and update nm_txq->pidx and kring->nr_hwcur */ 770 npkt_remaining -= n; 771 cxgbe_nm_tx(sc, nm_txq, kring, n, npkt_remaining, txcsum); 772 } 773 MPASS(npkt_remaining == 0); 774 MPASS(kring->nr_hwcur == head); 775 MPASS(nm_txq->dbidx == nm_txq->pidx); 776 777 /* 778 * Second part: reclaim buffers for completed transmissions. 779 */ 780 if (reclaimed || flags & NAF_FORCE_RECLAIM || nm_kr_txempty(kring)) { 781 reclaimed += reclaim_nm_tx_desc(nm_txq); 782 kring->nr_hwtail += reclaimed; 783 if (kring->nr_hwtail >= kring->nkr_num_slots) 784 kring->nr_hwtail -= kring->nkr_num_slots; 785 } 786 787 return (0); 788 } 789 790 static int 791 cxgbe_netmap_rxsync(struct netmap_kring *kring, int flags) 792 { 793 struct netmap_adapter *na = kring->na; 794 struct netmap_ring *ring = kring->ring; 795 struct ifnet *ifp = na->ifp; 796 struct vi_info *vi = ifp->if_softc; 797 struct adapter *sc = vi->pi->adapter; 798 struct sge_nm_rxq *nm_rxq = &sc->sge.nm_rxq[vi->first_nm_rxq + kring->ring_id]; 799 u_int const head = kring->rhead; 800 u_int n; 801 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 802 803 if (black_hole) 804 return (0); /* No updates ever. */ 805 806 if (netmap_no_pendintr || force_update) { 807 kring->nr_hwtail = atomic_load_acq_32(&nm_rxq->fl_cidx); 808 kring->nr_kflags &= ~NKR_PENDINTR; 809 } 810 811 /* Userspace done with buffers from kring->nr_hwcur to head */ 812 n = head >= kring->nr_hwcur ? head - kring->nr_hwcur : 813 kring->nkr_num_slots - kring->nr_hwcur + head; 814 n &= ~7U; 815 if (n > 0) { 816 u_int fl_pidx = nm_rxq->fl_pidx; 817 struct netmap_slot *slot = &ring->slot[fl_pidx]; 818 uint64_t ba; 819 int i, dbinc = 0, hwidx = nm_rxq->fl_hwidx; 820 821 /* 822 * We always deal with 8 buffers at a time. We must have 823 * stopped at an 8B boundary (fl_pidx) last time around and we 824 * must have a multiple of 8B buffers to give to the freelist. 825 */ 826 MPASS((fl_pidx & 7) == 0); 827 MPASS((n & 7) == 0); 828 829 IDXINCR(kring->nr_hwcur, n, kring->nkr_num_slots); 830 IDXINCR(nm_rxq->fl_pidx, n, nm_rxq->fl_sidx); 831 832 while (n > 0) { 833 for (i = 0; i < 8; i++, fl_pidx++, slot++) { 834 PNMB(na, slot, &ba); 835 MPASS(ba != 0); 836 nm_rxq->fl_desc[fl_pidx] = htobe64(ba | hwidx); 837 slot->flags &= ~NS_BUF_CHANGED; 838 MPASS(fl_pidx <= nm_rxq->fl_sidx); 839 } 840 n -= 8; 841 if (fl_pidx == nm_rxq->fl_sidx) { 842 fl_pidx = 0; 843 slot = &ring->slot[0]; 844 } 845 if (++dbinc == 8 && n >= 32) { 846 wmb(); 847 t4_write_reg(sc, sc->sge_kdoorbell_reg, 848 nm_rxq->fl_db_val | V_PIDX(dbinc)); 849 dbinc = 0; 850 } 851 } 852 MPASS(nm_rxq->fl_pidx == fl_pidx); 853 854 if (dbinc > 0) { 855 wmb(); 856 t4_write_reg(sc, sc->sge_kdoorbell_reg, 857 nm_rxq->fl_db_val | V_PIDX(dbinc)); 858 } 859 } 860 861 return (0); 862 } 863 864 void 865 cxgbe_nm_attach(struct vi_info *vi) 866 { 867 struct port_info *pi; 868 struct adapter *sc; 869 struct netmap_adapter na; 870 871 MPASS(vi->nnmrxq > 0); 872 MPASS(vi->ifp != NULL); 873 874 pi = vi->pi; 875 sc = pi->adapter; 876 877 bzero(&na, sizeof(na)); 878 879 na.ifp = vi->ifp; 880 na.na_flags = NAF_BDG_MAYSLEEP; 881 882 /* Netmap doesn't know about the space reserved for the status page. */ 883 na.num_tx_desc = vi->qsize_txq - sc->params.sge.spg_len / EQ_ESIZE; 884 885 /* 886 * The freelist's cidx/pidx drives netmap's rx cidx/pidx. So 887 * num_rx_desc is based on the number of buffers that can be held in the 888 * freelist, and not the number of entries in the iq. (These two are 889 * not exactly the same due to the space taken up by the status page). 890 */ 891 na.num_rx_desc = rounddown(vi->qsize_rxq, 8); 892 na.nm_txsync = cxgbe_netmap_txsync; 893 na.nm_rxsync = cxgbe_netmap_rxsync; 894 na.nm_register = cxgbe_netmap_reg; 895 na.num_tx_rings = vi->nnmtxq; 896 na.num_rx_rings = vi->nnmrxq; 897 netmap_attach(&na); 898 } 899 900 void 901 cxgbe_nm_detach(struct vi_info *vi) 902 { 903 904 MPASS(vi->nnmrxq > 0); 905 MPASS(vi->ifp != NULL); 906 907 netmap_detach(vi->ifp); 908 } 909 910 static inline const void * 911 unwrap_nm_fw6_msg(const struct cpl_fw6_msg *cpl) 912 { 913 914 MPASS(cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL); 915 916 /* data[0] is RSS header */ 917 return (&cpl->data[1]); 918 } 919 920 static void 921 handle_nm_sge_egr_update(struct adapter *sc, struct ifnet *ifp, 922 const struct cpl_sge_egr_update *egr) 923 { 924 uint32_t oq; 925 struct sge_nm_txq *nm_txq; 926 927 oq = be32toh(egr->opcode_qid); 928 MPASS(G_CPL_OPCODE(oq) == CPL_SGE_EGR_UPDATE); 929 nm_txq = (void *)sc->sge.eqmap[G_EGR_QID(oq) - sc->sge.eq_start]; 930 931 netmap_tx_irq(ifp, nm_txq->nid); 932 } 933 934 void 935 t4_nm_intr(void *arg) 936 { 937 struct sge_nm_rxq *nm_rxq = arg; 938 struct vi_info *vi = nm_rxq->vi; 939 struct adapter *sc = vi->pi->adapter; 940 struct ifnet *ifp = vi->ifp; 941 struct netmap_adapter *na = NA(ifp); 942 struct netmap_kring *kring = &na->rx_rings[nm_rxq->nid]; 943 struct netmap_ring *ring = kring->ring; 944 struct iq_desc *d = &nm_rxq->iq_desc[nm_rxq->iq_cidx]; 945 const void *cpl; 946 uint32_t lq; 947 u_int n = 0, work = 0; 948 uint8_t opcode; 949 uint32_t fl_cidx = atomic_load_acq_32(&nm_rxq->fl_cidx); 950 u_int fl_credits = fl_cidx & 7; 951 952 while ((d->rsp.u.type_gen & F_RSPD_GEN) == nm_rxq->iq_gen) { 953 954 rmb(); 955 956 lq = be32toh(d->rsp.pldbuflen_qid); 957 opcode = d->rss.opcode; 958 cpl = &d->cpl[0]; 959 960 switch (G_RSPD_TYPE(d->rsp.u.type_gen)) { 961 case X_RSPD_TYPE_FLBUF: 962 if (black_hole != 2) { 963 /* No buffer packing so new buf every time */ 964 MPASS(lq & F_RSPD_NEWBUF); 965 } 966 967 /* fall through */ 968 969 case X_RSPD_TYPE_CPL: 970 MPASS(opcode < NUM_CPL_CMDS); 971 972 switch (opcode) { 973 case CPL_FW4_MSG: 974 case CPL_FW6_MSG: 975 cpl = unwrap_nm_fw6_msg(cpl); 976 /* fall through */ 977 case CPL_SGE_EGR_UPDATE: 978 handle_nm_sge_egr_update(sc, ifp, cpl); 979 break; 980 case CPL_RX_PKT: 981 ring->slot[fl_cidx].len = G_RSPD_LEN(lq) - 982 sc->params.sge.fl_pktshift; 983 ring->slot[fl_cidx].flags = kring->nkr_slot_flags; 984 fl_cidx += (lq & F_RSPD_NEWBUF) ? 1 : 0; 985 fl_credits += (lq & F_RSPD_NEWBUF) ? 1 : 0; 986 if (__predict_false(fl_cidx == nm_rxq->fl_sidx)) 987 fl_cidx = 0; 988 break; 989 default: 990 panic("%s: unexpected opcode 0x%x on nm_rxq %p", 991 __func__, opcode, nm_rxq); 992 } 993 break; 994 995 case X_RSPD_TYPE_INTR: 996 /* Not equipped to handle forwarded interrupts. */ 997 panic("%s: netmap queue received interrupt for iq %u\n", 998 __func__, lq); 999 1000 default: 1001 panic("%s: illegal response type %d on nm_rxq %p", 1002 __func__, G_RSPD_TYPE(d->rsp.u.type_gen), nm_rxq); 1003 } 1004 1005 d++; 1006 if (__predict_false(++nm_rxq->iq_cidx == nm_rxq->iq_sidx)) { 1007 nm_rxq->iq_cidx = 0; 1008 d = &nm_rxq->iq_desc[0]; 1009 nm_rxq->iq_gen ^= F_RSPD_GEN; 1010 } 1011 1012 if (__predict_false(++n == rx_ndesc)) { 1013 atomic_store_rel_32(&nm_rxq->fl_cidx, fl_cidx); 1014 if (black_hole && fl_credits >= 8) { 1015 fl_credits /= 8; 1016 IDXINCR(nm_rxq->fl_pidx, fl_credits * 8, 1017 nm_rxq->fl_sidx); 1018 t4_write_reg(sc, sc->sge_kdoorbell_reg, 1019 nm_rxq->fl_db_val | V_PIDX(fl_credits)); 1020 fl_credits = fl_cidx & 7; 1021 } else if (!black_hole) { 1022 netmap_rx_irq(ifp, nm_rxq->nid, &work); 1023 MPASS(work != 0); 1024 } 1025 t4_write_reg(sc, sc->sge_gts_reg, 1026 V_CIDXINC(n) | V_INGRESSQID(nm_rxq->iq_cntxt_id) | 1027 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); 1028 n = 0; 1029 } 1030 } 1031 1032 atomic_store_rel_32(&nm_rxq->fl_cidx, fl_cidx); 1033 if (black_hole) { 1034 fl_credits /= 8; 1035 IDXINCR(nm_rxq->fl_pidx, fl_credits * 8, nm_rxq->fl_sidx); 1036 t4_write_reg(sc, sc->sge_kdoorbell_reg, 1037 nm_rxq->fl_db_val | V_PIDX(fl_credits)); 1038 } else 1039 netmap_rx_irq(ifp, nm_rxq->nid, &work); 1040 1041 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(n) | 1042 V_INGRESSQID((u32)nm_rxq->iq_cntxt_id) | 1043 V_SEINTARM(V_QINTR_TIMER_IDX(holdoff_tmr_idx))); 1044 } 1045 #endif 1046