1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 Chelsio Communications, Inc. 5 * All rights reserved. 6 * Written by: Navdeep Parhar <np@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include "opt_ddb.h" 34 #include "opt_inet.h" 35 #include "opt_inet6.h" 36 #include "opt_ratelimit.h" 37 #include "opt_rss.h" 38 39 #include <sys/param.h> 40 #include <sys/conf.h> 41 #include <sys/priv.h> 42 #include <sys/kernel.h> 43 #include <sys/bus.h> 44 #include <sys/module.h> 45 #include <sys/malloc.h> 46 #include <sys/queue.h> 47 #include <sys/taskqueue.h> 48 #include <sys/pciio.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pci_private.h> 52 #include <sys/firmware.h> 53 #include <sys/sbuf.h> 54 #include <sys/smp.h> 55 #include <sys/socket.h> 56 #include <sys/sockio.h> 57 #include <sys/sysctl.h> 58 #include <net/ethernet.h> 59 #include <net/if.h> 60 #include <net/if_types.h> 61 #include <net/if_dl.h> 62 #include <net/if_vlan_var.h> 63 #ifdef RSS 64 #include <net/rss_config.h> 65 #endif 66 #include <netinet/in.h> 67 #include <netinet/ip.h> 68 #if defined(__i386__) || defined(__amd64__) 69 #include <machine/md_var.h> 70 #include <machine/cputypes.h> 71 #include <vm/vm.h> 72 #include <vm/pmap.h> 73 #endif 74 #include <crypto/rijndael/rijndael.h> 75 #ifdef DDB 76 #include <ddb/ddb.h> 77 #include <ddb/db_lex.h> 78 #endif 79 80 #include "common/common.h" 81 #include "common/t4_msg.h" 82 #include "common/t4_regs.h" 83 #include "common/t4_regs_values.h" 84 #include "cudbg/cudbg.h" 85 #include "t4_clip.h" 86 #include "t4_ioctl.h" 87 #include "t4_l2t.h" 88 #include "t4_mp_ring.h" 89 #include "t4_if.h" 90 #include "t4_smt.h" 91 92 /* T4 bus driver interface */ 93 static int t4_probe(device_t); 94 static int t4_attach(device_t); 95 static int t4_detach(device_t); 96 static int t4_child_location_str(device_t, device_t, char *, size_t); 97 static int t4_ready(device_t); 98 static int t4_read_port_device(device_t, int, device_t *); 99 static device_method_t t4_methods[] = { 100 DEVMETHOD(device_probe, t4_probe), 101 DEVMETHOD(device_attach, t4_attach), 102 DEVMETHOD(device_detach, t4_detach), 103 104 DEVMETHOD(bus_child_location_str, t4_child_location_str), 105 106 DEVMETHOD(t4_is_main_ready, t4_ready), 107 DEVMETHOD(t4_read_port_device, t4_read_port_device), 108 109 DEVMETHOD_END 110 }; 111 static driver_t t4_driver = { 112 "t4nex", 113 t4_methods, 114 sizeof(struct adapter) 115 }; 116 117 118 /* T4 port (cxgbe) interface */ 119 static int cxgbe_probe(device_t); 120 static int cxgbe_attach(device_t); 121 static int cxgbe_detach(device_t); 122 device_method_t cxgbe_methods[] = { 123 DEVMETHOD(device_probe, cxgbe_probe), 124 DEVMETHOD(device_attach, cxgbe_attach), 125 DEVMETHOD(device_detach, cxgbe_detach), 126 { 0, 0 } 127 }; 128 static driver_t cxgbe_driver = { 129 "cxgbe", 130 cxgbe_methods, 131 sizeof(struct port_info) 132 }; 133 134 /* T4 VI (vcxgbe) interface */ 135 static int vcxgbe_probe(device_t); 136 static int vcxgbe_attach(device_t); 137 static int vcxgbe_detach(device_t); 138 static device_method_t vcxgbe_methods[] = { 139 DEVMETHOD(device_probe, vcxgbe_probe), 140 DEVMETHOD(device_attach, vcxgbe_attach), 141 DEVMETHOD(device_detach, vcxgbe_detach), 142 { 0, 0 } 143 }; 144 static driver_t vcxgbe_driver = { 145 "vcxgbe", 146 vcxgbe_methods, 147 sizeof(struct vi_info) 148 }; 149 150 static d_ioctl_t t4_ioctl; 151 152 static struct cdevsw t4_cdevsw = { 153 .d_version = D_VERSION, 154 .d_ioctl = t4_ioctl, 155 .d_name = "t4nex", 156 }; 157 158 /* T5 bus driver interface */ 159 static int t5_probe(device_t); 160 static device_method_t t5_methods[] = { 161 DEVMETHOD(device_probe, t5_probe), 162 DEVMETHOD(device_attach, t4_attach), 163 DEVMETHOD(device_detach, t4_detach), 164 165 DEVMETHOD(bus_child_location_str, t4_child_location_str), 166 167 DEVMETHOD(t4_is_main_ready, t4_ready), 168 DEVMETHOD(t4_read_port_device, t4_read_port_device), 169 170 DEVMETHOD_END 171 }; 172 static driver_t t5_driver = { 173 "t5nex", 174 t5_methods, 175 sizeof(struct adapter) 176 }; 177 178 179 /* T5 port (cxl) interface */ 180 static driver_t cxl_driver = { 181 "cxl", 182 cxgbe_methods, 183 sizeof(struct port_info) 184 }; 185 186 /* T5 VI (vcxl) interface */ 187 static driver_t vcxl_driver = { 188 "vcxl", 189 vcxgbe_methods, 190 sizeof(struct vi_info) 191 }; 192 193 /* T6 bus driver interface */ 194 static int t6_probe(device_t); 195 static device_method_t t6_methods[] = { 196 DEVMETHOD(device_probe, t6_probe), 197 DEVMETHOD(device_attach, t4_attach), 198 DEVMETHOD(device_detach, t4_detach), 199 200 DEVMETHOD(bus_child_location_str, t4_child_location_str), 201 202 DEVMETHOD(t4_is_main_ready, t4_ready), 203 DEVMETHOD(t4_read_port_device, t4_read_port_device), 204 205 DEVMETHOD_END 206 }; 207 static driver_t t6_driver = { 208 "t6nex", 209 t6_methods, 210 sizeof(struct adapter) 211 }; 212 213 214 /* T6 port (cc) interface */ 215 static driver_t cc_driver = { 216 "cc", 217 cxgbe_methods, 218 sizeof(struct port_info) 219 }; 220 221 /* T6 VI (vcc) interface */ 222 static driver_t vcc_driver = { 223 "vcc", 224 vcxgbe_methods, 225 sizeof(struct vi_info) 226 }; 227 228 /* ifnet interface */ 229 static void cxgbe_init(void *); 230 static int cxgbe_ioctl(struct ifnet *, unsigned long, caddr_t); 231 static int cxgbe_transmit(struct ifnet *, struct mbuf *); 232 static void cxgbe_qflush(struct ifnet *); 233 234 MALLOC_DEFINE(M_CXGBE, "cxgbe", "Chelsio T4/T5 Ethernet driver and services"); 235 236 /* 237 * Correct lock order when you need to acquire multiple locks is t4_list_lock, 238 * then ADAPTER_LOCK, then t4_uld_list_lock. 239 */ 240 static struct sx t4_list_lock; 241 SLIST_HEAD(, adapter) t4_list; 242 #ifdef TCP_OFFLOAD 243 static struct sx t4_uld_list_lock; 244 SLIST_HEAD(, uld_info) t4_uld_list; 245 #endif 246 247 /* 248 * Tunables. See tweak_tunables() too. 249 * 250 * Each tunable is set to a default value here if it's known at compile-time. 251 * Otherwise it is set to -n as an indication to tweak_tunables() that it should 252 * provide a reasonable default (upto n) when the driver is loaded. 253 * 254 * Tunables applicable to both T4 and T5 are under hw.cxgbe. Those specific to 255 * T5 are under hw.cxl. 256 */ 257 SYSCTL_NODE(_hw, OID_AUTO, cxgbe, CTLFLAG_RD, 0, "cxgbe(4) parameters"); 258 SYSCTL_NODE(_hw, OID_AUTO, cxl, CTLFLAG_RD, 0, "cxgbe(4) T5+ parameters"); 259 SYSCTL_NODE(_hw_cxgbe, OID_AUTO, toe, CTLFLAG_RD, 0, "cxgbe(4) TOE parameters"); 260 261 /* 262 * Number of queues for tx and rx, NIC and offload. 263 */ 264 #define NTXQ 16 265 int t4_ntxq = -NTXQ; 266 SYSCTL_INT(_hw_cxgbe, OID_AUTO, ntxq, CTLFLAG_RDTUN, &t4_ntxq, 0, 267 "Number of TX queues per port"); 268 TUNABLE_INT("hw.cxgbe.ntxq10g", &t4_ntxq); /* Old name, undocumented */ 269 270 #define NRXQ 8 271 int t4_nrxq = -NRXQ; 272 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nrxq, CTLFLAG_RDTUN, &t4_nrxq, 0, 273 "Number of RX queues per port"); 274 TUNABLE_INT("hw.cxgbe.nrxq10g", &t4_nrxq); /* Old name, undocumented */ 275 276 #define NTXQ_VI 1 277 static int t4_ntxq_vi = -NTXQ_VI; 278 SYSCTL_INT(_hw_cxgbe, OID_AUTO, ntxq_vi, CTLFLAG_RDTUN, &t4_ntxq_vi, 0, 279 "Number of TX queues per VI"); 280 281 #define NRXQ_VI 1 282 static int t4_nrxq_vi = -NRXQ_VI; 283 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nrxq_vi, CTLFLAG_RDTUN, &t4_nrxq_vi, 0, 284 "Number of RX queues per VI"); 285 286 static int t4_rsrv_noflowq = 0; 287 SYSCTL_INT(_hw_cxgbe, OID_AUTO, rsrv_noflowq, CTLFLAG_RDTUN, &t4_rsrv_noflowq, 288 0, "Reserve TX queue 0 of each VI for non-flowid packets"); 289 290 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 291 #define NOFLDTXQ 8 292 static int t4_nofldtxq = -NOFLDTXQ; 293 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldtxq, CTLFLAG_RDTUN, &t4_nofldtxq, 0, 294 "Number of offload TX queues per port"); 295 296 #define NOFLDRXQ 2 297 static int t4_nofldrxq = -NOFLDRXQ; 298 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldrxq, CTLFLAG_RDTUN, &t4_nofldrxq, 0, 299 "Number of offload RX queues per port"); 300 301 #define NOFLDTXQ_VI 1 302 static int t4_nofldtxq_vi = -NOFLDTXQ_VI; 303 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldtxq_vi, CTLFLAG_RDTUN, &t4_nofldtxq_vi, 0, 304 "Number of offload TX queues per VI"); 305 306 #define NOFLDRXQ_VI 1 307 static int t4_nofldrxq_vi = -NOFLDRXQ_VI; 308 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldrxq_vi, CTLFLAG_RDTUN, &t4_nofldrxq_vi, 0, 309 "Number of offload RX queues per VI"); 310 311 #define TMR_IDX_OFLD 1 312 int t4_tmr_idx_ofld = TMR_IDX_OFLD; 313 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx_ofld, CTLFLAG_RDTUN, 314 &t4_tmr_idx_ofld, 0, "Holdoff timer index for offload queues"); 315 316 #define PKTC_IDX_OFLD (-1) 317 int t4_pktc_idx_ofld = PKTC_IDX_OFLD; 318 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx_ofld, CTLFLAG_RDTUN, 319 &t4_pktc_idx_ofld, 0, "holdoff packet counter index for offload queues"); 320 321 /* 0 means chip/fw default, non-zero number is value in microseconds */ 322 static u_long t4_toe_keepalive_idle = 0; 323 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, keepalive_idle, CTLFLAG_RDTUN, 324 &t4_toe_keepalive_idle, 0, "TOE keepalive idle timer (us)"); 325 326 /* 0 means chip/fw default, non-zero number is value in microseconds */ 327 static u_long t4_toe_keepalive_interval = 0; 328 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, keepalive_interval, CTLFLAG_RDTUN, 329 &t4_toe_keepalive_interval, 0, "TOE keepalive interval timer (us)"); 330 331 /* 0 means chip/fw default, non-zero number is # of keepalives before abort */ 332 static int t4_toe_keepalive_count = 0; 333 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, keepalive_count, CTLFLAG_RDTUN, 334 &t4_toe_keepalive_count, 0, "Number of TOE keepalive probes before abort"); 335 336 /* 0 means chip/fw default, non-zero number is value in microseconds */ 337 static u_long t4_toe_rexmt_min = 0; 338 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, rexmt_min, CTLFLAG_RDTUN, 339 &t4_toe_rexmt_min, 0, "Minimum TOE retransmit interval (us)"); 340 341 /* 0 means chip/fw default, non-zero number is value in microseconds */ 342 static u_long t4_toe_rexmt_max = 0; 343 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, rexmt_max, CTLFLAG_RDTUN, 344 &t4_toe_rexmt_max, 0, "Maximum TOE retransmit interval (us)"); 345 346 /* 0 means chip/fw default, non-zero number is # of rexmt before abort */ 347 static int t4_toe_rexmt_count = 0; 348 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, rexmt_count, CTLFLAG_RDTUN, 349 &t4_toe_rexmt_count, 0, "Number of TOE retransmissions before abort"); 350 351 /* -1 means chip/fw default, other values are raw backoff values to use */ 352 static int t4_toe_rexmt_backoff[16] = { 353 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 354 }; 355 SYSCTL_NODE(_hw_cxgbe_toe, OID_AUTO, rexmt_backoff, CTLFLAG_RD, 0, 356 "cxgbe(4) TOE retransmit backoff values"); 357 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 0, CTLFLAG_RDTUN, 358 &t4_toe_rexmt_backoff[0], 0, ""); 359 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 1, CTLFLAG_RDTUN, 360 &t4_toe_rexmt_backoff[1], 0, ""); 361 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 2, CTLFLAG_RDTUN, 362 &t4_toe_rexmt_backoff[2], 0, ""); 363 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 3, CTLFLAG_RDTUN, 364 &t4_toe_rexmt_backoff[3], 0, ""); 365 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 4, CTLFLAG_RDTUN, 366 &t4_toe_rexmt_backoff[4], 0, ""); 367 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 5, CTLFLAG_RDTUN, 368 &t4_toe_rexmt_backoff[5], 0, ""); 369 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 6, CTLFLAG_RDTUN, 370 &t4_toe_rexmt_backoff[6], 0, ""); 371 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 7, CTLFLAG_RDTUN, 372 &t4_toe_rexmt_backoff[7], 0, ""); 373 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 8, CTLFLAG_RDTUN, 374 &t4_toe_rexmt_backoff[8], 0, ""); 375 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 9, CTLFLAG_RDTUN, 376 &t4_toe_rexmt_backoff[9], 0, ""); 377 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 10, CTLFLAG_RDTUN, 378 &t4_toe_rexmt_backoff[10], 0, ""); 379 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 11, CTLFLAG_RDTUN, 380 &t4_toe_rexmt_backoff[11], 0, ""); 381 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 12, CTLFLAG_RDTUN, 382 &t4_toe_rexmt_backoff[12], 0, ""); 383 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 13, CTLFLAG_RDTUN, 384 &t4_toe_rexmt_backoff[13], 0, ""); 385 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 14, CTLFLAG_RDTUN, 386 &t4_toe_rexmt_backoff[14], 0, ""); 387 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 15, CTLFLAG_RDTUN, 388 &t4_toe_rexmt_backoff[15], 0, ""); 389 #endif 390 391 #ifdef DEV_NETMAP 392 #define NNMTXQ_VI 2 393 static int t4_nnmtxq_vi = -NNMTXQ_VI; 394 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmtxq_vi, CTLFLAG_RDTUN, &t4_nnmtxq_vi, 0, 395 "Number of netmap TX queues per VI"); 396 397 #define NNMRXQ_VI 2 398 static int t4_nnmrxq_vi = -NNMRXQ_VI; 399 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmrxq_vi, CTLFLAG_RDTUN, &t4_nnmrxq_vi, 0, 400 "Number of netmap RX queues per VI"); 401 #endif 402 403 /* 404 * Holdoff parameters for ports. 405 */ 406 #define TMR_IDX 1 407 int t4_tmr_idx = TMR_IDX; 408 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx, CTLFLAG_RDTUN, &t4_tmr_idx, 409 0, "Holdoff timer index"); 410 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_10G", &t4_tmr_idx); /* Old name */ 411 412 #define PKTC_IDX (-1) 413 int t4_pktc_idx = PKTC_IDX; 414 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx, CTLFLAG_RDTUN, &t4_pktc_idx, 415 0, "Holdoff packet counter index"); 416 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_10G", &t4_pktc_idx); /* Old name */ 417 418 /* 419 * Size (# of entries) of each tx and rx queue. 420 */ 421 unsigned int t4_qsize_txq = TX_EQ_QSIZE; 422 SYSCTL_INT(_hw_cxgbe, OID_AUTO, qsize_txq, CTLFLAG_RDTUN, &t4_qsize_txq, 0, 423 "Number of descriptors in each TX queue"); 424 425 unsigned int t4_qsize_rxq = RX_IQ_QSIZE; 426 SYSCTL_INT(_hw_cxgbe, OID_AUTO, qsize_rxq, CTLFLAG_RDTUN, &t4_qsize_rxq, 0, 427 "Number of descriptors in each RX queue"); 428 429 /* 430 * Interrupt types allowed (bits 0, 1, 2 = INTx, MSI, MSI-X respectively). 431 */ 432 int t4_intr_types = INTR_MSIX | INTR_MSI | INTR_INTX; 433 SYSCTL_INT(_hw_cxgbe, OID_AUTO, interrupt_types, CTLFLAG_RDTUN, &t4_intr_types, 434 0, "Interrupt types allowed (bit 0 = INTx, 1 = MSI, 2 = MSI-X)"); 435 436 /* 437 * Configuration file. All the _CF names here are special. 438 */ 439 #define DEFAULT_CF "default" 440 #define BUILTIN_CF "built-in" 441 #define FLASH_CF "flash" 442 #define UWIRE_CF "uwire" 443 #define FPGA_CF "fpga" 444 static char t4_cfg_file[32] = DEFAULT_CF; 445 SYSCTL_STRING(_hw_cxgbe, OID_AUTO, config_file, CTLFLAG_RDTUN, t4_cfg_file, 446 sizeof(t4_cfg_file), "Firmware configuration file"); 447 448 /* 449 * PAUSE settings (bit 0, 1, 2 = rx_pause, tx_pause, pause_autoneg respectively). 450 * rx_pause = 1 to heed incoming PAUSE frames, 0 to ignore them. 451 * tx_pause = 1 to emit PAUSE frames when the rx FIFO reaches its high water 452 * mark or when signalled to do so, 0 to never emit PAUSE. 453 * pause_autoneg = 1 means PAUSE will be negotiated if possible and the 454 * negotiated settings will override rx_pause/tx_pause. 455 * Otherwise rx_pause/tx_pause are applied forcibly. 456 */ 457 static int t4_pause_settings = PAUSE_RX | PAUSE_TX | PAUSE_AUTONEG; 458 SYSCTL_INT(_hw_cxgbe, OID_AUTO, pause_settings, CTLFLAG_RDTUN, 459 &t4_pause_settings, 0, 460 "PAUSE settings (bit 0 = rx_pause, 1 = tx_pause, 2 = pause_autoneg)"); 461 462 /* 463 * Forward Error Correction settings (bit 0, 1 = RS, BASER respectively). 464 * -1 to run with the firmware default. Same as FEC_AUTO (bit 5) 465 * 0 to disable FEC. 466 */ 467 static int t4_fec = -1; 468 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fec, CTLFLAG_RDTUN, &t4_fec, 0, 469 "Forward Error Correction (bit 0 = RS, bit 1 = BASER_RS)"); 470 471 /* 472 * Link autonegotiation. 473 * -1 to run with the firmware default. 474 * 0 to disable. 475 * 1 to enable. 476 */ 477 static int t4_autoneg = -1; 478 SYSCTL_INT(_hw_cxgbe, OID_AUTO, autoneg, CTLFLAG_RDTUN, &t4_autoneg, 0, 479 "Link autonegotiation"); 480 481 /* 482 * Firmware auto-install by driver during attach (0, 1, 2 = prohibited, allowed, 483 * encouraged respectively). '-n' is the same as 'n' except the firmware 484 * version used in the checks is read from the firmware bundled with the driver. 485 */ 486 static int t4_fw_install = 1; 487 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fw_install, CTLFLAG_RDTUN, &t4_fw_install, 0, 488 "Firmware auto-install (0 = prohibited, 1 = allowed, 2 = encouraged)"); 489 490 /* 491 * ASIC features that will be used. Disable the ones you don't want so that the 492 * chip resources aren't wasted on features that will not be used. 493 */ 494 static int t4_nbmcaps_allowed = 0; 495 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nbmcaps_allowed, CTLFLAG_RDTUN, 496 &t4_nbmcaps_allowed, 0, "Default NBM capabilities"); 497 498 static int t4_linkcaps_allowed = 0; /* No DCBX, PPP, etc. by default */ 499 SYSCTL_INT(_hw_cxgbe, OID_AUTO, linkcaps_allowed, CTLFLAG_RDTUN, 500 &t4_linkcaps_allowed, 0, "Default link capabilities"); 501 502 static int t4_switchcaps_allowed = FW_CAPS_CONFIG_SWITCH_INGRESS | 503 FW_CAPS_CONFIG_SWITCH_EGRESS; 504 SYSCTL_INT(_hw_cxgbe, OID_AUTO, switchcaps_allowed, CTLFLAG_RDTUN, 505 &t4_switchcaps_allowed, 0, "Default switch capabilities"); 506 507 #ifdef RATELIMIT 508 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC | 509 FW_CAPS_CONFIG_NIC_HASHFILTER | FW_CAPS_CONFIG_NIC_ETHOFLD; 510 #else 511 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC | 512 FW_CAPS_CONFIG_NIC_HASHFILTER; 513 #endif 514 SYSCTL_INT(_hw_cxgbe, OID_AUTO, niccaps_allowed, CTLFLAG_RDTUN, 515 &t4_niccaps_allowed, 0, "Default NIC capabilities"); 516 517 static int t4_toecaps_allowed = -1; 518 SYSCTL_INT(_hw_cxgbe, OID_AUTO, toecaps_allowed, CTLFLAG_RDTUN, 519 &t4_toecaps_allowed, 0, "Default TCP offload capabilities"); 520 521 static int t4_rdmacaps_allowed = -1; 522 SYSCTL_INT(_hw_cxgbe, OID_AUTO, rdmacaps_allowed, CTLFLAG_RDTUN, 523 &t4_rdmacaps_allowed, 0, "Default RDMA capabilities"); 524 525 static int t4_cryptocaps_allowed = -1; 526 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cryptocaps_allowed, CTLFLAG_RDTUN, 527 &t4_cryptocaps_allowed, 0, "Default crypto capabilities"); 528 529 static int t4_iscsicaps_allowed = -1; 530 SYSCTL_INT(_hw_cxgbe, OID_AUTO, iscsicaps_allowed, CTLFLAG_RDTUN, 531 &t4_iscsicaps_allowed, 0, "Default iSCSI capabilities"); 532 533 static int t4_fcoecaps_allowed = 0; 534 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fcoecaps_allowed, CTLFLAG_RDTUN, 535 &t4_fcoecaps_allowed, 0, "Default FCoE capabilities"); 536 537 static int t5_write_combine = 0; 538 SYSCTL_INT(_hw_cxl, OID_AUTO, write_combine, CTLFLAG_RDTUN, &t5_write_combine, 539 0, "Use WC instead of UC for BAR2"); 540 541 static int t4_num_vis = 1; 542 SYSCTL_INT(_hw_cxgbe, OID_AUTO, num_vis, CTLFLAG_RDTUN, &t4_num_vis, 0, 543 "Number of VIs per port"); 544 545 /* 546 * PCIe Relaxed Ordering. 547 * -1: driver should figure out a good value. 548 * 0: disable RO. 549 * 1: enable RO. 550 * 2: leave RO alone. 551 */ 552 static int pcie_relaxed_ordering = -1; 553 SYSCTL_INT(_hw_cxgbe, OID_AUTO, pcie_relaxed_ordering, CTLFLAG_RDTUN, 554 &pcie_relaxed_ordering, 0, 555 "PCIe Relaxed Ordering: 0 = disable, 1 = enable, 2 = leave alone"); 556 557 static int t4_panic_on_fatal_err = 0; 558 SYSCTL_INT(_hw_cxgbe, OID_AUTO, panic_on_fatal_err, CTLFLAG_RDTUN, 559 &t4_panic_on_fatal_err, 0, "panic on fatal errors"); 560 561 #ifdef TCP_OFFLOAD 562 /* 563 * TOE tunables. 564 */ 565 static int t4_cop_managed_offloading = 0; 566 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cop_managed_offloading, CTLFLAG_RDTUN, 567 &t4_cop_managed_offloading, 0, 568 "COP (Connection Offload Policy) controls all TOE offload"); 569 #endif 570 571 /* Functions used by VIs to obtain unique MAC addresses for each VI. */ 572 static int vi_mac_funcs[] = { 573 FW_VI_FUNC_ETH, 574 FW_VI_FUNC_OFLD, 575 FW_VI_FUNC_IWARP, 576 FW_VI_FUNC_OPENISCSI, 577 FW_VI_FUNC_OPENFCOE, 578 FW_VI_FUNC_FOISCSI, 579 FW_VI_FUNC_FOFCOE, 580 }; 581 582 struct intrs_and_queues { 583 uint16_t intr_type; /* INTx, MSI, or MSI-X */ 584 uint16_t num_vis; /* number of VIs for each port */ 585 uint16_t nirq; /* Total # of vectors */ 586 uint16_t ntxq; /* # of NIC txq's for each port */ 587 uint16_t nrxq; /* # of NIC rxq's for each port */ 588 uint16_t nofldtxq; /* # of TOE/ETHOFLD txq's for each port */ 589 uint16_t nofldrxq; /* # of TOE rxq's for each port */ 590 591 /* The vcxgbe/vcxl interfaces use these and not the ones above. */ 592 uint16_t ntxq_vi; /* # of NIC txq's */ 593 uint16_t nrxq_vi; /* # of NIC rxq's */ 594 uint16_t nofldtxq_vi; /* # of TOE txq's */ 595 uint16_t nofldrxq_vi; /* # of TOE rxq's */ 596 uint16_t nnmtxq_vi; /* # of netmap txq's */ 597 uint16_t nnmrxq_vi; /* # of netmap rxq's */ 598 }; 599 600 static void setup_memwin(struct adapter *); 601 static void position_memwin(struct adapter *, int, uint32_t); 602 static int validate_mem_range(struct adapter *, uint32_t, uint32_t); 603 static int fwmtype_to_hwmtype(int); 604 static int validate_mt_off_len(struct adapter *, int, uint32_t, uint32_t, 605 uint32_t *); 606 static int fixup_devlog_params(struct adapter *); 607 static int cfg_itype_and_nqueues(struct adapter *, struct intrs_and_queues *); 608 static int contact_firmware(struct adapter *); 609 static int partition_resources(struct adapter *); 610 static int get_params__pre_init(struct adapter *); 611 static int set_params__pre_init(struct adapter *); 612 static int get_params__post_init(struct adapter *); 613 static int set_params__post_init(struct adapter *); 614 static void t4_set_desc(struct adapter *); 615 static bool fixed_ifmedia(struct port_info *); 616 static void build_medialist(struct port_info *); 617 static void init_link_config(struct port_info *); 618 static int fixup_link_config(struct port_info *); 619 static int apply_link_config(struct port_info *); 620 static int cxgbe_init_synchronized(struct vi_info *); 621 static int cxgbe_uninit_synchronized(struct vi_info *); 622 static void quiesce_txq(struct adapter *, struct sge_txq *); 623 static void quiesce_wrq(struct adapter *, struct sge_wrq *); 624 static void quiesce_iq(struct adapter *, struct sge_iq *); 625 static void quiesce_fl(struct adapter *, struct sge_fl *); 626 static int t4_alloc_irq(struct adapter *, struct irq *, int rid, 627 driver_intr_t *, void *, char *); 628 static int t4_free_irq(struct adapter *, struct irq *); 629 static void get_regs(struct adapter *, struct t4_regdump *, uint8_t *); 630 static void vi_refresh_stats(struct adapter *, struct vi_info *); 631 static void cxgbe_refresh_stats(struct adapter *, struct port_info *); 632 static void cxgbe_tick(void *); 633 static void cxgbe_sysctls(struct port_info *); 634 static int sysctl_int_array(SYSCTL_HANDLER_ARGS); 635 static int sysctl_bitfield_8b(SYSCTL_HANDLER_ARGS); 636 static int sysctl_bitfield_16b(SYSCTL_HANDLER_ARGS); 637 static int sysctl_btphy(SYSCTL_HANDLER_ARGS); 638 static int sysctl_noflowq(SYSCTL_HANDLER_ARGS); 639 static int sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS); 640 static int sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS); 641 static int sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS); 642 static int sysctl_qsize_txq(SYSCTL_HANDLER_ARGS); 643 static int sysctl_pause_settings(SYSCTL_HANDLER_ARGS); 644 static int sysctl_fec(SYSCTL_HANDLER_ARGS); 645 static int sysctl_autoneg(SYSCTL_HANDLER_ARGS); 646 static int sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS); 647 static int sysctl_temperature(SYSCTL_HANDLER_ARGS); 648 static int sysctl_loadavg(SYSCTL_HANDLER_ARGS); 649 static int sysctl_cctrl(SYSCTL_HANDLER_ARGS); 650 static int sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS); 651 static int sysctl_cim_la(SYSCTL_HANDLER_ARGS); 652 static int sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS); 653 static int sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS); 654 static int sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS); 655 static int sysctl_cpl_stats(SYSCTL_HANDLER_ARGS); 656 static int sysctl_ddp_stats(SYSCTL_HANDLER_ARGS); 657 static int sysctl_devlog(SYSCTL_HANDLER_ARGS); 658 static int sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS); 659 static int sysctl_hw_sched(SYSCTL_HANDLER_ARGS); 660 static int sysctl_lb_stats(SYSCTL_HANDLER_ARGS); 661 static int sysctl_linkdnrc(SYSCTL_HANDLER_ARGS); 662 static int sysctl_meminfo(SYSCTL_HANDLER_ARGS); 663 static int sysctl_mps_tcam(SYSCTL_HANDLER_ARGS); 664 static int sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS); 665 static int sysctl_path_mtus(SYSCTL_HANDLER_ARGS); 666 static int sysctl_pm_stats(SYSCTL_HANDLER_ARGS); 667 static int sysctl_rdma_stats(SYSCTL_HANDLER_ARGS); 668 static int sysctl_tcp_stats(SYSCTL_HANDLER_ARGS); 669 static int sysctl_tids(SYSCTL_HANDLER_ARGS); 670 static int sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS); 671 static int sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS); 672 static int sysctl_tp_la(SYSCTL_HANDLER_ARGS); 673 static int sysctl_tx_rate(SYSCTL_HANDLER_ARGS); 674 static int sysctl_ulprx_la(SYSCTL_HANDLER_ARGS); 675 static int sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS); 676 static int sysctl_cpus(SYSCTL_HANDLER_ARGS); 677 #ifdef TCP_OFFLOAD 678 static int sysctl_tls_rx_ports(SYSCTL_HANDLER_ARGS); 679 static int sysctl_tp_tick(SYSCTL_HANDLER_ARGS); 680 static int sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS); 681 static int sysctl_tp_timer(SYSCTL_HANDLER_ARGS); 682 static int sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS); 683 static int sysctl_tp_backoff(SYSCTL_HANDLER_ARGS); 684 static int sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS); 685 static int sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS); 686 #endif 687 static int get_sge_context(struct adapter *, struct t4_sge_context *); 688 static int load_fw(struct adapter *, struct t4_data *); 689 static int load_cfg(struct adapter *, struct t4_data *); 690 static int load_boot(struct adapter *, struct t4_bootrom *); 691 static int load_bootcfg(struct adapter *, struct t4_data *); 692 static int cudbg_dump(struct adapter *, struct t4_cudbg_dump *); 693 static void free_offload_policy(struct t4_offload_policy *); 694 static int set_offload_policy(struct adapter *, struct t4_offload_policy *); 695 static int read_card_mem(struct adapter *, int, struct t4_mem_range *); 696 static int read_i2c(struct adapter *, struct t4_i2c_data *); 697 #ifdef TCP_OFFLOAD 698 static int toe_capability(struct vi_info *, int); 699 #endif 700 static int mod_event(module_t, int, void *); 701 static int notify_siblings(device_t, int); 702 703 struct { 704 uint16_t device; 705 char *desc; 706 } t4_pciids[] = { 707 {0xa000, "Chelsio Terminator 4 FPGA"}, 708 {0x4400, "Chelsio T440-dbg"}, 709 {0x4401, "Chelsio T420-CR"}, 710 {0x4402, "Chelsio T422-CR"}, 711 {0x4403, "Chelsio T440-CR"}, 712 {0x4404, "Chelsio T420-BCH"}, 713 {0x4405, "Chelsio T440-BCH"}, 714 {0x4406, "Chelsio T440-CH"}, 715 {0x4407, "Chelsio T420-SO"}, 716 {0x4408, "Chelsio T420-CX"}, 717 {0x4409, "Chelsio T420-BT"}, 718 {0x440a, "Chelsio T404-BT"}, 719 {0x440e, "Chelsio T440-LP-CR"}, 720 }, t5_pciids[] = { 721 {0xb000, "Chelsio Terminator 5 FPGA"}, 722 {0x5400, "Chelsio T580-dbg"}, 723 {0x5401, "Chelsio T520-CR"}, /* 2 x 10G */ 724 {0x5402, "Chelsio T522-CR"}, /* 2 x 10G, 2 X 1G */ 725 {0x5403, "Chelsio T540-CR"}, /* 4 x 10G */ 726 {0x5407, "Chelsio T520-SO"}, /* 2 x 10G, nomem */ 727 {0x5409, "Chelsio T520-BT"}, /* 2 x 10GBaseT */ 728 {0x540a, "Chelsio T504-BT"}, /* 4 x 1G */ 729 {0x540d, "Chelsio T580-CR"}, /* 2 x 40G */ 730 {0x540e, "Chelsio T540-LP-CR"}, /* 4 x 10G */ 731 {0x5410, "Chelsio T580-LP-CR"}, /* 2 x 40G */ 732 {0x5411, "Chelsio T520-LL-CR"}, /* 2 x 10G */ 733 {0x5412, "Chelsio T560-CR"}, /* 1 x 40G, 2 x 10G */ 734 {0x5414, "Chelsio T580-LP-SO-CR"}, /* 2 x 40G, nomem */ 735 {0x5415, "Chelsio T502-BT"}, /* 2 x 1G */ 736 {0x5418, "Chelsio T540-BT"}, /* 4 x 10GBaseT */ 737 {0x5419, "Chelsio T540-LP-BT"}, /* 4 x 10GBaseT */ 738 {0x541a, "Chelsio T540-SO-BT"}, /* 4 x 10GBaseT, nomem */ 739 {0x541b, "Chelsio T540-SO-CR"}, /* 4 x 10G, nomem */ 740 741 /* Custom */ 742 {0x5483, "Custom T540-CR"}, 743 {0x5484, "Custom T540-BT"}, 744 }, t6_pciids[] = { 745 {0xc006, "Chelsio Terminator 6 FPGA"}, /* T6 PE10K6 FPGA (PF0) */ 746 {0x6400, "Chelsio T6-DBG-25"}, /* 2 x 10/25G, debug */ 747 {0x6401, "Chelsio T6225-CR"}, /* 2 x 10/25G */ 748 {0x6402, "Chelsio T6225-SO-CR"}, /* 2 x 10/25G, nomem */ 749 {0x6403, "Chelsio T6425-CR"}, /* 4 x 10/25G */ 750 {0x6404, "Chelsio T6425-SO-CR"}, /* 4 x 10/25G, nomem */ 751 {0x6405, "Chelsio T6225-OCP-SO"}, /* 2 x 10/25G, nomem */ 752 {0x6406, "Chelsio T62100-OCP-SO"}, /* 2 x 40/50/100G, nomem */ 753 {0x6407, "Chelsio T62100-LP-CR"}, /* 2 x 40/50/100G */ 754 {0x6408, "Chelsio T62100-SO-CR"}, /* 2 x 40/50/100G, nomem */ 755 {0x6409, "Chelsio T6210-BT"}, /* 2 x 10GBASE-T */ 756 {0x640d, "Chelsio T62100-CR"}, /* 2 x 40/50/100G */ 757 {0x6410, "Chelsio T6-DBG-100"}, /* 2 x 40/50/100G, debug */ 758 {0x6411, "Chelsio T6225-LL-CR"}, /* 2 x 10/25G */ 759 {0x6414, "Chelsio T61100-OCP-SO"}, /* 1 x 40/50/100G, nomem */ 760 {0x6415, "Chelsio T6201-BT"}, /* 2 x 1000BASE-T */ 761 762 /* Custom */ 763 {0x6480, "Custom T6225-CR"}, 764 {0x6481, "Custom T62100-CR"}, 765 {0x6482, "Custom T6225-CR"}, 766 {0x6483, "Custom T62100-CR"}, 767 {0x6484, "Custom T64100-CR"}, 768 {0x6485, "Custom T6240-SO"}, 769 {0x6486, "Custom T6225-SO-CR"}, 770 {0x6487, "Custom T6225-CR"}, 771 }; 772 773 #ifdef TCP_OFFLOAD 774 /* 775 * service_iq_fl() has an iq and needs the fl. Offset of fl from the iq should 776 * be exactly the same for both rxq and ofld_rxq. 777 */ 778 CTASSERT(offsetof(struct sge_ofld_rxq, iq) == offsetof(struct sge_rxq, iq)); 779 CTASSERT(offsetof(struct sge_ofld_rxq, fl) == offsetof(struct sge_rxq, fl)); 780 #endif 781 CTASSERT(sizeof(struct cluster_metadata) <= CL_METADATA_SIZE); 782 783 static int 784 t4_probe(device_t dev) 785 { 786 int i; 787 uint16_t v = pci_get_vendor(dev); 788 uint16_t d = pci_get_device(dev); 789 uint8_t f = pci_get_function(dev); 790 791 if (v != PCI_VENDOR_ID_CHELSIO) 792 return (ENXIO); 793 794 /* Attach only to PF0 of the FPGA */ 795 if (d == 0xa000 && f != 0) 796 return (ENXIO); 797 798 for (i = 0; i < nitems(t4_pciids); i++) { 799 if (d == t4_pciids[i].device) { 800 device_set_desc(dev, t4_pciids[i].desc); 801 return (BUS_PROBE_DEFAULT); 802 } 803 } 804 805 return (ENXIO); 806 } 807 808 static int 809 t5_probe(device_t dev) 810 { 811 int i; 812 uint16_t v = pci_get_vendor(dev); 813 uint16_t d = pci_get_device(dev); 814 uint8_t f = pci_get_function(dev); 815 816 if (v != PCI_VENDOR_ID_CHELSIO) 817 return (ENXIO); 818 819 /* Attach only to PF0 of the FPGA */ 820 if (d == 0xb000 && f != 0) 821 return (ENXIO); 822 823 for (i = 0; i < nitems(t5_pciids); i++) { 824 if (d == t5_pciids[i].device) { 825 device_set_desc(dev, t5_pciids[i].desc); 826 return (BUS_PROBE_DEFAULT); 827 } 828 } 829 830 return (ENXIO); 831 } 832 833 static int 834 t6_probe(device_t dev) 835 { 836 int i; 837 uint16_t v = pci_get_vendor(dev); 838 uint16_t d = pci_get_device(dev); 839 840 if (v != PCI_VENDOR_ID_CHELSIO) 841 return (ENXIO); 842 843 for (i = 0; i < nitems(t6_pciids); i++) { 844 if (d == t6_pciids[i].device) { 845 device_set_desc(dev, t6_pciids[i].desc); 846 return (BUS_PROBE_DEFAULT); 847 } 848 } 849 850 return (ENXIO); 851 } 852 853 static void 854 t5_attribute_workaround(device_t dev) 855 { 856 device_t root_port; 857 uint32_t v; 858 859 /* 860 * The T5 chips do not properly echo the No Snoop and Relaxed 861 * Ordering attributes when replying to a TLP from a Root 862 * Port. As a workaround, find the parent Root Port and 863 * disable No Snoop and Relaxed Ordering. Note that this 864 * affects all devices under this root port. 865 */ 866 root_port = pci_find_pcie_root_port(dev); 867 if (root_port == NULL) { 868 device_printf(dev, "Unable to find parent root port\n"); 869 return; 870 } 871 872 v = pcie_adjust_config(root_port, PCIER_DEVICE_CTL, 873 PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE, 0, 2); 874 if ((v & (PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE)) != 875 0) 876 device_printf(dev, "Disabled No Snoop/Relaxed Ordering on %s\n", 877 device_get_nameunit(root_port)); 878 } 879 880 static const struct devnames devnames[] = { 881 { 882 .nexus_name = "t4nex", 883 .ifnet_name = "cxgbe", 884 .vi_ifnet_name = "vcxgbe", 885 .pf03_drv_name = "t4iov", 886 .vf_nexus_name = "t4vf", 887 .vf_ifnet_name = "cxgbev" 888 }, { 889 .nexus_name = "t5nex", 890 .ifnet_name = "cxl", 891 .vi_ifnet_name = "vcxl", 892 .pf03_drv_name = "t5iov", 893 .vf_nexus_name = "t5vf", 894 .vf_ifnet_name = "cxlv" 895 }, { 896 .nexus_name = "t6nex", 897 .ifnet_name = "cc", 898 .vi_ifnet_name = "vcc", 899 .pf03_drv_name = "t6iov", 900 .vf_nexus_name = "t6vf", 901 .vf_ifnet_name = "ccv" 902 } 903 }; 904 905 void 906 t4_init_devnames(struct adapter *sc) 907 { 908 int id; 909 910 id = chip_id(sc); 911 if (id >= CHELSIO_T4 && id - CHELSIO_T4 < nitems(devnames)) 912 sc->names = &devnames[id - CHELSIO_T4]; 913 else { 914 device_printf(sc->dev, "chip id %d is not supported.\n", id); 915 sc->names = NULL; 916 } 917 } 918 919 static int 920 t4_ifnet_unit(struct adapter *sc, struct port_info *pi) 921 { 922 const char *parent, *name; 923 long value; 924 int line, unit; 925 926 line = 0; 927 parent = device_get_nameunit(sc->dev); 928 name = sc->names->ifnet_name; 929 while (resource_find_dev(&line, name, &unit, "at", parent) == 0) { 930 if (resource_long_value(name, unit, "port", &value) == 0 && 931 value == pi->port_id) 932 return (unit); 933 } 934 return (-1); 935 } 936 937 static int 938 t4_attach(device_t dev) 939 { 940 struct adapter *sc; 941 int rc = 0, i, j, rqidx, tqidx, nports; 942 struct make_dev_args mda; 943 struct intrs_and_queues iaq; 944 struct sge *s; 945 uint32_t *buf; 946 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 947 int ofld_tqidx; 948 #endif 949 #ifdef TCP_OFFLOAD 950 int ofld_rqidx; 951 #endif 952 #ifdef DEV_NETMAP 953 int nm_rqidx, nm_tqidx; 954 #endif 955 int num_vis; 956 957 sc = device_get_softc(dev); 958 sc->dev = dev; 959 TUNABLE_INT_FETCH("hw.cxgbe.dflags", &sc->debug_flags); 960 961 if ((pci_get_device(dev) & 0xff00) == 0x5400) 962 t5_attribute_workaround(dev); 963 pci_enable_busmaster(dev); 964 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { 965 uint32_t v; 966 967 pci_set_max_read_req(dev, 4096); 968 v = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2); 969 sc->params.pci.mps = 128 << ((v & PCIEM_CTL_MAX_PAYLOAD) >> 5); 970 if (pcie_relaxed_ordering == 0 && 971 (v & PCIEM_CTL_RELAXED_ORD_ENABLE) != 0) { 972 v &= ~PCIEM_CTL_RELAXED_ORD_ENABLE; 973 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2); 974 } else if (pcie_relaxed_ordering == 1 && 975 (v & PCIEM_CTL_RELAXED_ORD_ENABLE) == 0) { 976 v |= PCIEM_CTL_RELAXED_ORD_ENABLE; 977 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2); 978 } 979 } 980 981 sc->sge_gts_reg = MYPF_REG(A_SGE_PF_GTS); 982 sc->sge_kdoorbell_reg = MYPF_REG(A_SGE_PF_KDOORBELL); 983 sc->traceq = -1; 984 mtx_init(&sc->ifp_lock, sc->ifp_lockname, 0, MTX_DEF); 985 snprintf(sc->ifp_lockname, sizeof(sc->ifp_lockname), "%s tracer", 986 device_get_nameunit(dev)); 987 988 snprintf(sc->lockname, sizeof(sc->lockname), "%s", 989 device_get_nameunit(dev)); 990 mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF); 991 t4_add_adapter(sc); 992 993 mtx_init(&sc->sfl_lock, "starving freelists", 0, MTX_DEF); 994 TAILQ_INIT(&sc->sfl); 995 callout_init_mtx(&sc->sfl_callout, &sc->sfl_lock, 0); 996 997 mtx_init(&sc->reg_lock, "indirect register access", 0, MTX_DEF); 998 999 sc->policy = NULL; 1000 rw_init(&sc->policy_lock, "connection offload policy"); 1001 1002 rc = t4_map_bars_0_and_4(sc); 1003 if (rc != 0) 1004 goto done; /* error message displayed already */ 1005 1006 memset(sc->chan_map, 0xff, sizeof(sc->chan_map)); 1007 1008 /* Prepare the adapter for operation. */ 1009 buf = malloc(PAGE_SIZE, M_CXGBE, M_ZERO | M_WAITOK); 1010 rc = -t4_prep_adapter(sc, buf); 1011 free(buf, M_CXGBE); 1012 if (rc != 0) { 1013 device_printf(dev, "failed to prepare adapter: %d.\n", rc); 1014 goto done; 1015 } 1016 1017 /* 1018 * This is the real PF# to which we're attaching. Works from within PCI 1019 * passthrough environments too, where pci_get_function() could return a 1020 * different PF# depending on the passthrough configuration. We need to 1021 * use the real PF# in all our communication with the firmware. 1022 */ 1023 j = t4_read_reg(sc, A_PL_WHOAMI); 1024 sc->pf = chip_id(sc) <= CHELSIO_T5 ? G_SOURCEPF(j) : G_T6_SOURCEPF(j); 1025 sc->mbox = sc->pf; 1026 1027 t4_init_devnames(sc); 1028 if (sc->names == NULL) { 1029 rc = ENOTSUP; 1030 goto done; /* error message displayed already */ 1031 } 1032 1033 /* 1034 * Do this really early, with the memory windows set up even before the 1035 * character device. The userland tool's register i/o and mem read 1036 * will work even in "recovery mode". 1037 */ 1038 setup_memwin(sc); 1039 if (t4_init_devlog_params(sc, 0) == 0) 1040 fixup_devlog_params(sc); 1041 make_dev_args_init(&mda); 1042 mda.mda_devsw = &t4_cdevsw; 1043 mda.mda_uid = UID_ROOT; 1044 mda.mda_gid = GID_WHEEL; 1045 mda.mda_mode = 0600; 1046 mda.mda_si_drv1 = sc; 1047 rc = make_dev_s(&mda, &sc->cdev, "%s", device_get_nameunit(dev)); 1048 if (rc != 0) 1049 device_printf(dev, "failed to create nexus char device: %d.\n", 1050 rc); 1051 1052 /* Go no further if recovery mode has been requested. */ 1053 if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) { 1054 device_printf(dev, "recovery mode.\n"); 1055 goto done; 1056 } 1057 1058 #if defined(__i386__) 1059 if ((cpu_feature & CPUID_CX8) == 0) { 1060 device_printf(dev, "64 bit atomics not available.\n"); 1061 rc = ENOTSUP; 1062 goto done; 1063 } 1064 #endif 1065 1066 /* Contact the firmware and try to become the master driver. */ 1067 rc = contact_firmware(sc); 1068 if (rc != 0) 1069 goto done; /* error message displayed already */ 1070 MPASS(sc->flags & FW_OK); 1071 1072 rc = get_params__pre_init(sc); 1073 if (rc != 0) 1074 goto done; /* error message displayed already */ 1075 1076 if (sc->flags & MASTER_PF) { 1077 rc = partition_resources(sc); 1078 if (rc != 0) 1079 goto done; /* error message displayed already */ 1080 t4_intr_clear(sc); 1081 } 1082 1083 rc = get_params__post_init(sc); 1084 if (rc != 0) 1085 goto done; /* error message displayed already */ 1086 1087 rc = set_params__post_init(sc); 1088 if (rc != 0) 1089 goto done; /* error message displayed already */ 1090 1091 rc = t4_map_bar_2(sc); 1092 if (rc != 0) 1093 goto done; /* error message displayed already */ 1094 1095 rc = t4_create_dma_tag(sc); 1096 if (rc != 0) 1097 goto done; /* error message displayed already */ 1098 1099 /* 1100 * First pass over all the ports - allocate VIs and initialize some 1101 * basic parameters like mac address, port type, etc. 1102 */ 1103 for_each_port(sc, i) { 1104 struct port_info *pi; 1105 1106 pi = malloc(sizeof(*pi), M_CXGBE, M_ZERO | M_WAITOK); 1107 sc->port[i] = pi; 1108 1109 /* These must be set before t4_port_init */ 1110 pi->adapter = sc; 1111 pi->port_id = i; 1112 /* 1113 * XXX: vi[0] is special so we can't delay this allocation until 1114 * pi->nvi's final value is known. 1115 */ 1116 pi->vi = malloc(sizeof(struct vi_info) * t4_num_vis, M_CXGBE, 1117 M_ZERO | M_WAITOK); 1118 1119 /* 1120 * Allocate the "main" VI and initialize parameters 1121 * like mac addr. 1122 */ 1123 rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i); 1124 if (rc != 0) { 1125 device_printf(dev, "unable to initialize port %d: %d\n", 1126 i, rc); 1127 free(pi->vi, M_CXGBE); 1128 free(pi, M_CXGBE); 1129 sc->port[i] = NULL; 1130 goto done; 1131 } 1132 1133 snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d", 1134 device_get_nameunit(dev), i); 1135 mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF); 1136 sc->chan_map[pi->tx_chan] = i; 1137 1138 /* All VIs on this port share this media. */ 1139 ifmedia_init(&pi->media, IFM_IMASK, cxgbe_media_change, 1140 cxgbe_media_status); 1141 1142 PORT_LOCK(pi); 1143 init_link_config(pi); 1144 fixup_link_config(pi); 1145 build_medialist(pi); 1146 if (fixed_ifmedia(pi)) 1147 pi->flags |= FIXED_IFMEDIA; 1148 PORT_UNLOCK(pi); 1149 1150 pi->dev = device_add_child(dev, sc->names->ifnet_name, 1151 t4_ifnet_unit(sc, pi)); 1152 if (pi->dev == NULL) { 1153 device_printf(dev, 1154 "failed to add device for port %d.\n", i); 1155 rc = ENXIO; 1156 goto done; 1157 } 1158 pi->vi[0].dev = pi->dev; 1159 device_set_softc(pi->dev, pi); 1160 } 1161 1162 /* 1163 * Interrupt type, # of interrupts, # of rx/tx queues, etc. 1164 */ 1165 nports = sc->params.nports; 1166 rc = cfg_itype_and_nqueues(sc, &iaq); 1167 if (rc != 0) 1168 goto done; /* error message displayed already */ 1169 1170 num_vis = iaq.num_vis; 1171 sc->intr_type = iaq.intr_type; 1172 sc->intr_count = iaq.nirq; 1173 1174 s = &sc->sge; 1175 s->nrxq = nports * iaq.nrxq; 1176 s->ntxq = nports * iaq.ntxq; 1177 if (num_vis > 1) { 1178 s->nrxq += nports * (num_vis - 1) * iaq.nrxq_vi; 1179 s->ntxq += nports * (num_vis - 1) * iaq.ntxq_vi; 1180 } 1181 s->neq = s->ntxq + s->nrxq; /* the free list in an rxq is an eq */ 1182 s->neq += nports; /* ctrl queues: 1 per port */ 1183 s->niq = s->nrxq + 1; /* 1 extra for firmware event queue */ 1184 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1185 if (is_offload(sc) || is_ethoffload(sc)) { 1186 s->nofldtxq = nports * iaq.nofldtxq; 1187 if (num_vis > 1) 1188 s->nofldtxq += nports * (num_vis - 1) * iaq.nofldtxq_vi; 1189 s->neq += s->nofldtxq; 1190 1191 s->ofld_txq = malloc(s->nofldtxq * sizeof(struct sge_wrq), 1192 M_CXGBE, M_ZERO | M_WAITOK); 1193 } 1194 #endif 1195 #ifdef TCP_OFFLOAD 1196 if (is_offload(sc)) { 1197 s->nofldrxq = nports * iaq.nofldrxq; 1198 if (num_vis > 1) 1199 s->nofldrxq += nports * (num_vis - 1) * iaq.nofldrxq_vi; 1200 s->neq += s->nofldrxq; /* free list */ 1201 s->niq += s->nofldrxq; 1202 1203 s->ofld_rxq = malloc(s->nofldrxq * sizeof(struct sge_ofld_rxq), 1204 M_CXGBE, M_ZERO | M_WAITOK); 1205 } 1206 #endif 1207 #ifdef DEV_NETMAP 1208 if (num_vis > 1) { 1209 s->nnmrxq = nports * (num_vis - 1) * iaq.nnmrxq_vi; 1210 s->nnmtxq = nports * (num_vis - 1) * iaq.nnmtxq_vi; 1211 } 1212 s->neq += s->nnmtxq + s->nnmrxq; 1213 s->niq += s->nnmrxq; 1214 1215 s->nm_rxq = malloc(s->nnmrxq * sizeof(struct sge_nm_rxq), 1216 M_CXGBE, M_ZERO | M_WAITOK); 1217 s->nm_txq = malloc(s->nnmtxq * sizeof(struct sge_nm_txq), 1218 M_CXGBE, M_ZERO | M_WAITOK); 1219 #endif 1220 1221 s->ctrlq = malloc(nports * sizeof(struct sge_wrq), M_CXGBE, 1222 M_ZERO | M_WAITOK); 1223 s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE, 1224 M_ZERO | M_WAITOK); 1225 s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE, 1226 M_ZERO | M_WAITOK); 1227 s->iqmap = malloc(s->niq * sizeof(struct sge_iq *), M_CXGBE, 1228 M_ZERO | M_WAITOK); 1229 s->eqmap = malloc(s->neq * sizeof(struct sge_eq *), M_CXGBE, 1230 M_ZERO | M_WAITOK); 1231 1232 sc->irq = malloc(sc->intr_count * sizeof(struct irq), M_CXGBE, 1233 M_ZERO | M_WAITOK); 1234 1235 t4_init_l2t(sc, M_WAITOK); 1236 t4_init_smt(sc, M_WAITOK); 1237 t4_init_tx_sched(sc); 1238 #ifdef RATELIMIT 1239 t4_init_etid_table(sc); 1240 #endif 1241 #ifdef INET6 1242 t4_init_clip_table(sc); 1243 #endif 1244 if (sc->vres.key.size != 0) 1245 sc->key_map = vmem_create("T4TLS key map", sc->vres.key.start, 1246 sc->vres.key.size, 32, 0, M_FIRSTFIT | M_WAITOK); 1247 1248 /* 1249 * Second pass over the ports. This time we know the number of rx and 1250 * tx queues that each port should get. 1251 */ 1252 rqidx = tqidx = 0; 1253 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1254 ofld_tqidx = 0; 1255 #endif 1256 #ifdef TCP_OFFLOAD 1257 ofld_rqidx = 0; 1258 #endif 1259 #ifdef DEV_NETMAP 1260 nm_rqidx = nm_tqidx = 0; 1261 #endif 1262 for_each_port(sc, i) { 1263 struct port_info *pi = sc->port[i]; 1264 struct vi_info *vi; 1265 1266 if (pi == NULL) 1267 continue; 1268 1269 pi->nvi = num_vis; 1270 for_each_vi(pi, j, vi) { 1271 vi->pi = pi; 1272 vi->qsize_rxq = t4_qsize_rxq; 1273 vi->qsize_txq = t4_qsize_txq; 1274 1275 vi->first_rxq = rqidx; 1276 vi->first_txq = tqidx; 1277 vi->tmr_idx = t4_tmr_idx; 1278 vi->pktc_idx = t4_pktc_idx; 1279 vi->nrxq = j == 0 ? iaq.nrxq : iaq.nrxq_vi; 1280 vi->ntxq = j == 0 ? iaq.ntxq : iaq.ntxq_vi; 1281 1282 rqidx += vi->nrxq; 1283 tqidx += vi->ntxq; 1284 1285 if (j == 0 && vi->ntxq > 1) 1286 vi->rsrv_noflowq = t4_rsrv_noflowq ? 1 : 0; 1287 else 1288 vi->rsrv_noflowq = 0; 1289 1290 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1291 vi->first_ofld_txq = ofld_tqidx; 1292 vi->nofldtxq = j == 0 ? iaq.nofldtxq : iaq.nofldtxq_vi; 1293 ofld_tqidx += vi->nofldtxq; 1294 #endif 1295 #ifdef TCP_OFFLOAD 1296 vi->ofld_tmr_idx = t4_tmr_idx_ofld; 1297 vi->ofld_pktc_idx = t4_pktc_idx_ofld; 1298 vi->first_ofld_rxq = ofld_rqidx; 1299 vi->nofldrxq = j == 0 ? iaq.nofldrxq : iaq.nofldrxq_vi; 1300 1301 ofld_rqidx += vi->nofldrxq; 1302 #endif 1303 #ifdef DEV_NETMAP 1304 if (j > 0) { 1305 vi->first_nm_rxq = nm_rqidx; 1306 vi->first_nm_txq = nm_tqidx; 1307 vi->nnmrxq = iaq.nnmrxq_vi; 1308 vi->nnmtxq = iaq.nnmtxq_vi; 1309 nm_rqidx += vi->nnmrxq; 1310 nm_tqidx += vi->nnmtxq; 1311 } 1312 #endif 1313 } 1314 } 1315 1316 rc = t4_setup_intr_handlers(sc); 1317 if (rc != 0) { 1318 device_printf(dev, 1319 "failed to setup interrupt handlers: %d\n", rc); 1320 goto done; 1321 } 1322 1323 rc = bus_generic_probe(dev); 1324 if (rc != 0) { 1325 device_printf(dev, "failed to probe child drivers: %d\n", rc); 1326 goto done; 1327 } 1328 1329 /* 1330 * Ensure thread-safe mailbox access (in debug builds). 1331 * 1332 * So far this was the only thread accessing the mailbox but various 1333 * ifnets and sysctls are about to be created and their handlers/ioctls 1334 * will access the mailbox from different threads. 1335 */ 1336 sc->flags |= CHK_MBOX_ACCESS; 1337 1338 rc = bus_generic_attach(dev); 1339 if (rc != 0) { 1340 device_printf(dev, 1341 "failed to attach all child ports: %d\n", rc); 1342 goto done; 1343 } 1344 1345 device_printf(dev, 1346 "PCIe gen%d x%d, %d ports, %d %s interrupt%s, %d eq, %d iq\n", 1347 sc->params.pci.speed, sc->params.pci.width, sc->params.nports, 1348 sc->intr_count, sc->intr_type == INTR_MSIX ? "MSI-X" : 1349 (sc->intr_type == INTR_MSI ? "MSI" : "INTx"), 1350 sc->intr_count > 1 ? "s" : "", sc->sge.neq, sc->sge.niq); 1351 1352 t4_set_desc(sc); 1353 1354 notify_siblings(dev, 0); 1355 1356 done: 1357 if (rc != 0 && sc->cdev) { 1358 /* cdev was created and so cxgbetool works; recover that way. */ 1359 device_printf(dev, 1360 "error during attach, adapter is now in recovery mode.\n"); 1361 rc = 0; 1362 } 1363 1364 if (rc != 0) 1365 t4_detach_common(dev); 1366 else 1367 t4_sysctls(sc); 1368 1369 return (rc); 1370 } 1371 1372 static int 1373 t4_child_location_str(device_t bus, device_t dev, char *buf, size_t buflen) 1374 { 1375 struct adapter *sc; 1376 struct port_info *pi; 1377 int i; 1378 1379 sc = device_get_softc(bus); 1380 buf[0] = '\0'; 1381 for_each_port(sc, i) { 1382 pi = sc->port[i]; 1383 if (pi != NULL && pi->dev == dev) { 1384 snprintf(buf, buflen, "port=%d", pi->port_id); 1385 break; 1386 } 1387 } 1388 return (0); 1389 } 1390 1391 static int 1392 t4_ready(device_t dev) 1393 { 1394 struct adapter *sc; 1395 1396 sc = device_get_softc(dev); 1397 if (sc->flags & FW_OK) 1398 return (0); 1399 return (ENXIO); 1400 } 1401 1402 static int 1403 t4_read_port_device(device_t dev, int port, device_t *child) 1404 { 1405 struct adapter *sc; 1406 struct port_info *pi; 1407 1408 sc = device_get_softc(dev); 1409 if (port < 0 || port >= MAX_NPORTS) 1410 return (EINVAL); 1411 pi = sc->port[port]; 1412 if (pi == NULL || pi->dev == NULL) 1413 return (ENXIO); 1414 *child = pi->dev; 1415 return (0); 1416 } 1417 1418 static int 1419 notify_siblings(device_t dev, int detaching) 1420 { 1421 device_t sibling; 1422 int error, i; 1423 1424 error = 0; 1425 for (i = 0; i < PCI_FUNCMAX; i++) { 1426 if (i == pci_get_function(dev)) 1427 continue; 1428 sibling = pci_find_dbsf(pci_get_domain(dev), pci_get_bus(dev), 1429 pci_get_slot(dev), i); 1430 if (sibling == NULL || !device_is_attached(sibling)) 1431 continue; 1432 if (detaching) 1433 error = T4_DETACH_CHILD(sibling); 1434 else 1435 (void)T4_ATTACH_CHILD(sibling); 1436 if (error) 1437 break; 1438 } 1439 return (error); 1440 } 1441 1442 /* 1443 * Idempotent 1444 */ 1445 static int 1446 t4_detach(device_t dev) 1447 { 1448 struct adapter *sc; 1449 int rc; 1450 1451 sc = device_get_softc(dev); 1452 1453 rc = notify_siblings(dev, 1); 1454 if (rc) { 1455 device_printf(dev, 1456 "failed to detach sibling devices: %d\n", rc); 1457 return (rc); 1458 } 1459 1460 return (t4_detach_common(dev)); 1461 } 1462 1463 int 1464 t4_detach_common(device_t dev) 1465 { 1466 struct adapter *sc; 1467 struct port_info *pi; 1468 int i, rc; 1469 1470 sc = device_get_softc(dev); 1471 1472 if (sc->cdev) { 1473 destroy_dev(sc->cdev); 1474 sc->cdev = NULL; 1475 } 1476 1477 sc->flags &= ~CHK_MBOX_ACCESS; 1478 if (sc->flags & FULL_INIT_DONE) { 1479 if (!(sc->flags & IS_VF)) 1480 t4_intr_disable(sc); 1481 } 1482 1483 if (device_is_attached(dev)) { 1484 rc = bus_generic_detach(dev); 1485 if (rc) { 1486 device_printf(dev, 1487 "failed to detach child devices: %d\n", rc); 1488 return (rc); 1489 } 1490 } 1491 1492 for (i = 0; i < sc->intr_count; i++) 1493 t4_free_irq(sc, &sc->irq[i]); 1494 1495 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK) 1496 t4_free_tx_sched(sc); 1497 1498 for (i = 0; i < MAX_NPORTS; i++) { 1499 pi = sc->port[i]; 1500 if (pi) { 1501 t4_free_vi(sc, sc->mbox, sc->pf, 0, pi->vi[0].viid); 1502 if (pi->dev) 1503 device_delete_child(dev, pi->dev); 1504 1505 mtx_destroy(&pi->pi_lock); 1506 free(pi->vi, M_CXGBE); 1507 free(pi, M_CXGBE); 1508 } 1509 } 1510 1511 device_delete_children(dev); 1512 1513 if (sc->flags & FULL_INIT_DONE) 1514 adapter_full_uninit(sc); 1515 1516 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK) 1517 t4_fw_bye(sc, sc->mbox); 1518 1519 if (sc->intr_type == INTR_MSI || sc->intr_type == INTR_MSIX) 1520 pci_release_msi(dev); 1521 1522 if (sc->regs_res) 1523 bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid, 1524 sc->regs_res); 1525 1526 if (sc->udbs_res) 1527 bus_release_resource(dev, SYS_RES_MEMORY, sc->udbs_rid, 1528 sc->udbs_res); 1529 1530 if (sc->msix_res) 1531 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_rid, 1532 sc->msix_res); 1533 1534 if (sc->l2t) 1535 t4_free_l2t(sc->l2t); 1536 if (sc->smt) 1537 t4_free_smt(sc->smt); 1538 #ifdef RATELIMIT 1539 t4_free_etid_table(sc); 1540 #endif 1541 if (sc->key_map) 1542 vmem_destroy(sc->key_map); 1543 #ifdef INET6 1544 t4_destroy_clip_table(sc); 1545 #endif 1546 1547 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1548 free(sc->sge.ofld_txq, M_CXGBE); 1549 #endif 1550 #ifdef TCP_OFFLOAD 1551 free(sc->sge.ofld_rxq, M_CXGBE); 1552 #endif 1553 #ifdef DEV_NETMAP 1554 free(sc->sge.nm_rxq, M_CXGBE); 1555 free(sc->sge.nm_txq, M_CXGBE); 1556 #endif 1557 free(sc->irq, M_CXGBE); 1558 free(sc->sge.rxq, M_CXGBE); 1559 free(sc->sge.txq, M_CXGBE); 1560 free(sc->sge.ctrlq, M_CXGBE); 1561 free(sc->sge.iqmap, M_CXGBE); 1562 free(sc->sge.eqmap, M_CXGBE); 1563 free(sc->tids.ftid_tab, M_CXGBE); 1564 free(sc->tids.hpftid_tab, M_CXGBE); 1565 free_hftid_hash(&sc->tids); 1566 free(sc->tids.atid_tab, M_CXGBE); 1567 free(sc->tids.tid_tab, M_CXGBE); 1568 free(sc->tt.tls_rx_ports, M_CXGBE); 1569 t4_destroy_dma_tag(sc); 1570 if (mtx_initialized(&sc->sc_lock)) { 1571 sx_xlock(&t4_list_lock); 1572 SLIST_REMOVE(&t4_list, sc, adapter, link); 1573 sx_xunlock(&t4_list_lock); 1574 mtx_destroy(&sc->sc_lock); 1575 } 1576 1577 callout_drain(&sc->sfl_callout); 1578 if (mtx_initialized(&sc->tids.ftid_lock)) { 1579 mtx_destroy(&sc->tids.ftid_lock); 1580 cv_destroy(&sc->tids.ftid_cv); 1581 } 1582 if (mtx_initialized(&sc->tids.atid_lock)) 1583 mtx_destroy(&sc->tids.atid_lock); 1584 if (mtx_initialized(&sc->sfl_lock)) 1585 mtx_destroy(&sc->sfl_lock); 1586 if (mtx_initialized(&sc->ifp_lock)) 1587 mtx_destroy(&sc->ifp_lock); 1588 if (mtx_initialized(&sc->reg_lock)) 1589 mtx_destroy(&sc->reg_lock); 1590 1591 if (rw_initialized(&sc->policy_lock)) { 1592 rw_destroy(&sc->policy_lock); 1593 #ifdef TCP_OFFLOAD 1594 if (sc->policy != NULL) 1595 free_offload_policy(sc->policy); 1596 #endif 1597 } 1598 1599 for (i = 0; i < NUM_MEMWIN; i++) { 1600 struct memwin *mw = &sc->memwin[i]; 1601 1602 if (rw_initialized(&mw->mw_lock)) 1603 rw_destroy(&mw->mw_lock); 1604 } 1605 1606 bzero(sc, sizeof(*sc)); 1607 1608 return (0); 1609 } 1610 1611 static int 1612 cxgbe_probe(device_t dev) 1613 { 1614 char buf[128]; 1615 struct port_info *pi = device_get_softc(dev); 1616 1617 snprintf(buf, sizeof(buf), "port %d", pi->port_id); 1618 device_set_desc_copy(dev, buf); 1619 1620 return (BUS_PROBE_DEFAULT); 1621 } 1622 1623 #define T4_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | \ 1624 IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO | \ 1625 IFCAP_VLAN_HWTSO | IFCAP_LINKSTATE | IFCAP_HWCSUM_IPV6 | IFCAP_HWSTATS | \ 1626 IFCAP_HWRXTSTMP) 1627 #define T4_CAP_ENABLE (T4_CAP) 1628 1629 static int 1630 cxgbe_vi_attach(device_t dev, struct vi_info *vi) 1631 { 1632 struct ifnet *ifp; 1633 struct sbuf *sb; 1634 1635 vi->xact_addr_filt = -1; 1636 callout_init(&vi->tick, 1); 1637 1638 /* Allocate an ifnet and set it up */ 1639 ifp = if_alloc(IFT_ETHER); 1640 if (ifp == NULL) { 1641 device_printf(dev, "Cannot allocate ifnet\n"); 1642 return (ENOMEM); 1643 } 1644 vi->ifp = ifp; 1645 ifp->if_softc = vi; 1646 1647 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1648 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1649 1650 ifp->if_init = cxgbe_init; 1651 ifp->if_ioctl = cxgbe_ioctl; 1652 ifp->if_transmit = cxgbe_transmit; 1653 ifp->if_qflush = cxgbe_qflush; 1654 ifp->if_get_counter = cxgbe_get_counter; 1655 #ifdef RATELIMIT 1656 ifp->if_snd_tag_alloc = cxgbe_snd_tag_alloc; 1657 ifp->if_snd_tag_modify = cxgbe_snd_tag_modify; 1658 ifp->if_snd_tag_query = cxgbe_snd_tag_query; 1659 ifp->if_snd_tag_free = cxgbe_snd_tag_free; 1660 #endif 1661 1662 ifp->if_capabilities = T4_CAP; 1663 ifp->if_capenable = T4_CAP_ENABLE; 1664 #ifdef TCP_OFFLOAD 1665 if (vi->nofldrxq != 0) 1666 ifp->if_capabilities |= IFCAP_TOE; 1667 #endif 1668 #ifdef RATELIMIT 1669 if (is_ethoffload(vi->pi->adapter) && vi->nofldtxq != 0) { 1670 ifp->if_capabilities |= IFCAP_TXRTLMT; 1671 ifp->if_capenable |= IFCAP_TXRTLMT; 1672 } 1673 #endif 1674 ifp->if_hwassist = CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO | 1675 CSUM_UDP_IPV6 | CSUM_TCP_IPV6; 1676 1677 ifp->if_hw_tsomax = IP_MAXPACKET; 1678 ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS_TSO; 1679 #ifdef RATELIMIT 1680 if (is_ethoffload(vi->pi->adapter) && vi->nofldtxq != 0) 1681 ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS_EO_TSO; 1682 #endif 1683 ifp->if_hw_tsomaxsegsize = 65536; 1684 1685 ether_ifattach(ifp, vi->hw_addr); 1686 #ifdef DEV_NETMAP 1687 if (vi->nnmrxq != 0) 1688 cxgbe_nm_attach(vi); 1689 #endif 1690 sb = sbuf_new_auto(); 1691 sbuf_printf(sb, "%d txq, %d rxq (NIC)", vi->ntxq, vi->nrxq); 1692 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 1693 switch (ifp->if_capabilities & (IFCAP_TOE | IFCAP_TXRTLMT)) { 1694 case IFCAP_TOE: 1695 sbuf_printf(sb, "; %d txq (TOE)", vi->nofldtxq); 1696 break; 1697 case IFCAP_TOE | IFCAP_TXRTLMT: 1698 sbuf_printf(sb, "; %d txq (TOE/ETHOFLD)", vi->nofldtxq); 1699 break; 1700 case IFCAP_TXRTLMT: 1701 sbuf_printf(sb, "; %d txq (ETHOFLD)", vi->nofldtxq); 1702 break; 1703 } 1704 #endif 1705 #ifdef TCP_OFFLOAD 1706 if (ifp->if_capabilities & IFCAP_TOE) 1707 sbuf_printf(sb, ", %d rxq (TOE)", vi->nofldrxq); 1708 #endif 1709 #ifdef DEV_NETMAP 1710 if (ifp->if_capabilities & IFCAP_NETMAP) 1711 sbuf_printf(sb, "; %d txq, %d rxq (netmap)", 1712 vi->nnmtxq, vi->nnmrxq); 1713 #endif 1714 sbuf_finish(sb); 1715 device_printf(dev, "%s\n", sbuf_data(sb)); 1716 sbuf_delete(sb); 1717 1718 vi_sysctls(vi); 1719 1720 return (0); 1721 } 1722 1723 static int 1724 cxgbe_attach(device_t dev) 1725 { 1726 struct port_info *pi = device_get_softc(dev); 1727 struct adapter *sc = pi->adapter; 1728 struct vi_info *vi; 1729 int i, rc; 1730 1731 callout_init_mtx(&pi->tick, &pi->pi_lock, 0); 1732 1733 rc = cxgbe_vi_attach(dev, &pi->vi[0]); 1734 if (rc) 1735 return (rc); 1736 1737 for_each_vi(pi, i, vi) { 1738 if (i == 0) 1739 continue; 1740 vi->dev = device_add_child(dev, sc->names->vi_ifnet_name, -1); 1741 if (vi->dev == NULL) { 1742 device_printf(dev, "failed to add VI %d\n", i); 1743 continue; 1744 } 1745 device_set_softc(vi->dev, vi); 1746 } 1747 1748 cxgbe_sysctls(pi); 1749 1750 bus_generic_attach(dev); 1751 1752 return (0); 1753 } 1754 1755 static void 1756 cxgbe_vi_detach(struct vi_info *vi) 1757 { 1758 struct ifnet *ifp = vi->ifp; 1759 1760 ether_ifdetach(ifp); 1761 1762 /* Let detach proceed even if these fail. */ 1763 #ifdef DEV_NETMAP 1764 if (ifp->if_capabilities & IFCAP_NETMAP) 1765 cxgbe_nm_detach(vi); 1766 #endif 1767 cxgbe_uninit_synchronized(vi); 1768 callout_drain(&vi->tick); 1769 vi_full_uninit(vi); 1770 1771 if_free(vi->ifp); 1772 vi->ifp = NULL; 1773 } 1774 1775 static int 1776 cxgbe_detach(device_t dev) 1777 { 1778 struct port_info *pi = device_get_softc(dev); 1779 struct adapter *sc = pi->adapter; 1780 int rc; 1781 1782 /* Detach the extra VIs first. */ 1783 rc = bus_generic_detach(dev); 1784 if (rc) 1785 return (rc); 1786 device_delete_children(dev); 1787 1788 doom_vi(sc, &pi->vi[0]); 1789 1790 if (pi->flags & HAS_TRACEQ) { 1791 sc->traceq = -1; /* cloner should not create ifnet */ 1792 t4_tracer_port_detach(sc); 1793 } 1794 1795 cxgbe_vi_detach(&pi->vi[0]); 1796 callout_drain(&pi->tick); 1797 ifmedia_removeall(&pi->media); 1798 1799 end_synchronized_op(sc, 0); 1800 1801 return (0); 1802 } 1803 1804 static void 1805 cxgbe_init(void *arg) 1806 { 1807 struct vi_info *vi = arg; 1808 struct adapter *sc = vi->pi->adapter; 1809 1810 if (begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4init") != 0) 1811 return; 1812 cxgbe_init_synchronized(vi); 1813 end_synchronized_op(sc, 0); 1814 } 1815 1816 static int 1817 cxgbe_ioctl(struct ifnet *ifp, unsigned long cmd, caddr_t data) 1818 { 1819 int rc = 0, mtu, flags; 1820 struct vi_info *vi = ifp->if_softc; 1821 struct port_info *pi = vi->pi; 1822 struct adapter *sc = pi->adapter; 1823 struct ifreq *ifr = (struct ifreq *)data; 1824 uint32_t mask; 1825 1826 switch (cmd) { 1827 case SIOCSIFMTU: 1828 mtu = ifr->ifr_mtu; 1829 if (mtu < ETHERMIN || mtu > MAX_MTU) 1830 return (EINVAL); 1831 1832 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4mtu"); 1833 if (rc) 1834 return (rc); 1835 ifp->if_mtu = mtu; 1836 if (vi->flags & VI_INIT_DONE) { 1837 t4_update_fl_bufsize(ifp); 1838 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1839 rc = update_mac_settings(ifp, XGMAC_MTU); 1840 } 1841 end_synchronized_op(sc, 0); 1842 break; 1843 1844 case SIOCSIFFLAGS: 1845 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4flg"); 1846 if (rc) 1847 return (rc); 1848 1849 if (ifp->if_flags & IFF_UP) { 1850 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1851 flags = vi->if_flags; 1852 if ((ifp->if_flags ^ flags) & 1853 (IFF_PROMISC | IFF_ALLMULTI)) { 1854 rc = update_mac_settings(ifp, 1855 XGMAC_PROMISC | XGMAC_ALLMULTI); 1856 } 1857 } else { 1858 rc = cxgbe_init_synchronized(vi); 1859 } 1860 vi->if_flags = ifp->if_flags; 1861 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1862 rc = cxgbe_uninit_synchronized(vi); 1863 } 1864 end_synchronized_op(sc, 0); 1865 break; 1866 1867 case SIOCADDMULTI: 1868 case SIOCDELMULTI: 1869 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4multi"); 1870 if (rc) 1871 return (rc); 1872 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1873 rc = update_mac_settings(ifp, XGMAC_MCADDRS); 1874 end_synchronized_op(sc, 0); 1875 break; 1876 1877 case SIOCSIFCAP: 1878 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4cap"); 1879 if (rc) 1880 return (rc); 1881 1882 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1883 if (mask & IFCAP_TXCSUM) { 1884 ifp->if_capenable ^= IFCAP_TXCSUM; 1885 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP); 1886 1887 if (IFCAP_TSO4 & ifp->if_capenable && 1888 !(IFCAP_TXCSUM & ifp->if_capenable)) { 1889 ifp->if_capenable &= ~IFCAP_TSO4; 1890 if_printf(ifp, 1891 "tso4 disabled due to -txcsum.\n"); 1892 } 1893 } 1894 if (mask & IFCAP_TXCSUM_IPV6) { 1895 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6; 1896 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6); 1897 1898 if (IFCAP_TSO6 & ifp->if_capenable && 1899 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) { 1900 ifp->if_capenable &= ~IFCAP_TSO6; 1901 if_printf(ifp, 1902 "tso6 disabled due to -txcsum6.\n"); 1903 } 1904 } 1905 if (mask & IFCAP_RXCSUM) 1906 ifp->if_capenable ^= IFCAP_RXCSUM; 1907 if (mask & IFCAP_RXCSUM_IPV6) 1908 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6; 1909 1910 /* 1911 * Note that we leave CSUM_TSO alone (it is always set). The 1912 * kernel takes both IFCAP_TSOx and CSUM_TSO into account before 1913 * sending a TSO request our way, so it's sufficient to toggle 1914 * IFCAP_TSOx only. 1915 */ 1916 if (mask & IFCAP_TSO4) { 1917 if (!(IFCAP_TSO4 & ifp->if_capenable) && 1918 !(IFCAP_TXCSUM & ifp->if_capenable)) { 1919 if_printf(ifp, "enable txcsum first.\n"); 1920 rc = EAGAIN; 1921 goto fail; 1922 } 1923 ifp->if_capenable ^= IFCAP_TSO4; 1924 } 1925 if (mask & IFCAP_TSO6) { 1926 if (!(IFCAP_TSO6 & ifp->if_capenable) && 1927 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) { 1928 if_printf(ifp, "enable txcsum6 first.\n"); 1929 rc = EAGAIN; 1930 goto fail; 1931 } 1932 ifp->if_capenable ^= IFCAP_TSO6; 1933 } 1934 if (mask & IFCAP_LRO) { 1935 #if defined(INET) || defined(INET6) 1936 int i; 1937 struct sge_rxq *rxq; 1938 1939 ifp->if_capenable ^= IFCAP_LRO; 1940 for_each_rxq(vi, i, rxq) { 1941 if (ifp->if_capenable & IFCAP_LRO) 1942 rxq->iq.flags |= IQ_LRO_ENABLED; 1943 else 1944 rxq->iq.flags &= ~IQ_LRO_ENABLED; 1945 } 1946 #endif 1947 } 1948 #ifdef TCP_OFFLOAD 1949 if (mask & IFCAP_TOE) { 1950 int enable = (ifp->if_capenable ^ mask) & IFCAP_TOE; 1951 1952 rc = toe_capability(vi, enable); 1953 if (rc != 0) 1954 goto fail; 1955 1956 ifp->if_capenable ^= mask; 1957 } 1958 #endif 1959 if (mask & IFCAP_VLAN_HWTAGGING) { 1960 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1961 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1962 rc = update_mac_settings(ifp, XGMAC_VLANEX); 1963 } 1964 if (mask & IFCAP_VLAN_MTU) { 1965 ifp->if_capenable ^= IFCAP_VLAN_MTU; 1966 1967 /* Need to find out how to disable auto-mtu-inflation */ 1968 } 1969 if (mask & IFCAP_VLAN_HWTSO) 1970 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 1971 if (mask & IFCAP_VLAN_HWCSUM) 1972 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 1973 #ifdef RATELIMIT 1974 if (mask & IFCAP_TXRTLMT) 1975 ifp->if_capenable ^= IFCAP_TXRTLMT; 1976 #endif 1977 if (mask & IFCAP_HWRXTSTMP) { 1978 int i; 1979 struct sge_rxq *rxq; 1980 1981 ifp->if_capenable ^= IFCAP_HWRXTSTMP; 1982 for_each_rxq(vi, i, rxq) { 1983 if (ifp->if_capenable & IFCAP_HWRXTSTMP) 1984 rxq->iq.flags |= IQ_RX_TIMESTAMP; 1985 else 1986 rxq->iq.flags &= ~IQ_RX_TIMESTAMP; 1987 } 1988 } 1989 1990 #ifdef VLAN_CAPABILITIES 1991 VLAN_CAPABILITIES(ifp); 1992 #endif 1993 fail: 1994 end_synchronized_op(sc, 0); 1995 break; 1996 1997 case SIOCSIFMEDIA: 1998 case SIOCGIFMEDIA: 1999 case SIOCGIFXMEDIA: 2000 ifmedia_ioctl(ifp, ifr, &pi->media, cmd); 2001 break; 2002 2003 case SIOCGI2C: { 2004 struct ifi2creq i2c; 2005 2006 rc = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 2007 if (rc != 0) 2008 break; 2009 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 2010 rc = EPERM; 2011 break; 2012 } 2013 if (i2c.len > sizeof(i2c.data)) { 2014 rc = EINVAL; 2015 break; 2016 } 2017 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4i2c"); 2018 if (rc) 2019 return (rc); 2020 rc = -t4_i2c_rd(sc, sc->mbox, pi->port_id, i2c.dev_addr, 2021 i2c.offset, i2c.len, &i2c.data[0]); 2022 end_synchronized_op(sc, 0); 2023 if (rc == 0) 2024 rc = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c)); 2025 break; 2026 } 2027 2028 default: 2029 rc = ether_ioctl(ifp, cmd, data); 2030 } 2031 2032 return (rc); 2033 } 2034 2035 static int 2036 cxgbe_transmit(struct ifnet *ifp, struct mbuf *m) 2037 { 2038 struct vi_info *vi = ifp->if_softc; 2039 struct port_info *pi = vi->pi; 2040 struct adapter *sc = pi->adapter; 2041 struct sge_txq *txq; 2042 void *items[1]; 2043 int rc; 2044 2045 M_ASSERTPKTHDR(m); 2046 MPASS(m->m_nextpkt == NULL); /* not quite ready for this yet */ 2047 2048 if (__predict_false(pi->link_cfg.link_ok == false)) { 2049 m_freem(m); 2050 return (ENETDOWN); 2051 } 2052 2053 rc = parse_pkt(sc, &m); 2054 if (__predict_false(rc != 0)) { 2055 MPASS(m == NULL); /* was freed already */ 2056 atomic_add_int(&pi->tx_parse_error, 1); /* rare, atomic is ok */ 2057 return (rc); 2058 } 2059 #ifdef RATELIMIT 2060 if (m->m_pkthdr.snd_tag != NULL) { 2061 /* EAGAIN tells the stack we are not the correct interface. */ 2062 if (__predict_false(ifp != m->m_pkthdr.snd_tag->ifp)) { 2063 m_freem(m); 2064 return (EAGAIN); 2065 } 2066 2067 return (ethofld_transmit(ifp, m)); 2068 } 2069 #endif 2070 2071 /* Select a txq. */ 2072 txq = &sc->sge.txq[vi->first_txq]; 2073 if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE) 2074 txq += ((m->m_pkthdr.flowid % (vi->ntxq - vi->rsrv_noflowq)) + 2075 vi->rsrv_noflowq); 2076 2077 items[0] = m; 2078 rc = mp_ring_enqueue(txq->r, items, 1, 4096); 2079 if (__predict_false(rc != 0)) 2080 m_freem(m); 2081 2082 return (rc); 2083 } 2084 2085 static void 2086 cxgbe_qflush(struct ifnet *ifp) 2087 { 2088 struct vi_info *vi = ifp->if_softc; 2089 struct sge_txq *txq; 2090 int i; 2091 2092 /* queues do not exist if !VI_INIT_DONE. */ 2093 if (vi->flags & VI_INIT_DONE) { 2094 for_each_txq(vi, i, txq) { 2095 TXQ_LOCK(txq); 2096 txq->eq.flags |= EQ_QFLUSH; 2097 TXQ_UNLOCK(txq); 2098 while (!mp_ring_is_idle(txq->r)) { 2099 mp_ring_check_drainage(txq->r, 0); 2100 pause("qflush", 1); 2101 } 2102 TXQ_LOCK(txq); 2103 txq->eq.flags &= ~EQ_QFLUSH; 2104 TXQ_UNLOCK(txq); 2105 } 2106 } 2107 if_qflush(ifp); 2108 } 2109 2110 static uint64_t 2111 vi_get_counter(struct ifnet *ifp, ift_counter c) 2112 { 2113 struct vi_info *vi = ifp->if_softc; 2114 struct fw_vi_stats_vf *s = &vi->stats; 2115 2116 vi_refresh_stats(vi->pi->adapter, vi); 2117 2118 switch (c) { 2119 case IFCOUNTER_IPACKETS: 2120 return (s->rx_bcast_frames + s->rx_mcast_frames + 2121 s->rx_ucast_frames); 2122 case IFCOUNTER_IERRORS: 2123 return (s->rx_err_frames); 2124 case IFCOUNTER_OPACKETS: 2125 return (s->tx_bcast_frames + s->tx_mcast_frames + 2126 s->tx_ucast_frames + s->tx_offload_frames); 2127 case IFCOUNTER_OERRORS: 2128 return (s->tx_drop_frames); 2129 case IFCOUNTER_IBYTES: 2130 return (s->rx_bcast_bytes + s->rx_mcast_bytes + 2131 s->rx_ucast_bytes); 2132 case IFCOUNTER_OBYTES: 2133 return (s->tx_bcast_bytes + s->tx_mcast_bytes + 2134 s->tx_ucast_bytes + s->tx_offload_bytes); 2135 case IFCOUNTER_IMCASTS: 2136 return (s->rx_mcast_frames); 2137 case IFCOUNTER_OMCASTS: 2138 return (s->tx_mcast_frames); 2139 case IFCOUNTER_OQDROPS: { 2140 uint64_t drops; 2141 2142 drops = 0; 2143 if (vi->flags & VI_INIT_DONE) { 2144 int i; 2145 struct sge_txq *txq; 2146 2147 for_each_txq(vi, i, txq) 2148 drops += counter_u64_fetch(txq->r->drops); 2149 } 2150 2151 return (drops); 2152 2153 } 2154 2155 default: 2156 return (if_get_counter_default(ifp, c)); 2157 } 2158 } 2159 2160 uint64_t 2161 cxgbe_get_counter(struct ifnet *ifp, ift_counter c) 2162 { 2163 struct vi_info *vi = ifp->if_softc; 2164 struct port_info *pi = vi->pi; 2165 struct adapter *sc = pi->adapter; 2166 struct port_stats *s = &pi->stats; 2167 2168 if (pi->nvi > 1 || sc->flags & IS_VF) 2169 return (vi_get_counter(ifp, c)); 2170 2171 cxgbe_refresh_stats(sc, pi); 2172 2173 switch (c) { 2174 case IFCOUNTER_IPACKETS: 2175 return (s->rx_frames); 2176 2177 case IFCOUNTER_IERRORS: 2178 return (s->rx_jabber + s->rx_runt + s->rx_too_long + 2179 s->rx_fcs_err + s->rx_len_err); 2180 2181 case IFCOUNTER_OPACKETS: 2182 return (s->tx_frames); 2183 2184 case IFCOUNTER_OERRORS: 2185 return (s->tx_error_frames); 2186 2187 case IFCOUNTER_IBYTES: 2188 return (s->rx_octets); 2189 2190 case IFCOUNTER_OBYTES: 2191 return (s->tx_octets); 2192 2193 case IFCOUNTER_IMCASTS: 2194 return (s->rx_mcast_frames); 2195 2196 case IFCOUNTER_OMCASTS: 2197 return (s->tx_mcast_frames); 2198 2199 case IFCOUNTER_IQDROPS: 2200 return (s->rx_ovflow0 + s->rx_ovflow1 + s->rx_ovflow2 + 2201 s->rx_ovflow3 + s->rx_trunc0 + s->rx_trunc1 + s->rx_trunc2 + 2202 s->rx_trunc3 + pi->tnl_cong_drops); 2203 2204 case IFCOUNTER_OQDROPS: { 2205 uint64_t drops; 2206 2207 drops = s->tx_drop; 2208 if (vi->flags & VI_INIT_DONE) { 2209 int i; 2210 struct sge_txq *txq; 2211 2212 for_each_txq(vi, i, txq) 2213 drops += counter_u64_fetch(txq->r->drops); 2214 } 2215 2216 return (drops); 2217 2218 } 2219 2220 default: 2221 return (if_get_counter_default(ifp, c)); 2222 } 2223 } 2224 2225 /* 2226 * The kernel picks a media from the list we had provided but we still validate 2227 * the requeste. 2228 */ 2229 int 2230 cxgbe_media_change(struct ifnet *ifp) 2231 { 2232 struct vi_info *vi = ifp->if_softc; 2233 struct port_info *pi = vi->pi; 2234 struct ifmedia *ifm = &pi->media; 2235 struct link_config *lc = &pi->link_cfg; 2236 struct adapter *sc = pi->adapter; 2237 int rc; 2238 2239 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4mec"); 2240 if (rc != 0) 2241 return (rc); 2242 PORT_LOCK(pi); 2243 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) { 2244 /* ifconfig .. media autoselect */ 2245 if (!(lc->supported & FW_PORT_CAP32_ANEG)) { 2246 rc = ENOTSUP; /* AN not supported by transceiver */ 2247 goto done; 2248 } 2249 lc->requested_aneg = AUTONEG_ENABLE; 2250 lc->requested_speed = 0; 2251 lc->requested_fc |= PAUSE_AUTONEG; 2252 } else { 2253 lc->requested_aneg = AUTONEG_DISABLE; 2254 lc->requested_speed = 2255 ifmedia_baudrate(ifm->ifm_media) / 1000000; 2256 lc->requested_fc = 0; 2257 if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_RXPAUSE) 2258 lc->requested_fc |= PAUSE_RX; 2259 if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_TXPAUSE) 2260 lc->requested_fc |= PAUSE_TX; 2261 } 2262 if (pi->up_vis > 0) { 2263 fixup_link_config(pi); 2264 rc = apply_link_config(pi); 2265 } 2266 done: 2267 PORT_UNLOCK(pi); 2268 end_synchronized_op(sc, 0); 2269 return (rc); 2270 } 2271 2272 /* 2273 * Base media word (without ETHER, pause, link active, etc.) for the port at the 2274 * given speed. 2275 */ 2276 static int 2277 port_mword(struct port_info *pi, uint32_t speed) 2278 { 2279 2280 MPASS(speed & M_FW_PORT_CAP32_SPEED); 2281 MPASS(powerof2(speed)); 2282 2283 switch(pi->port_type) { 2284 case FW_PORT_TYPE_BT_SGMII: 2285 case FW_PORT_TYPE_BT_XFI: 2286 case FW_PORT_TYPE_BT_XAUI: 2287 /* BaseT */ 2288 switch (speed) { 2289 case FW_PORT_CAP32_SPEED_100M: 2290 return (IFM_100_T); 2291 case FW_PORT_CAP32_SPEED_1G: 2292 return (IFM_1000_T); 2293 case FW_PORT_CAP32_SPEED_10G: 2294 return (IFM_10G_T); 2295 } 2296 break; 2297 case FW_PORT_TYPE_KX4: 2298 if (speed == FW_PORT_CAP32_SPEED_10G) 2299 return (IFM_10G_KX4); 2300 break; 2301 case FW_PORT_TYPE_CX4: 2302 if (speed == FW_PORT_CAP32_SPEED_10G) 2303 return (IFM_10G_CX4); 2304 break; 2305 case FW_PORT_TYPE_KX: 2306 if (speed == FW_PORT_CAP32_SPEED_1G) 2307 return (IFM_1000_KX); 2308 break; 2309 case FW_PORT_TYPE_KR: 2310 case FW_PORT_TYPE_BP_AP: 2311 case FW_PORT_TYPE_BP4_AP: 2312 case FW_PORT_TYPE_BP40_BA: 2313 case FW_PORT_TYPE_KR4_100G: 2314 case FW_PORT_TYPE_KR_SFP28: 2315 case FW_PORT_TYPE_KR_XLAUI: 2316 switch (speed) { 2317 case FW_PORT_CAP32_SPEED_1G: 2318 return (IFM_1000_KX); 2319 case FW_PORT_CAP32_SPEED_10G: 2320 return (IFM_10G_KR); 2321 case FW_PORT_CAP32_SPEED_25G: 2322 return (IFM_25G_KR); 2323 case FW_PORT_CAP32_SPEED_40G: 2324 return (IFM_40G_KR4); 2325 case FW_PORT_CAP32_SPEED_50G: 2326 return (IFM_50G_KR2); 2327 case FW_PORT_CAP32_SPEED_100G: 2328 return (IFM_100G_KR4); 2329 } 2330 break; 2331 case FW_PORT_TYPE_FIBER_XFI: 2332 case FW_PORT_TYPE_FIBER_XAUI: 2333 case FW_PORT_TYPE_SFP: 2334 case FW_PORT_TYPE_QSFP_10G: 2335 case FW_PORT_TYPE_QSA: 2336 case FW_PORT_TYPE_QSFP: 2337 case FW_PORT_TYPE_CR4_QSFP: 2338 case FW_PORT_TYPE_CR_QSFP: 2339 case FW_PORT_TYPE_CR2_QSFP: 2340 case FW_PORT_TYPE_SFP28: 2341 /* Pluggable transceiver */ 2342 switch (pi->mod_type) { 2343 case FW_PORT_MOD_TYPE_LR: 2344 switch (speed) { 2345 case FW_PORT_CAP32_SPEED_1G: 2346 return (IFM_1000_LX); 2347 case FW_PORT_CAP32_SPEED_10G: 2348 return (IFM_10G_LR); 2349 case FW_PORT_CAP32_SPEED_25G: 2350 return (IFM_25G_LR); 2351 case FW_PORT_CAP32_SPEED_40G: 2352 return (IFM_40G_LR4); 2353 case FW_PORT_CAP32_SPEED_50G: 2354 return (IFM_50G_LR2); 2355 case FW_PORT_CAP32_SPEED_100G: 2356 return (IFM_100G_LR4); 2357 } 2358 break; 2359 case FW_PORT_MOD_TYPE_SR: 2360 switch (speed) { 2361 case FW_PORT_CAP32_SPEED_1G: 2362 return (IFM_1000_SX); 2363 case FW_PORT_CAP32_SPEED_10G: 2364 return (IFM_10G_SR); 2365 case FW_PORT_CAP32_SPEED_25G: 2366 return (IFM_25G_SR); 2367 case FW_PORT_CAP32_SPEED_40G: 2368 return (IFM_40G_SR4); 2369 case FW_PORT_CAP32_SPEED_50G: 2370 return (IFM_50G_SR2); 2371 case FW_PORT_CAP32_SPEED_100G: 2372 return (IFM_100G_SR4); 2373 } 2374 break; 2375 case FW_PORT_MOD_TYPE_ER: 2376 if (speed == FW_PORT_CAP32_SPEED_10G) 2377 return (IFM_10G_ER); 2378 break; 2379 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE: 2380 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE: 2381 switch (speed) { 2382 case FW_PORT_CAP32_SPEED_1G: 2383 return (IFM_1000_CX); 2384 case FW_PORT_CAP32_SPEED_10G: 2385 return (IFM_10G_TWINAX); 2386 case FW_PORT_CAP32_SPEED_25G: 2387 return (IFM_25G_CR); 2388 case FW_PORT_CAP32_SPEED_40G: 2389 return (IFM_40G_CR4); 2390 case FW_PORT_CAP32_SPEED_50G: 2391 return (IFM_50G_CR2); 2392 case FW_PORT_CAP32_SPEED_100G: 2393 return (IFM_100G_CR4); 2394 } 2395 break; 2396 case FW_PORT_MOD_TYPE_LRM: 2397 if (speed == FW_PORT_CAP32_SPEED_10G) 2398 return (IFM_10G_LRM); 2399 break; 2400 case FW_PORT_MOD_TYPE_NA: 2401 MPASS(0); /* Not pluggable? */ 2402 /* fall throough */ 2403 case FW_PORT_MOD_TYPE_ERROR: 2404 case FW_PORT_MOD_TYPE_UNKNOWN: 2405 case FW_PORT_MOD_TYPE_NOTSUPPORTED: 2406 break; 2407 case FW_PORT_MOD_TYPE_NONE: 2408 return (IFM_NONE); 2409 } 2410 break; 2411 case FW_PORT_TYPE_NONE: 2412 return (IFM_NONE); 2413 } 2414 2415 return (IFM_UNKNOWN); 2416 } 2417 2418 void 2419 cxgbe_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 2420 { 2421 struct vi_info *vi = ifp->if_softc; 2422 struct port_info *pi = vi->pi; 2423 struct adapter *sc = pi->adapter; 2424 struct link_config *lc = &pi->link_cfg; 2425 2426 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4med") != 0) 2427 return; 2428 PORT_LOCK(pi); 2429 2430 if (pi->up_vis == 0) { 2431 /* 2432 * If all the interfaces are administratively down the firmware 2433 * does not report transceiver changes. Refresh port info here 2434 * so that ifconfig displays accurate ifmedia at all times. 2435 * This is the only reason we have a synchronized op in this 2436 * function. Just PORT_LOCK would have been enough otherwise. 2437 */ 2438 t4_update_port_info(pi); 2439 build_medialist(pi); 2440 } 2441 2442 /* ifm_status */ 2443 ifmr->ifm_status = IFM_AVALID; 2444 if (lc->link_ok == false) 2445 goto done; 2446 ifmr->ifm_status |= IFM_ACTIVE; 2447 2448 /* ifm_active */ 2449 ifmr->ifm_active = IFM_ETHER | IFM_FDX; 2450 ifmr->ifm_active &= ~(IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE); 2451 if (lc->fc & PAUSE_RX) 2452 ifmr->ifm_active |= IFM_ETH_RXPAUSE; 2453 if (lc->fc & PAUSE_TX) 2454 ifmr->ifm_active |= IFM_ETH_TXPAUSE; 2455 ifmr->ifm_active |= port_mword(pi, speed_to_fwcap(lc->speed)); 2456 done: 2457 PORT_UNLOCK(pi); 2458 end_synchronized_op(sc, 0); 2459 } 2460 2461 static int 2462 vcxgbe_probe(device_t dev) 2463 { 2464 char buf[128]; 2465 struct vi_info *vi = device_get_softc(dev); 2466 2467 snprintf(buf, sizeof(buf), "port %d vi %td", vi->pi->port_id, 2468 vi - vi->pi->vi); 2469 device_set_desc_copy(dev, buf); 2470 2471 return (BUS_PROBE_DEFAULT); 2472 } 2473 2474 static int 2475 alloc_extra_vi(struct adapter *sc, struct port_info *pi, struct vi_info *vi) 2476 { 2477 int func, index, rc; 2478 uint32_t param, val; 2479 2480 ASSERT_SYNCHRONIZED_OP(sc); 2481 2482 index = vi - pi->vi; 2483 MPASS(index > 0); /* This function deals with _extra_ VIs only */ 2484 KASSERT(index < nitems(vi_mac_funcs), 2485 ("%s: VI %s doesn't have a MAC func", __func__, 2486 device_get_nameunit(vi->dev))); 2487 func = vi_mac_funcs[index]; 2488 rc = t4_alloc_vi_func(sc, sc->mbox, pi->tx_chan, sc->pf, 0, 1, 2489 vi->hw_addr, &vi->rss_size, &vi->vfvld, &vi->vin, func, 0); 2490 if (rc < 0) { 2491 device_printf(vi->dev, "failed to allocate virtual interface %d" 2492 "for port %d: %d\n", index, pi->port_id, -rc); 2493 return (-rc); 2494 } 2495 vi->viid = rc; 2496 2497 if (vi->rss_size == 1) { 2498 /* 2499 * This VI didn't get a slice of the RSS table. Reduce the 2500 * number of VIs being created (hw.cxgbe.num_vis) or modify the 2501 * configuration file (nvi, rssnvi for this PF) if this is a 2502 * problem. 2503 */ 2504 device_printf(vi->dev, "RSS table not available.\n"); 2505 vi->rss_base = 0xffff; 2506 2507 return (0); 2508 } 2509 2510 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 2511 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) | 2512 V_FW_PARAMS_PARAM_YZ(vi->viid); 2513 rc = t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 2514 if (rc) 2515 vi->rss_base = 0xffff; 2516 else { 2517 MPASS((val >> 16) == vi->rss_size); 2518 vi->rss_base = val & 0xffff; 2519 } 2520 2521 return (0); 2522 } 2523 2524 static int 2525 vcxgbe_attach(device_t dev) 2526 { 2527 struct vi_info *vi; 2528 struct port_info *pi; 2529 struct adapter *sc; 2530 int rc; 2531 2532 vi = device_get_softc(dev); 2533 pi = vi->pi; 2534 sc = pi->adapter; 2535 2536 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4via"); 2537 if (rc) 2538 return (rc); 2539 rc = alloc_extra_vi(sc, pi, vi); 2540 end_synchronized_op(sc, 0); 2541 if (rc) 2542 return (rc); 2543 2544 rc = cxgbe_vi_attach(dev, vi); 2545 if (rc) { 2546 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid); 2547 return (rc); 2548 } 2549 return (0); 2550 } 2551 2552 static int 2553 vcxgbe_detach(device_t dev) 2554 { 2555 struct vi_info *vi; 2556 struct adapter *sc; 2557 2558 vi = device_get_softc(dev); 2559 sc = vi->pi->adapter; 2560 2561 doom_vi(sc, vi); 2562 2563 cxgbe_vi_detach(vi); 2564 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid); 2565 2566 end_synchronized_op(sc, 0); 2567 2568 return (0); 2569 } 2570 2571 static struct callout fatal_callout; 2572 2573 static void 2574 delayed_panic(void *arg) 2575 { 2576 struct adapter *sc = arg; 2577 2578 panic("%s: panic on fatal error", device_get_nameunit(sc->dev)); 2579 } 2580 2581 void 2582 t4_fatal_err(struct adapter *sc, bool fw_error) 2583 { 2584 2585 t4_shutdown_adapter(sc); 2586 log(LOG_ALERT, "%s: encountered fatal error, adapter stopped.\n", 2587 device_get_nameunit(sc->dev)); 2588 if (fw_error) { 2589 ASSERT_SYNCHRONIZED_OP(sc); 2590 sc->flags |= ADAP_ERR; 2591 } else { 2592 ADAPTER_LOCK(sc); 2593 sc->flags |= ADAP_ERR; 2594 ADAPTER_UNLOCK(sc); 2595 } 2596 2597 if (t4_panic_on_fatal_err) { 2598 log(LOG_ALERT, "%s: panic on fatal error after 30s", 2599 device_get_nameunit(sc->dev)); 2600 callout_reset(&fatal_callout, hz * 30, delayed_panic, sc); 2601 } 2602 } 2603 2604 void 2605 t4_add_adapter(struct adapter *sc) 2606 { 2607 sx_xlock(&t4_list_lock); 2608 SLIST_INSERT_HEAD(&t4_list, sc, link); 2609 sx_xunlock(&t4_list_lock); 2610 } 2611 2612 int 2613 t4_map_bars_0_and_4(struct adapter *sc) 2614 { 2615 sc->regs_rid = PCIR_BAR(0); 2616 sc->regs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 2617 &sc->regs_rid, RF_ACTIVE); 2618 if (sc->regs_res == NULL) { 2619 device_printf(sc->dev, "cannot map registers.\n"); 2620 return (ENXIO); 2621 } 2622 sc->bt = rman_get_bustag(sc->regs_res); 2623 sc->bh = rman_get_bushandle(sc->regs_res); 2624 sc->mmio_len = rman_get_size(sc->regs_res); 2625 setbit(&sc->doorbells, DOORBELL_KDB); 2626 2627 sc->msix_rid = PCIR_BAR(4); 2628 sc->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 2629 &sc->msix_rid, RF_ACTIVE); 2630 if (sc->msix_res == NULL) { 2631 device_printf(sc->dev, "cannot map MSI-X BAR.\n"); 2632 return (ENXIO); 2633 } 2634 2635 return (0); 2636 } 2637 2638 int 2639 t4_map_bar_2(struct adapter *sc) 2640 { 2641 2642 /* 2643 * T4: only iWARP driver uses the userspace doorbells. There is no need 2644 * to map it if RDMA is disabled. 2645 */ 2646 if (is_t4(sc) && sc->rdmacaps == 0) 2647 return (0); 2648 2649 sc->udbs_rid = PCIR_BAR(2); 2650 sc->udbs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 2651 &sc->udbs_rid, RF_ACTIVE); 2652 if (sc->udbs_res == NULL) { 2653 device_printf(sc->dev, "cannot map doorbell BAR.\n"); 2654 return (ENXIO); 2655 } 2656 sc->udbs_base = rman_get_virtual(sc->udbs_res); 2657 2658 if (chip_id(sc) >= CHELSIO_T5) { 2659 setbit(&sc->doorbells, DOORBELL_UDB); 2660 #if defined(__i386__) || defined(__amd64__) 2661 if (t5_write_combine) { 2662 int rc, mode; 2663 2664 /* 2665 * Enable write combining on BAR2. This is the 2666 * userspace doorbell BAR and is split into 128B 2667 * (UDBS_SEG_SIZE) doorbell regions, each associated 2668 * with an egress queue. The first 64B has the doorbell 2669 * and the second 64B can be used to submit a tx work 2670 * request with an implicit doorbell. 2671 */ 2672 2673 rc = pmap_change_attr((vm_offset_t)sc->udbs_base, 2674 rman_get_size(sc->udbs_res), PAT_WRITE_COMBINING); 2675 if (rc == 0) { 2676 clrbit(&sc->doorbells, DOORBELL_UDB); 2677 setbit(&sc->doorbells, DOORBELL_WCWR); 2678 setbit(&sc->doorbells, DOORBELL_UDBWC); 2679 } else { 2680 device_printf(sc->dev, 2681 "couldn't enable write combining: %d\n", 2682 rc); 2683 } 2684 2685 mode = is_t5(sc) ? V_STATMODE(0) : V_T6_STATMODE(0); 2686 t4_write_reg(sc, A_SGE_STAT_CFG, 2687 V_STATSOURCE_T5(7) | mode); 2688 } 2689 #endif 2690 } 2691 sc->iwt.wc_en = isset(&sc->doorbells, DOORBELL_UDBWC) ? 1 : 0; 2692 2693 return (0); 2694 } 2695 2696 struct memwin_init { 2697 uint32_t base; 2698 uint32_t aperture; 2699 }; 2700 2701 static const struct memwin_init t4_memwin[NUM_MEMWIN] = { 2702 { MEMWIN0_BASE, MEMWIN0_APERTURE }, 2703 { MEMWIN1_BASE, MEMWIN1_APERTURE }, 2704 { MEMWIN2_BASE_T4, MEMWIN2_APERTURE_T4 } 2705 }; 2706 2707 static const struct memwin_init t5_memwin[NUM_MEMWIN] = { 2708 { MEMWIN0_BASE, MEMWIN0_APERTURE }, 2709 { MEMWIN1_BASE, MEMWIN1_APERTURE }, 2710 { MEMWIN2_BASE_T5, MEMWIN2_APERTURE_T5 }, 2711 }; 2712 2713 static void 2714 setup_memwin(struct adapter *sc) 2715 { 2716 const struct memwin_init *mw_init; 2717 struct memwin *mw; 2718 int i; 2719 uint32_t bar0; 2720 2721 if (is_t4(sc)) { 2722 /* 2723 * Read low 32b of bar0 indirectly via the hardware backdoor 2724 * mechanism. Works from within PCI passthrough environments 2725 * too, where rman_get_start() can return a different value. We 2726 * need to program the T4 memory window decoders with the actual 2727 * addresses that will be coming across the PCIe link. 2728 */ 2729 bar0 = t4_hw_pci_read_cfg4(sc, PCIR_BAR(0)); 2730 bar0 &= (uint32_t) PCIM_BAR_MEM_BASE; 2731 2732 mw_init = &t4_memwin[0]; 2733 } else { 2734 /* T5+ use the relative offset inside the PCIe BAR */ 2735 bar0 = 0; 2736 2737 mw_init = &t5_memwin[0]; 2738 } 2739 2740 for (i = 0, mw = &sc->memwin[0]; i < NUM_MEMWIN; i++, mw_init++, mw++) { 2741 rw_init(&mw->mw_lock, "memory window access"); 2742 mw->mw_base = mw_init->base; 2743 mw->mw_aperture = mw_init->aperture; 2744 mw->mw_curpos = 0; 2745 t4_write_reg(sc, 2746 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, i), 2747 (mw->mw_base + bar0) | V_BIR(0) | 2748 V_WINDOW(ilog2(mw->mw_aperture) - 10)); 2749 rw_wlock(&mw->mw_lock); 2750 position_memwin(sc, i, 0); 2751 rw_wunlock(&mw->mw_lock); 2752 } 2753 2754 /* flush */ 2755 t4_read_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2)); 2756 } 2757 2758 /* 2759 * Positions the memory window at the given address in the card's address space. 2760 * There are some alignment requirements and the actual position may be at an 2761 * address prior to the requested address. mw->mw_curpos always has the actual 2762 * position of the window. 2763 */ 2764 static void 2765 position_memwin(struct adapter *sc, int idx, uint32_t addr) 2766 { 2767 struct memwin *mw; 2768 uint32_t pf; 2769 uint32_t reg; 2770 2771 MPASS(idx >= 0 && idx < NUM_MEMWIN); 2772 mw = &sc->memwin[idx]; 2773 rw_assert(&mw->mw_lock, RA_WLOCKED); 2774 2775 if (is_t4(sc)) { 2776 pf = 0; 2777 mw->mw_curpos = addr & ~0xf; /* start must be 16B aligned */ 2778 } else { 2779 pf = V_PFNUM(sc->pf); 2780 mw->mw_curpos = addr & ~0x7f; /* start must be 128B aligned */ 2781 } 2782 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, idx); 2783 t4_write_reg(sc, reg, mw->mw_curpos | pf); 2784 t4_read_reg(sc, reg); /* flush */ 2785 } 2786 2787 int 2788 rw_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val, 2789 int len, int rw) 2790 { 2791 struct memwin *mw; 2792 uint32_t mw_end, v; 2793 2794 MPASS(idx >= 0 && idx < NUM_MEMWIN); 2795 2796 /* Memory can only be accessed in naturally aligned 4 byte units */ 2797 if (addr & 3 || len & 3 || len <= 0) 2798 return (EINVAL); 2799 2800 mw = &sc->memwin[idx]; 2801 while (len > 0) { 2802 rw_rlock(&mw->mw_lock); 2803 mw_end = mw->mw_curpos + mw->mw_aperture; 2804 if (addr >= mw_end || addr < mw->mw_curpos) { 2805 /* Will need to reposition the window */ 2806 if (!rw_try_upgrade(&mw->mw_lock)) { 2807 rw_runlock(&mw->mw_lock); 2808 rw_wlock(&mw->mw_lock); 2809 } 2810 rw_assert(&mw->mw_lock, RA_WLOCKED); 2811 position_memwin(sc, idx, addr); 2812 rw_downgrade(&mw->mw_lock); 2813 mw_end = mw->mw_curpos + mw->mw_aperture; 2814 } 2815 rw_assert(&mw->mw_lock, RA_RLOCKED); 2816 while (addr < mw_end && len > 0) { 2817 if (rw == 0) { 2818 v = t4_read_reg(sc, mw->mw_base + addr - 2819 mw->mw_curpos); 2820 *val++ = le32toh(v); 2821 } else { 2822 v = *val++; 2823 t4_write_reg(sc, mw->mw_base + addr - 2824 mw->mw_curpos, htole32(v)); 2825 } 2826 addr += 4; 2827 len -= 4; 2828 } 2829 rw_runlock(&mw->mw_lock); 2830 } 2831 2832 return (0); 2833 } 2834 2835 int 2836 alloc_atid_tab(struct tid_info *t, int flags) 2837 { 2838 int i; 2839 2840 MPASS(t->natids > 0); 2841 MPASS(t->atid_tab == NULL); 2842 2843 t->atid_tab = malloc(t->natids * sizeof(*t->atid_tab), M_CXGBE, 2844 M_ZERO | flags); 2845 if (t->atid_tab == NULL) 2846 return (ENOMEM); 2847 mtx_init(&t->atid_lock, "atid lock", NULL, MTX_DEF); 2848 t->afree = t->atid_tab; 2849 t->atids_in_use = 0; 2850 for (i = 1; i < t->natids; i++) 2851 t->atid_tab[i - 1].next = &t->atid_tab[i]; 2852 t->atid_tab[t->natids - 1].next = NULL; 2853 2854 return (0); 2855 } 2856 2857 void 2858 free_atid_tab(struct tid_info *t) 2859 { 2860 2861 KASSERT(t->atids_in_use == 0, 2862 ("%s: %d atids still in use.", __func__, t->atids_in_use)); 2863 2864 if (mtx_initialized(&t->atid_lock)) 2865 mtx_destroy(&t->atid_lock); 2866 free(t->atid_tab, M_CXGBE); 2867 t->atid_tab = NULL; 2868 } 2869 2870 int 2871 alloc_atid(struct adapter *sc, void *ctx) 2872 { 2873 struct tid_info *t = &sc->tids; 2874 int atid = -1; 2875 2876 mtx_lock(&t->atid_lock); 2877 if (t->afree) { 2878 union aopen_entry *p = t->afree; 2879 2880 atid = p - t->atid_tab; 2881 MPASS(atid <= M_TID_TID); 2882 t->afree = p->next; 2883 p->data = ctx; 2884 t->atids_in_use++; 2885 } 2886 mtx_unlock(&t->atid_lock); 2887 return (atid); 2888 } 2889 2890 void * 2891 lookup_atid(struct adapter *sc, int atid) 2892 { 2893 struct tid_info *t = &sc->tids; 2894 2895 return (t->atid_tab[atid].data); 2896 } 2897 2898 void 2899 free_atid(struct adapter *sc, int atid) 2900 { 2901 struct tid_info *t = &sc->tids; 2902 union aopen_entry *p = &t->atid_tab[atid]; 2903 2904 mtx_lock(&t->atid_lock); 2905 p->next = t->afree; 2906 t->afree = p; 2907 t->atids_in_use--; 2908 mtx_unlock(&t->atid_lock); 2909 } 2910 2911 static void 2912 queue_tid_release(struct adapter *sc, int tid) 2913 { 2914 2915 CXGBE_UNIMPLEMENTED("deferred tid release"); 2916 } 2917 2918 void 2919 release_tid(struct adapter *sc, int tid, struct sge_wrq *ctrlq) 2920 { 2921 struct wrqe *wr; 2922 struct cpl_tid_release *req; 2923 2924 wr = alloc_wrqe(sizeof(*req), ctrlq); 2925 if (wr == NULL) { 2926 queue_tid_release(sc, tid); /* defer */ 2927 return; 2928 } 2929 req = wrtod(wr); 2930 2931 INIT_TP_WR_MIT_CPL(req, CPL_TID_RELEASE, tid); 2932 2933 t4_wrq_tx(sc, wr); 2934 } 2935 2936 static int 2937 t4_range_cmp(const void *a, const void *b) 2938 { 2939 return ((const struct t4_range *)a)->start - 2940 ((const struct t4_range *)b)->start; 2941 } 2942 2943 /* 2944 * Verify that the memory range specified by the addr/len pair is valid within 2945 * the card's address space. 2946 */ 2947 static int 2948 validate_mem_range(struct adapter *sc, uint32_t addr, uint32_t len) 2949 { 2950 struct t4_range mem_ranges[4], *r, *next; 2951 uint32_t em, addr_len; 2952 int i, n, remaining; 2953 2954 /* Memory can only be accessed in naturally aligned 4 byte units */ 2955 if (addr & 3 || len & 3 || len == 0) 2956 return (EINVAL); 2957 2958 /* Enabled memories */ 2959 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 2960 2961 r = &mem_ranges[0]; 2962 n = 0; 2963 bzero(r, sizeof(mem_ranges)); 2964 if (em & F_EDRAM0_ENABLE) { 2965 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR); 2966 r->size = G_EDRAM0_SIZE(addr_len) << 20; 2967 if (r->size > 0) { 2968 r->start = G_EDRAM0_BASE(addr_len) << 20; 2969 if (addr >= r->start && 2970 addr + len <= r->start + r->size) 2971 return (0); 2972 r++; 2973 n++; 2974 } 2975 } 2976 if (em & F_EDRAM1_ENABLE) { 2977 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR); 2978 r->size = G_EDRAM1_SIZE(addr_len) << 20; 2979 if (r->size > 0) { 2980 r->start = G_EDRAM1_BASE(addr_len) << 20; 2981 if (addr >= r->start && 2982 addr + len <= r->start + r->size) 2983 return (0); 2984 r++; 2985 n++; 2986 } 2987 } 2988 if (em & F_EXT_MEM_ENABLE) { 2989 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 2990 r->size = G_EXT_MEM_SIZE(addr_len) << 20; 2991 if (r->size > 0) { 2992 r->start = G_EXT_MEM_BASE(addr_len) << 20; 2993 if (addr >= r->start && 2994 addr + len <= r->start + r->size) 2995 return (0); 2996 r++; 2997 n++; 2998 } 2999 } 3000 if (is_t5(sc) && em & F_EXT_MEM1_ENABLE) { 3001 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 3002 r->size = G_EXT_MEM1_SIZE(addr_len) << 20; 3003 if (r->size > 0) { 3004 r->start = G_EXT_MEM1_BASE(addr_len) << 20; 3005 if (addr >= r->start && 3006 addr + len <= r->start + r->size) 3007 return (0); 3008 r++; 3009 n++; 3010 } 3011 } 3012 MPASS(n <= nitems(mem_ranges)); 3013 3014 if (n > 1) { 3015 /* Sort and merge the ranges. */ 3016 qsort(mem_ranges, n, sizeof(struct t4_range), t4_range_cmp); 3017 3018 /* Start from index 0 and examine the next n - 1 entries. */ 3019 r = &mem_ranges[0]; 3020 for (remaining = n - 1; remaining > 0; remaining--, r++) { 3021 3022 MPASS(r->size > 0); /* r is a valid entry. */ 3023 next = r + 1; 3024 MPASS(next->size > 0); /* and so is the next one. */ 3025 3026 while (r->start + r->size >= next->start) { 3027 /* Merge the next one into the current entry. */ 3028 r->size = max(r->start + r->size, 3029 next->start + next->size) - r->start; 3030 n--; /* One fewer entry in total. */ 3031 if (--remaining == 0) 3032 goto done; /* short circuit */ 3033 next++; 3034 } 3035 if (next != r + 1) { 3036 /* 3037 * Some entries were merged into r and next 3038 * points to the first valid entry that couldn't 3039 * be merged. 3040 */ 3041 MPASS(next->size > 0); /* must be valid */ 3042 memcpy(r + 1, next, remaining * sizeof(*r)); 3043 #ifdef INVARIANTS 3044 /* 3045 * This so that the foo->size assertion in the 3046 * next iteration of the loop do the right 3047 * thing for entries that were pulled up and are 3048 * no longer valid. 3049 */ 3050 MPASS(n < nitems(mem_ranges)); 3051 bzero(&mem_ranges[n], (nitems(mem_ranges) - n) * 3052 sizeof(struct t4_range)); 3053 #endif 3054 } 3055 } 3056 done: 3057 /* Done merging the ranges. */ 3058 MPASS(n > 0); 3059 r = &mem_ranges[0]; 3060 for (i = 0; i < n; i++, r++) { 3061 if (addr >= r->start && 3062 addr + len <= r->start + r->size) 3063 return (0); 3064 } 3065 } 3066 3067 return (EFAULT); 3068 } 3069 3070 static int 3071 fwmtype_to_hwmtype(int mtype) 3072 { 3073 3074 switch (mtype) { 3075 case FW_MEMTYPE_EDC0: 3076 return (MEM_EDC0); 3077 case FW_MEMTYPE_EDC1: 3078 return (MEM_EDC1); 3079 case FW_MEMTYPE_EXTMEM: 3080 return (MEM_MC0); 3081 case FW_MEMTYPE_EXTMEM1: 3082 return (MEM_MC1); 3083 default: 3084 panic("%s: cannot translate fw mtype %d.", __func__, mtype); 3085 } 3086 } 3087 3088 /* 3089 * Verify that the memory range specified by the memtype/offset/len pair is 3090 * valid and lies entirely within the memtype specified. The global address of 3091 * the start of the range is returned in addr. 3092 */ 3093 static int 3094 validate_mt_off_len(struct adapter *sc, int mtype, uint32_t off, uint32_t len, 3095 uint32_t *addr) 3096 { 3097 uint32_t em, addr_len, maddr; 3098 3099 /* Memory can only be accessed in naturally aligned 4 byte units */ 3100 if (off & 3 || len & 3 || len == 0) 3101 return (EINVAL); 3102 3103 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 3104 switch (fwmtype_to_hwmtype(mtype)) { 3105 case MEM_EDC0: 3106 if (!(em & F_EDRAM0_ENABLE)) 3107 return (EINVAL); 3108 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR); 3109 maddr = G_EDRAM0_BASE(addr_len) << 20; 3110 break; 3111 case MEM_EDC1: 3112 if (!(em & F_EDRAM1_ENABLE)) 3113 return (EINVAL); 3114 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR); 3115 maddr = G_EDRAM1_BASE(addr_len) << 20; 3116 break; 3117 case MEM_MC: 3118 if (!(em & F_EXT_MEM_ENABLE)) 3119 return (EINVAL); 3120 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 3121 maddr = G_EXT_MEM_BASE(addr_len) << 20; 3122 break; 3123 case MEM_MC1: 3124 if (!is_t5(sc) || !(em & F_EXT_MEM1_ENABLE)) 3125 return (EINVAL); 3126 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 3127 maddr = G_EXT_MEM1_BASE(addr_len) << 20; 3128 break; 3129 default: 3130 return (EINVAL); 3131 } 3132 3133 *addr = maddr + off; /* global address */ 3134 return (validate_mem_range(sc, *addr, len)); 3135 } 3136 3137 static int 3138 fixup_devlog_params(struct adapter *sc) 3139 { 3140 struct devlog_params *dparams = &sc->params.devlog; 3141 int rc; 3142 3143 rc = validate_mt_off_len(sc, dparams->memtype, dparams->start, 3144 dparams->size, &dparams->addr); 3145 3146 return (rc); 3147 } 3148 3149 static void 3150 update_nirq(struct intrs_and_queues *iaq, int nports) 3151 { 3152 int extra = T4_EXTRA_INTR; 3153 3154 iaq->nirq = extra; 3155 iaq->nirq += nports * (iaq->nrxq + iaq->nofldrxq); 3156 iaq->nirq += nports * (iaq->num_vis - 1) * 3157 max(iaq->nrxq_vi, iaq->nnmrxq_vi); 3158 iaq->nirq += nports * (iaq->num_vis - 1) * iaq->nofldrxq_vi; 3159 } 3160 3161 /* 3162 * Adjust requirements to fit the number of interrupts available. 3163 */ 3164 static void 3165 calculate_iaq(struct adapter *sc, struct intrs_and_queues *iaq, int itype, 3166 int navail) 3167 { 3168 int old_nirq; 3169 const int nports = sc->params.nports; 3170 3171 MPASS(nports > 0); 3172 MPASS(navail > 0); 3173 3174 bzero(iaq, sizeof(*iaq)); 3175 iaq->intr_type = itype; 3176 iaq->num_vis = t4_num_vis; 3177 iaq->ntxq = t4_ntxq; 3178 iaq->ntxq_vi = t4_ntxq_vi; 3179 iaq->nrxq = t4_nrxq; 3180 iaq->nrxq_vi = t4_nrxq_vi; 3181 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 3182 if (is_offload(sc) || is_ethoffload(sc)) { 3183 iaq->nofldtxq = t4_nofldtxq; 3184 iaq->nofldtxq_vi = t4_nofldtxq_vi; 3185 } 3186 #endif 3187 #ifdef TCP_OFFLOAD 3188 if (is_offload(sc)) { 3189 iaq->nofldrxq = t4_nofldrxq; 3190 iaq->nofldrxq_vi = t4_nofldrxq_vi; 3191 } 3192 #endif 3193 #ifdef DEV_NETMAP 3194 iaq->nnmtxq_vi = t4_nnmtxq_vi; 3195 iaq->nnmrxq_vi = t4_nnmrxq_vi; 3196 #endif 3197 3198 update_nirq(iaq, nports); 3199 if (iaq->nirq <= navail && 3200 (itype != INTR_MSI || powerof2(iaq->nirq))) { 3201 /* 3202 * This is the normal case -- there are enough interrupts for 3203 * everything. 3204 */ 3205 goto done; 3206 } 3207 3208 /* 3209 * If extra VIs have been configured try reducing their count and see if 3210 * that works. 3211 */ 3212 while (iaq->num_vis > 1) { 3213 iaq->num_vis--; 3214 update_nirq(iaq, nports); 3215 if (iaq->nirq <= navail && 3216 (itype != INTR_MSI || powerof2(iaq->nirq))) { 3217 device_printf(sc->dev, "virtual interfaces per port " 3218 "reduced to %d from %d. nrxq=%u, nofldrxq=%u, " 3219 "nrxq_vi=%u nofldrxq_vi=%u, nnmrxq_vi=%u. " 3220 "itype %d, navail %u, nirq %d.\n", 3221 iaq->num_vis, t4_num_vis, iaq->nrxq, iaq->nofldrxq, 3222 iaq->nrxq_vi, iaq->nofldrxq_vi, iaq->nnmrxq_vi, 3223 itype, navail, iaq->nirq); 3224 goto done; 3225 } 3226 } 3227 3228 /* 3229 * Extra VIs will not be created. Log a message if they were requested. 3230 */ 3231 MPASS(iaq->num_vis == 1); 3232 iaq->ntxq_vi = iaq->nrxq_vi = 0; 3233 iaq->nofldtxq_vi = iaq->nofldrxq_vi = 0; 3234 iaq->nnmtxq_vi = iaq->nnmrxq_vi = 0; 3235 if (iaq->num_vis != t4_num_vis) { 3236 device_printf(sc->dev, "extra virtual interfaces disabled. " 3237 "nrxq=%u, nofldrxq=%u, nrxq_vi=%u nofldrxq_vi=%u, " 3238 "nnmrxq_vi=%u. itype %d, navail %u, nirq %d.\n", 3239 iaq->nrxq, iaq->nofldrxq, iaq->nrxq_vi, iaq->nofldrxq_vi, 3240 iaq->nnmrxq_vi, itype, navail, iaq->nirq); 3241 } 3242 3243 /* 3244 * Keep reducing the number of NIC rx queues to the next lower power of 3245 * 2 (for even RSS distribution) and halving the TOE rx queues and see 3246 * if that works. 3247 */ 3248 do { 3249 if (iaq->nrxq > 1) { 3250 do { 3251 iaq->nrxq--; 3252 } while (!powerof2(iaq->nrxq)); 3253 } 3254 if (iaq->nofldrxq > 1) 3255 iaq->nofldrxq >>= 1; 3256 3257 old_nirq = iaq->nirq; 3258 update_nirq(iaq, nports); 3259 if (iaq->nirq <= navail && 3260 (itype != INTR_MSI || powerof2(iaq->nirq))) { 3261 device_printf(sc->dev, "running with reduced number of " 3262 "rx queues because of shortage of interrupts. " 3263 "nrxq=%u, nofldrxq=%u. " 3264 "itype %d, navail %u, nirq %d.\n", iaq->nrxq, 3265 iaq->nofldrxq, itype, navail, iaq->nirq); 3266 goto done; 3267 } 3268 } while (old_nirq != iaq->nirq); 3269 3270 /* One interrupt for everything. Ugh. */ 3271 device_printf(sc->dev, "running with minimal number of queues. " 3272 "itype %d, navail %u.\n", itype, navail); 3273 iaq->nirq = 1; 3274 MPASS(iaq->nrxq == 1); 3275 iaq->ntxq = 1; 3276 if (iaq->nofldrxq > 1) 3277 iaq->nofldtxq = 1; 3278 done: 3279 MPASS(iaq->num_vis > 0); 3280 if (iaq->num_vis > 1) { 3281 MPASS(iaq->nrxq_vi > 0); 3282 MPASS(iaq->ntxq_vi > 0); 3283 } 3284 MPASS(iaq->nirq > 0); 3285 MPASS(iaq->nrxq > 0); 3286 MPASS(iaq->ntxq > 0); 3287 if (itype == INTR_MSI) { 3288 MPASS(powerof2(iaq->nirq)); 3289 } 3290 } 3291 3292 static int 3293 cfg_itype_and_nqueues(struct adapter *sc, struct intrs_and_queues *iaq) 3294 { 3295 int rc, itype, navail, nalloc; 3296 3297 for (itype = INTR_MSIX; itype; itype >>= 1) { 3298 3299 if ((itype & t4_intr_types) == 0) 3300 continue; /* not allowed */ 3301 3302 if (itype == INTR_MSIX) 3303 navail = pci_msix_count(sc->dev); 3304 else if (itype == INTR_MSI) 3305 navail = pci_msi_count(sc->dev); 3306 else 3307 navail = 1; 3308 restart: 3309 if (navail == 0) 3310 continue; 3311 3312 calculate_iaq(sc, iaq, itype, navail); 3313 nalloc = iaq->nirq; 3314 rc = 0; 3315 if (itype == INTR_MSIX) 3316 rc = pci_alloc_msix(sc->dev, &nalloc); 3317 else if (itype == INTR_MSI) 3318 rc = pci_alloc_msi(sc->dev, &nalloc); 3319 3320 if (rc == 0 && nalloc > 0) { 3321 if (nalloc == iaq->nirq) 3322 return (0); 3323 3324 /* 3325 * Didn't get the number requested. Use whatever number 3326 * the kernel is willing to allocate. 3327 */ 3328 device_printf(sc->dev, "fewer vectors than requested, " 3329 "type=%d, req=%d, rcvd=%d; will downshift req.\n", 3330 itype, iaq->nirq, nalloc); 3331 pci_release_msi(sc->dev); 3332 navail = nalloc; 3333 goto restart; 3334 } 3335 3336 device_printf(sc->dev, 3337 "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n", 3338 itype, rc, iaq->nirq, nalloc); 3339 } 3340 3341 device_printf(sc->dev, 3342 "failed to find a usable interrupt type. " 3343 "allowed=%d, msi-x=%d, msi=%d, intx=1", t4_intr_types, 3344 pci_msix_count(sc->dev), pci_msi_count(sc->dev)); 3345 3346 return (ENXIO); 3347 } 3348 3349 #define FW_VERSION(chip) ( \ 3350 V_FW_HDR_FW_VER_MAJOR(chip##FW_VERSION_MAJOR) | \ 3351 V_FW_HDR_FW_VER_MINOR(chip##FW_VERSION_MINOR) | \ 3352 V_FW_HDR_FW_VER_MICRO(chip##FW_VERSION_MICRO) | \ 3353 V_FW_HDR_FW_VER_BUILD(chip##FW_VERSION_BUILD)) 3354 #define FW_INTFVER(chip, intf) (chip##FW_HDR_INTFVER_##intf) 3355 3356 /* Just enough of fw_hdr to cover all version info. */ 3357 struct fw_h { 3358 __u8 ver; 3359 __u8 chip; 3360 __be16 len512; 3361 __be32 fw_ver; 3362 __be32 tp_microcode_ver; 3363 __u8 intfver_nic; 3364 __u8 intfver_vnic; 3365 __u8 intfver_ofld; 3366 __u8 intfver_ri; 3367 __u8 intfver_iscsipdu; 3368 __u8 intfver_iscsi; 3369 __u8 intfver_fcoepdu; 3370 __u8 intfver_fcoe; 3371 }; 3372 /* Spot check a couple of fields. */ 3373 CTASSERT(offsetof(struct fw_h, fw_ver) == offsetof(struct fw_hdr, fw_ver)); 3374 CTASSERT(offsetof(struct fw_h, intfver_nic) == offsetof(struct fw_hdr, intfver_nic)); 3375 CTASSERT(offsetof(struct fw_h, intfver_fcoe) == offsetof(struct fw_hdr, intfver_fcoe)); 3376 3377 struct fw_info { 3378 uint8_t chip; 3379 char *kld_name; 3380 char *fw_mod_name; 3381 struct fw_h fw_h; 3382 } fw_info[] = { 3383 { 3384 .chip = CHELSIO_T4, 3385 .kld_name = "t4fw_cfg", 3386 .fw_mod_name = "t4fw", 3387 .fw_h = { 3388 .chip = FW_HDR_CHIP_T4, 3389 .fw_ver = htobe32(FW_VERSION(T4)), 3390 .intfver_nic = FW_INTFVER(T4, NIC), 3391 .intfver_vnic = FW_INTFVER(T4, VNIC), 3392 .intfver_ofld = FW_INTFVER(T4, OFLD), 3393 .intfver_ri = FW_INTFVER(T4, RI), 3394 .intfver_iscsipdu = FW_INTFVER(T4, ISCSIPDU), 3395 .intfver_iscsi = FW_INTFVER(T4, ISCSI), 3396 .intfver_fcoepdu = FW_INTFVER(T4, FCOEPDU), 3397 .intfver_fcoe = FW_INTFVER(T4, FCOE), 3398 }, 3399 }, { 3400 .chip = CHELSIO_T5, 3401 .kld_name = "t5fw_cfg", 3402 .fw_mod_name = "t5fw", 3403 .fw_h = { 3404 .chip = FW_HDR_CHIP_T5, 3405 .fw_ver = htobe32(FW_VERSION(T5)), 3406 .intfver_nic = FW_INTFVER(T5, NIC), 3407 .intfver_vnic = FW_INTFVER(T5, VNIC), 3408 .intfver_ofld = FW_INTFVER(T5, OFLD), 3409 .intfver_ri = FW_INTFVER(T5, RI), 3410 .intfver_iscsipdu = FW_INTFVER(T5, ISCSIPDU), 3411 .intfver_iscsi = FW_INTFVER(T5, ISCSI), 3412 .intfver_fcoepdu = FW_INTFVER(T5, FCOEPDU), 3413 .intfver_fcoe = FW_INTFVER(T5, FCOE), 3414 }, 3415 }, { 3416 .chip = CHELSIO_T6, 3417 .kld_name = "t6fw_cfg", 3418 .fw_mod_name = "t6fw", 3419 .fw_h = { 3420 .chip = FW_HDR_CHIP_T6, 3421 .fw_ver = htobe32(FW_VERSION(T6)), 3422 .intfver_nic = FW_INTFVER(T6, NIC), 3423 .intfver_vnic = FW_INTFVER(T6, VNIC), 3424 .intfver_ofld = FW_INTFVER(T6, OFLD), 3425 .intfver_ri = FW_INTFVER(T6, RI), 3426 .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU), 3427 .intfver_iscsi = FW_INTFVER(T6, ISCSI), 3428 .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU), 3429 .intfver_fcoe = FW_INTFVER(T6, FCOE), 3430 }, 3431 } 3432 }; 3433 3434 static struct fw_info * 3435 find_fw_info(int chip) 3436 { 3437 int i; 3438 3439 for (i = 0; i < nitems(fw_info); i++) { 3440 if (fw_info[i].chip == chip) 3441 return (&fw_info[i]); 3442 } 3443 return (NULL); 3444 } 3445 3446 /* 3447 * Is the given firmware API compatible with the one the driver was compiled 3448 * with? 3449 */ 3450 static int 3451 fw_compatible(const struct fw_h *hdr1, const struct fw_h *hdr2) 3452 { 3453 3454 /* short circuit if it's the exact same firmware version */ 3455 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver) 3456 return (1); 3457 3458 /* 3459 * XXX: Is this too conservative? Perhaps I should limit this to the 3460 * features that are supported in the driver. 3461 */ 3462 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x) 3463 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) && 3464 SAME_INTF(ofld) && SAME_INTF(ri) && SAME_INTF(iscsipdu) && 3465 SAME_INTF(iscsi) && SAME_INTF(fcoepdu) && SAME_INTF(fcoe)) 3466 return (1); 3467 #undef SAME_INTF 3468 3469 return (0); 3470 } 3471 3472 static int 3473 load_fw_module(struct adapter *sc, const struct firmware **dcfg, 3474 const struct firmware **fw) 3475 { 3476 struct fw_info *fw_info; 3477 3478 *dcfg = NULL; 3479 if (fw != NULL) 3480 *fw = NULL; 3481 3482 fw_info = find_fw_info(chip_id(sc)); 3483 if (fw_info == NULL) { 3484 device_printf(sc->dev, 3485 "unable to look up firmware information for chip %d.\n", 3486 chip_id(sc)); 3487 return (EINVAL); 3488 } 3489 3490 *dcfg = firmware_get(fw_info->kld_name); 3491 if (*dcfg != NULL) { 3492 if (fw != NULL) 3493 *fw = firmware_get(fw_info->fw_mod_name); 3494 return (0); 3495 } 3496 3497 return (ENOENT); 3498 } 3499 3500 static void 3501 unload_fw_module(struct adapter *sc, const struct firmware *dcfg, 3502 const struct firmware *fw) 3503 { 3504 3505 if (fw != NULL) 3506 firmware_put(fw, FIRMWARE_UNLOAD); 3507 if (dcfg != NULL) 3508 firmware_put(dcfg, FIRMWARE_UNLOAD); 3509 } 3510 3511 /* 3512 * Return values: 3513 * 0 means no firmware install attempted. 3514 * ERESTART means a firmware install was attempted and was successful. 3515 * +ve errno means a firmware install was attempted but failed. 3516 */ 3517 static int 3518 install_kld_firmware(struct adapter *sc, struct fw_h *card_fw, 3519 const struct fw_h *drv_fw, const char *reason, int *already) 3520 { 3521 const struct firmware *cfg, *fw; 3522 const uint32_t c = be32toh(card_fw->fw_ver); 3523 uint32_t d, k; 3524 int rc, fw_install; 3525 struct fw_h bundled_fw; 3526 bool load_attempted; 3527 3528 cfg = fw = NULL; 3529 load_attempted = false; 3530 fw_install = t4_fw_install < 0 ? -t4_fw_install : t4_fw_install; 3531 3532 if (reason != NULL) 3533 goto install; 3534 3535 if ((sc->flags & FW_OK) == 0) { 3536 3537 if (c == 0xffffffff) { 3538 reason = "missing"; 3539 goto install; 3540 } 3541 3542 return (0); 3543 } 3544 3545 memcpy(&bundled_fw, drv_fw, sizeof(bundled_fw)); 3546 if (t4_fw_install < 0) { 3547 rc = load_fw_module(sc, &cfg, &fw); 3548 if (rc != 0 || fw == NULL) { 3549 device_printf(sc->dev, 3550 "failed to load firmware module: %d. cfg %p, fw %p;" 3551 " will use compiled-in firmware version for" 3552 "hw.cxgbe.fw_install checks.\n", 3553 rc, cfg, fw); 3554 } else { 3555 memcpy(&bundled_fw, fw->data, sizeof(bundled_fw)); 3556 } 3557 load_attempted = true; 3558 } 3559 d = be32toh(bundled_fw.fw_ver); 3560 3561 if (!fw_compatible(card_fw, &bundled_fw)) { 3562 reason = "incompatible or unusable"; 3563 goto install; 3564 } 3565 3566 if (d > c) { 3567 reason = "older than the version bundled with this driver"; 3568 goto install; 3569 } 3570 3571 if (fw_install == 2 && d != c) { 3572 reason = "different than the version bundled with this driver"; 3573 goto install; 3574 } 3575 3576 /* No reason to do anything to the firmware already on the card. */ 3577 rc = 0; 3578 goto done; 3579 3580 install: 3581 rc = 0; 3582 if ((*already)++) 3583 goto done; 3584 3585 if (fw_install == 0) { 3586 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 3587 "but the driver is prohibited from installing a firmware " 3588 "on the card.\n", 3589 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 3590 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason); 3591 3592 goto done; 3593 } 3594 3595 /* 3596 * We'll attempt to install a firmware. Load the module first (if it 3597 * hasn't been loaded already). 3598 */ 3599 if (!load_attempted) { 3600 rc = load_fw_module(sc, &cfg, &fw); 3601 if (rc != 0 || fw == NULL) { 3602 device_printf(sc->dev, 3603 "failed to load firmware module: %d. cfg %p, fw %p\n", 3604 rc, cfg, fw); 3605 /* carry on */ 3606 } 3607 } 3608 if (fw == NULL) { 3609 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 3610 "but the driver cannot take corrective action because it " 3611 "is unable to load the firmware module.\n", 3612 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 3613 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason); 3614 rc = sc->flags & FW_OK ? 0 : ENOENT; 3615 goto done; 3616 } 3617 k = be32toh(((const struct fw_hdr *)fw->data)->fw_ver); 3618 if (k != d) { 3619 MPASS(t4_fw_install > 0); 3620 device_printf(sc->dev, 3621 "firmware in KLD (%u.%u.%u.%u) is not what the driver was " 3622 "expecting (%u.%u.%u.%u) and will not be used.\n", 3623 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k), 3624 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k), 3625 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d), 3626 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d)); 3627 rc = sc->flags & FW_OK ? 0 : EINVAL; 3628 goto done; 3629 } 3630 3631 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 3632 "installing firmware %u.%u.%u.%u on card.\n", 3633 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 3634 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason, 3635 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d), 3636 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d)); 3637 3638 rc = -t4_fw_upgrade(sc, sc->mbox, fw->data, fw->datasize, 0); 3639 if (rc != 0) { 3640 device_printf(sc->dev, "failed to install firmware: %d\n", rc); 3641 } else { 3642 /* Installed successfully, update the cached header too. */ 3643 rc = ERESTART; 3644 memcpy(card_fw, fw->data, sizeof(*card_fw)); 3645 } 3646 done: 3647 unload_fw_module(sc, cfg, fw); 3648 3649 return (rc); 3650 } 3651 3652 /* 3653 * Establish contact with the firmware and attempt to become the master driver. 3654 * 3655 * A firmware will be installed to the card if needed (if the driver is allowed 3656 * to do so). 3657 */ 3658 static int 3659 contact_firmware(struct adapter *sc) 3660 { 3661 int rc, already = 0; 3662 enum dev_state state; 3663 struct fw_info *fw_info; 3664 struct fw_hdr *card_fw; /* fw on the card */ 3665 const struct fw_h *drv_fw; 3666 3667 fw_info = find_fw_info(chip_id(sc)); 3668 if (fw_info == NULL) { 3669 device_printf(sc->dev, 3670 "unable to look up firmware information for chip %d.\n", 3671 chip_id(sc)); 3672 return (EINVAL); 3673 } 3674 drv_fw = &fw_info->fw_h; 3675 3676 /* Read the header of the firmware on the card */ 3677 card_fw = malloc(sizeof(*card_fw), M_CXGBE, M_ZERO | M_WAITOK); 3678 restart: 3679 rc = -t4_get_fw_hdr(sc, card_fw); 3680 if (rc != 0) { 3681 device_printf(sc->dev, 3682 "unable to read firmware header from card's flash: %d\n", 3683 rc); 3684 goto done; 3685 } 3686 3687 rc = install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw, NULL, 3688 &already); 3689 if (rc == ERESTART) 3690 goto restart; 3691 if (rc != 0) 3692 goto done; 3693 3694 rc = t4_fw_hello(sc, sc->mbox, sc->mbox, MASTER_MAY, &state); 3695 if (rc < 0 || state == DEV_STATE_ERR) { 3696 rc = -rc; 3697 device_printf(sc->dev, 3698 "failed to connect to the firmware: %d, %d. " 3699 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW)); 3700 #if 0 3701 if (install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw, 3702 "not responding properly to HELLO", &already) == ERESTART) 3703 goto restart; 3704 #endif 3705 goto done; 3706 } 3707 MPASS(be32toh(card_fw->flags) & FW_HDR_FLAGS_RESET_HALT); 3708 sc->flags |= FW_OK; /* The firmware responded to the FW_HELLO. */ 3709 3710 if (rc == sc->pf) { 3711 sc->flags |= MASTER_PF; 3712 rc = install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw, 3713 NULL, &already); 3714 if (rc == ERESTART) 3715 rc = 0; 3716 else if (rc != 0) 3717 goto done; 3718 } else if (state == DEV_STATE_UNINIT) { 3719 /* 3720 * We didn't get to be the master so we definitely won't be 3721 * configuring the chip. It's a bug if someone else hasn't 3722 * configured it already. 3723 */ 3724 device_printf(sc->dev, "couldn't be master(%d), " 3725 "device not already initialized either(%d). " 3726 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW)); 3727 rc = EPROTO; 3728 goto done; 3729 } else { 3730 /* 3731 * Some other PF is the master and has configured the chip. 3732 * This is allowed but untested. 3733 */ 3734 device_printf(sc->dev, "PF%d is master, device state %d. " 3735 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW)); 3736 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "pf%d", rc); 3737 sc->cfcsum = 0; 3738 rc = 0; 3739 } 3740 done: 3741 if (rc != 0 && sc->flags & FW_OK) { 3742 t4_fw_bye(sc, sc->mbox); 3743 sc->flags &= ~FW_OK; 3744 } 3745 free(card_fw, M_CXGBE); 3746 return (rc); 3747 } 3748 3749 static int 3750 copy_cfg_file_to_card(struct adapter *sc, char *cfg_file, 3751 uint32_t mtype, uint32_t moff) 3752 { 3753 struct fw_info *fw_info; 3754 const struct firmware *dcfg, *rcfg = NULL; 3755 const uint32_t *cfdata; 3756 uint32_t cflen, addr; 3757 int rc; 3758 3759 load_fw_module(sc, &dcfg, NULL); 3760 3761 /* Card specific interpretation of "default". */ 3762 if (strncmp(cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) { 3763 if (pci_get_device(sc->dev) == 0x440a) 3764 snprintf(cfg_file, sizeof(t4_cfg_file), UWIRE_CF); 3765 if (is_fpga(sc)) 3766 snprintf(cfg_file, sizeof(t4_cfg_file), FPGA_CF); 3767 } 3768 3769 if (strncmp(cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) { 3770 if (dcfg == NULL) { 3771 device_printf(sc->dev, 3772 "KLD with default config is not available.\n"); 3773 rc = ENOENT; 3774 goto done; 3775 } 3776 cfdata = dcfg->data; 3777 cflen = dcfg->datasize & ~3; 3778 } else { 3779 char s[32]; 3780 3781 fw_info = find_fw_info(chip_id(sc)); 3782 if (fw_info == NULL) { 3783 device_printf(sc->dev, 3784 "unable to look up firmware information for chip %d.\n", 3785 chip_id(sc)); 3786 rc = EINVAL; 3787 goto done; 3788 } 3789 snprintf(s, sizeof(s), "%s_%s", fw_info->kld_name, cfg_file); 3790 3791 rcfg = firmware_get(s); 3792 if (rcfg == NULL) { 3793 device_printf(sc->dev, 3794 "unable to load module \"%s\" for configuration " 3795 "profile \"%s\".\n", s, cfg_file); 3796 rc = ENOENT; 3797 goto done; 3798 } 3799 cfdata = rcfg->data; 3800 cflen = rcfg->datasize & ~3; 3801 } 3802 3803 if (cflen > FLASH_CFG_MAX_SIZE) { 3804 device_printf(sc->dev, 3805 "config file too long (%d, max allowed is %d).\n", 3806 cflen, FLASH_CFG_MAX_SIZE); 3807 rc = EINVAL; 3808 goto done; 3809 } 3810 3811 rc = validate_mt_off_len(sc, mtype, moff, cflen, &addr); 3812 if (rc != 0) { 3813 device_printf(sc->dev, 3814 "%s: addr (%d/0x%x) or len %d is not valid: %d.\n", 3815 __func__, mtype, moff, cflen, rc); 3816 rc = EINVAL; 3817 goto done; 3818 } 3819 write_via_memwin(sc, 2, addr, cfdata, cflen); 3820 done: 3821 if (rcfg != NULL) 3822 firmware_put(rcfg, FIRMWARE_UNLOAD); 3823 unload_fw_module(sc, dcfg, NULL); 3824 return (rc); 3825 } 3826 3827 struct caps_allowed { 3828 uint16_t nbmcaps; 3829 uint16_t linkcaps; 3830 uint16_t switchcaps; 3831 uint16_t niccaps; 3832 uint16_t toecaps; 3833 uint16_t rdmacaps; 3834 uint16_t cryptocaps; 3835 uint16_t iscsicaps; 3836 uint16_t fcoecaps; 3837 }; 3838 3839 #define FW_PARAM_DEV(param) \ 3840 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \ 3841 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param)) 3842 #define FW_PARAM_PFVF(param) \ 3843 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \ 3844 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param)) 3845 3846 /* 3847 * Provide a configuration profile to the firmware and have it initialize the 3848 * chip accordingly. This may involve uploading a configuration file to the 3849 * card. 3850 */ 3851 static int 3852 apply_cfg_and_initialize(struct adapter *sc, char *cfg_file, 3853 const struct caps_allowed *caps_allowed) 3854 { 3855 int rc; 3856 struct fw_caps_config_cmd caps; 3857 uint32_t mtype, moff, finicsum, cfcsum, param, val; 3858 3859 rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST); 3860 if (rc != 0) { 3861 device_printf(sc->dev, "firmware reset failed: %d.\n", rc); 3862 return (rc); 3863 } 3864 3865 bzero(&caps, sizeof(caps)); 3866 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 3867 F_FW_CMD_REQUEST | F_FW_CMD_READ); 3868 if (strncmp(cfg_file, BUILTIN_CF, sizeof(t4_cfg_file)) == 0) { 3869 mtype = 0; 3870 moff = 0; 3871 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 3872 } else if (strncmp(cfg_file, FLASH_CF, sizeof(t4_cfg_file)) == 0) { 3873 mtype = FW_MEMTYPE_FLASH; 3874 moff = t4_flash_cfg_addr(sc); 3875 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID | 3876 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) | 3877 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) | 3878 FW_LEN16(caps)); 3879 } else { 3880 /* 3881 * Ask the firmware where it wants us to upload the config file. 3882 */ 3883 param = FW_PARAM_DEV(CF); 3884 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 3885 if (rc != 0) { 3886 /* No support for config file? Shouldn't happen. */ 3887 device_printf(sc->dev, 3888 "failed to query config file location: %d.\n", rc); 3889 goto done; 3890 } 3891 mtype = G_FW_PARAMS_PARAM_Y(val); 3892 moff = G_FW_PARAMS_PARAM_Z(val) << 16; 3893 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID | 3894 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) | 3895 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) | 3896 FW_LEN16(caps)); 3897 3898 rc = copy_cfg_file_to_card(sc, cfg_file, mtype, moff); 3899 if (rc != 0) { 3900 device_printf(sc->dev, 3901 "failed to upload config file to card: %d.\n", rc); 3902 goto done; 3903 } 3904 } 3905 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps); 3906 if (rc != 0) { 3907 device_printf(sc->dev, "failed to pre-process config file: %d " 3908 "(mtype %d, moff 0x%x).\n", rc, mtype, moff); 3909 goto done; 3910 } 3911 3912 finicsum = be32toh(caps.finicsum); 3913 cfcsum = be32toh(caps.cfcsum); /* actual */ 3914 if (finicsum != cfcsum) { 3915 device_printf(sc->dev, 3916 "WARNING: config file checksum mismatch: %08x %08x\n", 3917 finicsum, cfcsum); 3918 } 3919 sc->cfcsum = cfcsum; 3920 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", cfg_file); 3921 3922 /* 3923 * Let the firmware know what features will (not) be used so it can tune 3924 * things accordingly. 3925 */ 3926 #define LIMIT_CAPS(x) do { \ 3927 caps.x##caps &= htobe16(caps_allowed->x##caps); \ 3928 } while (0) 3929 LIMIT_CAPS(nbm); 3930 LIMIT_CAPS(link); 3931 LIMIT_CAPS(switch); 3932 LIMIT_CAPS(nic); 3933 LIMIT_CAPS(toe); 3934 LIMIT_CAPS(rdma); 3935 LIMIT_CAPS(crypto); 3936 LIMIT_CAPS(iscsi); 3937 LIMIT_CAPS(fcoe); 3938 #undef LIMIT_CAPS 3939 if (caps.niccaps & htobe16(FW_CAPS_CONFIG_NIC_HASHFILTER)) { 3940 /* 3941 * TOE and hashfilters are mutually exclusive. It is a config 3942 * file or firmware bug if both are reported as available. Try 3943 * to cope with the situation in non-debug builds by disabling 3944 * TOE. 3945 */ 3946 MPASS(caps.toecaps == 0); 3947 3948 caps.toecaps = 0; 3949 caps.rdmacaps = 0; 3950 caps.iscsicaps = 0; 3951 } 3952 3953 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 3954 F_FW_CMD_REQUEST | F_FW_CMD_WRITE); 3955 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 3956 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), NULL); 3957 if (rc != 0) { 3958 device_printf(sc->dev, 3959 "failed to process config file: %d.\n", rc); 3960 goto done; 3961 } 3962 3963 t4_tweak_chip_settings(sc); 3964 set_params__pre_init(sc); 3965 3966 /* get basic stuff going */ 3967 rc = -t4_fw_initialize(sc, sc->mbox); 3968 if (rc != 0) { 3969 device_printf(sc->dev, "fw_initialize failed: %d.\n", rc); 3970 goto done; 3971 } 3972 done: 3973 return (rc); 3974 } 3975 3976 /* 3977 * Partition chip resources for use between various PFs, VFs, etc. 3978 */ 3979 static int 3980 partition_resources(struct adapter *sc) 3981 { 3982 char cfg_file[sizeof(t4_cfg_file)]; 3983 struct caps_allowed caps_allowed; 3984 int rc; 3985 bool fallback; 3986 3987 /* Only the master driver gets to configure the chip resources. */ 3988 MPASS(sc->flags & MASTER_PF); 3989 3990 #define COPY_CAPS(x) do { \ 3991 caps_allowed.x##caps = t4_##x##caps_allowed; \ 3992 } while (0) 3993 bzero(&caps_allowed, sizeof(caps_allowed)); 3994 COPY_CAPS(nbm); 3995 COPY_CAPS(link); 3996 COPY_CAPS(switch); 3997 COPY_CAPS(nic); 3998 COPY_CAPS(toe); 3999 COPY_CAPS(rdma); 4000 COPY_CAPS(crypto); 4001 COPY_CAPS(iscsi); 4002 COPY_CAPS(fcoe); 4003 fallback = sc->debug_flags & DF_DISABLE_CFG_RETRY ? false : true; 4004 snprintf(cfg_file, sizeof(cfg_file), "%s", t4_cfg_file); 4005 retry: 4006 rc = apply_cfg_and_initialize(sc, cfg_file, &caps_allowed); 4007 if (rc != 0 && fallback) { 4008 device_printf(sc->dev, 4009 "failed (%d) to configure card with \"%s\" profile, " 4010 "will fall back to a basic configuration and retry.\n", 4011 rc, cfg_file); 4012 snprintf(cfg_file, sizeof(cfg_file), "%s", BUILTIN_CF); 4013 bzero(&caps_allowed, sizeof(caps_allowed)); 4014 COPY_CAPS(nbm); 4015 COPY_CAPS(link); 4016 COPY_CAPS(switch); 4017 COPY_CAPS(nic); 4018 fallback = false; 4019 goto retry; 4020 } 4021 #undef COPY_CAPS 4022 return (rc); 4023 } 4024 4025 /* 4026 * Retrieve parameters that are needed (or nice to have) very early. 4027 */ 4028 static int 4029 get_params__pre_init(struct adapter *sc) 4030 { 4031 int rc; 4032 uint32_t param[2], val[2]; 4033 4034 t4_get_version_info(sc); 4035 4036 snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u", 4037 G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers), 4038 G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers), 4039 G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers), 4040 G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers)); 4041 4042 snprintf(sc->bs_version, sizeof(sc->bs_version), "%u.%u.%u.%u", 4043 G_FW_HDR_FW_VER_MAJOR(sc->params.bs_vers), 4044 G_FW_HDR_FW_VER_MINOR(sc->params.bs_vers), 4045 G_FW_HDR_FW_VER_MICRO(sc->params.bs_vers), 4046 G_FW_HDR_FW_VER_BUILD(sc->params.bs_vers)); 4047 4048 snprintf(sc->tp_version, sizeof(sc->tp_version), "%u.%u.%u.%u", 4049 G_FW_HDR_FW_VER_MAJOR(sc->params.tp_vers), 4050 G_FW_HDR_FW_VER_MINOR(sc->params.tp_vers), 4051 G_FW_HDR_FW_VER_MICRO(sc->params.tp_vers), 4052 G_FW_HDR_FW_VER_BUILD(sc->params.tp_vers)); 4053 4054 snprintf(sc->er_version, sizeof(sc->er_version), "%u.%u.%u.%u", 4055 G_FW_HDR_FW_VER_MAJOR(sc->params.er_vers), 4056 G_FW_HDR_FW_VER_MINOR(sc->params.er_vers), 4057 G_FW_HDR_FW_VER_MICRO(sc->params.er_vers), 4058 G_FW_HDR_FW_VER_BUILD(sc->params.er_vers)); 4059 4060 param[0] = FW_PARAM_DEV(PORTVEC); 4061 param[1] = FW_PARAM_DEV(CCLK); 4062 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 4063 if (rc != 0) { 4064 device_printf(sc->dev, 4065 "failed to query parameters (pre_init): %d.\n", rc); 4066 return (rc); 4067 } 4068 4069 sc->params.portvec = val[0]; 4070 sc->params.nports = bitcount32(val[0]); 4071 sc->params.vpd.cclk = val[1]; 4072 4073 /* Read device log parameters. */ 4074 rc = -t4_init_devlog_params(sc, 1); 4075 if (rc == 0) 4076 fixup_devlog_params(sc); 4077 else { 4078 device_printf(sc->dev, 4079 "failed to get devlog parameters: %d.\n", rc); 4080 rc = 0; /* devlog isn't critical for device operation */ 4081 } 4082 4083 return (rc); 4084 } 4085 4086 /* 4087 * Any params that need to be set before FW_INITIALIZE. 4088 */ 4089 static int 4090 set_params__pre_init(struct adapter *sc) 4091 { 4092 int rc = 0; 4093 uint32_t param, val; 4094 4095 if (chip_id(sc) >= CHELSIO_T6) { 4096 param = FW_PARAM_DEV(HPFILTER_REGION_SUPPORT); 4097 val = 1; 4098 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 4099 /* firmwares < 1.20.1.0 do not have this param. */ 4100 if (rc == FW_EINVAL && sc->params.fw_vers < 4101 (V_FW_HDR_FW_VER_MAJOR(1) | V_FW_HDR_FW_VER_MINOR(20) | 4102 V_FW_HDR_FW_VER_MICRO(1) | V_FW_HDR_FW_VER_BUILD(0))) { 4103 rc = 0; 4104 } 4105 if (rc != 0) { 4106 device_printf(sc->dev, 4107 "failed to enable high priority filters :%d.\n", 4108 rc); 4109 } 4110 } 4111 4112 /* Enable opaque VIIDs with firmwares that support it. */ 4113 param = FW_PARAM_DEV(OPAQUE_VIID_SMT_EXTN); 4114 val = 1; 4115 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 4116 if (rc == 0 && val == 1) 4117 sc->params.viid_smt_extn_support = true; 4118 else 4119 sc->params.viid_smt_extn_support = false; 4120 4121 return (rc); 4122 } 4123 4124 /* 4125 * Retrieve various parameters that are of interest to the driver. The device 4126 * has been initialized by the firmware at this point. 4127 */ 4128 static int 4129 get_params__post_init(struct adapter *sc) 4130 { 4131 int rc; 4132 uint32_t param[7], val[7]; 4133 struct fw_caps_config_cmd caps; 4134 4135 param[0] = FW_PARAM_PFVF(IQFLINT_START); 4136 param[1] = FW_PARAM_PFVF(EQ_START); 4137 param[2] = FW_PARAM_PFVF(FILTER_START); 4138 param[3] = FW_PARAM_PFVF(FILTER_END); 4139 param[4] = FW_PARAM_PFVF(L2T_START); 4140 param[5] = FW_PARAM_PFVF(L2T_END); 4141 param[6] = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 4142 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 4143 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_VDD); 4144 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 7, param, val); 4145 if (rc != 0) { 4146 device_printf(sc->dev, 4147 "failed to query parameters (post_init): %d.\n", rc); 4148 return (rc); 4149 } 4150 4151 sc->sge.iq_start = val[0]; 4152 sc->sge.eq_start = val[1]; 4153 if ((int)val[3] > (int)val[2]) { 4154 sc->tids.ftid_base = val[2]; 4155 sc->tids.ftid_end = val[3]; 4156 sc->tids.nftids = val[3] - val[2] + 1; 4157 } 4158 sc->vres.l2t.start = val[4]; 4159 sc->vres.l2t.size = val[5] - val[4] + 1; 4160 KASSERT(sc->vres.l2t.size <= L2T_SIZE, 4161 ("%s: L2 table size (%u) larger than expected (%u)", 4162 __func__, sc->vres.l2t.size, L2T_SIZE)); 4163 sc->params.core_vdd = val[6]; 4164 4165 if (chip_id(sc) >= CHELSIO_T6) { 4166 4167 sc->tids.tid_base = t4_read_reg(sc, 4168 A_LE_DB_ACTIVE_TABLE_START_INDEX); 4169 4170 param[0] = FW_PARAM_PFVF(HPFILTER_START); 4171 param[1] = FW_PARAM_PFVF(HPFILTER_END); 4172 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 4173 if (rc != 0) { 4174 device_printf(sc->dev, 4175 "failed to query hpfilter parameters: %d.\n", rc); 4176 return (rc); 4177 } 4178 if ((int)val[1] > (int)val[0]) { 4179 sc->tids.hpftid_base = val[0]; 4180 sc->tids.hpftid_end = val[1]; 4181 sc->tids.nhpftids = val[1] - val[0] + 1; 4182 4183 /* 4184 * These should go off if the layout changes and the 4185 * driver needs to catch up. 4186 */ 4187 MPASS(sc->tids.hpftid_base == 0); 4188 MPASS(sc->tids.tid_base == sc->tids.nhpftids); 4189 } 4190 } 4191 4192 /* 4193 * MPSBGMAP is queried separately because only recent firmwares support 4194 * it as a parameter and we don't want the compound query above to fail 4195 * on older firmwares. 4196 */ 4197 param[0] = FW_PARAM_DEV(MPSBGMAP); 4198 val[0] = 0; 4199 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 4200 if (rc == 0) 4201 sc->params.mps_bg_map = val[0]; 4202 else 4203 sc->params.mps_bg_map = 0; 4204 4205 /* 4206 * Determine whether the firmware supports the filter2 work request. 4207 * This is queried separately for the same reason as MPSBGMAP above. 4208 */ 4209 param[0] = FW_PARAM_DEV(FILTER2_WR); 4210 val[0] = 0; 4211 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 4212 if (rc == 0) 4213 sc->params.filter2_wr_support = val[0] != 0; 4214 else 4215 sc->params.filter2_wr_support = 0; 4216 4217 /* 4218 * Find out whether we're allowed to use the ULPTX MEMWRITE DSGL. 4219 * This is queried separately for the same reason as other params above. 4220 */ 4221 param[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL); 4222 val[0] = 0; 4223 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 4224 if (rc == 0) 4225 sc->params.ulptx_memwrite_dsgl = val[0] != 0; 4226 else 4227 sc->params.ulptx_memwrite_dsgl = false; 4228 4229 /* get capabilites */ 4230 bzero(&caps, sizeof(caps)); 4231 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 4232 F_FW_CMD_REQUEST | F_FW_CMD_READ); 4233 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 4234 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps); 4235 if (rc != 0) { 4236 device_printf(sc->dev, 4237 "failed to get card capabilities: %d.\n", rc); 4238 return (rc); 4239 } 4240 4241 #define READ_CAPS(x) do { \ 4242 sc->x = htobe16(caps.x); \ 4243 } while (0) 4244 READ_CAPS(nbmcaps); 4245 READ_CAPS(linkcaps); 4246 READ_CAPS(switchcaps); 4247 READ_CAPS(niccaps); 4248 READ_CAPS(toecaps); 4249 READ_CAPS(rdmacaps); 4250 READ_CAPS(cryptocaps); 4251 READ_CAPS(iscsicaps); 4252 READ_CAPS(fcoecaps); 4253 4254 if (sc->niccaps & FW_CAPS_CONFIG_NIC_HASHFILTER) { 4255 MPASS(chip_id(sc) > CHELSIO_T4); 4256 MPASS(sc->toecaps == 0); 4257 sc->toecaps = 0; 4258 4259 param[0] = FW_PARAM_DEV(NTID); 4260 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 4261 if (rc != 0) { 4262 device_printf(sc->dev, 4263 "failed to query HASHFILTER parameters: %d.\n", rc); 4264 return (rc); 4265 } 4266 sc->tids.ntids = val[0]; 4267 if (sc->params.fw_vers < 4268 (V_FW_HDR_FW_VER_MAJOR(1) | V_FW_HDR_FW_VER_MINOR(20) | 4269 V_FW_HDR_FW_VER_MICRO(5) | V_FW_HDR_FW_VER_BUILD(0))) { 4270 MPASS(sc->tids.ntids >= sc->tids.nhpftids); 4271 sc->tids.ntids -= sc->tids.nhpftids; 4272 } 4273 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS); 4274 sc->params.hash_filter = 1; 4275 } 4276 if (sc->niccaps & FW_CAPS_CONFIG_NIC_ETHOFLD) { 4277 param[0] = FW_PARAM_PFVF(ETHOFLD_START); 4278 param[1] = FW_PARAM_PFVF(ETHOFLD_END); 4279 param[2] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); 4280 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 3, param, val); 4281 if (rc != 0) { 4282 device_printf(sc->dev, 4283 "failed to query NIC parameters: %d.\n", rc); 4284 return (rc); 4285 } 4286 if ((int)val[1] > (int)val[0]) { 4287 sc->tids.etid_base = val[0]; 4288 sc->tids.etid_end = val[1]; 4289 sc->tids.netids = val[1] - val[0] + 1; 4290 sc->params.eo_wr_cred = val[2]; 4291 sc->params.ethoffload = 1; 4292 } 4293 } 4294 if (sc->toecaps) { 4295 /* query offload-related parameters */ 4296 param[0] = FW_PARAM_DEV(NTID); 4297 param[1] = FW_PARAM_PFVF(SERVER_START); 4298 param[2] = FW_PARAM_PFVF(SERVER_END); 4299 param[3] = FW_PARAM_PFVF(TDDP_START); 4300 param[4] = FW_PARAM_PFVF(TDDP_END); 4301 param[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); 4302 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 4303 if (rc != 0) { 4304 device_printf(sc->dev, 4305 "failed to query TOE parameters: %d.\n", rc); 4306 return (rc); 4307 } 4308 sc->tids.ntids = val[0]; 4309 if (sc->params.fw_vers < 4310 (V_FW_HDR_FW_VER_MAJOR(1) | V_FW_HDR_FW_VER_MINOR(20) | 4311 V_FW_HDR_FW_VER_MICRO(5) | V_FW_HDR_FW_VER_BUILD(0))) { 4312 MPASS(sc->tids.ntids >= sc->tids.nhpftids); 4313 sc->tids.ntids -= sc->tids.nhpftids; 4314 } 4315 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS); 4316 if ((int)val[2] > (int)val[1]) { 4317 sc->tids.stid_base = val[1]; 4318 sc->tids.nstids = val[2] - val[1] + 1; 4319 } 4320 sc->vres.ddp.start = val[3]; 4321 sc->vres.ddp.size = val[4] - val[3] + 1; 4322 sc->params.ofldq_wr_cred = val[5]; 4323 sc->params.offload = 1; 4324 } else { 4325 /* 4326 * The firmware attempts memfree TOE configuration for -SO cards 4327 * and will report toecaps=0 if it runs out of resources (this 4328 * depends on the config file). It may not report 0 for other 4329 * capabilities dependent on the TOE in this case. Set them to 4330 * 0 here so that the driver doesn't bother tracking resources 4331 * that will never be used. 4332 */ 4333 sc->iscsicaps = 0; 4334 sc->rdmacaps = 0; 4335 } 4336 if (sc->rdmacaps) { 4337 param[0] = FW_PARAM_PFVF(STAG_START); 4338 param[1] = FW_PARAM_PFVF(STAG_END); 4339 param[2] = FW_PARAM_PFVF(RQ_START); 4340 param[3] = FW_PARAM_PFVF(RQ_END); 4341 param[4] = FW_PARAM_PFVF(PBL_START); 4342 param[5] = FW_PARAM_PFVF(PBL_END); 4343 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 4344 if (rc != 0) { 4345 device_printf(sc->dev, 4346 "failed to query RDMA parameters(1): %d.\n", rc); 4347 return (rc); 4348 } 4349 sc->vres.stag.start = val[0]; 4350 sc->vres.stag.size = val[1] - val[0] + 1; 4351 sc->vres.rq.start = val[2]; 4352 sc->vres.rq.size = val[3] - val[2] + 1; 4353 sc->vres.pbl.start = val[4]; 4354 sc->vres.pbl.size = val[5] - val[4] + 1; 4355 4356 param[0] = FW_PARAM_PFVF(SQRQ_START); 4357 param[1] = FW_PARAM_PFVF(SQRQ_END); 4358 param[2] = FW_PARAM_PFVF(CQ_START); 4359 param[3] = FW_PARAM_PFVF(CQ_END); 4360 param[4] = FW_PARAM_PFVF(OCQ_START); 4361 param[5] = FW_PARAM_PFVF(OCQ_END); 4362 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 4363 if (rc != 0) { 4364 device_printf(sc->dev, 4365 "failed to query RDMA parameters(2): %d.\n", rc); 4366 return (rc); 4367 } 4368 sc->vres.qp.start = val[0]; 4369 sc->vres.qp.size = val[1] - val[0] + 1; 4370 sc->vres.cq.start = val[2]; 4371 sc->vres.cq.size = val[3] - val[2] + 1; 4372 sc->vres.ocq.start = val[4]; 4373 sc->vres.ocq.size = val[5] - val[4] + 1; 4374 4375 param[0] = FW_PARAM_PFVF(SRQ_START); 4376 param[1] = FW_PARAM_PFVF(SRQ_END); 4377 param[2] = FW_PARAM_DEV(MAXORDIRD_QP); 4378 param[3] = FW_PARAM_DEV(MAXIRD_ADAPTER); 4379 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 4, param, val); 4380 if (rc != 0) { 4381 device_printf(sc->dev, 4382 "failed to query RDMA parameters(3): %d.\n", rc); 4383 return (rc); 4384 } 4385 sc->vres.srq.start = val[0]; 4386 sc->vres.srq.size = val[1] - val[0] + 1; 4387 sc->params.max_ordird_qp = val[2]; 4388 sc->params.max_ird_adapter = val[3]; 4389 } 4390 if (sc->iscsicaps) { 4391 param[0] = FW_PARAM_PFVF(ISCSI_START); 4392 param[1] = FW_PARAM_PFVF(ISCSI_END); 4393 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 4394 if (rc != 0) { 4395 device_printf(sc->dev, 4396 "failed to query iSCSI parameters: %d.\n", rc); 4397 return (rc); 4398 } 4399 sc->vres.iscsi.start = val[0]; 4400 sc->vres.iscsi.size = val[1] - val[0] + 1; 4401 } 4402 if (sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS) { 4403 param[0] = FW_PARAM_PFVF(TLS_START); 4404 param[1] = FW_PARAM_PFVF(TLS_END); 4405 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 4406 if (rc != 0) { 4407 device_printf(sc->dev, 4408 "failed to query TLS parameters: %d.\n", rc); 4409 return (rc); 4410 } 4411 sc->vres.key.start = val[0]; 4412 sc->vres.key.size = val[1] - val[0] + 1; 4413 } 4414 4415 t4_init_sge_params(sc); 4416 4417 /* 4418 * We've got the params we wanted to query via the firmware. Now grab 4419 * some others directly from the chip. 4420 */ 4421 rc = t4_read_chip_settings(sc); 4422 4423 return (rc); 4424 } 4425 4426 static int 4427 set_params__post_init(struct adapter *sc) 4428 { 4429 uint32_t param, val; 4430 #ifdef TCP_OFFLOAD 4431 int i, v, shift; 4432 #endif 4433 4434 /* ask for encapsulated CPLs */ 4435 param = FW_PARAM_PFVF(CPLFW4MSG_ENCAP); 4436 val = 1; 4437 (void)t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 4438 4439 /* Enable 32b port caps if the firmware supports it. */ 4440 param = FW_PARAM_PFVF(PORT_CAPS32); 4441 val = 1; 4442 if (t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val) == 0) 4443 sc->params.port_caps32 = 1; 4444 4445 /* Let filter + maskhash steer to a part of the VI's RSS region. */ 4446 val = 1 << (G_MASKSIZE(t4_read_reg(sc, A_TP_RSS_CONFIG_TNL)) - 1); 4447 t4_set_reg_field(sc, A_TP_RSS_CONFIG_TNL, V_MASKFILTER(M_MASKFILTER), 4448 V_MASKFILTER(val - 1)); 4449 4450 #ifdef TCP_OFFLOAD 4451 /* 4452 * Override the TOE timers with user provided tunables. This is not the 4453 * recommended way to change the timers (the firmware config file is) so 4454 * these tunables are not documented. 4455 * 4456 * All the timer tunables are in microseconds. 4457 */ 4458 if (t4_toe_keepalive_idle != 0) { 4459 v = us_to_tcp_ticks(sc, t4_toe_keepalive_idle); 4460 v &= M_KEEPALIVEIDLE; 4461 t4_set_reg_field(sc, A_TP_KEEP_IDLE, 4462 V_KEEPALIVEIDLE(M_KEEPALIVEIDLE), V_KEEPALIVEIDLE(v)); 4463 } 4464 if (t4_toe_keepalive_interval != 0) { 4465 v = us_to_tcp_ticks(sc, t4_toe_keepalive_interval); 4466 v &= M_KEEPALIVEINTVL; 4467 t4_set_reg_field(sc, A_TP_KEEP_INTVL, 4468 V_KEEPALIVEINTVL(M_KEEPALIVEINTVL), V_KEEPALIVEINTVL(v)); 4469 } 4470 if (t4_toe_keepalive_count != 0) { 4471 v = t4_toe_keepalive_count & M_KEEPALIVEMAXR2; 4472 t4_set_reg_field(sc, A_TP_SHIFT_CNT, 4473 V_KEEPALIVEMAXR1(M_KEEPALIVEMAXR1) | 4474 V_KEEPALIVEMAXR2(M_KEEPALIVEMAXR2), 4475 V_KEEPALIVEMAXR1(1) | V_KEEPALIVEMAXR2(v)); 4476 } 4477 if (t4_toe_rexmt_min != 0) { 4478 v = us_to_tcp_ticks(sc, t4_toe_rexmt_min); 4479 v &= M_RXTMIN; 4480 t4_set_reg_field(sc, A_TP_RXT_MIN, 4481 V_RXTMIN(M_RXTMIN), V_RXTMIN(v)); 4482 } 4483 if (t4_toe_rexmt_max != 0) { 4484 v = us_to_tcp_ticks(sc, t4_toe_rexmt_max); 4485 v &= M_RXTMAX; 4486 t4_set_reg_field(sc, A_TP_RXT_MAX, 4487 V_RXTMAX(M_RXTMAX), V_RXTMAX(v)); 4488 } 4489 if (t4_toe_rexmt_count != 0) { 4490 v = t4_toe_rexmt_count & M_RXTSHIFTMAXR2; 4491 t4_set_reg_field(sc, A_TP_SHIFT_CNT, 4492 V_RXTSHIFTMAXR1(M_RXTSHIFTMAXR1) | 4493 V_RXTSHIFTMAXR2(M_RXTSHIFTMAXR2), 4494 V_RXTSHIFTMAXR1(1) | V_RXTSHIFTMAXR2(v)); 4495 } 4496 for (i = 0; i < nitems(t4_toe_rexmt_backoff); i++) { 4497 if (t4_toe_rexmt_backoff[i] != -1) { 4498 v = t4_toe_rexmt_backoff[i] & M_TIMERBACKOFFINDEX0; 4499 shift = (i & 3) << 3; 4500 t4_set_reg_field(sc, A_TP_TCP_BACKOFF_REG0 + (i & ~3), 4501 M_TIMERBACKOFFINDEX0 << shift, v << shift); 4502 } 4503 } 4504 #endif 4505 return (0); 4506 } 4507 4508 #undef FW_PARAM_PFVF 4509 #undef FW_PARAM_DEV 4510 4511 static void 4512 t4_set_desc(struct adapter *sc) 4513 { 4514 char buf[128]; 4515 struct adapter_params *p = &sc->params; 4516 4517 snprintf(buf, sizeof(buf), "Chelsio %s", p->vpd.id); 4518 4519 device_set_desc_copy(sc->dev, buf); 4520 } 4521 4522 static inline void 4523 ifmedia_add4(struct ifmedia *ifm, int m) 4524 { 4525 4526 ifmedia_add(ifm, m, 0, NULL); 4527 ifmedia_add(ifm, m | IFM_ETH_TXPAUSE, 0, NULL); 4528 ifmedia_add(ifm, m | IFM_ETH_RXPAUSE, 0, NULL); 4529 ifmedia_add(ifm, m | IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE, 0, NULL); 4530 } 4531 4532 /* 4533 * This is the selected media, which is not quite the same as the active media. 4534 * The media line in ifconfig is "media: Ethernet selected (active)" if selected 4535 * and active are not the same, and "media: Ethernet selected" otherwise. 4536 */ 4537 static void 4538 set_current_media(struct port_info *pi) 4539 { 4540 struct link_config *lc; 4541 struct ifmedia *ifm; 4542 int mword; 4543 u_int speed; 4544 4545 PORT_LOCK_ASSERT_OWNED(pi); 4546 4547 /* Leave current media alone if it's already set to IFM_NONE. */ 4548 ifm = &pi->media; 4549 if (ifm->ifm_cur != NULL && 4550 IFM_SUBTYPE(ifm->ifm_cur->ifm_media) == IFM_NONE) 4551 return; 4552 4553 lc = &pi->link_cfg; 4554 if (lc->requested_aneg != AUTONEG_DISABLE && 4555 lc->supported & FW_PORT_CAP32_ANEG) { 4556 ifmedia_set(ifm, IFM_ETHER | IFM_AUTO); 4557 return; 4558 } 4559 mword = IFM_ETHER | IFM_FDX; 4560 if (lc->requested_fc & PAUSE_TX) 4561 mword |= IFM_ETH_TXPAUSE; 4562 if (lc->requested_fc & PAUSE_RX) 4563 mword |= IFM_ETH_RXPAUSE; 4564 if (lc->requested_speed == 0) 4565 speed = port_top_speed(pi) * 1000; /* Gbps -> Mbps */ 4566 else 4567 speed = lc->requested_speed; 4568 mword |= port_mword(pi, speed_to_fwcap(speed)); 4569 ifmedia_set(ifm, mword); 4570 } 4571 4572 /* 4573 * Returns true if the ifmedia list for the port cannot change. 4574 */ 4575 static bool 4576 fixed_ifmedia(struct port_info *pi) 4577 { 4578 4579 return (pi->port_type == FW_PORT_TYPE_BT_SGMII || 4580 pi->port_type == FW_PORT_TYPE_BT_XFI || 4581 pi->port_type == FW_PORT_TYPE_BT_XAUI || 4582 pi->port_type == FW_PORT_TYPE_KX4 || 4583 pi->port_type == FW_PORT_TYPE_KX || 4584 pi->port_type == FW_PORT_TYPE_KR || 4585 pi->port_type == FW_PORT_TYPE_BP_AP || 4586 pi->port_type == FW_PORT_TYPE_BP4_AP || 4587 pi->port_type == FW_PORT_TYPE_BP40_BA || 4588 pi->port_type == FW_PORT_TYPE_KR4_100G || 4589 pi->port_type == FW_PORT_TYPE_KR_SFP28 || 4590 pi->port_type == FW_PORT_TYPE_KR_XLAUI); 4591 } 4592 4593 static void 4594 build_medialist(struct port_info *pi) 4595 { 4596 uint32_t ss, speed; 4597 int unknown, mword, bit; 4598 struct link_config *lc; 4599 struct ifmedia *ifm; 4600 4601 PORT_LOCK_ASSERT_OWNED(pi); 4602 4603 if (pi->flags & FIXED_IFMEDIA) 4604 return; 4605 4606 /* 4607 * Rebuild the ifmedia list. 4608 */ 4609 ifm = &pi->media; 4610 ifmedia_removeall(ifm); 4611 lc = &pi->link_cfg; 4612 ss = G_FW_PORT_CAP32_SPEED(lc->supported); /* Supported Speeds */ 4613 if (__predict_false(ss == 0)) { /* not supposed to happen. */ 4614 MPASS(ss != 0); 4615 no_media: 4616 MPASS(LIST_EMPTY(&ifm->ifm_list)); 4617 ifmedia_add(ifm, IFM_ETHER | IFM_NONE, 0, NULL); 4618 ifmedia_set(ifm, IFM_ETHER | IFM_NONE); 4619 return; 4620 } 4621 4622 unknown = 0; 4623 for (bit = S_FW_PORT_CAP32_SPEED; bit < fls(ss); bit++) { 4624 speed = 1 << bit; 4625 MPASS(speed & M_FW_PORT_CAP32_SPEED); 4626 if (ss & speed) { 4627 mword = port_mword(pi, speed); 4628 if (mword == IFM_NONE) { 4629 goto no_media; 4630 } else if (mword == IFM_UNKNOWN) 4631 unknown++; 4632 else 4633 ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | mword); 4634 } 4635 } 4636 if (unknown > 0) /* Add one unknown for all unknown media types. */ 4637 ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | IFM_UNKNOWN); 4638 if (lc->supported & FW_PORT_CAP32_ANEG) 4639 ifmedia_add(ifm, IFM_ETHER | IFM_AUTO, 0, NULL); 4640 4641 set_current_media(pi); 4642 } 4643 4644 /* 4645 * Initialize the requested fields in the link config based on driver tunables. 4646 */ 4647 static void 4648 init_link_config(struct port_info *pi) 4649 { 4650 struct link_config *lc = &pi->link_cfg; 4651 4652 PORT_LOCK_ASSERT_OWNED(pi); 4653 4654 lc->requested_speed = 0; 4655 4656 if (t4_autoneg == 0) 4657 lc->requested_aneg = AUTONEG_DISABLE; 4658 else if (t4_autoneg == 1) 4659 lc->requested_aneg = AUTONEG_ENABLE; 4660 else 4661 lc->requested_aneg = AUTONEG_AUTO; 4662 4663 lc->requested_fc = t4_pause_settings & (PAUSE_TX | PAUSE_RX | 4664 PAUSE_AUTONEG); 4665 4666 if (t4_fec == -1 || t4_fec & FEC_AUTO) 4667 lc->requested_fec = FEC_AUTO; 4668 else { 4669 lc->requested_fec = FEC_NONE; 4670 if (t4_fec & FEC_RS) 4671 lc->requested_fec |= FEC_RS; 4672 if (t4_fec & FEC_BASER_RS) 4673 lc->requested_fec |= FEC_BASER_RS; 4674 } 4675 } 4676 4677 /* 4678 * Makes sure that all requested settings comply with what's supported by the 4679 * port. Returns the number of settings that were invalid and had to be fixed. 4680 */ 4681 static int 4682 fixup_link_config(struct port_info *pi) 4683 { 4684 int n = 0; 4685 struct link_config *lc = &pi->link_cfg; 4686 uint32_t fwspeed; 4687 4688 PORT_LOCK_ASSERT_OWNED(pi); 4689 4690 /* Speed (when not autonegotiating) */ 4691 if (lc->requested_speed != 0) { 4692 fwspeed = speed_to_fwcap(lc->requested_speed); 4693 if ((fwspeed & lc->supported) == 0) { 4694 n++; 4695 lc->requested_speed = 0; 4696 } 4697 } 4698 4699 /* Link autonegotiation */ 4700 MPASS(lc->requested_aneg == AUTONEG_ENABLE || 4701 lc->requested_aneg == AUTONEG_DISABLE || 4702 lc->requested_aneg == AUTONEG_AUTO); 4703 if (lc->requested_aneg == AUTONEG_ENABLE && 4704 !(lc->supported & FW_PORT_CAP32_ANEG)) { 4705 n++; 4706 lc->requested_aneg = AUTONEG_AUTO; 4707 } 4708 4709 /* Flow control */ 4710 MPASS((lc->requested_fc & ~(PAUSE_TX | PAUSE_RX | PAUSE_AUTONEG)) == 0); 4711 if (lc->requested_fc & PAUSE_TX && 4712 !(lc->supported & FW_PORT_CAP32_FC_TX)) { 4713 n++; 4714 lc->requested_fc &= ~PAUSE_TX; 4715 } 4716 if (lc->requested_fc & PAUSE_RX && 4717 !(lc->supported & FW_PORT_CAP32_FC_RX)) { 4718 n++; 4719 lc->requested_fc &= ~PAUSE_RX; 4720 } 4721 if (!(lc->requested_fc & PAUSE_AUTONEG) && 4722 !(lc->supported & FW_PORT_CAP32_FORCE_PAUSE)) { 4723 n++; 4724 lc->requested_fc |= PAUSE_AUTONEG; 4725 } 4726 4727 /* FEC */ 4728 if ((lc->requested_fec & FEC_RS && 4729 !(lc->supported & FW_PORT_CAP32_FEC_RS)) || 4730 (lc->requested_fec & FEC_BASER_RS && 4731 !(lc->supported & FW_PORT_CAP32_FEC_BASER_RS))) { 4732 n++; 4733 lc->requested_fec = FEC_AUTO; 4734 } 4735 4736 return (n); 4737 } 4738 4739 /* 4740 * Apply the requested L1 settings, which are expected to be valid, to the 4741 * hardware. 4742 */ 4743 static int 4744 apply_link_config(struct port_info *pi) 4745 { 4746 struct adapter *sc = pi->adapter; 4747 struct link_config *lc = &pi->link_cfg; 4748 int rc; 4749 4750 #ifdef INVARIANTS 4751 ASSERT_SYNCHRONIZED_OP(sc); 4752 PORT_LOCK_ASSERT_OWNED(pi); 4753 4754 if (lc->requested_aneg == AUTONEG_ENABLE) 4755 MPASS(lc->supported & FW_PORT_CAP32_ANEG); 4756 if (!(lc->requested_fc & PAUSE_AUTONEG)) 4757 MPASS(lc->supported & FW_PORT_CAP32_FORCE_PAUSE); 4758 if (lc->requested_fc & PAUSE_TX) 4759 MPASS(lc->supported & FW_PORT_CAP32_FC_TX); 4760 if (lc->requested_fc & PAUSE_RX) 4761 MPASS(lc->supported & FW_PORT_CAP32_FC_RX); 4762 if (lc->requested_fec & FEC_RS) 4763 MPASS(lc->supported & FW_PORT_CAP32_FEC_RS); 4764 if (lc->requested_fec & FEC_BASER_RS) 4765 MPASS(lc->supported & FW_PORT_CAP32_FEC_BASER_RS); 4766 #endif 4767 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc); 4768 if (rc != 0) { 4769 /* Don't complain if the VF driver gets back an EPERM. */ 4770 if (!(sc->flags & IS_VF) || rc != FW_EPERM) 4771 device_printf(pi->dev, "l1cfg failed: %d\n", rc); 4772 } else { 4773 /* 4774 * An L1_CFG will almost always result in a link-change event if 4775 * the link is up, and the driver will refresh the actual 4776 * fec/fc/etc. when the notification is processed. If the link 4777 * is down then the actual settings are meaningless. 4778 * 4779 * This takes care of the case where a change in the L1 settings 4780 * may not result in a notification. 4781 */ 4782 if (lc->link_ok && !(lc->requested_fc & PAUSE_AUTONEG)) 4783 lc->fc = lc->requested_fc & (PAUSE_TX | PAUSE_RX); 4784 } 4785 return (rc); 4786 } 4787 4788 #define FW_MAC_EXACT_CHUNK 7 4789 4790 /* 4791 * Program the port's XGMAC based on parameters in ifnet. The caller also 4792 * indicates which parameters should be programmed (the rest are left alone). 4793 */ 4794 int 4795 update_mac_settings(struct ifnet *ifp, int flags) 4796 { 4797 int rc = 0; 4798 struct vi_info *vi = ifp->if_softc; 4799 struct port_info *pi = vi->pi; 4800 struct adapter *sc = pi->adapter; 4801 int mtu = -1, promisc = -1, allmulti = -1, vlanex = -1; 4802 4803 ASSERT_SYNCHRONIZED_OP(sc); 4804 KASSERT(flags, ("%s: not told what to update.", __func__)); 4805 4806 if (flags & XGMAC_MTU) 4807 mtu = ifp->if_mtu; 4808 4809 if (flags & XGMAC_PROMISC) 4810 promisc = ifp->if_flags & IFF_PROMISC ? 1 : 0; 4811 4812 if (flags & XGMAC_ALLMULTI) 4813 allmulti = ifp->if_flags & IFF_ALLMULTI ? 1 : 0; 4814 4815 if (flags & XGMAC_VLANEX) 4816 vlanex = ifp->if_capenable & IFCAP_VLAN_HWTAGGING ? 1 : 0; 4817 4818 if (flags & (XGMAC_MTU|XGMAC_PROMISC|XGMAC_ALLMULTI|XGMAC_VLANEX)) { 4819 rc = -t4_set_rxmode(sc, sc->mbox, vi->viid, mtu, promisc, 4820 allmulti, 1, vlanex, false); 4821 if (rc) { 4822 if_printf(ifp, "set_rxmode (%x) failed: %d\n", flags, 4823 rc); 4824 return (rc); 4825 } 4826 } 4827 4828 if (flags & XGMAC_UCADDR) { 4829 uint8_t ucaddr[ETHER_ADDR_LEN]; 4830 4831 bcopy(IF_LLADDR(ifp), ucaddr, sizeof(ucaddr)); 4832 rc = t4_change_mac(sc, sc->mbox, vi->viid, vi->xact_addr_filt, 4833 ucaddr, true, &vi->smt_idx); 4834 if (rc < 0) { 4835 rc = -rc; 4836 if_printf(ifp, "change_mac failed: %d\n", rc); 4837 return (rc); 4838 } else { 4839 vi->xact_addr_filt = rc; 4840 rc = 0; 4841 } 4842 } 4843 4844 if (flags & XGMAC_MCADDRS) { 4845 const uint8_t *mcaddr[FW_MAC_EXACT_CHUNK]; 4846 int del = 1; 4847 uint64_t hash = 0; 4848 struct ifmultiaddr *ifma; 4849 int i = 0, j; 4850 4851 if_maddr_rlock(ifp); 4852 CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 4853 if (ifma->ifma_addr->sa_family != AF_LINK) 4854 continue; 4855 mcaddr[i] = 4856 LLADDR((struct sockaddr_dl *)ifma->ifma_addr); 4857 MPASS(ETHER_IS_MULTICAST(mcaddr[i])); 4858 i++; 4859 4860 if (i == FW_MAC_EXACT_CHUNK) { 4861 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, 4862 del, i, mcaddr, NULL, &hash, 0); 4863 if (rc < 0) { 4864 rc = -rc; 4865 for (j = 0; j < i; j++) { 4866 if_printf(ifp, 4867 "failed to add mc address" 4868 " %02x:%02x:%02x:" 4869 "%02x:%02x:%02x rc=%d\n", 4870 mcaddr[j][0], mcaddr[j][1], 4871 mcaddr[j][2], mcaddr[j][3], 4872 mcaddr[j][4], mcaddr[j][5], 4873 rc); 4874 } 4875 goto mcfail; 4876 } 4877 del = 0; 4878 i = 0; 4879 } 4880 } 4881 if (i > 0) { 4882 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, del, i, 4883 mcaddr, NULL, &hash, 0); 4884 if (rc < 0) { 4885 rc = -rc; 4886 for (j = 0; j < i; j++) { 4887 if_printf(ifp, 4888 "failed to add mc address" 4889 " %02x:%02x:%02x:" 4890 "%02x:%02x:%02x rc=%d\n", 4891 mcaddr[j][0], mcaddr[j][1], 4892 mcaddr[j][2], mcaddr[j][3], 4893 mcaddr[j][4], mcaddr[j][5], 4894 rc); 4895 } 4896 goto mcfail; 4897 } 4898 } 4899 4900 rc = -t4_set_addr_hash(sc, sc->mbox, vi->viid, 0, hash, 0); 4901 if (rc != 0) 4902 if_printf(ifp, "failed to set mc address hash: %d", rc); 4903 mcfail: 4904 if_maddr_runlock(ifp); 4905 } 4906 4907 return (rc); 4908 } 4909 4910 /* 4911 * {begin|end}_synchronized_op must be called from the same thread. 4912 */ 4913 int 4914 begin_synchronized_op(struct adapter *sc, struct vi_info *vi, int flags, 4915 char *wmesg) 4916 { 4917 int rc, pri; 4918 4919 #ifdef WITNESS 4920 /* the caller thinks it's ok to sleep, but is it really? */ 4921 if (flags & SLEEP_OK) 4922 WITNESS_WARN(WARN_GIANTOK | WARN_SLEEPOK, NULL, 4923 "begin_synchronized_op"); 4924 #endif 4925 4926 if (INTR_OK) 4927 pri = PCATCH; 4928 else 4929 pri = 0; 4930 4931 ADAPTER_LOCK(sc); 4932 for (;;) { 4933 4934 if (vi && IS_DOOMED(vi)) { 4935 rc = ENXIO; 4936 goto done; 4937 } 4938 4939 if (!IS_BUSY(sc)) { 4940 rc = 0; 4941 break; 4942 } 4943 4944 if (!(flags & SLEEP_OK)) { 4945 rc = EBUSY; 4946 goto done; 4947 } 4948 4949 if (mtx_sleep(&sc->flags, &sc->sc_lock, pri, wmesg, 0)) { 4950 rc = EINTR; 4951 goto done; 4952 } 4953 } 4954 4955 KASSERT(!IS_BUSY(sc), ("%s: controller busy.", __func__)); 4956 SET_BUSY(sc); 4957 #ifdef INVARIANTS 4958 sc->last_op = wmesg; 4959 sc->last_op_thr = curthread; 4960 sc->last_op_flags = flags; 4961 #endif 4962 4963 done: 4964 if (!(flags & HOLD_LOCK) || rc) 4965 ADAPTER_UNLOCK(sc); 4966 4967 return (rc); 4968 } 4969 4970 /* 4971 * Tell if_ioctl and if_init that the VI is going away. This is 4972 * special variant of begin_synchronized_op and must be paired with a 4973 * call to end_synchronized_op. 4974 */ 4975 void 4976 doom_vi(struct adapter *sc, struct vi_info *vi) 4977 { 4978 4979 ADAPTER_LOCK(sc); 4980 SET_DOOMED(vi); 4981 wakeup(&sc->flags); 4982 while (IS_BUSY(sc)) 4983 mtx_sleep(&sc->flags, &sc->sc_lock, 0, "t4detach", 0); 4984 SET_BUSY(sc); 4985 #ifdef INVARIANTS 4986 sc->last_op = "t4detach"; 4987 sc->last_op_thr = curthread; 4988 sc->last_op_flags = 0; 4989 #endif 4990 ADAPTER_UNLOCK(sc); 4991 } 4992 4993 /* 4994 * {begin|end}_synchronized_op must be called from the same thread. 4995 */ 4996 void 4997 end_synchronized_op(struct adapter *sc, int flags) 4998 { 4999 5000 if (flags & LOCK_HELD) 5001 ADAPTER_LOCK_ASSERT_OWNED(sc); 5002 else 5003 ADAPTER_LOCK(sc); 5004 5005 KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__)); 5006 CLR_BUSY(sc); 5007 wakeup(&sc->flags); 5008 ADAPTER_UNLOCK(sc); 5009 } 5010 5011 static int 5012 cxgbe_init_synchronized(struct vi_info *vi) 5013 { 5014 struct port_info *pi = vi->pi; 5015 struct adapter *sc = pi->adapter; 5016 struct ifnet *ifp = vi->ifp; 5017 int rc = 0, i; 5018 struct sge_txq *txq; 5019 5020 ASSERT_SYNCHRONIZED_OP(sc); 5021 5022 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 5023 return (0); /* already running */ 5024 5025 if (!(sc->flags & FULL_INIT_DONE) && 5026 ((rc = adapter_full_init(sc)) != 0)) 5027 return (rc); /* error message displayed already */ 5028 5029 if (!(vi->flags & VI_INIT_DONE) && 5030 ((rc = vi_full_init(vi)) != 0)) 5031 return (rc); /* error message displayed already */ 5032 5033 rc = update_mac_settings(ifp, XGMAC_ALL); 5034 if (rc) 5035 goto done; /* error message displayed already */ 5036 5037 PORT_LOCK(pi); 5038 if (pi->up_vis == 0) { 5039 t4_update_port_info(pi); 5040 fixup_link_config(pi); 5041 build_medialist(pi); 5042 apply_link_config(pi); 5043 } 5044 5045 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, true, true); 5046 if (rc != 0) { 5047 if_printf(ifp, "enable_vi failed: %d\n", rc); 5048 PORT_UNLOCK(pi); 5049 goto done; 5050 } 5051 5052 /* 5053 * Can't fail from this point onwards. Review cxgbe_uninit_synchronized 5054 * if this changes. 5055 */ 5056 5057 for_each_txq(vi, i, txq) { 5058 TXQ_LOCK(txq); 5059 txq->eq.flags |= EQ_ENABLED; 5060 TXQ_UNLOCK(txq); 5061 } 5062 5063 /* 5064 * The first iq of the first port to come up is used for tracing. 5065 */ 5066 if (sc->traceq < 0 && IS_MAIN_VI(vi)) { 5067 sc->traceq = sc->sge.rxq[vi->first_rxq].iq.abs_id; 5068 t4_write_reg(sc, is_t4(sc) ? A_MPS_TRC_RSS_CONTROL : 5069 A_MPS_T5_TRC_RSS_CONTROL, V_RSSCONTROL(pi->tx_chan) | 5070 V_QUEUENUMBER(sc->traceq)); 5071 pi->flags |= HAS_TRACEQ; 5072 } 5073 5074 /* all ok */ 5075 pi->up_vis++; 5076 ifp->if_drv_flags |= IFF_DRV_RUNNING; 5077 5078 if (pi->nvi > 1 || sc->flags & IS_VF) 5079 callout_reset(&vi->tick, hz, vi_tick, vi); 5080 else 5081 callout_reset(&pi->tick, hz, cxgbe_tick, pi); 5082 if (pi->link_cfg.link_ok) 5083 t4_os_link_changed(pi); 5084 PORT_UNLOCK(pi); 5085 done: 5086 if (rc != 0) 5087 cxgbe_uninit_synchronized(vi); 5088 5089 return (rc); 5090 } 5091 5092 /* 5093 * Idempotent. 5094 */ 5095 static int 5096 cxgbe_uninit_synchronized(struct vi_info *vi) 5097 { 5098 struct port_info *pi = vi->pi; 5099 struct adapter *sc = pi->adapter; 5100 struct ifnet *ifp = vi->ifp; 5101 int rc, i; 5102 struct sge_txq *txq; 5103 5104 ASSERT_SYNCHRONIZED_OP(sc); 5105 5106 if (!(vi->flags & VI_INIT_DONE)) { 5107 if (__predict_false(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 5108 KASSERT(0, ("uninited VI is running")); 5109 if_printf(ifp, "uninited VI with running ifnet. " 5110 "vi->flags 0x%016lx, if_flags 0x%08x, " 5111 "if_drv_flags 0x%08x\n", vi->flags, ifp->if_flags, 5112 ifp->if_drv_flags); 5113 } 5114 return (0); 5115 } 5116 5117 /* 5118 * Disable the VI so that all its data in either direction is discarded 5119 * by the MPS. Leave everything else (the queues, interrupts, and 1Hz 5120 * tick) intact as the TP can deliver negative advice or data that it's 5121 * holding in its RAM (for an offloaded connection) even after the VI is 5122 * disabled. 5123 */ 5124 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, false, false); 5125 if (rc) { 5126 if_printf(ifp, "disable_vi failed: %d\n", rc); 5127 return (rc); 5128 } 5129 5130 for_each_txq(vi, i, txq) { 5131 TXQ_LOCK(txq); 5132 txq->eq.flags &= ~EQ_ENABLED; 5133 TXQ_UNLOCK(txq); 5134 } 5135 5136 PORT_LOCK(pi); 5137 if (pi->nvi > 1 || sc->flags & IS_VF) 5138 callout_stop(&vi->tick); 5139 else 5140 callout_stop(&pi->tick); 5141 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 5142 PORT_UNLOCK(pi); 5143 return (0); 5144 } 5145 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 5146 pi->up_vis--; 5147 if (pi->up_vis > 0) { 5148 PORT_UNLOCK(pi); 5149 return (0); 5150 } 5151 5152 pi->link_cfg.link_ok = false; 5153 pi->link_cfg.speed = 0; 5154 pi->link_cfg.link_down_rc = 255; 5155 t4_os_link_changed(pi); 5156 PORT_UNLOCK(pi); 5157 5158 return (0); 5159 } 5160 5161 /* 5162 * It is ok for this function to fail midway and return right away. t4_detach 5163 * will walk the entire sc->irq list and clean up whatever is valid. 5164 */ 5165 int 5166 t4_setup_intr_handlers(struct adapter *sc) 5167 { 5168 int rc, rid, p, q, v; 5169 char s[8]; 5170 struct irq *irq; 5171 struct port_info *pi; 5172 struct vi_info *vi; 5173 struct sge *sge = &sc->sge; 5174 struct sge_rxq *rxq; 5175 #ifdef TCP_OFFLOAD 5176 struct sge_ofld_rxq *ofld_rxq; 5177 #endif 5178 #ifdef DEV_NETMAP 5179 struct sge_nm_rxq *nm_rxq; 5180 #endif 5181 #ifdef RSS 5182 int nbuckets = rss_getnumbuckets(); 5183 #endif 5184 5185 /* 5186 * Setup interrupts. 5187 */ 5188 irq = &sc->irq[0]; 5189 rid = sc->intr_type == INTR_INTX ? 0 : 1; 5190 if (forwarding_intr_to_fwq(sc)) 5191 return (t4_alloc_irq(sc, irq, rid, t4_intr_all, sc, "all")); 5192 5193 /* Multiple interrupts. */ 5194 if (sc->flags & IS_VF) 5195 KASSERT(sc->intr_count >= T4VF_EXTRA_INTR + sc->params.nports, 5196 ("%s: too few intr.", __func__)); 5197 else 5198 KASSERT(sc->intr_count >= T4_EXTRA_INTR + sc->params.nports, 5199 ("%s: too few intr.", __func__)); 5200 5201 /* The first one is always error intr on PFs */ 5202 if (!(sc->flags & IS_VF)) { 5203 rc = t4_alloc_irq(sc, irq, rid, t4_intr_err, sc, "err"); 5204 if (rc != 0) 5205 return (rc); 5206 irq++; 5207 rid++; 5208 } 5209 5210 /* The second one is always the firmware event queue (first on VFs) */ 5211 rc = t4_alloc_irq(sc, irq, rid, t4_intr_evt, &sge->fwq, "evt"); 5212 if (rc != 0) 5213 return (rc); 5214 irq++; 5215 rid++; 5216 5217 for_each_port(sc, p) { 5218 pi = sc->port[p]; 5219 for_each_vi(pi, v, vi) { 5220 vi->first_intr = rid - 1; 5221 5222 if (vi->nnmrxq > 0) { 5223 int n = max(vi->nrxq, vi->nnmrxq); 5224 5225 rxq = &sge->rxq[vi->first_rxq]; 5226 #ifdef DEV_NETMAP 5227 nm_rxq = &sge->nm_rxq[vi->first_nm_rxq]; 5228 #endif 5229 for (q = 0; q < n; q++) { 5230 snprintf(s, sizeof(s), "%x%c%x", p, 5231 'a' + v, q); 5232 if (q < vi->nrxq) 5233 irq->rxq = rxq++; 5234 #ifdef DEV_NETMAP 5235 if (q < vi->nnmrxq) 5236 irq->nm_rxq = nm_rxq++; 5237 5238 if (irq->nm_rxq != NULL && 5239 irq->rxq == NULL) { 5240 /* Netmap rx only */ 5241 rc = t4_alloc_irq(sc, irq, rid, 5242 t4_nm_intr, irq->nm_rxq, s); 5243 } 5244 if (irq->nm_rxq != NULL && 5245 irq->rxq != NULL) { 5246 /* NIC and Netmap rx */ 5247 rc = t4_alloc_irq(sc, irq, rid, 5248 t4_vi_intr, irq, s); 5249 } 5250 #endif 5251 if (irq->rxq != NULL && 5252 irq->nm_rxq == NULL) { 5253 /* NIC rx only */ 5254 rc = t4_alloc_irq(sc, irq, rid, 5255 t4_intr, irq->rxq, s); 5256 } 5257 if (rc != 0) 5258 return (rc); 5259 #ifdef RSS 5260 if (q < vi->nrxq) { 5261 bus_bind_intr(sc->dev, irq->res, 5262 rss_getcpu(q % nbuckets)); 5263 } 5264 #endif 5265 irq++; 5266 rid++; 5267 vi->nintr++; 5268 } 5269 } else { 5270 for_each_rxq(vi, q, rxq) { 5271 snprintf(s, sizeof(s), "%x%c%x", p, 5272 'a' + v, q); 5273 rc = t4_alloc_irq(sc, irq, rid, 5274 t4_intr, rxq, s); 5275 if (rc != 0) 5276 return (rc); 5277 #ifdef RSS 5278 bus_bind_intr(sc->dev, irq->res, 5279 rss_getcpu(q % nbuckets)); 5280 #endif 5281 irq++; 5282 rid++; 5283 vi->nintr++; 5284 } 5285 } 5286 #ifdef TCP_OFFLOAD 5287 for_each_ofld_rxq(vi, q, ofld_rxq) { 5288 snprintf(s, sizeof(s), "%x%c%x", p, 'A' + v, q); 5289 rc = t4_alloc_irq(sc, irq, rid, t4_intr, 5290 ofld_rxq, s); 5291 if (rc != 0) 5292 return (rc); 5293 irq++; 5294 rid++; 5295 vi->nintr++; 5296 } 5297 #endif 5298 } 5299 } 5300 MPASS(irq == &sc->irq[sc->intr_count]); 5301 5302 return (0); 5303 } 5304 5305 int 5306 adapter_full_init(struct adapter *sc) 5307 { 5308 int rc, i; 5309 #ifdef RSS 5310 uint32_t raw_rss_key[RSS_KEYSIZE / sizeof(uint32_t)]; 5311 uint32_t rss_key[RSS_KEYSIZE / sizeof(uint32_t)]; 5312 #endif 5313 5314 ASSERT_SYNCHRONIZED_OP(sc); 5315 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 5316 KASSERT((sc->flags & FULL_INIT_DONE) == 0, 5317 ("%s: FULL_INIT_DONE already", __func__)); 5318 5319 /* 5320 * queues that belong to the adapter (not any particular port). 5321 */ 5322 rc = t4_setup_adapter_queues(sc); 5323 if (rc != 0) 5324 goto done; 5325 5326 for (i = 0; i < nitems(sc->tq); i++) { 5327 sc->tq[i] = taskqueue_create("t4 taskq", M_NOWAIT, 5328 taskqueue_thread_enqueue, &sc->tq[i]); 5329 if (sc->tq[i] == NULL) { 5330 device_printf(sc->dev, 5331 "failed to allocate task queue %d\n", i); 5332 rc = ENOMEM; 5333 goto done; 5334 } 5335 taskqueue_start_threads(&sc->tq[i], 1, PI_NET, "%s tq%d", 5336 device_get_nameunit(sc->dev), i); 5337 } 5338 #ifdef RSS 5339 MPASS(RSS_KEYSIZE == 40); 5340 rss_getkey((void *)&raw_rss_key[0]); 5341 for (i = 0; i < nitems(rss_key); i++) { 5342 rss_key[i] = htobe32(raw_rss_key[nitems(rss_key) - 1 - i]); 5343 } 5344 t4_write_rss_key(sc, &rss_key[0], -1, 1); 5345 #endif 5346 5347 if (!(sc->flags & IS_VF)) 5348 t4_intr_enable(sc); 5349 sc->flags |= FULL_INIT_DONE; 5350 done: 5351 if (rc != 0) 5352 adapter_full_uninit(sc); 5353 5354 return (rc); 5355 } 5356 5357 int 5358 adapter_full_uninit(struct adapter *sc) 5359 { 5360 int i; 5361 5362 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 5363 5364 t4_teardown_adapter_queues(sc); 5365 5366 for (i = 0; i < nitems(sc->tq) && sc->tq[i]; i++) { 5367 taskqueue_free(sc->tq[i]); 5368 sc->tq[i] = NULL; 5369 } 5370 5371 sc->flags &= ~FULL_INIT_DONE; 5372 5373 return (0); 5374 } 5375 5376 #ifdef RSS 5377 #define SUPPORTED_RSS_HASHTYPES (RSS_HASHTYPE_RSS_IPV4 | \ 5378 RSS_HASHTYPE_RSS_TCP_IPV4 | RSS_HASHTYPE_RSS_IPV6 | \ 5379 RSS_HASHTYPE_RSS_TCP_IPV6 | RSS_HASHTYPE_RSS_UDP_IPV4 | \ 5380 RSS_HASHTYPE_RSS_UDP_IPV6) 5381 5382 /* Translates kernel hash types to hardware. */ 5383 static int 5384 hashconfig_to_hashen(int hashconfig) 5385 { 5386 int hashen = 0; 5387 5388 if (hashconfig & RSS_HASHTYPE_RSS_IPV4) 5389 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN; 5390 if (hashconfig & RSS_HASHTYPE_RSS_IPV6) 5391 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN; 5392 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV4) { 5393 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN | 5394 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN; 5395 } 5396 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV6) { 5397 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN | 5398 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN; 5399 } 5400 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV4) 5401 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN; 5402 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV6) 5403 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN; 5404 5405 return (hashen); 5406 } 5407 5408 /* Translates hardware hash types to kernel. */ 5409 static int 5410 hashen_to_hashconfig(int hashen) 5411 { 5412 int hashconfig = 0; 5413 5414 if (hashen & F_FW_RSS_VI_CONFIG_CMD_UDPEN) { 5415 /* 5416 * If UDP hashing was enabled it must have been enabled for 5417 * either IPv4 or IPv6 (inclusive or). Enabling UDP without 5418 * enabling any 4-tuple hash is nonsense configuration. 5419 */ 5420 MPASS(hashen & (F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN | 5421 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)); 5422 5423 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 5424 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV4; 5425 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 5426 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV6; 5427 } 5428 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 5429 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV4; 5430 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 5431 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV6; 5432 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 5433 hashconfig |= RSS_HASHTYPE_RSS_IPV4; 5434 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 5435 hashconfig |= RSS_HASHTYPE_RSS_IPV6; 5436 5437 return (hashconfig); 5438 } 5439 #endif 5440 5441 int 5442 vi_full_init(struct vi_info *vi) 5443 { 5444 struct adapter *sc = vi->pi->adapter; 5445 struct ifnet *ifp = vi->ifp; 5446 uint16_t *rss; 5447 struct sge_rxq *rxq; 5448 int rc, i, j; 5449 #ifdef RSS 5450 int nbuckets = rss_getnumbuckets(); 5451 int hashconfig = rss_gethashconfig(); 5452 int extra; 5453 #endif 5454 5455 ASSERT_SYNCHRONIZED_OP(sc); 5456 KASSERT((vi->flags & VI_INIT_DONE) == 0, 5457 ("%s: VI_INIT_DONE already", __func__)); 5458 5459 sysctl_ctx_init(&vi->ctx); 5460 vi->flags |= VI_SYSCTL_CTX; 5461 5462 /* 5463 * Allocate tx/rx/fl queues for this VI. 5464 */ 5465 rc = t4_setup_vi_queues(vi); 5466 if (rc != 0) 5467 goto done; /* error message displayed already */ 5468 5469 /* 5470 * Setup RSS for this VI. Save a copy of the RSS table for later use. 5471 */ 5472 if (vi->nrxq > vi->rss_size) { 5473 if_printf(ifp, "nrxq (%d) > hw RSS table size (%d); " 5474 "some queues will never receive traffic.\n", vi->nrxq, 5475 vi->rss_size); 5476 } else if (vi->rss_size % vi->nrxq) { 5477 if_printf(ifp, "nrxq (%d), hw RSS table size (%d); " 5478 "expect uneven traffic distribution.\n", vi->nrxq, 5479 vi->rss_size); 5480 } 5481 #ifdef RSS 5482 if (vi->nrxq != nbuckets) { 5483 if_printf(ifp, "nrxq (%d) != kernel RSS buckets (%d);" 5484 "performance will be impacted.\n", vi->nrxq, nbuckets); 5485 } 5486 #endif 5487 rss = malloc(vi->rss_size * sizeof (*rss), M_CXGBE, M_ZERO | M_WAITOK); 5488 for (i = 0; i < vi->rss_size;) { 5489 #ifdef RSS 5490 j = rss_get_indirection_to_bucket(i); 5491 j %= vi->nrxq; 5492 rxq = &sc->sge.rxq[vi->first_rxq + j]; 5493 rss[i++] = rxq->iq.abs_id; 5494 #else 5495 for_each_rxq(vi, j, rxq) { 5496 rss[i++] = rxq->iq.abs_id; 5497 if (i == vi->rss_size) 5498 break; 5499 } 5500 #endif 5501 } 5502 5503 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, rss, 5504 vi->rss_size); 5505 if (rc != 0) { 5506 free(rss, M_CXGBE); 5507 if_printf(ifp, "rss_config failed: %d\n", rc); 5508 goto done; 5509 } 5510 5511 #ifdef RSS 5512 vi->hashen = hashconfig_to_hashen(hashconfig); 5513 5514 /* 5515 * We may have had to enable some hashes even though the global config 5516 * wants them disabled. This is a potential problem that must be 5517 * reported to the user. 5518 */ 5519 extra = hashen_to_hashconfig(vi->hashen) ^ hashconfig; 5520 5521 /* 5522 * If we consider only the supported hash types, then the enabled hashes 5523 * are a superset of the requested hashes. In other words, there cannot 5524 * be any supported hash that was requested but not enabled, but there 5525 * can be hashes that were not requested but had to be enabled. 5526 */ 5527 extra &= SUPPORTED_RSS_HASHTYPES; 5528 MPASS((extra & hashconfig) == 0); 5529 5530 if (extra) { 5531 if_printf(ifp, 5532 "global RSS config (0x%x) cannot be accommodated.\n", 5533 hashconfig); 5534 } 5535 if (extra & RSS_HASHTYPE_RSS_IPV4) 5536 if_printf(ifp, "IPv4 2-tuple hashing forced on.\n"); 5537 if (extra & RSS_HASHTYPE_RSS_TCP_IPV4) 5538 if_printf(ifp, "TCP/IPv4 4-tuple hashing forced on.\n"); 5539 if (extra & RSS_HASHTYPE_RSS_IPV6) 5540 if_printf(ifp, "IPv6 2-tuple hashing forced on.\n"); 5541 if (extra & RSS_HASHTYPE_RSS_TCP_IPV6) 5542 if_printf(ifp, "TCP/IPv6 4-tuple hashing forced on.\n"); 5543 if (extra & RSS_HASHTYPE_RSS_UDP_IPV4) 5544 if_printf(ifp, "UDP/IPv4 4-tuple hashing forced on.\n"); 5545 if (extra & RSS_HASHTYPE_RSS_UDP_IPV6) 5546 if_printf(ifp, "UDP/IPv6 4-tuple hashing forced on.\n"); 5547 #else 5548 vi->hashen = F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN | 5549 F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN | 5550 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN | 5551 F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN | F_FW_RSS_VI_CONFIG_CMD_UDPEN; 5552 #endif 5553 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, vi->hashen, rss[0], 0, 0); 5554 if (rc != 0) { 5555 free(rss, M_CXGBE); 5556 if_printf(ifp, "rss hash/defaultq config failed: %d\n", rc); 5557 goto done; 5558 } 5559 5560 vi->rss = rss; 5561 vi->flags |= VI_INIT_DONE; 5562 done: 5563 if (rc != 0) 5564 vi_full_uninit(vi); 5565 5566 return (rc); 5567 } 5568 5569 /* 5570 * Idempotent. 5571 */ 5572 int 5573 vi_full_uninit(struct vi_info *vi) 5574 { 5575 struct port_info *pi = vi->pi; 5576 struct adapter *sc = pi->adapter; 5577 int i; 5578 struct sge_rxq *rxq; 5579 struct sge_txq *txq; 5580 #ifdef TCP_OFFLOAD 5581 struct sge_ofld_rxq *ofld_rxq; 5582 #endif 5583 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 5584 struct sge_wrq *ofld_txq; 5585 #endif 5586 5587 if (vi->flags & VI_INIT_DONE) { 5588 5589 /* Need to quiesce queues. */ 5590 5591 /* XXX: Only for the first VI? */ 5592 if (IS_MAIN_VI(vi) && !(sc->flags & IS_VF)) 5593 quiesce_wrq(sc, &sc->sge.ctrlq[pi->port_id]); 5594 5595 for_each_txq(vi, i, txq) { 5596 quiesce_txq(sc, txq); 5597 } 5598 5599 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 5600 for_each_ofld_txq(vi, i, ofld_txq) { 5601 quiesce_wrq(sc, ofld_txq); 5602 } 5603 #endif 5604 5605 for_each_rxq(vi, i, rxq) { 5606 quiesce_iq(sc, &rxq->iq); 5607 quiesce_fl(sc, &rxq->fl); 5608 } 5609 5610 #ifdef TCP_OFFLOAD 5611 for_each_ofld_rxq(vi, i, ofld_rxq) { 5612 quiesce_iq(sc, &ofld_rxq->iq); 5613 quiesce_fl(sc, &ofld_rxq->fl); 5614 } 5615 #endif 5616 free(vi->rss, M_CXGBE); 5617 free(vi->nm_rss, M_CXGBE); 5618 } 5619 5620 t4_teardown_vi_queues(vi); 5621 vi->flags &= ~VI_INIT_DONE; 5622 5623 return (0); 5624 } 5625 5626 static void 5627 quiesce_txq(struct adapter *sc, struct sge_txq *txq) 5628 { 5629 struct sge_eq *eq = &txq->eq; 5630 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx]; 5631 5632 (void) sc; /* unused */ 5633 5634 #ifdef INVARIANTS 5635 TXQ_LOCK(txq); 5636 MPASS((eq->flags & EQ_ENABLED) == 0); 5637 TXQ_UNLOCK(txq); 5638 #endif 5639 5640 /* Wait for the mp_ring to empty. */ 5641 while (!mp_ring_is_idle(txq->r)) { 5642 mp_ring_check_drainage(txq->r, 0); 5643 pause("rquiesce", 1); 5644 } 5645 5646 /* Then wait for the hardware to finish. */ 5647 while (spg->cidx != htobe16(eq->pidx)) 5648 pause("equiesce", 1); 5649 5650 /* Finally, wait for the driver to reclaim all descriptors. */ 5651 while (eq->cidx != eq->pidx) 5652 pause("dquiesce", 1); 5653 } 5654 5655 static void 5656 quiesce_wrq(struct adapter *sc, struct sge_wrq *wrq) 5657 { 5658 5659 /* XXXTX */ 5660 } 5661 5662 static void 5663 quiesce_iq(struct adapter *sc, struct sge_iq *iq) 5664 { 5665 (void) sc; /* unused */ 5666 5667 /* Synchronize with the interrupt handler */ 5668 while (!atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_DISABLED)) 5669 pause("iqfree", 1); 5670 } 5671 5672 static void 5673 quiesce_fl(struct adapter *sc, struct sge_fl *fl) 5674 { 5675 mtx_lock(&sc->sfl_lock); 5676 FL_LOCK(fl); 5677 fl->flags |= FL_DOOMED; 5678 FL_UNLOCK(fl); 5679 callout_stop(&sc->sfl_callout); 5680 mtx_unlock(&sc->sfl_lock); 5681 5682 KASSERT((fl->flags & FL_STARVING) == 0, 5683 ("%s: still starving", __func__)); 5684 } 5685 5686 static int 5687 t4_alloc_irq(struct adapter *sc, struct irq *irq, int rid, 5688 driver_intr_t *handler, void *arg, char *name) 5689 { 5690 int rc; 5691 5692 irq->rid = rid; 5693 irq->res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &irq->rid, 5694 RF_SHAREABLE | RF_ACTIVE); 5695 if (irq->res == NULL) { 5696 device_printf(sc->dev, 5697 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 5698 return (ENOMEM); 5699 } 5700 5701 rc = bus_setup_intr(sc->dev, irq->res, INTR_MPSAFE | INTR_TYPE_NET, 5702 NULL, handler, arg, &irq->tag); 5703 if (rc != 0) { 5704 device_printf(sc->dev, 5705 "failed to setup interrupt for rid %d, name %s: %d\n", 5706 rid, name, rc); 5707 } else if (name) 5708 bus_describe_intr(sc->dev, irq->res, irq->tag, "%s", name); 5709 5710 return (rc); 5711 } 5712 5713 static int 5714 t4_free_irq(struct adapter *sc, struct irq *irq) 5715 { 5716 if (irq->tag) 5717 bus_teardown_intr(sc->dev, irq->res, irq->tag); 5718 if (irq->res) 5719 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->rid, irq->res); 5720 5721 bzero(irq, sizeof(*irq)); 5722 5723 return (0); 5724 } 5725 5726 static void 5727 get_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf) 5728 { 5729 5730 regs->version = chip_id(sc) | chip_rev(sc) << 10; 5731 t4_get_regs(sc, buf, regs->len); 5732 } 5733 5734 #define A_PL_INDIR_CMD 0x1f8 5735 5736 #define S_PL_AUTOINC 31 5737 #define M_PL_AUTOINC 0x1U 5738 #define V_PL_AUTOINC(x) ((x) << S_PL_AUTOINC) 5739 #define G_PL_AUTOINC(x) (((x) >> S_PL_AUTOINC) & M_PL_AUTOINC) 5740 5741 #define S_PL_VFID 20 5742 #define M_PL_VFID 0xffU 5743 #define V_PL_VFID(x) ((x) << S_PL_VFID) 5744 #define G_PL_VFID(x) (((x) >> S_PL_VFID) & M_PL_VFID) 5745 5746 #define S_PL_ADDR 0 5747 #define M_PL_ADDR 0xfffffU 5748 #define V_PL_ADDR(x) ((x) << S_PL_ADDR) 5749 #define G_PL_ADDR(x) (((x) >> S_PL_ADDR) & M_PL_ADDR) 5750 5751 #define A_PL_INDIR_DATA 0x1fc 5752 5753 static uint64_t 5754 read_vf_stat(struct adapter *sc, u_int vin, int reg) 5755 { 5756 u32 stats[2]; 5757 5758 mtx_assert(&sc->reg_lock, MA_OWNED); 5759 if (sc->flags & IS_VF) { 5760 stats[0] = t4_read_reg(sc, VF_MPS_REG(reg)); 5761 stats[1] = t4_read_reg(sc, VF_MPS_REG(reg + 4)); 5762 } else { 5763 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) | 5764 V_PL_VFID(vin) | V_PL_ADDR(VF_MPS_REG(reg))); 5765 stats[0] = t4_read_reg(sc, A_PL_INDIR_DATA); 5766 stats[1] = t4_read_reg(sc, A_PL_INDIR_DATA); 5767 } 5768 return (((uint64_t)stats[1]) << 32 | stats[0]); 5769 } 5770 5771 static void 5772 t4_get_vi_stats(struct adapter *sc, u_int vin, struct fw_vi_stats_vf *stats) 5773 { 5774 5775 #define GET_STAT(name) \ 5776 read_vf_stat(sc, vin, A_MPS_VF_STAT_##name##_L) 5777 5778 stats->tx_bcast_bytes = GET_STAT(TX_VF_BCAST_BYTES); 5779 stats->tx_bcast_frames = GET_STAT(TX_VF_BCAST_FRAMES); 5780 stats->tx_mcast_bytes = GET_STAT(TX_VF_MCAST_BYTES); 5781 stats->tx_mcast_frames = GET_STAT(TX_VF_MCAST_FRAMES); 5782 stats->tx_ucast_bytes = GET_STAT(TX_VF_UCAST_BYTES); 5783 stats->tx_ucast_frames = GET_STAT(TX_VF_UCAST_FRAMES); 5784 stats->tx_drop_frames = GET_STAT(TX_VF_DROP_FRAMES); 5785 stats->tx_offload_bytes = GET_STAT(TX_VF_OFFLOAD_BYTES); 5786 stats->tx_offload_frames = GET_STAT(TX_VF_OFFLOAD_FRAMES); 5787 stats->rx_bcast_bytes = GET_STAT(RX_VF_BCAST_BYTES); 5788 stats->rx_bcast_frames = GET_STAT(RX_VF_BCAST_FRAMES); 5789 stats->rx_mcast_bytes = GET_STAT(RX_VF_MCAST_BYTES); 5790 stats->rx_mcast_frames = GET_STAT(RX_VF_MCAST_FRAMES); 5791 stats->rx_ucast_bytes = GET_STAT(RX_VF_UCAST_BYTES); 5792 stats->rx_ucast_frames = GET_STAT(RX_VF_UCAST_FRAMES); 5793 stats->rx_err_frames = GET_STAT(RX_VF_ERR_FRAMES); 5794 5795 #undef GET_STAT 5796 } 5797 5798 static void 5799 t4_clr_vi_stats(struct adapter *sc, u_int vin) 5800 { 5801 int reg; 5802 5803 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) | V_PL_VFID(vin) | 5804 V_PL_ADDR(VF_MPS_REG(A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L))); 5805 for (reg = A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L; 5806 reg <= A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H; reg += 4) 5807 t4_write_reg(sc, A_PL_INDIR_DATA, 0); 5808 } 5809 5810 static void 5811 vi_refresh_stats(struct adapter *sc, struct vi_info *vi) 5812 { 5813 struct timeval tv; 5814 const struct timeval interval = {0, 250000}; /* 250ms */ 5815 5816 if (!(vi->flags & VI_INIT_DONE)) 5817 return; 5818 5819 getmicrotime(&tv); 5820 timevalsub(&tv, &interval); 5821 if (timevalcmp(&tv, &vi->last_refreshed, <)) 5822 return; 5823 5824 mtx_lock(&sc->reg_lock); 5825 t4_get_vi_stats(sc, vi->vin, &vi->stats); 5826 getmicrotime(&vi->last_refreshed); 5827 mtx_unlock(&sc->reg_lock); 5828 } 5829 5830 static void 5831 cxgbe_refresh_stats(struct adapter *sc, struct port_info *pi) 5832 { 5833 u_int i, v, tnl_cong_drops, bg_map; 5834 struct timeval tv; 5835 const struct timeval interval = {0, 250000}; /* 250ms */ 5836 5837 getmicrotime(&tv); 5838 timevalsub(&tv, &interval); 5839 if (timevalcmp(&tv, &pi->last_refreshed, <)) 5840 return; 5841 5842 tnl_cong_drops = 0; 5843 t4_get_port_stats(sc, pi->tx_chan, &pi->stats); 5844 bg_map = pi->mps_bg_map; 5845 while (bg_map) { 5846 i = ffs(bg_map) - 1; 5847 mtx_lock(&sc->reg_lock); 5848 t4_read_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v, 1, 5849 A_TP_MIB_TNL_CNG_DROP_0 + i); 5850 mtx_unlock(&sc->reg_lock); 5851 tnl_cong_drops += v; 5852 bg_map &= ~(1 << i); 5853 } 5854 pi->tnl_cong_drops = tnl_cong_drops; 5855 getmicrotime(&pi->last_refreshed); 5856 } 5857 5858 static void 5859 cxgbe_tick(void *arg) 5860 { 5861 struct port_info *pi = arg; 5862 struct adapter *sc = pi->adapter; 5863 5864 PORT_LOCK_ASSERT_OWNED(pi); 5865 cxgbe_refresh_stats(sc, pi); 5866 5867 callout_schedule(&pi->tick, hz); 5868 } 5869 5870 void 5871 vi_tick(void *arg) 5872 { 5873 struct vi_info *vi = arg; 5874 struct adapter *sc = vi->pi->adapter; 5875 5876 vi_refresh_stats(sc, vi); 5877 5878 callout_schedule(&vi->tick, hz); 5879 } 5880 5881 /* 5882 * Should match fw_caps_config_<foo> enums in t4fw_interface.h 5883 */ 5884 static char *caps_decoder[] = { 5885 "\20\001IPMI\002NCSI", /* 0: NBM */ 5886 "\20\001PPP\002QFC\003DCBX", /* 1: link */ 5887 "\20\001INGRESS\002EGRESS", /* 2: switch */ 5888 "\20\001NIC\002VM\003IDS\004UM\005UM_ISGL" /* 3: NIC */ 5889 "\006HASHFILTER\007ETHOFLD", 5890 "\20\001TOE", /* 4: TOE */ 5891 "\20\001RDDP\002RDMAC", /* 5: RDMA */ 5892 "\20\001INITIATOR_PDU\002TARGET_PDU" /* 6: iSCSI */ 5893 "\003INITIATOR_CNXOFLD\004TARGET_CNXOFLD" 5894 "\005INITIATOR_SSNOFLD\006TARGET_SSNOFLD" 5895 "\007T10DIF" 5896 "\010INITIATOR_CMDOFLD\011TARGET_CMDOFLD", 5897 "\20\001LOOKASIDE\002TLSKEYS", /* 7: Crypto */ 5898 "\20\001INITIATOR\002TARGET\003CTRL_OFLD" /* 8: FCoE */ 5899 "\004PO_INITIATOR\005PO_TARGET", 5900 }; 5901 5902 void 5903 t4_sysctls(struct adapter *sc) 5904 { 5905 struct sysctl_ctx_list *ctx; 5906 struct sysctl_oid *oid; 5907 struct sysctl_oid_list *children, *c0; 5908 static char *doorbells = {"\20\1UDB\2WCWR\3UDBWC\4KDB"}; 5909 5910 ctx = device_get_sysctl_ctx(sc->dev); 5911 5912 /* 5913 * dev.t4nex.X. 5914 */ 5915 oid = device_get_sysctl_tree(sc->dev); 5916 c0 = children = SYSCTL_CHILDREN(oid); 5917 5918 sc->sc_do_rxcopy = 1; 5919 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "do_rx_copy", CTLFLAG_RW, 5920 &sc->sc_do_rxcopy, 1, "Do RX copy of small frames"); 5921 5922 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nports", CTLFLAG_RD, NULL, 5923 sc->params.nports, "# of ports"); 5924 5925 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "doorbells", 5926 CTLTYPE_STRING | CTLFLAG_RD, doorbells, (uintptr_t)&sc->doorbells, 5927 sysctl_bitfield_8b, "A", "available doorbells"); 5928 5929 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_clock", CTLFLAG_RD, NULL, 5930 sc->params.vpd.cclk, "core clock frequency (in KHz)"); 5931 5932 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_timers", 5933 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.timer_val, 5934 sizeof(sc->params.sge.timer_val), sysctl_int_array, "A", 5935 "interrupt holdoff timer values (us)"); 5936 5937 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pkt_counts", 5938 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.counter_val, 5939 sizeof(sc->params.sge.counter_val), sysctl_int_array, "A", 5940 "interrupt holdoff packet counter values"); 5941 5942 t4_sge_sysctls(sc, ctx, children); 5943 5944 sc->lro_timeout = 100; 5945 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lro_timeout", CTLFLAG_RW, 5946 &sc->lro_timeout, 0, "lro inactive-flush timeout (in us)"); 5947 5948 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dflags", CTLFLAG_RW, 5949 &sc->debug_flags, 0, "flags to enable runtime debugging"); 5950 5951 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "tp_version", 5952 CTLFLAG_RD, sc->tp_version, 0, "TP microcode version"); 5953 5954 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "firmware_version", 5955 CTLFLAG_RD, sc->fw_version, 0, "firmware version"); 5956 5957 if (sc->flags & IS_VF) 5958 return; 5959 5960 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "hw_revision", CTLFLAG_RD, 5961 NULL, chip_rev(sc), "chip hardware revision"); 5962 5963 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "sn", 5964 CTLFLAG_RD, sc->params.vpd.sn, 0, "serial number"); 5965 5966 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "pn", 5967 CTLFLAG_RD, sc->params.vpd.pn, 0, "part number"); 5968 5969 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "ec", 5970 CTLFLAG_RD, sc->params.vpd.ec, 0, "engineering change"); 5971 5972 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "md_version", 5973 CTLFLAG_RD, sc->params.vpd.md, 0, "manufacturing diags version"); 5974 5975 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "na", 5976 CTLFLAG_RD, sc->params.vpd.na, 0, "network address"); 5977 5978 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "er_version", CTLFLAG_RD, 5979 sc->er_version, 0, "expansion ROM version"); 5980 5981 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "bs_version", CTLFLAG_RD, 5982 sc->bs_version, 0, "bootstrap firmware version"); 5983 5984 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "scfg_version", CTLFLAG_RD, 5985 NULL, sc->params.scfg_vers, "serial config version"); 5986 5987 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "vpd_version", CTLFLAG_RD, 5988 NULL, sc->params.vpd_vers, "VPD version"); 5989 5990 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "cf", 5991 CTLFLAG_RD, sc->cfg_file, 0, "configuration file"); 5992 5993 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cfcsum", CTLFLAG_RD, NULL, 5994 sc->cfcsum, "config file checksum"); 5995 5996 #define SYSCTL_CAP(name, n, text) \ 5997 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, #name, \ 5998 CTLTYPE_STRING | CTLFLAG_RD, caps_decoder[n], (uintptr_t)&sc->name, \ 5999 sysctl_bitfield_16b, "A", "available " text " capabilities") 6000 6001 SYSCTL_CAP(nbmcaps, 0, "NBM"); 6002 SYSCTL_CAP(linkcaps, 1, "link"); 6003 SYSCTL_CAP(switchcaps, 2, "switch"); 6004 SYSCTL_CAP(niccaps, 3, "NIC"); 6005 SYSCTL_CAP(toecaps, 4, "TCP offload"); 6006 SYSCTL_CAP(rdmacaps, 5, "RDMA"); 6007 SYSCTL_CAP(iscsicaps, 6, "iSCSI"); 6008 SYSCTL_CAP(cryptocaps, 7, "crypto"); 6009 SYSCTL_CAP(fcoecaps, 8, "FCoE"); 6010 #undef SYSCTL_CAP 6011 6012 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nfilters", CTLFLAG_RD, 6013 NULL, sc->tids.nftids, "number of filters"); 6014 6015 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", CTLTYPE_INT | 6016 CTLFLAG_RD, sc, 0, sysctl_temperature, "I", 6017 "chip temperature (in Celsius)"); 6018 6019 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "loadavg", CTLTYPE_STRING | 6020 CTLFLAG_RD, sc, 0, sysctl_loadavg, "A", 6021 "microprocessor load averages (debug firmwares only)"); 6022 6023 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_vdd", CTLFLAG_RD, 6024 &sc->params.core_vdd, 0, "core Vdd (in mV)"); 6025 6026 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "local_cpus", 6027 CTLTYPE_STRING | CTLFLAG_RD, sc, LOCAL_CPUS, 6028 sysctl_cpus, "A", "local CPUs"); 6029 6030 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "intr_cpus", 6031 CTLTYPE_STRING | CTLFLAG_RD, sc, INTR_CPUS, 6032 sysctl_cpus, "A", "preferred CPUs for interrupts"); 6033 6034 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "swintr", CTLFLAG_RW, 6035 &sc->swintr, 0, "software triggered interrupts"); 6036 6037 /* 6038 * dev.t4nex.X.misc. Marked CTLFLAG_SKIP to avoid information overload. 6039 */ 6040 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "misc", 6041 CTLFLAG_RD | CTLFLAG_SKIP, NULL, 6042 "logs and miscellaneous information"); 6043 children = SYSCTL_CHILDREN(oid); 6044 6045 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cctrl", 6046 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6047 sysctl_cctrl, "A", "congestion control"); 6048 6049 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp0", 6050 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6051 sysctl_cim_ibq_obq, "A", "CIM IBQ 0 (TP0)"); 6052 6053 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp1", 6054 CTLTYPE_STRING | CTLFLAG_RD, sc, 1, 6055 sysctl_cim_ibq_obq, "A", "CIM IBQ 1 (TP1)"); 6056 6057 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ulp", 6058 CTLTYPE_STRING | CTLFLAG_RD, sc, 2, 6059 sysctl_cim_ibq_obq, "A", "CIM IBQ 2 (ULP)"); 6060 6061 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge0", 6062 CTLTYPE_STRING | CTLFLAG_RD, sc, 3, 6063 sysctl_cim_ibq_obq, "A", "CIM IBQ 3 (SGE0)"); 6064 6065 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge1", 6066 CTLTYPE_STRING | CTLFLAG_RD, sc, 4, 6067 sysctl_cim_ibq_obq, "A", "CIM IBQ 4 (SGE1)"); 6068 6069 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ncsi", 6070 CTLTYPE_STRING | CTLFLAG_RD, sc, 5, 6071 sysctl_cim_ibq_obq, "A", "CIM IBQ 5 (NCSI)"); 6072 6073 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_la", 6074 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, sysctl_cim_la, 6075 "A", "CIM logic analyzer"); 6076 6077 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ma_la", 6078 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6079 sysctl_cim_ma_la, "A", "CIM MA logic analyzer"); 6080 6081 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp0", 6082 CTLTYPE_STRING | CTLFLAG_RD, sc, 0 + CIM_NUM_IBQ, 6083 sysctl_cim_ibq_obq, "A", "CIM OBQ 0 (ULP0)"); 6084 6085 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp1", 6086 CTLTYPE_STRING | CTLFLAG_RD, sc, 1 + CIM_NUM_IBQ, 6087 sysctl_cim_ibq_obq, "A", "CIM OBQ 1 (ULP1)"); 6088 6089 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp2", 6090 CTLTYPE_STRING | CTLFLAG_RD, sc, 2 + CIM_NUM_IBQ, 6091 sysctl_cim_ibq_obq, "A", "CIM OBQ 2 (ULP2)"); 6092 6093 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp3", 6094 CTLTYPE_STRING | CTLFLAG_RD, sc, 3 + CIM_NUM_IBQ, 6095 sysctl_cim_ibq_obq, "A", "CIM OBQ 3 (ULP3)"); 6096 6097 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge", 6098 CTLTYPE_STRING | CTLFLAG_RD, sc, 4 + CIM_NUM_IBQ, 6099 sysctl_cim_ibq_obq, "A", "CIM OBQ 4 (SGE)"); 6100 6101 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ncsi", 6102 CTLTYPE_STRING | CTLFLAG_RD, sc, 5 + CIM_NUM_IBQ, 6103 sysctl_cim_ibq_obq, "A", "CIM OBQ 5 (NCSI)"); 6104 6105 if (chip_id(sc) > CHELSIO_T4) { 6106 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge0_rx", 6107 CTLTYPE_STRING | CTLFLAG_RD, sc, 6 + CIM_NUM_IBQ, 6108 sysctl_cim_ibq_obq, "A", "CIM OBQ 6 (SGE0-RX)"); 6109 6110 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge1_rx", 6111 CTLTYPE_STRING | CTLFLAG_RD, sc, 7 + CIM_NUM_IBQ, 6112 sysctl_cim_ibq_obq, "A", "CIM OBQ 7 (SGE1-RX)"); 6113 } 6114 6115 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_pif_la", 6116 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6117 sysctl_cim_pif_la, "A", "CIM PIF logic analyzer"); 6118 6119 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_qcfg", 6120 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6121 sysctl_cim_qcfg, "A", "CIM queue configuration"); 6122 6123 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cpl_stats", 6124 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6125 sysctl_cpl_stats, "A", "CPL statistics"); 6126 6127 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ddp_stats", 6128 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6129 sysctl_ddp_stats, "A", "non-TCP DDP statistics"); 6130 6131 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "devlog", 6132 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6133 sysctl_devlog, "A", "firmware's device log"); 6134 6135 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fcoe_stats", 6136 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6137 sysctl_fcoe_stats, "A", "FCoE statistics"); 6138 6139 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hw_sched", 6140 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6141 sysctl_hw_sched, "A", "hardware scheduler "); 6142 6143 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "l2t", 6144 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6145 sysctl_l2t, "A", "hardware L2 table"); 6146 6147 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "smt", 6148 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6149 sysctl_smt, "A", "hardware source MAC table"); 6150 6151 #ifdef INET6 6152 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "clip", 6153 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6154 sysctl_clip, "A", "active CLIP table entries"); 6155 #endif 6156 6157 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "lb_stats", 6158 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6159 sysctl_lb_stats, "A", "loopback statistics"); 6160 6161 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "meminfo", 6162 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6163 sysctl_meminfo, "A", "memory regions"); 6164 6165 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mps_tcam", 6166 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6167 chip_id(sc) <= CHELSIO_T5 ? sysctl_mps_tcam : sysctl_mps_tcam_t6, 6168 "A", "MPS TCAM entries"); 6169 6170 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "path_mtus", 6171 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6172 sysctl_path_mtus, "A", "path MTUs"); 6173 6174 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pm_stats", 6175 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6176 sysctl_pm_stats, "A", "PM statistics"); 6177 6178 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rdma_stats", 6179 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6180 sysctl_rdma_stats, "A", "RDMA statistics"); 6181 6182 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tcp_stats", 6183 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6184 sysctl_tcp_stats, "A", "TCP statistics"); 6185 6186 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tids", 6187 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6188 sysctl_tids, "A", "TID information"); 6189 6190 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_err_stats", 6191 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6192 sysctl_tp_err_stats, "A", "TP error statistics"); 6193 6194 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la_mask", 6195 CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_tp_la_mask, "I", 6196 "TP logic analyzer event capture mask"); 6197 6198 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la", 6199 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6200 sysctl_tp_la, "A", "TP logic analyzer"); 6201 6202 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_rate", 6203 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6204 sysctl_tx_rate, "A", "Tx rate"); 6205 6206 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ulprx_la", 6207 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6208 sysctl_ulprx_la, "A", "ULPRX logic analyzer"); 6209 6210 if (chip_id(sc) >= CHELSIO_T5) { 6211 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "wcwr_stats", 6212 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 6213 sysctl_wcwr_stats, "A", "write combined work requests"); 6214 } 6215 6216 #ifdef TCP_OFFLOAD 6217 if (is_offload(sc)) { 6218 int i; 6219 char s[4]; 6220 6221 /* 6222 * dev.t4nex.X.toe. 6223 */ 6224 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "toe", CTLFLAG_RD, 6225 NULL, "TOE parameters"); 6226 children = SYSCTL_CHILDREN(oid); 6227 6228 sc->tt.cong_algorithm = -1; 6229 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_algorithm", 6230 CTLFLAG_RW, &sc->tt.cong_algorithm, 0, "congestion control " 6231 "(-1 = default, 0 = reno, 1 = tahoe, 2 = newreno, " 6232 "3 = highspeed)"); 6233 6234 sc->tt.sndbuf = 256 * 1024; 6235 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sndbuf", CTLFLAG_RW, 6236 &sc->tt.sndbuf, 0, "max hardware send buffer size"); 6237 6238 sc->tt.ddp = 0; 6239 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ddp", CTLFLAG_RW, 6240 &sc->tt.ddp, 0, "DDP allowed"); 6241 6242 sc->tt.rx_coalesce = 1; 6243 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_coalesce", 6244 CTLFLAG_RW, &sc->tt.rx_coalesce, 0, "receive coalescing"); 6245 6246 sc->tt.tls = 0; 6247 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tls", CTLFLAG_RW, 6248 &sc->tt.tls, 0, "Inline TLS allowed"); 6249 6250 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tls_rx_ports", 6251 CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_tls_rx_ports, 6252 "I", "TCP ports that use inline TLS+TOE RX"); 6253 6254 sc->tt.tx_align = 1; 6255 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_align", 6256 CTLFLAG_RW, &sc->tt.tx_align, 0, "chop and align payload"); 6257 6258 sc->tt.tx_zcopy = 0; 6259 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_zcopy", 6260 CTLFLAG_RW, &sc->tt.tx_zcopy, 0, 6261 "Enable zero-copy aio_write(2)"); 6262 6263 sc->tt.cop_managed_offloading = !!t4_cop_managed_offloading; 6264 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 6265 "cop_managed_offloading", CTLFLAG_RW, 6266 &sc->tt.cop_managed_offloading, 0, 6267 "COP (Connection Offload Policy) controls all TOE offload"); 6268 6269 sc->tt.autorcvbuf_inc = 16 * 1024; 6270 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "autorcvbuf_inc", 6271 CTLFLAG_RW, &sc->tt.autorcvbuf_inc, 0, 6272 "autorcvbuf increment"); 6273 6274 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timer_tick", 6275 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, sysctl_tp_tick, "A", 6276 "TP timer tick (us)"); 6277 6278 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timestamp_tick", 6279 CTLTYPE_STRING | CTLFLAG_RD, sc, 1, sysctl_tp_tick, "A", 6280 "TCP timestamp tick (us)"); 6281 6282 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_tick", 6283 CTLTYPE_STRING | CTLFLAG_RD, sc, 2, sysctl_tp_tick, "A", 6284 "DACK tick (us)"); 6285 6286 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_timer", 6287 CTLTYPE_UINT | CTLFLAG_RD, sc, 0, sysctl_tp_dack_timer, 6288 "IU", "DACK timer (us)"); 6289 6290 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_min", 6291 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MIN, 6292 sysctl_tp_timer, "LU", "Minimum retransmit interval (us)"); 6293 6294 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_max", 6295 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MAX, 6296 sysctl_tp_timer, "LU", "Maximum retransmit interval (us)"); 6297 6298 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_min", 6299 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MIN, 6300 sysctl_tp_timer, "LU", "Persist timer min (us)"); 6301 6302 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_max", 6303 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MAX, 6304 sysctl_tp_timer, "LU", "Persist timer max (us)"); 6305 6306 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_idle", 6307 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_IDLE, 6308 sysctl_tp_timer, "LU", "Keepalive idle timer (us)"); 6309 6310 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_interval", 6311 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_INTVL, 6312 sysctl_tp_timer, "LU", "Keepalive interval timer (us)"); 6313 6314 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "initial_srtt", 6315 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_INIT_SRTT, 6316 sysctl_tp_timer, "LU", "Initial SRTT (us)"); 6317 6318 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "finwait2_timer", 6319 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_FINWAIT2_TIMER, 6320 sysctl_tp_timer, "LU", "FINWAIT2 timer (us)"); 6321 6322 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "syn_rexmt_count", 6323 CTLTYPE_UINT | CTLFLAG_RD, sc, S_SYNSHIFTMAX, 6324 sysctl_tp_shift_cnt, "IU", 6325 "Number of SYN retransmissions before abort"); 6326 6327 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_count", 6328 CTLTYPE_UINT | CTLFLAG_RD, sc, S_RXTSHIFTMAXR2, 6329 sysctl_tp_shift_cnt, "IU", 6330 "Number of retransmissions before abort"); 6331 6332 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_count", 6333 CTLTYPE_UINT | CTLFLAG_RD, sc, S_KEEPALIVEMAXR2, 6334 sysctl_tp_shift_cnt, "IU", 6335 "Number of keepalive probes before abort"); 6336 6337 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "rexmt_backoff", 6338 CTLFLAG_RD, NULL, "TOE retransmit backoffs"); 6339 children = SYSCTL_CHILDREN(oid); 6340 for (i = 0; i < 16; i++) { 6341 snprintf(s, sizeof(s), "%u", i); 6342 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, s, 6343 CTLTYPE_UINT | CTLFLAG_RD, sc, i, sysctl_tp_backoff, 6344 "IU", "TOE retransmit backoff"); 6345 } 6346 } 6347 #endif 6348 } 6349 6350 void 6351 vi_sysctls(struct vi_info *vi) 6352 { 6353 struct sysctl_ctx_list *ctx; 6354 struct sysctl_oid *oid; 6355 struct sysctl_oid_list *children; 6356 6357 ctx = device_get_sysctl_ctx(vi->dev); 6358 6359 /* 6360 * dev.v?(cxgbe|cxl).X. 6361 */ 6362 oid = device_get_sysctl_tree(vi->dev); 6363 children = SYSCTL_CHILDREN(oid); 6364 6365 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "viid", CTLFLAG_RD, NULL, 6366 vi->viid, "VI identifer"); 6367 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nrxq", CTLFLAG_RD, 6368 &vi->nrxq, 0, "# of rx queues"); 6369 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ntxq", CTLFLAG_RD, 6370 &vi->ntxq, 0, "# of tx queues"); 6371 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_rxq", CTLFLAG_RD, 6372 &vi->first_rxq, 0, "index of first rx queue"); 6373 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_txq", CTLFLAG_RD, 6374 &vi->first_txq, 0, "index of first tx queue"); 6375 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_base", CTLFLAG_RD, NULL, 6376 vi->rss_base, "start of RSS indirection table"); 6377 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_size", CTLFLAG_RD, NULL, 6378 vi->rss_size, "size of RSS indirection table"); 6379 6380 if (IS_MAIN_VI(vi)) { 6381 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rsrv_noflowq", 6382 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_noflowq, "IU", 6383 "Reserve queue 0 for non-flowid packets"); 6384 } 6385 6386 #ifdef TCP_OFFLOAD 6387 if (vi->nofldrxq != 0) { 6388 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldrxq", CTLFLAG_RD, 6389 &vi->nofldrxq, 0, 6390 "# of rx queues for offloaded TCP connections"); 6391 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_rxq", 6392 CTLFLAG_RD, &vi->first_ofld_rxq, 0, 6393 "index of first TOE rx queue"); 6394 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx_ofld", 6395 CTLTYPE_INT | CTLFLAG_RW, vi, 0, 6396 sysctl_holdoff_tmr_idx_ofld, "I", 6397 "holdoff timer index for TOE queues"); 6398 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx_ofld", 6399 CTLTYPE_INT | CTLFLAG_RW, vi, 0, 6400 sysctl_holdoff_pktc_idx_ofld, "I", 6401 "holdoff packet counter index for TOE queues"); 6402 } 6403 #endif 6404 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 6405 if (vi->nofldtxq != 0) { 6406 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldtxq", CTLFLAG_RD, 6407 &vi->nofldtxq, 0, 6408 "# of tx queues for TOE/ETHOFLD"); 6409 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_txq", 6410 CTLFLAG_RD, &vi->first_ofld_txq, 0, 6411 "index of first TOE/ETHOFLD tx queue"); 6412 } 6413 #endif 6414 #ifdef DEV_NETMAP 6415 if (vi->nnmrxq != 0) { 6416 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmrxq", CTLFLAG_RD, 6417 &vi->nnmrxq, 0, "# of netmap rx queues"); 6418 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmtxq", CTLFLAG_RD, 6419 &vi->nnmtxq, 0, "# of netmap tx queues"); 6420 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_rxq", 6421 CTLFLAG_RD, &vi->first_nm_rxq, 0, 6422 "index of first netmap rx queue"); 6423 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_txq", 6424 CTLFLAG_RD, &vi->first_nm_txq, 0, 6425 "index of first netmap tx queue"); 6426 } 6427 #endif 6428 6429 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx", 6430 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_tmr_idx, "I", 6431 "holdoff timer index"); 6432 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx", 6433 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_pktc_idx, "I", 6434 "holdoff packet counter index"); 6435 6436 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_rxq", 6437 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_rxq, "I", 6438 "rx queue size"); 6439 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_txq", 6440 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_txq, "I", 6441 "tx queue size"); 6442 } 6443 6444 static void 6445 cxgbe_sysctls(struct port_info *pi) 6446 { 6447 struct sysctl_ctx_list *ctx; 6448 struct sysctl_oid *oid; 6449 struct sysctl_oid_list *children, *children2; 6450 struct adapter *sc = pi->adapter; 6451 int i; 6452 char name[16]; 6453 static char *tc_flags = {"\20\1USER\2SYNC\3ASYNC\4ERR"}; 6454 6455 ctx = device_get_sysctl_ctx(pi->dev); 6456 6457 /* 6458 * dev.cxgbe.X. 6459 */ 6460 oid = device_get_sysctl_tree(pi->dev); 6461 children = SYSCTL_CHILDREN(oid); 6462 6463 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "linkdnrc", CTLTYPE_STRING | 6464 CTLFLAG_RD, pi, 0, sysctl_linkdnrc, "A", "reason why link is down"); 6465 if (pi->port_type == FW_PORT_TYPE_BT_XAUI) { 6466 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", 6467 CTLTYPE_INT | CTLFLAG_RD, pi, 0, sysctl_btphy, "I", 6468 "PHY temperature (in Celsius)"); 6469 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fw_version", 6470 CTLTYPE_INT | CTLFLAG_RD, pi, 1, sysctl_btphy, "I", 6471 "PHY firmware version"); 6472 } 6473 6474 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pause_settings", 6475 CTLTYPE_STRING | CTLFLAG_RW, pi, 0, sysctl_pause_settings, "A", 6476 "PAUSE settings (bit 0 = rx_pause, 1 = tx_pause, 2 = pause_autoneg)"); 6477 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fec", 6478 CTLTYPE_STRING | CTLFLAG_RW, pi, 0, sysctl_fec, "A", 6479 "Forward Error Correction (bit 0 = RS, bit 1 = BASER_RS)"); 6480 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "autoneg", 6481 CTLTYPE_INT | CTLFLAG_RW, pi, 0, sysctl_autoneg, "I", 6482 "autonegotiation (-1 = not supported)"); 6483 6484 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "max_speed", CTLFLAG_RD, NULL, 6485 port_top_speed(pi), "max speed (in Gbps)"); 6486 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "mps_bg_map", CTLFLAG_RD, NULL, 6487 pi->mps_bg_map, "MPS buffer group map"); 6488 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_e_chan_map", CTLFLAG_RD, 6489 NULL, pi->rx_e_chan_map, "TP rx e-channel map"); 6490 6491 if (sc->flags & IS_VF) 6492 return; 6493 6494 /* 6495 * dev.(cxgbe|cxl).X.tc. 6496 */ 6497 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "tc", CTLFLAG_RD, NULL, 6498 "Tx scheduler traffic classes (cl_rl)"); 6499 children2 = SYSCTL_CHILDREN(oid); 6500 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "pktsize", 6501 CTLFLAG_RW, &pi->sched_params->pktsize, 0, 6502 "pktsize for per-flow cl-rl (0 means up to the driver )"); 6503 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "burstsize", 6504 CTLFLAG_RW, &pi->sched_params->burstsize, 0, 6505 "burstsize for per-flow cl-rl (0 means up to the driver)"); 6506 for (i = 0; i < sc->chip_params->nsched_cls; i++) { 6507 struct tx_cl_rl_params *tc = &pi->sched_params->cl_rl[i]; 6508 6509 snprintf(name, sizeof(name), "%d", i); 6510 children2 = SYSCTL_CHILDREN(SYSCTL_ADD_NODE(ctx, 6511 SYSCTL_CHILDREN(oid), OID_AUTO, name, CTLFLAG_RD, NULL, 6512 "traffic class")); 6513 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "flags", 6514 CTLTYPE_STRING | CTLFLAG_RD, tc_flags, (uintptr_t)&tc->flags, 6515 sysctl_bitfield_8b, "A", "flags"); 6516 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "refcount", 6517 CTLFLAG_RD, &tc->refcount, 0, "references to this class"); 6518 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "params", 6519 CTLTYPE_STRING | CTLFLAG_RD, sc, (pi->port_id << 16) | i, 6520 sysctl_tc_params, "A", "traffic class parameters"); 6521 } 6522 6523 /* 6524 * dev.cxgbe.X.stats. 6525 */ 6526 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD, 6527 NULL, "port statistics"); 6528 children = SYSCTL_CHILDREN(oid); 6529 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "tx_parse_error", CTLFLAG_RD, 6530 &pi->tx_parse_error, 0, 6531 "# of tx packets with invalid length or # of segments"); 6532 6533 #define SYSCTL_ADD_T4_REG64(pi, name, desc, reg) \ 6534 SYSCTL_ADD_OID(ctx, children, OID_AUTO, name, \ 6535 CTLTYPE_U64 | CTLFLAG_RD, sc, reg, \ 6536 sysctl_handle_t4_reg64, "QU", desc) 6537 6538 SYSCTL_ADD_T4_REG64(pi, "tx_octets", "# of octets in good frames", 6539 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BYTES_L)); 6540 SYSCTL_ADD_T4_REG64(pi, "tx_frames", "total # of good frames", 6541 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_FRAMES_L)); 6542 SYSCTL_ADD_T4_REG64(pi, "tx_bcast_frames", "# of broadcast frames", 6543 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BCAST_L)); 6544 SYSCTL_ADD_T4_REG64(pi, "tx_mcast_frames", "# of multicast frames", 6545 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_MCAST_L)); 6546 SYSCTL_ADD_T4_REG64(pi, "tx_ucast_frames", "# of unicast frames", 6547 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_UCAST_L)); 6548 SYSCTL_ADD_T4_REG64(pi, "tx_error_frames", "# of error frames", 6549 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_ERROR_L)); 6550 SYSCTL_ADD_T4_REG64(pi, "tx_frames_64", 6551 "# of tx frames in this range", 6552 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_64B_L)); 6553 SYSCTL_ADD_T4_REG64(pi, "tx_frames_65_127", 6554 "# of tx frames in this range", 6555 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_65B_127B_L)); 6556 SYSCTL_ADD_T4_REG64(pi, "tx_frames_128_255", 6557 "# of tx frames in this range", 6558 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_128B_255B_L)); 6559 SYSCTL_ADD_T4_REG64(pi, "tx_frames_256_511", 6560 "# of tx frames in this range", 6561 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_256B_511B_L)); 6562 SYSCTL_ADD_T4_REG64(pi, "tx_frames_512_1023", 6563 "# of tx frames in this range", 6564 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_512B_1023B_L)); 6565 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1024_1518", 6566 "# of tx frames in this range", 6567 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1024B_1518B_L)); 6568 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1519_max", 6569 "# of tx frames in this range", 6570 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1519B_MAX_L)); 6571 SYSCTL_ADD_T4_REG64(pi, "tx_drop", "# of dropped tx frames", 6572 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_DROP_L)); 6573 SYSCTL_ADD_T4_REG64(pi, "tx_pause", "# of pause frames transmitted", 6574 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PAUSE_L)); 6575 SYSCTL_ADD_T4_REG64(pi, "tx_ppp0", "# of PPP prio 0 frames transmitted", 6576 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP0_L)); 6577 SYSCTL_ADD_T4_REG64(pi, "tx_ppp1", "# of PPP prio 1 frames transmitted", 6578 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP1_L)); 6579 SYSCTL_ADD_T4_REG64(pi, "tx_ppp2", "# of PPP prio 2 frames transmitted", 6580 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP2_L)); 6581 SYSCTL_ADD_T4_REG64(pi, "tx_ppp3", "# of PPP prio 3 frames transmitted", 6582 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP3_L)); 6583 SYSCTL_ADD_T4_REG64(pi, "tx_ppp4", "# of PPP prio 4 frames transmitted", 6584 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP4_L)); 6585 SYSCTL_ADD_T4_REG64(pi, "tx_ppp5", "# of PPP prio 5 frames transmitted", 6586 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP5_L)); 6587 SYSCTL_ADD_T4_REG64(pi, "tx_ppp6", "# of PPP prio 6 frames transmitted", 6588 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP6_L)); 6589 SYSCTL_ADD_T4_REG64(pi, "tx_ppp7", "# of PPP prio 7 frames transmitted", 6590 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP7_L)); 6591 6592 SYSCTL_ADD_T4_REG64(pi, "rx_octets", "# of octets in good frames", 6593 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BYTES_L)); 6594 SYSCTL_ADD_T4_REG64(pi, "rx_frames", "total # of good frames", 6595 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_FRAMES_L)); 6596 SYSCTL_ADD_T4_REG64(pi, "rx_bcast_frames", "# of broadcast frames", 6597 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BCAST_L)); 6598 SYSCTL_ADD_T4_REG64(pi, "rx_mcast_frames", "# of multicast frames", 6599 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MCAST_L)); 6600 SYSCTL_ADD_T4_REG64(pi, "rx_ucast_frames", "# of unicast frames", 6601 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_UCAST_L)); 6602 SYSCTL_ADD_T4_REG64(pi, "rx_too_long", "# of frames exceeding MTU", 6603 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L)); 6604 SYSCTL_ADD_T4_REG64(pi, "rx_jabber", "# of jabber frames", 6605 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L)); 6606 SYSCTL_ADD_T4_REG64(pi, "rx_fcs_err", 6607 "# of frames received with bad FCS", 6608 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L)); 6609 SYSCTL_ADD_T4_REG64(pi, "rx_len_err", 6610 "# of frames received with length error", 6611 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L)); 6612 SYSCTL_ADD_T4_REG64(pi, "rx_symbol_err", "symbol errors", 6613 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L)); 6614 SYSCTL_ADD_T4_REG64(pi, "rx_runt", "# of short frames received", 6615 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LESS_64B_L)); 6616 SYSCTL_ADD_T4_REG64(pi, "rx_frames_64", 6617 "# of rx frames in this range", 6618 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_64B_L)); 6619 SYSCTL_ADD_T4_REG64(pi, "rx_frames_65_127", 6620 "# of rx frames in this range", 6621 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_65B_127B_L)); 6622 SYSCTL_ADD_T4_REG64(pi, "rx_frames_128_255", 6623 "# of rx frames in this range", 6624 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_128B_255B_L)); 6625 SYSCTL_ADD_T4_REG64(pi, "rx_frames_256_511", 6626 "# of rx frames in this range", 6627 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_256B_511B_L)); 6628 SYSCTL_ADD_T4_REG64(pi, "rx_frames_512_1023", 6629 "# of rx frames in this range", 6630 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_512B_1023B_L)); 6631 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1024_1518", 6632 "# of rx frames in this range", 6633 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1024B_1518B_L)); 6634 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1519_max", 6635 "# of rx frames in this range", 6636 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1519B_MAX_L)); 6637 SYSCTL_ADD_T4_REG64(pi, "rx_pause", "# of pause frames received", 6638 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PAUSE_L)); 6639 SYSCTL_ADD_T4_REG64(pi, "rx_ppp0", "# of PPP prio 0 frames received", 6640 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP0_L)); 6641 SYSCTL_ADD_T4_REG64(pi, "rx_ppp1", "# of PPP prio 1 frames received", 6642 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP1_L)); 6643 SYSCTL_ADD_T4_REG64(pi, "rx_ppp2", "# of PPP prio 2 frames received", 6644 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP2_L)); 6645 SYSCTL_ADD_T4_REG64(pi, "rx_ppp3", "# of PPP prio 3 frames received", 6646 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP3_L)); 6647 SYSCTL_ADD_T4_REG64(pi, "rx_ppp4", "# of PPP prio 4 frames received", 6648 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP4_L)); 6649 SYSCTL_ADD_T4_REG64(pi, "rx_ppp5", "# of PPP prio 5 frames received", 6650 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP5_L)); 6651 SYSCTL_ADD_T4_REG64(pi, "rx_ppp6", "# of PPP prio 6 frames received", 6652 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP6_L)); 6653 SYSCTL_ADD_T4_REG64(pi, "rx_ppp7", "# of PPP prio 7 frames received", 6654 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP7_L)); 6655 6656 #undef SYSCTL_ADD_T4_REG64 6657 6658 #define SYSCTL_ADD_T4_PORTSTAT(name, desc) \ 6659 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, #name, CTLFLAG_RD, \ 6660 &pi->stats.name, desc) 6661 6662 /* We get these from port_stats and they may be stale by up to 1s */ 6663 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow0, 6664 "# drops due to buffer-group 0 overflows"); 6665 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow1, 6666 "# drops due to buffer-group 1 overflows"); 6667 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow2, 6668 "# drops due to buffer-group 2 overflows"); 6669 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow3, 6670 "# drops due to buffer-group 3 overflows"); 6671 SYSCTL_ADD_T4_PORTSTAT(rx_trunc0, 6672 "# of buffer-group 0 truncated packets"); 6673 SYSCTL_ADD_T4_PORTSTAT(rx_trunc1, 6674 "# of buffer-group 1 truncated packets"); 6675 SYSCTL_ADD_T4_PORTSTAT(rx_trunc2, 6676 "# of buffer-group 2 truncated packets"); 6677 SYSCTL_ADD_T4_PORTSTAT(rx_trunc3, 6678 "# of buffer-group 3 truncated packets"); 6679 6680 #undef SYSCTL_ADD_T4_PORTSTAT 6681 6682 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "tx_tls_records", 6683 CTLFLAG_RD, &pi->tx_tls_records, 6684 "# of TLS records transmitted"); 6685 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "tx_tls_octets", 6686 CTLFLAG_RD, &pi->tx_tls_octets, 6687 "# of payload octets in transmitted TLS records"); 6688 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "rx_tls_records", 6689 CTLFLAG_RD, &pi->rx_tls_records, 6690 "# of TLS records received"); 6691 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "rx_tls_octets", 6692 CTLFLAG_RD, &pi->rx_tls_octets, 6693 "# of payload octets in received TLS records"); 6694 } 6695 6696 static int 6697 sysctl_int_array(SYSCTL_HANDLER_ARGS) 6698 { 6699 int rc, *i, space = 0; 6700 struct sbuf sb; 6701 6702 sbuf_new_for_sysctl(&sb, NULL, 64, req); 6703 for (i = arg1; arg2; arg2 -= sizeof(int), i++) { 6704 if (space) 6705 sbuf_printf(&sb, " "); 6706 sbuf_printf(&sb, "%d", *i); 6707 space = 1; 6708 } 6709 rc = sbuf_finish(&sb); 6710 sbuf_delete(&sb); 6711 return (rc); 6712 } 6713 6714 static int 6715 sysctl_bitfield_8b(SYSCTL_HANDLER_ARGS) 6716 { 6717 int rc; 6718 struct sbuf *sb; 6719 6720 rc = sysctl_wire_old_buffer(req, 0); 6721 if (rc != 0) 6722 return(rc); 6723 6724 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 6725 if (sb == NULL) 6726 return (ENOMEM); 6727 6728 sbuf_printf(sb, "%b", *(uint8_t *)(uintptr_t)arg2, (char *)arg1); 6729 rc = sbuf_finish(sb); 6730 sbuf_delete(sb); 6731 6732 return (rc); 6733 } 6734 6735 static int 6736 sysctl_bitfield_16b(SYSCTL_HANDLER_ARGS) 6737 { 6738 int rc; 6739 struct sbuf *sb; 6740 6741 rc = sysctl_wire_old_buffer(req, 0); 6742 if (rc != 0) 6743 return(rc); 6744 6745 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 6746 if (sb == NULL) 6747 return (ENOMEM); 6748 6749 sbuf_printf(sb, "%b", *(uint16_t *)(uintptr_t)arg2, (char *)arg1); 6750 rc = sbuf_finish(sb); 6751 sbuf_delete(sb); 6752 6753 return (rc); 6754 } 6755 6756 static int 6757 sysctl_btphy(SYSCTL_HANDLER_ARGS) 6758 { 6759 struct port_info *pi = arg1; 6760 int op = arg2; 6761 struct adapter *sc = pi->adapter; 6762 u_int v; 6763 int rc; 6764 6765 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, "t4btt"); 6766 if (rc) 6767 return (rc); 6768 /* XXX: magic numbers */ 6769 rc = -t4_mdio_rd(sc, sc->mbox, pi->mdio_addr, 0x1e, op ? 0x20 : 0xc820, 6770 &v); 6771 end_synchronized_op(sc, 0); 6772 if (rc) 6773 return (rc); 6774 if (op == 0) 6775 v /= 256; 6776 6777 rc = sysctl_handle_int(oidp, &v, 0, req); 6778 return (rc); 6779 } 6780 6781 static int 6782 sysctl_noflowq(SYSCTL_HANDLER_ARGS) 6783 { 6784 struct vi_info *vi = arg1; 6785 int rc, val; 6786 6787 val = vi->rsrv_noflowq; 6788 rc = sysctl_handle_int(oidp, &val, 0, req); 6789 if (rc != 0 || req->newptr == NULL) 6790 return (rc); 6791 6792 if ((val >= 1) && (vi->ntxq > 1)) 6793 vi->rsrv_noflowq = 1; 6794 else 6795 vi->rsrv_noflowq = 0; 6796 6797 return (rc); 6798 } 6799 6800 static int 6801 sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS) 6802 { 6803 struct vi_info *vi = arg1; 6804 struct adapter *sc = vi->pi->adapter; 6805 int idx, rc, i; 6806 struct sge_rxq *rxq; 6807 uint8_t v; 6808 6809 idx = vi->tmr_idx; 6810 6811 rc = sysctl_handle_int(oidp, &idx, 0, req); 6812 if (rc != 0 || req->newptr == NULL) 6813 return (rc); 6814 6815 if (idx < 0 || idx >= SGE_NTIMERS) 6816 return (EINVAL); 6817 6818 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 6819 "t4tmr"); 6820 if (rc) 6821 return (rc); 6822 6823 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->pktc_idx != -1); 6824 for_each_rxq(vi, i, rxq) { 6825 #ifdef atomic_store_rel_8 6826 atomic_store_rel_8(&rxq->iq.intr_params, v); 6827 #else 6828 rxq->iq.intr_params = v; 6829 #endif 6830 } 6831 vi->tmr_idx = idx; 6832 6833 end_synchronized_op(sc, LOCK_HELD); 6834 return (0); 6835 } 6836 6837 static int 6838 sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS) 6839 { 6840 struct vi_info *vi = arg1; 6841 struct adapter *sc = vi->pi->adapter; 6842 int idx, rc; 6843 6844 idx = vi->pktc_idx; 6845 6846 rc = sysctl_handle_int(oidp, &idx, 0, req); 6847 if (rc != 0 || req->newptr == NULL) 6848 return (rc); 6849 6850 if (idx < -1 || idx >= SGE_NCOUNTERS) 6851 return (EINVAL); 6852 6853 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 6854 "t4pktc"); 6855 if (rc) 6856 return (rc); 6857 6858 if (vi->flags & VI_INIT_DONE) 6859 rc = EBUSY; /* cannot be changed once the queues are created */ 6860 else 6861 vi->pktc_idx = idx; 6862 6863 end_synchronized_op(sc, LOCK_HELD); 6864 return (rc); 6865 } 6866 6867 static int 6868 sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS) 6869 { 6870 struct vi_info *vi = arg1; 6871 struct adapter *sc = vi->pi->adapter; 6872 int qsize, rc; 6873 6874 qsize = vi->qsize_rxq; 6875 6876 rc = sysctl_handle_int(oidp, &qsize, 0, req); 6877 if (rc != 0 || req->newptr == NULL) 6878 return (rc); 6879 6880 if (qsize < 128 || (qsize & 7)) 6881 return (EINVAL); 6882 6883 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 6884 "t4rxqs"); 6885 if (rc) 6886 return (rc); 6887 6888 if (vi->flags & VI_INIT_DONE) 6889 rc = EBUSY; /* cannot be changed once the queues are created */ 6890 else 6891 vi->qsize_rxq = qsize; 6892 6893 end_synchronized_op(sc, LOCK_HELD); 6894 return (rc); 6895 } 6896 6897 static int 6898 sysctl_qsize_txq(SYSCTL_HANDLER_ARGS) 6899 { 6900 struct vi_info *vi = arg1; 6901 struct adapter *sc = vi->pi->adapter; 6902 int qsize, rc; 6903 6904 qsize = vi->qsize_txq; 6905 6906 rc = sysctl_handle_int(oidp, &qsize, 0, req); 6907 if (rc != 0 || req->newptr == NULL) 6908 return (rc); 6909 6910 if (qsize < 128 || qsize > 65536) 6911 return (EINVAL); 6912 6913 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 6914 "t4txqs"); 6915 if (rc) 6916 return (rc); 6917 6918 if (vi->flags & VI_INIT_DONE) 6919 rc = EBUSY; /* cannot be changed once the queues are created */ 6920 else 6921 vi->qsize_txq = qsize; 6922 6923 end_synchronized_op(sc, LOCK_HELD); 6924 return (rc); 6925 } 6926 6927 static int 6928 sysctl_pause_settings(SYSCTL_HANDLER_ARGS) 6929 { 6930 struct port_info *pi = arg1; 6931 struct adapter *sc = pi->adapter; 6932 struct link_config *lc = &pi->link_cfg; 6933 int rc; 6934 6935 if (req->newptr == NULL) { 6936 struct sbuf *sb; 6937 static char *bits = "\20\1RX\2TX\3AUTO"; 6938 6939 rc = sysctl_wire_old_buffer(req, 0); 6940 if (rc != 0) 6941 return(rc); 6942 6943 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 6944 if (sb == NULL) 6945 return (ENOMEM); 6946 6947 if (lc->link_ok) { 6948 sbuf_printf(sb, "%b", (lc->fc & (PAUSE_TX | PAUSE_RX)) | 6949 (lc->requested_fc & PAUSE_AUTONEG), bits); 6950 } else { 6951 sbuf_printf(sb, "%b", lc->requested_fc & (PAUSE_TX | 6952 PAUSE_RX | PAUSE_AUTONEG), bits); 6953 } 6954 rc = sbuf_finish(sb); 6955 sbuf_delete(sb); 6956 } else { 6957 char s[2]; 6958 int n; 6959 6960 s[0] = '0' + (lc->requested_fc & (PAUSE_TX | PAUSE_RX | 6961 PAUSE_AUTONEG)); 6962 s[1] = 0; 6963 6964 rc = sysctl_handle_string(oidp, s, sizeof(s), req); 6965 if (rc != 0) 6966 return(rc); 6967 6968 if (s[1] != 0) 6969 return (EINVAL); 6970 if (s[0] < '0' || s[0] > '9') 6971 return (EINVAL); /* not a number */ 6972 n = s[0] - '0'; 6973 if (n & ~(PAUSE_TX | PAUSE_RX | PAUSE_AUTONEG)) 6974 return (EINVAL); /* some other bit is set too */ 6975 6976 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 6977 "t4PAUSE"); 6978 if (rc) 6979 return (rc); 6980 PORT_LOCK(pi); 6981 lc->requested_fc = n; 6982 fixup_link_config(pi); 6983 if (pi->up_vis > 0) 6984 rc = apply_link_config(pi); 6985 set_current_media(pi); 6986 PORT_UNLOCK(pi); 6987 end_synchronized_op(sc, 0); 6988 } 6989 6990 return (rc); 6991 } 6992 6993 static int 6994 sysctl_fec(SYSCTL_HANDLER_ARGS) 6995 { 6996 struct port_info *pi = arg1; 6997 struct adapter *sc = pi->adapter; 6998 struct link_config *lc = &pi->link_cfg; 6999 int rc; 7000 int8_t old; 7001 7002 if (req->newptr == NULL) { 7003 struct sbuf *sb; 7004 static char *bits = "\20\1RS\2BASE-R\3RSVD1\4RSVD2\5RSVD3\6AUTO"; 7005 7006 rc = sysctl_wire_old_buffer(req, 0); 7007 if (rc != 0) 7008 return(rc); 7009 7010 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 7011 if (sb == NULL) 7012 return (ENOMEM); 7013 7014 /* 7015 * Display the requested_fec when the link is down -- the actual 7016 * FEC makes sense only when the link is up. 7017 */ 7018 if (lc->link_ok) { 7019 sbuf_printf(sb, "%b", (lc->fec & M_FW_PORT_CAP32_FEC) | 7020 (lc->requested_fec & FEC_AUTO), bits); 7021 } else { 7022 sbuf_printf(sb, "%b", lc->requested_fec, bits); 7023 } 7024 rc = sbuf_finish(sb); 7025 sbuf_delete(sb); 7026 } else { 7027 char s[3]; 7028 int n; 7029 7030 snprintf(s, sizeof(s), "%d", 7031 lc->requested_fec == FEC_AUTO ? -1 : 7032 lc->requested_fec & M_FW_PORT_CAP32_FEC); 7033 7034 rc = sysctl_handle_string(oidp, s, sizeof(s), req); 7035 if (rc != 0) 7036 return(rc); 7037 7038 n = strtol(&s[0], NULL, 0); 7039 if (n < 0 || n & FEC_AUTO) 7040 n = FEC_AUTO; 7041 else { 7042 if (n & ~M_FW_PORT_CAP32_FEC) 7043 return (EINVAL);/* some other bit is set too */ 7044 if (!powerof2(n)) 7045 return (EINVAL);/* one bit can be set at most */ 7046 } 7047 7048 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 7049 "t4fec"); 7050 if (rc) 7051 return (rc); 7052 PORT_LOCK(pi); 7053 old = lc->requested_fec; 7054 if (n == FEC_AUTO) 7055 lc->requested_fec = FEC_AUTO; 7056 else if (n == 0) 7057 lc->requested_fec = FEC_NONE; 7058 else { 7059 if ((lc->supported | V_FW_PORT_CAP32_FEC(n)) != 7060 lc->supported) { 7061 rc = ENOTSUP; 7062 goto done; 7063 } 7064 lc->requested_fec = n; 7065 } 7066 fixup_link_config(pi); 7067 if (pi->up_vis > 0) { 7068 rc = apply_link_config(pi); 7069 if (rc != 0) { 7070 lc->requested_fec = old; 7071 if (rc == FW_EPROTO) 7072 rc = ENOTSUP; 7073 } 7074 } 7075 done: 7076 PORT_UNLOCK(pi); 7077 end_synchronized_op(sc, 0); 7078 } 7079 7080 return (rc); 7081 } 7082 7083 static int 7084 sysctl_autoneg(SYSCTL_HANDLER_ARGS) 7085 { 7086 struct port_info *pi = arg1; 7087 struct adapter *sc = pi->adapter; 7088 struct link_config *lc = &pi->link_cfg; 7089 int rc, val; 7090 7091 if (lc->supported & FW_PORT_CAP32_ANEG) 7092 val = lc->requested_aneg == AUTONEG_DISABLE ? 0 : 1; 7093 else 7094 val = -1; 7095 rc = sysctl_handle_int(oidp, &val, 0, req); 7096 if (rc != 0 || req->newptr == NULL) 7097 return (rc); 7098 if (val == 0) 7099 val = AUTONEG_DISABLE; 7100 else if (val == 1) 7101 val = AUTONEG_ENABLE; 7102 else 7103 val = AUTONEG_AUTO; 7104 7105 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 7106 "t4aneg"); 7107 if (rc) 7108 return (rc); 7109 PORT_LOCK(pi); 7110 if (val == AUTONEG_ENABLE && !(lc->supported & FW_PORT_CAP32_ANEG)) { 7111 rc = ENOTSUP; 7112 goto done; 7113 } 7114 lc->requested_aneg = val; 7115 fixup_link_config(pi); 7116 if (pi->up_vis > 0) 7117 rc = apply_link_config(pi); 7118 set_current_media(pi); 7119 done: 7120 PORT_UNLOCK(pi); 7121 end_synchronized_op(sc, 0); 7122 return (rc); 7123 } 7124 7125 static int 7126 sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS) 7127 { 7128 struct adapter *sc = arg1; 7129 int reg = arg2; 7130 uint64_t val; 7131 7132 val = t4_read_reg64(sc, reg); 7133 7134 return (sysctl_handle_64(oidp, &val, 0, req)); 7135 } 7136 7137 static int 7138 sysctl_temperature(SYSCTL_HANDLER_ARGS) 7139 { 7140 struct adapter *sc = arg1; 7141 int rc, t; 7142 uint32_t param, val; 7143 7144 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4temp"); 7145 if (rc) 7146 return (rc); 7147 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 7148 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 7149 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_TMP); 7150 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 7151 end_synchronized_op(sc, 0); 7152 if (rc) 7153 return (rc); 7154 7155 /* unknown is returned as 0 but we display -1 in that case */ 7156 t = val == 0 ? -1 : val; 7157 7158 rc = sysctl_handle_int(oidp, &t, 0, req); 7159 return (rc); 7160 } 7161 7162 static int 7163 sysctl_loadavg(SYSCTL_HANDLER_ARGS) 7164 { 7165 struct adapter *sc = arg1; 7166 struct sbuf *sb; 7167 int rc; 7168 uint32_t param, val; 7169 7170 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4lavg"); 7171 if (rc) 7172 return (rc); 7173 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 7174 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_LOAD); 7175 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 7176 end_synchronized_op(sc, 0); 7177 if (rc) 7178 return (rc); 7179 7180 rc = sysctl_wire_old_buffer(req, 0); 7181 if (rc != 0) 7182 return (rc); 7183 7184 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7185 if (sb == NULL) 7186 return (ENOMEM); 7187 7188 if (val == 0xffffffff) { 7189 /* Only debug and custom firmwares report load averages. */ 7190 sbuf_printf(sb, "not available"); 7191 } else { 7192 sbuf_printf(sb, "%d %d %d", val & 0xff, (val >> 8) & 0xff, 7193 (val >> 16) & 0xff); 7194 } 7195 rc = sbuf_finish(sb); 7196 sbuf_delete(sb); 7197 7198 return (rc); 7199 } 7200 7201 static int 7202 sysctl_cctrl(SYSCTL_HANDLER_ARGS) 7203 { 7204 struct adapter *sc = arg1; 7205 struct sbuf *sb; 7206 int rc, i; 7207 uint16_t incr[NMTUS][NCCTRL_WIN]; 7208 static const char *dec_fac[] = { 7209 "0.5", "0.5625", "0.625", "0.6875", "0.75", "0.8125", "0.875", 7210 "0.9375" 7211 }; 7212 7213 rc = sysctl_wire_old_buffer(req, 0); 7214 if (rc != 0) 7215 return (rc); 7216 7217 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7218 if (sb == NULL) 7219 return (ENOMEM); 7220 7221 t4_read_cong_tbl(sc, incr); 7222 7223 for (i = 0; i < NCCTRL_WIN; ++i) { 7224 sbuf_printf(sb, "%2d: %4u %4u %4u %4u %4u %4u %4u %4u\n", i, 7225 incr[0][i], incr[1][i], incr[2][i], incr[3][i], incr[4][i], 7226 incr[5][i], incr[6][i], incr[7][i]); 7227 sbuf_printf(sb, "%8u %4u %4u %4u %4u %4u %4u %4u %5u %s\n", 7228 incr[8][i], incr[9][i], incr[10][i], incr[11][i], 7229 incr[12][i], incr[13][i], incr[14][i], incr[15][i], 7230 sc->params.a_wnd[i], dec_fac[sc->params.b_wnd[i]]); 7231 } 7232 7233 rc = sbuf_finish(sb); 7234 sbuf_delete(sb); 7235 7236 return (rc); 7237 } 7238 7239 static const char *qname[CIM_NUM_IBQ + CIM_NUM_OBQ_T5] = { 7240 "TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI", /* ibq's */ 7241 "ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI", /* obq's */ 7242 "SGE0-RX", "SGE1-RX" /* additional obq's (T5 onwards) */ 7243 }; 7244 7245 static int 7246 sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS) 7247 { 7248 struct adapter *sc = arg1; 7249 struct sbuf *sb; 7250 int rc, i, n, qid = arg2; 7251 uint32_t *buf, *p; 7252 char *qtype; 7253 u_int cim_num_obq = sc->chip_params->cim_num_obq; 7254 7255 KASSERT(qid >= 0 && qid < CIM_NUM_IBQ + cim_num_obq, 7256 ("%s: bad qid %d\n", __func__, qid)); 7257 7258 if (qid < CIM_NUM_IBQ) { 7259 /* inbound queue */ 7260 qtype = "IBQ"; 7261 n = 4 * CIM_IBQ_SIZE; 7262 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK); 7263 rc = t4_read_cim_ibq(sc, qid, buf, n); 7264 } else { 7265 /* outbound queue */ 7266 qtype = "OBQ"; 7267 qid -= CIM_NUM_IBQ; 7268 n = 4 * cim_num_obq * CIM_OBQ_SIZE; 7269 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK); 7270 rc = t4_read_cim_obq(sc, qid, buf, n); 7271 } 7272 7273 if (rc < 0) { 7274 rc = -rc; 7275 goto done; 7276 } 7277 n = rc * sizeof(uint32_t); /* rc has # of words actually read */ 7278 7279 rc = sysctl_wire_old_buffer(req, 0); 7280 if (rc != 0) 7281 goto done; 7282 7283 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req); 7284 if (sb == NULL) { 7285 rc = ENOMEM; 7286 goto done; 7287 } 7288 7289 sbuf_printf(sb, "%s%d %s", qtype , qid, qname[arg2]); 7290 for (i = 0, p = buf; i < n; i += 16, p += 4) 7291 sbuf_printf(sb, "\n%#06x: %08x %08x %08x %08x", i, p[0], p[1], 7292 p[2], p[3]); 7293 7294 rc = sbuf_finish(sb); 7295 sbuf_delete(sb); 7296 done: 7297 free(buf, M_CXGBE); 7298 return (rc); 7299 } 7300 7301 static void 7302 sbuf_cim_la4(struct adapter *sc, struct sbuf *sb, uint32_t *buf, uint32_t cfg) 7303 { 7304 uint32_t *p; 7305 7306 sbuf_printf(sb, "Status Data PC%s", 7307 cfg & F_UPDBGLACAPTPCONLY ? "" : 7308 " LS0Stat LS0Addr LS0Data"); 7309 7310 for (p = buf; p <= &buf[sc->params.cim_la_size - 8]; p += 8) { 7311 if (cfg & F_UPDBGLACAPTPCONLY) { 7312 sbuf_printf(sb, "\n %02x %08x %08x", p[5] & 0xff, 7313 p[6], p[7]); 7314 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x", 7315 (p[3] >> 8) & 0xff, p[3] & 0xff, p[4] >> 8, 7316 p[4] & 0xff, p[5] >> 8); 7317 sbuf_printf(sb, "\n %02x %x%07x %x%07x", 7318 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4, 7319 p[1] & 0xf, p[2] >> 4); 7320 } else { 7321 sbuf_printf(sb, 7322 "\n %02x %x%07x %x%07x %08x %08x " 7323 "%08x%08x%08x%08x", 7324 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4, 7325 p[1] & 0xf, p[2] >> 4, p[2] & 0xf, p[3], p[4], p[5], 7326 p[6], p[7]); 7327 } 7328 } 7329 } 7330 7331 static void 7332 sbuf_cim_la6(struct adapter *sc, struct sbuf *sb, uint32_t *buf, uint32_t cfg) 7333 { 7334 uint32_t *p; 7335 7336 sbuf_printf(sb, "Status Inst Data PC%s", 7337 cfg & F_UPDBGLACAPTPCONLY ? "" : 7338 " LS0Stat LS0Addr LS0Data LS1Stat LS1Addr LS1Data"); 7339 7340 for (p = buf; p <= &buf[sc->params.cim_la_size - 10]; p += 10) { 7341 if (cfg & F_UPDBGLACAPTPCONLY) { 7342 sbuf_printf(sb, "\n %02x %08x %08x %08x", 7343 p[3] & 0xff, p[2], p[1], p[0]); 7344 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x %02x%06x", 7345 (p[6] >> 8) & 0xff, p[6] & 0xff, p[5] >> 8, 7346 p[5] & 0xff, p[4] >> 8, p[4] & 0xff, p[3] >> 8); 7347 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x", 7348 (p[9] >> 16) & 0xff, p[9] & 0xffff, p[8] >> 16, 7349 p[8] & 0xffff, p[7] >> 16, p[7] & 0xffff, 7350 p[6] >> 16); 7351 } else { 7352 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x " 7353 "%08x %08x %08x %08x %08x %08x", 7354 (p[9] >> 16) & 0xff, 7355 p[9] & 0xffff, p[8] >> 16, 7356 p[8] & 0xffff, p[7] >> 16, 7357 p[7] & 0xffff, p[6] >> 16, 7358 p[2], p[1], p[0], p[5], p[4], p[3]); 7359 } 7360 } 7361 } 7362 7363 static int 7364 sbuf_cim_la(struct adapter *sc, struct sbuf *sb, int flags) 7365 { 7366 uint32_t cfg, *buf; 7367 int rc; 7368 7369 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg); 7370 if (rc != 0) 7371 return (rc); 7372 7373 MPASS(flags == M_WAITOK || flags == M_NOWAIT); 7374 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE, 7375 M_ZERO | flags); 7376 if (buf == NULL) 7377 return (ENOMEM); 7378 7379 rc = -t4_cim_read_la(sc, buf, NULL); 7380 if (rc != 0) 7381 goto done; 7382 if (chip_id(sc) < CHELSIO_T6) 7383 sbuf_cim_la4(sc, sb, buf, cfg); 7384 else 7385 sbuf_cim_la6(sc, sb, buf, cfg); 7386 7387 done: 7388 free(buf, M_CXGBE); 7389 return (rc); 7390 } 7391 7392 static int 7393 sysctl_cim_la(SYSCTL_HANDLER_ARGS) 7394 { 7395 struct adapter *sc = arg1; 7396 struct sbuf *sb; 7397 int rc; 7398 7399 rc = sysctl_wire_old_buffer(req, 0); 7400 if (rc != 0) 7401 return (rc); 7402 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7403 if (sb == NULL) 7404 return (ENOMEM); 7405 7406 rc = sbuf_cim_la(sc, sb, M_WAITOK); 7407 if (rc == 0) 7408 rc = sbuf_finish(sb); 7409 sbuf_delete(sb); 7410 return (rc); 7411 } 7412 7413 bool 7414 t4_os_dump_cimla(struct adapter *sc, int arg, bool verbose) 7415 { 7416 struct sbuf sb; 7417 int rc; 7418 7419 if (sbuf_new(&sb, NULL, 4096, SBUF_AUTOEXTEND) != &sb) 7420 return (false); 7421 rc = sbuf_cim_la(sc, &sb, M_NOWAIT); 7422 if (rc == 0) { 7423 rc = sbuf_finish(&sb); 7424 if (rc == 0) { 7425 log(LOG_DEBUG, "%s: CIM LA dump follows.\n%s", 7426 device_get_nameunit(sc->dev), sbuf_data(&sb)); 7427 } 7428 } 7429 sbuf_delete(&sb); 7430 return (false); 7431 } 7432 7433 static int 7434 sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS) 7435 { 7436 struct adapter *sc = arg1; 7437 u_int i; 7438 struct sbuf *sb; 7439 uint32_t *buf, *p; 7440 int rc; 7441 7442 rc = sysctl_wire_old_buffer(req, 0); 7443 if (rc != 0) 7444 return (rc); 7445 7446 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7447 if (sb == NULL) 7448 return (ENOMEM); 7449 7450 buf = malloc(2 * CIM_MALA_SIZE * 5 * sizeof(uint32_t), M_CXGBE, 7451 M_ZERO | M_WAITOK); 7452 7453 t4_cim_read_ma_la(sc, buf, buf + 5 * CIM_MALA_SIZE); 7454 p = buf; 7455 7456 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) { 7457 sbuf_printf(sb, "\n%02x%08x%08x%08x%08x", p[4], p[3], p[2], 7458 p[1], p[0]); 7459 } 7460 7461 sbuf_printf(sb, "\n\nCnt ID Tag UE Data RDY VLD"); 7462 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) { 7463 sbuf_printf(sb, "\n%3u %2u %x %u %08x%08x %u %u", 7464 (p[2] >> 10) & 0xff, (p[2] >> 7) & 7, 7465 (p[2] >> 3) & 0xf, (p[2] >> 2) & 1, 7466 (p[1] >> 2) | ((p[2] & 3) << 30), 7467 (p[0] >> 2) | ((p[1] & 3) << 30), (p[0] >> 1) & 1, 7468 p[0] & 1); 7469 } 7470 7471 rc = sbuf_finish(sb); 7472 sbuf_delete(sb); 7473 free(buf, M_CXGBE); 7474 return (rc); 7475 } 7476 7477 static int 7478 sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS) 7479 { 7480 struct adapter *sc = arg1; 7481 u_int i; 7482 struct sbuf *sb; 7483 uint32_t *buf, *p; 7484 int rc; 7485 7486 rc = sysctl_wire_old_buffer(req, 0); 7487 if (rc != 0) 7488 return (rc); 7489 7490 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7491 if (sb == NULL) 7492 return (ENOMEM); 7493 7494 buf = malloc(2 * CIM_PIFLA_SIZE * 6 * sizeof(uint32_t), M_CXGBE, 7495 M_ZERO | M_WAITOK); 7496 7497 t4_cim_read_pif_la(sc, buf, buf + 6 * CIM_PIFLA_SIZE, NULL, NULL); 7498 p = buf; 7499 7500 sbuf_printf(sb, "Cntl ID DataBE Addr Data"); 7501 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) { 7502 sbuf_printf(sb, "\n %02x %02x %04x %08x %08x%08x%08x%08x", 7503 (p[5] >> 22) & 0xff, (p[5] >> 16) & 0x3f, p[5] & 0xffff, 7504 p[4], p[3], p[2], p[1], p[0]); 7505 } 7506 7507 sbuf_printf(sb, "\n\nCntl ID Data"); 7508 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) { 7509 sbuf_printf(sb, "\n %02x %02x %08x%08x%08x%08x", 7510 (p[4] >> 6) & 0xff, p[4] & 0x3f, p[3], p[2], p[1], p[0]); 7511 } 7512 7513 rc = sbuf_finish(sb); 7514 sbuf_delete(sb); 7515 free(buf, M_CXGBE); 7516 return (rc); 7517 } 7518 7519 static int 7520 sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS) 7521 { 7522 struct adapter *sc = arg1; 7523 struct sbuf *sb; 7524 int rc, i; 7525 uint16_t base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; 7526 uint16_t size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; 7527 uint16_t thres[CIM_NUM_IBQ]; 7528 uint32_t obq_wr[2 * CIM_NUM_OBQ_T5], *wr = obq_wr; 7529 uint32_t stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)], *p = stat; 7530 u_int cim_num_obq, ibq_rdaddr, obq_rdaddr, nq; 7531 7532 cim_num_obq = sc->chip_params->cim_num_obq; 7533 if (is_t4(sc)) { 7534 ibq_rdaddr = A_UP_IBQ_0_RDADDR; 7535 obq_rdaddr = A_UP_OBQ_0_REALADDR; 7536 } else { 7537 ibq_rdaddr = A_UP_IBQ_0_SHADOW_RDADDR; 7538 obq_rdaddr = A_UP_OBQ_0_SHADOW_REALADDR; 7539 } 7540 nq = CIM_NUM_IBQ + cim_num_obq; 7541 7542 rc = -t4_cim_read(sc, ibq_rdaddr, 4 * nq, stat); 7543 if (rc == 0) 7544 rc = -t4_cim_read(sc, obq_rdaddr, 2 * cim_num_obq, obq_wr); 7545 if (rc != 0) 7546 return (rc); 7547 7548 t4_read_cimq_cfg(sc, base, size, thres); 7549 7550 rc = sysctl_wire_old_buffer(req, 0); 7551 if (rc != 0) 7552 return (rc); 7553 7554 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req); 7555 if (sb == NULL) 7556 return (ENOMEM); 7557 7558 sbuf_printf(sb, 7559 " Queue Base Size Thres RdPtr WrPtr SOP EOP Avail"); 7560 7561 for (i = 0; i < CIM_NUM_IBQ; i++, p += 4) 7562 sbuf_printf(sb, "\n%7s %5x %5u %5u %6x %4x %4u %4u %5u", 7563 qname[i], base[i], size[i], thres[i], G_IBQRDADDR(p[0]), 7564 G_IBQWRADDR(p[1]), G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]), 7565 G_QUEREMFLITS(p[2]) * 16); 7566 for ( ; i < nq; i++, p += 4, wr += 2) 7567 sbuf_printf(sb, "\n%7s %5x %5u %12x %4x %4u %4u %5u", qname[i], 7568 base[i], size[i], G_QUERDADDR(p[0]) & 0x3fff, 7569 wr[0] - base[i], G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]), 7570 G_QUEREMFLITS(p[2]) * 16); 7571 7572 rc = sbuf_finish(sb); 7573 sbuf_delete(sb); 7574 7575 return (rc); 7576 } 7577 7578 static int 7579 sysctl_cpl_stats(SYSCTL_HANDLER_ARGS) 7580 { 7581 struct adapter *sc = arg1; 7582 struct sbuf *sb; 7583 int rc; 7584 struct tp_cpl_stats stats; 7585 7586 rc = sysctl_wire_old_buffer(req, 0); 7587 if (rc != 0) 7588 return (rc); 7589 7590 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7591 if (sb == NULL) 7592 return (ENOMEM); 7593 7594 mtx_lock(&sc->reg_lock); 7595 t4_tp_get_cpl_stats(sc, &stats, 0); 7596 mtx_unlock(&sc->reg_lock); 7597 7598 if (sc->chip_params->nchan > 2) { 7599 sbuf_printf(sb, " channel 0 channel 1" 7600 " channel 2 channel 3"); 7601 sbuf_printf(sb, "\nCPL requests: %10u %10u %10u %10u", 7602 stats.req[0], stats.req[1], stats.req[2], stats.req[3]); 7603 sbuf_printf(sb, "\nCPL responses: %10u %10u %10u %10u", 7604 stats.rsp[0], stats.rsp[1], stats.rsp[2], stats.rsp[3]); 7605 } else { 7606 sbuf_printf(sb, " channel 0 channel 1"); 7607 sbuf_printf(sb, "\nCPL requests: %10u %10u", 7608 stats.req[0], stats.req[1]); 7609 sbuf_printf(sb, "\nCPL responses: %10u %10u", 7610 stats.rsp[0], stats.rsp[1]); 7611 } 7612 7613 rc = sbuf_finish(sb); 7614 sbuf_delete(sb); 7615 7616 return (rc); 7617 } 7618 7619 static int 7620 sysctl_ddp_stats(SYSCTL_HANDLER_ARGS) 7621 { 7622 struct adapter *sc = arg1; 7623 struct sbuf *sb; 7624 int rc; 7625 struct tp_usm_stats stats; 7626 7627 rc = sysctl_wire_old_buffer(req, 0); 7628 if (rc != 0) 7629 return(rc); 7630 7631 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7632 if (sb == NULL) 7633 return (ENOMEM); 7634 7635 t4_get_usm_stats(sc, &stats, 1); 7636 7637 sbuf_printf(sb, "Frames: %u\n", stats.frames); 7638 sbuf_printf(sb, "Octets: %ju\n", stats.octets); 7639 sbuf_printf(sb, "Drops: %u", stats.drops); 7640 7641 rc = sbuf_finish(sb); 7642 sbuf_delete(sb); 7643 7644 return (rc); 7645 } 7646 7647 static const char * const devlog_level_strings[] = { 7648 [FW_DEVLOG_LEVEL_EMERG] = "EMERG", 7649 [FW_DEVLOG_LEVEL_CRIT] = "CRIT", 7650 [FW_DEVLOG_LEVEL_ERR] = "ERR", 7651 [FW_DEVLOG_LEVEL_NOTICE] = "NOTICE", 7652 [FW_DEVLOG_LEVEL_INFO] = "INFO", 7653 [FW_DEVLOG_LEVEL_DEBUG] = "DEBUG" 7654 }; 7655 7656 static const char * const devlog_facility_strings[] = { 7657 [FW_DEVLOG_FACILITY_CORE] = "CORE", 7658 [FW_DEVLOG_FACILITY_CF] = "CF", 7659 [FW_DEVLOG_FACILITY_SCHED] = "SCHED", 7660 [FW_DEVLOG_FACILITY_TIMER] = "TIMER", 7661 [FW_DEVLOG_FACILITY_RES] = "RES", 7662 [FW_DEVLOG_FACILITY_HW] = "HW", 7663 [FW_DEVLOG_FACILITY_FLR] = "FLR", 7664 [FW_DEVLOG_FACILITY_DMAQ] = "DMAQ", 7665 [FW_DEVLOG_FACILITY_PHY] = "PHY", 7666 [FW_DEVLOG_FACILITY_MAC] = "MAC", 7667 [FW_DEVLOG_FACILITY_PORT] = "PORT", 7668 [FW_DEVLOG_FACILITY_VI] = "VI", 7669 [FW_DEVLOG_FACILITY_FILTER] = "FILTER", 7670 [FW_DEVLOG_FACILITY_ACL] = "ACL", 7671 [FW_DEVLOG_FACILITY_TM] = "TM", 7672 [FW_DEVLOG_FACILITY_QFC] = "QFC", 7673 [FW_DEVLOG_FACILITY_DCB] = "DCB", 7674 [FW_DEVLOG_FACILITY_ETH] = "ETH", 7675 [FW_DEVLOG_FACILITY_OFLD] = "OFLD", 7676 [FW_DEVLOG_FACILITY_RI] = "RI", 7677 [FW_DEVLOG_FACILITY_ISCSI] = "ISCSI", 7678 [FW_DEVLOG_FACILITY_FCOE] = "FCOE", 7679 [FW_DEVLOG_FACILITY_FOISCSI] = "FOISCSI", 7680 [FW_DEVLOG_FACILITY_FOFCOE] = "FOFCOE", 7681 [FW_DEVLOG_FACILITY_CHNET] = "CHNET", 7682 }; 7683 7684 static int 7685 sbuf_devlog(struct adapter *sc, struct sbuf *sb, int flags) 7686 { 7687 int i, j, rc, nentries, first = 0; 7688 struct devlog_params *dparams = &sc->params.devlog; 7689 struct fw_devlog_e *buf, *e; 7690 uint64_t ftstamp = UINT64_MAX; 7691 7692 if (dparams->addr == 0) 7693 return (ENXIO); 7694 7695 MPASS(flags == M_WAITOK || flags == M_NOWAIT); 7696 buf = malloc(dparams->size, M_CXGBE, M_ZERO | flags); 7697 if (buf == NULL) 7698 return (ENOMEM); 7699 7700 rc = read_via_memwin(sc, 1, dparams->addr, (void *)buf, dparams->size); 7701 if (rc != 0) 7702 goto done; 7703 7704 nentries = dparams->size / sizeof(struct fw_devlog_e); 7705 for (i = 0; i < nentries; i++) { 7706 e = &buf[i]; 7707 7708 if (e->timestamp == 0) 7709 break; /* end */ 7710 7711 e->timestamp = be64toh(e->timestamp); 7712 e->seqno = be32toh(e->seqno); 7713 for (j = 0; j < 8; j++) 7714 e->params[j] = be32toh(e->params[j]); 7715 7716 if (e->timestamp < ftstamp) { 7717 ftstamp = e->timestamp; 7718 first = i; 7719 } 7720 } 7721 7722 if (buf[first].timestamp == 0) 7723 goto done; /* nothing in the log */ 7724 7725 sbuf_printf(sb, "%10s %15s %8s %8s %s\n", 7726 "Seq#", "Tstamp", "Level", "Facility", "Message"); 7727 7728 i = first; 7729 do { 7730 e = &buf[i]; 7731 if (e->timestamp == 0) 7732 break; /* end */ 7733 7734 sbuf_printf(sb, "%10d %15ju %8s %8s ", 7735 e->seqno, e->timestamp, 7736 (e->level < nitems(devlog_level_strings) ? 7737 devlog_level_strings[e->level] : "UNKNOWN"), 7738 (e->facility < nitems(devlog_facility_strings) ? 7739 devlog_facility_strings[e->facility] : "UNKNOWN")); 7740 sbuf_printf(sb, e->fmt, e->params[0], e->params[1], 7741 e->params[2], e->params[3], e->params[4], 7742 e->params[5], e->params[6], e->params[7]); 7743 7744 if (++i == nentries) 7745 i = 0; 7746 } while (i != first); 7747 done: 7748 free(buf, M_CXGBE); 7749 return (rc); 7750 } 7751 7752 static int 7753 sysctl_devlog(SYSCTL_HANDLER_ARGS) 7754 { 7755 struct adapter *sc = arg1; 7756 int rc; 7757 struct sbuf *sb; 7758 7759 rc = sysctl_wire_old_buffer(req, 0); 7760 if (rc != 0) 7761 return (rc); 7762 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7763 if (sb == NULL) 7764 return (ENOMEM); 7765 7766 rc = sbuf_devlog(sc, sb, M_WAITOK); 7767 if (rc == 0) 7768 rc = sbuf_finish(sb); 7769 sbuf_delete(sb); 7770 return (rc); 7771 } 7772 7773 void 7774 t4_os_dump_devlog(struct adapter *sc) 7775 { 7776 int rc; 7777 struct sbuf sb; 7778 7779 if (sbuf_new(&sb, NULL, 4096, SBUF_AUTOEXTEND) != &sb) 7780 return; 7781 rc = sbuf_devlog(sc, &sb, M_NOWAIT); 7782 if (rc == 0) { 7783 rc = sbuf_finish(&sb); 7784 if (rc == 0) { 7785 log(LOG_DEBUG, "%s: device log follows.\n%s", 7786 device_get_nameunit(sc->dev), sbuf_data(&sb)); 7787 } 7788 } 7789 sbuf_delete(&sb); 7790 } 7791 7792 static int 7793 sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS) 7794 { 7795 struct adapter *sc = arg1; 7796 struct sbuf *sb; 7797 int rc; 7798 struct tp_fcoe_stats stats[MAX_NCHAN]; 7799 int i, nchan = sc->chip_params->nchan; 7800 7801 rc = sysctl_wire_old_buffer(req, 0); 7802 if (rc != 0) 7803 return (rc); 7804 7805 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7806 if (sb == NULL) 7807 return (ENOMEM); 7808 7809 for (i = 0; i < nchan; i++) 7810 t4_get_fcoe_stats(sc, i, &stats[i], 1); 7811 7812 if (nchan > 2) { 7813 sbuf_printf(sb, " channel 0 channel 1" 7814 " channel 2 channel 3"); 7815 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju %16ju %16ju", 7816 stats[0].octets_ddp, stats[1].octets_ddp, 7817 stats[2].octets_ddp, stats[3].octets_ddp); 7818 sbuf_printf(sb, "\nframesDDP: %16u %16u %16u %16u", 7819 stats[0].frames_ddp, stats[1].frames_ddp, 7820 stats[2].frames_ddp, stats[3].frames_ddp); 7821 sbuf_printf(sb, "\nframesDrop: %16u %16u %16u %16u", 7822 stats[0].frames_drop, stats[1].frames_drop, 7823 stats[2].frames_drop, stats[3].frames_drop); 7824 } else { 7825 sbuf_printf(sb, " channel 0 channel 1"); 7826 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju", 7827 stats[0].octets_ddp, stats[1].octets_ddp); 7828 sbuf_printf(sb, "\nframesDDP: %16u %16u", 7829 stats[0].frames_ddp, stats[1].frames_ddp); 7830 sbuf_printf(sb, "\nframesDrop: %16u %16u", 7831 stats[0].frames_drop, stats[1].frames_drop); 7832 } 7833 7834 rc = sbuf_finish(sb); 7835 sbuf_delete(sb); 7836 7837 return (rc); 7838 } 7839 7840 static int 7841 sysctl_hw_sched(SYSCTL_HANDLER_ARGS) 7842 { 7843 struct adapter *sc = arg1; 7844 struct sbuf *sb; 7845 int rc, i; 7846 unsigned int map, kbps, ipg, mode; 7847 unsigned int pace_tab[NTX_SCHED]; 7848 7849 rc = sysctl_wire_old_buffer(req, 0); 7850 if (rc != 0) 7851 return (rc); 7852 7853 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7854 if (sb == NULL) 7855 return (ENOMEM); 7856 7857 map = t4_read_reg(sc, A_TP_TX_MOD_QUEUE_REQ_MAP); 7858 mode = G_TIMERMODE(t4_read_reg(sc, A_TP_MOD_CONFIG)); 7859 t4_read_pace_tbl(sc, pace_tab); 7860 7861 sbuf_printf(sb, "Scheduler Mode Channel Rate (Kbps) " 7862 "Class IPG (0.1 ns) Flow IPG (us)"); 7863 7864 for (i = 0; i < NTX_SCHED; ++i, map >>= 2) { 7865 t4_get_tx_sched(sc, i, &kbps, &ipg, 1); 7866 sbuf_printf(sb, "\n %u %-5s %u ", i, 7867 (mode & (1 << i)) ? "flow" : "class", map & 3); 7868 if (kbps) 7869 sbuf_printf(sb, "%9u ", kbps); 7870 else 7871 sbuf_printf(sb, " disabled "); 7872 7873 if (ipg) 7874 sbuf_printf(sb, "%13u ", ipg); 7875 else 7876 sbuf_printf(sb, " disabled "); 7877 7878 if (pace_tab[i]) 7879 sbuf_printf(sb, "%10u", pace_tab[i]); 7880 else 7881 sbuf_printf(sb, " disabled"); 7882 } 7883 7884 rc = sbuf_finish(sb); 7885 sbuf_delete(sb); 7886 7887 return (rc); 7888 } 7889 7890 static int 7891 sysctl_lb_stats(SYSCTL_HANDLER_ARGS) 7892 { 7893 struct adapter *sc = arg1; 7894 struct sbuf *sb; 7895 int rc, i, j; 7896 uint64_t *p0, *p1; 7897 struct lb_port_stats s[2]; 7898 static const char *stat_name[] = { 7899 "OctetsOK:", "FramesOK:", "BcastFrames:", "McastFrames:", 7900 "UcastFrames:", "ErrorFrames:", "Frames64:", "Frames65To127:", 7901 "Frames128To255:", "Frames256To511:", "Frames512To1023:", 7902 "Frames1024To1518:", "Frames1519ToMax:", "FramesDropped:", 7903 "BG0FramesDropped:", "BG1FramesDropped:", "BG2FramesDropped:", 7904 "BG3FramesDropped:", "BG0FramesTrunc:", "BG1FramesTrunc:", 7905 "BG2FramesTrunc:", "BG3FramesTrunc:" 7906 }; 7907 7908 rc = sysctl_wire_old_buffer(req, 0); 7909 if (rc != 0) 7910 return (rc); 7911 7912 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7913 if (sb == NULL) 7914 return (ENOMEM); 7915 7916 memset(s, 0, sizeof(s)); 7917 7918 for (i = 0; i < sc->chip_params->nchan; i += 2) { 7919 t4_get_lb_stats(sc, i, &s[0]); 7920 t4_get_lb_stats(sc, i + 1, &s[1]); 7921 7922 p0 = &s[0].octets; 7923 p1 = &s[1].octets; 7924 sbuf_printf(sb, "%s Loopback %u" 7925 " Loopback %u", i == 0 ? "" : "\n", i, i + 1); 7926 7927 for (j = 0; j < nitems(stat_name); j++) 7928 sbuf_printf(sb, "\n%-17s %20ju %20ju", stat_name[j], 7929 *p0++, *p1++); 7930 } 7931 7932 rc = sbuf_finish(sb); 7933 sbuf_delete(sb); 7934 7935 return (rc); 7936 } 7937 7938 static int 7939 sysctl_linkdnrc(SYSCTL_HANDLER_ARGS) 7940 { 7941 int rc = 0; 7942 struct port_info *pi = arg1; 7943 struct link_config *lc = &pi->link_cfg; 7944 struct sbuf *sb; 7945 7946 rc = sysctl_wire_old_buffer(req, 0); 7947 if (rc != 0) 7948 return(rc); 7949 sb = sbuf_new_for_sysctl(NULL, NULL, 64, req); 7950 if (sb == NULL) 7951 return (ENOMEM); 7952 7953 if (lc->link_ok || lc->link_down_rc == 255) 7954 sbuf_printf(sb, "n/a"); 7955 else 7956 sbuf_printf(sb, "%s", t4_link_down_rc_str(lc->link_down_rc)); 7957 7958 rc = sbuf_finish(sb); 7959 sbuf_delete(sb); 7960 7961 return (rc); 7962 } 7963 7964 struct mem_desc { 7965 unsigned int base; 7966 unsigned int limit; 7967 unsigned int idx; 7968 }; 7969 7970 static int 7971 mem_desc_cmp(const void *a, const void *b) 7972 { 7973 return ((const struct mem_desc *)a)->base - 7974 ((const struct mem_desc *)b)->base; 7975 } 7976 7977 static void 7978 mem_region_show(struct sbuf *sb, const char *name, unsigned int from, 7979 unsigned int to) 7980 { 7981 unsigned int size; 7982 7983 if (from == to) 7984 return; 7985 7986 size = to - from + 1; 7987 if (size == 0) 7988 return; 7989 7990 /* XXX: need humanize_number(3) in libkern for a more readable 'size' */ 7991 sbuf_printf(sb, "%-15s %#x-%#x [%u]\n", name, from, to, size); 7992 } 7993 7994 static int 7995 sysctl_meminfo(SYSCTL_HANDLER_ARGS) 7996 { 7997 struct adapter *sc = arg1; 7998 struct sbuf *sb; 7999 int rc, i, n; 8000 uint32_t lo, hi, used, alloc; 8001 static const char *memory[] = {"EDC0:", "EDC1:", "MC:", "MC0:", "MC1:"}; 8002 static const char *region[] = { 8003 "DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:", 8004 "Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:", 8005 "Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:", 8006 "TDDP region:", "TPT region:", "STAG region:", "RQ region:", 8007 "RQUDP region:", "PBL region:", "TXPBL region:", 8008 "DBVFIFO region:", "ULPRX state:", "ULPTX state:", 8009 "On-chip queues:", "TLS keys:", 8010 }; 8011 struct mem_desc avail[4]; 8012 struct mem_desc mem[nitems(region) + 3]; /* up to 3 holes */ 8013 struct mem_desc *md = mem; 8014 8015 rc = sysctl_wire_old_buffer(req, 0); 8016 if (rc != 0) 8017 return (rc); 8018 8019 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8020 if (sb == NULL) 8021 return (ENOMEM); 8022 8023 for (i = 0; i < nitems(mem); i++) { 8024 mem[i].limit = 0; 8025 mem[i].idx = i; 8026 } 8027 8028 /* Find and sort the populated memory ranges */ 8029 i = 0; 8030 lo = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 8031 if (lo & F_EDRAM0_ENABLE) { 8032 hi = t4_read_reg(sc, A_MA_EDRAM0_BAR); 8033 avail[i].base = G_EDRAM0_BASE(hi) << 20; 8034 avail[i].limit = avail[i].base + (G_EDRAM0_SIZE(hi) << 20); 8035 avail[i].idx = 0; 8036 i++; 8037 } 8038 if (lo & F_EDRAM1_ENABLE) { 8039 hi = t4_read_reg(sc, A_MA_EDRAM1_BAR); 8040 avail[i].base = G_EDRAM1_BASE(hi) << 20; 8041 avail[i].limit = avail[i].base + (G_EDRAM1_SIZE(hi) << 20); 8042 avail[i].idx = 1; 8043 i++; 8044 } 8045 if (lo & F_EXT_MEM_ENABLE) { 8046 hi = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 8047 avail[i].base = G_EXT_MEM_BASE(hi) << 20; 8048 avail[i].limit = avail[i].base + 8049 (G_EXT_MEM_SIZE(hi) << 20); 8050 avail[i].idx = is_t5(sc) ? 3 : 2; /* Call it MC0 for T5 */ 8051 i++; 8052 } 8053 if (is_t5(sc) && lo & F_EXT_MEM1_ENABLE) { 8054 hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 8055 avail[i].base = G_EXT_MEM1_BASE(hi) << 20; 8056 avail[i].limit = avail[i].base + 8057 (G_EXT_MEM1_SIZE(hi) << 20); 8058 avail[i].idx = 4; 8059 i++; 8060 } 8061 if (!i) /* no memory available */ 8062 return 0; 8063 qsort(avail, i, sizeof(struct mem_desc), mem_desc_cmp); 8064 8065 (md++)->base = t4_read_reg(sc, A_SGE_DBQ_CTXT_BADDR); 8066 (md++)->base = t4_read_reg(sc, A_SGE_IMSG_CTXT_BADDR); 8067 (md++)->base = t4_read_reg(sc, A_SGE_FLM_CACHE_BADDR); 8068 (md++)->base = t4_read_reg(sc, A_TP_CMM_TCB_BASE); 8069 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_BASE); 8070 (md++)->base = t4_read_reg(sc, A_TP_CMM_TIMER_BASE); 8071 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_RX_FLST_BASE); 8072 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_TX_FLST_BASE); 8073 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_PS_FLST_BASE); 8074 8075 /* the next few have explicit upper bounds */ 8076 md->base = t4_read_reg(sc, A_TP_PMM_TX_BASE); 8077 md->limit = md->base - 1 + 8078 t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE) * 8079 G_PMTXMAXPAGE(t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE)); 8080 md++; 8081 8082 md->base = t4_read_reg(sc, A_TP_PMM_RX_BASE); 8083 md->limit = md->base - 1 + 8084 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) * 8085 G_PMRXMAXPAGE(t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE)); 8086 md++; 8087 8088 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) { 8089 if (chip_id(sc) <= CHELSIO_T5) 8090 md->base = t4_read_reg(sc, A_LE_DB_HASH_TID_BASE); 8091 else 8092 md->base = t4_read_reg(sc, A_LE_DB_HASH_TBL_BASE_ADDR); 8093 md->limit = 0; 8094 } else { 8095 md->base = 0; 8096 md->idx = nitems(region); /* hide it */ 8097 } 8098 md++; 8099 8100 #define ulp_region(reg) \ 8101 md->base = t4_read_reg(sc, A_ULP_ ## reg ## _LLIMIT);\ 8102 (md++)->limit = t4_read_reg(sc, A_ULP_ ## reg ## _ULIMIT) 8103 8104 ulp_region(RX_ISCSI); 8105 ulp_region(RX_TDDP); 8106 ulp_region(TX_TPT); 8107 ulp_region(RX_STAG); 8108 ulp_region(RX_RQ); 8109 ulp_region(RX_RQUDP); 8110 ulp_region(RX_PBL); 8111 ulp_region(TX_PBL); 8112 #undef ulp_region 8113 8114 md->base = 0; 8115 md->idx = nitems(region); 8116 if (!is_t4(sc)) { 8117 uint32_t size = 0; 8118 uint32_t sge_ctrl = t4_read_reg(sc, A_SGE_CONTROL2); 8119 uint32_t fifo_size = t4_read_reg(sc, A_SGE_DBVFIFO_SIZE); 8120 8121 if (is_t5(sc)) { 8122 if (sge_ctrl & F_VFIFO_ENABLE) 8123 size = G_DBVFIFO_SIZE(fifo_size); 8124 } else 8125 size = G_T6_DBVFIFO_SIZE(fifo_size); 8126 8127 if (size) { 8128 md->base = G_BASEADDR(t4_read_reg(sc, 8129 A_SGE_DBVFIFO_BADDR)); 8130 md->limit = md->base + (size << 2) - 1; 8131 } 8132 } 8133 md++; 8134 8135 md->base = t4_read_reg(sc, A_ULP_RX_CTX_BASE); 8136 md->limit = 0; 8137 md++; 8138 md->base = t4_read_reg(sc, A_ULP_TX_ERR_TABLE_BASE); 8139 md->limit = 0; 8140 md++; 8141 8142 md->base = sc->vres.ocq.start; 8143 if (sc->vres.ocq.size) 8144 md->limit = md->base + sc->vres.ocq.size - 1; 8145 else 8146 md->idx = nitems(region); /* hide it */ 8147 md++; 8148 8149 md->base = sc->vres.key.start; 8150 if (sc->vres.key.size) 8151 md->limit = md->base + sc->vres.key.size - 1; 8152 else 8153 md->idx = nitems(region); /* hide it */ 8154 md++; 8155 8156 /* add any address-space holes, there can be up to 3 */ 8157 for (n = 0; n < i - 1; n++) 8158 if (avail[n].limit < avail[n + 1].base) 8159 (md++)->base = avail[n].limit; 8160 if (avail[n].limit) 8161 (md++)->base = avail[n].limit; 8162 8163 n = md - mem; 8164 qsort(mem, n, sizeof(struct mem_desc), mem_desc_cmp); 8165 8166 for (lo = 0; lo < i; lo++) 8167 mem_region_show(sb, memory[avail[lo].idx], avail[lo].base, 8168 avail[lo].limit - 1); 8169 8170 sbuf_printf(sb, "\n"); 8171 for (i = 0; i < n; i++) { 8172 if (mem[i].idx >= nitems(region)) 8173 continue; /* skip holes */ 8174 if (!mem[i].limit) 8175 mem[i].limit = i < n - 1 ? mem[i + 1].base - 1 : ~0; 8176 mem_region_show(sb, region[mem[i].idx], mem[i].base, 8177 mem[i].limit); 8178 } 8179 8180 sbuf_printf(sb, "\n"); 8181 lo = t4_read_reg(sc, A_CIM_SDRAM_BASE_ADDR); 8182 hi = t4_read_reg(sc, A_CIM_SDRAM_ADDR_SIZE) + lo - 1; 8183 mem_region_show(sb, "uP RAM:", lo, hi); 8184 8185 lo = t4_read_reg(sc, A_CIM_EXTMEM2_BASE_ADDR); 8186 hi = t4_read_reg(sc, A_CIM_EXTMEM2_ADDR_SIZE) + lo - 1; 8187 mem_region_show(sb, "uP Extmem2:", lo, hi); 8188 8189 lo = t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE); 8190 sbuf_printf(sb, "\n%u Rx pages of size %uKiB for %u channels\n", 8191 G_PMRXMAXPAGE(lo), 8192 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) >> 10, 8193 (lo & F_PMRXNUMCHN) ? 2 : 1); 8194 8195 lo = t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE); 8196 hi = t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE); 8197 sbuf_printf(sb, "%u Tx pages of size %u%ciB for %u channels\n", 8198 G_PMTXMAXPAGE(lo), 8199 hi >= (1 << 20) ? (hi >> 20) : (hi >> 10), 8200 hi >= (1 << 20) ? 'M' : 'K', 1 << G_PMTXNUMCHN(lo)); 8201 sbuf_printf(sb, "%u p-structs\n", 8202 t4_read_reg(sc, A_TP_CMM_MM_MAX_PSTRUCT)); 8203 8204 for (i = 0; i < 4; i++) { 8205 if (chip_id(sc) > CHELSIO_T5) 8206 lo = t4_read_reg(sc, A_MPS_RX_MAC_BG_PG_CNT0 + i * 4); 8207 else 8208 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV0 + i * 4); 8209 if (is_t5(sc)) { 8210 used = G_T5_USED(lo); 8211 alloc = G_T5_ALLOC(lo); 8212 } else { 8213 used = G_USED(lo); 8214 alloc = G_ALLOC(lo); 8215 } 8216 /* For T6 these are MAC buffer groups */ 8217 sbuf_printf(sb, "\nPort %d using %u pages out of %u allocated", 8218 i, used, alloc); 8219 } 8220 for (i = 0; i < sc->chip_params->nchan; i++) { 8221 if (chip_id(sc) > CHELSIO_T5) 8222 lo = t4_read_reg(sc, A_MPS_RX_LPBK_BG_PG_CNT0 + i * 4); 8223 else 8224 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV4 + i * 4); 8225 if (is_t5(sc)) { 8226 used = G_T5_USED(lo); 8227 alloc = G_T5_ALLOC(lo); 8228 } else { 8229 used = G_USED(lo); 8230 alloc = G_ALLOC(lo); 8231 } 8232 /* For T6 these are MAC buffer groups */ 8233 sbuf_printf(sb, 8234 "\nLoopback %d using %u pages out of %u allocated", 8235 i, used, alloc); 8236 } 8237 8238 rc = sbuf_finish(sb); 8239 sbuf_delete(sb); 8240 8241 return (rc); 8242 } 8243 8244 static inline void 8245 tcamxy2valmask(uint64_t x, uint64_t y, uint8_t *addr, uint64_t *mask) 8246 { 8247 *mask = x | y; 8248 y = htobe64(y); 8249 memcpy(addr, (char *)&y + 2, ETHER_ADDR_LEN); 8250 } 8251 8252 static int 8253 sysctl_mps_tcam(SYSCTL_HANDLER_ARGS) 8254 { 8255 struct adapter *sc = arg1; 8256 struct sbuf *sb; 8257 int rc, i; 8258 8259 MPASS(chip_id(sc) <= CHELSIO_T5); 8260 8261 rc = sysctl_wire_old_buffer(req, 0); 8262 if (rc != 0) 8263 return (rc); 8264 8265 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8266 if (sb == NULL) 8267 return (ENOMEM); 8268 8269 sbuf_printf(sb, 8270 "Idx Ethernet address Mask Vld Ports PF" 8271 " VF Replication P0 P1 P2 P3 ML"); 8272 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) { 8273 uint64_t tcamx, tcamy, mask; 8274 uint32_t cls_lo, cls_hi; 8275 uint8_t addr[ETHER_ADDR_LEN]; 8276 8277 tcamy = t4_read_reg64(sc, MPS_CLS_TCAM_Y_L(i)); 8278 tcamx = t4_read_reg64(sc, MPS_CLS_TCAM_X_L(i)); 8279 if (tcamx & tcamy) 8280 continue; 8281 tcamxy2valmask(tcamx, tcamy, addr, &mask); 8282 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i)); 8283 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i)); 8284 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x %012jx" 8285 " %c %#x%4u%4d", i, addr[0], addr[1], addr[2], 8286 addr[3], addr[4], addr[5], (uintmax_t)mask, 8287 (cls_lo & F_SRAM_VLD) ? 'Y' : 'N', 8288 G_PORTMAP(cls_hi), G_PF(cls_lo), 8289 (cls_lo & F_VF_VALID) ? G_VF(cls_lo) : -1); 8290 8291 if (cls_lo & F_REPLICATE) { 8292 struct fw_ldst_cmd ldst_cmd; 8293 8294 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 8295 ldst_cmd.op_to_addrspace = 8296 htobe32(V_FW_CMD_OP(FW_LDST_CMD) | 8297 F_FW_CMD_REQUEST | F_FW_CMD_READ | 8298 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS)); 8299 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd)); 8300 ldst_cmd.u.mps.rplc.fid_idx = 8301 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) | 8302 V_FW_LDST_CMD_IDX(i)); 8303 8304 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, 8305 "t4mps"); 8306 if (rc) 8307 break; 8308 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd, 8309 sizeof(ldst_cmd), &ldst_cmd); 8310 end_synchronized_op(sc, 0); 8311 8312 if (rc != 0) { 8313 sbuf_printf(sb, "%36d", rc); 8314 rc = 0; 8315 } else { 8316 sbuf_printf(sb, " %08x %08x %08x %08x", 8317 be32toh(ldst_cmd.u.mps.rplc.rplc127_96), 8318 be32toh(ldst_cmd.u.mps.rplc.rplc95_64), 8319 be32toh(ldst_cmd.u.mps.rplc.rplc63_32), 8320 be32toh(ldst_cmd.u.mps.rplc.rplc31_0)); 8321 } 8322 } else 8323 sbuf_printf(sb, "%36s", ""); 8324 8325 sbuf_printf(sb, "%4u%3u%3u%3u %#3x", G_SRAM_PRIO0(cls_lo), 8326 G_SRAM_PRIO1(cls_lo), G_SRAM_PRIO2(cls_lo), 8327 G_SRAM_PRIO3(cls_lo), (cls_lo >> S_MULTILISTEN0) & 0xf); 8328 } 8329 8330 if (rc) 8331 (void) sbuf_finish(sb); 8332 else 8333 rc = sbuf_finish(sb); 8334 sbuf_delete(sb); 8335 8336 return (rc); 8337 } 8338 8339 static int 8340 sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS) 8341 { 8342 struct adapter *sc = arg1; 8343 struct sbuf *sb; 8344 int rc, i; 8345 8346 MPASS(chip_id(sc) > CHELSIO_T5); 8347 8348 rc = sysctl_wire_old_buffer(req, 0); 8349 if (rc != 0) 8350 return (rc); 8351 8352 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8353 if (sb == NULL) 8354 return (ENOMEM); 8355 8356 sbuf_printf(sb, "Idx Ethernet address Mask VNI Mask" 8357 " IVLAN Vld DIP_Hit Lookup Port Vld Ports PF VF" 8358 " Replication" 8359 " P0 P1 P2 P3 ML\n"); 8360 8361 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) { 8362 uint8_t dip_hit, vlan_vld, lookup_type, port_num; 8363 uint16_t ivlan; 8364 uint64_t tcamx, tcamy, val, mask; 8365 uint32_t cls_lo, cls_hi, ctl, data2, vnix, vniy; 8366 uint8_t addr[ETHER_ADDR_LEN]; 8367 8368 ctl = V_CTLREQID(1) | V_CTLCMDTYPE(0) | V_CTLXYBITSEL(0); 8369 if (i < 256) 8370 ctl |= V_CTLTCAMINDEX(i) | V_CTLTCAMSEL(0); 8371 else 8372 ctl |= V_CTLTCAMINDEX(i - 256) | V_CTLTCAMSEL(1); 8373 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl); 8374 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1); 8375 tcamy = G_DMACH(val) << 32; 8376 tcamy |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1); 8377 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1); 8378 lookup_type = G_DATALKPTYPE(data2); 8379 port_num = G_DATAPORTNUM(data2); 8380 if (lookup_type && lookup_type != M_DATALKPTYPE) { 8381 /* Inner header VNI */ 8382 vniy = ((data2 & F_DATAVIDH2) << 23) | 8383 (G_DATAVIDH1(data2) << 16) | G_VIDL(val); 8384 dip_hit = data2 & F_DATADIPHIT; 8385 vlan_vld = 0; 8386 } else { 8387 vniy = 0; 8388 dip_hit = 0; 8389 vlan_vld = data2 & F_DATAVIDH2; 8390 ivlan = G_VIDL(val); 8391 } 8392 8393 ctl |= V_CTLXYBITSEL(1); 8394 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl); 8395 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1); 8396 tcamx = G_DMACH(val) << 32; 8397 tcamx |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1); 8398 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1); 8399 if (lookup_type && lookup_type != M_DATALKPTYPE) { 8400 /* Inner header VNI mask */ 8401 vnix = ((data2 & F_DATAVIDH2) << 23) | 8402 (G_DATAVIDH1(data2) << 16) | G_VIDL(val); 8403 } else 8404 vnix = 0; 8405 8406 if (tcamx & tcamy) 8407 continue; 8408 tcamxy2valmask(tcamx, tcamy, addr, &mask); 8409 8410 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i)); 8411 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i)); 8412 8413 if (lookup_type && lookup_type != M_DATALKPTYPE) { 8414 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x " 8415 "%012jx %06x %06x - - %3c" 8416 " 'I' %4x %3c %#x%4u%4d", i, addr[0], 8417 addr[1], addr[2], addr[3], addr[4], addr[5], 8418 (uintmax_t)mask, vniy, vnix, dip_hit ? 'Y' : 'N', 8419 port_num, cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N', 8420 G_PORTMAP(cls_hi), G_T6_PF(cls_lo), 8421 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1); 8422 } else { 8423 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x " 8424 "%012jx - - ", i, addr[0], addr[1], 8425 addr[2], addr[3], addr[4], addr[5], 8426 (uintmax_t)mask); 8427 8428 if (vlan_vld) 8429 sbuf_printf(sb, "%4u Y ", ivlan); 8430 else 8431 sbuf_printf(sb, " - N "); 8432 8433 sbuf_printf(sb, "- %3c %4x %3c %#x%4u%4d", 8434 lookup_type ? 'I' : 'O', port_num, 8435 cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N', 8436 G_PORTMAP(cls_hi), G_T6_PF(cls_lo), 8437 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1); 8438 } 8439 8440 8441 if (cls_lo & F_T6_REPLICATE) { 8442 struct fw_ldst_cmd ldst_cmd; 8443 8444 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 8445 ldst_cmd.op_to_addrspace = 8446 htobe32(V_FW_CMD_OP(FW_LDST_CMD) | 8447 F_FW_CMD_REQUEST | F_FW_CMD_READ | 8448 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS)); 8449 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd)); 8450 ldst_cmd.u.mps.rplc.fid_idx = 8451 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) | 8452 V_FW_LDST_CMD_IDX(i)); 8453 8454 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, 8455 "t6mps"); 8456 if (rc) 8457 break; 8458 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd, 8459 sizeof(ldst_cmd), &ldst_cmd); 8460 end_synchronized_op(sc, 0); 8461 8462 if (rc != 0) { 8463 sbuf_printf(sb, "%72d", rc); 8464 rc = 0; 8465 } else { 8466 sbuf_printf(sb, " %08x %08x %08x %08x" 8467 " %08x %08x %08x %08x", 8468 be32toh(ldst_cmd.u.mps.rplc.rplc255_224), 8469 be32toh(ldst_cmd.u.mps.rplc.rplc223_192), 8470 be32toh(ldst_cmd.u.mps.rplc.rplc191_160), 8471 be32toh(ldst_cmd.u.mps.rplc.rplc159_128), 8472 be32toh(ldst_cmd.u.mps.rplc.rplc127_96), 8473 be32toh(ldst_cmd.u.mps.rplc.rplc95_64), 8474 be32toh(ldst_cmd.u.mps.rplc.rplc63_32), 8475 be32toh(ldst_cmd.u.mps.rplc.rplc31_0)); 8476 } 8477 } else 8478 sbuf_printf(sb, "%72s", ""); 8479 8480 sbuf_printf(sb, "%4u%3u%3u%3u %#x", 8481 G_T6_SRAM_PRIO0(cls_lo), G_T6_SRAM_PRIO1(cls_lo), 8482 G_T6_SRAM_PRIO2(cls_lo), G_T6_SRAM_PRIO3(cls_lo), 8483 (cls_lo >> S_T6_MULTILISTEN0) & 0xf); 8484 } 8485 8486 if (rc) 8487 (void) sbuf_finish(sb); 8488 else 8489 rc = sbuf_finish(sb); 8490 sbuf_delete(sb); 8491 8492 return (rc); 8493 } 8494 8495 static int 8496 sysctl_path_mtus(SYSCTL_HANDLER_ARGS) 8497 { 8498 struct adapter *sc = arg1; 8499 struct sbuf *sb; 8500 int rc; 8501 uint16_t mtus[NMTUS]; 8502 8503 rc = sysctl_wire_old_buffer(req, 0); 8504 if (rc != 0) 8505 return (rc); 8506 8507 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 8508 if (sb == NULL) 8509 return (ENOMEM); 8510 8511 t4_read_mtu_tbl(sc, mtus, NULL); 8512 8513 sbuf_printf(sb, "%u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u", 8514 mtus[0], mtus[1], mtus[2], mtus[3], mtus[4], mtus[5], mtus[6], 8515 mtus[7], mtus[8], mtus[9], mtus[10], mtus[11], mtus[12], mtus[13], 8516 mtus[14], mtus[15]); 8517 8518 rc = sbuf_finish(sb); 8519 sbuf_delete(sb); 8520 8521 return (rc); 8522 } 8523 8524 static int 8525 sysctl_pm_stats(SYSCTL_HANDLER_ARGS) 8526 { 8527 struct adapter *sc = arg1; 8528 struct sbuf *sb; 8529 int rc, i; 8530 uint32_t tx_cnt[MAX_PM_NSTATS], rx_cnt[MAX_PM_NSTATS]; 8531 uint64_t tx_cyc[MAX_PM_NSTATS], rx_cyc[MAX_PM_NSTATS]; 8532 static const char *tx_stats[MAX_PM_NSTATS] = { 8533 "Read:", "Write bypass:", "Write mem:", "Bypass + mem:", 8534 "Tx FIFO wait", NULL, "Tx latency" 8535 }; 8536 static const char *rx_stats[MAX_PM_NSTATS] = { 8537 "Read:", "Write bypass:", "Write mem:", "Flush:", 8538 "Rx FIFO wait", NULL, "Rx latency" 8539 }; 8540 8541 rc = sysctl_wire_old_buffer(req, 0); 8542 if (rc != 0) 8543 return (rc); 8544 8545 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 8546 if (sb == NULL) 8547 return (ENOMEM); 8548 8549 t4_pmtx_get_stats(sc, tx_cnt, tx_cyc); 8550 t4_pmrx_get_stats(sc, rx_cnt, rx_cyc); 8551 8552 sbuf_printf(sb, " Tx pcmds Tx bytes"); 8553 for (i = 0; i < 4; i++) { 8554 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 8555 tx_cyc[i]); 8556 } 8557 8558 sbuf_printf(sb, "\n Rx pcmds Rx bytes"); 8559 for (i = 0; i < 4; i++) { 8560 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 8561 rx_cyc[i]); 8562 } 8563 8564 if (chip_id(sc) > CHELSIO_T5) { 8565 sbuf_printf(sb, 8566 "\n Total wait Total occupancy"); 8567 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 8568 tx_cyc[i]); 8569 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 8570 rx_cyc[i]); 8571 8572 i += 2; 8573 MPASS(i < nitems(tx_stats)); 8574 8575 sbuf_printf(sb, 8576 "\n Reads Total wait"); 8577 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 8578 tx_cyc[i]); 8579 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 8580 rx_cyc[i]); 8581 } 8582 8583 rc = sbuf_finish(sb); 8584 sbuf_delete(sb); 8585 8586 return (rc); 8587 } 8588 8589 static int 8590 sysctl_rdma_stats(SYSCTL_HANDLER_ARGS) 8591 { 8592 struct adapter *sc = arg1; 8593 struct sbuf *sb; 8594 int rc; 8595 struct tp_rdma_stats stats; 8596 8597 rc = sysctl_wire_old_buffer(req, 0); 8598 if (rc != 0) 8599 return (rc); 8600 8601 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 8602 if (sb == NULL) 8603 return (ENOMEM); 8604 8605 mtx_lock(&sc->reg_lock); 8606 t4_tp_get_rdma_stats(sc, &stats, 0); 8607 mtx_unlock(&sc->reg_lock); 8608 8609 sbuf_printf(sb, "NoRQEModDefferals: %u\n", stats.rqe_dfr_mod); 8610 sbuf_printf(sb, "NoRQEPktDefferals: %u", stats.rqe_dfr_pkt); 8611 8612 rc = sbuf_finish(sb); 8613 sbuf_delete(sb); 8614 8615 return (rc); 8616 } 8617 8618 static int 8619 sysctl_tcp_stats(SYSCTL_HANDLER_ARGS) 8620 { 8621 struct adapter *sc = arg1; 8622 struct sbuf *sb; 8623 int rc; 8624 struct tp_tcp_stats v4, v6; 8625 8626 rc = sysctl_wire_old_buffer(req, 0); 8627 if (rc != 0) 8628 return (rc); 8629 8630 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 8631 if (sb == NULL) 8632 return (ENOMEM); 8633 8634 mtx_lock(&sc->reg_lock); 8635 t4_tp_get_tcp_stats(sc, &v4, &v6, 0); 8636 mtx_unlock(&sc->reg_lock); 8637 8638 sbuf_printf(sb, 8639 " IP IPv6\n"); 8640 sbuf_printf(sb, "OutRsts: %20u %20u\n", 8641 v4.tcp_out_rsts, v6.tcp_out_rsts); 8642 sbuf_printf(sb, "InSegs: %20ju %20ju\n", 8643 v4.tcp_in_segs, v6.tcp_in_segs); 8644 sbuf_printf(sb, "OutSegs: %20ju %20ju\n", 8645 v4.tcp_out_segs, v6.tcp_out_segs); 8646 sbuf_printf(sb, "RetransSegs: %20ju %20ju", 8647 v4.tcp_retrans_segs, v6.tcp_retrans_segs); 8648 8649 rc = sbuf_finish(sb); 8650 sbuf_delete(sb); 8651 8652 return (rc); 8653 } 8654 8655 static int 8656 sysctl_tids(SYSCTL_HANDLER_ARGS) 8657 { 8658 struct adapter *sc = arg1; 8659 struct sbuf *sb; 8660 int rc; 8661 struct tid_info *t = &sc->tids; 8662 8663 rc = sysctl_wire_old_buffer(req, 0); 8664 if (rc != 0) 8665 return (rc); 8666 8667 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 8668 if (sb == NULL) 8669 return (ENOMEM); 8670 8671 if (t->natids) { 8672 sbuf_printf(sb, "ATID range: 0-%u, in use: %u\n", t->natids - 1, 8673 t->atids_in_use); 8674 } 8675 8676 if (t->nhpftids) { 8677 sbuf_printf(sb, "HPFTID range: %u-%u, in use: %u\n", 8678 t->hpftid_base, t->hpftid_end, t->hpftids_in_use); 8679 } 8680 8681 if (t->ntids) { 8682 sbuf_printf(sb, "TID range: "); 8683 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) { 8684 uint32_t b, hb; 8685 8686 if (chip_id(sc) <= CHELSIO_T5) { 8687 b = t4_read_reg(sc, A_LE_DB_SERVER_INDEX) / 4; 8688 hb = t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4; 8689 } else { 8690 b = t4_read_reg(sc, A_LE_DB_SRVR_START_INDEX); 8691 hb = t4_read_reg(sc, A_T6_LE_DB_HASH_TID_BASE); 8692 } 8693 8694 if (b) 8695 sbuf_printf(sb, "%u-%u, ", t->tid_base, b - 1); 8696 sbuf_printf(sb, "%u-%u", hb, t->ntids - 1); 8697 } else 8698 sbuf_printf(sb, "%u-%u", t->tid_base, t->ntids - 1); 8699 sbuf_printf(sb, ", in use: %u\n", 8700 atomic_load_acq_int(&t->tids_in_use)); 8701 } 8702 8703 if (t->nstids) { 8704 sbuf_printf(sb, "STID range: %u-%u, in use: %u\n", t->stid_base, 8705 t->stid_base + t->nstids - 1, t->stids_in_use); 8706 } 8707 8708 if (t->nftids) { 8709 sbuf_printf(sb, "FTID range: %u-%u, in use: %u\n", t->ftid_base, 8710 t->ftid_end, t->ftids_in_use); 8711 } 8712 8713 if (t->netids) { 8714 sbuf_printf(sb, "ETID range: %u-%u, in use: %u\n", t->etid_base, 8715 t->etid_base + t->netids - 1, t->etids_in_use); 8716 } 8717 8718 sbuf_printf(sb, "HW TID usage: %u IP users, %u IPv6 users", 8719 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV4), 8720 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV6)); 8721 8722 rc = sbuf_finish(sb); 8723 sbuf_delete(sb); 8724 8725 return (rc); 8726 } 8727 8728 static int 8729 sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS) 8730 { 8731 struct adapter *sc = arg1; 8732 struct sbuf *sb; 8733 int rc; 8734 struct tp_err_stats stats; 8735 8736 rc = sysctl_wire_old_buffer(req, 0); 8737 if (rc != 0) 8738 return (rc); 8739 8740 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 8741 if (sb == NULL) 8742 return (ENOMEM); 8743 8744 mtx_lock(&sc->reg_lock); 8745 t4_tp_get_err_stats(sc, &stats, 0); 8746 mtx_unlock(&sc->reg_lock); 8747 8748 if (sc->chip_params->nchan > 2) { 8749 sbuf_printf(sb, " channel 0 channel 1" 8750 " channel 2 channel 3\n"); 8751 sbuf_printf(sb, "macInErrs: %10u %10u %10u %10u\n", 8752 stats.mac_in_errs[0], stats.mac_in_errs[1], 8753 stats.mac_in_errs[2], stats.mac_in_errs[3]); 8754 sbuf_printf(sb, "hdrInErrs: %10u %10u %10u %10u\n", 8755 stats.hdr_in_errs[0], stats.hdr_in_errs[1], 8756 stats.hdr_in_errs[2], stats.hdr_in_errs[3]); 8757 sbuf_printf(sb, "tcpInErrs: %10u %10u %10u %10u\n", 8758 stats.tcp_in_errs[0], stats.tcp_in_errs[1], 8759 stats.tcp_in_errs[2], stats.tcp_in_errs[3]); 8760 sbuf_printf(sb, "tcp6InErrs: %10u %10u %10u %10u\n", 8761 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1], 8762 stats.tcp6_in_errs[2], stats.tcp6_in_errs[3]); 8763 sbuf_printf(sb, "tnlCongDrops: %10u %10u %10u %10u\n", 8764 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1], 8765 stats.tnl_cong_drops[2], stats.tnl_cong_drops[3]); 8766 sbuf_printf(sb, "tnlTxDrops: %10u %10u %10u %10u\n", 8767 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1], 8768 stats.tnl_tx_drops[2], stats.tnl_tx_drops[3]); 8769 sbuf_printf(sb, "ofldVlanDrops: %10u %10u %10u %10u\n", 8770 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1], 8771 stats.ofld_vlan_drops[2], stats.ofld_vlan_drops[3]); 8772 sbuf_printf(sb, "ofldChanDrops: %10u %10u %10u %10u\n\n", 8773 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1], 8774 stats.ofld_chan_drops[2], stats.ofld_chan_drops[3]); 8775 } else { 8776 sbuf_printf(sb, " channel 0 channel 1\n"); 8777 sbuf_printf(sb, "macInErrs: %10u %10u\n", 8778 stats.mac_in_errs[0], stats.mac_in_errs[1]); 8779 sbuf_printf(sb, "hdrInErrs: %10u %10u\n", 8780 stats.hdr_in_errs[0], stats.hdr_in_errs[1]); 8781 sbuf_printf(sb, "tcpInErrs: %10u %10u\n", 8782 stats.tcp_in_errs[0], stats.tcp_in_errs[1]); 8783 sbuf_printf(sb, "tcp6InErrs: %10u %10u\n", 8784 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1]); 8785 sbuf_printf(sb, "tnlCongDrops: %10u %10u\n", 8786 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1]); 8787 sbuf_printf(sb, "tnlTxDrops: %10u %10u\n", 8788 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1]); 8789 sbuf_printf(sb, "ofldVlanDrops: %10u %10u\n", 8790 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1]); 8791 sbuf_printf(sb, "ofldChanDrops: %10u %10u\n\n", 8792 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1]); 8793 } 8794 8795 sbuf_printf(sb, "ofldNoNeigh: %u\nofldCongDefer: %u", 8796 stats.ofld_no_neigh, stats.ofld_cong_defer); 8797 8798 rc = sbuf_finish(sb); 8799 sbuf_delete(sb); 8800 8801 return (rc); 8802 } 8803 8804 static int 8805 sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS) 8806 { 8807 struct adapter *sc = arg1; 8808 struct tp_params *tpp = &sc->params.tp; 8809 u_int mask; 8810 int rc; 8811 8812 mask = tpp->la_mask >> 16; 8813 rc = sysctl_handle_int(oidp, &mask, 0, req); 8814 if (rc != 0 || req->newptr == NULL) 8815 return (rc); 8816 if (mask > 0xffff) 8817 return (EINVAL); 8818 tpp->la_mask = mask << 16; 8819 t4_set_reg_field(sc, A_TP_DBG_LA_CONFIG, 0xffff0000U, tpp->la_mask); 8820 8821 return (0); 8822 } 8823 8824 struct field_desc { 8825 const char *name; 8826 u_int start; 8827 u_int width; 8828 }; 8829 8830 static void 8831 field_desc_show(struct sbuf *sb, uint64_t v, const struct field_desc *f) 8832 { 8833 char buf[32]; 8834 int line_size = 0; 8835 8836 while (f->name) { 8837 uint64_t mask = (1ULL << f->width) - 1; 8838 int len = snprintf(buf, sizeof(buf), "%s: %ju", f->name, 8839 ((uintmax_t)v >> f->start) & mask); 8840 8841 if (line_size + len >= 79) { 8842 line_size = 8; 8843 sbuf_printf(sb, "\n "); 8844 } 8845 sbuf_printf(sb, "%s ", buf); 8846 line_size += len + 1; 8847 f++; 8848 } 8849 sbuf_printf(sb, "\n"); 8850 } 8851 8852 static const struct field_desc tp_la0[] = { 8853 { "RcfOpCodeOut", 60, 4 }, 8854 { "State", 56, 4 }, 8855 { "WcfState", 52, 4 }, 8856 { "RcfOpcSrcOut", 50, 2 }, 8857 { "CRxError", 49, 1 }, 8858 { "ERxError", 48, 1 }, 8859 { "SanityFailed", 47, 1 }, 8860 { "SpuriousMsg", 46, 1 }, 8861 { "FlushInputMsg", 45, 1 }, 8862 { "FlushInputCpl", 44, 1 }, 8863 { "RssUpBit", 43, 1 }, 8864 { "RssFilterHit", 42, 1 }, 8865 { "Tid", 32, 10 }, 8866 { "InitTcb", 31, 1 }, 8867 { "LineNumber", 24, 7 }, 8868 { "Emsg", 23, 1 }, 8869 { "EdataOut", 22, 1 }, 8870 { "Cmsg", 21, 1 }, 8871 { "CdataOut", 20, 1 }, 8872 { "EreadPdu", 19, 1 }, 8873 { "CreadPdu", 18, 1 }, 8874 { "TunnelPkt", 17, 1 }, 8875 { "RcfPeerFin", 16, 1 }, 8876 { "RcfReasonOut", 12, 4 }, 8877 { "TxCchannel", 10, 2 }, 8878 { "RcfTxChannel", 8, 2 }, 8879 { "RxEchannel", 6, 2 }, 8880 { "RcfRxChannel", 5, 1 }, 8881 { "RcfDataOutSrdy", 4, 1 }, 8882 { "RxDvld", 3, 1 }, 8883 { "RxOoDvld", 2, 1 }, 8884 { "RxCongestion", 1, 1 }, 8885 { "TxCongestion", 0, 1 }, 8886 { NULL } 8887 }; 8888 8889 static const struct field_desc tp_la1[] = { 8890 { "CplCmdIn", 56, 8 }, 8891 { "CplCmdOut", 48, 8 }, 8892 { "ESynOut", 47, 1 }, 8893 { "EAckOut", 46, 1 }, 8894 { "EFinOut", 45, 1 }, 8895 { "ERstOut", 44, 1 }, 8896 { "SynIn", 43, 1 }, 8897 { "AckIn", 42, 1 }, 8898 { "FinIn", 41, 1 }, 8899 { "RstIn", 40, 1 }, 8900 { "DataIn", 39, 1 }, 8901 { "DataInVld", 38, 1 }, 8902 { "PadIn", 37, 1 }, 8903 { "RxBufEmpty", 36, 1 }, 8904 { "RxDdp", 35, 1 }, 8905 { "RxFbCongestion", 34, 1 }, 8906 { "TxFbCongestion", 33, 1 }, 8907 { "TxPktSumSrdy", 32, 1 }, 8908 { "RcfUlpType", 28, 4 }, 8909 { "Eread", 27, 1 }, 8910 { "Ebypass", 26, 1 }, 8911 { "Esave", 25, 1 }, 8912 { "Static0", 24, 1 }, 8913 { "Cread", 23, 1 }, 8914 { "Cbypass", 22, 1 }, 8915 { "Csave", 21, 1 }, 8916 { "CPktOut", 20, 1 }, 8917 { "RxPagePoolFull", 18, 2 }, 8918 { "RxLpbkPkt", 17, 1 }, 8919 { "TxLpbkPkt", 16, 1 }, 8920 { "RxVfValid", 15, 1 }, 8921 { "SynLearned", 14, 1 }, 8922 { "SetDelEntry", 13, 1 }, 8923 { "SetInvEntry", 12, 1 }, 8924 { "CpcmdDvld", 11, 1 }, 8925 { "CpcmdSave", 10, 1 }, 8926 { "RxPstructsFull", 8, 2 }, 8927 { "EpcmdDvld", 7, 1 }, 8928 { "EpcmdFlush", 6, 1 }, 8929 { "EpcmdTrimPrefix", 5, 1 }, 8930 { "EpcmdTrimPostfix", 4, 1 }, 8931 { "ERssIp4Pkt", 3, 1 }, 8932 { "ERssIp6Pkt", 2, 1 }, 8933 { "ERssTcpUdpPkt", 1, 1 }, 8934 { "ERssFceFipPkt", 0, 1 }, 8935 { NULL } 8936 }; 8937 8938 static const struct field_desc tp_la2[] = { 8939 { "CplCmdIn", 56, 8 }, 8940 { "MpsVfVld", 55, 1 }, 8941 { "MpsPf", 52, 3 }, 8942 { "MpsVf", 44, 8 }, 8943 { "SynIn", 43, 1 }, 8944 { "AckIn", 42, 1 }, 8945 { "FinIn", 41, 1 }, 8946 { "RstIn", 40, 1 }, 8947 { "DataIn", 39, 1 }, 8948 { "DataInVld", 38, 1 }, 8949 { "PadIn", 37, 1 }, 8950 { "RxBufEmpty", 36, 1 }, 8951 { "RxDdp", 35, 1 }, 8952 { "RxFbCongestion", 34, 1 }, 8953 { "TxFbCongestion", 33, 1 }, 8954 { "TxPktSumSrdy", 32, 1 }, 8955 { "RcfUlpType", 28, 4 }, 8956 { "Eread", 27, 1 }, 8957 { "Ebypass", 26, 1 }, 8958 { "Esave", 25, 1 }, 8959 { "Static0", 24, 1 }, 8960 { "Cread", 23, 1 }, 8961 { "Cbypass", 22, 1 }, 8962 { "Csave", 21, 1 }, 8963 { "CPktOut", 20, 1 }, 8964 { "RxPagePoolFull", 18, 2 }, 8965 { "RxLpbkPkt", 17, 1 }, 8966 { "TxLpbkPkt", 16, 1 }, 8967 { "RxVfValid", 15, 1 }, 8968 { "SynLearned", 14, 1 }, 8969 { "SetDelEntry", 13, 1 }, 8970 { "SetInvEntry", 12, 1 }, 8971 { "CpcmdDvld", 11, 1 }, 8972 { "CpcmdSave", 10, 1 }, 8973 { "RxPstructsFull", 8, 2 }, 8974 { "EpcmdDvld", 7, 1 }, 8975 { "EpcmdFlush", 6, 1 }, 8976 { "EpcmdTrimPrefix", 5, 1 }, 8977 { "EpcmdTrimPostfix", 4, 1 }, 8978 { "ERssIp4Pkt", 3, 1 }, 8979 { "ERssIp6Pkt", 2, 1 }, 8980 { "ERssTcpUdpPkt", 1, 1 }, 8981 { "ERssFceFipPkt", 0, 1 }, 8982 { NULL } 8983 }; 8984 8985 static void 8986 tp_la_show(struct sbuf *sb, uint64_t *p, int idx) 8987 { 8988 8989 field_desc_show(sb, *p, tp_la0); 8990 } 8991 8992 static void 8993 tp_la_show2(struct sbuf *sb, uint64_t *p, int idx) 8994 { 8995 8996 if (idx) 8997 sbuf_printf(sb, "\n"); 8998 field_desc_show(sb, p[0], tp_la0); 8999 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL) 9000 field_desc_show(sb, p[1], tp_la0); 9001 } 9002 9003 static void 9004 tp_la_show3(struct sbuf *sb, uint64_t *p, int idx) 9005 { 9006 9007 if (idx) 9008 sbuf_printf(sb, "\n"); 9009 field_desc_show(sb, p[0], tp_la0); 9010 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL) 9011 field_desc_show(sb, p[1], (p[0] & (1 << 17)) ? tp_la2 : tp_la1); 9012 } 9013 9014 static int 9015 sysctl_tp_la(SYSCTL_HANDLER_ARGS) 9016 { 9017 struct adapter *sc = arg1; 9018 struct sbuf *sb; 9019 uint64_t *buf, *p; 9020 int rc; 9021 u_int i, inc; 9022 void (*show_func)(struct sbuf *, uint64_t *, int); 9023 9024 rc = sysctl_wire_old_buffer(req, 0); 9025 if (rc != 0) 9026 return (rc); 9027 9028 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9029 if (sb == NULL) 9030 return (ENOMEM); 9031 9032 buf = malloc(TPLA_SIZE * sizeof(uint64_t), M_CXGBE, M_ZERO | M_WAITOK); 9033 9034 t4_tp_read_la(sc, buf, NULL); 9035 p = buf; 9036 9037 switch (G_DBGLAMODE(t4_read_reg(sc, A_TP_DBG_LA_CONFIG))) { 9038 case 2: 9039 inc = 2; 9040 show_func = tp_la_show2; 9041 break; 9042 case 3: 9043 inc = 2; 9044 show_func = tp_la_show3; 9045 break; 9046 default: 9047 inc = 1; 9048 show_func = tp_la_show; 9049 } 9050 9051 for (i = 0; i < TPLA_SIZE / inc; i++, p += inc) 9052 (*show_func)(sb, p, i); 9053 9054 rc = sbuf_finish(sb); 9055 sbuf_delete(sb); 9056 free(buf, M_CXGBE); 9057 return (rc); 9058 } 9059 9060 static int 9061 sysctl_tx_rate(SYSCTL_HANDLER_ARGS) 9062 { 9063 struct adapter *sc = arg1; 9064 struct sbuf *sb; 9065 int rc; 9066 u64 nrate[MAX_NCHAN], orate[MAX_NCHAN]; 9067 9068 rc = sysctl_wire_old_buffer(req, 0); 9069 if (rc != 0) 9070 return (rc); 9071 9072 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 9073 if (sb == NULL) 9074 return (ENOMEM); 9075 9076 t4_get_chan_txrate(sc, nrate, orate); 9077 9078 if (sc->chip_params->nchan > 2) { 9079 sbuf_printf(sb, " channel 0 channel 1" 9080 " channel 2 channel 3\n"); 9081 sbuf_printf(sb, "NIC B/s: %10ju %10ju %10ju %10ju\n", 9082 nrate[0], nrate[1], nrate[2], nrate[3]); 9083 sbuf_printf(sb, "Offload B/s: %10ju %10ju %10ju %10ju", 9084 orate[0], orate[1], orate[2], orate[3]); 9085 } else { 9086 sbuf_printf(sb, " channel 0 channel 1\n"); 9087 sbuf_printf(sb, "NIC B/s: %10ju %10ju\n", 9088 nrate[0], nrate[1]); 9089 sbuf_printf(sb, "Offload B/s: %10ju %10ju", 9090 orate[0], orate[1]); 9091 } 9092 9093 rc = sbuf_finish(sb); 9094 sbuf_delete(sb); 9095 9096 return (rc); 9097 } 9098 9099 static int 9100 sysctl_ulprx_la(SYSCTL_HANDLER_ARGS) 9101 { 9102 struct adapter *sc = arg1; 9103 struct sbuf *sb; 9104 uint32_t *buf, *p; 9105 int rc, i; 9106 9107 rc = sysctl_wire_old_buffer(req, 0); 9108 if (rc != 0) 9109 return (rc); 9110 9111 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9112 if (sb == NULL) 9113 return (ENOMEM); 9114 9115 buf = malloc(ULPRX_LA_SIZE * 8 * sizeof(uint32_t), M_CXGBE, 9116 M_ZERO | M_WAITOK); 9117 9118 t4_ulprx_read_la(sc, buf); 9119 p = buf; 9120 9121 sbuf_printf(sb, " Pcmd Type Message" 9122 " Data"); 9123 for (i = 0; i < ULPRX_LA_SIZE; i++, p += 8) { 9124 sbuf_printf(sb, "\n%08x%08x %4x %08x %08x%08x%08x%08x", 9125 p[1], p[0], p[2], p[3], p[7], p[6], p[5], p[4]); 9126 } 9127 9128 rc = sbuf_finish(sb); 9129 sbuf_delete(sb); 9130 free(buf, M_CXGBE); 9131 return (rc); 9132 } 9133 9134 static int 9135 sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS) 9136 { 9137 struct adapter *sc = arg1; 9138 struct sbuf *sb; 9139 int rc, v; 9140 9141 MPASS(chip_id(sc) >= CHELSIO_T5); 9142 9143 rc = sysctl_wire_old_buffer(req, 0); 9144 if (rc != 0) 9145 return (rc); 9146 9147 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9148 if (sb == NULL) 9149 return (ENOMEM); 9150 9151 v = t4_read_reg(sc, A_SGE_STAT_CFG); 9152 if (G_STATSOURCE_T5(v) == 7) { 9153 int mode; 9154 9155 mode = is_t5(sc) ? G_STATMODE(v) : G_T6_STATMODE(v); 9156 if (mode == 0) { 9157 sbuf_printf(sb, "total %d, incomplete %d", 9158 t4_read_reg(sc, A_SGE_STAT_TOTAL), 9159 t4_read_reg(sc, A_SGE_STAT_MATCH)); 9160 } else if (mode == 1) { 9161 sbuf_printf(sb, "total %d, data overflow %d", 9162 t4_read_reg(sc, A_SGE_STAT_TOTAL), 9163 t4_read_reg(sc, A_SGE_STAT_MATCH)); 9164 } else { 9165 sbuf_printf(sb, "unknown mode %d", mode); 9166 } 9167 } 9168 rc = sbuf_finish(sb); 9169 sbuf_delete(sb); 9170 9171 return (rc); 9172 } 9173 9174 static int 9175 sysctl_cpus(SYSCTL_HANDLER_ARGS) 9176 { 9177 struct adapter *sc = arg1; 9178 enum cpu_sets op = arg2; 9179 cpuset_t cpuset; 9180 struct sbuf *sb; 9181 int i, rc; 9182 9183 MPASS(op == LOCAL_CPUS || op == INTR_CPUS); 9184 9185 CPU_ZERO(&cpuset); 9186 rc = bus_get_cpus(sc->dev, op, sizeof(cpuset), &cpuset); 9187 if (rc != 0) 9188 return (rc); 9189 9190 rc = sysctl_wire_old_buffer(req, 0); 9191 if (rc != 0) 9192 return (rc); 9193 9194 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 9195 if (sb == NULL) 9196 return (ENOMEM); 9197 9198 CPU_FOREACH(i) 9199 sbuf_printf(sb, "%d ", i); 9200 rc = sbuf_finish(sb); 9201 sbuf_delete(sb); 9202 9203 return (rc); 9204 } 9205 9206 #ifdef TCP_OFFLOAD 9207 static int 9208 sysctl_tls_rx_ports(SYSCTL_HANDLER_ARGS) 9209 { 9210 struct adapter *sc = arg1; 9211 int *old_ports, *new_ports; 9212 int i, new_count, rc; 9213 9214 if (req->newptr == NULL && req->oldptr == NULL) 9215 return (SYSCTL_OUT(req, NULL, imax(sc->tt.num_tls_rx_ports, 1) * 9216 sizeof(sc->tt.tls_rx_ports[0]))); 9217 9218 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4tlsrx"); 9219 if (rc) 9220 return (rc); 9221 9222 if (sc->tt.num_tls_rx_ports == 0) { 9223 i = -1; 9224 rc = SYSCTL_OUT(req, &i, sizeof(i)); 9225 } else 9226 rc = SYSCTL_OUT(req, sc->tt.tls_rx_ports, 9227 sc->tt.num_tls_rx_ports * sizeof(sc->tt.tls_rx_ports[0])); 9228 if (rc == 0 && req->newptr != NULL) { 9229 new_count = req->newlen / sizeof(new_ports[0]); 9230 new_ports = malloc(new_count * sizeof(new_ports[0]), M_CXGBE, 9231 M_WAITOK); 9232 rc = SYSCTL_IN(req, new_ports, new_count * 9233 sizeof(new_ports[0])); 9234 if (rc) 9235 goto err; 9236 9237 /* Allow setting to a single '-1' to clear the list. */ 9238 if (new_count == 1 && new_ports[0] == -1) { 9239 ADAPTER_LOCK(sc); 9240 old_ports = sc->tt.tls_rx_ports; 9241 sc->tt.tls_rx_ports = NULL; 9242 sc->tt.num_tls_rx_ports = 0; 9243 ADAPTER_UNLOCK(sc); 9244 free(old_ports, M_CXGBE); 9245 } else { 9246 for (i = 0; i < new_count; i++) { 9247 if (new_ports[i] < 1 || 9248 new_ports[i] > IPPORT_MAX) { 9249 rc = EINVAL; 9250 goto err; 9251 } 9252 } 9253 9254 ADAPTER_LOCK(sc); 9255 old_ports = sc->tt.tls_rx_ports; 9256 sc->tt.tls_rx_ports = new_ports; 9257 sc->tt.num_tls_rx_ports = new_count; 9258 ADAPTER_UNLOCK(sc); 9259 free(old_ports, M_CXGBE); 9260 new_ports = NULL; 9261 } 9262 err: 9263 free(new_ports, M_CXGBE); 9264 } 9265 end_synchronized_op(sc, 0); 9266 return (rc); 9267 } 9268 9269 static void 9270 unit_conv(char *buf, size_t len, u_int val, u_int factor) 9271 { 9272 u_int rem = val % factor; 9273 9274 if (rem == 0) 9275 snprintf(buf, len, "%u", val / factor); 9276 else { 9277 while (rem % 10 == 0) 9278 rem /= 10; 9279 snprintf(buf, len, "%u.%u", val / factor, rem); 9280 } 9281 } 9282 9283 static int 9284 sysctl_tp_tick(SYSCTL_HANDLER_ARGS) 9285 { 9286 struct adapter *sc = arg1; 9287 char buf[16]; 9288 u_int res, re; 9289 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 9290 9291 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION); 9292 switch (arg2) { 9293 case 0: 9294 /* timer_tick */ 9295 re = G_TIMERRESOLUTION(res); 9296 break; 9297 case 1: 9298 /* TCP timestamp tick */ 9299 re = G_TIMESTAMPRESOLUTION(res); 9300 break; 9301 case 2: 9302 /* DACK tick */ 9303 re = G_DELAYEDACKRESOLUTION(res); 9304 break; 9305 default: 9306 return (EDOOFUS); 9307 } 9308 9309 unit_conv(buf, sizeof(buf), (cclk_ps << re), 1000000); 9310 9311 return (sysctl_handle_string(oidp, buf, sizeof(buf), req)); 9312 } 9313 9314 static int 9315 sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS) 9316 { 9317 struct adapter *sc = arg1; 9318 u_int res, dack_re, v; 9319 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 9320 9321 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION); 9322 dack_re = G_DELAYEDACKRESOLUTION(res); 9323 v = ((cclk_ps << dack_re) / 1000000) * t4_read_reg(sc, A_TP_DACK_TIMER); 9324 9325 return (sysctl_handle_int(oidp, &v, 0, req)); 9326 } 9327 9328 static int 9329 sysctl_tp_timer(SYSCTL_HANDLER_ARGS) 9330 { 9331 struct adapter *sc = arg1; 9332 int reg = arg2; 9333 u_int tre; 9334 u_long tp_tick_us, v; 9335 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 9336 9337 MPASS(reg == A_TP_RXT_MIN || reg == A_TP_RXT_MAX || 9338 reg == A_TP_PERS_MIN || reg == A_TP_PERS_MAX || 9339 reg == A_TP_KEEP_IDLE || reg == A_TP_KEEP_INTVL || 9340 reg == A_TP_INIT_SRTT || reg == A_TP_FINWAIT2_TIMER); 9341 9342 tre = G_TIMERRESOLUTION(t4_read_reg(sc, A_TP_TIMER_RESOLUTION)); 9343 tp_tick_us = (cclk_ps << tre) / 1000000; 9344 9345 if (reg == A_TP_INIT_SRTT) 9346 v = tp_tick_us * G_INITSRTT(t4_read_reg(sc, reg)); 9347 else 9348 v = tp_tick_us * t4_read_reg(sc, reg); 9349 9350 return (sysctl_handle_long(oidp, &v, 0, req)); 9351 } 9352 9353 /* 9354 * All fields in TP_SHIFT_CNT are 4b and the starting location of the field is 9355 * passed to this function. 9356 */ 9357 static int 9358 sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS) 9359 { 9360 struct adapter *sc = arg1; 9361 int idx = arg2; 9362 u_int v; 9363 9364 MPASS(idx >= 0 && idx <= 24); 9365 9366 v = (t4_read_reg(sc, A_TP_SHIFT_CNT) >> idx) & 0xf; 9367 9368 return (sysctl_handle_int(oidp, &v, 0, req)); 9369 } 9370 9371 static int 9372 sysctl_tp_backoff(SYSCTL_HANDLER_ARGS) 9373 { 9374 struct adapter *sc = arg1; 9375 int idx = arg2; 9376 u_int shift, v, r; 9377 9378 MPASS(idx >= 0 && idx < 16); 9379 9380 r = A_TP_TCP_BACKOFF_REG0 + (idx & ~3); 9381 shift = (idx & 3) << 3; 9382 v = (t4_read_reg(sc, r) >> shift) & M_TIMERBACKOFFINDEX0; 9383 9384 return (sysctl_handle_int(oidp, &v, 0, req)); 9385 } 9386 9387 static int 9388 sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS) 9389 { 9390 struct vi_info *vi = arg1; 9391 struct adapter *sc = vi->pi->adapter; 9392 int idx, rc, i; 9393 struct sge_ofld_rxq *ofld_rxq; 9394 uint8_t v; 9395 9396 idx = vi->ofld_tmr_idx; 9397 9398 rc = sysctl_handle_int(oidp, &idx, 0, req); 9399 if (rc != 0 || req->newptr == NULL) 9400 return (rc); 9401 9402 if (idx < 0 || idx >= SGE_NTIMERS) 9403 return (EINVAL); 9404 9405 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 9406 "t4otmr"); 9407 if (rc) 9408 return (rc); 9409 9410 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->ofld_pktc_idx != -1); 9411 for_each_ofld_rxq(vi, i, ofld_rxq) { 9412 #ifdef atomic_store_rel_8 9413 atomic_store_rel_8(&ofld_rxq->iq.intr_params, v); 9414 #else 9415 ofld_rxq->iq.intr_params = v; 9416 #endif 9417 } 9418 vi->ofld_tmr_idx = idx; 9419 9420 end_synchronized_op(sc, LOCK_HELD); 9421 return (0); 9422 } 9423 9424 static int 9425 sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS) 9426 { 9427 struct vi_info *vi = arg1; 9428 struct adapter *sc = vi->pi->adapter; 9429 int idx, rc; 9430 9431 idx = vi->ofld_pktc_idx; 9432 9433 rc = sysctl_handle_int(oidp, &idx, 0, req); 9434 if (rc != 0 || req->newptr == NULL) 9435 return (rc); 9436 9437 if (idx < -1 || idx >= SGE_NCOUNTERS) 9438 return (EINVAL); 9439 9440 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 9441 "t4opktc"); 9442 if (rc) 9443 return (rc); 9444 9445 if (vi->flags & VI_INIT_DONE) 9446 rc = EBUSY; /* cannot be changed once the queues are created */ 9447 else 9448 vi->ofld_pktc_idx = idx; 9449 9450 end_synchronized_op(sc, LOCK_HELD); 9451 return (rc); 9452 } 9453 #endif 9454 9455 static int 9456 get_sge_context(struct adapter *sc, struct t4_sge_context *cntxt) 9457 { 9458 int rc; 9459 9460 if (cntxt->cid > M_CTXTQID) 9461 return (EINVAL); 9462 9463 if (cntxt->mem_id != CTXT_EGRESS && cntxt->mem_id != CTXT_INGRESS && 9464 cntxt->mem_id != CTXT_FLM && cntxt->mem_id != CTXT_CNM) 9465 return (EINVAL); 9466 9467 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ctxt"); 9468 if (rc) 9469 return (rc); 9470 9471 if (sc->flags & FW_OK) { 9472 rc = -t4_sge_ctxt_rd(sc, sc->mbox, cntxt->cid, cntxt->mem_id, 9473 &cntxt->data[0]); 9474 if (rc == 0) 9475 goto done; 9476 } 9477 9478 /* 9479 * Read via firmware failed or wasn't even attempted. Read directly via 9480 * the backdoor. 9481 */ 9482 rc = -t4_sge_ctxt_rd_bd(sc, cntxt->cid, cntxt->mem_id, &cntxt->data[0]); 9483 done: 9484 end_synchronized_op(sc, 0); 9485 return (rc); 9486 } 9487 9488 static int 9489 load_fw(struct adapter *sc, struct t4_data *fw) 9490 { 9491 int rc; 9492 uint8_t *fw_data; 9493 9494 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldfw"); 9495 if (rc) 9496 return (rc); 9497 9498 /* 9499 * The firmware, with the sole exception of the memory parity error 9500 * handler, runs from memory and not flash. It is almost always safe to 9501 * install a new firmware on a running system. Just set bit 1 in 9502 * hw.cxgbe.dflags or dev.<nexus>.<n>.dflags first. 9503 */ 9504 if (sc->flags & FULL_INIT_DONE && 9505 (sc->debug_flags & DF_LOAD_FW_ANYTIME) == 0) { 9506 rc = EBUSY; 9507 goto done; 9508 } 9509 9510 fw_data = malloc(fw->len, M_CXGBE, M_WAITOK); 9511 if (fw_data == NULL) { 9512 rc = ENOMEM; 9513 goto done; 9514 } 9515 9516 rc = copyin(fw->data, fw_data, fw->len); 9517 if (rc == 0) 9518 rc = -t4_load_fw(sc, fw_data, fw->len); 9519 9520 free(fw_data, M_CXGBE); 9521 done: 9522 end_synchronized_op(sc, 0); 9523 return (rc); 9524 } 9525 9526 static int 9527 load_cfg(struct adapter *sc, struct t4_data *cfg) 9528 { 9529 int rc; 9530 uint8_t *cfg_data = NULL; 9531 9532 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf"); 9533 if (rc) 9534 return (rc); 9535 9536 if (cfg->len == 0) { 9537 /* clear */ 9538 rc = -t4_load_cfg(sc, NULL, 0); 9539 goto done; 9540 } 9541 9542 cfg_data = malloc(cfg->len, M_CXGBE, M_WAITOK); 9543 if (cfg_data == NULL) { 9544 rc = ENOMEM; 9545 goto done; 9546 } 9547 9548 rc = copyin(cfg->data, cfg_data, cfg->len); 9549 if (rc == 0) 9550 rc = -t4_load_cfg(sc, cfg_data, cfg->len); 9551 9552 free(cfg_data, M_CXGBE); 9553 done: 9554 end_synchronized_op(sc, 0); 9555 return (rc); 9556 } 9557 9558 static int 9559 load_boot(struct adapter *sc, struct t4_bootrom *br) 9560 { 9561 int rc; 9562 uint8_t *br_data = NULL; 9563 u_int offset; 9564 9565 if (br->len > 1024 * 1024) 9566 return (EFBIG); 9567 9568 if (br->pf_offset == 0) { 9569 /* pfidx */ 9570 if (br->pfidx_addr > 7) 9571 return (EINVAL); 9572 offset = G_OFFSET(t4_read_reg(sc, PF_REG(br->pfidx_addr, 9573 A_PCIE_PF_EXPROM_OFST))); 9574 } else if (br->pf_offset == 1) { 9575 /* offset */ 9576 offset = G_OFFSET(br->pfidx_addr); 9577 } else { 9578 return (EINVAL); 9579 } 9580 9581 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldbr"); 9582 if (rc) 9583 return (rc); 9584 9585 if (br->len == 0) { 9586 /* clear */ 9587 rc = -t4_load_boot(sc, NULL, offset, 0); 9588 goto done; 9589 } 9590 9591 br_data = malloc(br->len, M_CXGBE, M_WAITOK); 9592 if (br_data == NULL) { 9593 rc = ENOMEM; 9594 goto done; 9595 } 9596 9597 rc = copyin(br->data, br_data, br->len); 9598 if (rc == 0) 9599 rc = -t4_load_boot(sc, br_data, offset, br->len); 9600 9601 free(br_data, M_CXGBE); 9602 done: 9603 end_synchronized_op(sc, 0); 9604 return (rc); 9605 } 9606 9607 static int 9608 load_bootcfg(struct adapter *sc, struct t4_data *bc) 9609 { 9610 int rc; 9611 uint8_t *bc_data = NULL; 9612 9613 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf"); 9614 if (rc) 9615 return (rc); 9616 9617 if (bc->len == 0) { 9618 /* clear */ 9619 rc = -t4_load_bootcfg(sc, NULL, 0); 9620 goto done; 9621 } 9622 9623 bc_data = malloc(bc->len, M_CXGBE, M_WAITOK); 9624 if (bc_data == NULL) { 9625 rc = ENOMEM; 9626 goto done; 9627 } 9628 9629 rc = copyin(bc->data, bc_data, bc->len); 9630 if (rc == 0) 9631 rc = -t4_load_bootcfg(sc, bc_data, bc->len); 9632 9633 free(bc_data, M_CXGBE); 9634 done: 9635 end_synchronized_op(sc, 0); 9636 return (rc); 9637 } 9638 9639 static int 9640 cudbg_dump(struct adapter *sc, struct t4_cudbg_dump *dump) 9641 { 9642 int rc; 9643 struct cudbg_init *cudbg; 9644 void *handle, *buf; 9645 9646 /* buf is large, don't block if no memory is available */ 9647 buf = malloc(dump->len, M_CXGBE, M_NOWAIT | M_ZERO); 9648 if (buf == NULL) 9649 return (ENOMEM); 9650 9651 handle = cudbg_alloc_handle(); 9652 if (handle == NULL) { 9653 rc = ENOMEM; 9654 goto done; 9655 } 9656 9657 cudbg = cudbg_get_init(handle); 9658 cudbg->adap = sc; 9659 cudbg->print = (cudbg_print_cb)printf; 9660 9661 #ifndef notyet 9662 device_printf(sc->dev, "%s: wr_flash %u, len %u, data %p.\n", 9663 __func__, dump->wr_flash, dump->len, dump->data); 9664 #endif 9665 9666 if (dump->wr_flash) 9667 cudbg->use_flash = 1; 9668 MPASS(sizeof(cudbg->dbg_bitmap) == sizeof(dump->bitmap)); 9669 memcpy(cudbg->dbg_bitmap, dump->bitmap, sizeof(cudbg->dbg_bitmap)); 9670 9671 rc = cudbg_collect(handle, buf, &dump->len); 9672 if (rc != 0) 9673 goto done; 9674 9675 rc = copyout(buf, dump->data, dump->len); 9676 done: 9677 cudbg_free_handle(handle); 9678 free(buf, M_CXGBE); 9679 return (rc); 9680 } 9681 9682 static void 9683 free_offload_policy(struct t4_offload_policy *op) 9684 { 9685 struct offload_rule *r; 9686 int i; 9687 9688 if (op == NULL) 9689 return; 9690 9691 r = &op->rule[0]; 9692 for (i = 0; i < op->nrules; i++, r++) { 9693 free(r->bpf_prog.bf_insns, M_CXGBE); 9694 } 9695 free(op->rule, M_CXGBE); 9696 free(op, M_CXGBE); 9697 } 9698 9699 static int 9700 set_offload_policy(struct adapter *sc, struct t4_offload_policy *uop) 9701 { 9702 int i, rc, len; 9703 struct t4_offload_policy *op, *old; 9704 struct bpf_program *bf; 9705 const struct offload_settings *s; 9706 struct offload_rule *r; 9707 void *u; 9708 9709 if (!is_offload(sc)) 9710 return (ENODEV); 9711 9712 if (uop->nrules == 0) { 9713 /* Delete installed policies. */ 9714 op = NULL; 9715 goto set_policy; 9716 } if (uop->nrules > 256) { /* arbitrary */ 9717 return (E2BIG); 9718 } 9719 9720 /* Copy userspace offload policy to kernel */ 9721 op = malloc(sizeof(*op), M_CXGBE, M_ZERO | M_WAITOK); 9722 op->nrules = uop->nrules; 9723 len = op->nrules * sizeof(struct offload_rule); 9724 op->rule = malloc(len, M_CXGBE, M_ZERO | M_WAITOK); 9725 rc = copyin(uop->rule, op->rule, len); 9726 if (rc) { 9727 free(op->rule, M_CXGBE); 9728 free(op, M_CXGBE); 9729 return (rc); 9730 } 9731 9732 r = &op->rule[0]; 9733 for (i = 0; i < op->nrules; i++, r++) { 9734 9735 /* Validate open_type */ 9736 if (r->open_type != OPEN_TYPE_LISTEN && 9737 r->open_type != OPEN_TYPE_ACTIVE && 9738 r->open_type != OPEN_TYPE_PASSIVE && 9739 r->open_type != OPEN_TYPE_DONTCARE) { 9740 error: 9741 /* 9742 * Rules 0 to i have malloc'd filters that need to be 9743 * freed. Rules i+1 to nrules have userspace pointers 9744 * and should be left alone. 9745 */ 9746 op->nrules = i; 9747 free_offload_policy(op); 9748 return (rc); 9749 } 9750 9751 /* Validate settings */ 9752 s = &r->settings; 9753 if ((s->offload != 0 && s->offload != 1) || 9754 s->cong_algo < -1 || s->cong_algo > CONG_ALG_HIGHSPEED || 9755 s->sched_class < -1 || 9756 s->sched_class >= sc->chip_params->nsched_cls) { 9757 rc = EINVAL; 9758 goto error; 9759 } 9760 9761 bf = &r->bpf_prog; 9762 u = bf->bf_insns; /* userspace ptr */ 9763 bf->bf_insns = NULL; 9764 if (bf->bf_len == 0) { 9765 /* legal, matches everything */ 9766 continue; 9767 } 9768 len = bf->bf_len * sizeof(*bf->bf_insns); 9769 bf->bf_insns = malloc(len, M_CXGBE, M_ZERO | M_WAITOK); 9770 rc = copyin(u, bf->bf_insns, len); 9771 if (rc != 0) 9772 goto error; 9773 9774 if (!bpf_validate(bf->bf_insns, bf->bf_len)) { 9775 rc = EINVAL; 9776 goto error; 9777 } 9778 } 9779 set_policy: 9780 rw_wlock(&sc->policy_lock); 9781 old = sc->policy; 9782 sc->policy = op; 9783 rw_wunlock(&sc->policy_lock); 9784 free_offload_policy(old); 9785 9786 return (0); 9787 } 9788 9789 #define MAX_READ_BUF_SIZE (128 * 1024) 9790 static int 9791 read_card_mem(struct adapter *sc, int win, struct t4_mem_range *mr) 9792 { 9793 uint32_t addr, remaining, n; 9794 uint32_t *buf; 9795 int rc; 9796 uint8_t *dst; 9797 9798 rc = validate_mem_range(sc, mr->addr, mr->len); 9799 if (rc != 0) 9800 return (rc); 9801 9802 buf = malloc(min(mr->len, MAX_READ_BUF_SIZE), M_CXGBE, M_WAITOK); 9803 addr = mr->addr; 9804 remaining = mr->len; 9805 dst = (void *)mr->data; 9806 9807 while (remaining) { 9808 n = min(remaining, MAX_READ_BUF_SIZE); 9809 read_via_memwin(sc, 2, addr, buf, n); 9810 9811 rc = copyout(buf, dst, n); 9812 if (rc != 0) 9813 break; 9814 9815 dst += n; 9816 remaining -= n; 9817 addr += n; 9818 } 9819 9820 free(buf, M_CXGBE); 9821 return (rc); 9822 } 9823 #undef MAX_READ_BUF_SIZE 9824 9825 static int 9826 read_i2c(struct adapter *sc, struct t4_i2c_data *i2cd) 9827 { 9828 int rc; 9829 9830 if (i2cd->len == 0 || i2cd->port_id >= sc->params.nports) 9831 return (EINVAL); 9832 9833 if (i2cd->len > sizeof(i2cd->data)) 9834 return (EFBIG); 9835 9836 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4i2crd"); 9837 if (rc) 9838 return (rc); 9839 rc = -t4_i2c_rd(sc, sc->mbox, i2cd->port_id, i2cd->dev_addr, 9840 i2cd->offset, i2cd->len, &i2cd->data[0]); 9841 end_synchronized_op(sc, 0); 9842 9843 return (rc); 9844 } 9845 9846 int 9847 t4_os_find_pci_capability(struct adapter *sc, int cap) 9848 { 9849 int i; 9850 9851 return (pci_find_cap(sc->dev, cap, &i) == 0 ? i : 0); 9852 } 9853 9854 int 9855 t4_os_pci_save_state(struct adapter *sc) 9856 { 9857 device_t dev; 9858 struct pci_devinfo *dinfo; 9859 9860 dev = sc->dev; 9861 dinfo = device_get_ivars(dev); 9862 9863 pci_cfg_save(dev, dinfo, 0); 9864 return (0); 9865 } 9866 9867 int 9868 t4_os_pci_restore_state(struct adapter *sc) 9869 { 9870 device_t dev; 9871 struct pci_devinfo *dinfo; 9872 9873 dev = sc->dev; 9874 dinfo = device_get_ivars(dev); 9875 9876 pci_cfg_restore(dev, dinfo); 9877 return (0); 9878 } 9879 9880 void 9881 t4_os_portmod_changed(struct port_info *pi) 9882 { 9883 struct adapter *sc = pi->adapter; 9884 struct vi_info *vi; 9885 struct ifnet *ifp; 9886 static const char *mod_str[] = { 9887 NULL, "LR", "SR", "ER", "TWINAX", "active TWINAX", "LRM" 9888 }; 9889 9890 KASSERT((pi->flags & FIXED_IFMEDIA) == 0, 9891 ("%s: port_type %u", __func__, pi->port_type)); 9892 9893 vi = &pi->vi[0]; 9894 if (begin_synchronized_op(sc, vi, HOLD_LOCK, "t4mod") == 0) { 9895 PORT_LOCK(pi); 9896 build_medialist(pi); 9897 if (pi->mod_type != FW_PORT_MOD_TYPE_NONE) { 9898 fixup_link_config(pi); 9899 apply_link_config(pi); 9900 } 9901 PORT_UNLOCK(pi); 9902 end_synchronized_op(sc, LOCK_HELD); 9903 } 9904 9905 ifp = vi->ifp; 9906 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE) 9907 if_printf(ifp, "transceiver unplugged.\n"); 9908 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN) 9909 if_printf(ifp, "unknown transceiver inserted.\n"); 9910 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED) 9911 if_printf(ifp, "unsupported transceiver inserted.\n"); 9912 else if (pi->mod_type > 0 && pi->mod_type < nitems(mod_str)) { 9913 if_printf(ifp, "%dGbps %s transceiver inserted.\n", 9914 port_top_speed(pi), mod_str[pi->mod_type]); 9915 } else { 9916 if_printf(ifp, "transceiver (type %d) inserted.\n", 9917 pi->mod_type); 9918 } 9919 } 9920 9921 void 9922 t4_os_link_changed(struct port_info *pi) 9923 { 9924 struct vi_info *vi; 9925 struct ifnet *ifp; 9926 struct link_config *lc; 9927 int v; 9928 9929 PORT_LOCK_ASSERT_OWNED(pi); 9930 9931 for_each_vi(pi, v, vi) { 9932 ifp = vi->ifp; 9933 if (ifp == NULL) 9934 continue; 9935 9936 lc = &pi->link_cfg; 9937 if (lc->link_ok) { 9938 ifp->if_baudrate = IF_Mbps(lc->speed); 9939 if_link_state_change(ifp, LINK_STATE_UP); 9940 } else { 9941 if_link_state_change(ifp, LINK_STATE_DOWN); 9942 } 9943 } 9944 } 9945 9946 void 9947 t4_iterate(void (*func)(struct adapter *, void *), void *arg) 9948 { 9949 struct adapter *sc; 9950 9951 sx_slock(&t4_list_lock); 9952 SLIST_FOREACH(sc, &t4_list, link) { 9953 /* 9954 * func should not make any assumptions about what state sc is 9955 * in - the only guarantee is that sc->sc_lock is a valid lock. 9956 */ 9957 func(sc, arg); 9958 } 9959 sx_sunlock(&t4_list_lock); 9960 } 9961 9962 static int 9963 t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag, 9964 struct thread *td) 9965 { 9966 int rc; 9967 struct adapter *sc = dev->si_drv1; 9968 9969 rc = priv_check(td, PRIV_DRIVER); 9970 if (rc != 0) 9971 return (rc); 9972 9973 switch (cmd) { 9974 case CHELSIO_T4_GETREG: { 9975 struct t4_reg *edata = (struct t4_reg *)data; 9976 9977 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 9978 return (EFAULT); 9979 9980 if (edata->size == 4) 9981 edata->val = t4_read_reg(sc, edata->addr); 9982 else if (edata->size == 8) 9983 edata->val = t4_read_reg64(sc, edata->addr); 9984 else 9985 return (EINVAL); 9986 9987 break; 9988 } 9989 case CHELSIO_T4_SETREG: { 9990 struct t4_reg *edata = (struct t4_reg *)data; 9991 9992 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 9993 return (EFAULT); 9994 9995 if (edata->size == 4) { 9996 if (edata->val & 0xffffffff00000000) 9997 return (EINVAL); 9998 t4_write_reg(sc, edata->addr, (uint32_t) edata->val); 9999 } else if (edata->size == 8) 10000 t4_write_reg64(sc, edata->addr, edata->val); 10001 else 10002 return (EINVAL); 10003 break; 10004 } 10005 case CHELSIO_T4_REGDUMP: { 10006 struct t4_regdump *regs = (struct t4_regdump *)data; 10007 int reglen = t4_get_regs_len(sc); 10008 uint8_t *buf; 10009 10010 if (regs->len < reglen) { 10011 regs->len = reglen; /* hint to the caller */ 10012 return (ENOBUFS); 10013 } 10014 10015 regs->len = reglen; 10016 buf = malloc(reglen, M_CXGBE, M_WAITOK | M_ZERO); 10017 get_regs(sc, regs, buf); 10018 rc = copyout(buf, regs->data, reglen); 10019 free(buf, M_CXGBE); 10020 break; 10021 } 10022 case CHELSIO_T4_GET_FILTER_MODE: 10023 rc = get_filter_mode(sc, (uint32_t *)data); 10024 break; 10025 case CHELSIO_T4_SET_FILTER_MODE: 10026 rc = set_filter_mode(sc, *(uint32_t *)data); 10027 break; 10028 case CHELSIO_T4_GET_FILTER: 10029 rc = get_filter(sc, (struct t4_filter *)data); 10030 break; 10031 case CHELSIO_T4_SET_FILTER: 10032 rc = set_filter(sc, (struct t4_filter *)data); 10033 break; 10034 case CHELSIO_T4_DEL_FILTER: 10035 rc = del_filter(sc, (struct t4_filter *)data); 10036 break; 10037 case CHELSIO_T4_GET_SGE_CONTEXT: 10038 rc = get_sge_context(sc, (struct t4_sge_context *)data); 10039 break; 10040 case CHELSIO_T4_LOAD_FW: 10041 rc = load_fw(sc, (struct t4_data *)data); 10042 break; 10043 case CHELSIO_T4_GET_MEM: 10044 rc = read_card_mem(sc, 2, (struct t4_mem_range *)data); 10045 break; 10046 case CHELSIO_T4_GET_I2C: 10047 rc = read_i2c(sc, (struct t4_i2c_data *)data); 10048 break; 10049 case CHELSIO_T4_CLEAR_STATS: { 10050 int i, v, bg_map; 10051 u_int port_id = *(uint32_t *)data; 10052 struct port_info *pi; 10053 struct vi_info *vi; 10054 10055 if (port_id >= sc->params.nports) 10056 return (EINVAL); 10057 pi = sc->port[port_id]; 10058 if (pi == NULL) 10059 return (EIO); 10060 10061 /* MAC stats */ 10062 t4_clr_port_stats(sc, pi->tx_chan); 10063 pi->tx_parse_error = 0; 10064 pi->tnl_cong_drops = 0; 10065 mtx_lock(&sc->reg_lock); 10066 for_each_vi(pi, v, vi) { 10067 if (vi->flags & VI_INIT_DONE) 10068 t4_clr_vi_stats(sc, vi->vin); 10069 } 10070 bg_map = pi->mps_bg_map; 10071 v = 0; /* reuse */ 10072 while (bg_map) { 10073 i = ffs(bg_map) - 1; 10074 t4_write_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v, 10075 1, A_TP_MIB_TNL_CNG_DROP_0 + i); 10076 bg_map &= ~(1 << i); 10077 } 10078 mtx_unlock(&sc->reg_lock); 10079 10080 /* 10081 * Since this command accepts a port, clear stats for 10082 * all VIs on this port. 10083 */ 10084 for_each_vi(pi, v, vi) { 10085 if (vi->flags & VI_INIT_DONE) { 10086 struct sge_rxq *rxq; 10087 struct sge_txq *txq; 10088 struct sge_wrq *wrq; 10089 10090 for_each_rxq(vi, i, rxq) { 10091 #if defined(INET) || defined(INET6) 10092 rxq->lro.lro_queued = 0; 10093 rxq->lro.lro_flushed = 0; 10094 #endif 10095 rxq->rxcsum = 0; 10096 rxq->vlan_extraction = 0; 10097 } 10098 10099 for_each_txq(vi, i, txq) { 10100 txq->txcsum = 0; 10101 txq->tso_wrs = 0; 10102 txq->vlan_insertion = 0; 10103 txq->imm_wrs = 0; 10104 txq->sgl_wrs = 0; 10105 txq->txpkt_wrs = 0; 10106 txq->txpkts0_wrs = 0; 10107 txq->txpkts1_wrs = 0; 10108 txq->txpkts0_pkts = 0; 10109 txq->txpkts1_pkts = 0; 10110 txq->raw_wrs = 0; 10111 mp_ring_reset_stats(txq->r); 10112 } 10113 10114 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 10115 /* nothing to clear for each ofld_rxq */ 10116 10117 for_each_ofld_txq(vi, i, wrq) { 10118 wrq->tx_wrs_direct = 0; 10119 wrq->tx_wrs_copied = 0; 10120 } 10121 #endif 10122 10123 if (IS_MAIN_VI(vi)) { 10124 wrq = &sc->sge.ctrlq[pi->port_id]; 10125 wrq->tx_wrs_direct = 0; 10126 wrq->tx_wrs_copied = 0; 10127 } 10128 } 10129 } 10130 break; 10131 } 10132 case CHELSIO_T4_SCHED_CLASS: 10133 rc = t4_set_sched_class(sc, (struct t4_sched_params *)data); 10134 break; 10135 case CHELSIO_T4_SCHED_QUEUE: 10136 rc = t4_set_sched_queue(sc, (struct t4_sched_queue *)data); 10137 break; 10138 case CHELSIO_T4_GET_TRACER: 10139 rc = t4_get_tracer(sc, (struct t4_tracer *)data); 10140 break; 10141 case CHELSIO_T4_SET_TRACER: 10142 rc = t4_set_tracer(sc, (struct t4_tracer *)data); 10143 break; 10144 case CHELSIO_T4_LOAD_CFG: 10145 rc = load_cfg(sc, (struct t4_data *)data); 10146 break; 10147 case CHELSIO_T4_LOAD_BOOT: 10148 rc = load_boot(sc, (struct t4_bootrom *)data); 10149 break; 10150 case CHELSIO_T4_LOAD_BOOTCFG: 10151 rc = load_bootcfg(sc, (struct t4_data *)data); 10152 break; 10153 case CHELSIO_T4_CUDBG_DUMP: 10154 rc = cudbg_dump(sc, (struct t4_cudbg_dump *)data); 10155 break; 10156 case CHELSIO_T4_SET_OFLD_POLICY: 10157 rc = set_offload_policy(sc, (struct t4_offload_policy *)data); 10158 break; 10159 default: 10160 rc = ENOTTY; 10161 } 10162 10163 return (rc); 10164 } 10165 10166 #ifdef TCP_OFFLOAD 10167 static int 10168 toe_capability(struct vi_info *vi, int enable) 10169 { 10170 int rc; 10171 struct port_info *pi = vi->pi; 10172 struct adapter *sc = pi->adapter; 10173 10174 ASSERT_SYNCHRONIZED_OP(sc); 10175 10176 if (!is_offload(sc)) 10177 return (ENODEV); 10178 10179 if (enable) { 10180 if ((vi->ifp->if_capenable & IFCAP_TOE) != 0) { 10181 /* TOE is already enabled. */ 10182 return (0); 10183 } 10184 10185 /* 10186 * We need the port's queues around so that we're able to send 10187 * and receive CPLs to/from the TOE even if the ifnet for this 10188 * port has never been UP'd administratively. 10189 */ 10190 if (!(vi->flags & VI_INIT_DONE)) { 10191 rc = vi_full_init(vi); 10192 if (rc) 10193 return (rc); 10194 } 10195 if (!(pi->vi[0].flags & VI_INIT_DONE)) { 10196 rc = vi_full_init(&pi->vi[0]); 10197 if (rc) 10198 return (rc); 10199 } 10200 10201 if (isset(&sc->offload_map, pi->port_id)) { 10202 /* TOE is enabled on another VI of this port. */ 10203 pi->uld_vis++; 10204 return (0); 10205 } 10206 10207 if (!uld_active(sc, ULD_TOM)) { 10208 rc = t4_activate_uld(sc, ULD_TOM); 10209 if (rc == EAGAIN) { 10210 log(LOG_WARNING, 10211 "You must kldload t4_tom.ko before trying " 10212 "to enable TOE on a cxgbe interface.\n"); 10213 } 10214 if (rc != 0) 10215 return (rc); 10216 KASSERT(sc->tom_softc != NULL, 10217 ("%s: TOM activated but softc NULL", __func__)); 10218 KASSERT(uld_active(sc, ULD_TOM), 10219 ("%s: TOM activated but flag not set", __func__)); 10220 } 10221 10222 /* Activate iWARP and iSCSI too, if the modules are loaded. */ 10223 if (!uld_active(sc, ULD_IWARP)) 10224 (void) t4_activate_uld(sc, ULD_IWARP); 10225 if (!uld_active(sc, ULD_ISCSI)) 10226 (void) t4_activate_uld(sc, ULD_ISCSI); 10227 10228 pi->uld_vis++; 10229 setbit(&sc->offload_map, pi->port_id); 10230 } else { 10231 pi->uld_vis--; 10232 10233 if (!isset(&sc->offload_map, pi->port_id) || pi->uld_vis > 0) 10234 return (0); 10235 10236 KASSERT(uld_active(sc, ULD_TOM), 10237 ("%s: TOM never initialized?", __func__)); 10238 clrbit(&sc->offload_map, pi->port_id); 10239 } 10240 10241 return (0); 10242 } 10243 10244 /* 10245 * Add an upper layer driver to the global list. 10246 */ 10247 int 10248 t4_register_uld(struct uld_info *ui) 10249 { 10250 int rc = 0; 10251 struct uld_info *u; 10252 10253 sx_xlock(&t4_uld_list_lock); 10254 SLIST_FOREACH(u, &t4_uld_list, link) { 10255 if (u->uld_id == ui->uld_id) { 10256 rc = EEXIST; 10257 goto done; 10258 } 10259 } 10260 10261 SLIST_INSERT_HEAD(&t4_uld_list, ui, link); 10262 ui->refcount = 0; 10263 done: 10264 sx_xunlock(&t4_uld_list_lock); 10265 return (rc); 10266 } 10267 10268 int 10269 t4_unregister_uld(struct uld_info *ui) 10270 { 10271 int rc = EINVAL; 10272 struct uld_info *u; 10273 10274 sx_xlock(&t4_uld_list_lock); 10275 10276 SLIST_FOREACH(u, &t4_uld_list, link) { 10277 if (u == ui) { 10278 if (ui->refcount > 0) { 10279 rc = EBUSY; 10280 goto done; 10281 } 10282 10283 SLIST_REMOVE(&t4_uld_list, ui, uld_info, link); 10284 rc = 0; 10285 goto done; 10286 } 10287 } 10288 done: 10289 sx_xunlock(&t4_uld_list_lock); 10290 return (rc); 10291 } 10292 10293 int 10294 t4_activate_uld(struct adapter *sc, int id) 10295 { 10296 int rc; 10297 struct uld_info *ui; 10298 10299 ASSERT_SYNCHRONIZED_OP(sc); 10300 10301 if (id < 0 || id > ULD_MAX) 10302 return (EINVAL); 10303 rc = EAGAIN; /* kldoad the module with this ULD and try again. */ 10304 10305 sx_slock(&t4_uld_list_lock); 10306 10307 SLIST_FOREACH(ui, &t4_uld_list, link) { 10308 if (ui->uld_id == id) { 10309 if (!(sc->flags & FULL_INIT_DONE)) { 10310 rc = adapter_full_init(sc); 10311 if (rc != 0) 10312 break; 10313 } 10314 10315 rc = ui->activate(sc); 10316 if (rc == 0) { 10317 setbit(&sc->active_ulds, id); 10318 ui->refcount++; 10319 } 10320 break; 10321 } 10322 } 10323 10324 sx_sunlock(&t4_uld_list_lock); 10325 10326 return (rc); 10327 } 10328 10329 int 10330 t4_deactivate_uld(struct adapter *sc, int id) 10331 { 10332 int rc; 10333 struct uld_info *ui; 10334 10335 ASSERT_SYNCHRONIZED_OP(sc); 10336 10337 if (id < 0 || id > ULD_MAX) 10338 return (EINVAL); 10339 rc = ENXIO; 10340 10341 sx_slock(&t4_uld_list_lock); 10342 10343 SLIST_FOREACH(ui, &t4_uld_list, link) { 10344 if (ui->uld_id == id) { 10345 rc = ui->deactivate(sc); 10346 if (rc == 0) { 10347 clrbit(&sc->active_ulds, id); 10348 ui->refcount--; 10349 } 10350 break; 10351 } 10352 } 10353 10354 sx_sunlock(&t4_uld_list_lock); 10355 10356 return (rc); 10357 } 10358 10359 int 10360 uld_active(struct adapter *sc, int uld_id) 10361 { 10362 10363 MPASS(uld_id >= 0 && uld_id <= ULD_MAX); 10364 10365 return (isset(&sc->active_ulds, uld_id)); 10366 } 10367 #endif 10368 10369 /* 10370 * t = ptr to tunable. 10371 * nc = number of CPUs. 10372 * c = compiled in default for that tunable. 10373 */ 10374 static void 10375 calculate_nqueues(int *t, int nc, const int c) 10376 { 10377 int nq; 10378 10379 if (*t > 0) 10380 return; 10381 nq = *t < 0 ? -*t : c; 10382 *t = min(nc, nq); 10383 } 10384 10385 /* 10386 * Come up with reasonable defaults for some of the tunables, provided they're 10387 * not set by the user (in which case we'll use the values as is). 10388 */ 10389 static void 10390 tweak_tunables(void) 10391 { 10392 int nc = mp_ncpus; /* our snapshot of the number of CPUs */ 10393 10394 if (t4_ntxq < 1) { 10395 #ifdef RSS 10396 t4_ntxq = rss_getnumbuckets(); 10397 #else 10398 calculate_nqueues(&t4_ntxq, nc, NTXQ); 10399 #endif 10400 } 10401 10402 calculate_nqueues(&t4_ntxq_vi, nc, NTXQ_VI); 10403 10404 if (t4_nrxq < 1) { 10405 #ifdef RSS 10406 t4_nrxq = rss_getnumbuckets(); 10407 #else 10408 calculate_nqueues(&t4_nrxq, nc, NRXQ); 10409 #endif 10410 } 10411 10412 calculate_nqueues(&t4_nrxq_vi, nc, NRXQ_VI); 10413 10414 #if defined(TCP_OFFLOAD) || defined(RATELIMIT) 10415 calculate_nqueues(&t4_nofldtxq, nc, NOFLDTXQ); 10416 calculate_nqueues(&t4_nofldtxq_vi, nc, NOFLDTXQ_VI); 10417 #endif 10418 #ifdef TCP_OFFLOAD 10419 calculate_nqueues(&t4_nofldrxq, nc, NOFLDRXQ); 10420 calculate_nqueues(&t4_nofldrxq_vi, nc, NOFLDRXQ_VI); 10421 10422 if (t4_toecaps_allowed == -1) 10423 t4_toecaps_allowed = FW_CAPS_CONFIG_TOE; 10424 10425 if (t4_rdmacaps_allowed == -1) { 10426 t4_rdmacaps_allowed = FW_CAPS_CONFIG_RDMA_RDDP | 10427 FW_CAPS_CONFIG_RDMA_RDMAC; 10428 } 10429 10430 if (t4_iscsicaps_allowed == -1) { 10431 t4_iscsicaps_allowed = FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU | 10432 FW_CAPS_CONFIG_ISCSI_TARGET_PDU | 10433 FW_CAPS_CONFIG_ISCSI_T10DIF; 10434 } 10435 10436 if (t4_tmr_idx_ofld < 0 || t4_tmr_idx_ofld >= SGE_NTIMERS) 10437 t4_tmr_idx_ofld = TMR_IDX_OFLD; 10438 10439 if (t4_pktc_idx_ofld < -1 || t4_pktc_idx_ofld >= SGE_NCOUNTERS) 10440 t4_pktc_idx_ofld = PKTC_IDX_OFLD; 10441 #else 10442 if (t4_toecaps_allowed == -1) 10443 t4_toecaps_allowed = 0; 10444 10445 if (t4_rdmacaps_allowed == -1) 10446 t4_rdmacaps_allowed = 0; 10447 10448 if (t4_iscsicaps_allowed == -1) 10449 t4_iscsicaps_allowed = 0; 10450 #endif 10451 10452 #ifdef DEV_NETMAP 10453 calculate_nqueues(&t4_nnmtxq_vi, nc, NNMTXQ_VI); 10454 calculate_nqueues(&t4_nnmrxq_vi, nc, NNMRXQ_VI); 10455 #endif 10456 10457 if (t4_tmr_idx < 0 || t4_tmr_idx >= SGE_NTIMERS) 10458 t4_tmr_idx = TMR_IDX; 10459 10460 if (t4_pktc_idx < -1 || t4_pktc_idx >= SGE_NCOUNTERS) 10461 t4_pktc_idx = PKTC_IDX; 10462 10463 if (t4_qsize_txq < 128) 10464 t4_qsize_txq = 128; 10465 10466 if (t4_qsize_rxq < 128) 10467 t4_qsize_rxq = 128; 10468 while (t4_qsize_rxq & 7) 10469 t4_qsize_rxq++; 10470 10471 t4_intr_types &= INTR_MSIX | INTR_MSI | INTR_INTX; 10472 10473 /* 10474 * Number of VIs to create per-port. The first VI is the "main" regular 10475 * VI for the port. The rest are additional virtual interfaces on the 10476 * same physical port. Note that the main VI does not have native 10477 * netmap support but the extra VIs do. 10478 * 10479 * Limit the number of VIs per port to the number of available 10480 * MAC addresses per port. 10481 */ 10482 if (t4_num_vis < 1) 10483 t4_num_vis = 1; 10484 if (t4_num_vis > nitems(vi_mac_funcs)) { 10485 t4_num_vis = nitems(vi_mac_funcs); 10486 printf("cxgbe: number of VIs limited to %d\n", t4_num_vis); 10487 } 10488 10489 if (pcie_relaxed_ordering < 0 || pcie_relaxed_ordering > 2) { 10490 pcie_relaxed_ordering = 1; 10491 #if defined(__i386__) || defined(__amd64__) 10492 if (cpu_vendor_id == CPU_VENDOR_INTEL) 10493 pcie_relaxed_ordering = 0; 10494 #endif 10495 } 10496 } 10497 10498 #ifdef DDB 10499 static void 10500 t4_dump_tcb(struct adapter *sc, int tid) 10501 { 10502 uint32_t base, i, j, off, pf, reg, save, tcb_addr, win_pos; 10503 10504 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 2); 10505 save = t4_read_reg(sc, reg); 10506 base = sc->memwin[2].mw_base; 10507 10508 /* Dump TCB for the tid */ 10509 tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE); 10510 tcb_addr += tid * TCB_SIZE; 10511 10512 if (is_t4(sc)) { 10513 pf = 0; 10514 win_pos = tcb_addr & ~0xf; /* start must be 16B aligned */ 10515 } else { 10516 pf = V_PFNUM(sc->pf); 10517 win_pos = tcb_addr & ~0x7f; /* start must be 128B aligned */ 10518 } 10519 t4_write_reg(sc, reg, win_pos | pf); 10520 t4_read_reg(sc, reg); 10521 10522 off = tcb_addr - win_pos; 10523 for (i = 0; i < 4; i++) { 10524 uint32_t buf[8]; 10525 for (j = 0; j < 8; j++, off += 4) 10526 buf[j] = htonl(t4_read_reg(sc, base + off)); 10527 10528 db_printf("%08x %08x %08x %08x %08x %08x %08x %08x\n", 10529 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], 10530 buf[7]); 10531 } 10532 10533 t4_write_reg(sc, reg, save); 10534 t4_read_reg(sc, reg); 10535 } 10536 10537 static void 10538 t4_dump_devlog(struct adapter *sc) 10539 { 10540 struct devlog_params *dparams = &sc->params.devlog; 10541 struct fw_devlog_e e; 10542 int i, first, j, m, nentries, rc; 10543 uint64_t ftstamp = UINT64_MAX; 10544 10545 if (dparams->start == 0) { 10546 db_printf("devlog params not valid\n"); 10547 return; 10548 } 10549 10550 nentries = dparams->size / sizeof(struct fw_devlog_e); 10551 m = fwmtype_to_hwmtype(dparams->memtype); 10552 10553 /* Find the first entry. */ 10554 first = -1; 10555 for (i = 0; i < nentries && !db_pager_quit; i++) { 10556 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e), 10557 sizeof(e), (void *)&e); 10558 if (rc != 0) 10559 break; 10560 10561 if (e.timestamp == 0) 10562 break; 10563 10564 e.timestamp = be64toh(e.timestamp); 10565 if (e.timestamp < ftstamp) { 10566 ftstamp = e.timestamp; 10567 first = i; 10568 } 10569 } 10570 10571 if (first == -1) 10572 return; 10573 10574 i = first; 10575 do { 10576 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e), 10577 sizeof(e), (void *)&e); 10578 if (rc != 0) 10579 return; 10580 10581 if (e.timestamp == 0) 10582 return; 10583 10584 e.timestamp = be64toh(e.timestamp); 10585 e.seqno = be32toh(e.seqno); 10586 for (j = 0; j < 8; j++) 10587 e.params[j] = be32toh(e.params[j]); 10588 10589 db_printf("%10d %15ju %8s %8s ", 10590 e.seqno, e.timestamp, 10591 (e.level < nitems(devlog_level_strings) ? 10592 devlog_level_strings[e.level] : "UNKNOWN"), 10593 (e.facility < nitems(devlog_facility_strings) ? 10594 devlog_facility_strings[e.facility] : "UNKNOWN")); 10595 db_printf(e.fmt, e.params[0], e.params[1], e.params[2], 10596 e.params[3], e.params[4], e.params[5], e.params[6], 10597 e.params[7]); 10598 10599 if (++i == nentries) 10600 i = 0; 10601 } while (i != first && !db_pager_quit); 10602 } 10603 10604 static struct command_table db_t4_table = LIST_HEAD_INITIALIZER(db_t4_table); 10605 _DB_SET(_show, t4, NULL, db_show_table, 0, &db_t4_table); 10606 10607 DB_FUNC(devlog, db_show_devlog, db_t4_table, CS_OWN, NULL) 10608 { 10609 device_t dev; 10610 int t; 10611 bool valid; 10612 10613 valid = false; 10614 t = db_read_token(); 10615 if (t == tIDENT) { 10616 dev = device_lookup_by_name(db_tok_string); 10617 valid = true; 10618 } 10619 db_skip_to_eol(); 10620 if (!valid) { 10621 db_printf("usage: show t4 devlog <nexus>\n"); 10622 return; 10623 } 10624 10625 if (dev == NULL) { 10626 db_printf("device not found\n"); 10627 return; 10628 } 10629 10630 t4_dump_devlog(device_get_softc(dev)); 10631 } 10632 10633 DB_FUNC(tcb, db_show_t4tcb, db_t4_table, CS_OWN, NULL) 10634 { 10635 device_t dev; 10636 int radix, tid, t; 10637 bool valid; 10638 10639 valid = false; 10640 radix = db_radix; 10641 db_radix = 10; 10642 t = db_read_token(); 10643 if (t == tIDENT) { 10644 dev = device_lookup_by_name(db_tok_string); 10645 t = db_read_token(); 10646 if (t == tNUMBER) { 10647 tid = db_tok_number; 10648 valid = true; 10649 } 10650 } 10651 db_radix = radix; 10652 db_skip_to_eol(); 10653 if (!valid) { 10654 db_printf("usage: show t4 tcb <nexus> <tid>\n"); 10655 return; 10656 } 10657 10658 if (dev == NULL) { 10659 db_printf("device not found\n"); 10660 return; 10661 } 10662 if (tid < 0) { 10663 db_printf("invalid tid\n"); 10664 return; 10665 } 10666 10667 t4_dump_tcb(device_get_softc(dev), tid); 10668 } 10669 #endif 10670 10671 /* 10672 * Borrowed from cesa_prep_aes_key(). 10673 * 10674 * NB: The crypto engine wants the words in the decryption key in reverse 10675 * order. 10676 */ 10677 void 10678 t4_aes_getdeckey(void *dec_key, const void *enc_key, unsigned int kbits) 10679 { 10680 uint32_t ek[4 * (RIJNDAEL_MAXNR + 1)]; 10681 uint32_t *dkey; 10682 int i; 10683 10684 rijndaelKeySetupEnc(ek, enc_key, kbits); 10685 dkey = dec_key; 10686 dkey += (kbits / 8) / 4; 10687 10688 switch (kbits) { 10689 case 128: 10690 for (i = 0; i < 4; i++) 10691 *--dkey = htobe32(ek[4 * 10 + i]); 10692 break; 10693 case 192: 10694 for (i = 0; i < 2; i++) 10695 *--dkey = htobe32(ek[4 * 11 + 2 + i]); 10696 for (i = 0; i < 4; i++) 10697 *--dkey = htobe32(ek[4 * 12 + i]); 10698 break; 10699 case 256: 10700 for (i = 0; i < 4; i++) 10701 *--dkey = htobe32(ek[4 * 13 + i]); 10702 for (i = 0; i < 4; i++) 10703 *--dkey = htobe32(ek[4 * 14 + i]); 10704 break; 10705 } 10706 MPASS(dkey == dec_key); 10707 } 10708 10709 static struct sx mlu; /* mod load unload */ 10710 SX_SYSINIT(cxgbe_mlu, &mlu, "cxgbe mod load/unload"); 10711 10712 static int 10713 mod_event(module_t mod, int cmd, void *arg) 10714 { 10715 int rc = 0; 10716 static int loaded = 0; 10717 10718 switch (cmd) { 10719 case MOD_LOAD: 10720 sx_xlock(&mlu); 10721 if (loaded++ == 0) { 10722 t4_sge_modload(); 10723 t4_register_shared_cpl_handler(CPL_SET_TCB_RPL, 10724 t4_filter_rpl, CPL_COOKIE_FILTER); 10725 t4_register_shared_cpl_handler(CPL_L2T_WRITE_RPL, 10726 do_l2t_write_rpl, CPL_COOKIE_FILTER); 10727 t4_register_shared_cpl_handler(CPL_ACT_OPEN_RPL, 10728 t4_hashfilter_ao_rpl, CPL_COOKIE_HASHFILTER); 10729 t4_register_shared_cpl_handler(CPL_SET_TCB_RPL, 10730 t4_hashfilter_tcb_rpl, CPL_COOKIE_HASHFILTER); 10731 t4_register_shared_cpl_handler(CPL_ABORT_RPL_RSS, 10732 t4_del_hashfilter_rpl, CPL_COOKIE_HASHFILTER); 10733 t4_register_cpl_handler(CPL_TRACE_PKT, t4_trace_pkt); 10734 t4_register_cpl_handler(CPL_T5_TRACE_PKT, t5_trace_pkt); 10735 t4_register_cpl_handler(CPL_SMT_WRITE_RPL, 10736 do_smt_write_rpl); 10737 sx_init(&t4_list_lock, "T4/T5 adapters"); 10738 SLIST_INIT(&t4_list); 10739 callout_init(&fatal_callout, 1); 10740 #ifdef TCP_OFFLOAD 10741 sx_init(&t4_uld_list_lock, "T4/T5 ULDs"); 10742 SLIST_INIT(&t4_uld_list); 10743 #endif 10744 #ifdef INET6 10745 t4_clip_modload(); 10746 #endif 10747 t4_tracer_modload(); 10748 tweak_tunables(); 10749 } 10750 sx_xunlock(&mlu); 10751 break; 10752 10753 case MOD_UNLOAD: 10754 sx_xlock(&mlu); 10755 if (--loaded == 0) { 10756 int tries; 10757 10758 sx_slock(&t4_list_lock); 10759 if (!SLIST_EMPTY(&t4_list)) { 10760 rc = EBUSY; 10761 sx_sunlock(&t4_list_lock); 10762 goto done_unload; 10763 } 10764 #ifdef TCP_OFFLOAD 10765 sx_slock(&t4_uld_list_lock); 10766 if (!SLIST_EMPTY(&t4_uld_list)) { 10767 rc = EBUSY; 10768 sx_sunlock(&t4_uld_list_lock); 10769 sx_sunlock(&t4_list_lock); 10770 goto done_unload; 10771 } 10772 #endif 10773 tries = 0; 10774 while (tries++ < 5 && t4_sge_extfree_refs() != 0) { 10775 uprintf("%ju clusters with custom free routine " 10776 "still is use.\n", t4_sge_extfree_refs()); 10777 pause("t4unload", 2 * hz); 10778 } 10779 #ifdef TCP_OFFLOAD 10780 sx_sunlock(&t4_uld_list_lock); 10781 #endif 10782 sx_sunlock(&t4_list_lock); 10783 10784 if (t4_sge_extfree_refs() == 0) { 10785 t4_tracer_modunload(); 10786 #ifdef INET6 10787 t4_clip_modunload(); 10788 #endif 10789 #ifdef TCP_OFFLOAD 10790 sx_destroy(&t4_uld_list_lock); 10791 #endif 10792 sx_destroy(&t4_list_lock); 10793 t4_sge_modunload(); 10794 loaded = 0; 10795 } else { 10796 rc = EBUSY; 10797 loaded++; /* undo earlier decrement */ 10798 } 10799 } 10800 done_unload: 10801 sx_xunlock(&mlu); 10802 break; 10803 } 10804 10805 return (rc); 10806 } 10807 10808 static devclass_t t4_devclass, t5_devclass, t6_devclass; 10809 static devclass_t cxgbe_devclass, cxl_devclass, cc_devclass; 10810 static devclass_t vcxgbe_devclass, vcxl_devclass, vcc_devclass; 10811 10812 DRIVER_MODULE(t4nex, pci, t4_driver, t4_devclass, mod_event, 0); 10813 MODULE_VERSION(t4nex, 1); 10814 MODULE_DEPEND(t4nex, firmware, 1, 1, 1); 10815 #ifdef DEV_NETMAP 10816 MODULE_DEPEND(t4nex, netmap, 1, 1, 1); 10817 #endif /* DEV_NETMAP */ 10818 10819 DRIVER_MODULE(t5nex, pci, t5_driver, t5_devclass, mod_event, 0); 10820 MODULE_VERSION(t5nex, 1); 10821 MODULE_DEPEND(t5nex, firmware, 1, 1, 1); 10822 #ifdef DEV_NETMAP 10823 MODULE_DEPEND(t5nex, netmap, 1, 1, 1); 10824 #endif /* DEV_NETMAP */ 10825 10826 DRIVER_MODULE(t6nex, pci, t6_driver, t6_devclass, mod_event, 0); 10827 MODULE_VERSION(t6nex, 1); 10828 MODULE_DEPEND(t6nex, firmware, 1, 1, 1); 10829 #ifdef DEV_NETMAP 10830 MODULE_DEPEND(t6nex, netmap, 1, 1, 1); 10831 #endif /* DEV_NETMAP */ 10832 10833 DRIVER_MODULE(cxgbe, t4nex, cxgbe_driver, cxgbe_devclass, 0, 0); 10834 MODULE_VERSION(cxgbe, 1); 10835 10836 DRIVER_MODULE(cxl, t5nex, cxl_driver, cxl_devclass, 0, 0); 10837 MODULE_VERSION(cxl, 1); 10838 10839 DRIVER_MODULE(cc, t6nex, cc_driver, cc_devclass, 0, 0); 10840 MODULE_VERSION(cc, 1); 10841 10842 DRIVER_MODULE(vcxgbe, cxgbe, vcxgbe_driver, vcxgbe_devclass, 0, 0); 10843 MODULE_VERSION(vcxgbe, 1); 10844 10845 DRIVER_MODULE(vcxl, cxl, vcxl_driver, vcxl_devclass, 0, 0); 10846 MODULE_VERSION(vcxl, 1); 10847 10848 DRIVER_MODULE(vcc, cc, vcc_driver, vcc_devclass, 0, 0); 10849 MODULE_VERSION(vcc, 1); 10850